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MB super-sections; legacy versions also defined a 1 kB tiny page. The ARM uses a two-level pagetable if using 4 kB and 64 kB pages, or just a one-level pagetable |
for 1 MB sections and 16 MB sections. TLB updates are performed automatically by page-table walking hardware. The IBM System/370 has had an MMU since the early 1970s; it was |
initially known as a DAT (Dynamic Address Translation) box. It has the unusual feature of storing accessed and dirty bits outside of the page table. They refer to physical memory |
rather than virtual memory. They are accessed by special-purpose instructions. This reduces overhead for the OS, which would otherwise need to propagate accessed and dirty bits from the page tables |
to a more physically oriented data structure. This makes OS-level virtualization easier.[clarification needed] These features have been inherited by succeeding mainframe architectures, up to the current z/Architecture. The DEC Alpha |
processor divides memory into 8 kB pages. After a TLB miss, low-level firmware machine code (here called PALcode) walks a 3-level tree-structured page table. Addresses are broken down as follows: |
21 bits unused, 10 bits to index the root level of the tree, 10 bits to index the middle level of the tree, 10 bits to index the leaf level |
of the tree, and 13 bits that pass through to the physical address without modification. Full read/write/execute permission bits are supported. The MIPS architecture supports 1 to 64 entries in |
the TLB. The number of TLB entries is configurable at CPU configuration before synthesis. TLB entries are dual. Each TLB entry maps a virtual page number (VPN2) to either one |
of two page frame numbers (PFN0 or PFN1), depending on the least significant bit of the virtual address that is not part of the page mask. This bit and the |
page mask bits, are not stored in the VPN2. Each TLB entry has its own page size, which can be any value from 1 kB to 256 MB in multiples |
of 4. Each PFN in a TLB entry has a caching attribute, a dirty and a valid status bit. A VPN2 has a global status bit and an OS assigned |
ID which participates in the virtual address TLB entry match, if the global status bit is set to 0. A PFN stores the physical address without the page mask bits. |
A TLB Refill exception is generated when there are no entries in the TLB that match the mapped virtual address. A TLB Invalid exception is generated when there is a |
match but the entry is marked invalid. A TLB Modified exception is generated when there is a match but the dirty status is not set. If a TLB exception occurs |
when processing a TLB exception, a double fault TLB exception, it is dispatched to its own exception handler. MIPS32 and MIPS32r2 support 32 bits of virtual address space and up |
to 36 bits of physical address space. MIPS64 supports up to 64 bits of virtual address space and up to 59 bits of physical address space. The original Sun 1 |
was a single-board computer built around the Motorola 68000 microprocessor and introduced in 1982. It included the original Sun 1 Memory Management Unit, that provided address translation, memory protection, memory |
sharing and memory allocation for multiple processes running on the CPU. All access of the CPU to private on-board RAM, external Multibus memory, on-board I/O and the Multibus I/O ran |
through the MMU where they were translated and protected in uniform fashion. The MMU was implemented in hardware on the CPU board. The MMU consisted of a context register, a |
segment map and a page map. Virtual addresses from the CPU were translated into intermediate addresses by the segment map, which in turn were translated into physical addresses by the |
page map. The page size was 2 kB and the segment size was 32 kB which gave 16 pages per segment. Up to 16 contexts could be mapped concurrently. The |
maximum logical address space for a context was 1024 pages or 2 MB. The maximum physical address that could be mapped simultaneously was also 2 MB. The context register was |
important in a multitasking operating system because it allowed the CPU to switch between processes without reloading all the translation state information. The 4-bit context register could switch between 16 |
sections of the segment map under supervisor control which allowed 16 contexts to be mapped concurrently. Each context had its own virtual address space. Sharing of virtual address space and |
inter-context communications could be provided by writing the same values in to the segment or page maps of different contexts. Additional contexts could be handled by treating the segment map |
as a context cache and replacing out-of-date contexts on a least-recently-used basis. The context register made no distinction between user and supervisor states; interrupts and traps did not switch contexts |
which required that all valid interrupt vectors always be mapped in page 0 of context, as well as the valid Supervisor Stack. In PowerPC G1, G2, G3, and G4, pages |
are normally 4 kB. After a TLB miss, the standard PowerPC MMU begins two simultaneous lookups. One lookup attempts to match the address with one of 4 or 8 Data |
Block Address Translation (DBAT) registers, or 4 or 8 Instruction Block Address Translation registers (IBAT) as appropriate. The BAT registers can map linear chunks of memory as large as 256 |
MB, and are normally used by an OS to map large portions of the address space for the OS kernel's own use. If the BAT lookup succeeds, the other lookup |
is halted and ignored. The other lookup, not directly supported by all processors in this family, is via a so-called "inverted page table" which acts as a hashed off-chip extension |
of the TLB. First, the top 4 bits of the address are used to select one of 16 segment registers. 24 bits from the segment register replace those 4 bits, |
producing a 52-bit address. The use of segment registers allows multiple processes to share the same hash table. The 52-bit address is hashed, then used as an index into the |
off-chip table. There, a group of 8 page table entries is scanned for one that matches. If none match due to excessive hash collisions, the processor tries again with a |
slightly different hash function. If this too fails, the CPU traps into the OS (with MMU disabled) so that the problem may be resolved. The OS needs to discard an |
entry from the hash table to make space for a new entry. The OS may generate the new entry from a more-normal tree-like page table or from per-mapping data structures |
which are likely to be slower and more space-efficient. Support for no-execute control is in the segment registers, leading to 256 MB granularity. A major problem with this design is |
poor cache locality caused by the hash function. Tree-based designs avoid this by placing the page table entries for adjacent pages in adjacent locations. An operating system running on the |
PowerPC may minimize the size of the hash table to reduce this problem. It is also somewhat slow to remove the page table entries of a process; the OS may |
avoid reusing segment values to delay facing this or it may elect to suffer the waste of memory associated with per-process hash tables. G1 chips do not search for page |
table entries, but they do generate the hash with the expectation that an OS will search the standard hash table via software. The OS can write to the TLB. G2, |
G3, and early G4 chips use hardware to search the hash table. The latest chips allow the OS to choose either method. On chips that make this optional or do |
not support it at all, the OS may choose to use a tree-based page table exclusively. The x86 architecture has evolved over a very long time while maintaining full software |
compatibility even for OS code. Thus the MMU is extremely complex, with many different possible operating modes. Normal operation of the traditional 80386 CPU and its successors (IA-32) is described |
here. The CPU primarily divides memory into 4 kB pages. Segment registers, fundamental to the older 8088 and 80286 MMU designs, are not used in modern OSes with one major |
exception: access to thread-specific data for applications or CPU-specific data for OS kernels, which is done with explicit use of the FS and GS segment registers. All memory access involves |
a segment register, chosen according to the code being executed. The segment register acts as an index into a table, which provides an offset to be added to the virtual |
address. Except when using FS or GS as described above, the OS ensures that the offset will be zero. After the offset is added, the address is masked to be |
no larger than 32 bits. The result may be looked up via a tree-structured page table, with the bits of the address being split as follows: 10 bits for the |
branch of the tree, 10 bits for the leaves of the branch, and the 12 lowest bits being directly copied to the result. Some operating systems, such as OpenBSD with |
its W^X feature, and Linux with the Exec Shield or PaX patches, may also limit the length of the code segment, as specified by the CS register, to disallow execution |
of code in modifiable regions of the address space. Minor revisions of the MMU introduced with the Pentium have allowed very large 4 MB pages by skipping the bottom level |
of the tree. Minor revisions of the MMU introduced with the Pentium Pro introduced the Physical Address Extension (PAE) feature, enabling 36-bit physical addresses via three-level page tables (with 9+9+2 |
bits for the three levels, and the 12 lowest bits being directly copied to the result; large pages become only 2 MB in size). In addition, the Page Attribute Table |
allowed specification of cacheability by looking up a few high bits in a small on-CPU table. No-execute support was originally only provided on a per-segment basis, making it very awkward |
to use. More recent x86 chips provide a per-page no-execute bit in the PAE mode. The W^X, Exec Shield, and PaX mechanisms described above emulate per-page non-execute support on machines |
x86 processors lacking the NX bit by setting the length of the code segment, with a performance loss and a reduction in the available address space. x86-64 is a 64-bit |
extension of x86 that almost entirely removes segmentation in favor of the flat memory model used by almost all operating systems for the 386 or newer processors. In long mode, |
all segment offsets are ignored, except for the FS and GS segments. When used with 4 kB pages, the page table tree has four levels instead of three. The virtual |
addresses are divided up as follows: 16 bits unused, 9 bits each for 4 tree levels (total: 36 bits), and the 12 lowest bits directly copied to the result. With |
2 MB pages there are only three levels of page table, for a total of 27 bits used in paging and 21 bits of offset. Some newer CPUs also support |
a 1 GB page with two levels of paging and 30 bits of offset. CPUID can be used to determine if 1 GB pages are supported. In all three cases, |
the 16 highest bits are required to be equal to the 48th bit, or in other words, the low 48 bits are sign extended to the higher bits. This is |
done to allow a future expansion of the addressable range, without compromising backwards compatibility. In all levels of the page table, the page table entry includes a no-execute bit. Tanenbaum |
et al., recently stated that the B5000 (and descendant systems) have no MMU. To understand the functionality provided by an MMU, it is instructive to study a counter example of |
a system that achieves this functionality by other means. The B5000 was the first commercial system to support virtual memory after the Atlas. It provides the two functions of an |
MMU in different ways. Firstly, the mapping of virtual memory addresses. Instead of needing an MMU, the MCP systems are descriptor based. Each allocated memory block is given a master |
descriptor with the properties of the block, i.e., the size, address, and whether present in memory. When a request is made to access the block for reading or writing, the |
hardware checks its presence via the presence bit (pbit) in the descriptor. A pbit of 1 indicates the presence of the block. In this case the block can be accessed |
via the physical address in the descriptor. If the pbit is zero, an interrupt is generated for the MCP (operating system) to make the block present. If the address field |
is zero, this is the first access to this block and it is allocated (an init pbit). If the address field is non-zero, it is a disk address of the |
block, which has previously been rolled out, so the block is fetched from disk and the pbit is set to 1 and the physical memory address updated to point to |
the block in memory (another pbit). This makes descriptors equivalent to a page-table entry in an MMU system. System performance can be monitored through the number of pbits. Init pbits |
indicate initial allocations, but a high level of other pbits indicate that the system may be thrashing. Note that all memory allocation is therefore completely automatic (one of the features |
of modern systems) and there is no way to allocate blocks other than this mechanism. There are no such calls as malloc or dealloc, since memory blocks are also automatically |
discarded. The scheme is also lazy, since a block will not be allocated until it is actually referenced. When memory is near full, the MCP examines the working set, trying |
compaction (since the system is segmented, not paged), deallocating read-only segments (such as code-segments which can be restored from their original copy), and as a last resort, rolling dirty data |
segments out to disk. Secondly, protection. Since all accesses are via the descriptor the hardware can check all accesses are within bounds, and in the case of a write that |
the process has write permission. The MCP system is inherently secure and thus has no need of an MMU to provide this level of memory protection. Descriptors are read only |
to user processes and may only be updated by the system (hardware or MCP). (Descriptors have a tag of 5 and odd-tagged words are read only – code words have |
a tag of 3.) Blocks can be shared between processes via copy descriptors in the process stack – thus some processes may have write permission, whereas others not. A code |
segment is read only, thus reentrant and shared between processes. Copy descriptors contain a 20-bit address field giving index of the master descriptor in the master descriptor array. This also |
implements a very efficient and secure IPC mechanism. Blocks can easily be relocated since only the master descriptor needs update when a block's status changes. The only other aspect is |
performance – do MMU- or non-MMU-based systems provide better performance? MCP systems may be implemented on top of standard hardware that does have an MMU (e.g., a standard PC). Even |
if the system implementation uses the MMU in some way, this will not be at all visible at the MCP level. Here you can share your comments or contribute with |
SHORT TALK BULLETIN - Vol.XI May, 1933 No.5 "Thou shalt not remove thy neighbor's landmark, which they of old have set in thine inheritance, which thou shalt inherit in the land the Lord thy God hath given thee (Deuteronomy XIX:14). The Masons "of old time set thine inheritance" (Masonry) certain |
fundamental principles which are named as "Landmarks" as early as the Constitutions of 1723. Men have quarreled about the stone markers set up as boundaries for land ever since sections of the earth were claimed as property; in like manner have Masons differed about what are and what are not |
Landmarks of the Order. In this country particularly, with forty-nine Jurisdictions, each sovereign within its own territory, arguments about Landmarks are never ending. This Bulletin attempts not to settle any of these numerous controversies, but only to bring before the average Lodge Member some of the reasons why hi... |
Masonic Landmarks may differ from those his own Grand Lodge may have set up for him to follow. In 1858 Albert Gallatin Mackey, the great Masonic jurist and authority, listed twenty-five fundamental principles as the true Landmarks of Freemasonry. Although critical scholarship has since riddled the list as to accuracy, |
Mackey's ideas of what constitute the essential qualities of a Landmark - antiquity, universality and irrevocability - are still respected. This definition excludes from the classification of Landmarks any principle which is any two of these but no the third, It is by his own standards that many critics have |
measured Mackey's Landmarks and found them wanting. As an example of what is meant; it is "ancient," in the sense that it was recognized in the "Constitutions" of the Grand Lodge in 1723, that a Grand Master appoints own Deputy Grand Master. But the practice is by no means universal. |
Lodges are now universally governed by Grand Lodges, but the practice has antiquity of only two hundred and sixteen years. According to Mackey's dicta, neither the manner of creating a Deputy Grand Master not the fundamental governing body of the Craft can be considered as Landmarks. A few principles are |
so universally recognized that they are freely admitted to be essentials, even in Jurisdictions which have no pronouncements as to the Landmarks. Belief in a Supreme Being, the Volume of sacred Law as a necessary part of the furniture of the Lodge, that a Masons must be a man are |
essentials all over the world, though not necessarily listed in all Jurisdictions. On the validity of certain principles all authorities agree, but differ as to their antiquity, universality and irrevocability. A substantial minority of American Grand Jurisdictions have Officially adopted Mackey's twenty-five Ancient L... |
compilations, use other Old Charges, or decline to specify what are and what are not the Landmarks of the Craft. The right and power of any Grand Lodge to determine for itself just what is and what is not "law" in its Jurisdiction is unquestioned. Therefore, when a Jurisdiction sets |
forth any list of Landmarks in its Code, they have all the force of Ancient Landmarks in that Jurisdiction, whether they are actually so or not. "Actually so" refers to inherent nature; that which cannot be altered by law, no matter what the lawmaking authority. The National Legislature has the |
undoubted "right" to enact a law that unsupported objects must fall. "Per contra," it then has the right to repeal the law of gravity, and forbid things to fall when no longer supported. But it has not the "power" to enforce, change or suspend the law of gravity! A Grand |
Lodge which says "Thus and such is an Ancient Landmark "in that Jurisdiction," give that pronouncement the full force and effect of an Ancient Landmark "in that Jurisdiction, but its edict does not "actually" make it such. One Jurisdiction follows Lockwood's list of nineteen landmarks, of which number 8 reads: |
"That every Lodge has an inherent right to be represented in Grand Lodge by its first three officers, or their proxies." This is good Masonic law in most Jurisdictions, but not all; the Mason from this Jurisdiction (Washington, D.C.) who moves to New York or Texas and there affiliates finds |
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