max_stars_repo_path stringlengths 4 261 | max_stars_repo_name stringlengths 6 106 | max_stars_count int64 0 38.8k | id stringlengths 1 6 | text stringlengths 7 1.05M |
|---|---|---|---|---|
electrum/src/main/resources/models/book/chapter2/addressBook1f.als | haslab/Electrum | 29 | 3521 | <reponame>haslab/Electrum
module tour/addressBook1f ----- Page 12
sig Name, Addr { }
sig Book {
addr: Name -> lone Addr
}
pred add [b, b1: Book, n: Name, a: Addr] {
b1.addr = b.addr + n->a
}
pred showAdd [b, b1: Book, n: Name, a: Addr] {
add [b, b1, n, a]
#Name.(b1.addr) > 1
}
// This command generates an instance similar to Fig 2.5
run showAdd for 3 but 2 Book
|
stm32f4/stm32f411xx/svd/stm32_svd-i2c.ads | ekoeppen/STM32_Generic_Ada_Drivers | 1 | 17176 | -- This spec has been automatically generated from STM32F411xx.svd
pragma Restrictions (No_Elaboration_Code);
pragma Ada_2012;
pragma Style_Checks (Off);
with System;
package STM32_SVD.I2C is
pragma Preelaborate;
---------------
-- Registers --
---------------
subtype CR1_PE_Field is STM32_SVD.Bit;
subtype CR1_SMBUS_Field is STM32_SVD.Bit;
subtype CR1_SMBTYPE_Field is STM32_SVD.Bit;
subtype CR1_ENARP_Field is STM32_SVD.Bit;
subtype CR1_ENPEC_Field is STM32_SVD.Bit;
subtype CR1_ENGC_Field is STM32_SVD.Bit;
subtype CR1_NOSTRETCH_Field is STM32_SVD.Bit;
subtype CR1_START_Field is STM32_SVD.Bit;
subtype CR1_STOP_Field is STM32_SVD.Bit;
subtype CR1_ACK_Field is STM32_SVD.Bit;
subtype CR1_POS_Field is STM32_SVD.Bit;
subtype CR1_PEC_Field is STM32_SVD.Bit;
subtype CR1_ALERT_Field is STM32_SVD.Bit;
subtype CR1_SWRST_Field is STM32_SVD.Bit;
-- Control register 1
type CR1_Register is record
-- Peripheral enable
PE : CR1_PE_Field := 16#0#;
-- SMBus mode
SMBUS : CR1_SMBUS_Field := 16#0#;
-- unspecified
Reserved_2_2 : STM32_SVD.Bit := 16#0#;
-- SMBus type
SMBTYPE : CR1_SMBTYPE_Field := 16#0#;
-- ARP enable
ENARP : CR1_ENARP_Field := 16#0#;
-- PEC enable
ENPEC : CR1_ENPEC_Field := 16#0#;
-- General call enable
ENGC : CR1_ENGC_Field := 16#0#;
-- Clock stretching disable (Slave mode)
NOSTRETCH : CR1_NOSTRETCH_Field := 16#0#;
-- Start generation
START : CR1_START_Field := 16#0#;
-- Stop generation
STOP : CR1_STOP_Field := 16#0#;
-- Acknowledge enable
ACK : CR1_ACK_Field := 16#0#;
-- Acknowledge/PEC Position (for data reception)
POS : CR1_POS_Field := 16#0#;
-- Packet error checking
PEC : CR1_PEC_Field := 16#0#;
-- SMBus alert
ALERT : CR1_ALERT_Field := 16#0#;
-- unspecified
Reserved_14_14 : STM32_SVD.Bit := 16#0#;
-- Software reset
SWRST : CR1_SWRST_Field := 16#0#;
-- unspecified
Reserved_16_31 : STM32_SVD.UInt16 := 16#0#;
end record
with Volatile_Full_Access, Size => 32,
Bit_Order => System.Low_Order_First;
for CR1_Register use record
PE at 0 range 0 .. 0;
SMBUS at 0 range 1 .. 1;
Reserved_2_2 at 0 range 2 .. 2;
SMBTYPE at 0 range 3 .. 3;
ENARP at 0 range 4 .. 4;
ENPEC at 0 range 5 .. 5;
ENGC at 0 range 6 .. 6;
NOSTRETCH at 0 range 7 .. 7;
START at 0 range 8 .. 8;
STOP at 0 range 9 .. 9;
ACK at 0 range 10 .. 10;
POS at 0 range 11 .. 11;
PEC at 0 range 12 .. 12;
ALERT at 0 range 13 .. 13;
Reserved_14_14 at 0 range 14 .. 14;
SWRST at 0 range 15 .. 15;
Reserved_16_31 at 0 range 16 .. 31;
end record;
subtype CR2_FREQ_Field is STM32_SVD.UInt6;
subtype CR2_ITERREN_Field is STM32_SVD.Bit;
subtype CR2_ITEVTEN_Field is STM32_SVD.Bit;
subtype CR2_ITBUFEN_Field is STM32_SVD.Bit;
subtype CR2_DMAEN_Field is STM32_SVD.Bit;
subtype CR2_LAST_Field is STM32_SVD.Bit;
-- Control register 2
type CR2_Register is record
-- Peripheral clock frequency
FREQ : CR2_FREQ_Field := 16#0#;
-- unspecified
Reserved_6_7 : STM32_SVD.UInt2 := 16#0#;
-- Error interrupt enable
ITERREN : CR2_ITERREN_Field := 16#0#;
-- Event interrupt enable
ITEVTEN : CR2_ITEVTEN_Field := 16#0#;
-- Buffer interrupt enable
ITBUFEN : CR2_ITBUFEN_Field := 16#0#;
-- DMA requests enable
DMAEN : CR2_DMAEN_Field := 16#0#;
-- DMA last transfer
LAST : CR2_LAST_Field := 16#0#;
-- unspecified
Reserved_13_31 : STM32_SVD.UInt19 := 16#0#;
end record
with Volatile_Full_Access, Size => 32,
Bit_Order => System.Low_Order_First;
for CR2_Register use record
FREQ at 0 range 0 .. 5;
Reserved_6_7 at 0 range 6 .. 7;
ITERREN at 0 range 8 .. 8;
ITEVTEN at 0 range 9 .. 9;
ITBUFEN at 0 range 10 .. 10;
DMAEN at 0 range 11 .. 11;
LAST at 0 range 12 .. 12;
Reserved_13_31 at 0 range 13 .. 31;
end record;
subtype OAR1_ADD0_Field is STM32_SVD.Bit;
subtype OAR1_ADD7_Field is STM32_SVD.UInt7;
subtype OAR1_ADD10_Field is STM32_SVD.UInt2;
subtype OAR1_ADDMODE_Field is STM32_SVD.Bit;
-- Own address register 1
type OAR1_Register is record
-- Interface address
ADD0 : OAR1_ADD0_Field := 16#0#;
-- Interface address
ADD7 : OAR1_ADD7_Field := 16#0#;
-- Interface address
ADD10 : OAR1_ADD10_Field := 16#0#;
-- unspecified
Reserved_10_14 : STM32_SVD.UInt5 := 16#0#;
-- Addressing mode (slave mode)
ADDMODE : OAR1_ADDMODE_Field := 16#0#;
-- unspecified
Reserved_16_31 : STM32_SVD.UInt16 := 16#0#;
end record
with Volatile_Full_Access, Size => 32,
Bit_Order => System.Low_Order_First;
for OAR1_Register use record
ADD0 at 0 range 0 .. 0;
ADD7 at 0 range 1 .. 7;
ADD10 at 0 range 8 .. 9;
Reserved_10_14 at 0 range 10 .. 14;
ADDMODE at 0 range 15 .. 15;
Reserved_16_31 at 0 range 16 .. 31;
end record;
subtype OAR2_ENDUAL_Field is STM32_SVD.Bit;
subtype OAR2_ADD2_Field is STM32_SVD.UInt7;
-- Own address register 2
type OAR2_Register is record
-- Dual addressing mode enable
ENDUAL : OAR2_ENDUAL_Field := 16#0#;
-- Interface address
ADD2 : OAR2_ADD2_Field := 16#0#;
-- unspecified
Reserved_8_31 : STM32_SVD.UInt24 := 16#0#;
end record
with Volatile_Full_Access, Size => 32,
Bit_Order => System.Low_Order_First;
for OAR2_Register use record
ENDUAL at 0 range 0 .. 0;
ADD2 at 0 range 1 .. 7;
Reserved_8_31 at 0 range 8 .. 31;
end record;
subtype DR_DR_Field is STM32_SVD.Byte;
-- Data register
type DR_Register is record
-- 8-bit data register
DR : DR_DR_Field := 16#0#;
-- unspecified
Reserved_8_31 : STM32_SVD.UInt24 := 16#0#;
end record
with Volatile_Full_Access, Size => 32,
Bit_Order => System.Low_Order_First;
for DR_Register use record
DR at 0 range 0 .. 7;
Reserved_8_31 at 0 range 8 .. 31;
end record;
subtype SR1_SB_Field is STM32_SVD.Bit;
subtype SR1_ADDR_Field is STM32_SVD.Bit;
subtype SR1_BTF_Field is STM32_SVD.Bit;
subtype SR1_ADD10_Field is STM32_SVD.Bit;
subtype SR1_STOPF_Field is STM32_SVD.Bit;
subtype SR1_RxNE_Field is STM32_SVD.Bit;
subtype SR1_TxE_Field is STM32_SVD.Bit;
subtype SR1_BERR_Field is STM32_SVD.Bit;
subtype SR1_ARLO_Field is STM32_SVD.Bit;
subtype SR1_AF_Field is STM32_SVD.Bit;
subtype SR1_OVR_Field is STM32_SVD.Bit;
subtype SR1_PECERR_Field is STM32_SVD.Bit;
subtype SR1_TIMEOUT_Field is STM32_SVD.Bit;
subtype SR1_SMBALERT_Field is STM32_SVD.Bit;
-- Status register 1
type SR1_Register is record
-- Read-only. Start bit (Master mode)
SB : SR1_SB_Field := 16#0#;
-- Read-only. Address sent (master mode)/matched (slave mode)
ADDR : SR1_ADDR_Field := 16#0#;
-- Read-only. Byte transfer finished
BTF : SR1_BTF_Field := 16#0#;
-- Read-only. 10-bit header sent (Master mode)
ADD10 : SR1_ADD10_Field := 16#0#;
-- Read-only. Stop detection (slave mode)
STOPF : SR1_STOPF_Field := 16#0#;
-- unspecified
Reserved_5_5 : STM32_SVD.Bit := 16#0#;
-- Read-only. Data register not empty (receivers)
RxNE : SR1_RxNE_Field := 16#0#;
-- Read-only. Data register empty (transmitters)
TxE : SR1_TxE_Field := 16#0#;
-- Bus error
BERR : SR1_BERR_Field := 16#0#;
-- Arbitration lost (master mode)
ARLO : SR1_ARLO_Field := 16#0#;
-- Acknowledge failure
AF : SR1_AF_Field := 16#0#;
-- Overrun/Underrun
OVR : SR1_OVR_Field := 16#0#;
-- PEC Error in reception
PECERR : SR1_PECERR_Field := 16#0#;
-- unspecified
Reserved_13_13 : STM32_SVD.Bit := 16#0#;
-- Timeout or Tlow error
TIMEOUT : SR1_TIMEOUT_Field := 16#0#;
-- SMBus alert
SMBALERT : SR1_SMBALERT_Field := 16#0#;
-- unspecified
Reserved_16_31 : STM32_SVD.UInt16 := 16#0#;
end record
with Volatile_Full_Access, Size => 32,
Bit_Order => System.Low_Order_First;
for SR1_Register use record
SB at 0 range 0 .. 0;
ADDR at 0 range 1 .. 1;
BTF at 0 range 2 .. 2;
ADD10 at 0 range 3 .. 3;
STOPF at 0 range 4 .. 4;
Reserved_5_5 at 0 range 5 .. 5;
RxNE at 0 range 6 .. 6;
TxE at 0 range 7 .. 7;
BERR at 0 range 8 .. 8;
ARLO at 0 range 9 .. 9;
AF at 0 range 10 .. 10;
OVR at 0 range 11 .. 11;
PECERR at 0 range 12 .. 12;
Reserved_13_13 at 0 range 13 .. 13;
TIMEOUT at 0 range 14 .. 14;
SMBALERT at 0 range 15 .. 15;
Reserved_16_31 at 0 range 16 .. 31;
end record;
subtype SR2_MSL_Field is STM32_SVD.Bit;
subtype SR2_BUSY_Field is STM32_SVD.Bit;
subtype SR2_TRA_Field is STM32_SVD.Bit;
subtype SR2_GENCALL_Field is STM32_SVD.Bit;
subtype SR2_SMBDEFAULT_Field is STM32_SVD.Bit;
subtype SR2_SMBHOST_Field is STM32_SVD.Bit;
subtype SR2_DUALF_Field is STM32_SVD.Bit;
subtype SR2_PEC_Field is STM32_SVD.Byte;
-- Status register 2
type SR2_Register is record
-- Read-only. Master/slave
MSL : SR2_MSL_Field;
-- Read-only. Bus busy
BUSY : SR2_BUSY_Field;
-- Read-only. Transmitter/receiver
TRA : SR2_TRA_Field;
-- unspecified
Reserved_3_3 : STM32_SVD.Bit;
-- Read-only. General call address (Slave mode)
GENCALL : SR2_GENCALL_Field;
-- Read-only. SMBus device default address (Slave mode)
SMBDEFAULT : SR2_SMBDEFAULT_Field;
-- Read-only. SMBus host header (Slave mode)
SMBHOST : SR2_SMBHOST_Field;
-- Read-only. Dual flag (Slave mode)
DUALF : SR2_DUALF_Field;
-- Read-only. acket error checking register
PEC : SR2_PEC_Field;
-- unspecified
Reserved_16_31 : STM32_SVD.UInt16;
end record
with Volatile_Full_Access, Size => 32,
Bit_Order => System.Low_Order_First;
for SR2_Register use record
MSL at 0 range 0 .. 0;
BUSY at 0 range 1 .. 1;
TRA at 0 range 2 .. 2;
Reserved_3_3 at 0 range 3 .. 3;
GENCALL at 0 range 4 .. 4;
SMBDEFAULT at 0 range 5 .. 5;
SMBHOST at 0 range 6 .. 6;
DUALF at 0 range 7 .. 7;
PEC at 0 range 8 .. 15;
Reserved_16_31 at 0 range 16 .. 31;
end record;
subtype CCR_CCR_Field is STM32_SVD.UInt12;
subtype CCR_DUTY_Field is STM32_SVD.Bit;
subtype CCR_F_S_Field is STM32_SVD.Bit;
-- Clock control register
type CCR_Register is record
-- Clock control register in Fast/Standard mode (Master mode)
CCR : CCR_CCR_Field := 16#0#;
-- unspecified
Reserved_12_13 : STM32_SVD.UInt2 := 16#0#;
-- Fast mode duty cycle
DUTY : CCR_DUTY_Field := 16#0#;
-- I2C master mode selection
F_S : CCR_F_S_Field := 16#0#;
-- unspecified
Reserved_16_31 : STM32_SVD.UInt16 := 16#0#;
end record
with Volatile_Full_Access, Size => 32,
Bit_Order => System.Low_Order_First;
for CCR_Register use record
CCR at 0 range 0 .. 11;
Reserved_12_13 at 0 range 12 .. 13;
DUTY at 0 range 14 .. 14;
F_S at 0 range 15 .. 15;
Reserved_16_31 at 0 range 16 .. 31;
end record;
subtype TRISE_TRISE_Field is STM32_SVD.UInt6;
-- TRISE register
type TRISE_Register is record
-- Maximum rise time in Fast/Standard mode (Master mode)
TRISE : TRISE_TRISE_Field := 16#2#;
-- unspecified
Reserved_6_31 : STM32_SVD.UInt26 := 16#0#;
end record
with Volatile_Full_Access, Size => 32,
Bit_Order => System.Low_Order_First;
for TRISE_Register use record
TRISE at 0 range 0 .. 5;
Reserved_6_31 at 0 range 6 .. 31;
end record;
-----------------
-- Peripherals --
-----------------
-- Inter-integrated circuit
type I2C_Peripheral is record
-- Control register 1
CR1 : aliased CR1_Register;
-- Control register 2
CR2 : aliased CR2_Register;
-- Own address register 1
OAR1 : aliased OAR1_Register;
-- Own address register 2
OAR2 : aliased OAR2_Register;
-- Data register
DR : aliased DR_Register;
-- Status register 1
SR1 : aliased SR1_Register;
-- Status register 2
SR2 : aliased SR2_Register;
-- Clock control register
CCR : aliased CCR_Register;
-- TRISE register
TRISE : aliased TRISE_Register;
end record
with Volatile;
for I2C_Peripheral use record
CR1 at 16#0# range 0 .. 31;
CR2 at 16#4# range 0 .. 31;
OAR1 at 16#8# range 0 .. 31;
OAR2 at 16#C# range 0 .. 31;
DR at 16#10# range 0 .. 31;
SR1 at 16#14# range 0 .. 31;
SR2 at 16#18# range 0 .. 31;
CCR at 16#1C# range 0 .. 31;
TRISE at 16#20# range 0 .. 31;
end record;
-- Inter-integrated circuit
I2C1_Periph : aliased I2C_Peripheral
with Import, Address => System'To_Address (16#40005400#);
-- Inter-integrated circuit
I2C2_Periph : aliased I2C_Peripheral
with Import, Address => System'To_Address (16#40005800#);
-- Inter-integrated circuit
I2C3_Periph : aliased I2C_Peripheral
with Import, Address => System'To_Address (16#40005C00#);
end STM32_SVD.I2C;
|
Transynther/x86/_processed/NONE/_xt_/i9-9900K_12_0xca_notsx.log_21829_1311.asm | ljhsiun2/medusa | 9 | 103854 | <reponame>ljhsiun2/medusa
.global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r12
push %r8
push %rcx
push %rdx
push %rsi
lea addresses_WT_ht+0x16fcd, %r12
nop
xor %r8, %r8
movb (%r12), %r10b
nop
nop
nop
nop
xor $56508, %r10
lea addresses_D_ht+0x747d, %rcx
nop
nop
nop
sub %r8, %r8
mov $0x6162636465666768, %rdx
movq %rdx, %xmm5
vmovups %ymm5, (%rcx)
nop
nop
nop
inc %r10
lea addresses_D_ht+0x3d21, %r12
nop
nop
nop
inc %rsi
mov $0x6162636465666768, %r8
movq %r8, (%r12)
nop
nop
nop
nop
sub $21190, %rdx
lea addresses_normal_ht+0x2c2b, %rcx
nop
nop
nop
nop
nop
dec %r8
movw $0x6162, (%rcx)
nop
cmp $37020, %r8
pop %rsi
pop %rdx
pop %rcx
pop %r8
pop %r12
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r11
push %r12
push %rbx
push %rcx
push %rdi
push %rsi
// REPMOV
lea addresses_WT+0xe5ed, %rsi
lea addresses_UC+0x1d4ad, %rdi
clflush (%rsi)
nop
nop
sub %rbx, %rbx
mov $57, %rcx
rep movsb
// Exception!!!
nop
nop
nop
nop
mov (0), %rbx
nop
add %r11, %r11
// Load
lea addresses_D+0xd7cd, %r11
nop
add %r12, %r12
mov (%r11), %r10
nop
nop
nop
nop
nop
xor %rcx, %rcx
// Store
lea addresses_A+0x1a04d, %rdi
nop
cmp %rcx, %rcx
mov $0x5152535455565758, %r11
movq %r11, (%rdi)
nop
xor %r12, %r12
// Store
lea addresses_US+0x781d, %r10
cmp %rbx, %rbx
mov $0x5152535455565758, %rsi
movq %rsi, %xmm7
vmovups %ymm7, (%r10)
xor %rbx, %rbx
// Store
lea addresses_UC+0xf2c5, %rcx
nop
xor $59686, %rsi
movw $0x5152, (%rcx)
cmp %r10, %r10
// Store
lea addresses_RW+0x15881, %rsi
nop
nop
nop
nop
nop
sub %rbx, %rbx
movb $0x51, (%rsi)
sub %r12, %r12
// Store
mov $0x44b06f0000000c0d, %rsi
nop
nop
xor %rbx, %rbx
movw $0x5152, (%rsi)
nop
nop
nop
nop
nop
xor $33842, %rcx
// Store
mov $0x1c71920000000e4d, %rsi
nop
nop
dec %rdi
mov $0x5152535455565758, %r11
movq %r11, (%rsi)
nop
nop
cmp %rcx, %rcx
// Store
lea addresses_PSE+0x1284d, %rcx
nop
nop
nop
nop
nop
xor %rdi, %rdi
movw $0x5152, (%rcx)
nop
nop
nop
nop
sub %rdi, %rdi
// Store
lea addresses_WC+0x684d, %rsi
xor %r10, %r10
movl $0x51525354, (%rsi)
nop
nop
nop
nop
nop
xor $4502, %rdi
// Faulty Load
lea addresses_normal+0xd84d, %r11
nop
sub %r12, %r12
mov (%r11), %si
lea oracles, %r12
and $0xff, %rsi
shlq $12, %rsi
mov (%r12,%rsi,1), %rsi
pop %rsi
pop %rdi
pop %rcx
pop %rbx
pop %r12
pop %r11
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_normal', 'NT': False, 'AVXalign': False, 'size': 4, 'congruent': 0}}
{'OP': 'REPM', 'src': {'same': False, 'congruent': 5, 'type': 'addresses_WT'}, 'dst': {'same': False, 'congruent': 4, 'type': 'addresses_UC'}}
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_D', 'NT': False, 'AVXalign': False, 'size': 8, 'congruent': 7}}
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_A', 'NT': False, 'AVXalign': False, 'size': 8, 'congruent': 8}}
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_US', 'NT': False, 'AVXalign': False, 'size': 32, 'congruent': 4}}
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_UC', 'NT': True, 'AVXalign': False, 'size': 2, 'congruent': 3}}
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_RW', 'NT': True, 'AVXalign': False, 'size': 1, 'congruent': 2}}
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_NC', 'NT': False, 'AVXalign': False, 'size': 2, 'congruent': 6}}
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_NC', 'NT': False, 'AVXalign': False, 'size': 8, 'congruent': 9}}
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_PSE', 'NT': False, 'AVXalign': False, 'size': 2, 'congruent': 9}}
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_WC', 'NT': False, 'AVXalign': False, 'size': 4, 'congruent': 9}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'same': True, 'type': 'addresses_normal', 'NT': False, 'AVXalign': False, 'size': 2, 'congruent': 0}}
<gen_prepare_buffer>
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_WT_ht', 'NT': False, 'AVXalign': False, 'size': 1, 'congruent': 6}}
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_D_ht', 'NT': False, 'AVXalign': False, 'size': 32, 'congruent': 0}}
{'OP': 'STOR', 'dst': {'same': True, 'type': 'addresses_D_ht', 'NT': False, 'AVXalign': False, 'size': 8, 'congruent': 0}}
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_normal_ht', 'NT': False, 'AVXalign': False, 'size': 2, 'congruent': 1}}
{'34': 21829}
34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34
*/
|
unittests/ASM/FEX_bugs/Test_CmpSelect_Merge_branch.asm | cobalt2727/FEX | 0 | 12329 | <gh_stars>0
%ifdef CONFIG
{
"RegData": {
"RAX": "0x0000000aaaaafaaa"
}
}
%endif
%macro intcompare 3
; instruction, value1, value2
mov rcx, %2
mov rdx, %3
shl rax, 1
cmp rcx, rdx
; Conditional branch
%1 %%true
%%fallthrough:
; False fallthrough path
mov rbx, 0
jmp %%combine
%%true:
; True path
mov rbx, 1
%%combine:
; Combine
or rax, rbx
%endmacro
; This test specifically tests the Select and compare merging that occurs in OpcodeDispatcher
; The easiest way to test this is to do the comparison op and then SETcc with the flags that we want to ensure is working
; RAX will be our result
mov rax, 0
; RBX will be our temp for setcc
mov rbx, 0
; Test integer ops
; RCX and RDX for comparison values
mov rcx, 0
mov rdx, 0
; Test EQ - true
intcompare je, 0, 0
; Test EQ - false
intcompare je, 0, 1
; Test NEQ - true
intcompare jne, 0, 1
; Test NEQ - false
intcompare jne, 0, 0
; Test SGE - true
intcompare jge, 0, 0
; Test SGE - false
intcompare jge, 0, 1
; Test SGE with sign difference - true
intcompare jge, 1, -1
; Test SGE with sign difference - false
intcompare jge, -1, 1
; Test SLT - true
intcompare jl, 0, 1
; Test SLT - false
intcompare jl, 0, 0
; Test SLT with sign difference - true
intcompare jl, -1, 1
; Test SLT with sign difference - false
intcompare jl, 1, -1
; Test SGT - true
intcompare jg, 1, 0
; Test SGT - false
intcompare jg, 0, 0
; Test SGT with sign difference - true
intcompare jg, 1, -1
; Test SGT with sign difference - false
intcompare jg, -1, 1
; Test SLE - true
intcompare jle, 0, 0
; Test SLE - false
intcompare jle, 1, 0
; Test SLE with sign difference - true
intcompare jle, -1, 1
; Test SLE with sign difference - false
intcompare jle, 1, -1
; Test UGE - true
intcompare jae, 0, 0
; Test UGE - false
intcompare jae, 1, 0
; Test UGE with *sign* difference - true
intcompare jae, -1, 1
; Test UGE with *sign* difference - false
intcompare jb, 1, -1
; Test ULT - true
intcompare jb, 0, 1
; Test ULT - false
intcompare jb, 1, 0
; Test ULT with *sign* difference - true
intcompare jb, 1, -1
; Test ULT with *sign* difference - false
intcompare jb, -1, 1
; Test UGT - true
intcompare ja, 1, 0
; Test UGT - false
intcompare ja, 0, 1
; Test UGT with *sign* difference - true
intcompare ja, -1, 1
; Test UGT with *sign* difference - false
intcompare ja, 1, -1
; Test ULE - true
intcompare jbe, 0, 0
; Test ULE - false
intcompare jbe, 1, 0
; Test ULE with *sign* difference - true
intcompare jbe, 1, -1
; Test ULE with *sign* difference - false
intcompare jbe, -1, 1
hlt
|
Actions/Resources/GetVocabularyAction/main.applescript | mikecsh/ProVoc | 5 | 1549 | <reponame>mikecsh/ProVoc
-- main.applescript
-- ProVoc
-- Created by <NAME> on 19.05.06.
-- Copyright 2006 Arizona Software. All rights reserved.
on run {input, parameters}
set theSelectionOnly to |selectionOnly| of parameters
set theIncludeNames to |includeNames| of parameters
set theIncludeComments to |includeComments| of parameters
tell application "ProVoc"
return export only selection theSelectionOnly include names theIncludeNames include comments theIncludeComments
end tell
end run
|
alloy4fun_models/trashltl/models/8/XR5PZx89kSZrW9c3X.als | Kaixi26/org.alloytools.alloy | 0 | 544 | open main
pred idXR5PZx89kSZrW9c3X_prop9 {
all p : Protected | p not in Trash' and p.(^link) not in Trash'
}
pred __repair { idXR5PZx89kSZrW9c3X_prop9 }
check __repair { idXR5PZx89kSZrW9c3X_prop9 <=> prop9o } |
lib/Explore/Product.agda | crypto-agda/explore | 2 | 10682 | {-# OPTIONS --without-K #-}
{- The main definitions are the following:
* exploreΣ
* exploreΣ-ind
* adequate-sumΣ
-}
open import Level.NP
open import Type hiding (★)
open import Type.Identities
open import Function.NP
open import Function.Extensionality
open import Data.Two
open import Data.Product.NP
open import Data.Fin
open import Relation.Binary.Logical
open import Relation.Binary.PropositionalEquality.NP using (_≡_ ; module ≡-Reasoning; !_; _∙_; coe; tr; ap; ap₂; J-orig)
open import HoTT
open import Category.Monad.Continuation.Alias
open import Explore.Core
open import Explore.Properties
import Explore.Monad as EM
open import Explore.Explorable
module Explore.Product where
module _ {m a b} {A : ★ a} {B : A → ★ b} where
exploreΣ : Explore m A → (∀ {x} → Explore m (B x)) → Explore m (Σ A B)
exploreΣ exploreᴬ exploreᴮ ε _⊕_ = exploreᴬ ε _⊕_ ⟨,⟩ exploreᴮ ε _⊕_
module _ {eᴬ : Explore m A} {eᴮ : ∀ {x} → Explore m (B x)} where
exploreΣ-ind : ∀ {p} → ExploreInd p eᴬ → (∀ {x} → ExploreInd p (eᴮ {x})) → ExploreInd p (exploreΣ eᴬ eᴮ)
exploreΣ-ind Peᴬ Peᴮ P Pε P⊕ Pf =
Peᴬ (λ e → P (λ _ _ _ → e _ _ _)) Pε P⊕ (λ x → Peᴮ {x} (λ e → P (λ _ _ _ → e _ _ _)) Pε P⊕ (curry Pf x))
module _
{ℓ₀ ℓ₁ ℓᵣ}
{a₀ a₁ aᵣ} {A₀ : ★ a₀} {A₁ : ★ a₁} {Aᵣ : ⟦★⟧ aᵣ A₀ A₁}
{b₀ b₁ bᵣ} {B₀ : A₀ → ★ b₀} {B₁ : A₁ → ★ b₁} {Bᵣ : (Aᵣ ⟦→⟧ ⟦★⟧ bᵣ) B₀ B₁}
{eᴬ₀ : Explore ℓ₀ A₀} {eᴬ₁ : Explore ℓ₁ A₁}(eᴬᵣ : ⟦Explore⟧ ℓᵣ Aᵣ eᴬ₀ eᴬ₁)
{eᴮ₀ : ∀ {x} → Explore ℓ₀ (B₀ x)} {eᴮ₁ : ∀ {x} → Explore ℓ₁ (B₁ x)}(eᴮᵣ : ∀ {x₀ x₁}(x : Aᵣ x₀ x₁) → ⟦Explore⟧ ℓᵣ (Bᵣ x) (eᴮ₀ {x₀}) (eᴮ₁ {x₁}))
where
⟦exploreΣ⟧ : ⟦Explore⟧ ℓᵣ (⟦Σ⟧ Aᵣ Bᵣ) (exploreΣ eᴬ₀ (λ {x} → eᴮ₀ {x})) (exploreΣ eᴬ₁ (λ {x} → eᴮ₁ {x}))
⟦exploreΣ⟧ P Pε P⊕ Pf = eᴬᵣ P Pε P⊕ (λ {x₀} {x₁} x → eᴮᵣ x P Pε P⊕ (λ xᵣ → Pf (x ⟦,⟧ xᵣ)))
module _
{ℓ₀ ℓ₁ ℓᵣ}
{a} {A : ★ a}
{b} {B : A → ★ b}
{eᴬ₀ : Explore ℓ₀ A} {eᴬ₁ : Explore ℓ₁ A}(eᴬᵣ : ⟦Explore⟧ ℓᵣ _≡_ eᴬ₀ eᴬ₁)
{eᴮ₀ : ∀ {x} → Explore ℓ₀ (B x)} {eᴮ₁ : ∀ {x} → Explore ℓ₁ (B x)}
(eᴮᵣ : ∀ x → ⟦Explore⟧ ℓᵣ _≡_ (eᴮ₀ {x}) (eᴮ₁ {x}))
where
⟦exploreΣ⟧≡ : ⟦Explore⟧ ℓᵣ _≡_ (exploreΣ eᴬ₀ (λ {x} → eᴮ₀ {x})) (exploreΣ eᴬ₁ (λ {x} → eᴮ₁ {x}))
⟦exploreΣ⟧≡ P Pε P⊕ Pf = eᴬᵣ P Pε P⊕ λ x → J-orig _ (λ y → eᴮᵣ y P Pε P⊕ (Pf ∘ ap (_,_ y))) x
module _
{ℓ₀ ℓ₁ ℓᵣ}
{a} {A : ★ a}
{b} {B : A → ★ b}
{eᴬ₀ : Explore ℓ₀ A} {eᴬ₁ : Explore ℓ₁ A}(eᴬᵣ : ⟦Explore⟧ ℓᵣ _≡_ eᴬ₀ eᴬ₁)
{eᴮ₀ : ∀ {x} → Explore ℓ₀ (B x)} {eᴮ₁ : ∀ {x} → Explore ℓ₁ (B x)}
(eᴮᵣ : ∀ {x₀ x₁} (x : x₀ ≡ x₁) → ⟦Explore⟧ ℓᵣ (λ b₀ b₁ → tr B x b₀ ≡ b₁) (eᴮ₀ {x₀}) (eᴮ₁ {x₁}))
where
⟦exploreΣ⟧↑≡ : ⟦Explore⟧ ℓᵣ _≡_ (exploreΣ eᴬ₀ (λ {x} → eᴮ₀ {x})) (exploreΣ eᴬ₁ (λ {x} → eᴮ₁ {x}))
⟦exploreΣ⟧↑≡ P Pε P⊕ Pf = eᴬᵣ P Pε P⊕ (λ x → eᴮᵣ x P Pε P⊕ (Pf ∘ pair= x))
module _ {A : ★₀} {B : A → ★₀} {sumᴬ : Sum A} {sumᴮ : ∀ {x} → Sum (B x)}{{_ : FunExt}}{{_ : UA}} where
open Adequacy _≡_
private
sumᴬᴮ : Sum (Σ A B)
sumᴬᴮ = sumᴬ ⟨,⟩ (λ {x} → sumᴮ {x})
adequate-sumΣ : Adequate-sum sumᴬ → (∀ {x} → Adequate-sum (sumᴮ {x})) → Adequate-sum sumᴬᴮ
adequate-sumΣ asumᴬ asumᴮ f
= Fin (sumᴬᴮ f)
≡⟨by-definition⟩
Fin (sumᴬ (λ a → sumᴮ (λ b → f (a , b))))
≡⟨ asumᴬ _ ⟩
Σ A (λ a → Fin (sumᴮ (λ b → f (a , b))))
≡⟨ Σ=′ _ (λ _ → asumᴮ _) ⟩
Σ A (λ a → Σ (B a) (λ b → Fin (f (a , b))))
≡⟨ Σ-assoc ⟩
Σ (Σ A B) (Fin ∘ f)
∎
where open ≡-Reasoning
-- From now on, these are derived definitions for convenience and pedagogical reasons
explore× : ∀ {m a b} {A : ★ a} {B : ★ b} → Explore m A → Explore m B → Explore m (A × B)
explore× exploreᴬ exploreᴮ = exploreΣ exploreᴬ exploreᴮ
explore×-ind : ∀ {m p a b} {A : ★ a} {B : ★ b} {eᴬ : Explore m A} {eᴮ : Explore m B}
→ ExploreInd p eᴬ → ExploreInd p eᴮ
→ ExploreInd p (explore× eᴬ eᴮ)
explore×-ind Peᴬ Peᴮ = exploreΣ-ind Peᴬ Peᴮ
sumΣ : ∀ {a b} {A : ★ a} {B : A → ★ b} → Sum A → (∀ {x} → Sum (B x)) → Sum (Σ A B)
sumΣ = _⟨,⟩_
sum× : ∀ {a b} {A : ★ a} {B : ★ b} → Sum A → Sum B → Sum (A × B)
sum× = _⟨,⟩′_
module _ {ℓ₀ ℓ₁ ℓᵣ A₀ A₁ B₀ B₁}
{Aᵣ : ⟦★₀⟧ A₀ A₁}
{Bᵣ : ⟦★₀⟧ B₀ B₁}
{eᴬ₀ : Explore ℓ₀ A₀} {eᴬ₁ : Explore ℓ₁ A₁}(eᴬᵣ : ⟦Explore⟧ ℓᵣ Aᵣ eᴬ₀ eᴬ₁)
{eᴮ₀ : Explore ℓ₀ B₀} {eᴮ₁ : Explore ℓ₁ B₁}(eᴮᵣ : ⟦Explore⟧ ℓᵣ Bᵣ eᴮ₀ eᴮ₁)
where
⟦explore×⟧ : ⟦Explore⟧ ℓᵣ (Aᵣ ⟦×⟧ Bᵣ) (explore× eᴬ₀ eᴮ₀) (explore× eᴬ₁ eᴮ₁)
⟦explore×⟧ P Pε P⊕ Pf = eᴬᵣ P Pε P⊕ (λ x → eᴮᵣ P Pε P⊕ (λ y → Pf (_⟦,⟧_ x y)))
module _ {ℓ₀ ℓ₁ ℓᵣ} {A B : ★₀}
{eᴬ₀ : Explore ℓ₀ A} {eᴬ₁ : Explore ℓ₁ A}(eᴬᵣ : ⟦Explore⟧ ℓᵣ _≡_ eᴬ₀ eᴬ₁)
{eᴮ₀ : Explore ℓ₀ B} {eᴮ₁ : Explore ℓ₁ B}(eᴮᵣ : ⟦Explore⟧ ℓᵣ _≡_ eᴮ₀ eᴮ₁)
where
⟦explore×⟧≡ : ⟦Explore⟧ ℓᵣ _≡_ (explore× eᴬ₀ eᴮ₀) (explore× eᴬ₁ eᴮ₁)
⟦explore×⟧≡ P Pε P⊕ Pf = eᴬᵣ P Pε P⊕ (λ x → eᴮᵣ P Pε P⊕ (λ y → Pf (ap₂ _,_ x y)))
{-
μΣ : ∀ {A} {B : A → ★ _} → Explorable A → (∀ {x} → Explorable (B x)) → Explorable (Σ A B)
μΣ μA μB = mk _ (exploreΣ-ind (explore-ind μA) (explore-ind μB))
(adequate-sumΣ (adequate-sum μA) (adequate-sum μB))
infixr 4 _×-μ_
_×-μ_ : ∀ {A B} → Explorable A → Explorable B → Explorable (A × B)
μA ×-μ μB = μΣ μA μB
_×-cmp_ : ∀ {A B : ★₀ } → Cmp A → Cmp B → Cmp (A × B)
(ca ×-cmp cb) (a , b) (a' , b') = ca a a' ∧ cb b b'
×-unique : ∀ {A B}(μA : Explorable A)(μB : Explorable B)(cA : Cmp A)(cB : Cmp B)
→ Unique cA (count μA) → Unique cB (count μB) → Unique (cA ×-cmp cB) (count (μA ×-μ μB))
×-unique μA μB cA cB uA uB (x , y) = count (μA ×-μ μB) ((cA ×-cmp cB) (x , y)) ≡⟨ explore-ext μA _ (λ x' → help (cA x x')) ⟩
count μA (cA x) ≡⟨ uA x ⟩
1 ∎
where
open ≡-Reasoning
help : ∀ b → count μB (λ y' → b ∧ cB y y') ≡ (if b then 1 else 0)
help = [0: sum-zero μB 1: uB y ]
-}
{-
module _ {A} {Aₚ : A → ★₀} {B : A → _} {eᴬ : Explore ₁ A} (eᴬₚ : [Explore] _ _ Aₚ eᴬ) (eᴬ-ind : ExploreInd (ₛ ₀) eᴬ) {eᴮ : ∀ {x} → Explore ₀ (B x)} where
open import Explore.One
--open import Explore.Product
exploreΠᵉ : Explore ₀ (Πᵉ eᴬ B)
exploreΠᵉ = eᴬ-ind (λ e → Explore ₀ (Πᵉ e B)) (λ ε _∙₁_ x → x _) explore× (λ x → eᴮ {x})
exploreΠᵉ' : Explore ₀ (Πᵉ eᴬ B)
exploreΠᵉ' = λ {M} ε _∙₁_ x → {!eᴬₚ (const (Lift M))!}
exploreΠᵉ-ind : ExploreInd ₁ exploreΠᵉ
exploreΠᵉ-ind = {!⟦Explore⟧ᵤ _ _ _ eᴬ!}
-}
module _ {ℓ a b} {A : ★ a} {B : A → ★ b} {eᴬ : Explore (ₛ ℓ) A} {eᴮ : ∀ {x} → Explore (ₛ ℓ) (B x)} where
private
eᴬᴮ = exploreΣ eᴬ λ {x} → eᴮ {x}
focusΣ : Focus eᴬ → (∀ {x} → Focus (eᴮ {x})) → Focus eᴬᴮ
focusΣ fᴬ fᴮ ((x , y) , z) = fᴬ (x , fᴮ (y , z))
lookupΣ : Lookup eᴬ → (∀ {x} → Lookup (eᴮ {x})) → Lookup eᴬᴮ
lookupΣ lookupᴬ lookupᴮ d = uncurry (lookupᴮ ∘ lookupᴬ d)
-- can also be derived from explore-ind
reifyΣ : Reify eᴬ → (∀ {x} → Reify (eᴮ {x})) → Reify eᴬᴮ
reifyΣ reifyᴬ reifyᴮ f = reifyᴬ (reifyᴮ ∘ curry f)
module _ {ℓ} {A : ★₀} {B : A → ★₀}
{eᴬ : Explore (ₛ ℓ) A} {eᴮ : ∀ {x} → Explore (ₛ ℓ) (B x)}
{{_ : UA}}{{_ : FunExt}} where
private
eᴬᴮ = exploreΣ eᴬ λ {x} → eᴮ {x}
ΣᵉΣ-ok : Adequate-Σ (Σᵉ eᴬ) → (∀ {x} → Adequate-Σ (Σᵉ (eᴮ {x}))) → Adequate-Σ (Σᵉ eᴬᴮ)
ΣᵉΣ-ok eᴬ eᴮ f = eᴬ _ ∙ Σ=′ _ (λ _ → eᴮ _) ∙ Σ-assoc
ΠᵉΣ-ok : Adequate-Π (Πᵉ eᴬ) → (∀ {x} → Adequate-Π (Πᵉ (eᴮ {x}))) → Adequate-Π (Πᵉ eᴬᴮ)
ΠᵉΣ-ok eᴬ eᴮ f = eᴬ _ ∙ Π=′ _ (λ _ → eᴮ _) ∙ ! ΠΣ-curry
module _ {ℓ a b} {A : ★ a} {B : ★ b} {eᴬ : Explore (ₛ ℓ) A} {eᴮ : Explore (ₛ ℓ) B} where
private
eᴬᴮ = explore× eᴬ eᴮ
focus× : Focus eᴬ → Focus eᴮ → Focus eᴬᴮ
focus× fᴬ fᴮ = focusΣ {eᴬ = eᴬ} {eᴮ = eᴮ} fᴬ fᴮ
lookup× : Lookup eᴬ → Lookup eᴮ → Lookup eᴬᴮ
lookup× fᴬ fᴮ = lookupΣ {eᴬ = eᴬ} {eᴮ = eᴮ} fᴬ fᴮ
module _ {ℓ} {A B : ★₀} {eᴬ : Explore (ₛ ℓ) A} {eᴮ : Explore (ₛ ℓ) B} where
private
eᴬᴮ = explore× eᴬ eᴮ
Σᵉ×-ok : {{_ : UA}}{{_ : FunExt}} → Adequate-Σ (Σᵉ eᴬ) → Adequate-Σ (Σᵉ eᴮ) → Adequate-Σ (Σᵉ eᴬᴮ)
Σᵉ×-ok eᴬ eᴮ f = eᴬ _ ∙ Σ=′ _ (λ _ → eᴮ _) ∙ Σ-assoc
Πᵉ×-ok : {{_ : UA}}{{_ : FunExt}} → Adequate-Π (Πᵉ eᴬ) → Adequate-Π (Πᵉ eᴮ) → Adequate-Π (Πᵉ eᴬᴮ)
Πᵉ×-ok eᴬ eᴮ f = eᴬ _ ∙ Π=′ _ (λ _ → eᴮ _) ∙ ! ΠΣ-curry
module Operators where
infixr 4 _×ᵉ_ _×ⁱ_ _×ˢ_
_×ᵉ_ = explore×
_×ⁱ_ = explore×-ind
_×ᵃ_ = adequate-sumΣ
_×ˢ_ = sum×
_×ᶠ_ = focus×
_×ˡ_ = lookup×
-- Those are here only for pedagogical use
private
fst-explore : ∀ {m} {A : ★₀} {B : A → ★₀} → Explore m (Σ A B) → Explore m A
fst-explore = EM.map _ fst
snd-explore : ∀ {m} {A B : ★₀} → Explore m (A × B) → Explore m B
snd-explore = EM.map _ snd
sum'Σ : ∀ {A : ★₀} {B : A → ★₀} → Sum A → (∀ x → Sum (B x)) → Sum (Σ A B)
sum'Σ sumᴬ sumᴮ f = sumᴬ (λ x₀ →
sumᴮ x₀ (λ x₁ →
f (x₀ , x₁)))
explore×' : ∀ {A B : ★₀} → Explore₀ A → Explore _ B → Explore _ (A × B)
explore×' exploreᴬ exploreᴮ ε _⊕_ f = exploreᴬ ε _⊕_ (λ x → exploreᴮ ε _⊕_ (curry f x))
explore×-ind' : ∀ {A B} {eᴬ : Explore _ A} {eᴮ : Explore _ B}
→ ExploreInd₀ eᴬ → ExploreInd₀ eᴮ → ExploreInd₀ (explore×' eᴬ eᴮ)
explore×-ind' Peᴬ Peᴮ P Pε P⊕ Pf =
Peᴬ (λ e → P (λ _ _ _ → e _ _ _)) Pε P⊕ (Peᴮ (λ e → P (λ _ _ _ → e _ _ _)) Pε P⊕ ∘ curry Pf)
-- liftM2 _,_ in the continuation monad
sum×' : ∀ {A B : ★₀} → Sum A → Sum B → Sum (A × B)
sum×' sumᴬ sumᴮ f = sumᴬ λ x₀ →
sumᴮ λ x₁ →
f (x₀ , x₁)
-- -}
-- -}
-- -}
|
src/gl/interface/gl-objects-queries.ads | Roldak/OpenGLAda | 79 | 11594 | <gh_stars>10-100
-- part of OpenGLAda, (c) 2017 <NAME>
-- released under the terms of the MIT license, see the file "COPYING"
with GL.Low_Level.Enums;
package GL.Objects.Queries is
pragma Preelaborate;
type Query_Object is new GL_Object with private;
Default_Query : constant Query_Object;
procedure Begin_Query (Target : GL.Low_Level.Enums.Query_Param;
Object : Query_Object);
procedure End_Query (Target : GL.Low_Level.Enums.Query_Param);
procedure Begin_Query_Indexed (Target : GL.Low_Level.Enums.Query_Param;
Index : UInt; Object : Query_Object);
procedure End_Query_Indexed (Target : GL.Low_Level.Enums.Query_Param;
Index : UInt);
procedure Get_Query_Object (Object : Query_Object;
Pname : GL.Low_Level.Enums.Query_Results;
Params : out UInt);
function Is_Query (Query : Query_Object) return Boolean;
procedure Query_Counter (Object : Query_Object;
Target : Low_Level.Enums.Query_Param);
private
type Query_Object is new GL_Object with null record;
overriding
procedure Internal_Create_Id (Object : Query_Object; Id : out UInt);
overriding
procedure Internal_Release_Id (Object : Query_Object; Id : UInt);
Default_Query : constant Query_Object := Query_Object'(
Ada.Finalization.Controlled with
Reference => Reference_To_Null_Object'Access);
end GL.Objects.Queries;
|
graphics/palettes.asm | cppchriscpp/ld38 | 4 | 241538 | <filename>graphics/palettes.asm
.export _main_palette, _sprite_palette
_main_palette:
.incbin "graphics/main.pal"
_sprite_palette:
.incbin "graphics/sprite.pal" |
source/compiler/compiler-context.adb | yannickmoy/protobuf | 12 | 10432 | <gh_stars>10-100
-- MIT License
--
-- Copyright (c) 2020 <NAME>
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-- THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
with League.String_Vectors;
with Compiler.File_Descriptors;
package body Compiler.Context is
function "+" (Text : Wide_Wide_String)
return League.Strings.Universal_String
renames League.Strings.To_Universal_String;
Reserved : String_Sets.Set;
---------
-- "+" --
---------
function "+"
(Self : Ada_Type_Name) return League.Strings.Universal_String
is
use type League.Strings.Universal_String;
begin
if Self.Package_Name.Is_Empty then
return Self.Type_Name;
else
return Self.Package_Name & "." & Self.Type_Name;
end if;
end "+";
--------------
-- Get_File --
--------------
function Get_File
(Request : Google.Protobuf.Compiler.Plugin.Code_Generator_Request;
Name : League.Strings.Universal_String)
return Google.Protobuf.Descriptor.File_Descriptor_Proto
is
use type League.Strings.Universal_String;
begin
for J in 1 .. Request.Proto_File.Length loop
declare
Result : constant Google.Protobuf.Descriptor.File_Descriptor_Proto
:= Request.Proto_File (J);
begin
if Result.Name.Is_Set and then Result.Name.Value = Name then
return Result;
end if;
end;
end loop;
raise Constraint_Error;
end Get_File;
--------------------------
-- Populate_Named_Types --
--------------------------
procedure Populate_Named_Types
(Request : Google.Protobuf.Compiler.Plugin.Code_Generator_Request;
Map : in out Compiler.Context.Named_Type_Maps.Map) is
begin
for J in 1 .. Request.Proto_File.Length loop
Compiler.File_Descriptors.Populate_Named_Types
(Request.Proto_File (J), Map);
end loop;
end Populate_Named_Types;
-------------------
-- Relative_Name --
-------------------
function Relative_Name
(Full_Name : League.Strings.Universal_String;
Current_Package : League.Strings.Universal_String)
return League.Strings.Universal_String
is
use type League.Strings.Universal_String;
FN : constant League.String_Vectors.Universal_String_Vector :=
Full_Name.Split ('.');
CP : constant League.String_Vectors.Universal_String_Vector :=
Current_Package.Split ('.');
begin
for J in 1 .. FN.Length - 1 loop
declare
Prefix : constant League.Strings.Universal_String :=
FN.Element (J);
Ok : Boolean := True;
begin
for K in J + 1 .. CP.Length loop
Ok := Prefix /= CP.Element (K);
exit when not Ok;
end loop;
if Ok then
declare
Result : League.String_Vectors.Universal_String_Vector;
begin
for K in J .. FN.Length loop
Result.Append (FN.Element (K));
end loop;
return Result.Join ('.');
end;
end if;
end;
end loop;
return FN.Element (FN.Length);
end Relative_Name;
-----------------
-- To_Ada_Name --
-----------------
function To_Ada_Name
(Text : League.Strings.Universal_String)
return League.Strings.Universal_String
is
use type League.Strings.Universal_String;
Allow_Underscore : Boolean := False;
Force_Upper : Boolean := True;
Last_Was_Upper : Boolean := True;
Result : League.Strings.Universal_String;
begin
if Reserved.Contains (Text.To_Lowercase) then
return To_Ada_Name ("PB_" & Text);
elsif Text.Ends_With ("_") then
return To_Ada_Name (Text.Head (Text.Length - 1));
end if;
for J in 1 .. Text.Length loop
if Text.Element (J).To_Wide_Wide_Character = '_' then
if Allow_Underscore then
Result.Append (Text.Element (J));
end if;
Force_Upper := True;
elsif Force_Upper then
Result.Append (Text.Slice (J, J).To_Uppercase);
Force_Upper := False;
Last_Was_Upper := True;
elsif Text.Slice (J, J).To_Uppercase /= Text.Slice (J, J) then
Last_Was_Upper := False;
Result.Append (Text.Element (J));
elsif not Last_Was_Upper then
Last_Was_Upper := True;
Result.Append ("_");
Result.Append (Text.Element (J));
else
Result.Append (Text.Element (J));
end if;
Allow_Underscore := Text.Element (J).To_Wide_Wide_Character /= '_';
end loop;
return Result;
end To_Ada_Name;
--------------------------
-- To_Selected_Ada_Name --
--------------------------
function To_Selected_Ada_Name
(Text : League.Strings.Universal_String)
return League.Strings.Universal_String
is
List : League.String_Vectors.Universal_String_Vector := Text.Split ('.');
begin
for J in 1 .. List.Length loop
List.Replace (J, To_Ada_Name (List (J)));
end loop;
return List.Join ('.');
end To_Selected_Ada_Name;
begin
Reserved.Insert (+"begin");
Reserved.Insert (+"end");
Reserved.Insert (+"package");
Reserved.Insert (+"type");
end Compiler.Context;
|
Agda/subuniverses.agda | tmoux/HoTT-Intro | 0 | 13726 | {-# OPTIONS --without-K --allow-unsolved-metas #-}
module subuniverses where
import 14-univalence
open 14-univalence public
{-
is-local :
{l1 l2 l3 l4 : Level}
{I : UU l1} {A : I → UU l2} {B : I → UU l3} (f : (i : I) → A i → B i)
(X : UU l4) → UU (l1 ⊔ (l2 ⊔ (l3 ⊔ l4)))
is-local {I = I} {B = B} f X =
(i : I) → is-equiv (λ (h : B i → X) → h ∘ (f i))
is-subuniverse-is-local :
{l1 l2 l3 l4 : Level}
{I : UU l1} {A : I → UU l2} {B : I → UU l3} (f : (i : I) → A i → B i) →
is-subuniverse (is-local {l4 = l4} f)
is-subuniverse-is-local f X = is-prop-Π (λ i → is-subtype-is-equiv _)
-}
universal-property-localization :
{l1 l2 : Level} (P : subuniverse l1 l2)
(X : UU l1) (Y : total-subuniverse P) (l : X → pr1 Y) →
UU ((lsuc l1) ⊔ l2)
universal-property-localization {l1} (pair P H) X (pair Y p) l =
(Z : UU l1) (q : P Z) → is-equiv (λ (h : Y → Z) → h ∘ l)
universal-property-localization' :
(l : Level) (α : Level → Level) (P : (l : Level) → subuniverse l (α l))
(g : (l1 l2 : Level) → is-global-subuniverse α P l1 l2)
{l1 l2 : Level} (X : UU l1) (Y : total-subuniverse (P l2)) (f : X → pr1 Y) →
UU ((lsuc l) ⊔ ((α l) ⊔ (l1 ⊔ l2)))
universal-property-localization' l α P g X Y f =
(Z : total-subuniverse (P l)) → is-equiv (λ (h : (pr1 Y) → (pr1 Z)) → h ∘ f)
is-prop-universal-property-localization :
{l1 l2 : Level} (P : subuniverse l1 l2) (X : UU l1)
(Y : total-subuniverse P) (l : X → pr1 Y) →
is-prop (universal-property-localization P X Y l)
is-prop-universal-property-localization (pair P H) X (pair Y p) l =
is-prop-Π (λ Z → is-prop-Π (λ q → is-subtype-is-equiv _))
has-localization :
{l1 l2 : Level} (P : subuniverse l1 l2) (X : UU l1) →
UU ((lsuc l1) ⊔ l2)
has-localization {l1} P X =
Σ ( total-subuniverse P)
( λ Y → Σ (X → pr1 Y) (universal-property-localization P X Y))
Eq-localizations :
{l1 l2 : Level} (P : subuniverse l1 l2) (X : UU l1) →
( s t : has-localization P X) → UU l1
Eq-localizations (pair P H) X
(pair (pair Y p) (pair l up)) t =
let Y' = pr1 (pr1 t)
p' = pr1 (pr1 t)
l' = pr1 (pr2 t)
up' = pr2 (pr2 t)
in
Σ ( Y ≃ Y')
( λ e → ((map-equiv e) ∘ l) ~ l' )
reflexive-Eq-localizations :
{l1 l2 : Level} (P : subuniverse l1 l2) (X : UU l1) →
(s : has-localization P X) → Eq-localizations P X s s
reflexive-Eq-localizations (pair P H) X (pair (pair Y p) (pair l up)) =
pair (equiv-id Y) (htpy-refl l)
Eq-localizations-eq :
{l1 l2 : Level} (P : subuniverse l1 l2) (X : UU l1) →
( s t : has-localization P X) → Id s t → Eq-localizations P X s t
Eq-localizations-eq P X s s refl = reflexive-Eq-localizations P X s
is-contr-total-Eq-localizations :
{l1 l2 : Level} (P : subuniverse l1 l2) (X : UU l1)
(s : has-localization P X) →
is-contr (Σ (has-localization P X) (Eq-localizations P X s))
is-contr-total-Eq-localizations
(pair P H) X (pair (pair Y p) (pair l up)) =
is-contr-total-Eq-structure
( λ Y' l' e → ((map-equiv e) ∘ l) ~ (pr1 l'))
( is-contr-total-Eq-total-subuniverse (pair P H) (pair Y p))
( pair (pair Y p) (equiv-id Y))
( is-contr-total-Eq-substructure
( is-contr-total-htpy l)
( is-prop-universal-property-localization (pair P H) X (pair Y p))
( l)
( htpy-refl _)
( up))
is-equiv-Eq-localizations-eq :
{l1 l2 : Level} (P : subuniverse l1 l2) (X : UU l1) →
( s t : has-localization P X) → is-equiv (Eq-localizations-eq P X s t)
is-equiv-Eq-localizations-eq P X s =
fundamental-theorem-id s
( reflexive-Eq-localizations P X s)
( is-contr-total-Eq-localizations P X s)
( Eq-localizations-eq P X s)
eq-Eq-localizations :
{l1 l2 : Level} (P : subuniverse l1 l2) (X : UU l1)
( s t : has-localization P X) → (Eq-localizations P X s t) → Id s t
eq-Eq-localizations P X s t =
inv-is-equiv (is-equiv-Eq-localizations-eq P X s t)
uniqueness-localizations :
{l1 l2 : Level} (P : subuniverse l1 l2) (X : UU l1) →
( s t : has-localization P X) → Eq-localizations P X s t
uniqueness-localizations (pair P H) X
(pair (pair Y p) (pair l up)) (pair (pair Y' p') (pair l' up')) =
pair
( pair
( inv-is-equiv (up Y' p') l')
( is-equiv-has-inverse
( pair
( inv-is-equiv (up' Y p) l)
( pair
( htpy-eq
( ap
( pr1 {B = λ h → Id (h ∘ l') l'})
( center
( is-prop-is-contr
( is-contr-map-is-equiv (up' Y' p') l')
( pair
( ( inv-is-equiv (up Y' p') l') ∘
( inv-is-equiv (up' Y p) l))
( ( ap
( λ t → (inv-is-equiv (up Y' p') l') ∘ t)
( issec-inv-is-equiv (up' Y p) l)) ∙
( issec-inv-is-equiv (up Y' p') l')))
( pair id refl)))))
( htpy-eq
( ap
( pr1 {B = λ h → Id (h ∘ l) l})
( center
( is-prop-is-contr
( is-contr-map-is-equiv (up Y p) l)
( pair
( ( inv-is-equiv (up' Y p) l) ∘
( inv-is-equiv (up Y' p') l'))
( ( ap
( λ t → (inv-is-equiv (up' Y p) l) ∘ t)
( issec-inv-is-equiv (up Y' p') l')) ∙
issec-inv-is-equiv (up' Y p) l))
( pair id refl)))))))))
( htpy-eq (issec-inv-is-equiv (up Y' p') l'))
is-prop-localizations :
{l1 l2 : Level} (P : subuniverse l1 l2) (X : UU l1) →
is-prop (has-localization P X)
is-prop-localizations P X =
is-prop-is-prop'
( λ Y Y' → eq-Eq-localizations P X Y Y'
( uniqueness-localizations P X Y Y'))
universal-property-localization-equiv-is-local :
{l1 l2 : Level} (P : subuniverse l1 l2) (X : UU l1) →
(Y : UU l1) (p : (pr1 P) Y) (l : X → Y) →
is-equiv l → universal-property-localization P X (pair Y p) l
universal-property-localization-equiv-is-local
(pair P H) X Y p l is-equiv-l Z q =
is-equiv-precomp-is-equiv l is-equiv-l Z
universal-property-localization-id-is-local :
{l1 l2 : Level} (P : subuniverse l1 l2) (X : UU l1) (q : (pr1 P) X) →
universal-property-localization P X (pair X q) id
universal-property-localization-id-is-local P X q =
universal-property-localization-equiv-is-local P X X q id (is-equiv-id X)
is-equiv-localization-is-local :
{l1 l2 : Level} (P : subuniverse l1 l2) (X : UU l1) →
( Y : has-localization P X) → (pr1 P) X → is-equiv (pr1 (pr2 Y))
is-equiv-localization-is-local
(pair P H) X (pair (pair Y p) (pair l up)) q =
is-equiv-right-factor
( id)
( inv-is-equiv (up X q) id)
( l)
( htpy-eq (inv (issec-inv-is-equiv (up X q) id)))
( pr2
( pr1
( uniqueness-localizations (pair P H) X
( pair (pair Y p) (pair l up))
( pair
( pair X q)
( pair id
( universal-property-localization-id-is-local
(pair P H) X q))))))
( is-equiv-id X)
is-local-is-equiv-localization :
{l1 l2 : Level} (P : subuniverse l1 l2) (X : UU l1) →
( Y : has-localization P X) → is-equiv (pr1 (pr2 Y)) → (pr1 P) X
is-local-is-equiv-localization
(pair P H) X (pair (pair Y p) (pair l up)) is-equiv-l =
in-subuniverse-equiv' P (pair l is-equiv-l) p
strong-retraction-property-localization :
{l1 l2 : Level} (P : subuniverse l1 l2) (X : UU l1) →
(Y : total-subuniverse P) (l : X → pr1 Y) → UU l1
strong-retraction-property-localization (pair P H) X (pair Y p) l =
is-equiv (λ (h : Y → X) → h ∘ l)
retraction-property-localization :
{l1 l2 : Level} (P : subuniverse l1 l2) (X : UU l1) →
(Y : total-subuniverse P) (l : X → pr1 Y) → UU l1
retraction-property-localization (pair P H) X (pair Y p) l =
retr l
strong-retraction-property-localization-is-equiv-localization :
{l1 l2 : Level} (P : subuniverse l1 l2) (X : UU l1) →
(Y : total-subuniverse P) (l : X → pr1 Y) →
is-equiv l → strong-retraction-property-localization P X Y l
strong-retraction-property-localization-is-equiv-localization
(pair P H) X (pair Y p) l is-equiv-l =
is-equiv-precomp-is-equiv l is-equiv-l X
retraction-property-localization-strong-retraction-property-localization :
{l1 l2 : Level} (P : subuniverse l1 l2) (X : UU l1) →
(Y : total-subuniverse P) (l : X → pr1 Y) →
strong-retraction-property-localization P X Y l →
retraction-property-localization P X Y l
retraction-property-localization-strong-retraction-property-localization
(pair P H) X (pair Y p) l s =
tot (λ h → htpy-eq) (center (is-contr-map-is-equiv s id))
is-equiv-localization-retraction-property-localization :
{l1 l2 : Level} (P : subuniverse l1 l2) (X : UU l1) →
(Y : has-localization P X) →
retraction-property-localization P X (pr1 Y) (pr1 (pr2 Y)) →
is-equiv (pr1 (pr2 Y))
is-equiv-localization-retraction-property-localization
(pair P H) X (pair (pair Y p) (pair l up)) (pair g isretr-g) =
is-equiv-has-inverse
( pair g
( pair
( htpy-eq
( ap
( pr1 {B = λ (h : Y → Y) → Id (h ∘ l) l})
( center
( is-prop-is-contr
( is-contr-map-is-equiv (up Y p) l)
( pair (l ∘ g) (ap (λ t → l ∘ t) (eq-htpy isretr-g)))
( pair id refl)))))
( isretr-g)))
is-local-retraction-property-localization :
{l1 l2 : Level} (P : subuniverse l1 l2) (X : UU l1) →
(Y : has-localization P X) →
retraction-property-localization P X (pr1 Y) (pr1 (pr2 Y)) →
(pr1 P) X
is-local-retraction-property-localization P X Y r =
is-local-is-equiv-localization P X Y
( is-equiv-localization-retraction-property-localization P X Y r)
is-local-has-localization-is-contr :
{l1 l2 : Level} (P : subuniverse l1 l2) (X : UU l1) →
is-contr X → has-localization P X → (pr1 P) X
is-local-has-localization-is-contr
(pair P H) X is-contr-X (pair (pair Y p) (pair l up)) =
is-local-retraction-property-localization (pair P H) X
( pair (pair Y p) (pair l up))
( pair
( λ _ → center is-contr-X)
( contraction is-contr-X))
has-localization-is-local-is-contr :
{l1 l2 : Level} (P : subuniverse l1 l2) (X : UU l1) →
is-contr X → (pr1 P) X → has-localization P X
has-localization-is-local-is-contr (pair P H) X is-contr-X p =
pair
( pair X p)
( pair id (universal-property-localization-id-is-local (pair P H) X p))
is-contr-raise-unit :
(l : Level) → is-contr (raise l unit)
is-contr-raise-unit l =
is-contr-is-equiv' unit
( map-raise l unit)
( is-equiv-map-raise l unit)
( is-contr-unit)
is-local-unit-localization-unit :
{l1 l2 : Level} (P : subuniverse l1 l2) →
(Y : has-localization P (raise l1 unit)) →
(pr1 P) (raise l1 unit)
is-local-unit-localization-unit P Y =
is-local-has-localization-is-contr P (raise _ unit) (is-contr-raise-unit _) Y
toto-dependent-elimination-localization :
{l1 l2 : Level} (P : subuniverse l1 l2) (X : UU l1) →
(has-loc-X : has-localization P X) →
let Y = pr1 (pr1 has-loc-X)
l = pr1 (pr2 has-loc-X)
in
(Z : Y → UU l1) →
Σ (Y → Y) (λ h → (y : Y) → Z (h y)) →
Σ (X → Y) (λ h → (x : X) → Z (h x))
toto-dependent-elimination-localization (pair P H) X
(pair (pair Y p) (pair l up)) Z =
toto
( λ (h : X → Y) → (x : X) → Z (h x))
( λ h → h ∘ l)
( λ h h' x → h' (l x))
square-dependent-elimination-localization :
{l1 l2 : Level} (P : subuniverse l1 l2) (X : UU l1) →
(has-loc-X : has-localization P X) →
let Y = pr1 (pr1 has-loc-X)
l = pr1 (pr2 has-loc-X)
in
(Z : Y → UU l1) (q : (pr1 P) (Σ _ Z)) →
( ( λ (h : Y → Σ Y Z) → h ∘ l) ∘
( inv-choice-∞)) ~
( ( inv-choice-∞) ∘
( toto-dependent-elimination-localization P X has-loc-X Z))
square-dependent-elimination-localization
(pair P H) X (pair (pair Y p) (pair l up)) Z q =
htpy-refl
is-equiv-toto-dependent-elimination-localization :
{l1 l2 : Level} (P : subuniverse l1 l2) (X : UU l1) →
(has-loc-X : has-localization P X)
(Z : pr1 (pr1 has-loc-X) → UU l1) (q : (pr1 P) (Σ _ Z)) →
is-equiv (toto-dependent-elimination-localization P X has-loc-X Z)
is-equiv-toto-dependent-elimination-localization
(pair P H) X (pair (pair Y p) (pair l up)) Z q =
is-equiv-top-is-equiv-bottom-square
( inv-choice-∞)
( inv-choice-∞)
( toto-dependent-elimination-localization
(pair P H) X (pair (pair Y p) (pair l up)) Z)
( λ h → h ∘ l)
( square-dependent-elimination-localization
(pair P H) X (pair (pair Y p) (pair l up)) Z q)
( is-equiv-inv-choice-∞)
( is-equiv-inv-choice-∞)
( up (Σ Y Z) q)
dependent-elimination-localization :
{l1 l2 : Level} (P : subuniverse l1 l2) →
(X : UU l1) (Y : has-localization P X) →
(Z : (pr1 (pr1 Y)) → UU l1) (q : (pr1 P) (Σ _ Z)) →
is-equiv (λ (h : (y : (pr1 (pr1 Y))) → (Z y)) → λ x → h (pr1 (pr2 Y) x))
dependent-elimination-localization (pair P H) X (pair (pair Y p) (pair l up)) Z q =
is-fiberwise-equiv-is-equiv-toto-is-equiv-base-map
( λ (h : X → Y) → (x : X) → Z (h x))
( λ (h : Y → Y) → h ∘ l)
( λ (h : Y → Y) (h' : (y : Y) → Z (h y)) (x : X) → h' (l x))
( up Y p)
( is-equiv-toto-dependent-elimination-localization
(pair P H) X (pair (pair Y p) (pair l up)) Z q)
( id)
is-reflective-subuniverse :
{l1 l2 : Level} (P : subuniverse l1 l2) → UU ((lsuc l1) ⊔ l2)
is-reflective-subuniverse {l1} P = (X : UU l1) → has-localization P X
reflective-subuniverse :
(l1 l2 : Level) → UU ((lsuc l1) ⊔ (lsuc l2))
reflective-subuniverse l1 l2 = Σ (subuniverse l1 l2) is-reflective-subuniverse
is-local :
{l1 l2 : Level} (L : reflective-subuniverse l1 l2) →
UU l1 → UU l2
is-local L = pr1 (pr1 L)
is-prop-is-local :
{l1 l2 : Level} (L : reflective-subuniverse l1 l2) →
(X : UU l1) → is-prop (is-local L X)
is-prop-is-local L = pr2 (pr1 L)
total-reflective-subuniverse :
{l1 l2 : Level} (L : reflective-subuniverse l1 l2) → UU ((lsuc l1) ⊔ l2)
total-reflective-subuniverse L = total-subuniverse (pr1 L)
local-type-localization :
{l1 l2 : Level} (L : reflective-subuniverse l1 l2)
(X : UU l1) → total-reflective-subuniverse L
local-type-localization L X = pr1 ((pr2 L) X)
type-localization :
{l1 l2 : Level} (L : reflective-subuniverse l1 l2) →
UU l1 → UU l1
type-localization L X = pr1 (local-type-localization L X)
is-local-type-localization :
{l1 l2 : Level} (L : reflective-subuniverse l1 l2)
(X : UU l1) → is-local L (type-localization L X)
is-local-type-localization L X = pr2 (local-type-localization L X)
universal-map-localization :
{l1 l2 : Level} (L : reflective-subuniverse l1 l2) (X : UU l1) →
Σ ( X → type-localization L X)
( universal-property-localization (pr1 L) X (local-type-localization L X))
universal-map-localization L X = pr2 ((pr2 L) X)
unit-localization :
{l1 l2 : Level} (L : reflective-subuniverse l1 l2)
(X : UU l1) → X → type-localization L X
unit-localization L X = pr1 (universal-map-localization L X)
universal-property-map-localization :
{l1 l2 : Level} (L : reflective-subuniverse l1 l2) (X : UU l1) →
universal-property-localization (pr1 L) X
( local-type-localization L X)
( unit-localization L X)
universal-property-map-localization L X = pr2 (universal-map-localization L X)
dependent-elimination-reflective-subuniverse :
{l1 l2 : Level} (L : reflective-subuniverse l1 l2) (X : UU l1) →
(Y : type-localization L X → UU l1)
(is-loc-total-Y : is-local L (Σ _ Y)) →
is-equiv
( λ (h : (x' : type-localization L X) → Y x') x → h (unit-localization L X x))
dependent-elimination-reflective-subuniverse L X =
dependent-elimination-localization (pr1 L) X ((pr2 L) X)
is-contr-square-localization :
{l1 l2 : Level} (L : reflective-subuniverse l1 l2) {X Y : UU l1} (f : X → Y) →
is-contr
( Σ (type-localization L X → type-localization L Y)
( λ Lf → coherence-square (unit-localization L X) f Lf (unit-localization L Y)))
is-contr-square-localization L f = {!!}
|
oeis/247/A247560.asm | neoneye/loda-programs | 11 | 102481 | <gh_stars>10-100
; A247560: a(n) = 3*a(n-1) - 4*a(n-2) with a(0) = a(1) = 1.
; 1,1,-1,-7,-17,-23,-1,89,271,457,287,-967,-4049,-8279,-8641,7193,56143,139657,194399,24569,-703889,-2209943,-3814273,-2603047,7447951,32756041,68476319,74404793,-50690897,-449691863,-1146312001,-1640168551,-335257649,5554901257,18005734367,31797598073,23369856751,-57080822039,-264721893121,-565842391207,-638639601137,347450761417,3596910688799,9400929020729,13815144306991,3841716838057,-43735426713793,-146573147493607,-264777735625649,-208040616902519,434989091795039,2137129742995193
mov $1,1
mov $2,1
lpb $0
sub $0,1
sub $2,$1
mul $2,2
add $1,$2
mul $2,2
lpe
mov $0,$1
|
src/compiling/ANTLR/grammar/ProceduralBlocksAndAssignments.g4 | jecassis/VSCode-SystemVerilog | 75 | 4643 | grammar ProceduralBlocksAndAssignments;
import ParallelAndSequentialBlocks;
initial_construct : 'initial' statement_or_null ;
always_construct : always_keyword statement ;
always_keyword : 'always' | 'always_comb' | 'always_latch' | 'always_ff' ;
final_construct : 'final' function_statement ;
blocking_assignment : variable_lvalue '=' delay_or_event_control expression
| nonrange_variable_lvalue '=' dynamic_array_new
| ( implicit_class_handle '.' | class_scope | package_scope )? hierarchical_variable_identifier
select '=' class_new
| operator_assignment ;
operator_assignment : variable_lvalue assignment_operator expression ;
assignment_operator : '=' | '+=' | '-=' | '*=' | '/=' | '%=' | '&=' | '|=' | '^=' | '<<=' | '>>='
| '<<<=' | '>>>=' ;
nonblocking_assignment : variable_lvalue '<=' ( delay_or_event_control )? expression ;
procedural_continuous_assignment : 'assign' variable_assignment
| 'deassign' variable_lvalue
| 'force' variable_assignment
| 'force' net_assignment
| 'release' variable_lvalue
| 'release' net_lvalue ;
variable_assignment : variable_lvalue '=' expression ;
|
src/main/antlr4/com/navelplace/jsemver/antlr/Ruby.g4 | BrianDeacon/JSemver | 0 | 5487 | grammar Ruby;
clauses: clause (COMMA clause)* EOF ;
clause: WS* (singleQuote unquotedClause singleQuote) WS* | WS* unquotedClause WS* ;
singleQuote: SINGLE_QUOTE ;
unquotedClause: operator? WS* version ;
operator: OPERATOR ;
version: major (DOT minor (DOT patch)?)? ;
major: VERSION_ELEMENT ;
minor: VERSION_ELEMENT ;
patch: VERSION_ELEMENT ;
VERSION_ELEMENT: ZERO | NON_ZERO (NUMBER)* ;
NON_ZERO: '1'..'9' ;
ZERO: '0' ;
NUMBER: ZERO | NON_ZERO ;
OPERATOR: SIMPLE_OPERATOR | TWIDDLE_WAKA ;
fragment TWIDDLE_WAKA: TILDE GT ;
fragment SIMPLE_OPERATOR: GTEQ | LTEQ | LT | GT | EQ ;
fragment LTEQ: LT EQ ;
fragment GTEQ: GT EQ ;
fragment LT: '<' ;
fragment GT: '>' ;
fragment EQ: '=' ;
fragment TILDE: '~' ;
DOT: '.' ;
COMMA: ',' ;
SINGLE_QUOTE: '\'';
WS : [\t ]+;
|
examples/example-2.asm | Ruben-Sten/PP2LAL2PP | 1 | 511 | ;#
;# Example file of how a PP2LAL2PP language file looks like.
;# This is a descriptive doc comment
;#
@CODE
IOAREA EQU -16 ; Address of the I/O-Area, modulo 2^18.
INPUT EQU 7 ; Position of the input buttons (relative to IOAREA).
OUTPUT EQU 11 ; Relative position of the power outputs.
DSPDIG EQU 9 ; Relative position of the 7-segment display's digit selector.
DSPSEG EQU 8 ; Relative position of the 7-segment display's segments.
TIMER EQU 13 ; Timer address relative to IOAREA.
ADCONV EQU 6 ; A/D-converter address relative to IOAREA.
MAGIC_VALUE EQU 42 ; Include contents of const.pp2 or const.pp2lal2pp
DISPLAY_MAX EQU 16 ; Other constants
countOne EQU 1 ; Global variables. Variables will initialise to 0 when nothing is declared.
countTwo EQU 2 ; Global variables. Variables will initialise to 0 when nothing is declared.
previousState EQU 3 ; Global variables. Variables will initialise to 0 when nothing is declared.
currentState EQU 4 ; Global variables. Variables will initialise to 0 when nothing is declared.
;#
;# Initialisation of the program.
;#
init: LOAD R5 IOAREA ; Store the address of the IOAREA for later use.
LOAD R0 0 ; Default value to load in global base.
STOR R0 [GB+countOne] ; Give global variable countOne initial value 0.
STOR R0 [GB+countTwo] ; Give global variable countTwo initial value 0.
STOR R0 [GB+previousState] ; Give global variable previousState initial value 0.
STOR R0 [GB+currentState] ; Give global variable currentState initial value 0.
;#
;# Main loop that continuously executes until exit() is called or the machine gets
;# shut down.
;#
main: LOAD R0 [GB+currentState] ; Mark the current state as old {previousState = currentState}
STOR R0 [GB+previousState] ; >
BRS getButtonState ; Call function getButtonState.
PUSH R4 ; Update LEDs to accomodate the new buttons states {declare buttonState}
LOAD R0 [SP+0] ; Load the value of variable buttonState.
PUSH R0 ; Push the value onto the stack.
BRS setLEDs ; Call function setLEDs.
ADD SP 1 ; Reset the stack pointer position.
LOAD R0 [SP+0] ; Isolate the last 2 buttons {currentState = (buttonState & 3)}
AND R0 3 ; >
STOR R0 [GB+currentState] ; >
LOAD R0 0 ; Determine what button has been pressed. {declare button}
PUSH R0 ; Save the initial value of button.
LOAD R0 [GB+previousState] ; Check if previousState != 3 (if-statement #52).
CMP R0 3 ; >
BNE if52_true ; Branch to if-block when previousState != 3.
BRA if52_end ; Skip the if-block.
if52_true: LOAD R0 [GB+previousState] ; Operation button = (previousState ^ currentState).
XOR R0 [GB+currentState] ; >
STOR R0 [SP+0] ; >
if52_end: LOAD R0 0 ; Dummy instruction to always make the label work.
LOAD R0 0 ; Inject raw assembly
LOAD R0 [GB+countOne] ; Makes sure the counters don't exceed the display maximum. {countOne %= DISPLAY_MAX}
MOD R0 DISPLAY_MAX ; >
STOR R0 [GB+countOne] ; >
LOAD R0 [GB+countTwo] ; Operation countTwo %= DISPLAY_MAX.
MOD R0 DISPLAY_MAX ; >
STOR R0 [GB+countTwo] ; >
LOAD R0 [SP+0] ; Display the right counters
CMP R0 1 ; Check if button == 1 (if-statement #71).
BEQ if71_true ; Branch to if-block when button == 1.
LOAD R0 [SP+0] ; Display the right counters
CMP R0 2 ; Check if button == 2 (if-statement #69).
BEQ if69_true ; Branch to if-block when button == 2.
BRA if69_end ; Skip the if-block.
if69_true: LOAD R3 2 ; Load the index of the display on the 7Segment display.
LOAD R0 [GB+countTwo] ; Load the value to display on the 7Segment display.
BRS set7Segment ; Call function set7Segment.
if69_end: LOAD R0 0 ; Dummy instruction to always make the label work.
BRA if71_end ; Skip the if-block.
if71_true: LOAD R3 1 ; Load the index of the display on the 7Segment display.
LOAD R0 [GB+countOne] ; Load the value to display on the 7Segment display.
BRS set7Segment ; Call function set7Segment.
if71_end: LOAD R0 0 ; Dummy instruction to always make the label work.
ADD SP 2 ; Reset stack pointer.
BRA main ; Repeat function main.
;#
;# Routine Hex7Seg maps a number in the range [0..15] to its hexadecimal
;# representation pattern for the 7-segment display.
;# R0 : upon entry, contains the number
;# R1 : upon exit, contains the resulting pattern
;#
Hex7Seg: BRS Hex7Seg_bgn ; Push address(tbl) onto stack and proceed at "bgn".
Hex7Seg_tbl: CONS %01111110 ; 7-segment pattern for '0'.
CONS %00110000 ; 7-segment pattern for '1'.
CONS %01101101 ; 7-segment pattern for '2'.
CONS %01111001 ; 7-segment pattern for '3'.
CONS %00110011 ; 7-segment pattern for '4'.
CONS %01011011 ; 7-segment pattern for '5'.
CONS %01011111 ; 7-segment pattern for '6'.
CONS %01110000 ; 7-segment pattern for '7'.
CONS %01111111 ; 7-segment pattern for '8'.
CONS %01111011 ; 7-segment pattern for '9'.
CONS %01110111 ; 7-segment pattern for 'A'.
CONS %00011111 ; 7-segment pattern for 'b'.
CONS %01001110 ; 7-segment pattern for 'C'.
CONS %00111101 ; 7-segment pattern for 'd'.
CONS %01001111 ; 7-segment pattern for 'E'.
CONS %01000111 ; 7-segment pattern for 'F'.
Hex7Seg_bgn: AND R0 %01111 ; R0 := R0 MOD 16 , just to be safe...
LOAD R1 [SP++] ; R1 = address(tbl) (retrieve from stack)
LOAD R1 [R1+R0] ; R1 = tbl[R0]
RTS
;#
;# Set the value of a digit on the 7 Segment-display.
;# R0 : upon entry, contains the number to display.
;# R3 : upon entry, contains the index of the display.
;#
set7Segment: BRS Hex7Seg ; Translate (value in) R0 into a display pattern.
STOR R1 [R5+DSPSEG] ; And place this in the Display Element.
STOR R3 [R5+DSPDIG] ; Activate Display Element #0.
RTS ; Exit set7Segment function.
@END |
SVD2ada/svd/stm32_svd-ethernet.ads | JCGobbi/Nucleo-STM32H743ZI | 0 | 29354 | pragma Style_Checks (Off);
-- This spec has been automatically generated from STM32H743x.svd
pragma Restrictions (No_Elaboration_Code);
with HAL;
with System;
package STM32_SVD.Ethernet is
pragma Preelaborate;
---------------
-- Registers --
---------------
subtype DMAMR_PR_Field is HAL.UInt3;
-- DMA mode register
type DMAMR_Register is record
-- Software Reset
SWR : Boolean := False;
-- Read-only. DMA Tx or Rx Arbitration Scheme
DA : Boolean := False;
-- unspecified
Reserved_2_10 : HAL.UInt9 := 16#0#;
-- Read-only. Transmit priority
TXPR : Boolean := False;
-- Read-only. Priority ratio
PR : DMAMR_PR_Field := 16#0#;
-- unspecified
Reserved_15_15 : HAL.Bit := 16#0#;
-- Interrupt Mode
INTM : Boolean := False;
-- unspecified
Reserved_17_31 : HAL.UInt15 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for DMAMR_Register use record
SWR at 0 range 0 .. 0;
DA at 0 range 1 .. 1;
Reserved_2_10 at 0 range 2 .. 10;
TXPR at 0 range 11 .. 11;
PR at 0 range 12 .. 14;
Reserved_15_15 at 0 range 15 .. 15;
INTM at 0 range 16 .. 16;
Reserved_17_31 at 0 range 17 .. 31;
end record;
-- System bus mode register
type DMASBMR_Register is record
-- Fixed Burst Length
FB : Boolean := False;
-- unspecified
Reserved_1_11 : HAL.UInt11 := 16#0#;
-- Address-Aligned Beats
AAL : Boolean := False;
-- unspecified
Reserved_13_13 : HAL.Bit := 16#0#;
-- Read-only. Mixed Burst
MB : Boolean := False;
-- Read-only. Rebuild INCRx Burst
RB : Boolean := False;
-- unspecified
Reserved_16_31 : HAL.UInt16 := 16#101#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for DMASBMR_Register use record
FB at 0 range 0 .. 0;
Reserved_1_11 at 0 range 1 .. 11;
AAL at 0 range 12 .. 12;
Reserved_13_13 at 0 range 13 .. 13;
MB at 0 range 14 .. 14;
RB at 0 range 15 .. 15;
Reserved_16_31 at 0 range 16 .. 31;
end record;
-- Interrupt status register
type DMAISR_Register is record
-- Read-only. DMA Channel Interrupt Status
DC0IS : Boolean;
-- unspecified
Reserved_1_15 : HAL.UInt15;
-- Read-only. MTL Interrupt Status
MTLIS : Boolean;
-- Read-only. MAC Interrupt Status
MACIS : Boolean;
-- unspecified
Reserved_18_31 : HAL.UInt14;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for DMAISR_Register use record
DC0IS at 0 range 0 .. 0;
Reserved_1_15 at 0 range 1 .. 15;
MTLIS at 0 range 16 .. 16;
MACIS at 0 range 17 .. 17;
Reserved_18_31 at 0 range 18 .. 31;
end record;
subtype DMADSR_RPS0_Field is HAL.UInt4;
subtype DMADSR_TPS0_Field is HAL.UInt4;
-- Debug status register
type DMADSR_Register is record
-- Read-only. AHB Master Write Channel
AXWHSTS : Boolean;
-- unspecified
Reserved_1_7 : HAL.UInt7;
-- Read-only. DMA Channel Receive Process State
RPS0 : DMADSR_RPS0_Field;
-- Read-only. DMA Channel Transmit Process State
TPS0 : DMADSR_TPS0_Field;
-- unspecified
Reserved_16_31 : HAL.UInt16;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for DMADSR_Register use record
AXWHSTS at 0 range 0 .. 0;
Reserved_1_7 at 0 range 1 .. 7;
RPS0 at 0 range 8 .. 11;
TPS0 at 0 range 12 .. 15;
Reserved_16_31 at 0 range 16 .. 31;
end record;
subtype DMACCR_MSS_Field is HAL.UInt14;
subtype DMACCR_DSL_Field is HAL.UInt3;
-- Channel control register
type DMACCR_Register is record
-- Maximum Segment Size
MSS : DMACCR_MSS_Field := 16#0#;
-- unspecified
Reserved_14_15 : HAL.UInt2 := 16#0#;
-- 8xPBL mode
PBLX8 : Boolean := False;
-- unspecified
Reserved_17_17 : HAL.Bit := 16#0#;
-- Descriptor Skip Length
DSL : DMACCR_DSL_Field := 16#0#;
-- unspecified
Reserved_21_31 : HAL.UInt11 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for DMACCR_Register use record
MSS at 0 range 0 .. 13;
Reserved_14_15 at 0 range 14 .. 15;
PBLX8 at 0 range 16 .. 16;
Reserved_17_17 at 0 range 17 .. 17;
DSL at 0 range 18 .. 20;
Reserved_21_31 at 0 range 21 .. 31;
end record;
subtype DMACTxCR_TXPBL_Field is HAL.UInt6;
-- Channel transmit control register
type DMACTxCR_Register is record
-- Start or Stop Transmission Command
ST : Boolean := False;
-- unspecified
Reserved_1_3 : HAL.UInt3 := 16#0#;
-- Operate on Second Packet
OSF : Boolean := False;
-- unspecified
Reserved_5_11 : HAL.UInt7 := 16#0#;
-- TCP Segmentation Enabled
TSE : Boolean := False;
-- unspecified
Reserved_13_15 : HAL.UInt3 := 16#0#;
-- Transmit Programmable Burst Length
TXPBL : DMACTxCR_TXPBL_Field := 16#0#;
-- unspecified
Reserved_22_31 : HAL.UInt10 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for DMACTxCR_Register use record
ST at 0 range 0 .. 0;
Reserved_1_3 at 0 range 1 .. 3;
OSF at 0 range 4 .. 4;
Reserved_5_11 at 0 range 5 .. 11;
TSE at 0 range 12 .. 12;
Reserved_13_15 at 0 range 13 .. 15;
TXPBL at 0 range 16 .. 21;
Reserved_22_31 at 0 range 22 .. 31;
end record;
subtype DMACRxCR_RBSZ_Field is HAL.UInt14;
subtype DMACRxCR_RXPBL_Field is HAL.UInt6;
-- Channel receive control register
type DMACRxCR_Register is record
-- Start or Stop Receive Command
SR : Boolean := False;
-- Receive Buffer size
RBSZ : DMACRxCR_RBSZ_Field := 16#0#;
-- unspecified
Reserved_15_15 : HAL.Bit := 16#0#;
-- RXPBL
RXPBL : DMACRxCR_RXPBL_Field := 16#0#;
-- unspecified
Reserved_22_30 : HAL.UInt9 := 16#0#;
-- DMA Rx Channel Packet Flush
RPF : Boolean := False;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for DMACRxCR_Register use record
SR at 0 range 0 .. 0;
RBSZ at 0 range 1 .. 14;
Reserved_15_15 at 0 range 15 .. 15;
RXPBL at 0 range 16 .. 21;
Reserved_22_30 at 0 range 22 .. 30;
RPF at 0 range 31 .. 31;
end record;
subtype DMACTxDLAR_TDESLA_Field is HAL.UInt30;
-- Channel Tx descriptor list address register
type DMACTxDLAR_Register is record
-- unspecified
Reserved_0_1 : HAL.UInt2 := 16#0#;
-- Start of Transmit List
TDESLA : DMACTxDLAR_TDESLA_Field := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for DMACTxDLAR_Register use record
Reserved_0_1 at 0 range 0 .. 1;
TDESLA at 0 range 2 .. 31;
end record;
subtype DMACRxDLAR_RDESLA_Field is HAL.UInt30;
-- Channel Rx descriptor list address register
type DMACRxDLAR_Register is record
-- unspecified
Reserved_0_1 : HAL.UInt2 := 16#0#;
-- Start of Receive List
RDESLA : DMACRxDLAR_RDESLA_Field := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for DMACRxDLAR_Register use record
Reserved_0_1 at 0 range 0 .. 1;
RDESLA at 0 range 2 .. 31;
end record;
subtype DMACTxDTPR_TDT_Field is HAL.UInt30;
-- Channel Tx descriptor tail pointer register
type DMACTxDTPR_Register is record
-- unspecified
Reserved_0_1 : HAL.UInt2 := 16#0#;
-- Transmit Descriptor Tail Pointer
TDT : DMACTxDTPR_TDT_Field := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for DMACTxDTPR_Register use record
Reserved_0_1 at 0 range 0 .. 1;
TDT at 0 range 2 .. 31;
end record;
subtype DMACRxDTPR_RDT_Field is HAL.UInt30;
-- Channel Rx descriptor tail pointer register
type DMACRxDTPR_Register is record
-- unspecified
Reserved_0_1 : HAL.UInt2 := 16#0#;
-- Receive Descriptor Tail Pointer
RDT : DMACRxDTPR_RDT_Field := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for DMACRxDTPR_Register use record
Reserved_0_1 at 0 range 0 .. 1;
RDT at 0 range 2 .. 31;
end record;
subtype DMACTxRLR_TDRL_Field is HAL.UInt10;
-- Channel Tx descriptor ring length register
type DMACTxRLR_Register is record
-- Transmit Descriptor Ring Length
TDRL : DMACTxRLR_TDRL_Field := 16#0#;
-- unspecified
Reserved_10_31 : HAL.UInt22 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for DMACTxRLR_Register use record
TDRL at 0 range 0 .. 9;
Reserved_10_31 at 0 range 10 .. 31;
end record;
subtype DMACRxRLR_RDRL_Field is HAL.UInt10;
-- Channel Rx descriptor ring length register
type DMACRxRLR_Register is record
-- Receive Descriptor Ring Length
RDRL : DMACRxRLR_RDRL_Field := 16#0#;
-- unspecified
Reserved_10_31 : HAL.UInt22 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for DMACRxRLR_Register use record
RDRL at 0 range 0 .. 9;
Reserved_10_31 at 0 range 10 .. 31;
end record;
-- Channel interrupt enable register
type DMACIER_Register is record
-- Transmit Interrupt Enable
TIE : Boolean := False;
-- Transmit Stopped Enable
TXSE : Boolean := False;
-- Transmit Buffer Unavailable Enable
TBUE : Boolean := False;
-- unspecified
Reserved_3_5 : HAL.UInt3 := 16#0#;
-- Receive Interrupt Enable
RIE : Boolean := False;
-- Receive Buffer Unavailable Enable
RBUE : Boolean := False;
-- Receive Stopped Enable
RSE : Boolean := False;
-- Receive Watchdog Timeout Enable
RWTE : Boolean := False;
-- Early Transmit Interrupt Enable
ETIE : Boolean := False;
-- Early Receive Interrupt Enable
ERIE : Boolean := False;
-- Fatal Bus Error Enable
FBEE : Boolean := False;
-- Context Descriptor Error Enable
CDEE : Boolean := False;
-- Abnormal Interrupt Summary Enable
AIE : Boolean := False;
-- Normal Interrupt Summary Enable
NIE : Boolean := False;
-- unspecified
Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for DMACIER_Register use record
TIE at 0 range 0 .. 0;
TXSE at 0 range 1 .. 1;
TBUE at 0 range 2 .. 2;
Reserved_3_5 at 0 range 3 .. 5;
RIE at 0 range 6 .. 6;
RBUE at 0 range 7 .. 7;
RSE at 0 range 8 .. 8;
RWTE at 0 range 9 .. 9;
ETIE at 0 range 10 .. 10;
ERIE at 0 range 11 .. 11;
FBEE at 0 range 12 .. 12;
CDEE at 0 range 13 .. 13;
AIE at 0 range 14 .. 14;
NIE at 0 range 15 .. 15;
Reserved_16_31 at 0 range 16 .. 31;
end record;
subtype DMACRxIWTR_RWT_Field is HAL.UInt8;
-- Channel Rx interrupt watchdog timer register
type DMACRxIWTR_Register is record
-- Receive Interrupt Watchdog Timer Count
RWT : DMACRxIWTR_RWT_Field := 16#0#;
-- unspecified
Reserved_8_31 : HAL.UInt24 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for DMACRxIWTR_Register use record
RWT at 0 range 0 .. 7;
Reserved_8_31 at 0 range 8 .. 31;
end record;
subtype DMACSR_TEB_Field is HAL.UInt3;
subtype DMACSR_REB_Field is HAL.UInt3;
-- Channel status register
type DMACSR_Register is record
-- Transmit Interrupt
TI : Boolean := False;
-- Transmit Process Stopped
TPS : Boolean := False;
-- Transmit Buffer Unavailable
TBU : Boolean := False;
-- unspecified
Reserved_3_5 : HAL.UInt3 := 16#0#;
-- Receive Interrupt
RI : Boolean := False;
-- Receive Buffer Unavailable
RBU : Boolean := False;
-- Receive Process Stopped
RPS : Boolean := False;
-- Receive Watchdog Timeout
RWT : Boolean := False;
-- Early Transmit Interrupt
ET : Boolean := False;
-- Early Receive Interrupt
ER : Boolean := False;
-- Fatal Bus Error
FBE : Boolean := False;
-- Context Descriptor Error
CDE : Boolean := False;
-- Abnormal Interrupt Summary
AIS : Boolean := False;
-- Normal Interrupt Summary
NIS : Boolean := False;
-- Read-only. Tx DMA Error Bits
TEB : DMACSR_TEB_Field := 16#0#;
-- Read-only. Rx DMA Error Bits
REB : DMACSR_REB_Field := 16#0#;
-- unspecified
Reserved_22_31 : HAL.UInt10 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for DMACSR_Register use record
TI at 0 range 0 .. 0;
TPS at 0 range 1 .. 1;
TBU at 0 range 2 .. 2;
Reserved_3_5 at 0 range 3 .. 5;
RI at 0 range 6 .. 6;
RBU at 0 range 7 .. 7;
RPS at 0 range 8 .. 8;
RWT at 0 range 9 .. 9;
ET at 0 range 10 .. 10;
ER at 0 range 11 .. 11;
FBE at 0 range 12 .. 12;
CDE at 0 range 13 .. 13;
AIS at 0 range 14 .. 14;
NIS at 0 range 15 .. 15;
TEB at 0 range 16 .. 18;
REB at 0 range 19 .. 21;
Reserved_22_31 at 0 range 22 .. 31;
end record;
subtype DMACMFCR_MFC_Field is HAL.UInt11;
-- Channel missed frame count register
type DMACMFCR_Register is record
-- Read-only. Dropped Packet Counters
MFC : DMACMFCR_MFC_Field;
-- unspecified
Reserved_11_14 : HAL.UInt4;
-- Read-only. Overflow status of the MFC Counter
MFCO : Boolean;
-- unspecified
Reserved_16_31 : HAL.UInt16;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for DMACMFCR_Register use record
MFC at 0 range 0 .. 10;
Reserved_11_14 at 0 range 11 .. 14;
MFCO at 0 range 15 .. 15;
Reserved_16_31 at 0 range 16 .. 31;
end record;
subtype MACCR_PRELEN_Field is HAL.UInt2;
subtype MACCR_BL_Field is HAL.UInt2;
subtype MACCR_IPG_Field is HAL.UInt3;
subtype MACCR_SARC_Field is HAL.UInt3;
-- Operating mode configuration register
type MACCR_Register is record
-- Receiver Enable
RE : Boolean := False;
-- TE
TE : Boolean := False;
-- PRELEN
PRELEN : MACCR_PRELEN_Field := 16#0#;
-- DC
DC : Boolean := False;
-- BL
BL : MACCR_BL_Field := 16#0#;
-- unspecified
Reserved_7_7 : HAL.Bit := 16#0#;
-- DR
DR : Boolean := False;
-- DCRS
DCRS : Boolean := False;
-- DO
DO_k : Boolean := False;
-- ECRSFD
ECRSFD : Boolean := False;
-- LM
LM : Boolean := False;
-- DM
DM : Boolean := False;
-- FES
FES : Boolean := False;
-- unspecified
Reserved_15_15 : HAL.Bit := 16#0#;
-- JE
JE : Boolean := False;
-- JD
JD : Boolean := False;
-- unspecified
Reserved_18_18 : HAL.Bit := 16#0#;
-- WD
WD : Boolean := False;
-- ACS
ACS : Boolean := False;
-- CST
CST : Boolean := False;
-- S2KP
S2KP : Boolean := False;
-- GPSLCE
GPSLCE : Boolean := False;
-- IPG
IPG : MACCR_IPG_Field := 16#0#;
-- IPC
IPC : Boolean := False;
-- SARC
SARC : MACCR_SARC_Field := 16#0#;
-- ARPEN
ARPEN : Boolean := False;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACCR_Register use record
RE at 0 range 0 .. 0;
TE at 0 range 1 .. 1;
PRELEN at 0 range 2 .. 3;
DC at 0 range 4 .. 4;
BL at 0 range 5 .. 6;
Reserved_7_7 at 0 range 7 .. 7;
DR at 0 range 8 .. 8;
DCRS at 0 range 9 .. 9;
DO_k at 0 range 10 .. 10;
ECRSFD at 0 range 11 .. 11;
LM at 0 range 12 .. 12;
DM at 0 range 13 .. 13;
FES at 0 range 14 .. 14;
Reserved_15_15 at 0 range 15 .. 15;
JE at 0 range 16 .. 16;
JD at 0 range 17 .. 17;
Reserved_18_18 at 0 range 18 .. 18;
WD at 0 range 19 .. 19;
ACS at 0 range 20 .. 20;
CST at 0 range 21 .. 21;
S2KP at 0 range 22 .. 22;
GPSLCE at 0 range 23 .. 23;
IPG at 0 range 24 .. 26;
IPC at 0 range 27 .. 27;
SARC at 0 range 28 .. 30;
ARPEN at 0 range 31 .. 31;
end record;
subtype MACECR_GPSL_Field is HAL.UInt14;
subtype MACECR_EIPG_Field is HAL.UInt5;
-- Extended operating mode configuration register
type MACECR_Register is record
-- GPSL
GPSL : MACECR_GPSL_Field := 16#0#;
-- unspecified
Reserved_14_15 : HAL.UInt2 := 16#0#;
-- DCRCC
DCRCC : Boolean := False;
-- SPEN
SPEN : Boolean := False;
-- USP
USP : Boolean := False;
-- unspecified
Reserved_19_23 : HAL.UInt5 := 16#0#;
-- EIPGEN
EIPGEN : Boolean := False;
-- EIPG
EIPG : MACECR_EIPG_Field := 16#0#;
-- unspecified
Reserved_30_31 : HAL.UInt2 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACECR_Register use record
GPSL at 0 range 0 .. 13;
Reserved_14_15 at 0 range 14 .. 15;
DCRCC at 0 range 16 .. 16;
SPEN at 0 range 17 .. 17;
USP at 0 range 18 .. 18;
Reserved_19_23 at 0 range 19 .. 23;
EIPGEN at 0 range 24 .. 24;
EIPG at 0 range 25 .. 29;
Reserved_30_31 at 0 range 30 .. 31;
end record;
subtype MACPFR_PCF_Field is HAL.UInt2;
-- Packet filtering control register
type MACPFR_Register is record
-- PR
PR : Boolean := False;
-- HUC
HUC : Boolean := False;
-- HMC
HMC : Boolean := False;
-- DAIF
DAIF : Boolean := False;
-- PM
PM : Boolean := False;
-- DBF
DBF : Boolean := False;
-- PCF
PCF : MACPFR_PCF_Field := 16#0#;
-- SAIF
SAIF : Boolean := False;
-- SAF
SAF : Boolean := False;
-- HPF
HPF : Boolean := False;
-- unspecified
Reserved_11_15 : HAL.UInt5 := 16#0#;
-- VTFE
VTFE : Boolean := False;
-- unspecified
Reserved_17_19 : HAL.UInt3 := 16#0#;
-- IPFE
IPFE : Boolean := False;
-- DNTU
DNTU : Boolean := False;
-- unspecified
Reserved_22_30 : HAL.UInt9 := 16#0#;
-- RA
RA : Boolean := False;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACPFR_Register use record
PR at 0 range 0 .. 0;
HUC at 0 range 1 .. 1;
HMC at 0 range 2 .. 2;
DAIF at 0 range 3 .. 3;
PM at 0 range 4 .. 4;
DBF at 0 range 5 .. 5;
PCF at 0 range 6 .. 7;
SAIF at 0 range 8 .. 8;
SAF at 0 range 9 .. 9;
HPF at 0 range 10 .. 10;
Reserved_11_15 at 0 range 11 .. 15;
VTFE at 0 range 16 .. 16;
Reserved_17_19 at 0 range 17 .. 19;
IPFE at 0 range 20 .. 20;
DNTU at 0 range 21 .. 21;
Reserved_22_30 at 0 range 22 .. 30;
RA at 0 range 31 .. 31;
end record;
subtype MACWTR_WTO_Field is HAL.UInt4;
-- Watchdog timeout register
type MACWTR_Register is record
-- WTO
WTO : MACWTR_WTO_Field := 16#0#;
-- unspecified
Reserved_4_7 : HAL.UInt4 := 16#0#;
-- PWE
PWE : Boolean := False;
-- unspecified
Reserved_9_31 : HAL.UInt23 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACWTR_Register use record
WTO at 0 range 0 .. 3;
Reserved_4_7 at 0 range 4 .. 7;
PWE at 0 range 8 .. 8;
Reserved_9_31 at 0 range 9 .. 31;
end record;
subtype MACVTR_VL_Field is HAL.UInt16;
subtype MACVTR_EVLS_Field is HAL.UInt2;
subtype MACVTR_EIVLS_Field is HAL.UInt2;
-- VLAN tag register
type MACVTR_Register is record
-- VL
VL : MACVTR_VL_Field := 16#0#;
-- ETV
ETV : Boolean := False;
-- VTIM
VTIM : Boolean := False;
-- ESVL
ESVL : Boolean := False;
-- ERSVLM
ERSVLM : Boolean := False;
-- DOVLTC
DOVLTC : Boolean := False;
-- EVLS
EVLS : MACVTR_EVLS_Field := 16#0#;
-- unspecified
Reserved_23_23 : HAL.Bit := 16#0#;
-- EVLRXS
EVLRXS : Boolean := False;
-- VTHM
VTHM : Boolean := False;
-- EDVLP
EDVLP : Boolean := False;
-- ERIVLT
ERIVLT : Boolean := False;
-- EIVLS
EIVLS : MACVTR_EIVLS_Field := 16#0#;
-- unspecified
Reserved_30_30 : HAL.Bit := 16#0#;
-- EIVLRXS
EIVLRXS : Boolean := False;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACVTR_Register use record
VL at 0 range 0 .. 15;
ETV at 0 range 16 .. 16;
VTIM at 0 range 17 .. 17;
ESVL at 0 range 18 .. 18;
ERSVLM at 0 range 19 .. 19;
DOVLTC at 0 range 20 .. 20;
EVLS at 0 range 21 .. 22;
Reserved_23_23 at 0 range 23 .. 23;
EVLRXS at 0 range 24 .. 24;
VTHM at 0 range 25 .. 25;
EDVLP at 0 range 26 .. 26;
ERIVLT at 0 range 27 .. 27;
EIVLS at 0 range 28 .. 29;
Reserved_30_30 at 0 range 30 .. 30;
EIVLRXS at 0 range 31 .. 31;
end record;
subtype MACVHTR_VLHT_Field is HAL.UInt16;
-- VLAN Hash table register
type MACVHTR_Register is record
-- VLHT
VLHT : MACVHTR_VLHT_Field := 16#0#;
-- unspecified
Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACVHTR_Register use record
VLHT at 0 range 0 .. 15;
Reserved_16_31 at 0 range 16 .. 31;
end record;
subtype MACVIR_VLT_Field is HAL.UInt16;
subtype MACVIR_VLC_Field is HAL.UInt2;
-- VLAN inclusion register
type MACVIR_Register is record
-- VLT
VLT : MACVIR_VLT_Field := 16#0#;
-- VLC
VLC : MACVIR_VLC_Field := 16#0#;
-- VLP
VLP : Boolean := False;
-- CSVL
CSVL : Boolean := False;
-- VLTI
VLTI : Boolean := False;
-- unspecified
Reserved_21_31 : HAL.UInt11 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACVIR_Register use record
VLT at 0 range 0 .. 15;
VLC at 0 range 16 .. 17;
VLP at 0 range 18 .. 18;
CSVL at 0 range 19 .. 19;
VLTI at 0 range 20 .. 20;
Reserved_21_31 at 0 range 21 .. 31;
end record;
subtype MACIVIR_VLT_Field is HAL.UInt16;
subtype MACIVIR_VLC_Field is HAL.UInt2;
-- Inner VLAN inclusion register
type MACIVIR_Register is record
-- VLT
VLT : MACIVIR_VLT_Field := 16#0#;
-- VLC
VLC : MACIVIR_VLC_Field := 16#0#;
-- VLP
VLP : Boolean := False;
-- CSVL
CSVL : Boolean := False;
-- VLTI
VLTI : Boolean := False;
-- unspecified
Reserved_21_31 : HAL.UInt11 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACIVIR_Register use record
VLT at 0 range 0 .. 15;
VLC at 0 range 16 .. 17;
VLP at 0 range 18 .. 18;
CSVL at 0 range 19 .. 19;
VLTI at 0 range 20 .. 20;
Reserved_21_31 at 0 range 21 .. 31;
end record;
subtype MACQTxFCR_PLT_Field is HAL.UInt3;
subtype MACQTxFCR_PT_Field is HAL.UInt16;
-- Tx Queue flow control register
type MACQTxFCR_Register is record
-- FCB_BPA
FCB_BPA : Boolean := False;
-- TFE
TFE : Boolean := False;
-- unspecified
Reserved_2_3 : HAL.UInt2 := 16#0#;
-- PLT
PLT : MACQTxFCR_PLT_Field := 16#0#;
-- DZPQ
DZPQ : Boolean := False;
-- unspecified
Reserved_8_15 : HAL.UInt8 := 16#0#;
-- PT
PT : MACQTxFCR_PT_Field := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACQTxFCR_Register use record
FCB_BPA at 0 range 0 .. 0;
TFE at 0 range 1 .. 1;
Reserved_2_3 at 0 range 2 .. 3;
PLT at 0 range 4 .. 6;
DZPQ at 0 range 7 .. 7;
Reserved_8_15 at 0 range 8 .. 15;
PT at 0 range 16 .. 31;
end record;
-- Rx flow control register
type MACRxFCR_Register is record
-- RFE
RFE : Boolean := False;
-- UP
UP : Boolean := False;
-- unspecified
Reserved_2_31 : HAL.UInt30 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACRxFCR_Register use record
RFE at 0 range 0 .. 0;
UP at 0 range 1 .. 1;
Reserved_2_31 at 0 range 2 .. 31;
end record;
-- Interrupt status register
type MACISR_Register is record
-- unspecified
Reserved_0_2 : HAL.UInt3;
-- Read-only. PHYIS
PHYIS : Boolean;
-- Read-only. PMTIS
PMTIS : Boolean;
-- Read-only. LPIIS
LPIIS : Boolean;
-- unspecified
Reserved_6_7 : HAL.UInt2;
-- Read-only. MMCIS
MMCIS : Boolean;
-- Read-only. MMCRXIS
MMCRXIS : Boolean;
-- Read-only. MMCTXIS
MMCTXIS : Boolean;
-- unspecified
Reserved_11_11 : HAL.Bit;
-- Read-only. TSIS
TSIS : Boolean;
-- Read-only. TXSTSIS
TXSTSIS : Boolean;
-- Read-only. RXSTSIS
RXSTSIS : Boolean;
-- unspecified
Reserved_15_31 : HAL.UInt17;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACISR_Register use record
Reserved_0_2 at 0 range 0 .. 2;
PHYIS at 0 range 3 .. 3;
PMTIS at 0 range 4 .. 4;
LPIIS at 0 range 5 .. 5;
Reserved_6_7 at 0 range 6 .. 7;
MMCIS at 0 range 8 .. 8;
MMCRXIS at 0 range 9 .. 9;
MMCTXIS at 0 range 10 .. 10;
Reserved_11_11 at 0 range 11 .. 11;
TSIS at 0 range 12 .. 12;
TXSTSIS at 0 range 13 .. 13;
RXSTSIS at 0 range 14 .. 14;
Reserved_15_31 at 0 range 15 .. 31;
end record;
-- Interrupt enable register
type MACIER_Register is record
-- unspecified
Reserved_0_2 : HAL.UInt3 := 16#0#;
-- PHYIE
PHYIE : Boolean := False;
-- PMTIE
PMTIE : Boolean := False;
-- LPIIE
LPIIE : Boolean := False;
-- unspecified
Reserved_6_11 : HAL.UInt6 := 16#0#;
-- TSIE
TSIE : Boolean := False;
-- TXSTSIE
TXSTSIE : Boolean := False;
-- RXSTSIE
RXSTSIE : Boolean := False;
-- unspecified
Reserved_15_31 : HAL.UInt17 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACIER_Register use record
Reserved_0_2 at 0 range 0 .. 2;
PHYIE at 0 range 3 .. 3;
PMTIE at 0 range 4 .. 4;
LPIIE at 0 range 5 .. 5;
Reserved_6_11 at 0 range 6 .. 11;
TSIE at 0 range 12 .. 12;
TXSTSIE at 0 range 13 .. 13;
RXSTSIE at 0 range 14 .. 14;
Reserved_15_31 at 0 range 15 .. 31;
end record;
-- Rx Tx status register
type MACRxTxSR_Register is record
-- Read-only. TJT
TJT : Boolean;
-- Read-only. NCARR
NCARR : Boolean;
-- Read-only. LCARR
LCARR : Boolean;
-- Read-only. EXDEF
EXDEF : Boolean;
-- Read-only. LCOL
LCOL : Boolean;
-- Read-only. LCOL
EXCOL : Boolean;
-- unspecified
Reserved_6_7 : HAL.UInt2;
-- Read-only. RWT
RWT : Boolean;
-- unspecified
Reserved_9_31 : HAL.UInt23;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACRxTxSR_Register use record
TJT at 0 range 0 .. 0;
NCARR at 0 range 1 .. 1;
LCARR at 0 range 2 .. 2;
EXDEF at 0 range 3 .. 3;
LCOL at 0 range 4 .. 4;
EXCOL at 0 range 5 .. 5;
Reserved_6_7 at 0 range 6 .. 7;
RWT at 0 range 8 .. 8;
Reserved_9_31 at 0 range 9 .. 31;
end record;
subtype MACPCSR_RWKPTR_Field is HAL.UInt5;
-- PMT control status register
type MACPCSR_Register is record
-- PWRDWN
PWRDWN : Boolean := False;
-- MGKPKTEN
MGKPKTEN : Boolean := False;
-- RWKPKTEN
RWKPKTEN : Boolean := False;
-- unspecified
Reserved_3_4 : HAL.UInt2 := 16#0#;
-- Read-only. MGKPRCVD
MGKPRCVD : Boolean := False;
-- Read-only. RWKPRCVD
RWKPRCVD : Boolean := False;
-- unspecified
Reserved_7_8 : HAL.UInt2 := 16#0#;
-- GLBLUCAST
GLBLUCAST : Boolean := False;
-- RWKPFE
RWKPFE : Boolean := False;
-- unspecified
Reserved_11_23 : HAL.UInt13 := 16#0#;
-- RWKPTR
RWKPTR : MACPCSR_RWKPTR_Field := 16#0#;
-- unspecified
Reserved_29_30 : HAL.UInt2 := 16#0#;
-- RWKFILTRST
RWKFILTRST : Boolean := False;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACPCSR_Register use record
PWRDWN at 0 range 0 .. 0;
MGKPKTEN at 0 range 1 .. 1;
RWKPKTEN at 0 range 2 .. 2;
Reserved_3_4 at 0 range 3 .. 4;
MGKPRCVD at 0 range 5 .. 5;
RWKPRCVD at 0 range 6 .. 6;
Reserved_7_8 at 0 range 7 .. 8;
GLBLUCAST at 0 range 9 .. 9;
RWKPFE at 0 range 10 .. 10;
Reserved_11_23 at 0 range 11 .. 23;
RWKPTR at 0 range 24 .. 28;
Reserved_29_30 at 0 range 29 .. 30;
RWKFILTRST at 0 range 31 .. 31;
end record;
-- LPI control status register
type MACLCSR_Register is record
-- Read-only. TLPIEN
TLPIEN : Boolean := False;
-- Read-only. TLPIEX
TLPIEX : Boolean := False;
-- Read-only. RLPIEN
RLPIEN : Boolean := False;
-- Read-only. RLPIEX
RLPIEX : Boolean := False;
-- unspecified
Reserved_4_7 : HAL.UInt4 := 16#0#;
-- Read-only. TLPIST
TLPIST : Boolean := False;
-- Read-only. RLPIST
RLPIST : Boolean := False;
-- unspecified
Reserved_10_15 : HAL.UInt6 := 16#0#;
-- LPIEN
LPIEN : Boolean := False;
-- PLS
PLS : Boolean := False;
-- PLSEN
PLSEN : Boolean := False;
-- LPITXA
LPITXA : Boolean := False;
-- LPITE
LPITE : Boolean := False;
-- unspecified
Reserved_21_31 : HAL.UInt11 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACLCSR_Register use record
TLPIEN at 0 range 0 .. 0;
TLPIEX at 0 range 1 .. 1;
RLPIEN at 0 range 2 .. 2;
RLPIEX at 0 range 3 .. 3;
Reserved_4_7 at 0 range 4 .. 7;
TLPIST at 0 range 8 .. 8;
RLPIST at 0 range 9 .. 9;
Reserved_10_15 at 0 range 10 .. 15;
LPIEN at 0 range 16 .. 16;
PLS at 0 range 17 .. 17;
PLSEN at 0 range 18 .. 18;
LPITXA at 0 range 19 .. 19;
LPITE at 0 range 20 .. 20;
Reserved_21_31 at 0 range 21 .. 31;
end record;
subtype MACLTCR_TWT_Field is HAL.UInt16;
subtype MACLTCR_LST_Field is HAL.UInt10;
-- LPI timers control register
type MACLTCR_Register is record
-- TWT
TWT : MACLTCR_TWT_Field := 16#0#;
-- LST
LST : MACLTCR_LST_Field := 16#3E8#;
-- unspecified
Reserved_26_31 : HAL.UInt6 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACLTCR_Register use record
TWT at 0 range 0 .. 15;
LST at 0 range 16 .. 25;
Reserved_26_31 at 0 range 26 .. 31;
end record;
subtype MACLETR_LPIET_Field is HAL.UInt17;
-- LPI entry timer register
type MACLETR_Register is record
-- LPIET
LPIET : MACLETR_LPIET_Field := 16#0#;
-- unspecified
Reserved_17_31 : HAL.UInt15 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACLETR_Register use record
LPIET at 0 range 0 .. 16;
Reserved_17_31 at 0 range 17 .. 31;
end record;
subtype MAC1USTCR_TIC_1US_CNTR_Field is HAL.UInt12;
-- 1-microsecond-tick counter register
type MAC1USTCR_Register is record
-- TIC_1US_CNTR
TIC_1US_CNTR : MAC1USTCR_TIC_1US_CNTR_Field := 16#0#;
-- unspecified
Reserved_12_31 : HAL.UInt20 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MAC1USTCR_Register use record
TIC_1US_CNTR at 0 range 0 .. 11;
Reserved_12_31 at 0 range 12 .. 31;
end record;
subtype MACVR_SNPSVER_Field is HAL.UInt8;
subtype MACVR_USERVER_Field is HAL.UInt8;
-- Version register
type MACVR_Register is record
-- Read-only. SNPSVER
SNPSVER : MACVR_SNPSVER_Field;
-- Read-only. USERVER
USERVER : MACVR_USERVER_Field;
-- unspecified
Reserved_16_31 : HAL.UInt16;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACVR_Register use record
SNPSVER at 0 range 0 .. 7;
USERVER at 0 range 8 .. 15;
Reserved_16_31 at 0 range 16 .. 31;
end record;
subtype MACDR_RFCFCSTS_Field is HAL.UInt2;
subtype MACDR_TFCSTS_Field is HAL.UInt2;
-- Debug register
type MACDR_Register is record
-- Read-only. RPESTS
RPESTS : Boolean;
-- Read-only. RFCFCSTS
RFCFCSTS : MACDR_RFCFCSTS_Field;
-- unspecified
Reserved_3_15 : HAL.UInt13;
-- Read-only. TPESTS
TPESTS : Boolean;
-- Read-only. TFCSTS
TFCSTS : MACDR_TFCSTS_Field;
-- unspecified
Reserved_19_31 : HAL.UInt13;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACDR_Register use record
RPESTS at 0 range 0 .. 0;
RFCFCSTS at 0 range 1 .. 2;
Reserved_3_15 at 0 range 3 .. 15;
TPESTS at 0 range 16 .. 16;
TFCSTS at 0 range 17 .. 18;
Reserved_19_31 at 0 range 19 .. 31;
end record;
subtype MACHWF1R_RXFIFOSIZE_Field is HAL.UInt5;
subtype MACHWF1R_TXFIFOSIZE_Field is HAL.UInt5;
subtype MACHWF1R_ADDR64_Field is HAL.UInt2;
subtype MACHWF1R_HASHTBLSZ_Field is HAL.UInt2;
subtype MACHWF1R_L3L4FNUM_Field is HAL.UInt4;
-- HW feature 1 register
type MACHWF1R_Register is record
-- Read-only. RXFIFOSIZE
RXFIFOSIZE : MACHWF1R_RXFIFOSIZE_Field;
-- unspecified
Reserved_5_5 : HAL.Bit;
-- Read-only. TXFIFOSIZE
TXFIFOSIZE : MACHWF1R_TXFIFOSIZE_Field;
-- Read-only. OSTEN
OSTEN : Boolean;
-- Read-only. PTOEN
PTOEN : Boolean;
-- Read-only. ADVTHWORD
ADVTHWORD : Boolean;
-- Read-only. ADDR64
ADDR64 : MACHWF1R_ADDR64_Field;
-- Read-only. DCBEN
DCBEN : Boolean;
-- Read-only. SPHEN
SPHEN : Boolean;
-- Read-only. TSOEN
TSOEN : Boolean;
-- Read-only. DBGMEMA
DBGMEMA : Boolean;
-- Read-only. AVSEL
AVSEL : Boolean;
-- unspecified
Reserved_21_23 : HAL.UInt3;
-- Read-only. HASHTBLSZ
HASHTBLSZ : MACHWF1R_HASHTBLSZ_Field;
-- unspecified
Reserved_26_26 : HAL.Bit;
-- Read-only. L3L4FNUM
L3L4FNUM : MACHWF1R_L3L4FNUM_Field;
-- unspecified
Reserved_31_31 : HAL.Bit;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACHWF1R_Register use record
RXFIFOSIZE at 0 range 0 .. 4;
Reserved_5_5 at 0 range 5 .. 5;
TXFIFOSIZE at 0 range 6 .. 10;
OSTEN at 0 range 11 .. 11;
PTOEN at 0 range 12 .. 12;
ADVTHWORD at 0 range 13 .. 13;
ADDR64 at 0 range 14 .. 15;
DCBEN at 0 range 16 .. 16;
SPHEN at 0 range 17 .. 17;
TSOEN at 0 range 18 .. 18;
DBGMEMA at 0 range 19 .. 19;
AVSEL at 0 range 20 .. 20;
Reserved_21_23 at 0 range 21 .. 23;
HASHTBLSZ at 0 range 24 .. 25;
Reserved_26_26 at 0 range 26 .. 26;
L3L4FNUM at 0 range 27 .. 30;
Reserved_31_31 at 0 range 31 .. 31;
end record;
subtype MACHWF2R_RXQCNT_Field is HAL.UInt4;
subtype MACHWF2R_TXQCNT_Field is HAL.UInt4;
subtype MACHWF2R_RXCHCNT_Field is HAL.UInt4;
subtype MACHWF2R_TXCHCNT_Field is HAL.UInt4;
subtype MACHWF2R_PPSOUTNUM_Field is HAL.UInt3;
subtype MACHWF2R_AUXSNAPNUM_Field is HAL.UInt3;
-- HW feature 2 register
type MACHWF2R_Register is record
-- Read-only. RXQCNT
RXQCNT : MACHWF2R_RXQCNT_Field;
-- unspecified
Reserved_4_5 : HAL.UInt2;
-- Read-only. TXQCNT
TXQCNT : MACHWF2R_TXQCNT_Field;
-- unspecified
Reserved_10_11 : HAL.UInt2;
-- Read-only. RXCHCNT
RXCHCNT : MACHWF2R_RXCHCNT_Field;
-- unspecified
Reserved_16_17 : HAL.UInt2;
-- Read-only. TXCHCNT
TXCHCNT : MACHWF2R_TXCHCNT_Field;
-- unspecified
Reserved_22_23 : HAL.UInt2;
-- Read-only. PPSOUTNUM
PPSOUTNUM : MACHWF2R_PPSOUTNUM_Field;
-- unspecified
Reserved_27_27 : HAL.Bit;
-- Read-only. AUXSNAPNUM
AUXSNAPNUM : MACHWF2R_AUXSNAPNUM_Field;
-- unspecified
Reserved_31_31 : HAL.Bit;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACHWF2R_Register use record
RXQCNT at 0 range 0 .. 3;
Reserved_4_5 at 0 range 4 .. 5;
TXQCNT at 0 range 6 .. 9;
Reserved_10_11 at 0 range 10 .. 11;
RXCHCNT at 0 range 12 .. 15;
Reserved_16_17 at 0 range 16 .. 17;
TXCHCNT at 0 range 18 .. 21;
Reserved_22_23 at 0 range 22 .. 23;
PPSOUTNUM at 0 range 24 .. 26;
Reserved_27_27 at 0 range 27 .. 27;
AUXSNAPNUM at 0 range 28 .. 30;
Reserved_31_31 at 0 range 31 .. 31;
end record;
subtype MACMDIOAR_GOC_Field is HAL.UInt2;
subtype MACMDIOAR_CR_Field is HAL.UInt4;
subtype MACMDIOAR_NTC_Field is HAL.UInt3;
subtype MACMDIOAR_RDA_Field is HAL.UInt5;
subtype MACMDIOAR_PA_Field is HAL.UInt5;
-- MDIO address register
type MACMDIOAR_Register is record
-- MB
MB : Boolean := False;
-- C45E
C45E : Boolean := False;
-- GOC
GOC : MACMDIOAR_GOC_Field := 16#0#;
-- SKAP
SKAP : Boolean := False;
-- unspecified
Reserved_5_7 : HAL.UInt3 := 16#0#;
-- CR
CR : MACMDIOAR_CR_Field := 16#0#;
-- NTC
NTC : MACMDIOAR_NTC_Field := 16#0#;
-- unspecified
Reserved_15_15 : HAL.Bit := 16#0#;
-- RDA
RDA : MACMDIOAR_RDA_Field := 16#0#;
-- PA
PA : MACMDIOAR_PA_Field := 16#0#;
-- BTB
BTB : Boolean := False;
-- PSE
PSE : Boolean := False;
-- unspecified
Reserved_28_31 : HAL.UInt4 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACMDIOAR_Register use record
MB at 0 range 0 .. 0;
C45E at 0 range 1 .. 1;
GOC at 0 range 2 .. 3;
SKAP at 0 range 4 .. 4;
Reserved_5_7 at 0 range 5 .. 7;
CR at 0 range 8 .. 11;
NTC at 0 range 12 .. 14;
Reserved_15_15 at 0 range 15 .. 15;
RDA at 0 range 16 .. 20;
PA at 0 range 21 .. 25;
BTB at 0 range 26 .. 26;
PSE at 0 range 27 .. 27;
Reserved_28_31 at 0 range 28 .. 31;
end record;
subtype MACMDIODR_MD_Field is HAL.UInt16;
subtype MACMDIODR_RA_Field is HAL.UInt16;
-- MDIO data register
type MACMDIODR_Register is record
-- MD
MD : MACMDIODR_MD_Field := 16#0#;
-- RA
RA : MACMDIODR_RA_Field := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACMDIODR_Register use record
MD at 0 range 0 .. 15;
RA at 0 range 16 .. 31;
end record;
subtype MACA0HR_ADDRHI_Field is HAL.UInt16;
-- Address 0 high register
type MACA0HR_Register is record
-- ADDRHI
ADDRHI : MACA0HR_ADDRHI_Field := 16#FFFF#;
-- unspecified
Reserved_16_30 : HAL.UInt15 := 16#0#;
-- Read-only. AE
AE : Boolean := True;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACA0HR_Register use record
ADDRHI at 0 range 0 .. 15;
Reserved_16_30 at 0 range 16 .. 30;
AE at 0 range 31 .. 31;
end record;
subtype MACA1HR_ADDRHI_Field is HAL.UInt16;
subtype MACA1HR_MBC_Field is HAL.UInt6;
-- Address 1 high register
type MACA1HR_Register is record
-- ADDRHI
ADDRHI : MACA1HR_ADDRHI_Field := 16#FFFF#;
-- unspecified
Reserved_16_23 : HAL.UInt8 := 16#0#;
-- MBC
MBC : MACA1HR_MBC_Field := 16#0#;
-- SA
SA : Boolean := False;
-- AE
AE : Boolean := False;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACA1HR_Register use record
ADDRHI at 0 range 0 .. 15;
Reserved_16_23 at 0 range 16 .. 23;
MBC at 0 range 24 .. 29;
SA at 0 range 30 .. 30;
AE at 0 range 31 .. 31;
end record;
subtype MACA2HR_ADDRHI_Field is HAL.UInt16;
subtype MACA2HR_MBC_Field is HAL.UInt6;
-- Address 2 high register
type MACA2HR_Register is record
-- ADDRHI
ADDRHI : MACA2HR_ADDRHI_Field := 16#FFFF#;
-- unspecified
Reserved_16_23 : HAL.UInt8 := 16#0#;
-- MBC
MBC : MACA2HR_MBC_Field := 16#0#;
-- SA
SA : Boolean := False;
-- AE
AE : Boolean := False;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACA2HR_Register use record
ADDRHI at 0 range 0 .. 15;
Reserved_16_23 at 0 range 16 .. 23;
MBC at 0 range 24 .. 29;
SA at 0 range 30 .. 30;
AE at 0 range 31 .. 31;
end record;
subtype MACA3HR_ADDRHI_Field is HAL.UInt16;
subtype MACA3HR_MBC_Field is HAL.UInt6;
-- Address 3 high register
type MACA3HR_Register is record
-- ADDRHI
ADDRHI : MACA3HR_ADDRHI_Field := 16#FFFF#;
-- unspecified
Reserved_16_23 : HAL.UInt8 := 16#0#;
-- MBC
MBC : MACA3HR_MBC_Field := 16#0#;
-- SA
SA : Boolean := False;
-- AE
AE : Boolean := False;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACA3HR_Register use record
ADDRHI at 0 range 0 .. 15;
Reserved_16_23 at 0 range 16 .. 23;
MBC at 0 range 24 .. 29;
SA at 0 range 30 .. 30;
AE at 0 range 31 .. 31;
end record;
-- MMC control register
type MMC_CONTROL_Register is record
-- CNTRST
CNTRST : Boolean := False;
-- CNTSTOPRO
CNTSTOPRO : Boolean := False;
-- RSTONRD
RSTONRD : Boolean := False;
-- CNTFREEZ
CNTFREEZ : Boolean := False;
-- CNTPRST
CNTPRST : Boolean := False;
-- CNTPRSTLVL
CNTPRSTLVL : Boolean := False;
-- unspecified
Reserved_6_7 : HAL.UInt2 := 16#0#;
-- UCDBC
UCDBC : Boolean := False;
-- unspecified
Reserved_9_31 : HAL.UInt23 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MMC_CONTROL_Register use record
CNTRST at 0 range 0 .. 0;
CNTSTOPRO at 0 range 1 .. 1;
RSTONRD at 0 range 2 .. 2;
CNTFREEZ at 0 range 3 .. 3;
CNTPRST at 0 range 4 .. 4;
CNTPRSTLVL at 0 range 5 .. 5;
Reserved_6_7 at 0 range 6 .. 7;
UCDBC at 0 range 8 .. 8;
Reserved_9_31 at 0 range 9 .. 31;
end record;
-- MMC Rx interrupt register
type MMC_RX_INTERRUPT_Register is record
-- unspecified
Reserved_0_4 : HAL.UInt5;
-- Read-only. RXCRCERPIS
RXCRCERPIS : Boolean;
-- Read-only. RXALGNERPIS
RXALGNERPIS : Boolean;
-- unspecified
Reserved_7_16 : HAL.UInt10;
-- Read-only. RXUCGPIS
RXUCGPIS : Boolean;
-- unspecified
Reserved_18_25 : HAL.UInt8;
-- Read-only. RXLPIUSCIS
RXLPIUSCIS : Boolean;
-- Read-only. RXLPITRCIS
RXLPITRCIS : Boolean;
-- unspecified
Reserved_28_31 : HAL.UInt4;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MMC_RX_INTERRUPT_Register use record
Reserved_0_4 at 0 range 0 .. 4;
RXCRCERPIS at 0 range 5 .. 5;
RXALGNERPIS at 0 range 6 .. 6;
Reserved_7_16 at 0 range 7 .. 16;
RXUCGPIS at 0 range 17 .. 17;
Reserved_18_25 at 0 range 18 .. 25;
RXLPIUSCIS at 0 range 26 .. 26;
RXLPITRCIS at 0 range 27 .. 27;
Reserved_28_31 at 0 range 28 .. 31;
end record;
-- MMC Tx interrupt register
type MMC_TX_INTERRUPT_Register is record
-- unspecified
Reserved_0_13 : HAL.UInt14;
-- Read-only. TXSCOLGPIS
TXSCOLGPIS : Boolean;
-- Read-only. TXMCOLGPIS
TXMCOLGPIS : Boolean;
-- unspecified
Reserved_16_20 : HAL.UInt5;
-- Read-only. TXGPKTIS
TXGPKTIS : Boolean;
-- unspecified
Reserved_22_25 : HAL.UInt4;
-- Read-only. TXLPIUSCIS
TXLPIUSCIS : Boolean;
-- Read-only. TXLPITRCIS
TXLPITRCIS : Boolean;
-- unspecified
Reserved_28_31 : HAL.UInt4;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MMC_TX_INTERRUPT_Register use record
Reserved_0_13 at 0 range 0 .. 13;
TXSCOLGPIS at 0 range 14 .. 14;
TXMCOLGPIS at 0 range 15 .. 15;
Reserved_16_20 at 0 range 16 .. 20;
TXGPKTIS at 0 range 21 .. 21;
Reserved_22_25 at 0 range 22 .. 25;
TXLPIUSCIS at 0 range 26 .. 26;
TXLPITRCIS at 0 range 27 .. 27;
Reserved_28_31 at 0 range 28 .. 31;
end record;
-- MMC Rx interrupt mask register
type MMC_RX_INTERRUPT_MASK_Register is record
-- unspecified
Reserved_0_4 : HAL.UInt5 := 16#0#;
-- RXCRCERPIM
RXCRCERPIM : Boolean := False;
-- RXALGNERPIM
RXALGNERPIM : Boolean := False;
-- unspecified
Reserved_7_16 : HAL.UInt10 := 16#0#;
-- RXUCGPIM
RXUCGPIM : Boolean := False;
-- unspecified
Reserved_18_25 : HAL.UInt8 := 16#0#;
-- RXLPIUSCIM
RXLPIUSCIM : Boolean := False;
-- Read-only. RXLPITRCIM
RXLPITRCIM : Boolean := False;
-- unspecified
Reserved_28_31 : HAL.UInt4 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MMC_RX_INTERRUPT_MASK_Register use record
Reserved_0_4 at 0 range 0 .. 4;
RXCRCERPIM at 0 range 5 .. 5;
RXALGNERPIM at 0 range 6 .. 6;
Reserved_7_16 at 0 range 7 .. 16;
RXUCGPIM at 0 range 17 .. 17;
Reserved_18_25 at 0 range 18 .. 25;
RXLPIUSCIM at 0 range 26 .. 26;
RXLPITRCIM at 0 range 27 .. 27;
Reserved_28_31 at 0 range 28 .. 31;
end record;
-- MMC Tx interrupt mask register
type MMC_TX_INTERRUPT_MASK_Register is record
-- unspecified
Reserved_0_13 : HAL.UInt14 := 16#0#;
-- TXSCOLGPIM
TXSCOLGPIM : Boolean := False;
-- TXMCOLGPIM
TXMCOLGPIM : Boolean := False;
-- unspecified
Reserved_16_20 : HAL.UInt5 := 16#0#;
-- TXGPKTIM
TXGPKTIM : Boolean := False;
-- unspecified
Reserved_22_25 : HAL.UInt4 := 16#0#;
-- TXLPIUSCIM
TXLPIUSCIM : Boolean := False;
-- Read-only. TXLPITRCIM
TXLPITRCIM : Boolean := False;
-- unspecified
Reserved_28_31 : HAL.UInt4 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MMC_TX_INTERRUPT_MASK_Register use record
Reserved_0_13 at 0 range 0 .. 13;
TXSCOLGPIM at 0 range 14 .. 14;
TXMCOLGPIM at 0 range 15 .. 15;
Reserved_16_20 at 0 range 16 .. 20;
TXGPKTIM at 0 range 21 .. 21;
Reserved_22_25 at 0 range 22 .. 25;
TXLPIUSCIM at 0 range 26 .. 26;
TXLPITRCIM at 0 range 27 .. 27;
Reserved_28_31 at 0 range 28 .. 31;
end record;
subtype MACL3L4C0R_L3HSBM0_Field is HAL.UInt5;
subtype MACL3L4C0R_L3HDBM0_Field is HAL.UInt5;
-- L3 and L4 control 0 register
type MACL3L4C0R_Register is record
-- L3PEN0
L3PEN0 : Boolean := False;
-- unspecified
Reserved_1_1 : HAL.Bit := 16#0#;
-- L3SAM0
L3SAM0 : Boolean := False;
-- L3SAIM0
L3SAIM0 : Boolean := False;
-- L3DAM0
L3DAM0 : Boolean := False;
-- L3DAIM0
L3DAIM0 : Boolean := False;
-- L3HSBM0
L3HSBM0 : MACL3L4C0R_L3HSBM0_Field := 16#0#;
-- L3HDBM0
L3HDBM0 : MACL3L4C0R_L3HDBM0_Field := 16#0#;
-- L4PEN0
L4PEN0 : Boolean := False;
-- unspecified
Reserved_17_17 : HAL.Bit := 16#0#;
-- L4SPM0
L4SPM0 : Boolean := False;
-- L4SPIM0
L4SPIM0 : Boolean := False;
-- L4DPM0
L4DPM0 : Boolean := False;
-- L4DPIM0
L4DPIM0 : Boolean := False;
-- unspecified
Reserved_22_31 : HAL.UInt10 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACL3L4C0R_Register use record
L3PEN0 at 0 range 0 .. 0;
Reserved_1_1 at 0 range 1 .. 1;
L3SAM0 at 0 range 2 .. 2;
L3SAIM0 at 0 range 3 .. 3;
L3DAM0 at 0 range 4 .. 4;
L3DAIM0 at 0 range 5 .. 5;
L3HSBM0 at 0 range 6 .. 10;
L3HDBM0 at 0 range 11 .. 15;
L4PEN0 at 0 range 16 .. 16;
Reserved_17_17 at 0 range 17 .. 17;
L4SPM0 at 0 range 18 .. 18;
L4SPIM0 at 0 range 19 .. 19;
L4DPM0 at 0 range 20 .. 20;
L4DPIM0 at 0 range 21 .. 21;
Reserved_22_31 at 0 range 22 .. 31;
end record;
subtype MACL4A0R_L4SP0_Field is HAL.UInt16;
subtype MACL4A0R_L4DP0_Field is HAL.UInt16;
-- Layer4 address filter 0 register
type MACL4A0R_Register is record
-- L4SP0
L4SP0 : MACL4A0R_L4SP0_Field := 16#0#;
-- L4DP0
L4DP0 : MACL4A0R_L4DP0_Field := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACL4A0R_Register use record
L4SP0 at 0 range 0 .. 15;
L4DP0 at 0 range 16 .. 31;
end record;
subtype MACL3L4C1R_L3HSBM1_Field is HAL.UInt5;
subtype MACL3L4C1R_L3HDBM1_Field is HAL.UInt5;
-- L3 and L4 control 1 register
type MACL3L4C1R_Register is record
-- L3PEN1
L3PEN1 : Boolean := False;
-- unspecified
Reserved_1_1 : HAL.Bit := 16#0#;
-- L3SAM1
L3SAM1 : Boolean := False;
-- L3SAIM1
L3SAIM1 : Boolean := False;
-- L3DAM1
L3DAM1 : Boolean := False;
-- L3DAIM1
L3DAIM1 : Boolean := False;
-- L3HSBM1
L3HSBM1 : MACL3L4C1R_L3HSBM1_Field := 16#0#;
-- L3HDBM1
L3HDBM1 : MACL3L4C1R_L3HDBM1_Field := 16#0#;
-- L4PEN1
L4PEN1 : Boolean := False;
-- unspecified
Reserved_17_17 : HAL.Bit := 16#0#;
-- L4SPM1
L4SPM1 : Boolean := False;
-- L4SPIM1
L4SPIM1 : Boolean := False;
-- L4DPM1
L4DPM1 : Boolean := False;
-- L4DPIM1
L4DPIM1 : Boolean := False;
-- unspecified
Reserved_22_31 : HAL.UInt10 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACL3L4C1R_Register use record
L3PEN1 at 0 range 0 .. 0;
Reserved_1_1 at 0 range 1 .. 1;
L3SAM1 at 0 range 2 .. 2;
L3SAIM1 at 0 range 3 .. 3;
L3DAM1 at 0 range 4 .. 4;
L3DAIM1 at 0 range 5 .. 5;
L3HSBM1 at 0 range 6 .. 10;
L3HDBM1 at 0 range 11 .. 15;
L4PEN1 at 0 range 16 .. 16;
Reserved_17_17 at 0 range 17 .. 17;
L4SPM1 at 0 range 18 .. 18;
L4SPIM1 at 0 range 19 .. 19;
L4DPM1 at 0 range 20 .. 20;
L4DPIM1 at 0 range 21 .. 21;
Reserved_22_31 at 0 range 22 .. 31;
end record;
subtype MACL4A1R_L4SP1_Field is HAL.UInt16;
subtype MACL4A1R_L4DP1_Field is HAL.UInt16;
-- Layer 4 address filter 1 register
type MACL4A1R_Register is record
-- L4SP1
L4SP1 : MACL4A1R_L4SP1_Field := 16#0#;
-- L4DP1
L4DP1 : MACL4A1R_L4DP1_Field := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACL4A1R_Register use record
L4SP1 at 0 range 0 .. 15;
L4DP1 at 0 range 16 .. 31;
end record;
subtype MACTSCR_SNAPTYPSEL_Field is HAL.UInt2;
-- Timestamp control Register
type MACTSCR_Register is record
-- TSENA
TSENA : Boolean := False;
-- TSCFUPDT
TSCFUPDT : Boolean := False;
-- TSINIT
TSINIT : Boolean := False;
-- TSUPDT
TSUPDT : Boolean := False;
-- unspecified
Reserved_4_4 : HAL.Bit := 16#0#;
-- TSADDREG
TSADDREG : Boolean := False;
-- unspecified
Reserved_6_7 : HAL.UInt2 := 16#0#;
-- TSENALL
TSENALL : Boolean := False;
-- TSCTRLSSR
TSCTRLSSR : Boolean := True;
-- TSVER2ENA
TSVER2ENA : Boolean := False;
-- TSIPENA
TSIPENA : Boolean := False;
-- TSIPV6ENA
TSIPV6ENA : Boolean := False;
-- TSIPV4ENA
TSIPV4ENA : Boolean := False;
-- TSEVNTENA
TSEVNTENA : Boolean := False;
-- TSMSTRENA
TSMSTRENA : Boolean := False;
-- SNAPTYPSEL
SNAPTYPSEL : MACTSCR_SNAPTYPSEL_Field := 16#0#;
-- TSENMACADDR
TSENMACADDR : Boolean := False;
-- Read-only. CSC
CSC : Boolean := False;
-- unspecified
Reserved_20_23 : HAL.UInt4 := 16#0#;
-- TXTSSTSM
TXTSSTSM : Boolean := False;
-- unspecified
Reserved_25_31 : HAL.UInt7 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACTSCR_Register use record
TSENA at 0 range 0 .. 0;
TSCFUPDT at 0 range 1 .. 1;
TSINIT at 0 range 2 .. 2;
TSUPDT at 0 range 3 .. 3;
Reserved_4_4 at 0 range 4 .. 4;
TSADDREG at 0 range 5 .. 5;
Reserved_6_7 at 0 range 6 .. 7;
TSENALL at 0 range 8 .. 8;
TSCTRLSSR at 0 range 9 .. 9;
TSVER2ENA at 0 range 10 .. 10;
TSIPENA at 0 range 11 .. 11;
TSIPV6ENA at 0 range 12 .. 12;
TSIPV4ENA at 0 range 13 .. 13;
TSEVNTENA at 0 range 14 .. 14;
TSMSTRENA at 0 range 15 .. 15;
SNAPTYPSEL at 0 range 16 .. 17;
TSENMACADDR at 0 range 18 .. 18;
CSC at 0 range 19 .. 19;
Reserved_20_23 at 0 range 20 .. 23;
TXTSSTSM at 0 range 24 .. 24;
Reserved_25_31 at 0 range 25 .. 31;
end record;
subtype MACSSIR_SNSINC_Field is HAL.UInt8;
subtype MACSSIR_SSINC_Field is HAL.UInt8;
-- Sub-second increment register
type MACSSIR_Register is record
-- unspecified
Reserved_0_7 : HAL.UInt8 := 16#0#;
-- SNSINC
SNSINC : MACSSIR_SNSINC_Field := 16#0#;
-- SSINC
SSINC : MACSSIR_SSINC_Field := 16#0#;
-- unspecified
Reserved_24_31 : HAL.UInt8 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACSSIR_Register use record
Reserved_0_7 at 0 range 0 .. 7;
SNSINC at 0 range 8 .. 15;
SSINC at 0 range 16 .. 23;
Reserved_24_31 at 0 range 24 .. 31;
end record;
subtype MACSTNR_TSSS_Field is HAL.UInt31;
-- System time nanoseconds register
type MACSTNR_Register is record
-- Read-only. TSSS
TSSS : MACSTNR_TSSS_Field;
-- unspecified
Reserved_31_31 : HAL.Bit;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACSTNR_Register use record
TSSS at 0 range 0 .. 30;
Reserved_31_31 at 0 range 31 .. 31;
end record;
subtype MACSTNUR_TSSS_Field is HAL.UInt31;
-- System time nanoseconds update register
type MACSTNUR_Register is record
-- TSSS
TSSS : MACSTNUR_TSSS_Field := 16#0#;
-- ADDSUB
ADDSUB : Boolean := False;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACSTNUR_Register use record
TSSS at 0 range 0 .. 30;
ADDSUB at 0 range 31 .. 31;
end record;
subtype MACTSSR_ATSSTN_Field is HAL.UInt4;
subtype MACTSSR_ATSNS_Field is HAL.UInt5;
-- Timestamp status register
type MACTSSR_Register is record
-- Read-only. TSSOVF
TSSOVF : Boolean;
-- Read-only. TSTARGT0
TSTARGT0 : Boolean;
-- Read-only. AUXTSTRIG
AUXTSTRIG : Boolean;
-- Read-only. TSTRGTERR0
TSTRGTERR0 : Boolean;
-- unspecified
Reserved_4_14 : HAL.UInt11;
-- Read-only. TXTSSIS
TXTSSIS : Boolean;
-- Read-only. ATSSTN
ATSSTN : MACTSSR_ATSSTN_Field;
-- unspecified
Reserved_20_23 : HAL.UInt4;
-- Read-only. ATSSTM
ATSSTM : Boolean;
-- Read-only. ATSNS
ATSNS : MACTSSR_ATSNS_Field;
-- unspecified
Reserved_30_31 : HAL.UInt2;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACTSSR_Register use record
TSSOVF at 0 range 0 .. 0;
TSTARGT0 at 0 range 1 .. 1;
AUXTSTRIG at 0 range 2 .. 2;
TSTRGTERR0 at 0 range 3 .. 3;
Reserved_4_14 at 0 range 4 .. 14;
TXTSSIS at 0 range 15 .. 15;
ATSSTN at 0 range 16 .. 19;
Reserved_20_23 at 0 range 20 .. 23;
ATSSTM at 0 range 24 .. 24;
ATSNS at 0 range 25 .. 29;
Reserved_30_31 at 0 range 30 .. 31;
end record;
subtype MACTxTSSNR_TXTSSLO_Field is HAL.UInt31;
-- Tx timestamp status nanoseconds register
type MACTxTSSNR_Register is record
-- Read-only. TXTSSLO
TXTSSLO : MACTxTSSNR_TXTSSLO_Field;
-- Read-only. TXTSSMIS
TXTSSMIS : Boolean;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACTxTSSNR_Register use record
TXTSSLO at 0 range 0 .. 30;
TXTSSMIS at 0 range 31 .. 31;
end record;
-- MACACR_ATSEN array
type MACACR_ATSEN_Field_Array is array (0 .. 3) of Boolean
with Component_Size => 1, Size => 4;
-- Type definition for MACACR_ATSEN
type MACACR_ATSEN_Field
(As_Array : Boolean := False)
is record
case As_Array is
when False =>
-- ATSEN as a value
Val : HAL.UInt4;
when True =>
-- ATSEN as an array
Arr : MACACR_ATSEN_Field_Array;
end case;
end record
with Unchecked_Union, Size => 4;
for MACACR_ATSEN_Field use record
Val at 0 range 0 .. 3;
Arr at 0 range 0 .. 3;
end record;
-- Auxiliary control register
type MACACR_Register is record
-- ATSFC
ATSFC : Boolean := False;
-- unspecified
Reserved_1_3 : HAL.UInt3 := 16#0#;
-- ATSEN0
ATSEN : MACACR_ATSEN_Field := (As_Array => False, Val => 16#0#);
-- unspecified
Reserved_8_31 : HAL.UInt24 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACACR_Register use record
ATSFC at 0 range 0 .. 0;
Reserved_1_3 at 0 range 1 .. 3;
ATSEN at 0 range 4 .. 7;
Reserved_8_31 at 0 range 8 .. 31;
end record;
subtype MACATSNR_AUXTSLO_Field is HAL.UInt31;
-- Auxiliary timestamp nanoseconds register
type MACATSNR_Register is record
-- Read-only. AUXTSLO
AUXTSLO : MACATSNR_AUXTSLO_Field;
-- unspecified
Reserved_31_31 : HAL.Bit;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACATSNR_Register use record
AUXTSLO at 0 range 0 .. 30;
Reserved_31_31 at 0 range 31 .. 31;
end record;
subtype MACPPSCR_PPSCTRL_Field is HAL.UInt4;
subtype MACPPSCR_TRGTMODSEL0_Field is HAL.UInt2;
-- PPS control register
type MACPPSCR_Register is record
-- PPSCTRL
PPSCTRL : MACPPSCR_PPSCTRL_Field := 16#0#;
-- PPSEN0
PPSEN0 : Boolean := False;
-- TRGTMODSEL0
TRGTMODSEL0 : MACPPSCR_TRGTMODSEL0_Field := 16#0#;
-- unspecified
Reserved_7_31 : HAL.UInt25 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACPPSCR_Register use record
PPSCTRL at 0 range 0 .. 3;
PPSEN0 at 0 range 4 .. 4;
TRGTMODSEL0 at 0 range 5 .. 6;
Reserved_7_31 at 0 range 7 .. 31;
end record;
subtype MACPPSTTSR_TSTRH0_Field is HAL.UInt31;
-- PPS target time seconds register
type MACPPSTTSR_Register is record
-- TSTRH0
TSTRH0 : MACPPSTTSR_TSTRH0_Field := 16#0#;
-- unspecified
Reserved_31_31 : HAL.Bit := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACPPSTTSR_Register use record
TSTRH0 at 0 range 0 .. 30;
Reserved_31_31 at 0 range 31 .. 31;
end record;
subtype MACPPSTTNR_TTSL0_Field is HAL.UInt31;
-- PPS target time nanoseconds register
type MACPPSTTNR_Register is record
-- TTSL0
TTSL0 : MACPPSTTNR_TTSL0_Field := 16#0#;
-- TRGTBUSY0
TRGTBUSY0 : Boolean := False;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACPPSTTNR_Register use record
TTSL0 at 0 range 0 .. 30;
TRGTBUSY0 at 0 range 31 .. 31;
end record;
subtype MACPOCR_DN_Field is HAL.UInt8;
-- PTP Offload control register
type MACPOCR_Register is record
-- PTOEN
PTOEN : Boolean := False;
-- ASYNCEN
ASYNCEN : Boolean := False;
-- APDREQEN
APDREQEN : Boolean := False;
-- unspecified
Reserved_3_3 : HAL.Bit := 16#0#;
-- ASYNCTRIG
ASYNCTRIG : Boolean := False;
-- APDREQTRIG
APDREQTRIG : Boolean := False;
-- DRRDIS
DRRDIS : Boolean := False;
-- unspecified
Reserved_7_7 : HAL.Bit := 16#0#;
-- DN
DN : MACPOCR_DN_Field := 16#0#;
-- unspecified
Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACPOCR_Register use record
PTOEN at 0 range 0 .. 0;
ASYNCEN at 0 range 1 .. 1;
APDREQEN at 0 range 2 .. 2;
Reserved_3_3 at 0 range 3 .. 3;
ASYNCTRIG at 0 range 4 .. 4;
APDREQTRIG at 0 range 5 .. 5;
DRRDIS at 0 range 6 .. 6;
Reserved_7_7 at 0 range 7 .. 7;
DN at 0 range 8 .. 15;
Reserved_16_31 at 0 range 16 .. 31;
end record;
subtype MACSPI2R_SPI2_Field is HAL.UInt16;
-- PTP Source port identity 2 register
type MACSPI2R_Register is record
-- SPI2
SPI2 : MACSPI2R_SPI2_Field := 16#0#;
-- unspecified
Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACSPI2R_Register use record
SPI2 at 0 range 0 .. 15;
Reserved_16_31 at 0 range 16 .. 31;
end record;
subtype MACLMIR_LSI_Field is HAL.UInt8;
subtype MACLMIR_DRSYNCR_Field is HAL.UInt3;
subtype MACLMIR_LMPDRI_Field is HAL.UInt8;
-- Log message interval register
type MACLMIR_Register is record
-- LSI
LSI : MACLMIR_LSI_Field := 16#0#;
-- DRSYNCR
DRSYNCR : MACLMIR_DRSYNCR_Field := 16#0#;
-- unspecified
Reserved_11_23 : HAL.UInt13 := 16#0#;
-- LMPDRI
LMPDRI : MACLMIR_LMPDRI_Field := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MACLMIR_Register use record
LSI at 0 range 0 .. 7;
DRSYNCR at 0 range 8 .. 10;
Reserved_11_23 at 0 range 11 .. 23;
LMPDRI at 0 range 24 .. 31;
end record;
-- Operating mode Register
type MTLOMR_Register is record
-- unspecified
Reserved_0_0 : HAL.Bit := 16#0#;
-- DTXSTS
DTXSTS : Boolean := False;
-- unspecified
Reserved_2_7 : HAL.UInt6 := 16#0#;
-- CNTPRST
CNTPRST : Boolean := False;
-- CNTCLR
CNTCLR : Boolean := False;
-- unspecified
Reserved_10_31 : HAL.UInt22 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MTLOMR_Register use record
Reserved_0_0 at 0 range 0 .. 0;
DTXSTS at 0 range 1 .. 1;
Reserved_2_7 at 0 range 2 .. 7;
CNTPRST at 0 range 8 .. 8;
CNTCLR at 0 range 9 .. 9;
Reserved_10_31 at 0 range 10 .. 31;
end record;
-- Interrupt status Register
type MTLISR_Register is record
-- Read-only. Queue interrupt status
Q0IS : Boolean;
-- unspecified
Reserved_1_31 : HAL.UInt31;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MTLISR_Register use record
Q0IS at 0 range 0 .. 0;
Reserved_1_31 at 0 range 1 .. 31;
end record;
subtype MTLTxQOMR_TXQEN_Field is HAL.UInt2;
subtype MTLTxQOMR_TTC_Field is HAL.UInt3;
subtype MTLTxQOMR_TQS_Field is HAL.UInt3;
-- Tx queue operating mode Register
type MTLTxQOMR_Register is record
-- Flush Transmit Queue
FTQ : Boolean := False;
-- Transmit Store and Forward
TSF : Boolean := False;
-- Read-only. Transmit Queue Enable
TXQEN : MTLTxQOMR_TXQEN_Field := 16#2#;
-- Transmit Threshold Control
TTC : MTLTxQOMR_TTC_Field := 16#0#;
-- unspecified
Reserved_7_15 : HAL.UInt9 := 16#0#;
-- Transmit Queue Size
TQS : MTLTxQOMR_TQS_Field := 16#7#;
-- unspecified
Reserved_19_31 : HAL.UInt13 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MTLTxQOMR_Register use record
FTQ at 0 range 0 .. 0;
TSF at 0 range 1 .. 1;
TXQEN at 0 range 2 .. 3;
TTC at 0 range 4 .. 6;
Reserved_7_15 at 0 range 7 .. 15;
TQS at 0 range 16 .. 18;
Reserved_19_31 at 0 range 19 .. 31;
end record;
subtype MTLTxQUR_UFFRMCNT_Field is HAL.UInt11;
-- Tx queue underflow register
type MTLTxQUR_Register is record
-- Read-only. Underflow Packet Counter
UFFRMCNT : MTLTxQUR_UFFRMCNT_Field;
-- Read-only. UFCNTOVF
UFCNTOVF : Boolean;
-- unspecified
Reserved_12_31 : HAL.UInt20;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MTLTxQUR_Register use record
UFFRMCNT at 0 range 0 .. 10;
UFCNTOVF at 0 range 11 .. 11;
Reserved_12_31 at 0 range 12 .. 31;
end record;
subtype MTLTxQDR_TRCSTS_Field is HAL.UInt2;
subtype MTLTxQDR_PTXQ_Field is HAL.UInt3;
subtype MTLTxQDR_STXSTSF_Field is HAL.UInt3;
-- Tx queue debug Register
type MTLTxQDR_Register is record
-- Read-only. TXQPAUSED
TXQPAUSED : Boolean;
-- Read-only. TRCSTS
TRCSTS : MTLTxQDR_TRCSTS_Field;
-- Read-only. TWCSTS
TWCSTS : Boolean;
-- Read-only. TXQSTS
TXQSTS : Boolean;
-- Read-only. TXSTSFSTS
TXSTSFSTS : Boolean;
-- unspecified
Reserved_6_15 : HAL.UInt10;
-- Read-only. PTXQ
PTXQ : MTLTxQDR_PTXQ_Field;
-- unspecified
Reserved_19_19 : HAL.Bit;
-- Read-only. STXSTSF
STXSTSF : MTLTxQDR_STXSTSF_Field;
-- unspecified
Reserved_23_31 : HAL.UInt9;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MTLTxQDR_Register use record
TXQPAUSED at 0 range 0 .. 0;
TRCSTS at 0 range 1 .. 2;
TWCSTS at 0 range 3 .. 3;
TXQSTS at 0 range 4 .. 4;
TXSTSFSTS at 0 range 5 .. 5;
Reserved_6_15 at 0 range 6 .. 15;
PTXQ at 0 range 16 .. 18;
Reserved_19_19 at 0 range 19 .. 19;
STXSTSF at 0 range 20 .. 22;
Reserved_23_31 at 0 range 23 .. 31;
end record;
-- Queue interrupt control status Register
type MTLQICSR_Register is record
-- TXUNFIS
TXUNFIS : Boolean := False;
-- unspecified
Reserved_1_7 : HAL.UInt7 := 16#0#;
-- TXUIE
TXUIE : Boolean := False;
-- unspecified
Reserved_9_15 : HAL.UInt7 := 16#0#;
-- RXOVFIS
RXOVFIS : Boolean := False;
-- unspecified
Reserved_17_23 : HAL.UInt7 := 16#0#;
-- RXOIE
RXOIE : Boolean := False;
-- unspecified
Reserved_25_31 : HAL.UInt7 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MTLQICSR_Register use record
TXUNFIS at 0 range 0 .. 0;
Reserved_1_7 at 0 range 1 .. 7;
TXUIE at 0 range 8 .. 8;
Reserved_9_15 at 0 range 9 .. 15;
RXOVFIS at 0 range 16 .. 16;
Reserved_17_23 at 0 range 17 .. 23;
RXOIE at 0 range 24 .. 24;
Reserved_25_31 at 0 range 25 .. 31;
end record;
subtype MTLRxQOMR_RTC_Field is HAL.UInt2;
subtype MTLRxQOMR_RFA_Field is HAL.UInt3;
subtype MTLRxQOMR_RFD_Field is HAL.UInt3;
subtype MTLRxQOMR_RQS_Field is HAL.UInt3;
-- Rx queue operating mode register
type MTLRxQOMR_Register is record
-- RTC
RTC : MTLRxQOMR_RTC_Field := 16#0#;
-- unspecified
Reserved_2_2 : HAL.Bit := 16#0#;
-- FUP
FUP : Boolean := False;
-- FEP
FEP : Boolean := False;
-- RSF
RSF : Boolean := False;
-- DIS_TCP_EF
DIS_TCP_EF : Boolean := False;
-- EHFC
EHFC : Boolean := False;
-- RFA
RFA : MTLRxQOMR_RFA_Field := 16#0#;
-- unspecified
Reserved_11_13 : HAL.UInt3 := 16#0#;
-- RFD
RFD : MTLRxQOMR_RFD_Field := 16#0#;
-- unspecified
Reserved_17_19 : HAL.UInt3 := 16#0#;
-- Read-only. RQS
RQS : MTLRxQOMR_RQS_Field := 16#7#;
-- unspecified
Reserved_23_31 : HAL.UInt9 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MTLRxQOMR_Register use record
RTC at 0 range 0 .. 1;
Reserved_2_2 at 0 range 2 .. 2;
FUP at 0 range 3 .. 3;
FEP at 0 range 4 .. 4;
RSF at 0 range 5 .. 5;
DIS_TCP_EF at 0 range 6 .. 6;
EHFC at 0 range 7 .. 7;
RFA at 0 range 8 .. 10;
Reserved_11_13 at 0 range 11 .. 13;
RFD at 0 range 14 .. 16;
Reserved_17_19 at 0 range 17 .. 19;
RQS at 0 range 20 .. 22;
Reserved_23_31 at 0 range 23 .. 31;
end record;
subtype MTLRxQMPOCR_OVFPKTCNT_Field is HAL.UInt11;
subtype MTLRxQMPOCR_MISPKTCNT_Field is HAL.UInt11;
-- Rx queue missed packet and overflow counter register
type MTLRxQMPOCR_Register is record
-- Read-only. OVFPKTCNT
OVFPKTCNT : MTLRxQMPOCR_OVFPKTCNT_Field;
-- Read-only. OVFCNTOVF
OVFCNTOVF : Boolean;
-- unspecified
Reserved_12_15 : HAL.UInt4;
-- Read-only. MISPKTCNT
MISPKTCNT : MTLRxQMPOCR_MISPKTCNT_Field;
-- Read-only. MISCNTOVF
MISCNTOVF : Boolean;
-- unspecified
Reserved_28_31 : HAL.UInt4;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MTLRxQMPOCR_Register use record
OVFPKTCNT at 0 range 0 .. 10;
OVFCNTOVF at 0 range 11 .. 11;
Reserved_12_15 at 0 range 12 .. 15;
MISPKTCNT at 0 range 16 .. 26;
MISCNTOVF at 0 range 27 .. 27;
Reserved_28_31 at 0 range 28 .. 31;
end record;
subtype MTLRxQDR_RRCSTS_Field is HAL.UInt2;
subtype MTLRxQDR_RXQSTS_Field is HAL.UInt2;
subtype MTLRxQDR_PRXQ_Field is HAL.UInt14;
-- Rx queue debug register
type MTLRxQDR_Register is record
-- Read-only. RWCSTS
RWCSTS : Boolean;
-- Read-only. RRCSTS
RRCSTS : MTLRxQDR_RRCSTS_Field;
-- unspecified
Reserved_3_3 : HAL.Bit;
-- Read-only. RXQSTS
RXQSTS : MTLRxQDR_RXQSTS_Field;
-- unspecified
Reserved_6_15 : HAL.UInt10;
-- Read-only. PRXQ
PRXQ : MTLRxQDR_PRXQ_Field;
-- unspecified
Reserved_30_31 : HAL.UInt2;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
for MTLRxQDR_Register use record
RWCSTS at 0 range 0 .. 0;
RRCSTS at 0 range 1 .. 2;
Reserved_3_3 at 0 range 3 .. 3;
RXQSTS at 0 range 4 .. 5;
Reserved_6_15 at 0 range 6 .. 15;
PRXQ at 0 range 16 .. 29;
Reserved_30_31 at 0 range 30 .. 31;
end record;
-----------------
-- Peripherals --
-----------------
-- Ethernet: DMA mode register (DMA)
type Ethernet_DMA_Peripheral is record
-- DMA mode register
DMAMR : aliased DMAMR_Register;
-- System bus mode register
DMASBMR : aliased DMASBMR_Register;
-- Interrupt status register
DMAISR : aliased DMAISR_Register;
-- Debug status register
DMADSR : aliased DMADSR_Register;
-- Channel control register
DMACCR : aliased DMACCR_Register;
-- Channel transmit control register
DMACTxCR : aliased DMACTxCR_Register;
-- Channel receive control register
DMACRxCR : aliased DMACRxCR_Register;
-- Channel Tx descriptor list address register
DMACTxDLAR : aliased DMACTxDLAR_Register;
-- Channel Rx descriptor list address register
DMACRxDLAR : aliased DMACRxDLAR_Register;
-- Channel Tx descriptor tail pointer register
DMACTxDTPR : aliased DMACTxDTPR_Register;
-- Channel Rx descriptor tail pointer register
DMACRxDTPR : aliased DMACRxDTPR_Register;
-- Channel Tx descriptor ring length register
DMACTxRLR : aliased DMACTxRLR_Register;
-- Channel Rx descriptor ring length register
DMACRxRLR : aliased DMACRxRLR_Register;
-- Channel interrupt enable register
DMACIER : aliased DMACIER_Register;
-- Channel Rx interrupt watchdog timer register
DMACRxIWTR : aliased DMACRxIWTR_Register;
-- Channel current application transmit descriptor register
DMACCATxDR : aliased HAL.UInt32;
-- Channel current application receive descriptor register
DMACCARxDR : aliased HAL.UInt32;
-- Channel current application transmit buffer register
DMACCATxBR : aliased HAL.UInt32;
-- Channel current application receive buffer register
DMACCARxBR : aliased HAL.UInt32;
-- Channel status register
DMACSR : aliased DMACSR_Register;
-- Channel missed frame count register
DMACMFCR : aliased DMACMFCR_Register;
end record
with Volatile;
for Ethernet_DMA_Peripheral use record
DMAMR at 16#0# range 0 .. 31;
DMASBMR at 16#4# range 0 .. 31;
DMAISR at 16#8# range 0 .. 31;
DMADSR at 16#C# range 0 .. 31;
DMACCR at 16#100# range 0 .. 31;
DMACTxCR at 16#104# range 0 .. 31;
DMACRxCR at 16#108# range 0 .. 31;
DMACTxDLAR at 16#114# range 0 .. 31;
DMACRxDLAR at 16#11C# range 0 .. 31;
DMACTxDTPR at 16#120# range 0 .. 31;
DMACRxDTPR at 16#128# range 0 .. 31;
DMACTxRLR at 16#12C# range 0 .. 31;
DMACRxRLR at 16#130# range 0 .. 31;
DMACIER at 16#134# range 0 .. 31;
DMACRxIWTR at 16#138# range 0 .. 31;
DMACCATxDR at 16#144# range 0 .. 31;
DMACCARxDR at 16#14C# range 0 .. 31;
DMACCATxBR at 16#154# range 0 .. 31;
DMACCARxBR at 16#15C# range 0 .. 31;
DMACSR at 16#160# range 0 .. 31;
DMACMFCR at 16#16C# range 0 .. 31;
end record;
-- Ethernet: DMA mode register (DMA)
Ethernet_DMA_Periph : aliased Ethernet_DMA_Peripheral
with Import, Address => Ethernet_DMA_Base;
-- Ethernet: media access control (MAC)
type Ethernet_MAC_Peripheral is record
-- Operating mode configuration register
MACCR : aliased MACCR_Register;
-- Extended operating mode configuration register
MACECR : aliased MACECR_Register;
-- Packet filtering control register
MACPFR : aliased MACPFR_Register;
-- Watchdog timeout register
MACWTR : aliased MACWTR_Register;
-- Hash Table 0 register
MACHT0R : aliased HAL.UInt32;
-- Hash Table 1 register
MACHT1R : aliased HAL.UInt32;
-- VLAN tag register
MACVTR : aliased MACVTR_Register;
-- VLAN Hash table register
MACVHTR : aliased MACVHTR_Register;
-- VLAN inclusion register
MACVIR : aliased MACVIR_Register;
-- Inner VLAN inclusion register
MACIVIR : aliased MACIVIR_Register;
-- Tx Queue flow control register
MACQTxFCR : aliased MACQTxFCR_Register;
-- Rx flow control register
MACRxFCR : aliased MACRxFCR_Register;
-- Interrupt status register
MACISR : aliased MACISR_Register;
-- Interrupt enable register
MACIER : aliased MACIER_Register;
-- Rx Tx status register
MACRxTxSR : aliased MACRxTxSR_Register;
-- PMT control status register
MACPCSR : aliased MACPCSR_Register;
-- Remove wakeup packet filter register
MACRWKPFR : aliased HAL.UInt32;
-- LPI control status register
MACLCSR : aliased MACLCSR_Register;
-- LPI timers control register
MACLTCR : aliased MACLTCR_Register;
-- LPI entry timer register
MACLETR : aliased MACLETR_Register;
-- 1-microsecond-tick counter register
MAC1USTCR : aliased MAC1USTCR_Register;
-- Version register
MACVR : aliased MACVR_Register;
-- Debug register
MACDR : aliased MACDR_Register;
-- HW feature 1 register
MACHWF1R : aliased MACHWF1R_Register;
-- HW feature 2 register
MACHWF2R : aliased MACHWF2R_Register;
-- MDIO address register
MACMDIOAR : aliased MACMDIOAR_Register;
-- MDIO data register
MACMDIODR : aliased MACMDIODR_Register;
-- Address 0 high register
MACA0HR : aliased MACA0HR_Register;
-- Address 0 low register
MACA0LR : aliased HAL.UInt32;
-- Address 1 high register
MACA1HR : aliased MACA1HR_Register;
-- Address 1 low register
MACA1LR : aliased HAL.UInt32;
-- Address 2 high register
MACA2HR : aliased MACA2HR_Register;
-- Address 2 low register
MACA2LR : aliased HAL.UInt32;
-- Address 3 high register
MACA3HR : aliased MACA3HR_Register;
-- Address 3 low register
MACA3LR : aliased HAL.UInt32;
-- MMC control register
MMC_CONTROL : aliased MMC_CONTROL_Register;
-- MMC Rx interrupt register
MMC_RX_INTERRUPT : aliased MMC_RX_INTERRUPT_Register;
-- MMC Tx interrupt register
MMC_TX_INTERRUPT : aliased MMC_TX_INTERRUPT_Register;
-- MMC Rx interrupt mask register
MMC_RX_INTERRUPT_MASK : aliased MMC_RX_INTERRUPT_MASK_Register;
-- MMC Tx interrupt mask register
MMC_TX_INTERRUPT_MASK : aliased MMC_TX_INTERRUPT_MASK_Register;
-- Tx single collision good packets register
TX_SINGLE_COLLISION_GOOD_PACKETS : aliased HAL.UInt32;
-- Tx multiple collision good packets register
TX_MULTIPLE_COLLISION_GOOD_PACKETS : aliased HAL.UInt32;
-- Tx packet count good register
TX_PACKET_COUNT_GOOD : aliased HAL.UInt32;
-- Rx CRC error packets register
RX_CRC_ERROR_PACKETS : aliased HAL.UInt32;
-- Rx alignment error packets register
RX_ALIGNMENT_ERROR_PACKETS : aliased HAL.UInt32;
-- Rx unicast packets good register
RX_UNICAST_PACKETS_GOOD : aliased HAL.UInt32;
-- Tx LPI microsecond timer register
TX_LPI_USEC_CNTR : aliased HAL.UInt32;
-- Tx LPI transition counter register
TX_LPI_TRAN_CNTR : aliased HAL.UInt32;
-- Rx LPI microsecond counter register
RX_LPI_USEC_CNTR : aliased HAL.UInt32;
-- Rx LPI transition counter register
RX_LPI_TRAN_CNTR : aliased HAL.UInt32;
-- L3 and L4 control 0 register
MACL3L4C0R : aliased MACL3L4C0R_Register;
-- Layer4 address filter 0 register
MACL4A0R : aliased MACL4A0R_Register;
-- MACL3A00R
MACL3A00R : aliased HAL.UInt32;
-- Layer3 address 1 filter 0 register
MACL3A10R : aliased HAL.UInt32;
-- Layer3 Address 2 filter 0 register
MACL3A20 : aliased HAL.UInt32;
-- Layer3 Address 3 filter 0 register
MACL3A30 : aliased HAL.UInt32;
-- L3 and L4 control 1 register
MACL3L4C1R : aliased MACL3L4C1R_Register;
-- Layer 4 address filter 1 register
MACL4A1R : aliased MACL4A1R_Register;
-- Layer3 address 0 filter 1 Register
MACL3A01R : aliased HAL.UInt32;
-- Layer3 address 1 filter 1 register
MACL3A11R : aliased HAL.UInt32;
-- Layer3 address 2 filter 1 Register
MACL3A21R : aliased HAL.UInt32;
-- Layer3 address 3 filter 1 register
MACL3A31R : aliased HAL.UInt32;
-- ARP address register
MACARPAR : aliased HAL.UInt32;
-- Timestamp control Register
MACTSCR : aliased MACTSCR_Register;
-- Sub-second increment register
MACSSIR : aliased MACSSIR_Register;
-- System time seconds register
MACSTSR : aliased HAL.UInt32;
-- System time nanoseconds register
MACSTNR : aliased MACSTNR_Register;
-- System time seconds update register
MACSTSUR : aliased HAL.UInt32;
-- System time nanoseconds update register
MACSTNUR : aliased MACSTNUR_Register;
-- Timestamp addend register
MACTSAR : aliased HAL.UInt32;
-- Timestamp status register
MACTSSR : aliased MACTSSR_Register;
-- Tx timestamp status nanoseconds register
MACTxTSSNR : aliased MACTxTSSNR_Register;
-- Tx timestamp status seconds register
MACTxTSSSR : aliased HAL.UInt32;
-- Auxiliary control register
MACACR : aliased MACACR_Register;
-- Auxiliary timestamp nanoseconds register
MACATSNR : aliased MACATSNR_Register;
-- Auxiliary timestamp seconds register
MACATSSR : aliased HAL.UInt32;
-- Timestamp Ingress asymmetric correction register
MACTSIACR : aliased HAL.UInt32;
-- Timestamp Egress asymmetric correction register
MACTSEACR : aliased HAL.UInt32;
-- Timestamp Ingress correction nanosecond register
MACTSICNR : aliased HAL.UInt32;
-- Timestamp Egress correction nanosecond register
MACTSECNR : aliased HAL.UInt32;
-- PPS control register
MACPPSCR : aliased MACPPSCR_Register;
-- PPS target time seconds register
MACPPSTTSR : aliased MACPPSTTSR_Register;
-- PPS target time nanoseconds register
MACPPSTTNR : aliased MACPPSTTNR_Register;
-- PPS interval register
MACPPSIR : aliased HAL.UInt32;
-- PPS width register
MACPPSWR : aliased HAL.UInt32;
-- PTP Offload control register
MACPOCR : aliased MACPOCR_Register;
-- PTP Source Port Identity 0 Register
MACSPI0R : aliased HAL.UInt32;
-- PTP Source port identity 1 register
MACSPI1R : aliased HAL.UInt32;
-- PTP Source port identity 2 register
MACSPI2R : aliased MACSPI2R_Register;
-- Log message interval register
MACLMIR : aliased MACLMIR_Register;
end record
with Volatile;
for Ethernet_MAC_Peripheral use record
MACCR at 16#0# range 0 .. 31;
MACECR at 16#4# range 0 .. 31;
MACPFR at 16#8# range 0 .. 31;
MACWTR at 16#C# range 0 .. 31;
MACHT0R at 16#10# range 0 .. 31;
MACHT1R at 16#14# range 0 .. 31;
MACVTR at 16#50# range 0 .. 31;
MACVHTR at 16#58# range 0 .. 31;
MACVIR at 16#60# range 0 .. 31;
MACIVIR at 16#64# range 0 .. 31;
MACQTxFCR at 16#70# range 0 .. 31;
MACRxFCR at 16#90# range 0 .. 31;
MACISR at 16#B0# range 0 .. 31;
MACIER at 16#B4# range 0 .. 31;
MACRxTxSR at 16#B8# range 0 .. 31;
MACPCSR at 16#C0# range 0 .. 31;
MACRWKPFR at 16#C4# range 0 .. 31;
MACLCSR at 16#D0# range 0 .. 31;
MACLTCR at 16#D4# range 0 .. 31;
MACLETR at 16#D8# range 0 .. 31;
MAC1USTCR at 16#DC# range 0 .. 31;
MACVR at 16#110# range 0 .. 31;
MACDR at 16#114# range 0 .. 31;
MACHWF1R at 16#120# range 0 .. 31;
MACHWF2R at 16#124# range 0 .. 31;
MACMDIOAR at 16#200# range 0 .. 31;
MACMDIODR at 16#204# range 0 .. 31;
MACA0HR at 16#300# range 0 .. 31;
MACA0LR at 16#304# range 0 .. 31;
MACA1HR at 16#308# range 0 .. 31;
MACA1LR at 16#30C# range 0 .. 31;
MACA2HR at 16#310# range 0 .. 31;
MACA2LR at 16#314# range 0 .. 31;
MACA3HR at 16#318# range 0 .. 31;
MACA3LR at 16#31C# range 0 .. 31;
MMC_CONTROL at 16#700# range 0 .. 31;
MMC_RX_INTERRUPT at 16#704# range 0 .. 31;
MMC_TX_INTERRUPT at 16#708# range 0 .. 31;
MMC_RX_INTERRUPT_MASK at 16#70C# range 0 .. 31;
MMC_TX_INTERRUPT_MASK at 16#710# range 0 .. 31;
TX_SINGLE_COLLISION_GOOD_PACKETS at 16#74C# range 0 .. 31;
TX_MULTIPLE_COLLISION_GOOD_PACKETS at 16#750# range 0 .. 31;
TX_PACKET_COUNT_GOOD at 16#768# range 0 .. 31;
RX_CRC_ERROR_PACKETS at 16#794# range 0 .. 31;
RX_ALIGNMENT_ERROR_PACKETS at 16#798# range 0 .. 31;
RX_UNICAST_PACKETS_GOOD at 16#7C4# range 0 .. 31;
TX_LPI_USEC_CNTR at 16#7EC# range 0 .. 31;
TX_LPI_TRAN_CNTR at 16#7F0# range 0 .. 31;
RX_LPI_USEC_CNTR at 16#7F4# range 0 .. 31;
RX_LPI_TRAN_CNTR at 16#7F8# range 0 .. 31;
MACL3L4C0R at 16#900# range 0 .. 31;
MACL4A0R at 16#904# range 0 .. 31;
MACL3A00R at 16#910# range 0 .. 31;
MACL3A10R at 16#914# range 0 .. 31;
MACL3A20 at 16#918# range 0 .. 31;
MACL3A30 at 16#91C# range 0 .. 31;
MACL3L4C1R at 16#930# range 0 .. 31;
MACL4A1R at 16#934# range 0 .. 31;
MACL3A01R at 16#940# range 0 .. 31;
MACL3A11R at 16#944# range 0 .. 31;
MACL3A21R at 16#948# range 0 .. 31;
MACL3A31R at 16#94C# range 0 .. 31;
MACARPAR at 16#AE0# range 0 .. 31;
MACTSCR at 16#B00# range 0 .. 31;
MACSSIR at 16#B04# range 0 .. 31;
MACSTSR at 16#B08# range 0 .. 31;
MACSTNR at 16#B0C# range 0 .. 31;
MACSTSUR at 16#B10# range 0 .. 31;
MACSTNUR at 16#B14# range 0 .. 31;
MACTSAR at 16#B18# range 0 .. 31;
MACTSSR at 16#B20# range 0 .. 31;
MACTxTSSNR at 16#B30# range 0 .. 31;
MACTxTSSSR at 16#B34# range 0 .. 31;
MACACR at 16#B40# range 0 .. 31;
MACATSNR at 16#B48# range 0 .. 31;
MACATSSR at 16#B4C# range 0 .. 31;
MACTSIACR at 16#B50# range 0 .. 31;
MACTSEACR at 16#B54# range 0 .. 31;
MACTSICNR at 16#B58# range 0 .. 31;
MACTSECNR at 16#B5C# range 0 .. 31;
MACPPSCR at 16#B70# range 0 .. 31;
MACPPSTTSR at 16#B80# range 0 .. 31;
MACPPSTTNR at 16#B84# range 0 .. 31;
MACPPSIR at 16#B88# range 0 .. 31;
MACPPSWR at 16#B8C# range 0 .. 31;
MACPOCR at 16#BC0# range 0 .. 31;
MACSPI0R at 16#BC4# range 0 .. 31;
MACSPI1R at 16#BC8# range 0 .. 31;
MACSPI2R at 16#BCC# range 0 .. 31;
MACLMIR at 16#BD0# range 0 .. 31;
end record;
-- Ethernet: media access control (MAC)
Ethernet_MAC_Periph : aliased Ethernet_MAC_Peripheral
with Import, Address => Ethernet_MAC_Base;
-- Ethernet: MTL mode register (MTL)
type Ethernet_MTL_Peripheral is record
-- Operating mode Register
MTLOMR : aliased MTLOMR_Register;
-- Interrupt status Register
MTLISR : aliased MTLISR_Register;
-- Tx queue operating mode Register
MTLTxQOMR : aliased MTLTxQOMR_Register;
-- Tx queue underflow register
MTLTxQUR : aliased MTLTxQUR_Register;
-- Tx queue debug Register
MTLTxQDR : aliased MTLTxQDR_Register;
-- Queue interrupt control status Register
MTLQICSR : aliased MTLQICSR_Register;
-- Rx queue operating mode register
MTLRxQOMR : aliased MTLRxQOMR_Register;
-- Rx queue missed packet and overflow counter register
MTLRxQMPOCR : aliased MTLRxQMPOCR_Register;
-- Rx queue debug register
MTLRxQDR : aliased MTLRxQDR_Register;
end record
with Volatile;
for Ethernet_MTL_Peripheral use record
MTLOMR at 16#0# range 0 .. 31;
MTLISR at 16#20# range 0 .. 31;
MTLTxQOMR at 16#100# range 0 .. 31;
MTLTxQUR at 16#104# range 0 .. 31;
MTLTxQDR at 16#108# range 0 .. 31;
MTLQICSR at 16#12C# range 0 .. 31;
MTLRxQOMR at 16#130# range 0 .. 31;
MTLRxQMPOCR at 16#134# range 0 .. 31;
MTLRxQDR at 16#138# range 0 .. 31;
end record;
-- Ethernet: MTL mode register (MTL)
Ethernet_MTL_Periph : aliased Ethernet_MTL_Peripheral
with Import, Address => Ethernet_MTL_Base;
end STM32_SVD.Ethernet;
|
Ada95/src/terminal_interface-curses-forms-field_types-user.ads | arc-aosp/external_libncurses | 35 | 27688 | ------------------------------------------------------------------------------
-- --
-- GNAT ncurses Binding --
-- --
-- Terminal_Interface.Curses.Forms.Field_Types.User --
-- --
-- S P E C --
-- --
------------------------------------------------------------------------------
-- Copyright (c) 1998,2008 Free Software Foundation, Inc. --
-- --
-- Permission is hereby granted, free of charge, to any person obtaining a --
-- copy of this software and associated documentation files (the --
-- "Software"), to deal in the Software without restriction, including --
-- without limitation the rights to use, copy, modify, merge, publish, --
-- distribute, distribute with modifications, sublicense, and/or sell --
-- copies of the Software, and to permit persons to whom the Software is --
-- furnished to do so, subject to the following conditions: --
-- --
-- The above copyright notice and this permission notice shall be included --
-- in all copies or substantial portions of the Software. --
-- --
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS --
-- OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF --
-- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. --
-- IN NO EVENT SHALL THE ABOVE COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, --
-- DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR --
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR --
-- THE USE OR OTHER DEALINGS IN THE SOFTWARE. --
-- --
-- Except as contained in this notice, the name(s) of the above copyright --
-- holders shall not be used in advertising or otherwise to promote the --
-- sale, use or other dealings in this Software without prior written --
-- authorization. --
------------------------------------------------------------------------------
-- Author: <NAME>, 1996
-- Version Control:
-- $Revision: 1.12 $
-- $Date: 2008/07/26 18:49:38 $
-- Binding Version 01.00
------------------------------------------------------------------------------
with Interfaces.C;
package Terminal_Interface.Curses.Forms.Field_Types.User is
pragma Preelaborate (Terminal_Interface.Curses.Forms.Field_Types.User);
subtype C_Int is Interfaces.C.int;
type User_Defined_Field_Type is abstract new Field_Type with null record;
-- This is the root of the mechanism we use to create field types in
-- Ada95. You should your own type derive from this one and implement
-- the Field_Check and Character_Check functions for your own type.
type User_Defined_Field_Type_Access is access all
User_Defined_Field_Type'Class;
function Field_Check
(Fld : Field;
Typ : User_Defined_Field_Type) return Boolean
is abstract;
-- If True is returned, the field is considered valid, otherwise it is
-- invalid.
function Character_Check
(Ch : Character;
Typ : User_Defined_Field_Type) return Boolean
is abstract;
-- If True is returned, the character is considered as valid for the
-- field, otherwise as invalid.
procedure Set_Field_Type (Fld : in Field;
Typ : in User_Defined_Field_Type);
-- This should work for all types derived from User_Defined_Field_Type.
-- No need to reimplement it for your derived type.
-- +----------------------------------------------------------------------
-- | Private Part.
-- | Used by the Choice child package.
private
function C_Generic_Type return C_Field_Type;
function Generic_Field_Check (Fld : Field;
Usr : System.Address) return C_Int;
pragma Convention (C, Generic_Field_Check);
-- This is the generic Field_Check_Function for the low-level fieldtype
-- representing all the User_Defined_Field_Type derivates. It routes
-- the call to the Field_Check implementation for the type.
function Generic_Char_Check (Ch : C_Int;
Usr : System.Address) return C_Int;
pragma Convention (C, Generic_Char_Check);
-- This is the generic Char_Check_Function for the low-level fieldtype
-- representing all the User_Defined_Field_Type derivates. It routes
-- the call to the Character_Check implementation for the type.
end Terminal_Interface.Curses.Forms.Field_Types.User;
|
test/Fail/Issue958.agda | cruhland/agda | 1,989 | 1929 |
postulate FunctorOps : Set
module FunctorOps (ops : FunctorOps) where
postulate map : Set
postulate IsFunctor : Set
module IsFunctor (fun : IsFunctor) where
postulate ops : FunctorOps
open FunctorOps ops public
-- inside here `FunctorOps.map ops` gets printed as `map`
open IsFunctor
-- out here it should too
test : (F : IsFunctor) → FunctorOps.map (ops F)
test F = F
-- EXPECTED: IsFunctor !=< map F
|
alloy4fun_models/trashltl/models/9/WN3dWTaEB82RW6H43.als | Kaixi26/org.alloytools.alloy | 0 | 3863 | <gh_stars>0
open main
pred idWN3dWTaEB82RW6H43_prop10 {
always all f:Protected | always f in Protected
}
pred __repair { idWN3dWTaEB82RW6H43_prop10 }
check __repair { idWN3dWTaEB82RW6H43_prop10 <=> prop10o } |
P6/P6Judger - 100 testpoints/testpoint/testpoint97.asm | flyinglandlord/BUAA-CO-2021 | 5 | 100104 | ori $1, $0, 15
ori $2, $0, 7
ori $3, $0, 3
ori $4, $0, 15
sw $3, 0($0)
sw $4, 4($0)
sw $4, 8($0)
sw $2, 12($0)
sw $4, 16($0)
sw $1, 20($0)
sw $1, 24($0)
sw $1, 28($0)
sw $3, 32($0)
sw $2, 36($0)
sw $2, 40($0)
sw $2, 44($0)
sw $1, 48($0)
sw $1, 52($0)
sw $2, 56($0)
sw $3, 60($0)
sw $4, 64($0)
sw $1, 68($0)
sw $4, 72($0)
sw $2, 76($0)
sw $4, 80($0)
sw $3, 84($0)
sw $4, 88($0)
sw $4, 92($0)
sw $1, 96($0)
sw $1, 100($0)
sw $2, 104($0)
sw $4, 108($0)
sw $2, 112($0)
sw $2, 116($0)
sw $3, 120($0)
sw $2, 124($0)
div $2, $2
mthi $2
lui $4, 9
divu $4, $4
TAG1:
bltz $4, TAG2
addiu $2, $4, 0
bltz $4, TAG2
lui $3, 12
TAG2:
addiu $2, $3, 15
lui $4, 7
bgez $4, TAG3
sll $0, $0, 0
TAG3:
addu $2, $4, $4
sll $0, $0, 0
bne $2, $2, TAG4
sll $0, $0, 0
TAG4:
addiu $4, $2, 13
lui $1, 8
bgtz $4, TAG5
sll $0, $0, 0
TAG5:
slti $2, $3, 4
multu $2, $2
beq $2, $3, TAG6
mult $2, $2
TAG6:
sltiu $4, $2, 3
blez $2, TAG7
multu $2, $2
mflo $4
TAG7:
xori $3, $4, 9
srlv $1, $4, $3
lui $4, 15
beq $4, $3, TAG8
TAG8:
sll $0, $0, 0
lui $4, 12
lui $1, 7
beq $4, $1, TAG9
TAG9:
multu $1, $1
xor $2, $1, $1
sll $0, $0, 0
sll $0, $0, 0
TAG10:
bgtz $4, TAG11
lui $4, 12
bne $4, $4, TAG11
multu $4, $4
TAG11:
sll $0, $0, 0
sll $0, $0, 0
lui $1, 3
lui $2, 9
TAG12:
bgtz $2, TAG13
mult $2, $2
andi $3, $2, 14
mflo $1
TAG13:
sll $0, $0, 0
mflo $3
blez $3, TAG14
sll $0, $0, 0
TAG14:
bne $1, $1, TAG15
divu $1, $1
lui $1, 10
lui $4, 12
TAG15:
sltu $1, $4, $4
sll $0, $0, 0
lui $1, 2
multu $1, $1
TAG16:
mflo $3
bgtz $1, TAG17
mflo $4
sb $4, 0($4)
TAG17:
lh $2, 0($4)
lh $1, 0($4)
sb $4, 0($2)
sb $4, 0($2)
TAG18:
sb $1, 0($1)
mtlo $1
mfhi $4
lhu $1, 0($4)
TAG19:
mfhi $2
lui $1, 3
and $3, $2, $2
mthi $1
TAG20:
mfhi $1
mthi $3
lui $1, 6
sll $0, $0, 0
TAG21:
sll $0, $0, 0
sll $0, $0, 0
sll $0, $0, 0
mtlo $2
TAG22:
bltz $2, TAG23
mthi $2
lui $4, 11
multu $4, $4
TAG23:
mult $4, $4
addiu $1, $4, 14
sll $0, $0, 0
multu $4, $4
TAG24:
mtlo $1
sll $0, $0, 0
bgtz $1, TAG25
mflo $2
TAG25:
sll $0, $0, 0
mult $2, $2
lui $1, 3
mflo $3
TAG26:
bgtz $3, TAG27
mthi $3
sltiu $3, $3, 3
lb $4, 0($3)
TAG27:
divu $4, $4
lui $1, 6
lui $4, 11
mult $4, $4
TAG28:
subu $3, $4, $4
sltiu $1, $4, 12
xor $3, $3, $3
or $3, $3, $1
TAG29:
lui $3, 9
addiu $4, $3, 15
sllv $2, $4, $3
srl $3, $2, 12
TAG30:
mfhi $1
sll $4, $3, 13
addiu $1, $4, 10
sll $0, $0, 0
TAG31:
sll $0, $0, 0
addiu $4, $3, 1
addu $2, $3, $3
lbu $1, -288($2)
TAG32:
bgez $1, TAG33
sltu $1, $1, $1
bgez $1, TAG33
divu $1, $1
TAG33:
lui $2, 9
bgtz $1, TAG34
mflo $1
beq $1, $2, TAG34
TAG34:
mfhi $2
lbu $4, 0($1)
lui $2, 12
lui $1, 2
TAG35:
bne $1, $1, TAG36
lui $1, 12
sll $0, $0, 0
mflo $3
TAG36:
sllv $1, $3, $3
bgtz $3, TAG37
mtlo $3
mfhi $1
TAG37:
sltu $1, $1, $1
lui $3, 4
lui $4, 6
bltz $3, TAG38
TAG38:
lui $2, 5
addu $1, $2, $4
blez $1, TAG39
sll $0, $0, 0
TAG39:
mult $1, $1
lui $3, 6
xori $3, $1, 10
bgtz $3, TAG40
TAG40:
sll $0, $0, 0
sll $0, $0, 0
bne $3, $3, TAG41
mthi $3
TAG41:
mfhi $4
blez $4, TAG42
addiu $2, $4, 1
mult $4, $2
TAG42:
sll $0, $0, 0
mflo $3
sll $0, $0, 0
mflo $1
TAG43:
or $1, $1, $1
lui $3, 5
sll $3, $1, 6
sll $0, $0, 0
TAG44:
sll $0, $0, 0
slti $3, $3, 11
srlv $1, $3, $3
addi $4, $3, 7
TAG45:
lb $3, 0($4)
bgtz $3, TAG46
xori $2, $3, 3
addu $3, $2, $4
TAG46:
mfhi $3
lb $2, 0($3)
lui $3, 6
bltz $3, TAG47
TAG47:
lui $2, 7
bne $3, $2, TAG48
andi $3, $3, 8
mfhi $4
TAG48:
bgez $4, TAG49
divu $4, $4
beq $4, $4, TAG49
mfhi $3
TAG49:
lbu $4, 0($3)
srlv $1, $4, $3
and $4, $3, $4
mfhi $3
TAG50:
sw $3, 0($3)
multu $3, $3
multu $3, $3
blez $3, TAG51
TAG51:
sh $3, 0($3)
bgez $3, TAG52
lui $2, 11
lh $3, 0($3)
TAG52:
add $2, $3, $3
lui $1, 5
slti $2, $2, 5
mfhi $1
TAG53:
mtlo $1
lw $4, 0($1)
blez $1, TAG54
slt $1, $4, $4
TAG54:
slti $4, $1, 8
subu $4, $4, $4
sh $1, 0($4)
bne $1, $4, TAG55
TAG55:
multu $4, $4
lbu $3, 0($4)
lh $4, 0($4)
sw $4, 0($3)
TAG56:
mult $4, $4
bne $4, $4, TAG57
srlv $2, $4, $4
xor $1, $4, $2
TAG57:
sh $1, 0($1)
mthi $1
lw $1, 0($1)
slt $4, $1, $1
TAG58:
lui $2, 9
lui $4, 11
lui $3, 2
srlv $3, $4, $4
TAG59:
sll $0, $0, 0
blez $4, TAG60
sll $0, $0, 0
sll $0, $0, 0
TAG60:
beq $3, $3, TAG61
mthi $3
mtlo $3
sh $3, 0($3)
TAG61:
lui $4, 15
or $4, $3, $4
bne $4, $3, TAG62
sll $0, $0, 0
TAG62:
blez $4, TAG63
sll $0, $0, 0
bltz $4, TAG63
mult $4, $4
TAG63:
lui $2, 13
lui $1, 7
sll $0, $0, 0
lui $3, 11
TAG64:
multu $3, $3
addiu $4, $3, 9
sll $0, $0, 0
lui $3, 4
TAG65:
sll $0, $0, 0
andi $2, $3, 13
lbu $1, 0($2)
mthi $2
TAG66:
mtlo $1
mthi $1
andi $1, $1, 7
lui $1, 4
TAG67:
bgtz $1, TAG68
sll $0, $0, 0
lhu $4, 0($1)
mfhi $2
TAG68:
mtlo $2
sw $2, 0($2)
srlv $2, $2, $2
blez $2, TAG69
TAG69:
lui $2, 1
lui $4, 6
subu $3, $2, $2
mfhi $4
TAG70:
mtlo $4
beq $4, $4, TAG71
mthi $4
srl $2, $4, 2
TAG71:
multu $2, $2
ori $2, $2, 11
beq $2, $2, TAG72
srl $4, $2, 11
TAG72:
bgtz $4, TAG73
mflo $1
multu $4, $1
divu $4, $1
TAG73:
lbu $1, 0($1)
beq $1, $1, TAG74
lui $2, 13
lui $3, 0
TAG74:
addiu $1, $3, 15
sb $3, 0($3)
bgez $3, TAG75
multu $1, $1
TAG75:
bltz $1, TAG76
sb $1, 0($1)
sllv $4, $1, $1
lb $4, 0($1)
TAG76:
mthi $4
mflo $3
sh $4, -225($3)
lui $2, 2
TAG77:
divu $2, $2
bgtz $2, TAG78
lui $3, 2
mtlo $2
TAG78:
slt $4, $3, $3
mtlo $4
sll $4, $4, 10
bne $3, $4, TAG79
TAG79:
xori $3, $4, 13
beq $3, $3, TAG80
sllv $3, $3, $4
bne $3, $3, TAG80
TAG80:
lui $4, 5
multu $4, $4
mfhi $4
mult $3, $4
TAG81:
bne $4, $4, TAG82
ori $1, $4, 9
beq $4, $1, TAG82
div $4, $1
TAG82:
lui $4, 15
mtlo $1
sll $0, $0, 0
xor $3, $4, $4
TAG83:
or $2, $3, $3
beq $3, $2, TAG84
sb $2, 0($3)
lui $3, 5
TAG84:
blez $3, TAG85
sw $3, 0($3)
sh $3, 0($3)
lw $3, 0($3)
TAG85:
srlv $3, $3, $3
bgez $3, TAG86
lui $4, 9
sll $1, $4, 6
TAG86:
beq $1, $1, TAG87
lui $2, 6
mthi $1
mflo $3
TAG87:
mtlo $3
mult $3, $3
lui $2, 13
mfhi $3
TAG88:
bgtz $3, TAG89
sh $3, 0($3)
sra $1, $3, 10
mflo $2
TAG89:
mflo $2
addiu $4, $2, 11
mflo $1
mtlo $4
TAG90:
slti $4, $1, 13
addi $3, $1, 6
lui $4, 6
mfhi $1
TAG91:
lhu $2, 0($1)
srav $4, $2, $2
lbu $4, 0($2)
lw $4, 0($4)
TAG92:
bgez $4, TAG93
ori $2, $4, 13
bne $4, $2, TAG93
mfhi $4
TAG93:
mthi $4
mthi $4
multu $4, $4
sw $4, 0($4)
TAG94:
lui $1, 8
mthi $1
div $1, $1
or $4, $1, $4
TAG95:
andi $3, $4, 8
sllv $4, $3, $3
sltiu $2, $4, 3
beq $3, $3, TAG96
TAG96:
mtlo $2
mthi $2
sb $2, 0($2)
lui $3, 4
TAG97:
bne $3, $3, TAG98
sll $0, $0, 0
lb $3, 0($4)
mfhi $4
TAG98:
addiu $4, $4, 1
sb $4, 0($4)
beq $4, $4, TAG99
subu $3, $4, $4
TAG99:
mthi $3
bltz $3, TAG100
add $4, $3, $3
multu $4, $4
TAG100:
sllv $2, $4, $4
or $3, $2, $4
sh $3, 0($4)
bgtz $2, TAG101
TAG101:
mflo $2
multu $2, $2
mtlo $3
blez $2, TAG102
TAG102:
lh $3, 0($2)
lui $2, 12
div $2, $2
mflo $3
TAG103:
lui $2, 15
lui $4, 15
mfhi $3
mthi $2
TAG104:
lhu $2, 0($3)
mflo $1
lui $3, 4
srav $1, $2, $2
TAG105:
xor $2, $1, $1
sb $1, 0($2)
lhu $4, 0($1)
sw $1, 0($2)
TAG106:
mult $4, $4
multu $4, $4
lb $4, 0($4)
multu $4, $4
TAG107:
addi $2, $4, 8
multu $4, $4
addu $4, $2, $4
mtlo $2
TAG108:
sra $1, $4, 1
bgtz $4, TAG109
lhu $4, 0($4)
multu $1, $4
TAG109:
sb $4, 0($4)
lbu $2, 0($4)
div $4, $2
nor $4, $4, $4
TAG110:
mthi $4
blez $4, TAG111
mflo $3
lhu $4, 0($3)
TAG111:
sll $0, $0, 0
lui $1, 9
srav $1, $3, $1
sra $1, $1, 8
TAG112:
lui $1, 2
sll $0, $0, 0
addiu $2, $1, 2
multu $1, $1
TAG113:
and $3, $2, $2
bne $3, $3, TAG114
andi $3, $3, 4
mthi $2
TAG114:
beq $3, $3, TAG115
lbu $2, 0($3)
mfhi $3
mult $3, $3
TAG115:
addi $3, $3, 0
beq $3, $3, TAG116
mtlo $3
sltiu $4, $3, 7
TAG116:
lui $1, 13
mthi $4
sw $4, 16($4)
mtlo $4
TAG117:
and $3, $1, $1
addu $2, $3, $3
mult $3, $2
addu $2, $1, $3
TAG118:
div $2, $2
mtlo $2
addiu $2, $2, 4
bne $2, $2, TAG119
TAG119:
addiu $2, $2, 15
sll $3, $2, 5
sll $0, $0, 0
beq $2, $3, TAG120
TAG120:
mfhi $1
addu $3, $3, $3
lui $1, 15
lui $4, 12
TAG121:
mflo $3
sll $0, $0, 0
sll $0, $0, 0
lui $2, 1
TAG122:
beq $2, $2, TAG123
divu $2, $2
bgez $2, TAG123
lui $4, 1
TAG123:
beq $4, $4, TAG124
sll $0, $0, 0
mthi $4
blez $4, TAG124
TAG124:
mtlo $1
bne $1, $1, TAG125
xor $3, $1, $1
mthi $3
TAG125:
sll $2, $3, 7
mflo $4
bltz $3, TAG126
sllv $4, $3, $2
TAG126:
mflo $1
mthi $1
div $1, $1
multu $4, $1
TAG127:
mfhi $1
lw $4, 0($1)
lb $4, 0($1)
sltiu $1, $1, 6
TAG128:
addiu $1, $1, 12
bne $1, $1, TAG129
lui $1, 15
slt $3, $1, $1
TAG129:
addu $1, $3, $3
sw $3, 0($1)
mfhi $1
mtlo $1
TAG130:
mflo $3
addi $1, $3, 11
lui $4, 10
bltz $1, TAG131
TAG131:
sll $0, $0, 0
lui $2, 15
bgtz $2, TAG132
andi $3, $2, 0
TAG132:
bne $3, $3, TAG133
mult $3, $3
lbu $4, 0($3)
multu $3, $3
TAG133:
lui $4, 2
blez $4, TAG134
sll $0, $0, 0
bgez $4, TAG134
TAG134:
mfhi $4
bgez $4, TAG135
lui $4, 7
blez $4, TAG135
TAG135:
slti $2, $4, 10
bltz $4, TAG136
subu $4, $2, $4
or $2, $2, $4
TAG136:
lui $1, 8
andi $3, $1, 13
or $3, $3, $2
bgez $2, TAG137
TAG137:
sll $0, $0, 0
bne $2, $3, TAG138
lui $3, 10
sll $0, $0, 0
TAG138:
addiu $4, $1, 1
lui $2, 2
lui $1, 0
sra $4, $1, 9
TAG139:
sltu $1, $4, $4
mult $1, $1
beq $4, $1, TAG140
mfhi $2
TAG140:
bgez $2, TAG141
mult $2, $2
sb $2, 0($2)
bne $2, $2, TAG141
TAG141:
sltiu $4, $2, 7
lhu $4, 0($2)
mtlo $2
mthi $2
TAG142:
lui $2, 3
bne $2, $4, TAG143
lui $1, 11
lui $2, 14
TAG143:
mtlo $2
mtlo $2
srl $3, $2, 9
mtlo $2
TAG144:
mthi $3
lui $4, 3
slti $3, $4, 12
mthi $3
TAG145:
add $1, $3, $3
sltu $2, $1, $1
blez $2, TAG146
slt $4, $3, $3
TAG146:
multu $4, $4
lui $1, 0
bne $4, $1, TAG147
lhu $1, 0($4)
TAG147:
lui $2, 3
bne $1, $1, TAG148
mthi $1
mflo $1
TAG148:
lui $1, 1
lui $4, 10
lui $4, 10
beq $1, $4, TAG149
TAG149:
xori $2, $4, 7
mthi $4
lui $4, 6
mflo $1
TAG150:
or $2, $1, $1
lui $2, 6
bne $2, $2, TAG151
subu $3, $1, $2
TAG151:
mflo $4
lui $3, 14
mthi $3
lui $2, 3
TAG152:
bgtz $2, TAG153
divu $2, $2
mflo $3
lb $2, 0($2)
TAG153:
mthi $2
srav $2, $2, $2
beq $2, $2, TAG154
sll $0, $0, 0
TAG154:
sw $4, 0($4)
addi $1, $4, 0
ori $3, $1, 3
mult $3, $4
TAG155:
lb $2, 0($3)
addu $2, $2, $3
mfhi $4
mthi $3
TAG156:
mfhi $2
add $1, $4, $2
bgez $2, TAG157
mflo $4
TAG157:
multu $4, $4
sltiu $1, $4, 12
andi $1, $1, 6
mflo $2
TAG158:
lbu $4, 0($2)
mult $4, $4
mfhi $1
mfhi $4
TAG159:
lui $4, 11
mthi $4
lui $4, 2
sll $0, $0, 0
TAG160:
sltiu $4, $4, 4
mult $4, $4
srlv $3, $4, $4
srav $2, $4, $3
TAG161:
sra $1, $2, 14
mtlo $1
mthi $1
multu $1, $2
TAG162:
beq $1, $1, TAG163
lui $3, 14
sb $1, 0($3)
slti $1, $1, 14
TAG163:
lbu $3, 0($1)
sll $4, $3, 6
mfhi $2
beq $1, $4, TAG164
TAG164:
mtlo $2
sllv $3, $2, $2
beq $2, $3, TAG165
sh $2, 0($2)
TAG165:
lui $2, 3
lui $2, 13
bgtz $3, TAG166
sll $0, $0, 0
TAG166:
mtlo $2
sll $0, $0, 0
lui $1, 11
sll $0, $0, 0
TAG167:
sltu $1, $4, $4
mtlo $4
mthi $4
bne $4, $4, TAG168
TAG168:
mtlo $1
sb $1, 0($1)
srav $1, $1, $1
sltu $1, $1, $1
TAG169:
or $1, $1, $1
bgez $1, TAG170
mtlo $1
mfhi $1
TAG170:
srav $1, $1, $1
lui $1, 6
addu $1, $1, $1
mtlo $1
TAG171:
xori $1, $1, 8
bgtz $1, TAG172
sll $0, $0, 0
mfhi $3
TAG172:
bne $3, $3, TAG173
mult $3, $3
sw $3, 0($3)
sltiu $2, $3, 6
TAG173:
beq $2, $2, TAG174
lbu $1, 0($2)
mtlo $2
mtlo $2
TAG174:
mthi $1
bltz $1, TAG175
xori $2, $1, 9
mfhi $2
TAG175:
mult $2, $2
mult $2, $2
mfhi $3
bne $3, $2, TAG176
TAG176:
sb $3, 0($3)
slti $3, $3, 3
bgez $3, TAG177
sb $3, 0($3)
TAG177:
bne $3, $3, TAG178
mfhi $1
sra $2, $3, 4
lui $2, 8
TAG178:
nor $1, $2, $2
slt $2, $2, $1
mult $1, $2
sltiu $2, $2, 1
TAG179:
blez $2, TAG180
mfhi $3
mflo $3
multu $2, $2
TAG180:
mfhi $4
sra $3, $3, 8
sll $4, $3, 10
sw $4, 0($3)
TAG181:
mflo $1
xori $3, $1, 9
sb $4, 0($3)
lui $1, 1
TAG182:
sra $2, $1, 12
srl $3, $2, 4
sll $3, $1, 2
lui $2, 10
TAG183:
ori $1, $2, 3
lui $3, 4
slti $3, $3, 4
bgez $2, TAG184
TAG184:
lh $2, 0($3)
mfhi $2
bgez $2, TAG185
mthi $2
TAG185:
srlv $4, $2, $2
beq $2, $2, TAG186
lhu $2, 0($4)
mfhi $3
TAG186:
bgez $3, TAG187
mflo $3
mfhi $3
divu $3, $3
TAG187:
mthi $3
beq $3, $3, TAG188
lui $1, 0
sltu $1, $3, $3
TAG188:
sh $1, 0($1)
lbu $4, 0($1)
lui $3, 5
beq $1, $4, TAG189
TAG189:
divu $3, $3
mtlo $3
mthi $3
bltz $3, TAG190
TAG190:
mfhi $1
lui $4, 14
sll $0, $0, 0
sltu $4, $4, $4
TAG191:
lhu $1, 0($4)
mtlo $4
mult $1, $1
srlv $1, $4, $4
TAG192:
sb $1, 0($1)
lui $3, 15
sb $3, 0($1)
andi $4, $1, 6
TAG193:
multu $4, $4
xori $2, $4, 9
or $1, $2, $2
slt $3, $1, $2
TAG194:
bgtz $3, TAG195
subu $4, $3, $3
sh $3, 0($3)
ori $1, $3, 5
TAG195:
lbu $3, 0($1)
mflo $4
nor $1, $3, $1
bne $1, $1, TAG196
TAG196:
mflo $3
bgez $1, TAG197
sw $1, 0($3)
sh $3, 6($1)
TAG197:
lui $2, 1
beq $3, $3, TAG198
sh $2, 0($3)
divu $2, $2
TAG198:
mthi $2
sll $0, $0, 0
mfhi $3
sll $0, $0, 0
TAG199:
nor $1, $1, $1
mult $1, $1
sb $1, 0($1)
div $1, $1
TAG200:
div $1, $1
beq $1, $1, TAG201
sra $3, $1, 12
or $2, $1, $3
TAG201:
sll $0, $0, 0
mfhi $3
mult $2, $3
beq $4, $2, TAG202
TAG202:
lui $2, 13
bgtz $2, TAG203
addiu $4, $3, 1
or $2, $4, $4
TAG203:
sllv $1, $2, $2
sll $0, $0, 0
srav $3, $2, $1
mflo $4
TAG204:
ori $1, $4, 1
mfhi $1
lhu $1, 0($4)
lui $2, 9
TAG205:
mthi $2
beq $2, $2, TAG206
div $2, $2
beq $2, $2, TAG206
TAG206:
andi $3, $2, 7
bgtz $2, TAG207
srlv $3, $3, $2
lui $1, 2
TAG207:
lui $3, 10
mtlo $3
subu $2, $3, $3
mthi $1
TAG208:
multu $2, $2
lui $3, 4
bne $2, $2, TAG209
lh $4, 0($2)
TAG209:
sh $4, 0($4)
lh $4, 0($4)
lui $4, 12
mfhi $3
TAG210:
xori $2, $3, 2
xor $4, $3, $2
lui $4, 5
bgtz $4, TAG211
TAG211:
mthi $4
multu $4, $4
lui $3, 11
sll $0, $0, 0
TAG212:
and $3, $3, $3
beq $3, $3, TAG213
mtlo $3
mthi $3
TAG213:
mflo $3
divu $3, $3
bgtz $3, TAG214
mthi $3
TAG214:
sll $0, $0, 0
bne $3, $3, TAG215
ori $3, $3, 2
srlv $2, $3, $3
TAG215:
mflo $2
beq $2, $2, TAG216
sb $2, 0($2)
beq $2, $2, TAG216
TAG216:
mtlo $2
lb $1, 0($2)
bne $1, $1, TAG217
xor $3, $2, $2
TAG217:
xor $2, $3, $3
beq $2, $2, TAG218
ori $2, $2, 10
multu $2, $2
TAG218:
mthi $2
mflo $3
sra $1, $2, 10
mult $3, $3
TAG219:
xori $1, $1, 2
blez $1, TAG220
sb $1, 0($1)
lb $4, 0($1)
TAG220:
mflo $3
mfhi $1
blez $4, TAG221
lui $3, 11
TAG221:
sll $0, $0, 0
mtlo $3
mthi $3
sll $0, $0, 0
TAG222:
lh $2, 0($2)
mflo $4
mtlo $4
mfhi $1
TAG223:
srl $3, $1, 14
mult $1, $1
sll $2, $1, 15
slti $3, $3, 2
TAG224:
blez $3, TAG225
multu $3, $3
sw $3, 0($3)
slti $2, $3, 7
TAG225:
addiu $4, $2, 9
xor $4, $2, $4
xor $3, $2, $4
beq $3, $4, TAG226
TAG226:
mthi $3
lui $4, 7
sra $3, $3, 7
mthi $3
TAG227:
sll $0, $0, 0
sll $0, $0, 0
mtlo $3
beq $3, $3, TAG228
TAG228:
sll $0, $0, 0
lui $2, 7
mult $2, $4
mtlo $4
TAG229:
sll $0, $0, 0
sll $0, $0, 0
sll $0, $0, 0
sll $0, $0, 0
TAG230:
lui $3, 0
mtlo $3
mtlo $4
bne $3, $3, TAG231
TAG231:
lui $4, 11
bgtz $3, TAG232
lh $4, 0($3)
mult $4, $4
TAG232:
sll $0, $0, 0
addi $1, $3, 14
divu $1, $4
bgtz $4, TAG233
TAG233:
lui $1, 4
sltu $2, $1, $1
lui $4, 15
slti $1, $2, 15
TAG234:
lui $4, 10
beq $1, $1, TAG235
lui $2, 3
sb $2, 0($1)
TAG235:
sll $0, $0, 0
div $2, $2
lui $2, 13
add $3, $3, $2
TAG236:
sltu $1, $3, $3
lui $1, 13
slti $1, $3, 10
lhu $3, 0($1)
TAG237:
lui $1, 6
mflo $4
sh $4, -256($3)
bltz $4, TAG238
TAG238:
mfhi $3
bgtz $3, TAG239
mfhi $2
lbu $1, 0($4)
TAG239:
mtlo $1
addu $4, $1, $1
mfhi $3
mthi $4
TAG240:
mtlo $3
andi $3, $3, 1
sh $3, 0($3)
lui $4, 8
TAG241:
mult $4, $4
div $4, $4
bltz $4, TAG242
mflo $3
TAG242:
beq $3, $3, TAG243
sb $3, 0($3)
lb $4, 0($3)
lui $1, 0
TAG243:
mtlo $1
bgtz $1, TAG244
lui $4, 11
mflo $3
TAG244:
multu $3, $3
mult $3, $3
lw $4, 0($3)
bne $4, $4, TAG245
TAG245:
div $4, $4
beq $4, $4, TAG246
sll $0, $0, 0
mthi $4
TAG246:
sll $0, $0, 0
divu $4, $4
andi $3, $2, 5
mthi $4
TAG247:
lui $2, 6
lhu $4, 0($3)
beq $4, $3, TAG248
lui $2, 3
TAG248:
beq $2, $2, TAG249
subu $3, $2, $2
xori $4, $3, 15
addu $2, $4, $3
TAG249:
sll $0, $0, 0
bgez $2, TAG250
mtlo $2
mthi $2
TAG250:
lui $3, 4
bgtz $2, TAG251
lui $1, 0
andi $3, $3, 11
TAG251:
mfhi $2
multu $2, $2
sll $4, $3, 12
blez $3, TAG252
TAG252:
mthi $4
mthi $4
bgtz $4, TAG253
sra $2, $4, 3
TAG253:
beq $2, $2, TAG254
mthi $2
lbu $2, 0($2)
and $3, $2, $2
TAG254:
ori $3, $3, 15
lui $4, 7
sll $0, $0, 0
div $3, $3
TAG255:
sll $0, $0, 0
mfhi $3
lbu $1, 0($3)
ori $4, $3, 9
TAG256:
mtlo $4
beq $4, $4, TAG257
lui $3, 8
lb $4, 0($3)
TAG257:
sb $4, 0($4)
lbu $2, 0($4)
lui $3, 10
mult $3, $4
TAG258:
blez $3, TAG259
subu $3, $3, $3
mult $3, $3
mfhi $1
TAG259:
sub $2, $1, $1
mult $1, $1
bne $1, $2, TAG260
ori $4, $2, 8
TAG260:
xor $1, $4, $4
srl $1, $4, 13
beq $4, $1, TAG261
lh $3, 0($1)
TAG261:
mult $3, $3
andi $2, $3, 0
lhu $1, -256($3)
mflo $1
TAG262:
slti $1, $1, 6
sllv $4, $1, $1
sub $2, $4, $1
lui $4, 2
TAG263:
lui $4, 4
beq $4, $4, TAG264
andi $1, $4, 14
beq $4, $4, TAG264
TAG264:
xori $3, $1, 10
bne $1, $3, TAG265
sllv $4, $3, $3
sh $4, 0($1)
TAG265:
sb $4, -10240($4)
sra $1, $4, 7
lbu $3, -10240($4)
multu $1, $1
TAG266:
sll $1, $3, 13
mult $1, $3
lui $1, 7
lui $1, 4
TAG267:
xor $4, $1, $1
mult $4, $4
bne $4, $4, TAG268
sltu $3, $1, $1
TAG268:
multu $3, $3
blez $3, TAG269
lhu $1, 0($3)
ori $1, $1, 5
TAG269:
mult $1, $1
bltz $1, TAG270
multu $1, $1
beq $1, $1, TAG270
TAG270:
div $1, $1
mfhi $1
mflo $4
sltiu $3, $4, 12
TAG271:
lui $4, 14
bne $4, $3, TAG272
mtlo $3
mthi $3
TAG272:
mtlo $4
sll $0, $0, 0
sll $0, $0, 0
div $4, $3
TAG273:
bne $3, $3, TAG274
addu $2, $3, $3
sh $2, 0($2)
mthi $2
TAG274:
lhu $1, 0($2)
mtlo $1
sh $2, 0($1)
lui $1, 7
TAG275:
sll $0, $0, 0
mtlo $1
bgez $1, TAG276
sll $0, $0, 0
TAG276:
addu $2, $1, $1
multu $2, $2
lui $1, 8
mfhi $1
TAG277:
srlv $4, $1, $1
subu $3, $4, $1
mult $4, $4
mthi $1
TAG278:
sll $0, $0, 0
lh $3, 184($3)
or $3, $3, $3
blez $3, TAG279
TAG279:
lui $1, 9
sb $3, -256($3)
div $3, $3
sll $0, $0, 0
TAG280:
bne $4, $4, TAG281
mfhi $2
lh $4, 0($2)
bne $4, $4, TAG281
TAG281:
multu $4, $4
subu $4, $4, $4
mtlo $4
mflo $3
TAG282:
lui $2, 12
bgtz $2, TAG283
lui $1, 14
addiu $3, $2, 10
TAG283:
sw $3, 0($3)
mult $3, $3
mfhi $3
mtlo $3
TAG284:
sw $3, 0($3)
andi $2, $3, 10
mfhi $1
mtlo $3
TAG285:
beq $1, $1, TAG286
mthi $1
lhu $4, 0($1)
mflo $3
TAG286:
mtlo $3
bltz $3, TAG287
mult $3, $3
addu $1, $3, $3
TAG287:
lui $1, 4
andi $3, $1, 15
blez $1, TAG288
mfhi $1
TAG288:
and $4, $1, $1
srl $3, $1, 10
bgez $3, TAG289
srlv $4, $1, $3
TAG289:
bltz $4, TAG290
lh $4, 0($4)
mflo $3
mflo $1
TAG290:
multu $1, $1
lb $1, 0($1)
sub $4, $1, $1
lui $2, 2
TAG291:
sll $3, $2, 12
mthi $2
subu $2, $3, $2
sll $0, $0, 0
TAG292:
addu $3, $2, $2
bgez $3, TAG293
mult $3, $2
add $1, $3, $3
TAG293:
lhu $2, 0($1)
slti $4, $1, 8
lbu $2, 0($2)
or $1, $2, $4
TAG294:
divu $1, $1
lui $3, 0
mthi $1
mtlo $1
TAG295:
sh $3, 0($3)
lui $3, 13
sll $0, $0, 0
sll $0, $0, 0
TAG296:
lui $4, 3
xori $1, $4, 11
bltz $4, TAG297
addu $3, $1, $1
TAG297:
mtlo $3
andi $3, $3, 1
multu $3, $3
mflo $3
TAG298:
andi $4, $3, 1
lhu $1, 0($3)
lh $4, 0($1)
bltz $4, TAG299
TAG299:
sll $4, $4, 11
mthi $4
mult $4, $4
bgtz $4, TAG300
TAG300:
multu $4, $4
mfhi $3
mfhi $2
lui $1, 13
TAG301:
mfhi $1
bltz $1, TAG302
sh $1, 0($1)
mtlo $1
TAG302:
sb $1, 0($1)
sh $1, 0($1)
mfhi $1
mfhi $2
TAG303:
lui $2, 3
sll $0, $0, 0
bne $2, $2, TAG304
subu $4, $2, $2
TAG304:
bne $4, $4, TAG305
mult $4, $4
mult $4, $4
lh $4, 0($4)
TAG305:
mfhi $2
slti $4, $2, 10
slti $2, $4, 6
mthi $2
TAG306:
mtlo $2
mfhi $3
mfhi $1
beq $2, $2, TAG307
TAG307:
lb $2, 0($1)
mflo $2
sb $2, 0($1)
addiu $3, $2, 12
TAG308:
mthi $3
bgez $3, TAG309
mthi $3
mtlo $3
TAG309:
or $1, $3, $3
lbu $2, 0($3)
lui $3, 3
srlv $4, $3, $3
TAG310:
mfhi $3
bne $4, $3, TAG311
sll $0, $0, 0
subu $3, $3, $4
TAG311:
mtlo $3
mfhi $1
lui $2, 9
sltu $3, $3, $3
TAG312:
bgez $3, TAG313
mtlo $3
mfhi $1
sw $1, 0($1)
TAG313:
mthi $1
slti $1, $1, 15
or $3, $1, $1
sb $3, 0($1)
TAG314:
sb $3, 0($3)
sb $3, 0($3)
sltiu $4, $3, 2
xori $3, $4, 10
TAG315:
slt $3, $3, $3
lb $1, 0($3)
sllv $3, $3, $1
sh $3, 0($1)
TAG316:
mflo $2
sb $3, 0($2)
lui $3, 2
lui $2, 12
TAG317:
bgtz $2, TAG318
mflo $3
mflo $3
beq $3, $3, TAG318
TAG318:
lui $3, 1
mfhi $4
bgtz $3, TAG319
divu $4, $3
TAG319:
addiu $3, $4, 9
lui $3, 15
bgtz $3, TAG320
nor $4, $4, $3
TAG320:
divu $4, $4
sll $0, $0, 0
bgtz $4, TAG321
xor $1, $4, $4
TAG321:
sltiu $3, $1, 3
sw $3, 0($1)
bne $1, $1, TAG322
lh $4, 0($1)
TAG322:
nor $1, $4, $4
lw $4, 2($1)
slti $1, $4, 4
bgez $1, TAG323
TAG323:
lui $4, 2
bgtz $4, TAG324
sb $1, 0($1)
bgtz $1, TAG324
TAG324:
srav $1, $4, $4
bltz $1, TAG325
lui $3, 9
blez $4, TAG325
TAG325:
srlv $3, $3, $3
mthi $3
andi $1, $3, 4
multu $3, $3
TAG326:
mfhi $4
xor $3, $1, $1
mthi $4
mtlo $1
TAG327:
sw $3, 0($3)
mult $3, $3
lbu $2, 0($3)
lui $3, 5
TAG328:
mfhi $3
ori $3, $3, 12
lui $4, 14
sll $3, $3, 15
TAG329:
sll $0, $0, 0
sll $0, $0, 0
lui $1, 1
mflo $1
TAG330:
bne $1, $1, TAG331
addiu $3, $1, 6
sb $3, 0($1)
mtlo $1
TAG331:
lbu $1, 0($3)
sllv $3, $1, $3
lui $4, 5
bne $1, $3, TAG332
TAG332:
mtlo $4
mflo $4
sll $0, $0, 0
mfhi $2
TAG333:
sll $1, $2, 12
sw $1, 0($1)
bgtz $2, TAG334
mtlo $2
TAG334:
lui $4, 13
mult $4, $1
lui $3, 5
multu $3, $1
TAG335:
lui $4, 6
mtlo $3
mult $4, $3
mfhi $1
TAG336:
beq $1, $1, TAG337
slti $3, $1, 3
sh $1, 0($3)
bne $1, $1, TAG337
TAG337:
multu $3, $3
bltz $3, TAG338
lb $1, 0($3)
mfhi $4
TAG338:
sll $3, $4, 12
mflo $2
xor $3, $4, $3
lb $1, 0($2)
TAG339:
mtlo $1
bgez $1, TAG340
addiu $3, $1, 8
mtlo $3
TAG340:
mtlo $3
blez $3, TAG341
addu $1, $3, $3
addiu $4, $1, 6
TAG341:
mfhi $4
mult $4, $4
bgez $4, TAG342
mult $4, $4
TAG342:
lb $4, 0($4)
lh $3, 0($4)
sb $4, 0($4)
multu $4, $3
TAG343:
sb $3, 0($3)
mthi $3
mfhi $4
lhu $2, 0($3)
TAG344:
bne $2, $2, TAG345
ori $3, $2, 7
sb $2, 0($3)
mfhi $2
TAG345:
andi $4, $2, 2
bgtz $4, TAG346
sw $2, 0($2)
lui $3, 6
TAG346:
lui $2, 11
andi $3, $3, 4
lhu $4, 0($3)
sw $2, 0($4)
TAG347:
mthi $4
sh $4, 0($4)
mult $4, $4
mfhi $3
TAG348:
mtlo $3
srlv $3, $3, $3
multu $3, $3
mfhi $3
TAG349:
lh $1, 0($3)
bne $3, $3, TAG350
slti $3, $1, 1
lui $2, 0
TAG350:
lui $4, 8
lui $4, 4
xori $3, $2, 15
blez $4, TAG351
TAG351:
lui $1, 11
div $1, $1
blez $1, TAG352
sllv $2, $3, $3
TAG352:
mtlo $2
sll $0, $0, 0
srl $3, $3, 11
bne $3, $3, TAG353
TAG353:
lui $2, 0
mfhi $2
lbu $4, 0($2)
lui $2, 2
TAG354:
sll $0, $0, 0
mthi $2
mfhi $4
mthi $2
TAG355:
mfhi $3
addiu $1, $4, 8
blez $3, TAG356
mtlo $4
TAG356:
mtlo $1
sll $0, $0, 0
lui $3, 13
sll $0, $0, 0
TAG357:
lui $4, 11
sll $0, $0, 0
bne $4, $3, TAG358
mthi $3
TAG358:
mfhi $1
sll $0, $0, 0
lui $3, 4
mtlo $2
TAG359:
sll $0, $0, 0
sll $0, $0, 0
sll $0, $0, 0
sllv $2, $3, $2
TAG360:
sll $0, $0, 0
sll $0, $0, 0
sll $0, $0, 0
or $3, $1, $1
TAG361:
sll $0, $0, 0
lui $2, 8
mthi $3
sllv $3, $3, $2
TAG362:
sll $0, $0, 0
sll $0, $0, 0
mflo $3
sll $0, $0, 0
TAG363:
sll $0, $0, 0
lui $4, 7
beq $3, $3, TAG364
mflo $2
TAG364:
div $2, $2
multu $2, $2
sltiu $4, $2, 12
sll $0, $0, 0
TAG365:
multu $4, $4
mfhi $2
beq $4, $2, TAG366
multu $2, $2
TAG366:
multu $2, $2
mthi $2
lw $1, 0($2)
sll $0, $0, 0
TAG367:
bgez $3, TAG368
lui $1, 6
sw $3, 0($1)
ori $3, $1, 9
TAG368:
bne $3, $3, TAG369
andi $1, $3, 12
mult $1, $1
sb $3, 0($1)
TAG369:
addiu $3, $1, 7
and $2, $1, $3
sb $1, 0($1)
lbu $4, 0($1)
TAG370:
andi $4, $4, 2
lw $3, 0($4)
mult $4, $4
bne $4, $3, TAG371
TAG371:
nor $4, $3, $3
sll $0, $0, 0
sll $0, $0, 0
bgez $3, TAG372
TAG372:
sll $0, $0, 0
beq $3, $4, TAG373
mfhi $1
sll $0, $0, 0
TAG373:
sb $1, 0($1)
sub $3, $1, $1
mflo $3
mflo $4
TAG374:
lui $4, 11
bgez $4, TAG375
lui $3, 13
addiu $1, $3, 0
TAG375:
sw $1, 0($1)
ori $2, $1, 15
sb $1, 0($2)
lui $3, 12
TAG376:
bne $3, $3, TAG377
lui $4, 11
lui $3, 14
mult $3, $3
TAG377:
bne $3, $3, TAG378
mthi $3
mfhi $4
or $4, $3, $4
TAG378:
lui $3, 13
multu $3, $4
mthi $3
lui $4, 10
TAG379:
lui $3, 0
lui $2, 10
mflo $3
mflo $2
TAG380:
sra $2, $2, 10
srav $3, $2, $2
or $1, $2, $2
multu $2, $1
TAG381:
lui $4, 13
mtlo $1
mtlo $1
mflo $4
TAG382:
sb $4, 0($4)
mfhi $1
slti $1, $4, 7
lui $2, 6
TAG383:
bne $2, $2, TAG384
addiu $1, $2, 2
mflo $2
mtlo $2
TAG384:
ori $1, $2, 8
addiu $3, $1, 6
beq $3, $3, TAG385
mult $3, $2
TAG385:
divu $3, $3
mflo $1
mthi $1
sh $1, 0($3)
TAG386:
sll $1, $1, 15
lui $4, 10
and $1, $1, $1
mthi $4
TAG387:
lui $4, 8
mult $4, $4
mthi $1
mfhi $1
TAG388:
beq $1, $1, TAG389
srl $3, $1, 4
lui $4, 10
blez $4, TAG389
TAG389:
sll $0, $0, 0
sll $0, $0, 0
addu $3, $2, $2
mult $2, $2
TAG390:
add $2, $3, $3
sllv $3, $2, $2
and $1, $3, $3
mfhi $1
TAG391:
mfhi $4
and $1, $1, $1
mtlo $4
lui $4, 8
TAG392:
mflo $2
bgtz $4, TAG393
mfhi $3
sltiu $4, $2, 15
TAG393:
mult $4, $4
bne $4, $4, TAG394
sll $0, $0, 0
mfhi $4
TAG394:
mfhi $1
bne $1, $4, TAG395
mtlo $4
lui $4, 7
TAG395:
mult $4, $4
blez $4, TAG396
lui $2, 12
mthi $4
TAG396:
mthi $2
mthi $2
mthi $2
mflo $2
TAG397:
ori $1, $2, 4
lui $1, 12
bgtz $1, TAG398
sll $0, $0, 0
TAG398:
lui $1, 2
ori $2, $1, 0
divu $1, $1
sll $0, $0, 0
TAG399:
sltiu $2, $1, 13
sll $0, $0, 0
lui $2, 8
lui $2, 3
TAG400:
xori $3, $2, 3
bne $2, $3, TAG401
lui $3, 15
mfhi $2
TAG401:
bltz $2, TAG402
mthi $2
lui $2, 11
mflo $3
TAG402:
lb $2, 0($3)
lui $4, 7
multu $4, $2
divu $3, $3
TAG403:
xori $3, $4, 6
sll $0, $0, 0
subu $2, $4, $3
lui $4, 9
TAG404:
bne $4, $4, TAG405
multu $4, $4
sll $0, $0, 0
mtlo $4
TAG405:
bltz $2, TAG406
mtlo $2
or $1, $2, $2
srl $4, $2, 10
TAG406:
bne $4, $4, TAG407
divu $4, $4
mthi $4
mtlo $4
TAG407:
bne $4, $4, TAG408
mflo $1
ori $4, $4, 3
bltz $4, TAG408
TAG408:
lui $3, 8
srav $4, $3, $4
divu $4, $4
lui $3, 4
TAG409:
bgez $3, TAG410
sll $0, $0, 0
bgez $3, TAG410
mthi $3
TAG410:
lui $4, 11
sll $0, $0, 0
slti $2, $3, 3
sra $1, $4, 7
TAG411:
bgez $1, TAG412
srav $3, $1, $1
and $2, $1, $3
lw $1, 0($1)
TAG412:
div $1, $1
mthi $1
addiu $1, $1, 1
mtlo $1
TAG413:
sltu $1, $1, $1
xori $1, $1, 11
mthi $1
mtlo $1
TAG414:
subu $2, $1, $1
slti $2, $1, 2
mult $2, $2
beq $2, $2, TAG415
TAG415:
lb $1, 0($2)
blez $2, TAG416
lb $3, 0($1)
sh $2, 0($3)
TAG416:
mfhi $4
bne $4, $3, TAG417
mthi $4
lui $3, 2
TAG417:
sll $0, $0, 0
mthi $4
bne $3, $4, TAG418
sh $3, 0($4)
TAG418:
mult $4, $4
mtlo $4
lui $1, 1
bne $1, $1, TAG419
TAG419:
mfhi $3
addiu $1, $3, 8
lh $1, 0($1)
multu $1, $1
TAG420:
sll $0, $0, 0
lbu $1, 0($2)
sh $2, 0($1)
lw $2, 0($1)
TAG421:
addiu $1, $2, 15
lh $1, 0($2)
bne $1, $2, TAG422
multu $1, $1
TAG422:
lui $1, 1
mthi $1
bgez $1, TAG423
mfhi $3
TAG423:
sll $0, $0, 0
multu $4, $4
mthi $4
add $3, $4, $3
TAG424:
subu $2, $3, $3
or $4, $2, $2
bgtz $3, TAG425
nor $3, $3, $3
TAG425:
beq $3, $3, TAG426
multu $3, $3
ori $4, $3, 11
mflo $3
TAG426:
bgtz $3, TAG427
sltiu $1, $3, 4
beq $3, $1, TAG427
sh $1, 0($1)
TAG427:
mult $1, $1
multu $1, $1
mtlo $1
lui $1, 0
TAG428:
bltz $1, TAG429
sub $3, $1, $1
mthi $3
bne $1, $1, TAG429
TAG429:
sb $3, 0($3)
lui $4, 6
bgtz $3, TAG430
sb $3, 0($3)
TAG430:
sll $0, $0, 0
and $2, $4, $4
sll $0, $0, 0
sll $0, $0, 0
TAG431:
lh $4, 0($1)
blez $4, TAG432
lh $3, 0($4)
mflo $4
TAG432:
bgez $4, TAG433
mthi $4
sw $4, 0($4)
lh $2, 0($4)
TAG433:
lui $4, 8
mtlo $4
bne $2, $4, TAG434
divu $4, $2
TAG434:
sll $0, $0, 0
mthi $2
addu $1, $4, $4
mult $1, $4
TAG435:
nor $2, $1, $1
addu $2, $1, $2
beq $1, $2, TAG436
xori $1, $1, 15
TAG436:
srav $1, $1, $1
lui $2, 7
divu $1, $1
mfhi $2
TAG437:
beq $2, $2, TAG438
sltu $1, $2, $2
lb $4, 0($2)
mtlo $2
TAG438:
sltu $3, $4, $4
bgtz $4, TAG439
lui $3, 9
lui $1, 0
TAG439:
multu $1, $1
mtlo $1
mthi $1
bne $1, $1, TAG440
TAG440:
mthi $1
bgez $1, TAG441
lui $3, 5
lui $3, 11
TAG441:
ori $4, $3, 9
or $4, $4, $4
sll $0, $0, 0
mfhi $3
TAG442:
sb $3, 0($3)
multu $3, $3
beq $3, $3, TAG443
and $2, $3, $3
TAG443:
mult $2, $2
mflo $1
sh $2, 0($1)
mthi $2
TAG444:
sh $1, 0($1)
lb $3, 0($1)
sb $1, 0($3)
sw $3, 0($1)
TAG445:
srl $2, $3, 8
srlv $4, $2, $2
sw $3, 0($3)
bne $3, $4, TAG446
TAG446:
mflo $4
mtlo $4
lui $4, 13
srl $3, $4, 9
TAG447:
sltiu $3, $3, 11
lw $3, 0($3)
sw $3, 0($3)
lbu $4, 0($3)
TAG448:
mflo $3
or $3, $4, $4
mflo $4
sra $1, $4, 11
TAG449:
mflo $1
bltz $1, TAG450
slt $1, $1, $1
slti $1, $1, 7
TAG450:
lb $4, 0($1)
mthi $1
div $1, $1
multu $4, $1
TAG451:
mtlo $4
xori $1, $4, 5
bgez $4, TAG452
mthi $4
TAG452:
sb $1, 0($1)
div $1, $1
blez $1, TAG453
srav $3, $1, $1
TAG453:
sllv $1, $3, $3
lui $1, 14
mtlo $1
lui $2, 9
TAG454:
lui $1, 6
lui $1, 11
addiu $1, $2, 14
sll $0, $0, 0
TAG455:
sll $0, $0, 0
lui $3, 2
sll $0, $0, 0
divu $3, $3
TAG456:
sll $0, $0, 0
sll $0, $0, 0
sll $0, $0, 0
mthi $3
TAG457:
sll $0, $0, 0
mflo $3
sb $3, 0($3)
mthi $3
TAG458:
addiu $2, $3, 0
bgtz $3, TAG459
sb $2, 0($3)
beq $3, $3, TAG459
TAG459:
divu $2, $2
lui $3, 10
bne $2, $2, TAG460
mtlo $3
TAG460:
bgez $3, TAG461
multu $3, $3
mflo $2
mtlo $3
TAG461:
xori $3, $2, 10
addiu $4, $3, 3
beq $2, $3, TAG462
sltiu $2, $3, 2
TAG462:
multu $2, $2
sb $2, 0($2)
multu $2, $2
mflo $3
TAG463:
bgez $3, TAG464
lh $1, 0($3)
sw $1, 0($1)
sub $2, $1, $1
TAG464:
mflo $1
mult $1, $2
mtlo $1
lb $1, 0($2)
TAG465:
mfhi $3
nor $4, $3, $3
sb $1, 0($3)
lui $4, 10
TAG466:
mflo $4
sub $3, $4, $4
bne $3, $3, TAG467
mflo $4
TAG467:
lui $1, 10
bgez $1, TAG468
slti $3, $1, 1
sb $3, 0($4)
TAG468:
lhu $1, 0($3)
mthi $1
sw $1, -256($1)
bgtz $1, TAG469
TAG469:
subu $1, $1, $1
beq $1, $1, TAG470
sltiu $2, $1, 15
srav $4, $1, $1
TAG470:
mult $4, $4
nor $2, $4, $4
sh $2, 1($2)
slti $4, $2, 4
TAG471:
lbu $2, 0($4)
ori $1, $2, 12
mtlo $4
sb $4, 0($4)
TAG472:
sllv $2, $1, $1
beq $2, $1, TAG473
divu $2, $2
beq $2, $1, TAG473
TAG473:
or $3, $2, $2
sll $0, $0, 0
divu $3, $2
lui $2, 12
TAG474:
sll $0, $0, 0
lui $2, 5
bltz $1, TAG475
mthi $2
TAG475:
subu $4, $2, $2
sll $0, $0, 0
sw $2, 0($4)
mflo $2
TAG476:
blez $2, TAG477
divu $2, $2
xori $4, $2, 0
lbu $4, 0($4)
TAG477:
beq $4, $4, TAG478
mflo $1
lui $2, 2
lui $2, 10
TAG478:
mfhi $2
mthi $2
sb $2, 0($2)
mtlo $2
TAG479:
lbu $2, 0($2)
lh $4, 0($2)
multu $4, $2
bgtz $2, TAG480
TAG480:
mfhi $1
mflo $3
beq $1, $4, TAG481
lui $3, 5
TAG481:
lui $2, 12
bltz $2, TAG482
andi $4, $3, 15
xor $1, $2, $2
TAG482:
multu $1, $1
slti $1, $1, 13
sb $1, 0($1)
lui $1, 0
TAG483:
mult $1, $1
lh $3, 0($1)
lh $2, 0($1)
addiu $3, $3, 8
TAG484:
bne $3, $3, TAG485
divu $3, $3
sltiu $2, $3, 0
divu $2, $3
TAG485:
lbu $4, 0($2)
bne $4, $2, TAG486
multu $2, $2
multu $4, $4
TAG486:
addiu $1, $4, 14
sh $1, 0($4)
srav $3, $1, $4
lbu $1, 0($4)
TAG487:
bgtz $1, TAG488
sltu $2, $1, $1
sltu $2, $2, $2
nor $4, $1, $2
TAG488:
andi $2, $4, 3
lw $4, 0($4)
sll $0, $0, 0
beq $2, $4, TAG489
TAG489:
sll $0, $0, 0
srlv $1, $4, $4
mtlo $4
lui $4, 10
TAG490:
sltu $3, $4, $4
sh $4, 0($3)
mthi $3
sll $0, $0, 0
TAG491:
beq $3, $3, TAG492
srav $1, $3, $3
sh $3, 0($1)
blez $1, TAG492
TAG492:
multu $1, $1
bltz $1, TAG493
sw $1, 0($1)
slt $1, $1, $1
TAG493:
mflo $1
sb $1, 0($1)
mult $1, $1
bne $1, $1, TAG494
TAG494:
lui $3, 11
bne $1, $1, TAG495
lh $3, 0($1)
addiu $3, $3, 7
TAG495:
beq $3, $3, TAG496
srl $1, $3, 0
mtlo $3
and $2, $3, $1
TAG496:
mflo $1
multu $1, $2
lui $1, 11
mflo $3
TAG497:
beq $3, $3, TAG498
lui $4, 15
mfhi $3
lhu $2, 0($4)
TAG498:
mthi $2
mthi $2
ori $2, $2, 5
div $2, $2
TAG499:
lbu $2, 0($2)
multu $2, $2
sb $2, 0($2)
bgez $2, TAG500
TAG500:
div $2, $2
mfhi $2
sw $2, 0($2)
lb $2, 0($2)
TAG501:
lhu $2, 0($2)
mflo $2
mfhi $2
mflo $1
TAG502:
bgtz $1, TAG503
lui $1, 8
beq $1, $1, TAG503
mfhi $4
TAG503:
sll $0, $0, 0
divu $4, $4
sb $4, 0($3)
lui $2, 2
TAG504:
lui $1, 1
divu $2, $1
lui $1, 10
srl $4, $2, 1
TAG505:
lui $3, 5
beq $4, $4, TAG506
mthi $4
bne $4, $4, TAG506
TAG506:
mtlo $3
multu $3, $3
mthi $3
bne $3, $3, TAG507
TAG507:
lui $4, 5
sll $0, $0, 0
nor $1, $4, $3
sll $0, $0, 0
TAG508:
lui $4, 8
sll $0, $0, 0
srlv $3, $3, $4
sll $0, $0, 0
TAG509:
lui $2, 0
divu $3, $3
lui $2, 8
mult $2, $2
TAG510:
sll $0, $0, 0
bne $2, $2, TAG511
andi $3, $2, 5
subu $4, $2, $2
TAG511:
mthi $4
mult $4, $4
addi $4, $4, 8
sltiu $1, $4, 5
TAG512:
mfhi $2
lhu $4, 0($2)
mthi $1
sltiu $4, $2, 8
TAG513:
lui $1, 9
bgtz $1, TAG514
xori $2, $4, 1
mtlo $2
TAG514:
mtlo $2
sra $3, $2, 14
lui $1, 2
mtlo $1
TAG515:
beq $1, $1, TAG516
mthi $1
sw $1, 0($1)
lw $1, 0($1)
TAG516:
bltz $1, TAG517
slti $2, $1, 1
mflo $1
div $1, $1
TAG517:
mfhi $2
mfhi $2
bne $1, $2, TAG518
mtlo $1
TAG518:
sb $2, 0($2)
srav $2, $2, $2
lhu $4, 0($2)
mflo $4
TAG519:
bne $4, $4, TAG520
mflo $2
mfhi $4
mtlo $4
TAG520:
mflo $3
xori $2, $3, 3
beq $2, $3, TAG521
mtlo $2
TAG521:
sb $2, 0($2)
sb $2, 0($2)
mult $2, $2
bgtz $2, TAG522
TAG522:
sb $2, 0($2)
subu $2, $2, $2
subu $2, $2, $2
mult $2, $2
TAG523:
multu $2, $2
sltiu $4, $2, 13
mthi $2
sh $4, 0($2)
TAG524:
sb $4, 0($4)
sb $4, 0($4)
addiu $2, $4, 12
bgez $2, TAG525
TAG525:
and $4, $2, $2
bgez $2, TAG526
lui $3, 6
bgez $2, TAG526
TAG526:
sll $0, $0, 0
mtlo $3
bgez $3, TAG527
sll $0, $0, 0
TAG527:
sltiu $2, $2, 6
or $1, $2, $2
lui $4, 2
bltz $1, TAG528
TAG528:
subu $3, $4, $4
lb $1, 0($3)
div $4, $1
bgez $1, TAG529
TAG529:
ori $4, $1, 1
addiu $4, $4, 9
mtlo $4
beq $4, $4, TAG530
TAG530:
subu $3, $4, $4
mthi $3
mflo $1
mtlo $4
TAG531:
mthi $1
mfhi $3
bgez $1, TAG532
and $1, $3, $3
TAG532:
lb $2, 0($1)
mtlo $2
lhu $3, 0($2)
bgtz $2, TAG533
TAG533:
divu $3, $3
sh $3, -257($3)
mflo $2
srl $1, $2, 5
TAG534:
mfhi $4
bltz $4, TAG535
lw $1, 0($4)
blez $4, TAG535
TAG535:
mthi $1
lui $4, 8
sll $0, $0, 0
blez $4, TAG536
TAG536:
multu $4, $4
srl $1, $4, 1
lui $4, 6
lui $2, 11
TAG537:
xori $4, $2, 4
sll $0, $0, 0
sll $0, $0, 0
sll $0, $0, 0
TAG538:
mflo $4
bltz $4, TAG539
lw $2, 0($4)
lb $3, 0($4)
TAG539:
mthi $3
mfhi $4
lui $1, 6
mthi $3
TAG540:
lui $4, 3
sll $0, $0, 0
srlv $4, $4, $4
lui $1, 7
TAG541:
mfhi $2
or $4, $2, $2
mflo $2
sb $2, 0($4)
TAG542:
mfhi $1
lui $1, 9
lui $1, 15
sll $0, $0, 0
TAG543:
mtlo $2
mflo $4
srlv $3, $4, $2
mfhi $3
TAG544:
lui $3, 4
sllv $3, $3, $3
mflo $4
beq $3, $4, TAG545
TAG545:
lb $3, 0($4)
sra $4, $3, 1
xori $1, $3, 4
bne $4, $1, TAG546
TAG546:
mthi $1
bltz $1, TAG547
sra $3, $1, 15
multu $1, $3
TAG547:
xor $1, $3, $3
srav $3, $1, $3
mflo $4
blez $3, TAG548
TAG548:
multu $4, $4
sw $4, 0($4)
mtlo $4
bgez $4, TAG549
TAG549:
mtlo $4
sra $4, $4, 8
mflo $4
sw $4, 0($4)
TAG550:
mflo $2
bne $4, $2, TAG551
lbu $4, 0($2)
bgez $4, TAG551
TAG551:
ori $3, $4, 3
mflo $3
srav $1, $4, $4
lui $4, 13
TAG552:
sll $0, $0, 0
lui $4, 8
slt $2, $4, $2
lui $1, 11
TAG553:
sra $3, $1, 15
sll $1, $1, 15
divu $3, $1
addiu $4, $1, 10
TAG554:
bne $4, $4, TAG555
div $4, $4
mtlo $4
mthi $4
TAG555:
mthi $4
sll $0, $0, 0
sll $0, $0, 0
mfhi $2
TAG556:
bgtz $2, TAG557
divu $2, $2
sll $1, $2, 1
bne $1, $2, TAG557
TAG557:
lw $4, 0($1)
sllv $3, $1, $4
bne $1, $1, TAG558
sltiu $3, $1, 5
TAG558:
multu $3, $3
sw $3, 0($3)
mflo $4
bltz $3, TAG559
TAG559:
sb $4, 0($4)
mtlo $4
sltiu $2, $4, 15
sb $2, 0($2)
TAG560:
slti $4, $2, 1
lui $2, 6
mtlo $2
lhu $2, 0($4)
TAG561:
sll $3, $2, 3
lw $3, -2048($3)
mflo $3
lui $4, 7
TAG562:
sll $0, $0, 0
div $4, $4
lui $4, 10
slti $2, $4, 2
TAG563:
beq $2, $2, TAG564
sltiu $2, $2, 0
sh $2, 0($2)
beq $2, $2, TAG564
TAG564:
nor $3, $2, $2
lui $1, 7
sll $0, $0, 0
sb $1, 1($3)
TAG565:
mflo $4
bltz $4, TAG566
lbu $4, 0($4)
bltz $4, TAG566
TAG566:
sltu $2, $4, $4
lui $3, 4
bgez $2, TAG567
ori $3, $2, 10
TAG567:
lb $3, 0($3)
multu $3, $3
addi $1, $3, 12
sh $3, 0($3)
TAG568:
lb $4, 0($1)
lhu $2, 0($1)
srl $4, $2, 4
sllv $1, $4, $1
TAG569:
multu $1, $1
mtlo $1
sub $2, $1, $1
lui $3, 9
TAG570:
blez $3, TAG571
xori $4, $3, 10
subu $2, $3, $4
sll $0, $0, 0
TAG571:
sll $0, $0, 0
bltz $2, TAG572
subu $3, $4, $4
divu $3, $4
TAG572:
lh $3, 0($3)
mult $3, $3
blez $3, TAG573
ori $1, $3, 5
TAG573:
mtlo $1
lui $2, 2
multu $2, $2
mfhi $4
TAG574:
sltu $4, $4, $4
or $2, $4, $4
bltz $2, TAG575
lui $4, 6
TAG575:
multu $4, $4
addiu $3, $4, 6
mfhi $2
bne $2, $3, TAG576
TAG576:
srl $2, $2, 15
xori $3, $2, 12
beq $3, $2, TAG577
lbu $2, 0($3)
TAG577:
sb $2, 0($2)
mthi $2
div $2, $2
xori $1, $2, 0
TAG578:
lui $3, 9
slti $3, $3, 3
mflo $2
mult $3, $3
TAG579:
mfhi $2
bne $2, $2, TAG580
lui $4, 10
xor $4, $2, $2
TAG580:
multu $4, $4
lui $2, 10
lw $2, 0($4)
andi $4, $2, 12
TAG581:
lui $4, 11
sll $0, $0, 0
mthi $4
mflo $3
TAG582:
lw $3, 0($3)
mtlo $3
add $4, $3, $3
multu $3, $4
TAG583:
sb $4, 0($4)
slt $2, $4, $4
lui $4, 6
beq $4, $4, TAG584
TAG584:
sll $0, $0, 0
mflo $1
sll $0, $0, 0
lui $1, 6
TAG585:
bgtz $1, TAG586
addu $1, $1, $1
mthi $1
sltu $1, $1, $1
TAG586:
and $4, $1, $1
ori $1, $4, 15
div $1, $4
bgez $1, TAG587
TAG587:
mult $1, $1
lui $3, 13
sll $0, $0, 0
slt $2, $1, $1
TAG588:
addu $1, $2, $2
blez $1, TAG589
sub $4, $2, $1
srav $2, $1, $1
TAG589:
sw $2, 0($2)
mult $2, $2
add $3, $2, $2
bgtz $2, TAG590
TAG590:
multu $3, $3
sra $2, $3, 8
lhu $3, 0($2)
mfhi $1
TAG591:
srav $1, $1, $1
bne $1, $1, TAG592
sllv $1, $1, $1
lui $3, 4
TAG592:
xori $3, $3, 13
srav $1, $3, $3
sllv $2, $3, $3
srl $3, $1, 14
TAG593:
mtlo $3
lui $2, 13
sll $0, $0, 0
lui $4, 4
TAG594:
lui $4, 2
bgez $4, TAG595
lui $2, 1
bne $4, $4, TAG595
TAG595:
sltiu $4, $2, 15
divu $4, $2
lui $2, 2
mtlo $4
TAG596:
div $2, $2
srav $3, $2, $2
sll $0, $0, 0
bne $3, $3, TAG597
TAG597:
mthi $3
lui $4, 7
mthi $4
sll $0, $0, 0
TAG598:
divu $4, $4
sll $0, $0, 0
divu $4, $4
sll $0, $0, 0
TAG599:
sll $0, $0, 0
beq $4, $4, TAG600
mtlo $2
beq $2, $2, TAG600
TAG600:
mfhi $3
mult $3, $3
xor $1, $3, $2
sll $0, $0, 0
TAG601:
div $1, $1
lui $4, 10
mthi $1
mtlo $1
TAG602:
sll $0, $0, 0
bgtz $1, TAG603
mthi $4
andi $2, $1, 15
TAG603:
mfhi $2
sll $0, $0, 0
mfhi $2
lui $2, 0
TAG604:
lui $4, 15
bne $4, $4, TAG605
mthi $4
sll $0, $0, 0
TAG605:
mflo $3
beq $1, $3, TAG606
lui $4, 3
mfhi $3
TAG606:
mtlo $3
xori $2, $3, 4
lui $3, 15
sll $0, $0, 0
TAG607:
bne $3, $3, TAG608
sltu $4, $3, $3
lui $4, 2
sll $0, $0, 0
TAG608:
lui $3, 12
sll $0, $0, 0
sll $0, $0, 0
mtlo $3
TAG609:
bne $3, $3, TAG610
mflo $2
sll $0, $0, 0
or $1, $3, $2
TAG610:
subu $4, $1, $1
mtlo $1
andi $3, $1, 6
lb $3, 0($3)
TAG611:
addi $4, $3, 9
lbu $4, 0($3)
or $2, $4, $3
bne $2, $3, TAG612
TAG612:
mtlo $2
mult $2, $2
srlv $3, $2, $2
sltiu $4, $2, 6
TAG613:
mtlo $4
mtlo $4
srav $4, $4, $4
blez $4, TAG614
TAG614:
mult $4, $4
bgtz $4, TAG615
sltiu $1, $4, 15
xori $1, $1, 12
TAG615:
divu $1, $1
mflo $3
bne $3, $1, TAG616
mtlo $1
TAG616:
mthi $3
sb $3, 0($3)
mthi $3
lui $2, 12
TAG617:
divu $2, $2
lui $2, 9
bne $2, $2, TAG618
nor $1, $2, $2
TAG618:
sll $0, $0, 0
srlv $2, $3, $1
sb $1, 0($3)
lui $3, 7
TAG619:
sll $0, $0, 0
bne $3, $3, TAG620
multu $3, $3
lui $1, 11
TAG620:
mtlo $1
sll $0, $0, 0
mflo $2
sll $0, $0, 0
TAG621:
sll $0, $0, 0
multu $2, $2
addu $4, $2, $2
bne $2, $2, TAG622
TAG622:
ori $2, $4, 12
multu $2, $4
lui $2, 6
sll $0, $0, 0
TAG623:
sll $0, $0, 0
bne $2, $2, TAG624
mfhi $2
mflo $1
TAG624:
sll $0, $0, 0
sll $0, $0, 0
bltz $1, TAG625
xor $3, $1, $1
TAG625:
mtlo $3
beq $3, $3, TAG626
sw $3, 0($3)
lui $2, 15
TAG626:
mfhi $1
lb $3, -484($2)
lui $4, 9
blez $3, TAG627
TAG627:
slti $4, $4, 0
mflo $2
addiu $1, $4, 12
mtlo $2
TAG628:
lui $2, 12
lhu $1, 0($1)
lui $4, 1
sll $0, $0, 0
TAG629:
mtlo $4
sll $0, $0, 0
slt $3, $4, $4
lui $1, 11
TAG630:
mult $1, $1
sll $0, $0, 0
divu $1, $1
multu $1, $1
TAG631:
lui $1, 9
lui $1, 11
beq $1, $1, TAG632
sll $0, $0, 0
TAG632:
mfhi $4
bne $1, $1, TAG633
divu $1, $4
sltiu $3, $1, 10
TAG633:
lui $4, 0
blez $4, TAG634
lb $3, 0($3)
divu $3, $3
TAG634:
sw $3, 0($3)
mthi $3
lhu $1, 0($3)
addiu $3, $3, 4
TAG635:
mthi $3
mtlo $3
beq $3, $3, TAG636
lui $1, 15
TAG636:
subu $4, $1, $1
addu $2, $1, $1
subu $1, $2, $2
lhu $1, 0($4)
TAG637:
sb $1, 0($1)
bltz $1, TAG638
sh $1, 0($1)
bgtz $1, TAG638
TAG638:
add $1, $1, $1
sh $1, 0($1)
mtlo $1
lbu $3, 0($1)
TAG639:
mflo $1
bltz $3, TAG640
addiu $4, $1, 6
mult $4, $1
TAG640:
xori $3, $4, 14
lui $1, 1
sh $3, 0($3)
mflo $2
TAG641:
multu $2, $2
mtlo $2
bne $2, $2, TAG642
add $3, $2, $2
TAG642:
beq $3, $3, TAG643
lui $1, 5
multu $3, $1
beq $1, $1, TAG643
TAG643:
sll $0, $0, 0
beq $1, $1, TAG644
sra $1, $1, 4
srlv $3, $1, $1
TAG644:
mult $3, $3
mult $3, $3
mtlo $3
andi $2, $3, 6
TAG645:
multu $2, $2
sllv $1, $2, $2
bne $1, $1, TAG646
sltu $2, $1, $1
TAG646:
addi $2, $2, 7
andi $2, $2, 2
addiu $4, $2, 0
sb $2, 0($2)
TAG647:
beq $4, $4, TAG648
divu $4, $4
div $4, $4
mtlo $4
TAG648:
mtlo $4
sh $4, 0($4)
lh $2, 0($4)
mthi $2
TAG649:
andi $4, $2, 8
mult $4, $4
mtlo $4
lui $1, 13
TAG650:
lui $2, 2
sll $0, $0, 0
blez $2, TAG651
addiu $2, $1, 15
TAG651:
lui $2, 6
beq $2, $2, TAG652
mfhi $3
addi $2, $2, 10
TAG652:
div $2, $2
sra $4, $2, 7
lui $2, 8
addu $4, $4, $4
TAG653:
addiu $3, $4, 13
bne $3, $3, TAG654
srl $4, $4, 1
mfhi $3
TAG654:
mult $3, $3
beq $3, $3, TAG655
mflo $1
mflo $4
TAG655:
mult $4, $4
sltu $3, $4, $4
mtlo $4
mult $3, $3
TAG656:
mflo $1
xori $4, $1, 11
lui $1, 7
ori $2, $4, 11
TAG657:
lui $4, 8
subu $2, $2, $2
sb $2, 0($2)
multu $4, $4
TAG658:
addi $4, $2, 10
divu $2, $4
sh $2, 0($4)
mfhi $4
TAG659:
andi $4, $4, 11
mfhi $1
multu $4, $1
blez $4, TAG660
TAG660:
mult $1, $1
beq $1, $1, TAG661
mult $1, $1
xori $1, $1, 11
TAG661:
bgtz $1, TAG662
lb $2, 0($1)
bltz $1, TAG662
lh $2, 0($2)
TAG662:
multu $2, $2
sw $2, 0($2)
lui $4, 12
beq $2, $2, TAG663
TAG663:
mtlo $4
addiu $3, $4, 15
mtlo $3
div $3, $3
TAG664:
bgtz $3, TAG665
sltu $2, $3, $3
bgtz $3, TAG665
lui $1, 11
TAG665:
lw $1, 0($1)
lhu $4, 0($1)
bne $4, $1, TAG666
lui $3, 11
TAG666:
divu $3, $3
nor $2, $3, $3
sra $3, $3, 8
bgtz $3, TAG667
TAG667:
subu $3, $3, $3
addiu $3, $3, 8
mult $3, $3
sw $3, 0($3)
TAG668:
beq $3, $3, TAG669
mfhi $3
mthi $3
bne $3, $3, TAG669
TAG669:
mfhi $3
beq $3, $3, TAG670
lui $1, 8
andi $4, $3, 9
TAG670:
lbu $1, 0($4)
mfhi $4
beq $4, $1, TAG671
xori $2, $1, 2
TAG671:
lhu $3, 0($2)
mtlo $3
bgtz $2, TAG672
lui $4, 4
TAG672:
mthi $4
beq $4, $4, TAG673
mthi $4
mfhi $3
TAG673:
subu $1, $3, $3
mult $1, $3
sh $1, 0($3)
sh $3, 0($1)
TAG674:
multu $1, $1
nor $1, $1, $1
addiu $3, $1, 15
divu $1, $3
TAG675:
lb $1, 0($3)
sh $1, 0($3)
mthi $1
lui $3, 5
TAG676:
beq $3, $3, TAG677
mtlo $3
sw $3, 0($3)
sub $3, $3, $3
TAG677:
subu $1, $3, $3
lb $3, 0($1)
mtlo $3
xor $4, $1, $3
TAG678:
beq $4, $4, TAG679
mfhi $1
bltz $1, TAG679
slt $1, $4, $4
TAG679:
bgez $1, TAG680
sb $1, 0($1)
subu $3, $1, $1
mult $1, $3
TAG680:
blez $3, TAG681
multu $3, $3
addiu $4, $3, 5
sltu $4, $3, $4
TAG681:
xori $1, $4, 13
lui $4, 4
sb $4, 0($1)
lui $3, 4
TAG682:
bne $3, $3, TAG683
sll $0, $0, 0
mthi $3
lui $3, 0
TAG683:
mfhi $2
lbu $1, 0($3)
sll $0, $0, 0
mflo $2
TAG684:
mthi $2
sra $1, $2, 12
bne $2, $2, TAG685
lui $3, 12
TAG685:
beq $3, $3, TAG686
addiu $1, $3, 6
lui $3, 13
and $3, $1, $1
TAG686:
bltz $3, TAG687
addiu $3, $3, 7
mult $3, $3
lui $2, 5
TAG687:
bgtz $2, TAG688
mult $2, $2
lui $2, 11
lui $1, 0
TAG688:
lui $1, 13
mflo $4
multu $1, $4
sll $0, $0, 0
TAG689:
blez $4, TAG690
sw $4, 0($4)
lui $4, 13
mfhi $2
TAG690:
mflo $3
bgez $2, TAG691
xor $3, $2, $3
lui $2, 14
TAG691:
addu $2, $2, $2
bltz $2, TAG692
multu $2, $2
sll $0, $0, 0
TAG692:
sll $0, $0, 0
lui $2, 6
sll $0, $0, 0
sll $0, $0, 0
TAG693:
sll $0, $0, 0
mflo $1
lui $4, 7
sllv $2, $1, $1
TAG694:
mult $2, $2
bgez $2, TAG695
lui $3, 6
lbu $2, 0($2)
TAG695:
sw $2, 0($2)
bgez $2, TAG696
sllv $2, $2, $2
and $2, $2, $2
TAG696:
lw $1, 0($2)
bgez $2, TAG697
mfhi $4
bgez $4, TAG697
TAG697:
lh $2, 0($4)
bltz $2, TAG698
mtlo $4
bgez $2, TAG698
TAG698:
lui $1, 11
andi $1, $1, 9
beq $1, $1, TAG699
xori $3, $1, 14
TAG699:
sh $3, 0($3)
sb $3, 0($3)
lui $3, 0
srl $1, $3, 10
TAG700:
sltu $4, $1, $1
lb $3, 0($1)
lui $1, 6
bgez $3, TAG701
TAG701:
multu $1, $1
lui $3, 1
subu $1, $1, $1
sub $2, $3, $1
TAG702:
mfhi $1
sll $0, $0, 0
mflo $4
mthi $2
TAG703:
lhu $3, 0($4)
mfhi $3
mflo $2
sll $0, $0, 0
TAG704:
lui $4, 0
sltu $3, $2, $2
mult $3, $4
bgtz $3, TAG705
TAG705:
lui $2, 10
mfhi $1
lui $4, 10
mult $4, $1
TAG706:
nor $4, $4, $4
bne $4, $4, TAG707
sll $0, $0, 0
beq $4, $4, TAG707
TAG707:
sltiu $2, $2, 10
mult $2, $2
xori $3, $2, 4
xor $2, $3, $2
TAG708:
xor $2, $2, $2
lw $4, 0($2)
srav $3, $2, $4
bgtz $4, TAG709
TAG709:
slti $1, $3, 1
sb $3, 0($1)
blez $1, TAG710
sllv $4, $3, $1
TAG710:
sw $4, 0($4)
lw $2, 0($4)
lui $4, 0
lb $1, 0($4)
TAG711:
lui $3, 2
bne $3, $3, TAG712
mthi $1
beq $1, $3, TAG712
TAG712:
mflo $1
slti $2, $1, 14
blez $1, TAG713
lbu $3, 0($2)
TAG713:
sltu $4, $3, $3
mthi $3
sll $3, $4, 8
ori $1, $3, 10
TAG714:
slt $1, $1, $1
slt $4, $1, $1
sh $1, 0($1)
beq $4, $4, TAG715
TAG715:
mtlo $4
sra $4, $4, 14
bgez $4, TAG716
mflo $4
TAG716:
multu $4, $4
srl $1, $4, 15
sb $4, 0($4)
multu $1, $1
TAG717:
lw $3, 0($1)
mthi $3
lui $2, 11
lui $2, 4
TAG718:
bne $2, $2, TAG719
sll $0, $0, 0
sll $0, $0, 0
sll $0, $0, 0
TAG719:
sb $1, 0($1)
mfhi $2
mtlo $2
or $4, $1, $1
TAG720:
sb $4, 0($4)
beq $4, $4, TAG721
mult $4, $4
mtlo $4
TAG721:
sh $4, 0($4)
lui $1, 1
sll $0, $0, 0
bgtz $4, TAG722
TAG722:
sll $0, $0, 0
sll $0, $0, 0
bgez $1, TAG723
sll $3, $1, 2
TAG723:
sll $0, $0, 0
mult $2, $3
and $2, $2, $2
bgtz $2, TAG724
TAG724:
sw $2, 0($2)
mfhi $3
mflo $1
mthi $3
TAG725:
lui $3, 6
bne $3, $3, TAG726
lh $4, 0($1)
mflo $3
TAG726:
sw $3, 0($3)
bltz $3, TAG727
addiu $3, $3, 3
mflo $4
TAG727:
lui $4, 10
mflo $1
mthi $4
bne $4, $1, TAG728
TAG728:
addiu $3, $1, 1
sb $3, 0($3)
sra $4, $3, 13
sltu $4, $3, $1
TAG729:
bltz $4, TAG730
srlv $2, $4, $4
and $2, $4, $4
andi $2, $4, 13
TAG730:
sw $2, 0($2)
sw $2, 0($2)
xor $4, $2, $2
lui $2, 7
TAG731:
addiu $1, $2, 13
div $1, $1
blez $2, TAG732
divu $1, $1
TAG732:
mult $1, $1
sll $0, $0, 0
sll $0, $0, 0
beq $4, $1, TAG733
TAG733:
mfhi $3
lui $1, 13
mflo $3
mtlo $3
TAG734:
sll $0, $0, 0
subu $1, $3, $3
lui $3, 14
mult $1, $3
TAG735:
mthi $3
slt $2, $3, $3
blez $2, TAG736
mfhi $1
TAG736:
lui $2, 1
blez $1, TAG737
mflo $2
beq $2, $2, TAG737
TAG737:
subu $3, $2, $2
multu $3, $2
multu $2, $2
mthi $2
TAG738:
beq $3, $3, TAG739
mflo $2
beq $2, $3, TAG739
mthi $2
TAG739:
bgez $2, TAG740
sb $2, 0($2)
div $2, $2
lui $3, 1
TAG740:
lhu $3, 0($3)
sltu $3, $3, $3
blez $3, TAG741
srav $2, $3, $3
TAG741:
srl $4, $2, 12
mflo $3
lui $4, 15
lui $4, 8
TAG742:
sll $0, $0, 0
sllv $2, $4, $4
mtlo $2
beq $4, $2, TAG743
TAG743:
lui $1, 9
beq $2, $1, TAG744
sll $0, $0, 0
subu $4, $1, $2
TAG744:
bgtz $4, TAG745
andi $2, $4, 14
lui $2, 2
addiu $3, $4, 2
TAG745:
mfhi $2
mthi $2
blez $3, TAG746
mult $2, $2
TAG746:
mtlo $2
bgtz $2, TAG747
sll $2, $2, 14
add $3, $2, $2
TAG747:
multu $3, $3
bne $3, $3, TAG748
mflo $3
bne $3, $3, TAG748
TAG748:
mfhi $1
sb $1, 0($3)
mflo $1
lui $3, 11
TAG749:
andi $1, $3, 3
mflo $4
lui $4, 6
subu $3, $4, $1
TAG750:
nop
nop
test_end:
beq $0, $0, test_end
nop |
programs/oeis/185/A185014.asm | neoneye/loda | 22 | 172596 | ; A185014: Characteristic function of four.
; 0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
cmp $0,4
|
oeis/014/A014918.asm | neoneye/loda-programs | 11 | 172723 | ; A014918: a(1)=1, a(n) = n*6^(n-1) + a(n-1).
; 1,13,121,985,7465,54121,380713,2620201,17736745,118513705,783641641,5137206313,33435376681,216285092905,1391747554345,8914707307561,56873575734313,361553445739561,2291192622439465,14478387422649385,91257714663971881,573870628752284713,3601169817124428841,22554695170410896425,141014228628451318825,880201717406623554601,5485908378255235177513,34143638712424374164521,212230962931904023583785,1317600561535570813082665,8170892072878304907975721,50617084659259109624732713,313252901287490338809666601
add $0,1
lpb $0
add $1,$0
sub $0,1
mul $1,6
lpe
div $1,6
mov $0,$1
|
programs/oeis/309/A309827.asm | neoneye/loda | 22 | 22693 | <reponame>neoneye/loda<filename>programs/oeis/309/A309827.asm
; A309827: a(n) is the square of the number consisting of one 1 and n 6's: (166...6)^2.
; 1,256,27556,2775556,277755556,27777555556,2777775555556,277777755555556,27777777555555556,2777777775555555556,277777777755555555556,27777777777555555555556,2777777777775555555555556,277777777777755555555555556,27777777777777555555555555556,2777777777777775555555555555556,277777777777777755555555555555556,27777777777777777555555555555555556
seq $0,185123 ; a(n) = n 9's sandwiched between two 1's.
mov $1,2
add $1,$0
mul $1,$0
div $1,144
add $1,1
mov $0,$1
|
fiat-amd64/390.08_ratio10396_seed2412526886283759_square_p434.asm | dderjoel/fiat-crypto | 491 | 86382 | <reponame>dderjoel/fiat-crypto<filename>fiat-amd64/390.08_ratio10396_seed2412526886283759_square_p434.asm
SECTION .text
GLOBAL square_p434
square_p434:
sub rsp, 0x568 ; last 0x30 (6) for Caller - save regs
mov [ rsp + 0x538 ], rbx; saving to stack
mov [ rsp + 0x540 ], rbp; saving to stack
mov [ rsp + 0x548 ], r12; saving to stack
mov [ rsp + 0x550 ], r13; saving to stack
mov [ rsp + 0x558 ], r14; saving to stack
mov [ rsp + 0x560 ], r15; saving to stack
mov rax, [ rsi + 0x10 ]; load m64 x2 to register64
mov rdx, rax; x2 to rdx
mulx rax, r10, [ rsi + 0x0 ]; x178, x177<- x2 * arg1[0]
mulx r11, rbx, [ rsi + 0x10 ]; x174, x173<- x2 * arg1[2]
mulx rbp, r12, [ rsi + 0x30 ]; x166, x165<- x2 * arg1[6]
mulx r13, r14, [ rsi + 0x8 ]; x176, x175<- x2 * arg1[1]
mov r15, [ rsi + 0x0 ]; load m64 x7 to register64
mulx rcx, r8, [ rsi + 0x28 ]; x168, x167<- x2 * arg1[5]
xor r9, r9
adox r14, rax
adox rbx, r13
mulx rax, r13, [ rsi + 0x18 ]; x172, x171<- x2 * arg1[3]
adox r13, r11
mov r11, [ rsi + 0x20 ]; load m64 x4 to register64
mulx rdx, r9, [ rsi + 0x20 ]; x170, x169<- x2 * arg1[4]
adox r9, rax
adox r8, rdx
mov rdx, r15; x7 to rdx
mulx r15, rax, [ rsi + 0x0 ]; x21, x20<- x7 * arg1[0]
adox r12, rcx
mov rcx, 0xffffffffffffffff ; moving imm to reg
xchg rdx, rax; x20, swapping with x7, which is currently in rdx
mov [ rsp + 0x0 ], rdi; spilling out1 to mem
mov [ rsp + 0x8 ], r12; spilling x189 to mem
mulx rdi, r12, rcx; x46, x45<- x20 * 0xffffffffffffffff
mov rcx, 0x0 ; moving imm to reg
adox rbp, rcx
mov rcx, 0xfdc1767ae2ffffff ; moving imm to reg
mov [ rsp + 0x10 ], rbp; spilling x191 to mem
mov [ rsp + 0x18 ], r8; spilling x187 to mem
mulx rbp, r8, rcx; x42, x41<- x20 * 0xfdc1767ae2ffffff
mov rcx, 0xffffffffffffffff ; moving imm to reg
mov [ rsp + 0x20 ], r9; spilling x185 to mem
mov [ rsp + 0x28 ], r13; spilling x183 to mem
mulx r9, r13, rcx; x48, x47<- x20 * 0xffffffffffffffff
mov [ rsp + 0x30 ], rbx; spilling x181 to mem
mov [ rsp + 0x38 ], r14; spilling x179 to mem
mulx rbx, r14, rcx; x44, x43<- x20 * 0xffffffffffffffff
mov rcx, 0x6cfc5fd681c52056 ; moving imm to reg
mov [ rsp + 0x40 ], r10; spilling x177 to mem
mov [ rsp + 0x48 ], r15; spilling x21 to mem
mulx r10, r15, rcx; x38, x37<- x20 * 0x6cfc5fd681c52056
adcx r12, r9
adcx r14, rdi
adcx r8, rbx
mov rdi, 0x7bc65c783158aea3 ; moving imm to reg
mulx r9, rbx, rdi; x40, x39<- x20 * 0x7bc65c783158aea3
mov rdi, rdx; preserving value of x20 into a new reg
mov rdx, [ rsi + 0x8 ]; saving arg1[1] in rdx.
mov [ rsp + 0x50 ], r8; spilling x53 to mem
mulx rcx, r8, rax; x19, x18<- x7 * arg1[1]
adcx rbx, rbp
mov rdx, 0x2341f27177344 ; moving imm to reg
mov [ rsp + 0x58 ], rbx; spilling x55 to mem
mulx rbp, rbx, rdi; x36, x35<- x20 * 0x2341f27177344
xchg rdx, r11; x4, swapping with 0x2341f27177344, which is currently in rdx
mov [ rsp + 0x60 ], r14; spilling x51 to mem
mulx r11, r14, [ rsi + 0x8 ]; x350, x349<- x4 * arg1[1]
mov [ rsp + 0x68 ], r12; spilling x49 to mem
mov r12, [ rsi + 0x8 ]; load m64 x1 to register64
mov [ rsp + 0x70 ], r12; spilling x1 to mem
mov [ rsp + 0x78 ], rcx; spilling x19 to mem
mulx r12, rcx, [ rsi + 0x10 ]; x348, x347<- x4 * arg1[2]
adcx r15, r9
mov [ rsp + 0x80 ], r15; spilling x57 to mem
mulx r9, r15, [ rsi + 0x0 ]; x352, x351<- x4 * arg1[0]
mov [ rsp + 0x88 ], r15; spilling x351 to mem
mov [ rsp + 0x90 ], r12; spilling x348 to mem
mulx r15, r12, [ rsi + 0x18 ]; x346, x345<- x4 * arg1[3]
adcx rbx, r10
mov r10, -0x2 ; moving imm to reg
inc r10; OF<-0x0, preserve CF (debug: 6; load -2, increase it, save as -1)
adox r14, r9
mov r9, 0x0 ; moving imm to reg
adcx rbp, r9
mulx r9, r10, [ rsi + 0x28 ]; x342, x341<- x4 * arg1[5]
adox rcx, r11
clc;
adcx r13, rdi
setc r13b; spill CF x63 to reg (r13)
clc;
adcx r8, [ rsp + 0x48 ]
mulx rdi, r11, [ rsi + 0x20 ]; x344, x343<- x4 * arg1[4]
mov [ rsp + 0x98 ], rcx; spilling x355 to mem
mulx rdx, rcx, [ rsi + 0x30 ]; x340, x339<- x4 * arg1[6]
mov [ rsp + 0xa0 ], r14; spilling x353 to mem
mov r14, rdx; preserving value of x340 into a new reg
mov rdx, [ rsi + 0x10 ]; saving arg1[2] in rdx.
mov [ rsp + 0xa8 ], rbp; spilling x61 to mem
mov [ rsp + 0xb0 ], rbx; spilling x59 to mem
mulx rbp, rbx, rax; x17, x16<- x7 * arg1[2]
mov rdx, [ rsp + 0x90 ]; x357, copying x348 here, cause x348 is needed in a reg for other than x357, namely all: , x357--x358, size: 1
adox rdx, r12
adox r11, r15
adox r10, rdi
mov r15, [ rsp + 0x78 ]; x24, copying x19 here, cause x19 is needed in a reg for other than x24, namely all: , x24--x25, size: 1
adcx r15, rbx
seto r12b; spill OF x362 to reg (r12)
mov rdi, 0x0 ; moving imm to reg
dec rdi; OF<-0x0, preserve CF (debug: state 4 (thanks Paul))
movzx r13, r13b
adox r13, rdi; loading flag
adox r8, [ rsp + 0x68 ]
mov r13, [ rsp + 0x60 ]; x66, copying x51 here, cause x51 is needed in a reg for other than x66, namely all: , x66--x67, size: 1
adox r13, r15
mov rbx, rdx; preserving value of x357 into a new reg
mov rdx, [ rsi + 0x10 ]; saving arg1[2] in rdx.
mulx r15, rdi, [ rsp + 0x70 ]; x87, x86<- x1 * arg1[2]
mov rdx, [ rsi + 0x0 ]; arg1[0] to rdx
mov [ rsp + 0xb8 ], r10; spilling x361 to mem
mov [ rsp + 0xc0 ], r11; spilling x359 to mem
mulx r10, r11, [ rsp + 0x70 ]; x91, x90<- x1 * arg1[0]
setc dl; spill CF x25 to reg (rdx)
clc;
mov [ rsp + 0xc8 ], rbx; spilling x357 to mem
mov rbx, -0x1 ; moving imm to reg
movzx r12, r12b
adcx r12, rbx; loading flag
adcx r9, rcx
seto cl; spill OF x67 to reg (rcx)
inc rbx; OF<-0x0, preserve CF (debug: state 2 (y: -1, n: 0))
adox r11, r8
mov r12b, dl; preserving value of x25 into a new reg
mov rdx, [ rsi + 0x8 ]; saving arg1[1] in rdx.
mulx r8, rbx, [ rsp + 0x70 ]; x89, x88<- x1 * arg1[1]
setc dl; spill CF x364 to reg (rdx)
clc;
adcx rbx, r10
movzx r10, dl; x365, copying x364 here, cause x364 is needed in a reg for other than x365, namely all: , x365, size: 1
lea r10, [ r10 + r14 ]
mov r14, 0xffffffffffffffff ; moving imm to reg
mov rdx, r11; x105 to rdx
mov [ rsp + 0xd0 ], r10; spilling x365 to mem
mulx r11, r10, r14; x134, x133<- x105 * 0xffffffffffffffff
adox rbx, r13
mov [ rsp + 0xd8 ], r9; spilling x363 to mem
mulx r13, r9, r14; x132, x131<- x105 * 0xffffffffffffffff
adcx rdi, r8
setc r8b; spill CF x95 to reg (r8)
clc;
adcx r9, r11
setc r11b; spill CF x136 to reg (r11)
clc;
adcx r10, rdx
mov [ rsp + 0xe0 ], r15; spilling x87 to mem
mulx r10, r15, r14; x130, x129<- x105 * 0xffffffffffffffff
mov r14, rdx; preserving value of x105 into a new reg
mov rdx, [ rsi + 0x18 ]; saving arg1[3] in rdx.
mov [ rsp + 0xe8 ], r10; spilling x130 to mem
mov byte [ rsp + 0xf0 ], r8b; spilling byte x95 to mem
mulx r10, r8, rax; x15, x14<- x7 * arg1[3]
adcx r9, rbx
setc dl; spill CF x151 to reg (rdx)
clc;
mov rbx, -0x1 ; moving imm to reg
movzx r12, r12b
adcx r12, rbx; loading flag
adcx rbp, r8
setc r12b; spill CF x27 to reg (r12)
clc;
movzx rcx, cl
adcx rcx, rbx; loading flag
adcx rbp, [ rsp + 0x50 ]
seto cl; spill OF x108 to reg (rcx)
inc rbx; OF<-0x0, preserve CF (debug: state 2 (y: -1, n: 0))
adox r9, [ rsp + 0x40 ]
mov r8, 0xffffffffffffffff ; moving imm to reg
xchg rdx, r9; x192, swapping with x151, which is currently in rdx
mov [ rsp + 0xf8 ], r10; spilling x15 to mem
mulx rbx, r10, r8; x221, x220<- x192 * 0xffffffffffffffff
seto r8b; spill OF x193 to reg (r8)
mov byte [ rsp + 0x100 ], r12b; spilling byte x27 to mem
mov r12, -0x1 ; moving imm to reg
inc r12; OF<-0x0, preserve CF (debug: state 5 (thanks Paul))
mov r12, -0x1 ; moving imm to reg
movzx r11, r11b
adox r11, r12; loading flag
adox r13, r15
mov r11, 0xffffffffffffffff ; moving imm to reg
mulx r15, r12, r11; x219, x218<- x192 * 0xffffffffffffffff
mov r11, [ rsi + 0x18 ]; load m64 x3 to register64
mov [ rsp + 0x108 ], r15; spilling x219 to mem
seto r15b; spill OF x138 to reg (r15)
mov [ rsp + 0x110 ], r11; spilling x3 to mem
mov r11, -0x2 ; moving imm to reg
inc r11; OF<-0x0, preserve CF (debug: 6; load -2, increase it, save as -1)
adox r12, rbx
seto bl; spill OF x223 to reg (rbx)
inc r11; OF<-0x0, preserve CF (debug: state 2 (y: -1, n: 0))
adox r10, rdx
setc r10b; spill CF x69 to reg (r10)
clc;
mov r11, -0x1 ; moving imm to reg
movzx rcx, cl
adcx rcx, r11; loading flag
adcx rbp, rdi
setc cl; spill CF x110 to reg (rcx)
clc;
movzx r9, r9b
adcx r9, r11; loading flag
adcx rbp, r13
setc dil; spill CF x153 to reg (rdi)
clc;
movzx r8, r8b
adcx r8, r11; loading flag
adcx rbp, [ rsp + 0x38 ]
adox r12, rbp
mov r9, rdx; preserving value of x192 into a new reg
mov rdx, [ rsi + 0x0 ]; saving arg1[0] in rdx.
mulx r8, r13, [ rsp + 0x110 ]; x265, x264<- x3 * arg1[0]
setc dl; spill CF x195 to reg (rdx)
clc;
adcx r13, r12
mov rbp, 0x6cfc5fd681c52056 ; moving imm to reg
xchg rdx, r13; x279, swapping with x195, which is currently in rdx
mulx r12, r11, rbp; x298, x297<- x279 * 0x6cfc5fd681c52056
mov rbp, 0xffffffffffffffff ; moving imm to reg
mov [ rsp + 0x118 ], r8; spilling x265 to mem
mov byte [ rsp + 0x120 ], r13b; spilling byte x195 to mem
mulx r8, r13, rbp; x308, x307<- x279 * 0xffffffffffffffff
mov rbp, 0x7bc65c783158aea3 ; moving imm to reg
mov [ rsp + 0x128 ], r13; spilling x307 to mem
mov byte [ rsp + 0x130 ], dil; spilling byte x153 to mem
mulx r13, rdi, rbp; x300, x299<- x279 * 0x7bc65c783158aea3
mov rbp, 0xffffffffffffffff ; moving imm to reg
mov byte [ rsp + 0x138 ], cl; spilling byte x110 to mem
mov byte [ rsp + 0x140 ], r10b; spilling byte x69 to mem
mulx rcx, r10, rbp; x306, x305<- x279 * 0xffffffffffffffff
setc bpl; spill CF x280 to reg (rbp)
clc;
adcx r10, r8
mov r8, 0xffffffffffffffff ; moving imm to reg
mov [ rsp + 0x148 ], r10; spilling x309 to mem
mov byte [ rsp + 0x150 ], bpl; spilling byte x280 to mem
mulx r10, rbp, r8; x304, x303<- x279 * 0xffffffffffffffff
mov r8, 0xfdc1767ae2ffffff ; moving imm to reg
mov byte [ rsp + 0x158 ], r15b; spilling byte x138 to mem
mov byte [ rsp + 0x160 ], bl; spilling byte x223 to mem
mulx r15, rbx, r8; x302, x301<- x279 * 0xfdc1767ae2ffffff
adcx rbp, rcx
adcx rbx, r10
mov rcx, rdx; preserving value of x279 into a new reg
mov rdx, [ rsi + 0x18 ]; saving arg1[3] in rdx.
mulx r10, r8, [ rsp + 0x70 ]; x85, x84<- x1 * arg1[3]
adcx rdi, r15
mov rdx, 0x2341f27177344 ; moving imm to reg
mov [ rsp + 0x168 ], rdi; spilling x315 to mem
mulx r15, rdi, rcx; x296, x295<- x279 * 0x2341f27177344
adcx r11, r13
adcx rdi, r12
mov r12, rdx; preserving value of 0x2341f27177344 into a new reg
mov rdx, [ rsi + 0x20 ]; saving arg1[4] in rdx.
mov [ rsp + 0x170 ], rdi; spilling x319 to mem
mulx r13, rdi, rax; x13, x12<- x7 * arg1[4]
mov rdx, 0xfdc1767ae2ffffff ; moving imm to reg
mov [ rsp + 0x178 ], r11; spilling x317 to mem
mulx r12, r11, r14; x128, x127<- x105 * 0xfdc1767ae2ffffff
mov rdx, 0x0 ; moving imm to reg
adcx r15, rdx
mov rdx, 0xffffffffffffffff ; moving imm to reg
mov [ rsp + 0x180 ], r15; spilling x321 to mem
mov [ rsp + 0x188 ], rbx; spilling x313 to mem
mulx r15, rbx, r9; x217, x216<- x192 * 0xffffffffffffffff
mov [ rsp + 0x190 ], rbp; spilling x311 to mem
mov rbp, rdx; preserving value of 0xffffffffffffffff into a new reg
mov rdx, [ rsi + 0x20 ]; saving arg1[4] in rdx.
mov [ rsp + 0x198 ], r15; spilling x217 to mem
mov [ rsp + 0x1a0 ], r12; spilling x128 to mem
mulx r15, r12, [ rsp + 0x70 ]; x83, x82<- x1 * arg1[4]
movzx rdx, byte [ rsp + 0x100 ]; load byte memx27 to register64
clc;
mov rbp, -0x1 ; moving imm to reg
adcx rdx, rbp; loading flag
adcx rdi, [ rsp + 0xf8 ]
setc dl; spill CF x29 to reg (rdx)
movzx rbp, byte [ rsp + 0x160 ]; load byte memx223 to register64
clc;
mov [ rsp + 0x1a8 ], r15; spilling x83 to mem
mov r15, -0x1 ; moving imm to reg
adcx rbp, r15; loading flag
adcx rbx, [ rsp + 0x108 ]
setc bpl; spill CF x225 to reg (rbp)
movzx r15, byte [ rsp + 0xf0 ]; load byte memx95 to register64
clc;
mov [ rsp + 0x1b0 ], rbx; spilling x224 to mem
mov rbx, -0x1 ; moving imm to reg
adcx r15, rbx; loading flag
adcx r8, [ rsp + 0xe0 ]
seto r15b; spill OF x238 to reg (r15)
movzx rbx, byte [ rsp + 0x158 ]; load byte memx138 to register64
mov byte [ rsp + 0x1b8 ], bpl; spilling byte x225 to mem
mov rbp, -0x1 ; moving imm to reg
inc rbp; OF<-0x0, preserve CF (debug: state 5 (thanks Paul))
mov rbp, -0x1 ; moving imm to reg
adox rbx, rbp; loading flag
adox r11, [ rsp + 0xe8 ]
setc bl; spill CF x97 to reg (rbx)
movzx rbp, byte [ rsp + 0x140 ]; load byte memx69 to register64
clc;
mov byte [ rsp + 0x1c0 ], r15b; spilling byte x238 to mem
mov r15, -0x1 ; moving imm to reg
adcx rbp, r15; loading flag
adcx rdi, [ rsp + 0x58 ]
setc bpl; spill CF x71 to reg (rbp)
movzx r15, byte [ rsp + 0x138 ]; load byte memx110 to register64
clc;
mov [ rsp + 0x1c8 ], r13; spilling x13 to mem
mov r13, -0x1 ; moving imm to reg
adcx r15, r13; loading flag
adcx rdi, r8
setc r15b; spill CF x112 to reg (r15)
movzx r8, byte [ rsp + 0x130 ]; load byte memx153 to register64
clc;
adcx r8, r13; loading flag
adcx rdi, r11
xchg rdx, rax; x7, swapping with x29, which is currently in rdx
mulx r8, r11, [ rsi + 0x28 ]; x11, x10<- x7 * arg1[5]
setc r13b; spill CF x155 to reg (r13)
clc;
mov [ rsp + 0x1d0 ], r8; spilling x11 to mem
mov r8, -0x1 ; moving imm to reg
movzx rbx, bl
adcx rbx, r8; loading flag
adcx r10, r12
setc r12b; spill CF x99 to reg (r12)
clc;
movzx rax, al
adcx rax, r8; loading flag
adcx r11, [ rsp + 0x1c8 ]
setc al; spill CF x31 to reg (rax)
movzx rbx, byte [ rsp + 0x120 ]; load byte memx195 to register64
clc;
adcx rbx, r8; loading flag
adcx rdi, [ rsp + 0x30 ]
mov rbx, 0x7bc65c783158aea3 ; moving imm to reg
xchg rdx, rbx; 0x7bc65c783158aea3, swapping with x7, which is currently in rdx
mov byte [ rsp + 0x1d8 ], r12b; spilling byte x99 to mem
mulx r8, r12, r14; x126, x125<- x105 * 0x7bc65c783158aea3
mov rdx, 0x6cfc5fd681c52056 ; moving imm to reg
mov [ rsp + 0x1e0 ], r8; spilling x126 to mem
mov byte [ rsp + 0x1e8 ], al; spilling byte x31 to mem
mulx r8, rax, r14; x124, x123<- x105 * 0x6cfc5fd681c52056
mov rdx, 0xfdc1767ae2ffffff ; moving imm to reg
mov [ rsp + 0x1f0 ], r8; spilling x124 to mem
mov [ rsp + 0x1f8 ], rax; spilling x123 to mem
mulx r8, rax, r9; x215, x214<- x192 * 0xfdc1767ae2ffffff
mov rdx, [ rsp + 0x1a0 ]; x141, copying x128 here, cause x128 is needed in a reg for other than x141, namely all: , x141--x142, size: 1
adox rdx, r12
seto r12b; spill OF x142 to reg (r12)
mov [ rsp + 0x200 ], r8; spilling x215 to mem
mov r8, 0x0 ; moving imm to reg
dec r8; OF<-0x0, preserve CF (debug: state 4 (thanks Paul))
movzx rbp, bpl
adox rbp, r8; loading flag
adox r11, [ rsp + 0x80 ]
mov rbp, 0x7bc65c783158aea3 ; moving imm to reg
xchg rdx, r9; x192, swapping with x141, which is currently in rdx
mov byte [ rsp + 0x208 ], r12b; spilling byte x142 to mem
mulx r8, r12, rbp; x213, x212<- x192 * 0x7bc65c783158aea3
xchg rdx, rbx; x7, swapping with x192, which is currently in rdx
mulx rdx, rbp, [ rsi + 0x30 ]; x9, x8<- x7 * arg1[6]
mov [ rsp + 0x210 ], r8; spilling x213 to mem
setc r8b; spill CF x197 to reg (r8)
mov [ rsp + 0x218 ], r12; spilling x212 to mem
movzx r12, byte [ rsp + 0x1b8 ]; load byte memx225 to register64
clc;
mov [ rsp + 0x220 ], rdx; spilling x9 to mem
mov rdx, -0x1 ; moving imm to reg
adcx r12, rdx; loading flag
adcx rax, [ rsp + 0x198 ]
setc r12b; spill CF x227 to reg (r12)
clc;
movzx r15, r15b
adcx r15, rdx; loading flag
adcx r11, r10
setc r15b; spill CF x114 to reg (r15)
clc;
movzx r13, r13b
adcx r13, rdx; loading flag
adcx r11, r9
seto r13b; spill OF x73 to reg (r13)
movzx r10, byte [ rsp + 0x1c0 ]; load byte memx238 to register64
inc rdx; OF<-0x0, preserve CF (debug: state 2 (y: -1, n: 0))
mov r9, -0x1 ; moving imm to reg
adox r10, r9; loading flag
adox rdi, [ rsp + 0x1b0 ]
setc r10b; spill CF x157 to reg (r10)
clc;
movzx r8, r8b
adcx r8, r9; loading flag
adcx r11, [ rsp + 0x28 ]
adox rax, r11
seto r8b; spill OF x242 to reg (r8)
movzx r11, byte [ rsp + 0x1e8 ]; load byte memx31 to register64
dec rdx; OF<-0x0, preserve CF (debug: state 1(0x0) (thanks Paul))
adox r11, rdx; loading flag
adox rbp, [ rsp + 0x1d0 ]
mov rdx, [ rsp + 0x70 ]; x1 to rdx
mulx r9, r11, [ rsi + 0x28 ]; x81, x80<- x1 * arg1[5]
mov [ rsp + 0x228 ], rax; spilling x241 to mem
seto al; spill OF x33 to reg (rax)
mov [ rsp + 0x230 ], rdi; spilling x239 to mem
mov rdi, 0x0 ; moving imm to reg
dec rdi; OF<-0x0, preserve CF (debug: state 4 (thanks Paul))
movzx r13, r13b
adox r13, rdi; loading flag
adox rbp, [ rsp + 0xb0 ]
mov r13, [ rsp + 0x1f8 ]; load m64 x123 to register64
setc dil; spill CF x199 to reg (rdi)
mov byte [ rsp + 0x238 ], r8b; spilling byte x242 to mem
movzx r8, byte [ rsp + 0x208 ]; load byte memx142 to register64
clc;
mov byte [ rsp + 0x240 ], r12b; spilling byte x227 to mem
mov r12, -0x1 ; moving imm to reg
adcx r8, r12; loading flag
adcx r13, [ rsp + 0x1e0 ]
setc r8b; spill CF x144 to reg (r8)
movzx r12, byte [ rsp + 0x1d8 ]; load byte memx99 to register64
clc;
mov byte [ rsp + 0x248 ], dil; spilling byte x199 to mem
mov rdi, -0x1 ; moving imm to reg
adcx r12, rdi; loading flag
adcx r11, [ rsp + 0x1a8 ]
setc r12b; spill CF x101 to reg (r12)
clc;
movzx r15, r15b
adcx r15, rdi; loading flag
adcx rbp, r11
mulx rdx, r15, [ rsi + 0x30 ]; x79, x78<- x1 * arg1[6]
setc r11b; spill CF x116 to reg (r11)
clc;
movzx r10, r10b
adcx r10, rdi; loading flag
adcx rbp, r13
setc r10b; spill CF x159 to reg (r10)
clc;
movzx r12, r12b
adcx r12, rdi; loading flag
adcx r9, r15
mov r13, 0x2341f27177344 ; moving imm to reg
xchg rdx, r14; x105, swapping with x79, which is currently in rdx
mulx rdx, r12, r13; x122, x121<- x105 * 0x2341f27177344
movzx r15, al; x34, copying x33 here, cause x33 is needed in a reg for other than x34, namely all: , x34, size: 1
mov rdi, [ rsp + 0x220 ]; load m64 x9 to register64
lea r15, [ r15 + rdi ]; r8/64 + m8
setc dil; spill CF x103 to reg (rdi)
movzx rax, byte [ rsp + 0x248 ]; load byte memx199 to register64
clc;
mov r13, -0x1 ; moving imm to reg
adcx rax, r13; loading flag
adcx rbp, [ rsp + 0x20 ]
mov rax, [ rsp + 0xa8 ]; x76, copying x61 here, cause x61 is needed in a reg for other than x76, namely all: , x76--x77, size: 1
adox rax, r15
setc r15b; spill CF x201 to reg (r15)
clc;
movzx r8, r8b
adcx r8, r13; loading flag
adcx r12, [ rsp + 0x1f0 ]
setc r8b; spill CF x146 to reg (r8)
clc;
movzx r11, r11b
adcx r11, r13; loading flag
adcx rax, r9
mov r11, 0x6cfc5fd681c52056 ; moving imm to reg
xchg rdx, rbx; x192, swapping with x122, which is currently in rdx
mulx r9, r13, r11; x211, x210<- x192 * 0x6cfc5fd681c52056
movzx r11, dil; x104, copying x103 here, cause x103 is needed in a reg for other than x104, namely all: , x104, size: 1
lea r11, [ r11 + r14 ]
setc r14b; spill CF x118 to reg (r14)
clc;
mov rdi, -0x1 ; moving imm to reg
movzx r10, r10b
adcx r10, rdi; loading flag
adcx rax, r12
movzx r10, r8b; x147, copying x146 here, cause x146 is needed in a reg for other than x147, namely all: , x147, size: 1
lea r10, [ r10 + rbx ]
mov rbx, [ rsp + 0x200 ]; load m64 x215 to register64
setc r12b; spill CF x161 to reg (r12)
movzx r8, byte [ rsp + 0x240 ]; load byte memx227 to register64
clc;
adcx r8, rdi; loading flag
adcx rbx, [ rsp + 0x218 ]
mov r8, [ rsp + 0x210 ]; x230, copying x213 here, cause x213 is needed in a reg for other than x230, namely all: , x230--x231, size: 1
adcx r8, r13
mov r13, 0x2341f27177344 ; moving imm to reg
mulx rdx, rdi, r13; x209, x208<- x192 * 0x2341f27177344
movzx r13, r14b; x119, copying x118 here, cause x118 is needed in a reg for other than x119, namely all: , x119--x120, size: 1
adox r13, r11
adcx rdi, r9
seto r14b; spill OF x120 to reg (r14)
mov r9, -0x1 ; moving imm to reg
inc r9; OF<-0x0, preserve CF (debug: state 5 (thanks Paul))
mov r11, -0x1 ; moving imm to reg
movzx r15, r15b
adox r15, r11; loading flag
adox rax, [ rsp + 0x18 ]
adcx rdx, r9
clc;
movzx r12, r12b
adcx r12, r11; loading flag
adcx r13, r10
movzx r15, r14b; x164, copying x120 here, cause x120 is needed in a reg for other than x164, namely all: , x164, size: 1
adcx r15, r9
mov r12, [ rsp + 0x8 ]; x204, copying x189 here, cause x189 is needed in a reg for other than x204, namely all: , x204--x205, size: 1
adox r12, r13
movzx r10, byte [ rsp + 0x238 ]; load byte memx242 to register64
clc;
adcx r10, r11; loading flag
adcx rbp, rbx
adcx r8, rax
adcx rdi, r12
mov r10, [ rsp + 0x10 ]; x206, copying x191 here, cause x191 is needed in a reg for other than x206, namely all: , x206--x207, size: 1
adox r10, r15
mov rbx, rdx; preserving value of x234 into a new reg
mov rdx, [ rsp + 0x110 ]; saving x3 in rdx.
mulx r14, rax, [ rsi + 0x8 ]; x263, x262<- x3 * arg1[1]
adcx rbx, r10
setc r13b; spill CF x250 to reg (r13)
clc;
adcx rax, [ rsp + 0x118 ]
mulx r15, r12, [ rsi + 0x10 ]; x261, x260<- x3 * arg1[2]
adcx r12, r14
setc r10b; spill CF x269 to reg (r10)
movzx r14, byte [ rsp + 0x150 ]; load byte memx280 to register64
clc;
adcx r14, r11; loading flag
adcx rax, [ rsp + 0x230 ]
mov r14, [ rsp + 0x228 ]; x283, copying x241 here, cause x241 is needed in a reg for other than x283, namely all: , x283--x284, size: 1
adcx r14, r12
setc r12b; spill CF x284 to reg (r12)
clc;
adcx rcx, [ rsp + 0x128 ]
mov rcx, [ rsi + 0x28 ]; load m64 x5 to register64
movzx r9, r13b; x251, copying x250 here, cause x250 is needed in a reg for other than x251, namely all: , x251, size: 1
mov r11, 0x0 ; moving imm to reg
adox r9, r11
xchg rdx, rcx; x5, swapping with x3, which is currently in rdx
mulx r13, r11, [ rsi + 0x0 ]; x439, x438<- x5 * arg1[0]
mov [ rsp + 0x250 ], r9; spilling x251 to mem
mov r9, [ rsp + 0x148 ]; x324, copying x309 here, cause x309 is needed in a reg for other than x324, namely all: , x324--x325, size: 1
adcx r9, rax
mov rax, [ rsp + 0x190 ]; x326, copying x311 here, cause x311 is needed in a reg for other than x326, namely all: , x326--x327, size: 1
adcx rax, r14
mov r14, -0x2 ; moving imm to reg
inc r14; OF<-0x0, preserve CF (debug: 6; load -2, increase it, save as -1)
adox r9, [ rsp + 0x88 ]
mov r14, rdx; preserving value of x5 into a new reg
mov rdx, [ rsi + 0x18 ]; saving arg1[3] in rdx.
mov [ rsp + 0x258 ], rbx; spilling x249 to mem
mov [ rsp + 0x260 ], rdi; spilling x247 to mem
mulx rbx, rdi, rcx; x259, x258<- x3 * arg1[3]
mov rdx, 0xffffffffffffffff ; moving imm to reg
mov [ rsp + 0x268 ], r8; spilling x245 to mem
mov [ rsp + 0x270 ], rbx; spilling x259 to mem
mulx r8, rbx, r9; x395, x394<- x366 * 0xffffffffffffffff
seto dl; spill OF x367 to reg (rdx)
mov [ rsp + 0x278 ], r13; spilling x439 to mem
mov r13, -0x1 ; moving imm to reg
inc r13; OF<-0x0, preserve CF (debug: state 5 (thanks Paul))
mov r13, -0x1 ; moving imm to reg
movzx r10, r10b
adox r10, r13; loading flag
adox r15, rdi
mov r10, [ rsi + 0x30 ]; load m64 x6 to register64
setc dil; spill CF x327 to reg (rdi)
clc;
adcx rbx, r9
seto bl; spill OF x271 to reg (rbx)
inc r13; OF<-0x0, preserve CF (debug: state 2 (y: -1, n: 0))
mov r13, -0x1 ; moving imm to reg
movzx rdx, dl
adox rdx, r13; loading flag
adox rax, [ rsp + 0xa0 ]
mov rdx, 0xffffffffffffffff ; moving imm to reg
mov byte [ rsp + 0x280 ], bl; spilling byte x271 to mem
mulx r13, rbx, r9; x391, x390<- x366 * 0xffffffffffffffff
mov [ rsp + 0x288 ], r13; spilling x391 to mem
mov [ rsp + 0x290 ], r10; spilling x6 to mem
mulx r13, r10, r9; x393, x392<- x366 * 0xffffffffffffffff
seto dl; spill OF x369 to reg (rdx)
mov [ rsp + 0x298 ], r11; spilling x438 to mem
mov r11, -0x2 ; moving imm to reg
inc r11; OF<-0x0, preserve CF (debug: 6; load -2, increase it, save as -1)
adox r10, r8
adox rbx, r13
seto r8b; spill OF x399 to reg (r8)
inc r11; OF<-0x0, preserve CF (debug: state 2 (y: -1, n: 0))
mov r13, -0x1 ; moving imm to reg
movzx r12, r12b
adox r12, r13; loading flag
adox rbp, r15
xchg rdx, r14; x5, swapping with x369, which is currently in rdx
mulx r12, r15, [ rsi + 0x8 ]; x437, x436<- x5 * arg1[1]
setc r11b; spill CF x410 to reg (r11)
clc;
movzx rdi, dil
adcx rdi, r13; loading flag
adcx rbp, [ rsp + 0x188 ]
seto dil; spill OF x286 to reg (rdi)
inc r13; OF<-0x0, preserve CF (debug: state 2 (y: -1, n: 0))
mov r13, -0x1 ; moving imm to reg
movzx r11, r11b
adox r11, r13; loading flag
adox rax, r10
setc r11b; spill CF x329 to reg (r11)
clc;
adcx rax, [ rsp + 0x298 ]
mov r10, 0xffffffffffffffff ; moving imm to reg
xchg rdx, r10; 0xffffffffffffffff, swapping with x5, which is currently in rdx
mov byte [ rsp + 0x2a0 ], r8b; spilling byte x399 to mem
mulx r13, r8, rax; x482, x481<- x453 * 0xffffffffffffffff
mov [ rsp + 0x2a8 ], r12; spilling x437 to mem
mov byte [ rsp + 0x2b0 ], r11b; spilling byte x329 to mem
mulx r12, r11, rax; x480, x479<- x453 * 0xffffffffffffffff
setc dl; spill CF x454 to reg (rdx)
clc;
mov [ rsp + 0x2b8 ], r12; spilling x480 to mem
mov r12, -0x1 ; moving imm to reg
movzx r14, r14b
adcx r14, r12; loading flag
adcx rbp, [ rsp + 0x98 ]
seto r14b; spill OF x412 to reg (r14)
inc r12; OF<-0x0, preserve CF (debug: state 2 (y: -1, n: 0))
adox r8, rax
mov r8b, dl; preserving value of x454 into a new reg
mov rdx, [ rsi + 0x0 ]; saving arg1[0] in rdx.
mov byte [ rsp + 0x2c0 ], dil; spilling byte x286 to mem
mulx r12, rdi, [ rsp + 0x290 ]; x526, x525<- x6 * arg1[0]
setc dl; spill CF x371 to reg (rdx)
clc;
adcx r15, [ rsp + 0x278 ]
mov [ rsp + 0x2c8 ], r12; spilling x526 to mem
setc r12b; spill CF x441 to reg (r12)
clc;
mov byte [ rsp + 0x2d0 ], dl; spilling byte x371 to mem
mov rdx, -0x1 ; moving imm to reg
movzx r14, r14b
adcx r14, rdx; loading flag
adcx rbp, rbx
setc bl; spill CF x414 to reg (rbx)
clc;
adcx r11, r13
seto r14b; spill OF x497 to reg (r14)
inc rdx; OF<-0x0, preserve CF (debug: state 2 (y: -1, n: 0))
mov r13, -0x1 ; moving imm to reg
movzx r8, r8b
adox r8, r13; loading flag
adox rbp, r15
seto r8b; spill OF x456 to reg (r8)
dec rdx; OF<-0x0, preserve CF (debug: state 1(0x0) (thanks Paul))
movzx r14, r14b
adox r14, rdx; loading flag
adox rbp, r11
setc r13b; spill CF x484 to reg (r13)
clc;
adcx rdi, rbp
mov r14, 0xffffffffffffffff ; moving imm to reg
mov rdx, r14; 0xffffffffffffffff to rdx
mulx r14, r15, rdi; x567, x566<- x540 * 0xffffffffffffffff
mov r11, 0x6cfc5fd681c52056 ; moving imm to reg
xchg rdx, rdi; x540, swapping with 0xffffffffffffffff, which is currently in rdx
mulx rbp, rdi, r11; x559, x558<- x540 * 0x6cfc5fd681c52056
mov r11, 0xffffffffffffffff ; moving imm to reg
mov byte [ rsp + 0x2d8 ], r13b; spilling byte x484 to mem
mov byte [ rsp + 0x2e0 ], r8b; spilling byte x456 to mem
mulx r13, r8, r11; x569, x568<- x540 * 0xffffffffffffffff
mov byte [ rsp + 0x2e8 ], bl; spilling byte x414 to mem
mov byte [ rsp + 0x2f0 ], r12b; spilling byte x441 to mem
mulx rbx, r12, r11; x565, x564<- x540 * 0xffffffffffffffff
setc r11b; spill CF x541 to reg (r11)
clc;
adcx r15, r13
mov r13, 0x2341f27177344 ; moving imm to reg
mov [ rsp + 0x2f8 ], r15; spilling x570 to mem
mov byte [ rsp + 0x300 ], r11b; spilling byte x541 to mem
mulx r15, r11, r13; x557, x556<- x540 * 0x2341f27177344
mov r13, 0xfdc1767ae2ffffff ; moving imm to reg
mov [ rsp + 0x308 ], r15; spilling x557 to mem
mov [ rsp + 0x310 ], r8; spilling x568 to mem
mulx r15, r8, r13; x563, x562<- x540 * 0xfdc1767ae2ffffff
adcx r12, r14
adcx r8, rbx
mov r14, rdx; preserving value of x540 into a new reg
mov rdx, [ rsi + 0x10 ]; saving arg1[2] in rdx.
mulx rbx, r13, r10; x435, x434<- x5 * arg1[2]
mov rdx, 0x7bc65c783158aea3 ; moving imm to reg
mov [ rsp + 0x318 ], r8; spilling x574 to mem
mov [ rsp + 0x320 ], r12; spilling x572 to mem
mulx r8, r12, r14; x561, x560<- x540 * 0x7bc65c783158aea3
adcx r12, r15
adcx rdi, r8
mov r15, 0xfdc1767ae2ffffff ; moving imm to reg
xchg rdx, r15; 0xfdc1767ae2ffffff, swapping with 0x7bc65c783158aea3, which is currently in rdx
mulx r8, r15, r9; x389, x388<- x366 * 0xfdc1767ae2ffffff
adcx r11, rbp
setc bpl; spill CF x581 to reg (rbp)
clc;
adcx r14, [ rsp + 0x310 ]
mov r14, rdx; preserving value of 0xfdc1767ae2ffffff into a new reg
mov rdx, [ rsi + 0x20 ]; saving arg1[4] in rdx.
mov [ rsp + 0x328 ], r11; spilling x580 to mem
mov [ rsp + 0x330 ], rdi; spilling x578 to mem
mulx r11, rdi, rcx; x257, x256<- x3 * arg1[4]
setc dl; spill CF x584 to reg (rdx)
movzx r14, byte [ rsp + 0x280 ]; load byte memx271 to register64
clc;
mov [ rsp + 0x338 ], r12; spilling x576 to mem
mov r12, -0x1 ; moving imm to reg
adcx r14, r12; loading flag
adcx rdi, [ rsp + 0x270 ]
setc r14b; spill CF x273 to reg (r14)
movzx r12, byte [ rsp + 0x2c0 ]; load byte memx286 to register64
clc;
mov [ rsp + 0x340 ], r8; spilling x389 to mem
mov r8, -0x1 ; moving imm to reg
adcx r12, r8; loading flag
adcx rdi, [ rsp + 0x268 ]
setc r12b; spill CF x288 to reg (r12)
movzx r8, byte [ rsp + 0x2b0 ]; load byte memx329 to register64
clc;
mov [ rsp + 0x348 ], rbx; spilling x435 to mem
mov rbx, -0x1 ; moving imm to reg
adcx r8, rbx; loading flag
adcx rdi, [ rsp + 0x168 ]
seto r8b; spill OF x499 to reg (r8)
movzx rbx, byte [ rsp + 0x2f0 ]; load byte memx441 to register64
mov byte [ rsp + 0x350 ], r12b; spilling byte x288 to mem
mov r12, 0x0 ; moving imm to reg
dec r12; OF<-0x0, preserve CF (debug: state 4 (thanks Paul))
adox rbx, r12; loading flag
adox r13, [ rsp + 0x2a8 ]
movzx rbx, bpl; x582, copying x581 here, cause x581 is needed in a reg for other than x582, namely all: , x582, size: 1
mov r12, [ rsp + 0x308 ]; load m64 x557 to register64
lea rbx, [ rbx + r12 ]; r8/64 + m8
seto r12b; spill OF x443 to reg (r12)
movzx rbp, byte [ rsp + 0x2a0 ]; load byte memx399 to register64
mov [ rsp + 0x358 ], rbx; spilling x582 to mem
mov rbx, 0x0 ; moving imm to reg
dec rbx; OF<-0x0, preserve CF (debug: state 4 (thanks Paul))
adox rbp, rbx; loading flag
adox r15, [ rsp + 0x288 ]
setc bpl; spill CF x331 to reg (rbp)
movzx rbx, byte [ rsp + 0x2d0 ]; load byte memx371 to register64
clc;
mov byte [ rsp + 0x360 ], r12b; spilling byte x443 to mem
mov r12, -0x1 ; moving imm to reg
adcx rbx, r12; loading flag
adcx rdi, [ rsp + 0xc8 ]
setc bl; spill CF x373 to reg (rbx)
movzx r12, byte [ rsp + 0x2e8 ]; load byte memx414 to register64
clc;
mov byte [ rsp + 0x368 ], bpl; spilling byte x331 to mem
mov rbp, -0x1 ; moving imm to reg
adcx r12, rbp; loading flag
adcx rdi, r15
mov r12b, dl; preserving value of x584 into a new reg
mov rdx, [ rsi + 0x8 ]; saving arg1[1] in rdx.
mulx r15, rbp, [ rsp + 0x290 ]; x524, x523<- x6 * arg1[1]
mov rdx, 0xffffffffffffffff ; moving imm to reg
mov byte [ rsp + 0x370 ], bl; spilling byte x373 to mem
mov [ rsp + 0x378 ], r15; spilling x524 to mem
mulx rbx, r15, rax; x478, x477<- x453 * 0xffffffffffffffff
setc dl; spill CF x416 to reg (rdx)
mov [ rsp + 0x380 ], rbx; spilling x478 to mem
movzx rbx, byte [ rsp + 0x2e0 ]; load byte memx456 to register64
clc;
mov byte [ rsp + 0x388 ], r12b; spilling byte x584 to mem
mov r12, -0x1 ; moving imm to reg
adcx rbx, r12; loading flag
adcx rdi, r13
seto bl; spill OF x401 to reg (rbx)
movzx r13, byte [ rsp + 0x2d8 ]; load byte memx484 to register64
inc r12; OF<-0x0, preserve CF (debug: state 2 (y: -1, n: 0))
mov r12, -0x1 ; moving imm to reg
adox r13, r12; loading flag
adox r15, [ rsp + 0x2b8 ]
xchg rdx, rcx; x3, swapping with x416, which is currently in rdx
mulx r13, r12, [ rsi + 0x28 ]; x255, x254<- x3 * arg1[5]
mov [ rsp + 0x390 ], r13; spilling x255 to mem
setc r13b; spill CF x458 to reg (r13)
clc;
adcx rbp, [ rsp + 0x2c8 ]
mov byte [ rsp + 0x398 ], r13b; spilling byte x458 to mem
seto r13b; spill OF x486 to reg (r13)
mov byte [ rsp + 0x3a0 ], cl; spilling byte x416 to mem
mov rcx, 0x0 ; moving imm to reg
dec rcx; OF<-0x0, preserve CF (debug: state 4 (thanks Paul))
movzx r8, r8b
adox r8, rcx; loading flag
adox rdi, r15
setc r8b; spill CF x528 to reg (r8)
clc;
movzx r14, r14b
adcx r14, rcx; loading flag
adcx r11, r12
setc r14b; spill CF x275 to reg (r14)
movzx r15, byte [ rsp + 0x300 ]; load byte memx541 to register64
clc;
adcx r15, rcx; loading flag
adcx rdi, rbp
seto r15b; spill OF x501 to reg (r15)
movzx r12, byte [ rsp + 0x388 ]; load byte memx584 to register64
inc rcx; OF<-0x0, preserve CF (debug: state 2 (y: -1, n: 0))
mov rbp, -0x1 ; moving imm to reg
adox r12, rbp; loading flag
adox rdi, [ rsp + 0x2f8 ]
setc r12b; spill CF x543 to reg (r12)
seto bpl; spill OF x586 to reg (rbp)
mov byte [ rsp + 0x3a8 ], r14b; spilling byte x275 to mem
mov r14, rdi; x600, copying x585 here, cause x585 is needed in a reg for other than x600, namely all: , x600--x601, x616, size: 2
mov byte [ rsp + 0x3b0 ], r15b; spilling byte x501 to mem
mov r15, 0xffffffffffffffff ; moving imm to reg
sub r14, r15
mov rcx, rdx; preserving value of x3 into a new reg
mov rdx, [ rsi + 0x10 ]; saving arg1[2] in rdx.
mov [ rsp + 0x3b8 ], r14; spilling x600 to mem
mulx r15, r14, [ rsp + 0x290 ]; x522, x521<- x6 * arg1[2]
mov rdx, 0xfdc1767ae2ffffff ; moving imm to reg
mov [ rsp + 0x3c0 ], r15; spilling x522 to mem
mov byte [ rsp + 0x3c8 ], bpl; spilling byte x586 to mem
mulx r15, rbp, rax; x476, x475<- x453 * 0xfdc1767ae2ffffff
mov rdx, 0x0 ; moving imm to reg
dec rdx; OF<-0x0, preserve CF (debug: state 4 (thanks Paul))
movzx r13, r13b
adox r13, rdx; loading flag
adox rbp, [ rsp + 0x380 ]
mov rdx, r10; x5 to rdx
mulx r10, r13, [ rsi + 0x18 ]; x433, x432<- x5 * arg1[3]
mov [ rsp + 0x3d0 ], r15; spilling x476 to mem
seto r15b; spill OF x488 to reg (r15)
mov [ rsp + 0x3d8 ], r10; spilling x433 to mem
mov r10, -0x1 ; moving imm to reg
inc r10; OF<-0x0, preserve CF (debug: state 5 (thanks Paul))
mov r10, -0x1 ; moving imm to reg
movzx r8, r8b
adox r8, r10; loading flag
adox r14, [ rsp + 0x378 ]
seto r8b; spill OF x530 to reg (r8)
movzx r10, byte [ rsp + 0x350 ]; load byte memx288 to register64
mov byte [ rsp + 0x3e0 ], r15b; spilling byte x488 to mem
mov r15, 0x0 ; moving imm to reg
dec r15; OF<-0x0, preserve CF (debug: state 4 (thanks Paul))
adox r10, r15; loading flag
adox r11, [ rsp + 0x260 ]
setc r10b; spill CF x601 to reg (r10)
movzx r15, byte [ rsp + 0x368 ]; load byte memx331 to register64
clc;
mov byte [ rsp + 0x3e8 ], r8b; spilling byte x530 to mem
mov r8, -0x1 ; moving imm to reg
adcx r15, r8; loading flag
adcx r11, [ rsp + 0x178 ]
setc r15b; spill CF x333 to reg (r15)
movzx r8, byte [ rsp + 0x360 ]; load byte memx443 to register64
clc;
mov byte [ rsp + 0x3f0 ], r10b; spilling byte x601 to mem
mov r10, -0x1 ; moving imm to reg
adcx r8, r10; loading flag
adcx r13, [ rsp + 0x348 ]
mov r8, 0x7bc65c783158aea3 ; moving imm to reg
xchg rdx, r8; 0x7bc65c783158aea3, swapping with x5, which is currently in rdx
mov byte [ rsp + 0x3f8 ], r15b; spilling byte x333 to mem
mulx r10, r15, r9; x387, x386<- x366 * 0x7bc65c783158aea3
setc dl; spill CF x445 to reg (rdx)
clc;
mov [ rsp + 0x400 ], r10; spilling x387 to mem
mov r10, -0x1 ; moving imm to reg
movzx rbx, bl
adcx rbx, r10; loading flag
adcx r15, [ rsp + 0x340 ]
mov bl, dl; preserving value of x445 into a new reg
mov rdx, [ rsi + 0x30 ]; saving arg1[6] in rdx.
mulx rcx, r10, rcx; x253, x252<- x3 * arg1[6]
setc dl; spill CF x403 to reg (rdx)
mov byte [ rsp + 0x408 ], bl; spilling byte x445 to mem
movzx rbx, byte [ rsp + 0x370 ]; load byte memx373 to register64
clc;
mov [ rsp + 0x410 ], rcx; spilling x253 to mem
mov rcx, -0x1 ; moving imm to reg
adcx rbx, rcx; loading flag
adcx r11, [ rsp + 0xc0 ]
setc bl; spill CF x375 to reg (rbx)
movzx rcx, byte [ rsp + 0x3a0 ]; load byte memx416 to register64
clc;
mov byte [ rsp + 0x418 ], dl; spilling byte x403 to mem
mov rdx, -0x1 ; moving imm to reg
adcx rcx, rdx; loading flag
adcx r11, r15
setc cl; spill CF x418 to reg (rcx)
movzx r15, byte [ rsp + 0x398 ]; load byte memx458 to register64
clc;
adcx r15, rdx; loading flag
adcx r11, r13
seto r15b; spill OF x290 to reg (r15)
movzx r13, byte [ rsp + 0x3b0 ]; load byte memx501 to register64
inc rdx; OF<-0x0, preserve CF (debug: state 2 (y: -1, n: 0))
mov rdx, -0x1 ; moving imm to reg
adox r13, rdx; loading flag
adox r11, rbp
setc r13b; spill CF x460 to reg (r13)
clc;
movzx r12, r12b
adcx r12, rdx; loading flag
adcx r11, r14
seto r12b; spill OF x503 to reg (r12)
movzx rbp, byte [ rsp + 0x3a8 ]; load byte memx275 to register64
inc rdx; OF<-0x0, preserve CF (debug: state 2 (y: -1, n: 0))
mov r14, -0x1 ; moving imm to reg
adox rbp, r14; loading flag
adox r10, [ rsp + 0x390 ]
setc bpl; spill CF x545 to reg (rbp)
clc;
movzx r15, r15b
adcx r15, r14; loading flag
adcx r10, [ rsp + 0x258 ]
setc r15b; spill CF x292 to reg (r15)
movzx rdx, byte [ rsp + 0x3c8 ]; load byte memx586 to register64
clc;
adcx rdx, r14; loading flag
adcx r11, [ rsp + 0x320 ]
setc dl; spill CF x588 to reg (rdx)
movzx r14, byte [ rsp + 0x3f8 ]; load byte memx333 to register64
clc;
mov byte [ rsp + 0x420 ], bpl; spilling byte x545 to mem
mov rbp, -0x1 ; moving imm to reg
adcx r14, rbp; loading flag
adcx r10, [ rsp + 0x170 ]
mov r14, [ rsp + 0x410 ]; x278, copying x253 here, cause x253 is needed in a reg for other than x278, namely all: , x278, size: 1
mov rbp, 0x0 ; moving imm to reg
adox r14, rbp
dec rbp; OF<-0x0, preserve CF (debug: state 3 (y: 0, n: -1))
movzx rbx, bl
adox rbx, rbp; loading flag
adox r10, [ rsp + 0xb8 ]
mov bl, dl; preserving value of x588 into a new reg
mov rdx, [ rsi + 0x18 ]; saving arg1[3] in rdx.
mov byte [ rsp + 0x428 ], r12b; spilling byte x503 to mem
mulx rbp, r12, [ rsp + 0x290 ]; x520, x519<- x6 * arg1[3]
mov rdx, 0x6cfc5fd681c52056 ; moving imm to reg
mov [ rsp + 0x430 ], rbp; spilling x520 to mem
mov byte [ rsp + 0x438 ], bl; spilling byte x588 to mem
mulx rbp, rbx, r9; x385, x384<- x366 * 0x6cfc5fd681c52056
xchg rdx, r8; x5, swapping with 0x6cfc5fd681c52056, which is currently in rdx
mov [ rsp + 0x440 ], rbp; spilling x385 to mem
mulx r8, rbp, [ rsi + 0x20 ]; x431, x430<- x5 * arg1[4]
mov byte [ rsp + 0x448 ], r13b; spilling byte x460 to mem
setc r13b; spill CF x335 to reg (r13)
mov [ rsp + 0x450 ], r8; spilling x431 to mem
movzx r8, byte [ rsp + 0x3e8 ]; load byte memx530 to register64
clc;
mov [ rsp + 0x458 ], r11; spilling x587 to mem
mov r11, -0x1 ; moving imm to reg
adcx r8, r11; loading flag
adcx r12, [ rsp + 0x3c0 ]
setc r8b; spill CF x532 to reg (r8)
movzx r11, byte [ rsp + 0x408 ]; load byte memx445 to register64
clc;
mov [ rsp + 0x460 ], r12; spilling x531 to mem
mov r12, -0x1 ; moving imm to reg
adcx r11, r12; loading flag
adcx rbp, [ rsp + 0x3d8 ]
mov r11, 0x2341f27177344 ; moving imm to reg
xchg rdx, r9; x366, swapping with x5, which is currently in rdx
mulx rdx, r12, r11; x383, x382<- x366 * 0x2341f27177344
setc r11b; spill CF x447 to reg (r11)
mov byte [ rsp + 0x468 ], r8b; spilling byte x532 to mem
movzx r8, byte [ rsp + 0x418 ]; load byte memx403 to register64
clc;
mov [ rsp + 0x470 ], rdx; spilling x383 to mem
mov rdx, -0x1 ; moving imm to reg
adcx r8, rdx; loading flag
adcx rbx, [ rsp + 0x400 ]
setc r8b; spill CF x405 to reg (r8)
clc;
movzx rcx, cl
adcx rcx, rdx; loading flag
adcx r10, rbx
setc cl; spill CF x420 to reg (rcx)
clc;
movzx r15, r15b
adcx r15, rdx; loading flag
adcx r14, [ rsp + 0x250 ]
setc r15b; spill CF x294 to reg (r15)
seto bl; spill OF x377 to reg (rbx)
movzx rdx, byte [ rsp + 0x3f0 ]; x601, copying x601 here, cause x601 is needed in a reg for other than x601, namely all: , x602--x603, size: 1
add rdx, -0x1
mov rdx, [ rsp + 0x458 ]; x602, copying x587 here, cause x587 is needed in a reg for other than x602, namely all: , x617, x602--x603, size: 2
mov byte [ rsp + 0x478 ], cl; spilling byte x420 to mem
mov rcx, 0xffffffffffffffff ; moving imm to reg
sbb rdx, rcx
mov rcx, 0x0 ; moving imm to reg
dec rcx; OF<-0x0, preserve CF (debug: state 4 (thanks Paul))
movzx r13, r13b
adox r13, rcx; loading flag
adox r14, [ rsp + 0x180 ]
xchg rdx, r9; x5, swapping with x602, which is currently in rdx
mulx r13, rcx, [ rsi + 0x28 ]; x429, x428<- x5 * arg1[5]
mov [ rsp + 0x480 ], r9; spilling x602 to mem
setc r9b; spill CF x603 to reg (r9)
clc;
mov [ rsp + 0x488 ], r13; spilling x429 to mem
mov r13, -0x1 ; moving imm to reg
movzx r11, r11b
adcx r11, r13; loading flag
adcx rcx, [ rsp + 0x450 ]
mov r11, 0x6cfc5fd681c52056 ; moving imm to reg
xchg rdx, rax; x453, swapping with x5, which is currently in rdx
mov [ rsp + 0x490 ], rcx; spilling x448 to mem
mulx r13, rcx, r11; x472, x471<- x453 * 0x6cfc5fd681c52056
mov r11, 0x7bc65c783158aea3 ; moving imm to reg
mov [ rsp + 0x498 ], r13; spilling x472 to mem
mov [ rsp + 0x4a0 ], r14; spilling x336 to mem
mulx r13, r14, r11; x474, x473<- x453 * 0x7bc65c783158aea3
setc r11b; spill CF x449 to reg (r11)
mov byte [ rsp + 0x4a8 ], bl; spilling byte x377 to mem
movzx rbx, byte [ rsp + 0x448 ]; load byte memx460 to register64
clc;
mov byte [ rsp + 0x4b0 ], r9b; spilling byte x603 to mem
mov r9, -0x1 ; moving imm to reg
adcx rbx, r9; loading flag
adcx r10, rbp
movzx rbx, r15b; x338, copying x294 here, cause x294 is needed in a reg for other than x338, namely all: , x338, size: 1
mov rbp, 0x0 ; moving imm to reg
adox rbx, rbp
movzx r15, byte [ rsp + 0x3e0 ]; load byte memx488 to register64
dec rbp; OF<-0x0, preserve CF (debug: state 1(0x0) (thanks Paul))
adox r15, rbp; loading flag
adox r14, [ rsp + 0x3d0 ]
setc r9b; spill CF x462 to reg (r9)
movzx r15, byte [ rsp + 0x428 ]; load byte memx503 to register64
clc;
adcx r15, rbp; loading flag
adcx r10, r14
setc r15b; spill CF x505 to reg (r15)
clc;
movzx r8, r8b
adcx r8, rbp; loading flag
adcx r12, [ rsp + 0x440 ]
mov r8, [ rsp + 0x470 ]; x408, copying x383 here, cause x383 is needed in a reg for other than x408, namely all: , x408, size: 1
mov r14, 0x0 ; moving imm to reg
adcx r8, r14
movzx r14, byte [ rsp + 0x420 ]; load byte memx545 to register64
clc;
adcx r14, rbp; loading flag
adcx r10, [ rsp + 0x460 ]
adox rcx, r13
seto r14b; spill OF x492 to reg (r14)
movzx r13, byte [ rsp + 0x438 ]; load byte memx588 to register64
inc rbp; OF<-0x0, preserve CF (debug: state 2 (y: -1, n: 0))
mov rbp, -0x1 ; moving imm to reg
adox r13, rbp; loading flag
adox r10, [ rsp + 0x318 ]
setc r13b; spill CF x547 to reg (r13)
seto bpl; spill OF x590 to reg (rbp)
mov [ rsp + 0x4b8 ], r8; spilling x408 to mem
movzx r8, byte [ rsp + 0x4b0 ]; x603, copying x603 here, cause x603 is needed in a reg for other than x603, namely all: , x604--x605, size: 1
add r8, -0x1
mov r8, r10; x604, copying x589 here, cause x589 is needed in a reg for other than x604, namely all: , x618, x604--x605, size: 2
mov byte [ rsp + 0x4c0 ], r11b; spilling byte x449 to mem
mov r11, 0xffffffffffffffff ; moving imm to reg
sbb r8, r11
mov r11, rdx; preserving value of x453 into a new reg
mov rdx, [ rsp + 0x290 ]; saving x6 in rdx.
mov [ rsp + 0x4c8 ], r8; spilling x604 to mem
mov byte [ rsp + 0x4d0 ], bpl; spilling byte x590 to mem
mulx r8, rbp, [ rsi + 0x20 ]; x518, x517<- x6 * arg1[4]
mov [ rsp + 0x4d8 ], r8; spilling x518 to mem
mov r8, [ rsp + 0x4a0 ]; load m64 x336 to register64
mov [ rsp + 0x4e0 ], rbx; spilling x338 to mem
movzx rbx, byte [ rsp + 0x4a8 ]; load byte memx377 to register64
mov byte [ rsp + 0x4e8 ], r13b; spilling byte x547 to mem
mov r13, 0x0 ; moving imm to reg
dec r13; OF<-0x0, preserve CF (debug: state 4 (thanks Paul))
adox rbx, r13; loading flag
adox r8, [ rsp + 0xd8 ]
mov rbx, 0x2341f27177344 ; moving imm to reg
xchg rdx, r11; x453, swapping with x6, which is currently in rdx
mulx rdx, r13, rbx; x470, x469<- x453 * 0x2341f27177344
setc bl; spill CF x605 to reg (rbx)
mov [ rsp + 0x4f0 ], rdx; spilling x470 to mem
movzx rdx, byte [ rsp + 0x478 ]; load byte memx420 to register64
clc;
mov [ rsp + 0x4f8 ], rbp; spilling x517 to mem
mov rbp, -0x1 ; moving imm to reg
adcx rdx, rbp; loading flag
adcx r8, r12
seto dl; spill OF x379 to reg (rdx)
inc rbp; OF<-0x0, preserve CF (debug: state 2 (y: -1, n: 0))
mov r12, -0x1 ; moving imm to reg
movzx r14, r14b
adox r14, r12; loading flag
adox r13, [ rsp + 0x498 ]
setc r14b; spill CF x422 to reg (r14)
clc;
movzx r9, r9b
adcx r9, r12; loading flag
adcx r8, [ rsp + 0x490 ]
seto r9b; spill OF x494 to reg (r9)
inc r12; OF<-0x0, preserve CF (debug: state 1(-0x1) (thanks Paul))
mov rbp, -0x1 ; moving imm to reg
movzx r15, r15b
adox r15, rbp; loading flag
adox r8, rcx
mov r15, [ rsp + 0x4f8 ]; load m64 x517 to register64
seto cl; spill OF x507 to reg (rcx)
movzx r12, byte [ rsp + 0x468 ]; load byte memx532 to register64
inc rbp; OF<-0x0, preserve CF (debug: state 2 (y: -1, n: 0))
mov rbp, -0x1 ; moving imm to reg
adox r12, rbp; loading flag
adox r15, [ rsp + 0x430 ]
setc r12b; spill CF x464 to reg (r12)
movzx rbp, byte [ rsp + 0x4e8 ]; load byte memx547 to register64
clc;
mov byte [ rsp + 0x500 ], r9b; spilling byte x494 to mem
mov r9, -0x1 ; moving imm to reg
adcx rbp, r9; loading flag
adcx r8, r15
mov rbp, [ rsp + 0xd0 ]; load m64 x365 to register64
setc r15b; spill CF x549 to reg (r15)
clc;
movzx rdx, dl
adcx rdx, r9; loading flag
adcx rbp, [ rsp + 0x4e0 ]
setc dl; spill CF x381 to reg (rdx)
movzx r9, byte [ rsp + 0x4d0 ]; load byte memx590 to register64
clc;
mov byte [ rsp + 0x508 ], r15b; spilling byte x549 to mem
mov r15, -0x1 ; moving imm to reg
adcx r9, r15; loading flag
adcx r8, [ rsp + 0x338 ]
mov r9b, dl; preserving value of x381 into a new reg
mov rdx, [ rsi + 0x30 ]; saving arg1[6] in rdx.
mulx rax, r15, rax; x427, x426<- x5 * arg1[6]
mov rdx, [ rsi + 0x28 ]; arg1[5] to rdx
mov [ rsp + 0x510 ], r13; spilling x493 to mem
mov byte [ rsp + 0x518 ], cl; spilling byte x507 to mem
mulx r13, rcx, r11; x516, x515<- x6 * arg1[5]
setc dl; spill CF x592 to reg (rdx)
mov [ rsp + 0x520 ], r13; spilling x516 to mem
movzx r13, byte [ rsp + 0x4c0 ]; load byte memx449 to register64
clc;
mov byte [ rsp + 0x528 ], r9b; spilling byte x381 to mem
mov r9, -0x1 ; moving imm to reg
adcx r13, r9; loading flag
adcx r15, [ rsp + 0x488 ]
mov r13, 0x0 ; moving imm to reg
adcx rax, r13
mov r13, [ rsp + 0x4d8 ]; x535, copying x518 here, cause x518 is needed in a reg for other than x535, namely all: , x535--x536, size: 1
adox r13, rcx
clc;
movzx r14, r14b
adcx r14, r9; loading flag
adcx rbp, [ rsp + 0x4b8 ]
setc r14b; spill CF x424 to reg (r14)
seto cl; spill OF x536 to reg (rcx)
movzx r9, bl; x605, copying x605 here, cause x605 is needed in a reg for other than x605, namely all: , x606--x607, size: 1
add r9, -0x1
mov rbx, r8; x606, copying x591 here, cause x591 is needed in a reg for other than x606, namely all: , x619, x606--x607, size: 2
mov r9, 0xfdc1767ae2ffffff ; moving imm to reg
sbb rbx, r9
mov r9b, dl; preserving value of x592 into a new reg
mov rdx, [ rsi + 0x30 ]; saving arg1[6] in rdx.
mov [ rsp + 0x530 ], rbx; spilling x606 to mem
mulx r11, rbx, r11; x514, x513<- x6 * arg1[6]
mov rdx, -0x1 ; moving imm to reg
inc rdx; OF<-0x0, preserve CF (debug: state 5 (thanks Paul))
mov rdx, -0x1 ; moving imm to reg
movzx r12, r12b
adox r12, rdx; loading flag
adox rbp, r15
movzx r12, r14b; x425, copying x424 here, cause x424 is needed in a reg for other than x425, namely all: , x425, size: 1
movzx r15, byte [ rsp + 0x528 ]; load byte memx381 to register64
lea r12, [ r12 + r15 ]; r64+m8
setc r15b; spill CF x607 to reg (r15)
movzx r14, byte [ rsp + 0x518 ]; load byte memx507 to register64
clc;
adcx r14, rdx; loading flag
adcx rbp, [ rsp + 0x510 ]
movzx r14, byte [ rsp + 0x500 ]; x495, copying x494 here, cause x494 is needed in a reg for other than x495, namely all: , x495, size: 1
mov rdx, [ rsp + 0x4f0 ]; load m64 x470 to register64
lea r14, [ r14 + rdx ]; r8/64 + m8
adox rax, r12
seto dl; spill OF x468 to reg (rdx)
mov r12, 0x0 ; moving imm to reg
dec r12; OF<-0x0, preserve CF (debug: state 4 (thanks Paul))
movzx rcx, cl
adox rcx, r12; loading flag
adox rbx, [ rsp + 0x520 ]
adcx r14, rax
mov rcx, 0x0 ; moving imm to reg
adox r11, rcx
movzx rax, byte [ rsp + 0x508 ]; load byte memx549 to register64
dec rcx; OF<-0x0, preserve CF (debug: state 1(0x0) (thanks Paul))
adox rax, rcx; loading flag
adox rbp, r13
adox rbx, r14
movzx r12, dl; x512, copying x468 here, cause x468 is needed in a reg for other than x512, namely all: , x512, size: 1
mov rax, 0x0 ; moving imm to reg
adcx r12, rax
clc;
movzx r9, r9b
adcx r9, rcx; loading flag
adcx rbp, [ rsp + 0x330 ]
adox r11, r12
mov r9, [ rsp + 0x328 ]; x595, copying x580 here, cause x580 is needed in a reg for other than x595, namely all: , x595--x596, size: 1
adcx r9, rbx
mov r13, [ rsp + 0x358 ]; x597, copying x582 here, cause x582 is needed in a reg for other than x597, namely all: , x597--x598, size: 1
adcx r13, r11
setc dl; spill CF x598 to reg (rdx)
seto r14b; spill OF x555 to reg (r14)
movzx rbx, r15b; x607, copying x607 here, cause x607 is needed in a reg for other than x607, namely all: , x608--x609, size: 1
add rbx, -0x1
mov rbx, rbp; x608, copying x593 here, cause x593 is needed in a reg for other than x608, namely all: , x608--x609, x620, size: 2
mov r15, 0x7bc65c783158aea3 ; moving imm to reg
sbb rbx, r15
movzx r12, dl; x599, copying x598 here, cause x598 is needed in a reg for other than x599, namely all: , x599, size: 1
movzx r14, r14b
lea r12, [ r12 + r14 ]
mov r14, r9; x610, copying x595 here, cause x595 is needed in a reg for other than x610, namely all: , x621, x610--x611, size: 2
mov r11, 0x6cfc5fd681c52056 ; moving imm to reg
sbb r14, r11
mov rdx, r13; x612, copying x597 here, cause x597 is needed in a reg for other than x612, namely all: , x612--x613, x622, size: 2
mov rax, 0x2341f27177344 ; moving imm to reg
sbb rdx, rax
sbb r12, 0x00000000
cmovc rdx, r13; if CF, x622<- x597 (nzVar)
cmovc r14, r9; if CF, x621<- x595 (nzVar)
mov r12, [ rsp + 0x530 ]; x619, copying x606 here, cause x606 is needed in a reg for other than x619, namely all: , x619, size: 1
cmovc r12, r8; if CF, x619<- x591 (nzVar)
mov r8, [ rsp + 0x4c8 ]; x618, copying x604 here, cause x604 is needed in a reg for other than x618, namely all: , x618, size: 1
cmovc r8, r10; if CF, x618<- x589 (nzVar)
mov r10, [ rsp + 0x3b8 ]; x616, copying x600 here, cause x600 is needed in a reg for other than x616, namely all: , x616, size: 1
cmovc r10, rdi; if CF, x616<- x585 (nzVar)
mov rdi, [ rsp + 0x0 ]; load m64 out1 to register64
mov [ rdi + 0x10 ], r8; out1[2] = x618
cmovc rbx, rbp; if CF, x620<- x593 (nzVar)
mov [ rdi + 0x28 ], r14; out1[5] = x621
mov rbp, [ rsp + 0x480 ]; x617, copying x602 here, cause x602 is needed in a reg for other than x617, namely all: , x617, size: 1
cmovc rbp, [ rsp + 0x458 ]; if CF, x617<- x587 (nzVar)
mov [ rdi + 0x30 ], rdx; out1[6] = x622
mov [ rdi + 0x20 ], rbx; out1[4] = x620
mov [ rdi + 0x0 ], r10; out1[0] = x616
mov [ rdi + 0x8 ], rbp; out1[1] = x617
mov [ rdi + 0x18 ], r12; out1[3] = x619
mov rbx, [ rsp + 0x538 ]; restoring from stack
mov rbp, [ rsp + 0x540 ]; restoring from stack
mov r12, [ rsp + 0x548 ]; restoring from stack
mov r13, [ rsp + 0x550 ]; restoring from stack
mov r14, [ rsp + 0x558 ]; restoring from stack
mov r15, [ rsp + 0x560 ]; restoring from stack
add rsp, 0x568
ret
; cpu Intel(R) Core(TM) i9-10900K CPU @ 3.70GHz
; clocked at 4800 MHz
; first cyclecount 681.85, best 386.8, lastGood 390.08
; seed 2412526886283759
; CC / CFLAGS clang / -march=native -mtune=native -O3
; time needed: 6440623 ms / 60000 runs=> 107.34371666666667ms/run
; Time spent for assembling and measureing (initial batch_size=25, initial num_batches=101): 114887 ms
; Ratio (time for assembling + measure)/(total runtime for 60000runs): 0.017837870653196128
; number reverted permutation/ tried permutation: 18693 / 29897 =62.525%
; number reverted decision/ tried decision: 17520 / 30104 =58.198% |
programs/oeis/317/A317301.asm | jmorken/loda | 1 | 91394 | ; A317301: Sequence obtained by taking the general formula for generalized k-gonal numbers: m*((k - 2)*m - k + 4)/2, where m = 0, +1, -1, +2, -2, +3, -3, ... and k >= 5. Here k = 1.
; 0,1,-2,1,-5,0,-9,-2,-14,-5,-20,-9,-27,-14,-35,-20,-44,-27,-54,-35,-65,-44,-77,-54,-90,-65,-104,-77,-119,-90,-135,-104,-152,-119,-170,-135,-189,-152,-209,-170,-230,-189,-252,-209,-275,-230,-299,-252,-324,-275,-350,-299,-377,-324,-405,-350,-434,-377,-464,-405,-495,-434,-527,-464,-560,-495,-594,-527,-629,-560,-665,-594,-702,-629,-740,-665,-779,-702,-819,-740,-860,-779,-902,-819,-945,-860,-989,-902,-1034,-945,-1080,-989,-1127,-1034,-1175,-1080,-1224,-1127,-1274,-1175,-1325,-1224,-1377,-1274,-1430,-1325,-1484,-1377,-1539,-1430,-1595,-1484,-1652,-1539,-1710,-1595,-1769,-1652,-1829,-1710,-1890,-1769,-1952,-1829,-2015,-1890,-2079,-1952,-2144,-2015,-2210,-2079,-2277,-2144,-2345,-2210,-2414,-2277,-2484,-2345,-2555,-2414,-2627,-2484,-2700,-2555,-2774,-2627,-2849,-2700,-2925,-2774,-3002,-2849,-3080,-2925,-3159,-3002,-3239,-3080,-3320,-3159,-3402,-3239,-3485,-3320,-3569,-3402,-3654,-3485,-3740,-3569,-3827,-3654,-3915,-3740,-4004,-3827,-4094,-3915,-4185,-4004,-4277,-4094,-4370,-4185,-4464,-4277,-4559,-4370,-4655,-4464,-4752,-4559,-4850,-4655,-4949,-4752,-5049,-4850,-5150,-4949,-5252,-5049,-5355,-5150,-5459,-5252,-5564,-5355,-5670,-5459,-5777,-5564,-5885,-5670,-5994,-5777,-6104,-5885,-6215,-5994,-6327,-6104,-6440,-6215,-6554,-6327,-6669,-6440,-6785,-6554,-6902,-6669,-7020,-6785,-7139,-6902,-7259,-7020,-7380,-7139,-7502,-7259,-7625,-7380,-7749,-7502,-7874,-7625
mov $1,$0
mov $2,$0
lpb $2
sub $0,7
sub $2,1
add $1,$2
add $1,$0
sub $2,1
lpe
|
CRC/naive_methods_asm.asm | zu3st/CRC | 103 | 87900 | .CODE
; this poly CAN be changed to any desired 32-bit CRC poly.
P equ 082f63b78h
; uint32_t f(const void* M, uint32_t bytes);
;; OPTION 1
option_1_cf_jump PROC
xor eax, eax
test edx, edx
jz END_OF_LOOP
add rcx, rdx
neg rdx
START_OF_LOOP:
xor al, byte ptr [rcx + rdx]
REPEAT 8
shr eax, 1
jnc @F
xor eax, P
@@:
ENDM
inc rdx
jnz START_OF_LOOP
END_OF_LOOP:
ret
option_1_cf_jump ENDP
;; OPTION 2
option_2_multiply_mask PROC
xor eax, eax
test edx, edx
jz END_OF_LOOP
add rcx, rdx
neg rdx
mov r9d, P
START_OF_LOOP:
xor al, byte ptr [rcx + rdx]
REPEAT 8
mov r8d, eax
shr eax, 1
and r8d, 1
imul r8d, r9d
xor eax, r8d
ENDM
inc rdx
jnz START_OF_LOOP
END_OF_LOOP:
ret
option_2_multiply_mask ENDP
;; OPTION 3
option_3_bit_mask PROC
xor eax, eax
test edx, edx
jz END_OF_LOOP
add rcx, rdx
neg rdx
START_OF_LOOP:
xor al, byte ptr [rcx + rdx]
REPEAT 8
mov r8d, eax
shr eax, 1
and r8d, 1
neg r8d
and r8d, P
xor eax, r8d
ENDM
inc rdx
jnz START_OF_LOOP
END_OF_LOOP:
ret
option_3_bit_mask ENDP
;; OPTION 4
option_4_cmove PROC
xor eax, eax
test edx, edx
jz END_OF_LOOP
add rcx, rdx
neg rdx
mov r9d, P
START_OF_LOOP:
xor al, byte ptr [rcx + rdx]
REPEAT 8
xor r8d, r8d
shr eax, 1
cmovc r8d, r9d
xor eax, r8d
ENDM
inc rdx
jnz START_OF_LOOP
END_OF_LOOP:
ret
option_4_cmove ENDP
END
|
Transynther/x86/_processed/NC/_st_zr_4k_/i7-7700_9_0x48_notsx.log_21829_480.asm | ljhsiun2/medusa | 9 | 10918 | <reponame>ljhsiun2/medusa
.global s_prepare_buffers
s_prepare_buffers:
push %r11
push %r12
push %r8
push %r9
push %rbp
push %rcx
push %rdi
push %rdx
push %rsi
lea addresses_D_ht+0x1e745, %rbp
inc %rdx
movups (%rbp), %xmm0
vpextrq $1, %xmm0, %r11
nop
nop
nop
nop
sub %r9, %r9
lea addresses_A_ht+0x108e5, %r8
and %r12, %r12
mov $0x6162636465666768, %rdi
movq %rdi, %xmm0
movups %xmm0, (%r8)
nop
nop
nop
nop
cmp %r9, %r9
lea addresses_UC_ht+0x1577f, %rdi
nop
nop
nop
nop
nop
cmp $14423, %r11
mov (%rdi), %r12d
dec %r12
lea addresses_WT_ht+0x8c75, %r12
nop
nop
nop
nop
add %r8, %r8
movb (%r12), %r9b
nop
and %r9, %r9
lea addresses_D_ht+0x130e5, %rsi
lea addresses_WT_ht+0x13205, %rdi
nop
nop
nop
add $32311, %rdx
mov $27, %rcx
rep movsl
nop
nop
sub %rcx, %rcx
lea addresses_A_ht+0x15cc5, %r12
nop
nop
nop
nop
nop
sub %rsi, %rsi
movups (%r12), %xmm7
vpextrq $1, %xmm7, %rcx
nop
nop
add $28001, %r9
lea addresses_normal_ht+0x973d, %rsi
lea addresses_WC_ht+0x5fe5, %rdi
clflush (%rdi)
nop
nop
nop
nop
xor $40039, %rbp
mov $112, %rcx
rep movsl
dec %rdi
lea addresses_normal_ht+0x1545, %r11
dec %rbp
mov (%r11), %rdi
cmp $4693, %rcx
pop %rsi
pop %rdx
pop %rdi
pop %rcx
pop %rbp
pop %r9
pop %r8
pop %r12
pop %r11
ret
.global s_faulty_load
s_faulty_load:
push %r11
push %r8
push %r9
push %rbp
push %rdi
push %rsi
// Store
lea addresses_A+0x138e5, %rdi
and %r9, %r9
mov $0x5152535455565758, %r11
movq %r11, %xmm0
vmovups %ymm0, (%rdi)
nop
nop
nop
nop
nop
sub $10691, %rbp
// Faulty Load
mov $0x46f87100000008e5, %r9
nop
nop
nop
xor %r8, %r8
mov (%r9), %r11w
lea oracles, %rsi
and $0xff, %r11
shlq $12, %r11
mov (%rsi,%r11,1), %r11
pop %rsi
pop %rdi
pop %rbp
pop %r9
pop %r8
pop %r11
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'same': False, 'NT': False, 'AVXalign': False, 'size': 16, 'type': 'addresses_NC', 'congruent': 0}}
{'dst': {'same': False, 'NT': False, 'AVXalign': False, 'size': 32, 'type': 'addresses_A', 'congruent': 11}, 'OP': 'STOR'}
[Faulty Load]
{'OP': 'LOAD', 'src': {'same': True, 'NT': False, 'AVXalign': False, 'size': 2, 'type': 'addresses_NC', 'congruent': 0}}
<gen_prepare_buffer>
{'OP': 'LOAD', 'src': {'same': False, 'NT': False, 'AVXalign': False, 'size': 16, 'type': 'addresses_D_ht', 'congruent': 1}}
{'dst': {'same': False, 'NT': False, 'AVXalign': False, 'size': 16, 'type': 'addresses_A_ht', 'congruent': 8}, 'OP': 'STOR'}
{'OP': 'LOAD', 'src': {'same': False, 'NT': False, 'AVXalign': False, 'size': 4, 'type': 'addresses_UC_ht', 'congruent': 0}}
{'OP': 'LOAD', 'src': {'same': False, 'NT': False, 'AVXalign': False, 'size': 1, 'type': 'addresses_WT_ht', 'congruent': 4}}
{'dst': {'same': True, 'congruent': 5, 'type': 'addresses_WT_ht'}, 'OP': 'REPM', 'src': {'same': False, 'congruent': 11, 'type': 'addresses_D_ht'}}
{'OP': 'LOAD', 'src': {'same': True, 'NT': False, 'AVXalign': False, 'size': 16, 'type': 'addresses_A_ht', 'congruent': 1}}
{'dst': {'same': True, 'congruent': 8, 'type': 'addresses_WC_ht'}, 'OP': 'REPM', 'src': {'same': False, 'congruent': 0, 'type': 'addresses_normal_ht'}}
{'OP': 'LOAD', 'src': {'same': False, 'NT': False, 'AVXalign': False, 'size': 8, 'type': 'addresses_normal_ht', 'congruent': 5}}
{'58': 3823, '00': 18006}
58 58 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 58 00 00 00 00 00 00 00 00 00 00 58 58 58 58 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 58 00 00 58 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 58 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 58 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 58 58 58 58 58 58 58 58 58 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 58 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 58 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 58 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 58 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 58 58 58 00 58 58 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 58 00 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 00 58 58 58 58 58 58 58 58 58 58 58 58 58 00 58 58 58 58 58 58 00 58 58 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 00 58 58 58 58 58 58 58 00 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 00 00 00 00 00 00 00 00 00 00 00 00 00 58 00 00 00 00 00 00 00 00 00 00 00 00 58 58 58 00 58 58 58 58 58 58 58 58 58 58 58 58 58 58 00 00 00 58 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 00 58 58 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 58 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 58 58 58 58 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 58 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 58 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*/
|
programs/oeis/117/A117619.asm | neoneye/loda | 22 | 242217 | ; A117619: a(n) = n^2 + 7.
; 7,8,11,16,23,32,43,56,71,88,107,128,151,176,203,232,263,296,331,368,407,448,491,536,583,632,683,736,791,848,907,968,1031,1096,1163,1232,1303,1376,1451,1528,1607,1688,1771,1856,1943,2032,2123,2216,2311,2408,2507,2608,2711,2816,2923,3032,3143,3256,3371,3488,3607,3728,3851,3976,4103,4232,4363,4496,4631,4768,4907,5048,5191,5336,5483,5632,5783,5936,6091,6248,6407,6568,6731,6896,7063,7232,7403,7576,7751,7928,8107,8288,8471,8656,8843,9032,9223,9416,9611,9808
pow $0,2
add $0,7
|
specs/ada/server/tkmrpc-contexts-isa.ads | DrenfongWong/tkm-rpc | 0 | 12182 | <filename>specs/ada/server/tkmrpc-contexts-isa.ads<gh_stars>0
with Tkmrpc.Types;
package Tkmrpc.Contexts.isa
is
type isa_State_Type is
(clean,
-- Initial clean state
invalid,
-- Error state
stale,
-- IKE SA stale.
active
-- IKE SA is in active use.
);
function Get_State
(Id : Types.isa_id_type)
return isa_State_Type
with
Pre => Is_Valid (Id);
function Is_Valid (Id : Types.isa_id_type) return Boolean;
-- Returns True if the given id has a valid value.
function Has_ae_id
(Id : Types.isa_id_type;
ae_id : Types.ae_id_type)
return Boolean
with
Pre => Is_Valid (Id);
-- Returns True if the context specified by id has the given
-- ae_id value.
function Has_creation_time
(Id : Types.isa_id_type;
creation_time : Types.rel_time_type)
return Boolean
with
Pre => Is_Valid (Id);
-- Returns True if the context specified by id has the given
-- creation_time value.
function Has_ia_id
(Id : Types.isa_id_type;
ia_id : Types.ia_id_type)
return Boolean
with
Pre => Is_Valid (Id);
-- Returns True if the context specified by id has the given
-- ia_id value.
function Has_max_rekey_age
(Id : Types.isa_id_type;
max_rekey_age : Types.duration_type)
return Boolean
with
Pre => Is_Valid (Id);
-- Returns True if the context specified by id has the given
-- max_rekey_age value.
function Has_sk_d
(Id : Types.isa_id_type;
sk_d : Types.key_type)
return Boolean
with
Pre => Is_Valid (Id);
-- Returns True if the context specified by id has the given
-- sk_d value.
function Has_State
(Id : Types.isa_id_type;
State : isa_State_Type)
return Boolean
with
Pre => Is_Valid (Id);
-- Returns True if the context specified by id has the given
-- State value.
procedure create
(Id : Types.isa_id_type;
ae_id : Types.ae_id_type;
ia_id : Types.ia_id_type;
sk_d : Types.key_type;
creation_time : Types.rel_time_type)
with
Pre => Is_Valid (Id) and then
(Has_State (Id, clean)),
Post => Has_State (Id, active) and
Has_ae_id (Id, ae_id) and
Has_ia_id (Id, ia_id) and
Has_sk_d (Id, sk_d) and
Has_creation_time (Id, creation_time);
function get_ae_id
(Id : Types.isa_id_type)
return Types.ae_id_type
with
Pre => Is_Valid (Id) and then
(Has_State (Id, active)),
Post => Has_ae_id (Id, get_ae_id'Result);
function get_sk_d
(Id : Types.isa_id_type)
return Types.key_type
with
Pre => Is_Valid (Id) and then
(Has_State (Id, active)),
Post => Has_sk_d (Id, get_sk_d'Result);
procedure invalidate
(Id : Types.isa_id_type)
with
Pre => Is_Valid (Id),
Post => Has_State (Id, invalid);
procedure reset
(Id : Types.isa_id_type)
with
Pre => Is_Valid (Id),
Post => Has_State (Id, clean);
end Tkmrpc.Contexts.isa;
|
sdk-6.5.20/tools/led/example/sdk5665.asm | copslock/broadcom_cpri | 0 | 90735 | ;
; $Id: sdk5665.asm,v 1.8 2012/03/02 14:34:03 yaronm Exp $
;
; This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
;
; Copyright 2007-2020 Broadcom Inc. All rights reserved.
;
;
; This is the default program for the 5665 SDK (BCM95665K4S)
;
; To start it, use the following commands from BCM:
;
; 0:led load sdk5665.hex
; *:led start
;
; The BCM5665 SDK has 26 columns of 4 LEDs each, as shown below:
;
; L01 L03 L05 L07 L09 L11 L13 L15 L17 L19 ... L47 LG1 LG3
; A01 A03 A05 A07 A09 A11 A13 A15 A17 A19 ... A47 AG1 LG3
; L02 L04 L06 L08 L10 L12 L14 L16 L18 L20 ... L48 LG2 LG4
; A02 A04 A06 A08 A10 A12 A14 A16 A18 A20 ... A48 AG2 LG4
;
; There is one bit per LED with the following colors:
; ZERO Green
; ONE Black
;
; The bits are shifted out in the following order:
; A01, L01, ..., A48, L48, AG1, LG1, ..., AG4, LG4
;
; Current implementation:
;
; L01 reflects port 1 link status
; A01 reflects port 1 activity
;
; On the bringup board, the LED polarity is 0 on, 1 off.
;
;
MIN_FE_PORT EQU 0
BREAK_FE_PORT EQU 24
RESUME_FE_PORT EQU 32
MAX_FE_PORT EQU 55
STOP_FE_PORT EQU 56
NUM_FE_PORT EQU 48
MIN_GE_PORT EQU 24
MAX_GE_PORT EQU 27
STOP_GE_PORT EQU 28
NUM_GE_PORT EQU 4
MIN_PORT EQU 0
MAX_PORT EQU 55
NUM_PORT EQU 52
PACK_SRC EQU 0
PACK_DST EQU 128
PACK_NUM EQU 13
;
; Main Update Routine
;
; This routine is called once per tick.
;
update:
sub a,a ; ld a,MIN_FE_PORT (but only one instr)
up1:
call doport
cmp a,BREAK_FE_PORT
jnz up1
ld a,RESUME_FE_PORT
up2:
call doport
cmp a,STOP_FE_PORT
jnz up2
ld a,MIN_GE_PORT
up3:
call doport
cmp a,STOP_GE_PORT
jnz up3
;
; This bit is a workaround for a bug in the 5665 LED processor.
;
; The pack instruction should put the data into data mem at 0x80.
; However, the internal register to store this address is only 7 bits.
; So the data is packed starting at address 0.
; This leads to two caveats:
;
; 1) Port 0 data _MUST_ be consumed before the first pack instruction.
;
; 2) The output data must be moved from location 0 to location 128.
;
;
sub b,b ; ld b,PACK_SRC (but only one instr)
ld a,PACK_DST
packmove:
ld (a),(b)
inc a
inc b
cmp b,PACK_NUM
jnz packmove
send 104 ; (48 + 4) * 2 bits
doport:
port a
ld (PORT_NUM),a
call link_status ; Lower LED for this port
call activity ; Upper LED for this port
; We need to cache the output bits to not stomp Port 0 data.
ld a,(LINK_CACHE)
pushst a
pack
ld a,(ACT_CACHE)
pushst a
pack
ld a,(PORT_NUM)
inc a
ret
activity:
pushst RX
pop
jc act_led_set
pushst TX
pop
jc act_led_set
ld a,ONE ; Off
ld (ACT_CACHE),a
ret
act_led_set:
ld a,ZERO ; On
ld (ACT_CACHE),a
ret
link_status:
ld a,(PORT_NUM) ; Check for link down
ld b,PORTDATA
add b,a
ld b,(b)
tst b,0
jnc ls_led_clear
ld a,ZERO ; On
ld (LINK_CACHE),a
ret
ls_led_clear:
ld a,ONE ; Off
ld (LINK_CACHE),a
ret
;
; Variables (SDK software initializes LED memory from 0x80-0xff to 0)
;
TXRX_ALT_COUNT equ 0xe0
HD_COUNT equ 0xe1
GIG_ALT_COUNT equ 0xe2
PORT_NUM equ 0xe3
LINK_CACHE equ 0xe4
ACT_CACHE equ 0xe5
;
; Port data, which must be updated continually by main CPU's
; linkscan task. See $SDK/src/appl/diag/ledproc.c for examples.
; In this program, bit 0 is assumed to contain the link up/down status.
;
PORTDATA equ 0xa0 ; Size 57 bytes
;
; Symbolic names for the bits of the port status fields
;
RX equ 0x0 ; received packet
TX equ 0x1 ; transmitted packet
COLL equ 0x2 ; collision indicator
SPEED_C equ 0x3 ; 100 Mbps
SPEED_M equ 0x4 ; 1000 Mbps
DUPLEX equ 0x5 ; half/full duplex
FLOW equ 0x6 ; flow control capable
LINKUP equ 0x7 ; link down/up status
LINKEN equ 0x8 ; link disabled/enabled status
ZERO equ 0xE ; always 0
ONE equ 0xF ; always 1
|
tests/assembly/logical operations/0302.asm | danecreekphotography/6502ts | 0 | 85823 | <filename>tests/assembly/logical operations/0302.asm
; 0302 - ORA immediate
.segment "VECTORS"
.word $eaea
.word init
.word $eaea
.code
init:
ora #%10000000 ; Test negative
ora #%00000000 ; Test zero
|
_anim/obj43.asm | vladjester2020/Sonic1TMR | 0 | 244727 | ; ---------------------------------------------------------------------------
; Animation script - Roller enemy
; ---------------------------------------------------------------------------
dc.w byte_E190-Ani_obj43
dc.w byte_E196-Ani_obj43
dc.w byte_E19C-Ani_obj43
byte_E190: dc.b $F, 2, 1, 0, $FE, 1
byte_E196: dc.b $F, 1, 2, $FD, 2, 0
byte_E19C: dc.b 3, 3, 4, 2, $FF
even |
gcc-gcc-7_3_0-release/gcc/ada/g-traceb.ads | best08618/asylo | 7 | 21703 | <reponame>best08618/asylo
------------------------------------------------------------------------------
-- --
-- GNAT RUN-TIME COMPONENTS --
-- --
-- G N A T . T R A C E B A C K --
-- --
-- S p e c --
-- --
-- Copyright (C) 1999-2016, AdaCore --
-- --
-- GNAT is free software; you can redistribute it and/or modify it under --
-- terms of the GNU General Public License as published by the Free Soft- --
-- ware Foundation; either version 3, or (at your option) any later ver- --
-- sion. GNAT is distributed in the hope that it will be useful, but WITH- --
-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY --
-- or FITNESS FOR A PARTICULAR PURPOSE. --
-- --
-- As a special exception under Section 7 of GPL version 3, you are granted --
-- additional permissions described in the GCC Runtime Library Exception, --
-- version 3.1, as published by the Free Software Foundation. --
-- --
-- You should have received a copy of the GNU General Public License and --
-- a copy of the GCC Runtime Library Exception along with this program; --
-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see --
-- <http://www.gnu.org/licenses/>. --
-- --
-- GNAT was originally developed by the GNAT team at New York University. --
-- Extensive contributions were provided by Ada Core Technologies Inc. --
-- --
------------------------------------------------------------------------------
-- Run-time non-symbolic traceback support
-- This package provides a method for generating a traceback of the
-- current execution location. The traceback shows the locations of
-- calls in the call chain, up to either the top or a designated
-- number of levels.
-- The traceback information is in the form of absolute code locations.
-- These code locations may be converted to corresponding source locations
-- using the external addr2line utility, or from within GDB.
-- In order to use this facility, in some cases the binder must be invoked
-- with -E switch (store the backtrace with exception occurrence). Please
-- refer to gnatbind documentation for more information.
-- To analyze the code locations later using addr2line or gdb, the necessary
-- units must be compiled with the debugging switch -g in the usual manner.
-- Note that it is not necessary to compile with -g to use Call_Chain. In
-- other words, the following sequence of steps can be used:
-- Compile without -g
-- Run the program, and call Call_Chain
-- Recompile with -g
-- Use addr2line to interpret the absolute call locations (note that
-- addr2line expects addresses in hexadecimal format).
-- This capability is currently supported on the following targets:
-- AiX PowerPC
-- GNU/Linux x86
-- GNU/Linux PowerPC
-- LynxOS x86
-- LynxOS 178 xcoff PowerPC
-- LynxOS 178 elf PowerPC
-- Solaris x86
-- Solaris sparc
-- VxWorks ARM
-- VxWorks7 ARM
-- VxWorks PowerPC
-- VxWorks x86
-- Windows XP
-- Note: see also GNAT.Traceback.Symbolic, a child unit in file g-trasym.ads
-- providing symbolic trace back capability for a subset of the above targets.
with System;
with Ada.Exceptions.Traceback;
package GNAT.Traceback is
pragma Elaborate_Body;
subtype Code_Loc is System.Address;
-- Code location used in building tracebacks
subtype Tracebacks_Array is Ada.Exceptions.Traceback.Tracebacks_Array;
-- Traceback array used to hold a generated traceback list
----------------
-- Call_Chain --
----------------
procedure Call_Chain (Traceback : out Tracebacks_Array; Len : out Natural);
-- Store up to Traceback'Length tracebacks corresponding to the current
-- call chain. The first entry stored corresponds to the deepest level
-- of subprogram calls. Len shows the number of traceback entries stored.
-- It will be equal to Traceback'Length unless the entire traceback is
-- shorter, in which case positions in Traceback past the Len position
-- are undefined on return.
end GNAT.Traceback;
|
libsrc/_DEVELOPMENT/compress/zx1/z80/asm_dzx1_turbo.asm | ahjelm/z88dk | 640 | 3370 | <reponame>ahjelm/z88dk
IF !__CPU_INTEL__ && !__CPU_GBZ80__
SECTION smc_compress
PUBLIC asm_dzx1_turbo
asm_dzx1_turbo:
INCLUDE "dzx1_turbo.asm"
ENDIF
|
oeis/340/A340683.asm | neoneye/loda-programs | 11 | 12243 | ; A340683: a(n) = A007949((A003961(A003961(n))+1)/2), where A003961 shifts the prime factorization of n one step towards larger primes, and A007949(x) gives the exponent of largest power of 3 dividing x.
; Submitted by <NAME>(s3)
; 0,1,0,0,1,2,0,2,0,0,2,0,0,1,1,0,1,1,1,1,0,0,0,1,0,1,0,0,0,0,1,1,1,0,2,0,0,0,0,0,1,1,3,1,3,1,1,0,0,1,4,0,0,1,0,1,1,1,0,2,2,0,0,0,1,0,0,2,0,0,0,1,1,3,0,1,1,2,2,2,0,0,0,0,0,0,0,0,1,0,0,0,2,0,0,1,0,2,1,0
seq $0,253885 ; Permutation of even numbers: a(n) = A003961(n+1) - 1.
seq $0,292251 ; The 3-adic valuation of A048673(n).
|
sort/bubblesort.asm | MrRaffo/c64routines | 0 | 103 | ;==================
; BUBBLE SORT
;==================
;SORT_Bubble8Bit
; sorts a list of unsigned bytes in place, not entirely useless for C64
; as sprite multiplexors use 'almost' sorted lists and so bubble sort can
; exit early when handling them
; PARAM1 - low byte of address of first item in list
; PARAM2 - high byte of address of first item in list
; PARAM3 - length of list, number of items to sort
; RETVAL1 - number of passes to sort
!zone SORT_Bubble8Bit
SORT_Bubble8Bit
lda PARAM1
sta ZEROPAGE_POINTER_1
lda PARAM2
sta ZEROPAGE_POINTER_1 + 1
dec PARAM3 ; size of list
ldx #$00 ; did a swap happen?
ldy #$00 ; zeropage addressing offset
sty RETVAL1 ; number of passes
.BubbleLoop
lda (ZEROPAGE_POINTER_1),y
iny
cmp (ZEROPAGE_POINTER_1),y
; carry is set if number in accumulator is larger than one encountered
bcc .NoSwapNeeded
beq .NoSwapNeeded
.SwapValues
; make the swap, this could probably be more efficient
inx ; register that a swap happened
sta PARAM4
lda (ZEROPAGE_POINTER_1),y
dey
sta (ZEROPAGE_POINTER_1),y
iny
lda PARAM4
sta (ZEROPAGE_POINTER_1),y
.NoSwapNeeded
cpy PARAM3 ; check if we've hit the end of the list
bne .BubbleLoop
.CheckEndOfLoop
; this should be hit at the end of every pass
inc RETVAL1
cpx #$00 ; check if no exchanges were needed and exit early
beq .BubbleDone
ldy #$00 ; prepare for another pass
ldx #$00
jmp .BubbleLoop
.BubbleDone
|
asm/0000_LDA.asm | barrettotte/angstrom-cpu | 0 | 165026 | <reponame>barrettotte/angstrom-cpu
; load accumulator with memory
LDI #0 ; 00010000 00000000 0x1000
ADI #1 ; 10000000 00000001 0x8001
STA #0x21 ; 00100000 00010101 0x2015
LDI #0 ; 00010000 00000000 0x1000
LDA #0x21 ; 00000000 00010101 0x0015
|
examples/simulator/src/gdb_remote-target.adb | Fabien-Chouteau/libriscv | 0 | 19245 | with GDB_Remote.Agent; use GDB_Remote.Agent;
package body GDB_Remote.Target is
subtype Dispatch is Class;
---------------
-- From_Host --
---------------
procedure From_Host (This : in out Instance; C : Character) is
Evt : constant Agent.Event := This.Received (C);
begin
case Evt.Kind is
when Agent.None | Agent.Got_Ack | Agent.Got_Nack =>
null;
when Agent.Got_Packet =>
case Evt.P.Kind is
when Bad_Packet =>
This.Nack;
when Unknown_Packet =>
This.Send_Packet ("");
when Detach =>
This.Ack;
This.Send_Packet ("OK");
Dispatch (This).Detach;
when General_Query => null;
case Evt.P.Q_Topic is
when Supported =>
This.Ack;
This.Send_Packet ("PacketSize=1024");
when TStatus =>
-- Send empty packet because we don't support Traces...
This.Ack;
This.Send_Packet ("");
when Attached =>
This.Ack;
This.Send_Packet ("1");
when Thread_Info_Start =>
This.Ack;
This.Send_Packet ("m1");
when Thread_Info_Cont =>
This.Ack;
This.Send_Packet ("l");
when Unknown_General_Query =>
-- Send empty packet when we don't know the query
This.Ack;
This.Send_Packet ("");
end case;
when Query_Supported_Continue =>
This.Ack;
This.Send_Packet ("vCont;c;s;t");
when Must_Reply_Empty =>
This.Ack;
This.Send_Packet ("");
when Question_Halt =>
This.Ack;
This.Send_Packet ("T05thread:01;");
when Set_Thread =>
This.Ack;
This.Send_Packet ("OK");
when Read_General_Registers =>
This.Ack;
This.Start_Packet;
declare
Success : Boolean := False;
Data : Register;
begin
for Id in 0 .. Dispatch (This).Last_General_Register loop
Dispatch (This).Read_Register (Id, Data, Success);
Push_Register (Parent.Instance (This), Data);
end loop;
end;
This.End_Packet;
when Read_Register =>
This.Ack;
declare
Success : Boolean := False;
Data : Register;
begin
Dispatch (This).Read_Register (Evt.P.Register_Id, Data, Success);
if Success then
This.Start_Packet;
Push_Register (Parent.Instance (This), Data);
This.End_Packet;
else
This.Send_Packet ("");
end if;
end;
when Read_Memory =>
This.Ack;
This.Start_Packet;
declare
Data : Unsigned_8;
Success : Boolean;
begin
for X in Evt.P.M_Address .. Evt.P.M_Address + Evt.P.M_Size - 1 loop
Dispatch (This).Read_Memory (X, Data, Success);
if Success then
This.Push_Data (Hex (Data));
else
-- In theory GDB is able to handle a shorter answer
-- than expected if the target "can read only part of
-- the region of memory", in practice this makes GDB
-- crash. So we send zero instead.
This.Push_Data ("00");
end if;
end loop;
end;
This.End_Packet;
when Write_Memory =>
This.Ack;
declare
Data : Unsigned_8;
Success : Boolean;
begin
for X in Evt.P.M_Address .. Evt.P.M_Address + Evt.P.M_Size - 1 loop
Data := Dispatch (This).Next_Data (Success);
if not Success then
This.Send_Packet ("E ");
return;
end if;
Dispatch (This).Write_Memory (X, Data, Success);
if not Success then
This.Send_Packet ("E ");
return;
end if;
end loop;
end;
This.Send_Packet ("OK");
when Continue =>
This.Ack;
Dispatch (This).Continue;
when Continue_Addr =>
This.Ack;
Dispatch (This).Continue_At (Evt.P.C_Address);
when Single_Step =>
This.Ack;
Dispatch (This).Continue (Single_Step => True);
when Single_Step_Addr =>
This.Ack;
Dispatch (This).Continue_At (Evt.P.C_Address,
Single_Step => True);
when Insert_Breakpoint | Remove_Breakpoint =>
This.Ack;
if Dispatch (This).Supported (Evt.P.B_Type) then
if Evt.P.Kind = Insert_Breakpoint then
Dispatch (This).Insert_Breakpoint (Evt.P.B_Type,
Evt.P.B_Addr,
Evt.P.B_Kind);
else
Dispatch (This).Remove_Breakpoint (Evt.P.B_Type,
Evt.P.B_Addr,
Evt.P.B_Kind);
end if;
else
Dispatch (This).Send_Packet ("");
end if;
end case;
when Agent.Got_An_Interrupt =>
Dispatch (This).Halt;
This.Send_Packet ("T02Thread:01;");
end case;
end From_Host;
end GDB_Remote.Target;
|
builtin_echo.asm | jhunkeler/minos | 1 | 4452 | <filename>builtin_echo.asm
%ifndef _BUILTIN_ECHO_ASM
%define _BUILTIN_ECHO_ASM
builtin_echo:
push bp
mov bp, sp
mov cx, word [bp + 4] ; argc
mov bx, word [bp + 6] ; argv
cmp cx, 0 ; if no arguments, return
jbe .return
.output: ; print argv
push word [bx]
push .msg_fmt
call printf
add sp, 2 * 2
add bx, 2
dec cx
jne .output
.return:
mov sp, bp
pop bp
ret
.msg_fmt db '%s ', 0
%endif
|
src/Substitution.agda | nad/chi | 2 | 6705 | ------------------------------------------------------------------------
-- Some substitution lemmas
------------------------------------------------------------------------
open import Atom
module Substitution (atoms : χ-atoms) where
open import Equality.Propositional
open import Prelude hiding (const)
open import Bag-equivalence equality-with-J using (_∈_)
open import Chi atoms
open χ-atoms atoms
private
variable
c : Const
e e′ e″ : Exp
x y : Var
xs : List Var
-- Some simplification lemmas for the substitution functions.
var-step-≡ : x ≡ y → var y [ x ← e ] ≡ e
var-step-≡ {x = x} {y = y} x≡y with x V.≟ y
… | yes _ = refl
… | no x≢y = ⊥-elim (x≢y x≡y)
var-step-≢ : x ≢ y → var y [ x ← e ] ≡ var y
var-step-≢ {x = x} {y = y} x≢y with x V.≟ y
… | no _ = refl
… | yes x≡y = ⊥-elim (x≢y x≡y)
lambda-step-≡ : x ≡ y → lambda y e [ x ← e′ ] ≡ lambda y e
lambda-step-≡ {x = x} {y = y} x≡y with x V.≟ y
… | yes _ = refl
… | no x≢y = ⊥-elim (x≢y x≡y)
lambda-step-≢ :
x ≢ y → lambda y e [ x ← e′ ] ≡ lambda y (e [ x ← e′ ])
lambda-step-≢ {x = x} {y = y} x≢y with x V.≟ y
… | no _ = refl
… | yes x≡y = ⊥-elim (x≢y x≡y)
rec-step-≡ : x ≡ y → rec y e [ x ← e′ ] ≡ rec y e
rec-step-≡ {x = x} {y = y} x≡y with x V.≟ y
… | yes _ = refl
… | no x≢y = ⊥-elim (x≢y x≡y)
rec-step-≢ :
x ≢ y → rec y e [ x ← e′ ] ≡ rec y (e [ x ← e′ ])
rec-step-≢ {x = x} {y = y} x≢y with x V.≟ y
… | no _ = refl
… | yes x≡y = ⊥-elim (x≢y x≡y)
branch-step-∈ :
x ∈ xs →
branch c xs e [ x ← e′ ]B ≡ branch c xs e
branch-step-∈ {x = x} {xs = xs} x∈xs with V.member x xs
… | yes _ = refl
… | no x∉xs = ⊥-elim (x∉xs x∈xs)
branch-step-∉ :
¬ x ∈ xs →
branch c xs e [ x ← e′ ]B ≡ branch c xs (e [ x ← e′ ])
branch-step-∉ {x = x} {xs = xs} x∉xs with V.member x xs
… | no _ = refl
… | yes x∈xs = ⊥-elim (x∉xs x∈xs)
-- A "fusion" lemma.
mutual
fusion : ∀ e → e [ x ← e′ ] [ x ← e″ ] ≡ e [ x ← e′ [ x ← e″ ] ]
fusion (apply e₁ e₂) =
cong₂ apply (fusion e₁) (fusion e₂)
fusion {x = x} {e′ = e′} {e″ = e″} (lambda y e) with x V.≟ y
… | yes _ = refl
… | no _ =
lambda y (e [ x ← e′ ] [ x ← e″ ]) ≡⟨ cong (lambda _) $ fusion e ⟩∎
lambda y (e [ x ← e′ [ x ← e″ ] ]) ∎
fusion (case e bs) =
cong₂ case (fusion e) (fusion-B⋆ bs)
fusion {x = x} {e′ = e′} {e″ = e″} (rec y e) with x V.≟ y
… | yes _ = refl
… | no _ =
rec y (e [ x ← e′ ] [ x ← e″ ]) ≡⟨ cong (rec _) $ fusion e ⟩∎
rec y (e [ x ← e′ [ x ← e″ ] ]) ∎
fusion {x = x} {e″ = e″} (var y) with x V.≟ y
… | yes _ = refl
… | no x≢y =
var y [ x ← e″ ] ≡⟨ var-step-≢ x≢y ⟩∎
var y ∎
fusion (const c es) =
cong (const c) (fusion-⋆ es)
fusion-B :
∀ b → b [ x ← e′ ]B [ x ← e″ ]B ≡ b [ x ← e′ [ x ← e″ ] ]B
fusion-B {x = x} {e′ = e′} {e″ = e″} (branch c xs e)
with V.member x xs
… | yes x∈xs =
branch c xs e [ x ← e″ ]B ≡⟨ branch-step-∈ x∈xs ⟩∎
branch c xs e ∎
… | no x∉xs =
branch c xs (e [ x ← e′ ]) [ x ← e″ ]B ≡⟨ branch-step-∉ x∉xs ⟩
branch c xs (e [ x ← e′ ] [ x ← e″ ]) ≡⟨ cong (branch _ _) $ fusion e ⟩∎
branch c xs (e [ x ← e′ [ x ← e″ ] ]) ∎
fusion-⋆ :
∀ es → es [ x ← e′ ]⋆ [ x ← e″ ]⋆ ≡ es [ x ← e′ [ x ← e″ ] ]⋆
fusion-⋆ [] = refl
fusion-⋆ (e ∷ es) = cong₂ _∷_ (fusion e) (fusion-⋆ es)
fusion-B⋆ :
∀ bs → bs [ x ← e′ ]B⋆ [ x ← e″ ]B⋆ ≡ bs [ x ← e′ [ x ← e″ ] ]B⋆
fusion-B⋆ [] = refl
fusion-B⋆ (b ∷ bs) = cong₂ _∷_ (fusion-B b) (fusion-B⋆ bs)
|
alloy4fun_models/trashltl/models/13/7FtSWiwrD6Xj4WDWA.als | Kaixi26/org.alloytools.alloy | 0 | 747 | open main
pred id7FtSWiwrD6Xj4WDWA_prop14 {
eventually some Protected & Trash => no Protected' & Trash'
}
pred __repair { id7FtSWiwrD6Xj4WDWA_prop14 }
check __repair { id7FtSWiwrD6Xj4WDWA_prop14 <=> prop14o } |
src/002/b.ads | xeenta/learning-ada | 0 | 26168 | <filename>src/002/b.ads
package B is
procedure Print_Modify;
end B;
|
Transynther/x86/_processed/AVXALIGN/_zr_/i7-7700_9_0xca_notsx.log_6271_1001.asm | ljhsiun2/medusa | 9 | 91530 | .global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r12
push %r14
push %r15
lea addresses_D_ht+0xa1a, %r15
sub %r14, %r14
and $0xffffffffffffffc0, %r15
movaps (%r15), %xmm1
vpextrq $0, %xmm1, %r10
add $57961, %r15
lea addresses_WC_ht+0x5d3e, %r12
nop
nop
nop
xor $4273, %r10
movl $0x61626364, (%r12)
nop
nop
inc %r12
pop %r15
pop %r14
pop %r12
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r11
push %r14
push %r15
push %rax
push %rbx
push %rcx
push %rsi
// Store
lea addresses_A+0x1209a, %rcx
nop
nop
add $13487, %r11
movw $0x5152, (%rcx)
nop
xor $58284, %rbx
// Store
lea addresses_UC+0xff02, %rax
nop
nop
nop
nop
xor %r14, %r14
mov $0x5152535455565758, %rsi
movq %rsi, (%rax)
nop
nop
nop
nop
lfence
// Store
lea addresses_normal+0xd0b2, %r14
nop
cmp %rsi, %rsi
movw $0x5152, (%r14)
inc %r14
// Store
lea addresses_RW+0x1b15a, %r15
and %rcx, %rcx
movl $0x51525354, (%r15)
inc %rax
// Store
lea addresses_WT+0xf89a, %rbx
inc %r14
mov $0x5152535455565758, %rcx
movq %rcx, (%rbx)
nop
nop
dec %rsi
// Store
lea addresses_normal+0x18b9a, %r14
clflush (%r14)
dec %r11
movl $0x51525354, (%r14)
nop
nop
nop
nop
nop
cmp %r15, %r15
// Store
lea addresses_RW+0xcc02, %rcx
nop
cmp $23529, %r11
mov $0x5152535455565758, %rbx
movq %rbx, %xmm3
movups %xmm3, (%rcx)
inc %r14
// Load
lea addresses_PSE+0x1649a, %rbx
nop
nop
nop
and %r14, %r14
mov (%rbx), %si
nop
nop
nop
nop
dec %rax
// Faulty Load
lea addresses_A+0x1449a, %rax
clflush (%rax)
nop
and %rbx, %rbx
mov (%rax), %rsi
lea oracles, %r14
and $0xff, %rsi
shlq $12, %rsi
mov (%r14,%rsi,1), %rsi
pop %rsi
pop %rcx
pop %rbx
pop %rax
pop %r15
pop %r14
pop %r11
ret
/*
<gen_faulty_load>
[REF]
{'src': {'NT': False, 'AVXalign': False, 'size': 32, 'congruent': 0, 'same': True, 'type': 'addresses_A'}, 'OP': 'LOAD'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 2, 'congruent': 8, 'same': False, 'type': 'addresses_A'}, 'OP': 'STOR'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 8, 'congruent': 3, 'same': False, 'type': 'addresses_UC'}, 'OP': 'STOR'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 2, 'congruent': 3, 'same': False, 'type': 'addresses_normal'}, 'OP': 'STOR'}
{'dst': {'NT': False, 'AVXalign': True, 'size': 4, 'congruent': 6, 'same': False, 'type': 'addresses_RW'}, 'OP': 'STOR'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 8, 'congruent': 10, 'same': False, 'type': 'addresses_WT'}, 'OP': 'STOR'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 4, 'congruent': 5, 'same': False, 'type': 'addresses_normal'}, 'OP': 'STOR'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 16, 'congruent': 0, 'same': False, 'type': 'addresses_RW'}, 'OP': 'STOR'}
{'src': {'NT': False, 'AVXalign': False, 'size': 2, 'congruent': 9, 'same': False, 'type': 'addresses_PSE'}, 'OP': 'LOAD'}
[Faulty Load]
{'src': {'NT': False, 'AVXalign': True, 'size': 8, 'congruent': 0, 'same': True, 'type': 'addresses_A'}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'src': {'NT': False, 'AVXalign': True, 'size': 16, 'congruent': 6, 'same': False, 'type': 'addresses_D_ht'}, 'OP': 'LOAD'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 4, 'congruent': 2, 'same': False, 'type': 'addresses_WC_ht'}, 'OP': 'STOR'}
{'00': 6271}
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*/
|
test/Fail/Issue721c.agda | shlevy/agda | 1,989 | 1660 | -- 2012-10-20 Andreas
module Issue721c where
data Bool : Set where
false true : Bool
record Foo (b : Bool) : Set where
field
_*_ : Bool → Bool → Bool
data _≡_ {A : Set} (x : A) : A → Set where
refl : x ≡ x
record ∃ {A : Set} (B : A → Set) : Set where
constructor pack
field fst : A
snd : B fst
dontExpandTooMuch : (F : Foo false) → ∃ λ t → t ≡ t
dontExpandTooMuch F = pack t t
where open Foo F
d = λ x → x * x
t = d (d (d (d true)))
-- t should not be expanded in the error message
|
programs/oeis/094/A094328.asm | jmorken/loda | 1 | 172425 | <gh_stars>1-10
; A094328: Iterate the map in A006369 starting at 4.
; 4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6
mod $0,5
mov $1,7
lpb $0
sub $1,$0
sub $0,1
mul $1,2
lpe
sub $1,4
div $1,3
add $1,3
|
src/keystore-repository-data.ads | thierr26/ada-keystore | 0 | 4263 | <filename>src/keystore-repository-data.ads
-----------------------------------------------------------------------
-- keystore-repository-data -- Data access and management for the keystore
-- Copyright (C) 2019 <NAME>
-- Written by <NAME> (<EMAIL>)
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-----------------------------------------------------------------------
with Ada.Streams;
with Util.Streams;
with Util.Encoders.AES;
with Keystore.IO;
with Keystore.Repository.Keys;
private package Keystore.Repository.Data is
-- Start offset of the data entry descriptor in the data block.
function Data_Entry_Offset (Index : in Natural) return IO.Block_Index is
(IO.BT_DATA_START + Stream_Element_Offset (Index * DATA_ENTRY_SIZE) - DATA_ENTRY_SIZE - 1);
-- Write the data in one or several blocks.
procedure Add_Data (Manager : in out Wallet_Repository;
Iterator : in out Keys.Data_Key_Iterator;
Content : in Ada.Streams.Stream_Element_Array;
Offset : in out Interfaces.Unsigned_64);
procedure Add_Data (Manager : in out Wallet_Repository;
Iterator : in out Keys.Data_Key_Iterator;
Content : in out Util.Streams.Input_Stream'Class;
Offset : in out Interfaces.Unsigned_64);
-- Update the data fragments.
procedure Update_Data (Manager : in out Wallet_Repository;
Iterator : in out Keys.Data_Key_Iterator;
Content : in Ada.Streams.Stream_Element_Array;
Last_Pos : out Ada.Streams.Stream_Element_Offset;
Offset : in out Interfaces.Unsigned_64);
procedure Update_Data (Manager : in out Wallet_Repository;
Iterator : in out Keys.Data_Key_Iterator;
Content : in out Util.Streams.Input_Stream'Class;
End_Of_Stream : out Boolean;
Offset : in out Interfaces.Unsigned_64);
-- Erase the data fragments starting at the key iterator current position.
procedure Delete_Data (Manager : in out Wallet_Repository;
Iterator : in out Keys.Data_Key_Iterator);
-- Get the data associated with the named entry.
procedure Get_Data (Manager : in out Wallet_Repository;
Iterator : in out Keys.Data_Key_Iterator;
Output : out Ada.Streams.Stream_Element_Array);
-- Get the data associated with the named entry and write it in the output stream.
procedure Get_Data (Manager : in out Wallet_Repository;
Iterator : in out Keys.Data_Key_Iterator;
Output : in out Util.Streams.Output_Stream'Class);
private
-- Find the data block to hold a new data entry that occupies the given space.
-- The first data block that has enough space is used otherwise a new block
-- is allocated and initialized.
procedure Allocate_Data_Block (Manager : in out Wallet_Repository;
Space : in IO.Block_Index;
Work : in Workers.Data_Work_Access);
end Keystore.Repository.Data;
|
test/Succeed/Issue447.agda | cruhland/agda | 1,989 | 12093 | <reponame>cruhland/agda<gh_stars>1000+
-- Abstract definitions can't be projection-like
module Issue447 where
postulate
I : Set
R : I → Set
module M (i : I) (r : R i) where
abstract
P : Set₂
P = Set₁
p : P
p = Set
|
programs/oeis/120/A120169.asm | jmorken/loda | 1 | 5551 | ; A120169: a(1)=12; a(n)=floor((49+sum(a(1) to a(n-1)))/4).
; 12,15,19,23,29,36,45,57,71,89,111,139,173,217,271,339,423,529,661,827,1033,1292,1615,2018,2523,3154,3942,4928,6160,7700,9625,12031,15039,18798,23498,29372,36715,45894,57368,71710,89637,112046,140058,175072,218840,273550,341938,427422,534278,667847,834809,1043511,1304389,1630486,2038108,2547635,3184544,3980680,4975850,6219812,7774765,9718456,12148070,15185088,18981360,23726700,29658375,37072969,46341211,57926514,72408142,90510178,113137722,141422153,176777691,220972114,276215142,345268928,431586160,539482700,674353375,842941718,1053677148,1317096435,1646370544,2057963180,2572453975,3215567468,4019459335,5024324169,6280405211,7850506514,9813133143,12266416428,15333020535,19166275669,23957844586,29947305733,37434132166,46792665208,58490831510,73113539387,91391924234,114239905292,142799881615,178499852019,223124815024,278906018780,348632523475,435790654344,544738317930,680922897412,851153621765,1063942027206,1329927534008,1662409417510,2078011771887,2597514714859,3246893393574,4058616741967,5073270927459,6341588659324,7926985824155,9908732280194,12385915350242,15482394187803,19352992734753,24191240918442,30239051148052,37798813935065,47248517418831,59060646773539,73825808466924,92282260583655,115352825729569,144191032161961,180238790202451,225298487753064,281623109691330,352028887114162,440036108892703,550045136115879,687556420144848,859445525181060,1074306906476325,1342883633095407,1678604541369258,2098255676711573,2622819595889466,3278524494861833,4098155618577291,5122694523221614,6403368154027017,8004210192533771
add $0,4
mov $2,2
mov $3,2
lpb $0
sub $0,$2
sub $0,1
mov $1,$3
add $1,2
sub $1,$2
div $1,4
add $3,9
trn $2,$3
add $3,$1
lpe
add $1,9
|
oeis/323/A323650.asm | neoneye/loda-programs | 11 | 18561 | ; A323650: Flower garden sequence (see Comments for precise definition).
; Submitted by <NAME>
; 0,1,3,7,15,19,27,39,63,67,75,87,111,123,147,183,255,259,267,279,303,315,339,375,447,459,483,519,591,627,699,807,1023,1027,1035,1047,1071,1083,1107,1143,1215,1227,1251,1287,1359,1395,1467,1575,1791,1803,1827,1863,1935,1971,2043,2151,2367,2403,2475
lpb $0
sub $0,1
mov $2,$0
max $2,0
seq $2,323651 ; Number of elements added at n-th stage to the toothpick structure of A323650.
add $1,$2
lpe
mov $0,$1
|
programs/oeis/010/A010170.asm | karttu/loda | 0 | 89741 | ; A010170: Continued fraction for sqrt(99).
; 9,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1,18,1
mov $1,9
lpb $0,1
mod $0,2
mul $1,2
lpe
gcd $1,$0
|
nasm assembly/assignment 5 -backup/qs3.asm | AI-Factor-y/NASM-library | 0 | 91852 | <filename>nasm assembly/assignment 5 -backup/qs3.asm
section .data
msg1 : db 'debug here --',10
l1 : equ $-msg1
msg2 : db 'Enter your string : '
l2 : equ $-msg2
msg3 : db 'The sorted string is : '
l3 : equ $-msg3
msg4 : db 'msg 4 here'
l4: equ $-msg4
msg5 : db 'msg 5 here',10
l5: equ $-msg5
space:db ' '
newline:db '',10
section .bss
num: resd 1
counter: resd 1
n: resd 10
string_matrix: resb 1000
section .text
global _start
_start:
mov eax, 4
mov ebx, 1
mov ecx, msg2
mov edx, l2
int 80h
mov ebx, string_matrix
call read_string_as_matrix
call sort_string_matrix ;; procedure to sort the string
mov eax, 4
mov ebx, 1
mov ecx, msg3
mov edx, l3
int 80h
mov ebx , string_matrix
call print_string_in_matrix
mov eax, 4
mov ebx, 1
mov ecx, newline
mov edx, 1
int 80h
exit:
mov eax,1
mov ebx,0
int 80h
; section for procedures
;----------------------------
sort_string_matrix:
;; usage
;-------
; string base address in ebx
section .bss
sort_i: resd 1
sort_j: resd 1
str_1_pos : resd 1
str_2_pos: resd 1
section .text
push rax ; push all
push rbx
push rcx
mov dword[sort_i],0
mov dword[sort_j],0
sort_mat_loop1:
mov eax, [sort_i]
inc eax
cmp eax, [no_of_words]
je exit_sort_mat_loop1
mov [sort_j],eax
sort_mat_loop2:
push rbx
push rcx
push rbx
mov ax, word[sort_i]
mov bx, word[row_size]
mul bx
mov word[str_1_pos],ax
mov ax, word[sort_j]
mul bx
mov word[str_2_pos],ax
pop rbx
mov ecx, ebx
add ecx, [str_2_pos]
add ebx, [str_1_pos]
call compare_strings
cmp word[compare_flag],1
jne skip_swapping
call swap_strings
skip_swapping:
pop rcx
pop rbx
inc dword[sort_j]
mov eax,[sort_j]
cmp eax,[no_of_words]
je exit_sort_mat_loop2
jmp sort_mat_loop2
exit_sort_mat_loop2:
inc dword[sort_i]
jmp sort_mat_loop1
exit_sort_mat_loop1:
pop rcx
pop rbx
pop rax ; pop all
ret
swap_strings:
;;usage :
;---------
;; string 1 in ebx and string 2 in ecx
section .bss
swap_temp_str: resb 50
s_temp_counter: resd 1
section .text
push rax
push rbx
push rcx
push rdx
mov dword[s_temp_counter],0
push rbx
swap_loop_create_temp: ; temp=s[i]
mov dl,byte[ebx]
push rbx
mov ebx, swap_temp_str
mov eax, [s_temp_counter]
mov byte[ebx+eax],dl
inc dword[s_temp_counter]
pop rbx
cmp dl,0
je exit_swap_loop_create_temp
inc ebx
jmp swap_loop_create_temp
exit_swap_loop_create_temp:
pop rbx
push rbx
push rcx
swap_loop_1:
mov dl,byte[ecx]
mov byte[ebx],dl
cmp dl,0
je exit_swap_loop_1
inc ebx
inc ecx
jmp swap_loop_1
exit_swap_loop_1:
pop rcx
pop rbx
mov ebx, swap_temp_str
swap_loop_2:
mov dl,byte[ebx]
mov byte[ecx],dl
cmp dl,0
je exit_swap_loop_2
inc ebx
inc ecx
jmp swap_loop_2
exit_swap_loop_2:
pop rdx
pop rcx
pop rbx
pop rax
ret
print_array_string:
;; usage
;-----------
; 1: base address of string to print is stored in ebx
section .bss
temp_print_str : resb 1
section .text
push rax
push rbx
push rcx
printing:
mov al, byte[ebx]
mov byte[temp_print_str], al
cmp byte[temp_print_str], 0 ;; checks if the character is NULL character
je end_printing
push rbx
mov eax, 4
mov ebx, 1
mov ecx, temp_print_str
mov edx, 1
int 80h
pop rbx
inc ebx
jmp printing
end_printing:
pop rcx
pop rbx
pop rax
ret
compare_strings:
;; usage
;-----------
; 1 : string 1 should be in ebx string 2 should be in ecx
; 2 : if string 1> string 2 : compare_flag=1
; 3 : if string 2> string 1 : compare_flag=2
; 4 : if string 1==string 2 : compare_flag=0
section .bss
counter_i : resd 1
compare_flag: resd 1
section .text
push rax
push rbx
push rcx
mov word[counter_i],0
mov dword[compare_flag],0
compare_str_loop:
mov eax,[counter_i]
mov al,byte[ebx+eax] ;; extraxt string1[i]
cmp al,0
je check_is_str_2_ended ;; if string1[i]==null then check if string 2 is ended too
;; if not ended then string 2 is greater than string_1
push rax
mov eax, [counter_i]
mov dl,byte[ecx+eax] ;; check string 2 is ended then string 1 is greater since string 1 is
;; not ended .. (if its ended control should not reach here)
pop rax
cmp dl,0 ;; compare the two characters
je str_1_greater
cmp al,dl
je continue_compare_str
cmp al,dl
ja str_1_greater
mov dword[compare_flag],2 ; string 2 is greater
jmp exit_compare_str_loop
str_1_greater:
mov dword[compare_flag],1 ; string 1 is greater
jmp exit_compare_str_loop
continue_compare_str:
inc dword[counter_i]
jmp compare_str_loop
check_is_str_2_ended:
push rax
mov eax, [counter_i] ;; check whether string2 is ended
mov dl,byte[ecx+eax] ;; if ended then strings are equal else string 2 is greater
pop rax
cmp dl,0
je exit_compare_str_loop
mov dword[compare_flag],2
exit_compare_str_loop:
pop rcx
pop rbx
pop rax
ret
read_string_as_matrix:
section .bss
row_size: resd 1
rs_i: resd 1
rs_j: resd 1
rs_pos: resd 1
rs_temp: resb 1
no_of_words: resd 1
section .text
push rax
push rbx
push rcx
push rdx
mov dword[row_size],50
mov dword[rs_i],0
mov dword[rs_j],0
mov dword[no_of_words],1
rs_loop_i:
mov dword[rs_j],0
rs_loop_j:
push rbx
mov eax, 3
mov ebx, 0
mov ecx, rs_temp
mov edx, 1
int 80h
pop rbx
cmp byte[rs_temp], 10 ;; check if the input is ’Enter’
je exit_rs_loop_i
cmp byte[rs_temp],' '
je exit_rs_loop_j
push rbx
mov ax,word[rs_i]
mov bx,word[row_size]
mul bx
add ax,word[rs_j]
mov word[rs_pos],ax
; call debugger
pop rbx
mov cl,byte[rs_temp]
mov eax, [rs_pos]
mov byte[ebx+eax], cl
inc dword[rs_j]
jmp rs_loop_j
exit_rs_loop_j:
push rbx
mov ax,word[rs_i]
mov bx,word[row_size]
mul bx
add ax,word[rs_j]
mov word[rs_pos],ax
pop rbx
mov eax, [rs_pos]
mov byte[ebx+eax], 0
inc dword[no_of_words] ;; finds the total no of words
inc dword[rs_i]
jmp rs_loop_i
exit_rs_loop_i:
push rbx
mov ax,word[rs_i]
mov bx,word[row_size]
mul bx
add ax,word[rs_j]
mov word[rs_pos],ax
pop rbx
mov eax, [rs_pos]
mov byte[ebx+eax], 0
pop rdx
pop rcx
pop rbx
pop rax
ret
print_string_in_matrix:
section .bss
ps_i: resd 1
ps_j: resd 1
ps_pos: resd 1
ps_temp: resb 1
section .text
push rax
push rbx
push rcx
push rdx
mov dword[ps_i],0
mov dword[ps_j],0
ps_loop_i:
mov ax, word[ps_i]
cmp ax, word[no_of_words]
je exit_ps_loop_i
mov dword[ps_j],0
ps_loop_j:
push rbx
mov ax, word[ps_i]
mov bx, word[row_size]
mul bx
add ax,word[ps_j]
mov word[ps_pos],ax
pop rbx
mov eax, [ps_pos]
mov al, byte[ebx+eax]
mov byte[ps_temp], al
cmp byte[ps_temp],0
je exit_ps_loop_j
push rbx
mov eax, 4
mov ebx, 1
mov ecx, ps_temp
mov edx, 1
int 80h
pop rbx
inc dword[ps_j]
jmp ps_loop_j
exit_ps_loop_j:
inc dword[ps_i]
call debugger
jmp ps_loop_i
exit_ps_loop_i:
pop rdx
pop rcx
pop rbx
pop rax
ret
debugger:
section .data
msg_debugger : db ' '
msg_debugger_l : equ $-msg_debugger
section .text
push rax
push rbx
push rcx
push rdx
; debug----
mov eax, 4
mov ebx, 1
mov ecx, msg_debugger
mov edx, msg_debugger_l
int 80h
;debug ---
pop rdx
pop rcx
pop rbx
pop rax
; action
ret
|
Language/Cloaca.g4 | rockobonaparte/cloaca | 3 | 1750 | <gh_stars>1-10
// Original inspiration: https://github.com/antlr/grammars-v4/blob/master/python3-cs/Python3.g4
grammar Cloaca;
tokens { INDENT, DEDENT }
@lexer::header{
using System.Linq;
using System.Text.RegularExpressions;
}
@lexer::members {
// A queue where extra tokens are pushed on (see the NEWLINE lexer rule).
private System.Collections.Generic.LinkedList<IToken> Tokens = new System.Collections.Generic.LinkedList<IToken>();
// The stack that keeps track of the indentation level.
private System.Collections.Generic.Stack<int> Indents = new System.Collections.Generic.Stack<int>();
// The amount of opened braces, brackets and parenthesis.
private int Opened = 0;
// The most recently produced token.
private IToken LastToken = null;
public override void Emit(IToken token)
{
base.Token = token;
Tokens.AddLast(token);
}
private CommonToken CommonToken(int type, string text)
{
int stop = CharIndex - 1;
int start = text.Length == 0 ? stop : stop - text.Length + 1;
return new CommonToken(this._tokenFactorySourcePair, type, DefaultTokenChannel, start, stop);
}
private IToken CreateDedent()
{
var dedent = CommonToken(CloacaParser.DEDENT, "");
dedent.Line = LastToken.Line;
return dedent;
}
public override IToken NextToken()
{
// Check if the end-of-file is ahead and there are still some DEDENTS expected.
if (_input.La(1) == Eof && Indents.Count != 0)
{
// Remove any trailing EOF tokens from our buffer.
for (var node = Tokens.First; node != null; )
{
var temp = node.Next;
if (node.Value.Type == Eof)
{
Tokens.Remove(node);
}
node = temp;
}
// First emit an extra line break that serves as the end of the statement.
this.Emit(CommonToken(CloacaParser.NEWLINE, "\n"));
// Now emit as much DEDENT tokens as needed.
while (Indents.Count != 0)
{
Emit(CreateDedent());
Indents.Pop();
}
// Put the EOF back on the token stream.
Emit(CommonToken(CloacaParser.Eof, "<EOF>"));
}
var next = base.NextToken();
if (next.Channel == DefaultTokenChannel)
{
// Keep track of the last token on the default channel.
LastToken = next;
}
if (Tokens.Count == 0)
{
return next;
}
else
{
var x = Tokens.First.Value;
Tokens.RemoveFirst();
return x;
}
}
// Calculates the indentation of the provided spaces, taking the
// following rules into account:
//
// "Tabs are replaced (from left to right) by one to eight spaces
// such that the total number of characters up to and including
// the replacement is a multiple of eight [...]"
//
// -- https://docs.python.org/3.1/reference/lexical_analysis.html#indentation
static int GetIndentationCount(string spaces)
{
int count = 0;
foreach (char ch in spaces.ToCharArray())
{
count += ch == '\t' ? 8 - (count % 8) : 1;
}
return count;
}
bool AtStartOfInput()
{
return Column == 0 && Line == 1;
}
}
single_input: NEWLINE | simple_stmt | compound_stmt NEWLINE;
file_input: (NEWLINE | stmt)* EOF;
eval_input: testlist NEWLINE* EOF;
decorator: '@' dotted_name ( '(' (arglist)? ')' )? NEWLINE;
decorators: decorator+;
decorated: decorators (classdef | funcdef | async_funcdef);
async_funcdef : ASYNC funcdef;
funcdef : 'def' NAME parameters ('->' test)? ':' suite;
parameters : '(' (typedargslist)? ')';
typedargslist : (tfpdef ('=' test)? (',' tfpdef ('=' test)?)* (',' ('*' (tfpdef)? (',' tfpdef ('=' test)?)* (',' ('**' tfpdef (',')?)?)?
| '**' tfpdef (',')?)?)?
| '*' (tfpdef)? (',' tfpdef ('=' test)?)* (',' ('**' tfpdef (',')?)?)?
| '**' tfpdef (',')?);
tfpdef: NAME (':' test)?;
varargslist: (vfpdef ('=' test)? (',' vfpdef ('=' test)?)* (',' (
'*' (vfpdef)? (',' vfpdef ('=' test)?)* (',' ('**' vfpdef (',')?)?)?
| '**' vfpdef (',')?)?)?
| '*' (vfpdef)? (',' vfpdef ('=' test)?)* (',' ('**' vfpdef (',')?)?)?
| '**' vfpdef (',')?
);
vfpdef: NAME;
stmt: simple_stmt | compound_stmt;
simple_stmt: small_stmt (';' small_stmt)* (';')? NEWLINE;
small_stmt: (expr_stmt | del_stmt | pass_stmt | flow_stmt |
import_stmt | global_stmt | nonlocal_stmt | assert_stmt);
expr_stmt: testlist_star_expr (annassign | augassign (yield_expr|testlist) |
('=' (yield_expr|testlist_star_expr))*);
annassign: ':' test ('=' test)?;
testlist_star_expr: (test|star_expr) (',' (test|star_expr))* (',')?;
augassign: ('+=' | '-=' | '*=' | '@=' | '/=' | '%=' | '&=' | '|=' | '^=' |
'<<=' | '>>=' | '**=' | '//=');
// For normal and annotated assignments, additional restrictions enforced by the interpreter
del_stmt: 'del' exprlist;
pass_stmt: 'pass';
flow_stmt: break_stmt | continue_stmt | return_stmt | raise_stmt | yield_stmt;
break_stmt: 'break';
continue_stmt: 'continue';
return_stmt: 'return' (testlist)?;
yield_stmt: yield_expr;
raise_stmt: 'raise' (test ('from' test)?)?;
import_stmt: import_name | import_from;
import_name: 'import' dotted_as_names;
// note below: the ('.' | '...') is necessary because '...' is tokenized as ELLIPSIS
import_from: ('from' (('.' | '...')* dotted_name | ('.' | '...')+)
'import' ('*' | '(' import_as_names ')' | import_as_names));
import_as_name: NAME ('as' NAME)?;
dotted_as_name: dotted_name ('as' NAME)?;
import_as_names: import_as_name (',' import_as_name)* (',')?;
dotted_as_names: dotted_as_name (',' dotted_as_name)*;
dotted_name: NAME ('.' NAME)*;
global_stmt: 'global' NAME (',' NAME)*;
nonlocal_stmt: 'nonlocal' NAME (',' NAME)*;
assert_stmt: 'assert' test (',' test)?;
compound_stmt: if_stmt | while_stmt | for_stmt | try_stmt | with_stmt | funcdef | classdef | decorated | async_stmt;
async_stmt: ASYNC (funcdef | with_stmt | for_stmt);
if_stmt: 'if' test ':' suite ('elif' test ':' suite)* ('else' ':' suite)?;
while_stmt: 'while' test ':' suite ('else' ':' suite)?;
for_stmt: 'for' exprlist 'in' testlist ':' suite ('else' ':' suite)?;
try_stmt: ('try' ':' suite
((except_clause ':' suite)+
('else' ':' suite)?
('finally' ':' suite)? |
'finally' ':' suite));
with_stmt: 'with' with_item (',' with_item)* ':' suite;
with_item: test ('as' expr)?;
// NB compile.c makes sure that the default except clause is last
except_clause: 'except' (test ('as' NAME)?)?;
suite: simple_stmt | NEWLINE INDENT stmt+ DEDENT;
test: or_test ('if' or_test 'else' test)? | lambdef;
test_nocond: or_test | lambdef_nocond;
lambdef: 'lambda' (varargslist)? ':' test;
lambdef_nocond: 'lambda' (varargslist)? ':' test_nocond;
or_test: and_test ('or' and_test)*;
and_test: not_test ('and' not_test)*;
not_test: 'not' not_test | comparison;
comparison: expr (comp_op expr)*;
// <> isn't actually a valid comparison operator in Python. It's here for the
// sake of a __future__ import described in PEP 401 (which really works :-)
//comp_op: '<'|'>'|'=='|'>='|'<='|'<>'|'!='|'in'|'not' 'in'|'is'|'is' 'not';
comp_op : op=(COMP_OP_LT | COMP_OP_GT | COMP_OP_EQ | COMP_OP_GTE | COMP_OP_LTE |
COMP_OP_LTGT | COMP_OP_NE | COMP_OP_IN | COMP_OP_NOT_IN | COMP_OP_IS |
COMP_OP_IS_NOT);
star_expr: '*' expr;
expr: xor_expr ('|' xor_expr)*;
xor_expr: and_expr ('^' and_expr)*;
and_expr: shift_expr ('&' shift_expr)*;
shift_expr: arith_expr (('<<'|'>>') arith_expr)*;
arith_expr: term (('+'|'-') term)*;
term: factor (('*'|'@'|'/'|'%'|'//') factor)*;
factor: ('+'|'-'|'~') factor | power;
power: atom_expr ('**' factor)?;
atom_expr: (AWAIT)? atom trailer*;
atom: '(' (yield_expr|testlist_comp)? ')' # AtomParens
| '[' (testlist_comp)? ']' # AtomSquareBrackets
| '{' (dictorsetmaker)? '}' # AtomCurlyBrackets
| WAIT # AtomWait
| NAME # AtomName
| NUMBER # AtomNumber
| STRING+ # AtomString
| '...' # AtomDots
| 'None' # AtomNoneType
| ('True' | 'False') # AtomBool
;
testlist_comp: (test|star_expr) ( comp_for | (',' (test|star_expr))* (',')? );
trailer: '(' (arglist)? ')' | '[' subscriptlist ']' | '.' NAME;
subscriptlist: subscript (',' subscript)* (',')?;
subscript: test | (test)? ':' (test)? (sliceop)?;
sliceop: ':' (test)?;
exprlist: (expr|star_expr) (',' (expr|star_expr))* (',')?;
testlist: test (',' test)* (',')?;
dictorsetmaker: ( ((test ':' test | '**' expr)
(comp_for | (',' (test ':' test | '**' expr))* (',')?)) |
((test | star_expr)
(comp_for | (',' (test | star_expr))* (',')?)) );
classdef: 'class' NAME ('(' (arglist)? ')')? ':' suite;
arglist: argument (',' argument)* (',')?;
//// The reason that keywords are test nodes instead of NAME is that using NAME
//// results in an ambiguity. ast.c makes sure it's a NAME.
//// "test '=' test" is really "keyword '=' test", but we have no such token.
//// These need to be in a single rule to avoid grammar that is ambiguous
//// to our LL(1) parser. Even though 'test' includes '*expr' in star_expr,
//// we explicitly match '*' here, too, to give it proper precedence.
//// Illegal combinations and orderings are blocked in ast.c:
//// multiple (test comp_for) arguments are blocked; keyword unpackings
//// that precede iterable unpackings are blocked; etc.
//argument: ( test (comp_for)? |
// test '=' test |
// '**' test |
// '*' test );
argument: ( test (comp_for)? |
test '=' test |
'**' test |
'*' test );
comp_iter: comp_for | comp_if;
comp_for: (ASYNC)? 'for' exprlist 'in' or_test (comp_iter)?;
comp_if: 'if' test_nocond (comp_iter)?;
// not used in grammar, but may appear in "node" passed from Parser to Compiler
encoding_decl: NAME;
yield_expr: 'yield' (yield_arg)?;
yield_arg: 'from' test | testlist;
/*
* Lexer Rules
*/
STRING
: STRING_LITERAL
// | BYTES_LITERAL
;
NUMBER
: INTEGER
| FLOAT_NUMBER
| IMAG_NUMBER
;
INTEGER
: DECIMAL_INTEGER
| OCT_INTEGER
| HEX_INTEGER
| BIN_INTEGER
;
// Reserved words
WAIT : 'wait' ;
COMP_OP_LT : '<' ;
COMP_OP_GT : '>' ;
COMP_OP_EQ : '==' ;
COMP_OP_GTE : '>=' ;
COMP_OP_LTE : '<=' ;
COMP_OP_LTGT : '<>' ;
COMP_OP_NE : '!=' ;
COMP_OP_IN : 'in' ;
COMP_OP_NOT_IN : 'not in';
COMP_OP_IS : 'is' ;
COMP_OP_IS_NOT : 'is not';
// General tokens
DEF : 'def';
MUL : '*' ;
DIV : '/' ;
MOD : '%';
IDIV : '//';
AT : '@';
ADD : '+' ;
SUB : '-' ;
ASSIGN : '=' ;
NAME : [a-zA-Z0-9_]+ ;
COLON : ':' ;
NEWLINE
: ( {AtStartOfInput()}? SPACES
| ( '\r'? '\n' | '\r' | '\f' ) SPACES?
)
{
var newLine = (new Regex("[^\r\n\f]+")).Replace(Text, "");
var spaces = (new Regex("[\r\n\f]+")).Replace(Text, "");
// Strip newlines inside open clauses except if we are near EOF. We keep NEWLINEs near EOF to
// satisfy the final newline needed by the single_put rule used by the REPL.
int next = _input.La(1);
int nextnext = _input.La(2);
if (Opened > 0 || (nextnext != -1 && (next == '\r' || next == '\n' || next == '\f' || next == '#')))
{
// If we're inside a list or on a blank line, ignore all indents,
// dedents and line breaks.
Skip();
}
else
{
Emit(CommonToken(NEWLINE, newLine));
int indent = GetIndentationCount(spaces);
int previous = Indents.Count == 0 ? 0 : Indents.Peek();
if (indent == previous)
{
// skip indents of the same size as the present indent-size
Skip();
}
else if (indent > previous) {
Indents.Push(indent);
Emit(CommonToken(CloacaParser.INDENT, spaces));
}
else {
// Possibly emit more than 1 DEDENT token.
while(Indents.Count != 0 && Indents.Peek() > indent)
{
this.Emit(CreateDedent());
Indents.Pop();
}
}
}
}
;
/// stringliteral ::= [stringprefix](shortstring | longstring)
/// stringprefix ::= "r" | "u" | "R" | "U" | "f" | "F"
/// | "fr" | "Fr" | "fR" | "FR" | "rf" | "rF" | "Rf" | "RF"
STRING_LITERAL
: ( [rR] | [uU] | [fF] | ( [fF] [rR] ) | ( [rR] [fF] ) )? ( SHORT_STRING | LONG_STRING )
;
/// decimalinteger ::= nonzerodigit digit* | "0"+
DECIMAL_INTEGER
: NON_ZERO_DIGIT DIGIT*
| '0'+
;
/// octinteger ::= "0" ("o" | "O") octdigit+
OCT_INTEGER
: '0' [oO] OCT_DIGIT+
;
/// hexinteger ::= "0" ("x" | "X") hexdigit+
HEX_INTEGER
: '0' [xX] HEX_DIGIT+
;
/// bininteger ::= "0" ("b" | "B") bindigit+
BIN_INTEGER
: '0' [bB] BIN_DIGIT+
;
/// floatnumber ::= pointfloat | exponentfloat
FLOAT_NUMBER
: POINT_FLOAT
| EXPONENT_FLOAT
;
/// imagnumber ::= (floatnumber | intpart) ("j" | "J")
IMAG_NUMBER
: ( FLOAT_NUMBER | INT_PART ) [jJ]
;
OPEN_PAREN : '(' {Opened++;};
CLOSE_PAREN : ')' {Opened--;};
OPEN_BRACK : '[' {Opened++;};
CLOSE_BRACK : ']' {Opened--;};
OPEN_BRACE : '{' {Opened++;};
CLOSE_BRACE : '}' {Opened--;};
SKIP_
: ( SPACES | COMMENT | LINE_JOINING ) -> skip
;
/// shortstring ::= "'" shortstringitem* "'" | '"' shortstringitem* '"'
/// shortstringitem ::= shortstringchar | stringescapeseq
/// shortstringchar ::= <any source character except "\" or newline or the quote>
fragment SHORT_STRING
: '\'' ( STRING_ESCAPE_SEQ | ~[\\\r\n\f'] )* '\''
| '"' ( STRING_ESCAPE_SEQ | ~[\\\r\n\f"] )* '"'
;
/// longstring ::= "'''" longstringitem* "'''" | '"""' longstringitem* '"""'
fragment LONG_STRING
: '\'\'\'' LONG_STRING_ITEM*? '\'\'\''
| '"""' LONG_STRING_ITEM*? '"""'
;
/// longstringitem ::= longstringchar | stringescapeseq
fragment LONG_STRING_ITEM
: LONG_STRING_CHAR
| STRING_ESCAPE_SEQ
;
/// longstringchar ::= <any source character except "\">
fragment LONG_STRING_CHAR
: ~'\\'
;
/// stringescapeseq ::= "\" <any source character>
fragment STRING_ESCAPE_SEQ
: '\\' .
| '\\' NEWLINE
;
/// nonzerodigit ::= "1"..."9"
fragment NON_ZERO_DIGIT
: [1-9]
;
/// digit ::= "0"..."9"
fragment DIGIT
: [0-9]
;
/// octdigit ::= "0"..."7"
fragment OCT_DIGIT
: [0-7]
;
/// hexdigit ::= digit | "a"..."f" | "A"..."F"
fragment HEX_DIGIT
: [0-9a-fA-F]
;
/// bindigit ::= "0" | "1"
fragment BIN_DIGIT
: [01]
;
/// pointfloat ::= [intpart] fraction | intpart "."
fragment POINT_FLOAT
: INT_PART? FRACTION
| INT_PART '.'
;
/// exponentfloat ::= (intpart | pointfloat) exponent
fragment EXPONENT_FLOAT
: ( INT_PART | POINT_FLOAT ) EXPONENT
;
/// intpart ::= digit+
fragment INT_PART
: DIGIT+
;
/// fraction ::= "." digit+
fragment FRACTION
: '.' DIGIT+
;
/// exponent ::= ("e" | "E") ["+" | "-"] digit+
fragment EXPONENT
: [eE] [+-]? DIGIT+
;
fragment SPACES
: [ \t]+
;
fragment COMMENT
: '#' ~[\r\n\f]*
;
fragment LINE_JOINING
: '\\' SPACES? ( '\r'? '\n' | '\r' | '\f')
;
|
Gathered CTF writeups/ptr-yudai-writeups/2019/TokyoWesterns_CTF_5th_2019/ebc/ebc.asm | mihaid-b/CyberSakura | 1 | 24274 | <reponame>mihaid-b/CyberSakura<filename>Gathered CTF writeups/ptr-yudai-writeups/2019/TokyoWesterns_CTF_5th_2019/ebc/ebc.asm
0x0000000004006000: 79 01 fc 0f MOVREL R1, 0x0ffc
0x0000000004006004: 20 91 MOVqw R1, @R1
0x0000000004006006: 72 91 85 21 MOVnw R1, @R1 (+5, +24)
0x000000000400600a: b5 08 10 00 PUSHn @R0 (+0, +16)
0x000000000400600e: 35 01 PUSHn R1
0x0000000004006010: 83 29 01 00 00 10 CALLEXa @R1 (+1, +0)
0x0000000004006016: 60 00 02 10 MOVqw R0, R0 (+2, +0)
0x000000000400601a: 04 00 RET
0x000000000400601c: 56 66 XOR R6, R6
0x000000000400601e: 20 63 MOVqw R3, R6
0x0000000004006020: 4a 64 NOT R4, R6
0x0000000004006022: 79 07 2a 10 MOVREL R7, 0x102a
0x0000000004006026: 6b 07 PUSH R7
0x0000000004006028: 60 81 18 00 MOVqw R1, @R0 (+0, +24)
0x000000000400602c: 02 0a JMP8 0x0a
0x000000000400602e: 56 66 XOR R6, R6
0x0000000004006030: 77 33 08 00 MOVIqw R3, 0x0008
0x0000000004006034: 0a 64 NOT R4, R6
0x0000000004006036: 79 07 fc 0f MOVREL R7, 0x0ffc
0x000000000400603a: 6b 07 PUSH R7
0x000000000400603c: 60 81 18 00 MOVqw R1, @R0 (+0, +24)
0x0000000004006040: 54 41 AND R1, R4
0x0000000004006042: 6b 01 PUSH R1
0x0000000004006044: cc 67 04 00 ADD R7, R6 (0x0004)
0x0000000004006048: 79 05 ca 0f MOVREL R5, 0x0fca
0x000000000400604c: 20 81 MOVqw R1, @R0
0x000000000400604e: 77 32 04 00 MOVIqw R2, 0x0004
0x0000000004006052: ce 32 f1 ff MUL R2, R3 (0xfff1)
0x0000000004006056: 4b 22 NEG R2, R2
0x0000000004006058: 58 21 SHR R1, R2
0x000000000400605a: 4c 11 ADD R1, R1
0x000000000400605c: 6b 05 PUSH R5
0x000000000400605e: 4c 15 ADD R5, R1
0x0000000004006060: 1e df MOVww @R7, @R5
0x0000000004006062: cc 67 02 00 ADD R7, R6 (0x0002)
0x0000000004006066: 6c 05 POP R5
0x0000000004006068: d8 64 04 00 SHR R4, R6 (0x0004)
0x000000000400606c: 54 48 AND @R0, R4
0x000000000400606e: cc 63 01 00 ADD R3, R6 (0x0001)
0x0000000004006072: 6f 03 10 00 CMPIgte R3, (0x0010)
0x0000000004006076: 82 ea JMP8cc 0xea
0x0000000004006078: 6c 01 POP R1
0x000000000400607a: 83 10 80 ff ff ff CALL R0 (0xffffff80)
0x0000000004006080: 6c 01 POP R1
0x0000000004006082: 04 00 RET
0x0000000004006084: 79 01 78 0f MOVREL R1, 0x0f78
0x0000000004006088: 20 91 MOVqw R1, @R1
0x000000000400608a: 72 91 63 10 MOVnw R1, @R1 (+3, +24)
0x000000000400608e: 77 32 00 00 MOVIqw R2, 0x0000
0x0000000004006092: 35 02 PUSHn R2
0x0000000004006094: 35 01 PUSHn R1
0x0000000004006096: 03 29 CALLEXa @R1
0x0000000004006098: 36 01 POPn R1
0x000000000400609a: 36 02 POPn R2
0x000000000400609c: 79 03 60 0f MOVREL R3, 0x0f60
0x00000000040060a0: 20 b3 MOVqw R3, @R3
0x00000000040060a2: 72 b3 89 21 MOVnw R3, @R3 (+9, +24)
0x00000000040060a6: 79 02 5e 0f MOVREL R2, 0x0f5e
0x00000000040060aa: 35 02 PUSHn R2
0x00000000040060ac: 60 11 02 10 MOVqw R1, R1 (+2, +0)
0x00000000040060b0: 35 01 PUSHn R1
0x00000000040060b2: 77 31 01 00 MOVIqw R1, 0x0001
0x00000000040060b6: 35 01 PUSHn R1
0x00000000040060b8: 83 2b 89 01 00 10 CALLEXa @R3 (+9, +24)
0x00000000040060be: 60 00 03 10 MOVqw R0, R0 (+3, +0)
0x00000000040060c2: 79 01 3a 0f MOVREL R1, 0x0f3a
0x00000000040060c6: 20 91 MOVqw R1, @R1
0x00000000040060c8: 72 91 63 10 MOVnw R1, @R1 (+3, +24)
0x00000000040060cc: 79 02 40 0f MOVREL R2, 0x0f40
0x00000000040060d0: 35 02 PUSHn R2
0x00000000040060d2: 35 01 PUSHn R1
0x00000000040060d4: 83 29 01 00 00 10 CALLEXa @R1 (+1, +0)
0x00000000040060da: 36 01 POPn R1
0x00000000040060dc: 36 02 POPn R2
0x00000000040060de: 04 00 RET
0x00000000040060e0: 77 33 00 00 MOVIqw R3, 0x0000
0x00000000040060e4: 77 34 20 00 MOVIqw R4, 0x0020
0x00000000040060e8: 6b 03 PUSH R3
0x00000000040060ea: 6b 04 PUSH R4
0x00000000040060ec: 83 10 92 ff ff ff CALL R0 (0xffffff92)
0x00000000040060f2: 6c 04 POP R4
0x00000000040060f4: 6c 03 POP R3
0x00000000040060f6: 79 01 18 0f MOVREL R1, 0x0f18
0x00000000040060fa: 6b 01 PUSH R1
0x00000000040060fc: 83 10 fe fe ff ff CALL R0 (0xfffffefe)
0x0000000004006102: 6c 01 POP R1
0x0000000004006104: 79 01 0a 0f MOVREL R1, 0x0f0a
0x0000000004006108: 79 02 76 0f MOVREL R2, 0x0f76
0x000000000400610c: 4c 32 ADD R2, R3
0x000000000400610e: 1d 9a MOVbw @R2, @R1
0x0000000004006110: 77 31 01 00 MOVIqw R1, 0x0001
0x0000000004006114: 4c 13 ADD R3, R1
0x0000000004006116: 45 43 CMPeq R3, R4
0x0000000004006118: 82 e7 JMP8cc 0xe7
0x000000000400611a: 04 00 RET
0x000000000400611c: 79 01 e0 0e MOVREL R1, 0x0ee0
0x0000000004006120: 72 89 41 10 MOVnw @R1, @R0 (+1, +16)
0x0000000004006124: 79 01 d8 0f MOVREL R1, 0x0fd8
0x0000000004006128: 6b 01 PUSH R1
0x000000000400612a: 83 10 d0 fe ff ff CALL R0 (0xfffffed0)
0x0000000004006130: 6c 01 POP R1
0x0000000004006132: 83 10 a8 ff ff ff CALL R0 (0xffffffa8)
0x0000000004006138: 79 01 be 0f MOVREL R1, 0x0fbe
0x000000000400613c: 6b 01 PUSH R1
0x000000000400613e: 83 10 bc fe ff ff CALL R0 (0xfffffebc)
0x0000000004006144: 6c 01 POP R1
0x0000000004006146: 79 02 ca 0f MOVREL R2, 0x0fca
0x000000000400614a: 79 03 06 02 MOVREL R3, 0x0206
0x000000000400614e: 79 04 ba 0f MOVREL R4, 0x0fba
0x0000000004006152: 20 c4 MOVqw R4, @R4
0x0000000004006154: 77 35 00 00 MOVIqw R5, 0x0000
0x0000000004006158: 79 06 1e 0f MOVREL R6, 0x0f1e
0x000000000400615c: 1f e6 MOVdw R6, @R6
0x000000000400615e: 1f a1 MOVdw R1, @R2
0x0000000004006160: 16 61 XOR R1, R6
0x0000000004006162: 1f 1b MOVdw @R3, R1
0x0000000004006164: 77 31 04 00 MOVIqw R1, 0x0004
0x0000000004006168: 4c 12 ADD R2, R1
0x000000000400616a: 4c 13 ADD R3, R1
0x000000000400616c: 4c 15 ADD R5, R1
0x000000000400616e: 45 54 CMPeq R4, R5
0x0000000004006170: 82 f6 JMP8cc 0xf6
0x0000000004006172: 79 01 0c 0f MOVREL R1, 0x0f0c
0x0000000004006176: 20 91 MOVqw R1, @R1
0x0000000004006178: 6b 01 PUSH R1
0x000000000400617a: 83 10 d4 01 00 00 CALL R0 (0x000001d4)
0x0000000004006180: 6c 01 POP R1
0x0000000004006182: 77 31 01 00 MOVIqw R1, 0x0001
0x0000000004006186: 45 71 CMPeq R1, R7
0x0000000004006188: 81 90 c4 01 00 00 JMPcc R0 (0x000001c4)
0x000000000400618e: 79 03 6e 0e MOVREL R3, 0x0e6e
0x0000000004006192: 20 b3 MOVqw R3, @R3
0x0000000004006194: 72 b3 89 21 MOVnw R3, @R3 (+9, +24)
0x0000000004006198: 79 01 de 0e MOVREL R1, 0x0ede
0x000000000400619c: 35 01 PUSHn R1
0x000000000400619e: 77 31 08 00 MOVIqw R1, 0x0008
0x00000000040061a2: 35 01 PUSHn R1
0x00000000040061a4: 79 01 da 0e MOVREL R1, 0x0eda
0x00000000040061a8: 35 01 PUSHn R1
0x00000000040061aa: 83 2b 28 18 00 20 CALLEXa @R3 (+40, +24)
0x00000000040061b0: 60 00 03 10 MOVqw R0, R0 (+3, +0)
0x00000000040061b4: 79 02 24 12 MOVREL R2, 0x1224
0x00000000040061b8: 79 03 98 01 MOVREL R3, 0x0198
0x00000000040061bc: 79 04 14 12 MOVREL R4, 0x1214
0x00000000040061c0: 20 c4 MOVqw R4, @R4
0x00000000040061c2: 77 35 00 00 MOVIqw R5, 0x0000
0x00000000040061c6: 79 06 b0 0e MOVREL R6, 0x0eb0
0x00000000040061ca: 1f e6 MOVdw R6, @R6
0x00000000040061cc: 1f a1 MOVdw R1, @R2
0x00000000040061ce: 16 61 XOR R1, R6
0x00000000040061d0: 1f 1b MOVdw @R3, R1
0x00000000040061d2: 77 31 04 00 MOVIqw R1, 0x0004
0x00000000040061d6: 4c 12 ADD R2, R1
0x00000000040061d8: 4c 13 ADD R3, R1
0x00000000040061da: 4c 15 ADD R5, R1
0x00000000040061dc: 45 54 CMPeq R4, R5
0x00000000040061de: 82 f6 JMP8cc 0xf6
0x00000000040061e0: 79 01 a6 0e MOVREL R1, 0x0ea6
0x00000000040061e4: 20 91 MOVqw R1, @R1
0x00000000040061e6: 6b 01 PUSH R1
0x00000000040061e8: 83 10 66 01 00 00 CALL R0 (0x00000166)
0x00000000040061ee: 6c 01 POP R1
0x00000000040061f0: 77 31 01 00 MOVIqw R1, 0x0001
0x00000000040061f4: 45 71 CMPeq R1, R7
0x00000000040061f6: 81 90 56 01 00 00 JMPcc R0 (0x00000156)
0x00000000040061fc: 79 03 00 0e MOVREL R3, 0x0e00
0x0000000004006200: 20 b3 MOVqw R3, @R3
0x0000000004006202: 72 b3 89 21 MOVnw R3, @R3 (+9, +24)
0x0000000004006206: 79 01 70 0e MOVREL R1, 0x0e70
0x000000000400620a: 35 01 PUSHn R1
0x000000000400620c: 77 31 08 00 MOVIqw R1, 0x0008
0x0000000004006210: 35 01 PUSHn R1
0x0000000004006212: 79 01 74 0e MOVREL R1, 0x0e74
0x0000000004006216: 35 01 PUSHn R1
0x0000000004006218: 83 2b 28 18 00 20 CALLEXa @R3 (+40, +24)
0x000000000400621e: 60 00 03 10 MOVqw R0, R0 (+3, +0)
0x0000000004006222: 79 02 1e 19 MOVREL R2, 0x191e
0x0000000004006226: 79 03 2a 01 MOVREL R3, 0x012a
0x000000000400622a: 79 04 0e 19 MOVREL R4, 0x190e
0x000000000400622e: 20 c4 MOVqw R4, @R4
0x0000000004006230: 77 35 00 00 MOVIqw R5, 0x0000
0x0000000004006234: 79 06 42 0e MOVREL R6, 0x0e42
0x0000000004006238: 1f e6 MOVdw R6, @R6
0x000000000400623a: 1f a1 MOVdw R1, @R2
0x000000000400623c: 16 61 XOR R1, R6
0x000000000400623e: 1f 1b MOVdw @R3, R1
0x0000000004006240: 77 31 04 00 MOVIqw R1, 0x0004
0x0000000004006244: 4c 12 ADD R2, R1
0x0000000004006246: 4c 13 ADD R3, R1
0x0000000004006248: 4c 15 ADD R5, R1
0x000000000400624a: 45 54 CMPeq R4, R5
0x000000000400624c: 82 f6 JMP8cc 0xf6
0x000000000400624e: 79 01 40 0e MOVREL R1, 0x0e40
0x0000000004006252: 20 91 MOVqw R1, @R1
0x0000000004006254: 6b 01 PUSH R1
0x0000000004006256: 83 10 f8 00 00 00 CALL R0 (0x000000f8)
0x000000000400625c: 6c 01 POP R1
0x000000000400625e: 77 31 01 00 MOVIqw R1, 0x0001
0x0000000004006262: 45 71 CMPeq R1, R7
0x0000000004006264: 82 76 JMP8cc 0x76
0x0000000004006266: 79 03 96 0d MOVREL R3, 0x0d96
0x000000000400626a: 20 b3 MOVqw R3, @R3
0x000000000400626c: 72 b3 89 21 MOVnw R3, @R3 (+9, +24)
0x0000000004006270: 79 01 06 0e MOVREL R1, 0x0e06
0x0000000004006274: 35 01 PUSHn R1
0x0000000004006276: 77 31 08 00 MOVIqw R1, 0x0008
0x000000000400627a: 35 01 PUSHn R1
0x000000000400627c: 79 01 12 0e MOVREL R1, 0x0e12
0x0000000004006280: 35 01 PUSHn R1
0x0000000004006282: 83 2b 28 18 00 20 CALLEXa @R3 (+40, +24)
0x0000000004006288: 60 00 03 10 MOVqw R0, R0 (+3, +0)
0x000000000400628c: 79 02 ec 20 MOVREL R2, 0x20ec
0x0000000004006290: 79 03 c0 00 MOVREL R3, 0x00c0
0x0000000004006294: 79 04 dc 20 MOVREL R4, 0x20dc
0x0000000004006298: 20 c4 MOVqw R4, @R4
0x000000000400629a: 77 35 00 00 MOVIqw R5, 0x0000
0x000000000400629e: 79 06 d8 0d MOVREL R6, 0x0dd8
0x00000000040062a2: 1f e6 MOVdw R6, @R6
0x00000000040062a4: 1f a1 MOVdw R1, @R2
0x00000000040062a6: 16 61 XOR R1, R6
0x00000000040062a8: 1f 1b MOVdw @R3, R1
0x00000000040062aa: 77 31 04 00 MOVIqw R1, 0x0004
0x00000000040062ae: 4c 12 ADD R2, R1
0x00000000040062b0: 4c 13 ADD R3, R1
0x00000000040062b2: 4c 15 ADD R5, R1
0x00000000040062b4: 45 54 CMPeq R4, R5
0x00000000040062b6: 82 f6 JMP8cc 0xf6
0x00000000040062b8: 79 03 44 0d MOVREL R3, 0x0d44
0x00000000040062bc: 20 b3 MOVqw R3, @R3
0x00000000040062be: 72 b3 89 21 MOVnw R3, @R3 (+9, +24)
0x00000000040062c2: 79 01 b4 0d MOVREL R1, 0x0db4
0x00000000040062c6: 35 01 PUSHn R1
0x00000000040062c8: 77 31 08 00 MOVIqw R1, 0x0008
0x00000000040062cc: 35 01 PUSHn R1
0x00000000040062ce: 79 01 c8 0d MOVREL R1, 0x0dc8
0x00000000040062d2: 35 01 PUSHn R1
0x00000000040062d4: 83 2b 28 18 00 20 CALLEXa @R3 (+40, +24)
0x00000000040062da: 60 00 03 10 MOVqw R0, R0 (+3, +0)
0x00000000040062de: 79 01 98 0d MOVREL R1, 0x0d98
0x00000000040062e2: 77 32 00 00 MOVIqw R2, 0x0000
0x00000000040062e6: 1f 92 MOVdw R2, @R1
0x00000000040062e8: 35 02 PUSHn R2
0x00000000040062ea: 79 01 ac 0d MOVREL R1, 0x0dac
0x00000000040062ee: 20 91 MOVqw R1, @R1
0x00000000040062f0: 6b 01 PUSH R1
0x00000000040062f2: 83 10 5c 00 00 00 CALL R0 (0x0000005c)
0x00000000040062f8: 60 00 02 10 MOVqw R0, R0 (+2, +0)
0x00000000040062fc: 77 31 01 00 MOVIqw R1, 0x0001
0x0000000004006300: 45 71 CMPeq R1, R7
0x0000000004006302: 82 27 JMP8cc 0x27
0x0000000004006304: 79 02 7a 0d MOVREL R2, 0x0d7a
0x0000000004006308: 79 03 96 0d MOVREL R3, 0x0d96
0x000000000400630c: 77 34 00 00 MOVIqw R4, 0x0000
0x0000000004006310: 77 35 20 00 MOVIqw R5, 0x0020
0x0000000004006314: 1d ab MOVbw @R3, @R2
0x0000000004006316: 77 31 01 00 MOVIqw R1, 0x0001
0x000000000400631a: 4c 12 ADD R2, R1
0x000000000400631c: 4c 14 ADD R4, R1
0x000000000400631e: 77 31 02 00 MOVIqw R1, 0x0002
0x0000000004006322: 4c 13 ADD R3, R1
0x0000000004006324: 45 54 CMPeq R4, R5
0x0000000004006326: 82 f6 JMP8cc 0xf6
0x0000000004006328: 79 01 be 0d MOVREL R1, 0x0dbe
0x000000000400632c: 6b 01 PUSH R1
0x000000000400632e: 83 10 cc fc ff ff CALL R0 (0xfffffccc)
0x0000000004006334: 6c 01 POP R1
0x0000000004006336: 79 01 68 0d MOVREL R1, 0x0d68
0x000000000400633a: 6b 01 PUSH R1
0x000000000400633c: 83 10 be fc ff ff CALL R0 (0xfffffcbe)
0x0000000004006342: 6c 01 POP R1
0x0000000004006344: 79 01 b0 0d MOVREL R1, 0x0db0
0x0000000004006348: 6b 01 PUSH R1
0x000000000400634a: 83 10 b0 fc ff ff CALL R0 (0xfffffcb0)
0x0000000004006350: 6c 01 POP R1
0x0000000004006352: 04 00 RET
|
day08/src/vm.ads | jwarwick/aoc_2020 | 3 | 1054 | <gh_stars>1-10
with Ada.Strings.Unbounded;
with Ada.Containers.Hashed_Maps;
use Ada.Containers;
package VM is
type Instruction_Index is new Natural;
type VM is private;
VM_Exception : exception;
function load_file(file : in String) return VM;
procedure reset(v : in out VM);
function acc(v : in VM) return Integer;
function pc(v : in VM) return Instruction_Index;
function eval(v : in out VM; max_steps : in Positive) return Boolean;
function step(v : in out VM) return Boolean;
function instructions(v : in VM) return Count_Type;
procedure print(v : in VM);
procedure swap_nop_jmp(idx : in Instruction_Index; v : in out VM);
private
type Op is (acc, jmp, nop, halt);
type Op_Record (Ins : Op := nop) is
record
Index : Instruction_Index;
case Ins is
when acc | jmp | nop =>
Arg : Integer;
when halt =>
null;
end case;
end record;
function instruction_index_hash(key : in Instruction_Index) return Hash_Type;
package Op_Hashed_Maps is new Ada.Containers.Hashed_Maps
(Key_Type => Instruction_Index,
Element_Type => Op_Record,
Hash => instruction_index_hash,
Equivalent_Keys => "=");
use Op_Hashed_Maps;
type VM is record
Source : Ada.Strings.Unbounded.Unbounded_String;
PC : Instruction_Index := 0;
Acc : Integer := 0;
Halted : Boolean := false;
Instructions : Op_Hashed_Maps.Map := Empty_Map;
end record;
end VM;
|
electrum/src/main/resources/models/book/appendixE/p300-hotel.als | haslab/Electrum | 29 | 1893 | module hotel
open util/ordering [Time] as timeOrder
sig Key, Time {}
sig Card {
fst, snd: Key
}
sig Room {
key: Key one->Time
}
one sig Desk {
issued: Key->Time,
prev: (Room->lone Key)->Time
}
sig Guest {
cards: Card->Time
}
pred init [t: Time] {
Desk.prev.t = key.t
no issued.t and no cards.t ------ bug! (see page 303)
}
pred checkin [t,t1: Time, r: Room, g: Guest] {
some c: Card {
c.fst = r.(Desk.prev.t)
c.snd not in Desk.issued.t
cards.t1 = cards.t + g->c ------------- bug! (see page 306)
Desk.issued.t1 = Desk.issued.t + c.snd
Desk.prev.t1 = Desk.prev.t ++ r->c.snd
}
key.t = key.t1
}
pred enter [t,t1: Time, r: Room, g: Guest] {
some c: g.cards.t |
let k = r.key.t {
c.snd = k and key.t1 = key.t
or c.fst = k and key.t1 = key.t ++ r->c.snd
}
issued.t = issued.t1 and (Desk<:prev).t = prev.t1
cards.t = cards.t1
}
fact Traces {
init [first]
all t: Time - last | some g: Guest, r: Room |
checkin [t, t.next, r, g] or enter[t, t.next, r, g]
}
assert NoIntruder {
no t1: Time, g: Guest, g1: Guest-g, r: Room |
let t2=t1.next, t3=t2.next, t4=t3.next {
enter [t1, t2, r, g]
enter [t2, t3, r, g1]
enter [t3, t4, r, g]
}
}
-- This check reveals a bug (similar to Fig E.3) in which the initial key was issued twice.
check NoIntruder for 3 but 6 Time, 1 Room, 2 Guest
|
test/src/test_scroll_window.ads | Fabien-Chouteau/Giza | 7 | 19614 | <reponame>Fabien-Chouteau/Giza
with Giza.Widget.Scrolling;
use Giza.Widget;
with Basic_Test_Window; use Basic_Test_Window;
package Test_Scroll_Window is
type Scroll_Window is new Test_Window with private;
type Scroll_Window_Ref is access all Scroll_Window;
overriding
procedure On_Init (This : in out Scroll_Window);
overriding
procedure On_Displayed (This : in out Scroll_Window);
overriding
procedure On_Hidden (This : in out Scroll_Window);
private
type Scroll_Window is new Test_Window with record
Scroll_Vert : Scrolling.Ref;
Scroll_Horizon : Scrolling.Ref;
Scroll_Both : Scrolling.Ref;
end record;
end Test_Scroll_Window;
|
src/Data/PropFormula/Theorems/Weakening.agda | jonaprieto/agda-prop | 13 | 15055 | ------------------------------------------------------------------------------
-- Agda-Prop Library.
-- Extension Theorems of the Syntax definitions.
------------------------------------------------------------------------------
open import Data.Nat using ( ℕ )
module Data.PropFormula.Theorems.Weakening ( n : ℕ ) where
------------------------------------------------------------------------------
open import Data.PropFormula.Syntax n
open import Data.PropFormula.Properties n using ( substΓ )
open import Data.List using ( List ; [] ; _∷_ ; _++_ ; [_] )
open import Relation.Binary.PropositionalEquality
using ( _≡_; refl; cong; trans; sym)
------------------------------------------------------------------------------
-- Theorem.
weaken-Δ₁
: ∀ {Γ} {φ}
→ (Δ : Ctxt)
→ Γ ⊢ φ
→ Γ ⨆ Δ ⊢ φ
-- Proof.
weaken-Δ₁ {[]} {φ} [] Γ⊢φ = Γ⊢φ
weaken-Δ₁ {x ∷ Γ} {φ} [] Γ⊢φ = substΓ (sym helper) Γ⊢φ
where
helper : ∀ {Γ} → Γ ⨆ [] ≡ Γ
helper {[]} = refl
helper {x ∷ Γ} rewrite helper {Γ = Γ} = refl
weaken-Δ₁ {Γ} {φ} (x ∷ []) Γ⊢φ = weaken x Γ⊢φ
weaken-Δ₁ {Γ} {φ} (x₁ ∷ Δ) Γ⊢φ =
substΓ
helper
(weaken-Δ₁ Δ
(weaken x₁ Γ⊢φ))
where
helper : ∀ {Γ Δ} {x} → (Γ , x ) ⨆ Δ ≡ Γ ⨆ (x ∷ Δ)
helper {[]} {Δ} = refl
helper {y ∷ Γ} {Δ} {x} rewrite helper {Γ = Γ} {Δ = Δ} {x = x} = refl
-------------------------------------------------------------------------- ∎
-- Theorem.
weaken-Δ₂
: ∀ {Γ} {φ}
→ (Δ : Ctxt)
→ Γ ⊢ φ
→ Δ ⨆ Γ ⊢ φ
-- Proof.
weaken-Δ₂ {_} [] Γ⊢φ = Γ⊢φ
weaken-Δ₂ {[]} (hyp ∷ []) Γ⊢φ = weaken₂ hyp Γ⊢φ
weaken-Δ₂ {_} (hyp ∷ []) Γ⊢φ = weaken₂ hyp Γ⊢φ
weaken-Δ₂ {_} (hyp ∷ hyps) Γ⊢φ = weaken₂ hyp (weaken-Δ₂ hyps Γ⊢φ)
-------------------------------------------------------------------------- ∎
|
oeis/248/A248216.asm | neoneye/loda-programs | 11 | 10601 | <reponame>neoneye/loda-programs<filename>oeis/248/A248216.asm<gh_stars>10-100
; A248216: a(n) = 6^n - 2^n.
; 0,4,32,208,1280,7744,46592,279808,1679360,10077184,60465152,362795008,2176778240,13060685824,78364147712,470184951808,2821109841920,16926659313664,101559956406272,609359739486208,3656158439014400,21936950638280704,131621703838072832,789730223045214208,4738381338304839680,28430288029896146944,170581728179511099392,1023490369077335031808,6140942214464547061760,36845653286788356112384,221073919720732284157952,1326443518324397999915008,7958661109946396589424640,47751966659678396716417024
mov $1,6
pow $1,$0
mov $2,2
pow $2,$0
sub $1,$2
mov $0,$1
|
src/main/fragment/mega45gs02-common/vdsz1=vdsz2_ror_1.asm | jbrandwood/kickc | 2 | 179712 | <reponame>jbrandwood/kickc
ldq {z2}
asrq
stq {z1} |
resources/sprites.asm | VincentFoulon80/vixx | 1 | 11673 | <filename>resources/sprites.asm
!ifndef is_main !eof
!set .sprite_addr = vram_sprites_base
!set .sprite_size = $20
bullet_packet_size = .sprite_size
bullet_packet_qty = $01
bullet_bank = vram_sprites_base_b
bullet_address = .sprite_addr
bullet_spid = <(bullet_address >> 5)
bullet_spid_size = vera_sprite_width_8px | vera_sprite_height_8px
bullet_spid_def = vera_sprite_mode_4bpp + (bullet_bank << 3) + (bullet_address >> 13)
bullet !byte $00,$00,$00,$00
!byte $00,$0A,$A0,$00
!byte $00,$A1,$1A,$00
!byte $0A,$11,$11,$A0
!byte $0A,$11,$11,$A0
!byte $00,$A1,$1A,$00
!byte $00,$0A,$A0,$00
!byte $00,$00,$00,$00
!set .sprite_addr = .sprite_addr + .sprite_size
bullet_panic_packet_size = .sprite_size
bullet_panic_packet_qty = $01
bullet_panic_bank = vram_sprites_base_b
bullet_panic_address = .sprite_addr
bullet_panic_spid = <(bullet_panic_address >> 5)
bullet_panic_spid_size = vera_sprite_width_8px | vera_sprite_height_8px
bullet_panic_spid_def = vera_sprite_mode_4bpp + (bullet_panic_bank << 3) + (bullet_panic_address >> 13)
bullet_panic !byte $0A,$00,$00,$A0
!byte $00,$00,$00,$00
!byte $A0,$00,$A0,$00
!byte $00,$00,$00,$00
!byte $00,$A0,$00,$00
!byte $00,$00,$00,$A0
!byte $A0,$00,$00,$00
!byte $00,$00,$A0,$00
!set .sprite_addr = .sprite_addr + .sprite_size
bullet_glitch1_packet_size = .sprite_size
bullet_glitch1_packet_qty = $01
bullet_glitch1_bank = vram_sprites_base_b
bullet_glitch1_address = .sprite_addr
bullet_glitch1_spid = <(bullet_glitch1_address >> 5)
bullet_glitch1_spid_size = vera_sprite_width_8px | vera_sprite_height_8px
bullet_glitch1_spid_def = vera_sprite_mode_4bpp + (bullet_glitch1_bank << 3) + (bullet_glitch1_address >> 13)
bullet_glitch1 !byte $00,$00,$00,$00
!byte $0A,$A0,$00,$00
!byte $00,$0A,$11,$A0
!byte $0A,$11,$11,$A0
!byte $A1,$11,$1A,$00
!byte $00,$A1,$1A,$00
!byte $00,$00,$00,$AA
!byte $00,$00,$00,$00
!set .sprite_addr = .sprite_addr + .sprite_size
bullet_glitch2_packet_size = .sprite_size
bullet_glitch2_packet_qty = $01
bullet_glitch2_bank = vram_sprites_base_b
bullet_glitch2_address = .sprite_addr
bullet_glitch2_spid = <(bullet_glitch2_address >> 5)
bullet_glitch2_spid_size = vera_sprite_width_8px | vera_sprite_height_8px
bullet_glitch2_spid_def = vera_sprite_mode_4bpp + (bullet_glitch2_bank << 3) + (bullet_glitch2_address >> 13)
bullet_glitch2 !byte $0A,$00,$00,$00
!byte $0A,$0A,$0A,$00
!byte $00,$01,$A1,$00
!byte $00,$01,$11,$00
!byte $00,$A1,$1A,$A0
!byte $00,$A1,$10,$A0
!byte $00,$1A,$10,$00
!byte $00,$A0,$A0,$00
!set .sprite_addr = .sprite_addr + .sprite_size
player_packet_size = .sprite_size
player_packet_qty = $01
player_bank = vram_sprites_base_b
player_address = .sprite_addr
player_spid = <(player_address >> 5)
player_spid_size = vera_sprite_width_8px | vera_sprite_height_8px
player_spid_def = vera_sprite_mode_4bpp + (player_bank << 3) + (player_address >> 13)
player !byte $00,$0D,$D0,$00
!byte $00,$0D,$D0,$00
!byte $D0,$0D,$D0,$0D
!byte $D0,$DD,$DD,$0D
!byte $D5,$DD,$DD,$5D
!byte $D5,$DD,$DD,$5D
!byte $D5,$DD,$DD,$5D
!byte $D0,$DD,$DD,$0D
!set .sprite_addr = .sprite_addr + .sprite_size
touched_player_packet_size = .sprite_size
touched_player_packet_qty = $01
touched_player_bank = vram_sprites_base_b
touched_player_address = .sprite_addr
touched_player_spid = <(touched_player_address >> 5)
touched_player_spid_size = vera_sprite_width_8px | vera_sprite_height_8px
touched_player_spid_def = vera_sprite_mode_4bpp + (touched_player_bank << 3) + (touched_player_address >> 13)
touched_player !byte $00,$0A,$A0,$00
!byte $00,$0A,$A0,$00
!byte $A0,$0A,$A0,$0A
!byte $A0,$AA,$AA,$0A
!byte $A2,$AA,$AA,$2A
!byte $A2,$AA,$AA,$2A
!byte $A2,$AA,$AA,$2A
!byte $A0,$AA,$AA,$0A
!set .sprite_addr = .sprite_addr + .sprite_size
virus1_packet_size = .sprite_size*4
virus1_packet_qty = $01
virus1_bank = vram_sprites_base_b
virus1_address = .sprite_addr
virus1_spid = <(virus1_address >> 5)
virus1_spid_size = vera_sprite_width_16px | vera_sprite_height_16px
virus1_spid_def = vera_sprite_mode_4bpp + (virus1_bank << 3) + (virus1_address >> 13)
virus1 !byte $22,$22,$22,$22,$22,$22,$20,$00
!byte $2A,$AA,$AA,$AA,$AA,$AA,$20,$00
!byte $2A,$22,$2A,$2A,$22,$2A,$20,$00
!byte $2A,$2A,$2A,$2A,$2A,$2A,$20,$00
!byte $2A,$2A,$2A,$2A,$2A,$2A,$20,$00
!byte $2A,$22,$2A,$2A,$22,$2A,$20,$00
!byte $2A,$AA,$AA,$AA,$AA,$AA,$20,$00
!byte $2A,$2A,$2A,$2A,$2A,$2A,$20,$00
!byte $2A,$2A,$2A,$2A,$2A,$2A,$20,$00
!byte $2A,$2A,$2A,$2A,$2A,$2A,$20,$00
!byte $2A,$2A,$2A,$2A,$2A,$2A,$20,$00
!byte $2A,$AA,$AA,$AA,$AA,$AA,$20,$00
!byte $22,$22,$22,$22,$22,$22,$20,$00
!byte $00,$00,$00,$00,$00,$00,$00,$00
!byte $00,$00,$00,$00,$00,$00,$00,$00
!byte $00,$00,$00,$00,$00,$00,$00,$00
!set .sprite_addr = .sprite_addr + .sprite_size*4
virus2_packet_size = .sprite_size*4
virus2_packet_qty = $01
virus2_bank = vram_sprites_base_b
virus2_address = .sprite_addr
virus2_spid = <(virus2_address >> 5)
virus2_spid_size = vera_sprite_width_16px | vera_sprite_height_16px
virus2_spid_def = vera_sprite_mode_4bpp + (virus2_bank << 3) + (virus2_address >> 13)
virus2 !byte $22,$22,$22,$22,$22,$22,$20,$00
!byte $2A,$AA,$AA,$AA,$AA,$A2,$00,$00
!byte $2A,$22,$2A,$2A,$22,$2A,$22,$00
!byte $2A,$2A,$2A,$2A,$2A,$2A,$20,$00
!byte $2A,$2A,$2A,$2A,$2A,$2A,$20,$00
!byte $2A,$22,$2A,$2A,$22,$2A,$20,$00
!byte $2A,$AA,$AA,$AA,$AA,$A2,$00,$00
!byte $2A,$2A,$2A,$2A,$2A,$2A,$20,$00
!byte $2A,$2A,$2A,$2A,$2A,$2A,$20,$00
!byte $2A,$2A,$2A,$2A,$2A,$22,$00,$00
!byte $2A,$2A,$2A,$2A,$2A,$2A,$20,$00
!byte $2A,$AA,$AA,$AA,$AA,$A2,$00,$00
!byte $22,$22,$22,$22,$22,$22,$00,$00
!byte $00,$00,$00,$00,$00,$00,$20,$00
!byte $00,$00,$00,$00,$00,$00,$00,$00
!byte $00,$00,$00,$00,$00,$00,$00,$00
!set .sprite_addr = .sprite_addr + .sprite_size*4
virus3_packet_size = .sprite_size*4
virus3_packet_qty = $01
virus3_bank = vram_sprites_base_b
virus3_address = .sprite_addr
virus3_spid = <(virus3_address >> 5)
virus3_spid_size = vera_sprite_width_16px | vera_sprite_height_16px
virus3_spid_def = vera_sprite_mode_4bpp + (virus3_bank << 3) + (virus3_address >> 13)
virus3 !byte $22,$22,$22,$22,$20,$02,$20,$00
!byte $2A,$AA,$AA,$AA,$A2,$02,$00,$00
!byte $2A,$22,$2A,$2A,$22,$00,$22,$00
!byte $2A,$2A,$2A,$2A,$2A,$22,$20,$00
!byte $2A,$2A,$2A,$2A,$22,$02,$20,$00
!byte $2A,$22,$2A,$2A,$22,$22,$20,$00
!byte $2A,$AA,$AA,$AA,$A2,$00,$00,$00
!byte $2A,$2A,$2A,$2A,$22,$02,$20,$00
!byte $2A,$2A,$2A,$2A,$22,$00,$20,$00
!byte $2A,$2A,$2A,$2A,$2A,$20,$00,$00
!byte $2A,$2A,$2A,$2A,$2A,$20,$20,$00
!byte $2A,$AA,$AA,$AA,$A2,$02,$00,$00
!byte $22,$22,$22,$22,$20,$02,$00,$00
!byte $00,$00,$00,$00,$00,$00,$20,$00
!byte $00,$00,$00,$00,$00,$00,$00,$00
!byte $00,$00,$00,$00,$00,$00,$00,$00
!set .sprite_addr = .sprite_addr + .sprite_size*4
virus4_packet_size = .sprite_size*4
virus4_packet_qty = $01
virus4_bank = vram_sprites_base_b
virus4_address = .sprite_addr
virus4_spid = <(virus4_address >> 5)
virus4_spid_size = vera_sprite_width_16px | vera_sprite_height_16px
virus4_spid_def = vera_sprite_mode_4bpp + (virus4_bank << 3) + (virus4_address >> 13)
virus4 !byte $22,$22,$22,$22,$20,$00,$00,$00
!byte $2A,$AA,$AA,$AA,$A2,$02,$00,$00
!byte $2A,$22,$2A,$22,$22,$00,$22,$00
!byte $2A,$2A,$2A,$20,$02,$02,$00,$00
!byte $2A,$2A,$2A,$20,$00,$00,$00,$00
!byte $2A,$22,$2A,$20,$02,$00,$20,$00
!byte $2A,$AA,$AA,$A2,$02,$00,$00,$00
!byte $2A,$2A,$2A,$2A,$22,$00,$20,$00
!byte $2A,$2A,$2A,$2A,$20,$02,$00,$00
!byte $2A,$2A,$2A,$2A,$20,$00,$00,$00
!byte $2A,$2A,$2A,$22,$00,$20,$00,$00
!byte $2A,$AA,$A2,$00,$00,$00,$00,$00
!byte $22,$22,$22,$22,$20,$00,$00,$00
!byte $00,$00,$00,$22,$00,$00,$20,$00
!byte $00,$00,$00,$00,$02,$00,$00,$00
!byte $00,$00,$00,$00,$00,$00,$00,$00
!set .sprite_addr = .sprite_addr + .sprite_size*4
virus5_packet_size = .sprite_size*4
virus5_packet_qty = $01
virus5_bank = vram_sprites_base_b
virus5_address = .sprite_addr
virus5_spid = <(virus5_address >> 5)
virus5_spid_size = vera_sprite_width_16px | vera_sprite_height_16px
virus5_spid_def = vera_sprite_mode_4bpp + (virus5_bank << 3) + (virus5_address >> 13)
virus5 !byte $22,$22,$22,$22,$00,$00,$00,$00
!byte $2A,$AA,$A2,$20,$02,$00,$00,$00
!byte $2A,$22,$20,$00,$00,$00,$00,$00
!byte $2A,$2A,$20,$20,$00,$00,$00,$00
!byte $2A,$2A,$22,$20,$00,$00,$00,$00
!byte $2A,$22,$2A,$20,$00,$00,$00,$00
!byte $2A,$AA,$AA,$22,$00,$00,$00,$00
!byte $2A,$2A,$2A,$2A,$22,$00,$00,$00
!byte $2A,$2A,$2A,$22,$20,$00,$00,$00
!byte $22,$2A,$22,$00,$00,$00,$00,$00
!byte $20,$02,$20,$00,$00,$20,$00,$00
!byte $00,$00,$02,$00,$00,$00,$00,$00
!byte $02,$22,$00,$02,$20,$00,$00,$00
!byte $00,$00,$00,$02,$00,$00,$20,$00
!byte $00,$20,$00,$00,$00,$00,$00,$00
!byte $00,$00,$00,$00,$00,$00,$00,$00
!set .sprite_addr = .sprite_addr + .sprite_size*4
virus6_packet_size = .sprite_size*4
virus6_packet_qty = $01
virus6_bank = vram_sprites_base_b
virus6_address = .sprite_addr
virus6_spid = <(virus6_address >> 5)
virus6_spid_size = vera_sprite_width_16px | vera_sprite_height_16px
virus6_spid_def = vera_sprite_mode_4bpp + (virus6_bank << 3) + (virus6_address >> 13)
virus6 !byte $02,$02,$22,$22,$00,$00,$00,$00
!byte $00,$00,$00,$20,$00,$00,$00,$00
!byte $20,$22,$20,$00,$00,$00,$00,$00
!byte $20,$02,$20,$20,$00,$00,$00,$00
!byte $22,$02,$22,$20,$00,$00,$00,$00
!byte $02,$00,$2A,$20,$00,$00,$00,$00
!byte $22,$00,$2A,$22,$00,$00,$00,$00
!byte $00,$22,$2A,$2A,$22,$00,$00,$00
!byte $00,$02,$2A,$22,$20,$00,$00,$00
!byte $20,$02,$22,$00,$00,$00,$00,$00
!byte $20,$02,$20,$00,$00,$00,$00,$00
!byte $00,$00,$02,$00,$00,$00,$00,$00
!byte $02,$22,$00,$02,$20,$00,$00,$00
!byte $00,$00,$00,$02,$00,$00,$00,$00
!byte $00,$00,$00,$00,$00,$00,$00,$00
!byte $00,$00,$00,$00,$00,$00,$00,$00
!set .sprite_addr = .sprite_addr + .sprite_size*4 |
alloy4fun_models/trashltl/models/5/oZyiRx7Jrt8DPN366.als | Kaixi26/org.alloytools.alloy | 0 | 1061 | <filename>alloy4fun_models/trashltl/models/5/oZyiRx7Jrt8DPN366.als
open main
pred idoZyiRx7Jrt8DPN366_prop6 {
some f:File | f in Trash releases always f in Trash
}
pred __repair { idoZyiRx7Jrt8DPN366_prop6 }
check __repair { idoZyiRx7Jrt8DPN366_prop6 <=> prop6o } |
array_sort.asm | mohammadekhosravi/assembly | 2 | 91535 | <reponame>mohammadekhosravi/assembly<gh_stars>1-10
; ------------ARRAY SORT---------------
; THIS PROGRAM GET SIZE OF ARRAY AND EACH ELEMENT OF ARRAY AND THEN SORT ARRAY AND PRINT IT OUT.
; WORK WITH BOTH SINGED AND UNSIGNDED NUMBERS.
.MODEL SMALL
.DATA
MSG1 DB "ENTER SIZE OF ARRAY: $"
MSG2 DB "SORTED ARRAY IS: (PRINTED VERTICALLY) $"
LINE DB "---------------------------------------------$"
ELEMENT_TO_PRINT DB "ELEMENT $" ; PRINT ELEMENT X.
ELEMENT_COUNTER DB 00H ; COUNT NUMBER OF ELEMENTS.
COLON DB " : $"
NEW_LINE DB 0DH,0AH, '$' ; NEW LINE CODE.
START_FIRST_NUMBER DW ? ; BECAUSE SI IN 16 BIT RIGISTER
START_SECOND_NUMBER DW 0002H ; BECAUSE SI IN 16 BIT RIGISTER
SIZE DB ? ; SIZE OF INPUT ARRAY
DONT_PUSH DW ?
INPUT LABEL BYTE ; EACH ONE OF USER INPUT COME HERE. MAXIMUM 50 DIGIT NUMBER.
MAX DB 50
LEN DB ?
BUFFER DB 50 DUP('?')
RESULT LABEL BYTE ; THE INFAMOUS ARRAY ITSELF.
MAX1 DB 200
LEN1 DB ?
BUFFER1 DB 200 DUP('?')
FIRST_NUMBER LABEL BYTE ; FIRST SELECTED NUMBER FROM ARRAY.
MAX2 DB 1
LEN2 DB 00H
BUFFER2 DB 200 DUP('?')
SECOND_NUMBER LABEL BYTE ; SECOND SELECTED NUMBER FROM ARRAY.
MAX3 DB 1
LEN3 DB 00H
BUFFER3 DB 200 DUP('?')
TEMP LABEL BYTE ; TEMPORARY NUMBER FOR SWAPPING.
MAX4 DB 1
LEN4 DB 00H
BUFFER4 DB 200 DUP('?')
.CODE
MAIN PROC
MOV AX, @DATA ; INITIALIZATION OF DATA SEGMENT.
MOV DS, AX
; ------------------NUMBER OF ROWS------------------
LEA DX, MSG1 ; PRINT MSG1 TO STANDARD OUTPUT.
MOV AH, 9
INT 21H
MOV AH, 1 ; READ THE NMBER OF ROWS.
INT 21H
SUB AL, 30H ; CONVERT ASCII TO DECIMAL.
MOV SIZE, AL ; STORE NOR VALUE.
; --------NEW LINE----------------------------------
LEA DX, NEW_LINE
MOV AH, 9
INT 21H
; -------GET ARRAY'S ELEMENT FROM INPUT-------------
CALL GET_INPUT
; ------------SORT ARRAY----------------------------
CALL SORT_ARRAY
; ---------PRINT ARRAY------------------------------
CALL PRINT_ARRAY
; ----------RETURN CONTROL TO OPERATING SYSTEM------
MOV AX, 4C00H
INT 21H
MAIN ENDP
SORT_ARRAY PROC
; WE USE NON-OPTIMIZED BUBBLE SORT HERE.
SORT_ARRAY_OUTER_LOOP:
DEC SIZE
CALL INNER_LOOP
CMP SIZE, 0
JE GO_BACK
JMP SORT_ARRAY_OUTER_LOOP
GO_BACK:
RET
SORT_ARRAY ENDP
INNER_LOOP PROC
XOR CX, CX
MOV CL, LEN1
MOV LEN2, 00H
MOV START_SECOND_NUMBER, 2 ; SO SI=2 BECAUSE AFTER EACH OUTER LOOP WE NEED TO START FROM FIRST ARRAY'S ELEMENT.
SORT_ARRAY_INNER_LOOP:
SUB CL, LEN2 ; HOW MUCH DIGIT YOU PROCEED.
MOV SI, START_SECOND_NUMBER ; AFTER CMP ARRAY[I], ARRAY[I + 1] WE WANT TO CMP ARRAY[I + 1], ARRAY[I + 2]
CALL SORT_UTIL
LOOP SORT_ARRAY_INNER_LOOP
RET
INNER_LOOP ENDP
SORT_UTIL PROC
; GIVEN <I> COMPARE AND SWAP ARRAY[I], ARRAY[I + 1] IF NEEDED.
PUSH CX
MOV LEN2, 00H
MOV LEN3, 00H
MOV LEN4, 00H
; CLEAR BUFFERS
CLEAR_BUFFER2:
MOV DI, 2
CLEAR_BUFFER2_LOOP:
MOV BL, FIRST_NUMBER[DI]
CMP BL, 3FH
JE CLEAR_BUFFER3
MOV FIRST_NUMBER[DI], 3FH
INC DI
JMP CLEAR_BUFFER2_LOOP
CLEAR_BUFFER3:
MOV DI, 2
CLEAR_BUFFER3_LOOP:
MOV BL, SECOND_NUMBER[DI]
CMP BL, 3FH
JE CLEAR_BUFFER4
MOV SECOND_NUMBER[DI], 3FH
INC DI
JMP CLEAR_BUFFER3_LOOP
CLEAR_BUFFER4:
MOV DI, 2
CLEAR_BUFFER4_LOOP:
MOV BL, TEMP[DI]
CMP BL, 3FH
JE SET_DI_FN
MOV TEMP[DI], 3FH
INC DI
JMP CLEAR_BUFFER4_LOOP
SET_DI_FN:
MOV START_FIRST_NUMBER, SI ; STORE ADDRESS OF FIRST NUMBER FOR SWAPPING.
MOV DI, 2
JMP FN
FN:
MOV BL, RESULT[SI]
INC SI
CMP BL, 0DH ; COMPARE WITH CARRIGE RETURN
JE SET_DI_SN
MOV FIRST_NUMBER[DI], BL
INC LEN2
INC DI
JMP FN
SET_DI_SN:
MOV START_SECOND_NUMBER, SI ; STORE ADDRESS OF SECOND NUMBER FOR SWAPPING.
MOV DI, 2
JMP SN
SN:
MOV BL, RESULT[SI + 1]
CMP BL, 3FH
JE END_ARRAY ; CHANGE VALUE OF CL TO 1 BECAUSE WE REACH TO END OF ARRAY.
MOV BL, RESULT[SI]
INC SI
CMP BL, 0DH ; COMPARE WITH CARRIGE RETURN
JE COMPARE
;CMP BL, 3FH ; END OF ARRAY
;JE CONTINUE
MOV SECOND_NUMBER[DI], BL
INC LEN3
INC DI
JMP SN
;END_ARRAY:
; MOV CL, 1
; JMP COMPARE
END_ARRAY:
POP CX
MOV CX, 1 ; WE REACH THE END OF ARRAY SO WE NEED TO EXIT FROM OUTER LOOP.
PUSH CX
JMP COMPARE
COMPARE:
MOV DI, 2
MOV AL, FIRST_NUMBER[DI]
CMP AL, 2DH
JE AVVALI_MANFI
JMP AVVALI_MOSBAT
AVVALI_MANFI:
MOV AL, SECOND_NUMBER[DI]
CMP AL, 2DH
JE DOVVOMI_HAM_MANFI
JMP AVVALI_MANFI_DOVVOMI_MOSBAT
DOVVOMI_HAM_MANFI:
MOV AL, LEN2
CMP AL, LEN3
JB SWAP
JA CONTINUE
MOV DONT_PUSH, CX
;PUSH CX
MOV CL, LEN2
DEC CL
COMPARE_HARDO_MANFI_LOOP:
INC DI
MOV AL, FIRST_NUMBER[DI]
CMP AL, SECOND_NUMBER[DI]
JB SWAP
JA CONTINUE
LOOP COMPARE_HARDO_MANFI_LOOP
;POP CX
MOV CX, DONT_PUSH
JMP CONTINUE
AVVALI_MANFI_DOVVOMI_MOSBAT:
MOV CX, DONT_PUSH
;POP CX
JMP CONTINUE
AVVALI_MOSBAT:
MOV AL, SECOND_NUMBER[DI]
CMP AL, 2DH
JE AVVALI_MOSBAT_DOVVOMI_MANFI
JMP AVVALI_MOSBAT_DOVVOMI_MOSBAT
AVVALI_MOSBAT_DOVVOMI_MANFI:
JMP SWAP
AVVALI_MOSBAT_DOVVOMI_MOSBAT:
MOV AL, LEN2
CMP AL, LEN3 ; FIRST COMPARE LENGTH OF NUMBERS.
JA SWAP ; IF FIRST NUMBER IS BIGGER GO SWAP THEM.
JB CONTINUE ; IF SECOND NUMBER IS BIGGER DON'T DO ANY SWAPPING.
MOV DI, 2
;PUSH CX
MOV DONT_PUSH, CX
MOV CL, LEN2
COMPARE_LOOP: ; THEN COMPARE EACH DIGIT ON NUMBERS.
MOV AL, FIRST_NUMBER[DI]
CMP AL, SECOND_NUMBER[DI]
JA SWAP ; IF FIRST NUMBER IS BIGGER GO SWAP THEM.
JB CONTINUE ; IF SECOND NUMBER IS BIGGER DON'T DO ANY SWAPPING.
INC DI
LOOP COMPARE_LOOP
MOV CX, DONT_PUSH
;POP CX
JMP CONTINUE
SWAP:
; WE DO SWAPPING LIKE IN C.
; AND BECAUSE WE USE BUBLE SORT WE JUST SWAP TWO ADJACENT NUMBERS.
; FIRST_NUMBER -> TEMP
; SECOND_NUMBER -> FIRST_NUMBER
; TEMP -> SECOND_NUMBER
PUSH SI
;-------------FINRST_NUMBER -> TEMP ----------
MOV SI, 2
MOV DI, 2
MOV CL, LEN2
FIRST_TO_TEMP_LOOP:
MOV BL, FIRST_NUMBER[SI]
MOV TEMP[DI], BL
INC LEN4
INC SI
INC DI
LOOP FIRST_TO_TEMP_LOOP
;----------SECOND_NUMBER -> FIRST_NUMBER--------
MOV DI, START_FIRST_NUMBER
MOV SI, 2
MOV CL, LEN3
SECOND_TO_FIRST_LOOP:
MOV BL, SECOND_NUMBER[SI]
MOV RESULT[DI], BL ; REMEMBER THAT WE SWAP NUMBER INSIDE THE ARRAY ITSELF.
INC SI
INC DI
LOOP SECOND_TO_FIRST_LOOP
MOV RESULT[DI], 0DH
INC DI
;------------TEMP -> SECOND_NUMBER--------------
MOV START_SECOND_NUMBER, DI
;MOV DI, START_SECOND_NUMBER
MOV SI, 2
MOV CL, LEN4
TEMP_TO_SECOND_LOOP:
MOV BL, TEMP[SI]
MOV RESULT[DI], BL
INC SI
INC DI
LOOP TEMP_TO_SECOND_LOOP
MOV RESULT[DI], 0DH
POP SI
JMP CONTINUE
CONTINUE:
POP CX
RET
SORT_UTIL ENDP
GET_INPUT PROC
XOR CX, CX
MOV CL, SIZE ; SET COUNTER TO SIZE OF ARRAY
ROW:
; --------NEW LINE-----------
LEA DX, NEW_LINE
MOV AH, 9
INT 21H
; PRINT "ELENET X".
LEA DX, ELEMENT_TO_PRINT
MOV AH, 9
INT 21H
; PRINT THE X PART.
MOV BL, ELEMENT_COUNTER
ADD BL, 30H
MOV AH, 2
MOV DL, BL
INT 21H
INC ELEMENT_COUNTER
; PRINT " : "
LEA DX, COLON
MOV AH, 9
INT 21H
; GET INPUT FROM USER
LEA DX, INPUT
MOV AH, 0AH
INT 21H
CALL PUSH_NUMBER
;MOV [SI], AL
;ADD SI, 2 ; BECAUSE ARRAY IS WORD(2 BYTE).
LOOP ROW
; RESTORE REGISTERS VALUE FROM STACK.
RET
GET_INPUT ENDP
PUSH_NUMBER PROC
; SAVE REGISTERS VALUE IN STACK.
PUSH CX
XOR SI, SI
XOR DI, DI
XOR AX, AX
XOR CX, CX
MOV CL, LEN
INC CL
MOV DI, AX
ADD DI, 2
XOR AX, AX
MOV AL, LEN1
MOV SI, AX
ADD SI, 2
ADD LEN1, CL
DIGIT:
MOV AL, INPUT[DI]
MOV RESULT[SI], AL
INC DI
INC SI
LOOP DIGIT
; RESTORE REGISTERS VALUE FROM STACK.
POP CX
RET
PUSH_NUMBER ENDP
PRINT_ARRAY PROC
; SAVE REGISTERS VALUE IN STACK.
PUSH CX
LEA DX, NEW_LINE ; \N
MOV AH, 9
INT 21H
LEA DX, NEW_LINE ; \N
MOV AH, 9
INT 21H
LEA DX, LINE ; -------------------------------------------
MOV AH, 9
INT 21H
LEA DX, NEW_LINE ; \N
MOV AH, 9
INT 21H
LEA DX, NEW_LINE ; \N
MOV AH, 9
INT 21H
LEA DX, MSG2
MOV AH, 9
INT 21H
LEA DX, NEW_LINE ; \N
MOV AH, 9
INT 21H
MOV SI, 2 ; BECAUSE TWO FIRST ELEMENT OF ARRAY ARE NOT INPUT NUMBERS.
XOR CX, CX
MOV CL, LEN1
PRINT:
MOV BL, RESULT[SI]
INC SI
CMP BL, 0DH ; COMPARE WITH CARRIGE RETURN
JNE PRINT_NUM
LEA DX, NEW_LINE ; \N
MOV AH, 9
INT 21H
PRINT_NUM:
; ANOTHER WAY TO PRINT A CHARACTER
;MOV AH, 2
;MOV DL, BL
;INT 21H
MOV AL, BL
MOV AH, 0EH
INT 10H
LOOP PRINT
; RESTORE REGISTERS VALUE FROM STACK.
POP CX
RET
PRINT_ARRAY ENDP
END MAIN ; THE VERY LAST LINE |
hdes-dialect/hdes-ast/src/main/antlr4/imports/FlowParser.g4 | the-wrench-io/hdes-parent | 1 | 5898 | <gh_stars>1-10
parser grammar FlowParser;
options { tokenVocab = HdesLexer; }
import TypeDefParser, ExpressionParser;
flowUnit: simpleTypeName headers '{' steps '}';
steps: step*;
step: simpleTypeName '(' ')' '{' (iterateAction | callAction) stepAs? pointer '}';
stepAs: '.'? AS '(' mapping ')';
callAction: callDef*;
callDef: callAwait? simpleTypeName '(' mapping ')';
callAwait: AWAIT;
iterateAction: MAP '(' typeName ')' '.'? TO '(' '{' iterateBody '}' ')';
iterateBody: callAction | steps;
pointer: whenThenPointerArgs | thenPointer;
whenThenPointerArgs: (whenThenPointer (whenThenPointer)* elsePointer?) | thenPointer?;
whenThenPointer: IF '(' expressionUnit ')' thenPointer;
elsePointer: ELSE thenPointer;
thenPointer
: (RETURN (endAsPointer | simpleTypeName '(' ')'))
| continuePointer;
continuePointer: CONTINUE;
endAsPointer: mapping; |
Task/Array-concatenation/Ada/array-concatenation.ada | LaudateCorpus1/RosettaCodeData | 1 | 27420 | type T is array (Positive range <>) of Integer;
X : T := (1, 2, 3);
Y : T := X & (4, 5, 6); -- Concatenate X and (4, 5, 6)
|
Transynther/x86/_processed/AVXALIGN/_ht_st_zr_un_/i7-7700_9_0x48_notsx.log_331_462.asm | ljhsiun2/medusa | 9 | 86051 | <gh_stars>1-10
.global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r11
push %r12
push %r13
push %r9
push %rax
push %rcx
push %rdi
push %rsi
lea addresses_normal_ht+0xd16f, %r12
dec %r9
mov (%r12), %r13d
nop
nop
nop
and $38500, %r13
lea addresses_D_ht+0xc6ef, %r12
cmp $32596, %rdi
vmovups (%r12), %ymm6
vextracti128 $1, %ymm6, %xmm6
vpextrq $1, %xmm6, %r10
nop
xor %r13, %r13
lea addresses_WT_ht+0xb998, %r11
nop
nop
nop
nop
add %r12, %r12
mov $0x6162636465666768, %rdi
movq %rdi, %xmm5
movups %xmm5, (%r11)
cmp $31630, %r11
lea addresses_D_ht+0x706f, %rdi
nop
cmp $62320, %rax
movb $0x61, (%rdi)
nop
nop
nop
inc %r12
lea addresses_WT_ht+0xf76f, %rsi
lea addresses_A_ht+0x2aef, %rdi
clflush (%rsi)
clflush (%rdi)
nop
nop
nop
nop
cmp $23990, %r10
mov $112, %rcx
rep movsq
add $33786, %rax
lea addresses_UC_ht+0x1c96f, %rax
nop
nop
nop
sub $25427, %rsi
movb $0x61, (%rax)
nop
cmp %rcx, %rcx
lea addresses_normal_ht+0x117ef, %r12
nop
nop
nop
xor %r13, %r13
vmovups (%r12), %ymm4
vextracti128 $0, %ymm4, %xmm4
vpextrq $1, %xmm4, %rcx
nop
nop
nop
xor %r11, %r11
lea addresses_normal_ht+0x9c4f, %rcx
nop
nop
nop
nop
xor $50730, %rsi
movb $0x61, (%rcx)
nop
nop
nop
nop
sub %rax, %rax
lea addresses_WC_ht+0x1d14f, %rsi
cmp %r9, %r9
mov (%rsi), %r13
nop
nop
nop
add %r13, %r13
lea addresses_WT_ht+0x1b8ef, %r11
nop
nop
nop
nop
xor $32659, %rcx
movb (%r11), %r9b
nop
nop
nop
nop
add $56461, %rax
lea addresses_UC_ht+0x18aef, %rsi
lea addresses_WT_ht+0x446f, %rdi
clflush (%rsi)
nop
nop
nop
nop
nop
sub $62801, %rax
mov $38, %rcx
rep movsb
inc %r10
lea addresses_WC_ht+0x1927f, %r9
clflush (%r9)
cmp $33385, %r10
movw $0x6162, (%r9)
and %rdi, %rdi
lea addresses_normal_ht+0x1e7ef, %r10
nop
and $31682, %r11
movb $0x61, (%r10)
nop
nop
add %r11, %r11
pop %rsi
pop %rdi
pop %rcx
pop %rax
pop %r9
pop %r13
pop %r12
pop %r11
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r12
push %r13
push %r9
push %rbp
push %rcx
push %rdx
// Store
lea addresses_A+0x154ef, %r10
nop
nop
nop
inc %rdx
mov $0x5152535455565758, %r13
movq %r13, %xmm0
vmovaps %ymm0, (%r10)
nop
nop
xor %rdx, %rdx
// Store
lea addresses_WT+0xdcef, %r13
nop
sub $1797, %rbp
mov $0x5152535455565758, %r12
movq %r12, (%r13)
nop
nop
nop
sub $8422, %rdx
// Faulty Load
lea addresses_WT+0xdcef, %r12
nop
nop
nop
xor %rcx, %rcx
vmovntdqa (%r12), %ymm0
vextracti128 $0, %ymm0, %xmm0
vpextrq $1, %xmm0, %rbp
lea oracles, %rcx
and $0xff, %rbp
shlq $12, %rbp
mov (%rcx,%rbp,1), %rbp
pop %rdx
pop %rcx
pop %rbp
pop %r9
pop %r13
pop %r12
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'same': False, 'NT': False, 'AVXalign': False, 'size': 8, 'type': 'addresses_WT', 'congruent': 0}}
{'dst': {'same': False, 'NT': False, 'AVXalign': True, 'size': 32, 'type': 'addresses_A', 'congruent': 11}, 'OP': 'STOR'}
{'dst': {'same': True, 'NT': False, 'AVXalign': False, 'size': 8, 'type': 'addresses_WT', 'congruent': 0}, 'OP': 'STOR'}
[Faulty Load]
{'OP': 'LOAD', 'src': {'same': True, 'NT': True, 'AVXalign': False, 'size': 32, 'type': 'addresses_WT', 'congruent': 0}}
<gen_prepare_buffer>
{'OP': 'LOAD', 'src': {'same': False, 'NT': False, 'AVXalign': False, 'size': 4, 'type': 'addresses_normal_ht', 'congruent': 6}}
{'OP': 'LOAD', 'src': {'same': False, 'NT': False, 'AVXalign': False, 'size': 32, 'type': 'addresses_D_ht', 'congruent': 8}}
{'dst': {'same': False, 'NT': False, 'AVXalign': False, 'size': 16, 'type': 'addresses_WT_ht', 'congruent': 0}, 'OP': 'STOR'}
{'dst': {'same': False, 'NT': False, 'AVXalign': False, 'size': 1, 'type': 'addresses_D_ht', 'congruent': 7}, 'OP': 'STOR'}
{'dst': {'same': False, 'congruent': 8, 'type': 'addresses_A_ht'}, 'OP': 'REPM', 'src': {'same': False, 'congruent': 7, 'type': 'addresses_WT_ht'}}
{'dst': {'same': False, 'NT': False, 'AVXalign': False, 'size': 1, 'type': 'addresses_UC_ht', 'congruent': 2}, 'OP': 'STOR'}
{'OP': 'LOAD', 'src': {'same': False, 'NT': False, 'AVXalign': False, 'size': 32, 'type': 'addresses_normal_ht', 'congruent': 7}}
{'dst': {'same': False, 'NT': False, 'AVXalign': False, 'size': 1, 'type': 'addresses_normal_ht', 'congruent': 5}, 'OP': 'STOR'}
{'OP': 'LOAD', 'src': {'same': False, 'NT': False, 'AVXalign': False, 'size': 8, 'type': 'addresses_WC_ht', 'congruent': 4}}
{'OP': 'LOAD', 'src': {'same': False, 'NT': True, 'AVXalign': True, 'size': 1, 'type': 'addresses_WT_ht', 'congruent': 10}}
{'dst': {'same': False, 'congruent': 7, 'type': 'addresses_WT_ht'}, 'OP': 'REPM', 'src': {'same': False, 'congruent': 6, 'type': 'addresses_UC_ht'}}
{'dst': {'same': False, 'NT': False, 'AVXalign': False, 'size': 2, 'type': 'addresses_WC_ht', 'congruent': 4}, 'OP': 'STOR'}
{'dst': {'same': False, 'NT': False, 'AVXalign': False, 'size': 1, 'type': 'addresses_normal_ht', 'congruent': 8}, 'OP': 'STOR'}
{'ff': 6, '46': 3, '49': 12, '00': 306, '6e': 1, '37': 1, '9f': 1, 'ad': 1}
00 00 00 00 00 00 00 ff 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 49 00 00 ff 00 00 00 00 49 00 00 49 ff 46 00 00 00 00 00 00 00 49 00 49 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 49 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 46 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff 00 ff 00 00 00 00 00 00 46 00 00 00 00 00 00 00 00 00 00 00 00 00 00 49 49 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 49 49 00 ff 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 37 00 00 00 00 49 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 49 00 00 00 00 00 00 00 ad 00 00 00 00 00 00 00 00 00 9f 00 00 00 00 00 00 00 00 00 6e 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*/
|
Task/Pascals-triangle/Ada/pascals-triangle-2.ada | LaudateCorpus1/RosettaCodeData | 1 | 30676 | <filename>Task/Pascals-triangle/Ada/pascals-triangle-2.ada
package body Pascal is
function First_Row(Max_Length: Positive) return Row is
R: Row(0 .. Max_Length) := (0 | 1 => 1, others => 0);
begin
return R;
end First_Row;
function Next_Row(R: Row) return Row is
S: Row(R'Range);
begin
S(0) := Length(R)+1;
S(Length(S)) := 1;
for J in reverse 2 .. Length(R) loop
S(J) := R(J)+R(J-1);
end loop;
S(1) := 1;
return S;
end Next_Row;
function Length(R: Row) return Positive is
begin
return R(0);
end Length;
end Pascal;
|
libsrc/video/tms9918/l_tms9918_disable_interrupts_nmi.asm | jpoikela/z88dk | 640 | 5800 | <reponame>jpoikela/z88dk
SECTION code_clib
PUBLIC l_tms9918_disable_interrupts
PUBLIC l_tms9918_enable_interrupts
PUBLIC __vdp_enable_status
INCLUDE "video/tms9918/vdp.inc"
l_tms9918_disable_interrupts:
ld a,128
ld (__vdp_enable_status),a
ret
l_tms9918_enable_interrupts:
xor a
ld (__vdp_enable_status),a
IF VDP_STATUS < 0
ld a,(-VDP_STATUS)
ELSE
ld a, VDP_STATUS / 256
in a,(VDP_STATUS % 256)
ENDIF
ret
SECTION bss_clib
__vdp_enable_status:
defb 0
|
examples/hello_world_request_reply2/src/primes-requester_main.adb | alexcamposruiz/dds-requestreply | 0 | 21514 |
with Ada.Command_Line;
with Ada.Text_IO; use Ada.Text_IO;
with DDS.DomainParticipant;
with DDS.DomainParticipantFactory;
with Primes.PrimeNumberRequester;
with Primes_IDL_File.PrimeNumberRequest_TypeSupport;
with RTIDDS.Config;
procedure Primes.Requester_Main is
use Primes_IDL_File;
use DDS.DomainParticipant;
use all type DDS.ReturnCode_T;
procedure Requester_Shutdown (Participant : in out DDS.DomainParticipant.Ref_Access;
Requester : in out PrimeNumberRequester.Ref_Access;
Request : in out PrimeNumberRequest_Access) is
begin
PrimeNumberRequest_TypeSupport.Delete_Data (Request);
PrimeNumberRequester.Delete (Requester);
if Participant /= null then
Participant.Delete_Contained_Entities;
end if;
--
DDS.DomainParticipantFactory.Get_Instance.Delete_Participant (Participant);
DDS.DomainParticipantFactory.Get_Instance.Finalize_Instance;
end;
procedure Requester_Main (N : DDS.long ;
Primes_Per_Reply : DDS.long ;
Domain_Id : DDS.DomainId_T)
is
Retcode : DDS.ReturnCode_T;
Replies : aliased PrimeNumberReply_Seq.Sequence;
Info_Seq : aliased DDS.SampleInfo_Seq.Sequence;
Participant : DDS.DomainParticipant.Ref_Access;
Requester : PrimeNumberRequester.Ref_Access;
Request : PrimeNumberRequest_Access := PrimeNumberRequest_TypeSupport.Create_Data;
MAX_WAIT : constant DDS.Duration_T := DDS.To_Duration_T (20.0);
In_Progress : Boolean := False;
use type PrimeNumberRequester.Ref_Access;
use PrimeNumberReply_Seq;
use DDS.SampleInfo_Seq;
begin
-- Create the participant
Participant := DDS.DomainParticipantFactory.Get_Instance.Create_Participant (Domain_Id);
if Participant = null then
Put_Line (Standard_Error, "create_participant error");
Ada.Command_Line.Set_Exit_Status (ADa.Command_Line.Failure);
return;
end if;
-- Create the requester with that participant, and a QoS profile
-- defined in USER_QOS_PROFILES.xml
--
Requester := PrimeNumberRequester.Create (Participant => Participant,
Service_Name => Service_Name,
Qos_Library_Name => Qos_Library_Name,
Qos_Profile_Name => Qos_Profile_Name);
if Requester = null then
Put_Line (Standard_Error, "create requester error");
Ada.Command_Line.Set_Exit_Status (Ada.Command_Line.Failure);
Requester_Shutdown (Participant, Requester, Request);
return;
end if;
Request := PrimeNumberRequest_TypeSupport.Create_Data;
if Request = null then
Put_Line (Standard_Error, "Create data error");
ADa.Command_Line.Set_Exit_Status (ADa.Command_Line.Failure);
Requester_Shutdown (Participant, Requester, Request);
return;
end if;
Request.N := N;
Request.Primes_Per_Reply := Primes_Per_Reply;
Retcode := Requester.Send_Request (Request.all);
if Retcode /= DDS.RETCODE_OK then
Put_Line (Standard_Error, "send_request error:" & Retcode'Img );
Ada.Command_Line.Set_Exit_Status (ADa.Command_Line.Failure);
Requester_Shutdown (Participant, Requester, Request);
return;
end if;
Retcode := Requester.Receive_Replies
(Replies => Replies'Unrestricted_Access,
Sample_Info => Info_Seq'Unrestricted_Access,
Min_Reply_Count => 1,
Max_Reply_Count => DDS.LENGTH_UNLIMITED,
Timeout => MAX_WAIT);
In_Progress := True;
while In_Progress and then (Retcode = DDS.RETCODE_OK)loop
Put_Line ("(");
for I in 1 .. Get_Length (Replies'Unrestricted_Access) loop
declare
Reply : constant PrimeNumberReply_Access := Get_Reference (Replies'Unrestricted_Access, I);
Info : constant DDS.SampleInfo_Access := Get_Reference (Info_Seq'Unrestricted_Access, I);
begin
if (Info.Valid_Data) then
for Prime_Number of Reply.Primes loop
Put (Prime_Number.all'Img);
end loop;
end if;
if Reply.Status /= REPLY_IN_PROGRESS then
In_Progress := False;
if Reply.Status = REPLY_ERROR then
Put_Line (Standard_Error, "Error in Replier");
elsif Reply.Status = REPLY_COMPLETED then
Put_Line ("DONE");
end if;
end if;
Put_Line (")");
end;
end loop;
-- Return the loan to the middleware
Requester.Return_Loan (Replies, Info_Seq);
if In_Progress then
Retcode := Requester.Receive_Replies
(Replies => Replies'Unrestricted_Access,
Sample_Info => Info_Seq'Unrestricted_Access,
Min_Reply_Count => 1,
Max_Reply_Count => DDS.LENGTH_UNLIMITED,
Timeout => MAX_WAIT);
end if;
end loop;
if Retcode /= DDS.RETCODE_OK then
if (Retcode = DDS.RETCODE_TIMEOUT) then
Put_Line (Standard_Error, "Timed out waiting for prime numbers");
else
Put_Line (Standard_Error, "Error receiving replies" & Retcode'Img);
end if;
end if;
Requester_Shutdown (Participant, Requester, Request);
end;
Domain_Id : DDS.DomainId_T := 0;
N : DDS.long;
Primes_Per_Reply : DDS.long := 5;
begin
if Ada.Command_Line.Argument_Count < 1 then
Put_Line ("PrimeNumberRequester:");
Put_Line ("Sends a request to calculate the prime numbers <= n");
Put_Line ("Parameters: <n> [<primes_per_reply> = 5] [<domain_id> = 0]");
Ada.Command_Line.Set_Exit_Status (Ada.Command_Line.Failure);
return;
end if;
N := DDS.Integer'Value (Ada.Command_Line.Argument (1));
if Ada.Command_Line.Argument_Count < 1 then
Primes_Per_Reply := DDS.Integer'Value (Ada.Command_Line.Argument (2));
end if;
if Ada.Command_Line.Argument_Count < 2 then
Domain_Id := DDS.DomainId_T'Value (Ada.Command_Line.Argument (3));
end if;
RTIDDS.Config.Logger.Get_Instance.Set_Verbosity (RTIDDS.Config.VERBOSITY_SILENT);
-- Uncomment this to turn on additional logging
-- RTIDDS.Config.Logger.Get_Instance.Set_Verbosity (RTIDDS.Config.VERBOSITY_WARNING);
Put_Line ("PrimeNumberRequester: Sending a request to calculate the ");
Put_Line ("prime numbers <= %d in sequences of %d or less elements " &
N'Img & Primes_Per_Reply'Img);
Put_Line ("(on domain %d)" & Domain_Id'Img);
Requester_Main (N, Primes_Per_Reply, Domain_Id);
end;
|
tests/mips1.asm | QuarticCat/qc-mips-cpu | 0 | 9790 | <gh_stars>0
.text
# This test does not include any hazards, jump, branch
# This test only aims to test the normal function of the cpu.
# To test wheter the cpu can do other instructions correctly.
addi $v0, $zero, 1
addi $v1, $zero, 2
addiu $a0, $zero, 20
addiu $a1, $zero, 16
addiu $a2, $zero, 4
add $a3, $v0, $v1 # 3 in $a3
addi $t0, $v0, -2 # -1 in $t0
sub $t1, $a1, $a0 # -4 in $t1 1111_...._1100
subu $t2, $a0, $a1 # 4 in $t2
slt $t3, $v1, $v0 # 0 in $t3
slt $t4, $v0, $v1 # 1 in $t4
sll $t5, $t0, 3 # 32'hfffffff8 in $t5
sllv $t6, $t0, $a2 #32'hfffffff0 in $t6
srl $t7, $t0, 3 # 32'h1fffffff in $t7
srlv $s1, $t0, $a2 # 32'h0fffffff in $t8
sra $s2, $t5, 2 # 32'hfffffffe in $s2
srav $s3, $t5, $v0 # 32'hfffffffc in $s3
and $s4, $t1, $t2 # 4 in $s4
andi $s5, $t1, 13 # 12 in $s5
or $s6, $t1, $v1 # -2 in $s6
ori $s7, $t1, 3 # -1 in $s7
nor $t8, $t1, $v1 # 1 in $t8
xor $t9, $t1, $v1 # -2 in $t9
xori $k0, $t1, -5 # 32'hffff0007 in $k0
addu $k1, $t0, $v0 # 0 in $k1
sw $v0, 0($zero) # 1 in DATA_MEM[0]
sw $v1, 4($zero) # 2 in DATA_MEM[1]
sw $a0, 8($zero) # 20 in DATA_MEM[2]
sw $a1, 12($zero) # 16 in DATA_MEM[3]
sw $a2, 16($zero) # 4 in DATA_MEM[4]
sw $a3, 20($zero) # 3 in DATA_MEM[5]
sw $t0, 24($zero) # -1 in DATA_MEM[6]
sw $t1, 28($zero) # -4 in DATA_MEM[7]
sw $t2, 32($zero) # 4 in DATA_MEM[8]
sw $t3, 36($zero) # 0 in DATA_MEM[9]
sw $t4, 40($zero) # 1 in DATA_MEM[10]
sw $t5, 44($zero) # 32'hfffffff8 in DATA_MEM[11]
sw $t6, 48($zero) # 32'hfffffff0 in DATA_MEM[12]
sw $t7, 52($zero) # 32'h1fffffff in DATA_MEM[13]
sw $s1, 56($zero) # 32'h0fffffff in DATA_MEM[14]
sw $s2, 60($zero) # 32'hfffffffe in DATA_MEM[15]
sw $s3, 64($zero) # 32'hfffffffc in DATA_MEM[16]
sw $s4, 68($zero) # 4 in DATA_MEM[17]
sw $s5, 72($zero) # 12 in DATA_MEM[18]
sw $s6, 76($zero) # -2 in DATA_MEM[19]
sw $s7, 80($zero) # -1 in DATA_MEM[20]
sw $t8, 84($zero) # 1 in DATA_MEM[21]
sw $t9, 88($zero) # -2 in DATA_MEM[22] **********
lw $gp, 52($zero) # 32'h1fffffff in $gp
sw $k0, 92($zero) # 32'hffff0007 in DATA_MEM[23]
sw $k1, 96($zero) # 0 in DATA_MEM[24]
sw $gp, 100($zero) # 32'h1fffffff in DATA_MEM[25] |
arch/ARM/STM32/svd/stm32f7x9/stm32_svd-syscfg.ads | rocher/Ada_Drivers_Library | 192 | 10952 | -- This spec has been automatically generated from STM32F7x9.svd
pragma Restrictions (No_Elaboration_Code);
pragma Ada_2012;
pragma Style_Checks (Off);
with HAL;
with System;
package STM32_SVD.SYSCFG is
pragma Preelaborate;
---------------
-- Registers --
---------------
subtype MEMRM_MEM_MODE_Field is HAL.UInt3;
subtype MEMRM_SWP_FMC_Field is HAL.UInt2;
-- memory remap register
type MEMRM_Register is record
-- Memory mapping selection
MEM_MODE : MEMRM_MEM_MODE_Field := 16#0#;
-- unspecified
Reserved_3_7 : HAL.UInt5 := 16#0#;
-- Flash bank mode selection
FB_MODE : Boolean := False;
-- unspecified
Reserved_9_9 : HAL.Bit := 16#0#;
-- FMC memory mapping swap
SWP_FMC : MEMRM_SWP_FMC_Field := 16#0#;
-- unspecified
Reserved_12_31 : HAL.UInt20 := 16#0#;
end record
with Volatile_Full_Access, Size => 32,
Bit_Order => System.Low_Order_First;
for MEMRM_Register use record
MEM_MODE at 0 range 0 .. 2;
Reserved_3_7 at 0 range 3 .. 7;
FB_MODE at 0 range 8 .. 8;
Reserved_9_9 at 0 range 9 .. 9;
SWP_FMC at 0 range 10 .. 11;
Reserved_12_31 at 0 range 12 .. 31;
end record;
-- peripheral mode configuration register
type PMC_Register is record
-- unspecified
Reserved_0_15 : HAL.UInt16 := 16#0#;
-- ADC1DC2
ADC1DC2 : Boolean := False;
-- ADC2DC2
ADC2DC2 : Boolean := False;
-- ADC3DC2
ADC3DC2 : Boolean := False;
-- unspecified
Reserved_19_22 : HAL.UInt4 := 16#0#;
-- Ethernet PHY interface selection
MII_RMII_SEL : Boolean := False;
-- unspecified
Reserved_24_31 : HAL.UInt8 := 16#0#;
end record
with Volatile_Full_Access, Size => 32,
Bit_Order => System.Low_Order_First;
for PMC_Register use record
Reserved_0_15 at 0 range 0 .. 15;
ADC1DC2 at 0 range 16 .. 16;
ADC2DC2 at 0 range 17 .. 17;
ADC3DC2 at 0 range 18 .. 18;
Reserved_19_22 at 0 range 19 .. 22;
MII_RMII_SEL at 0 range 23 .. 23;
Reserved_24_31 at 0 range 24 .. 31;
end record;
-- EXTICR1_EXTI array element
subtype EXTICR1_EXTI_Element is HAL.UInt4;
-- EXTICR1_EXTI array
type EXTICR1_EXTI_Field_Array is array (0 .. 3) of EXTICR1_EXTI_Element
with Component_Size => 4, Size => 16;
-- Type definition for EXTICR1_EXTI
type EXTICR1_EXTI_Field
(As_Array : Boolean := False)
is record
case As_Array is
when False =>
-- EXTI as a value
Val : HAL.UInt16;
when True =>
-- EXTI as an array
Arr : EXTICR1_EXTI_Field_Array;
end case;
end record
with Unchecked_Union, Size => 16;
for EXTICR1_EXTI_Field use record
Val at 0 range 0 .. 15;
Arr at 0 range 0 .. 15;
end record;
-- external interrupt configuration register 1
type EXTICR1_Register is record
-- EXTI x configuration (x = 0 to 3)
EXTI : EXTICR1_EXTI_Field :=
(As_Array => False, Val => 16#0#);
-- unspecified
Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
with Volatile_Full_Access, Size => 32,
Bit_Order => System.Low_Order_First;
for EXTICR1_Register use record
EXTI at 0 range 0 .. 15;
Reserved_16_31 at 0 range 16 .. 31;
end record;
-- EXTICR2_EXTI array element
subtype EXTICR2_EXTI_Element is HAL.UInt4;
-- EXTICR2_EXTI array
type EXTICR2_EXTI_Field_Array is array (4 .. 7) of EXTICR2_EXTI_Element
with Component_Size => 4, Size => 16;
-- Type definition for EXTICR2_EXTI
type EXTICR2_EXTI_Field
(As_Array : Boolean := False)
is record
case As_Array is
when False =>
-- EXTI as a value
Val : HAL.UInt16;
when True =>
-- EXTI as an array
Arr : EXTICR2_EXTI_Field_Array;
end case;
end record
with Unchecked_Union, Size => 16;
for EXTICR2_EXTI_Field use record
Val at 0 range 0 .. 15;
Arr at 0 range 0 .. 15;
end record;
-- external interrupt configuration register 2
type EXTICR2_Register is record
-- EXTI x configuration (x = 4 to 7)
EXTI : EXTICR2_EXTI_Field :=
(As_Array => False, Val => 16#0#);
-- unspecified
Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
with Volatile_Full_Access, Size => 32,
Bit_Order => System.Low_Order_First;
for EXTICR2_Register use record
EXTI at 0 range 0 .. 15;
Reserved_16_31 at 0 range 16 .. 31;
end record;
-- EXTICR3_EXTI array element
subtype EXTICR3_EXTI_Element is HAL.UInt4;
-- EXTICR3_EXTI array
type EXTICR3_EXTI_Field_Array is array (8 .. 11) of EXTICR3_EXTI_Element
with Component_Size => 4, Size => 16;
-- Type definition for EXTICR3_EXTI
type EXTICR3_EXTI_Field
(As_Array : Boolean := False)
is record
case As_Array is
when False =>
-- EXTI as a value
Val : HAL.UInt16;
when True =>
-- EXTI as an array
Arr : EXTICR3_EXTI_Field_Array;
end case;
end record
with Unchecked_Union, Size => 16;
for EXTICR3_EXTI_Field use record
Val at 0 range 0 .. 15;
Arr at 0 range 0 .. 15;
end record;
-- external interrupt configuration register 3
type EXTICR3_Register is record
-- EXTI x configuration (x = 8 to 11)
EXTI : EXTICR3_EXTI_Field :=
(As_Array => False, Val => 16#0#);
-- unspecified
Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
with Volatile_Full_Access, Size => 32,
Bit_Order => System.Low_Order_First;
for EXTICR3_Register use record
EXTI at 0 range 0 .. 15;
Reserved_16_31 at 0 range 16 .. 31;
end record;
-- EXTICR4_EXTI array element
subtype EXTICR4_EXTI_Element is HAL.UInt4;
-- EXTICR4_EXTI array
type EXTICR4_EXTI_Field_Array is array (12 .. 15) of EXTICR4_EXTI_Element
with Component_Size => 4, Size => 16;
-- Type definition for EXTICR4_EXTI
type EXTICR4_EXTI_Field
(As_Array : Boolean := False)
is record
case As_Array is
when False =>
-- EXTI as a value
Val : HAL.UInt16;
when True =>
-- EXTI as an array
Arr : EXTICR4_EXTI_Field_Array;
end case;
end record
with Unchecked_Union, Size => 16;
for EXTICR4_EXTI_Field use record
Val at 0 range 0 .. 15;
Arr at 0 range 0 .. 15;
end record;
-- external interrupt configuration register 4
type EXTICR4_Register is record
-- EXTI x configuration (x = 12 to 15)
EXTI : EXTICR4_EXTI_Field :=
(As_Array => False, Val => 16#0#);
-- unspecified
Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
with Volatile_Full_Access, Size => 32,
Bit_Order => System.Low_Order_First;
for EXTICR4_Register use record
EXTI at 0 range 0 .. 15;
Reserved_16_31 at 0 range 16 .. 31;
end record;
-- Compensation cell control register
type CMPCR_Register is record
-- Read-only. Compensation cell power-down
CMP_PD : Boolean;
-- unspecified
Reserved_1_7 : HAL.UInt7;
-- Read-only. READY
READY : Boolean;
-- unspecified
Reserved_9_31 : HAL.UInt23;
end record
with Volatile_Full_Access, Size => 32,
Bit_Order => System.Low_Order_First;
for CMPCR_Register use record
CMP_PD at 0 range 0 .. 0;
Reserved_1_7 at 0 range 1 .. 7;
READY at 0 range 8 .. 8;
Reserved_9_31 at 0 range 9 .. 31;
end record;
-----------------
-- Peripherals --
-----------------
-- System configuration controller
type SYSCFG_Peripheral is record
-- memory remap register
MEMRM : aliased MEMRM_Register;
-- peripheral mode configuration register
PMC : aliased PMC_Register;
-- external interrupt configuration register 1
EXTICR1 : aliased EXTICR1_Register;
-- external interrupt configuration register 2
EXTICR2 : aliased EXTICR2_Register;
-- external interrupt configuration register 3
EXTICR3 : aliased EXTICR3_Register;
-- external interrupt configuration register 4
EXTICR4 : aliased EXTICR4_Register;
-- Compensation cell control register
CMPCR : aliased CMPCR_Register;
end record
with Volatile;
for SYSCFG_Peripheral use record
MEMRM at 16#0# range 0 .. 31;
PMC at 16#4# range 0 .. 31;
EXTICR1 at 16#8# range 0 .. 31;
EXTICR2 at 16#C# range 0 .. 31;
EXTICR3 at 16#10# range 0 .. 31;
EXTICR4 at 16#14# range 0 .. 31;
CMPCR at 16#20# range 0 .. 31;
end record;
-- System configuration controller
SYSCFG_Periph : aliased SYSCFG_Peripheral
with Import, Address => System'To_Address (16#40013800#);
end STM32_SVD.SYSCFG;
|
src/main.asm | haramako/castle | 2 | 81790 |
.export scroll
.segment "main"
;;; scanline中のスクロールを行う
;;; x: X座標 y: Y座標
;;; See: http://forums.nesdev.com/viewtopic.php?p=64111#p64111
;;; use 56cycle ( jsr含む、最後の'sta _PPU_ADDR'まで )
scroll:
lda #0
clc
rol a
asl a
asl a
sta _nes_PPU_ADDR
tya
sta _nes_PPU_SCROLL
asl a
asl a
and #%11100000
sta _common_scroll_x+0
txa
lsr a
lsr a
lsr a
ora _common_scroll_x+0
;finish setting the scroll during HBlank (11 cycles)
stx _nes_PPU_SCROLL
sta _nes_PPU_ADDR
rts
|
programs/oeis/132/A132596.asm | neoneye/loda | 22 | 83478 | ; A132596: X-values of solutions to the equation X*(X + 1) - 6*Y^2 = 0.
; 0,2,24,242,2400,23762,235224,2328482,23049600,228167522,2258625624,22358088722,221322261600,2190864527282,21687323011224,214682365584962,2125136332838400,21036680962799042,208241673295152024,2061380051988721202,20405558846592060000,201994208413931878802,1999536525292726728024,19793371044513335401442,195934173919840627286400,1939548368153892937462562,19199549507619088747339224,190055946708036994535929682,1881359917572750856611957600,18623543229019471571583646322,184354072372621964859224505624,1824917180497200177020661409922,18064817732599379805347389593600,178823260145496597876453234526082,1770167783722366598959184955667224,17522854577078169391715396322146162,173458377987059327318194778265794400
seq $0,87799 ; a(n) = 10*a(n-1) - a(n-2), starting with a(0) = 2 and a(1) = 10.
div $0,4
|
programs/oeis/219/A219029.asm | neoneye/loda | 22 | 12718 | ; A219029: a(n) = n - 1 - phi(phi(n)).
; -1,0,1,2,2,4,4,5,6,7,6,9,8,11,10,11,8,15,12,15,16,17,12,19,16,21,20,23,16,25,22,23,24,25,26,31,24,31,30,31,24,37,30,35,36,35,24,39,36,41,34,43,28,47,38,47,44,45,30,51,44,53,50,47,48,57,46,51,48,61,46,63,48,61,58,63,60,69,54,63,62,65,42,75,52,73,62,71,48,81,66,71,76,71,70,79,64,85,82,83
mov $1,$0
sub $0,1
mov $3,$1
lpb $1
add $1,$3
mov $3,$1
div $3,2
seq $3,10554 ; a(n) = phi(phi(n)), where phi is the Euler totient function.
add $0,$3
sub $1,$0
sub $1,1
mov $0,$1
mov $1,$2
lpe
|
programs/oeis/260/A260444.asm | neoneye/loda | 22 | 96848 | ; A260444: Infinite palindromic word (a(1),a(2),a(3),...) with initial word w(1) = (1,0,0) and midword sequence (a(n)); see A260390.
; 1,0,0,1,0,0,1,0,1,0,0,1,0,0,1,0,1,0,0,1,0,0,1,0,1,0,0,1,0,0,1,1,1,0,0,1,0,0,1,0,1,0,0,1,0,0,1,0,1,0,0,1,0,0,1,0,1,0,0,1,0,0,1,0,1,0,0,1,0,0,1,0,1,0,0,1,0,0,1,0,1,0,0,1,0,0
mov $2,$0
min $0,1
mov $1,1
add $2,1
pow $2,2
add $2,1
lpb $2
div $0,2
mul $1,2
sub $2,1
mov $4,6
lpb $2
mov $3,$1
seq $3,10051 ; Characteristic function of primes: 1 if n is prime, else 0.
sub $0,$3
add $1,2
dif $2,4
cmp $4,$0
lpe
mul $2,$4
div $2,6
lpe
sub $0,1
mod $0,2
add $0,2
mod $0,2
|
oeis/286/A286630.asm | neoneye/loda-programs | 11 | 175706 | <reponame>neoneye/loda-programs
; A286630: a(0) = 1; for n >= 1, a(n) = A000040(n) * A002110(n).
; Submitted by <NAME>
; 1,4,18,150,1470,25410,390390,8678670,184294110,5131136010,187621103670,6217375194030,274567310987970,12474260804615610,562558737261811290,28899819781659096270,1727225399291072370690,113442860659098545705130,7154591262923825229979470,526507543922377892743899030,39613798938995626228686492690,2973266683745178762995356613310,254193936619913159724027679776270,22166354802209895662516793493401570,2115418028774754018587897846520889590,223640092502715287201050908291180338790
mov $1,1
mov $2,1
lpb $0
mov $3,$2
lpb $3
add $2,1
mov $4,$1
gcd $4,$2
cmp $4,1
cmp $4,0
sub $3,$4
lpe
sub $0,1
add $2,1
mul $1,$2
lpe
mul $2,$1
mov $0,$2
|
aosvs/aosvs-sys_memory.adb | SMerrony/dgemua | 2 | 22294 | -- MIT License
-- Copyright (c) 2021 <NAME>
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
with Ada.Characters.Handling; use Ada.Characters.Handling;
with Interfaces; use Interfaces;
with AOSVS.Agent;
with Debug_Logs; use Debug_Logs;
with Memory; use Memory;
with PARU_32;
package body AOSVS.Sys_Memory is
function Sys_GSHPT (CPU : in out CPU_T; PID : in Word_T; Ring : in Phys_Addr_T) return Boolean is
begin
Loggers.Debug_Print (Sc_Log, "?GSHPT");
CPU.AC(0) := RAM.Get_First_Shared_Page and 16#0003_ffff#;
CPU.AC(1) := RAM.Get_Num_Shared_Pages;
Loggers.Debug_Print (Sc_Log, "----- First: " & Dword_To_String (CPU.AC(0), Hex, 8) &
"(Hex), Number: " & Dword_To_String (CPU.AC(1), Decimal, 8) & "(Dec.)");
return true;
end Sys_GSHPT;
function Sys_MEM (CPU : in out CPU_T; PID : in Word_T; TID : in Word_T; Ring_Mask : in Phys_Addr_T) return Boolean is
I32 : Integer_32 := Integer_32(RAM.Get_First_Shared_Page) - Integer_32(RAM.Get_Last_Unshared_Page) - 4;
begin
Loggers.Debug_Print (Debug_Log, "?MEM"); Loggers.Debug_Print (Sc_Log, "?MEM");
-- No. Unshared Pages Available
CPU.AC(0) := (if I32 < 0 then 0 else Dword_T(I32)); -- Not sure why we need the 4-page gap...
-- No. Unshared Pages currently in use
CPU.AC(1) := RAM.Get_Num_Unshared_Pages;
-- Hignest Unshared addr in logical addr space
CPU.AC(2) := ((RAM.Get_Last_Unshared_Page - 1) * Dword_T(Memory.Words_Per_Page)) or Dword_T(Ring_Mask);
return true;
end Sys_MEM;
function Sys_MEMI (CPU : in out CPU_T; PID : in Word_T; TID : in Word_T; Ring_Mask : in Phys_Addr_T) return Boolean is
Change : Integer_32 := Dword_To_Integer_32(CPU.AC(0));
Last_Unshared : Dword_T := RAM.Get_Last_Unshared_Page;
begin
Loggers.Debug_Print (Debug_Log, "?MEMI"); Loggers.Debug_Print (Sc_Log, "?MEMI");
if Change > 0 then
-- adding pages
if Dword_T(Change) > (RAM.Get_First_Shared_Page - RAM.Get_Last_Unshared_Page) then
CPU.AC(0) := Dword_T(PARU_32.ERMEM);
Loggers.Debug_Print (Sc_Log, "----- Requested more pages than available");
return false;
end if;
for P in 1 .. Integer(Change) loop
Last_Unshared := Last_Unshared + 1;
RAM.Map_Page (Natural(Last_Unshared), false);
Loggers.Debug_Print (Sc_Log, "----- Mapped page : " & Dword_To_String (Last_Unshared, Hex, 8));
end loop;
CPU.AC(1) := ((RAM.Get_Last_Unshared_Page * Dword_T(Memory.Words_Per_Page)) - 1) or Dword_T(Ring_Mask);
Loggers.Debug_Print (Sc_Log, "----- Mapped for addresses up to " & Dword_To_String (CPU.AC(1), Octal, 11));
elsif Change < 0 then
-- removing pages
raise Processor.Not_Yet_Implemented with "Removing unshared pages with ?MEMI";
else
Loggers.Debug_Print (Sc_Log, "----- AC0 was zero - doing nothing");
end if;
return true;
end Sys_MEMI;
function Sys_SOPEN (CPU : in out CPU_T; PID, TID : in Word_T) return Boolean is
SO_Name : String := To_Upper (RAM.Read_String_BA (CPU.AC(0), false));
SO_Path : String := To_String(Agent.Actions.Get_Virtual_Root) &
Slashify_Path(Agent.Actions.Get_Working_Directory(PID) &
":" & SO_Name);
Chan_No, Err : Word_T;
begin
Loggers.Debug_Print (Sc_Log, "?SOPEN Path: " & SO_Name);
Loggers.Debug_Print (Sc_Log, "------ Resolved to local file: " & SO_Path);
if CPU.AC(1) /= 16#ffff_ffff# then
raise Processor.Not_Yet_Implemented with "?SOPEN of specific channel";
end if;
Agent.Actions.Shared_Open (PID_T(PID), SO_Path, (CPU.AC(2) = 0), Chan_No, Err);
if Err /= 0 then
CPU.AC(0) := Dword_T(Err);
return false;
end if;
CPU.AC(1) := Dword_T(Chan_No);
Loggers.Debug_Print (Sc_Log, "---- Allocated channel No." & Chan_No'Image);
return true;
end Sys_Sopen;
function Sys_SPAGE (CPU : in out CPU_T; PID : in Word_T; TID : in Word_T) return Boolean is
Chan_No : Natural := Natural(Lower_Word (CPU.AC(1)));
Pkt_Addr : Phys_Addr_T := Phys_Addr_T(CPU.AC(2));
Mem_Pages : Natural := Natural(RAM.Read_Word(Pkt_Addr + PARU_32.PSTI) and 16#00ff#) / 4;
Page_Arr : Page_Arr_T(1 .. Mem_Pages);
Start_Addr : Phys_Addr_T := Phys_Addr_T(RAM.Read_Dword(Pkt_Addr + PARU_32.PCAD));
Start_Block : Natural := Natural(RAM.Read_Dword(Pkt_Addr + PARU_32.PRNH)); -- Disk block addr (not page #)
Err : Word_T;
begin
Loggers.Debug_Print (Sc_Log, "?SPAGE - Channel No." & Chan_No'Image);
Loggers.Debug_Print (Sc_Log, "------ - Mem Pages. " & Mem_Pages'Image);
Loggers.Debug_Print (Sc_Log, "------ - Base Addr. " & Dword_To_String (RAM.Read_Dword(Pkt_Addr + PARU_32.PCAD), Octal, 11));
Loggers.Debug_Print (Sc_Log, "------ - 1st Block. " & Dword_To_String (RAM.Read_Dword(Pkt_Addr + PARU_32.PRNH), Octal, 11));
Agent.Actions.Shared_Read (PID_T(PID), Chan_No, Start_Addr, Mem_Pages, Start_Block, Page_Arr, Err);
if Err /= 0 then
CPU.AC(0) := Dword_T(Err);
return false;
end if;
return true;
end Sys_SPAGE;
function Sys_SSHPT (CPU : in out CPU_T; PID : in Word_T; Ring : in Phys_Addr_T) return Boolean is
Increase, Page_Num : Integer;
begin
Loggers.Debug_Print (Sc_Log, "?SSHPT");
Loggers.Debug_Print (Sc_Log, "----- First: " & Dword_To_String (CPU.AC(0), Hex, 8) &
"(Hex), Number: " & Dword_To_String (CPU.AC(1), Decimal, 8) & "(Dec.)");
if CPU.AC(1) < RAM.Get_Num_Shared_Pages then
raise Processor.Not_Yet_Implemented with "Removing shared pages via ?SSHPT";
end if;
Increase := Integer(CPU.AC(1)) - Integer(RAM.Get_Num_Shared_Pages);
Loggers.Debug_Print (Sc_Log, "----- Change Requested:" & Increase'Image & "(Dec.)");
-- At the beginning?
Page_Num := Integer(CPU.AC(0));
if CPU.AC(0) < (RAM.Get_First_Shared_Page and 16#0003_ffff#) then
for P in 0 .. Increase - 1 loop
if RAM.Page_Mapped (Page_Num + P) then
CPU.AC(0) := Dword_T(PARU_32.ERMEM);
return false;
end if;
RAM.Map_Page (P, true);
end loop;
else -- add at end
while RAM.Get_Num_Shared_Pages < CPU.AC(1) loop
RAM.Map_Page (Integer(RAM.Get_First_Shared_Page + RAM.Get_Num_Shared_Pages), true);
Loggers.Debug_Print (Sc_Log, "----- Mapping Page:" &
Dword_To_String(RAM.Get_First_Shared_Page + RAM.Get_Num_Shared_Pages, Hex, 8));
end loop;
end if;
return true;
end Sys_SSHPT;
end AOSVS.Sys_Memory; |
BasicConcreteImplementations.agda | mietek/lamport-timestamps | 0 | 10958 | module BasicConcreteImplementations where
open import AbstractInterfaces public
-- Process identifiers.
instance
⟨P⟩ : IsProc
⟨P⟩ = record
{ Proc = ℕ
; _≡ₚ?_ = _≡?_
; _<ₚ_ = _<_
; trans<ₚ = trans<
; tri<ₚ = tri<
}
-- Process clocks, message timestamps, and event timestamps.
instance
⟨T⟩ : IsTime
⟨T⟩ = record
{ Time = ℕ
; _≡ₜ?_ = _≡?_
; _<ₜ_ = _<_
; trans<ₜ = trans<
; tri<ₜ = tri<
; irrefl<ₜ = irrefl<
; sucₜ = suc
; _⊔ₜ_ = _⊔_
; n<s[n⊔m]ₜ = n<s[n⊔m]
}
-- Messages.
data BasicMsg : (Pᵢ Pⱼ : Proc) (Tₘ : Time) → Set where
instance
⟨M⟩ : IsMsg
⟨M⟩ = record
{ Msg = BasicMsg
}
-- Events within one process.
data BasicEvent : Proc → Time → Set where
send : ∀ {Cᵢ Pᵢ Pⱼ Tₘ} {{_ : Tₘ ≡ sucₜ Cᵢ}} →
Msg Pᵢ Pⱼ Tₘ → BasicEvent Pᵢ Tₘ
recv : ∀ {Cⱼ Pᵢ Pⱼ Tₘ Tⱼ} {{_ : Tⱼ ≡ sucₜ (Tₘ ⊔ₜ Cⱼ)}} →
Msg Pᵢ Pⱼ Tₘ → BasicEvent Pⱼ Tⱼ
instance
⟨E⟩ : IsEvent
⟨E⟩ = record
{ Event = BasicEvent
; isSendₑ = λ {Cᵢ} m a → a ≡ send {Cᵢ} m
; isRecvₑ = λ {Cⱼ} m a → a ≡ recv {Cⱼ} m
; absurdₑ = λ { {{refl}} (refl , ()) }
}
|
src/yeison_multi.ads | mosteo/yeison | 6 | 30356 | package Yeison_Multi with Preelaborate is
type Any is tagged private;
type Scalar is tagged private with
Integer_Literal => To_Int,
String_Literal => To_Str;
function To_Int (Img : String) return Scalar;
function To_Str (Img : Wide_Wide_String) return Scalar;
type Map is tagged private with
Aggregate => (Empty => Empty,
Add_Named => Insert);
function Empty return Map;
procedure Insert (This : in out Map; Key : String; Val : Any'Class);
procedure Insert (This : in out Map; Key : String; Val : Scalar'Class);
procedure Insert (This : in out Map; Key : String; Val : Map);
private
type Any is tagged null record;
type Scalar is tagged null record;
type Map is tagged null record;
end Yeison_Multi;
|
oeis/034/A034584.asm | neoneye/loda-programs | 11 | 8439 | <filename>oeis/034/A034584.asm<gh_stars>10-100
; A034584: Radon-Hurwitz numbers: log_2 of dimension of an irreducible R-module for Clifford algebra Cl_n.
; Submitted by <NAME>(s1)
; 0,1,2,2,3,3,3,3,4,5,6,6,7,7,7,7,8,9,10,10,11,11,11,11,12,13,14,14,15,15,15,15,16,17,18,18,19,19,19,19,20,21,22,22,23,23,23,23,24,25,26,26,27,27,27,27,28,29,30,30,31,31,31,31
mov $1,$0
lpb $0
mul $0,7
mod $0,8
div $0,2
lpe
add $1,$0
div $1,2
mov $0,$1
|
Transynther/x86/_processed/NONE/_xt_/i7-7700_9_0x48.log_21829_1113.asm | ljhsiun2/medusa | 9 | 83688 | .global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r15
push %r8
push %r9
push %rax
push %rcx
push %rdi
push %rdx
push %rsi
lea addresses_D_ht+0x1b101, %r8
dec %r10
mov (%r8), %dx
nop
nop
nop
nop
sub $50274, %rax
lea addresses_WC_ht+0x1cc03, %r15
nop
nop
nop
nop
nop
and $25548, %r9
movups (%r15), %xmm5
vpextrq $1, %xmm5, %rax
nop
nop
dec %r9
lea addresses_A_ht+0x1d863, %rsi
lea addresses_WT_ht+0x4063, %rdi
nop
nop
nop
nop
nop
sub %r15, %r15
mov $88, %rcx
rep movsw
sub $52378, %r15
lea addresses_WT_ht+0x1b9e3, %rdi
nop
nop
nop
sub %r15, %r15
mov $0x6162636465666768, %rcx
movq %rcx, (%rdi)
nop
nop
dec %r15
lea addresses_WT_ht+0x111e3, %rsi
lea addresses_WT_ht+0x1e873, %rdi
clflush (%rsi)
nop
nop
nop
nop
xor %rdx, %rdx
mov $23, %rcx
rep movsw
nop
cmp %r8, %r8
lea addresses_WC_ht+0x9de3, %r10
nop
nop
nop
cmp %rdx, %rdx
movl $0x61626364, (%r10)
nop
nop
sub $12414, %r8
lea addresses_normal_ht+0x1a3b, %r15
nop
nop
nop
cmp %r9, %r9
mov $0x6162636465666768, %rsi
movq %rsi, %xmm4
vmovups %ymm4, (%r15)
nop
nop
nop
nop
dec %rdx
lea addresses_UC_ht+0x101e3, %rcx
nop
nop
nop
nop
nop
cmp %r10, %r10
mov $0x6162636465666768, %rsi
movq %rsi, (%rcx)
and %r9, %r9
lea addresses_D_ht+0x1c883, %rsi
mfence
movw $0x6162, (%rsi)
nop
nop
nop
nop
nop
sub $633, %r8
lea addresses_D_ht+0x18e37, %rsi
lea addresses_WT_ht+0x174f7, %rdi
nop
add $34328, %r8
mov $78, %rcx
rep movsl
nop
nop
nop
nop
nop
xor $65086, %r9
lea addresses_normal_ht+0x11d03, %r8
clflush (%r8)
add $44292, %rdx
mov $0x6162636465666768, %rcx
movq %rcx, (%r8)
and %r8, %r8
pop %rsi
pop %rdx
pop %rdi
pop %rcx
pop %rax
pop %r9
pop %r8
pop %r15
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r13
push %r14
push %r8
push %r9
push %rdi
push %rsi
// Store
lea addresses_US+0xf843, %rdi
nop
nop
nop
nop
cmp $16138, %r8
mov $0x5152535455565758, %rsi
movq %rsi, (%rdi)
nop
cmp $53455, %r10
// Faulty Load
lea addresses_D+0x169e3, %r13
nop
sub $14568, %r14
mov (%r13), %rdi
lea oracles, %r8
and $0xff, %rdi
shlq $12, %rdi
mov (%r8,%rdi,1), %rdi
pop %rsi
pop %rdi
pop %r9
pop %r8
pop %r14
pop %r13
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'type': 'addresses_D', 'AVXalign': False, 'congruent': 0, 'size': 4, 'same': True, 'NT': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_US', 'AVXalign': False, 'congruent': 4, 'size': 8, 'same': False, 'NT': False}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'type': 'addresses_D', 'AVXalign': False, 'congruent': 0, 'size': 8, 'same': True, 'NT': False}}
<gen_prepare_buffer>
{'OP': 'LOAD', 'src': {'type': 'addresses_D_ht', 'AVXalign': False, 'congruent': 1, 'size': 2, 'same': True, 'NT': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_WC_ht', 'AVXalign': False, 'congruent': 4, 'size': 16, 'same': False, 'NT': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_A_ht', 'congruent': 4, 'same': False}, 'dst': {'type': 'addresses_WT_ht', 'congruent': 7, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_WT_ht', 'AVXalign': False, 'congruent': 11, 'size': 8, 'same': False, 'NT': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_WT_ht', 'congruent': 10, 'same': False}, 'dst': {'type': 'addresses_WT_ht', 'congruent': 2, 'same': True}}
{'OP': 'STOR', 'dst': {'type': 'addresses_WC_ht', 'AVXalign': False, 'congruent': 10, 'size': 4, 'same': False, 'NT': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_normal_ht', 'AVXalign': False, 'congruent': 2, 'size': 32, 'same': False, 'NT': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_UC_ht', 'AVXalign': False, 'congruent': 11, 'size': 8, 'same': False, 'NT': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_D_ht', 'AVXalign': False, 'congruent': 5, 'size': 2, 'same': False, 'NT': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_D_ht', 'congruent': 2, 'same': False}, 'dst': {'type': 'addresses_WT_ht', 'congruent': 1, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_normal_ht', 'AVXalign': False, 'congruent': 4, 'size': 8, 'same': False, 'NT': False}}
{'36': 21829}
36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36
*/
|
_build/dispatcher/jmp_ippsGFpECTstPoint_28802bc6.asm | zyktrcn/ippcp | 1 | 88937 | extern m7_ippsGFpECTstPoint:function
extern n8_ippsGFpECTstPoint:function
extern y8_ippsGFpECTstPoint:function
extern e9_ippsGFpECTstPoint:function
extern l9_ippsGFpECTstPoint:function
extern n0_ippsGFpECTstPoint:function
extern k0_ippsGFpECTstPoint:function
extern ippcpJumpIndexForMergedLibs
extern ippcpSafeInit:function
segment .data
align 8
dq .Lin_ippsGFpECTstPoint
.Larraddr_ippsGFpECTstPoint:
dq m7_ippsGFpECTstPoint
dq n8_ippsGFpECTstPoint
dq y8_ippsGFpECTstPoint
dq e9_ippsGFpECTstPoint
dq l9_ippsGFpECTstPoint
dq n0_ippsGFpECTstPoint
dq k0_ippsGFpECTstPoint
segment .text
global ippsGFpECTstPoint:function (ippsGFpECTstPoint.LEndippsGFpECTstPoint - ippsGFpECTstPoint)
.Lin_ippsGFpECTstPoint:
db 0xf3, 0x0f, 0x1e, 0xfa
call ippcpSafeInit wrt ..plt
align 16
ippsGFpECTstPoint:
db 0xf3, 0x0f, 0x1e, 0xfa
mov rax, qword [rel ippcpJumpIndexForMergedLibs wrt ..gotpc]
movsxd rax, dword [rax]
lea r11, [rel .Larraddr_ippsGFpECTstPoint]
mov r11, qword [r11+rax*8]
jmp r11
.LEndippsGFpECTstPoint:
|
src/main/antlr4/org/bierner/matchbook/parser/Matchbook.g4 | gbierner/matchbook | 0 | 594 | /*
* Copyright (c) 2014, <NAME>
*/
grammar Matchbook;
@parser::header {
}
@lexer::header {
}
expression: or EOF;
or: is (OR is)*;
is: isnt (IS isnt)*;
isnt: sequence (ISNT sequence)?;
sequence: repeat+;
repeat:
capture #RepeatNone
| capture '?' #Repeat0or1
| capture '[' NUMBER ']' #RepeatN
| capture '[' NUMBER ':' NUMBER ']' #RepeatNtoM
;
capture: (LOWERCASE '=')? atom;
atom:
LOWERCASE #Stems
| STEMS #Stems
| STRICT_STEMS #StrictStems
| TOKENS #Tokens
| EXACT_CONCEPT #ExactConcept
| CONCEPT #Concept
| CHUNK #Chunk
| POS #Pos
| REGEX #Regex
| START #Start
| END #End
| ANNOTATION #Annotation
| ANNOTATION WITH or #With
| ANNOTATION WITH '(' or (',' or)* ')' #WithList
| '(' or ')' #Expr
;
START:'START';
END :'END';
OR :'OR';
IS :'IS';
ISNT :'ISNT';
WITH :'WITH';
NUMBER: [0-9]+;
LOWERCASE : [a-z][a-z0-9_]*;
ANNOTATION: [A-Z]+(':'[a-zA-Z]+)?;
TOKENS: '"'~['"']+'"';
STEMS: '\''~['\'']+'\'';
STRICT_STEMS: '\'''\''~['\'']+'\'''\'';
EXACT_CONCEPT: '<''<'~['>']+'>''>';
CONCEPT: '<'~['>']+'>';
CHUNK: '['[A-Z]+']';
POS: '{'[A-Z]+'}';
REGEX: '/'(~['/']|'\\/')+'/';
WS : [ \t\r\n]+ -> skip ; // skip spaces, tabs, newlines
|
src/Sym_Expr/test/test_report.adb | fintatarta/eugen | 0 | 22258 | ----------------------------------------------------------------------------
-- Symbolic Expressions (symexpr)
--
-- Copyright (C) 2012, <NAME>
--
-- This file is part of symexpr.
--
-- symexpr is free software: you can redistribute it and/or modify
-- it under the terms of the Lesser GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- symexpr is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the Lesser GNU General Public License
-- along with gclp. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------
with Ada.Strings.Fixed;
package body Test_Report is
function Pad_To (What : String; To : Positive)
return String
is
use Ada.Strings.Fixed;
begin
if What'Length < To then
return (To - What'Length) * " " & What;
else
return What;
end if;
end Pad_To;
procedure Be_Verbose (This : in out Reporter_Type;
Flag : in Boolean := True) is
begin
This.Verbose := Flag;
end Be_Verbose;
procedure Set_Tab (This : in out Reporter_Type;
Tab : in Positive) is
begin
This.Tab := Tab;
end Set_Tab;
procedure Close_Suite (This : in out Reporter_Type) is
Suite_Name : constant String := To_String (This.Name);
begin
if (This.N_Tests = 0) then
return;
end if;
if (Suite_Name /= "") then
declare
Buf : constant String := " Test suite '" & Suite_Name & "'";
begin
if (This.Tab <= Buf'Length) then
This.Tab := Buf'Length + 1;
end if;
if This.Tab > Buf'Length then
Put (File => This.Output_To.all,
Item => Buf
& To_String ((This.Tab - Buf'Length) * '.'));
else
Put (File => This.Output_To.all,
Item => Buf & "...");
This.Tab := Buf'Length + 3;
end if;
Put (File => This.Output_To.all,
Item => " passed ");
end;
else
Put (File => This.Output_To.all,
Item => "Passed ");
end if;
declare
Plural : String := "s";
begin
if (This.N_Test_Ok = 1) then
Plural := " ";
end if;
Put (File => This.Output_To.all,
Item => Pad_To (Positive'Image (This.N_Test_OK), 3)
& " test" & Plural & " out of "
& Pad_To (Natural'Image (This.N_Tests), 3)
& ": ");
end;
if (This.N_Tests = This.N_Test_OK) then
This.N_Suite_OK := This.N_Suite_OK + 1;
Put_Line (File => This.Output_To.all,
Item => "SUCCESS");
else
Put (File => This.Output_To.all,
Item => "FAILURE");
Put (" ");
declare
use Boolean_Lists;
Position : Cursor;
begin
Position := This.Suite_Results.First;
while Position /= No_Element loop
if Element (Position) then
Put ("+");
else
Put ("-");
end if;
Next (Position);
end loop;
end;
This.Status := Ada.Command_Line.Failure;
end if;
This.N_Tests := 0;
This.N_Test_OK := 0;
This.N_Suites := This.N_Suites + 1;
end Close_Suite;
procedure Final (This : in out Reporter_Type;
Set_Status : in Boolean := True) is
function Plural(X : Natural) return String is
begin
if (X = 1) then
return "";
else
return "s";
end if;
end Plural;
begin
if (This.N_Suites = 0 and This.N_Tests = 0) then
return;
end if;
-- Put_Line ("XXX" & Integer'Image (This.N_Tests));
if (This.N_Tests > 0) then
Close_Suite(This);
end if;
if (This.N_Suites > 1) then
New_Line (File => This.Output_To.all);
Put (File => This.Output_To.all,
Item => "Passed "
& Pad_To (Integer'Image (This.N_Suite_OK), 3)
& " test suite" & Plural (This.N_Suite_OK) & " out of "
& Pad_To (Integer'Image (This.N_Suites), 3)
& ": ");
if (This.N_Suites = This.N_Suite_OK) then
Put_Line(File => This.Output_To.all,
Item => "SUCCESS");
else
Put_Line(File => This.Output_To.all,
Item => "FAILURE");
end if;
end if;
if (Set_Status) then
Ada.Command_Line.Set_Exit_Status(This.Status);
end if;
end Final;
procedure New_Suite (This : in out Reporter_Type;
Name : in String := "") is
begin
if (This.Verbose) then
Put_line (This.Output_To.all, "New test suite " & Name);
end if;
-- Put_Line ("YYY" & Integer'Image (This.N_Tests));
if (This.N_Tests /= 0) then
Close_Suite(This);
end if;
This.Name := To_Unbounded_String (Name);
This.Suite_Results.Clear;
end New_Suite;
procedure Success (This : in out Reporter_Type) is
begin
New_Result (This, True);
end Success;
procedure Failure (This : in out Reporter_Type) is
begin
New_Result (This, False);
end Failure;
procedure New_Result (This : in out Reporter_Type;
Ok : in Boolean) is
begin
if (This.Verbose) then
if (Ok) then
Put_line (This.Output_To.all, "Success");
else
Put_line (This.Output_To.all, "FAILURE");
end if;
end if;
This.N_Tests := This.N_Tests + 1;
if (Ok) then
This.N_Test_OK := This.N_Test_OK + 1;
end if;
This.Suite_Results.Append (OK);
end New_Result;
procedure Do_Suite (This : in out Reporter_Type;
Cases : in Test_Case_Array;
Name : in String := "") is
begin
New_Suite(This, Name);
for I in Cases'Range loop
if (This.Verbose) then
Put (File => This.Output_To.all,
Item => "Test # " & Positive'Image(I) & " ");
end if;
New_Result(This, Check(Cases(I)));
end loop;
end Do_Suite;
procedure Set_Output (This : in out Reporter_Type;
File : in File_Access) is
begin
This.Output_To := File;
end Set_Output;
end Test_Report;
-- -- function "and" (X, Y : Ada.Command_Line.Exit_Status)
-- -- return Ada.Command_Line.Exit_Status is
-- -- begin
-- -- if (X = Ada.Command_Line.Success) then
-- -- return Y;
-- -- else
-- -- return Ada.Command_Line.Failure;
-- -- end if;
-- -- end "and";
--
-- procedure Do_Report (This : in out Reporter_Type;
-- Num_Trials : in Positive;
-- Num_Success : in Natural;
-- Name : in String := "";
-- Set_Status : in Boolean := True)
-- is
--
-- begin
-- This.N_Suites := This.N_Suites + 1;
--
-- if (Name /= "") then
-- Put ("Test " & Name & ": passed ");
-- else
-- Put ("Passed ");
-- end if;
--
-- Put (Positive'Image(Num_Success)
-- & " tests out of "
-- & Natural'Image(Num_Trials)
-- & ": ");
--
-- if (Num_Success = Num_Trials) then
-- This.N_Suite_OK := This.N_Suite_OK + 1;
-- Put_Line ("SUCCESS");
-- else
-- Put_Line ("FAILURE");
-- This.Status := Ada.Command_Line.Failure;
-- end if;
--
-- if (Set_Status) then
-- Ada.Command_Line.Set_Exit_Status(This.Status);
-- end if;
-- end Do_Report;
|
Transynther/x86/_processed/NONE/_zr_/i7-7700_9_0x48.log_21829_170.asm | ljhsiun2/medusa | 9 | 88142 | .global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r8
push %rax
push %rbx
push %rcx
push %rdi
push %rsi
lea addresses_WT_ht+0x5d4b, %rdi
nop
nop
add %r8, %r8
movb $0x61, (%rdi)
nop
nop
nop
add $27953, %rbx
lea addresses_WC_ht+0x1915f, %rsi
lea addresses_UC_ht+0x1690b, %rdi
nop
nop
dec %r10
mov $67, %rcx
rep movsb
nop
nop
nop
nop
add $57736, %rsi
lea addresses_WC_ht+0x1450b, %rsi
lea addresses_UC_ht+0xe70b, %rdi
nop
nop
nop
nop
nop
inc %r10
mov $127, %rcx
rep movsw
nop
nop
nop
nop
xor $12571, %rsi
lea addresses_normal_ht+0x18b0b, %rsi
nop
nop
and $61659, %rdi
mov $0x6162636465666768, %r8
movq %r8, (%rsi)
nop
nop
nop
add $46037, %r10
lea addresses_UC_ht+0x18d0b, %rdi
and $16349, %rsi
mov $0x6162636465666768, %rbx
movq %rbx, (%rdi)
nop
add %r10, %r10
lea addresses_WC_ht+0x1d10b, %rsi
lea addresses_normal_ht+0x1620b, %rdi
nop
nop
nop
and $24048, %rbx
mov $1, %rcx
rep movsb
nop
nop
nop
nop
nop
xor %rsi, %rsi
lea addresses_A_ht+0x83cb, %rbx
nop
xor %r8, %r8
movw $0x6162, (%rbx)
sub %r10, %r10
lea addresses_normal_ht+0x595b, %rbx
nop
nop
sub %rax, %rax
mov $0x6162636465666768, %r8
movq %r8, (%rbx)
nop
nop
nop
nop
nop
lfence
lea addresses_WC_ht+0x1710b, %rdi
xor $30050, %rcx
movl $0x61626364, (%rdi)
nop
nop
nop
nop
nop
sub %rbx, %rbx
lea addresses_UC_ht+0x19f0b, %rsi
lea addresses_UC_ht+0x1da0b, %rdi
nop
nop
nop
and %r8, %r8
mov $3, %rcx
rep movsb
nop
xor $26241, %r8
pop %rsi
pop %rdi
pop %rcx
pop %rbx
pop %rax
pop %r8
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r8
push %r9
push %rbp
push %rcx
push %rdi
push %rsi
// Store
lea addresses_WC+0xcb0b, %r10
cmp %r9, %r9
movl $0x51525354, (%r10)
sub %r10, %r10
// Load
mov $0x90b, %r10
nop
nop
nop
nop
sub %r8, %r8
mov (%r10), %edi
nop
nop
nop
nop
nop
dec %r9
// Store
mov $0x6029e000000005ff, %rcx
nop
nop
nop
cmp %r9, %r9
mov $0x5152535455565758, %r8
movq %r8, (%rcx)
cmp %r8, %r8
// Store
lea addresses_normal+0x310b, %rsi
nop
inc %rdi
movb $0x51, (%rsi)
nop
nop
and $8199, %r9
// Store
lea addresses_UC+0x15083, %r9
nop
nop
inc %rbp
mov $0x5152535455565758, %r8
movq %r8, %xmm3
and $0xffffffffffffffc0, %r9
movaps %xmm3, (%r9)
nop
add $13708, %r9
// Faulty Load
lea addresses_UC+0x3d0b, %rcx
nop
sub %rdi, %rdi
vmovups (%rcx), %ymm6
vextracti128 $0, %ymm6, %xmm6
vpextrq $1, %xmm6, %r10
lea oracles, %r9
and $0xff, %r10
shlq $12, %r10
mov (%r9,%r10,1), %r10
pop %rsi
pop %rdi
pop %rcx
pop %rbp
pop %r9
pop %r8
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'type': 'addresses_UC', 'AVXalign': False, 'congruent': 0, 'size': 16, 'same': False, 'NT': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_WC', 'AVXalign': False, 'congruent': 9, 'size': 4, 'same': False, 'NT': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_P', 'AVXalign': False, 'congruent': 9, 'size': 4, 'same': False, 'NT': True}}
{'OP': 'STOR', 'dst': {'type': 'addresses_NC', 'AVXalign': False, 'congruent': 1, 'size': 8, 'same': False, 'NT': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_normal', 'AVXalign': False, 'congruent': 9, 'size': 1, 'same': False, 'NT': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_UC', 'AVXalign': True, 'congruent': 1, 'size': 16, 'same': False, 'NT': False}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'type': 'addresses_UC', 'AVXalign': False, 'congruent': 0, 'size': 32, 'same': True, 'NT': False}}
<gen_prepare_buffer>
{'OP': 'STOR', 'dst': {'type': 'addresses_WT_ht', 'AVXalign': False, 'congruent': 6, 'size': 1, 'same': False, 'NT': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_WC_ht', 'congruent': 2, 'same': False}, 'dst': {'type': 'addresses_UC_ht', 'congruent': 8, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_WC_ht', 'congruent': 11, 'same': True}, 'dst': {'type': 'addresses_UC_ht', 'congruent': 5, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_normal_ht', 'AVXalign': False, 'congruent': 9, 'size': 8, 'same': True, 'NT': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_UC_ht', 'AVXalign': False, 'congruent': 11, 'size': 8, 'same': False, 'NT': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_WC_ht', 'congruent': 9, 'same': False}, 'dst': {'type': 'addresses_normal_ht', 'congruent': 7, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_A_ht', 'AVXalign': False, 'congruent': 6, 'size': 2, 'same': False, 'NT': True}}
{'OP': 'STOR', 'dst': {'type': 'addresses_normal_ht', 'AVXalign': False, 'congruent': 4, 'size': 8, 'same': False, 'NT': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_WC_ht', 'AVXalign': False, 'congruent': 9, 'size': 4, 'same': False, 'NT': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_UC_ht', 'congruent': 9, 'same': True}, 'dst': {'type': 'addresses_UC_ht', 'congruent': 8, 'same': False}}
{'00': 21829}
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*/
|
oeis/004/A004798.asm | neoneye/loda-programs | 11 | 81033 | ; A004798: Convolution of Fibonacci numbers 1,2,3,5,... with themselves.
; Submitted by <NAME>
; 1,4,10,22,45,88,167,310,566,1020,1819,3216,5645,9848,17090,29522,50793,87080,148819,253610,431086,731064,1237175,2089632,3523225,5930668,9968122,16730830,28045221,46954360,78524159,131181406,218933030,365044788,608135635,1012268592,1683650213,2798252960,4647483314,7713650570,12794628321,21209687624,35139219115,58185218642,96295652830,159288398448,263362793327,435237460800,718965265201,1187154006100,1959435562474,3232857139846,5331876564765,8790585138328,14487896999255,23869768867462
add $0,2
seq $0,140992 ; a(0) = 0, a(1) = 1; for n > 1, a(n) = a(n-2) + a(n-1) + A000071(n+1).
sub $0,1
|
Transynther/x86/_processed/AVXALIGN/_zr_/i9-9900K_12_0xa0.log_21829_1876.asm | ljhsiun2/medusa | 9 | 24593 | .global s_prepare_buffers
s_prepare_buffers:
push %r11
push %r12
push %r14
push %rbx
push %rcx
push %rdi
push %rsi
lea addresses_D_ht+0x11583, %rsi
lea addresses_A_ht+0x1b583, %rdi
clflush (%rsi)
sub $15762, %r12
mov $37, %rcx
rep movsw
nop
cmp $46543, %r14
lea addresses_UC_ht+0xa921, %rsi
lea addresses_A_ht+0x1b65b, %rdi
nop
nop
nop
nop
nop
inc %rbx
mov $48, %rcx
rep movsb
nop
inc %rcx
lea addresses_normal_ht+0x6583, %rsi
lea addresses_normal_ht+0x10c4d, %rdi
nop
add $38629, %r11
mov $38, %rcx
rep movsw
nop
nop
nop
add $52308, %r12
lea addresses_WC_ht+0x13dab, %rbx
nop
nop
add %r12, %r12
mov $0x6162636465666768, %rcx
movq %rcx, %xmm2
vmovups %ymm2, (%rbx)
nop
nop
nop
nop
and $43089, %rsi
lea addresses_A_ht+0xc003, %r11
nop
nop
nop
sub %rbx, %rbx
movb $0x61, (%r11)
add $18320, %r11
lea addresses_WT_ht+0xf583, %rsi
clflush (%rsi)
nop
nop
nop
nop
nop
cmp %rbx, %rbx
movups (%rsi), %xmm5
vpextrq $0, %xmm5, %r14
nop
nop
nop
nop
cmp $47410, %r12
lea addresses_WT_ht+0x1a7d2, %r14
nop
and $30896, %rcx
vmovups (%r14), %ymm5
vextracti128 $1, %ymm5, %xmm5
vpextrq $0, %xmm5, %rdi
sub %r12, %r12
pop %rsi
pop %rdi
pop %rcx
pop %rbx
pop %r14
pop %r12
pop %r11
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r14
push %r8
push %r9
push %rcx
// Faulty Load
lea addresses_A+0x17583, %r9
nop
nop
nop
nop
nop
dec %rcx
movaps (%r9), %xmm4
vpextrq $0, %xmm4, %r14
lea oracles, %r8
and $0xff, %r14
shlq $12, %r14
mov (%r8,%r14,1), %r14
pop %rcx
pop %r9
pop %r8
pop %r14
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'src': {'NT': False, 'same': False, 'congruent': 0, 'type': 'addresses_A', 'AVXalign': False, 'size': 32}, 'OP': 'LOAD'}
[Faulty Load]
{'src': {'NT': False, 'same': True, 'congruent': 0, 'type': 'addresses_A', 'AVXalign': True, 'size': 16}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'src': {'same': False, 'congruent': 9, 'type': 'addresses_D_ht'}, 'OP': 'REPM', 'dst': {'same': False, 'congruent': 11, 'type': 'addresses_A_ht'}}
{'src': {'same': True, 'congruent': 1, 'type': 'addresses_UC_ht'}, 'OP': 'REPM', 'dst': {'same': False, 'congruent': 3, 'type': 'addresses_A_ht'}}
{'src': {'same': False, 'congruent': 11, 'type': 'addresses_normal_ht'}, 'OP': 'REPM', 'dst': {'same': True, 'congruent': 1, 'type': 'addresses_normal_ht'}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 2, 'type': 'addresses_WC_ht', 'AVXalign': False, 'size': 32}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 4, 'type': 'addresses_A_ht', 'AVXalign': False, 'size': 1}}
{'src': {'NT': False, 'same': False, 'congruent': 11, 'type': 'addresses_WT_ht', 'AVXalign': False, 'size': 16}, 'OP': 'LOAD'}
{'src': {'NT': False, 'same': False, 'congruent': 0, 'type': 'addresses_WT_ht', 'AVXalign': False, 'size': 32}, 'OP': 'LOAD'}
{'00': 21829}
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*/
|
ourGrammar.g4 | adam-pog/sawatiKhap | 0 | 556 | grammar ourGrammar;
options {
language=Java;
}
start : 'settings' '[' option+ ']' workspace*;
option : ID '=' value;
workspace : 'workspace' NUM '[' application+ ']';
application : ID '{' appoption* '}';
appoption : ID '=' appvalue;
ID : ('a'..'z' | 'A'..'Z') ('a'..'z' | 'A'..'Z'| NUM | SYMBOLS)+;
value : ID | NUM | (SYMBOLS | ID | NUM)+;
appvalue : '\'' (~'\'')* '\'' ;
SYMBOLS : '/'|'&'|'*'|'^'|'%'|'_'|'-'|'#'|'"'|':'|'.'|',';
NUM : [0-9]+;
WS : [ \r\t\n]+ -> skip;
|
tests/syntax_examples/src/basic_declaration-subprogram_body_stub_name.adb | TNO/Dependency_Graph_Extractor-Ada | 1 | 25080 | separate(Basic_Declaration)
procedure Subprogram_Body_Stub_Name is
begin
null;
end Subprogram_Body_Stub_Name;
|
libsrc/_DEVELOPMENT/arch/zx/display/c/sccz80/zx_saddr2cx.asm | teknoplop/z88dk | 0 | 19278 | <filename>libsrc/_DEVELOPMENT/arch/zx/display/c/sccz80/zx_saddr2cx.asm<gh_stars>0
; uint zx_saddr2cx(void *saddr)
SECTION code_clib
SECTION code_arch
PUBLIC zx_saddr2cx
EXTERN asm_zx_saddr2cx
defc zx_saddr2cx = asm_zx_saddr2cx
|
xnlib/xnclib/setjmp.asm | manaskamal/aurora-xeneva | 8 | 1851 | ;;-------------------------------------------------------
;; Copyright (C) <NAME>
;;
;; /PROJECT - Aurora's Xeneva
;; /AUTHOR - <NAME>
;;
;;-------------------------------------------------------
section .text
[BITS 64]
global setjmp
setjmp:
mov [rcx], rbx
mov [rcx + 8], rbp
mov [rcx + 16], r12
mov [rcx + 24], r13
mov [rcx + 32], r14
mov [rcx + 40],r15
pop r15
mov rdx, rsp
mov [rcx + 48], rdx
push r15
mov rdx,[rsp]
mov [rcx + 56], rdx
xor eax, eax
ret
global longjmp
longjmp:
xor rax, rax
cmp rdx, 1
adc rax, rdx
mov rbx, [rcx]
mov rbp, [rcx + 8]
mov r12, [rcx + 16]
mov r13, [rcx + 24]
mov r14, [rcx + 32]
mov r15, [rcx + 40]
mov rsp, [rcx + 48]
jmp [rcx + 56] |
libsrc/_DEVELOPMENT/arch/zx/misc/c/sccz80/zx_visit_wc_attr_callee.asm | jpoikela/z88dk | 640 | 8371 | ; void zx_visit_wc_attr(struct r_Rect8 *r, void *function)
SECTION code_clib
SECTION code_arch
PUBLIC zx_visit_wc_attr_callee
EXTERN asm_zx_visit_wc_attr
zx_visit_wc_attr_callee:
pop af
pop de
pop ix
push af
jp asm_zx_visit_wc_attr
|
CE3105/ASM3.asm | rafaellepalmos/Assembly_Language | 0 | 86384 | <filename>CE3105/ASM3.asm
data segment
entername DB 'Enter your name:$'
enterlast DB 'Enter your last name:$'
enterid DB 'Enter your ID number:$'
enterfac DB 'Enter your faculty:$'
name1 DB 'Name:$'
last db 'Last name:$'
id db 'ID:$'
fac db 'Faculty:$'
name2 DB 20d DUP ('$')
last2 DB 20d DUP ('$')
id2 DB 20d DUP ('$')
fac2 DB 20d DUP ('$')
nl DB 0ah,0dh,('$')
data ends
temp segment stack
db 200h dup(?)
temp ends
code segment
assume cs:code, ds:data, ss:temp
start: mov ax,data
mov ds,ax
mov ah,01h
int 21h
mov cl,al
mov ah,01h
int 21h
sub al,30h
add cl,al
mov dl,cl
mov ah,02h
int 21h
mov ax,4c00h
int 21h
code ends
end start |
Validation/pyFrame3DD-master/gcc-master/gcc/ada/libgnarl/s-taskin.adb | djamal2727/Main-Bearing-Analytical-Model | 0 | 28623 | <filename>Validation/pyFrame3DD-master/gcc-master/gcc/ada/libgnarl/s-taskin.adb
------------------------------------------------------------------------------
-- --
-- GNAT RUN-TIME LIBRARY (GNARL) COMPONENTS --
-- --
-- S Y S T E M . T A S K I N G --
-- --
-- B o d y --
-- --
-- Copyright (C) 1992-2020, Free Software Foundation, Inc. --
-- --
-- GNARL is free software; you can redistribute it and/or modify it under --
-- terms of the GNU General Public License as published by the Free Soft- --
-- ware Foundation; either version 3, or (at your option) any later ver- --
-- sion. GNAT is distributed in the hope that it will be useful, but WITH- --
-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY --
-- or FITNESS FOR A PARTICULAR PURPOSE. --
-- --
-- As a special exception under Section 7 of GPL version 3, you are granted --
-- additional permissions described in the GCC Runtime Library Exception, --
-- version 3.1, as published by the Free Software Foundation. --
-- --
-- You should have received a copy of the GNU General Public License and --
-- a copy of the GCC Runtime Library Exception along with this program; --
-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see --
-- <http://www.gnu.org/licenses/>. --
-- --
-- GNARL was developed by the GNARL team at Florida State University. --
-- Extensive contributions were provided by Ada Core Technologies, Inc. --
-- --
------------------------------------------------------------------------------
with System.Task_Primitives.Operations;
with System.Storage_Elements;
package body System.Tasking is
package STPO renames System.Task_Primitives.Operations;
---------------------
-- Detect_Blocking --
---------------------
function Detect_Blocking return Boolean is
GL_Detect_Blocking : Integer;
pragma Import (C, GL_Detect_Blocking, "__gl_detect_blocking");
-- Global variable exported by the binder generated file. A value equal
-- to 1 indicates that pragma Detect_Blocking is active, while 0 is used
-- for the pragma not being present.
begin
return GL_Detect_Blocking = 1;
end Detect_Blocking;
-----------------------
-- Number_Of_Entries --
-----------------------
function Number_Of_Entries (Self_Id : Task_Id) return Entry_Index is
begin
return Entry_Index (Self_Id.Entry_Num);
end Number_Of_Entries;
----------
-- Self --
----------
function Self return Task_Id renames STPO.Self;
------------------
-- Storage_Size --
------------------
function Storage_Size (T : Task_Id) return System.Parameters.Size_Type is
begin
return
System.Parameters.Size_Type
(T.Common.Compiler_Data.Pri_Stack_Info.Size);
end Storage_Size;
---------------------
-- Initialize_ATCB --
---------------------
procedure Initialize_ATCB
(Self_ID : Task_Id;
Task_Entry_Point : Task_Procedure_Access;
Task_Arg : System.Address;
Parent : Task_Id;
Elaborated : Access_Boolean;
Base_Priority : System.Any_Priority;
Base_CPU : System.Multiprocessors.CPU_Range;
Domain : Dispatching_Domain_Access;
Task_Info : System.Task_Info.Task_Info_Type;
Stack_Size : System.Parameters.Size_Type;
T : Task_Id;
Success : out Boolean)
is
begin
T.Common.State := Unactivated;
-- Initialize T.Common.LL
STPO.Initialize_TCB (T, Success);
if not Success then
return;
end if;
-- Note that use of an aggregate here for this assignment
-- would be illegal, because Common_ATCB is limited because
-- Task_Primitives.Private_Data is limited.
T.Common.Parent := Parent;
T.Common.Base_Priority := Base_Priority;
T.Common.Base_CPU := Base_CPU;
-- The Domain defaults to that of the activator. But that can be null in
-- the case of foreign threads (see Register_Foreign_Thread), in which
-- case we default to the System_Domain.
if Domain /= null then
T.Common.Domain := Domain;
elsif Self_ID.Common.Domain /= null then
T.Common.Domain := Self_ID.Common.Domain;
else
T.Common.Domain := System_Domain;
end if;
pragma Assert (T.Common.Domain /= null);
T.Common.Current_Priority := 0;
T.Common.Protected_Action_Nesting := 0;
T.Common.Call := null;
T.Common.Task_Arg := Task_Arg;
T.Common.Task_Entry_Point := Task_Entry_Point;
T.Common.Activator := Self_ID;
T.Common.Wait_Count := 0;
T.Common.Elaborated := Elaborated;
T.Common.Activation_Failed := False;
T.Common.Task_Info := Task_Info;
T.Common.Global_Task_Lock_Nesting := 0;
T.Common.Fall_Back_Handler := null;
T.Common.Specific_Handler := null;
T.Common.Debug_Events := (others => False);
T.Common.Task_Image_Len := 0;
if T.Common.Parent = null then
-- For the environment task, the adjusted stack size is meaningless.
-- For example, an unspecified Stack_Size means that the stack size
-- is determined by the environment, or can grow dynamically. The
-- Stack_Checking algorithm therefore needs to use the requested
-- size, or 0 in case of an unknown size.
T.Common.Compiler_Data.Pri_Stack_Info.Size :=
Storage_Elements.Storage_Offset (Stack_Size);
else
T.Common.Compiler_Data.Pri_Stack_Info.Size :=
Storage_Elements.Storage_Offset
(Parameters.Adjust_Storage_Size (Stack_Size));
end if;
-- Link the task into the list of all tasks
T.Common.All_Tasks_Link := All_Tasks_List;
All_Tasks_List := T;
end Initialize_ATCB;
----------------
-- Initialize --
----------------
Main_Task_Image : constant String := "main_task";
-- Image of environment task
Main_Priority : Integer;
pragma Import (C, Main_Priority, "__gl_main_priority");
-- Priority for main task. Note that this is of type Integer, not Priority,
-- because we use the value -1 to indicate the default main priority, and
-- that is of course not in Priority'range.
Main_CPU : Integer;
pragma Import (C, Main_CPU, "__gl_main_cpu");
-- Affinity for main task. Note that this is of type Integer, not
-- CPU_Range, because we use the value -1 to indicate the unassigned
-- affinity, and that is of course not in CPU_Range'Range.
Initialized : Boolean := False;
-- Used to prevent multiple calls to Initialize
procedure Initialize is
T : Task_Id;
Base_Priority : Any_Priority;
Base_CPU : System.Multiprocessors.CPU_Range;
Success : Boolean;
use type System.Multiprocessors.CPU_Range;
begin
if Initialized then
return;
end if;
Initialized := True;
-- Initialize Environment Task
Base_Priority :=
(if Main_Priority = Unspecified_Priority
then Default_Priority
else Priority (Main_Priority));
Base_CPU :=
(if Main_CPU = Unspecified_CPU
then System.Multiprocessors.Not_A_Specific_CPU
else System.Multiprocessors.CPU_Range (Main_CPU));
-- At program start-up the environment task is allocated to the default
-- system dispatching domain.
-- Make sure that the processors which are not available are not taken
-- into account. Use Number_Of_CPUs to know the exact number of
-- processors in the system at execution time.
System_Domain :=
new Dispatching_Domain'
(Multiprocessors.CPU'First .. Multiprocessors.Number_Of_CPUs =>
True);
T := STPO.New_ATCB (0);
Initialize_ATCB
(Self_ID => null,
Task_Entry_Point => null,
Task_Arg => Null_Address,
Parent => Null_Task,
Elaborated => null,
Base_Priority => Base_Priority,
Base_CPU => Base_CPU,
Domain => System_Domain,
Task_Info => Task_Info.Unspecified_Task_Info,
Stack_Size => 0,
T => T,
Success => Success);
pragma Assert (Success);
STPO.Initialize (T);
STPO.Set_Priority (T, T.Common.Base_Priority);
T.Common.State := Runnable;
T.Common.Task_Image_Len := Main_Task_Image'Length;
T.Common.Task_Image (Main_Task_Image'Range) := Main_Task_Image;
Dispatching_Domain_Tasks :=
new Array_Allocated_Tasks'
(Multiprocessors.CPU'First .. Multiprocessors.Number_Of_CPUs => 0);
-- Signal that this task is being allocated to a processor
if Base_CPU /= System.Multiprocessors.Not_A_Specific_CPU then
-- Increase the number of tasks attached to the CPU to which this
-- task is allocated.
Dispatching_Domain_Tasks (Base_CPU) :=
Dispatching_Domain_Tasks (Base_CPU) + 1;
end if;
-- The full initialization of the environment task's Entry_Calls array
-- is deferred to Init_RTS because only the first element of the array
-- is used by the restricted Ravenscar runtime.
T.Entry_Calls (T.Entry_Calls'First).Self := T;
T.Entry_Calls (T.Entry_Calls'First).Level := T.Entry_Calls'First;
end Initialize;
end System.Tasking;
|
programs/oeis/081/A081490.asm | karttu/loda | 0 | 89769 | <gh_stars>0
; A081490: Leading term of n-th row of A081491.
; 1,2,4,9,19,36,62,99,149,214,296,397,519,664,834,1031,1257,1514,1804,2129,2491,2892,3334,3819,4349,4926,5552,6229,6959,7744,8586,9487,10449,11474,12564,13721,14947,16244,17614,19059,20581,22182,23864,25629
mov $2,$0
mul $2,2
bin $2,3
mov $3,$2
div $3,4
add $0,$3
mov $1,$0
add $1,1
|
processor/processor-eagle_mem_ref_p.adb | SMerrony/dgemua | 2 | 14265 | <filename>processor/processor-eagle_mem_ref_p.adb
-- MIT License
-- Copyright (c) 2021 <NAME>
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
with Ada.Text_IO; use Ada.Text_IO;
with Debug_Logs; use Debug_Logs;
with Resolver; use Resolver;
package body Processor.Eagle_Mem_Ref_P is
procedure Do_Eagle_Mem_Ref (I : in Decoded_Instr_T; CPU : in out CPU_T) is
Addr : Phys_Addr_T;
Word : Word_T;
S64,
S64_Mem,
S64_Ac : Integer_64;
I32 : Integer_32;
I16_Ac, I16_Mem : Integer_16;
DW : Dword_T;
Low_Byte: Boolean;
procedure Set_OVR (New_OVR : in Boolean) is
begin
if New_OVR then
Set_W_Bit(CPU.PSR, 1);
else
Clear_W_Bit(CPU.PSR, 1);
end if;
end Set_OVR;
begin
case I.Instruction is
when I_LLDB =>
DW := Shift_Right(Dword_T(I.Disp_32), 1);
Addr := Resolve_31bit_Disp (CPU, false, I.Mode, Dword_To_Integer_32(DW), I.Disp_Offset);
Low_Byte := Test_DW_Bit (Dword_T(I.Disp_32), 31);
CPU.AC(I.Ac) := Dword_T(RAM.Read_Byte(Addr, Low_Byte));
when I_LLEF =>
CPU.AC(I.Ac) := Dword_T(Resolve_31bit_Disp (CPU, I.Ind, I.Mode, I.Disp_31, I.Disp_Offset));
when I_LLEFB =>
DW := Shift_Right(Dword_T(I.Disp_32), 1);
if Test_DW_Bit (Dword_T(I.Disp_32), 0) then
DW := DW or 16#8000_0000#;
end if;
I32 := Dword_To_Integer_32(DW);
Addr := Shift_Left(Resolve_31bit_Disp (CPU, false, I.Mode, I32, I.Disp_Offset), 1);
if Test_DW_Bit (Dword_T(I.Disp_32), 31) then
Addr := Addr or 1;
end if;
CPU.AC(I.Ac) := Dword_T(Addr);
when I_LNADI =>
Addr := Resolve_31bit_Disp (CPU, I.Ind, I.Mode, I.Disp_31, I.Disp_Offset);
Word := RAM.Read_Word (Addr);
Word := Word + Word_T(I.Imm_U16);
RAM.Write_Word (Addr, Word);
when I_LNADD =>
Addr := Resolve_31bit_Disp (CPU, I.Ind, I.Mode, I.Disp_31, I.Disp_Offset);
I32 := Integer_32(Word_To_Integer_16(RAM.Read_Word(Addr))) +
Integer_32(Word_To_Integer_16(DG_Types.Lower_Word(CPU.AC(I.Ac))));
CPU.Carry := (I32 > Max_Pos_S16) or (I32 < Min_Neg_S16);
Set_OVR (CPU.Carry);
CPU.AC(I.Ac) := Integer_32_To_Dword(I32);
when I_LNLDA =>
Addr := Resolve_31bit_Disp (CPU, I.Ind, I.Mode, I.Disp_31, I.Disp_Offset);
CPU.AC(I.Ac) := Sext_Word_To_Dword (RAM.Read_Word(Addr));
when I_LNSBI =>
Addr := Resolve_31bit_Disp (CPU, I.Ind, I.Mode, I.Disp_31, I.Disp_Offset);
Word := RAM.Read_Word (Addr);
Word := Word - Word_T(I.Imm_U16);
RAM.Write_Word (Addr, Word);
when I_LNSTA =>
Addr := Resolve_31bit_Disp (CPU, I.Ind, I.Mode, I.Disp_31, I.Disp_Offset);
RAM.Write_Word (Addr, DG_Types.Lower_Word(CPU.AC(I.Ac)));
when I_LSTB =>
DW := Shift_Right(Dword_T(I.Disp_32), 1);
Addr := Resolve_31bit_Disp (CPU, false, I.Mode, Dword_To_Integer_32(DW), I.Disp_Offset);
Low_Byte := Test_DW_Bit(Dword_T(I.Disp_32), 31);
RAM.Write_Byte(Addr, Low_Byte, Byte_T(CPU.AC(I.Ac)));
when I_LWADD =>
Addr := Resolve_31bit_Disp (CPU, I.Ind, I.Mode, I.Disp_31, I.Disp_Offset);
S64 := Integer_64(Dword_To_Integer_32(RAM.Read_Dword(Addr))) + Integer_64(Dword_To_Integer_32(CPU.AC(I.Ac)));
if S64 < Min_Neg_S32 or S64 > Max_Pos_S32 then
Set_OVR (true);
end if;
CPU.AC(I.Ac) := Lower_Dword(Qword_T(Integer_64_To_Unsigned_64(S64)));
when I_LWLDA =>
Addr := Resolve_31bit_Disp (CPU, I.Ind, I.Mode, I.Disp_31, I.Disp_Offset);
CPU.AC(I.Ac) := RAM.Read_Dword (Addr);
when I_LWMUL =>
Addr := Resolve_31bit_Disp (CPU, I.Ind, I.Mode, I.Disp_31, I.Disp_Offset);
S64 := Integer_64(Dword_To_Integer_32(RAM.Read_Dword(Addr))) * Integer_64(Dword_To_Integer_32(CPU.AC(I.Ac)));
if S64 < Min_Neg_S32 or S64 > Max_Pos_S32 then
Set_OVR (true);
end if;
CPU.AC(I.Ac) := Lower_Dword(Qword_T(Integer_64_To_Unsigned_64(S64)));
when I_LWSTA =>
Addr := Resolve_31bit_Disp (CPU, I.Ind, I.Mode, I.Disp_31, I.Disp_Offset);
RAM.Write_Dword (Addr, CPU.AC(I.Ac));
when I_LWSUB =>
Addr := Resolve_31bit_Disp (CPU, I.Ind, I.Mode, I.Disp_31, I.Disp_Offset);
I32 := Dword_To_Integer_32(CPU.AC(I.Ac)) - Dword_To_Integer_32(RAM.Read_Dword(Addr));
CPU.AC(I.Ac) := Integer_32_To_Dword(I32);
when I_WBLM =>
-- AC0 - unused, AC1 - no. wds to move (if neg then descending order), AC2 - src, AC3 - dest
while CPU.AC(1) /= 0 loop
RAM.Write_Word(Phys_Addr_T(CPU.AC(3)),
RAM.Read_Word (Phys_Addr_T(CPU.AC(2))));
if Test_DW_Bit (CPU.AC(1), 0) then
CPU.AC(1) := CPU.AC(1) + 1;
CPU.AC(2) := CPU.AC(2) - 1;
CPU.AC(3) := CPU.AC(3) - 1;
else
CPU.AC(1) := CPU.AC(1) - 1;
CPU.AC(2) := CPU.AC(2) + 1;
CPU.AC(3) := CPU.AC(3) + 1;
end if;
end loop;
when I_WBTO | I_WBTZ =>
declare
Offset : Phys_Addr_T := Phys_Addr_T(Shift_Right(CPU.AC(I.Acd), 4));
Bit_Num : Integer := Integer(CPU.AC(I.Acd) and 16#0000_000f#);
begin
if I.Acs = I.Acd then
Addr := CPU.PC and 16#7000_0000#;
else
Addr := Resolve_32bit_Indirectable_Addr(CPU.ATU, CPU.AC(I.Acs));
end if;
Word := RAM.Read_Word (Addr + Offset);
if I.Instruction = I_WBTO then
Set_W_Bit (Word, Bit_Num);
else
Clear_W_Bit (Word, Bit_Num);
end if;
RAM.Write_Word (Addr + Offset, Word);
end;
when I_WCMP =>
declare
Str1_Dir, Str2_Dir : Integer_32;
Str1_Char, Str2_Char : Byte_T;
function Get_Dir(AC : in Dword_T) return Integer_32 is
begin
if AC = 0 then return 0; end if;
if Test_DW_Bit (AC, 0) then
return -1;
else
return 1;
end if;
end Get_Dir;
begin
Str1_Dir := Get_Dir(CPU.AC(1));
Str2_Dir := Get_Dir(CPU.AC(0));
if (Str1_Dir = 0) and (Str2_Dir = 0) then
Loggers.Debug_Print (Debug_Log, "WARNING: WCMP called with 2 zero lengths not doing anything");
else
while (CPU.AC(1) /= 0) and (CPU.AC(0) /= 0) loop
Loggers.Debug_Print (Debug_Log, "... AC0:" & CPU.AC(0)'Image & " AC1:" & CPU.AC(1)'Image);
-- read the two bytes to compare, substitute with a space if one string has run out
if CPU.AC(1) /= 0 then
Str1_Char := RAM.Read_Byte_BA (CPU.AC(3));
else
Str1_Char := 32;
end if;
if CPU.AC(0) /= 0 then
Str2_Char := RAM.Read_Byte_BA (CPU.AC(2));
else
Str2_Char := 32;
end if;
Loggers.Debug_Print (Debug_Log, "... Comparing " & Str1_Char'Image & " and " & Str2_Char'Image);
-- compare
if Str1_Char < Str2_Char then
CPU.AC(1) := 16#ffff_ffff#;
exit;
end if;
if Str1_Char > Str2_Char then
CPU.AC(1) := 1;
exit;
end if;
-- they were equal, so adjust remaining lengths, move pointers, and loop round
if Str2_Dir < 0 then
CPU.AC(2) := CPU.AC(2) - 1;
if CPU.AC(0) /= 0 then
CPU.AC(0) := CPU.AC(0) + 1;
end if;
else
CPU.AC(2) := CPU.AC(2) + 1;
if CPU.AC(0) /= 0 then
CPU.AC(0) := CPU.AC(0) - 1;
end if;
end if;
if Str1_Dir < 0 then
CPU.AC(3) := CPU.AC(3) - 1;
if CPU.AC(1) /= 0 then
CPU.AC(1) := CPU.AC(1) + 1;
end if;
else
CPU.AC(3) := CPU.AC(3) + 1;
if CPU.AC(1) /= 0 then
CPU.AC(1) := CPU.AC(1) - 1;
end if;
end if;
end loop;
end if;
end;
when I_WCMV =>
declare
Dest_Ascend, Src_Ascend : Boolean;
Dest_Cnt, Src_Cnt : Integer_32;
begin
Dest_Cnt := Dword_To_Integer_32(CPU.AC(0));
if Dest_Cnt = 0 then
Loggers.Debug_Print (Debug_Log, "WARNING: WCMV called with AC0 = 0, not moving anything");
CPU.Carry := false;
else
Dest_Ascend := Dest_Cnt > 0;
Src_Cnt := Dword_To_Integer_32(CPU.AC(1));
Src_Ascend := Src_Cnt > 0;
Loggers.Debug_Print (Debug_Log, "... Source Count:" & Src_Cnt'Image & "., Dest. Count:" & Dest_Cnt'Image);
CPU.Carry := (Abs Src_Cnt) > (Abs Dest_Cnt);
-- move Src_Cnt bytes
loop
Loggers.Debug_Print (Debug_Log, "... Copy from: " & Dword_To_String (CPU.AC(3),Octal,11,true) &
" to: " & Dword_To_String (CPU.AC(2),Octal,11,true) &
" remaining Src:" & Src_Cnt'Image & "., Dest:" & Dest_Cnt'Image);
RAM.Copy_Byte_BA(CPU.AC(3),CPU.AC(2));
if Src_Ascend then
CPU.AC(3) := CPU.AC(3) + 1;
Src_Cnt := Src_Cnt - 1;
else
CPU.AC(3) := CPU.AC(3) - 1;
Src_Cnt := Src_Cnt + 1;
end if;
if Dest_Ascend then
CPU.AC(2) := CPU.AC(2) + 1;
Dest_Cnt := Dest_Cnt - 1;
else
CPU.AC(2) := CPU.AC(2) - 1;
Dest_Cnt := Dest_Cnt + 1;
end if;
exit when (Src_Cnt = 0) or (Dest_Cnt = 0);
end loop;
-- now fill any excess bytes with ASCII spaces
while Dest_Cnt /= 0 loop
RAM.Write_Byte_BA(CPU.AC(2), 32);
if Dest_Ascend then
CPU.AC(2) := CPU.AC(2) + 1;
Dest_Cnt := Dest_Cnt - 1;
else
CPU.AC(2) := CPU.AC(2) - 1;
Dest_Cnt := Dest_Cnt + 1;
end if;
end loop;
CPU.AC(0) := 0;
CPU.AC(1) := Dword_T(Src_Cnt);
end if;
end;
when I_WCST =>
declare
Delim_Tab_Addr : Phys_Addr_T;
type Delim_Tab_T is array (Byte_T range 0 .. 255) of Boolean;
Delim_Tab : Delim_Tab_T;
Wd : Word_T;
Src_Len : Integer_32 := Dword_To_Integer_32(CPU.AC(1));
Char_Ix : Integer_32 := 0;
Ascending : Boolean := (Src_Len > 0);
Char_Val : Byte_T;
begin
if CPU.AC(1) = 0 then
Loggers.Debug_Print (Debug_Log, "WARNING: WCST called with AC1 = 0, not scanning anything");
else
Delim_Tab_Addr := Resolve_32bit_Indirectable_Addr (CPU.ATU, CPU.AC(0));
CPU.AC(0) := Dword_T(Delim_Tab_Addr);
-- load the table which is 256 bits stored as 16 words
for T_Ix in 0 .. 15 loop
Wd := RAM.Read_Word (Delim_Tab_Addr + Phys_Addr_T(T_Ix));
for Bit in 0 .. 15 loop
Delim_Tab(Byte_T((T_Ix * 16) + Bit)) := Test_W_Bit (Wd, Bit);
end loop;
Loggers.Debug_Print (Debug_Log, "... Delim. Tab. " & Word_To_String(Wd, Binary, 16, true));
end loop;
if Ascending then
while Char_Ix < Src_Len loop
Char_Val := RAM.Read_Byte_BA(CPU.AC(3) + Dword_T(Char_Ix));
Char_Ix := Char_Ix + 1;
exit when Delim_Tab(Char_Val);
end loop;
CPU.AC(1) := Integer_32_To_Dword(Char_Ix);
CPU.AC(3) := CPU.AC(3) + Dword_T(Char_Ix);
else
raise Not_Yet_Implemented;
end if;
end if;
end;
when I_WCTR =>
declare
Trans_Tab_Addr : Phys_Addr_T;
type Trans_Tab_T is array (0 .. 255) of Byte_T;
Trans_Tab : Trans_Tab_T;
Src_Byte, Trans_Byte, Str2_Byte, Trans2_Byte : Byte_T;
begin
if CPU.AC(1) = 0 then
Loggers.Debug_Print (Debug_Log, "WARNING: WCTR called with AC1 = 0, not translating anything");
else
Trans_Tab_Addr := Shift_Left(Resolve_32bit_Indirectable_Addr (CPU.ATU, CPU.AC(0)),1);
for C in 0 .. 255 loop
Trans_Tab(C) := RAM.Read_Byte_BA (Dword_T(Trans_Tab_Addr) + Dword_T(C));
end loop;
while CPU.AC(1) /= 0 loop
Src_Byte := RAM.Read_Byte_BA (CPU.AC(3));
CPU.AC(3) := CPU.AC(3) + 1;
Trans_Byte := Trans_Tab(Integer(Src_Byte));
if Test_DW_Bit (CPU.AC(1), 0) then
-- move mode
RAM.Write_Byte_BA(CPU.AC(2), Trans_Byte);
CPU.AC(2) := CPU.AC(2) + 1;
CPU.AC(1) := CPU.AC(1) + 1;
else
-- compare mode
Str2_Byte := RAM.Read_Byte_BA (CPU.AC(2));
CPU.AC(2) := CPU.AC(2) + 1;
Trans2_Byte := Trans_Tab(Integer(Str2_Byte));
if Src_Byte < Trans2_Byte then
CPU.AC(1) := 16#ffff_ffff#;
exit;
elsif Src_Byte > Trans2_Byte then
CPU.AC(1) := CPU.AC(1) + 1;
exit;
end if;
CPU.AC(1) := CPU.AC(1) - 1;
end if;
end loop;
end if;
end;
when I_WLDB =>
CPU.AC(I.Acd) := Dword_T(RAM.Read_Byte_BA(CPU.AC(I.Acs)));
when I_WSTB =>
RAM.Write_Byte_BA (CPU.AC(I.Acs), Byte_T(CPU.AC(I.Acd) and 16#00ff#));
when I_XLDB =>
Addr := Resolve_15bit_Disp (CPU, false, I.Mode, I.Disp_15, I.Disp_Offset); -- TODO 'Long' resolve???
CPU.AC(I.Ac) := Dword_T(RAM.Read_Byte(Addr, I.Low_Byte));
when I_XLEF =>
Addr := Resolve_15bit_Disp (CPU, I.Ind, I.Mode, I.Disp_15, I.Disp_Offset);
Loggers.Debug_Print (Debug_Log, "... Addr resolved to: " & Dword_To_String(Dword_T(Addr), Octal, 11));
Loggers.Debug_Print (Debug_Log, "... from Disp_15: " & Int_To_String( Integer(I.Disp_15), Octal, 11) &
" Offset: " & Int_To_String( Integer(I.Disp_Offset), Octal, 11));
CPU.AC(I.Ac) := Dword_T(Addr);
when I_XLEFB =>
Addr := Resolve_15bit_Disp (CPU, false, I.Mode, I.Disp_15, I.Disp_Offset);
Addr := Shift_Left (Addr, 1);
if I.Low_Byte then
Addr := Addr + 1;
end if;
CPU.AC(I.Ac) := Dword_T(Addr); -- FIXME constrain to Ring? or in Resolve?
when I_XNADD =>
Addr := Resolve_15bit_Disp (CPU, I.Ind, I.Mode, I.Disp_15, I.Disp_Offset);
I16_Mem := Word_To_Integer_16(RAM.Read_Word(Addr));
I16_Ac := Word_To_Integer_16(DG_Types.Lower_Word(CPU.AC(I.Ac)));
I16_Ac := I16_Ac + I16_Mem;
I32 := Integer_32(I16_Ac) + Integer_32(I16_Mem);
if (I32 > Max_Pos_S16) or (I32 < Min_Neg_S16) then
CPU.Carry := true;
Set_OVR (true);
end if;
CPU.AC(I.Ac) := Integer_32_To_Dword(Integer_32(I16_Ac));
when I_XNADI =>
Addr := Resolve_15bit_Disp (CPU, I.Ind, I.Mode, I.Disp_15, I.Disp_Offset);
I32 := Integer_32(Word_To_Integer_16(RAM.Read_Word(Addr))) + Integer_32(I.Imm_U16);
if (I32 > Max_Pos_S16) or (I32 < Min_Neg_S16) then
CPU.Carry := true;
Set_OVR (true);
end if;
RAM.Write_Dword (Addr, Integer_32_To_Dword(I32) and 16#0000_ffff#);
when I_XNLDA =>
Addr := Resolve_15bit_Disp (CPU, I.Ind, I.Mode, I.Disp_15, I.Disp_Offset);
Word := RAM.Read_Word (Addr);
CPU.AC(I.Ac) := Dword_T(Word);
if Test_W_Bit (Word, 0) then
CPU.AC(I.Ac) := CPU.AC(I.Ac) or 16#ffff_0000#;
end if;
when I_XNMUL =>
Addr := Resolve_15bit_Disp (CPU, I.Ind, I.Mode, I.Disp_15, I.Disp_Offset);
I16_Mem := Word_To_Integer_16(RAM.Read_Word(Addr));
I16_Ac := Word_To_Integer_16(DG_Types.Lower_Word(CPU.AC(I.Ac)));
I16_Ac := I16_Ac * I16_Mem;
I32 := Integer_32(I16_Ac) * Integer_32(I16_Mem);
if (I32 > Max_Pos_S16) or (I32 < Min_Neg_S16) then
CPU.Carry := true;
Set_OVR (true);
end if;
CPU.AC(I.Ac) := Integer_32_To_Dword(Integer_32(I16_Ac));
when I_XNSBI =>
Addr := Resolve_15bit_Disp (CPU, I.Ind, I.Mode, I.Disp_15, I.Disp_Offset);
I32 := Integer_32(Word_To_Integer_16(RAM.Read_Word(Addr))) - Integer_32(I.Imm_U16);
if (I32 > Max_Pos_S16) or (I32 < Min_Neg_S16) then
CPU.Carry := true;
Set_OVR (true);
end if;
RAM.Write_Word (Addr, Word_T(I32));
when I_XNSTA =>
Addr := Resolve_15bit_Disp (CPU, I.Ind, I.Mode, I.Disp_15, I.Disp_Offset);
RAM.Write_Word (Addr, DG_Types.Lower_Word(CPU.AC(I.Ac)));
when I_XSTB =>
Addr := Resolve_15bit_Disp (CPU, false, I.Mode, I.Disp_15, I.Disp_Offset); -- TODO 'Long' resolve???
RAM.Write_Byte (Word_Addr => Addr,
Low_Byte => I.Low_Byte,
Byt => Byte_T(CPU.AC(I.Ac) and 16#0000_00ff#));
when I_XNSUB =>
Addr := Resolve_15bit_Disp (CPU, I.Ind, I.Mode, I.Disp_15, I.Disp_Offset);
I16_Mem := Word_To_Integer_16(RAM.Read_Word(Addr));
I16_Ac := Word_To_Integer_16(DG_Types.Lower_Word(CPU.AC(I.Ac)));
I16_Ac := I16_Ac - I16_Mem;
I32 := Integer_32(I16_Ac) - Integer_32(I16_Mem);
if (I32 > Max_Pos_S16) or (I32 < Min_Neg_S16) then
CPU.Carry := true;
Set_OVR (true);
end if;
CPU.AC(I.Ac) := Integer_32_To_Dword(Integer_32(I16_Ac));
when I_XWADD =>
Addr := Resolve_15bit_Disp (CPU, I.Ind, I.Mode, I.Disp_15, I.Disp_Offset);
S64_Mem := Integer_64(Dword_To_Integer_32(RAM.Read_Dword(Addr)));
S64_Ac := Integer_64(Dword_To_Integer_32(CPU.AC(I.Ac)));
S64 := S64_Ac + S64_Mem;
if (S64 > Max_Pos_S32) or (S64 < Min_Neg_S32) then
CPU.Carry := true;
Set_OVR (true);
end if;
CPU.Ac(I.Ac) := Dword_T(Integer_64_To_Unsigned_64(S64)and 16#0000_0000_ffff_ffff#);
when I_XWADI =>
Addr := Resolve_15bit_Disp (CPU, I.Ind, I.Mode, I.Disp_15, I.Disp_Offset);
S64 := Integer_64(Dword_To_Integer_32(RAM.Read_Dword(Addr))) + Integer_64(I.Imm_U16);
if (S64 > Max_Pos_S32) or (S64 < Min_Neg_S32) then
CPU.Carry := true;
Set_OVR (true);
end if;
S64 := Integer_64(Integer_64_To_Unsigned_64(S64) and 16#0000_0000_ffff_ffff#);
RAM.Write_Dword (Addr, Dword_T(Integer_64_To_Unsigned_64(S64)));
when I_XWLDA =>
Addr := Resolve_15bit_Disp (CPU, I.Ind, I.Mode, I.Disp_15, I.Disp_Offset);
CPU.AC(I.Ac) := RAM.Read_Dword (Addr);
when I_XWMUL =>
Addr := Resolve_15bit_Disp (CPU, I.Ind, I.Mode, I.Disp_15, I.Disp_Offset);
S64_Mem := Integer_64(Dword_To_Integer_32(RAM.Read_Dword(Addr)));
S64_Ac := Integer_64(Dword_To_Integer_32(CPU.AC(I.Ac)));
S64 := S64_Ac * S64_Mem;
if (S64 > Max_Pos_S32) or (S64 < Min_Neg_S32) then
CPU.Carry := true;
Set_OVR (true);
end if;
CPU.Ac(I.Ac) := Dword_T(Integer_64_To_Unsigned_64(S64));
when I_XWSBI =>
Addr := Resolve_15bit_Disp (CPU, I.Ind, I.Mode, I.Disp_15, I.Disp_Offset);
S64 := Integer_64(Dword_To_Integer_32(RAM.Read_Dword(Addr))) - Integer_64(I.Imm_U16);
if (S64 > Max_Pos_S32) or (S64 < Min_Neg_S32) then
CPU.Carry := true;
Set_OVR (true);
end if;
S64 := Integer_64(Integer_64_To_Unsigned_64(S64) and 16#0000_0000_ffff_ffff#);
RAM.Write_Dword (Addr, Dword_T(Integer_64_To_Unsigned_64(S64)));
when I_XWSTA =>
Addr := Resolve_15bit_Disp (CPU, I.Ind, I.Mode, I.Disp_15, I.Disp_Offset);
RAM.Write_Dword (Addr, CPU.AC(I.Ac));
when I_XWSUB =>
Addr := Resolve_15bit_Disp (CPU, I.Ind, I.Mode, I.Disp_15, I.Disp_Offset);
S64_Mem := Integer_64(Dword_To_Integer_32(RAM.Read_Dword(Addr)));
S64_Ac := Integer_64(Dword_To_Integer_32(CPU.AC(I.Ac)));
S64 := S64_Ac - S64_Mem;
if (S64 > Max_Pos_S32) or (S64 < Min_Neg_S32) then
CPU.Carry := true;
Set_OVR (true);
end if;
CPU.Ac(I.Ac) := Dword_T(Integer_64_To_Unsigned_64(S64) and 16#0000_0000_ffff_ffff#);
when others =>
Put_Line ("ERROR: EAGLE_MEMREF instruction " & To_String(I.Mnemonic) &
" not yet implemented");
raise Execution_Failure with "ERROR: EAGLE_MEMREF instruction " & To_String(I.Mnemonic) &
" not yet implemented";
end case;
CPU.PC := CPU.PC + Phys_Addr_T(I.Instr_Len);
end Do_Eagle_Mem_Ref;
end Processor.Eagle_Mem_Ref_P; |
src/API/protypo-api-engine_values.ads | fintatarta/protypo | 0 | 23857 | <reponame>fintatarta/protypo
pragma Ada_2012;
limited with Protypo.Api.Engine_Values.Handlers;
package Protypo.Api.Engine_Values is
use Ada.Strings.Unbounded;
type Engine_Value_Class is
(
Void,
Int,
Real,
Text,
Array_Handler,
Record_Handler,
Ambivalent_Handler,
Function_Handler,
Reference_Handler,
Constant_Handler,
Iterator
);
subtype Scalar_Classes is Engine_Value_Class range Int .. Text;
subtype Numeric_Classes is Scalar_Classes range Int .. Real;
subtype Handler_Classes is Engine_Value_Class range Array_Handler .. Constant_Handler;
type Engine_Value (Class : Engine_Value_Class) is private;
Void_Value : constant Engine_Value;
subtype Integer_Value is Engine_Value (Int);
subtype Real_Value is Engine_Value (Real);
subtype String_Value is Engine_Value (Text);
subtype Array_Value is Engine_Value (Array_Handler);
subtype Record_Value is Engine_Value (Record_Handler);
subtype Ambivalent_Value is Engine_Value (Ambivalent_Handler);
subtype Iterator_Value is Engine_Value (Iterator);
subtype Function_Value is Engine_Value (Function_Handler);
subtype Reference_Value is Engine_Value (Reference_Handler);
subtype Constant_Value is Engine_Value (Constant_Handler);
subtype Handler_Value is Engine_Value
with Dynamic_Predicate => (Handler_Value.Class in Array_Handler .. Constant_Handler);
function Is_Scalar (X : Engine_Value) return Boolean
is (X.Class in Scalar_Classes);
function Is_Numeric (X : Engine_Value) return Boolean
is (X.Class in Numeric_Classes);
function Is_Handler (X : Engine_Value) return Boolean
is (X.Class in Handler_Classes);
function Mixed_Numeric (X, Y : Numeric_Classes) return Numeric_Classes
is (if X = Y then X else Real);
-- Function used in contracts. Return the highest common numeric
-- class between X and Y (Int if both are integers, Real otherwise)
function Compatible_Scalars (X, Y : Engine_Value) return Boolean
is ((X.Class = Text and Y.Class = Text) or (Is_Numeric (X) and Is_Numeric (Y)))
with Pre => Is_Scalar (X) and Is_Scalar (Y);
-- Function used in contract to express the fact that X and Y are
-- compatible, that is, they are both text or numeric.
function Identity (X : Engine_Value) return Engine_Value
is (X);
-- Strange this function, uh? Well, it is convenient to instantiate
-- generic wrapper packages. See, for example, Array_Wrappers
function "-" (X : Engine_Value) return Engine_Value
with Pre => Is_Numeric (X),
Post => X.Class = "-"'Result.Class;
function "not" (X : Engine_Value) return Integer_Value
with Pre => Is_Numeric (X);
function "mod" (X, Y : Integer_Value) return Integer_Value;
function "+" (Left, Right : Engine_Value) return Engine_Value
with
Pre =>
(Left.Class = Text and Right.Class = Text)
or (Is_Numeric (Left) and Is_Numeric (Right)),
Post =>
"+"'Result.Class = (if Is_Numeric (Left)
then
Mixed_Numeric (Left.Class, Right.Class)
else
Text);
function "-" (Left, Right : Engine_Value) return Engine_Value
with Pre => Is_Numeric (Left) and Is_Numeric (Right),
Post => "-"'Result.Class = Mixed_Numeric (Left.Class, Right.Class);
function "*" (Left, Right : Engine_Value) return Engine_Value
with Pre => Is_Numeric (Left) and Is_Numeric (Right),
Post => "*"'Result.Class = Mixed_Numeric (Left.Class, Right.Class);
function "/" (Left, Right : Engine_Value) return Engine_Value
with Pre => Is_Numeric (Left) and Is_Numeric (Right),
Post => "/"'Result.Class = Mixed_Numeric (Left.Class, Right.Class);
function "=" (Left, Right : Engine_Value) return Integer_Value
with Pre => Compatible_Scalars (Left, Right);
function "/=" (Left, Right : Engine_Value) return Integer_Value
with Pre => Compatible_Scalars (Left, Right);
function "<" (Left, Right : Engine_Value) return Integer_Value
with Pre => Compatible_Scalars (Left, Right);
function "<=" (Left, Right : Engine_Value) return Integer_Value
with Pre => Compatible_Scalars (Left, Right);
function ">" (Left, Right : Engine_Value) return Integer_Value
with Pre => Compatible_Scalars (Left, Right);
function ">=" (Left, Right : Engine_Value) return Integer_Value
with Pre => Compatible_Scalars (Left, Right);
function "and" (Left, Right : Integer_Value) return Integer_Value;
function "or" (Left, Right : Integer_Value) return Integer_Value;
function "xor" (Left, Right : Integer_Value) return Integer_Value;
function Create (Val : Integer) return Integer_Value;
function Create (Val : Float) return Real_Value;
function Create (Val : String) return String_Value;
function Create (Val : Unbounded_String) return String_Value;
function Create (Val : Boolean) return Integer_Value;
function Get_Integer (Val : Integer_Value) return Integer;
function Get_Integer (Val : Engine_Value; Default : Integer) return Integer;
function Get_Boolean (Val : Integer_Value) return Boolean;
function Get_Float (Val : Real_Value) return Float;
function Get_Float (Val : Engine_Value; Default : Float) return Float;
function Get_String (Val : String_Value) return String;
function Get_String (Val : Engine_Value; Default : String) return String;
private
-- type Engine_Value_Vector is range 1 .. 2;
type Engine_Value (Class : Engine_Value_Class) is
record
case Class is
when Void =>
null;
when Int =>
Int_Val : Integer;
when Real =>
Real_Val : Float;
when Text =>
Text_Val : Unbounded_String;
when Array_Handler =>
Array_Object : access Handlers.Array_Interface;
when Record_Handler =>
Record_Object : access Handlers.Record_Interface;
when Ambivalent_Handler =>
Ambivalent_Object : access Handlers.Ambivalent_Interface;
when Iterator =>
Iteration_Object : access Handlers.Iterator_Interface;
when Function_Handler =>
Function_Object : access Handlers.Function_Interface;
when Reference_Handler =>
Reference_Object : access Handlers.Reference_Interface;
when Constant_Handler =>
Constant_Object : access Handlers.Constant_Interface;
end case;
end record;
Void_Value : constant Engine_Value := (Class => Void);
function Bool (X : Integer) return Integer
is (if X /= 0 then 1 else 0);
function Bool (X : Float) return Integer
is (if X /= 0.0 then 1 else 0);
function Bool (X : Engine_Value) return Integer
is (case X.Class is
when Int => Bool (Get_Integer (X)),
when Real => Bool (Get_Float (X)),
when others => raise Constraint_Error);
function Real (X : Engine_Value) return Float
is (case X.Class is
when Int => Float (Get_Integer (X)),
when Real => Get_Float (X),
when others => raise Constraint_Error);
function Create (Val : Integer) return Integer_Value
is (Engine_Value'(Class => Int,
Int_Val => Val));
function Create (Val : Float) return Real_Value
is (Engine_Value'(Class => Real,
Real_Val => Val));
function Create (Val : String) return String_Value
is (Engine_Value'(Class => Text,
Text_Val => To_Unbounded_String (Val)));
function Create (Val : Unbounded_String) return String_Value
is (Create (To_String (Val)));
function Create (Val : Boolean) return Integer_Value
is (Engine_Value'(Class => Int,
Int_Val => (if Val then 1 else 0)));
function Get_Integer (Val : Integer_Value) return Integer
is (Val.Int_Val);
function Get_Integer (Val : Engine_Value; Default : Integer) return Integer
is (case Val.Class is
when Void =>
Default,
when Int =>
Val.Int_Val,
when others =>
raise Constraint_Error);
function Get_Float (Val : Real_Value) return Float
is (Val.Real_Val);
function Get_Float (Val : Engine_Value; Default : Float) return Float
is (case Val.Class is
when Void =>
Default,
when Int =>
Float (Val.Int_Val),
when Real =>
Val.Real_Val,
when others =>
raise Constraint_Error);
function Get_String (Val : String_Value) return String
is (To_String (Val.Text_Val));
function Get_String (Val : Engine_Value; Default : String) return String
is (case Val.Class is
when Void =>
Default,
when Text =>
Get_String (Val),
when others =>
raise Constraint_Error);
function Get_Boolean (Val : Integer_Value) return Boolean
is ((if Val.Int_Val = 0 then False else True));
function "-" (Left, Right : Engine_Value) return Engine_Value
is (Left + (-Right));
function "/=" (Left, Right : Engine_Value) return Integer_Value
is (not (Left = Right));
function ">" (Left, Right : Engine_Value) return Integer_Value
is (Right < Left);
function "<=" (Left, Right : Engine_Value) return Integer_Value
is (Right >= Left);
function ">=" (Left, Right : Engine_Value) return Integer_Value
is (not (Left < Right));
end Protypo.Api.Engine_Values;
|
arch/subr.asm | decagondev/CS_41_long | 0 | 96287 | <gh_stars>0
mov ax, 10
mov bx, 20
call add_bx_to_ax
mov bx, 123
hlt
add_bx_to_ax:
add ax, bx
ret |
Practica 03/P03_Ejercicio3/src/ejercicio3.adb | dpr1005/Tiempo-Real-Ejercicios | 0 | 14695 | with Ada.Text_IO; use Ada.Text_IO; with Ada.Integer_Text_IO;
procedure Ejercicio3 is
type Identificador is new Integer;
type Rep is new Integer;
task type Tarea_Original(IdTarea : Identificador; Rep : Integer);
task body Tarea_Original is
begin
for I in 1..Rep loop
Put_Line("Soy la tarea: " & IdTarea'Image);
end loop;
delay 0.01;
end Tarea_Original;
Tarea1 : Tarea_Original(1,1);
Tarea2 : Tarea_Original(2,2);
Tarea3 : Tarea_Original(3,3);
begin
null;
end Ejercicio3;
|
src/vn/ductt/verk/parser/SystemVerilogParser.g4 | bynoud/verk | 0 | 1141 | <filename>src/vn/ductt/verk/parser/SystemVerilogParser.g4
// Copyright (c) Microsoft Corporation. All rights reserved.
// Licensed under the MIT License.
//*******************************************************************/
//* Company: Microsoft Corporation */
//* Engineer: <NAME> */
//* */
//* Revision: */
//* Revision 0.1.0 - Internal Beta Release */
//* Revision 0.2.0 - ANTLR GitHub Release */
//* */
//* Additional Comments: */
//* */
//*******************************************************************/
parser grammar SystemVerilogParser;
options { tokenVocab=SystemVerilogLexer; }
// TODO
// + fix else if -> done for statement, need for generate
// + fix operator precedence
// + hier id get the last bit-select into it -> check if this file has same issue
module_keyword : Module_keyword_only | Macromodule ;
struct_keyword : Struct | UnionStruct ;
any_case_keyword : Case_keyword | Casez | Casex ;
semicolon : Semicolon
| Semicolon Semicolon
| Double_semicolon
;
//Operators
//polarity_operator : '+' | '-' ;
unary_operator : '+' | '-' | '!' | Tilde | '&' | '~&' | '|' | '~|' | '^' | '~^' | '^~' ;
//binary_operator : '+' | '-' | '*' | '/' | '%' | '==' | '!=' | '===' | '!==' | '&&' | '||' | '**' | '<' | '<=' | '>' | '>=' | '&' | '|' | '^' | '^~' | '~^' | '>>' | '<<' | '>>>' | '<<<' ;
// DT: change '<'/'>' to token
binary_operator : '+' | '-' | '*' | '/' | '%' | '==' | '!=' | '===' | '!==' | '&&' | '||' | '**' | '<' | '<=' | '>' | '>=' | '&' | '|' | '^' | '^~' | '~^' | '>>' | '<<' | '>>>' | '<<<' ;
//unary_module_path_operator : '!' | '~' | '&' | '~&' | '|' | '~|' | '^' | '~^' | '^~' ;
//binary_module_path_operator : '==' | '!=' | '&&' | '||' | '&' | '|' | '^' | '^~' | '~^' ;
unary_assign_operator : '++' | '--' ;
binary_assign_operator : '+=' | '-=' | '&=' | '|=' ;
//Source Text
source_text : description_star EOF ;
//Description
description_star : ( description )* ;
header_text : compiler_directive
| design_attribute
| import_package
;
design_attribute : attribute_instance ;
compiler_directive : timescale_compiler_directive
| default_nettype_statement
;
description : header_text
| package_declaration semicolon?
| module_declaration semicolon?
| function_declaration semicolon?
| enum_declaration semicolon?
| typedef_declaration semicolon?
;
/**********PARSER**********/
/**********MODULES**********/
module_declaration : attribute_instance_star
module_keyword module_identifier
module_interface
semicolon
module_item_star
Endmodule (colon_module_identifier)?
;
module_identifier : identifier ;
module_interface : (module_parameter_interface)? (module_port_interface)? ;
module_parameter_interface : Hash Open_parenthesis (list_of_interface_parameters)? Close_parenthesis ;
module_port_interface : Open_parenthesis (list_of_interface_ports)? Close_parenthesis ;
module_item_star : (module_item)*;
module_item : import_package
| parameter_item_semicolon
| attr_port_item_semicolon
//| variable_item
| attr_variable_item_semicolon
| subroutine_item_semicolon
| attr_construct_item
| attr_generated_instantiation
| attr_component_item
| compiler_item
| type_item
//| verification_item
;
colon_module_identifier : Colon module_identifier ;
/**********MODULES**********/
/**********PACKAGES**********/
package_declaration : attribute_instance_star
Package package_identifier semicolon
package_item_star
Endpackage (colon_package_identifier)?
;
package_identifier : identifier ;
colon_package_identifier : Colon package_identifier ;
package_item_star : (package_item)* ;
package_item : import_package
| parameter_item_semicolon
//| attr_port_item_semicolon
//| variable_item
| attr_variable_item_semicolon
| subroutine_item_semicolon
//| attr_construct_item
//| attr_generated_instantiation
| attr_component_item
| compiler_item
| type_item
//| verification_item
;
import_package : Import package_identifier Double_colon Star semicolon
| Import package_identifier Double_colon package_item_identifier semicolon
;
package_item_identifier : identifier ;
/**********PACKAGES**********/
/**********ITEMS**********/
parameter_item_semicolon : parameter_item semicolon ;
parameter_item : parameter_declaration
| local_parameter_declaration
| parameter_override
;
attr_port_item_semicolon : attribute_instance_star port_declaration semicolon ;
//attr_port_item_semicolon : attr_port_declaration_semicolon ;
attr_variable_item_semicolon : attribute_instance_star variable_item semicolon ;
variable_item : net_declaration
| reg_declaration
| logic_declaration
| bits_declaration
| integer_declaration
| int_declaration
| real_declaration
| time_declaration
| realtime_declaration
| event_declaration
| genvar_declaration
| usertype_variable_declaration
| string_declaration
| struct_declaration
| enum_declaration
;
subroutine_item_semicolon : subroutine_item semicolon? ;
subroutine_item : task_declaration
| function_declaration
;
attr_construct_item : attribute_instance_star construct_item ;
construct_item : continuous_assign
| initial_construct
| final_construct
| always_construct
;
attr_component_item : attribute_instance_star component_item ;
component_item : module_instantiation
| gate_instantiation
;
compiler_item : timescale_compiler_directive
| timeunit_directive semicolon
| timeprecision_directive semicolon
;
type_item : default_nettype_statement
| typedef_declaration semicolon
;
//verification_item : assertion_property_block
// | specify_block
// | specparam_declaration
// | property_block
// ;
null_item : semicolon ;
/**********ITEMS**********/
/**********PARAMETERS**********/
list_of_interface_parameters : list_of_parameter_declarations
| list_of_parameter_descriptions
;
list_of_parameter_declarations : parameter_declaration comma_parameter_declaration_star ;
comma_parameter_declaration_star : ( comma_parameter_declaration )*;
comma_parameter_declaration : Comma parameter_declaration ;
list_of_parameter_descriptions : list_of_variable_descriptions ;
param_declaration : (Signed | Unsigned)? (dimension_plus)? list_of_hierarchical_variable_descriptions ;
param_description : param_declaration
//| net_declaration
//| reg_declaration
| logic_declaration
//| bits_declaration
| integer_declaration
| int_declaration
| real_declaration
| time_declaration
| realtime_declaration
//| event_declaration
//| genvar_declaration
| usertype_variable_declaration
| string_declaration
//| struct_declaration
//| enum_declaration
;
parameter_declaration : Parameter param_description ;
local_parameter_declaration : Localparam param_description ;
parameter_override : Defparam param_description ;
/**********PARAMETERS**********/
/**********PORTS**********/
list_of_tf_interface_ports : list_of_port_identifiers
| list_of_tf_port_declarations
;
list_of_tf_port_declarations : list_of_tf_port_declarations_comma
| list_of_tf_port_declarations_semicolon
;
list_of_tf_port_declarations_comma : attr_tf_port_declaration comma_attr_tf_port_declaration_star ;
comma_attr_tf_port_declaration_star : ( comma_attr_tf_port_declaration )* ;
comma_attr_tf_port_declaration : Comma attr_tf_port_declaration ;
list_of_tf_port_declarations_semicolon : attr_tf_port_declaration_semicolon_plus ;
attr_tf_port_declaration_semicolon_plus : (attr_tf_port_declaration_semicolon)+ ;
attr_tf_port_declaration_semicolon_star : (attr_tf_port_declaration_semicolon)* ;
attr_tf_port_declaration_semicolon : attr_tf_port_declaration semicolon ;
attr_tf_port_declaration : attribute_instance_star tf_port_declaration ;
tf_port_declaration : inout_declaration
| input_declaration
| output_declaration
| ref_declaration
| tf_declaration
;
list_of_interface_ports : list_of_port_identifiers
| list_of_port_declarations
;
list_of_port_identifiers : port_identifier comma_port_identifier_star (Comma)?;
comma_port_identifier_star : ( comma_port_identifier )* ;
comma_port_identifier : Comma port_identifier ;
port_identifier : identifier ;
list_of_port_declarations : list_of_port_declarations_comma
| list_of_port_declarations_semicolon
;
list_of_port_declarations_comma : attr_port_declaration comma_attr_port_declaration_star ;
comma_attr_port_declaration_star : ( comma_attr_port_declaration )* ;
comma_attr_port_declaration : Comma attr_port_declaration ;
list_of_port_declarations_semicolon : attr_port_declaration_semicolon_plus ;
attr_port_declaration_semicolon_plus : (attr_port_declaration_semicolon)+ ;
attr_port_declaration_semicolon_star : (attr_port_declaration_semicolon)* ;
attr_port_declaration_semicolon : attr_port_declaration semicolon ;
attr_port_declaration : attribute_instance_star port_declaration ;
port_declaration : inout_declaration
| input_declaration
| output_declaration
| ref_declaration
//| tf_declaration
;
port_description : (Signed | Unsigned)? (dimension_plus)? list_of_variable_descriptions ;
inout_description : port_description
| net_declaration
;
input_description : port_description
| net_declaration
| reg_declaration
| logic_declaration
| bits_declaration
| int_declaration
| integer_declaration
| real_declaration
| time_declaration
| usertype_variable_declaration
| string_declaration
;
output_description : port_description
| net_declaration
| reg_declaration
| logic_declaration
| integer_declaration
| time_declaration
| usertype_variable_declaration
| string_declaration
;
ref_description : port_description
| net_declaration
| reg_declaration
| logic_declaration
| integer_declaration
| time_declaration
| usertype_variable_declaration
| string_declaration
;
tf_declaration : port_description
| real_declaration
| net_declaration
| reg_declaration
| logic_declaration
| bits_declaration
| int_declaration
| integer_declaration
| time_declaration
| usertype_variable_declaration
| string_declaration
;
inout_declaration : Inout inout_description ;
input_declaration : Input input_description ;
output_declaration : Output output_description ;
ref_declaration : Ref ref_description ;
/**********PORTS**********/
/**********DECLARATIONS**********/
user_type : user_type_identifer;
user_type_identifer : identifier ;
dimension_plus : ( dimension )+;
dimension_star : ( dimension )* ;
dimension : Left_bracket range_expression Right_bracket ;
range_expression : index_expression
| sb_range
| base_increment_range
| base_decrement_range
;
index_expression : expression
| Dollar
| Star
;
sb_range : base_expression Colon expression ;
base_increment_range : base_expression Plus_colon expression ;
base_decrement_range : base_expression Minus_colon expression ;
base_expression : expression ;
net_type : Supply0
| Supply1
| Tri
| Tri_and
| Tri_or
| Tri_reg
| Tri0
| Tri1
| Uwire
| Wire
| Wand
| Wor
| NONE
;
drive_strength : Open_parenthesis drive_strength_value_0 Comma drive_strength_value_1 Close_parenthesis ;
drive_strength_value_0 : strength0
| strength1
| highz0
| highz1
;
drive_strength_value_1 : strength0
| strength1
| highz0
| highz1
;
strength0 : Supply0
| Strong0
| Pull0
| Weak0
;
strength1 : Supply1
| Strong1
| Pull1
| Weak1
;
highz0 : Highz0 ;
highz1 : Highz1 ;
charge_strength : Open_parenthesis charge_size Close_parenthesis ;
charge_size : Small
| Medium
| Large
;
list_of_variable_descriptions : variable_description comma_variable_description_star ;
comma_variable_description_star : (comma_variable_description)* ;
comma_variable_description : Comma variable_description ;
variable_description : variable_identifier (dimension_plus)? ( Equal expression )? ;
variable_identifier : identifier ;
list_of_hierarchical_variable_descriptions : hierarchical_variable_description comma_hierarchical_variable_description_star ;
comma_hierarchical_variable_description_star : (comma_hierarchical_variable_description)* ;
comma_hierarchical_variable_description : Comma hierarchical_variable_description ;
hierarchical_variable_description : hierarchical_variable_identifier (dimension_plus)? ( Equal expression )? ;
hierarchical_variable_identifier : hierarchical_identifier ;
net_declaration : net_type (user_type)? (drive_strength)? (charge_strength)? (Vectored | Scalared)? (Signed | Unsigned)? (dimension_plus)? (delay)? list_of_variable_descriptions ;
reg_declaration : Reg (Signed | Unsigned)? (dimension_plus)? list_of_variable_descriptions ;
logic_declaration : Logic (Signed | Unsigned)? (dimension_plus)? list_of_variable_descriptions ;
bits_type : Bit
| Byte
;
bits_declaration : bits_type (Signed | Unsigned)? (dimension_plus)? list_of_variable_descriptions ;
integer_declaration : (Automatic)? Integer (Signed | Unsigned)? list_of_variable_descriptions ;
int_declaration : (Automatic | Static | Const)? Int (Signed | Unsigned)? list_of_variable_descriptions ;
real_declaration : Real list_of_variable_descriptions ;
time_declaration : Time list_of_variable_descriptions ;
realtime_declaration : Realtime list_of_variable_descriptions ;
event_declaration : Event_keyword list_of_variable_descriptions ;
genvar_declaration : Genvar list_of_variable_descriptions ;
usertype_variable_declaration : (Automatic)? user_type (dimension)? list_of_variable_descriptions ;
string_declaration : SVString list_of_variable_descriptions ;
struct_declaration : struct_type list_of_variable_descriptions ;
enum_declaration : enumerated_type list_of_variable_descriptions ;
/**********DECLARATIONS**********/
/**********FUNCTIONS**********/
function_declaration : Function (Automatic)? (Signed | Unsigned)? (function_type)? (dimension)? function_identifier
(function_interface)? semicolon
function_item_declaration_star function_statement
Endfunction (colon_function_identifier)?
;
function_type : Logic
| Integer
| Int
| Real
| Realtime
| Time
| Reg
| SVString
| bits_type
| user_type
;
function_identifier : identifier ;
function_interface : Open_parenthesis (list_of_tf_interface_ports)? Close_parenthesis ;
function_item_declaration_star : ( function_item_declaration_semicolon )* ;
function_item_declaration_semicolon : function_item_declaration semicolon ;
function_item_declaration : block_item_declaration
| port_declaration
;
function_statement : statement_star ;
colon_function_identifier : Colon function_identifier ;
/**********FUNCTIONS**********/
/**********TASKS**********/
task_declaration : Task (Automatic)? task_identifier
(task_interface)? semicolon
task_item_declaration_star task_statement
Endtask
;
task_identifier : identifier ;
task_interface : Open_parenthesis (list_of_tf_interface_ports)? Close_parenthesis ;
task_item_declaration_semicolon : task_item_declaration semicolon ;
task_item_declaration : block_item_declaration
| port_declaration
;
task_item_declaration_star : ( task_item_declaration_semicolon )* ;
task_statement : statement_star ;
/**********TASKS**********/
/**********STRUCTS**********/
struct_item_semicolon : struct_item semicolon ;
struct_item_star : (struct_item_semicolon)* ;
struct_item : logic_declaration
| bits_declaration
| int_declaration
| integer_declaration
| usertype_variable_declaration
| time_declaration
;
struct_type : struct_keyword (Packed)? Left_curly_bracket struct_item_star Right_curly_bracket ;
/**********STRUCTS**********/
/**********ENUM**********/
enum_type : Integer
| Logic
| bits_type
| Int
;
list_of_enum_items : enum_item comma_enum_item_star ;
enum_item : enum_identifier
| enum_identifier Equal expression
;
enum_identifier : identifier ;
comma_enum_item_star : (comma_enum_item)* ;
comma_enum_item : Comma enum_item ;
enumerated_type : Enum (enum_type)? (Signed | Unsigned)? (dimension)? Left_curly_bracket list_of_enum_items Right_curly_bracket ;
/**********ENUM**********/
/**********MODULE INST**********/
module_instantiation : module_identifier (parameter_interface_assignments)? list_of_module_instances semicolon ;
parameter_interface_assignments : Hash Open_parenthesis (list_of_interface_assignments)? Close_parenthesis ;
list_of_interface_assignments : list_of_ordered_interface_assignments
| list_of_named_interface_assignments
;
list_of_ordered_interface_assignments : ordered_interface_assignment comma_ordered_interface_assignment_star ;
comma_ordered_interface_assignment_star : (comma_ordered_interface_assignment)* ;
comma_ordered_interface_assignment : Comma (ordered_interface_assignment)? ;
ordered_interface_assignment : expression ;
list_of_named_interface_assignments : named_interface_assignment comma_named_interface_assignment_star ;
comma_named_interface_assignment_star : (comma_named_interface_assignment)* ;
comma_named_interface_assignment : Comma named_interface_assignment ;
named_interface_assignment : Dot identifier (Open_parenthesis (expression)? Close_parenthesis)?
| Dot Star;
list_of_module_instances : module_instance comma_module_instance_star ;
comma_module_instance_star : ( comma_module_instance )* ;
comma_module_instance : Comma module_instance ;
module_instance : module_instance_identifier (port_interface_assignments)? ;
module_instance_identifier : arrayed_identifier ;
arrayed_identifier : simple_arrayed_identifier | escaped_arrayed_identifier ;
simple_arrayed_identifier : Simple_identifier (dimension)? ;
escaped_arrayed_identifier : Escaped_identifier (dimension)? ;
port_interface_assignments : Open_parenthesis (list_of_interface_assignments)? Close_parenthesis ;
/**********MODULE INST**********/
/**********GATE INST**********/
delay : Hash delay_value
| Hash Open_parenthesis list_of_delay_values Close_parenthesis
;
list_of_delay_values : delay_value comma_delay_value_star ;
comma_delay_value_star : (comma_delay_value)* ;
comma_delay_value : Comma delay_value ;
delay_value : expression ;
pulldown_strength : Open_parenthesis strength0 Comma strength1 Close_parenthesis
| Open_parenthesis strength1 Comma strength0 Close_parenthesis
| Open_parenthesis strength0 Close_parenthesis
;
pullup_strength : Open_parenthesis strength0 Comma strength1 Close_parenthesis
| Open_parenthesis strength1 Comma strength0 Close_parenthesis
| Open_parenthesis strength1 Close_parenthesis
;
gate_instance_identifier : arrayed_identifier ;
gate_instantiation : cmos_instantiation
| mos_instantiation
| pass_instantiation
| pulldown_instantiation
| pullup_instantiation
| enable_instantiation
| n_input_instantiation
| n_output_instantiation
| pass_enable_instantiation
;
enable_gatetype : Bufif0 | Bufif1 | Notif0 | Notif1 ;
mos_switchtype : Nmos | Pmos | Rnmos | Rpmos ;
cmos_switchtype : Cmos | Rcmos ;
n_output_gatetype : Buf | Not ;
n_input_gatetype : And | Nand | Or | Nor | Xor | Xnor ;
pass_switchtype : Tran | Rtran ;
pass_enable_switchtype : Tranif0 | Tranif1 | Rtranif1 | Rtranif0 ;
pulldown_instantiation : Pulldown ( pulldown_strength )? list_of_pull_gate_instance semicolon ;
pullup_instantiation : Pullup ( pullup_strength )? list_of_pull_gate_instance semicolon ;
enable_instantiation : enable_gatetype ( drive_strength )? ( delay )? list_of_enable_gate_instance semicolon ;
mos_instantiation : mos_switchtype ( delay )? list_of_mos_switch_instance semicolon ;
cmos_instantiation : cmos_switchtype ( delay )? list_of_cmos_switch_instance semicolon ;
n_output_instantiation : n_output_gatetype ( drive_strength )? ( delay )? list_of_n_output_gate_instance semicolon ;
n_input_instantiation : n_input_gatetype ( drive_strength )? ( delay )? list_of_n_input_gate_instance semicolon ;
pass_instantiation : pass_switchtype list_of_pass_switch_instance semicolon ;
pass_enable_instantiation : pass_enable_switchtype ( delay )? list_of_pass_enable_switch_instance semicolon ;
list_of_pull_gate_instance : pull_gate_instance comma_pull_gate_instance_star ;
list_of_enable_gate_instance : enable_gate_instance comma_enable_gate_instance_star ;
list_of_mos_switch_instance : mos_switch_instance comma_mos_switch_instance_star ;
list_of_cmos_switch_instance : cmos_switch_instance comma_cmos_switch_instance_star ;
list_of_n_input_gate_instance : n_input_gate_instance comma_n_input_gate_instance_star ;
list_of_n_output_gate_instance : n_output_gate_instance comma_n_output_gate_instance_star ;
list_of_pass_switch_instance : pass_switch_instance comma_pass_switch_instance_star ;
list_of_pass_enable_switch_instance : pass_enable_switch_instance comma_pass_enable_switch_instance_star ;
comma_pull_gate_instance_star : (comma_pull_gate_instance)* ;
comma_enable_gate_instance_star : (comma_enable_gate_instance)* ;
comma_mos_switch_instance_star : (comma_mos_switch_instance)* ;
comma_cmos_switch_instance_star : (comma_cmos_switch_instance)* ;
comma_n_input_gate_instance_star : (comma_n_input_gate_instance)* ;
comma_n_output_gate_instance_star : (comma_n_output_gate_instance)* ;
comma_pass_switch_instance_star : (comma_pass_switch_instance)* ;
comma_pass_enable_switch_instance_star : (comma_pass_enable_switch_instance)* ;
comma_pull_gate_instance : Comma pull_gate_instance ;
comma_enable_gate_instance : Comma enable_gate_instance ;
comma_mos_switch_instance : Comma mos_switch_instance ;
comma_cmos_switch_instance : Comma cmos_switch_instance ;
comma_n_input_gate_instance : Comma n_input_gate_instance ;
comma_n_output_gate_instance : Comma n_output_gate_instance ;
comma_pass_switch_instance : Comma pass_switch_instance ;
comma_pass_enable_switch_instance : Comma pass_enable_switch_instance ;
pull_gate_instance : ( gate_instance_identifier )? pull_gate_interface ;
enable_gate_instance : ( gate_instance_identifier )? enable_gate_interface ;
mos_switch_instance : ( gate_instance_identifier )? mos_switch_interface ;
cmos_switch_instance : ( gate_instance_identifier )? cmos_switch_interface ;
n_input_gate_instance : ( gate_instance_identifier )? n_input_gate_interface ;
n_output_gate_instance : ( gate_instance_identifier )? n_output_gate_interface ;
pass_switch_instance : ( gate_instance_identifier )? pass_switch_interface ;
pass_enable_switch_instance : ( gate_instance_identifier )? pass_enable_switch_interface ;
pull_gate_interface : Open_parenthesis output_terminal Close_parenthesis ;
enable_gate_interface : Open_parenthesis output_terminal Comma input_terminal Comma enable_terminal Close_parenthesis ;
mos_switch_interface : Open_parenthesis output_terminal Comma input_terminal Comma enable_terminal Close_parenthesis ;
cmos_switch_interface : Open_parenthesis output_terminal Comma input_terminal Comma ncontrol_terminal Comma pcontrol_terminal Close_parenthesis ;
n_input_gate_interface : Open_parenthesis output_terminal Comma list_of_input_terminals Close_parenthesis ;
n_output_gate_interface : Open_parenthesis list_of_output_terminals Comma input_terminal Close_parenthesis ;
pass_switch_interface : Open_parenthesis inout_terminal Comma inout_terminal Close_parenthesis ;
pass_enable_switch_interface : Open_parenthesis inout_terminal Comma inout_terminal Comma enable_terminal Close_parenthesis ;
list_of_input_terminals : input_terminal comma_input_terminal_star ;
list_of_output_terminals : output_terminal comma_output_terminal_star ;
comma_input_terminal_star : (comma_input_terminal)* ;
comma_output_terminal_star : (comma_output_terminal)* ;
comma_input_terminal : Comma input_terminal ;
comma_output_terminal : Comma output_terminal ;
enable_terminal : expression ;
input_terminal : expression ;
inout_terminal : expression ;
ncontrol_terminal : expression ;
output_terminal : expression ;
pcontrol_terminal : expression ;
/**********GATE INST**********/
/**********STATEMENT**********/
statement_star : ( statement_semicolon )* ;
statement_semicolon : attribute_instance_star statement semicolon?
| null_statement
;
statement : assignment_statement
| flow_control_statement
| block_statement
| task_call_statement
| event_statement
| procedural_statement
| expression_statement
| subroutine_statement
;
assignment_statement : blocking_assignment
| nonblocking_assignment
| prefix_assignment
| postfix_assignment
| operator_assignment
| declarative_assignment
;
flow_control_statement : case_statement
| conditional_statement
| loop_statement
;
block_statement : par_block
| seq_block
;
task_call_statement : task_enable
| system_task_enable
| disable_statement
;
event_statement : event_trigger
| wait_statement
;
procedural_statement : procedural_continuous_assignments
| procedural_timing_control_statement
| procedural_assertion_statement
| property_statement
;
expression_statement : expression ;
subroutine_statement : return_statement ;
return_statement : Return expression
| Return
;
null_statement : semicolon ;
/**********STATEMENT**********/
/**********PROCEDURAL**********/
procedural_continuous_assignments : assign_statement
| deassign_statement
| force_statement
| release_statement
;
assign_statement : Assign assignment_statement ;
deassign_statement : Deassign variable_lvalue ;
force_statement : Force assignment_statement ;
release_statement : Release variable_lvalue ;
procedural_timing_control_statement : delay_or_event_control statement_semicolon ;
property_statement : disable_condition_statement ;
disable_condition_statement : Disable Iff Open_parenthesis expression Close_parenthesis property_expression ;
property_expression : expression ;
procedural_assertion_statement : assert_statement ( assert_else_statement )? ;
assert_else_statement : Else statement ;
assert_statement : (hierarchical_identifier Colon)? Assert Open_parenthesis expression Close_parenthesis ;
/**********PROCEDURAL**********/
/**********TASKENABLE**********/
system_task_enable : system_task_identifier ( task_interface_assignments )? ;
system_task_identifier : Dollar_Identifier ;
task_interface_assignments : Open_parenthesis (list_of_interface_assignments)? Close_parenthesis ;
task_enable : hierarchical_task_identifier ( task_interface_assignments )? ;
hierarchical_task_identifier : hierarchical_identifier ;
disable_statement : Disable hierarchical_task_identifier
| Disable hierarchical_block_identifier
;
hierarchical_block_identifier : hierarchical_identifier ;
/**********TASKENABLE**********/
/**********ASSIGNMENTS**********/
variable_lvalue : hierarchical_variable_lvalue
| variable_concatenation
;
hierarchical_variable_lvalue : primary_hierarchical_identifier ;
variable_concatenation : Left_curly_bracket variable_concatenation_value comma_vcv_star Right_curly_bracket ;
variable_concatenation_value : primary_hierarchical_identifier
| variable_concatenation
;
comma_vcv_star : ( Comma variable_concatenation_value )* ;
blocking_assignment : variable_lvalue Equal ( delay_or_event_control )? expression ;
nonblocking_assignment : variable_lvalue Left_angle_equals ( delay_or_event_control )? expression ;
prefix_assignment : unary_assign_operator variable_lvalue;
postfix_assignment : variable_lvalue unary_assign_operator;
operator_assignment : variable_lvalue binary_assign_operator expression ;
declarative_assignment : reg_declaration
| logic_declaration
| bits_declaration
| integer_declaration
| int_declaration
| genvar_declaration
;
/**********ASSIGNMENTS**********/
/**********DELAY_EVENT**********/
delay_or_event_control : delay_control
| event_control
| repeat_event_control
;
delay_control : Hash delay_value
| Hash Open_parenthesis delay_value Close_parenthesis
| Hash Open_parenthesis mintypmax_expression Close_parenthesis
;
event_control : event_control_identifier
| event_control_expression
| event_control_wildcard
;
event_control_identifier : At event_identifier ;
event_control_expression : At Open_parenthesis event_expression Close_parenthesis ;
event_expression : single_event_expression
| event_expression_or
;
single_event_expression : expression
| hierarchical_identifier
| event_expression_edgespec expression
;
event_expression_edgespec : Posedge | Negedge ;
event_expression_or : list_of_event_expression_comma
| list_of_event_expression_or
;
list_of_event_expression_comma : single_event_expression comma_event_expression_star ;
comma_event_expression_star : (comma_event_expression)* ;
comma_event_expression : Comma single_event_expression ;
list_of_event_expression_or : single_event_expression or_event_expression_star ;
or_event_expression_star : (or_event_expression)* ;
or_event_expression : Or single_event_expression ;
event_control_wildcard : At Star
| At Open_parenthesis Star Close_parenthesis
;
repeat_event_control : Repeat Open_parenthesis expression Close_parenthesis event_control ;
event_trigger : Dash_right_angle hierarchical_event_identifier ;
hierarchical_event_identifier : hierarchical_identifier ;
event_identifier : identifier ;
wait_statement : Wait Open_parenthesis expression Close_parenthesis statement_semicolon ;
/**********DELAY_EVENT**********/
/**********GENERATES**********/
attr_generated_instantiation : attribute_instance_star generated_instantiation ;
generated_instantiation : Generate generate_item_star Endgenerate semicolon? ;
generate_item_star : ( generate_item )* ;
generate_item : generate_conditional_statement
| generate_case_statement
| generate_loop_statement
| generate_block
//| import_package
| parameter_item_semicolon
//| attr_port_item_semicolon
| attr_variable_item_semicolon
| subroutine_item_semicolon
| attr_construct_item
//| attr_generated_instantiation
| attr_component_item
//| compiler_item
//| type_item
//| verification_item
| null_item
;
generate_block : Begin (generate_colon_block_identifier0)? generate_item_star End (generate_colon_block_identifier1)? semicolon? ;
generate_colon_block_identifier0 : generate_colon_block_identifier ;
generate_colon_block_identifier1 : generate_colon_block_identifier ;
generate_colon_block_identifier : Colon generate_block_identifier ;
generate_block_identifier : identifier ;
generate_conditional_statement : generate_if_statement (generate_else_statement)? ;
generate_if_statement : If Open_parenthesis conditional_expression Close_parenthesis generate_item ;
generate_else_statement : Else generate_item ;
generate_loop_statement : generate_forever_loop_statement
| generate_repeat_loop_statement
| generate_while_loop_statement
| generate_do_loop_statement
| generate_for_loop_statement
;
generate_forever_loop_statement : Forever generate_item ;
generate_repeat_loop_statement : Repeat Open_parenthesis loop_terminate_expression Close_parenthesis generate_item ;
generate_while_loop_statement : While Open_parenthesis loop_terminate_expression Close_parenthesis generate_item ;
generate_do_loop_statement : Do generate_item While Open_parenthesis loop_terminate_expression Close_parenthesis semicolon ;
generate_for_loop_statement : For Open_parenthesis loop_init_assignment semicolon loop_terminate_expression semicolon (loop_step_assignment)? Close_parenthesis generate_item ;
generate_case_statement : any_case_keyword Open_parenthesis case_switch Close_parenthesis generate_case_item_star Endcase ;
generate_case_item_star : ( generate_case_item )* ;
generate_case_item : (case_item_key) Colon generate_item
| Default (Colon)? generate_item
;
/**********GENERATES**********/
/**********CONDITIONAL STATEMENT**********/
//conditional_statement : if_statement (else_statement)? ;
//
//if_statement : If Open_parenthesis conditional_expression Close_parenthesis statement_semicolon ;
//
//else_statement : Else statement_semicolon ;
// DT: above syntax don't care if/else if/ else if nesting
conditional_statement
: if_statement ({_input.LA(1)==Else && _input.LA(2)==If}? elseif_statement |
{_input.LA(1)==Else}? else_statement | )
;
if_statement
: If Open_parenthesis conditional_expression Close_parenthesis statement_semicolon
;
elseif_statement
: Else If Open_parenthesis conditional_expression Close_parenthesis statement_semicolon
;
else_statement
: Else statement_semicolon
;
conditional_expression : expression ;
/**********CONDITIONAL STATEMENT**********/
/**********LOOP STATEMENT**********/
loop_statement : forever_loop_statement
| repeat_loop_statement
| while_loop_statement
| do_loop_statement
| for_loop_statement
;
forever_loop_statement : Forever statement_semicolon ;
repeat_loop_statement : Repeat Open_parenthesis loop_terminate_expression Close_parenthesis statement_semicolon ;
while_loop_statement : While Open_parenthesis loop_terminate_expression Close_parenthesis statement_semicolon ;
do_loop_statement : Do statement_semicolon While Open_parenthesis loop_terminate_expression Close_parenthesis semicolon ;
for_loop_statement : For Open_parenthesis loop_init_assignment semicolon loop_terminate_expression semicolon (loop_step_assignment)? Close_parenthesis statement_semicolon ;
loop_init_assignment : declarative_assignment
| blocking_assignment
;
loop_terminate_expression : expression ;
loop_step_assignment : blocking_assignment
| postfix_assignment
| prefix_assignment
| operator_assignment
;
/**********LOOP STATEMENT**********/
/**********CASE STATEMENT**********/
case_statement : any_case_keyword Open_parenthesis case_switch Close_parenthesis case_item_star Endcase ;
case_item_star : ( case_item )* ;
case_item : (case_item_key) Colon statement_semicolon
| Default (Colon)? statement_semicolon
;
case_switch : expression ;
case_item_key : case_item_key_expression comma_case_item_key_expression_star ;
case_item_key_expression : expression ;
comma_case_item_key_expression : Comma case_item_key_expression ;
comma_case_item_key_expression_star : (comma_case_item_key_expression)* ;
/**********CASE STATEMENT**********/
/**********EXPRESSION**********/
expression : unary_expression
| unary_post_assign_expression
| unary_pre_assign_expression
| binary_expression
| ternary_expression
| mintypmax_expression
| single_expression
;
single_expression : String_literal
//| primary_range
| primary
| arrayed_structured_value
| structured_value
;
primary_range : primary dimension ;
primary : number
| concatenation
| multiple_concatenation
| function_call
| system_function_call
| constant_function_call
| imported_function_call
| primary_imported_hierarchical_identifier
| primary_hierarchical_identifier
| type_cast_expression
| parenthesis_expression
;
unary_expression : unary_operator expression ;
unary_post_assign_expression : single_expression unary_assign_operator ;
unary_pre_assign_expression : unary_assign_operator single_expression ;
binary_expression : single_expression binary_operator expression ;
ternary_expression : single_expression Question_mark expression Colon expression ;
mintypmax_expression : single_expression Colon expression Colon expression ;
structured_value : Quote Left_curly_bracket expression (Comma expression)* Right_curly_bracket
| Quote Left_curly_bracket expression Right_curly_bracket
| Left_curly_bracket Right_curly_bracket
;
arrayed_structured_value : Quote Left_curly_bracket arrayed_structure_item_plus Right_curly_bracket
;
arrayed_structure_item : Default Colon expression
| hierarchical_identifier Colon expression
;
comma_arrayed_structure_item : Comma arrayed_structure_item ;
comma_arrayed_structure_item_star : (comma_arrayed_structure_item)* ;
arrayed_structure_item_plus : arrayed_structure_item comma_arrayed_structure_item_star ;
variable_type_cast : variable_type Quote expression;
width_type_cast : number Quote expression;
sign_type_cast : (Signed | Unsigned) Quote expression;
null_type_cast : Quote expression;
variable_type : Int
| user_type
//| Logic
//| Integer
//| Real
//| Realtime
//| Time
//| Reg
//| SVString
//| bits_type
;
type_cast_identifier : identifier ;
type_cast_expression : variable_type_cast
| width_type_cast
| sign_type_cast
| null_type_cast
;
function_call : hierarchical_function_identifier attribute_instance_star function_interface_assignments ;
hierarchical_function_identifier : hierarchical_identifier ;
function_interface_assignments : Open_parenthesis (list_of_interface_assignments)? Close_parenthesis ;
system_function_call : system_function_identifier ( function_interface_assignments )? ;
system_function_identifier : Dollar_Identifier ;
constant_function_call : function_call ;
imported_function_call : imported_function_hierarchical_identifier attribute_instance_star function_interface_assignments ;
imported_function_hierarchical_identifier : imported_hierarchical_identifier ;
primary_hierarchical_identifier : hierarchical_identifier (dimension_plus)? ;
primary_imported_hierarchical_identifier : imported_hierarchical_identifier (dimension_plus)? ;
imported_hierarchical_identifier : identifier Double_colon hierarchical_identifier ;
parenthesis_expression : Open_parenthesis expression Close_parenthesis ;
concatenation : Left_curly_bracket expression comma_expression_star Right_curly_bracket ;
multiple_concatenation : Left_curly_bracket expression concatenation Right_curly_bracket ;
comma_expression_plus : ( Comma expression )+ ;
comma_expression_star : ( Comma expression )* ;
/**********EXPRESSION**********/
/**********TYPEDEF**********/
typedef_declaration : Typedef typedef_definition typedef_identifier ;
typedef_identifier : identifier ;
typedef_definition : typedef_definition_type
| enumerated_type
| struct_type
;
typedef_definition_type : complex_type
| typedef_type
;
complex_type : typedef_type (Signed | Unsigned)? (dimension_plus)?
;
typedef_type : Reg
| Logic
| bits_type
| net_type
| user_type
;
/**********TYPEDEF**********/
/**********BLOCK**********/
par_block : Fork ( Colon block_identifier )?
block_item_declaration_star
statement_star
join_keyword ( colon_block_identifier )?
;
seq_block : Begin ( Colon block_identifier )?
block_item_declaration_star
statement_star
End ( colon_block_identifier )?
;
block_identifier : identifier ;
colon_block_identifier : Colon block_identifier ;
block_item_declaration_star : ( block_item_declaration_semicolon )* ;
block_item_declaration_semicolon : block_item_declaration semicolon ;
block_item_declaration : reg_declaration
| event_declaration
| logic_declaration
| bits_declaration
| integer_declaration
| int_declaration
| local_parameter_declaration
| parameter_declaration
| real_declaration
| realtime_declaration
| time_declaration
| string_declaration
| usertype_variable_declaration
;
join_keyword : Join | Join_none | Join_any ;
/**********BLOCK**********/
/**********CONSTRUCTS**********/
continuous_assign : Assign ( drive_strength )? ( delay )? list_of_variable_assignments semicolon ;
list_of_variable_assignments : variable_assignment comma_variable_assignment_star ;
comma_variable_assignment_star : ( comma_variable_assignment )* ;
comma_variable_assignment : Comma variable_assignment ;
variable_assignment : variable_lvalue Equal expression ;
initial_construct : Initial statement_semicolon ;
final_construct : Final statement_semicolon ;
always_keyword : Always | Always_comb | Always_ff ;
always_construct : always_keyword statement_semicolon ;
/**********CONSTRUCTS**********/
/**********ATTRIBUTES**********/
attribute_instance_star : ( attribute_instance )* ;
attribute_instance : Open_parenthesis Star attr_spec attr_spec_star Star Close_parenthesis ;
attr_spec_star : ( Comma attr_spec )* ;
attr_spec : attr_name Equal expression
| attr_name
;
attr_name : identifier ;
/**********ATTRIBUTES**********/
/**********LISTS**********/
/**********LISTS**********/
/**********IDENTIFIERS**********/
identifier : Simple_identifier
| Escaped_identifier
;
/**********IDENTIFIERS**********/
/**********HIERARCHICAL IDENTIFIERS**********/
hierarchical_identifier : hierarchical_identifier_branch_item dot_hierarchical_identifier_branch_item_star ;
dot_hierarchical_identifier_branch_item_star : (dot_hierarchical_identifier_branch_item)* ;
dot_hierarchical_identifier_branch_item : Dot hierarchical_identifier_branch_item ;
hierarchical_identifier_branch_item : identifier (dimension_plus)? ;
/**********HIERARCHICAL IDENTIFIERS**********/
/**********TIME DIRECTIVES**********/
timescale_compiler_directive : Tick_timescale Time_literal Forward_slash Time_literal ;
timeunit_directive : Timeunit Time_literal ;
timeprecision_directive : Timeprecision Time_literal ;
/**********TIME DIRECTIVES**********/
/**********NETTYPE DIRECTIVES**********/
default_nettype_statement : Default_nettype net_type ;
/**********NETTYPE DIRECTIVES**********/
/**********NUMBERS**********/
number : integral_number
| real_number
;
integral_number : Decimal_number
| Octal_number
| Binary_number
| Hex_number
;
real_number : Fixed_point_number
| Real_exp_form
;
/**********NUMBERS**********/
/**********VERIFICATION**********/
//assertion_property_block : (assert_identifier_colon)? Assert Property Open_parenthesis statement Close_parenthesis (assert_property_statement)? ( assert_else_statement )? (semicolon)? ;
//assert_identifier_colon : assertion_identifier Colon ;
//assert_property_statement : statement ;
//specify_block : Specify ( specify_item )* Endspecify ;
//specify_item : specparam_declaration
// | pulsestyle_declaration
// | showcancelled_declaration
// | path_declaration
// ;
//specparam_declaration : Specparam (dimension)? list_of_specparam_assignments ;
//pulsestyle_declaration : Pulsestyle_onevent list_of_path_outputs semicolon
// | Pulsestyle_ondetect list_of_path_outputs semicolon
// ;
//showcancelled_declaration : Showcancelled list_of_path_outputs semicolon
// | Noshowcancelled list_of_path_outputs semicolon
// ;
//path_declaration : simple_path_declaration semicolon
// | edge_sensitive_path_declaration semicolon
// | state_dependent_path_declaration semicolon
// ;
//list_of_specparam_assignments : specparam_assignment ( Comma specparam_assignment )* ;
//state_dependent_path_declaration : If Open_parenthesis module_path_expression Close_parenthesis simple_path_declaration
// | If Open_parenthesis module_path_expression Close_parenthesis edge_sensitive_path_declaration
// | Ifnone simple_path_declaration
// ;
//edge_sensitive_path_declaration : parallel_edge_sensitive_path_description Equal path_delay_value
// | full_edge_sensitive_path_description Equal path_delay_value
// ;
//parallel_edge_sensitive_path_description : Open_parenthesis ( edge_identifier )? specify_input_terminal_descriptor Equals_right_angle specify_output_terminal_descriptor ( polarity_operator )? Colon data_source_expression Close_parenthesis ;
//simple_path_declaration : parallel_path_description Equal path_delay_value
// | full_path_description Equal path_delay_value
// ;
//full_path_description : Open_parenthesis list_of_path_inputs ( polarity_operator )? Star_right_angle list_of_path_outputs Close_parenthesis ;
//specparam_assignment : specparam_identifier Equal constant_mintypmax_expression
// | pulse_control_specparam
// ;
//parallel_path_description : ( specify_input_terminal_descriptor ( polarity_operator )? Equals_right_angle specify_output_terminal_descriptor ) ;
//path_delay_value : list_of_path_delay_expressions
// | Open_parenthesis list_of_path_delay_expressions Close_parenthesis
// ;
//full_edge_sensitive_path_description : Open_parenthesis ( edge_identifier )? list_of_path_inputs Star_right_angle list_of_path_outputs ( polarity_operator )? Colon data_source_expression Close_parenthesis ;
//list_of_path_outputs : specify_output_terminal_descriptor ( Comma specify_output_terminal_descriptor )* ;
//specparam_identifier : identifier ;
//pulse_control_specparam : Path_pulse_dollar Equal Open_parenthesis reject_limit_value ( Comma error_limit_value )? Close_parenthesis semicolon
// | Path_pulse_dollar specify_input_terminal_descriptor Dollar specify_output_terminal_descriptor Equal
// Open_parenthesis reject_limit_value ( Comma error_limit_value )? Close_parenthesis semicolon
// ;
//specify_output_terminal_descriptor : output_identifier
// | output_identifier Left_bracket constant_expression Right_bracket
// | output_identifier Left_bracket range_expression Right_bracket
// ;
//output_identifier : output_port_identifier
// | inout_port_identifier
// ;
//list_of_path_delay_expressions : t_path_delay_expression
// | trise_path_delay_expression Comma tfall_path_delay_expression
// | trise_path_delay_expression Comma tfall_path_delay_expression Comma tz_path_delay_expression
// | t01_path_delay_expression Comma t10_path_delay_expression Comma t0z_path_delay_expression Comma tz1_path_delay_expression Comma t1z_path_delay_expression Comma tz0_path_delay_expression
// | t01_path_delay_expression Comma t10_path_delay_expression Comma t0z_path_delay_expression Comma tz1_path_delay_expression Comma t1z_path_delay_expression Comma tz0_path_delay_expression Comma t0x_path_delay_expression Comma tx1_path_delay_expression Comma t1x_path_delay_expression Comma tx0_path_delay_expression Comma txz_path_delay_expression Comma tzx_path_delay_expression
// ;
//edge_identifier : Posedge | Negedge ;
//list_of_path_inputs : specify_input_terminal_descriptor ( Comma specify_input_terminal_descriptor )* ;
//specify_input_terminal_descriptor : input_identifier
// | input_identifier Left_bracket constant_expression Right_bracket
// | input_identifier Left_bracket range_expression Right_bracket
// ;
//data_source_expression : expression ;
//reject_limit_value : limit_value ;
//error_limit_value : limit_value ;
//output_port_identifier : identifier ;
//input_identifier : input_port_identifier
// | inout_port_identifier
// ;
//inout_port_identifier : identifier ;
//t_path_delay_expression : path_delay_expression ;
//trise_path_delay_expression : path_delay_expression ;
//tfall_path_delay_expression : path_delay_expression ;
//tz_path_delay_expression : path_delay_expression ;
//t01_path_delay_expression : path_delay_expression ;
//t10_path_delay_expression : path_delay_expression ;
//t0z_path_delay_expression : path_delay_expression ;
//tz1_path_delay_expression : path_delay_expression ;
//t1z_path_delay_expression : path_delay_expression ;
//tz0_path_delay_expression : path_delay_expression ;
//t0x_path_delay_expression : path_delay_expression ;
//tx1_path_delay_expression : path_delay_expression ;
//t1x_path_delay_expression : path_delay_expression ;
//tx0_path_delay_expression : path_delay_expression ;
//txz_path_delay_expression : path_delay_expression ;
//tzx_path_delay_expression : path_delay_expression ;
//recursive set of rules
//module_path_primary : number
// | identifier
// | module_path_concatenation
// | module_path_multiple_concatenation
// | function_call
// | system_function_call
// | constant_function_call
// | Open_parenthesis module_path_mintypmax_expression Close_parenthesis
// ;
//module_path_multiple_concatenation : Left_curly_bracket constant_expression module_path_concatenation Right_curly_bracket ;
//module_path_concatenation : Left_curly_bracket module_path_expression ( Comma module_path_expression )* Right_curly_bracket ;
//module_path_mintypmax_expression : module_path_expression (Colon module_path_expression Colon module_path_expression)? ;
//module_path_expression : ( module_path_primary | unary_module_path_operator attribute_instance_star module_path_primary )
// ( binary_module_path_operator attribute_instance_star module_path_expression | Question_mark attribute_instance_star module_path_expression Colon module_path_expression )*
// ;
//limit_value : constant_mintypmax_expression ;
//input_port_identifier : identifier ;
//path_delay_expression : constant_mintypmax_expression ;
//constant_mintypmax_expression : constant_expression
// | constant_expression Colon constant_expression Colon constant_expression
// ;
//property_block : Property assertion_identifier semicolon statement Endproperty ;
//assertion_identifier : identifier ;
/**********VERIFICATION**********/
/**********LIBRARY**********/
//library_descriptions : library_declaration
// | config_declaration
// ;
//library_declaration : Library library_identifier file_path_spec ( Comma file_path_spec )* ( Incdir file_path_spec ( Comma file_path_spec )* )? semicolon ;
//library_identifier : identifier ;
//file_path_spec : String_literal ;
//config_declaration : Config config_identifier semicolon design_statement ( config_rule_statement )* Endconfig semicolon? ;
//config_identifier : identifier ;
//design_statement : Design ( ( library_identifier Dot )? cell_identifier )* semicolon ;
//config_rule_statement : Default liblist_clause
// | inst_clause liblist_clause
// | inst_clause use_clause
// | cell_clause liblist_clause
// | cell_clause use_clause
// ;
//liblist_clause : Liblist library_identifier* ;
//inst_clause : Instance inst_name ;
//use_clause : Use ( library_identifier Dot )? cell_identifier ( Colon Config )? ;
//cell_clause : Cell ( library_identifier Dot )? cell_identifier ;
//cell_identifier : identifier ;
//inst_name : topmodule_identifier ( Dot instance_identifier )* ;
//topmodule_identifier : identifier ;
//instance_identifier : identifier ;
/**********LIBRARY**********/
|
processor/src/main/antlr4/br/com/easymath/processor/mathematical/grammar/Formula.g4 | eduardovalentim/easymath | 0 | 1395 | grammar Formula;
// starting point for parsing a formula
formula
: expression
;
expression
: LPAREN expression RPAREN #parenthesis
| LBRACK expression RBRACK #brackets
| LBRACE expression RBRACE #braces
| (operator=ADD|operator=SUB) expression #unary
| expression operator=BANG #unary
| expression operator=CARET expression #binary
| expression (operator=MUL|operator=DIV|operator=MOD) expression #binary
| expression (operator=ADD|operator=SUB) expression #binary
| Identifier LPAREN expression (COMMA expression)* RPAREN #function
| Number #constant
| Identifier #input
;
Identifier
: Letter (Letter | Digit)*
;
Number
: Digit + (DOT Digit +)?
;
fragment
Letter
: [a-zA-Z_]
;
fragment
Digit
: '0'..'9'
;
LPAREN : '(';
RPAREN : ')';
LBRACE : '{';
RBRACE : '}';
LBRACK : '[';
RBRACK : ']';
SEMI : ';';
COMMA : ',';
DOT : '.';
ASSIGN : '=';
GT : '>';
LT : '<';
BANG : '!';
TILDE : '~';
QUESTION : '?';
COLON : ':';
EQUAL : '==';
LE : '<=';
GE : '>=';
NOTEQUAL : '!=';
AND : '&&';
OR : '||';
INC : '++';
DEC : '--';
ADD : '+';
SUB : '-';
MUL : '*';
DIV : '/';
BITAND : '&';
BITOR : '|';
CARET : '^';
MOD : '%';
//
// Whitespace
//
WS : [ \t\r\n\u000C]+ -> skip
;
|
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