max_stars_repo_path stringlengths 4 261 | max_stars_repo_name stringlengths 6 106 | max_stars_count int64 0 38.8k | id stringlengths 1 6 | text stringlengths 7 1.05M |
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libsrc/target/x1/graphics/w_xorpixl.asm | Frodevan/z88dk | 640 | 3196 | ;
; Generic pseudo graphics routines for text-only platforms
;
; Xor pixel at (x,y) coordinate.
SECTION code_clib
PUBLIC w_xorpixel
EXTERN __spc1000_mode
defc NEEDxor = 1
.w_xorpixel
INCLUDE "w_pixel.inc"
|
Terceiro semestre/SDMI - Sistemas Digitais e Microcontroladores/PIC/ExstoKit/ExstoKit.asm | Eduardo-Barreto/Tecnico-Mecatronic | 2 | 5626 | <gh_stars>1-10
_resetAll:
;ExstoKit.c,60 :: void resetAll(){
;ExstoKit.c,61 :: display1 = 1;
BSF PORTA+0, 5
;ExstoKit.c,62 :: display2 = 1;
BSF PORTA+0, 2
;ExstoKit.c,63 :: display3 = 1;
BSF PORTE+0, 0
;ExstoKit.c,64 :: display4 = 1;
BSF PORTE+0, 2
;ExstoKit.c,65 :: pinoA = 0;
BCF PORTD+0, 0
;ExstoKit.c,66 :: pinoB = 0;
BCF PORTD+0, 1
;ExstoKit.c,67 :: pinoC = 0;
BCF PORTD+0, 2
;ExstoKit.c,68 :: pinoD = 0;
BCF PORTD+0, 3
;ExstoKit.c,69 :: pinoE = 0;
BCF PORTD+0, 4
;ExstoKit.c,70 :: pinoF = 0;
BCF PORTD+0, 5
;ExstoKit.c,71 :: pinoG = 0;
BCF PORTD+0, 6
;ExstoKit.c,72 :: pinoDP = 0;
BCF PORTD+0, 7
;ExstoKit.c,73 :: display1 = 0;
BCF PORTA+0, 5
;ExstoKit.c,74 :: display2 = 0;
BCF PORTA+0, 2
;ExstoKit.c,75 :: display3 = 0;
BCF PORTE+0, 0
;ExstoKit.c,76 :: display4 = 0;
BCF PORTE+0, 2
;ExstoKit.c,77 :: }
L_end_resetAll:
RETURN 0
; end of _resetAll
_resetDisplays:
;ExstoKit.c,79 :: void resetDisplays(){
;ExstoKit.c,80 :: display1 = 0;
BCF PORTA+0, 5
;ExstoKit.c,81 :: display2 = 0;
BCF PORTA+0, 2
;ExstoKit.c,82 :: display3 = 0;
BCF PORTE+0, 0
;ExstoKit.c,83 :: display4 = 0;
BCF PORTE+0, 2
;ExstoKit.c,84 :: }
L_end_resetDisplays:
RETURN 0
; end of _resetDisplays
_setNumber:
;ExstoKit.c,86 :: void setNumber(int _display, int _number){
;ExstoKit.c,87 :: switch(_display){
GOTO L_setNumber0
;ExstoKit.c,88 :: case 1:
L_setNumber2:
;ExstoKit.c,89 :: display1 = 1;
BSF PORTA+0, 5
;ExstoKit.c,90 :: break;
GOTO L_setNumber1
;ExstoKit.c,92 :: case 2:
L_setNumber3:
;ExstoKit.c,93 :: display2 = 1;
BSF PORTA+0, 2
;ExstoKit.c,94 :: break;
GOTO L_setNumber1
;ExstoKit.c,96 :: case 3:
L_setNumber4:
;ExstoKit.c,97 :: display3 = 1;
BSF PORTE+0, 0
;ExstoKit.c,98 :: break;
GOTO L_setNumber1
;ExstoKit.c,100 :: case 4:
L_setNumber5:
;ExstoKit.c,101 :: display4 = 1;
BSF PORTE+0, 2
;ExstoKit.c,102 :: break;
GOTO L_setNumber1
;ExstoKit.c,104 :: default:
L_setNumber6:
;ExstoKit.c,105 :: return;
GOTO L_end_setNumber
;ExstoKit.c,106 :: }
L_setNumber0:
MOVLW 0
XORWF FARG_setNumber__display+1, 0
BTFSS STATUS+0, 2
GOTO L__setNumber30
MOVLW 1
XORWF FARG_setNumber__display+0, 0
L__setNumber30:
BTFSC STATUS+0, 2
GOTO L_setNumber2
MOVLW 0
XORWF FARG_setNumber__display+1, 0
BTFSS STATUS+0, 2
GOTO L__setNumber31
MOVLW 2
XORWF FARG_setNumber__display+0, 0
L__setNumber31:
BTFSC STATUS+0, 2
GOTO L_setNumber3
MOVLW 0
XORWF FARG_setNumber__display+1, 0
BTFSS STATUS+0, 2
GOTO L__setNumber32
MOVLW 3
XORWF FARG_setNumber__display+0, 0
L__setNumber32:
BTFSC STATUS+0, 2
GOTO L_setNumber4
MOVLW 0
XORWF FARG_setNumber__display+1, 0
BTFSS STATUS+0, 2
GOTO L__setNumber33
MOVLW 4
XORWF FARG_setNumber__display+0, 0
L__setNumber33:
BTFSC STATUS+0, 2
GOTO L_setNumber5
GOTO L_setNumber6
L_setNumber1:
;ExstoKit.c,107 :: PORTD = numbers[_number];
MOVF FARG_setNumber__number+0, 0
MOVWF R0
MOVF FARG_setNumber__number+1, 0
MOVWF R1
RLCF R0, 1
BCF R0, 0
RLCF R1, 1
MOVLW _numbers+0
ADDWF R0, 0
MOVWF FSR0L+0
MOVLW hi_addr(_numbers+0)
ADDWFC R1, 0
MOVWF FSR0L+1
MOVF POSTINC0+0, 0
MOVWF PORTD+0
;ExstoKit.c,108 :: delay_ms(1);
MOVLW 7
MOVWF R12, 0
MOVLW 125
MOVWF R13, 0
L_setNumber7:
DECFSZ R13, 1, 1
BRA L_setNumber7
DECFSZ R12, 1, 1
BRA L_setNumber7
;ExstoKit.c,109 :: resetDisplays();
CALL _resetDisplays+0, 0
;ExstoKit.c,110 :: }
L_end_setNumber:
RETURN 0
; end of _setNumber
_setNumbers:
;ExstoKit.c,112 :: void setNumbers(int _numbers[4], int _timer){
;ExstoKit.c,113 :: int c = 0;
CLRF setNumbers_c_L0+0
CLRF setNumbers_c_L0+1
;ExstoKit.c,114 :: for (c; c<=_timer; c++){
L_setNumbers8:
MOVLW 128
XORWF FARG_setNumbers__timer+1, 0
MOVWF R0
MOVLW 128
XORWF setNumbers_c_L0+1, 0
SUBWF R0, 0
BTFSS STATUS+0, 2
GOTO L__setNumbers35
MOVF setNumbers_c_L0+0, 0
SUBWF FARG_setNumbers__timer+0, 0
L__setNumbers35:
BTFSS STATUS+0, 0
GOTO L_setNumbers9
;ExstoKit.c,115 :: setNumber(1, _numbers[0]);
MOVLW 1
MOVWF FARG_setNumber__display+0
MOVLW 0
MOVWF FARG_setNumber__display+1
MOVFF FARG_setNumbers__numbers+0, FSR0L+0
MOVFF FARG_setNumbers__numbers+1, FSR0H+0
MOVF POSTINC0+0, 0
MOVWF FARG_setNumber__number+0
MOVF POSTINC0+0, 0
MOVWF FARG_setNumber__number+1
CALL _setNumber+0, 0
;ExstoKit.c,116 :: setNumber(2, _numbers[1]);
MOVLW 2
MOVWF FARG_setNumber__display+0
MOVLW 0
MOVWF FARG_setNumber__display+1
MOVLW 2
ADDWF FARG_setNumbers__numbers+0, 0
MOVWF FSR0L+0
MOVLW 0
ADDWFC FARG_setNumbers__numbers+1, 0
MOVWF FSR0L+1
MOVF POSTINC0+0, 0
MOVWF FARG_setNumber__number+0
MOVF POSTINC0+0, 0
MOVWF FARG_setNumber__number+1
CALL _setNumber+0, 0
;ExstoKit.c,117 :: setNumber(3, _numbers[2]);
MOVLW 3
MOVWF FARG_setNumber__display+0
MOVLW 0
MOVWF FARG_setNumber__display+1
MOVLW 4
ADDWF FARG_setNumbers__numbers+0, 0
MOVWF FSR0L+0
MOVLW 0
ADDWFC FARG_setNumbers__numbers+1, 0
MOVWF FSR0L+1
MOVF POSTINC0+0, 0
MOVWF FARG_setNumber__number+0
MOVF POSTINC0+0, 0
MOVWF FARG_setNumber__number+1
CALL _setNumber+0, 0
;ExstoKit.c,118 :: setNumber(4, _numbers[3]);
MOVLW 4
MOVWF FARG_setNumber__display+0
MOVLW 0
MOVWF FARG_setNumber__display+1
MOVLW 6
ADDWF FARG_setNumbers__numbers+0, 0
MOVWF FSR0L+0
MOVLW 0
ADDWFC FARG_setNumbers__numbers+1, 0
MOVWF FSR0L+1
MOVF POSTINC0+0, 0
MOVWF FARG_setNumber__number+0
MOVF POSTINC0+0, 0
MOVWF FARG_setNumber__number+1
CALL _setNumber+0, 0
;ExstoKit.c,114 :: for (c; c<=_timer; c++){
INFSNZ setNumbers_c_L0+0, 1
INCF setNumbers_c_L0+1, 1
;ExstoKit.c,119 :: }
GOTO L_setNumbers8
L_setNumbers9:
;ExstoKit.c,120 :: }
L_end_setNumbers:
RETURN 0
; end of _setNumbers
_setLetter:
;ExstoKit.c,122 :: void setLetter(int _display, int _letterIndex){
;ExstoKit.c,123 :: switch(_display){
GOTO L_setLetter11
;ExstoKit.c,124 :: case 1:
L_setLetter13:
;ExstoKit.c,125 :: display1 = 1;
BSF PORTA+0, 5
;ExstoKit.c,126 :: break;
GOTO L_setLetter12
;ExstoKit.c,128 :: case 2:
L_setLetter14:
;ExstoKit.c,129 :: display2 = 1;
BSF PORTA+0, 2
;ExstoKit.c,130 :: break;
GOTO L_setLetter12
;ExstoKit.c,132 :: case 3:
L_setLetter15:
;ExstoKit.c,133 :: display3 = 1;
BSF PORTE+0, 0
;ExstoKit.c,134 :: break;
GOTO L_setLetter12
;ExstoKit.c,136 :: case 4:
L_setLetter16:
;ExstoKit.c,137 :: display4 = 1;
BSF PORTE+0, 2
;ExstoKit.c,138 :: break;
GOTO L_setLetter12
;ExstoKit.c,140 :: default:
L_setLetter17:
;ExstoKit.c,141 :: return;
GOTO L_end_setLetter
;ExstoKit.c,142 :: }
L_setLetter11:
MOVLW 0
XORWF FARG_setLetter__display+1, 0
BTFSS STATUS+0, 2
GOTO L__setLetter37
MOVLW 1
XORWF FARG_setLetter__display+0, 0
L__setLetter37:
BTFSC STATUS+0, 2
GOTO L_setLetter13
MOVLW 0
XORWF FARG_setLetter__display+1, 0
BTFSS STATUS+0, 2
GOTO L__setLetter38
MOVLW 2
XORWF FARG_setLetter__display+0, 0
L__setLetter38:
BTFSC STATUS+0, 2
GOTO L_setLetter14
MOVLW 0
XORWF FARG_setLetter__display+1, 0
BTFSS STATUS+0, 2
GOTO L__setLetter39
MOVLW 3
XORWF FARG_setLetter__display+0, 0
L__setLetter39:
BTFSC STATUS+0, 2
GOTO L_setLetter15
MOVLW 0
XORWF FARG_setLetter__display+1, 0
BTFSS STATUS+0, 2
GOTO L__setLetter40
MOVLW 4
XORWF FARG_setLetter__display+0, 0
L__setLetter40:
BTFSC STATUS+0, 2
GOTO L_setLetter16
GOTO L_setLetter17
L_setLetter12:
;ExstoKit.c,143 :: PORTD = letters[_letterIndex];
MOVF FARG_setLetter__letterIndex+0, 0
MOVWF R0
MOVF FARG_setLetter__letterIndex+1, 0
MOVWF R1
RLCF R0, 1
BCF R0, 0
RLCF R1, 1
MOVLW _letters+0
ADDWF R0, 0
MOVWF FSR0L+0
MOVLW hi_addr(_letters+0)
ADDWFC R1, 0
MOVWF FSR0L+1
MOVF POSTINC0+0, 0
MOVWF PORTD+0
;ExstoKit.c,144 :: delay_ms(1);
MOVLW 7
MOVWF R12, 0
MOVLW 125
MOVWF R13, 0
L_setLetter18:
DECFSZ R13, 1, 1
BRA L_setLetter18
DECFSZ R12, 1, 1
BRA L_setLetter18
;ExstoKit.c,145 :: resetDisplays();
CALL _resetDisplays+0, 0
;ExstoKit.c,146 :: }
L_end_setLetter:
RETURN 0
; end of _setLetter
_setWord:
;ExstoKit.c,148 :: void setWord(int _letters[4], int _timer){
;ExstoKit.c,149 :: int c = 0;
CLRF setWord_c_L0+0
CLRF setWord_c_L0+1
;ExstoKit.c,150 :: for (c; c<=_timer; c++){
L_setWord19:
MOVLW 128
XORWF FARG_setWord__timer+1, 0
MOVWF R0
MOVLW 128
XORWF setWord_c_L0+1, 0
SUBWF R0, 0
BTFSS STATUS+0, 2
GOTO L__setWord42
MOVF setWord_c_L0+0, 0
SUBWF FARG_setWord__timer+0, 0
L__setWord42:
BTFSS STATUS+0, 0
GOTO L_setWord20
;ExstoKit.c,151 :: setLetter(1, _letters[0]);
MOVLW 1
MOVWF FARG_setLetter__display+0
MOVLW 0
MOVWF FARG_setLetter__display+1
MOVFF FARG_setWord__letters+0, FSR0L+0
MOVFF FARG_setWord__letters+1, FSR0H+0
MOVF POSTINC0+0, 0
MOVWF FARG_setLetter__letterIndex+0
MOVF POSTINC0+0, 0
MOVWF FARG_setLetter__letterIndex+1
CALL _setLetter+0, 0
;ExstoKit.c,152 :: setLetter(2, _letters[1]);
MOVLW 2
MOVWF FARG_setLetter__display+0
MOVLW 0
MOVWF FARG_setLetter__display+1
MOVLW 2
ADDWF FARG_setWord__letters+0, 0
MOVWF FSR0L+0
MOVLW 0
ADDWFC FARG_setWord__letters+1, 0
MOVWF FSR0L+1
MOVF POSTINC0+0, 0
MOVWF FARG_setLetter__letterIndex+0
MOVF POSTINC0+0, 0
MOVWF FARG_setLetter__letterIndex+1
CALL _setLetter+0, 0
;ExstoKit.c,153 :: setLetter(3, _letters[2]);
MOVLW 3
MOVWF FARG_setLetter__display+0
MOVLW 0
MOVWF FARG_setLetter__display+1
MOVLW 4
ADDWF FARG_setWord__letters+0, 0
MOVWF FSR0L+0
MOVLW 0
ADDWFC FARG_setWord__letters+1, 0
MOVWF FSR0L+1
MOVF POSTINC0+0, 0
MOVWF FARG_setLetter__letterIndex+0
MOVF POSTINC0+0, 0
MOVWF FARG_setLetter__letterIndex+1
CALL _setLetter+0, 0
;ExstoKit.c,154 :: setLetter(4, _letters[3]);
MOVLW 4
MOVWF FARG_setLetter__display+0
MOVLW 0
MOVWF FARG_setLetter__display+1
MOVLW 6
ADDWF FARG_setWord__letters+0, 0
MOVWF FSR0L+0
MOVLW 0
ADDWFC FARG_setWord__letters+1, 0
MOVWF FSR0L+1
MOVF POSTINC0+0, 0
MOVWF FARG_setLetter__letterIndex+0
MOVF POSTINC0+0, 0
MOVWF FARG_setLetter__letterIndex+1
CALL _setLetter+0, 0
;ExstoKit.c,150 :: for (c; c<=_timer; c++){
INFSNZ setWord_c_L0+0, 1
INCF setWord_c_L0+1, 1
;ExstoKit.c,155 :: }
GOTO L_setWord19
L_setWord20:
;ExstoKit.c,156 :: }
L_end_setWord:
RETURN 0
; end of _setWord
_slideWord:
;ExstoKit.c,158 :: void slideWord(int _letters[8], int _timer){
;ExstoKit.c,162 :: for(counter=0; counter<8; counter++){
CLRF slideWord_counter_L0+0
CLRF slideWord_counter_L0+1
L_slideWord22:
MOVLW 128
XORWF slideWord_counter_L0+1, 0
MOVWF R0
MOVLW 128
SUBWF R0, 0
BTFSS STATUS+0, 2
GOTO L__slideWord44
MOVLW 8
SUBWF slideWord_counter_L0+0, 0
L__slideWord44:
BTFSC STATUS+0, 0
GOTO L_slideWord23
;ExstoKit.c,163 :: _letters[0] = _letters[counter-7];
MOVLW 7
SUBWF slideWord_counter_L0+0, 0
MOVWF R3
MOVLW 0
SUBWFB slideWord_counter_L0+1, 0
MOVWF R4
MOVF R3, 0
MOVWF R0
MOVF R4, 0
MOVWF R1
RLCF R0, 1
BCF R0, 0
RLCF R1, 1
MOVF FARG_slideWord__letters+0, 0
ADDWF R0, 1
MOVF FARG_slideWord__letters+1, 0
ADDWFC R1, 1
MOVFF FARG_slideWord__letters+0, FSR1L+0
MOVFF FARG_slideWord__letters+1, FSR1H+0
MOVFF R0, FSR0L+0
MOVFF R1, FSR0H+0
MOVF POSTINC0+0, 0
MOVWF POSTINC1+0
MOVF POSTINC0+0, 0
MOVWF POSTINC1+0
;ExstoKit.c,164 :: _letters[1] = _letters[counter-6];
MOVLW 2
ADDWF FARG_slideWord__letters+0, 0
MOVWF FSR1L+0
MOVLW 0
ADDWFC FARG_slideWord__letters+1, 0
MOVWF FSR1L+1
MOVLW 6
SUBWF slideWord_counter_L0+0, 0
MOVWF R3
MOVLW 0
SUBWFB slideWord_counter_L0+1, 0
MOVWF R4
MOVF R3, 0
MOVWF R0
MOVF R4, 0
MOVWF R1
RLCF R0, 1
BCF R0, 0
RLCF R1, 1
MOVF R0, 0
ADDWF FARG_slideWord__letters+0, 0
MOVWF FSR0L+0
MOVF R1, 0
ADDWFC FARG_slideWord__letters+1, 0
MOVWF FSR0L+1
MOVF POSTINC0+0, 0
MOVWF POSTINC1+0
MOVF POSTINC0+0, 0
MOVWF POSTINC1+0
;ExstoKit.c,165 :: _letters[2] = _letters[counter-5];
MOVLW 4
ADDWF FARG_slideWord__letters+0, 0
MOVWF FSR1L+0
MOVLW 0
ADDWFC FARG_slideWord__letters+1, 0
MOVWF FSR1L+1
MOVLW 5
SUBWF slideWord_counter_L0+0, 0
MOVWF R3
MOVLW 0
SUBWFB slideWord_counter_L0+1, 0
MOVWF R4
MOVF R3, 0
MOVWF R0
MOVF R4, 0
MOVWF R1
RLCF R0, 1
BCF R0, 0
RLCF R1, 1
MOVF R0, 0
ADDWF FARG_slideWord__letters+0, 0
MOVWF FSR0L+0
MOVF R1, 0
ADDWFC FARG_slideWord__letters+1, 0
MOVWF FSR0L+1
MOVF POSTINC0+0, 0
MOVWF POSTINC1+0
MOVF POSTINC0+0, 0
MOVWF POSTINC1+0
;ExstoKit.c,166 :: _letters[3] = _letters[counter-4];
MOVLW 6
ADDWF FARG_slideWord__letters+0, 0
MOVWF FSR1L+0
MOVLW 0
ADDWFC FARG_slideWord__letters+1, 0
MOVWF FSR1L+1
MOVLW 4
SUBWF slideWord_counter_L0+0, 0
MOVWF R3
MOVLW 0
SUBWFB slideWord_counter_L0+1, 0
MOVWF R4
MOVF R3, 0
MOVWF R0
MOVF R4, 0
MOVWF R1
RLCF R0, 1
BCF R0, 0
RLCF R1, 1
MOVF R0, 0
ADDWF FARG_slideWord__letters+0, 0
MOVWF FSR0L+0
MOVF R1, 0
ADDWFC FARG_slideWord__letters+1, 0
MOVWF FSR0L+1
MOVF POSTINC0+0, 0
MOVWF POSTINC1+0
MOVF POSTINC0+0, 0
MOVWF POSTINC1+0
;ExstoKit.c,167 :: _letters[4] = _letters[counter-3];
MOVLW 8
ADDWF FARG_slideWord__letters+0, 0
MOVWF FSR1L+0
MOVLW 0
ADDWFC FARG_slideWord__letters+1, 0
MOVWF FSR1L+1
MOVLW 3
SUBWF slideWord_counter_L0+0, 0
MOVWF R3
MOVLW 0
SUBWFB slideWord_counter_L0+1, 0
MOVWF R4
MOVF R3, 0
MOVWF R0
MOVF R4, 0
MOVWF R1
RLCF R0, 1
BCF R0, 0
RLCF R1, 1
MOVF R0, 0
ADDWF FARG_slideWord__letters+0, 0
MOVWF FSR0L+0
MOVF R1, 0
ADDWFC FARG_slideWord__letters+1, 0
MOVWF FSR0L+1
MOVF POSTINC0+0, 0
MOVWF POSTINC1+0
MOVF POSTINC0+0, 0
MOVWF POSTINC1+0
;ExstoKit.c,168 :: _letters[5] = _letters[counter-2];
MOVLW 10
ADDWF FARG_slideWord__letters+0, 0
MOVWF FSR1L+0
MOVLW 0
ADDWFC FARG_slideWord__letters+1, 0
MOVWF FSR1L+1
MOVLW 2
SUBWF slideWord_counter_L0+0, 0
MOVWF R3
MOVLW 0
SUBWFB slideWord_counter_L0+1, 0
MOVWF R4
MOVF R3, 0
MOVWF R0
MOVF R4, 0
MOVWF R1
RLCF R0, 1
BCF R0, 0
RLCF R1, 1
MOVF R0, 0
ADDWF FARG_slideWord__letters+0, 0
MOVWF FSR0L+0
MOVF R1, 0
ADDWFC FARG_slideWord__letters+1, 0
MOVWF FSR0L+1
MOVF POSTINC0+0, 0
MOVWF POSTINC1+0
MOVF POSTINC0+0, 0
MOVWF POSTINC1+0
;ExstoKit.c,169 :: _letters[6] = _letters[counter-1];
MOVLW 12
ADDWF FARG_slideWord__letters+0, 0
MOVWF FSR1L+0
MOVLW 0
ADDWFC FARG_slideWord__letters+1, 0
MOVWF FSR1L+1
MOVLW 1
SUBWF slideWord_counter_L0+0, 0
MOVWF R3
MOVLW 0
SUBWFB slideWord_counter_L0+1, 0
MOVWF R4
MOVF R3, 0
MOVWF R0
MOVF R4, 0
MOVWF R1
RLCF R0, 1
BCF R0, 0
RLCF R1, 1
MOVF R0, 0
ADDWF FARG_slideWord__letters+0, 0
MOVWF FSR0L+0
MOVF R1, 0
ADDWFC FARG_slideWord__letters+1, 0
MOVWF FSR0L+1
MOVF POSTINC0+0, 0
MOVWF POSTINC1+0
MOVF POSTINC0+0, 0
MOVWF POSTINC1+0
;ExstoKit.c,170 :: _letters[7] = _letters[counter];
MOVLW 14
ADDWF FARG_slideWord__letters+0, 0
MOVWF FSR1L+0
MOVLW 0
ADDWFC FARG_slideWord__letters+1, 0
MOVWF FSR1L+1
MOVF slideWord_counter_L0+0, 0
MOVWF R0
MOVF slideWord_counter_L0+1, 0
MOVWF R1
RLCF R0, 1
BCF R0, 0
RLCF R1, 1
MOVF R0, 0
ADDWF FARG_slideWord__letters+0, 0
MOVWF FSR0L+0
MOVF R1, 0
ADDWFC FARG_slideWord__letters+1, 0
MOVWF FSR0L+1
MOVF POSTINC0+0, 0
MOVWF POSTINC1+0
MOVF POSTINC0+0, 0
MOVWF POSTINC1+0
;ExstoKit.c,172 :: wordOne[0] = _letters[0];
MOVFF FARG_slideWord__letters+0, FSR0L+0
MOVFF FARG_slideWord__letters+1, FSR0H+0
MOVF POSTINC0+0, 0
MOVWF slideWord_wordOne_L0+0
MOVF POSTINC0+0, 0
MOVWF slideWord_wordOne_L0+1
;ExstoKit.c,173 :: wordOne[1] = _letters[1];
MOVLW 2
ADDWF FARG_slideWord__letters+0, 0
MOVWF FSR0L+0
MOVLW 0
ADDWFC FARG_slideWord__letters+1, 0
MOVWF FSR0L+1
MOVF POSTINC0+0, 0
MOVWF slideWord_wordOne_L0+2
MOVF POSTINC0+0, 0
MOVWF slideWord_wordOne_L0+3
;ExstoKit.c,174 :: wordOne[2] = _letters[2];
MOVLW 4
ADDWF FARG_slideWord__letters+0, 0
MOVWF FSR0L+0
MOVLW 0
ADDWFC FARG_slideWord__letters+1, 0
MOVWF FSR0L+1
MOVF POSTINC0+0, 0
MOVWF slideWord_wordOne_L0+4
MOVF POSTINC0+0, 0
MOVWF slideWord_wordOne_L0+5
;ExstoKit.c,175 :: wordOne[3] = _letters[3];
MOVLW 6
ADDWF FARG_slideWord__letters+0, 0
MOVWF FSR0L+0
MOVLW 0
ADDWFC FARG_slideWord__letters+1, 0
MOVWF FSR0L+1
MOVF POSTINC0+0, 0
MOVWF slideWord_wordOne_L0+6
MOVF POSTINC0+0, 0
MOVWF slideWord_wordOne_L0+7
;ExstoKit.c,177 :: wordTwo[0] = _letters[4];
MOVLW 8
ADDWF FARG_slideWord__letters+0, 0
MOVWF FSR0L+0
MOVLW 0
ADDWFC FARG_slideWord__letters+1, 0
MOVWF FSR0L+1
MOVF POSTINC0+0, 0
MOVWF slideWord_wordTwo_L0+0
MOVF POSTINC0+0, 0
MOVWF slideWord_wordTwo_L0+1
;ExstoKit.c,178 :: wordTwo[1] = _letters[5];
MOVLW 10
ADDWF FARG_slideWord__letters+0, 0
MOVWF FSR0L+0
MOVLW 0
ADDWFC FARG_slideWord__letters+1, 0
MOVWF FSR0L+1
MOVF POSTINC0+0, 0
MOVWF slideWord_wordTwo_L0+2
MOVF POSTINC0+0, 0
MOVWF slideWord_wordTwo_L0+3
;ExstoKit.c,179 :: wordTwo[2] = _letters[6];
MOVLW 12
ADDWF FARG_slideWord__letters+0, 0
MOVWF FSR0L+0
MOVLW 0
ADDWFC FARG_slideWord__letters+1, 0
MOVWF FSR0L+1
MOVF POSTINC0+0, 0
MOVWF slideWord_wordTwo_L0+4
MOVF POSTINC0+0, 0
MOVWF slideWord_wordTwo_L0+5
;ExstoKit.c,180 :: wordTwo[3] = _letters[7];
MOVLW 14
ADDWF FARG_slideWord__letters+0, 0
MOVWF FSR0L+0
MOVLW 0
ADDWFC FARG_slideWord__letters+1, 0
MOVWF FSR0L+1
MOVF POSTINC0+0, 0
MOVWF slideWord_wordTwo_L0+6
MOVF POSTINC0+0, 0
MOVWF slideWord_wordTwo_L0+7
;ExstoKit.c,181 :: setWord(wordOne, _timer);
MOVLW slideWord_wordOne_L0+0
MOVWF FARG_setWord__letters+0
MOVLW hi_addr(slideWord_wordOne_L0+0)
MOVWF FARG_setWord__letters+1
MOVF FARG_slideWord__timer+0, 0
MOVWF FARG_setWord__timer+0
MOVF FARG_slideWord__timer+1, 0
MOVWF FARG_setWord__timer+1
CALL _setWord+0, 0
;ExstoKit.c,182 :: setWord(wordTwo, _timer);
MOVLW slideWord_wordTwo_L0+0
MOVWF FARG_setWord__letters+0
MOVLW hi_addr(slideWord_wordTwo_L0+0)
MOVWF FARG_setWord__letters+1
MOVF FARG_slideWord__timer+0, 0
MOVWF FARG_setWord__timer+0
MOVF FARG_slideWord__timer+1, 0
MOVWF FARG_setWord__timer+1
CALL _setWord+0, 0
;ExstoKit.c,162 :: for(counter=0; counter<8; counter++){
INFSNZ slideWord_counter_L0+0, 1
INCF slideWord_counter_L0+1, 1
;ExstoKit.c,183 :: }
GOTO L_slideWord22
L_slideWord23:
;ExstoKit.c,184 :: }
L_end_slideWord:
RETURN 0
; end of _slideWord
_main:
;ExstoKit.c,186 :: void main() {
;ExstoKit.c,187 :: int sexshop[8] = {18, 4, 23, 26, 18, 7, 14, 15};
MOVLW ?ICSmain_sexshop_L0+0
MOVWF TBLPTRL+0
MOVLW hi_addr(?ICSmain_sexshop_L0+0)
MOVWF TBLPTRL+1
MOVLW higher_addr(?ICSmain_sexshop_L0+0)
MOVWF TBLPTRL+2
MOVLW main_sexshop_L0+0
MOVWF FSR1L+0
MOVLW hi_addr(main_sexshop_L0+0)
MOVWF FSR1L+1
MOVLW 16
MOVWF R0
MOVLW 1
MOVWF R1
CALL ___CC2DW+0, 0
;ExstoKit.c,188 :: ADCON1 = 0b00001111;
MOVLW 15
MOVWF ADCON1+0
;ExstoKit.c,189 :: TRISD = 0b00000000;
CLRF TRISD+0
;ExstoKit.c,190 :: TRISA.B5 = 0;
BCF TRISA+0, 5
;ExstoKit.c,191 :: TRISA.B2 = 0;
BCF TRISA+0, 2
;ExstoKit.c,192 :: TRISE.B2 = 0;
BCF TRISE+0, 2
;ExstoKit.c,193 :: TRISE.B0 = 0;
BCF TRISE+0, 0
;ExstoKit.c,195 :: resetAll();
CALL _resetAll+0, 0
;ExstoKit.c,197 :: while(1){
L_main25:
;ExstoKit.c,198 :: slideWord(sexshop, 300);
MOVLW main_sexshop_L0+0
MOVWF FARG_slideWord__letters+0
MOVLW hi_addr(main_sexshop_L0+0)
MOVWF FARG_slideWord__letters+1
MOVLW 44
MOVWF FARG_slideWord__timer+0
MOVLW 1
MOVWF FARG_slideWord__timer+1
CALL _slideWord+0, 0
;ExstoKit.c,199 :: }
GOTO L_main25
;ExstoKit.c,203 :: }
L_end_main:
GOTO $+0
; end of _main
|
P1/Tests/ex-2.16.4.asm | caiopo/INE5411 | 1 | 95199 | .text
.globl main
main:
li $t0, 0x0001000
slt $t2, $t0, $t0
bnez $t2, Else
j Done
Else:
addi $t2, $t2, 2
Done: |
programs/oeis/108/A108357.asm | karttu/loda | 1 | 29675 | <filename>programs/oeis/108/A108357.asm
; A108357: Expansion of (1+x^2+x^4)/(1-x^8).
; 1,0,1,0,1,0,0,0,1,0,1,0,1,0,0,0,1,0,1,0,1,0,0,0,1,0,1,0,1,0,0,0,1,0,1,0,1,0,0,0,1,0,1,0,1,0,0,0,1,0,1,0,1,0,0,0,1,0,1,0,1,0,0,0,1,0,1,0,1,0,0,0,1,0,1,0,1,0,0,0,1,0,1,0,1,0,0,0,1,0,1,0,1,0,0,0,1,0,1,0,1
mod $0,8
mul $0,3
mov $1,15
trn $1,$0
mod $1,2
|
examples/ada-help-binary/src/show_help.adb | stcarrez/resource-embedder | 7 | 15585 | <reponame>stcarrez/resource-embedder
with Ada.Text_IO.Text_Streams;
with Ada.Command_Line;
with Resources.Help;
with Resources.Man;
with System.Storage_Elements;
procedure Show_Help is
use Ada.Text_IO;
use Resources;
use System.Storage_Elements;
procedure Print (Name : in String) is
C : access constant Storage_Array := Man.Get_Content (Name);
begin
if C = null then
C := Help.Get_Content (Name);
if C = null then
Ada.Text_IO.Put_Line ("FAIL: No help for '" & Name & "'");
Ada.Command_Line.Set_Exit_Status (Ada.Command_Line.Failure);
end if;
end if;
Storage_Array'Write (Text_Streams.Stream (Current_Output), C.all);
end Print;
Count : constant Natural := Ada.Command_Line.Argument_Count;
begin
if Count = 0 then
Ada.Text_IO.Put_Line ("Help names:");
for Name of Help.Names loop
Ada.Text_IO.Put_Line (" " & Name.all);
end loop;
Ada.Text_IO.Put_Line ("Man pages:");
for Name of Man.Names loop
Ada.Text_IO.Put_Line (" " & Name.all);
end loop;
return;
end if;
for I in 1 .. Count loop
Print (Ada.Command_Line.Argument (I));
end loop;
end Show_Help;
|
gcc-gcc-7_3_0-release/gcc/testsuite/gnat.dg/no_exc_prop.ads | best08618/asylo | 7 | 21989 | pragma Restrictions (No_Exception_Propagation);
package no_exc_prop is
protected Simple_Barrier is
entry Wait;
procedure Signal;
private
Signaled : Boolean := False;
end Simple_Barrier;
end no_exc_prop;
|
oeis/343/A343570.asm | neoneye/loda-programs | 11 | 93727 | ; A343570: If n = Product (p_j^k_j) then a(n) = Product (p_j^k_j + 3), with a(1) = 1.
; Submitted by <NAME>
; 1,5,6,7,8,30,10,11,12,40,14,42,16,50,48,19,20,60,22,56,60,70,26,66,28,80,30,70,32,240,34,35,84,100,80,84,40,110,96,88,44,300,46,98,96,130,50,114,52,140,120,112,56,150,112,110,132,160,62,336,64,170,120,67,128,420,70,140,156,400,74
add $0,1
mov $1,1
mov $2,2
lpb $0
mov $3,$0
lpb $3
mov $4,$0
mod $4,$2
add $2,1
cmp $4,0
cmp $4,0
sub $3,$4
lpe
mov $5,1
lpb $0
dif $0,$2
mul $5,$2
lpe
add $5,3
mul $1,$5
lpe
mov $0,$1
|
data/jpred4/jp_batch_1613899824___uvfKOC/jp_batch_1613899824___uvfKOC.als | jonriege/predict-protein-structure | 0 | 1378 | SILENT_MODE
BLOCK_FILE jp_batch_1613899824___uvfKOC.concise.blc
MAX_NSEQ 364
MAX_INPUT_LEN 366
OUTPUT_FILE jp_batch_1613899824___uvfKOC.concise.ps
PORTRAIT
POINTSIZE 8
IDENT_WIDTH 12
X_OFFSET 2
Y_OFFSET 2
DEFINE_FONT 0 Helvetica DEFAULT
DEFINE_FONT 1 Helvetica REL 0.75
DEFINE_FONT 7 Helvetica REL 0.6
DEFINE_FONT 3 Helvetica-Bold DEFAULT
DEFINE_FONT 4 Times-Bold DEFAULT
DEFINE_FONT 5 Helvetica-BoldOblique DEFAULT
#
DEFINE_COLOUR 3 1 0.62 0.67 # Turquiose
DEFINE_COLOUR 4 1 1 0 # Yellow
DEFINE_COLOUR 5 1 0 0 # Red
DEFINE_COLOUR 7 1 0 1 # Purple
DEFINE_COLOUR 8 0 0 1 # Blue
DEFINE_COLOUR 9 0 1 0 # Green
DEFINE_COLOUR 10 0.41 0.64 1.00 # Pale blue
DEFINE_COLOUR 11 0.41 0.82 0.67 # Pale green
DEFINE_COLOUR 50 0.69 0.18 0.37 # Pink (helix)
DEFINE_COLOUR 51 1.00 0.89 0.00 # Gold (strand)
NUMBER_INT 10
SETUP
#
# Highlight specific residues.
# Avoid highlighting Lupas 'C' predictions by
# limiting the highlighting to the alignments
Scol_CHARS C 1 1 237 353 4
Ccol_CHARS H ALL 5
Ccol_CHARS P ALL 8
SURROUND_CHARS LIV ALL
#
# Replace known structure types with whitespace
SUB_CHARS 1 354 237 363 H SPACE
SUB_CHARS 1 354 237 363 E SPACE
SUB_CHARS 1 354 237 363 - SPACE
STRAND 4 357 9
COLOUR_TEXT_REGION 4 357 9 357 51
STRAND 25 357 28
COLOUR_TEXT_REGION 25 357 28 357 51
STRAND 48 357 54
COLOUR_TEXT_REGION 48 357 54 357 51
STRAND 60 357 66
COLOUR_TEXT_REGION 60 357 66 357 51
STRAND 74 357 78
COLOUR_TEXT_REGION 74 357 78 357 51
STRAND 89 357 94
COLOUR_TEXT_REGION 89 357 94 357 51
STRAND 154 357 155
COLOUR_TEXT_REGION 154 357 155 357 51
STRAND 170 357 175
COLOUR_TEXT_REGION 170 357 175 357 51
STRAND 181 357 181
COLOUR_TEXT_REGION 181 357 181 357 51
STRAND 188 357 200
COLOUR_TEXT_REGION 188 357 200 357 51
STRAND 209 357 215
COLOUR_TEXT_REGION 209 357 215 357 51
STRAND 229 357 232
COLOUR_TEXT_REGION 229 357 232 357 51
HELIX 101 357 114
COLOUR_TEXT_REGION 101 357 114 357 50
HELIX 119 357 121
COLOUR_TEXT_REGION 119 357 121 357 50
STRAND 4 362 9
COLOUR_TEXT_REGION 4 362 9 362 51
STRAND 25 362 28
COLOUR_TEXT_REGION 25 362 28 362 51
STRAND 32 362 33
COLOUR_TEXT_REGION 32 362 33 362 51
STRAND 47 362 54
COLOUR_TEXT_REGION 47 362 54 362 51
STRAND 60 362 66
COLOUR_TEXT_REGION 60 362 66 362 51
STRAND 74 362 78
COLOUR_TEXT_REGION 74 362 78 362 51
STRAND 89 362 94
COLOUR_TEXT_REGION 89 362 94 362 51
STRAND 147 362 148
COLOUR_TEXT_REGION 147 362 148 362 51
STRAND 154 362 156
COLOUR_TEXT_REGION 154 362 156 362 51
STRAND 170 362 175
COLOUR_TEXT_REGION 170 362 175 362 51
STRAND 181 362 183
COLOUR_TEXT_REGION 181 362 183 362 51
STRAND 188 362 200
COLOUR_TEXT_REGION 188 362 200 362 51
STRAND 209 362 214
COLOUR_TEXT_REGION 209 362 214 362 51
STRAND 230 362 232
COLOUR_TEXT_REGION 230 362 232 362 51
HELIX 100 362 112
COLOUR_TEXT_REGION 100 362 112 362 50
STRAND 4 363 9
COLOUR_TEXT_REGION 4 363 9 363 51
STRAND 52 363 53
COLOUR_TEXT_REGION 52 363 53 363 51
STRAND 60 363 66
COLOUR_TEXT_REGION 60 363 66 363 51
STRAND 74 363 77
COLOUR_TEXT_REGION 74 363 77 363 51
STRAND 90 363 93
COLOUR_TEXT_REGION 90 363 93 363 51
STRAND 170 363 175
COLOUR_TEXT_REGION 170 363 175 363 51
STRAND 180 363 180
COLOUR_TEXT_REGION 180 363 180 363 51
STRAND 189 363 191
COLOUR_TEXT_REGION 189 363 191 363 51
STRAND 195 363 200
COLOUR_TEXT_REGION 195 363 200 363 51
STRAND 210 363 215
COLOUR_TEXT_REGION 210 363 215 363 51
STRAND 229 363 231
COLOUR_TEXT_REGION 229 363 231 363 51
HELIX 103 363 123
COLOUR_TEXT_REGION 103 363 123 363 50
HELIX 137 363 140
COLOUR_TEXT_REGION 137 363 140 363 50
|
programs/oeis/006/A006645.asm | neoneye/loda | 22 | 99008 | <reponame>neoneye/loda
; A006645: Self-convolution of Pell numbers (A000129).
; 0,0,1,4,14,44,131,376,1052,2888,7813,20892,55338,145428,379655,985520,2545720,6547792,16777993,42847988,109099078,277040572,701794187,1773851304,4474555476,11266301976,28318897549,71070913036,178106093666,445740656420,1114147888655,2781614954080,6937095319664,17282819159456,43016478293521,106970278622436,265779785945214,659829854202444,1636862252136083,4057699877736152,10051975803917452,24885224597450728,61569285018887317,152241087787241852,376232906917472410,929287087422405940,2294148899686824215,5660848708445353488,13961715777800669352,34419283008142267632,84816156743499493657,208918349138065408468,514402235254892906678,1266088332761300567516,3115059307239655329179,7661533273278383146504,18837258912334126750916,46299643541059818826424,113762863939217833888669,279441599752136807751660,686204838053538161172690,1684585053411947874806340,4134401274592950111984671,10144174039581615245883584,24883348557439231099166944,61022855998809945582155584,149613629447441909034769441,366731237522809205332215236,898722918643673989831532782,2201951825740499966940467308,5393822886135973157735173283,13209764980965387532401412152,32344883929983929956541900028,79182762387720552163483615368,193808398880916825453509839525,474278770047325090128503115100,1160422348946600570996516419850,2838715497780364249751536475732,6943093814158038671045590763303,16978976095237698810564721307248,41514432412566660330165041379608,101488686705378724765596823374992,248066883801272744488752734748457,606253456048829188292592405418164,1481410877358689704800311817296166,3619380375426630739895454695979516,8841619038992554052322072792904619,21595818439633366722003542105056616,52741103301483146118987892233202996,128786919795269004082760738855100760,314440579780583703152730929740865965,767628247886230853247447130215393740
mov $2,$0
mov $4,$0
lpb $2
mov $0,$4
sub $2,1
sub $0,$2
lpb $0
sub $0,2
mov $3,$0
mov $0,1
max $3,0
seq $3,26937 ; a(n) = Sum_{k=0..n} (k+1)*T(n,n-k), where T is given by A008288.
lpe
add $1,$3
lpe
mov $0,$1
|
programs/oeis/212/A212519.asm | neoneye/loda | 22 | 91707 | ; A212519: Number of (w,x,y,z) with all terms in {1,...,n} and w>2x and y>=3z.
; 0,0,0,1,4,12,30,63,108,192,300,450,660,936,1260,1715,2240,2880,3672,4617,5670,7000,8470,10164,12144,14400,16848,19773,22932,26460,30450,34875,39600,45056,50864,57222,64260,71928,80028,89167,98800,109200,120540,132741,145530,159720,174570,190440,207552,225792,244800,265625,287300,310284,334854,360855,387828,417088,447412,479370,513300,549000,585900,625611,666624,709632,755040,802593,851598,903992,957950,1014300,1073520,1135296,1198800,1266325,1335700,1407900,1483482,1562067,1642680,1728000,1815480,1906254,2000964,2099160,2199708,2305703,2414192,2526480,2643300,2764125,2887650,3017416,3150034,3286992,3429120,3575808,3725568,3882417
mov $1,$0
sub $1,1
mov $3,$0
sub $0,1
mul $3,$1
sub $0,$3
sub $1,$0
sub $1,$0
mov $0,1
sub $1,$3
lpb $1
sub $1,4
mov $2,$3
div $2,3
add $0,$2
lpe
div $0,2
|
source/units/program-units-subunits.adb | reznikmm/gela | 0 | 5778 | -- SPDX-FileCopyrightText: 2019 <NAME> <<EMAIL>>
--
-- SPDX-License-Identifier: MIT
-------------------------------------------------------------
with Program.Units.Bodies;
package body Program.Units.Subunits is
--------------------
-- Append_Subunit --
--------------------
procedure Append_Subunit
(Self : in out Subunit;
Value : Program.Compilation_Units.Compilation_Unit_Access)
is
begin
Self.Subunits.Append (Value);
end Append_Subunit;
----------------
-- Initialize --
----------------
procedure Initialize
(Self : in out Subunit;
Compilation : Program.Compilations.Compilation_Access;
Full_Name : Text;
Context_Clause : Program.Element_Vectors.Element_Vector_Access;
Unit_Declaration : not null Program.Elements.Element_Access;
Parent_Body : not null Program.Compilation_Units
.Compilation_Unit_Access) is
begin
Self.Initialize
(Compilation => Compilation,
Full_Name => Full_Name,
Context_Clause => Context_Clause,
Unit_Declaration => Unit_Declaration);
Self.Parent_Body := Parent_Body;
if Parent_Body.all in Program.Units.Bodies.Unit_Body then
Program.Units.Bodies.Unit_Body (Parent_Body.all).Append_Subunit
(Self'Unchecked_Access);
else
Subunit (Parent_Body.all).Append_Subunit (Self'Unchecked_Access);
end if;
Self.Subunits.Clear;
end Initialize;
--------------
-- Subunits --
--------------
overriding function Subunits (Self : access Subunit)
return Program.Compilation_Unit_Vectors.Compilation_Unit_Vector_Access is
begin
if Self.Subunits.Is_Empty then
return null;
else
return Self.Subunits'Access;
end if;
end Subunits;
-----------------
-- Parent_Body --
-----------------
overriding function Parent_Body (Self : access Subunit)
return not null Program.Compilation_Units.Compilation_Unit_Access is
begin
return Self.Parent_Body;
end Parent_Body;
end Program.Units.Subunits;
|
Task/Find-limit-of-recursion/AppleScript/find-limit-of-recursion-2.applescript | LaudateCorpus1/RosettaCodeData | 1 | 3077 | <filename>Task/Find-limit-of-recursion/AppleScript/find-limit-of-recursion-2.applescript<gh_stars>1-10
-- HIGHEST CHURCH NUMERAL REPRESENTABLE IN APPLESCRIPT ?
-- (This should be a good proxy for recursion depth)
on run
script unrepresentable
on |λ|(x)
try
churchFromInt(x)
return false
on error
return true
end try
x > 10
end |λ|
end script
"The highest Church-encoded integer representable in Applescript is " & ¬
(|until|(unrepresentable, my succ, 0) - 1)
end run
-- CHURCH NUMERALS ------------------------------------------------------
-- chZero :: (a -> a) -> a -> a
on chZero(f)
script
on |λ|(x)
x
end |λ|
end script
end chZero
-- chSucc :: ((a -> a) -> a -> a) -> (a -> a) -> a -> a
on chSucc(n)
script
on |λ|(f)
script
property mf : mReturn(f)'s |λ|
on |λ|(x)
mf(mReturn(n)'s |λ|(mf)'s |λ|(x))
end |λ|
end script
end |λ|
end script
end chSucc
-- churchFromInt :: Int -> (a -> a) -> a -> a
on churchFromInt(x)
script go
on |λ|(i)
if 0 < i then
chSucc(|λ|(i - 1))
else
chZero
end if
end |λ|
end script
go's |λ|(x)
end churchFromInt
-- intFromChurch :: ((Int -> Int) -> Int -> Int) -> Int
on intFromChurch(cn)
mReturn(cn)'s |λ|(my succ)'s |λ|(0)
end intFromChurch
-- GENERIC FUNCTIONS ----------------------------------------
-- until :: (a -> Bool) -> (a -> a) -> a -> a
on |until|(p, f, x)
set v to x
set mp to mReturn(p)
set mf to mReturn(f)
repeat until mp's |λ|(v)
set v to mf's |λ|(v)
end repeat
end |until|
-- Lift 2nd class handler function into 1st class script wrapper
-- mReturn :: First-class m => (a -> b) -> m (a -> b)
on mReturn(f)
if class of f is script then
f
else
script
property |λ| : f
end script
end if
end mReturn
-- succ :: Enum a => a -> a
on succ(x)
1 + x
end succ
|
.emacs.d/elpa/wisi-3.1.3/wisitoken-generate-lr-lalr_generate.ads | caqg/linux-home | 0 | 4880 | <filename>.emacs.d/elpa/wisi-3.1.3/wisitoken-generate-lr-lalr_generate.ads
-- Abstract :
--
-- Generalized LALR parse table generator.
--
-- Copyright (C) 2002 - 2003, 2009 - 2010, 2013 - 2015, 2017 - 2020 Free Software Foundation, Inc.
--
-- This file is part of the WisiToken package.
--
-- The WisiToken package is free software; you can redistribute it
-- and/or modify it under terms of the GNU General Public License as
-- published by the Free Software Foundation; either version 3, or
-- (at your option) any later version. This library is distributed in
-- the hope that it will be useful, but WITHOUT ANY WARRANTY; without
-- even the implied warranty of MERCHAN- TABILITY or FITNESS FOR A
-- PARTICULAR PURPOSE.
--
-- As a special exception under Section 7 of GPL version 3, you are granted
-- additional permissions described in the GCC Runtime Library Exception,
-- version 3.1, as published by the Free Software Foundation.
pragma License (Modified_GPL);
with WisiToken.Generate.LR1_Items;
with WisiToken.Productions;
package WisiToken.Generate.LR.LALR_Generate is
function Generate
(Grammar : in out WisiToken.Productions.Prod_Arrays.Vector;
Descriptor : in WisiToken.Descriptor;
Known_Conflicts : in Conflict_Lists.List := Conflict_Lists.Empty_List;
McKenzie_Param : in McKenzie_Param_Type := Default_McKenzie_Param;
Parse_Table_File_Name : in String := "";
Include_Extra : in Boolean := False;
Ignore_Conflicts : in Boolean := False;
Partial_Recursion : in Boolean := True)
return Parse_Table_Ptr
with Pre =>
Descriptor.Last_Lookahead = Descriptor.First_Nonterminal and
Descriptor.First_Nonterminal = Descriptor.Accept_ID;
-- Generate a generalized LALR parse table for Grammar. The
-- grammar start symbol is the LHS of the first production in
-- Grammar.
--
-- Unless Ignore_Unused_Tokens is True, raise Grammar_Error if
-- there are unused tokens.
--
-- Unless Ignore_Unknown_Conflicts is True, raise Grammar_Error if there
-- are unknown conflicts.
----------
-- Visible for unit tests
function LALR_Goto_Transitions
(Kernel : in LR1_Items.Item_Set;
Symbol : in Token_ID;
First_Nonterm_Set : in Token_Array_Token_Set;
Grammar : in WisiToken.Productions.Prod_Arrays.Vector;
Descriptor : in WisiToken.Descriptor)
return LR1_Items.Item_Set;
-- Return the Item_Set that is the goto for Symbol from Kernel.
-- If there is no such Item_Set, Result.Set is null.
function LALR_Kernels
(Grammar : in WisiToken.Productions.Prod_Arrays.Vector;
First_Nonterm_Set : in Token_Array_Token_Set;
Descriptor : in WisiToken.Descriptor)
return LR1_Items.Item_Set_List;
procedure Fill_In_Lookaheads
(Grammar : in WisiToken.Productions.Prod_Arrays.Vector;
Has_Empty_Production : in Token_ID_Set;
First_Terminal_Sequence : in Token_Sequence_Arrays.Vector;
Kernels : in out LR1_Items.Item_Set_List;
Descriptor : in WisiToken.Descriptor);
procedure Add_Actions
(Kernels : in LR1_Items.Item_Set_List;
Grammar : in WisiToken.Productions.Prod_Arrays.Vector;
Has_Empty_Production : in Token_ID_Set;
First_Nonterm_Set : in Token_Array_Token_Set;
First_Terminal_Sequence : in Token_Sequence_Arrays.Vector;
Conflict_Counts : out Conflict_Count_Lists.List;
Conflicts : out Conflict_Lists.List;
Table : in out Parse_Table;
Descriptor : in WisiToken.Descriptor);
end WisiToken.Generate.LR.LALR_Generate;
|
exp/t42.asm | nishuiq/Assembly-Learning | 0 | 29389 | <reponame>nishuiq/Assembly-Learning
assume cs:code
code segment
mov ax,cs ;______ 代码补全
mov ds,ax
mov ax,0020h
mov es,ax
mov bx,0
mov cx,0017h ;______ 先随意置入一个数，再Debug进行反编译查看 mov ax, 4c00h 的地址
s:
mov al,[bx]
mov es:[bx],al
inc bx
loop s
mov ax,4c00h
int 21h
code ends
end |
alloy4fun_models/trashltl/models/10/njrJKHN2trvb963vj.als | Kaixi26/org.alloytools.alloy | 0 | 1441 | <filename>alloy4fun_models/trashltl/models/10/njrJKHN2trvb963vj.als
open main
pred idnjrJKHN2trvb963vj_prop11 {
Protected' = ((File - Protected)-Trash)
}
pred __repair { idnjrJKHN2trvb963vj_prop11 }
check __repair { idnjrJKHN2trvb963vj_prop11 <=> prop11o } |
src/offmt_lib-storage.ads | Fabien-Chouteau/offmt-tool | 0 | 16123 | <filename>src/offmt_lib-storage.ads
with Ada.Strings.Unbounded;
package Offmt_Lib.Storage is
type Store_Result (Success : Boolean) is record
case Success is
when True => null;
when False =>
Msg : Ada.Strings.Unbounded.Unbounded_String;
end case;
end record;
function Store (Map : Trace_Map; Filename : String) return Store_Result;
type Load_Result (Success : Boolean) is record
case Success is
when True =>
Map : Trace_Map;
when False =>
Msg : Ada.Strings.Unbounded.Unbounded_String;
end case;
end record;
function Load (Filename : String) return Load_Result;
end Offmt_Lib.Storage;
|
source/nodes/program-nodes-constrained_array_types.ads | optikos/oasis | 0 | 18382 | -- Copyright (c) 2019 <NAME> <<EMAIL>>
--
-- SPDX-License-Identifier: MIT
-- License-Filename: LICENSE
-------------------------------------------------------------
with Program.Lexical_Elements;
with Program.Elements.Discrete_Ranges;
with Program.Elements.Component_Definitions;
with Program.Elements.Constrained_Array_Types;
with Program.Element_Visitors;
package Program.Nodes.Constrained_Array_Types is
pragma Preelaborate;
type Constrained_Array_Type is
new Program.Nodes.Node
and Program.Elements.Constrained_Array_Types.Constrained_Array_Type
and Program.Elements.Constrained_Array_Types
.Constrained_Array_Type_Text
with private;
function Create
(Array_Token : not null Program.Lexical_Elements
.Lexical_Element_Access;
Left_Bracket_Token : not null Program.Lexical_Elements
.Lexical_Element_Access;
Index_Subtypes : not null Program.Elements.Discrete_Ranges
.Discrete_Range_Vector_Access;
Right_Bracket_Token : not null Program.Lexical_Elements
.Lexical_Element_Access;
Of_Token : not null Program.Lexical_Elements
.Lexical_Element_Access;
Component_Definition : not null Program.Elements.Component_Definitions
.Component_Definition_Access)
return Constrained_Array_Type;
type Implicit_Constrained_Array_Type is
new Program.Nodes.Node
and Program.Elements.Constrained_Array_Types.Constrained_Array_Type
with private;
function Create
(Index_Subtypes : not null Program.Elements.Discrete_Ranges
.Discrete_Range_Vector_Access;
Component_Definition : not null Program.Elements.Component_Definitions
.Component_Definition_Access;
Is_Part_Of_Implicit : Boolean := False;
Is_Part_Of_Inherited : Boolean := False;
Is_Part_Of_Instance : Boolean := False)
return Implicit_Constrained_Array_Type
with Pre =>
Is_Part_Of_Implicit or Is_Part_Of_Inherited or Is_Part_Of_Instance;
private
type Base_Constrained_Array_Type is
abstract new Program.Nodes.Node
and Program.Elements.Constrained_Array_Types.Constrained_Array_Type
with record
Index_Subtypes : not null Program.Elements.Discrete_Ranges
.Discrete_Range_Vector_Access;
Component_Definition : not null Program.Elements.Component_Definitions
.Component_Definition_Access;
end record;
procedure Initialize
(Self : aliased in out Base_Constrained_Array_Type'Class);
overriding procedure Visit
(Self : not null access Base_Constrained_Array_Type;
Visitor : in out Program.Element_Visitors.Element_Visitor'Class);
overriding function Index_Subtypes
(Self : Base_Constrained_Array_Type)
return not null Program.Elements.Discrete_Ranges
.Discrete_Range_Vector_Access;
overriding function Component_Definition
(Self : Base_Constrained_Array_Type)
return not null Program.Elements.Component_Definitions
.Component_Definition_Access;
overriding function Is_Constrained_Array_Type_Element
(Self : Base_Constrained_Array_Type)
return Boolean;
overriding function Is_Type_Definition_Element
(Self : Base_Constrained_Array_Type)
return Boolean;
overriding function Is_Definition_Element
(Self : Base_Constrained_Array_Type)
return Boolean;
type Constrained_Array_Type is
new Base_Constrained_Array_Type
and Program.Elements.Constrained_Array_Types.Constrained_Array_Type_Text
with record
Array_Token : not null Program.Lexical_Elements
.Lexical_Element_Access;
Left_Bracket_Token : not null Program.Lexical_Elements
.Lexical_Element_Access;
Right_Bracket_Token : not null Program.Lexical_Elements
.Lexical_Element_Access;
Of_Token : not null Program.Lexical_Elements
.Lexical_Element_Access;
end record;
overriding function To_Constrained_Array_Type_Text
(Self : aliased in out Constrained_Array_Type)
return Program.Elements.Constrained_Array_Types
.Constrained_Array_Type_Text_Access;
overriding function Array_Token
(Self : Constrained_Array_Type)
return not null Program.Lexical_Elements.Lexical_Element_Access;
overriding function Left_Bracket_Token
(Self : Constrained_Array_Type)
return not null Program.Lexical_Elements.Lexical_Element_Access;
overriding function Right_Bracket_Token
(Self : Constrained_Array_Type)
return not null Program.Lexical_Elements.Lexical_Element_Access;
overriding function Of_Token
(Self : Constrained_Array_Type)
return not null Program.Lexical_Elements.Lexical_Element_Access;
type Implicit_Constrained_Array_Type is
new Base_Constrained_Array_Type
with record
Is_Part_Of_Implicit : Boolean;
Is_Part_Of_Inherited : Boolean;
Is_Part_Of_Instance : Boolean;
end record;
overriding function To_Constrained_Array_Type_Text
(Self : aliased in out Implicit_Constrained_Array_Type)
return Program.Elements.Constrained_Array_Types
.Constrained_Array_Type_Text_Access;
overriding function Is_Part_Of_Implicit
(Self : Implicit_Constrained_Array_Type)
return Boolean;
overriding function Is_Part_Of_Inherited
(Self : Implicit_Constrained_Array_Type)
return Boolean;
overriding function Is_Part_Of_Instance
(Self : Implicit_Constrained_Array_Type)
return Boolean;
end Program.Nodes.Constrained_Array_Types;
|
programs/oeis/021/A021578.asm | neoneye/loda | 22 | 102925 | ; A021578: Decimal expansion of 1/574.
; 0,0,1,7,4,2,1,6,0,2,7,8,7,4,5,6,4,4,5,9,9,3,0,3,1,3,5,8,8,8,5,0,1,7,4,2,1,6,0,2,7,8,7,4,5,6,4,4,5,9,9,3,0,3,1,3,5,8,8,8,5,0,1,7,4,2,1,6,0,2,7,8,7,4,5,6,4,4,5,9,9,3,0,3,1,3,5,8,8,8,5,0,1,7,4,2,1,6,0
add $0,1
mov $1,10
pow $1,$0
mul $1,6
div $1,3444
mod $1,10
mov $0,$1
|
programs/oeis/037/A037251.asm | neoneye/loda | 22 | 244956 | ; A037251: a(n) = n^3*(n^3 + 1)*(n-1).
; 0,0,72,1512,12480,63000,234360,707952,1838592,4257360,9009000,17728920,32864832,57948072,97919640,159516000,251719680,386279712,578306952,846949320,1216152000,1715507640,2381201592,3257057232,4395686400,5859750000,7723333800,10073444472,13011630912,16655735880,21141783000,26626004160,33287012352,41328124992,50979842760,62502489000,76189014720,92367974232,111406676472,133714517040,159746496000,190006926480,225053339112,265500587352,312025158720,365369697000,426347740440,495848680992,574842949632,664387432800,765631125000,879821022600,1008308263872,1152554520312,1314138644280,1494763578000,1696263528960,1920611416752,2169926596392,2446482863160,2752716744000,3091236080520,3464828908632,3876472639872,4329343549440,4826826576000,5372525438280,5970273073512,6624142402752,7338457428120,8117804667000,8967044928240,9891325435392,10896092302032,11987103364200,13170441375000,14452527566400,15840135583272,17340405794712,18960859987680,20709416448000,22594405433760,24624585046152,26809157502792,29157785818560,31680610899000,34388269051320,37291909918032,40403214838272,43734415641840,47298313881000,51108300505080,55178375982912,59523170878152,64157966882520,69098718312000,74362074071040,79965400089792,85926802239432,92265149730600
mov $1,$0
sub $0,1
mov $3,$1
mul $3,$1
mov $2,$3
pow $2,2
add $2,$1
mul $2,$3
mul $0,$2
|
3-mid/opengl/source/lean/geometry/opengl-primitive-long_indexed.adb | charlie5/lace | 20 | 690 | <reponame>charlie5/lace
with
openGL.Errors,
openGL.Buffer,
openGL.Tasks,
GL.Binding,
ada.unchecked_Deallocation;
package body openGL.Primitive.long_indexed
is
---------
--- Forge
--
procedure define (Self : in out Item; Kind : in facet_Kind;
Indices : in long_Indices)
is
use Buffer.long_indices.Forge;
buffer_Indices : aliased long_Indices := (Indices'Range => <>);
begin
for Each in buffer_Indices'Range
loop
buffer_Indices (Each) := Indices (Each) - 1; -- Adjust indices to zero-based-indexing for GL.
end loop;
Self.facet_Kind := Kind;
Self.Indices := new Buffer.long_indices.Object' (to_Buffer (buffer_Indices'Access,
usage => Buffer.static_Draw));
end define;
function new_Primitive (Kind : in facet_Kind;
Indices : in long_Indices) return Primitive.long_indexed.view
is
Self : constant View := new Item;
begin
define (Self.all, Kind, Indices);
return Self;
end new_Primitive;
overriding
procedure destroy (Self : in out Item)
is
procedure free is new ada.unchecked_Deallocation (Buffer.long_indices.Object'Class,
Buffer.long_indices.view);
begin
Buffer.destroy (Self.Indices.all);
free (Self.Indices);
end destroy;
--------------
-- Attributes
--
procedure Indices_are (Self : in out Item; Now : in long_Indices)
is
use Buffer.long_indices;
buffer_Indices : aliased long_Indices := (Now'Range => <>);
begin
for Each in buffer_Indices'Range
loop
buffer_Indices (Each) := Now (Each) - 1; -- Adjust indices to zero-based-indexing for GL.
end loop;
Self.Indices.set (to => buffer_Indices);
end Indices_are;
--------------
-- Operations
--
overriding
procedure render (Self : in out Item)
is
use GL,
GL.Binding;
begin
Tasks.check;
openGL.Primitive.item (Self).render; -- Do base class render.
Self.Indices.enable;
glDrawElements (Thin (Self.facet_Kind),
gl.GLint (Self.Indices.Length),
GL_UNSIGNED_INT,
null);
Errors.log;
end render;
end openGL.Primitive.long_indexed;
|
deepppl/parser/stan.g4 | jburroni/deepppl | 0 | 3711 | <filename>deepppl/parser/stan.g4
/*
* Copyright 2018 IBM Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
grammar stan;
/** Includes (section 2.2) */
// XXX TODO: #include file.stan XXX
/** Comments (section 2.3) */
COMMENT
: '/*' .*? '*/' -> channel(3) // COMMENTS
;
LINE_COMMENT
: '//' ~[\r\n]* -> channel(3) //COMMENTS
;
/** Whitespaces (section 2.4) */
WS : [ \t\r\n\u000C]+ -> channel(1) // WHITESPACES
;
/** Numeric literals (section 4.1) */
IntegerLiteral
: DecimalNumeral
;
RealLiteral:
Digits '.' Digits? ExponentPart?
| '.' Digits ExponentPart?
| Digits ExponentPart
;
fragment
ExponentPart:
('e'|'E') ('+'|'-')? Digits
;
fragment
DecimalNumeral
: '0'
| NonZeroDigit Digits?
;
fragment
Digits
: Digit+
;
fragment
Digit
: '0'
| NonZeroDigit
;
fragment
NonZeroDigit
: [1-9]
;
StringLiteral
: '"' ([a-z]|[A-Z]|[0-9]|Symbol)* '"'
;
fragment
Symbol
: '~'
| '@'
| '#'
| '$'
| '%'
| '^'
| '&'
| '*'
| '_'
| '\''
| '`'
| '-'
| '+'
| '='
| '{'
| ' '
| '}'
| '['
| ']'
| '('
| ')'
| '<'
| '>'
| '|'
| '/'
| '!'
| '?'
| '.'
| ','
| ';'
| ':'
;
/** Variables and keywords (section 4.2) */
/* Keywords */
FOR: 'for';
IN: 'in';
WHILE: 'while';
REPEAT: 'repeat';
UNTIL: 'until';
IF: 'if';
THEN: 'then';
ELSE: 'else';
TRUE: 'true';
FALSE: 'false';
/* Type names */
INT: 'int';
REAL: 'real';
VECTOR: 'vector';
SIMPLEX: 'simplex';
ORDERED: 'ordered';
POSITIVE_ORDERED: 'positive_ordered';
ROW_VECTOR: 'row_vector';
UNIT_VECTOR: 'unit_vector';
MATRIX: 'matrix';
CHOLESKY_FACTOR_CORR: 'cholesky_factor_corr';
CHOLESKY_FACTOR_COV: 'cholesky_factor_cov';
CORR_MATRIX: 'corr_matrix';
COV_MATRIX: 'cov_matrix';
/* Block identifiers */
FUNCTIONS: 'functions';
MODEL: 'model';
DATA: 'data';
PARAMETERS: 'parameters';
QUANTITIES: 'quantities';
TRANSFORMED: 'transformed';
GENERATED: 'generated';
/* Reserved Names from Stan Implementation */
VAR: 'var';
FVAR: 'fvar';
STAN_MAJOR: 'STAN_MAJOR';
STAN_MINOR: 'STAN_MINOR';
STAN_PATCH: 'STAN_PATCH';
STAN_MATH_MAJOR: 'STAN_MATH_MAJOR';
STAN_MATH_MINOR: 'STAN_MATH_MINOR';
STAN_MATH_PATCH: 'STAN_MATH_PATCH';
/* Reserved Names from C++ */
ALIGNAS: 'alignas';
ALIGNOF: 'alignof';
AND: 'and';
AND_EQ: 'and_eq';
ASM: 'asm';
AUTO: 'auto';
BITAND: 'bitand';
BITOR: 'bitor';
BOOL: 'bool';
BREAK: 'break';
CASE: 'case';
CATCH: 'catch';
CHAR: 'char';
CHAR16_T: 'char16_t';
CHAR32_T: 'char32_t';
CLASS: 'class';
COMPL: 'compl';
CONST: 'const';
CONSTEXPR: 'constexpr';
CONST_CAST: 'const_cast';
CONTINUE: 'continue';
DECLTYPE: 'decltype';
DEFAULT: 'default';
DELETE: 'delete';
DO: 'do';
DOUBLE: 'double';
DYNAMIC_CAST: 'dynamic_cast';
ENUM: 'enum';
EXPLICIT: 'explicit';
EXPORT: 'export';
EXTERN: 'extern';
FLOAT: 'float';
FRIEND: 'friend';
GOTO: 'goto';
INLINE: 'inline';
LONG: 'long';
MUTABLE: 'mutable';
NAMESPACE: 'namespace';
NEW: 'new';
NOEXCEPT: 'noexcept';
NOT: 'not';
NOT_EQ: 'not_eq';
NULLPTR: 'nullptr';
OPERATOR: 'operator';
OR: 'or';
OR_EQ: 'or_eq';
PRIVATE: 'private';
PROTECTED: 'protected';
PUBLIC: 'public';
REGISTER: 'register';
REINTERPRET_CAST: 'reinterpret_cast';
RETURN: 'return';
SHORT: 'short';
SIGNED: 'signed';
SIZEOF: 'sizeof';
STATIC: 'static';
STATIC_ASSERT: 'static_assert';
STATIC_CAST: 'static_cast';
STRUCT: 'struct';
SWITCH: 'switch';
TEMPLATE: 'template';
THIS: 'this';
THREAD_LOCAL: 'thread_local';
THROW: 'throw';
TRY: 'try';
TYPEDEF: 'typedef';
TYPEID: 'typeid';
TYPENAME: 'typename';
UNION: 'union';
UNSIGNED: 'unsigned';
USING: 'using';
VIRTUAL: 'virtual';
VOID: 'void';
VOLATILE: 'volatile';
WCHAR_T: 'wchar_t';
XOR: 'xor';
XOR_EQ: 'xor_eq';
/* Variables */
BAD_IDENTIFIER
: [a-zA-Z] [a-zA-Z0-9_]* '__'
;
IDENTIFIER
: [a-zA-Z] [a-zA-Z0-9_]*
;
/* Operators (figure 4.1) */
OR_OP: '||';
AND_OP: '&&';
EQ_OP: '==';
NEQ_OP: '!=';
LT_OP: '<';
LE_OP: '<=';
GT_OP: '>';
GE_OP: '>=';
PLUS_OP: '+';
MINUS_OP: '-';
MULT_OP: '*';
DIV_OP: '/';
MOD_OP: '%';
LEFT_DIV_OP: '\\';
DOT_MULT_OP: '.*';
DOT_DIV_OP: './';
NOT_OP: '!';
POW_OP: '^';
TRANSPOSE_OP: '\'';
PLUS_EQ: '+=';
MINUS_EQ: '-=';
MULT_EQ: '*=';
DIV_EQ: '/=';
DOT_MULT_EQ: '.*=';
DOT_DIV_EQ: './=';
/* Types (section 3.1) */
primitiveType
: REAL
| INT
;
vectorType
: VECTOR
| SIMPLEX
| UNIT_VECTOR
| ORDERED
| POSITIVE_ORDERED
| ROW_VECTOR
;
matrixType
: MATRIX
| CORR_MATRIX
| COV_MATRIX
| CHOLESKY_FACTOR_COV
| CHOLESKY_FACTOR_CORR
;
type_
: primitiveType typeConstraints? ('[' ']')?
| vectorType typeConstraints? ('[' expression ']')?
| matrixType typeConstraints? ('[' expression (',' expression)? ']')?
;
typeConstraints
: '<' typeConstraintList '>'
;
typeConstraintList
: typeConstraint (',' typeConstraint)*
;
typeConstraint
: IDENTIFIER '=' atom
;
variableDecl
: type_ IDENTIFIER arrayDim? ';'
| type_ IDENTIFIER arrayDim? '=' expression ';'
;
arrayDim
: '[' expressionCommaList ']'
;
variableDeclsOpt
: variableDecl*
;
/** Numeric Litterals (section 4.1) */
constant
: IntegerLiteral
| RealLiteral
;
/** Variable (section 4.2) */
variable
: IDENTIFIER
;
/** Vector, matrix and array expressions (section 4.2) */
vectorExpr
: '[' expressionCommaList ']'
;
arrayExpr
: '{' expressionCommaList '}'
;
atom
: constant
| variable
| vectorExpr
| arrayExpr
| atom '[' indexExpression ']'
| atom '(' expressionCommaListOpt ')'
| '(' expression ')'
;
expression
: atom
| expression TRANSPOSE_OP
| <assoc=right> e1=expression POW_OP e2=expression
| op=(NOT_OP|PLUS_OP|MINUS_OP) expression
| e1=expression op=(DOT_MULT_OP|DOT_DIV_OP) e2=expression
| e1=expression LEFT_DIV_OP e2=expression
| e1=expression op=(MULT_OP|DIV_OP|MOD_OP) e2=expression
| e1=expression op=(PLUS_OP|MINUS_OP) e2=expression
| e1=expression op=(LT_OP|LE_OP|GT_OP|GE_OP) e2=expression
| e1=expression op=(EQ_OP|NEQ_OP) e2=expression
| e1=expression AND_OP e2=expression
| e1=expression OR_OP e2=expression
| <assoc=right> e1=expression '?' e2=expression ':' e3=expression
;
indexExpression
: expressionCommaListOpt
| e1=expression? ':' e2=expression?
;
expressionCommaList
: expression (',' expression)*
;
expressionCommaListOpt
: expressionCommaList?
;
/** Statements (section 5) */
/** Assignment (section 5.1) */
lvalue
: IDENTIFIER
| IDENTIFIER '[' expressionCommaList ']'
;
assignStmt
: lvalue '=' expression ';'
| lvalue op=(PLUS_EQ|MINUS_EQ|MULT_EQ|DIV_EQ|DOT_MULT_EQ|DOT_DIV_EQ) expression ';'
;
/** Sampling (section 5.3) */
lvalueSampling
: lvalue
| expression
;
samplingStmt
: lvalueSampling '~' IDENTIFIER '(' expressionCommaList ')' truncation? ';'
| lvalueSampling PLUS_EQ IDENTIFIER '(' IDENTIFIER '|' expressionCommaList ')' ';'
;
truncation
: 'T' '[' e1=expression? ',' e1=expression? ']'
;
/** For loops (section 5.4) */
forStmt
: FOR '(' IDENTIFIER IN atom ':' atom ')' statement
| FOR '(' IDENTIFIER IN atom ')' statement
;
/** Conditional statements (section 5.5) */
conditionalStmt
: IF '(' expression ')' s1=statement (ELSE s2=statement)?
;
/** While loops (section 5.6) */
whileStmt
: WHILE '(' expression ')' statement
;
/** Blocks (section 5.7) */
blockStmt
: '{' variableDeclsOpt statementsOpt '}'
;
/** Functions calls (sections 5.9 and 5.10) */
callStmt
: IDENTIFIER '(' expressionOrStringCommaList ')' ';'
;
expressionOrString
: expression
| StringLiteral
;
expressionOrStringCommaList:
| expressionOrString (',' expressionOrString)*
;
/** statements */
statement
: assignStmt
| samplingStmt
| forStmt
| conditionalStmt
| whileStmt
| blockStmt
| callStmt
| BREAK ';'
| CONTINUE ';'
;
statementsOpt
: statement*
;
/** Functions (section 7) */
functionType
: type_ IDENTIFIER '(' parameterCommaListopt ')'
| VOID IDENTIFIER '(' parameterCommaListopt ')'
;
parameterDecl
: type_ IDENTIFIER
;
parameterCommaList
: parameterDecl (',' parameterDecl)*
;
parameterCommaListopt
: parameterCommaList?
;
functionStatement
: statement
| RETURN expression ';'
| RETURN ';'
;
functionStatementsOpt
: functionStatement*
;
functionDecl
: functionType '{' variableDeclsOpt functionStatementsOpt '}'
| functionType ';'
;
functionDeclsOpt
: functionDecl*
;
/** Program blocks (section 6) */
functionBlock
: FUNCTIONS '{' functionDeclsOpt '}'
;
dataBlock
: DATA '{' variableDeclsOpt '}'
;
transformedDataBlock
: TRANSFORMED DATA '{' variableDeclsOpt statementsOpt '}'
;
parametersBlock
: PARAMETERS '{' variableDeclsOpt '}'
;
transformedParametersBlock
: TRANSFORMED PARAMETERS '{' variableDeclsOpt statementsOpt '}'
;
modelBlock
: MODEL '{' variableDeclsOpt statementsOpt '}'
;
generatedQuantitiesBlock
: GENERATED QUANTITIES '{' variableDeclsOpt statementsOpt '}'
;
program
: functionBlock?
dataBlock?
transformedDataBlock?
parametersBlock?
transformedParametersBlock?
modelBlock?
generatedQuantitiesBlock?
;
|
tools-src/gnu/gcc/gcc/ada/prj-tree.adb | enfoTek/tomato.linksys.e2000.nvram-mod | 80 | 25625 | <gh_stars>10-100
------------------------------------------------------------------------------
-- --
-- GNAT COMPILER COMPONENTS --
-- --
-- P R J . T R E E --
-- --
-- B o d y --
-- --
-- $Revision$
-- --
-- Copyright (C) 2001 Free Software Foundation, Inc. --
-- --
-- GNAT is free software; you can redistribute it and/or modify it under --
-- terms of the GNU General Public License as published by the Free Soft- --
-- ware Foundation; either version 2, or (at your option) any later ver- --
-- sion. GNAT is distributed in the hope that it will be useful, but WITH- --
-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY --
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --
-- for more details. You should have received a copy of the GNU General --
-- Public License distributed with GNAT; see file COPYING. If not, write --
-- to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, --
-- MA 02111-1307, USA. --
-- --
-- GNAT was originally developed by the GNAT team at New York University. --
-- Extensive contributions were provided by Ada Core Technologies Inc. --
-- --
------------------------------------------------------------------------------
with Stringt; use Stringt;
package body Prj.Tree is
use Tree_Private_Part;
--------------------------------
-- Associative_Array_Index_Of --
--------------------------------
function Associative_Array_Index_Of
(Node : Project_Node_Id)
return String_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
(Project_Nodes.Table (Node).Kind = N_Attribute_Declaration));
return Project_Nodes.Table (Node).Value;
end Associative_Array_Index_Of;
----------------------
-- Case_Insensitive --
----------------------
function Case_Insensitive (Node : Project_Node_Id) return Boolean is
begin
pragma Assert
(Node /= Empty_Node
and then
(Project_Nodes.Table (Node).Kind = N_Attribute_Declaration));
return Project_Nodes.Table (Node).Case_Insensitive;
end Case_Insensitive;
--------------------------------
-- Case_Variable_Reference_Of --
--------------------------------
function Case_Variable_Reference_Of
(Node : Project_Node_Id)
return Project_Node_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Case_Construction);
return Project_Nodes.Table (Node).Field1;
end Case_Variable_Reference_Of;
-----------------------
-- Current_Item_Node --
-----------------------
function Current_Item_Node
(Node : Project_Node_Id)
return Project_Node_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Declarative_Item);
return Project_Nodes.Table (Node).Field1;
end Current_Item_Node;
------------------
-- Current_Term --
------------------
function Current_Term
(Node : Project_Node_Id)
return Project_Node_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Term);
return Project_Nodes.Table (Node).Field1;
end Current_Term;
--------------------------
-- Default_Project_Node --
--------------------------
function Default_Project_Node
(Of_Kind : Project_Node_Kind;
And_Expr_Kind : Variable_Kind := Undefined)
return Project_Node_Id
is
begin
Project_Nodes.Increment_Last;
Project_Nodes.Table (Project_Nodes.Last) :=
(Kind => Of_Kind,
Location => No_Location,
Directory => No_Name,
Expr_Kind => And_Expr_Kind,
Variables => Empty_Node,
Packages => Empty_Node,
Pkg_Id => Empty_Package,
Name => No_Name,
Path_Name => No_Name,
Value => No_String,
Field1 => Empty_Node,
Field2 => Empty_Node,
Field3 => Empty_Node,
Case_Insensitive => False);
return Project_Nodes.Last;
end Default_Project_Node;
------------------
-- Directory_Of --
------------------
function Directory_Of (Node : Project_Node_Id) return Name_Id is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Project);
return Project_Nodes.Table (Node).Directory;
end Directory_Of;
------------------------
-- Expression_Kind_Of --
------------------------
function Expression_Kind_Of (Node : Project_Node_Id) return Variable_Kind is
begin
pragma Assert
(Node /= Empty_Node
and then
(Project_Nodes.Table (Node).Kind = N_Literal_String
or else
Project_Nodes.Table (Node).Kind = N_Attribute_Declaration
or else
Project_Nodes.Table (Node).Kind = N_Variable_Declaration
or else
Project_Nodes.Table (Node).Kind = N_Typed_Variable_Declaration
or else
Project_Nodes.Table (Node).Kind = N_Expression
or else
Project_Nodes.Table (Node).Kind = N_Term
or else
Project_Nodes.Table (Node).Kind = N_Variable_Reference
or else
Project_Nodes.Table (Node).Kind = N_Attribute_Reference));
return Project_Nodes.Table (Node).Expr_Kind;
end Expression_Kind_Of;
-------------------
-- Expression_Of --
-------------------
function Expression_Of
(Node : Project_Node_Id)
return Project_Node_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
(Project_Nodes.Table (Node).Kind = N_Attribute_Declaration
or else
Project_Nodes.Table (Node).Kind = N_Typed_Variable_Declaration
or else
Project_Nodes.Table (Node).Kind = N_Variable_Declaration));
return Project_Nodes.Table (Node).Field1;
end Expression_Of;
---------------------------
-- External_Reference_Of --
---------------------------
function External_Reference_Of
(Node : Project_Node_Id)
return Project_Node_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_External_Value);
return Project_Nodes.Table (Node).Field1;
end External_Reference_Of;
-------------------------
-- External_Default_Of --
-------------------------
function External_Default_Of
(Node : Project_Node_Id)
return Project_Node_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_External_Value);
return Project_Nodes.Table (Node).Field2;
end External_Default_Of;
------------------------
-- First_Case_Item_Of --
------------------------
function First_Case_Item_Of
(Node : Project_Node_Id)
return Project_Node_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Case_Construction);
return Project_Nodes.Table (Node).Field2;
end First_Case_Item_Of;
---------------------
-- First_Choice_Of --
---------------------
function First_Choice_Of
(Node : Project_Node_Id)
return Project_Node_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Case_Item);
return Project_Nodes.Table (Node).Field1;
end First_Choice_Of;
-------------------------------
-- First_Declarative_Item_Of --
-------------------------------
function First_Declarative_Item_Of
(Node : Project_Node_Id)
return Project_Node_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
(Project_Nodes.Table (Node).Kind = N_Project_Declaration
or else
Project_Nodes.Table (Node).Kind = N_Case_Item
or else
Project_Nodes.Table (Node).Kind = N_Package_Declaration));
if Project_Nodes.Table (Node).Kind = N_Project_Declaration then
return Project_Nodes.Table (Node).Field1;
else
return Project_Nodes.Table (Node).Field2;
end if;
end First_Declarative_Item_Of;
------------------------------
-- First_Expression_In_List --
------------------------------
function First_Expression_In_List
(Node : Project_Node_Id)
return Project_Node_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Literal_String_List);
return Project_Nodes.Table (Node).Field1;
end First_Expression_In_List;
--------------------------
-- First_Literal_String --
--------------------------
function First_Literal_String
(Node : Project_Node_Id)
return Project_Node_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_String_Type_Declaration);
return Project_Nodes.Table (Node).Field1;
end First_Literal_String;
----------------------
-- First_Package_Of --
----------------------
function First_Package_Of
(Node : Project_Node_Id)
return Package_Declaration_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Project);
return Project_Nodes.Table (Node).Packages;
end First_Package_Of;
--------------------------
-- First_String_Type_Of --
--------------------------
function First_String_Type_Of
(Node : Project_Node_Id)
return Project_Node_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Project);
return Project_Nodes.Table (Node).Field3;
end First_String_Type_Of;
----------------
-- First_Term --
----------------
function First_Term
(Node : Project_Node_Id)
return Project_Node_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Expression);
return Project_Nodes.Table (Node).Field1;
end First_Term;
-----------------------
-- First_Variable_Of --
-----------------------
function First_Variable_Of
(Node : Project_Node_Id)
return Variable_Node_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
(Project_Nodes.Table (Node).Kind = N_Project
or else
Project_Nodes.Table (Node).Kind = N_Package_Declaration));
return Project_Nodes.Table (Node).Variables;
end First_Variable_Of;
--------------------------
-- First_With_Clause_Of --
--------------------------
function First_With_Clause_Of
(Node : Project_Node_Id)
return Project_Node_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Project);
return Project_Nodes.Table (Node).Field1;
end First_With_Clause_Of;
----------------
-- Initialize --
----------------
procedure Initialize is
begin
Project_Nodes.Set_Last (Empty_Node);
Projects_Htable.Reset;
end Initialize;
-------------
-- Kind_Of --
-------------
function Kind_Of (Node : Project_Node_Id) return Project_Node_Kind is
begin
pragma Assert (Node /= Empty_Node);
return Project_Nodes.Table (Node).Kind;
end Kind_Of;
-----------------
-- Location_Of --
-----------------
function Location_Of (Node : Project_Node_Id) return Source_Ptr is
begin
pragma Assert (Node /= Empty_Node);
return Project_Nodes.Table (Node).Location;
end Location_Of;
-------------------------
-- Modified_Project_Of --
-------------------------
function Modified_Project_Of
(Node : Project_Node_Id)
return Project_Node_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Project_Declaration);
return Project_Nodes.Table (Node).Field2;
end Modified_Project_Of;
------------------------------
-- Modified_Project_Path_Of --
------------------------------
function Modified_Project_Path_Of
(Node : Project_Node_Id)
return String_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Project);
return Project_Nodes.Table (Node).Value;
end Modified_Project_Path_Of;
-------------
-- Name_Of --
-------------
function Name_Of (Node : Project_Node_Id) return Name_Id is
begin
pragma Assert (Node /= Empty_Node);
return Project_Nodes.Table (Node).Name;
end Name_Of;
--------------------
-- Next_Case_Item --
--------------------
function Next_Case_Item
(Node : Project_Node_Id)
return Project_Node_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Case_Item);
return Project_Nodes.Table (Node).Field3;
end Next_Case_Item;
---------------------------
-- Next_Declarative_Item --
---------------------------
function Next_Declarative_Item
(Node : Project_Node_Id)
return Project_Node_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Declarative_Item);
return Project_Nodes.Table (Node).Field2;
end Next_Declarative_Item;
-----------------------------
-- Next_Expression_In_List --
-----------------------------
function Next_Expression_In_List
(Node : Project_Node_Id)
return Project_Node_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Expression);
return Project_Nodes.Table (Node).Field2;
end Next_Expression_In_List;
-------------------------
-- Next_Literal_String --
-------------------------
function Next_Literal_String
(Node : Project_Node_Id)
return Project_Node_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Literal_String);
return Project_Nodes.Table (Node).Field1;
end Next_Literal_String;
-----------------------------
-- Next_Package_In_Project --
-----------------------------
function Next_Package_In_Project
(Node : Project_Node_Id)
return Project_Node_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Package_Declaration);
return Project_Nodes.Table (Node).Field3;
end Next_Package_In_Project;
----------------------
-- Next_String_Type --
----------------------
function Next_String_Type
(Node : Project_Node_Id)
return Project_Node_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_String_Type_Declaration);
return Project_Nodes.Table (Node).Field2;
end Next_String_Type;
---------------
-- Next_Term --
---------------
function Next_Term
(Node : Project_Node_Id)
return Project_Node_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Term);
return Project_Nodes.Table (Node).Field2;
end Next_Term;
-------------------
-- Next_Variable --
-------------------
function Next_Variable
(Node : Project_Node_Id)
return Project_Node_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
(Project_Nodes.Table (Node).Kind = N_Typed_Variable_Declaration
or else
Project_Nodes.Table (Node).Kind = N_Variable_Declaration));
return Project_Nodes.Table (Node).Field3;
end Next_Variable;
-------------------------
-- Next_With_Clause_Of --
-------------------------
function Next_With_Clause_Of
(Node : Project_Node_Id)
return Project_Node_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_With_Clause);
return Project_Nodes.Table (Node).Field2;
end Next_With_Clause_Of;
-------------------
-- Package_Id_Of --
-------------------
function Package_Id_Of (Node : Project_Node_Id) return Package_Node_Id is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Package_Declaration);
return Project_Nodes.Table (Node).Pkg_Id;
end Package_Id_Of;
---------------------
-- Package_Node_Of --
---------------------
function Package_Node_Of
(Node : Project_Node_Id)
return Project_Node_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
(Project_Nodes.Table (Node).Kind = N_Variable_Reference
or else
Project_Nodes.Table (Node).Kind = N_Attribute_Reference));
return Project_Nodes.Table (Node).Field2;
end Package_Node_Of;
------------------
-- Path_Name_Of --
------------------
function Path_Name_Of (Node : Project_Node_Id) return Name_Id is
begin
pragma Assert
(Node /= Empty_Node
and then
(Project_Nodes.Table (Node).Kind = N_Project
or else
Project_Nodes.Table (Node).Kind = N_With_Clause));
return Project_Nodes.Table (Node).Path_Name;
end Path_Name_Of;
----------------------------
-- Project_Declaration_Of --
----------------------------
function Project_Declaration_Of
(Node : Project_Node_Id)
return Project_Node_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Project);
return Project_Nodes.Table (Node).Field2;
end Project_Declaration_Of;
---------------------
-- Project_Node_Of --
---------------------
function Project_Node_Of
(Node : Project_Node_Id)
return Project_Node_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
(Project_Nodes.Table (Node).Kind = N_With_Clause
or else
Project_Nodes.Table (Node).Kind = N_Variable_Reference
or else
Project_Nodes.Table (Node).Kind = N_Attribute_Reference));
return Project_Nodes.Table (Node).Field1;
end Project_Node_Of;
-----------------------------------
-- Project_Of_Renamed_Package_Of --
-----------------------------------
function Project_Of_Renamed_Package_Of
(Node : Project_Node_Id)
return Project_Node_Id
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Package_Declaration);
return Project_Nodes.Table (Node).Field1;
end Project_Of_Renamed_Package_Of;
------------------------------------
-- Set_Associative_Array_Index_Of --
------------------------------------
procedure Set_Associative_Array_Index_Of
(Node : Project_Node_Id;
To : String_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Attribute_Declaration);
Project_Nodes.Table (Node).Value := To;
end Set_Associative_Array_Index_Of;
--------------------------
-- Set_Case_Insensitive --
--------------------------
procedure Set_Case_Insensitive
(Node : Project_Node_Id;
To : Boolean)
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Attribute_Declaration);
Project_Nodes.Table (Node).Case_Insensitive := To;
end Set_Case_Insensitive;
------------------------------------
-- Set_Case_Variable_Reference_Of --
------------------------------------
procedure Set_Case_Variable_Reference_Of
(Node : Project_Node_Id;
To : Project_Node_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Case_Construction);
Project_Nodes.Table (Node).Field1 := To;
end Set_Case_Variable_Reference_Of;
---------------------------
-- Set_Current_Item_Node --
---------------------------
procedure Set_Current_Item_Node
(Node : Project_Node_Id;
To : Project_Node_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Declarative_Item);
Project_Nodes.Table (Node).Field1 := To;
end Set_Current_Item_Node;
----------------------
-- Set_Current_Term --
----------------------
procedure Set_Current_Term
(Node : Project_Node_Id;
To : Project_Node_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Term);
Project_Nodes.Table (Node).Field1 := To;
end Set_Current_Term;
----------------------
-- Set_Directory_Of --
----------------------
procedure Set_Directory_Of
(Node : Project_Node_Id;
To : Name_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Project);
Project_Nodes.Table (Node).Directory := To;
end Set_Directory_Of;
----------------------------
-- Set_Expression_Kind_Of --
----------------------------
procedure Set_Expression_Kind_Of
(Node : Project_Node_Id;
To : Variable_Kind)
is
begin
pragma Assert
(Node /= Empty_Node
and then
(Project_Nodes.Table (Node).Kind = N_Literal_String
or else
Project_Nodes.Table (Node).Kind = N_Attribute_Declaration
or else
Project_Nodes.Table (Node).Kind = N_Variable_Declaration
or else
Project_Nodes.Table (Node).Kind = N_Typed_Variable_Declaration
or else
Project_Nodes.Table (Node).Kind = N_Expression
or else
Project_Nodes.Table (Node).Kind = N_Term
or else
Project_Nodes.Table (Node).Kind = N_Variable_Reference
or else
Project_Nodes.Table (Node).Kind = N_Attribute_Reference));
Project_Nodes.Table (Node).Expr_Kind := To;
end Set_Expression_Kind_Of;
-----------------------
-- Set_Expression_Of --
-----------------------
procedure Set_Expression_Of
(Node : Project_Node_Id;
To : Project_Node_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
(Project_Nodes.Table (Node).Kind = N_Attribute_Declaration
or else
Project_Nodes.Table (Node).Kind = N_Typed_Variable_Declaration
or else
Project_Nodes.Table (Node).Kind = N_Variable_Declaration));
Project_Nodes.Table (Node).Field1 := To;
end Set_Expression_Of;
-------------------------------
-- Set_External_Reference_Of --
-------------------------------
procedure Set_External_Reference_Of
(Node : Project_Node_Id;
To : Project_Node_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_External_Value);
Project_Nodes.Table (Node).Field1 := To;
end Set_External_Reference_Of;
-----------------------------
-- Set_External_Default_Of --
-----------------------------
procedure Set_External_Default_Of
(Node : Project_Node_Id;
To : Project_Node_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_External_Value);
Project_Nodes.Table (Node).Field2 := To;
end Set_External_Default_Of;
----------------------------
-- Set_First_Case_Item_Of --
----------------------------
procedure Set_First_Case_Item_Of
(Node : Project_Node_Id;
To : Project_Node_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Case_Construction);
Project_Nodes.Table (Node).Field2 := To;
end Set_First_Case_Item_Of;
-------------------------
-- Set_First_Choice_Of --
-------------------------
procedure Set_First_Choice_Of
(Node : Project_Node_Id;
To : Project_Node_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Case_Item);
Project_Nodes.Table (Node).Field1 := To;
end Set_First_Choice_Of;
------------------------
-- Set_Next_Case_Item --
------------------------
procedure Set_Next_Case_Item
(Node : Project_Node_Id;
To : Project_Node_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Case_Item);
Project_Nodes.Table (Node).Field3 := To;
end Set_Next_Case_Item;
-----------------------------------
-- Set_First_Declarative_Item_Of --
-----------------------------------
procedure Set_First_Declarative_Item_Of
(Node : Project_Node_Id;
To : Project_Node_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
(Project_Nodes.Table (Node).Kind = N_Project_Declaration
or else
Project_Nodes.Table (Node).Kind = N_Case_Item
or else
Project_Nodes.Table (Node).Kind = N_Package_Declaration));
if Project_Nodes.Table (Node).Kind = N_Project_Declaration then
Project_Nodes.Table (Node).Field1 := To;
else
Project_Nodes.Table (Node).Field2 := To;
end if;
end Set_First_Declarative_Item_Of;
----------------------------------
-- Set_First_Expression_In_List --
----------------------------------
procedure Set_First_Expression_In_List
(Node : Project_Node_Id;
To : Project_Node_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Literal_String_List);
Project_Nodes.Table (Node).Field1 := To;
end Set_First_Expression_In_List;
------------------------------
-- Set_First_Literal_String --
------------------------------
procedure Set_First_Literal_String
(Node : Project_Node_Id;
To : Project_Node_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_String_Type_Declaration);
Project_Nodes.Table (Node).Field1 := To;
end Set_First_Literal_String;
--------------------------
-- Set_First_Package_Of --
--------------------------
procedure Set_First_Package_Of
(Node : Project_Node_Id;
To : Package_Declaration_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Project);
Project_Nodes.Table (Node).Packages := To;
end Set_First_Package_Of;
------------------------------
-- Set_First_String_Type_Of --
------------------------------
procedure Set_First_String_Type_Of
(Node : Project_Node_Id;
To : Project_Node_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Project);
Project_Nodes.Table (Node).Field3 := To;
end Set_First_String_Type_Of;
--------------------
-- Set_First_Term --
--------------------
procedure Set_First_Term
(Node : Project_Node_Id;
To : Project_Node_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Expression);
Project_Nodes.Table (Node).Field1 := To;
end Set_First_Term;
---------------------------
-- Set_First_Variable_Of --
---------------------------
procedure Set_First_Variable_Of
(Node : Project_Node_Id;
To : Variable_Node_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
(Project_Nodes.Table (Node).Kind = N_Project
or else
Project_Nodes.Table (Node).Kind = N_Package_Declaration));
Project_Nodes.Table (Node).Variables := To;
end Set_First_Variable_Of;
------------------------------
-- Set_First_With_Clause_Of --
------------------------------
procedure Set_First_With_Clause_Of
(Node : Project_Node_Id;
To : Project_Node_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Project);
Project_Nodes.Table (Node).Field1 := To;
end Set_First_With_Clause_Of;
-----------------
-- Set_Kind_Of --
-----------------
procedure Set_Kind_Of
(Node : Project_Node_Id;
To : Project_Node_Kind)
is
begin
pragma Assert (Node /= Empty_Node);
Project_Nodes.Table (Node).Kind := To;
end Set_Kind_Of;
---------------------
-- Set_Location_Of --
---------------------
procedure Set_Location_Of
(Node : Project_Node_Id;
To : Source_Ptr)
is
begin
pragma Assert (Node /= Empty_Node);
Project_Nodes.Table (Node).Location := To;
end Set_Location_Of;
-----------------------------
-- Set_Modified_Project_Of --
-----------------------------
procedure Set_Modified_Project_Of
(Node : Project_Node_Id;
To : Project_Node_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Project_Declaration);
Project_Nodes.Table (Node).Field2 := To;
end Set_Modified_Project_Of;
----------------------------------
-- Set_Modified_Project_Path_Of --
----------------------------------
procedure Set_Modified_Project_Path_Of
(Node : Project_Node_Id;
To : String_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Project);
Project_Nodes.Table (Node).Value := To;
end Set_Modified_Project_Path_Of;
-----------------
-- Set_Name_Of --
-----------------
procedure Set_Name_Of
(Node : Project_Node_Id;
To : Name_Id)
is
begin
pragma Assert (Node /= Empty_Node);
Project_Nodes.Table (Node).Name := To;
end Set_Name_Of;
-------------------------------
-- Set_Next_Declarative_Item --
-------------------------------
procedure Set_Next_Declarative_Item
(Node : Project_Node_Id;
To : Project_Node_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Declarative_Item);
Project_Nodes.Table (Node).Field2 := To;
end Set_Next_Declarative_Item;
---------------------------------
-- Set_Next_Expression_In_List --
---------------------------------
procedure Set_Next_Expression_In_List
(Node : Project_Node_Id;
To : Project_Node_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Expression);
Project_Nodes.Table (Node).Field2 := To;
end Set_Next_Expression_In_List;
-----------------------------
-- Set_Next_Literal_String --
-----------------------------
procedure Set_Next_Literal_String
(Node : Project_Node_Id;
To : Project_Node_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Literal_String);
Project_Nodes.Table (Node).Field1 := To;
end Set_Next_Literal_String;
---------------------------------
-- Set_Next_Package_In_Project --
---------------------------------
procedure Set_Next_Package_In_Project
(Node : Project_Node_Id;
To : Project_Node_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Package_Declaration);
Project_Nodes.Table (Node).Field3 := To;
end Set_Next_Package_In_Project;
--------------------------
-- Set_Next_String_Type --
--------------------------
procedure Set_Next_String_Type
(Node : Project_Node_Id;
To : Project_Node_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_String_Type_Declaration);
Project_Nodes.Table (Node).Field2 := To;
end Set_Next_String_Type;
-------------------
-- Set_Next_Term --
-------------------
procedure Set_Next_Term
(Node : Project_Node_Id;
To : Project_Node_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Term);
Project_Nodes.Table (Node).Field2 := To;
end Set_Next_Term;
-----------------------
-- Set_Next_Variable --
-----------------------
procedure Set_Next_Variable
(Node : Project_Node_Id;
To : Project_Node_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
(Project_Nodes.Table (Node).Kind = N_Typed_Variable_Declaration
or else
Project_Nodes.Table (Node).Kind = N_Variable_Declaration));
Project_Nodes.Table (Node).Field3 := To;
end Set_Next_Variable;
-----------------------------
-- Set_Next_With_Clause_Of --
-----------------------------
procedure Set_Next_With_Clause_Of
(Node : Project_Node_Id;
To : Project_Node_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_With_Clause);
Project_Nodes.Table (Node).Field2 := To;
end Set_Next_With_Clause_Of;
-----------------------
-- Set_Package_Id_Of --
-----------------------
procedure Set_Package_Id_Of
(Node : Project_Node_Id;
To : Package_Node_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Package_Declaration);
Project_Nodes.Table (Node).Pkg_Id := To;
end Set_Package_Id_Of;
-------------------------
-- Set_Package_Node_Of --
-------------------------
procedure Set_Package_Node_Of
(Node : Project_Node_Id;
To : Project_Node_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
(Project_Nodes.Table (Node).Kind = N_Variable_Reference
or else
Project_Nodes.Table (Node).Kind = N_Attribute_Reference));
Project_Nodes.Table (Node).Field2 := To;
end Set_Package_Node_Of;
----------------------
-- Set_Path_Name_Of --
----------------------
procedure Set_Path_Name_Of
(Node : Project_Node_Id;
To : Name_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
(Project_Nodes.Table (Node).Kind = N_Project
or else
Project_Nodes.Table (Node).Kind = N_With_Clause));
Project_Nodes.Table (Node).Path_Name := To;
end Set_Path_Name_Of;
--------------------------------
-- Set_Project_Declaration_Of --
--------------------------------
procedure Set_Project_Declaration_Of
(Node : Project_Node_Id;
To : Project_Node_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Project);
Project_Nodes.Table (Node).Field2 := To;
end Set_Project_Declaration_Of;
-------------------------
-- Set_Project_Node_Of --
-------------------------
procedure Set_Project_Node_Of
(Node : Project_Node_Id;
To : Project_Node_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
(Project_Nodes.Table (Node).Kind = N_With_Clause
or else
Project_Nodes.Table (Node).Kind = N_Variable_Reference
or else
Project_Nodes.Table (Node).Kind = N_Attribute_Reference));
Project_Nodes.Table (Node).Field1 := To;
end Set_Project_Node_Of;
---------------------------------------
-- Set_Project_Of_Renamed_Package_Of --
---------------------------------------
procedure Set_Project_Of_Renamed_Package_Of
(Node : Project_Node_Id;
To : Project_Node_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
Project_Nodes.Table (Node).Kind = N_Package_Declaration);
Project_Nodes.Table (Node).Field1 := To;
end Set_Project_Of_Renamed_Package_Of;
------------------------
-- Set_String_Type_Of --
------------------------
procedure Set_String_Type_Of
(Node : Project_Node_Id;
To : Project_Node_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
(Project_Nodes.Table (Node).Kind = N_Variable_Reference
or else
Project_Nodes.Table (Node).Kind = N_Typed_Variable_Declaration)
and then
Project_Nodes.Table (To).Kind = N_String_Type_Declaration);
if Project_Nodes.Table (Node).Kind = N_Variable_Reference then
Project_Nodes.Table (Node).Field3 := To;
else
Project_Nodes.Table (Node).Field2 := To;
end if;
end Set_String_Type_Of;
-------------------------
-- Set_String_Value_Of --
-------------------------
procedure Set_String_Value_Of
(Node : Project_Node_Id;
To : String_Id)
is
begin
pragma Assert
(Node /= Empty_Node
and then
(Project_Nodes.Table (Node).Kind = N_With_Clause
or else
Project_Nodes.Table (Node).Kind = N_Literal_String));
Project_Nodes.Table (Node).Value := To;
end Set_String_Value_Of;
--------------------
-- String_Type_Of --
--------------------
function String_Type_Of (Node : Project_Node_Id)
return Project_Node_Id is
begin
pragma Assert
(Node /= Empty_Node
and then
(Project_Nodes.Table (Node).Kind = N_Variable_Reference
or else
Project_Nodes.Table (Node).Kind = N_Typed_Variable_Declaration));
if Project_Nodes.Table (Node).Kind = N_Variable_Reference then
return Project_Nodes.Table (Node).Field3;
else
return Project_Nodes.Table (Node).Field2;
end if;
end String_Type_Of;
---------------------
-- String_Value_Of --
---------------------
function String_Value_Of (Node : Project_Node_Id) return String_Id is
begin
pragma Assert
(Node /= Empty_Node
and then
(Project_Nodes.Table (Node).Kind = N_With_Clause
or else
Project_Nodes.Table (Node).Kind = N_Literal_String));
return Project_Nodes.Table (Node).Value;
end String_Value_Of;
--------------------
-- Value_Is_Valid --
--------------------
function Value_Is_Valid
(For_Typed_Variable : Project_Node_Id;
Value : String_Id)
return Boolean
is
begin
pragma Assert
(For_Typed_Variable /= Empty_Node
and then
(Project_Nodes.Table (For_Typed_Variable).Kind =
N_Typed_Variable_Declaration));
declare
Current_String : Project_Node_Id :=
First_Literal_String
(String_Type_Of (For_Typed_Variable));
begin
while Current_String /= Empty_Node
and then
not String_Equal (String_Value_Of (Current_String), Value)
loop
Current_String :=
Next_Literal_String (Current_String);
end loop;
return Current_String /= Empty_Node;
end;
end Value_Is_Valid;
end Prj.Tree;
|
alloy4fun_models/trashltl/models/3/kMfjxpGc65nNY4krH.als | Kaixi26/org.alloytools.alloy | 0 | 592 | <reponame>Kaixi26/org.alloytools.alloy
open main
pred idkMfjxpGc65nNY4krH_prop4 {
some File
}
pred __repair { idkMfjxpGc65nNY4krH_prop4 }
check __repair { idkMfjxpGc65nNY4krH_prop4 <=> prop4o } |
src/main/antlr4/ru/mail/jira/plugins/groovy/impl/jql/antlr/AggregateExpressionQuery.g4 | Raschudesny/jira-plugins-groovy | 45 | 1532 | grammar AggregateExpressionQuery;
DOT: '.';
COMMA: ',';
LEFT_BRACKET: '(';
RIGHT_BRACKET: ')';
PLUS: '+';
MINUS: '-';
DIV: '/';
MULT: '*';
STRING: DQSTRING | SQSTRING;
DQSTRING: '"' ( '\\"' | . )*? '"';
SQSTRING: '\'' ( '\\\'' | . )*? '\'';
WS : [ \r\t\n]+ -> skip ;
NUMBER: '0'..'9'+;
UQSTRING: ('a'..'z' | 'A'..'Z' | '0'..'9' | '_')+;
variable: UQSTRING;
method_parameter_value: STRING | NUMBER;
method_parameters: method_parameter_value (COMMA method_parameter_value)*;
method_name: UQSTRING;
method_call: method_name LEFT_BRACKET method_parameters? RIGHT_BRACKET;
statement: variable DOT method_call;
arithmetic_operation: PLUS | MINUS | DIV | MULT;
aggregate_expression:
LEFT_BRACKET aggregate_expression arithmetic_operation aggregate_expression RIGHT_BRACKET |
aggregate_expression arithmetic_operation aggregate_expression |
LEFT_BRACKET statement RIGHT_BRACKET |
statement;
|
Transynther/x86/_processed/NONE/_xt_/i7-8650U_0xd2.log_498_1211.asm | ljhsiun2/medusa | 9 | 178407 | .global s_prepare_buffers
s_prepare_buffers:
push %r12
push %r14
push %rax
push %rbx
push %rcx
push %rdi
push %rdx
push %rsi
lea addresses_D_ht+0x19bc6, %rcx
nop
sub %rbx, %rbx
mov $0x6162636465666768, %rdx
movq %rdx, (%rcx)
nop
cmp %rsi, %rsi
lea addresses_A_ht+0x249e, %rsi
lea addresses_normal_ht+0x5ee, %rdi
nop
nop
nop
nop
cmp $55560, %rax
mov $34, %rcx
rep movsq
nop
nop
nop
add %rdi, %rdi
lea addresses_A_ht+0xf49e, %rsi
clflush (%rsi)
nop
nop
nop
nop
nop
and $27990, %rbx
movw $0x6162, (%rsi)
nop
nop
inc %rdx
lea addresses_UC_ht+0x6b4e, %rsi
lea addresses_normal_ht+0x50b1, %rdi
nop
nop
sub %rax, %rax
mov $36, %rcx
rep movsl
nop
nop
nop
cmp $57316, %rdx
lea addresses_A_ht+0x219e, %rdx
nop
nop
nop
and $6668, %rdi
mov $0x6162636465666768, %rax
movq %rax, %xmm3
and $0xffffffffffffffc0, %rdx
vmovntdq %ymm3, (%rdx)
nop
nop
nop
add %rdi, %rdi
lea addresses_WT_ht+0xc9e, %rsi
nop
lfence
mov $0x6162636465666768, %rbx
movq %rbx, %xmm7
movups %xmm7, (%rsi)
nop
nop
nop
xor %rbx, %rbx
lea addresses_WT_ht+0x1715e, %rsi
nop
sub $45079, %rcx
mov (%rsi), %di
nop
nop
nop
nop
add $14528, %rcx
lea addresses_UC_ht+0x5e9e, %rsi
lea addresses_WC_ht+0x1121e, %rdi
nop
nop
nop
xor $15951, %r14
mov $39, %rcx
rep movsb
nop
nop
cmp $13350, %rdx
lea addresses_D_ht+0xe6ba, %rsi
lea addresses_A_ht+0x18656, %rdi
nop
nop
nop
nop
dec %r12
mov $91, %rcx
rep movsw
nop
nop
nop
nop
lfence
lea addresses_normal_ht+0x1887e, %rcx
nop
nop
add $49663, %rax
movb (%rcx), %dl
add $23537, %rax
lea addresses_normal_ht+0xf85e, %rsi
lea addresses_UC_ht+0x13896, %rdi
clflush (%rsi)
clflush (%rdi)
nop
nop
and $9322, %rbx
mov $95, %rcx
rep movsq
nop
nop
nop
nop
dec %rdi
pop %rsi
pop %rdx
pop %rdi
pop %rcx
pop %rbx
pop %rax
pop %r14
pop %r12
ret
.global s_faulty_load
s_faulty_load:
push %r15
push %rax
push %rbx
push %rcx
push %rdi
push %rdx
// Store
lea addresses_normal+0x1196e, %rax
nop
nop
nop
nop
cmp %r15, %r15
mov $0x5152535455565758, %rdx
movq %rdx, (%rax)
nop
nop
nop
sub %rcx, %rcx
// Faulty Load
lea addresses_RW+0x749e, %rcx
clflush (%rcx)
and %rdx, %rdx
mov (%rcx), %ebx
lea oracles, %rax
and $0xff, %rbx
shlq $12, %rbx
mov (%rax,%rbx,1), %rbx
pop %rdx
pop %rdi
pop %rcx
pop %rbx
pop %rax
pop %r15
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'type': 'addresses_RW', 'size': 16, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_normal', 'size': 8, 'AVXalign': False, 'NT': False, 'congruent': 3, 'same': False}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'type': 'addresses_RW', 'size': 4, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': True}}
<gen_prepare_buffer>
{'OP': 'STOR', 'dst': {'type': 'addresses_D_ht', 'size': 8, 'AVXalign': False, 'NT': False, 'congruent': 2, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_A_ht', 'congruent': 11, 'same': True}, 'dst': {'type': 'addresses_normal_ht', 'congruent': 3, 'same': True}}
{'OP': 'STOR', 'dst': {'type': 'addresses_A_ht', 'size': 2, 'AVXalign': False, 'NT': True, 'congruent': 10, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_UC_ht', 'congruent': 2, 'same': False}, 'dst': {'type': 'addresses_normal_ht', 'congruent': 0, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_A_ht', 'size': 32, 'AVXalign': False, 'NT': True, 'congruent': 8, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_WT_ht', 'size': 16, 'AVXalign': False, 'NT': False, 'congruent': 11, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_WT_ht', 'size': 2, 'AVXalign': False, 'NT': True, 'congruent': 6, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_UC_ht', 'congruent': 8, 'same': False}, 'dst': {'type': 'addresses_WC_ht', 'congruent': 7, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_D_ht', 'congruent': 2, 'same': False}, 'dst': {'type': 'addresses_A_ht', 'congruent': 3, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_normal_ht', 'size': 1, 'AVXalign': False, 'NT': False, 'congruent': 4, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_normal_ht', 'congruent': 5, 'same': False}, 'dst': {'type': 'addresses_UC_ht', 'congruent': 2, 'same': False}}
{'32': 498}
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
*/
|
src/plfa/part1/InequalityReasoningExercise.agda | abolotina/plfa.github.io | 0 | 12032 | <gh_stars>0
module InequalityReasoningExercise where
open import EqualityAux
infix 4 _≤_
data _≤_ : ℕ → ℕ → Set where
z≤n : ∀ {n : ℕ}
--------
→ zero ≤ n
s≤s : ∀ {m n : ℕ}
→ m ≤ n
-------------
→ suc m ≤ suc n
≤-refl : ∀ {n : ℕ}
-----
→ n ≤ n
≤-refl {zero} = z≤n
≤-refl {suc n} = s≤s ≤-refl
≤-trans : ∀ {m n p : ℕ}
→ m ≤ n
→ n ≤ p
-----
→ m ≤ p
≤-trans z≤n _ = z≤n
≤-trans (s≤s m≤n) (s≤s n≤p) = s≤s (≤-trans m≤n n≤p)
module ≤-Reasoning where
infix 1 ≤-begin_
infixr 2 _≤⟨⟩_ _≤⟨_⟩_ _≤-≡⟨_⟩_
infix 3 _≤-∎
≤-begin_ : ∀ {x y : ℕ}
→ x ≤ y
-----
→ x ≤ y
≤-begin x≤y = x≤y
_≤⟨⟩_ : ∀ (x : ℕ) {y : ℕ}
→ x ≤ y
-----
→ x ≤ y
x ≤⟨⟩ x≤y = x≤y
_≤⟨_⟩_ : ∀ (x : ℕ) {y z : ℕ}
→ x ≤ y
→ y ≤ z
-----
→ x ≤ z
x ≤⟨ x≤y ⟩ y≤z = ≤-trans x≤y y≤z
_≤-≡⟨_⟩_ : ∀ (x : ℕ) {y z : ℕ}
→ x ≡ y
→ y ≤ z
-----
→ x ≤ z
x ≤-≡⟨ refl ⟩ y≤z = ≤-trans ≤-refl y≤z
_≤-∎ : ∀ (x : ℕ)
-----
→ x ≤ x
x ≤-∎ = ≤-refl
open ≤-Reasoning
+-monoʳ-≤ : ∀ (n p q : ℕ)
→ p ≤ q
-------------
→ n + p ≤ n + q
+-monoʳ-≤ zero p q p≤q =
≤-begin
zero + p
≤⟨⟩
p
≤⟨ p≤q ⟩
q
≤⟨⟩
zero + q
≤-∎
+-monoʳ-≤ (suc n) p q p≤q =
≤-begin
(suc n) + p
≤⟨⟩
suc (n + p)
≤⟨ s≤s (+-monoʳ-≤ n p q p≤q) ⟩
suc (n + q)
≤⟨⟩
(suc n) + q
≤-∎
+-monoˡ-≤ : ∀ (m n p : ℕ)
→ m ≤ n
-------------
→ m + p ≤ n + p
+-monoˡ-≤ m n p m≤n =
≤-begin
m + p
≤-≡⟨ +-comm m p ⟩
p + m
≤⟨ +-monoʳ-≤ p m n m≤n ⟩
p + n
≤-≡⟨ +-comm p n ⟩
n + p
≤-∎
+-mono-≤ : ∀ (m n p q : ℕ)
→ m ≤ n
→ p ≤ q
-------------
→ m + p ≤ n + q
+-mono-≤ m n p q m≤n p≤q =
≤-begin
m + p
≤⟨ +-monoˡ-≤ m n p m≤n ⟩
n + p
≤⟨ +-monoʳ-≤ n p q p≤q ⟩
n + q
≤-∎
|
src/Fragment/Setoid/Morphism/Properties.agda | yallop/agda-fragment | 18 | 13224 | {-# OPTIONS --without-K --exact-split --safe #-}
module Fragment.Setoid.Morphism.Properties where
open import Fragment.Setoid.Morphism.Base
open import Fragment.Setoid.Morphism.Setoid
open import Level using (Level)
open import Relation.Binary using (Setoid)
private
variable
a b c d ℓ₁ ℓ₂ ℓ₃ ℓ₄ : Level
A : Setoid a ℓ₁
B : Setoid b ℓ₂
C : Setoid c ℓ₃
D : Setoid d ℓ₄
id-unitˡ : ∀ {f : A ↝ B} → id · f ≗ f
id-unitˡ {B = B} = Setoid.refl B
id-unitʳ : ∀ {f : A ↝ B} → f · id ≗ f
id-unitʳ {B = B} = Setoid.refl B
·-assoc : ∀ (h : C ↝ D) (g : B ↝ C) (f : A ↝ B)
→ (h · g) · f ≗ h · (g · f)
·-assoc {D = D} _ _ _ = Setoid.refl D
·-congˡ : ∀ (h : B ↝ C) (f g : A ↝ B)
→ f ≗ g
→ h · f ≗ h · g
·-congˡ h _ _ f≗g = ∣ h ∣-cong f≗g
·-congʳ : ∀ (h : A ↝ B) (f g : B ↝ C)
→ f ≗ g
→ f · h ≗ g · h
·-congʳ _ _ _ f≗g = f≗g
|
oeis/159/A159656.asm | neoneye/loda-programs | 11 | 247500 | ; A159656: Numerator of Hermite(n, 18/19).
; Submitted by <NAME>
; 1,36,574,-31320,-2370804,5103216,8742318216,292616324064,-33649488597360,-2901533477298624,114199171722894816,25060241888120278656,-4801113850900597056,-217294775817306515769600,-7777548674818481563737984,1916423841667868925104549376,153222110448327436639046144256,-16622532242807434103802093198336,-2479059344383838585044527729738240,126780292629707224551409004934998016,38571826620926957793491555574209104896,-442121667219601841956650030589843574784,-600742415246400200375358366717392817125376
add $0,1
mov $3,11
lpb $0
sub $0,1
add $2,$3
mov $3,$1
mov $1,$2
mul $1,361
mul $2,36
mul $3,-1
mul $3,$0
mul $3,2
lpe
mov $0,$1
div $0,3971
|
source/nodes/program-nodes-requeue_statements.adb | optikos/oasis | 0 | 10495 | <gh_stars>0
-- Copyright (c) 2019 <NAME> <<EMAIL>>
--
-- SPDX-License-Identifier: MIT
-- License-Filename: LICENSE
-------------------------------------------------------------
package body Program.Nodes.Requeue_Statements is
function Create
(Requeue_Token : not null Program.Lexical_Elements
.Lexical_Element_Access;
Entry_Name : not null Program.Elements.Expressions.Expression_Access;
With_Token : Program.Lexical_Elements.Lexical_Element_Access;
Abort_Token : Program.Lexical_Elements.Lexical_Element_Access;
Semicolon_Token : not null Program.Lexical_Elements
.Lexical_Element_Access)
return Requeue_Statement is
begin
return Result : Requeue_Statement :=
(Requeue_Token => Requeue_Token, Entry_Name => Entry_Name,
With_Token => With_Token, Abort_Token => Abort_Token,
Semicolon_Token => Semicolon_Token, Enclosing_Element => null)
do
Initialize (Result);
end return;
end Create;
function Create
(Entry_Name : not null Program.Elements.Expressions
.Expression_Access;
Is_Part_Of_Implicit : Boolean := False;
Is_Part_Of_Inherited : Boolean := False;
Is_Part_Of_Instance : Boolean := False;
Has_With_Abort : Boolean := False)
return Implicit_Requeue_Statement is
begin
return Result : Implicit_Requeue_Statement :=
(Entry_Name => Entry_Name, Is_Part_Of_Implicit => Is_Part_Of_Implicit,
Is_Part_Of_Inherited => Is_Part_Of_Inherited,
Is_Part_Of_Instance => Is_Part_Of_Instance,
Has_With_Abort => Has_With_Abort, Enclosing_Element => null)
do
Initialize (Result);
end return;
end Create;
overriding function Entry_Name
(Self : Base_Requeue_Statement)
return not null Program.Elements.Expressions.Expression_Access is
begin
return Self.Entry_Name;
end Entry_Name;
overriding function Requeue_Token
(Self : Requeue_Statement)
return not null Program.Lexical_Elements.Lexical_Element_Access is
begin
return Self.Requeue_Token;
end Requeue_Token;
overriding function With_Token
(Self : Requeue_Statement)
return Program.Lexical_Elements.Lexical_Element_Access is
begin
return Self.With_Token;
end With_Token;
overriding function Abort_Token
(Self : Requeue_Statement)
return Program.Lexical_Elements.Lexical_Element_Access is
begin
return Self.Abort_Token;
end Abort_Token;
overriding function Semicolon_Token
(Self : Requeue_Statement)
return not null Program.Lexical_Elements.Lexical_Element_Access is
begin
return Self.Semicolon_Token;
end Semicolon_Token;
overriding function Has_With_Abort
(Self : Requeue_Statement)
return Boolean is
begin
return Self.With_Token.Assigned;
end Has_With_Abort;
overriding function Is_Part_Of_Implicit
(Self : Implicit_Requeue_Statement)
return Boolean is
begin
return Self.Is_Part_Of_Implicit;
end Is_Part_Of_Implicit;
overriding function Is_Part_Of_Inherited
(Self : Implicit_Requeue_Statement)
return Boolean is
begin
return Self.Is_Part_Of_Inherited;
end Is_Part_Of_Inherited;
overriding function Is_Part_Of_Instance
(Self : Implicit_Requeue_Statement)
return Boolean is
begin
return Self.Is_Part_Of_Instance;
end Is_Part_Of_Instance;
overriding function Has_With_Abort
(Self : Implicit_Requeue_Statement)
return Boolean is
begin
return Self.Has_With_Abort;
end Has_With_Abort;
procedure Initialize (Self : aliased in out Base_Requeue_Statement'Class) is
begin
Set_Enclosing_Element (Self.Entry_Name, Self'Unchecked_Access);
null;
end Initialize;
overriding function Is_Requeue_Statement_Element
(Self : Base_Requeue_Statement)
return Boolean is
pragma Unreferenced (Self);
begin
return True;
end Is_Requeue_Statement_Element;
overriding function Is_Statement_Element
(Self : Base_Requeue_Statement)
return Boolean is
pragma Unreferenced (Self);
begin
return True;
end Is_Statement_Element;
overriding procedure Visit
(Self : not null access Base_Requeue_Statement;
Visitor : in out Program.Element_Visitors.Element_Visitor'Class) is
begin
Visitor.Requeue_Statement (Self);
end Visit;
overriding function To_Requeue_Statement_Text
(Self : aliased in out Requeue_Statement)
return Program.Elements.Requeue_Statements
.Requeue_Statement_Text_Access is
begin
return Self'Unchecked_Access;
end To_Requeue_Statement_Text;
overriding function To_Requeue_Statement_Text
(Self : aliased in out Implicit_Requeue_Statement)
return Program.Elements.Requeue_Statements
.Requeue_Statement_Text_Access is
pragma Unreferenced (Self);
begin
return null;
end To_Requeue_Statement_Text;
end Program.Nodes.Requeue_Statements;
|
bitmap.adb | FROL256/ada-ray-tracer | 3 | 3253 | <reponame>FROL256/ada-ray-tracer<gh_stars>1-10
with Interfaces;
with Ada.Streams.Stream_IO;
use Interfaces;
use Ada.Streams.Stream_IO;
package body Bitmap is
procedure Init(im : out Image; w : Integer; h : Integer) is
begin
im.width := w;
im.height := h;
im.data := new PixelData(0 .. w*h-1);
end Init;
procedure Delete(im : in out Image) is
begin
im.width := 0;
im.height := 0;
delete(im.data);
im.data := null;
end Delete;
procedure LoadBMP(im : in out Image; a_fileName : String) is
begin
null;
end LoadBMP;
procedure SaveBMP(im : Image; a_fileName : String) is
BMP_File : File_Type;
S : Stream_Access;
header : BITBAPFILEHEADER;
info : BITMAPINFOHEADER;
px : Pixel;
pxU : Unsigned_32;
begin
header.bfType := 16#4d42#;
header.bfSize := 14 + 40 + DWORD(im.width*im.height*3);
header.bfReserved1 := 0;
header.bfReserved2 := 0;
header.bfOffBits := 14 + 40;
info.biSize := 40;
info.biWidth := DWORD(im.width);
info.biHeight := DWORD(im.height);
info.biPlanes := 1;
info.biBitCount := 24;
info.biCompression := 0;
info.biSizeImage := 0;
info.biXPelsPerMeter := 0;
info.biYPelsPerMeter := 0;
info.biClrUsed := 0;
info.biClrImportant := 0;
Create(File => BMP_File,
Mode => Out_File,
Name => a_fileName,
Form => "");
S := Stream(BMP_File);
BITBAPFILEHEADER'Write(S, header);
BITMAPINFOHEADER'Write(S, info);
for i in im.data'First .. im.data'Last loop
pxU := im.data(i);
px.b := Unsigned_8(Shift_Right(pxU,0) and 255);
px.g := Unsigned_8(Shift_Right(pxU,8) and 255);
px.r := Unsigned_8(Shift_Right(pxU,16) and 255);
Pixel'Write(S, px);
end loop;
Close(BMP_File);
end SaveBMP;
end Bitmap;
|
sub_401280.asm | nanabingies/KiLogr | 0 | 164115 | <filename>sub_401280.asm
.text:00401280 ; =============== S U B R O U T I N E =======================================
.text:00401280
.text:00401280 ; Attributes: bp-based frame
.text:00401280
.text:00401280 sub_401280 proc near ; CODE XREF: sub_401250+23↑p
.text:00401280
.text:00401280 var_98 = byte ptr -98h
.text:00401280 var_90 = byte ptr -90h
.text:00401280 var_88 = dword ptr -88h
.text:00401280 var_84 = byte ptr -84h
.text:00401280 var_6D = byte ptr -6Dh
.text:00401280 var_4 = dword ptr -4
.text:00401280 arg_0 = dword ptr 8
.text:00401280
.text:00401280 push ebp
.text:00401281 mov ebp, esp
.text:00401283 sub esp, 98h
.text:00401289 mov eax, ___security_cookie
.text:0040128E xor eax, ebp
.text:00401290 mov [ebp+var_4], eax
.text:00401293 push ebx
.text:00401294 push esi
.text:00401295 push edi
.text:00401296 push 5
.text:00401298 pop ecx
.text:00401299 mov esi, offset aDeviceKeyboard ; "\\Device\\KeyboardClass0"
.text:0040129E mov ebx, [ebp+arg_0]
.text:004012A1 lea edi, [ebp+var_84]
.text:004012A7 rep movsd
.text:004012A9 push 69h ; 'i'
.text:004012AB lea eax, [ebp+var_6D]
.text:004012AE movsw
.text:004012B0 movsb
.text:004012B1 xor esi, esi
.text:004012B3 push esi
.text:004012B4 push eax
.text:004012B5 call memset
.text:004012BA add esp, 0Ch
.text:004012BD lea eax, [ebp+var_88]
.text:004012C3 push eax
.text:004012C4 push 1
.text:004012C6 push esi
.text:004012C7 push 0Bh
.text:004012C9 push esi
.text:004012CA push esi
.text:004012CB push ebx
.text:004012CC call ds:IoCreateDevice
.text:004012D2 pop edi
.text:004012D3 pop esi
.text:004012D4 pop ebx
.text:004012D5 test eax, eax
.text:004012D7 jns short loc_4012DE
.text:004012D9
.text:004012D9 loc_4012D9: ; CODE XREF: sub_401280+BC↓j
.text:004012D9 lfence
.text:004012DC jmp short loc_40134D
.text:004012DE ; ---------------------------------------------------------------------------
.text:004012DE
.text:004012DE loc_4012DE: ; CODE XREF: sub_401280+57↑j
.text:004012DE mov eax, [ebp+var_88]
.text:004012E4 or dword ptr [eax+1Ch], 2004h
.text:004012EB mov eax, [ebp+var_88]
.text:004012F1 and dword ptr [eax+1Ch], 0FFFFFF7Fh
.text:004012F8 lea eax, [ebp+var_84]
.text:004012FE push eax
.text:004012FF lea eax, [ebp+var_98]
.text:00401305 push eax
.text:00401306 call ds:RtlInitAnsiString
.text:0040130C push 1
.text:0040130E lea eax, [ebp+var_98]
.text:00401314 push eax
.text:00401315 lea eax, [ebp+var_90]
.text:0040131B push eax
.text:0040131C call ds:RtlAnsiStringToUnicodeString
.text:00401322 push offset DeviceObject
.text:00401327 lea eax, [ebp+var_90]
.text:0040132D push eax
.text:0040132E push [ebp+var_88]
.text:00401334 call ds:IoAttachDevice
.text:0040133A test eax, eax
.text:0040133C js short loc_4012D9
.text:0040133E lea eax, [ebp+var_90]
.text:00401344 push eax
.text:00401345 call ds:RtlFreeUnicodeString
.text:0040134B xor eax, eax
.text:0040134D
.text:0040134D loc_40134D: ; CODE XREF: sub_401280+5C↑j
.text:0040134D mov ecx, [ebp+var_4]
.text:00401350 xor ecx, ebp
.text:00401352 call @__security_check_cookie@4 ; __security_check_cookie(x)
.text:00401357 leave
.text:00401358 retn 4
.text:00401358 sub_401280 endp
.text:00401358
.text:00401358 ; ---------------------------------------------------------------------------
|
lab8/source/kernel.asm | wkcn/OSLabs | 73 | 90964 | <filename>lab8/source/kernel.asm
BITS 16
[global _start]
[extern main]
[global RunNum]
[global UserID]
[global INT09H_FLAG]
;16k = 0x4000
;4M = 0x4 0 0000
MaxRunNum equ 128
MSG_SEGMENT equ 4000h
SCREEN_SEGMENT equ MSG_SEGMENT + 100h
PCB_SEGMENT equ SCREEN_SEGMENT + (80 * 25 * 2 / 16) * 4
PROG_SEGMENT equ PCB_SEGMENT + (MaxRunNum * PCBSize / 16)
UserProgramOffset equ 100h
UpdateTimes equ 20
;写入中断向量表
%macro WriteIVT 2
mov ax,%1
mov bx,4
mul bx
mov si,ax
mov ax,%2
mov [cs:si],ax ; offset
mov ax,cs
mov [cs:si + 2],ax
%endmacro
;Init
mov ax,cs
mov ds,ax
mov ax, 0
mov ss, ax
mov sp, 7c00h
mov ax, [cs:09h * 4]
mov word [INT09HORG], ax
mov ax, [cs:09h * 4 + 2]
mov word [INT09HORG + 2], ax
WriteIVT 08h,WKCNINTTimer ; Timer Interupt
WriteIVT 09h,WKCNINTKeyBoard
WriteIVT 20h,WKCNINT20H ; 进程退出(为了简单, 这个中断只有一个功能)
WriteIVT 21h,WKCNINT21H ; 进程功能
WriteIVT 22h,WKCNINT22H ; 进程通信
_start:
mov ax, PCB_SEGMENT
mov es, ax
mov al, 1
mov byte [es:_STATE_OFFSET], al; 设置Shell为运行态
;SetTimer
mov al,34h
out 43h,al ; write control word
mov ax,1193182/UpdateTimes ;X times / seconds
out 40h,al
mov al,ah
out 40h,al
mov ax,cs
mov ds,ax
mov ss,ax
mov es,ax
sti
jmp main
%macro SaveReg 1
mov ax, %1
mov [es:(bx + _%1_OFFSET)], ax
%endmacro
%macro LoadReg 1
mov ax, [es:(bx + _%1_OFFSET)]
mov %1, ax
%endmacro
;键盘中断
WKCNINTKeyBoard:
push ax
mov al,1
xor byte [cs:INT09H_FLAG], al
;sti
pushf
call far [cs:INT09HORG]
pop ax
iret
WKCNINT20H:
push es
push dx
push bx
push ax
;切换到ShellMode
mov ax, [cs:RunID]
mov bx, PCBSize
mul bx
mov bx, ax
mov ax, PCB_SEGMENT
mov es, ax
mov byte[es:(bx + _STATE_OFFSET)], 4 ; Dead
pop ax
pop bx
pop dx
pop es
iret
;注意, 如果这个放在代码段, 会导致被当成代码运行:-(
INT21HJMPLIST:
dw TabShellMode, TabProgState, GetRunID, RETN_PCB_S, RETN_PROG_S, RETN_MSG_S, RETN_MAXRUNNUM
dw STOP_CLOCK, START_CLOCK, INC_RUNNUM, RETN_RUNNUM, RETN_SCREEN_S
WKCNINT21H:
;21H中断
;AH = 00h, 切换ShellMode到al状态
;AH = 01h, 切换进程状态到al
;AH = 02h, 得到当前进程ID
;AH = 03h, 返回PCB_SEGMENT
;AH = 04h, 返回PROG_SEGMENT
;AH = 05h, 返回MSG_SEGMENT
;AH = 06h, 返回MaxRunNum
;AH = 07h, 停止时钟
;AH = 08h, 开启时钟
;AH = 09h, ++RunNum
;AH = 0Ah, 返回RunNum
;AH = 0Bh, 返回SCREEN_SEGMENT
push dx
push cx
push bx
;判断是否有效
;cmp ah, 0x09
;ja INT21HEND
xor bx, bx
mov bl, ah
shl bx, 1
jmp word[cs:(INT21HJMPLIST + bx)]
;AH = 00h
TabShellMode:
nop
jmp INT21HEND
;AH = 01h
TabProgState:
mov dl, al
mov ax, [cs:RunID]
mov bx, PCBSize
mul bx
mov bx, ax
mov ax, PCB_SEGMENT
push es
mov es, ax
mov byte[es:(bx + _STATE_OFFSET)], dl
pop es
jmp INT21HEND
;AH = 02h
GetRunID:
mov ax, [cs:RunID]
jmp INT21HEND
RETN_PCB_S:
mov ax, PCB_SEGMENT
jmp INT21HEND
RETN_PROG_S:
mov ax, PROG_SEGMENT
jmp INT21HEND
RETN_MSG_S:
mov ax, MSG_SEGMENT
jmp INT21HEND
RETN_SCREEN_S:
mov ax, SCREEN_SEGMENT
jmp INT21HEND
RETN_MAXRUNNUM:
mov ax, MaxRunNum
jmp INT21HEND
STOP_CLOCK:
mov byte[cs:CLOCKON],0
jmp INT21HEND
START_CLOCK:
mov byte[cs:CLOCKON],1
jmp INT21HEND
INC_RUNNUM:
inc word[cs:RunNum]
jmp INT21HEND
RETN_RUNNUM:
mov ax, word[cs:RunNum]
jmp INT21HEND
INT21HEND:
pop bx
pop cx
pop dx
iret
INT22HJMPLIST:
dw MSG_READ, MSG_WRITE, SET_MSG_V,RESET_MSG,CLOSE_MSG,INT22HEND
WKCNINT22H:
;22H进程, 进程通信
;ah = 00h 读
;ah = 01h 写
;ah = 02h 信号量设置(bh=0, 清零; bh=1, 加1; bh=2, 减1; bh=3, 设置为bl值)
;ah = 03h 设置端口
;ah = 04h 关闭端口
;ah = 05h 只返回信号量
;al = 端口值
;基地址bx, 缓存大小cx, 段地址dx
;返回信号量(ax)
;信号描述 大小
;是否开启 byte
;信号量 byte
;大小 word
;偏移量 word
;段地址 word
;
;总大小 8
MSG_OPENED_OFF equ 0
MSG_SIG_OFF equ 1
MSG_SIZE_OFF equ 2
MSG_OFFSET_OFF equ 4
MSG_SEG_OFF equ 6
push dx
push cx
push bx
push es
push ds
push si
push di
mov es, dx; es = 目标段地址
mov di, bx
;[es:di] = 目标量
mov bl, ah; bl 记录功能号
mov ah, 8
mul ah
;ax = 信号偏移量
mov si, ax
mov ax, MSG_SEGMENT
mov ds, ax
;[ds:si] = 信号量
cmp bl, 0x05
ja INT22HEND
mov bh, 0
shl bx, 1
jmp word[cs:(INT22HJMPLIST + bx)]
%macro INIT_MSG_RW 1
cmp byte[ds:si + MSG_OPENED_OFF], 0
je INT22HEND
cmp cx, word[ds:si + MSG_SIZE_OFF]
jbe NOT_OVERFLOW_%1
mov cx, word[ds:si + MSG_SIZE_OFF]
NOT_OVERFLOW_%1:
mov ax, [ds:si + MSG_SEG_OFF]
mov bx, [ds:si + MSG_OFFSET_OFF]
cld
%endmacro
MSG_READ:
INIT_MSG_RW 0
mov ds, ax
mov si, bx
MSG_READ_LOOP:
movsb
loop MSG_READ_LOOP
jmp INT22HEND
MSG_WRITE:
INIT_MSG_RW 1
mov dx, es
mov es, ax
mov ds, dx
mov si, di
mov di, bx
MSG_WRITE_LOOP:
movsb
loop MSG_WRITE_LOOP
mov dx, di
mov si, dx
mov dx, es
mov ds, dx
jmp INT22HEND
SET_MSG_V:
cmp byte[ds:si + MSG_OPENED_OFF], 0
je INT22HEND
;信号量设置(bh=0, 清零; bh=1, 加1; bh=2, 减1; bh=3, 设置为bl值)
mov bx, di
cmp bh, 0
je SET_MSG_V_CLEAR
cmp bh, 1
je SET_MSG_V_ADD
cmp bh, 2
je SET_MSG_V_DEC
cmp bh, 3
je SET_MSG_V_NUM
SET_MSG_V_CLEAR:
mov byte[ds:si+MSG_SIG_OFF],0
jmp INT22HEND
SET_MSG_V_ADD:
inc byte[ds:si+MSG_SIG_OFF]
jmp INT22HEND
SET_MSG_V_DEC:
dec byte[ds:si+MSG_SIG_OFF]
jmp INT22HEND
SET_MSG_V_NUM:
mov byte[ds:si+MSG_SIG_OFF],bl
jmp INT22HEND
RESET_MSG:
mov ax, 0x0001
mov word[ds:si], ax
mov word[ds:si + MSG_SIZE_OFF], cx
mov word[ds:si + MSG_OFFSET_OFF], di
mov ax, es
mov word[ds:si + MSG_SEG_OFF], ax
jmp INT22HEND
CLOSE_MSG:
xor al, al
mov byte[ds:si], al
jmp INT22HEND
INT22HEND:
;设置信号量
mov al, byte[ds:si + MSG_SIG_OFF]
pop di
pop si
pop ds
pop es
pop bx
pop cx
pop dx
iret
WKCNINTTimer:
;cli
;Save current Progress
;System Stack: *\flags\cs\ip
push ds
;System Stack: *\flags\cs\ip\ds(old)
push cs
;System Stack: *\flags\cs\ip\ds(old)\cs(kernel)
pop ds
;ds = data segment(kernel)
;System Stack: *\flags\cs\ip\ds(old)
mov [ds:AX_SAVE], ax
mov [ds:BX_SAVE], bx
mov [ds:CX_SAVE], cx
mov [ds:DX_SAVE], dx
mov ax, word[ds:RunID]
;Must have a progress, it is Shell :-)
;ES,DS,DI,SI,BP,SP,BX,DX,CX,AX,SS,IP,CS,FLAGS
mov bx,PCBSize
mul bx
;add ax, Processes; current process PCB
mov bx,ax
push ds
mov ax, PCB_SEGMENT
mov ds, ax
mov ax, es
mov [bx + _ES_OFFSET], ax
pop ds
mov ax, PCB_SEGMENT
mov es, ax
;SaveReg ES
SaveReg DI
SaveReg SI
SaveReg BP
pop word[es:(bx + _DS_OFFSET)] ;System Stack: *\flags\cs\ip\
nop; 如果不加这句,会丢失下面一条pop语句,奇怪的bug!
pop word[es:(bx + _IP_OFFSET)]
pop word[es:(bx + _CS_OFFSET)]
pop word[es:(bx + _FLAGS_OFFSET)]
;System Stack: *
SaveReg SP
mov ax, [ds:DX_SAVE]
mov [es:(bx + _DX_OFFSET)], ax
mov ax, [ds:CX_SAVE]
mov [es:(bx + _CX_OFFSET)], ax
mov ax, [ds:BX_SAVE]
mov [es:(bx + _BX_OFFSET)], ax
mov ax, ss
mov [es:(bx + _SS_OFFSET)], ax
mov ax, [ds:AX_SAVE]
mov [es:(bx + _AX_OFFSET)], ax
;All Saved!
;Run Next Program!
;进程调度
;ax 是将要运行的进程id
;可用寄存器, ax,bx
;运行用户程序
mov ax, word [ds:RunID]
mov cx, PCBSize
cmp byte [ds:CLOCKON], 1
jne GoodUserProg ; 不等于1, 说明切换关闭
;假如不是Running态, 不能继续运行
cmp byte [es:(bx + _STATE_OFFSET)], 1
jne FindUserProg
mov dl, byte [es:(bx + _UID_OFFSET)]
cmp dl, byte [ds:UserID]
jne FindUserProg
mov dl, byte [ds:PRIORITY_COUNT]
inc byte [ds:PRIORITY_COUNT]
;bx 还是之前程序的PCB偏移
cmp dl, byte [es:(bx + _PRIORITY_OFFSET)]
; <= 不高于,不进行进程切换
jna GoodUserProg
mov byte [ds:PRIORITY_COUNT], 0
FindUserProg:
inc ax
cmp ax, MaxRunNum
jb MayExUserProg
; 越界了
mov ax, 0
jmp GoodUserProg
;可能是要执行的用户程序
MayExUserProg:
push ax
mul cx
mov si, ax
pop ax
xor dx, dx
; 判断是否当前用户
mov dl, byte [es:(si + _UID_OFFSET)]
cmp byte [cs:UserID], dl
jne FindUserProg
;判断状态
mov dl, byte [es:(si + _STATE_OFFSET)]
shl dx, 1
mov di, dx
jmp word [cs:(ProgState + di)]
ProgState:
;EMPTY, RUNNING, SUSPEND, READY, DEAD, BLOCKED
dw FindUserProg, GoodUserProg, FindUserProg, ReadyState, DeadState, FindUserProg
ReadyState:
mov byte [es:(si + _STATE_OFFSET)], 1; Ready -> Running
jmp GoodUserProg
DeadState:
;Dead
cmp byte [es:(si + _KIND_OFFSET)], 2; 若等于则为线程
jne KillCommonProg
;线程终结处理
jmp FindUserProg ; 暂时处理方法为: 由主线程统一处理
%macro ReleaseProg 0
mov byte[cs:CLOCKON],0
push cx
push bx
push ax
;释放进程所占内存
mov ax, 0
mov bx, word [es:(si + _SEG_OFFSET)]
mov cx, word [es:(si + _SSIZE_OFFSET)]
sti
int 23h
;清除信号量
mov ah, 05h
mov al, byte [es:(si + _ID_OFFSET)]
sti
int 25h
mov byte [es:(si + _STATE_OFFSET)], 0
dec word [ds:RunNum]
pop ax
pop bx
pop cx
mov byte[cs:CLOCKON],1
%endmacro
KillCommonProg:
ReleaseProg
;杀死线程
mov bx, ax
push ax
mov ax, MaxRunNum - 1
KillThread:
push ax
mul cx
mov si, ax
pop ax
cmp byte [es:(si + _STATE_OFFSET)], 0 ; 空进程
je NOTTHREAD
cmp byte [es:(si + _KIND_OFFSET)], 2; 等于则线程
jne NOTTHREAD
cmp byte [es:(si + _PARENT_ID_OFFSET)], bl
jne NOTTHREAD
ReleaseProg
NOTTHREAD:
dec ax
jg KillThread
pop ax
jmp FindUserProg
GoodUserProg:
mov word[ds:RunID], ax
LOAD_PCB:
;Parameter: ax = RunID
;Stack: *
;Restart RunID(ax)
;Must have a progress, it is Shell :-)
;ES,DS,DI,SI,BP,SP,BX,DX,CX,AX,SS,IP,CS,FLAGS
mov bx,PCBSize
mul bx
;add ax, Processes; current process PCB
mov bx, ax
;Now DS is kernel DS
LoadReg SP
mov ax, word[es:(bx + _SS_OFFSET)]
mov ss, ax
mov ax, word[es:(bx + _FLAGS_OFFSET)]
push ax
mov ax, word[es:(bx + _CS_OFFSET)]
push ax
mov ax, word[es:(bx + _IP_OFFSET)]
push ax
LoadReg DI
LoadReg SI
LoadReg BP
;LoadReg ES
mov ax, es
mov ds, ax
mov ax, [es:(bx + _ES_OFFSET)]
mov es, ax
mov cx, [bx + _CX_OFFSET]
mov dx, [bx + _DX_OFFSET]
mov ax, [bx + _DS_OFFSET]
push ax
mov ax, [bx + _BX_OFFSET]
push ax
;*/flags/cs/ip/ds/bx
mov ax, [bx + _AX_OFFSET]
pop bx
pop ds
push ax
mov al,20h
out 20h,al
out 0A0h,al
pop ax
;sti
iret
%macro SetOffset 1
%1_OFFSET equ (%1 - Processes)
%endmacro
DATA:
AX_SAVE dw 0
BX_SAVE dw 0
CX_SAVE dw 0
DX_SAVE dw 0
IVT:
INT09HORG dd 0
INT09H_FLAG db 0
PCBCONST:
PCBSize equ FirstProcessEnd - Processes
SetOffset _ID
SetOffset _UID
SetOffset _STATE
SetOffset _NAME
SetOffset _SIZE
SetOffset _SSIZE
SetOffset _SEG
SetOffset _KIND
SetOffset _PARENT_ID
SetOffset _PRIORITY
SetOffset _ES
SetOffset _DS
SetOffset _DI
SetOffset _SI
SetOffset _BP
SetOffset _SP
SetOffset _BX
SetOffset _DX
SetOffset _CX
SetOffset _AX
SetOffset _SS
SetOffset _IP
SetOffset _CS
SetOffset _FLAGS
ProcessesTable:
RunID dw 0 ; default to open shell
UserID db 0
RunNum dw 1
PRIORITY_COUNT db 0
ProcessIDAssigner dw 1; 进程 ID 分配
CLOCKON db 1
Processes:
_ID db 0
_UID db 0
_STATE db 0 ; 结束态0, 运行态1
_NAME db "0123456789ABCDEF" ; 16 bytes
_KIND db 0
_PARENT_ID db 0
_BLOCK_NEXT db 0
_PRIORITY db 0
_SEG dw 0
_SSIZE dw 0
_SIZE dw 0
_ES dw 0
_DS dw 0
_DI dw 0
_SI dw 0
_BP dw 0
_SP dw 0
_BX dw 0
_DX dw 0
_CX dw 0
_AX dw 0
_SS dw 0
_IP dw 0
_CS dw 0
_FLAGS dw 512
FirstProcessEnd:
|
ada/original_2008/ada-gui/agar-gui-widget-scrollbar.ads | auzkok/libagar | 286 | 25675 | <filename>ada/original_2008/ada-gui/agar-gui-widget-scrollbar.ads<gh_stars>100-1000
with agar.core.event;
with agar.core.timeout;
package agar.gui.widget.scrollbar is
use type c.unsigned;
type type_t is (SCROLLBAR_HORIZ, SCROLLBAR_VERT);
for type_t use (SCROLLBAR_HORIZ => 0, SCROLLBAR_VERT => 1);
for type_t'size use c.unsigned'size;
pragma convention (c, type_t);
type button_t is (
SCROLLBAR_BUTTON_NONE,
SCROLLBAR_BUTTON_DEC,
SCROLLBAR_BUTTON_INC,
SCROLLBAR_BUTTON_SCROLL
);
for button_t use (
SCROLLBAR_BUTTON_NONE => 0,
SCROLLBAR_BUTTON_DEC => 1,
SCROLLBAR_BUTTON_INC => 2,
SCROLLBAR_BUTTON_SCROLL => 3
);
for button_t'size use c.unsigned'size;
pragma convention (c, button_t);
type flags_t is new c.unsigned;
SCROLLBAR_HFILL : constant flags_t := 16#01#;
SCROLLBAR_VFILL : constant flags_t := 16#02#;
SCROLLBAR_EXPAND : constant flags_t := SCROLLBAR_HFILL or SCROLLBAR_VFILL;
type scrollbar_t is limited private;
type scrollbar_access_t is access all scrollbar_t;
pragma convention (c, scrollbar_access_t);
-- API
function allocate_integer
(parent : widget_access_t;
bar_type : type_t;
flags : flags_t;
min : agar.core.types.integer_access_t;
max : agar.core.types.integer_access_t;
visible : agar.core.types.integer_access_t) return scrollbar_access_t;
pragma import (c, allocate_integer, "AG_ScrollbarNewInt");
function allocate_unsigned
(parent : widget_access_t;
bar_type : type_t;
flags : flags_t;
min : agar.core.types.unsigned_access_t;
max : agar.core.types.unsigned_access_t;
visible : agar.core.types.unsigned_access_t) return scrollbar_access_t;
pragma import (c, allocate_unsigned, "AG_ScrollbarNewUint");
function allocate_float
(parent : widget_access_t;
bar_type : type_t;
flags : flags_t;
min : agar.core.types.float_access_t;
max : agar.core.types.float_access_t;
visible : agar.core.types.float_access_t) return scrollbar_access_t;
pragma import (c, allocate_float, "AG_ScrollbarNewFloat");
function allocate_double
(parent : widget_access_t;
bar_type : type_t;
flags : flags_t;
min : agar.core.types.double_access_t;
max : agar.core.types.double_access_t;
visible : agar.core.types.double_access_t) return scrollbar_access_t;
pragma import (c, allocate_double, "AG_ScrollbarNewDouble");
function allocate_uint8
(parent : widget_access_t;
bar_type : type_t;
flags : flags_t;
value : agar.core.types.uint8_ptr_t;
min : agar.core.types.uint8_ptr_t;
max : agar.core.types.uint8_ptr_t;
visible : agar.core.types.uint8_ptr_t) return scrollbar_access_t;
pragma import (c, allocate_uint8, "AG_ScrollbarNewUint8");
function allocate_int8
(parent : widget_access_t;
bar_type : type_t;
flags : flags_t;
value : agar.core.types.int8_ptr_t;
min : agar.core.types.int8_ptr_t;
max : agar.core.types.int8_ptr_t;
visible : agar.core.types.int8_ptr_t) return scrollbar_access_t;
pragma import (c, allocate_int8, "AG_ScrollbarNewSint8");
function allocate_uint16
(parent : widget_access_t;
bar_type : type_t;
flags : flags_t;
value : agar.core.types.uint16_ptr_t;
min : agar.core.types.uint16_ptr_t;
max : agar.core.types.uint16_ptr_t;
visible : agar.core.types.uint16_ptr_t) return scrollbar_access_t;
pragma import (c, allocate_uint16, "AG_ScrollbarNewUint16");
function allocate_int16
(parent : widget_access_t;
bar_type : type_t;
flags : flags_t;
value : agar.core.types.int16_ptr_t;
min : agar.core.types.int16_ptr_t;
max : agar.core.types.int16_ptr_t;
visible : agar.core.types.int16_ptr_t) return scrollbar_access_t;
pragma import (c, allocate_int16, "AG_ScrollbarNewSint16");
function allocate_uint32
(parent : widget_access_t;
bar_type : type_t;
flags : flags_t;
value : agar.core.types.uint32_ptr_t;
min : agar.core.types.uint32_ptr_t;
max : agar.core.types.uint32_ptr_t;
visible : agar.core.types.uint32_ptr_t) return scrollbar_access_t;
pragma import (c, allocate_uint32, "AG_ScrollbarNewUint32");
function allocate_int32
(parent : widget_access_t;
bar_type : type_t;
flags : flags_t;
value : agar.core.types.int32_ptr_t;
min : agar.core.types.int32_ptr_t;
max : agar.core.types.int32_ptr_t;
visible : agar.core.types.int32_ptr_t) return scrollbar_access_t;
pragma import (c, allocate_int32, "AG_ScrollbarNewSint32");
procedure set_size
(scrollbar : scrollbar_access_t;
size : natural);
pragma inline (set_size);
function get_size (scrollbar : scrollbar_access_t) return natural;
pragma inline (get_size);
function visible (scrollbar : scrollbar_access_t) return boolean;
pragma inline (visible);
procedure set_increment
(scrollbar : scrollbar_access_t;
increment : positive);
pragma inline (set_increment);
procedure set_increment
(scrollbar : scrollbar_access_t;
increment : long_float);
pragma inline (set_increment);
function widget (scrollbar : scrollbar_access_t) return widget_access_t;
pragma inline (widget);
private
type scrollbar_t is record
widget : aliased widget_t;
flags : flags_t;
value : c.int;
min : c.int;
max : c.int;
visible : c.int;
bar_type : type_t;
bar_button : button_t;
button_width : c.int;
bar_width : c.int;
arrow_height : c.int;
button_inc_func : access agar.core.event.event_t;
button_dec_func : access agar.core.event.event_t;
scroll_to : agar.core.timeout.timeout_t;
inc_to : agar.core.timeout.timeout_t;
dec_to : agar.core.timeout.timeout_t;
x_offset : c.int;
extent : c.int;
r_inc : c.double;
i_inc : c.int;
end record;
pragma convention (c, scrollbar_t);
end agar.gui.widget.scrollbar;
|
x265/source/common/x86/intrapred8.asm | xu5343/ffmpegtoolkit_CentOS7 | 14 | 104212 | ;*****************************************************************************
;* Copyright (C) 2013-2017 MulticoreWare, Inc
;*
;* Authors: <NAME> <<EMAIL>> <<EMAIL>>
;* <NAME> <<EMAIL>>
;*
;* This program is free software; you can redistribute it and/or modify
;* it under the terms of the GNU General Public License as published by
;* the Free Software Foundation; either version 2 of the License, or
;* (at your option) any later version.
;*
;* This program is distributed in the hope that it will be useful,
;* but WITHOUT ANY WARRANTY; without even the implied warranty of
;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;* GNU General Public License for more details.
;*
;* You should have received a copy of the GNU General Public License
;* along with this program; if not, write to the Free Software
;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02111, USA.
;*
;* This program is also available under a commercial proprietary license.
;* For more information, contact us at license @ x265.com.
;*****************************************************************************/
%include "x86inc.asm"
%include "x86util.asm"
SECTION_RODATA 32
const intra_pred_shuff_0_8, times 2 db 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8
db 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9
intra_pred_shuff_15_0: times 2 db 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
intra_filter4_shuf0: times 2 db 2, 3, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
intra_filter4_shuf1: times 2 db 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
intra_filter4_shuf2: times 2 db 4, 5, 0, 1, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
pb_0_8 times 8 db 0, 8
pb_unpackbw1 times 2 db 1, 8, 2, 8, 3, 8, 4, 8
pb_swap8: times 2 db 7, 6, 5, 4, 3, 2, 1, 0
c_trans_4x4 db 0, 4, 8, 12, 1, 5, 9, 13, 2, 6, 10, 14, 3, 7, 11, 15
const tab_S1, db 15, 14, 12, 11, 10, 9, 7, 6, 5, 4, 2, 1, 0, 0, 0, 0
const tab_S2, db 0, 1, 3, 5, 7, 9, 11, 13, 0, 0, 0, 0, 0, 0, 0, 0
const tab_Si, db 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7
pb_fact0: db 0, 2, 4, 6, 8, 10, 12, 14, 0, 0, 0, 0, 0, 0, 0, 0
c_mode32_12_0: db 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 13, 7, 0
c_mode32_13_0: db 3, 6, 10, 13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
c_mode32_13_shuf: db 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0
c_mode32_14_shuf: db 15, 14, 13, 0, 2, 3, 4, 5, 6, 7, 10, 11, 12, 13, 14, 15
c_mode32_14_0: db 15, 12, 10, 7, 5, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
c_mode32_15_0: db 15, 13, 11, 9, 8, 6, 4, 2, 0, 0, 0, 0, 0, 0, 0, 0
c_mode32_16_0: db 15, 14, 12, 11, 9, 8, 6, 5, 3, 2, 0, 0, 0, 0, 0, 0
c_mode32_17_0: db 15, 14, 12, 11, 10, 9, 7, 6, 5, 4, 2, 1, 0, 0, 0, 0
c_mode32_18_0: db 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
c_shuf8_0: db 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8
c_deinterval8: db 0, 8, 1, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15
pb_unpackbq: db 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1
c_mode16_12: db 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 13, 6
c_mode16_13: db 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 11, 7, 4
c_mode16_14: db 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 12, 10, 7, 5, 2
c_mode16_15: db 0, 0, 0, 0, 0, 0, 0, 0, 15, 13, 11, 9, 8, 6, 4, 2
c_mode16_16: db 8, 6, 5, 3, 2, 0, 15, 14, 12, 11, 9, 8, 6, 5, 3, 2
c_mode16_17: db 4, 2, 1, 0, 15, 14, 12, 11, 10, 9, 7, 6, 5, 4, 2, 1
c_mode16_18: db 0, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1
ALIGN 32
c_ang8_src1_9_2_10: db 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9
c_ang8_26_20: db 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20
c_ang8_src3_11_4_12: db 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11
c_ang8_14_8: db 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8
c_ang8_src5_13_5_13: db 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12
c_ang8_2_28: db 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28
c_ang8_src6_14_7_15: db 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14
c_ang8_22_16: db 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16
c_ang8_21_10 : db 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10
c_ang8_src2_10_3_11: db 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10
c_ang8_31_20: db 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20
c_ang8_src4_12_4_12: times 2 db 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11
c_ang8_9_30: db 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30
c_ang8_src5_13_6_14: db 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13
c_ang8_19_8: db 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8
c_ang8_17_2: db 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2
c_ang8_19_4: db 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4
c_ang8_21_6: db 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6
c_ang8_23_8: db 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8,
c_ang8_src4_12_5_13: db 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12
c_ang8_13_26: db 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26
c_ang8_7_20: db 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20
c_ang8_1_14: db 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14
c_ang8_27_8: db 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8
c_ang8_src2_10_2_10: db 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9
c_ang8_src3_11_3_11: db 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10
c_ang8_31_8: db 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8
c_ang8_13_22: db 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22
c_ang8_27_4: db 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4
c_ang8_9_18: db 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18
c_ang8_5_10: db 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10
c_ang8_15_20: db 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20
c_ang8_25_30: db 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30
c_ang8_3_8: db 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8
c_ang8_mode_27: db 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4
db 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8
db 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12
db 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16
c_ang8_mode_25: db 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28
db 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24
db 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20
db 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16
c_ang8_mode_24: db 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22
db 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12
db 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2
db 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24
ALIGN 32
c_ang16_mode_25: db 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28
db 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24
db 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20
db 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16
db 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12
db 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8
db 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4
db 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0
ALIGN 32
c_ang16_mode_11: db 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14
db 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12
db 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10
db 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8
db 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6
db 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4
db 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2
db 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0
ALIGN 32
c_ang16_mode_12: db 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19
db 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14
db 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9
db 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4
db 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31
db 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26
db 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21
db 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16
ALIGN 32
c_ang16_mode_13: db 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15
db 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6
db 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29
db 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20
db 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11
db 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2
db 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25
db 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16
ALIGN 32
c_ang16_mode_28: db 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10
db 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20
db 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30
db 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8
db 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18
db 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28
db 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6
db 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16
ALIGN 32
c_ang16_mode_9: db 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18
db 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20
db 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22
db 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24
db 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26
db 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28
db 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30
db 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0
ALIGN 32
c_ang16_mode_27: db 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4
db 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8
db 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12
db 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16
db 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20
db 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24
db 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28
db 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30
db 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0
ALIGN 32
intra_pred_shuff_0_15: db 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15
ALIGN 32
c_ang16_mode_29: db 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18
db 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27
db 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13
db 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31
db 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17
db 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26
db 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12
db 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30
db 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16
ALIGN 32
c_ang16_mode_30: db 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26
db 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20
db 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14
db 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27
db 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21
db 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15
db 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28
db 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22
db 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16
ALIGN 32
c_ang16_mode_31: db 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17
db 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19
db 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21
db 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23
db 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25
db 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27
db 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29
db 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31
db 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16
ALIGN 32
c_ang16_mode_24: db 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22
db 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12
db 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2
db 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24
db 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14
db 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4
db 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26
db 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16
ALIGN 32
c_ang16_mode_23: db 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14
db 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5
db 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19
db 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1
db 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15
db 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6
db 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20
db 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2
db 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16
ALIGN 32
c_ang16_mode_22: db 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6
db 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12
db 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18
db 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5
db 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11
db 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17
db 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4
db 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10
db 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16
ALIGN 32
intra_pred_shuff_0_4: times 4 db 0, 1, 1, 2, 2, 3, 3, 4
intra_pred4_shuff1: db 0, 1, 1, 2, 2, 3, 3, 4, 0, 1, 1, 2, 2, 3, 3, 4, 0, 1, 1, 2, 2, 3, 3, 4, 1, 2, 2, 3, 3, 4, 4, 5
intra_pred4_shuff2: db 0, 1, 1, 2, 2, 3, 3, 4, 0, 1, 1, 2, 2, 3, 3, 4, 1, 2, 2, 3, 3, 4, 4, 5, 1, 2, 2, 3, 3, 4, 4, 5
intra_pred4_shuff31: db 0, 1, 1, 2, 2, 3, 3, 4, 1, 2, 2, 3, 3, 4, 4, 5, 1, 2, 2, 3, 3, 4, 4, 5, 2, 3, 3, 4, 4, 5, 5, 6
intra_pred4_shuff33: db 0, 1, 1, 2, 2, 3, 3, 4, 1, 2, 2, 3, 3, 4, 4, 5, 2, 3, 3, 4, 4, 5, 5, 6, 3, 4, 4, 5, 5, 6, 6, 7
intra_pred4_shuff3: db 8, 9, 9, 10, 10, 11, 11, 12, 9, 10, 10, 11, 11, 12, 12, 13, 10, 11, 11, 12, 12, 13, 13, 14, 11, 12, 12, 13, 13, 14, 14, 15
intra_pred4_shuff4: db 9, 10, 10, 11, 11, 12, 12, 13, 10, 11, 11, 12, 12, 13, 13, 14, 10, 11, 11, 12, 12, 13, 13, 14, 11, 12, 12, 13, 13, 14, 14, 15
intra_pred4_shuff5: db 9, 10, 10, 11, 11, 12, 12, 13, 10, 11, 11, 12, 12, 13, 13, 14, 10, 11, 11, 12, 12, 13, 13, 14, 11, 12, 12, 13, 13, 14, 14, 15
intra_pred4_shuff6: db 9, 10, 10, 11, 11, 12, 12, 13, 9, 10, 10, 11, 11, 12, 12, 13, 10, 11, 11, 12, 12, 13, 13, 14, 10, 11, 11, 12, 12, 13, 13, 14
intra_pred4_shuff7: db 9, 10, 10, 11, 11, 12, 12, 13, 9, 10, 10, 11, 11, 12, 12, 13, 9, 10, 10, 11, 11, 12, 12, 13, 10, 11, 11, 12, 12, 13, 13, 14
intra_pred4_shuff9: db 9, 10, 10, 11, 11, 12, 12, 13, 9, 10, 10, 11, 11, 12, 12, 13, 9, 10, 10, 11, 11, 12, 12, 13, 9, 10, 10, 11, 11, 12, 12, 13
intra_pred4_shuff12: db 0, 9, 9, 10, 10, 11, 11, 12, 0, 9, 9, 10, 10, 11, 11, 12, 0, 9, 9, 10, 10, 11, 11, 12,0, 9, 9, 10, 10, 11, 11, 12
intra_pred4_shuff13: db 0, 9, 9, 10, 10, 11, 11, 12, 0, 9, 9, 10, 10, 11, 11, 12, 0, 9, 9, 10, 10, 11, 11, 12, 4, 0, 0, 9, 9, 10, 10, 11
intra_pred4_shuff14: db 0, 9, 9, 10, 10, 11, 11, 12, 0, 9, 9, 10, 10, 11, 11, 12, 2, 0, 0, 9, 9, 10, 10, 11, 2, 0, 0, 9, 9, 10, 10, 11
intra_pred4_shuff15: db 0, 9, 9, 10, 10, 11, 11, 12, 2, 0, 0, 9, 9, 10, 10, 11, 2, 0, 0, 9, 9, 10, 10, 11, 4, 2, 2, 0, 0, 9, 9, 10
intra_pred4_shuff16: db 0, 9, 9, 10, 10, 11, 11, 12, 2, 0, 0, 9, 9, 10, 10, 11, 2, 0, 0, 9, 9, 10, 10, 11, 3, 2, 2, 0, 0, 9, 9, 10
intra_pred4_shuff17: db 0, 9, 9, 10, 10, 11, 11, 12, 1, 0, 0, 9, 9, 10, 10, 11, 2, 1, 1, 0, 0, 9, 9, 10, 4, 2, 2, 1, 1, 0, 0, 9
intra_pred4_shuff19: db 0, 1, 1, 2, 2, 3, 3, 4, 9, 0, 0, 1, 1, 2, 2, 3, 10, 9, 9, 0, 0, 1, 1, 2, 12, 10, 10, 9, 9, 0, 0, 1
intra_pred4_shuff20: db 0, 1, 1, 2, 2, 3, 3, 4, 10, 0, 0, 1, 1, 2, 2, 3, 10, 0, 0, 1, 1, 2, 2, 3, 11, 10, 10, 0, 0, 1, 1, 2
intra_pred4_shuff21: db 0, 1, 1, 2, 2, 3, 3, 4, 10, 0, 0, 1, 1, 2, 2, 3, 10, 0, 0, 1, 1, 2, 2, 3, 12, 10, 10, 0, 0, 1, 1, 2
intra_pred4_shuff22: db 0, 1, 1, 2, 2, 3, 3, 4, 0, 1, 1, 2, 2, 3, 3, 4, 10, 0, 0, 1, 1, 2, 2, 3, 10, 0, 0, 1, 1, 2, 2, 3
intra_pred4_shuff23: db 0, 1, 1, 2, 2, 3, 3, 4, 0, 1, 1, 2, 2, 3, 3, 4, 0, 1, 1, 2, 2, 3, 3, 4, 12, 0, 0, 1, 1, 2, 2, 3
c_ang4_mode_27: db 30, 2, 30, 2, 30, 2, 30, 2, 28, 4, 28, 4, 28, 4, 28, 4, 26, 6, 26, 6, 26, 6, 26, 6, 24, 8, 24, 8, 24, 8, 24, 8
c_ang4_mode_28: db 27, 5, 27, 5, 27, 5, 27, 5, 22, 10, 22, 10, 22, 10, 22, 10, 17, 15, 17, 15, 17, 15, 17, 15, 12, 20, 12, 20, 12, 20, 12, 20
c_ang4_mode_29: db 23, 9, 23, 9, 23, 9, 23, 9, 14, 18, 14, 18, 14, 18, 14, 18, 5, 27, 5, 27, 5, 27, 5, 27, 28, 4, 28, 4, 28, 4, 28, 4
c_ang4_mode_30: db 19, 13, 19, 13, 19, 13, 19, 13, 6, 26, 6, 26, 6, 26, 6, 26, 25, 7, 25, 7, 25, 7, 25, 7, 12, 20, 12, 20, 12, 20, 12, 20
c_ang4_mode_31: db 15, 17, 15, 17, 15, 17, 15, 17, 30, 2, 30, 2, 30, 2, 30, 2, 13, 19, 13, 19, 13, 19, 13, 19, 28, 4, 28, 4, 28, 4, 28, 4
c_ang4_mode_32: db 11, 21, 11, 21, 11, 21, 11, 21, 22, 10, 22, 10, 22, 10, 22, 10, 1, 31, 1, 31, 1, 31, 1, 31, 12, 20, 12, 20, 12, 20, 12, 20
c_ang4_mode_33: db 6, 26, 6, 26, 6, 26, 6, 26, 12, 20, 12, 20, 12, 20, 12, 20, 18, 14, 18, 14, 18, 14, 18, 14, 24, 8, 24, 8, 24, 8, 24, 8
c_ang4_mode_5: db 15, 17, 15, 17, 15, 17, 15, 17, 30, 2, 30, 2, 30, 2, 30, 2, 13, 19, 13, 19, 13, 19, 13, 19, 28, 4, 28, 4, 28, 4, 28, 4
c_ang4_mode_6: db 19, 13, 19, 13, 19, 13, 19, 13, 6, 26, 6, 26, 6, 26, 6, 26, 25, 7, 25, 7, 25, 7, 25, 7, 12, 20, 12, 20, 12, 20, 12, 20
c_ang4_mode_7: db 23, 9, 23, 9, 23, 9, 23, 9, 14, 18, 14, 18, 14, 18, 14, 18, 5, 27, 5, 27, 5, 27, 5, 27, 28, 4, 28, 4, 28, 4, 28, 4
c_ang4_mode_8: db 27, 5, 27, 5, 27, 5, 27, 5, 22, 10, 22, 10, 22, 10, 22, 10, 17, 15, 17, 15, 17, 15, 17, 15, 12, 20, 12, 20, 12, 20, 12, 20
c_ang4_mode_9: db 30, 2, 30, 2, 30, 2, 30, 2, 28, 4, 28, 4, 28, 4, 28, 4, 26, 6, 26, 6, 26, 6, 26, 6, 24, 8, 24, 8, 24, 8, 24, 8
c_ang4_mode_11: db 2, 30, 2, 30, 2, 30, 2, 30, 4, 28, 4, 28, 4, 28, 4, 28, 6, 26, 6, 26, 6, 26, 6, 26, 8, 24, 8, 24, 8, 24, 8, 24
c_ang4_mode_12: db 5, 27, 5, 27, 5, 27, 5, 27, 10, 22, 10, 22, 10, 22, 10, 22, 15, 17, 15, 17, 15, 17, 15, 17, 20, 12, 20, 12, 20, 12, 20, 12
c_ang4_mode_13: db 9, 23, 9, 23, 9, 23, 9, 23, 18, 14, 18, 14, 18, 14, 18, 14, 27, 5, 27, 5, 27, 5, 27, 5, 4, 28, 4, 28, 4, 28, 4, 28
c_ang4_mode_14: db 13, 19, 13, 19, 13, 19, 13, 19, 26, 6, 26, 6, 26, 6, 26, 6, 7, 25, 7, 25, 7, 25, 7, 25, 20, 12, 20, 12, 20, 12, 20, 12
c_ang4_mode_15: db 17, 15, 17, 15, 17, 15, 17, 15, 2, 30, 2, 30, 2, 30, 2, 30, 19, 13, 19, 13, 19, 13, 19, 13, 4, 28, 4, 28, 4, 28, 4, 28, 4
c_ang4_mode_16: db 21, 11, 21, 11, 21, 11, 21, 11, 10, 22, 10, 22, 10, 22, 10, 22, 31, 1, 31, 1, 31, 1, 31, 1, 20, 12, 20, 12, 20, 12, 20, 12
c_ang4_mode_17: db 26, 6, 26, 6, 26, 6, 26, 6, 20, 12, 20, 12, 20, 12, 20, 12, 14, 18, 14, 18, 14, 18, 14, 18, 8, 24, 8, 24, 8, 24, 8, 24
c_ang4_mode_19: db 26, 6, 26, 6, 26, 6, 26, 6, 20, 12, 20, 12, 20, 12, 20, 12, 14, 18, 14, 18, 14, 18, 14, 18, 8, 24, 8, 24, 8, 24, 8, 24
c_ang4_mode_20: db 21, 11, 21, 11, 21, 11, 21, 11, 10, 22, 10, 22, 10, 22, 10, 22, 31, 1, 31, 1, 31, 1, 31, 1, 20, 12, 20, 12, 20, 12, 20, 12
c_ang4_mode_21: db 17, 15, 17, 15, 17, 15, 17, 15, 2, 30, 2, 30, 2, 30, 2, 30, 19, 13, 19, 13, 19, 13, 19, 13, 4, 28, 4, 28, 4, 28, 4, 28
c_ang4_mode_22: db 13, 19, 13, 19, 13, 19, 13, 19, 26, 6, 26, 6, 26, 6, 26, 6, 7, 25, 7, 25, 7, 25, 7, 25, 20, 12, 20, 12, 20, 12, 20, 12
c_ang4_mode_23: db 9, 23, 9, 23, 9, 23, 9, 23, 18, 14, 18, 14, 18, 14, 18, 14, 27, 5, 27, 5, 27, 5, 27, 5, 4, 28, 4, 28, 4, 28, 4, 28
c_ang4_mode_24: db 5, 27, 5, 27, 5, 27, 5, 27, 10, 22, 10, 22, 10, 22, 10, 22, 15, 17, 15, 17, 15, 17, 15, 17, 20, 12, 20, 12, 20, 12, 20, 12
c_ang4_mode_25: db 2, 30, 2, 30, 2, 30, 2, 30, 4, 28, 4, 28, 4, 28, 4, 28, 6, 26, 6, 26, 6, 26, 6, 26, 8, 24, 8, 24, 8, 24, 8, 24
ALIGN 32
;; (blkSize - 1 - x)
pw_planar4_0: dw 3, 2, 1, 0, 3, 2, 1, 0
ALIGN 32
c_ang8_mode_13: db 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14
db 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28
db 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10
db 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24
ALIGN 32
c_ang8_mode_14: db 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6
db 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12
db 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18
db 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24
ALIGN 32
c_ang8_mode_15: db 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30
db 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28
db 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26
db 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24
const c_ang8_mode_16, db 8, 7, 6, 5, 4, 3, 2, 1, 0, 9, 10, 12, 13, 15, 0, 0
const intra_pred8_shuff16, db 0, 1, 1, 2, 3, 3, 4, 5
db 1, 2, 2, 3, 4, 4, 5, 6
db 2, 3, 3, 4, 5, 5, 6, 7
db 3, 4, 4, 5, 6, 6, 7, 8
db 4, 5, 5, 6, 7, 7, 8, 9
const angHor8_tab_16, db (32-11), 11, (32-22), 22, (32-1 ), 1, (32-12), 12, (32-23), 23, (32- 2), 2, (32-13), 13, (32-24), 24
const c_ang8_mode_20, db 15, 13, 12, 10, 9, 0, 1, 2, 3, 4, 5, 6, 7, 8, 0, 0
; NOTE: this big table improve speed ~10%, if we have broadcast instruction work on high-128bits infuture, we can remove the table
const angHor8_tab_20, times 8 db (32-24), 24
times 8 db (32-13), 13
times 8 db (32- 2), 2
times 8 db (32-23), 23
times 8 db (32-12), 12
times 8 db (32- 1), 1
times 8 db (32-22), 22
times 8 db (32-11), 11
const ang16_shuf_mode9, times 8 db 0, 1
times 8 db 1, 2
const angHor_tab_9, db (32-2), 2, (32-4), 4, (32-6), 6, (32-8), 8, (32-10), 10, (32-12), 12, (32-14), 14, (32-16), 16
db (32-18), 18, (32-20), 20, (32-22), 22, (32-24), 24, (32-26), 26, (32-28), 28, (32-30), 30, (32-32), 32
const angHor_tab_11, db (32-30), 30, (32-28), 28, (32-26), 26, (32-24), 24, (32-22), 22, (32-20), 20, (32-18), 18, (32-16), 16
db (32-14), 14, (32-12), 12, (32-10), 10, (32- 8), 8, (32- 6), 6, (32- 4), 4, (32- 2), 2, (32- 0), 0
const ang16_shuf_mode12, db 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 1, 2, 1, 2, 3, 4, 3, 4, 3, 4, 3, 4, 3, 4, 3, 4, 2, 3, 2, 3
db 1, 2, 1, 2, 1, 2, 1, 2, 0, 1, 0, 1, 0, 1, 0, 1, 2, 3, 2, 3, 2, 3, 2, 3, 1, 2, 1, 2, 1, 2, 1, 2
const angHor_tab_12, db (32-27), 27, (32-22), 22, (32-17), 17, (32-12), 12, (32-7), 7, (32-2), 2, (32-29), 29, (32-24), 24
db (32-19), 19, (32-14), 14, (32-9), 9, (32-4), 4, (32-31), 31, (32-26), 26, (32-21), 21, (32-16), 16
const ang16_shuf_mode13, db 4, 5, 4, 5, 4, 5, 3, 4, 3, 4, 3, 4, 3, 4, 2, 3, 5, 6, 5, 6, 5, 6, 4, 5, 4, 5, 4, 5, 4, 5, 3, 4
db 2, 3, 2, 3, 1, 2, 1, 2, 1, 2, 1, 2, 0, 1, 0, 1, 3, 4, 3, 4, 2, 3, 2, 3, 2, 3, 2, 3, 1, 2, 1, 2
db 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 11, 7, 4, 0, 0 ,0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 11, 7, 4, 0
const angHor_tab_13, db (32-23), 23, (32-14), 14, (32-5), 5, (32-28), 28, (32-19), 19, (32-10), 10, (32-1), 1, (32-24), 24
db (32-15), 15, (32-6), 6, (32-29), 29, (32-20), 20, (32-11), 11, (32-2), 2, (32-25), 25, (32-16), 16
const ang16_shuf_mode14, db 6, 7, 6, 7, 5, 6, 5, 6, 4, 5, 4, 5, 4, 5, 3, 4, 7, 8, 7, 8, 6, 7, 6, 7, 5, 6, 5, 6, 5, 6, 4, 5
db 3, 4, 2, 3, 2, 3, 2, 3, 1, 2, 1, 2, 0, 1, 0, 1, 4, 5, 3, 4, 3, 4, 3, 4, 2, 3, 2, 3, 1, 2, 1, 2
db 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 12, 10, 7, 5, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 12, 10, 7, 5, 2, 0
const angHor_tab_14, db (32-19), 19, (32-6), 6, (32-25), 25, (32-12), 12, (32-31), 31, (32-18), 18, (32-5), 5, (32-24), 24
db (32-11), 11, (32-30), 30, (32-17), 17, (32-4), 4, (32-23), 23, (32-10), 10, (32-29), 29, (32-16), 16
const ang16_shuf_mode15, db 8, 9, 7, 8, 7, 8, 6, 7, 6, 7, 5, 6, 5, 6, 4, 5, 9, 10, 8, 9, 8, 9, 7, 8, 7, 8, 6, 7, 6, 7, 5, 6
db 4, 5, 3, 4, 3, 4, 2, 3, 2, 3, 1, 2, 1, 2, 0, 1, 5, 6, 4, 5, 4, 5, 3, 4, 3, 4, 2, 3, 2, 3, 1, 2
db 0, 0, 0, 0, 0, 0, 0, 15, 13, 11, 9, 8, 6, 4, 2, 0, 0, 0, 0, 0, 0, 0, 0, 15, 13, 11, 9, 8, 6, 4, 2, 0
const angHor_tab_15, db (32-15), 15, (32-30), 30, (32-13), 13, (32-28), 28, (32-11), 11, (32-26), 26, (32-9), 9, (32-24), 24
db (32-7), 7, (32-22), 22, (32-5), 5, (32-20), 20, (32-3), 3, (32-18), 18, (32-1), 1, (32- 16), 16
const ang16_shuf_mode16, db 10, 11, 9, 10, 9, 10, 8, 9, 7, 8, 7, 8, 6, 7, 5, 6, 11, 12, 10, 11, 10, 11, 9, 10, 8, 9, 8, 9, 7, 8, 6, 7
db 5, 6, 4, 5, 3, 4, 3, 4, 2, 3, 1, 2, 1, 2, 0, 1, 6, 7, 5, 6, 4, 5, 4, 5, 3, 4, 2, 3, 2, 3, 1, 2
db 0 ,0, 0, 0, 0, 15, 14, 12 , 11, 9, 8, 6, 5, 3, 2, 0, 0, 0, 0, 0, 0, 15, 14, 12, 11, 9, 8, 6, 5, 3, 2, 0
const angHor_tab_16, db (32-11), 11, (32-22), 22, (32-1), 1, (32-12), 12, (32-23), 23, (32-2), 2, (32-13), 13, (32-24), 24
db (32-3), 3, (32-14), 14, (32-25), 25, (32-4), 4, (32-15), 15, (32-26), 26, (32-5), 5, (32-16), 16
const ang16_shuf_mode17, db 12, 13, 11, 12, 10, 11, 9, 10, 8, 9, 8, 9, 7, 8, 6, 7, 13, 14, 12, 13, 11, 12, 10, 11, 9, 10, 9, 10, 8, 9, 7, 8
db 5, 6, 4, 5, 4, 5, 3, 4, 2, 3, 1, 2, 0, 1, 0, 1, 6, 7, 5, 6, 5, 6, 4, 5, 3, 4, 2, 3, 1, 2, 1, 2
db 0, 0, 0, 15, 14, 12, 11, 10, 9, 7, 6, 5, 4, 2, 1, 0, 0, 0, 0, 15, 14, 12, 11, 10, 9, 7, 6, 5, 4, 2, 1, 0
const angHor_tab_17, db (32- 6), 6, (32-12), 12, (32-18), 18, (32-24), 24, (32-30), 30, (32- 4), 4, (32-10), 10, (32-16), 16
db (32-22), 22, (32-28), 28, (32- 2), 2, (32- 8), 8, (32-14), 14, (32-20), 20, (32-26), 26, (32- 0), 0
; Intrapred_angle32x32, modes 1 to 33 constants
const ang32_shuf_mode9, times 8 db 0, 1
times 8 db 1, 2
const ang32_shuf_mode11, times 8 db 1, 2
times 8 db 0, 1
const ang32_fact_mode12, db (32-27), 27, (32-22), 22, (32-17), 17, (32-12), 12, (32- 7), 7, (32- 2), 2, (32-29), 29, (32-24), 24
db (32-11), 11, (32- 6), 6, (32- 1), 1, (32-28), 28, (32-23), 23, (32-18), 18, (32-13), 13, (32- 8), 8
db (32-19), 19, (32-14), 14, (32- 9), 9, (32- 4), 4, (32-31), 31, (32-26), 26, (32-21), 21, (32-16), 16
db (32- 3), 3, (32-30), 30, (32-25), 25, (32-20), 20, (32-15), 15, (32-10), 10, (32- 5), 5, (32- 0), 0
const ang32_shuf_mode12, db 4, 5, 4, 5, 4, 5, 4, 5, 4, 5, 4, 5, 3, 4, 3, 4, 2, 3, 2, 3, 2, 3, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2
db 3, 4, 3, 4, 3, 4, 3, 4, 2, 3, 2, 3, 2, 3, 2, 3, 1, 2, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1
const ang32_shuf_mode24, db 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 13, 13, 6, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 10, 3, 3
dd 0, 0, 7, 3, 0, 0, 7, 3
const ang32_fact_mode13, db (32-23), 23, (32-14), 14, (32- 5), 5, (32-28), 28, (32-19), 19, (32-10), 10, (32- 1), 1, (32-24), 24
db (32- 7), 7, (32-30), 30, (32-21), 21, (32-12), 12, (32- 3), 3, (32-26), 26, (32-17), 17, (32- 8), 8
db (32-15), 15, (32- 6), 6, (32-29), 29, (32-20), 20, (32-11), 11, (32- 2), 2, (32-25), 25, (32-16), 16
db (32-31), 31, (32-22), 22, (32-13), 13, (32- 4), 4, (32-27), 27, (32-18), 18, (32- 9), 9, (32- 0), 0
const ang32_shuf_mode13, db 14, 15, 14, 15, 14, 15, 13, 14, 13, 14, 13, 14, 13, 14, 12, 13, 10, 11, 9, 10, 9, 10, 9, 10, 9, 10, 8, 9, 8, 9, 8, 9
db 12, 13, 12, 13, 11, 12, 11, 12, 11, 12, 11, 12, 10, 11, 10, 11, 7, 8, 7, 8, 7, 8, 7, 8, 6, 7, 6, 7, 6, 7, 6, 7
db 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 11, 7, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 9, 5, 2
const ang32_shuf_mode23, db 0, 0, 0, 0, 0, 0, 0, 0, 14, 14, 11, 11, 7, 7, 4, 4, 0, 0, 0, 0, 0, 0, 0, 0, 12, 12, 9, 9, 5, 5, 2, 2
const ang32_fact_mode14, db (32-19), 19, (32- 6), 6, (32-25), 25, (32-12), 12, (32-31), 31, (32-18), 18, (32- 5), 5, (32-24), 24
db (32- 3), 3, (32-22), 22, (32- 9), 9, (32-28), 28, (32-15), 15, (32- 2), 2, (32-21), 21, (32- 8), 8
db (32-11), 11, (32-30), 30, (32-17), 17, (32- 4), 4, (32-23), 23, (32-10), 10, (32-29), 29, (32-16), 16
db (32-27), 27, (32-14), 14, (32- 1), 1, (32-20), 20, (32- 7), 7, (32-26), 26, (32-13), 13, (32- 0), 0
const ang32_shuf_mode14, db 14, 15, 14, 15, 13, 14, 13, 14, 12, 13, 12, 13, 12, 13, 11, 12, 8, 9, 7, 8, 7, 8, 6, 7, 6, 7, 6, 7, 5, 6, 5, 6
db 11, 12, 10, 11, 10, 11, 10, 11, 9, 10, 9, 10, 8, 9, 8, 9, 4, 5, 4, 5, 4, 5, 3, 4, 3, 4, 2, 3, 2, 3, 2, 3
db 0, 0, 0, 0, 0, 0, 0, 0, 15, 12, 10, 7, 5, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 11, 9, 6, 4, 1
const ang32_shuf_mode22, db 0, 0, 15, 15, 13, 13, 10, 10, 8, 8, 5, 5, 3, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 12, 9, 9, 7, 7, 4, 4, 2
const ang32_fact_mode15, db (32-15), 15, (32-30), 30, (32-13), 13, (32-28), 28, (32-11), 11, (32-26), 26, (32- 9), 9, (32-24), 24
db (32-31), 31, (32-14), 14, (32-29), 29, (32-12), 12, (32-27), 27, (32-10), 10, (32-25), 25, (32- 8), 8
db (32- 7), 7, (32-22), 22, (32- 5), 5, (32-20), 20, (32- 3), 3, (32-18), 18, (32- 1), 1, (32-16), 16
db (32-23), 23, (32- 6), 6, (32-21), 21, (32- 4), 4, (32-19), 19, (32- 2), 2, (32-17), 17, (32- 0), 0
const ang32_shuf_mode15, db 14, 15, 13, 14, 13, 14, 12, 13, 12, 13, 11, 12, 11, 12, 10, 11, 5, 6, 5, 6, 4, 5, 4, 5, 3, 4, 3, 4, 2, 3, 2, 3
db 12, 13, 11, 12, 11, 12, 10, 11, 10, 11, 9, 10, 9, 10, 8, 9, 3, 4, 3, 4, 2, 3, 2, 3, 1, 2, 1, 2, 0, 1, 0, 1
db 0, 0, 0, 0, 0, 0, 0, 0, 15, 13, 11, 9, 8, 6, 4, 2, 0, 0, 0, 0, 0, 0, 0, 0, 14, 12, 10, 8, 7, 5, 3, 1
const ang32_shuf_mode21, db 15, 15, 13, 13, 11, 11, 9, 9, 8, 8, 6, 6, 4, 4, 2, 2, 14, 14, 12, 12, 10, 10, 8, 8, 7, 7, 5, 5, 3, 3, 1, 1
const ang32_fact_mode16, db (32-11), 11, (32-22), 22, (32- 1), 1, (32-12), 12, (32-23), 23, (32- 2), 2, (32-13), 13, (32-24), 24
db (32- 3), 3, (32-14), 14, (32-25), 25, (32- 4), 4, (32-15), 15, (32-26), 26, (32- 5), 5, (32-16), 16
db (32-27), 27, (32- 6), 6, (32-17), 17, (32-28), 28, (32- 7), 7, (32-18), 18, (32-29), 29, (32- 8), 8
db (32-19), 19, (32-30), 30, (32- 9), 9, (32-20), 20, (32-31), 31, (32-10), 10, (32-21), 21, (32- 0), 0
const ang32_shuf_mode16, db 14, 15, 13, 14, 13, 14, 12, 13, 11, 12, 11, 12, 10, 11, 9, 10, 9, 10, 8, 9, 7, 8, 7, 8, 6, 7, 5, 6, 5, 6, 4, 5
db 14, 15, 14, 15, 13, 14, 12, 13, 12, 13, 11, 12, 10, 11, 10, 11, 9, 10, 8, 9, 8, 9, 7, 8, 6, 7, 6, 7, 5, 6, 5, 6
db 0, 0, 0, 0, 15, 14, 12, 11, 9, 8, 6, 5, 3, 2, 0, 0, 0, 0, 0, 0, 0, 0, 14, 13, 11, 10, 8, 7, 5, 4, 2, 1
dd 7, 1, 2, 3, 7, 1, 2, 3
const ang32_shuf_mode20, db 12, 11, 9, 8, 6, 5, 3, 2, 0, 0, 0, 0, 0, 0, 14, 15, 8, 7, 5, 4, 2, 1, 0, 0, 14, 13, 13, 11, 11, 10, 10, 8
db 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 1, 1, 0, 0
const ang32_fact_mode17, db (32- 6), 6, (32-12), 12, (32-18), 18, (32-24), 24, (32-30), 30, (32- 4), 4, (32-10), 10, (32-16), 16
db (32-22), 22, (32-28), 28, (32- 2), 2, (32- 8), 8, (32-14), 14, (32-20), 20, (32-26), 26, (32- 0), 0
const ang32_shuf_mode17, db 14, 15, 13, 14, 12, 13, 11, 12, 10, 11, 10, 11, 9, 10, 8, 9, 7, 8, 6, 7, 6, 7, 5, 6, 4, 5, 3, 4, 2, 3, 2, 3
db 0, 0, 0, 0, 15, 14, 12, 11, 10, 9, 7, 6, 5, 4, 2, 1, 0, 0, 0, 15, 14, 12, 11, 10, 9, 7, 6, 5, 4, 2, 1, 0
const ang32_shuf_mode19, db 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15
dd 0, 0, 2, 3, 0, 0, 7, 1
dd 0, 0, 5, 6, 0, 0, 0, 0
; Intrapred_angle8x8, modes 1 to 33 constants
const ang8_shuf_mode3, db 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 4, 5, 5, 6, 6, 7, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 5, 6, 6, 7, 7, 8
const ang8_shuf_mode4, db 0, 1, 1, 2, 1, 2, 2, 3, 3, 4, 3, 4, 4, 5, 5, 6, 1, 2, 2, 3, 2, 3, 3, 4, 4, 5, 4, 5, 5, 6, 6, 7
const ang8_shuf_mode5, db 0, 1, 1, 2, 1, 2, 2, 3, 2, 3, 3, 4, 3, 4, 4, 5, 1, 2, 2, 3, 2, 3, 3, 4, 3, 4, 4, 5, 4, 5, 5, 6
const ang8_shuf_mode6, db 0, 1, 0, 1, 1, 2, 1, 2, 2, 3, 2, 3, 2, 3, 3, 4, 1, 2, 1, 2, 2, 3, 2, 3, 3, 4, 3, 4, 3, 4, 4, 5
const ang8_shuf_mode7, db 0, 1, 0, 1, 0, 1, 1, 2, 1, 2, 1, 2, 1, 2, 2, 3, 1, 2, 1, 2, 1, 2, 2, 3, 2, 3, 2, 3, 2, 3, 3, 4
const ang8_shuf_mode8, db 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 2, 3, 2, 3
const ang8_shuf_mode9, db 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2
const ang8_shuf_mode12, db 7, 8, 7, 8, 7, 8, 7, 8, 7, 8, 7, 8, 6, 7, 6, 7, 8, 9, 8, 9, 8, 9, 8, 9, 8, 9, 8, 9, 7, 8, 7, 8
const ang8_shuf_mode13, db 8, 9, 8, 9, 8, 9, 7, 8, 7, 8, 7, 8, 7, 8, 6, 7, 9, 10, 9, 10, 9, 10, 8, 9, 8, 9, 8, 9, 8, 9, 7, 8
const ang8_shuf_mode14, db 9, 10, 9, 10, 8, 9, 8, 9, 7, 8, 7, 8, 7, 8, 6, 7, 10, 11, 10, 11, 9, 10, 9, 10, 8, 9, 8, 9, 8, 9, 7, 8
const ang8_shuf_mode15, db 10, 11, 9, 10, 9, 10, 8, 9, 8, 9, 7, 8, 7, 8, 6, 7, 11, 12, 10, 11, 10, 11, 9, 10, 9, 10, 8, 9, 8, 9, 7, 8
db 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 6, 4, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 6, 4, 2, 0
const ang8_shuf_mode16, db 11, 12, 10, 11, 10, 11, 9, 10, 8, 9, 8, 9, 7, 8, 6, 7, 12, 13, 11, 12, 11, 12, 10, 11, 9, 10, 9, 10, 8, 9, 7, 8
db 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 6, 5, 3, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 6, 5, 3, 2, 0
const ang8_shuf_mode17, db 12, 13, 11, 12, 10, 11, 9, 10, 8, 9, 8, 9, 7, 8, 6, 7, 13, 14, 12, 13, 11, 12, 10, 11, 9, 10, 9, 10, 8, 9, 7, 8
db 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 2, 1, 0
const ang8_fact_mode3, db (32-26), 26, (32-20), 20, (32-14), 14, (32- 8), 8, (32- 2), 2, (32-28), 28, (32-22), 22, (32-16), 16
const ang8_fact_mode4, db (32-21), 21, (32-10), 10, (32-31), 31, (32-20), 20, (32- 9), 9, (32-30), 30, (32-19), 19, (32- 8), 8
const ang8_fact_mode5, db (32-17), 17, (32- 2), 2, (32-19), 19, (32- 4), 4, (32-21), 21, (32- 6), 6, (32-23), 23, (32- 8), 8
const ang8_fact_mode6, db (32-13), 13, (32-26), 26, (32- 7), 7, (32-20), 20, (32- 1), 1, (32-14), 14, (32-27), 27, (32- 8), 8
const ang8_fact_mode7, db (32- 9), 9, (32-18), 18, (32-27), 27, (32- 4), 4, (32-13), 13, (32-22), 22, (32-31), 31, (32- 8), 8
const ang8_fact_mode8, db (32- 5), 5, (32-10), 10, (32-15), 15, (32-20), 20, (32-25), 25, (32-30), 30, (32- 3), 3, (32- 8), 8
const ang8_fact_mode9, db (32- 2), 2, (32- 4), 4, (32- 6), 6, (32- 8), 8, (32-10), 10, (32-12), 12, (32-14), 14, (32-16), 16
const ang8_fact_mode11, db (32-30), 30, (32-28), 28, (32-26), 26, (32-24), 24, (32-22), 22, (32-20), 20, (32-18), 18, (32-16), 16
const ang8_fact_mode12, db (32-27), 27, (32-22), 22, (32-17), 17, (32-12), 12, (32- 7), 7, (32- 2), 2, (32-29), 29, (32-24), 24
const ang8_fact_mode13, db (32-23), 23, (32-14), 14, (32- 5), 5, (32-28), 28, (32-19), 19, (32-10), 10, (32- 1), 1, (32-24), 24
const ang8_fact_mode14, db (32-19), 19, (32- 6), 6, (32-25), 25, (32-12), 12, (32-31), 31, (32-18), 18, (32- 5), 5, (32-24), 24
const ang8_fact_mode15, db (32-15), 15, (32-30), 30, (32-13), 13, (32-28), 28, (32-11), 11, (32-26), 26, (32- 9), 9, (32-24), 24
const ang8_fact_mode16, db (32-11), 11, (32-22), 22, (32- 1), 1, (32-12), 12, (32-23), 23, (32- 2), 2, (32-13), 13, (32-24), 24
const ang8_fact_mode17, db (32- 6), 6, (32-12), 12, (32-18), 18, (32-24), 24, (32-30), 30, (32- 4), 4, (32-10), 10, (32-16), 16
const ang_table
%assign x 0
%rep 32
times 8 db (32-x), x
%assign x x+1
%endrep
const ang_table_avx2
%assign x 0
%rep 32
times 16 db (32-x), x
%assign x x+1
%endrep
const pw_ang_table
%assign x 0
%rep 32
times 4 dw (32-x), x
%assign x x+1
%endrep
SECTION .text
cextern pb_1
cextern pb_2
cextern pw_2
cextern pw_3
cextern pw_4
cextern pw_7
cextern pw_8
cextern pw_16
cextern pw_15
cextern pw_31
cextern pw_32
cextern pw_257
cextern pw_512
cextern pw_1024
cextern pw_4096
cextern pw_00ff
cextern pb_unpackbd1
cextern multiL
cextern multiH
cextern multiH2
cextern multiH3
cextern multi_2Row
cextern trans8_shuf
cextern pw_planar16_mul
cextern pw_planar32_mul
;---------------------------------------------------------------------------------------------
; void intra_pred_dc(pixel* dst, intptr_t dstStride, pixel *srcPix, int dirMode, int bFilter)
;---------------------------------------------------------------------------------------------
INIT_XMM sse2
cglobal intra_pred_dc4, 5,5,3
inc r2
pxor m0, m0
movu m1, [r2]
pshufd m1, m1, 0xF8
psadbw m1, m0 ; m1 = sum
test r4d, r4d
paddw m1, [pw_4]
psraw m1, 3
movd r4d, m1 ; r4d = dc_val
pmullw m1, [pw_257]
pshuflw m1, m1, 0x00
; store DC 4x4
lea r3, [r1 * 3]
movd [r0], m1
movd [r0 + r1], m1
movd [r0 + r1 * 2], m1
movd [r0 + r3], m1
; do DC filter
jz .end
lea r3d, [r4d * 2 + 2] ; r3d = DC * 2 + 2
add r4d, r3d ; r4d = DC * 3 + 2
movd m1, r4d
pshuflw m1, m1, 0 ; m1 = pixDCx3
; filter top
movd m2, [r2]
punpcklbw m2, m0
paddw m2, m1
psraw m2, 2
packuswb m2, m2
movd [r0], m2 ; overwrite top-left pixel, we will update it later
; filter top-left
movzx r4d, byte [r2 + 8]
add r3d, r4d
movzx r4d, byte [r2]
add r3d, r4d
shr r3d, 2
mov [r0], r3b
; filter left
add r0, r1
movq m2, [r2 + 9]
punpcklbw m2, m0
paddw m2, m1
psraw m2, 2
packuswb m2, m2
%if ARCH_X86_64
movq r4, m2
mov [r0], r4b
shr r4, 8
mov [r0 + r1], r4b
shr r4, 8
mov [r0 + r1 * 2], r4b
%else
movd r2d, m2
mov [r0], r2b
shr r2, 8
mov [r0 + r1], r2b
shr r2, 8
mov [r0 + r1 * 2], r2b
%endif
.end:
RET
;---------------------------------------------------------------------------------------------
; void intra_pred_dc(pixel* dst, intptr_t dstStride, pixel *srcPix, int dirMode, int bFilter)
;---------------------------------------------------------------------------------------------
INIT_XMM sse2
cglobal intra_pred_dc8, 5, 7, 3
pxor m0, m0
movh m1, [r2 + 1]
movh m2, [r2 + 17]
punpcklqdq m1, m2
psadbw m1, m0
pshufd m2, m1, 2
paddw m1, m2
paddw m1, [pw_8]
psraw m1, 4
pmullw m1, [pw_257]
pshuflw m1, m1, 0x00 ; m1 = byte [dc_val ...]
test r4d, r4d
; store DC 8x8
lea r6, [r1 + r1 * 2]
lea r5, [r6 + r1 * 2]
movh [r0], m1
movh [r0 + r1], m1
movh [r0 + r1 * 2], m1
movh [r0 + r6], m1
movh [r0 + r1 * 4], m1
movh [r0 + r5], m1
movh [r0 + r6 * 2], m1
lea r5, [r5 + r1 * 2]
movh [r0 + r5], m1
; Do DC Filter
jz .end
psrlw m1, 8
movq m2, [pw_2]
pmullw m2, m1
paddw m2, [pw_2]
movd r4d, m2 ; r4d = DC * 2 + 2
paddw m1, m2 ; m1 = DC * 3 + 2
pshufd m1, m1, 0
; filter top
movq m2, [r2 + 1]
punpcklbw m2, m0
paddw m2, m1
psraw m2, 2 ; sum = sum / 16
packuswb m2, m2
movh [r0], m2
; filter top-left
movzx r3d, byte [r2 + 17]
add r4d, r3d
movzx r3d, byte [r2 + 1]
add r3d, r4d
shr r3d, 2
mov [r0], r3b
; filter left
movq m2, [r2 + 18]
punpcklbw m2, m0
paddw m2, m1
psraw m2, 2
packuswb m2, m2
movd r2d, m2
lea r0, [r0 + r1]
lea r5, [r6 + r1 * 2]
mov [r0], r2b
shr r2, 8
mov [r0 + r1], r2b
shr r2, 8
mov [r0 + r1 * 2], r2b
shr r2, 8
mov [r0 + r6], r2b
pshufd m2, m2, 0x01
movd r2d, m2
mov [r0 + r1 * 4], r2b
shr r2, 8
mov [r0 + r5], r2b
shr r2, 8
mov [r0 + r6 * 2], r2b
.end:
RET
;--------------------------------------------------------------------------------------------
; void intra_pred_dc(pixel* dst, intptr_t dstStride, pixel *srcPix, int dirMode, int bFilter)
;--------------------------------------------------------------------------------------------
INIT_XMM sse2
%if ARCH_X86_64
cglobal intra_pred_dc16, 5, 10, 4
%else
cglobal intra_pred_dc16, 5, 7, 4
%endif
pxor m0, m0
movu m1, [r2 + 1]
movu m2, [r2 + 33]
psadbw m1, m0
psadbw m2, m0
paddw m1, m2
pshufd m2, m1, 2
paddw m1, m2
paddw m1, [pw_16]
psraw m1, 5
pmullw m1, [pw_257]
pshuflw m1, m1, 0x00 ; m1 = byte [dc_val ...]
pshufd m1, m1, 0x00
test r4d, r4d
; store DC 16x16
%if ARCH_X86_64
lea r6, [r1 + r1 * 2] ;index 3
lea r7, [r1 + r1 * 4] ;index 5
lea r8, [r6 + r1 * 4] ;index 7
lea r9, [r0 + r8] ;base + 7
movu [r0], m1
movu [r0 + r1], m1
movu [r0 + r1 * 2], m1
movu [r0 + r6], m1
movu [r0 + r1 * 4], m1
movu [r0 + r7], m1
movu [r0 + r6 * 2], m1
movu [r0 + r8], m1
movu [r0 + r1 * 8], m1
movu [r9 + r1 * 2], m1
movu [r0 + r7 * 2], m1
movu [r9 + r1 * 4], m1
movu [r0 + r6 * 4], m1
movu [r9 + r6 * 2], m1
movu [r0 + r8 * 2], m1
movu [r9 + r1 * 8], m1
%else ;32 bit
mov r6, r0
movu [r0], m1
movu [r0 + r1], m1
lea r0, [r0 + r1 * 2]
movu [r0], m1
movu [r0 + r1], m1
lea r0, [r0 + r1 * 2]
movu [r0], m1
movu [r0 + r1], m1
lea r0, [r0 + r1 * 2]
movu [r0], m1
movu [r0 + r1], m1
lea r0, [r0 + r1 * 2]
movu [r0], m1
movu [r0 + r1], m1
lea r0, [r0 + r1 * 2]
movu [r0], m1
movu [r0 + r1], m1
lea r0, [r0 + r1 * 2]
movu [r0], m1
movu [r0 + r1], m1
lea r0, [r0 + r1 * 2]
movu [r0], m1
movu [r0 + r1], m1
%endif
; Do DC Filter
jz .end
psrlw m1, 8
mova m2, [pw_2]
pmullw m2, m1
paddw m2, [pw_2]
movd r4d, m2
paddw m1, m2
; filter top
movh m2, [r2 + 1]
punpcklbw m2, m0
paddw m2, m1
psraw m2, 2
packuswb m2, m2
movh m3, [r2 + 9]
punpcklbw m3, m0
paddw m3, m1
psraw m3, 2
packuswb m3, m3
; filter top-left
movzx r5d, byte [r2 + 33]
add r4d, r5d
movzx r3d, byte [r2 + 1]
add r3d, r4d
shr r3d, 2
%if ARCH_X86_64
movh [r0], m2
movh [r0 + 8], m3
mov [r0], r3b
%else ;32 bit
movh [r6], m2
movh [r6 + 8], m3
mov [r6], r3b
add r6, r1
%endif
; filter left
movh m2, [r2 + 34]
punpcklbw m2, m0
paddw m2, m1
psraw m2, 2
packuswb m2, m2
movh m3, [r2 + 42]
punpcklbw m3, m0
paddw m3, m1
psraw m3, 2
packuswb m3, m3
%if ARCH_X86_64
movh r3, m2
mov [r0 + r1], r3b
shr r3, 8
mov [r0 + r1 * 2], r3b
shr r3, 8
mov [r0 + r6], r3b
shr r3, 8
mov [r0 + r1 * 4], r3b
shr r3, 8
mov [r0 + r7], r3b
shr r3, 8
mov [r0 + r6 * 2], r3b
shr r3, 8
mov [r0 + r8], r3b
shr r3, 8
mov [r0 + r1 * 8], r3b
movh r3, m3
mov [r9 + r1 * 2], r3b
shr r3, 8
mov [r0 + r7 * 2], r3b
shr r3, 8
mov [r9 + r1 * 4], r3b
shr r3, 8
mov [r0 + r6 * 4], r3b
shr r3, 8
mov [r9 + r6 * 2], r3b
shr r3, 8
mov [r0 + r8 * 2], r3b
shr r3, 8
mov [r9 + r1 * 8], r3b
%else ;32 bit
movd r2d, m2
pshufd m2, m2, 0x01
mov [r6], r2b
shr r2, 8
mov [r6 + r1], r2b
shr r2, 8
mov [r6 + r1 * 2], r2b
lea r6, [r6 + r1 * 2]
shr r2, 8
mov [r6 + r1], r2b
movd r2d, m2
mov [r6 + r1 * 2], r2b
lea r6, [r6 + r1 * 2]
shr r2, 8
mov [r6 + r1], r2b
shr r2, 8
mov [r6 + r1 * 2], r2b
lea r6, [r6 + r1 * 2]
shr r2, 8
mov [r6 + r1], r2b
movd r2d, m3
pshufd m3, m3, 0x01
mov [r6 + r1 * 2], r2b
lea r6, [r6 + r1 * 2]
shr r2, 8
mov [r6 + r1], r2b
shr r2, 8
mov [r6 + r1 * 2], r2b
lea r6, [r6 + r1 * 2]
shr r2, 8
mov [r6 + r1], r2b
movd r2d, m3
mov [r6 + r1 * 2], r2b
lea r6, [r6 + r1 * 2]
shr r2, 8
mov [r6 + r1], r2b
shr r2, 8
mov [r6 + r1 * 2], r2b
%endif
.end:
RET
;---------------------------------------------------------------------------------------------
; void intra_pred_dc(pixel* dst, intptr_t dstStride, pixel *srcPix, int dirMode, int bFilter)
;---------------------------------------------------------------------------------------------
INIT_XMM sse2
cglobal intra_pred_dc32, 3, 3, 5
pxor m0, m0
movu m1, [r2 + 1]
movu m2, [r2 + 17]
movu m3, [r2 + 65]
movu m4, [r2 + 81]
psadbw m1, m0
psadbw m2, m0
psadbw m3, m0
psadbw m4, m0
paddw m1, m2
paddw m3, m4
paddw m1, m3
pshufd m2, m1, 2
paddw m1, m2
paddw m1, [pw_32]
psraw m1, 6
pmullw m1, [pw_257]
pshuflw m1, m1, 0x00 ; m1 = byte [dc_val ...]
pshufd m1, m1, 0x00
%assign x 0
%rep 16
; store DC 16x16
movu [r0], m1
movu [r0 + r1], m1
movu [r0 + 16], m1
movu [r0 + r1 + 16], m1
%if x < 16
lea r0, [r0 + 2 * r1]
%endif
%assign x x+1
%endrep
RET
;---------------------------------------------------------------------------------------
; void intra_pred_planar(pixel* dst, intptr_t dstStride, pixel*srcPix, int, int filter)
;---------------------------------------------------------------------------------------
INIT_XMM sse2
cglobal intra_pred_planar4, 3,3,5
pxor m0, m0
movh m1, [r2 + 1]
punpcklbw m1, m0
movh m2, [r2 + 9]
punpcklbw m2, m0
pshufhw m3, m1, 0 ; topRight
pshufd m3, m3, 0xAA
pshufhw m4, m2, 0 ; bottomLeft
pshufd m4, m4, 0xAA
pmullw m3, [multi_2Row] ; (x + 1) * topRight
pmullw m0, m1, [pw_3] ; (blkSize - 1 - y) * above[x]
paddw m3, [pw_4]
paddw m3, m4
paddw m3, m0
psubw m4, m1
pshuflw m1, m2, 0
pmullw m1, [pw_planar4_0]
paddw m1, m3
paddw m3, m4
psraw m1, 3
packuswb m1, m1
movd [r0], m1
pshuflw m1, m2, 01010101b
pmullw m1, [pw_planar4_0]
paddw m1, m3
paddw m3, m4
psraw m1, 3
packuswb m1, m1
movd [r0 + r1], m1
lea r0, [r0 + 2 * r1]
pshuflw m1, m2, 10101010b
pmullw m1, [pw_planar4_0]
paddw m1, m3
paddw m3, m4
psraw m1, 3
packuswb m1, m1
movd [r0], m1
pshuflw m1, m2, 11111111b
pmullw m1, [pw_planar4_0]
paddw m1, m3
psraw m1, 3
packuswb m1, m1
movd [r0 + r1], m1
RET
;---------------------------------------------------------------------------------------
; void intra_pred_planar(pixel* dst, intptr_t dstStride, pixel*srcPix, int, int filter)
;---------------------------------------------------------------------------------------
INIT_XMM sse2
cglobal intra_pred_planar8, 3,3,6
pxor m0, m0
movh m1, [r2 + 1]
punpcklbw m1, m0
movh m2, [r2 + 17]
punpcklbw m2, m0
movd m3, [r2 + 9] ; topRight = above[8];
movd m4, [r2 + 25] ; bottomLeft = left[8];
pand m3, [pw_00ff]
pand m4, [pw_00ff]
pshuflw m3, m3, 0x00
pshuflw m4, m4, 0x00
pshufd m3, m3, 0x44
pshufd m4, m4, 0x44
pmullw m3, [multiL] ; (x + 1) * topRight
pmullw m0, m1, [pw_7] ; (blkSize - 1 - y) * above[x]
paddw m3, [pw_8]
paddw m3, m4
paddw m3, m0
psubw m4, m1
%macro INTRA_PRED_PLANAR_8 1
%if (%1 < 4)
pshuflw m5, m2, 0x55 * %1
pshufd m5, m5, 0
%else
pshufhw m5, m2, 0x55 * (%1 - 4)
pshufd m5, m5, 0xAA
%endif
pmullw m5, [pw_planar16_mul + mmsize]
paddw m5, m3
psraw m5, 4
packuswb m5, m5
movh [r0], m5
%if (%1 < 7)
paddw m3, m4
lea r0, [r0 + r1]
%endif
%endmacro
INTRA_PRED_PLANAR_8 0
INTRA_PRED_PLANAR_8 1
INTRA_PRED_PLANAR_8 2
INTRA_PRED_PLANAR_8 3
INTRA_PRED_PLANAR_8 4
INTRA_PRED_PLANAR_8 5
INTRA_PRED_PLANAR_8 6
INTRA_PRED_PLANAR_8 7
RET
;---------------------------------------------------------------------------------------
; void intra_pred_planar(pixel* dst, intptr_t dstStride, pixel*srcPix, int, int filter)
;---------------------------------------------------------------------------------------
INIT_XMM sse2
cglobal intra_pred_planar16, 3,5,8
pxor m0, m0
movh m2, [r2 + 1]
punpcklbw m2, m0
movh m7, [r2 + 9]
punpcklbw m7, m0
movd m3, [r2 + 17] ; topRight = above[16]
movd m6, [r2 + 49] ; bottomLeft = left[16]
pand m3, [pw_00ff]
pand m6, [pw_00ff]
pshuflw m3, m3, 0x00
pshuflw m6, m6, 0x00
pshufd m3, m3, 0x44 ; v_topRight
pshufd m6, m6, 0x44 ; v_bottomLeft
pmullw m4, m3, [multiH] ; (x + 1) * topRight
pmullw m3, [multiL] ; (x + 1) * topRight
pmullw m1, m2, [pw_15] ; (blkSize - 1 - y) * above[x]
pmullw m5, m7, [pw_15] ; (blkSize - 1 - y) * above[x]
paddw m4, [pw_16]
paddw m3, [pw_16]
paddw m4, m6
paddw m3, m6
paddw m4, m5
paddw m3, m1
psubw m1, m6, m7
psubw m6, m2
movh m2, [r2 + 33]
punpcklbw m2, m0
movh m7, [r2 + 41]
punpcklbw m7, m0
%macro INTRA_PRED_PLANAR_16 1
%if (%1 < 4)
pshuflw m5, m2, 0x55 * %1
pshufd m5, m5, 0
%else
%if (%1 < 8)
pshufhw m5, m2, 0x55 * (%1 - 4)
pshufd m5, m5, 0xAA
%else
%if (%1 < 12)
pshuflw m5, m7, 0x55 * (%1 - 8)
pshufd m5, m5, 0
%else
pshufhw m5, m7, 0x55 * (%1 - 12)
pshufd m5, m5, 0xAA
%endif
%endif
%endif
%if (%1 > 0)
paddw m3, m6
paddw m4, m1
lea r0, [r0 + r1]
%endif
pmullw m0, m5, [pw_planar16_mul + mmsize]
pmullw m5, [pw_planar16_mul]
paddw m0, m4
paddw m5, m3
psraw m5, 5
psraw m0, 5
packuswb m5, m0
movu [r0], m5
%endmacro
INTRA_PRED_PLANAR_16 0
INTRA_PRED_PLANAR_16 1
INTRA_PRED_PLANAR_16 2
INTRA_PRED_PLANAR_16 3
INTRA_PRED_PLANAR_16 4
INTRA_PRED_PLANAR_16 5
INTRA_PRED_PLANAR_16 6
INTRA_PRED_PLANAR_16 7
INTRA_PRED_PLANAR_16 8
INTRA_PRED_PLANAR_16 9
INTRA_PRED_PLANAR_16 10
INTRA_PRED_PLANAR_16 11
INTRA_PRED_PLANAR_16 12
INTRA_PRED_PLANAR_16 13
INTRA_PRED_PLANAR_16 14
INTRA_PRED_PLANAR_16 15
RET
;---------------------------------------------------------------------------------------
; void intra_pred_planar(pixel* dst, intptr_t dstStride, pixel*srcPix, int, int filter)
;---------------------------------------------------------------------------------------
INIT_XMM sse2
%if ARCH_X86_64 == 1
cglobal intra_pred_planar32, 3,3,16
movd m3, [r2 + 33] ; topRight = above[32]
pxor m7, m7
pand m3, [pw_00ff]
pshuflw m3, m3, 0x00
pshufd m3, m3, 0x44
pmullw m0, m3, [multiL] ; (x + 1) * topRight
pmullw m1, m3, [multiH] ; (x + 1) * topRight
pmullw m2, m3, [multiH2] ; (x + 1) * topRight
pmullw m3, [multiH3] ; (x + 1) * topRight
movd m11, [r2 + 97] ; bottomLeft = left[32]
pand m11, [pw_00ff]
pshuflw m11, m11, 0x00
pshufd m11, m11, 0x44
mova m5, m11
paddw m5, [pw_32]
paddw m0, m5
paddw m1, m5
paddw m2, m5
paddw m3, m5
mova m8, m11
mova m9, m11
mova m10, m11
mova m12, [pw_31]
movh m4, [r2 + 1]
punpcklbw m4, m7
psubw m8, m4
pmullw m4, m12
paddw m0, m4
movh m4, [r2 + 9]
punpcklbw m4, m7
psubw m9, m4
pmullw m4, m12
paddw m1, m4
movh m4, [r2 + 17]
punpcklbw m4, m7
psubw m10, m4
pmullw m4, m12
paddw m2, m4
movh m4, [r2 + 25]
punpcklbw m4, m7
psubw m11, m4
pmullw m4, m12
paddw m3, m4
mova m12, [pw_planar32_mul]
mova m13, [pw_planar32_mul + mmsize]
mova m14, [pw_planar16_mul]
mova m15, [pw_planar16_mul + mmsize]
%macro PROCESS 1
pmullw m5, %1, m12
pmullw m6, %1, m13
paddw m5, m0
paddw m6, m1
psraw m5, 6
psraw m6, 6
packuswb m5, m6
movu [r0], m5
pmullw m5, %1, m14
pmullw %1, m15
paddw m5, m2
paddw %1, m3
psraw m5, 6
psraw %1, 6
packuswb m5, %1
movu [r0 + 16], m5
%endmacro
%macro INCREMENT 0
paddw m2, m10
paddw m3, m11
paddw m0, m8
paddw m1, m9
add r0, r1
%endmacro
%assign x 0
%rep 4
pxor m7, m7
movq m4, [r2 + 65 + x * 8]
punpcklbw m4, m7
%assign y 0
%rep 8
%if y < 4
pshuflw m7, m4, 0x55 * y
pshufd m7, m7, 0x44
%else
pshufhw m7, m4, 0x55 * (y - 4)
pshufd m7, m7, 0xEE
%endif
PROCESS m7
%if x + y < 10
INCREMENT
%endif
%assign y y+1
%endrep
%assign x x+1
%endrep
RET
%else ;end ARCH_X86_64, start ARCH_X86_32
cglobal intra_pred_planar32, 3,3,8,0-(4*mmsize)
movd m3, [r2 + 33] ; topRight = above[32]
pxor m7, m7
pand m3, [pw_00ff]
pshuflw m3, m3, 0x00
pshufd m3, m3, 0x44
pmullw m0, m3, [multiL] ; (x + 1) * topRight
pmullw m1, m3, [multiH] ; (x + 1) * topRight
pmullw m2, m3, [multiH2] ; (x + 1) * topRight
pmullw m3, [multiH3] ; (x + 1) * topRight
movd m6, [r2 + 97] ; bottomLeft = left[32]
pand m6, [pw_00ff]
pshuflw m6, m6, 0x00
pshufd m6, m6, 0x44
mova m5, m6
paddw m5, [pw_32]
paddw m0, m5
paddw m1, m5
paddw m2, m5
paddw m3, m5
movh m4, [r2 + 1]
punpcklbw m4, m7
psubw m5, m6, m4
mova [rsp + 0 * mmsize], m5
pmullw m4, [pw_31]
paddw m0, m4
movh m4, [r2 + 9]
punpcklbw m4, m7
psubw m5, m6, m4
mova [rsp + 1 * mmsize], m5
pmullw m4, [pw_31]
paddw m1, m4
movh m4, [r2 + 17]
punpcklbw m4, m7
psubw m5, m6, m4
mova [rsp + 2 * mmsize], m5
pmullw m4, [pw_31]
paddw m2, m4
movh m4, [r2 + 25]
punpcklbw m4, m7
psubw m5, m6, m4
mova [rsp + 3 * mmsize], m5
pmullw m4, [pw_31]
paddw m3, m4
%macro PROCESS 1
pmullw m5, %1, [pw_planar32_mul]
pmullw m6, %1, [pw_planar32_mul + mmsize]
paddw m5, m0
paddw m6, m1
psraw m5, 6
psraw m6, 6
packuswb m5, m6
movu [r0], m5
pmullw m5, %1, [pw_planar16_mul]
pmullw %1, [pw_planar16_mul + mmsize]
paddw m5, m2
paddw %1, m3
psraw m5, 6
psraw %1, 6
packuswb m5, %1
movu [r0 + 16], m5
%endmacro
%macro INCREMENT 0
paddw m0, [rsp + 0 * mmsize]
paddw m1, [rsp + 1 * mmsize]
paddw m2, [rsp + 2 * mmsize]
paddw m3, [rsp + 3 * mmsize]
add r0, r1
%endmacro
%assign y 0
%rep 4
pxor m7, m7
movq m4, [r2 + 65 + y * 8]
punpcklbw m4, m7
%assign x 0
%rep 8
%if x < 4
pshuflw m7, m4, 0x55 * x
pshufd m7, m7, 0x44
%else
pshufhw m7, m4, 0x55 * (x - 4)
pshufd m7, m7, 0xEE
%endif
PROCESS m7
%if x + y < 10
INCREMENT
%endif
%assign x x+1
%endrep
%assign y y+1
%endrep
RET
%endif ; end ARCH_X86_32
%macro STORE_4x4 0
movd [r0], m0
psrldq m0, 4
movd [r0 + r1], m0
psrldq m0, 4
movd [r0 + r1 * 2], m0
lea r1, [r1 * 3]
psrldq m0, 4
movd [r0 + r1], m0
%endmacro
%macro TRANSPOSE_4x4 0
pshufd m0, m0, 0xD8
pshufd m1, m2, 0xD8
pshuflw m0, m0, 0xD8
pshuflw m1, m1, 0xD8
pshufhw m0, m0, 0xD8
pshufhw m1, m1, 0xD8
mova m2, m0
punpckldq m0, m1
punpckhdq m2, m1
packuswb m0, m2
%endmacro
;-----------------------------------------------------------------------------------------
; void intraPredAng4(pixel* dst, intptr_t dstStride, pixel* src, int dirMode, int bFilter)
;-----------------------------------------------------------------------------------------
INIT_XMM sse2
cglobal intra_pred_ang4_2, 3,5,1
lea r4, [r2 + 2]
add r2, 10
cmp r3m, byte 34
cmove r2, r4
movh m0, [r2]
movd [r0], m0
psrldq m0, 1
movd [r0 + r1], m0
psrldq m0, 1
movd [r0 + r1 * 2], m0
lea r1, [r1 * 3]
psrldq m0, 1
movd [r0 + r1], m0
RET
INIT_XMM sse2
cglobal intra_pred_ang4_3, 3,3,5
movh m3, [r2 + 9] ; [8 7 6 5 4 3 2 1]
punpcklbw m3, m3
psrldq m3, 1
movh m0, m3 ;[x x x x x x x x 5 4 4 3 3 2 2 1]
psrldq m3, 2
movh m1, m3 ;[x x x x x x x x 6 5 5 4 4 3 3 2]
psrldq m3, 2
movh m2, m3 ;[x x x x x x x x 7 6 6 5 5 4 4 3]
psrldq m3, 2 ;[x x x x x x x x 8 7 7 6 6 5 5 4]
pxor m4, m4
punpcklbw m1, m4
pmaddwd m1, [pw_ang_table + 20 * 16]
punpcklbw m0, m4
pmaddwd m0, [pw_ang_table + 26 * 16]
packssdw m0, m1
paddw m0, [pw_16]
psraw m0, 5
punpcklbw m3, m4
pmaddwd m3, [pw_ang_table + 8 * 16]
punpcklbw m2, m4
pmaddwd m2, [pw_ang_table + 14 * 16]
packssdw m2, m3
paddw m2, [pw_16]
psraw m2, 5
TRANSPOSE_4x4
STORE_4x4
RET
cglobal intra_pred_ang4_4, 3,3,5
movh m1, [r2 + 9] ;[8 7 6 5 4 3 2 1]
punpcklbw m1, m1
psrldq m1, 1
movh m0, m1 ;[x x x x x x x x 5 4 4 3 3 2 2 1]
psrldq m1, 2
movh m2, m1 ;[x x x x x x x x 6 5 5 4 4 3 3 2]
psrldq m1, 2 ;[x x x x x x x x 7 6 6 5 5 4 4 3]
pxor m4, m4
punpcklbw m2, m4
mova m3, m2
pmaddwd m3, [pw_ang_table + 10 * 16]
punpcklbw m0, m4
pmaddwd m0, [pw_ang_table + 21 * 16]
packssdw m0, m3
paddw m0, [pw_16]
psraw m0, 5
punpcklbw m1, m4
pmaddwd m1, [pw_ang_table + 20 * 16]
pmaddwd m2, [pw_ang_table + 31 * 16]
packssdw m2, m1
paddw m2, [pw_16]
psraw m2, 5
TRANSPOSE_4x4
STORE_4x4
RET
cglobal intra_pred_ang4_5, 3,3,5
movh m3, [r2 + 9] ;[8 7 6 5 4 3 2 1]
punpcklbw m3, m3
psrldq m3, 1
mova m0, m3 ;[x 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
psrldq m3, 2
mova m2, m3 ;[x x x x x x x x 6 5 5 4 4 3 3 2]
psrldq m3, 2 ;[x x x x x x x x 7 6 6 5 5 4 4 3]
pxor m1, m1
punpcklbw m2, m1
mova m4, m2
pmaddwd m4, [pw_ang_table + 2 * 16]
punpcklbw m0, m1
pmaddwd m0, [pw_ang_table + 17 * 16]
packssdw m0, m4
paddw m0, [pw_16]
psraw m0, 5
punpcklbw m3, m1
pmaddwd m3, [pw_ang_table + 4 * 16]
pmaddwd m2, [pw_ang_table + 19 * 16]
packssdw m2, m3
paddw m2, [pw_16]
psraw m2, 5
TRANSPOSE_4x4
STORE_4x4
RET
cglobal intra_pred_ang4_6, 3,3,4
movh m2, [r2 + 9] ;[8 7 6 5 4 3 2 1]
punpcklbw m2, m2
psrldq m2, 1
movh m0, m2 ;[x 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
psrldq m2, 2 ;[x x x 8 8 7 7 6 6 5 5 4 4 3 3 2]
pxor m1, m1
punpcklbw m0, m1
mova m3, m0
pmaddwd m3, [pw_ang_table + 26 * 16]
pmaddwd m0, [pw_ang_table + 13 * 16]
packssdw m0, m3
paddw m0, [pw_16]
psraw m0, 5
punpcklbw m2, m1
mova m3, m2
pmaddwd m3, [pw_ang_table + 20 * 16]
pmaddwd m2, [pw_ang_table + 7 * 16]
packssdw m2, m3
paddw m2, [pw_16]
psraw m2, 5
TRANSPOSE_4x4
STORE_4x4
RET
cglobal intra_pred_ang4_7, 3,3,5
movh m3, [r2 + 9] ;[8 7 6 5 4 3 2 1]
punpcklbw m3, m3
psrldq m3, 1
movh m0, m3 ;[x 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
psrldq m3, 2 ;[x x x x x x x x 6 5 5 4 4 3 3 2]
pxor m1, m1
punpcklbw m0, m1
mova m4, m0
mova m2, m0
pmaddwd m4, [pw_ang_table + 18 * 16]
pmaddwd m0, [pw_ang_table + 9 * 16]
packssdw m0, m4
paddw m0, [pw_16]
psraw m0, 5
punpcklbw m3, m1
pmaddwd m3, [pw_ang_table + 4 * 16]
pmaddwd m2, [pw_ang_table + 27 * 16]
packssdw m2, m3
paddw m2, [pw_16]
psraw m2, 5
TRANSPOSE_4x4
STORE_4x4
RET
cglobal intra_pred_ang4_8, 3,3,5
movh m0, [r2 + 9] ;[8 7 6 5 4 3 2 1]
punpcklbw m0, m0
psrldq m0, 1 ;[x 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
pxor m1, m1
punpcklbw m0, m1
mova m2, m0
mova m3, m0
mova m4, m2
pmaddwd m3, [pw_ang_table + 10 * 16]
pmaddwd m0, [pw_ang_table + 5 * 16]
packssdw m0, m3
paddw m0, [pw_16]
psraw m0, 5
pmaddwd m4, [pw_ang_table + 20 * 16]
pmaddwd m2, [pw_ang_table + 15 * 16]
packssdw m2, m4
paddw m2, [pw_16]
psraw m2, 5
TRANSPOSE_4x4
STORE_4x4
RET
cglobal intra_pred_ang4_9, 3,3,5
movh m0, [r2 + 9] ;[8 7 6 5 4 3 2 1]
punpcklbw m0, m0
psrldq m0, 1 ;[x 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
pxor m1, m1
punpcklbw m0, m1
mova m2, m0
mova m3, m0
mova m4, m2
pmaddwd m3, [pw_ang_table + 4 * 16]
pmaddwd m0, [pw_ang_table + 2 * 16]
packssdw m0, m3
paddw m0, [pw_16]
psraw m0, 5
pmaddwd m4, [pw_ang_table + 8 * 16]
pmaddwd m2, [pw_ang_table + 6 * 16]
packssdw m2, m4
paddw m2, [pw_16]
psraw m2, 5
TRANSPOSE_4x4
STORE_4x4
RET
cglobal intra_pred_ang4_10, 3,5,4
movd m0, [r2 + 9] ;[8 7 6 5 4 3 2 1]
punpcklbw m0, m0
punpcklwd m0, m0
pshufd m1, m0, 1
movhlps m2, m0
pshufd m3, m0, 3
movd [r0 + r1], m1
movd [r0 + r1 * 2], m2
lea r1, [r1 * 3]
movd [r0 + r1], m3
cmp r4m, byte 0
jz .quit
; filter
pxor m3, m3
punpcklbw m0, m3
movh m1, [r2] ;[4 3 2 1 0]
punpcklbw m1, m3
pshuflw m2, m1, 0x00
psrldq m1, 2
psubw m1, m2
psraw m1, 1
paddw m0, m1
packuswb m0, m0
.quit:
movd [r0], m0
RET
cglobal intra_pred_ang4_11, 3,3,5
movd m1, [r2 + 9] ;[4 3 2 1]
movh m0, [r2 - 7] ;[A x x x x x x x]
punpcklbw m1, m1 ;[4 4 3 3 2 2 1 1]
punpcklqdq m0, m1 ;[4 4 3 3 2 2 1 1 A x x x x x x x]]
psrldq m0, 7 ;[x x x x x x x x 4 3 3 2 2 1 1 A]
pxor m1, m1
punpcklbw m0, m1
mova m2, m0
mova m3, m0
mova m4, m2
pmaddwd m3, [pw_ang_table + 28 * 16]
pmaddwd m0, [pw_ang_table + 30 * 16]
packssdw m0, m3
paddw m0, [pw_16]
psraw m0, 5
pmaddwd m4, [pw_ang_table + 24 * 16]
pmaddwd m2, [pw_ang_table + 26 * 16]
packssdw m2, m4
paddw m2, [pw_16]
psraw m2, 5
TRANSPOSE_4x4
STORE_4x4
RET
cglobal intra_pred_ang4_12, 3,3,5
movd m1, [r2 + 9] ;[4 3 2 1]
movh m0, [r2 - 7] ;[A x x x x x x x]
punpcklbw m1, m1 ;[4 4 3 3 2 2 1 1]
punpcklqdq m0, m1 ;[4 4 3 3 2 2 1 1 A x x x x x x x]
psrldq m0, 7 ;[x x x x x x x x 4 3 3 2 2 1 1 A]
pxor m1, m1
punpcklbw m0, m1
mova m2, m0
mova m3, m0
mova m4, m2
pmaddwd m3, [pw_ang_table + 22 * 16]
pmaddwd m0, [pw_ang_table + 27 * 16]
packssdw m0, m3
paddw m0, [pw_16]
psraw m0, 5
pmaddwd m4, [pw_ang_table + 12 * 16]
pmaddwd m2, [pw_ang_table + 17 * 16]
packssdw m2, m4
paddw m2, [pw_16]
psraw m2, 5
TRANSPOSE_4x4
STORE_4x4
RET
cglobal intra_pred_ang4_24, 3,3,5
movd m1, [r2 + 1] ;[4 3 2 1]
movh m0, [r2 - 7] ;[A x x x x x x x]
punpcklbw m1, m1 ;[4 4 3 3 2 2 1 1]
punpcklqdq m0, m1 ;[4 4 3 3 2 2 1 1 A x x x x x x x]
psrldq m0, 7 ;[x x x x x x x x 4 3 3 2 2 1 1 A]
pxor m1, m1
punpcklbw m0, m1
mova m2, m0
mova m3, m0
mova m4, m2
pmaddwd m3, [pw_ang_table + 22 * 16]
pmaddwd m0, [pw_ang_table + 27 * 16]
packssdw m0, m3
paddw m0, [pw_16]
psraw m0, 5
pmaddwd m4, [pw_ang_table + 12 * 16]
pmaddwd m2, [pw_ang_table + 17 * 16]
packssdw m2, m4
paddw m2, [pw_16]
psraw m2, 5
packuswb m0, m2
STORE_4x4
RET
cglobal intra_pred_ang4_13, 3,3,5
movd m1, [r2 - 1] ;[x x A x]
movd m2, [r2 + 9] ;[4 3 2 1]
movd m0, [r2 + 3] ;[x x B x]
punpcklbw m0, m1 ;[x x x x A B x x]
punpckldq m0, m2 ;[4 3 2 1 A B x x]
psrldq m0, 2 ;[x x 4 3 2 1 A B]
punpcklbw m0, m0
psrldq m0, 1
movh m3, m0 ;[x x x x x 4 4 3 3 2 2 1 1 A A B]
psrldq m0, 2 ;[x x x x x x x 4 4 3 3 2 2 1 1 A]
pxor m1, m1
punpcklbw m0, m1
mova m4, m0
mova m2, m0
pmaddwd m4, [pw_ang_table + 14 * 16]
pmaddwd m0, [pw_ang_table + 23 * 16]
packssdw m0, m4
paddw m0, [pw_16]
psraw m0, 5
punpcklbw m3, m1
pmaddwd m3, [pw_ang_table + 28 * 16]
pmaddwd m2, [pw_ang_table + 5 * 16]
packssdw m2, m3
paddw m2, [pw_16]
psraw m2, 5
TRANSPOSE_4x4
STORE_4x4
RET
cglobal intra_pred_ang4_14, 3,3,4
movd m1, [r2 - 1] ;[x x A x]
movd m0, [r2 + 1] ;[x x B x]
punpcklbw m0, m1 ;[A B x x]
movd m1, [r2 + 9] ;[4 3 2 1]
punpckldq m0, m1 ;[4 3 2 1 A B x x]
psrldq m0, 2 ;[x x 4 3 2 1 A B]
punpcklbw m0, m0 ;[x x x x 4 4 3 3 2 2 1 1 A A B B]
psrldq m0, 1
movh m2, m0 ;[x x x x x 4 4 3 3 2 2 1 1 A A B]
psrldq m0, 2 ;[x x x x x x x 4 4 3 3 2 2 1 1 A]
pxor m1, m1
punpcklbw m0, m1
mova m3, m0
pmaddwd m3, [pw_ang_table + 6 * 16]
pmaddwd m0, [pw_ang_table + 19 * 16]
packssdw m0, m3
paddw m0, [pw_16]
psraw m0, 5
punpcklbw m2, m1
mova m3, m2
pmaddwd m3, [pw_ang_table + 12 * 16]
pmaddwd m2, [pw_ang_table + 25 * 16]
packssdw m2, m3
paddw m2, [pw_16]
psraw m2, 5
TRANSPOSE_4x4
STORE_4x4
RET
cglobal intra_pred_ang4_15, 3,3,5
movd m0, [r2] ;[x x x A]
movd m1, [r2 + 2] ;[x x x B]
punpcklbw m1, m0 ;[x x A B]
movd m0, [r2 + 3] ;[x x C x]
punpcklwd m0, m1 ;[A B C x]
movd m1, [r2 + 9] ;[4 3 2 1]
punpckldq m0, m1 ;[4 3 2 1 A B C x]
psrldq m0, 1 ;[x 4 3 2 1 A B C]
punpcklbw m0, m0 ;[x x 4 4 3 3 2 2 1 1 A A B B C C]
psrldq m0, 1
movh m1, m0 ;[x x x 4 4 3 3 2 2 1 1 A A B B C]
psrldq m0, 2
movh m2, m0 ;[x x x x x 4 4 3 3 2 2 1 1 A A B]
psrldq m0, 2 ;[x x x x x x x 4 4 3 3 2 2 1 1 A]
pxor m4, m4
punpcklbw m2, m4
mova m3, m2
pmaddwd m3, [pw_ang_table + 30 * 16]
punpcklbw m0, m4
pmaddwd m0, [pw_ang_table + 15 * 16]
packssdw m0, m3
paddw m0, [pw_16]
psraw m0, 5
punpcklbw m1, m4
pmaddwd m1, [pw_ang_table + 28 * 16]
pmaddwd m2, [pw_ang_table + 13 * 16]
packssdw m2, m1
paddw m2, [pw_16]
psraw m2, 5
TRANSPOSE_4x4
STORE_4x4
RET
cglobal intra_pred_ang4_16, 3,3,5
movd m2, [r2] ;[x x x A]
movd m1, [r2 + 2] ;[x x x B]
punpcklbw m1, m2 ;[x x A B]
movd m0, [r2 + 2] ;[x x C x]
punpcklwd m0, m1 ;[A B C x]
movd m1, [r2 + 9] ;[4 3 2 1]
punpckldq m0, m1 ;[4 3 2 1 A B C x]
psrldq m0, 1 ;[x 4 3 2 1 A B C]
punpcklbw m0, m0 ;[x x 4 4 3 3 2 2 1 1 A A B B C C]
psrldq m0, 1
movh m1, m0 ;[x x x 4 4 3 3 2 2 1 1 A A B B C]
psrldq m0, 2
movh m2, m0 ;[x x x x x 4 4 3 3 2 2 1 1 A A B]
psrldq m0, 2 ;[x x x x x x x 4 4 3 3 2 2 1 1 A]
pxor m4, m4
punpcklbw m2, m4
mova m3, m2
pmaddwd m3, [pw_ang_table + 22 * 16]
punpcklbw m0, m4
pmaddwd m0, [pw_ang_table + 11 * 16]
packssdw m0, m3
paddw m0, [pw_16]
psraw m0, 5
punpcklbw m1, m4
pmaddwd m1, [pw_ang_table + 12 * 16]
pmaddwd m2, [pw_ang_table + 1 * 16]
packssdw m2, m1
paddw m2, [pw_16]
psraw m2, 5
TRANSPOSE_4x4
STORE_4x4
RET
cglobal intra_pred_ang4_17, 3,3,5
movd m2, [r2] ;[x x x A]
movd m3, [r2 + 1] ;[x x x B]
movd m4, [r2 + 2] ;[x x x C]
movd m0, [r2 + 4] ;[x x x D]
punpcklbw m3, m2 ;[x x A B]
punpcklbw m0, m4 ;[x x C D]
punpcklwd m0, m3 ;[A B C D]
movd m1, [r2 + 9] ;[4 3 2 1]
punpckldq m0, m1 ;[4 3 2 1 A B C D]
punpcklbw m0, m0 ;[4 4 3 3 2 2 1 1 A A B B C C D D]
psrldq m0, 1
movh m1, m0 ;[x 4 4 3 3 2 2 1 1 A A B B C C D]
psrldq m0, 2
movh m2, m0 ;[x x x 4 4 3 3 2 2 1 1 A A B B C]
psrldq m0, 2
movh m3, m0 ;[x x x x x 4 4 3 3 2 2 1 1 A A B]
psrldq m0, 2 ;[x x x x x x x 4 4 3 3 2 2 1 1 A]
pxor m4, m4
punpcklbw m3, m4
pmaddwd m3, [pw_ang_table + 12 * 16]
punpcklbw m0, m4
pmaddwd m0, [pw_ang_table + 6 * 16]
packssdw m0, m3
paddw m0, [pw_16]
psraw m0, 5
punpcklbw m1, m4
pmaddwd m1, [pw_ang_table + 24 * 16]
punpcklbw m2, m4
pmaddwd m2, [pw_ang_table + 18 * 16]
packssdw m2, m1
paddw m2, [pw_16]
psraw m2, 5
TRANSPOSE_4x4
STORE_4x4
RET
cglobal intra_pred_ang4_18, 3,4,2
mov r3d, [r2 + 8]
mov r3b, byte [r2]
bswap r3d
movd m0, r3d
movd m1, [r2 + 1]
punpckldq m0, m1
lea r3, [r1 * 3]
movd [r0 + r3], m0
psrldq m0, 1
movd [r0 + r1 * 2], m0
psrldq m0, 1
movd [r0 + r1], m0
psrldq m0, 1
movd [r0], m0
RET
cglobal intra_pred_ang4_19, 3,3,5
movd m2, [r2] ;[x x x A]
movd m3, [r2 + 9] ;[x x x B]
movd m4, [r2 + 10] ;[x x x C]
movd m0, [r2 + 12] ;[x x x D]
punpcklbw m3, m2 ;[x x A B]
punpcklbw m0, m4 ;[x x C D]
punpcklwd m0, m3 ;[A B C D]
movd m1, [r2 + 1] ;[4 3 2 1]
punpckldq m0, m1 ;[4 3 2 1 A B C D]
punpcklbw m0, m0 ;[4 4 3 3 2 2 1 1 A A B B C C D D]
psrldq m0, 1
movh m1, m0 ;[x 4 4 3 3 2 2 1 1 A A B B C C D]
psrldq m0, 2
movh m2, m0 ;[x x x 4 4 3 3 2 2 1 1 A A B B C]
psrldq m0, 2
movh m3, m0 ;[x x x x x 4 4 3 3 2 2 1 1 A A B]
psrldq m0, 2 ;[x x x x x x x 4 4 3 3 2 2 1 1 A]
pxor m4, m4
punpcklbw m3, m4
pmaddwd m3, [pw_ang_table + 12 * 16]
punpcklbw m0, m4
pmaddwd m0, [pw_ang_table + 6 * 16]
packssdw m0, m3
paddw m0, [pw_16]
psraw m0, 5
punpcklbw m1, m4
pmaddwd m1, [pw_ang_table + 24 * 16]
punpcklbw m2, m4
pmaddwd m2, [pw_ang_table + 18 * 16]
packssdw m2, m1
paddw m2, [pw_16]
psraw m2, 5
packuswb m0, m2
STORE_4x4
RET
cglobal intra_pred_ang4_20, 3,3,5
movd m2, [r2] ;[x x x A]
movd m1, [r2 + 10] ;[x x x B]
punpcklbw m1, m2 ;[x x A B]
movd m0, [r2 + 10] ;[x x C x]
punpcklwd m0, m1 ;[A B C x]
movd m1, [r2 + 1] ;[4 3 2 1]
punpckldq m0, m1 ;[4 3 2 1 A B C x]
psrldq m0, 1 ;[x 4 3 2 1 A B C]
punpcklbw m0, m0 ;[x x 4 4 3 3 2 2 1 1 A A B B C C]
psrldq m0, 1
movh m1, m0 ;[x x x 4 4 3 3 2 2 1 1 A A B B C]
psrldq m0, 2
movh m2, m0 ;[x x x x x 4 4 3 3 2 2 1 1 A A B]
psrldq m0, 2 ;[x x x x x x x 4 4 3 3 2 2 1 1 A]
pxor m4, m4
punpcklbw m2, m4
mova m3, m2
pmaddwd m3, [pw_ang_table + 22 * 16]
punpcklbw m0, m4
pmaddwd m0, [pw_ang_table + 11 * 16]
packssdw m0, m3
paddw m0, [pw_16]
psraw m0, 5
punpcklbw m1, m4
pmaddwd m1, [pw_ang_table + 12 * 16]
pmaddwd m2, [pw_ang_table + 1 * 16]
packssdw m2, m1
paddw m2, [pw_16]
psraw m2, 5
packuswb m0, m2
STORE_4x4
RET
cglobal intra_pred_ang4_21, 3,3,5
movd m0, [r2] ;[x x x A]
movd m1, [r2 + 10] ;[x x x B]
punpcklbw m1, m0 ;[x x A B]
movd m0, [r2 + 11] ;[x x C x]
punpcklwd m0, m1 ;[A B C x]
movd m1, [r2 + 1] ;[4 3 2 1]
punpckldq m0, m1 ;[4 3 2 1 A B C x]
psrldq m0, 1 ;[x 4 3 2 1 A B C]
punpcklbw m0, m0 ;[x x 4 4 3 3 2 2 1 1 A A B B C C]
psrldq m0, 1
movh m1, m0 ;[x x x 4 4 3 3 2 2 1 1 A A B B C]
psrldq m0, 2
movh m2, m0 ;[x x x x x 4 4 3 3 2 2 1 1 A A B]
psrldq m0, 2 ;[x x x x x x x 4 4 3 3 2 2 1 1 A]
pxor m4, m4
punpcklbw m2, m4
mova m3, m2
pmaddwd m3, [pw_ang_table + 30 * 16]
punpcklbw m0, m4
pmaddwd m0, [pw_ang_table + 15 * 16]
packssdw m0, m3
paddw m0, [pw_16]
psraw m0, 5
punpcklbw m1, m4
pmaddwd m1, [pw_ang_table + 28 * 16]
pmaddwd m2, [pw_ang_table + 13 * 16]
packssdw m2, m1
paddw m2, [pw_16]
psraw m2, 5
packuswb m0, m2
STORE_4x4
RET
cglobal intra_pred_ang4_22, 3,3,4
movd m1, [r2 - 1] ;[x x A x]
movd m0, [r2 + 9] ;[x x B x]
punpcklbw m0, m1 ;[A B x x]
movd m1, [r2 + 1] ;[4 3 2 1]
punpckldq m0, m1 ;[4 3 2 1 A B x x]
psrldq m0, 2 ;[x x 4 3 2 1 A B]
punpcklbw m0, m0 ;[x x x x 4 4 3 3 2 2 1 1 A A B B]
psrldq m0, 1
movh m2, m0 ;[x x x x x 4 4 3 3 2 2 1 1 A A B]
psrldq m0, 2 ;[x x x x x x x 4 4 3 3 2 2 1 1 A]
pxor m1, m1
punpcklbw m0, m1
mova m3, m0
pmaddwd m3, [pw_ang_table + 6 * 16]
pmaddwd m0, [pw_ang_table + 19 * 16]
packssdw m0, m3
paddw m0, [pw_16]
psraw m0, 5
punpcklbw m2, m1
mova m3, m2
pmaddwd m3, [pw_ang_table + 12 * 16]
pmaddwd m2, [pw_ang_table + 25 * 16]
packssdw m2, m3
paddw m2, [pw_16]
psraw m2, 5
packuswb m0, m2
STORE_4x4
RET
cglobal intra_pred_ang4_23, 3,3,5
movd m1, [r2 - 1] ;[x x A x]
movd m2, [r2 + 1] ;[4 3 2 1]
movd m0, [r2 + 11] ;[x x B x]
punpcklbw m0, m1 ;[x x x x A B x x]
punpckldq m0, m2 ;[4 3 2 1 A B x x]
psrldq m0, 2 ;[x x 4 3 2 1 A B]
punpcklbw m0, m0
psrldq m0, 1
mova m3, m0 ;[x x x x x 4 4 3 3 2 2 1 1 A A B]
psrldq m0, 2 ;[x x x x x x x 4 4 3 3 2 2 1 1 A]
pxor m1, m1
punpcklbw m0, m1
mova m4, m0
mova m2, m0
pmaddwd m4, [pw_ang_table + 14 * 16]
pmaddwd m0, [pw_ang_table + 23 * 16]
packssdw m0, m4
paddw m0, [pw_16]
psraw m0, 5
punpcklbw m3, m1
pmaddwd m3, [pw_ang_table + 28 * 16]
pmaddwd m2, [pw_ang_table + 5 * 16]
packssdw m2, m3
paddw m2, [pw_16]
psraw m2, 5
packuswb m0, m2
STORE_4x4
RET
cglobal intra_pred_ang4_25, 3,3,5
movd m1, [r2 + 1] ;[4 3 2 1]
movh m0, [r2 - 7] ;[A x x x x x x x]
punpcklbw m1, m1 ;[4 4 3 3 2 2 1 1]
punpcklqdq m0, m1 ;[4 4 3 3 2 2 1 1 A x x x x x x x]
psrldq m0, 7 ;[x x x x x x x x 4 3 3 2 2 1 1 A]
pxor m1, m1
punpcklbw m0, m1
mova m2, m0
mova m3, m0
mova m4, m2
pmaddwd m3, [pw_ang_table + 28 * 16]
pmaddwd m0, [pw_ang_table + 30 * 16]
packssdw m0, m3
paddw m0, [pw_16]
psraw m0, 5
pmaddwd m4, [pw_ang_table + 24 * 16]
pmaddwd m2, [pw_ang_table + 26 * 16]
packssdw m2, m4
paddw m2, [pw_16]
psraw m2, 5
packuswb m0, m2
STORE_4x4
RET
cglobal intra_pred_ang4_26, 3,4,4
movd m0, [r2 + 1] ;[8 7 6 5 4 3 2 1]
; store
movd [r0], m0
movd [r0 + r1], m0
movd [r0 + r1 * 2], m0
lea r3, [r1 * 3]
movd [r0 + r3], m0
; filter
cmp r4m, byte 0
jz .quit
pxor m3, m3
punpcklbw m0, m3
pshuflw m0, m0, 0x00
movd m2, [r2]
punpcklbw m2, m3
pshuflw m2, m2, 0x00
movd m1, [r2 + 9]
punpcklbw m1, m3
psubw m1, m2
psraw m1, 1
paddw m0, m1
packuswb m0, m0
movd r2d, m0
mov [r0], r2b
shr r2, 8
mov [r0 + r1], r2b
shr r2, 8
mov [r0 + r1 * 2], r2b
shr r2, 8
mov [r0 + r3], r2b
.quit:
RET
cglobal intra_pred_ang4_27, 3,3,5
movh m0, [r2 + 1] ;[8 7 6 5 4 3 2 1]
punpcklbw m0, m0
psrldq m0, 1 ;[x 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
pxor m1, m1
punpcklbw m0, m1
mova m2, m0
mova m3, m0
mova m4, m2
pmaddwd m3, [pw_ang_table + 4 * 16]
pmaddwd m0, [pw_ang_table + 2 * 16]
packssdw m0, m3
paddw m0, [pw_16]
psraw m0, 5
pmaddwd m4, [pw_ang_table + 8 * 16]
pmaddwd m2, [pw_ang_table + 6 * 16]
packssdw m2, m4
paddw m2, [pw_16]
psraw m2, 5
packuswb m0, m2
STORE_4x4
RET
cglobal intra_pred_ang4_28, 3,3,5
movh m0, [r2 + 1] ;[8 7 6 5 4 3 2 1]
punpcklbw m0, m0
psrldq m0, 1 ;[x 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
pxor m1, m1
punpcklbw m0, m1
mova m2, m0
mova m3, m0
mova m4, m2
pmaddwd m3, [pw_ang_table + 10 * 16]
pmaddwd m0, [pw_ang_table + 5 * 16]
packssdw m0, m3
paddw m0, [pw_16]
psraw m0, 5
pmaddwd m4, [pw_ang_table + 20 * 16]
pmaddwd m2, [pw_ang_table + 15 * 16]
packssdw m2, m4
paddw m2, [pw_16]
psraw m2, 5
packuswb m0, m2
STORE_4x4
RET
cglobal intra_pred_ang4_29, 3,3,5
movh m3, [r2 + 1] ;[8 7 6 5 4 3 2 1]
punpcklbw m3, m3
psrldq m3, 1
movh m0, m3 ;[x 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
psrldq m3, 2 ;[x x x x x x x x 6 5 5 4 4 3 3 2]
pxor m1, m1
punpcklbw m0, m1
mova m4, m0
mova m2, m0
pmaddwd m4, [pw_ang_table + 18 * 16]
pmaddwd m0, [pw_ang_table + 9 * 16]
packssdw m0, m4
paddw m0, [pw_16]
psraw m0, 5
punpcklbw m3, m1
pmaddwd m3, [pw_ang_table + 4 * 16]
pmaddwd m2, [pw_ang_table + 27 * 16]
packssdw m2, m3
paddw m2, [pw_16]
psraw m2, 5
packuswb m0, m2
STORE_4x4
RET
cglobal intra_pred_ang4_30, 3,3,4
movh m2, [r2 + 1] ;[8 7 6 5 4 3 2 1]
punpcklbw m2, m2
psrldq m2, 1
movh m0, m2 ;[x 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
psrldq m2, 2 ;[x x x 8 8 7 7 6 6 5 5 4 4 3 3 2]
pxor m1, m1
punpcklbw m0, m1
mova m3, m0
pmaddwd m3, [pw_ang_table + 26 * 16]
pmaddwd m0, [pw_ang_table + 13 * 16]
packssdw m0, m3
paddw m0, [pw_16]
psraw m0, 5
punpcklbw m2, m1
mova m3, m2
pmaddwd m3, [pw_ang_table + 20 * 16]
pmaddwd m2, [pw_ang_table + 7 * 16]
packssdw m2, m3
paddw m2, [pw_16]
psraw m2, 5
packuswb m0, m2
STORE_4x4
RET
cglobal intra_pred_ang4_31, 3,3,5
movh m3, [r2 + 1] ;[8 7 6 5 4 3 2 1]
punpcklbw m3, m3
psrldq m3, 1
mova m0, m3 ;[x 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
psrldq m3, 2
mova m2, m3 ;[x x x x x x x x 6 5 5 4 4 3 3 2]
psrldq m3, 2 ;[x x x x x x x x 7 6 6 5 5 4 4 3]
pxor m1, m1
punpcklbw m2, m1
mova m4, m2
pmaddwd m4, [pw_ang_table + 2 * 16]
punpcklbw m0, m1
pmaddwd m0, [pw_ang_table + 17 * 16]
packssdw m0, m4
paddw m0, [pw_16]
psraw m0, 5
punpcklbw m3, m1
pmaddwd m3, [pw_ang_table + 4 * 16]
pmaddwd m2, [pw_ang_table + 19 * 16]
packssdw m2, m3
paddw m2, [pw_16]
psraw m2, 5
packuswb m0, m2
STORE_4x4
RET
cglobal intra_pred_ang4_32, 3,3,5
movh m1, [r2 + 1] ;[8 7 6 5 4 3 2 1]
punpcklbw m1, m1
psrldq m1, 1
movh m0, m1 ;[x x x x x x x x 5 4 4 3 3 2 2 1]
psrldq m1, 2
movh m2, m1 ;[x x x x x x x x 6 5 5 4 4 3 3 2]
psrldq m1, 2 ;[x x x x x x x x 7 6 6 5 5 4 4 3]
pxor m4, m4
punpcklbw m2, m4
mova m3, m2
pmaddwd m3, [pw_ang_table + 10 * 16]
punpcklbw m0, m4
pmaddwd m0, [pw_ang_table + 21 * 16]
packssdw m0, m3
paddw m0, [pw_16]
psraw m0, 5
punpcklbw m1, m4
pmaddwd m1, [pw_ang_table + 20 * 16]
pmaddwd m2, [pw_ang_table + 31 * 16]
packssdw m2, m1
paddw m2, [pw_16]
psraw m2, 5
packuswb m0, m2
STORE_4x4
RET
cglobal intra_pred_ang4_33, 3,3,5
movh m3, [r2 + 1] ; [8 7 6 5 4 3 2 1]
punpcklbw m3, m3
psrldq m3, 1
movh m0, m3 ;[x x x x x x x x 5 4 4 3 3 2 2 1]
psrldq m3, 2
movh m1, m3 ;[x x x x x x x x 6 5 5 4 4 3 3 2]
psrldq m3, 2
movh m2, m3 ;[x x x x x x x x 7 6 6 5 5 4 4 3]
psrldq m3, 2 ;[x x x x x x x x 8 7 7 6 6 5 5 4]
pxor m4, m4
punpcklbw m1, m4
pmaddwd m1, [pw_ang_table + 20 * 16]
punpcklbw m0, m4
pmaddwd m0, [pw_ang_table + 26 * 16]
packssdw m0, m1
paddw m0, [pw_16]
psraw m0, 5
punpcklbw m3, m4
pmaddwd m3, [pw_ang_table + 8 * 16]
punpcklbw m2, m4
pmaddwd m2, [pw_ang_table + 14 * 16]
packssdw m2, m3
paddw m2, [pw_16]
psraw m2, 5
packuswb m0, m2
STORE_4x4
RET
;---------------------------------------------------------------------------------------------
; void intra_pred_dc(pixel* dst, intptr_t dstStride, pixel *srcPix, int dirMode, int bFilter)
;---------------------------------------------------------------------------------------------
INIT_XMM sse4
cglobal intra_pred_dc4, 5,5,3
inc r2
pxor m0, m0
movd m1, [r2]
movd m2, [r2 + 8]
punpckldq m1, m2
psadbw m1, m0 ; m1 = sum
test r4d, r4d
pmulhrsw m1, [pw_4096] ; m1 = (sum + 4) / 8
movd r4d, m1 ; r4d = dc_val
pshufb m1, m0 ; m1 = byte [dc_val ...]
; store DC 4x4
lea r3, [r1 * 3]
movd [r0], m1
movd [r0 + r1], m1
movd [r0 + r1 * 2], m1
movd [r0 + r3], m1
; do DC filter
jz .end
lea r3d, [r4d * 2 + 2] ; r3d = DC * 2 + 2
add r4d, r3d ; r4d = DC * 3 + 2
movd m1, r4d
pshuflw m1, m1, 0 ; m1 = pixDCx3
pshufd m1, m1, 0
; filter top
movd m2, [r2]
movd m0, [r2 + 9]
punpckldq m2, m0
pmovzxbw m2, m2
paddw m2, m1
psraw m2, 2
packuswb m2, m2
movd [r0], m2 ; overwrite top-left pixel, we will update it later
; filter top-left
movzx r4d, byte [r2 + 8]
add r3d, r4d
movzx r4d, byte [r2]
add r3d, r4d
shr r3d, 2
mov [r0], r3b
; filter left
add r0, r1
pextrb [r0], m2, 4
pextrb [r0 + r1], m2, 5
pextrb [r0 + r1 * 2], m2, 6
.end:
RET
;---------------------------------------------------------------------------------------------
; void intra_pred_dc(pixel* dst, intptr_t dstStride, pixel *srcPix, int dirMode, int bFilter)
;---------------------------------------------------------------------------------------------
INIT_XMM sse4
cglobal intra_pred_dc8, 5, 7, 3
lea r3, [r2 + 17]
inc r2
pxor m0, m0
movh m1, [r2]
movh m2, [r3]
punpcklqdq m1, m2
psadbw m1, m0
pshufd m2, m1, 2
paddw m1, m2
movd r5d, m1
add r5d, 8
shr r5d, 4 ; sum = sum / 16
movd m1, r5d
pshufb m1, m0 ; m1 = byte [dc_val ...]
test r4d, r4d
; store DC 8x8
mov r6, r0
movh [r0], m1
movh [r0 + r1], m1
lea r0, [r0 + r1 * 2]
movh [r0], m1
movh [r0 + r1], m1
lea r0, [r0 + r1 * 2]
movh [r0], m1
movh [r0 + r1], m1
lea r0, [r0 + r1 * 2]
movh [r0], m1
movh [r0 + r1], m1
; Do DC Filter
jz .end
lea r4d, [r5d * 2 + 2] ; r4d = DC * 2 + 2
add r5d, r4d ; r5d = DC * 3 + 2
movd m1, r5d
pshuflw m1, m1, 0 ; m1 = pixDCx3
pshufd m1, m1, 0
; filter top
pmovzxbw m2, [r2]
paddw m2, m1
psraw m2, 2
packuswb m2, m2
movh [r6], m2
; filter top-left
movzx r5d, byte [r3]
add r4d, r5d
movzx r3d, byte [r2]
add r3d, r4d
shr r3d, 2
mov [r6], r3b
; filter left
add r6, r1
pmovzxbw m2, [r2 + 17]
paddw m2, m1
psraw m2, 2
packuswb m2, m2
pextrb [r6], m2, 0
pextrb [r6 + r1], m2, 1
pextrb [r6 + 2 * r1], m2, 2
lea r6, [r6 + r1 * 2]
pextrb [r6 + r1], m2, 3
pextrb [r6 + r1 * 2], m2, 4
pextrb [r6 + r1 * 4], m2, 6
lea r1, [r1 * 3]
pextrb [r6 + r1], m2, 5
.end:
RET
;--------------------------------------------------------------------------------------------
; void intra_pred_dc(pixel* dst, intptr_t dstStride, pixel *srcPix, int dirMode, int bFilter)
;--------------------------------------------------------------------------------------------
INIT_XMM sse4
cglobal intra_pred_dc16, 5, 7, 4
lea r3, [r2 + 33]
inc r2
pxor m0, m0
movu m1, [r2]
movu m2, [r3]
psadbw m1, m0
psadbw m2, m0
paddw m1, m2
pshufd m2, m1, 2
paddw m1, m2
movd r5d, m1
add r5d, 16
shr r5d, 5 ; sum = sum / 32
movd m1, r5d
pshufb m1, m0 ; m1 = byte [dc_val ...]
test r4d, r4d
; store DC 16x16
mov r6, r0
movu [r0], m1
movu [r0 + r1], m1
lea r0, [r0 + r1 * 2]
movu [r0], m1
movu [r0 + r1], m1
lea r0, [r0 + r1 * 2]
movu [r0], m1
movu [r0 + r1], m1
lea r0, [r0 + r1 * 2]
movu [r0], m1
movu [r0 + r1], m1
lea r0, [r0 + r1 * 2]
movu [r0], m1
movu [r0 + r1], m1
lea r0, [r0 + r1 * 2]
movu [r0], m1
movu [r0 + r1], m1
lea r0, [r0 + r1 * 2]
movu [r0], m1
movu [r0 + r1], m1
lea r0, [r0 + r1 * 2]
movu [r0], m1
movu [r0 + r1], m1
; Do DC Filter
jz .end
lea r4d, [r5d * 2 + 2] ; r4d = DC * 2 + 2
add r5d, r4d ; r5d = DC * 3 + 2
movd m1, r5d
pshuflw m1, m1, 0 ; m1 = pixDCx3
pshufd m1, m1, 0
; filter top
pmovzxbw m2, [r2]
paddw m2, m1
psraw m2, 2
packuswb m2, m2
movh [r6], m2
pmovzxbw m3, [r2 + 8]
paddw m3, m1
psraw m3, 2
packuswb m3, m3
movh [r6 + 8], m3
; filter top-left
movzx r5d, byte [r3]
add r4d, r5d
movzx r3d, byte [r2]
add r3d, r4d
shr r3d, 2
mov [r6], r3b
; filter left
add r6, r1
pmovzxbw m2, [r2 + 33]
paddw m2, m1
psraw m2, 2
packuswb m2, m2
pextrb [r6], m2, 0
pextrb [r6 + r1], m2, 1
pextrb [r6 + r1 * 2], m2, 2
lea r6, [r6 + r1 * 2]
pextrb [r6 + r1], m2, 3
pextrb [r6 + r1 * 2], m2, 4
lea r6, [r6 + r1 * 2]
pextrb [r6 + r1], m2, 5
pextrb [r6 + r1 * 2], m2, 6
lea r6, [r6 + r1 * 2]
pextrb [r6 + r1], m2, 7
pmovzxbw m3, [r2 + 41]
paddw m3, m1
psraw m3, 2
packuswb m3, m3
pextrb [r6 + r1 * 2], m3, 0
lea r6, [r6 + r1 * 2]
pextrb [r6 + r1], m3, 1
pextrb [r6 + r1 * 2], m3, 2
lea r6, [r6 + r1 * 2]
pextrb [r6 + r1], m3, 3
pextrb [r6 + r1 * 2], m3, 4
lea r6, [r6 + r1 * 2]
pextrb [r6 + r1], m3, 5
pextrb [r6 + r1 * 2], m3, 6
.end:
RET
;---------------------------------------------------------------------------------------------
; void intra_pred_dc(pixel* dst, intptr_t dstStride, pixel *srcPix, int dirMode, int bFilter)
;---------------------------------------------------------------------------------------------
INIT_XMM sse4
cglobal intra_pred_dc32, 3, 5, 5
lea r3, [r2 + 65]
inc r2
pxor m0, m0
movu m1, [r2]
movu m2, [r2 + 16]
movu m3, [r3]
movu m4, [r3 + 16]
psadbw m1, m0
psadbw m2, m0
psadbw m3, m0
psadbw m4, m0
paddw m1, m2
paddw m3, m4
paddw m1, m3
pshufd m2, m1, 2
paddw m1, m2
movd r4d, m1
add r4d, 32
shr r4d, 6 ; sum = sum / 64
movd m1, r4d
pshufb m1, m0 ; m1 = byte [dc_val ...]
%rep 2
; store DC 16x16
movu [r0], m1
movu [r0 + r1], m1
movu [r0 + 16], m1
movu [r0 + r1 + 16],m1
lea r0, [r0 + 2 * r1]
movu [r0], m1
movu [r0 + r1], m1
movu [r0 + 16], m1
movu [r0 + r1 + 16],m1
lea r0, [r0 + 2 * r1]
movu [r0], m1
movu [r0 + r1], m1
movu [r0 + 16], m1
movu [r0 + r1 + 16],m1
lea r0, [r0 + 2 * r1]
movu [r0], m1
movu [r0 + r1], m1
movu [r0 + 16], m1
movu [r0 + r1 + 16],m1
lea r0, [r0 + 2 * r1]
movu [r0], m1
movu [r0 + r1], m1
movu [r0 + 16], m1
movu [r0 + r1 + 16],m1
lea r0, [r0 + 2 * r1]
movu [r0], m1
movu [r0 + r1], m1
movu [r0 + 16], m1
movu [r0 + r1 + 16],m1
lea r0, [r0 + 2 * r1]
movu [r0], m1
movu [r0 + r1], m1
movu [r0 + 16], m1
movu [r0 + r1 + 16],m1
lea r0, [r0 + 2 * r1]
movu [r0], m1
movu [r0 + r1], m1
movu [r0 + 16], m1
movu [r0 + r1 + 16],m1
lea r0, [r0 + 2 * r1]
%endrep
RET
;---------------------------------------------------------------------------------------------
; void intra_pred_dc(pixel* dst, intptr_t dstStride, pixel *srcPix, int dirMode, int bFilter)
;---------------------------------------------------------------------------------------------
%if ARCH_X86_64 == 1
INIT_YMM avx2
cglobal intra_pred_dc32, 3, 4, 3
lea r3, [r1 * 3]
pxor m0, m0
movu m1, [r2 + 1]
movu m2, [r2 + 65]
psadbw m1, m0
psadbw m2, m0
paddw m1, m2
vextracti128 xm2, m1, 1
paddw m1, m2
pshufd m2, m1, 2
paddw m1, m2
pmulhrsw m1, [pw_512] ; sum = (sum + 32) / 64
vpbroadcastb m1, xm1 ; m1 = byte [dc_val ...]
movu [r0 + r1 * 0], m1
movu [r0 + r1 * 1], m1
movu [r0 + r1 * 2], m1
movu [r0 + r3 * 1], m1
lea r0, [r0 + 4 * r1]
movu [r0 + r1 * 0], m1
movu [r0 + r1 * 1], m1
movu [r0 + r1 * 2], m1
movu [r0 + r3 * 1], m1
lea r0, [r0 + 4 * r1]
movu [r0 + r1 * 0], m1
movu [r0 + r1 * 1], m1
movu [r0 + r1 * 2], m1
movu [r0 + r3 * 1], m1
lea r0, [r0 + 4 * r1]
movu [r0 + r1 * 0], m1
movu [r0 + r1 * 1], m1
movu [r0 + r1 * 2], m1
movu [r0 + r3 * 1], m1
lea r0, [r0 + 4 * r1]
movu [r0 + r1 * 0], m1
movu [r0 + r1 * 1], m1
movu [r0 + r1 * 2], m1
movu [r0 + r3 * 1], m1
lea r0, [r0 + 4 * r1]
movu [r0 + r1 * 0], m1
movu [r0 + r1 * 1], m1
movu [r0 + r1 * 2], m1
movu [r0 + r3 * 1], m1
lea r0, [r0 + 4 * r1]
movu [r0 + r1 * 0], m1
movu [r0 + r1 * 1], m1
movu [r0 + r1 * 2], m1
movu [r0 + r3 * 1], m1
lea r0, [r0 + 4 * r1]
movu [r0 + r1 * 0], m1
movu [r0 + r1 * 1], m1
movu [r0 + r1 * 2], m1
movu [r0 + r3 * 1], m1
RET
%endif ;; ARCH_X86_64 == 1
;---------------------------------------------------------------------------------------
; void intra_pred_planar(pixel* dst, intptr_t dstStride, pixel*srcPix, int, int filter)
;---------------------------------------------------------------------------------------
INIT_XMM sse4
cglobal intra_pred_planar4, 3,3,7
pmovzxbw m1, [r2 + 1]
pmovzxbw m2, [r2 + 9]
pshufhw m3, m1, 0 ; topRight
pshufd m3, m3, 0xAA
pshufhw m4, m2, 0 ; bottomLeft
pshufd m4, m4, 0xAA
pmullw m3, [multi_2Row] ; (x + 1) * topRight
pmullw m0, m1, [pw_3] ; (blkSize - 1 - y) * above[x]
mova m6, [pw_planar4_0]
paddw m3, [pw_4]
paddw m3, m4
paddw m3, m0
psubw m4, m1
pshuflw m5, m2, 0
pmullw m5, m6
paddw m5, m3
paddw m3, m4
psraw m5, 3
packuswb m5, m5
movd [r0], m5
pshuflw m5, m2, 01010101b
pmullw m5, m6
paddw m5, m3
paddw m3, m4
psraw m5, 3
packuswb m5, m5
movd [r0 + r1], m5
lea r0, [r0 + 2 * r1]
pshuflw m5, m2, 10101010b
pmullw m5, m6
paddw m5, m3
paddw m3, m4
psraw m5, 3
packuswb m5, m5
movd [r0], m5
pshuflw m5, m2, 11111111b
pmullw m5, m6
paddw m5, m3
paddw m3, m4
psraw m5, 3
packuswb m5, m5
movd [r0 + r1], m5
RET
;---------------------------------------------------------------------------------------
; void intra_pred_planar(pixel* dst, intptr_t dstStride, pixel*srcPix, int, int filter)
;---------------------------------------------------------------------------------------
INIT_XMM sse4
cglobal intra_pred_planar8, 3,3,7
pmovzxbw m1, [r2 + 1]
pmovzxbw m2, [r2 + 17]
movd m3, [r2 + 9] ; topRight = above[8];
movd m4, [r2 + 25] ; bottomLeft = left[8];
pxor m0, m0
pshufb m3, m0
pshufb m4, m0
punpcklbw m3, m0 ; v_topRight
punpcklbw m4, m0 ; v_bottomLeft
pmullw m3, [multiL] ; (x + 1) * topRight
pmullw m0, m1, [pw_7] ; (blkSize - 1 - y) * above[x]
mova m6, [pw_planar16_mul + mmsize]
paddw m3, [pw_8]
paddw m3, m4
paddw m3, m0
psubw m4, m1
%macro INTRA_PRED_PLANAR8 1
%if (%1 < 4)
pshuflw m5, m2, 0x55 * %1
pshufd m5, m5, 0
%else
pshufhw m5, m2, 0x55 * (%1 - 4)
pshufd m5, m5, 0xAA
%endif
pmullw m5, m6
paddw m5, m3
paddw m3, m4
psraw m5, 4
packuswb m5, m5
movh [r0], m5
lea r0, [r0 + r1]
%endmacro
INTRA_PRED_PLANAR8 0
INTRA_PRED_PLANAR8 1
INTRA_PRED_PLANAR8 2
INTRA_PRED_PLANAR8 3
INTRA_PRED_PLANAR8 4
INTRA_PRED_PLANAR8 5
INTRA_PRED_PLANAR8 6
INTRA_PRED_PLANAR8 7
RET
;---------------------------------------------------------------------------------------
; void intra_pred_planar(pixel* dst, intptr_t dstStride, pixel*srcPix, int, int filter)
;---------------------------------------------------------------------------------------
INIT_XMM sse4
cglobal intra_pred_planar16, 3,3,8
pmovzxbw m2, [r2 + 1]
pmovzxbw m7, [r2 + 9]
movd m3, [r2 + 17] ; topRight = above[16]
movd m6, [r2 + 49] ; bottomLeft = left[16]
pxor m0, m0
pshufb m3, m0
pshufb m6, m0
punpcklbw m3, m0 ; v_topRight
punpcklbw m6, m0 ; v_bottomLeft
pmullw m4, m3, [multiH] ; (x + 1) * topRight
pmullw m3, [multiL] ; (x + 1) * topRight
pmullw m1, m2, [pw_15] ; (blkSize - 1 - y) * above[x]
pmullw m5, m7, [pw_15] ; (blkSize - 1 - y) * above[x]
paddw m4, [pw_16]
paddw m3, [pw_16]
paddw m4, m6
paddw m3, m6
paddw m4, m5
paddw m3, m1
psubw m1, m6, m7
psubw m6, m2
pmovzxbw m2, [r2 + 33]
pmovzxbw m7, [r2 + 41]
%macro INTRA_PRED_PLANAR16 1
%if (%1 < 4)
pshuflw m5, m2, 0x55 * %1
pshufd m5, m5, 0
%else
%if (%1 < 8)
pshufhw m5, m2, 0x55 * (%1 - 4)
pshufd m5, m5, 0xAA
%else
%if (%1 < 12)
pshuflw m5, m7, 0x55 * (%1 - 8)
pshufd m5, m5, 0
%else
pshufhw m5, m7, 0x55 * (%1 - 12)
pshufd m5, m5, 0xAA
%endif
%endif
%endif
pmullw m0, m5, [pw_planar16_mul + mmsize]
pmullw m5, [pw_planar16_mul]
paddw m0, m4
paddw m5, m3
paddw m3, m6
paddw m4, m1
psraw m5, 5
psraw m0, 5
packuswb m5, m0
movu [r0], m5
lea r0, [r0 + r1]
%endmacro
INTRA_PRED_PLANAR16 0
INTRA_PRED_PLANAR16 1
INTRA_PRED_PLANAR16 2
INTRA_PRED_PLANAR16 3
INTRA_PRED_PLANAR16 4
INTRA_PRED_PLANAR16 5
INTRA_PRED_PLANAR16 6
INTRA_PRED_PLANAR16 7
INTRA_PRED_PLANAR16 8
INTRA_PRED_PLANAR16 9
INTRA_PRED_PLANAR16 10
INTRA_PRED_PLANAR16 11
INTRA_PRED_PLANAR16 12
INTRA_PRED_PLANAR16 13
INTRA_PRED_PLANAR16 14
INTRA_PRED_PLANAR16 15
RET
;---------------------------------------------------------------------------------------
; void intra_pred_planar(pixel* dst, intptr_t dstStride, pixel*srcPix, int, int filter)
;---------------------------------------------------------------------------------------
INIT_YMM avx2
cglobal intra_pred_planar16, 3,3,6
vpbroadcastw m3, [r2 + 17]
mova m5, [pw_00ff]
vpbroadcastw m4, [r2 + 49]
mova m0, [pw_planar16_mul]
pmovzxbw m2, [r2 + 1]
pand m3, m5 ; v_topRight
pand m4, m5 ; v_bottomLeft
pmullw m3, [multiL] ; (x + 1) * topRight
pmullw m1, m2, [pw_15] ; (blkSize - 1 - y) * above[x]
paddw m3, [pw_16]
paddw m3, m4
paddw m3, m1
psubw m4, m2
add r2, 33
%macro INTRA_PRED_PLANAR16_AVX2 1
vpbroadcastw m1, [r2 + %1]
vpsrlw m2, m1, 8
pand m1, m5
pmullw m1, m0
pmullw m2, m0
paddw m1, m3
paddw m3, m4
psraw m1, 5
paddw m2, m3
psraw m2, 5
paddw m3, m4
packuswb m1, m2
vpermq m1, m1, 11011000b
movu [r0], xm1
vextracti128 [r0 + r1], m1, 1
lea r0, [r0 + r1 * 2]
%endmacro
INTRA_PRED_PLANAR16_AVX2 0
INTRA_PRED_PLANAR16_AVX2 2
INTRA_PRED_PLANAR16_AVX2 4
INTRA_PRED_PLANAR16_AVX2 6
INTRA_PRED_PLANAR16_AVX2 8
INTRA_PRED_PLANAR16_AVX2 10
INTRA_PRED_PLANAR16_AVX2 12
INTRA_PRED_PLANAR16_AVX2 14
%undef INTRA_PRED_PLANAR16_AVX2
RET
;---------------------------------------------------------------------------------------
; void intra_pred_planar(pixel* dst, intptr_t dstStride, pixel*srcPix, int, int filter)
;---------------------------------------------------------------------------------------
INIT_XMM sse4
%if ARCH_X86_64 == 1
cglobal intra_pred_planar32, 3,4,12
%else
cglobal intra_pred_planar32, 3,4,8,0-(4*mmsize)
%define m8 [rsp + 0 * mmsize]
%define m9 [rsp + 1 * mmsize]
%define m10 [rsp + 2 * mmsize]
%define m11 [rsp + 3 * mmsize]
%endif
movd m3, [r2 + 33] ; topRight = above[32]
pxor m7, m7
pshufb m3, m7
punpcklbw m3, m7 ; v_topRight
pmullw m0, m3, [multiL] ; (x + 1) * topRight
pmullw m1, m3, [multiH] ; (x + 1) * topRight
pmullw m2, m3, [multiH2] ; (x + 1) * topRight
pmullw m3, [multiH3] ; (x + 1) * topRight
movd m6, [r2 + 97] ; bottomLeft = left[32]
pshufb m6, m7
punpcklbw m6, m7 ; v_bottomLeft
paddw m0, m6
paddw m1, m6
paddw m2, m6
paddw m3, m6
paddw m0, [pw_32]
paddw m1, [pw_32]
paddw m2, [pw_32]
paddw m3, [pw_32]
pmovzxbw m4, [r2 + 1]
pmullw m5, m4, [pw_31]
paddw m0, m5
psubw m5, m6, m4
mova m8, m5
pmovzxbw m4, [r2 + 9]
pmullw m5, m4, [pw_31]
paddw m1, m5
psubw m5, m6, m4
mova m9, m5
pmovzxbw m4, [r2 + 17]
pmullw m5, m4, [pw_31]
paddw m2, m5
psubw m5, m6, m4
mova m10, m5
pmovzxbw m4, [r2 + 25]
pmullw m5, m4, [pw_31]
paddw m3, m5
psubw m5, m6, m4
mova m11, m5
add r2, 65 ; (2 * blkSize + 1)
%macro INTRA_PRED_PLANAR32 0
movd m4, [r2]
pshufb m4, m7
punpcklbw m4, m7
pmullw m5, m4, [pw_planar32_mul]
pmullw m6, m4, [pw_planar32_mul + mmsize]
paddw m5, m0
paddw m6, m1
paddw m0, m8
paddw m1, m9
psraw m5, 6
psraw m6, 6
packuswb m5, m6
movu [r0], m5
pmullw m5, m4, [pw_planar16_mul]
pmullw m4, [pw_planar16_mul + mmsize]
paddw m5, m2
paddw m4, m3
paddw m2, m10
paddw m3, m11
psraw m5, 6
psraw m4, 6
packuswb m5, m4
movu [r0 + 16], m5
lea r0, [r0 + r1]
inc r2
%endmacro
mov r3, 4
.loop:
INTRA_PRED_PLANAR32
INTRA_PRED_PLANAR32
INTRA_PRED_PLANAR32
INTRA_PRED_PLANAR32
INTRA_PRED_PLANAR32
INTRA_PRED_PLANAR32
INTRA_PRED_PLANAR32
INTRA_PRED_PLANAR32
dec r3
jnz .loop
RET
;---------------------------------------------------------------------------------------
; void intra_pred_planar(pixel* dst, intptr_t dstStride, pixel*srcPix, int, int filter)
;---------------------------------------------------------------------------------------
%if ARCH_X86_64 == 1
INIT_YMM avx2
cglobal intra_pred_planar32, 3,4,11
mova m6, [pw_00ff]
vpbroadcastw m3, [r2 + 33] ; topRight = above[32]
vpbroadcastw m2, [r2 + 97] ; bottomLeft = left[32]
pand m3, m6
pand m2, m6
pmullw m0, m3, [multiL] ; (x + 1) * topRight
pmullw m3, [multiH2] ; (x + 1) * topRight
paddw m0, m2
paddw m3, m2
paddw m0, [pw_32]
paddw m3, [pw_32]
pmovzxbw m4, [r2 + 1]
pmovzxbw m1, [r2 + 17]
pmullw m5, m4, [pw_31]
paddw m0, m5
psubw m5, m2, m4
psubw m2, m1
pmullw m1, [pw_31]
paddw m3, m1
mova m1, m5
add r2, 65 ; (2 * blkSize + 1)
mova m9, [pw_planar32_mul]
mova m10, [pw_planar16_mul]
%macro INTRA_PRED_PLANAR32_AVX2 0
vpbroadcastw m4, [r2]
vpsrlw m7, m4, 8
pand m4, m6
pmullw m5, m4, m9
pmullw m4, m4, m10
paddw m5, m0
paddw m4, m3
paddw m0, m1
paddw m3, m2
psraw m5, 6
psraw m4, 6
packuswb m5, m4
pmullw m8, m7, m9
pmullw m7, m7, m10
vpermq m5, m5, 11011000b
paddw m8, m0
paddw m7, m3
paddw m0, m1
paddw m3, m2
psraw m8, 6
psraw m7, 6
packuswb m8, m7
add r2, 2
vpermq m8, m8, 11011000b
movu [r0], m5
movu [r0 + r1], m8
lea r0, [r0 + r1 * 2]
%endmacro
INTRA_PRED_PLANAR32_AVX2
INTRA_PRED_PLANAR32_AVX2
INTRA_PRED_PLANAR32_AVX2
INTRA_PRED_PLANAR32_AVX2
INTRA_PRED_PLANAR32_AVX2
INTRA_PRED_PLANAR32_AVX2
INTRA_PRED_PLANAR32_AVX2
INTRA_PRED_PLANAR32_AVX2
INTRA_PRED_PLANAR32_AVX2
INTRA_PRED_PLANAR32_AVX2
INTRA_PRED_PLANAR32_AVX2
INTRA_PRED_PLANAR32_AVX2
INTRA_PRED_PLANAR32_AVX2
INTRA_PRED_PLANAR32_AVX2
INTRA_PRED_PLANAR32_AVX2
INTRA_PRED_PLANAR32_AVX2
%undef INTRA_PRED_PLANAR32_AVX2
RET
%endif ;; ARCH_X86_64 == 1
;-----------------------------------------------------------------------------------------
; void intraPredAng4(pixel* dst, intptr_t dstStride, pixel* src, int dirMode, int bFilter)
;-----------------------------------------------------------------------------------------
INIT_XMM ssse3
cglobal intra_pred_ang4_2, 3,5,3
lea r4, [r2 + 2]
add r2, 10
cmp r3m, byte 34
cmove r2, r4
movh m0, [r2]
movd [r0], m0
palignr m1, m0, 1
movd [r0 + r1], m1
palignr m2, m0, 2
movd [r0 + r1 * 2], m2
lea r1, [r1 * 3]
psrldq m0, 3
movd [r0 + r1], m0
RET
INIT_XMM sse4
cglobal intra_pred_ang4_3, 3,5,5
mov r4, 1
cmp r3m, byte 33
mov r3, 9
cmove r3, r4
movh m0, [r2 + r3] ; [8 7 6 5 4 3 2 1]
palignr m1, m0, 1 ; [x 8 7 6 5 4 3 2]
punpcklbw m0, m1 ; [x 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
palignr m1, m0, 2 ; [x x x x x x x x 6 5 5 4 4 3 3 2]
palignr m2, m0, 4 ; [x x x x x x x x 7 6 6 5 5 4 4 3]
palignr m3, m0, 6 ; [x x x x x x x x 8 7 7 6 6 5 5 4]
punpcklqdq m0, m1
punpcklqdq m2, m3
lea r3, [ang_table + 20 * 16]
movh m3, [r3 + 6 * 16] ; [26]
movhps m3, [r3] ; [20]
movh m4, [r3 - 6 * 16] ; [14]
movhps m4, [r3 - 12 * 16] ; [ 8]
jmp .do_filter4x4
; NOTE: share path, input is m0=[1 0], m2=[3 2], m3,m4=coef, flag_z=no_transpose
ALIGN 16
.do_filter4x4:
mova m1, [pw_1024]
pmaddubsw m0, m3
pmulhrsw m0, m1
pmaddubsw m2, m4
pmulhrsw m2, m1
packuswb m0, m2
; NOTE: mode 33 doesn't reorde, UNSAFE but I don't use any instruction that affect eflag register before
jz .store
; transpose 4x4
pshufb m0, [c_trans_4x4]
.store:
; TODO: use pextrd here after intrinsic ssse3 removed
movd [r0], m0
pextrd [r0 + r1], m0, 1
pextrd [r0 + r1 * 2], m0, 2
lea r1, [r1 * 3]
pextrd [r0 + r1], m0, 3
RET
cglobal intra_pred_ang4_4, 3,5,5
xor r4, r4
inc r4
cmp r3m, byte 32
mov r3, 9
cmove r3, r4
movh m0, [r2 + r3] ; [8 7 6 5 4 3 2 1]
palignr m1, m0, 1 ; [x 8 7 6 5 4 3 2]
punpcklbw m0, m1 ; [x 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
palignr m1, m0, 2 ; [x x x x x x x x 6 5 5 4 4 3 3 2]
palignr m3, m0, 4 ; [x x x x x x x x 7 6 6 5 5 4 4 3]
punpcklqdq m0, m1
punpcklqdq m2, m1, m3
lea r3, [ang_table + 18 * 16]
movh m3, [r3 + 3 * 16] ; [21]
movhps m3, [r3 - 8 * 16] ; [10]
movh m4, [r3 + 13 * 16] ; [31]
movhps m4, [r3 + 2 * 16] ; [20]
jmp mangle(private_prefix %+ _ %+ intra_pred_ang4_3 %+ SUFFIX %+ .do_filter4x4)
cglobal intra_pred_ang4_5, 3,5,5
xor r4, r4
inc r4
cmp r3m, byte 31
mov r3, 9
cmove r3, r4
movh m0, [r2 + r3] ; [8 7 6 5 4 3 2 1]
palignr m1, m0, 1 ; [x 8 7 6 5 4 3 2]
punpcklbw m0, m1 ; [x 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
palignr m1, m0, 2 ; [x x x x x x x x 6 5 5 4 4 3 3 2]
palignr m3, m0, 4 ; [x x x x x x x x 7 6 6 5 5 4 4 3]
punpcklqdq m0, m1
punpcklqdq m2, m1, m3
lea r3, [ang_table + 10 * 16]
movh m3, [r3 + 7 * 16] ; [17]
movhps m3, [r3 - 8 * 16] ; [ 2]
movh m4, [r3 + 9 * 16] ; [19]
movhps m4, [r3 - 6 * 16] ; [ 4]
jmp mangle(private_prefix %+ _ %+ intra_pred_ang4_3 %+ SUFFIX %+ .do_filter4x4)
cglobal intra_pred_ang4_6, 3,5,5
xor r4, r4
inc r4
cmp r3m, byte 30
mov r3, 9
cmove r3, r4
movh m0, [r2 + r3] ; [8 7 6 5 4 3 2 1]
palignr m1, m0, 1 ; [x 8 7 6 5 4 3 2]
punpcklbw m0, m1 ; [x 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
palignr m2, m0, 2 ; [x x x x x x x x 6 5 5 4 4 3 3 2]
punpcklqdq m0, m0
punpcklqdq m2, m2
lea r3, [ang_table + 19 * 16]
movh m3, [r3 - 6 * 16] ; [13]
movhps m3, [r3 + 7 * 16] ; [26]
movh m4, [r3 - 12 * 16] ; [ 7]
movhps m4, [r3 + 1 * 16] ; [20]
jmp mangle(private_prefix %+ _ %+ intra_pred_ang4_3 %+ SUFFIX %+ .do_filter4x4)
cglobal intra_pred_ang4_7, 3,5,5
xor r4, r4
inc r4
cmp r3m, byte 29
mov r3, 9
cmove r3, r4
movh m0, [r2 + r3] ; [8 7 6 5 4 3 2 1]
palignr m1, m0, 1 ; [x 8 7 6 5 4 3 2]
punpcklbw m0, m1 ; [x 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
palignr m3, m0, 2 ; [x x x x x x x x 6 5 5 4 4 3 3 2]
punpcklqdq m2, m0, m3
punpcklqdq m0, m0
lea r3, [ang_table + 20 * 16]
movh m3, [r3 - 11 * 16] ; [ 9]
movhps m3, [r3 - 2 * 16] ; [18]
movh m4, [r3 + 7 * 16] ; [27]
movhps m4, [r3 - 16 * 16] ; [ 4]
jmp mangle(private_prefix %+ _ %+ intra_pred_ang4_3 %+ SUFFIX %+ .do_filter4x4)
cglobal intra_pred_ang4_8, 3,5,5
xor r4, r4
inc r4
cmp r3m, byte 28
mov r3, 9
cmove r3, r4
movh m0, [r2 + r3] ; [8 7 6 5 4 3 2 1]
palignr m1, m0, 1 ; [x 8 7 6 5 4 3 2]
punpcklbw m0, m1 ; [x 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
punpcklqdq m0, m0
mova m2, m0
lea r3, [ang_table + 13 * 16]
movh m3, [r3 - 8 * 16] ; [ 5]
movhps m3, [r3 - 3 * 16] ; [10]
movh m4, [r3 + 2 * 16] ; [15]
movhps m4, [r3 + 7 * 16] ; [20]
jmp mangle(private_prefix %+ _ %+ intra_pred_ang4_3 %+ SUFFIX %+ .do_filter4x4)
cglobal intra_pred_ang4_9, 3,5,5
xor r4, r4
inc r4
cmp r3m, byte 27
mov r3, 9
cmove r3, r4
movh m0, [r2 + r3] ; [8 7 6 5 4 3 2 1]
palignr m1, m0, 1 ; [x 8 7 6 5 4 3 2]
punpcklbw m0, m1 ; [x 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
punpcklqdq m0, m0
mova m2, m0
lea r3, [ang_table + 4 * 16]
movh m3, [r3 - 2 * 16] ; [ 2]
movhps m3, [r3 - 0 * 16] ; [ 4]
movh m4, [r3 + 2 * 16] ; [ 6]
movhps m4, [r3 + 4 * 16] ; [ 8]
jmp mangle(private_prefix %+ _ %+ intra_pred_ang4_3 %+ SUFFIX %+ .do_filter4x4)
cglobal intra_pred_ang4_10, 3,3,4
movd m0, [r2 + 9] ; [8 7 6 5 4 3 2 1]
pshufb m0, [pb_unpackbd1]
pshufd m1, m0, 1
movhlps m2, m0
pshufd m3, m0, 3
movd [r0 + r1], m1
movd [r0 + r1 * 2], m2
lea r1, [r1 * 3]
movd [r0 + r1], m3
cmp r4m, byte 0
jz .quit
; filter
pmovzxbw m0, m0 ; [-1 -1 -1 -1]
movh m1, [r2] ; [4 3 2 1 0]
pshufb m2, m1, [pb_0_8] ; [0 0 0 0]
pshufb m1, [pb_unpackbw1] ; [4 3 2 1]
psubw m1, m2
psraw m1, 1
paddw m0, m1
packuswb m0, m0
.quit:
movd [r0], m0
RET
INIT_XMM sse4
cglobal intra_pred_ang4_26, 3,4,3
movd m0, [r2 + 1] ; [8 7 6 5 4 3 2 1]
; store
movd [r0], m0
movd [r0 + r1], m0
movd [r0 + r1 * 2], m0
lea r3, [r1 * 3]
movd [r0 + r3], m0
; filter
cmp r4m, byte 0
jz .quit
pshufb m0, [pb_0_8] ; [ 1 1 1 1]
movh m1, [r2 + 8] ; [-4 -3 -2 -1 0]
pinsrb m1, [r2], 0
pshufb m2, m1, [pb_0_8] ; [0 0 0 0]
pshufb m1, [pb_unpackbw1] ; [-4 -3 -2 -1]
psubw m1, m2
psraw m1, 1
paddw m0, m1
packuswb m0, m0
pextrb [r0], m0, 0
pextrb [r0 + r1], m0, 1
pextrb [r0 + r1 * 2], m0, 2
pextrb [r0 + r3], m0, 3
.quit:
RET
cglobal intra_pred_ang4_11, 3,5,5
xor r4, r4
cmp r3m, byte 25
mov r3, 8
cmove r3, r4
movh m0, [r2 + r3] ; [x x x 4 3 2 1 0]
pinsrb m0, [r2], 0
palignr m1, m0, 1 ; [x x x x 4 3 2 1]
punpcklbw m0, m1 ; [x x x x x x x x 4 3 3 2 2 1 1 0]
punpcklqdq m0, m0
mova m2, m0
lea r3, [ang_table + 24 * 16]
movh m3, [r3 + 6 * 16] ; [24]
movhps m3, [r3 + 4 * 16] ; [26]
movh m4, [r3 + 2 * 16] ; [28]
movhps m4, [r3 + 0 * 16] ; [30]
jmp mangle(private_prefix %+ _ %+ intra_pred_ang4_3 %+ SUFFIX %+ .do_filter4x4)
cglobal intra_pred_ang4_12, 3,5,5
xor r4, r4
cmp r3m, byte 24
mov r3, 8
cmove r3, r4
movh m0, [r2 + r3] ; [x x x 4 3 2 1 0]
pinsrb m0, [r2], 0
palignr m1, m0, 1 ; [x x x x 4 3 2 1]
punpcklbw m0, m1 ; [x x x x x x x x 4 3 3 2 2 1 1 0]
punpcklqdq m0, m0
mova m2, m0
lea r3, [ang_table + 20 * 16]
movh m3, [r3 + 7 * 16] ; [27]
movhps m3, [r3 + 2 * 16] ; [22]
movh m4, [r3 - 3 * 16] ; [17]
movhps m4, [r3 - 8 * 16] ; [12]
jmp mangle(private_prefix %+ _ %+ intra_pred_ang4_3 %+ SUFFIX %+ .do_filter4x4)
cglobal intra_pred_ang4_13, 4,5,5
xor r4, r4
cmp r3m, byte 23
mov r3, 8
jz .next
xchg r3, r4
.next:
movh m1, [r2 + r4 - 1] ; [x x 4 3 2 1 0 x]
pinsrb m1, [r2], 1
palignr m0, m1, 1 ; [x x x 4 3 2 1 0]
palignr m2, m1, 2 ; [x x x x 4 3 2 1]
pinsrb m1, [r2 + r3 + 4], 0
punpcklbw m1, m0 ; [3 2 2 1 1 0 0 x]
punpcklbw m0, m2 ; [4 3 3 2 2 1 1 0]
punpcklqdq m2, m0, m1
punpcklqdq m0, m0
lea r3, [ang_table + 21 * 16]
movh m3, [r3 + 2 * 16] ; [23]
movhps m3, [r3 - 7 * 16] ; [14]
movh m4, [r3 - 16 * 16] ; [ 5]
movhps m4, [r3 + 7 * 16] ; [28]
jmp mangle(private_prefix %+ _ %+ intra_pred_ang4_3 %+ SUFFIX %+ .do_filter4x4)
cglobal intra_pred_ang4_14, 4,5,5
xor r4, r4
cmp r3m, byte 22
mov r3, 8
jz .next
xchg r3, r4
.next:
movh m2, [r2 + r4 - 1] ; [x x 4 3 2 1 0 x]
pinsrb m2, [r2], 1
palignr m0, m2, 1 ; [x x x 4 3 2 1 0]
palignr m1, m2, 2 ; [x x x x 4 3 2 1]
pinsrb m2, [r2 + r3 + 2], 0
punpcklbw m2, m0 ; [3 2 2 1 1 0 0 x]
punpcklbw m0, m1 ; [4 3 3 2 2 1 1 0]
punpcklqdq m0, m0
punpcklqdq m2, m2
lea r3, [ang_table + 19 * 16]
movh m3, [r3 + 0 * 16] ; [19]
movhps m3, [r3 - 13 * 16] ; [ 6]
movh m4, [r3 + 6 * 16] ; [25]
movhps m4, [r3 - 7 * 16] ; [12]
jmp mangle(private_prefix %+ _ %+ intra_pred_ang4_3 %+ SUFFIX %+ .do_filter4x4)
cglobal intra_pred_ang4_15, 4,5,5
xor r4, r4
cmp r3m, byte 21
mov r3, 8
jz .next
xchg r3, r4
.next:
movh m2, [r2 + r4 - 1] ; [x x 4 3 2 1 0 x]
pinsrb m2, [r2], 1
palignr m0, m2, 1 ; [x x x 4 3 2 1 0]
palignr m1, m2, 2 ; [x x x x 4 3 2 1]
pinsrb m2, [r2 + r3 + 2], 0
pslldq m3, m2, 1 ; [x 4 3 2 1 0 x y]
pinsrb m3, [r2 + r3 + 4], 0
punpcklbw m4, m3, m2 ; [2 1 1 0 0 x x y]
punpcklbw m2, m0 ; [3 2 2 1 1 0 0 x]
punpcklbw m0, m1 ; [4 3 3 2 2 1 1 0]
punpcklqdq m0, m2
punpcklqdq m2, m4
lea r3, [ang_table + 23 * 16]
movh m3, [r3 - 8 * 16] ; [15]
movhps m3, [r3 + 7 * 16] ; [30]
movh m4, [r3 - 10 * 16] ; [13]
movhps m4, [r3 + 5 * 16] ; [28]
jmp mangle(private_prefix %+ _ %+ intra_pred_ang4_3 %+ SUFFIX %+ .do_filter4x4)
cglobal intra_pred_ang4_16, 3,5,5
xor r4, r4
cmp r3m, byte 20
mov r3, 8
jz .next
xchg r3, r4
.next:
movh m2, [r2 + r4 - 1] ; [x x 4 3 2 1 0 x]
pinsrb m2, [r2], 1
palignr m0, m2, 1 ; [x x x 4 3 2 1 0]
palignr m1, m2, 2 ; [x x x x 4 3 2 1]
pinsrb m2, [r2 + r3 + 2], 0
pslldq m3, m2, 1 ; [x 4 3 2 1 0 x y]
pinsrb m3, [r2 + r3 + 3], 0
punpcklbw m4, m3, m2 ; [2 1 1 0 0 x x y]
punpcklbw m2, m0 ; [3 2 2 1 1 0 0 x]
punpcklbw m0, m1 ; [4 3 3 2 2 1 1 0]
punpcklqdq m0, m2
punpcklqdq m2, m4
lea r3, [ang_table + 19 * 16]
movh m3, [r3 - 8 * 16] ; [11]
movhps m3, [r3 + 3 * 16] ; [22]
movh m4, [r3 - 18 * 16] ; [ 1]
movhps m4, [r3 - 7 * 16] ; [12]
jmp mangle(private_prefix %+ _ %+ intra_pred_ang4_3 %+ SUFFIX %+ .do_filter4x4)
cglobal intra_pred_ang4_17, 3,5,5
xor r4, r4
cmp r3m, byte 19
mov r3, 8
jz .next
xchg r3, r4
.next:
movh m3, [r2 + r4 - 1] ; [- - 4 3 2 1 0 x]
pinsrb m3, [r2], 1
palignr m0, m3, 1 ; [- - - 4 3 2 1 0]
palignr m1, m3, 2 ; [- - - - 4 3 2 1]
mova m4, m0
punpcklbw m0, m1 ; [4 3 3 2 2 1 1 0]
pinsrb m3, [r2 + r3 + 1], 0
punpcklbw m1, m3, m4 ; [3 2 2 1 1 0 0 x]
punpcklqdq m0, m1
pslldq m2, m3, 1 ; [- 4 3 2 1 0 x y]
pinsrb m2, [r2 + r3 + 2], 0
pslldq m1, m2, 1 ; [4 3 2 1 0 x y z]
pinsrb m1, [r2 + r3 + 4], 0
punpcklbw m1, m2 ; [1 0 0 x x y y z]
punpcklbw m2, m3 ; [2 1 1 0 0 x x y]
punpcklqdq m2, m1
lea r3, [ang_table + 14 * 16]
movh m3, [r3 - 8 * 16] ; [ 6]
movhps m3, [r3 - 2 * 16] ; [12]
movh m4, [r3 + 4 * 16] ; [18]
movhps m4, [r3 + 10 * 16] ; [24]
jmp mangle(private_prefix %+ _ %+ intra_pred_ang4_3 %+ SUFFIX %+ .do_filter4x4)
cglobal intra_pred_ang4_18, 3,5,1
mov r4d, [r2 + 8]
mov r3b, byte [r2]
mov [r2 + 8], r3b
mov r3d, [r2 + 8]
bswap r3d
movd m0, r3d
pinsrd m0, [r2 + 1], 1 ; [- 3 2 1 0 -1 -2 -3]
lea r3, [r1 * 3]
movd [r0 + r3], m0
psrldq m0, 1
movd [r0 + r1 * 2], m0
psrldq m0, 1
movd [r0 + r1], m0
psrldq m0, 1
movd [r0], m0
mov [r2 + 8], r4w
RET
;-----------------------------------------------------------------------------------------
; void intraPredAng8(pixel* dst, intptr_t dstStride, pixel* src, int dirMode, int bFilter)
;-----------------------------------------------------------------------------------------
INIT_XMM ssse3
cglobal intra_pred_ang8_2, 3,5,2
lea r4, [r2 + 2]
add r2, 18
cmp r3m, byte 34
cmove r2, r4
movu m0, [r2]
lea r4, [r1 * 3]
movh [r0], m0
palignr m1, m0, 1
movh [r0 + r1], m1
palignr m1, m0, 2
movh [r0 + r1 * 2], m1
palignr m1, m0, 3
movh [r0 + r4], m1
palignr m1, m0, 4
lea r0, [r0 + r1 * 4]
movh [r0], m1
palignr m1, m0, 5
movh [r0 + r1], m1
palignr m1, m0, 6
movh [r0 + r1 * 2], m1
palignr m1, m0, 7
movh [r0 + r4], m1
RET
INIT_XMM sse4
cglobal intra_pred_ang8_3, 3,5,8
lea r4, [r2 + 1]
add r2, 17
cmp r3m, byte 33
cmove r2, r4
lea r3, [ang_table + 22 * 16]
lea r4, [ang_table + 8 * 16]
mova m3, [pw_1024]
movu m0, [r2] ; [16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
palignr m1, m0, 1 ; [x 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
punpckhbw m2, m0, m1 ; [x 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m0, m1 ; [9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
palignr m1, m2, m0, 2 ; [10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2]
pmaddubsw m4, m0, [r3 + 4 * 16] ; [26]
pmulhrsw m4, m3
pmaddubsw m1, [r3 - 2 * 16] ; [20]
pmulhrsw m1, m3
packuswb m4, m1
palignr m5, m2, m0, 4 ; [11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3]
pmaddubsw m5, [r3 - 8 * 16] ; [14]
pmulhrsw m5, m3
palignr m6, m2, m0, 6 ; [12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 4]
pmaddubsw m6, [r4] ; [ 8]
pmulhrsw m6, m3
packuswb m5, m6
palignr m1, m2, m0, 8 ; [13 12 12 11 11 10 10 9 9 8 8 7 7 6 6 5]
pmaddubsw m6, m1, [r4 - 6 * 16] ; [ 2]
pmulhrsw m6, m3
pmaddubsw m1, [r3 + 6 * 16] ; [28]
pmulhrsw m1, m3
packuswb m6, m1
palignr m1, m2, m0, 10 ; [14 13 13 12 12 11 11 10 10 9 9 8 8 7 7 6]
pmaddubsw m1, [r3] ; [22]
pmulhrsw m1, m3
palignr m2, m0, 12 ; [15 14 14 13 13 12 12 11 11 10 10 9 9 8 8 7]
pmaddubsw m2, [r3 - 6 * 16] ; [16]
pmulhrsw m2, m3
packuswb m1, m2
jmp .transpose8x8
ALIGN 16
.transpose8x8:
jz .store
; transpose 8x8
punpckhbw m0, m4, m5
punpcklbw m4, m5
punpckhbw m2, m4, m0
punpcklbw m4, m0
punpckhbw m0, m6, m1
punpcklbw m6, m1
punpckhbw m1, m6, m0
punpcklbw m6, m0
punpckhdq m5, m4, m6
punpckldq m4, m6
punpckldq m6, m2, m1
punpckhdq m2, m1
mova m1, m2
.store:
lea r4, [r1 * 3]
movh [r0], m4
movhps [r0 + r1], m4
movh [r0 + r1 * 2], m5
movhps [r0 + r4], m5
add r0, r4
movh [r0 + r1], m6
movhps [r0 + r1 * 2], m6
movh [r0 + r4], m1
movhps [r0 + r1 * 4], m1
RET
cglobal intra_pred_ang8_4, 3,5,8
lea r4, [r2 + 1]
add r2, 17
cmp r3m, byte 32
cmove r2, r4
lea r3, [ang_table + 24 * 16]
lea r4, [ang_table + 10 * 16]
mova m3, [pw_1024]
movu m0, [r2] ; [16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
palignr m1, m0, 1 ; [x 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
punpckhbw m2, m0, m1 ; [x 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m0, m1 ; [9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
palignr m1, m2, m0, 2 ; [10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2]
mova m5, m1
pmaddubsw m4, m0, [r3 - 3 * 16] ; [21]
pmulhrsw m4, m3
pmaddubsw m1, [r4] ; [10]
pmulhrsw m1, m3
packuswb m4, m1
pmaddubsw m5, [r3 + 7 * 16] ; [31]
pmulhrsw m5, m3
palignr m6, m2, m0, 4 ; [11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3]
pmaddubsw m6, [r3 - 4 * 16] ; [ 20]
pmulhrsw m6, m3
packuswb m5, m6
palignr m1, m2, m0, 6 ; [12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 4]
pmaddubsw m6, m1, [r4 - 1 * 16] ; [ 9]
pmulhrsw m6, m3
pmaddubsw m1, [r3 + 6 * 16] ; [30]
pmulhrsw m1, m3
packuswb m6, m1
palignr m1, m2, m0, 8 ; [13 12 12 11 11 10 10 9 9 8 8 7 7 6 6 5]
pmaddubsw m1, [r3 - 5 * 16] ; [19]
pmulhrsw m1, m3
palignr m2, m0, 10 ; [14 13 13 12 12 11 11 10 10 9 9 8 8 7 7 8]
pmaddubsw m2, [r4 - 2 * 16] ; [8]
pmulhrsw m2, m3
packuswb m1, m2
jmp mangle(private_prefix %+ _ %+ intra_pred_ang8_3 %+ SUFFIX %+ .transpose8x8)
cglobal intra_pred_ang8_5, 3,5,8
lea r4, [r2 + 1]
add r2, 17
cmp r3m, byte 31
cmove r2, r4
lea r3, [ang_table + 17 * 16]
lea r4, [ang_table + 2 * 16]
mova m3, [pw_1024]
movu m0, [r2] ; [16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
palignr m1, m0, 1 ; [x 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
punpckhbw m2, m0, m1 ; [x 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m0, m1 ; [9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
palignr m1, m2, m0, 2 ; [10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2]
mova m5, m1
pmaddubsw m4, m0, [r3] ; [17]
pmulhrsw m4, m3
pmaddubsw m1, [r4] ; [2]
pmulhrsw m1, m3
packuswb m4, m1
pmaddubsw m5, [r3 + 2 * 16] ; [19]
pmulhrsw m5, m3
palignr m6, m2, m0, 4 ; [11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3]
mova m1, m6
pmaddubsw m1, [r4 + 2 * 16] ; [4]
pmulhrsw m1, m3
packuswb m5, m1
pmaddubsw m6, [r3 + 4 * 16] ; [21]
pmulhrsw m6, m3
palignr m1, m2, m0, 6 ; [12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 4]
mova m7, m1
pmaddubsw m7, [r4 + 4 * 16] ; [6]
pmulhrsw m7, m3
packuswb m6, m7
pmaddubsw m1, [r3 + 6 * 16] ; [23]
pmulhrsw m1, m3
palignr m2, m0, 8 ; [13 12 12 11 11 10 10 9 9 8 8 7 7 8 8 9]
pmaddubsw m2, [r4 + 6 * 16] ; [8]
pmulhrsw m2, m3
packuswb m1, m2
jmp mangle(private_prefix %+ _ %+ intra_pred_ang8_3 %+ SUFFIX %+ .transpose8x8)
cglobal intra_pred_ang8_6, 3,5,8
lea r4, [r2 + 1]
add r2, 17
cmp r3m, byte 30
cmove r2, r4
lea r3, [ang_table + 20 * 16]
lea r4, [ang_table + 8 * 16]
mova m7, [pw_1024]
movu m0, [r2] ; [16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
palignr m1, m0, 1 ; [x 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
punpckhbw m2, m0, m1 ; [x 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m0, m1 ; [9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
mova m1, m0
pmaddubsw m4, m0, [r3 - 7 * 16] ; [13]
pmulhrsw m4, m7
pmaddubsw m1, [r3 + 6 * 16] ; [26]
pmulhrsw m1, m7
packuswb m4, m1
palignr m6, m2, m0, 2 ; [10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2]
pmaddubsw m5, m6, [r4 - 1 * 16] ; [7]
pmulhrsw m5, m7
pmaddubsw m6, [r3] ; [20]
pmulhrsw m6, m7
packuswb m5, m6
palignr m1, m2, m0, 4 ; [11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3]
pmaddubsw m6, m1, [r4 - 7 * 16] ; [1]
pmulhrsw m6, m7
mova m3, m1
pmaddubsw m3, [r3 - 6 * 16] ; [14]
pmulhrsw m3, m7
packuswb m6, m3
pmaddubsw m1, [r3 + 7 * 16] ; [27]
pmulhrsw m1, m7
palignr m2, m0, 6 ; [12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 4]
pmaddubsw m2, [r4] ; [8]
pmulhrsw m2, m7
packuswb m1, m2
jmp mangle(private_prefix %+ _ %+ intra_pred_ang8_3 %+ SUFFIX %+ .transpose8x8)
cglobal intra_pred_ang8_7, 3,5,8
lea r4, [r2 + 1]
add r2, 17
cmp r3m, byte 29
cmove r2, r4
lea r3, [ang_table + 24 * 16]
lea r4, [ang_table + 6 * 16]
mova m7, [pw_1024]
movu m0, [r2] ; [16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
palignr m1, m0, 1 ; [x 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
punpckhbw m2, m0, m1 ; [x 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m0, m1 ; [9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
pmaddubsw m4, m0, [r4 + 3 * 16] ; [9]
pmulhrsw m4, m7
pmaddubsw m3, m0, [r3 - 6 * 16] ; [18]
pmulhrsw m3, m7
packuswb m4, m3
pmaddubsw m5, m0, [r3 + 3 * 16] ; [27]
pmulhrsw m5, m7
palignr m1, m2, m0, 2 ; [10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2]
pmaddubsw m6, m1, [r4 - 2 * 16] ; [4]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m1, [r4 + 7 * 16] ; [13]
pmulhrsw m6, m7
mova m3, m1
pmaddubsw m3, [r3 - 2 * 16] ; [22]
pmulhrsw m3, m7
packuswb m6, m3
pmaddubsw m1, [r3 + 7 * 16] ; [31]
pmulhrsw m1, m7
palignr m2, m0, 4 ; [11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3]
pmaddubsw m2, [r4 + 2 * 16] ; [8]
pmulhrsw m2, m7
packuswb m1, m2
jmp mangle(private_prefix %+ _ %+ intra_pred_ang8_3 %+ SUFFIX %+ .transpose8x8)
cglobal intra_pred_ang8_8, 3,5,8
lea r4, [r2 + 1]
add r2, 17
cmp r3m, byte 28
cmove r2, r4
lea r3, [ang_table + 23 * 16]
lea r4, [ang_table + 8 * 16]
mova m7, [pw_1024]
movu m0, [r2] ; [16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
palignr m1, m0, 1 ; [x 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
punpckhbw m2, m0, m1 ; [x 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m0, m1 ; [9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
palignr m2, m0, 2 ; [10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2]
pmaddubsw m4, m0, [r4 - 3 * 16] ; [5]
pmulhrsw m4, m7
pmaddubsw m3, m0, [r4 + 2 * 16] ; [10]
pmulhrsw m3, m7
packuswb m4, m3
pmaddubsw m5, m0, [r3 - 8 * 16] ; [15]
pmulhrsw m5, m7
pmaddubsw m6, m0, [r3 - 3 * 16] ; [20]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m0, [r3 + 2 * 16] ; [25]
pmulhrsw m6, m7
pmaddubsw m0, [r3 + 7 * 16] ; [30]
pmulhrsw m0, m7
packuswb m6, m0
pmaddubsw m1, m2, [r4 - 5 * 16] ; [3]
pmulhrsw m1, m7
pmaddubsw m2, [r4] ; [8]
pmulhrsw m2, m7
packuswb m1, m2
jmp mangle(private_prefix %+ _ %+ intra_pred_ang8_3 %+ SUFFIX %+ .transpose8x8)
cglobal intra_pred_ang8_9, 3,5,8
lea r4, [r2 + 1]
add r2, 17
cmp r3m, byte 27
cmove r2, r4
lea r3, [ang_table + 10 * 16]
mova m7, [pw_1024]
movu m0, [r2] ; [16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
palignr m1, m0, 1 ; [x 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
punpcklbw m0, m1 ; [9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
pmaddubsw m4, m0, [r3 - 8 * 16] ; [2]
pmulhrsw m4, m7
pmaddubsw m3, m0, [r3 - 6 * 16] ; [4]
pmulhrsw m3, m7
packuswb m4, m3
pmaddubsw m5, m0, [r3 - 4 * 16] ; [6]
pmulhrsw m5, m7
pmaddubsw m6, m0, [r3 - 2 * 16] ; [8]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m0, [r3] ; [10]
pmulhrsw m6, m7
pmaddubsw m2, m0, [r3 + 2 * 16] ; [12]
pmulhrsw m2, m7
packuswb m6, m2
pmaddubsw m1, m0, [r3 + 4 * 16] ; [14]
pmulhrsw m1, m7
pmaddubsw m0, [r3 + 6 * 16] ; [16]
pmulhrsw m0, m7
packuswb m1, m0
jmp mangle(private_prefix %+ _ %+ intra_pred_ang8_3 %+ SUFFIX %+ .transpose8x8)
cglobal intra_pred_ang8_10, 3,6,5
movh m0, [r2 + 17]
mova m4, [pb_unpackbq]
palignr m1, m0, 2
pshufb m1, m4
palignr m2, m0, 4
pshufb m2, m4
palignr m3, m0, 6
pshufb m3, m4
pshufb m0, m4
lea r5, [r1 * 3]
movhps [r0 + r1], m0
movh [r0 + r1 * 2], m1
movhps [r0 + r5], m1
lea r3, [r0 + r1 * 4]
movh [r3], m2
movhps [r3 + r1], m2
movh [r3 + r1 * 2], m3
movhps [r3 + r5], m3
; filter
cmp r4m, byte 0
jz .quit
pmovzxbw m0, m0
movu m1, [r2]
palignr m2, m1, 1
pshufb m1, m4
pmovzxbw m1, m1
pmovzxbw m2, m2
psubw m2, m1
psraw m2, 1
paddw m0, m2
packuswb m0, m0
.quit:
movh [r0], m0
RET
cglobal intra_pred_ang8_26, 3,6,3
movu m2, [r2]
palignr m0, m2, 1
lea r5, [r1 * 3]
movh [r0], m0
movh [r0 + r1], m0
movh [r0 + r1 * 2], m0
movh [r0 + r5], m0
lea r3, [r0 + r1 * 4]
movh [r3], m0
movh [r3 + r1], m0
movh [r3 + r1 * 2], m0
movh [r3 + r5], m0
; filter
cmp r4m, byte 0
jz .quit
pshufb m2, [pb_unpackbq]
movhlps m1, m2
pmovzxbw m2, m2
movu m0, [r2 + 17]
pmovzxbw m1, m1
pmovzxbw m0, m0
psubw m0, m2
psraw m0, 1
paddw m1, m0
packuswb m1, m1
pextrb [r0], m1, 0
pextrb [r0 + r1], m1, 1
pextrb [r0 + r1 * 2], m1, 2
pextrb [r0 + r5], m1, 3
pextrb [r3], m1, 4
pextrb [r3 + r1], m1, 5
pextrb [r3 + r1 * 2], m1, 6
pextrb [r3 + r5], m1, 7
.quit:
RET
cglobal intra_pred_ang8_11, 3,5,8
xor r4, r4
cmp r3m, byte 25
mov r3, 16
cmove r3, r4
movu m0, [r2 + r3] ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0]
pinsrb m0, [r2], 0
palignr m1, m0, 1 ; [x 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
punpcklbw m0, m1 ; [8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0]
lea r3, [ang_table + 23 * 16]
mova m7, [pw_1024]
pmaddubsw m4, m0, [r3 + 7 * 16] ; [30]
pmulhrsw m4, m7
pmaddubsw m3, m0, [r3 + 5 * 16] ; [28]
pmulhrsw m3, m7
packuswb m4, m3
pmaddubsw m5, m0, [r3 + 3 * 16] ; [26]
pmulhrsw m5, m7
pmaddubsw m6, m0, [r3 + 1 * 16] ; [24]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m0, [r3 - 1 * 16] ; [22]
pmulhrsw m6, m7
pmaddubsw m2, m0, [r3 - 3 * 16] ; [20]
pmulhrsw m2, m7
packuswb m6, m2
pmaddubsw m1, m0, [r3 - 5 * 16] ; [18]
pmulhrsw m1, m7
pmaddubsw m0, [r3 - 7 * 16] ; [16]
pmulhrsw m0, m7
packuswb m1, m0
jmp mangle(private_prefix %+ _ %+ intra_pred_ang8_3 %+ SUFFIX %+ .transpose8x8)
cglobal intra_pred_ang8_12, 3,5,8
xor r4, r4
cmp r3m, byte 24
mov r3, 16
jz .next
xchg r3, r4
.next:
movu m1, [r2 + r4] ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0]
pinsrb m1, [r2], 0
pslldq m0, m1, 1 ; [14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a]
pinsrb m0, [r2 + r3 + 6], 0
lea r4, [ang_table + 22 * 16]
mova m7, [pw_1024]
punpckhbw m2, m0, m1 ; [15 14 14 13 13 12 12 11 11 10 10 9 9 8 8 7]
punpcklbw m0, m1 ; [7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 a]
palignr m2, m0, 2 ; [8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0]
pmaddubsw m4, m2, [r4 + 5 * 16] ; [27]
pmulhrsw m4, m7
pmaddubsw m3, m2, [r4] ; [22]
pmulhrsw m3, m7
packuswb m4, m3
pmaddubsw m1, m0, [r4 + 7 * 16] ; [29]
pmulhrsw m1, m7
pmaddubsw m0, [r4 + 2 * 16] ; [24]
pmulhrsw m0, m7
packuswb m1, m0
pmaddubsw m5, m2, [r4 - 5 * 16] ; [17]
pmulhrsw m5, m7
lea r4, [ang_table + 7 * 16]
pmaddubsw m6, m2, [r4 + 5 * 16] ; [12]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m2, [r4] ; [7]
pmulhrsw m6, m7
pmaddubsw m2, [r4 - 5 * 16] ; [2]
pmulhrsw m2, m7
packuswb m6, m2
jmp mangle(private_prefix %+ _ %+ intra_pred_ang8_3 %+ SUFFIX %+ .transpose8x8)
cglobal intra_pred_ang8_13, 4,5,8
xor r4, r4
cmp r3m, byte 23
mov r3, 16
jz .next
xchg r3, r4
.next:
movu m1, [r2 + r4] ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0]
pinsrb m1, [r2], 0
pslldq m1, 1 ; [14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a]
pinsrb m1, [r2 + r3 + 4], 0
pslldq m0, m1, 1 ; [13 12 11 10 9 8 7 6 5 4 3 2 1 0 a b]
pinsrb m0, [r2 + r3 + 7], 0
punpckhbw m5, m0, m1 ; [14 13 13 12 12 11 11 10 10 9 9 8 8 7 7 6]
punpcklbw m0, m1 ; [6 5 5 4 4 3 3 2 2 1 1 0 0 a a b]
palignr m1, m5, m0, 2 ; [7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 a]
palignr m5, m0, 4 ; [8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0]
lea r4, [ang_table + 24 * 16]
mova m7, [pw_1024]
pmaddubsw m4, m5, [r4 - 1 * 16] ; [23]
pmulhrsw m4, m7
pmaddubsw m6, m1, [r4 + 4 * 16] ; [28]
pmulhrsw m6, m7
pmaddubsw m0, [r4] ; [24]
pmulhrsw m0, m7
lea r4, [ang_table + 13 * 16]
pmaddubsw m3, m5, [r4 + 1 * 16] ; [14]
pmulhrsw m3, m7
packuswb m4, m3
pmaddubsw m5, [r4 - 8 * 16] ; [5]
pmulhrsw m5, m7
packuswb m5, m6
pmaddubsw m6, m1, [r4 + 6 * 16] ; [19]
pmulhrsw m6, m7
pmaddubsw m2, m1, [r4 - 3 * 16] ; [10]
pmulhrsw m2, m7
packuswb m6, m2
pmaddubsw m1, [r4 - 12 * 16] ; [1]
pmulhrsw m1, m7
packuswb m1, m0
jmp mangle(private_prefix %+ _ %+ intra_pred_ang8_3 %+ SUFFIX %+ .transpose8x8)
cglobal intra_pred_ang8_14, 4,5,8
xor r4, r4
cmp r3m, byte 22
mov r3, 16
jz .next
xchg r3, r4
.next:
movu m1, [r2 + r4 - 2] ; [13 12 11 10 9 8 7 6 5 4 3 2 1 0 a b]
pinsrb m1, [r2], 2
pinsrb m1, [r2 + r3 + 2], 1
pinsrb m1, [r2 + r3 + 5], 0
pslldq m0, m1, 1 ; [12 11 10 9 8 7 6 5 4 3 2 1 0 a b c]
pinsrb m0, [r2 + r3 + 7], 0
punpckhbw m2, m0, m1 ; [13 12 12 11 11 10 10 9 9 8 8 7 7 6 6 5]
punpcklbw m0, m1 ; [5 4 4 3 3 2 2 1 1 0 0 a a b b c]
palignr m1, m2, m0, 2 ; [6 5 5 4 4 3 3 2 2 1 1 0 0 a a b]
palignr m6, m2, m0, 4 ; [7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 a]
palignr m2, m0, 6 ; [8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0]
lea r4, [ang_table + 24 * 16]
mova m3, [pw_1024]
pmaddubsw m4, m2, [r4 - 5 * 16] ; [19]
pmulhrsw m4, m3
pmaddubsw m0, [r4] ; [24]
pmulhrsw m0, m3
pmaddubsw m5, m6, [r4 + 1 * 16] ; [25]
pmulhrsw m5, m3
lea r4, [ang_table + 12 * 16]
pmaddubsw m6, [r4] ; [12]
pmulhrsw m6, m3
packuswb m5, m6
pmaddubsw m6, m1, [r4 + 19 * 16] ; [31]
pmulhrsw m6, m3
pmaddubsw m2, [r4 - 6 * 16] ; [6]
pmulhrsw m2, m3
packuswb m4, m2
pmaddubsw m2, m1, [r4 + 6 * 16] ; [18]
pmulhrsw m2, m3
packuswb m6, m2
pmaddubsw m1, [r4 - 7 * 16] ; [5]
pmulhrsw m1, m3
packuswb m1, m0
jmp mangle(private_prefix %+ _ %+ intra_pred_ang8_3 %+ SUFFIX %+ .transpose8x8)
cglobal intra_pred_ang8_15, 4,5,8
xor r4, r4
cmp r3m, byte 21
mov r3, 16
jz .next
xchg r3, r4
.next:
movu m1, [r2 + r4] ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0]
pinsrb m1, [r2], 0
movu m2, [r2 + r3]
pshufb m2, [c_mode16_15]
palignr m1, m2, 13 ; [12 11 10 9 8 7 6 5 4 3 2 1 0 a b c]
pslldq m0, m1, 1 ; [11 10 9 8 7 6 5 4 3 2 1 0 a b c d]
pinsrb m0, [r2 + r3 + 8], 0
punpckhbw m4, m0, m1 ; [12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 4]
punpcklbw m0, m1 ; [4 3 3 2 2 1 1 0 0 a a b b c c d]
palignr m1, m4, m0, 2 ; [5 4 4 3 3 2 2 1 1 0 0 a a b b c]
palignr m6, m4, m0, 4 ; [6 5 5 4 4 3 3 2 2 1 1 0 0 a a b]
palignr m5, m4, m0, 6 ; [7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 a]
palignr m4, m0, 8 ; [8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0]
lea r4, [ang_table + 23 * 16]
mova m3, [pw_1024]
pmaddubsw m4, [r4 - 8 * 16] ; [15]
pmulhrsw m4, m3
pmaddubsw m2, m5, [r4 + 7 * 16] ; [30]
pmulhrsw m2, m3
packuswb m4, m2
pmaddubsw m5, [r4 - 10 * 16] ; [13]
pmulhrsw m5, m3
pmaddubsw m2, m6, [r4 + 5 * 16] ; [28]
pmulhrsw m2, m3
packuswb m5, m2
pmaddubsw m2, m1, [r4 + 3 * 16] ; [26]
pmulhrsw m2, m3
pmaddubsw m0, [r4 + 1 * 16] ; [24]
pmulhrsw m0, m3
lea r4, [ang_table + 11 * 16]
pmaddubsw m6, [r4] ; [11]
pmulhrsw m6, m3
packuswb m6, m2
pmaddubsw m1, [r4 - 2 * 16] ; [9]
pmulhrsw m1, m3
packuswb m1, m0
jmp mangle(private_prefix %+ _ %+ intra_pred_ang8_3 %+ SUFFIX %+ .transpose8x8)
cglobal intra_pred_ang8_16, 4,5,8
xor r4, r4
cmp r3m, byte 20
mov r3, 16
jz .next
xchg r3, r4
.next:
movu m1, [r2 + r4] ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0]
pinsrb m1, [r2], 0
movu m2, [r2 + r3]
pshufb m2, [c_mode16_16]
palignr m1, m2, 12 ; [11 10 9 8 7 6 5 4 3 2 1 0 a b c d]
pslldq m0, m1, 1 ; [10 9 8 7 6 5 4 3 2 1 0 a b c d e]
pinsrb m0, [r2 + r3 + 8], 0
punpckhbw m4, m0, m1 ; [11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3]
punpcklbw m0, m1 ; [3 2 2 1 1 0 0 a a b b c c d d e]
palignr m1, m4, m0, 2 ; [4 3 3 2 2 1 1 0 0 a a b b c c d]
palignr m6, m4, m0, 4 ; [5 4 4 3 3 2 2 1 1 0 0 a a b b c]
palignr m2, m4, m0, 6 ; [6 5 5 4 4 3 3 2 2 1 1 0 0 a a b]
palignr m5, m4, m0, 8 ; [7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 a]
palignr m4, m0, 10 ; [8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0]
lea r4, [ang_table + 22 * 16]
mova m7, [pw_1024]
pmaddubsw m3, m5, [r4] ; [22]
pmulhrsw m3, m7
pmaddubsw m0, [r4 + 2 * 16] ; [24]
pmulhrsw m0, m7
lea r4, [ang_table + 9 * 16]
pmaddubsw m4, [r4 + 2 * 16] ; [11]
pmulhrsw m4, m7
packuswb m4, m3
pmaddubsw m2, [r4 + 3 * 16] ; [12]
pmulhrsw m2, m7
pmaddubsw m5, [r4 - 8 * 16] ; [1]
pmulhrsw m5, m7
packuswb m5, m2
mova m2, m6
pmaddubsw m6, [r4 + 14 * 16] ; [23]
pmulhrsw m6, m7
pmaddubsw m2, [r4 - 7 * 16] ; [2]
pmulhrsw m2, m7
packuswb m6, m2
pmaddubsw m1, [r4 + 4 * 16] ; [13]
pmulhrsw m1, m7
packuswb m1, m0
jmp mangle(private_prefix %+ _ %+ intra_pred_ang8_3 %+ SUFFIX %+ .transpose8x8)
cglobal intra_pred_ang8_17, 4,5,8
xor r4, r4
cmp r3m, byte 19
mov r3, 16
jz .next
xchg r3, r4
.next:
movu m2, [r2 + r4] ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0]
pinsrb m2, [r2], 0
movu m1, [r2 + r3]
pshufb m1, [c_mode16_17]
palignr m2, m1, 11 ; [10 9 8 7 6 5 4 3 2 1 0 a b c d e]
pslldq m0, m2, 1 ; [9 8 7 6 5 4 3 2 1 0 a b c d e f]
pinsrb m0, [r2 + r3 + 7], 0
punpckhbw m1, m0, m2 ; [10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2]
punpcklbw m0, m2 ; [2 1 1 0 0 a a b b c c d d e e f]
palignr m5, m1, m0, 8 ; [6 5 5 4 4 3 3 2 2 1 1 0 0 a a b]
palignr m2, m1, m0, 10 ; [7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 a]
palignr m4, m1, m0, 12 ; [8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0]
lea r4, [ang_table + 17 * 16]
mova m3, [pw_1024]
pmaddubsw m2, [r4 - 5 * 16] ; [12]
pmulhrsw m2, m3
pmaddubsw m4, [r4 - 11 * 16] ; [6]
pmulhrsw m4, m3
packuswb m4, m2
pmaddubsw m5, [r4 + 1 * 16] ; [18]
pmulhrsw m5, m3
palignr m2, m1, m0, 6 ; [5 4 4 3 3 2 2 1 1 0 0 a a b b c]
pmaddubsw m2, [r4 + 7 * 16] ; [24]
pmulhrsw m2, m3
packuswb m5, m2
palignr m6, m1, m0, 4 ; [4 3 3 2 2 1 1 0 0 a a b b c c d]
mova m2, m6
pmaddubsw m6, [r4 + 13 * 16] ; [30]
pmulhrsw m6, m3
pmaddubsw m2, [r4 - 13 * 16] ; [4]
pmulhrsw m2, m3
packuswb m6, m2
palignr m1, m0, 2 ; [3 2 2 1 1 0 0 a a b b c c d d e]
pmaddubsw m1, [r4 - 7 * 16] ; [10]
pmulhrsw m1, m3
pmaddubsw m0, [r4 - 1 * 16] ; [16]
pmulhrsw m0, m3
packuswb m1, m0
jmp mangle(private_prefix %+ _ %+ intra_pred_ang8_3 %+ SUFFIX %+ .transpose8x8)
cglobal intra_pred_ang8_18, 4,4,1
movu m0, [r2 + 16]
pinsrb m0, [r2], 0
pshufb m0, [pb_swap8]
movhps m0, [r2 + 1]
lea r2, [r0 + r1 * 4]
lea r3, [r1 * 3]
movh [r2 + r3], m0
psrldq m0, 1
movh [r2 + r1 * 2], m0
psrldq m0, 1
movh [r2 + r1], m0
psrldq m0, 1
movh [r2], m0
psrldq m0, 1
movh [r0 + r3], m0
psrldq m0, 1
movh [r0 + r1 * 2], m0
psrldq m0, 1
movh [r0 + r1], m0
psrldq m0, 1
movh [r0], m0
RET
%macro TRANSPOSE_STORE_8x8 6
%if %2 == 1
; transpose 8x8 and then store, used by angle BLOCK_16x16 and BLOCK_32x32
punpckhbw m0, %3, %4
punpcklbw %3, %4
punpckhbw %4, %3, m0
punpcklbw %3, m0
punpckhbw m0, %5, m1
punpcklbw %5, %6
punpckhbw %6, %5, m0
punpcklbw %5, m0
punpckhdq m0, %3, %5
punpckldq %3, %5
punpckldq %5, %4, %6
punpckhdq %4, %6
movh [r0 + + %1 * 8], %3
movhps [r0 + r1 + %1 * 8], %3
movh [r0 + r1*2 + %1 * 8], m0
movhps [r0 + r5 + %1 * 8], m0
movh [r6 + %1 * 8], %5
movhps [r6 + r1 + %1 * 8], %5
movh [r6 + r1*2 + %1 * 8], %4
movhps [r6 + r5 + %1 * 8], %4
%else
; store 8x8, used by angle BLOCK_16x16 and BLOCK_32x32
movh [r0 ], %3
movhps [r0 + r1 ], %3
movh [r0 + r1 * 2], %4
movhps [r0 + r5 ], %4
lea r0, [r0 + r1 * 4]
movh [r0 ], %5
movhps [r0 + r1 ], %5
movh [r0 + r1 * 2], %6
movhps [r0 + r5 ], %6
lea r0, [r0 + r1 * 4]
%endif
%endmacro
;------------------------------------------------------------------------------------------
; void intraPredAng16(pixel* dst, intptr_t dstStride, pixel* src, int dirMode, int bFilter)
;------------------------------------------------------------------------------------------
INIT_XMM ssse3
cglobal intra_pred_ang16_2, 3,5,3
lea r4, [r2 + 2]
add r2, 34
cmp r3m, byte 34
cmove r2, r4
movu m0, [r2]
movu m1, [r2 + 16]
movu [r0], m0
palignr m2, m1, m0, 1
movu [r0 + r1], m2
lea r0, [r0 + r1 * 2]
palignr m2, m1, m0, 2
movu [r0], m2
palignr m2, m1, m0, 3
movu [r0 + r1], m2
lea r0, [r0 + r1 * 2]
palignr m2, m1, m0, 4
movu [r0], m2
palignr m2, m1, m0, 5
movu [r0 + r1], m2
lea r0, [r0 + r1 * 2]
palignr m2, m1, m0, 6
movu [r0], m2
palignr m2, m1, m0, 7
movu [r0 + r1], m2
lea r0, [r0 + r1 * 2]
palignr m2, m1, m0, 8
movu [r0], m2
palignr m2, m1, m0, 9
movu [r0 + r1], m2
lea r0, [r0 + r1 * 2]
palignr m2, m1, m0, 10
movu [r0], m2
palignr m2, m1, m0, 11
movu [r0 + r1], m2
lea r0, [r0 + r1 * 2]
palignr m2, m1, m0, 12
movu [r0], m2
palignr m2, m1, m0, 13
movu [r0 + r1], m2
lea r0, [r0 + r1 * 2]
palignr m2, m1, m0, 14
movu [r0], m2
palignr m2, m1, m0, 15
movu [r0 + r1], m2
RET
INIT_XMM sse4
cglobal intra_pred_ang16_3, 3,7,8
add r2, 32
lea r3, [ang_table + 16 * 16]
mov r4d, 2
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0 + r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
.loop:
movu m0, [r2 + 1]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
palignr m1, m2, m0, 2
pmaddubsw m4, m0, [r3 + 10 * 16] ; [26]
pmulhrsw m4, m7
pmaddubsw m1, [r3 + 4 * 16] ; [20]
pmulhrsw m1, m7
packuswb m4, m1
palignr m5, m2, m0, 4
pmaddubsw m5, [r3 - 2 * 16] ; [14]
pmulhrsw m5, m7
palignr m6, m2, m0, 6
pmaddubsw m6, [r3 - 8 * 16] ; [ 8]
pmulhrsw m6, m7
packuswb m5, m6
palignr m1, m2, m0, 8
pmaddubsw m6, m1, [r3 - 14 * 16] ; [ 2]
pmulhrsw m6, m7
pmaddubsw m1, [r3 + 12 * 16] ; [28]
pmulhrsw m1, m7
packuswb m6, m1
palignr m1, m2, m0, 10
pmaddubsw m1, [r3 + 6 * 16] ; [22]
pmulhrsw m1, m7
palignr m2, m0, 12
pmaddubsw m2, [r3] ; [16]
pmulhrsw m2, m7
packuswb m1, m2
TRANSPOSE_STORE_8x8 0, 1, m4, m5, m6, m1
movu m0, [r2 + 8]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
palignr m5, m2, m0, 2
pmaddubsw m4, m0, [r3 - 6 * 16] ; [10]
pmulhrsw m4, m7
pmaddubsw m1, m5, [r3 - 12 * 16] ; [04]
pmulhrsw m1, m7
packuswb m4, m1
pmaddubsw m5, [r3 + 14 * 16] ; [30]
pmulhrsw m5, m7
palignr m6, m2, m0, 4
pmaddubsw m6, [r3 + 8 * 16] ; [24]
pmulhrsw m6, m7
packuswb m5, m6
palignr m1, m2, m0, 6
pmaddubsw m6, m1, [r3 + 2 * 16] ; [18]
pmulhrsw m6, m7
palignr m1, m2, m0, 8
pmaddubsw m1, [r3 - 4 * 16] ; [12]
pmulhrsw m1, m7
packuswb m6, m1
palignr m1, m2, m0, 10
pmaddubsw m1, [r3 - 10 * 16] ; [06]
pmulhrsw m1, m7
packuswb m1, m1
movhps m1, [r2 + 14] ; [00]
TRANSPOSE_STORE_8x8 1, 1, m4, m5, m6, m1
lea r0, [r6 + r1 * 4]
lea r6, [r6 + r1 * 8]
add r2, 8
dec r4
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang16_33, 3,7,8
lea r3, [ang_table + 16 * 16]
mov r4d, 2
lea r5, [r1 * 3]
mov r6, r0
mova m7, [pw_1024]
.loop:
movu m0, [r2 + 1]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
palignr m1, m2, m0, 2
pmaddubsw m4, m0, [r3 + 10 * 16] ; [26]
pmulhrsw m4, m7
pmaddubsw m1, [r3 + 4 * 16] ; [20]
pmulhrsw m1, m7
packuswb m4, m1
palignr m5, m2, m0, 4
pmaddubsw m5, [r3 - 2 * 16] ; [14]
pmulhrsw m5, m7
palignr m6, m2, m0, 6
pmaddubsw m6, [r3 - 8 * 16] ; [ 8]
pmulhrsw m6, m7
packuswb m5, m6
palignr m1, m2, m0, 8
pmaddubsw m6, m1, [r3 - 14 * 16] ; [ 2]
pmulhrsw m6, m7
pmaddubsw m1, [r3 + 12 * 16] ; [28]
pmulhrsw m1, m7
packuswb m6, m1
palignr m1, m2, m0, 10
pmaddubsw m1, [r3 + 6 * 16] ; [22]
pmulhrsw m1, m7
palignr m2, m0, 12
pmaddubsw m2, [r3] ; [16]
pmulhrsw m2, m7
packuswb m1, m2
TRANSPOSE_STORE_8x8 0, 0, m4, m5, m6, m1
movu m0, [r2 + 8]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
palignr m5, m2, m0, 2
pmaddubsw m4, m0, [r3 - 6 * 16] ; [10]
pmulhrsw m4, m7
pmaddubsw m1, m5, [r3 - 12 * 16] ; [04]
pmulhrsw m1, m7
packuswb m4, m1
pmaddubsw m5, [r3 + 14 * 16] ; [30]
pmulhrsw m5, m7
palignr m6, m2, m0, 4
pmaddubsw m6, [r3 + 8 * 16] ; [24]
pmulhrsw m6, m7
packuswb m5, m6
palignr m1, m2, m0, 6
pmaddubsw m6, m1, [r3 + 2 * 16] ; [18]
pmulhrsw m6, m7
palignr m1, m2, m0, 8
pmaddubsw m1, [r3 - 4 * 16] ; [12]
pmulhrsw m1, m7
packuswb m6, m1
palignr m1, m2, m0, 10
pmaddubsw m1, [r3 - 10 * 16] ; [06]
pmulhrsw m1, m7
packuswb m1, m1
movh m2, [r2 + 14] ; [00]
movh [r0 ], m4
movhps [r0 + r1 ], m4
movh [r0 + r1 * 2], m5
movhps [r0 + r5 ], m5
lea r0, [r0 + r1 * 4]
movh [r0 ], m6
movhps [r0 + r1 ], m6
movh [r0 + r1 * 2], m1
movh [r0 + r5 ], m2
lea r0, [r6 + 8]
add r2, 8
dec r4
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang16_4, 3,7,8
add r2, 32
lea r3, [ang_table + 16 * 16]
mov r4d, 2
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0 + r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
.loop:
movu m0, [r2 + 1]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
palignr m1, m2, m0, 2
mova m5, m1
pmaddubsw m4, m0, [r3 + 5 * 16] ; [21]
pmulhrsw m4, m7
pmaddubsw m1, [r3 - 6 * 16] ; [10]
pmulhrsw m1, m7
packuswb m4, m1
pmaddubsw m5, [r3 + 15 * 16] ; [31]
pmulhrsw m5, m7
palignr m6, m2, m0, 4
pmaddubsw m6, [r3 + 4 * 16] ; [ 20]
pmulhrsw m6, m7
packuswb m5, m6
palignr m1, m2, m0, 6
pmaddubsw m6, m1, [r3 - 7 * 16] ; [ 9]
pmulhrsw m6, m7
pmaddubsw m1, [r3 + 14 * 16] ; [30]
pmulhrsw m1, m7
packuswb m6, m1
palignr m1, m2, m0, 8
pmaddubsw m1, [r3 + 3 * 16] ; [19]
pmulhrsw m1, m7
palignr m2, m0, 10
pmaddubsw m3, m2, [r3 - 8 * 16] ; [8]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 0, 1, m4, m5, m6, m1
pmaddubsw m4, m2, [r3 + 13 * 16] ; [29]
pmulhrsw m4, m7
movu m0, [r2 + 6]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
palignr m1, m2, m0, 2
pmaddubsw m1, [r3 + 2 * 16] ; [18]
pmulhrsw m1, m7
packuswb m4, m1
palignr m5, m2, m0, 4
mova m6, m5
pmaddubsw m5, [r3 - 9 * 16] ; [07]
pmulhrsw m5, m7
pmaddubsw m6, [r3 + 12 * 16] ; [28]
pmulhrsw m6, m7
packuswb m5, m6
palignr m6, m2, m0, 6
pmaddubsw m6, [r3 + 16] ; [17]
pmulhrsw m6, m7
palignr m1, m2, m0, 8
palignr m2, m0, 10
pmaddubsw m3, m1, [r3 - 10 * 16] ; [06]
pmulhrsw m3, m7
packuswb m6, m3
pmaddubsw m1, [r3 + 11 * 16] ; [27]
pmulhrsw m1, m7
pmaddubsw m2, [r3] ; [16]
pmulhrsw m2, m7
packuswb m1, m2
TRANSPOSE_STORE_8x8 1, 1, m4, m5, m6, m1
lea r0, [r6 + r1 * 4]
lea r6, [r6 + r1 * 8]
add r2, 8
dec r4
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang16_32, 3,7,8
lea r3, [ang_table + 16 * 16]
mov r4d, 2
lea r5, [r1 * 3] ; r5 -> 3 * stride
mov r6, r0
mova m7, [pw_1024]
.loop:
movu m0, [r2 + 1]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
palignr m1, m2, m0, 2
mova m5, m1
pmaddubsw m4, m0, [r3 + 5 * 16] ; [21]
pmulhrsw m4, m7
pmaddubsw m1, [r3 - 6 * 16] ; [10]
pmulhrsw m1, m7
packuswb m4, m1
pmaddubsw m5, [r3 + 15 * 16] ; [31]
pmulhrsw m5, m7
palignr m6, m2, m0, 4
pmaddubsw m6, [r3 + 4 * 16] ; [ 20]
pmulhrsw m6, m7
packuswb m5, m6
palignr m1, m2, m0, 6
pmaddubsw m6, m1, [r3 - 7 * 16] ; [ 9]
pmulhrsw m6, m7
pmaddubsw m1, [r3 + 14 * 16] ; [30]
pmulhrsw m1, m7
packuswb m6, m1
palignr m1, m2, m0, 8
pmaddubsw m1, [r3 + 3 * 16] ; [19]
pmulhrsw m1, m7
palignr m2, m0, 10
pmaddubsw m3, m2, [r3 - 8 * 16] ; [8]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 0, 0, m4, m5, m6, m1
pmaddubsw m4, m2, [r3 + 13 * 16] ; [29]
pmulhrsw m4, m7
movu m0, [r2 + 6]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
palignr m1, m2, m0, 2
pmaddubsw m1, [r3 + 2 * 16] ; [18]
pmulhrsw m1, m7
packuswb m4, m1
palignr m5, m2, m0, 4
mova m6, m5
pmaddubsw m5, [r3 - 9 * 16] ; [07]
pmulhrsw m5, m7
pmaddubsw m6, [r3 + 12 * 16] ; [28]
pmulhrsw m6, m7
packuswb m5, m6
palignr m6, m2, m0, 6
pmaddubsw m6, [r3 + 16] ; [17]
pmulhrsw m6, m7
palignr m1, m2, m0, 8
palignr m2, m0, 10
pmaddubsw m3, m1, [r3 - 10 * 16] ; [06]
pmulhrsw m3, m7
packuswb m6, m3
pmaddubsw m1, [r3 + 11 * 16] ; [27]
pmulhrsw m1, m7
pmaddubsw m2, [r3] ; [16]
pmulhrsw m2, m7
packuswb m1, m2
TRANSPOSE_STORE_8x8 1, 0, m4, m5, m6, m1
lea r0, [r6 + 8]
add r2, 8
dec r4
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang16_5, 3,7,8
add r2, 32
lea r3, [ang_table + 16 * 16]
mov r4d, 2
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0 + r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
.loop:
movu m3, [r2 + 1] ;[16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
movu m1, [r2 + 2] ;[17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
punpckhbw m2, m3, m1 ;[17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m3, m1 ;[9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
palignr m5, m2, m3, 2
pmaddubsw m4, m3, [r3 + 16] ; [17]
pmulhrsw m4, m7
pmaddubsw m1, m5, [r3 - 14 * 16] ; [2]
pmulhrsw m1, m7
packuswb m4, m1
palignr m6, m2, m3, 4
pmaddubsw m5, [r3 + 3 * 16] ; [19]
pmulhrsw m5, m7
pmaddubsw m1, m6, [r3 - 12 * 16] ; [4]
pmulhrsw m1, m7
packuswb m5, m1
palignr m1, m2, m3, 6
pmaddubsw m6, [r3 + 5 * 16] ; [21]
pmulhrsw m6, m7
pmaddubsw m0, m1, [r3 - 10 * 16] ; [6]
pmulhrsw m0, m7
packuswb m6, m0
palignr m0, m2, m3, 8
pmaddubsw m1, [r3 + 7 * 16] ; [23]
pmulhrsw m1, m7
pmaddubsw m0, [r3 - 8 * 16] ; [8]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 1, m4, m5, m6, m1
palignr m4, m2, m3, 8
palignr m5, m2, m3, 10
pmaddubsw m4, [r3 + 9 * 16] ; [25]
pmulhrsw m4, m7
pmaddubsw m1, m5, [r3 - 6 * 16] ; [10]
pmulhrsw m1, m7
packuswb m4, m1
palignr m6, m2, m3, 12
pmaddubsw m5, [r3 + 11 * 16] ; [27]
pmulhrsw m5, m7
pmaddubsw m1, m6, [r3 - 4 * 16] ; [12]
pmulhrsw m1, m7
packuswb m5, m1
palignr m1, m2, m3, 14
pmaddubsw m6, [r3 + 13 * 16] ; [29]
pmulhrsw m6, m7
pmaddubsw m0, m1, [r3 - 2 * 16] ; [14]
pmulhrsw m0, m7
packuswb m6, m0
pmaddubsw m1, [r3 + 15 * 16] ; [31]
pmulhrsw m1, m7
pmaddubsw m2, [r3] ; [16]
pmulhrsw m2, m7
packuswb m1, m2
TRANSPOSE_STORE_8x8 1, 1, m4, m5, m6, m1
lea r0, [r6 + r1 * 4]
lea r6, [r6 + r1 * 8]
add r2, 8
dec r4
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang16_31, 3,7,8
lea r3, [ang_table + 16 * 16]
mov r4d, 2
lea r5, [r1 * 3] ; r5 -> 3 * stride
mov r6, r0
mova m7, [pw_1024]
.loop:
movu m3, [r2 + 1] ;[16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
movu m1, [r2 + 2] ;[17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
punpckhbw m2, m3, m1 ;[17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m3, m1 ;[9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
palignr m5, m2, m3, 2
pmaddubsw m4, m3, [r3 + 16] ; [17]
pmulhrsw m4, m7
pmaddubsw m1, m5, [r3 - 14 * 16] ; [2]
pmulhrsw m1, m7
packuswb m4, m1
palignr m6, m2, m3, 4
pmaddubsw m5, [r3 + 3 * 16] ; [19]
pmulhrsw m5, m7
pmaddubsw m1, m6, [r3 - 12 * 16] ; [4]
pmulhrsw m1, m7
packuswb m5, m1
palignr m1, m2, m3, 6
pmaddubsw m6, [r3 + 5 * 16] ; [21]
pmulhrsw m6, m7
pmaddubsw m0, m1, [r3 - 10 * 16] ; [6]
pmulhrsw m0, m7
packuswb m6, m0
palignr m0, m2, m3, 8
pmaddubsw m1, [r3 + 7 * 16] ; [23]
pmulhrsw m1, m7
pmaddubsw m0, [r3 - 8 * 16] ; [8]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 0, m4, m5, m6, m1
palignr m4, m2, m3, 8
palignr m5, m2, m3, 10
pmaddubsw m4, [r3 + 9 * 16] ; [25]
pmulhrsw m4, m7
pmaddubsw m1, m5, [r3 - 6 * 16] ; [10]
pmulhrsw m1, m7
packuswb m4, m1
palignr m6, m2, m3, 12
pmaddubsw m5, [r3 + 11 * 16] ; [27]
pmulhrsw m5, m7
pmaddubsw m1, m6, [r3 - 4 * 16] ; [12]
pmulhrsw m1, m7
packuswb m5, m1
palignr m1, m2, m3, 14
pmaddubsw m6, [r3 + 13 * 16] ; [29]
pmulhrsw m6, m7
pmaddubsw m0, m1, [r3 - 2 * 16] ; [14]
pmulhrsw m0, m7
packuswb m6, m0
pmaddubsw m1, [r3 + 15 * 16] ; [31]
pmulhrsw m1, m7
pmaddubsw m2, [r3] ; [16]
pmulhrsw m2, m7
packuswb m1, m2
TRANSPOSE_STORE_8x8 1, 0, m4, m5, m6, m1
lea r0, [r6 + 8]
add r2, 8
dec r4
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang16_6, 3,7,8
add r2, 32
lea r3, [ang_table + 16 * 16]
mov r4d, 2
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0 + r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
.loop:
movu m3, [r2 + 1] ;[16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
palignr m1, m3, 1 ;[x 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
punpckhbw m2, m3, m1 ;[x 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m3, m1 ;[9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
pmaddubsw m4, m3, [r3 - 3 * 16] ; [13]
pmulhrsw m4, m7
pmaddubsw m1, m3, [r3 + 10 * 16] ; [26]
pmulhrsw m1, m7
packuswb m4, m1
palignr m6, m2, m3, 2
pmaddubsw m5, m6, [r3 - 9 * 16] ; [7]
pmulhrsw m5, m7
pmaddubsw m6, [r3 + 4 * 16] ; [20]
pmulhrsw m6, m7
packuswb m5, m6
palignr m1, m2, m3, 4
pmaddubsw m6, m1, [r3 - 15 * 16] ; [1]
pmulhrsw m6, m7
pmaddubsw m0, m1, [r3 - 2 * 16] ; [14]
pmulhrsw m0, m7
packuswb m6, m0
palignr m0, m2, m3, 6
pmaddubsw m1, [r3 + 11 * 16] ; [27]
pmulhrsw m1, m7
pmaddubsw m0, [r3 - 8 * 16] ; [8]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 1, m4, m5, m6, m1
palignr m4, m2, m3, 6
palignr m6, m2, m3, 8
pmaddubsw m4, [r3 + 5 * 16] ; [21]
pmulhrsw m4, m7
pmaddubsw m1, m6, [r3 - 14 * 16] ; [2]
pmulhrsw m1, m7
packuswb m4, m1
pmaddubsw m5, m6, [r3 - 16] ; [15]
pmulhrsw m5, m7
pmaddubsw m6, [r3 + 12 * 16] ; [28]
pmulhrsw m6, m7
packuswb m5, m6
palignr m0, m2, m3, 10
pmaddubsw m6, m0, [r3 - 7 * 16] ; [9]
pmulhrsw m6, m7
pmaddubsw m0, [r3 + 6 * 16] ; [22]
pmulhrsw m0, m7
packuswb m6, m0
palignr m2, m3, 12
pmaddubsw m1, m2, [r3 - 13 * 16] ; [3]
pmulhrsw m1, m7
pmaddubsw m2, [r3] ; [16]
pmulhrsw m2, m7
packuswb m1, m2
TRANSPOSE_STORE_8x8 1, 1, m4, m5, m6, m1
lea r0, [r6 + r1 * 4]
lea r6, [r6 + r1 * 8]
add r2, 8
dec r4
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang16_30, 3,7,8
lea r3, [ang_table + 16 * 16]
mov r4d, 2
lea r5, [r1 * 3] ; r5 -> 3 * stride
mov r6, r0
mova m7, [pw_1024]
.loop:
movu m3, [r2 + 1] ;[16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
palignr m1, m3, 1 ;[x 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
punpckhbw m2, m3, m1 ;[x 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m3, m1 ;[9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
pmaddubsw m4, m3, [r3 - 3 * 16] ; [13]
pmulhrsw m4, m7
pmaddubsw m1, m3, [r3 + 10 * 16] ; [26]
pmulhrsw m1, m7
packuswb m4, m1
palignr m6, m2, m3, 2
pmaddubsw m5, m6, [r3 - 9 * 16] ; [7]
pmulhrsw m5, m7
pmaddubsw m6, [r3 + 4 * 16] ; [20]
pmulhrsw m6, m7
packuswb m5, m6
palignr m1, m2, m3, 4
pmaddubsw m6, m1, [r3 - 15 * 16] ; [1]
pmulhrsw m6, m7
pmaddubsw m0, m1, [r3 - 2 * 16] ; [14]
pmulhrsw m0, m7
packuswb m6, m0
palignr m0, m2, m3, 6
pmaddubsw m1, [r3 + 11 * 16] ; [27]
pmulhrsw m1, m7
pmaddubsw m0, [r3 - 8 * 16] ; [8]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 0, m4, m5, m6, m1
palignr m4, m2, m3, 6
palignr m6, m2, m3, 8
pmaddubsw m4, [r3 + 5 * 16] ; [21]
pmulhrsw m4, m7
pmaddubsw m1, m6, [r3 - 14 * 16] ; [2]
pmulhrsw m1, m7
packuswb m4, m1
pmaddubsw m5, m6, [r3 - 16] ; [15]
pmulhrsw m5, m7
pmaddubsw m6, [r3 + 12 * 16] ; [28]
pmulhrsw m6, m7
packuswb m5, m6
palignr m0, m2, m3, 10
pmaddubsw m6, m0, [r3 - 7 * 16] ; [9]
pmulhrsw m6, m7
pmaddubsw m0, [r3 + 6 * 16] ; [22]
pmulhrsw m0, m7
packuswb m6, m0
palignr m2, m3, 12
pmaddubsw m1, m2, [r3 - 13 * 16] ; [3]
pmulhrsw m1, m7
pmaddubsw m2, [r3] ; [16]
pmulhrsw m2, m7
packuswb m1, m2
TRANSPOSE_STORE_8x8 1, 0, m4, m5, m6, m1
lea r0, [r6 + 8]
add r2, 8
dec r4
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang16_7, 3,7,8
add r2, 32
lea r3, [ang_table + 16 * 16]
mov r4d, 2
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0 + r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
.loop:
movu m3, [r2 + 1] ;[16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
palignr m1, m3, 1 ;[x 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
punpckhbw m2, m3, m1 ;[x 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m3, m1 ;[9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
pmaddubsw m4, m3, [r3 - 7 * 16] ; [9]
pmulhrsw m4, m7
pmaddubsw m0, m3, [r3 + 2 * 16] ; [18]
pmulhrsw m0, m7
packuswb m4, m0
palignr m1, m2, m3, 2
pmaddubsw m5, m3, [r3 + 11 * 16] ; [27]
pmulhrsw m5, m7
pmaddubsw m6, m1, [r3 - 12 * 16] ; [4]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m1, [r3 - 3 * 16] ; [13]
pmulhrsw m6, m7
pmaddubsw m0, m1, [r3 + 6 * 16] ; [22]
pmulhrsw m0, m7
packuswb m6, m0
palignr m0, m2, m3, 4
pmaddubsw m1, [r3 + 15 * 16] ; [31]
pmulhrsw m1, m7
pmaddubsw m0, [r3 - 8 * 16] ; [8]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 1, m4, m5, m6, m1
palignr m1, m2, m3, 4
pmaddubsw m4, m1, [r3 + 16] ; [17]
pmulhrsw m4, m7
pmaddubsw m1, [r3 + 10 * 16] ; [26]
pmulhrsw m1, m7
packuswb m4, m1
palignr m0, m2, m3, 6
pmaddubsw m5, m0, [r3 - 13 * 16] ; [03]
pmulhrsw m5, m7
pmaddubsw m6, m0, [r3 - 4 * 16] ; [12]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m0, [r3 + 5 * 16] ; [21]
pmulhrsw m6, m7
pmaddubsw m0, [r3 + 14 * 16] ; [30]
pmulhrsw m0, m7
packuswb m6, m0
palignr m2, m3, 8
pmaddubsw m1, m2, [r3 - 9 * 16] ; [07]
pmulhrsw m1, m7
pmaddubsw m2, [r3] ; [16]
pmulhrsw m2, m7
packuswb m1, m2
TRANSPOSE_STORE_8x8 1, 1, m4, m5, m6, m1
lea r0, [r6 + r1 * 4]
lea r6, [r6 + r1 * 8]
add r2, 8
dec r4
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang16_29, 3,7,8
lea r3, [ang_table + 16 * 16]
mov r4d, 2
lea r5, [r1 * 3] ; r5 -> 3 * stride
mov r6, r0
mova m7, [pw_1024]
.loop:
movu m3, [r2 + 1] ;[16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
palignr m1, m3, 1 ;[x 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
punpckhbw m2, m3, m1 ;[x 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m3, m1 ;[9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
pmaddubsw m4, m3, [r3 - 7 * 16] ; [9]
pmulhrsw m4, m7
pmaddubsw m0, m3, [r3 + 2 * 16] ; [18]
pmulhrsw m0, m7
packuswb m4, m0
palignr m1, m2, m3, 2
pmaddubsw m5, m3, [r3 + 11 * 16] ; [27]
pmulhrsw m5, m7
pmaddubsw m6, m1, [r3 - 12 * 16] ; [4]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m1, [r3 - 3 * 16] ; [13]
pmulhrsw m6, m7
pmaddubsw m0, m1, [r3 + 6 * 16] ; [22]
pmulhrsw m0, m7
packuswb m6, m0
palignr m0, m2, m3, 4
pmaddubsw m1, [r3 + 15 * 16] ; [31]
pmulhrsw m1, m7
pmaddubsw m0, [r3 - 8 * 16] ; [8]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 0, m4, m5, m6, m1
palignr m1, m2, m3, 4
pmaddubsw m4, m1, [r3 + 16] ; [17]
pmulhrsw m4, m7
pmaddubsw m1, [r3 + 10 * 16] ; [26]
pmulhrsw m1, m7
packuswb m4, m1
palignr m0, m2, m3, 6
pmaddubsw m5, m0, [r3 - 13 * 16] ; [03]
pmulhrsw m5, m7
pmaddubsw m6, m0, [r3 - 4 * 16] ; [12]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m0, [r3 + 5 * 16] ; [21]
pmulhrsw m6, m7
pmaddubsw m0, [r3 + 14 * 16] ; [30]
pmulhrsw m0, m7
packuswb m6, m0
palignr m2, m3, 8
pmaddubsw m1, m2, [r3 - 9 * 16] ; [07]
pmulhrsw m1, m7
pmaddubsw m2, [r3] ; [16]
pmulhrsw m2, m7
packuswb m1, m2
TRANSPOSE_STORE_8x8 1, 0, m4, m5, m6, m1
lea r0, [r6 + 8]
add r2, 8
dec r4
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang16_8, 3,7,8
add r2, 32
lea r3, [ang_table + 16 * 16]
mov r4d, 2
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0 + r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
.loop:
movu m1, [r2 + 1] ;[16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
palignr m3, m1, 1 ;[x 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
punpckhbw m0, m1, m3 ;[x 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m1, m3 ;[9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
pmaddubsw m4, m1, [r3 - 11 * 16] ; [5]
pmulhrsw m4, m7
pmaddubsw m2, m1, [r3 - 6 * 16] ; [10]
pmulhrsw m2, m7
packuswb m4, m2
pmaddubsw m5, m1, [r3 - 1 * 16] ; [15]
pmulhrsw m5, m7
pmaddubsw m6, m1, [r3 + 4 * 16] ; [20]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m1, [r3 + 9 * 16] ; [25]
pmulhrsw m6, m7
pmaddubsw m2, m1, [r3 + 14 * 16] ; [30]
pmulhrsw m2, m7
packuswb m6, m2
palignr m2, m0, m1, 2
palignr m3, m0, m1, 4
pmaddubsw m1, m2, [r3 - 13 * 16] ; [3]
pmulhrsw m1, m7
pmaddubsw m0, m2, [r3 - 8 * 16] ; [8]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 1, m4, m5, m6, m1
pmaddubsw m4, m2, [r3 - 3 * 16] ; [13]
pmulhrsw m4, m7
pmaddubsw m5, m2, [r3 + 2 * 16] ; [18]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m2, [r3 + 7 * 16] ; [23]
pmulhrsw m5, m7
pmaddubsw m2, [r3 + 12 * 16] ; [28]
pmulhrsw m2, m7
packuswb m5, m2
pmaddubsw m6, m3, [r3 - 15 * 16] ; [01]
pmulhrsw m6, m7
pmaddubsw m1, m3, [r3 - 10 * 16] ; [06]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m1, m3, [r3 - 5 * 16] ; [11]
pmulhrsw m1, m7
pmaddubsw m3, [r3] ; [16]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 1, 1, m4, m5, m6, m1
lea r0, [r6 + r1 * 4]
lea r6, [r6 + r1 * 8]
add r2, 8
dec r4
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang16_28, 3,7,8
lea r3, [ang_table + 16 * 16]
mov r4d, 2
lea r5, [r1 * 3] ; r5 -> 3 * stride
mov r6, r0
mova m7, [pw_1024]
.loop:
movu m1, [r2 + 1] ;[16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
palignr m3, m1, 1 ;[x 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
punpckhbw m0, m1, m3 ;[x 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m1, m3 ;[9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
pmaddubsw m4, m1, [r3 - 11 * 16] ; [5]
pmulhrsw m4, m7
pmaddubsw m2, m1, [r3 - 6 * 16] ; [10]
pmulhrsw m2, m7
packuswb m4, m2
pmaddubsw m5, m1, [r3 - 1 * 16] ; [15]
pmulhrsw m5, m7
pmaddubsw m6, m1, [r3 + 4 * 16] ; [20]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m1, [r3 + 9 * 16] ; [25]
pmulhrsw m6, m7
pmaddubsw m2, m1, [r3 + 14 * 16] ; [30]
pmulhrsw m2, m7
packuswb m6, m2
palignr m2, m0, m1, 2
palignr m3, m0, m1, 4
pmaddubsw m1, m2, [r3 - 13 * 16] ; [3]
pmulhrsw m1, m7
pmaddubsw m0, m2, [r3 - 8 * 16] ; [8]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 0, m4, m5, m6, m1
pmaddubsw m4, m2, [r3 - 3 * 16] ; [13]
pmulhrsw m4, m7
pmaddubsw m5, m2, [r3 + 2 * 16] ; [18]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m2, [r3 + 7 * 16] ; [23]
pmulhrsw m5, m7
pmaddubsw m2, [r3 + 12 * 16] ; [28]
pmulhrsw m2, m7
packuswb m5, m2
pmaddubsw m6, m3, [r3 - 15 * 16] ; [01]
pmulhrsw m6, m7
pmaddubsw m1, m3, [r3 - 10 * 16] ; [06]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m1, m3, [r3 - 5 * 16] ; [11]
pmulhrsw m1, m7
pmaddubsw m3, [r3] ; [16]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 1, 0, m4, m5, m6, m1
lea r0, [r6 + 8]
add r2, 8
dec r4
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang16_9, 3,7,8
add r2, 32
lea r3, [ang_table + 16 * 16]
mov r4d, 2
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0 + r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
.loop:
movu m2, [r2 + 1] ;[16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
palignr m3, m2, 1 ;[x 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
punpcklbw m2, m3 ;[9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
pmaddubsw m4, m2, [r3 - 14 * 16] ; [2]
pmulhrsw m4, m7
pmaddubsw m0, m2, [r3 - 12 * 16] ; [4]
pmulhrsw m0, m7
packuswb m4, m0
pmaddubsw m5, m2, [r3 - 10 * 16] ; [6]
pmulhrsw m5, m7
pmaddubsw m6, m2, [r3 - 8 * 16] ; [8]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m2, [r3 - 6 * 16] ; [10]
pmulhrsw m6, m7
pmaddubsw m0, m2, [r3 - 4 * 16] ; [12]
pmulhrsw m0, m7
packuswb m6, m0
pmaddubsw m1, m2, [r3 - 2 * 16] ; [14]
pmulhrsw m1, m7
pmaddubsw m0, m2, [r3] ; [16]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 1, m4, m5, m6, m1
pmaddubsw m4, m2, [r3 + 2 * 16] ; [18]
pmulhrsw m4, m7
pmaddubsw m5, m2, [r3 + 4 * 16] ; [20]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m2, [r3 + 6 * 16] ; [22]
pmulhrsw m5, m7
pmaddubsw m6, m2, [r3 + 8 * 16] ; [24]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m2, [r3 + 10 * 16] ; [26]
pmulhrsw m6, m7
pmaddubsw m1, m2, [r3 + 12 * 16] ; [28]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m1, m2, [r3 + 14 * 16] ; [30]
pmulhrsw m1, m7
packuswb m1, m1
punpcklqdq m1, m3 ; [00]
TRANSPOSE_STORE_8x8 1, 1, m4, m5, m6, m1
lea r0, [r6 + r1 * 4]
lea r6, [r6 + r1 * 8]
add r2, 8
dec r4
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang16_27, 3,7,8
lea r3, [ang_table + 16 * 16]
mov r4d, 2
lea r5, [r1 * 3] ; r5 -> 3 * stride
mov r6, r0
mova m7, [pw_1024]
.loop:
movu m3, [r2 + 1] ;[16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
palignr m2, m3, 1 ;[x 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
punpcklbw m3, m2 ;[9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
pmaddubsw m4, m3, [r3 - 14 * 16] ; [2]
pmulhrsw m4, m7
pmaddubsw m0, m3, [r3 - 12 * 16] ; [4]
pmulhrsw m0, m7
packuswb m4, m0
pmaddubsw m5, m3, [r3 - 10 * 16] ; [6]
pmulhrsw m5, m7
pmaddubsw m6, m3, [r3 - 8 * 16] ; [8]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m3, [r3 - 6 * 16] ; [10]
pmulhrsw m6, m7
pmaddubsw m0, m3, [r3 - 4 * 16] ; [12]
pmulhrsw m0, m7
packuswb m6, m0
pmaddubsw m1, m3, [r3 - 2 * 16] ; [14]
pmulhrsw m1, m7
pmaddubsw m0, m3, [r3] ; [16]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 0, m4, m5, m6, m1
pmaddubsw m4, m3, [r3 + 2 * 16] ; [18]
pmulhrsw m4, m7
pmaddubsw m5, m3, [r3 + 4 * 16] ; [20]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r3 + 6 * 16] ; [22]
pmulhrsw m5, m7
pmaddubsw m6, m3, [r3 + 8 * 16] ; [24]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m3, [r3 + 10 * 16] ; [26]
pmulhrsw m6, m7
pmaddubsw m1, m3, [r3 + 12 * 16] ; [28]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m1, m3, [r3 + 14 * 16] ; [30]
pmulhrsw m1, m7
packuswb m1, m1
movh [r0 ], m4
movhps [r0 + r1 ], m4
movh [r0 + r1 * 2], m5
movhps [r0 + r5 ], m5
lea r0, [r0 + r1 * 4]
movh [r0 ], m6
movhps [r0 + r1 ], m6
movh [r0 + r1 * 2], m1
movh [r0 + r5 ], m2
lea r0, [r6 + 8]
add r2, 8
dec r4
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang16_10, 5,6,8
lea r5, [r1 * 3]
pxor m7, m7
movu m0, [r2 + 1 + 32]
palignr m1, m0, 1
pshufb m1, m7
palignr m2, m0, 2
pshufb m2, m7
palignr m3, m0, 3
pshufb m3, m7
palignr m4, m0, 4
pshufb m4, m7
palignr m5, m0, 5
pshufb m5, m7
palignr m6, m0, 6
pshufb m6, m7
movu [r0 + r1], m1
movu [r0 + r1 * 2], m2
movu [r0 + r5], m3
lea r3, [r0 + r1 * 4]
movu [r3], m4
movu [r3 + r1], m5
movu [r3 + r1 * 2], m6
palignr m1, m0, 7
pshufb m1, m7
movhlps m2, m0
pshufb m2, m7
palignr m3, m0, 9
pshufb m3, m7
palignr m4, m0, 10
pshufb m4, m7
palignr m5, m0, 11
pshufb m5, m7
palignr m6, m0, 12
pshufb m6, m7
movu [r3 + r5], m1
lea r3, [r3 + r1 * 4]
movu [r3], m2
movu [r3 + r1], m3
movu [r3 + r1 * 2], m4
movu [r3 + r5], m5
lea r3, [r3 + r1 * 4]
movu [r3], m6
palignr m1, m0, 13
pshufb m1, m7
palignr m2, m0, 14
pshufb m2, m7
palignr m3, m0, 15
pshufb m3, m7
pshufb m0, m7
movu [r3 + r1], m1
movu [r3 + r1 * 2], m2
movu [r3 + r5], m3
; filter
cmp r4w, byte 0
jz .quit
pmovzxbw m0, m0
mova m1, m0
movu m2, [r2]
movu m3, [r2 + 1]
pshufb m2, m7
pmovzxbw m2, m2
movhlps m4, m3
pmovzxbw m3, m3
pmovzxbw m4, m4
psubw m3, m2
psubw m4, m2
psraw m3, 1
psraw m4, 1
paddw m0, m3
paddw m1, m4
packuswb m0, m1
.quit:
movu [r0], m0
RET
INIT_XMM sse4
%if ARCH_X86_64 == 1
cglobal intra_pred_ang16_26, 3,8,5
mov r7, r4mp
%define bfilter r7w
%else
cglobal intra_pred_ang16_26, 5,7,5,0-4
%define bfilter dword[rsp]
mov bfilter, r4
%endif
movu m0, [r2 + 1]
lea r4, [r1 * 3]
lea r3, [r0 + r1 * 4]
lea r5, [r3 + r1 * 4]
lea r6, [r5 + r1 * 4]
movu [r0], m0
movu [r0 + r1], m0
movu [r0 + r1 * 2], m0
movu [r0 + r4], m0
movu [r3], m0
movu [r3 + r1], m0
movu [r3 + r1 * 2], m0
movu [r3 + r4], m0
movu [r5], m0
movu [r5 + r1], m0
movu [r5 + r1 * 2], m0
movu [r5 + r4], m0
movu [r6], m0
movu [r6 + r1], m0
movu [r6 + r1 * 2], m0
movu [r6 + r4], m0
; filter
cmp bfilter, byte 0
jz .quit
pxor m4, m4
pshufb m0, m4
pmovzxbw m0, m0
mova m1, m0
movu m2, [r2 + 32]
pinsrb m2, [r2], 0
movu m3, [r2 + 1 + 32]
pshufb m2, m4
pmovzxbw m2, m2
movhlps m4, m3
pmovzxbw m3, m3
pmovzxbw m4, m4
psubw m3, m2
psubw m4, m2
psraw m3, 1
psraw m4, 1
paddw m0, m3
paddw m1, m4
packuswb m0, m1
pextrb [r0], m0, 0
pextrb [r0 + r1], m0, 1
pextrb [r0 + r1 * 2], m0, 2
pextrb [r0 + r4], m0, 3
pextrb [r3], m0, 4
pextrb [r3 + r1], m0, 5
pextrb [r3 + r1 * 2], m0, 6
pextrb [r3 + r4], m0, 7
pextrb [r5], m0, 8
pextrb [r5 + r1], m0, 9
pextrb [r5 + r1 * 2], m0, 10
pextrb [r5 + r4], m0, 11
pextrb [r6], m0, 12
pextrb [r6 + r1], m0, 13
pextrb [r6 + r1 * 2], m0, 14
pextrb [r6 + r4], m0, 15
.quit:
RET
INIT_XMM sse4
cglobal intra_pred_ang16_11, 3,7,8
lea r3, [ang_table + 16 * 16]
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0 + r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
movu m3, [r2 + 32] ;[15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0]
pinsrb m3, [r2], 0
mova m2, m3
palignr m1, m3, 1 ;[15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
punpcklbw m3, m1 ;[8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0]
pmaddubsw m4, m3, [r3 + 14 * 16] ; [30]
pmulhrsw m4, m7
pmaddubsw m0, m3, [r3 + 12 * 16] ; [28]
pmulhrsw m0, m7
packuswb m4, m0
pmaddubsw m5, m3, [r3 + 10 * 16] ; [26]
pmulhrsw m5, m7
pmaddubsw m6, m3, [r3 + 8 * 16] ; [24]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m3, [r3 + 6 * 16] ; [22]
pmulhrsw m6, m7
pmaddubsw m0, m3, [r3 + 4 * 16] ; [20]
pmulhrsw m0, m7
packuswb m6, m0
pmaddubsw m1, m3, [r3 + 2 * 16] ; [18]
pmulhrsw m1, m7
pmaddubsw m0, m3, [r3] ; [16]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 1, m4, m5, m6, m1
pmaddubsw m4, m3, [r3 - 2 * 16] ; [14]
pmulhrsw m4, m7
pmaddubsw m5, m3, [r3 - 4 * 16] ; [12]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r3 - 6 * 16] ; [10]
pmulhrsw m5, m7
pmaddubsw m6, m3, [r3 - 8 * 16] ; [08]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m3, [r3 - 10 * 16] ; [06]
pmulhrsw m6, m7
pmaddubsw m1, m3, [r3 - 12 * 16] ; [04]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m1, m3, [r3 - 14 * 16] ; [02]
pmulhrsw m1, m7
packuswb m1, m1
punpcklqdq m1, m2 ;[00]
TRANSPOSE_STORE_8x8 1, 1, m4, m5, m6, m1
lea r0, [r6 + r1 * 4]
lea r6, [r6 + r1 * 8]
movu m3, [r2 + 40] ;[15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0]
mova m2, m3
palignr m1, m3, 1 ;[15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
punpcklbw m3, m1 ;[8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0]
pmaddubsw m4, m3, [r3 + 14 * 16] ; [30]
pmulhrsw m4, m7
pmaddubsw m0, m3, [r3 + 12 * 16] ; [28]
pmulhrsw m0, m7
packuswb m4, m0
pmaddubsw m5, m3, [r3 + 10 * 16] ; [26]
pmulhrsw m5, m7
pmaddubsw m6, m3, [r3 + 8 * 16] ; [24]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m3, [r3 + 6 * 16] ; [22]
pmulhrsw m6, m7
pmaddubsw m0, m3, [r3 + 4 * 16] ; [20]
pmulhrsw m0, m7
packuswb m6, m0
pmaddubsw m1, m3, [r3 + 2 * 16] ; [18]
pmulhrsw m1, m7
pmaddubsw m0, m3, [r3] ; [16]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 1, m4, m5, m6, m1
pmaddubsw m4, m3, [r3 - 2 * 16] ; [14]
pmulhrsw m4, m7
pmaddubsw m5, m3, [r3 - 4 * 16] ; [12]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r3 - 6 * 16] ; [10]
pmulhrsw m5, m7
pmaddubsw m6, m3, [r3 - 8 * 16] ; [08]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m3, [r3 - 10 * 16] ; [06]
pmulhrsw m6, m7
pmaddubsw m1, m3, [r3 - 12 * 16] ; [04]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m1, m3, [r3 - 14 * 16] ; [02]
pmulhrsw m1, m7
packuswb m1, m1
punpcklqdq m1, m2 ;[00]
TRANSPOSE_STORE_8x8 1, 1, m4, m5, m6, m1
RET
INIT_XMM sse4
cglobal intra_pred_ang16_25, 3,7,8
lea r3, [ang_table + 16 * 16]
mov r4d, 2
lea r5, [r1 * 3] ; r5 -> 3 * stride
mov r6, r0
mova m7, [pw_1024]
.loop:
movu m3, [r2] ;[15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0]
mova m2, m3
palignr m1, m3, 1 ;[15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
punpcklbw m3, m1 ;[8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0]
pmaddubsw m4, m3, [r3 + 14 * 16] ; [30]
pmulhrsw m4, m7
pmaddubsw m0, m3, [r3 + 12 * 16] ; [28]
pmulhrsw m0, m7
packuswb m4, m0
pmaddubsw m5, m3, [r3 + 10 * 16] ; [26]
pmulhrsw m5, m7
pmaddubsw m6, m3, [r3 + 8 * 16] ; [24]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m3, [r3 + 6 * 16] ; [22]
pmulhrsw m6, m7
pmaddubsw m0, m3, [r3 + 4 * 16] ; [20]
pmulhrsw m0, m7
packuswb m6, m0
pmaddubsw m1, m3, [r3 + 2 * 16] ; [18]
pmulhrsw m1, m7
pmaddubsw m0, m3, [r3] ; [16]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 0, m4, m5, m6, m1
pmaddubsw m4, m3, [r3 - 2 * 16] ; [14]
pmulhrsw m4, m7
pmaddubsw m5, m3, [r3 - 4 * 16] ; [12]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r3 - 6 * 16] ; [10]
pmulhrsw m5, m7
pmaddubsw m6, m3, [r3 - 8 * 16] ; [08]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m3, [r3 - 10 * 16] ; [06]
pmulhrsw m6, m7
pmaddubsw m1, m3, [r3 - 12 * 16] ; [04]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m1, m3, [r3 - 14 * 16] ; [02]
pmulhrsw m1, m7
packuswb m1, m1
movh [r0 ], m4
movhps [r0 + r1 ], m4
movh [r0 + r1 * 2], m5
movhps [r0 + r5 ], m5
lea r0, [r0 + r1 * 4]
movh [r0 ], m6
movhps [r0 + r1 ], m6
movh [r0 + r1 * 2], m1
movh [r0 + r5 ], m2
lea r0, [r6 + 8]
add r2, 8
dec r4
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang16_12, 4,7,8
lea r4, [ang_table + 16 * 16]
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0 + r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
movu m3, [r2 + 32] ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0]
pinsrb m3, [r2], 0
punpckhbw m0, m3, m3 ; [15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8]
punpcklbw m3, m3 ; [7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0]
movu m2, [r2]
pshufb m2, [c_mode16_12]
palignr m0, m3, 1 ; [8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0]
pmaddubsw m4, m0, [r4 + 11 * 16] ; [27]
pmulhrsw m4, m7
pmaddubsw m1, m0, [r4 + 6 * 16] ; [22]
pmulhrsw m1, m7
packuswb m4, m1
pmaddubsw m5, m0, [r4 + 1 * 16] ; [17]
pmulhrsw m5, m7
pmaddubsw m6, m0, [r4 - 4 * 16] ; [12]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m0, [r4 - 9 * 16] ; [7]
pmulhrsw m6, m7
pmaddubsw m0, [r4 - 14 * 16] ; [2]
pmulhrsw m0, m7
packuswb m6, m0
palignr m3, m2, 15
pmaddubsw m1, m3, [r4 + 13 * 16] ; [29]
pmulhrsw m1, m7
pmaddubsw m0, m3, [r4 + 8 * 16] ; [24]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 1, m4, m5, m6, m1
pmaddubsw m4, m3, [r4 + 3 * 16] ; [19]
pmulhrsw m4, m7
pmaddubsw m5, m3, [r4 - 2 * 16] ; [14]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r4 - 7 * 16] ; [09]
pmulhrsw m5, m7
pmaddubsw m6, m3, [r4 - 12 * 16] ; [04]
pmulhrsw m6, m7
packuswb m5, m6
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 15 * 16] ; [31]
pmulhrsw m6, m7
pmaddubsw m1, m3, [r4 + 10 * 16] ; [26]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m1, m3, [r4 + 5 * 16] ; [21]
pmulhrsw m1, m7
pmaddubsw m3, [r4] ; [16]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 1, 1, m4, m5, m6, m1
lea r0, [r6 + r1 * 4]
lea r6, [r6 + r1 * 8]
movu m1, [r2 + 1 + 32] ; [16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
pslldq m3, m1, 1 ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 x]
punpckhbw m3, m1 ; [16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8]
movlhps m2, m1 ; [8 7 6 5 4 3 2 1 x x x x x x x]
pmaddubsw m4, m3, [r4 + 11 * 16] ; [27]
pmulhrsw m4, m7
pmaddubsw m5, m3, [r4 + 6 * 16] ; [22]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r4 + 1 * 16] ; [17]
pmulhrsw m5, m7
pmaddubsw m6, m3, [r4 - 4 * 16] ; [12]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m3, [r4 - 9 * 16] ; [7]
pmulhrsw m6, m7
pmaddubsw m0, m3, [r4 - 14 * 16] ; [2]
pmulhrsw m0, m7
packuswb m6, m0
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 + 13 * 16] ; [29]
pmulhrsw m1, m7
pmaddubsw m0, m3, [r4 + 8 * 16] ; [24]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 1, m4, m5, m6, m1
pmaddubsw m4, m3, [r4 + 3 * 16] ; [19]
pmulhrsw m4, m7
pmaddubsw m5, m3, [r4 - 2 * 16] ; [14]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r4 - 7 * 16] ; [09]
pmulhrsw m5, m7
pmaddubsw m6, m3, [r4 - 12 * 16] ; [04]
pmulhrsw m6, m7
packuswb m5, m6
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 15 * 16] ; [31]
pmulhrsw m6, m7
pmaddubsw m1, m3, [r4 + 10 * 16] ; [26]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m1, m3, [r4 + 5 * 16] ; [21]
pmulhrsw m1, m7
pmaddubsw m3, [r4] ; [16]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 1, 1, m4, m5, m6, m1
RET
INIT_XMM sse4
cglobal intra_pred_ang16_24, 4,7,8
lea r4, [ang_table + 16 * 16]
lea r5, [r1 * 3] ; r5 -> 3 * stride
mov r6, r0
mova m7, [pw_1024]
movu m3, [r2] ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0]
punpckhbw m0, m3, m3 ; [15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8]
punpcklbw m3, m3 ; [7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0]
movu m2, [r2 + 32]
pshufb m2, [c_mode16_12]
palignr m0, m3, 1 ; [8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0]
pmaddubsw m4, m0, [r4 + 11 * 16] ; [27]
pmulhrsw m4, m7
pmaddubsw m1, m0, [r4 + 6 * 16] ; [22]
pmulhrsw m1, m7
packuswb m4, m1
pmaddubsw m5, m0, [r4 + 1 * 16] ; [17]
pmulhrsw m5, m7
pmaddubsw m6, m0, [r4 - 4 * 16] ; [12]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m0, [r4 - 9 * 16] ; [7]
pmulhrsw m6, m7
pmaddubsw m0, [r4 - 14 * 16] ; [2]
pmulhrsw m0, m7
packuswb m6, m0
palignr m3, m2, 15
pmaddubsw m1, m3, [r4 + 13 * 16] ; [29]
pmulhrsw m1, m7
pmaddubsw m0, m3, [r4 + 8 * 16] ; [24]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 0, m4, m5, m6, m1
pmaddubsw m4, m3, [r4 + 3 * 16] ; [19]
pmulhrsw m4, m7
pmaddubsw m5, m3, [r4 - 2 * 16] ; [14]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r4 - 7 * 16] ; [09]
pmulhrsw m5, m7
pmaddubsw m6, m3, [r4 - 12 * 16] ; [04]
pmulhrsw m6, m7
packuswb m5, m6
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 15 * 16] ; [31]
pmulhrsw m6, m7
pmaddubsw m1, m3, [r4 + 10 * 16] ; [26]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m1, m3, [r4 + 5 * 16] ; [21]
pmulhrsw m1, m7
pmaddubsw m3, [r4] ; [16]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 1, 0, m4, m5, m6, m1
lea r0, [r6 + 8]
movu m1, [r2 + 1] ; [16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
pslldq m3, m1, 1 ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 x]
punpckhbw m3, m1 ; [16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8]
movlhps m2, m1 ; [8 7 6 5 4 3 2 1 x x x x x x x]
pmaddubsw m4, m3, [r4 + 11 * 16] ; [27]
pmulhrsw m4, m7
pmaddubsw m5, m3, [r4 + 6 * 16] ; [22]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r4 + 1 * 16] ; [17]
pmulhrsw m5, m7
pmaddubsw m6, m3, [r4 - 4 * 16] ; [12]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m3, [r4 - 9 * 16] ; [7]
pmulhrsw m6, m7
pmaddubsw m0, m3, [r4 - 14 * 16] ; [2]
pmulhrsw m0, m7
packuswb m6, m0
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 + 13 * 16] ; [29]
pmulhrsw m1, m7
pmaddubsw m0, m3, [r4 + 8 * 16] ; [24]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 0, m4, m5, m6, m1
pmaddubsw m4, m3, [r4 + 3 * 16] ; [19]
pmulhrsw m4, m7
pmaddubsw m5, m3, [r4 - 2 * 16] ; [14]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r4 - 7 * 16] ; [09]
pmulhrsw m5, m7
pmaddubsw m6, m3, [r4 - 12 * 16] ; [04]
pmulhrsw m6, m7
packuswb m5, m6
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 15 * 16] ; [31]
pmulhrsw m6, m7
pmaddubsw m1, m3, [r4 + 10 * 16] ; [26]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m1, m3, [r4 + 5 * 16] ; [21]
pmulhrsw m1, m7
pmaddubsw m3, [r4] ; [16]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 1, 0, m4, m5, m6, m1
RET
INIT_XMM sse4
cglobal intra_pred_ang16_13, 4,7,8
lea r4, [ang_table + 16 * 16]
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0 + r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
movu m3, [r2 + 32] ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0]
pinsrb m3, [r2], 0
punpckhbw m5, m3, m3 ; [15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8]
punpcklbw m3, m3 ; [7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0]
movu m2, [r2]
pshufb m2, [c_mode16_13]
palignr m5, m3, 1 ; [8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0]
pmaddubsw m4, m5, [r4 + 7 * 16] ; [23]
pmulhrsw m4, m7
pmaddubsw m0, m5, [r4 - 2 * 16] ; [14]
pmulhrsw m0, m7
packuswb m4, m0
pmaddubsw m5, [r4 - 11 * 16] ; [05]
pmulhrsw m5, m7
palignr m3, m2, 15
pmaddubsw m6, m3, [r4 + 12 * 16] ; [28]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m3, [r4 + 3 * 16] ; [19]
pmulhrsw m6, m7
pmaddubsw m0, m3, [r4 - 6 * 16] ; [10]
pmulhrsw m0, m7
packuswb m6, m0
pmaddubsw m1, m3, [r4 - 15 * 16] ; [01]
pmulhrsw m1, m7
palignr m3, m2, 14
pmaddubsw m0, m3, [r4 + 8 * 16] ; [24]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 1, m4, m5, m6, m1
pmaddubsw m4, m3, [r4 - 16] ; [15]
pmulhrsw m4, m7
pmaddubsw m5, m3, [r4 - 10 * 16] ; [06]
pmulhrsw m5, m7
packuswb m4, m5
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 + 13 * 16] ; [29]
pmulhrsw m5, m7
pmaddubsw m6, m3, [r4 + 4 * 16] ; [20]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m3, [r4 - 5 * 16] ; [11]
pmulhrsw m6, m7
pmaddubsw m1, m3, [r4 - 14 * 16] ; [02]
pmulhrsw m1, m7
packuswb m6, m1
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 + 9 * 16] ; [25]
pmulhrsw m1, m7
pmaddubsw m3, [r4] ; [16]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 1, 1, m4, m5, m6, m1
lea r0, [r6 + r1 * 4]
lea r6, [r6 + r1 * 8]
movu m1, [r2 + 1 + 32] ; [16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
pslldq m3, m1, 1 ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 x]
punpckhbw m3, m1 ; [16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8]
movlhps m2, m1 ; [8 7 6 5 4 3 2 1 x x x x x x x]
pmaddubsw m4, m3, [r4 + 7 * 16] ; [23]
pmulhrsw m4, m7
pmaddubsw m5, m3, [r4 - 2 * 16] ; [14]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r4 - 11 * 16] ; [05]
pmulhrsw m5, m7
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 12 * 16] ; [28]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m3, [r4 + 3 * 16] ; [19]
pmulhrsw m6, m7
pmaddubsw m0, m3, [r4 - 6 * 16] ; [10]
pmulhrsw m0, m7
packuswb m6, m0
pmaddubsw m1, m3, [r4 - 15 * 16] ; [01]
pmulhrsw m1, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m0, m3, [r4 + 8 * 16] ; [24]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 1, m4, m5, m6, m1
pmaddubsw m4, m3, [r4 - 16] ; [15]
pmulhrsw m4, m7
pmaddubsw m5, m3, [r4 - 10 * 16] ; [06]
pmulhrsw m5, m7
packuswb m4, m5
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 + 13 * 16] ; [29]
pmulhrsw m5, m7
pmaddubsw m6, m3, [r4 + 4 * 16] ; [20]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m3, [r4 - 5 * 16] ; [11]
pmulhrsw m6, m7
pmaddubsw m1, m3, [r4 - 14 * 16] ; [02]
pmulhrsw m1, m7
packuswb m6, m1
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 + 9 * 16] ; [25]
pmulhrsw m1, m7
pmaddubsw m3, [r4] ; [16]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 1, 1, m4, m5, m6, m1
RET
INIT_XMM sse4
cglobal intra_pred_ang16_23, 4,7,8
lea r4, [ang_table + 16 * 16]
lea r5, [r1 * 3] ; r5 -> 3 * stride
mov r6, r0
mova m7, [pw_1024]
movu m3, [r2] ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0]
punpckhbw m5, m3, m3 ; [15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8]
punpcklbw m3, m3 ; [7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0]
movu m2, [r2 + 32]
pshufb m2, [c_mode16_13]
palignr m5, m3, 1 ; [8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0]
pmaddubsw m4, m5, [r4 + 7 * 16] ; [23]
pmulhrsw m4, m7
pmaddubsw m0, m5, [r4 - 2 * 16] ; [14]
pmulhrsw m0, m7
packuswb m4, m0
pmaddubsw m5, [r4 - 11 * 16] ; [05]
pmulhrsw m5, m7
palignr m3, m2, 15
pmaddubsw m6, m3, [r4 + 12 * 16] ; [28]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m3, [r4 + 3 * 16] ; [19]
pmulhrsw m6, m7
pmaddubsw m0, m3, [r4 - 6 * 16] ; [10]
pmulhrsw m0, m7
packuswb m6, m0
pmaddubsw m1, m3, [r4 - 15 * 16] ; [01]
pmulhrsw m1, m7
palignr m3, m2, 14
pmaddubsw m0, m3, [r4 + 8 * 16] ; [24]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 0, m4, m5, m6, m1
pmaddubsw m4, m3, [r4 - 16] ; [15]
pmulhrsw m4, m7
pmaddubsw m5, m3, [r4 - 10 * 16] ; [06]
pmulhrsw m5, m7
packuswb m4, m5
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 + 13 * 16] ; [29]
pmulhrsw m5, m7
pmaddubsw m6, m3, [r4 + 4 * 16] ; [20]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m3, [r4 - 5 * 16] ; [11]
pmulhrsw m6, m7
pmaddubsw m1, m3, [r4 - 14 * 16] ; [02]
pmulhrsw m1, m7
packuswb m6, m1
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 + 9 * 16] ; [25]
pmulhrsw m1, m7
pmaddubsw m3, [r4] ; [16]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 1, 0, m4, m5, m6, m1
lea r0, [r6 + 8]
movu m1, [r2 + 1] ; [16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
pslldq m3, m1, 1 ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 x]
punpckhbw m3, m1 ; [16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8]
movlhps m2, m1 ; [8 7 6 5 4 3 2 1 x x x x x x x]
pmaddubsw m4, m3, [r4 + 7 * 16] ; [23]
pmulhrsw m4, m7
pmaddubsw m5, m3, [r4 - 2 * 16] ; [14]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r4 - 11 * 16] ; [05]
pmulhrsw m5, m7
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 12 * 16] ; [28]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m3, [r4 + 3 * 16] ; [19]
pmulhrsw m6, m7
pmaddubsw m0, m3, [r4 - 6 * 16] ; [10]
pmulhrsw m0, m7
packuswb m6, m0
pmaddubsw m1, m3, [r4 - 15 * 16] ; [01]
pmulhrsw m1, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m0, m3, [r4 + 8 * 16] ; [24]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 0, m4, m5, m6, m1
pmaddubsw m4, m3, [r4 - 16] ; [15]
pmulhrsw m4, m7
pmaddubsw m5, m3, [r4 - 10 * 16] ; [06]
pmulhrsw m5, m7
packuswb m4, m5
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 + 13 * 16] ; [29]
pmulhrsw m5, m7
pmaddubsw m6, m3, [r4 + 4 * 16] ; [20]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m3, [r4 - 5 * 16] ; [11]
pmulhrsw m6, m7
pmaddubsw m1, m3, [r4 - 14 * 16] ; [02]
pmulhrsw m1, m7
packuswb m6, m1
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 + 9 * 16] ; [25]
pmulhrsw m1, m7
pmaddubsw m3, [r4] ; [16]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 1, 0, m4, m5, m6, m1
RET
INIT_XMM sse4
cglobal intra_pred_ang16_14, 4,7,8
lea r4, [ang_table + 16 * 16]
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0 + r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
movu m3, [r2 + 32] ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0]
pinsrb m3, [r2], 0
punpckhbw m5, m3, m3 ; [15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8]
punpcklbw m3, m3 ; [7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0]
movu m2, [r2]
pshufb m2, [c_mode16_14]
palignr m5, m3, 1 ; [8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0]
pmaddubsw m4, m5, [r4 + 3 * 16] ; [19]
pmulhrsw m4, m7
pmaddubsw m5, [r4 - 10 * 16] ; [06]
pmulhrsw m5, m7
packuswb m4, m5
palignr m3, m2, 15
pmaddubsw m5, m3, [r4 + 9 * 16] ; [25]
pmulhrsw m5, m7
pmaddubsw m6, m3, [r4 - 4 * 16] ; [12]
pmulhrsw m6, m7
packuswb m5, m6
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 15 * 16] ; [31]
pmulhrsw m6, m7
pmaddubsw m0, m3, [r4 + 2 * 16] ; [18]
pmulhrsw m0, m7
packuswb m6, m0
pmaddubsw m1, m3, [r4 - 11 * 16] ; [05]
pmulhrsw m1, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m0, m3, [r4 + 8 * 16] ; [24]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 1, m4, m5, m6, m1
pmaddubsw m4, m3, [r4 - 5 * 16] ; [11]
pmulhrsw m4, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 + 14 * 16] ; [30]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r4 + 16] ; [17]
pmulhrsw m5, m7
pmaddubsw m6, m3, [r4 - 12 * 16] ; [04]
pmulhrsw m6, m7
packuswb m5, m6
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 7 * 16] ; [23]
pmulhrsw m6, m7
pmaddubsw m1, m3, [r4 - 6 * 16] ; [10]
pmulhrsw m1, m7
packuswb m6, m1
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 + 13 * 16] ; [29]
pmulhrsw m1, m7
pmaddubsw m3, [r4] ; [16]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 1, 1, m4, m5, m6, m1
lea r0, [r6 + r1 * 4]
lea r6, [r6 + r1 * 8]
movu m1, [r2 + 1 + 32] ; [16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
pslldq m3, m1, 1 ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 x]
punpckhbw m3, m1 ; [16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8]
movlhps m2, m1 ; [8 7 6 5 4 3 2 1 x x x x x x x]
pmaddubsw m4, m3, [r4 + 3 * 16] ; [19]
pmulhrsw m4, m7
pmaddubsw m5, m3, [r4 - 10 * 16] ; [06]
pmulhrsw m5, m7
packuswb m4, m5
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 + 9 * 16] ; [25]
pmulhrsw m5, m7
pmaddubsw m6, m3, [r4 - 4 * 16] ; [12]
pmulhrsw m6, m7
packuswb m5, m6
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 15 * 16] ; [31]
pmulhrsw m6, m7
pmaddubsw m0, m3, [r4 + 2 * 16] ; [18]
pmulhrsw m0, m7
packuswb m6, m0
pmaddubsw m1, m3, [r4 - 11 * 16] ; [05]
pmulhrsw m1, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m0, m3, [r4 + 8 * 16] ; [24]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 1, m4, m5, m6, m1
pmaddubsw m4, m3, [r4 - 5 * 16] ; [11]
pmulhrsw m4, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 + 14 * 16] ; [30]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r4 + 16] ; [17]
pmulhrsw m5, m7
pmaddubsw m6, m3, [r4 - 12 * 16] ; [04]
pmulhrsw m6, m7
packuswb m5, m6
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 7 * 16] ; [23]
pmulhrsw m6, m7
pmaddubsw m1, m3, [r4 - 6 * 16] ; [10]
pmulhrsw m1, m7
packuswb m6, m1
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 + 13 * 16] ; [29]
pmulhrsw m1, m7
pmaddubsw m3, [r4] ; [16]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 1, 1, m4, m5, m6, m1
RET
INIT_XMM sse4
cglobal intra_pred_ang16_22, 4,7,8
lea r4, [ang_table + 16 * 16]
lea r5, [r1 * 3] ; r5 -> 3 * stride
mov r6, r0
mova m7, [pw_1024]
movu m3, [r2] ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0]
punpckhbw m5, m3, m3 ; [15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8]
punpcklbw m3, m3 ; [7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0]
movu m2, [r2 + 32]
pshufb m2, [c_mode16_14]
palignr m5, m3, 1 ; [8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0]
pmaddubsw m4, m5, [r4 + 3 * 16] ; [19]
pmulhrsw m4, m7
pmaddubsw m5, [r4 - 10 * 16] ; [06]
pmulhrsw m5, m7
packuswb m4, m5
palignr m3, m2, 15
pmaddubsw m5, m3, [r4 + 9 * 16] ; [25]
pmulhrsw m5, m7
pmaddubsw m6, m3, [r4 - 4 * 16] ; [12]
pmulhrsw m6, m7
packuswb m5, m6
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 15 * 16] ; [31]
pmulhrsw m6, m7
pmaddubsw m0, m3, [r4 + 2 * 16] ; [18]
pmulhrsw m0, m7
packuswb m6, m0
pmaddubsw m1, m3, [r4 - 11 * 16] ; [05]
pmulhrsw m1, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m0, m3, [r4 + 8 * 16] ; [24]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 0, m4, m5, m6, m1
pmaddubsw m4, m3, [r4 - 5 * 16] ; [11]
pmulhrsw m4, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 + 14 * 16] ; [30]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r4 + 16] ; [17]
pmulhrsw m5, m7
pmaddubsw m6, m3, [r4 - 12 * 16] ; [04]
pmulhrsw m6, m7
packuswb m5, m6
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 7 * 16] ; [23]
pmulhrsw m6, m7
pmaddubsw m1, m3, [r4 - 6 * 16] ; [10]
pmulhrsw m1, m7
packuswb m6, m1
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 + 13 * 16] ; [29]
pmulhrsw m1, m7
pmaddubsw m3, [r4] ; [16]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 1, 0, m4, m5, m6, m1
lea r0, [r6 + 8]
movu m1, [r2 + 1] ; [16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
pslldq m3, m1, 1 ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 x]
punpckhbw m3, m1 ; [16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8]
movlhps m2, m1 ; [8 7 6 5 4 3 2 1 x x x x x x x]
pmaddubsw m4, m3, [r4 + 3 * 16] ; [19]
pmulhrsw m4, m7
pmaddubsw m5, m3, [r4 - 10 * 16] ; [06]
pmulhrsw m5, m7
packuswb m4, m5
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 + 9 * 16] ; [25]
pmulhrsw m5, m7
pmaddubsw m6, m3, [r4 - 4 * 16] ; [12]
pmulhrsw m6, m7
packuswb m5, m6
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 15 * 16] ; [31]
pmulhrsw m6, m7
pmaddubsw m0, m3, [r4 + 2 * 16] ; [18]
pmulhrsw m0, m7
packuswb m6, m0
pmaddubsw m1, m3, [r4 - 11 * 16] ; [05]
pmulhrsw m1, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m0, m3, [r4 + 8 * 16] ; [24]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 0, m4, m5, m6, m1
pmaddubsw m4, m3, [r4 - 5 * 16] ; [11]
pmulhrsw m4, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 + 14 * 16] ; [30]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r4 + 16] ; [17]
pmulhrsw m5, m7
pmaddubsw m6, m3, [r4 - 12 * 16] ; [04]
pmulhrsw m6, m7
packuswb m5, m6
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 7 * 16] ; [23]
pmulhrsw m6, m7
pmaddubsw m1, m3, [r4 - 6 * 16] ; [10]
pmulhrsw m1, m7
packuswb m6, m1
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 + 13 * 16] ; [29]
pmulhrsw m1, m7
pmaddubsw m3, [r4] ; [16]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 1, 0, m4, m5, m6, m1
RET
INIT_XMM sse4
cglobal intra_pred_ang16_15, 4,7,8
lea r4, [ang_table + 16 * 16]
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0 + r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
movu m3, [r2 + 32] ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0]
pinsrb m3, [r2], 0
punpckhbw m4, m3, m3 ; [15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8]
punpcklbw m3, m3 ; [7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0]
movu m2, [r2]
pshufb m2, [c_mode16_15]
palignr m4, m3, 1 ; [8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0]
pmaddubsw m4, [r4 - 16] ; [15]
pmulhrsw m4, m7
palignr m3, m2, 15
pmaddubsw m5, m3, [r4 + 14 * 16] ; [30]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r4 - 3 * 16] ; [13]
pmulhrsw m5, m7
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 12 * 16] ; [28]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m3, [r4 - 5 * 16] ; [11]
pmulhrsw m6, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m0, m3, [r4 + 10 * 16] ; [26]
pmulhrsw m0, m7
packuswb m6, m0
pmaddubsw m1, m3, [r4 - 7 * 16] ; [09]
pmulhrsw m1, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m0, m3, [r4 + 8 * 16] ; [24]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 1, m4, m5, m6, m1
pmaddubsw m4, m3, [r4 - 9 * 16] ; [07]
pmulhrsw m4, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 + 6 * 16] ; [22]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r4 - 11 * 16] ; [05]
pmulhrsw m5, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 4 * 16] ; [20]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m3, [r4 - 13 * 16] ; [03]
pmulhrsw m6, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 + 2 * 16] ; [18]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m1, m3, [r4 - 15 * 16] ; [01]
pmulhrsw m1, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m3, [r4] ; [16]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 1, 1, m4, m5, m6, m1
lea r0, [r6 + r1 * 4]
lea r6, [r6 + r1 * 8]
movu m1, [r2 + 1 + 32] ; [16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
pslldq m3, m1, 1 ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 x]
punpckhbw m3, m1 ; [16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8]
movlhps m2, m1 ; [8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 15L]
pmaddubsw m4, m3, [r4 - 16] ; [15]
pmulhrsw m4, m7
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 + 14 * 16] ; [30]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r4 - 3 * 16] ; [13]
pmulhrsw m5, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 12 * 16] ; [28]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m3, [r4 - 5 * 16] ; [11]
pmulhrsw m6, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m0, m3, [r4 + 10 * 16] ; [26]
pmulhrsw m0, m7
packuswb m6, m0
pmaddubsw m1, m3, [r4 - 7 * 16] ; [09]
pmulhrsw m1, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m0, m3, [r4 + 8 * 16] ; [24]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 1, m4, m5, m6, m1
pmaddubsw m4, m3, [r4 - 9 * 16] ; [07]
pmulhrsw m4, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 + 6 * 16] ; [22]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r4 - 11 * 16] ; [05]
pmulhrsw m5, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 4 * 16] ; [20]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m3, [r4 - 13 * 16] ; [03]
pmulhrsw m6, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 + 2 * 16] ; [18]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m1, m3, [r4 - 15 * 16] ; [01]
pmulhrsw m1, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m3, [r4] ; [16]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 1, 1, m4, m5, m6, m1
RET
INIT_XMM sse4
cglobal intra_pred_ang16_21, 4,7,8
lea r4, [ang_table + 16 * 16]
lea r5, [r1 * 3] ; r5 -> 3 * stride
mov r6, r0
mova m7, [pw_1024]
movu m3, [r2] ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0]
punpckhbw m4, m3, m3 ; [15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8]
punpcklbw m3, m3 ; [7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0]
movu m2, [r2 + 32]
pinsrb m2, [r2], 0
pshufb m2, [c_mode16_15]
palignr m4, m3, 1 ; [8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0]
pmaddubsw m4, [r4 - 16] ; [15]
pmulhrsw m4, m7
palignr m3, m2, 15
pmaddubsw m5, m3, [r4 + 14 * 16] ; [30]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r4 - 3 * 16] ; [13]
pmulhrsw m5, m7
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 12 * 16] ; [28]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m3, [r4 - 5 * 16] ; [11]
pmulhrsw m6, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m0, m3, [r4 + 10 * 16] ; [26]
pmulhrsw m0, m7
packuswb m6, m0
pmaddubsw m1, m3, [r4 - 7 * 16] ; [09]
pmulhrsw m1, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m0, m3, [r4 + 8 * 16] ; [24]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 0, m4, m5, m6, m1
pmaddubsw m4, m3, [r4 - 9 * 16] ; [07]
pmulhrsw m4, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 + 6 * 16] ; [22]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r4 - 11 * 16] ; [05]
pmulhrsw m5, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 4 * 16] ; [20]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m3, [r4 - 13 * 16] ; [03]
pmulhrsw m6, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 + 2 * 16] ; [18]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m1, m3, [r4 - 15 * 16] ; [01]
pmulhrsw m1, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m3, [r4] ; [16]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 1, 0, m4, m5, m6, m1
lea r0, [r6 + 8]
movu m1, [r2 + 1] ; [16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
pslldq m3, m1, 1 ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 x]
punpckhbw m3, m1 ; [16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8]
movlhps m2, m1 ; [8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 15L]
pmaddubsw m4, m3, [r4 - 16] ; [15]
pmulhrsw m4, m7
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 + 14 * 16] ; [30]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r4 - 3 * 16] ; [13]
pmulhrsw m5, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 12 * 16] ; [28]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m3, [r4 - 5 * 16] ; [11]
pmulhrsw m6, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m0, m3, [r4 + 10 * 16] ; [26]
pmulhrsw m0, m7
packuswb m6, m0
pmaddubsw m1, m3, [r4 - 7 * 16] ; [09]
pmulhrsw m1, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m0, m3, [r4 + 8 * 16] ; [24]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 0, m4, m5, m6, m1
pmaddubsw m4, m3, [r4 - 9 * 16] ; [07]
pmulhrsw m4, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 + 6 * 16] ; [22]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r4 - 11 * 16] ; [05]
pmulhrsw m5, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 4 * 16] ; [20]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m3, [r4 - 13 * 16] ; [03]
pmulhrsw m6, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 + 2 * 16] ; [18]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m1, m3, [r4 - 15 * 16] ; [01]
pmulhrsw m1, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m3, [r4] ; [16]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 1, 0, m4, m5, m6, m1
RET
INIT_XMM sse4
cglobal intra_pred_ang16_16, 4,7,8
lea r4, [ang_table + 16 * 16]
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0 + r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
movu m3, [r2 + 32] ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0]
pinsrb m3, [r2], 0
punpckhbw m4, m3, m3 ; [15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8]
punpcklbw m3, m3 ; [7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0]
movu m2, [r2]
pshufb m2, [c_mode16_16] ; [2, 3, 5, 6, 8, 9, 11, 12, 14, 15, 0, 2, 3, 5, 6, 8]
palignr m4, m3, 1 ; [8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0]
pmaddubsw m4, [r4 - 5 * 16] ; [11]
pmulhrsw m4, m7
palignr m3, m2, 15
pmaddubsw m5, m3, [r4 + 6 * 16] ; [22]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r4 - 15 * 16] ; [01]
pmulhrsw m5, m7
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 - 4 * 16] ; [12]
pmulhrsw m6, m7
packuswb m5, m6
pslldq m2, 1 ; [3, 5, 6, 8, 9, 11, 12, 14, 15, 0, 2, 3, 5, 6, 8, x]
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 7 * 16] ; [23]
pmulhrsw m6, m7
pmaddubsw m0, m3, [r4 - 14 * 16] ; [02]
pmulhrsw m0, m7
packuswb m6, m0
pslldq m2, 1 ; [5, 6, 8, 9, 11, 12, 14, 15, 0, 2, 3, 5, 6, 8, x, x]
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 - 3 * 16] ; [13]
pmulhrsw m1, m7
pslldq m2, 1 ; [6, 8, 9, 11, 12, 14, 15, 0, 2, 3, 5, 6, 8, x, x, x]
palignr m3, m2, 14
pmaddubsw m0, m3, [r4 + 8 * 16] ; [24]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 1, m4, m5, m6, m1
pmaddubsw m4, m3, [r4 - 13 * 16] ; [03]
pmulhrsw m4, m7
pslldq m2, 1 ; [8, 9, 11, 12, 14, 15, 0, 2, 3, 5, 6, 8, x, x, x, x]
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 - 2 * 16] ; [14]
pmulhrsw m5, m7
packuswb m4, m5
pslldq m2, 1 ; [9, 11, 12, 14, 15, 0, 2, 3, 5, 6, 8, x, x, x, x, x]
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 + 9 * 16] ; [25]
pmulhrsw m5, m7
pmaddubsw m6, m3, [r4 - 12 * 16] ; [04]
pmulhrsw m6, m7
packuswb m5, m6
pslldq m2, 1 ; [11, 12, 14, 15, 0, 2, 3, 5, 6, 8, x, x, x, x, x, x]
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 - 16] ; [15]
pmulhrsw m6, m7
pslldq m2, 1 ; [12, 14, 15, 0, 2, 3, 5, 6, 8, x, x, x, x, x, x, x]
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 + 10 * 16] ; [26]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m1, m3, [r4 - 11 * 16] ; [05]
pmulhrsw m1, m7
pslldq m2, 1 ; [14, 15, 0, 2, 3, 5, 6, 8, x, x, x, x, x, x, x, x]
palignr m3, m2, 14
pmaddubsw m3, [r4] ; [16]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 1, 1, m4, m5, m6, m1
lea r0, [r6 + r1 * 4]
lea r6, [r6 + r1 * 8]
movu m1, [r2 + 1 + 32] ; [16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
pslldq m3, m1, 1 ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 x]
punpckhbw m3, m1 ; [16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8]
palignr m2, m2, 6 ; [x, x, x, x, x, x, 14, 15, 0, 2, 3, 5, 6, 8, x, x]
movlhps m2, m1 ; [8 7 6 5 4 3 2 1 0, 2, 3, 5, 6, 8, x, x]
pmaddubsw m4, m3, [r4 - 5 * 16] ; [11]
pmulhrsw m4, m7
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 + 6 * 16] ; [22]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r4 - 15 * 16] ; [01]
pmulhrsw m5, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 - 4 * 16] ; [12]
pmulhrsw m6, m7
packuswb m5, m6
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 7 * 16] ; [23]
pmulhrsw m6, m7
pmaddubsw m0, m3, [r4 - 14 * 16] ; [02]
pmulhrsw m0, m7
packuswb m6, m0
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 - 3 * 16] ; [13]
pmulhrsw m1, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m0, m3, [r4 + 8 * 16] ; [24]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 1, m4, m5, m6, m1
pmaddubsw m4, m3, [r4 - 13 * 16] ; [03]
pmulhrsw m4, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 - 2 * 16] ; [14]
pmulhrsw m5, m7
packuswb m4, m5
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 + 9 * 16] ; [25]
pmulhrsw m5, m7
pmaddubsw m6, m3, [r4 - 12 * 16] ; [04]
pmulhrsw m6, m7
packuswb m5, m6
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 - 16] ; [15]
pmulhrsw m6, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 + 10 * 16] ; [26]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m1, m3, [r4 - 11 * 16] ; [05]
pmulhrsw m1, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m3, [r4] ; [16]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 1, 1, m4, m5, m6, m1
RET
INIT_XMM sse4
cglobal intra_pred_ang16_20, 4,7,8
lea r4, [ang_table + 16 * 16]
lea r5, [r1 * 3] ; r5 -> 3 * stride
mov r6, r0
mova m7, [pw_1024]
movu m3, [r2] ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0]
punpckhbw m4, m3, m3 ; [15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8]
punpcklbw m3, m3 ; [7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0]
movu m2, [r2 + 32]
pinsrb m2, [r2], 0
pshufb m2, [c_mode16_16] ; [2, 3, 5, 6, 8, 9, 11, 12, 14, 15, 0, 2, 3, 5, 6, 8]
palignr m4, m3, 1 ; [8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0]
pmaddubsw m4, [r4 - 5 * 16] ; [11]
pmulhrsw m4, m7
palignr m3, m2, 15
pmaddubsw m5, m3, [r4 + 6 * 16] ; [22]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r4 - 15 * 16] ; [01]
pmulhrsw m5, m7
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 - 4 * 16] ; [12]
pmulhrsw m6, m7
packuswb m5, m6
pslldq m2, 1 ; [3, 5, 6, 8, 9, 11, 12, 14, 15, 0, 2, 3, 5, 6, 8, x]
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 7 * 16] ; [23]
pmulhrsw m6, m7
pmaddubsw m0, m3, [r4 - 14 * 16] ; [02]
pmulhrsw m0, m7
packuswb m6, m0
pslldq m2, 1 ; [5, 6, 8, 9, 11, 12, 14, 15, 0, 2, 3, 5, 6, 8, x, x]
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 - 3 * 16] ; [13]
pmulhrsw m1, m7
pslldq m2, 1 ; [6, 8, 9, 11, 12, 14, 15, 0, 2, 3, 5, 6, 8, x, x, x]
palignr m3, m2, 14
pmaddubsw m0, m3, [r4 + 8 * 16] ; [24]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 0, m4, m5, m6, m1
pmaddubsw m4, m3, [r4 - 13 * 16] ; [03]
pmulhrsw m4, m7
pslldq m2, 1 ; [8, 9, 11, 12, 14, 15, 0, 2, 3, 5, 6, 8, x, x, x, x]
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 - 2 * 16] ; [14]
pmulhrsw m5, m7
packuswb m4, m5
pslldq m2, 1 ; [9, 11, 12, 14, 15, 0, 2, 3, 5, 6, 8, x, x, x, x, x]
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 + 9 * 16] ; [25]
pmulhrsw m5, m7
pmaddubsw m6, m3, [r4 - 12 * 16] ; [04]
pmulhrsw m6, m7
packuswb m5, m6
pslldq m2, 1 ; [11, 12, 14, 15, 0, 2, 3, 5, 6, 8, x, x, x, x, x, x]
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 - 16] ; [15]
pmulhrsw m6, m7
pslldq m2, 1 ; [12, 14, 15, 0, 2, 3, 5, 6, 8, x, x, x, x, x, x, x]
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 + 10 * 16] ; [26]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m1, m3, [r4 - 11 * 16] ; [05]
pmulhrsw m1, m7
pslldq m2, 1 ; [14, 15, 0, 2, 3, 5, 6, 8, x, x, x, x, x, x, x, x]
palignr m3, m2, 14
pmaddubsw m3, [r4] ; [16]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 1, 0, m4, m5, m6, m1
lea r0, [r6 + 8]
movu m1, [r2 + 1] ; [16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
pslldq m3, m1, 1 ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 x]
punpckhbw m3, m1 ; [16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8]
palignr m2, m2, 6 ; [x, x, x, x, x, x, 14, 15, 0, 2, 3, 5, 6, 8, x, x]
movlhps m2, m1 ; [8 7 6 5 4 3 2 1 0, 2, 3, 5, 6, 8, x, x]
pmaddubsw m4, m3, [r4 - 5 * 16] ; [11]
pmulhrsw m4, m7
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 + 6 * 16] ; [22]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r4 - 15 * 16] ; [01]
pmulhrsw m5, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 - 4 * 16] ; [12]
pmulhrsw m6, m7
packuswb m5, m6
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 7 * 16] ; [23]
pmulhrsw m6, m7
pmaddubsw m0, m3, [r4 - 14 * 16] ; [02]
pmulhrsw m0, m7
packuswb m6, m0
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 - 3 * 16] ; [13]
pmulhrsw m1, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m0, m3, [r4 + 8 * 16] ; [24]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 0, m4, m5, m6, m1
pmaddubsw m4, m3, [r4 - 13 * 16] ; [03]
pmulhrsw m4, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 - 2 * 16] ; [14]
pmulhrsw m5, m7
packuswb m4, m5
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 + 9 * 16] ; [25]
pmulhrsw m5, m7
pmaddubsw m6, m3, [r4 - 12 * 16] ; [04]
pmulhrsw m6, m7
packuswb m5, m6
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 - 16] ; [15]
pmulhrsw m6, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 + 10 * 16] ; [26]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m1, m3, [r4 - 11 * 16] ; [05]
pmulhrsw m1, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m3, [r4] ; [16]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 1, 0, m4, m5, m6, m1
RET
INIT_XMM sse4
cglobal intra_pred_ang16_17, 4,7,8
lea r4, [ang_table + 16 * 16]
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0 + r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
movu m3, [r2 + 32] ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0]
pinsrb m3, [r2], 0
punpckhbw m4, m3, m3 ; [15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8]
punpcklbw m3, m3 ; [7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0]
movu m2, [r2]
pshufb m2, [c_mode16_17] ; [1, 2, 4, 5, 6, 7, 9, 10, 11, 12, 14, 15, 0, 1, 2, 4]
palignr m4, m3, 1 ; [8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0]
pmaddubsw m4, [r4 - 10 * 16] ; [06]
pmulhrsw m4, m7
palignr m3, m2, 15
pmaddubsw m5, m3, [r4 - 4 * 16] ; [12]
pmulhrsw m5, m7
packuswb m4, m5
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 + 2 * 16] ; [18]
pmulhrsw m5, m7
pslldq m2, 1 ; [2, 4, 5, 6, 7, 9, 10, 11, 12, 14, 15, 0, 1, 2, 4, x]
pinsrb m2, [r2 + 5], 0 ; [2, 4, 5, 6, 7, 9, 10, 11, 12, 14, 15, 0, 1, 2, 4, 5]
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 8 * 16] ; [24]
pmulhrsw m6, m7
packuswb m5, m6
pslldq m2, 1 ; [4, 5, 6, 7, 9, 10, 11, 12, 14, 15, 0, 1, 2, 4, 5, x]
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 14 * 16] ; [30]
pmulhrsw m6, m7
pmaddubsw m0, m3, [r4 - 12 * 16] ; [04]
pmulhrsw m0, m7
packuswb m6, m0
pslldq m2, 1 ; [5, 6, 7, 9, 10, 11, 12, 14, 15, 0, 1, 2, 4, 5, x, x]
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 - 6 * 16] ; [10]
pmulhrsw m1, m7
pslldq m2, 1 ; [6, 7, 9, 10, 11, 12, 14, 15, 0, 1, 2, 4, 5, x, x, x]
palignr m3, m2, 14
pmaddubsw m0, m3, [r4] ; [16]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 1, m4, m5, m6, m1
pslldq m2, 1 ; [7, 9, 10, 11, 12, 14, 15, 0, 1, 2, 4, 5, x, x, x, x]
palignr m3, m2, 14
pmaddubsw m4, m3, [r4 + 6 * 16] ; [22]
pmulhrsw m4, m7
pslldq m2, 1 ; [9, 10, 11, 12, 14, 15, 0, 1, 2, 4, 5, x, x, x, x, x]
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 + 12 * 16] ; [28]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r4 - 14 * 16] ; [02]
pmulhrsw m5, m7
pslldq m2, 1 ; [10, 11, 12, 14, 15, 0, 1, 2, 4, 5, x, x, x, x, x, x]
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 - 8 * 16] ; [08]
pmulhrsw m6, m7
packuswb m5, m6
pslldq m2, 1 ; [11, 12, 14, 15, 0, 1, 2, 4, 5, x, x, x, x, x, x, x]
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 - 2 * 16] ; [14]
pmulhrsw m6, m7
pslldq m2, 1 ; [12, 14, 15, 0, 1, 2, 4, 5, x, x, x, x, x, x, x, x]
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 + 4 * 16] ; [20]
pmulhrsw m1, m7
packuswb m6, m1
pslldq m2, 1 ; [14, 15, 0, 1, 2, 4, 5, x, x, x, x, x, x, x, x, x]
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 + 10 * 16] ; [26]
pmulhrsw m1, m7
pmaddubsw m3, [r4 - 16 * 16] ; [00]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 1, 1, m4, m5, m6, m1
lea r0, [r6 + r1 * 4]
lea r6, [r6 + r1 * 8]
movu m1, [r2 + 1 + 32] ; [16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
pslldq m3, m1, 1 ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 x]
punpckhbw m3, m1 ; [16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8]
palignr m2, m2, 6 ; [x, x, x, x, x, x, 14, 15, 0, 1, 2, 4, 5, x, x, x]
movlhps m2, m1 ; [8 7 6 5 4 3 2 1 0, 1, 2, 4, 5, x, x, x]
pmaddubsw m4, m3, [r4 - 10 * 16] ; [06]
pmulhrsw m4, m7
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 - 4 * 16] ; [12]
pmulhrsw m5, m7
packuswb m4, m5
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 + 2 * 16] ; [18]
pmulhrsw m5, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 8 * 16] ; [24]
pmulhrsw m6, m7
packuswb m5, m6
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 14 * 16] ; [30]
pmulhrsw m6, m7
pmaddubsw m0, m3, [r4 - 12 * 16] ; [04]
pmulhrsw m0, m7
packuswb m6, m0
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 - 6 * 16] ; [10]
pmulhrsw m1, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m0, m3, [r4] ; [16]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 1, m4, m5, m6, m1
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m4, m3, [r4 + 6 * 16] ; [22]
pmulhrsw m4, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 + 12 * 16] ; [28]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r4 - 14 * 16] ; [02]
pmulhrsw m5, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 - 8 * 16] ; [08]
pmulhrsw m6, m7
packuswb m5, m6
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 - 2 * 16] ; [14]
pmulhrsw m6, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 + 4 * 16] ; [20]
pmulhrsw m1, m7
packuswb m6, m1
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 + 10 * 16] ; [26]
pmulhrsw m1, m7
pmaddubsw m3, [r4 - 16 * 16] ; [00]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 1, 1, m4, m5, m6, m1
RET
INIT_XMM sse4
cglobal intra_pred_ang16_19, 4,7,8
lea r4, [ang_table + 16 * 16]
lea r5, [r1 * 3] ; r5 -> 3 * stride
mov r6, r0
mova m7, [pw_1024]
movu m3, [r2] ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0]
punpckhbw m4, m3, m3 ; [15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8]
punpcklbw m3, m3 ; [7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0]
movu m2, [r2 + 32]
pinsrb m2, [r2], 0
pshufb m2, [c_mode16_17] ; [1, 2, 4, 5, 6, 7, 9, 10, 11, 12, 14, 15, 0, 1, 2, 4]
palignr m4, m3, 1 ; [8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0]
pmaddubsw m4, [r4 - 10 * 16] ; [06]
pmulhrsw m4, m7
palignr m3, m2, 15
pmaddubsw m5, m3, [r4 - 4 * 16] ; [12]
pmulhrsw m5, m7
packuswb m4, m5
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 + 2 * 16] ; [18]
pmulhrsw m5, m7
pslldq m2, 1 ; [2, 4, 5, 6, 7, 9, 10, 11, 12, 14, 15, 0, 1, 2, 4, x]
pinsrb m2, [r2 + 5 + 32], 0 ; [2, 4, 5, 6, 7, 9, 10, 11, 12, 14, 15, 0, 1, 2, 4, 5]
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 8 * 16] ; [24]
pmulhrsw m6, m7
packuswb m5, m6
pslldq m2, 1 ; [4, 5, 6, 7, 9, 10, 11, 12, 14, 15, 0, 1, 2, 4, 5, x]
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 14 * 16] ; [30]
pmulhrsw m6, m7
pmaddubsw m0, m3, [r4 - 12 * 16] ; [04]
pmulhrsw m0, m7
packuswb m6, m0
pslldq m2, 1 ; [5, 6, 7, 9, 10, 11, 12, 14, 15, 0, 1, 2, 4, 5, x, x]
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 - 6 * 16] ; [10]
pmulhrsw m1, m7
pslldq m2, 1 ; [6, 7, 9, 10, 11, 12, 14, 15, 0, 1, 2, 4, 5, x, x, x]
palignr m3, m2, 14
pmaddubsw m0, m3, [r4] ; [16]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 0, m4, m5, m6, m1
pslldq m2, 1 ; [7, 9, 10, 11, 12, 14, 15, 0, 1, 2, 4, 5, x, x, x, x]
palignr m3, m2, 14
pmaddubsw m4, m3, [r4 + 6 * 16] ; [22]
pmulhrsw m4, m7
pslldq m2, 1 ; [9, 10, 11, 12, 14, 15, 0, 1, 2, 4, 5, x, x, x, x, x]
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 + 12 * 16] ; [28]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r4 - 14 * 16] ; [02]
pmulhrsw m5, m7
pslldq m2, 1 ; [10, 11, 12, 14, 15, 0, 1, 2, 4, 5, x, x, x, x, x, x]
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 - 8 * 16] ; [08]
pmulhrsw m6, m7
packuswb m5, m6
pslldq m2, 1 ; [11, 12, 14, 15, 0, 1, 2, 4, 5, x, x, x, x, x, x, x]
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 - 2 * 16] ; [14]
pmulhrsw m6, m7
pslldq m2, 1 ; [12, 14, 15, 0, 1, 2, 4, 5, x, x, x, x, x, x, x, x]
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 + 4 * 16] ; [20]
pmulhrsw m1, m7
packuswb m6, m1
pslldq m2, 1 ; [14, 15, 0, 1, 2, 4, 5, x, x, x, x, x, x, x, x, x]
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 + 10 * 16] ; [26]
pmulhrsw m1, m7
pmaddubsw m3, [r4 - 16 * 16] ; [00]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 1, 0, m4, m5, m6, m1
lea r0, [r6 + 8]
movu m1, [r2 + 1] ; [16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
pslldq m3, m1, 1 ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 x]
punpckhbw m3, m1 ; [16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8]
palignr m2, m2, 6 ; [x, x, x, x, x, 14, 15, 0, 1, 2, 4, 5, x, x, x]
movlhps m2, m1 ; [8 7 6 5 4 3 2 1 0, 2, 3, 5, 6, 8, x, x]
pmaddubsw m4, m3, [r4 - 10 * 16] ; [06]
pmulhrsw m4, m7
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 - 4 * 16] ; [12]
pmulhrsw m5, m7
packuswb m4, m5
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 + 2 * 16] ; [18]
pmulhrsw m5, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 8 * 16] ; [24]
pmulhrsw m6, m7
packuswb m5, m6
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 + 14 * 16] ; [30]
pmulhrsw m6, m7
pmaddubsw m0, m3, [r4 - 12 * 16] ; [04]
pmulhrsw m0, m7
packuswb m6, m0
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 - 6 * 16] ; [10]
pmulhrsw m1, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m0, m3, [r4] ; [16]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, 0, m4, m5, m6, m1
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m4, m3, [r4 + 6 * 16] ; [22]
pmulhrsw m4, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m5, m3, [r4 + 12 * 16] ; [28]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m3, [r4 - 14 * 16] ; [02]
pmulhrsw m5, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 - 8 * 16] ; [08]
pmulhrsw m6, m7
packuswb m5, m6
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m6, m3, [r4 - 2 * 16] ; [14]
pmulhrsw m6, m7
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 + 4 * 16] ; [20]
pmulhrsw m1, m7
packuswb m6, m1
pslldq m2, 1
palignr m3, m2, 14
pmaddubsw m1, m3, [r4 + 10 * 16] ; [26]
pmulhrsw m1, m7
pmaddubsw m3, [r4 - 16 * 16] ; [00]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 1, 0, m4, m5, m6, m1
RET
INIT_XMM sse4
cglobal intra_pred_ang16_18, 4,5,3
movu m0, [r2]
movu m1, [r2 + 32]
mova m2, [c_mode16_18]
pshufb m1, m2
lea r2, [r1 * 2]
lea r3, [r1 * 3]
lea r4, [r1 * 4]
movu [r0], m0
palignr m2, m0, m1, 15
movu [r0 + r1], m2
palignr m2, m0, m1, 14
movu [r0 + r2], m2
palignr m2, m0, m1, 13
movu [r0 + r3], m2
lea r0, [r0 + r4]
palignr m2, m0, m1, 12
movu [r0], m2
palignr m2, m0, m1, 11
movu [r0 + r1], m2
palignr m2, m0, m1, 10
movu [r0 + r2], m2
palignr m2, m0, m1, 9
movu [r0 + r3], m2
lea r0, [r0 + r4]
palignr m2, m0, m1, 8
movu [r0], m2
palignr m2, m0, m1, 7
movu [r0 + r1], m2
palignr m2, m0, m1, 6
movu [r0 + r2], m2
palignr m2, m0, m1, 5
movu [r0 + r3], m2
lea r0, [r0 + r4]
palignr m2, m0, m1, 4
movu [r0], m2
palignr m2, m0, m1, 3
movu [r0 + r1], m2
palignr m2, m0, m1, 2
movu [r0 + r2], m2
palignr m0, m1, 1
movu [r0 + r3], m0
RET
; Process Intra32x32, input 8x8 in [m0, m1, m2, m3, m4, m5, m6, m7], output 8x8
%macro PROC32_8x8 10 ; col4, transpose[0/1] c0, c1, c2, c3, c4, c5, c6, c7
%if %3 == 0
%else
pshufb m0, [r3]
pmaddubsw m0, [r4 + %3 * 16]
pmulhrsw m0, [pw_1024]
%endif
%if %4 == 0
pmovzxbw m1, m1
%else
pshufb m1, [r3]
pmaddubsw m1, [r4 + %4 * 16]
pmulhrsw m1, [pw_1024]
%endif
%if %3 == 0
packuswb m1, m1
movlhps m0, m1
%else
packuswb m0, m1
%endif
mova m1, [pw_1024]
%if %5 == 0
%else
pshufb m2, [r3]
pmaddubsw m2, [r4 + %5 * 16]
pmulhrsw m2, m1
%endif
%if %6 == 0
pmovzxbw m3, m3
%else
pshufb m3, [r3]
pmaddubsw m3, [r4 + %6 * 16]
pmulhrsw m3, m1
%endif
%if %5 == 0
packuswb m3, m3
movlhps m2, m3
%else
packuswb m2, m3
%endif
%if %7 == 0
%else
pshufb m4, [r3]
pmaddubsw m4, [r4 + %7 * 16]
pmulhrsw m4, m1
%endif
%if %8 == 0
pmovzxbw m5, m5
%else
pshufb m5, [r3]
pmaddubsw m5, [r4 + %8 * 16]
pmulhrsw m5, m1
%endif
%if %7 == 0
packuswb m5, m5
movlhps m4, m5
%else
packuswb m4, m5
%endif
%if %9 == 0
%else
pshufb m6, [r3]
pmaddubsw m6, [r4 + %9 * 16]
pmulhrsw m6, m1
%endif
%if %10 == 0
pmovzxbw m7, m7
%else
pshufb m7, [r3]
pmaddubsw m7, [r4 + %10 * 16]
pmulhrsw m7, m1
%endif
%if %9 == 0
packuswb m7, m7
movlhps m6, m7
%else
packuswb m6, m7
%endif
%if %2 == 1
; transpose
punpckhbw m1, m0, m2
punpcklbw m0, m2
punpckhbw m3, m0, m1
punpcklbw m0, m1
punpckhbw m1, m4, m6
punpcklbw m4, m6
punpckhbw m6, m4, m1
punpcklbw m4, m1
punpckhdq m2, m0, m4
punpckldq m0, m4
punpckldq m4, m3, m6
punpckhdq m3, m6
movh [r0 + + %1 * 8], m0
movhps [r0 + r1 + %1 * 8], m0
movh [r0 + r1*2 + %1 * 8], m2
movhps [r0 + r5 + %1 * 8], m2
movh [r6 + %1 * 8], m4
movhps [r6 + r1 + %1 * 8], m4
movh [r6 + r1*2 + %1 * 8], m3
movhps [r6 + r5 + %1 * 8], m3
%else
movh [r0 ], m0
movhps [r0 + r1 ], m0
movh [r0 + r1 * 2], m2
movhps [r0 + r5 ], m2
lea r0, [r0 + r1 * 4]
movh [r0 ], m4
movhps [r0 + r1 ], m4
movh [r0 + r1 * 2], m6
movhps [r0 + r5 ], m6
%endif
%endmacro
%macro MODE_3_33 1
movu m0, [r2 + 1] ; [16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
palignr m1, m0, 1 ; [ x 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
punpckhbw m2, m0, m1 ; [x 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m0, m1 ; [9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
palignr m1, m2, m0, 2 ; [10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2]
pmaddubsw m4, m0, [r3 + 10 * 16] ; [26]
pmulhrsw m4, m7
pmaddubsw m1, [r3 + 4 * 16] ; [20]
pmulhrsw m1, m7
packuswb m4, m1
palignr m5, m2, m0, 4
pmaddubsw m5, [r3 - 2 * 16] ; [14]
pmulhrsw m5, m7
palignr m6, m2, m0, 6
pmaddubsw m6, [r3 - 8 * 16] ; [ 8]
pmulhrsw m6, m7
packuswb m5, m6
palignr m1, m2, m0, 8
pmaddubsw m6, m1, [r3 - 14 * 16] ; [ 2]
pmulhrsw m6, m7
pmaddubsw m1, [r3 + 12 * 16] ; [28]
pmulhrsw m1, m7
packuswb m6, m1
palignr m1, m2, m0, 10
pmaddubsw m1, [r3 + 6 * 16] ; [22]
pmulhrsw m1, m7
palignr m2, m0, 12
pmaddubsw m2, [r3] ; [16]
pmulhrsw m2, m7
packuswb m1, m2
TRANSPOSE_STORE_8x8 0, %1, m4, m5, m6, m1
movu m0, [r2 + 8]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
palignr m5, m2, m0, 2
pmaddubsw m4, m0, [r3 - 6 * 16] ; [10]
pmulhrsw m4, m7
pmaddubsw m1, m5, [r3 - 12 * 16] ; [04]
pmulhrsw m1, m7
packuswb m4, m1
pmaddubsw m5, [r3 + 14 * 16] ; [30]
pmulhrsw m5, m7
palignr m6, m2, m0, 4
pmaddubsw m6, [r3 + 8 * 16] ; [24]
pmulhrsw m6, m7
packuswb m5, m6
palignr m1, m2, m0, 6
pmaddubsw m6, m1, [r3 + 2 * 16] ; [18]
pmulhrsw m6, m7
palignr m1, m2, m0, 8
pmaddubsw m1, [r3 - 4 * 16] ; [12]
pmulhrsw m1, m7
packuswb m6, m1
palignr m1, m2, m0, 10
pmaddubsw m1, [r3 - 10 * 16] ; [06]
pmulhrsw m1, m7
packuswb m1, m1
movhps m1, [r2 + 14] ; [00]
TRANSPOSE_STORE_8x8 1, %1, m4, m5, m6, m1
movu m0, [r2 + 14]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
palignr m1, m2, m0, 2
pmaddubsw m4, m0, [r3 + 10 * 16] ; [26]
pmulhrsw m4, m7
pmaddubsw m1, [r3 + 4 * 16] ; [20]
pmulhrsw m1, m7
packuswb m4, m1
palignr m5, m2, m0, 4
pmaddubsw m5, [r3 - 2 * 16] ; [14]
pmulhrsw m5, m7
palignr m6, m2, m0, 6
pmaddubsw m6, [r3 - 8 * 16] ; [ 8]
pmulhrsw m6, m7
packuswb m5, m6
palignr m1, m2, m0, 8
pmaddubsw m6, m1, [r3 - 14 * 16] ; [ 2]
pmulhrsw m6, m7
pmaddubsw m1, [r3 + 12 * 16] ; [28]
pmulhrsw m1, m7
packuswb m6, m1
palignr m1, m2, m0, 10
pmaddubsw m1, [r3 + 6 * 16] ; [22]
pmulhrsw m1, m7
palignr m2, m0, 12
pmaddubsw m2, [r3] ; [16]
pmulhrsw m2, m7
packuswb m1, m2
TRANSPOSE_STORE_8x8 2, %1, m4, m5, m6, m1
movu m0, [r2 + 21]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
palignr m5, m2, m0, 2
pmaddubsw m4, m0, [r3 - 6 * 16] ; [10]
pmulhrsw m4, m7
pmaddubsw m1, m5, [r3 - 12 * 16] ; [04]
pmulhrsw m1, m7
packuswb m4, m1
pmaddubsw m5, [r3 + 14 * 16] ; [30]
pmulhrsw m5, m7
palignr m6, m2, m0, 4
pmaddubsw m6, [r3 + 8 * 16] ; [24]
pmulhrsw m6, m7
packuswb m5, m6
palignr m1, m2, m0, 6
pmaddubsw m6, m1, [r3 + 2 * 16] ; [18]
pmulhrsw m6, m7
palignr m1, m2, m0, 8
pmaddubsw m1, [r3 - 4 * 16] ; [12]
pmulhrsw m1, m7
packuswb m6, m1
palignr m1, m2, m0, 10
pmaddubsw m1, [r3 - 10 * 16] ; [06]
pmulhrsw m1, m7
packuswb m1, m1
movhps m1, [r2 + 27] ; [00]
TRANSPOSE_STORE_8x8 3, %1, m4, m5, m6, m1
%endmacro
%macro MODE_4_32 1
movu m0, [r2 + 1]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
palignr m1, m2, m0, 2
mova m5, m1
pmaddubsw m4, m0, [r3 + 5 * 16] ; [21]
pmulhrsw m4, m7
pmaddubsw m1, [r3 - 6 * 16] ; [10]
pmulhrsw m1, m7
packuswb m4, m1
pmaddubsw m5, [r3 + 15 * 16] ; [31]
pmulhrsw m5, m7
palignr m6, m2, m0, 4
pmaddubsw m6, [r3 + 4 * 16] ; [ 20]
pmulhrsw m6, m7
packuswb m5, m6
palignr m1, m2, m0, 6
pmaddubsw m6, m1, [r3 - 7 * 16] ; [ 9]
pmulhrsw m6, m7
pmaddubsw m1, [r3 + 14 * 16] ; [30]
pmulhrsw m1, m7
packuswb m6, m1
palignr m1, m2, m0, 8
pmaddubsw m1, [r3 + 3 * 16] ; [19]
pmulhrsw m1, m7
palignr m2, m0, 10
pmaddubsw m3, m2, [r3 - 8 * 16] ; [8]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 0, %1, m4, m5, m6, m1
pmaddubsw m4, m2, [r3 + 13 * 16] ; [29]
pmulhrsw m4, m7
movu m0, [r2 + 6]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
palignr m1, m2, m0, 2
pmaddubsw m1, [r3 + 2 * 16] ; [18]
pmulhrsw m1, m7
packuswb m4, m1
palignr m5, m2, m0, 4
mova m6, m5
pmaddubsw m5, [r3 - 9 * 16] ; [07]
pmulhrsw m5, m7
pmaddubsw m6, [r3 + 12 * 16] ; [28]
pmulhrsw m6, m7
packuswb m5, m6
palignr m6, m2, m0, 6
pmaddubsw m6, [r3 + 16] ; [17]
pmulhrsw m6, m7
palignr m1, m2, m0, 8
pmaddubsw m3, m1, [r3 - 10 * 16] ; [06]
pmulhrsw m3, m7
packuswb m6, m3
pmaddubsw m1, [r3 + 11 * 16] ; [27]
pmulhrsw m1, m7
palignr m2, m0, 10
pmaddubsw m2, [r3] ; [16]
pmulhrsw m2, m7
packuswb m1, m2
TRANSPOSE_STORE_8x8 1, %1, m4, m5, m6, m1
movu m0, [r2 + 12]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
mova m1, m0
pmaddubsw m4, m0, [r3 - 11 * 16] ; [5]
pmulhrsw m4, m7
pmaddubsw m1, [r3 + 10 * 16] ; [26]
pmulhrsw m1, m7
packuswb m4, m1
palignr m5, m2, m0, 2
pmaddubsw m5, [r3 - 16] ; [15]
pmulhrsw m5, m7
palignr m6, m2, m0, 4
mova m1, m6
pmaddubsw m1, [r3 - 12 * 16] ; [4]
pmulhrsw m1, m7
packuswb m5, m1
pmaddubsw m6, [r3 + 9 * 16] ; [25]
pmulhrsw m6, m7
palignr m1, m2, m0, 6
pmaddubsw m1, [r3 - 2 * 16] ; [14]
pmulhrsw m1, m7
packuswb m6, m1
palignr m1, m2, m0, 8
mova m2, m1
pmaddubsw m1, [r3 - 13 * 16] ; [3]
pmulhrsw m1, m7
pmaddubsw m2, [r3 + 8 * 16] ; [24]
pmulhrsw m2, m7
packuswb m1, m2
TRANSPOSE_STORE_8x8 2, %1, m4, m5, m6, m1
movu m0, [r2 + 17]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
pmaddubsw m4, m0, [r3 - 3 * 16] ; [13]
pmulhrsw m4, m7
palignr m5, m2, m0, 2
pmaddubsw m1, m5, [r3 - 14 * 16] ; [2]
pmulhrsw m1, m7
packuswb m4, m1
pmaddubsw m5, [r3 + 7 * 16] ; [23]
pmulhrsw m5, m7
palignr m6, m2, m0, 4
pmaddubsw m6, [r3 - 4 * 16] ; [12]
pmulhrsw m6, m7
packuswb m5, m6
palignr m6, m2, m0, 6
mova m1, m6
pmaddubsw m6, [r3 - 15 * 16] ; [1]
pmulhrsw m6, m7
pmaddubsw m1, [r3 + 6 * 16] ; [22]
pmulhrsw m1, m7
packuswb m6, m1
palignr m1, m2, m0, 8
pmaddubsw m1, [r3 - 5 * 16] ; [11]
pmulhrsw m1, m7
packuswb m1, m1
movhps m1, [r2 + 22] ; [00]
TRANSPOSE_STORE_8x8 3, %1, m4, m5, m6, m1
%endmacro
%macro MODE_5_31 1
movu m0, [r2 + 1]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
palignr m1, m2, m0, 2
mova m5, m1
pmaddubsw m4, m0, [r3 + 16] ; [17]
pmulhrsw m4, m7
pmaddubsw m1, [r3 - 14 * 16] ; [2]
pmulhrsw m1, m7
packuswb m4, m1
pmaddubsw m5, [r3 + 3 * 16] ; [19]
pmulhrsw m5, m7
palignr m6, m2, m0, 4
mova m1, m6
pmaddubsw m6, [r3 - 12 * 16] ; [4]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m1, [r3 + 5 * 16] ; [21]
pmulhrsw m6, m7
palignr m1, m2, m0, 6
mova m3, m1
pmaddubsw m3, [r3 - 10 * 16] ; [6]
pmulhrsw m3, m7
packuswb m6, m3
pmaddubsw m1, [r3 + 7 * 16] ; [23]
pmulhrsw m1, m7
palignr m2, m0, 8
pmaddubsw m2, [r3 - 8 * 16] ; [8]
pmulhrsw m2, m7
packuswb m1, m2
TRANSPOSE_STORE_8x8 0, %1, m4, m5, m6, m1
movu m0, [r2 + 5]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
palignr m1, m2, m0, 2
mova m5, m1
pmaddubsw m4, m0, [r3 + 9 * 16] ; [25]
pmulhrsw m4, m7
pmaddubsw m1, [r3 - 6 * 16] ; [10]
pmulhrsw m1, m7
packuswb m4, m1
pmaddubsw m5, [r3 + 11 * 16] ; [27]
pmulhrsw m5, m7
palignr m6, m2, m0, 4
mova m1, m6
pmaddubsw m6, [r3 - 4 * 16] ; [12]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m1, [r3 + 13 * 16] ; [29]
pmulhrsw m6, m7
palignr m1, m2, m0, 6
mova m3, m1
pmaddubsw m3, [r3 - 2 * 16] ; [14]
pmulhrsw m3, m7
packuswb m6, m3
pmaddubsw m1, [r3 + 15 * 16] ; [31]
pmulhrsw m1, m7
palignr m2, m0, 8
pmaddubsw m2, [r3] ; [16]
pmulhrsw m2, m7
packuswb m1, m2
TRANSPOSE_STORE_8x8 1, %1, m4, m5, m6, m1
movu m0, [r2 + 10]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
mova m1, m0
pmaddubsw m4, m0, [r3 - 15 * 16] ; [1]
pmulhrsw m4, m7
pmaddubsw m1, [r3 + 2 * 16] ; [18]
pmulhrsw m1, m7
packuswb m4, m1
palignr m5, m2, m0, 2
mova m1, m5
pmaddubsw m5, [r3 - 13 * 16] ; [3]
pmulhrsw m5, m7
pmaddubsw m1, [r3 + 4 * 16] ; [20]
pmulhrsw m1, m7
packuswb m5, m1
palignr m1, m2, m0, 4
pmaddubsw m6, m1, [r3 - 11 * 16] ; [5]
pmulhrsw m6, m7
pmaddubsw m1, [r3 + 6 * 16] ; [22]
pmulhrsw m1, m7
packuswb m6, m1
palignr m2, m0, 6
pmaddubsw m1, m2, [r3 - 9 * 16] ; [7]
pmulhrsw m1, m7
pmaddubsw m2, [r3 + 8 * 16] ; [24]
pmulhrsw m2, m7
packuswb m1, m2
TRANSPOSE_STORE_8x8 2, %1, m4, m5, m6, m1
movu m0, [r2 + 14]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
mova m1, m0
pmaddubsw m4, m0, [r3 - 7 * 16] ; [9]
pmulhrsw m4, m7
pmaddubsw m1, [r3 + 10 * 16] ; [26]
pmulhrsw m1, m7
packuswb m4, m1
palignr m5, m2, m0, 2
mova m1, m5
pmaddubsw m5, [r3 - 5 * 16] ; [11]
pmulhrsw m5, m7
pmaddubsw m1, [r3 + 12 * 16] ; [28]
pmulhrsw m1, m7
packuswb m5, m1
palignr m1, m2, m0, 4
pmaddubsw m6, m1, [r3 - 3 * 16] ; [13]
pmulhrsw m6, m7
pmaddubsw m1, [r3 + 14 * 16] ; [30]
pmulhrsw m1, m7
packuswb m6, m1
palignr m2, m0, 6
pmaddubsw m1, m2, [r3 - 16] ; [15]
pmulhrsw m1, m7
packuswb m1, m1
movhps m1, [r2 + 18] ; [00]
TRANSPOSE_STORE_8x8 3, %1, m4, m5, m6, m1
%endmacro
%macro MODE_6_30 1
movu m0, [r2 + 1]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
mova m1, m0
pmaddubsw m4, m0, [r3 - 3 * 16] ; [13]
pmulhrsw m4, m7
pmaddubsw m1, [r3 + 10 * 16] ; [26]
pmulhrsw m1, m7
packuswb m4, m1
palignr m6, m2, m0, 2
pmaddubsw m5, m6, [r3 - 9 * 16] ; [7]
pmulhrsw m5, m7
pmaddubsw m6, [r3 + 4 * 16] ; [20]
pmulhrsw m6, m7
packuswb m5, m6
palignr m1, m2, m0, 4
pmaddubsw m6, m1, [r3 - 15 * 16] ; [1]
pmulhrsw m6, m7
pmaddubsw m3, m1, [r3 - 2 * 16] ; [14]
pmulhrsw m3, m7
packuswb m6, m3
pmaddubsw m1, [r3 + 11 * 16] ; [27]
pmulhrsw m1, m7
palignr m2, m0, 6
pmaddubsw m3, m2, [r3 - 8 * 16] ; [8]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 0, %1, m4, m5, m6, m1
pmaddubsw m4, m2, [r3 + 5 * 16] ; [21]
pmulhrsw m4, m7
movu m0, [r2 + 5]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
mova m6, m0
pmaddubsw m1, m6, [r3 - 14 * 16] ; [2]
pmulhrsw m1, m7
packuswb m4, m1
pmaddubsw m5, m6, [r3 - 16] ; [15]
pmulhrsw m5, m7
pmaddubsw m6, [r3 + 12 * 16] ; [28]
pmulhrsw m6, m7
packuswb m5, m6
palignr m3, m2, m0, 2
pmaddubsw m6, m3, [r3 - 7 * 16] ; [9]
pmulhrsw m6, m7
pmaddubsw m3, [r3 + 6 * 16] ; [22]
pmulhrsw m3, m7
packuswb m6, m3
palignr m2, m0, 4
pmaddubsw m1, m2, [r3 - 13 * 16] ; [3]
pmulhrsw m1, m7
pmaddubsw m3, m2, [r3] ; [16]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 1, %1, m4, m5, m6, m1
pmaddubsw m4, m2, [r3 + 13 * 16] ; [29]
pmulhrsw m4, m7
movu m0, [r2 + 7]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
palignr m5, m2, m0, 2
pmaddubsw m1, m5, [r3 - 6 * 16] ; [10]
pmulhrsw m1, m7
packuswb m4, m1
pmaddubsw m5, [r3 + 7 * 16] ; [23]
pmulhrsw m5, m7
palignr m1, m2, m0, 4
pmaddubsw m6, m1, [r3 - 12 * 16] ; [4]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m1, [r3 + 16] ; [17]
pmulhrsw m6, m7
pmaddubsw m1, [r3 + 14 * 16] ; [30]
pmulhrsw m1, m7
packuswb m6, m1
palignr m2, m2, m0, 6
pmaddubsw m1, m2, [r3 - 5 * 16] ; [11]
pmulhrsw m1, m7
pmaddubsw m2, m2, [r3 + 8 * 16] ; [24]
pmulhrsw m2, m7
packuswb m1, m2
TRANSPOSE_STORE_8x8 2, %1, m4, m5, m6, m1
movu m0, [r2 + 11]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
mova m5, m0
pmaddubsw m4, m0, [r3 - 11 * 16] ; [5]
pmulhrsw m4, m7
pmaddubsw m3, m5, [r3 + 2 * 16] ; [18]
pmulhrsw m3, m7
packuswb m4, m3
pmaddubsw m5, [r3 + 15 * 16] ; [31]
pmulhrsw m5, m7
palignr m6, m2, m0, 2
pmaddubsw m1, m6, [r3 - 4 * 16] ; [12]
pmulhrsw m1, m7
packuswb m5, m1
pmaddubsw m6, [r3 + 9 * 16] ; [25]
pmulhrsw m6, m7
palignr m1, m2, m0, 4
pmaddubsw m2, m1, [r3 - 10 * 16] ; [6]
pmulhrsw m2, m7
packuswb m6, m2
pmaddubsw m1, [r3 + 3 * 16] ; [19]
pmulhrsw m1, m7
packuswb m1, m1
movhps m1, [r2 + 14] ; [00]
TRANSPOSE_STORE_8x8 3, %1, m4, m5, m6, m1
%endmacro
%macro MODE_7_29 1
movu m0, [r2 + 1]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
mova m5, m0
pmaddubsw m4, m0, [r3 - 7 * 16] ; [9]
pmulhrsw m4, m7
pmaddubsw m3, m5, [r3 + 2 * 16] ; [18]
pmulhrsw m3, m7
packuswb m4, m3
pmaddubsw m5, [r3 + 11 * 16] ; [27]
pmulhrsw m5, m7
palignr m1, m2, m0, 2
palignr m2, m0, 4
pmaddubsw m6, m1, [r3 - 12 * 16] ; [4]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m1, [r3 - 3 * 16] ; [13]
pmulhrsw m6, m7
pmaddubsw m0, m1, [r3 + 6 * 16] ; [22]
pmulhrsw m0, m7
packuswb m6, m0
pmaddubsw m1, [r3 + 15 * 16] ; [31]
pmulhrsw m1, m7
pmaddubsw m0, m2, [r3 - 8 * 16] ; [8]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, %1, m4, m5, m6, m1
pmaddubsw m4, m2, [r3 + 16] ; [17]
pmulhrsw m4, m7
pmaddubsw m2, [r3 + 10 * 16] ; [26]
pmulhrsw m2, m7
packuswb m4, m2
movu m0, [r2 + 4]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
palignr m2, m0, 2
pmaddubsw m5, m0, [r3 - 13 * 16] ; [03]
pmulhrsw m5, m7
pmaddubsw m6, m0, [r3 - 4 * 16] ; [12]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m0, [r3 + 5 * 16] ; [21]
pmulhrsw m6, m7
pmaddubsw m0, [r3 + 14 * 16] ; [30]
pmulhrsw m0, m7
packuswb m6, m0
pmaddubsw m1, m2, [r3 - 9 * 16] ; [07]
pmulhrsw m1, m7
pmaddubsw m3, m2, [r3] ; [16]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 1, %1, m4, m5, m6, m1
pmaddubsw m4, m2, [r3 + 9 * 16] ; [25]
pmulhrsw m4, m7
movu m0, [r2 + 6]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
palignr m2, m0, 2
pmaddubsw m1, m0, [r3 - 14 * 16] ; [2]
pmulhrsw m1, m7
packuswb m4, m1
pmaddubsw m5, m0, [r3 - 5 * 16] ; [11]
pmulhrsw m5, m7
pmaddubsw m6, m0, [r3 + 4 * 16] ; [20]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m0, [r3 + 13 * 16] ; [29]
pmulhrsw m6, m7
pmaddubsw m1, m2, [r3 - 10 * 16] ; [6]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m1, m2, [r3 - 16] ; [15]
pmulhrsw m1, m7
pmaddubsw m2, m2, [r3 + 8 * 16] ; [24]
pmulhrsw m2, m7
packuswb m1, m2
TRANSPOSE_STORE_8x8 2, %1, m4, m5, m6, m1
movu m0, [r2 + 8]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
pmaddubsw m4, m0, [r3 - 15 * 16] ; [1]
pmulhrsw m4, m7
pmaddubsw m3, m0, [r3 - 6 * 16] ; [10]
pmulhrsw m3, m7
packuswb m4, m3
pmaddubsw m5, m0, [r3 + 3 * 16] ; [19]
pmulhrsw m5, m7
pmaddubsw m6, m0, [r3 + 12 * 16] ; [28]
pmulhrsw m6, m7
packuswb m5, m6
palignr m2, m0, 2
pmaddubsw m6, m2, [r3 - 11 * 16] ; [5]
pmulhrsw m6, m7
pmaddubsw m0, m2, [r3 - 2 * 16] ; [14]
pmulhrsw m0, m7
packuswb m6, m0
pmaddubsw m1, m2, [r3 + 7 * 16] ; [23]
pmulhrsw m1, m7
packuswb m1, m1
movhps m1, [r2 + 10] ; [0]
TRANSPOSE_STORE_8x8 3, %1, m4, m5, m6, m1
%endmacro
%macro MODE_8_28 1
movu m0, [r2 + 1]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
palignr m2, m0, 2
pmaddubsw m4, m0, [r3 - 11 * 16] ; [5]
pmulhrsw m4, m7
pmaddubsw m3, m0, [r3 - 6 * 16] ; [10]
pmulhrsw m3, m7
packuswb m4, m3
pmaddubsw m5, m0, [r3 - 1 * 16] ; [15]
pmulhrsw m5, m7
pmaddubsw m6, m0, [r3 + 4 * 16] ; [20]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m0, [r3 + 9 * 16] ; [25]
pmulhrsw m6, m7
pmaddubsw m0, [r3 + 14 * 16] ; [30]
pmulhrsw m0, m7
packuswb m6, m0
pmaddubsw m1, m2, [r3 - 13 * 16] ; [3]
pmulhrsw m1, m7
pmaddubsw m0, m2, [r3 - 8 * 16] ; [8]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, %1, m4, m5, m6, m1
pmaddubsw m4, m2, [r3 - 3 * 16] ; [13]
pmulhrsw m4, m7
pmaddubsw m5, m2, [r3 + 2 * 16] ; [18]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m2, [r3 + 7 * 16] ; [23]
pmulhrsw m5, m7
pmaddubsw m2, [r3 + 12 * 16] ; [28]
pmulhrsw m2, m7
packuswb m5, m2
movu m0, [r2 + 3]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
pmaddubsw m6, m0, [r3 - 15 * 16] ; [01]
pmulhrsw m6, m7
pmaddubsw m1, m0, [r3 - 10 * 16] ; [06]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m1, m0, [r3 - 5 * 16] ; [11]
pmulhrsw m1, m7
mova m2, m0
pmaddubsw m0, [r3] ; [16]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 1, %1, m4, m5, m6, m1
pmaddubsw m4, m2, [r3 + 5 * 16] ; [21]
pmulhrsw m4, m7
pmaddubsw m5, m2, [r3 + 10 * 16] ; [26]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m2, [r3 + 15 * 16] ; [31]
pmulhrsw m5, m7
movu m0, [r2 + 4]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
pmaddubsw m2, m0, [r3 - 12 * 16] ; [4]
pmulhrsw m2, m7
packuswb m5, m2
pmaddubsw m6, m0, [r3 - 7 * 16] ; [9]
pmulhrsw m6, m7
pmaddubsw m1, m0, [r3 - 2 * 16] ; [14]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m1, m0, [r3 + 3 * 16] ; [19]
pmulhrsw m1, m7
mova m2, m0
pmaddubsw m0, [r3 + 8 * 16] ; [24]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 2, %1, m4, m5, m6, m1
pmaddubsw m4, m2, [r3 + 13 * 16] ; [29]
pmulhrsw m4, m7
movu m0, [r2 + 5]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
pmaddubsw m1, m0, [r3 - 14 * 16] ; [2]
pmulhrsw m1, m7
packuswb m4, m1
pmaddubsw m5, m0, [r3 - 9 * 16] ; [7]
pmulhrsw m5, m7
pmaddubsw m6, m0, [r3 - 4 * 16] ; [12]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m0, [r3 + 16] ; [17]
pmulhrsw m6, m7
pmaddubsw m1, m0, [r3 + 6 * 16] ; [22]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m1, m0, [r3 + 11 * 16] ; [27]
pmulhrsw m1, m7
packuswb m1, m1
movhps m1, [r2 + 6] ; [00]
TRANSPOSE_STORE_8x8 3, %1, m4, m5, m6, m1
%endmacro
%macro MODE_9_27 1
movu m2, [r2 + 1]
palignr m1, m2, 1
punpckhbw m0, m2, m1
punpcklbw m2, m1
pmaddubsw m4, m2, [r3 - 14 * 16] ; [2]
pmulhrsw m4, m7
pmaddubsw m3, m2, [r3 - 12 * 16] ; [4]
pmulhrsw m3, m7
packuswb m4, m3
pmaddubsw m5, m2, [r3 - 10 * 16] ; [6]
pmulhrsw m5, m7
pmaddubsw m6, m2, [r3 - 8 * 16] ; [8]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m2, [r3 - 6 * 16] ; [10]
pmulhrsw m6, m7
pmaddubsw m3, m2, [r3 - 4 * 16] ; [12]
pmulhrsw m3, m7
packuswb m6, m3
pmaddubsw m1, m2, [r3 - 2 * 16] ; [14]
pmulhrsw m1, m7
pmaddubsw m0, m2, [r3] ; [16]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 0, %1, m4, m5, m6, m1
pmaddubsw m4, m2, [r3 + 2 * 16] ; [18]
pmulhrsw m4, m7
pmaddubsw m5, m2, [r3 + 4 * 16] ; [20]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m2, [r3 + 6 * 16] ; [22]
pmulhrsw m5, m7
pmaddubsw m6, m2, [r3 + 8 * 16] ; [24]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m2, [r3 + 10 * 16] ; [26]
pmulhrsw m6, m7
pmaddubsw m1, m2, [r3 + 12 * 16] ; [28]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m1, m2, [r3 + 14 * 16] ; [30]
pmulhrsw m1, m7
packuswb m1, m1
movhps m1, [r2 + 2] ; [00]
TRANSPOSE_STORE_8x8 1, %1, m4, m5, m6, m1
movu m2, [r2 + 2]
palignr m1, m2, 1
punpcklbw m2, m1
pmaddubsw m4, m2, [r3 - 14 * 16] ; [2]
pmulhrsw m4, m7
pmaddubsw m3, m2, [r3 - 12 * 16] ; [4]
pmulhrsw m3, m7
packuswb m4, m3
pmaddubsw m5, m2, [r3 - 10 * 16] ; [6]
pmulhrsw m5, m7
pmaddubsw m6, m2, [r3 - 8 * 16] ; [8]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m2, [r3 - 6 * 16] ; [10]
pmulhrsw m6, m7
pmaddubsw m0, m2, [r3 - 4 * 16] ; [12]
pmulhrsw m0, m7
packuswb m6, m0
pmaddubsw m1, m2, [r3 - 2 * 16] ; [14]
pmulhrsw m1, m7
pmaddubsw m0, m2, [r3] ; [16]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 2, %1, m4, m5, m6, m1
movu m2, [r2 + 2]
palignr m1, m2, 1
punpcklbw m2, m1
pmaddubsw m4, m2, [r3 + 2 * 16] ; [18]
pmulhrsw m4, m7
pmaddubsw m5, m2, [r3 + 4 * 16] ; [20]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m2, [r3 + 6 * 16] ; [22]
pmulhrsw m5, m7
pmaddubsw m6, m2, [r3 + 8 * 16] ; [24]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m2, [r3 + 10 * 16] ; [26]
pmulhrsw m6, m7
pmaddubsw m1, m2, [r3 + 12 * 16] ; [28]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m1, m2, [r3 + 14 * 16] ; [30]
pmulhrsw m1, m7
packuswb m1, m1
movhps m1, [r2 + 3] ; [00]
TRANSPOSE_STORE_8x8 3, %1, m4, m5, m6, m1
%endmacro
%macro MODE_12_24 1
movu m2, [r2]
palignr m1, m2, 1
punpckhbw m0, m2, m1
punpcklbw m2, m1
palignr m0, m2, 2
pmaddubsw m4, m0, [r4 + 11 * 16] ; [27]
pmulhrsw m4, m7
pmaddubsw m3, m0, [r4 + 6 * 16] ; [22]
pmulhrsw m3, m7
packuswb m4, m3
pmaddubsw m5, m0, [r4 + 16] ; [17]
pmulhrsw m5, m7
pmaddubsw m6, m0, [r4 - 4 * 16] ; [12]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m0, [r4 - 9 * 16] ; [7]
pmulhrsw m6, m7
pmaddubsw m3, m0, [r4 - 14 * 16] ; [2]
pmulhrsw m3, m7
packuswb m6, m3
pmaddubsw m1, m2, [r4 + 13 * 16] ; [29]
pmulhrsw m1, m7
pmaddubsw m3, m2, [r4 + 8 * 16] ; [24]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 0, %1, m4, m5, m6, m1
pmaddubsw m4, m2, [r4 + 3 * 16] ; [19]
pmulhrsw m4, m7
pmaddubsw m5, m2, [r4 - 2 * 16] ; [14]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m2, [r4 - 7 * 16] ; [09]
pmulhrsw m5, m7
pmaddubsw m6, m2, [r4 - 12 * 16] ; [04]
pmulhrsw m6, m7
packuswb m5, m6
movu m0, [r2 - 2]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
palignr m2, m0, 2
pmaddubsw m6, m2, [r4 + 15 * 16] ; [31]
pmulhrsw m6, m7
pmaddubsw m1, m2, [r4 + 10 * 16] ; [26]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m1, m2, [r4 + 5 * 16] ; [21]
pmulhrsw m1, m7
pmaddubsw m3, m2, [r4] ; [16]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 1, %1, m4, m5, m6, m1
pmaddubsw m4, m2, [r4 - 5 * 16] ; [11]
pmulhrsw m4, m7
pmaddubsw m3, m2, [r4 - 10 * 16] ; [06]
pmulhrsw m3, m7
packuswb m4, m3
pmaddubsw m5, m2, [r4 - 15 * 16] ; [1]
pmulhrsw m5, m7
movu m0, [r2 - 3]
palignr m1, m0, 1
punpckhbw m2, m0, m1
punpcklbw m0, m1
palignr m2, m0, 2
pmaddubsw m6, m2, [r4 + 12 * 16] ; [28]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m2, [r4 + 7 * 16] ; [23]
pmulhrsw m6, m7
pmaddubsw m3, m2, [r4 + 2 * 16] ; [18]
pmulhrsw m3, m7
packuswb m6, m3
pmaddubsw m1, m2, [r4 - 3 * 16] ; [13]
pmulhrsw m1, m7
pmaddubsw m3, m2, [r4 - 8 * 16] ; [8]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 2, %1, m4, m5, m6, m1
pmaddubsw m4, m2, [r4 - 13 * 16] ; [3]
pmulhrsw m4, m7
movu m2, [r2 - 4]
palignr m1, m2, 1
punpckhbw m0, m2, m1
punpcklbw m2, m1
palignr m0, m2, 2
pmaddubsw m5, m0, [r4 + 14 * 16] ; [30]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m0, [r4 + 9 * 16] ; [25]
pmulhrsw m5, m7
pmaddubsw m6, m0, [r4 + 4 * 16] ; [20]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m0, [r4 - 16] ; [15]
pmulhrsw m6, m7
pmaddubsw m1, m0, [r4 - 6 * 16] ; [10]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m1, m0, [r4 - 11 * 16] ; [05]
pmulhrsw m1, m7
movu m2, [pb_fact0]
pshufb m0, m2
pmovzxbw m0, m0
packuswb m1, m0
TRANSPOSE_STORE_8x8 3, %1, m4, m5, m6, m1
%endmacro
;------------------------------------------------------------------------------------------
; void intraPredAng32(pixel* dst, intptr_t dstStride, pixel* src, int dirMode, int bFilter)
;------------------------------------------------------------------------------------------
INIT_XMM ssse3
cglobal intra_pred_ang32_2, 3,5,4
lea r4, [r2]
add r2, 64
cmp r3m, byte 34
cmove r2, r4
movu m0, [r2 + 2]
movu m1, [r2 + 18]
movu m3, [r2 + 34]
lea r3, [r1 * 3]
movu [r0], m0
movu [r0 + 16], m1
palignr m2, m1, m0, 1
movu [r0 + r1], m2
palignr m2, m3, m1, 1
movu [r0 + r1 + 16], m2
palignr m2, m1, m0, 2
movu [r0 + r1 * 2], m2
palignr m2, m3, m1, 2
movu [r0 + r1 * 2 + 16], m2
palignr m2, m1, m0, 3
movu [r0 + r3], m2
palignr m2, m3, m1, 3
movu [r0 + r3 + 16], m2
lea r0, [r0 + r1 * 4]
palignr m2, m1, m0, 4
movu [r0], m2
palignr m2, m3, m1, 4
movu [r0 + 16], m2
palignr m2, m1, m0, 5
movu [r0 + r1], m2
palignr m2, m3, m1, 5
movu [r0 + r1 + 16], m2
palignr m2, m1, m0, 6
movu [r0 + r1 * 2], m2
palignr m2, m3, m1, 6
movu [r0 + r1 * 2 + 16], m2
palignr m2, m1, m0, 7
movu [r0 + r3], m2
palignr m2, m3, m1, 7
movu [r0 + r3 + 16], m2
lea r0, [r0 + r1 * 4]
palignr m2, m1, m0, 8
movu [r0], m2
palignr m2, m3, m1, 8
movu [r0 + 16], m2
palignr m2, m1, m0, 9
movu [r0 + r1], m2
palignr m2, m3, m1, 9
movu [r0 + r1 + 16], m2
palignr m2, m1, m0, 10
movu [r0 + r1 * 2], m2
palignr m2, m3, m1, 10
movu [r0 + r1 * 2 + 16], m2
palignr m2, m1, m0, 11
movu [r0 + r3], m2
palignr m2, m3, m1, 11
movu [r0 + r3 + 16], m2
lea r0, [r0 + r1 * 4]
palignr m2, m1, m0, 12
movu [r0], m2
palignr m2, m3, m1, 12
movu [r0 + 16], m2
palignr m2, m1, m0, 13
movu [r0 + r1], m2
palignr m2, m3, m1, 13
movu [r0 + r1 + 16], m2
palignr m2, m1, m0, 14
movu [r0 + r1 * 2], m2
palignr m2, m3, m1, 14
movu [r0 + r1 * 2 + 16], m2
palignr m2, m1, m0, 15
movu [r0 + r3], m2
palignr m2, m3, m1, 15
movu [r0 + r3 + 16], m2
lea r0, [r0 + r1 * 4]
movu [r0], m1
movu m0, [r2 + 50]
movu [r0 + 16], m3
palignr m2, m3, m1, 1
movu [r0 + r1], m2
palignr m2, m0, m3, 1
movu [r0 + r1 + 16], m2
palignr m2, m3, m1, 2
movu [r0 + r1 * 2], m2
palignr m2, m0, m3, 2
movu [r0 + r1 * 2 + 16], m2
palignr m2, m3, m1, 3
movu [r0 + r3], m2
palignr m2, m0, m3, 3
movu [r0 + r3 + 16], m2
lea r0, [r0 + r1 * 4]
palignr m2, m3, m1, 4
movu [r0], m2
palignr m2, m0, m3, 4
movu [r0 + 16], m2
palignr m2, m3, m1, 5
movu [r0 + r1], m2
palignr m2, m0, m3, 5
movu [r0 + r1 + 16], m2
palignr m2, m3, m1, 6
movu [r0 + r1 * 2], m2
palignr m2, m0, m3, 6
movu [r0 + r1 * 2 + 16], m2
palignr m2, m3, m1, 7
movu [r0 + r3], m2
palignr m2, m0, m3, 7
movu [r0 + r3 + 16], m2
lea r0, [r0 + r1 * 4]
palignr m2, m3, m1, 8
movu [r0], m2
palignr m2, m0, m3, 8
movu [r0 + 16], m2
palignr m2, m3, m1, 9
movu [r0 + r1], m2
palignr m2, m0, m3, 9
movu [r0 + r1 + 16], m2
palignr m2, m3, m1, 10
movu [r0 + r1 * 2], m2
palignr m2, m0, m3, 10
movu [r0 + r1 * 2 + 16], m2
palignr m2, m3, m1, 11
movu [r0 + r3], m2
palignr m2, m0, m3, 11
movu [r0 + r3 + 16], m2
lea r0, [r0 + r1 * 4]
palignr m2, m3, m1, 12
movu [r0], m2
palignr m2, m0, m3, 12
movu [r0 + 16], m2
palignr m2, m3, m1, 13
movu [r0 + r1], m2
palignr m2, m0, m3, 13
movu [r0 + r1 + 16], m2
palignr m2, m3, m1, 14
movu [r0 + r1 * 2], m2
palignr m2, m0, m3, 14
movu [r0 + r1 * 2 + 16], m2
palignr m2, m3, m1, 15
movu [r0 + r3], m2
palignr m2, m0, m3, 15
movu [r0 + r3 + 16], m2
RET
INIT_XMM sse4
cglobal intra_pred_ang32_3, 3,7,8
add r2, 64
lea r3, [ang_table + 16 * 16]
mov r4d, 4
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0 + r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
.loop:
MODE_3_33 1
lea r0, [r6 + r1 * 4]
lea r6, [r6 + r1 * 8]
add r2, 8
dec r4
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang32_4, 3,7,8
add r2, 64
lea r3, [ang_table + 16 * 16]
mov r4d, 4
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0 + r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
.loop:
MODE_4_32 1
lea r0, [r6 + r1 * 4]
lea r6, [r6 + r1 * 8]
add r2, 8
dec r4
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang32_5, 3,7,8
add r2, 64
lea r3, [ang_table + 16 * 16]
mov r4d, 4
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0 + r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
.loop:
MODE_5_31 1
lea r0, [r6 + r1 * 4]
lea r6, [r6 + r1 * 8]
add r2, 8
dec r4
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang32_6, 3,7,8
add r2, 64
lea r3, [ang_table + 16 * 16]
mov r4d, 4
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0 + r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
.loop:
MODE_6_30 1
lea r0, [r6 + r1 * 4]
lea r6, [r6 + r1 * 8]
add r2, 8
dec r4
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang32_7, 3,7,8
add r2, 64
lea r3, [ang_table + 16 * 16]
mov r4d, 4
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0 + r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
.loop:
MODE_7_29 1
lea r0, [r6 + r1 * 4]
lea r6, [r6 + r1 * 8]
add r2, 8
dec r4
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang32_8, 3,7,8
add r2, 64
lea r3, [ang_table + 16 * 16]
mov r4d, 4
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0 + r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
.loop:
MODE_8_28 1
lea r0, [r6 + r1 * 4]
lea r6, [r6 + r1 * 8]
add r2, 8
dec r4
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang32_9, 3,7,8
add r2, 64
lea r3, [ang_table + 16 * 16]
mov r4d, 4
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0 + r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
.loop:
MODE_9_27 1
lea r0, [r6 + r1 * 4]
lea r6, [r6 + r1 * 8]
add r2, 8
dec r4
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang32_10, 5,7,8,0-(2*mmsize)
%define m8 [rsp + 0 * mmsize]
%define m9 [rsp + 1 * mmsize]
pxor m7, m7
mov r6, 2
movu m0, [r2]
movu m1, [r2 + 1]
mova m8, m0
mova m9, m1
mov r3d, r4d
lea r4, [r1 * 3]
.loop:
movu m0, [r2 + 1 + 64]
palignr m1, m0, 1
pshufb m1, m7
palignr m2, m0, 2
pshufb m2, m7
palignr m3, m0, 3
pshufb m3, m7
palignr m4, m0, 4
pshufb m4, m7
palignr m5, m0, 5
pshufb m5, m7
palignr m6, m0, 6
pshufb m6, m7
movu [r0 + r1], m1
movu [r0 + r1 + 16], m1
movu [r0 + r1 * 2], m2
movu [r0 + r1 * 2 + 16], m2
movu [r0 + r4], m3
movu [r0 + r4 + 16], m3
lea r5, [r0 + r1 * 4]
movu [r5], m4
movu [r5 + 16], m4
movu [r5 + r1], m5
movu [r5 + r1 + 16], m5
movu [r5 + r1 * 2], m6
movu [r5 + r1 * 2 + 16], m6
palignr m1, m0, 7
pshufb m1, m7
movhlps m2, m0
pshufb m2, m7
palignr m3, m0, 9
pshufb m3, m7
palignr m4, m0, 10
pshufb m4, m7
palignr m5, m0, 11
pshufb m5, m7
palignr m6, m0, 12
pshufb m6, m7
movu [r5 + r4], m1
movu [r5 + r4 + 16], m1
lea r5, [r5 + r1 * 4]
movu [r5], m2
movu [r5 + 16], m2
movu [r5 + r1], m3
movu [r5 + r1 + 16], m3
movu [r5 + r1 * 2], m4
movu [r5 + r1 * 2 + 16], m4
movu [r5 + r4], m5
movu [r5 + r4 + 16], m5
lea r5, [r5 + r1 * 4]
movu [r5], m6
movu [r5 + 16], m6
palignr m1, m0, 13
pshufb m1, m7
palignr m2, m0, 14
pshufb m2, m7
palignr m3, m0, 15
pshufb m3, m7
pshufb m0, m7
movu [r5 + r1], m1
movu [r5 + r1 + 16], m1
movu [r5 + r1 * 2], m2
movu [r5 + r1 * 2 + 16], m2
movu [r5 + r4], m3
movu [r5 + r4 + 16], m3
; filter
cmp r3d, byte 0
jz .quit
movhlps m1, m0
pmovzxbw m0, m0
mova m1, m0
movu m2, m8
movu m3, m9
pshufb m2, m7
pmovzxbw m2, m2
movhlps m4, m3
pmovzxbw m3, m3
pmovzxbw m4, m4
psubw m3, m2
psubw m4, m2
psraw m3, 1
psraw m4, 1
paddw m0, m3
paddw m1, m4
packuswb m0, m1
.quit:
movu [r0], m0
movu [r0 + 16], m0
dec r6
lea r0, [r5 + r1 * 4]
lea r2, [r2 + 16]
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang32_11, 4,7,8
; NOTE: alignment stack to 64 bytes, so all of local data in same cache line
mov r6, rsp
sub rsp, 64+gprsize
and rsp, ~63
mov [rsp+64], r6
; collect reference pixel
movu m0, [r2 + 16]
pxor m1, m1
pshufb m0, m1 ; [0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0]
mova [rsp], m0
movu m0, [r2 + 64]
pinsrb m0, [r2], 0
movu m1, [r2 + 16 + 64]
movu m2, [r2 + 32 + 64]
movu [rsp + 1], m0
movu [rsp + 1 + 16], m1
movu [rsp + 1 + 32], m2
mov [rsp + 63], byte 4
; filter
lea r2, [rsp + 1] ; r2 -> [0]
lea r3, [c_shuf8_0] ; r3 -> shuffle8
lea r4, [ang_table] ; r4 -> ang_table
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0 + r1 * 4] ; r6 -> 4 * stride
mova m5, [pw_1024] ; m5 -> 1024
mova m6, [c_deinterval8] ; m6 -> c_deinterval8
.loop:
; Row[0 - 7]
movu m7, [r2]
mova m0, m7
mova m1, m7
mova m2, m7
mova m3, m7
mova m4, m7
mova m5, m7
mova m6, m7
PROC32_8x8 0, 1, 30,28,26,24,22,20,18,16
; Row[8 - 15]
movu m7, [r2]
mova m0, m7
mova m1, m7
mova m2, m7
mova m3, m7
mova m4, m7
mova m5, m7
mova m6, m7
PROC32_8x8 1, 1, 14,12,10,8,6,4,2,0
; Row[16 - 23]
movu m7, [r2 - 1]
mova m0, m7
mova m1, m7
mova m2, m7
mova m3, m7
mova m4, m7
mova m5, m7
mova m6, m7
PROC32_8x8 2, 1, 30,28,26,24,22,20,18,16
; Row[24 - 31]
movu m7, [r2 - 1]
mova m0, m7
mova m1, m7
mova m2, m7
mova m3, m7
mova m4, m7
mova m5, m7
mova m6, m7
PROC32_8x8 3, 1, 14,12,10,8,6,4,2,0
lea r0, [r6 + r1 * 4]
lea r6, [r6 + r1 * 8]
add r2, 8
dec byte [rsp + 63]
jnz .loop
mov rsp, [rsp+64]
RET
%macro MODE_12_24_ROW0 1
movu m0, [r3 + 6]
pshufb m0, [c_mode32_12_0]
pinsrb m0, [r3 + 26], 12
mova above, m0
movu m2, [r2]
%if %1 == 1
pinsrb m2, [r3], 0
%endif
palignr m1, m2, 1
punpcklbw m2, m1
pmaddubsw m4, m2, [r4 + 11 * 16] ; [27]
pmulhrsw m4, m7
pmaddubsw m3, m2, [r4 + 6 * 16] ; [22]
pmulhrsw m3, m7
packuswb m4, m3
pmaddubsw m5, m2, [r4 + 16] ; [17]
pmulhrsw m5, m7
pmaddubsw m6, m2, [r4 - 4 * 16] ; [12]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m2, [r4 - 9 * 16] ; [7]
pmulhrsw m6, m7
pmaddubsw m3, m2, [r4 - 14 * 16] ; [2]
pmulhrsw m3, m7
packuswb m6, m3
movu m1, [r2] ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0]
%if %1 == 1
pinsrb m1, [r3], 0
%endif
palignr m2, m1, above, 15 ; [14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a]
punpcklbw m2, m1 ; [7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 a]
pmaddubsw m1, m2, [r4 + 13 * 16] ; [29]
pmulhrsw m1, m7
pmaddubsw m3, m2, [r4 + 8 * 16] ; [24]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 0, %1, m4, m5, m6, m1
pmaddubsw m4, m2, [r4 + 3 * 16] ; [19]
pmulhrsw m4, m7
pmaddubsw m5, m2, [r4 - 2 * 16] ; [14]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m2, [r4 - 7 * 16] ; [09]
pmulhrsw m5, m7
pmaddubsw m6, m2, [r4 - 12 * 16] ; [04]
pmulhrsw m6, m7
packuswb m5, m6
palignr m2, above, 14 ;[6 5 5 4 4 3 3 2 2 1 1 0 0 a a b]
pmaddubsw m6, m2, [r4 + 15 * 16] ; [31]
pmulhrsw m6, m7
pmaddubsw m1, m2, [r4 + 10 * 16] ; [26]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m1, m2, [r4 + 5 * 16] ; [21]
pmulhrsw m1, m7
pmaddubsw m3, m2, [r4] ; [16]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 1, %1, m4, m5, m6, m1
pmaddubsw m4, m2, [r4 - 5 * 16] ; [11]
pmulhrsw m4, m7
pmaddubsw m3, m2, [r4 - 10 * 16] ; [06]
pmulhrsw m3, m7
packuswb m4, m3
pmaddubsw m5, m2, [r4 - 15 * 16] ; [1]
pmulhrsw m5, m7
pslldq m1, above, 1
palignr m2, m1, 14
pmaddubsw m6, m2, [r4 + 12 * 16] ; [28]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m2, [r4 + 7 * 16] ; [23]
pmulhrsw m6, m7
pmaddubsw m3, m2, [r4 + 2 * 16] ; [18]
pmulhrsw m3, m7
packuswb m6, m3
pmaddubsw m1, m2, [r4 - 3 * 16] ; [13]
pmulhrsw m1, m7
pmaddubsw m3, m2, [r4 - 8 * 16] ; [8]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 2, %1, m4, m5, m6, m1
pmaddubsw m4, m2, [r4 - 13 * 16] ; [3]
pmulhrsw m4, m7
pslldq m1, above, 2
palignr m2, m1, 14
pmaddubsw m5, m2, [r4 + 14 * 16] ; [30]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m2, [r4 + 9 * 16] ; [25]
pmulhrsw m5, m7
pmaddubsw m6, m2, [r4 + 4 * 16] ; [20]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m2, [r4 - 16] ; [15]
pmulhrsw m6, m7
pmaddubsw m1, m2, [r4 - 6 * 16] ; [10]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m1, m2, [r4 - 11 * 16] ; [05]
pmulhrsw m1, m7
movu m0, [pb_fact0]
pshufb m2, m0
pmovzxbw m2, m2
packuswb m1, m2
TRANSPOSE_STORE_8x8 3, %1, m4, m5, m6, m1
%endmacro
INIT_XMM sse4
cglobal intra_pred_ang32_12, 3,7,8,0-(1*mmsize)
%define above [rsp + 0 * mmsize]
mov r3, r2
add r2, 64
lea r4, [ang_table + 16 * 16]
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0 + r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
MODE_12_24_ROW0 1
lea r0, [r6 + r1 * 4]
lea r6, [r6 + r1 * 8]
add r2, 7
mov r3, 3
.loop:
MODE_12_24 1
lea r0, [r6 + r1 * 4]
lea r6, [r6 + r1 * 8]
add r2, 8
dec r3
jnz .loop
RET
%macro MODE_13_23_ROW0 1
movu m0, [r3 + 1]
movu m1, [r3 + 15]
pshufb m0, [c_mode32_13_0]
pshufb m1, [c_mode32_13_0]
punpckldq m0, m1
pshufb m0, [c_mode32_13_shuf]
mova above, m0
movu m2, [r2]
%if (%1 == 1)
pinsrb m2, [r3], 0
%endif
palignr m1, m2, 1
punpcklbw m2, m1
pmaddubsw m4, m2, [r4 + 7 * 16] ; [23]
pmulhrsw m4, m7
pmaddubsw m3, m2, [r4 - 2 * 16] ; [14]
pmulhrsw m3, m7
packuswb m4, m3
pmaddubsw m5, m2, [r4 - 11 * 16] ; [5]
pmulhrsw m5, m7
movu m1, [r2] ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0]
%if (%1 == 1)
pinsrb m1, [r3], 0
%endif
palignr m2, m1, above, 15 ; [14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a]
punpcklbw m2, m1 ; [7 6 6 5 5 4 4 3 3 2 2 1 1 0 0]
pmaddubsw m6, m2, [r4 + 12 * 16] ; [28]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m2, [r4 + 3 * 16] ; [19]
pmulhrsw m6, m7
pmaddubsw m0, m2, [r4 - 6 * 16] ; [10]
pmulhrsw m0, m7
packuswb m6, m0
pmaddubsw m1, m2, [r4 - 15 * 16] ; [1]
pmulhrsw m1, m7
palignr m2, above, 14
pmaddubsw m3, m2, [r4 + 8 * 16] ; [24]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 0, %1, m4, m5, m6, m1
pmaddubsw m4, m2, [r4 - 16] ; [15]
pmulhrsw m4, m7
pmaddubsw m5, m2, [r4 - 10 * 16] ; [6]
pmulhrsw m5, m7
packuswb m4, m5
pslldq m0, above, 1
palignr m2, m0, 14
pmaddubsw m5, m2, [r4 + 13 * 16] ; [29]
pmulhrsw m5, m7
pmaddubsw m6, m2, [r4 + 4 * 16] ; [20]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m2, [r4 - 5 * 16] ; [11]
pmulhrsw m6, m7
pmaddubsw m1, m2, [r4 - 14 * 16] ; [2]
pmulhrsw m1, m7
packuswb m6, m1
pslldq m0, 1
palignr m2, m0, 14
pmaddubsw m1, m2, [r4 + 9 * 16] ; [25]
pmulhrsw m1, m7
pmaddubsw m0, m2, [r4] ; [16]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 1, %1, m4, m5, m6, m1
pmaddubsw m4, m2, [r4 - 9 * 16] ; [7]
pmulhrsw m4, m7
pslldq m0, above, 3
palignr m2, m0, 14
pmaddubsw m3, m2, [r4 + 14 * 16] ; [30]
pmulhrsw m3, m7
packuswb m4, m3
pmaddubsw m5, m2, [r4 + 5 * 16] ; [21]
pmulhrsw m5, m7
pmaddubsw m6, m2, [r4 - 4 * 16] ; [12]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m2, [r4 - 13 * 16] ; [3]
pmulhrsw m6, m7
pslldq m0, 1
palignr m2, m0, 14
pmaddubsw m0, m2, [r4 + 10 * 16] ; [26]
pmulhrsw m0, m7
packuswb m6, m0
pmaddubsw m1, m2, [r4 + 16] ; [17]
pmulhrsw m1, m7
pmaddubsw m0, m2, [r4 - 8 * 16] ; [8]
pmulhrsw m0, m7
packuswb m1, m0
TRANSPOSE_STORE_8x8 2, %1, m4, m5, m6, m1
pslldq m0, above, 5
palignr m2, m0, 14
pmaddubsw m4, m2, [r4 + 15 * 16] ; [31]
pmulhrsw m4, m7
pmaddubsw m5, m2, [r4 + 6 * 16] ; [22]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m2, [r4 - 3 * 16] ; [13]
pmulhrsw m5, m7
pmaddubsw m6, m2, [r4 - 12 * 16] ; [04]
pmulhrsw m6, m7
packuswb m5, m6
pslldq m0, 1
palignr m2, m0, 14
pmaddubsw m6, m2, [r4 + 11 * 16] ; [27]
pmulhrsw m6, m7
pmaddubsw m1, m2, [r4 + 2 * 16] ; [18]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m1, m2, [r4 - 7 * 16] ; [09]
pmulhrsw m1, m7
pmaddubsw m3, m2, [r4 - 16 * 16] ; [00]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 3, %1, m4, m5, m6, m1
%endmacro
%macro MODE_13_23 2
movu m2, [r2] ; [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
palignr m1, m2, 1 ; [x ,15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1]
punpckhbw m0, m2, m1 ; [x, 15, 15, 14, 14, 13, 13, 12, 12, 11, 11, 10, 10, 9, 9, 8]
punpcklbw m2, m1 ; [8, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1, 1, 0]
palignr m0, m2, 2 ; [9, 8, 8, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1]
pmaddubsw m4, m0, [r4 + 7 * 16] ; [23]
pmulhrsw m4, m7
pmaddubsw m3, m0, [r4 - 2 * 16] ; [14]
pmulhrsw m3, m7
packuswb m4, m3
pmaddubsw m5, m0, [r4 - 11 * 16] ; [05]
pmulhrsw m5, m7
pmaddubsw m6, m2, [r4 + 12 * 16] ; [28]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m2, [r4 + 3 * 16] ; [19]
pmulhrsw m6, m7
pmaddubsw m3, m2, [r4 - 6 * 16] ; [10]
pmulhrsw m3, m7
packuswb m6, m3
pmaddubsw m1, m2, [r4 - 15 * 16] ; [1]
pmulhrsw m1, m7
movu m2, [r2 - 2] ; [14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, -1]
palignr m3, m2, 1 ; [x, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
punpckhbw m0, m2, m3
punpcklbw m2, m3
palignr m0, m2, 2
pmaddubsw m3, m0, [r4 + 8 * 16] ; [24]
pmulhrsw m3, m7
packuswb m1, m3
mova m3, m0
TRANSPOSE_STORE_8x8 0, %1, m4, m5, m6, m1
pmaddubsw m4, m3, [r4 - 16] ; [15]
pmulhrsw m4, m7
pmaddubsw m5, m3, [r4 - 10 * 16] ; [6]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m2, [r4 + 13 * 16] ; [29]
pmulhrsw m5, m7
pmaddubsw m6, m2, [r4 + 4 * 16] ; [20]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m2, [r4 - 5 * 16] ; [11]
pmulhrsw m6, m7
pmaddubsw m1, m2, [r4 - 14 * 16] ; [2]
pmulhrsw m1, m7
packuswb m6, m1
movu m2, [r2 - 4] ; [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
palignr m1, m2, 1 ; [x ,15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1]
punpckhbw m0, m2, m1 ; [x, 15, 15, 14, 14, 13, 13, 12, 12, 11, 11, 10, 10, 9, 9, 8]
punpcklbw m2, m1 ; [8, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1, 1, 0]
palignr m0, m2, 2 ; [9, 8, 8, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1]
pmaddubsw m1, m0, [r4 + 9 * 16] ; [25]
pmulhrsw m1, m7
pmaddubsw m3, m0, [r4] ; [16]
pmulhrsw m3, m7
packuswb m1, m3
mova m3, m0
TRANSPOSE_STORE_8x8 1, %1, m4, m5, m6, m1
pmaddubsw m4, m3, [r4 - 9 * 16] ; [7]
pmulhrsw m4, m7
pmaddubsw m3, m2, [r4 + 14 * 16] ; [30]
pmulhrsw m3, m7
packuswb m4, m3
pmaddubsw m5, m2, [r4 + 5 * 16] ; [21]
pmulhrsw m5, m7
pmaddubsw m6, m2, [r4 - 4 * 16] ; [12]
pmulhrsw m6, m7
packuswb m5, m6
pmaddubsw m6, m2, [r4 - 13 * 16] ; [3]
pmulhrsw m6, m7
movu m2, [r2 - 6] ; [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
palignr m1, m2, 1 ; [x ,15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1]
punpckhbw m0, m2, m1 ; [x, 15, 15, 14, 14, 13, 13, 12, 12, 11, 11, 10, 10, 9, 9, 8]
punpcklbw m2, m1 ; [8, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1, 1, 0]
palignr m0, m2, 2 ; [9, 8, 8, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1]
pmaddubsw m3, m0, [r4 + 10 * 16] ; [26]
pmulhrsw m3, m7
packuswb m6, m3
pmaddubsw m1, m0, [r4 + 16] ; [17]
pmulhrsw m1, m7
pmaddubsw m3, m0, [r4 - 8 * 16] ; [8]
pmulhrsw m3, m7
packuswb m1, m3
TRANSPOSE_STORE_8x8 2, %1, m4, m5, m6, m1
pmaddubsw m4, m2, [r4 + 15 * 16] ; [31]
pmulhrsw m4, m7
pmaddubsw m5, m2, [r4 + 6 * 16] ; [22]
pmulhrsw m5, m7
packuswb m4, m5
pmaddubsw m5, m2, [r4 - 3 * 16] ; [13]
pmulhrsw m5, m7
pmaddubsw m6, m2, [r4 - 12 * 16] ; [04]
pmulhrsw m6, m7
packuswb m5, m6
movu m2, [r2 - 7] ; [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
%if ((%1 & %2) == 1)
pinsrb m2, [r3], 0
%endif
palignr m1, m2, 1 ; [x ,15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1]
punpcklbw m2, m1 ; [8, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1, 1, 0]
pmaddubsw m6, m2, [r4 + 11 * 16] ; [27]
pmulhrsw m6, m7
pmaddubsw m1, m2, [r4 + 2 * 16] ; [18]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m1, m2, [r4 - 7 * 16] ; [09]
pmulhrsw m1, m7
movu m0, [pb_fact0]
pshufb m2, m0
pmovzxbw m2, m2
packuswb m1, m2
TRANSPOSE_STORE_8x8 3, %1, m4, m5, m6, m1
%endmacro
INIT_XMM sse4
cglobal intra_pred_ang32_13, 3,7,8,0-(1*mmsize)
%define above [rsp + 0 * mmsize]
mov r3, r2
add r2, 64
lea r4, [ang_table + 16 * 16]
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0 + r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
MODE_13_23_ROW0 1
lea r0, [r6 + r1 * 4]
lea r6, [r6 + r1 * 8]
add r2, 7
MODE_13_23 1, 1
lea r0, [r6 + r1 * 4]
lea r6, [r6 + r1 * 8]
add r2, 8
mov r3, 2
.loop:
MODE_13_23 1, 0
lea r0, [r6 + r1 * 4]
lea r6, [r6 + r1 * 8]
add r2, 8
dec r3
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang32_14, 3,7,8
; NOTE: alignment stack to 64 bytes, so all of local data in same cache line
mov r6, rsp
sub rsp, 64+gprsize
and rsp, ~63
mov [rsp+64], r6
; collect reference pixel
movu m0, [r2]
movu m1, [r2 + 15]
pshufb m0, [c_mode32_14_0] ; [x x x x x x x x x 0 2 5 7 10 12 15]
pshufb m1, [c_mode32_14_0] ; [x x x x x x x x x 15 17 20 22 25 27 30]
pslldq m1, 10 ; [17 20 22 25 27 30 x x x x x x x x x x x]
palignr m0, m1, 10 ; [x x x 0 2 5 7 10 12 15 17 20 22 25 27 30]
mova [rsp], m0
movu m0, [r2 + 1 + 64]
movu m1, [r2 + 1 + 16 + 64]
movu [rsp + 13], m0
movu [rsp + 13 + 16], m1
mov [rsp + 63], byte 4
; filter
lea r2, [rsp + 13] ; r2 -> [0]
lea r3, [c_shuf8_0] ; r3 -> shuffle8
lea r4, [ang_table] ; r4 -> ang_table
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0 + r1 * 4] ; r6 -> 4 * stride
mova m5, [pw_1024] ; m5 -> 1024
mova m6, [c_deinterval8] ; m6 -> c_deinterval8
.loop:
; Row[0 - 7]
movu m7, [r2 - 4]
palignr m0, m7, 3
mova m1, m0
palignr m2, m7, 2
mova m3, m2
palignr m4, m7, 1
mova m5, m4
mova m6, m4
PROC32_8x8 0, 1, 19,6,25,12,31,18,5,24
; Row[8 - 15]
movu m7, [r2 - 7]
palignr m0, m7, 3
palignr m1, m7, 2
mova m2, m1
mova m3, m1
palignr m4, m7, 1
mova m5, m4
mova m6, m7
PROC32_8x8 1, 1, 11,30,17,4,23,10,29,16
; Row[16 - 23]
movu m7, [r2 - 10]
palignr m0, m7, 3
palignr m1, m7, 2
mova m2, m1
palignr m3, m7, 1
mova m4, m3
mova m5, m3
mova m6, m7
PROC32_8x8 2, 1, 3,22,9,28,15,2,21,8
; Row[24 - 31]
movu m7, [r2 - 13]
palignr m0, m7, 2
mova m1, m0
mova m2, m0
palignr m3, m7, 1
mova m4, m3
mova m5, m7
mova m6, m7
PROC32_8x8 3, 1, 27,14,1,20,7,26,13,0
lea r0, [r6 + r1 * 4]
lea r6, [r6 + r1 * 8]
add r2, 8
dec byte [rsp + 63]
jnz .loop
mov rsp, [rsp+64]
RET
INIT_XMM sse4
cglobal intra_pred_ang32_15, 4,7,8
; NOTE: alignment stack to 64 bytes, so all of local data in same cache line
mov r6, rsp
sub rsp, 64+gprsize
and rsp, ~63
mov [rsp+64], r6
; collect reference pixel
movu m0, [r2]
movu m1, [r2 + 15]
pshufb m0, [c_mode32_15_0] ; [x x x x x x x 0 2 4 6 8 9 11 13 15]
pshufb m1, [c_mode32_15_0] ; [x x x x x x x 15 17 19 21 23 24 26 28 30]
mova [rsp], m1
movu [rsp + 8], m0
movu m0, [r2 + 1 + 64]
movu m1, [r2 + 1 + 16 + 64]
movu [rsp + 17], m0
movu [rsp + 17 + 16], m1
mov [rsp + 63], byte 4
; filter
lea r2, [rsp + 17] ; r2 -> [0]
lea r3, [c_shuf8_0] ; r3 -> shuffle8
lea r4, [ang_table] ; r4 -> ang_table
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0 + r1 * 4] ; r6 -> 4 * stride
mova m5, [pw_1024] ; m5 -> 1024
mova m6, [c_deinterval8] ; m6 -> c_deinterval8
.loop:
; Row[0 - 7]
movu m7, [r2 - 5]
palignr m0, m7, 4
palignr m1, m7, 3
mova m2, m1
palignr m3, m7, 2
mova m4, m3
palignr m5, m7, 1
mova m6, m5
PROC32_8x8 0, 1, 15,30,13,28,11,26,9,24
; Row[8 - 15]
movu m7, [r2 - 9]
palignr m0, m7, 4
palignr m1, m7, 3
mova m2, m1
palignr m3, m7, 2
mova m4, m3
palignr m5, m7, 1
mova m6, m5
PROC32_8x8 1, 1, 7,22,5,20,3,18,1,16
; Row[16 - 23]
movu m7, [r2 - 13]
palignr m0, m7, 3
mova m1, m0
palignr m2, m7, 2
mova m3, m2
palignr m4, m7, 1
mova m5, m4
mova m6, m7
PROC32_8x8 2, 1, 31,14,29,12,27,10,25,8
; Row[24 - 31]
movu m7, [r2 - 17]
palignr m0, m7, 3
mova m1, m0
palignr m2, m7, 2
mova m3, m2
palignr m4, m7, 1
mova m5, m4
mova m6, m7
PROC32_8x8 3, 1, 23,6,21,4,19,2,17,0
lea r0, [r6 + r1 * 4]
lea r6, [r6 + r1 * 8]
add r2, 8
dec byte [rsp + 63]
jnz .loop
mov rsp, [rsp+64]
RET
INIT_XMM sse4
cglobal intra_pred_ang32_16, 4,7,8
; NOTE: alignment stack to 64 bytes, so all of local data in same cache line
mov r6, rsp
sub rsp, 64+gprsize
and rsp, ~63
mov [rsp+64], r6
; collect reference pixel
movu m0, [r2]
movu m1, [r2 + 15]
pshufb m0, [c_mode32_16_0] ; [x x x x x 0 2 3 5 6 8 9 11 12 14 15]
pshufb m1, [c_mode32_16_0] ; [x x x x x 15 17 18 20 21 23 24 26 27 29 30]
mova [rsp], m1
movu [rsp + 10], m0
movu m0, [r2 + 1 + 64]
movu m1, [r2 + 1 + 16 + 64]
movu [rsp + 21], m0
movu [rsp + 21 + 16], m1
mov [rsp + 63], byte 4
; filter
lea r2, [rsp + 21] ; r2 -> [0]
lea r3, [c_shuf8_0] ; r3 -> shuffle8
lea r4, [ang_table] ; r4 -> ang_table
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0 + r1 * 4] ; r6 -> 4 * stride
mova m5, [pw_1024] ; m5 -> 1024
mova m6, [c_deinterval8] ; m6 -> c_deinterval8
.loop:
; Row[0 - 7]
movu m7, [r2 - 6]
palignr m0, m7, 5
palignr m1, m7, 4
mova m2, m1
palignr m3, m7, 3
palignr m4, m7, 2
mova m5, m4
palignr m6, m7, 1
PROC32_8x8 0, 1, 11,22,1,12,23,2,13,24
; Row[8 - 15]
movu m7, [r2 - 11]
palignr m0, m7, 5
palignr m1, m7, 4
palignr m2, m7, 3
mova m3, m2
palignr m4, m7, 2
palignr m5, m7, 1
mova m6, m5
PROC32_8x8 1, 1, 3,14,25,4,15,26,5,16
; Row[16 - 23]
movu m7, [r2 - 16]
palignr m0, m7, 4
mova m1, m0
palignr m2, m7, 3
palignr m3, m7, 2
mova m4, m3
palignr m5, m7, 1
mova m6, m7
PROC32_8x8 2, 1, 27,6,17,28,7,18,29,8
; Row[24 - 31]
movu m7, [r2 - 21]
palignr m0, m7, 4
palignr m1, m7, 3
mova m2, m1
palignr m3, m7, 2
palignr m4, m7, 1
mova m5, m4
mova m6, m7
PROC32_8x8 3, 1, 19,30,9,20,31,10,21,0
lea r0, [r6 + r1 * 4]
lea r6, [r6 + r1 * 8]
add r2, 8
dec byte [rsp + 63]
jnz .loop
mov rsp, [rsp+64]
RET
INIT_XMM sse4
cglobal intra_pred_ang32_17, 4,7,8
; NOTE: alignment stack to 64 bytes, so all of local data in same cache line
mov r6, rsp
sub rsp, 64+gprsize
and rsp, ~63
mov [rsp+64], r6
; collect reference pixel
movu m0, [r2]
movu m1, [r2 + 16]
pshufb m0, [c_mode32_17_0]
pshufb m1, [c_mode32_17_0]
mova [rsp ], m1
movu [rsp + 13], m0
movu m0, [r2 + 1 + 64]
movu m1, [r2 + 1 + 16 + 64]
movu [rsp + 26], m0
movu [rsp + 26 + 16], m1
mov [rsp + 63], byte 4
; filter
lea r2, [rsp + 25] ; r2 -> [0]
lea r3, [c_shuf8_0] ; r3 -> shuffle8
lea r4, [ang_table] ; r4 -> ang_table
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0 + r1 * 4] ; r6 -> 4 * stride
mova m5, [pw_1024] ; m5 -> 1024
mova m6, [c_deinterval8] ; m6 -> c_deinterval8
.loop:
; Row[0 - 7]
movu m7, [r2 - 6]
palignr m0, m7, 6
palignr m1, m7, 5
palignr m2, m7, 4
palignr m3, m7, 3
palignr m4, m7, 2
mova m5, m4
palignr m6, m7, 1
PROC32_8x8 0, 1, 6,12,18,24,30,4,10,16
; Row[7 - 15]
movu m7, [r2 - 12]
palignr m0, m7, 5
palignr m1, m7, 4
mova m2, m1
palignr m3, m7, 3
palignr m4, m7, 2
palignr m5, m7, 1
mova m6, m7
PROC32_8x8 1, 1, 22,28,2,8,14,20,26,0
; Row[16 - 23]
movu m7, [r2 - 19]
palignr m0, m7, 6
palignr m1, m7, 5
palignr m2, m7, 4
palignr m3, m7, 3
palignr m4, m7, 2
mova m5, m4
palignr m6, m7, 1
PROC32_8x8 2, 1, 6,12,18,24,30,4,10,16
; Row[24 - 31]
movu m7, [r2 - 25]
palignr m0, m7, 5
palignr m1, m7, 4
mova m2, m1
palignr m3, m7, 3
palignr m4, m7, 2
palignr m5, m7, 1
mova m6, m7
PROC32_8x8 3, 1, 22,28,2,8,14,20,26,0
lea r0, [r6 + r1 * 4]
lea r6, [r6 + r1 * 8]
add r2, 8
dec byte [rsp + 63]
jnz .loop
mov rsp, [rsp+64]
RET
INIT_YMM avx2
cglobal intra_pred_ang32_18, 4, 4, 3
movu m0, [r2]
movu xm1, [r2 + 1 + 64]
pshufb xm1, [intra_pred_shuff_15_0]
mova xm2, xm0
vinserti128 m1, m1, xm2, 1
lea r3, [r1 * 3]
movu [r0], m0
palignr m2, m0, m1, 15
movu [r0 + r1], m2
palignr m2, m0, m1, 14
movu [r0 + r1 * 2], m2
palignr m2, m0, m1, 13
movu [r0 + r3], m2
lea r0, [r0 + r1 * 4]
palignr m2, m0, m1, 12
movu [r0], m2
palignr m2, m0, m1, 11
movu [r0 + r1], m2
palignr m2, m0, m1, 10
movu [r0 + r1 * 2], m2
palignr m2, m0, m1, 9
movu [r0 + r3], m2
lea r0, [r0 + r1 * 4]
palignr m2, m0, m1, 8
movu [r0], m2
palignr m2, m0, m1, 7
movu [r0 + r1], m2
palignr m2, m0, m1, 6
movu [r0 + r1 * 2], m2
palignr m2, m0, m1, 5
movu [r0 + r3], m2
lea r0, [r0 + r1 * 4]
palignr m2, m0, m1, 4
movu [r0], m2
palignr m2, m0, m1, 3
movu [r0 + r1], m2
palignr m2, m0, m1, 2
movu [r0 + r1 * 2], m2
palignr m2, m0, m1, 1
movu [r0 + r3], m2
lea r0, [r0 + r1 * 4]
movu [r0], m1
movu xm0, [r2 + 64 + 17]
pshufb xm0, [intra_pred_shuff_15_0]
vinserti128 m0, m0, xm1, 1
palignr m2, m1, m0, 15
movu [r0 + r1], m2
palignr m2, m1, m0, 14
movu [r0 + r1 * 2], m2
palignr m2, m1, m0, 13
movu [r0 + r3], m2
lea r0, [r0 + r1 * 4]
palignr m2, m1, m0, 12
movu [r0], m2
palignr m2, m1, m0, 11
movu [r0 + r1], m2
palignr m2, m1, m0, 10
movu [r0 + r1 * 2], m2
palignr m2, m1, m0, 9
movu [r0 + r3], m2
lea r0, [r0 + r1 * 4]
palignr m2, m1, m0, 8
movu [r0], m2
palignr m2, m1, m0, 7
movu [r0 + r1], m2
palignr m2, m1, m0,6
movu [r0 + r1 * 2], m2
palignr m2, m1, m0, 5
movu [r0 + r3], m2
lea r0, [r0 + r1 * 4]
palignr m2, m1, m0, 4
movu [r0], m2
palignr m2, m1, m0, 3
movu [r0 + r1], m2
palignr m2, m1, m0,2
movu [r0 + r1 * 2], m2
palignr m2, m1, m0, 1
movu [r0 + r3], m2
RET
INIT_XMM sse4
cglobal intra_pred_ang32_18, 4,5,5
movu m0, [r2] ; [15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0]
movu m1, [r2 + 16] ; [31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16]
movu m2, [r2 + 1 + 64] ; [16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
movu m3, [r2 + 17 + 64] ; [32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17]
lea r2, [r1 * 2]
lea r3, [r1 * 3]
lea r4, [r1 * 4]
movu [r0], m0
movu [r0 + 16], m1
pshufb m2, [c_mode32_18_0] ; [1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16]
pshufb m3, [c_mode32_18_0] ; [17 18 19 20 21 22 23 24 25 26 27 28 19 30 31 32]
palignr m4, m0, m2, 15
movu [r0 + r1], m4
palignr m4, m1, m0, 15
movu [r0 + r1 + 16], m4
palignr m4, m0, m2, 14
movu [r0 + r2], m4
palignr m4, m1, m0, 14
movu [r0 + r2 + 16], m4
palignr m4, m0, m2, 13
movu [r0 + r3], m4
palignr m4, m1, m0, 13
movu [r0 + r3 + 16], m4
lea r0, [r0 + r4]
palignr m4, m0, m2, 12
movu [r0], m4
palignr m4, m1, m0, 12
movu [r0 + 16], m4
palignr m4, m0, m2, 11
movu [r0 + r1], m4
palignr m4, m1, m0, 11
movu [r0 + r1 + 16], m4
palignr m4, m0, m2, 10
movu [r0 + r2], m4
palignr m4, m1, m0, 10
movu [r0 + r2 + 16], m4
palignr m4, m0, m2, 9
movu [r0 + r3], m4
palignr m4, m1, m0, 9
movu [r0 + r3 + 16], m4
lea r0, [r0 + r4]
palignr m4, m0, m2, 8
movu [r0], m4
palignr m4, m1, m0, 8
movu [r0 + 16], m4
palignr m4, m0, m2, 7
movu [r0 + r1], m4
palignr m4, m1, m0, 7
movu [r0 + r1 + 16], m4
palignr m4, m0, m2, 6
movu [r0 + r2], m4
palignr m4, m1, m0, 6
movu [r0 + r2 + 16], m4
palignr m4, m0, m2, 5
movu [r0 + r3], m4
palignr m4, m1, m0, 5
movu [r0 + r3 + 16], m4
lea r0, [r0 + r4]
palignr m4, m0, m2, 4
movu [r0], m4
palignr m4, m1, m0, 4
movu [r0 + 16], m4
palignr m4, m0, m2, 3
movu [r0 + r1], m4
palignr m4, m1, m0, 3
movu [r0 + r1 + 16], m4
palignr m4, m0, m2, 2
movu [r0 + r2], m4
palignr m4, m1, m0, 2
movu [r0 + r2 + 16], m4
palignr m4, m0, m2, 1
movu [r0 + r3], m4
palignr m4, m1, m0, 1
movu [r0 + r3 + 16], m4
lea r0, [r0 + r4]
movu [r0], m2
movu [r0 + 16], m0
palignr m4, m2, m3, 15
movu [r0 + r1], m4
palignr m4, m0, m2, 15
movu [r0 + r1 + 16], m4
palignr m4, m2, m3, 14
movu [r0 + r2], m4
palignr m4, m0, m2, 14
movu [r0 + r2 + 16], m4
palignr m4, m2, m3, 13
movu [r0 + r3], m4
palignr m4, m0, m2, 13
movu [r0 + r3 + 16], m4
lea r0, [r0 + r4]
palignr m4, m2, m3, 12
movu [r0], m4
palignr m4, m0, m2, 12
movu [r0 + 16], m4
palignr m4, m2, m3, 11
movu [r0 + r1], m4
palignr m4, m0, m2, 11
movu [r0 + r1 + 16], m4
palignr m4, m2, m3, 10
movu [r0 + r2], m4
palignr m4, m0, m2, 10
movu [r0 + r2 + 16], m4
palignr m4, m2, m3, 9
movu [r0 + r3], m4
palignr m4, m0, m2, 9
movu [r0 + r3 + 16], m4
lea r0, [r0 + r4]
palignr m4, m2, m3, 8
movu [r0], m4
palignr m4, m0, m2, 8
movu [r0 + 16], m4
palignr m4, m2, m3, 7
movu [r0 + r1], m4
palignr m4, m0, m2, 7
movu [r0 + r1 + 16], m4
palignr m4, m2, m3, 6
movu [r0 + r2], m4
palignr m4, m0, m2, 6
movu [r0 + r2 + 16], m4
palignr m4, m2, m3, 5
movu [r0 + r3], m4
palignr m4, m0, m2, 5
movu [r0 + r3 + 16], m4
lea r0, [r0 + r4]
palignr m4, m2, m3, 4
movu [r0], m4
palignr m4, m0, m2, 4
movu [r0 + 16], m4
palignr m4, m2, m3, 3
movu [r0 + r1], m4
palignr m4, m0, m2, 3
movu [r0 + r1 + 16], m4
palignr m4, m2, m3, 2
movu [r0 + r2], m4
palignr m4, m0, m2, 2
movu [r0 + r2 + 16], m4
palignr m4, m2, m3, 1
movu [r0 + r3], m4
palignr m4, m0, m2, 1
movu [r0 + r3 + 16], m4
RET
INIT_XMM sse4
cglobal intra_pred_ang32_19, 4,7,8
; NOTE: alignment stack to 64 bytes, so all of local data in same cache line
mov r6, rsp
sub rsp, 64+gprsize
and rsp, ~63
mov [rsp+64], r6
; collect reference pixel
movu m0, [r2 + 64]
pinsrb m0, [r2], 0
movu m1, [r2 + 16 + 64]
pshufb m0, [c_mode32_17_0]
pshufb m1, [c_mode32_17_0]
mova [rsp ], m1
movu [rsp + 13], m0
movu m0, [r2 + 1]
movu m1, [r2 + 1 + 16]
movu [rsp + 26], m0
movu [rsp + 26 + 16], m1
mov [rsp + 63], byte 4
; filter
lea r2, [rsp + 25] ; r2 -> [0]
lea r3, [c_shuf8_0] ; r3 -> shuffle8
lea r4, [ang_table] ; r4 -> ang_table
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0] ; r6 -> r0
mova m5, [pw_1024] ; m5 -> 1024
mova m6, [c_deinterval8] ; m6 -> c_deinterval8
.loop:
; Row[0 - 7]
movu m7, [r2 - 6]
palignr m0, m7, 6
palignr m1, m7, 5
palignr m2, m7, 4
palignr m3, m7, 3
palignr m4, m7, 2
mova m5, m4
palignr m6, m7, 1
PROC32_8x8 0, 0, 6,12,18,24,30,4,10,16
; Row[7 - 15]
movu m7, [r2 - 12]
palignr m0, m7, 5
palignr m1, m7, 4
mova m2, m1
palignr m3, m7, 3
palignr m4, m7, 2
palignr m5, m7, 1
mova m6, m7
lea r0, [r0 + r1 * 4]
PROC32_8x8 1, 0, 22,28,2,8,14,20,26,0
; Row[16 - 23]
movu m7, [r2 - 19]
palignr m0, m7, 6
palignr m1, m7, 5
palignr m2, m7, 4
palignr m3, m7, 3
palignr m4, m7, 2
mova m5, m4
palignr m6, m7, 1
lea r0, [r0 + r1 * 4]
PROC32_8x8 2, 0, 6,12,18,24,30,4,10,16
; Row[24 - 31]
movu m7, [r2 - 25]
palignr m0, m7, 5
palignr m1, m7, 4
mova m2, m1
palignr m3, m7, 3
palignr m4, m7, 2
palignr m5, m7, 1
mova m6, m7
lea r0, [r0 + r1 * 4]
PROC32_8x8 3, 0, 22,28,2,8,14,20,26,0
add r6, 8
mov r0, r6
add r2, 8
dec byte [rsp + 63]
jnz .loop
mov rsp, [rsp+64]
RET
INIT_XMM sse4
cglobal intra_pred_ang32_20, 4,7,8
; NOTE: alignment stack to 64 bytes, so all of local data in same cache line
mov r6, rsp
sub rsp, 64+gprsize
and rsp, ~63
mov [rsp+64], r6
; collect reference pixel
movu m0, [r2 + 64]
pinsrb m0, [r2], 0
movu m1, [r2 + 15 + 64]
pshufb m0, [c_mode32_16_0] ; [x x x x x 0 2 3 5 6 8 9 11 12 14 15]
pshufb m1, [c_mode32_16_0] ; [x x x x x 15 17 18 20 21 23 24 26 27 29 30]
mova [rsp], m1
movu [rsp + 10], m0
movu m0, [r2 + 1]
movu m1, [r2 + 1 + 16]
movu [rsp + 21], m0
movu [rsp + 21 + 16], m1
mov [rsp + 63], byte 4
; filter
lea r2, [rsp + 21] ; r2 -> [0]
lea r3, [c_shuf8_0] ; r3 -> shuffle8
lea r4, [ang_table] ; r4 -> ang_table
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0] ; r6 -> r0
mova m5, [pw_1024] ; m5 -> 1024
mova m6, [c_deinterval8] ; m6 -> c_deinterval8
.loop:
; Row[0 - 7]
movu m7, [r2 - 6]
palignr m0, m7, 5
palignr m1, m7, 4
mova m2, m1
palignr m3, m7, 3
palignr m4, m7, 2
mova m5, m4
palignr m6, m7, 1
PROC32_8x8 0, 0, 11,22,1,12,23,2,13,24
; Row[8 - 15]
movu m7, [r2 - 11]
palignr m0, m7, 5
palignr m1, m7, 4
palignr m2, m7, 3
mova m3, m2
palignr m4, m7, 2
palignr m5, m7, 1
mova m6, m5
lea r0, [r0 + r1 * 4]
PROC32_8x8 1, 0, 3,14,25,4,15,26,5,16
; Row[16 - 23]
movu m7, [r2 - 16]
palignr m0, m7, 4
mova m1, m0
palignr m2, m7, 3
palignr m3, m7, 2
mova m4, m3
palignr m5, m7, 1
mova m6, m7
lea r0, [r0 + r1 * 4]
PROC32_8x8 2, 0, 27,6,17,28,7,18,29,8
; Row[24 - 31]
movu m7, [r2 - 21]
palignr m0, m7, 4
palignr m1, m7, 3
mova m2, m1
palignr m3, m7, 2
palignr m4, m7, 1
mova m5, m4
mova m6, m7
lea r0, [r0 + r1 * 4]
PROC32_8x8 3, 0, 19,30,9,20,31,10,21,0
add r6, 8
mov r0, r6
add r2, 8
dec byte [rsp + 63]
jnz .loop
mov rsp, [rsp+64]
RET
INIT_XMM sse4
cglobal intra_pred_ang32_21, 4,7,8
; NOTE: alignment stack to 64 bytes, so all of local data in same cache line
mov r6, rsp
sub rsp, 64+gprsize
and rsp, ~63
mov [rsp+64], r6
; collect reference pixel
movu m0, [r2 + 64]
pinsrb m0, [r2], 0
movu m1, [r2 + 15 + 64]
pshufb m0, [c_mode32_15_0] ; [x x x x x x x 0 2 4 6 8 9 11 13 15]
pshufb m1, [c_mode32_15_0] ; [x x x x x x x 15 17 19 21 23 24 26 28 30]
mova [rsp], m1
movu [rsp + 8], m0
movu m0, [r2 + 1]
movu m1, [r2 + 1 + 16]
movu [rsp + 17], m0
movu [rsp + 17 + 16], m1
mov [rsp + 63], byte 4
; filter
lea r2, [rsp + 17] ; r2 -> [0]
lea r3, [c_shuf8_0] ; r3 -> shuffle8
lea r4, [ang_table] ; r4 -> ang_table
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0] ; r6 -> r0
mova m5, [pw_1024] ; m5 -> 1024
mova m6, [c_deinterval8] ; m6 -> c_deinterval8
.loop:
; Row[0 - 7]
movu m7, [r2 - 5]
palignr m0, m7, 4
palignr m1, m7, 3
mova m2, m1
palignr m3, m7, 2
mova m4, m3
palignr m5, m7, 1
mova m6, m5
PROC32_8x8 0, 0, 15,30,13,28,11,26,9,24
; Row[8 - 15]
movu m7, [r2 - 9]
palignr m0, m7, 4
palignr m1, m7, 3
mova m2, m1
palignr m3, m7, 2
mova m4, m3
palignr m5, m7, 1
mova m6, m5
lea r0, [r0 + r1 * 4]
PROC32_8x8 1, 0, 7,22,5,20,3,18,1,16
; Row[16 - 23]
movu m7, [r2 - 13]
palignr m0, m7, 3
mova m1, m0
palignr m2, m7, 2
mova m3, m2
palignr m4, m7, 1
mova m5, m4
mova m6, m7
lea r0, [r0 + r1 * 4]
PROC32_8x8 2, 0, 31,14,29,12,27,10,25,8
; Row[24 - 31]
movu m7, [r2 - 17]
palignr m0, m7, 3
mova m1, m0
palignr m2, m7, 2
mova m3, m2
palignr m4, m7, 1
mova m5, m4
mova m6, m7
lea r0, [r0 + r1 * 4]
PROC32_8x8 3, 0, 23,6,21,4,19,2,17,0
add r6, 8
mov r0, r6
add r2, 8
dec byte [rsp + 63]
jnz .loop
mov rsp, [rsp+64]
RET
INIT_XMM sse4
cglobal intra_pred_ang32_22, 4,7,8
; NOTE: alignment stack to 64 bytes, so all of local data in same cache line
mov r6, rsp
sub rsp, 64+gprsize
and rsp, ~63
mov [rsp+64], r6
; collect reference pixel
movu m0, [r2 + 64]
pinsrb m0, [r2], 0
movu m1, [r2 + 15 + 64]
pshufb m0, [c_mode32_14_0] ; [x x x x x x x x x 0 2 5 7 10 12 15]
pshufb m1, [c_mode32_14_0] ; [x x x x x x x x x 15 17 20 22 25 27 30]
pslldq m1, 10 ; [17 20 22 25 27 30 x x x x x x x x x x x]
palignr m0, m1, 10 ; [x x x 0 2 5 7 10 12 15 17 20 22 25 27 30]
mova [rsp], m0
movu m0, [r2 + 1]
movu m1, [r2 + 1 + 16]
movu [rsp + 13], m0
movu [rsp + 13 + 16], m1
mov [rsp + 63], byte 4
; filter
lea r2, [rsp + 13] ; r2 -> [0]
lea r3, [c_shuf8_0] ; r3 -> shuffle8
lea r4, [ang_table] ; r4 -> ang_table
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0] ; r6 -> r0
mova m5, [pw_1024] ; m5 -> 1024
mova m6, [c_deinterval8] ; m6 -> c_deinterval8
.loop:
; Row[0 - 7]
movu m7, [r2 - 4]
palignr m0, m7, 3
mova m1, m0
palignr m2, m7, 2
mova m3, m2
palignr m4, m7, 1
mova m5, m4
mova m6, m4
PROC32_8x8 0, 0, 19,6,25,12,31,18,5,24
; Row[8 - 15]
movu m7, [r2 - 7]
palignr m0, m7, 3
palignr m1, m7, 2
mova m2, m1
mova m3, m1
palignr m4, m7, 1
mova m5, m4
mova m6, m7
lea r0, [r0 + r1 * 4]
PROC32_8x8 1, 0, 11,30,17,4,23,10,29,16
; Row[16 - 23]
movu m7, [r2 - 10]
palignr m0, m7, 3
palignr m1, m7, 2
mova m2, m1
palignr m3, m7, 1
mova m4, m3
mova m5, m3
mova m6, m7
lea r0, [r0 + r1 * 4]
PROC32_8x8 2, 0, 3,22,9,28,15,2,21,8
; Row[24 - 31]
movu m7, [r2 - 13]
palignr m0, m7, 2
mova m1, m0
mova m2, m0
palignr m3, m7, 1
mova m4, m3
mova m5, m7
mova m6, m7
lea r0, [r0 + r1 * 4]
PROC32_8x8 3, 0, 27,14,1,20,7,26,13,0
add r6, 8
mov r0, r6
add r2, 8
dec byte [rsp + 63]
jnz .loop
mov rsp, [rsp+64]
RET
INIT_XMM sse4
cglobal intra_pred_ang32_23, 4,7,8,0-(1*mmsize)
%define above [rsp + 0 * mmsize]
lea r3, [r2 + 64]
lea r4, [ang_table + 16 * 16]
lea r5, [r1 * 3] ; r5 -> 3 * stride
mov r6, r0
mova m7, [pw_1024]
MODE_13_23_ROW0 0
add r6, 8
mov r0, r6
add r2, 7
mov r3, 3
.loop:
MODE_13_23 0, 0
add r6, 8
mov r0, r6
add r2, 8
dec r3
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang32_24, 4,7,8,0-(1*mmsize)
%define above [rsp + 0 * mmsize]
lea r3, [r2 + 64]
lea r4, [ang_table + 16 * 16]
lea r5, [r1 * 3] ; r5 -> 3 * stride
mov r6, r0
mova m7, [pw_1024]
MODE_12_24_ROW0 0
add r6, 8
mov r0, r6
add r2, 7
mov r3, 3
.loop:
MODE_12_24 0
add r6, 8
mov r0, r6
add r2, 8
dec r3
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang32_25, 4,7,8
; NOTE: alignment stack to 64 bytes, so all of local data in same cache line
mov r6, rsp
sub rsp, 64+gprsize
and rsp, ~63
mov [rsp+64], r6
; collect reference pixel
movu m0, [r2 + 16 + 64]
pxor m1, m1
pshufb m0, m1 ; [0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0]
mova [rsp], m0
movu m0, [r2]
movu m1, [r2 + 16]
movu m2, [r2 + 32]
movu [rsp + 1], m0
movu [rsp + 1 + 16], m1
movu [rsp + 1 + 32], m2
mov [rsp + 63], byte 4
; filter
lea r2, [rsp + 1] ; r2 -> [0]
lea r3, [c_shuf8_0] ; r3 -> shuffle8
lea r4, [ang_table] ; r4 -> ang_table
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r0] ; r6 -> r0
mova m5, [pw_1024] ; m5 -> 1024
mova m6, [c_deinterval8] ; m6 -> c_deinterval8
.loop:
; Row[0 - 7]
movu m7, [r2]
mova m0, m7
mova m1, m7
mova m2, m7
mova m3, m7
mova m4, m7
mova m5, m7
mova m6, m7
PROC32_8x8 0, 0, 30,28,26,24,22,20,18,16
; Row[8 - 15]
movu m7, [r2]
mova m0, m7
mova m1, m7
mova m2, m7
mova m3, m7
mova m4, m7
mova m5, m7
mova m6, m7
lea r0, [r0 + r1 * 4]
PROC32_8x8 1, 0, 14,12,10,8,6,4,2,0
; Row[16 - 23]
movu m7, [r2 - 1]
mova m0, m7
mova m1, m7
mova m2, m7
mova m3, m7
mova m4, m7
mova m5, m7
mova m6, m7
lea r0, [r0 + r1 * 4]
PROC32_8x8 2, 0, 30,28,26,24,22,20,18,16
; Row[24 - 31]
movu m7, [r2 - 1]
mova m0, m7
mova m1, m7
mova m2, m7
mova m3, m7
mova m4, m7
mova m5, m7
mova m6, m7
lea r0, [r0 + r1 * 4]
PROC32_8x8 3, 0, 14,12,10,8,6,4,2,0
add r6, 8
mov r0, r6
add r2, 8
dec byte [rsp + 63]
jnz .loop
mov rsp, [rsp+64]
RET
INIT_XMM sse4
cglobal intra_pred_ang32_26, 5,7,7,0-(2*mmsize)
%define m8 [rsp + 0 * mmsize]
%define m9 [rsp + 1 * mmsize]
mov r6, 2
movu m0, [r2 + 64]
pinsrb m0, [r2], 0
movu m1, [r2 + 1 + 64]
mova m8, m0
mova m9, m1
mov r3d, r4d
lea r4, [r1 * 3]
.loop:
movu m0, [r2 + 1]
movu [r0], m0
movu [r0 + r1], m0
movu [r0 + r1 * 2], m0
movu [r0 + r4], m0
lea r5, [r0 + r1 * 4]
movu [r5], m0
movu [r5 + r1], m0
movu [r5 + r1 * 2], m0
movu [r5 + r4], m0
lea r5, [r5 + r1 * 4]
movu [r5], m0
movu [r5 + r1], m0
movu [r5 + r1 * 2], m0
movu [r5 + r4], m0
lea r5, [r5 + r1 * 4]
movu [r5], m0
movu [r5 + r1], m0
movu [r5 + r1 * 2], m0
movu [r5 + r4], m0
lea r5, [r0 + r1 * 4]
movu [r5], m0
movu [r5 + r1], m0
movu [r5 + r1 * 2], m0
movu [r5 + r4], m0
lea r5, [r5 + r1 * 4]
movu [r5], m0
movu [r5 + r1], m0
movu [r5 + r1 * 2], m0
movu [r5 + r4], m0
lea r5, [r5 + r1 * 4]
movu [r5], m0
movu [r5 + r1], m0
movu [r5 + r1 * 2], m0
movu [r5 + r4], m0
lea r5, [r5 + r1 * 4]
movu [r5], m0
movu [r5 + r1], m0
movu [r5 + r1 * 2], m0
movu [r5 + r4], m0
lea r5, [r5 + r1 * 4]
movu [r5], m0
movu [r5 + r1], m0
movu [r5 + r1 * 2], m0
movu [r5 + r4], m0
lea r5, [r5 + r1 * 4]
movu [r5], m0
movu [r5 + r1], m0
movu [r5 + r1 * 2], m0
movu [r5 + r4], m0
lea r5, [r5 + r1 * 4]
movu [r5], m0
movu [r5 + r1], m0
movu [r5 + r1 * 2], m0
movu [r5 + r4], m0
; filter
cmp r3d, byte 0
jz .quit
pxor m4, m4
pshufb m0, m4
pmovzxbw m0, m0
mova m1, m0
movu m2, m8
movu m3, m9
pshufb m2, m4
pmovzxbw m2, m2
movhlps m4, m3
pmovzxbw m3, m3
pmovzxbw m4, m4
psubw m3, m2
psubw m4, m2
psraw m3, 1
psraw m4, 1
paddw m0, m3
paddw m1, m4
packuswb m0, m1
pextrb [r0], m0, 0
pextrb [r0 + r1], m0, 1
pextrb [r0 + r1 * 2], m0, 2
pextrb [r0 + r4], m0, 3
lea r5, [r0 + r1 * 4]
pextrb [r5], m0, 4
pextrb [r5 + r1], m0, 5
pextrb [r5 + r1 * 2], m0, 6
pextrb [r5 + r4], m0, 7
lea r5, [r5 + r1 * 4]
pextrb [r5], m0, 8
pextrb [r5 + r1], m0, 9
pextrb [r5 + r1 * 2], m0, 10
pextrb [r5 + r4], m0, 11
lea r5, [r5 + r1 * 4]
pextrb [r5], m0, 12
pextrb [r5 + r1], m0, 13
pextrb [r5 + r1 * 2], m0, 14
pextrb [r5 + r4], m0, 15
.quit:
lea r2, [r2 + 16]
add r0, 16
dec r6d
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang32_27, 3,7,8
lea r3, [ang_table + 16 * 16]
mov r4d, 4
lea r5, [r1 * 3]
mov r6, r0
mova m7, [pw_1024]
.loop:
MODE_9_27 0
add r6, 8
mov r0, r6
add r2, 8
dec r4
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang32_28, 3,7,8
lea r3, [ang_table + 16 * 16]
mov r4d, 4
lea r5, [r1 * 3]
mov r6, r0
mova m7, [pw_1024]
.loop:
MODE_8_28 0
add r6, 8
mov r0, r6
add r2, 8
dec r4
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang32_29, 3,7,8
lea r3, [ang_table + 16 * 16]
mov r4d, 4
lea r5, [r1 * 3]
mov r6, r0
mova m7, [pw_1024]
.loop:
MODE_7_29 0
add r6, 8
mov r0, r6
add r2, 8
dec r4
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang32_30, 3,7,8
lea r3, [ang_table + 16 * 16]
mov r4d, 4
lea r5, [r1 * 3]
mov r6, r0
mova m7, [pw_1024]
.loop:
MODE_6_30 0
add r6, 8
mov r0, r6
add r2, 8
dec r4
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang32_31, 3,7,8
lea r3, [ang_table + 16 * 16]
mov r4d, 4
lea r5, [r1 * 3]
mov r6, r0
mova m7, [pw_1024]
.loop:
MODE_5_31 0
add r6, 8
mov r0, r6
add r2, 8
dec r4
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang32_32, 3,7,8
lea r3, [ang_table + 16 * 16]
mov r4d, 4
lea r5, [r1 * 3]
mov r6, r0
mova m7, [pw_1024]
.loop:
MODE_4_32 0
add r6, 8
mov r0, r6
add r2, 8
dec r4
jnz .loop
RET
INIT_XMM sse4
cglobal intra_pred_ang32_33, 3,7,8
lea r3, [ang_table + 16 * 16]
mov r4d, 4
lea r5, [r1 * 3]
mov r6, r0
mova m7, [pw_1024]
.loop:
MODE_3_33 0
add r6, 8
mov r0, r6
add r2, 8
dec r4
jnz .loop
RET
;-----------------------------------------------------------------------------------------
; start of intra_pred_ang32 angular modes avx2 asm
;-----------------------------------------------------------------------------------------
%if ARCH_X86_64 == 1
INIT_YMM avx2
; register mapping :
; %1-%8 - output registers
; %9 - temp register
; %10 - for label naming
%macro TRANSPOSE_32x8_AVX2 10
jnz .skip%10
; transpose 8x32 to 32x8 and then store
punpcklbw m%9, m%1, m%2
punpckhbw m%1, m%2
punpcklbw m%2, m%3, m%4
punpckhbw m%3, m%4
punpcklbw m%4, m%5, m%6
punpckhbw m%5, m%6
punpcklbw m%6, m%7, m%8
punpckhbw m%7, m%8
punpcklwd m%8, m%9, m%2
punpckhwd m%9, m%2
punpcklwd m%2, m%4, m%6
punpckhwd m%4, m%6
punpcklwd m%6, m%1, m%3
punpckhwd m%1, m%3
punpcklwd m%3, m%5, m%7
punpckhwd m%5, m%7
punpckldq m%7, m%8, m%2
punpckhdq m%8, m%2
punpckldq m%2, m%6, m%3
punpckhdq m%6, m%3
punpckldq m%3, m%9, m%4
punpckhdq m%9, m%4
punpckldq m%4, m%1, m%5
punpckhdq m%1, m%5
movq [r0 + r1 * 0], xm%7
movhps [r0 + r1 * 1], xm%7
movq [r0 + r1 * 2], xm%8
movhps [r0 + r5 * 1], xm%8
lea r0, [r0 + r6]
movq [r0 + r1 * 0], xm%3
movhps [r0 + r1 * 1], xm%3
movq [r0 + r1 * 2], xm%9
movhps [r0 + r5 * 1], xm%9
lea r0, [r0 + r6]
movq [r0 + r1 * 0], xm%2
movhps [r0 + r1 * 1], xm%2
movq [r0 + r1 * 2], xm%6
movhps [r0 + r5 * 1], xm%6
lea r0, [r0 + r6]
movq [r0 + r1 * 0], xm%4
movhps [r0 + r1 * 1], xm%4
movq [r0 + r1 * 2], xm%1
movhps [r0 + r5 * 1], xm%1
lea r0, [r0 + r6]
vpermq m%8, m%8, 00001110b
vpermq m%7, m%7, 00001110b
vpermq m%6, m%6, 00001110b
vpermq m%3, m%3, 00001110b
vpermq m%9, m%9, 00001110b
vpermq m%2, m%2, 00001110b
vpermq m%4, m%4, 00001110b
vpermq m%1, m%1, 00001110b
movq [r0 + r1 * 0], xm%7
movhps [r0 + r1 * 1], xm%7
movq [r0 + r1 * 2], xm%8
movhps [r0 + r5 * 1], xm%8
lea r0, [r0 + r6]
movq [r0 + r1 * 0], xm%3
movhps [r0 + r1 * 1], xm%3
movq [r0 + r1 * 2], xm%9
movhps [r0 + r5 * 1], xm%9
lea r0, [r0 + r6]
movq [r0 + r1 * 0], xm%2
movhps [r0 + r1 * 1], xm%2
movq [r0 + r1 * 2], xm%6
movhps [r0 + r5 * 1], xm%6
lea r0, [r0 + r6]
movq [r0 + r1 * 0], xm%4
movhps [r0 + r1 * 1], xm%4
movq [r0 + r1 * 2], xm%1
movhps [r0 + r5 * 1], xm%1
lea r0, [r4 + 8]
jmp .end%10
.skip%10:
movu [r0 + r1 * 0], m%1
movu [r0 + r1 * 1], m%2
movu [r0 + r1 * 2], m%3
movu [r0 + r5 * 1], m%4
lea r0, [r0 + r6]
movu [r0 + r1 * 0], m%5
movu [r0 + r1 * 1], m%6
movu [r0 + r1 * 2], m%7
movu [r0 + r5 * 1], m%8
lea r0, [r0 + r6]
.end%10:
%endmacro
cglobal ang32_mode_3_33_row_0_15
test r7d, r7d
; rows 0 to 7
movu m0, [r2 + 1] ; [32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
movu m1, [r2 + 2] ; [33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
movu m3, [r2 + 17] ; [48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17]
movu m4, [r2 + 18] ; [49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18]
punpckhbw m2, m0, m1 ; [33 32 32 31 31 30 30 29 29 28 28 27 27 26 26 25 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m0, m1 ; [25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
punpcklbw m3, m4 ; [41 40 40 39 39 38 38 37 37 36 36 35 35 34 34 33 25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17]
pmaddubsw m4, m0, [r3 + 10 * 32] ; [26]
pmulhrsw m4, m7
pmaddubsw m1, m2, [r3 + 10 * 32]
pmulhrsw m1, m7
packuswb m4, m1
palignr m5, m2, m0, 2
palignr m1, m3, m2, 2
pmaddubsw m5, [r3 + 4 * 32] ; [20]
pmulhrsw m5, m7
pmaddubsw m1, [r3 + 4 * 32]
pmulhrsw m1, m7
packuswb m5, m1
palignr m6, m2, m0, 4
palignr m1, m3, m2, 4
pmaddubsw m6, [r3 - 2 * 32] ; [14]
pmulhrsw m6, m7
pmaddubsw m1, [r3 - 2 * 32]
pmulhrsw m1, m7
packuswb m6, m1
palignr m8, m2, m0, 6
palignr m1, m3, m2, 6
pmaddubsw m8, [r3 - 8 * 32] ; [8]
pmulhrsw m8, m7
pmaddubsw m1, [r3 - 8 * 32]
pmulhrsw m1, m7
packuswb m8, m1
palignr m10, m2, m0, 8
palignr m11, m3, m2, 8
pmaddubsw m9, m10, [r3 - 14 * 32] ; [2]
pmulhrsw m9, m7
pmaddubsw m1, m11, [r3 - 14 * 32]
pmulhrsw m1, m7
packuswb m9, m1
pmaddubsw m10, [r3 + 12 * 32] ; [28]
pmulhrsw m10, m7
pmaddubsw m11, [r3 + 12 * 32]
pmulhrsw m11, m7
packuswb m10, m11
palignr m11, m2, m0, 10
palignr m1, m3, m2, 10
pmaddubsw m11, [r3 + 6 * 32] ; [22]
pmulhrsw m11, m7
pmaddubsw m1, [r3 + 6 * 32]
pmulhrsw m1, m7
packuswb m11, m1
palignr m12, m2, m0, 12
palignr m1, m3, m2, 12
pmaddubsw m12, [r3] ; [16]
pmulhrsw m12, m7
pmaddubsw m1, [r3]
pmulhrsw m1, m7
packuswb m12, m1
TRANSPOSE_32x8_AVX2 4, 5, 6, 8, 9, 10, 11, 12, 1, 0
; rows 8 to 15
palignr m4, m2, m0, 14
palignr m1, m3, m2, 14
pmaddubsw m4, [r3 - 6 * 32] ; [10]
pmulhrsw m4, m7
pmaddubsw m1, [r3 - 6 * 32]
pmulhrsw m1, m7
packuswb m4, m1
pmaddubsw m5, m2, [r3 - 12 * 32] ; [4]
pmulhrsw m5, m7
pmaddubsw m1, m3, [r3 - 12 * 32]
pmulhrsw m1, m7
packuswb m5, m1
pmaddubsw m6, m2, [r3 + 14 * 32] ; [30]
pmulhrsw m6, m7
pmaddubsw m1, m3, [r3 + 14 * 32]
pmulhrsw m1, m7
packuswb m6, m1
movu m0, [r2 + 25]
movu m1, [r2 + 26]
punpcklbw m0, m1
palignr m8, m3, m2, 2
palignr m1, m0, m3, 2
pmaddubsw m8, [r3 + 8 * 32] ; [24]
pmulhrsw m8, m7
pmaddubsw m1, [r3 + 8 * 32]
pmulhrsw m1, m7
packuswb m8, m1
palignr m9, m3, m2, 4
palignr m1, m0, m3, 4
pmaddubsw m9, [r3 + 2 * 32] ; [18]
pmulhrsw m9, m7
pmaddubsw m1, [r3 + 2 * 32]
pmulhrsw m1, m7
packuswb m9, m1
palignr m10, m3, m2, 6
palignr m1, m0, m3, 6
pmaddubsw m10, [r3 - 4 * 32] ; [12]
pmulhrsw m10, m7
pmaddubsw m1, [r3 - 4 * 32]
pmulhrsw m1, m7
packuswb m10, m1
palignr m11, m3, m2, 8
palignr m1, m0, m3, 8
pmaddubsw m11, [r3 - 10 * 32] ; [6]
pmulhrsw m11, m7
pmaddubsw m1, [r3 - 10 * 32]
pmulhrsw m1, m7
packuswb m11, m1
movu m12, [r2 + 14]
TRANSPOSE_32x8_AVX2 4, 5, 6, 8, 9, 10, 11, 12, 1, 8
ret
INIT_YMM avx2
cglobal intra_pred_ang32_3, 3,8,13
add r2, 64
lea r3, [ang_table_avx2 + 32 * 16]
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
mov r4, r0
xor r7d, r7d
call ang32_mode_3_33_row_0_15
add r4, 16
mov r0, r4
add r2, 13
call ang32_mode_3_33_row_0_15
RET
INIT_YMM avx2
cglobal intra_pred_ang32_33, 3,8,13
lea r3, [ang_table_avx2 + 32 * 16]
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
xor r7d, r7d
inc r7d
call ang32_mode_3_33_row_0_15
add r2, 13
call ang32_mode_3_33_row_0_15
RET
cglobal ang32_mode_4_32_row_0_15
test r7d, r7d
; rows 0 to 7
movu m0, [r2 + 1] ; [32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
movu m1, [r2 + 2] ; [33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
movu m3, [r2 + 17] ; [48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17]
movu m4, [r2 + 18] ; [49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18]
punpckhbw m2, m0, m1 ; [33 32 32 31 31 30 30 29 29 28 28 27 27 26 26 25 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m0, m1 ; [25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
punpcklbw m3, m4 ; [41 40 40 39 39 38 38 37 37 36 36 35 35 34 34 33 25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17]
pmaddubsw m4, m0, [r3 + 5 * 32] ; [21]
pmulhrsw m4, m7
pmaddubsw m1, m2, [r3 + 5 * 32]
pmulhrsw m1, m7
packuswb m4, m1
palignr m6, m2, m0, 2
palignr m1, m3, m2, 2
pmaddubsw m5, m6, [r3 - 6 * 32] ; [10]
pmulhrsw m5, m7
pmaddubsw m8, m1, [r3 - 6 * 32]
pmulhrsw m8, m7
packuswb m5, m8
pmaddubsw m6, [r3 + 15 * 32] ; [31]
pmulhrsw m6, m7
pmaddubsw m1, [r3 + 15 * 32]
pmulhrsw m1, m7
packuswb m6, m1
palignr m8, m2, m0, 4
palignr m1, m3, m2, 4
pmaddubsw m8, [r3 + 4 * 32] ; [20]
pmulhrsw m8, m7
pmaddubsw m1, [r3 + 4 * 32]
pmulhrsw m1, m7
packuswb m8, m1
palignr m10, m2, m0, 6
palignr m11, m3, m2, 6
pmaddubsw m9, m10, [r3 - 7 * 32] ; [9]
pmulhrsw m9, m7
pmaddubsw m1, m11, [r3 - 7 * 32]
pmulhrsw m1, m7
packuswb m9, m1
pmaddubsw m10, [r3 + 14 * 32] ; [30]
pmulhrsw m10, m7
pmaddubsw m11, [r3 + 14 * 32]
pmulhrsw m11, m7
packuswb m10, m11
palignr m11, m2, m0, 8
palignr m1, m3, m2, 8
pmaddubsw m11, [r3 + 3 * 32] ; [19]
pmulhrsw m11, m7
pmaddubsw m1, [r3 + 3 * 32]
pmulhrsw m1, m7
packuswb m11, m1
palignr m12, m2, m0, 10
palignr m1, m3, m2, 10
pmaddubsw m12, [r3 - 8 * 32] ; [8]
pmulhrsw m12, m7
pmaddubsw m1, [r3 - 8 * 32]
pmulhrsw m1, m7
packuswb m12, m1
TRANSPOSE_32x8_AVX2 4, 5, 6, 8, 9, 10, 11, 12, 1, 0
; rows 8 to 15
palignr m4, m2, m0, 10
palignr m1, m3, m2, 10
pmaddubsw m4, [r3 + 13 * 32] ; [29]
pmulhrsw m4, m7
pmaddubsw m1, [r3 + 13 * 32]
pmulhrsw m1, m7
packuswb m4, m1
palignr m5, m2, m0, 12
palignr m1, m3, m2, 12
pmaddubsw m5, [r3 + 2 * 32] ; [18]
pmulhrsw m5, m7
pmaddubsw m1, [r3 + 2 * 32]
pmulhrsw m1, m7
packuswb m5, m1
palignr m8, m2, m0, 14
palignr m1, m3, m2, 14
pmaddubsw m6, m8, [r3 - 9 * 32] ; [7]
pmulhrsw m6, m7
pmaddubsw m9, m1, [r3 - 9 * 32]
pmulhrsw m9, m7
packuswb m6, m9
pmaddubsw m8, [r3 + 12 * 32] ; [28]
pmulhrsw m8, m7
pmaddubsw m1, [r3 + 12 * 32]
pmulhrsw m1, m7
packuswb m8, m1
pmaddubsw m9, m2, [r3 + 1 * 32] ; [17]
pmulhrsw m9, m7
pmaddubsw m1, m3, [r3 + 1 * 32]
pmulhrsw m1, m7
packuswb m9, m1
movu m0, [r2 + 25]
movu m1, [r2 + 26]
punpcklbw m0, m1
palignr m11, m3, m2, 2
palignr m1, m0, m3, 2
pmaddubsw m10, m11, [r3 - 10 * 32] ; [6]
pmulhrsw m10, m7
pmaddubsw m12, m1, [r3 - 10 * 32]
pmulhrsw m12, m7
packuswb m10, m12
pmaddubsw m11, [r3 + 11 * 32] ; [27]
pmulhrsw m11, m7
pmaddubsw m1, [r3 + 11 * 32]
pmulhrsw m1, m7
packuswb m11, m1
palignr m0, m3, 4
palignr m3, m2, 4
pmaddubsw m3, [r3] ; [16]
pmulhrsw m3, m7
pmaddubsw m0, [r3]
pmulhrsw m0, m7
packuswb m3, m0
TRANSPOSE_32x8_AVX2 4, 5, 6, 8, 9, 10, 11, 3, 0, 8
ret
cglobal ang32_mode_4_32_row_16_31
test r7d, r7d
; rows 0 to 7
movu m0, [r2 + 1] ; [32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
movu m1, [r2 + 2] ; [33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
movu m3, [r2 + 17] ; [48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17]
movu m4, [r2 + 18] ; [49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18]
punpckhbw m2, m0, m1 ; [33 32 32 31 31 30 30 29 29 28 28 27 27 26 26 25 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m0, m1 ; [25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
punpcklbw m3, m4 ; [41 40 40 39 39 38 38 37 37 36 36 35 35 34 34 33 25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17]
pmaddubsw m4, m0, [r3 - 11 * 32] ; [5]
pmulhrsw m4, m7
pmaddubsw m1, m2, [r3 - 11 * 32]
pmulhrsw m1, m7
packuswb m4, m1
pmaddubsw m5, m0, [r3 + 10 * 32] ; [26]
pmulhrsw m5, m7
pmaddubsw m1, m2, [r3 + 10 * 32]
pmulhrsw m1, m7
packuswb m5, m1
palignr m6, m2, m0, 2
palignr m1, m3, m2, 2
pmaddubsw m6, [r3 - 1 * 32] ; [15]
pmulhrsw m6, m7
pmaddubsw m1, [r3 - 1 * 32]
pmulhrsw m1, m7
packuswb m6, m1
palignr m9, m2, m0, 4
palignr m10, m3, m2, 4
pmaddubsw m8, m9, [r3 - 12 * 32] ; [4]
pmulhrsw m8, m7
pmaddubsw m1, m10, [r3 - 12 * 32]
pmulhrsw m1, m7
packuswb m8, m1
pmaddubsw m9, [r3 + 9 * 32] ; [25]
pmulhrsw m9, m7
pmaddubsw m10, [r3 + 9 * 32]
pmulhrsw m10, m7
packuswb m9, m10
palignr m10, m2, m0, 6
palignr m11, m3, m2, 6
pmaddubsw m10, [r3 - 2 * 32] ; [14]
pmulhrsw m10, m7
pmaddubsw m11, [r3 - 2 * 32]
pmulhrsw m11, m7
packuswb m10, m11
palignr m12, m2, m0, 8
palignr m1, m3, m2, 8
pmaddubsw m11, m12, [r3 - 13 * 32] ; [3]
pmulhrsw m11, m7
pmaddubsw m1, [r3 - 13 * 32]
pmulhrsw m1, m7
packuswb m11, m1
palignr m1, m3, m2, 8
pmaddubsw m12, [r3 + 8 * 32] ; [24]
pmulhrsw m12, m7
pmaddubsw m1, [r3 + 8 * 32]
pmulhrsw m1, m7
packuswb m12, m1
TRANSPOSE_32x8_AVX2 4, 5, 6, 8, 9, 10, 11, 12, 1, 0
; rows 8 to 15
palignr m4, m2, m0, 10
palignr m1, m3, m2, 10
pmaddubsw m4, [r3 - 3 * 32] ; [13]
pmulhrsw m4, m7
pmaddubsw m1, [r3 - 3 * 32]
pmulhrsw m1, m7
packuswb m4, m1
palignr m6, m2, m0, 12
palignr m8, m3, m2, 12
pmaddubsw m5, m6, [r3 - 14 * 32] ; [2]
pmulhrsw m5, m7
pmaddubsw m1, m8, [r3 - 14 * 32]
pmulhrsw m1, m7
packuswb m5, m1
pmaddubsw m6, [r3 + 7 * 32] ; [23]
pmulhrsw m6, m7
pmaddubsw m8, [r3 + 7 * 32]
pmulhrsw m8, m7
packuswb m6, m8
palignr m8, m2, m0, 14
palignr m1, m3, m2, 14
pmaddubsw m8, [r3 - 4 * 32] ; [12]
pmulhrsw m8, m7
pmaddubsw m1, [r3 - 4 * 32]
pmulhrsw m1, m7
packuswb m8, m1
pmaddubsw m9, m2, [r3 - 15 * 32] ; [1]
pmulhrsw m9, m7
pmaddubsw m1, m3, [r3 - 15 * 32]
pmulhrsw m1, m7
packuswb m9, m1
pmaddubsw m10, m2, [r3 + 6 * 32] ; [22]
pmulhrsw m10, m7
pmaddubsw m1, m3, [r3 + 6 * 32]
pmulhrsw m1, m7
packuswb m10, m1
movu m0, [r2 + 25]
movu m1, [r2 + 26]
punpcklbw m0, m1
palignr m11, m3, m2, 2
palignr m1, m0, m3, 2
pmaddubsw m11, [r3 - 5 * 32] ; [11]
pmulhrsw m11, m7
pmaddubsw m1, [r3 - 5 * 32]
pmulhrsw m1, m7
packuswb m11, m1
movu m12, [r2 + 11]
TRANSPOSE_32x8_AVX2 4, 5, 6, 8, 9, 10, 11, 12, 1, 8
ret
INIT_YMM avx2
cglobal intra_pred_ang32_4, 3,8,13
add r2, 64
lea r3, [ang_table_avx2 + 32 * 16]
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
mov r4, r0
xor r7d, r7d
call ang32_mode_4_32_row_0_15
add r4, 16
mov r0, r4
add r2, 11
call ang32_mode_4_32_row_16_31
RET
INIT_YMM avx2
cglobal intra_pred_ang32_32, 3,8,13
lea r3, [ang_table_avx2 + 32 * 16]
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
xor r7d, r7d
inc r7d
call ang32_mode_4_32_row_0_15
add r2, 11
call ang32_mode_4_32_row_16_31
RET
cglobal ang32_mode_5_31_row_0_15
test r7d, r7d
; rows 0 to 7
movu m0, [r2 + 1] ; [32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
movu m1, [r2 + 2] ; [33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
movu m3, [r2 + 17] ; [48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17]
movu m4, [r2 + 18] ; [49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18]
punpckhbw m2, m0, m1 ; [33 32 32 31 31 30 30 29 29 28 28 27 27 26 26 25 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m0, m1 ; [25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
punpcklbw m3, m4 ; [41 40 40 39 39 38 38 37 37 36 36 35 35 34 34 33 25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17]
pmaddubsw m4, m0, [r3 + 1 * 32] ; [17]
pmulhrsw m4, m7
pmaddubsw m1, m2, [r3 + 1 * 32]
pmulhrsw m1, m7
packuswb m4, m1
palignr m6, m2, m0, 2
palignr m1, m3, m2, 2
pmaddubsw m5, m6, [r3 - 14 * 32] ; [2]
pmulhrsw m5, m7
pmaddubsw m8, m1, [r3 - 14 * 32]
pmulhrsw m8, m7
packuswb m5, m8
pmaddubsw m6, [r3 + 3 * 32] ; [19]
pmulhrsw m6, m7
pmaddubsw m1, [r3 + 3 * 32]
pmulhrsw m1, m7
packuswb m6, m1
palignr m9, m2, m0, 4
palignr m10, m3, m2, 4
pmaddubsw m8, m9, [r3 - 12 * 32] ; [4]
pmulhrsw m8, m7
pmaddubsw m1, m10, [r3 - 12 * 32]
pmulhrsw m1, m7
packuswb m8, m1
pmaddubsw m9, [r3 + 5 * 32] ; [21]
pmulhrsw m9, m7
pmaddubsw m10, [r3 + 5 * 32]
pmulhrsw m10, m7
packuswb m9, m10
palignr m11, m2, m0, 6
palignr m12, m3, m2, 6
pmaddubsw m10, m11, [r3 - 10 * 32] ; [6]
pmulhrsw m10, m7
pmaddubsw m1, m12, [r3 - 10 * 32]
pmulhrsw m1, m7
packuswb m10, m1
pmaddubsw m11, [r3 + 7 * 32] ; [23]
pmulhrsw m11, m7
pmaddubsw m12, [r3 + 7 * 32]
pmulhrsw m12, m7
packuswb m11, m12
palignr m12, m2, m0, 8
palignr m1, m3, m2, 8
pmaddubsw m12, [r3 - 8 * 32] ; [8]
pmulhrsw m12, m7
pmaddubsw m1, [r3 - 8 * 32]
pmulhrsw m1, m7
packuswb m12, m1
TRANSPOSE_32x8_AVX2 4, 5, 6, 8, 9, 10, 11, 12, 1, 0
; rows 8 to 15
palignr m4, m2, m0, 8
palignr m1, m3, m2, 8
pmaddubsw m4, [r3 + 9 * 32] ; [25]
pmulhrsw m4, m7
pmaddubsw m1, [r3 + 9 * 32]
pmulhrsw m1, m7
packuswb m4, m1
palignr m6, m2, m0, 10
palignr m1, m3, m2, 10
pmaddubsw m5, m6, [r3 - 6 * 32] ; [10]
pmulhrsw m5, m7
pmaddubsw m8, m1, [r3 - 6 * 32]
pmulhrsw m8, m7
packuswb m5, m8
pmaddubsw m6, [r3 + 11 * 32] ; [27]
pmulhrsw m6, m7
pmaddubsw m1, [r3 + 11 * 32]
pmulhrsw m1, m7
packuswb m6, m1
palignr m9, m2, m0, 12
palignr m1, m3, m2, 12
pmaddubsw m8, m9, [r3 - 4 * 32] ; [12]
pmulhrsw m8, m7
pmaddubsw m10, m1, [r3 - 4 * 32]
pmulhrsw m10, m7
packuswb m8, m10
pmaddubsw m9, [r3 + 13 * 32] ; [29]
pmulhrsw m9, m7
pmaddubsw m1, [r3 + 13 * 32]
pmulhrsw m1, m7
packuswb m9, m1
palignr m11, m2, m0, 14
palignr m1, m3, m2, 14
pmaddubsw m10, m11, [r3 - 2 * 32] ; [14]
pmulhrsw m10, m7
pmaddubsw m12, m1, [r3 - 2 * 32]
pmulhrsw m12, m7
packuswb m10, m12
pmaddubsw m11, [r3 + 15 * 32] ; [31]
pmulhrsw m11, m7
pmaddubsw m1, [r3 + 15 * 32]
pmulhrsw m1, m7
packuswb m11, m1
pmaddubsw m2, [r3] ; [16]
pmulhrsw m2, m7
pmaddubsw m3, [r3]
pmulhrsw m3, m7
packuswb m2, m3
TRANSPOSE_32x8_AVX2 4, 5, 6, 8, 9, 10, 11, 2, 0, 8
ret
cglobal ang32_mode_5_31_row_16_31
test r7d, r7d
; rows 0 to 7
movu m0, [r2 + 1] ; [32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
movu m1, [r2 + 2] ; [33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
movu m3, [r2 + 17] ; [48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17]
movu m4, [r2 + 18] ; [49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18]
punpckhbw m2, m0, m1 ; [33 32 32 31 31 30 30 29 29 28 28 27 27 26 26 25 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m0, m1 ; [25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
punpcklbw m3, m4 ; [41 40 40 39 39 38 38 37 37 36 36 35 35 34 34 33 25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17]
pmaddubsw m4, m0, [r3 - 15 * 32] ; [1]
pmulhrsw m4, m7
pmaddubsw m1, m2, [r3 - 15 * 32]
pmulhrsw m1, m7
packuswb m4, m1
pmaddubsw m5, m0, [r3 + 2 * 32] ; [18]
pmulhrsw m5, m7
pmaddubsw m8, m2, [r3 + 2 * 32]
pmulhrsw m8, m7
packuswb m5, m8
palignr m8, m2, m0, 2
palignr m9, m3, m2, 2
pmaddubsw m6, m8, [r3 - 13 * 32] ; [3]
pmulhrsw m6, m7
pmaddubsw m1, m9, [r3 - 13 * 32]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m8, [r3 + 4 * 32] ; [20]
pmulhrsw m8, m7
pmaddubsw m9, [r3 + 4 * 32]
pmulhrsw m9, m7
packuswb m8, m9
palignr m10, m2, m0, 4
palignr m1, m3, m2, 4
pmaddubsw m9, m10, [r3 - 11 * 32] ; [5]
pmulhrsw m9, m7
pmaddubsw m11, m1, [r3 - 11 * 32]
pmulhrsw m11, m7
packuswb m9, m11
pmaddubsw m10, [r3 + 6 * 32] ; [22]
pmulhrsw m10, m7
pmaddubsw m1, [r3 + 6 * 32]
pmulhrsw m1, m7
packuswb m10, m1
palignr m12, m2, m0, 6
palignr m1, m3, m2, 6
pmaddubsw m11, m12, [r3 - 9 * 32] ; [7]
pmulhrsw m11, m7
pmaddubsw m1, [r3 - 9 * 32]
pmulhrsw m1, m7
packuswb m11, m1
palignr m1, m3, m2, 6
pmaddubsw m12, [r3 + 8 * 32] ; [24]
pmulhrsw m12, m7
pmaddubsw m1, [r3 + 8 * 32]
pmulhrsw m1, m7
packuswb m12, m1
TRANSPOSE_32x8_AVX2 4, 5, 6, 8, 9, 10, 11, 12, 1, 0
; rows 8 to 15
palignr m5, m2, m0, 8
palignr m8, m3, m2, 8
pmaddubsw m4, m5, [r3 - 7 * 32] ; [9]
pmulhrsw m4, m7
pmaddubsw m1, m8, [r3 - 7 * 32]
pmulhrsw m1, m7
packuswb m4, m1
pmaddubsw m5, [r3 + 10 * 32] ; [26]
pmulhrsw m5, m7
pmaddubsw m8, [r3 + 10 * 32]
pmulhrsw m8, m7
packuswb m5, m8
palignr m8, m2, m0, 10
palignr m9, m3, m2, 10
pmaddubsw m6, m8, [r3 - 5 * 32] ; [11]
pmulhrsw m6, m7
pmaddubsw m1, m9, [r3 - 5 * 32]
pmulhrsw m1, m7
packuswb m6, m1
pmaddubsw m8, [r3 + 12 * 32] ; [28]
pmulhrsw m8, m7
pmaddubsw m9, [r3 + 12 * 32]
pmulhrsw m9, m7
packuswb m8, m9
palignr m10, m2, m0, 12
palignr m11, m3, m2, 12
pmaddubsw m9, m10, [r3 - 3 * 32] ; [13]
pmulhrsw m9, m7
pmaddubsw m1, m11, [r3 - 3 * 32]
pmulhrsw m1, m7
packuswb m9, m1
pmaddubsw m10, [r3 + 14 * 32] ; [30]
pmulhrsw m10, m7
pmaddubsw m11, [r3 + 14 * 32]
pmulhrsw m11, m7
packuswb m10, m11
palignr m11, m2, m0, 14
palignr m1, m3, m2, 14
pmaddubsw m11, [r3 - 1 * 32] ; [15]
pmulhrsw m11, m7
pmaddubsw m1, [r3 - 1 * 32]
pmulhrsw m1, m7
packuswb m11, m1
movu m2, [r2 + 9]
TRANSPOSE_32x8_AVX2 4, 5, 6, 8, 9, 10, 11, 2, 0, 8
ret
INIT_YMM avx2
cglobal intra_pred_ang32_5, 3,8,13
add r2, 64
lea r3, [ang_table_avx2 + 32 * 16]
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
mov r4, r0
xor r7d, r7d
call ang32_mode_5_31_row_0_15
add r4, 16
mov r0, r4
add r2, 9
call ang32_mode_5_31_row_16_31
RET
INIT_YMM avx2
cglobal intra_pred_ang32_31, 3,8,13
lea r3, [ang_table_avx2 + 32 * 16]
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
xor r7d, r7d
inc r7d
call ang32_mode_5_31_row_0_15
add r2, 9
call ang32_mode_5_31_row_16_31
RET
cglobal ang32_mode_6_30_row_0_15
test r7d, r7d
; rows 0 to 7
movu m0, [r2 + 1] ; [32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
movu m1, [r2 + 2] ; [33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
movu m3, [r2 + 17] ; [48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17]
movu m4, [r2 + 18] ; [49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18]
punpckhbw m2, m0, m1 ; [33 32 32 31 31 30 30 29 29 28 28 27 27 26 26 25 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m0, m1 ; [25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
punpcklbw m3, m4 ; [41 40 40 39 39 38 38 37 37 36 36 35 35 34 34 33 25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17]
pmaddubsw m4, m0, [r3 - 3 * 32] ; [13]
pmulhrsw m4, m7
pmaddubsw m1, m2, [r3 - 3 * 32]
pmulhrsw m1, m7
packuswb m4, m1
pmaddubsw m5, m0, [r3 + 10 * 32] ; [26]
pmulhrsw m5, m7
pmaddubsw m8, m2, [r3 + 10 * 32]
pmulhrsw m8, m7
packuswb m5, m8
palignr m8, m2, m0, 2
palignr m1, m3, m2, 2
pmaddubsw m6, m8, [r3 - 9 * 32] ; [7]
pmulhrsw m6, m7
pmaddubsw m9, m1, [r3 - 9 * 32]
pmulhrsw m9, m7
packuswb m6, m9
pmaddubsw m8, [r3 + 4 * 32] ; [20]
pmulhrsw m8, m7
pmaddubsw m1, [r3 + 4 * 32]
pmulhrsw m1, m7
packuswb m8, m1
palignr m11, m2, m0, 4
palignr m1, m3, m2, 4
pmaddubsw m9, m11, [r3 - 15 * 32] ; [1]
pmulhrsw m9, m7
pmaddubsw m12, m1, [r3 - 15 * 32]
pmulhrsw m12, m7
packuswb m9, m12
pmaddubsw m10, m11, [r3 - 2 * 32] ; [14]
pmulhrsw m10, m7
pmaddubsw m12, m1, [r3 - 2 * 32]
pmulhrsw m12, m7
packuswb m10, m12
pmaddubsw m11, [r3 + 11 * 32] ; [27]
pmulhrsw m11, m7
pmaddubsw m1, [r3 + 11 * 32]
pmulhrsw m1, m7
packuswb m11, m1
palignr m12, m2, m0, 6
palignr m1, m3, m2, 6
pmaddubsw m12, [r3 - 8 * 32] ; [8]
pmulhrsw m12, m7
pmaddubsw m1, [r3 - 8 * 32]
pmulhrsw m1, m7
packuswb m12, m1
TRANSPOSE_32x8_AVX2 4, 5, 6, 8, 9, 10, 11, 12, 1, 0
; rows 8 to 15
palignr m4, m2, m0, 6
palignr m1, m3, m2, 6
pmaddubsw m4, [r3 + 5 * 32] ; [21]
pmulhrsw m4, m7
pmaddubsw m1, [r3 + 5 * 32]
pmulhrsw m1, m7
packuswb m4, m1
palignr m8, m2, m0, 8
palignr m1, m3, m2, 8
pmaddubsw m5, m8, [r3 - 14 * 32] ; [2]
pmulhrsw m5, m7
pmaddubsw m9, m1, [r3 - 14 * 32]
pmulhrsw m9, m7
packuswb m5, m9
pmaddubsw m6, m8, [r3 - 1 * 32] ; [15]
pmulhrsw m6, m7
pmaddubsw m9, m1, [r3 - 1 * 32]
pmulhrsw m9, m7
packuswb m6, m9
pmaddubsw m8, [r3 + 12 * 32] ; [28]
pmulhrsw m8, m7
pmaddubsw m1, [r3 + 12 * 32]
pmulhrsw m1, m7
packuswb m8, m1
palignr m10, m2, m0, 10
palignr m1, m3, m2, 10
pmaddubsw m9, m10, [r3 - 7 * 32] ; [9]
pmulhrsw m9, m7
pmaddubsw m11, m1, [r3 - 7 * 32]
pmulhrsw m11, m7
packuswb m9, m11
pmaddubsw m10, [r3 + 6 * 32] ; [22]
pmulhrsw m10, m7
pmaddubsw m1, m1, [r3 + 6 * 32]
pmulhrsw m1, m7
packuswb m10, m1
palignr m3, m2, 12
palignr m2, m0, 12
pmaddubsw m11, m2, [r3 - 13 * 32] ; [3]
pmulhrsw m11, m7
pmaddubsw m1, m3, [r3 - 13 * 32]
pmulhrsw m1, m7
packuswb m11, m1
pmaddubsw m2, [r3] ; [16]
pmulhrsw m2, m7
pmaddubsw m3, [r3]
pmulhrsw m3, m7
packuswb m2, m3
TRANSPOSE_32x8_AVX2 4, 5, 6, 8, 9, 10, 11, 2, 0, 8
ret
cglobal ang32_mode_6_30_row_16_31
test r7d, r7d
; rows 0 to 7
movu m0, [r2 + 1] ; [32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
movu m1, [r2 + 2] ; [33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
movu m3, [r2 + 17] ; [48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17]
movu m4, [r2 + 18] ; [49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18]
punpckhbw m2, m0, m1 ; [33 32 32 31 31 30 30 29 29 28 28 27 27 26 26 25 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m0, m1 ; [25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
punpcklbw m3, m4 ; [41 40 40 39 39 38 38 37 37 36 36 35 35 34 34 33 25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17]
pmaddubsw m4, m0, [r3 + 13 * 32] ; [29]
pmulhrsw m4, m7
pmaddubsw m1, m2, [r3 + 13 * 32]
pmulhrsw m1, m7
packuswb m4, m1
palignr m6, m2, m0, 2
palignr m1, m3, m2, 2
pmaddubsw m5, m6, [r3 - 6 * 32] ; [10]
pmulhrsw m5, m7
pmaddubsw m8, m1, [r3 - 6 * 32]
pmulhrsw m8, m7
packuswb m5, m8
pmaddubsw m6, [r3 + 7 * 32] ; [23]
pmulhrsw m6, m7
pmaddubsw m1, [r3 + 7 * 32]
pmulhrsw m1, m7
packuswb m6, m1
palignr m10, m2, m0, 4
palignr m1, m3, m2, 4
pmaddubsw m8, m10, [r3 - 12 * 32] ; [4]
pmulhrsw m8, m7
pmaddubsw m11, m1, [r3 - 12 * 32]
pmulhrsw m11, m7
packuswb m8, m11
pmaddubsw m9, m10, [r3 + 1 * 32] ; [17]
pmulhrsw m9, m7
pmaddubsw m11, m1, [r3 + 1 * 32]
pmulhrsw m11, m7
packuswb m9, m11
pmaddubsw m10, [r3 + 14 * 32] ; [30]
pmulhrsw m10, m7
pmaddubsw m1, [r3 + 14 * 32]
pmulhrsw m1, m7
packuswb m10, m1
palignr m12, m2, m0, 6
palignr m1, m3, m2, 6
pmaddubsw m11, m12, [r3 - 5 * 32] ; [11]
pmulhrsw m11, m7
pmaddubsw m1, [r3 - 5 * 32]
pmulhrsw m1, m7
packuswb m11, m1
palignr m1, m3, m2, 6
pmaddubsw m12, [r3 + 8 * 32] ; [24]
pmulhrsw m12, m7
pmaddubsw m1, [r3 + 8 * 32]
pmulhrsw m1, m7
packuswb m12, m1
TRANSPOSE_32x8_AVX2 4, 5, 6, 8, 9, 10, 11, 12, 1, 0
; rows 8 to 15
palignr m6, m2, m0, 8
palignr m1, m3, m2, 8
pmaddubsw m4, m6, [r3 - 11 * 32] ; [5]
pmulhrsw m4, m7
pmaddubsw m8, m1, [r3 - 11 * 32]
pmulhrsw m8, m7
packuswb m4, m8
pmaddubsw m5, m6, [r3 + 2 * 32] ; [18]
pmulhrsw m5, m7
pmaddubsw m9, m1, [r3 + 2 * 32]
pmulhrsw m9, m7
packuswb m5, m9
pmaddubsw m6, [r3 + 15 * 32] ; [31]
pmulhrsw m6, m7
pmaddubsw m1, [r3 + 15 * 32]
pmulhrsw m1, m7
packuswb m6, m1
palignr m9, m2, m0, 10
palignr m1, m3, m2, 10
pmaddubsw m8, m9, [r3 - 4 * 32] ; [12]
pmulhrsw m8, m7
pmaddubsw m10, m1, [r3 - 4 * 32]
pmulhrsw m10, m7
packuswb m8, m10
pmaddubsw m9, [r3 + 9 * 32] ; [25]
pmulhrsw m9, m7
pmaddubsw m1, [r3 + 9 * 32]
pmulhrsw m1, m7
packuswb m9, m1
palignr m3, m2, 12
palignr m2, m0, 12
pmaddubsw m10, m2, [r3 - 10 * 32] ; [6]
pmulhrsw m10, m7
pmaddubsw m1, m3, [r3 - 10 * 32]
pmulhrsw m1, m7
packuswb m10, m1
pmaddubsw m2, [r3 + 3 * 32] ; [19]
pmulhrsw m2, m7
pmaddubsw m3, [r3 + 3 * 32]
pmulhrsw m3, m7
packuswb m2, m3
movu m3, [r2 + 8] ; [0]
TRANSPOSE_32x8_AVX2 4, 5, 6, 8, 9, 10, 2, 3, 0, 8
ret
INIT_YMM avx2
cglobal intra_pred_ang32_6, 3,8,13
add r2, 64
lea r3, [ang_table_avx2 + 32 * 16]
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
mov r4, r0
xor r7d, r7d
call ang32_mode_6_30_row_0_15
add r4, 16
mov r0, r4
add r2, 6
call ang32_mode_6_30_row_16_31
RET
INIT_YMM avx2
cglobal intra_pred_ang32_30, 3,8,13
lea r3, [ang_table_avx2 + 32 * 16]
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
xor r7d, r7d
inc r7d
call ang32_mode_6_30_row_0_15
add r2, 6
call ang32_mode_6_30_row_16_31
RET
cglobal ang32_mode_7_29_row_0_15
test r7d, r7d
; rows 0 to 7
movu m0, [r2 + 1] ; [32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
movu m1, [r2 + 2] ; [33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
movu m3, [r2 + 17] ; [48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17]
movu m4, [r2 + 18] ; [49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18]
punpckhbw m2, m0, m1 ; [33 32 32 31 31 30 30 29 29 28 28 27 27 26 26 25 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m0, m1 ; [25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
punpcklbw m3, m4 ; [41 40 40 39 39 38 38 37 37 36 36 35 35 34 34 33 25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17]
pmaddubsw m4, m0, [r3 - 7 * 32] ; [9]
pmulhrsw m4, m7
pmaddubsw m1, m2, [r3 - 7 * 32]
pmulhrsw m1, m7
packuswb m4, m1
pmaddubsw m5, m0, [r3 + 2 * 32] ; [18]
pmulhrsw m5, m7
pmaddubsw m8, m2, [r3 + 2 * 32]
pmulhrsw m8, m7
packuswb m5, m8
pmaddubsw m6, m0, [r3 + 11 * 32] ; [27]
pmulhrsw m6, m7
pmaddubsw m9, m2, [r3 + 11 * 32]
pmulhrsw m9, m7
packuswb m6, m9
palignr m11, m2, m0, 2
palignr m1, m3, m2, 2
pmaddubsw m8, m11, [r3 - 12 * 32] ; [4]
pmulhrsw m8, m7
pmaddubsw m12, m1, [r3 - 12 * 32]
pmulhrsw m12, m7
packuswb m8, m12
pmaddubsw m9, m11, [r3 - 3 * 32] ; [13]
pmulhrsw m9, m7
pmaddubsw m12, m1, [r3 - 3 * 32]
pmulhrsw m12, m7
packuswb m9, m12
pmaddubsw m10, m11, [r3 + 6 * 32] ; [22]
pmulhrsw m10, m7
pmaddubsw m12, m1, [r3 + 6 * 32]
pmulhrsw m12, m7
packuswb m10, m12
pmaddubsw m11, [r3 + 15 * 32] ; [31]
pmulhrsw m11, m7
pmaddubsw m1, [r3 + 15 * 32]
pmulhrsw m1, m7
packuswb m11, m1
palignr m12, m2, m0, 4
palignr m1, m3, m2, 4
pmaddubsw m12, [r3 - 8 * 32] ; [8]
pmulhrsw m12, m7
pmaddubsw m1, [r3 - 8 * 32]
pmulhrsw m1, m7
packuswb m12, m1
TRANSPOSE_32x8_AVX2 4, 5, 6, 8, 9, 10, 11, 12, 1, 0
; rows 8 to 15
palignr m5, m2, m0, 4
palignr m1, m3, m2, 4
pmaddubsw m4, m5, [r3 + 1 * 32] ; [17]
pmulhrsw m4, m7
pmaddubsw m8, m1, [r3 + 1 * 32]
pmulhrsw m8, m7
packuswb m4, m8
pmaddubsw m5, [r3 + 10 * 32] ; [26]
pmulhrsw m5, m7
pmaddubsw m1, [r3 + 10 * 32]
pmulhrsw m1, m7
packuswb m5, m1
palignr m10, m2, m0, 6
palignr m1, m3, m2, 6
pmaddubsw m6, m10, [r3 - 13 * 32] ; [3]
pmulhrsw m6, m7
pmaddubsw m9, m1, [r3 - 13 * 32]
pmulhrsw m9, m7
packuswb m6, m9
pmaddubsw m8, m10, [r3 - 4 * 32] ; [12]
pmulhrsw m8, m7
pmaddubsw m11, m1, [r3 - 4 * 32]
pmulhrsw m11, m7
packuswb m8, m11
pmaddubsw m9, m10, [r3 + 5 * 32] ; [21]
pmulhrsw m9, m7
pmaddubsw m11, m1, [r3 + 5 * 32]
pmulhrsw m11, m7
packuswb m9, m11
pmaddubsw m10, [r3 + 14 * 32] ; [30]
pmulhrsw m10, m7
pmaddubsw m1, [r3 + 14 * 32]
pmulhrsw m1, m7
packuswb m10, m1
palignr m3, m2, 8
palignr m2, m0, 8
pmaddubsw m11, m2, [r3 - 9 * 32] ; [7]
pmulhrsw m11, m7
pmaddubsw m1, m3, [r3 - 9 * 32]
pmulhrsw m1, m7
packuswb m11, m1
pmaddubsw m2, [r3] ; [16]
pmulhrsw m2, m7
pmaddubsw m3, [r3]
pmulhrsw m3, m7
packuswb m2, m3
TRANSPOSE_32x8_AVX2 4, 5, 6, 8, 9, 10, 11, 2, 0, 8
ret
cglobal ang32_mode_7_29_row_16_31
test r7d, r7d
; rows 0 to 7
movu m0, [r2 + 1] ; [32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
movu m1, [r2 + 2] ; [33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
movu m3, [r2 + 17] ; [48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17]
movu m4, [r2 + 18] ; [49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18]
punpckhbw m2, m0, m1 ; [33 32 32 31 31 30 30 29 29 28 28 27 27 26 26 25 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m0, m1 ; [25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
punpcklbw m3, m4 ; [41 40 40 39 39 38 38 37 37 36 36 35 35 34 34 33 25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17]
pmaddubsw m4, m0, [r3 + 9 * 32] ; [25]
pmulhrsw m4, m7
pmaddubsw m1, m2, [r3 + 9 * 32]
pmulhrsw m1, m7
packuswb m4, m1
palignr m9, m2, m0, 2
palignr m1, m3, m2, 2
pmaddubsw m5, m9, [r3 - 14 * 32] ; [2]
pmulhrsw m5, m7
pmaddubsw m8, m1, [r3 - 14 * 32]
pmulhrsw m8, m7
packuswb m5, m8
pmaddubsw m6, m9, [r3 - 5 * 32] ; [11]
pmulhrsw m6, m7
pmaddubsw m10, m1, [r3 - 5 * 32]
pmulhrsw m10, m7
packuswb m6, m10
pmaddubsw m8, m9, [r3 + 4 * 32] ; [20]
pmulhrsw m8, m7
pmaddubsw m10, m1, [r3 + 4 * 32]
pmulhrsw m10, m7
packuswb m8, m10
pmaddubsw m9, [r3 + 13 * 32] ; [29]
pmulhrsw m9, m7
pmaddubsw m1, [r3 + 13 * 32]
pmulhrsw m1, m7
packuswb m9, m1
palignr m12, m2, m0, 4
palignr m1, m3, m2, 4
pmaddubsw m10, m12, [r3 - 10 * 32] ; [6]
pmulhrsw m10, m7
pmaddubsw m11, m1, [r3 - 10 * 32]
pmulhrsw m11, m7
packuswb m10, m11
pmaddubsw m11, m12, [r3 - 1 * 32] ; [15]
pmulhrsw m11, m7
pmaddubsw m1, [r3 - 1 * 32]
pmulhrsw m1, m7
packuswb m11, m1
palignr m1, m3, m2, 4
pmaddubsw m12, [r3 + 8 * 32] ; [24]
pmulhrsw m12, m7
pmaddubsw m1, [r3 + 8 * 32]
pmulhrsw m1, m7
packuswb m12, m1
TRANSPOSE_32x8_AVX2 4, 5, 6, 8, 9, 10, 11, 12, 1, 0
; rows 8 to 15
palignr m8, m2, m0, 6
palignr m1, m3, m2, 6
pmaddubsw m4, m8, [r3 - 15 * 32] ; [1]
pmulhrsw m4, m7
pmaddubsw m9, m1, [r3 - 15 * 32]
pmulhrsw m9, m7
packuswb m4, m9
pmaddubsw m5, m8, [r3 - 6 * 32] ; [10]
pmulhrsw m5, m7
pmaddubsw m9, m1, [r3 - 6 * 32]
pmulhrsw m9, m7
packuswb m5, m9
pmaddubsw m6, m8, [r3 + 3 * 32] ; [19]
pmulhrsw m6, m7
pmaddubsw m9, m1, [r3 + 3 * 32]
pmulhrsw m9, m7
packuswb m6, m9
pmaddubsw m8, [r3 + 12 * 32] ; [28]
pmulhrsw m8, m7
pmaddubsw m1, [r3 + 12 * 32]
pmulhrsw m1, m7
packuswb m8, m1
palignr m3, m2, 8
palignr m2, m0, 8
pmaddubsw m9, m2, [r3 - 11 * 32] ; [5]
pmulhrsw m9, m7
pmaddubsw m1, m3, [r3 - 11 * 32]
pmulhrsw m1, m7
packuswb m9, m1
pmaddubsw m10, m2, [r3 - 2 * 32] ; [14]
pmulhrsw m10, m7
pmaddubsw m1, m3, [r3 - 2 * 32]
pmulhrsw m1, m7
packuswb m10, m1
pmaddubsw m2, [r3 + 7 * 32] ; [23]
pmulhrsw m2, m7
pmaddubsw m3, [r3 + 7 * 32]
pmulhrsw m3, m7
packuswb m2, m3
movu m1, [r2 + 6] ; [0]
TRANSPOSE_32x8_AVX2 4, 5, 6, 8, 9, 10, 2, 1, 0, 8
ret
INIT_YMM avx2
cglobal intra_pred_ang32_7, 3,8,13
add r2, 64
lea r3, [ang_table_avx2 + 32 * 16]
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
mov r4, r0
xor r7d, r7d
call ang32_mode_7_29_row_0_15
add r4, 16
mov r0, r4
add r2, 4
call ang32_mode_7_29_row_16_31
RET
INIT_YMM avx2
cglobal intra_pred_ang32_29, 3,8,13
lea r3, [ang_table_avx2 + 32 * 16]
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
xor r7d, r7d
inc r7d
call ang32_mode_7_29_row_0_15
add r2, 4
call ang32_mode_7_29_row_16_31
RET
cglobal ang32_mode_8_28_avx2
test r7d, r7d
; rows 0 to 7
movu m0, [r2 + 1] ; [32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
movu m1, [r2 + 2] ; [33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
movu m3, [r2 + 17] ; [48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17]
movu m4, [r2 + 18] ; [49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18]
punpckhbw m2, m0, m1 ; [33 32 32 31 31 30 30 29 29 28 28 27 27 26 26 25 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m0, m1 ; [25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
punpcklbw m3, m4 ; [41 40 40 39 39 38 38 37 37 36 36 35 35 34 34 33 25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17]
pmaddubsw m4, m0, [r3 - 11 * 32] ; [5]
pmulhrsw m4, m7
pmaddubsw m1, m2, [r3 - 11 * 32]
pmulhrsw m1, m7
packuswb m4, m1
pmaddubsw m5, m0, [r3 - 6 * 32] ; [10]
pmulhrsw m5, m7
pmaddubsw m8, m2, [r3 - 6 * 32]
pmulhrsw m8, m7
packuswb m5, m8
pmaddubsw m6, m0, [r3 - 1 * 32] ; [15]
pmulhrsw m6, m7
pmaddubsw m9, m2, [r3 - 1 * 32]
pmulhrsw m9, m7
packuswb m6, m9
pmaddubsw m8, m0, [r3 + 4 * 32] ; [20]
pmulhrsw m8, m7
pmaddubsw m12, m2, [r3 + 4 * 32]
pmulhrsw m12, m7
packuswb m8, m12
pmaddubsw m9, m0, [r3 + 9 * 32] ; [25]
pmulhrsw m9, m7
pmaddubsw m12, m2, [r3 + 9 * 32]
pmulhrsw m12, m7
packuswb m9, m12
pmaddubsw m10, m0, [r3 + 14 * 32] ; [30]
pmulhrsw m10, m7
pmaddubsw m12, m2, [r3 + 14 * 32]
pmulhrsw m12, m7
packuswb m10, m12
palignr m12, m2, m0, 2
palignr m1, m3, m2, 2
pmaddubsw m11, m12, [r3 - 13 * 32] ; [3]
pmulhrsw m11, m7
pmaddubsw m1, [r3 - 13 * 32]
pmulhrsw m1, m7
packuswb m11, m1
palignr m1, m3, m2, 2
pmaddubsw m12, [r3 - 8 * 32] ; [8]
pmulhrsw m12, m7
pmaddubsw m1, [r3 - 8 * 32]
pmulhrsw m1, m7
packuswb m12, m1
TRANSPOSE_32x8_AVX2 4, 5, 6, 8, 9, 10, 11, 12, 1, 0
; rows 8 to 15
palignr m8, m2, m0, 2
palignr m1, m3, m2, 2
pmaddubsw m4, m8, [r3 - 3 * 32] ; [13]
pmulhrsw m4, m7
pmaddubsw m9, m1, [r3 - 3 * 32]
pmulhrsw m9, m7
packuswb m4, m9
pmaddubsw m5, m8, [r3 + 2 * 32] ; [18]
pmulhrsw m5, m7
pmaddubsw m9, m1, [r3 + 2 * 32]
pmulhrsw m9, m7
packuswb m5, m9
pmaddubsw m6, m8, [r3 + 7 * 32] ; [23]
pmulhrsw m6, m7
pmaddubsw m9, m1, [r3 + 7 * 32]
pmulhrsw m9, m7
packuswb m6, m9
pmaddubsw m8, [r3 + 12 * 32] ; [28]
pmulhrsw m8, m7
pmaddubsw m1, [r3 + 12 * 32]
pmulhrsw m1, m7
packuswb m8, m1
palignr m12, m2, m0, 4
palignr m1, m3, m2, 4
pmaddubsw m9, m12, [r3 - 15 * 32] ; [1]
pmulhrsw m9, m7
pmaddubsw m11, m1, [r3 - 15 * 32]
pmulhrsw m11, m7
packuswb m9, m11
pmaddubsw m10, m12, [r3 - 10 * 32] ; [6]
pmulhrsw m10, m7
pmaddubsw m11, m1, [r3 - 10 * 32]
pmulhrsw m11, m7
packuswb m10, m11
pmaddubsw m11, m12, [r3 - 5 * 32] ; [11]
pmulhrsw m11, m7
pmaddubsw m1, [r3 - 5 * 32]
pmulhrsw m1, m7
packuswb m11, m1
palignr m1, m3, m2, 4
pmaddubsw m12, [r3] ; [16]
pmulhrsw m12, m7
pmaddubsw m1, [r3]
pmulhrsw m1, m7
packuswb m12, m1
TRANSPOSE_32x8_AVX2 4, 5, 6, 8, 9, 10, 11, 12, 1, 8
; rows 16 to 23
jnz .doNotAdjustBufferPtr
lea r4, [r4 + mmsize/2]
mov r0, r4
.doNotAdjustBufferPtr:
palignr m6, m2, m0, 4
palignr m1, m3, m2, 4
pmaddubsw m4, m6, [r3 + 5 * 32] ; [21]
pmulhrsw m4, m7
pmaddubsw m8, m1, [r3 + 5 * 32]
pmulhrsw m8, m7
packuswb m4, m8
pmaddubsw m5, m6, [r3 + 10 * 32] ; [26]
pmulhrsw m5, m7
pmaddubsw m8, m1, [r3 + 10 * 32]
pmulhrsw m8, m7
packuswb m5, m8
pmaddubsw m6, [r3 + 15 * 32] ; [31]
pmulhrsw m6, m7
pmaddubsw m1, [r3 + 15 * 32]
pmulhrsw m1, m7
packuswb m6, m1
palignr m12, m2, m0, 6
palignr m1, m3, m2, 6
pmaddubsw m8, m12, [r3 - 12 * 32] ; [4]
pmulhrsw m8, m7
pmaddubsw m11, m1, [r3 - 12 * 32]
pmulhrsw m11, m7
packuswb m8, m11
pmaddubsw m9, m12, [r3 - 7 * 32] ; [9]
pmulhrsw m9, m7
pmaddubsw m11, m1, [r3 - 7 * 32]
pmulhrsw m11, m7
packuswb m9, m11
pmaddubsw m10, m12, [r3 - 2 * 32] ; [14]
pmulhrsw m10, m7
pmaddubsw m11, m1, [r3 - 2 * 32]
pmulhrsw m11, m7
packuswb m10, m11
pmaddubsw m11, m12, [r3 + 3 * 32] ; [19]
pmulhrsw m11, m7
pmaddubsw m1, [r3 + 3 * 32]
pmulhrsw m1, m7
packuswb m11, m1
palignr m1, m3, m2, 6
pmaddubsw m12, [r3 + 8 * 32] ; [24]
pmulhrsw m12, m7
pmaddubsw m1, [r3 + 8 * 32]
pmulhrsw m1, m7
packuswb m12, m1
TRANSPOSE_32x8_AVX2 4, 5, 6, 8, 9, 10, 11, 12, 1, 16
; rows 24 to 31
palignr m4, m2, m0, 6
palignr m1, m3, m2, 6
pmaddubsw m4, [r3 + 13 * 32] ; [29]
pmulhrsw m4, m7
pmaddubsw m1, [r3 + 13 * 32]
pmulhrsw m1, m7
packuswb m4, m1
palignr m3, m2, 8
palignr m2, m0, 8
pmaddubsw m5, m2, [r3 - 14 * 32] ; [2]
pmulhrsw m5, m7
pmaddubsw m9, m3, [r3 - 14 * 32]
pmulhrsw m9, m7
packuswb m5, m9
pmaddubsw m6, m2, [r3 - 9 * 32] ; [7]
pmulhrsw m6, m7
pmaddubsw m9, m3, [r3 - 9 * 32]
pmulhrsw m9, m7
packuswb m6, m9
pmaddubsw m8, m2, [r3 - 4 * 32] ; [12]
pmulhrsw m8, m7
pmaddubsw m1, m3, [r3 - 4 * 32]
pmulhrsw m1, m7
packuswb m8, m1
pmaddubsw m9, m2, [r3 + 1 * 32] ; [17]
pmulhrsw m9, m7
pmaddubsw m11, m3, [r3 + 1 * 32]
pmulhrsw m11, m7
packuswb m9, m11
pmaddubsw m10, m2, [r3 + 6 * 32] ; [22]
pmulhrsw m10, m7
pmaddubsw m1, m3, [r3 + 6 * 32]
pmulhrsw m1, m7
packuswb m10, m1
pmaddubsw m2, [r3 + 11 * 32] ; [27]
pmulhrsw m2, m7
pmaddubsw m3, [r3 + 11 * 32]
pmulhrsw m3, m7
packuswb m2, m3
movu m3, [r2 + 6] ; [0]
TRANSPOSE_32x8_AVX2 4, 5, 6, 8, 9, 10, 2, 3, 0, 24
ret
INIT_YMM avx2
cglobal intra_pred_ang32_8, 3,8,13
add r2, 64
lea r3, [ang_table_avx2 + 32 * 16]
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
mov r4, r0
xor r7d, r7d
call ang32_mode_8_28_avx2
RET
INIT_YMM avx2
cglobal intra_pred_ang32_28, 3,8,13
lea r3, [ang_table_avx2 + 32 * 16]
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
xor r7d, r7d
inc r7d
call ang32_mode_8_28_avx2
RET
INIT_YMM avx2
cglobal intra_pred_ang32_9, 3,5,8
vbroadcasti128 m0, [angHor_tab_9]
vbroadcasti128 m1, [angHor_tab_9 + mmsize/2]
mova m2, [pw_1024]
mova m7, [ang32_shuf_mode9]
lea r3, [r1 * 3]
vbroadcasti128 m3, [r2 + mmsize*2 + 1]
vbroadcasti128 m6, [r2 + mmsize*2 + 17]
pshufb m5, m3, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m6, m3, 1
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m6, m3, 2
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1*2], m4
palignr m5, m6, m3, 3
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 4
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m6, m3, 5
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m6, m3, 6
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1*2], m4
palignr m5, m6, m3, 7
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 8
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m6, m3, 9
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m6, m3, 10
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1*2], m4
palignr m5, m6, m3, 11
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 12
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m6, m3, 13
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m6, m3, 14
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1*2], m4
palignr m5, m6, m3, 15
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
vbroadcasti128 m3, [r2 + mmsize*2 + 33]
pshufb m5, m6, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m3, m6, 1
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m3, m6, 2
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1*2], m4
palignr m5, m3, m6, 3
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m5, m3, m6, 4
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m3, m6, 5
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m3, m6, 6
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1*2], m4
palignr m5, m3, m6, 7
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m5, m3, m6, 8
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m3, m6, 9
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m3, m6, 10
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1*2], m4
palignr m5, m3, m6, 11
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m5, m3, m6, 12
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m3, m6, 13
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m3, m6, 14
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1*2], m4
palignr m5, m3, m6, 15
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
RET
cglobal intra_pred_ang32_27, 3,5,6
lea r3, [ang_table_avx2 + 32 * 16]
lea r4, [r1 * 3] ; r4 -> 3 * stride
mova m5, [pw_1024]
; rows 0 to 7
movu m0, [r2 + 1] ; [32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
movu m1, [r2 + 2] ; [33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
movu m3, [r2 + 17] ; [48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17]
movu m4, [r2 + 18] ; [49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18]
punpckhbw m2, m0, m1 ; [33 32 32 31 31 30 30 29 29 28 28 27 27 26 26 25 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m0, m1 ; [25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
punpcklbw m3, m4 ; [41 40 40 39 39 38 38 37 37 36 36 35 35 34 34 33 25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17]
pmaddubsw m4, m0, [r3 - 14 * 32] ; [2]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 - 14 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m0, [r3 - 12 * 32] ; [4]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 - 12 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m0, [r3 - 10 * 32] ; [6]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 - 10 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pmaddubsw m4, m0, [r3 - 8 * 32] ; [8]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 - 8 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
pmaddubsw m4, m0, [r3 - 6 * 32] ; [10]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 - 6 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m0, [r3 - 4 * 32] ; [12]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 - 4 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m0, [r3 - 2 * 32] ; [14]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 - 2 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pmaddubsw m4, m0, [r3] ; [16]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
; rows 8 to 15
pmaddubsw m4, m0, [r3 + 2 * 32] ; [18]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 + 2 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m0, [r3 + 4 * 32] ; [20]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 + 4 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m0, [r3 + 6 * 32] ; [22]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 + 6 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pmaddubsw m4, m0, [r3 + 8 * 32] ; [24]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 + 8 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
pmaddubsw m4, m0, [r3 + 10 * 32] ; [26]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 + 10 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m0, [r3 + 12 * 32] ; [28]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 + 12 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m0, [r3 + 14 * 32] ; [30]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 + 14 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
palignr m3, m2, 2
palignr m2, m0, 2
movu m1, [r2 + 2] ; [0]
movu [r0 + r4], m1
lea r0, [r0 + r1 * 4]
; rows 16 to 23
pmaddubsw m4, m2, [r3 - 14 * 32] ; [2]
pmulhrsw m4, m5
pmaddubsw m1, m3, [r3 - 14 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m2, [r3 - 12 * 32] ; [4]
pmulhrsw m4, m5
pmaddubsw m1, m3, [r3 - 12 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m2, [r3 - 10 * 32] ; [6]
pmulhrsw m4, m5
pmaddubsw m1, m3, [r3 - 10 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pmaddubsw m4, m2, [r3 - 8 * 32] ; [8]
pmulhrsw m4, m5
pmaddubsw m1, m3, [r3 - 8 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
pmaddubsw m4, m2, [r3 - 6 * 32] ; [10]
pmulhrsw m4, m5
pmaddubsw m1, m3, [r3 - 6 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m2, [r3 - 4 * 32] ; [12]
pmulhrsw m4, m5
pmaddubsw m1, m3, [r3 - 4 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m2, [r3 - 2 * 32] ; [14]
pmulhrsw m4, m5
pmaddubsw m1, m3, [r3 - 2 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pmaddubsw m4, m2, [r3] ; [16]
pmulhrsw m4, m5
pmaddubsw m1, m3, [r3]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
; rows 8 to 15
pmaddubsw m4, m2, [r3 + 2 * 32] ; [18]
pmulhrsw m4, m5
pmaddubsw m1, m3, [r3 + 2 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m2, [r3 + 4 * 32] ; [20]
pmulhrsw m4, m5
pmaddubsw m1, m3, [r3 + 4 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m2, [r3 + 6 * 32] ; [22]
pmulhrsw m4, m5
pmaddubsw m1, m3, [r3 + 6 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pmaddubsw m4, m2, [r3 + 8 * 32] ; [24]
pmulhrsw m4, m5
pmaddubsw m1, m3, [r3 + 8 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
pmaddubsw m4, m2, [r3 + 10 * 32] ; [26]
pmulhrsw m4, m5
pmaddubsw m1, m3, [r3 + 10 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m2, [r3 + 12 * 32] ; [28]
pmulhrsw m4, m5
pmaddubsw m1, m3, [r3 + 12 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m2, [r3 + 14 * 32] ; [30]
pmulhrsw m2, m5
pmaddubsw m3, [r3 + 14 * 32]
pmulhrsw m3, m5
packuswb m2, m3
movu [r0 + r1*2], m2
movu m1, [r2 + 3] ; [0]
movu [r0 + r4], m1
RET
cglobal intra_pred_ang32_10, 5,5,4
pxor m0, m0
mova m1, [pb_1]
lea r4, [r1 * 3]
vbroadcasti128 m2, [r2 + mmsize*2 + 1]
pshufb m3, m2, m0
movu [r0], m3
paddb m0, m1
pshufb m3, m2, m0
movu [r0 + r1], m3
paddb m0, m1
pshufb m3, m2, m0
movu [r0 + r1 * 2], m3
paddb m0, m1
pshufb m3, m2, m0
movu [r0 + r4], m3
lea r0, [r0 + r1 * 4]
paddb m0, m1
pshufb m3, m2, m0
movu [r0], m3
paddb m0, m1
pshufb m3, m2, m0
movu [r0 + r1], m3
paddb m0, m1
pshufb m3, m2, m0
movu [r0 + r1 * 2], m3
paddb m0, m1
pshufb m3, m2, m0
movu [r0 + r4], m3
lea r0, [r0 + r1 * 4]
paddb m0, m1
pshufb m3, m2, m0
movu [r0], m3
paddb m0, m1
pshufb m3, m2, m0
movu [r0 + r1], m3
paddb m0, m1
pshufb m3, m2, m0
movu [r0 + r1 * 2], m3
paddb m0, m1
pshufb m3, m2, m0
movu [r0 + r4], m3
lea r0, [r0 + r1 * 4]
paddb m0, m1
pshufb m3, m2, m0
movu [r0], m3
paddb m0, m1
pshufb m3, m2, m0
movu [r0 + r1], m3
paddb m0, m1
pshufb m3, m2, m0
movu [r0 + r1 * 2], m3
paddb m0, m1
pshufb m3, m2, m0
movu [r0 + r4], m3
lea r0, [r0 + r1 * 4]
pxor m0, m0
vbroadcasti128 m2, [r2 + mmsize*2 + mmsize/2 + 1]
pshufb m3, m2, m0
movu [r0], m3
paddb m0, m1
pshufb m3, m2, m0
movu [r0 + r1], m3
paddb m0, m1
pshufb m3, m2, m0
movu [r0 + r1 * 2], m3
paddb m0, m1
pshufb m3, m2, m0
movu [r0 + r4], m3
lea r0, [r0 + r1 * 4]
paddb m0, m1
pshufb m3, m2, m0
movu [r0], m3
paddb m0, m1
pshufb m3, m2, m0
movu [r0 + r1], m3
paddb m0, m1
pshufb m3, m2, m0
movu [r0 + r1 * 2], m3
paddb m0, m1
pshufb m3, m2, m0
movu [r0 + r4], m3
lea r0, [r0 + r1 * 4]
paddb m0, m1
pshufb m3, m2, m0
movu [r0], m3
paddb m0, m1
pshufb m3, m2, m0
movu [r0 + r1], m3
paddb m0, m1
pshufb m3, m2, m0
movu [r0 + r1 * 2], m3
paddb m0, m1
pshufb m3, m2, m0
movu [r0 + r4], m3
lea r0, [r0 + r1 * 4]
paddb m0, m1
pshufb m3, m2, m0
movu [r0], m3
paddb m0, m1
pshufb m3, m2, m0
movu [r0 + r1], m3
paddb m0, m1
pshufb m3, m2, m0
movu [r0 + r1 * 2], m3
paddb m0, m1
pshufb m3, m2, m0
movu [r0 + r4], m3
RET
cglobal intra_pred_ang32_11, 3,4,8
vbroadcasti128 m0, [angHor_tab_11]
vbroadcasti128 m1, [angHor_tab_11 + mmsize/2]
mova m2, [pw_1024]
mova m7, [ang32_shuf_mode11]
lea r3, [r1 * 3]
; prepare for [16 0 -1 -2 ...]
movu xm3, [r2 + mmsize*2 - 1]
vbroadcasti128 m6, [r2 + mmsize*2 + 15]
pinsrb xm3, [r2 + 0], 1
pinsrb xm3, [r2 + 16], 0
vinserti128 m3, m3, xm3, 1 ; [16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14]
pshufb m5, m3, m7 ; [ 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 16 0 16 0 16 0 16 0 16 0 16 0 16 0 16 0]
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m6, m3, 1
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m6, m3, 2
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m5, m6, m3, 3
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 4
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m6, m3, 5
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m6, m3, 6
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m5, m6, m3, 7
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 8
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m6, m3, 9
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m6, m3, 10
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m5, m6, m3, 11
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 12
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m6, m3, 13
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m6, m3, 14
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m5, m6, m3, 15
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
mova m3, m6
vbroadcasti128 m6, [r2 + mmsize*2 + 15 + 16]
pshufb m5, m3, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m6, m3, 1
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m6, m3, 2
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m5, m6, m3, 3
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 4
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m6, m3, 5
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m6, m3, 6
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m5, m6, m3, 7
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 8
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m6, m3, 9
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m6, m3, 10
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m5, m6, m3, 11
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 12
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m6, m3, 13
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m6, m3, 14
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m5, m6, m3, 15
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
RET
cglobal intra_pred_ang32_25, 3,5,7
lea r3, [ang_table_avx2 + 32 * 16]
lea r4, [r1 * 3]
mova m5, [pw_1024]
; rows 0 to 7
movu m0, [r2 + 0] ; [31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0]
movu m1, [r2 + 1] ; [32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
pinsrb xm3, [r2], 15
pinsrb xm3, [r2 + mmsize*2 + 16], 14
punpckhbw m2, m0, m1 ; [32 31 31 30 30 29 29 28 28 27 27 26 26 25 25 24 16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8]
punpcklbw m0, m1 ; [24 23 23 22 22 21 21 20 20 19 19 18 18 17 17 16 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0]
vinserti128 m3, m3, xm2, 1 ; [16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 0 16 x x x x x x x x x x x x x x]
pmaddubsw m4, m0, [r3 + 14 * 32] ; [30]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 + 14 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m0, [r3 + 12 * 32] ; [28]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 + 12 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m0, [r3 + 10 * 32] ; [26]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 + 10 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pmaddubsw m4, m0, [r3 + 8 * 32] ; [24]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 + 8 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
pmaddubsw m4, m0, [r3 + 6 * 32] ; [22]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 + 6 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m0, [r3 + 4 * 32] ; [20]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 + 4 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m0, [r3 + 2 * 32] ; [18]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 + 2 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pmaddubsw m4, m0, [r3] ; [16]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
; rows 8 to 15
pmaddubsw m4, m0, [r3 - 2 * 32] ; [14]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 - 2 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m0, [r3 - 4 * 32] ; [12]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 - 4 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m0, [r3 - 6 * 32] ; [10]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 - 6 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pmaddubsw m4, m0, [r3 - 8 * 32] ; [8]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 - 8 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
pmaddubsw m4, m0, [r3 - 10 * 32] ; [6]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 - 10 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m0, [r3 - 12 * 32] ; [4]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 - 12 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m0, [r3 - 14 * 32] ; [2]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 - 14 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1 * 2], m4
movu m1, [r2] ; [0]
movu [r0 + r4], m1
lea r0, [r0 + r1 * 4]
palignr m2, m0, 14
palignr m0, m3, 14
; rows 16 to 23
pmaddubsw m4, m0, [r3 + 14 * 32] ; [30]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 + 14 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m0, [r3 + 12 * 32] ; [28]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 + 12 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m0, [r3 + 10 * 32] ; [26]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 + 10 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pmaddubsw m4, m0, [r3 + 8 * 32] ; [24]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 + 8 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
pmaddubsw m4, m0, [r3 + 6 * 32] ; [22]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 + 6 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m0, [r3 + 4 * 32] ; [20]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 + 4 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m0, [r3 + 2 * 32] ; [18]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 + 2 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pmaddubsw m4, m0, [r3] ; [16]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
; rows 24 to 31
pmaddubsw m4, m0, [r3 - 2 * 32] ; [14]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 - 2 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m0, [r3 - 4 * 32] ; [12]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 - 4 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m0, [r3 - 6 * 32] ; [10]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 - 6 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1 * 2], m4
pmaddubsw m4, m0, [r3 - 8 * 32] ; [8]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 - 8 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
pmaddubsw m4, m0, [r3 - 10 * 32] ; [6]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 - 10 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m0, [r3 - 12 * 32] ; [4]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 - 12 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m0, [r3 - 14 * 32] ; [2]
pmulhrsw m0, m5
pmaddubsw m2, [r3 - 14 * 32]
pmulhrsw m2, m5
packuswb m0, m2
movu [r0 + r1*2], m0
movu m1, [r2 + 1] ; [0]
palignr m1, m3, 14
movu [r0 + r4], m1
RET
cglobal intra_pred_ang32_12, 3,4,9
movu m0, [ang32_fact_mode12]
movu m1, [ang32_fact_mode12 + mmsize]
mova m2, [pw_1024]
mova m7, [ang32_shuf_mode12]
mova m8, [ang32_shuf_mode12 + mmsize]
lea r3, [r1 * 3]
; prepare for [26, 19, 13, 6, 0, -1, -2....]
movu xm4, [r2 + mmsize*2 - 4]
vbroadcasti128 m6, [r2 + mmsize*2 + 12]
pinsrb xm4, [r2 + 0], 4
pinsrb xm4, [r2 + 6], 3
pinsrb xm4, [r2 + 13], 2
pinsrb xm4, [r2 + 19], 1
pinsrb xm4, [r2 + 26], 0
vinserti128 m3, m4, xm4, 1 ; [26, 19, 13, 6, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 26, 19, 13, 6, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11]
pshufb m4, m3, m7 ; [ 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 6, 0, 6, 0, 13, 6, 13, 6, 13, 6, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13]
pshufb m5, m3, m8 ; [ 6, 0, 6, 0, 6, 0, 6, 0, 13, 6, 13, 6, 13, 6, 13, 6, 19, 13, 16, 19, 16, 19, 16, 19, 16, 19, 16, 19, 16, 19, 16, 19]
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m4, m6, m3, 1
pshufb m5, m4, m8
pshufb m4, m7
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m4, m6, m3, 2
pshufb m5, m4, m8
pshufb m4, m7
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m4, m6, m3, 3
pshufb m5, m4, m8
pshufb m4, m7
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m4, m6, m3, 4
pshufb m5, m4, m8
pshufb m4, m7
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m4, m6, m3, 5
pshufb m5, m4, m8
pshufb m4, m7
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m4, m6, m3, 6
pshufb m5, m4, m8
pshufb m4, m7
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m4, m6, m3, 7
pshufb m5, m4, m8
pshufb m4, m7
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m4, m6, m3, 8
pshufb m5, m4, m8
pshufb m4, m7
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m4, m6, m3, 9
pshufb m5, m4, m8
pshufb m4, m7
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m4, m6, m3, 10
pshufb m5, m4, m8
pshufb m4, m7
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m4, m6, m3, 11
pshufb m5, m4, m8
pshufb m4, m7
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m4, m6, m3, 12
pshufb m5, m4, m8
pshufb m4, m7
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m4, m6, m3, 13
pshufb m5, m4, m8
pshufb m4, m7
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m4, m6, m3, 14
pshufb m5, m4, m8
pshufb m4, m7
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m4, m6, m3, 15
pshufb m5, m4, m8
pshufb m4, m7
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
mova m3, m6
vbroadcasti128 m6, [r2 + mmsize*2 + 12 + 16]
pshufb m4, m3, m7
pshufb m5, m3, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m4, m6, m3, 1
pshufb m5, m4, m8
pshufb m4, m7
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m4, m6, m3, 2
pshufb m5, m4, m8
pshufb m4, m7
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m4, m6, m3, 3
pshufb m5, m4, m8
pshufb m4, m7
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m4, m6, m3, 4
pshufb m5, m4, m8
pshufb m4, m7
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m4, m6, m3, 5
pshufb m5, m4, m8
pshufb m4, m7
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m4, m6, m3, 6
pshufb m5, m4, m8
pshufb m4, m7
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m4, m6, m3, 7
pshufb m5, m4, m8
pshufb m4, m7
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m4, m6, m3, 8
pshufb m5, m4, m8
pshufb m4, m7
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m4, m6, m3, 9
pshufb m5, m4, m8
pshufb m4, m7
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m4, m6, m3, 10
pshufb m5, m4, m8
pshufb m4, m7
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m4, m6, m3, 11
pshufb m5, m4, m8
pshufb m4, m7
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m4, m6, m3, 12
pshufb m5, m4, m8
pshufb m4, m7
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m4, m6, m3, 13
pshufb m5, m4, m8
pshufb m4, m7
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m4, m6, m3, 14
pshufb m5, m4, m8
pshufb m4, m7
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m4, m6, m3, 15
pshufb m5, m4, m8
pshufb m4, m7
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
RET
cglobal intra_pred_ang32_24, 3,5,8
lea r3, [ang_table_avx2 + 32 * 16]
lea r4, [r1 * 3]
mova m5, [pw_1024]
; rows 0 to 7
movu m0, [r2 + 0]
movu m1, [r2 + 1]
punpckhbw m2, m0, m1
punpcklbw m0, m1
movu m4, [r2 + mmsize*2]
pshufb m4, [ang32_shuf_mode24]
mova m3, [ang32_shuf_mode24 + mmsize]
vpermd m4, m3, m4 ; [6 6 13 13 19 19 26 26 x x x...]
palignr m3, m0, m4, 1
vinserti128 m3, m3, xm2, 1
pmaddubsw m4, m0, [r3 + 11 * 32] ; [27]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 + 11 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m0, [r3 + 6 * 32] ; [22]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 + 6 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m0, [r3 + 1 * 32] ; [17]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 + 1 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pmaddubsw m4, m0, [r3 - 4 * 32] ; [12]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 - 4 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
pmaddubsw m4, m0, [r3 - 9 * 32] ; [7]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 - 9 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m0, [r3 - 14 * 32] ; [2]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 - 14 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
palignr m6, m0, m3, 14
palignr m7, m2, m0, 14
pmaddubsw m4, m6, [r3 + 13 * 32] ; [29]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 13 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pmaddubsw m4, m6, [r3 + 8 * 32] ; [24]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 8 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
; rows 8 to 15
pmaddubsw m4, m6, [r3 + 3 * 32] ; [19]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 3 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m6, [r3 - 2 * 32] ; [14]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 2 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m6, [r3 - 7 * 32] ; [9]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 7 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pmaddubsw m4, m6, [r3 - 12 * 32] ; [4]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 12 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
palignr m6, m0, m3, 12
palignr m7, m2, m0, 12
pmaddubsw m4, m6, [r3 + 15 * 32] ; [31]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 15 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m6, [r3 + 10 * 32] ; [26]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 10 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m6, [r3 + 5 * 32] ; [21]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 5 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1 * 2], m4
pmaddubsw m4, m6, [r3] ; [16]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
; rows 16 to 23
pmaddubsw m4, m6, [r3 - 5 * 32] ; [11]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 5 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m6, [r3 - 10 * 32] ; [6]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 10 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m6, [r3 - 15 * 32] ; [1]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 15 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
palignr m6, m0, m3, 10
palignr m7, m2, m0, 10
pmaddubsw m4, m6, [r3 + 12 * 32] ; [28]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 12 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
pmaddubsw m4, m6, [r3 + 7 * 32] ; [23]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 7 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m6, [r3 + 2 * 32] ; [18]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 2 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m6, [r3 - 3 * 32] ; [13]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 3 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pmaddubsw m4, m6, [r3 - 8 * 32] ; [8]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 8 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
; rows 24 to 31
pmaddubsw m4, m6, [r3 - 13 * 32] ; [3]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 13 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
palignr m6, m0, m3, 8
palignr m7, m2, m0, 8
pmaddubsw m4, m6, [r3 + 14 * 32] ; [30]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 14 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m6, [r3 + 9 * 32] ; [25]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 9 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1 * 2], m4
pmaddubsw m4, m6, [r3 + 4 * 32] ; [20]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 4 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
pmaddubsw m4, m6, [r3 - 1 * 32] ; [15]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 1 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m6, [r3 - 6 * 32] ; [10]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 6 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m6, [r3 - 11 * 32] ; [5]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 11 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pand m6, [pw_00ff]
pand m7, [pw_00ff]
packuswb m6, m7
movu [r0 + r4], m6
RET
cglobal intra_pred_ang32_13, 3,4,9
movu m0, [ang32_fact_mode13]
movu m1, [ang32_fact_mode13 + mmsize]
mova m2, [pw_1024]
mova m7, [ang32_shuf_mode13]
mova m8, [ang32_shuf_mode13 + mmsize]
lea r3, [r1 * 3]
; prepare for [28, 25, 21, 18, 14, 11, 7, 4, 0, -1, -2....]
movu m6, [r2]
pshufb m6, [ang32_shuf_mode13 + mmsize*2]
mova m3, [ang32_shuf_mode24 + mmsize*1]
vpermd m6, m3, m6
palignr m6, m6, 1
vbroadcasti128 m3, [r2 + mmsize*2 + 1]
palignr m5, m3, m6, 1
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m3, m6, 2
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m3, m6, 3
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m5, m3, m6, 4
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m5, m3, m6, 5
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m3, m6, 6
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m3, m6, 7
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m5, m3, m6, 8
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m5, m3, m6, 9
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m3, m6, 10
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m3, m6, 11
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m5, m3, m6, 12
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m5, m3, m6, 13
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m3, m6, 14
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m3, m6, 15
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
pshufb m4, m3, m7
pshufb m5, m3, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
mova m6, m3
vbroadcasti128 m3, [r2 + mmsize*2 + 17]
palignr m5, m3, m6, 1
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m3, m6, 2
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m3, m6, 3
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m5, m3, m6, 4
pshufb m4, m5, m7
pshufb m5, m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m5, m3, m6, 5
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m3, m6, 6
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m3, m6, 7
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m5, m3, m6, 8
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m5, m3, m6, 9
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m3, m6, 10
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m3, m6, 11
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m5, m3, m6, 12
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m5, m3, m6, 13
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m3, m6, 14
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m3, m6, 15
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
pshufb m4, m3, m7
pshufb m5, m3, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
RET
cglobal intra_pred_ang32_23, 3,5,8
lea r3, [ang_table_avx2 + 32 * 16]
lea r4, [r1 * 3]
mova m5, [pw_1024]
; rows 0 to 7
movu m0, [r2 + 0]
movu m1, [r2 + 1]
punpckhbw m2, m0, m1
punpcklbw m0, m1
movu m4, [r2 + mmsize*2]
pshufb m4, [ang32_shuf_mode23]
vpermq m4, m4, q1313
palignr m3, m0, m4, 1
vinserti128 m3, m3, xm2, 1
pmaddubsw m4, m0, [r3 + 7 * 32] ; [23]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 + 7 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m0, [r3 - 2 * 32] ; [14]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 - 2 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m0, [r3 - 11 * 32] ; [5]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 - 11 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
palignr m6, m0, m3, 14
palignr m7, m2, m0, 14
pmaddubsw m4, m6, [r3 + 12 * 32] ; [28]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 12 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
pmaddubsw m4, m6, [r3 + 3 * 32] ; [19]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 3 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m6, [r3 - 6 * 32] ; [10]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 6 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m6, [r3 - 15 * 32] ; [1]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 15 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
palignr m6, m0, m3, 12
palignr m7, m2, m0, 12
pmaddubsw m4, m6, [r3 + 8 * 32] ; [24]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 8 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
; rows 8 to 15
pmaddubsw m4, m6, [r3 - 1 * 32] ; [15]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 1 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m6, [r3 - 10 * 32] ; [6]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 10 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
palignr m6, m0, m3, 10
palignr m7, m2, m0, 10
pmaddubsw m4, m6, [r3 + 13 * 32] ; [29]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 13 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pmaddubsw m4, m6, [r3 + 4 * 32] ; [20]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 4 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
pmaddubsw m4, m6, [r3 - 5 * 32] ; [11]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 5 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m6, [r3 - 14 * 32] ; [2]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 14 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
palignr m6, m0, m3, 8
palignr m7, m2, m0, 8
pmaddubsw m4, m6, [r3 + 9 * 32] ; [25]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 9 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1 * 2], m4
pmaddubsw m4, m6, [r3] ; [16]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
; rows 16 to 23
pmaddubsw m4, m6, [r3 - 9 * 32] ; [7]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 9 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
palignr m6, m0, m3, 6
palignr m7, m2, m0, 6
pmaddubsw m4, m6, [r3 + 14 * 32] ; [30]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 14 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m6, [r3 + 5 * 32] ; [21]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 5 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pmaddubsw m4, m6, [r3 - 4 * 32] ; [12]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 4 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
pmaddubsw m4, m6, [r3 - 13 * 32] ; [3]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 13 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
palignr m6, m0, m3, 4
palignr m7, m2, m0, 4
pmaddubsw m4, m6, [r3 + 10 * 32] ; [26]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 10 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m6, [r3 + 1 * 32] ; [17]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 1 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pmaddubsw m4, m6, [r3 - 8 * 32] ; [8]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 8 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
; rows 24 to 31
palignr m6, m0, m3, 2
palignr m7, m2, m0, 2
pmaddubsw m4, m6, [r3 + 15 * 32] ; [31]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 15 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m6, [r3 + 6 * 32] ; [22]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 6 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m6, [r3 - 3 * 32] ; [13]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 3 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1 * 2], m4
pmaddubsw m4, m6, [r3 - 12 * 32] ; [4]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 12 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
pmaddubsw m4, m3, [r3 + 11 * 32] ; [27]
pmulhrsw m4, m5
pmaddubsw m1, m0, [r3 + 11 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m3, [r3 + 2 * 32] ; [18]
pmulhrsw m4, m5
pmaddubsw m1, m0, [r3 + 2 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m3, [r3 - 7 * 32] ; [9]
pmulhrsw m4, m5
pmaddubsw m1, m0, [r3 - 7 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pand m3, [pw_00ff]
pand m0, [pw_00ff]
packuswb m3, m0
movu [r0 + r4], m3
RET
cglobal intra_pred_ang32_14, 3,4,9
movu m0, [ang32_fact_mode14]
movu m1, [ang32_fact_mode14 + mmsize]
mova m2, [pw_1024]
mova m7, [ang32_shuf_mode14]
mova m8, [ang32_shuf_mode14 + mmsize]
lea r3, [r1 * 3]
; prepare for [30, 27, 25, 22, 20, 17, 15, 12, 10, 7, 5, 2, 0, -1, -2...]
movu m6, [r2]
pshufb m6, [ang32_shuf_mode14 + mmsize*2]
vpermq m6, m6, 01110111b
pslldq m6, m6, 1
vbroadcasti128 m3, [r2 + mmsize*2 + 1]
palignr m5, m3, m6, 1
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m3, m6, 2
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m3, m6, 3
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m5, m3, m6, 4
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m5, m3, m6, 5
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m3, m6, 6
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m3, m6, 7
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m5, m3, m6, 8
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m5, m3, m6, 9
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m3, m6, 10
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m3, m6, 11
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m5, m3, m6, 12
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m5, m3, m6, 13
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m3, m6, 14
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m3, m6, 15
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
pshufb m4, m3, m7
pshufb m5, m3, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
mova m6, m3
vbroadcasti128 m3, [r2 + mmsize*2 + 17]
palignr m5, m3, m6, 1
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m3, m6, 2
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m3, m6, 3
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m5, m3, m6, 4
pshufb m4, m5, m7
pshufb m5, m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m5, m3, m6, 5
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m3, m6, 6
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m3, m6, 7
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m5, m3, m6, 8
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m5, m3, m6, 9
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m3, m6, 10
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m3, m6, 11
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m5, m3, m6, 12
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m5, m3, m6, 13
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m5, m3, m6, 14
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m5, m3, m6, 15
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
pshufb m4, m3, m7
pshufb m5, m3, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
RET
cglobal intra_pred_ang32_22, 3,5,9
lea r3, [ang_table_avx2 + 32 * 16]
lea r4, [r1 * 3]
mova m5, [pw_1024]
; rows 0 to 7
movu m0, [r2 + 0]
movu m1, [r2 + 1]
punpckhbw m2, m0, m1
punpcklbw m0, m1
movu m4, [r2 + mmsize*2 + 2]
pshufb m4, [ang32_shuf_mode22]
vextracti128 xm8, m4, 1
palignr m3, m0, m4, 2
palignr m3, m8, 15
vinserti128 m3, m3, xm2, 1
vinserti128 m8, m8, xm0, 1
pmaddubsw m4, m0, [r3 + 3 * 32] ; [19]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 + 3 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m0, [r3 - 10 * 32] ; [6]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 - 10 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
palignr m6, m0, m3, 14
palignr m7, m2, m0, 14
pmaddubsw m4, m6, [r3 + 9 * 32] ; [25]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 9 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pmaddubsw m4, m6, [r3 - 4 * 32] ; [12]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 4 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
palignr m6, m0, m3, 12
palignr m7, m2, m0, 12
pmaddubsw m4, m6, [r3 + 15 * 32] ; [31]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 15 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m6, [r3 + 2 * 32] ; [18]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 2 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m6, [r3 - 11 * 32] ; [5]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 11 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
palignr m6, m0, m3, 10
palignr m7, m2, m0, 10
pmaddubsw m4, m6, [r3 + 8 * 32] ; [24]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 8 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
; rows 8 to 15
pmaddubsw m4, m6, [r3 - 5 * 32] ; [11]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 5 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
palignr m6, m0, m3, 8
palignr m7, m2, m0, 8
pmaddubsw m4, m6, [r3 + 14 * 32] ; [30]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 14 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m6, [r3 + 1 * 32] ; [17]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 1 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pmaddubsw m4, m6, [r3 - 12 * 32] ; [4]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 12 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
palignr m6, m0, m3, 6
palignr m7, m2, m0, 6
pmaddubsw m4, m6, [r3 + 7 * 32] ; [23]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 7 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m6, [r3 - 6 * 32] ; [10]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 6 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
palignr m6, m0, m3, 4
palignr m7, m2, m0, 4
pmaddubsw m4, m6, [r3 + 13 * 32] ; [29]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 13 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1 * 2], m4
pmaddubsw m4, m6, [r3] ; [16]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
; rows 16 to 23
pmaddubsw m4, m6, [r3 - 13 * 32] ; [3]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 13 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
palignr m6, m0, m3, 2
palignr m7, m2, m0, 2
pmaddubsw m4, m6, [r3 + 6 * 32] ; [22]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 6 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m6, [r3 - 7 * 32] ; [9]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 7 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pmaddubsw m4, m3, [r3 + 12 * 32] ; [28]
pmulhrsw m4, m5
pmaddubsw m1, m0, [r3 + 12 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
pmaddubsw m4, m3, [r3 - 1 * 32] ; [15]
pmulhrsw m4, m5
pmaddubsw m1, m0, [r3 - 1 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m3, [r3 - 14 * 32] ; [2]
pmulhrsw m4, m5
pmaddubsw m1, m0, [r3 - 14 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
palignr m6, m3, m8, 14
palignr m7, m0, m3, 14
pmaddubsw m4, m6, [r3 + 5 * 32] ; [21]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 5 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pmaddubsw m4, m6, [r3 - 8 * 32] ; [8]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 8 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
; rows 24 to 31
palignr m6, m3, m8, 12
palignr m7, m0, m3, 12
pmaddubsw m4, m6, [r3 + 11 * 32] ; [27]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 11 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m6, [r3 - 2 * 32] ; [14]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 2 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m6, [r3 - 15 * 32] ; [1]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 15 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1 * 2], m4
palignr m6, m3, m8, 10
palignr m7, m0, m3, 10
pmaddubsw m4, m6, [r3 + 4 * 32] ; [20]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 4 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
pmaddubsw m4, m6, [r3 - 9 * 32] ; [7]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 9 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
palignr m0, m3, 8
palignr m3, m8, 8
pmaddubsw m4, m3, [r3 + 10 * 32] ; [26]
pmulhrsw m4, m5
pmaddubsw m1, m0, [r3 + 10 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m3, [r3 - 3 * 32] ; [13]
pmulhrsw m4, m5
pmaddubsw m1, m0, [r3 - 3 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pand m3, [pw_00ff]
pand m0, [pw_00ff]
packuswb m3, m0
movu [r0 + r4], m3
RET
cglobal intra_pred_ang32_15, 3,4,9
movu m0, [ang32_fact_mode15]
movu m1, [ang32_fact_mode15 + mmsize]
mova m2, [pw_1024]
mova m7, [ang32_shuf_mode15]
mova m8, [ang32_shuf_mode15 + mmsize]
lea r3, [r1 * 3]
; prepare for [30, 28, 26, 24, 23, 21, 19, 17, 15, 13, 11, 9, 8, 6, 4, 2, 0, -1, -2...]
movu m6, [r2]
pshufb m6, [ang32_shuf_mode15 + mmsize*2]
vpermq m6, m6, 01110111b
movu xm3, [r2 + mmsize*2]
pinsrb xm3, [r2], 0
vpermq m3, m3, 01000100b
palignr m4, m3, m6, 2
pshufb m4, m7
pshufb m5, m6, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m4, m3, m6, 3
pshufb m4, m7
palignr m5, m3, m6, 1
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m4, m3, m6, 4
pshufb m4, m7
palignr m5, m3, m6, 2
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m4, m3, m6, 5
pshufb m4, m7
palignr m5, m3, m6, 3
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m4, m3, m6, 6
pshufb m4, m7
palignr m5, m3, m6, 4
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m4, m3, m6, 7
pshufb m4, m7
palignr m5, m3, m6, 5
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m4, m3, m6, 8
pshufb m4, m7
palignr m5, m3, m6, 6
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m4, m3, m6, 9
pshufb m4, m7
palignr m5, m3, m6, 7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m4, m3, m6, 10
pshufb m4, m7
palignr m5, m3, m6, 8
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m4, m3, m6, 11
pshufb m4, m7
palignr m5, m3, m6, 9
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m4, m3, m6, 12
pshufb m4, m7
palignr m5, m3, m6, 10
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m4, m3, m6, 13
pshufb m4, m7
palignr m5, m3, m6, 11
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m4, m3, m6, 14
pshufb m4, m7
palignr m5, m3, m6, 12
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m4, m3, m6, 15
pshufb m4, m7
palignr m5, m3, m6, 13
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
pshufb m4, m3, m7
palignr m5, m3, m6, 14
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m5, m3, m6, 15
mova m6, m3
vbroadcasti128 m3, [r2 + mmsize*2 + 16]
palignr m4, m3, m6, 1
pshufb m4, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m4, m3, m6, 2
pshufb m4, m7
pshufb m5, m6, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m4, m3, m6, 3
pshufb m4, m7
palignr m5, m3, m6, 1
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m4, m3, m6, 4
pshufb m4, m7
palignr m5, m3, m6, 2
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m4, m3, m6, 5
pshufb m4, m7
palignr m5, m3, m6, 3
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m4, m3, m6, 6
pshufb m4, m7
palignr m5, m3, m6, 4
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m4, m3, m6, 7
pshufb m4, m7
palignr m5, m3, m6, 5
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m4, m3, m6, 8
pshufb m4, m7
palignr m5, m3, m6, 6
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m4, m3, m6, 9
pshufb m4, m7
palignr m5, m3, m6, 7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m4, m3, m6, 10
pshufb m4, m7
palignr m5, m3, m6, 8
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m4, m3, m6, 11
pshufb m4, m7
palignr m5, m3, m6, 9
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
palignr m4, m3, m6, 12
pshufb m4, m7
palignr m5, m3, m6, 10
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m4, m3, m6, 13
pshufb m4, m7
palignr m5, m3, m6, 11
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m4, m3, m6, 14
pshufb m4, m7
palignr m5, m3, m6, 12
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], m4
palignr m4, m3, m6, 15
pshufb m4, m7
palignr m5, m3, m6, 13
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1], m4
pshufb m4, m3, m7
palignr m5, m3, m6, 14
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], m4
palignr m5, m3, m6, 15
vbroadcasti128 m6, [r2 + mmsize*2 + 32]
palignr m4, m6, m3, 1
pshufb m4, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r3], m4
RET
cglobal intra_pred_ang32_21, 3,5,9
lea r3, [ang_table_avx2 + 32 * 16]
lea r4, [r1 * 3]
mova m5, [pw_1024]
; rows 0 to 7
movu m0, [r2 + 0]
movu m1, [r2 + 1]
punpckhbw m2, m0, m1
punpcklbw m0, m1
movu m4, [r2 + mmsize*2]
pshufb m4, [ang32_shuf_mode21]
vextracti128 xm6, m4, 1
palignr m3, m0, m4, 1
palignr m8, m3, m6, 1
vinserti128 m3, m3, xm2, 1
vinserti128 m8, m8, xm0, 1
pmaddubsw m4, m0, [r3 - 1 * 32] ; [15]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 - 1 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
palignr m6, m0, m3, 14
palignr m7, m2, m0, 14
pmaddubsw m4, m6, [r3 + 14 * 32] ; [30]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 14 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m6, [r3 - 3 * 32] ; [13]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 3 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
palignr m6, m0, m3, 12
palignr m7, m2, m0, 12
pmaddubsw m4, m6, [r3 + 12 * 32] ; [28]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 12 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
pmaddubsw m4, m6, [r3 - 5 * 32] ; [11]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 5 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
palignr m6, m0, m3, 10
palignr m7, m2, m0, 10
pmaddubsw m4, m6, [r3 + 10 * 32] ; [26]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 10 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m6, [r3 - 7 * 32] ; [9]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 7 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
palignr m6, m0, m3, 8
palignr m7, m2, m0, 8
pmaddubsw m4, m6, [r3 + 8 * 32] ; [24]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 8 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
; rows 8 to 15
pmaddubsw m4, m6, [r3 - 9 * 32] ; [7]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 9 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
palignr m6, m0, m3, 6
palignr m7, m2, m0, 6
pmaddubsw m4, m6, [r3 + 6 * 32] ; [22]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 6 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m6, [r3 - 11 * 32] ; [5]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 11 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
palignr m6, m0, m3, 4
palignr m7, m2, m0, 4
pmaddubsw m4, m6, [r3 + 4 * 32] ; [20]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 4 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
pmaddubsw m4, m6, [r3 - 13 * 32] ; [3]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 13 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
palignr m6, m0, m3, 2
palignr m7, m2, m0, 2
pmaddubsw m4, m6, [r3 + 2 * 32] ; [18]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 2 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m6, [r3 - 15 * 32] ; [1]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 15 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1 * 2], m4
pmaddubsw m4, m3, [r3] ; [16]
pmulhrsw m4, m5
pmaddubsw m1, m0, [r3]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
; rows 16 to 23
palignr m6, m3, m8, 14
palignr m7, m0, m3, 14
pmaddubsw m4, m6, [r3 + 15 * 32] ; [31]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 15 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m6, [r3 - 2 * 32] ; [14]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 2 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
palignr m6, m3, m8, 12
palignr m7, m0, m3, 12
pmaddubsw m4, m6, [r3 + 13 * 32] ; [29]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 13 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pmaddubsw m4, m6, [r3 - 4 * 32] ; [12]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 4 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
palignr m6, m3, m8, 10
palignr m7, m0, m3, 10
pmaddubsw m4, m6, [r3 + 11 * 32] ; [27]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 11 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m6, [r3 - 6 * 32] ; [10]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 6 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
palignr m6, m3, m8, 8
palignr m7, m0, m3, 8
pmaddubsw m4, m6, [r3 + 9 * 32] ; [25]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 9 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pmaddubsw m4, m6, [r3 - 8 * 32] ; [8]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 8 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
; rows 24 to 31
palignr m6, m3, m8, 6
palignr m7, m0, m3, 6
pmaddubsw m4, m6, [r3 + 7 * 32] ; [23]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 7 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m6, [r3 - 10 * 32] ; [6]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 10 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
palignr m6, m3, m8, 4
palignr m7, m0, m3, 4
pmaddubsw m4, m6, [r3 + 5 * 32] ; [21]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 5 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1 * 2], m4
pmaddubsw m4, m6, [r3 - 12 * 32] ; [4]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 12 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
palignr m6, m3, m8, 2
palignr m7, m0, m3, 2
pmaddubsw m4, m6, [r3 + 3 * 32] ; [19]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 3 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m6, [r3 - 14 * 32] ; [2]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 14 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m8, [r3 + 1 * 32] ; [17]
pmulhrsw m4, m5
pmaddubsw m1, m3, [r3 + 1 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pand m8, [pw_00ff]
pand m3, [pw_00ff]
packuswb m8, m3
movu [r0 + r4], m8
RET
cglobal intra_pred_ang32_16, 3,4,10
movu m0, [ang32_fact_mode16]
movu m1, [ang32_fact_mode16 + mmsize]
mova m2, [pw_1024]
mova m7, [ang32_shuf_mode16]
mova m8, [ang32_shuf_mode16 + mmsize]
lea r3, [r1 * 3]
; prepare for [30, 29, 27, 26, 24, 23, 21, 20, 18, 17, 15, 14, 12, 11, 9, 8, 6, 5, 3, 2, 0, -1, -2...]
movu m6, [r2]
pshufb m6, [ang32_shuf_mode16 + mmsize*2]
mova m9, m6
mova m3, [ang32_shuf_mode16 + mmsize*3]
vpermd m6, m3, m6
vpermq m9, m9, q3232
pslldq m9, 4
palignr m6, m9, 15
pslldq m9, 1
vbroadcasti128 m3, [r2 + mmsize*2 + 1]
palignr m4, m3, m6, 1
palignr m5, m6, m9, 6
pshufb m4, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0], m4
palignr m4, m3, m6, 2
palignr m5, m6, m9, 7
pshufb m4, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1], m4
palignr m4, m3, m6, 3
palignr m5, m6, m9, 8
pshufb m4, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1 * 2], m4
palignr m4, m3, m6, 4
palignr m5, m6, m9, 9
pshufb m4, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m4, m3, m6, 5
palignr m5, m6, m9, 10
pshufb m4, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0], m4
palignr m4, m3, m6, 6
palignr m5, m6, m9, 11
pshufb m4, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1], m4
palignr m4, m3, m6, 7
palignr m5, m6, m9, 12
pshufb m4, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1 * 2], m4
palignr m4, m3, m6, 8
palignr m5, m6, m9, 13
pshufb m4, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m4, m3, m6, 9
palignr m5, m6, m9, 14
pshufb m4, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0], m4
palignr m4, m3, m6, 10
palignr m5, m6, m9, 15
pshufb m4, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1], m4
palignr m4, m3, m6, 11
pshufb m4, m7
pshufb m5, m6, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1 * 2], m4
palignr m4, m3, m6, 12
palignr m5, m3, m6, 1
pshufb m4, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m4, m3, m6, 13
palignr m5, m3, m6, 2
pshufb m4, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0], m4
palignr m4, m3, m6, 14
palignr m5, m3, m6, 3
pshufb m4, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1], m4
palignr m4, m3, m6, 15
palignr m5, m3, m6, 4
pshufb m4, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1 * 2], m4
palignr m5, m3, m6, 5
pshufb m4, m3, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
vbroadcasti128 m9, [r2 + mmsize*2 + 17]
palignr m4, m9, m3, 1
palignr m5, m3, m6, 6
pshufb m4, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0], m4
palignr m4, m9, m3, 2
palignr m5, m3, m6, 7
pshufb m4, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1], m4
palignr m4, m9, m3, 3
palignr m5, m3, m6, 8
pshufb m4, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1 * 2], m4
palignr m4, m9, m3, 4
palignr m5, m3, m6, 9
pshufb m4, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m4, m9, m3, 5
palignr m5, m3, m6, 10
pshufb m4, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0], m4
palignr m4, m9, m3, 6
palignr m5, m3, m6, 11
pshufb m4, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1], m4
palignr m4, m9, m3, 7
palignr m5, m3, m6, 12
pshufb m4, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1 * 2], m4
palignr m4, m9, m3, 8
palignr m5, m3, m6, 13
pshufb m4, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m4, m9, m3, 9
palignr m5, m3, m6, 14
pshufb m4, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0], m4
palignr m4, m9, m3, 10
palignr m5, m3, m6, 15
pshufb m4, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1], m4
palignr m4, m9, m3, 11
pshufb m4, m7
pshufb m5, m3, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1 * 2], m4
palignr m4, m9, m3, 12
palignr m5, m9, m3, 1
pshufb m4, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m4, m9, m3, 13
palignr m5, m9, m3, 2
pshufb m4, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0], m4
palignr m4, m9, m3, 14
palignr m5, m9, m3, 3
pshufb m4, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1], m4
palignr m4, m9, m3, 15
palignr m5, m9, m3, 4
pshufb m4, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1 * 2], m4
palignr m5, m9, m3, 5
pshufb m4, m9, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r3], m4
RET
cglobal intra_pred_ang32_20, 3,5,10
lea r3, [ang_table_avx2 + 32 * 16]
lea r4, [r1 * 3]
mova m5, [pw_1024]
; rows 0 to 7
movu m0, [r2 + 0]
movu m1, [r2 + 1]
punpckhbw m2, m0, m1
punpcklbw m0, m1
movu m4, [r2 + mmsize*2]
pshufb m4, [ang32_shuf_mode20]
mova m9, m4
vpermq m9, m9, q3333
mova m7, m4
vpermq m7, m7, q1111
palignr m4, m7, 14
pshufb m4, [ang32_shuf_mode20 + mmsize*1]
vextracti128 xm6, m4, 1
palignr m3, m0, m4, 1
palignr m8, m3, m6, 1
vinserti128 m3, m3, xm2, 1
vinserti128 m8, m8, xm0, 1
vinserti128 m9, m9, xm3, 1
pmaddubsw m4, m0, [r3 - 5 * 32] ; [11]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 - 5 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
palignr m6, m0, m3, 14
palignr m7, m2, m0, 14
pmaddubsw m4, m6, [r3 + 6 * 32] ; [22]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 6 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m6, [r3 - 15 * 32] ; [1]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 15 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
palignr m6, m0, m3, 12
palignr m7, m2, m0, 12
pmaddubsw m4, m6, [r3 - 4 * 32] ; [12]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 4 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
palignr m6, m0, m3, 10
palignr m7, m2, m0, 10
pmaddubsw m4, m6, [r3 + 7 * 32] ; [23]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 7 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m6, [r3 - 14 * 32] ; [2]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 14 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
palignr m6, m0, m3, 8
palignr m7, m2, m0, 8
pmaddubsw m4, m6, [r3 - 3 * 32] ; [13]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 3 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
palignr m6, m0, m3, 6
palignr m7, m2, m0, 6
pmaddubsw m4, m6, [r3 + 8 * 32] ; [24]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 8 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
; rows 8 to 15
pmaddubsw m4, m6, [r3 - 13 * 32] ; [3]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 13 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
palignr m6, m0, m3, 4
palignr m7, m2, m0, 4
pmaddubsw m4, m6, [r3 - 2 * 32] ; [14]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 2 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
palignr m6, m0, m3, 2
palignr m7, m2, m0, 2
pmaddubsw m4, m6, [r3 + 9 * 32] ; [25]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 9 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pmaddubsw m4, m6, [r3 - 12 * 32] ; [4]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 12 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
pmaddubsw m4, m3, [r3 - 1 * 32] ; [15]
pmulhrsw m4, m5
pmaddubsw m1, m0, [r3 - 1 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
palignr m6, m3, m8, 14
palignr m7, m0, m3, 14
pmaddubsw m4, m6, [r3 + 10 * 32] ; [26]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 10 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m6, [r3 - 11 * 32] ; [5]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 11 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1 * 2], m4
palignr m6, m3, m8, 12
palignr m7, m0, m3, 12
pmaddubsw m4, m6, [r3] ; [16]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
; rows 16 to 23
palignr m6, m3, m8, 10
palignr m7, m0, m3, 10
pmaddubsw m4, m6, [r3 + 11 * 32] ; [27]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 11 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m6, [r3 - 10 * 32] ; [6]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 10 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
palignr m6, m3, m8, 8
palignr m7, m0, m3, 8
pmaddubsw m4, m6, [r3 + 1 * 32] ; [17]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 1 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
palignr m6, m3, m8, 6
palignr m7, m0, m3, 6
pmaddubsw m4, m6, [r3 + 12 * 32] ; [28]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 12 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
pmaddubsw m4, m6, [r3 - 9 * 32] ; [7]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 9 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
palignr m6, m3, m8, 4
palignr m7, m0, m3, 4
pmaddubsw m4, m6, [r3 + 2 * 32] ; [18]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 2 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
palignr m6, m3, m8, 2
palignr m7, m0, m3, 2
pmaddubsw m4, m6, [r3 + 13 * 32] ; [29]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 13 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pmaddubsw m4, m6, [r3 - 8 * 32] ; [8]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 8 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
; rows 24 to 31
pmaddubsw m4, m8, [r3 + 3 * 32] ; [19]
pmulhrsw m4, m5
pmaddubsw m1, m3, [r3 + 3 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
palignr m6, m8, m9, 14
palignr m7, m3, m8, 14
pmaddubsw m4, m6, [r3 + 14 * 32] ; [30]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 14 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m6, [r3 - 7 * 32] ; [9]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 7 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1 * 2], m4
palignr m6, m8, m9, 12
palignr m7, m3, m8, 12
pmaddubsw m4, m6, [r3 + 4 * 32] ; [20]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 4 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
palignr m6, m8, m9, 10
palignr m7, m3, m8, 10
pmaddubsw m4, m6, [r3 + 15 * 32] ; [31]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 15 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m6, [r3 - 6 * 32] ; [10]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 6 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
palignr m6, m8, m9, 8
palignr m7, m3, m8, 8
pmaddubsw m4, m6, [r3 + 5 * 32] ; [21]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 5 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pand m6, [pw_00ff]
pand m7, [pw_00ff]
packuswb m6, m7
movu [r0 + r4], m6
RET
cglobal intra_pred_ang32_17, 3,4,8
movu m0, [ang32_fact_mode17]
mova m2, [pw_1024]
mova m7, [ang32_shuf_mode17]
lea r3, [r1 * 3]
; prepare for [31, 30, 28, 27, 26, 25, 23, 22, 21, 20, 18, 17, 16, 15, 14, 12, 11, 10, 9, 7, 6, 5, 4, 2, 1, 0, -1, -2...]
movu m6, [r2]
pshufb m6, [ang32_shuf_mode17 + mmsize]
mova m1, m6
mova m3, [ang32_shuf_mode16 + mmsize*3]
vpermd m6, m3, m6
vpermq m1, m1, q3232
pslldq m1, 4
movu xm4, [r2 + mmsize*2]
pinsrb xm4, [r2], 0
vinserti128 m3, m4, xm4, 1
palignr m4, m3, m6, 2
palignr m5, m6, m1, 5
pshufb m4, m7
pshufb m5, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0], m4
palignr m4, m3, m6, 3
palignr m5, m6, m1, 6
pshufb m4, m7
pshufb m5, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1], m4
palignr m4, m3, m6, 4
palignr m5, m6, m1, 7
pshufb m4, m7
pshufb m5, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1 * 2], m4
palignr m4, m3, m6, 5
palignr m5, m6, m1, 8
pshufb m4, m7
pshufb m5, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m4, m3, m6, 6
palignr m5, m6, m1, 9
pshufb m4, m7
pshufb m5, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0], m4
palignr m4, m3, m6, 7
palignr m5, m6, m1, 10
pshufb m4, m7
pshufb m5, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1], m4
palignr m4, m3, m6, 8
palignr m5, m6, m1, 11
pshufb m4, m7
pshufb m5, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1 * 2], m4
palignr m4, m3, m6, 9
palignr m5, m6, m1, 12
pshufb m4, m7
pshufb m5, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m4, m3, m6, 10
palignr m5, m6, m1, 13
pshufb m4, m7
pshufb m5, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0], m4
palignr m4, m3, m6, 11
palignr m5, m6, m1, 14
pshufb m4, m7
pshufb m5, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1], m4
palignr m4, m3, m6, 12
palignr m5, m6, m1, 15
pshufb m4, m7
pshufb m5, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1 * 2], m4
palignr m4, m3, m6, 13
pshufb m4, m7
pshufb m5, m6, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m4, m3, m6, 14
palignr m5, m3, m6, 1
pshufb m4, m7
pshufb m5, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0], m4
palignr m4, m3, m6, 15
palignr m5, m3, m6, 2
pshufb m4, m7
pshufb m5, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1], m4
palignr m5, m3, m6, 3
pshufb m4, m3, m7
pshufb m5, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1 * 2], m4
vbroadcasti128 m1, [r2 + mmsize*2 + 16]
palignr m4, m1, m3, 1
palignr m5, m3, m6, 4
pshufb m4, m7
pshufb m5, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m4, m1, m3, 2
palignr m5, m3, m6, 5
pshufb m4, m7
pshufb m5, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0], m4
palignr m4, m1, m3, 3
palignr m5, m3, m6, 6
pshufb m4, m7
pshufb m5, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1], m4
palignr m4, m1, m3, 4
palignr m5, m3, m6, 7
pshufb m4, m7
pshufb m5, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1 * 2], m4
palignr m4, m1, m3, 5
palignr m5, m3, m6, 8
pshufb m4, m7
pshufb m5, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m4, m1, m3, 6
palignr m5, m3, m6, 9
pshufb m4, m7
pshufb m5, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0], m4
palignr m4, m1, m3, 7
palignr m5, m3, m6, 10
pshufb m4, m7
pshufb m5, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1], m4
palignr m4, m1, m3, 8
palignr m5, m3, m6, 11
pshufb m4, m7
pshufb m5, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1 * 2], m4
palignr m4, m1, m3, 9
palignr m5, m3, m6, 12
pshufb m4, m7
pshufb m5, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m4, m1, m3, 10
palignr m5, m3, m6, 13
pshufb m4, m7
pshufb m5, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0], m4
palignr m4, m1, m3, 11
palignr m5, m3, m6, 14
pshufb m4, m7
pshufb m5, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1], m4
palignr m4, m1, m3, 12
palignr m5, m3, m6, 15
pshufb m4, m7
pshufb m5, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1 * 2], m4
palignr m4, m1, m3, 13
pshufb m4, m7
pshufb m5, m3, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r3], m4
lea r0, [r0 + r1 * 4]
palignr m4, m1, m3, 14
palignr m5, m1, m3, 1
pshufb m4, m7
pshufb m5, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0], m4
palignr m4, m1, m3, 15
palignr m5, m1, m3, 2
pshufb m4, m7
pshufb m5, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1], m4
vbroadcasti128 m6, [r2 + mmsize*2 + mmsize]
palignr m5, m1, m3, 3
pshufb m4, m1, m7
pshufb m5, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r1 * 2], m4
palignr m4, m6, m1, 1
palignr m5, m1, m3, 4
pshufb m4, m7
pshufb m5, m7
pmaddubsw m4, m0
pmaddubsw m5, m0
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
vpermq m4, m4, q3120
movu [r0 + r3], m4
RET
cglobal intra_pred_ang32_19, 3,5,10
lea r3, [ang_table_avx2 + 32 * 16]
lea r4, [r1 * 3]
mova m5, [pw_1024]
; rows 0 to 7
movu m0, [r2 + 0]
movu m1, [r2 + 1]
punpckhbw m2, m0, m1
punpcklbw m0, m1
movu m4, [r2 + mmsize*2]
pshufb m4, [ang32_shuf_mode17 + mmsize*1]
mova m3, [ang32_shuf_mode19 + mmsize*1]
mova m6, [ang32_shuf_mode19 + mmsize*2]
mova m9, m4
vpermd m4, m3, m4
vpermd m9, m6, m9
pshufb m4, [ang32_shuf_mode19]
pshufb m9, [ang32_shuf_mode19]
vextracti128 xm6, m4, 1
palignr m3, m0, m4, 1
palignr m8, m3, m6, 1
palignr m7, m8, m9, 1
vinserti128 m3, m3, xm2, 1
vinserti128 m8, m8, xm0, 1
vinserti128 m9, m7, xm3, 1
pmaddubsw m4, m0, [r3 - 10 * 32] ; [6]
pmulhrsw m4, m5
pmaddubsw m1, m2, [r3 - 10 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
palignr m6, m0, m3, 14
palignr m7, m2, m0, 14
pmaddubsw m4, m6, [r3 - 4 * 32] ; [12]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 4 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
palignr m6, m0, m3, 12
palignr m7, m2, m0, 12
pmaddubsw m4, m6, [r3 + 2 * 32] ; [18]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 2 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
palignr m6, m0, m3, 10
palignr m7, m2, m0, 10
pmaddubsw m4, m6, [r3 + 8 * 32] ; [24]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 8 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
palignr m6, m0, m3, 8
palignr m7, m2, m0, 8
pmaddubsw m4, m6, [r3 + 14 * 32] ; [30]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 14 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m6, [r3 - 12 * 32] ; [4]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 12 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
palignr m6, m0, m3, 6
palignr m7, m2, m0, 6
pmaddubsw m4, m6, [r3 - 6 * 32] ; [10]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 6 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
palignr m6, m0, m3, 4
palignr m7, m2, m0, 4
pmaddubsw m4, m6, [r3] ; [16]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
; rows 8 to 15
palignr m6, m0, m3, 2
palignr m7, m2, m0, 2
pmaddubsw m4, m6, [r3 + 6 * 32] ; [22]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 6 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m3, [r3 + 12 * 32] ; [28]
pmulhrsw m4, m5
pmaddubsw m1, m0, [r3 + 12 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m3, [r3 - 14 * 32] ; [2]
pmulhrsw m4, m5
pmaddubsw m1, m0, [r3 - 14 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
palignr m6, m3, m8, 14
palignr m7, m0, m3, 14
pmaddubsw m4, m6, [r3 - 8 * 32] ; [8]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 8 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
palignr m6, m3, m8, 12
palignr m7, m0, m3, 12
pmaddubsw m4, m6, [r3 - 2 * 32] ; [14]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 2 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
palignr m6, m3, m8, 10
palignr m7, m0, m3, 10
pmaddubsw m4, m6, [r3 + 4 * 32] ; [20]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 4 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
palignr m6, m3, m8, 8
palignr m7, m0, m3, 8
pmaddubsw m4, m6, [r3 + 10 * 32] ; [26]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 10 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1 * 2], m4
pand m6, [pw_00ff]
pand m7, [pw_00ff]
packuswb m6, m7
movu [r0 + r4], m6
lea r0, [r0 + r1 * 4]
; rows 16 to 23
palignr m6, m3, m8, 6
palignr m7, m0, m3, 6
pmaddubsw m4, m6, [r3 - 10 * 32] ; [6]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 10 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
palignr m6, m3, m8, 4
palignr m7, m0, m3, 4
pmaddubsw m4, m6, [r3 - 4 * 32] ; [12]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 4 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
palignr m6, m3, m8, 2
palignr m7, m0, m3, 2
pmaddubsw m4, m6, [r3 + 2 * 32] ; [18]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 2 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
pmaddubsw m4, m8, [r3 + 8 * 32] ; [24]
pmulhrsw m4, m5
pmaddubsw m1, m3, [r3 + 8 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
palignr m6, m8, m9, 14
palignr m7, m3, m8, 14
pmaddubsw m4, m6, [r3 + 14 * 32] ; [30]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 14 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m6, [r3 - 12 * 32] ; [4]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 12 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
palignr m6, m8, m9, 12
palignr m7, m3, m8, 12
pmaddubsw m4, m6, [r3 - 6 * 32] ; [10]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 6 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
palignr m6, m8, m9, 10
palignr m7, m3, m8, 10
pmaddubsw m4, m6, [r3] ; [16]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
; rows 24 to 31
palignr m6, m8, m9, 8
palignr m7, m3, m8, 8
pmaddubsw m4, m6, [r3 + 6 * 32] ; [22]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 6 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
palignr m6, m8, m9, 6
palignr m7, m3, m8, 6
pmaddubsw m4, m6, [r3 + 12 * 32] ; [28]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 12 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
pmaddubsw m4, m6, [r3 - 14 * 32] ; [2]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 14 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1*2], m4
palignr m6, m8, m9, 4
palignr m7, m3, m8, 4
pmaddubsw m4, m6, [r3 - 8 * 32] ; [8]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 8 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r4], m4
lea r0, [r0 + r1 * 4]
vpbroadcastb m0, [r2 + mmsize*2 + 31]
palignr m1, m9, m0, 1
vinserti128 m0, m1, xm8, 1
palignr m6, m8, m9, 2
palignr m7, m3, m8, 2
pmaddubsw m4, m6, [r3 - 2 * 32] ; [14]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 - 2 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0], m4
pmaddubsw m4, m9, [r3 + 4 * 32] ; [20]
pmulhrsw m4, m5
pmaddubsw m1, m8, [r3 + 4 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1], m4
palignr m6, m9, m0, 14
palignr m7, m8, m9, 14
pmaddubsw m4, m6, [r3 + 10 * 32] ; [26]
pmulhrsw m4, m5
pmaddubsw m1, m7, [r3 + 10 * 32]
pmulhrsw m1, m5
packuswb m4, m1
movu [r0 + r1 * 2], m4
pand m6, [pw_00ff]
pand m7, [pw_00ff]
packuswb m6, m7
movu [r0 + r4], m6
RET
%endif ; ARCH_X86_64
;-----------------------------------------------------------------------------------------
; end of intra_pred_ang32 angular modes avx2 asm
;-----------------------------------------------------------------------------------------
;-----------------------------------------------------------------------------------------
; void intraPredAng8(pixel* dst, intptr_t dstStride, pixel* src, int dirMode, int bFilter)
;-----------------------------------------------------------------------------------------
INIT_YMM avx2
%macro ang8_store8x8 0
lea r3, [3 * r1]
vextracti128 xm2, m1, 1
vextracti128 xm5, m4, 1
movq [r0], xm1
movq [r0 + r1], xm2
movhps [r0 + 2 * r1], xm1
movhps [r0 + r3], xm2
lea r0, [r0 + 4 * r1]
movq [r0], xm4
movq [r0 + r1], xm5
movhps [r0 + 2 * r1], xm4
movhps [r0 + r3], xm5
%endmacro
cglobal intra_pred_ang8_3, 3,4,6
vbroadcasti128 m0, [r2 + 17]
mova m5, [ang8_shuf_mode3]
mova m3, [pb_2]
pshufb m1, m0, m5
paddb m5, m3
pshufb m2, m0, m5
paddb m5, m3
pshufb m4, m0, m5
paddb m5, m3
pshufb m0, m5
vbroadcasti128 m5, [ang8_fact_mode3]
mova m3, [pw_1024]
pmaddubsw m1, m5
pmaddubsw m2, m5
pmaddubsw m4, m5
pmaddubsw m0, m5
pmulhrsw m1, m3
pmulhrsw m2, m3
pmulhrsw m4, m3
pmulhrsw m0, m3
packuswb m1, m2
packuswb m4, m0
ang8_store8x8
RET
INIT_YMM avx2
cglobal intra_pred_ang8_33, 3,4,5
mova m3, [pw_1024]
vbroadcasti128 m0, [r2 + 1]
pshufb m1, m0, [c_ang8_src1_9_2_10]
pshufb m2, m0, [c_ang8_src3_11_4_12]
pshufb m4, m0, [c_ang8_src5_13_5_13]
pshufb m0, [c_ang8_src6_14_7_15]
pmaddubsw m1, [c_ang8_26_20]
pmulhrsw m1, m3
pmaddubsw m2, [c_ang8_14_8]
pmulhrsw m2, m3
pmaddubsw m4, [c_ang8_2_28]
pmulhrsw m4, m3
pmaddubsw m0, [c_ang8_22_16]
pmulhrsw m0, m3
packuswb m1, m2
packuswb m4, m0
lea r3, [3 * r1]
movq [r0], xm1
vextracti128 xm2, m1, 1
movq [r0 + r1], xm2
movhps [r0 + 2 * r1], xm1
movhps [r0 + r3], xm2
lea r0, [r0 + 4 * r1]
movq [r0], xm4
vextracti128 xm2, m4, 1
movq [r0 + r1], xm2
movhps [r0 + 2 * r1], xm4
movhps [r0 + r3], xm2
RET
INIT_YMM avx2
cglobal intra_pred_ang8_4, 3,4,6
vbroadcasti128 m0, [r2 + 17]
mova m5, [ang8_shuf_mode4]
mova m3, [pb_2]
pshufb m1, m0, m5
paddb m5, m3
pshufb m2, m0, m5
paddb m5, m3
pshufb m4, m0, m5
paddb m5, m3
pshufb m0, m5
vbroadcasti128 m5, [ang8_fact_mode4]
mova m3, [pw_1024]
pmaddubsw m1, m5
pmaddubsw m2, m5
pmaddubsw m4, m5
pmaddubsw m0, m5
pmulhrsw m1, m3
pmulhrsw m2, m3
pmulhrsw m4, m3
pmulhrsw m0, m3
packuswb m1, m2
packuswb m4, m0
ang8_store8x8
RET
INIT_YMM avx2
cglobal intra_pred_ang8_32, 3,4,5
mova m3, [pw_1024]
vbroadcasti128 m0, [r2 + 1]
pshufb m1, m0, [c_ang8_src1_9_2_10]
pshufb m2, m0, [c_ang8_src2_10_3_11]
pshufb m4, m0, [c_ang8_src4_12_4_12]
pshufb m0, [c_ang8_src5_13_6_14]
pmaddubsw m1, [c_ang8_21_10]
pmulhrsw m1, m3
pmaddubsw m2, [c_ang8_31_20]
pmulhrsw m2, m3
pmaddubsw m4, [c_ang8_9_30]
pmulhrsw m4, m3
pmaddubsw m0, [c_ang8_19_8]
pmulhrsw m0, m3
packuswb m1, m2
packuswb m4, m0
lea r3, [3 * r1]
movq [r0], xm1
vextracti128 xm2, m1, 1
movq [r0 + r1], xm2
movhps [r0 + 2 * r1], xm1
movhps [r0 + r3], xm2
lea r0, [r0 + 4 * r1]
movq [r0], xm4
vextracti128 xm2, m4, 1
movq [r0 + r1], xm2
movhps [r0 + 2 * r1], xm4
movhps [r0 + r3], xm2
RET
INIT_YMM avx2
cglobal intra_pred_ang8_5, 3, 4, 6
vbroadcasti128 m0, [r2 + 17]
mova m5, [ang8_shuf_mode5]
mova m3, [pb_2]
pshufb m1, m0, m5
paddb m5, m3
pshufb m2, m0, m5
paddb m5, m3
pshufb m4, m0, m5
paddb m5, m3
pshufb m0, m5
vbroadcasti128 m5, [ang8_fact_mode5]
mova m3, [pw_1024]
pmaddubsw m1, m5
pmaddubsw m2, m5
pmaddubsw m4, m5
pmaddubsw m0, m5
pmulhrsw m1, m3
pmulhrsw m2, m3
pmulhrsw m4, m3
pmulhrsw m0, m3
packuswb m1, m2
packuswb m4, m0
ang8_store8x8
RET
INIT_YMM avx2
cglobal intra_pred_ang8_31, 3, 4, 5
mova m3, [pw_1024]
vbroadcasti128 m0, [r2 + 1]
pshufb m1, m0, [c_ang8_src1_9_2_10]
pshufb m2, m0, [c_ang8_src2_10_3_11]
pshufb m4, m0, [c_ang8_src3_11_4_12]
pshufb m0, [c_ang8_src4_12_5_13]
pmaddubsw m1, [c_ang8_17_2]
pmulhrsw m1, m3
pmaddubsw m2, [c_ang8_19_4]
pmulhrsw m2, m3
pmaddubsw m4, [c_ang8_21_6]
pmulhrsw m4, m3
pmaddubsw m0, [c_ang8_23_8]
pmulhrsw m0, m3
packuswb m1, m2
packuswb m4, m0
lea r3, [3 * r1]
movq [r0], xm1
vextracti128 xm2, m1, 1
movq [r0 + r1], xm2
movhps [r0 + 2 * r1], xm1
movhps [r0 + r3], xm2
lea r0, [r0 + 4 * r1]
movq [r0], xm4
vextracti128 xm2, m4, 1
movq [r0 + r1], xm2
movhps [r0 + 2 * r1], xm4
movhps [r0 + r3], xm2
RET
INIT_YMM avx2
cglobal intra_pred_ang8_6, 3, 4, 6
vbroadcasti128 m0, [r2 + 17]
mova m5, [ang8_shuf_mode6]
mova m3, [pb_2]
pshufb m1, m0, m5
paddb m5, m3
pshufb m2, m0, m5
paddb m5, m3
pshufb m4, m0, m5
paddb m5, m3
pshufb m0, m5
vbroadcasti128 m5, [ang8_fact_mode6]
mova m3, [pw_1024]
pmaddubsw m1, m5
pmaddubsw m2, m5
pmaddubsw m4, m5
pmaddubsw m0, m5
pmulhrsw m1, m3
pmulhrsw m2, m3
pmulhrsw m4, m3
pmulhrsw m0, m3
packuswb m1, m2
packuswb m4, m0
ang8_store8x8
RET
INIT_YMM avx2
cglobal intra_pred_ang8_30, 3, 4, 5
mova m3, [pw_1024]
vbroadcasti128 m0, [r2 + 1]
pshufb m1, m0, [intra_pred_shuff_0_8]
pshufb m2, m0, [c_ang8_src2_10_2_10]
pshufb m4, m0, [c_ang8_src3_11_3_11]
pshufb m0, [c_ang8_src3_11_4_12]
pmaddubsw m1, [c_ang8_13_26]
pmulhrsw m1, m3
pmaddubsw m2, [c_ang8_7_20]
pmulhrsw m2, m3
pmaddubsw m4, [c_ang8_1_14]
pmulhrsw m4, m3
pmaddubsw m0, [c_ang8_27_8]
pmulhrsw m0, m3
packuswb m1, m2
packuswb m4, m0
lea r3, [3 * r1]
movq [r0], xm1
vextracti128 xm2, m1, 1
movq [r0 + r1], xm2
movhps [r0 + 2 * r1], xm1
movhps [r0 + r3], xm2
lea r0, [r0 + 4 * r1]
movq [r0], xm4
vextracti128 xm2, m4, 1
movq [r0 + r1], xm2
movhps [r0 + 2 * r1], xm4
movhps [r0 + r3], xm2
RET
INIT_YMM avx2
cglobal intra_pred_ang8_9, 3, 5, 6
vbroadcasti128 m0, [r2 + 17]
mova m5, [ang8_shuf_mode9]
mova m3, [pb_2]
pshufb m1, m0, m5
paddb m5, m3
pshufb m2, m0, m5
paddb m5, m3
pshufb m4, m0, m5
paddb m5, m3
pshufb m0, m5
vbroadcasti128 m5, [ang8_fact_mode9]
mova m3, [pw_1024]
pmaddubsw m1, m5
pmaddubsw m2, m5
pmaddubsw m4, m5
pmaddubsw m0, m5
pmulhrsw m1, m3
pmulhrsw m2, m3
pmulhrsw m4, m3
pmulhrsw m0, m3
packuswb m1, m2
packuswb m4, m0
ang8_store8x8
RET
INIT_YMM avx2
cglobal intra_pred_ang8_27, 3, 5, 5
mova m3, [pw_1024]
vbroadcasti128 m0, [r2 + 1]
pshufb m0, [intra_pred_shuff_0_8]
lea r4, [c_ang8_mode_27]
pmaddubsw m1, m0, [r4]
pmulhrsw m1, m3
pmaddubsw m2, m0, [r4 + mmsize]
pmulhrsw m2, m3
pmaddubsw m4, m0, [r4 + 2 * mmsize]
pmulhrsw m4, m3
pmaddubsw m0, [r4 + 3 * mmsize]
pmulhrsw m0, m3
packuswb m1, m2
packuswb m4, m0
lea r3, [3 * r1]
movq [r0], xm1
vextracti128 xm2, m1, 1
movq [r0 + r1], xm2
movhps [r0 + 2 * r1], xm1
movhps [r0 + r3], xm2
lea r0, [r0 + 4 * r1]
movq [r0], xm4
vextracti128 xm2, m4, 1
movq [r0 + r1], xm2
movhps [r0 + 2 * r1], xm4
movhps [r0 + r3], xm2
RET
INIT_YMM avx2
cglobal intra_pred_ang8_25, 3, 5, 5
mova m3, [pw_1024]
vbroadcasti128 m0, [r2]
pshufb m0, [intra_pred_shuff_0_8]
lea r4, [c_ang8_mode_25]
pmaddubsw m1, m0, [r4]
pmulhrsw m1, m3
pmaddubsw m2, m0, [r4 + mmsize]
pmulhrsw m2, m3
pmaddubsw m4, m0, [r4 + 2 * mmsize]
pmulhrsw m4, m3
pmaddubsw m0, [r4 + 3 * mmsize]
pmulhrsw m0, m3
packuswb m1, m2
packuswb m4, m0
lea r3, [3 * r1]
movq [r0], xm1
vextracti128 xm2, m1, 1
movq [r0 + r1], xm2
movhps [r0 + 2 * r1], xm1
movhps [r0 + r3], xm2
lea r0, [r0 + 4 * r1]
movq [r0], xm4
vextracti128 xm2, m4, 1
movq [r0 + r1], xm2
movhps [r0 + 2 * r1], xm4
movhps [r0 + r3], xm2
RET
INIT_YMM avx2
cglobal intra_pred_ang8_7, 3, 4, 6
vbroadcasti128 m0, [r2 + 17]
mova m5, [ang8_shuf_mode7]
mova m3, [pb_2]
pshufb m1, m0, m5
paddb m5, m3
pshufb m2, m0, m5
paddb m5, m3
pshufb m4, m0, m5
paddb m5, m3
pshufb m0, m5
vbroadcasti128 m5, [ang8_fact_mode7]
mova m3, [pw_1024]
pmaddubsw m1, m5
pmaddubsw m2, m5
pmaddubsw m4, m5
pmaddubsw m0, m5
pmulhrsw m1, m3
pmulhrsw m2, m3
pmulhrsw m4, m3
pmulhrsw m0, m3
packuswb m1, m2
packuswb m4, m0
ang8_store8x8
RET
INIT_YMM avx2
cglobal intra_pred_ang8_29, 3, 4, 5
mova m3, [pw_1024]
vbroadcasti128 m0, [r2 + 1]
pshufb m1, m0, [intra_pred_shuff_0_8]
pshufb m2, m0, [c_ang8_src1_9_2_10]
pshufb m4, m0, [c_ang8_src2_10_2_10]
pshufb m0, [c_ang8_src2_10_3_11]
pmaddubsw m1, [c_ang8_9_18]
pmulhrsw m1, m3
pmaddubsw m2, [c_ang8_27_4]
pmulhrsw m2, m3
pmaddubsw m4, [c_ang8_13_22]
pmulhrsw m4, m3
pmaddubsw m0, [c_ang8_31_8]
pmulhrsw m0, m3
packuswb m1, m2
packuswb m4, m0
lea r3, [3 * r1]
movq [r0], xm1
vextracti128 xm2, m1, 1
movq [r0 + r1], xm2
movhps [r0 + 2 * r1], xm1
movhps [r0 + r3], xm2
lea r0, [r0 + 4 * r1]
movq [r0], xm4
vextracti128 xm2, m4, 1
movq [r0 + r1], xm2
movhps [r0 + 2 * r1], xm4
movhps [r0 + r3], xm2
RET
INIT_YMM avx2
cglobal intra_pred_ang8_8, 3, 4, 6
vbroadcasti128 m0, [r2 + 17]
mova m5, [ang8_shuf_mode8]
mova m3, [pb_2]
pshufb m1, m0, m5
paddb m5, m3
pshufb m2, m0, m5
paddb m5, m3
pshufb m4, m0, m5
paddb m5, m3
pshufb m0, m5
vbroadcasti128 m5, [ang8_fact_mode8]
mova m3, [pw_1024]
pmaddubsw m1, m5
pmaddubsw m2, m5
pmaddubsw m4, m5
pmaddubsw m0, m5
pmulhrsw m1, m3
pmulhrsw m2, m3
pmulhrsw m4, m3
pmulhrsw m0, m3
packuswb m1, m2
packuswb m4, m0
ang8_store8x8
RET
INIT_YMM avx2
cglobal intra_pred_ang8_28, 3, 4, 6
mova m3, [pw_1024]
vbroadcasti128 m0, [r2 + 1]
mova m5, [intra_pred_shuff_0_8]
pshufb m1, m0, m5
pshufb m2, m0, m5
pshufb m4, m0, m5
pshufb m0, [c_ang8_src2_10_2_10]
pmaddubsw m1, [c_ang8_5_10]
pmulhrsw m1, m3
pmaddubsw m2, [c_ang8_15_20]
pmulhrsw m2, m3
pmaddubsw m4, [c_ang8_25_30]
pmulhrsw m4, m3
pmaddubsw m0, [c_ang8_3_8]
pmulhrsw m0, m3
packuswb m1, m2
packuswb m4, m0
lea r3, [3 * r1]
movq [r0], xm1
vextracti128 xm2, m1, 1
movq [r0 + r1], xm2
movhps [r0 + 2 * r1], xm1
movhps [r0 + r3], xm2
lea r0, [r0 + 4 * r1]
movq [r0], xm4
vextracti128 xm2, m4, 1
movq [r0 + r1], xm2
movhps [r0 + 2 * r1], xm4
movhps [r0 + r3], xm2
RET
INIT_YMM avx2
cglobal intra_pred_ang8_11, 3, 5, 6
mova m3, [pw_1024]
movu xm1, [r2 + 16]
pinsrb xm1, [r2], 0
vinserti128 m0, m1, xm1, 1
mova m5, [ang8_shuf_mode9]
mova m3, [pb_2]
pshufb m1, m0, m5
paddb m5, m3
pshufb m2, m0, m5
paddb m5, m3
pshufb m4, m0, m5
paddb m5, m3
pshufb m0, m5
vbroadcasti128 m5, [ang8_fact_mode11]
mova m3, [pw_1024]
pmaddubsw m1, m5
pmaddubsw m2, m5
pmaddubsw m4, m5
pmaddubsw m0, m5
pmulhrsw m1, m3
pmulhrsw m2, m3
pmulhrsw m4, m3
pmulhrsw m0, m3
packuswb m1, m2
packuswb m4, m0
ang8_store8x8
RET
INIT_YMM avx2
cglobal intra_pred_ang8_15, 3, 6, 6
vbroadcasti128 m1, [r2 + 17]
vbroadcasti128 m2, [r2]
mova m3, [ang8_shuf_mode15 + mmsize]
pshufb m2, m3
palignr m1, m2, 11
mova m5, [ang8_shuf_mode15]
mova m3, [pb_2]
pshufb m0, m1, m5
psubb m5, m3
pshufb m4, m1, m5
psubb m5, m3
pshufb m2, m1, m5
psubb m5, m3
pshufb m1, m5
vbroadcasti128 m5, [ang8_fact_mode15]
mova m3, [pw_1024]
pmaddubsw m1, m5
pmaddubsw m2, m5
pmaddubsw m4, m5
pmaddubsw m0, m5
pmulhrsw m1, m3
pmulhrsw m2, m3
pmulhrsw m4, m3
pmulhrsw m0, m3
packuswb m1, m2
packuswb m4, m0
ang8_store8x8
RET
INIT_YMM avx2
cglobal intra_pred_ang8_16, 3,4,6
vbroadcasti128 m1, [r2 + 17]
vbroadcasti128 m2, [r2]
mova m3, [ang8_shuf_mode16 + mmsize]
pshufb m2, m3
palignr m1, m2, 10
mova m5, [ang8_shuf_mode16]
mova m3, [pb_2]
pshufb m0, m1, m5
psubb m5, m3
pshufb m4, m1, m5
psubb m5, m3
pshufb m2, m1, m5
psubb m5, m3
pshufb m1, m5
vbroadcasti128 m5, [ang8_fact_mode16]
mova m3, [pw_1024]
pmaddubsw m1, m5
pmaddubsw m2, m5
pmaddubsw m4, m5
pmaddubsw m0, m5
pmulhrsw m1, m3
pmulhrsw m2, m3
pmulhrsw m4, m3
pmulhrsw m0, m3
packuswb m1, m2
packuswb m4, m0
ang8_store8x8
RET
INIT_YMM avx2
cglobal intra_pred_ang8_17, 3,4,6
vbroadcasti128 m1, [r2 + 17]
vbroadcasti128 m2, [r2]
mova m3, [ang8_shuf_mode17 + mmsize]
pshufb m2, m3
palignr m1, m2, 9
mova m5, [ang8_shuf_mode17]
mova m3, [pb_2]
pshufb m0, m1, m5
psubb m5, m3
pshufb m4, m1, m5
psubb m5, m3
pshufb m2, m1, m5
psubb m5, m3
pshufb m1, m5
vbroadcasti128 m5, [ang8_fact_mode17]
mova m3, [pw_1024]
pmaddubsw m1, m5
pmaddubsw m2, m5
pmaddubsw m4, m5
pmaddubsw m0, m5
pmulhrsw m1, m3
pmulhrsw m2, m3
pmulhrsw m4, m3
pmulhrsw m0, m3
packuswb m1, m2
packuswb m4, m0
ang8_store8x8
RET
%if 1
INIT_YMM avx2
cglobal intra_pred_ang8_20, 3,5,6
lea r0, [r0 + r1 * 8]
sub r0, r1
neg r1
lea r3, [angHor8_tab_20]
lea r4, [r1 * 3]
movu m5, [intra_pred_shuff_0_8 + 16]
; prepare reference pixel
movq xm1, [r2 + 1] ; m3 = [ 1 2 3 4 5 6 7 8 x x x x x x x x]
movhps xm1, [r2 + 16 + 2] ; m3 = [ 1 2 3 4 5 6 7 8 -2 -3 x -5 -6 x -8 x]
palignr xm1, xm1, [r2 - 15], 15 ; m3 = [ 0 1 2 3 4 5 6 7 8 -2 -3 x -5 -6 x -8]
pshufb xm1, [c_ang8_mode_20]
vinserti128 m1, m1, xm1, 1
; process 4 rows
pshufb m3, m1, m5
psrldq m1, 2
pmaddubsw m3, [r3 + 0 * 16]
pmulhrsw m3, [pw_1024]
pshufb m4, m1, [intra_pred_shuff_0_8]
psrldq m1, 1
pmaddubsw m4, [r3 + 2 * 16]
pmulhrsw m4, [pw_1024]
packuswb m3, m4
vextracti128 xm4, m3, 1
movq [r0], xm3
movq [r0 + r1], xm4
movhps [r0 + r1 * 2], xm3
movhps [r0 + r4], xm4
; process 4 rows
lea r0, [r0 + r1 * 4]
pshufb m3, m1, m5
psrldq m1, 1
pmaddubsw m3, [r3 + 4 * 16]
pmulhrsw m3, [pw_1024]
pshufb m4, m1, m5
pmaddubsw m4, [r3 + 6 * 16]
pmulhrsw m4, [pw_1024]
packuswb m3, m4
vextracti128 xm4, m3, 1
movq [r0], xm3
movq [r0 + r1], xm4
movhps [r0 + r1 * 2], xm3
movhps [r0 + r4], xm4
RET
%else
INIT_YMM avx2
cglobal intra_pred_ang8_20, 3, 6, 6
mova m3, [pw_1024]
movu xm5, [r2]
lea r5, [intra_pred_shuff_0_8]
mova xm0, xm5
pslldq xm5, 1
pinsrb xm5, [r2 + 2 + 16], 0
vinserti128 m0, m0, xm5, 1
pshufb m0, [r5]
lea r4, [c_ang8_mode_20]
pmaddubsw m1, m0, [r4]
pmulhrsw m1, m3
mova xm0, xm5
pslldq xm5, 1
pinsrb xm5, [r2 + 3 + 16], 0
vinserti128 m0, m0, xm5, 1
pshufb m0, [r5]
pmaddubsw m2, m0, [r4 + mmsize]
pmulhrsw m2, m3
pslldq xm5, 1
pinsrb xm5, [r2 + 5 + 16], 0
vinserti128 m0, m5, xm5, 1
pshufb m0, [r5]
pmaddubsw m4, m0, [r4 + 2 * mmsize]
pmulhrsw m4, m3
pslldq xm5, 1
pinsrb xm5, [r2 + 6 + 16], 0
mova xm0, xm5
pslldq xm5, 1
pinsrb xm5, [r2 + 8 + 16], 0
vinserti128 m0, m0, xm5, 1
pshufb m0, [r5]
pmaddubsw m0, [r4 + 3 * mmsize]
pmulhrsw m0, m3
packuswb m1, m2
packuswb m4, m0
lea r3, [3 * r1]
movq [r0], xm1
vextracti128 xm2, m1, 1
movq [r0 + r1], xm2
movhps [r0 + 2 * r1], xm1
movhps [r0 + r3], xm2
lea r0, [r0 + 4 * r1]
movq [r0], xm4
vextracti128 xm2, m4, 1
movq [r0 + r1], xm2
movhps [r0 + 2 * r1], xm4
movhps [r0 + r3], xm2
RET
%endif
INIT_YMM avx2
cglobal intra_pred_ang8_21, 3, 6, 6
mova m3, [pw_1024]
movu xm5, [r2]
lea r5, [intra_pred_shuff_0_8]
mova xm0, xm5
pslldq xm5, 1
pinsrb xm5, [r2 + 2 + 16], 0
vinserti128 m0, m0, xm5, 1
pshufb m0, [r5]
lea r4, [c_ang8_mode_15]
pmaddubsw m1, m0, [r4]
pmulhrsw m1, m3
mova xm0, xm5
pslldq xm5, 1
pinsrb xm5, [r2 + 4 + 16], 0
vinserti128 m0, m0, xm5, 1
pshufb m0, [r5]
pmaddubsw m2, m0, [r4 + mmsize]
pmulhrsw m2, m3
mova xm0, xm5
pslldq xm5, 1
pinsrb xm5, [r2 + 6 + 16], 0
vinserti128 m0, m0, xm5, 1
pshufb m0, [r5]
pmaddubsw m4, m0, [r4 + 2 * mmsize]
pmulhrsw m4, m3
mova xm0, xm5
pslldq xm5, 1
pinsrb xm5, [r2 + 8 + 16], 0
vinserti128 m0, m0, xm5, 1
pshufb m0, [r5]
pmaddubsw m0, [r4 + 3 * mmsize]
pmulhrsw m0, m3
packuswb m1, m2
packuswb m4, m0
lea r3, [3 * r1]
movq [r0], xm1
vextracti128 xm2, m1, 1
movq [r0 + r1], xm2
movhps [r0 + 2 * r1], xm1
movhps [r0 + r3], xm2
lea r0, [r0 + 4 * r1]
movq [r0], xm4
vextracti128 xm2, m4, 1
movq [r0 + r1], xm2
movhps [r0 + 2 * r1], xm4
movhps [r0 + r3], xm2
RET
INIT_YMM avx2
cglobal intra_pred_ang8_22, 3, 6, 6
mova m3, [pw_1024]
movu xm5, [r2]
lea r5, [intra_pred_shuff_0_8]
vinserti128 m0, m5, xm5, 1
pshufb m0, [r5]
lea r4, [c_ang8_mode_14]
pmaddubsw m1, m0, [r4]
pmulhrsw m1, m3
pslldq xm5, 1
pinsrb xm5, [r2 + 2 + 16], 0
vinserti128 m0, m5, xm5, 1
pshufb m0, [r5]
pmaddubsw m2, m0, [r4 + mmsize]
pmulhrsw m2, m3
pslldq xm5, 1
pinsrb xm5, [r2 + 5 + 16], 0
vinserti128 m0, m5, xm5, 1
pshufb m0, [r5]
pmaddubsw m4, m0, [r4 + 2 * mmsize]
pmulhrsw m4, m3
pslldq xm5, 1
pinsrb xm5, [r2 + 7 + 16], 0
pshufb xm5, [r5]
vinserti128 m0, m0, xm5, 1
pmaddubsw m0, [r4 + 3 * mmsize]
pmulhrsw m0, m3
packuswb m1, m2
packuswb m4, m0
lea r3, [3 * r1]
movq [r0], xm1
vextracti128 xm2, m1, 1
movq [r0 + r1], xm2
movhps [r0 + 2 * r1], xm1
movhps [r0 + r3], xm2
lea r0, [r0 + 4 * r1]
movq [r0], xm4
vextracti128 xm2, m4, 1
movq [r0 + r1], xm2
movhps [r0 + 2 * r1], xm4
movhps [r0 + r3], xm2
RET
INIT_YMM avx2
cglobal intra_pred_ang8_14, 3, 6, 6
movu xm1, [r2 + 13]
vinserti128 m1, m1, xm1, 1
pinsrb xm1, [r2 + 0], 3
pinsrb xm1, [r2 + 2], 2
pinsrb xm1, [r2 + 5], 1
pinsrb xm1, [r2 + 7], 0
vinserti128 m1, m1, xm1, 1
mova m5, [ang8_shuf_mode14]
mova m3, [pb_2]
pshufb m0, m1, m5
psubb m5, m3
pshufb m4, m1, m5
psubb m5, m3
pshufb m2, m1, m5
psubb m5, m3
pshufb m1, m5
vbroadcasti128 m5, [ang8_fact_mode14]
mova m3, [pw_1024]
pmaddubsw m1, m5
pmaddubsw m2, m5
pmaddubsw m4, m5
pmaddubsw m0, m5
pmulhrsw m1, m3
pmulhrsw m2, m3
pmulhrsw m4, m3
pmulhrsw m0, m3
packuswb m1, m2
packuswb m4, m0
ang8_store8x8
RET
INIT_YMM avx2
cglobal intra_pred_ang8_13, 3, 6, 6
movu xm1, [r2 + 14]
pinsrb xm1, [r2 + 0], 2
pinsrb xm1, [r2 + 4], 1
pinsrb xm1, [r2 + 7], 0
vinserti128 m1, m1, xm1, 1
mova m5, [ang8_shuf_mode13]
mova m3, [pb_2]
pshufb m0, m1, m5
psubb m5, m3
pshufb m4, m1, m5
psubb m5, m3
pshufb m2, m1, m5
psubb m5, m3
pshufb m1, m5
vbroadcasti128 m5, [ang8_fact_mode13]
mova m3, [pw_1024]
pmaddubsw m1, m5
pmaddubsw m2, m5
pmaddubsw m4, m5
pmaddubsw m0, m5
pmulhrsw m1, m3
pmulhrsw m2, m3
pmulhrsw m4, m3
pmulhrsw m0, m3
packuswb m1, m2
packuswb m4, m0
ang8_store8x8
RET
INIT_YMM avx2
cglobal intra_pred_ang8_23, 3, 6, 6
mova m3, [pw_1024]
movu xm5, [r2]
lea r5, [intra_pred_shuff_0_8]
vinserti128 m0, m5, xm5, 1
pshufb m0, [r5]
lea r4, [c_ang8_mode_13]
pmaddubsw m1, m0, [r4]
pmulhrsw m1, m3
pslldq xm5, 1
pinsrb xm5, [r2 + 4 + 16], 0
pshufb xm4, xm5, [r5]
vinserti128 m0, m0, xm4, 1
pmaddubsw m2, m0, [r4 + mmsize]
pmulhrsw m2, m3
vinserti128 m0, m0, xm4, 0
pmaddubsw m4, m0, [r4 + 2 * mmsize]
pmulhrsw m4, m3
pslldq xm5, 1
pinsrb xm5, [r2 + 7 + 16], 0
pshufb xm5, [r5]
vinserti128 m0, m0, xm5, 1
pmaddubsw m0, [r4 + 3 * mmsize]
pmulhrsw m0, m3
packuswb m1, m2
packuswb m4, m0
lea r3, [3 * r1]
movq [r0], xm1
vextracti128 xm2, m1, 1
movq [r0 + r1], xm2
movhps [r0 + 2 * r1], xm1
movhps [r0 + r3], xm2
lea r0, [r0 + 4 * r1]
movq [r0], xm4
vextracti128 xm2, m4, 1
movq [r0 + r1], xm2
movhps [r0 + 2 * r1], xm4
movhps [r0 + r3], xm2
RET
INIT_YMM avx2
cglobal intra_pred_ang8_12, 3, 5, 6
movu xm1, [r2 + 15]
pinsrb xm1, [r2 + 0], 1
pinsrb xm1, [r2 + 6], 0
vinserti128 m1, m1, xm1, 1
mova m5, [ang8_shuf_mode12]
mova m3, [pb_2]
pshufb m0, m1, m5
psubb m5, m3
pshufb m4, m1, m5
psubb m5, m3
pshufb m2, m1, m5
psubb m5, m3
pshufb m1, m5
vbroadcasti128 m5, [ang8_fact_mode12]
mova m3, [pw_1024]
pmaddubsw m1, m5
pmaddubsw m2, m5
pmaddubsw m4, m5
pmaddubsw m0, m5
pmulhrsw m1, m3
pmulhrsw m2, m3
pmulhrsw m4, m3
pmulhrsw m0, m3
packuswb m1, m2
packuswb m4, m0
ang8_store8x8
RET
INIT_YMM avx2
cglobal intra_pred_ang8_24, 3, 5, 5
mova m3, [pw_1024]
vbroadcasti128 m0, [r2]
pshufb m0, [intra_pred_shuff_0_8]
lea r4, [c_ang8_mode_24]
pmaddubsw m1, m0, [r4]
pmulhrsw m1, m3
pmaddubsw m2, m0, [r4 + mmsize]
pmulhrsw m2, m3
pmaddubsw m4, m0, [r4 + 2 * mmsize]
pmulhrsw m4, m3
pslldq xm0, 2
pinsrb xm0, [r2 + 16 + 6], 0
pinsrb xm0, [r2 + 0], 1
vinserti128 m0, m0, xm0, 1
pmaddubsw m0, [r4 + 3 * mmsize]
pmulhrsw m0, m3
packuswb m1, m2
packuswb m4, m0
lea r3, [3 * r1]
movq [r0], xm1
vextracti128 xm2, m1, 1
movq [r0 + r1], xm2
movhps [r0 + 2 * r1], xm1
movhps [r0 + r3], xm2
lea r0, [r0 + 4 * r1]
movq [r0], xm4
vextracti128 xm2, m4, 1
movq [r0 + r1], xm2
movhps [r0 + 2 * r1], xm4
movhps [r0 + r3], xm2
RET
%macro INTRA_PRED_ANG16_MC0 3
pmaddubsw m3, m1, [r4 + %3 * mmsize]
pmulhrsw m3, m0
pmaddubsw m4, m2, [r4 + %3 * mmsize]
pmulhrsw m4, m0
packuswb m3, m4
movu [%1], xm3
vextracti128 xm4, m3, 1
movu [%2], xm4
%endmacro
%macro INTRA_PRED_ANG16_MC1 1
INTRA_PRED_ANG16_MC0 r0, r0 + r1, %1
INTRA_PRED_ANG16_MC0 r0 + 2 * r1, r0 + r3, (%1 + 1)
%endmacro
%macro INTRA_PRED_ANG16_MC2 1
vbroadcasti128 m1, [r2 + %1]
pshufb m1, m5
vbroadcasti128 m2, [r2 + (%1 + 8)]
pshufb m2, m5
%endmacro
%macro INTRA_PRED_ANG16_MC3 2
vperm2i128 m1, m1, m2, 00100000b
pmaddubsw m3, m1, [r4 + (%2 * mmsize)]
pmulhrsw m3, m0
packuswb m3, m3
vpermq m3, m3, 11011000b
movu [%1], xm3
%endmacro
%macro INTRA_PRED_ANG16_MC4 3
vperm2i128 m1, m1, m2, 00100000b
pmaddubsw m4, m1, [r4 + (%3 * mmsize)]
pmulhrsw m4, m0
packuswb m3, m4
vpermq m3, m3, 11011000b
movu [%1], xm3
vextracti128 xm3, m3, 1
movu [%2], xm3
%endmacro
%if ARCH_X86_64 == 1
%macro INTRA_PRED_TRANS_STORE_16x16 0
punpcklbw m8, m0, m1
punpckhbw m0, m1
punpcklbw m1, m2, m3
punpckhbw m2, m3
punpcklbw m3, m4, m5
punpckhbw m4, m5
punpcklbw m5, m6, m7
punpckhbw m6, m7
punpcklwd m7, m8, m1
punpckhwd m8, m1
punpcklwd m1, m3, m5
punpckhwd m3, m5
punpcklwd m5, m0, m2
punpckhwd m0, m2
punpcklwd m2, m4, m6
punpckhwd m4, m6
punpckldq m6, m7, m1
punpckhdq m7, m1
punpckldq m1, m8, m3
punpckhdq m8, m3
punpckldq m3, m5, m2
punpckhdq m5, m2
punpckldq m2, m0, m4
punpckhdq m0, m4
vpermq m6, m6, 0xD8
vpermq m7, m7, 0xD8
vpermq m1, m1, 0xD8
vpermq m8, m8, 0xD8
vpermq m3, m3, 0xD8
vpermq m5, m5, 0xD8
vpermq m2, m2, 0xD8
vpermq m0, m0, 0xD8
movu [r0], xm6
vextracti128 xm4, m6, 1
movu [r0 + r1], xm4
movu [r0 + 2 * r1], xm7
vextracti128 xm4, m7, 1
movu [r0 + r3], xm4
lea r0, [r0 + 4 * r1]
movu [r0], xm1
vextracti128 xm4, m1, 1
movu [r0 + r1], xm4
movu [r0 + 2 * r1], xm8
vextracti128 xm4, m8, 1
movu [r0 + r3], xm4
lea r0, [r0 + 4 * r1]
movu [r0], xm3
vextracti128 xm4, m3, 1
movu [r0 + r1], xm4
movu [r0 + 2 * r1], xm5
vextracti128 xm4, m5, 1
movu [r0 + r3], xm4
lea r0, [r0 + 4 * r1]
movu [r0], xm2
vextracti128 xm4, m2, 1
movu [r0 + r1], xm4
movu [r0 + 2 * r1], xm0
vextracti128 xm4, m0, 1
movu [r0 + r3], xm4
%endmacro
%macro INTRA_PRED_ANG16_CAL_ROW 3
pmaddubsw %1, m9, [r4 + (%3 * mmsize)]
pmulhrsw %1, m11
pmaddubsw %2, m10, [r4 + (%3 * mmsize)]
pmulhrsw %2, m11
packuswb %1, %2
%endmacro
INIT_YMM avx2
cglobal intra_pred_ang16_12, 3,4,9
vbroadcasti128 m0, [angHor_tab_12]
vbroadcasti128 m1, [angHor_tab_12 + mmsize/2]
mova m2, [pw_1024]
mova m7, [ang16_shuf_mode12]
mova m8, [ang16_shuf_mode12 + mmsize]
lea r3, [r1 * 3]
movu xm4, [r2 + mmsize - 2]
pinsrb xm4, [r2 + 0], 2
pinsrb xm4, [r2 + 6], 1
pinsrb xm4, [r2 + 13], 0
vbroadcasti128 m6, [r2 + mmsize + 14]
vinserti128 m3, m4, xm4, 1
pshufb m4, m3, m7
pshufb m5, m3, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 2
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 4
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 6
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 8
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 10
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 12
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 14
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
RET
INIT_YMM avx2
cglobal intra_pred_ang16_13, 3,4,9
vbroadcasti128 m0, [angHor_tab_13]
vbroadcasti128 m1, [angHor_tab_13 + mmsize/2]
mova m2, [pw_1024]
mova m7, [ang16_shuf_mode13]
mova m8, [ang16_shuf_mode13 + mmsize]
lea r3, [r1 * 3]
vbroadcasti128 m3, [r2 + mmsize + 1]
vbroadcasti128 m4, [r2]
pshufb m4, [ang16_shuf_mode13 + mmsize * 2]
palignr m3, m4, 11
vbroadcasti128 m6, [r2 + mmsize + 12]
pshufb m4, m3, m7
pshufb m5, m3, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 2
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 4
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 6
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 8
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 10
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 12
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 14
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
RET
INIT_YMM avx2
cglobal intra_pred_ang16_14, 3,4,9
vbroadcasti128 m0, [angHor_tab_14]
vbroadcasti128 m1, [angHor_tab_14 + mmsize/2]
mova m2, [pw_1024]
mova m7, [ang16_shuf_mode14]
mova m8, [ang16_shuf_mode14 + mmsize]
lea r3, [r1 * 3]
vbroadcasti128 m3, [r2 + mmsize + 1]
vbroadcasti128 m4, [r2]
pshufb m4, [ang16_shuf_mode14 + mmsize * 2]
palignr m3, m4, 9
vbroadcasti128 m6, [r2 + mmsize + 10]
pshufb m4, m3, m7
pshufb m5, m3, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 2
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 4
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 6
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 8
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 10
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 12
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 14
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
RET
INIT_YMM avx2
cglobal intra_pred_ang16_15, 3,4,9
vbroadcasti128 m0, [angHor_tab_15]
vbroadcasti128 m1, [angHor_tab_15 + mmsize/2]
mova m2, [pw_1024]
mova m7, [ang16_shuf_mode15]
mova m8, [ang16_shuf_mode15 + mmsize]
lea r3, [r1 * 3]
vbroadcasti128 m3, [r2 + mmsize + 1]
vbroadcasti128 m4, [r2]
pshufb m4, [ang16_shuf_mode15 + mmsize * 2]
palignr m3, m3, m4, 7
vbroadcasti128 m6, [r2 + mmsize + 8]
pshufb m4, m3, m7
pshufb m5, m3, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 2
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 4
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 6
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 8
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 10
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 12
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 14
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
RET
INIT_YMM avx2
cglobal intra_pred_ang16_16, 3,4,9
vbroadcasti128 m0, [angHor_tab_16]
vbroadcasti128 m1, [angHor_tab_16 + mmsize/2]
mova m2, [pw_1024]
mova m7, [ang16_shuf_mode16]
mova m8, [ang16_shuf_mode16 + mmsize]
lea r3, [r1 * 3]
vbroadcasti128 m3, [r2 + mmsize + 1]
vbroadcasti128 m4, [r2]
pshufb m4, [ang16_shuf_mode16 + mmsize * 2]
palignr m3, m4, 5
vbroadcasti128 m6, [r2 + mmsize + 6]
pshufb m4, m3, m7
pshufb m5, m3, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 2
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 4
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 6
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 8
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 10
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 12
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 14
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
RET
INIT_YMM avx2
cglobal intra_pred_ang16_17, 3,4,9
vbroadcasti128 m0, [angHor_tab_17]
vbroadcasti128 m1, [angHor_tab_17 + mmsize/2]
mova m2, [pw_1024]
mova m7, [ang16_shuf_mode17]
mova m8, [ang16_shuf_mode17 + mmsize]
lea r3, [r1 * 3]
vbroadcasti128 m3, [r2 + mmsize + 1]
vbroadcasti128 m4, [r2]
pshufb m4, [ang16_shuf_mode17 + mmsize * 2]
palignr m3, m4, 3
vbroadcasti128 m6, [r2 + mmsize + 4]
pshufb m4, m3, m7
pshufb m5, m3, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 2
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 4
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 6
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 8
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 10
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 12
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 14
pshufb m4, m5, m7
pshufb m5, m8
pmaddubsw m4, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
RET
INIT_YMM avx2
cglobal intra_pred_ang16_11, 3,4,8
vbroadcasti128 m0, [angHor_tab_11]
vbroadcasti128 m1, [angHor_tab_11 + mmsize/2]
mova m2, [pw_1024]
mova m7, [ang32_shuf_mode9]
lea r3, [r1 * 3]
; prepare for [0 -1 -2...]
movu xm3, [r2 + mmsize]
pinsrb xm3, [r2], 0
vbroadcasti128 m6, [r2 + mmsize + 16]
vinserti128 m3, m3, xm3, 1
pshufb m5, m3, m7 ; [ 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2]
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 2
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 4
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 6
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 8
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 10
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 12
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 14
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
RET
; transpose 8x32 to 16x16, used for intra_ang16x16 avx2 asm
%if ARCH_X86_64 == 1
INIT_YMM avx2
%macro TRANSPOSE_STORE_8x32 12
jc .skip
punpcklbw m%9, m%1, m%2
punpckhbw m%1, m%2
punpcklbw m%10, m%3, m%4
punpckhbw m%3, m%4
punpcklwd m%11, m%9, m%10
punpckhwd m%9, m%10
punpcklwd m%10, m%1, m%3
punpckhwd m%1, m%3
punpckldq m%12, m%11, m%10
punpckhdq m%11, m%10
punpckldq m%10, m%9, m%1
punpckhdq m%9, m%1
punpcklbw m%1, m%5, m%6
punpckhbw m%5, m%6
punpcklbw m%2, m%7, m%8
punpckhbw m%7, m%8
punpcklwd m%3, m%1, m%2
punpckhwd m%1, m%2
punpcklwd m%4, m%5, m%7
punpckhwd m%5, m%7
punpckldq m%2, m%3, m%4
punpckhdq m%3, m%4
punpckldq m%4, m%1, m%5
punpckhdq m%1, m%5
punpckldq m%5, m%12, m%2
punpckhdq m%6, m%12, m%2
punpckldq m%7, m%10, m%4
punpckhdq m%8, m%10, m%4
punpckldq m%2, m%11, m%3
punpckhdq m%11, m%11, m%3
punpckldq m%4, m%9, m%1
punpckhdq m%9, m%9, m%1
movu [r0 + r1 * 0], xm%5
movu [r0 + r1 * 1], xm%6
movu [r0 + r1 * 2], xm%2
movu [r0 + r5 * 1], xm%11
add r0, r6
movu [r0 + r1 * 0], xm%7
movu [r0 + r1 * 1], xm%8
movu [r0 + r1 * 2], xm%4
movu [r0 + r5 * 1], xm%9
add r0, r6
vextracti128 [r0 + r1 * 0], m%5, 1
vextracti128 [r0 + r1 * 1], m%6, 1
vextracti128 [r0 + r1 * 2], m%2, 1
vextracti128 [r0 + r5 * 1], m%11, 1
add r0, r6
vextracti128 [r0 + r1 * 0], m%7, 1
vextracti128 [r0 + r1 * 1], m%8, 1
vextracti128 [r0 + r1 * 2], m%4, 1
vextracti128 [r0 + r5 * 1], m%9, 1
jmp .end
.skip:
vpermq m%1, m%1, q3120
vpermq m%2, m%2, q3120
vpermq m%3, m%3, q3120
vpermq m%4, m%4, q3120
vpermq m%5, m%5, q3120
vpermq m%6, m%6, q3120
vpermq m%7, m%7, q3120
vpermq m%8, m%8, q3120
movu [r0 + r1 * 0], xm%1
movu [r0 + r1 * 1], xm%2
movu [r0 + r1 * 2], xm%3
movu [r0 + r5 * 1], xm%4
add r0, r6
movu [r0 + r1 * 0], xm%5
movu [r0 + r1 * 1], xm%6
movu [r0 + r1 * 2], xm%7
movu [r0 + r5 * 1], xm%8
add r0, r6
vextracti128 [r0 + r1 * 0], m%1, 1
vextracti128 [r0 + r1 * 1], m%2, 1
vextracti128 [r0 + r1 * 2], m%3, 1
vextracti128 [r0 + r5 * 1], m%4, 1
add r0, r6
vextracti128 [r0 + r1 * 0], m%5, 1
vextracti128 [r0 + r1 * 1], m%6, 1
vextracti128 [r0 + r1 * 2], m%7, 1
vextracti128 [r0 + r5 * 1], m%8, 1
.end:
%endmacro
cglobal ang16_mode_3_33
; rows 0 to 7
movu m0, [r2 + 1] ; [32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
movu m1, [r2 + 2] ; [33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
punpckhbw m2, m0, m1 ; [33 32 32 31 31 30 30 29 29 28 28 27 27 26 26 25 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m0, m1 ; [25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
vextracti128 xm1, m0, 1
vperm2i128 m0, m0, m2, 0x20 ; [17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
vperm2i128 m2, m2, m1, 0x20 ; [25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
pmaddubsw m4, m0, [r3 + 10 * 32] ; [26]
pmulhrsw m4, m7
palignr m5, m2, m0, 2
pmaddubsw m5, [r3 + 4 * 32] ; [20]
pmulhrsw m5, m7
palignr m6, m2, m0, 4
palignr m8, m2, m0, 6
pmaddubsw m6, [r3 - 2 * 32] ; [14]
pmulhrsw m6, m7
pmaddubsw m8, [r3 - 8 * 32] ; [8]
pmulhrsw m8, m7
palignr m10, m2, m0, 8
pmaddubsw m9, m10, [r3 - 14 * 32] ; [2]
pmulhrsw m9, m7
pmaddubsw m10, [r3 + 12 * 32] ; [28]
pmulhrsw m10, m7
palignr m11, m2, m0, 10
palignr m12, m2, m0, 12
pmaddubsw m11, [r3 + 6 * 32] ; [22]
pmulhrsw m11, m7
pmaddubsw m12, [r3] ; [16]
pmulhrsw m12, m7
; rows 8 to 15
palignr m3, m2, m0, 14
palignr m1, m1, m2, 14
pmaddubsw m3, [r3 - 6 * 32] ; [10]
pmulhrsw m3, m7
packuswb m4, m3
pmaddubsw m3, m2, [r3 - 12 * 32] ; [4]
pmulhrsw m3, m7
packuswb m5, m3
pmaddubsw m3, m2, [r3 + 14 * 32] ; [30]
pmulhrsw m3, m7
packuswb m6, m3
movu xm0, [r2 + 25]
movu xm1, [r2 + 26]
punpcklbw m0, m1
mova m1, m2
vinserti128 m1, m1, xm0, 0
vpermq m1, m1, 01001110b
palignr m3, m1, m2, 2
pmaddubsw m3, [r3 + 8 * 32] ; [24]
pmulhrsw m3, m7
packuswb m8, m3
palignr m3, m1, m2, 4
pmaddubsw m3, [r3 + 2 * 32] ; [18]
pmulhrsw m3, m7
packuswb m9, m3
palignr m3, m1, m2, 6
pmaddubsw m3, [r3 - 4 * 32] ; [12]
pmulhrsw m3, m7
packuswb m10, m3
palignr m3, m1, m2, 8
pmaddubsw m3, [r3 - 10 * 32] ; [6]
pmulhrsw m3, m7
packuswb m11, m3
pmovzxbw m1, [r2 + 14]
packuswb m12, m1
TRANSPOSE_STORE_8x32 4, 5, 6, 8, 9, 10, 11, 12, 0, 1, 2, 3
ret
INIT_YMM avx2
cglobal intra_pred_ang16_3, 3, 7, 13
add r2, 32
lea r3, [ang_table_avx2 + 16 * 32]
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
clc
call ang16_mode_3_33
RET
INIT_YMM avx2
cglobal intra_pred_ang16_33, 3, 7, 13
lea r3, [ang_table_avx2 + 16 * 32]
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
stc
call ang16_mode_3_33
RET
cglobal ang16_mode_4_32
; rows 0 to 7
movu m0, [r2 + 1] ; [32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
movu m1, [r2 + 2] ; [33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
punpckhbw m2, m0, m1 ; [33 32 32 31 31 30 30 29 29 28 28 27 27 26 26 25 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m0, m1 ; [25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
vextracti128 xm1, m0, 1
vperm2i128 m0, m0, m2, 0x20 ; [17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
vperm2i128 m2, m2, m1, 0x20 ; [25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
pmaddubsw m4, m0, [r3 + 5 * 32] ; [21]
pmulhrsw m4, m7
palignr m1, m2, m0, 2
pmaddubsw m5, m1, [r3 - 6 * 32] ; [10]
pmulhrsw m5, m7
palignr m8, m2, m0, 4
pmaddubsw m6, m1, [r3 + 15 * 32] ; [31]
pmulhrsw m6, m7
pmaddubsw m8, [r3 + 4 * 32] ; [20]
pmulhrsw m8, m7
palignr m10, m2, m0, 6
pmaddubsw m9, m10, [r3 - 7 * 32] ; [9]
pmulhrsw m9, m7
pmaddubsw m10, [r3 + 14 * 32] ; [30]
pmulhrsw m10, m7
palignr m11, m2, m0, 8
palignr m1, m2, m0, 10
pmaddubsw m11, [r3 + 3 * 32] ; [19]
pmulhrsw m11, m7
pmaddubsw m12, m1, [r3 - 8 * 32] ; [8]
pmulhrsw m12, m7
; rows 8 to 15
pmaddubsw m3, m1, [r3 + 13 * 32] ; [29]
pmulhrsw m3, m7
packuswb m4, m3
palignr m3, m2, m0, 12
pmaddubsw m3, m3, [r3 + 2 * 32] ; [18]
pmulhrsw m3, m7
packuswb m5, m3
palignr m1, m2, m0, 14
pmaddubsw m3, m1, [r3 - 9 * 32] ; [7]
pmulhrsw m3, m7
packuswb m6, m3
pmaddubsw m3, m1, [r3 + 12 * 32] ; [28]
pmulhrsw m3, m7
packuswb m8, m3
palignr m3, m2, m0, 16
pmaddubsw m3, [r3 + 1 * 32] ; [17]
pmulhrsw m3, m7
packuswb m9, m3
movu xm0, [r2 + 25]
movu xm1, [r2 + 26]
punpcklbw m0, m1
mova m1, m2
vinserti128 m1, m1, xm0, 0
vpermq m1, m1, 01001110b
palignr m0, m1, m2, 2
pmaddubsw m3, m0, [r3 - 10 * 32] ; [6]
pmulhrsw m3, m7
packuswb m10, m3
pmaddubsw m3, m0, [r3 + 11 * 32] ; [27]
pmulhrsw m3, m7
packuswb m11, m3
palignr m1, m1, m2, 4
pmaddubsw m1, [r3] ; [16]
pmulhrsw m1, m7
packuswb m12, m1
TRANSPOSE_STORE_8x32 4, 5, 6, 8, 9, 10, 11, 12, 0, 1, 2, 3
ret
INIT_YMM avx2
cglobal intra_pred_ang16_4, 3, 7, 13
add r2, 32
lea r3, [ang_table_avx2 + 16 * 32]
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
clc
call ang16_mode_4_32
RET
INIT_YMM avx2
cglobal intra_pred_ang16_32, 3, 7, 13
lea r3, [ang_table_avx2 + 16 * 32]
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
stc
call ang16_mode_4_32
RET
cglobal ang16_mode_5
; rows 0 to 7
movu m0, [r2 + 1] ; [32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
movu m1, [r2 + 2] ; [33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
punpckhbw m2, m0, m1 ; [33 32 32 31 31 30 30 29 29 28 28 27 27 26 26 25 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m0, m1 ; [25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
vextracti128 xm1, m0, 1
vperm2i128 m0, m0, m2, 0x20 ; [17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
vperm2i128 m2, m2, m1, 0x20 ; [25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
pmaddubsw m4, m0, [r3 + 1 * 32] ; [17]
pmulhrsw m4, m7
palignr m1, m2, m0, 2
pmaddubsw m5, m1, [r3 - 14 * 32] ; [2]
pmulhrsw m5, m7
palignr m3, m2, m0, 4
pmaddubsw m6, m1, [r3 + 3 * 32] ; [19]
pmulhrsw m6, m7
pmaddubsw m8, m3, [r3 - 12 * 32] ; [4]
pmulhrsw m8, m7
pmaddubsw m9, m3, [r3 + 5 * 32] ; [21]
pmulhrsw m9, m7
palignr m3, m2, m0, 6
pmaddubsw m10, m3, [r3 - 10 * 32] ; [6]
pmulhrsw m10, m7
palignr m1, m2, m0, 8
pmaddubsw m11, m3, [r3 + 7 * 32] ; [23]
pmulhrsw m11, m7
pmaddubsw m12, m1, [r3 - 8 * 32] ; [8]
pmulhrsw m12, m7
; rows 8 to 15
pmaddubsw m3, m1, [r3 + 9 * 32] ; [25]
pmulhrsw m3, m7
packuswb m4, m3
palignr m1, m2, m0, 10
pmaddubsw m3, m1, [r3 - 6 * 32] ; [10]
pmulhrsw m3, m7
packuswb m5, m3
pmaddubsw m3, m1, [r3 + 11 * 32] ; [27]
pmulhrsw m3, m7
packuswb m6, m3
palignr m1, m2, m0, 12
pmaddubsw m3, m1, [r3 - 4 * 32] ; [12]
pmulhrsw m3, m7
packuswb m8, m3
pmaddubsw m3, m1, [r3 + 13 * 32] ; [29]
pmulhrsw m3, m7
packuswb m9, m3
palignr m1, m2, m0, 14
pmaddubsw m3, m1, [r3 - 2 * 32] ; [14]
pmulhrsw m3, m7
packuswb m10, m3
pmaddubsw m3, m1, [r3 + 15 * 32] ; [31]
pmulhrsw m3, m7
packuswb m11, m3
palignr m1, m2, m0, 16
pmaddubsw m1, [r3] ; [16]
pmulhrsw m1, m7
packuswb m12, m1
TRANSPOSE_STORE_8x32 4, 5, 6, 8, 9, 10, 11, 12, 0, 1, 2, 3
ret
INIT_YMM avx2
cglobal intra_pred_ang16_5, 3, 7, 13
add r2, 32
lea r3, [ang_table_avx2 + 16 * 32]
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
clc
call ang16_mode_5
RET
cglobal ang16_mode_6
; rows 0 to 7
movu m0, [r2 + 1] ; [32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
movu m1, [r2 + 2] ; [33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
punpckhbw m2, m0, m1 ; [33 32 32 31 31 30 30 29 29 28 28 27 27 26 26 25 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m0, m1 ; [25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
vextracti128 xm1, m0, 1
vperm2i128 m0, m0, m2, 0x20 ; [17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
vperm2i128 m2, m2, m1, 0x20 ; [25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
pmaddubsw m4, m0, [r3 - 3 * 32] ; [13]
pmulhrsw m4, m7
pmaddubsw m5, m0, [r3 + 10 * 32] ; [26]
pmulhrsw m5, m7
palignr m3, m2, m0, 2
pmaddubsw m6, m3, [r3 - 9 * 32] ; [7]
pmulhrsw m6, m7
pmaddubsw m8, m3, [r3 + 4 * 32] ; [20]
pmulhrsw m8, m7
palignr m3, m2, m0, 4
pmaddubsw m9, m3, [r3 - 15 * 32] ; [1]
pmulhrsw m9, m7
pmaddubsw m10, m3, [r3 - 2 * 32] ; [14]
pmulhrsw m10, m7
pmaddubsw m11, m3, [r3 + 11 * 32] ; [27]
pmulhrsw m11, m7
palignr m1, m2, m0, 6
pmaddubsw m12, m1, [r3 - 8 * 32] ; [8]
pmulhrsw m12, m7
; rows 8 to 15
pmaddubsw m3, m1, [r3 + 5 * 32] ; [21]
pmulhrsw m3, m7
packuswb m4, m3
palignr m1, m2, m0, 8
pmaddubsw m3, m1, [r3 - 14 * 32] ; [2]
pmulhrsw m3, m7
packuswb m5, m3
pmaddubsw m3, m1, [r3 - 1 * 32] ; [15]
pmulhrsw m3, m7
packuswb m6, m3
pmaddubsw m3, m1, [r3 + 12 * 32] ; [28]
pmulhrsw m3, m7
packuswb m8, m3
palignr m1, m2, m0, 10
pmaddubsw m3, m1, [r3 - 7 * 32] ; [9]
pmulhrsw m3, m7
packuswb m9, m3
pmaddubsw m3, m1, [r3 + 6 * 32] ; [22]
pmulhrsw m3, m7
packuswb m10, m3
palignr m1, m2, m0, 12
pmaddubsw m3, m1, [r3 - 13 * 32] ; [3]
pmulhrsw m3, m7
packuswb m11, m3
pmaddubsw m1, [r3] ; [16]
pmulhrsw m1, m7
packuswb m12, m1
TRANSPOSE_STORE_8x32 4, 5, 6, 8, 9, 10, 11, 12, 0, 1, 2, 3
ret
INIT_YMM avx2
cglobal intra_pred_ang16_6, 3, 7, 13
add r2, 32
lea r3, [ang_table_avx2 + 16 * 32]
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
clc
call ang16_mode_6
RET
cglobal ang16_mode_7
; rows 0 to 7
movu m0, [r2 + 1] ; [32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
movu m1, [r2 + 2] ; [33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
punpckhbw m2, m0, m1 ; [33 32 32 31 31 30 30 29 29 28 28 27 27 26 26 25 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m0, m1 ; [25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
vextracti128 xm1, m0, 1
vperm2i128 m0, m0, m2, 0x20 ; [17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
vperm2i128 m2, m2, m1, 0x20 ; [25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
pmaddubsw m4, m0, [r3 - 7 * 32] ; [9]
pmulhrsw m4, m7
pmaddubsw m5, m0, [r3 + 2 * 32] ; [18]
pmulhrsw m5, m7
pmaddubsw m6, m0, [r3 + 11 * 32] ; [27]
pmulhrsw m6, m7
palignr m3, m2, m0, 2
pmaddubsw m8, m3, [r3 - 12 * 32] ; [4]
pmulhrsw m8, m7
pmaddubsw m9, m3, [r3 - 3 * 32] ; [13]
pmulhrsw m9, m7
pmaddubsw m10, m3, [r3 + 6 * 32] ; [22]
pmulhrsw m10, m7
pmaddubsw m11, m3, [r3 + 15 * 32] ; [31]
pmulhrsw m11, m7
palignr m1, m2, m0, 4
pmaddubsw m12, m1, [r3 - 8 * 32] ; [8]
pmulhrsw m12, m7
; rows 8 to 15
pmaddubsw m3, m1, [r3 + 1 * 32] ; [17]
pmulhrsw m3, m7
packuswb m4, m3
pmaddubsw m3, m1, [r3 + 10 * 32] ; [26]
pmulhrsw m3, m7
packuswb m5, m3
palignr m1, m2, m0, 6
pmaddubsw m3, m1, [r3 - 13 * 32] ; [3]
pmulhrsw m3, m7
packuswb m6, m3
pmaddubsw m3, m1, [r3 - 4 * 32] ; [12]
pmulhrsw m3, m7
packuswb m8, m3
pmaddubsw m3, m1, [r3 + 5 * 32] ; [21]
pmulhrsw m3, m7
packuswb m9, m3
pmaddubsw m3, m1, [r3 + 14 * 32] ; [30]
pmulhrsw m3, m7
packuswb m10, m3
palignr m1, m2, m0, 8
pmaddubsw m3, m1, [r3 - 9 * 32] ; [7]
pmulhrsw m3, m7
packuswb m11, m3
pmaddubsw m1, [r3] ; [16]
pmulhrsw m1, m7
packuswb m12, m1
TRANSPOSE_STORE_8x32 4, 5, 6, 8, 9, 10, 11, 12, 0, 1, 2, 3
ret
INIT_YMM avx2
cglobal intra_pred_ang16_7, 3, 7, 13
add r2, 32
lea r3, [ang_table_avx2 + 16 * 32]
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
clc
call ang16_mode_7
RET
cglobal ang16_mode_8
; rows 0 to 7
movu m0, [r2 + 1] ; [32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
movu m1, [r2 + 2] ; [33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
punpckhbw m2, m0, m1 ; [33 32 32 31 31 30 30 29 29 28 28 27 27 26 26 25 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
punpcklbw m0, m1 ; [25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
vextracti128 xm1, m0, 1
vperm2i128 m0, m0, m2, 0x20 ; [17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1]
vperm2i128 m2, m2, m1, 0x20 ; [25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9]
pmaddubsw m4, m0, [r3 - 11 * 32] ; [5]
pmulhrsw m4, m7
pmaddubsw m5, m0, [r3 - 6 * 32] ; [10]
pmulhrsw m5, m7
pmaddubsw m6, m0, [r3 - 1 * 32] ; [15]
pmulhrsw m6, m7
pmaddubsw m8, m0, [r3 + 4 * 32] ; [20]
pmulhrsw m8, m7
pmaddubsw m9, m0, [r3 + 9 * 32] ; [25]
pmulhrsw m9, m7
pmaddubsw m10, m0, [r3 + 14 * 32] ; [30]
pmulhrsw m10, m7
palignr m1, m2, m0, 2
pmaddubsw m11, m1, [r3 - 13 * 32] ; [3]
pmulhrsw m11, m7
pmaddubsw m12, m1, [r3 - 8 * 32] ; [8]
pmulhrsw m12, m7
; rows 8 to 15
pmaddubsw m3, m1, [r3 - 3 * 32] ; [13]
pmulhrsw m3, m7
packuswb m4, m3
pmaddubsw m3, m1, [r3 + 2 * 32] ; [18]
pmulhrsw m3, m7
packuswb m5, m3
pmaddubsw m3, m1, [r3 + 7 * 32] ; [23]
pmulhrsw m3, m7
packuswb m6, m3
pmaddubsw m3, m1, [r3 + 12 * 32] ; [28]
pmulhrsw m3, m7
packuswb m8, m3
palignr m1, m2, m0, 4
pmaddubsw m3, m1, [r3 - 15 * 32] ; [1]
pmulhrsw m3, m7
packuswb m9, m3
pmaddubsw m3, m1, [r3 - 10 * 32] ; [6]
pmulhrsw m3, m7
packuswb m10, m3
pmaddubsw m3, m1, [r3 - 5 * 32] ; [11]
pmulhrsw m3, m7
packuswb m11, m3
pmaddubsw m1, [r3] ; [16]
pmulhrsw m1, m7
packuswb m12, m1
TRANSPOSE_STORE_8x32 4, 5, 6, 8, 9, 10, 11, 12, 0, 1, 2, 3
ret
INIT_YMM avx2
cglobal intra_pred_ang16_8, 3, 7, 13
add r2, 32
lea r3, [ang_table_avx2 + 16 * 32]
lea r5, [r1 * 3] ; r5 -> 3 * stride
lea r6, [r1 * 4] ; r6 -> 4 * stride
mova m7, [pw_1024]
clc
call ang16_mode_8
RET
%endif ; ARCH_X86_64
INIT_YMM avx2
cglobal intra_pred_ang16_9, 3,4,8
vbroadcasti128 m0, [angHor_tab_9]
vbroadcasti128 m1, [angHor_tab_9 + mmsize/2]
mova m2, [pw_1024]
lea r3, [r1 * 3]
mova m7, [ang16_shuf_mode9]
vbroadcasti128 m6, [r2 + mmsize + 17]
vbroadcasti128 m3, [r2 + mmsize + 1]
pshufb m5, m3, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 2
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 4
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 6
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 8
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 10
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
lea r0, [r0 + r1 * 4]
palignr m5, m6, m3, 12
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0], xm4
vextracti128 [r0 + r1], m4, 1
palignr m5, m6, m3, 14
pshufb m5, m7
pmaddubsw m4, m5, m0
pmaddubsw m5, m1
pmulhrsw m4, m2
pmulhrsw m5, m2
packuswb m4, m5
movu [r0 + r1 * 2], xm4
vextracti128 [r0 + r3], m4, 1
RET
%endif
INIT_YMM avx2
cglobal intra_pred_ang16_25, 3, 5, 5
mova m0, [pw_1024]
vbroadcasti128 m1, [r2]
pshufb m1, [intra_pred_shuff_0_8]
vbroadcasti128 m2, [r2 + 8]
pshufb m2, [intra_pred_shuff_0_8]
lea r3, [3 * r1]
lea r4, [c_ang16_mode_25]
INTRA_PRED_ANG16_MC1 0
lea r0, [r0 + 4 * r1]
INTRA_PRED_ANG16_MC1 2
add r4, 4 * mmsize
lea r0, [r0 + 4 * r1]
INTRA_PRED_ANG16_MC1 0
lea r0, [r0 + 4 * r1]
INTRA_PRED_ANG16_MC1 2
RET
INIT_YMM avx2
cglobal intra_pred_ang16_28, 3, 5, 6
mova m0, [pw_1024]
mova m5, [intra_pred_shuff_0_8]
lea r3, [3 * r1]
lea r4, [c_ang16_mode_28]
INTRA_PRED_ANG16_MC2 1
INTRA_PRED_ANG16_MC1 0
lea r0, [r0 + 4 * r1]
INTRA_PRED_ANG16_MC0 r0, r0 + r1, 2
INTRA_PRED_ANG16_MC2 2
INTRA_PRED_ANG16_MC0 r0 + 2 * r1, r0 + r3, 3
lea r0, [r0 + 4 * r1]
add r4, 4 * mmsize
INTRA_PRED_ANG16_MC1 0
INTRA_PRED_ANG16_MC2 3
lea r0, [r0 + 4 * r1]
INTRA_PRED_ANG16_MC1 2
RET
INIT_YMM avx2
cglobal intra_pred_ang16_27, 3, 5, 5
mova m0, [pw_1024]
lea r3, [3 * r1]
lea r4, [c_ang16_mode_27]
vbroadcasti128 m1, [r2 + 1]
pshufb m1, [intra_pred_shuff_0_8]
vbroadcasti128 m2, [r2 + 9]
pshufb m2, [intra_pred_shuff_0_8]
INTRA_PRED_ANG16_MC1 0
lea r0, [r0 + 4 * r1]
INTRA_PRED_ANG16_MC1 2
lea r0, [r0 + 4 * r1]
add r4, 4 * mmsize
INTRA_PRED_ANG16_MC1 0
lea r0, [r0 + 4 * r1]
INTRA_PRED_ANG16_MC0 r0, r0 + r1, 2
vperm2i128 m1, m1, m2, 00100000b
pmaddubsw m3, m1, [r4 + 3 * mmsize]
pmulhrsw m3, m0
vbroadcasti128 m2, [r2 + 2]
pshufb m2, [intra_pred_shuff_0_15]
pmaddubsw m2, [r4 + 4 * mmsize]
pmulhrsw m2, m0
packuswb m3, m2
vpermq m3, m3, 11011000b
movu [r0 + 2 * r1], xm3
vextracti128 xm4, m3, 1
movu [r0 + r3], xm4
RET
INIT_YMM avx2
cglobal intra_pred_ang16_29, 3, 5, 5
mova m0, [pw_1024]
mova m5, [intra_pred_shuff_0_8]
lea r3, [3 * r1]
lea r4, [c_ang16_mode_29]
INTRA_PRED_ANG16_MC2 1
INTRA_PRED_ANG16_MC0 r0, r0 + r1, 0
INTRA_PRED_ANG16_MC3 r0 + 2 * r1, 1
INTRA_PRED_ANG16_MC2 2
INTRA_PRED_ANG16_MC0 r0 + r3, r0 + 4 * r1, 2
lea r0, [r0 + r1 * 4]
INTRA_PRED_ANG16_MC0 r0 + r1, r0 + 2 * r1, 3
INTRA_PRED_ANG16_MC2 3
add r4, 4 * mmsize
INTRA_PRED_ANG16_MC0 r0 + r3, r0 + 4 * r1, 0
lea r0, [r0 + r1 * 4]
INTRA_PRED_ANG16_MC3 r0 + r1, 1
INTRA_PRED_ANG16_MC2 4
INTRA_PRED_ANG16_MC0 r0 + 2 * r1, r0 + r3, 2
lea r0, [r0 + r1 * 4]
INTRA_PRED_ANG16_MC0 r0, r0 + r1, 3
add r4, 4 * mmsize
INTRA_PRED_ANG16_MC2 5
INTRA_PRED_ANG16_MC0 r0 + 2 * r1, r0 + r3, 0
RET
INIT_YMM avx2
cglobal intra_pred_ang16_30, 3, 5, 6
mova m0, [pw_1024]
mova m5, [intra_pred_shuff_0_8]
lea r3, [3 * r1]
lea r4, [c_ang16_mode_30]
INTRA_PRED_ANG16_MC2 1
INTRA_PRED_ANG16_MC0 r0, r0 + r1, 0
INTRA_PRED_ANG16_MC2 2
INTRA_PRED_ANG16_MC0 r0 + 2 * r1, r0 + r3, 1
INTRA_PRED_ANG16_MC2 3
lea r0, [r0 + 4 * r1]
INTRA_PRED_ANG16_MC0 r0, r0 + r1, 2
INTRA_PRED_ANG16_MC3 r0 + 2 * r1, 3
INTRA_PRED_ANG16_MC2 4
add r4, 4 * mmsize
INTRA_PRED_ANG16_MC0 r0 + r3, r0 + 4 * r1, 0
INTRA_PRED_ANG16_MC2 5
lea r0, [r0 + 4 * r1]
INTRA_PRED_ANG16_MC0 r0 + r1, r0 + 2 * r1, 1
INTRA_PRED_ANG16_MC3 r0 + r3 , 2
INTRA_PRED_ANG16_MC2 6
lea r0, [r0 + 4 * r1]
INTRA_PRED_ANG16_MC0 r0, r0 + r1, 3
INTRA_PRED_ANG16_MC2 7
INTRA_PRED_ANG16_MC0 r0 + 2 * r1, r0 + r3, 4
RET
INIT_YMM avx2
cglobal intra_pred_ang16_31, 3, 5, 6
mova m0, [pw_1024]
mova m5, [intra_pred_shuff_0_8]
lea r3, [3 * r1]
lea r4, [c_ang16_mode_31]
INTRA_PRED_ANG16_MC2 1
INTRA_PRED_ANG16_MC3 r0, 0
INTRA_PRED_ANG16_MC2 2
INTRA_PRED_ANG16_MC0 r0 + r1, r0 + 2 * r1, 1
INTRA_PRED_ANG16_MC2 3
INTRA_PRED_ANG16_MC0 r0 + r3, r0 + 4 * r1, 2
INTRA_PRED_ANG16_MC2 4
lea r0, [r0 + 4 * r1]
INTRA_PRED_ANG16_MC0 r0 + r1, r0 + 2 * r1, 3
INTRA_PRED_ANG16_MC2 5
add r4, 4 * mmsize
INTRA_PRED_ANG16_MC0 r0 + r3, r0 + 4 * r1, 0
INTRA_PRED_ANG16_MC2 6
lea r0, [r0 + 4 * r1]
INTRA_PRED_ANG16_MC0 r0 + r1, r0 + 2 * r1, 1
INTRA_PRED_ANG16_MC2 7
INTRA_PRED_ANG16_MC0 r0 + r3, r0 + 4 * r1, 2
INTRA_PRED_ANG16_MC2 8
lea r0, [r0 + 4 * r1]
INTRA_PRED_ANG16_MC0 r0 + r1, r0 + 2 * r1, 3
INTRA_PRED_ANG16_MC2 9
INTRA_PRED_ANG16_MC3 r0 + r3, 4
RET
INIT_YMM avx2
cglobal intra_pred_ang16_24, 3, 5, 6
mova m0, [pw_1024]
mova m5, [intra_pred_shuff_0_8]
lea r3, [3 * r1]
lea r4, [c_ang16_mode_24]
INTRA_PRED_ANG16_MC2 0
INTRA_PRED_ANG16_MC1 0
lea r0, [r0 + 4 * r1]
INTRA_PRED_ANG16_MC0 r0, r0 + r1, 2
movu xm1, [r2 - 1]
pinsrb xm1, [r2 + 38], 0
vinserti128 m1, m1, xm1, 1
pshufb m1, m5
vbroadcasti128 m2, [r2 + 7]
pshufb m2, m5
INTRA_PRED_ANG16_MC0 r0 + 2 * r1, r0 + r3, 3
lea r0, [r0 + 4 * r1]
add r4, 4 * mmsize
INTRA_PRED_ANG16_MC1 0
movu xm1, [r2 - 2]
pinsrb xm1, [r2 + 45], 0
pinsrb xm1, [r2 + 38], 1
vinserti128 m1, m1, xm1, 1
pshufb m1, m5
vbroadcasti128 m2, [r2 + 6]
pshufb m2, m5
lea r0, [r0 + 4 * r1]
INTRA_PRED_ANG16_MC1 2
RET
%macro INTRA_PRED_ANG16_MC5 2
pslldq xm6, xm6, 1
pinsrb xm6, [r2 + %1], 0
vinserti128 m1, m6, xm6, 1
pshufb m1, m5
vbroadcasti128 m2, [r2 + %2]
pshufb m2, m5
%endmacro
INIT_YMM avx2
cglobal intra_pred_ang16_23, 3, 5, 7
mova m0, [pw_1024]
mova m5, [intra_pred_shuff_0_8]
lea r3, [3 * r1]
lea r4, [c_ang16_mode_23]
INTRA_PRED_ANG16_MC2 0
INTRA_PRED_ANG16_MC0 r0, r0 + r1, 0
INTRA_PRED_ANG16_MC3 r0 + 2 * r1, 1
movu xm6, [r2 - 1]
pinsrb xm6, [r2 + 36], 0
vinserti128 m1, m6, xm6, 1
pshufb m1, m5
vbroadcasti128 m2, [r2 + 7]
pshufb m2, m5
INTRA_PRED_ANG16_MC0 r0 + r3, r0 + 4 * r1, 2
lea r0, [r0 + 4 * r1]
INTRA_PRED_ANG16_MC0 r0 + r1, r0 + 2 * r1, 3
add r4, 4 * mmsize
INTRA_PRED_ANG16_MC5 39, 6
INTRA_PRED_ANG16_MC0 r0 + r3, r0 + 4 * r1, 0
lea r0, [r0 + 4 * r1]
INTRA_PRED_ANG16_MC3 r0 + r1, 1
INTRA_PRED_ANG16_MC5 43, 5
INTRA_PRED_ANG16_MC0 r0 + 2 * r1, r0 + r3, 2
lea r0, [r0 + 4 * r1]
INTRA_PRED_ANG16_MC0 r0, r0 + r1, 3
add r4, 4 * mmsize
INTRA_PRED_ANG16_MC5 46, 4
INTRA_PRED_ANG16_MC0 r0 + 2 * r1, r0 + r3, 0
RET
INIT_YMM avx2
cglobal intra_pred_ang16_22, 3, 5, 7
mova m0, [pw_1024]
mova m5, [intra_pred_shuff_0_8]
lea r3, [3 * r1]
lea r4, [c_ang16_mode_22]
INTRA_PRED_ANG16_MC2 0
INTRA_PRED_ANG16_MC0 r0, r0 + r1, 0
movu xm6, [r2 - 1]
pinsrb xm6, [r2 + 34], 0
vinserti128 m1, m6, xm6, 1
pshufb m1, m5
vbroadcasti128 m2, [r2 + 7]
pshufb m2, m5
INTRA_PRED_ANG16_MC0 r0 + 2 * r1, r0 + r3, 1
lea r0, [r0 + 4 * r1]
INTRA_PRED_ANG16_MC5 37, 6
INTRA_PRED_ANG16_MC0 r0, r0 + r1, 2
INTRA_PRED_ANG16_MC3 r0 + 2 * r1, 3
add r4, 4 * mmsize
INTRA_PRED_ANG16_MC5 39, 5
INTRA_PRED_ANG16_MC0 r0 + r3, r0 + 4 * r1, 0
lea r0, [r0 + 4 * r1]
INTRA_PRED_ANG16_MC5 42, 4
INTRA_PRED_ANG16_MC0 r0 + r1, r0 + 2 * r1, 1
INTRA_PRED_ANG16_MC3 r0 + r3, 2
lea r0, [r0 + 4 * r1]
INTRA_PRED_ANG16_MC5 44, 3
INTRA_PRED_ANG16_MC0 r0, r0 + r1, 3
INTRA_PRED_ANG16_MC5 47, 2
INTRA_PRED_ANG16_MC0 r0 + 2 * r1, r0 + r3, 4
RET
%macro INTRA_PRED_ANG32_ALIGNR_STORE 1
lea r0, [r0 + 4 * r1]
palignr m2, m1, m0, %1
movu [r0], m2
palignr m2, m1, m0, (%1 + 1)
movu [r0 + r1], m2
palignr m2, m1, m0, (%1 + 2)
movu [r0 + 2 * r1], m2
palignr m2, m1, m0, (%1 + 3)
movu [r0 + r3], m2
%endmacro
INIT_YMM avx2
cglobal intra_pred_ang32_34, 3, 4,3
lea r3, [3 * r1]
movu m0, [r2 + 2]
movu m1, [r2 + 18]
movu [r0], m0
palignr m2, m1, m0, 1
movu [r0 + r1], m2
palignr m2, m1, m0, 2
movu [r0 + 2 * r1], m2
palignr m2, m1, m0, 3
movu [r0 + r3], m2
INTRA_PRED_ANG32_ALIGNR_STORE 4
INTRA_PRED_ANG32_ALIGNR_STORE 8
INTRA_PRED_ANG32_ALIGNR_STORE 12
lea r0, [r0 + 4 * r1]
palignr m2, m1, m0, 16
movu [r0], m2
movu m0, [r2 + 19]
movu [r0 + r1], m0
movu m1, [r2 + 35]
palignr m2, m1, m0, 1
movu [r0 + 2 * r1], m2
palignr m2, m1, m0, 2
movu [r0 + r3], m2
INTRA_PRED_ANG32_ALIGNR_STORE 3
INTRA_PRED_ANG32_ALIGNR_STORE 7
INTRA_PRED_ANG32_ALIGNR_STORE 11
RET
INIT_YMM avx2
cglobal intra_pred_ang32_2, 3, 4,3
lea r3, [3 * r1]
movu m0, [r2 + 64 + 2]
movu m1, [r2 + 64 + 18]
movu [r0], m0
palignr m2, m1, m0, 1
movu [r0 + r1], m2
palignr m2, m1, m0, 2
movu [r0 + 2 * r1], m2
palignr m2, m1, m0, 3
movu [r0 + r3], m2
INTRA_PRED_ANG32_ALIGNR_STORE 4
INTRA_PRED_ANG32_ALIGNR_STORE 8
INTRA_PRED_ANG32_ALIGNR_STORE 12
lea r0, [r0 + 4 * r1]
palignr m2, m1, m0, 16
movu [r0], m2
movu m0, [r2 + 64 + 19]
movu [r0 + r1], m0
movu m1, [r2 + 64 + 35]
palignr m2, m1, m0, 1
movu [r0 + 2 * r1], m2
palignr m2, m1, m0, 2
movu [r0 + r3], m2
INTRA_PRED_ANG32_ALIGNR_STORE 3
INTRA_PRED_ANG32_ALIGNR_STORE 7
INTRA_PRED_ANG32_ALIGNR_STORE 11
RET
%macro INTRA_PRED_ANG32_STORE 0
lea r0, [r0 + 4 * r1]
movu [r0], m0
movu [r0 + r1], m0
movu [r0 + r1 * 2], m0
movu [r0 + r3], m0
%endmacro
INIT_YMM avx2
cglobal intra_pred_ang32_26, 3, 4, 1
lea r3, [3 * r1]
movu m0, [r2 + 1]
movu [r0], m0
movu [r0 + r1], m0
movu [r0 + r1 * 2], m0
movu [r0 + r3], m0
INTRA_PRED_ANG32_STORE
INTRA_PRED_ANG32_STORE
INTRA_PRED_ANG32_STORE
INTRA_PRED_ANG32_STORE
INTRA_PRED_ANG32_STORE
INTRA_PRED_ANG32_STORE
INTRA_PRED_ANG32_STORE
RET
%macro INTRA_PRED_STORE_4x4 0
movd [r0], xm0
pextrd [r0 + r1], xm0, 1
vextracti128 xm0, m0, 1
lea r0, [r0 + 2 * r1]
movd [r0], xm0
pextrd [r0 + r1], xm0, 1
%endmacro
%macro INTRA_PRED_TRANS_STORE_4x4 0
vpermq m0, m0, 00001000b
pshufb m0, [c_trans_4x4]
;store
movd [r0], xm0
pextrd [r0 + r1], xm0, 1
lea r0, [r0 + 2 * r1]
pextrd [r0], xm0, 2
pextrd [r0 + r1], xm0, 3
%endmacro
INIT_YMM avx2
cglobal intra_pred_ang4_27, 3, 3, 1
vbroadcasti128 m0, [r2 + 1]
pshufb m0, [intra_pred_shuff_0_4]
pmaddubsw m0, [c_ang4_mode_27]
pmulhrsw m0, [pw_1024]
packuswb m0, m0
INTRA_PRED_STORE_4x4
RET
INIT_YMM avx2
cglobal intra_pred_ang4_28, 3, 3, 1
vbroadcasti128 m0, [r2 + 1]
pshufb m0, [intra_pred_shuff_0_4]
pmaddubsw m0, [c_ang4_mode_28]
pmulhrsw m0, [pw_1024]
packuswb m0, m0
INTRA_PRED_STORE_4x4
RET
INIT_YMM avx2
cglobal intra_pred_ang4_29, 3, 3, 1
vbroadcasti128 m0, [r2 + 1]
pshufb m0, [intra_pred4_shuff1]
pmaddubsw m0, [c_ang4_mode_29]
pmulhrsw m0, [pw_1024]
packuswb m0, m0
INTRA_PRED_STORE_4x4
RET
INIT_YMM avx2
cglobal intra_pred_ang4_30, 3, 3, 1
vbroadcasti128 m0, [r2 + 1]
pshufb m0, [intra_pred4_shuff2]
pmaddubsw m0, [c_ang4_mode_30]
pmulhrsw m0, [pw_1024]
packuswb m0, m0
INTRA_PRED_STORE_4x4
RET
INIT_YMM avx2
cglobal intra_pred_ang4_31, 3, 3, 1
vbroadcasti128 m0, [r2 + 1]
pshufb m0, [intra_pred4_shuff31]
pmaddubsw m0, [c_ang4_mode_31]
pmulhrsw m0, [pw_1024]
packuswb m0, m0
INTRA_PRED_STORE_4x4
RET
INIT_YMM avx2
cglobal intra_pred_ang4_32, 3, 3, 1
vbroadcasti128 m0, [r2 + 1]
pshufb m0, [intra_pred4_shuff31]
pmaddubsw m0, [c_ang4_mode_32]
pmulhrsw m0, [pw_1024]
packuswb m0, m0
INTRA_PRED_STORE_4x4
RET
INIT_YMM avx2
cglobal intra_pred_ang4_33, 3, 3, 1
vbroadcasti128 m0, [r2 + 1]
pshufb m0, [intra_pred4_shuff33]
pmaddubsw m0, [c_ang4_mode_33]
pmulhrsw m0, [pw_1024]
packuswb m0, m0
INTRA_PRED_STORE_4x4
RET
INIT_YMM avx2
cglobal intra_pred_ang4_3, 3, 3, 1
vbroadcasti128 m0, [r2 + 1]
pshufb m0, [intra_pred4_shuff3]
pmaddubsw m0, [c_ang4_mode_33]
pmulhrsw m0, [pw_1024]
packuswb m0, m0
INTRA_PRED_TRANS_STORE_4x4
RET
INIT_YMM avx2
cglobal intra_pred_ang4_4, 3, 3, 1
vbroadcasti128 m0, [r2]
pshufb m0, [intra_pred4_shuff5]
pmaddubsw m0, [c_ang4_mode_32]
pmulhrsw m0, [pw_1024]
packuswb m0, m0
INTRA_PRED_TRANS_STORE_4x4
RET
INIT_YMM avx2
cglobal intra_pred_ang4_5, 3, 3, 1
vbroadcasti128 m0, [r2]
pshufb m0, [intra_pred4_shuff5]
pmaddubsw m0, [c_ang4_mode_5]
pmulhrsw m0, [pw_1024]
packuswb m0, m0
INTRA_PRED_TRANS_STORE_4x4
RET
INIT_YMM avx2
cglobal intra_pred_ang4_6, 3, 3, 1
vbroadcasti128 m0, [r2]
pshufb m0, [intra_pred4_shuff6]
pmaddubsw m0, [c_ang4_mode_6]
pmulhrsw m0, [pw_1024]
packuswb m0, m0
INTRA_PRED_TRANS_STORE_4x4
RET
INIT_YMM avx2
cglobal intra_pred_ang4_7, 3, 3, 1
vbroadcasti128 m0, [r2]
pshufb m0, [intra_pred4_shuff7]
pmaddubsw m0, [c_ang4_mode_7]
pmulhrsw m0, [pw_1024]
packuswb m0, m0
INTRA_PRED_TRANS_STORE_4x4
RET
INIT_YMM avx2
cglobal intra_pred_ang4_8, 3, 3, 1
vbroadcasti128 m0, [r2]
pshufb m0, [intra_pred4_shuff9]
pmaddubsw m0, [c_ang4_mode_8]
pmulhrsw m0, [pw_1024]
packuswb m0, m0
INTRA_PRED_TRANS_STORE_4x4
RET
INIT_YMM avx2
cglobal intra_pred_ang4_9, 3, 3, 1
vbroadcasti128 m0, [r2]
pshufb m0, [intra_pred4_shuff9]
pmaddubsw m0, [c_ang4_mode_9]
pmulhrsw m0, [pw_1024]
packuswb m0, m0
INTRA_PRED_TRANS_STORE_4x4
RET
INIT_YMM avx2
cglobal intra_pred_ang4_11, 3, 3, 1
vbroadcasti128 m0, [r2]
pshufb m0, [intra_pred4_shuff12]
pmaddubsw m0, [c_ang4_mode_11]
pmulhrsw m0, [pw_1024]
packuswb m0, m0
INTRA_PRED_TRANS_STORE_4x4
RET
INIT_YMM avx2
cglobal intra_pred_ang4_12, 3, 3, 1
vbroadcasti128 m0, [r2]
pshufb m0, [intra_pred4_shuff12]
pmaddubsw m0, [c_ang4_mode_12]
pmulhrsw m0, [pw_1024]
packuswb m0, m0
INTRA_PRED_TRANS_STORE_4x4
RET
INIT_YMM avx2
cglobal intra_pred_ang4_13, 3, 3, 1
vbroadcasti128 m0, [r2]
pshufb m0, [intra_pred4_shuff13]
pmaddubsw m0, [c_ang4_mode_13]
pmulhrsw m0, [pw_1024]
packuswb m0, m0
INTRA_PRED_TRANS_STORE_4x4
RET
INIT_YMM avx2
cglobal intra_pred_ang4_14, 3, 3, 1
vbroadcasti128 m0, [r2]
pshufb m0, [intra_pred4_shuff14]
pmaddubsw m0, [c_ang4_mode_14]
pmulhrsw m0, [pw_1024]
packuswb m0, m0
INTRA_PRED_TRANS_STORE_4x4
RET
INIT_YMM avx2
cglobal intra_pred_ang4_15, 3, 3, 1
vbroadcasti128 m0, [r2]
pshufb m0, [intra_pred4_shuff15]
pmaddubsw m0, [c_ang4_mode_15]
pmulhrsw m0, [pw_1024]
packuswb m0, m0
INTRA_PRED_TRANS_STORE_4x4
RET
INIT_YMM avx2
cglobal intra_pred_ang4_16, 3, 3, 1
vbroadcasti128 m0, [r2]
pshufb m0, [intra_pred4_shuff16]
pmaddubsw m0, [c_ang4_mode_16]
pmulhrsw m0, [pw_1024]
packuswb m0, m0
INTRA_PRED_TRANS_STORE_4x4
RET
INIT_YMM avx2
cglobal intra_pred_ang4_17, 3, 3, 1
vbroadcasti128 m0, [r2]
pshufb m0, [intra_pred4_shuff17]
pmaddubsw m0, [c_ang4_mode_17]
pmulhrsw m0, [pw_1024]
packuswb m0, m0
INTRA_PRED_TRANS_STORE_4x4
RET
INIT_YMM avx2
cglobal intra_pred_ang4_19, 3, 3, 1
vbroadcasti128 m0, [r2]
pshufb m0, [intra_pred4_shuff19]
pmaddubsw m0, [c_ang4_mode_19]
pmulhrsw m0, [pw_1024]
packuswb m0, m0
INTRA_PRED_STORE_4x4
RET
INIT_YMM avx2
cglobal intra_pred_ang4_20, 3, 3, 1
vbroadcasti128 m0, [r2]
pshufb m0, [intra_pred4_shuff20]
pmaddubsw m0, [c_ang4_mode_20]
pmulhrsw m0, [pw_1024]
packuswb m0, m0
INTRA_PRED_STORE_4x4
RET
INIT_YMM avx2
cglobal intra_pred_ang4_21, 3, 3, 1
vbroadcasti128 m0, [r2]
pshufb m0, [intra_pred4_shuff21]
pmaddubsw m0, [c_ang4_mode_21]
pmulhrsw m0, [pw_1024]
packuswb m0, m0
INTRA_PRED_STORE_4x4
RET
INIT_YMM avx2
cglobal intra_pred_ang4_22, 3, 3, 1
vbroadcasti128 m0, [r2]
pshufb m0, [intra_pred4_shuff22]
pmaddubsw m0, [c_ang4_mode_22]
pmulhrsw m0, [pw_1024]
packuswb m0, m0
INTRA_PRED_STORE_4x4
RET
INIT_YMM avx2
cglobal intra_pred_ang4_23, 3, 3, 1
vbroadcasti128 m0, [r2]
pshufb m0, [intra_pred4_shuff23]
pmaddubsw m0, [c_ang4_mode_23]
pmulhrsw m0, [pw_1024]
packuswb m0, m0
INTRA_PRED_STORE_4x4
RET
INIT_YMM avx2
cglobal intra_pred_ang4_24, 3, 3, 1
vbroadcasti128 m0, [r2]
pshufb m0, [intra_pred_shuff_0_4]
pmaddubsw m0, [c_ang4_mode_24]
pmulhrsw m0, [pw_1024]
packuswb m0, m0
INTRA_PRED_STORE_4x4
RET
INIT_YMM avx2
cglobal intra_pred_ang4_25, 3, 3, 1
vbroadcasti128 m0, [r2]
pshufb m0, [intra_pred_shuff_0_4]
pmaddubsw m0, [c_ang4_mode_25]
pmulhrsw m0, [pw_1024]
packuswb m0, m0
INTRA_PRED_STORE_4x4
RET
;-----------------------------------------------------------------------------------
; void intra_filter_NxN(const pixel* references, pixel* filtered)
;-----------------------------------------------------------------------------------
INIT_XMM sse4
cglobal intra_filter_4x4, 2,4,5
mov r2b, byte [r0 + 8] ; topLast
mov r3b, byte [r0 + 16] ; LeftLast
; filtering top
pmovzxbw m0, [r0 + 0]
pmovzxbw m1, [r0 + 8]
pmovzxbw m2, [r0 + 16]
pshufb m4, m0, [intra_filter4_shuf0] ; [6 5 4 3 2 1 0 1] samples[i - 1]
palignr m3, m1, m0, 4
pshufb m3, [intra_filter4_shuf1] ; [8 7 6 5 4 3 2 9] samples[i + 1]
psllw m0, 1
paddw m4, m3
paddw m0, m4
paddw m0, [pw_2]
psrlw m0, 2
; filtering left
palignr m4, m1, m1, 14 ; [14 13 12 11 10 9 8 15] samples[i - 1]
pinsrb m4, [r0], 2 ; [14 13 12 11 10 9 0 15] samples[i + 1]
palignr m3, m2, m1, 4
pshufb m3, [intra_filter4_shuf1]
psllw m1, 1
paddw m4, m3
paddw m1, m4
paddw m1, [pw_2]
psrlw m1, 2
packuswb m0, m1
movu [r1], m0
mov [r1 + 8], r2b ; topLast
mov [r1 + 16], r3b ; LeftLast
RET
INIT_XMM sse4
cglobal intra_filter_8x8, 2,4,6
mov r2b, byte [r0 + 16] ; topLast
mov r3b, byte [r0 + 32] ; LeftLast
; filtering top
pmovzxbw m0, [r0 + 0]
pmovzxbw m1, [r0 + 8]
pmovzxbw m2, [r0 + 16]
pshufb m4, m0, [intra_filter4_shuf0] ; [6 5 4 3 2 1 0 1] samples[i - 1]
palignr m5, m1, m0, 2
pinsrb m5, [r0 + 17], 0 ; [8 7 6 5 4 3 2 9] samples[i + 1]
palignr m3, m1, m0, 14
psllw m0, 1
paddw m4, m5
paddw m0, m4
paddw m0, [pw_2]
psrlw m0, 2
palignr m4, m2, m1, 2
psllw m1, 1
paddw m4, m3
paddw m1, m4
paddw m1, [pw_2]
psrlw m1, 2
packuswb m0, m1
movu [r1], m0
; filtering left
pmovzxbw m1, [r0 + 24]
pmovzxbw m0, [r0 + 32]
palignr m4, m2, m2, 14
pinsrb m4, [r0], 2
palignr m5, m1, m2, 2
palignr m3, m1, m2, 14
palignr m0, m1, 2
psllw m2, 1
paddw m4, m5
paddw m2, m4
paddw m2, [pw_2]
psrlw m2, 2
psllw m1, 1
paddw m0, m3
paddw m1, m0
paddw m1, [pw_2]
psrlw m1, 2
packuswb m2, m1
movu [r1 + 16], m2
mov [r1 + 16], r2b ; topLast
mov [r1 + 32], r3b ; LeftLast
RET
INIT_XMM sse4
cglobal intra_filter_16x16, 2,4,6
mov r2b, byte [r0 + 32] ; topLast
mov r3b, byte [r0 + 64] ; LeftLast
; filtering top
pmovzxbw m0, [r0 + 0]
pmovzxbw m1, [r0 + 8]
pmovzxbw m2, [r0 + 16]
pshufb m4, m0, [intra_filter4_shuf0] ; [6 5 4 3 2 1 0 1] samples[i - 1]
palignr m5, m1, m0, 2
pinsrb m5, [r0 + 33], 0 ; [8 7 6 5 4 3 2 9] samples[i + 1]
palignr m3, m1, m0, 14
psllw m0, 1
paddw m4, m5
paddw m0, m4
paddw m0, [pw_2]
psrlw m0, 2
palignr m4, m2, m1, 2
psllw m5, m1, 1
paddw m4, m3
paddw m5, m4
paddw m5, [pw_2]
psrlw m5, 2
packuswb m0, m5
movu [r1], m0
pmovzxbw m0, [r0 + 24]
pmovzxbw m5, [r0 + 32]
palignr m3, m2, m1, 14
palignr m4, m0, m2, 2
psllw m1, m2, 1
paddw m3, m4
paddw m1, m3
paddw m1, [pw_2]
psrlw m1, 2
palignr m3, m0, m2, 14
palignr m4, m5, m0, 2
psllw m0, 1
paddw m4, m3
paddw m0, m4
paddw m0, [pw_2]
psrlw m0, 2
packuswb m1, m0
movu [r1 + 16], m1
; filtering left
pmovzxbw m1, [r0 + 40]
pmovzxbw m2, [r0 + 48]
palignr m4, m5, m5, 14
pinsrb m4, [r0], 2
palignr m0, m1, m5, 2
psllw m3, m5, 1
paddw m4, m0
paddw m3, m4
paddw m3, [pw_2]
psrlw m3, 2
palignr m0, m1, m5, 14
palignr m4, m2, m1, 2
psllw m5, m1, 1
paddw m4, m0
paddw m5, m4
paddw m5, [pw_2]
psrlw m5, 2
packuswb m3, m5
movu [r1 + 32], m3
pmovzxbw m5, [r0 + 56]
pmovzxbw m0, [r0 + 64]
palignr m3, m2, m1, 14
palignr m4, m5, m2, 2
psllw m1, m2, 1
paddw m3, m4
paddw m1, m3
paddw m1, [pw_2]
psrlw m1, 2
palignr m3, m5, m2, 14
palignr m4, m0, m5, 2
psllw m5, 1
paddw m4, m3
paddw m5, m4
paddw m5, [pw_2]
psrlw m5, 2
packuswb m1, m5
movu [r1 + 48], m1
mov [r1 + 32], r2b ; topLast
mov [r1 + 64], r3b ; LeftLast
RET
INIT_XMM sse4
cglobal intra_filter_32x32, 2,4,6
mov r2b, byte [r0 + 64] ; topLast
mov r3b, byte [r0 + 128] ; LeftLast
; filtering top
; 0 to 15
pmovzxbw m0, [r0 + 0]
pmovzxbw m1, [r0 + 8]
pmovzxbw m2, [r0 + 16]
pshufb m4, m0, [intra_filter4_shuf0] ; [6 5 4 3 2 1 0 1] samples[i - 1]
palignr m5, m1, m0, 2
pinsrb m5, [r0 + 65], 0 ; [8 7 6 5 4 3 2 9] samples[i + 1]
palignr m3, m1, m0, 14
psllw m0, 1
paddw m4, m5
paddw m0, m4
paddw m0, [pw_2]
psrlw m0, 2
palignr m4, m2, m1, 2
psllw m5, m1, 1
paddw m4, m3
paddw m5, m4
paddw m5, [pw_2]
psrlw m5, 2
packuswb m0, m5
movu [r1], m0
; 16 to 31
pmovzxbw m0, [r0 + 24]
pmovzxbw m5, [r0 + 32]
palignr m3, m2, m1, 14
palignr m4, m0, m2, 2
psllw m1, m2, 1
paddw m3, m4
paddw m1, m3
paddw m1, [pw_2]
psrlw m1, 2
palignr m3, m0, m2, 14
palignr m4, m5, m0, 2
psllw m2, m0, 1
paddw m4, m3
paddw m2, m4
paddw m2, [pw_2]
psrlw m2, 2
packuswb m1, m2
movu [r1 + 16], m1
; 32 to 47
pmovzxbw m1, [r0 + 40]
pmovzxbw m2, [r0 + 48]
palignr m3, m5, m0, 14
palignr m4, m1, m5, 2
psllw m0, m5, 1
paddw m3, m4
paddw m0, m3
paddw m0, [pw_2]
psrlw m0, 2
palignr m3, m1, m5, 14
palignr m4, m2, m1, 2
psllw m5, m1, 1
paddw m4, m3
paddw m5, m4
paddw m5, [pw_2]
psrlw m5, 2
packuswb m0, m5
movu [r1 + 32], m0
; 48 to 63
pmovzxbw m0, [r0 + 56]
pmovzxbw m5, [r0 + 64]
palignr m3, m2, m1, 14
palignr m4, m0, m2, 2
psllw m1, m2, 1
paddw m3, m4
paddw m1, m3
paddw m1, [pw_2]
psrlw m1, 2
palignr m3, m0, m2, 14
palignr m4, m5, m0, 2
psllw m0, 1
paddw m4, m3
paddw m0, m4
paddw m0, [pw_2]
psrlw m0, 2
packuswb m1, m0
movu [r1 + 48], m1
; filtering left
; 64 to 79
pmovzxbw m1, [r0 + 72]
pmovzxbw m2, [r0 + 80]
palignr m4, m5, m5, 14
pinsrb m4, [r0], 2
palignr m0, m1, m5, 2
psllw m3, m5, 1
paddw m4, m0
paddw m3, m4
paddw m3, [pw_2]
psrlw m3, 2
palignr m0, m1, m5, 14
palignr m4, m2, m1, 2
psllw m5, m1, 1
paddw m4, m0
paddw m5, m4
paddw m5, [pw_2]
psrlw m5, 2
packuswb m3, m5
movu [r1 + 64], m3
; 80 to 95
pmovzxbw m5, [r0 + 88]
pmovzxbw m0, [r0 + 96]
palignr m3, m2, m1, 14
palignr m4, m5, m2, 2
psllw m1, m2, 1
paddw m3, m4
paddw m1, m3
paddw m1, [pw_2]
psrlw m1, 2
palignr m3, m5, m2, 14
palignr m4, m0, m5, 2
psllw m2, m5, 1
paddw m4, m3
paddw m2, m4
paddw m2, [pw_2]
psrlw m2, 2
packuswb m1, m2
movu [r1 + 80], m1
; 96 to 111
pmovzxbw m1, [r0 + 104]
pmovzxbw m2, [r0 + 112]
palignr m3, m0, m5, 14
palignr m4, m1, m0, 2
psllw m5, m0, 1
paddw m3, m4
paddw m5, m3
paddw m5, [pw_2]
psrlw m5, 2
palignr m3, m1, m0, 14
palignr m4, m2, m1, 2
psllw m0, m1, 1
paddw m4, m3
paddw m0, m4
paddw m0, [pw_2]
psrlw m0, 2
packuswb m5, m0
movu [r1 + 96], m5
; 112 to 127
pmovzxbw m5, [r0 + 120]
pmovzxbw m0, [r0 + 128]
palignr m3, m2, m1, 14
palignr m4, m5, m2, 2
psllw m1, m2, 1
paddw m3, m4
paddw m1, m3
paddw m1, [pw_2]
psrlw m1, 2
palignr m3, m5, m2, 14
palignr m4, m0, m5, 2
psllw m5, 1
paddw m4, m3
paddw m5, m4
paddw m5, [pw_2]
psrlw m5, 2
packuswb m1, m5
movu [r1 + 112], m1
mov [r1 + 64], r2b ; topLast
mov [r1 + 128], r3b ; LeftLast
RET
INIT_YMM avx2
cglobal intra_filter_4x4, 2,4,4
mov r2b, byte [r0 + 8] ; topLast
mov r3b, byte [r0 + 16] ; LeftLast
; filtering top
pmovzxbw m0, [r0]
vpbroadcastw m2, xm0
pmovzxbw m1, [r0 + 8]
palignr m3, m0, m2, 14 ; [6 5 4 3 2 1 0 0] [14 13 12 11 10 9 8 0]
pshufb m3, [intra_filter4_shuf2] ; [6 5 4 3 2 1 0 1] [14 13 12 11 10 9 0 9] samples[i - 1]
palignr m1, m0, 4 ; [9 8 7 6 5 4 3 2]
palignr m1, m1, 14 ; [9 8 7 6 5 4 3 2]
psllw m0, 1
paddw m3, m1
paddw m0, m3
paddw m0, [pw_2]
psrlw m0, 2
packuswb m0, m0
vpermq m0, m0, 10001000b
movu [r1], xm0
mov [r1 + 8], r2b ; topLast
mov [r1 + 16], r3b ; LeftLast
RET
|
programs/oeis/288/A288213.asm | karttu/loda | 0 | 160626 | ; A288213: Fixed point of the mapping 00->0010, 1->011, starting with 00.
; 0,0,1,0,0,1,1,0,0,1,0,0,1,1,0,1,1,0,0,1,0,0,1,1,0,0,1,0,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,0,0,1,1,0,0,1,0,0,1,1,0,1,1,0,0,1,0,0,1,1,0,0,1,0,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,0,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,0,0,1,1,0,0,1,0,0,1,1,0,1,1,0,0,1,0,0,1,1,0,0,1,0,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,0,0,1,1,0,0,1,0,0,1,1,0,1,1,0,0,1,0,0,1,1,0,0,1,0,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,0,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,0,0,1,1,0,0,1,0,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,0,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,0,0,1,1,0,0,1,0
mov $1,2
cal $0,1954 ; Wythoff game.
gcd $0,2
add $1,$0
sub $1,3
|
Platform/UefiSeven/Int10hHandler.asm | cecekpawon/UefiSevenPkg | 0 | 169408 | <filename>Platform/UefiSeven/Int10hHandler.asm
;------------------------------------------------------------------------------
; @file
; A minimal Int10h stub that allows the Windows 7 SP1 default VGA driver to
; 'swithc' to the 1024x768x32 video mode on devices that do not have a VGA ROM
; or Int10h handler.
;
; Adapted from VbeShim.asm from the Qemu project.
;
; Copyright (c) 2020, <NAME>
; Copyright (c) 2016, <NAME>
; Copyright (c) 2014, Red Hat, Inc.
; Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>
;
; This program and the accompanying materials are licensed and made available
; under the terms and conditions of the BSD License which accompanies this
; distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
; WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
;------------------------------------------------------------------------------
; Uncomment the following to enable serial console output on COM1
;%define DEBUG
%macro DebugLog 1
%ifdef DEBUG
push si
mov si, %1
call SerialPrint
pop si
%endif
%endmacro
BITS 16
ORG 0
VbeInfo:
TIMES 256 nop ; this will be filled in by the efi shim
VbeModeInfo:
TIMES 256 nop ; this will be filled in by the efi shim
InterruptHandlerEntry:
; Main entry point for the interrupt handler
; http://wiki.osdev.org/BIOS#Common_functions
DebugLog StrInterruptHandlerEntry
cmp ax, 0x4f00
je GetInfo
cmp ax, 0x4f01
je GetModeInfo
cmp ax, 0x4f02
je SetMode
cmp ax, 0x4f03
je GetMode
cmp ax, 0x4f10
je GetPmCapabilities
cmp ax, 0x4f15
je ReadEdid
cmp ah, 0x00
je SetModeLegacy
DebugLog StrUnknownFunction
Hang:
jmp Hang
GetInfo:
; Function 00: Return Controller Information
; Inputs:
; AX = 0x4f00
; ES:DI = pointer to VESA_BIOS_EXTENSIONS_INFORMATION_BLOCK buffer
; Outputs:
; AX = return status
push es ; store registers on stack
push di
push ds
push si
push cx
DebugLog StrEnterGetInfo
push cs
pop ds ; load the code segment address to DS
mov si, VbeInfo ; load offset of VbeInfo from program start to SI
mov cx, 256 ; we want to copy 256 bytes
cld ; clear direction flag
rep movsb ; move 256 bytes of VbeInfo at DS:SI to buffer at ES:DI
pop cx ; restore registers from stack
pop si
pop ds
pop di
pop es
jmp Success ; ax=0x4f
GetModeInfo:
; Function 01: Return Mode Information
; Inputs:
; AX = 0x4f01
; CX = mode number
; ES:DI = pointer to VESA_BIOS_EXTENSIONS_MODE_INFORMATION_BLOCK buffer
; Outputs:
; AX = return status
push es ; store registers on stack
push di
push ds
push si
push cx
DebugLog StrEnterGetModeInfo
and cx, ~0x4000 ; clear potentially set LFB (linear frame buffer) bit in mode number
cmp cx, 0x00f1 ; offer information on only known mode
je GetKnownModeInfo1
DebugLog StrUnknownMode
jmp Hang
GetKnownModeInfo1:
push cs
pop ds ; load the code segment address to DS
mov si, VbeModeInfo ; load offset of VbeModeInfo from program start to SI
mov cx, 256 ; we want to copy 256 bytes
cld ; clear direction flag
rep movsb ; move 256 bytes of VbeModeInfo at DS:SI to buffer at ES:DI
pop cx ; restore registers from stack
pop si
pop ds
pop di
pop es
jmp Success ; ax=0x4f
SetMode:
; Function 02: Set Mode
; Inputs:
; AX = 0x4f02
; BX = desired mode to set
; ES:DI = pointer to VESA_BIOS_EXTENSIONS_CRTC_INFORMATION_BLOCK structure
; Outputs:
; AX = return status
push dx ; store registers on stack
push ax
DebugLog StrEnterSetMode
cmp bx, 0x40f1 ; 0x40f1 mode
; <15>=0 Clear display memory
; <14>=1 Use linear/flat frame buffer model
; <13:12>=00 Reserved (must be 0)
; <11>=0 Use current default refresh rate
; <10:9>00
; <8:0>=011110001 Mode Number 241 ???
; to identify available modes use sudo hwinfo --framebuffer
je SetKnownMode1
DebugLog StrUnknownMode
jmp Hang
SetKnownMode1:
; everything is done by the efi shim
pop ax ; restore registers from stack
pop dx
jmp Success ; ax=0x4f
GetMode:
; Function 03: Return Current Mode
; Inputs:
; AX = 0x4f03
; Outputs:
; AX = return status
; BX = current mode
DebugLog StrEnterGetMode
mov bx, 0x40f1
jmp Success ; ax=0x4f
GetPmCapabilities:
; Function 10: Get Power Management Capabilities
; Inputs:
; AX = 0x4f10
; BL = 0
; ES:DI = null pointer
; Outputs:
; AL = 0x4f if function is supported
; AH = 0 if successful, else failed
DebugLog StrGetPmCapabilities
jmp Unsupported ; ax=0x014f
ReadEdid:
; Function 15: implement VBE/DDC service
; Inputs:
; AX = 0x4f15
; BL = report VBE/DDC capabilities
; ES:DI = null pointer
; Outputs:
; AX = return status
; BH = approx. time in seconds to transfer EDID block
; BL = DDC level supported
DebugLog StrReadEdid
jmp Unsupported ; ax=0x014f
SetModeLegacy:
; Inputs:
; AH = 0x00
; AL = video mode
; Outputs:
; AL = video mode flag (20h for mode > 7, 30h for 0-5,7 and 3Fh for 6)
; Notes:
; We only pretend to do something here, don't set any modes.
DebugLog StrEnterSetModeLegacy
cmp al, 0x03 ; 80x25 chars @ 720x400x16
je SetKnownModeLegacy1
cmp al, 0x12 ; 80x30 chars @ 640x480x256
je SetKnownModeLegacy2
DebugLog StrUnknownMode
jmp Hang
SetKnownModeLegacy1:
mov al, 0x30 ; return success value
jmp SetModeLegacyDone
SetKnownModeLegacy2:
mov al, 0x20 ; return success value
SetModeLegacyDone:
DebugLog StrExitSuccess
iret
Success:
DebugLog StrExitSuccess
mov ax, 0x004f
iret
Unsupported:
DebugLog StrExitUnsupported
mov ax, 0x014f
iret
%ifdef DEBUG
SerialPrint:
pusha
push ds ; save original
push cs
pop ds
mov dx, 03F8h + 01h ;Disable all interrupts
mov al, 0000_0000b
out dx,al
mov dx, 03F8h + 03h ;Enable DLAB
mov al, 1000_0000b
out dx,al
mov dx, 03F8h + 00h ;Set divisor to 1 (lo byte) 115200 baud
mov al, 0000_0001b
out dx,al
mov dx, 03F8h + 01h ;(hi byte)
mov al, 0000_0000b
out dx,al
mov dx, 03F8h + 03h ; 8 bits, no parity, one stop bit
mov al, 0000_0011b
out dx,al
mov dx, 03F8h + 02h ; Enable FIFO, clear them, with 14-byte threshold
mov al, 1100_0111b
out dx,al
mov dx, 03F8h + 04h ; IRQs enabled, RTS/DSR set
mov al, 0000_1011b
out dx,al
mov dx, 03F8h + 03h ;Line Control Register: 0x3F8 + 0x3
in al, dx
and al, 0111_1111b ;Set DLAB=0
out dx,al
SerialPrintLoop:
mov dx, 03F8h + 05h ;Line Status Register: 0x3F8 + 0x5
in al, dx
test al, 0010_0000b ;Use bit 5 to see if THR is empty
jz SerialPrintLoop
lodsb
cmp al, 0
je SerialPrintDone
mov dx, 03F8h ; COM1
out dx, al
jmp SerialPrintLoop
SerialPrintDone:
pop ds ; restore original
popa
ret
StrExitSuccess:
db 'Exit', 0x0a, 0
StrExitUnsupported:
db 'Unsupported', 0x0a, 0
StrUnknownFunction:
db 'Unknown Function', 0x0a, 0
StrEnterGetInfo:
db 'GetInfo', 0x0a, 0
StrEnterGetModeInfo:
db 'GetModeInfo', 0x0a, 0
StrEnterGetMode:
db 'GetMode', 0x0a, 0
StrEnterSetMode:
db 'SetMode', 0x0a, 0
StrEnterSetModeLegacy:
db 'SetModeLegacy', 0x0a, 0
StrUnknownMode:
db 'Unknown Mode', 0x0a, 0
StrGetPmCapabilities:
db 'GetPmCapabilities', 0x0a, 0
StrReadEdid:
db 'ReadEdid', 0x0a, 0
StrInterruptHandlerEntry:
db 'InterruptHandlerEntry', 0x0a, 0
%endif
|
learn-antlr/src/main/antlr/com/github/tt4g/learn/antlr/TripleUnderscoreTokenLexer.g4 | tt4g/learn-antlr | 0 | 591 | /**
* Parse "___" ${IDENTIFIER} "___" pattern.
*/
lexer grammar TripleUnderscoreTokenLexer;
TRIPLE_UNDERSCORE_IDENTIFIER : TRIPLE_UNDERSCORE [a-z0-9]+ TRIPLE_UNDERSCORE ;
fragment TRIPLE_UNDERSCORE : UNDERSCORE UNDERSCORE UNDERSCORE;
fragment UNDERSCORE: '_' ;
|
src-raven/bbs-units.adb | BrentSeidel/BBS-Ada | 1 | 8733 | --
-- This is free and unencumbered software released into the public domain.
--
-- Anyone is free to copy, modify, publish, use, compile, sell, or
-- distribute this software, either in source code form or as a compiled
-- binary, for any purpose, commercial or non-commercial, and by any
-- means.
--
-- In jurisdictions that recognize copyright laws, the author or authors
-- of this software dedicate any and all copyright interest in the
-- software to the public domain. We make this dedication for the benefit
-- of the public at large and to the detriment of our heirs and
-- successors. We intend this dedication to be an overt act of
-- relinquishment in perpetuity of all present and future rights to this
-- software under copyright law.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-- IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- OTHER DEALINGS IN THE SOFTWARE.
--
-- For more information, please refer to <http://unlicense.org>
--
package body BBS.units with SPARK_Mode => on is
--
-- Get elementary math functions for floating point numbers
--
-- package float_functions is new Ada.Numerics.Generic_Elementary_Functions(float);
-- function "**"(Left, Right : float) return float
-- renames float_functions."**";
--
-- Since the conversion and operation routines are so simple, most have been
-- converted to expression functions. Occasionally, one may be left here
-- due to dependencies with partial type declarations.
--
-- Unit conversion routines. Most of these are pretty simple. Add as needed.
-- The conversion factors come from a variety of sources and definitions.
--
-- -------------------------------------------------------------------------
-- *** Distance conversions ***
--
--
-- Length functions
--
function "/"(Left : len_m; Right : Duration) return vel_m_s is
begin
return vel_m_s(Float(Left) / Float(Right));
end;
-- -------------------------------------------------------------------------
-- *** Area conversions ***
--
-- -------------------------------------------------------------------------
-- *** Volume conversions ***
--
-- -------------------------------------------------------------------------
-- *** Mass conversions ***
--
-- -------------------------------------------------------------------------
-- *** Force conversions ***
--
-- none
--
-- Force functions
--
function "*"(Left : mass_kg; Right : accel_m_s2) return force_n is
begin
return force_n(Float(Left) * Float(Right));
end;
--
function "*"(Left : accel_m_s2; Right : mass_kg) return force_n is
begin
return force_n(Float(Left) * Float(Right));
end;
--
function "/"(Left : force_n; Right : accel_m_s2) return mass_kg is
begin
return mass_kg(Float(Left) / Float(Right));
end;
--
function "/"(Left : force_n; Right : mass_kg) return accel_m_s2 is
begin
return accel_m_s2(Float(Left) / Float(Right));
end;
-- -------------------------------------------------------------------------
-- *** Temperature conversions ***
--
-- -------------------------------------------------------------------------
-- *** Pressure conversions ***
--
--
-- Given local pressure and altimeter setting, determine the pressure
-- altitude. Given local pressure and altitude, determine the altimeter
-- setting.
--
-- function pressure_altitude(pressure : press_p; altm : press_p)
-- return len_m is
-- begin
-- return len_m(44330.0 * (1.0 - (float(pressure)/float(altm))**float(1.0/5.255)));
-- end;
--
-- function altimeter(pressure : press_p; altitude : len_m) return press_p is
-- begin
-- return press_p(float(pressure)/(1.0 - (float(altitude)/44330.0)**float(5.255)));
-- end;
-- -------------------------------------------------------------------------
-- *** Velocity conversions ***
--
--
-- Velocity functions
--
function "/"(Left : vel_m_s; Right : Duration) return accel_m_s2 is
begin
return accel_m_s2(Float(Left) / Float(Right));
end;
-- -------------------------------------------------------------------------
-- *** Acceleration conversions ***
--
-- -------------------------------------------------------------------------
-- *** Angle conversions ***
--
-- -------------------------------------------------------------------------
-- *** Rotation rate conversions ***
--
-- -------------------------------------------------------------------------
-- *** Functions for Ohms law ***
--
-- -------------------------------------------------------------------------
-- *** Frequency and time conversions ***
--
end;
|
programs/oeis/168/A168212.asm | karttu/loda | 1 | 165204 | ; A168212: a(n) = 7*n - a(n-1) + 1 with n>1, a(1)=4.
; 4,11,11,18,18,25,25,32,32,39,39,46,46,53,53,60,60,67,67,74,74,81,81,88,88,95,95,102,102,109,109,116,116,123,123,130,130,137,137,144,144,151,151,158,158,165,165,172,172,179,179,186,186,193,193,200,200,207,207,214,214,221,221,228,228,235,235,242,242,249,249,256,256,263,263,270,270,277,277,284,284,291,291,298,298,305,305,312,312,319,319,326,326,333,333,340,340,347,347,354,354,361,361,368,368,375,375,382,382,389,389,396,396,403,403,410,410,417,417,424,424,431,431,438,438,445,445,452,452,459,459,466,466,473,473,480,480,487,487,494,494,501,501,508,508,515,515,522,522,529,529,536,536,543,543,550,550,557,557,564,564,571,571,578,578,585,585,592,592,599,599,606,606,613,613,620,620,627,627,634,634,641,641,648,648,655,655,662,662,669,669,676,676,683,683,690,690,697,697,704,704,711,711,718,718,725,725,732,732,739,739,746,746,753,753,760,760,767,767,774,774,781,781,788,788,795,795,802,802,809,809,816,816,823,823,830,830,837,837,844,844,851,851,858,858,865,865,872,872,879
mov $1,$0
add $1,1
div $1,2
mul $1,7
add $1,4
|
alloy4fun_models/trashltl/models/11/KyJ6s2hNnrzkfoHWa.als | Kaixi26/org.alloytools.alloy | 0 | 1773 | open main
pred idKyJ6s2hNnrzkfoHWa_prop12 {
always some f : File | f not in Trash until (eventually f in Trash => eventually f not in Trash)
}
pred __repair { idKyJ6s2hNnrzkfoHWa_prop12 }
check __repair { idKyJ6s2hNnrzkfoHWa_prop12 <=> prop12o } |
tarmi.ads | DerickEddington/tarmi | 0 | 7217 | <reponame>DerickEddington/tarmi
-- TODO: Figure-out the memory management issues... is it
-- possible to use only standard Ada facilities, or is an
-- additional GC unavoidable?
package Tarmi is
type Datum_R is abstract tagged null record;
type Datum is not null access constant Datum_R'Class;
type Pair_R is new Datum_R with
record
First : Datum;
Second : Datum;
end record;
type Pair is not null access constant Pair_R;
subtype String_Type is Standard.String;
Nil : constant Datum;
Ignore : constant Datum;
Not_Implemented : exception; -- TODO: remove when development done
private
type Singleton is new Datum_R with null record;
Nil_Obj : aliased constant Singleton := (null record);
Nil : constant Datum := Nil_Obj'Access;
Ignore_Obj : aliased constant Singleton := (null record);
Ignore : constant Datum := Ignore_Obj'Access;
end Tarmi;
|
src/implementation/cl-helpers.ads | flyx/OpenCLAda | 8 | 20254 | <reponame>flyx/OpenCLAda
--------------------------------------------------------------------------------
-- Copyright (c) 2013, <NAME> <<EMAIL>>
--
-- Permission to use, copy, modify, and/or distribute this software for any
-- purpose with or without fee is hereby granted, provided that the above
-- copyright notice and this permission notice appear in all copies.
--
-- THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-- WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-- ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-- WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-- ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-- OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
--------------------------------------------------------------------------------
with Ada.Text_IO;
with Interfaces.C;
with CL.Enumerations;
private package CL.Helpers is
generic
type Return_T is private;
type Parameter_T is (<>);
with function C_Getter (Object : System.Address;
Param : Parameter_T;
Value_Size : Size;
Value : System.Address;
Return_Size : Size_Ptr)
return Enumerations.Error_Code;
function Get_Parameter (Object : in CL_Object'Class;
Param : in Parameter_T) return Return_T;
pragma Inline (Get_Parameter);
generic
type Return_T is private;
type Parameter_T is (<>);
with function C_Getter (Object1 : System.Address;
Object2 : System.Address;
Param : Parameter_T;
Value_Size : Size;
Value : System.Address;
Return_Size : Size_Ptr)
return Enumerations.Error_Code;
function Get_Parameter2 (Object1 : in CL_Object'Class;
Object2 : in CL_Object'Class;
Param : in Parameter_T) return Return_T;
pragma Inline (Get_Parameter2);
generic
type Return_Element_T is private;
type Return_T is array (Positive range <>) of Return_Element_T;
type Parameter_T is (<>);
with function C_Getter (Object : System.Address;
Param : Parameter_T;
Value_Size : Size;
Value : System.Address;
Return_Size : Size_Ptr)
return Enumerations.Error_Code;
function Get_Parameters (Object : in CL_Object'Class;
Param : in Parameter_T) return Return_T;
pragma Inline (Get_Parameters);
generic
type Return_Element_T is private;
type Return_T is array (Positive range <>) of aliased Return_Element_T;
type Parameter_T is (<>);
with function C_Getter (Object : System.Address;
Param : Parameter_T;
Value_Size : Size;
Value : access Return_Element_T;
Return_Size : Size_Ptr)
return Enumerations.Error_Code;
function Get_Parameters_Safe (Object : in CL_Object'Class;
Param : in Parameter_T) return Return_T;
pragma Inline (Get_Parameters_Safe);
generic
type Parameter_T is (<>);
with function C_Getter (Object : System.Address;
Param : Parameter_T;
Value_Size : Size;
Value : access Interfaces.C.char_array;
Return_Size : Size_Ptr)
return Enumerations.Error_Code;
function Get_String (Object : in CL_Object'Class;
Param : in Parameter_T) return String;
pragma Inline (Get_String);
generic
type Return_Element_T is private;
type Return_T is array (Positive range <>) of Return_Element_T;
type Parameter_T is (<>);
with function C_Getter (Object1 : System.Address;
Object2 : System.Address;
Param : Parameter_T;
Value_Size : Size;
Value : System.Address;
Return_Size : Size_Ptr)
return Enumerations.Error_Code;
function Get_Parameters2 (Object1 : in CL_Object'Class;
Object2 : in CL_Object'Class;
Param : in Parameter_T) return Return_T;
pragma Inline (Get_Parameters2);
generic
type Return_Element_T is private;
type Return_T is array (Positive range <>) of Return_Element_T;
type Parameter_T is private;
with function C_Getter (Object : System.Address;
Param : Parameter_T;
Num_Entries : UInt;
Devices : System.Address;
Num_Devices : UInt_Ptr)
return Enumerations.Error_Code;
function Get_Objects (Object : in CL_Object'Class;
Param : in Parameter_T) return Return_T;
pragma Inline (Get_Objects);
-- Takes an error code and raises the corresponding exception
procedure Error_Handler (Error : Enumerations.Error_Code);
pragma Inline (Error_Handler);
generic
type Element_T is new CL_Object with private;
type Element_List_T is array (Positive range <>) of Element_T;
function Raw_List (List : Element_List_T) return Address_List;
generic
type Element_T is abstract new CL_Object with private;
type Element_List_T is array (Integer range <>) of access Element_T'Class;
function Raw_List_From_Polymorphic (List : Element_List_T) return Address_List;
generic
type Object_T is new Runtime_Object with private;
function New_Reference (Location : System.Address) return Object_T;
function Read_File (File : Ada.Text_IO.File_Type) return String;
-- converts a bit vector that is represented as record to a raw Bitfield
-- value. Apart from the conversion itself, this function fills all unused
-- bits with zeros, because the OpenCL interface requires bitfields to be
-- zero at all bits that are not defined to hold a value.
generic
type Bit_Vector_Record is private;
Used_Bits : Natural;
function Record_To_Bitfield (Bit_Vector : Bit_Vector_Record) return Bitfield;
end CL.Helpers;
|
audio tools/ab_Squirrel3 Public/sound.asm | langel/pce-dev-kit | 1 | 96792 | ;-----------------------------------------------------------------------------
; sound.asm - the squirrel MML player, which can be used to control the psg
;-----------------------------------------------------------------------------
; modified mar 2010 by <NAME>.
; Copyright 2010 by <NAME>. All rights reserved
;.............................................................................
; this file should contain the PSG_BIOS dispatch routine and the player
; routine. The actual PSG_BIOS functions are in a different file and page, to
; minimize the code space used in the irq handler (startup) page
;*****************************************************************************
; this is the actual psg-bios interface. All PSG_BIOS functions are called from
; here.
; Note that the actual functions may be in a different page of memory; hence,
; we have to map them in before we call them. All PSG_BIOS functions MUST
; reside in the same page of memory.
;-----------------------------------------------------------------------------------
; IN: _DH = function number
; OUT: _AX = function return value (if any)
; USE: _X and _Y are preserved
; _A is trashed
;............................................................................
; I'm not sure if this is the correct name or not, but it should work
psg_bios:
;------------------------------------------------------------------------
; save contents of X and Y registers, so they are not lost
phx ; save contents of X register
phy ; save contents of Y register
;------------------------------------------------------------------------
; this maps the bios functions into the cpu address space.
tma #PAGE(psgOn) ; get page number for code in 'our' area
pha ; save it
lda #BANK(psgOn) ; load page number for our code.
tam #PAGE(psgOn) ; map the code in
;------------------------------------------------------------------------
; validate function number
lda <_dh ; get function number
cmp #psgBiosEntries ; in valid range ?
bcs .psgBadParam ; skip call if out of range
;------------------------------------------------------------------------
; this calls the actual function code, via indirection.
asl A ; 2 bytes per address
tax ; place offset into index register
lda <_al ; get parameter
jsr psgBiosCall ; call the function from the table, as a sub-routine
;------------------------------------------------------------------------
; restore the original code that we mapped out
.psgBadParam:
tax ; save any return value in X.
pla ; get page number for original code
tam #PAGE(psgOn) ; map original code back in
txa ; restore the original return value
;------------------------------------------------------------------------
; restore original register values
ply
plx
rts
;----------------------------------------------------------------------------------------
; this is used to call the actual bios functions.
;----------------------------------------------------------------------------------------
psgBiosCall:
jmp [psgBiosTable,X]
;----------------------------------------------------------------------------------------
; the PSG-BIOS functions. The table needs to be in this page, so we can call them
; after we map them in. (NOTE: the actual functions MAY be in a different page)
;----------------------------------------------------------------------------------------
psgBiosTable:
.dw psgOn ; psg_on (00)
.dw psgOff ; psg_off (01)
.dw psgInit ; psg_init (02)
.dw psgBank ; psg_bank (03)
.dw psgTrack ; psg_track (04)
.dw psgWave ; psg_wave (05)
.dw psgEnv ; psg_env (06)
.dw psgFM ; psg_fm (07)
.dw psgPE ; psg_pe (08)
.dw psgPC ; psg_pc (09)
.dw psgSetTempo ; psg_settempo (0a)
.dw psgPlay ; psg_play (0b)
.dw psgMStat ; psg_mstat (0c)
.dw psgSStat ; psg_sstat (0d)
.dw psgMStop ; psg_mstop (0e)
.dw psgSStop ; psg_sstop (0f)
.dw psgAStop ; psg_astop (10)
.dw psgMvOff ; psg_mvoff (11)
.dw psgCont ; psg_cont (12)
.dw psgFadeOut ; psg_fdout (13)
.dw psgDCnt ; psg_dcnt (14)
psgBiosTableEnd = * ; table end is here
psgBiosEntries = (psgBiosTableEnd - psgBiosTable) / 2
;-----------------------------------------------------------------------------------------------
; this brings in the psg_bios functions. As promised, they are in a seperate bank.
;-----------------------------------------------------------------------------------------------
.bank PSG_BANK,"PSG Driver"
.include "main\PsgBiosFuncs.asm"
;...............................................................................................
; These are the driver rountines. Note that it's pretty big, which is why
; we go through all the hoops to run it from the non-fixed page :-)
;...............................................................................................
; this brings in the actual main track driver routine pieces.
;...............................................................................................
.include "main\psgDrive.asm" ; the main track driver routine
.include "main\mmlParse.asm" ; mml data parser
.include "main\bytecodes.asm" ; mml operations
.include "main\volume.asm" ; volume control
.include "main\drums.asm" ; percussion / noise control
.include "main\adsr.asm" ; volume envelope handler
.include "main\freqEnv.asm" ; frequency processing
.include "main\fade.asm" ; fade-out processing.
.include "main\output.asm" ; output to hardware
;...............................................................................................
; this brings in the actual sub track driver routine pieces.
;...............................................................................................
.include "sub\psgDrive.asm"
.include "sub\mmlParse.asm"
.include "sub\bytecodes.asm"
.include "sub\volume.asm"
.include "sub\drums.asm"
.include "sub\adsr.asm"
.include "sub\freqEnv.asm"
.include "sub\fade.asm"
.include "sub\output.asm"
;...............................................................................................
; the data tables we use.
.include "data\freqTable.inc"
.include "data\tempoTable.inc"
.include "data\envelopes.inc"
.include "data\waveTable.inc"
;
; now, return context to bank established in
; file which included this
;
.bank START_BANK
|
tests/src/reference_qoi.ads | joffreyhuguet/qoi-ada | 7 | 21896 | with System;
with Interfaces.C;
with Interfaces.C.Strings;
with System.Storage_Elements; use System.Storage_Elements;
with QOI;
package Reference_QOI is
type Ref_Desc is record
width : Interfaces.C.unsigned;
height : Interfaces.C.unsigned;
channels : Interfaces.C.char;
colorspace : Interfaces.C.char;
end record
with Convention => C;
type Ref_Desc_Acc is access all Ref_Desc;
function Encode (Data : System.Address;
Desc : not null Ref_Desc_Acc;
Out_Len : not null access Interfaces.C.int)
return System.Address;
pragma Import (C, Encode, "qoi_encode");
function Check_Encode (Pix : Storage_Array;
Desc : QOI.QOI_Desc;
Output : Storage_Array)
return Boolean;
function Decode (Data : System.Address;
Size : Interfaces.C.int;
Desc : not null Ref_Desc_Acc;
Channels : Interfaces.C.int)
return System.Address;
pragma Import (C, Decode, "qoi_decode");
function Check_Decode (Data : Storage_Array;
Out_Desc : QOI.QOI_Desc;
Out_Data : Storage_Array)
return Boolean;
end Reference_QOI;
|
grammarlang/grammarlang.g4 | matteoloca/ll1-validator | 1 | 5785 | grammar grammarlang;
rulelist: start_symbol? rule_+ EOF;
start_symbol: START_SYMBOL_KEYWORD SYMBOL SEMICOLON;
rule_: l ASSIGN r SEMICOLON;
l: SYMBOL;
r: SYMBOL*;
START_SYMBOL_KEYWORD: '#start_symbol';
ASSIGN: '->' | '=>';
SEMICOLON: ';';
SYMBOL: ('A' ..'Z' | 'a' .. 'z' | '0' ..'9' | '_')+;
COMMENT: ('//' ~[\r\n]* (('\r'? '\n') | EOF) | '/*' .*? '*/') -> skip;
WS: [ \r\n\t] -> skip;
|
Arquitectura de computadores I/Proyecto 1/compiler/ASMcode/drawSomething.asm | Arturok/TEC | 0 | 175741 | <reponame>Arturok/TEC<gh_stars>0
.data
frameBuffer:.space 0x80000 ; frame buffer address
bmp: .word 0x10000100
bmpwidth: .word 256
bmpheight: .word 2
color: .word 0xFFFFFF
pixeldot: .word 2
#lines: .float
.text
main:
la
la $s0, 100
la $s1, 80
la $s2, 150
la $s3, 120
la $t0, pixeldot
move $s1, $t1
move $s0, $t2
sub $t5, $t1, $t0 # deltax
sub $t6, $t3, $t2 #deltay
sll $t6, $t6, 2
sub $t7, $t6, $t5 # d
lw $t0, color
move $t0, $a0
addi $s0, $s0, 1
bgt $s0, $t8, addcolour
addcolour:
lw $t0, color
move $t0, $s0
addmorecolour:
lw $t0, color
move $t0, $s2
jal loop
setpixel:
lw $a3, bmp
lw $a2, bmpheight
lw $a1, bmpwidth
slt $s0, $s0, $a1
beq $s0, $t8, addonx
slt $s2, $s2, $a2
beq $s2, $t8, addony
lw $t0, color
move $t0, $s0
lw $t0, color
move $t0, $s2
jal drawpix
addonx:
addi $s0, $s0, 1
addony:
addi $s2, $s2, 1
drawpix:
li $t0, 0x10000100
lw $a3, bmp
lw $a2, bmpheight
lw $a1, bmpwidth
sll $s2, $s2, 1
add $t4, $s2, $s0
sll $t4, $t4, 2
add $t4, $t4, $t0
lw $a1, color
sw $a1, ($t4)
loop:
bgt $t7, $t4, increment
jal decrement
nop
increment:
lw $t0, color
move $t0, $s2
addi $s2, $s2, 1
bgt $s2, $t8, addmorecolour
sll $t5, $t5, 2
sub $t7, $t7, $t5
jal exit
decrement:
add $t7, $t7, $t6
jal exit
exit:
li $v0, 10
syscall
Printline:
li $v0, 4
li $a0, 0x1000
syscall
|
programs/oeis/171/A171891.asm | neoneye/loda | 22 | 104160 | <gh_stars>10-100
; A171891: 1 and all numbers >= 10.
; 1,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77
mov $1,$0
add $0,9
lpb $0
mul $0,$1
add $0,1
lpe
|
programs/oeis/156/A156778.asm | neoneye/loda | 22 | 242390 | <gh_stars>10-100
; A156778: n*A007504(n)/2 = n*(sum of first n primes)/2
; 0,1,5,15,34,70,123,203,308,450,645,880,1182,1547,1967,2460,3048,3740,4509,5396,6390,7476,8701,10051,11556,13250,15093,17064,19194,21460,23895,26660,29616,32802,36159,39830,43686,47804,52193,56823,61740
mov $1,$0
seq $1,7504 ; Sum of the first n primes.
mul $0,$1
div $0,2
|
lib/am335x_sdk/ti/csl/arch/c7x/src/csl_c7xmisc.asm | brandonbraun653/Apollo | 2 | 90855 | ;;*****************************************************************************
;; Copyright (C) 2018 Texas Instruments Incorporated - http:;;www.ti.com/
;;
;; Redistribution and use in source and binary forms, with or without
;; modification, are permitted provided that the following conditions
;; are met:
;;
;; Redistributions of source code must retain the above copyright
;; notice, this list of conditions and the following disclaimer.
;;
;; Redistributions in binary form must reproduce the above copyright
;; notice, this list of conditions and the following disclaimer in the
;; documentation and/or other materials provided with the
;; distribution.
;;
;; Neither the name of Texas Instruments Incorporated nor the names of
;; its contributors may be used to endorse or promote products derived
;; from this software without specific prior written permission.
;;
;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
;; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
;; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
;; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
;; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
;; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
;; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
;; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
;; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
;; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;*****************************************************************************
.global CSL_c7xL1PCacheInvalidateAll
CSL_c7xL1PCacheInvalidateAll:
IINVAL 0x3 ;; CPU instruction to invalidate all L1P content
RET .B1
;; uint64_t CSL_c7xSecSupv2NonSecSupv(void);
.global CSL_c7xSecSupv2NonSecSupv
CSL_c7xSecSupv2NonSecSupv:
;; Allow all events to be handled as interrupts in non-secure mode
MVK64 .L1 0h, A2
MVC .S1 A2, ECLMR
MVK64 .L1 0h, A2
MVC .S1 A2, EASGR
;; now switch to non-secure supervisor mode
MVC .S1 TSR, A1
MVK64 .L1 0fffffffffffffff8h, A2 ;; save all bits except [2:0]
ANDD .L1 A1, A2, A3
ORD .L1 A3, 03h, A3
MVC .S1 RP, A2
MVK64 .L1 1, A4
RETE .S1 A2, A3
|
oeis/021/A021891.asm | neoneye/loda-programs | 11 | 166668 | ; A021891: Decimal expansion of 1/887.
; Submitted by Jon Maiga
; 0,0,1,1,2,7,3,9,5,7,1,5,8,9,6,2,7,9,5,9,4,1,3,7,5,4,2,2,7,7,3,3,9,3,4,6,1,1,0,4,8,4,7,8,0,1,5,7,8,3,5,4,0,0,2,2,5,4,7,9,1,4,3,1,7,9,2,5,5,9,1,8,8,2,7,5,0,8,4,5,5,4,6,7,8,6,9,2,2,2,0,9,6,9,5,6,0,3,1
add $0,1
mov $2,10
pow $2,$0
div $2,887
mov $0,$2
mod $0,10
|
gnutls/nettle/arm/v6/sha1-compress.asm | TheShellLand/crossover-source | 0 | 179992 | C arm/v6/sha1-compress.asm
ifelse(<
Copyright (C) 2013 <NAME>
This file is part of GNU Nettle.
GNU Nettle is free software: you can redistribute it and/or
modify it under the terms of either:
* the GNU Lesser General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your
option) any later version.
or
* the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your
option) any later version.
or both in parallel, as here.
GNU Nettle is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received copies of the GNU General Public License and
the GNU Lesser General Public License along with this program. If
not, see http://www.gnu.org/licenses/.
>)
.file "sha1-compress.asm"
.arch armv6
define(<STATE>, <r0>)
define(<INPUT>, <r1>)
define(<SA>, <r2>)
define(<SB>, <r3>)
define(<SC>, <r4>)
define(<SD>, <r5>)
define(<SE>, <r6>)
define(<T0>, <r7>)
define(<SHIFT>, <r8>)
define(<WPREV>, <r10>)
define(<W>, <r12>)
define(<K>, <lr>)
C FIXME: Could avoid a mov with even and odd variants.
define(<LOAD>, <
ldr T0, [INPUT], #+4
sel W, WPREV, T0
ror W, W, SHIFT
mov WPREV, T0
IF_LE(< rev W, W>)
str W, [SP,#eval(4*$1)]
>)
define(<EXPN>, <
ldr W, [sp, #+eval(4*$1)]
ldr T0, [sp, #+eval(4*(($1 + 2) % 16))]
eor W, W, T0
ldr T0, [sp, #+eval(4*(($1 + 8) % 16))]
eor W, W, T0
ldr T0, [sp, #+eval(4*(($1 + 13) % 16))]
eor W, W, T0
ror W, W, #31
str W, [sp, #+eval(4*$1)]
>)
C F1(B,C,D) = D^(B&(C^D))
C ROUND1(A,B,C,D,E)
define(<ROUND1>, <
eor T0, $3, $4
add $5, $5, K
and T0, T0, $2
add $5, $5, $1, ror #27
eor T0, T0, $4
add $5, $5, W
ror $2, $2, #2
add $5, $5, T0
>)
C F2(B,C,D) = B^C^D
define(<ROUND2>, <
eor T0, $2, $4
add $5, $5, K
eor T0, T0, $3
add $5, $5, $1, ror #27
add $5, $5, W
ror $2, $2, #2
add $5, $5, T0
>)
C F3(B,C,D) = (B&C) | (D & (B|C)) = (B & (C ^ D)) + (C & D)
define(<ROUND3>, <
eor T0, $3, $4
add $5, $5, K
and T0, T0, $2
add $5, $5, $1, ror #27
add $5, $5, T0
add $5, $5, W
and T0, $3, $4
ror $2, $2, #2
add $5, $5, T0
>)
C void nettle_sha1_compress(uint32_t *state, const uint8_t *input)
.text
.align 2
.LK1:
.int 0x5A827999
.LK2:
.int 0x6ED9EBA1
.LK3:
.int 0x8F1BBCDC
PROLOGUE(nettle_sha1_compress)
push {r4,r5,r6,r7,r8,r10,lr}
sub sp, sp, #64
C Sets SHIFT to 8*low bits of input pointer. Sets up GE flags
C as follows, corresponding to bytes to be used from WPREV
C SHIFT 0 8 16 24
C CPSR.GE 0000 1110 1100 1000
ands SHIFT, INPUT, #3
and INPUT, INPUT, $-4
ldr WPREV, [INPUT]
addne INPUT, INPUT, #4 C Unaligned input
lsl SHIFT, SHIFT, #3
mov T0, #0
movne T0, #-1
IF_LE(< lsl W, T0, SHIFT>)
IF_BE(< lsr W, T0, SHIFT>)
uadd8 T0, T0, W C Sets APSR.GE bits
C on BE rotate right by 32-SHIFT bits
C because there is no rotate left
IF_BE(< rsb SHIFT, SHIFT, #32>)
ldr K, .LK1
ldm STATE, {SA,SB,SC,SD,SE}
LOAD( 0) ROUND1(SA, SB, SC, SD, SE)
LOAD( 1) ROUND1(SE, SA, SB, SC, SD)
LOAD( 2) ROUND1(SD, SE, SA, SB, SC)
LOAD( 3) ROUND1(SC, SD, SE, SA, SB)
LOAD( 4) ROUND1(SB, SC, SD, SE, SA)
LOAD( 5) ROUND1(SA, SB, SC, SD, SE)
LOAD( 6) ROUND1(SE, SA, SB, SC, SD)
LOAD( 7) ROUND1(SD, SE, SA, SB, SC)
LOAD( 8) ROUND1(SC, SD, SE, SA, SB)
LOAD( 9) ROUND1(SB, SC, SD, SE, SA)
LOAD(10) ROUND1(SA, SB, SC, SD, SE)
LOAD(11) ROUND1(SE, SA, SB, SC, SD)
LOAD(12) ROUND1(SD, SE, SA, SB, SC)
LOAD(13) ROUND1(SC, SD, SE, SA, SB)
LOAD(14) ROUND1(SB, SC, SD, SE, SA)
LOAD(15) ROUND1(SA, SB, SC, SD, SE)
EXPN( 0) ROUND1(SE, SA, SB, SC, SD)
EXPN( 1) ROUND1(SD, SE, SA, SB, SC)
EXPN( 2) ROUND1(SC, SD, SE, SA, SB)
EXPN( 3) ROUND1(SB, SC, SD, SE, SA)
ldr K, .LK2
EXPN( 4) ROUND2(SA, SB, SC, SD, SE)
EXPN( 5) ROUND2(SE, SA, SB, SC, SD)
EXPN( 6) ROUND2(SD, SE, SA, SB, SC)
EXPN( 7) ROUND2(SC, SD, SE, SA, SB)
EXPN( 8) ROUND2(SB, SC, SD, SE, SA)
EXPN( 9) ROUND2(SA, SB, SC, SD, SE)
EXPN(10) ROUND2(SE, SA, SB, SC, SD)
EXPN(11) ROUND2(SD, SE, SA, SB, SC)
EXPN(12) ROUND2(SC, SD, SE, SA, SB)
EXPN(13) ROUND2(SB, SC, SD, SE, SA)
EXPN(14) ROUND2(SA, SB, SC, SD, SE)
EXPN(15) ROUND2(SE, SA, SB, SC, SD)
EXPN( 0) ROUND2(SD, SE, SA, SB, SC)
EXPN( 1) ROUND2(SC, SD, SE, SA, SB)
EXPN( 2) ROUND2(SB, SC, SD, SE, SA)
EXPN( 3) ROUND2(SA, SB, SC, SD, SE)
EXPN( 4) ROUND2(SE, SA, SB, SC, SD)
EXPN( 5) ROUND2(SD, SE, SA, SB, SC)
EXPN( 6) ROUND2(SC, SD, SE, SA, SB)
EXPN( 7) ROUND2(SB, SC, SD, SE, SA)
ldr K, .LK3
EXPN( 8) ROUND3(SA, SB, SC, SD, SE)
EXPN( 9) ROUND3(SE, SA, SB, SC, SD)
EXPN(10) ROUND3(SD, SE, SA, SB, SC)
EXPN(11) ROUND3(SC, SD, SE, SA, SB)
EXPN(12) ROUND3(SB, SC, SD, SE, SA)
EXPN(13) ROUND3(SA, SB, SC, SD, SE)
EXPN(14) ROUND3(SE, SA, SB, SC, SD)
EXPN(15) ROUND3(SD, SE, SA, SB, SC)
EXPN( 0) ROUND3(SC, SD, SE, SA, SB)
EXPN( 1) ROUND3(SB, SC, SD, SE, SA)
EXPN( 2) ROUND3(SA, SB, SC, SD, SE)
EXPN( 3) ROUND3(SE, SA, SB, SC, SD)
EXPN( 4) ROUND3(SD, SE, SA, SB, SC)
EXPN( 5) ROUND3(SC, SD, SE, SA, SB)
EXPN( 6) ROUND3(SB, SC, SD, SE, SA)
EXPN( 7) ROUND3(SA, SB, SC, SD, SE)
EXPN( 8) ROUND3(SE, SA, SB, SC, SD)
EXPN( 9) ROUND3(SD, SE, SA, SB, SC)
EXPN(10) ROUND3(SC, SD, SE, SA, SB)
EXPN(11) ROUND3(SB, SC, SD, SE, SA)
ldr K, .LK4
EXPN(12) ROUND2(SA, SB, SC, SD, SE)
EXPN(13) ROUND2(SE, SA, SB, SC, SD)
EXPN(14) ROUND2(SD, SE, SA, SB, SC)
EXPN(15) ROUND2(SC, SD, SE, SA, SB)
EXPN( 0) ROUND2(SB, SC, SD, SE, SA)
EXPN( 1) ROUND2(SA, SB, SC, SD, SE)
EXPN( 2) ROUND2(SE, SA, SB, SC, SD)
EXPN( 3) ROUND2(SD, SE, SA, SB, SC)
EXPN( 4) ROUND2(SC, SD, SE, SA, SB)
EXPN( 5) ROUND2(SB, SC, SD, SE, SA)
EXPN( 6) ROUND2(SA, SB, SC, SD, SE)
EXPN( 7) ROUND2(SE, SA, SB, SC, SD)
EXPN( 8) ROUND2(SD, SE, SA, SB, SC)
EXPN( 9) ROUND2(SC, SD, SE, SA, SB)
EXPN(10) ROUND2(SB, SC, SD, SE, SA)
EXPN(11) ROUND2(SA, SB, SC, SD, SE)
EXPN(12) ROUND2(SE, SA, SB, SC, SD)
EXPN(13) ROUND2(SD, SE, SA, SB, SC)
EXPN(14) ROUND2(SC, SD, SE, SA, SB)
EXPN(15) ROUND2(SB, SC, SD, SE, SA)
C Use registers we no longer need.
ldm STATE, {INPUT,T0,SHIFT,W,K}
add SA, SA, INPUT
add SB, SB, T0
add SC, SC, SHIFT
add SD, SD, W
add SE, SE, K
add sp, sp, #64
stm STATE, {SA,SB,SC,SD,SE}
pop {r4,r5,r6,r7,r8,r10,pc}
EPILOGUE(nettle_sha1_compress)
.LK4:
.int 0xCA62C1D6
|
mode.asm | shailesh4/findMode_MIPS | 0 | 21920 | <gh_stars>0
#-------------------------------------------------------------------------------
#author: <NAME>
#data : 2019,05,14
#description : example program for reading, modifying and getting a Green Component from source files
#-------------------------------------------------------------------------------
#only 24-bits 600x50 pixels BMP files are supported
.eqv BMP_FILE_SIZE 122880
#########################################################################################################################################################
# source 1 to source 4 82,62,77,82 62-82
# source 5 to source 8 104,103,132,150 103-150
# source 9 to source 12 185,159,182,164 159-185
#########################################################################################################################################################
.data
#space for the 600x50px 24-bits bmp image
.align 4
res: .space 2
image: .space BMP_FILE_SIZE
s1: .asciiz "source1.bmp"
s2: .asciiz "source2.bmp"
s3: .asciiz "source3.bmp"
s4: .asciiz "source4.bmp"
s5: .asciiz "source5.bmp"
s6: .asciiz "source6.bmp"
s7: .asciiz "source7.bmp"
s8: .asciiz "source8.bmp"
s9: .asciiz "source9.bmp"
s10: .asciiz "source10.bmp"
s11: .asciiz "source11.bmp"
s12: .asciiz "source12.bmp"
files: .word s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12
iterator: .word 0
no_of_files: .word 11
temp_range: .word 0:3
.word 0
temp_iterator: .word 0
custom_ranges: .word 0:5
.word 0
custom_iterator: .word 0
message: .asciiz " \n "
message1: .asciiz "adz"
message2: .asciiz "pea"
message3: .asciiz "qui"
errors: .asciiz "There was an error while opening the file. Terminating the Program..."
list_of_pixels: .word 0:255
.word 0
fname: .asciiz "source2.bmp"
.text
.globl read_bmp
.globl get_pixels
.globl get_mode
main:
la $s0, files # initialize files
lw $s5, iterator
start:
lw $s4, no_of_files # load again after iteration s4
bgt $s5,$s4, exit
sll $s7, $s5, 2 # To go to the next file
addu $s7, $s7, $s0 # remember to increment s7
addi $s5,$s5,1
li $v0, 4
la $a0, message
syscall
li $v0, 4
la $a0, message
syscall
li $v0, 4
lw $a0, ($s7)
syscall
jal read_bmp
jal get_pixels
jal get_mode
move $a0, $v0
jal get_description
jal clear_list
j start
exit:
#jal get_custom_ranges
li $v0,10 #Terminate the program
syscall
# ============================================================================
read_bmp:
#description:
# reads the contents of a bmp file into memory
#arguments:
# none
#return value: none
sub $sp, $sp, 4 #push $ra to the stack
sw $ra,4($sp)
sub $sp, $sp, 4 #push $s1
sw $s1, 4($sp)
#open file
lw $v0, 0($s7)
la $a0, ($v0) #file name
li $v0, 13
#la $a0, fname
li $a1, 0 #flags: 0-read file
li $a2, 0 #mode: ignored
syscall
move $s1, $v0 # save the file descriptor
#li $v0, 4
#lw $a0, 0($s7) $print the file name
#la $a0, ($a0)
#syscall
#check for errors - if the file was opened
#...
blt $v0,0, error
j no_error
error:
li $v0, 4
la $a0, message
syscall
li $v0, 4
la $a0, errors
syscall
li $v0, 4
la $a0, message
syscall
j exit
#read file
no_error:
li $v0, 14
move $a0, $s1
la $a1, image
li $a2, BMP_FILE_SIZE
syscall
#close file
li $v0, 16
move $a0, $s1
syscall
lw $s1, 4($sp) #restore (pop) $s1
add $sp, $sp, 4
lw $ra, 4($sp) #restore (pop) $ra
add $sp, $sp, 4
jr $ra
# ============================================================================
# ============================================================================
get_pixels:
#description:
# returns color of specified pixel
#arguments:
# $a0 - x coordinate
# $a1 - y coordinate - (0,0) - bottom left corner
#return value:
# $v0 - 0RGB - pixel color
#Initialize the registers
addiu $t0, $zero, 0
addiu $t1, $zero, 0
addiu $t2, $zero, 0
addiu $t3, $zero, 0
addiu $t7, $zero, 0
addiu $t6, $zero, 0
addiu $t5, $zero, 0
sub $sp, $sp, 4 #push $ra to the stack
sw $ra,4($sp)
la $t1, image + 10 #adress of file offset to pixel array
lw $t2, ($t1) #file offset to pixel array in $t2
la $s6, image + 34 # size of the image
lw $s4, ($s6)
#li $v0, 1
#move $a0, $t2 #printing the size of the image
#syscall
#li $v0, 4
#la $a0, message
#syscall
la $t1, image #adress of bitmap
add $t2, $t1, $t2 #adress of pixel array in $t2
la $t9, list_of_pixels
while:
#pixel address calculation
bgt $t0,$s4 , exit_while
lbu $v0,1($t2) #load G
move $t3, $v0 #if you printed the pixels, change v0 to a different register
move $t6, $t9
move $t7, $t3
#add $t7, $t7, -1
sll $t7, $t7, 2
addu $t6, $t6, $t7
lw $t5, 0($t6)
addu $t5, $t5, 1
sw $t5, 0($t6) #in this block we increment our counter of particular index of array
add $t2, $t2, 3 #pixel address
addiu $t0, $t0, 3
j while
#get color
exit_while:
lw $ra, 4($sp) #restore (pop) $ra
add $sp, $sp, 4
jr $ra
# ============================================================================
get_mode:
# It will return the highest value in the array of 256 values that we get from getPixels program
sub $sp, $sp, 4 #push $ra to the stack
sw $ra,4($sp)
la $t1, list_of_pixels
addiu $t0, $zero, 0
addiu $t7, $zero, 0
addiu $t6, $zero, 0
addiu $t5, $zero, 0
addiu $t2, $zero, 0
mode_while:
#pixel address calculation
beq $t0, 256, exit_mode_while
move $t5, $t0
sll $t5, $t5, 2 #every number takes 4 bytes so we shift it (offset)
addu $t5, $t5, $t1
lw $t2, ($t5)
bgt $t2, $t7, swap
addiu $t0, $t0, 1
j mode_while
swap:
#addiu $t7,$zero,0
#move $t7, $t9
move $t7, $t2
move $t6, $t0
addiu $t0, $t0, 1
j mode_while
#get color
exit_mode_while:
addiu $t0, $zero, 0
li $v0, 4
la $a0, message
syscall
li $v0, 1
move $a0, $t6
syscall
li $v0, 4
la $a0, message
syscall
j deal_with_temp
exit_mode:
move $v0, $t6
lw $ra, 4($sp) #restore (pop) $ra
add $sp, $sp, 4
jr $ra
deal_with_temp:
la $t7, temp_range
la $t5, temp_iterator
lw $t3, ($t5)
sll $t4, $t3, 2
addu $t4, $t4, $t7
sw $t6, 0($t4)
addi $t3, $t3, 1
bgt $t3, 3, zero_iterator
sw $t3, ($t5)
j exit_mode
zero_iterator:
addiu $t3, $zero, 0
sw $t3, ($t5)
jal put_custom_ranges
j exit_mode
# ============================================================================
put_custom_ranges:
sub $sp, $sp, 4 #push $ra to the stack
sw $ra,4($sp)
la $t1, temp_range
la $t2, custom_ranges
la $t3, custom_iterator
addiu $t0, $zero, 0
lw $t6, ($t1)
lw $t7, ($t1)
custom_while:
#pixel address calculation
beq $t0, 4, exit_custom_while
sll $t5, $t0, 2 #every number takes 4 bytes so we shift it (offset)
addu $t5, $t5, $t1
lw $t4, ($t5)
blt $t4, $t6, custom_swap_min
bgt $t4, $t7, custom_swap_max
addiu $t0, $t0, 1
j custom_while
custom_swap_min:
move $t6, $t4
addiu $t0, $t0, 1
j custom_while
custom_swap_max:
move $t7, $t4
addiu $t0, $t0, 1
j custom_while
exit_custom_while:
sw $t6, ($t2)
sw $t7, 4($t2)
lw $t4, ($t3)
addiu $t4, $t4, 2
sw $t4, ($t3)
lw $ra, 4($sp) #restore (pop) $ra
add $sp, $sp, 4
jr $ra
###################################################################################
# ============================================================================
get_description:
sub $sp, $sp, 4 #push $ra to the stack
sw $ra,4($sp)
move $t6, $a0
bgt $t6,102, pea #len lin oat
adz:
li $v0, 4
la $a0, message1
syscall
j exit_description
pea:
bgt $t6,158, qui
li $v0, 4
la $a0, message2
syscall
j exit_description
qui:
li $v0, 4
la $a0, message3
syscall
exit_description:
lw $ra, 4($sp) #restore (pop) $ra
add $sp, $sp, 4
jr $ra
###################################################################################
clear_list:
sub $sp, $sp, 4 #push $ra to the stack
sw $ra,4($sp)
la $t6, list_of_pixels
addu $t5,$zero,0
while_clear_list:
beq $t5, 255, exit_clear_list
move $t1, $t6
move $t3, $t5
sll $t3,$t3,2
addu $t1,$t1, $t3
lw $t2, ($t1)
addu $t2,$zero,0
sw $t2, ($t1)
addiu $t5,$t5,1
j while_clear_list
exit_clear_list:
lw $ra, 4($sp) #restore (pop) $ra
add $sp, $sp, 4
jr $ra
###################################################################################
clear_temp:
sub $sp, $sp, 4 #push $ra to the stack
sw $ra,4($sp)
la $t6, custom_ranges
addu $t5,$zero,0
while_temp:
beq $t5, 3, exit_temp
move $t1, $t6
move $t3, $t5
sll $t3,$t3,2
addu $t1,$t1, $t3
lw $t2, ($t1)
addu $t2,$zero,0
sw $t2, ($t1)
addiu $t5,$t5,1
j while_temp
exit_temp:
lw $ra, 4($sp) #restore (pop) $ra
add $sp, $sp, 4
jr $ra
###################################################################################
get_custom_ranges:
sub $sp, $sp, 4 #push $ra to the stack
sw $ra,4($sp)
la $t6, custom_ranges
addu $t5,$zero,0
get_while:
beq $t5,6, get_while_exit
move $t3, $t5
sll $t3, $t3, 2
addu $t6, $t6, $t3
lw $t2, ($t6)
li $v0, 4
la $a0, message
syscall
li $v0, 1
move $a0, $t2
syscall
li $v0, 4
la $a0, message
syscall
addu $t5, $t5, 1
get_while_exit:
lw $ra, 4($sp) #restore (pop) $ra
add $sp, $sp, 4
jr $ra
|
hypervisor/hypervisor.asm | TheMachine02/Sorcery | 14 | 240031 | <gh_stars>10-100
define VM_HYPERVISOR_FLAG $D00080
define VM_HYPERVISOR_SETTINGS -1
define VM_HYPERVISOR_DATA -4
define VM_HYPERVISOR_ADRESS $0BF000
define VM_HYPERVISOR_RAM_ADRESS $D3F000
define VM_HYPERVISOR_RAM $D00000 ; some scratch RAM
define VM_HYPERVISOR_LUT 0
define VM_HYPERVISOR_AWARE $DEC0ADDE
_sprintf equ 00000BCh
_os_GetSystemStats equ 0021ED4h
virtual at VM_HYPERVISOR_RAM
vm_guest_count:
db 0
; guest table pointing to "header" of leaf file
vm_guest_table:
rb 54
vm_cursor:
db 0
vm_delay:
db 0
vm_second:
db 0
vm_string_boot:
rb 64
end virtual
hypervisor_ram:=$
hypervisor_offset:= $ - VM_HYPERVISOR_ADRESS
guest_tios_interrupt_jp_ram:= guest_tios_interrupt_jp + hypervisor_offset
guest_tios_nmi_jp_ram:= guest_tios_nmi_jp + hypervisor_offset
guest_tios_boot_jp_ram:= guest_tios_boot_jp + hypervisor_offset
guest_tios_name_ram:= guest_tios_name + hypervisor_offset
org VM_HYPERVISOR_ADRESS
hypercall:
jr .flash_unlock
dw 0
jr .flash_lock
dw 0
; other if needed
.flash_unlock:
; need to be in privileged flash actually
in0 a, ($06)
or a, 4
out0 ($06), a
; flash sequence
ld a, 4
di
jr $+2
di
rsmix
im 1
out0 ($28), a
in0 a, ($28)
bit 2, a
ret
.flash_lock:
xor a, a
out0 ($28), a
in0 a, ($06)
res 2, a
out0 ($06), a
ret
; guest data ;
guest_tios:
; header
jr .init
dw $0000
.interrupt:
guest_tios_interrupt_jp:=$+1
jp $0
.nmi:
guest_tios_nmi_jp:=$+1
jp $0
dd VM_HYPERVISOR_AWARE
guest_tios_name:=$
db "TI-os version 0.0.0", 0
.init:
; cleanup LCD state
ld hl, $E4002D
ld a, l
ld de, $D40000
ld bc, 76800*2
ldir
ld ($E30018), a
; actual jump pointer
guest_tios_boot_jp:=$+1
jp $0
guest_custom:
; custom image should be leaf file exposing a 'special' header at entry point
; jp .init / jp .interrupt / jp .nmi / dd VM_HYPERVISOR_AWARE / NAME / db 0
hypervisor:
; NOTE : we check for value = 0, but overriding the value in RAM could be *very* bad either way
.init:
call .boot_detect
bit VM_HYPERVISOR_LUT, (iy+VM_HYPERVISOR_SETTINGS)
jr z, guest_tios.init
ld hl, (iy+VM_HYPERVISOR_DATA)
add hl, de
or a, a
sbc hl, de
jr z, .init_failure
ld bc, 8
add hl, bc
.init_failure:
jp (hl)
.interrupt:
bit VM_HYPERVISOR_LUT, (iy+VM_HYPERVISOR_SETTINGS)
jr z, guest_tios.interrupt
ld hl, (iy+VM_HYPERVISOR_DATA)
add hl, de
or a, a
sbc hl, de
jr z, .interrupt_failure
jp (hl)
.interrupt_failure:
; we'll need to acknowledge interrupt ourselves if we are in this very special case where interrupt are on, but we have not yet reached boot code (stupid boot 5.0.0)
ld hl, ($F00014)
ld ($F00008), hl
pop hl
pop iy
pop ix
exx
ex af, af'
ei
ret
.nmi:
bit VM_HYPERVISOR_LUT, (iy+VM_HYPERVISOR_SETTINGS)
jr z, guest_tios.nmi
push hl
push af
ld hl, VM_HYPERVISOR_FLAG+VM_HYPERVISOR_DATA
ld hl, (hl)
add hl, de
or a, a
sbc hl, de
jr z, .nmi_restart
pop af
inc hl
inc hl
inc hl
inc hl
ex (sp), hl
ret
.nmi_restart:
pop af
pop hl
; nothing loaded ? Boot reset
rst $08
.boot_detect:
di
xor a, a
sbc hl, hl
ld (VM_HYPERVISOR_DATA), hl
; NOTE : does there is even a TI OS installed ?
; (in theory, we answer always here, since we chained ourselves to the TIOS, and we will fall with it)
; try to detect ti os version
ld hl, guest_tios
ld (vm_guest_table), hl
ld (vm_cursor), a
inc a
ld (vm_guest_count), a
; we have the correct substring version, and entry point with guest_tios
; we need to parse tifs and find leaf file that could be launched
call .boot_search_leaf
; the table was filled
; minimal LCD init
ld hl, $D40000
ld ($E30010), hl
ld a,$27
ld ($E30018), a
ld ($E30200), hl
; palette cleanup
ld hl, $E4FFFF
ld ($E30202), hl
ld de, $E30204
ld bc, 508
ldir
or a, a
sbc hl, hl
ld ix, $000100
ld bc, .boot_string_choose
call .putstring
ld hl, vm_delay
ld (hl), 60
inc hl
ld (hl), 4
.boot_choose_loop:
ld bc, $00083c
.wait:
call .vsync
ld hl, vm_delay
dec (hl)
jr nz, .no_decrement
ld (hl), c
inc hl
dec (hl)
jp z, .boot_do
.no_decrement:
djnz .wait
ld hl, vm_second
ld c, (hl)
push bc
ld bc, .boot_string_enter
push bc
inc hl
push hl
call _sprintf
pop bc
ld hl, 6
add hl, sp
ld sp, hl
ld hl, 19*256+0
ld ix, $000100
call .putstring
lea hl, ix+3
.boot_display_name:
ld a, (vm_guest_count)
ld b, a
.boot_display_loop:
push hl
push bc
ld a, (vm_cursor)
inc a
ld ix, $000100
cp a, h
jr nz, .boot_reverse_color
ld ix, $010001
.boot_reverse_color:
;; ld hl, 2*256+3
push hl
ld a, h
dec a
or a, a
sbc hl, hl
ld l, a
add hl, hl
add hl, hl
add hl, hl
ld bc, vm_guest_table
add hl, bc
ld hl, (hl)
ld bc, 16
add hl, bc
push hl
pop bc
pop hl
call .putstring
pop bc
pop hl
inc h
djnz .boot_display_loop
ld hl, $F50000
ld (hl), 2
xor a, a
.scan_wait:
cp a, (hl)
jr nz, .scan_wait
ld l, $1E
ld a, (hl)
ld hl, vm_cursor
rra
jr nc, .boot_next0
inc (hl)
call .boot_reset_time
.boot_next0:
bit 2, a
jr z, .boot_next1
dec (hl)
call .boot_reset_time
.boot_next1:
jp p, .boot_still_pos
ld (hl), b
.boot_still_pos:
ld a, (vm_guest_count)
dec a
cp a, (hl)
jr nc, .boot_still_up
ld (hl), a
.boot_still_up:
ld a, ($F5001C)
rra
jp nc, .boot_choose_loop
.boot_do:
ld iy, VM_HYPERVISOR_FLAG
ld a, (vm_cursor)
or a, a
res VM_HYPERVISOR_LUT, (iy+VM_HYPERVISOR_SETTINGS)
ret z
sbc hl, hl
ld l, a
add hl, hl
add hl, hl
add hl, hl
ld bc, vm_guest_table
add hl, bc
ld ix, (hl)
inc hl
inc hl
inc hl
inc hl
ld hl, (hl)
ld (iy+VM_HYPERVISOR_DATA), hl
set VM_HYPERVISOR_LUT, (iy+VM_HYPERVISOR_SETTINGS)
lea iy, ix-16
jp leaf.exec_static
.boot_reset_time:
push hl
ld hl, vm_delay
ld (hl), 60
inc hl
ld (hl), 4
pop hl
ret
.boot_search_leaf:
ld b, $34
ld hl, $0C0000
.boot_parse:
push bc
; create an inode for each file found and fill it
ld a, (hl)
cp a, $F0
jr nz, .boot_invalid_sector
inc hl
push hl
.boot_parse_sector:
ld a, (hl)
; unexpected value, quit current sector
cp a, $F0
jr z, .boot_skip_file
cp a, $FC
jr z, .boot_check_file
.boot_parse_sector_continue:
pop hl
.boot_invalid_sector:
ld bc, 65536
add hl, bc
ld h, b
ld l, c
pop bc
djnz .boot_parse
ret
.boot_skip_file:
inc hl
inc.s bc
ld c, (hl)
inc hl
ld b, (hl)
inc hl
add hl, bc
jr .boot_parse_sector
.boot_check_file:
inc hl
inc.s bc
ld c, (hl)
inc hl
ld b, (hl)
inc hl
push hl
add hl, bc
ex (sp), hl
ld a, (hl) ; file type
ld bc, 6
cp a, c
jr nz, .boot_next
add hl, bc
; goes directly to NAME
ld c, (hl)
add hl, bc
; skiped name, now five byte to skip
ld c, 5
add hl, bc
; hl = start of file
push hl
pop iy
call leaf.check_file
jr nz, .boot_next
; it is one of our !
ld a, (vm_guest_count)
or a, a
sbc hl, hl
ld l, a
add hl, hl
add hl, hl
add hl, hl
ld bc, vm_guest_table
add hl, bc
lea iy, iy + LEAF_HEADER_SIZE
ld (hl), iy
inc hl
inc hl
inc hl
inc hl
ld bc, (iy+LEAF_HEADER_ENTRY-LEAF_HEADER_SIZE)
inc bc
inc bc
inc bc
inc bc
ld (hl), bc
inc a
ld (vm_guest_count), a
.boot_next:
pop hl
jp .boot_parse_sector
.boot_string_choose:
db "Choose OS to boot from :", 0
.boot_string_enter:
db "Press Enter to boot. Boot selected in %2d second(s)", 0
|
jvm_demo/java/expression/antlr/practice_myself/src/main/java/com/hwloser/simple/hello/arithmetic/easy/prog/Expr.g4 | Hwloser/untitled | 0 | 6816 | grammar Expr;
/* 起始规则，语法分析的七点 */
prog: stat+ ;
stat: expr NEWLINE
| ID '=' expr NEWLINE
| NEWLINE
;
expr: expr ('*'|'/') expr
| expr ('+'|'-') expr
| INT
| ID
| '(' expr ')'
;
ID : [a-zA-Z]+ ; // 匹配标识符
INT : [0-9]+ ; // 匹配整数
WS : [ \t]+ -> skip ; // 丢弃空白字符
NEWLINE : '\n' ; // 告诉语法分析器一个新行的开始 (即语句终止标志)
|
Transynther/x86/_processed/AVXALIGN/_st_sm_/i9-9900K_12_0xa0.log_21829_39.asm | ljhsiun2/medusa | 9 | 164591 | <filename>Transynther/x86/_processed/AVXALIGN/_st_sm_/i9-9900K_12_0xa0.log_21829_39.asm
.global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r15
push %r9
push %rax
push %rbx
push %rcx
push %rdi
push %rsi
lea addresses_D_ht+0x18bdc, %r15
nop
nop
nop
nop
nop
cmp $37541, %r9
mov (%r15), %rbx
nop
nop
nop
nop
nop
xor $48348, %rax
lea addresses_UC_ht+0x16f4c, %rdi
nop
dec %r10
mov (%rdi), %r15
nop
nop
nop
cmp %r9, %r9
lea addresses_UC_ht+0x1dd9c, %rsi
lea addresses_UC_ht+0x59dc, %rdi
sub %r10, %r10
mov $37, %rcx
rep movsb
nop
add %rcx, %rcx
pop %rsi
pop %rdi
pop %rcx
pop %rbx
pop %rax
pop %r9
pop %r15
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r11
push %r14
push %r15
push %r9
push %rax
push %rbx
push %rsi
// Store
mov $0x487b4a00000007dc, %r14
dec %rsi
movl $0x51525354, (%r14)
sub $9353, %r11
// Store
lea addresses_RW+0x9cc6, %rax
nop
nop
cmp %r15, %r15
movb $0x51, (%rax)
nop
nop
nop
nop
add %rsi, %rsi
// Store
lea addresses_US+0x1b5bc, %rax
nop
nop
nop
nop
cmp %r15, %r15
movw $0x5152, (%rax)
nop
nop
nop
nop
xor %rax, %rax
// Store
lea addresses_WT+0x47dc, %r14
nop
xor %r15, %r15
mov $0x5152535455565758, %rbx
movq %rbx, %xmm3
movups %xmm3, (%r14)
xor $36955, %rsi
// Store
lea addresses_UC+0x1397c, %rax
nop
nop
nop
and $61514, %r14
movb $0x51, (%rax)
nop
nop
nop
nop
nop
add %r14, %r14
// Store
lea addresses_UC+0x1138e, %r14
clflush (%r14)
nop
nop
nop
nop
and %rsi, %rsi
movb $0x51, (%r14)
nop
nop
nop
nop
nop
xor $38755, %r11
// Faulty Load
lea addresses_WT+0x47dc, %r15
nop
nop
nop
nop
nop
cmp %rsi, %rsi
mov (%r15), %r11
lea oracles, %rax
and $0xff, %r11
shlq $12, %r11
mov (%rax,%r11,1), %r11
pop %rsi
pop %rbx
pop %rax
pop %r9
pop %r15
pop %r14
pop %r11
ret
/*
<gen_faulty_load>
[REF]
{'src': {'NT': False, 'same': False, 'congruent': 0, 'type': 'addresses_WT', 'AVXalign': False, 'size': 4}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 10, 'type': 'addresses_NC', 'AVXalign': False, 'size': 4}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 0, 'type': 'addresses_RW', 'AVXalign': False, 'size': 1}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 3, 'type': 'addresses_US', 'AVXalign': False, 'size': 2}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': True, 'congruent': 0, 'type': 'addresses_WT', 'AVXalign': False, 'size': 16}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 4, 'type': 'addresses_UC', 'AVXalign': False, 'size': 1}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 1, 'type': 'addresses_UC', 'AVXalign': False, 'size': 1}}
[Faulty Load]
{'src': {'NT': False, 'same': True, 'congruent': 0, 'type': 'addresses_WT', 'AVXalign': True, 'size': 8}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'src': {'NT': False, 'same': False, 'congruent': 9, 'type': 'addresses_D_ht', 'AVXalign': True, 'size': 8}, 'OP': 'LOAD'}
{'src': {'NT': False, 'same': False, 'congruent': 0, 'type': 'addresses_UC_ht', 'AVXalign': False, 'size': 8}, 'OP': 'LOAD'}
{'src': {'same': False, 'congruent': 6, 'type': 'addresses_UC_ht'}, 'OP': 'REPM', 'dst': {'same': False, 'congruent': 9, 'type': 'addresses_UC_ht'}}
{'58': 21829}
58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58
*/
|
Transynther/x86/_processed/NONE/_xt_/i3-7100_9_0x84_notsx.log_21829_1792.asm | ljhsiun2/medusa | 9 | 179833 | <filename>Transynther/x86/_processed/NONE/_xt_/i3-7100_9_0x84_notsx.log_21829_1792.asm
.global s_prepare_buffers
s_prepare_buffers:
push %r11
push %r15
push %rcx
lea addresses_UC_ht+0x10277, %r11
clflush (%r11)
nop
nop
nop
nop
nop
cmp $61281, %rcx
mov $0x6162636465666768, %r15
movq %r15, %xmm1
and $0xffffffffffffffc0, %r11
movaps %xmm1, (%r11)
add %r11, %r11
pop %rcx
pop %r15
pop %r11
ret
.global s_faulty_load
s_faulty_load:
push %r13
push %r14
push %r8
push %r9
push %rsi
// Faulty Load
lea addresses_normal+0x1ef7, %r8
nop
nop
nop
nop
nop
xor $19311, %r13
movb (%r8), %r9b
lea oracles, %r13
and $0xff, %r9
shlq $12, %r9
mov (%r13,%r9,1), %r9
pop %rsi
pop %r9
pop %r8
pop %r14
pop %r13
ret
/*
<gen_faulty_load>
[REF]
{'src': {'type': 'addresses_normal', 'same': False, 'size': 32, 'congruent': 0, 'NT': True, 'AVXalign': False}, 'OP': 'LOAD'}
[Faulty Load]
{'src': {'type': 'addresses_normal', 'same': True, 'size': 1, 'congruent': 0, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'dst': {'type': 'addresses_UC_ht', 'same': False, 'size': 16, 'congruent': 7, 'NT': False, 'AVXalign': True}, 'OP': 'STOR'}
{'34': 21829}
34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34
*/
|
libsrc/math/mbf32/c/asm/___mbf32_SQR.asm | jpoikela/z88dk | 640 | 22280 | SECTION code_fp_mbf32
PUBLIC ___mbf32_SQR
EXTERN SQR
defc ___mbf32_SQR = SQR
|
oeis/186/A186707.asm | neoneye/loda-programs | 11 | 95041 | ; A186707: Partial sums of A007202 (crystal ball sequence for hexagonal close-packing).
; Submitted by <NAME>(s2)
; 1,14,71,224,547,1134,2101,3584,5741,8750,12811,18144,24991,33614,44297,57344,73081,91854,114031,140000,170171,204974,244861,290304,341797,399854,465011,537824,618871,708750,808081,917504,1037681,1169294,1313047,1469664,1639891,1824494,2024261,2240000,2472541,2722734,2991451,3279584,3588047,3917774,4269721,4644864,5044201,5468750,5919551,6397664,6904171,7440174,8006797,8605184,9236501,9901934,10602691,11340000,12115111,12929294,13783841,14680064,15619297,16602894,17632231,18708704,19833731
add $0,1
pow $0,4
add $0,3
mul $0,7
div $0,2
mul $0,4
sub $0,56
div $0,16
add $0,1
|
Safari/Close-Right-Tab.applescript | boisy/AppleScripts | 116 | 249 | <reponame>boisy/AppleScripts
try
tell application "Safari"
tell window 1
close tab ((index of current tab) + 1)
end tell
end tell
on error
beep
end try
|
day05/day05.adb | thorstel/Advent-of-Code-2018 | 2 | 19670 | with Ada.Text_IO; use Ada.Text_IO;
procedure Day05 is
function React (Unit1 : Character; Unit2 : Character) return Boolean is
Result : Boolean := False;
begin
if abs (Character'Pos (Unit1) - Character'Pos (Unit2)) = 32 then
Result := True;
end if;
return Result;
end React;
function Filter_Reactions (Polymer : String;
Ignore : Character) return String
is
Result : String (Polymer'Range);
Last : Natural := Result'First - 1;
I : Natural := Result'First;
begin
while I <= Polymer'Last loop
declare
Keep : Boolean := True;
begin
if Polymer (I) = Ignore or
abs (Character'Pos (Polymer (I)) - Character'Pos (Ignore)) = 32
then
I := I + 1;
else
if I < Polymer'Last then
if React (Polymer (I), Polymer (I + 1)) then
Keep := False;
end if;
end if;
if Keep then
Last := Last + 1;
Result (Last) := Polymer (I);
I := I + 1;
else
I := I + 2;
end if;
end if;
end;
end loop;
declare
New_Polymer : constant String := Result (Result'First .. Last);
begin
if Last = Polymer'Last then
return New_Polymer;
else
return Filter_Reactions (New_Polymer, Ignore);
end if;
end;
end Filter_Reactions;
Input_File : File_Type;
begin
Open (Input_File, In_File, "input.txt");
declare
Input : constant String := Get_Line (Input_File);
Minimum_Length : Natural;
Current_Length : Natural;
begin
-- Part 1
Minimum_Length := Filter_Reactions (Input, '_')'Length;
Put_Line ("Part 1 =" & Integer'Image (Minimum_Length));
-- Part 2
for C in Character'Pos ('a') .. Character'Pos ('z') loop
Current_Length := Filter_Reactions (Input, Character'Val (C))'Length;
if Current_Length < Minimum_Length then
Minimum_Length := Current_Length;
end if;
end loop;
Put_Line ("Part 2 =" & Integer'Image (Minimum_Length));
end;
Close (Input_File);
end Day05;
|
programs/oeis/174/A174595.asm | karttu/loda | 0 | 20281 | ; A174595: a(n) = 5*n^2/8 - n + 1/2 + (-1)^n*(-3*n^2/8 + n - 1/2).
; 0,0,1,4,4,16,9,36,16,64,25,100,36,144,49,196,64,256,81,324,100,400,121,484,144,576,169,676,196,784,225,900,256,1024,289,1156,324,1296,361,1444,400,1600,441,1764,484,1936,529,2116,576,2304,625,2500,676,2704,729,2916,784,3136,841,3364,900,3600,961,3844,1024,4096,1089,4356,1156,4624,1225,4900,1296,5184,1369,5476,1444,5776,1521,6084,1600,6400,1681,6724,1764,7056,1849,7396,1936,7744,2025,8100,2116,8464,2209,8836,2304,9216,2401,9604,2500,10000,2601,10404,2704,10816,2809,11236,2916,11664,3025,12100,3136,12544,3249,12996,3364,13456,3481,13924,3600,14400,3721,14884,3844,15376,3969,15876,4096,16384,4225,16900,4356,17424,4489,17956,4624,18496,4761,19044,4900,19600,5041,20164,5184,20736,5329,21316,5476,21904,5625,22500,5776,23104,5929,23716,6084,24336,6241,24964,6400,25600,6561,26244,6724,26896,6889,27556,7056,28224,7225,28900,7396,29584,7569,30276,7744,30976,7921,31684,8100,32400,8281,33124,8464,33856,8649,34596,8836,35344,9025,36100,9216,36864,9409,37636,9604,38416,9801,39204,10000,40000,10201,40804,10404,41616,10609,42436,10816,43264,11025,44100,11236,44944,11449,45796,11664,46656,11881,47524,12100,48400,12321,49284,12544,50176,12769,51076,12996,51984,13225,52900,13456,53824,13689,54756,13924,55696,14161,56644,14400,57600,14641,58564,14884,59536,15129,60516,15376,61504
mov $3,$0
mod $0,2
mov $1,$3
sub $1,$0
lpb $0,1
mul $0,$2
mul $1,2
lpe
pow $1,2
div $1,4
|
source/oasis/program-elements-formal_object_declarations.ads | reznikmm/gela | 0 | 9387 | -- SPDX-FileCopyrightText: 2019 <NAME> <<EMAIL>>
--
-- SPDX-License-Identifier: MIT
-------------------------------------------------------------
with Program.Elements.Declarations;
with Program.Elements.Defining_Identifiers;
with Program.Lexical_Elements;
with Program.Elements.Expressions;
with Program.Elements.Aspect_Specifications;
package Program.Elements.Formal_Object_Declarations is
pragma Pure (Program.Elements.Formal_Object_Declarations);
type Formal_Object_Declaration is
limited interface and Program.Elements.Declarations.Declaration;
type Formal_Object_Declaration_Access is
access all Formal_Object_Declaration'Class with Storage_Size => 0;
not overriding function Names
(Self : Formal_Object_Declaration)
return not null Program.Elements.Defining_Identifiers
.Defining_Identifier_Vector_Access is abstract;
not overriding function Object_Subtype
(Self : Formal_Object_Declaration)
return not null Program.Elements.Element_Access is abstract;
not overriding function Default_Expression
(Self : Formal_Object_Declaration)
return Program.Elements.Expressions.Expression_Access is abstract;
not overriding function Aspects
(Self : Formal_Object_Declaration)
return Program.Elements.Aspect_Specifications
.Aspect_Specification_Vector_Access is abstract;
not overriding function Has_In
(Self : Formal_Object_Declaration)
return Boolean is abstract;
not overriding function Has_Out
(Self : Formal_Object_Declaration)
return Boolean is abstract;
not overriding function Has_Not_Null
(Self : Formal_Object_Declaration)
return Boolean is abstract;
type Formal_Object_Declaration_Text is limited interface;
type Formal_Object_Declaration_Text_Access is
access all Formal_Object_Declaration_Text'Class with Storage_Size => 0;
not overriding function To_Formal_Object_Declaration_Text
(Self : in out Formal_Object_Declaration)
return Formal_Object_Declaration_Text_Access is abstract;
not overriding function Colon_Token
(Self : Formal_Object_Declaration_Text)
return not null Program.Lexical_Elements.Lexical_Element_Access
is abstract;
not overriding function In_Token
(Self : Formal_Object_Declaration_Text)
return Program.Lexical_Elements.Lexical_Element_Access is abstract;
not overriding function Out_Token
(Self : Formal_Object_Declaration_Text)
return Program.Lexical_Elements.Lexical_Element_Access is abstract;
not overriding function Not_Token
(Self : Formal_Object_Declaration_Text)
return Program.Lexical_Elements.Lexical_Element_Access is abstract;
not overriding function Null_Token
(Self : Formal_Object_Declaration_Text)
return Program.Lexical_Elements.Lexical_Element_Access is abstract;
not overriding function Assignment_Token
(Self : Formal_Object_Declaration_Text)
return Program.Lexical_Elements.Lexical_Element_Access is abstract;
not overriding function With_Token
(Self : Formal_Object_Declaration_Text)
return Program.Lexical_Elements.Lexical_Element_Access is abstract;
not overriding function Semicolon_Token
(Self : Formal_Object_Declaration_Text)
return not null Program.Lexical_Elements.Lexical_Element_Access
is abstract;
end Program.Elements.Formal_Object_Declarations;
|
src/Data/Desc.agda | johnyob/agda-desc | 0 | 5935 | <filename>src/Data/Desc.agda
-- ----------------------------------------------------------------------
-- The Agda Descriptor Library
--
-- (Open) Descriptors
-- ----------------------------------------------------------------------
module Data.Desc where
open import Data.List using (List; []; _∷_)
open import Data.List.Relation.Unary.All using (All; []; _∷_)
open import Data.List.Relation.Unary.Any using (here; there)
open import Data.List.Membership.Propositional using (_∈_)
open import Data.Product using (Σ; _,_)
open import Data.Var using (_-Scoped[_]; Var; get; zero; suc; tabulate)
open import Data.Unit.Polymorphic using (⊤; tt)
open import Level using (Level; 0ℓ; _⊔_)
open import Relation.Unary using (IUniversal; _⇒_)
private
variable
A : Set
1ℓ : Level
1ℓ = Level.suc 0ℓ
-- ----------------------------------------------------------------------
-- Definition
--
-- An open description is a open dependent type theory.
-- Our theoretic model is described by:
--
-- Metatheoretic terms:
--
-- Agda sets A, B ∷= ...
-- Agda values x, y ∷= ...
--
-- Open object terms:
--
-- kinds κ ∷= Set | Π A κ
-- types T ∷= a | T x | Π A T | T ⟶ T
--
-- A descriptor is a set of well-kinded constructor types.
data Kind : Set₁ where
`Set₀ : Kind
`Π : (A : Set) → (A → Kind) → Kind
private
variable
κ κ′ : Kind
Γ : List Kind
B : A → Kind
infixr 6 _⟶_
data Type : Kind -Scoped[ 1ℓ ] where
`_ : ∀[ Var κ ⇒ Type κ ]
_·_ : Type (`Π A B) Γ → (a : A) → Type (B a) Γ
`Π : (A : Set) → (A → Type `Set₀ Γ) → Type `Set₀ Γ
_⟶_ : Type `Set₀ Γ → Type `Set₀ Γ → Type `Set₀ Γ
mutual
data Pos : Type κ Γ → Set where
`_ : ∀ (x : Var κ Γ)
-- ----------------
→ Pos (` x)
_·_ : ∀ {T : Type (`Π A B) Γ}
→ Pos T
→ (a : A)
-- ------------------------
→ Pos (T · a)
`Π : (A : Set) {T : A → Type `Set₀ Γ}
→ ((a : A) → Pos (T a))
-- --------------------------------
→ Pos (`Π A T)
_⟶_ : ∀ {T T′ : Type `Set₀ Γ}
→ Neg T
→ Pos T′
-- --------------------------
→ Pos (T ⟶ T′)
data Neg : Type κ Γ → Set where
_·_ : ∀ {T : Type (`Π A B) Γ}
→ Neg T
→ (a : A)
-- ------------------------
→ Neg (T · a)
`Π : (A : Set) {T : A → Type `Set₀ Γ}
→ ((a : A) → Neg (T a))
-- --------------------------------
→ Neg (`Π A T)
_⟶_ : ∀ {T T′ : Type `Set₀ Γ}
→ Pos T
→ Neg T′
-- --------------------------
→ Neg (T ⟶ T′)
data StrictPos : Type κ Γ → Set where
`_ : ∀ (x : Var κ Γ)
-- ----------------
→ StrictPos (` x)
_·_ : ∀ {T : Type (`Π A B) Γ}
→ StrictPos T
→ (a : A)
-- ------------------------
→ StrictPos (T · a)
`Π : (A : Set) {T : A → Type `Set₀ Γ}
→ ((a : A) → StrictPos (T a))
-- --------------------------------
→ StrictPos (`Π A T)
data Con : Type κ Γ → Set where
`_ : ∀ (x : Var κ Γ)
-- ----------------
→ Con (` x)
_·_ : ∀ {T : Type (`Π A B) Γ}
→ Con T
→ (a : A)
-- ------------------------
→ Con (T · a)
`Π : (A : Set) {T : A → Type `Set₀ Γ}
→ ((a : A) → Con (T a))
-- --------------------------------
→ Con (`Π A T)
_⟶_ : ∀ {T T′ : Type `Set₀ Γ}
→ StrictPos T
→ Con T′
-- --------------------------
→ Con (T ⟶ T′)
data Constr : Kind -Scoped[ 1ℓ ] where
! : {T : Type κ Γ} → Con T → Constr κ Γ
++⇒C : ∀{T : Type κ Γ} → StrictPos T → Con T
++⇒C (` x) = ` x
++⇒C (P · a) = ++⇒C P · a
++⇒C (`Π A P) = `Π A (λ a → ++⇒C (P a))
Desc : List Kind → Set₁
Desc Γ = List (Constr `Set₀ Γ)
-- ----------------------------------------------------------------------
-- Interpretation
lift⟦_⟧ᴷ : Kind → (ℓ : Level) → Set (Level.suc ℓ)
lift⟦ `Set₀ ⟧ᴷ ℓ = Set ℓ
lift⟦ `Π A κ ⟧ᴷ ℓ = (a : A) → lift⟦ κ a ⟧ᴷ ℓ
-- Lifting of lift⟦_⟧ᴷ to a context
lift⟪_⟫ᴷ : List Kind → (ℓ : Level) → Set (Level.suc ℓ)
lift⟪ Γ ⟫ᴷ ℓ = All (λ κ → lift⟦ κ ⟧ᴷ ℓ) Γ
⟦_⟧ᴷ : Kind → Set₁
⟦ `Set₀ ⟧ᴷ = Set
⟦ `Π A κ ⟧ᴷ = (a : A) → ⟦ κ a ⟧ᴷ
⟪_⟫ᴷ : List Kind → Set₁
⟪ Γ ⟫ᴷ = All ⟦_⟧ᴷ Γ
-- ----------------------------------------------------------------------
-- Fixpoint
--
-- To define the fixed point, we're looking for a fixpoint of the form:
-- μ : Desc Γ → ⟪ Γ ⟫ᴷ
--
-- To consider the interpretation of constructors and type formers,
-- we first describe the terms formed by constructors and
-- positive types:
--
-- constructor terms c ∷= Constrᵢ | c · a | c · p
private
variable
C : Constr `Set₀ Γ
D : Desc Γ
data Term : Constr `Set₀ Γ -Scoped[ 1ℓ ] where
`Constr : ∀[ Var C ⇒ Term C ]
_·_ : ∀ {A} {T : A → Type `Set₀ Γ} {C : (a : A) → Con (T a)}
→ Term (! (`Π A C)) D → (a : A) → Term (! (C a)) D
_•_ : ∀ {T T′ : Type `Set₀ Γ} {P : StrictPos T} {C : Con T′}
→ Term (! (P ⟶ C)) D → Term (! (++⇒C P)) D → Term (! C) D
μᵏ : Constr κ Γ → Desc Γ → lift⟦ κ ⟧ᴷ 1ℓ
μᵏ {κ = `Set₀} C D = Term C D
μᵏ {κ = `Π _ _} (! C) D = λ a → μᵏ (! (C · a)) D
μᴰ : Desc Γ → lift⟪ Γ ⟫ᴷ 1ℓ
μᴰ D = tabulate λ x → μᵏ (! (` x)) D
-- ----------------------------------------------------------------------
-- Examples
ℕᴰ : Desc (`Set₀ ∷ [])
ℕᴰ = ! (` zero) ∷ ! ((` zero) ⟶ (` zero)) ∷ []
`ℕ : Set₁
`ℕ = get zero (μᴰ ℕᴰ)
pattern `zero = `Constr zero
pattern `suc n = `Constr (suc zero) • n
_ : `ℕ
_ = `suc (`suc `zero)
|
Transynther/x86/_processed/NONE/_xt_/i7-7700_9_0x48_notsx.log_21829_1061.asm | ljhsiun2/medusa | 9 | 244103 | .global s_prepare_buffers
s_prepare_buffers:
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r14
push %rax
push %rbp
push %rdi
push %rdx
// Faulty Load
lea addresses_UC+0x55b1, %r10
nop
nop
nop
cmp $45927, %rdx
vmovups (%r10), %ymm1
vextracti128 $1, %ymm1, %xmm1
vpextrq $1, %xmm1, %rbp
lea oracles, %rdx
and $0xff, %rbp
shlq $12, %rbp
mov (%rdx,%rbp,1), %rbp
pop %rdx
pop %rdi
pop %rbp
pop %rax
pop %r14
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'same': False, 'NT': False, 'AVXalign': False, 'size': 4, 'type': 'addresses_UC', 'congruent': 0}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'same': True, 'NT': False, 'AVXalign': False, 'size': 32, 'type': 'addresses_UC', 'congruent': 0}}
<gen_prepare_buffer>
{'37': 21829}
37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37
*/
|
Driver/Mouse/Pqpen/pqpen.asm | steakknife/pcgeos | 504 | 7861 | <gh_stars>100-1000
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
Copyright (c) GeoWorks 1989 -- All Rights Reserved
PROJECT: PC GEOS
MODULE: MOUSE DRIVER -- Mouse Systems serial mouse
FILE: pqpen.asm
AUTHOR: <NAME>, August 9, 1989
ROUTINES:
Name Description
---- -----------
MouseDevInit Initialize device
MouseDevExit Exit device (actually MouseClosePort in
mouseSerCommon.asm)
REVISION HISTORY:
Name Date Description
---- ---- -----------
Adam 3/24/89 Initial revision
DESCRIPTION:
Device-dependent support for Mouse Systems serial mouse.
$Id: pqpen.asm,v 1.1 97/04/18 11:48:05 newdeal Exp $
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
_Mouse = 1
;
MOUSE_CANT_SET_RATE = 1
MOUSE_NUM_BUTTONS = 1
MOUSE_USES_ABSOLUTE_DELTAS = 1
DIGITIZER_X_RES = 96 ;96 DPI
DIGITIZER_Y_RES = 72 ;72 DPI
DEBUG_POQET_PEN = 0
include mouseCommon.asm ; Include common definitions/code.
;------------------------------------------------------------------------------
; DEVICE STRINGS
;------------------------------------------------------------------------------
MouseExtendedInfoSeg segment lmem LMEM_TYPE_GENERAL
mouseExtendedInfo DriverExtendedInfoTable <
{}, ; lmem header added by Esp
length mouseNameTable, ; Number of supported devices
offset mouseNameTable,
offset mouseInfoTable
>
mouseNameTable lptr.char poqetPad
lptr.char 0 ; null-terminator
poqetPad chunk.char 'PoqetPad Pen', 0
mouseInfoTable MouseExtendedInfo \
0 ;poqetPad
CheckHack <length mouseInfoTable eq length mouseNameTable>
MouseExtendedInfoSeg ends
;------------------------------------------------------------------------------
; VARIABLES/DATA/CONSTANTS
;------------------------------------------------------------------------------
idata segment
oldVector fptr.far
;
; Packet format
;
; The reading of a packet is performed by a state machine in MouseDevHandler.
; On any input error, we reset the state machine to discard whatever packet
; we were reading.
;
; The mouse motion is accumulated in newX and newY, while the packet's
; button info is stored in 'buttons'
;
newX word
newY word
buttons byte
;
; State machine definitions
;
InStates etype byte
IS_START enum InStates ; At start of packet -- byte
; must have have high bit on
IS_X_LOW enum InStates ; Expecting X low
IS_X_HIGH enum InStates ; Expecting X high
IS_Y_LOW enum InStates ; Expecting Y low
IS_Y_HIGH enum InStates ; Expecting Y high
IS_ERR enum InStates ; Error received -- discard
; until sync byte (not actually
; used since IS_START state
; discards until sync)
inState InStates IS_START
mouseRates label byte ; Needed to avoid assembly errors.
MOUSE_NUM_RATES equ 0 ; We can't change the report rate.
if DEBUG_POQET_PEN
HACK_BUF_SIZE = 2000
hackPtr word 0
pbuf byte HACK_BUF_SIZE dup (0)
endif
idata ends
Resident segment resource
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
MouseInit
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: Initialize the com port for the mouse
CALLED BY: MouseInit
PASS: DS=ES=dgroup
RETURN: Carry clear if ok
DESTROYED: DI
PSEUDO CODE/STRATEGY:
Figure out which port to use.
Open it.
The data format is specified in the DEF constants above, as
extracted from the documentation.
Return with carry clear.
KNOWN BUGS/SIDE EFFECTS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
ardeb 3/29/89 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
MouseDevInit proc far uses ax, bx, cx, dx, si, di, bp
.enter
mov di, offset oldVector
mov bx, segment MouseDevHandler
mov cx, offset MouseDevHandler
mov ax, 2
call SysCatchDeviceInterrupt
;
; All's well that ends well...
;
clc
.leave
ret
MouseDevInit endp
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
MouseDevExit
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: Close down.
CALLED BY: MousePortExit
PASS: DS = dgroup
RETURN: Carry set if couldn't close the port (someone else was
closing it (!)).
DESTROYED: AX, BX, DI
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
ardeb 9/25/89 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
MouseDevExit proc far
;
; Close down the port...if it was ever opened, that is.
;
segmov es, ds
mov di, offset oldVector
mov ax, 2
call SysResetDeviceInterrupt
ret
MouseDevExit endp
;------------------------------------------------------------------------------
; RESIDENT DEVICE-DEPENDENT ROUTINES
;------------------------------------------------------------------------------
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
MouseTestDevice
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: Check for the existence of a device
CALLED BY: DRE_TEST_DEVICE
PASS: dx:si = pointer to null-terminated device name string
RETURN: carry set if string is invalid
carry clear if string is valid
ax = DevicePresent enum in either case
DESTROYED: nothing
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
ardeb 9/27/90 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
MouseTestDevice proc near
.enter
clc
;;; call MouseDevTest
.leave
ret
MouseTestDevice endp
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
MouseSetDevice
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: Turn on the device.
CALLED BY: DRE_SET_DEVICE
PASS: dx:si = pointer to null-terminated device name string
RETURN: nothing
DESTROYED: nothing
PSEUDO CODE/STRATEGY:
Just call the device-initialization routine in Init
KNOWN BUGS/SIDE EFFECTS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
ardeb 9/27/90 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
MouseSetDevice proc near
.enter
call MouseDevInit
.leave
ret
MouseSetDevice endp
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
MouseDevHandler
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: HandleMem the receipt of a byte in the packet.
CALLED BY: INT2
PASS: none
RETURN: none
DESTROYED: none
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
ardeb 3/24/89 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
MouseDevHandler proc far uses ax, bx, cx, dx, si, di, bp, ds, es
.enter
call SysEnterInterrupt
mov dx, dgroup
mov ds, dx
; loop reading bytes and calling FSM
readLoop:
mov dx, 0x3e8
in al, dx
call FSMByte
mov dx, 0x3ea
in al, dx
test al, 1
jz readLoop
mov al, IC_GENEOI
out IC1_CMDPORT, al
call SysExitInterrupt
.leave
iret
MouseDevHandler endp
COMMENT @----------------------------------------------------------------------
FUNCTION: FSMByte
DESCRIPTION: Handle a byte from the digitizer
CALLED BY: INTERNAL
PASS:
al - byte
ds - idata
RETURN:
none
DESTROYED:
ax, dx
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Tony 2/15/92 Initial version
------------------------------------------------------------------------------@
FSMByte proc near
if DEBUG_POQET_PEN
push si
mov si, ds:hackPtr
mov ds:[pbuf][si], al
inc si
cmp si, HACK_BUF_SIZE
jnz 1$
clr si
1$:
mov ds:hackPtr, si
pop si
endif
mov ah, ds:inState
cmp ah, IS_START
jnz notFirst
;
; Make sure start byte is legal (high bit must be set)
;
test al, 0x80
jnz 5$
toError:
jmp error
5$:
; treat 0x98 as error (always has data 0)
cmp al, 0x98
jz toError
;
; Record button state, change states and return.
;
mov ds:buttons, al
mov ds:inState, IS_X_LOW
jmp done
notFirst:
test al, 0x80
jnz toError
cmp ah, IS_X_LOW
jnz notXLow
;
; Expecting X low -- record it and return.
;
shl al
mov ds:newX.low, al
mov ds:inState, IS_X_HIGH
jmp done
notXLow:
cmp ah, IS_X_HIGH
jnz notXHigh
;
; Expecting X high -- record it and return
;
mov ds:newX.high, al
shr ds:newX
mov ds:inState, IS_Y_LOW
jmp done
notXHigh:
cmp ah, IS_Y_LOW
jnz notYLow
;
; Expecting Y low -- record it and return.
;
shl al
mov ds:newY.low, al
mov ds:inState, IS_Y_HIGH
jmp done
notYLow:
cmp ah, IS_Y_HIGH
jnz error
;
; Expecting X high -- record it and return
;
mov ds:newY.high, al
shr ds:newY
; packet complete -- send it
DIGITIZER_MAX_X = 4096
DIGITIZER_MAX_Y = 4096
X_MULTIPLIER = 30800 ; 31018
Y_MULTIPLIER = 25000 ; 28560
mov ax, ds:newX
cmp ax, DIGITIZER_MAX_X
jbe 10$
clr ax
10$:
mov bx, X_MULTIPLIER
mul bx
mov cx, dx ;cx = x pos
mov ax, ds:newY
cmp ax, DIGITIZER_MAX_Y
jbe 20$
clr ax
20$:
mov bx, Y_MULTIPLIER
mul bx ;dx = y pos
MAX_POSITION_X = 639
MAX_POSITION_Y = 207
cmp cx, MAX_POSITION_X
jbe notOutOfRangeX
mov cx, MAX_POSITION_X
notOutOfRangeX:
cmp dx, MAX_POSITION_Y
jbe notOutOfRangeY
mov dx, MAX_POSITION_Y
notOutOfRangeY:
;
; Shift buttons into BH for later manipulation.
;
mov bh, mask MOUSE_B0 or mask MOUSE_B1 or mask MOUSE_B2 \
or mask MOUSE_B3
cmp ds:buttons, 0x82
jz notPress
mov bh, mask MOUSE_B1 or mask MOUSE_B2 or mask MOUSE_B3
notPress:
;
; Deliver whatever events are required.
;
call MouseSendEvents
;
; Go back to waiting for the start byte (Fall Through)
;
error:
;
; Error -- discard byte but reset state machine
;
mov ds:inState, IS_START
done:
ret
FSMByte endp
Resident ends
|
programs/oeis/062/A062828.asm | neoneye/loda | 22 | 179818 | ; A062828: a(n) = gcd(2n, n(n+1)/2).
; 1,1,6,2,5,3,14,4,9,5,22,6,13,7,30,8,17,9,38,10,21,11,46,12,25,13,54,14,29,15,62,16,33,17,70,18,37,19,78,20,41,21,86,22,45,23,94,24,49,25,102,26,53,27,110,28,57,29,118,30,61,31,126,32,65,33,134,34,69,35,142,36,73,37,150,38,77,39,158,40,81,41,166,42,85,43,174,44,89,45,182,46,93,47,190,48,97,49,198,50
sub $2,$0
add $0,2
sub $2,$0
bin $0,2
gcd $0,$2
|
src/Vec.agda | nad/equality | 3 | 13116 | <reponame>nad/equality
------------------------------------------------------------------------
-- Vectors, defined using a recursive function
------------------------------------------------------------------------
{-# OPTIONS --without-K --safe #-}
open import Equality
module Vec
{reflexive} (eq : ∀ {a p} → Equality-with-J a p reflexive) where
open import Prelude
open import Bijection eq using (_↔_)
open Derived-definitions-and-properties eq
open import Function-universe eq hiding (id; _∘_)
open import List eq using (length)
open import Surjection eq using (_↠_; ↠-≡)
private
variable
a b c : Level
A B : Type a
f g : A → B
n : ℕ
------------------------------------------------------------------------
-- The type
-- Vectors.
Vec : Type a → ℕ → Type a
Vec A zero = ↑ _ ⊤
Vec A (suc n) = A × Vec A n
------------------------------------------------------------------------
-- Some simple functions
-- Finds the element at the given position.
index : Vec A n → Fin n → A
index {n = suc _} (x , _) fzero = x
index {n = suc _} (_ , xs) (fsuc i) = index xs i
-- Updates the element at the given position.
infix 3 _[_≔_]
_[_≔_] : Vec A n → Fin n → A → Vec A n
_[_≔_] {n = zero} _ () _
_[_≔_] {n = suc _} (x , xs) fzero y = y , xs
_[_≔_] {n = suc _} (x , xs) (fsuc i) y = x , (xs [ i ≔ y ])
-- Applies the function to every element in the vector.
map : (A → B) → Vec A n → Vec B n
map {n = zero} f _ = _
map {n = suc _} f (x , xs) = f x , map f xs
-- Constructs a vector containing a certain number of copies of the
-- given element.
replicate : A → Vec A n
replicate {n = zero} _ = _
replicate {n = suc _} x = x , replicate x
-- The head of the vector.
head : Vec A (suc n) → A
head = proj₁
-- The tail of the vector.
tail : Vec A (suc n) → Vec A n
tail = proj₂
------------------------------------------------------------------------
-- Conversions to and from lists
-- Vectors can be converted to lists.
to-list : Vec A n → List A
to-list {n = zero} _ = []
to-list {n = suc n} (x , xs) = x ∷ to-list xs
-- Lists can be converted to vectors.
from-list : (xs : List A) → Vec A (length xs)
from-list [] = _
from-list (x ∷ xs) = x , from-list xs
-- ∃ (Vec A) is isomorphic to List A.
∃Vec↔List : ∃ (Vec A) ↔ List A
∃Vec↔List {A = A} = record
{ surjection = record
{ logical-equivalence = record
{ to = to-list ∘ proj₂
; from = λ xs → length xs , from-list xs
}
; right-inverse-of = to∘from
}
; left-inverse-of = uncurry from∘to
}
where
to∘from : (xs : List A) → to-list (from-list xs) ≡ xs
to∘from [] = refl _
to∘from (x ∷ xs) = cong (x ∷_) (to∘from xs)
tail′ : A → ∃ (Vec A) ↠ ∃ (Vec A)
tail′ y = record
{ logical-equivalence = record
{ to = λ where
(suc n , _ , xs) → n , xs
xs@(zero , _) → xs
; from = Σ-map suc (y ,_)
}
; right-inverse-of = refl
}
from∘to :
∀ n (xs : Vec A n) →
(length (to-list xs) , from-list (to-list xs)) ≡ (n , xs)
from∘to zero _ = refl _
from∘to (suc n) (x , xs) = $⟨ from∘to n xs ⟩
(length (to-list xs) , from-list (to-list xs)) ≡ (n , xs) ↝⟨ _↠_.from $ ↠-≡ (tail′ x) ⟩□
(length (to-list (x , xs)) , from-list (to-list (x , xs)))
≡
(suc n , x , xs) □
------------------------------------------------------------------------
-- Some properties
-- The map function satisfies the functor laws.
map-id :
{A : Type a} {xs : Vec A n} → map id xs ≡ xs
map-id {n = zero} = refl _
map-id {n = suc n} = cong (_ ,_) map-id
map-∘ :
{A : Type a} {B : Type b} {C : Type c} {f : B → C} {g : A → B}
{xs : Vec A n} →
map (f ∘ g) xs ≡ map f (map g xs)
map-∘ {n = zero} = refl _
map-∘ {n = suc n} = cong (_ ,_) map-∘
-- If f and g are pointwise equal, then map f xs and map g xs are
-- equal.
map-cong :
∀ {n} {xs : Vec A n} →
(∀ x → f x ≡ g x) → map f xs ≡ map g xs
map-cong {n = zero} _ = refl _
map-cong {n = suc n} hyp = cong₂ _,_ (hyp _) (map-cong hyp)
|
oeis/025/A025905.asm | neoneye/loda-programs | 11 | 104319 | ; A025905: Expansion of 1/((1-x^6)(1-x^9)(1-x^11)).
; 1,0,0,0,0,0,1,0,0,1,0,1,1,0,0,1,0,1,2,0,1,1,1,1,2,0,1,2,1,2,2,1,1,3,1,2,3,1,2,3,2,2,4,1,3,4,2,3,4,2,3,5,2,4,5,3,4,5,3,4,6,3,5,6,4,5,7,4,5,7,4,6,8,5,6,8,5,7,9,5
mov $3,2
mov $5,$0
lpb $3
mov $0,$5
sub $3,1
add $0,$3
trn $0,1
seq $0,29114 ; Expansion of 1/((1-x)(1-x^6)(1-x^9)(1-x^11)).
mov $2,$3
mul $2,$0
add $4,$2
lpe
min $5,1
mul $5,$0
mov $0,$4
sub $0,$5
|
data/mapObjects/MtMoonPokecenter.asm | AmateurPanda92/pokemon-rby-dx | 9 | 166580 | MtMoonPokecenter_Object:
db $0 ; border block
db 2 ; warps
warp 3, 7, 0, -1
warp 4, 7, 0, -1
db 0 ; signs
db 6 ; objects
object SPRITE_NURSE, 3, 1, STAY, DOWN, 1 ; person
object SPRITE_BUG_CATCHER, 4, 3, STAY, UP, 2 ; person
object SPRITE_GENTLEMAN, 7, 3, STAY, UP, 3 ; person
object SPRITE_FAT_BALD_GUY, 10, 6, WALK, 2, 4 ; person
object SPRITE_CLIPBOARD, 7, 2, STAY, NONE, 5 ; person
object SPRITE_CABLE_CLUB_WOMAN, 11, 2, STAY, DOWN, 6 ; person
; warp-to
warp_to 3, 7, MT_MOON_POKECENTER_WIDTH
warp_to 4, 7, MT_MOON_POKECENTER_WIDTH
|
other.7z/SFC.7z/SFC/ソースデータ/ヨッシーアイランド/ツール/tool/map/chip/Gdefchr.asm | prismotizm/gigaleak | 0 | 17876 | <gh_stars>0
Name: Gdefchr.asm
Type: file
Size: 7232
Last-Modified: '2016-05-13T04:52:57Z'
SHA-1: 354A3DC58D43C0F2E52E1C4305E6F3B10F11664C
Description: null
|
scripts/Level changes/Master to -inf.applescript | samschloegel/qlab-scripts | 8 | 737 | -- For help, bug reports, or feature suggestions, please visit https://github.com/samschloegel/qlab-scripts
-- Built for QLab 4. v211121-01
tell application id "com.figure53.QLab.4" to tell front workspace
set theSelection to (selected as list)
repeat with eachCue in theSelection
if q type of eachCue is in {"Audio", "Mic", "Fade"} then
eachCue setLevel row 0 column 0 db -120
end if
end repeat
end tell |
grammar/CurrencyConverter.g4 | Andrew-Morozko/currency-converter | 19 | 7585 | <reponame>Andrew-Morozko/currency-converter<gh_stars>10-100
grammar CurrencyConverter;
import CurrencyConverterSymbols;
root: line EOF;
line: implicit_src TO dst | explicit_src dst | implicit_src;
explicit_src: currency expr | expr currency;
implicit_src: explicit_src | expr;
dst: currency;
expr:
num
| '(' expr ')'
| op = SUB right = expr
| left = expr op = POW right = expr
| left = expr op = (MUL | DIV) right = expr
| left = expr op = (ADD | SUB) right = expr
| left = expr op = (ADD | SUB) right_pct = persent_expr;
persent_expr: num PERCENT | '(' expr ')' PERCENT;
num: sepnum;
sepnum: sepnum sepnum | sepnum SEP+ sepnum | SEP+ sepnum | NUM;
currency: name = CURNAME | sym = CURSIGN;
CURNAME: [A-Za-z][A-Za-z][A-Za-z];
NUM: [0-9]+;
SEP: [.,`'];
TO: [tT][oO] | [iI][nN];
ADD: '+';
SUB: '-';
MUL: '*';
DIV: '/';
POW: '^';
PERCENT: '%';
WS: [ \t\n]+ -> skip;
|
1A/S5/PIM/tps/tp1/puissance_mieux.adb | MOUDDENEHamza/ENSEEIHT | 4 | 24430 | with Ada.Text_IO; use Ada.Text_IO;
with Ada.Integer_Text_IO; use Ada.Integer_Text_IO;
with Ada.Float_Text_IO; use Ada.Float_Text_IO;
procedure puissance_mieux is
x, res : Float;
n, p : Integer;
begin
-- Ask number who we will calculate it power with a exponent power.
Put ("Enter your x : ");
Get (x);
res := Float(1);
-- Ask the exponent of the number.
Put ("Enter your exponent : ");
Get (n);
-- Display the power.
for i in 1..abs(n) loop
if n mod 2 = 0 then
p := n / 2;
if n >= 0 then -- If the exponent is greater than 0.
res := (x ** 2) ** p ;
else
res := res * (Float(1) / (x ** 2) ** p);
end if;
else
p := n / 2;
if n >= 0 then -- If the exponent is greater than 0.
res := ((x ** 2) ** p) * x;
else
res := (res / (((x ** 2) ** p) * x));
end if;
end if;
end loop;
Put_Line (Float'Image(res));
end puissance_mieux;
|
firmware/coreboot/3rdparty/libgfxinit/common/hw-gfx-gma-display_probing.ads | fabiojna02/OpenCellular | 1 | 17607 | <filename>firmware/coreboot/3rdparty/libgfxinit/common/hw-gfx-gma-display_probing.ads
--
-- Copyright (C) 2015-2016 secunet Security Networks AG
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
package HW.GFX.GMA.Display_Probing
is
type Port_List_Range is range 0 .. 7;
type Port_List is array (Port_List_Range) of Port_Type;
All_Ports : constant Port_List :=
(DP1, DP2, DP3, HDMI1, HDMI2, HDMI3, Analog, Internal);
procedure Scan_Ports
(Configs : out Pipe_Configs;
Ports : in Port_List := All_Ports;
Max_Pipe : in Pipe_Index := Pipe_Index'Last;
Keep_Power : in Boolean := False);
end HW.GFX.GMA.Display_Probing;
|
s1/music-improved/Mus83 - MZ.asm | Cancer52/flamedriver | 9 | 163506 | <filename>s1/music-improved/Mus83 - MZ.asm
Mus83_MZ_Header:
smpsHeaderStartSong 1
smpsHeaderVoice Mus83_MZ_Voices
smpsHeaderChan $06, $03
smpsHeaderTempo $02, $09
smpsHeaderDAC Mus83_MZ_DAC
smpsHeaderFM Mus83_MZ_FM1, $E8, $15
smpsHeaderFM Mus83_MZ_FM2, $E8, $0E
smpsHeaderFM Mus83_MZ_FM3, $E8, $15
smpsHeaderFM Mus83_MZ_FM4, $E8, $17
smpsHeaderFM Mus83_MZ_FM5, $E8, $17
smpsHeaderPSG Mus83_MZ_PSG1, $D0, $03, $00, fTone_08
smpsHeaderPSG Mus83_MZ_PSG2, $D0, $05, $00, fTone_08
smpsHeaderPSG Mus83_MZ_PSG3, $0B, $03, $00, fTone_09
; FM3 Data
Mus83_MZ_FM3:
smpsAlterNote $02
; FM1 Data
Mus83_MZ_FM1:
smpsSetvoice $00
dc.b nRst, $24
Mus83_MZ_Jump04:
smpsCall Mus83_MZ_Call04
dc.b nA6, $09, nRst, $03, nA6, $06, nG6, nA6, $09, nRst, $03, nA6
dc.b $06, nG6, nA6, $09, nRst, $03, nA6, $06, nG6, nA6, $0C, nB6
dc.b nF6, $12, nE6, $35, nRst, $01
smpsCall Mus83_MZ_Call04
dc.b nA6, $24, nB6, $0C, nAb6, $24, nB6, $09, nRst, $03, nB6, $12
dc.b nA6, $4D, nRst, $61, nRst, $48
smpsJump Mus83_MZ_Jump04
Mus83_MZ_Call04:
dc.b nA5, $06, nB5, nC6, nE6, nB6, $09, nRst, $03, nB6, $06, nA6
dc.b nB6, $09, nRst, $03, nB6, $06, nA6, nB6, $09, nRst, $03, nB6
dc.b $06, nA6, nB6, nA6, nE6, nC6, nG6, $0C, nA6, $06, smpsNoAttack, nF6
dc.b $4D, nRst, $01
smpsReturn
; FM4 Data
Mus83_MZ_FM4:
smpsSetvoice $03
smpsAlterVol $F7
dc.b nRst, $06, nE5, $03, $03, $06, nRst, nE4, $1E
smpsSetvoice $02
smpsAlterVol $09
dc.b nB6, $06
Mus83_MZ_Jump03:
smpsCall Mus83_MZ_Call03
dc.b nA6, $09, nRst, $03, nA6, nRst, nB6, $06, nRst, nA6, $0C, nRst
dc.b $06, nA6, $09, nRst, $03, nA6, nRst, nB6, $06, nRst, nA6, $0C
dc.b nRst, $18, nG6, $03, nRst, $0F, nG6, $03, nRst, $39, nB6, $06
smpsCall Mus83_MZ_Call03
dc.b nF6, $09, nRst, $03, nF6, nRst, nA6, $06, nRst, nF6, $0C, nRst
dc.b $06, nAb6, $09, nRst, $03, nAb6, nRst, nB6, $06, nRst, nAb6, $0C
dc.b nRst, $18, nC7, $03, nRst, $0F, nC7, $03, nRst, $09, nE7, $09
dc.b nRst, $03, nE7, nRst, nD7, $06, nRst, nC7, $03, nRst, nB6, $12
smpsCall Mus83_MZ_Call02
smpsJump Mus83_MZ_Jump03
Mus83_MZ_Call03:
dc.b smpsNoAttack, $03, nRst, nB6, nRst, nC7, $06, nRst, nB6, $0C, nRst, $06
dc.b nB6, $09, nRst, $03, nB6, nRst, nC7, $06, nRst, nB6, $0C, nRst
dc.b $18, nC7, $03, nRst, $0F, nC7, $03, nRst, $1B, nC7, $03, nRst
dc.b $0F, nC7, $03, nRst, $09
smpsReturn
; FM5 Data
Mus83_MZ_FM5:
smpsSetvoice $04
smpsAlterVol $FC
smpsAlterPitch $24
dc.b nRst, $06, nE4, $03, $03, $06, nRst, nE3, $1E
smpsSetvoice $02
smpsAlterPitch $DC
smpsAlterVol $04
dc.b nG6, $06
Mus83_MZ_Jump02:
smpsCall Mus83_MZ_Call01
dc.b nF6, $09, nRst, $03, nF6, nRst, nG6, $06, nRst, nF6, $0C, nRst
dc.b $06, nF6, $09, nRst, $03, nF6, nRst, nG6, $06, nRst, nF6, $0C
dc.b nRst, $18, nE6, $03, nRst, $0F, nE6, $03, nRst, $39, nG6, $06
smpsCall Mus83_MZ_Call01
dc.b nD6, $09, nRst, $03, nD6, nRst, nF6, $06, nRst, nD6, $0C, nRst
dc.b $06, nE6, $09, nRst, $03, nE6, nRst, nAb6, $06, nRst, nE6, $0C
dc.b nRst, $18, nA6, $03, nRst, $0F, nA6, $03, nRst, $09, nC7, $09
dc.b nRst, $03, nC7, nRst, nB6, $06, nRst, nA6, $03, nRst, nAb6, $12
smpsAlterNote $03
smpsCall Mus83_MZ_Call02
smpsAlterNote $00
smpsJump Mus83_MZ_Jump02
Mus83_MZ_Call01:
dc.b smpsNoAttack, $03, nRst, nG6, nRst, nA6, $06, nRst, nG6, $0C, nRst, $06
dc.b nG6, $09, nRst, $03, nG6, nRst, nA6, $06, nRst, nG6, $0C, nRst
dc.b $18, nA6, $03, nRst, $0F, nA6, $03, nRst, $1B, nA6, $03, nRst
dc.b $0F, nA6, $03, nRst, $09
smpsReturn
; FM2 Data
Mus83_MZ_FM2:
smpsSetvoice $01
dc.b nRst, $06, nE4, $03, nE4
smpsNop $01
dc.b nE4, $06, nRst, nE3, $24
Mus83_MZ_Jump01:
smpsCall Mus83_MZ_Call00
Mus83_MZ_Loop00:
dc.b nG3, $03, nRst, nG3, $06, nD4, $03, nRst, nD4, $06, nB3, $03
dc.b nRst, nB3, $06, nD4, $03, nRst, nD4, $06
smpsLoop $01, $02, Mus83_MZ_Loop00
dc.b nC4, $03, nRst, nC4, $06, nG4, $03, nRst, nG4, $06, nE4, $03
dc.b nRst, nE4, $06, nG4, $03, nRst, nG4, $06, nB3, $03, nRst, nB3
dc.b $06, nF4, $03, nRst, nF4, $06, nE4, $03, nRst, nE4, $06, nB3
dc.b $03, nRst, nB3, $06
smpsCall Mus83_MZ_Call00
dc.b nB3, $03, nRst, nB3, $06, nF4, $03, nRst, nF4, $06, nD4, $03
dc.b nRst, nD4, $06, nF4, $03, nRst, nF4, $06, nE4, $03, nRst, nE4
dc.b $06, nB4, $03, nRst, nB4, $06, nAb4, $03, nRst, nAb4, $06, nB4
dc.b $03, nRst, nB4, $06, nA3, $03, nRst, nA3, $06, nE4, $03, nRst
dc.b nE4, $06, nC4, $03, nRst, nC4, $06, nE4, $03, nRst, nE4, $06
dc.b nA3, $03, nRst, nA3, $06, nE4, $03, nRst, nE4, $06, nD4, $03
dc.b nRst, nD4, $06, nE4, $03, nRst, nE4, $06
Mus83_MZ_Loop01:
dc.b nA3, $12, nA3, $06, nG3, $12, nG3, $06, nF3, $12, nF3, $06
dc.b nG3, $12, nG3, $06
smpsLoop $01, $02, Mus83_MZ_Loop01
smpsNop $01
smpsJump Mus83_MZ_Jump01
Mus83_MZ_Call00:
dc.b nA3, $03, nRst, nA3, $06, nE4, $03, nRst, nE4, $06, nD4, $03
dc.b nRst, nD4, $06, nE4, $03, nRst, nE4, $06
smpsLoop $00, $02, Mus83_MZ_Call00
Mus83_MZ_Loop05:
dc.b nD4, $03, nRst, nD4, $06, nA4, $03, nRst, nA4, $06, nF4, $03
dc.b nRst, nF4, $06, nA4, $03, nRst, nA4, $06
smpsLoop $00, $02, Mus83_MZ_Loop05
smpsReturn
; PSG1 Data
Mus83_MZ_PSG1:
dc.b nRst, $3C
Mus83_MZ_Jump06:
dc.b nRst, $60
smpsCall Mus83_MZ_Call06
dc.b nRst, $2A, nF7, $0C, nF7, $06, nD7, $0C, nB6, $06, nAb6, $2A
dc.b nRst, $48
smpsCall Mus83_MZ_Call06
dc.b nRst, $60
Mus83_MZ_Loop03:
dc.b nA6, $06, nC7, $03, nA6, nC7, $06, nA6, nB6, nG6, nD6, nB6
dc.b nF6, nA6, $03, nF6, nA6, $06, nF6, nG6, nA6, nB6, nG6
smpsLoop $00, $02, Mus83_MZ_Loop03
smpsJump Mus83_MZ_Jump06
Mus83_MZ_Call06:
dc.b nRst, $30, nF7, $03, nD7, nA6, nF6, nD7, nA6, nF6, nD6, nA6
dc.b nF6, nD6, nA5, nF6, nD6, nA5, nF5, $27, nRst, $3C
smpsReturn
; PSG2 Data
Mus83_MZ_PSG2:
dc.b nRst, $02
smpsAlterNote $01
smpsJump Mus83_MZ_PSG1
; PSG3 Data
Mus83_MZ_PSG3:
smpsPSGform $E7
smpsPSGAlterVol $FF
; These first three notes are too high when combined with this track's
; transposition value, causing them to overflow the PSG frequency table
; and play invalid notes. In the Sonic 1 prototype, this problem was
; even worse as there were smpsChangeTransposition commands around the
; following line that raised the notes yet another octave higher,
; causing the fourth note to break too.
; Since the commands are gone now, we can assume that this was the
; developers' intended solution, though it unfortunately only fixed the
; fourth note. So, in order to fix the bug for good, the notes on the
; following line have to be lowered by yet another octave.
;dc.b nRst, $06, nE5, $03, $03, $06, nRst, nE4, $24
dc.b nRst, $06, nE4, $03, $03, $06, nRst, nE3, $24 ; Fixed
smpsPSGAlterVol $01
Mus83_MZ_Jump05:
smpsCall Mus83_MZ_Call05
dc.b nG3, nG3, nD4, nD4, nB3, nB3, nD4, nD4, nG3, nG3, nD4, nD4
dc.b nB3, nB3, nD4, nD4, nC4, nC4, nG4, nG4, nE4, nE4, nG4, nG4
dc.b nB3, nB3, nF4, nF4, nE4, nE4, nB3, nB3
smpsCall Mus83_MZ_Call05
dc.b nB3, nB3, nF4, nF4, nD4, nD4, nF4, nF4, nE4, nE4, nB4, nB4
dc.b nAb4, nAb4, nB4, nB4, nA3, nA3, nE4, nE4, nC4, nC4, nE4, nE4
dc.b nA3, nA3, nE4, nE4, nD4, nD4, nE4, nE4
smpsPSGAlterVol $FF
Mus83_MZ_Loop02:
dc.b nA4, $12, nA4, $06, nG4, $12, nG4, $06, nF4, $12, nF4, $06
dc.b nG4, $12, nG4, $06
smpsLoop $00, $02, Mus83_MZ_Loop02
smpsPSGAlterVol $01
smpsJump Mus83_MZ_Jump05
Mus83_MZ_Call05:
dc.b nA3, $06, nA3, nE4, nE4, nD4, nD4, nE4, nE4, nA3, nA3, nE4
dc.b nE4, nD4, nD4, nE4, nE4, nD4, nD4, nA4, nA4, nF4, nF4, nA4
dc.b nA4, nD4, nD4, nA4, nA4, nF4, nF4, nA4, nA4
smpsReturn
; DAC Data
Mus83_MZ_DAC:
dc.b nRst, $06, dSnare, $03, $03, $0C, dKick, $0C, $0C, $0C
Mus83_MZ_Jump00:
dc.b dKick, $0C
smpsJump Mus83_MZ_Jump00
Mus83_MZ_Call02:
smpsNoteFill $06
Mus83_MZ_Loop04:
dc.b nRst, $06, nE7, nC7, nA6, $0C, nD7, $06, nB6, nG6, nRst, nC7
dc.b nA6, nF6, $0C, nD7, $06, nB6, nG6
smpsLoop $00, $02, Mus83_MZ_Loop04
smpsNoteFill $00
smpsReturn
Mus83_MZ_Voices:
; Voice $00
; $22
; $0A, $13, $05, $11, $03, $12, $12, $11, $00, $13, $13, $00
; $03, $02, $02, $01, $1F, $1F, $0F, $0F, $1E, $18, $26, $81
smpsVcAlgorithm $02
smpsVcFeedback $04
smpsVcUnusedBits $00
smpsVcDetune $01, $00, $01, $00
smpsVcCoarseFreq $01, $05, $03, $0A
smpsVcRateScale $00, $00, $00, $00
smpsVcAttackRate $11, $12, $12, $03
smpsVcAmpMod $00, $00, $00, $00
smpsVcDecayRate1 $00, $13, $13, $00
smpsVcDecayRate2 $01, $02, $02, $03
smpsVcDecayLevel $00, $00, $01, $01
smpsVcReleaseRate $0F, $0F, $0F, $0F
smpsVcTotalLevel $01, $26, $18, $1E
; Voice $01
; $3A
; $61, $3C, $14, $31, $9C, $DB, $9C, $DA, $04, $09, $04, $03
; $03, $01, $03, $00, $1F, $0F, $0F, $AF, $21, $47, $31, $80
smpsVcAlgorithm $02
smpsVcFeedback $07
smpsVcUnusedBits $00
smpsVcDetune $03, $01, $03, $06
smpsVcCoarseFreq $01, $04, $0C, $01
smpsVcRateScale $03, $02, $03, $02
smpsVcAttackRate $1A, $1C, $1B, $1C
smpsVcAmpMod $00, $00, $00, $00
smpsVcDecayRate1 $03, $04, $09, $04
smpsVcDecayRate2 $00, $03, $01, $03
smpsVcDecayLevel $0A, $00, $00, $01
smpsVcReleaseRate $0F, $0F, $0F, $0F
smpsVcTotalLevel $00, $31, $47, $21
; Voice $02
; $3A
; $01, $07, $01, $01, $8E, $8E, $8D, $53, $0E, $0E, $0E, $03
; $00, $00, $00, $00, $1F, $FF, $1F, $0F, $18, $28, $27, $80
smpsVcAlgorithm $02
smpsVcFeedback $07
smpsVcUnusedBits $00
smpsVcDetune $00, $00, $00, $00
smpsVcCoarseFreq $01, $01, $07, $01
smpsVcRateScale $01, $02, $02, $02
smpsVcAttackRate $13, $0D, $0E, $0E
smpsVcAmpMod $00, $00, $00, $00
smpsVcDecayRate1 $03, $0E, $0E, $0E
smpsVcDecayRate2 $00, $00, $00, $00
smpsVcDecayLevel $00, $01, $0F, $01
smpsVcReleaseRate $0F, $0F, $0F, $0F
smpsVcTotalLevel $00, $27, $28, $18
; Voice $03
; $23
; $7C, $32, $00, $00, $5F, $58, $DC, $DF, $04, $0B, $04, $04
; $06, $0C, $08, $08, $1F, $1F, $BF, $BF, $24, $26, $16, $80
smpsVcAlgorithm $03
smpsVcFeedback $04
smpsVcUnusedBits $00
smpsVcDetune $00, $00, $03, $07
smpsVcCoarseFreq $00, $00, $02, $0C
smpsVcRateScale $03, $03, $01, $01
smpsVcAttackRate $1F, $1C, $18, $1F
smpsVcAmpMod $00, $00, $00, $00
smpsVcDecayRate1 $04, $04, $0B, $04
smpsVcDecayRate2 $08, $08, $0C, $06
smpsVcDecayLevel $0B, $0B, $01, $01
smpsVcReleaseRate $0F, $0F, $0F, $0F
smpsVcTotalLevel $00, $16, $26, $24
; Voice $04
; $02
; $3C, $32, $55, $51, $1F, $98, $1F, $9F, $0F, $11, $0E, $11
; $0E, $05, $08, $05, $5F, $0F, $6F, $0F, $2D, $2D, $2F, $80
smpsVcAlgorithm $02
smpsVcFeedback $00
smpsVcUnusedBits $00
smpsVcDetune $05, $05, $03, $03
smpsVcCoarseFreq $01, $05, $02, $0C
smpsVcRateScale $02, $00, $02, $00
smpsVcAttackRate $1F, $1F, $18, $1F
smpsVcAmpMod $00, $00, $00, $00
smpsVcDecayRate1 $11, $0E, $11, $0F
smpsVcDecayRate2 $05, $08, $05, $0E
smpsVcDecayLevel $00, $06, $00, $05
smpsVcReleaseRate $0F, $0F, $0F, $0F
smpsVcTotalLevel $00, $2F, $2D, $2D
|
oeis/037/A037643.asm | neoneye/loda-programs | 11 | 101616 | ; A037643: Base 8 digits are, in order, the first n terms of the periodic sequence with initial period 2,3,1.
; Submitted by <NAME>
; 2,19,153,1226,9811,78489,627914,5023315,40186521,321492170,2571937363,20575498905,164603991242,1316831929939,10534655439513,84277243516106,674217948128851,5393743585030809
seq $0,33135 ; Base 8 digits are, in order, the first n terms of the periodic sequence with initial period 1,1,0.
mul $0,17
div $0,8
|
libsrc/_DEVELOPMENT/arch/ts2068/misc/z80/asm_tshr_cls.asm | jpoikela/z88dk | 640 | 162674 | <filename>libsrc/_DEVELOPMENT/arch/ts2068/misc/z80/asm_tshr_cls.asm
; ===============================================================
; 2017
; ===============================================================
;
; void tshr_cls(uchar paper)
;
; Clear screen using paper colour.
;
; ===============================================================
INCLUDE "config_private.inc"
SECTION code_clib
SECTION code_arch
PUBLIC asm_tshr_cls
EXTERN asm_tshr_cls_attr
EXTERN asm_tshr_cls_pix
asm_tshr_cls:
; enter : l = attr
;
; uses : af, bc, de, hl
push hl
ld l,0
call asm_tshr_cls_pix
pop hl
jp asm_tshr_cls_attr
|
BreadthFirstWithoutProof.agda | nad/codata | 1 | 6159 | ------------------------------------------------------------------------
-- Breadth-first labelling of trees
------------------------------------------------------------------------
-- This module just defines breadth-first labelling. For a full
-- development including a specification and proof, see BreadthFirst.
module BreadthFirstWithoutProof where
open import Codata.Musical.Notation
open import Codata.Musical.Stream
open import Data.Product
open import Tree using (Tree; leaf; node)
------------------------------------------------------------------------
-- Universe
data U : Set₁ where
tree : (a : U) → U
stream : (a : U) → U
_⊗_ : (a b : U) → U
⌈_⌉ : (A : Set) → U
El : U → Set
El (tree a) = Tree (El a)
El (stream a) = Stream (El a)
El (a ⊗ b) = El a × El b
El ⌈ A ⌉ = A
------------------------------------------------------------------------
-- Programs
infixr 5 _∷_
infixr 4 _,_
mutual
data ElP : U → Set₁ where
↓ : ∀ {a} (w : ElW a) → ElP a
fst : ∀ {a b} (p : ElP (a ⊗ b)) → ElP a
snd : ∀ {a b} (p : ElP (a ⊗ b)) → ElP b
lab : ∀ {A B} (t : Tree A) (bss : ElP (stream ⌈ Stream B ⌉)) →
ElP (tree ⌈ B ⌉ ⊗ stream ⌈ Stream B ⌉)
-- The term WHNF is a bit of a misnomer here; only recursive
-- /coinductive/ arguments are suspended (in the form of programs).
data ElW : U → Set₁ where
leaf : ∀ {a} → ElW (tree a)
node : ∀ {a}
(l : ∞ (ElP (tree a))) (x : ElW a) (r : ∞ (ElP (tree a))) →
ElW (tree a)
_∷_ : ∀ {a} (x : ElW a) (xs : ∞ (ElP (stream a))) → ElW (stream a)
_,_ : ∀ {a b} (x : ElW a) (y : ElW b) → ElW (a ⊗ b)
⌈_⌉ : ∀ {A} (x : A) → ElW ⌈ A ⌉
fstW : ∀ {a b} → ElW (a ⊗ b) → ElW a
fstW (x , y) = x
sndW : ∀ {a b} → ElW (a ⊗ b) → ElW b
sndW (x , y) = y
-- Uses the n-th stream to label the n-th level in the tree. Returns
-- the remaining stream elements (for every level).
labW : ∀ {A B} → Tree A → ElW (stream ⌈ Stream B ⌉) →
ElW (tree ⌈ B ⌉ ⊗ stream ⌈ Stream B ⌉)
labW leaf bss = (leaf , bss)
labW (node l _ r) (⌈ b ∷ bs ⌉ ∷ bss) =
(node (♯ fst x) ⌈ b ⌉ (♯ fst y) , ⌈ ♭ bs ⌉ ∷ ♯ snd y)
where
x = lab (♭ l) (♭ bss)
y = lab (♭ r) (snd x)
whnf : ∀ {a} → ElP a → ElW a
whnf (↓ w) = w
whnf (fst p) = fstW (whnf p)
whnf (snd p) = sndW (whnf p)
whnf (lab t bss) = labW t (whnf bss)
mutual
⟦_⟧W : ∀ {a} → ElW a → El a
⟦ leaf ⟧W = leaf
⟦ node l x r ⟧W = node (♯ ⟦ ♭ l ⟧P) ⟦ x ⟧W (♯ ⟦ ♭ r ⟧P)
⟦ x ∷ xs ⟧W = ⟦ x ⟧W ∷ ♯ ⟦ ♭ xs ⟧P
⟦ (x , y) ⟧W = (⟦ x ⟧W , ⟦ y ⟧W)
⟦ ⌈ x ⌉ ⟧W = x
⟦_⟧P : ∀ {a} → ElP a → El a
⟦ p ⟧P = ⟦ whnf p ⟧W
------------------------------------------------------------------------
-- Breadth-first labelling
label′ : ∀ {A B} → Tree A → Stream B →
ElP (tree ⌈ B ⌉ ⊗ stream ⌈ Stream B ⌉)
label′ t bs = lab t (↓ (⌈ bs ⌉ ∷ ♯ snd (label′ t bs)))
label : ∀ {A B} → Tree A → Stream B → Tree B
label t bs = ⟦ fst (label′ t bs) ⟧P
|
out/bootblock.asm | harveydong/learning-xv6 | 0 | 166661 |
out/bootblock.o: file format elf32-i386
Disassembly of section .text:
00007c00 <start>:
7c00: fa cli
7c01: 31 c0 xor %eax,%eax
7c03: 8e d8 mov %eax,%ds
7c05: 8e c0 mov %eax,%es
7c07: 8e d0 mov %eax,%ss
7c09: b8 00 7c 89 c4 mov $0xc4897c00,%eax
00007c0e <seta20.1>:
7c0e: e4 64 in $0x64,%al
7c10: a8 02 test $0x2,%al
7c12: 75 fa jne 7c0e <seta20.1>
7c14: b0 d1 mov $0xd1,%al
7c16: e6 64 out %al,$0x64
00007c18 <seta20.2>:
7c18: e4 64 in $0x64,%al
7c1a: a8 02 test $0x2,%al
7c1c: 75 fa jne 7c18 <seta20.2>
7c1e: b0 df mov $0xdf,%al
7c20: e6 60 out %al,$0x60
7c22: 88 16 mov %dl,(%esi)
7c24: 65 7c b4 gs jl 7bdb <start-0x25>
7c27: 42 inc %edx
7c28: 8a 16 mov (%esi),%dl
7c2a: 65 7c be gs jl 7beb <start-0x15>
7c2d: ca 7c cd lret $0xcd7c
7c30: 13 72 57 adc 0x57(%edx),%esi
7c33: 0f 01 16 lgdtl (%esi)
7c36: b4 7c mov $0x7c,%ah
7c38: 0f 20 c0 mov %cr0,%eax
7c3b: 66 83 c8 01 or $0x1,%ax
7c3f: 0f 22 c0 mov %eax,%cr0
7c42: ea .byte 0xea
7c43: 47 inc %edi
7c44: 7c 08 jl 7c4e <start32+0x7>
...
00007c47 <start32>:
7c47: 66 b8 10 00 mov $0x10,%ax
7c4b: 8e d8 mov %eax,%ds
7c4d: 8e c0 mov %eax,%es
7c4f: 8e d0 mov %eax,%ss
7c51: 66 b8 00 00 mov $0x0,%ax
7c55: 8e e0 mov %eax,%fs
7c57: 8e e8 mov %eax,%gs
7c59: bc 00 7c 00 00 mov $0x7c00,%esp
7c5e: e8 77 00 00 00 call 7cda <bootmain>
00007c63 <spin>:
7c63: eb fe jmp 7c63 <spin>
00007c65 <DriveNumber>:
...
00007c66 <msg_ReadFail>:
7c66: 46 inc %esi
7c67: 61 popa
7c68: 69 6c 65 64 20 74 6f imul $0x206f7420,0x64(%ebp,%eiz,2),%ebp
7c6f: 20
7c70: 72 65 jb 7cd7 <ST3_DAP+0xd>
7c72: 61 popa
7c73: 64 20 64 72 69 and %ah,%fs:0x69(%edx,%esi,2)
7c78: 76 65 jbe 7cdf <bootmain+0x5>
7c7a: 2e cs
...
00007c7c <print_string_16>:
7c7c: 60 pusha
7c7d: b4 0e mov $0xe,%ah
00007c7f <.repeat>:
7c7f: ac lods %ds:(%esi),%al
7c80: 3c 00 cmp $0x0,%al
7c82: 74 04 je 7c88 <.done>
7c84: cd 10 int $0x10
7c86: eb f7 jmp 7c7f <.repeat>
00007c88 <.done>:
7c88: 61 popa
7c89: c3 ret
00007c8a <read_fail>:
7c8a: 66 8b 35 66 7c 00 00 mov 0x7c66,%si
7c91: e8 e6 ff ff ff call 7c7c <print_string_16>
7c96: eb 00 jmp 7c98 <halt>
00007c98 <halt>:
7c98: f4 hlt
7c99: eb fd jmp 7c98 <halt>
7c9b: 90 nop
00007c9c <gdt>:
...
7ca4: ff (bad)
7ca5: ff 00 incl (%eax)
7ca7: 00 00 add %al,(%eax)
7ca9: 9a cf 00 ff ff 00 00 lcall $0x0,$0xffff00cf
7cb0: 00 .byte 0x0
7cb1: 92 xchg %eax,%edx
7cb2: cf iret
...
00007cb4 <gdtdesc>:
7cb4: 17 pop %ss
7cb5: 00 .byte 0x0
7cb6: 9c pushf
7cb7: 7c 00 jl 7cb9 <gdtdesc+0x5>
...
00007cba <ST2_DAP>:
7cba: 10 00 adc %al,(%eax)
7cbc: 10 00 adc %al,(%eax)
7cbe: 00 80 00 00 01 00 add %al,0x10000(%eax)
7cc4: 00 00 add %al,(%eax)
7cc6: 00 00 add %al,(%eax)
...
00007cca <ST3_DAP>:
7cca: 10 00 adc %al,(%eax)
7ccc: 64 00 00 add %al,%fs:(%eax)
7ccf: 00 00 add %al,(%eax)
7cd1: 10 01 adc %al,(%ecx)
7cd3: 00 00 add %al,(%eax)
7cd5: 00 00 add %al,(%eax)
7cd7: 00 00 add %al,(%eax)
...
00007cda <bootmain>:
7cda: 55 push %ebp
7cdb: ba 00 00 01 00 mov $0x10000,%edx
7ce0: 89 e5 mov %esp,%ebp
7ce2: 57 push %edi
7ce3: 56 push %esi
7ce4: 53 push %ebx
7ce5: 31 f6 xor %esi,%esi
7ce7: 83 ec 1c sub $0x1c,%esp
7cea: c6 05 00 80 0b 00 61 movb $0x61,0xb8000
7cf1: c6 05 02 80 0b 00 61 movb $0x61,0xb8002
7cf8: c6 05 04 80 0b 00 61 movb $0x61,0xb8004
7cff: c6 05 06 80 0b 00 61 movb $0x61,0xb8006
7d06: c6 05 08 80 0b 00 61 movb $0x61,0xb8008
7d0d: 81 3a 02 b0 ad 1b cmpl $0x1badb002,(%edx)
7d13: 75 10 jne 7d25 <bootmain+0x4b>
7d15: 8b 42 04 mov 0x4(%edx),%eax
7d18: 8b 4a 08 mov 0x8(%edx),%ecx
7d1b: 01 c1 add %eax,%ecx
7d1d: 81 f9 fe 4f 52 e4 cmp $0xe4524ffe,%ecx
7d23: 74 0e je 7d33 <bootmain+0x59>
7d25: 46 inc %esi
7d26: 83 c2 04 add $0x4,%edx
7d29: 81 fe 00 08 00 00 cmp $0x800,%esi
7d2f: 75 dc jne 7d0d <bootmain+0x33>
7d31: eb 58 jmp 7d8b <bootmain+0xb1>
7d33: a9 00 00 01 00 test $0x10000,%eax
7d38: 74 51 je 7d8b <bootmain+0xb1>
7d3a: 8b 7a 10 mov 0x10(%edx),%edi
7d3d: 8b 5a 0c mov 0xc(%edx),%ebx
7d40: 39 df cmp %ebx,%edi
7d42: 77 47 ja 7d8b <bootmain+0xb1>
7d44: 8b 42 14 mov 0x14(%edx),%eax
7d47: 39 c7 cmp %eax,%edi
7d49: 77 40 ja 7d8b <bootmain+0xb1>
7d4b: 29 f8 sub %edi,%eax
7d4d: 89 c1 mov %eax,%ecx
7d4f: c1 e9 02 shr $0x2,%ecx
7d52: 89 4d e4 mov %ecx,-0x1c(%ebp)
7d55: 89 f9 mov %edi,%ecx
7d57: 29 d9 sub %ebx,%ecx
7d59: 8d b4 b1 00 00 01 00 lea 0x10000(%ecx,%esi,4),%esi
7d60: 8b 4d e4 mov -0x1c(%ebp),%ecx
7d63: f3 a5 rep movsl %ds:(%esi),%es:(%edi)
7d65: 89 c1 mov %eax,%ecx
7d67: 83 e1 03 and $0x3,%ecx
7d6a: 74 02 je 7d6e <bootmain+0x94>
7d6c: f3 a4 rep movsb %ds:(%esi),%es:(%edi)
7d6e: 8b 4a 18 mov 0x18(%edx),%ecx
7d71: 8b 7a 14 mov 0x14(%edx),%edi
7d74: 39 f9 cmp %edi,%ecx
7d76: 76 07 jbe 7d7f <bootmain+0xa5>
7d78: 29 f9 sub %edi,%ecx
7d7a: 31 c0 xor %eax,%eax
7d7c: fc cld
7d7d: f3 aa rep stos %al,%es:(%edi)
7d7f: 8b 42 1c mov 0x1c(%edx),%eax
7d82: 83 c4 1c add $0x1c,%esp
7d85: 5b pop %ebx
7d86: 5e pop %esi
7d87: 5f pop %edi
7d88: 5d pop %ebp
7d89: ff e0 jmp *%eax
7d8b: 83 c4 1c add $0x1c,%esp
7d8e: 5b pop %ebx
7d8f: 5e pop %esi
7d90: 5f pop %edi
7d91: 5d pop %ebp
7d92: c3 ret
|
text/textsBetween.applescript | adriannier/applescript-functions | 7 | 437 | textsBetween("<a href=\"a\"></a><a href=\"b\"></a><a href=\"c\"></a><a href=\" \"", "<a href=\"", "\"")
on textsBetween(str, a, b)
(* Returns substrings between a start string and an end string *)
try
set aLength to length of a
set bLength to length of b
set buffer to str
set matches to {}
repeat
set aOffset to offset of a in buffer
if aOffset is 0 then
-- No more matches for a
exit repeat
else
try
set buffer to text (aOffset + aLength) thru -1 of buffer
on error
-- End of string
set buffer to ""
end try
set bOffset to offset of b in buffer
if bOffset is 0 then
-- No more matches for b
exit repeat
else
if bOffset is 1 then
-- Empty string
set match to ""
else
set match to text 1 thru (bOffset - 1) of buffer
end if
set end of matches to match
try
set buffer to text (bOffset + bLength) thru -1 of buffer
on error
-- End of string
set buffer to ""
end try
end if
end if
end repeat
return matches
on error eMsg number eNum
error "textsBetween: " & eMsg number eNum
end try
end textsBetween
|
oeis/142/A142395.asm | neoneye/loda-programs | 11 | 6204 | <gh_stars>10-100
; A142395: Primes congruent to 44 mod 47.
; Submitted by <NAME>(s4)
; 373,467,937,1031,1783,1877,2347,2441,3851,4133,4603,5167,5261,5449,6389,6577,7517,8081,8269,8363,9209,9397,9491,9679,10243,10337,12781,13063,13627,13721,15131,15319,15413,15601,16447,16729,16823,17011,17293,17387,17669,18233,18797,19079,19267,20113,20771,20959,21523,21617,22369,22651,23027,23497,23873,24061,24907,25189,25471,25847,26317,26693,26881,27539,28573,28949,29137,29231,29983,30829,31393,31769,31957,32051,32803,33179,33461,33931,34213,34589,34871,35059,35153,35999,36187,36469,36563
mov $1,16
mov $2,$0
add $2,2
pow $2,2
lpb $2
add $1,32
mul $1,2
sub $2,1
mov $3,$1
sub $3,6
seq $3,10051 ; Characteristic function of primes: 1 if n is prime, else 0.
sub $0,$3
add $1,31
div $1,2
mov $4,$0
max $4,0
cmp $4,$0
mul $2,$4
lpe
mov $0,$1
sub $0,131
mul $0,2
add $0,227
|
src/labels.adb | python36/d0xfa | 0 | 1949 | package body labels is
function last_label return label_t is
begin
return last;
end last_label;
function get_by_name (str : string) return label_t is
cur : labels_t.cursor := labels_t.find(labels, str);
begin
if cur = labels_t.no_element then
return null_label;
end if;
return (cursor => cur);
end get_by_name;
function create (str : string; addr : pos_addr_t := null_pos_addr) return label_t is
cur : labels_t.cursor;
tb : boolean;
begin
labels_t.insert(labels, str, addr, cur, tb);
if not tb then
raise error_label_exist;
end if;
last := (cursor => cur);
return last_label;
end create;
procedure create (str : string; addr : pos_addr_t := null_pos_addr) is
begin
void(create(str, addr));
end create;
procedure set (label : label_t; addr : pos_addr_t) is
begin
if label.cursor = labels_t.no_element then
raise error_label_is_null;
end if;
labels_t.replace_element(labels, label.cursor, addr);
end set;
function set (label : label_t; addr : pos_addr_t) return label_t is
begin
set(label, addr);
return label;
end set;
function get (label : label_t) return pos_addr_t is
begin
if label.cursor = labels_t.no_element then
raise error_label_is_null;
end if;
return labels_t.element(label.cursor);
end get;
function name (label : label_t) return string is
begin
if label.cursor = labels_t.no_element then
raise error_label_is_null;
end if;
return labels_t.key(label.cursor);
end name;
procedure void (label : label_t) is
begin
null;
end void;
end labels; |
projects/batfish/src/main/antlr4/org/batfish/grammar/arista/Legacy_routemap.g4 | sc68cal/batfish | 0 | 5124 | <filename>projects/batfish/src/main/antlr4/org/batfish/grammar/arista/Legacy_routemap.g4
parser grammar Legacy_routemap;
import Legacy_common;
options {
tokenVocab = AristaLexer;
}
as_expr
:
dec
| AUTO
;
continue_rm_stanza
:
CONTINUE dec? NEWLINE
;
ip_policy_list_stanza
:
IP POLICY_LIST name = variable access_list_action NEWLINE match_rm_stanza*
;
match_as_number_rm_stanza
:
AS_NUMBER num = dec NEWLINE
;
match_as_path_access_list_rm_stanza
:
AS_PATH
(
name_list += variable
)+ NEWLINE
;
match_as_rm_stanza
:
MATCH AS num = dec NEWLINE
;
match_community_list_rm_stanza
:
COMMUNITY
(
name_list += variable
)+ NEWLINE
;
match_extcommunity_rm_stanza
:
EXTCOMMUNITY
(
name_list += variable
)+ NEWLINE
;
match_interface_rm_stanza
:
INTERFACE interface_name+ NEWLINE
;
match_ip_access_list_rm_stanza
:
IP ADDRESS
(
name_list += variable_access_list
)+ NEWLINE
;
match_ipv6_access_list_rm_stanza
:
IPV6 ADDRESS
(
name_list += variable_access_list
)+ NEWLINE
;
match_ip_multicast_rm_stanza
:
IP MULTICAST null_rest_of_line
;
match_ip_next_hop_rm_stanza_null
:
IP NEXT_HOP
(
NULL
) NEWLINE
;
match_ip_prefix_list_rm_stanza
:
IP ADDRESS IP? PREFIX_LIST
(
name_list += variable
)+ NEWLINE
;
match_ip_route_source_rm_stanza
:
IP ROUTE_SOURCE src = dec NEWLINE
;
match_ipv6_prefix_list_rm_stanza
:
IPV6 ADDRESS PREFIX_LIST
(
name_list += variable
)+ NEWLINE
;
match_length_rm_stanza
:
LENGTH null_rest_of_line
;
match_policy_list_rm_stanza
:
POLICY_LIST
(
name_list += variable
)+ NEWLINE
;
match_route_type_rm_stanza
:
ROUTE_TYPE variable NEWLINE
;
match_source_protocol_rm_stanza
:
SOURCE_PROTOCOL
(
BGP (bgpasn = bgp_asn)?
| CONNECTED
| ISIS
| OSPF (area = dec)?
| RIP
| STATIC
)+ NEWLINE
;
match_rm_stanza
:
MATCH
(
match_as_number_rm_stanza
| match_as_path_access_list_rm_stanza
| match_as_rm_stanza
| match_community_list_rm_stanza
| match_extcommunity_rm_stanza
| match_interface_rm_stanza
| match_ip_access_list_rm_stanza
| match_ip_multicast_rm_stanza
| match_ip_next_hop_rm_stanza_null
| match_ip_prefix_list_rm_stanza
| match_ip_route_source_rm_stanza
| match_ipv6_access_list_rm_stanza
| match_ipv6_prefix_list_rm_stanza
| match_length_rm_stanza
| match_policy_list_rm_stanza
| match_route_type_rm_stanza
| match_source_protocol_rm_stanza
| match_tag_rm_stanza
)
;
match_tag_rm_stanza
:
TAG (tag_list += uint32)+ NEWLINE
;
no_route_map_stanza
:
NO ROUTE_MAP name = variable NEWLINE
;
null_rm_stanza
:
NO?
(
DESCRIPTION
| SUB_ROUTE_MAP
) null_rest_of_line
;
origin_expr_literal
:
(
EGP bgp_asn
)
| IGP
| INCOMPLETE
;
rm_stanza
:
continue_rm_stanza
| match_rm_stanza
| null_rm_stanza
| rm_set
;
route_map_stanza
:
// Both action and number are optional but number must come with action
ROUTE_MAP name = variable (rmt = access_list_action (num = dec)?)? NEWLINE
rm_stanza*
;
set_as_path_prepend_rm_stanza
:
AS_PATH PREPEND LAST_AS?
(
as_list += as_expr
)+ NEWLINE
;
set_as_path_tag_rm_stanza
:
AS_PATH TAG NEWLINE
;
set_comm_list_delete_rm_stanza
:
COMM_LIST name = variable DELETE NEWLINE
;
set_community_additive_rm_stanza
:
COMMUNITY
(
(
ADD
(
communities += literal_standard_community
)+
)
|
(
(
communities += literal_standard_community
)+ ADDITIVE
)
) NEWLINE
;
set_community_list_additive_rm_stanza
:
COMMUNITY COMMUNITY_LIST
(
comm_lists += variable
)+ ADDITIVE NEWLINE
;
set_community_list_rm_stanza
:
COMMUNITY COMMUNITY_LIST
(
comm_lists += variable
)+ NEWLINE
;
set_community_none_rm_stanza
:
COMMUNITY NONE NEWLINE
;
set_community_rm_stanza
:
COMMUNITY
(
communities += literal_standard_community
)+ NEWLINE
;
set_extcommunity_rm_stanza
:
EXTCOMMUNITY
(
COST
| RT
) extended_community NEWLINE
;
set_interface_rm_stanza
:
INTERFACE null_rest_of_line
;
set_ip_default_nexthop_stanza
:
IP DEFAULT NEXT_HOP nhip = IP_ADDRESS NEWLINE
;
set_ip_df_rm_stanza
:
IP DF null_rest_of_line
;
set_ip_precedence_stanza
:
IP PRECEDENCE
(
val = DIGIT
| CRITICAL
| FLASH
| FLASH_OVERRIDE
| IMMEDIATE
| INTERNET
| NETWORK
| PRIORITY
| ROUTE
) NEWLINE
;
set_ipv6_rm_stanza
:
IPV6 null_rest_of_line
;
set_local_preference_rm_stanza
:
LOCAL_PREFERENCE pref = int_expr NEWLINE
;
set_metric_rm_stanza
:
METRIC metric = int_expr NEWLINE
;
set_metric_type_rm_stanza
:
METRIC_TYPE type = variable NEWLINE
;
set_mpls_label_rm_stanza
:
MPLS_LABEL NEWLINE
;
set_next_hop_peer_address_stanza
:
IP NEXT_HOP PEER_ADDRESS NEWLINE
;
set_next_hop_rm_stanza
:
IP? NEXT_HOP
(
nexthop_list += IP_ADDRESS
)+ NEWLINE
;
set_nlri_rm_stanza_null
:
NLRI
(
UNICAST
| MULTICAST
)+ NEWLINE
;
set_origin_rm_stanza
:
ORIGIN origin_expr_literal NEWLINE
;
set_tag_rm_stanza
:
TAG tag = uint32 NEWLINE
;
set_traffic_index_rm_stanza_null
:
TRAFFIC_INDEX index = dec NEWLINE
;
set_weight_rm_stanza
:
WEIGHT weight = dec NEWLINE
;
rm_set
:
SET
(
// EOS up here
rms_distance
// Legacy below
| set_as_path_prepend_rm_stanza
| set_as_path_tag_rm_stanza
| set_comm_list_delete_rm_stanza
| set_community_rm_stanza
| set_community_additive_rm_stanza
| set_community_list_additive_rm_stanza
| set_community_list_rm_stanza
| set_community_none_rm_stanza
| set_extcommunity_rm_stanza
| set_interface_rm_stanza
| set_ip_default_nexthop_stanza
| set_ip_df_rm_stanza
| set_ip_precedence_stanza
| set_ipv6_rm_stanza
| set_local_preference_rm_stanza
| set_metric_rm_stanza
| set_metric_type_rm_stanza
| set_mpls_label_rm_stanza
| set_next_hop_peer_address_stanza
| set_next_hop_rm_stanza
| set_nlri_rm_stanza_null
| set_origin_rm_stanza
| set_tag_rm_stanza
| set_traffic_index_rm_stanza_null
| set_weight_rm_stanza
)
;
rms_distance
:
// 1-255
DISTANCE distance = dec NEWLINE
;
variable_access_list
:
~( IP | IPV6 | NEWLINE | PREFIX_LIST )
;
|
oeis/025/A025973.asm | neoneye/loda-programs | 11 | 101514 | <gh_stars>10-100
; A025973: Expansion of 1/((1-2x)(1-4x)(1-7x)(1-10x)).
; Submitted by <NAME>
; 1,23,349,4443,51597,568155,6054973,63196331,650620333,6637326267,67293219357,679380276939,6838972903309,68706054180059,689275354683901,6908259384473067,69191143298038125,692671313513140731
mov $1,1
mov $2,$0
mov $3,$0
lpb $2
mov $0,$3
sub $2,1
sub $0,$2
seq $0,16292 ; Expansion of 1/((1-2x)*(1-4x)*(1-10x)).
mul $1,7
add $1,$0
lpe
mov $0,$1
|
oeis/016/A016280.asm | neoneye/loda-programs | 11 | 163415 | <filename>oeis/016/A016280.asm<gh_stars>10-100
; A016280: Expansion of 1/((1-2x)(1-3x)(1-11x)).
; Submitted by <NAME>
; 1,16,195,2210,24521,270396,2976415,32746870,360234741,3962640176,43589217035,479481914730,5274302648161,58017333896356,638190687176055,7020097601917790,77221073750104781,849431811638310936,9343749929183157475,102781249224500468050,1130593741479963404601,12436531156310974315916,136801842719514852265295,1504820269914945787677510,16553022969065250919507621,182083252659720301913303296,2002915779256930946509603515,22032073571826263288129658170,242352809290088964799266733841
mov $1,1
mov $2,1
mov $3,2
lpb $0
sub $0,1
mul $1,11
mul $3,3
add $3,2
add $1,$3
mul $2,2
add $2,1
sub $1,$2
lpe
mov $0,$1
|
Cubical/ZCohomology/Properties.agda | ayberkt/cubical | 0 | 10052 | <reponame>ayberkt/cubical<gh_stars>0
{-# OPTIONS --cubical --no-import-sorts --safe #-}
module Cubical.ZCohomology.Properties where
open import Cubical.ZCohomology.Base
open import Cubical.HITs.S1
open import Cubical.HITs.Sn
open import Cubical.Foundations.HLevels
open import Cubical.Foundations.Function
open import Cubical.Foundations.Equiv
open import Cubical.Foundations.Prelude
open import Cubical.Foundations.Pointed
open import Cubical.Foundations.Transport
open import Cubical.Foundations.Isomorphism
open import Cubical.Foundations.GroupoidLaws
open import Cubical.Foundations.Univalence
open import Cubical.Data.Empty
open import Cubical.Data.Sigma hiding (_×_)
open import Cubical.HITs.Susp
open import Cubical.HITs.Wedge
open import Cubical.HITs.SetTruncation renaming (rec to sRec ; rec2 to sRec2 ; elim to sElim ; elim2 to sElim2 ; setTruncIsSet to §)
open import Cubical.Data.Int renaming (_+_ to _ℤ+_)
open import Cubical.Data.Nat
open import Cubical.HITs.Truncation renaming (elim to trElim ; map to trMap ; rec to trRec ; elim3 to trElim3)
open import Cubical.Homotopy.Loopspace
open import Cubical.Homotopy.Connected
open import Cubical.Homotopy.Freudenthal
open import Cubical.Algebra.Group
open import Cubical.Algebra.Semigroup
open import Cubical.Algebra.Monoid
open import Cubical.Foundations.Equiv.HalfAdjoint
open import Cubical.Data.NatMinusOne
open import Cubical.HITs.Pushout
open import Cubical.Data.Sum.Base
open import Cubical.Data.HomotopyGroup
open import Cubical.ZCohomology.KcompPrelims
open Iso renaming (inv to inv')
private
variable
ℓ ℓ' : Level
A : Type ℓ
B : Type ℓ'
A' : Pointed ℓ
infixr 34 _+ₖ_
infixr 34 _+ₕ_
is2ConnectedKn : (n : ℕ) → isConnected 2 (coHomK (suc n))
is2ConnectedKn zero = ∣ ∣ base ∣ ∣
, trElim (λ _ → isOfHLevelPath 2 (isOfHLevelTrunc 2) _ _)
(trElim (λ _ → isOfHLevelPath 3 (isOfHLevelSuc 2 (isOfHLevelTrunc 2)) _ _)
(toPropElim (λ _ → isOfHLevelTrunc 2 _ _) refl))
is2ConnectedKn (suc n) = ∣ ∣ north ∣ ∣
, trElim (λ _ → isOfHLevelPath 2 (isOfHLevelTrunc 2) _ _)
(trElim (λ _ → isProp→isOfHLevelSuc (3 + n) (isOfHLevelTrunc 2 _ _))
(suspToPropElim (ptSn (suc n)) (λ _ → isOfHLevelTrunc 2 _ _) refl))
isConnectedKn : (n : ℕ) → isConnected (2 + n) (coHomK (suc n))
isConnectedKn n = isOfHLevelRetractFromIso 0 (invIso (truncOfTruncIso (2 + n) 1)) (sphereConnected (suc n))
-- Induction principles for cohomology groups
-- If we want to show a proposition about some x : Hⁿ(A), it suffices to show it under the
-- assumption that x = ∣f∣₂ and that f is pointed
coHomPointedElim : {A : Type ℓ} (n : ℕ) (a : A) {B : coHom (suc n) A → Type ℓ'}
→ ((x : coHom (suc n) A) → isProp (B x))
→ ((f : A → coHomK (suc n)) → f a ≡ coHom-pt (suc n) → B ∣ f ∣₂)
→ (x : coHom (suc n) A) → B x
coHomPointedElim {ℓ' = ℓ'} {A = A} n a isprop indp =
sElim (λ _ → isOfHLevelSuc 1 (isprop _))
λ f → helper n isprop indp f (f a) refl
where
helper : (n : ℕ) {B : coHom (suc n) A → Type ℓ'}
→ ((x : coHom (suc n) A) → isProp (B x))
→ ((f : A → coHomK (suc n)) → f a ≡ coHom-pt (suc n) → B ∣ f ∣₂)
→ (f : A → coHomK (suc n))
→ (x : coHomK (suc n))
→ f a ≡ x → B ∣ f ∣₂
-- pattern matching a bit extra to avoid isOfHLevelPlus'
helper zero isprop ind f =
trElim (λ _ → isOfHLevelPlus {n = 1} 2 (isPropΠ λ _ → isprop _))
(toPropElim (λ _ → isPropΠ λ _ → isprop _) (ind f))
helper (suc zero) isprop ind f =
trElim (λ _ → isOfHLevelPlus {n = 1} 3 (isPropΠ λ _ → isprop _))
(suspToPropElim base (λ _ → isPropΠ λ _ → isprop _) (ind f))
helper (suc (suc zero)) isprop ind f =
trElim (λ _ → isOfHLevelPlus {n = 1} 4 (isPropΠ λ _ → isprop _))
(suspToPropElim north (λ _ → isPropΠ λ _ → isprop _) (ind f))
helper (suc (suc (suc n))) isprop ind f =
trElim (λ _ → isOfHLevelPlus' {n = 5 + n} 1 (isPropΠ λ _ → isprop _))
(suspToPropElim north (λ _ → isPropΠ λ _ → isprop _) (ind f))
coHomPointedElim2 : {A : Type ℓ} (n : ℕ) (a : A) {B : coHom (suc n) A → coHom (suc n) A → Type ℓ'}
→ ((x y : coHom (suc n) A) → isProp (B x y))
→ ((f g : A → coHomK (suc n)) → f a ≡ coHom-pt (suc n) → g a ≡ coHom-pt (suc n) → B ∣ f ∣₂ ∣ g ∣₂)
→ (x y : coHom (suc n) A) → B x y
coHomPointedElim2 {ℓ' = ℓ'} {A = A} n a isprop indp = sElim2 (λ _ _ → isOfHLevelSuc 1 (isprop _ _))
λ f g → helper n a isprop indp f g (f a) (g a) refl refl
where
helper : (n : ℕ) (a : A) {B : coHom (suc n) A → coHom (suc n) A → Type ℓ'}
→ ((x y : coHom (suc n) A) → isProp (B x y))
→ ((f g : A → coHomK (suc n)) → f a ≡ coHom-pt (suc n) → g a ≡ coHom-pt (suc n) → B ∣ f ∣₂ ∣ g ∣₂)
→ (f g : A → coHomK (suc n))
→ (x y : coHomK (suc n))
→ f a ≡ x → g a ≡ y
→ B ∣ f ∣₂ ∣ g ∣₂
helper zero a isprop indp f g =
elim2 (λ _ _ → isOfHLevelPlus {n = 1} 2 (isPropΠ2 λ _ _ → isprop _ _))
(toPropElim2 (λ _ _ → isPropΠ2 λ _ _ → isprop _ _) (indp f g))
helper (suc zero) a isprop indp f g =
elim2 (λ _ _ → isOfHLevelPlus {n = 1} 3 (isPropΠ2 λ _ _ → isprop _ _))
(suspToPropElim2 base (λ _ _ → isPropΠ2 λ _ _ → isprop _ _) (indp f g))
helper (suc (suc zero)) a isprop indp f g =
elim2 (λ _ _ → isOfHLevelPlus {n = 1} 4 (isPropΠ2 λ _ _ → isprop _ _))
(suspToPropElim2 north (λ _ _ → isPropΠ2 λ _ _ → isprop _ _) (indp f g))
helper (suc (suc (suc n))) a isprop indp f g =
elim2 (λ _ _ → isOfHLevelPlus' {n = 5 + n} 1 (isPropΠ2 λ _ _ → isprop _ _))
(suspToPropElim2 north (λ _ _ → isPropΠ2 λ _ _ → isprop _ _) (indp f g))
{- Equivalence between cohomology of A and reduced cohomology of (A + 1) -}
coHomRed+1Equiv : (n : ℕ) →
(A : Type ℓ) →
(coHom n A) ≡ (coHomRed n ((A ⊎ Unit , inr (tt))))
coHomRed+1Equiv zero A i = ∥ helpLemma {C = (Int , pos 0)} i ∥₂
module coHomRed+1 where
helpLemma : {C : Pointed ℓ} → ( (A → (typ C)) ≡ ((((A ⊎ Unit) , inr (tt)) →∙ C)))
helpLemma {C = C} = isoToPath (iso map1
map2
(λ b → linvPf b)
(λ _ → refl))
where
map1 : (A → typ C) → ((((A ⊎ Unit) , inr (tt)) →∙ C))
map1 f = map1' , refl
module helpmap where
map1' : A ⊎ Unit → fst C
map1' (inl x) = f x
map1' (inr x) = pt C
map2 : ((((A ⊎ Unit) , inr (tt)) →∙ C)) → (A → typ C)
map2 (g , pf) x = g (inl x)
linvPf : (b :((((A ⊎ Unit) , inr (tt)) →∙ C))) → map1 (map2 b) ≡ b
linvPf (f , snd) i = (λ x → helper x i) , λ j → snd ((~ i) ∨ j)
where
helper : (x : A ⊎ Unit) → ((helpmap.map1') (map2 (f , snd)) x) ≡ f x
helper (inl x) = refl
helper (inr tt) = sym snd
coHomRed+1Equiv (suc zero) A i = ∥ coHomRed+1.helpLemma A i {C = (coHomK 1 , ∣ base ∣)} i ∥₂
coHomRed+1Equiv (suc (suc n)) A i = ∥ coHomRed+1.helpLemma A i {C = (coHomK (2 + n) , ∣ north ∣)} i ∥₂
-----------
Kn→ΩKn+1 : (n : ℕ) → coHomK n → typ (Ω (coHomK-ptd (suc n)))
Kn→ΩKn+1 n = Iso.fun (Iso-Kn-ΩKn+1 n)
ΩKn+1→Kn : (n : ℕ) → typ (Ω (coHomK-ptd (suc n))) → coHomK n
ΩKn+1→Kn n = Iso.inv (Iso-Kn-ΩKn+1 n)
Kn≃ΩKn+1 : {n : ℕ} → coHomK n ≃ typ (Ω (coHomK-ptd (suc n)))
Kn≃ΩKn+1 {n = n} = isoToEquiv (Iso-Kn-ΩKn+1 n)
---------- Algebra/Group stuff --------
0ₖ : (n : ℕ) → coHomK n
0ₖ = coHom-pt
_+ₖ_ : {n : ℕ} → coHomK n → coHomK n → coHomK n
_+ₖ_ {n = n} x y = ΩKn+1→Kn n (Kn→ΩKn+1 n x ∙ Kn→ΩKn+1 n y)
-ₖ_ : {n : ℕ} → coHomK n → coHomK n
-ₖ_ {n = n} x = ΩKn+1→Kn n (sym (Kn→ΩKn+1 n x))
-- subtraction as a binary operator
_-ₖ_ : {n : ℕ} → coHomK n → coHomK n → coHomK n
_-ₖ_ {n = n} x y = ΩKn+1→Kn n (Kn→ΩKn+1 n x ∙ sym (Kn→ΩKn+1 n y))
+ₖ-syntax : (n : ℕ) → coHomK n → coHomK n → coHomK n
+ₖ-syntax n = _+ₖ_ {n = n}
-ₖ-syntax : (n : ℕ) → coHomK n → coHomK n
-ₖ-syntax n = -ₖ_ {n = n}
-'ₖ-syntax : (n : ℕ) → coHomK n → coHomK n → coHomK n
-'ₖ-syntax n = _-ₖ_ {n = n}
syntax +ₖ-syntax n x y = x +[ n ]ₖ y
syntax -ₖ-syntax n x = -[ n ]ₖ x
syntax -'ₖ-syntax n x y = x -[ n ]ₖ y
Kn→ΩKn+10ₖ : (n : ℕ) → Kn→ΩKn+1 n (0ₖ n) ≡ refl
Kn→ΩKn+10ₖ zero = sym (rUnit refl)
Kn→ΩKn+10ₖ (suc zero) i j = ∣ (rCancel (merid base) i j) ∣
Kn→ΩKn+10ₖ (suc (suc n)) i j = ∣ (rCancel (merid north) i j) ∣
ΩKn+1→Kn-refl : (n : ℕ) → ΩKn+1→Kn n refl ≡ 0ₖ n
ΩKn+1→Kn-refl zero = refl
ΩKn+1→Kn-refl (suc zero) = refl
ΩKn+1→Kn-refl (suc (suc zero)) = refl
ΩKn+1→Kn-refl (suc (suc (suc zero))) = refl
ΩKn+1→Kn-refl (suc (suc (suc (suc zero)))) = refl
ΩKn+1→Kn-refl (suc (suc (suc (suc (suc n))))) = refl
-0ₖ : {n : ℕ} → -[ n ]ₖ (0ₖ n) ≡ (0ₖ n)
-0ₖ {n = n} = (λ i → ΩKn+1→Kn n (sym (Kn→ΩKn+10ₖ n i)))
∙∙ (λ i → ΩKn+1→Kn n (Kn→ΩKn+10ₖ n (~ i)))
∙∙ Iso.leftInv (Iso-Kn-ΩKn+1 n) (0ₖ n)
+ₖ→∙ : (n : ℕ) (a b : coHomK n) → Kn→ΩKn+1 n (a +[ n ]ₖ b) ≡ Kn→ΩKn+1 n a ∙ Kn→ΩKn+1 n b
+ₖ→∙ n a b = Iso.rightInv (Iso-Kn-ΩKn+1 n) (Kn→ΩKn+1 n a ∙ Kn→ΩKn+1 n b)
lUnitₖ : (n : ℕ) (x : coHomK n) → (0ₖ n) +[ n ]ₖ x ≡ x
lUnitₖ 0 x = Iso.leftInv (Iso-Kn-ΩKn+1 zero) x
lUnitₖ (suc zero) = trElim (λ _ → isOfHLevelPath 3 (isOfHLevelTrunc 3) _ _) λ x → Iso.leftInv (Iso-Kn-ΩKn+1 1) ∣ x ∣
lUnitₖ (suc (suc n)) x =
(λ i → ΩKn+1→Kn (2 + n) (Kn→ΩKn+10ₖ (2 + n) i ∙ Kn→ΩKn+1 (2 + n) x)) ∙∙
(cong (ΩKn+1→Kn (2 + n)) (sym (lUnit (Kn→ΩKn+1 (2 + n) x)))) ∙∙
Iso.leftInv (Iso-Kn-ΩKn+1 (2 + n)) x
rUnitₖ : (n : ℕ) (x : coHomK n) → x +[ n ]ₖ (0ₖ n) ≡ x
rUnitₖ 0 x = Iso.leftInv (Iso-Kn-ΩKn+1 zero) x
rUnitₖ (suc zero) = trElim (λ _ → isOfHLevelPath 3 (isOfHLevelTrunc 3) _ _) λ x → Iso.leftInv (Iso-Kn-ΩKn+1 1) ∣ x ∣
rUnitₖ (suc (suc n)) x =
(λ i → ΩKn+1→Kn (2 + n) (Kn→ΩKn+1 (2 + n) x ∙ Kn→ΩKn+10ₖ (2 + n) i))
∙∙ (cong (ΩKn+1→Kn (2 + n)) (sym (rUnit (Kn→ΩKn+1 (2 + n) x))))
∙∙ Iso.leftInv (Iso-Kn-ΩKn+1 (2 + n)) x
rCancelₖ : (n : ℕ) (x : coHomK n) → x +[ n ]ₖ (-[ n ]ₖ x) ≡ (0ₖ n)
rCancelₖ zero x = (λ i → ΩKn+1→Kn 0 (Kn→ΩKn+1 zero x ∙ Iso.rightInv (Iso-Kn-ΩKn+1 zero) (sym (Kn→ΩKn+1 zero x)) i)) ∙
cong (ΩKn+1→Kn 0) (rCancel (Kn→ΩKn+1 zero x))
rCancelₖ (suc n) x = (λ i → ΩKn+1→Kn (suc n) (Kn→ΩKn+1 (1 + n) x ∙ Iso.rightInv (Iso-Kn-ΩKn+1 (1 + n)) (sym (Kn→ΩKn+1 (1 + n) x)) i)) ∙
cong (ΩKn+1→Kn (suc n)) (rCancel (Kn→ΩKn+1 (1 + n) x)) ∙
(λ i → ΩKn+1→Kn (suc n) (Kn→ΩKn+10ₖ (suc n) (~ i))) ∙
Iso.leftInv (Iso-Kn-ΩKn+1 (suc n)) (0ₖ (suc n))
lCancelₖ : (n : ℕ) (x : coHomK n) → (-[ n ]ₖ x) +[ n ]ₖ x ≡ (0ₖ n)
lCancelₖ 0 x = (λ i → ΩKn+1→Kn 0 (Iso.rightInv (Iso-Kn-ΩKn+1 zero) (sym (Kn→ΩKn+1 zero x)) i ∙ Kn→ΩKn+1 zero x)) ∙
cong (ΩKn+1→Kn 0) (lCancel (Kn→ΩKn+1 zero x))
lCancelₖ (suc n) x = (λ i → ΩKn+1→Kn (suc n) (Iso.rightInv (Iso-Kn-ΩKn+1 (1 + n)) (sym (Kn→ΩKn+1 (1 + n) x)) i ∙ Kn→ΩKn+1 (1 + n) x)) ∙
cong (ΩKn+1→Kn (suc n)) (lCancel (Kn→ΩKn+1 (1 + n) x)) ∙
(λ i → (ΩKn+1→Kn (suc n)) (Kn→ΩKn+10ₖ (suc n) (~ i))) ∙
Iso.leftInv (Iso-Kn-ΩKn+1 (suc n)) (0ₖ (suc n))
assocₖ : (n : ℕ) (x y z : coHomK n) → ((x +[ n ]ₖ y) +[ n ]ₖ z) ≡ (x +[ n ]ₖ (y +[ n ]ₖ z))
assocₖ n x y z = ((λ i → ΩKn+1→Kn n (Kn→ΩKn+1 n (ΩKn+1→Kn n (Kn→ΩKn+1 n x ∙ Kn→ΩKn+1 n y)) ∙ Kn→ΩKn+1 n z)) ∙∙
(λ i → ΩKn+1→Kn n (Iso.rightInv (Iso-Kn-ΩKn+1 n) (Kn→ΩKn+1 n x ∙ Kn→ΩKn+1 n y) i ∙ Kn→ΩKn+1 n z)) ∙∙
(λ i → ΩKn+1→Kn n (assoc (Kn→ΩKn+1 n x) (Kn→ΩKn+1 n y) (Kn→ΩKn+1 n z) (~ i)))) ∙
(λ i → ΩKn+1→Kn n ((Kn→ΩKn+1 n x) ∙ Iso.rightInv (Iso-Kn-ΩKn+1 n) ((Kn→ΩKn+1 n y ∙ Kn→ΩKn+1 n z)) (~ i)))
cancelₖ : (n : ℕ) (x : coHomK n) → x -[ n ]ₖ x ≡ (0ₖ n)
cancelₖ zero x = cong (ΩKn+1→Kn 0) (rCancel (Kn→ΩKn+1 zero x))
cancelₖ (suc zero) x = cong (ΩKn+1→Kn 1) (rCancel (Kn→ΩKn+1 1 x))
cancelₖ (suc (suc zero)) x = cong (ΩKn+1→Kn 2) (rCancel (Kn→ΩKn+1 2 x))
cancelₖ (suc (suc (suc zero))) x = cong (ΩKn+1→Kn 3) (rCancel (Kn→ΩKn+1 3 x))
cancelₖ (suc (suc (suc (suc zero)))) x = cong (ΩKn+1→Kn 4) (rCancel (Kn→ΩKn+1 4 x))
cancelₖ (suc (suc (suc (suc (suc n))))) x = cong (ΩKn+1→Kn (5 + n)) (rCancel (Kn→ΩKn+1 (5 + n) x))
-rUnitₖ : (n : ℕ) (x : coHomK n) → x -[ n ]ₖ 0ₖ n ≡ x
-rUnitₖ zero x = rUnitₖ zero x
-rUnitₖ (suc n) x = cong (λ y → ΩKn+1→Kn (suc n) (Kn→ΩKn+1 (suc n) x ∙ sym y)) (Kn→ΩKn+10ₖ (suc n))
∙∙ cong (ΩKn+1→Kn (suc n)) (sym (rUnit (Kn→ΩKn+1 (suc n) x)))
∙∙ Iso.leftInv (Iso-Kn-ΩKn+1 (suc n)) x
isComm∙ : ∀ {ℓ} (A : Pointed ℓ) → Type ℓ
isComm∙ A = (p q : typ (Ω A)) → p ∙ q ≡ q ∙ p
abstract
isCommA→isCommTrunc : ∀ {ℓ} {A : Pointed ℓ} (n : ℕ) → isComm∙ A → isOfHLevel (suc n) (typ A) → isComm∙ (∥ typ A ∥ (suc n) , ∣ pt A ∣)
isCommA→isCommTrunc {A = (A , a)} n comm hlev p q =
((λ i j → (Iso.leftInv (truncIdempotentIso (suc n) hlev) ((p ∙ q) j) (~ i)))
∙∙ (λ i → cong {B = λ _ → ∥ A ∥ (suc n) } (λ x → ∣ x ∣) (cong (trRec hlev (λ x → x)) (p ∙ q)))
∙∙ (λ i → cong {B = λ _ → ∥ A ∥ (suc n) } (λ x → ∣ x ∣) (congFunct {A = ∥ A ∥ (suc n)} {B = A} (trRec hlev (λ x → x)) p q i)))
∙ ((λ i → cong {B = λ _ → ∥ A ∥ (suc n) } (λ x → ∣ x ∣) (comm (cong (trRec hlev (λ x → x)) p) (cong (trRec hlev (λ x → x)) q) i))
∙∙ (λ i → cong {B = λ _ → ∥ A ∥ (suc n) } (λ x → ∣ x ∣) (congFunct {A = ∥ A ∥ (suc n)} {B = A} (trRec hlev (λ x → x)) q p (~ i)))
∙∙ (λ i j → (Iso.leftInv (truncIdempotentIso (suc n) hlev) ((q ∙ p) j) i)))
isCommΩK1 : (n : ℕ) → isComm∙ ((Ω^ n) (coHomK-ptd 1))
isCommΩK1 zero = isCommA→isCommTrunc 2 comm-ΩS¹ isGroupoidS¹
isCommΩK1 (suc n) = Eckmann-Hilton n
open Iso renaming (inv to inv')
ptdIso→comm : ∀ {ℓ ℓ'} {A : Pointed ℓ} {B : Type ℓ'} (e : Iso (typ A) B) → isComm∙ A → isComm∙ (B , Iso.fun e (pt A))
ptdIso→comm {A = (A , a)} {B = B} e comm p q =
sym (rightInv (congIso e) (p ∙ q))
∙∙ (cong (fun (congIso e)) ((invCongFunct e p q)
∙∙ (comm (inv' (congIso e) p) (inv' (congIso e) q))
∙∙ (sym (invCongFunct e q p))))
∙∙ rightInv (congIso e) (q ∙ p)
isCommΩK : (n : ℕ) → isComm∙ (coHomK-ptd n)
isCommΩK zero p q = isSetInt _ _ (p ∙ q) (q ∙ p)
isCommΩK (suc zero) = isCommA→isCommTrunc 2 comm-ΩS¹ isGroupoidS¹
isCommΩK (suc (suc n)) = subst isComm∙ (λ i → coHomK (2 + n) , ΩKn+1→Kn-refl (2 + n) i) (ptdIso→comm {A = (_ , _)} (invIso (Iso-Kn-ΩKn+1 (2 + n))) (Eckmann-Hilton 0))
commₖ : (n : ℕ) (x y : coHomK n) → (x +[ n ]ₖ y) ≡ (y +[ n ]ₖ x)
commₖ 0 x y i = ΩKn+1→Kn 0 (isCommΩK1 0 (Kn→ΩKn+1 0 x) (Kn→ΩKn+1 0 y) i)
commₖ 1 x y i = ΩKn+1→Kn 1 (ptdIso→comm {A = ((∣ north ∣ ≡ ∣ north ∣) , snd ((Ω^ 1) (coHomK 3 , ∣ north ∣)))}
{B = coHomK 2}
(invIso (Iso-Kn-ΩKn+1 2)) (Eckmann-Hilton 0) (Kn→ΩKn+1 1 x) (Kn→ΩKn+1 1 y) i)
commₖ 2 x y i = ΩKn+1→Kn 2 (ptdIso→comm {A = (∣ north ∣ ≡ ∣ north ∣) , snd ((Ω^ 1) (coHomK 4 , ∣ north ∣))}
{B = coHomK 3}
(invIso (Iso-Kn-ΩKn+1 3)) (Eckmann-Hilton 0) (Kn→ΩKn+1 2 x) (Kn→ΩKn+1 2 y) i)
commₖ 3 x y i = ΩKn+1→Kn 3 (ptdIso→comm {A = (∣ north ∣ ≡ ∣ north ∣) , snd ((Ω^ 1) (coHomK 5 , ∣ north ∣))}
{B = coHomK 4}
(invIso (Iso-Kn-ΩKn+1 4)) (Eckmann-Hilton 0) (Kn→ΩKn+1 3 x) (Kn→ΩKn+1 3 y) i)
commₖ (suc (suc (suc (suc n)))) x y i =
ΩKn+1→Kn (4 + n) (ptdIso→comm {A = (∣ north ∣ ≡ ∣ north ∣) , snd ((Ω^ 1) (coHomK (6 + n) , ∣ north ∣))}
{B = coHomK (5 + n)}
(invIso (Iso-Kn-ΩKn+1 (5 + n))) (Eckmann-Hilton 0) (Kn→ΩKn+1 (4 + n) x) (Kn→ΩKn+1 (4 + n) y) i)
rUnitₖ' : (n : ℕ) (x : coHomK n) → x +[ n ]ₖ (0ₖ n) ≡ x
rUnitₖ' n x = commₖ n x (0ₖ n) ∙ lUnitₖ n x
-distrₖ : (n : ℕ) (x y : coHomK n) → -[ n ]ₖ (x +[ n ]ₖ y) ≡ (-[ n ]ₖ x) +[ n ]ₖ (-[ n ]ₖ y)
-distrₖ n x y = ((λ i → ΩKn+1→Kn n (sym (Kn→ΩKn+1 n (ΩKn+1→Kn n (Kn→ΩKn+1 n x ∙ Kn→ΩKn+1 n y))))) ∙∙
(λ i → ΩKn+1→Kn n (sym (Iso.rightInv (Iso-Kn-ΩKn+1 n) (Kn→ΩKn+1 n x ∙ Kn→ΩKn+1 n y) i))) ∙∙
(λ i → ΩKn+1→Kn n (symDistr (Kn→ΩKn+1 n x) (Kn→ΩKn+1 n y) i))) ∙∙
(λ i → ΩKn+1→Kn n (Iso.rightInv (Iso-Kn-ΩKn+1 n) (sym (Kn→ΩKn+1 n y)) (~ i) ∙ (Iso.rightInv (Iso-Kn-ΩKn+1 n) (sym (Kn→ΩKn+1 n x)) (~ i)))) ∙∙
commₖ n (-[ n ]ₖ y) (-[ n ]ₖ x)
private
rCancelLem : (n : ℕ) (x : coHomK n) → ΩKn+1→Kn n ((Kn→ΩKn+1 n x) ∙ refl) ≡ ΩKn+1→Kn n (Kn→ΩKn+1 n x)
rCancelLem zero x = refl
rCancelLem (suc n) x = cong (ΩKn+1→Kn (suc n)) (sym (rUnit (Kn→ΩKn+1 (suc n) x)))
lCancelLem : (n : ℕ) (x : coHomK n) → ΩKn+1→Kn n (refl ∙ (Kn→ΩKn+1 n x)) ≡ ΩKn+1→Kn n (Kn→ΩKn+1 n x)
lCancelLem zero x = refl
lCancelLem (suc n) x = cong (ΩKn+1→Kn (suc n)) (sym (lUnit (Kn→ΩKn+1 (suc n) x)))
-cancelRₖ : (n : ℕ) (x y : coHomK n) → (y +[ n ]ₖ x) -[ n ]ₖ x ≡ y
-cancelRₖ n x y = (cong (ΩKn+1→Kn n) ((cong (_∙ sym (Kn→ΩKn+1 n x)) (+ₖ→∙ n y x))
∙∙ sym (assoc _ _ _)
∙∙ cong (Kn→ΩKn+1 n y ∙_) (rCancel _)))
∙∙ rCancelLem n y
∙∙ Iso.leftInv (Iso-Kn-ΩKn+1 n) y
-cancelLₖ : (n : ℕ) (x y : coHomK n) → (x +[ n ]ₖ y) -[ n ]ₖ x ≡ y
-cancelLₖ n x y = cong (λ z → z -[ n ]ₖ x) (commₖ n x y) ∙ -cancelRₖ n x y
-+cancelₖ : (n : ℕ) (x y : coHomK n) → (x -[ n ]ₖ y) +[ n ]ₖ y ≡ x
-+cancelₖ n x y = (cong (ΩKn+1→Kn n) ((cong (_∙ (Kn→ΩKn+1 n y)) (Iso.rightInv (Iso-Kn-ΩKn+1 n) (Kn→ΩKn+1 n x ∙ sym (Kn→ΩKn+1 n y))))
∙∙ sym (assoc _ _ _)
∙∙ cong (Kn→ΩKn+1 n x ∙_) (lCancel _)))
∙∙ rCancelLem n x
∙∙ Iso.leftInv (Iso-Kn-ΩKn+1 n) x
---- Group structure of cohomology groups ---
_+ₕ_ : {n : ℕ} → coHom n A → coHom n A → coHom n A
_+ₕ_ {n = n} = sRec2 § λ a b → ∣ (λ x → a x +[ n ]ₖ b x) ∣₂
-ₕ_ : {n : ℕ} → coHom n A → coHom n A
-ₕ_ {n = n} = sRec § λ a → ∣ (λ x → -[ n ]ₖ a x) ∣₂
_-ₕ_ : {n : ℕ} → coHom n A → coHom n A → coHom n A
_-ₕ_ {n = n} = sRec2 § λ a b → ∣ (λ x → a x -[ n ]ₖ b x) ∣₂
+ₕ-syntax : (n : ℕ) → coHom n A → coHom n A → coHom n A
+ₕ-syntax n = _+ₕ_ {n = n}
-ₕ-syntax : (n : ℕ) → coHom n A → coHom n A
-ₕ-syntax n = -ₕ_ {n = n}
-ₕ'-syntax : (n : ℕ) → coHom n A → coHom n A → coHom n A
-ₕ'-syntax n = _-ₕ_ {n = n}
syntax +ₕ-syntax n x y = x +[ n ]ₕ y
syntax -ₕ-syntax n x = -[ n ]ₕ x
syntax -ₕ'-syntax n x y = x -[ n ]ₕ y
0ₕ : (n : ℕ) → coHom n A
0ₕ n = ∣ (λ _ → (0ₖ n)) ∣₂
rUnitₕ : (n : ℕ) (x : coHom n A) → x +[ n ]ₕ (0ₕ n) ≡ x
rUnitₕ n = sElim (λ _ → isOfHLevelPath 1 (§ _ _))
λ a i → ∣ funExt (λ x → rUnitₖ n (a x)) i ∣₂
lUnitₕ : (n : ℕ) (x : coHom n A) → (0ₕ n) +[ n ]ₕ x ≡ x
lUnitₕ n = sElim (λ _ → isOfHLevelPath 1 (§ _ _))
λ a i → ∣ funExt (λ x → lUnitₖ n (a x)) i ∣₂
rCancelₕ : (n : ℕ) (x : coHom n A) → x +[ n ]ₕ (-[ n ]ₕ x) ≡ 0ₕ n
rCancelₕ n = sElim (λ _ → isOfHLevelPath 1 (§ _ _))
λ a i → ∣ funExt (λ x → rCancelₖ n (a x)) i ∣₂
lCancelₕ : (n : ℕ) (x : coHom n A) → (-[ n ]ₕ x) +[ n ]ₕ x ≡ 0ₕ n
lCancelₕ n = sElim (λ _ → isOfHLevelPath 1 (§ _ _))
λ a i → ∣ funExt (λ x → lCancelₖ n (a x)) i ∣₂
assocₕ : (n : ℕ) (x y z : coHom n A) → ((x +[ n ]ₕ y) +[ n ]ₕ z) ≡ (x +[ n ]ₕ (y +[ n ]ₕ z))
assocₕ n = elim3 (λ _ _ _ → isOfHLevelPath 1 (§ _ _))
λ a b c i → ∣ funExt (λ x → assocₖ n (a x) (b x) (c x)) i ∣₂
commₕ : (n : ℕ) (x y : coHom n A) → (x +[ n ]ₕ y) ≡ (y +[ n ]ₕ x)
commₕ n = sElim2 (λ _ _ → isOfHLevelPath 1 (§ _ _))
λ a b i → ∣ funExt (λ x → commₖ n (a x) (b x)) i ∣₂
cancelₕ : (n : ℕ) (x : coHom n A) → x -[ n ]ₕ x ≡ 0ₕ n
cancelₕ n = sElim (λ _ → isOfHLevelPath 1 (§ _ _))
λ a i → ∣ funExt (λ x → cancelₖ n (a x)) i ∣₂
-ₖ-ₖ : (n : ℕ) (x : coHomK n) → (-[ n ]ₖ (-[ n ]ₖ x)) ≡ x
-ₖ-ₖ n x = cong ((ΩKn+1→Kn n) ∘ sym) (Iso.rightInv (Iso-Kn-ΩKn+1 n) (sym (Kn→ΩKn+1 n x))) ∙ Iso.leftInv (Iso-Kn-ΩKn+1 n) x
-- Proof that rUnitₖ and lUnitₖ agree on 0ₖ. Needed for Mayer-Vietoris.
private
rUnitlUnitGen : ∀ {ℓ ℓ'} {A : Type ℓ} {B : Type ℓ'} {b : B} (e : Iso A (b ≡ b))
(0A : A)
(0fun : fun e 0A ≡ refl)
→ Path (inv' e (fun e 0A ∙ fun e 0A) ≡ 0A)
(cong (inv' e) (cong (_∙ fun e 0A) 0fun) ∙∙ cong (inv' e) (sym (lUnit (fun e 0A))) ∙∙ Iso.leftInv e 0A)
(cong (inv' e) (cong (fun e 0A ∙_) 0fun) ∙∙ cong (inv' e) (sym (rUnit (fun e 0A))) ∙∙ Iso.leftInv e 0A)
rUnitlUnitGen e 0A 0fun =
(λ i → cong (inv' e) (cong (_∙ fun e 0A) 0fun) ∙∙ rUnit (cong (inv' e) (sym (lUnit (fun e 0A)))) i ∙∙ Iso.leftInv e 0A)
∙ ((λ i → (λ j → inv' e (0fun (~ i ∧ j) ∙ 0fun (j ∧ i)))
∙∙ ((λ j → inv' e (0fun (~ i ∨ j) ∙ 0fun i))
∙∙ cong (inv' e) (sym (lUnit (0fun i)))
∙∙ λ j → inv' e (0fun (i ∧ (~ j))))
∙∙ Iso.leftInv e 0A)
∙∙ (λ i → (λ j → inv' e (fun e 0A ∙ 0fun j))
∙∙ (λ j → inv' e (0fun (j ∧ ~ i) ∙ refl))
∙∙ cong (inv' e) (sym (rUnit (0fun (~ i))))
∙∙ (λ j → inv' e (0fun (~ i ∧ ~ j)))
∙∙ Iso.leftInv e 0A)
∙∙ λ i → cong (inv' e) (cong (fun e 0A ∙_) 0fun)
∙∙ rUnit (cong (inv' e) (sym (rUnit (fun e 0A)))) (~ i)
∙∙ Iso.leftInv e 0A)
rUnitlUnit0 : (n : ℕ) → rUnitₖ n (0ₖ n) ≡ lUnitₖ n (0ₖ n)
rUnitlUnit0 0 = refl
rUnitlUnit0 (suc zero) = refl
rUnitlUnit0 (suc (suc n)) = sym (rUnitlUnitGen (Iso-Kn-ΩKn+1 (2 + n)) (0ₖ (2 + n)) (Kn→ΩKn+10ₖ (2 + n)))
-cancelLₕ : (n : ℕ) (x y : coHom n A) → (x +[ n ]ₕ y) -[ n ]ₕ x ≡ y
-cancelLₕ n = sElim2 (λ _ _ → isOfHLevelPath 1 (§ _ _))
λ a b i → ∣ (λ x → -cancelLₖ n (a x) (b x) i) ∣₂
-cancelRₕ : (n : ℕ) (x y : coHom n A) → (y +[ n ]ₕ x) -[ n ]ₕ x ≡ y
-cancelRₕ n = sElim2 (λ _ _ → isOfHLevelPath 1 (§ _ _))
λ a b i → ∣ (λ x → -cancelRₖ n (a x) (b x) i) ∣₂
-+cancelₕ : (n : ℕ) (x y : coHom n A) → (x -[ n ]ₕ y) +[ n ]ₕ y ≡ x
-+cancelₕ n = sElim2 (λ _ _ → isOfHLevelPath 1 (§ _ _))
λ a b i → ∣ (λ x → -+cancelₖ n (a x) (b x) i) ∣₂
-- Group structure of reduced cohomology groups (in progress - might need K to compute properly first) ---
+ₕ∙ : {A : Pointed ℓ} (n : ℕ) → coHomRed n A → coHomRed n A → coHomRed n A
+ₕ∙ zero = sRec2 § λ { (a , pa) (b , pb) → ∣ (λ x → a x +[ zero ]ₖ b x) , (λ i → (pa i +[ zero ]ₖ pb i)) ∣₂ }
+ₕ∙ (suc zero) = sRec2 § λ { (a , pa) (b , pb) → ∣ (λ x → a x +[ 1 ]ₖ b x) , (λ i → pa i +[ 1 ]ₖ pb i) ∙ lUnitₖ 1 (0ₖ 1) ∣₂ }
+ₕ∙ (suc (suc n)) = sRec2 § λ { (a , pa) (b , pb) → ∣ (λ x → a x +[ (2 + n) ]ₖ b x) , (λ i → pa i +[ (2 + n) ]ₖ pb i) ∙ lUnitₖ (2 + n) (0ₖ (2 + n)) ∣₂ }
open IsSemigroup
open IsMonoid
open GroupStr
open GroupHom
coHomGr : ∀ {ℓ} (n : ℕ) (A : Type ℓ) → Group {ℓ}
coHomGr n A = coHom n A , coHomGrnA
where
coHomGrnA : GroupStr (coHom n A)
0g coHomGrnA = 0ₕ n
GroupStr._+_ coHomGrnA = λ x y → x +[ n ]ₕ y
- coHomGrnA = λ x → -[ n ]ₕ x
isGroup coHomGrnA = helper
where
abstract
helper : IsGroup (0ₕ n) (λ x y → x +[ n ]ₕ y) (λ x → -[ n ]ₕ x)
helper = makeIsGroup § (λ x y z → sym (assocₕ n x y z)) (rUnitₕ n) (lUnitₕ n) (rCancelₕ n) (lCancelₕ n)
×coHomGr : (n : ℕ) (A : Type ℓ) (B : Type ℓ') → Group
×coHomGr n A B = dirProd (coHomGr n A) (coHomGr n B)
coHomFun : ∀ {ℓ ℓ'} {A : Type ℓ} {B : Type ℓ'} (n : ℕ) (f : A → B) → coHom n B → coHom n A
coHomFun n f = sRec § λ β → ∣ β ∘ f ∣₂
-distrLemma : ∀ {ℓ ℓ'} {A : Type ℓ} {B : Type ℓ'} (n m : ℕ) (f : GroupHom (coHomGr n A) (coHomGr m B))
(x y : coHom n A)
→ fun f (x -[ n ]ₕ y) ≡ fun f x -[ m ]ₕ fun f y
-distrLemma n m f' x y = sym (-cancelRₕ m (f y) (f (x -[ n ]ₕ y)))
∙∙ cong (λ x → x -[ m ]ₕ f y) (sym (isHom f' (x -[ n ]ₕ y) y))
∙∙ cong (λ x → x -[ m ]ₕ f y) ( cong f (-+cancelₕ n _ _))
where
f = fun f'
--- the loopspace of Kₙ is commutative regardless of base
addIso : (n : ℕ) (x : coHomK n) → Iso (coHomK n) (coHomK n)
fun (addIso n x) y = y +[ n ]ₖ x
inv' (addIso n x) y = y -[ n ]ₖ x
rightInv (addIso n x) y = -+cancelₖ n y x
leftInv (addIso n x) y = -cancelRₖ n x y
isCommΩK-based : (n : ℕ) (x : coHomK n) → isComm∙ (coHomK n , x)
isCommΩK-based zero x p q = isSetInt _ _ (p ∙ q) (q ∙ p)
isCommΩK-based (suc zero) x =
subst isComm∙ (λ i → coHomK 1 , lUnitₖ 1 x i)
(ptdIso→comm {A = (_ , 0ₖ 1)} (addIso 1 x)
(isCommΩK 1))
isCommΩK-based (suc (suc n)) x =
subst isComm∙ (λ i → coHomK (suc (suc n)) , lUnitₖ (suc (suc n)) x i)
(ptdIso→comm {A = (_ , 0ₖ (suc (suc n)))} (addIso (suc (suc n)) x)
(isCommΩK (suc (suc n))))
addLemma : (a b : Int) → a +[ 0 ]ₖ b ≡ (a ℤ+ b)
addLemma a b = (cong (ΩKn+1→Kn 0) (sym (congFunct ∣_∣ (intLoop a) (intLoop b))))
∙∙ (λ i → ΩKn+1→Kn 0 (cong ∣_∣ (intLoop-hom a b i)))
∙∙ Iso.leftInv (Iso-Kn-ΩKn+1 0) (a ℤ+ b)
---
-- hidden versions of cohom stuff using the "lock" hack. The locked versions can be used when proving things.
-- Swapping "key" for "tt*" will then give computing functions.
Unit' : Type₀
Unit' = lockUnit {ℓ-zero}
lock : ∀ {ℓ} {A : Type ℓ} → Unit' → A → A
lock unlock = λ x → x
module lockedCohom (key : Unit') where
+K : (n : ℕ) → coHomK n → coHomK n → coHomK n
+K n = lock key (_+ₖ_ {n = n})
-K : (n : ℕ) → coHomK n → coHomK n
-K n = lock key (-ₖ_ {n = n})
-Kbin : (n : ℕ) → coHomK n → coHomK n → coHomK n
-Kbin n = lock key (_-ₖ_ {n = n})
rUnitK : (n : ℕ) (x : coHomK n) → +K n x (0ₖ n) ≡ x
rUnitK n x = pm key
where
pm : (t : Unit') → lock t (_+ₖ_ {n = n}) x (0ₖ n) ≡ x
pm unlock = rUnitₖ n x
lUnitK : (n : ℕ) (x : coHomK n) → +K n (0ₖ n) x ≡ x
lUnitK n x = pm key
where
pm : (t : Unit') → lock t (_+ₖ_ {n = n}) (0ₖ n) x ≡ x
pm unlock = lUnitₖ n x
rCancelK : (n : ℕ) (x : coHomK n) → +K n x (-K n x) ≡ 0ₖ n
rCancelK n x = pm key
where
pm : (t : Unit') → lock t (_+ₖ_ {n = n}) x (lock t (-ₖ_ {n = n}) x) ≡ 0ₖ n
pm unlock = rCancelₖ n x
lCancelK : (n : ℕ) (x : coHomK n) → +K n (-K n x) x ≡ 0ₖ n
lCancelK n x = pm key
where
pm : (t : Unit') → lock t (_+ₖ_ {n = n}) (lock t (-ₖ_ {n = n}) x) x ≡ 0ₖ n
pm unlock = lCancelₖ n x
-cancelRK : (n : ℕ) (x y : coHomK n) → -Kbin n (+K n y x) x ≡ y
-cancelRK n x y = pm key
where
pm : (t : Unit') → lock t (_-ₖ_ {n = n}) (lock t (_+ₖ_ {n = n}) y x) x ≡ y
pm unlock = -cancelRₖ n x y
-cancelLK : (n : ℕ) (x y : coHomK n) → -Kbin n (+K n x y) x ≡ y
-cancelLK n x y = pm key
where
pm : (t : Unit') → lock t (_-ₖ_ {n = n}) (lock t (_+ₖ_ {n = n}) x y) x ≡ y
pm unlock = -cancelLₖ n x y
-+cancelK : (n : ℕ) (x y : coHomK n) → +K n (-Kbin n x y) y ≡ x
-+cancelK n x y = pm key
where
pm : (t : Unit') → lock t (_+ₖ_ {n = n}) (lock t (_-ₖ_ {n = n}) x y) y ≡ x
pm unlock = -+cancelₖ n x y
cancelK : (n : ℕ) (x : coHomK n) → -Kbin n x x ≡ 0ₖ n
cancelK n x = pm key
where
pm : (t : Unit') → (lock t (_-ₖ_ {n = n}) x x) ≡ 0ₖ n
pm unlock = cancelₖ n x
assocK : (n : ℕ) (x y z : coHomK n) → +K n (+K n x y) z ≡ +K n x (+K n y z)
assocK n x y z = pm key
where
pm : (t : Unit') → lock t (_+ₖ_ {n = n}) (lock t (_+ₖ_ {n = n}) x y) z
≡ lock t (_+ₖ_ {n = n}) x (lock t (_+ₖ_ {n = n}) y z)
pm unlock = assocₖ n x y z
commK : (n : ℕ) (x y : coHomK n) → +K n x y ≡ +K n y x
commK n x y = pm key
where
pm : (t : Unit') → lock t (_+ₖ_ {n = n}) x y ≡ lock t (_+ₖ_ {n = n}) y x
pm unlock = commₖ n x y
-- cohom
+H : (n : ℕ) (x y : coHom n A) → coHom n A
+H n = sRec2 § λ a b → ∣ (λ x → +K n (a x) (b x)) ∣₂
-H : (n : ℕ) (x : coHom n A) → coHom n A
-H n = sRec § λ a → ∣ (λ x → -K n (a x)) ∣₂
-Hbin : (n : ℕ) → coHom n A → coHom n A → coHom n A
-Hbin n = sRec2 § λ a b → ∣ (λ x → -Kbin n (a x) (b x)) ∣₂
rUnitH : (n : ℕ) (x : coHom n A) → +H n x (0ₕ n) ≡ x
rUnitH n = sElim (λ _ → isOfHLevelPath 1 (§ _ _))
λ a i → ∣ funExt (λ x → rUnitK n (a x)) i ∣₂
lUnitH : (n : ℕ) (x : coHom n A) → +H n (0ₕ n) x ≡ x
lUnitH n = sElim (λ _ → isOfHLevelPath 1 (§ _ _))
λ a i → ∣ funExt (λ x → lUnitK n (a x)) i ∣₂
rCancelH : (n : ℕ) (x : coHom n A) → +H n x (-H n x) ≡ 0ₕ n
rCancelH n = sElim (λ _ → isOfHLevelPath 1 (§ _ _))
λ a i → ∣ funExt (λ x → rCancelK n (a x)) i ∣₂
lCancelH : (n : ℕ) (x : coHom n A) → +H n (-H n x) x ≡ 0ₕ n
lCancelH n = sElim (λ _ → isOfHLevelPath 1 (§ _ _))
λ a i → ∣ funExt (λ x → lCancelK n (a x)) i ∣₂
assocH : (n : ℕ) (x y z : coHom n A) → (+H n (+H n x y) z) ≡ (+H n x (+H n y z))
assocH n = elim3 (λ _ _ _ → isOfHLevelPath 1 (§ _ _))
λ a b c i → ∣ funExt (λ x → assocK n (a x) (b x) (c x)) i ∣₂
commH : (n : ℕ) (x y : coHom n A) → (+H n x y) ≡ (+H n y x)
commH n = sElim2 (λ _ _ → isOfHLevelPath 1 (§ _ _))
λ a b i → ∣ funExt (λ x → commK n (a x) (b x)) i ∣₂
-cancelRH : (n : ℕ) (x y : coHom n A) → -Hbin n (+H n y x) x ≡ y
-cancelRH n = sElim2 (λ _ _ → isOfHLevelPath 1 (§ _ _))
λ a b i → ∣ (λ x → -cancelRK n (a x) (b x) i) ∣₂
-cancelLH : (n : ℕ) (x y : coHom n A) → -Hbin n (+H n x y) x ≡ y
-cancelLH n = sElim2 (λ _ _ → isOfHLevelPath 1 (§ _ _))
λ a b i → ∣ (λ x → -cancelLK n (a x) (b x) i) ∣₂
-+cancelH : (n : ℕ) (x y : coHom n A) → +H n (-Hbin n x y) y ≡ x
-+cancelH n = sElim2 (λ _ _ → isOfHLevelPath 1 (§ _ _))
λ a b i → ∣ (λ x → -+cancelK n (a x) (b x) i) ∣₂
+K→∙ : (key : Unit') (n : ℕ) (a b : coHomK n) → Kn→ΩKn+1 n (lockedCohom.+K key n a b) ≡ Kn→ΩKn+1 n a ∙ Kn→ΩKn+1 n b
+K→∙ unlock = +ₖ→∙
+H≡+ₕ : (key : Unit') (n : ℕ) → lockedCohom.+H key {A = A} n ≡ _+ₕ_ {n = n}
+H≡+ₕ unlock _ = refl
rUnitlUnit0K : (key : Unit') (n : ℕ) → lockedCohom.rUnitK key n (0ₖ n) ≡ lockedCohom.lUnitK key n (0ₖ n)
rUnitlUnit0K unlock = rUnitlUnit0
|
Ano_2/LFA/bloco2/ex01/Hello.g4 | Karkanius/MIECT | 7 | 3307 | grammar Hello ; // Define a grammar called Hello
greetings : 'hello' ID ; // match a keyword hello followed by an identifier
ID : [a-z]+ ; // match lower-case identifier
WS : [ \t\r\n]+ -> skip ; // skip spaces, tabs, newlines, \r (Windows)
|
libsrc/_DEVELOPMENT/alloc/malloc/c/sdcc_iy/malloc_fastcall.asm | meesokim/z88dk | 0 | 19391 |
; void *malloc_fastcall(size_t size)
INCLUDE "clib_cfg.asm"
SECTION code_alloc_malloc
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
IF __CLIB_OPT_MULTITHREAD & $01
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
PUBLIC _malloc_fastcall
_malloc_fastcall:
INCLUDE "alloc/malloc/z80/asm_malloc.asm"
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
ELSE
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
PUBLIC _malloc_fastcall
EXTERN _malloc_unlocked_fastcall
defc _malloc_fastcall = _malloc_unlocked_fastcall
INCLUDE "alloc/malloc/z80/asm_malloc.asm"
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
ENDIF
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
oeis/295/A295860.asm | neoneye/loda-programs | 11 | 95241 | <gh_stars>10-100
; A295860: a(n) = a(n-1) + 3*a(n-2) -2*a(n-3) - 2*a(n-4), where a(0) = -2, a(1) = 1, a(2) = 0, a(3) = 1.
; Submitted by <NAME>
; -2,1,0,1,3,4,11,15,34,49,99,148,279,427,770,1197,2095,3292,5643,8935,15090,24025,40139,64164,106351,170515,280962,451477,740631,1192108,1949123,3141231,5123122,8264353,13453011,21717364,35301447,57018811,92582402,149601213,242707903,392309116,636065595,1028374711,1666537458,2694912169,4365643931,7060556100,11434588639,18495144739,29946510594,48441655333,78421720359,126863375692,205352204915,332215580607,537702003250,869917583857,1407888022563,2277805606420,3686230499895,5964036106315
mov $2,1
mov $3,-2
mov $4,1
lpb $0
sub $0,1
mov $5,$1
add $1,$3
mov $3,$4
mov $4,$2
mov $2,$3
mul $2,2
add $5,$4
mov $3,$5
lpe
mov $0,$3
|
Transynther/x86/_processed/NONE/_xt_/i7-7700_9_0xca_notsx.log_21829_1137.asm | ljhsiun2/medusa | 9 | 164509 | <gh_stars>1-10
.global s_prepare_buffers
s_prepare_buffers:
push %r8
push %r9
push %rax
push %rbp
push %rbx
push %rcx
push %rdi
push %rsi
lea addresses_WC_ht+0x925d, %rsi
lea addresses_A_ht+0xd05d, %rdi
clflush (%rdi)
nop
add $4456, %r8
mov $9, %rcx
rep movsl
nop
nop
nop
nop
sub $13476, %r9
lea addresses_UC_ht+0x1955d, %rsi
lea addresses_A_ht+0x1d95d, %rdi
nop
and $53107, %rbp
mov $126, %rcx
rep movsq
nop
nop
nop
nop
xor %r9, %r9
lea addresses_WT_ht+0x70dd, %rsi
nop
nop
nop
add %rax, %rax
movw $0x6162, (%rsi)
nop
cmp $427, %rbp
lea addresses_WT_ht+0x17965, %rsi
nop
nop
sub %rdi, %rdi
mov $0x6162636465666768, %rcx
movq %rcx, (%rsi)
nop
nop
nop
nop
dec %rdi
lea addresses_WT_ht+0xee3d, %rsi
lea addresses_WC_ht+0xd55d, %rdi
nop
nop
nop
nop
xor $43512, %rbx
mov $28, %rcx
rep movsb
nop
nop
nop
nop
nop
inc %rcx
lea addresses_A_ht+0x1d55d, %rsi
nop
nop
nop
xor %rcx, %rcx
movups (%rsi), %xmm5
vpextrq $1, %xmm5, %rbp
nop
nop
nop
xor $11020, %rcx
lea addresses_WT_ht+0x1ac5d, %rax
nop
nop
nop
nop
xor $14906, %r8
mov $0x6162636465666768, %rbp
movq %rbp, (%rax)
nop
nop
nop
nop
nop
sub $26838, %rdi
lea addresses_D_ht+0xbd87, %rsi
lea addresses_A_ht+0x102dd, %rdi
nop
nop
nop
and %rax, %rax
mov $93, %rcx
rep movsq
sub %rbp, %rbp
lea addresses_WT_ht+0x3441, %r8
nop
add %rbp, %rbp
movups (%r8), %xmm3
vpextrq $0, %xmm3, %r9
nop
nop
cmp %rbx, %rbx
lea addresses_WT_ht+0x1cd2b, %rax
nop
nop
nop
nop
nop
and $61160, %r9
mov (%rax), %esi
nop
nop
nop
cmp $55789, %rax
lea addresses_normal_ht+0x695d, %rbx
nop
nop
dec %r9
mov $0x6162636465666768, %r8
movq %r8, %xmm5
vmovups %ymm5, (%rbx)
nop
nop
nop
nop
nop
cmp $61134, %r9
lea addresses_normal_ht+0x1344a, %rbx
nop
nop
nop
and %r9, %r9
movb (%rbx), %al
nop
nop
nop
nop
nop
cmp $41003, %rbp
lea addresses_A_ht+0xdcd, %r9
add %r8, %r8
mov (%r9), %si
nop
nop
nop
cmp $63928, %rdi
pop %rsi
pop %rdi
pop %rcx
pop %rbx
pop %rbp
pop %rax
pop %r9
pop %r8
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r11
push %r12
push %r14
push %r9
push %rax
push %rsi
// Load
lea addresses_UC+0xa6a8, %r10
clflush (%r10)
nop
nop
nop
dec %r9
movb (%r10), %al
nop
nop
and %r11, %r11
// Load
lea addresses_D+0x16d5d, %r12
nop
nop
sub %r14, %r14
mov (%r12), %rax
nop
nop
dec %r9
// Store
lea addresses_A+0x355d, %r9
clflush (%r9)
nop
nop
cmp %r14, %r14
mov $0x5152535455565758, %r10
movq %r10, (%r9)
nop
nop
nop
nop
nop
and $37353, %rax
// Load
lea addresses_normal+0x4f5d, %r9
nop
nop
sub $43477, %r14
mov (%r9), %eax
nop
nop
xor $21710, %r10
// Store
lea addresses_PSE+0x1955d, %r12
nop
cmp %rsi, %rsi
movb $0x51, (%r12)
nop
nop
nop
nop
nop
sub %r9, %r9
// Faulty Load
lea addresses_PSE+0x2d5d, %r9
clflush (%r9)
nop
nop
add %rax, %rax
mov (%r9), %r11w
lea oracles, %r9
and $0xff, %r11
shlq $12, %r11
mov (%r9,%r11,1), %r11
pop %rsi
pop %rax
pop %r9
pop %r14
pop %r12
pop %r11
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'src': {'NT': False, 'AVXalign': False, 'size': 4, 'congruent': 0, 'same': True, 'type': 'addresses_PSE'}, 'OP': 'LOAD'}
{'src': {'NT': False, 'AVXalign': True, 'size': 1, 'congruent': 0, 'same': False, 'type': 'addresses_UC'}, 'OP': 'LOAD'}
{'src': {'NT': False, 'AVXalign': False, 'size': 8, 'congruent': 11, 'same': False, 'type': 'addresses_D'}, 'OP': 'LOAD'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 8, 'congruent': 11, 'same': False, 'type': 'addresses_A'}, 'OP': 'STOR'}
{'src': {'NT': False, 'AVXalign': False, 'size': 4, 'congruent': 8, 'same': False, 'type': 'addresses_normal'}, 'OP': 'LOAD'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 1, 'congruent': 11, 'same': False, 'type': 'addresses_PSE'}, 'OP': 'STOR'}
[Faulty Load]
{'src': {'NT': False, 'AVXalign': False, 'size': 2, 'congruent': 0, 'same': True, 'type': 'addresses_PSE'}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'src': {'congruent': 8, 'same': False, 'type': 'addresses_WC_ht'}, 'dst': {'congruent': 8, 'same': False, 'type': 'addresses_A_ht'}, 'OP': 'REPM'}
{'src': {'congruent': 10, 'same': False, 'type': 'addresses_UC_ht'}, 'dst': {'congruent': 10, 'same': True, 'type': 'addresses_A_ht'}, 'OP': 'REPM'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 2, 'congruent': 7, 'same': False, 'type': 'addresses_WT_ht'}, 'OP': 'STOR'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 8, 'congruent': 2, 'same': False, 'type': 'addresses_WT_ht'}, 'OP': 'STOR'}
{'src': {'congruent': 5, 'same': False, 'type': 'addresses_WT_ht'}, 'dst': {'congruent': 8, 'same': False, 'type': 'addresses_WC_ht'}, 'OP': 'REPM'}
{'src': {'NT': False, 'AVXalign': False, 'size': 16, 'congruent': 11, 'same': False, 'type': 'addresses_A_ht'}, 'OP': 'LOAD'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 8, 'congruent': 8, 'same': False, 'type': 'addresses_WT_ht'}, 'OP': 'STOR'}
{'src': {'congruent': 1, 'same': False, 'type': 'addresses_D_ht'}, 'dst': {'congruent': 5, 'same': True, 'type': 'addresses_A_ht'}, 'OP': 'REPM'}
{'src': {'NT': False, 'AVXalign': False, 'size': 16, 'congruent': 1, 'same': False, 'type': 'addresses_WT_ht'}, 'OP': 'LOAD'}
{'src': {'NT': False, 'AVXalign': False, 'size': 4, 'congruent': 0, 'same': False, 'type': 'addresses_WT_ht'}, 'OP': 'LOAD'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 32, 'congruent': 7, 'same': False, 'type': 'addresses_normal_ht'}, 'OP': 'STOR'}
{'src': {'NT': True, 'AVXalign': False, 'size': 1, 'congruent': 0, 'same': False, 'type': 'addresses_normal_ht'}, 'OP': 'LOAD'}
{'src': {'NT': False, 'AVXalign': False, 'size': 2, 'congruent': 4, 'same': False, 'type': 'addresses_A_ht'}, 'OP': 'LOAD'}
{'33': 21829}
33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33
*/
|
mixins/src/base_type.adb | gerr135/ada_gems | 6 | 21846 | <reponame>gerr135/ada_gems<filename>mixins/src/base_type.adb
with Ada.Text_IO; use Ada.Text_IO;
package body base_type is
procedure method(Self : The_Type) is
begin
Put_Line(" bt:method");
end;
end base_type;
|
data/pokemon/base_stats/shieldon.asm | AtmaBuster/pokeplat-gen2 | 6 | 94597 | db 0 ; species ID placeholder
db 30, 42, 118, 30, 42, 88
; hp atk def spd sat sdf
db ROCK, STEEL ; type
db 45 ; catch rate
db 70 ; base exp
db NO_ITEM, NO_ITEM ; items
db GENDER_F12_5 ; gender ratio
db 30 ; step cycles to hatch
INCBIN "gfx/pokemon/shieldon/front.dimensions"
db GROWTH_ERRATIC ; growth rate
dn EGG_MONSTER, EGG_MONSTER ; egg groups
db 70 ; happiness
; tm/hm learnset
tmhm ROAR, TOXIC, HIDDEN_POWER, SUNNY_DAY, TAUNT, ICE_BEAM, BLIZZARD, PROTECT, RAIN_DANCE, FRUSTRATION, IRON_TAIL, THUNDERBOLT, THUNDER, EARTHQUAKE, RETURN, DIG, DOUBLE_TEAM, SHOCK_WAVE, FLAMETHROWER, SANDSTORM, FIRE_BLAST, ROCK_TOMB, TORMENT, FACADE, SECRET_POWER, REST, ATTRACT, ENDURE, ROCK_POLISH, STONE_EDGE, STEALTH_ROCK, CAPTIVATE, ROCK_SLIDE, SLEEP_TALK, NATURAL_GIFT, SWAGGER, SUBSTITUTE, FLASH_CANNON, STRENGTH, ROCK_SMASH, ANCIENTPOWER, EARTH_POWER, IRON_DEFENSE, IRON_HEAD, MAGNET_RISE, SNORE
; end
|
src/tool-template/src/main/antlr4/io/ciera/tool/templateengine/parser/RSLLexer.g4 | lwriemen/ciera | 0 | 3147 | lexer grammar RSLLexer;
// THE 'INITIAL' MODE IS FOR MATCHING SEQUENCES AT THE BEGINNING OF A LINE
COMMENT: [ \t]* '.' '/' '/' ( ~( [\r\n] ) )+ ( '\r\n' | '\n' ) -> skip;
INITIAL_DOT: [ \t]* '.' -> skip, pushMode(CONTROL);
INITIAL_BLOB: ( [ \t]+ | [ \t]* ( ~( [$ \t\r\n.] ) | '$$' | '..' ) ( ~( [$\r\n] ) | '$$' )* ) -> type(BLOB), pushMode(BUFFER);
INITIAL_DOLLAR: DOLLAR -> type(DOLLAR), pushMode(BUFFER), pushMode(SUBVAR);
INITIAL_NEWLINE: NEWLINE -> type(NEWLINE);
// THE 'BUFFER' MODE IS FOR MATCHING LITERAL TEXT WITHIN A LINE
mode BUFFER;
DOLLAR: '$' -> pushMode(SUBVAR);
BLOB: ( ~( [$\r\n] ) | [ \t] | '$$' )+;
BUFFER_NEWLINE: NEWLINE -> popMode, type(NEWLINE);
// THE 'STRING' MODE IS FOR MATCHING LITERAL TEXT WITHIN QUOTATION MARKS
mode STRING;
STRING_DOLLAR: DOLLAR -> type(DOLLAR), pushMode(SUBVAR);
STRING_BLOB: ( ~( [$\r\n"] ) | [ \t] | '$$' | '""' )+ -> type(BLOB);
STRING_QUOTE: QUOTE -> type(QUOTE), popMode;
// THE 'SUBVAR' MODE IS FOR MATCHING FORMAT CHARACTERS IN A SUBSTITUTION
mode SUBVAR;
FORMAT: ( [ucl_rot] )+ ;
LCURLY: '{' -> pushMode(CONTROL);
// THE 'CONTROL' MODE IS FOR MATCHING RSL CONTROL STRUCTURES
mode CONTROL;
// literals
BOOLEAN_LITERAL: 'true' | 'false';
INTEGER_LITERAL: '0' | '-'? [1-9][0-9]*;
REAL_LITERAL: '-'? ( '0' | [1-9][0-9]* ) '.' [0-9]+; // allows -0.0 but oh well
// keywords
IF: 'if';
ELIF: 'elif';
ELSE: 'else';
END: 'end';
// symbols
DOT: '.';
RCURLY: '}' -> popMode, popMode;
QUOTE: '"' -> pushMode(STRING);
EMPTY: 'empty';
NOT_EMPTY: 'not_empty';
NOT: 'not';
MINUS: '-';
AND: 'and';
OR: 'or';
PLUS: '+';
TIMES: '*';
DIVIDE: '/';
REM: '%';
LT: '<';
LTE: '<=';
GT: '>';
GTE: '>=';
EQ: '==';
NE: '!=';
LPAREN: '(';
RPAREN: ')';
NEWLINE: ( '\r\n' | '\n' ) -> popMode;
ID: [a-zA-Z][a-zA-Z0-9_]* ;
WS: [ \t] -> skip;
|
notes/FOT/FOL/SchemataATP.agda | asr/fotc | 11 | 12410 | ------------------------------------------------------------------------------
-- Testing the FOL schemata
------------------------------------------------------------------------------
{-# OPTIONS --exact-split #-}
{-# OPTIONS --no-sized-types #-}
{-# OPTIONS --no-universe-polymorphism #-}
{-# OPTIONS --without-K #-}
module FOT.FOL.SchemataATP where
open import FOL.Base
------------------------------------------------------------------------------
postulate id₁ : {A₁ : D → Set} → ∀ {x} → A₁ x → A₁ x
{-# ATP prove id₁ #-}
id₂ : {A₁ : D → Set} → ∀ {x} → A₁ x → A₁ x
id₂ {A} {x} = prf
where
postulate prf : A x → A x
{-# ATP prove prf #-}
|
misc/RecursiveDescent/Hybrid/Mixfix/Fixity.agda | yurrriq/parser-combinators | 7 | 3288 | ------------------------------------------------------------------------
-- Fixity and associativity
------------------------------------------------------------------------
module RecursiveDescent.Hybrid.Mixfix.Fixity where
open import Data.Fin using (Fin; zero; suc; #_)
open import Data.Fin.Props using (eq?)
open import Relation.Nullary
open import Relation.Binary
open import Relation.Binary.PropositionalEquality
data Associativity : Set where
left : Associativity
right : Associativity
non : Associativity
-- A combination of fixity and associativity. Only infix operators
-- have associativity.
-- Note that infix is a reserved word.
data Fixity : Set where
prefx : Fixity
infx : (assoc : Associativity) -> Fixity
postfx : Fixity
closed : Fixity
Fixity-is-finite : LeftInverse Fixity (Fin 6)
Fixity-is-finite = record
{ from = from
; to = to
; left-inverse = left-inverse
}
where
to : Fixity -> Fin 6
to prefx = # 0
to (infx left) = # 1
to (infx right) = # 2
to (infx non) = # 3
to postfx = # 4
to closed = # 5
from : Fin 6 -> Fixity
from zero = prefx
from (suc zero) = infx left
from (suc (suc zero)) = infx right
from (suc (suc (suc zero))) = infx non
from (suc (suc (suc (suc zero)))) = postfx
from (suc (suc (suc (suc (suc zero))))) = closed
from (suc (suc (suc (suc (suc (suc ()))))))
left-inverse : from LeftInverseOf to
left-inverse prefx = refl
left-inverse (infx left) = refl
left-inverse (infx right) = refl
left-inverse (infx non) = refl
left-inverse postfx = refl
left-inverse closed = refl
_≟_ : Decidable (_≡_ {Fixity})
_≟_ = eq? injection
where open LeftInverse Fixity-is-finite
|
src/InitDevice.adb | mokafiht/u2f_key_SDCC | 1 | 23518 | <gh_stars>1-10
M:InitDevice
F:G$enter_DefaultMode_from_RESET$0$0({2}DF,SV:S),Z,0,0,0,0,0
S:LInitDevice.enter_DefaultMode_from_RESET$SFRPAGE_save$1$21({1}SC:U),R,0,0,[r7]
F:G$VREG_0_enter_DefaultMode_from_RESET$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$CLOCK_0_enter_DefaultMode_from_RESET$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$PORTS_0_enter_DefaultMode_from_RESET$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$PORTS_1_enter_DefaultMode_from_RESET$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$PBCFG_0_enter_DefaultMode_from_RESET$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$CIP51_0_enter_DefaultMode_from_RESET$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$TIMER01_0_enter_DefaultMode_from_RESET$0$0({2}DF,SV:S),Z,0,0,0,0,0
S:LInitDevice.TIMER01_0_enter_DefaultMode_from_RESET$TCON_save$1$35({1}SC:U),R,0,0,[r7]
F:G$TIMER16_2_enter_DefaultMode_from_RESET$0$0({2}DF,SV:S),Z,0,0,0,0,0
S:LInitDevice.TIMER16_2_enter_DefaultMode_from_RESET$TMR2CN0_TR2_save$1$37({1}SC:U),R,0,0,[r7]
F:G$TIMER16_3_enter_DefaultMode_from_RESET$0$0({2}DF,SV:S),Z,0,0,0,0,0
S:LInitDevice.TIMER16_3_enter_DefaultMode_from_RESET$TMR3CN0_TR3_save$1$39({1}SC:U),R,0,0,[r7]
F:G$TIMER_SETUP_0_enter_DefaultMode_from_RESET$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$SMBUS_0_enter_DefaultMode_from_RESET$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$UART_0_enter_DefaultMode_from_RESET$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$INTERRUPT_0_enter_DefaultMode_from_RESET$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$PCA_0_enter_DefaultMode_from_RESET$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$PCACH_0_enter_DefaultMode_from_RESET$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$PCACH_1_enter_DefaultMode_from_RESET$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$PCACH_2_enter_DefaultMode_from_RESET$0$0({2}DF,SV:S),Z,0,0,0,0,0
T:FInitDevice$SI_UU32[({0}S:S$u32$0$0({4}SL:U),Z,0,0)({0}S:S$s32$0$0({4}SL:S),Z,0,0)({0}S:S$uu16$0$0({4}DA2d,STSI_UU16:S),Z,0,0)({0}S:S$u16$0$0({4}DA2d,SI:U),Z,0,0)({0}S:S$s16$0$0({4}DA2d,SI:S),Z,0,0)({0}S:S$u8$0$0({4}DA4d,SC:U),Z,0,0)({0}S:S$s8$0$0({4}DA4d,SC:S),Z,0,0)]
T:FInitDevice$SI_UU16[({0}S:S$u16$0$0({2}SI:U),Z,0,0)({0}S:S$s16$0$0({2}SI:S),Z,0,0)({0}S:S$u8$0$0({2}DA2d,SC:U),Z,0,0)({0}S:S$s8$0$0({2}DA2d,SC:S),Z,0,0)]
T:FInitDevice$SI_GEN_PTR[({0}S:S$u8$0$0({3}DA3d,SC:U),Z,0,0)({0}S:S$gptr$0$0({3}ST__00000000:S),Z,0,0)]
T:FInitDevice$__00000000[({0}S:S$memtype$0$0({1}SC:U),Z,0,0)({1}S:S$address$0$0({2}STSI_UU16:S),Z,0,0)]
S:G$ACC$0$0({1}SC:U),I,0,0
S:G$ADC0AC$0$0({1}SC:U),I,0,0
S:G$ADC0CF$0$0({1}SC:U),I,0,0
S:G$ADC0CN0$0$0({1}SC:U),I,0,0
S:G$ADC0CN1$0$0({1}SC:U),I,0,0
S:G$ADC0GTH$0$0({1}SC:U),I,0,0
S:G$ADC0GTL$0$0({1}SC:U),I,0,0
S:G$ADC0H$0$0({1}SC:U),I,0,0
S:G$ADC0L$0$0({1}SC:U),I,0,0
S:G$ADC0LTH$0$0({1}SC:U),I,0,0
S:G$ADC0LTL$0$0({1}SC:U),I,0,0
S:G$ADC0MX$0$0({1}SC:U),I,0,0
S:G$ADC0PWR$0$0({1}SC:U),I,0,0
S:G$ADC0TK$0$0({1}SC:U),I,0,0
S:G$B$0$0({1}SC:U),I,0,0
S:G$CKCON0$0$0({1}SC:U),I,0,0
S:G$CKCON1$0$0({1}SC:U),I,0,0
S:G$CLKSEL$0$0({1}SC:U),I,0,0
S:G$CMP0CN0$0$0({1}SC:U),I,0,0
S:G$CMP0CN1$0$0({1}SC:U),I,0,0
S:G$CMP0MD$0$0({1}SC:U),I,0,0
S:G$CMP0MX$0$0({1}SC:U),I,0,0
S:G$CMP1CN0$0$0({1}SC:U),I,0,0
S:G$CMP1CN1$0$0({1}SC:U),I,0,0
S:G$CMP1MD$0$0({1}SC:U),I,0,0
S:G$CMP1MX$0$0({1}SC:U),I,0,0
S:G$CRC0CN0$0$0({1}SC:U),I,0,0
S:G$CRC0CN1$0$0({1}SC:U),I,0,0
S:G$CRC0CNT$0$0({1}SC:U),I,0,0
S:G$CRC0DAT$0$0({1}SC:U),I,0,0
S:G$CRC0FLIP$0$0({1}SC:U),I,0,0
S:G$CRC0IN$0$0({1}SC:U),I,0,0
S:G$CRC0ST$0$0({1}SC:U),I,0,0
S:G$DERIVID$0$0({1}SC:U),I,0,0
S:G$DEVICEID$0$0({1}SC:U),I,0,0
S:G$DPH$0$0({1}SC:U),I,0,0
S:G$DPL$0$0({1}SC:U),I,0,0
S:G$EIE1$0$0({1}SC:U),I,0,0
S:G$EIE2$0$0({1}SC:U),I,0,0
S:G$EIP1$0$0({1}SC:U),I,0,0
S:G$EIP1H$0$0({1}SC:U),I,0,0
S:G$EIP2$0$0({1}SC:U),I,0,0
S:G$EIP2H$0$0({1}SC:U),I,0,0
S:G$EMI0CN$0$0({1}SC:U),I,0,0
S:G$FLKEY$0$0({1}SC:U),I,0,0
S:G$HFO0CAL$0$0({1}SC:U),I,0,0
S:G$HFO1CAL$0$0({1}SC:U),I,0,0
S:G$HFOCN$0$0({1}SC:U),I,0,0
S:G$I2C0CN0$0$0({1}SC:U),I,0,0
S:G$I2C0DIN$0$0({1}SC:U),I,0,0
S:G$I2C0DOUT$0$0({1}SC:U),I,0,0
S:G$I2C0FCN0$0$0({1}SC:U),I,0,0
S:G$I2C0FCN1$0$0({1}SC:U),I,0,0
S:G$I2C0FCT$0$0({1}SC:U),I,0,0
S:G$I2C0SLAD$0$0({1}SC:U),I,0,0
S:G$I2C0STAT$0$0({1}SC:U),I,0,0
S:G$IE$0$0({1}SC:U),I,0,0
S:G$IP$0$0({1}SC:U),I,0,0
S:G$IPH$0$0({1}SC:U),I,0,0
S:G$IT01CF$0$0({1}SC:U),I,0,0
S:G$LFO0CN$0$0({1}SC:U),I,0,0
S:G$P0$0$0({1}SC:U),I,0,0
S:G$P0MASK$0$0({1}SC:U),I,0,0
S:G$P0MAT$0$0({1}SC:U),I,0,0
S:G$P0MDIN$0$0({1}SC:U),I,0,0
S:G$P0MDOUT$0$0({1}SC:U),I,0,0
S:G$P0SKIP$0$0({1}SC:U),I,0,0
S:G$P1$0$0({1}SC:U),I,0,0
S:G$P1MASK$0$0({1}SC:U),I,0,0
S:G$P1MAT$0$0({1}SC:U),I,0,0
S:G$P1MDIN$0$0({1}SC:U),I,0,0
S:G$P1MDOUT$0$0({1}SC:U),I,0,0
S:G$P1SKIP$0$0({1}SC:U),I,0,0
S:G$P2$0$0({1}SC:U),I,0,0
S:G$P2MASK$0$0({1}SC:U),I,0,0
S:G$P2MAT$0$0({1}SC:U),I,0,0
S:G$P2MDIN$0$0({1}SC:U),I,0,0
S:G$P2MDOUT$0$0({1}SC:U),I,0,0
S:G$P2SKIP$0$0({1}SC:U),I,0,0
S:G$P3$0$0({1}SC:U),I,0,0
S:G$P3MDIN$0$0({1}SC:U),I,0,0
S:G$P3MDOUT$0$0({1}SC:U),I,0,0
S:G$PCA0CENT$0$0({1}SC:U),I,0,0
S:G$PCA0CLR$0$0({1}SC:U),I,0,0
S:G$PCA0CN0$0$0({1}SC:U),I,0,0
S:G$PCA0CPH0$0$0({1}SC:U),I,0,0
S:G$PCA0CPH1$0$0({1}SC:U),I,0,0
S:G$PCA0CPH2$0$0({1}SC:U),I,0,0
S:G$PCA0CPL0$0$0({1}SC:U),I,0,0
S:G$PCA0CPL1$0$0({1}SC:U),I,0,0
S:G$PCA0CPL2$0$0({1}SC:U),I,0,0
S:G$PCA0CPM0$0$0({1}SC:U),I,0,0
S:G$PCA0CPM1$0$0({1}SC:U),I,0,0
S:G$PCA0CPM2$0$0({1}SC:U),I,0,0
S:G$PCA0H$0$0({1}SC:U),I,0,0
S:G$PCA0L$0$0({1}SC:U),I,0,0
S:G$PCA0MD$0$0({1}SC:U),I,0,0
S:G$PCA0POL$0$0({1}SC:U),I,0,0
S:G$PCA0PWM$0$0({1}SC:U),I,0,0
S:G$PCON0$0$0({1}SC:U),I,0,0
S:G$PCON1$0$0({1}SC:U),I,0,0
S:G$PFE0CN$0$0({1}SC:U),I,0,0
S:G$PRTDRV$0$0({1}SC:U),I,0,0
S:G$PSCTL$0$0({1}SC:U),I,0,0
S:G$PSW$0$0({1}SC:U),I,0,0
S:G$REF0CN$0$0({1}SC:U),I,0,0
S:G$REG0CN$0$0({1}SC:U),I,0,0
S:G$REG1CN$0$0({1}SC:U),I,0,0
S:G$REVID$0$0({1}SC:U),I,0,0
S:G$RSTSRC$0$0({1}SC:U),I,0,0
S:G$SBCON1$0$0({1}SC:U),I,0,0
S:G$SBRLH1$0$0({1}SC:U),I,0,0
S:G$SBRLL1$0$0({1}SC:U),I,0,0
S:G$SBUF0$0$0({1}SC:U),I,0,0
S:G$SBUF1$0$0({1}SC:U),I,0,0
S:G$SCON0$0$0({1}SC:U),I,0,0
S:G$SCON1$0$0({1}SC:U),I,0,0
S:G$SFRPAGE$0$0({1}SC:U),I,0,0
S:G$SFRPGCN$0$0({1}SC:U),I,0,0
S:G$SFRSTACK$0$0({1}SC:U),I,0,0
S:G$SMB0ADM$0$0({1}SC:U),I,0,0
S:G$SMB0ADR$0$0({1}SC:U),I,0,0
S:G$SMB0CF$0$0({1}SC:U),I,0,0
S:G$SMB0CN0$0$0({1}SC:U),I,0,0
S:G$SMB0DAT$0$0({1}SC:U),I,0,0
S:G$SMB0FCN0$0$0({1}SC:U),I,0,0
S:G$SMB0FCN1$0$0({1}SC:U),I,0,0
S:G$SMB0FCT$0$0({1}SC:U),I,0,0
S:G$SMB0RXLN$0$0({1}SC:U),I,0,0
S:G$SMB0TC$0$0({1}SC:U),I,0,0
S:G$SMOD1$0$0({1}SC:U),I,0,0
S:G$SP$0$0({1}SC:U),I,0,0
S:G$SPI0CFG$0$0({1}SC:U),I,0,0
S:G$SPI0CKR$0$0({1}SC:U),I,0,0
S:G$SPI0CN0$0$0({1}SC:U),I,0,0
S:G$SPI0DAT$0$0({1}SC:U),I,0,0
S:G$SPI0FCN0$0$0({1}SC:U),I,0,0
S:G$SPI0FCN1$0$0({1}SC:U),I,0,0
S:G$SPI0FCT$0$0({1}SC:U),I,0,0
S:G$TCON$0$0({1}SC:U),I,0,0
S:G$TH0$0$0({1}SC:U),I,0,0
S:G$TH1$0$0({1}SC:U),I,0,0
S:G$TL0$0$0({1}SC:U),I,0,0
S:G$TL1$0$0({1}SC:U),I,0,0
S:G$TMOD$0$0({1}SC:U),I,0,0
S:G$TMR2CN0$0$0({1}SC:U),I,0,0
S:G$TMR2CN1$0$0({1}SC:U),I,0,0
S:G$TMR2H$0$0({1}SC:U),I,0,0
S:G$TMR2L$0$0({1}SC:U),I,0,0
S:G$TMR2RLH$0$0({1}SC:U),I,0,0
S:G$TMR2RLL$0$0({1}SC:U),I,0,0
S:G$TMR3CN0$0$0({1}SC:U),I,0,0
S:G$TMR3CN1$0$0({1}SC:U),I,0,0
S:G$TMR3H$0$0({1}SC:U),I,0,0
S:G$TMR3L$0$0({1}SC:U),I,0,0
S:G$TMR3RLH$0$0({1}SC:U),I,0,0
S:G$TMR3RLL$0$0({1}SC:U),I,0,0
S:G$TMR4CN0$0$0({1}SC:U),I,0,0
S:G$TMR4CN1$0$0({1}SC:U),I,0,0
S:G$TMR4H$0$0({1}SC:U),I,0,0
S:G$TMR4L$0$0({1}SC:U),I,0,0
S:G$TMR4RLH$0$0({1}SC:U),I,0,0
S:G$TMR4RLL$0$0({1}SC:U),I,0,0
S:G$UART1FCN0$0$0({1}SC:U),I,0,0
S:G$UART1FCN1$0$0({1}SC:U),I,0,0
S:G$UART1FCT$0$0({1}SC:U),I,0,0
S:G$UART1LIN$0$0({1}SC:U),I,0,0
S:G$USB0ADR$0$0({1}SC:U),I,0,0
S:G$USB0AEC$0$0({1}SC:U),I,0,0
S:G$USB0CDCF$0$0({1}SC:U),I,0,0
S:G$USB0CDCN$0$0({1}SC:U),I,0,0
S:G$USB0CDSTA$0$0({1}SC:U),I,0,0
S:G$USB0CF$0$0({1}SC:U),I,0,0
S:G$USB0DAT$0$0({1}SC:U),I,0,0
S:G$USB0XCN$0$0({1}SC:U),I,0,0
S:G$VDM0CN$0$0({1}SC:U),I,0,0
S:G$WDTCN$0$0({1}SC:U),I,0,0
S:G$XBR0$0$0({1}SC:U),I,0,0
S:G$XBR1$0$0({1}SC:U),I,0,0
S:G$XBR2$0$0({1}SC:U),I,0,0
S:G$ADC0GT$0$0({2}SI:U),I,0,0
S:G$ADC0$0$0({2}SI:U),I,0,0
S:G$ADC0LT$0$0({2}SI:U),I,0,0
S:G$DP$0$0({2}SI:U),I,0,0
S:G$PCA0CP0$0$0({2}SI:U),I,0,0
S:G$PCA0CP1$0$0({2}SI:U),I,0,0
S:G$PCA0CP2$0$0({2}SI:U),I,0,0
S:G$PCA0$0$0({2}SI:U),I,0,0
S:G$SBRL1$0$0({2}SI:U),I,0,0
S:G$TMR2$0$0({2}SI:U),I,0,0
S:G$TMR2RL$0$0({2}SI:U),I,0,0
S:G$TMR3$0$0({2}SI:U),I,0,0
S:G$TMR3RL$0$0({2}SI:U),I,0,0
S:G$TMR4$0$0({2}SI:U),I,0,0
S:G$TMR4RL$0$0({2}SI:U),I,0,0
S:G$_XPAGE$0$0({1}SC:U),I,0,0
S:G$ACC_ACC0$0$0({1}SX:U),J,0,0
S:G$ACC_ACC1$0$0({1}SX:U),J,0,0
S:G$ACC_ACC2$0$0({1}SX:U),J,0,0
S:G$ACC_ACC3$0$0({1}SX:U),J,0,0
S:G$ACC_ACC4$0$0({1}SX:U),J,0,0
S:G$ACC_ACC5$0$0({1}SX:U),J,0,0
S:G$ACC_ACC6$0$0({1}SX:U),J,0,0
S:G$ACC_ACC7$0$0({1}SX:U),J,0,0
S:G$ADC0CN0_ADCM0$0$0({1}SX:U),J,0,0
S:G$ADC0CN0_ADCM1$0$0({1}SX:U),J,0,0
S:G$ADC0CN0_ADCM2$0$0({1}SX:U),J,0,0
S:G$ADC0CN0_ADWINT$0$0({1}SX:U),J,0,0
S:G$ADC0CN0_ADBUSY$0$0({1}SX:U),J,0,0
S:G$ADC0CN0_ADINT$0$0({1}SX:U),J,0,0
S:G$ADC0CN0_ADBMEN$0$0({1}SX:U),J,0,0
S:G$ADC0CN0_ADEN$0$0({1}SX:U),J,0,0
S:G$B_B0$0$0({1}SX:U),J,0,0
S:G$B_B1$0$0({1}SX:U),J,0,0
S:G$B_B2$0$0({1}SX:U),J,0,0
S:G$B_B3$0$0({1}SX:U),J,0,0
S:G$B_B4$0$0({1}SX:U),J,0,0
S:G$B_B5$0$0({1}SX:U),J,0,0
S:G$B_B6$0$0({1}SX:U),J,0,0
S:G$B_B7$0$0({1}SX:U),J,0,0
S:G$IE_EX0$0$0({1}SX:U),J,0,0
S:G$IE_ET0$0$0({1}SX:U),J,0,0
S:G$IE_EX1$0$0({1}SX:U),J,0,0
S:G$IE_ET1$0$0({1}SX:U),J,0,0
S:G$IE_ES0$0$0({1}SX:U),J,0,0
S:G$IE_ET2$0$0({1}SX:U),J,0,0
S:G$IE_ESPI0$0$0({1}SX:U),J,0,0
S:G$IE_EA$0$0({1}SX:U),J,0,0
S:G$IP_PX0$0$0({1}SX:U),J,0,0
S:G$IP_PT0$0$0({1}SX:U),J,0,0
S:G$IP_PX1$0$0({1}SX:U),J,0,0
S:G$IP_PT1$0$0({1}SX:U),J,0,0
S:G$IP_PS0$0$0({1}SX:U),J,0,0
S:G$IP_PT2$0$0({1}SX:U),J,0,0
S:G$IP_PSPI0$0$0({1}SX:U),J,0,0
S:G$P0_B0$0$0({1}SX:U),J,0,0
S:G$P0_B1$0$0({1}SX:U),J,0,0
S:G$P0_B2$0$0({1}SX:U),J,0,0
S:G$P0_B3$0$0({1}SX:U),J,0,0
S:G$P0_B4$0$0({1}SX:U),J,0,0
S:G$P0_B5$0$0({1}SX:U),J,0,0
S:G$P0_B6$0$0({1}SX:U),J,0,0
S:G$P0_B7$0$0({1}SX:U),J,0,0
S:G$P1_B0$0$0({1}SX:U),J,0,0
S:G$P1_B1$0$0({1}SX:U),J,0,0
S:G$P1_B2$0$0({1}SX:U),J,0,0
S:G$P1_B3$0$0({1}SX:U),J,0,0
S:G$P1_B4$0$0({1}SX:U),J,0,0
S:G$P1_B5$0$0({1}SX:U),J,0,0
S:G$P1_B6$0$0({1}SX:U),J,0,0
S:G$P1_B7$0$0({1}SX:U),J,0,0
S:G$P2_B0$0$0({1}SX:U),J,0,0
S:G$P2_B1$0$0({1}SX:U),J,0,0
S:G$P2_B2$0$0({1}SX:U),J,0,0
S:G$P2_B3$0$0({1}SX:U),J,0,0
S:G$P3_B0$0$0({1}SX:U),J,0,0
S:G$P3_B1$0$0({1}SX:U),J,0,0
S:G$PCA0CN0_CCF0$0$0({1}SX:U),J,0,0
S:G$PCA0CN0_CCF1$0$0({1}SX:U),J,0,0
S:G$PCA0CN0_CCF2$0$0({1}SX:U),J,0,0
S:G$PCA0CN0_CR$0$0({1}SX:U),J,0,0
S:G$PCA0CN0_CF$0$0({1}SX:U),J,0,0
S:G$PSW_PARITY$0$0({1}SX:U),J,0,0
S:G$PSW_F1$0$0({1}SX:U),J,0,0
S:G$PSW_OV$0$0({1}SX:U),J,0,0
S:G$PSW_RS0$0$0({1}SX:U),J,0,0
S:G$PSW_RS1$0$0({1}SX:U),J,0,0
S:G$PSW_F0$0$0({1}SX:U),J,0,0
S:G$PSW_AC$0$0({1}SX:U),J,0,0
S:G$PSW_CY$0$0({1}SX:U),J,0,0
S:G$SCON0_RI$0$0({1}SX:U),J,0,0
S:G$SCON0_TI$0$0({1}SX:U),J,0,0
S:G$SCON0_RB8$0$0({1}SX:U),J,0,0
S:G$SCON0_TB8$0$0({1}SX:U),J,0,0
S:G$SCON0_REN$0$0({1}SX:U),J,0,0
S:G$SCON0_MCE$0$0({1}SX:U),J,0,0
S:G$SCON0_SMODE$0$0({1}SX:U),J,0,0
S:G$SCON1_RI$0$0({1}SX:U),J,0,0
S:G$SCON1_TI$0$0({1}SX:U),J,0,0
S:G$SCON1_RBX$0$0({1}SX:U),J,0,0
S:G$SCON1_TBX$0$0({1}SX:U),J,0,0
S:G$SCON1_REN$0$0({1}SX:U),J,0,0
S:G$SCON1_PERR$0$0({1}SX:U),J,0,0
S:G$SCON1_OVR$0$0({1}SX:U),J,0,0
S:G$SMB0CN0_SI$0$0({1}SX:U),J,0,0
S:G$SMB0CN0_ACK$0$0({1}SX:U),J,0,0
S:G$SMB0CN0_ARBLOST$0$0({1}SX:U),J,0,0
S:G$SMB0CN0_ACKRQ$0$0({1}SX:U),J,0,0
S:G$SMB0CN0_STO$0$0({1}SX:U),J,0,0
S:G$SMB0CN0_STA$0$0({1}SX:U),J,0,0
S:G$SMB0CN0_TXMODE$0$0({1}SX:U),J,0,0
S:G$SMB0CN0_MASTER$0$0({1}SX:U),J,0,0
S:G$SPI0CN0_SPIEN$0$0({1}SX:U),J,0,0
S:G$SPI0CN0_TXNF$0$0({1}SX:U),J,0,0
S:G$SPI0CN0_NSSMD0$0$0({1}SX:U),J,0,0
S:G$SPI0CN0_NSSMD1$0$0({1}SX:U),J,0,0
S:G$SPI0CN0_RXOVRN$0$0({1}SX:U),J,0,0
S:G$SPI0CN0_MODF$0$0({1}SX:U),J,0,0
S:G$SPI0CN0_WCOL$0$0({1}SX:U),J,0,0
S:G$SPI0CN0_SPIF$0$0({1}SX:U),J,0,0
S:G$TCON_IT0$0$0({1}SX:U),J,0,0
S:G$TCON_IE0$0$0({1}SX:U),J,0,0
S:G$TCON_IT1$0$0({1}SX:U),J,0,0
S:G$TCON_IE1$0$0({1}SX:U),J,0,0
S:G$TCON_TR0$0$0({1}SX:U),J,0,0
S:G$TCON_TF0$0$0({1}SX:U),J,0,0
S:G$TCON_TR1$0$0({1}SX:U),J,0,0
S:G$TCON_TF1$0$0({1}SX:U),J,0,0
S:G$TMR2CN0_T2XCLK0$0$0({1}SX:U),J,0,0
S:G$TMR2CN0_T2XCLK1$0$0({1}SX:U),J,0,0
S:G$TMR2CN0_TR2$0$0({1}SX:U),J,0,0
S:G$TMR2CN0_T2SPLIT$0$0({1}SX:U),J,0,0
S:G$TMR2CN0_TF2CEN$0$0({1}SX:U),J,0,0
S:G$TMR2CN0_TF2LEN$0$0({1}SX:U),J,0,0
S:G$TMR2CN0_TF2L$0$0({1}SX:U),J,0,0
S:G$TMR2CN0_TF2H$0$0({1}SX:U),J,0,0
S:G$TMR4CN0_T4XCLK0$0$0({1}SX:U),J,0,0
S:G$TMR4CN0_T4XCLK1$0$0({1}SX:U),J,0,0
S:G$TMR4CN0_TR4$0$0({1}SX:U),J,0,0
S:G$TMR4CN0_T4SPLIT$0$0({1}SX:U),J,0,0
S:G$TMR4CN0_TF4CEN$0$0({1}SX:U),J,0,0
S:G$TMR4CN0_TF4LEN$0$0({1}SX:U),J,0,0
S:G$TMR4CN0_TF4L$0$0({1}SX:U),J,0,0
S:G$TMR4CN0_TF4H$0$0({1}SX:U),J,0,0
S:G$UART1FCN1_RIE$0$0({1}SX:U),J,0,0
S:G$UART1FCN1_RXTO0$0$0({1}SX:U),J,0,0
S:G$UART1FCN1_RXTO1$0$0({1}SX:U),J,0,0
S:G$UART1FCN1_RFRQ$0$0({1}SX:U),J,0,0
S:G$UART1FCN1_TIE$0$0({1}SX:U),J,0,0
S:G$UART1FCN1_TXHOLD$0$0({1}SX:U),J,0,0
S:G$UART1FCN1_TXNF$0$0({1}SX:U),J,0,0
S:G$UART1FCN1_TFRQ$0$0({1}SX:U),J,0,0
S:G$HFOSC_0_enter_DefaultMode_from_RESET$0$0({2}DF,SV:S),C,0,0
|
PMOO/ADA/Lab_1_2_Ada/probar_cines.adb | usainzg/EHU | 0 | 6042 | <reponame>usainzg/EHU<filename>PMOO/ADA/Lab_1_2_Ada/probar_cines.adb
WITH Ada.Text_IO;
USE Ada.Text_IO;
WITH Salas, Cine;
USE Salas;
PROCEDURE Probar_Cines IS
S1,
S2,
S3,
S4,
S5 : Salas.Sala;
BEGIN
S1 := Crear_Sala(" Ava ", 12,18);
Modificar_Pelicula(S1, "FormaDAgua");
S2 := Crear_Sala("Marilyn", 12,18);
Modificar_Pelicula(S2,"BlackPanth");
S3 := Crear_Sala("Audrey ", 11,10);
Modificar_Pelicula(S3,"HiloInvisi");
S4 := Crear_Sala("Hepburn", 11,10);
Modificar_Pelicula(S4,"CuaderSara");
S5 := Crear_Sala(" Rita ", 11,10);
Modificar_Pelicula(S5,"HiloInvisi");
Cine.Crear_Cine(" Golem ");
Cine.Anadir_Sala(S1);
Cine.Anadir_Sala(S2);
Cine.Anadir_Sala(S3);
Cine.Anadir_Sala(S4);
Cine.Anadir_Sala(S5);
Cine.Mostrar_Salas;
Cine.Mostrar_Cartelera;
New_Line;
New_Line;
Cine.Vender_Localidades_Contiguas("HiloInvisi", 9);
Cine.Vender_Localidades_Contiguas( "HiloInvisi" ,8);
Cine.Vender_Localidades_Contiguas( "HiloInvisi", 7);
Cine.Vender_Localidades_Contiguas("HiloInvisi", 6);
Cine.Vender_Localidades_Contiguas("HiloInvisi", 5);
Cine.Vender_Localidades_Contiguas("HiloInvisi", 10);
Cine.Vender_Localidades_Contiguas("HiloInvisi", 6);
Cine.Vender_Localidades_Contiguas("HiloInvisi", 3);
Cine.Vender_Localidades_Contiguas("HiloInvisi", 10);
Cine.Vender_Localidades_Contiguas("HiloInvisi", 10);
Cine.Vender_Localidades_Contiguas("HiloInvisi", 10);
Cine.Vender_Localidades_Contiguas("HiloInvisi", 10);
Cine.Vender_Localidades_Contiguas("HiloInvisi", 6);
Cine.Vender_Localidades_Contiguas("HiloInvisi", 6);
Cine.Vender_Localidades_Contiguas("CuaderSara", 10);
Cine.Vender_Localidades_Contiguas("CuaderSara", 10);
Cine.Vender_Localidades_Contiguas("CuaderSara", 10);
Cine.Vender_Localidades_Contiguas("CuaderSara", 10);
Cine.Mostrar_Salas;
Cine.Cambiar_Peliculas("HiloInvisi", "SinPelicul");
Cine.Mostrar_Cartelera;
END Probar_Cines;
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1-base/math/applet/test/suite/math_tests-geometry_2d.adb | charlie5/lace-alire | 1 | 8648 | <reponame>charlie5/lace-alire
with
Ahven,
float_Math.Geometry.d2;
package body math_Tests.Geometry_2d
is
use Ahven,
float_Math;
function almost_Equal (Left, Right : in Real) return Boolean
is
Tolerance : constant := 0.000_001;
begin
return abs (Left - Right) <= Tolerance;
end almost_Equal;
procedure Polygon_is_convex_Test
is
use float_Math.Geometry.d2;
the_Poly : Polygon := (vertex_Count => 4,
vertices => ((-1.0, -1.0),
( 1.0, -1.0),
( 1.0, 1.0),
(-1.0, 1.0)));
begin
assert (is_Convex (the_Poly),
"T1 => " & Image (the_Poly) & " should be convex ... failed !");
the_Poly.Vertices (3) := (0.0, 0.0);
assert (is_Convex (the_Poly),
"T2 => " & Image (the_Poly) & " should be convex ... failed !");
the_Poly.Vertices (3) := (0.0, 0.1);
assert (is_Convex (the_Poly),
"T3 => " & Image (the_Poly) & " should be convex ... failed !");
the_Poly.Vertices (3) := (0.0, -0.1);
assert (not is_Convex (the_Poly),
"T4 => " & Image (the_Poly) & " should not be convex ... failed !");
end Polygon_is_convex_Test;
procedure triangle_Area_Test
is
use float_Math.Geometry.d2;
the_Tri : Triangle := (vertices => (( 0.0, 0.0),
( 1.0, 0.0),
( 1.0, 1.0)));
begin
assert (almost_Equal (Area (the_Tri), 0.5),
"T1 => & Image (the_Tri) & area should be 0.5 ... failed ! " & Image (Area (the_Tri), 12));
the_Tri := (vertices => ((-0.11073643, -0.179634809),
(-0.0553682148, 0.410182595),
(-0.0276841074, 0.705091298)));
assert (Area (the_Tri) >= 0.0,
"T2 => & Image (the_Tri) & area should be positive ... failed !");
the_Tri := (vertices => ((-1.0, -1.0),
( 1.0, -1.0),
( 1.0, -0.999999)));
assert (Area (the_Tri) > 0.0,
"T3 => & Image (the_Tri) & area should be positive ... failed !");
the_Tri := (vertices => ((-0.11073643, -0.179634809),
(-0.0276841074, 0.705091298),
(-0.0553682148, 0.410182595)));
assert (Area (the_Tri) >= 0.0,
"T4 => & Image (the_Tri) & area should be positive ... failed !");
-- tbd: Add tests for degenerate triangles.
end triangle_Area_Test;
overriding
procedure Initialize (T : in out Test) is
begin
T.set_Name ("Geometry (2D) Tests");
Framework.add_test_Routine (T, Polygon_is_convex_Test'Access, "Polygon is convex Test");
Framework.add_test_Routine (T, triangle_Area_Test 'Access, "Triangle area Test");
end Initialize;
end math_Tests.Geometry_2d;
|
ASMFiles/procedures in Assembly.asm | Undeadtaker/Assembly | 0 | 242343 | <filename>ASMFiles/procedures in Assembly.asm<gh_stars>0
.model small
.data
.code
first proc ; every process should begin with its name, after that have the name proc that signals the beginning of the process
mov dl, 51 ; the first procedure changes the value of the dl reg to 51 (hex 3)
; jmp jump ; this would be an illegal statement. We can't jump from one process to another ones' label.
ret ; every process should have a ret word in it (return), except the main process
first endp ; we end the process with its name and the word endp
main proc ; the word proc actually means procedure and this is the main procedure where the code is executed.
; the concept of procedures is actually somewhat similar to methods, where this main proc is the main method
mov dl, 53
mov ah, 02h
int 21h
call first ; How we actually call the procedure,
int 21h ; print to screen again
hlt ; command to halt the CPU cycle
; label:
; label:: ; the jump label is now global, meaning it can be accessed from everywhere. BUT IT IS NOT RECOMMENDED AT ALL!!!
endp ; the endp means that we end the main process, not the whole program! If we want to write more processes
; we should write them after endp and before endmain
end main
|
Data/BitVector/ContainmentOrder.agda | copumpkin/bitvector | 3 | 15480 | <reponame>copumpkin/bitvector<gh_stars>1-10
module Data.BitVector.ContainmentOrder where
open import Data.Empty
open import Data.Sum
open import Data.Vec
open import Relation.Nullary
open import Relation.Binary
open import Relation.Binary.PropositionalEquality
open import Data.Nat hiding (_≟_; _≤_; _≤?_) renaming (zero to Nzero; suc to Nsuc)
open import Data.BitVector
infix 4 _⊂_
data _⊂_ : ∀ {n} → BitVector n → BitVector n → Set where
[]⊂[] : [] ⊂ []
0#⊂0# : ∀ {n} {x y : BitVector n} → (x⊂y : x ⊂ y) → (0# ∷ x) ⊂ (0# ∷ y)
b⊂1# : ∀ {n} {x y : BitVector n} {b} → (x⊂y : x ⊂ y) → (b ∷ x) ⊂ (1# ∷ y)
⊂-refl : ∀ {n} → _≡_ ⇒ (_⊂_ {n})
⊂-refl {0} {[]} refl = []⊂[]
⊂-refl {Nsuc n} {0# ∷ xs} refl = 0#⊂0# (⊂-refl refl)
⊂-refl {Nsuc n} {1# ∷ xs} refl = b⊂1# (⊂-refl refl)
⊂-antisym : ∀ {n} → Antisymmetric _≡_ (_⊂_ {n})
⊂-antisym []⊂[] []⊂[] = refl
⊂-antisym (0#⊂0# x⊂y) (0#⊂0# y⊂x) rewrite ⊂-antisym x⊂y y⊂x = refl
⊂-antisym (b⊂1# x⊂y) (b⊂1# y⊂x) rewrite ⊂-antisym x⊂y y⊂x = refl
⊂-trans : ∀ {n} → Transitive (_⊂_ {n})
⊂-trans []⊂[] []⊂[] = []⊂[]
⊂-trans (0#⊂0# x⊂y) (0#⊂0# y⊂z) = 0#⊂0# (⊂-trans x⊂y y⊂z)
⊂-trans (0#⊂0# x⊂y) (b⊂1# y⊂z) = b⊂1# (⊂-trans x⊂y y⊂z)
⊂-trans (b⊂1# x⊂y) (b⊂1# y⊂z) = b⊂1# (⊂-trans x⊂y y⊂z)
_⊂?_ : ∀ {n} → Decidable (_⊂_ {n})
[] ⊂? [] = yes []⊂[]
(x ∷ xs) ⊂? (y ∷ ys) with xs ⊂? ys
(0# ∷ xs) ⊂? (0# ∷ ys) | no xs≢ys = no helper
where helper : ¬ 0# ∷ xs ⊂ 0# ∷ ys
helper (0#⊂0# pf) = xs≢ys pf
(x ∷ xs) ⊂? (1# ∷ ys) | no xs≢ys = no helper
where helper : ¬ x ∷ xs ⊂ 1# ∷ ys
helper (b⊂1# pf) = xs≢ys pf
(1# ∷ xs) ⊂? (0# ∷ ys) | no xs≢ys = no (λ ())
(0# ∷ xs) ⊂? (0# ∷ ys) | yes xs≡ys = yes (0#⊂0# xs≡ys)
(0# ∷ xs) ⊂? (1# ∷ ys) | yes xs≡ys = yes (b⊂1# xs≡ys)
(1# ∷ xs) ⊂? (0# ∷ ys) | yes xs≡ys = no (λ ())
(1# ∷ xs) ⊂? (1# ∷ ys) | yes xs≡ys = yes (b⊂1# xs≡ys)
decPoset : ∀ {n} → DecPoset _ _ _
decPoset {n} = record
{ Carrier = BitVector n
; _≈_ = _≡_
; _≤_ = _⊂_
; isDecPartialOrder = record
{ isPartialOrder = record
{ isPreorder = record
{ isEquivalence = isEquivalence
; reflexive = ⊂-refl
; trans = ⊂-trans
}
; antisym = ⊂-antisym
}
; _≟_ = _≟_
; _≤?_ = _⊂?_
}
} |
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