id stringlengths 22 129 | text stringlengths 60 19.5k | arch stringclasses 9
values | syntax stringclasses 5
values | kind stringclasses 4
values | repo stringclasses 32
values | path stringlengths 7 108 | license stringclasses 10
values | commit stringlengths 40 40 | source_host stringclasses 1
value | category stringclasses 15
values | source_url stringlengths 85 192 | line_start int64 1 5.48k | line_end int64 4 5.5k |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NetBSD/src:sys/arch/powerpc/powerpc/trap_subr.S:24 | mfdar %r30
mfdsisr %r31
streg %r30,(CI_TEMPSAVE+CPUSAVE_DAR)(%r1)
streg %r31,(CI_TEMPSAVE+CPUSAVE_DSISR)(%r1)
#ifdef DDB
mfsrr1 %r31
mtcr %r31
bt MSR_PR,trapstart /* branch is user mode */
mfsprg1 %r31 /* get old SP */
#if 0
subf %r30,%r30,%r31 /* subtract DAR from it */
addi %r30,%r30,2048 /* offset resu... | powerpc | gas-like | handwritten | NetBSD/src | sys/arch/powerpc/powerpc/trap_subr.S | BSD-2-Clause | bf17480c06c0c6855be3bc73cce3e8b499cc40ab | github | kernel | https://github.com/NetBSD/src/blob/bf17480c06c0c6855be3bc73cce3e8b499cc40ab/sys/arch/powerpc/powerpc/trap_subr.S | 921 | 980 |
NetBSD/src:sys/arch/powerpc/powerpc/trap_subr.S:25 | mtcr %r1
mfsprg1 %r1 /* restore SP (might have been
overwritten) */
s_trap:
bf MSR_PR,k_trap /* branch if PSL_PR is false */
GET_CPUINFO(%r1) /* get cpu_info for this cpu */
u_trap:
ldptr %r1,CI_CURPCB(%r1)
addi %r1,%r1,USPACE-CALLFRAMELEN /* stack is top of user struct */
/*
* Now the common trap ca... | powerpc | gas-like | handwritten | NetBSD/src | sys/arch/powerpc/powerpc/trap_subr.S | BSD-2-Clause | bf17480c06c0c6855be3bc73cce3e8b499cc40ab | github | kernel | https://github.com/NetBSD/src/blob/bf17480c06c0c6855be3bc73cce3e8b499cc40ab/sys/arch/powerpc/powerpc/trap_subr.S | 961 | 1,020 |
NetBSD/src:sys/arch/powerpc/powerpc/trap_subr.S:26 | andi. %r4,%r4,1
beq trapleave
li %r6,EXC_AST
stint %r6,FRAME_EXC(%r1)
b trapagain
trapleave:
FRAME_RESTORE_CALLEE
intrleave:
FRAME_LEAVE(CI_TEMPSAVE)
RFI
/*
* Trap handler for syscalls (EXC_SC)
*/
/* LINTSTUB: Var: int sctrap[1], scsize[1]; */
.globl _C_LABEL(sctrap),_C_LABEL(scsize),_C_LABEL(sctrapexit)
_... | powerpc | gas-like | handwritten | NetBSD/src | sys/arch/powerpc/powerpc/trap_subr.S | BSD-2-Clause | bf17480c06c0c6855be3bc73cce3e8b499cc40ab | github | kernel | https://github.com/NetBSD/src/blob/bf17480c06c0c6855be3bc73cce3e8b499cc40ab/sys/arch/powerpc/powerpc/trap_subr.S | 1,001 | 1,060 |
NetBSD/src:sys/arch/powerpc/powerpc/trap_subr.S:27 | ldptr %r1,CI_CURPCB(%r1)
addi %r1,%r1,USPACE-CALLFRAMELEN /* stack is top of user struct */
RESTORE_KERN_SRS(%r30,%r31) /* First enable KERNEL mapping */
FRAME_SETUP(CI_TEMPSAVE)
/* Now we can recover interrupts again: */
mfmsr %r7
ori %r7,%r7,(PSL_EE|PSL_ME|PSL_RI)@l
mtmsr %r7
isync
addi %r3,%r1,FRAME_TF
/* Ca... | powerpc | gas-like | handwritten | NetBSD/src | sys/arch/powerpc/powerpc/trap_subr.S | BSD-2-Clause | bf17480c06c0c6855be3bc73cce3e8b499cc40ab | github | kernel | https://github.com/NetBSD/src/blob/bf17480c06c0c6855be3bc73cce3e8b499cc40ab/sys/arch/powerpc/powerpc/trap_subr.S | 1,041 | 1,100 |
NetBSD/src:sys/arch/powerpc/powerpc/trap_subr.S:28 | ori %r30,%r30,(PSL_DR|PSL_IR); /* turn on relocation */ \
mtmsr %r30; /* stack can be accessed now */ \
isync; \
mfsprg1 %r31; /* get saved SP */ \
stregu %r31,-FRAMELEN(%r1); /* save it in the callframe */ \
streg %r0,FRAME_R0(%r1); /* save R0 in the trapframe */ \
streg %r31,FRAME_R1(%r1); /* save S... | powerpc | gas-like | handwritten | NetBSD/src | sys/arch/powerpc/powerpc/trap_subr.S | BSD-2-Clause | bf17480c06c0c6855be3bc73cce3e8b499cc40ab | github | kernel | https://github.com/NetBSD/src/blob/bf17480c06c0c6855be3bc73cce3e8b499cc40ab/sys/arch/powerpc/powerpc/trap_subr.S | 1,081 | 1,140 |
NetBSD/src:sys/arch/powerpc/powerpc/trap_subr.S:29 | ori %r6,%r6,PSL_RI; /* turn on recovery interrupt */\
mtmsr %r6; \
SAVE_VRSAVE(%r1,%r6); \
SAVE_MQ(%r1,%r7)
/* LINTSTUB: Var: int extint_call[1]; */
/*
* R1=sp, R28=LR, R29=CR, R30=scratch, R31=scratch
*/
.globl _C_LABEL(extint_call)
extintr:
INTR_SETUP(CI_TEMPSAVE, EXC_EXI)
/* make trapframe a... | powerpc | gas-like | handwritten | NetBSD/src | sys/arch/powerpc/powerpc/trap_subr.S | BSD-2-Clause | bf17480c06c0c6855be3bc73cce3e8b499cc40ab | github | kernel | https://github.com/NetBSD/src/blob/bf17480c06c0c6855be3bc73cce3e8b499cc40ab/sys/arch/powerpc/powerpc/trap_subr.S | 1,121 | 1,180 |
NetBSD/src:sys/arch/powerpc/powerpc/trap_subr.S:30 | streg %r16,FRAME_R16(%r1)
streg %r17,FRAME_R17(%r1)
streg %r18,FRAME_R18(%r1)
streg %r19,FRAME_R19(%r1)
streg %r20,FRAME_R20(%r1)
streg %r21,FRAME_R21(%r1)
streg %r22,FRAME_R22(%r1)
streg %r23,FRAME_R23(%r1)
streg %r24,FRAME_R24(%r1)
streg %r25,FRAME_R25(%r1)
streg %r26,FRAME_R26(%r1)
streg %r27,FRAME_R27(%r... | powerpc | gas-like | handwritten | NetBSD/src | sys/arch/powerpc/powerpc/trap_subr.S | BSD-2-Clause | bf17480c06c0c6855be3bc73cce3e8b499cc40ab | github | kernel | https://github.com/NetBSD/src/blob/bf17480c06c0c6855be3bc73cce3e8b499cc40ab/sys/arch/powerpc/powerpc/trap_subr.S | 1,161 | 1,220 |
NetBSD/src:sys/arch/powerpc/powerpc/trap_subr.S:31 | .globl _C_LABEL(ddb_trap)
_C_LABEL(ddb_trap):
mtsprg1 %r1
mfmsr %r3
mtsrr1 %r3
andi. %r3,%r3,~(PSL_EE|PSL_ME)@l
mtmsr %r3 /* disable interrupts */
isync
ENABLE_64BIT_BRIDGE(%r3)
GET_CPUINFO(%r3)
streg %r28,(CI_DDBSAVE+CPUSAVE_R28)(%r3)
streg %r29,(CI_DDBSAVE+CPUSAVE_R29)(%r3)
streg %r30,(CI_DDBSAVE+CPUSAVE... | powerpc | gas-like | handwritten | NetBSD/src | sys/arch/powerpc/powerpc/trap_subr.S | BSD-2-Clause | bf17480c06c0c6855be3bc73cce3e8b499cc40ab | github | kernel | https://github.com/NetBSD/src/blob/bf17480c06c0c6855be3bc73cce3e8b499cc40ab/sys/arch/powerpc/powerpc/trap_subr.S | 1,201 | 1,248 |
NetBSD/src:sys/arch/powerpc/powerpc/trap_subr.S:7 | _C_LABEL(alisize) = .-_C_LABEL(alitrap)
#if !defined(PPC_MPC8XX)
/*
* Similar to the above for DSI
* Has to handle BAT spills
* and standard pagetable spills
*/
/* LINTSTUB: Var: int dsicode[1], dsisize[1]; */
.globl _C_LABEL(dsitrap),_C_LABEL(dsisize)
_C_LABEL(dsitrap):
mtsprg1 %r1
ENABLE_64BIT_BRIDGE(%r1)
GE... | powerpc | gas-like | handwritten | NetBSD/src | sys/arch/powerpc/powerpc/trap_subr.S | BSD-2-Clause | 3a3e6e6861107fa30395b99abb65697f94ef1bf8 | github | kernel | https://github.com/NetBSD/src/blob/3a3e6e6861107fa30395b99abb65697f94ef1bf8/sys/arch/powerpc/powerpc/trap_subr.S | 241 | 300 |
NetBSD/src:sys/arch/powerpc/powerpc/trap_subr.S:8 | bf 30,1f /* branch if supervisor valid is
false */
/* get batl */
ldreg %r31,SZREG(%r31)
/* We randomly use the highest two bat registers here */
mftb %r28
mtcr %r28
.globl dsitrap_fix_dbat4, dsitrap_fix_dbat5
.globl dsitrap_fix_dbat6, dsitrap_fix_dbat7
dsitrap_fix_dbat4:
bt 31,3f
/*
* If we are run... | powerpc | gas-like | handwritten | NetBSD/src | sys/arch/powerpc/powerpc/trap_subr.S | BSD-2-Clause | 3a3e6e6861107fa30395b99abb65697f94ef1bf8 | github | kernel | https://github.com/NetBSD/src/blob/3a3e6e6861107fa30395b99abb65697f94ef1bf8/sys/arch/powerpc/powerpc/trap_subr.S | 281 | 340 |
NetBSD/src:sys/arch/prep/prep/locore.S:2 | #include <sys/syscall.h>
#include <machine/param.h>
#include <machine/psl.h>
#include <machine/trap.h>
#include <machine/asm.h>
#include <powerpc/spr.h>
#include <powerpc/oea/spr.h>
#include "ksyms.h"
/*
* Some instructions gas doesn't understand (yet?)
*/
#define bdneq bdnzf 2,
/*
* cache bit
*/
#define HID0_... | x86_64 | gas-like | handwritten | NetBSD/src | sys/arch/prep/prep/locore.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/prep/prep/locore.S | 41 | 100 |
NetBSD/src:sys/arch/prep/prep/locore.S:3 | */
.text
.globl _C_LABEL(kernel_text)
_C_LABEL(kernel_text):
/*
* Startup entry. Note, this must be the first thing in the text
* segment!
*/
.text
.globl __start
__start:
li 0,0
mtmsr 0 /* Disable FPU/MMU/exceptions */
isync
/* compute end of kernel memory */
#if NKSYMS || defined(DDB) || defined(MODULA... | x86_64 | gas-like | handwritten | NetBSD/src | sys/arch/prep/prep/locore.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/prep/prep/locore.S | 81 | 140 |
NetBSD/src:sys/arch/prep/prep/locore.S:4 | beq 3f /* not needed for 601 */
mfspr 11,SPR_HID0
andi. 0,11,HID0_DCE
ori 11,11,HID0_ICE|HID0_DCE
ori 8,11,HID0_ICFI
bne 1f /* don't invalidate the D-cache */
ori 8,8,HID0_DCI /* unless it wasn't enabled */
1:
sync
mtspr SPR_HID0,8 /* enable and invalidate caches */
sync
mtspr SPR_HID0,11 /* enable cac... | x86_64 | gas-like | handwritten | NetBSD/src | sys/arch/prep/prep/locore.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/prep/prep/locore.S | 121 | 180 |
NetBSD/src:sys/arch/prep/prep/locore.S:5 | .globl _C_LABEL(disable_intr)
_C_LABEL(disable_intr):
mfmsr 3
andi. 4,3,~PSL_EE@l
mtmsr 4
blr
/*
* Pull in common switch / setfault code.
*/
#include <powerpc/powerpc/locore_subr.S>
/*
* Pull in common trap vector code.
*/
#include <powerpc/powerpc/trap_subr.S>
/*
* Pull in common pio / bus_space code.
*/
... | x86_64 | gas-like | handwritten | NetBSD/src | sys/arch/prep/prep/locore.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/prep/prep/locore.S | 161 | 182 |
NetBSD/src:sys/arch/prep/stand/boot/srt0.s:1 | /* $NetBSD: srt0.s,v 1.3 2005/12/11 12:18:48 christos Exp $ */
/*
* Copyright (C) 1996-1999 Cort Dougan (cort@fsmlasb.com).
* Copyright (C) 1996-1999 Gary Thomas (gdt@osf.org).
* Copyright (C) 1996-1999 Paul Mackeras (paulus@linuxcare.com).
* All rights reserved.
*
* Redistribution and use in source and binary f... | arm64 | gas-like | handwritten | NetBSD/src | sys/arch/prep/stand/boot/srt0.s | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/prep/stand/boot/srt0.s | 1 | 60 |
NetBSD/src:sys/arch/prep/stand/boot/srt0.s:2 | .text
.globl _start
_start:
bl start
start:
mr 11,3 /* Save pointer to residual/board data */
li 3,MSR_IP /* Establish default MSR value */
mtmsr 3
isync
mflr 7
bl flush_icache
mfspr 3,1008
lis 4,~(HID0_ICE|HID0_DCE)@h
ori 4,4,~(HID0_ICE|HID0_DCE)@l
andc 3,3,4
mtspr 1008,3
mtlr 7
/*
* check if we nee... | arm64 | gas-like | handwritten | NetBSD/src | sys/arch/prep/stand/boot/srt0.s | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/prep/stand/boot/srt0.s | 41 | 100 |
NetBSD/src:sys/arch/prep/stand/boot/srt0.s:3 | lis 5,end@h
ori 5,5,end@l
addi 5,5,3 /* Round up - just in case */
sub 5,5,4 /* Compute # longwords to move */
srwi 5,5,2
mtctr 5
subi 3,3,4 /* Set up for loop */
subi 4,4,4
2:
lwzu 5,4(3)
stwu 5,4(4)
bdnz 2b
lis 3,start_ldr@h
ori 3,3,start_ldr@l
mtlr 3 /* Easiest way to do an absolute jump */
blr
s... | arm64 | gas-like | handwritten | NetBSD/src | sys/arch/prep/stand/boot/srt0.s | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/prep/stand/boot/srt0.s | 81 | 140 |
NetBSD/src:sys/arch/prep/stand/boot/srt0.s:4 | */
.globl flush_icache
flush_icache:
mflr 5
bl flush_dcache
mfspr 4,1008
li 4,0
ori 4,4,HID0_ICE|HID0_ICFI
or 3,3,4
mtspr 1008,3
andc 3,3,4
ori 3,3,HID0_ICE
mtspr 1008,3
mtlr 5
blr
/*
* Flush data cache
*/
.globl flush_dcache
flush_dcache:
lis 3,0x1000@h
ori 3,3,0x1000@l
li 4,1024
mtctr 4
1:
lwz 4... | arm64 | gas-like | handwritten | NetBSD/src | sys/arch/prep/stand/boot/srt0.s | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/prep/stand/boot/srt0.s | 121 | 155 |
NetBSD/src:sys/arch/riscv/riscv/bus_space_generic.S:2 | /* void bs_c_4(a0: tag, a1: src, srcoffset, dst, dstoffset, count); */
/* void bs_c_8(a0: tag, a1: src, srcoffset, dst, dstoffset, count); */
/* void bs_sr_1(a0: tag, a1: addr, a2: offset, a3: value, a4: count); */
/* void bs_sr_2(a0: tag, a1: addr, a2: offset, a3: value, a4: count); */
/* void bs_sr_4(a0: tag, a1: ad... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/bus_space_generic.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/bus_space_generic.S | 41 | 100 |
NetBSD/src:sys/arch/riscv/riscv/bus_space_generic.S:3 | /* uint64_t bs_r_8(a0: tag, a1: addr, a2: offset); */
ENTRY_NP(generic_bs_r_8)
PTR_L a5, BS_STRIDE(a0) /* stride */
PTR_SLL a2, a2, a5 /* offset <<= stride */
PTR_ADD a2, a2, a1 /* add to address */
ld a0, 0(a2) /* load 64-bit */
ret
END(generic_bs_r_8)
#endif
/* void bs_rm_1(a0: tag, a1: addr, a2: offset, a3... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/bus_space_generic.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/bus_space_generic.S | 81 | 140 |
NetBSD/src:sys/arch/riscv/riscv/bus_space_generic.S:4 | PTR_L a5, BS_STRIDE(a0) /* stride */
PTR_SLL a2, a2, a5 /* offset <<= stride */
PTR_ADD a2, a2, a1 /* add to address */
1:
lhu a0, 0(a2) /* load 16-bit */
sh a0, 0(a3) /* store 16-bit */
add a3, a3, 2
add a4, a4, -1 /* count-- */
bnez a4, 1b
ret
2:
la a0, 3f
tail _C_LABEL(panic)
3:
.asciz "_bs_rm_2: cou... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/bus_space_generic.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/bus_space_generic.S | 121 | 180 |
NetBSD/src:sys/arch/riscv/riscv/bus_space_generic.S:5 | END(generic_bs_rm_4)
#ifdef _LP64
/* void bs_rm_8(a0: tag, a1: addr, a2: offset, a3: datap, a4: count); */
ENTRY_NP(generic_bs_rm_8)
#ifdef DIAGNOSTIC
beqz a4, 2f
#endif
PTR_L a5, BS_STRIDE(a0) /* stride */
PTR_SLL a2, a2, a5 /* offset <<= stride */
PTR_ADD a2, a2, a1 /* add to address */
1:
ld a0, 0(a2) /* l... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/bus_space_generic.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/bus_space_generic.S | 161 | 220 |
NetBSD/src:sys/arch/riscv/riscv/bus_space_generic.S:6 | lbu a0, 0(a2) /* load 8-bit */
sb a0, 0(a3) /* *dst = value */
add a2, a2, t0 /* src += delta */
add a3, a3, 1 /* dst++ */
add a4, a4, -1 /* count-- */
bnez a4, 1b
ret
2:
la a0, 3f
tail _C_LABEL(panic)
3:
.asciz "_bs_rr_1: count == 0"
.balign 4, 0
END(generic_bs_rr_1)
/* void bs_rr_2(a0: tag, a1: addr,... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/bus_space_generic.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/bus_space_generic.S | 201 | 260 |
NetBSD/src:sys/arch/riscv/riscv/bus_space_generic.S:7 | tail _C_LABEL(panic)
3:
.asciz "_bs_rr_2: count == 0"
.balign 4, 0
END(generic_bs_rr_2)
/* void bs_rr_4(a0: tag, a1: addr, a2: offset, a3: datap, a4: count); */
/* void bs_rr_8(a0: tag, a1: addr, a2: offset, a3: datap, a4: count); */
/* void bs_w_1(a0: tag, a1: addr, a2: offset, a3: value); */
ENTRY_NP(generic_b... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/bus_space_generic.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/bus_space_generic.S | 241 | 300 |
NetBSD/src:sys/arch/riscv/riscv/bus_space_generic.S:8 | #ifdef _LP64
/* void bs_w_8(a0: tag, a1: addr, a2: offset, a3: value); */
ENTRY_NP(generic_bs_w_8)
PTR_L a5, BS_STRIDE(a0) /* stride */
PTR_SLL a2, a2, a5 /* offset <<= stride */
PTR_ADD a2, a2, a1 /* add to address */
sd a3, 0(a2) /* store 64-bit */
ret
END(generic_bs_w_8)
#endif
/* void bs_wm_1(a0: tag, a1:... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/bus_space_generic.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/bus_space_generic.S | 281 | 340 |
NetBSD/src:sys/arch/riscv/riscv/bus_space_generic.S:9 | #ifdef DIAGNOSTIC
beqz a4, 2f
#endif
PTR_L a5, BS_STRIDE(a0) /* stride */
PTR_SLL a2, a2, a5 /* offset <<= stride */
PTR_ADD a2, a2, a1 /* add to address */
1:
lhu a0, 0(a3) /* load 16-bit */
sh a0, 0(a2) /* store 16-bit */
add a3, a3, 2
add a4, a4, -1 /* count-- */
bnez a4, 1b
ret
2:
la a0, 3f
tail _C... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/bus_space_generic.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/bus_space_generic.S | 321 | 380 |
NetBSD/src:sys/arch/riscv/riscv/bus_space_generic.S:10 | 3:
.asciz "_bs_wm_4: count == 0"
.balign 4, 0
END(generic_bs_wm_4)
#ifdef _LP64
/* void bs_wm_8(a0: tag, a1: addr, a2: offset, a3: datap, a4: count); */
ENTRY_NP(generic_bs_wm_8)
#ifdef DIAGNOSTIC
beqz a4, 2f
#endif
PTR_L a5, BS_STRIDE(a0) /* stride */
PTR_SLL a2, a2, a5 /* offset <<= stride */
PTR_ADD a2, a2,... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/bus_space_generic.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/bus_space_generic.S | 361 | 395 |
NetBSD/src:sys/arch/riscv/riscv/bus_space_generic.S:3 | /* uint64_t bs_r_8(a0: tag, a1: addr, a2: offset); */
ENTRY_NP(generic_bs_r_8)
PTR_L a5, BS_STRIDE(a0) /* stride */
PTR_SLL a2, a2, a5 /* offset <<= stride */
PTR_ADD a2, a2, a1 /* add to address */
ld a0, 0(a2) /* load 64-bit */
ret
END(generic_bs_r_8)
#endif
/* void bs_rm_1(a0: tag, a1: addr, a2: offset, a3... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/bus_space_generic.S | BSD-2-Clause | 6f60f891c42d9b2faeefeb7252ae193c785ed546 | github | kernel | https://github.com/NetBSD/src/blob/6f60f891c42d9b2faeefeb7252ae193c785ed546/sys/arch/riscv/riscv/bus_space_generic.S | 81 | 140 |
NetBSD/src:sys/arch/riscv/riscv/bus_space_generic.S:4 | PTR_SLL a2, a2, a5 /* offset <<= stride */
PTR_ADD a2, a2, a1 /* add to address */
1:
lhu a0, 0(a2) /* load 16-bit */
sh a0, 0(a3) /* store 16-bit */
add a3, a3, 2
add a4, a4, -1 /* count-- */
bnez a4, 1b
ret
2:
la a0, 3f
tail _C_LABEL(panic)
3:
.asciz "_bs_rm_2: count == 0"
END(generic_bs_rm_2)
/* voi... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/bus_space_generic.S | BSD-2-Clause | 6f60f891c42d9b2faeefeb7252ae193c785ed546 | github | kernel | https://github.com/NetBSD/src/blob/6f60f891c42d9b2faeefeb7252ae193c785ed546/sys/arch/riscv/riscv/bus_space_generic.S | 121 | 180 |
NetBSD/src:sys/arch/riscv/riscv/bus_space_generic.S:5 | #ifdef _LP64
/* void bs_rm_8(a0: tag, a1: addr, a2: offset, a3: datap, a4: count); */
ENTRY_NP(generic_bs_rm_8)
#ifdef DIAGNOSTIC
beqz a4, 2f
#endif
PTR_L a5, BS_STRIDE(a0) /* stride */
PTR_SLL a2, a2, a5 /* offset <<= stride */
PTR_ADD a2, a2, a1 /* add to address */
1:
ld a0, 0(a2) /* load 64-bit */
sd a0, 0... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/bus_space_generic.S | BSD-2-Clause | 6f60f891c42d9b2faeefeb7252ae193c785ed546 | github | kernel | https://github.com/NetBSD/src/blob/6f60f891c42d9b2faeefeb7252ae193c785ed546/sys/arch/riscv/riscv/bus_space_generic.S | 161 | 220 |
NetBSD/src:sys/arch/riscv/riscv/bus_space_generic.S:6 | add a4, a4, -1 /* count-- */
bnez a4, 1b
ret
2:
la a0, 3f
tail _C_LABEL(panic)
3:
.asciz "_bs_rr_1: count == 0"
END(generic_bs_rr_1)
/* void bs_rr_2(a0: tag, a1: addr, a2: offset, a3: datap, a4: count); */
ENTRY_NP(generic_bs_rr_2)
#ifdef DIAGNOSTIC
beqz a4, 2f
#endif
PTR_L a5, BS_STRIDE(a0) /* stride */
li ... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/bus_space_generic.S | BSD-2-Clause | 6f60f891c42d9b2faeefeb7252ae193c785ed546 | github | kernel | https://github.com/NetBSD/src/blob/6f60f891c42d9b2faeefeb7252ae193c785ed546/sys/arch/riscv/riscv/bus_space_generic.S | 201 | 260 |
NetBSD/src:sys/arch/riscv/riscv/bus_space_generic.S:7 | /* void bs_rr_4(a0: tag, a1: addr, a2: offset, a3: datap, a4: count); */
/* void bs_rr_8(a0: tag, a1: addr, a2: offset, a3: datap, a4: count); */
/* void bs_w_1(a0: tag, a1: addr, a2: offset, a3: value); */
ENTRY_NP(generic_bs_w_1)
PTR_L a5, BS_STRIDE(a0) /* stride */
PTR_SLL a2, a2, a5 /* offset <<= stride */
P... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/bus_space_generic.S | BSD-2-Clause | 6f60f891c42d9b2faeefeb7252ae193c785ed546 | github | kernel | https://github.com/NetBSD/src/blob/6f60f891c42d9b2faeefeb7252ae193c785ed546/sys/arch/riscv/riscv/bus_space_generic.S | 241 | 300 |
NetBSD/src:sys/arch/riscv/riscv/bus_space_generic.S:8 | PTR_SLL a2, a2, a5 /* offset <<= stride */
PTR_ADD a2, a2, a1 /* add to address */
sd a3, 0(a2) /* store 64-bit */
ret
END(generic_bs_w_8)
#endif
/* void bs_wm_1(a0: tag, a1: addr, a2: offset, a3: datap, a4: count); */
ENTRY_NP(generic_bs_wm_1)
#ifdef DIAGNOSTIC
beqz a4, 2f
#endif
PTR_L a5, BS_STRIDE(a0) /* s... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/bus_space_generic.S | BSD-2-Clause | 6f60f891c42d9b2faeefeb7252ae193c785ed546 | github | kernel | https://github.com/NetBSD/src/blob/6f60f891c42d9b2faeefeb7252ae193c785ed546/sys/arch/riscv/riscv/bus_space_generic.S | 281 | 340 |
NetBSD/src:sys/arch/riscv/riscv/bus_space_generic.S:9 | lhu a0, 0(a3) /* load 16-bit */
sh a0, 0(a2) /* store 16-bit */
add a3, a3, 2
add a4, a4, -1 /* count-- */
bnez a4, 1b
ret
2:
la a0, 3f
tail _C_LABEL(panic)
3:
.asciz "_bs_wm_2: count == 0"
END(generic_bs_wm_2)
/* void bs_wm_4(a0: tag, a1: addr, a2: offset, a3: datap, a4: count); */
ENTRY_NP(generic_bs_wm_... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/bus_space_generic.S | BSD-2-Clause | 6f60f891c42d9b2faeefeb7252ae193c785ed546 | github | kernel | https://github.com/NetBSD/src/blob/6f60f891c42d9b2faeefeb7252ae193c785ed546/sys/arch/riscv/riscv/bus_space_generic.S | 321 | 380 |
NetBSD/src:sys/arch/riscv/riscv/bus_space_generic.S:10 | #ifdef DIAGNOSTIC
beqz a4, 2f
#endif
PTR_L a5, BS_STRIDE(a0) /* stride */
PTR_SLL a2, a2, a5 /* offset <<= stride */
PTR_ADD a2, a2, a1 /* add to address */
1:
ld a0, 0(a3) /* load 64-bit */
sd a0, 0(a2) /* store 64-bit */
add a3, a3, 8
add a4, a4, -1 /* count-- */
bnez a4, 1b
ret
2:
la a0, 3f
tail _C_... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/bus_space_generic.S | BSD-2-Clause | 6f60f891c42d9b2faeefeb7252ae193c785ed546 | github | kernel | https://github.com/NetBSD/src/blob/6f60f891c42d9b2faeefeb7252ae193c785ed546/sys/arch/riscv/riscv/bus_space_generic.S | 361 | 385 |
NetBSD/src:sys/arch/riscv/riscv/bus_space_generic.S:3 | /* uint64_t bs_r_8(a0: tag, a1: addr, a2: offset); */
ENTRY_NP(generic_bs_r_8)
PTR_L a5, BS_STRIDE(a0) /* stride */
PTR_SLL a2, a2, a5 /* offset <<= stride */
PTR_ADD a2, a2, a1 /* add to address */
ld a0, 0(a2) /* load 64-bit */
ret
END(generic_bs_r_8)
#endif
/* void bs_rm_1(a0: tag, a1: addr, a2: offset, a3... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/bus_space_generic.S | BSD-2-Clause | 3a3e6e6861107fa30395b99abb65697f94ef1bf8 | github | kernel | https://github.com/NetBSD/src/blob/3a3e6e6861107fa30395b99abb65697f94ef1bf8/sys/arch/riscv/riscv/bus_space_generic.S | 81 | 140 |
NetBSD/src:sys/arch/riscv/riscv/bus_space_generic.S:4 | PTR_SLL a2, a2, a5 /* offset <<= stride */
PTR_ADD a2, a2, a1 /* add to address */
1:
lhu a0, 0(a2) /* load 16-bit */
sh a0, 0(a3) /* store 16-bit */
add a3, a3, 2
add a4, a4, -1 /* count-- */
bnez a4, 1b
ret
2:
la x0, 3f
tail _C_LABEL(panic)
3:
.asciz "_bs_rm_2: count == 0"
END(generic_bs_rm_2)
/* voi... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/bus_space_generic.S | BSD-2-Clause | 3a3e6e6861107fa30395b99abb65697f94ef1bf8 | github | kernel | https://github.com/NetBSD/src/blob/3a3e6e6861107fa30395b99abb65697f94ef1bf8/sys/arch/riscv/riscv/bus_space_generic.S | 121 | 180 |
NetBSD/src:sys/arch/riscv/riscv/bus_space_generic.S:5 | #ifdef _LP64
/* void bs_rm_8(a0: tag, a1: addr, a2: offset, a3: datap, a4: count); */
ENTRY_NP(generic_bs_rm_8)
#ifdef DIAGNOSTIC
beqz a4, 2f
#endif
PTR_L a5, BS_STRIDE(a0) /* stride */
PTR_SLL a2, a2, a5 /* offset <<= stride */
PTR_ADD a2, a2, a1 /* add to address */
1:
ld a0, 0(a2) /* load 64-bit */
sd a0, 0... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/bus_space_generic.S | BSD-2-Clause | 3a3e6e6861107fa30395b99abb65697f94ef1bf8 | github | kernel | https://github.com/NetBSD/src/blob/3a3e6e6861107fa30395b99abb65697f94ef1bf8/sys/arch/riscv/riscv/bus_space_generic.S | 161 | 220 |
NetBSD/src:sys/arch/riscv/riscv/bus_space_generic.S:6 | add a4, a4, -1 /* count-- */
bnez a4, 1b
ret
2:
la x0, 3f
tail _C_LABEL(panic)
3:
.asciz "_bs_rr_1: count == 0"
END(generic_bs_rr_1)
/* void bs_rr_2(a0: tag, a1: addr, a2: offset, a3: datap, a4: count); */
ENTRY_NP(generic_bs_rr_2)
#ifdef DIAGNOSTIC
beqz a4, 2f
#endif
PTR_L a5, BS_STRIDE(a0) /* stride */
li ... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/bus_space_generic.S | BSD-2-Clause | 3a3e6e6861107fa30395b99abb65697f94ef1bf8 | github | kernel | https://github.com/NetBSD/src/blob/3a3e6e6861107fa30395b99abb65697f94ef1bf8/sys/arch/riscv/riscv/bus_space_generic.S | 201 | 260 |
NetBSD/src:sys/arch/riscv/riscv/bus_space_generic.S:8 | PTR_SLL a2, a2, a5 /* offset <<= stride */
PTR_ADD a2, a2, a1 /* add to address */
sd a3, 0(a2) /* store 64-bit */
ret
END(generic_bs_w_8)
#endif
/* void bs_wm_1(a0: tag, a1: addr, a2: offset, a3: datap, a4: count); */
ENTRY_NP(generic_bs_wm_1)
#ifdef DIAGNOSTIC
beqz a4, 2f
#endif
PTR_L a5, BS_STRIDE(a0) /* s... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/bus_space_generic.S | BSD-2-Clause | 3a3e6e6861107fa30395b99abb65697f94ef1bf8 | github | kernel | https://github.com/NetBSD/src/blob/3a3e6e6861107fa30395b99abb65697f94ef1bf8/sys/arch/riscv/riscv/bus_space_generic.S | 281 | 340 |
NetBSD/src:sys/arch/riscv/riscv/bus_space_generic.S:9 | lhu a0, 0(a3) /* load 16-bit */
sh a0, 0(a2) /* store 16-bit */
add a3, a3, 2
add a4, a4, -1 /* count-- */
bnez a4, 1b
ret
2:
la x0, 3f
tail _C_LABEL(panic)
3:
.asciz "_bs_wm_2: count == 0"
END(generic_bs_wm_2)
/* void bs_wm_4(a0: tag, a1: addr, a2: offset, a3: datap, a4: count); */
ENTRY_NP(generic_bs_wm_... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/bus_space_generic.S | BSD-2-Clause | 3a3e6e6861107fa30395b99abb65697f94ef1bf8 | github | kernel | https://github.com/NetBSD/src/blob/3a3e6e6861107fa30395b99abb65697f94ef1bf8/sys/arch/riscv/riscv/bus_space_generic.S | 321 | 380 |
NetBSD/src:sys/arch/riscv/riscv/bus_space_generic.S:10 | #ifdef DIAGNOSTIC
beqz a4, 2f
#endif
PTR_L a5, BS_STRIDE(a0) /* stride */
PTR_SLL a2, a2, a5 /* offset <<= stride */
PTR_ADD a2, a2, a1 /* add to address */
1:
ld a0, 0(a3) /* load 64-bit */
sd a0, 0(a2) /* store 64-bit */
add a3, a3, 8
add a4, a4, -1 /* count-- */
bnez a4, 1b
ret
2:
la x0, 3f
tail _C_... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/bus_space_generic.S | BSD-2-Clause | 3a3e6e6861107fa30395b99abb65697f94ef1bf8 | github | kernel | https://github.com/NetBSD/src/blob/3a3e6e6861107fa30395b99abb65697f94ef1bf8/sys/arch/riscv/riscv/bus_space_generic.S | 361 | 385 |
NetBSD/src:sys/arch/riscv/riscv/bus_space_notimpl.S:2 | * 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/bus_space_notimpl.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/bus_space_notimpl.S | 41 | 100 |
NetBSD/src:sys/arch/riscv/riscv/bus_space_notimpl.S:3 | NOT_IMPL(bs_notimpl_bs_alloc, "alloc")
NOT_IMPL(bs_notimpl_bs_free, "free")
NOT_IMPL(bs_notimpl_bs_vaddr, "vaddr")
NOT_IMPL(bs_notimpl_bs_mmap, "mmap")
NOT_IMPL(bs_notimpl_bs_barrier, "barrier")
/* read */
NOT_IMPL(bs_notimpl_bs_r_1, "read_1")
NOT_IMPL(bs_notimpl_bs_r_2, "read_2")
NOT_IMPL(bs_notimpl_bs_r_4, "read_4")... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/bus_space_notimpl.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/bus_space_notimpl.S | 81 | 140 |
NetBSD/src:sys/arch/riscv/riscv/bus_space_notimpl.S:4 | NOT_IMPL(bs_notimpl_bs_w_8, "write_8")
/* write_multi */
NOT_IMPL(bs_notimpl_bs_wm_1, "write_multi_1")
NOT_IMPL(bs_notimpl_bs_wm_2, "write_multi_2")
NOT_IMPL(bs_notimpl_bs_wm_4, "write_multi_4")
NOT_IMPL(bs_notimpl_bs_wm_8, "write_multi_8")
/* write_region */
NOT_IMPL(bs_notimpl_bs_wr_1, "write_region_1")
NOT_IMPL(bs... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/bus_space_notimpl.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/bus_space_notimpl.S | 121 | 180 |
NetBSD/src:sys/arch/riscv/riscv/bus_space_notimpl.S:5 | NOT_IMPL(bs_notimpl_bs_w_2_s, "write_stream_2")
NOT_IMPL(bs_notimpl_bs_w_4_s, "write_stream_4")
NOT_IMPL(bs_notimpl_bs_w_8_s, "write_stream_8")
/* read_region_stream */
NOT_IMPL(bs_notimpl_bs_rr_1_s, "read_region_stream_1")
NOT_IMPL(bs_notimpl_bs_rr_2_s, "read_region_stream_2")
NOT_IMPL(bs_notimpl_bs_rr_4_s, "read_reg... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/bus_space_notimpl.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/bus_space_notimpl.S | 161 | 187 |
NetBSD/src:sys/arch/riscv/riscv/copy.S:1 | /*-
* Copyright (c) 2024 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Nick Hudson
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* ... | riscv | gas-like | macro-heavy | NetBSD/src | sys/arch/riscv/riscv/copy.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/copy.S | 1 | 60 |
NetBSD/src:sys/arch/riscv/riscv/copy.S:2 | REG_S a0, UCAS_FRAME_A0(sp)
REG_S a1, UCAS_FRAME_A1(sp)
REG_S s0, UCAS_FRAME_S0(sp)
REG_S ra, UCAS_FRAME_RA(sp)
addi s0, sp, UCAS_FRAME_SIZE
.endm
.macro exit_ucas
REG_L s0, UCAS_FRAME_S0(sp)
REG_L ra, UCAS_FRAME_RA(sp)
addi sp, sp, UCAS_FRAME_SIZE
.endm
.macro enter_cpu_onfault
// error = cpu_set_onfault(&fb... | riscv | gas-like | macro-heavy | NetBSD/src | sys/arch/riscv/riscv/copy.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/copy.S | 41 | 100 |
NetBSD/src:sys/arch/riscv/riscv/copy.S:3 | /*
* int _ucas_32(volatile uint32_t *ptr, uint32_t old,
* uint32_t new, uint32_t *ret)
*
* Implies release/acquire barriers until someone tells me
* otherwise about _ucas_32/64.
*/
ENTRY(_ucas_32)
li t0, (VM_MAXUSER_ADDRESS - 4)
bltu t0, a0, 3f
enter_ucas
enter_cpu_onfault
REG_L t0, UCAS_FRAME_A0(sp)
REG... | riscv | gas-like | macro-heavy | NetBSD/src | sys/arch/riscv/riscv/copy.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/copy.S | 81 | 140 |
NetBSD/src:sys/arch/riscv/riscv/copy.S:4 | #ifdef _LP64
/*
* int _ucas_64(volatile uint64_t *ptr, uint64_t old,
* uint64_t new, uint64_t *ret)
*
* Implies release/acquire barriers until someone tells me
* otherwise about _ucas_32/64.
*/
ENTRY(_ucas_64)
li t0, (VM_MAXUSER_ADDRESS - 8)
bltu t0, a0, 3f
enter_ucas
enter_cpu_onfault
REG_L t0, (FB_LEN +... | riscv | gas-like | macro-heavy | NetBSD/src | sys/arch/riscv/riscv/copy.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/copy.S | 121 | 160 |
NetBSD/src:sys/arch/riscv/riscv/copy.S:3 | /*
* int _ucas_32(volatile uint32_t *ptr, uint32_t old,
* uint32_t new, uint32_t *ret)
*
* Implies release/acquire barriers until someone tells me
* otherwise about _ucas_32/64.
*/
ENTRY(_ucas_32)
li t0, (VM_MAXUSER_ADDRESS - 4)
bltu t0, a0, 3f
enter_ucas
enter_cpu_onfault
REG_L t0, UCAS_FRAME_A0(sp)
REG... | riscv | gas-like | macro-heavy | NetBSD/src | sys/arch/riscv/riscv/copy.S | BSD-2-Clause | 5b566ab1538eec8c00530eb93270931537f430b0 | github | kernel | https://github.com/NetBSD/src/blob/5b566ab1538eec8c00530eb93270931537f430b0/sys/arch/riscv/riscv/copy.S | 81 | 140 |
NetBSD/src:sys/arch/riscv/riscv/copy.S:4 | /*
* int _ucas_64(volatile uint64_t *ptr, uint64_t old,
* uint64_t new, uint64_t *ret)
*
* Implies release/acquire barriers until someone tells me
* otherwise about _ucas_32/64.
*/
ENTRY(_ucas_64)
li t0, (VM_MAXUSER_ADDRESS - 8)
bltu t0, a0, 3f
enter_ucas
enter_cpu_onfault
REG_L t0, (FB_LEN + 0 * SZREG)(s... | riscv | gas-like | macro-heavy | NetBSD/src | sys/arch/riscv/riscv/copy.S | BSD-2-Clause | 5b566ab1538eec8c00530eb93270931537f430b0 | github | kernel | https://github.com/NetBSD/src/blob/5b566ab1538eec8c00530eb93270931537f430b0/sys/arch/riscv/riscv/copy.S | 121 | 158 |
NetBSD/src:sys/arch/riscv/riscv/cpu_switch.S:1 | /* $NetBSD: cpu_switch.S,v 1.8 2026/03/12 05:16:32 andvar Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Matt Thomas of 3am Software Foundry.
*
* Redistribution and use in source and binary for... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/cpu_switch.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/cpu_switch.S | 1 | 60 |
NetBSD/src:sys/arch/riscv/riscv/cpu_switch.S:2 | ENTRY_NP(cpu_switchto)
addi sp, sp, -TF_LEN // allocate trapframe
REG_S ra, TF_RA(sp) // save return address
REG_S s0, TF_S0(sp) // save callee saved address
REG_S s1, TF_S1(sp) // save callee saved address
REG_S s2, TF_S2(sp) // save callee saved address
REG_S s3, TF_S3(sp) // save callee saved address
R... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/cpu_switch.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/cpu_switch.S | 41 | 100 |
NetBSD/src:sys/arch/riscv/riscv/cpu_switch.S:3 | * order to safely block without requiring atomic r/m/w in
* mutex_exit.
*/
fence w,w
PTR_S tp, CI_CURLWP(t1) // # update curcpu with the new curlwp
fence w,r
REG_L sp, L_MD_KTF(tp) // # load its kernel stack pointer
csrw sstatus, t0 // enable interrupts
REG_L s0, TF_S0(sp) // restore callee saved
REG_L s... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/cpu_switch.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/cpu_switch.S | 81 | 140 |
NetBSD/src:sys/arch/riscv/riscv/cpu_switch.S:4 | * s1 = arg
*/
ENTRY_NP(lwp_trampoline)
call _C_LABEL(lwp_startup) // call lwp startup
// If the saved func returns, we are returning to user land.
PTR_LA ra, exception_userexit
mv a0, s2 // get saved arg
jr s1 // call saved func
END(lwp_trampoline)
ENTRY_NP(cpu_fast_switchto_cleanup)
// PTR_L t0, L_CPU(tp)... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/cpu_switch.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/cpu_switch.S | 121 | 180 |
NetBSD/src:sys/arch/riscv/riscv/cpu_switch.S:5 | REG_S s2, TF_S2(sp) // save callee saved register
REG_S s3, TF_S3(sp) // save callee saved register
REG_S s4, TF_S4(sp) // save callee saved register
REG_S s5, TF_S5(sp) // save callee saved register
REG_S s6, TF_S6(sp) // save callee saved register
REG_S s7, TF_S7(sp) // save callee saved register
REG_S s8... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/cpu_switch.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/cpu_switch.S | 161 | 220 |
NetBSD/src:sys/arch/riscv/riscv/cpu_switch.S:6 | fence w,r // for mutex_enter; see cpu_switchto
csrw sstatus, t0 // reenable interrupts
mv sp, s1 // restore stack pointer
REG_L ra, TF_RA(sp) // get return address
REG_L s0, TF_S0(sp) // restore register we used
REG_L s1, TF_S1(sp) // restore register we used
REG_L a0, (TF_LEN + CALLFRAME_S0)(sp) // Pas... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/cpu_switch.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/cpu_switch.S | 201 | 260 |
NetBSD/src:sys/arch/riscv/riscv/cpu_switch.S:7 | j .Lexception_common
//
// The exception happened while we were already in the kernel. That
// means tp already has curlwp and sp has the kernel stack pointer so
// just need to restore it and then adjust it down for space for the
// trap frame. We save t1 so we can use it to save the original sp
// into the t... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/cpu_switch.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/cpu_switch.S | 241 | 300 |
NetBSD/src:sys/arch/riscv/riscv/cpu_switch.S:8 | REG_S s1, TF_S1(sp) // save s1
REG_S s2, TF_S2(sp) // save s2
REG_S s3, TF_S3(sp) // save s3
REG_S s4, TF_S4(sp) // save s4
REG_S s5, TF_S5(sp) // save s5
REG_S s6, TF_S6(sp) // save s6
REG_S s7, TF_S7(sp) // save s7
REG_S s8, TF_S8(sp) // save s8
REG_S s9, TF_S9(sp) // save s9
REG_S s10, TF_S10(sp) ... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/cpu_switch.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/cpu_switch.S | 281 | 340 |
NetBSD/src:sys/arch/riscv/riscv/cpu_switch.S:9 | call _C_LABEL(cpu_trap) // just call trap to handle it
ALTENTRY(exception_kernexit)
// If we got here, we are returning from a kernel exception (either a
// trap or interrupt). Simply return the volatile registers and the
// exception PC and status, load the saved SP from the trapframe, and
// return from the exc... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/cpu_switch.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/cpu_switch.S | 321 | 380 |
NetBSD/src:sys/arch/riscv/riscv/cpu_switch.S:10 | csrw sepc, t0 // restore exception PC
REG_L t0, TF_T0(sp) // restore t0
REG_L t1, TF_T1(sp) // restore t1
REG_L sp, TF_SP(sp) // restore SP
sret // and we're done
trap_user:
#if 0
/* Already saved */
REG_S s0, TF_S0(sp) // only save from userland
REG_S s1, TF_S1(sp) // only save from userland
REG_S s... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/cpu_switch.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/cpu_switch.S | 361 | 420 |
NetBSD/src:sys/arch/riscv/riscv/cpu_switch.S:11 | REG_L s0, TF_S0(sp) // only restore from userland
REG_L s1, TF_S1(sp) // only restore from userland
REG_L s2, TF_S2(sp) // only restore from userland
REG_L s3, TF_S3(sp) // only restore from userland
REG_L s4, TF_S4(sp) // only restore from userland
REG_L s5, TF_S5(sp) // only restore from userland
REG_L s6... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/cpu_switch.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/cpu_switch.S | 401 | 460 |
NetBSD/src:sys/arch/riscv/riscv/cpu_switch.S:12 | trap_doast:
INT_S zero, L_MD_ASTPENDING(tp)
csrsi sstatus, SR_SIE // reenable interrupts
mv a0, sp // only argument is trapframe
// ra is still exception_userexit ?
tail _C_LABEL(cpu_ast)
/*
*/
intr_handler:
beqz t1, intr_user
PTR_LA ra, exception_kernexit
tail _C_LABEL(cpu_intr)
END(cpu_exception_handle... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/cpu_switch.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/cpu_switch.S | 441 | 500 |
NetBSD/src:sys/arch/riscv/riscv/cpu_switch.S:13 | ret
END(cpu_set_onfault)
ENTRY_NP(setjmp)
REG_S ra, FB_RA(a0)
REG_S s0, FB_S0(a0)
REG_S s1, FB_S1(a0)
REG_S s2, FB_S2(a0)
REG_S s3, FB_S3(a0)
REG_S s4, FB_S4(a0)
REG_S s5, FB_S5(a0)
REG_S s6, FB_S6(a0)
REG_S s7, FB_S7(a0)
REG_S s8, FB_S8(a0)
REG_S s9, FB_S9(a0)
REG_S s10, FB_S10(a0)
REG_S s11, FB_S11(a0)... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/cpu_switch.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/cpu_switch.S | 481 | 522 |
NetBSD/src:sys/arch/riscv/riscv/cpu_switch.S:1 | /* $NetBSD: cpu_switch.S,v 1.7 2025/04/20 07:47:26 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Matt Thomas of 3am Software Foundry.
*
* Redistribution and use in source and binary form... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/cpu_switch.S | BSD-2-Clause | 7cdf4fc94439b8b590a82b99e363ab2fa389517b | github | kernel | https://github.com/NetBSD/src/blob/7cdf4fc94439b8b590a82b99e363ab2fa389517b/sys/arch/riscv/riscv/cpu_switch.S | 1 | 60 |
NetBSD/src:sys/arch/riscv/riscv/cpu_switch.S:8 | REG_S s1, TF_S1(sp) // save s1
REG_S s2, TF_S2(sp) // save s2
REG_S s3, TF_S3(sp) // save s3
REG_S s4, TF_S4(sp) // save s4
REG_S s5, TF_S5(sp) // save s5
REG_S s6, TF_S6(sp) // save s6
REG_S s7, TF_S7(sp) // save s7
REG_S s8, TF_S8(sp) // save s8
REG_S s9, TF_S9(sp) // save s9
REG_S s10, TF_S10(sp) ... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/cpu_switch.S | BSD-2-Clause | 7cdf4fc94439b8b590a82b99e363ab2fa389517b | github | kernel | https://github.com/NetBSD/src/blob/7cdf4fc94439b8b590a82b99e363ab2fa389517b/sys/arch/riscv/riscv/cpu_switch.S | 281 | 340 |
NetBSD/src:sys/arch/riscv/riscv/cpu_switch.S:1 | /* $NetBSD: cpu_switch.S,v 1.6 2024/05/02 18:18:17 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Matt Thomas of 3am Software Foundry.
*
* Redistribution and use in source and binary form... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/cpu_switch.S | BSD-2-Clause | d3587104cec07f7a43748a2ae69bd311aa490f4b | github | kernel | https://github.com/NetBSD/src/blob/d3587104cec07f7a43748a2ae69bd311aa490f4b/sys/arch/riscv/riscv/cpu_switch.S | 1 | 60 |
NetBSD/src:sys/arch/riscv/riscv/cpu_switch.S:13 | ret
END(cpu_set_onfault)
ENTRY_NP(setjmp)
REG_S ra, FB_RA(a0)
REG_S s0, FB_S0(a0)
REG_S s1, FB_S1(a0)
REG_S s2, FB_S2(a0)
REG_S s3, FB_S3(a0)
REG_S s4, FB_S4(a0)
REG_S s5, FB_S5(a0)
REG_S s6, FB_S6(a0)
REG_S s7, FB_S7(a0)
REG_S s8, FB_S8(a0)
REG_S s9, FB_S9(a0)
REG_S s10, FB_S10(a0)
REG_S s11, FB_S11(a0)... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/cpu_switch.S | BSD-2-Clause | d3587104cec07f7a43748a2ae69bd311aa490f4b | github | kernel | https://github.com/NetBSD/src/blob/d3587104cec07f7a43748a2ae69bd311aa490f4b/sys/arch/riscv/riscv/cpu_switch.S | 481 | 522 |
NetBSD/src:sys/arch/riscv/riscv/cpu_switch.S:1 | /* $NetBSD: cpu_switch.S,v 1.5 2023/05/07 12:41:48 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Matt Thomas of 3am Software Foundry.
*
* Redistribution and use in source and binary form... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/cpu_switch.S | BSD-2-Clause | 3a3e6e6861107fa30395b99abb65697f94ef1bf8 | github | kernel | https://github.com/NetBSD/src/blob/3a3e6e6861107fa30395b99abb65697f94ef1bf8/sys/arch/riscv/riscv/cpu_switch.S | 1 | 60 |
NetBSD/src:sys/arch/riscv/riscv/cpu_switch.S:12 | trap_doast:
INT_S zero, L_MD_ASTPENDING(tp)
csrsi sstatus, SR_SIE // reenable interrupts
mv a0, sp // only argument is trapframe
// ra is still exception_userexit ?
tail _C_LABEL(cpu_ast)
/*
*/
intr_handler:
beqz t1, intr_user
PTR_LA ra, exception_kernexit
tail _C_LABEL(cpu_intr)
END(cpu_exception_handle... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/cpu_switch.S | BSD-2-Clause | 3a3e6e6861107fa30395b99abb65697f94ef1bf8 | github | kernel | https://github.com/NetBSD/src/blob/3a3e6e6861107fa30395b99abb65697f94ef1bf8/sys/arch/riscv/riscv/cpu_switch.S | 441 | 500 |
NetBSD/src:sys/arch/riscv/riscv/cpu_switch.S:13 | li a0, 0
ret
END(cpu_set_onfault)
ENTRY_NP(setjmp)
REG_S ra, FB_RA(a0)
REG_S s0, FB_S0(a0)
REG_S s1, FB_S1(a0)
REG_S s2, FB_S2(a0)
REG_S s3, FB_S3(a0)
REG_S s4, FB_S4(a0)
REG_S s5, FB_S5(a0)
REG_S s6, FB_S6(a0)
REG_S s7, FB_S7(a0)
REG_S s8, FB_S8(a0)
REG_S s9, FB_S9(a0)
REG_S s10, FB_S10(a0)
REG_S s11, ... | riscv | gas-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/cpu_switch.S | BSD-2-Clause | 3a3e6e6861107fa30395b99abb65697f94ef1bf8 | github | kernel | https://github.com/NetBSD/src/blob/3a3e6e6861107fa30395b99abb65697f94ef1bf8/sys/arch/riscv/riscv/cpu_switch.S | 481 | 523 |
NetBSD/src:sys/arch/riscv/riscv/locore.S:2 | #define PRINTS(string) \
call locore_prints ; \
.asciz string ; \
.align 3 ; \
#if defined(VERBOSE_INIT_RISCV)
#define VPRINTS(string) \
call locore_prints ; \
.asciz string ; \
.align 3 ; \
#define VPRINTX(regno) \
mv a0, regno ; \
call locore_printx
#define VPRINTXNL(regno) \
mv a0, regno ; \
ca... | riscv | intel-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/locore.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/locore.S | 41 | 100 |
NetBSD/src:sys/arch/riscv/riscv/locore.S:3 | ENTRY_NP(start)
csrw sie, zero // disable interrupts
csrw sip, zero // clear any pending
li s0, SR_FS
csrc sstatus, s0 // disable FP
mv s10, a0 // copy hartid
mv s11, a1 // copy dtb PA
/* set the stack pointer for boot */
PTR_LA t0, _C_LABEL(bootstk)
mv sp, t0
VPRINTS("\n------------\nNetBSD start\... | riscv | intel-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/locore.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/locore.S | 81 | 140 |
NetBSD/src:sys/arch/riscv/riscv/locore.S:4 | /*
* Before we construct the initial MMU tables, we need to know
* if there are any extra PTE bits that we need to include.
* (Grumble, mumble, T-Head XMAE).
*
* We'll push space for 2 PTE prototypes, and fill them with
* zeros for now. sp[0] is for "regular memory", sp[1] is
* for "devices".
*/
addi ... | riscv | intel-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/locore.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/locore.S | 121 | 180 |
NetBSD/src:sys/arch/riscv/riscv/locore.S:5 | * Our load address is not fixed, but our VA is. We need to construct
* an initial PDETAB.
*
* The space for the initial page table is included in the kernel
* .bss size calculation so we know the space exists.
*/
li a1, 0
PTR_LA s2, _C_LABEL(l1_pte)
mv s4, s2 // last page table
#ifdef _LP64
PTR_LA s3,... | riscv | intel-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/locore.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/locore.S | 161 | 220 |
NetBSD/src:sys/arch/riscv/riscv/locore.S:6 | VPRINTS("\n\r")
VPRINTS("bss: ")
PTR_LA a0, _C_LABEL(__bss_start)
VPRINTX(a0)
VPRINTS(" - ")
VPRINTXNL(s7)
VPRINTS("\n\r")
// a0 start of memory to clear
// a1 end of memory to clear
PTR_LA a0, _C_LABEL(__bss_start)
mv a1, s7
call clear_bss // zero through kernel_end (inc. stack)
li s7, PTE_V // ... | riscv | intel-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/locore.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/locore.S | 201 | 260 |
NetBSD/src:sys/arch/riscv/riscv/locore.S:7 | VPRINTX(s3)
#endif
VPRINTS(": ")
VPRINTXNL(t0)
VPRINTS("\n\r")
#endif // _LP64
// kernel VA
li t1, ((VM_MIN_KERNEL_ADDRESS >> SEGSHIFT) & (NPDEPG - 1)) * SZREG
add s9, s2, t1
#if PGSHIFT < PTE_PPN_SHIFT
#error Code assumes PGSHIFT is greater than PTE_PPN_SHIFT
#endif
li s5, (VM_KERNEL_SIZE >> SEGSHIFT) //... | riscv | intel-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/locore.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/locore.S | 241 | 300 |
NetBSD/src:sys/arch/riscv/riscv/locore.S:8 | // DTB VA
li t1, ((VM_KERNEL_DTB_BASE >> SEGSHIFT) & (NPDEPG - 1)) * SZREG
add s9, s2, t1
li s7, PTE_KERN | PTE_HARDWIRED | PTE_R | PTE_W
REG_L a0, 0(sp)
or s7, s7, a0
//
// Fill in the PDE for the DTB. Only do one - if any more are required
// they will be mapped in later.
//
mv s0, s11
srli s0, s0, SEGS... | riscv | intel-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/locore.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/locore.S | 281 | 340 |
NetBSD/src:sys/arch/riscv/riscv/locore.S:9 | VPRINTX(s9)
VPRINTS(": ")
VPRINTXNL(s0)
REG_S s0, 0(s9)
#endif
/* Pop the PTE prototypes pushed way up above. */
addi sp, sp, (2 * SZREG)
li a0, 'P'
call _C_LABEL(uartputc)
/* Set supervisor trap vector base register */
PTR_LA t0, vstart
add t0, t0, s8
csrw stvec, t0
/* Set supervisor address translat... | riscv | intel-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/locore.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/locore.S | 321 | 380 |
NetBSD/src:sys/arch/riscv/riscv/locore.S:10 | li a0, '\n'
call _C_LABEL(uartputc) // uartputs doesn't use stack
li a0, '\r'
call _C_LABEL(uartputc) // uartputs doesn't use stack
PTR_LA tp, _C_LABEL(lwp0) // put curlwp in tp
/* Set supervisor trap vector base register */
PTR_LA a0, _C_LABEL(cpu_exception_handler)
csrw stvec, a0
PTR_LA t0, bootstk // top... | riscv | intel-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/locore.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/locore.S | 361 | 420 |
NetBSD/src:sys/arch/riscv/riscv/locore.S:11 | and t1, s11, t1
or t0, t0, t1
/* Set the global pointer */
.option push
.option norelax
lla gp, __global_pointer$
.option pop
// Now we should ready to start initializing the kernel.
mv a0, s10 // hartid
mv a1, s11 // dtb (physical)
li s0, 0 // zero frame pointer
call _C_LABEL(init_riscv) // do MD s... | riscv | intel-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/locore.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/locore.S | 401 | 460 |
NetBSD/src:sys/arch/riscv/riscv/locore.S:12 | /*
* Calculate the difference between the VA and PA for start and
* keep in s8.
*/
PTR_LA t0, start
PTR_L s8, .Lstart
sub s8, s8, t0
#ifdef _LP64
PTR_LA s4, _C_LABEL(l2_pte)
#else
PTR_LA s4, _C_LABEL(l1_pte)
#endif
// s4 is satp address....
// s8 is kern_vtopdiff
//
/* Set supervisor trap vector base... | riscv | intel-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/locore.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/locore.S | 441 | 500 |
NetBSD/src:sys/arch/riscv/riscv/locore.S:13 | /* Set the global pointer */
.option push
.option norelax
lla gp, __global_pointer$
.option pop
/* Set SP to VA */
add sp, sp, s8
/* Set supervisor trap vector base register with ipi_handler */
PTR_LA a0, _C_LABEL(ipi_handler)
csrw stvec, a0
csrsi sie, SIE_SSIE
csrsi sstatus, SR_SIE // enable interrupts
... | riscv | intel-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/locore.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/locore.S | 481 | 540 |
NetBSD/src:sys/arch/riscv/riscv/locore.S:14 | /* Set supervisor trap vector base register */
PTR_LA a0, _C_LABEL(cpu_exception_handler)
csrw stvec, a0
li t0, CI_SIZE
mul t0, s11, t0
PTR_LA t1, _C_LABEL(cpu_info_store)
add a0, t0, t1 /* a0 = &cpu_info_store[cpuindex] */
/*
* set curlwp (tp and curcpu()->ci_curlwp) now we know the
* idle lwp from curcp... | riscv | intel-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/locore.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/locore.S | 521 | 580 |
NetBSD/src:sys/arch/riscv/riscv/locore.S:15 | * A very basic exception handler to just return when an IPI comes in during
* AP bringup.
*
* The handler address needs to have bottom two bits as zero.
*/
.align 2
ipi_handler:
csrrw tp, sscratch, tp // swap scratch and thread pointer
bnez tp, 1f // tp != 0, something went wrong.
csrr tp, scause // get ... | riscv | intel-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/locore.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/locore.S | 561 | 620 |
NetBSD/src:sys/arch/riscv/riscv/locore.S:16 | .quad CONSADDR
#else
.word CONSADDR
#endif
#endif
ENTRY_NP(uartputc)
#ifdef EARLYCONS
tail ___CONCAT(EARLYCONS, _platform_early_putchar)
#else
#define SBI_LEGACY_CONSOLE_PUTCHAR 1
li a7, SBI_LEGACY_CONSOLE_PUTCHAR
ecall
ret
#endif
END(uartputc)
ENTRY_NP(uartgetc)
#ifdef EARLYCONS
li a0, -1
#else
#define SBI_L... | riscv | intel-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/locore.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/locore.S | 601 | 660 |
NetBSD/src:sys/arch/riscv/riscv/locore.S:17 | .globl _C_LABEL(cpu_Debugger_insn)
.globl _C_LABEL(cpu_Debugger_ret)
ENTRY_NP(cpu_Debugger)
cpu_Debugger_insn:
ebreak
cpu_Debugger_ret:
ret
END(cpu_Debugger)
ENTRY_NP(locore_prints)
addi sp, sp, -(SZREG * 2)
REG_S s0, (0 * SZREG)(sp)
mv s0, ra
1:
lbu a0, 0(s0)
beqz a0, 2f
call uartputc
addi s0, s0, 1
j... | riscv | intel-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/locore.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/locore.S | 641 | 700 |
NetBSD/src:sys/arch/riscv/riscv/locore.S:18 | REG_S ra, (3 * SZREG)(sp)
mv s1, a0 // our print value
li s2, 10
li a0, '0'
call uartputc
li a0, 'x'
call uartputc
// Word size in bits
li s0, (SZREG * 8)
1:
addi s0, s0, -4 // nibble shift
srl a0, s1, s0 // extract ...
andi a0, a0, 0xf
bltu a0, s2, 2f
addi a0, a0, ('a' - '0' - 10)
2: addi a0, a0, '0... | riscv | intel-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/locore.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/locore.S | 681 | 740 |
NetBSD/src:sys/arch/riscv/riscv/locore.S:19 | ret
END(locore_printx)
ENTRY_NP(locore_printxnl)
addi sp, sp, -(SZREG * 2)
REG_S ra, (1 * SZREG)(sp)
call locore_printx
li a0, '\n'
call uartputc
li a0, '\r'
call uartputc
REG_L ra, (1 * SZREG)(sp)
addi sp, sp, (SZREG * 2)
ret
END(locore_printxnl)
#endif /* VERBOSE_INIT_RISCV */
.data
.align 2
hart_... | riscv | intel-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/locore.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/locore.S | 721 | 778 |
NetBSD/src:sys/arch/riscv/riscv/locore.S:20 | #ifdef MULTIPROCESSOR
.space BOOT_AP_STACKSIZE * (MAXCPUS - 1)
#endif
// .section "_init_memory", "aw", %nobits
.align PGSHIFT
mmutables_start:
bootstrap_pde:
.global _C_LABEL(bootstrap_pde)
#ifdef _LP64
.global _C_LABEL(l2_pte)
l2_pte:
.space PAGE_SIZE
#endif
.global _C_LABEL(l1_pte)
l1_pte:
.space PAGE_SIZE
m... | riscv | intel-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/locore.S | BSD-2-Clause | 3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd | github | kernel | https://github.com/NetBSD/src/blob/3f1390c8cc18c3f67a4bd2632f8c7ad919cf86fd/sys/arch/riscv/riscv/locore.S | 761 | 778 |
NetBSD/src:sys/arch/riscv/riscv/locore.S:3 | ENTRY_NP(start)
csrw sie, zero // disable interrupts
csrw sip, zero // clear any pending
li s0, SR_FS
csrc sstatus, s0 // disable FP
mv s10, a0 // copy hartid
mv s11, a1 // copy dtb PA
/* set the stack pointer for boot */
PTR_LA t0, _C_LABEL(bootstk)
mv sp, t0
VPRINTS("\n------------\nNetBSD start\... | riscv | intel-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/locore.S | BSD-2-Clause | a7890ee99c2af93c8dd8db94e412051a296c1e74 | github | kernel | https://github.com/NetBSD/src/blob/a7890ee99c2af93c8dd8db94e412051a296c1e74/sys/arch/riscv/riscv/locore.S | 81 | 140 |
NetBSD/src:sys/arch/riscv/riscv/locore.S:4 | /*
* Our load address is not fixed, but our VA is. We need to construct
* an initial PDETAB.
*
* The space for the initial page table is included in the kernel
* .bss size calculation so we know the space exists.
*/
li a1, 0
PTR_LA s2, _C_LABEL(l1_pte)
mv s4, s2 // last page table
#ifdef _LP64
PTR_L... | riscv | intel-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/locore.S | BSD-2-Clause | a7890ee99c2af93c8dd8db94e412051a296c1e74 | github | kernel | https://github.com/NetBSD/src/blob/a7890ee99c2af93c8dd8db94e412051a296c1e74/sys/arch/riscv/riscv/locore.S | 121 | 180 |
NetBSD/src:sys/arch/riscv/riscv/locore.S:5 | VPRINTXNL(s8)
VPRINTS("\n\r")
VPRINTS("bss: ")
PTR_LA a0, _C_LABEL(__bss_start)
VPRINTX(a0)
VPRINTS(" - ")
VPRINTXNL(s7)
VPRINTS("\n\r")
// a0 start of memory to clear
// a1 end of memory to clear
PTR_LA a0, _C_LABEL(__bss_start)
mv a1, s7
call clear_bss // zero through kernel_end (inc. stack)
l... | riscv | intel-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/locore.S | BSD-2-Clause | a7890ee99c2af93c8dd8db94e412051a296c1e74 | github | kernel | https://github.com/NetBSD/src/blob/a7890ee99c2af93c8dd8db94e412051a296c1e74/sys/arch/riscv/riscv/locore.S | 161 | 220 |
NetBSD/src:sys/arch/riscv/riscv/locore.S:6 | VPRINTX(s3)
#endif
VPRINTS(": ")
VPRINTXNL(t0)
VPRINTS("\n\r")
#endif // _LP64
// kernel VA
li t1, ((VM_MIN_KERNEL_ADDRESS >> SEGSHIFT) & (NPDEPG - 1)) * SZREG
add s9, s2, t1
#if PGSHIFT < PTE_PPN_SHIFT
#error Code assumes PGSHIFT is greater than PTE_PPN_SHIFT
#endif
li s5, (VM_KERNEL_SIZE >> SEGSHIFT) //... | riscv | intel-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/locore.S | BSD-2-Clause | a7890ee99c2af93c8dd8db94e412051a296c1e74 | github | kernel | https://github.com/NetBSD/src/blob/a7890ee99c2af93c8dd8db94e412051a296c1e74/sys/arch/riscv/riscv/locore.S | 201 | 260 |
NetBSD/src:sys/arch/riscv/riscv/locore.S:7 | // DTB VA
li t1, ((VM_KERNEL_DTB_BASE >> SEGSHIFT) & (NPDEPG - 1)) * SZREG
add s9, s2, t1
li s7, PTE_KERN | PTE_HARDWIRED | PTE_R | PTE_W
//
// Fill in the PDE for the DTB. Only do one - if any more are required
// they will be mapped in later.
//
mv s0, s11
srli s0, s0, SEGSHIFT // round down to NBSEG, and... | riscv | intel-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/locore.S | BSD-2-Clause | a7890ee99c2af93c8dd8db94e412051a296c1e74 | github | kernel | https://github.com/NetBSD/src/blob/a7890ee99c2af93c8dd8db94e412051a296c1e74/sys/arch/riscv/riscv/locore.S | 241 | 300 |
NetBSD/src:sys/arch/riscv/riscv/locore.S:8 | li a0, 'P'
call _C_LABEL(uartputc)
/* Set supervisor trap vector base register */
PTR_LA t0, vstart
add t0, t0, s8
csrw stvec, t0
/* Set supervisor address translation and protection register */
srli t1, s4, PGSHIFT
#ifdef _LP64
li t0, SATP_MODE_SV39
#else
li t0, SATP_MODE_SV32
#endif
or t0, t0, t1
sfence.... | riscv | intel-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/locore.S | BSD-2-Clause | a7890ee99c2af93c8dd8db94e412051a296c1e74 | github | kernel | https://github.com/NetBSD/src/blob/a7890ee99c2af93c8dd8db94e412051a296c1e74/sys/arch/riscv/riscv/locore.S | 281 | 340 |
NetBSD/src:sys/arch/riscv/riscv/locore.S:9 | csrw stvec, a0
PTR_LA t0, bootstk // top of lwp0uspace
PTR_S t0, L_PCB(tp) // set uarea of lwp (already zeroed)
addi sp, t0, -TF_LEN // switch to new stack
PTR_S sp, L_MD_UTF(tp) // store pointer to empty trapframe
PTR_LA t1, _C_LABEL(kernel_pmap_store)
add t2, s4, s8 // PA -> VA
srli t3, s4, PGSHIFT
PTR... | riscv | intel-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/locore.S | BSD-2-Clause | a7890ee99c2af93c8dd8db94e412051a296c1e74 | github | kernel | https://github.com/NetBSD/src/blob/a7890ee99c2af93c8dd8db94e412051a296c1e74/sys/arch/riscv/riscv/locore.S | 321 | 380 |
NetBSD/src:sys/arch/riscv/riscv/locore.S:10 | // Now we should ready to start initializing the kernel.
mv a0, s10 // hartid
mv a1, s11 // dtb (physical)
li s0, 0 // zero frame pointer
call _C_LABEL(init_riscv) // do MD startup
tail _C_LABEL(main) // and transfer to main
/* No return from main */
END(start)
#if defined(MULTIPROCESSOR)
// a0 is hart... | riscv | intel-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/locore.S | BSD-2-Clause | a7890ee99c2af93c8dd8db94e412051a296c1e74 | github | kernel | https://github.com/NetBSD/src/blob/a7890ee99c2af93c8dd8db94e412051a296c1e74/sys/arch/riscv/riscv/locore.S | 361 | 420 |
NetBSD/src:sys/arch/riscv/riscv/locore.S:11 | #ifdef _LP64
PTR_LA s4, _C_LABEL(l2_pte)
#else
PTR_LA s4, _C_LABEL(l1_pte)
#endif
// s4 is satp address....
// s8 is kern_vtopdiff
//
/* Set supervisor trap vector base register */
PTR_LA t0, vmpstart
add t0, t0, s8
csrw stvec, t0
/* Set supervisor address translation and protection register */
srli t1, s... | riscv | intel-like | handwritten | NetBSD/src | sys/arch/riscv/riscv/locore.S | BSD-2-Clause | a7890ee99c2af93c8dd8db94e412051a296c1e74 | github | kernel | https://github.com/NetBSD/src/blob/a7890ee99c2af93c8dd8db94e412051a296c1e74/sys/arch/riscv/riscv/locore.S | 401 | 460 |
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