id stringlengths 22 129 | text stringlengths 60 19.5k | arch stringclasses 9
values | syntax stringclasses 5
values | kind stringclasses 4
values | repo stringclasses 32
values | path stringlengths 7 108 | license stringclasses 10
values | commit stringlengths 40 40 | source_host stringclasses 1
value | category stringclasses 15
values | source_url stringlengths 85 192 | line_start int64 1 5.48k | line_end int64 4 5.5k |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:19 | fnma.s1 FR_E4 = FR_B,FR_Y2,f1 // e4 = 1-b*y2
nop.i 0
}
{ .mfi
nop.m 0
fma.s1 FR_X = FR_R0,FR_Y2,FR_Q0 // x = q+r*y2
nop.i 0
};;
{ .mfi
nop.m 0
fma.s1 FR_Z = FR_X,f1,f1 // x+1
nop.i 0
};;
{ .mfi
nop.m 0
(... | arm64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_atanhl.S | LGPL-2.1 | 3a327316ad615f7e4264d3e13d23052d9dc84694 | github | libc | https://github.com/bminor/glibc/blob/3a327316ad615f7e4264d3e13d23052d9dc84694/sysdeps/ia64/fpu/e_atanhl.S | 721 | 780 |
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:20 | { .mfi
add GR_ad_tbl_3 = 0x280,GR_ad_z_1 // point to Constants_G_H_h3
nop.f 0
nop.i 0
};;
{ .mfi
shladd GR_ad_z_1 = GR_Index1,2,GR_ad_z_1 // point to Z_1
nop.f 0
extr.u GR_X_0 = GR_signif,49,15 // get high 15 bits of significand
};;
{ .... | arm64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_atanhl.S | LGPL-2.1 | 3a327316ad615f7e4264d3e13d23052d9dc84694 | github | libc | https://github.com/bminor/glibc/blob/3a327316ad615f7e4264d3e13d23052d9dc84694/sysdeps/ia64/fpu/e_atanhl.S | 761 | 820 |
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:21 | //
// For performance,don't use result of pmpyshr2.u for 4 cycles.
//
{ .mfi
ldfe FR_log2_lo = [GR_ad_q],16 // load log2_lo
nop.f 0
sub GR_N = GR_N,GR_Bias
};;
{ .mfi
ldfe FR_Q4 = [GR_ad_q],16 // load Q4
fms.s1 FR_S_lo = FR_AA,f1,FR_Z // form ... | arm64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_atanhl.S | LGPL-2.1 | 3a327316ad615f7e4264d3e13d23052d9dc84694 | github | libc | https://github.com/bminor/glibc/blob/3a327316ad615f7e4264d3e13d23052d9dc84694/sysdeps/ia64/fpu/e_atanhl.S | 801 | 860 |
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:22 | ldfd FR_h2 = [GR_ad_tbl_2] // load h_2
fma.s1 FR_S_lo = FR_S_lo,f1,FR_BB // S_lo = S_lo + BB
nop.i 0
}
{ .mfi
setf.exp FR_2_to_minus_N = GR_minus_N // form 2^(-N)
fma.s1 FR_X_lo = FR_R1,FR_Y3,f0 // x_lo = r1*y3
nop.i 0
};;
{ .mfi
nop.m ... | arm64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_atanhl.S | LGPL-2.1 | 3a327316ad615f7e4264d3e13d23052d9dc84694 | github | libc | https://github.com/bminor/glibc/blob/3a327316ad615f7e4264d3e13d23052d9dc84694/sysdeps/ia64/fpu/e_atanhl.S | 841 | 900 |
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:23 | //
{ .mfi
nop.m 0
nop.f 0
extr.u GR_Index3 = GR_X_2,1,5 // extract bits 1-5 of X_2
}
{ .mfi
nop.m 0
fma.s1 FR_S_lo = FR_S_lo,f1,FR_X_lo // S_lo = S_lo + Arg_lo
nop.i 0
};;
{ .mfi
shladd GR_ad_tbl_3 = GR_Index3,4,GR_ad_tbl_3 ... | arm64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_atanhl.S | LGPL-2.1 | 3a327316ad615f7e4264d3e13d23052d9dc84694 | github | libc | https://github.com/bminor/glibc/blob/3a327316ad615f7e4264d3e13d23052d9dc84694/sysdeps/ia64/fpu/e_atanhl.S | 881 | 940 |
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:24 | nop.i 0
};;
{ .mfi
nop.m 0
// S_lo = S_lo * 2^(-N)
fma.s1 FR_S_lo = FR_S_lo,FR_2_to_minus_N,f0
nop.i 0
};;
{ .mfi
nop.m 0
fmpy.s1 FR_G = FR_G,FR_G3 // G = (G_1 * G_2) * G_3
nop.i 0
}
{ .mfi
nop.m 0
fadd.s1... | arm64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_atanhl.S | LGPL-2.1 | 3a327316ad615f7e4264d3e13d23052d9dc84694 | github | libc | https://github.com/bminor/glibc/blob/3a327316ad615f7e4264d3e13d23052d9dc84694/sysdeps/ia64/fpu/e_atanhl.S | 921 | 980 |
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:25 | nop.m 0
fma.s1 FR_r = FR_G,FR_S_lo,FR_r // r = G * S_lo + (G * S_hi - 1)
nop.i 0
};;
{ .mfi
nop.m 0
fma.s1 FR_poly_lo = FR_r,FR_Q4,FR_Q3 // poly_lo = r * Q4 + Q3
nop.i 0
}
{ .mfi
nop.m 0
fmpy.s1 FR_rsq = FR_r,FR_r // r... | arm64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_atanhl.S | LGPL-2.1 | 3a327316ad615f7e4264d3e13d23052d9dc84694 | github | libc | https://github.com/bminor/glibc/blob/3a327316ad615f7e4264d3e13d23052d9dc84694/sysdeps/ia64/fpu/e_atanhl.S | 961 | 1,020 |
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:26 | nop.i 0
};;
{ .mfi
nop.m 0
// Y_lo = poly_hi + poly_lo/2
fma.s0 FR_Y_lo = FR_poly_lo,FR_Half,FR_poly_hi
nop.i 0
};;
{ .mfb
nop.m 0
// Result = arctanh(x) = Y_hi/2 + Y_lo
fma.s0 f8 = FR_Y_hi,FR_Half,FR_Y_lo
br.ret.sptk b0
};;
... | arm64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_atanhl.S | LGPL-2.1 | 3a327316ad615f7e4264d3e13d23052d9dc84694 | github | libc | https://github.com/bminor/glibc/blob/3a327316ad615f7e4264d3e13d23052d9dc84694/sysdeps/ia64/fpu/e_atanhl.S | 1,001 | 1,060 |
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:27 | nop.i 0
}
{ .mfi
nop.m 0
fma.s1 FR_C5 = FR_C5,FR_x2,FR_C3
nop.i 0
};;
{ .mfi
nop.m 0
fma.s1 FR_x8 = FR_x4,FR_x4,f0
nop.i 0
};;
{ .mfi
nop.m 0
fma.s1 FR_C17 = FR_C17,FR_x4,FR_C13
nop.i 0
};;... | arm64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_atanhl.S | LGPL-2.1 | 3a327316ad615f7e4264d3e13d23052d9dc84694 | github | libc | https://github.com/bminor/glibc/blob/3a327316ad615f7e4264d3e13d23052d9dc84694/sysdeps/ia64/fpu/e_atanhl.S | 1,041 | 1,100 |
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:28 | nop.m 0
fmerge.s FR_Arg_X = f8, f8
nop.i 0
};;
{ .mfb
mov GR_Parameter_TAG = 130
fmerge.s FR_RESULT = f8,FR_Rcp // result is +-inf
br.cond.sptk __libm_error_region // exit if |x| = 1.0
};;
atanhl_gt_one:
{ .mfi
nop.m 0
fmerge.s ... | arm64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_atanhl.S | LGPL-2.1 | 3a327316ad615f7e4264d3e13d23052d9dc84694 | github | libc | https://github.com/bminor/glibc/blob/3a327316ad615f7e4264d3e13d23052d9dc84694/sysdeps/ia64/fpu/e_atanhl.S | 1,081 | 1,140 |
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:29 | stfe [GR_Parameter_Y] = FR_Arg_Y,16 // Save Parameter 2 on stack
add GR_Parameter_X = 16,sp // Parameter 1 address
.save b0,GR_SAVE_B0
mov GR_SAVE_B0=b0 // Save b0
};;
.body
{ .mib
stfe [GR_Parameter_X] = FR_Arg_X // Store Parameter 1 on stack
... | arm64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_atanhl.S | LGPL-2.1 | 3a327316ad615f7e4264d3e13d23052d9dc84694 | github | libc | https://github.com/bminor/glibc/blob/3a327316ad615f7e4264d3e13d23052d9dc84694/sysdeps/ia64/fpu/e_atanhl.S | 1,121 | 1,157 |
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:28 | nop.m 0
fmerge.s FR_Arg_X = f8, f8
nop.i 0
};;
{ .mfb
mov GR_Parameter_TAG = 130
fmerge.s FR_RESULT = f8,FR_Rcp // result is +-inf
br.cond.sptk __libm_error_region // exit if |x| = 1.0
};;
atanhl_gt_one:
{ .mfi
nop.m 0
fmerge.s ... | arm64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_atanhl.S | LGPL-2.1 | 890b7a4b33d482b5c768ab47d70758b80227e9bc | github | libc | https://github.com/bminor/glibc/blob/890b7a4b33d482b5c768ab47d70758b80227e9bc/sysdeps/ia64/fpu/e_atanhl.S | 1,081 | 1,140 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:3 | // Get 2^(index_2/8) from table_2;
// Calculate exp(r) by 5th order polynomial
// r = x - n (log2/128)_high
// delta = - n (log2/128)_low
// Calculate exp(delta) as 1 + delta
// Special values
//==============================================================
// cosh(+0) = 1.0
/... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_cosh.S | 81 | 140 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:4 | //==============================================================
rRshf = r14
rN_neg = r14
rAD_TB1 = r15
rAD_TB2 = r16
rAD_P = r17
rN = r18
rIndex_1 = r19
rIndex_2_16 = r20
rM = r21
rB... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_cosh.S | 121 | 180 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:5 | FR_X = f10
FR_Y = f1
FR_RESULT = f8
fRSHF_2TO56 = f6
fINV_LN2_2TO63 = f7
fW_2TO56_RSH = f9
f2TOM56 = f11
fP5 = f12
fP4 = f13
fP3 = f14
fP2 = f15
fLn2_by_128_hi ... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_cosh.S | 161 | 220 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:6 | fP54 = f50
fP5432 = f50
fP32 = f51
fP = f52
fP54_neg = f53
fP5432_neg = f53
fP32_neg = f54
fP_neg = f55
fF_neg = f56
f2M_neg = f57
fS1_neg = f58
fT1_neg ... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_cosh.S | 201 | 260 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:7 | // double-extended 1/ln(2)
// 3fff b8aa 3b29 5c17 f0bb be87fed0691d3e88
// 3fff b8aa 3b29 5c17 f0bc
// For speed the significand will be loaded directly with a movl and setf.sig
// and the exponent will be bias+63 instead of bias+0. Thus subsequent
// computations need to scale appropriately.
// The constant 128/l... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_cosh.S | 241 | 300 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:8 | data8 0x87DB357FF698D792 , 0x00003FFF
data8 0x88980E8092DA8527 , 0x00003FFF
data8 0x8955EE03618E5FDD , 0x00003FFF
data8 0x8A14D575496EFD9A , 0x00003FFF
data8 0x8AD4C6452C728924 , 0x00003FFF
LOCAL_OBJECT_END(exp_table_1)
// Table 2 is 2^(index_1/8) where
// index_2 goes from 0 to 7
LOCAL_OBJECT_START(exp_table_2)
data8... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_cosh.S | 281 | 340 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:9 | { .mlx
getf.exp rSignexp_x = f8 // Must recompute if x unorm
movl rSig_inv_ln2 = 0xb8aa3b295c17f0bc // significand of 1/ln2
}
{ .mlx
addl rAD_TB1 = @ltoff(exp_table_1), gp
movl rRshf_2to56 = 0x4768000000000000 // 1.10000 2^(63+56)
}
;;
{ .mfi
... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_cosh.S | 321 | 380 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:10 | nop.i 0
}
{ .mfb
setf.exp f2TOM56 = rExp_2tom56 // form 2^-56 for scaling Nfloat
nop.f 0
(p6) br.cond.spnt COSH_UNORM // Branch if x=unorm
}
;;
COSH_COMMON:
{ .mfi
ldfe fLn2_by_128_hi = [rAD_TB1],16
nop.f 0
nop.i 0
... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_cosh.S | 361 | 420 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:11 | ;;
{ .mfi
nop.m 0
fmerge.s fAbsX = f0, fNormX // Form |x|
nop.i 0
}
{ .mfb
cmp.gt p7, p0 = -2, rExp_x // Test |x| < 2^(-2)
fma.s1 fXsq = fNormX, fNormX, f0 // x*x for small path
(p7) br.cond.spnt COSH_SMALL // Branch i... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_cosh.S | 401 | 460 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:12 | // Nfloat = round_int(W)
// The signficand of fW_2TO56_RSH contains the rounded integer part of W,
// as a twos complement number in the lower bits (that is, it may be negative).
// That twos complement number (called N) is put into rN.
// Since fW_2TO56_RSH is scaled by 2^56, it must be multiplied by 2^-56
// before ... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_cosh.S | 441 | 500 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:13 | }
{ .mfi
and rIndex_2_16 = 0x70, rN
fnma.s1 fF = fNfloat, fLn2_by_128_lo, f1
sub rN_neg = r0, rN
}
;;
{ .mmi
and rIndex_1_neg = 0x0f, rN_neg
add rBiased_M = rExp_bias_minus_1, rM
shr rM_neg = rN_neg, 0x7
}
{ .mmi... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_cosh.S | 481 | 540 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:14 | nop.i 0
}
{ .mmf
setf.exp f2M_neg = rBiased_M_neg
ldfe fT2_neg = [rAD_T2_neg]
fma.s1 fF_neg = fNfloat, fLn2_by_128_lo, f1
}
;;
{ .mfi
nop.m 0
fma.s1 fRsq = fR, fR, f0
nop.i 0
}
{ .mfi
ldfe fT1_neg ... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_cosh.S | 521 | 580 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:15 | { .mfi
nop.m 0
fma.s1 fP5432 = fRsq, fP54, fP32
nop.i 0
}
{ .mfi
nop.m 0
fma.s1 fS2 = fF,fT2,f0
nop.i 0
}
;;
{ .mfi
nop.m 0
fma.s1 fS1 = f2M,fT1,f0
nop.i 0
}
{ .mfi
nop.... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_cosh.S | 561 | 620 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:16 | }
{ .mfi
nop.m 0
fma.s1 fS = fS1,fS2,f0
nop.i 0
}
;;
{ .mfi
nop.m 0
fms.s1 fP_neg = fRsq, fP5432_neg, fR
nop.i 0
}
{ .mfi
nop.m 0
fma.s1 fS_neg = fS1_neg,fS2_neg,f0
nop.i ... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_cosh.S | 601 | 660 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:17 | nop.m 0
fma.d.s0 f8 = fExp, f1, fExp_neg
br.ret.sptk b0 // Normal path exit
}
;;
// Here if 0 < |x| < 0.25
COSH_SMALL:
{ .mmf
add rAD_T1 = 0x1a0, rAD_TB1
add rAD_T2 = 0x1d0, rAD_TB1
}
;;
{ .mmf
ldfe fA6 = [rAD_T1],1... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_cosh.S | 641 | 700 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:18 | ;;
{ .mfi
nop.m 0
fma.s1 fA65 = fXsq, fA6, fA5
nop.i 0
}
{ .mfi
nop.m 0
fma.s1 fA43 = fXsq, fA4, fA3
nop.i 0
}
;;
{ .mfi
nop.m 0
fma.s1 fA21 = fXsq, fA2, fA1
nop.i 0
}
;;
{ .mf... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_cosh.S | 681 | 740 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:19 | }
{ .mfb
nop.m 0
fma.d.s0 f8 = fA654321, fXsq, f1
br.ret.sptk b0 // Exit if 0 < |x| < 0.25
}
;;
COSH_POSSIBLE_OVERFLOW:
// Here if fMAX_DBL_NORM_ARG < |x| < fMIN_DBL_OFLOW_ARG
// This cannot happen if input is a double, only if input higher precision.
// Overflow... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_cosh.S | 721 | 780 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:20 | { .mfi
nop.m 0
fcmp.ge.s1 p6, p0 = fWre_urm_f8, fGt_pln // Test for overflow
nop.i 0
}
;;
{ .mfb
nop.m 0
nop.f 0
(p6) br.cond.spnt COSH_CERTAIN_OVERFLOW // Branch if overflow
}
;;
{ .mfb
nop.m 0
fma.d.s0 f8 = ... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_cosh.S | 761 | 820 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:21 | ;;
// Here if x unorm
COSH_UNORM:
{ .mfb
getf.exp rSignexp_x = fNormX // Must recompute if x unorm
fcmp.eq.s0 p6, p0 = f8, f0 // Set D flag
br.cond.sptk COSH_COMMON
}
;;
GLOBAL_IEEE754_END(cosh)
libm_alias_double_other (__cosh, cosh)
LOCAL_LIBM_ENTRY(__libm_error_region)
.... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_cosh.S | 801 | 860 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:22 | }
{ .mib
stfd [GR_Parameter_Y] = FR_RESULT // STORE Parameter 3 on stack
add GR_Parameter_Y = -16,GR_Parameter_Y
br.call.sptk b0=__libm_error_support# // Call error handling function
};;
{ .mmi
add GR_Parameter_RESULT = 48,sp
nop.m 0
nop.i 0
};;
{ .mmi
... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_cosh.S | 841 | 866 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:3 | // Get 2^(index_1/128) from table_1;
// Get 2^(index_2/8) from table_2;
// Calculate exp(r) by 5th order polynomial
// r = x - n (log2/128)_high
// delta = - n (log2/128)_low
// Calculate exp(delta) as 1 + delta
// Special values
//==========================================... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 0609ec0a74f6360ebfb45d048f071a75dfcbc6c7 | github | libc | https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_cosh.S | 81 | 140 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:4 | // Assembly macros
//==============================================================
rRshf = r14
rN_neg = r14
rAD_TB1 = r15
rAD_TB2 = r16
rAD_P = r17
rN = r18
rIndex_1 = r19
rIndex_2_16 = r20
rM ... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 0609ec0a74f6360ebfb45d048f071a75dfcbc6c7 | github | libc | https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_cosh.S | 121 | 180 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:5 | GR_Parameter_TAG = r40
FR_X = f10
FR_Y = f1
FR_RESULT = f8
fRSHF_2TO56 = f6
fINV_LN2_2TO63 = f7
fW_2TO56_RSH = f9
f2TOM56 = f11
fP5 = f12
fP4 = f13
fP3 = f14
fP2 ... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 0609ec0a74f6360ebfb45d048f071a75dfcbc6c7 | github | libc | https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_cosh.S | 161 | 220 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:6 | fTmp = f49
fP54 = f50
fP5432 = f50
fP32 = f51
fP = f52
fP54_neg = f53
fP5432_neg = f53
fP32_neg = f54
fP_neg = f55
fF_neg = f56
f2M_neg = f57
fS1_neg ... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 0609ec0a74f6360ebfb45d048f071a75dfcbc6c7 | github | libc | https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_cosh.S | 201 | 260 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:8 | data8 0x871F61969E8D1010 , 0x00003FFF
data8 0x87DB357FF698D792 , 0x00003FFF
data8 0x88980E8092DA8527 , 0x00003FFF
data8 0x8955EE03618E5FDD , 0x00003FFF
data8 0x8A14D575496EFD9A , 0x00003FFF
data8 0x8AD4C6452C728924 , 0x00003FFF
LOCAL_OBJECT_END(exp_table_1)
// Table 2 is 2^(index_1/8) where
// index_2 goes from 0 to 7... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 0609ec0a74f6360ebfb45d048f071a75dfcbc6c7 | github | libc | https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_cosh.S | 281 | 340 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:9 | { .mlx
getf.exp rSignexp_x = f8 // Must recompute if x unorm
movl rSig_inv_ln2 = 0xb8aa3b295c17f0bc // significand of 1/ln2
}
{ .mlx
addl rAD_TB1 = @ltoff(exp_table_1), gp
movl rRshf_2to56 = 0x4768000000000000 // 1.10000 2^(63+56)
}
;;
{ .mfi
... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 0609ec0a74f6360ebfb45d048f071a75dfcbc6c7 | github | libc | https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_cosh.S | 321 | 380 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:10 | fclass.m p10,p0 = f8,0x1e3 // Test for x=inf, nan, NaT
nop.i 0
}
{ .mfb
setf.exp f2TOM56 = rExp_2tom56 // form 2^-56 for scaling Nfloat
nop.f 0
(p6) br.cond.spnt COSH_UNORM // Branch if x=unorm
}
;;
COSH_COMMON:
{ .mfi
ldfe fLn2_by_12... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 0609ec0a74f6360ebfb45d048f071a75dfcbc6c7 | github | libc | https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_cosh.S | 361 | 420 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:11 | }
;;
{ .mfi
nop.m 0
fmerge.s fAbsX = f0, fNormX // Form |x|
nop.i 0
}
{ .mfb
cmp.gt p7, p0 = -2, rExp_x // Test |x| < 2^(-2)
fma.s1 fXsq = fNormX, fNormX, f0 // x*x for small path
(p7) br.cond.spnt COSH_SMALL // Branch... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 0609ec0a74f6360ebfb45d048f071a75dfcbc6c7 | github | libc | https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_cosh.S | 401 | 460 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:12 | ;;
// Nfloat = round_int(W)
// The signficand of fW_2TO56_RSH contains the rounded integer part of W,
// as a twos complement number in the lower bits (that is, it may be negative).
// That twos complement number (called N) is put into rN.
// Since fW_2TO56_RSH is scaled by 2^56, it must be multiplied by 2^-56
// bef... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 0609ec0a74f6360ebfb45d048f071a75dfcbc6c7 | github | libc | https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_cosh.S | 441 | 500 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:13 | shr rM = rN, 0x7
}
{ .mfi
and rIndex_2_16 = 0x70, rN
fnma.s1 fF = fNfloat, fLn2_by_128_lo, f1
sub rN_neg = r0, rN
}
;;
{ .mmi
and rIndex_1_neg = 0x0f, rN_neg
add rBiased_M = rExp_bias_minus_1, rM
shr ... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 0609ec0a74f6360ebfb45d048f071a75dfcbc6c7 | github | libc | https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_cosh.S | 481 | 540 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:14 | nop.m 0
nop.i 0
}
{ .mmf
setf.exp f2M_neg = rBiased_M_neg
ldfe fT2_neg = [rAD_T2_neg]
fma.s1 fF_neg = fNfloat, fLn2_by_128_lo, f1
}
;;
{ .mfi
nop.m 0
fma.s1 fRsq = fR, fR, f0
nop.i 0
}
{ .mfi
... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 0609ec0a74f6360ebfb45d048f071a75dfcbc6c7 | github | libc | https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_cosh.S | 521 | 580 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:16 | nop.i 0
}
{ .mfi
nop.m 0
fma.s1 fS = fS1,fS2,f0
nop.i 0
}
;;
{ .mfi
nop.m 0
fms.s1 fP_neg = fRsq, fP5432_neg, fR
nop.i 0
}
{ .mfi
nop.m 0
fma.s1 fS_neg = fS1_neg,fS2_neg,f0
... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 0609ec0a74f6360ebfb45d048f071a75dfcbc6c7 | github | libc | https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_cosh.S | 601 | 660 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:17 | { .mfb
nop.m 0
fma.d.s0 f8 = fExp, f1, fExp_neg
br.ret.sptk b0 // Normal path exit
}
;;
// Here if 0 < |x| < 0.25
COSH_SMALL:
{ .mmf
add rAD_T1 = 0x1a0, rAD_TB1
add rAD_T2 = 0x1d0, rAD_TB1
}
;;
{ .mmf
ldfe fA6... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 0609ec0a74f6360ebfb45d048f071a75dfcbc6c7 | github | libc | https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_cosh.S | 641 | 700 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:18 | }
;;
{ .mfi
nop.m 0
fma.s1 fA65 = fXsq, fA6, fA5
nop.i 0
}
{ .mfi
nop.m 0
fma.s1 fA43 = fXsq, fA4, fA3
nop.i 0
}
;;
{ .mfi
nop.m 0
fma.s1 fA21 = fXsq, fA2, fA1
nop.i 0
}
;;
{ .... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 0609ec0a74f6360ebfb45d048f071a75dfcbc6c7 | github | libc | https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_cosh.S | 681 | 740 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:19 | nop.i 0
}
{ .mfb
nop.m 0
fma.d.s0 f8 = fA654321, fXsq, f1
br.ret.sptk b0 // Exit if 0 < |x| < 0.25
}
;;
COSH_POSSIBLE_OVERFLOW:
// Here if fMAX_DBL_NORM_ARG < |x| < fMIN_DBL_OFLOW_ARG
// This cannot happen if input is a double, only if input higher prec... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 0609ec0a74f6360ebfb45d048f071a75dfcbc6c7 | github | libc | https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_cosh.S | 721 | 780 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:20 | { .mfi
nop.m 0
fcmp.ge.s1 p6, p0 = fWre_urm_f8, fGt_pln // Test for overflow
nop.i 0
}
;;
{ .mfb
nop.m 0
nop.f 0
(p6) br.cond.spnt COSH_CERTAIN_OVERFLOW // Branch if overflow
}
;;
{ .mfb
nop.m 0
fma.d.s0 f8 = ... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 0609ec0a74f6360ebfb45d048f071a75dfcbc6c7 | github | libc | https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_cosh.S | 761 | 820 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:21 | }
;;
// Here if x unorm
COSH_UNORM:
{ .mfb
getf.exp rSignexp_x = fNormX // Must recompute if x unorm
fcmp.eq.s0 p6, p0 = f8, f0 // Set D flag
br.cond.sptk COSH_COMMON
}
;;
GLOBAL_IEEE754_END(cosh)
libm_alias_double_other (__cosh, cosh)
LOCAL_LIBM_ENTRY(__libm_error_region)... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 0609ec0a74f6360ebfb45d048f071a75dfcbc6c7 | github | libc | https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_cosh.S | 801 | 860 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:22 | nop.b 0
}
{ .mib
stfd [GR_Parameter_Y] = FR_RESULT // STORE Parameter 3 on stack
add GR_Parameter_Y = -16,GR_Parameter_Y
br.call.sptk b0=__libm_error_support# // Call error handling function
};;
{ .mmi
add GR_Parameter_RESULT = 48,sp
nop.m 0
nop.i 0
};;
{ .mmi... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 0609ec0a74f6360ebfb45d048f071a75dfcbc6c7 | github | libc | https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_cosh.S | 841 | 867 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:20 | { .mfi
nop.m 0
fcmp.ge.s1 p6, p0 = fWre_urm_f8, fGt_pln // Test for overflow
nop.i 0
}
;;
{ .mfb
nop.m 0
nop.f 0
(p6) br.cond.spnt COSH_CERTAIN_OVERFLOW // Branch if overflow
}
;;
{ .mfb
nop.m 0
fma.d.s0 f8 = ... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 890b7a4b33d482b5c768ab47d70758b80227e9bc | github | libc | https://github.com/bminor/glibc/blob/890b7a4b33d482b5c768ab47d70758b80227e9bc/sysdeps/ia64/fpu/e_cosh.S | 761 | 820 |
bminor/glibc:sysdeps/ia64/fpu/e_cosh.S:21 | }
;;
// Here if x unorm
COSH_UNORM:
{ .mfb
getf.exp rSignexp_x = fNormX // Must recompute if x unorm
fcmp.eq.s0 p6, p0 = f8, f0 // Set D flag
br.cond.sptk COSH_COMMON
}
;;
GLOBAL_IEEE754_END(cosh)
LOCAL_LIBM_ENTRY(__libm_error_region)
.prologue
{ .mfi
add GR_Para... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_cosh.S | LGPL-2.1 | 890b7a4b33d482b5c768ab47d70758b80227e9bc | github | libc | https://github.com/bminor/glibc/blob/890b7a4b33d482b5c768ab47d70758b80227e9bc/sysdeps/ia64/fpu/e_cosh.S | 801 | 860 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:4 | // General registers used:
// r2, r3, r16 -> r38
// Predicate registers used:
// p6 -> p15
// Assembly macros
//*********************************************************************
// integer registers used
// scratch
rNJ = r2
rNJ_neg = r3
rJ_neg = r16
rN_neg ... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_coshf.S | 121 | 180 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:5 | GR_Parameter_RESULT = r37
GR_Parameter_TAG = r38
// floating point registers used
FR_X = f10
FR_Y = f1
FR_RESULT = f8
// scratch
fRightShifter = f6
f64DivLn2 = f7
fNormX = f9
fNint = f10
fN = f11
... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_coshf.S | 161 | 220 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:6 | RODATA
.align 16
LOCAL_OBJECT_START(_coshf_table)
data4 0x42b2d4fd // Smallest single arg to overflow single result
data4 0x42b2d4fc // Largest single arg to give normal single result
data4 0x00000000 // pad
data4 0x00000000 // pad
//
// 2^(j/64) table, j goes from 0 to 63
data8 0x00000... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_coshf.S | 201 | 260 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:7 | data8 0x0006247EB03A5585 // 2^(30/64)
data8 0x0006623882552225 // 2^(31/64)
data8 0x0006A09E667F3BCD // 2^(32/64)
data8 0x0006DFB23C651A2F // 2^(33/64)
data8 0x00071F75E8EC5F74 // 2^(34/64)
data8 0x00075FEB564267C9 // 2^(35/64)
data8 0x0007A11473EB0187 // 2^(36/64)
data8 0x0007E2F336CF4E62 // 2^(37/64)
data8 0x00082589... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_coshf.S | 241 | 300 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:8 | data8 0x3fdfffffffe2f097 // A1
LOCAL_OBJECT_END(cosh_p_table)
.section .text
GLOBAL_IEEE754_ENTRY(coshf)
{ .mlx
getf.exp rSignexp_x = f8 // Must recompute if x unorm
movl r64DivLn2 = 0x40571547652B82FE // 64/ln(2)
}
{ .mlx
addl rTblAddr = @ltoff(_coshf_table),gp
... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_coshf.S | 281 | 340 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:9 | ;;
{ .mfi
mov rExp_mask = 0x1ffff
fcmp.eq.s1 p13, p0 = f0, f8 // test for x = 0.0
shl rA3 = rA3, 12 // 0x3E2AA000, approx to 1.0/6.0 in SP
}
{ .mfb
nop.m 0
nop.f 0
(p6) br.cond.spnt COSH_UNORM // Branch if x=unorm
}
;;
CO... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_coshf.S | 321 | 380 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:10 | { .mfi
sub rExp_x = rExp_x, rExp_bias // True exponent of x
fmerge.s fAbsX = f0, fNormX // Form |x|
nop.i 0
}
;;
{ .mfi
nop.m 0
// x*(64/ln(2)) + Right Shifter
fma.s1 fNint = fNormX, f64DivLn2, fRightShifter
add ... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_coshf.S | 361 | 420 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:11 | nop.i 0
}
;;
{ .mfi
addl rN = 0xFFBF - 63, rNJ // biased and shifted n-1,j
fnma.s1 fR = fLn2Div64, fN, fNormX // R = x - N*ln(2)/64
and rJ = rJ_mask, rNJ // bits of j
}
{ .mfi
sub rNJ_neg = r0, rNJ // bits of n, j for -... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_coshf.S | 401 | 460 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:12 | { .mfi
ld8 rJ_neg = [rJ_neg] // Table value for -x
nop.f 0
shl rN_neg = rN_neg, 46 // 2^(n-1) bits in DP format for -x
}
;;
{ .mfi
or rN = rN, rJ // bits of 2^n * 2^(j/64) in DP format
nop.f 0
nop.i 0
}
;;... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_coshf.S | 441 | 500 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:13 | fms.s1 fP_neg = fP_neg, fRSqr, fR // P = (A3*R + A2)*R^2 + R, -x
nop.i 0
}
;;
{ .mfi
nop.m 0
fmpy.s0 fTmp = fLn2Div64, fLn2Div64 // Force inexact
nop.i 0
}
;;
{ .mfi
nop.m 0
fma.s1 fExp = fP, fT, fT ... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_coshf.S | 481 | 540 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:14 | }
;;
{ .mmi
ldfpd fA4, fA3 = [rAd1]
ldfpd fA2, fA1 = [rAd2]
nop.i 0
}
;;
{ .mfi
nop.m 0
fma.s1 fX4 = fXsq, fXsq, f0
nop.i 0
}
;;
{ .mfi
nop.m 0
fma.s1 fA43 = fXsq, fA4, fA3
nop.i ... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_coshf.S | 521 | 580 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:15 | nop.i 0
}
{ .mfb
nop.m 0
fma.s.s0 f8 = fA4321, fXsq, f1
br.ret.sptk b0 // Exit if 0 < |x| < 0.25
}
;;
COSH_POSSIBLE_OVERFLOW:
// Here if fMAX_SGL_NORM_ARG < x < fMIN_SGL_OFLOW_ARG
// This cannot happen if input is a single, only if input higher precision... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_coshf.S | 561 | 620 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:16 | { .mfi
nop.m 0
fcmp.ge.s1 p6, p0 = fWre_urm_f8, fGt_pln // Test for overflow
nop.i 0
}
;;
{ .mfb
nop.m 0
nop.f 0
(p6) br.cond.spnt COSH_CERTAIN_OVERFLOW // Branch if overflow
}
;;
{ .mfb
nop.m 0
fma.s.s0 f8 = ... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_coshf.S | 601 | 660 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:17 | }
;;
// Here if x unorm
COSH_UNORM:
{ .mfb
getf.exp rSignexp_x = fNormX // Must recompute if x unorm
fcmp.eq.s0 p6, p0 = f8, f0 // Set D flag
br.cond.sptk COSH_COMMON // Return to main path
}
;;
GLOBAL_IEEE754_END(coshf)
libm_alias_float_other (__cosh, cosh)
LOC... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_coshf.S | 641 | 700 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:18 | add GR_Parameter_RESULT = 0,GR_Parameter_Y // Parameter 3 address
}
{ .mib
stfs [GR_Parameter_Y] = FR_RESULT // Store Parameter 3 on stack
add GR_Parameter_Y = -16,GR_Parameter_Y
br.call.sptk b0=__libm_error_support# // Call error handling function
};;
{ .mmi
add GR_Parameter_RESU... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_coshf.S | 681 | 711 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:4 | // f6,f7, f9 -> f15, f32 -> f45
// General registers used:
// r2, r3, r16 -> r38
// Predicate registers used:
// p6 -> p15
// Assembly macros
//*********************************************************************
// integer registers used
// scratch
rNJ = r2
rNJ_neg = r3
rJ_neg ... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | aa1142c593447b433208a79bd5a95095cd5dd892 | github | libc | https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_coshf.S | 121 | 180 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:5 | GR_Parameter_Y = r36
GR_Parameter_RESULT = r37
GR_Parameter_TAG = r38
// floating point registers used
FR_X = f10
FR_Y = f1
FR_RESULT = f8
// scratch
fRightShifter = f6
f64DivLn2 = f7
fNormX = f9
fNint = f10
... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | aa1142c593447b433208a79bd5a95095cd5dd892 | github | libc | https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_coshf.S | 161 | 220 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:6 | RODATA
.align 16
LOCAL_OBJECT_START(_coshf_table)
data4 0x42b2d4fd // Smallest single arg to overflow single result
data4 0x42b2d4fc // Largest single arg to give normal single result
data4 0x00000000 // pad
data4 0x00000000 // pad
//
// 2^(j/64) table, j goes from 0 to 63
data8 0x00000... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | aa1142c593447b433208a79bd5a95095cd5dd892 | github | libc | https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_coshf.S | 201 | 260 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:7 | data8 0x0005E76F15AD2148 // 2^(29/64)
data8 0x0006247EB03A5585 // 2^(30/64)
data8 0x0006623882552225 // 2^(31/64)
data8 0x0006A09E667F3BCD // 2^(32/64)
data8 0x0006DFB23C651A2F // 2^(33/64)
data8 0x00071F75E8EC5F74 // 2^(34/64)
data8 0x00075FEB564267C9 // 2^(35/64)
data8 0x0007A11473EB0187 // 2^(36/64)
data8 0x0007E2F3... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | aa1142c593447b433208a79bd5a95095cd5dd892 | github | libc | https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_coshf.S | 241 | 300 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:8 | data8 0x3fa5555572601504 // A2
data8 0x3fdfffffffe2f097 // A1
LOCAL_OBJECT_END(cosh_p_table)
.section .text
GLOBAL_IEEE754_ENTRY(coshf)
{ .mlx
getf.exp rSignexp_x = f8 // Must recompute if x unorm
movl r64DivLn2 = 0x40571547652B82FE // 64/ln(2)
}
{ .mlx
addl rTblAddr =... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | aa1142c593447b433208a79bd5a95095cd5dd892 | github | libc | https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_coshf.S | 281 | 340 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:9 | }
;;
{ .mfi
mov rExp_mask = 0x1ffff
fcmp.eq.s1 p13, p0 = f0, f8 // test for x = 0.0
shl rA3 = rA3, 12 // 0x3E2AA000, approx to 1.0/6.0 in SP
}
{ .mfb
nop.m 0
nop.f 0
(p6) br.cond.spnt COSH_UNORM // Branch if x=unorm
}
;;
... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | aa1142c593447b433208a79bd5a95095cd5dd892 | github | libc | https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_coshf.S | 321 | 380 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:10 | { .mfi
sub rExp_x = rExp_x, rExp_bias // True exponent of x
fmerge.s fAbsX = f0, fNormX // Form |x|
nop.i 0
}
;;
{ .mfi
nop.m 0
// x*(64/ln(2)) + Right Shifter
fma.s1 fNint = fNormX, f64DivLn2, fRightShifter
add ... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | aa1142c593447b433208a79bd5a95095cd5dd892 | github | libc | https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_coshf.S | 361 | 420 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:11 | fcmp.gt.s1 p13, p0 = fAbsX, fMAX_SGL_NORM_ARG
nop.i 0
}
;;
{ .mfi
addl rN = 0xFFBF - 63, rNJ // biased and shifted n-1,j
fnma.s1 fR = fLn2Div64, fN, fNormX // R = x - N*ln(2)/64
and rJ = rJ_mask, rNJ // bits of j
}
{ .mfi
sub ... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | aa1142c593447b433208a79bd5a95095cd5dd892 | github | libc | https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_coshf.S | 401 | 460 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:12 | { .mfi
ld8 rJ_neg = [rJ_neg] // Table value for -x
nop.f 0
shl rN_neg = rN_neg, 46 // 2^(n-1) bits in DP format for -x
}
;;
{ .mfi
or rN = rN, rJ // bits of 2^n * 2^(j/64) in DP format
nop.f 0
nop.i 0
}
;;... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | aa1142c593447b433208a79bd5a95095cd5dd892 | github | libc | https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_coshf.S | 441 | 500 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:13 | nop.m 0
fms.s1 fP_neg = fP_neg, fRSqr, fR // P = (A3*R + A2)*R^2 + R, -x
nop.i 0
}
;;
{ .mfi
nop.m 0
fmpy.s0 fTmp = fLn2Div64, fLn2Div64 // Force inexact
nop.i 0
}
;;
{ .mfi
nop.m 0
fma.s1 fExp ... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | aa1142c593447b433208a79bd5a95095cd5dd892 | github | libc | https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_coshf.S | 481 | 540 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:14 | nop.i 0
}
;;
{ .mmi
ldfpd fA4, fA3 = [rAd1]
ldfpd fA2, fA1 = [rAd2]
nop.i 0
}
;;
{ .mfi
nop.m 0
fma.s1 fX4 = fXsq, fXsq, f0
nop.i 0
}
;;
{ .mfi
nop.m 0
fma.s1 fA43 = fXsq, fA4, fA3
... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | aa1142c593447b433208a79bd5a95095cd5dd892 | github | libc | https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_coshf.S | 521 | 580 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:15 | fmpy.s0 fTmp = fA4, fA4
nop.i 0
}
{ .mfb
nop.m 0
fma.s.s0 f8 = fA4321, fXsq, f1
br.ret.sptk b0 // Exit if 0 < |x| < 0.25
}
;;
COSH_POSSIBLE_OVERFLOW:
// Here if fMAX_SGL_NORM_ARG < x < fMIN_SGL_OFLOW_ARG
// This cannot happen if input is a ... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | aa1142c593447b433208a79bd5a95095cd5dd892 | github | libc | https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_coshf.S | 561 | 620 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:16 | { .mfi
nop.m 0
fcmp.ge.s1 p6, p0 = fWre_urm_f8, fGt_pln // Test for overflow
nop.i 0
}
;;
{ .mfb
nop.m 0
nop.f 0
(p6) br.cond.spnt COSH_CERTAIN_OVERFLOW // Branch if overflow
}
;;
{ .mfb
nop.m 0
fma.s.s0 f8 = ... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | aa1142c593447b433208a79bd5a95095cd5dd892 | github | libc | https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_coshf.S | 601 | 660 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:17 | br.cond.sptk __libm_error_region
}
;;
// Here if x unorm
COSH_UNORM:
{ .mfb
getf.exp rSignexp_x = fNormX // Must recompute if x unorm
fcmp.eq.s0 p6, p0 = f8, f0 // Set D flag
br.cond.sptk COSH_COMMON // Return to main path
}
;;
GLOBAL_IEEE754_END(coshf)
libm_al... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | aa1142c593447b433208a79bd5a95095cd5dd892 | github | libc | https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_coshf.S | 641 | 700 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:18 | nop.f 0
add GR_Parameter_RESULT = 0,GR_Parameter_Y // Parameter 3 address
}
{ .mib
stfs [GR_Parameter_Y] = FR_RESULT // Store Parameter 3 on stack
add GR_Parameter_Y = -16,GR_Parameter_Y
br.call.sptk b0=__libm_error_support# // Call error handling function
};;
{ .mmi
add GR_... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | aa1142c593447b433208a79bd5a95095cd5dd892 | github | libc | https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_coshf.S | 681 | 712 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:16 | { .mfi
nop.m 0
fcmp.ge.s1 p6, p0 = fWre_urm_f8, fGt_pln // Test for overflow
nop.i 0
}
;;
{ .mfb
nop.m 0
nop.f 0
(p6) br.cond.spnt COSH_CERTAIN_OVERFLOW // Branch if overflow
}
;;
{ .mfb
nop.m 0
fma.s.s0 f8 = ... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | 890b7a4b33d482b5c768ab47d70758b80227e9bc | github | libc | https://github.com/bminor/glibc/blob/890b7a4b33d482b5c768ab47d70758b80227e9bc/sysdeps/ia64/fpu/e_coshf.S | 601 | 660 |
bminor/glibc:sysdeps/ia64/fpu/e_coshf.S:17 | br.cond.sptk __libm_error_region
}
;;
// Here if x unorm
COSH_UNORM:
{ .mfb
getf.exp rSignexp_x = fNormX // Must recompute if x unorm
fcmp.eq.s0 p6, p0 = f8, f0 // Set D flag
br.cond.sptk COSH_COMMON // Return to main path
}
;;
GLOBAL_IEEE754_END(coshf)
LOCAL... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshf.S | LGPL-2.1 | 890b7a4b33d482b5c768ab47d70758b80227e9bc | github | libc | https://github.com/bminor/glibc/blob/890b7a4b33d482b5c768ab47d70758b80227e9bc/sysdeps/ia64/fpu/e_coshf.S | 641 | 700 |
bminor/glibc:sysdeps/ia64/fpu/e_coshl.S:4 | // ==============
// Can approximate result by exp(x)/2 in this region.
// Y_hi = Tjhi
// Y_lo = Tjhi * (p_odd + p_even) + Tjlo
// cosh(x) = Y_hi + Y_lo
//
// 4. COSH_HUGE |x| >= 11357.21655 ( 400c b174 ddc0 31ae c0ea )
// ============
// Set error tag and call error support
//
//
// Assembly macros
//============... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshl.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_coshl.S | 121 | 180 |
bminor/glibc:sysdeps/ia64/fpu/e_coshl.S:5 | r_exp_32 = r30
r_exp_huge = r30
r_ad4 = r31
GR_SAVE_PFS = r34
GR_SAVE_B0 = r35
GR_SAVE_GP = r36
GR_Parameter_X = r37
GR_Parameter_Y = r38
GR_Parameter_RESULT = r39
GR_Parameter_TAG = r40
f_ABS_X = f9
f_X2 ... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshl.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_coshl.S | 161 | 220 |
bminor/glibc:sysdeps/ia64/fpu/e_coshl.S:6 | f_peven = f49
f_podd_temp1 = f50
f_podd_temp2 = f51
f_podd = f52
f_poly65 = f53
f_poly6543 = f53
f_poly6to1 = f53
f_poly43 = f54
f_poly21 = f55
f_X3 = f56
f_INV_LN2_2TO63 = f57
f_RSHF_2TO... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshl.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_coshl.S | 201 | 260 |
bminor/glibc:sysdeps/ia64/fpu/e_coshl.S:7 | f_P1 = f81
f_P2 = f82
f_P3 = f83
f_P4 = f84
f_P5 = f85
f_P6 = f86
f_Tjhi_spos = f87
f_Tjlo_spos = f88
f_huge = f89
f_signed_hi_lo = f90
// Data tables
//====================... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshl.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_coshl.S | 241 | 300 |
bminor/glibc:sysdeps/ia64/fpu/e_coshl.S:8 | data8 0xD00D0C6DCC26A86B, 0x00003FF2 // A3
data8 0x8000000000000002, 0x00003FFE // B1
data8 0xAAAAAAAAAA402C77, 0x00003FFA // B2
data8 0xB60B6CC96BDB144D, 0x00003FF5 // B3
LOCAL_OBJECT_END(cosh_ab_table)
LOCAL_OBJECT_START(cosh_j_hi_table)
data8 0xB504F333F9DE6484, 0x00003FFE
data8 0xB6FD91E328D1779... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshl.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_coshl.S | 281 | 340 |
bminor/glibc:sysdeps/ia64/fpu/e_coshl.S:9 | data8 0x8164D1F3BC030773, 0x00003FFF
data8 0x82CD8698AC2BA1D7, 0x00003FFF
data8 0x843A28C3ACDE4046, 0x00003FFF
data8 0x85AAC367CC487B15, 0x00003FFF
data8 0x871F61969E8D1010, 0x00003FFF
data8 0x88980E8092DA8527, 0x00003FFF
data8 0x8A14D575496EFD9A, 0x00003FFF
data8 0x8B95C1E3EA8BD6E7, 0x00003FFF
... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshl.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_coshl.S | 321 | 380 |
bminor/glibc:sysdeps/ia64/fpu/e_coshl.S:10 | data4 0x9DBF517B
data4 0x1EF88AFB
data4 0x1E03B216
data4 0x1E78AB43
data4 0x9E7B1747
data4 0x9EFE3C0E
data4 0x9D36F837
data4 0x9DEE53E4
data4 0x9E24AE8E
data4 0x1D912473
data4 0x1EB243BE
data4 0x1E669A2F
data4 0x9BBC610A
data4 0x1E761035
data4 0x9E0BE175
data4 0x1CCB12A1
... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshl.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_coshl.S | 361 | 420 |
bminor/glibc:sysdeps/ia64/fpu/e_coshl.S:11 | data4 0x9EB319B0
data4 0x1EBA2BEB
data4 0x1F11D537
data4 0x1F0D5A46
data4 0x9E5E7BCA
data4 0x9F3AAFD1
data4 0x9E86DACC
data4 0x9F3EDDC2
data4 0x1E496E3D
data4 0x9F490BF6
data4 0x1DD1DB48
data4 0x1E65EBFB
data4 0x9F427496
data4 0x1F283C4A
data4 0x1F4B0047
data4 0x1F130152
... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshl.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_coshl.S | 401 | 460 |
bminor/glibc:sysdeps/ia64/fpu/e_coshl.S:12 | }
{ .mfi
nop.m 0
fnorm.s1 f_NORM_X = f8
mov r_exp_2tom57 = 0xffff-57
}
;;
{ .mfi
setf.d f_RSHF_2TO57 = r_rshf_2to57 // Form const 1.100 * 2^120
fclass.m p10,p0 = f8, 0x0b // Test for denorm
mov r_exp_mask = 0x1ffff
}... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshl.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_coshl.S | 441 | 500 |
bminor/glibc:sysdeps/ia64/fpu/e_coshl.S:13 | }
;;
// Common path -- return here from COSH_DENORM if x is unnorm
COSH_COMMON:
{ .mfi
ldfe f_smlst_oflow_input = [r_ad2e],16
(p7) fma.s0 f8 = f1, f1, f0 // Result = 1.0 if x=0
add r_ad5 = 0x580, r_ad1 // Point to j_lo_table midpoint
}
{ .mib
ldfe f_lo... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshl.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_coshl.S | 481 | 540 |
bminor/glibc:sysdeps/ia64/fpu/e_coshl.S:14 | }
;;
// Here if |x| >= 0.25
COSH_BY_TBL:
// ******************************************************
// STEP 1 (TBL and EXP) - Argument reduction
// ******************************************************
// Get the following constants.
// Inv_log2by64
// log2by64_hi
// log2by64_lo
// We want 2^(N-1) and 2^(-N-1). So b... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshl.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_coshl.S | 521 | 580 |
bminor/glibc:sysdeps/ia64/fpu/e_coshl.S:15 | mov r_signexp_0_5 = 0x0fffe // signexp of +0.5
}
;;
// Test for |x| >= overflow limit
{ .mfi
ldfe f_B1 = [r_ad3],16
fcmp.ge.s1 p6,p0 = f_ABS_X, f_smlst_oflow_input
nop.i 0
}
;;
{ .mfi
ldfe f_B2 = [r_ad3],16
nop.f 0
mov ... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshl.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_coshl.S | 561 | 620 |
bminor/glibc:sysdeps/ia64/fpu/e_coshl.S:16 | // R = (ax - M*log2by64_hi) - M*log2by64_lo
{ .mfi
nop.m 0
fnma.s1 f_R_temp = f_M, f_log2by64_hi, f_ABS_X
and r_j = 0x3f, r_M
}
;;
{ .mii
nop.m 0
shl r_jshf = r_j, 0x2 // Shift j so can sign extend it
;;
sxt1 r_jshf = r... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshl.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_coshl.S | 601 | 660 |
bminor/glibc:sysdeps/ia64/fpu/e_coshl.S:17 | }
{ .mfi
shladd r_ad_mJ_hi = r_mj, 4, r_ad4 // pointer to Tmjhi
nop.f 0
shladd r_ad_mJ_lo = r_mj, 2, r_ad5 // pointer to Tmjlo
}
;;
{ .mfi
sub r_2mNm1 = r_signexp_0_5, r_N // signexp 2^(-N-1)
nop.f 0
shladd r_ad_J_lo = r_j, ... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshl.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_coshl.S | 641 | 700 |
bminor/glibc:sysdeps/ia64/fpu/e_coshl.S:18 | nop.m 0
nop.m 0
fma.s1 f_Rsq = f_R, f_R, f0
}
;;
// Calculate p_even
// B_2 + Rsq *B_3
// B_1 + Rsq * (B_2 + Rsq *B_3)
// p_even = Rsq * (B_1 + Rsq * (B_2 + Rsq *B_3))
{ .mfi
nop.m 0
fma.s1 f_peven_temp1 = f_Rsq, f_B3, f_B2
nop.i ... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshl.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_coshl.S | 681 | 740 |
bminor/glibc:sysdeps/ia64/fpu/e_coshl.S:19 | // C_hi = spos * Tjhi + SC_hi_temp
// C_hi = spos * Tjhi + (sneg * Tmjhi)
{ .mfi
nop.m 0
(p6) fma.s1 f_SC_hi_temp = f_sneg, f_Tmjhi, f0
nop.i 0
}
;;
// If TBL,
// C_lo_temp3 = sneg * Tmjlo
// C_lo_temp4 = spos * Tjlo + C_lo_temp3
// C_lo_temp4 = spos * Tjlo + (sneg * Tmjlo)
{... | x86_64 | intel-like | handwritten | bminor/glibc | sysdeps/ia64/fpu/e_coshl.S | LGPL-2.1 | 30891f35fa7da832b66d80d0807610df361851f3 | github | libc | https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_coshl.S | 721 | 780 |
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