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int64
1
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int64
4
5.5k
bminor/glibc:sysdeps/ia64/fpu/e_atanh.S:6
fLogT = f50 fLogT_N = f51 fX2 = f52 fX3 = f53 fX4 = f54 fX8 = f55 fP0 = f56 fP5 = f57 fP4 = f58 fP3 = f59 fP2 = f60 fP1 ...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanh.S
LGPL-2.1
0609ec0a74f6360ebfb45d048f071a75dfcbc6c7
github
libc
https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_atanh.S
201
260
bminor/glibc:sysdeps/ia64/fpu/e_atanh.S:7
data8 0x0000000000000000 // pad data8 0xb17217f7d1cf79ac , 0x00003ffd // 0.5*log(2) data8 0x0000000000000000 , 0x00000000 // pad to eliminate bank conflicts LOCAL_OBJECT_END(atanh_data) LOCAL_OBJECT_START(atanh_data_2) data8 0x8649FB89D3AD51FB , 0x00003FFB // C9 data8 0xCC10AABEF160077A , 0x00003F...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanh.S
LGPL-2.1
0609ec0a74f6360ebfb45d048f071a75dfcbc6c7
github
libc
https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_atanh.S
241
300
bminor/glibc:sysdeps/ia64/fpu/e_atanh.S:8
data8 0xffd3488d5c980465 , 0x00003ff9 // log(1/frcpa(1+16/2^-8))/2 data8 0x87609ce2ed300490 , 0x00003ffa // log(1/frcpa(1+17/2^-8))/2 data8 0x8ede9321e8c85927 , 0x00003ffa // log(1/frcpa(1+18/2^-8))/2 data8 0x96639427f2f8e2f4 , 0x00003ffa // log(1/frcpa(1+19/2^-8))/2 data8 0x9defad3e8f73217b , 0x00003ffa // l...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanh.S
LGPL-2.1
0609ec0a74f6360ebfb45d048f071a75dfcbc6c7
github
libc
https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_atanh.S
281
340
bminor/glibc:sysdeps/ia64/fpu/e_atanh.S:9
data8 0xb819bee9e720d42f , 0x00003ffb // log(1/frcpa(1+50/2^-8))/2 // data8 0xbbb2a0947b093a5d , 0x00003ffb // log(1/frcpa(1+51/2^-8))/2 data8 0xbf4ec1505811684a , 0x00003ffb // log(1/frcpa(1+52/2^-8))/2 data8 0xc2535bacfa8975ff , 0x00003ffb // log(1/frcpa(1+53/2^-8))/2 data8 0xc55a3eafad187eb8 , 0x00003ffb // ...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanh.S
LGPL-2.1
0609ec0a74f6360ebfb45d048f071a75dfcbc6c7
github
libc
https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_atanh.S
321
380
bminor/glibc:sysdeps/ia64/fpu/e_atanh.S:10
data8 0x90a22b6875c6a1f8 , 0x00003ffc // log(1/frcpa(1+83/2^-8))/2 data8 0x91f62cc8f5d24837 , 0x00003ffc // log(1/frcpa(1+84/2^-8))/2 data8 0x93a06cfc3857d980 , 0x00003ffc // log(1/frcpa(1+85/2^-8))/2 // data8 0x94f66d5e6fd01ced , 0x00003ffc // log(1/frcpa(1+86/2^-8))/2 data8 0x96a330156e6772f2 , 0x00003ffc // ...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanh.S
LGPL-2.1
0609ec0a74f6360ebfb45d048f071a75dfcbc6c7
github
libc
https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_atanh.S
361
420
bminor/glibc:sysdeps/ia64/fpu/e_atanh.S:11
data8 0xc034f19c139186f4 , 0x00003ffc // log(1/frcpa(1+116/2^-8))/2 data8 0xc14cb69f7c5e55ab , 0x00003ffc // log(1/frcpa(1+117/2^-8))/2 data8 0xc2c2abbb6e5fd56f , 0x00003ffc // log(1/frcpa(1+118/2^-8))/2 data8 0xc439b2c193e6771e , 0x00003ffc // log(1/frcpa(1+119/2^-8))/2 data8 0xc553acb9d5c67733 , 0x00003ffc //...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanh.S
LGPL-2.1
0609ec0a74f6360ebfb45d048f071a75dfcbc6c7
github
libc
https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_atanh.S
401
460
bminor/glibc:sysdeps/ia64/fpu/e_atanh.S:12
data8 0xeca84b83d7297b87 , 0x00003ffc // log(1/frcpa(1+150/2^-8))/2 // data8 0xedd977f4962aa158 , 0x00003ffc // log(1/frcpa(1+151/2^-8))/2 data8 0xef7179a22f257754 , 0x00003ffc // log(1/frcpa(1+152/2^-8))/2 data8 0xf0a450d139366ca7 , 0x00003ffc // log(1/frcpa(1+153/2^-8))/2 data8 0xf1d7e0524ff9ffdb , 0x00003ffc...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanh.S
LGPL-2.1
0609ec0a74f6360ebfb45d048f071a75dfcbc6c7
github
libc
https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_atanh.S
441
500
bminor/glibc:sysdeps/ia64/fpu/e_atanh.S:13
data8 0x8a572ac5a5496882 , 0x00003ffd // log(1/frcpa(1+183/2^-8))/2 data8 0x8afc2d0ce3b2dadf , 0x00003ffd // log(1/frcpa(1+184/2^-8))/2 data8 0x8b6a69c608cfd3af , 0x00003ffd // log(1/frcpa(1+185/2^-8))/2 // data8 0x8c101e106e899a83 , 0x00003ffd // log(1/frcpa(1+186/2^-8))/2 data8 0x8cb63de258f9d626 , 0x00003ffd...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanh.S
LGPL-2.1
0609ec0a74f6360ebfb45d048f071a75dfcbc6c7
github
libc
https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_atanh.S
481
540
bminor/glibc:sysdeps/ia64/fpu/e_atanh.S:14
data8 0x9ccd0abd301f399c , 0x00003ffd // log(1/frcpa(1+216/2^-8))/2 data8 0x9d7e67f3bdce8888 , 0x00003ffd // log(1/frcpa(1+217/2^-8))/2 data8 0x9df4ea81a99daa01 , 0x00003ffd // log(1/frcpa(1+218/2^-8))/2 data8 0x9e6ba405a54514ba , 0x00003ffd // log(1/frcpa(1+219/2^-8))/2 data8 0x9f1e21c8c7bb62b3 , 0x00003ffd //...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanh.S
LGPL-2.1
0609ec0a74f6360ebfb45d048f071a75dfcbc6c7
github
libc
https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_atanh.S
521
580
bminor/glibc:sysdeps/ia64/fpu/e_atanh.S:15
data8 0xaeb5d9175437afa2 , 0x00003ffd // log(1/frcpa(1+250/2^-8))/2 // data8 0xaf349c322e9c7cee , 0x00003ffd // log(1/frcpa(1+251/2^-8))/2 data8 0xafb39e30d1768d1c , 0x00003ffd // log(1/frcpa(1+252/2^-8))/2 data8 0xb032df51c2c93116 , 0x00003ffd // log(1/frcpa(1+253/2^-8))/2 data8 0xb0b25fd3e6035ad9 , 0x00003ffd...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanh.S
LGPL-2.1
0609ec0a74f6360ebfb45d048f071a75dfcbc6c7
github
libc
https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_atanh.S
561
620
bminor/glibc:sysdeps/ia64/fpu/e_atanh.S:16
fcmp.lt.s1 p10,p11 = f8,f0 // is x < 0 ? nop.i 0 } { .mfb nop.m 0 fnorm.s1 fNormX = f8 // Normalize x (p13) br.cond.spnt ATANH_UNORM // Branch if x=unorm } ;; ATANH_COMMON: // Return here if x=unorm and not denorm { .mfi...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanh.S
LGPL-2.1
0609ec0a74f6360ebfb45d048f071a75dfcbc6c7
github
libc
https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_atanh.S
601
660
bminor/glibc:sysdeps/ia64/fpu/e_atanh.S:17
} ;; { .mfi ldfe fC7 = [Data2Ptr], 16 (p10) fnma.s1 fOnePx = fNormX, f1, f1 // fOnePx = 1 + |x| cmp.ge p6,p0 = rArgExpb, rBias // is Expb(Arg) >= Expb(1) ? } { .mfb nop.m 0 nop.f 0 (p6) br.cond.spnt atanh_ge_one // Branc...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanh.S
LGPL-2.1
0609ec0a74f6360ebfb45d048f071a75dfcbc6c7
github
libc
https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_atanh.S
641
700
bminor/glibc:sysdeps/ia64/fpu/e_atanh.S:18
nop.i 0 } { .mfi nop.m 0 (p10) fnma.s1 fRcp1 = fRcp0n, fOneMx, f1 // t = 1 - r0*x nop.i 0 } ;; { .mfi ldfpd fP3, fP2 = [DataPtr], 16 // r1 = r0 + r0*t = r0 + r0*(1 - r0*x) (p11) fma.s1 fRcp1 = fRcp0, fRcp1, fRcp0 nop.i 0 } { .mfi ...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanh.S
LGPL-2.1
0609ec0a74f6360ebfb45d048f071a75dfcbc6c7
github
libc
https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_atanh.S
681
740
bminor/glibc:sysdeps/ia64/fpu/e_atanh.S:19
{ .mfi adds RcpTablePtr = 0xB0, DataPtr fnma.s1 fRcp3 = fRcp2, fOneMx, f1 // t = 1 - r2*x nop.i 0 } { .mfi nop.m 0 fma.s1 fY4Rcp = fRcp2, fOnePx, f0 // fY4Rcp = r2*(1 + x) nop.i 0 } ;; // polynomial approximation & final recon...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanh.S
LGPL-2.1
0609ec0a74f6360ebfb45d048f071a75dfcbc6c7
github
libc
https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_atanh.S
721
780
bminor/glibc:sysdeps/ia64/fpu/e_atanh.S:20
{ .mmi and rExpb = rSExpb, rExpbMask ;; sub rN = rExpb, rBias // exponent extr.u rInd = rSig,55,8 // Extract 8 bits } ;; { .mmi setf.sig fN4Cvt = rN shladd RcpTablePtr = rInd, 4, RcpTablePtr nop.i 0 } ;; { ...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanh.S
LGPL-2.1
0609ec0a74f6360ebfb45d048f071a75dfcbc6c7
github
libc
https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_atanh.S
761
820
bminor/glibc:sysdeps/ia64/fpu/e_atanh.S:21
{ .mfi nop.m 0 fma.s1 fP10 = fP1, fR2, fR // P1*r^2 + r nop.i 0 } ;; { .mfi nop.m 0 fcvt.xf fN = fN4Cvt nop.i 0 } { .mfi nop.m 0 fma.s1 fP54 = fP54, fR2, fP32 // (P5*r + P4)*r^2 + P3*r + P2 ...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanh.S
LGPL-2.1
0609ec0a74f6360ebfb45d048f071a75dfcbc6c7
github
libc
https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_atanh.S
801
860
bminor/glibc:sysdeps/ia64/fpu/e_atanh.S:22
nop.m 0 // -0.5*(((P5*r + P4)*r^2 + P3*r + P2)*r^3 + P1*r^2 + r) - 0.5*(N*Log2 + T) (p10) fms.d.s0 f8 = fP54, fP1, fLogT_N br.ret.sptk b0 // Exit for 0.25 <= |x| < 1.0 } ;; // Here if 0 < |x| < 0.25 atanh_near_zero: { .mfi ldfe fC4 = [Data2Ptr], 16 ...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanh.S
LGPL-2.1
0609ec0a74f6360ebfb45d048f071a75dfcbc6c7
github
libc
https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_atanh.S
841
900
bminor/glibc:sysdeps/ia64/fpu/e_atanh.S:23
{ .mfi nop.m 0 fma.s1 fP54 = fC5, fX2, fC4 // C5*x^2 + C4 nop.i 0 } ;; { .mfi nop.m 0 fma.s1 fP32 = fC3, fX2, fC2 // C3*x^2 + C2 nop.i 0 } ;; { .mfi nop.m 0 fma.s1 fP10 = fC1, fX2, fC0 ...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanh.S
LGPL-2.1
0609ec0a74f6360ebfb45d048f071a75dfcbc6c7
github
libc
https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_atanh.S
881
940
bminor/glibc:sysdeps/ia64/fpu/e_atanh.S:24
fma.s1 fP98 = fP98, fX4, fP10 nop.i 0 } ;; { .mfb nop.m 0 // C9*x^21 + C8*x^19 + C7*x^17 + C6*x^15 + C5*x^13 + C4*x^11 + C3*x^9 + // C2*x^7 + C1*x^5 + C0*x^3 + x fma.d.s0 f8 = fP98, fX3, fNormX br.ret.sptk b0 // Exit for 0 < |x...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanh.S
LGPL-2.1
0609ec0a74f6360ebfb45d048f071a75dfcbc6c7
github
libc
https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_atanh.S
921
980
bminor/glibc:sysdeps/ia64/fpu/e_atanh.S:25
} ;; // Here if |x| >= 1.0 atanh_ge_one: { .mfi alloc r32 = ar.pfs,1,3,4,0 fmerge.s fAbsX = f0, f8 // Form |x| nop.i 0 } ;; { .mfi nop.m 0 fmerge.s f10 = f8, f8 // Save input for error call nop.i 0 } ;; { .mfi nop...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanh.S
LGPL-2.1
0609ec0a74f6360ebfb45d048f071a75dfcbc6c7
github
libc
https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_atanh.S
961
1,020
bminor/glibc:sysdeps/ia64/fpu/e_atanh.S:26
;; { .mfb (p6) mov atanh_GR_tag = 132 (p6) fmerge.s f8 = f8, fRcp // result is +-inf br.cond.sptk __libm_error_region // Exit if |x| >= 1.0 } ;; GLOBAL_LIBM_END(atanh) libm_alias_double_other (atanh, atanh) LOCAL_LIBM_ENTRY(__libm_error_region) .prologue { .mfi add ...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanh.S
LGPL-2.1
0609ec0a74f6360ebfb45d048f071a75dfcbc6c7
github
libc
https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_atanh.S
1,001
1,060
bminor/glibc:sysdeps/ia64/fpu/e_atanh.S:27
nop.b 0 } { .mib stfd [GR_Parameter_Y] = f8 // STORE Parameter 3 on stack add GR_Parameter_Y = -16,GR_Parameter_Y br.call.sptk b0=__libm_error_support# // Call error handling function };; { .mmi add GR_Parameter_RESULT = 48,sp nop.m 0 nop.i 0 };; { .mmi ...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanh.S
LGPL-2.1
0609ec0a74f6360ebfb45d048f071a75dfcbc6c7
github
libc
https://github.com/bminor/glibc/blob/0609ec0a74f6360ebfb45d048f071a75dfcbc6c7/sysdeps/ia64/fpu/e_atanh.S
1,041
1,072
bminor/glibc:sysdeps/ia64/fpu/e_atanh.S:25
} ;; // Here if |x| >= 1.0 atanh_ge_one: { .mfi alloc r32 = ar.pfs,1,3,4,0 fmerge.s fAbsX = f0, f8 // Form |x| nop.i 0 } ;; { .mfi nop.m 0 fmerge.s f10 = f8, f8 // Save input for error call nop.i 0 } ;; { .mfi nop...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanh.S
LGPL-2.1
890b7a4b33d482b5c768ab47d70758b80227e9bc
github
libc
https://github.com/bminor/glibc/blob/890b7a4b33d482b5c768ab47d70758b80227e9bc/sysdeps/ia64/fpu/e_atanh.S
961
1,020
bminor/glibc:sysdeps/ia64/fpu/e_atanh.S:26
;; { .mfb (p6) mov atanh_GR_tag = 132 (p6) fmerge.s f8 = f8, fRcp // result is +-inf br.cond.sptk __libm_error_region // Exit if |x| >= 1.0 } ;; GLOBAL_LIBM_END(atanh) LOCAL_LIBM_ENTRY(__libm_error_region) .prologue { .mfi add GR_Parameter_Y=-32,sp // Pa...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanh.S
LGPL-2.1
890b7a4b33d482b5c768ab47d70758b80227e9bc
github
libc
https://github.com/bminor/glibc/blob/890b7a4b33d482b5c768ab47d70758b80227e9bc/sysdeps/ia64/fpu/e_atanh.S
1,001
1,060
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:4
// pre-index = f_1f_2....f_8 // index = pre_index * 16 // get the dxt table entry at index + offset = T // // result = (T + Nfloat * log(2)) + rseries // // The T table is calculated as follows // Form x_k = 1 + k/2^8 where k goes from 0... 255 // y_k = frcpa(x_k) // log(1/y_k) in quad and round to double-ex...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhf.S
121
180
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:5
rExpbp = r23 rSigm = r24 rSigp = r25 rNm = r26 rNp = r27 rIndm = r28 rIndp = r29 GR_SAVE_B0 = r33 GR_SAVE_GP = r34 GR_SAVE_PFS = r35 GR_Parameter_X = r36 GR_Paramet...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhf.S
161
220
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:6
fP10p = f54 fX2 = f55 fP3 = f56 fP2 = f57 fP1 = f58 fHalf = f59 // Data tables //============================================================== RODATA .align 16 LOCAL_OBJECT_START(atanhf_data) data8 0xbfc000100...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhf.S
201
260
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:7
data8 0x3f9c441e06f72a9e //log(1/frcpa(1+14/256))/2 data8 0x3f9e1e6713606d07 //log(1/frcpa(1+15/256))/2 data8 0x3f9ffa6911ab9301 //log(1/frcpa(1+16/256))/2 data8 0x3fa0ec139c5da601 //log(1/frcpa(1+17/256))/2 data8 0x3fa1dbd2643d190b //log(1/frcpa(1+18/256))/2 data8 0x3fa2cc7284fe5f1c //log(1/frcpa(1+1...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhf.S
241
300
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:8
data8 0x3fb8ab47d5f5a310 //log(1/frcpa(1+54/256))/2 data8 0x3fb91fe49096581b //log(1/frcpa(1+55/256))/2 data8 0x3fb981634011aa75 //log(1/frcpa(1+56/256))/2 data8 0x3fb9f6c407089664 //log(1/frcpa(1+57/256))/2 data8 0x3fba58e729348f43 //log(1/frcpa(1+58/256))/2 data8 0x3fbabb55c31693ad //log(1/frcpa(1+5...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhf.S
281
340
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:9
data8 0x3fc419b423d5e8c7 //log(1/frcpa(1+94/256))/2 data8 0x3fc44591e0539f49 //log(1/frcpa(1+95/256))/2 data8 0x3fc47c9175b6f0ad //log(1/frcpa(1+96/256))/2 data8 0x3fc4a8b341552b09 //log(1/frcpa(1+97/256))/2 data8 0x3fc4d4f3908901a0 //log(1/frcpa(1+98/256))/2 data8 0x3fc501528da1f968 //log(1/frcpa(1+9...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhf.S
321
380
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:10
data8 0x3fcb015b3eb1e790 //log(1/frcpa(1+134/256))/2 data8 0x3fcb323a3a635948 //log(1/frcpa(1+135/256))/2 data8 0x3fcb56fa04462909 //log(1/frcpa(1+136/256))/2 data8 0x3fcb881aa659bc93 //log(1/frcpa(1+137/256))/2 data8 0x3fcbad0bef3db165 //log(1/frcpa(1+138/256))/2 data8 0x3fcbd21297781c2f //log(1/frcp...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhf.S
361
420
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:11
data8 0x3fd0a10074cf9019 //log(1/frcpa(1+174/256))/2 data8 0x3fd0b5343a234477 //log(1/frcpa(1+175/256))/2 data8 0x3fd0c974c89431ce //log(1/frcpa(1+176/256))/2 data8 0x3fd0ddc2305b9886 //log(1/frcpa(1+177/256))/2 data8 0x3fd0eb524bafc918 //log(1/frcpa(1+178/256))/2 data8 0x3fd0ffb54213a476 //log(1/frcp...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhf.S
401
460
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:12
data8 0x3fd37c299f3c366a //log(1/frcpa(1+214/256))/2 data8 0x3fd38ae2171976e7 //log(1/frcpa(1+215/256))/2 data8 0x3fd399a157a603e7 //log(1/frcpa(1+216/256))/2 data8 0x3fd3afccfe77b9d1 //log(1/frcpa(1+217/256))/2 data8 0x3fd3be9d503533b5 //log(1/frcpa(1+218/256))/2 data8 0x3fd3cd7480b4a8a3 //log(1/frcp...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhf.S
441
500
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:13
data8 0x3fd6164bfa7cc06b //log(1/frcpa(1+254/256))/2 data8 0x3fd62643fecf9743 //log(1/frcpa(1+255/256))/2 LOCAL_OBJECT_END(atanhf_data2) .section .text GLOBAL_LIBM_ENTRY(atanhf) { .mfi getf.exp rArgSExpb = f8 fclass.m p9,p0 = f8, 0x0b // is arg denormal ? mov rExpbM...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhf.S
481
540
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:14
// Return here if x=unorm and not denorm { .mfi ldfpd fP3, fP2 = [DataPtr], 16 fma.s1 fX2 = f8, f8, f0 // x^2 nop.i 0 } { .mfb nop.m 0 (p7) fma.s.s0 f8 = f8,f1,f8 // NaN or +/-0 (p7) br.ret.spnt b0 } ;; { .mfi ldfpd fP1, fHa...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhf.S
521
580
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:15
} ;; { .mfb getf.sig rSigp = fOnePx (p8) fma.s.s0 f8 = fX2, f8, f8 // x + x^3 (p8) br.ret.spnt b0 // Exit for MAX_DENORM_ABS < |x| < 2^-20 } ;; { .mfi ldfd fLog2 = [DataPtr], 16 fms.s1 fRm = fRcpM, fOneMx, f1 // rm = rcpm * (1 - x) - 1 nop.i ...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhf.S
561
620
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:16
{ .mmi ldfd fLogTm = [RcpTablePtrM] shladd RcpTablePtrP = rIndp, 3, DataPtr nop.i 0 } ;; { .mfi ldfd fLogTp = [RcpTablePtrP] fma.s1 fRm2 = fRm, fRm, f0 // rm^2 nop.i 0 } { .mfi nop.m 0 fma.s1 fP32m = fP3,...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhf.S
601
660
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:17
} ;; { .mfi nop.m 0 fcvt.xf fNm = fN4CvtM nop.i 0 } { .mfi nop.m 0 fcvt.xf fNp = fN4CvtP nop.i 0 } ;; { .mfi nop.m 0 // (P3*rm + P2)*rm^2 + (P1*rm + 1) fma.s1 fP32m = fP32m, fRm2, fP10m nop.i ...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhf.S
641
700
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:18
} ;; { .mfi nop.m 0 // ((P3*rm + P2)*rm^2 + (P3*rm + 1))*0.5*rm + (Nm*ln(2)/2 + Tm/2) fma.d.s1 fP32m = fP32m, fRm, fLogTm nop.i 0 } { .mfi nop.m 0 // ((P3*rp + P2)*rp^2 + (P3*rp + 1))*0.5*rp + (Np*ln(2)/2 + Tp/2) fma.d.s1 fP32p = fP32p, fRp, f...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhf.S
681
740
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:19
;; .pred.rel "mutex",p6,p7 { .mfi nop.m 0 (p6) fnma.s.s0 f8 = f8,f8,f8 // Result x-x^2 if x=-denorm nop.i 0 } { .mfb nop.m 0 (p7) fma.s.s0 f8 = f8,f8,f8 // Result x+x^2 if x=+denorm br.ret.spnt b0 // Ex...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhf.S
721
780
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:20
(p7) mov atanh_GR_tag = 133 (p7) frcpa.s0 f8, p0 = f0, f0 // Get QNaN, and raise invalid nop.i 0 } ;; // Set error tag and result, and raise Z flag if |x| = 1.0 { .mfi nop.m 0 (p6) frcpa.s0 fRm, p0 = f1, f0 // Get inf, and raise Z flag nop.i ...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhf.S
761
820
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:21
{ .mmi stfs [GR_Parameter_Y] = f1,16 // STORE Parameter 2 on stack add GR_Parameter_X = 16,sp // Parameter 1 address .save b0, GR_SAVE_B0 mov GR_SAVE_B0=b0 // Save b0 };; .body { .mib stfs [GR_Parameter_X] = f10 // STORE Parameter 1 on stack ...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhf.S
801
845
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:4
// Nfloat = float(n) where n is the true unbiased exponent // pre-index = f_1f_2....f_8 // index = pre_index * 16 // get the dxt table entry at index + offset = T // // result = (T + Nfloat * log(2)) + rseries // // The T table is calculated as follows // Form x_k = 1 + k/2^8 where k goes from 0... 255 // y_k = f...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
aa1142c593447b433208a79bd5a95095cd5dd892
github
libc
https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_atanhf.S
121
180
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:5
rExpbm = r22 rExpbp = r23 rSigm = r24 rSigp = r25 rNm = r26 rNp = r27 rIndm = r28 rIndp = r29 GR_SAVE_B0 = r33 GR_SAVE_GP = r34 GR_SAVE_PFS = r35 GR_Paramet...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
aa1142c593447b433208a79bd5a95095cd5dd892
github
libc
https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_atanhf.S
161
220
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:6
fP10m = f53 fP10p = f54 fX2 = f55 fP3 = f56 fP2 = f57 fP1 = f58 fHalf = f59 // Data tables //============================================================== RODATA .align 16 LOCAL_OBJECT_START(at...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
aa1142c593447b433208a79bd5a95095cd5dd892
github
libc
https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_atanhf.S
201
260
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:7
data8 0x3f9a6b8abe73af4c //log(1/frcpa(1+13/256))/2 data8 0x3f9c441e06f72a9e //log(1/frcpa(1+14/256))/2 data8 0x3f9e1e6713606d07 //log(1/frcpa(1+15/256))/2 data8 0x3f9ffa6911ab9301 //log(1/frcpa(1+16/256))/2 data8 0x3fa0ec139c5da601 //log(1/frcpa(1+17/256))/2 data8 0x3fa1dbd2643d190b //log(1/frcpa(1+1...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
aa1142c593447b433208a79bd5a95095cd5dd892
github
libc
https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_atanhf.S
241
300
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:8
data8 0x3fb84a6b759f512f //log(1/frcpa(1+53/256))/2 data8 0x3fb8ab47d5f5a310 //log(1/frcpa(1+54/256))/2 data8 0x3fb91fe49096581b //log(1/frcpa(1+55/256))/2 data8 0x3fb981634011aa75 //log(1/frcpa(1+56/256))/2 data8 0x3fb9f6c407089664 //log(1/frcpa(1+57/256))/2 data8 0x3fba58e729348f43 //log(1/frcpa(1+5...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
aa1142c593447b433208a79bd5a95095cd5dd892
github
libc
https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_atanhf.S
281
340
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:9
data8 0x3fc3edf463c1683e //log(1/frcpa(1+93/256))/2 data8 0x3fc419b423d5e8c7 //log(1/frcpa(1+94/256))/2 data8 0x3fc44591e0539f49 //log(1/frcpa(1+95/256))/2 data8 0x3fc47c9175b6f0ad //log(1/frcpa(1+96/256))/2 data8 0x3fc4a8b341552b09 //log(1/frcpa(1+97/256))/2 data8 0x3fc4d4f3908901a0 //log(1/frcpa(1+9...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
aa1142c593447b433208a79bd5a95095cd5dd892
github
libc
https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_atanhf.S
321
380
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:10
data8 0x3fcadccc6fdf6a81 //log(1/frcpa(1+133/256))/2 data8 0x3fcb015b3eb1e790 //log(1/frcpa(1+134/256))/2 data8 0x3fcb323a3a635948 //log(1/frcpa(1+135/256))/2 data8 0x3fcb56fa04462909 //log(1/frcpa(1+136/256))/2 data8 0x3fcb881aa659bc93 //log(1/frcpa(1+137/256))/2 data8 0x3fcbad0bef3db165 //log(1/frcp...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
aa1142c593447b433208a79bd5a95095cd5dd892
github
libc
https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_atanhf.S
361
420
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:11
data8 0x3fd08cd9687e7b0e //log(1/frcpa(1+173/256))/2 data8 0x3fd0a10074cf9019 //log(1/frcpa(1+174/256))/2 data8 0x3fd0b5343a234477 //log(1/frcpa(1+175/256))/2 data8 0x3fd0c974c89431ce //log(1/frcpa(1+176/256))/2 data8 0x3fd0ddc2305b9886 //log(1/frcpa(1+177/256))/2 data8 0x3fd0eb524bafc918 //log(1/frcp...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
aa1142c593447b433208a79bd5a95095cd5dd892
github
libc
https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_atanhf.S
401
460
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:12
data8 0x3fd36621961a6a99 //log(1/frcpa(1+213/256))/2 data8 0x3fd37c299f3c366a //log(1/frcpa(1+214/256))/2 data8 0x3fd38ae2171976e7 //log(1/frcpa(1+215/256))/2 data8 0x3fd399a157a603e7 //log(1/frcpa(1+216/256))/2 data8 0x3fd3afccfe77b9d1 //log(1/frcpa(1+217/256))/2 data8 0x3fd3be9d503533b5 //log(1/frcp...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
aa1142c593447b433208a79bd5a95095cd5dd892
github
libc
https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_atanhf.S
441
500
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:13
data8 0x3fd6065bea385926 //log(1/frcpa(1+253/256))/2 data8 0x3fd6164bfa7cc06b //log(1/frcpa(1+254/256))/2 data8 0x3fd62643fecf9743 //log(1/frcpa(1+255/256))/2 LOCAL_OBJECT_END(atanhf_data2) .section .text GLOBAL_LIBM_ENTRY(atanhf) { .mfi getf.exp rArgSExpb = f8 fclass.m p9,p0 = f8, 0x0...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
aa1142c593447b433208a79bd5a95095cd5dd892
github
libc
https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_atanhf.S
481
540
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:14
ATANH_COMMON: // Return here if x=unorm and not denorm { .mfi ldfpd fP3, fP2 = [DataPtr], 16 fma.s1 fX2 = f8, f8, f0 // x^2 nop.i 0 } { .mfb nop.m 0 (p7) fma.s.s0 f8 = f8,f1,f8 // NaN or +/-0 (p7) br.ret.spnt b0 } ;; { .mfi ldfpd ...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
aa1142c593447b433208a79bd5a95095cd5dd892
github
libc
https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_atanhf.S
521
580
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:15
(p6) br.cond.spnt atanhf_ge_one } ;; { .mfb getf.sig rSigp = fOnePx (p8) fma.s.s0 f8 = fX2, f8, f8 // x + x^3 (p8) br.ret.spnt b0 // Exit for MAX_DENORM_ABS < |x| < 2^-20 } ;; { .mfi ldfd fLog2 = [DataPtr], 16 fms.s1 fRm = fRcpM, fOneMx, f1 // rm = r...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
aa1142c593447b433208a79bd5a95095cd5dd892
github
libc
https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_atanhf.S
561
620
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:16
{ .mmi ldfd fLogTm = [RcpTablePtrM] shladd RcpTablePtrP = rIndp, 3, DataPtr nop.i 0 } ;; { .mfi ldfd fLogTp = [RcpTablePtrP] fma.s1 fRm2 = fRm, fRm, f0 // rm^2 nop.i 0 } { .mfi nop.m 0 fma.s1 fP32m = fP3,...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
aa1142c593447b433208a79bd5a95095cd5dd892
github
libc
https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_atanhf.S
601
660
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:17
nop.i 0 } ;; { .mfi nop.m 0 fcvt.xf fNm = fN4CvtM nop.i 0 } { .mfi nop.m 0 fcvt.xf fNp = fN4CvtP nop.i 0 } ;; { .mfi nop.m 0 // (P3*rm + P2)*rm^2 + (P1*rm + 1) fma.s1 fP32m = fP32m, fRm2, fP10m ...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
aa1142c593447b433208a79bd5a95095cd5dd892
github
libc
https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_atanhf.S
641
700
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:18
nop.i 0 } ;; { .mfi nop.m 0 // ((P3*rm + P2)*rm^2 + (P3*rm + 1))*0.5*rm + (Nm*ln(2)/2 + Tm/2) fma.d.s1 fP32m = fP32m, fRm, fLogTm nop.i 0 } { .mfi nop.m 0 // ((P3*rp + P2)*rp^2 + (P3*rp + 1))*0.5*rp + (Np*ln(2)/2 + Tp/2) fma.d.s1 fP32p...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
aa1142c593447b433208a79bd5a95095cd5dd892
github
libc
https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_atanhf.S
681
740
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:19
} ;; .pred.rel "mutex",p6,p7 { .mfi nop.m 0 (p6) fnma.s.s0 f8 = f8,f8,f8 // Result x-x^2 if x=-denorm nop.i 0 } { .mfb nop.m 0 (p7) fma.s.s0 f8 = f8,f8,f8 // Result x+x^2 if x=+denorm br.ret.spnt b0 // ...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
aa1142c593447b433208a79bd5a95095cd5dd892
github
libc
https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_atanhf.S
721
780
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:20
{ .mfi (p7) mov atanh_GR_tag = 133 (p7) frcpa.s0 f8, p0 = f0, f0 // Get QNaN, and raise invalid nop.i 0 } ;; // Set error tag and result, and raise Z flag if |x| = 1.0 { .mfi nop.m 0 (p6) frcpa.s0 fRm, p0 = f1, f0 // Get inf, and raise Z flag nop....
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
aa1142c593447b433208a79bd5a95095cd5dd892
github
libc
https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_atanhf.S
761
820
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:21
};; { .mmi stfs [GR_Parameter_Y] = f1,16 // STORE Parameter 2 on stack add GR_Parameter_X = 16,sp // Parameter 1 address .save b0, GR_SAVE_B0 mov GR_SAVE_B0=b0 // Save b0 };; .body { .mib stfs [GR_Parameter_X] = f10 // STORE Parameter 1 on sta...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
aa1142c593447b433208a79bd5a95095cd5dd892
github
libc
https://github.com/bminor/glibc/blob/aa1142c593447b433208a79bd5a95095cd5dd892/sysdeps/ia64/fpu/e_atanhf.S
801
846
bminor/glibc:sysdeps/ia64/fpu/e_atanhf.S:20
{ .mfi (p7) mov atanh_GR_tag = 133 (p7) frcpa.s0 f8, p0 = f0, f0 // Get QNaN, and raise invalid nop.i 0 } ;; // Set error tag and result, and raise Z flag if |x| = 1.0 { .mfi nop.m 0 (p6) frcpa.s0 fRm, p0 = f1, f0 // Get inf, and raise Z flag nop....
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhf.S
LGPL-2.1
890b7a4b33d482b5c768ab47d70758b80227e9bc
github
libc
https://github.com/bminor/glibc/blob/890b7a4b33d482b5c768ab47d70758b80227e9bc/sysdeps/ia64/fpu/e_atanhf.S
761
820
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:5
// // Step 1: Argument Reduction // ------ // Based on S_hi, obtain G_1, G_2, G_3 from a table and calculate // // G := G_1 * G_2 * G_3 // r := (G * S_hi - 1) + G * S_lo // // These G_j's have the property that the product is exactly // representable and that |r| < 2^(-12) as a result. // // ...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhl.S
161
220
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:6
data8 0xAAAAAAAAAAAAAAAA,0x00003FFD // C3 data4 0x3f000000 // 1/2 data4 0x00000000 // pad data4 0x00000000 data4 0x00000000 LOCAL_OBJECT_END(Constants_TaylorSeries) LOCAL_OBJECT_START(Constants_Q) data4 0x00000000,0xB1721800,0x00003FFE,0x00000000 // log2_hi data4 0x4361C4C6...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhl.S
201
260
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:7
data8 0x0000000000000000 data4 0x3F70F0F0,0x3D785196 data8 0x3DA163A6617D741C data4 0x3F638E38,0x3DF13843 data8 0x3E2C55E6CBD3D5BB data4 0x3F579430,0x3E2FF9A0 data8 0xBE3EB0BFD86EA5E7 data4 0x3F4CCCC8,0x3E647FD6 data8 0x3E2E6A8C86B12760 data4 0x3F430C30,0x3E8B3AE7 data8 0x3E47574C5C0739BA data4 0x3F3A2E88,0...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhl.S
241
300
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:8
data4 0x00007D8D data4 0x00007D12 data4 0x00007C98 data4 0x00007C20 data4 0x00007BA8 data4 0x00007B31 data4 0x00007ABB data4 0x00007A45 data4 0x000079D1 data4 0x0000795D data4 0x000078EB LOCAL_OBJECT_END(Constants_Z_2) // G2 and H2 - IEEE single and h2 - IEEE double LOCAL_OBJECT_START(Constants_G_H_h2) data...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhl.S
281
340
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:9
data8 0xBE139A06BF72A8CD data4 0x3F73A0D0,0x3D4AE46F data8 0x3E1D9202F8FBA6CF data4 0x3F72B9D0,0x3D5A1756 data8 0xBE1DCCC4BA796223 data4 0x3F71D488,0x3D693B9D data8 0xBE049391B6B7C239 LOCAL_OBJECT_END(Constants_G_H_h2) // G3 and H3 - IEEE single and h3 - IEEE double LOCAL_OBJECT_START(Constants_G_H_h3) data4 0...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhl.S
321
380
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:10
data8 0x3DC6E17B4F2083D3 data4 0x3F7F8438,0x3AF7CBED data8 0x3DAE314B811D4394 data4 0x3F7F7C40,0x3B03E1F3 data8 0xBDD46F21B08F2DB1 data4 0x3F7F7448,0x3B0BDE2F data8 0xBDDC30A46D34522B data4 0x3F7F6C50,0x3B13DAAA data8 0x3DCB0070B1F473DB data4 0x3F7F6458,0x3B1BD766 data8 0xBDD65DDC6AD282FD data4 0x3F7F5C68,0...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhl.S
361
420
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:11
FR_C17 = f50 FR_C15 = f51 FR_C13 = f52 FR_C11 = f53 FR_C9 = f54 FR_C7 = f55 FR_C5 = f56 FR_C3 = f57 FR_x2 = f58 FR_x3 = f59 FR_x4 = f60 FR_x8 = f61 FR_Rcp ...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhl.S
401
460
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:12
FR_X = f48 FR_BB = f48 FR_X_lo = f49 FR_G = f50 FR_Y_hi = f51 FR_H = f51 FR_h = f52 FR_G2 = f53 FR_H2 = f54 FR_h2 = f55 FR_G3 = f56 FR_H3 = f57 FR_h3 ...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhl.S
441
500
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:13
FR_05r = f72 FR_Half = f73 FR_Arg_X = f50 FR_Arg_Y = f0 FR_RESULT = f8 // General Purpose Registers GR_ad_05 = r33 GR_Index1 = r34 GR_ArgExp = r34 GR_Index2 = r35 GR_ExpMask = r35 GR_NearZeroBound = r36 GR...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhl.S
481
540
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:14
// Added for unwind support // GR_SAVE_PFS = r46 GR_SAVE_B0 = r47 GR_SAVE_GP = r48 GR_Parameter_X = r49 GR_Parameter_Y = r50 GR_Parameter_RESULT = r51 GR_Parameter_TAG = r52 .section .text GLOBAL_LIBM_ENTRY(atanhl) { .mfi alloc r32 = ar.pfs,0,17,4,0 fnma.s1...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhl.S
521
580
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:15
{ .mfi nop.m 0 fma.s1 FR_x2 = f8,f8,f0 nop.i 0 };; { .mfi add GR_ad_z_1 = 0x0F0,GR_ad_taylor fclass.m p9,p0 = f8,0x0a // is arg -denormal ? add GR_ad_taylor_2 = 0x010,GR_ad_taylor } { .mfi add GR_ad_05 = 0x080,GR_ad_tayl...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhl.S
561
620
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:16
{ .mfb ldfe FR_C9 = [GR_ad_taylor],32 (p10) fma.s0 f8 = f8,f8,f8 // +denormal (p10) br.ret.spnt b0 // exit for +denormal };; { .mfi ldfe FR_C7 = [GR_ad_taylor_2],32 (p6) frcpa.s1 FR_Yn,p11 = f1,FR_Bn // y = frcpa(b) and GR_ArgExp = GR_ArgExp,GR_E...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhl.S
601
660
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:17
};; { .mfi nop.m 0 (p6) fnma.s1 FR_E0 = FR_Yn,FR_Bn,f1 // e = 1-b*y nop.i 0 } { .mfb nop.m 0 (p6) fma.s1 FR_Y0 = FR_Yn,f1,f0 (p8) br.cond.spnt atanhl_gt_one // |arg| > 1 };; { .mfi nop.m 0 (p7) fnma.s1 FR_E0 = FR_Yp,FR_Bp,f1 nop.i ...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhl.S
641
700
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:18
} { .mfi nop.m 0 fma.s1 FR_E1 = FR_E0,FR_E0,f0 // e1 = e^2 nop.i 0 };; { .mfb nop.m 0 // Return generated NaN or other value for unsupported values. (p10) fma.s0 f8 = f8, f0, f0 (p10) br.ret.spnt b0 };; { .mfi nop.m 0 fma.s1 F...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhl.S
681
740
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:19
nop.i 0 } { .mfi nop.m 0 fma.s1 FR_X = FR_R0,FR_Y2,FR_Q0 // x = q+r*y2 nop.i 0 };; { .mfi nop.m 0 fma.s1 FR_Z = FR_X,f1,f1 // x+1 nop.i 0 };; { .mfi nop.m 0 (p6) fnma.s1 FR_Half = FR_Half,f1,f0 // sign(arg)/2 ...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhl.S
721
780
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:20
add GR_ad_tbl_3 = 0x280,GR_ad_z_1 // point to Constants_G_H_h3 nop.f 0 nop.i 0 };; { .mfi shladd GR_ad_z_1 = GR_Index1,2,GR_ad_z_1 // point to Z_1 nop.f 0 extr.u GR_X_0 = GR_signif,49,15 // get high 15 bits of significand };; { .mfi ld4...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhl.S
761
820
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:21
// For performance,don't use result of pmpyshr2.u for 4 cycles. // { .mfi ldfe FR_log2_lo = [GR_ad_q],16 // load log2_lo nop.f 0 sub GR_N = GR_N,GR_Bias };; { .mfi ldfe FR_Q4 = [GR_ad_q],16 // load Q4 fms.s1 FR_S_lo = FR_AA,f1,FR_Z // form S_l...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhl.S
801
860
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:22
fma.s1 FR_S_lo = FR_S_lo,f1,FR_BB // S_lo = S_lo + BB nop.i 0 } { .mfi setf.exp FR_2_to_minus_N = GR_minus_N // form 2^(-N) fma.s1 FR_X_lo = FR_R1,FR_Y3,f0 // x_lo = r1*y3 nop.i 0 };; { .mfi nop.m 0 nop.f 0 pmpyshr2.u GR_X_2...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhl.S
841
900
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:23
{ .mfi nop.m 0 nop.f 0 extr.u GR_Index3 = GR_X_2,1,5 // extract bits 1-5 of X_2 } { .mfi nop.m 0 fma.s1 FR_S_lo = FR_S_lo,f1,FR_X_lo // S_lo = S_lo + Arg_lo nop.i 0 };; { .mfi shladd GR_ad_tbl_3 = GR_Index3,4,GR_ad_tbl_3 // ...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhl.S
881
940
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:24
};; { .mfi nop.m 0 // S_lo = S_lo * 2^(-N) fma.s1 FR_S_lo = FR_S_lo,FR_2_to_minus_N,f0 nop.i 0 };; { .mfi nop.m 0 fmpy.s1 FR_G = FR_G,FR_G3 // G = (G_1 * G_2) * G_3 nop.i 0 } { .mfi nop.m 0 fadd.s1 FR_H = FR...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhl.S
921
980
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:25
fma.s1 FR_r = FR_G,FR_S_lo,FR_r // r = G * S_lo + (G * S_hi - 1) nop.i 0 };; { .mfi nop.m 0 fma.s1 FR_poly_lo = FR_r,FR_Q4,FR_Q3 // poly_lo = r * Q4 + Q3 nop.i 0 } { .mfi nop.m 0 fmpy.s1 FR_rsq = FR_r,FR_r // rsq = r * r nop.i...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhl.S
961
1,020
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:26
};; { .mfi nop.m 0 // Y_lo = poly_hi + poly_lo/2 fma.s0 FR_Y_lo = FR_poly_lo,FR_Half,FR_poly_hi nop.i 0 };; { .mfb nop.m 0 // Result = arctanh(x) = Y_hi/2 + Y_lo fma.s0 f8 = FR_Y_hi,FR_Half,FR_Y_lo br.ret.sptk b0 };; // Taylor's ser...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhl.S
1,001
1,060
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:27
} { .mfi nop.m 0 fma.s1 FR_C5 = FR_C5,FR_x2,FR_C3 nop.i 0 };; { .mfi nop.m 0 fma.s1 FR_x8 = FR_x4,FR_x4,f0 nop.i 0 };; { .mfi nop.m 0 fma.s1 FR_C17 = FR_C17,FR_x4,FR_C13 nop.i 0 };; { .mfi no...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhl.S
1,041
1,100
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:28
fmerge.s FR_Arg_X = f8, f8 nop.i 0 };; { .mfb mov GR_Parameter_TAG = 130 fmerge.s FR_RESULT = f8,FR_Rcp // result is +-inf br.cond.sptk __libm_error_region // exit if |x| = 1.0 };; atanhl_gt_one: { .mfi nop.m 0 fmerge.s FR_Arg_X = f8, f8 ...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhl.S
1,081
1,140
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:29
add GR_Parameter_X = 16,sp // Parameter 1 address .save b0,GR_SAVE_B0 mov GR_SAVE_B0=b0 // Save b0 };; .body { .mib stfe [GR_Parameter_X] = FR_Arg_X // Store Parameter 1 on stack add GR_Parameter_RESULT = 0,GR_Parameter_Y nop.b 0 ...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
30891f35fa7da832b66d80d0807610df361851f3
github
libc
https://github.com/bminor/glibc/blob/30891f35fa7da832b66d80d0807610df361851f3/sysdeps/ia64/fpu/e_atanhl.S
1,121
1,156
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:5
// !-----------------------------------------------------------------------! // // Step 1: Argument Reduction // ------ // Based on S_hi, obtain G_1, G_2, G_3 from a table and calculate // // G := G_1 * G_2 * G_3 // r := (G * S_hi - 1) + G * S_lo // // These G_j's have the property that the pro...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
3a327316ad615f7e4264d3e13d23052d9dc84694
github
libc
https://github.com/bminor/glibc/blob/3a327316ad615f7e4264d3e13d23052d9dc84694/sysdeps/ia64/fpu/e_atanhl.S
161
220
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:6
data8 0xCCCCCCCCCCCCCCCD,0x00003FFC // C5 data8 0xAAAAAAAAAAAAAAAA,0x00003FFD // C3 data4 0x3f000000 // 1/2 data4 0x00000000 // pad data4 0x00000000 data4 0x00000000 LOCAL_OBJECT_END(Constants_TaylorSeries) LOCAL_OBJECT_START(Constants_Q) data4 0x00000000,0xB1721800,0x00003...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
3a327316ad615f7e4264d3e13d23052d9dc84694
github
libc
https://github.com/bminor/glibc/blob/3a327316ad615f7e4264d3e13d23052d9dc84694/sysdeps/ia64/fpu/e_atanhl.S
201
260
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:7
data4 0x3F800000,0x00000000 data8 0x0000000000000000 data4 0x3F70F0F0,0x3D785196 data8 0x3DA163A6617D741C data4 0x3F638E38,0x3DF13843 data8 0x3E2C55E6CBD3D5BB data4 0x3F579430,0x3E2FF9A0 data8 0xBE3EB0BFD86EA5E7 data4 0x3F4CCCC8,0x3E647FD6 data8 0x3E2E6A8C86B12760 data4 0x3F430C30,0x3E8B3AE7 data8 0x3E47574...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
3a327316ad615f7e4264d3e13d23052d9dc84694
github
libc
https://github.com/bminor/glibc/blob/3a327316ad615f7e4264d3e13d23052d9dc84694/sysdeps/ia64/fpu/e_atanhl.S
241
300
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:8
data4 0x00007E08 data4 0x00007D8D data4 0x00007D12 data4 0x00007C98 data4 0x00007C20 data4 0x00007BA8 data4 0x00007B31 data4 0x00007ABB data4 0x00007A45 data4 0x000079D1 data4 0x0000795D data4 0x000078EB LOCAL_OBJECT_END(Constants_Z_2) // G2 and H2 - IEEE single and h2 - IEEE double LOCAL_OBJECT_START(Cons...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
3a327316ad615f7e4264d3e13d23052d9dc84694
github
libc
https://github.com/bminor/glibc/blob/3a327316ad615f7e4264d3e13d23052d9dc84694/sysdeps/ia64/fpu/e_atanhl.S
281
340
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:9
data4 0x3F748988,0x3D3BA322 data8 0xBE139A06BF72A8CD data4 0x3F73A0D0,0x3D4AE46F data8 0x3E1D9202F8FBA6CF data4 0x3F72B9D0,0x3D5A1756 data8 0xBE1DCCC4BA796223 data4 0x3F71D488,0x3D693B9D data8 0xBE049391B6B7C239 LOCAL_OBJECT_END(Constants_G_H_h2) // G3 and H3 - IEEE single and h3 - IEEE double LOCAL_OBJECT_STA...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
3a327316ad615f7e4264d3e13d23052d9dc84694
github
libc
https://github.com/bminor/glibc/blob/3a327316ad615f7e4264d3e13d23052d9dc84694/sysdeps/ia64/fpu/e_atanhl.S
321
380
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:10
data4 0x3F7F8C30,0x3AE7D474 data8 0x3DC6E17B4F2083D3 data4 0x3F7F8438,0x3AF7CBED data8 0x3DAE314B811D4394 data4 0x3F7F7C40,0x3B03E1F3 data8 0xBDD46F21B08F2DB1 data4 0x3F7F7448,0x3B0BDE2F data8 0xBDDC30A46D34522B data4 0x3F7F6C50,0x3B13DAAA data8 0x3DCB0070B1F473DB data4 0x3F7F6458,0x3B1BD766 data8 0xBDD65DD...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
3a327316ad615f7e4264d3e13d23052d9dc84694
github
libc
https://github.com/bminor/glibc/blob/3a327316ad615f7e4264d3e13d23052d9dc84694/sysdeps/ia64/fpu/e_atanhl.S
361
420
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:11
// Floating Point Registers FR_C17 = f50 FR_C15 = f51 FR_C13 = f52 FR_C11 = f53 FR_C9 = f54 FR_C7 = f55 FR_C5 = f56 FR_C3 = f57 FR_x2 = f58 FR_x3 = f59 FR_x4 = f60 FR_x8...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
3a327316ad615f7e4264d3e13d23052d9dc84694
github
libc
https://github.com/bminor/glibc/blob/3a327316ad615f7e4264d3e13d23052d9dc84694/sysdeps/ia64/fpu/e_atanhl.S
401
460
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:12
FR_Yn = f47 FR_X = f48 FR_BB = f48 FR_X_lo = f49 FR_G = f50 FR_Y_hi = f51 FR_H = f51 FR_h = f52 FR_G2 = f53 FR_H2 = f54 FR_h2 = f55 FR_G3 = f56 FR_H3 ...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
3a327316ad615f7e4264d3e13d23052d9dc84694
github
libc
https://github.com/bminor/glibc/blob/3a327316ad615f7e4264d3e13d23052d9dc84694/sysdeps/ia64/fpu/e_atanhl.S
441
500
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:13
FR_rsq = f71 FR_05r = f72 FR_Half = f73 FR_Arg_X = f50 FR_Arg_Y = f0 FR_RESULT = f8 // General Purpose Registers GR_ad_05 = r33 GR_Index1 = r34 GR_ArgExp = r34 GR_Index2 = r35 GR_ExpMask = r35 GR...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
3a327316ad615f7e4264d3e13d23052d9dc84694
github
libc
https://github.com/bminor/glibc/blob/3a327316ad615f7e4264d3e13d23052d9dc84694/sysdeps/ia64/fpu/e_atanhl.S
481
540
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:14
// // Added for unwind support // GR_SAVE_PFS = r46 GR_SAVE_B0 = r47 GR_SAVE_GP = r48 GR_Parameter_X = r49 GR_Parameter_Y = r50 GR_Parameter_RESULT = r51 GR_Parameter_TAG = r52 .section .text GLOBAL_LIBM_ENTRY(atanhl) { .mfi alloc r32 = ar.pfs,0,17,4,0 fnma...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
3a327316ad615f7e4264d3e13d23052d9dc84694
github
libc
https://github.com/bminor/glibc/blob/3a327316ad615f7e4264d3e13d23052d9dc84694/sysdeps/ia64/fpu/e_atanhl.S
521
580
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:15
} { .mfi nop.m 0 fma.s1 FR_x2 = f8,f8,f0 nop.i 0 };; { .mfi add GR_ad_z_1 = 0x0F0,GR_ad_taylor fclass.m p9,p0 = f8,0x0a // is arg -denormal ? add GR_ad_taylor_2 = 0x010,GR_ad_taylor } { .mfi add GR_ad_05 = 0x080,GR_ad_ta...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
3a327316ad615f7e4264d3e13d23052d9dc84694
github
libc
https://github.com/bminor/glibc/blob/3a327316ad615f7e4264d3e13d23052d9dc84694/sysdeps/ia64/fpu/e_atanhl.S
561
620
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:16
} { .mfb ldfe FR_C9 = [GR_ad_taylor],32 (p10) fma.s0 f8 = f8,f8,f8 // +denormal (p10) br.ret.spnt b0 // exit for +denormal };; { .mfi ldfe FR_C7 = [GR_ad_taylor_2],32 (p6) frcpa.s1 FR_Yn,p11 = f1,FR_Bn // y = frcpa(b) and GR_ArgExp = GR_ArgExp,GR...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
3a327316ad615f7e4264d3e13d23052d9dc84694
github
libc
https://github.com/bminor/glibc/blob/3a327316ad615f7e4264d3e13d23052d9dc84694/sysdeps/ia64/fpu/e_atanhl.S
601
660
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:17
nop.i 0 };; { .mfi nop.m 0 (p6) fnma.s1 FR_E0 = FR_Yn,FR_Bn,f1 // e = 1-b*y nop.i 0 } { .mfb nop.m 0 (p6) fma.s1 FR_Y0 = FR_Yn,f1,f0 (p8) br.cond.spnt atanhl_gt_one // |arg| > 1 };; { .mfi nop.m 0 (p7) fnma.s1 FR_E0 = FR_Yp,FR_Bp,f1...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
3a327316ad615f7e4264d3e13d23052d9dc84694
github
libc
https://github.com/bminor/glibc/blob/3a327316ad615f7e4264d3e13d23052d9dc84694/sysdeps/ia64/fpu/e_atanhl.S
641
700
bminor/glibc:sysdeps/ia64/fpu/e_atanhl.S:18
nop.i 0 } { .mfi nop.m 0 fma.s1 FR_E1 = FR_E0,FR_E0,f0 // e1 = e^2 nop.i 0 };; { .mfb nop.m 0 // Return generated NaN or other value for unsupported values. (p10) fma.s0 f8 = f8, f0, f0 (p10) br.ret.spnt b0 };; { .mfi nop.m 0 ...
arm64
intel-like
handwritten
bminor/glibc
sysdeps/ia64/fpu/e_atanhl.S
LGPL-2.1
3a327316ad615f7e4264d3e13d23052d9dc84694
github
libc
https://github.com/bminor/glibc/blob/3a327316ad615f7e4264d3e13d23052d9dc84694/sysdeps/ia64/fpu/e_atanhl.S
681
740