code stringlengths 1 2.01M | repo_name stringlengths 3 62 | path stringlengths 1 267 | language stringclasses 231 values | license stringclasses 13 values | size int64 1 2.01M |
|---|---|---|---|---|---|
.loadmask {
z-index: 100;
position: absolute;
top:0;
left:0;
-moz-opacity: 0.5;
opacity: .50;
filter: alpha(opacity=50);
background-color: #CCC;
width: 100%;
height: 100%;
zoom: 1;
}
.loadmask-msg {
z-index: 20001;
position: absolute;
top: 0;
left: 0;
border:1px solid #6593cf;
background: #c3daf9;
padding:2px;
}
.loadmask-msg div {
padding:5px 10px 5px 25px;
background: #fbfbfb url('../img/loading.gif') no-repeat 5px 5px;
line-height: 16px;
border:1px solid #a3bad9;
color:#222;
font:normal 11px tahoma, arial, helvetica, sans-serif;
cursor:wait;
}
.masked {
overflow: hidden !important;
}
.masked-relative {
position: relative !important;
}
.masked-hidden {
visibility: hidden !important;
} | zytools | trunk/WebContent/css/jquery.loadmask.css | CSS | asf20 | 843 |
/**********************************
Use: Reset Styles for all browsers
***********************************/
body, p, blockquote {
margin: 0;
padding: 0;
}
a img, iframe { border: none; }
/* Headers
------------------------------*/
h1, h2, h3, h4, h5, h6 {
margin: 0;
padding: 0;
font-size: 100%;
}
/* Lists
------------------------------*/
ul, ol, dl, li, dt, dd {
margin: 0;
padding: 0;
}
/* Links
------------------------------*/
a, a:link {}
a:visited {}
a:hover {}
a:active {}
/* Forms
------------------------------*/
form, fieldset {
margin: 0;
padding: 0;
}
fieldset { border: 1px solid #000; }
legend {
padding: 0;
color: #000;
}
input, textarea, select {
margin: 0;
padding: 1px;
font-size: 100%;
font-family: inherit;
}
select { padding: 0; } | zytools | trunk/WebContent/css/reset.css | CSS | asf20 | 790 |
body { font: 76% Arial, Verdana, sans-serif; color: #333; padding: 10px 20px; }
h1 { font-size: 250%; color: #f34105; }
h1 sup { font-size: 50%; }
h2 { color: #f34105; font-size: 175%; }
a { color: #005bd8; }
a:hover { text-decoration: none; }
.hr hr { display: none; }
form { margin: 10px 0; }
table { width: 100%; border-collapse: collapse; margin: 1em 0; }
thead th { background: #f34105; color: #fff; }
tbody th { text-align: left; }
table th, table td { border: 1px solid #ddd; padding: 2px 5px; font-size: 100%; }
pre { font-size: 130%; background: #f7f7f7; padding: 10px 10px; font-weight: bold; }
.odd, .r1 { background: #fff; }
.even, .r2 { background: #eee; }
.r3 { background: #ebebeb; }
.search { font-weight: bold; }
dt { margin-top: 10px; font-weight: bold; }
dd { margin: 0;}
.new { color: #f34105; text-transform: uppercase; font-size: 85%; margin-left: 3px; }
form.quicksearch { padding: 10px; background: #f7f7f7; }
form.quicksearch input { margin-left: 5px; width: 300px; }
form.quicksearch img { vertical-align: middle; margin-left: 5px; }
fieldset { border: 1px solid #ccc;}
form input { font-size: 16px;}
#footer { background: #333; color: #fff; padding: 10px; margin-top: 20px; }
#footer a { color: #fff; }
#footer span { margin: 0 2px; color: #666; }
.github { font-size: 150%; font-weight: bold; }
.github a { background: #fff172; padding: 3px 10px;}
| zytools | trunk/WebContent/css/style.css | CSS | asf20 | 1,384 |
#pager ul.pages {
display:block;
border:none;
text-transform:uppercase;
font-size:10px;
margin:10px 0 50px;
padding:0;
}
#pager ul.pages li {
list-style:none;
float:left;
border:1px solid #ccc;
text-decoration:none;
margin:0 5px 0 0;
padding:5px;
}
#pager ul.pages li:hover {
border:1px solid #003f7e;
}
#pager ul.pages li.pgEmpty {
border:1px solid #eee;
color:#eee;
}
#pager ul.pages li.pgCurrent {
border:1px solid #003f7e;
color:#000;
font-weight:700;
background-color:#eee;
} | zytools | trunk/WebContent/css/Pager.css | CSS | asf20 | 487 |
/**********************************
Name: infoForm Styles
***********************************/
form.infoForm {
width: 1000px;
font-size: 1.0em;
color: #333;
}
form.infoForm label {
color: #333;
width:500px;
height:60px;
}
form.infoForm label.error, label.error {
/* remove the next line when you have trouble in IE6 with labels in list */
color: red;
font-style: italic
}
div.error { display: none; }
input { border: 1px solid gray; }
input.checkbox { border: none }
input:focus { border: 1px dotted black; }
input.error { border: 1px dotted red; }
form.infoForm .gray * { color: gray; } | zytools | trunk/WebContent/css/form.css | CSS | asf20 | 601 |
package com.zhongyi.file;
import java.io.File;
import java.io.FileInputStream;
import java.io.FileNotFoundException;
import java.io.IOException;
import java.io.InputStream;
import java.util.ArrayList;
import java.util.Collection;
import java.util.List;
import org.apache.log4j.Logger;
import org.apache.poi.hssf.usermodel.HSSFWorkbook;
import org.apache.poi.poifs.filesystem.POIFSFileSystem;
import org.apache.poi.ss.usermodel.Cell;
import org.apache.poi.ss.usermodel.DateUtil;
import org.apache.poi.ss.usermodel.Row;
import org.apache.poi.ss.usermodel.Sheet;
import org.apache.poi.ss.usermodel.Workbook;
import org.apache.poi.xssf.usermodel.XSSFWorkbook;
/**
*
* <p>
*
*
* @author <a href="mailto:lysongfie@126.com">Songfei</a>
* @version 1.0,2012-2-25
*/
public class FileReader {
Sheet sheet;
private Workbook wkbook;
private ArrayList<String> worksheets = new ArrayList<String>();
private String fileName;
private boolean isExcel2007;
Logger logger = Logger.getLogger(FileReader.class);
public void loadFile(String fileName) throws IOException{
InputStream is = null;
this.fileName = fileName;
try {
is = new FileInputStream(new File(fileName));
this.loadFile(is);
} catch (FileNotFoundException e) {
e.printStackTrace();
}
}
public void loadFile(InputStream is) throws IOException{
if (wkbook == null){
if (this.isExcel2007){
try {
wkbook = new XSSFWorkbook(is);
} catch (IOException e) {
e.printStackTrace();
}
}else{
POIFSFileSystem excel = null;
try {
excel = new POIFSFileSystem(is);
} catch (Exception e) {
logger.error(
" Not a Valid Excel File : " + fileName);
}
wkbook = new HSSFWorkbook(excel);
int noOfWorksheets = wkbook.getNumberOfSheets();
if (noOfWorksheets != 0) {
for (int count = 0; count < noOfWorksheets; ++count) {
worksheets.add(wkbook.getSheetName(count));
}
}
}
}
}
public void loadWorkSheet(int index){
sheet = wkbook.getSheetAt(index);
}
public Collection<String> getWorkSheets(){
return worksheets;
}
public List<String> getRow() {
List<String> dataList = new ArrayList<String>();
for(Row row : sheet){
for(Cell cell : row){
switch(cell.getCellType()){
case Cell.CELL_TYPE_BOOLEAN:
//得到Boolean对象的方法
dataList.add(String.valueOf(cell.getBooleanCellValue()));
break;
case Cell.CELL_TYPE_NUMERIC:
//先看是否是日期格式
if(DateUtil.isCellDateFormatted(cell)){
//读取日期格式
dataList.add(String.valueOf(cell.getDateCellValue()));
}else{
//读取数字
dataList.add(String.valueOf(cell.getNumericCellValue()));
}
break;
case Cell.CELL_TYPE_FORMULA:
//读取公式
dataList.add(cell.getCellFormula());
break;
case Cell.CELL_TYPE_STRING:
//读取String
dataList.add(cell.getRichStringCellValue().getString());
break;
}
}
}
return dataList;
}
}
| zytools | trunk/src/com/zhongyi/file/FileReader.java | Java | asf20 | 3,909 |
package com.zhongyi.file;
import java.io.File;
import java.io.FileInputStream;
import java.io.FileNotFoundException;
import java.io.IOException;
import java.io.InputStream;
import java.sql.Timestamp;
import org.apache.log4j.Logger;
import org.apache.poi.ss.usermodel.Row;
import org.apache.poi.ss.usermodel.Sheet;
import org.apache.poi.ss.usermodel.Workbook;
import org.apache.poi.xssf.usermodel.XSSFWorkbook;
import com.zhongyi.db.impl.DBManagerImpl;
import com.zhongyi.entity.Company;
import com.zhongyi.entity.Contact;
import com.zhongyi.util.ImportUtil;
import com.zhongyi.util.UUIDGenerator;
public class TestReader {
private static final String filePath = "K:\\中易运维\\信息采集\\201204";
private static Logger logger = Logger.getLogger(TestReader.class);
public static void read(String fileName){
InputStream is = null;
Workbook wkbook = null;
Sheet sheet = null;
Row row = null;
Company corp = null;
Contact contact = null;
String insetCompany = "insert into td_company(id,corp_name,area_id,address,origin_site,home_page,corp_level,corp_type,linker,keyword,create_time,remark) values (?,?,?,?,?,?,?,?,?,?,?,?)";
String insertContact = "insert into td_contact(id,corp_id,contact_info,info_type,remark,create_time) values (?,?,?,?,?,?)";
logger.info("begin to execute : " + fileName);
try {
is = new FileInputStream(fileName);
wkbook = new XSSFWorkbook(is);
sheet = wkbook.getSheetAt(0);
int rowCount = sheet.getLastRowNum();
for (int i = 1; i <= rowCount; i++) {
corp = new Company();
row = sheet.getRow(i);
//判断当前行是否为空行
if(ImportUtil.isRowNull(row)){
break;
}
String corpId = UUIDGenerator.create();
//company message
corp.setId(corpId);
corp.setCorp_type(ImportUtil.getCellValue(row.getCell(1)));
corp.setKeyword(ImportUtil.getCellValue(row.getCell(2)));
corp.setCorp_name(ImportUtil.getCellValue(row.getCell(4)));
corp.setLinker(ImportUtil.getCellValue(row.getCell(5)));
corp.setOrigin_site(ImportUtil.getCellValue(row.getCell(10)));
corp.setCreate_time(new Timestamp(System.currentTimeMillis()));
corp.setRemark(ImportUtil.getCellValue(row.getCell(11)));
insertCompany(insetCompany,corp);
//Email
String value = ImportUtil.getCellValue(row.getCell(6));
String[] vs = null;
if(value != null && value.length() > 0){
vs = value.split("\\|");
for(String v : vs){
contact = new Contact();
contact.setId(UUIDGenerator.create());
contact.setCorp_id(corpId);
contact.setContact_info(v.trim());
contact.setInfo_type("E");
contact.setCreate_time(new Timestamp(System.currentTimeMillis()));
insertContact(insertContact,contact);
}
}
//phone
value = ImportUtil.getCellValue(row.getCell(7));
if(value != null && value.length() > 0){
vs = value.split("\\|");
for(String v : vs){
contact = new Contact();
contact.setId(UUIDGenerator.create());
contact.setCorp_id(corpId);
contact.setContact_info(v.trim());
contact.setInfo_type("P");
contact.setCreate_time(new Timestamp(System.currentTimeMillis()));
insertContact(insertContact,contact);
}
}
//mobile
value = ImportUtil.getCellValue(row.getCell(8));
if(value != null && value.length() > 0){
vs = value.split("\\|");
for(String v : vs){
contact = new Contact();
contact.setId(UUIDGenerator.create());
contact.setCorp_id(corpId);
contact.setContact_info(v.trim());
contact.setInfo_type("M");
contact.setCreate_time(new Timestamp(System.currentTimeMillis()));
insertContact(insertContact,contact);
}
}
//Fax
value = ImportUtil.getCellValue(row.getCell(9));
if(value != null && value.length() > 0){
vs = value.split("\\|");
for(String v : vs){
contact = new Contact();
contact.setId(UUIDGenerator.create());
contact.setCorp_id(corpId);
contact.setContact_info(v.trim());
contact.setInfo_type("F");
contact.setCreate_time(new Timestamp(System.currentTimeMillis()));
insertContact(insertContact,contact);
}
}
}
} catch (FileNotFoundException e) {
logger.error("can not find the source file ... ", e);
} catch (IOException e) {
logger.error("error to load the file by poi ... ", e);
}
logger.info("finish ... ");
}
public static void main(String[] args) {
File dirFile = new File(filePath);
String basePath = dirFile.getAbsolutePath();
if(dirFile.isDirectory()){
String[] files = dirFile.list();
for(String file : files){
read(basePath + File.separator + file);
}
}else{
read(basePath);
}
}
public static void insertCompany(String sql,Company corp){
DBManagerImpl dbManger = new DBManagerImpl();
//id,corp_name,area_id,address,origin_site,home_page,corp_level,corp_type,linker,keyword,create_time,remark
dbManger.insertToDB(sql, new Object[]{corp.getId(),corp.getCorp_name(),corp.getArea_id(),corp.getAdress(),corp.getOrigin_site(),corp.getHome_page(),corp.getCorp_level(),corp.getCorp_type(),corp.getLinker(),corp.getKeyword(),corp.getCreate_time(),corp.getRemark()});
}
public static void insertContact(String sql , Contact contact){
DBManagerImpl dbManger = new DBManagerImpl();
//id,corp_id,contact_info,info_type,remark,create_time
dbManger.insertToDB(sql, new Object[]{contact.getId(),contact.getCorp_id(),contact.getContact_info(),contact.getInfo_type(),contact.getRemark(),contact.getCreate_time()});
}
}
| zytools | trunk/src/com/zhongyi/file/TestReader.java | Java | asf20 | 5,728 |
package com.zhongyi.db.impl;
import java.sql.Connection;
import java.sql.SQLException;
import java.util.List;
import java.util.Map;
import org.apache.commons.dbcp.BasicDataSource;
import org.apache.commons.dbutils.DbUtils;
import org.apache.commons.dbutils.QueryRunner;
import org.apache.commons.dbutils.handlers.BeanListHandler;
import org.apache.commons.dbutils.handlers.MapHandler;
import org.apache.commons.dbutils.handlers.MapListHandler;
import org.apache.log4j.Logger;
import com.zhongyi.db.DBManager;
/**
* 数据库操作类
* <p>
*
*
* @author <a href="mailto:lysongfei@gmail.com">songfei</a>
* @version 1.0, 2012-3-8
*/
public class DBManagerImpl implements DBManager {
/* 注入dbcp数据源 */
public BasicDataSource dataSource;
public void setDataSource(BasicDataSource dataSource) {
this.dataSource = dataSource;
}
public int deleteFromDB(String sql, Object[] params) {
int res = -1;
Connection conn = null;
QueryRunner qRunner = null;
try {
qRunner = new QueryRunner();
conn = dataSource.getConnection();
conn.setAutoCommit(false);
res = qRunner.update(conn,sql, params);
conn.commit();
} catch (SQLException e) {
try {
conn.rollback();
} catch (SQLException e1) {
logger.error("error rollback delete operation ... ", e1);
}
logger.error("error when delete data from database ... ",e);
}finally{
DbUtils.closeQuietly(conn);
}
return res;
}
public int insertToDB(String sql, Object[] params) {
int res = -1;
Connection conn = null;
QueryRunner qRunner = null;
try {
qRunner = new QueryRunner();
conn = dataSource.getConnection();
conn.setAutoCommit(false);
res = qRunner.update(conn,sql, params);
conn.commit();
} catch (SQLException e) {
try {
conn.rollback();
} catch (SQLException e1) {
logger.error("error rollback insert operation ... ", e1);
}
logger.error("error when insert data to database ... ",e);
}finally{
DbUtils.closeQuietly(conn);
}
return res;
}
public List queryForMapList(String sql, Object[] params) {
List mapList = null;
Connection conn = null;
QueryRunner qRunner = null;
try {
qRunner = new QueryRunner();
conn = dataSource.getConnection();
mapList = qRunner.query(conn,sql, new MapListHandler(),params);
} catch (SQLException e) {
logger.error("error when query data from database ... ",e);
}finally{
try {
DbUtils.close(conn);
} catch (SQLException e) {
// TODO Auto-generated catch block
e.printStackTrace();
}
// DbUtils.closeQuietly(conn);
}
return mapList;
}
public <T>List<T> queryForBeanList(String sql, Object[] params,Class<T> entityClass) {
List<T> beanList = null;
Connection conn = null;
QueryRunner qRunner = null;
try {
qRunner = new QueryRunner();
conn = dataSource.getConnection();
beanList = (List<T>) qRunner.query(conn,sql, new BeanListHandler(entityClass), params);
} catch (SQLException e) {
logger.error("error when query data from database ... ",e);
}finally{
DbUtils.closeQuietly(conn);
}
return beanList;
}
@Override
public int updateDB(String sql, Object[] params) {
int res = -1;
Connection conn = null;
QueryRunner qRunner = null;
try {
qRunner = new QueryRunner();
conn = dataSource.getConnection();
conn.setAutoCommit(false);
res = qRunner.update(conn,sql, params);
conn.commit();
} catch (SQLException e) {
try {
conn.rollback();
} catch (SQLException e1) {
logger.error("error rollback update operation ... ", e1);
}
logger.error("error when update data to database ... ",e);
}finally{
DbUtils.closeQuietly(conn);
}
return res;
}
@Override
public Map queryForMap(String sql, Object[] params) {
Map map = null;
Connection conn = null;
QueryRunner qRunner = null;
try {
qRunner = new QueryRunner();
conn = dataSource.getConnection();
map = qRunner.query(conn,sql, new MapHandler(),params);
} catch (SQLException e) {
logger.error("error when query data from database ... ",e);
}finally{
DbUtils.closeQuietly(conn);
}
return map;
}
public static Logger logger = Logger.getLogger (DBManagerImpl.class) ;
}
| zytools | trunk/src/com/zhongyi/db/impl/DBManagerImpl.java | Java | asf20 | 4,363 |
package com.zhongyi.db;
import java.util.List;
import java.util.Map;
/**
* DBUtil数据库操作类
* <p>
*
*
* @author <a href="mailto:lysongfie@gmail.com">songfei</a>
* @version 1.0,2012-2-27
*/
public interface DBManager {
public List queryForMapList(String sql,Object[] params);
public <T>List<T> queryForBeanList(String sql , Object[] params,Class<T> entityClass);
public Map queryForMap(String sql,Object[] params);
public int insertToDB(String sql,Object[] params);
public int deleteFromDB(String sql , Object[] params);
public int updateDB(String sql , Object[] params);
}
| zytools | trunk/src/com/zhongyi/db/DBManager.java | Java | asf20 | 639 |
package com.zhongyi.http;
import java.io.IOException;
import java.sql.Timestamp;
import javax.servlet.http.HttpServletRequest;
import com.zhongyi.entity.Company;
import com.zhongyi.entity.Contact;
import com.zhongyi.http.base.BaseAction;
import com.zhongyi.http.service.MessageService;
import com.zhongyi.util.Constant;
import com.zhongyi.util.HttpUtil;
import com.zhongyi.util.UUIDGenerator;
/**
* 企业信息录入处理类
* <p>
*
*
* @author <a href="mailto:lysongfei@gmail.com">songfei</a>
* @version 3.0, 2012-4-24
*/
public class MessageAction extends BaseAction {
/**
*
*/
private static final long serialVersionUID = 1L;
private String corpName;
/* text类型ajax返回值 */
// private String responseText;
private MessageService messageService;
//信息分隔符
private final String MESSAGE_SEPARATOR = "\n{1,}?";
public String getCorpName() {
return corpName;
}
public void setCorpName(String corpName) {
this.corpName = corpName;
}
public void setMessageService(MessageService messageService) {
this.messageService = messageService;
}
/**
* 处理企业信息录入
*/
public void doInput(){
String resText = "no";
HttpServletRequest request = HttpUtil.getRequest();
String uuid = UUIDGenerator.create();
Company corp = new Company();
Contact contact = null;
corp.setId(uuid);
HttpUtil.setComapny(corp, request);
corp.setCreate_time(new Timestamp(System.currentTimeMillis()));
messageService.addCompany(Constant.CORP_INSERT_SQL, corp);
//处理EMAIL
String[] values = null;
String info = corp.getEmail();
if(info != null && info.length() > 0){
values = info.split(MESSAGE_SEPARATOR);
for(String email : values){
if(email.trim().length() > 0){
contact = new Contact();
contact.setId(UUIDGenerator.create());
contact.setCorp_id(uuid);
contact.setContact_info(email.trim());
contact.setInfo_type("E");
contact.setCreate_time(new Timestamp(System.currentTimeMillis()));
messageService.addContact(Constant.CONTACT_INSERT_SQL, contact);
}
}
}
//处理MOBILE
info = corp.getMobile();
if(info != null && info.length() > 0){
values = info.split(MESSAGE_SEPARATOR);
for(String mobile : values){
if(mobile.trim().length() > 0){
contact = new Contact();
contact.setId(UUIDGenerator.create());
contact.setCorp_id(uuid);
contact.setContact_info(mobile.trim());
contact.setInfo_type("M");
contact.setCreate_time(new Timestamp(System.currentTimeMillis()));
messageService.addContact(Constant.CONTACT_INSERT_SQL, contact);
}
}
}
//处理PHONE
info = corp.getPhone();
if(info != null && info.length() > 0){
values = info.split(MESSAGE_SEPARATOR);
for(String phone : values){
if(phone.trim().length() > 0){
contact = new Contact();
contact.setId(UUIDGenerator.create());
contact.setCorp_id(uuid);
contact.setContact_info(phone.trim());
contact.setInfo_type("P");
contact.setCreate_time(new Timestamp(System.currentTimeMillis()));
messageService.addContact(Constant.CONTACT_INSERT_SQL, contact);
}
}
}
//处理FAX
info = corp.getFax();
if(info != null && info.length() > 0){
values = info.split(MESSAGE_SEPARATOR);
for(String fax : values){
if(fax.trim().length() > 0){
contact = new Contact();
contact.setId(UUIDGenerator.create());
contact.setCorp_id(uuid);
contact.setContact_info(fax.trim());
contact.setInfo_type("F");
contact.setCreate_time(new Timestamp(System.currentTimeMillis()));
messageService.addContact(Constant.CONTACT_INSERT_SQL, contact);
}
}
}
try {
resText = "yes";
HttpUtil.getResponse().getWriter().write(resText);
HttpUtil.getResponse().getWriter().flush();
HttpUtil.getResponse().getWriter().close();
} catch (IOException e) {
e.printStackTrace();
}
}
public String doCorpUniqueValidate(){
String responseText = "true";
if(this.corpName != null && this.corpName.trim().length() > 0){
int count = messageService.getComanyCount(Constant.CORP_COUNT_SQL, this.corpName);
if(count > 0){
responseText = "false";
}
}
try {
HttpUtil.getResponse().getWriter().write(responseText);
HttpUtil.getResponse().getWriter().flush();
HttpUtil.getResponse().getWriter().close();
} catch (IOException e) {
e.printStackTrace();
}
return NONE;
}
}
| zytools | trunk/src/com/zhongyi/http/MessageAction.java | Java | asf20 | 4,590 |
package com.zhongyi.http.service;
import com.zhongyi.entity.Company;
import com.zhongyi.entity.Contact;
public interface FileService {
public boolean saveCorp(String saveSQL,Company corp);
public boolean saveContact(String saveSQL , Contact contact);
}
| zytools | trunk/src/com/zhongyi/http/service/FileService.java | Java | asf20 | 275 |
package com.zhongyi.http.service.impl;
import java.util.ArrayList;
import java.util.List;
import com.zhongyi.db.DBManager;
import com.zhongyi.entity.Company;
import com.zhongyi.entity.Contact;
import com.zhongyi.entity.SysLog;
import com.zhongyi.http.service.MailService;
import com.zhongyi.util.Constant;
import com.zhongyi.util.MailUtil;
import com.zhongyi.util.Pager;
public class MailServiceImpl implements MailService {
private DBManager dbManager ;
private MailUtil mailManager;
public void setDbManager(DBManager dbManager) {
this.dbManager = dbManager;
}
public void setMailManager(MailUtil mailManager) {
this.mailManager = mailManager;
}
@Override
public List<Contact> queryMailList(String pagerSQL, Pager pager) {
// TODO Auto-generated method stub
return dbManager.queryForBeanList(Constant.EMAIL_PAGER_SQL, new Object[]{pager.getStartNum(),pager.getPageSize()}, Contact.class);
}
@Override
public List<Contact> queryMailList(String pagerSQL, Object[] params) {
// TODO Auto-generated method stub
return dbManager.queryForBeanList(Constant.EMAIL_PAGER_SQL, params, Contact.class);
}
@Override
public List queryMailByStatus(String status) {
// TODO Auto-generated method stub
return null;
}
@Override
public List queryForList(String query) {
// TODO Auto-generated method stub
return dbManager.queryForMapList(query, null);
}
@Override
public List<Contact> getMailByIds(String querySQL,String[] ids) {
List<Contact> contactList = new ArrayList<Contact>();
for(String mid : ids){
contactList.addAll(dbManager.queryForBeanList(querySQL, new String[]{mid}, Contact.class));
}
return contactList;
}
@Override
public List<Company> getCorpListById(String querySQL,String[] corpIds) {
// TODO Auto-generated method stub
List<Company> corpList = new ArrayList<Company>();
for(String cid : corpIds){
corpList.addAll(dbManager.queryForBeanList(querySQL, new String[]{cid}, Company.class));
}
return corpList;
}
@Override
public boolean sendHtmlMailList(List<Contact> mailList, String subject,
String message, String content, String mailType) {
// TODO Auto-generated method stub
return false;
}
public boolean sendHtmlMail(Contact mail, String subject, String message,
String content, String mailType) {
// TODO Auto-generated method stub
return mailManager.sendHtmlMail(mail.getContact_info(), subject, message, content);
}
@Override
public void updateMailStatus(String updateSQL,Contact contact,String status) {
// TODO Auto-generated method stub
dbManager.updateDB(updateSQL, new String[]{status,contact.getId()});
}
@Override
public void insertToSysLog(String insertSQL, SysLog sysLog) {
// TODO Auto-generated method stub
dbManager.insertToDB(Constant.SYSLOG_INSERT_SQL, new Object[]{sysLog.getId(),sysLog.getContact_id(),sysLog.getContact_info(),sysLog.getInfo_type(),sysLog.getInfo_body(),sysLog.getContact_time(),sysLog.getRemark(),sysLog.getStatus()});
}
}
| zytools | trunk/src/com/zhongyi/http/service/impl/MailServiceImpl.java | Java | asf20 | 3,089 |
package com.zhongyi.http.service.impl;
import com.zhongyi.db.DBManager;
import com.zhongyi.entity.Company;
import com.zhongyi.entity.Contact;
import com.zhongyi.http.service.FileService;
public class FileServiceImpl implements FileService {
public DBManager dbManager ;
public void setDbManager(DBManager dbManager) {
this.dbManager = dbManager;
}
@Override
public boolean saveCorp(String saveSQL, Company corp) {
int res = dbManager.insertToDB(saveSQL, new Object[]{corp.getId(),corp.getCorp_name(),corp.getArea_id(),corp.getAdress(),corp.getOrigin_site(),corp.getHome_page(),corp.getCorp_level(),corp.getCorp_type(),corp.getLinker(),corp.getKeyword(),corp.getCreate_time(),corp.getRemark()});
if(res > 0){
return true;
}
return false;
}
@Override
public boolean saveContact(String saveSQL, Contact contact) {
int res = dbManager.insertToDB(saveSQL, new Object[]{contact.getId(),contact.getCorp_id(),contact.getContact_info(),contact.getInfo_type(),contact.getRemark(),contact.getCreate_time()});
if(res > 0){
return true;
}
return false;
}
}
| zytools | trunk/src/com/zhongyi/http/service/impl/FileServiceImpl.java | Java | asf20 | 1,120 |
package com.zhongyi.http.service.impl;
import java.util.List;
import java.util.Map;
import com.zhongyi.db.DBManager;
import com.zhongyi.entity.Company;
import com.zhongyi.entity.Contact;
import com.zhongyi.http.service.MessageService;
public class MessageServiceImpl implements MessageService {
public DBManager dbManager ;
public void setDbManager(DBManager dbManager) {
this.dbManager = dbManager;
}
@Override
public void addCompany(String insert, Company corp) {
// TODO Auto-generated method stub
dbManager.insertToDB(insert, new Object[]{corp.getId(),corp.getCorp_name(),corp.getArea_id(),corp.getAdress(),corp.getOrigin_site(),corp.getHome_page(),corp.getCorp_level(),corp.getCorp_type(),corp.getLinker(),corp.getKeyword(),corp.getCreate_time(),corp.getRemark()});
}
@Override
public List getAllCompany() {
// TODO Auto-generated method stub
return null;
}
@Override
public void addContact(String insert, Contact contact) {
// TODO Auto-generated method stub
dbManager.insertToDB(insert, new Object[]{contact.getId(),contact.getCorp_id(),contact.getContact_info(),contact.getInfo_type(),contact.getRemark(),contact.getCreate_time()});
}
@Override
public int getComanyCount(String countSQL , String corpName) {
// TODO Auto-generated method stub
Long result = new Long(0);
Map map = dbManager.queryForMap(countSQL, new Object[]{corpName.trim()});
if(map != null && map.get("total") != null){
result = (Long)map.get("total");
}
return result.intValue();
}
}
| zytools | trunk/src/com/zhongyi/http/service/impl/MessageServiceImpl.java | Java | asf20 | 1,570 |
package com.zhongyi.http.service;
import java.util.List;
import com.zhongyi.entity.Company;
import com.zhongyi.entity.Contact;
import com.zhongyi.entity.SysLog;
import com.zhongyi.util.Pager;
public interface MailService {
/**
* 查询邮件列表
* @return
*/
public List<Contact> queryMailList(String pagerSQL, Pager pager);
public List<Contact> queryMailList(String pagerSQL, Object[] params);
public List queryForList(String query);
public List<Contact> getMailByIds(String querySQL,String[] ids);
/**
* 邮件群发
* @param mailList
* @param subject
* @param message
* @param content
* @param mailType
* @return
*/
public boolean sendHtmlMailList(List<Contact> mailList,String subject,String message,String content,String mailType);
/**
*
* @param mail
* @param subject
* @param message
* @param content
* @param mailType
* @return
*/
public boolean sendHtmlMail(Contact mail,String subject,String message,String content,String mailType);
/**
* 查询企业基础信息
* @param corpIds
* @return
*/
public List<Company> getCorpListById(String querySQL,String[] corpIds);
public List queryMailByStatus(String status);
/**
* 更新邮件发送状态
* @param contact
*/
public void updateMailStatus(String updateSQL,Contact contact,String status);
/**
* 记录邮件发送日志
* @param insertSQL
* @param sysLog
*/
public void insertToSysLog(String insertSQL,SysLog sysLog);
}
| zytools | trunk/src/com/zhongyi/http/service/MailService.java | Java | asf20 | 1,569 |
package com.zhongyi.http.service;
import java.util.List;
import com.zhongyi.entity.Company;
import com.zhongyi.entity.Contact;
public interface MessageService {
/**
* 企业信息录入
* @param insert
* @param corp
*/
public void addCompany(String insert,Company corp);
// public void editCompany(String sql,Company corp);
public List getAllCompany();
public void addContact(String insert,Contact contact);
/**
* 企业数量统计
* @param countSQL
* @param corpName
* @return
*/
public int getComanyCount(String countSQL,String corpName);
// public void editContact();
}
| zytools | trunk/src/com/zhongyi/http/service/MessageService.java | Java | asf20 | 648 |
package com.zhongyi.http.service;
import java.io.IOException;
import java.io.InputStream;
import com.zhongyi.entity.Contact;
import com.zhongyi.entity.SysLog;
import com.zhongyi.util.HttpUtil;
import com.zhongyi.util.StringUtil;
public class QuartzService {
private MailService mailService;
public void setMailService(MailService mailService) {
this.mailService = mailService;
}
/**
* 定时器发送邮件
*/
public void quartzSendMail(){
boolean status = false;
SysLog sysLog = null;
// List<Contact> contactList = mailService.queryMailList(Constant.EMAIL_PAGER_SQL,new Integer[]{0,50});
// for(Contact con : contactList){
// status = mailService.sendHtmlMail(con, "/manufacture Refractory Materials and Castings/ZhongYi Foundry Co., Ltd", "Your email client does not support HTML messages.Visit www.zhongyifoundry.com for details please.", content, null);
//
// sysLog = new SysLog();
// sysLog.setId(UUIDGenerator.create());
// sysLog.setContact_id(con.getId());
// sysLog.setContact_info(con.getContact_info());
// sysLog.setInfo_type(con.getInfo_type());
// sysLog.setInfo_body(content);
// sysLog.setContact_time(new Timestamp(System.currentTimeMillis()));
// sysLog.setStatus((status==true)?"1":"0");
// //更新邮件状态为 "已发送"
// if(status){
// mailService.updateMailStatus(Constant.CONTACT_STAUTS_UPDATE_SQL, con, "1");
// }
// mailService.insertToSysLog(Constant.SYSLOG_INSERT_SQL, sysLog);
// }
Contact con = new Contact();
con.setContact_info("sf314948016@126.com");
InputStream ins = HttpUtil.getServletContext().getResourceAsStream("/template/mailTemplate.html");
String htmlContent = StringUtil.readHtmlToString(ins);
try {
ins.close();
} catch (IOException e) {
e.printStackTrace();
}finally{
ins = null;
}
mailService.sendHtmlMail(con, "/manufacture Refractory Materials and Castings/ZhongYi Foundry Co., Ltd", "Your email client does not support HTML messages.Visit www.zhongyifoundry.com for details please.", htmlContent, null);
}
}
| zytools | trunk/src/com/zhongyi/http/service/QuartzService.java | Java | asf20 | 2,120 |
package com.zhongyi.http.base;
import com.opensymphony.xwork2.ActionSupport;
public class BaseAction extends ActionSupport {
}
| zytools | trunk/src/com/zhongyi/http/base/BaseAction.java | Java | asf20 | 138 |
package com.zhongyi.http;
import java.io.IOException;
import java.io.InputStream;
import java.sql.Timestamp;
import java.util.HashMap;
import java.util.List;
import java.util.Map;
import org.apache.log4j.Logger;
import com.google.gson.Gson;
import com.zhongyi.entity.Company;
import com.zhongyi.entity.Contact;
import com.zhongyi.entity.SysLog;
import com.zhongyi.http.base.BaseAction;
import com.zhongyi.http.service.MailService;
import com.zhongyi.util.Constant;
import com.zhongyi.util.HttpUtil;
import com.zhongyi.util.Pager;
import com.zhongyi.util.StringUtil;
import com.zhongyi.util.UUIDGenerator;
public class MailAction extends BaseAction {
/**
*
*/
private static final long serialVersionUID = 1L;
private List<Contact> mailList;
private MailService mailService;
private String[] mids;
/* 邮件内容 */
private String message;
private String subject;
private String content;
/* 当前页数 */
private String pageNum ;
/* 分页大小 */
private String pageSize ;
private Pager pager;
public void setMailService(MailService mailService) {
this.mailService = mailService;
}
public List<Contact> getMailList() {
return mailList;
}
public void setMailList(List<Contact> mailList) {
this.mailList = mailList;
}
public String getPageNum() {
return pageNum;
}
public void setPageNum(String pageNum) {
this.pageNum = pageNum;
}
public String getPageSize() {
return pageSize;
}
public void setPageSize(String pageSize) {
this.pageSize = pageSize;
}
public String sendMail(){
return SUCCESS;
}
public Pager getPager() {
return pager;
}
public void setPager(Pager pager) {
this.pager = pager;
}
public String[] getMids() {
return mids;
}
public void setMids(String[] mids) {
this.mids = mids;
}
public String getMessage() {
return message;
}
public void setMessage(String message) {
if(message == null || message.trim().length() == 0){
this.message = "Your email client does not support HTML messages.Visit www.zhongyifoundry.com for details please.";
return ;
}
this.message = message;
}
public String getSubject() {
return subject;
}
public void setSubject(String subject) {
if(subject == null || subject.trim().length() == 0){
this.subject = " /manufacture Refractory Materials and Castings/ZhongYi Foundry Co., Ltd";
return ;
}
this.subject = subject;
}
public String getContent() {
return content;
}
public void setContent(String content) {
if(content == null || content.trim().length() == 0){
InputStream ins = HttpUtil.getServletContext().getResourceAsStream("/template/mailTemplate.html");
this.content = StringUtil.readHtmlToString(ins);
try {
ins.close();
} catch (IOException e) {
e.printStackTrace();
}finally{
ins = null;
}
return ;
}
this.content = content;
}
/**
* 待发送邮件列表
* @return
*/
public String queryList(){
int currentPage = 1;
int pageSize = 20;
Long total = new Long(0);
Map map = null;
if(pageNum != null && pageNum.length() > 0){
currentPage = Integer.valueOf(pageNum);
}
if(this.pageSize != null && this.pageSize.length() > 0){
pageSize = Integer.valueOf(this.pageSize);
}
List list = mailService.queryForList(Constant.EMAIL_COUNT_SQL);
if(list != null && list.size() > 0){
map = (Map)list.get(0);
total = (Long)map.get("total");
}
pager = new Pager(pageSize,currentPage,total.intValue());
mailList = mailService.queryMailList(Constant.EMAIL_PAGER_SQL,pager);
return "allMailList";
}
public void ajaxQuery(){
Map<Object,Object> jsonMap = new HashMap<Object,Object>();
int currentPage = 1;
int pageSize = 20;
Long total = new Long(0);
Map map = null;
if(pageNum != null && pageNum.length() > 0){
currentPage = Integer.valueOf(pageNum);
}
if(this.pageSize != null && this.pageSize.length() > 0){
pageSize = Integer.valueOf(this.pageSize);
}
List list = mailService.queryForList(Constant.EMAIL_COUNT_SQL);
if(list != null && list.size() > 0){
map = (Map)list.get(0);
total = (Long)map.get("total");
}
pager = new Pager(pageSize,currentPage,total.intValue());
mailList = mailService.queryMailList(Constant.EMAIL_PAGER_SQL,pager);
Gson gson = new Gson();
jsonMap.put("list", mailList);
jsonMap.put("pager", pager);
String backJSON = gson.toJson(jsonMap);
logger.debug("json : " + backJSON);
try {
HttpUtil.getResponse().getWriter().write(backJSON);
HttpUtil.getResponse().getWriter().flush();
HttpUtil.getResponse().getWriter().close();
} catch (IOException e) {
e.printStackTrace();
}
}
/**
* 发送邮件
* @return
*/
public String sendMails(){
String responseText = "no";
if(this.mids != null && this.mids.length > 0){
boolean status = false;
Company corp = null;
SysLog sysLog = null;
List<Company> corpList = null;
List<Contact> contactList = mailService.getMailByIds(Constant.CONTACT_IDQUERY_SQL,mids);
for(Contact con : contactList){
corpList = mailService.getCorpListById(Constant.CONTACT_IDQUERY_SQL,new String[]{con.getCorp_id()});
if(corpList != null && corpList.size() > 0){
corp = corpList.get(0);
subject = corp.getCorp_name() + subject;
}
status = mailService.sendHtmlMail(con, subject, message, content, null);
sysLog = new SysLog();
sysLog.setId(UUIDGenerator.create());
sysLog.setContact_id(con.getId());
sysLog.setContact_info(con.getContact_info());
sysLog.setInfo_type(con.getInfo_type());
sysLog.setInfo_body(content);
sysLog.setContact_time(new Timestamp(System.currentTimeMillis()));
sysLog.setStatus((status==true)?"1":"0");
//更新邮件状态为 "已发送"
if(status){
mailService.updateMailStatus(Constant.CONTACT_STAUTS_UPDATE_SQL, con, "1");
responseText = "yes";
}
mailService.insertToSysLog(Constant.SYSLOG_INSERT_SQL, sysLog);
}
}
//辅助测试邮件
Contact con = new Contact();
con.setContact_info("sf314948016@126.com");
mailService.sendHtmlMail(con, subject, message, content, null);
try {
HttpUtil.getResponse().getWriter().write(responseText);
HttpUtil.getResponse().getWriter().flush();
HttpUtil.getResponse().getWriter().close();
} catch (IOException e) {
e.printStackTrace();
}
return null;
}
private Logger logger = Logger.getLogger(MailAction.class);
}
| zytools | trunk/src/com/zhongyi/http/MailAction.java | Java | asf20 | 6,627 |
package com.zhongyi.http;
import java.io.File;
import java.io.FileInputStream;
import java.io.FileOutputStream;
import java.io.IOException;
import java.io.InputStream;
import java.sql.Timestamp;
import org.apache.poi.ss.usermodel.Row;
import org.apache.poi.ss.usermodel.Sheet;
import org.apache.poi.ss.usermodel.Workbook;
import org.apache.poi.xssf.usermodel.XSSFWorkbook;
import com.zhongyi.entity.Company;
import com.zhongyi.entity.Contact;
import com.zhongyi.http.base.BaseAction;
import com.zhongyi.http.service.FileService;
import com.zhongyi.util.Constant;
import com.zhongyi.util.HttpUtil;
import com.zhongyi.util.ImportUtil;
import com.zhongyi.util.StringUtil;
import com.zhongyi.util.UUIDGenerator;
/**
* 企业信息-源文件上传
*
* <p>
*
*
* @author <a href="mailto:lysongfei@gmail.com">songfei</a>
* @version 1.0, 2012-6-9
*/
public class FileAction extends BaseAction {
/**
*
*/
private static final long serialVersionUID = 1L;
private File doc;
// 封装上传文件类型的属性
private String docContentType;
// 封装上传文件名的属性
private String docFileName;
private String savePath;
private FileService fileService;
public File getDoc() {
return doc;
}
public void setDoc(File doc) {
this.doc = doc;
}
public String getDocContentType() {
return docContentType;
}
public void setDocContentType(String docContentType) {
this.docContentType = docContentType;
}
public String getDocFileName() {
return docFileName;
}
public void setDocFileName(String docFileName) {
this.docFileName = docFileName;
}
public String getSavePath() {
return savePath;
}
public void setSavePath(String savePath) {
this.savePath = HttpUtil.getServletContext().getRealPath(savePath);
}
public void setFileService(FileService fileService) {
this.fileService = fileService;
}
public String upload(){
FileOutputStream fos = null;
FileInputStream fis = null;
Workbook wkbook = null;
Sheet sheet = null;
Row row = null;
Company corp = null;
Contact contact = null;
try {
// 建立文件上传流
fis = new FileInputStream(doc);
fos = new FileOutputStream(savePath + "\\" + getDocFileName());
byte[] buffer = new byte[1024];
int len = 0;
while ((len = fis.read(buffer)) > 0) {
fos.write(buffer, 0, len);
}
fos.flush();
fis = new FileInputStream(savePath + "\\" + getDocFileName());
wkbook = new XSSFWorkbook(fis);
sheet = wkbook.getSheetAt(0);
int rowCount = sheet.getLastRowNum();
for (int i = 1; i <= rowCount; i++) {
corp = new Company();
row = sheet.getRow(i);
//判断当前行是否为空行
if(ImportUtil.isRowNull(row)){
break;
}
String corpId = UUIDGenerator.create();
//company message
corp.setId(corpId);
corp.setCorp_type(ImportUtil.getCellValue(row.getCell(1)));
corp.setKeyword(ImportUtil.getCellValue(row.getCell(2)));
corp.setArea_id(ImportUtil.getCellValue(row.getCell(3)));
corp.setCorp_name(ImportUtil.getCellValue(row.getCell(4)));
corp.setLinker(ImportUtil.getCellValue(row.getCell(5)));
corp.setOrigin_site(ImportUtil.getCellValue(row.getCell(10)));
corp.setCreate_time(new Timestamp(System.currentTimeMillis()));
corp.setRemark(ImportUtil.getCellValue(row.getCell(11)));
this.fileService.saveCorp(Constant.CORP_INSERT_SQL, corp);
//Email
String value = ImportUtil.getCellValue(row.getCell(6));
String[] vs = null;
if(value != null && value.length() > 0){
vs = value.split("\\|");
for(String v : vs){
contact = new Contact();
contact.setId(UUIDGenerator.create());
contact.setCorp_id(corpId);
contact.setContact_info(StringUtil.parseString(v));
contact.setInfo_type("E");
contact.setCreate_time(new Timestamp(System.currentTimeMillis()));
this.fileService.saveContact(Constant.CONTACT_INSERT_SQL, contact);
}
}
//phone
value = ImportUtil.getCellValue(row.getCell(7));
if(value != null && value.length() > 0){
vs = value.split("\\|");
for(String v : vs){
contact = new Contact();
contact.setId(UUIDGenerator.create());
contact.setCorp_id(corpId);
contact.setContact_info(StringUtil.parseString(v));
contact.setInfo_type("P");
contact.setCreate_time(new Timestamp(System.currentTimeMillis()));
this.fileService.saveContact(Constant.CONTACT_INSERT_SQL, contact);
}
}
//mobile
value = ImportUtil.getCellValue(row.getCell(8));
if(value != null && value.length() > 0){
vs = value.split("\\|");
for(String v : vs){
contact = new Contact();
contact.setId(UUIDGenerator.create());
contact.setCorp_id(corpId);
contact.setContact_info(StringUtil.parseString(v));
contact.setInfo_type("M");
contact.setCreate_time(new Timestamp(System.currentTimeMillis()));
this.fileService.saveContact(Constant.CONTACT_INSERT_SQL, contact);
}
}
//Fax
value = ImportUtil.getCellValue(row.getCell(9));
if(value != null && value.length() > 0){
vs = value.split("\\|");
for(String v : vs){
contact = new Contact();
contact.setId(UUIDGenerator.create());
contact.setCorp_id(corpId);
contact.setContact_info(StringUtil.parseString(v));
contact.setInfo_type("F");
contact.setCreate_time(new Timestamp(System.currentTimeMillis()));
this.fileService.saveContact(Constant.CONTACT_INSERT_SQL, contact);
}
}
}
} catch (Exception e) {
System.out.println("文件上传失败");
e.printStackTrace();
} finally {
try {
fis.close();
fos.close();
} catch (IOException e) {
System.out.println("文件流关闭失败！");
e.printStackTrace();
}
}
return SUCCESS;
}
}
| zytools | trunk/src/com/zhongyi/http/FileAction.java | Java | asf20 | 6,190 |
package com.zhongyi.util;
import java.io.File;
import java.io.FileInputStream;
import java.io.FileNotFoundException;
import java.io.IOException;
import java.io.InputStream;
import java.io.InputStreamReader;
import java.util.regex.Matcher;
import java.util.regex.Pattern;
import org.springframework.util.StringUtils;
/**
* 自定义字符串处理类
* <p>
*
*
* @author <a href="mailto:lysongfei@gmail.com">songfei</a>
* @version 3.0, 2012-4-24
*/
public class StringUtil {
private static final int CHAR_BUFFER_SIZE = 200;
public static String readHtmlToString(String htmlPath){
InputStreamReader isReader = null;
StringBuilder sBuilder = new StringBuilder();
if(htmlPath != null && htmlPath.length() > 0){
int index = -1;
File file = new File(htmlPath);
char[] cs = new char[CHAR_BUFFER_SIZE];
if(file.exists()){//文件存在
try {
isReader = new InputStreamReader(new FileInputStream(file));
index = isReader.read(cs);
while(index != -1){
sBuilder.append(cs, 0, index);
index = isReader.read(cs);
}
} catch (FileNotFoundException e) {
e.printStackTrace();
} catch (IOException e) {
e.printStackTrace();
}finally{
if(isReader != null){
try {
isReader.close();
} catch (IOException e) {
e.printStackTrace();
}
}
}
}
}
return sBuilder.toString();
}
public static String readHtmlToString(InputStream ins){
InputStreamReader isReader = null;
StringBuilder sBuilder = new StringBuilder();
int index = -1;
char[] cs = new char[CHAR_BUFFER_SIZE];
try {
isReader = new InputStreamReader(ins);
index = isReader.read(cs);
while(index != -1){
sBuilder.append(cs, 0, index);
index = isReader.read(cs);
}
} catch (FileNotFoundException e) {
e.printStackTrace();
} catch (IOException e) {
e.printStackTrace();
}finally{
if(isReader != null){
try {
isReader.close();
} catch (IOException e) {
e.printStackTrace();
}
}
}
return sBuilder.toString();
}
public static String parseHtmlString(String htmlString){
return null;
}
/**
* 字符串清洗
* @param str
* @return
*/
public static String parseString(String str){
String result = null;
if(str != null && str.length() > 0){
Pattern pattern = Pattern.compile("\\s*|\t|\r|\n");
//去除字符串中空格、回车、换行符
Matcher matcher = pattern.matcher(str);
result = matcher.replaceAll("");
}
return result;
}
/**
* 验证邮件格式是否正确
* @param email
* @return
*/
public static boolean isEmailAddress(String email) {
Pattern emailer = Pattern.compile("\\w+([-+.]\\w+)*@\\w+([-.]\\w+)*\\.\\w+([-.]\\w+)*");
if (!StringUtils.hasText(email))
return false;
email = email.toLowerCase();
return emailer.matcher(email).matches();
}
}
| zytools | trunk/src/com/zhongyi/util/StringUtil.java | Java | asf20 | 3,062 |
package com.zhongyi.util;
import java.io.IOException;
import java.io.InputStream;
import java.sql.Connection;
import java.sql.SQLException;
import java.util.Properties;
import org.apache.commons.dbcp.BasicDataSource;
import org.apache.log4j.Logger;
import org.springframework.context.ApplicationContext;
import org.springframework.context.support.FileSystemXmlApplicationContext;
import org.springframework.web.context.support.WebApplicationContextUtils;
/**
* 自定义JDBC辅助工具类
* <p>
*
*
* @author <a href="mailto:lysongfei@gmail.com">songfei</a>
* @version 3.0, 2012-4-24
*/
public class DBUtil {
public static Logger logger = Logger.getLogger (DBUtil.class) ;
/**
* 获取数据库连接
* @return
*/
public static Connection getConnection(){
Connection conn = null;
try {
ApplicationContext ac = WebApplicationContextUtils.getWebApplicationContext(HttpUtil.getServletContext());
// ApplicationContext ac = new FileSystemXmlApplicationContext("/WebContent/WEB-INF/classes/dataAccessContext-local.xml");
BasicDataSource dataSource = (BasicDataSource)ac.getBean("dataSource");
conn = dataSource.getConnection();
} catch (SQLException e) {
logger.error("error getting the database connection ... ",e);
}
return conn;
}
}
| zytools | trunk/src/com/zhongyi/util/DBUtil.java | Java | asf20 | 1,333 |
package com.zhongyi.util;
import java.lang.reflect.InvocationTargetException;
import javax.servlet.ServletContext;
import javax.servlet.http.HttpServletRequest;
import javax.servlet.http.HttpServletResponse;
import javax.servlet.http.HttpSession;
import org.apache.commons.beanutils.BeanUtils;
import org.apache.log4j.Logger;
import org.apache.struts2.ServletActionContext;
import com.opensymphony.xwork2.ActionContext;
import com.zhongyi.entity.Company;
/**
* Http请求辅助工具类
* <p>
*
*
* @author <a href="mailto:lysongfei@gmail.com">songfei</a>
* @version 3.0, 2012-4-24
*/
public class HttpUtil {
private static Logger logger = Logger.getLogger(HttpUtil.class);
public static void setComapny(Company corp,HttpServletRequest request){
try {
BeanUtils.setProperty(corp, "corp_name", request.getParameter("p_corp_name"));
BeanUtils.setProperty(corp, "area_id", request.getParameter("p_area_id"));
BeanUtils.setProperty(corp, "adress", request.getParameter("p_adress"));
BeanUtils.setProperty(corp, "origin_site", request.getParameter("p_origin_site"));
BeanUtils.setProperty(corp, "home_page", request.getParameter("p_home_page"));
BeanUtils.setProperty(corp, "corp_level", request.getParameter("p_corp_level"));
BeanUtils.setProperty(corp, "corp_type", request.getParameter("p_corp_type"));
BeanUtils.setProperty(corp, "linker", request.getParameter("p_linker"));
BeanUtils.setProperty(corp, "keyword", request.getParameter("p_keyword"));
BeanUtils.setProperty(corp, "remark", request.getParameter("p_remark"));
//表单临时赋值字段
BeanUtils.setProperty(corp, "email", request.getParameter("p_email"));
BeanUtils.setProperty(corp, "phone", request.getParameter("p_phone"));
BeanUtils.setProperty(corp, "mobile", request.getParameter("p_mobile"));
BeanUtils.setProperty(corp, "fax", request.getParameter("p_fax"));
} catch (IllegalAccessException e) {
logger.info("", e);
} catch (InvocationTargetException e) {
logger.info("",e);
}
}
public static HttpServletRequest getRequest(){
return ServletActionContext.getRequest();
}
public static HttpServletResponse getResponse(){
ActionContext.getContext().getSession();
return ServletActionContext.getResponse();
}
public static HttpSession getSession(){
return ServletActionContext.getRequest().getSession();
}
public static ServletContext getServletContext(){
return ServletActionContext.getServletContext();
}
}
| zytools | trunk/src/com/zhongyi/util/HttpUtil.java | Java | asf20 | 2,553 |
package com.zhongyi.util;
import java.io.File;
import java.text.DateFormat;
import java.text.SimpleDateFormat;
import java.util.HashMap;
import java.util.LinkedHashMap;
import org.apache.commons.io.FilenameUtils;
import org.apache.log4j.Logger;
import org.apache.poi.hssf.usermodel.HSSFCell;
import org.apache.poi.hssf.usermodel.HSSFDateUtil;
import org.apache.poi.ss.usermodel.Cell;
import org.apache.poi.ss.usermodel.Row;
/**
* Excel数据导入辅助工具类
* <p>
*
*
* @author <a href="mailto:lysongfei@gmail.com">songfei</a>
* @version 3.0, 2012-4-24
*/
public class ImportUtil {
private static Logger logger = Logger.getLogger(ImportUtil.class);
public static boolean isRowNull(Row row){
String cellValue = "";
String flag = "";
boolean isNull = false;
int cellNum = row.getLastCellNum();
for(int i=0;i<cellNum;i++){
cellValue = getCellValue(row.getCell(i));
if(cellValue == null || cellValue.trim().length() == 0 ){
flag += 1;
}
}
if(flag.length() == cellNum){
isNull = true;
}
return isNull;
}
public static String getCellValue(Cell cell) {
String value = "";
if (cell != null) {
if (cell.getCellType() == HSSFCell.CELL_TYPE_STRING) {// 字符串型
value = cell.getRichStringCellValue().toString();
} else if (cell.getCellType() == HSSFCell.CELL_TYPE_NUMERIC) {// 数值型
if (HSSFDateUtil.isCellDateFormatted(cell)) {//日期型
DateFormat format = new SimpleDateFormat("yyyy-MM-dd");
value = format.format(cell.getDateCellValue());
} else {//数值型
value = String.valueOf(cell.getNumericCellValue());
}
} else if (cell.getCellType() == HSSFCell.CELL_TYPE_BOOLEAN) {// 是否为布尔型
value = Boolean.toString(cell.getBooleanCellValue());
} else if(cell.getCellType() == HSSFCell.CELL_TYPE_FORMULA){
value = cell.getCellFormula();
}
}
return value.trim();
}
/**
* 整理指定目录中的数据文件
* HashMap<String,String> 1：文件名称(含扩展名) 2:文件绝对路径
* @param dir 数据文件目录
* @return 数据文件集合
*/
public static HashMap<String,String> getMatchFiles(File dir) {
long start = System.currentTimeMillis();
HashMap<String, String> fileNames = new LinkedHashMap<String, String>();
File[] dataFiles = null;
if(dir.exists() && dir.isDirectory()){
dataFiles = dir.listFiles();
for(int i=0;i<dataFiles.length;i++){
if(dataFiles[i].isDirectory()){
String[] fnames = dataFiles[i].list();
for(int j=0;j<fnames.length;j++){
fileNames.put(FilenameUtils.getName(fnames[j]),dataFiles[i].getAbsolutePath()+File.separator+fnames[j]);
}
}else{
String fname = dataFiles[i].getAbsolutePath();
fileNames.put(FilenameUtils.getName(fname),fname);
}
}
}
long end = System.currentTimeMillis();
logger.info("匹配文件耗时：" +(end-start) + "毫秒");
return fileNames;
}
}
| zytools | trunk/src/com/zhongyi/util/ImportUtil.java | Java | asf20 | 3,172 |
package com.zhongyi.util;
public class Pager {
private int currentPage = 1;// 当前页数
public int totalPages = 0;// 总页数
private int pageSize = 0;// 每页显示数
private int totalRows = 0;// 总数据数
private int startNum = 0;// 开始记录
private int nextPage = 0;// 下一页
private int previousPage = 0;// 上一页
private boolean hasNextPage = false;// 是否有下一页
private boolean hasPreviousPage = false;// 是否有前一页
public Pager(int pageSize, int currentPage, int totalRows) {
this.pageSize = pageSize;
this.currentPage = currentPage;
this.totalRows = totalRows;
if ((totalRows % pageSize) == 0) {
totalPages = totalRows / pageSize;
} else {
totalPages = totalRows / pageSize + 1;
}
if (currentPage >= totalPages) {
hasNextPage = false;
currentPage = totalPages;
} else {
hasNextPage = true;
}
if (currentPage <= 1) {
hasPreviousPage = false;
currentPage = 1;
} else {
hasPreviousPage = true;
}
startNum = (currentPage - 1) * pageSize;
nextPage = currentPage + 1;
if (nextPage >= totalPages) {
nextPage = totalPages;
}
previousPage = currentPage - 1;
if (previousPage <= 1) {
previousPage = 1;
}
}
public boolean isHasNextPage() {
return hasNextPage;
}
public boolean isHasPreviousPage() {
return hasPreviousPage;
}
/**
* @return the nextPage
*/
public int getNextPage() {
return nextPage;
}
/**
* @param nextPage
* the nextPage to set
*/
public void setNextPage(int nextPage) {
this.nextPage = nextPage;
}
/**
* @return the previousPage
*/
public int getPreviousPage() {
return previousPage;
}
/**
* @param previousPage
* the previousPage to set
*/
public void setPreviousPage(int previousPage) {
this.previousPage = previousPage;
}
/**
* @return the currentPage
*/
public int getCurrentPage() {
return currentPage;
}
/**
* @param currentPage
* the currentPage to set
*/
public void setCurrentPage(int currentPage) {
this.currentPage = currentPage;
}
/**
* @return the pageSize
*/
public int getPageSize() {
return pageSize;
}
/**
* @param pageSize
* the pageSize to set
*/
public void setPageSize(int pageSize) {
this.pageSize = pageSize;
}
/**
* @return the totalPages
*/
public int getTotalPages() {
return totalPages;
}
/**
* @param totalPages
* the totalPages to set
*/
public void setTotalPages(int totalPages) {
this.totalPages = totalPages;
}
/**
* @return the totalRows
*/
public int getTotalRows() {
return totalRows;
}
/**
* @param totalRows
* the totalRows to set
*/
public void setTotalRows(int totalRows) {
this.totalRows = totalRows;
}
/**
* @param hasNextPage
* the hasNextPage to set
*/
public void setHasNextPage(boolean hasNextPage) {
this.hasNextPage = hasNextPage;
}
/**
* @param hasPreviousPage
* the hasPreviousPage to set
*/
public void setHasPreviousPage(boolean hasPreviousPage) {
this.hasPreviousPage = hasPreviousPage;
}
/**
* @return the startNum
*/
public int getStartNum() {
return startNum;
}
/**
* @param startNum
* the startNum to set
*/
public void setStartNum(int startNum) {
this.startNum = startNum;
}
} | zytools | trunk/src/com/zhongyi/util/Pager.java | Java | asf20 | 3,573 |
package com.zhongyi.util;
/**
* 系统常量配置类
* <p>
*
*
* @author <a href="mailto:lysongfei@gmail.com">songfei</a>
* @version 3.0, 2012-4-24
*/
public class Constant {
/* 企业基础信息全字段INSERT语句*/
public static final String CORP_INSERT_SQL = "insert into td_company(id,corp_name,area_id,address,origin_site,home_page,corp_level,corp_type,linker,keyword,create_time,remark) values (?,?,?,?,?,?,?,?,?,?,?,?)";
/* 企业联系信息全字段INSERT语句*/
public static final String CONTACT_INSERT_SQL = "insert into td_contact(id,corp_id,contact_info,info_type,remark,create_time) values (?,?,?,?,?,?)";
/* 系统日志全字段INSERT语句*/
public static final String SYSLOG_INSERT_SQL = "insert into td_sys_log(id,contact_id,contact_info,info_type,info_body,contact_time,remark,status) values(?,?,?,?,?,?,?,?)";
/* 区域信息全字段INSERT语句*/
public static final String AREA_INSERT_SQL = "";
/* 企业基础信息全字段UPDATE语句*/
public static final String CORP_UPDATE_SQL = "";
/* 企业联系信息、邮件状态为更新 */
public static String CONTACT_STAUTS_UPDATE_SQL = "update td_contact set is_msend = ? where id = ?";
/* 企业基础信息辅助查询 */
public static final String CORP_COUNT_SQL = "select count(1) total from td_company where corp_name = ?";
/* 企业邮件信息辅助查询 */
public static final String EMAIL_PAGER_SQL = "select * from td_contact where info_type = 'E' and is_msend is null order by create_time desc limit ?,?";
public static final String EMAIL_COUNT_SQL = "select count(1) total from td_contact where info_type = 'E' and is_msend is null";
public static final String CONTACT_IDQUERY_SQL = "select * from td_contact where id = ?";
public static final String CORP_IDQUERY_SQL = "select * from td_company where id = ?";
}
| zytools | trunk/src/com/zhongyi/util/Constant.java | Java | asf20 | 1,892 |
package com.zhongyi.util;
import java.net.URL;
import java.util.List;
import org.apache.commons.mail.EmailAttachment;
import org.apache.commons.mail.EmailException;
import org.apache.commons.mail.HtmlEmail;
import org.apache.commons.mail.SimpleEmail;
import org.apache.log4j.Logger;
/**
* 邮件发送辅助工具类
* <p>
*
*
* @author <a href="mailto:lysongfei@gmail.com">songfei</a>
* @version 3.0, 2012-4-24
*/
public class MailUtil {
private MailConfiguration mailConfig;
public void setMailConfig(MailConfiguration mailConfig) {
this.mailConfig = mailConfig;
}
public static boolean sendMail(String mailTo,String mailSubject,String message,String templatePath,List<String> attachList){
boolean status = false;
return status;
}
public boolean sendTextMail(String mailTo,String mailSubject,String message){
boolean status = false;
SimpleEmail email=new SimpleEmail ();
email.setHostName(mailConfig.getSmtp());
email.setCharset(mailConfig.getCharset());
email.setAuthentication(mailConfig.getUser(), mailConfig.getPwd());
try {
email.addTo(mailTo);
email.setFrom(mailConfig.getUser());
email.setSubject(mailSubject);
email.setMsg(message);
email.send();
status = true;
} catch (EmailException e) {
logger.error("error send text mail to " + mailTo + " ..." , e);
}
return status;
}
public boolean sendHtmlMail(String mailTo,String mailSubject,String message,String htmlTemplatePath){
boolean status = false;
HtmlEmail email = new HtmlEmail();
email.setHostName(mailConfig.getSmtp());
email.setCharset(mailConfig.getCharset());
email.setAuthentication(mailConfig.getUser(), mailConfig.getPwd());
try {
// EmailAttachment attachment = new EmailAttachment();
// attachment.setURL(new URL("http://www.zhongyifoundry.com/wp-content/themes/twentyeleven/images/zhongyi_new.jpg"));
// attachment.setDisposition(EmailAttachment.ATTACHMENT);
// attachment.setDescription("Company Logo");
// attachment.setName("zhongyifoundry");
// String html = StringUtil.readHtmlToString(htmlTemplatePath);
email.addTo(mailTo);
email.setFrom(mailConfig.getUser());
email.setSubject(mailSubject);
email.setHtmlMsg(htmlTemplatePath);
email.setTextMsg(message);
// email.attach(attachment);
email.send();
status = true;
logger.info("success send mail to " + mailTo);
} catch (Exception e) {
logger.error("error send html mail to " + mailTo + " ..." , e);
}
return status;
}
public boolean sendHtmlMailWithImg(String mailTo,String mailObject,String message,String imgPath){
boolean status = false;
HtmlEmail email = new HtmlEmail();
email.setHostName(mailConfig.getSmtp());
email.setCharset(mailConfig.getCharset());
email.setAuthentication(mailConfig.getUser(), mailConfig.getPwd());
try {
email.addTo(mailTo);
email.setFrom(mailConfig.getUser());
email.setSubject(mailObject);
URL url = new URL(imgPath);
String cid = email.embed(url, "zhongyi logo");
email.setHtmlMsg("<html>The zhongyifoundry logo - <img src=\"cid:"+cid+"\"></html>");
email.send();
status = true;
} catch (Exception e) {
logger.error("error send html mail to " + mailTo + " ...", e);
}
return status;
}
public boolean sendMailWithAttachment(String mailTo,String mailObject,String message,List<String> attPathList){
boolean status = false;
HtmlEmail email = new HtmlEmail();
email.setHostName(mailConfig.getSmtp());
email.setCharset("GB2312");
email.setAuthentication(mailConfig.getUser(), mailConfig.getPwd());
EmailAttachment attachment = new EmailAttachment();
attachment.setPath("c:\\Sql Server导出数据至Oracle方法.doc");
attachment.setDisposition(EmailAttachment.ATTACHMENT);
attachment.setName("Sql Server导出数据至Oracle方法.doc");
String html = StringUtil.readHtmlToString("c:\\test.html");
try {
email.addTo("lysongfei@126.com");
email.setFrom("info@zhongyifoundry.com");
email.setSubject("common mail 附件发送测试 ");
email.setHtmlMsg(html);
email.attach(attachment);
email.send();
status = true;
} catch (Exception e) {
logger.error("error send html mail to " + mailTo + " ...", e);
}
return status;
}
private static Logger logger = Logger.getLogger(MailUtil.class);
}
| zytools | trunk/src/com/zhongyi/util/MailUtil.java | Java | asf20 | 4,431 |
package com.zhongyi.util;
public class MailConfiguration {
private String smtp;
private String pop;
private String user;
private String pwd;
private String charset;
private String smtp_port;
private String pop_port;
private String ssl;
public String getSmtp() {
return smtp;
}
public void setSmtp(String smtp) {
this.smtp = smtp;
}
public String getPop() {
return pop;
}
public void setPop(String pop) {
this.pop = pop;
}
public String getUser() {
return user;
}
public void setUser(String user) {
this.user = user;
}
public String getPwd() {
return pwd;
}
public void setPwd(String pwd) {
this.pwd = pwd;
}
public String getCharset() {
return charset;
}
public void setCharset(String charset) {
this.charset = charset;
}
public String getSmtp_port() {
return smtp_port;
}
public void setSmtp_port(String smtp_port) {
this.smtp_port = smtp_port;
}
public String getPop_port() {
return pop_port;
}
public void setPop_port(String pop_port) {
this.pop_port = pop_port;
}
public String getSsl() {
return ssl;
}
public void setSsl(String ssl) {
this.ssl = ssl;
}
}
| zytools | trunk/src/com/zhongyi/util/MailConfiguration.java | Java | asf20 | 1,199 |
package com.zhongyi.util;
import java.util.UUID;
/**
* UUID-32位ID生成器
* <p>
*
*
* @author <a href="mailto:lysongfie@gmail.com">songfei</a>
* @version 1.0,2012-2-25
*/
public class UUIDGenerator {
public static String create(){
String uuid = UUID.randomUUID().toString();
return uuid.replaceAll("-", "");
}
}
| zytools | trunk/src/com/zhongyi/util/UUIDGenerator.java | Java | asf20 | 353 |
package com.zhongyi.mail;
import java.io.File;
import java.io.FileInputStream;
import java.io.FileNotFoundException;
import java.io.IOException;
import java.nio.ByteBuffer;
import java.nio.channels.FileChannel;
public class TestNio {
public static void main(String[] args) {
String strFile = "c:\\test.html";
FileInputStream fis;
String htmlText = "";
try {
fis = new FileInputStream(new File(strFile));
FileChannel fc = fis.getChannel();
ByteBuffer bufer = ByteBuffer.allocate(1024);
byte[] by = new byte[1024];
while(fc.read(bufer) != -1){
htmlText += bufer.get(by).asCharBuffer().toString();
}
} catch (FileNotFoundException e) {
e.printStackTrace();
} catch (IOException e) {
e.printStackTrace();
}
System.out.println(htmlText);
}
}
| zytools | trunk/src/com/zhongyi/mail/TestNio.java | Java | asf20 | 817 |
package com.zhongyi.entity;
import java.sql.Timestamp;
/**
* 企业基础信息
* <p>
*
*
* @author <a href="mailto:lysongfei@gmail.com">songfei</a>
* @version 3.0, 2012-4-24
*/
public class Company {
private String id;
private String corp_name;
private String area_id;
private String adress;
private String origin_site;
private String home_page;
private String corp_level;
private String corp_type;
private String linker;
private String keyword;
private Timestamp create_time;
private String remark;
//表单临时赋值字段
private String email;
private String phone;
private String mobile;
private String fax;
public String getId() {
return id;
}
public void setId(String id) {
this.id = id;
}
public String getCorp_name() {
return corp_name;
}
public void setCorp_name(String corp_name) {
this.corp_name = corp_name;
}
public String getArea_id() {
return area_id;
}
public void setArea_id(String area_id) {
this.area_id = area_id;
}
public String getAdress() {
return adress;
}
public void setAdress(String adress) {
this.adress = adress;
}
public String getOrigin_site() {
return origin_site;
}
public void setOrigin_site(String origin_site) {
this.origin_site = origin_site;
}
public String getHome_page() {
return home_page;
}
public void setHome_page(String home_page) {
this.home_page = home_page;
}
public String getCorp_level() {
return corp_level;
}
public void setCorp_level(String corp_level) {
this.corp_level = corp_level;
}
public String getCorp_type() {
return corp_type;
}
public void setCorp_type(String corp_type) {
this.corp_type = corp_type;
}
public String getKeyword() {
return keyword;
}
public void setKeyword(String keyword) {
this.keyword = keyword;
}
public Timestamp getCreate_time() {
return create_time;
}
public void setCreate_time(Timestamp create_time) {
this.create_time = create_time;
}
public String getRemark() {
return remark;
}
public void setRemark(String remark) {
this.remark = remark;
}
public String getLinker() {
return linker;
}
public void setLinker(String linker) {
this.linker = linker;
}
public String getEmail() {
return email;
}
public void setEmail(String email) {
this.email = email;
}
public String getPhone() {
return phone;
}
public void setPhone(String phone) {
this.phone = phone;
}
public String getMobile() {
return mobile;
}
public void setMobile(String mobile) {
this.mobile = mobile;
}
public String getFax() {
return fax;
}
public void setFax(String fax) {
this.fax = fax;
}
} | zytools | trunk/src/com/zhongyi/entity/Company.java | Java | asf20 | 2,831 |
package com.zhongyi.entity;
import java.util.Date;
/**
* 系统日志信息
* <p>
*
*
* @author <a href="mailto:lysongfei@gmail.com">songfei</a>
* @version 3.0, 2012-4-24
*/
public class SysLog {
private String id;
private String contact_id;
private String contact_info;
private String info_type;
private String info_body;
private Date contact_time;
private String remark;
private String status;
public String getId() {
return id;
}
public void setId(String id) {
this.id = id;
}
public String getContact_id() {
return contact_id;
}
public void setContact_id(String contact_id) {
this.contact_id = contact_id;
}
public String getContact_info() {
return contact_info;
}
public void setContact_info(String contact_info) {
this.contact_info = contact_info;
}
public String getInfo_type() {
return info_type;
}
public void setInfo_type(String info_type) {
this.info_type = info_type;
}
public String getInfo_body() {
return info_body;
}
public void setInfo_body(String info_body) {
this.info_body = info_body;
}
public Date getContact_time() {
return contact_time;
}
public void setContact_time(Date contact_time) {
this.contact_time = contact_time;
}
public String getRemark() {
return remark;
}
public void setRemark(String remark) {
this.remark = remark;
}
public String getStatus() {
return status;
}
public void setStatus(String status) {
this.status = status;
}
}
| zytools | trunk/src/com/zhongyi/entity/SysLog.java | Java | asf20 | 1,574 |
package com.zhongyi.entity;
/**
* 全球区域信息
* <p>
*
*
* @author <a href="mailto:lysongfei@gmail.com">songfei</a>
* @version 3.0, 2012-4-24
*/
public class Area {
private String id;
private String parentId;
private String areaName;
private String remark;
public String getAreaName() {
return areaName;
}
public void setAreaName(String areaName) {
this.areaName = areaName;
}
public String getId() {
return id;
}
public void setId(String id) {
this.id = id;
}
public String getParentId() {
return parentId;
}
public void setParentId(String parentId) {
this.parentId = parentId;
}
public String getRemark() {
return remark;
}
public void setRemark(String remark) {
this.remark = remark;
}
}
| zytools | trunk/src/com/zhongyi/entity/Area.java | Java | asf20 | 816 |
package com.zhongyi.entity;
import java.sql.Timestamp;
/**
* 企业联系信息
* <p>
*
*
* @author <a href="mailto:lysongfie@gmail.com">songfei</a>
* @version 1.0,2012-2-27
*/
public class Contact {
private String id;
private String corp_id;
private String contact_info;
private String info_type; //信息类型（ 邮件：E 电话：P 手机：M 传真：F）
private String remark;
private Timestamp create_time;
private String is_msend;
public String getId() {
return id;
}
public void setId(String id) {
this.id = id;
}
public String getCorp_id() {
return corp_id;
}
public void setCorp_id(String corp_id) {
this.corp_id = corp_id;
}
public String getRemark() {
return remark;
}
public void setRemark(String remark) {
this.remark = remark;
}
public Timestamp getCreate_time() {
return create_time;
}
public void setCreate_time(Timestamp create_time) {
this.create_time = create_time;
}
public String getIs_msend() {
return is_msend;
}
public void setIs_msend(String is_msend) {
this.is_msend = is_msend;
}
public String getContact_info() {
return contact_info;
}
public void setContact_info(String contact_info) {
this.contact_info = contact_info;
}
public String getInfo_type() {
return info_type;
}
public void setInfo_type(String info_type) {
this.info_type = info_type;
}
}
| zytools | trunk/src/com/zhongyi/entity/Contact.java | Java | asf20 | 1,467 |
package com.zhongyi.search;
import java.io.IOException;
import java.util.regex.Matcher;
import java.util.regex.Pattern;
import org.apache.http.client.ClientProtocolException;
import org.apache.http.client.HttpClient;
import org.apache.http.client.ResponseHandler;
import org.apache.http.client.methods.HttpGet;
import org.apache.http.impl.client.BasicResponseHandler;
import org.apache.http.impl.client.DefaultHttpClient;
import org.htmlparser.Node;
import org.htmlparser.NodeFilter;
import org.htmlparser.Parser;
import org.htmlparser.filters.HasAttributeFilter;
import org.htmlparser.filters.TagNameFilter;
import org.htmlparser.tags.TableTag;
import org.htmlparser.util.NodeList;
import org.htmlparser.util.ParserException;
import org.htmlparser.util.SimpleNodeIterator;
public class TestSearch {
public static void main(String[] args) {
HttpClient httpclient = new DefaultHttpClient();
try {
HttpGet httpget = new HttpGet("http://www.ecplaza.net/trade-leads-buyer/required-a-regular-supplier-for--4747810.html");
System.out.println("executing request " + httpget.getURI());
// Create a response handler
ResponseHandler<String> responseHandler = new BasicResponseHandler();
String responseBody = httpclient.execute(httpget, responseHandler);
String matchString = parseHtml(responseBody);
// System.out.println("----------------------------------------");
System.out.println(responseBody);
// System.out.println("----------------------------------------");
} catch (ClientProtocolException e) {
// TODO Auto-generated catch block
e.printStackTrace();
} catch (IOException e) {
// TODO Auto-generated catch block
e.printStackTrace();
} finally {
// When HttpClient instance is no longer needed,
// shut down the connection manager to ensure
// immediate deallocation of all system resources
httpclient.getConnectionManager().shutdown();
}
}
public static String getMatchStringFromHtml(String htmlString,String[] regexs){
StringBuilder back = new StringBuilder("");
if(regexs != null){
Pattern p = null;
Matcher matcher = null;
for(String regex : regexs){
p = Pattern.compile(regex,Pattern.CASE_INSENSITIVE);
matcher = p.matcher(htmlString);
if(matcher.find()){
back.append(matcher.group());
}
}
}
return back.toString();
}
public static String parseHtml(String htmlString){
Parser parser = null;
TableTag tableTag = null;
NodeList nodeList = null;
NodeList tdNodes = null;
Node trNode = null;
Node thNode = null;
String thText = null;
SimpleNodeIterator nodeIter = null;
//CSS样式匹配
NodeFilter filter = new HasAttributeFilter("class", "contact_info");
try {
parser = new Parser(htmlString);
// parser.setURL("http://www.ecplaza.net/trade-leads-buyer/required-a-regular-supplier-for--4747810.html");
nodeList = parser.extractAllNodesThatMatch(filter);
tableTag = (TableTag) nodeList.elementAt(0);
nodeIter = tableTag.children();
while(nodeIter.hasMoreNodes()){
//TR节点
trNode = nodeIter.nextNode();
//TH子节点
tdNodes = trNode.getChildren().extractAllNodesThatMatch(new TagNameFilter("th"));
thNode = tdNodes.elementAt(0);
thText = thNode.getText();
//Company
if(thText != null && thText.indexOf("Company:") != -1){
System.out.println("Company:" + thNode.getNextSibling().getText());
}
if(thText != null && thText.indexOf("Country/Region:") != -1){
System.out.println("Country/Region:" + thNode.getNextSibling().getText());
}
if(thText != null && thText.indexOf("Address:") != -1){
System.out.println("Address:" + thNode.getNextSibling().getText());
}
if(thText != null && thText.indexOf("Contact:") != -1){
System.out.println("Contact:" + thNode.getNextSibling().getText());
}
if(thText != null && thText.indexOf("Phone:") != -1){
System.out.println("Phone:" + thNode.getNextSibling().getText());
}
if(thText != null && thText.indexOf("Fax:") != -1){
System.out.println("Fax:" + thNode.getNextSibling().getText());
}
if(thText != null && thText.indexOf("Mobile:") != -1){
System.out.println("Mobile:" + thNode.getNextSibling().getText());
}
if(thText != null && thText.indexOf("Tags:") != -1){
System.out.println("Tags:" + thNode.getNextSibling().getText());
}
}
} catch (ParserException e) {
e.printStackTrace();
}
return null;
}
}
| zytools | trunk/src/com/zhongyi/search/TestSearch.java | Java | asf20 | 4,745 |
package com.st.android.adkping;
import android.app.Activity;
import android.content.BroadcastReceiver;
import android.content.Context;
import android.content.Intent;
import android.content.IntentFilter;
import android.os.Bundle;
import android.os.Handler;
import android.os.Message;
import android.os.ParcelFileDescriptor;
import android.text.method.ScrollingMovementMethod;
import android.view.View;
import android.view.View.OnClickListener;
import android.widget.Button;
import android.widget.EditText;
import android.widget.LinearLayout;
import android.widget.ScrollView;
import android.widget.TextView;
import com.android.future.usb.UsbAccessory;
import com.android.future.usb.UsbManager;
import org.slf4j.Logger;
import org.slf4j.LoggerFactory;
import java.io.FileDescriptor;
import java.io.FileInputStream;
import java.io.FileOutputStream;
import java.io.IOException;
public class ADKPing extends Activity implements Runnable
{
private final Logger logger = LoggerFactory.getLogger("ADKPing");
private UsbManager usbManager;
UsbAccessory accessory;
ParcelFileDescriptor accessoryFileDescriptor;
FileInputStream accessoryInput;
FileOutputStream accessoryOutput;
LinearLayout layout;
ScrollView scrollView;
TextView logTextView;
EditText messageText;
Button setTextbutton;
String messageString;
Handler mHandler;
private final BroadcastReceiver usbBroadcastReceiver = new BroadcastReceiver()
{
public void onReceive(Context context, Intent intent)
{
String action = intent.getAction();
if (UsbManager.ACTION_USB_ACCESSORY_ATTACHED.equals(action)){
synchronized (this){
accessory = UsbManager.getAccessory(intent);
}
}
else if (UsbManager.ACTION_USB_ACCESSORY_DETACHED.equals(action)){
UsbAccessory accessory = UsbManager.getAccessory(intent);
if (accessory != null)
{
// call your method that cleans up and closes communication with the accessory
}
}
}
};
/* Inter-thread communication for appending debug text in UI */
void sendText(String text)
{
Message msg = new Message();
msg.obj = text;
mHandler.sendMessage(msg);
}
/**
* Main USB reading loop, processing incoming data from accessory
*/
public void run()
{
int ret = 0;
byte[] buffer = new byte[16384];
while(true){
try{
sendText("Receiving data\n");
/* Receive buffer */
ret = accessoryInput.read(buffer);
sendText("Received " + ret + " bytes\n");
/* Prepare reply buffer */
int i;
for(i=0; i<buffer.length; i++){
if(buffer[i] == 0) break;
}
String stringToSend = new String(buffer, 0, i, "US-ASCII") + " " + messageString;
byte[] bufferToSend = stringToSend.getBytes("US-ASCII");
/* Send buffer */
sendText("Sending back " + bufferToSend.length + " bytes\n");
accessoryOutput.write(bufferToSend, 0, bufferToSend.length);
sendText("Sent\n");
}
catch (IOException e){
/* Just get out */
sendText("Exception in reading/writing accessory\n");
logger.debug("Exception in USB accessory input reading", e);
break;
}
}
}
/* Scrolls the textview to the end */
private void scrollToEnd()
{
/* A simple scrollView.fullScroll(View.FOCUS_DOWN) wont work, as
* the layout has not happened yet :/
* Cfr.: http://stackoverflow.com/questions/3087877/scroll-to-last-line-of-tablelayout-within-a-scrollview
* */
scrollView.post(new Runnable() {
public void run() {
scrollView.fullScroll(View.FOCUS_DOWN);
}
});
}
@Override
public void onCreate(Bundle savedInstanceState)
{
super.onCreate(savedInstanceState);
usbManager = UsbManager.getInstance(this);
/* Handle the Accessory stuff */
IntentFilter filter = new IntentFilter(UsbManager.ACTION_USB_ACCESSORY_ATTACHED);
filter.addAction(UsbManager.ACTION_USB_ACCESSORY_DETACHED);
registerReceiver(usbBroadcastReceiver, filter);
if (getLastNonConfigurationInstance() != null){
accessory = (UsbAccessory) getLastNonConfigurationInstance();
openAccessory(accessory);
}
/* Set up the UI */
setContentView(R.layout.main);
logTextView = (TextView)findViewById(R.id.logTextView);
scrollView = (ScrollView)findViewById(R.id.ScrollView01);
messageText = (EditText)findViewById(R.id.editText);
setTextbutton = (Button)findViewById(R.id.setTextButton);
setTextbutton.setOnClickListener(new OnClickListener() {
@Override
public void onClick(View v) {
messageString = messageText.getText().toString();
}
});
/* Set up message handler used to update the UI from different thread
* which would crash UI with "CalledFromWrongThreadException" otherwise
*/
mHandler = new Handler()
{
@Override
public void handleMessage(Message msg)
{
String text = (String)msg.obj;
logTextView.append(text);
//msg.recycle();
scrollToEnd();
}
};
byte[] buffer = new byte[128];
buffer[0] = 'c';
buffer[1] = 'i';
buffer[2] = 'a';
buffer[3] = 'o';
buffer[4] = 0;
String test = null;
try{
test = new String(buffer, "US-ASCII");
}
catch(Exception e){
logger.debug("Exception:" + e);
};
logger.debug(test);
logger.debug("String length is " + test.length());
}
@Override
public Object onRetainNonConfigurationInstance()
{
return accessory != null ? accessory : super.onRetainNonConfigurationInstance();
}
@Override
public void onResume()
{
super.onResume();
Intent intent = getIntent();
if (accessoryInput != null && accessoryOutput != null)
return;
// TODO: verify, docs don't do this simple thing, not sure why?
UsbAccessory accessory = UsbManager.getAccessory(intent);
if (accessory != null)
openAccessory(accessory);
else
logger.error("Failed to resume accessory.");
}
@Override
public void onPause()
{
super.onPause();
closeAccessory();//daz dont we need to set accessory null ?
}
@Override
public void onDestroy()
{
unregisterReceiver(usbBroadcastReceiver);
super.onDestroy();
}
private void openAccessory(UsbAccessory accessory)
{
accessoryFileDescriptor = usbManager.openAccessory(accessory);
if (accessoryFileDescriptor != null)
{
this.accessory = accessory;
FileDescriptor fd = accessoryFileDescriptor.getFileDescriptor();
accessoryInput = new FileInputStream(fd);
accessoryOutput = new FileOutputStream(fd);
Thread thread = new Thread(null, this, "ADKPingThread");
thread.start();
logTextView.append("Accessory Opened\n");
logger.debug("accessory opened");
// TODO: enable USB operations in the app
}
else{
logTextView.append("Accessory failed\n");
logger.debug("accessory open fail");
}
}
private void closeAccessory()
{
// TODO: disable USB operations in the app
try{
if(accessoryFileDescriptor != null)
accessoryFileDescriptor.close();
}
catch (IOException e)
{}
finally{
accessoryFileDescriptor = null;
accessory = null;
}
}
}
| zz314326255--adkping | adkping/ADKPing/src/com/st/android/adkping/ADKPing.java | Java | oos | 7,060 |
/**
******************************************************************************
* @file stm32f10x_crc.h
* @author MCD Application Team
* @version V3.0.0
* @date 04/06/2009
* @brief This file contains all the functions prototypes for the CRC firmware
* library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_CRC_H
#define __STM32F10x_CRC_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @addtogroup CRC
* @{
*/
/** @defgroup CRC_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup CRC_Exported_Constants
* @{
*/
/**
* @}
*/
/** @defgroup CRC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup CRC_Exported_Functions
* @{
*/
void CRC_ResetDR(void);
uint32_t CRC_CalcCRC(uint32_t Data);
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
uint32_t CRC_GetCRC(void);
void CRC_SetIDRegister(uint8_t IDValue);
uint8_t CRC_GetIDRegister(void);
#endif /* __STM32F10x_CRC_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_crc.h | C | oos | 1,980 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : cortexm3_macro.h
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : Header file for cortexm3_macro.s.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __CORTEXM3_MACRO_H
#define __CORTEXM3_MACRO_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_type.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void __WFI(void);
void __WFE(void);
void __SEV(void);
void __ISB(void);
void __DSB(void);
void __DMB(void);
void __SVC(void);
u32 __MRS_CONTROL(void);
void __MSR_CONTROL(u32 Control);
void __SETPRIMASK(void);
void __RESETPRIMASK(void);
void __SETFAULTMASK(void);
void __RESETFAULTMASK(void);
void __BASEPRICONFIG(u32 NewPriority);
u32 __GetBASEPRI(void);
u16 __REV_HalfWord(u16 Data);
u32 __REV_Word(u32 Data);
#endif /* __CORTEXM3_MACRO_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/cortexm3_macro.h | C | oos | 2,172 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_rcc.h
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file contains all the functions prototypes for the
* RCC firmware library.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_RCC_H
#define __STM32F10x_RCC_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
typedef struct
{
u32 SYSCLK_Frequency;
u32 HCLK_Frequency;
u32 PCLK1_Frequency;
u32 PCLK2_Frequency;
u32 ADCCLK_Frequency;
}RCC_ClocksTypeDef;
/* Exported constants --------------------------------------------------------*/
/* HSE configuration */
#define RCC_HSE_OFF ((u32)0x00000000)
#define RCC_HSE_ON ((u32)0x00010000)
#define RCC_HSE_Bypass ((u32)0x00040000)
#define IS_RCC_HSE(HSE) ((HSE == RCC_HSE_OFF) || (HSE == RCC_HSE_ON) || \
(HSE == RCC_HSE_Bypass))
/* PLL entry clock source */
#define RCC_PLLSource_HSI_Div2 ((u32)0x00000000)
#define RCC_PLLSource_HSE_Div1 ((u32)0x00010000)
#define RCC_PLLSource_HSE_Div2 ((u32)0x00030000)
#define IS_RCC_PLL_SOURCE(SOURCE) ((SOURCE == RCC_PLLSource_HSI_Div2) || \
(SOURCE == RCC_PLLSource_HSE_Div1) || \
(SOURCE == RCC_PLLSource_HSE_Div2))
/* PLL multiplication factor */
#define RCC_PLLMul_2 ((u32)0x00000000)
#define RCC_PLLMul_3 ((u32)0x00040000)
#define RCC_PLLMul_4 ((u32)0x00080000)
#define RCC_PLLMul_5 ((u32)0x000C0000)
#define RCC_PLLMul_6 ((u32)0x00100000)
#define RCC_PLLMul_7 ((u32)0x00140000)
#define RCC_PLLMul_8 ((u32)0x00180000)
#define RCC_PLLMul_9 ((u32)0x001C0000)
#define RCC_PLLMul_10 ((u32)0x00200000)
#define RCC_PLLMul_11 ((u32)0x00240000)
#define RCC_PLLMul_12 ((u32)0x00280000)
#define RCC_PLLMul_13 ((u32)0x002C0000)
#define RCC_PLLMul_14 ((u32)0x00300000)
#define RCC_PLLMul_15 ((u32)0x00340000)
#define RCC_PLLMul_16 ((u32)0x00380000)
#define IS_RCC_PLL_MUL(MUL) ((MUL == RCC_PLLMul_2) || (MUL == RCC_PLLMul_3) ||\
(MUL == RCC_PLLMul_4) || (MUL == RCC_PLLMul_5) ||\
(MUL == RCC_PLLMul_6) || (MUL == RCC_PLLMul_7) ||\
(MUL == RCC_PLLMul_8) || (MUL == RCC_PLLMul_9) ||\
(MUL == RCC_PLLMul_10) || (MUL == RCC_PLLMul_11) ||\
(MUL == RCC_PLLMul_12) || (MUL == RCC_PLLMul_13) ||\
(MUL == RCC_PLLMul_14) || (MUL == RCC_PLLMul_15) ||\
(MUL == RCC_PLLMul_16))
/* System clock source */
#define RCC_SYSCLKSource_HSI ((u32)0x00000000)
#define RCC_SYSCLKSource_HSE ((u32)0x00000001)
#define RCC_SYSCLKSource_PLLCLK ((u32)0x00000002)
#define IS_RCC_SYSCLK_SOURCE(SOURCE) ((SOURCE == RCC_SYSCLKSource_HSI) || \
(SOURCE == RCC_SYSCLKSource_HSE) || \
(SOURCE == RCC_SYSCLKSource_PLLCLK))
/* AHB clock source */
#define RCC_SYSCLK_Div1 ((u32)0x00000000)
#define RCC_SYSCLK_Div2 ((u32)0x00000080)
#define RCC_SYSCLK_Div4 ((u32)0x00000090)
#define RCC_SYSCLK_Div8 ((u32)0x000000A0)
#define RCC_SYSCLK_Div16 ((u32)0x000000B0)
#define RCC_SYSCLK_Div64 ((u32)0x000000C0)
#define RCC_SYSCLK_Div128 ((u32)0x000000D0)
#define RCC_SYSCLK_Div256 ((u32)0x000000E0)
#define RCC_SYSCLK_Div512 ((u32)0x000000F0)
#define IS_RCC_HCLK(HCLK) ((HCLK == RCC_SYSCLK_Div1) || (HCLK == RCC_SYSCLK_Div2) || \
(HCLK == RCC_SYSCLK_Div4) || (HCLK == RCC_SYSCLK_Div8) || \
(HCLK == RCC_SYSCLK_Div16) || (HCLK == RCC_SYSCLK_Div64) || \
(HCLK == RCC_SYSCLK_Div128) || (HCLK == RCC_SYSCLK_Div256) || \
(HCLK == RCC_SYSCLK_Div512))
/* APB1/APB2 clock source */
#define RCC_HCLK_Div1 ((u32)0x00000000)
#define RCC_HCLK_Div2 ((u32)0x00000400)
#define RCC_HCLK_Div4 ((u32)0x00000500)
#define RCC_HCLK_Div8 ((u32)0x00000600)
#define RCC_HCLK_Div16 ((u32)0x00000700)
#define IS_RCC_PCLK(PCLK) ((PCLK == RCC_HCLK_Div1) || (PCLK == RCC_HCLK_Div2) || \
(PCLK == RCC_HCLK_Div4) || (PCLK == RCC_HCLK_Div8) || \
(PCLK == RCC_HCLK_Div16))
/* RCC Interrupt source */
#define RCC_IT_LSIRDY ((u8)0x01)
#define RCC_IT_LSERDY ((u8)0x02)
#define RCC_IT_HSIRDY ((u8)0x04)
#define RCC_IT_HSERDY ((u8)0x08)
#define RCC_IT_PLLRDY ((u8)0x10)
#define RCC_IT_CSS ((u8)0x80)
#define IS_RCC_IT(IT) (((IT & (u8)0xE0) == 0x00) && (IT != 0x00))
#define IS_RCC_GET_IT(IT) ((IT == RCC_IT_LSIRDY) || (IT == RCC_IT_LSERDY) || \
(IT == RCC_IT_HSIRDY) || (IT == RCC_IT_HSERDY) || \
(IT == RCC_IT_PLLRDY) || (IT == RCC_IT_CSS))
#define IS_RCC_CLEAR_IT(IT) (((IT & (u8)0x60) == 0x00) && (IT != 0x00))
/* USB clock source */
#define RCC_USBCLKSource_PLLCLK_1Div5 ((u8)0x00)
#define RCC_USBCLKSource_PLLCLK_Div1 ((u8)0x01)
#define IS_RCC_USBCLK_SOURCE(SOURCE) ((SOURCE == RCC_USBCLKSource_PLLCLK_1Div5) || \
(SOURCE == RCC_USBCLKSource_PLLCLK_Div1))
/* ADC clock source */
#define RCC_PCLK2_Div2 ((u32)0x00000000)
#define RCC_PCLK2_Div4 ((u32)0x00004000)
#define RCC_PCLK2_Div6 ((u32)0x00008000)
#define RCC_PCLK2_Div8 ((u32)0x0000C000)
#define IS_RCC_ADCCLK(ADCCLK) ((ADCCLK == RCC_PCLK2_Div2) || (ADCCLK == RCC_PCLK2_Div4) || \
(ADCCLK == RCC_PCLK2_Div6) || (ADCCLK == RCC_PCLK2_Div8))
/* LSE configuration */
#define RCC_LSE_OFF ((u8)0x00)
#define RCC_LSE_ON ((u8)0x01)
#define RCC_LSE_Bypass ((u8)0x04)
#define IS_RCC_LSE(LSE) ((LSE == RCC_LSE_OFF) || (LSE == RCC_LSE_ON) || \
(LSE == RCC_LSE_Bypass))
/* RTC clock source */
#define RCC_RTCCLKSource_LSE ((u32)0x00000100)
#define RCC_RTCCLKSource_LSI ((u32)0x00000200)
#define RCC_RTCCLKSource_HSE_Div128 ((u32)0x00000300)
#define IS_RCC_RTCCLK_SOURCE(SOURCE) ((SOURCE == RCC_RTCCLKSource_LSE) || \
(SOURCE == RCC_RTCCLKSource_LSI) || \
(SOURCE == RCC_RTCCLKSource_HSE_Div128))
/* AHB peripheral */
#define RCC_AHBPeriph_DMA ((u32)0x00000001)
#define RCC_AHBPeriph_SRAM ((u32)0x00000004)
#define RCC_AHBPeriph_FLITF ((u32)0x00000010)
#define IS_RCC_AHB_PERIPH(PERIPH) (((PERIPH & 0xFFFFFFEA) == 0x00) && (PERIPH != 0x00))
/* APB2 peripheral */
#define RCC_APB2Periph_AFIO ((u32)0x00000001)
#define RCC_APB2Periph_GPIOA ((u32)0x00000004)
#define RCC_APB2Periph_GPIOB ((u32)0x00000008)
#define RCC_APB2Periph_GPIOC ((u32)0x00000010)
#define RCC_APB2Periph_GPIOD ((u32)0x00000020)
#define RCC_APB2Periph_GPIOE ((u32)0x00000040)
#define RCC_APB2Periph_ADC1 ((u32)0x00000200)
#define RCC_APB2Periph_ADC2 ((u32)0x00000400)
#define RCC_APB2Periph_TIM1 ((u32)0x00000800)
#define RCC_APB2Periph_SPI1 ((u32)0x00001000)
#define RCC_APB2Periph_USART1 ((u32)0x00004000)
#define RCC_APB2Periph_ALL ((u32)0x00005E7D)
#define IS_RCC_APB2_PERIPH(PERIPH) (((PERIPH & 0xFFFFA182) == 0x00) && (PERIPH != 0x00))
/* APB1 peripheral */
#define RCC_APB1Periph_TIM2 ((u32)0x00000001)
#define RCC_APB1Periph_TIM3 ((u32)0x00000002)
#define RCC_APB1Periph_TIM4 ((u32)0x00000004)
#define RCC_APB1Periph_WWDG ((u32)0x00000800)
#define RCC_APB1Periph_SPI2 ((u32)0x00004000)
#define RCC_APB1Periph_USART2 ((u32)0x00020000)
#define RCC_APB1Periph_USART3 ((u32)0x00040000)
#define RCC_APB1Periph_I2C1 ((u32)0x00200000)
#define RCC_APB1Periph_I2C2 ((u32)0x00400000)
#define RCC_APB1Periph_USB ((u32)0x00800000)
#define RCC_APB1Periph_CAN ((u32)0x02000000)
#define RCC_APB1Periph_BKP ((u32)0x08000000)
#define RCC_APB1Periph_PWR ((u32)0x10000000)
#define RCC_APB1Periph_ALL ((u32)0x1AE64807)
#define IS_RCC_APB1_PERIPH(PERIPH) (((PERIPH & 0xE519B7F8) == 0x00) && (PERIPH != 0x00))
/* Clock source to output on MCO pin */
#define RCC_MCO_NoClock ((u8)0x00)
#define RCC_MCO_SYSCLK ((u8)0x04)
#define RCC_MCO_HSI ((u8)0x05)
#define RCC_MCO_HSE ((u8)0x06)
#define RCC_MCO_PLLCLK_Div2 ((u8)0x07)
#define IS_RCC_MCO(MCO) ((MCO == RCC_MCO_NoClock) || (MCO == RCC_MCO_HSI) || \
(MCO == RCC_MCO_SYSCLK) || (MCO == RCC_MCO_HSE) || \
(MCO == RCC_MCO_PLLCLK_Div2))
/* RCC Flag */
#define RCC_FLAG_HSIRDY ((u8)0x20)
#define RCC_FLAG_HSERDY ((u8)0x31)
#define RCC_FLAG_PLLRDY ((u8)0x39)
#define RCC_FLAG_LSERDY ((u8)0x41)
#define RCC_FLAG_LSIRDY ((u8)0x61)
#define RCC_FLAG_PINRST ((u8)0x7A)
#define RCC_FLAG_PORRST ((u8)0x7B)
#define RCC_FLAG_SFTRST ((u8)0x7C)
#define RCC_FLAG_IWDGRST ((u8)0x7D)
#define RCC_FLAG_WWDGRST ((u8)0x7E)
#define RCC_FLAG_LPWRRST ((u8)0x7F)
#define IS_RCC_FLAG(FLAG) ((FLAG == RCC_FLAG_HSIRDY) || (FLAG == RCC_FLAG_HSERDY) || \
(FLAG == RCC_FLAG_PLLRDY) || (FLAG == RCC_FLAG_LSERDY) || \
(FLAG == RCC_FLAG_LSIRDY) || (FLAG == RCC_FLAG_PINRST) || \
(FLAG == RCC_FLAG_PORRST) || (FLAG == RCC_FLAG_SFTRST) || \
(FLAG == RCC_FLAG_IWDGRST)|| (FLAG == RCC_FLAG_WWDGRST)|| \
(FLAG == RCC_FLAG_LPWRRST))
#define IS_RCC_CALIBRATION_VALUE(VALUE) (VALUE <= 0x1F)
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void RCC_DeInit(void);
void RCC_HSEConfig(u32 RCC_HSE);
void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue);
void RCC_HSICmd(FunctionalState NewState);
void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul);
void RCC_PLLCmd(FunctionalState NewState);
void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource);
u8 RCC_GetSYSCLKSource(void);
void RCC_HCLKConfig(u32 RCC_HCLK);
void RCC_PCLK1Config(u32 RCC_PCLK1);
void RCC_PCLK2Config(u32 RCC_PCLK2);
void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState);
void RCC_USBCLKConfig(u32 RCC_USBCLKSource);
void RCC_ADCCLKConfig(u32 RCC_ADCCLK);
void RCC_LSEConfig(u32 RCC_LSE);
void RCC_LSICmd(FunctionalState NewState);
void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource);
void RCC_RTCCLKCmd(FunctionalState NewState);
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState);
void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState);
void RCC_BackupResetCmd(FunctionalState NewState);
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
void RCC_MCOConfig(u8 RCC_MCO);
FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG);
void RCC_ClearFlag(void);
ITStatus RCC_GetITStatus(u8 RCC_IT);
void RCC_ClearITPendingBit(u8 RCC_IT);
#endif /* __STM32F10x_RCC_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_rcc.h | C | oos | 13,794 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_adc.h
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file contains all the functions prototypes for the
* ADC firmware library.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_ADC_H
#define __STM32F10x_ADC_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* ADC Init structure definition */
typedef struct
{
u32 ADC_Mode;
FunctionalState ADC_ScanConvMode;
FunctionalState ADC_ContinuousConvMode;
u32 ADC_ExternalTrigConv;
u32 ADC_DataAlign;
u8 ADC_NbrOfChannel;
}ADC_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/* ADC dual mode -------------------------------------------------------------*/
#define ADC_Mode_Independent ((u32)0x00000000)
#define ADC_Mode_RegInjecSimult ((u32)0x00010000)
#define ADC_Mode_RegSimult_AlterTrig ((u32)0x00020000)
#define ADC_Mode_InjecSimult_FastInterl ((u32)0x00030000)
#define ADC_Mode_InjecSimult_SlowInterl ((u32)0x00040000)
#define ADC_Mode_InjecSimult ((u32)0x00050000)
#define ADC_Mode_RegSimult ((u32)0x00060000)
#define ADC_Mode_FastInterl ((u32)0x00070000)
#define ADC_Mode_SlowInterl ((u32)0x00080000)
#define ADC_Mode_AlterTrig ((u32)0x00090000)
#define IS_ADC_MODE(MODE) ((MODE == ADC_Mode_Independent) || \
(MODE == ADC_Mode_RegInjecSimult) || \
(MODE == ADC_Mode_RegSimult_AlterTrig) || \
(MODE == ADC_Mode_InjecSimult_FastInterl) || \
(MODE == ADC_Mode_InjecSimult_SlowInterl) || \
(MODE == ADC_Mode_InjecSimult) || \
(MODE == ADC_Mode_RegSimult) || \
(MODE == ADC_Mode_FastInterl) || \
(MODE == ADC_Mode_SlowInterl) || \
(MODE == ADC_Mode_AlterTrig))
/* ADC extrenal trigger sources for regular channels conversion --------------*/
#define ADC_ExternalTrigConv_T1_CC1 ((u32)0x00000000)
#define ADC_ExternalTrigConv_T1_CC2 ((u32)0x00020000)
#define ADC_ExternalTrigConv_T1_CC3 ((u32)0x00040000)
#define ADC_ExternalTrigConv_T2_CC2 ((u32)0x00060000)
#define ADC_ExternalTrigConv_T3_TRGO ((u32)0x00080000)
#define ADC_ExternalTrigConv_T4_CC4 ((u32)0x000A0000)
#define ADC_ExternalTrigConv_Ext_IT11 ((u32)0x000C0000)
#define ADC_ExternalTrigConv_None ((u32)0x000E0000)
#define IS_ADC_EXT_TRIG(TRIG1) ((TRIG1 == ADC_ExternalTrigConv_T1_CC1) || \
(TRIG1 == ADC_ExternalTrigConv_T1_CC2) || \
(TRIG1 == ADC_ExternalTrigConv_T1_CC3) || \
(TRIG1 == ADC_ExternalTrigConv_T2_CC2) || \
(TRIG1 == ADC_ExternalTrigConv_T3_TRGO) || \
(TRIG1 == ADC_ExternalTrigConv_T4_CC4) || \
(TRIG1 == ADC_ExternalTrigConv_Ext_IT11) || \
(TRIG1 == ADC_ExternalTrigConv_None))
/* ADC data align ------------------------------------------------------------*/
#define ADC_DataAlign_Right ((u32)0x00000000)
#define ADC_DataAlign_Left ((u32)0x00000800)
#define IS_ADC_DATA_ALIGN(ALIGN) ((ALIGN == ADC_DataAlign_Right) || \
(ALIGN == ADC_DataAlign_Left))
/* ADC channels --------------------------------------------------------------*/
#define ADC_Channel_0 ((u8)0x00)
#define ADC_Channel_1 ((u8)0x01)
#define ADC_Channel_2 ((u8)0x02)
#define ADC_Channel_3 ((u8)0x03)
#define ADC_Channel_4 ((u8)0x04)
#define ADC_Channel_5 ((u8)0x05)
#define ADC_Channel_6 ((u8)0x06)
#define ADC_Channel_7 ((u8)0x07)
#define ADC_Channel_8 ((u8)0x08)
#define ADC_Channel_9 ((u8)0x09)
#define ADC_Channel_10 ((u8)0x0A)
#define ADC_Channel_11 ((u8)0x0B)
#define ADC_Channel_12 ((u8)0x0C)
#define ADC_Channel_13 ((u8)0x0D)
#define ADC_Channel_14 ((u8)0x0E)
#define ADC_Channel_15 ((u8)0x0F)
#define ADC_Channel_16 ((u8)0x10)
#define ADC_Channel_17 ((u8)0x11)
#define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL == ADC_Channel_0) || (CHANNEL == ADC_Channel_1) || \
(CHANNEL == ADC_Channel_2) || (CHANNEL == ADC_Channel_3) || \
(CHANNEL == ADC_Channel_4) || (CHANNEL == ADC_Channel_5) || \
(CHANNEL == ADC_Channel_6) || (CHANNEL == ADC_Channel_7) || \
(CHANNEL == ADC_Channel_8) || (CHANNEL == ADC_Channel_9) || \
(CHANNEL == ADC_Channel_10) || (CHANNEL == ADC_Channel_11) || \
(CHANNEL == ADC_Channel_12) || (CHANNEL == ADC_Channel_13) || \
(CHANNEL == ADC_Channel_14) || (CHANNEL == ADC_Channel_15) || \
(CHANNEL == ADC_Channel_16) || (CHANNEL == ADC_Channel_17))
/* ADC sampling times --------------------------------------------------------*/
#define ADC_SampleTime_1Cycles5 ((u8)0x00)
#define ADC_SampleTime_7Cycles5 ((u8)0x01)
#define ADC_SampleTime_13Cycles5 ((u8)0x02)
#define ADC_SampleTime_28Cycles5 ((u8)0x03)
#define ADC_SampleTime_41Cycles5 ((u8)0x04)
#define ADC_SampleTime_55Cycles5 ((u8)0x05)
#define ADC_SampleTime_71Cycles5 ((u8)0x06)
#define ADC_SampleTime_239Cycles5 ((u8)0x07)
#define IS_ADC_SAMPLE_TIME(TIME) ((TIME == ADC_SampleTime_1Cycles5) || \
(TIME == ADC_SampleTime_7Cycles5) || \
(TIME == ADC_SampleTime_13Cycles5) || \
(TIME == ADC_SampleTime_28Cycles5) || \
(TIME == ADC_SampleTime_41Cycles5) || \
(TIME == ADC_SampleTime_55Cycles5) || \
(TIME == ADC_SampleTime_71Cycles5) || \
(TIME == ADC_SampleTime_239Cycles5))
/* ADC extrenal trigger sources for injected channels conversion -------------*/
#define ADC_ExternalTrigInjecConv_T1_TRGO ((u32)0x00000000)
#define ADC_ExternalTrigInjecConv_T1_CC4 ((u32)0x00001000)
#define ADC_ExternalTrigInjecConv_T2_TRGO ((u32)0x00002000)
#define ADC_ExternalTrigInjecConv_T2_CC1 ((u32)0x00003000)
#define ADC_ExternalTrigInjecConv_T3_CC4 ((u32)0x00004000)
#define ADC_ExternalTrigInjecConv_T4_TRGO ((u32)0x00005000)
#define ADC_ExternalTrigInjecConv_Ext_IT15 ((u32)0x00006000)
#define ADC_ExternalTrigInjecConv_None ((u32)0x00007000)
#define IS_ADC_EXT_INJEC_TRIG(TRIG) ((TRIG == ADC_ExternalTrigInjecConv_T1_TRGO) || \
(TRIG == ADC_ExternalTrigInjecConv_T1_CC4) || \
(TRIG == ADC_ExternalTrigInjecConv_T2_TRGO) || \
(TRIG == ADC_ExternalTrigInjecConv_T2_CC1) || \
(TRIG == ADC_ExternalTrigInjecConv_T3_CC4) || \
(TRIG == ADC_ExternalTrigInjecConv_T4_TRGO) || \
(TRIG == ADC_ExternalTrigInjecConv_Ext_IT15) || \
(TRIG == ADC_ExternalTrigInjecConv_None))
/* ADC injected channel selection --------------------------------------------*/
#define ADC_InjectedChannel_1 ((u8)0x14)
#define ADC_InjectedChannel_2 ((u8)0x18)
#define ADC_InjectedChannel_3 ((u8)0x1C)
#define ADC_InjectedChannel_4 ((u8)0x20)
#define IS_ADC_INJECTED_CHANNEL(CHANNEL) ((CHANNEL == ADC_InjectedChannel_1) || \
(CHANNEL == ADC_InjectedChannel_2) || \
(CHANNEL == ADC_InjectedChannel_3) || \
(CHANNEL == ADC_InjectedChannel_4))
/* ADC analog watchdog selection ---------------------------------------------*/
#define ADC_AnalogWatchdog_SingleRegEnable ((u32)0x00800200)
#define ADC_AnalogWatchdog_SingleInjecEnable ((u32)0x00400200)
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((u32)0x00C00200)
#define ADC_AnalogWatchdog_AllRegEnable ((u32)0x00800000)
#define ADC_AnalogWatchdog_AllInjecEnable ((u32)0x00400000)
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((u32)0x00C00000)
#define ADC_AnalogWatchdog_None ((u32)0x00000000)
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) ((WATCHDOG == ADC_AnalogWatchdog_SingleRegEnable) || \
(WATCHDOG == ADC_AnalogWatchdog_SingleInjecEnable) || \
(WATCHDOG == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
(WATCHDOG == ADC_AnalogWatchdog_AllRegEnable) || \
(WATCHDOG == ADC_AnalogWatchdog_AllInjecEnable) || \
(WATCHDOG == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
(WATCHDOG == ADC_AnalogWatchdog_None))
/* ADC interrupts definition -------------------------------------------------*/
#define ADC_IT_EOC ((u16)0x0220)
#define ADC_IT_AWD ((u16)0x0140)
#define ADC_IT_JEOC ((u16)0x0480)
#define IS_ADC_IT(IT) (((IT & (u16)0xF81F) == 0x00) && (IT != 0x00))
#define IS_ADC_GET_IT(IT) ((IT == ADC_IT_EOC) || (IT == ADC_IT_AWD) || \
(IT == ADC_IT_JEOC))
/* ADC flags definition ------------------------------------------------------*/
#define ADC_FLAG_AWD ((u8)0x01)
#define ADC_FLAG_EOC ((u8)0x02)
#define ADC_FLAG_JEOC ((u8)0x04)
#define ADC_FLAG_JSTRT ((u8)0x08)
#define ADC_FLAG_STRT ((u8)0x10)
#define IS_ADC_CLEAR_FLAG(FLAG) (((FLAG & (u8)0xE0) == 0x00) && (FLAG != 0x00))
#define IS_ADC_GET_FLAG(FLAG) ((FLAG == ADC_FLAG_AWD) || (FLAG == ADC_FLAG_EOC) || \
(FLAG == ADC_FLAG_JEOC) || (FLAG == ADC_FLAG_JSTRT) || \
(FLAG == ADC_FLAG_STRT))
/* ADC thresholds ------------------------------------------------------------*/
#define IS_ADC_THRESHOLD(THRESHOLD) (THRESHOLD <= 0xFFF)
/* ADC injected offset -------------------------------------------------------*/
#define IS_ADC_OFFSET(OFFSET) (OFFSET <= 0xFFF)
/* ADC injected length -------------------------------------------------------*/
#define IS_ADC_INJECTED_LENGTH(LENGTH) ((LENGTH >= 0x1) && (LENGTH <= 0x4))
/* ADC injected rank ---------------------------------------------------------*/
#define IS_ADC_INJECTED_RANK(RANK) ((RANK >= 0x1) && (RANK <= 0x4))
/* ADC regular length --------------------------------------------------------*/
#define IS_ADC_REGULAR_LENGTH(LENGTH) ((LENGTH >= 0x1) && (LENGTH <= 0x10))
/* ADC regular rank ----------------------------------------------------------*/
#define IS_ADC_REGULAR_RANK(RANK) ((RANK >= 0x1) && (RANK <= 0x10))
/* ADC regular discontinuous mode number -------------------------------------*/
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) ((NUMBER >= 0x1) && (NUMBER <= 0x8))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void ADC_DeInit(ADC_TypeDef* ADCx);
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_ITConfig(ADC_TypeDef* ADCx, u16 ADC_IT, FunctionalState NewState);
void ADC_ResetCalibration(ADC_TypeDef* ADCx);
FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
void ADC_StartCalibration(ADC_TypeDef* ADCx);
FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, u8 Number);
void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime);
void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
u16 ADC_GetConversionValue(ADC_TypeDef* ADCx);
u32 ADC_GetDualModeConversionValue(void);
void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, u32 ADC_ExternalTrigInjecConv);
void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime);
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, u8 Length);
void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel, u16 Offset);
u16 ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel);
void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, u32 ADC_AnalogWatchdog);
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, u16 HighThreshold, u16 LowThreshold);
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel);
void ADC_TempSensorCmd(FunctionalState NewState);
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, u8 ADC_FLAG);
void ADC_ClearFlag(ADC_TypeDef* ADCx, u8 ADC_FLAG);
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, u16 ADC_IT);
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, u16 ADC_IT);
#endif /*__STM32F10x_ADC_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_adc.h | C | oos | 16,394 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_systick.h
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file contains all the functions prototypes for the
* SysTick firmware library.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_SYSTICK_H
#define __STM32F10x_SYSTICK_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* SysTick clock source */
#define SysTick_CLKSource_HCLK_Div8 ((u32)0xFFFFFFFB)
#define SysTick_CLKSource_HCLK ((u32)0x00000004)
#define IS_SYSTICK_CLK_SOURCE(SOURCE) ((SOURCE == SysTick_CLKSource_HCLK) || \
(SOURCE == SysTick_CLKSource_HCLK_Div8))
/* SysTick counter state */
#define SysTick_Counter_Disable ((u32)0xFFFFFFFE)
#define SysTick_Counter_Enable ((u32)0x00000001)
#define SysTick_Counter_Clear ((u32)0x00000000)
#define IS_SYSTICK_COUNTER(COUNTER) ((COUNTER == SysTick_Counter_Disable) || \
(COUNTER == SysTick_Counter_Enable) || \
(COUNTER == SysTick_Counter_Clear))
/* SysTick Flag */
#define SysTick_FLAG_COUNT ((u8)0x30)
#define SysTick_FLAG_SKEW ((u8)0x5E)
#define SysTick_FLAG_NOREF ((u8)0x5F)
#define IS_SYSTICK_FLAG(FLAG) ((FLAG == SysTick_FLAG_COUNT) || \
(FLAG == SysTick_FLAG_SKEW) || \
(FLAG == SysTick_FLAG_NOREF))
#define IS_SYSTICK_RELOAD(RELOAD) ((RELOAD > 0) || (RELOAD <= 0xFFFFFF))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void SysTick_CLKSourceConfig(u32 SysTick_CLKSource);
void SysTick_SetReload(u32 Reload);
void SysTick_CounterCmd(u32 SysTick_Counter);
void SysTick_ITConfig(FunctionalState NewState);
u32 SysTick_GetCounter(void);
FlagStatus SysTick_GetFlagStatus(u8 SysTick_FLAG);
#endif /* __STM32F10x_SYSTICK_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_systick.h | C | oos | 3,295 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_nvic.h
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file contains all the functions prototypes for the
* NVIC firmware library.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_NVIC_H
#define __STM32F10x_NVIC_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* NVIC Init Structure definition */
typedef struct
{
u8 NVIC_IRQChannel;
u8 NVIC_IRQChannelPreemptionPriority;
u8 NVIC_IRQChannelSubPriority;
FunctionalState NVIC_IRQChannelCmd;
} NVIC_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/* IRQ Channels --------------------------------------------------------------*/
#define WWDG_IRQChannel ((u8)0x00) /* Window WatchDog Interrupt */
#define PVD_IRQChannel ((u8)0x01) /* PVD through EXTI Line detection Interrupt */
#define TAMPER_IRQChannel ((u8)0x02) /* Tamper Interrupt */
#define RTC_IRQChannel ((u8)0x03) /* RTC global Interrupt */
#define FLASH_IRQChannel ((u8)0x04) /* FLASH global Interrupt */
#define RCC_IRQChannel ((u8)0x05) /* RCC global Interrupt */
#define EXTI0_IRQChannel ((u8)0x06) /* EXTI Line0 Interrupt */
#define EXTI1_IRQChannel ((u8)0x07) /* EXTI Line1 Interrupt */
#define EXTI2_IRQChannel ((u8)0x08) /* EXTI Line2 Interrupt */
#define EXTI3_IRQChannel ((u8)0x09) /* EXTI Line3 Interrupt */
#define EXTI4_IRQChannel ((u8)0x0A) /* EXTI Line4 Interrupt */
#define DMAChannel1_IRQChannel ((u8)0x0B) /* DMA Channel 1 global Interrupt */
#define DMAChannel2_IRQChannel ((u8)0x0C) /* DMA Channel 2 global Interrupt */
#define DMAChannel3_IRQChannel ((u8)0x0D) /* DMA Channel 3 global Interrupt */
#define DMAChannel4_IRQChannel ((u8)0x0E) /* DMA Channel 4 global Interrupt */
#define DMAChannel5_IRQChannel ((u8)0x0F) /* DMA Channel 5 global Interrupt */
#define DMAChannel6_IRQChannel ((u8)0x10) /* DMA Channel 6 global Interrupt */
#define DMAChannel7_IRQChannel ((u8)0x11) /* DMA Channel 7 global Interrupt */
#define ADC_IRQChannel ((u8)0x12) /* ADC global Interrupt */
#define USB_HP_CAN_TX_IRQChannel ((u8)0x13) /* USB High Priority or CAN TX Interrupts */
#define USB_LP_CAN_RX0_IRQChannel ((u8)0x14) /* USB Low Priority or CAN RX0 Interrupts */
#define CAN_RX1_IRQChannel ((u8)0x15) /* CAN RX1 Interrupt */
#define CAN_SCE_IRQChannel ((u8)0x16) /* CAN SCE Interrupt */
#define EXTI9_5_IRQChannel ((u8)0x17) /* External Line[9:5] Interrupts */
#define TIM1_BRK_IRQChannel ((u8)0x18) /* TIM1 Break Interrupt */
#define TIM1_UP_IRQChannel ((u8)0x19) /* TIM1 Update Interrupt */
#define TIM1_TRG_COM_IRQChannel ((u8)0x1A) /* TIM1 Trigger and Commutation Interrupt */
#define TIM1_CC_IRQChannel ((u8)0x1B) /* TIM1 Capture Compare Interrupt */
#define TIM2_IRQChannel ((u8)0x1C) /* TIM2 global Interrupt */
#define TIM3_IRQChannel ((u8)0x1D) /* TIM3 global Interrupt */
#define TIM4_IRQChannel ((u8)0x1E) /* TIM4 global Interrupt */
#define I2C1_EV_IRQChannel ((u8)0x1F) /* I2C1 Event Interrupt */
#define I2C1_ER_IRQChannel ((u8)0x20) /* I2C1 Error Interrupt */
#define I2C2_EV_IRQChannel ((u8)0x21) /* I2C2 Event Interrupt */
#define I2C2_ER_IRQChannel ((u8)0x22) /* I2C2 Error Interrupt */
#define SPI1_IRQChannel ((u8)0x23) /* SPI1 global Interrupt */
#define SPI2_IRQChannel ((u8)0x24) /* SPI2 global Interrupt */
#define USART1_IRQChannel ((u8)0x25) /* USART1 global Interrupt */
#define USART2_IRQChannel ((u8)0x26) /* USART2 global Interrupt */
#define USART3_IRQChannel ((u8)0x27) /* USART3 global Interrupt */
#define EXTI15_10_IRQChannel ((u8)0x28) /* External Line[15:10] Interrupts */
#define RTCAlarm_IRQChannel ((u8)0x29) /* RTC Alarm through EXTI Line Interrupt */
#define USBWakeUp_IRQChannel ((u8)0x2A) /* USB WakeUp from suspend through EXTI Line Interrupt */
#define IS_NVIC_IRQ_CHANNEL(CHANNEL) ((CHANNEL == WWDG_IRQChannel) || \
(CHANNEL == PVD_IRQChannel) || \
(CHANNEL == TAMPER_IRQChannel) || \
(CHANNEL == RTC_IRQChannel) || \
(CHANNEL == FLASH_IRQChannel) || \
(CHANNEL == RCC_IRQChannel) || \
(CHANNEL == EXTI0_IRQChannel) || \
(CHANNEL == EXTI1_IRQChannel) || \
(CHANNEL == EXTI2_IRQChannel) || \
(CHANNEL == EXTI3_IRQChannel) || \
(CHANNEL == EXTI4_IRQChannel) || \
(CHANNEL == DMAChannel1_IRQChannel) || \
(CHANNEL == DMAChannel2_IRQChannel) || \
(CHANNEL == DMAChannel3_IRQChannel) || \
(CHANNEL == DMAChannel4_IRQChannel) || \
(CHANNEL == DMAChannel5_IRQChannel) || \
(CHANNEL == DMAChannel6_IRQChannel) || \
(CHANNEL == DMAChannel7_IRQChannel) || \
(CHANNEL == ADC_IRQChannel) || \
(CHANNEL == USB_HP_CAN_TX_IRQChannel) || \
(CHANNEL == USB_LP_CAN_RX0_IRQChannel) || \
(CHANNEL == CAN_RX1_IRQChannel) || \
(CHANNEL == CAN_SCE_IRQChannel) || \
(CHANNEL == EXTI9_5_IRQChannel) || \
(CHANNEL == TIM1_BRK_IRQChannel) || \
(CHANNEL == TIM1_UP_IRQChannel) || \
(CHANNEL == TIM1_TRG_COM_IRQChannel) || \
(CHANNEL == TIM1_CC_IRQChannel) || \
(CHANNEL == TIM2_IRQChannel) || \
(CHANNEL == TIM3_IRQChannel) || \
(CHANNEL == TIM4_IRQChannel) || \
(CHANNEL == I2C1_EV_IRQChannel) || \
(CHANNEL == I2C1_ER_IRQChannel) || \
(CHANNEL == I2C2_EV_IRQChannel) || \
(CHANNEL == I2C2_ER_IRQChannel) || \
(CHANNEL == SPI1_IRQChannel) || \
(CHANNEL == SPI2_IRQChannel) || \
(CHANNEL == USART1_IRQChannel) || \
(CHANNEL == USART2_IRQChannel) || \
(CHANNEL == USART3_IRQChannel) || \
(CHANNEL == EXTI15_10_IRQChannel) || \
(CHANNEL == RTCAlarm_IRQChannel) || \
(CHANNEL == USBWakeUp_IRQChannel))
/* System Handlers -----------------------------------------------------------*/
#define SystemHandler_NMI ((u32)0x00001F) /* NMI Handler */
#define SystemHandler_HardFault ((u32)0x000000) /* Hard Fault Handler */
#define SystemHandler_MemoryManage ((u32)0x043430) /* Memory Manage Handler */
#define SystemHandler_BusFault ((u32)0x547931) /* Bus Fault Handler */
#define SystemHandler_UsageFault ((u32)0x24C232) /* Usage Fault Handler */
#define SystemHandler_SVCall ((u32)0x01FF40) /* SVCall Handler */
#define SystemHandler_DebugMonitor ((u32)0x0A0080) /* Debug Monitor Handler */
#define SystemHandler_PSV ((u32)0x02829C) /* PSV Handler */
#define SystemHandler_SysTick ((u32)0x02C39A) /* SysTick Handler */
#define IS_CONFIG_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \
(HANDLER == SystemHandler_BusFault) || \
(HANDLER == SystemHandler_UsageFault))
#define IS_PRIORITY_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \
(HANDLER == SystemHandler_BusFault) || \
(HANDLER == SystemHandler_UsageFault) || \
(HANDLER == SystemHandler_SVCall) || \
(HANDLER == SystemHandler_DebugMonitor) || \
(HANDLER == SystemHandler_PSV) || \
(HANDLER == SystemHandler_SysTick))
#define IS_GET_PENDING_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \
(HANDLER == SystemHandler_BusFault) || \
(HANDLER == SystemHandler_SVCall))
#define IS_SET_PENDING_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_NMI) || \
(HANDLER == SystemHandler_PSV) || \
(HANDLER == SystemHandler_SysTick))
#define IS_CLEAR_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_PSV) || \
(HANDLER == SystemHandler_SysTick))
#define IS_GET_ACTIVE_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \
(HANDLER == SystemHandler_BusFault) || \
(HANDLER == SystemHandler_UsageFault) || \
(HANDLER == SystemHandler_SVCall) || \
(HANDLER == SystemHandler_DebugMonitor) || \
(HANDLER == SystemHandler_PSV) || \
(HANDLER == SystemHandler_SysTick))
#define IS_FAULT_SOURCE_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_HardFault) || \
(HANDLER == SystemHandler_MemoryManage) || \
(HANDLER == SystemHandler_BusFault) || \
(HANDLER == SystemHandler_UsageFault) || \
(HANDLER == SystemHandler_DebugMonitor))
#define IS_FAULT_ADDRESS_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \
(HANDLER == SystemHandler_BusFault))
/* Vector Table Base ---------------------------------------------------------*/
#define NVIC_VectTab_RAM ((u32)0x20000000)
#define NVIC_VectTab_FLASH ((u32)0x00000000)
#define IS_NVIC_VECTTAB(VECTTAB) ((VECTTAB == NVIC_VectTab_RAM) || \
(VECTTAB == NVIC_VectTab_FLASH))
/* System Low Power ----------------------------------------------------------*/
#define NVIC_LP_SEVONPEND ((u8)0x10)
#define NVIC_LP_SLEEPDEEP ((u8)0x04)
#define NVIC_LP_SLEEPONEXIT ((u8)0x02)
#define IS_NVIC_LP(LP) ((LP == NVIC_LP_SEVONPEND) || \
(LP == NVIC_LP_SLEEPDEEP) || \
(LP == NVIC_LP_SLEEPONEXIT))
/* Preemption Priority Group -------------------------------------------------*/
#define NVIC_PriorityGroup_0 ((u32)0x700) /* 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PriorityGroup_1 ((u32)0x600) /* 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PriorityGroup_2 ((u32)0x500) /* 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PriorityGroup_3 ((u32)0x400) /* 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PriorityGroup_4 ((u32)0x300) /* 4 bits for pre-emption priority
0 bits for subpriority */
#define IS_NVIC_PRIORITY_GROUP(GROUP) ((GROUP == NVIC_PriorityGroup_0) || \
(GROUP == NVIC_PriorityGroup_1) || \
(GROUP == NVIC_PriorityGroup_2) || \
(GROUP == NVIC_PriorityGroup_3) || \
(GROUP == NVIC_PriorityGroup_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) (PRIORITY < 0x10)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) (PRIORITY < 0x10)
#define IS_NVIC_OFFSET(OFFSET) (OFFSET < 0x3FFFFF)
#define IS_NVIC_BASE_PRI(PRI) ((PRI > 0x00) && (PRI < 0x10))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void NVIC_DeInit(void);
void NVIC_SCBDeInit(void);
void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup);
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct);
void NVIC_SETPRIMASK(void);
void NVIC_RESETPRIMASK(void);
void NVIC_SETFAULTMASK(void);
void NVIC_RESETFAULTMASK(void);
void NVIC_BASEPRICONFIG(u32 NewPriority);
u32 NVIC_GetBASEPRI(void);
u16 NVIC_GetCurrentPendingIRQChannel(void);
ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel);
void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel);
void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel);
u16 NVIC_GetCurrentActiveHandler(void);
ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel);
u32 NVIC_GetCPUID(void);
void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset);
void NVIC_GenerateSystemReset(void);
void NVIC_GenerateCoreReset(void);
void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState);
void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState);
void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority,
u8 SystemHandlerSubPriority);
ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler);
void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler);
void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler);
ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler);
u32 NVIC_GetFaultHandlerSources(u32 SystemHandler);
u32 NVIC_GetFaultAddress(u32 SystemHandler);
#endif /* __STM32F10x_NVIC_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_nvic.h | C | oos | 16,376 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_can.h
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file contains all the functions prototypes for the
* CAN firmware library.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_CAN_H
#define __STM32F10x_CAN_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* CAN init structure definition */
typedef struct
{
FunctionalState CAN_TTCM;
FunctionalState CAN_ABOM;
FunctionalState CAN_AWUM;
FunctionalState CAN_NART;
FunctionalState CAN_RFLM;
FunctionalState CAN_TXFP;
u8 CAN_Mode;
u8 CAN_SJW;
u8 CAN_BS1;
u8 CAN_BS2;
u8 CAN_Clock;
u16 CAN_Prescaler;
} CAN_InitTypeDef;
/* CAN filter init structure definition */
typedef struct
{
u8 CAN_FilterNumber;
u8 CAN_FilterMode;
u8 CAN_FilterScale;
u16 CAN_FilterIdHigh;
u16 CAN_FilterIdLow;
u16 CAN_FilterMaskIdHigh;
u16 CAN_FilterMaskIdLow;
u16 CAN_FilterFIFOAssignment;
FunctionalState CAN_FilterActivation;
} CAN_FilterInitTypeDef;
/* CAN Tx message structure definition */
typedef struct
{
u32 StdId;
u32 ExtId;
u8 IDE;
u8 RTR;
u8 DLC;
u8 Data[8];
} CanTxMsg;
/* CAN Rx message structure definition */
typedef struct
{
u32 StdId;
u32 ExtId;
u8 IDE;
u8 RTR;
u8 DLC;
u8 Data[8];
u8 FMI;
} CanRxMsg;
/* Exported constants --------------------------------------------------------*/
/* CAN sleep constants */
#define CANINITFAILED ((u8)0x00) /* CAN initialization failed */
#define CANINITOK ((u8)0x01) /* CAN initialization failed */
/* CAN operating mode */
#define CAN_Mode_Normal ((u8)0x00) /* normal mode */
#define CAN_Mode_LoopBack ((u8)0x01) /* loopback mode */
#define CAN_Mode_Silent ((u8)0x02) /* silent mode */
#define CAN_Mode_Silent_LoopBack ((u8)0x03) /* loopback combined with silent mode */
#define IS_CAN_MODE(MODE) ((MODE == CAN_Mode_Normal) || (MODE == CAN_Mode_LoopBack)|| \
(MODE == CAN_Mode_Silent) || (MODE == CAN_Mode_Silent_LoopBack))
/* CAN synchronisation jump width */
#define CAN_SJW_0tq ((u8)0x00) /* 0 time quantum */
#define CAN_SJW_1tq ((u8)0x01) /* 1 time quantum */
#define CAN_SJW_2tq ((u8)0x02) /* 2 time quantum */
#define CAN_SJW_3tq ((u8)0x03) /* 3 time quantum */
#define IS_CAN_SJW(SJW) ((SJW == CAN_SJW_0tq) || (SJW == CAN_SJW_1tq)|| \
(SJW == CAN_SJW_2tq) || (SJW == CAN_SJW_3tq))
/* time quantum in bit segment 1 */
#define CAN_BS1_1tq ((u8)0x00) /* 1 time quantum */
#define CAN_BS1_2tq ((u8)0x01) /* 2 time quantum */
#define CAN_BS1_3tq ((u8)0x02) /* 3 time quantum */
#define CAN_BS1_4tq ((u8)0x03) /* 4 time quantum */
#define CAN_BS1_5tq ((u8)0x04) /* 5 time quantum */
#define CAN_BS1_6tq ((u8)0x05) /* 6 time quantum */
#define CAN_BS1_7tq ((u8)0x06) /* 7 time quantum */
#define CAN_BS1_8tq ((u8)0x07) /* 8 time quantum */
#define CAN_BS1_9tq ((u8)0x08) /* 9 time quantum */
#define CAN_BS1_10tq ((u8)0x09) /* 10 time quantum */
#define CAN_BS1_11tq ((u8)0x0A) /* 11 time quantum */
#define CAN_BS1_12tq ((u8)0x0B) /* 12 time quantum */
#define CAN_BS1_13tq ((u8)0x0C) /* 13 time quantum */
#define CAN_BS1_14tq ((u8)0x0D) /* 14 time quantum */
#define CAN_BS1_15tq ((u8)0x0E) /* 15 time quantum */
#define CAN_BS1_16tq ((u8)0x0F) /* 16 time quantum */
#define IS_CAN_BS1(BS1) (BS1 <= CAN_BS1_16tq)
/* time quantum in bit segment 2 */
#define CAN_BS2_1tq ((u8)0x00) /* 1 time quantum */
#define CAN_BS2_2tq ((u8)0x01) /* 2 time quantum */
#define CAN_BS2_3tq ((u8)0x02) /* 3 time quantum */
#define CAN_BS2_4tq ((u8)0x03) /* 4 time quantum */
#define CAN_BS2_5tq ((u8)0x04) /* 5 time quantum */
#define CAN_BS2_6tq ((u8)0x05) /* 6 time quantum */
#define CAN_BS2_7tq ((u8)0x06) /* 7 time quantum */
#define CAN_BS2_8tq ((u8)0x07) /* 8 time quantum */
#define IS_CAN_BS2(BS2) (BS2 <= CAN_BS2_8tq)
/* CAN clock selected */
#define CAN_Clock_8MHz ((u8)0x00) /* 8MHz XTAL clock selected */
#define CAN_Clock_APB ((u8)0x01) /* APB clock selected */
#define IS_CAN_CLOCK(CLOCK) ((CLOCK == CAN_Clock_8MHz) || (CLOCK == CAN_Clock_APB))
/* CAN clock prescaler */
#define IS_CAN_PRESCALER(PRESCALER) ((PRESCALER >= 1) && (PRESCALER <= 1024))
/* CAN filter number */
#define IS_CAN_FILTER_NUMBER(NUMBER) (NUMBER <= 13)
/* CAN filter mode */
#define CAN_FilterMode_IdMask ((u8)0x00) /* id/mask mode */
#define CAN_FilterMode_IdList ((u8)0x01) /* identifier list mode */
#define IS_CAN_FILTER_MODE(MODE) ((MODE == CAN_FilterMode_IdMask) || \
(MODE == CAN_FilterMode_IdList))
/* CAN filter scale */
#define CAN_FilterScale_16bit ((u8)0x00) /* 16-bit filter scale */
#define CAN_FilterScale_32bit ((u8)0x01) /* 2-bit filter scale */
#define IS_CAN_FILTER_SCALE(SCALE) ((SCALE == CAN_FilterScale_16bit) || \
(SCALE == CAN_FilterScale_32bit))
/* CAN filter FIFO assignation */
#define CAN_FilterFIFO0 ((u8)0x00) /* Filter FIFO 0 assignment for filter x */
#define CAN_FilterFIFO1 ((u8)0x01) /* Filter FIFO 1 assignment for filter x */
#define IS_CAN_FILTER_FIFO(FIFO) ((FIFO == CAN_FilterFIFO0) || \
(FIFO == CAN_FilterFIFO1))
/* CAN Tx */
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) (TRANSMITMAILBOX <= ((u8)0x02))
#define IS_CAN_STDID(STDID) (STDID <= ((u32)0x7FF))
#define IS_CAN_EXTID(EXTID) (EXTID <= ((u32)0x3FFFF))
#define IS_CAN_DLC(DLC) (DLC <= ((u8)0x08))
/* CAN identifier type */
#define CAN_ID_STD ((u32)0x00000000) /* Standard Id */
#define CAN_ID_EXT ((u32)0x00000004) /* Extended Id */
#define IS_CAN_IDTYPE(IDTYPE) ((IDTYPE == CAN_ID_STD) || (IDTYPE == CAN_ID_EXT))
/* CAN remote transmission request */
#define CAN_RTR_DATA ((u32)0x00000000) /* Data frame */
#define CAN_RTR_REMOTE ((u32)0x00000002) /* Remote frame */
#define IS_CAN_RTR(RTR) ((RTR == CAN_RTR_DATA) || (RTR == CAN_RTR_REMOTE))
/* CAN transmit constants */
#define CANTXFAILED ((u8)0x00) /* CAN transmission failed */
#define CANTXOK ((u8)0x01) /* CAN transmission succeeded */
#define CANTXPENDING ((u8)0x02) /* CAN transmission pending */
#define CAN_NO_MB ((u8)0x04) /* CAN cell did not provide an empty mailbox */
/* CAN receive FIFO number constants */
#define CAN_FIFO0 ((u8)0x00) /* CAN FIFO0 used to receive */
#define CAN_FIFO1 ((u8)0x01) /* CAN FIFO1 used to receive */
#define IS_CAN_FIFO(FIFO) ((FIFO == CAN_FIFO0) || (FIFO == CAN_FIFO1))
/* CAN sleep constants */
#define CANSLEEPFAILED ((u8)0x00) /* CAN did not enter the sleep mode */
#define CANSLEEPOK ((u8)0x01) /* CAN entered the sleep mode */
/* CAN wake up constants */
#define CANWAKEUPFAILED ((u8)0x00) /* CAN did not leave the sleep mode */
#define CANWAKEUPOK ((u8)0x01) /* CAN leaved the sleep mode */
/* CAN flags */
#define CAN_FLAG_EWG ((u32)0x00000001) /* Error Warning Flag */
#define CAN_FLAG_EPV ((u32)0x00000002) /* Error Passive Flag */
#define CAN_FLAG_BOF ((u32)0x00000004) /* Bus-Off Flag */
#define IS_CAN_FLAG(FLAG) ((FLAG == CAN_FLAG_EWG) || (FLAG == CAN_FLAG_EPV) ||\
(FLAG == CAN_FLAG_BOF))
/* CAN interrupts */
#define CAN_IT_RQCP0 ((u8)0x05) /* Request completed mailbox 0 */
#define CAN_IT_RQCP1 ((u8)0x06) /* Request completed mailbox 1 */
#define CAN_IT_RQCP2 ((u8)0x07) /* Request completed mailbox 2 */
#define CAN_IT_TME ((u32)0x00000001) /* Transmit mailbox empty */
#define CAN_IT_FMP0 ((u32)0x00000002) /* FIFO 0 message pending */
#define CAN_IT_FF0 ((u32)0x00000004) /* FIFO 0 full */
#define CAN_IT_FOV0 ((u32)0x00000008) /* FIFO 0 overrun */
#define CAN_IT_FMP1 ((u32)0x00000010) /* FIFO 1 message pending */
#define CAN_IT_FF1 ((u32)0x00000020) /* FIFO 1 full */
#define CAN_IT_FOV1 ((u32)0x00000040) /* FIFO 1 overrun */
#define CAN_IT_EWG ((u32)0x00000100) /* Error warning */
#define CAN_IT_EPV ((u32)0x00000200) /* Error passive */
#define CAN_IT_BOF ((u32)0x00000400) /* Bus-off */
#define CAN_IT_LEC ((u32)0x00000800) /* Last error code */
#define CAN_IT_ERR ((u32)0x00008000) /* Error */
#define CAN_IT_WKU ((u32)0x00010000) /* Wake-up */
#define CAN_IT_SLK ((u32)0x00020000) /* Sleep */
#define IS_CAN_IT(IT) ((IT == CAN_IT_RQCP0) || (IT == CAN_IT_RQCP1) ||\
(IT == CAN_IT_RQCP2) || (IT == CAN_IT_TME) ||\
(IT == CAN_IT_FMP0) || (IT == CAN_IT_FF0) ||\
(IT == CAN_IT_FOV0) || (IT == CAN_IT_FMP1) ||\
(IT == CAN_IT_FF1) || (IT == CAN_IT_FOV1) ||\
(IT == CAN_IT_EWG) || (IT == CAN_IT_EPV) ||\
(IT == CAN_IT_BOF) || (IT == CAN_IT_LEC) ||\
(IT == CAN_IT_ERR) || (IT == CAN_IT_WKU) ||\
(IT == CAN_IT_SLK))
/* Exported macro ------------------------------------------------------------*/
/* Exported function protypes ----------------------------------------------- */
void CAN_DeInit(void);
u8 CAN_Init(CAN_InitTypeDef* CAN_InitStruct);
void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
void CAN_ITConfig(u32 CAN_IT, FunctionalState NewState);
u8 CAN_Transmit(CanTxMsg* TxMessage);
u32 CAN_TransmitStatus(u8 TransmitMailbox);
void CAN_CancelTransmit(u8 Mailbox);
void CAN_FIFORelease(u8 FIFONumber);
u8 CAN_MessagePending(u8 FIFONumber);
void CAN_Receive(u8 FIFONumber, CanRxMsg* RxMessage);
u8 CAN_Sleep(void);
u8 CAN_WakeUp(void);
FlagStatus CAN_GetFlagStatus(u32 CAN_FLAG);
void CAN_ClearFlag(u32 CAN_FLAG);
ITStatus CAN_GetITStatus(u32 CAN_IT);
void CAN_ClearITPendingBit(u32 CAN_IT);
#endif /* __STM32F10x_CAN_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_can.h | C | oos | 12,163 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_tim.h
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file contains all the functions prototypes for the
* TIM firmware library.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_TIM_H
#define __STM32F10x_TIM_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* TIM Base Init structure definition */
typedef struct
{
u16 TIM_Period; /* Period value */
u16 TIM_Prescaler; /* Prescaler value */
u16 TIM_ClockDivision; /* Timer clock division */
u16 TIM_CounterMode; /* Timer Counter mode */
} TIM_TimeBaseInitTypeDef;
/* TIM Output Compare Init structure definition */
typedef struct
{
u16 TIM_OCMode; /* Timer Output Compare Mode */
u16 TIM_Channel; /* Timer Channel */
u16 TIM_Pulse; /* PWM or OC Channel pulse length */
u16 TIM_OCPolarity; /* PWM, OCM or OPM Channel polarity */
} TIM_OCInitTypeDef;
/* TIM Input Capture Init structure definition */
typedef struct
{
u16 TIM_ICMode; /* Timer Input Capture Mode */
u16 TIM_Channel; /* Timer Channel */
u16 TIM_ICPolarity; /* Input Capture polarity */
u16 TIM_ICSelection; /* Input Capture selection */
u16 TIM_ICPrescaler; /* Input Capture prescaler */
u8 TIM_ICFilter; /* Input Capture filter */
} TIM_ICInitTypeDef;
/* Exported constants -------------------------------------------------------*/
/* TIM Ouput Compare modes --------------------------------------------------*/
#define TIM_OCMode_Timing ((u16)0x0000)
#define TIM_OCMode_Active ((u16)0x0010)
#define TIM_OCMode_Inactive ((u16)0x0020)
#define TIM_OCMode_Toggle ((u16)0x0030)
#define TIM_OCMode_PWM1 ((u16)0x0060)
#define TIM_OCMode_PWM2 ((u16)0x0070)
#define IS_TIM_OC_MODE(MODE) ((MODE == TIM_OCMode_Timing) || \
(MODE == TIM_OCMode_Active) || \
(MODE == TIM_OCMode_Inactive) || \
(MODE == TIM_OCMode_Toggle)|| \
(MODE == TIM_OCMode_PWM1) || \
(MODE == TIM_OCMode_PWM2))
/* TIM Input Capture modes --------------------------------------------------*/
#define TIM_ICMode_ICAP ((u16)0x0007)
#define TIM_ICMode_PWMI ((u16)0x0006)
#define IS_TIM_IC_MODE(MODE) ((MODE == TIM_ICMode_ICAP) || \
(MODE == TIM_ICMode_PWMI))
/* TIM One Pulse Mode -------------------------------------------------------*/
#define TIM_OPMode_Single ((u16)0x0008)
#define TIM_OPMode_Repetitive ((u16)0x0000)
#define IS_TIM_OPM_MODE(MODE) ((MODE == TIM_OPMode_Single) || \
(MODE == TIM_OPMode_Repetitive))
/* TIM Channel --------------------------------------------------------------*/
#define TIM_Channel_1 ((u16)0x0000)
#define TIM_Channel_2 ((u16)0x0001)
#define TIM_Channel_3 ((u16)0x0002)
#define TIM_Channel_4 ((u16)0x0003)
#define IS_TIM_CHANNEL(CHANNEL) ((CHANNEL == TIM_Channel_1) || \
(CHANNEL == TIM_Channel_2) || \
(CHANNEL == TIM_Channel_3) || \
(CHANNEL == TIM_Channel_4))
/* TIM Clock Division CKD ---------------------------------------------------*/
#define TIM_CKD_DIV1 ((u16)0x0000)
#define TIM_CKD_DIV2 ((u16)0x0100)
#define TIM_CKD_DIV4 ((u16)0x0200)
#define IS_TIM_CKD_DIV(DIV) ((DIV == TIM_CKD_DIV1) || \
(DIV == TIM_CKD_DIV2) || \
(DIV == TIM_CKD_DIV4))
/* TIM Counter Mode ---------------------------------------------------------*/
#define TIM_CounterMode_Up ((u16)0x0000)
#define TIM_CounterMode_Down ((u16)0x0010)
#define TIM_CounterMode_CenterAligned1 ((u16)0x0020)
#define TIM_CounterMode_CenterAligned2 ((u16)0x0040)
#define TIM_CounterMode_CenterAligned3 ((u16)0x0060)
#define IS_TIM_COUNTER_MODE(MODE) ((MODE == TIM_CounterMode_Up) || \
(MODE == TIM_CounterMode_Down) || \
(MODE == TIM_CounterMode_CenterAligned1) || \
(MODE == TIM_CounterMode_CenterAligned2) || \
(MODE == TIM_CounterMode_CenterAligned3))
/* TIM Output Compare Polarity ----------------------------------------------*/
#define TIM_OCPolarity_High ((u16)0x0000)
#define TIM_OCPolarity_Low ((u16)0x0002)
#define IS_TIM_OC_POLARITY(POLARITY) ((POLARITY == TIM_OCPolarity_High) || \
(POLARITY == TIM_OCPolarity_Low))
/* TIM Input Capture Polarity -----------------------------------------------*/
#define TIM_ICPolarity_Rising ((u16)0x0000)
#define TIM_ICPolarity_Falling ((u16)0x0002)
#define IS_TIM_IC_POLARITY(POLARITY) ((POLARITY == TIM_ICPolarity_Rising) || \
(POLARITY == TIM_ICPolarity_Falling))
/* TIM Input Capture Channel Selection -------------------------------------*/
#define TIM_ICSelection_DirectTI ((u16)0x0001)
#define TIM_ICSelection_IndirectTI ((u16)0x0002)
#define TIM_ICSelection_TRGI ((u16)0x0003)
#define IS_TIM_IC_SELECTION(SELECTION) ((SELECTION == TIM_ICSelection_DirectTI) || \
(SELECTION == TIM_ICSelection_IndirectTI) || \
(SELECTION == TIM_ICSelection_TRGI))
/* TIM Input Capture Prescaler ----------------------------------------------*/
#define TIM_ICPSC_DIV1 ((u16)0x0000)
#define TIM_ICPSC_DIV2 ((u16)0x0004)
#define TIM_ICPSC_DIV4 ((u16)0x0008)
#define TIM_ICPSC_DIV8 ((u16)0x000C)
#define IS_TIM_IC_PRESCALER(PRESCALER) ((PRESCALER == TIM_ICPSC_DIV1) || \
(PRESCALER == TIM_ICPSC_DIV2) || \
(PRESCALER == TIM_ICPSC_DIV4) || \
(PRESCALER == TIM_ICPSC_DIV8))
/* TIM Input Capture Filer Value ---------------------------------------------*/
#define IS_TIM_IC_FILTER(ICFILTER) (ICFILTER <= 0xF)
/* TIM interrupt sources ----------------------------------------------------*/
#define TIM_IT_Update ((u16)0x0001)
#define TIM_IT_CC1 ((u16)0x0002)
#define TIM_IT_CC2 ((u16)0x0004)
#define TIM_IT_CC3 ((u16)0x0008)
#define TIM_IT_CC4 ((u16)0x0010)
#define TIM_IT_Trigger ((u16)0x0040)
#define IS_TIM_IT(IT) (((IT & (u16)0xFFA0) == 0x0000) && (IT != 0x0000))
#define IS_TIM_GET_IT(IT) ((IT == TIM_IT_Update) || \
(IT == TIM_IT_CC1) || \
(IT == TIM_IT_CC2) || \
(IT == TIM_IT_CC3) || \
(IT == TIM_IT_CC4) || \
(IT == TIM_IT_Trigger))
/* TIM DMA Base address -----------------------------------------------------*/
#define TIM_DMABase_CR1 ((u16)0x0000)
#define TIM_DMABase_CR2 ((u16)0x0001)
#define TIM_DMABase_SMCR ((u16)0x0002)
#define TIM_DMABase_DIER ((u16)0x0003)
#define TIM_DMABase_SR ((u16)0x0004)
#define TIM_DMABase_EGR ((u16)0x0005)
#define TIM_DMABase_CCMR1 ((u16)0x0006)
#define TIM_DMABase_CCMR2 ((u16)0x0007)
#define TIM_DMABase_CCER ((u16)0x0008)
#define TIM_DMABase_CNT ((u16)0x0009)
#define TIM_DMABase_PSC ((u16)0x000A)
#define TIM_DMABase_ARR ((u16)0x000B)
#define TIM_DMABase_CCR1 ((u16)0x000D)
#define TIM_DMABase_CCR2 ((u16)0x000E)
#define TIM_DMABase_CCR3 ((u16)0x000F)
#define TIM_DMABase_CCR4 ((u16)0x0010)
#define TIM_DMABase_DCR ((u16)0x0012)
#define IS_TIM_DMA_BASE(BASE) ((BASE == TIM_DMABase_CR1) || \
(BASE == TIM_DMABase_CR2) || \
(BASE == TIM_DMABase_SMCR) || \
(BASE == TIM_DMABase_DIER) || \
(BASE == TIM_DMABase_SR) || \
(BASE == TIM_DMABase_EGR) || \
(BASE == TIM_DMABase_CCMR1) || \
(BASE == TIM_DMABase_CCMR2) || \
(BASE == TIM_DMABase_CCER) || \
(BASE == TIM_DMABase_CNT) || \
(BASE == TIM_DMABase_PSC) || \
(BASE == TIM_DMABase_ARR) || \
(BASE == TIM_DMABase_CCR1) || \
(BASE == TIM_DMABase_CCR2) || \
(BASE == TIM_DMABase_CCR3) || \
(BASE == TIM_DMABase_CCR4) || \
(BASE == TIM_DMABase_DCR))
/* TIM DMA Burst Length -----------------------------------------------------*/
#define TIM_DMABurstLength_1Byte ((u16)0x0000)
#define TIM_DMABurstLength_2Bytes ((u16)0x0100)
#define TIM_DMABurstLength_3Bytes ((u16)0x0200)
#define TIM_DMABurstLength_4Bytes ((u16)0x0300)
#define TIM_DMABurstLength_5Bytes ((u16)0x0400)
#define TIM_DMABurstLength_6Bytes ((u16)0x0500)
#define TIM_DMABurstLength_7Bytes ((u16)0x0600)
#define TIM_DMABurstLength_8Bytes ((u16)0x0700)
#define TIM_DMABurstLength_9Bytes ((u16)0x0800)
#define TIM_DMABurstLength_10Bytes ((u16)0x0900)
#define TIM_DMABurstLength_11Bytes ((u16)0x0A00)
#define TIM_DMABurstLength_12Bytes ((u16)0x0B00)
#define TIM_DMABurstLength_13Bytes ((u16)0x0C00)
#define TIM_DMABurstLength_14Bytes ((u16)0x0D00)
#define TIM_DMABurstLength_15Bytes ((u16)0x0E00)
#define TIM_DMABurstLength_16Bytes ((u16)0x0F00)
#define TIM_DMABurstLength_17Bytes ((u16)0x1000)
#define TIM_DMABurstLength_18Bytes ((u16)0x1100)
#define IS_TIM_DMA_LENGTH(LENGTH) ((LENGTH == TIM_DMABurstLength_1Byte) || \
(LENGTH == TIM_DMABurstLength_2Bytes) || \
(LENGTH == TIM_DMABurstLength_3Bytes) || \
(LENGTH == TIM_DMABurstLength_4Bytes) || \
(LENGTH == TIM_DMABurstLength_5Bytes) || \
(LENGTH == TIM_DMABurstLength_6Bytes) || \
(LENGTH == TIM_DMABurstLength_7Bytes) || \
(LENGTH == TIM_DMABurstLength_8Bytes) || \
(LENGTH == TIM_DMABurstLength_9Bytes) || \
(LENGTH == TIM_DMABurstLength_10Bytes) || \
(LENGTH == TIM_DMABurstLength_11Bytes) || \
(LENGTH == TIM_DMABurstLength_12Bytes) || \
(LENGTH == TIM_DMABurstLength_13Bytes) || \
(LENGTH == TIM_DMABurstLength_14Bytes) || \
(LENGTH == TIM_DMABurstLength_15Bytes) || \
(LENGTH == TIM_DMABurstLength_16Bytes) || \
(LENGTH == TIM_DMABurstLength_17Bytes) || \
(LENGTH == TIM_DMABurstLength_18Bytes))
/* TIM DMA sources ----------------------------------------------------------*/
#define TIM_DMA_Update ((u16)0x0100)
#define TIM_DMA_CC1 ((u16)0x0200)
#define TIM_DMA_CC2 ((u16)0x0400)
#define TIM_DMA_CC3 ((u16)0x0800)
#define TIM_DMA_CC4 ((u16)0x1000)
#define TIM_DMA_Trigger ((u16)0x4000)
#define IS_TIM_DMA_SOURCE(SOURCE) (((SOURCE & (u16)0xA0FF) == 0x0000) && (SOURCE != 0x0000))
/* TIM External Trigger Prescaler -------------------------------------------*/
#define TIM_ExtTRGPSC_OFF ((u16)0x0000)
#define TIM_ExtTRGPSC_DIV2 ((u16)0x1000)
#define TIM_ExtTRGPSC_DIV4 ((u16)0x2000)
#define TIM_ExtTRGPSC_DIV8 ((u16)0x3000)
#define IS_TIM_EXT_PRESCALER(PRESCALER) ((PRESCALER == TIM_ExtTRGPSC_OFF) || \
(PRESCALER == TIM_ExtTRGPSC_DIV2) || \
(PRESCALER == TIM_ExtTRGPSC_DIV4) || \
(PRESCALER == TIM_ExtTRGPSC_DIV8))
/* TIM Input Trigger Selection ---------------------------------------------*/
#define TIM_TS_ITR0 ((u16)0x0000)
#define TIM_TS_ITR1 ((u16)0x0010)
#define TIM_TS_ITR2 ((u16)0x0020)
#define TIM_TS_ITR3 ((u16)0x0030)
#define TIM_TS_TI1F_ED ((u16)0x0040)
#define TIM_TS_TI1FP1 ((u16)0x0050)
#define TIM_TS_TI2FP2 ((u16)0x0060)
#define TIM_TS_ETRF ((u16)0x0070)
#define IS_TIM_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM_TS_ITR0) || \
(SELECTION == TIM_TS_ITR1) || \
(SELECTION == TIM_TS_ITR2) || \
(SELECTION == TIM_TS_ITR3) || \
(SELECTION == TIM_TS_TI1F_ED) || \
(SELECTION == TIM_TS_TI1FP1) || \
(SELECTION == TIM_TS_TI2FP2) || \
(SELECTION == TIM_TS_ETRF))
#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM_TS_ITR0) || \
(SELECTION == TIM_TS_ITR1) || \
(SELECTION == TIM_TS_ITR2) || \
(SELECTION == TIM_TS_ITR3))
#define IS_TIM_TIX_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM_TS_TI1F_ED) || \
(SELECTION == TIM_TS_TI1FP1) || \
(SELECTION == TIM_TS_TI2FP2))
/* TIM External Trigger Polarity --------------------------------------------*/
#define TIM_ExtTRGPolarity_Inverted ((u16)0x8000)
#define TIM_ExtTRGPolarity_NonInverted ((u16)0x0000)
#define IS_TIM_EXT_POLARITY(POLARITY) ((POLARITY == TIM_ExtTRGPolarity_Inverted) || \
(POLARITY == TIM_ExtTRGPolarity_NonInverted))
/* TIM Prescaler Reload Mode ------------------------------------------------*/
#define TIM_PSCReloadMode_Update ((u16)0x0000)
#define TIM_PSCReloadMode_Immediate ((u16)0x0001)
#define IS_TIM_PRESCALER_RELOAD(RELOAD) ((RELOAD == TIM_PSCReloadMode_Update) || \
(RELOAD == TIM_PSCReloadMode_Immediate))
/* TIM Forced Action --------------------------------------------------------*/
#define TIM_ForcedAction_Active ((u16)0x0050)
#define TIM_ForcedAction_InActive ((u16)0x0040)
#define IS_TIM_FORCED_ACTION(ACTION) ((ACTION == TIM_ForcedAction_Active) || \
(ACTION == TIM_ForcedAction_InActive))
/* TIM Encoder Mode ---------------------------------------------------------*/
#define TIM_EncoderMode_TI1 ((u16)0x0001)
#define TIM_EncoderMode_TI2 ((u16)0x0002)
#define TIM_EncoderMode_TI12 ((u16)0x0003)
#define IS_TIM_ENCODER_MODE(MODE) ((MODE == TIM_EncoderMode_TI1) || \
(MODE == TIM_EncoderMode_TI2) || \
(MODE == TIM_EncoderMode_TI12))
/* TIM Event Source ---------------------------------------------------------*/
#define TIM_EventSource_Update ((u16)0x0001)
#define TIM_EventSource_CC1 ((u16)0x0002)
#define TIM_EventSource_CC2 ((u16)0x0004)
#define TIM_EventSource_CC3 ((u16)0x0008)
#define TIM_EventSource_CC4 ((u16)0x0010)
#define TIM_EventSource_Trigger ((u16)0x0040)
#define IS_TIM_EVENT_SOURCE(SOURCE) (((SOURCE & (u16)0xFFA0) == 0x0000) && (SOURCE != 0x0000))
/* TIM Update Source --------------------------------------------------------*/
#define TIM_UpdateSource_Global ((u16)0x0000)
#define TIM_UpdateSource_Regular ((u16)0x0001)
#define IS_TIM_UPDATE_SOURCE(SOURCE) ((SOURCE == TIM_UpdateSource_Global) || \
(SOURCE == TIM_UpdateSource_Regular))
/* TIM Ouput Compare Preload State ------------------------------------------*/
#define TIM_OCPreload_Enable ((u16)0x0008)
#define TIM_OCPreload_Disable ((u16)0x0000)
#define IS_TIM_OCPRELOAD_STATE(STATE) ((STATE == TIM_OCPreload_Enable) || \
(STATE == TIM_OCPreload_Disable))
/* TIM Ouput Compare Fast State ---------------------------------------------*/
#define TIM_OCFast_Enable ((u16)0x0004)
#define TIM_OCFast_Disable ((u16)0x0000)
#define IS_TIM_OCFAST_STATE(STATE) ((STATE == TIM_OCFast_Enable) || \
(STATE == TIM_OCFast_Disable))
/* TIM Trigger Output Source ------------------------------------------------*/
#define TIM_TRGOSource_Reset ((u16)0x0000)
#define TIM_TRGOSource_Enable ((u16)0x0010)
#define TIM_TRGOSource_Update ((u16)0x0020)
#define TIM_TRGOSource_OC1 ((u16)0x0030)
#define TIM_TRGOSource_OC1Ref ((u16)0x0040)
#define TIM_TRGOSource_OC2Ref ((u16)0x0050)
#define TIM_TRGOSource_OC3Ref ((u16)0x0060)
#define TIM_TRGOSource_OC4Ref ((u16)0x0070)
#define IS_TIM_TRGO_SOURCE(SOURCE) ((SOURCE == TIM_TRGOSource_Reset) || \
(SOURCE == TIM_TRGOSource_Enable) || \
(SOURCE == TIM_TRGOSource_Update) || \
(SOURCE == TIM_TRGOSource_OC1) || \
(SOURCE == TIM_TRGOSource_OC1Ref) || \
(SOURCE == TIM_TRGOSource_OC2Ref) || \
(SOURCE == TIM_TRGOSource_OC3Ref) || \
(SOURCE == TIM_TRGOSource_OC4Ref))
/* TIM Slave Mode -----------------------------------------------------------*/
#define TIM_SlaveMode_Reset ((u16)0x0004)
#define TIM_SlaveMode_Gated ((u16)0x0005)
#define TIM_SlaveMode_Trigger ((u16)0x0006)
#define TIM_SlaveMode_External1 ((u16)0x0007)
#define IS_TIM_SLAVE_MODE(MODE) ((MODE == TIM_SlaveMode_Reset) || \
(MODE == TIM_SlaveMode_Gated) || \
(MODE == TIM_SlaveMode_Trigger) || \
(MODE == TIM_SlaveMode_External1))
/* TIM TIx External Clock Source --------------------------------------------*/
#define TIM_TIxExternalCLK1Source_TI1 ((u16)0x0050)
#define TIM_TIxExternalCLK1Source_TI2 ((u16)0x0060)
#define TIM_TIxExternalCLK1Source_TI1ED ((u16)0x0040)
#define IS_TIM_TIXCLK_SOURCE(SOURCE) ((SOURCE == TIM_TIxExternalCLK1Source_TI1) || \
(SOURCE == TIM_TIxExternalCLK1Source_TI2) || \
(SOURCE == TIM_TIxExternalCLK1Source_TI1ED))
/* TIM Master Slave Mode ----------------------------------------------------*/
#define TIM_MasterSlaveMode_Enable ((u16)0x0080)
#define TIM_MasterSlaveMode_Disable ((u16)0x0000)
#define IS_TIM_MSM_STATE(STATE) ((STATE == TIM_MasterSlaveMode_Enable) || \
(STATE == TIM_MasterSlaveMode_Disable))
/* TIM Flags ----------------------------------------------------------------*/
#define TIM_FLAG_Update ((u16)0x0001)
#define TIM_FLAG_CC1 ((u16)0x0002)
#define TIM_FLAG_CC2 ((u16)0x0004)
#define TIM_FLAG_CC3 ((u16)0x0008)
#define TIM_FLAG_CC4 ((u16)0x0010)
#define TIM_FLAG_Trigger ((u16)0x0040)
#define TIM_FLAG_CC1OF ((u16)0x0200)
#define TIM_FLAG_CC2OF ((u16)0x0400)
#define TIM_FLAG_CC3OF ((u16)0x0800)
#define TIM_FLAG_CC4OF ((u16)0x1000)
#define IS_TIM_GET_FLAG(FLAG) ((FLAG == TIM_FLAG_Update) || \
(FLAG == TIM_FLAG_CC1) || \
(FLAG == TIM_FLAG_CC2) || \
(FLAG == TIM_FLAG_CC3) || \
(FLAG == TIM_FLAG_CC4) || \
(FLAG == TIM_FLAG_Trigger) || \
(FLAG == TIM_FLAG_CC1OF) || \
(FLAG == TIM_FLAG_CC2OF) || \
(FLAG == TIM_FLAG_CC3OF) || \
(FLAG == TIM_FLAG_CC4OF))
#define IS_TIM_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xE1A0) == 0x0000) && (FLAG != 0x0000))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
void TIM_DeInit(TIM_TypeDef* TIMx);
void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
void TIM_OCInit(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_ITConfig(TIM_TypeDef* TIMx, u16 TIM_IT, FunctionalState NewState);
void TIM_DMAConfig(TIM_TypeDef* TIMx, u16 TIM_DMABase, u16 TIM_DMABurstLength);
void TIM_DMACmd(TIM_TypeDef* TIMx, u16 TIM_DMASource, FunctionalState Newstate);
void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource);
void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_TIxExternalCLKSource,
u16 TIM_ICPolarity, u8 ICFilter);
void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity,
u8 ExtTRGFilter);
void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity,
u8 ExtTRGFilter);
void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource);
void TIM_PrescalerConfig(TIM_TypeDef* TIMx, u16 Prescaler, u16 TIM_PSCReloadMode);
void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode);
void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState Newstate);
void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState Newstate);
void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
void TIM_OC1FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
void TIM_OC2FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
void TIM_OC3FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
void TIM_OC4FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState Newstate);
void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, u16 TIM_EncoderMode,
u16 TIM_IC1Polarity, u16 TIM_IC2Polarity);
void TIM_GenerateEvent(TIM_TypeDef* TIMx, u16 TIM_EventSource);
void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);
void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);
void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);
void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);
void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, u16 TIM_UpdateSource);
void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState Newstate);
void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, u16 TIM_OPMode);
void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, u16 TIM_TRGOSource);
void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, u16 TIM_SlaveMode);
void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, u16 TIM_MasterSlaveMode);
void TIM_SetAutoreload(TIM_TypeDef* TIMx, u16 Autoreload);
void TIM_SetCompare1(TIM_TypeDef* TIMx, u16 Compare1);
void TIM_SetCompare2(TIM_TypeDef* TIMx, u16 Compare2);
void TIM_SetCompare3(TIM_TypeDef* TIMx, u16 Compare3);
void TIM_SetCompare4(TIM_TypeDef* TIMx, u16 Compare4);
void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC1Prescaler);
void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC2Prescaler);
void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC3Prescaler);
void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC4Prescaler);
void TIM_SetClockDivision(TIM_TypeDef* TIMx, u16 TIM_CKD);
u16 TIM_GetCapture1(TIM_TypeDef* TIMx);
u16 TIM_GetCapture2(TIM_TypeDef* TIMx);
u16 TIM_GetCapture3(TIM_TypeDef* TIMx);
u16 TIM_GetCapture4(TIM_TypeDef* TIMx);
u16 TIM_GetCounter(TIM_TypeDef* TIMx);
u16 TIM_GetPrescaler(TIM_TypeDef* TIMx);
FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG);
void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG);
ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT);
void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT);
#endif /*__STM32F10x_TIM_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_tim.h | C | oos | 28,319 |
/**
******************************************************************************
* @file stm32f10x_spi.h
* @author MCD Application Team
* @version V3.0.0
* @date 04/06/2009
* @brief This file contains all the functions prototypes for the SPI firmware
* library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_SPI_H
#define __STM32F10x_SPI_H
/* Includes ------------------------------------------------------------------*/
//#include "stm32f10x.h"
#include "stm32f10x_map.h"
#define uint16_t unsigned short
#define uint8_t unsigned char
#define uint32_t unsigned long
#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
#define GPIO_Remap_SPI3 ( 1UL << 28UL )
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @addtogroup SPI
* @{
*/
/** @defgroup SPI_Exported_Types
* @{
*/
/**
* @brief SPI Init structure definition
*/
typedef struct
{
uint16_t SPI_Direction;
uint16_t SPI_Mode;
uint16_t SPI_DataSize;
uint16_t SPI_CPOL;
uint16_t SPI_CPHA;
uint16_t SPI_NSS;
uint16_t SPI_BaudRatePrescaler;
uint16_t SPI_FirstBit;
uint16_t SPI_CRCPolynomial;
}SPI_InitTypeDef;
/**
* @brief I2S Init structure definition
*/
typedef struct
{
uint16_t I2S_Mode;
uint16_t I2S_Standard;
uint16_t I2S_DataFormat;
uint16_t I2S_MCLKOutput;
uint16_t I2S_AudioFreq;
uint16_t I2S_CPOL;
}I2S_InitTypeDef;
/**
* @}
*/
/** @defgroup SPI_Exported_Constants
* @{
*/
#define IS_SPI_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == SPI1_BASE) || \
((*(uint32_t*)&(PERIPH)) == SPI2_BASE) || \
((*(uint32_t*)&(PERIPH)) == SPI3_BASE))
#define IS_SPI_23_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == SPI2_BASE) || \
((*(uint32_t*)&(PERIPH)) == SPI3_BASE))
/** @defgroup SPI_data_direction_mode
* @{
*/
#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
((MODE) == SPI_Direction_2Lines_RxOnly) || \
((MODE) == SPI_Direction_1Line_Rx) || \
((MODE) == SPI_Direction_1Line_Tx))
/**
* @}
*/
/** @defgroup SPI_master_slave_mode
* @{
*/
#define SPI_Mode_Master ((uint16_t)0x0104)
#define SPI_Mode_Slave ((uint16_t)0x0000)
#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
((MODE) == SPI_Mode_Slave))
/**
* @}
*/
/** @defgroup SPI_data_size
* @{
*/
#define SPI_DataSize_16b ((uint16_t)0x0800)
#define SPI_DataSize_8b ((uint16_t)0x0000)
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
((DATASIZE) == SPI_DataSize_8b))
/**
* @}
*/
/** @defgroup SPI_Clock_Polarity
* @{
*/
#define SPI_CPOL_Low ((uint16_t)0x0000)
#define SPI_CPOL_High ((uint16_t)0x0002)
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
((CPOL) == SPI_CPOL_High))
/**
* @}
*/
/** @defgroup SPI_Clock_Phase
* @{
*/
#define SPI_CPHA_1Edge ((uint16_t)0x0000)
#define SPI_CPHA_2Edge ((uint16_t)0x0001)
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
((CPHA) == SPI_CPHA_2Edge))
/**
* @}
*/
/** @defgroup SPI_Slave_Select_management
* @{
*/
#define SPI_NSS_Soft ((uint16_t)0x0200)
#define SPI_NSS_Hard ((uint16_t)0x0000)
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
((NSS) == SPI_NSS_Hard))
/**
* @}
*/
/** @defgroup SPI_BaudRate_Prescaler_
* @{
*/
#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
((PRESCALER) == SPI_BaudRatePrescaler_4) || \
((PRESCALER) == SPI_BaudRatePrescaler_8) || \
((PRESCALER) == SPI_BaudRatePrescaler_16) || \
((PRESCALER) == SPI_BaudRatePrescaler_32) || \
((PRESCALER) == SPI_BaudRatePrescaler_64) || \
((PRESCALER) == SPI_BaudRatePrescaler_128) || \
((PRESCALER) == SPI_BaudRatePrescaler_256))
/**
* @}
*/
/** @defgroup SPI_MSB_LSB_transmission
* @{
*/
#define SPI_FirstBit_MSB ((uint16_t)0x0000)
#define SPI_FirstBit_LSB ((uint16_t)0x0080)
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
((BIT) == SPI_FirstBit_LSB))
/**
* @}
*/
/** @defgroup I2S_Mode
* @{
*/
#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
#define I2S_Mode_MasterTx ((uint16_t)0x0200)
#define I2S_Mode_MasterRx ((uint16_t)0x0300)
#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
((MODE) == I2S_Mode_SlaveRx) || \
((MODE) == I2S_Mode_MasterTx) || \
((MODE) == I2S_Mode_MasterRx) )
/**
* @}
*/
/** @defgroup I2S_Standard
* @{
*/
#define I2S_Standard_Phillips ((uint16_t)0x0000)
#define I2S_Standard_MSB ((uint16_t)0x0010)
#define I2S_Standard_LSB ((uint16_t)0x0020)
#define I2S_Standard_PCMShort ((uint16_t)0x0030)
#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
((STANDARD) == I2S_Standard_MSB) || \
((STANDARD) == I2S_Standard_LSB) || \
((STANDARD) == I2S_Standard_PCMShort) || \
((STANDARD) == I2S_Standard_PCMLong))
/**
* @}
*/
/** @defgroup I2S_Data_Format
* @{
*/
#define I2S_DataFormat_16b ((uint16_t)0x0000)
#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
#define I2S_DataFormat_24b ((uint16_t)0x0003)
#define I2S_DataFormat_32b ((uint16_t)0x0005)
#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
((FORMAT) == I2S_DataFormat_16bextended) || \
((FORMAT) == I2S_DataFormat_24b) || \
((FORMAT) == I2S_DataFormat_32b))
/**
* @}
*/
/** @defgroup I2S_MCLK_Output
* @{
*/
#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
((OUTPUT) == I2S_MCLKOutput_Disable))
/**
* @}
*/
/** @defgroup I2S_Audio_Frequency
* @{
*/
#define I2S_AudioFreq_48k ((uint16_t)48000)
#define I2S_AudioFreq_44k ((uint16_t)44100)
#define I2S_AudioFreq_22k ((uint16_t)22050)
#define I2S_AudioFreq_16k ((uint16_t)16000)
#define I2S_AudioFreq_8k ((uint16_t)8000)
#define I2S_AudioFreq_Default ((uint16_t)2)
#define IS_I2S_AUDIO_FREQ(FREQ) (((FREQ) == I2S_AudioFreq_48k) || \
((FREQ) == I2S_AudioFreq_44k) || \
((FREQ) == I2S_AudioFreq_22k) || \
((FREQ) == I2S_AudioFreq_16k) || \
((FREQ) == I2S_AudioFreq_8k) || \
((FREQ) == I2S_AudioFreq_Default))
/**
* @}
*/
/** @defgroup I2S_Clock_Polarity
* @{
*/
#define I2S_CPOL_Low ((uint16_t)0x0000)
#define I2S_CPOL_High ((uint16_t)0x0008)
#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
((CPOL) == I2S_CPOL_High))
/**
* @}
*/
/** @defgroup SPI_I2S_DMA_transfer_requests
* @{
*/
#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
/**
* @}
*/
/** @defgroup SPI_NSS_internal_software_mangement
* @{
*/
#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
((INTERNAL) == SPI_NSSInternalSoft_Reset))
/**
* @}
*/
/** @defgroup SPI_CRC_Transmit_Receive
* @{
*/
#define SPI_CRC_Tx ((uint8_t)0x00)
#define SPI_CRC_Rx ((uint8_t)0x01)
#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
/**
* @}
*/
/** @defgroup SPI_direction_transmit_receive
* @{
*/
#define SPI_Direction_Rx ((uint16_t)0xBFFF)
#define SPI_Direction_Tx ((uint16_t)0x4000)
#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
((DIRECTION) == SPI_Direction_Tx))
/**
* @}
*/
/** @defgroup SPI_I2S_interrupts_definition
* @{
*/
#define SPI_I2S_IT_TXE ((uint8_t)0x71)
#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
#define SPI_I2S_IT_ERR ((uint8_t)0x50)
#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
((IT) == SPI_I2S_IT_RXNE) || \
((IT) == SPI_I2S_IT_ERR))
#define SPI_I2S_IT_OVR ((uint8_t)0x56)
#define SPI_IT_MODF ((uint8_t)0x55)
#define SPI_IT_CRCERR ((uint8_t)0x54)
#define I2S_IT_UDR ((uint8_t)0x53)
#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \
((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR))
/**
* @}
*/
/** @defgroup SPI_I2S_flags_definition
* @{
*/
#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
#define I2S_FLAG_UDR ((uint16_t)0x0008)
#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
#define SPI_FLAG_MODF ((uint16_t)0x0020)
#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))
/**
* @}
*/
/** @defgroup SPI_CRC_polynomial
* @{
*/
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
/**
* @}
*/
/**
* @}
*/
/** @defgroup SPI_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup SPI_Exported_Functions
* @{
*/
void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
void SPI_TransmitCRC(SPI_TypeDef* SPIx);
void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
#endif /*__STM32F10x_SPI_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_spi.h | C | oos | 15,174 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_lib.h
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file includes the peripherals header files in the
* user application.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_LIB_H
#define __STM32F10x_LIB_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
#ifdef _ADC
#include "stm32f10x_adc.h"
#endif /*_ADC */
#ifdef _BKP
#include "stm32f10x_bkp.h"
#endif /*_BKP */
#ifdef _CAN
#include "stm32f10x_can.h"
#endif /*_CAN */
#ifdef _DMA
#include "stm32f10x_dma.h"
#endif /*_DMA */
#ifdef _EXTI
#include "stm32f10x_exti.h"
#endif /*_EXTI */
#ifdef _FLASH
#include "stm32f10x_flash.h"
#endif /*_FLASH */
#ifdef _GPIO
#include "stm32f10x_gpio.h"
#endif /*_GPIO */
#ifdef _I2C
#include "stm32f10x_i2c.h"
#endif /*_I2C */
#ifdef _IWDG
#include "stm32f10x_iwdg.h"
#endif /*_IWDG */
#ifdef _NVIC
#include "stm32f10x_nvic.h"
#endif /*_NVIC */
#ifdef _PWR
#include "stm32f10x_pwr.h"
#endif /*_PWR */
#ifdef _RCC
#include "stm32f10x_rcc.h"
#endif /*_RCC */
#ifdef _RTC
#include "stm32f10x_rtc.h"
#endif /*_RTC */
#ifdef _SPI
#include "stm32f10x_spi.h"
#endif /*_SPI */
#ifdef _SysTick
#include "stm32f10x_systick.h"
#endif /*_SysTick */
#ifdef _TIM1
#include "stm32f10x_tim1.h"
#endif /*_TIM1 */
#ifdef _TIM
#include "stm32f10x_tim.h"
#endif /*_TIM */
#ifdef _USART
#include "stm32f10x_usart.h"
#endif /*_USART */
#ifdef _WWDG
#include "stm32f10x_wwdg.h"
#endif /*_WWDG */
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void debug(void);
#endif /* __STM32F10x_LIB_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_lib.h | C | oos | 3,060 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_usart.h
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file contains all the functions prototypes for the
* USART firmware library.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_USART_H
#define __STM32F10x_USART_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* UART Init Structure definition */
typedef struct
{
u32 USART_BaudRate;
u16 USART_WordLength;
u16 USART_StopBits;
u16 USART_Parity;
u16 USART_HardwareFlowControl;
u16 USART_Mode;
u16 USART_Clock;
u16 USART_CPOL;
u16 USART_CPHA;
u16 USART_LastBit;
} USART_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/* USART Word Length ---------------------------------------------------------*/
#define USART_WordLength_8b ((u16)0x0000)
#define USART_WordLength_9b ((u16)0x1000)
#define IS_USART_WORD_LENGTH(LENGTH) ((LENGTH == USART_WordLength_8b) || \
(LENGTH == USART_WordLength_9b))
/* USART Stop Bits -----------------------------------------------------------*/
#define USART_StopBits_1 ((u16)0x0000)
#define USART_StopBits_0_5 ((u16)0x1000)
#define USART_StopBits_2 ((u16)0x2000)
#define USART_StopBits_1_5 ((u16)0x3000)
#define IS_USART_STOPBITS(STOPBITS) ((STOPBITS == USART_StopBits_1) || \
(STOPBITS == USART_StopBits_0_5) || \
(STOPBITS == USART_StopBits_2) || \
(STOPBITS == USART_StopBits_1_5))
/* USART Parity --------------------------------------------------------------*/
#define USART_Parity_No ((u16)0x0000)
#define USART_Parity_Even ((u16)0x0400)
#define USART_Parity_Odd ((u16)0x0600)
#define IS_USART_PARITY(PARITY) ((PARITY == USART_Parity_No) || \
(PARITY == USART_Parity_Even) || \
(PARITY == USART_Parity_Odd))
/* USART Hardware Flow Control -----------------------------------------------*/
#define USART_HardwareFlowControl_None ((u16)0x0000)
#define USART_HardwareFlowControl_RTS ((u16)0x0100)
#define USART_HardwareFlowControl_CTS ((u16)0x0200)
#define USART_HardwareFlowControl_RTS_CTS ((u16)0x0300)
#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
((CONTROL == USART_HardwareFlowControl_None) || \
(CONTROL == USART_HardwareFlowControl_RTS) || \
(CONTROL == USART_HardwareFlowControl_CTS) || \
(CONTROL == USART_HardwareFlowControl_RTS_CTS))
/* USART Mode ----------------------------------------------------------------*/
#define USART_Mode_Rx ((u16)0x0004)
#define USART_Mode_Tx ((u16)0x0008)
#define IS_USART_MODE(MODE) (((MODE & (u16)0xFFF3) == 0x00) && (MODE != (u16)0x00))
/* USART Clock ---------------------------------------------------------------*/
#define USART_Clock_Disable ((u16)0x0000)
#define USART_Clock_Enable ((u16)0x0800)
#define IS_USART_CLOCK(CLOCK) ((CLOCK == USART_Clock_Disable) || \
(CLOCK == USART_Clock_Enable))
/* USART Clock Polarity ------------------------------------------------------*/
#define USART_CPOL_Low ((u16)0x0000)
#define USART_CPOL_High ((u16)0x0400)
#define IS_USART_CPOL(CPOL) ((CPOL == USART_CPOL_Low) || (CPOL == USART_CPOL_High))
/* USART Clock Phase ---------------------------------------------------------*/
#define USART_CPHA_1Edge ((u16)0x0000)
#define USART_CPHA_2Edge ((u16)0x0200)
#define IS_USART_CPHA(CPHA) ((CPHA == USART_CPHA_1Edge) || (CPHA == USART_CPHA_2Edge))
/* USART Last Bit ------------------------------------------------------------*/
#define USART_LastBit_Disable ((u16)0x0000)
#define USART_LastBit_Enable ((u16)0x0100)
#define IS_USART_LASTBIT(LASTBIT) ((LASTBIT == USART_LastBit_Disable) || \
(LASTBIT == USART_LastBit_Enable))
/* USART Interrupt definition ------------------------------------------------*/
#define USART_IT_PE ((u16)0x0028)
#define USART_IT_TXE ((u16)0x0727)
#define USART_IT_TC ((u16)0x0626)
#define USART_IT_RXNE ((u16)0x0525)
#define USART_IT_IDLE ((u16)0x0424)
#define USART_IT_LBD ((u16)0x0846)
#define USART_IT_CTS ((u16)0x096A)
#define USART_IT_ERR ((u16)0x0060)
#define USART_IT_ORE ((u16)0x0360)
#define USART_IT_NE ((u16)0x0260)
#define USART_IT_FE ((u16)0x0160)
#define IS_USART_CONFIG_IT(IT) ((IT == USART_IT_PE) || (IT == USART_IT_TXE) || \
(IT == USART_IT_TC) || (IT == USART_IT_RXNE) || \
(IT == USART_IT_IDLE) || (IT == USART_IT_LBD) || \
(IT == USART_IT_CTS) || (IT == USART_IT_ERR))
#define IS_USART_IT(IT) ((IT == USART_IT_PE) || (IT == USART_IT_TXE) || \
(IT == USART_IT_TC) || (IT == USART_IT_RXNE) || \
(IT == USART_IT_IDLE) || (IT == USART_IT_LBD) || \
(IT == USART_IT_CTS) || (IT == USART_IT_ORE) || \
(IT == USART_IT_NE) || (IT == USART_IT_FE))
/* USART DMA Requests --------------------------------------------------------*/
#define USART_DMAReq_Tx ((u16)0x0080)
#define USART_DMAReq_Rx ((u16)0x0040)
#define IS_USART_DMAREQ(DMAREQ) (((DMAREQ & (u16)0xFF3F) == 0x00) && (DMAREQ != (u16)0x00))
/* USART WakeUp methods ------------------------------------------------------*/
#define USART_WakeUp_IdleLine ((u16)0x0000)
#define USART_WakeUp_AddressMark ((u16)0x0800)
#define IS_USART_WAKEUP(WAKEUP) ((WAKEUP == USART_WakeUp_IdleLine) || \
(WAKEUP == USART_WakeUp_AddressMark))
/* USART LIN Break Detection Length ------------------------------------------*/
#define USART_LINBreakDetectLength_10b ((u16)0x0000)
#define USART_LINBreakDetectLength_11b ((u16)0x0020)
#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
((LENGTH == USART_LINBreakDetectLength_10b) || \
(LENGTH == USART_LINBreakDetectLength_11b))
/* USART IrDA Low Power ------------------------------------------------------*/
#define USART_IrDAMode_LowPower ((u16)0x0004)
#define USART_IrDAMode_Normal ((u16)0x0000)
#define IS_USART_IRDA_MODE(MODE) ((MODE == USART_IrDAMode_LowPower) || \
(MODE == USART_IrDAMode_Normal))
/* USART Flags ---------------------------------------------------------------*/
#define USART_FLAG_CTS ((u16)0x0200)
#define USART_FLAG_LBD ((u16)0x0100)
#define USART_FLAG_TXE ((u16)0x0080)
#define USART_FLAG_TC ((u16)0x0040)
#define USART_FLAG_RXNE ((u16)0x0020)
#define USART_FLAG_IDLE ((u16)0x0010)
#define USART_FLAG_ORE ((u16)0x0008)
#define USART_FLAG_NE ((u16)0x0004)
#define USART_FLAG_FE ((u16)0x0002)
#define USART_FLAG_PE ((u16)0x0001)
#define IS_USART_FLAG(FLAG) ((FLAG == USART_FLAG_PE) || (FLAG == USART_FLAG_TXE) || \
(FLAG == USART_FLAG_TC) || (FLAG == USART_FLAG_RXNE) || \
(FLAG == USART_FLAG_IDLE) || (FLAG == USART_FLAG_LBD) || \
(FLAG == USART_FLAG_CTS) || (FLAG == USART_FLAG_ORE) || \
(FLAG == USART_FLAG_NE) || (FLAG == USART_FLAG_FE))
#define IS_USART_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xFC00) == 0x00) && (FLAG != (u16)0x00))
#define IS_USART_ADDRESS(ADDRESS) (ADDRESS <= 0xF)
#define IS_USART_DATA(DATA) (DATA <= 0x1FF)
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void USART_DeInit(USART_TypeDef* USARTx);
void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_ITConfig(USART_TypeDef* USARTx, u16 USART_IT, FunctionalState NewState);
void USART_DMACmd(USART_TypeDef* USARTx, u16 USART_DMAReq, FunctionalState NewState);
void USART_SetAddress(USART_TypeDef* USARTx, u8 USART_Address);
void USART_WakeUpConfig(USART_TypeDef* USARTx, u16 USART_WakeUp);
void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, u16 USART_LINBreakDetectLength);
void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_SendData(USART_TypeDef* USARTx, u16 Data);
u16 USART_ReceiveData(USART_TypeDef* USARTx);
void USART_SendBreak(USART_TypeDef* USARTx);
void USART_SetGuardTime(USART_TypeDef* USARTx, u8 USART_GuardTime);
void USART_SetPrescaler(USART_TypeDef* USARTx, u8 USART_Prescaler);
void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_IrDAConfig(USART_TypeDef* USARTx, u16 USART_IrDAMode);
void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, u16 USART_FLAG);
void USART_ClearFlag(USART_TypeDef* USARTx, u16 USART_FLAG);
ITStatus USART_GetITStatus(USART_TypeDef* USARTx, u16 USART_IT);
void USART_ClearITPendingBit(USART_TypeDef* USARTx, u16 USART_IT);
#endif /* __STM32F10x_USART_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_usart.h | C | oos | 11,745 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_tim1.h
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file contains all the functions prototypes for the
* TIM1 firmware library.
********************************************************************************
* History:
* 04/02/2007: V0.2
* mm/dd/yyyy: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_TIM1_H
#define __STM32F10x_TIM1_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* TIM1 Time Base Init structure definition */
typedef struct
{
u16 TIM1_Prescaler;
u16 TIM1_CounterMode;
u16 TIM1_Period;
u16 TIM1_ClockDivision;
u8 TIM1_RepetitionCounter;
} TIM1_TimeBaseInitTypeDef;
/* TIM1 Output Compare Init structure definition */
typedef struct
{
u16 TIM1_OCMode;
u16 TIM1_OutputState;
u16 TIM1_OutputNState;
u16 TIM1_Pulse;
u16 TIM1_OCPolarity;
u16 TIM1_OCNPolarity;
u16 TIM1_OCIdleState;
u16 TIM1_OCNIdleState;
} TIM1_OCInitTypeDef;
/* TIM1 Input Capture Init structure definition */
typedef struct
{
u16 TIM1_Channel;
u16 TIM1_ICPolarity;
u16 TIM1_ICSelection;
u16 TIM1_ICPrescaler;
u8 TIM1_ICFilter;
} TIM1_ICInitTypeDef;
/* BDTR structure definition */
typedef struct
{
u16 TIM1_OSSRState;
u16 TIM1_OSSIState;
u16 TIM1_LOCKLevel;
u16 TIM1_DeadTime;
u16 TIM1_Break;
u16 TIM1_BreakPolarity;
u16 TIM1_AutomaticOutput;
} TIM1_BDTRInitTypeDef;
/* Exported constants --------------------------------------------------------*/
/* TIM1 Output Compare and PWM modes ----------------------------------------*/
#define TIM1_OCMode_Timing ((u16)0x0000)
#define TIM1_OCMode_Active ((u16)0x0010)
#define TIM1_OCMode_Inactive ((u16)0x0020)
#define TIM1_OCMode_Toggle ((u16)0x0030)
#define TIM1_OCMode_PWM1 ((u16)0x0060)
#define TIM1_OCMode_PWM2 ((u16)0x0070)
#define IS_TIM1_OC_MODE(MODE) ((MODE == TIM1_OCMode_Timing) || \
(MODE == TIM1_OCMode_Active) || \
(MODE == TIM1_OCMode_Inactive) || \
(MODE == TIM1_OCMode_Toggle)|| \
(MODE == TIM1_OCMode_PWM1) || \
(MODE == TIM1_OCMode_PWM2))
#define IS_TIM1_OCM(MODE)((MODE == TIM1_OCMode_Timing) || \
(MODE == TIM1_OCMode_Active) || \
(MODE == TIM1_OCMode_Inactive) || \
(MODE == TIM1_OCMode_Toggle)|| \
(MODE == TIM1_OCMode_PWM1) || \
(MODE == TIM1_OCMode_PWM2) || \
(MODE == TIM1_ForcedAction_Active) || \
(MODE == TIM1_ForcedAction_InActive))
/* TIM1 One Pulse Mode ------------------------------------------------------*/
#define TIM1_OPMode_Single ((u16)0x0001)
#define TIM1_OPMode_Repetitive ((u16)0x0000)
#define IS_TIM1_OPM_MODE(MODE) ((MODE == TIM1_OPMode_Single) || \
(MODE == TIM1_OPMode_Repetitive))
/* TIM1 Channel -------------------------------------------------------------*/
#define TIM1_Channel_1 ((u16)0x0000)
#define TIM1_Channel_2 ((u16)0x0001)
#define TIM1_Channel_3 ((u16)0x0002)
#define TIM1_Channel_4 ((u16)0x0003)
#define IS_TIM1_CHANNEL(CHANNEL) ((CHANNEL == TIM1_Channel_1) || \
(CHANNEL == TIM1_Channel_2) || \
(CHANNEL == TIM1_Channel_3) || \
(CHANNEL == TIM1_Channel_4))
#define IS_TIM1_PWMI_CHANNEL(CHANNEL) ((CHANNEL == TIM1_Channel_1) || \
(CHANNEL == TIM1_Channel_2))
#define IS_TIM1_COMPLEMENTARY_CHANNEL(CHANNEL) ((CHANNEL == TIM1_Channel_1) || \
(CHANNEL == TIM1_Channel_2) || \
(CHANNEL == TIM1_Channel_3))
/* TIM1 Clock Division CKD --------------------------------------------------*/
#define TIM1_CKD_DIV1 ((u16)0x0000)
#define TIM1_CKD_DIV2 ((u16)0x0100)
#define TIM1_CKD_DIV4 ((u16)0x0200)
#define IS_TIM1_CKD_DIV(DIV) ((DIV == TIM1_CKD_DIV1) || \
(DIV == TIM1_CKD_DIV2) || \
(DIV == TIM1_CKD_DIV4))
/* TIM1 Counter Mode --------------------------------------------------------*/
#define TIM1_CounterMode_Up ((u16)0x0000)
#define TIM1_CounterMode_Down ((u16)0x0010)
#define TIM1_CounterMode_CenterAligned1 ((u16)0x0020)
#define TIM1_CounterMode_CenterAligned2 ((u16)0x0040)
#define TIM1_CounterMode_CenterAligned3 ((u16)0x0060)
#define IS_TIM1_COUNTER_MODE(MODE) ((MODE == TIM1_CounterMode_Up) || \
(MODE == TIM1_CounterMode_Down) || \
(MODE == TIM1_CounterMode_CenterAligned1) || \
(MODE == TIM1_CounterMode_CenterAligned2) || \
(MODE == TIM1_CounterMode_CenterAligned3))
/* TIM1 Output Compare Polarity ---------------------------------------------*/
#define TIM1_OCPolarity_High ((u16)0x0000)
#define TIM1_OCPolarity_Low ((u16)0x0001)
#define IS_TIM1_OC_POLARITY(POLARITY) ((POLARITY == TIM1_OCPolarity_High) || \
(POLARITY == TIM1_OCPolarity_Low))
/* TIM1 Output Compare N Polarity -------------------------------------------*/
#define TIM1_OCNPolarity_High ((u16)0x0000)
#define TIM1_OCNPolarity_Low ((u16)0x0001)
#define IS_TIM1_OCN_POLARITY(POLARITY) ((POLARITY == TIM1_OCNPolarity_High) || \
(POLARITY == TIM1_OCNPolarity_Low))
/* TIM1 Output Compare states -----------------------------------------------*/
#define TIM1_OutputState_Disable ((u16)0x0000)
#define TIM1_OutputState_Enable ((u16)0x0001)
#define IS_TIM1_OUTPUT_STATE(STATE) ((STATE == TIM1_OutputState_Disable) || \
(STATE == TIM1_OutputState_Enable))
/* TIM1 Output Compare N States ---------------------------------------------*/
#define TIM1_OutputNState_Disable ((u16)0x0000)
#define TIM1_OutputNState_Enable ((u16)0x0001)
#define IS_TIM1_OUTPUTN_STATE(STATE) ((STATE == TIM1_OutputNState_Disable) || \
(STATE == TIM1_OutputNState_Enable))
/* Break Input enable/disable -----------------------------------------------*/
#define TIM1_Break_Enable ((u16)0x1000)
#define TIM1_Break_Disable ((u16)0x0000)
#define IS_TIM1_BREAK_STATE(STATE) ((STATE == TIM1_Break_Enable) || \
(STATE == TIM1_Break_Disable))
/* Break Polarity -----------------------------------------------------------*/
#define TIM1_BreakPolarity_Low ((u16)0x0000)
#define TIM1_BreakPolarity_High ((u16)0x2000)
#define IS_TIM1_BREAK_POLARITY(POLARITY) ((POLARITY == TIM1_BreakPolarity_Low) || \
(POLARITY == TIM1_BreakPolarity_High))
/* TIM1 AOE Bit Set/Reset ---------------------------------------------------*/
#define TIM1_AutomaticOutput_Enable ((u16)0x4000)
#define TIM1_AutomaticOutput_Disable ((u16)0x0000)
#define IS_TIM1_AUTOMATIC_OUTPUT_STATE(STATE) ((STATE == TIM1_AutomaticOutput_Enable) || \
(STATE == TIM1_AutomaticOutput_Disable))
/* Lock levels --------------------------------------------------------------*/
#define TIM1_LOCKLevel_OFF ((u16)0x0000)
#define TIM1_LOCKLevel_1 ((u16)0x0100)
#define TIM1_LOCKLevel_2 ((u16)0x0200)
#define TIM1_LOCKLevel_3 ((u16)0x0300)
#define IS_TIM1_LOCK_LEVEL(LEVEL) ((LEVEL == TIM1_LOCKLevel_OFF) || \
(LEVEL == TIM1_LOCKLevel_1) || \
(LEVEL == TIM1_LOCKLevel_2) || \
(LEVEL == TIM1_LOCKLevel_3))
/* OSSI: Off-State Selection for Idle mode states ---------------------------*/
#define TIM1_OSSIState_Enable ((u16)0x0400)
#define TIM1_OSSIState_Disable ((u16)0x0000)
#define IS_TIM1_OSSI_STATE(STATE) ((STATE == TIM1_OSSIState_Enable) || \
(STATE == TIM1_OSSIState_Disable))
/* OSSR: Off-State Selection for Run mode states ----------------------------*/
#define TIM1_OSSRState_Enable ((u16)0x0800)
#define TIM1_OSSRState_Disable ((u16)0x0000)
#define IS_TIM1_OSSR_STATE(STATE) ((STATE == TIM1_OSSRState_Enable) || \
(STATE == TIM1_OSSRState_Disable))
/* TIM1 Output Compare Idle State -------------------------------------------*/
#define TIM1_OCIdleState_Set ((u16)0x0001)
#define TIM1_OCIdleState_Reset ((u16)0x0000)
#define IS_TIM1_OCIDLE_STATE(STATE) ((STATE == TIM1_OCIdleState_Set) || \
(STATE == TIM1_OCIdleState_Reset))
/* TIM1 Output Compare N Idle State -----------------------------------------*/
#define TIM1_OCNIdleState_Set ((u16)0x0001)
#define TIM1_OCNIdleState_Reset ((u16)0x0000)
#define IS_TIM1_OCNIDLE_STATE(STATE) ((STATE == TIM1_OCNIdleState_Set) || \
(STATE == TIM1_OCNIdleState_Reset))
/* TIM1 Input Capture Polarity ----------------------------------------------*/
#define TIM1_ICPolarity_Rising ((u16)0x0000)
#define TIM1_ICPolarity_Falling ((u16)0x0001)
#define IS_TIM1_IC_POLARITY(POLARITY) ((POLARITY == TIM1_ICPolarity_Rising) || \
(POLARITY == TIM1_ICPolarity_Falling))
/* TIM1 Input Capture Selection ---------------------------------------------*/
#define TIM1_ICSelection_DirectTI ((u16)0x0001)
#define TIM1_ICSelection_IndirectTI ((u16)0x0002)
#define TIM1_ICSelection_TRGI ((u16)0x0003)
#define IS_TIM1_IC_SELECTION(SELECTION) ((SELECTION == TIM1_ICSelection_DirectTI) || \
(SELECTION == TIM1_ICSelection_IndirectTI) || \
(SELECTION == TIM1_ICSelection_TRGI))
/* TIM1 Input Capture Prescaler ---------------------------------------------*/
#define TIM1_ICPSC_DIV1 ((u16)0x0000)
#define TIM1_ICPSC_DIV2 ((u16)0x0004)
#define TIM1_ICPSC_DIV4 ((u16)0x0008)
#define TIM1_ICPSC_DIV8 ((u16)0x000C)
#define IS_TIM1_IC_PRESCALER(PRESCALER) ((PRESCALER == TIM1_ICPSC_DIV1) || \
(PRESCALER == TIM1_ICPSC_DIV2) || \
(PRESCALER == TIM1_ICPSC_DIV4) || \
(PRESCALER == TIM1_ICPSC_DIV8))
/* TIM1 Input Capture Filer Value ---------------------------------------------*/
#define IS_TIM1_IC_FILTER(ICFILTER) (ICFILTER <= 0xF)
/* TIM1 interrupt sources ---------------------------------------------------*/
#define TIM1_IT_Update ((u16)0x0001)
#define TIM1_IT_CC1 ((u16)0x0002)
#define TIM1_IT_CC2 ((u16)0x0004)
#define TIM1_IT_CC3 ((u16)0x0008)
#define TIM1_IT_CC4 ((u16)0x0010)
#define TIM1_IT_COM ((u16)0x0020)
#define TIM1_IT_Trigger ((u16)0x0040)
#define TIM1_IT_Break ((u16)0x0080)
#define IS_TIM1_IT(IT) (((IT & (u16)0xFF00) == 0x0000) && (IT != 0x0000))
#define IS_TIM1_GET_IT(IT) ((IT == TIM1_IT_Update) || \
(IT == TIM1_IT_CC1) || \
(IT == TIM1_IT_CC2) || \
(IT == TIM1_IT_CC3) || \
(IT == TIM1_IT_CC4) || \
(IT == TIM1_IT_COM) || \
(IT == TIM1_IT_Trigger) || \
(IT == TIM1_IT_Break))
/* TIM1 DMA Base address ----------------------------------------------------*/
#define TIM1_DMABase_CR1 ((u16)0x0000)
#define TIM1_DMABase_CR2 ((u16)0x0001)
#define TIM1_DMABase_SMCR ((u16)0x0002)
#define TIM1_DMABase_DIER ((u16)0x0003)
#define TIM1_DMABase_SR ((u16)0x0004)
#define TIM1_DMABase_EGR ((u16)0x0005)
#define TIM1_DMABase_CCMR1 ((u16)0x0006)
#define TIM1_DMABase_CCMR2 ((u16)0x0007)
#define TIM1_DMABase_CCER ((u16)0x0008)
#define TIM1_DMABase_CNT ((u16)0x0009)
#define TIM1_DMABase_PSC ((u16)0x000A)
#define TIM1_DMABase_ARR ((u16)0x000B)
#define TIM1_DMABase_RCR ((u16)0x000C)
#define TIM1_DMABase_CCR1 ((u16)0x000D)
#define TIM1_DMABase_CCR2 ((u16)0x000E)
#define TIM1_DMABase_CCR3 ((u16)0x000F)
#define TIM1_DMABase_CCR4 ((u16)0x0010)
#define TIM1_DMABase_BDTR ((u16)0x0011)
#define TIM1_DMABase_DCR ((u16)0x0012)
#define IS_TIM1_DMA_BASE(BASE) ((BASE == TIM1_DMABase_CR1) || \
(BASE == TIM1_DMABase_CR2) || \
(BASE == TIM1_DMABase_SMCR) || \
(BASE == TIM1_DMABase_DIER) || \
(BASE == TIM1_DMABase_SR) || \
(BASE == TIM1_DMABase_EGR) || \
(BASE == TIM1_DMABase_CCMR1) || \
(BASE == TIM1_DMABase_CCMR2) || \
(BASE == TIM1_DMABase_CCER) || \
(BASE == TIM1_DMABase_CNT) || \
(BASE == TIM1_DMABase_PSC) || \
(BASE == TIM1_DMABase_ARR) || \
(BASE == TIM1_DMABase_RCR) || \
(BASE == TIM1_DMABase_CCR1) || \
(BASE == TIM1_DMABase_CCR2) || \
(BASE == TIM1_DMABase_CCR3) || \
(BASE == TIM1_DMABase_CCR4) || \
(BASE == TIM1_DMABase_BDTR) || \
(BASE == TIM1_DMABase_DCR))
/* TIM1 DMA Burst Length ----------------------------------------------------*/
#define TIM1_DMABurstLength_1Byte ((u16)0x0000)
#define TIM1_DMABurstLength_2Bytes ((u16)0x0100)
#define TIM1_DMABurstLength_3Bytes ((u16)0x0200)
#define TIM1_DMABurstLength_4Bytes ((u16)0x0300)
#define TIM1_DMABurstLength_5Bytes ((u16)0x0400)
#define TIM1_DMABurstLength_6Bytes ((u16)0x0500)
#define TIM1_DMABurstLength_7Bytes ((u16)0x0600)
#define TIM1_DMABurstLength_8Bytes ((u16)0x0700)
#define TIM1_DMABurstLength_9Bytes ((u16)0x0800)
#define TIM1_DMABurstLength_10Bytes ((u16)0x0900)
#define TIM1_DMABurstLength_11Bytes ((u16)0x0A00)
#define TIM1_DMABurstLength_12Bytes ((u16)0x0B00)
#define TIM1_DMABurstLength_13Bytes ((u16)0x0C00)
#define TIM1_DMABurstLength_14Bytes ((u16)0x0D00)
#define TIM1_DMABurstLength_15Bytes ((u16)0x0E00)
#define TIM1_DMABurstLength_16Bytes ((u16)0x0F00)
#define TIM1_DMABurstLength_17Bytes ((u16)0x1000)
#define TIM1_DMABurstLength_18Bytes ((u16)0x1100)
#define IS_TIM1_DMA_LENGTH(LENGTH) ((LENGTH == TIM1_DMABurstLength_1Byte) || \
(LENGTH == TIM1_DMABurstLength_2Bytes) || \
(LENGTH == TIM1_DMABurstLength_3Bytes) || \
(LENGTH == TIM1_DMABurstLength_4Bytes) || \
(LENGTH == TIM1_DMABurstLength_5Bytes) || \
(LENGTH == TIM1_DMABurstLength_6Bytes) || \
(LENGTH == TIM1_DMABurstLength_7Bytes) || \
(LENGTH == TIM1_DMABurstLength_8Bytes) || \
(LENGTH == TIM1_DMABurstLength_9Bytes) || \
(LENGTH == TIM1_DMABurstLength_10Bytes) || \
(LENGTH == TIM1_DMABurstLength_11Bytes) || \
(LENGTH == TIM1_DMABurstLength_12Bytes) || \
(LENGTH == TIM1_DMABurstLength_13Bytes) || \
(LENGTH == TIM1_DMABurstLength_14Bytes) || \
(LENGTH == TIM1_DMABurstLength_15Bytes) || \
(LENGTH == TIM1_DMABurstLength_16Bytes) || \
(LENGTH == TIM1_DMABurstLength_17Bytes) || \
(LENGTH == TIM1_DMABurstLength_18Bytes))
/* TIM1 DMA sources ---------------------------------------------------------*/
#define TIM1_DMA_Update ((u16)0x0100)
#define TIM1_DMA_CC1 ((u16)0x0200)
#define TIM1_DMA_CC2 ((u16)0x0400)
#define TIM1_DMA_CC3 ((u16)0x0800)
#define TIM1_DMA_CC4 ((u16)0x1000)
#define TIM1_DMA_COM ((u16)0x2000)
#define TIM1_DMA_Trigger ((u16)0x4000)
#define IS_TIM1_DMA_SOURCE(SOURCE) (((SOURCE & (u16)0x80FF) == 0x0000) && (SOURCE != 0x0000))
/* TIM1 External Trigger Prescaler ------------------------------------------*/
#define TIM1_ExtTRGPSC_OFF ((u16)0x0000)
#define TIM1_ExtTRGPSC_DIV2 ((u16)0x1000)
#define TIM1_ExtTRGPSC_DIV4 ((u16)0x2000)
#define TIM1_ExtTRGPSC_DIV8 ((u16)0x3000)
#define IS_TIM1_EXT_PRESCALER(PRESCALER) ((PRESCALER == TIM1_ExtTRGPSC_OFF) || \
(PRESCALER == TIM1_ExtTRGPSC_DIV2) || \
(PRESCALER == TIM1_ExtTRGPSC_DIV4) || \
(PRESCALER == TIM1_ExtTRGPSC_DIV8))
/* TIM1 Internal Trigger Selection ------------------------------------------*/
#define TIM1_TS_ITR0 ((u16)0x0000)
#define TIM1_TS_ITR1 ((u16)0x0010)
#define TIM1_TS_ITR2 ((u16)0x0020)
#define TIM1_TS_ITR3 ((u16)0x0030)
#define TIM1_TS_TI1F_ED ((u16)0x0040)
#define TIM1_TS_TI1FP1 ((u16)0x0050)
#define TIM1_TS_TI2FP2 ((u16)0x0060)
#define TIM1_TS_ETRF ((u16)0x0070)
#define IS_TIM1_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM1_TS_ITR0) || \
(SELECTION == TIM1_TS_ITR1) || \
(SELECTION == TIM1_TS_ITR2) || \
(SELECTION == TIM1_TS_ITR3) || \
(SELECTION == TIM1_TS_TI1F_ED) || \
(SELECTION == TIM1_TS_TI1FP1) || \
(SELECTION == TIM1_TS_TI2FP2) || \
(SELECTION == TIM1_TS_ETRF))
#define IS_TIM1_INTERNAL_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM1_TS_ITR0) || \
(SELECTION == TIM1_TS_ITR1) || \
(SELECTION == TIM1_TS_ITR2) || \
(SELECTION == TIM1_TS_ITR3))
#define IS_TIM1_TIX_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM1_TS_TI1F_ED) || \
(SELECTION == TIM1_TS_TI1FP1) || \
(SELECTION == TIM1_TS_TI2FP2))
/* TIM1 External Trigger Polarity -------------------------------------------*/
#define TIM1_ExtTRGPolarity_Inverted ((u16)0x8000)
#define TIM1_ExtTRGPolarity_NonInverted ((u16)0x0000)
#define IS_TIM1_EXT_POLARITY(POLARITY) ((POLARITY == TIM1_ExtTRGPolarity_Inverted) || \
(POLARITY == TIM1_ExtTRGPolarity_NonInverted))
/* TIM1 Prescaler Reload Mode -----------------------------------------------*/
#define TIM1_PSCReloadMode_Update ((u16)0x0000)
#define TIM1_PSCReloadMode_Immediate ((u16)0x0001)
#define IS_TIM1_PRESCALER_RELOAD(RELOAD) ((RELOAD == TIM1_PSCReloadMode_Update) || \
(RELOAD == TIM1_PSCReloadMode_Immediate))
/* TIM1 Forced Action -------------------------------------------------------*/
#define TIM1_ForcedAction_Active ((u16)0x0050)
#define TIM1_ForcedAction_InActive ((u16)0x0040)
#define IS_TIM1_FORCED_ACTION(ACTION) ((ACTION == TIM1_ForcedAction_Active) || \
(ACTION == TIM1_ForcedAction_InActive))
/* TIM1 Encoder Mode --------------------------------------------------------*/
#define TIM1_EncoderMode_TI1 ((u16)0x0001)
#define TIM1_EncoderMode_TI2 ((u16)0x0002)
#define TIM1_EncoderMode_TI12 ((u16)0x0003)
#define IS_TIM1_ENCODER_MODE(MODE) ((MODE == TIM1_EncoderMode_TI1) || \
(MODE == TIM1_EncoderMode_TI2) || \
(MODE == TIM1_EncoderMode_TI12))
/* TIM1 Event Source --------------------------------------------------------*/
#define TIM1_EventSource_Update ((u16)0x0001)
#define TIM1_EventSource_CC1 ((u16)0x0002)
#define TIM1_EventSource_CC2 ((u16)0x0004)
#define TIM1_EventSource_CC3 ((u16)0x0008)
#define TIM1_EventSource_CC4 ((u16)0x0010)
#define TIM1_EventSource_COM ((u16)0x0020)
#define TIM1_EventSource_Trigger ((u16)0x0040)
#define TIM1_EventSource_Break ((u16)0x0080)
#define IS_TIM1_EVENT_SOURCE(SOURCE) (((SOURCE & (u16)0xFF00) == 0x0000) && (SOURCE != 0x0000))
/* TIM1 Update Source -------------------------------------------------------*/
#define TIM1_UpdateSource_Global ((u16)0x0000)
#define TIM1_UpdateSource_Regular ((u16)0x0001)
#define IS_TIM1_UPDATE_SOURCE(SOURCE) ((SOURCE == TIM1_UpdateSource_Global) || \
(SOURCE == TIM1_UpdateSource_Regular))
/* TIM1 Ouput Compare Preload State ------------------------------------------*/
#define TIM1_OCPreload_Enable ((u16)0x0001)
#define TIM1_OCPreload_Disable ((u16)0x0000)
#define IS_TIM1_OCPRELOAD_STATE(STATE) ((STATE == TIM1_OCPreload_Enable) || \
(STATE == TIM1_OCPreload_Disable))
/* TIM1 Ouput Compare Fast State ---------------------------------------------*/
#define TIM1_OCFast_Enable ((u16)0x0001)
#define TIM1_OCFast_Disable ((u16)0x0000)
#define IS_TIM1_OCFAST_STATE(STATE) ((STATE == TIM1_OCFast_Enable) || \
(STATE == TIM1_OCFast_Disable))
/* TIM1 Trigger Output Source -----------------------------------------------*/
#define TIM1_TRGOSource_Reset ((u16)0x0000)
#define TIM1_TRGOSource_Enable ((u16)0x0010)
#define TIM1_TRGOSource_Update ((u16)0x0020)
#define TIM1_TRGOSource_OC1 ((u16)0x0030)
#define TIM1_TRGOSource_OC1Ref ((u16)0x0040)
#define TIM1_TRGOSource_OC2Ref ((u16)0x0050)
#define TIM1_TRGOSource_OC3Ref ((u16)0x0060)
#define TIM1_TRGOSource_OC4Ref ((u16)0x0070)
#define IS_TIM1_TRGO_SOURCE(SOURCE) ((SOURCE == TIM1_TRGOSource_Reset) || \
(SOURCE == TIM1_TRGOSource_Enable) || \
(SOURCE == TIM1_TRGOSource_Update) || \
(SOURCE == TIM1_TRGOSource_OC1) || \
(SOURCE == TIM1_TRGOSource_OC1Ref) || \
(SOURCE == TIM1_TRGOSource_OC2Ref) || \
(SOURCE == TIM1_TRGOSource_OC3Ref) || \
(SOURCE == TIM1_TRGOSource_OC4Ref))
/* TIM1 Slave Mode ----------------------------------------------------------*/
#define TIM1_SlaveMode_Reset ((u16)0x0004)
#define TIM1_SlaveMode_Gated ((u16)0x0005)
#define TIM1_SlaveMode_Trigger ((u16)0x0006)
#define TIM1_SlaveMode_External1 ((u16)0x0007)
#define IS_TIM1_SLAVE_MODE(MODE) ((MODE == TIM1_SlaveMode_Reset) || \
(MODE == TIM1_SlaveMode_Gated) || \
(MODE == TIM1_SlaveMode_Trigger) || \
(MODE == TIM1_SlaveMode_External1))
/* TIM1 TIx External Clock Source -------------------------------------------*/
#define TIM1_TIxExternalCLK1Source_TI1 ((u16)0x0050)
#define TIM1_TIxExternalCLK1Source_TI2 ((u16)0x0060)
#define TIM1_TIxExternalCLK1Source_TI1ED ((u16)0x0040)
#define IS_TIM1_TIXCLK_SOURCE(SOURCE) ((SOURCE == TIM1_TIxExternalCLK1Source_TI1) || \
(SOURCE == TIM1_TIxExternalCLK1Source_TI2) || \
(SOURCE == TIM1_TIxExternalCLK1Source_TI1ED))
/* TIM1 Master Slave Mode ---------------------------------------------------*/
#define TIM1_MasterSlaveMode_Enable ((u16)0x0001)
#define TIM1_MasterSlaveMode_Disable ((u16)0x0000)
#define IS_TIM1_MSM_STATE(STATE) ((STATE == TIM1_MasterSlaveMode_Enable) || \
(STATE == TIM1_MasterSlaveMode_Disable))
/* TIM1 Flags ---------------------------------------------------------------*/
#define TIM1_FLAG_Update ((u16)0x0001)
#define TIM1_FLAG_CC1 ((u16)0x0002)
#define TIM1_FLAG_CC2 ((u16)0x0004)
#define TIM1_FLAG_CC3 ((u16)0x0008)
#define TIM1_FLAG_CC4 ((u16)0x0010)
#define TIM1_FLAG_COM ((u16)0x0020)
#define TIM1_FLAG_Trigger ((u16)0x0040)
#define TIM1_FLAG_Break ((u16)0x0080)
#define TIM1_FLAG_CC1OF ((u16)0x0200)
#define TIM1_FLAG_CC2OF ((u16)0x0400)
#define TIM1_FLAG_CC3OF ((u16)0x0800)
#define TIM1_FLAG_CC4OF ((u16)0x1000)
#define IS_TIM1_GET_FLAG(FLAG) ((FLAG == TIM1_FLAG_Update) || \
(FLAG == TIM1_FLAG_CC1) || \
(FLAG == TIM1_FLAG_CC2) || \
(FLAG == TIM1_FLAG_CC3) || \
(FLAG == TIM1_FLAG_CC4) || \
(FLAG == TIM1_FLAG_COM) || \
(FLAG == TIM1_FLAG_Trigger) || \
(FLAG == TIM1_FLAG_Break) || \
(FLAG == TIM1_FLAG_CC1OF) || \
(FLAG == TIM1_FLAG_CC2OF) || \
(FLAG == TIM1_FLAG_CC3OF) || \
(FLAG == TIM1_FLAG_CC4OF))
#define IS_TIM1_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xE100) == 0x0000) && (FLAG != 0x0000))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
void TIM1_DeInit(void);
void TIM1_TimeBaseInit(TIM1_TimeBaseInitTypeDef* TIM1_TimeBaseInitStruct);
void TIM1_OC1Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct);
void TIM1_OC2Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct);
void TIM1_OC3Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct);
void TIM1_OC4Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct);
void TIM1_BDTRConfig(TIM1_BDTRInitTypeDef *TIM1_BDTRInitStruct);
void TIM1_ICInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct);
void TIM1_PWMIConfig(TIM1_ICInitTypeDef* TIM1_ICInitStruct);
void TIM1_TimeBaseStructInit(TIM1_TimeBaseInitTypeDef* TIM1_TimeBaseInitStruct);
void TIM1_OCStructInit(TIM1_OCInitTypeDef* TIM1_OCInitStruct);
void TIM1_ICStructInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct);
void TIM1_BDTRStructInit(TIM1_BDTRInitTypeDef* TIM1_BDTRInitStruct);
void TIM1_Cmd(FunctionalState NewState);
void TIM1_CtrlPWMOutputs(FunctionalState Newstate);
void TIM1_ITConfig(u16 TIM1_IT, FunctionalState NewState);
void TIM1_DMAConfig(u16 TIM1_DMABase, u16 TIM1_DMABurstLength);
void TIM1_DMACmd(u16 TIM1_DMASource, FunctionalState Newstate);
void TIM1_InternalClockConfig(void);
void TIM1_ETRClockMode1Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity,
u16 ExtTRGFilter);
void TIM1_ETRClockMode2Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity,
u16 ExtTRGFilter);
void TIM1_ITRxExternalClockConfig(u16 TIM1_InputTriggerSource);
void TIM1_TIxExternalClockConfig(u16 TIM1_TIxExternalCLKSource, u16 TIM1_ICPolarity,
u8 ICFilter);
void TIM1_SelectInputTrigger(u16 TIM1_InputTriggerSource);
void TIM1_UpdateDisableConfig(FunctionalState Newstate);
void TIM1_UpdateRequestConfig(u8 TIM1_UpdateSource);
void TIM1_SelectHallSensor(FunctionalState Newstate);
void TIM1_SelectOnePulseMode(u16 TIM1_OPMode);
void TIM1_SelectOutputTrigger(u16 TIM1_TRGOSource);
void TIM1_SelectSlaveMode(u16 TIM1_SlaveMode);
void TIM1_SelectMasterSlaveMode(u16 TIM1_MasterSlaveMode);
void TIM1_EncoderInterfaceConfig(u16 TIM1_EncoderMode, u16 TIM1_IC1Polarity,
u16 TIM1_IC2Polarity);
void TIM1_PrescalerConfig(u16 Prescaler, u16 TIM1_PSCReloadMode);
void TIM1_CounterModeConfig(u16 TIM1_CounterMode);
void TIM1_ForcedOC1Config(u16 TIM1_ForcedAction);
void TIM1_ForcedOC2Config(u16 TIM1_ForcedAction);
void TIM1_ForcedOC3Config(u16 TIM1_ForcedAction);
void TIM1_ForcedOC4Config(u16 TIM1_ForcedAction);
void TIM1_ARRPreloadConfig(FunctionalState Newstate);
void TIM1_SelectCOM(FunctionalState Newstate);
void TIM1_SelectCCDMA(FunctionalState Newstate);
void TIM1_CCPreloadControl(FunctionalState Newstate);
void TIM1_OC1PreloadConfig(u16 TIM1_OCPreload);
void TIM1_OC2PreloadConfig(u16 TIM1_OCPreload);
void TIM1_OC3PreloadConfig(u16 TIM1_OCPreload);
void TIM1_OC4PreloadConfig(u16 TIM1_OCPreload);
void TIM1_OC1FastConfig(u16 TIM1_OCFast);
void TIM1_OC2FastConfig(u16 TIM1_OCFast);
void TIM1_OC3FastConfig(u16 TIM1_OCFast);
void TIM1_OC4FastConfig(u16 TIM1_OCFast);
void TIM1_GenerateEvent(u16 TIM1_EventSource);
void TIM1_OC1PolarityConfig(u16 TIM1_OCPolarity);
void TIM1_OC1NPolarityConfig(u16 TIM1_OCPolarity);
void TIM1_OC2PolarityConfig(u16 TIM1_OCPolarity);
void TIM1_OC2NPolarityConfig(u16 TIM1_OCPolarity);
void TIM1_OC3PolarityConfig(u16 TIM1_OCPolarity);
void TIM1_OC3NPolarityConfig(u16 TIM1_OCPolarity);
void TIM1_OC4PolarityConfig(u16 TIM1_OCPolarity);
void TIM1_CCxCmd(u16 TIM1_Channel, FunctionalState Newstate);
void TIM1_CCxNCmd(u16 TIM1_Channel, FunctionalState Newstate);
void TIM1_SelectOCxM(u16 TIM1_Channel, u16 TIM1_OCMode);
void TIM1_SetAutoreload(u16 Autoreload);
void TIM1_SetCompare1(u16 Compare1);
void TIM1_SetCompare2(u16 Compare2);
void TIM1_SetCompare3(u16 Compare3);
void TIM1_SetCompare4(u16 Compare4);
void TIM1_SetIC1Prescaler(u16 TIM1_IC1Prescaler);
void TIM1_SetIC2Prescaler(u16 TIM1_IC2Prescaler);
void TIM1_SetIC3Prescaler(u16 TIM1_IC3Prescaler);
void TIM1_SetIC4Prescaler(u16 TIM1_IC4Prescaler);
void TIM1_SetClockDivision(u16 TIM1_CKD);
u16 TIM1_GetCapture1(void);
u16 TIM1_GetCapture2(void);
u16 TIM1_GetCapture3(void);
u16 TIM1_GetCapture4(void);
u16 TIM1_GetCounter(void);
u16 TIM1_GetPrescaler(void);
FlagStatus TIM1_GetFlagStatus(u16 TIM1_FLAG);
void TIM1_ClearFlag(u16 TIM1_Flag);
ITStatus TIM1_GetITStatus(u16 TIM1_IT);
void TIM1_ClearITPendingBit(u16 TIM1_IT);
#endif /*__STM32F10x_TIM1_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_tim1.h | C | oos | 34,043 |
/**
******************************************************************************
* @file stm32f10x_fsmc.h
* @author MCD Application Team
* @version V3.0.0
* @date 04/06/2009
* @brief This file contains all the functions prototypes for the FSMC
* firmware library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_FSMC_H
#define __STM32F10x_FSMC_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @addtogroup FSMC
* @{
*/
/** @defgroup FSMC_Exported_Types
* @{
*/
/**
* @brief Timing parameters For NOR/SRAM Banks
*/
typedef struct
{
uint32_t FSMC_AddressSetupTime;
uint32_t FSMC_AddressHoldTime;
uint32_t FSMC_DataSetupTime;
uint32_t FSMC_BusTurnAroundDuration;
uint32_t FSMC_CLKDivision;
uint32_t FSMC_DataLatency;
uint32_t FSMC_AccessMode;
}FSMC_NORSRAMTimingInitTypeDef;
/**
* @brief FSMC NOR/SRAM Init structure definition
*/
typedef struct
{
uint32_t FSMC_Bank;
uint32_t FSMC_DataAddressMux;
uint32_t FSMC_MemoryType;
uint32_t FSMC_MemoryDataWidth;
uint32_t FSMC_BurstAccessMode;
uint32_t FSMC_WaitSignalPolarity;
uint32_t FSMC_WrapMode;
uint32_t FSMC_WaitSignalActive;
uint32_t FSMC_WriteOperation;
uint32_t FSMC_WaitSignal;
uint32_t FSMC_ExtendedMode;
uint32_t FSMC_WriteBurst;
FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct;/* Timing Parameters for write and read access if the ExtendedMode is not used*/
FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;/* Timing Parameters for write access if the ExtendedMode is used*/
}FSMC_NORSRAMInitTypeDef;
/**
* @brief Timing parameters For FSMC NAND and PCCARD Banks
*/
typedef struct
{
uint32_t FSMC_SetupTime;
uint32_t FSMC_WaitSetupTime;
uint32_t FSMC_HoldSetupTime;
uint32_t FSMC_HiZSetupTime;
}FSMC_NAND_PCCARDTimingInitTypeDef;
/**
* @brief FSMC NAND Init structure definition
*/
typedef struct
{
uint32_t FSMC_Bank;
uint32_t FSMC_Waitfeature;
uint32_t FSMC_MemoryDataWidth;
uint32_t FSMC_ECC;
uint32_t FSMC_ECCPageSize;
uint32_t FSMC_TCLRSetupTime;
uint32_t FSMC_TARSetupTime;
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct;/* FSMC Common Space Timing */
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct;/* FSMC Attribute Space Timing */
}FSMC_NANDInitTypeDef;
/**
* @brief FSMC PCCARD Init structure definition
*/
typedef struct
{
uint32_t FSMC_Waitfeature;
uint32_t FSMC_TCLRSetupTime;
uint32_t FSMC_TARSetupTime;
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct;/* FSMC Common Space Timing */
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /* FSMC Attribute Space Timing */
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /* FSMC IO Space Timing */
}FSMC_PCCARDInitTypeDef;
/**
* @}
*/
/** @defgroup FSMC_Exported_Constants
* @{
*/
/** @defgroup FSMC_Banks_definitions
* @{
*/
#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
#define FSMC_Bank2_NAND ((uint32_t)0x00000010)
#define FSMC_Bank3_NAND ((uint32_t)0x00000100)
#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)
#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
((BANK) == FSMC_Bank1_NORSRAM2) || \
((BANK) == FSMC_Bank1_NORSRAM3) || \
((BANK) == FSMC_Bank1_NORSRAM4))
#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
((BANK) == FSMC_Bank3_NAND))
#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
((BANK) == FSMC_Bank3_NAND) || \
((BANK) == FSMC_Bank4_PCCARD))
#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
((BANK) == FSMC_Bank3_NAND) || \
((BANK) == FSMC_Bank4_PCCARD))
/**
* @}
*/
/** @defgroup NOR_SRAM_Banks
* @{
*/
/** @defgroup FSMC_Data_Address_Bus_Multiplexing
* @{
*/
#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
((MUX) == FSMC_DataAddressMux_Enable))
/**
* @}
*/
/** @defgroup FSMC_Memory_Type
* @{
*/
#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
((MEMORY) == FSMC_MemoryType_PSRAM)|| \
((MEMORY) == FSMC_MemoryType_NOR))
/**
* @}
*/
/** @defgroup FSMC_Data_Width
* @{
*/
#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
((WIDTH) == FSMC_MemoryDataWidth_16b))
/**
* @}
*/
/** @defgroup FSMC_Burst_Access_Mode
* @{
*/
#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
((STATE) == FSMC_BurstAccessMode_Enable))
/**
* @}
*/
/** @defgroup FSMC_Wait_Signal_Polarity
* @{
*/
#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
((POLARITY) == FSMC_WaitSignalPolarity_High))
/**
* @}
*/
/** @defgroup FSMC_Wrap_Mode
* @{
*/
#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
#define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
((MODE) == FSMC_WrapMode_Enable))
/**
* @}
*/
/** @defgroup FSMC_Wait_Timing
* @{
*/
#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
/**
* @}
*/
/** @defgroup FSMC_Write_Operation
* @{
*/
#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
((OPERATION) == FSMC_WriteOperation_Enable))
/**
* @}
*/
/** @defgroup FSMC_Wait_Signal
* @{
*/
#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
((SIGNAL) == FSMC_WaitSignal_Enable))
/**
* @}
*/
/** @defgroup FSMC_Extended_Mode
* @{
*/
#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
((MODE) == FSMC_ExtendedMode_Enable))
/**
* @}
*/
/** @defgroup FSMC_Write_Burst
* @{
*/
#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
((BURST) == FSMC_WriteBurst_Enable))
/**
* @}
*/
/** @defgroup FSMC_Address_Setup_Time
* @{
*/
#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
/**
* @}
*/
/** @defgroup FSMC_Address_Hold_Time
* @{
*/
#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
/**
* @}
*/
/** @defgroup FSMC_Data_Setup_Time
* @{
*/
#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
/**
* @}
*/
/** @defgroup FSMC_Bus_Turn_around_Duration
* @{
*/
#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
/**
* @}
*/
/** @defgroup FSMC_CLK_Division
* @{
*/
#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
/**
* @}
*/
/** @defgroup FSMC_Data_Latency
* @{
*/
#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
/**
* @}
*/
/** @defgroup FSMC_Access_Mode
* @{
*/
#define FSMC_AccessMode_A ((uint32_t)0x00000000)
#define FSMC_AccessMode_B ((uint32_t)0x10000000)
#define FSMC_AccessMode_C ((uint32_t)0x20000000)
#define FSMC_AccessMode_D ((uint32_t)0x30000000)
#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
((MODE) == FSMC_AccessMode_B) || \
((MODE) == FSMC_AccessMode_C) || \
((MODE) == FSMC_AccessMode_D))
/**
* @}
*/
/**
* @}
*/
/** @defgroup NAND_and_PCCARD_Banks
* @{
*/
/** @defgroup FSMC_Wait_feature
* @{
*/
#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
((FEATURE) == FSMC_Waitfeature_Enable))
/**
* @}
*/
/** @defgroup FSMC_Memory_Data_Width
* @{
*/
#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
#define IS_FSMC_DATA_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
((WIDTH) == FSMC_MemoryDataWidth_16b))
/**
* @}
*/
/** @defgroup FSMC_ECC
* @{
*/
#define FSMC_ECC_Disable ((uint32_t)0x00000000)
#define FSMC_ECC_Enable ((uint32_t)0x00000040)
#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
((STATE) == FSMC_ECC_Enable))
/**
* @}
*/
/** @defgroup FSMC_ECC_Page_Size
* @{
*/
#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
((SIZE) == FSMC_ECCPageSize_512Bytes) || \
((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
((SIZE) == FSMC_ECCPageSize_8192Bytes))
/**
* @}
*/
/** @defgroup FSMC_TCLR_Setup_Time
* @{
*/
#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
/**
* @}
*/
/** @defgroup FSMC_TAR_Setup_Time
* @{
*/
#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
/**
* @}
*/
/** @defgroup FSMC_Setup_Time
* @{
*/
#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
/**
* @}
*/
/** @defgroup FSMC_Wait_Setup_Time
* @{
*/
#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
/**
* @}
*/
/** @defgroup FSMC_Hold_Setup_Time
* @{
*/
#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
/**
* @}
*/
/** @defgroup FSMC_HiZ_Setup_Time
* @{
*/
#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
/**
* @}
*/
/** @defgroup FSMC_Interrupt_sources
* @{
*/
#define FSMC_IT_RisingEdge ((uint32_t)0x00000008)
#define FSMC_IT_Level ((uint32_t)0x00000010)
#define FSMC_IT_FallingEdge ((uint32_t)0x00000020)
#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
((IT) == FSMC_IT_Level) || \
((IT) == FSMC_IT_FallingEdge))
/**
* @}
*/
/** @defgroup FSMC_Flags
* @{
*/
#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
#define FSMC_FLAG_Level ((uint32_t)0x00000002)
#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
((FLAG) == FSMC_FLAG_Level) || \
((FLAG) == FSMC_FLAG_FallingEdge) || \
((FLAG) == FSMC_FLAG_FEMPT))
#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/** @defgroup FSMC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup FSMC_Exported_Functions
* @{
*/
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
void FSMC_NANDDeInit(uint32_t FSMC_Bank);
void FSMC_PCCARDDeInit(void);
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
void FSMC_PCCARDCmd(FunctionalState NewState);
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
#endif /*__STM32F10x_FSMC_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_fsmc.h | C | oos | 17,276 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_gpio.h
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file contains all the functions prototypes for the
* GPIO firmware library.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_GPIO_H
#define __STM32F10x_GPIO_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* Output Maximum frequency selection ----------------------------------------*/
typedef enum
{
GPIO_Speed_10MHz = 1,
GPIO_Speed_2MHz,
GPIO_Speed_50MHz
}GPIOSpeed_TypeDef;
#define IS_GPIO_SPEED(SPEED) ((SPEED == GPIO_Speed_10MHz) || (SPEED == GPIO_Speed_2MHz) || \
(SPEED == GPIO_Speed_50MHz))
/* Configuration Mode enumeration --------------------------------------------*/
typedef enum
{ GPIO_Mode_AIN = 0x0,
GPIO_Mode_IN_FLOATING = 0x04,
GPIO_Mode_IPD = 0x28,
GPIO_Mode_IPU = 0x48,
GPIO_Mode_Out_OD = 0x14,
GPIO_Mode_Out_PP = 0x10,
GPIO_Mode_AF_OD = 0x1C,
GPIO_Mode_AF_PP = 0x18
}GPIOMode_TypeDef;
#define IS_GPIO_MODE(MODE) ((MODE == GPIO_Mode_AIN) || (MODE == GPIO_Mode_IN_FLOATING) || \
(MODE == GPIO_Mode_IPD) || (MODE == GPIO_Mode_IPU) || \
(MODE == GPIO_Mode_Out_OD) || (MODE == GPIO_Mode_Out_PP) || \
(MODE == GPIO_Mode_AF_OD) || (MODE == GPIO_Mode_AF_PP))
/* GPIO Init structure definition */
typedef struct
{
u16 GPIO_Pin;
GPIOSpeed_TypeDef GPIO_Speed;
GPIOMode_TypeDef GPIO_Mode;
}GPIO_InitTypeDef;
/* Bit_SET and Bit_RESET enumeration -----------------------------------------*/
typedef enum
{ Bit_RESET = 0,
Bit_SET
}BitAction;
#define IS_GPIO_BIT_ACTION(ACTION) ((ACTION == Bit_RESET) || (ACTION == Bit_SET))
/* Exported constants --------------------------------------------------------*/
/* GPIO pins define ----------------------------------------------------------*/
#define GPIO_Pin_0 ((u16)0x0001) /* Pin 0 selected */
#define GPIO_Pin_1 ((u16)0x0002) /* Pin 1 selected */
#define GPIO_Pin_2 ((u16)0x0004) /* Pin 2 selected */
#define GPIO_Pin_3 ((u16)0x0008) /* Pin 3 selected */
#define GPIO_Pin_4 ((u16)0x0010) /* Pin 4 selected */
#define GPIO_Pin_5 ((u16)0x0020) /* Pin 5 selected */
#define GPIO_Pin_6 ((u16)0x0040) /* Pin 6 selected */
#define GPIO_Pin_7 ((u16)0x0080) /* Pin 7 selected */
#define GPIO_Pin_8 ((u16)0x0100) /* Pin 8 selected */
#define GPIO_Pin_9 ((u16)0x0200) /* Pin 9 selected */
#define GPIO_Pin_10 ((u16)0x0400) /* Pin 10 selected */
#define GPIO_Pin_11 ((u16)0x0800) /* Pin 11 selected */
#define GPIO_Pin_12 ((u16)0x1000) /* Pin 12 selected */
#define GPIO_Pin_13 ((u16)0x2000) /* Pin 13 selected */
#define GPIO_Pin_14 ((u16)0x4000) /* Pin 14 selected */
#define GPIO_Pin_15 ((u16)0x8000) /* Pin 15 selected */
#define GPIO_Pin_All ((u16)0xFFFF) /* All pins selected */
#define IS_GPIO_PIN(PIN) (((PIN & (u16)0x00) == 0x00) && (PIN != (u16)0x00))
/* GPIO Remap define ---------------------------------------------------------*/
#define GPIO_Remap_SPI1 ((u32)0x00000001) /* SPI1 Alternate Function mapping */
#define GPIO_Remap_I2C1 ((u32)0x00000002) /* I2C1 Alternate Function mapping */
#define GPIO_Remap_USART1 ((u32)0x00000004) /* USART1 Alternate Function mapping */
#define GPIO_Remap_USART2 ((u32)0x00000008) /* USART2 Alternate Function mapping */
#define GPIO_PartialRemap_USART3 ((u32)0x00140010) /* USART3 Partial Alternate Function mapping */
#define GPIO_FullRemap_USART3 ((u32)0x00140030) /* USART3 Full Alternate Function mapping */
#define GPIO_PartialRemap_TIM1 ((u32)0x00160040) /* TIM1 Partial Alternate Function mapping */
#define GPIO_FullRemap_TIM1 ((u32)0x001600C0) /* TIM1 Full Alternate Function mapping */
#define GPIO_PartialRemap1_TIM2 ((u32)0x00180100) /* TIM2 Partial1 Alternate Function mapping */
#define GPIO_PartialRemap2_TIM2 ((u32)0x00180200) /* TIM2 Partial2 Alternate Function mapping */
#define GPIO_FullRemap_TIM2 ((u32)0x00180300) /* TIM2 Full Alternate Function mapping */
#define GPIO_PartialRemap_TIM3 ((u32)0x001A0800) /* TIM3 Partial Alternate Function mapping */
#define GPIO_FullRemap_TIM3 ((u32)0x001A0C00) /* TIM3 Full Alternate Function mapping */
#define GPIO_Remap_TIM4 ((u32)0x00001000) /* TIM4 Alternate Function mapping */
#define GPIO_Remap1_CAN ((u32)0x001D2000) /* CAN Alternate Function mapping */
#define GPIO_Remap2_CAN ((u32)0x001D6000) /* CAN Alternate Function mapping */
#define GPIO_Remap_PD01 ((u32)0x00008000) /* PD01 Alternate Function mapping */
#define GPIO_Remap_SWJ_NoJTRST ((u32)0x00300100) /* Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
#define GPIO_Remap_SWJ_JTAGDisable ((u32)0x00300200) /* JTAG-DP Disabled and SW-DP Enabled */
#define GPIO_Remap_SWJ_Disable ((u32)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */
#define IS_GPIO_REMAP(REMAP) ((REMAP == GPIO_Remap_SPI1) || (REMAP == GPIO_Remap_I2C1) || \
(REMAP == GPIO_Remap_USART1) || (REMAP == GPIO_Remap_USART2) || \
(REMAP == GPIO_PartialRemap_USART3) || (REMAP == GPIO_FullRemap_USART3) || \
(REMAP == GPIO_PartialRemap_TIM1) || (REMAP == GPIO_FullRemap_TIM1) || \
(REMAP == GPIO_PartialRemap1_TIM2) || (REMAP == GPIO_PartialRemap2_TIM2) || \
(REMAP == GPIO_FullRemap_TIM2) || (REMAP == GPIO_PartialRemap_TIM3) || \
(REMAP == GPIO_FullRemap_TIM3) || (REMAP == GPIO_Remap_TIM4) || \
(REMAP == GPIO_Remap1_CAN) || (REMAP == GPIO_Remap2_CAN) || \
(REMAP == GPIO_Remap_PD01) || (REMAP == GPIO_Remap_SWJ_NoJTRST) || \
(REMAP == GPIO_Remap_SWJ_JTAGDisable) || (REMAP == GPIO_Remap_SWJ_Disable))
/* GPIO Port Sources ---------------------------------------------------------*/
#define GPIO_PortSourceGPIOA ((u8)0x00)
#define GPIO_PortSourceGPIOB ((u8)0x01)
#define GPIO_PortSourceGPIOC ((u8)0x02)
#define GPIO_PortSourceGPIOD ((u8)0x03)
#define GPIO_PortSourceGPIOE ((u8)0x04)
#define IS_GPIO_PORT_SOURCE(PORTSOURCE) ((PORTSOURCE == GPIO_PortSourceGPIOA) || \
(PORTSOURCE == GPIO_PortSourceGPIOB) || \
(PORTSOURCE == GPIO_PortSourceGPIOC) || \
(PORTSOURCE == GPIO_PortSourceGPIOD) || \
(PORTSOURCE == GPIO_PortSourceGPIOE))
/* GPIO Pin sources ----------------------------------------------------------*/
#define GPIO_PinSource0 ((u8)0x00)
#define GPIO_PinSource1 ((u8)0x01)
#define GPIO_PinSource2 ((u8)0x02)
#define GPIO_PinSource3 ((u8)0x03)
#define GPIO_PinSource4 ((u8)0x04)
#define GPIO_PinSource5 ((u8)0x05)
#define GPIO_PinSource6 ((u8)0x06)
#define GPIO_PinSource7 ((u8)0x07)
#define GPIO_PinSource8 ((u8)0x08)
#define GPIO_PinSource9 ((u8)0x09)
#define GPIO_PinSource10 ((u8)0x0A)
#define GPIO_PinSource11 ((u8)0x0B)
#define GPIO_PinSource12 ((u8)0x0C)
#define GPIO_PinSource13 ((u8)0x0D)
#define GPIO_PinSource14 ((u8)0x0E)
#define GPIO_PinSource15 ((u8)0x0F)
#define IS_GPIO_PIN_SOURCE(PINSOURCE) ((PINSOURCE == GPIO_PinSource0) || \
(PINSOURCE == GPIO_PinSource1) || \
(PINSOURCE == GPIO_PinSource2) || \
(PINSOURCE == GPIO_PinSource3) || \
(PINSOURCE == GPIO_PinSource4) || \
(PINSOURCE == GPIO_PinSource5) || \
(PINSOURCE == GPIO_PinSource6) || \
(PINSOURCE == GPIO_PinSource7) || \
(PINSOURCE == GPIO_PinSource8) || \
(PINSOURCE == GPIO_PinSource9) || \
(PINSOURCE == GPIO_PinSource10) || \
(PINSOURCE == GPIO_PinSource11) || \
(PINSOURCE == GPIO_PinSource12) || \
(PINSOURCE == GPIO_PinSource13) || \
(PINSOURCE == GPIO_PinSource14) || \
(PINSOURCE == GPIO_PinSource15))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
void GPIO_AFIODeInit(void);
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
u8 GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);
u16 GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
u8 GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);
u16 GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin, BitAction BitVal);
void GPIO_Write(GPIO_TypeDef* GPIOx, u16 PortVal);
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);
void GPIO_EventOutputConfig(u8 GPIO_PortSource, u8 GPIO_PinSource);
void GPIO_EventOutputCmd(FunctionalState NewState);
void GPIO_PinRemapConfig(u32 GPIO_Remap, FunctionalState NewState);
void GPIO_EXTILineConfig(u8 GPIO_PortSource, u8 GPIO_PinSource);
#endif /* __STM32F10x_GPIO_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_gpio.h | C | oos | 11,530 |
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32fxxx_eth_lib.h
* Author : MCD Application Team
* Version : V2.0.2
* Date : 07/11/2008
* Description : This file includes the peripherals header files in the
* user application.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32FXXX_ETH_LIB_H
#define __STM32FXXX_ETH_LIB_H
/* Includes ------------------------------------------------------------------*/
#include "stm32fxxx_eth_map.h"
#ifdef _ETH_MAC
//RP_Modif
#include "ipport.h"
#include "netbuf.h"
#include "stm32fxxx_eth.h"
#endif /*_ETH_MAC */
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void eth_debug(void);
#endif /* __STM32FXXX_ETH_LIB_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth_lib.h | C | oos | 1,850 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_it.h
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file contains the headers of the interrupt handlers.
********************************************************************************
* History:
* mm/dd/yyyy: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_IT_H
#define __STM32F10x_IT_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_lib.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void NMIException(void);
void HardFaultException(void);
void MemManageException(void);
void BusFaultException(void);
void UsageFaultException(void);
void DebugMonitor(void);
void SVCHandler(void);
void PendSVC(void);
void SysTickHandler(void);
void WWDG_IRQHandler(void);
void PVD_IRQHandler(void);
void TAMPER_IRQHandler(void);
void RTC_IRQHandler(void);
void FLASH_IRQHandler(void);
void RCC_IRQHandler(void);
void EXTI0_IRQHandler(void);
void EXTI1_IRQHandler(void);
void EXTI2_IRQHandler(void);
void EXTI3_IRQHandler(void);
void EXTI4_IRQHandler(void);
void DMAChannel1_IRQHandler(void);
void DMAChannel2_IRQHandler(void);
void DMAChannel3_IRQHandler(void);
void DMAChannel4_IRQHandler(void);
void DMAChannel5_IRQHandler(void);
void DMAChannel6_IRQHandler(void);
void DMAChannel7_IRQHandler(void);
void ADC_IRQHandler(void);
void USB_HP_CAN_TX_IRQHandler(void);
void USB_LP_CAN_RX0_IRQHandler(void);
void CAN_RX1_IRQHandler(void);
void CAN_SCE_IRQHandler(void);
void EXTI9_5_IRQHandler(void);
void TIM1_BRK_IRQHandler(void);
void TIM1_UP_IRQHandler(void);
void TIM1_TRG_COM_IRQHandler(void);
void TIM1_CC_IRQHandler(void);
void TIM2_IRQHandler(void);
void TIM3_IRQHandler(void);
void TIM4_IRQHandler(void);
void I2C1_EV_IRQHandler(void);
void I2C1_ER_IRQHandler(void);
void I2C2_EV_IRQHandler(void);
void I2C2_ER_IRQHandler(void);
void SPI1_IRQHandler(void);
void SPI2_IRQHandler(void);
void USART1_IRQHandler(void);
void USART2_IRQHandler(void);
void USART3_IRQHandler(void);
void EXTI15_10_IRQHandler(void);
void RTCAlarm_IRQHandler(void);
void USBWakeUp_IRQHandler(void);
#endif /* __STM32F10x_IT_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_it.h | C | oos | 3,378 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_map.h
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file contains all the peripheral register's definitions
* and memory mapping.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_MAP_H
#define __STM32F10x_MAP_H
#ifndef EXT
#define EXT extern
#endif /* EXT */
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_conf.h"
#include "stm32f10x_type.h"
#include "cortexm3_macro.h"
/* Exported types ------------------------------------------------------------*/
/******************************************************************************/
/* IP registers structures */
/******************************************************************************/
/*------------------------ Analog to Digital Converter -----------------------*/
typedef struct
{
vu32 SR;
vu32 CR1;
vu32 CR2;
vu32 SMPR1;
vu32 SMPR2;
vu32 JOFR1;
vu32 JOFR2;
vu32 JOFR3;
vu32 JOFR4;
vu32 HTR;
vu32 LTR;
vu32 SQR1;
vu32 SQR2;
vu32 SQR3;
vu32 JSQR;
vu32 JDR1;
vu32 JDR2;
vu32 JDR3;
vu32 JDR4;
vu32 DR;
} ADC_TypeDef;
/*------------------------ Backup Registers ----------------------------------*/
typedef struct
{
u32 RESERVED0;
vu16 DR1;
u16 RESERVED1;
vu16 DR2;
u16 RESERVED2;
vu16 DR3;
u16 RESERVED3;
vu16 DR4;
u16 RESERVED4;
vu16 DR5;
u16 RESERVED5;
vu16 DR6;
u16 RESERVED6;
vu16 DR7;
u16 RESERVED7;
vu16 DR8;
u16 RESERVED8;
vu16 DR9;
u16 RESERVED9;
vu16 DR10;
u16 RESERVED10;
vu16 RTCCR;
u16 RESERVED11;
vu16 CR;
u16 RESERVED12;
vu16 CSR;
u16 RESERVED13;
} BKP_TypeDef;
/*------------------------ Controller Area Network ---------------------------*/
typedef struct
{
vu32 TIR;
vu32 TDTR;
vu32 TDLR;
vu32 TDHR;
} CAN_TxMailBox_TypeDef;
typedef struct
{
vu32 RIR;
vu32 RDTR;
vu32 RDLR;
vu32 RDHR;
} CAN_FIFOMailBox_TypeDef;
typedef struct
{
vu32 FR0;
vu32 FR1;
} CAN_FilterRegister_TypeDef;
typedef struct
{
vu32 MCR;
vu32 MSR;
vu32 TSR;
vu32 RF0R;
vu32 RF1R;
vu32 IER;
vu32 ESR;
vu32 BTR;
u32 RESERVED0[88];
CAN_TxMailBox_TypeDef sTxMailBox[3];
CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
u32 RESERVED1[12];
vu32 FMR;
vu32 FM0R;
u32 RESERVED2[1];
vu32 FS0R;
u32 RESERVED3[1];
vu32 FFA0R;
u32 RESERVED4[1];
vu32 FA0R;
u32 RESERVED5[8];
CAN_FilterRegister_TypeDef sFilterRegister[14];
} CAN_TypeDef;
/*------------------------ DMA Controller ------------------------------------*/
typedef struct
{
vu32 CCR;
vu32 CNDTR;
vu32 CPAR;
vu32 CMAR;
} DMA_Channel_TypeDef;
typedef struct
{
vu32 ISR;
vu32 IFCR;
} DMA_TypeDef;
/*------------------------ External Interrupt/Event Controller ---------------*/
typedef struct
{
vu32 IMR;
vu32 EMR;
vu32 RTSR;
vu32 FTSR;
vu32 SWIER;
vu32 PR;
} EXTI_TypeDef;
/*------------------------ FLASH and Option Bytes Registers ------------------*/
typedef struct
{
vu32 ACR;
vu32 KEYR;
vu32 OPTKEYR;
vu32 SR;
vu32 CR;
vu32 AR;
vu32 RESERVED;
vu32 OBR;
vu32 WRPR;
} FLASH_TypeDef;
typedef struct
{
vu16 RDP;
vu16 USER;
vu16 Data0;
vu16 Data1;
vu16 WRP0;
vu16 WRP1;
vu16 WRP2;
vu16 WRP3;
} OB_TypeDef;
/*------------------------ General Purpose and Alternate Function IO ---------*/
typedef struct
{
vu32 CRL;
vu32 CRH;
vu32 IDR;
vu32 ODR;
vu32 BSRR;
vu32 BRR;
vu32 LCKR;
} GPIO_TypeDef;
typedef struct
{
vu32 EVCR;
vu32 MAPR;
vu32 EXTICR[4];
} AFIO_TypeDef;
/*------------------------ Inter-integrated Circuit Interface ----------------*/
typedef struct
{
vu16 CR1;
u16 RESERVED0;
vu16 CR2;
u16 RESERVED1;
vu16 OAR1;
u16 RESERVED2;
vu16 OAR2;
u16 RESERVED3;
vu16 DR;
u16 RESERVED4;
vu16 SR1;
u16 RESERVED5;
vu16 SR2;
u16 RESERVED6;
vu16 CCR;
u16 RESERVED7;
vu16 TRISE;
u16 RESERVED8;
} I2C_TypeDef;
/*------------------------ Independent WATCHDOG ------------------------------*/
typedef struct
{
vu32 KR;
vu32 PR;
vu32 RLR;
vu32 SR;
} IWDG_TypeDef;
/*------------------------ Nested Vectored Interrupt Controller --------------*/
typedef struct
{
vu32 Enable[2];
u32 RESERVED0[30];
vu32 Disable[2];
u32 RSERVED1[30];
vu32 Set[2];
u32 RESERVED2[30];
vu32 Clear[2];
u32 RESERVED3[30];
vu32 Active[2];
u32 RESERVED4[62];
vu32 Priority[11];
} NVIC_TypeDef;
typedef struct
{
vu32 CPUID;
vu32 IRQControlState;
vu32 ExceptionTableOffset;
vu32 AIRC;
vu32 SysCtrl;
vu32 ConfigCtrl;
vu32 SystemPriority[3];
vu32 SysHandlerCtrl;
vu32 ConfigFaultStatus;
vu32 HardFaultStatus;
vu32 DebugFaultStatus;
vu32 MemoryManageFaultAddr;
vu32 BusFaultAddr;
} SCB_TypeDef;
/*------------------------ Power Controller ----------------------------------*/
typedef struct
{
vu32 CR;
vu32 CSR;
} PWR_TypeDef;
/*------------------------ Reset and Clock Controller ------------------------*/
typedef struct
{
vu32 CR;
vu32 CFGR;
vu32 CIR;
vu32 APB2RSTR;
vu32 APB1RSTR;
vu32 AHBENR;
vu32 APB2ENR;
vu32 APB1ENR;
vu32 BDCR;
vu32 CSR;
} RCC_TypeDef;
/*------------------------ Real-Time Clock -----------------------------------*/
typedef struct
{
vu16 CRH;
u16 RESERVED0;
vu16 CRL;
u16 RESERVED1;
vu16 PRLH;
u16 RESERVED2;
vu16 PRLL;
u16 RESERVED3;
vu16 DIVH;
u16 RESERVED4;
vu16 DIVL;
u16 RESERVED5;
vu16 CNTH;
u16 RESERVED6;
vu16 CNTL;
u16 RESERVED7;
vu16 ALRH;
u16 RESERVED8;
vu16 ALRL;
u16 RESERVED9;
} RTC_TypeDef;
/*------------------------ Serial Peripheral Interface -----------------------*/
typedef struct
{
vu16 CR1;
u16 RESERVED0;
vu16 CR2;
u16 RESERVED1;
vu16 SR;
u16 RESERVED2;
vu16 DR;
u16 RESERVED3;
vu16 CRCPR;
u16 RESERVED4;
vu16 RXCRCR;
u16 RESERVED5;
vu16 TXCRCR;
u16 RESERVED6;
vu16 I2SCFGR;
u16 RESERVED7;
vu16 I2SPR;
u16 RESERVED8;
} SPI_TypeDef;
/*------------------------ SystemTick ----------------------------------------*/
typedef struct
{
vu32 CTRL;
vu32 LOAD;
vu32 VAL;
vuc32 CALIB;
} SysTick_TypeDef;
/*------------------------ Advanced Control Timer ----------------------------*/
typedef struct
{
vu16 CR1;
u16 RESERVED0;
vu16 CR2;
u16 RESERVED1;
vu16 SMCR;
u16 RESERVED2;
vu16 DIER;
u16 RESERVED3;
vu16 SR;
u16 RESERVED4;
vu16 EGR;
u16 RESERVED5;
vu16 CCMR1;
u16 RESERVED6;
vu16 CCMR2;
u16 RESERVED7;
vu16 CCER;
u16 RESERVED8;
vu16 CNT;
u16 RESERVED9;
vu16 PSC;
u16 RESERVED10;
vu16 ARR;
u16 RESERVED11;
vu16 RCR;
u16 RESERVED12;
vu16 CCR1;
u16 RESERVED13;
vu16 CCR2;
u16 RESERVED14;
vu16 CCR3;
u16 RESERVED15;
vu16 CCR4;
u16 RESERVED16;
vu16 BDTR;
u16 RESERVED17;
vu16 DCR;
u16 RESERVED18;
vu16 DMAR;
u16 RESERVED19;
} TIM1_TypeDef;
/*------------------------ General Purpose Timer -----------------------------*/
typedef struct
{
vu16 CR1;
u16 RESERVED0;
vu16 CR2;
u16 RESERVED1;
vu16 SMCR;
u16 RESERVED2;
vu16 DIER;
u16 RESERVED3;
vu16 SR;
u16 RESERVED4;
vu16 EGR;
u16 RESERVED5;
vu16 CCMR1;
u16 RESERVED6;
vu16 CCMR2;
u16 RESERVED7;
vu16 CCER;
u16 RESERVED8;
vu16 CNT;
u16 RESERVED9;
vu16 PSC;
u16 RESERVED10;
vu16 ARR;
u16 RESERVED11[3];
vu16 CCR1;
u16 RESERVED12;
vu16 CCR2;
u16 RESERVED13;
vu16 CCR3;
u16 RESERVED14;
vu16 CCR4;
u16 RESERVED15[3];
vu16 DCR;
u16 RESERVED16;
vu16 DMAR;
u16 RESERVED17;
} TIM_TypeDef;
/*----------------- Universal Synchronous Asynchronous Receiver Transmitter --*/
typedef struct
{
vu16 SR;
u16 RESERVED0;
vu16 DR;
u16 RESERVED1;
vu16 BRR;
u16 RESERVED2;
vu16 CR1;
u16 RESERVED3;
vu16 CR2;
u16 RESERVED4;
vu16 CR3;
u16 RESERVED5;
vu16 GTPR;
u16 RESERVED6;
} USART_TypeDef;
/*------------------------ Window WATCHDOG -----------------------------------*/
typedef struct
{
vu32 CR;
vu32 CFR;
vu32 SR;
} WWDG_TypeDef;
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
/* Peripheral and SRAM base address in the alias region */
#define PERIPH_BB_BASE ((u32)0x42000000)
#define SRAM_BB_BASE ((u32)0x22000000)
/* Peripheral and SRAM base address in the bit-band region */
#define SRAM_BASE ((u32)0x20000000)
#define PERIPH_BASE ((u32)0x40000000)
/* Flash refisters base address */
#define FLASH_BASE ((u32)0x40022000)
/* Flash Option Bytes base address */
#define OB_BASE ((u32)0x1FFFF800)
/* Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
#define CAN_BASE (APB1PERIPH_BASE + 0x6400)
#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
#define DMA_BASE (AHBPERIPH_BASE + 0x0000)
#define DMA_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
#define DMA_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
#define DMA_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
#define DMA_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
#define DMA_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
#define DMA_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
#define DMA_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
/* System Control Space memory map */
#define SCS_BASE ((u32)0xE000E000)
#define SysTick_BASE (SCS_BASE + 0x0010)
#define NVIC_BASE (SCS_BASE + 0x0100)
#define SCB_BASE (SCS_BASE + 0x0D00)
/******************************************************************************/
/* IPs' declaration */
/******************************************************************************/
/*------------------- Non Debug Mode -----------------------------------------*/
#ifndef DEBUG
#ifdef _TIM2
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
#endif /*_TIM2 */
#ifdef _TIM3
#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
#endif /*_TIM3 */
#ifdef _TIM4
#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
#endif /*_TIM4 */
#ifdef _RTC
#define RTC ((RTC_TypeDef *) RTC_BASE)
#endif /*_RTC */
#ifdef _WWDG
#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
#endif /*_WWDG */
#ifdef _IWDG
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
#endif /*_IWDG */
#ifdef _SPI2
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
#endif /*_SPI2 */
#ifdef _USART2
#define USART2 ((USART_TypeDef *) USART2_BASE)
#endif /*_USART2 */
#ifdef _USART3
#define USART3 ((USART_TypeDef *) USART3_BASE)
#endif /*_USART3 */
#ifdef _I2C1
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#endif /*_I2C1 */
#ifdef _I2C2
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
#endif /*_I2C2 */
#ifdef _CAN
#define CAN ((CAN_TypeDef *) CAN_BASE)
#endif /*_CAN */
#ifdef _BKP
#define BKP ((BKP_TypeDef *) BKP_BASE)
#endif /*_BKP */
#ifdef _PWR
#define PWR ((PWR_TypeDef *) PWR_BASE)
#endif /*_PWR */
#ifdef _AFIO
#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
#endif /*_AFIO */
#ifdef _EXTI
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#endif /*_EXTI */
#ifdef _GPIOA
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#endif /*_GPIOA */
#ifdef _GPIOB
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#endif /*_GPIOB */
#ifdef _GPIOC
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#endif /*_GPIOC */
#ifdef _GPIOD
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#endif /*_GPIOD */
#ifdef _GPIOE
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#endif /*_GPIOE */
#ifdef _ADC1
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#endif /*_ADC1 */
#ifdef _ADC2
#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
#endif /*_ADC2 */
#ifdef _TIM1
#define TIM1 ((TIM1_TypeDef *) TIM1_BASE)
#endif /*_TIM1 */
#ifdef _SPI1
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#endif /*_SPI1 */
#ifdef _USART1
#define USART1 ((USART_TypeDef *) USART1_BASE)
#endif /*_USART1 */
#ifdef _DMA
#define DMA ((DMA_TypeDef *) DMA_BASE)
#endif /*_DMA */
#ifdef _DMA_Channel1
#define DMA_Channel1 ((DMA_Channel_TypeDef *) DMA_Channel1_BASE)
#endif /*_DMA_Channel1 */
#ifdef _DMA_Channel2
#define DMA_Channel2 ((DMA_Channel_TypeDef *) DMA_Channel2_BASE)
#endif /*_DMA_Channel2 */
#ifdef _DMA_Channel3
#define DMA_Channel3 ((DMA_Channel_TypeDef *) DMA_Channel3_BASE)
#endif /*_DMA_Channel3 */
#ifdef _DMA_Channel4
#define DMA_Channel4 ((DMA_Channel_TypeDef *) DMA_Channel4_BASE)
#endif /*_DMA_Channel4 */
#ifdef _DMA_Channel5
#define DMA_Channel5 ((DMA_Channel_TypeDef *) DMA_Channel5_BASE)
#endif /*_DMA_Channel5 */
#ifdef _DMA_Channel6
#define DMA_Channel6 ((DMA_Channel_TypeDef *) DMA_Channel6_BASE)
#endif /*_DMA_Channel6 */
#ifdef _DMA_Channel7
#define DMA_Channel7 ((DMA_Channel_TypeDef *) DMA_Channel7_BASE)
#endif /*_DMA_Channel7 */
#ifdef _FLASH
#define FLASH ((FLASH_TypeDef *) FLASH_BASE)
#define OB ((OB_TypeDef *) OB_BASE)
#endif /*_FLASH */
#ifdef _RCC
#define RCC ((RCC_TypeDef *) RCC_BASE)
#endif /*_RCC */
#ifdef _SysTick
#define SysTick ((SysTick_TypeDef *) SysTick_BASE)
#endif /*_SysTick */
#ifdef _NVIC
#define NVIC ((NVIC_TypeDef *) NVIC_BASE)
#endif /*_NVIC */
#ifdef _SCB
#define SCB ((SCB_TypeDef *) SCB_BASE)
#endif /*_SCB */
/*---------------------- Debug Mode -----------------------------------------*/
#else /* DEBUG */
#ifdef _TIM2
EXT TIM_TypeDef *TIM2;
#endif /*_TIM2 */
#ifdef _TIM3
EXT TIM_TypeDef *TIM3;
#endif /*_TIM3 */
#ifdef _TIM4
EXT TIM_TypeDef *TIM4;
#endif /*_TIM4 */
#ifdef _RTC
EXT RTC_TypeDef *RTC;
#endif /*_RTC */
#ifdef _WWDG
EXT WWDG_TypeDef *WWDG;
#endif /*_WWDG */
#ifdef _IWDG
EXT IWDG_TypeDef *IWDG;
#endif /*_IWDG */
#ifdef _SPI2
EXT SPI_TypeDef *SPI2;
#endif /*_SPI2 */
#ifdef _USART2
EXT USART_TypeDef *USART2;
#endif /*_USART2 */
#ifdef _USART3
EXT USART_TypeDef *USART3;
#endif /*_USART3 */
#ifdef _I2C1
EXT I2C_TypeDef *I2C1;
#endif /*_I2C1 */
#ifdef _I2C2
EXT I2C_TypeDef *I2C2;
#endif /*_I2C2 */
#ifdef _CAN
EXT CAN_TypeDef *CAN;
#endif /*_CAN */
#ifdef _BKP
EXT BKP_TypeDef *BKP;
#endif /*_BKP */
#ifdef _PWR
EXT PWR_TypeDef *PWR;
#endif /*_PWR */
#ifdef _AFIO
EXT AFIO_TypeDef *AFIO;
#endif /*_AFIO */
#ifdef _EXTI
EXT EXTI_TypeDef *EXTI;
#endif /*_EXTI */
#ifdef _GPIOA
EXT GPIO_TypeDef *GPIOA;
#endif /*_GPIOA */
#ifdef _GPIOB
EXT GPIO_TypeDef *GPIOB;
#endif /*_GPIOB */
#ifdef _GPIOC
EXT GPIO_TypeDef *GPIOC;
#endif /*_GPIOC */
#ifdef _GPIOD
EXT GPIO_TypeDef *GPIOD;
#endif /*_GPIOD */
#ifdef _GPIOE
EXT GPIO_TypeDef *GPIOE;
#endif /*_GPIOE */
#ifdef _ADC1
EXT ADC_TypeDef *ADC1;
#endif /*_ADC1 */
#ifdef _ADC2
EXT ADC_TypeDef *ADC2;
#endif /*_ADC2 */
#ifdef _TIM1
EXT TIM1_TypeDef *TIM1;
#endif /*_TIM1 */
#ifdef _SPI1
EXT SPI_TypeDef *SPI1;
#endif /*_SPI1 */
#ifdef _USART1
EXT USART_TypeDef *USART1;
#endif /*_USART1 */
#ifdef _DMA
EXT DMA_TypeDef *DMA;
#endif /*_DMA */
#ifdef _DMA_Channel1
EXT DMA_Channel_TypeDef *DMA_Channel1;
#endif /*_DMA_Channel1 */
#ifdef _DMA_Channel2
EXT DMA_Channel_TypeDef *DMA_Channel2;
#endif /*_DMA_Channel2 */
#ifdef _DMA_Channel3
EXT DMA_Channel_TypeDef *DMA_Channel3;
#endif /*_DMA_Channel3 */
#ifdef _DMA_Channel4
EXT DMA_Channel_TypeDef *DMA_Channel4;
#endif /*_DMA_Channel4 */
#ifdef _DMA_Channel5
EXT DMA_Channel_TypeDef *DMA_Channel5;
#endif /*_DMA_Channel5 */
#ifdef _DMA_Channel6
EXT DMA_Channel_TypeDef *DMA_Channel6;
#endif /*_DMA_Channel6 */
#ifdef _DMA_Channel7
EXT DMA_Channel_TypeDef *DMA_Channel7;
#endif /*_DMA_Channel7 */
#ifdef _FLASH
EXT FLASH_TypeDef *FLASH;
EXT OB_TypeDef *OB;
#endif /*_FLASH */
#ifdef _RCC
EXT RCC_TypeDef *RCC;
#endif /*_RCC */
#ifdef _SysTick
EXT SysTick_TypeDef *SysTick;
#endif /*_SysTick */
#ifdef _NVIC
EXT NVIC_TypeDef *NVIC;
#endif /*_NVIC */
#ifdef _SCB
EXT SCB_TypeDef *SCB;
#endif /*_SCB */
#endif /* DEBUG */
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
#endif /* __STM32F10x_MAP_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_map.h | C | oos | 20,592 |
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32fxxx_eth.h
* Author : MCD Application Team
* Version : V0.0.1
* Date : 12/17/2008
* Desciption : This file contains all the functions prototypes for the
* ETHERNET firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32FXXX_ETH_H
#define __STM32FXXX_ETH_H
/* Includes ------------------------------------------------------------------*/
#include "stm32fxxx_eth_map.h"
/* Exported types ------------------------------------------------------------*/
/* ETHERNET MAC Init structure definition */
typedef struct {
/* MAC ----------------------------------*/
u32 ETH_AutoNegotiation; /* Selects or not the AutoNegotiation with the external PHY */
u32 ETH_Watchdog; /* Enable/disable Watchdog timer */
u32 ETH_Jabber; /* Enable/disable Jabber timer */
u32 ETH_JumboFrame; /* Enable/disable Jumbo frame */
u32 ETH_InterFrameGap; /* Selects minimum IFG between frames during transmission */
u32 ETH_CarrierSense; /* Enable/disable Carrier Sense */
u32 ETH_Speed; /* Indicates the Ethernet speed: 10/100 Mbps */
u32 ETH_ReceiveOwn; /* Enable/disable the reception of frames when the TX_EN signal is asserted in Half-Duplex mode */
u32 ETH_LoopbackMode; /* Enable/disable internal MAC MII Loopback mode */
u32 ETH_Mode; /* Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode */
u32 ETH_ChecksumOffload; /* Enable/disable the calculation of complement sum of all received Ethernet frame payloads */
u32 ETH_RetryTransmission; /* Enable/disable the MAC attempt retries transmission, based on the settings of BL, when a colision occurs (Half-Duplex mode) */
u32 ETH_AutomaticPadCRCStrip; /* Enable/disable Automatic MAC Pad/CRC Stripping */
u32 ETH_BackOffLimit; /* Selects the BackOff limit value */
u32 ETH_DeferralCheck; /* Enable/disable deferral check function (Half-Duplex mode) */
u32 ETH_ReceiveAll; /* Enable/disable all frames reception by the MAC (No fitering)*/
u32 ETH_SourceAddrFilter; /* Selects EnableNormal/EnableInverse/disable Source Address Filter comparison */
u32 ETH_PassControlFrames; /* Selects None/All/FilterPass of all control frames (including unicast and multicast PAUSE frames) */
u32 ETH_BroadcastFramesReception; /* Enable/disable reception of Broadcast Frames */
u32 ETH_DestinationAddrFilter; /* Selects EnableNormal/EnableInverse destination filter for both unicast and multicast frames */
u32 ETH_PromiscuousMode; /* Enable/disable Promiscuous Mode */
u32 ETH_MulticastFramesFilter; /* Selects the Multicast Frames filter: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter */
u32 ETH_UnicastFramesFilter; /* Selects the Unicast Frames filter: HashTableFilter/PerfectFilter/PerfectHashTableFilter */
u32 ETH_HashTableHigh; /* This field contains the higher 32 bits of Hash table. */
u32 ETH_HashTableLow; /* This field contains the lower 32 bits of Hash table. */
u32 ETH_PauseTime; /* This field holds the value to be used in the Pause Time field in the transmit control frame */
u32 ETH_ZeroQuantaPause; /* Enable/disable the automatic generation of Zero-Quanta Pause Control frames */
u32 ETH_PauseLowThreshold; /* This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Frame */
u32 ETH_UnicastPauseFrameDetect; /* Enable/disable MAC to detect the Pause frames (with MAC Address0 unicast address and unique multicast address) */
u32 ETH_ReceiveFlowControl; /* Enable/disable the MAC to decode the received Pause frame and disable its transmitter for a specified (Pause Time) time */
u32 ETH_TransmitFlowControl; /* Enable/disable the MAC to transmit Pause frames (Full-Duplex mode) or the MAC back-pressure operation (Half-Duplex mode) */
u32 ETH_VLANTagComparison; /* Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for comparison and filtering */
u32 ETH_VLANTagIdentifier; /* VLAN tag identifier for receive frames */
/* DMA --------------------------*/
u32 ETH_DropTCPIPChecksumErrorFrame; /* Enable/disable Dropping of TCP/IP Checksum Error Frames */
u32 ETH_ReceiveStoreForward; /* Enable/disable Receive store and forward */
u32 ETH_FlushReceivedFrame; /* Enable/disable flushing of received frames */
u32 ETH_TransmitStoreForward; /* Enable/disable Transmit store and forward */
u32 ETH_TransmitThresholdControl; /* Selects the Transmit Threshold Control */
u32 ETH_ForwardErrorFrames; /* Enable/disable forward to DMA of all frames except runt error frames */
u32 ETH_ForwardUndersizedGoodFrames; /* Enable/disable Rx FIFO to forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC) */
u32 ETH_ReceiveThresholdControl; /* Selects the threshold level of the Receive FIFO */
u32 ETH_SecondFrameOperate; /* Enable/disable the DMA process of a second frame of Transmit data even before status for first frame is obtained */
u32 ETH_AddressAlignedBeats; /* Enable/disable Address Aligned Beats */
u32 ETH_FixedBurst; /* Enable/disable the AHB Master interface fixed burst transfers */
u32 ETH_RxDMABurstLength; /* Indicate the maximum number of beats to be transferred in one Rx DMA transaction */
u32 ETH_TxDMABurstLength; /* Indicate the maximum number of beats to be transferred in one Tx DMA transaction */
u32 ETH_DescriptorSkipLength; /* Specifies the number of word to skip between two unchained descriptors (Ring mode) */
u32 ETH_DMAArbitration; /* Selects DMA Tx/Rx arbitration */
}ETH_InitTypeDef;
/*----------------------------------------------------------------------------*/
/* DMA descriptors types */
/*----------------------------------------------------------------------------*/
/* ETHERNET DMA Desciptors data structure definition */
typedef struct {
volatile u32 Status; /* Status */
volatile u32 ControlBufferSize; /* Control and Buffer1, Buffer2 lengths */
volatile u32 Buffer1Addr; /* Buffer1 address pointer */
volatile u32 Buffer2NextDescAddr; /* Buffer2 or next descriptor address pointer */
} ETH_DMADESCTypeDef;
/* Exported constants --------------------------------------------------------*/
/*----------------------------------------------------------------------------*/
/* ETHERNET Frames defines */
/*----------------------------------------------------------------------------*/
/* ENET Buffers setting */
#define ETH_MAX_PACKET_SIZE 1520 /* ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */
#define ETH_HEADER 14 /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
#define ETH_CRC 4 /* Ethernet CRC */
#define ETH_EXTRA 2 /* Extra bytes in some cases */
#define VLAN_TAG 4 /* optional 802.1q VLAN Tag */
#define MIN_ETH_PAYLOAD 46 /* Minimum Ethernet payload size */
#define MAX_ETH_PAYLOAD 1500 /* Maximum Ethernet payload size */
#define JUMBO_FRAME_PAYLOAD 9000 /* Jumbo frame payload size */
/*--------------------------------------------------------*/
/* Ethernet DMA descriptors registers bits definition */
/*--------------------------------------------------------*/
/* DMA Tx Desciptor ---------------------------------------------------------*/
/*-----------------------------------------------------------------------------------------------
TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | |
-----------------------------------------------------------------------------------------------
TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
-----------------------------------------------------------------------------------------------
TDES2 | Buffer1 Address [31:0] |
-----------------------------------------------------------------------------------------------
TDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] |
----------------------------------------------------------------------------------------------*/
/* Bit definition of TDES0 register: DMA Tx descriptor status register */
#define ETH_DMATxDesc_OWN (0x80000000UL) /* OWN bit: descriptor is owned by DMA engine */
#define ETH_DMATxDesc_IC ((u32)0x40000000) /* Interrupt on Completion */
#define ETH_DMATxDesc_LS ((u32)0x20000000) /* Last Segment */
#define ETH_DMATxDesc_FS ((u32)0x10000000) /* First Segment */
#define ETH_DMATxDesc_DC ((u32)0x08000000) /* Disable CRC */
#define ETH_DMATxDesc_DP ((u32)0x04000000) /* Disable Padding */
#define ETH_DMATxDesc_TTSE ((u32)0x02000000) /* Transmit Time Stamp Enable */
#define ETH_DMATxDesc_CIC ((u32)0x00C00000) /* Checksum Insertion Control: 4 cases */
#define ETH_DMATxDesc_CIC_ByPass ((u32)0x00000000) /* Do Nothing: Checksum Engine is bypassed */
#define ETH_DMATxDesc_CIC_IPV4Header ((u32)0x00400000) /* IPV4 header Checksum Insertion */
#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((u32)0x00800000) /* TCP/UDP/ICMP Checksum Insertion calculated over segment only */
#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((u32)0x00C00000) /* TCP/UDP/ICMP Checksum Insertion fully calculated */
#define ETH_DMATxDesc_TER ((u32)0x00200000) /* Transmit End of Ring */
#define ETH_DMATxDesc_TCH ((u32)0x00100000) /* Second Address Chained */
#define ETH_DMATxDesc_TTSS ((u32)0x00020000) /* Tx Time Stamp Status */
#define ETH_DMATxDesc_IHE ((u32)0x00010000) /* IP Header Error */
#define ETH_DMATxDesc_ES ((u32)0x00008000) /* Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
#define ETH_DMATxDesc_JT ((u32)0x00004000) /* Jabber Timeout */
#define ETH_DMATxDesc_FF ((u32)0x00002000) /* Frame Flushed: DMA/MTL flushed the frame due to SW flush */
#define ETH_DMATxDesc_PCE ((u32)0x00001000) /* Payload Checksum Error */
#define ETH_DMATxDesc_LCA ((u32)0x00000800) /* Loss of Carrier: carrier lost during tramsmission */
#define ETH_DMATxDesc_NC ((u32)0x00000400) /* No Carrier: no carrier signal from the tranceiver */
#define ETH_DMATxDesc_LCO ((u32)0x00000200) /* Late Collision: transmission aborted due to collision */
#define ETH_DMATxDesc_EC ((u32)0x00000100) /* Excessive Collision: transmission aborted after 16 collisions */
#define ETH_DMATxDesc_VF ((u32)0x00000080) /* VLAN Frame */
#define ETH_DMATxDesc_CC ((u32)0x00000078) /* Collision Count */
#define ETH_DMATxDesc_ED ((u32)0x00000004) /* Excessive Deferral */
#define ETH_DMATxDesc_UF ((u32)0x00000002) /* Underflow Error: late data arrival from the memory */
#define ETH_DMATxDesc_DB ((u32)0x00000001) /* Deferred Bit */
/* Bit definition of TDES1 register */
#define ETH_DMATxDesc_TBS2 ((u32)0x1FFF0000) /* Transmit Buffer2 Size */
#define ETH_DMATxDesc_TBS1 ((u32)0x00001FFF) /* Transmit Buffer1 Size */
/* Bit definition of TDES2 register */
#define ETH_DMATxDesc_B1AP ((u32)0xFFFFFFFF) /* Buffer1 Address Pointer */
/* Bit definition of TDES3 register */
#define ETH_DMATxDesc_B2AP ((u32)0xFFFFFFFF) /* Buffer2 Address Pointer */
/* DMA Rx descriptor ---------------------------------------------------------*/
/*---------------------------------------------------------------------------------------------------------------------
RDES0 | OWN(31) | Status [30:0] |
---------------------------------------------------------------------------------------------------------------------
RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
---------------------------------------------------------------------------------------------------------------------
RDES2 | Buffer1 Address [31:0] |
---------------------------------------------------------------------------------------------------------------------
RDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] |
--------------------------------------------------------------------------------------------------------------------*/
/* Bit definition of RDES0 register: DMA Rx descriptor status register */
#define ETH_DMARxDesc_OWN ((u32)0x80000000) /* OWN bit: descriptor is owned by DMA engine */
#define ETH_DMARxDesc_AFM ((u32)0x40000000) /* DA Filter Fail for the rx frame */
#define ETH_DMARxDesc_FL ((u32)0x3FFF0000) /* Receive descriptor frame length */
#define ETH_DMARxDesc_ES ((u32)0x00008000) /* Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
#define ETH_DMARxDesc_DE ((u32)0x00004000) /* Desciptor error: no more descriptors for receive frame */
#define ETH_DMARxDesc_SAF ((u32)0x00002000) /* SA Filter Fail for the received frame */
#define ETH_DMARxDesc_LE ((u32)0x00001000) /* Frame size not matching with length field */
#define ETH_DMARxDesc_OE ((u32)0x00000800) /* Overflow Error: Frame was damaged due to buffer overflow */
#define ETH_DMARxDesc_VLAN ((u32)0x00000400) /* VLAN Tag: received frame is a VLAN frame */
#define ETH_DMARxDesc_FS ((u32)0x00000200) /* First descriptor of the frame */
#define ETH_DMARxDesc_LS ((u32)0x00000100) /* Last descriptor of the frame */
#define ETH_DMARxDesc_IPV4HCE ((u32)0x00000080) /* IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error */
#define ETH_DMARxDesc_RxLongFrame ((u32)0x00000080) /* (Giant Frame)Rx - frame is longer than 1518/1522 */
#define ETH_DMARxDesc_LC ((u32)0x00000040) /* Late collision occurred during reception */
#define ETH_DMARxDesc_FT ((u32)0x00000020) /* Frame type - Ethernet, otherwise 802.3 */
#define ETH_DMARxDesc_RWT ((u32)0x00000010) /* Receive Watchdog Timeout: watchdog timer expired during reception */
#define ETH_DMARxDesc_RE ((u32)0x00000008) /* Receive error: error reported by MII interface */
#define ETH_DMARxDesc_DBE ((u32)0x00000004) /* Dribble bit error: frame contains non int multiple of 8 bits */
#define ETH_DMARxDesc_CE ((u32)0x00000002) /* CRC error */
#define ETH_DMARxDesc_MAMPCE ((u32)0x00000001) /* Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
/* Bit definition of RDES1 register */
#define ETH_DMARxDesc_DIC ((u32)0x80000000) /* Disable Interrupt on Completion */
#define ETH_DMARxDesc_RBS2 ((u32)0x1FFF0000) /* Receive Buffer2 Size */
#define ETH_DMARxDesc_RER ((u32)0x00008000) /* Receive End of Ring */
#define ETH_DMARxDesc_RCH ((u32)0x00004000) /* Second Address Chained */
#define ETH_DMARxDesc_RBS1 ((u32)0x00001FFF) /* Receive Buffer1 Size */
/* Bit definition of RDES2 register */
#define ETH_DMARxDesc_B1AP ((u32)0xFFFFFFFF) /* Buffer1 Address Pointer */
/* Bit definition of RDES3 register */
#define ETH_DMARxDesc_B2AP ((u32)0xFFFFFFFF) /* Buffer2 Address Pointer */
/*----------------------------------------------------------------------------*/
/* Desciption of common PHY registers */
/*----------------------------------------------------------------------------*/
/* PHY Read/write Timeouts */
#define PHY_READ_TO ((u32)0x0004FFFF)
#define PHY_WRITE_TO ((u32)0x0004FFFF)
/* PHY Reset Delay */
#define PHY_ResetDelay ((u32)0x000FFFFF)
/* PHY Config Delay */
#define PHY_ConfigDelay ((u32)0x00FFFFFF)
/* PHY Register address */
#define PHY_BCR 0 /* Tranceiver Basic Control Register */
#define PHY_BSR 1 /* Tranceiver Basic Status Register */
/* PHY basic Control register */
#define PHY_Reset ((u16)0x8000) /* PHY Reset */
#define PHY_Loopback ((u16)0x4000) /* Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((u16)0x2100) /* Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M ((u16)0x2000) /* Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M ((u16)0x0100) /* Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((u16)0x0000) /* Set the half-duplex mode at 10 Mb/s */
#define PHY_AutoNegotiation ((u16)0x1000) /* Enable auto-negotiation function */
#define PHY_Restart_AutoNegotiation ((u16)0x0200) /* Restart auto-negotiation function */
#define PHY_Powerdown ((u16)0x0800) /* Select the power down mode */
#define PHY_Isolate ((u16)0x0400) /* Isolate PHY from MII */
/* PHY basic status register */
#define PHY_AutoNego_Complete ((u16)0x0020) /* Auto-Negotioation process completed */
#define PHY_Linked_Status ((u16)0x0004) /* Valid link established */
#define PHY_Jabber_detection ((u16)0x0002) /* Jabber condition detected */
/* The PHY status register value change from a PHY to another so the user have to update
this value depending on the used external PHY */
/* For LAN8700 */
//#define PHY_SR 31 /* Tranceiver Status Register */
/* For DP83848 */
#define PHY_SR 16 /* Tranceiver Status Register */
/* PHY status register */
/* The Speed and Duplex mask values change from a PHY to another so the user have to update
this value depending on the used external PHY */
/* For LAN8700 */
//#define PHY_Speed_Status ((u16)0x0004) /* Configured information of Speed: 10Mbps */
//#define PHY_Duplex_Status ((u16)0x0010) /* Configured information of Duplex: Full-duplex */
/* For DP83848 */
#define PHY_Speed_Status ((u16)0x0002) /* Configured information of Speed: 10Mbps */
#define PHY_Duplex_Status ((u16)0x0004) /* Configured information of Duplex: Full-duplex */
#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
#define IS_ETH_PHY_REG(REG) (((REG) == PHY_BCR) || \
((REG) == PHY_BSR) || \
((REG) == PHY_SR))
/*----------------------------------------------------------------------------*/
/* MAC defines */
/*----------------------------------------------------------------------------*/
/* ETHERNET AutoNegotiation --------------------------------------------------*/
#define ETH_AutoNegotiation_Enable ((u32)0x00000001)
#define ETH_AutoNegotiation_Disable ((u32)0x00000000)
#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AutoNegotiation_Enable) || \
((CMD) == ETH_AutoNegotiation_Disable))
/* ETHERNET watchdog ---------------------------------------------------------*/
#define ETH_Watchdog_Enable ((u32)0x00000000)
#define ETH_Watchdog_Disable ((u32)0x00800000)
#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_Watchdog_Enable) || \
((CMD) == ETH_Watchdog_Disable))
/* ETHERNET Jabber -----------------------------------------------------------*/
#define ETH_Jabber_Enable ((u32)0x00000000)
#define ETH_Jabber_Disable ((u32)0x00400000)
#define IS_ETH_JABBER(CMD) (((CMD) == ETH_Jabber_Enable) || \
((CMD) == ETH_Jabber_Disable))
/* ETHERNET Jumbo Frame ------------------------------------------------------*/
#define ETH_JumboFrame_Enable ((u32)0x00100000)
#define ETH_JumboFrame_Disable ((u32)0x00000000)
#define IS_ETH_JUMBO_FRAME(CMD) (((CMD) == ETH_JumboFrame_Enable) || \
((CMD) == ETH_JumboFrame_Disable))
/* ETHERNET Inter Frame Gap --------------------------------------------------*/
#define ETH_InterFrameGap_96Bit ((u32)0x00000000) /* minimum IFG between frames during transmission is 96Bit */
#define ETH_InterFrameGap_88Bit ((u32)0x00020000) /* minimum IFG between frames during transmission is 88Bit */
#define ETH_InterFrameGap_80Bit ((u32)0x00040000) /* minimum IFG between frames during transmission is 80Bit */
#define ETH_InterFrameGap_72Bit ((u32)0x00060000) /* minimum IFG between frames during transmission is 72Bit */
#define ETH_InterFrameGap_64Bit ((u32)0x00080000) /* minimum IFG between frames during transmission is 64Bit */
#define ETH_InterFrameGap_56Bit ((u32)0x000A0000) /* minimum IFG between frames during transmission is 56Bit */
#define ETH_InterFrameGap_48Bit ((u32)0x000C0000) /* minimum IFG between frames during transmission is 48Bit */
#define ETH_InterFrameGap_40Bit ((u32)0x000E0000) /* minimum IFG between frames during transmission is 40Bit */
#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_InterFrameGap_96Bit) || \
((GAP) == ETH_InterFrameGap_88Bit) || \
((GAP) == ETH_InterFrameGap_80Bit) || \
((GAP) == ETH_InterFrameGap_72Bit) || \
((GAP) == ETH_InterFrameGap_64Bit) || \
((GAP) == ETH_InterFrameGap_56Bit) || \
((GAP) == ETH_InterFrameGap_48Bit) || \
((GAP) == ETH_InterFrameGap_40Bit))
/* ETHERNET Carrier Sense ----------------------------------------------------*/
#define ETH_CarrierSense_Enable ((u32)0x00000000)
#define ETH_CarrierSense_Disable ((u32)0x00010000)
#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CarrierSense_Enable) || \
((CMD) == ETH_CarrierSense_Disable))
/* ETHERNET Speed ------------------------------------------------------------*/
#define ETH_Speed_10M ((u32)0x00000000)
#define ETH_Speed_100M ((u32)0x00004000)
#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_Speed_10M) || \
((SPEED) == ETH_Speed_100M))
/* ETHERNET Receive Own ------------------------------------------------------*/
#define ETH_ReceiveOwn_Enable ((u32)0x00000000)
#define ETH_ReceiveOwn_Disable ((u32)0x00002000)
#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_ReceiveOwn_Enable) || \
((CMD) == ETH_ReceiveOwn_Disable))
/* ETHERNET Loop back Mode ---------------------------------------------------*/
#define ETH_LoopbackMode_Enable ((u32)0x00001000)
#define ETH_LoopbackMode_Disable ((u32)0x00000000)
#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LoopbackMode_Enable) || \
((CMD) == ETH_LoopbackMode_Disable))
/* ETHERNET Duplex mode ------------------------------------------------------*/
#define ETH_Mode_FullDuplex ((u32)0x00000800)
#define ETH_Mode_HalfDuplex ((u32)0x00000000)
#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_Mode_FullDuplex) || \
((MODE) == ETH_Mode_HalfDuplex))
/* ETHERNET Checksum Offload -------------------------------------------------*/
#define ETH_ChecksumOffload_Enable ((u32)0x00000400)
#define ETH_ChecksumOffload_Disable ((u32)0x00000000)
#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_ChecksumOffload_Enable) || \
((CMD) == ETH_ChecksumOffload_Disable))
/* ETHERNET Retry Transmission -----------------------------------------------*/
#define ETH_RetryTransmission_Enable ((u32)0x00000000)
#define ETH_RetryTransmission_Disable ((u32)0x00000200)
#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RetryTransmission_Enable) || \
((CMD) == ETH_RetryTransmission_Disable))
/* ETHERNET Automatic Pad/CRC Strip ------------------------------------------*/
#define ETH_AutomaticPadCRCStrip_Enable ((u32)0x00000080)
#define ETH_AutomaticPadCRCStrip_Disable ((u32)0x00000000)
#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AutomaticPadCRCStrip_Enable) || \
((CMD) == ETH_AutomaticPadCRCStrip_Disable))
/* ETHERNET Back-Off limit ---------------------------------------------------*/
#define ETH_BackOffLimit_10 ((u32)0x00000000)
#define ETH_BackOffLimit_8 ((u32)0x00000020)
#define ETH_BackOffLimit_4 ((u32)0x00000040)
#define ETH_BackOffLimit_1 ((u32)0x00000060)
#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BackOffLimit_10) || \
((LIMIT) == ETH_BackOffLimit_8) || \
((LIMIT) == ETH_BackOffLimit_4) || \
((LIMIT) == ETH_BackOffLimit_1))
/* ETHERNET Deferral Check ---------------------------------------------------*/
#define ETH_DeferralCheck_Enable ((u32)0x00000010)
#define ETH_DeferralCheck_Disable ((u32)0x00000000)
#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DeferralCheck_Enable) || \
((CMD) == ETH_DeferralCheck_Disable))
/* ETHERNET Receive All ------------------------------------------------------*/
#define ETH_ReceiveAll_Enable ((u32)0x80000000)
#define ETH_ReceiveAll_Disable ((u32)0x00000000)
#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_ReceiveAll_Enable) || \
((CMD) == ETH_ReceiveAll_Disable))
/* ETHERNET Source Addr Filter ------------------------------------------------*/
#define ETH_SourceAddrFilter_Normal_Enable ((u32)0x00000200)
#define ETH_SourceAddrFilter_Inverse_Enable ((u32)0x00000300)
#define ETH_SourceAddrFilter_Disable ((u32)0x00000000)
#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SourceAddrFilter_Normal_Enable) || \
((CMD) == ETH_SourceAddrFilter_Inverse_Enable) || \
((CMD) == ETH_SourceAddrFilter_Disable))
/* ETHERNET Pass Control Frames ----------------------------------------------*/
#define ETH_PassControlFrames_BlockAll ((u32)0x00000040) /* MAC filters all control frames from reaching the application */
#define ETH_PassControlFrames_ForwardAll ((u32)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
#define ETH_PassControlFrames_ForwardPassedAddrFilter ((u32)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PassControlFrames_BlockAll) || \
((PASS) == ETH_PassControlFrames_ForwardAll) || \
((PASS) == ETH_PassControlFrames_ForwardPassedAddrFilter))
/* ETHERNET Broadcast Frames Reception ---------------------------------------*/
#define ETH_BroadcastFramesReception_Enable ((u32)0x00000000)
#define ETH_BroadcastFramesReception_Disable ((u32)0x00000020)
#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BroadcastFramesReception_Enable) || \
((CMD) == ETH_BroadcastFramesReception_Disable))
/* ETHERNET Destination Addr Filter ------------------------------------------*/
#define ETH_DestinationAddrFilter_Normal ((u32)0x00000000)
#define ETH_DestinationAddrFilter_Inverse ((u32)0x00000008)
#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DestinationAddrFilter_Normal) || \
((FILTER) == ETH_DestinationAddrFilter_Inverse))
/* ETHERNET Promiscuous Mode -------------------------------------------------*/
#define ETH_PromiscuousMode_Enable ((u32)0x00000001)
#define ETH_PromiscuousMode_Disable ((u32)0x00000000)
#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PromiscuousMode_Enable) || \
((CMD) == ETH_PromiscuousMode_Disable))
/* ETHERNET multicast frames filter --------------------------------------------*/
#define ETH_MulticastFramesFilter_PerfectHashTable ((u32)0x00000404)
#define ETH_MulticastFramesFilter_HashTable ((u32)0x00000004)
#define ETH_MulticastFramesFilter_Perfect ((u32)0x00000000)
#define ETH_MulticastFramesFilter_None ((u32)0x00000010)
#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MulticastFramesFilter_PerfectHashTable) || \
((FILTER) == ETH_MulticastFramesFilter_HashTable) || \
((FILTER) == ETH_MulticastFramesFilter_Perfect) || \
((FILTER) == ETH_MulticastFramesFilter_None))
/* ETHERNET unicast frames filter --------------------------------------------*/
#define ETH_UnicastFramesFilter_PerfectHashTable ((u32)0x00000402)
#define ETH_UnicastFramesFilter_HashTable ((u32)0x00000002)
#define ETH_UnicastFramesFilter_Perfect ((u32)0x00000000)
#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UnicastFramesFilter_PerfectHashTable) || \
((FILTER) == ETH_UnicastFramesFilter_HashTable) || \
((FILTER) == ETH_UnicastFramesFilter_Perfect))
/* ETHERNET Pause Time ------------------------------------------------*/
#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
/* ETHERNET Zero Quanta Pause ------------------------------------------------*/
#define ETH_ZeroQuantaPause_Enable ((u32)0x00000000)
#define ETH_ZeroQuantaPause_Disable ((u32)0x00000080)
#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZeroQuantaPause_Enable) || \
((CMD) == ETH_ZeroQuantaPause_Disable))
/* ETHERNET Pause Low Threshold ----------------------------------------------*/
#define ETH_PauseLowThreshold_Minus4 ((u32)0x00000000) /* Pause time minus 4 slot times */
#define ETH_PauseLowThreshold_Minus28 ((u32)0x00000010) /* Pause time minus 28 slot times */
#define ETH_PauseLowThreshold_Minus144 ((u32)0x00000020) /* Pause time minus 144 slot times */
#define ETH_PauseLowThreshold_Minus256 ((u32)0x00000030) /* Pause time minus 256 slot times */
#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PauseLowThreshold_Minus4) || \
((THRESHOLD) == ETH_PauseLowThreshold_Minus28) || \
((THRESHOLD) == ETH_PauseLowThreshold_Minus144) || \
((THRESHOLD) == ETH_PauseLowThreshold_Minus256))
/* ETHERNET Unicast Pause Frame Detect ---------------------------------------*/
#define ETH_UnicastPauseFrameDetect_Enable ((u32)0x00000008)
#define ETH_UnicastPauseFrameDetect_Disable ((u32)0x00000000)
#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UnicastPauseFrameDetect_Enable) || \
((CMD) == ETH_UnicastPauseFrameDetect_Disable))
/* ETHERNET Receive Flow Control ---------------------------------------------*/
#define ETH_ReceiveFlowControl_Enable ((u32)0x00000004)
#define ETH_ReceiveFlowControl_Disable ((u32)0x00000000)
#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_ReceiveFlowControl_Enable) || \
((CMD) == ETH_ReceiveFlowControl_Disable))
/* ETHERNET Transmit Flow Control --------------------------------------------*/
#define ETH_TransmitFlowControl_Enable ((u32)0x00000002)
#define ETH_TransmitFlowControl_Disable ((u32)0x00000000)
#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TransmitFlowControl_Enable) || \
((CMD) == ETH_TransmitFlowControl_Disable))
/* ETHERNET VLAN Tag Comparison ----------------------------------------------*/
#define ETH_VLANTagComparison_12Bit ((u32)0x00010000)
#define ETH_VLANTagComparison_16Bit ((u32)0x00000000)
#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTagComparison_12Bit) || \
((COMPARISON) == ETH_VLANTagComparison_16Bit))
#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
/* ETHERNET MAC Flags ---------------------------------------------------*/
#define ETH_MAC_FLAG_TST ((u32)0x00000200) /* Time stamp trigger flag (on MAC) */
#define ETH_MAC_FLAG_MMCT ((u32)0x00000040) /* MMC transmit flag */
#define ETH_MAC_FLAG_MMCR ((u32)0x00000020) /* MMC receive flag */
#define ETH_MAC_FLAG_MMC ((u32)0x00000010) /* MMC flag (on MAC) */
#define ETH_MAC_FLAG_PMT ((u32)0x00000008) /* PMT flag (on MAC) */
#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
((FLAG) == ETH_MAC_FLAG_PMT))
/* ETHERNET MAC Interrupts ---------------------------------------------------*/
#define ETH_MAC_IT_TST ((u32)0x00000200) /* Time stamp trigger interrupt (on MAC) */
#define ETH_MAC_IT_MMCT ((u32)0x00000040) /* MMC transmit interrupt */
#define ETH_MAC_IT_MMCR ((u32)0x00000020) /* MMC receive interrupt */
#define ETH_MAC_IT_MMC ((u32)0x00000010) /* MMC interrupt (on MAC) */
#define ETH_MAC_IT_PMT ((u32)0x00000008) /* PMT interrupt (on MAC) */
#define IS_ETH_MAC_IT(IT) ((((IT) & (u32)0xFFFFFDF7) == 0x00) && ((IT) != 0x00))
#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
((IT) == ETH_MAC_IT_PMT))
/* ETHERNET MAC addresses ----------------------------------------------------*/
#define ETH_MAC_Address0 ((u32)0x00000000)
#define ETH_MAC_Address1 ((u32)0x00000008)
#define ETH_MAC_Address2 ((u32)0x00000010)
#define ETH_MAC_Address3 ((u32)0x00000018)
#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_Address0) || \
((ADDRESS) == ETH_MAC_Address1) || \
((ADDRESS) == ETH_MAC_Address2) || \
((ADDRESS) == ETH_MAC_Address3))
#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_Address1) || \
((ADDRESS) == ETH_MAC_Address2) || \
((ADDRESS) == ETH_MAC_Address3))
/* ETHERNET MAC addresses filter: SA/DA filed of received frames ------------*/
#define ETH_MAC_AddressFilter_SA ((u32)0x00000000)
#define ETH_MAC_AddressFilter_DA ((u32)0x00000008)
#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_AddressFilter_SA) || \
((FILTER) == ETH_MAC_AddressFilter_DA))
/* ETHERNET MAC addresses filter: Mask bytes ---------------------------------*/
#define ETH_MAC_AddressMask_Byte6 ((u32)0x20000000) /* Mask MAC Address high reg bits [15:8] */
#define ETH_MAC_AddressMask_Byte5 ((u32)0x10000000) /* Mask MAC Address high reg bits [7:0] */
#define ETH_MAC_AddressMask_Byte4 ((u32)0x08000000) /* Mask MAC Address low reg bits [31:24] */
#define ETH_MAC_AddressMask_Byte3 ((u32)0x04000000) /* Mask MAC Address low reg bits [23:16] */
#define ETH_MAC_AddressMask_Byte2 ((u32)0x02000000) /* Mask MAC Address low reg bits [15:8] */
#define ETH_MAC_AddressMask_Byte1 ((u32)0x01000000) /* Mask MAC Address low reg bits [70] */
#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_AddressMask_Byte6) || \
((MASK) == ETH_MAC_AddressMask_Byte5) || \
((MASK) == ETH_MAC_AddressMask_Byte4) || \
((MASK) == ETH_MAC_AddressMask_Byte3) || \
((MASK) == ETH_MAC_AddressMask_Byte2) || \
((MASK) == ETH_MAC_AddressMask_Byte1))
/*----------------------------------------------------------------------------*/
/* Ethernet DMA Desciptors defines */
/*----------------------------------------------------------------------------*/
/* ETHERNET DMA Tx descriptor flags --------------------------------------------------------*/
#define IS_ETH_DMATxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATxDesc_OWN) || \
((FLAG) == ETH_DMATxDesc_IC) || \
((FLAG) == ETH_DMATxDesc_LS) || \
((FLAG) == ETH_DMATxDesc_FS) || \
((FLAG) == ETH_DMATxDesc_DC) || \
((FLAG) == ETH_DMATxDesc_DP) || \
((FLAG) == ETH_DMATxDesc_TTSE) || \
((FLAG) == ETH_DMATxDesc_TER) || \
((FLAG) == ETH_DMATxDesc_TCH) || \
((FLAG) == ETH_DMATxDesc_TTSS) || \
((FLAG) == ETH_DMATxDesc_IHE) || \
((FLAG) == ETH_DMATxDesc_ES) || \
((FLAG) == ETH_DMATxDesc_JT) || \
((FLAG) == ETH_DMATxDesc_FF) || \
((FLAG) == ETH_DMATxDesc_PCE) || \
((FLAG) == ETH_DMATxDesc_LCA) || \
((FLAG) == ETH_DMATxDesc_NC) || \
((FLAG) == ETH_DMATxDesc_LCO) || \
((FLAG) == ETH_DMATxDesc_EC) || \
((FLAG) == ETH_DMATxDesc_VF) || \
((FLAG) == ETH_DMATxDesc_CC) || \
((FLAG) == ETH_DMATxDesc_ED) || \
((FLAG) == ETH_DMATxDesc_UF) || \
((FLAG) == ETH_DMATxDesc_DB))
/* ETHERNET DMA Tx descriptor segment ----------------------------------------*/
#define ETH_DMATxDesc_LastSegment ((u32)0x40000000) /* Last Segment */
#define ETH_DMATxDesc_FirstSegment ((u32)0x20000000) /* First Segment */
#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATxDesc_LastSegment) || \
((SEGMENT) == ETH_DMATxDesc_FirstSegment))
/* ETHERNET DMA Tx descriptor Checksum Insertion Control --------------------*/
#define ETH_DMATxDesc_ChecksumByPass ((u32)0x00000000) /* Checksum engine bypass */
#define ETH_DMATxDesc_ChecksumIPV4Header ((u32)0x00400000) /* IPv4 header checksum insertion */
#define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment ((u32)0x00800000) /* TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
#define ETH_DMATxDesc_ChecksumTCPUDPICMPFull ((u32)0x00C00000) /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */
#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATxDesc_ChecksumByPass) || \
((CHECKSUM) == ETH_DMATxDesc_ChecksumIPV4Header) || \
((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPSegment) || \
((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPFull))
/* ETHERNET DMA Tx Desciptor buffer size */
#define IS_ETH_DMATxDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
/* ETHERNET DMA Rx descriptor flags --------------------------------------------------------*/
#define IS_ETH_DMARxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARxDesc_OWN) || \
((FLAG) == ETH_DMARxDesc_AFM) || \
((FLAG) == ETH_DMARxDesc_ES) || \
((FLAG) == ETH_DMARxDesc_DE) || \
((FLAG) == ETH_DMARxDesc_SAF) || \
((FLAG) == ETH_DMARxDesc_LE) || \
((FLAG) == ETH_DMARxDesc_OE) || \
((FLAG) == ETH_DMARxDesc_VLAN) || \
((FLAG) == ETH_DMARxDesc_FS) || \
((FLAG) == ETH_DMARxDesc_LS) || \
((FLAG) == ETH_DMARxDesc_IPV4HCE) || \
((FLAG) == ETH_DMARxDesc_RxLongFrame) || \
((FLAG) == ETH_DMARxDesc_LC) || \
((FLAG) == ETH_DMARxDesc_FT) || \
((FLAG) == ETH_DMARxDesc_RWT) || \
((FLAG) == ETH_DMARxDesc_RE) || \
((FLAG) == ETH_DMARxDesc_DBE) || \
((FLAG) == ETH_DMARxDesc_CE) || \
((FLAG) == ETH_DMARxDesc_MAMPCE))
/* ETHERNET DMA Rx descriptor buffers ---------------------------------------*/
#define ETH_DMARxDesc_Buffer1 ((u32)0x00000000) /* DMA Rx Desc Buffer1 */
#define ETH_DMARxDesc_Buffer2 ((u32)0x00000001) /* DMA Rx Desc Buffer2 */
#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARxDesc_Buffer1) || \
((BUFFER) == ETH_DMARxDesc_Buffer2))
/*----------------------------------------------------------------------------*/
/* Ethernet DMA defines */
/*----------------------------------------------------------------------------*/
/* ETHERNET Drop TCP/IP Checksum Error Frame ---------------------------------*/
#define ETH_DropTCPIPChecksumErrorFrame_Enable ((u32)0x00000000)
#define ETH_DropTCPIPChecksumErrorFrame_Disable ((u32)0x04000000)
#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DropTCPIPChecksumErrorFrame_Enable) || \
((CMD) == ETH_DropTCPIPChecksumErrorFrame_Disable))
/* ETHERNET Receive Store Forward --------------------------------------------*/
#define ETH_ReceiveStoreForward_Enable ((u32)0x02000000)
#define ETH_ReceiveStoreForward_Disable ((u32)0x00000000)
#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_ReceiveStoreForward_Enable) || \
((CMD) == ETH_ReceiveStoreForward_Disable))
/* ETHERNET Flush Received Frame ---------------------------------------------*/
#define ETH_FlushReceivedFrame_Enable ((u32)0x00000000)
#define ETH_FlushReceivedFrame_Disable ((u32)0x01000000)
#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FlushReceivedFrame_Enable) || \
((CMD) == ETH_FlushReceivedFrame_Disable))
/* ETHERNET Transmit Store Forward -------------------------------------------*/
#define ETH_TransmitStoreForward_Enable ((u32)0x00200000)
#define ETH_TransmitStoreForward_Disable ((u32)0x00000000)
#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TransmitStoreForward_Enable) || \
((CMD) == ETH_TransmitStoreForward_Disable))
/* ETHERNET Transmit Threshold Control ---------------------------------------*/
#define ETH_TransmitThresholdControl_64Bytes ((u32)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
#define ETH_TransmitThresholdControl_128Bytes ((u32)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
#define ETH_TransmitThresholdControl_192Bytes ((u32)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
#define ETH_TransmitThresholdControl_256Bytes ((u32)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
#define ETH_TransmitThresholdControl_40Bytes ((u32)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
#define ETH_TransmitThresholdControl_32Bytes ((u32)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
#define ETH_TransmitThresholdControl_24Bytes ((u32)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
#define ETH_TransmitThresholdControl_16Bytes ((u32)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TransmitThresholdControl_64Bytes) || \
((THRESHOLD) == ETH_TransmitThresholdControl_128Bytes) || \
((THRESHOLD) == ETH_TransmitThresholdControl_192Bytes) || \
((THRESHOLD) == ETH_TransmitThresholdControl_256Bytes) || \
((THRESHOLD) == ETH_TransmitThresholdControl_40Bytes) || \
((THRESHOLD) == ETH_TransmitThresholdControl_32Bytes) || \
((THRESHOLD) == ETH_TransmitThresholdControl_24Bytes) || \
((THRESHOLD) == ETH_TransmitThresholdControl_16Bytes))
/* ETHERNET Forward Error Frames ---------------------------------------------*/
#define ETH_ForwardErrorFrames_Enable ((u32)0x00000080)
#define ETH_ForwardErrorFrames_Disable ((u32)0x00000000)
#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_ForwardErrorFrames_Enable) || \
((CMD) == ETH_ForwardErrorFrames_Disable))
/* ETHERNET Forward Undersized Good Frames -----------------------------------*/
#define ETH_ForwardUndersizedGoodFrames_Enable ((u32)0x00000040)
#define ETH_ForwardUndersizedGoodFrames_Disable ((u32)0x00000000)
#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_ForwardUndersizedGoodFrames_Enable) || \
((CMD) == ETH_ForwardUndersizedGoodFrames_Disable))
/* ETHERNET Receive Threshold Control ----------------------------------------*/
#define ETH_ReceiveThresholdControl_64Bytes ((u32)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
#define ETH_ReceiveThresholdControl_32Bytes ((u32)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
#define ETH_ReceiveThresholdControl_96Bytes ((u32)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
#define ETH_ReceiveThresholdControl_128Bytes ((u32)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_ReceiveThresholdControl_64Bytes) || \
((THRESHOLD) == ETH_ReceiveThresholdControl_32Bytes) || \
((THRESHOLD) == ETH_ReceiveThresholdControl_96Bytes) || \
((THRESHOLD) == ETH_ReceiveThresholdControl_128Bytes))
/* ETHERNET Second Frame Operate ---------------------------------------------*/
#define ETH_SecondFrameOperate_Enable ((u32)0x00000004)
#define ETH_SecondFrameOperate_Disable ((u32)0x00000000)
#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SecondFrameOperate_Enable) || \
((CMD) == ETH_SecondFrameOperate_Disable))
/* ETHERNET Address Aligned Beats --------------------------------------------*/
#define ETH_AddressAlignedBeats_Enable ((u32)0x02000000)
#define ETH_AddressAlignedBeats_Disable ((u32)0x00000000)
#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_AddressAlignedBeats_Enable) || \
((CMD) == ETH_AddressAlignedBeats_Disable))
/* ETHERNET Fixed Burst ------------------------------------------------------*/
#define ETH_FixedBurst_Enable ((u32)0x00010000)
#define ETH_FixedBurst_Disable ((u32)0x00000000)
#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FixedBurst_Enable) || \
((CMD) == ETH_FixedBurst_Disable))
/* ETHERNET Rx DMA Burst Length ----------------------------------------------*/
#define ETH_RxDMABurstLength_1Beat ((u32)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
#define ETH_RxDMABurstLength_2Beat ((u32)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
#define ETH_RxDMABurstLength_4Beat ((u32)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
#define ETH_RxDMABurstLength_8Beat ((u32)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
#define ETH_RxDMABurstLength_16Beat ((u32)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
#define ETH_RxDMABurstLength_32Beat ((u32)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
#define ETH_RxDMABurstLength_4xPBL_4Beat ((u32)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
#define ETH_RxDMABurstLength_4xPBL_8Beat ((u32)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
#define ETH_RxDMABurstLength_4xPBL_16Beat ((u32)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
#define ETH_RxDMABurstLength_4xPBL_32Beat ((u32)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
#define ETH_RxDMABurstLength_4xPBL_64Beat ((u32)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
#define ETH_RxDMABurstLength_4xPBL_128Beat ((u32)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RxDMABurstLength_1Beat) || \
((LENGTH) == ETH_RxDMABurstLength_2Beat) || \
((LENGTH) == ETH_RxDMABurstLength_4Beat) || \
((LENGTH) == ETH_RxDMABurstLength_8Beat) || \
((LENGTH) == ETH_RxDMABurstLength_16Beat) || \
((LENGTH) == ETH_RxDMABurstLength_32Beat) || \
((LENGTH) == ETH_RxDMABurstLength_4xPBL_4Beat) || \
((LENGTH) == ETH_RxDMABurstLength_4xPBL_8Beat) || \
((LENGTH) == ETH_RxDMABurstLength_4xPBL_16Beat) || \
((LENGTH) == ETH_RxDMABurstLength_4xPBL_32Beat) || \
((LENGTH) == ETH_RxDMABurstLength_4xPBL_64Beat) || \
((LENGTH) == ETH_RxDMABurstLength_4xPBL_128Beat))
/* ETHERNET Tx DMA Burst Length ----------------------------------------------*/
#define ETH_TxDMABurstLength_1Beat ((u32)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
#define ETH_TxDMABurstLength_2Beat ((u32)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
#define ETH_TxDMABurstLength_4Beat ((u32)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
#define ETH_TxDMABurstLength_8Beat ((u32)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
#define ETH_TxDMABurstLength_16Beat ((u32)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
#define ETH_TxDMABurstLength_32Beat ((u32)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
#define ETH_TxDMABurstLength_4xPBL_4Beat ((u32)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
#define ETH_TxDMABurstLength_4xPBL_8Beat ((u32)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
#define ETH_TxDMABurstLength_4xPBL_16Beat ((u32)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
#define ETH_TxDMABurstLength_4xPBL_32Beat ((u32)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
#define ETH_TxDMABurstLength_4xPBL_64Beat ((u32)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
#define ETH_TxDMABurstLength_4xPBL_128Beat ((u32)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TxDMABurstLength_1Beat) || \
((LENGTH) == ETH_TxDMABurstLength_2Beat) || \
((LENGTH) == ETH_TxDMABurstLength_4Beat) || \
((LENGTH) == ETH_TxDMABurstLength_8Beat) || \
((LENGTH) == ETH_TxDMABurstLength_16Beat) || \
((LENGTH) == ETH_TxDMABurstLength_32Beat) || \
((LENGTH) == ETH_TxDMABurstLength_4xPBL_4Beat) || \
((LENGTH) == ETH_TxDMABurstLength_4xPBL_8Beat) || \
((LENGTH) == ETH_TxDMABurstLength_4xPBL_16Beat) || \
((LENGTH) == ETH_TxDMABurstLength_4xPBL_32Beat) || \
((LENGTH) == ETH_TxDMABurstLength_4xPBL_64Beat) || \
((LENGTH) == ETH_TxDMABurstLength_4xPBL_128Beat))
/* ETHERNET DMA Desciptor SkipLength */
#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
/* ETHERNET DMA Arbitration --------------------------------------------------*/
#define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((u32)0x00000000)
#define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((u32)0x00004000)
#define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((u32)0x00008000)
#define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((u32)0x0000C000)
#define ETH_DMAArbitration_RxPriorTx ((u32)0x00000002)
#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_1_1) || \
((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_2_1) || \
((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_3_1) || \
((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_4_1) || \
((RATIO) == ETH_DMAArbitration_RxPriorTx))
/* ETHERNET DMA Flags ---------------------------------------------------*/
#define ETH_DMA_FLAG_TST ((u32)0x20000000) /* Time-stamp trigger interrupt (on DMA) */
#define ETH_DMA_FLAG_PMT ((u32)0x10000000) /* PMT interrupt (on DMA) */
#define ETH_DMA_FLAG_MMC ((u32)0x08000000) /* MMC interrupt (on DMA) */
#define ETH_DMA_FLAG_DataTransferError ((u32)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
#define ETH_DMA_FLAG_ReadWriteError ((u32)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
#define ETH_DMA_FLAG_AccessError ((u32)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
#define ETH_DMA_FLAG_NIS ((u32)0x00010000) /* Normal interrupt summary flag */
#define ETH_DMA_FLAG_AIS ((u32)0x00008000) /* Abnormal interrupt summary flag */
#define ETH_DMA_FLAG_ER ((u32)0x00004000) /* Early receive flag */
#define ETH_DMA_FLAG_FBE ((u32)0x00002000) /* Fatal bus error flag */
#define ETH_DMA_FLAG_ET ((u32)0x00000400) /* Early transmit flag */
#define ETH_DMA_FLAG_RWT ((u32)0x00000200) /* Receive watchdog timeout flag */
#define ETH_DMA_FLAG_RPS ((u32)0x00000100) /* Receive process stopped flag */
#define ETH_DMA_FLAG_RBU ((u32)0x00000080) /* Receive buffer unavailable flag */
#define ETH_DMA_FLAG_R ((u32)0x00000040) /* Receive flag */
#define ETH_DMA_FLAG_TU ((u32)0x00000020) /* Underflow flag */
#define ETH_DMA_FLAG_RO ((u32)0x00000010) /* Overflow flag */
#define ETH_DMA_FLAG_TJT ((u32)0x00000008) /* Transmit jabber timeout flag */
#define ETH_DMA_FLAG_TBU ((u32)0x00000004) /* Transmit buffer unavailable flag */
#define ETH_DMA_FLAG_TPS ((u32)0x00000002) /* Transmit process stopped flag */
#define ETH_DMA_FLAG_T ((u32)0x00000001) /* Transmit flag */
#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (u32)0xFFFE1800) == 0x00) && ((FLAG) != 0x00))
#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DataTransferError) || \
((FLAG) == ETH_DMA_FLAG_ReadWriteError) || ((FLAG) == ETH_DMA_FLAG_AccessError) || \
((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
((FLAG) == ETH_DMA_FLAG_T))
/* ETHERNET DMA Interrupts ---------------------------------------------------*/
#define ETH_DMA_IT_TST ((u32)0x20000000) /* Time-stamp trigger interrupt (on DMA) */
#define ETH_DMA_IT_PMT ((u32)0x10000000) /* PMT interrupt (on DMA) */
#define ETH_DMA_IT_MMC ((u32)0x08000000) /* MMC interrupt (on DMA) */
#define ETH_DMA_IT_NIS ((u32)0x00010000) /* Normal interrupt summary */
#define ETH_DMA_IT_AIS ((u32)0x00008000) /* Abnormal interrupt summary */
#define ETH_DMA_IT_ER ((u32)0x00004000) /* Early receive interrupt */
#define ETH_DMA_IT_FBE ((u32)0x00002000) /* Fatal bus error interrupt */
#define ETH_DMA_IT_ET ((u32)0x00000400) /* Early transmit interrupt */
#define ETH_DMA_IT_RWT ((u32)0x00000200) /* Receive watchdog timeout interrupt */
#define ETH_DMA_IT_RPS ((u32)0x00000100) /* Receive process stopped interrupt */
#define ETH_DMA_IT_RBU ((u32)0x00000080) /* Receive buffer unavailable interrupt */
#define ETH_DMA_IT_R ((u32)0x00000040) /* Receive interrupt */
#define ETH_DMA_IT_TU ((u32)0x00000020) /* Underflow interrupt */
#define ETH_DMA_IT_RO ((u32)0x00000010) /* Overflow interrupt */
#define ETH_DMA_IT_TJT ((u32)0x00000008) /* Transmit jabber timeout interrupt */
#define ETH_DMA_IT_TBU ((u32)0x00000004) /* Transmit buffer unavailable interrupt */
#define ETH_DMA_IT_TPS ((u32)0x00000002) /* Transmit process stopped interrupt */
#define ETH_DMA_IT_T ((u32)0x00000001) /* Transmit interrupt */
#define IS_ETH_DMA_IT(IT) ((((IT) & (u32)0xFFFE1800) == 0x00) && ((IT) != 0x00))
#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
/* ETHERNET DMA transmit process state --------------------------------------------------------*/
#define ETH_DMA_TransmitProcess_Stopped ((u32)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
#define ETH_DMA_TransmitProcess_Fetching ((u32)0x00100000) /* Running - fetching the Tx descriptor */
#define ETH_DMA_TransmitProcess_Waiting ((u32)0x00200000) /* Running - waiting for status */
#define ETH_DMA_TransmitProcess_Reading ((u32)0x00300000) /* Running - reading the data from host memory */
#define ETH_DMA_TransmitProcess_Suspended ((u32)0x00600000) /* Suspended - Tx Desciptor unavailabe */
#define ETH_DMA_TransmitProcess_Closing ((u32)0x00700000) /* Running - closing Rx descriptor */
/* ETHERNET DMA receive process state --------------------------------------------------------*/
#define ETH_DMA_ReceiveProcess_Stopped ((u32)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
#define ETH_DMA_ReceiveProcess_Fetching ((u32)0x00020000) /* Running - fetching the Rx descriptor */
#define ETH_DMA_ReceiveProcess_Waiting ((u32)0x00060000) /* Running - waiting for packet */
#define ETH_DMA_ReceiveProcess_Suspended ((u32)0x00080000) /* Suspended - Rx Desciptor unavailable */
#define ETH_DMA_ReceiveProcess_Closing ((u32)0x000A0000) /* Running - closing descriptor */
#define ETH_DMA_ReceiveProcess_Queuing ((u32)0x000E0000) /* Running - queuing the recieve frame into host memory */
/* ETHERNET DMA overflow --------------------------------------------------------*/
#define ETH_DMA_Overflow_RxFIFOCounter ((u32)0x10000000) /* Overflow bit for FIFO overflow counter */
#define ETH_DMA_Overflow_MissedFrameCounter ((u32)0x00010000) /* Overflow bit for missed frame counter */
#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_Overflow_RxFIFOCounter) || \
((OVERFLOW) == ETH_DMA_Overflow_MissedFrameCounter))
/*----------------------------------------------------------------------------*/
/* Ethernet PMT defines */
/*----------------------------------------------------------------------------*/
/* ETHERNET PMT Flags --------------------------------------------------------*/
#define ETH_PMT_FLAG_WUFFRPR ((u32)0x80000000) /* Wake-Up Frame Filter Register Poniter Reset */
#define ETH_PMT_FLAG_WUFR ((u32)0x00000040) /* Wake-Up Frame Received */
#define ETH_PMT_FLAG_MPR ((u32)0x00000020) /* Magic Packet Received */
#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
((FLAG) == ETH_PMT_FLAG_MPR))
/*----------------------------------------------------------------------------*/
/* Ethernet MMC defines */
/*----------------------------------------------------------------------------*/
/* ETHERNET MMC Tx Interrupts */
#define ETH_MMC_IT_TGF ((u32)0x00200000) /* When Tx good frame counter reaches half the maximum value */
#define ETH_MMC_IT_TGFMSC ((u32)0x00008000) /* When Tx good multi col counter reaches half the maximum value */
#define ETH_MMC_IT_TGFSC ((u32)0x00004000) /* When Tx good single col counter reaches half the maximum value */
/* ETHERNET MMC Rx Interrupts */
#define ETH_MMC_IT_RGUF ((u32)0x10020000) /* When Rx good unicast frames counter reaches half the maximum value */
#define ETH_MMC_IT_RFAE ((u32)0x10000040) /* When Rx alignment error counter reaches half the maximum value */
#define ETH_MMC_IT_RFCE ((u32)0x10000020) /* When Rx crc error counter reaches half the maximum value */
#define IS_ETH_MMC_IT(IT) (((((IT) & (u32)0xFFDF3FFF) == 0x00) || (((IT) & (u32)0xEFFDFF9F) == 0x00)) && \
((IT) != 0x00))
#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
/* ETHERNET MMC Registers */
#define ETH_MMCCR ((u32)0x00000100) /* MMC CR register */
#define ETH_MMCRIR ((u32)0x00000104) /* MMC RIR register */
#define ETH_MMCTIR ((u32)0x00000108) /* MMC TIR register */
#define ETH_MMCRIMR ((u32)0x0000010C) /* MMC RIMR register */
#define ETH_MMCTIMR ((u32)0x00000110) /* MMC TIMR register */
#define ETH_MMCTGFSCCR ((u32)0x0000014C) /* MMC TGFSCCR register */
#define ETH_MMCTGFMSCCR ((u32)0x00000150) /* MMC TGFMSCCR register */
#define ETH_MMCTGFCR ((u32)0x00000168) /* MMC TGFCR register */
#define ETH_MMCRFCECR ((u32)0x00000194) /* MMC RFCECR register */
#define ETH_MMCRFAECR ((u32)0x00000198) /* MMC RFAECR register */
#define ETH_MMCRGUFCR ((u32)0x000001C4) /* MMC RGUFCR register */
/* ETHERNET MMC registers */
#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) || ((REG) == ETH_MMCRIR) || \
((REG) == ETH_MMCTIR) || ((REG) == ETH_MMCRIMR) || \
((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \
((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \
((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \
((REG) == ETH_MMCRGUFCR))
/*----------------------------------------------------------------------------*/
/* Ethernet PTP defines */
/*----------------------------------------------------------------------------*/
/* ETHERNET PTP time update method -------------------------------------------*/
#define ETH_PTP_FineUpdate ((u32)0x00000001) /* Fine Update method */
#define ETH_PTP_CoarseUpdate ((u32)0x00000000) /* Coarse Update method */
#define IS_ETH_PTP_UPDATE(UPDATE) (((UPDATE) == ETH_PTP_FineUpdate) || \
((UPDATE) == ETH_PTP_CoarseUpdate))
/* ETHERNET PTP Flags --------------------------------------------------------*/
#define ETH_PTP_FLAG_TSARU ((u32)0x00000020) /* Addend Register Update */
#define ETH_PTP_FLAG_TSITE ((u32)0x00000010) /* Time Stamp Interrupt Trigger */
#define ETH_PTP_FLAG_TSSTU ((u32)0x00000008) /* Time Stamp Update */
#define ETH_PTP_FLAG_TSSTI ((u32)0x00000004) /* Time Stamp Initialize */
#define IS_ETH_PTP_GET_FLAG(FLAG) (((FLAG) == ETH_PTP_FLAG_TSARU) || \
((FLAG) == ETH_PTP_FLAG_TSITE) || \
((FLAG) == ETH_PTP_FLAG_TSSTU) || \
((FLAG) == ETH_PTP_FLAG_TSSTI))
/* ETHERNET PTP subsecond increment */
#define IS_ETH_PTP_SUBSECOND_INCREMENT(SUBSECOND) ((SUBSECOND) <= 0xFF)
/* ETHERNET PTP time sign ----------------------------------------------------*/
#define ETH_PTP_PositiveTime ((u32)0x00000000) /* Positive time value */
#define ETH_PTP_NegativeTime ((u32)0x80000000) /* Negative time value */
#define IS_ETH_PTP_TIME_SIGN(SIGN) (((SIGN) == ETH_PTP_PositiveTime) || \
((SIGN) == ETH_PTP_NegativeTime))
/* ETHERNET PTP time stamp low update */
#define IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SUBSECOND) ((SUBSECOND) <= 0x7FFFFFFF)
/* ETHERNET PTP registers */
#define ETH_PTPTSCR ((u32)0x00000700) /* PTP TSCR register */
#define ETH_PTPSSIR ((u32)0x00000704) /* PTP SSIR register */
#define ETH_PTPTSHR ((u32)0x00000708) /* PTP TSHR register */
#define ETH_PTPTSLR ((u32)0x0000070C) /* PTP TSLR register */
#define ETH_PTPTSHUR ((u32)0x00000710) /* PTP TSHUR register */
#define ETH_PTPTSLUR ((u32)0x00000714) /* PTP TSLUR register */
#define ETH_PTPTSAR ((u32)0x00000718) /* PTP TSAR register */
#define ETH_PTPTTHR ((u32)0x0000071C) /* PTP TTHR register */
#define ETH_PTPTTLR ((u32)0x00000720) /* PTP TTLR register */
#define IS_ETH_PTP_REGISTER(REG) (((REG) == ETH_PTPTSCR) || ((REG) == ETH_PTPSSIR) || \
((REG) == ETH_PTPTSHR) || ((REG) == ETH_PTPTSLR) || \
((REG) == ETH_PTPTSHUR) || ((REG) == ETH_PTPTSLUR) || \
((REG) == ETH_PTPTSAR) || ((REG) == ETH_PTPTTHR) || \
((REG) == ETH_PTPTTLR))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void ETH_DeInit(void);
u32 ETH_Init(ETH_InitTypeDef* ETH_InitStruct, u16 PHYAddress);
void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct);
void ETH_SoftwareReset(void);
FlagStatus ETH_GetSoftwareResetStatus(void);
void ETH_Start(void);
u32 ETH_HandleTxPkt(u32 addr, u16 FrameLength);
u32 ETH_HandleRxPkt(u32 addr);
u32 ETH_GetRxPktSize(void);
void ETH_DropRxPkt(void);
/*--------------------------------- PHY ------------------------------------*/
u16 ETH_ReadPHYRegister(u16 PHYAddress, u16 PHYReg);
u32 ETH_WritePHYRegister(u16 PHYAddress, u16 PHYReg, u16 PHYValue);
u32 ETH_PHYLoopBackCmd(u16 PHYAddress, FunctionalState NewState);
/*--------------------------------- MAC ------------------------------------*/
void ETH_MACTransmissionCmd(FunctionalState NewState);
void ETH_MACReceptionCmd(FunctionalState NewState);
FlagStatus ETH_GetFlowControlBusyStatus(void);
void ETH_InitiatePauseControlFrame(void);
void ETH_BackPressureActivationCmd(FunctionalState NewState);
FlagStatus ETH_GetMACFlagStatus(u32 ETH_MAC_FLAG);
ITStatus ETH_GetMACITStatus(u32 ETH_MAC_IT);
void ETH_MACITConfig(u32 ETH_MAC_IT, FunctionalState NewState);
void ETH_MACAddressConfig(u32 MacAddr, u8 *Addr);
void ETH_GetMACAddress(u32 MacAddr, u8 *Addr);
void ETH_MACAddressPerfectFilterCmd(u32 MacAddr, FunctionalState NewState);
void ETH_MACAddressFilterConfig(u32 MacAddr, u32 Filter);
void ETH_MACAddressMaskBytesFilterConfig(u32 MacAddr, u32 MaskByte);
/*----------------------- DMA Tx/Rx descriptors ----------------------------*/
void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff, u32 TxBuffCount);
void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff1, u8 *TxBuff2, u32 TxBuffCount);
FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, u32 ETH_DMATxDescFlag);
u32 ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc);
void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc);
void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 DMATxDesc_FrameSegment);
void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 DMATxDesc_Checksum);
void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 BufferSize1, u32 BufferSize2);
void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff, u32 RxBuffCount);
void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff1, u8 *RxBuff2, u32 RxBuffCount);
FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, u32 ETH_DMARxDescFlag);
void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc);
u32 ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc);
void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
u32 ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, u32 DMARxDesc_Buffer);
/*--------------------------------- DMA ------------------------------------*/
FlagStatus ETH_GetDMAFlagStatus(u32 ETH_DMA_FLAG);
void ETH_DMAClearFlag(u32 ETH_DMA_FLAG);
ITStatus ETH_GetDMAITStatus(u32 ETH_DMA_IT);
void ETH_DMAClearITPendingBit(u32 ETH_DMA_IT);
u32 ETH_GetTransmitProcessState(void);
u32 ETH_GetReceiveProcessState(void);
void ETH_FlushTransmitFIFO(void);
FlagStatus ETH_GetFlushTransmitFIFOStatus(void);
void ETH_DMATransmissionCmd(FunctionalState NewState);
void ETH_DMAReceptionCmd(FunctionalState NewState);
void ETH_DMAITConfig(u32 ETH_DMA_IT, FunctionalState NewState);
FlagStatus ETH_GetDMAOverflowStatus(u32 ETH_DMA_Overflow);
u32 ETH_GetRxOverflowMissedFrameCounter(void);
u32 ETH_GetBufferUnavailableMissedFrameCounter(void);
u32 ETH_GetCurrentTxDescStartAddress(void);
u32 ETH_GetCurrentRxDescStartAddress(void);
u32 ETH_GetCurrentTxBufferAddress(void);
u32 ETH_GetCurrentRxBufferAddress(void);
void ETH_ResumeDMATransmission(void);
void ETH_ResumeDMAReception(void);
/*--------------------------------- PMT ------------------------------------*/
void ETH_ResetWakeUpFrameFilterRegisterPointer(void);
void ETH_SetWakeUpFrameFilterRegister(u32 *Buffer);
void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState);
FlagStatus ETH_GetPMTFlagStatus(u32 ETH_PMT_FLAG);
void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState);
void ETH_MagicPacketDetectionCmd(FunctionalState NewState);
void ETH_PowerDownCmd(FunctionalState NewState);
/*--------------------------------- MMC ------------------------------------*/
void ETH_MMCCounterFreezeCmd(FunctionalState NewState);
void ETH_MMCResetOnReadCmd(FunctionalState NewState);
void ETH_MMCCounterRolloverCmd(FunctionalState NewState);
void ETH_MMCCountersReset(void);
void ETH_MMCITConfig(u32 ETH_MMC_IT, FunctionalState NewState);
ITStatus ETH_GetMMCITStatus(u32 ETH_MMC_IT);
u32 ETH_GetMMCRegister(u32 ETH_MMCReg);
/*--------------------------------- PTP ------------------------------------*/
u32 ETH_HandlePTPTxPkt(u8 *ppkt, u16 FrameLength, u32 *PTPTxTab);
u32 ETH_HandlePTPRxPkt(u8 *ppkt, u32 *PTPRxTab);
void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, u8* TxBuff, u32 TxBuffCount);
void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, u8 *RxBuff, u32 RxBuffCount);
void ETH_EnablePTPTimeStampAddend(void);
void ETH_EnablePTPTimeStampInterruptTrigger(void);
void ETH_EnablePTPTimeStampUpdate(void);
void ETH_InitializePTPTimeStamp(void);
void ETH_PTPUpdateMethodConfig(u32 UpdateMethod);
void ETH_PTPTimeStampCmd(FunctionalState NewState);
FlagStatus ETH_GetPTPFlagStatus(u32 ETH_PTP_FLAG);
void ETH_SetPTPSubSecondIncrement(u32 SubSecondValue);
void ETH_SetPTPTimeStampUpdate(u32 Sign, u32 SecondValue, u32 SubSecondValue);
void ETH_SetPTPTimeStampAddend(u32 Value);
void ETH_SetPTPTargetTime(u32 HighValue, u32 LowValue);
u32 ETH_GetPTPRegister(u32 ETH_PTPReg);
#endif /* __STM32FXXX_ETH_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth.h | C | oos | 79,357 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_rtc.h
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file contains all the functions prototypes for the
* RTC firmware library.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_RTC_H
#define __STM32F10x_RTC_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* RTC interrupts define -----------------------------------------------------*/
#define RTC_IT_OW ((u16)0x0004) /* Overflow interrupt */
#define RTC_IT_ALR ((u16)0x0002) /* Alarm interrupt */
#define RTC_IT_SEC ((u16)0x0001) /* Second interrupt */
#define IS_RTC_IT(IT) (((IT & (u16)0xFFF8) == 0x00) && (IT != 0x00))
#define IS_RTC_GET_IT(IT) ((IT == RTC_IT_OW) || (IT == RTC_IT_ALR) || \
(IT == RTC_IT_SEC))
/* RTC interrupts flags ------------------------------------------------------*/
#define RTC_FLAG_RTOFF ((u16)0x0020) /* RTC Operation OFF flag */
#define RTC_FLAG_RSF ((u16)0x0008) /* Registers Synchronized flag */
#define RTC_FLAG_OW ((u16)0x0004) /* Overflow flag */
#define RTC_FLAG_ALR ((u16)0x0002) /* Alarm flag */
#define RTC_FLAG_SEC ((u16)0x0001) /* Second flag */
#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xFFF0) == 0x00) && (FLAG != 0x00))
#define IS_RTC_GET_FLAG(FLAG) ((FLAG == RTC_FLAG_RTOFF) || (FLAG == RTC_FLAG_RSF) || \
(FLAG == RTC_FLAG_OW) || (FLAG == RTC_FLAG_ALR) || \
(FLAG == RTC_FLAG_SEC))
#define IS_RTC_PRESCALER(PRESCALER) (PRESCALER <= 0xFFFFF)
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState);
void RTC_EnterConfigMode(void);
void RTC_ExitConfigMode(void);
u32 RTC_GetCounter(void);
void RTC_SetCounter(u32 CounterValue);
u32 RTC_GetPrescaler(void);
void RTC_SetPrescaler(u32 PrescalerValue);
void RTC_SetAlarm(u32 AlarmValue);
u32 RTC_GetDivider(void);
void RTC_WaitForLastTask(void);
void RTC_WaitForSynchro(void);
FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG);
void RTC_ClearFlag(u16 RTC_FLAG);
ITStatus RTC_GetITStatus(u16 RTC_IT);
void RTC_ClearITPendingBit(u16 RTC_IT);
#endif /* __STM32F10x_RTC_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_rtc.h | C | oos | 3,747 |
/**
******************************************************************************
* @file stm32f10x_dac.h
* @author MCD Application Team
* @version V3.0.0
* @date 04/06/2009
* @brief This file contains all the functions prototypes for the DAC firmware
* library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_DAC_H
#define __STM32F10x_DAC_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @addtogroup DAC
* @{
*/
/** @defgroup DAC_Exported_Types
* @{
*/
/**
* @brief DAC Init structure definition
*/
typedef struct
{
uint32_t DAC_Trigger;
uint32_t DAC_WaveGeneration;
uint32_t DAC_LFSRUnmask_TriangleAmplitude;
uint32_t DAC_OutputBuffer;
}DAC_InitTypeDef;
/**
* @}
*/
/** @defgroup DAC_Exported_Constants
* @{
*/
/** @defgroup DAC_trigger_selection
* @{
*/
#define DAC_Trigger_None ((uint32_t)0x00000000)
#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004)
#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C)
#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014)
#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C)
#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024)
#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C)
#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034)
#define DAC_Trigger_Software ((uint32_t)0x0000003C)
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
((TRIGGER) == DAC_Trigger_T6_TRGO) || \
((TRIGGER) == DAC_Trigger_T8_TRGO) || \
((TRIGGER) == DAC_Trigger_T7_TRGO) || \
((TRIGGER) == DAC_Trigger_T5_TRGO) || \
((TRIGGER) == DAC_Trigger_T2_TRGO) || \
((TRIGGER) == DAC_Trigger_T4_TRGO) || \
((TRIGGER) == DAC_Trigger_Ext_IT9) || \
((TRIGGER) == DAC_Trigger_Software))
/**
* @}
*/
/** @defgroup DAC_wave_generation
* @{
*/
#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
((WAVE) == DAC_WaveGeneration_Noise) || \
((WAVE) == DAC_WaveGeneration_Triangle))
/**
* @}
*/
/** @defgroup DAC_noise_wave_generation_mask_triangle_wave_generation_max_amplitude
* @{
*/
#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000)
#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100)
#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200)
#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300)
#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400)
#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500)
#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600)
#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700)
#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800)
#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900)
#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00)
#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00)
#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000)
#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100)
#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200)
#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300)
#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400)
#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500)
#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600)
#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700)
#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800)
#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900)
#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00)
#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00)
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
((VALUE) == DAC_TriangleAmplitude_1) || \
((VALUE) == DAC_TriangleAmplitude_3) || \
((VALUE) == DAC_TriangleAmplitude_7) || \
((VALUE) == DAC_TriangleAmplitude_15) || \
((VALUE) == DAC_TriangleAmplitude_31) || \
((VALUE) == DAC_TriangleAmplitude_63) || \
((VALUE) == DAC_TriangleAmplitude_127) || \
((VALUE) == DAC_TriangleAmplitude_255) || \
((VALUE) == DAC_TriangleAmplitude_511) || \
((VALUE) == DAC_TriangleAmplitude_1023) || \
((VALUE) == DAC_TriangleAmplitude_2047) || \
((VALUE) == DAC_TriangleAmplitude_4095))
/**
* @}
*/
/** @defgroup DAC_output_buffer
* @{
*/
#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
((STATE) == DAC_OutputBuffer_Disable))
/**
* @}
*/
/** @defgroup DAC_Channel_selection
* @{
*/
#define DAC_Channel_1 ((uint32_t)0x00000000)
#define DAC_Channel_2 ((uint32_t)0x00000010)
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
((CHANNEL) == DAC_Channel_2))
/**
* @}
*/
/** @defgroup DAC_data_alignement
* @{
*/
#define DAC_Align_12b_R ((uint32_t)0x00000000)
#define DAC_Align_12b_L ((uint32_t)0x00000004)
#define DAC_Align_8b_R ((uint32_t)0x00000008)
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
((ALIGN) == DAC_Align_12b_L) || \
((ALIGN) == DAC_Align_8b_R))
/**
* @}
*/
/** @defgroup DAC_wave_generation
* @{
*/
#define DAC_Wave_Noise ((uint32_t)0x00000040)
#define DAC_Wave_Triangle ((uint32_t)0x00000080)
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
((WAVE) == DAC_Wave_Triangle))
/**
* @}
*/
/** @defgroup DAC_data
* @{
*/
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
/**
* @}
*/
/**
* @}
*/
/** @defgroup DAC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup DAC_Exported_Functions
* @{
*/
void DAC_DeInit(void);
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
#endif /*__STM32F10x_DAC_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_dac.h | C | oos | 10,271 |
/**
******************************************************************************
* @file stm32f10x_flash.h
* @author MCD Application Team
* @version V3.0.0
* @date 04/06/2009
* @brief This file contains all the functions prototypes for the FLASH
* firmware library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_FLASH_H
#define __STM32F10x_FLASH_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @addtogroup FLASH
* @{
*/
/** @defgroup FLASH_Exported_Types
* @{
*/
/**
* @brief FLASH Status
*/
typedef enum
{
FLASH_BUSY = 1,
FLASH_ERROR_PG,
FLASH_ERROR_WRP,
FLASH_COMPLETE,
FLASH_TIMEOUT
}FLASH_Status;
/**
* @}
*/
/** @defgroup FLASH_Exported_Constants
* @{
*/
/** @defgroup Flash_Latency
* @{
*/
#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */
#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */
#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
((LATENCY) == FLASH_Latency_1) || \
((LATENCY) == FLASH_Latency_2))
/**
* @}
*/
/** @defgroup Half_Cycle_Enable_Disable
* @{
*/
#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /* FLASH Half Cycle Enable */
#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /* FLASH Half Cycle Disable */
#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \
((STATE) == FLASH_HalfCycleAccess_Disable))
/**
* @}
*/
/** @defgroup Prefetch_Buffer_Enable_Disable
* @{
*/
#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /* FLASH Prefetch Buffer Enable */
#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /* FLASH Prefetch Buffer Disable */
#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \
((STATE) == FLASH_PrefetchBuffer_Disable))
/**
* @}
*/
/** @defgroup Option_Bytes_Write_Protection
* @{
*/
/* Values to be used with STM32F10Xxx Medium-density devices: FLASH memory density
ranges between 32 and 128 Kbytes with page size equal to 1 Kbytes */
#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /* Write protection of page 0 to 3 */
#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /* Write protection of page 4 to 7 */
#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /* Write protection of page 8 to 11 */
#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /* Write protection of page 12 to 15 */
#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /* Write protection of page 16 to 19 */
#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /* Write protection of page 20 to 23 */
#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /* Write protection of page 24 to 27 */
#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /* Write protection of page 28 to 31 */
#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /* Write protection of page 32 to 35 */
#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /* Write protection of page 36 to 39 */
#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /* Write protection of page 40 to 43 */
#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /* Write protection of page 44 to 47 */
#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /* Write protection of page 48 to 51 */
#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /* Write protection of page 52 to 55 */
#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /* Write protection of page 56 to 59 */
#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /* Write protection of page 60 to 63 */
#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /* Write protection of page 64 to 67 */
#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /* Write protection of page 68 to 71 */
#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /* Write protection of page 72 to 75 */
#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /* Write protection of page 76 to 79 */
#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /* Write protection of page 80 to 83 */
#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /* Write protection of page 84 to 87 */
#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /* Write protection of page 88 to 91 */
#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /* Write protection of page 92 to 95 */
#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /* Write protection of page 96 to 99 */
#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /* Write protection of page 100 to 103 */
#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /* Write protection of page 104 to 107 */
#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /* Write protection of page 108 to 111 */
#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /* Write protection of page 112 to 115 */
#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /* Write protection of page 115 to 119 */
#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /* Write protection of page 120 to 123 */
#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /* Write protection of page 124 to 127 */
/* Values to be used with STM32F10Xxx High-density devices: FLASH memory density
ranges between 256 and 512 Kbytes with page size equal to 2 Kbytes */
#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */
#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */
#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */
#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */
#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */
#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */
#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */
#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */
#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */
#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */
#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */
#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */
#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */
#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */
#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */
#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */
#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */
#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */
#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */
#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */
#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */
#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */
#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */
#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */
#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */
#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */
#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */
#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */
#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */
#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */
#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */
#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /* Write protection of page 62 to 255 */
#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /* Write protection of all Pages */
#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))
#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0807FFFF))
#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
/**
* @}
*/
/** @defgroup Option_Bytes_IWatchdog
* @{
*/
#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */
#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
/**
* @}
*/
/** @defgroup Option_Bytes_nRST_STOP
* @{
*/
#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */
#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
/**
* @}
*/
/** @defgroup Option_Bytes_nRST_STDBY
* @{
*/
#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
/**
* @}
*/
/** @defgroup FLASH_Interrupts
* @{
*/
#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */
#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
/**
* @}
*/
/** @defgroup FLASH_Flags
* @{
*/
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */
#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /* FLASH Program error flag */
#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */
#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
((FLAG) == FLASH_FLAG_OPTERR))
/**
* @}
*/
/**
* @}
*/
/** @defgroup FLASH_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup FLASH_Exported_Functions
* @{
*/
void FLASH_SetLatency(uint32_t FLASH_Latency);
void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);
void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);
void FLASH_Unlock(void);
void FLASH_Lock(void);
FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
FLASH_Status FLASH_EraseAllPages(void);
FLASH_Status FLASH_EraseOptionBytes(void);
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);
FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
uint32_t FLASH_GetUserOptionByte(void);
uint32_t FLASH_GetWriteProtectionOptionByte(void);
FlagStatus FLASH_GetReadOutProtectionStatus(void);
FlagStatus FLASH_GetPrefetchBufferStatus(void);
void FLASH_ITConfig(uint16_t FLASH_IT, FunctionalState NewState);
FlagStatus FLASH_GetFlagStatus(uint16_t FLASH_FLAG);
void FLASH_ClearFlag(uint16_t FLASH_FLAG);
FLASH_Status FLASH_GetStatus(void);
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
#endif /* __STM32F10x_FLASH_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_flash.h | C | oos | 14,446 |
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f_eth_conf.h
* Author : MCD Application Team
* Version : VX.Y.Z
* Date : mm/dd/2008
* Description : ETHERNET firmware library configuration file.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F_ETH_CONF_H
#define __STM32F_ETH_CONF_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_type.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Uncomment the line below to compile the ETHERNET firmware library in DEBUG mode,
this will expanse the "assert_param" macro in the firmware library code (see
"Exported macro" section below) */
/*#define ETH_DEBUG 1*/
/* Comment the line below to disable the specific peripheral inclusion */
/************************************* ETHERNET *******************************/
#define _ETH_MAC
//#define _ETH_PTP
//#define _ETH_MMC
#define _ETH_DMA
/* Exported macro ------------------------------------------------------------*/
#ifdef ETH_DEBUG
/*******************************************************************************
* Macro Name : eth_assert_param
* Description : The eth_assert_param macro is used for ethernet function's parameters
* check.
* It is used only if the ethernet library is compiled in DEBUG mode.
* Input : - expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* Return : None
*******************************************************************************/
#define eth_assert_param(expr) ((expr) ? (void)0 : assert_failed((u8 *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(u8* file, u32 line);
#else
#define eth_assert_param(expr) ((void)0)
#endif /* ETH_DEBUG */
#endif /* __STM32F_ETH_CONF_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth_conf.h | C | oos | 3,046 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : lcd.h
* Author : MCD Application Team
* Date First Issued : mm/dd/yyyy
* Description : This file contains all the functions prototypes for the
* lcd software driver.
********************************************************************************
* History:
* mm/dd/yyyy
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __LCD_H
#define __LCD_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_lib.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* LCD Registers */
#define R0 0x00
#define R1 0x01
#define R2 0x02
#define R3 0x03
#define R5 0x05
#define R6 0x06
#define R13 0x0D
#define R14 0x0E
#define R15 0x0F
#define R16 0x10
#define R17 0x11
#define R18 0x12
#define R19 0x13
#define R20 0x14
#define R21 0x15
#define R22 0x16
#define R23 0x17
#define R24 0x18
#define R25 0x19
#define R26 0x1A
#define R27 0x1B
#define R28 0x1C
#define R29 0x1D
#define R30 0x1E
#define R31 0x1F
#define R32 0x20
#define R36 0x24
#define R37 0x25
#define R40 0x28
#define R43 0x2B
#define R45 0x2D
#define R49 0x31
#define R50 0x32
#define R51 0x33
#define R52 0x34
#define R53 0x35
#define R55 0x37
#define R59 0x3B
#define R60 0x3C
#define R61 0x3D
#define R62 0x3E
#define R63 0x3F
#define R64 0x40
#define R65 0x41
#define R66 0x42
#define R67 0x43
#define R68 0x44
#define R69 0x45
#define R70 0x46
#define R71 0x47
#define R72 0x48
#define R73 0x49
#define R74 0x4A
#define R75 0x4B
#define R76 0x4C
#define R77 0x4D
#define R78 0x4E
#define R79 0x4F
#define R80 0x50
#define R118 0x76
#define R134 0x86
#define R135 0x87
#define R136 0x88
#define R137 0x89
#define R139 0x8B
#define R140 0x8C
#define R141 0x8D
#define R143 0x8F
#define R144 0x90
#define R145 0x91
#define R146 0x92
#define R147 0x93
#define R148 0x94
#define R149 0x95
#define R150 0x96
#define R151 0x97
#define R152 0x98
#define R153 0x99
#define R154 0x9A
#define R157 0x9D
#define R192 0xC0
#define R193 0xC1
/* LCD Control pins */
#define CtrlPin_NCS GPIO_Pin_2 /* PB.02 */
#define CtrlPin_RS GPIO_Pin_7 /* PD.07 */
#define CtrlPin_NWR GPIO_Pin_15 /* PD.15 */
/* LCD color */
#define White 0xFFFF
#define Black 0x0000
#define Blue 0x001F
#define Orange 0x051F
#define Red 0xF800
#define Magenta 0xF81F
#define Green 0x07E0
#define Cyan 0x7FFF
#define Yellow 0xFFE0
#define Line0 0
#define Line1 24
#define Line2 48
#define Line3 72
#define Line4 96
#define Line5 120
#define Line6 144
#define Line7 168
#define Line8 192
#define Line9 216
#define Horizontal 0x00
#define Vertical 0x01
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/*----- High layer function -----*/
void LCD_Init(void);
void LCD_SetTextColor(vu16 Color);
void LCD_SetBackColor(vu16 Color);
void LCD_ClearLine(u8 Line);
void LCD_Clear(void);
void LCD_SetCursor(u8 Xpos, u16 Ypos);
void LCD_DrawChar(u8 Xpos, u16 Ypos, uc16 *c);
void LCD_DisplayChar(u8 Line, u16 Column, u8 Ascii);
void LCD_DisplayStringLine(u8 Line, u8 *ptr);
void LCD_DisplayString(u8 Line, u8 *ptr);
void LCD_ScrollText(u8 Line, u8 *ptr);
void LCD_SetDisplayWindow(u8 Xpos, u16 Ypos, u8 Height, u16 Width);
void LCD_DrawLine(u8 Xpos, u16 Ypos, u16 Length, u8 Direction);
void LCD_DrawRect(u8 Xpos, u16 Ypos, u8 Height, u16 Width);
void LCD_DrawCircle(u8 Xpos, u16 Ypos, u16 Radius);
void LCD_DrawMonoPict(uc32 *Pict);
void LCD_DrawBMP(u32 BmpAddress);
/*----- Medium layer function -----*/
void LCD_WriteReg(u8 LCD_Reg, u8 LCD_RegValue);
u8 LCD_ReadReg(u8 LCD_Reg);
void LCD_WriteRAM(u16 RGB_Code);
u16 LCD_ReadRAM(void);
void LCD_PowerOn(void);
void LCD_DisplayOn(void);
void LCD_DisplayOff(void);
/*----- Low layer function -----*/
void LCD_CtrlLinesConfig(void);
void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, u16 CtrlPins, BitAction BitVal);
void LCD_SPIConfig(void);
#endif /* __LCD_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/lcd.h | C | oos | 6,137 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_iwdg.h
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file contains all the functions prototypes for the
* IWDG firmware library.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_IWDG_H
#define __STM32F10x_IWDG_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Write access to IWDG_PR and IWDG_RLR registers */
#define IWDG_WriteAccess_Enable ((u16)0x5555)
#define IWDG_WriteAccess_Disable ((u16)0x0000)
#define IS_IWDG_WRITE_ACCESS(ACCESS) ((ACCESS == IWDG_WriteAccess_Enable) || \
(ACCESS == IWDG_WriteAccess_Disable))
/* IWDG prescaler */
#define IWDG_Prescaler_4 ((u8)0x00)
#define IWDG_Prescaler_8 ((u8)0x01)
#define IWDG_Prescaler_16 ((u8)0x02)
#define IWDG_Prescaler_32 ((u8)0x03)
#define IWDG_Prescaler_64 ((u8)0x04)
#define IWDG_Prescaler_128 ((u8)0x05)
#define IWDG_Prescaler_256 ((u8)0x06)
#define IS_IWDG_PRESCALER(PRESCALER) ((PRESCALER == IWDG_Prescaler_4) || \
(PRESCALER == IWDG_Prescaler_8) || \
(PRESCALER == IWDG_Prescaler_16) || \
(PRESCALER == IWDG_Prescaler_32) || \
(PRESCALER == IWDG_Prescaler_64) || \
(PRESCALER == IWDG_Prescaler_128)|| \
(PRESCALER == IWDG_Prescaler_256))
/* IWDG Flag */
#define IWDG_FLAG_PVU ((u16)0x0001)
#define IWDG_FLAG_RVU ((u16)0x0002)
#define IS_IWDG_FLAG(FLAG) ((FLAG == IWDG_FLAG_PVU) || (FLAG == IWDG_FLAG_RVU))
#define IS_IWDG_RELOAD(RELOAD) (RELOAD <= 0xFFF)
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void IWDG_WriteAccessCmd(u16 IWDG_WriteAccess);
void IWDG_SetPrescaler(u8 IWDG_Prescaler);
void IWDG_SetReload(u16 Reload);
void IWDG_ReloadCounter(void);
void IWDG_Enable(void);
FlagStatus IWDG_GetFlagStatus(u16 IWDG_FLAG);
#endif /* __STM32F10x_IWDG_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_iwdg.h | C | oos | 3,514 |
/**
******************************************************************************
* @file stm32f10x_dbgmcu.h
* @author MCD Application Team
* @version V3.0.0
* @date 04/06/2009
* @brief This file contains all the functions prototypes for the DBGMCU
* firmware library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_DBGMCU_H
#define __STM32F10x_DBGMCU_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @addtogroup DBGMCU
* @{
*/
/** @defgroup DBGMCU_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup DBGMCU_Exported_Constants
* @{
*/
#define DBGMCU_SLEEP ((uint32_t)0x00000001)
#define DBGMCU_STOP ((uint32_t)0x00000002)
#define DBGMCU_STANDBY ((uint32_t)0x00000004)
#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100)
#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200)
#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400)
#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800)
#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000)
#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000)
#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000)
#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000)
#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000)
#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000)
#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000)
#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000)
#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000)
#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFE000F8) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
/** @defgroup DBGMCU_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup DBGMCU_Exported_Functions
* @{
*/
uint32_t DBGMCU_GetREVID(void);
uint32_t DBGMCU_GetDEVID(void);
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
#endif /* __STM32F10x_DBGMCU_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_dbgmcu.h | C | oos | 2,980 |
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32fxxx_eth_map.h
* Author : MCD Application Team
* Version : VX.Y.Z
* Date : mm/dd/2008
* Description : This file contains all ETHERNET peripheral register's
* definitions and memory mapping.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32FXXX_ETH_MAP_H
#define __STM32FXXX_ETH_MAP_H
#ifndef EXT
#define EXT extern
#endif /* EXT */
/* Includes ------------------------------------------------------------------*/
#include "stm32fxxx_eth_conf.h"
#include "stm32f10x_type.h"
/* Exported types ------------------------------------------------------------*/
/******************************************************************************/
/* Ethernet Peripheral registers structures */
/******************************************************************************/
typedef struct
{
vu32 MACCR;
vu32 MACFFR;
vu32 MACHTHR;
vu32 MACHTLR;
vu32 MACMIIAR;
vu32 MACMIIDR;
vu32 MACFCR;
vu32 MACVLANTR;
vu32 RESERVED0[2];
vu32 MACRWUFFR;
vu32 MACPMTCSR;
vu32 RESERVED1[2];
vu32 MACSR;
vu32 MACIMR;
vu32 MACA0HR;
vu32 MACA0LR;
vu32 MACA1HR;
vu32 MACA1LR;
vu32 MACA2HR;
vu32 MACA2LR;
vu32 MACA3HR;
vu32 MACA3LR;
} ETH_MAC_TypeDef;
typedef struct
{
vu32 MMCCR;
vu32 MMCRIR;
vu32 MMCTIR;
vu32 MMCRIMR;
vu32 MMCTIMR;
vu32 RESERVED0[14];
vu32 MMCTGFSCCR;
vu32 MMCTGFMSCCR;
vu32 RESERVED1[5];
vu32 MMCTGFCR;
vu32 RESERVED2[10];
vu32 MMCRFCECR;
vu32 MMCRFAER;
vu32 RESERVED3[10];
vu32 MMCRGUFCR;
} ETH_MMC_TypeDef;
typedef struct
{
vu32 PTPTSCR;
vu32 PTPSSIR;
vu32 PTPTSHR;
vu32 PTPTSLR;
vu32 PTPTSHUR;
vu32 PTPTSLUR;
vu32 PTPTSAR;
vu32 PTPTTHR;
vu32 PTPTTLR;
} ETH_PTP_TypeDef;
typedef struct
{
vu32 DMABMR;
vu32 DMATPDR;
vu32 DMARPDR;
vu32 DMARDLAR;
vu32 DMATDLAR;
vu32 DMASR;
vu32 DMAOMR;
vu32 DMAIER;
vu32 DMAMFBOCR;
vu32 RESERVED0[9];
vu32 DMACHTDR;
vu32 DMACHRDR;
vu32 DMACHTBAR;
vu32 DMACHRBAR;
} ETH_DMA_TypeDef;
/******************************************************************************/
/* Ethernet MAC Registers bits definitions */
/******************************************************************************/
//#define IPNAME_REGNAME_BITNAME /* BIT MASK */
/* Bit definition for Ethernet MAC Control Register register */
#define ETH_MACCR_WD ((u32)0x00800000) /* Watchdog disable */
#define ETH_MACCR_JD ((u32)0x00400000) /* Jabber disable */
#define ETH_MACCR_JFE ((u32)0x00100000) /* Jumbo frame enable */
#define ETH_MACCR_IFG ((u32)0x000E0000) /* Inter-frame gap */
#define ETH_MACCR_IFG_96Bit ((u32)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
#define ETH_MACCR_IFG_88Bit ((u32)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
#define ETH_MACCR_IFG_80Bit ((u32)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
#define ETH_MACCR_IFG_72Bit ((u32)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
#define ETH_MACCR_IFG_64Bit ((u32)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
#define ETH_MACCR_IFG_56Bit ((u32)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
#define ETH_MACCR_IFG_48Bit ((u32)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
#define ETH_MACCR_IFG_40Bit ((u32)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
#define ETH_MACCR_CSD ((u32)0x00010000) /* Carrier sense disable (during transmission) */
#define ETH_MACCR_FES ((u32)0x00004000) /* Fast ethernet speed */
#define ETH_MACCR_ROD ((u32)0x00002000) /* Receive own disable */
#define ETH_MACCR_LM ((u32)0x00001000) /* loopback mode */
#define ETH_MACCR_DM ((u32)0x00000800) /* Duplex mode */
#define ETH_MACCR_IPCO ((u32)0x00000400) /* IP Checksum offload */
#define ETH_MACCR_RD ((u32)0x00000200) /* Retry disable */
#define ETH_MACCR_APCS ((u32)0x00000080) /* Automatic Pad/CRC stripping */
#define ETH_MACCR_BL ((u32)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
a transmission attempt during retries after a collision: 0 =< r <2^k */
#define ETH_MACCR_BL_10 ((u32)0x00000000) /* k = min (n, 10) */
#define ETH_MACCR_BL_8 ((u32)0x00000020) /* k = min (n, 8) */
#define ETH_MACCR_BL_4 ((u32)0x00000040) /* k = min (n, 4) */
#define ETH_MACCR_BL_1 ((u32)0x00000060) /* k = min (n, 1) */
#define ETH_MACCR_DC ((u32)0x00000010) /* Defferal check */
#define ETH_MACCR_TE ((u32)0x00000008) /* Transmitter enable */
#define ETH_MACCR_RE ((u32)0x00000004) /* Receiver enable */
/* Bit definition for Ethernet MAC Frame Filter Register */
#define ETH_MACFFR_RA ((u32)0x80000000) /* Receive all */
#define ETH_MACFFR_HPF ((u32)0x00000400) /* Hash or perfect filter */
#define ETH_MACFFR_SAF ((u32)0x00000200) /* Source address filter enable */
#define ETH_MACFFR_SAIF ((u32)0x00000100) /* SA inverse filtering */
#define ETH_MACFFR_PCF ((u32)0x000000C0) /* Pass control frames: 3 cases */
#define ETH_MACFFR_PCF_BlockAll ((u32)0x00000040) /* MAC filters all control frames from reaching the application */
#define ETH_MACFFR_PCF_ForwardAll ((u32)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((u32)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
#define ETH_MACFFR_BFD ((u32)0x00000020) /* Broadcast frame disable */
#define ETH_MACFFR_PAM ((u32)0x00000010) /* Pass all mutlicast */
#define ETH_MACFFR_DAIF ((u32)0x00000008) /* DA Inverse filtering */
#define ETH_MACFFR_HM ((u32)0x00000004) /* Hash multicast */
#define ETH_MACFFR_HU ((u32)0x00000002) /* Hash unicast */
#define ETH_MACFFR_PM ((u32)0x00000001) /* Promiscuous mode */
/* Bit definition for Ethernet MAC Hash Table High Register */
#define ETH_MACHTHR_HTH ((u32)0xFFFFFFFF) /* Hash table high */
/* Bit definition for Ethernet MAC Hash Table Low Register */
#define ETH_MACHTLR_HTL ((u32)0xFFFFFFFF) /* Hash table low */
/* Bit definition for Ethernet MAC MII Address Register */
#define ETH_MACMIIAR_PA ((u32)0x0000F800) /* Physical layer address */
#define ETH_MACMIIAR_MR ((u32)0x000007C0) /* MII register in the selected PHY */
#define ETH_MACMIIAR_CR ((u32)0x0000001C) /* CR clock range: 6 cases */
#define ETH_MACMIIAR_CR_Div42 ((u32)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */
#define ETH_MACMIIAR_CR_Div16 ((u32)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
#define ETH_MACMIIAR_CR_Div26 ((u32)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
#define ETH_MACMIIAR_MW ((u32)0x00000002) /* MII write */
#define ETH_MACMIIAR_MB ((u32)0x00000001) /* MII busy */
/* Bit definition for Ethernet MAC MII Data Register */
#define ETH_MACMIIDR_MD ((u32)0x0000FFFF) /* MII data: read/write data from/to PHY */
/* Bit definition for Ethernet MAC Flow Control Register */
#define ETH_MACFCR_PT ((u32)0xFFFF0000) /* Pause time */
#define ETH_MACFCR_ZQPD ((u32)0x00000080) /* Zero-quanta pause disable */
#define ETH_MACFCR_PLT ((u32)0x00000030) /* Pause low threshold: 4 cases */
#define ETH_MACFCR_PLT_Minus4 ((u32)0x00000000) /* Pause time minus 4 slot times */
#define ETH_MACFCR_PLT_Minus28 ((u32)0x00000010) /* Pause time minus 28 slot times */
#define ETH_MACFCR_PLT_Minus144 ((u32)0x00000020) /* Pause time minus 144 slot times */
#define ETH_MACFCR_PLT_Minus256 ((u32)0x00000030) /* Pause time minus 256 slot times */
#define ETH_MACFCR_UPFD ((u32)0x00000008) /* Unicast pause frame detect */
#define ETH_MACFCR_RFCE ((u32)0x00000004) /* Receive flow control enable */
#define ETH_MACFCR_TFCE ((u32)0x00000002) /* Transmit flow control enable */
#define ETH_MACFCR_FCBBPA ((u32)0x00000001) /* Flow control busy/backpressure activate */
/* Bit definition for Ethernet MAC VLAN Tag Register */
#define ETH_MACVLANTR_VLANTC ((u32)0x00010000) /* 12-bit VLAN tag comparison */
#define ETH_MACVLANTR_VLANTI ((u32)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
#define ETH_MACRWUFFR_D ((u32)0xFFFFFFFF) /* Wake-up frame filter register data */
/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
RSVD - Filter1 Command - RSVD - Filter0 Command
Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
/* Bit definition for Ethernet MAC PMT Control and Status Register */
#define ETH_MACPMTCSR_WFFRPR ((u32)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
#define ETH_MACPMTCSR_GU ((u32)0x00000200) /* Global Unicast */
#define ETH_MACPMTCSR_WFR ((u32)0x00000040) /* Wake-Up Frame Received */
#define ETH_MACPMTCSR_MPR ((u32)0x00000020) /* Magic Packet Received */
#define ETH_MACPMTCSR_WFE ((u32)0x00000004) /* Wake-Up Frame Enable */
#define ETH_MACPMTCSR_MPE ((u32)0x00000002) /* Magic Packet Enable */
#define ETH_MACPMTCSR_PD ((u32)0x00000001) /* Power Down */
/* Bit definition for Ethernet MAC Status Register */
#define ETH_MACSR_TSTS ((u32)0x00000200) /* Time stamp trigger status */
#define ETH_MACSR_MMCTS ((u32)0x00000040) /* MMC transmit status */
#define ETH_MACSR_MMMCRS ((u32)0x00000020) /* MMC receive status */
#define ETH_MACSR_MMCS ((u32)0x00000010) /* MMC status */
#define ETH_MACSR_PMTS ((u32)0x00000008) /* PMT status */
/* Bit definition for Ethernet MAC Interrupt Mask Register */
#define ETH_MACIMR_TSTIM ((u32)0x00000200) /* Time stamp trigger interrupt mask */
#define ETH_MACIMR_PMTIM ((u32)0x00000008) /* PMT interrupt mask */
/* Bit definition for Ethernet MAC Address0 High Register */
#define ETH_MACA0HR_MACA0H ((u32)0x0000FFFF) /* MAC address0 high */
/* Bit definition for Ethernet MAC Address0 Low Register */
#define ETH_MACA0LR_MACA0L ((u32)0xFFFFFFFF) /* MAC address0 low */
/* Bit definition for Ethernet MAC Address1 High Register */
#define ETH_MACA1HR_AE ((u32)0x80000000) /* Address enable */
#define ETH_MACA1HR_SA ((u32)0x40000000) /* Source address */
#define ETH_MACA1HR_MBC ((u32)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
#define ETH_MACA1HR_MBC_HBits15_8 ((u32)0x20000000) /* Mask MAC Address high reg bits [15:8] */
#define ETH_MACA1HR_MBC_HBits7_0 ((u32)0x10000000) /* Mask MAC Address high reg bits [7:0] */
#define ETH_MACA1HR_MBC_LBits31_24 ((u32)0x08000000) /* Mask MAC Address low reg bits [31:24] */
#define ETH_MACA1HR_MBC_LBits23_16 ((u32)0x04000000) /* Mask MAC Address low reg bits [23:16] */
#define ETH_MACA1HR_MBC_LBits15_8 ((u32)0x02000000) /* Mask MAC Address low reg bits [15:8] */
#define ETH_MACA1HR_MBC_LBits7_0 ((u32)0x01000000) /* Mask MAC Address low reg bits [7:0] */
#define ETH_MACA1HR_MACA1H ((u32)0x0000FFFF) /* MAC address1 high */
/* Bit definition for Ethernet MAC Address1 Low Register */
#define ETH_MACA1LR_MACA1L ((u32)0xFFFFFFFF) /* MAC address1 low */
/* Bit definition for Ethernet MAC Address2 High Register */
#define ETH_MACA2HR_AE ((u32)0x80000000) /* Address enable */
#define ETH_MACA2HR_SA ((u32)0x40000000) /* Source address */
#define ETH_MACA2HR_MBC ((u32)0x3F000000) /* Mask byte control */
#define ETH_MACA2HR_MBC_HBits15_8 ((u32)0x20000000) /* Mask MAC Address high reg bits [15:8] */
#define ETH_MACA2HR_MBC_HBits7_0 ((u32)0x10000000) /* Mask MAC Address high reg bits [7:0] */
#define ETH_MACA2HR_MBC_LBits31_24 ((u32)0x08000000) /* Mask MAC Address low reg bits [31:24] */
#define ETH_MACA2HR_MBC_LBits23_16 ((u32)0x04000000) /* Mask MAC Address low reg bits [23:16] */
#define ETH_MACA2HR_MBC_LBits15_8 ((u32)0x02000000) /* Mask MAC Address low reg bits [15:8] */
#define ETH_MACA2HR_MBC_LBits7_0 ((u32)0x01000000) /* Mask MAC Address low reg bits [70] */
#define ETH_MACA2HR_MACA2H ((u32)0x0000FFFF) /* MAC address1 high */
/* Bit definition for Ethernet MAC Address2 Low Register */
#define ETH_MACA2LR_MACA2L ((u32)0xFFFFFFFF) /* MAC address2 low */
/* Bit definition for Ethernet MAC Address3 High Register */
#define ETH_MACA3HR_AE ((u32)0x80000000) /* Address enable */
#define ETH_MACA3HR_SA ((u32)0x40000000) /* Source address */
#define ETH_MACA3HR_MBC ((u32)0x3F000000) /* Mask byte control */
#define ETH_MACA2HR_MBC_HBits15_8 ((u32)0x20000000) /* Mask MAC Address high reg bits [15:8] */
#define ETH_MACA2HR_MBC_HBits7_0 ((u32)0x10000000) /* Mask MAC Address high reg bits [7:0] */
#define ETH_MACA2HR_MBC_LBits31_24 ((u32)0x08000000) /* Mask MAC Address low reg bits [31:24] */
#define ETH_MACA2HR_MBC_LBits23_16 ((u32)0x04000000) /* Mask MAC Address low reg bits [23:16] */
#define ETH_MACA2HR_MBC_LBits15_8 ((u32)0x02000000) /* Mask MAC Address low reg bits [15:8] */
#define ETH_MACA2HR_MBC_LBits7_0 ((u32)0x01000000) /* Mask MAC Address low reg bits [70] */
#define ETH_MACA3HR_MACA3H ((u32)0x0000FFFF) /* MAC address3 high */
/* Bit definition for Ethernet MAC Address3 Low Register */
#define ETH_MACA3LR_MACA3L ((u32)0xFFFFFFFF) /* MAC address3 low */
/******************************************************************************/
/* Ethernet MMC Registers bits definition */
/******************************************************************************/
/* Bit definition for Ethernet MMC Contol Register */
#define ETH_MMCCR_MCF ((u32)0x00000008) /* MMC Counter Freeze */
#define ETH_MMCCR_ROR ((u32)0x00000004) /* Reset on Read */
#define ETH_MMCCR_CSR ((u32)0x00000002) /* Counter Stop Rollover */
#define ETH_MMCCR_CR ((u32)0x00000001) /* Counters Reset */
/* Bit definition for Ethernet MMC Receive Interrupt Register */
#define ETH_MMCRIR_RGUFS ((u32)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
#define ETH_MMCRIR_RFAES ((u32)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
#define ETH_MMCRIR_RFCES ((u32)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
/* Bit definition for Ethernet MMC Transmit Interrupt Register */
#define ETH_MMCTIR_TGFS ((u32)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
#define ETH_MMCTIR_TGFMSCS ((u32)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
#define ETH_MMCTIR_TGFSCS ((u32)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
#define ETH_MMCRIMR_RGUFM ((u32)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
#define ETH_MMCRIMR_RFAEM ((u32)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
#define ETH_MMCRIMR_RFCEM ((u32)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
#define ETH_MMCTIMR_TGFM ((u32)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
#define ETH_MMCTIMR_TGFMSCM ((u32)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
#define ETH_MMCTIMR_TGFSCM ((u32)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
#define ETH_MMCTGFSCCR_TGFSCC ((u32)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
#define ETH_MMCTGFMSCCR_TGFMSCC ((u32)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
#define ETH_MMCTGFCR_TGFC ((u32)0xFFFFFFFF) /* Number of good frames transmitted. */
/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
#define ETH_MMCRFCECR_RFCEC ((u32)0xFFFFFFFF) /* Number of frames received with CRC error. */
/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
#define ETH_MMCRFAECR_RFAEC ((u32)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
#define ETH_MMCRGUFCR_RGUFC ((u32)0xFFFFFFFF) /* Number of good unicast frames received. */
/******************************************************************************/
/* Ethernet PTP Registers bits definition */
/******************************************************************************/
/* Bit definition for Ethernet PTP Time Stamp Contol Register */
#define ETH_PTPTSCR_TSARU ((u32)0x00000020) /* Addend register update */
#define ETH_PTPTSCR_TSITE ((u32)0x00000010) /* Time stamp interrupt trigger enable */
#define ETH_PTPTSCR_TSSTU ((u32)0x00000008) /* Time stamp update */
#define ETH_PTPTSCR_TSSTI ((u32)0x00000004) /* Time stamp initialize */
#define ETH_PTPTSCR_TSFCU ((u32)0x00000002) /* Time stamp fine or coarse update */
#define ETH_PTPTSCR_TSE ((u32)0x00000001) /* Time stamp enable */
/* Bit definition for Ethernet PTP Sub-Second Increment Register */
#define ETH_PTPSSIR_STSSI ((u32)0x000000FF) /* System time Sub-second increment value */
/* Bit definition for Ethernet PTP Time Stamp High Register */
#define ETH_PTPTSHR_STS ((u32)0xFFFFFFFF) /* System Time second */
/* Bit definition for Ethernet PTP Time Stamp Low Register */
#define ETH_PTPTSLR_STPNS ((u32)0x80000000) /* System Time Positive or negative time */
#define ETH_PTPTSLR_STSS ((u32)0x7FFFFFFF) /* System Time sub-seconds */
/* Bit definition for Ethernet PTP Time Stamp High Update Register */
#define ETH_PTPTSHUR_TSUS ((u32)0xFFFFFFFF) /* Time stamp update seconds */
/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
#define ETH_PTPTSLUR_TSUPNS ((u32)0x80000000) /* Time stamp update Positive or negative time */
#define ETH_PTPTSLUR_TSUSS ((u32)0x7FFFFFFF) /* Time stamp update sub-seconds */
/* Bit definition for Ethernet PTP Time Stamp Addend Register */
#define ETH_PTPTSAR_TSA ((u32)0xFFFFFFFF) /* Time stamp addend */
/* Bit definition for Ethernet PTP Target Time High Register */
#define ETH_PTPTTHR_TTSH ((u32)0xFFFFFFFF) /* Target time stamp high */
/* Bit definition for Ethernet PTP Target Time Low Register */
#define ETH_PTPTTLR_TTSL ((u32)0xFFFFFFFF) /* Target time stamp low */
/******************************************************************************/
/* Ethernet DMA Registers bits definition */
/******************************************************************************/
/* Bit definition for Ethernet DMA Bus Mode Register */
#define ETH_DMABMR_AAB ((u32)0x02000000) /* Address-Aligned beats */
#define ETH_DMABMR_FPM ((u32)0x01000000) /* 4xPBL mode */
#define ETH_DMABMR_USP ((u32)0x00800000) /* Use separate PBL */
#define ETH_DMABMR_RDP ((u32)0x007E0000) /* RxDMA PBL */
/* Values to be confirmed: maybe they are inversed */
#define ETH_DMABMR_RDP_1Beat ((u32)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
#define ETH_DMABMR_RDP_2Beat ((u32)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
#define ETH_DMABMR_RDP_4Beat ((u32)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
#define ETH_DMABMR_RDP_8Beat ((u32)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
#define ETH_DMABMR_RDP_16Beat ((u32)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
#define ETH_DMABMR_RDP_32Beat ((u32)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
#define ETH_DMABMR_RDP_4xPBL_4Beat ((u32)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
#define ETH_DMABMR_RDP_4xPBL_8Beat ((u32)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
#define ETH_DMABMR_RDP_4xPBL_16Beat ((u32)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
#define ETH_DMABMR_RDP_4xPBL_32Beat ((u32)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
#define ETH_DMABMR_RDP_4xPBL_64Beat ((u32)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
#define ETH_DMABMR_RDP_4xPBL_128Beat ((u32)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
#define ETH_DMABMR_FB ((u32)0x00010000) /* Fixed Burst */
#define ETH_DMABMR_RTPR ((u32)0x0000C000) /* Rx Tx priority ratio */
#define ETH_DMABMR_RTPR_1_1 ((u32)0x00000000) /* Rx Tx priority ratio */
#define ETH_DMABMR_RTPR_2_1 ((u32)0x00004000) /* Rx Tx priority ratio */
#define ETH_DMABMR_RTPR_3_1 ((u32)0x00008000) /* Rx Tx priority ratio */
#define ETH_DMABMR_RTPR_4_1 ((u32)0x0000C000) /* Rx Tx priority ratio */
#define ETH_DMABMR_PBL ((u32)0x00003F00) /* Programmable burst length */
/* Values to be confirmed: maybe they are inversed */
#define ETH_DMABMR_PBL_1Beat ((u32)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
#define ETH_DMABMR_PBL_2Beat ((u32)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
#define ETH_DMABMR_PBL_4Beat ((u32)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
#define ETH_DMABMR_PBL_8Beat ((u32)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
#define ETH_DMABMR_PBL_16Beat ((u32)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
#define ETH_DMABMR_PBL_32Beat ((u32)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
#define ETH_DMABMR_PBL_4xPBL_4Beat ((u32)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
#define ETH_DMABMR_PBL_4xPBL_8Beat ((u32)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
#define ETH_DMABMR_PBL_4xPBL_16Beat ((u32)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
#define ETH_DMABMR_PBL_4xPBL_32Beat ((u32)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
#define ETH_DMABMR_PBL_4xPBL_64Beat ((u32)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
#define ETH_DMABMR_PBL_4xPBL_128Beat ((u32)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
#define ETH_DMABMR_DSL ((u32)0x0000007C) /* Descriptor Skip Length */
#define ETH_DMABMR_DA ((u32)0x00000002) /* DMA arbitration scheme */
#define ETH_DMABMR_SR ((u32)0x00000001) /* Software reset */
/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
#define ETH_DMATPDR_TPD ((u32)0xFFFFFFFF) /* Transmit poll demand */
/* Bit definition for Ethernet DMA Receive Poll Demand Register */
#define ETH_DMARPDR_RPD ((u32)0xFFFFFFFF) /* Receive poll demand */
/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
#define ETH_DMARDLAR_SRL ((u32)0xFFFFFFFF) /* Start of receive list */
/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
#define ETH_DMATDLAR_STL ((u32)0xFFFFFFFF) /* Start of transmit list */
/* Bit definition for Ethernet DMA Status Register */
#define ETH_DMASR_TSTS ((u32)0x20000000) /* Time-stamp trigger status */
#define ETH_DMASR_PMTS ((u32)0x10000000) /* PMT status */
#define ETH_DMASR_MMCS ((u32)0x08000000) /* MMC status */
#define ETH_DMASR_EBS ((u32)0x03800000) /* Error bits status */
/* combination with EBS[2:0] for GetFlagStatus function */
#define ETH_DMASR_EBS_DescAccess ((u32)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
#define ETH_DMASR_EBS_ReadTransf ((u32)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
#define ETH_DMASR_EBS_DataTransfTx ((u32)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
#define ETH_DMASR_TPS ((u32)0x00700000) /* Transmit process state */
#define ETH_DMASR_TPS_Stopped ((u32)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
#define ETH_DMASR_TPS_Fetching ((u32)0x00100000) /* Running - fetching the Tx descriptor */
#define ETH_DMASR_TPS_Waiting ((u32)0x00200000) /* Running - waiting for status */
#define ETH_DMASR_TPS_Reading ((u32)0x00300000) /* Running - reading the data from host memory */
#define ETH_DMASR_TPS_Suspended ((u32)0x00600000) /* Suspended - Tx Descriptor unavailabe */
#define ETH_DMASR_TPS_Closing ((u32)0x00700000) /* Running - closing Rx descriptor */
#define ETH_DMASR_RPS ((u32)0x000E0000) /* Receive process state */
#define ETH_DMASR_RPS_Stopped ((u32)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
#define ETH_DMASR_RPS_Fetching ((u32)0x00020000) /* Running - fetching the Rx descriptor */
#define ETH_DMASR_RPS_Waiting ((u32)0x00060000) /* Running - waiting for packet */
#define ETH_DMASR_RPS_Suspended ((u32)0x00080000) /* Suspended - Rx Descriptor unavailable */
#define ETH_DMASR_RPS_Closing ((u32)0x000A0000) /* Running - closing descriptor */
#define ETH_DMASR_RPS_Queuing ((u32)0x000E0000) /* Running - queuing the recieve frame into host memory */
#define ETH_DMASR_NIS ((u32)0x00010000) /* Normal interrupt summary */
#define ETH_DMASR_AIS ((u32)0x00008000) /* Abnormal interrupt summary */
#define ETH_DMASR_ERS ((u32)0x00004000) /* Early receive status */
#define ETH_DMASR_FBES ((u32)0x00002000) /* Fatal bus error status */
#define ETH_DMASR_ETS ((u32)0x00000400) /* Early transmit status */
#define ETH_DMASR_RWTS ((u32)0x00000200) /* Receive watchdog timeout status */
#define ETH_DMASR_RPSS ((u32)0x00000100) /* Receive process stopped status */
#define ETH_DMASR_RBUS ((u32)0x00000080) /* Receive buffer unavailable status */
#define ETH_DMASR_RS ((u32)0x00000040) /* Receive status */
#define ETH_DMASR_TUS ((u32)0x00000020) /* Transmit underflow status */
#define ETH_DMASR_ROS ((u32)0x00000010) /* Receive overflow status */
#define ETH_DMASR_TJTS ((u32)0x00000008) /* Transmit jabber timeout status */
#define ETH_DMASR_TBUS ((u32)0x00000004) /* Transmit buffer unavailable status */
#define ETH_DMASR_TPSS ((u32)0x00000002) /* Transmit process stopped status */
#define ETH_DMASR_TS ((u32)0x00000001) /* Transmit status */
/* Bit definition for Ethernet DMA Operation Mode Register */
#define ETH_DMAOMR_DTCEFD ((u32)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
#define ETH_DMAOMR_RSF ((u32)0x02000000) /* Receive store and forward */
#define ETH_DMAOMR_DFRF ((u32)0x01000000) /* Disable flushing of received frames */
#define ETH_DMAOMR_TSF ((u32)0x00200000) /* Transmit store and forward */
#define ETH_DMAOMR_FTF ((u32)0x00100000) /* Flush transmit FIFO */
#define ETH_DMAOMR_TTC ((u32)0x0001C000) /* Transmit threshold control */
#define ETH_DMAOMR_TTC_64Bytes ((u32)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
#define ETH_DMAOMR_TTC_128Bytes ((u32)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
#define ETH_DMAOMR_TTC_192Bytes ((u32)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
#define ETH_DMAOMR_TTC_256Bytes ((u32)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
#define ETH_DMAOMR_TTC_40Bytes ((u32)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
#define ETH_DMAOMR_TTC_32Bytes ((u32)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
#define ETH_DMAOMR_TTC_24Bytes ((u32)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
#define ETH_DMAOMR_TTC_16Bytes ((u32)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
#define ETH_DMAOMR_ST ((u32)0x00002000) /* Start/stop transmission command */
#define ETH_DMAOMR_FEF ((u32)0x00000080) /* Forward error frames */
#define ETH_DMAOMR_FUGF ((u32)0x00000040) /* Forward undersized good frames */
#define ETH_DMAOMR_RTC ((u32)0x00000018) /* receive threshold control */
#define ETH_DMAOMR_RTC_64Bytes ((u32)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
#define ETH_DMAOMR_RTC_32Bytes ((u32)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
#define ETH_DMAOMR_RTC_96Bytes ((u32)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
#define ETH_DMAOMR_RTC_128Bytes ((u32)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
#define ETH_DMAOMR_OSF ((u32)0x00000004) /* operate on second frame */
#define ETH_DMAOMR_SR ((u32)0x00000002) /* Start/stop receive */
/* Bit definition for Ethernet DMA Interrupt Enable Register */
#define ETH_DMAIER_NISE ((u32)0x00010000) /* Normal interrupt summary enable */
#define ETH_DMAIER_AISE ((u32)0x00008000) /* Abnormal interrupt summary enable */
#define ETH_DMAIER_ERIE ((u32)0x00004000) /* Early receive interrupt enable */
#define ETH_DMAIER_FBEIE ((u32)0x00002000) /* Fatal bus error interrupt enable */
#define ETH_DMAIER_ETIE ((u32)0x00000400) /* Early transmit interrupt enable */
#define ETH_DMAIER_RWTIE ((u32)0x00000200) /* Receive watchdog timeout interrupt enable */
#define ETH_DMAIER_RPSIE ((u32)0x00000100) /* Receive process stopped interrupt enable */
#define ETH_DMAIER_RBUIE ((u32)0x00000080) /* Receive buffer unavailable interrupt enable */
#define ETH_DMAIER_RIE ((u32)0x00000040) /* Receive interrupt enable */
#define ETH_DMAIER_TUIE ((u32)0x00000020) /* Transmit Underflow interrupt enable */
#define ETH_DMAIER_ROIE ((u32)0x00000010) /* Receive Overflow interrupt enable */
#define ETH_DMAIER_TJTIE ((u32)0x00000008) /* Transmit jabber timeout interrupt enable */
#define ETH_DMAIER_TBUIE ((u32)0x00000004) /* Transmit buffer unavailable interrupt enable */
#define ETH_DMAIER_TPSIE ((u32)0x00000002) /* Transmit process stopped interrupt enable */
#define ETH_DMAIER_TIE ((u32)0x00000001) /* Transmit interrupt enable */
/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
#define ETH_DMAMFBOCR_OFOC ((u32)0x10000000) /* Overflow bit for FIFO overflow counter */
#define ETH_DMAMFBOCR_MFA ((u32)0x0FFE0000) /* Number of frames missed by the application */
#define ETH_DMAMFBOCR_OMFC ((u32)0x00010000) /* Overflow bit for missed frame counter */
#define ETH_DMAMFBOCR_MFC ((u32)0x0000FFFF) /* Number of frames missed by the controller */
/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
#define ETH_DMACHTDR_HTDAP ((u32)0xFFFFFFFF) /* Host transmit descriptor address pointer */
/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
#define ETH_DMACHRDR_HRDAP ((u32)0xFFFFFFFF) /* Host receive descriptor address pointer */
/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
#define ETH_DMACHTBAR_HTBAP ((u32)0xFFFFFFFF) /* Host transmit buffer address pointer */
/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
#define ETH_DMACHRBAR_HRBAP ((u32)0xFFFFFFFF) /* Host receive buffer address pointer */
/******************************************************************************/
/* Macros */
/******************************************************************************/
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
/* ETHERNET registers base address */
#define ETH_BASE ((u32)0x40028000)
#define ETH_MAC_BASE (ETH_BASE)
#define ETH_MMC_BASE (ETH_BASE + 0x0100)
#define ETH_PTP_BASE (ETH_BASE + 0x0700)
#define ETH_DMA_BASE (ETH_BASE + 0x1000)
/******************************************************************************/
/* Peripheral declaration */
/******************************************************************************/
/*------------------------ Non Debug Mode ------------------------------------*/
#ifndef ETH_DEBUG
#ifdef _ETH_MAC
#define ETH_MAC ((ETH_MAC_TypeDef *) ETH_MAC_BASE)
#endif /*_ETH_MAC */
#ifdef _ETH_MMC
#define ETH_MMC ((ETH_MMC_TypeDef *) ETH_MMC_BASE)
#endif /*_ETH_MMC */
#ifdef _ETH_PTP
#define ETH_PTP ((ETH_PTP_TypeDef *) ETH_PTP_BASE)
#endif /*_ETH_PTP */
#ifdef _ETH_DMA
#define ETH_DMA ((ETH_DMA_TypeDef *) ETH_DMA_BASE)
#endif /*_ETH_DMA */
/*------------------------ Debug Mode ----------------------------------------*/
#else /* ETH_DEBUG */
#ifdef _ETH_MAC
EXT ETH_MAC_TypeDef *ETH_MAC;
#endif /*_ETH_MAC */
#ifdef _ETH_MMC
EXT ETH_MMC_TypeDef *ETH_MMC;
#endif /*_ETH_MMC */
#ifdef _ETH_PTP
EXT ETH_PTP_TypeDef *ETH_PTP;
#endif /*_ETH_PTP */
#ifdef _ETH_DMA
EXT ETH_DMA_TypeDef *ETH_DMA;
#endif /*_ETH_DMA */
#endif /* ETH_DEBUG */
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
#endif /* __STM32FXXX_ETH_MAP_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth_map.h | C | oos | 37,554 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_type.h
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file contains all the common data types used for the
* STM32F10x firmware library.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_TYPE_H
#define __STM32F10x_TYPE_H
/* Includes ------------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
typedef signed long s32;
typedef signed short s16;
typedef signed char s8;
typedef volatile signed long vs32;
typedef volatile signed short vs16;
typedef volatile signed char vs8;
typedef unsigned long u32;
typedef unsigned short u16;
typedef unsigned char u8;
typedef unsigned long const uc32; /* Read Only */
typedef unsigned short const uc16; /* Read Only */
typedef unsigned char const uc8; /* Read Only */
typedef volatile unsigned long vu32;
typedef volatile unsigned short vu16;
typedef volatile unsigned char vu8;
typedef volatile unsigned long const vuc32; /* Read Only */
typedef volatile unsigned short const vuc16; /* Read Only */
typedef volatile unsigned char const vuc8; /* Read Only */
typedef enum {FALSE = 0, TRUE = !FALSE} bool;
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) ((STATE == DISABLE) || (STATE == ENABLE))
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
#define U8_MAX ((u8)255)
#define S8_MAX ((s8)127)
#define S8_MIN ((s8)-128)
#define U16_MAX ((u16)65535u)
#define S16_MAX ((s16)32767)
#define S16_MIN ((s16)-32768)
#define U32_MAX ((u32)4294967295uL)
#define S32_MAX ((s32)2147483647)
#define S32_MIN ((s32)2147483648uL)
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
#endif /* __STM32F10x_TYPE_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_type.h | C | oos | 3,169 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_bkp.h
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file contains all the functions prototypes for the
* BKP firmware library.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_BKP_H
#define __STM32F10x_BKP_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Tamper Pin active level*/
#define BKP_TamperPinLevel_High ((u16)0x0000)
#define BKP_TamperPinLevel_Low ((u16)0x0001)
#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) ((LEVEL == BKP_TamperPinLevel_High) || \
(LEVEL == BKP_TamperPinLevel_Low))
/* Data Backup Register */
#define BKP_DR1 ((u16)0x0004)
#define BKP_DR2 ((u16)0x0008)
#define BKP_DR3 ((u16)0x000C)
#define BKP_DR4 ((u16)0x0010)
#define BKP_DR5 ((u16)0x0014)
#define BKP_DR6 ((u16)0x0018)
#define BKP_DR7 ((u16)0x001C)
#define BKP_DR8 ((u16)0x0020)
#define BKP_DR9 ((u16)0x0024)
#define BKP_DR10 ((u16)0x0028)
#define IS_BKP_DR(DR) ((DR == BKP_DR1) || (DR == BKP_DR2) || (DR == BKP_DR3) || \
(DR == BKP_DR4) || (DR == BKP_DR5) || (DR == BKP_DR6) || \
(DR == BKP_DR7) || (DR == BKP_DR8) || (DR == BKP_DR9) || \
(DR == BKP_DR10))
#define IS_BKP_CALIBRATION_VALUE(VALUE) (VALUE <= 0x7F)
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void BKP_DeInit(void);
void BKP_TamperPinLevelConfig(u16 BKP_TamperPinLevel);
void BKP_TamperPinCmd(FunctionalState NewState);
void BKP_ITConfig(FunctionalState NewState);
void BKP_RTCCalibrationClockOutputCmd(FunctionalState NewState);
void BKP_SetRTCCalibrationValue(u8 CalibrationValue);
void BKP_WriteBackupRegister(u16 BKP_DR, u16 Data);
u16 BKP_ReadBackupRegister(u16 BKP_DR);
FlagStatus BKP_GetFlagStatus(void);
void BKP_ClearFlag(void);
ITStatus BKP_GetITStatus(void);
void BKP_ClearITPendingBit(void);
#endif /* __STM32F10x_BKP_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_bkp.h | C | oos | 3,506 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_dma.h
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file contains all the functions prototypes for the
* DMA firmware library.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_DMA_H
#define __STM32F10x_DMA_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* DMA Init structure definition */
typedef struct
{
u32 DMA_PeripheralBaseAddr;
u32 DMA_MemoryBaseAddr;
u32 DMA_DIR;
u32 DMA_BufferSize;
u32 DMA_PeripheralInc;
u32 DMA_MemoryInc;
u32 DMA_PeripheralDataSize;
u32 DMA_MemoryDataSize;
u32 DMA_Mode;
u32 DMA_Priority;
u32 DMA_M2M;
}DMA_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/* DMA data transfer direction -----------------------------------------------*/
#define DMA_DIR_PeripheralDST ((u32)0x00000010)
#define DMA_DIR_PeripheralSRC ((u32)0x00000000)
#define IS_DMA_DIR(DIR) ((DIR == DMA_DIR_PeripheralDST) || \
(DIR == DMA_DIR_PeripheralSRC))
/* DMA peripheral incremented mode -------------------------------------------*/
#define DMA_PeripheralInc_Enable ((u32)0x00000040)
#define DMA_PeripheralInc_Disable ((u32)0x00000000)
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) ((STATE == DMA_PeripheralInc_Enable) || \
(STATE == DMA_PeripheralInc_Disable))
/* DMA memory incremented mode -----------------------------------------------*/
#define DMA_MemoryInc_Enable ((u32)0x00000080)
#define DMA_MemoryInc_Disable ((u32)0x00000000)
#define IS_DMA_MEMORY_INC_STATE(STATE) ((STATE == DMA_MemoryInc_Enable) || \
(STATE == DMA_MemoryInc_Disable))
/* DMA peripheral data size --------------------------------------------------*/
#define DMA_PeripheralDataSize_Byte ((u32)0x00000000)
#define DMA_PeripheralDataSize_HalfWord ((u32)0x00000100)
#define DMA_PeripheralDataSize_Word ((u32)0x00000200)
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) ((SIZE == DMA_PeripheralDataSize_Byte) || \
(SIZE == DMA_PeripheralDataSize_HalfWord) || \
(SIZE == DMA_PeripheralDataSize_Word))
/* DMA memory data size ------------------------------------------------------*/
#define DMA_MemoryDataSize_Byte ((u32)0x00000000)
#define DMA_MemoryDataSize_HalfWord ((u32)0x00000400)
#define DMA_MemoryDataSize_Word ((u32)0x00000800)
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) ((SIZE == DMA_MemoryDataSize_Byte) || \
(SIZE == DMA_MemoryDataSize_HalfWord) || \
(SIZE == DMA_MemoryDataSize_Word))
/* DMA circular/normal mode --------------------------------------------------*/
#define DMA_Mode_Circular ((u32)0x00000020)
#define DMA_Mode_Normal ((u32)0x00000000)
#define IS_DMA_MODE(MODE) ((MODE == DMA_Mode_Circular) || (MODE == DMA_Mode_Normal))
/* DMA priority level --------------------------------------------------------*/
#define DMA_Priority_VeryHigh ((u32)0x00003000)
#define DMA_Priority_High ((u32)0x00002000)
#define DMA_Priority_Medium ((u32)0x00001000)
#define DMA_Priority_Low ((u32)0x00000000)
#define IS_DMA_PRIORITY(PRIORITY) ((PRIORITY == DMA_Priority_VeryHigh) || \
(PRIORITY == DMA_Priority_High) || \
(PRIORITY == DMA_Priority_Medium) || \
(PRIORITY == DMA_Priority_Low))
/* DMA memory to memory ------------------------------------------------------*/
#define DMA_M2M_Enable ((u32)0x00004000)
#define DMA_M2M_Disable ((u32)0x00000000)
#define IS_DMA_M2M_STATE(STATE) ((STATE == DMA_M2M_Enable) || (STATE == DMA_M2M_Disable))
/* DMA interrupts definition -------------------------------------------------*/
#define DMA_IT_TC ((u32)0x00000002)
#define DMA_IT_HT ((u32)0x00000004)
#define DMA_IT_TE ((u32)0x00000008)
#define IS_DMA_CONFIG_IT(IT) (((IT & 0xFFFFFFF1) == 0x00) && (IT != 0x00))
#define DMA_IT_GL1 ((u32)0x00000001)
#define DMA_IT_TC1 ((u32)0x00000002)
#define DMA_IT_HT1 ((u32)0x00000004)
#define DMA_IT_TE1 ((u32)0x00000008)
#define DMA_IT_GL2 ((u32)0x00000010)
#define DMA_IT_TC2 ((u32)0x00000020)
#define DMA_IT_HT2 ((u32)0x00000040)
#define DMA_IT_TE2 ((u32)0x00000080)
#define DMA_IT_GL3 ((u32)0x00000100)
#define DMA_IT_TC3 ((u32)0x00000200)
#define DMA_IT_HT3 ((u32)0x00000400)
#define DMA_IT_TE3 ((u32)0x00000800)
#define DMA_IT_GL4 ((u32)0x00001000)
#define DMA_IT_TC4 ((u32)0x00002000)
#define DMA_IT_HT4 ((u32)0x00004000)
#define DMA_IT_TE4 ((u32)0x00008000)
#define DMA_IT_GL5 ((u32)0x00010000)
#define DMA_IT_TC5 ((u32)0x00020000)
#define DMA_IT_HT5 ((u32)0x00040000)
#define DMA_IT_TE5 ((u32)0x00080000)
#define DMA_IT_GL6 ((u32)0x00100000)
#define DMA_IT_TC6 ((u32)0x00200000)
#define DMA_IT_HT6 ((u32)0x00400000)
#define DMA_IT_TE6 ((u32)0x00800000)
#define DMA_IT_GL7 ((u32)0x01000000)
#define DMA_IT_TC7 ((u32)0x02000000)
#define DMA_IT_HT7 ((u32)0x04000000)
#define DMA_IT_TE7 ((u32)0x08000000)
#define IS_DMA_CLEAR_IT(IT) (((IT & 0xF0000000) == 0x00) && (IT != 0x00))
#define IS_DMA_GET_IT(IT) ((IT == DMA_IT_GL1) || (IT == DMA_IT_TC1) || \
(IT == DMA_IT_HT1) || (IT == DMA_IT_TE1) || \
(IT == DMA_IT_GL2) || (IT == DMA_IT_TC2) || \
(IT == DMA_IT_HT2) || (IT == DMA_IT_TE2) || \
(IT == DMA_IT_GL3) || (IT == DMA_IT_TC3) || \
(IT == DMA_IT_HT3) || (IT == DMA_IT_TE3) || \
(IT == DMA_IT_GL4) || (IT == DMA_IT_TC4) || \
(IT == DMA_IT_HT4) || (IT == DMA_IT_TE4) || \
(IT == DMA_IT_GL5) || (IT == DMA_IT_TC5) || \
(IT == DMA_IT_HT5) || (IT == DMA_IT_TE5) || \
(IT == DMA_IT_GL6) || (IT == DMA_IT_TC6) || \
(IT == DMA_IT_HT6) || (IT == DMA_IT_TE6) || \
(IT == DMA_IT_GL7) || (IT == DMA_IT_TC7) || \
(IT == DMA_IT_HT7) || (IT == DMA_IT_TE7))
/* DMA flags definition ------------------------------------------------------*/
#define DMA_FLAG_GL1 ((u32)0x00000001)
#define DMA_FLAG_TC1 ((u32)0x00000002)
#define DMA_FLAG_HT1 ((u32)0x00000004)
#define DMA_FLAG_TE1 ((u32)0x00000008)
#define DMA_FLAG_GL2 ((u32)0x00000010)
#define DMA_FLAG_TC2 ((u32)0x00000020)
#define DMA_FLAG_HT2 ((u32)0x00000040)
#define DMA_FLAG_TE2 ((u32)0x00000080)
#define DMA_FLAG_GL3 ((u32)0x00000100)
#define DMA_FLAG_TC3 ((u32)0x00000200)
#define DMA_FLAG_HT3 ((u32)0x00000400)
#define DMA_FLAG_TE3 ((u32)0x00000800)
#define DMA_FLAG_GL4 ((u32)0x00001000)
#define DMA_FLAG_TC4 ((u32)0x00002000)
#define DMA_FLAG_HT4 ((u32)0x00004000)
#define DMA_FLAG_TE4 ((u32)0x00008000)
#define DMA_FLAG_GL5 ((u32)0x00010000)
#define DMA_FLAG_TC5 ((u32)0x00020000)
#define DMA_FLAG_HT5 ((u32)0x00040000)
#define DMA_FLAG_TE5 ((u32)0x00080000)
#define DMA_FLAG_GL6 ((u32)0x00100000)
#define DMA_FLAG_TC6 ((u32)0x00200000)
#define DMA_FLAG_HT6 ((u32)0x00400000)
#define DMA_FLAG_TE6 ((u32)0x00800000)
#define DMA_FLAG_GL7 ((u32)0x01000000)
#define DMA_FLAG_TC7 ((u32)0x02000000)
#define DMA_FLAG_HT7 ((u32)0x04000000)
#define DMA_FLAG_TE7 ((u32)0x08000000)
#define IS_DMA_CLEAR_FLAG(FLAG) (((FLAG & 0xF0000000) == 0x00) && (FLAG != 0x00))
#define IS_DMA_GET_FLAG(FLAG) ((FLAG == DMA_FLAG_GL1) || (FLAG == DMA_FLAG_TC1) || \
(FLAG == DMA_FLAG_HT1) || (FLAG == DMA_FLAG_TE1) || \
(FLAG == DMA_FLAG_GL2) || (FLAG == DMA_FLAG_TC2) || \
(FLAG == DMA_FLAG_HT2) || (FLAG == DMA_FLAG_TE2) || \
(FLAG == DMA_FLAG_GL3) || (FLAG == DMA_FLAG_TC3) || \
(FLAG == DMA_FLAG_HT3) || (FLAG == DMA_FLAG_TE3) || \
(FLAG == DMA_FLAG_GL4) || (FLAG == DMA_FLAG_TC4) || \
(FLAG == DMA_FLAG_HT4) || (FLAG == DMA_FLAG_TE4) || \
(FLAG == DMA_FLAG_GL5) || (FLAG == DMA_FLAG_TC5) || \
(FLAG == DMA_FLAG_HT5) || (FLAG == DMA_FLAG_TE5) || \
(FLAG == DMA_FLAG_GL6) || (FLAG == DMA_FLAG_TC6) || \
(FLAG == DMA_FLAG_HT6) || (FLAG == DMA_FLAG_TE6) || \
(FLAG == DMA_FLAG_GL7) || (FLAG == DMA_FLAG_TC7) || \
(FLAG == DMA_FLAG_HT7) || (FLAG == DMA_FLAG_TE7))
/* DMA Buffer Size -----------------------------------------------------------*/
#define IS_DMA_BUFFER_SIZE(SIZE) ((SIZE >= 0x1) && (SIZE < 0x10000))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void DMA_DeInit(DMA_Channel_TypeDef* DMA_Channelx);
void DMA_Init(DMA_Channel_TypeDef* DMA_Channelx, DMA_InitTypeDef* DMA_InitStruct);
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
void DMA_Cmd(DMA_Channel_TypeDef* DMA_Channelx, FunctionalState NewState);
void DMA_ITConfig(DMA_Channel_TypeDef* DMA_Channelx, u32 DMA_IT, FunctionalState NewState);
u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMA_Channelx);
FlagStatus DMA_GetFlagStatus(u32 DMA_FLAG);
void DMA_ClearFlag(u32 DMA_FLAG);
ITStatus DMA_GetITStatus(u32 DMA_IT);
void DMA_ClearITPendingBit(u32 DMA_IT);
#endif /*__STM32F10x_DMA_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_dma.h | C | oos | 12,531 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_i2c.h
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file contains all the functions prototypes for the
* I2C firmware library.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_I2C_H
#define __STM32F10x_I2C_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* I2C Init structure definition */
typedef struct
{
u16 I2C_Mode;
u16 I2C_DutyCycle;
u16 I2C_OwnAddress1;
u16 I2C_Ack;
u16 I2C_AcknowledgedAddress;
u32 I2C_ClockSpeed;
}I2C_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/* I2C modes */
#define I2C_Mode_I2C ((u16)0x0000)
#define I2C_Mode_SMBusDevice ((u16)0x0002)
#define I2C_Mode_SMBusHost ((u16)0x000A)
#define IS_I2C_MODE(MODE) ((MODE == I2C_Mode_I2C) || \
(MODE == I2C_Mode_SMBusDevice) || \
(MODE == I2C_Mode_SMBusHost))
/* I2C duty cycle in fast mode */
#define I2C_DutyCycle_16_9 ((u16)0x4000)
#define I2C_DutyCycle_2 ((u16)0xBFFF)
#define IS_I2C_DUTY_CYCLE(CYCLE) ((CYCLE == I2C_DutyCycle_16_9) || \
(CYCLE == I2C_DutyCycle_2))
/* I2C cknowledgementy */
#define I2C_Ack_Enable ((u16)0x0400)
#define I2C_Ack_Disable ((u16)0x0000)
#define IS_I2C_ACK_STATE(STATE) ((STATE == I2C_Ack_Enable) || \
(STATE == I2C_Ack_Disable))
/* I2C transfer direction */
#define I2C_Direction_Transmitter ((u8)0x00)
#define I2C_Direction_Receiver ((u8)0x01)
#define IS_I2C_DIRECTION(DIRECTION) ((DIRECTION == I2C_Direction_Transmitter) || \
(DIRECTION == I2C_Direction_Receiver))
/* I2C acknowledged address defines */
#define I2C_AcknowledgedAddress_7bit ((u16)0x4000)
#define I2C_AcknowledgedAddress_10bit ((u16)0xC000)
#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) ((ADDRESS == I2C_AcknowledgedAddress_7bit) || \
(ADDRESS == I2C_AcknowledgedAddress_10bit))
/* I2C registers */
#define I2C_Register_CR1 ((u8)0x00)
#define I2C_Register_CR2 ((u8)0x04)
#define I2C_Register_OAR1 ((u8)0x08)
#define I2C_Register_OAR2 ((u8)0x0C)
#define I2C_Register_DR ((u8)0x10)
#define I2C_Register_SR1 ((u8)0x14)
#define I2C_Register_SR2 ((u8)0x18)
#define I2C_Register_CCR ((u8)0x1C)
#define I2C_Register_TRISE ((u8)0x20)
#define IS_I2C_REGISTER(REGISTER) ((REGISTER == I2C_Register_CR1) || \
(REGISTER == I2C_Register_CR2) || \
(REGISTER == I2C_Register_OAR1) || \
(REGISTER == I2C_Register_OAR2) || \
(REGISTER == I2C_Register_DR) || \
(REGISTER == I2C_Register_SR1) || \
(REGISTER == I2C_Register_SR2) || \
(REGISTER == I2C_Register_CCR) || \
(REGISTER == I2C_Register_TRISE))
/* I2C SMBus alert pin level */
#define I2C_SMBusAlert_Low ((u16)0x2000)
#define I2C_SMBusAlert_High ((u16)0xCFFF)
#define IS_I2C_SMBUS_ALERT(ALERT) ((ALERT == I2C_SMBusAlert_Low) || \
(ALERT == I2C_SMBusAlert_High))
/* I2C PEC position */
#define I2C_PECPosition_Next ((u16)0x0800)
#define I2C_PECPosition_Current ((u16)0xF7FF)
#define IS_I2C_PEC_POSITION(POSITION) ((POSITION == I2C_PECPosition_Next) || \
(POSITION == I2C_PECPosition_Current))
/* I2C interrupts definition */
#define I2C_IT_BUF ((u16)0x0400)
#define I2C_IT_EVT ((u16)0x0200)
#define I2C_IT_ERR ((u16)0x0100)
#define IS_I2C_CONFIG_IT(IT) (((IT & (u16)0xF8FF) == 0x00) && (IT != 0x00))
/* I2C interrupts definition */
#define I2C_IT_SMBALERT ((u32)0x10008000)
#define I2C_IT_TIMEOUT ((u32)0x10004000)
#define I2C_IT_PECERR ((u32)0x10001000)
#define I2C_IT_OVR ((u32)0x10000800)
#define I2C_IT_AF ((u32)0x10000400)
#define I2C_IT_ARLO ((u32)0x10000200)
#define I2C_IT_BERR ((u32)0x10000100)
#define I2C_IT_TXE ((u32)0x00000080)
#define I2C_IT_RXNE ((u32)0x00000040)
#define I2C_IT_STOPF ((u32)0x60000010)
#define I2C_IT_ADD10 ((u32)0x20000008)
#define I2C_IT_BTF ((u32)0x60000004)
#define I2C_IT_ADDR ((u32)0xA0000002)
#define I2C_IT_SB ((u32)0x20000001)
#define IS_I2C_CLEAR_IT(IT) ((IT == I2C_IT_SMBALERT) || (IT == I2C_IT_TIMEOUT) || \
(IT == I2C_IT_PECERR) || (IT == I2C_IT_OVR) || \
(IT == I2C_IT_AF) || (IT == I2C_IT_ARLO) || \
(IT == I2C_IT_BERR) || (IT == I2C_IT_STOPF) || \
(IT == I2C_IT_ADD10) || (IT == I2C_IT_BTF) || \
(IT == I2C_IT_ADDR) || (IT == I2C_IT_SB))
#define IS_I2C_GET_IT(IT) ((IT == I2C_IT_SMBALERT) || (IT == I2C_IT_TIMEOUT) || \
(IT == I2C_IT_PECERR) || (IT == I2C_IT_OVR) || \
(IT == I2C_IT_AF) || (IT == I2C_IT_ARLO) || \
(IT == I2C_IT_BERR) || (IT == I2C_IT_TXE) || \
(IT == I2C_IT_RXNE) || (IT == I2C_IT_STOPF) || \
(IT == I2C_IT_ADD10) || (IT == I2C_IT_BTF) || \
(IT == I2C_IT_ADDR) || (IT == I2C_IT_SB))
/* I2C flags definition */
#define I2C_FLAG_DUALF ((u32)0x00800000)
#define I2C_FLAG_SMBHOST ((u32)0x00400000)
#define I2C_FLAG_SMBDEFAULT ((u32)0x00200000)
#define I2C_FLAG_GENCALL ((u32)0x00100000)
#define I2C_FLAG_TRA ((u32)0x00040000)
#define I2C_FLAG_BUSY ((u32)0x00020000)
#define I2C_FLAG_MSL ((u32)0x00010000)
#define I2C_FLAG_SMBALERT ((u32)0x10008000)
#define I2C_FLAG_TIMEOUT ((u32)0x10004000)
#define I2C_FLAG_PECERR ((u32)0x10001000)
#define I2C_FLAG_OVR ((u32)0x10000800)
#define I2C_FLAG_AF ((u32)0x10000400)
#define I2C_FLAG_ARLO ((u32)0x10000200)
#define I2C_FLAG_BERR ((u32)0x10000100)
#define I2C_FLAG_TXE ((u32)0x00000080)
#define I2C_FLAG_RXNE ((u32)0x00000040)
#define I2C_FLAG_STOPF ((u32)0x60000010)
#define I2C_FLAG_ADD10 ((u32)0x20000008)
#define I2C_FLAG_BTF ((u32)0x60000004)
#define I2C_FLAG_ADDR ((u32)0xA0000002)
#define I2C_FLAG_SB ((u32)0x20000001)
#define IS_I2C_CLEAR_FLAG(FLAG) ((FLAG == I2C_FLAG_SMBALERT) || (FLAG == I2C_FLAG_TIMEOUT) || \
(FLAG == I2C_FLAG_PECERR) || (FLAG == I2C_FLAG_OVR) || \
(FLAG == I2C_FLAG_AF) || (FLAG == I2C_FLAG_ARLO) || \
(FLAG == I2C_FLAG_BERR) || (FLAG == I2C_FLAG_STOPF) || \
(FLAG == I2C_FLAG_ADD10) || (FLAG == I2C_FLAG_BTF) || \
(FLAG == I2C_FLAG_ADDR) || (FLAG == I2C_FLAG_SB))
#define IS_I2C_GET_FLAG(FLAG) ((FLAG == I2C_FLAG_DUALF) || (FLAG == I2C_FLAG_SMBHOST) || \
(FLAG == I2C_FLAG_SMBDEFAULT) || (FLAG == I2C_FLAG_GENCALL) || \
(FLAG == I2C_FLAG_TRA) || (FLAG == I2C_FLAG_BUSY) || \
(FLAG == I2C_FLAG_MSL) || (FLAG == I2C_FLAG_SMBALERT) || \
(FLAG == I2C_FLAG_TIMEOUT) || (FLAG == I2C_FLAG_PECERR) || \
(FLAG == I2C_FLAG_OVR) || (FLAG == I2C_FLAG_AF) || \
(FLAG == I2C_FLAG_ARLO) || (FLAG == I2C_FLAG_BERR) || \
(FLAG == I2C_FLAG_TXE) || (FLAG == I2C_FLAG_RXNE) || \
(FLAG == I2C_FLAG_STOPF) || (FLAG == I2C_FLAG_ADD10) || \
(FLAG == I2C_FLAG_BTF) || (FLAG == I2C_FLAG_ADDR) || \
(FLAG == I2C_FLAG_SB))
/* I2C Events */
/* EV1 */
#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((u32)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((u32)0x00020002) /* BUSY and ADDR flags */
#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((u32)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((u32)0x00820000) /* DUALF and BUSY flags */
#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((u32)0x00120000) /* GENCALL and BUSY flags */
/* EV2 */
#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((u32)0x00020040) /* BUSY and RXNE flags */
/* EV3 */
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((u32)0x00060084) /* TRA, BUSY, TXE and BTF flags */
/* EV4 */
#define I2C_EVENT_SLAVE_STOP_DETECTED ((u32)0x00000010) /* STOPF flag */
/* EV5 */
#define I2C_EVENT_MASTER_MODE_SELECT ((u32)0x00030001) /* BUSY, MSL and SB flag */
/* EV6 */
#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((u32)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((u32)0x00030002) /* BUSY, MSL and ADDR flags */
/* EV7 */
#define I2C_EVENT_MASTER_BYTE_RECEIVED ((u32)0x00030040) /* BUSY, MSL and RXNE flags */
/* EV8 */
#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((u32)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
/* EV9 */
#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((u32)0x00030008) /* BUSY, MSL and ADD10 flags */
/* EV3_1 */
#define I2C_EVENT_SLAVE_ACK_FAILURE ((u32)0x00000400) /* AF flag */
#define IS_I2C_EVENT(EVENT) ((EVENT == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
(EVENT == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
(EVENT == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
(EVENT == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
(EVENT == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
(EVENT == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
(EVENT == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
(EVENT == I2C_EVENT_SLAVE_STOP_DETECTED) || \
(EVENT == I2C_EVENT_MASTER_MODE_SELECT) || \
(EVENT == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
(EVENT == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
(EVENT == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
(EVENT == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
(EVENT == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
(EVENT == I2C_EVENT_SLAVE_ACK_FAILURE))
/* I2C own address1 -----------------------------------------------------------*/
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (ADDRESS1 <= 0x3FF)
/* I2C clock speed ------------------------------------------------------------*/
#define IS_I2C_CLOCK_SPEED(SPEED) ((SPEED >= 0x1) && (SPEED <= 400000))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void I2C_DeInit(I2C_TypeDef* I2Cx);
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, u8 Address);
void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_ITConfig(I2C_TypeDef* I2Cx, u16 I2C_IT, FunctionalState NewState);
void I2C_SendData(I2C_TypeDef* I2Cx, u8 Data);
u8 I2C_ReceiveData(I2C_TypeDef* I2Cx);
void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, u8 Address, u8 I2C_Direction);
u16 I2C_ReadRegister(I2C_TypeDef* I2Cx, u8 I2C_Register);
void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, u16 I2C_SMBusAlert);
void I2C_TransmitPEC(I2C_TypeDef* I2Cx);
void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, u16 I2C_PECPosition);
void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
u8 I2C_GetPEC(I2C_TypeDef* I2Cx);
void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, u16 I2C_DutyCycle);
u32 I2C_GetLastEvent(I2C_TypeDef* I2Cx);
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, u32 I2C_EVENT);
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, u32 I2C_FLAG);
void I2C_ClearFlag(I2C_TypeDef* I2Cx, u32 I2C_FLAG);
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, u32 I2C_IT);
void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, u32 I2C_IT);
#endif /*__STM32F10x_I2C_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_i2c.h | C | oos | 15,245 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_wwdg.h
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file contains all the functions prototypes for the
* WWDG firmware library.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_WWDG_H
#define __STM32F10x_WWDG_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* WWDG Prescaler */
#define WWDG_Prescaler_1 ((u32)0x00000000)
#define WWDG_Prescaler_2 ((u32)0x00000080)
#define WWDG_Prescaler_4 ((u32)0x00000100)
#define WWDG_Prescaler_8 ((u32)0x00000180)
#define IS_WWDG_PRESCALER(PRESCALER) ((PRESCALER == WWDG_Prescaler_1) || \
(PRESCALER == WWDG_Prescaler_2) || \
(PRESCALER == WWDG_Prescaler_4) || \
(PRESCALER == WWDG_Prescaler_8))
#define IS_WWDG_WINDOW_VALUE(VALUE) (VALUE <= 0x7F)
#define IS_WWDG_COUNTER(COUNTER) ((COUNTER >= 0x40) && (COUNTER <= 0x7F))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void WWDG_DeInit(void);
void WWDG_SetPrescaler(u32 WWDG_Prescaler);
void WWDG_SetWindowValue(u8 WindowValue);
void WWDG_EnableIT(void);
void WWDG_SetCounter(u8 Counter);
void WWDG_Enable(u8 Counter);
FlagStatus WWDG_GetFlagStatus(void);
void WWDG_ClearFlag(void);
#endif /* __STM32F10x_WWDG_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_wwdg.h | C | oos | 2,730 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : spi_flash.h
* Author : MCD Application Team
* Date First Issued : 02/05/2007
* Description : Header for spi_flash.c file.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __SPI_FLASH_H
#define __SPI_FLASH_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_lib.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
#define Low 0x00 /* Chip Select line low */
#define High 0x01 /* Chip Select line high */
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/*----- High layer function -----*/
void SPI_FLASH_Init(void);
void SPI_FLASH_SectorErase(u32 SectorAddr);
void SPI_FLASH_BulkErase(void);
void SPI_FLASH_PageWrite(u8* pBuffer, u32 WriteAddr, u16 NumByteToWrite);
void SPI_FLASH_BufferWrite(u8* pBuffer, u32 WriteAddr, u16 NumByteToWrite);
void SPI_FLASH_BufferRead(u8* pBuffer, u32 ReadAddr, u16 NumByteToRead);
u32 SPI_FLASH_ReadID(void);
void SPI_FLASH_StartReadSequence(u32 ReadAddr);
/*----- Low layer function -----*/
u8 SPI_FLASH_ReadByte(void);
void SPI_FLASH_ChipSelect(u8 State);
u8 SPI_FLASH_SendByte(u8 byte);
u16 SPI_FLASH_SendHalfWord(u16 HalfWord);
void SPI_FLASH_WriteEnable(void);
void SPI_FLASH_WaitForWriteEnd(void);
#endif /* __SPI_FLASH_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/spi_flash.h | C | oos | 2,503 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_exti.h
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file contains all the functions prototypes for the
* EXTI firmware library.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_EXTI_H
#define __STM32F10x_EXTI_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* EXTI mode enumeration -----------------------------------------------------*/
typedef enum
{
EXTI_Mode_Interrupt = 0x00,
EXTI_Mode_Event = 0x04
}EXTIMode_TypeDef;
#define IS_EXTI_MODE(MODE) ((MODE == EXTI_Mode_Interrupt) || (MODE == EXTI_Mode_Event))
/* EXTI Trigger enumeration --------------------------------------------------*/
typedef enum
{
EXTI_Trigger_Rising = 0x08,
EXTI_Trigger_Falling = 0x0C,
EXTI_Trigger_Rising_Falling = 0x10
}EXTITrigger_TypeDef;
#define IS_EXTI_TRIGGER(TRIGGER) ((TRIGGER == EXTI_Trigger_Rising) || \
(TRIGGER == EXTI_Trigger_Falling) || \
(TRIGGER == EXTI_Trigger_Rising_Falling))
/* EXTI Init Structure definition --------------------------------------------*/
typedef struct
{
u32 EXTI_Line;
EXTIMode_TypeDef EXTI_Mode;
EXTITrigger_TypeDef EXTI_Trigger;
FunctionalState EXTI_LineCmd;
}EXTI_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/* EXTI Lines ----------------------------------------------------------------*/
#define EXTI_Line0 ((u32)0x00001) /* External interrupt line 0 */
#define EXTI_Line1 ((u32)0x00002) /* External interrupt line 1 */
#define EXTI_Line2 ((u32)0x00004) /* External interrupt line 2 */
#define EXTI_Line3 ((u32)0x00008) /* External interrupt line 3 */
#define EXTI_Line4 ((u32)0x00010) /* External interrupt line 4 */
#define EXTI_Line5 ((u32)0x00020) /* External interrupt line 5 */
#define EXTI_Line6 ((u32)0x00040) /* External interrupt line 6 */
#define EXTI_Line7 ((u32)0x00080) /* External interrupt line 7 */
#define EXTI_Line8 ((u32)0x00100) /* External interrupt line 8 */
#define EXTI_Line9 ((u32)0x00200) /* External interrupt line 9 */
#define EXTI_Line10 ((u32)0x00400) /* External interrupt line 10 */
#define EXTI_Line11 ((u32)0x00800) /* External interrupt line 11 */
#define EXTI_Line12 ((u32)0x01000) /* External interrupt line 12 */
#define EXTI_Line13 ((u32)0x02000) /* External interrupt line 13 */
#define EXTI_Line14 ((u32)0x04000) /* External interrupt line 14 */
#define EXTI_Line15 ((u32)0x08000) /* External interrupt line 15 */
#define EXTI_Line16 ((u32)0x10000) /* External interrupt line 16
Connected to the PVD Output */
#define EXTI_Line17 ((u32)0x20000) /* External interrupt line 17
Connected to the RTC Alarm event */
#define EXTI_Line18 ((u32)0x40000) /* External interrupt line 18
Connected to the USB Wakeup from
suspend event */
#define IS_EXTI_LINE(LINE) (((LINE & (u32)0xFFF80000) == 0x00) && (LINE != (u16)0x00))
#define IS_GET_EXTI_LINE(LINE) ((LINE == EXTI_Line0) || (LINE == EXTI_Line1) || \
(LINE == EXTI_Line2) || (LINE == EXTI_Line3) || \
(LINE == EXTI_Line4) || (LINE == EXTI_Line5) || \
(LINE == EXTI_Line6) || (LINE == EXTI_Line7) || \
(LINE == EXTI_Line8) || (LINE == EXTI_Line9) || \
(LINE == EXTI_Line10) || (LINE == EXTI_Line11) || \
(LINE == EXTI_Line12) || (LINE == EXTI_Line13) || \
(LINE == EXTI_Line14) || (LINE == EXTI_Line15) || \
(LINE == EXTI_Line16) || (LINE == EXTI_Line17) || \
(LINE == EXTI_Line18))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void EXTI_DeInit(void);
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
void EXTI_GenerateSWInterrupt(u32 EXTI_Line);
FlagStatus EXTI_GetFlagStatus(u32 EXTI_Line);
void EXTI_ClearFlag(u32 EXTI_Line);
ITStatus EXTI_GetITStatus(u32 EXTI_Line);
void EXTI_ClearITPendingBit(u32 EXTI_Line);
#endif /* __STM32F10x_EXTI_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_exti.h | C | oos | 5,848 |
/**
******************************************************************************
* @file misc.h
* @author MCD Application Team
* @version V3.0.0
* @date 04/06/2009
* @brief This file contains all the functions prototypes for the
* miscellaneous firmware library functions.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MISC_H
#define __MISC_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @addtogroup MISC
* @{
*/
/** @defgroup MISC_Exported_Types
* @{
*/
/**
* @brief NVIC Init Structure definition
*/
typedef struct
{
uint8_t NVIC_IRQChannel;
uint8_t NVIC_IRQChannelPreemptionPriority;
uint8_t NVIC_IRQChannelSubPriority;
FunctionalState NVIC_IRQChannelCmd;
} NVIC_InitTypeDef;
/**
* @}
*/
/** @defgroup MISC_Exported_Constants
* @{
*/
/** @defgroup Vector_Table_Base
* @{
*/
#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
((VECTTAB) == NVIC_VectTab_FLASH))
/**
* @}
*/
/** @defgroup System_Low_Power
* @{
*/
#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
((LP) == NVIC_LP_SLEEPDEEP) || \
((LP) == NVIC_LP_SLEEPONEXIT))
/**
* @}
*/
/** @defgroup Preemption_Priority_Group
* @{
*/
#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /* 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /* 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /* 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /* 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /* 4 bits for pre-emption priority
0 bits for subpriority */
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
((GROUP) == NVIC_PriorityGroup_1) || \
((GROUP) == NVIC_PriorityGroup_2) || \
((GROUP) == NVIC_PriorityGroup_3) || \
((GROUP) == NVIC_PriorityGroup_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0007FFFF)
/**
* @}
*/
/** @defgroup SysTick_clock_source
* @{
*/
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
((SOURCE) == SysTick_CLKSource_HCLK_Div8))
/**
* @}
*/
/**
* @}
*/
/** @defgroup MISC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup MISC_Exported_Functions
* @{
*/
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
#endif /* __MISC_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/misc.h | C | oos | 4,951 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_pwr.h
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file contains all the functions prototypes for the
* PWR firmware library.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_PWR_H
#define __STM32F10x_PWR_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* PVD detection level */
#define PWR_PVDLevel_2V2 ((u32)0x00000000)
#define PWR_PVDLevel_2V3 ((u32)0x00000020)
#define PWR_PVDLevel_2V4 ((u32)0x00000040)
#define PWR_PVDLevel_2V5 ((u32)0x00000060)
#define PWR_PVDLevel_2V6 ((u32)0x00000080)
#define PWR_PVDLevel_2V7 ((u32)0x000000A0)
#define PWR_PVDLevel_2V8 ((u32)0x000000C0)
#define PWR_PVDLevel_2V9 ((u32)0x000000E0)
#define IS_PWR_PVD_LEVEL(LEVEL) ((LEVEL == PWR_PVDLevel_2V2) || (LEVEL == PWR_PVDLevel_2V3)|| \
(LEVEL == PWR_PVDLevel_2V4) || (LEVEL == PWR_PVDLevel_2V5)|| \
(LEVEL == PWR_PVDLevel_2V6) || (LEVEL == PWR_PVDLevel_2V7)|| \
(LEVEL == PWR_PVDLevel_2V8) || (LEVEL == PWR_PVDLevel_2V9))
/* Regulator state is STOP mode */
#define PWR_Regulator_ON ((u32)0x00000000)
#define PWR_Regulator_LowPower ((u32)0x00000001)
#define IS_PWR_REGULATOR(REGULATOR) ((REGULATOR == PWR_Regulator_ON) || \
(REGULATOR == PWR_Regulator_LowPower))
/* STOP mode entry */
#define PWR_STOPEntry_WFI ((u8)0x01)
#define PWR_STOPEntry_WFE ((u8)0x02)
#define IS_PWR_STOP_ENTRY(ENTRY) ((ENTRY == PWR_STOPEntry_WFI) || (ENTRY == PWR_STOPEntry_WFE))
/* PWR Flag */
#define PWR_FLAG_WU ((u32)0x00000001)
#define PWR_FLAG_SB ((u32)0x00000002)
#define PWR_FLAG_PVDO ((u32)0x00000004)
#define IS_PWR_GET_FLAG(FLAG) ((FLAG == PWR_FLAG_WU) || (FLAG == PWR_FLAG_SB) || \
(FLAG == PWR_FLAG_PVDO))
#define IS_PWR_CLEAR_FLAG(FLAG) ((FLAG == PWR_FLAG_WU) || (FLAG == PWR_FLAG_SB))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void PWR_DeInit(void);
void PWR_BackupAccessCmd(FunctionalState NewState);
void PWR_PVDCmd(FunctionalState NewState);
void PWR_PVDLevelConfig(u32 PWR_PVDLevel);
void PWR_WakeUpPinCmd(FunctionalState NewState);
void PWR_EnterSTOPMode(u32 PWR_Regulator, u8 PWR_STOPEntry);
void PWR_EnterSTANDBYMode(void);
FlagStatus PWR_GetFlagStatus(u32 PWR_FLAG);
void PWR_ClearFlag(u32 PWR_FLAG);
#endif /* __STM32F10x_PWR_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_pwr.h | C | oos | 3,955 |
/**
******************************************************************************
* @file stm32f10x_sdio.h
* @author MCD Application Team
* @version V3.0.0
* @date 04/06/2009
* @brief This file contains all the functions prototypes for the SDIO
* firmware library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_SDIO_H
#define __STM32F10x_SDIO_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @addtogroup SDIO
* @{
*/
/** @defgroup SDIO_Exported_Types
* @{
*/
typedef struct
{
uint8_t SDIO_ClockDiv;
uint32_t SDIO_ClockEdge;
uint32_t SDIO_ClockBypass;
uint32_t SDIO_ClockPowerSave;
uint32_t SDIO_BusWide;
uint32_t SDIO_HardwareFlowControl;
} SDIO_InitTypeDef;
typedef struct
{
uint32_t SDIO_Argument;
uint32_t SDIO_CmdIndex;
uint32_t SDIO_Response;
uint32_t SDIO_Wait;
uint32_t SDIO_CPSM;
} SDIO_CmdInitTypeDef;
typedef struct
{
uint32_t SDIO_DataTimeOut;
uint32_t SDIO_DataLength;
uint32_t SDIO_DataBlockSize;
uint32_t SDIO_TransferDir;
uint32_t SDIO_TransferMode;
uint32_t SDIO_DPSM;
} SDIO_DataInitTypeDef;
/**
* @}
*/
/** @defgroup SDIO_Exported_Constants
* @{
*/
/** @defgroup SDIO_Clock_Edge
* @{
*/
#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)
#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)
#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
((EDGE) == SDIO_ClockEdge_Falling))
/**
* @}
*/
/** @defgroup SDIO_Clock_Bypass
* @{
*/
#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)
#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400)
#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
((BYPASS) == SDIO_ClockBypass_Enable))
/**
* @}
*/
/** @defgroup SDIO_Clock_Power_Save_
* @{
*/
#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)
#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200)
#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
((SAVE) == SDIO_ClockPowerSave_Enable))
/**
* @}
*/
/** @defgroup SDIO_Bus_Wide
* @{
*/
#define SDIO_BusWide_1b ((uint32_t)0x00000000)
#define SDIO_BusWide_4b ((uint32_t)0x00000800)
#define SDIO_BusWide_8b ((uint32_t)0x00001000)
#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
((WIDE) == SDIO_BusWide_8b))
/**
* @}
*/
/** @defgroup SDIO_Hardware_Flow_Control_
* @{
*/
#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)
#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)
#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
((CONTROL) == SDIO_HardwareFlowControl_Enable))
/**
* @}
*/
/** @defgroup SDIO_Power_State
* @{
*/
#define SDIO_PowerState_OFF ((uint32_t)0x00000000)
#define SDIO_PowerState_ON ((uint32_t)0x00000003)
#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
/**
* @}
*/
/** @defgroup SDIO_Interrupt_soucres
* @{
*/
#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
#define SDIO_IT_CMDREND ((uint32_t)0x00000040)
#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
#define SDIO_IT_DATAEND ((uint32_t)0x00000100)
#define SDIO_IT_STBITERR ((uint32_t)0x00000200)
#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
#define SDIO_IT_CMDACT ((uint32_t)0x00000800)
#define SDIO_IT_TXACT ((uint32_t)0x00001000)
#define SDIO_IT_RXACT ((uint32_t)0x00002000)
#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
/**
* @}
*/
/** @defgroup SDIO_Command_Index_
* @{
*/
#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
/**
* @}
*/
/** @defgroup SDIO_Response_Type
* @{
*/
#define SDIO_Response_No ((uint32_t)0x00000000)
#define SDIO_Response_Short ((uint32_t)0x00000040)
#define SDIO_Response_Long ((uint32_t)0x000000C0)
#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
((RESPONSE) == SDIO_Response_Short) || \
((RESPONSE) == SDIO_Response_Long))
/**
* @}
*/
/** @defgroup SDIO_Wait_Interrupt_State
* @{
*/
#define SDIO_Wait_No ((uint32_t)0x00000000) /* SDIO No Wait, TimeOut is enabled */
#define SDIO_Wait_IT ((uint32_t)0x00000100) /* SDIO Wait Interrupt Request */
#define SDIO_Wait_Pend ((uint32_t)0x00000200) /* SDIO Wait End of transfer */
#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
((WAIT) == SDIO_Wait_Pend))
/**
* @}
*/
/** @defgroup SDIO_CPSM_State
* @{
*/
#define SDIO_CPSM_Disable ((uint32_t)0x00000000)
#define SDIO_CPSM_Enable ((uint32_t)0x00000400)
#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
/**
* @}
*/
/** @defgroup SDIO_Response_Registers
* @{
*/
#define SDIO_RESP1 ((uint32_t)0x00000000)
#define SDIO_RESP2 ((uint32_t)0x00000004)
#define SDIO_RESP3 ((uint32_t)0x00000008)
#define SDIO_RESP4 ((uint32_t)0x0000000C)
#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
/**
* @}
*/
/** @defgroup SDIO_Data_Length
* @{
*/
#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
/**
* @}
*/
/** @defgroup SDIO_Data_Block_Size
* @{
*/
#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)
#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)
#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)
#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)
#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)
#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)
#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)
#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)
#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)
#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)
#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)
#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)
#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)
#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)
#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)
#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
((SIZE) == SDIO_DataBlockSize_2b) || \
((SIZE) == SDIO_DataBlockSize_4b) || \
((SIZE) == SDIO_DataBlockSize_8b) || \
((SIZE) == SDIO_DataBlockSize_16b) || \
((SIZE) == SDIO_DataBlockSize_32b) || \
((SIZE) == SDIO_DataBlockSize_64b) || \
((SIZE) == SDIO_DataBlockSize_128b) || \
((SIZE) == SDIO_DataBlockSize_256b) || \
((SIZE) == SDIO_DataBlockSize_512b) || \
((SIZE) == SDIO_DataBlockSize_1024b) || \
((SIZE) == SDIO_DataBlockSize_2048b) || \
((SIZE) == SDIO_DataBlockSize_4096b) || \
((SIZE) == SDIO_DataBlockSize_8192b) || \
((SIZE) == SDIO_DataBlockSize_16384b))
/**
* @}
*/
/** @defgroup SDIO_Transfer_Direction
* @{
*/
#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)
#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)
#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
((DIR) == SDIO_TransferDir_ToSDIO))
/**
* @}
*/
/** @defgroup SDIO_Transfer_Type
* @{
*/
#define SDIO_TransferMode_Block ((uint32_t)0x00000000)
#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)
#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
((MODE) == SDIO_TransferMode_Block))
/**
* @}
*/
/** @defgroup SDIO_DPSM_State
* @{
*/
#define SDIO_DPSM_Disable ((uint32_t)0x00000000)
#define SDIO_DPSM_Enable ((uint32_t)0x00000001)
#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
/**
* @}
*/
/** @defgroup SDIO_Flags
* @{
*/
#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
((FLAG) == SDIO_FLAG_DCRCFAIL) || \
((FLAG) == SDIO_FLAG_CTIMEOUT) || \
((FLAG) == SDIO_FLAG_DTIMEOUT) || \
((FLAG) == SDIO_FLAG_TXUNDERR) || \
((FLAG) == SDIO_FLAG_RXOVERR) || \
((FLAG) == SDIO_FLAG_CMDREND) || \
((FLAG) == SDIO_FLAG_CMDSENT) || \
((FLAG) == SDIO_FLAG_DATAEND) || \
((FLAG) == SDIO_FLAG_STBITERR) || \
((FLAG) == SDIO_FLAG_DBCKEND) || \
((FLAG) == SDIO_FLAG_CMDACT) || \
((FLAG) == SDIO_FLAG_TXACT) || \
((FLAG) == SDIO_FLAG_RXACT) || \
((FLAG) == SDIO_FLAG_TXFIFOHE) || \
((FLAG) == SDIO_FLAG_RXFIFOHF) || \
((FLAG) == SDIO_FLAG_TXFIFOF) || \
((FLAG) == SDIO_FLAG_RXFIFOF) || \
((FLAG) == SDIO_FLAG_TXFIFOE) || \
((FLAG) == SDIO_FLAG_RXFIFOE) || \
((FLAG) == SDIO_FLAG_TXDAVL) || \
((FLAG) == SDIO_FLAG_RXDAVL) || \
((FLAG) == SDIO_FLAG_SDIOIT) || \
((FLAG) == SDIO_FLAG_CEATAEND))
#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
((IT) == SDIO_IT_DCRCFAIL) || \
((IT) == SDIO_IT_CTIMEOUT) || \
((IT) == SDIO_IT_DTIMEOUT) || \
((IT) == SDIO_IT_TXUNDERR) || \
((IT) == SDIO_IT_RXOVERR) || \
((IT) == SDIO_IT_CMDREND) || \
((IT) == SDIO_IT_CMDSENT) || \
((IT) == SDIO_IT_DATAEND) || \
((IT) == SDIO_IT_STBITERR) || \
((IT) == SDIO_IT_DBCKEND) || \
((IT) == SDIO_IT_CMDACT) || \
((IT) == SDIO_IT_TXACT) || \
((IT) == SDIO_IT_RXACT) || \
((IT) == SDIO_IT_TXFIFOHE) || \
((IT) == SDIO_IT_RXFIFOHF) || \
((IT) == SDIO_IT_TXFIFOF) || \
((IT) == SDIO_IT_RXFIFOF) || \
((IT) == SDIO_IT_TXFIFOE) || \
((IT) == SDIO_IT_RXFIFOE) || \
((IT) == SDIO_IT_TXDAVL) || \
((IT) == SDIO_IT_RXDAVL) || \
((IT) == SDIO_IT_SDIOIT) || \
((IT) == SDIO_IT_CEATAEND))
#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
/**
* @}
*/
/** @defgroup SDIO_Read_Wait_Mode
* @{
*/
#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000000)
#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000001)
#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
((MODE) == SDIO_ReadWaitMode_DATA2))
/**
* @}
*/
/**
* @}
*/
/** @defgroup SDIO_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup SDIO_Exported_Functions
* @{
*/
void SDIO_DeInit(void);
void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
void SDIO_ClockCmd(FunctionalState NewState);
void SDIO_SetPowerState(uint32_t SDIO_PowerState);
uint32_t SDIO_GetPowerState(void);
void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
void SDIO_DMACmd(FunctionalState NewState);
void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
uint8_t SDIO_GetCommandResponse(void);
uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
uint32_t SDIO_GetDataCounter(void);
uint32_t SDIO_ReadData(void);
void SDIO_WriteData(uint32_t Data);
uint32_t SDIO_GetFIFOCount(void);
void SDIO_StartSDIOReadWait(FunctionalState NewState);
void SDIO_StopSDIOReadWait(FunctionalState NewState);
void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
void SDIO_SetSDIOOperation(FunctionalState NewState);
void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
void SDIO_CommandCompletionCmd(FunctionalState NewState);
void SDIO_CEATAITCmd(FunctionalState NewState);
void SDIO_SendCEATACmd(FunctionalState NewState);
FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
void SDIO_ClearFlag(uint32_t SDIO_FLAG);
ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
#endif /* __STM32F10x_SDIO_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_sdio.h | C | oos | 18,598 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_bkp.c
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file provides all the BKP firmware functions.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_bkp.h"
#include "stm32f10x_rcc.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ------------ BKP registers bit address in the alias region ----------- */
#define BKP_OFFSET (BKP_BASE - PERIPH_BASE)
/* --- RTCCR Register ---*/
/* Alias word address of CCO bit */
#define RTCCR_OFFSET (BKP_OFFSET + 0x2C)
#define CCO_BitNumber 0x07
#define RTCCR_CCO_BB (PERIPH_BB_BASE + (RTCCR_OFFSET * 32) + (CCO_BitNumber * 4))
/* --- CR Register ---*/
/* Alias word address of TPAL bit */
#define CR_OFFSET (BKP_OFFSET + 0x30)
#define TPAL_BitNumber 0x01
#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))
/* Alias word address of TPE bit */
#define TPE_BitNumber 0x00
#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))
/* --- CSR Register ---*/
/* Alias word address of TPIE bit */
#define CSR_OFFSET (BKP_OFFSET + 0x34)
#define TPIE_BitNumber 0x02
#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
/* Alias word address of TIF bit */
#define TIF_BitNumber 0x09
#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
/* Alias word address of TEF bit */
#define TEF_BitNumber 0x08
#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
/* ---------------------- BKP registers bit mask ------------------------ */
/* RTCCR register bit mask */
#define RTCCR_CAL_Mask ((u16)0xFF80)
/* CSR register bit mask */
#define CSR_CTE_Set ((u16)0x0001)
#define CSR_CTI_Set ((u16)0x0002)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : BKP_DeInit
* Description : Deinitializes the BKP peripheral registers to their default
* reset values.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void BKP_DeInit(void)
{
RCC_BackupResetCmd(ENABLE);
RCC_BackupResetCmd(DISABLE);
}
/*******************************************************************************
* Function Name : BKP_TamperPinLevelConfig
* Description : Configures the Tamper Pin active level.
* Input : - BKP_TamperPinLevel: specifies the Tamper Pin active level.
* This parameter can be one of the following values:
* - BKP_TamperPinLevel_High: Tamper pin active on high level
* - BKP_TamperPinLevel_Low: Tamper pin active on low level
* Output : None
* Return : None
*******************************************************************************/
void BKP_TamperPinLevelConfig(u16 BKP_TamperPinLevel)
{
/* Check the parameters */
assert(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));
*(vu32 *) CR_TPAL_BB = BKP_TamperPinLevel;
}
/*******************************************************************************
* Function Name : BKP_TamperPinCmd
* Description : Enables or disables the Tamper Pin activation.
* Input : - NewState: new state of the Tamper Pin activation.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void BKP_TamperPinCmd(FunctionalState NewState)
{
/* Check the parameters */
assert(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) CR_TPE_BB = (u32)NewState;
}
/*******************************************************************************
* Function Name : BKP_ITConfig
* Description : Enables or disables the Tamper Pin Interrupt.
* Input : - NewState: new state of the Tamper Pin Interrupt.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void BKP_ITConfig(FunctionalState NewState)
{
/* Check the parameters */
assert(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) CSR_TPIE_BB = (u32)NewState;
}
/*******************************************************************************
* Function Name : BKP_RTCCalibrationClockOutputCmd
* Description : Enables or disables the output of the Calibration Clock.
* Input : - NewState: new state of the Calibration Clock output.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void BKP_RTCCalibrationClockOutputCmd(FunctionalState NewState)
{
/* Check the parameters */
assert(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) RTCCR_CCO_BB = (u32)NewState;
}
/*******************************************************************************
* Function Name : BKP_SetRTCCalibrationValue
* Description : Sets RTC Clock Calibration value.
* Input : - CalibrationValue: specifies the RTC Clock Calibration value.
* This parameter must be a number between 0 and 0x7F.
* Output : None
* Return : None
*******************************************************************************/
void BKP_SetRTCCalibrationValue(u8 CalibrationValue)
{
u16 tmpreg = 0;
/* Check the parameters */
assert(IS_BKP_CALIBRATION_VALUE(CalibrationValue));
tmpreg = BKP->RTCCR;
/* Clear CAL[6:0] bits */
tmpreg &= RTCCR_CAL_Mask;
/* Set CAL[6:0] bits according to CalibrationValue value */
tmpreg |= CalibrationValue;
/* Store the new value */
BKP->RTCCR = tmpreg;
}
/*******************************************************************************
* Function Name : BKP_WriteBackupRegister
* Description : Writes user data to the specified Data Backup Register.
* Input : - BKP_DR: specifies the Data Backup Register.
* This parameter can be BKP_DRx where x:[1, 10]
* - Data: data to write
* Output : None
* Return : None
*******************************************************************************/
void BKP_WriteBackupRegister(u16 BKP_DR, u16 Data)
{
/* Check the parameters */
assert(IS_BKP_DR(BKP_DR));
*(vu16 *) (BKP_BASE + BKP_DR) = Data;
}
/*******************************************************************************
* Function Name : BKP_ReadBackupRegister
* Description : Reads data from the specified Data Backup Register.
* Input : - BKP_DR: specifies the Data Backup Register.
* This parameter can be BKP_DRx where x:[1, 10]
* Output : None
* Return : The content of the specified Data Backup Register
*******************************************************************************/
u16 BKP_ReadBackupRegister(u16 BKP_DR)
{
/* Check the parameters */
assert(IS_BKP_DR(BKP_DR));
return (*(vu16 *) (BKP_BASE + BKP_DR));
}
/*******************************************************************************
* Function Name : BKP_GetFlagStatus
* Description : Checks whether the Tamper Pin Event flag is set or not.
* Input : None
* Output : None
* Return : The new state of the Tamper Pin Event flag (SET or RESET).
*******************************************************************************/
FlagStatus BKP_GetFlagStatus(void)
{
return (FlagStatus)(*(vu32 *) CSR_TEF_BB);
}
/*******************************************************************************
* Function Name : BKP_ClearFlag
* Description : Clears Tamper Pin Event pending flag.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void BKP_ClearFlag(void)
{
/* Set CTE bit to clear Tamper Pin Event flag */
BKP->CSR |= CSR_CTE_Set;
}
/*******************************************************************************
* Function Name : BKP_GetITStatus
* Description : Checks whether the Tamper Pin Interrupt has occurred or not.
* Input : None
* Output : None
* Return : The new state of the Tamper Pin Interrupt (SET or RESET).
*******************************************************************************/
ITStatus BKP_GetITStatus(void)
{
return (ITStatus)(*(vu32 *) CSR_TIF_BB);
}
/*******************************************************************************
* Function Name : BKP_ClearITPendingBit
* Description : Clears Tamper Pin Interrupt pending bit.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void BKP_ClearITPendingBit(void)
{
/* Set CTI bit to clear Tamper Pin Interrupt pending bit */
BKP->CSR |= CSR_CTI_Set;
}
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_bkp.c | C | oos | 10,694 |
/**
******************************************************************************
* @file stm32f10x_crc.c
* @author MCD Application Team
* @version V3.0.0
* @date 04/06/2009
* @brief This file provides all the CRC firmware functions.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_crc.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @defgroup CRC
* @brief CRC driver modules
* @{
*/
/** @defgroup CRC_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup CRC_Private_Defines
* @{
*/
/* CR register bit mask */
#define CR_RESET_Set ((uint32_t)0x00000001)
/**
* @}
*/
/** @defgroup CRC_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup CRC_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup CRC_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup CRC_Private_Functions
* @{
*/
/**
* @brief Resets the CRC Data register (DR).
* @param None
* @retval : None
*/
void CRC_ResetDR(void)
{
/* Reset CRC generator */
CRC->CR = CR_RESET_Set;
}
/**
* @brief Computes the 32-bit CRC of a given data word(32-bit).
* @param Data: data word(32-bit) to compute its CRC
* @retval : 32-bit CRC
*/
uint32_t CRC_CalcCRC(uint32_t Data)
{
CRC->DR = Data;
return (CRC->DR);
}
/**
* @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
* @param pBuffer: pointer to the buffer containing the data to be
* computed
* @param BufferLength: length of the buffer to be computed
* @retval : 32-bit CRC
*/
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
{
uint32_t index = 0;
for(index = 0; index < BufferLength; index++)
{
CRC->DR = pBuffer[index];
}
return (CRC->DR);
}
/**
* @brief Returns the current CRC value.
* @param None
* @retval : 32-bit CRC
*/
uint32_t CRC_GetCRC(void)
{
return (CRC->DR);
}
/**
* @brief Stores a 8-bit data in the Independent Data(ID) register.
* @param IDValue: 8-bit value to be stored in the ID register
* @retval : None
*/
void CRC_SetIDRegister(uint8_t IDValue)
{
CRC->IDR = IDValue;
}
/**
* @brief Returns the 8-bit data stored in the Independent Data(ID) register
* @param None
* @retval : 8-bit value of the ID register
*/
uint8_t CRC_GetIDRegister(void)
{
return (CRC->IDR);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_crc.c | C | oos | 3,340 |
/**
******************************************************************************
* @file misc.c
* @author MCD Application Team
* @version V3.0.0
* @date 04/06/2009
* @brief This file provides all the miscellaneous firmware functions.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
#include "misc.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @defgroup MISC
* @brief MISC driver modules
* @{
*/
/** @defgroup MISC_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup MISC_Private_Defines
* @{
*/
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
/**
* @}
*/
/** @defgroup MISC_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup MISC_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup MISC_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup MISC_Private_Functions
* @{
*/
/**
* @brief Configures the priority grouping: pre-emption priority and
* subpriority.
* @param NVIC_PriorityGroup: specifies the priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
* 4 bits for subpriority
* @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
* 3 bits for subpriority
* @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
* 2 bits for subpriority
* @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
* 1 bits for subpriority
* @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
* 0 bits for subpriority
* @retval : None
*/
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
}
/**
* @brief Initializes the NVIC peripheral according to the specified
* parameters in the NVIC_InitStruct.
* @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure
* that contains the configuration information for the
* specified NVIC peripheral.
* @retval : None
*/
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
{
uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
{
/* Compute the Corresponding IRQ Priority --------------------------------*/
tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
tmppre = (0x4 - tmppriority);
tmpsub = tmpsub >> tmppriority;
tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
tmppriority = tmppriority << 0x04;
NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
/* Enable the Selected IRQ Channels --------------------------------------*/
NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
}
else
{
/* Disable the Selected IRQ Channels -------------------------------------*/
NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
}
}
/**
* @brief Sets the vector table location and Offset.
* @param NVIC_VectTab: specifies if the vector table is in RAM or
* FLASH memory.
* This parameter can be one of the following values:
* @arg NVIC_VectTab_RAM
* @arg NVIC_VectTab_FLASH
* @param Offset: Vector Table base offset field.
* This value must be a multiple of 0x100.
* @retval : None
*/
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
{
/* Check the parameters */
assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
assert_param(IS_NVIC_OFFSET(Offset));
SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
}
/**
* @brief Selects the condition for the system to enter low power mode.
* @param LowPowerMode: Specifies the new mode for the system to enter
* low power mode.
* This parameter can be one of the following values:
* @arg NVIC_LP_SEVONPEND
* @arg NVIC_LP_SLEEPDEEP
* @arg NVIC_LP_SLEEPONEXIT
* @param NewState: new state of LP condition.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
*/
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_NVIC_LP(LowPowerMode));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
SCB->SCR |= LowPowerMode;
}
else
{
SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
}
}
/**
* @brief Configures the SysTick clock source.
* @param SysTick_CLKSource: specifies the SysTick clock source.
* This parameter can be one of the following values:
* @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8
* selected as SysTick clock source.
* @arg SysTick_CLKSource_HCLK: AHB clock selected as
* SysTick clock source.
* @retval : None
*/
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
{
/* Check the parameters */
assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
{
SysTick->CTRL |= SysTick_CLKSource_HCLK;
}
else
{
SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/src/misc.c | C | oos | 6,874 |
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32fxxx_eth_lib.c
* Author : MCD Application Team
* Version : V2.0.2
* Date : 07/11/2008
* Description : This file provides all peripherals pointers initialization.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#define EXT
#include "stm32f10x_lib.h"
/* Includes ------------------------------------------------------------------*/
#include "stm32fxxx_eth_lib.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
#ifdef ETH_DEBUG
/*******************************************************************************
* Function Name : ethernet_debug
* Description : This function initialize peripherals pointers.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void eth_debug(void)
{
/********************************** ETHERNET **********************************/
#ifdef _ETH_MAC
ETH_MAC = ((ETH_MAC_TypeDef *) ETH_MAC_BASE);
#endif /*_ETH_MAC */
#ifdef _ETH_MMC
ETH_MMC = ((ETH_MMC_TypeDef *) ETH_MMC_BASE);
#endif /*_ETH_MMC */
#ifdef _ETH_PTP
ETH_PTP = ((ETH_PTP_TypeDef *) ETH_PTP_BASE);
#endif /*_ETH_PTP */
#ifdef _ETH_DMA
ETH_DMA = ((ETH_DMA_TypeDef *) ETH_DMA_BASE);
#endif /*_ETH_DMA */
}
#endif /* ETH_DEBUG*/
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32fxxx_eth_lib.c | C | oos | 2,537 |
;******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
;* File Name : cortexm3_macro.s
;* Author : MCD Application Team
;* Date First Issued : 09/29/2006
;* Description : Instruction wrappers for special Cortex-M3 instructions.
;*******************************************************************************
; History:
; 05/21/2007: V0.3
; 04/02/2007: V0.2
; 02/05/2007: V0.1
; 09/29/2006: V0.01
;*******************************************************************************
; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
THUMB
REQUIRE8
PRESERVE8
AREA |.text|, CODE, READONLY, ALIGN=2
; Exported functions
EXPORT __WFI
EXPORT __WFE
EXPORT __SEV
EXPORT __ISB
EXPORT __DSB
EXPORT __DMB
EXPORT __SVC
EXPORT __MRS_CONTROL
EXPORT __MSR_CONTROL
EXPORT __MRS_PSP
EXPORT __MSR_PSP
EXPORT __MRS_MSP
EXPORT __MSR_MSP
EXPORT __SETPRIMASK
EXPORT __RESETPRIMASK
EXPORT __SETFAULTMASK
EXPORT __RESETFAULTMASK
EXPORT __BASEPRICONFIG
EXPORT __GetBASEPRI
EXPORT __REV_HalfWord
EXPORT __REV_Word
;*******************************************************************************
; Function Name : __WFI
; Description : Assembler function for the WFI instruction.
; Input : None
; Return : None
;*******************************************************************************
__WFI
WFI
BX r14
;*******************************************************************************
; Function Name : __WFE
; Description : Assembler function for the WFE instruction.
; Input : None
; Return : None
;*******************************************************************************
__WFE
WFE
BX r14
;*******************************************************************************
; Function Name : __SEV
; Description : Assembler function for the SEV instruction.
; Input : None
; Return : None
;*******************************************************************************
__SEV
SEV
BX r14
;*******************************************************************************
; Function Name : __ISB
; Description : Assembler function for the ISB instruction.
; Input : None
; Return : None
;*******************************************************************************
__ISB
ISB
BX r14
;*******************************************************************************
; Function Name : __DSB
; Description : Assembler function for the DSB instruction.
; Input : None
; Return : None
;*******************************************************************************
__DSB
DSB
BX r14
;*******************************************************************************
; Function Name : __DMB
; Description : Assembler function for the DMB instruction.
; Input : None
; Return : None
;*******************************************************************************
__DMB
DMB
BX r14
;*******************************************************************************
; Function Name : __SVC
; Description : Assembler function for the SVC instruction.
; Input : None
; Return : None
;*******************************************************************************
__SVC
SVC 0x01
BX r14
;*******************************************************************************
; Function Name : __MRS_CONTROL
; Description : Assembler function for the MRS instruction.
; Input : None
; Return : - r0 : Cortex-M3 CONTROL register value.
;*******************************************************************************
__MRS_CONTROL
MRS r0, CONTROL
BX r14
;*******************************************************************************
; Function Name : __MSR_CONTROL
; Description : Assembler function for the MSR instruction.
; Input : - r0 : Cortex-M3 CONTROL register new value.
; Return : None
;*******************************************************************************
__MSR_CONTROL
MSR CONTROL, r0
ISB
BX r14
;*******************************************************************************
; Function Name : __MRS_PSP
; Description : Assembler function for the MRS instruction.
; Input : None
; Return : - r0 : Process Stack value.
;*******************************************************************************
__MRS_PSP
MRS r0, PSP
BX r14
;*******************************************************************************
; Function Name : __MSR_PSP
; Description : Assembler function for the MSR instruction.
; Input : - r0 : Process Stack new value.
; Return : None
;*******************************************************************************
__MSR_PSP
MSR PSP, r0 ; set Process Stack value
BX r14
;*******************************************************************************
; Function Name : __MRS_MSP
; Description : Assembler function for the MRS instruction.
; Input : None
; Return : - r0 : Main Stack value.
;*******************************************************************************
__MRS_MSP
MRS r0, MSP
BX r14
;*******************************************************************************
; Function Name : __MSR_MSP
; Description : Assembler function for the MSR instruction.
; Input : - r0 : Main Stack new value.
; Return : None
;*******************************************************************************
__MSR_MSP
MSR MSP, r0 ; set Main Stack value
BX r14
;*******************************************************************************
; Function Name : __SETPRIMASK
; Description : Assembler function to set the PRIMASK.
; Input : None
; Return : None
;*******************************************************************************
__SETPRIMASK
CPSID i
BX r14
;*******************************************************************************
; Function Name : __RESETPRIMASK
; Description : Assembler function to reset the PRIMASK.
; Input : None
; Return : None
;*******************************************************************************
__RESETPRIMASK
CPSIE i
BX r14
;*******************************************************************************
; Function Name : __SETFAULTMASK
; Description : Assembler function to set the FAULTMASK.
; Input : None
; Return : None
;*******************************************************************************
__SETFAULTMASK
CPSID f
BX r14
;*******************************************************************************
; Function Name : __RESETFAULTMASK
; Description : Assembler function to reset the FAULTMASK.
; Input : None
; Return : None
;*******************************************************************************
__RESETFAULTMASK
CPSIE f
BX r14
;*******************************************************************************
; Function Name : __BASEPRICONFIG
; Description : Assembler function to set the Base Priority.
; Input : - r0 : Base Priority new value
; Return : None
;*******************************************************************************
__BASEPRICONFIG
MSR BASEPRI, r0
BX r14
;*******************************************************************************
; Function Name : __GetBASEPRI
; Description : Assembler function to get the Base Priority value.
; Input : None
; Return : - r0 : Base Priority value
;*******************************************************************************
__GetBASEPRI
MRS r0, BASEPRI_MAX
BX r14
;*******************************************************************************
; Function Name : __REV_HalfWord
; Description : Reverses the byte order in HalfWord(16-bit) input variable.
; Input : - r0 : specifies the input variable
; Return : - r0 : holds tve variable value after byte reversing.
;*******************************************************************************
__REV_HalfWord
REV16 r0, r0
BX r14
;*******************************************************************************
; Function Name : __REV_Word
; Description : Reverses the byte order in Word(32-bit) input variable.
; Input : - r0 : specifies the input variable
; Return : - r0 : holds tve variable value after byte reversing.
;*******************************************************************************
__REV_Word
REV r0, r0
BX r14
END
;******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE*****
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/src/cortexm3_macro_rvds.s | Unix Assembly | oos | 9,548 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : lcd.c
* Author : MCD Application Team
* Date First Issued : mm/dd/yyyy
* Description : This file includes the LCD driver for AM-240320LTNQW00H
* liquid Crystal Display Module of STM32F10x-EVAL.
********************************************************************************
* History:
* mm/dd/yyyy
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_type.h"
#include "lcd.h"
#include "spi_flash.h"
#include "FreeRTOS.h"
#include "task.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ASCII Table: each character is 16 column (16dots large)
and 24 raw (24 dots high) */
const uc16 ASCII_Table[] =
{
/* Space ' ' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '!' */
0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000, 0x0000,
0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '"' */
0x0000, 0x0000, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '#' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C60, 0x0C60,
0x0C60, 0x0630, 0x0630, 0x1FFE, 0x1FFE, 0x0630, 0x0738, 0x0318,
0x1FFE, 0x1FFE, 0x0318, 0x0318, 0x018C, 0x018C, 0x018C, 0x0000,
/* '$' */
0x0000, 0x0080, 0x03E0, 0x0FF8, 0x0E9C, 0x1C8C, 0x188C, 0x008C,
0x0098, 0x01F8, 0x07E0, 0x0E80, 0x1C80, 0x188C, 0x188C, 0x189C,
0x0CB8, 0x0FF0, 0x03E0, 0x0080, 0x0080, 0x0000, 0x0000, 0x0000,
/* '%' */
0x0000, 0x0000, 0x0000, 0x180E, 0x0C1B, 0x0C11, 0x0611, 0x0611,
0x0311, 0x0311, 0x019B, 0x018E, 0x38C0, 0x6CC0, 0x4460, 0x4460,
0x4430, 0x4430, 0x4418, 0x6C18, 0x380C, 0x0000, 0x0000, 0x0000,
/* '&' */
0x0000, 0x01E0, 0x03F0, 0x0738, 0x0618, 0x0618, 0x0330, 0x01F0,
0x00F0, 0x00F8, 0x319C, 0x330E, 0x1E06, 0x1C06, 0x1C06, 0x3F06,
0x73FC, 0x21F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* ''' */
0x0000, 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '(' */
0x0000, 0x0200, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x0060, 0x0060,
0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030,
0x0060, 0x0060, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0200, 0x0000,
/* ')' */
0x0000, 0x0020, 0x0060, 0x00C0, 0x0180, 0x0180, 0x0300, 0x0300,
0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600,
0x0300, 0x0300, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0020, 0x0000,
/* '*' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,
0x06D8, 0x07F8, 0x01E0, 0x0330, 0x0738, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '+' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,
0x0180, 0x0180, 0x0180, 0x3FFC, 0x3FFC, 0x0180, 0x0180, 0x0180,
0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* ',' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000,
/* '-' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x07E0, 0x07E0, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '.' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '/' */
0x0000, 0x0C00, 0x0C00, 0x0600, 0x0600, 0x0600, 0x0300, 0x0300,
0x0300, 0x0380, 0x0180, 0x0180, 0x0180, 0x00C0, 0x00C0, 0x00C0,
0x0060, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '0' */
0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x180C, 0x180C, 0x180C,
0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C18, 0x0E38,
0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '1' */
0x0000, 0x0100, 0x0180, 0x01C0, 0x01F0, 0x0198, 0x0188, 0x0180,
0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '2' */
0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x1800,
0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018,
0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '3' */
0x0000, 0x01E0, 0x07F8, 0x0E18, 0x0C0C, 0x0C0C, 0x0C00, 0x0600,
0x03C0, 0x07C0, 0x0C00, 0x1800, 0x1800, 0x180C, 0x180C, 0x0C18,
0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '4' */
0x0000, 0x0C00, 0x0E00, 0x0F00, 0x0F00, 0x0D80, 0x0CC0, 0x0C60,
0x0C60, 0x0C30, 0x0C18, 0x0C0C, 0x3FFC, 0x3FFC, 0x0C00, 0x0C00,
0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '5' */
0x0000, 0x0FF8, 0x0FF8, 0x0018, 0x0018, 0x000C, 0x03EC, 0x07FC,
0x0E1C, 0x1C00, 0x1800, 0x1800, 0x1800, 0x180C, 0x0C1C, 0x0E18,
0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '6' */
0x0000, 0x07C0, 0x0FF0, 0x1C38, 0x1818, 0x0018, 0x000C, 0x03CC,
0x0FEC, 0x0E3C, 0x1C1C, 0x180C, 0x180C, 0x180C, 0x1C18, 0x0E38,
0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '7' */
0x0000, 0x1FFC, 0x1FFC, 0x0C00, 0x0600, 0x0600, 0x0300, 0x0380,
0x0180, 0x01C0, 0x00C0, 0x00E0, 0x0060, 0x0060, 0x0070, 0x0030,
0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '8' */
0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x0C18, 0x0C18, 0x0638,
0x07F0, 0x07F0, 0x0C18, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C38,
0x0FF8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '9' */
0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C1C, 0x180C, 0x180C, 0x180C,
0x1C1C, 0x1E38, 0x1BF8, 0x19E0, 0x1800, 0x0C00, 0x0C00, 0x0E1C,
0x07F8, 0x01F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* ':' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* ';' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000, 0x0000,
/* '<' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x1000, 0x1C00, 0x0F80, 0x03E0, 0x00F8, 0x0018, 0x00F8, 0x03E0,
0x0F80, 0x1C00, 0x1000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '=' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x1FF8, 0x0000, 0x0000, 0x0000, 0x1FF8, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '>' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0008, 0x0038, 0x01F0, 0x07C0, 0x1F00, 0x1800, 0x1F00, 0x07C0,
0x01F0, 0x0038, 0x0008, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '?' */
0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x0C00,
0x0600, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x0000, 0x0000,
0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '@' */
0x0000, 0x0000, 0x07E0, 0x1818, 0x2004, 0x29C2, 0x4A22, 0x4411,
0x4409, 0x4409, 0x4409, 0x2209, 0x1311, 0x0CE2, 0x4002, 0x2004,
0x1818, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'A' */
0x0000, 0x0380, 0x0380, 0x06C0, 0x06C0, 0x06C0, 0x0C60, 0x0C60,
0x1830, 0x1830, 0x1830, 0x3FF8, 0x3FF8, 0x701C, 0x600C, 0x600C,
0xC006, 0xC006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'B' */
0x0000, 0x03FC, 0x0FFC, 0x0C0C, 0x180C, 0x180C, 0x180C, 0x0C0C,
0x07FC, 0x0FFC, 0x180C, 0x300C, 0x300C, 0x300C, 0x300C, 0x180C,
0x1FFC, 0x07FC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'C' */
0x0000, 0x07C0, 0x1FF0, 0x3838, 0x301C, 0x700C, 0x6006, 0x0006,
0x0006, 0x0006, 0x0006, 0x0006, 0x0006, 0x6006, 0x700C, 0x301C,
0x1FF0, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'D' */
0x0000, 0x03FE, 0x0FFE, 0x0E06, 0x1806, 0x1806, 0x3006, 0x3006,
0x3006, 0x3006, 0x3006, 0x3006, 0x3006, 0x1806, 0x1806, 0x0E06,
0x0FFE, 0x03FE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'E' */
0x0000, 0x3FFC, 0x3FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
0x1FFC, 0x1FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
0x3FFC, 0x3FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'F' */
0x0000, 0x3FF8, 0x3FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
0x0018, 0x0018, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'G' */
0x0000, 0x0FE0, 0x3FF8, 0x783C, 0x600E, 0xE006, 0xC007, 0x0003,
0x0003, 0xFE03, 0xFE03, 0xC003, 0xC007, 0xC006, 0xC00E, 0xF03C,
0x3FF8, 0x0FE0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'H' */
0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,
0x3FFC, 0x3FFC, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,
0x300C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'I' */
0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'J' */
0x0000, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600,
0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0618, 0x0618, 0x0738,
0x03F0, 0x01E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'K' */
0x0000, 0x3006, 0x1806, 0x0C06, 0x0606, 0x0306, 0x0186, 0x00C6,
0x0066, 0x0076, 0x00DE, 0x018E, 0x0306, 0x0606, 0x0C06, 0x1806,
0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'L' */
0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
0x1FF8, 0x1FF8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'M' */
0x0000, 0xE00E, 0xF01E, 0xF01E, 0xF01E, 0xD836, 0xD836, 0xD836,
0xD836, 0xCC66, 0xCC66, 0xCC66, 0xC6C6, 0xC6C6, 0xC6C6, 0xC6C6,
0xC386, 0xC386, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'N' */
0x0000, 0x300C, 0x301C, 0x303C, 0x303C, 0x306C, 0x306C, 0x30CC,
0x30CC, 0x318C, 0x330C, 0x330C, 0x360C, 0x360C, 0x3C0C, 0x3C0C,
0x380C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'O' */
0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xC003, 0xC003,
0xC003, 0xC003, 0xC003, 0xC003, 0xC003, 0x6006, 0x700E, 0x381C,
0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'P' */
0x0000, 0x0FFC, 0x1FFC, 0x380C, 0x300C, 0x300C, 0x300C, 0x300C,
0x180C, 0x1FFC, 0x07FC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
0x000C, 0x000C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'Q' */
0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xE003, 0xC003,
0xC003, 0xC003, 0xC003, 0xC003, 0xE007, 0x6306, 0x3F0E, 0x3C1C,
0x3FF8, 0xF7E0, 0xC000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'R' */
0x0000, 0x0FFE, 0x1FFE, 0x3806, 0x3006, 0x3006, 0x3006, 0x3806,
0x1FFE, 0x07FE, 0x0306, 0x0606, 0x0C06, 0x1806, 0x1806, 0x3006,
0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'S' */
0x0000, 0x03E0, 0x0FF8, 0x0C1C, 0x180C, 0x180C, 0x000C, 0x001C,
0x03F8, 0x0FE0, 0x1E00, 0x3800, 0x3006, 0x3006, 0x300E, 0x1C1C,
0x0FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'T' */
0x0000, 0x7FFE, 0x7FFE, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'U' */
0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,
0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x1818,
0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'V' */
0x0000, 0x6003, 0x3006, 0x3006, 0x3006, 0x180C, 0x180C, 0x180C,
0x0C18, 0x0C18, 0x0E38, 0x0630, 0x0630, 0x0770, 0x0360, 0x0360,
0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'W' */
0x0000, 0x6003, 0x61C3, 0x61C3, 0x61C3, 0x3366, 0x3366, 0x3366,
0x3366, 0x3366, 0x3366, 0x1B6C, 0x1B6C, 0x1B6C, 0x1A2C, 0x1E3C,
0x0E38, 0x0E38, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'X' */
0x0000, 0xE00F, 0x700C, 0x3018, 0x1830, 0x0C70, 0x0E60, 0x07C0,
0x0380, 0x0380, 0x03C0, 0x06E0, 0x0C70, 0x1C30, 0x1818, 0x300C,
0x600E, 0xE007, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'Y' */
0x0000, 0xC003, 0x6006, 0x300C, 0x381C, 0x1838, 0x0C30, 0x0660,
0x07E0, 0x03C0, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'Z' */
0x0000, 0x7FFC, 0x7FFC, 0x6000, 0x3000, 0x1800, 0x0C00, 0x0600,
0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, 0x000C, 0x0006,
0x7FFE, 0x7FFE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '[' */
0x0000, 0x03E0, 0x03E0, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060,
0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060,
0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x03E0, 0x03E0, 0x0000,
/* '\' */
0x0000, 0x0030, 0x0030, 0x0060, 0x0060, 0x0060, 0x00C0, 0x00C0,
0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0300, 0x0300, 0x0300,
0x0600, 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* ']' */
0x0000, 0x03E0, 0x03E0, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300,
0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300,
0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x03E0, 0x03E0, 0x0000,
/* '^' */
0x0000, 0x0000, 0x01C0, 0x01C0, 0x0360, 0x0360, 0x0360, 0x0630,
0x0630, 0x0C18, 0x0C18, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '_' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* ''' */
0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'a' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03F0, 0x07F8,
0x0C1C, 0x0C0C, 0x0F00, 0x0FF0, 0x0CF8, 0x0C0C, 0x0C0C, 0x0F1C,
0x0FF8, 0x18F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'b' */
0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x03D8, 0x0FF8,
0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38,
0x0FF8, 0x03D8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'c' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x07F0,
0x0E30, 0x0C18, 0x0018, 0x0018, 0x0018, 0x0018, 0x0C18, 0x0E30,
0x07F0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'd' */
0x0000, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x1BC0, 0x1FF0,
0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30,
0x1FF0, 0x1BC0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'e' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0,
0x0C30, 0x1818, 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x1838, 0x1C30,
0x0FF0, 0x07C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'f' */
0x0000, 0x0F80, 0x0FC0, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0,
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'g' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0DE0, 0x0FF8,
0x0E18, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0E18,
0x0FF8, 0x0DE0, 0x0C00, 0x0C0C, 0x061C, 0x07F8, 0x01F0, 0x0000,
/* 'h' */
0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x07D8, 0x0FF8,
0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818,
0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'i' */
0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'j' */
0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00F8, 0x0078, 0x0000,
/* 'k' */
0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0C0C, 0x060C,
0x030C, 0x018C, 0x00CC, 0x006C, 0x00FC, 0x019C, 0x038C, 0x030C,
0x060C, 0x0C0C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'l' */
0x0000, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'm' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3C7C, 0x7EFF,
0xE3C7, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183,
0xC183, 0xC183, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'n' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0798, 0x0FF8,
0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818,
0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'o' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0,
0x0C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C30,
0x0FF0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'p' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03D8, 0x0FF8,
0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38,
0x0FF8, 0x03D8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0000,
/* 'q' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1BC0, 0x1FF0,
0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30,
0x1FF0, 0x1BC0, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x0000,
/* 'r' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x07B0, 0x03F0,
0x0070, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030,
0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 's' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03E0, 0x03F0,
0x0E38, 0x0C18, 0x0038, 0x03F0, 0x07C0, 0x0C00, 0x0C18, 0x0E38,
0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 't' */
0x0000, 0x0000, 0x0080, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0,
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
0x07C0, 0x0780, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'u' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1818, 0x1818,
0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C38,
0x1FF0, 0x19E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'v' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x180C, 0x0C18,
0x0C18, 0x0C18, 0x0630, 0x0630, 0x0630, 0x0360, 0x0360, 0x0360,
0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'w' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x41C1, 0x41C1,
0x61C3, 0x6363, 0x6363, 0x6363, 0x3636, 0x3636, 0x3636, 0x1C1C,
0x1C1C, 0x1C1C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'x' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x381C, 0x1C38,
0x0C30, 0x0660, 0x0360, 0x0360, 0x0360, 0x0360, 0x0660, 0x0C30,
0x1C38, 0x381C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'y' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3018, 0x1830,
0x1830, 0x1870, 0x0C60, 0x0C60, 0x0CE0, 0x06C0, 0x06C0, 0x0380,
0x0380, 0x0380, 0x0180, 0x0180, 0x01C0, 0x00F0, 0x0070, 0x0000,
/* 'z' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1FFC, 0x1FFC,
0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018,
0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '{' */
0x0000, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
0x00C0, 0x0060, 0x0060, 0x0030, 0x0060, 0x0040, 0x00C0, 0x00C0,
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0000, 0x0000,
/* '|' */
0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000,
/* '}' */
0x0000, 0x0060, 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0180,
0x0180, 0x0300, 0x0300, 0x0600, 0x0300, 0x0100, 0x0180, 0x0180,
0x0180, 0x0180, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0000, 0x0000,
/* '~' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x10F0, 0x1FF8, 0x0F08, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
};
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Global variables to set the written text color */
static vu16 TextColor = 0x0000, BackColor = 0xFFFF;
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
static u32 StrLength(u8 *Str);
/*******************************************************************************
* Function Name : LCD_Init
* Description : Initializes LCD.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void LCD_Init(void)
{
/* Configure the LCD Control pins --------------------------------------------*/
LCD_CtrlLinesConfig();
/* Configure the SPI2 interface ----------------------------------------------*/
LCD_SPIConfig();
/* Enable the LCD Oscillator -------------------------------------------------*/
LCD_WriteReg(R1, 0x10);
LCD_WriteReg(R0, 0xA0);
LCD_WriteReg(R3, 0x01);
vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */
LCD_WriteReg(R3, 0x00);
LCD_WriteReg(R43, 0x04);
LCD_WriteReg(R40, 0x18);
LCD_WriteReg(R26, 0x05);
LCD_WriteReg(R37, 0x05);
LCD_WriteReg(R25, 0x00);
/* LCD Power On --------------------------------------------------------------*/
LCD_WriteReg(R28, 0x73);
LCD_WriteReg(R36, 0x74);
LCD_WriteReg(R30, 0x01);
LCD_WriteReg(R24, 0xC1);
vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */
LCD_WriteReg(R24, 0xE1);
LCD_WriteReg(R24, 0xF1);
vTaskDelay( 60 / portTICK_RATE_MS ); /* Delay 60 ms */
LCD_WriteReg(R24, 0xF5);
vTaskDelay( 60 / portTICK_RATE_MS ); /* Delay 60 ms */
LCD_WriteReg(R27, 0x09);
vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */
LCD_WriteReg(R31, 0x11);
LCD_WriteReg(R32, 0x0E);
LCD_WriteReg(R30, 0x81);
vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */
/* Chip Set ------------------------------------------------------------------*/
LCD_WriteReg(R157, 0x00);
LCD_WriteReg(R192, 0x00);
LCD_WriteReg(R14, 0x00);
LCD_WriteReg(R15, 0x00);
LCD_WriteReg(R16, 0x00);
LCD_WriteReg(R17, 0x00);
LCD_WriteReg(R18, 0x00);
LCD_WriteReg(R19, 0x00);
LCD_WriteReg(R20, 0x00);
LCD_WriteReg(R21, 0x00);
LCD_WriteReg(R22, 0x00);
LCD_WriteReg(R23, 0x00);
LCD_WriteReg(R52, 0x01);
LCD_WriteReg(R53, 0x00);
LCD_WriteReg(R75, 0x00);
LCD_WriteReg(R76, 0x00);
LCD_WriteReg(R78, 0x00);
LCD_WriteReg(R79, 0x00);
LCD_WriteReg(R80, 0x00);
LCD_WriteReg(R60, 0x00);
LCD_WriteReg(R61, 0x00);
LCD_WriteReg(R62, 0x01);
LCD_WriteReg(R63, 0x3F);
LCD_WriteReg(R64, 0x02);
LCD_WriteReg(R65, 0x02);
LCD_WriteReg(R66, 0x00);
LCD_WriteReg(R67, 0x00);
LCD_WriteReg(R68, 0x00);
LCD_WriteReg(R69, 0x00);
LCD_WriteReg(R70, 0xEF);
LCD_WriteReg(R71, 0x00);
LCD_WriteReg(R72, 0x00);
LCD_WriteReg(R73, 0x01);
LCD_WriteReg(R74, 0x3F);
LCD_WriteReg(R29, 0x08); /* R29:Gate scan direction setting */
LCD_WriteReg(R134, 0x00);
LCD_WriteReg(R135, 0x30);
LCD_WriteReg(R136, 0x02);
LCD_WriteReg(R137, 0x05);
LCD_WriteReg(R141, 0x01); /* R141:Register set-up mode for one line clock */
LCD_WriteReg(R139, 0x20); /* R139:One line SYSCLK number in one-line */
LCD_WriteReg(R51, 0x01); /* R51:N line inversion setting */
LCD_WriteReg(R55, 0x01); /* R55:Scanning method setting */
LCD_WriteReg(R118, 0x00);
/* Gamma Set -----------------------------------------------------------------*/
LCD_WriteReg(R143, 0x10);
LCD_WriteReg(R144, 0x67);
LCD_WriteReg(R145, 0x07);
LCD_WriteReg(R146, 0x65);
LCD_WriteReg(R147, 0x07);
LCD_WriteReg(R148, 0x01);
LCD_WriteReg(R149, 0x76);
LCD_WriteReg(R150, 0x56);
LCD_WriteReg(R151, 0x00);
LCD_WriteReg(R152, 0x06);
LCD_WriteReg(R153, 0x03);
LCD_WriteReg(R154, 0x00);
/* Display On ----------------------------------------------------------------*/
LCD_WriteReg(R1, 0x50);
LCD_WriteReg(R5, 0x04);
LCD_WriteReg(R0, 0x80);
LCD_WriteReg(R59, 0x01);
vTaskDelay( 40 / portTICK_RATE_MS ); /* Delay 40 ms */
LCD_WriteReg(R0, 0x20);
}
/*******************************************************************************
* Function Name : LCD_SetTextColor
* Description : Sets the Text color.
* Input : - Color: specifies the Text color code RGB(5-6-5).
* Output : - TextColor: Text color global variable used by LCD_DrawChar
* and LCD_DrawPicture functions.
* Return : None
*******************************************************************************/
void LCD_SetTextColor(vu16 Color)
{
TextColor = Color;
}
/*******************************************************************************
* Function Name : LCD_SetBackColor
* Description : Sets the Background color.
* Input : - Color: specifies the Background color code RGB(5-6-5).
* Output : - BackColor: Background color global variable used by
* LCD_DrawChar and LCD_DrawPicture functions.
* Return : None
*******************************************************************************/
void LCD_SetBackColor(vu16 Color)
{
BackColor = Color;
}
/*******************************************************************************
* Function Name : LCD_ClearLine
* Description : Clears the selected line.
* Input : - Line: the Line to be cleared.
* This parameter can be one of the following values:
* - Linex: where x can be 0..9
* Output : None
* Return : None
*******************************************************************************/
void LCD_ClearLine(u8 Line)
{
LCD_DisplayStringLine(Line, " ");
}
/*******************************************************************************
* Function Name : LCD_Clear
* Description : Clears the hole LCD.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void LCD_Clear(void)
{
u32 index = 0;
LCD_SetCursor(0x00, 0x013F);
for(index = 0; index < 0x12C00; index++)
{
LCD_WriteRAM(White);
}
}
/*******************************************************************************
* Function Name : LCD_SetCursor
* Description : Sets the cursor position.
* Input : - Xpos: specifies the X position.
* - Ypos: specifies the Y position.
* Output : None
* Return : None
*******************************************************************************/
void LCD_SetCursor(u8 Xpos, u16 Ypos)
{
LCD_WriteReg(R66, Xpos);
LCD_WriteReg(R67, ((Ypos & 0x100)>> 8));
LCD_WriteReg(R68, (Ypos & 0xFF));
}
/*******************************************************************************
* Function Name : LCD_DrawChar
* Description : Draws a character on LCD.
* Input : - Xpos: the Line where to display the character shape.
* This parameter can be one of the following values:
* - Linex: where x can be 0..9
* - Ypos: start column address.
* - c: pointer to the character data.
* Output : None
* Return : None
*******************************************************************************/
void LCD_DrawChar(u8 Xpos, u16 Ypos, uc16 *c)
{
u32 index = 0, i = 0;
u8 Xaddress = 0;
Xaddress = Xpos;
LCD_SetCursor(Xaddress, Ypos);
for(index = 0; index < 24; index++)
{
for(i = 0; i < 16; i++)
{
if((c[index] & (1 << i)) == 0x00)
{
LCD_WriteRAM(BackColor);
}
else
{
LCD_WriteRAM(TextColor);
}
}
Xaddress++;
LCD_SetCursor(Xaddress, Ypos);
}
}
/*******************************************************************************
* Function Name : LCD_DisplayChar
* Description : Displays one character (16dots width, 24dots height).
* Input : - Line: the Line where to display the character shape .
* This parameter can be one of the following values:
* - Linex: where x can be 0..9
* - Column: start column address.
* - Ascii: character ascii code, must be between 0x20 and 0x7E.
* Output : None
* Return : None
*******************************************************************************/
void LCD_DisplayChar(u8 Line, u16 Column, u8 Ascii)
{
Ascii -= 32;
LCD_DrawChar(Line, Column, &ASCII_Table[Ascii * 24]);
}
/*******************************************************************************
* Function Name : LCD_DisplayStringLine
* Description : Displays a maximum of 20 char on the LCD.
* Input : - Line: the Line where to display the character shape .
* This parameter can be one of the following values:
* - Linex: where x can be 0..9
* - *ptr: pointer to string to display on LCD.
* Output : None
* Return : None
*******************************************************************************/
void LCD_DisplayStringLine(u8 Line, u8 *ptr)
{
u32 i = 0;
u16 refcolumn = 319;
/* Send the string character by character on lCD */
while ((*ptr != 0) & (i < 20))
{
/* Display one character on LCD */
LCD_DisplayChar(Line, refcolumn, *ptr);
/* Decrement the column position by 16 */
refcolumn -= 16;
/* Point on the next character */
ptr++;
/* Increment the character counter */
i++;
}
}
/*******************************************************************************
* Function Name : LCD_DisplayString
* Description : Displays a maximum of 200 char on the LCD.
* Input : - Line: the starting Line where to display the character shape.
* This parameter can be one of the following values:
* - Linex: where x can be 0..9
* - *ptr: pointer to string to display on LCD.
* Output : None
* Return : None
*******************************************************************************/
void LCD_DisplayString(u8 Line, u8 *ptr)
{
u32 i = 0, column = 0, index = 0, spaceindex = 0;
u16 refcolumn = 319;
u32 length = 0;
/* Get the string length */
length = StrLength(ptr);
if(length > 200)
{
/* Set the Cursor position */
LCD_SetCursor(Line, 0x013F);
/* Clear the Selected Line */
LCD_ClearLine(Line);
LCD_DisplayStringLine(Line, " String too long ");
}
else
{
/* Set the Cursor position */
LCD_SetCursor(Line, 0x013F);
/* Clear the Selected Line */
LCD_ClearLine(Line);
while(length--)
{
if(index == 20)
{
if(*ptr == 0x20)
{
ptr++;
}
else
{
for(i = 0; i < spaceindex; i++)
{
LCD_DisplayChar(Line, column, ' ');
column -= 16;
}
ptr -= (spaceindex - 1);
length += (spaceindex - 1);
}
Line += 24;
/* Clear the Selected Line */
LCD_ClearLine(Line);
refcolumn = 319;
index = 0;
}
/* Display one character on LCD */
LCD_DisplayChar(Line, refcolumn, *ptr);
/* Increment character number in one line */
index++;
/* Decrement the column position by 16 */
refcolumn -= 16;
/* Point on the next character */
ptr++;
/* Increment the number of character after the last space */
spaceindex++;
if(*ptr == 0x20)
{
spaceindex = 0;
column = refcolumn - 16;
}
}
}
}
/*******************************************************************************
* Function Name : LCD_ScrollText
* Description :
* Input :
* Output : None
* Return : None
*******************************************************************************/
void LCD_ScrollText(u8 Line, u8 *ptr)
{
u32 i = 0, length = 0, x = 0;
u16 refcolumn = 319;
/* Get the string length */
length = StrLength(ptr);
while(1)
{
/* Send the string character by character on lCD */
while ((*ptr != 0) & (i < 20))
{
/* Display one character on LCD */
LCD_DisplayChar(Line, refcolumn, *ptr);
/* Decrement the column position by 16 */
refcolumn -= 16;
/* Point on the next character */
ptr++;
/* Increment the character counter */
i++;
}
vTaskDelay( 100 / portTICK_RATE_MS );
i = 0;
//LCD_ClearLine(Line);
ptr -= length;
x++;
if(refcolumn < 16)
{
x = 0;
}
refcolumn = 319 - (x * 16);
}
}
/*******************************************************************************
* Function Name : LCD_SetDisplayWindow
* Description : Sets a display window
* Input : - Xpos: specifies the X position.
* - Ypos: specifies the Y position.
* - Height: display window height.
* - Width: display window width.
* Output : None
* Return : None
*******************************************************************************/
void LCD_SetDisplayWindow(u8 Xpos, u16 Ypos, u8 Height, u16 Width)
{
LCD_WriteReg(R1, 0xD0);
LCD_WriteReg(R5, 0x14);
LCD_WriteReg(R69, Xpos);
LCD_WriteReg(R70, (Xpos + Height + 1));
LCD_WriteReg(R71, ((Ypos & 0x100)>> 8));
LCD_WriteReg(R72, (Ypos & 0xFF));
LCD_WriteReg(R73, (((Ypos + Width + 1) & 0x100)>> 8));
LCD_WriteReg(R74, ((Ypos + Width + 1) & 0xFF));
LCD_SetCursor(Xpos, Ypos);
}
/*******************************************************************************
* Function Name : LCD_DrawLine
* Description : Displays a line.
* Input : - Xpos: specifies the X position.
* - Ypos: specifies the Y position.
* - Length: line length.
* - Direction: line direction.
* This parameter can be one of the following values: Vertical
* or Horizontal.
* Output : None
* Return : None
*******************************************************************************/
void LCD_DrawLine(u8 Xpos, u16 Ypos, u16 Length, u8 Direction)
{
u32 i = 0;
LCD_SetCursor(Xpos, Ypos);
if(Direction == Horizontal)
{
for(i = 0; i < Length; i++)
{
LCD_WriteRAM(TextColor);
}
}
else
{
for(i = 0; i < Length; i++)
{
LCD_WriteRAM(TextColor);
Xpos++;
LCD_SetCursor(Xpos, Ypos);
}
}
}
/*******************************************************************************
* Function Name : LCD_DrawRect
* Description : Displays a rectangle.
* Input : - Xpos: specifies the X position.
* - Ypos: specifies the Y position.
* - Height: display rectangle height.
* - Width: display rectangle width.
* Output : None
* Return : None
*******************************************************************************/
void LCD_DrawRect(u8 Xpos, u16 Ypos, u8 Height, u16 Width)
{
LCD_DrawLine(Xpos, Ypos, Width, Horizontal);
LCD_DrawLine((Xpos + Height), Ypos, Width, Horizontal);
LCD_DrawLine(Xpos, Ypos, Height, Vertical);
LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, Vertical);
}
/*******************************************************************************
* Function Name : LCD_DrawCircle
* Description : Displays a circle.
* Input : - Xpos: specifies the X position.
* - Ypos: specifies the Y position.
* - Height: display rectangle height.
* - Width: display rectangle width.
* Output : None
* Return : None
*******************************************************************************/
void LCD_DrawCircle(u8 Xpos, u16 Ypos, u16 Radius)
{
s32 D; /* Decision Variable */
u32 CurX; /* Current X Value */
u32 CurY; /* Current Y Value */
D = 3 - (Radius << 1);
CurX = 0;
CurY = Radius;
while (CurX <= CurY)
{
LCD_SetCursor(Xpos + CurX, Ypos + CurY);
LCD_WriteRAM(TextColor);
LCD_SetCursor(Xpos + CurX, Ypos - CurY);
LCD_WriteRAM(TextColor);
LCD_SetCursor(Xpos - CurX, Ypos + CurY);
LCD_WriteRAM(TextColor);
LCD_SetCursor(Xpos - CurX, Ypos - CurY);
LCD_WriteRAM(TextColor);
LCD_SetCursor(Xpos + CurY, Ypos + CurX);
LCD_WriteRAM(TextColor);
LCD_SetCursor(Xpos + CurY, Ypos - CurX);
LCD_WriteRAM(TextColor);
LCD_SetCursor(Xpos - CurY, Ypos + CurX);
LCD_WriteRAM(TextColor);
LCD_SetCursor(Xpos - CurY, Ypos - CurX);
LCD_WriteRAM(TextColor);
if (D < 0)
{
D += (CurX << 2) + 6;
}
else
{
D += ((CurX - CurY) << 2) + 10;
CurY--;
}
CurX++;
}
}
/*******************************************************************************
* Function Name : LCD_DrawMonoPict
* Description : Displays a monocolor picture.
* Input : - Pict: pointer to the picture array.
* Output : None
* Return : None
*******************************************************************************/
void LCD_DrawMonoPict(uc32 *Pict)
{
u32 index = 0, i = 0;
LCD_SetCursor(0, 319);
for(index = 0; index < 2400; index++)
{
for(i = 0; i < 32; i++)
{
if((Pict[index] & (1 << i)) == 0x00)
{
LCD_WriteRAM(BackColor);
}
else
{
LCD_WriteRAM(TextColor);
}
}
}
}
/*******************************************************************************
* Function Name : LCD_DrawBMP
* Description : Displays a bitmap picture loaded in the SPI Flash.
* Input : - BmpAddress: Bmp picture address in the SPI Flash.
* Output : None
* Return : None
*******************************************************************************/
void LCD_DrawBMP(u32 BmpAddress)
{
u32 i = 0;
LCD_WriteReg(R1, 0xD0);
LCD_WriteReg(R5, 0x04);
LCD_SetCursor(239, 0x013F);
SPI_FLASH_StartReadSequence(BmpAddress);
/* Disable SPI1 */
SPI_Cmd(SPI1, DISABLE);
/* SPI in 16-bit mode */
SPI_DataSizeConfig(SPI1, SPI_DataSize_16b);
/* Enable SPI1 */
SPI_Cmd(SPI1, ENABLE);
for(i = 0; i < 76800; i++)
{
LCD_WriteRAM(__REV_HalfWord(SPI_FLASH_SendHalfWord(0xA5A5)));
}
/* Deselect the FLASH: Chip Select high */
SPI_FLASH_ChipSelect(1);
/* Disable SPI1 */
SPI_Cmd(SPI1, DISABLE);
/* SPI in 8-bit mode */
SPI_DataSizeConfig(SPI1, SPI_DataSize_8b);
/* Enable SPI1 */
SPI_Cmd(SPI1, ENABLE);
}
/*******************************************************************************
* Function Name : LCD_WriteReg
* Description : Writes to the selected LCD register.
* Input : - LCD_Reg: address of the selected register.
* - LCD_RegValue: value to write to the selected register.
* Output : None
* Return : None
*******************************************************************************/
void LCD_WriteReg(u8 LCD_Reg, u8 LCD_RegValue)
{
u16 tmp = 0;
LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_RESET);
LCD_CtrlLinesWrite(GPIOD, CtrlPin_RS, Bit_RESET);
LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_RESET);
tmp = LCD_Reg << 8;
tmp |= LCD_RegValue;
SPI_SendData(SPI2, tmp);
while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
{
}
LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_SET);
}
/*******************************************************************************
* Function Name : LCD_ReadReg
* Description : Reads the selected LCD Register.
* Input : None
* Output : None
* Return : LCD Register Value.
*******************************************************************************/
u8 LCD_ReadReg(u8 LCD_Reg)
{
u16 tmp = 0;
LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_RESET);
LCD_CtrlLinesWrite(GPIOD, CtrlPin_RS, Bit_RESET);
LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_RESET);
while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
{
}
SPI_SendData(SPI2, LCD_Reg);
LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_SET);
while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
{
}
SPI_SendData(SPI2, 0xFF);
while(SPI_GetFlagStatus(SPI2, SPI_FLAG_RXNE)== RESET)
{
}
tmp = SPI_ReceiveData(SPI2);
LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_SET);
return tmp;
}
/*******************************************************************************
* Function Name : LCD_WriteRAM
* Description : Writes to the LCD RAM.
* Input : - RGB_Code: the pixel color in RGB mode (5-6-5).
* Output : None
* Return : None
*******************************************************************************/
void LCD_WriteRAM(u16 RGB_Code)
{
LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_RESET);
LCD_CtrlLinesWrite(GPIOD, CtrlPin_RS, Bit_SET);
LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_RESET);
SPI_SendData(SPI2, RGB_Code);
while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
{
}
LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_SET);
}
/*******************************************************************************
* Function Name : LCD_ReadRAM
* Description : Reads the LCD RAM.
* Input : None
* Output : None
* Return : LCD RAM Value.
*******************************************************************************/
u16 LCD_ReadRAM(void)
{
u16 tmp = 0;
LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_SET);
LCD_CtrlLinesWrite(GPIOD, CtrlPin_RS, Bit_SET);
LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_RESET);
while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
{
}
SPI_SendData(SPI2, 0xFF);
while(SPI_GetFlagStatus(SPI2, SPI_FLAG_RXNE)==RESET)
{
}
tmp = SPI_ReceiveData(SPI2);
LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_SET);
return tmp;
}
/*******************************************************************************
* Function Name : LCD_PowerOn
* Description :
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void LCD_PowerOn(void)
{
/* Power On Set */
LCD_WriteReg(R28, 0x73);
LCD_WriteReg(R36, 0x74);
LCD_WriteReg(R30, 0x01);
LCD_WriteReg(R24, 0xC1);
vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */
LCD_WriteReg(R24, 0xE1);
LCD_WriteReg(R24, 0xF1);
vTaskDelay( 60 / portTICK_RATE_MS ); /* Delay 60 ms */
LCD_WriteReg(R24, 0xF5);
vTaskDelay( 60 / portTICK_RATE_MS ); /* Delay 60 ms */
LCD_WriteReg(R27, 0x09);
vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */
LCD_WriteReg(R31, 0x11);
LCD_WriteReg(R32, 0x0E);
LCD_WriteReg(R30, 0x81);
vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */
}
/*******************************************************************************
* Function Name : LCD_DisplayOn
* Description : Enables the Display.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void LCD_DisplayOn(void)
{
LCD_WriteReg(R1, 0x50);
LCD_WriteReg(R5, 0x04);
/* Display On */
LCD_WriteReg(R0, 0x80);
LCD_WriteReg(R59, 0x01);
vTaskDelay( 40 / portTICK_RATE_MS ); /* Delay 40 ms */
LCD_WriteReg(R0, 0x20);
}
/*******************************************************************************
* Function Name : LCD_DisplayOff
* Description : Disables the Display.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void LCD_DisplayOff(void)
{
/* Display Off */
LCD_WriteReg(R0, 0xA0);
vTaskDelay( 40 / portTICK_RATE_MS ); /* Delay 40 ms */
LCD_WriteReg(R59, 0x00);
}
/*******************************************************************************
* Function Name : LCD_CtrlLinesConfig
* Description : Configures LCD control lines in Output Push-Pull mode.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void LCD_CtrlLinesConfig(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
/* Configure NCS (PB.02) in Output Push-Pull mode */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_Init(GPIOB, &GPIO_InitStructure);
/* Configure NWR(RNW), RS (PD.15, PD.07) in Output Push-Pull mode */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_15;
GPIO_Init(GPIOD, &GPIO_InitStructure);
}
/*******************************************************************************
* Function Name : LCD_CtrlLinesWrite
* Description : Sets or reset LCD control lines.
* Input : - GPIOx: where x can be B or D to select the GPIO peripheral.
* - CtrlPins: the Control line. This parameter can be:
* - CtrlPin_NCS: Chip Select pin (PB.02)
* - CtrlPin_NWR: Read/Write Selection pin (PD.15)
* - CtrlPin_RS: Register/RAM Selection pin (PD.07)
* - BitVal: specifies the value to be written to the selected bit.
* This parameter can be:
* - Bit_RESET: to clear the port pin
* - Bit_SET: to set the port pin
* Output : None
* Return : None
*******************************************************************************/
void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, u16 CtrlPins, BitAction BitVal)
{
/* Set or Reset the control line */
GPIO_WriteBit(GPIOx, CtrlPins, BitVal);
}
/*******************************************************************************
* Function Name : LCD_SPIConfig
* Description : Configures the SPI2 interface.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void LCD_SPIConfig(void)
{
SPI_InitTypeDef SPI_InitStructure;
GPIO_InitTypeDef GPIO_InitStructure;
/* Enable GPIOA clock */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
/* Enable SPI2 clock */
RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
/* Configure SPI2 pins: NSS, SCK, MISO and MOSI */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOB, &GPIO_InitStructure);
/* SPI2 Config */
SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
SPI_InitStructure.SPI_DataSize = SPI_DataSize_16b;
SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
SPI_Init(SPI2, &SPI_InitStructure);
/* SPI2 enable */
SPI_Cmd(SPI2, ENABLE);
}
/*******************************************************************************
* Function Name : StrLength
* Description : Returns length of string.
* Input : - Str: Character Pointer.
* Output : None
* Return : String length.
*******************************************************************************/
static u32 StrLength(u8 *Str)
{
u32 Index = 0;
/* Increment the Index unless the end of string */
for(Index = 0; *Str != '\0'; Str++, Index++)
{
}
return Index;
}
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/src/lcd.c | C | oos | 53,242 |
/**
******************************************************************************
* @file stm32f10x_spi.c
* @author MCD Application Team
* @version V3.0.0
* @date 04/06/2009
* @brief This file provides all the SPI firmware functions.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_spi.h"
#include "stm32f10x_rcc.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @defgroup SPI
* @brief SPI driver modules
* @{
*/
/** @defgroup SPI_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup SPI_Private_Defines
* @{
*/
/* SPI SPE mask */
#define CR1_SPE_Set ((uint16_t)0x0040)
#define CR1_SPE_Reset ((uint16_t)0xFFBF)
/* I2S I2SE mask */
#define I2SCFGR_I2SE_Set ((uint16_t)0x0400)
#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF)
/* SPI CRCNext mask */
#define CR1_CRCNext_Set ((uint16_t)0x1000)
/* SPI CRCEN mask */
#define CR1_CRCEN_Set ((uint16_t)0x2000)
#define CR1_CRCEN_Reset ((uint16_t)0xDFFF)
/* SPI SSOE mask */
#define CR2_SSOE_Set ((uint16_t)0x0004)
#define CR2_SSOE_Reset ((uint16_t)0xFFFB)
/* SPI registers Masks */
#define CR1_CLEAR_Mask ((uint16_t)0x3040)
#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)
/* SPI or I2S mode selection masks */
#define SPI_Mode_Select ((uint16_t)0xF7FF)
#define I2S_Mode_Select ((uint16_t)0x0800)
/**
* @}
*/
/** @defgroup SPI_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup SPI_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup SPI_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup SPI_Private_Functions
* @{
*/
/**
* @brief Deinitializes the SPIx peripheral registers to their default
* reset values (Affects also the I2Ss).
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* @retval : None
*/
void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
switch (*(uint32_t*)&SPIx)
{
case SPI1_BASE:
/* Enable SPI1 reset state */
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
/* Release SPI1 from reset state */
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
break;
case SPI2_BASE:
/* Enable SPI2 reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
/* Release SPI2 from reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
break;
case SPI3_BASE:
/* Enable SPI3 reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
/* Release SPI3 from reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
break;
default:
break;
}
}
/**
* @brief Initializes the SPIx peripheral according to the specified
* parameters in the SPI_InitStruct.
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
* contains the configuration information for the specified
* SPI peripheral.
* @retval : None
*/
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
{
uint16_t tmpreg = 0;
/* check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
/* Check the SPI parameters */
assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
/*---------------------------- SPIx CR1 Configuration ------------------------*/
/* Get the SPIx CR1 value */
tmpreg = SPIx->CR1;
/* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
tmpreg &= CR1_CLEAR_Mask;
/* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
master/salve mode, CPOL and CPHA */
/* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
/* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
/* Set LSBFirst bit according to SPI_FirstBit value */
/* Set BR bits according to SPI_BaudRatePrescaler value */
/* Set CPOL bit according to SPI_CPOL value */
/* Set CPHA bit according to SPI_CPHA value */
tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
/* Write to SPIx CR1 */
SPIx->CR1 = tmpreg;
/* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
SPIx->I2SCFGR &= SPI_Mode_Select;
/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
/* Write to SPIx CRCPOLY */
SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
}
/**
* @brief Initializes the SPIx peripheral according to the specified
* parameters in the I2S_InitStruct.
* @param SPIx: where x can be 2 or 3 to select the SPI peripheral
* (configured in I2S mode).
* @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
* contains the configuration information for the specified
* SPI peripheral configured in I2S mode.
* @retval : None
*/
void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
{
uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
uint32_t tmp = 0;
RCC_ClocksTypeDef RCC_Clocks;
/* Check the I2S parameters */
assert_param(IS_SPI_23_PERIPH(SPIx));
assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
/* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask;
SPIx->I2SPR = 0x0002;
/* Get the I2SCFGR register value */
tmpreg = SPIx->I2SCFGR;
/* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
{
i2sodd = (uint16_t)0;
i2sdiv = (uint16_t)2;
}
/* If the requested audio frequency is not the default, compute the prescaler */
else
{
/* Check the frame length (For the Prescaler computing) */
if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
{
/* Packet length is 16 bits */
packetlength = 1;
}
else
{
/* Packet length is 32 bits */
packetlength = 2;
}
/* Get System Clock frequency */
RCC_GetClocksFreq(&RCC_Clocks);
/* Compute the Real divider depending on the MCLK output state with a flaoting point */
if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
{
/* MCLK output is enabled */
tmp = (uint16_t)(((10 * RCC_Clocks.SYSCLK_Frequency) / (256 * I2S_InitStruct->I2S_AudioFreq)) + 5);
}
else
{
/* MCLK output is disabled */
tmp = (uint16_t)(((10 * RCC_Clocks.SYSCLK_Frequency) / (32 * packetlength * I2S_InitStruct->I2S_AudioFreq)) + 5);
}
/* Remove the flaoting point */
tmp = tmp/10;
/* Check the parity of the divider */
i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
/* Compute the i2sdiv prescaler */
i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
i2sodd = (uint16_t) (i2sodd << 8);
}
/* Test if the divider is 1 or 0 */
if ((i2sdiv < 2) || (i2sdiv > 0xFF))
{
/* Set the default values */
i2sdiv = 2;
i2sodd = 0;
}
/* Write to SPIx I2SPR register the computed value */
SPIx->I2SPR = (uint16_t)(i2sdiv | i2sodd | I2S_InitStruct->I2S_MCLKOutput);
/* Configure the I2S with the SPI_InitStruct values */
tmpreg |= (uint16_t)(I2S_Mode_Select | I2S_InitStruct->I2S_Mode | \
I2S_InitStruct->I2S_Standard | I2S_InitStruct->I2S_DataFormat | \
I2S_InitStruct->I2S_CPOL);
/* Write to SPIx I2SCFGR */
SPIx->I2SCFGR = tmpreg;
}
/**
* @brief Fills each SPI_InitStruct member with its default value.
* @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure
* which will be initialized.
* @retval : None
*/
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
{
/*--------------- Reset SPI init structure parameters values -----------------*/
/* Initialize the SPI_Direction member */
SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
/* initialize the SPI_Mode member */
SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
/* initialize the SPI_DataSize member */
SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
/* Initialize the SPI_CPOL member */
SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
/* Initialize the SPI_CPHA member */
SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
/* Initialize the SPI_NSS member */
SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
/* Initialize the SPI_BaudRatePrescaler member */
SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
/* Initialize the SPI_FirstBit member */
SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
/* Initialize the SPI_CRCPolynomial member */
SPI_InitStruct->SPI_CRCPolynomial = 7;
}
/**
* @brief Fills each I2S_InitStruct member with its default value.
* @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure
* which will be initialized.
* @retval : None
*/
void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
{
/*--------------- Reset I2S init structure parameters values -----------------*/
/* Initialize the I2S_Mode member */
I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
/* Initialize the I2S_Standard member */
I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
/* Initialize the I2S_DataFormat member */
I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
/* Initialize the I2S_MCLKOutput member */
I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
/* Initialize the I2S_AudioFreq member */
I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
/* Initialize the I2S_CPOL member */
I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
}
/**
* @brief Enables or disables the specified SPI peripheral.
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* @param NewState: new state of the SPIx peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
*/
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected SPI peripheral */
SPIx->CR1 |= CR1_SPE_Set;
}
else
{
/* Disable the selected SPI peripheral */
SPIx->CR1 &= CR1_SPE_Reset;
}
}
/**
* @brief Enables or disables the specified SPI peripheral (in I2S mode).
* @param SPIx: where x can be 2 or 3 to select the SPI peripheral.
* @param NewState: new state of the SPIx peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
*/
void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_SPI_23_PERIPH(SPIx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected SPI peripheral (in I2S mode) */
SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;
}
else
{
/* Disable the selected SPI peripheral (in I2S mode) */
SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;
}
}
/**
* @brief Enables or disables the specified SPI/I2S interrupts.
* @param SPIx: where x can be :
* 1, 2 or 3 in SPI mode
* 2 or 3 in I2S mode
* @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to be
* enabled or disabled.
* This parameter can be one of the following values:
* @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
* @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
* @arg SPI_I2S_IT_ERR: Error interrupt mask
* @param NewState: new state of the specified SPI/I2S interrupt.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
*/
void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
{
uint16_t itpos = 0, itmask = 0 ;
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
/* Get the SPI/I2S IT index */
itpos = SPI_I2S_IT >> 4;
/* Set the IT mask */
itmask = (uint16_t)((uint16_t)1 << itpos);
if (NewState != DISABLE)
{
/* Enable the selected SPI/I2S interrupt */
SPIx->CR2 |= itmask;
}
else
{
/* Disable the selected SPI/I2S interrupt */
SPIx->CR2 &= (uint16_t)~itmask;
}
}
/**
* @brief Enables or disables the SPIx/I2Sx DMA interface.
* @param SPIx: where x can be :
* 1, 2 or 3 in SPI mode
* 2 or 3 in I2S mode
* @param SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request
* to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
* @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
* @param NewState: new state of the selected SPI/I2S DMA transfer
* request.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
*/
void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));
if (NewState != DISABLE)
{
/* Enable the selected SPI/I2S DMA requests */
SPIx->CR2 |= SPI_I2S_DMAReq;
}
else
{
/* Disable the selected SPI/I2S DMA requests */
SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
}
}
/**
* @brief Transmits a Data through the SPIx/I2Sx peripheral.
* @param SPIx: where x can be :
* 1, 2 or 3 in SPI mode
* 2 or 3 in I2S mode
* @param Data : Data to be transmitted..
* @retval : None
*/
void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
/* Write in the DR register the data to be sent */
SPIx->DR = Data;
}
/**
* @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
* @param SPIx: where x can be :
* 1, 2 or 3 in SPI mode
* 2 or 3 in I2S mode
* @retval : The value of the received data.
*/
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
/* Return the data in the DR register */
return SPIx->DR;
}
/**
* @brief Configures internally by software the NSS pin for the selected
* SPI.
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.
* This parameter can be one of the following values:
* @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
* @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
* @retval : None
*/
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
{
/* Set NSS pin internally by software */
SPIx->CR1 |= SPI_NSSInternalSoft_Set;
}
else
{
/* Reset NSS pin internally by software */
SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
}
}
/**
* @brief Enables or disables the SS output for the selected SPI.
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* @param NewState: new state of the SPIx SS output.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
*/
void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected SPI SS output */
SPIx->CR2 |= CR2_SSOE_Set;
}
else
{
/* Disable the selected SPI SS output */
SPIx->CR2 &= CR2_SSOE_Reset;
}
}
/**
* @brief Configures the data size for the selected SPI.
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* @param SPI_DataSize: specifies the SPI data size.
* This parameter can be one of the following values:
* @arg SPI_DataSize_16b: Set data frame format to 16bit
* @arg SPI_DataSize_8b: Set data frame format to 8bit
* @retval : None
*/
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_SPI_DATASIZE(SPI_DataSize));
/* Clear DFF bit */
SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;
/* Set new DFF bit value */
SPIx->CR1 |= SPI_DataSize;
}
/**
* @brief Transmit the SPIx CRC value.
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* @retval : None
*/
void SPI_TransmitCRC(SPI_TypeDef* SPIx)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
/* Enable the selected SPI CRC transmission */
SPIx->CR1 |= CR1_CRCNext_Set;
}
/**
* @brief Enables or disables the CRC value calculation of the
* transfered bytes.
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* @param NewState: new state of the SPIx CRC value calculation.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
*/
void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected SPI CRC calculation */
SPIx->CR1 |= CR1_CRCEN_Set;
}
else
{
/* Disable the selected SPI CRC calculation */
SPIx->CR1 &= CR1_CRCEN_Reset;
}
}
/**
* @brief Returns the transmit or the receive CRC register value for
* the specified SPI.
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* @param SPI_CRC: specifies the CRC register to be read.
* This parameter can be one of the following values:
* @arg SPI_CRC_Tx: Selects Tx CRC register
* @arg SPI_CRC_Rx: Selects Rx CRC register
* @retval : The selected CRC register value..
*/
uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
{
uint16_t crcreg = 0;
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_SPI_CRC(SPI_CRC));
if (SPI_CRC != SPI_CRC_Rx)
{
/* Get the Tx CRC register */
crcreg = SPIx->TXCRCR;
}
else
{
/* Get the Rx CRC register */
crcreg = SPIx->RXCRCR;
}
/* Return the selected CRC register */
return crcreg;
}
/**
* @brief Returns the CRC Polynomial register value for the specified SPI.
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* @retval : The CRC Polynomial register value.
*/
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
/* Return the CRC polynomial register */
return SPIx->CRCPR;
}
/**
* @brief Selects the data transfer direction in bi-directional mode
* for the specified SPI.
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* @param SPI_Direction: specifies the data transfer direction in
* bi-directional mode.
* This parameter can be one of the following values:
* @arg SPI_Direction_Tx: Selects Tx transmission direction
* @arg SPI_Direction_Rx: Selects Rx receive direction
* @retval : None
*/
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_SPI_DIRECTION(SPI_Direction));
if (SPI_Direction == SPI_Direction_Tx)
{
/* Set the Tx only mode */
SPIx->CR1 |= SPI_Direction_Tx;
}
else
{
/* Set the Rx only mode */
SPIx->CR1 &= SPI_Direction_Rx;
}
}
/**
* @brief Checks whether the specified SPI/I2S flag is set or not.
* @param SPIx: where x can be :
* 1, 2 or 3 in SPI mode
* 2 or 3 in I2S mode
* @param SPI_I2S_FLAG: specifies the SPI/I2S flag to check.
* This parameter can be one of the following values:
* @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
* @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
* @arg SPI_I2S_FLAG_BSY: Busy flag.
* @arg SPI_I2S_FLAG_OVR: Overrun flag.
* @arg SPI_FLAG_MODF: Mode Fault flag.
* @arg SPI_FLAG_CRCERR: CRC Error flag.
* @arg I2S_FLAG_UDR: Underrun Error flag.
* @arg I2S_FLAG_CHSIDE: Channel Side flag.
* @retval : The new state of SPI_I2S_FLAG (SET or RESET).
*/
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
/* Check the status of the specified SPI/I2S flag */
if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
{
/* SPI_I2S_FLAG is set */
bitstatus = SET;
}
else
{
/* SPI_I2S_FLAG is reset */
bitstatus = RESET;
}
/* Return the SPI_I2S_FLAG status */
return bitstatus;
}
/**
* @brief Clears the SPIx CRC Error (CRCERR) flag.
* @param SPIx: where x can be :
* 1, 2 or 3 in SPI mode
* @param SPI_I2S_FLAG: specifies the SPI flag to clear.
* This function clears only CRCERR flag.
* @note
* - OVR (OverRun error) flag is cleared by software sequence: a read
* operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read
* operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
* - UDR (UnderRun error) flag is cleared by a read operation to
* SPI_SR register (SPI_I2S_GetFlagStatus()).
* - MODF (Mode Fault) flag is cleared by software sequence: a read/write
* operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a
* write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
* @retval : None
*/
void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
/* Clear the selected SPI CRC Error (CRCERR) flag */
SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
}
/**
* @brief Checks whether the specified SPI/I2S interrupt has occurred or not.
* @param SPIx: where x can be :
* 1, 2 or 3 in SPI mode
* 2 or 3 in I2S mode
* @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to check.
* This parameter can be one of the following values:
* @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
* @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
* @arg SPI_I2S_IT_OVR: Overrun interrupt.
* @arg SPI_IT_MODF: Mode Fault interrupt.
* @arg SPI_IT_CRCERR: CRC Error interrupt.
* @arg I2S_IT_UDR: Underrun Error interrupt.
* @retval : The new state of SPI_I2S_IT (SET or RESET).
*/
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
{
ITStatus bitstatus = RESET;
uint16_t itpos = 0, itmask = 0, enablestatus = 0;
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
/* Get the SPI/I2S IT index */
itpos = (uint16_t)((uint16_t)0x01 << (SPI_I2S_IT & (uint8_t)0x0F));
/* Get the SPI/I2S IT mask */
itmask = SPI_I2S_IT >> 4;
/* Set the IT mask */
itmask = (uint16_t)((uint16_t)0x01 << itmask);
/* Get the SPI_I2S_IT enable bit status */
enablestatus = (SPIx->CR2 & itmask) ;
/* Check the status of the specified SPI/I2S interrupt */
if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
{
/* SPI_I2S_IT is set */
bitstatus = SET;
}
else
{
/* SPI_I2S_IT is reset */
bitstatus = RESET;
}
/* Return the SPI_I2S_IT status */
return bitstatus;
}
/**
* @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
* @param SPIx: where x can be :
* 1, 2 or 3 in SPI mode
* @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
* This function clears only CRCERR intetrrupt pending bit.
* @note
* - OVR (OverRun Error) interrupt pending bit is cleared by software
* sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData())
* followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
* - UDR (UnderRun Error) interrupt pending bit is cleared by a read
* operation to SPI_SR register (SPI_I2S_GetITStatus()).
* - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
* a read/write operation to SPI_SR register (SPI_I2S_GetITStatus())
* followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable
* the SPI).
* @retval : None
*/
void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
{
uint16_t itpos = 0;
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));
/* Get the SPI IT index */
itpos = (uint16_t)((uint16_t)0x01 << (SPI_I2S_IT & (uint8_t)0x0F));
/* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
SPIx->SR = (uint16_t)~itpos;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_spi.c | C | oos | 27,737 |
;******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
;* File Name : cortexm3_macro.s
;* Author : MCD Application Team
;* Date First Issued : 02/19/2007
;* Description : Instruction wrappers for special Cortex-M3 instructions.
;*******************************************************************************
; History:
; 04/02/2007: V0.2
; 02/19/2007: V0.1
;*******************************************************************************
; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
SECTION .text:CODE(2)
; Exported functions
EXPORT __WFI
EXPORT __WFE
EXPORT __SEV
EXPORT __ISB
EXPORT __DSB
EXPORT __DMB
EXPORT __SVC
EXPORT __MRS_CONTROL
EXPORT __MSR_CONTROL
EXPORT __MRS_PSP
EXPORT __MSR_PSP
EXPORT __MRS_MSP
EXPORT __MSR_MSP
EXPORT __SETPRIMASK
EXPORT __RESETPRIMASK
EXPORT __SETFAULTMASK
EXPORT __RESETFAULTMASK
EXPORT __BASEPRICONFIG
EXPORT __GetBASEPRI
EXPORT __REV_HalfWord
EXPORT __REV_Word
;*******************************************************************************
; Function Name : __WFI
; Description : Assembler function for the WFI instruction.
; Input : None
; Return : None
;*******************************************************************************
__WFI
WFI
BX r14
;*******************************************************************************
; Function Name : __WFE
; Description : Assembler function for the WFE instruction.
; Input : None
; Return : None
;*******************************************************************************
__WFE
WFE
BX r14
;*******************************************************************************
; Function Name : __SEV
; Description : Assembler function for the SEV instruction.
; Input : None
; Return : None
;*******************************************************************************
__SEV
SEV
BX r14
;*******************************************************************************
; Function Name : __ISB
; Description : Assembler function for the ISB instruction.
; Input : None
; Return : None
;*******************************************************************************
__ISB
ISB
BX r14
;*******************************************************************************
; Function Name : __DSB
; Description : Assembler function for the DSB instruction.
; Input : None
; Return : None
;*******************************************************************************
__DSB
DSB
BX r14
;*******************************************************************************
; Function Name : __DMB
; Description : Assembler function for the DMB instruction.
; Input : None
; Return : None
;*******************************************************************************
__DMB
DMB
BX r14
;*******************************************************************************
; Function Name : __SVC
; Description : Assembler function for the SVC instruction.
; Input : None
; Return : None
;*******************************************************************************
__SVC
SVC 0x01
BX r14
;*******************************************************************************
; Function Name : __MRS_CONTROL
; Description : Assembler function for the MRS instruction.
; Input : None
; Return : - r0 : Cortex-M3 CONTROL register value.
;*******************************************************************************
__MRS_CONTROL
MRS r0, CONTROL
BX r14
;*******************************************************************************
; Function Name : __MSR_CONTROL
; Description : Assembler function for the MSR instruction.
; Input : - r0 : Cortex-M3 CONTROL register new value.
; Return : None
;*******************************************************************************
__MSR_CONTROL
MSR CONTROL, r0
ISB
BX r14
;*******************************************************************************
; Function Name : __MRS_PSP
; Description : Assembler function for the MRS instruction.
; Input : None
; Return : - r0 : Process Stack value.
;*******************************************************************************
__MRS_PSP
MRS r0, PSP
BX r14
;*******************************************************************************
; Function Name : __MSR_PSP
; Description : Assembler function for the MSR instruction.
; Input : - r0 : Process Stack new value.
; Return : None
;*******************************************************************************
__MSR_PSP
MSR PSP, r0 ; set Process Stack value
BX r14
;*******************************************************************************
; Function Name : __MRS_MSP
; Description : Assembler function for the MRS instruction.
; Input : None
; Return : - r0 : Main Stack value.
;*******************************************************************************
__MRS_MSP
MRS r0, MSP
BX r14
;*******************************************************************************
; Function Name : __MSR_MSP
; Description : Assembler function for the MSR instruction.
; Input : - r0 : Main Stack new value.
; Return : None
;*******************************************************************************
__MSR_MSP
MSR MSP, r0 ; set Main Stack value
BX r14
;*******************************************************************************
; Function Name : __SETPRIMASK
; Description : Assembler function to set the PRIMASK.
; Input : None
; Return : None
;*******************************************************************************
__SETPRIMASK
CPSID i
BX r14
;*******************************************************************************
; Function Name : __RESETPRIMASK
; Description : Assembler function to reset the PRIMASK.
; Input : None
; Return : None
;*******************************************************************************
__RESETPRIMASK
CPSIE i
BX r14
;*******************************************************************************
; Function Name : __SETFAULTMASK
; Description : Assembler function to set the FAULTMASK.
; Input : None
; Return : None
;*******************************************************************************
__SETFAULTMASK
CPSID f
BX r14
;*******************************************************************************
; Function Name : __RESETFAULTMASK
; Description : Assembler function to reset the FAULTMASK.
; Input : None
; Return : None
;*******************************************************************************
__RESETFAULTMASK
CPSIE f
BX r14
;*******************************************************************************
; Function Name : __BASEPRICONFIG
; Description : Assembler function to set the Base Priority.
; Input : - r0 : Base Priority new value
; Return : None
;*******************************************************************************
__BASEPRICONFIG
MSR BASEPRI, r0
BX r14
;*******************************************************************************
; Function Name : __GetBASEPRI
; Description : Assembler function to get the Base Priority value.
; Input : None
; Return : - r0 : Base Priority value
;*******************************************************************************
__GetBASEPRI
MRS r0, BASEPRI_MAX
BX r14
;*******************************************************************************
; Function Name : __REV_HalfWord
; Description : Reverses the byte order in HalfWord(16-bit) input variable.
; Input : - r0 : specifies the input variable
; Return : - r0 : holds tve variable value after byte reversing.
;*******************************************************************************
__REV_HalfWord
REV16 r0, r0
BX r14
;*******************************************************************************
; Function Name : __REV_Word
; Description : Reverses the byte order in Word(32-bit) input variable.
; Input : - r0 : specifies the input variable
; Return : - r0 : holds tve variable value after byte reversing.
;*******************************************************************************
__REV_Word
REV r0, r0
BX r14
END
;******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE*****
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/src/cortexm3_macro_iar.s | Unix Assembly | oos | 9,440 |
/**
******************************************************************************
* @file stm32f10x_dac.c
* @author MCD Application Team
* @version V3.0.0
* @date 04/06/2009
* @brief This file provides all the DAC firmware functions.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_dac.h"
#include "stm32f10x_rcc.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @defgroup DAC
* @brief DAC driver modules
* @{
*/
/** @defgroup DAC_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup DAC_Private_Defines
* @{
*/
/* DAC EN mask */
#define CR_EN_Set ((uint32_t)0x00000001)
/* DAC DMAEN mask */
#define CR_DMAEN_Set ((uint32_t)0x00001000)
/* CR register Mask */
#define CR_CLEAR_Mask ((uint32_t)0x00000FFE)
/* DAC SWTRIG mask */
#define SWTRIGR_SWTRIG_Set ((uint32_t)0x00000001)
/* DAC Dual Channels SWTRIG masks */
#define DUAL_SWTRIG_Set ((uint32_t)0x00000003)
#define DUAL_SWTRIG_Reset ((uint32_t)0xFFFFFFFC)
/* DHR registers offsets */
#define DHR12R1_Offset ((uint32_t)0x00000008)
#define DHR12R2_Offset ((uint32_t)0x00000014)
#define DHR12RD_Offset ((uint32_t)0x00000020)
/* DOR register offset */
#define DOR_Offset ((uint32_t)0x0000002C)
/**
* @}
*/
/** @defgroup DAC_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup DAC_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup DAC_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup DAC_Private_Functions
* @{
*/
/**
* @brief Deinitializes the DAC peripheral registers to their default
* reset values.
* @param None
* @retval : None
*/
void DAC_DeInit(void)
{
/* Enable DAC reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
/* Release DAC from reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
}
/**
* @brief Initializes the DAC peripheral according to the specified
* parameters in the DAC_InitStruct.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
* contains the configuration information for the specified
* DAC channel.
* @retval : None
*/
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
{
uint32_t tmpreg1 = 0, tmpreg2 = 0;
/* Check the DAC parameters */
assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
/*---------------------------- DAC CR Configuration --------------------------*/
/* Get the DAC CR value */
tmpreg1 = DAC->CR;
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
tmpreg1 &= ~(CR_CLEAR_Mask << DAC_Channel);
/* Configure for the selected DAC channel: buffer output, trigger, wave genration,
mask/amplitude for wave genration */
/* Set TSELx and TENx bits according to DAC_Trigger value */
/* Set WAVEx bits according to DAC_WaveGeneration value */
/* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
/* Set BOFFx bit according to DAC_OutputBuffer value */
tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
/* Calculate CR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << DAC_Channel;
/* Write to DAC CR */
DAC->CR = tmpreg1;
}
/**
* @brief Fills each DAC_InitStruct member with its default value.
* @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure
* which will be initialized.
* @retval : None
*/
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
{
/*--------------- Reset DAC init structure parameters values -----------------*/
/* Initialize the DAC_Trigger member */
DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
/* Initialize the DAC_WaveGeneration member */
DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
/* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
/* Initialize the DAC_OutputBuffer member */
DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
}
/**
* @brief Enables or disables the specified DAC channel.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param NewState: new state of the DAC channel.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
*/
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DAC channel */
DAC->CR |= CR_EN_Set << DAC_Channel;
}
else
{
/* Disable the selected DAC channel */
DAC->CR &= ~(CR_EN_Set << DAC_Channel);
}
}
/**
* @brief Enables or disables the specified DAC channel DMA request.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param NewState: new state of the selected DAC channel DMA request.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
*/
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DAC channel DMA request */
DAC->CR |= CR_DMAEN_Set << DAC_Channel;
}
else
{
/* Disable the selected DAC channel DMA request */
DAC->CR &= ~(CR_DMAEN_Set << DAC_Channel);
}
}
/**
* @brief Enables or disables the selected DAC channel software trigger.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param NewState: new state of the selected DAC channel software trigger.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
*/
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable software trigger for the selected DAC channel */
DAC->SWTRIGR |= SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4);
}
else
{
/* Disable software trigger for the selected DAC channel */
DAC->SWTRIGR &= ~(SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4));
}
}
/**
* @brief Enables or disables simultaneously the two DAC channels software
* triggers.
* @param NewState: new state of the DAC channels software triggers.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
*/
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable software trigger for both DAC channels */
DAC->SWTRIGR |= DUAL_SWTRIG_Set ;
}
else
{
/* Disable software trigger for both DAC channels */
DAC->SWTRIGR &= DUAL_SWTRIG_Reset;
}
}
/**
* @brief Enables or disables the selected DAC channel wave generation.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_Wave: Specifies the wave type to enable or disable.
* This parameter can be one of the following values:
* @arg DAC_Wave_Noise: noise wave generation
* @arg DAC_Wave_Triangle: triangle wave generation
* @param NewState: new state of the selected DAC channel wave generation.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
*/
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_WAVE(DAC_Wave));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected wave generation for the selected DAC channel */
DAC->CR |= DAC_Wave << DAC_Channel;
}
else
{
/* Disable the selected wave generation for the selected DAC channel */
DAC->CR &= ~(DAC_Wave << DAC_Channel);
}
}
/**
* @brief Set the specified data holding register value for DAC channel1.
* @param DAC_Align: Specifies the data alignement for DAC channel1.
* This parameter can be one of the following values:
* @arg DAC_Align_8b_R: 8bit right data alignement selected
* @arg DAC_Align_12b_L: 12bit left data alignement selected
* @arg DAC_Align_12b_R: 12bit right data alignement selected
* @param Data : Data to be loaded in the selected data holding
* register.
* @retval : None
*/
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
{
/* Check the parameters */
assert_param(IS_DAC_ALIGN(DAC_Align));
assert_param(IS_DAC_DATA(Data));
/* Set the DAC channel1 selected data holding register */
*((__IO uint32_t *)(DAC_BASE + DHR12R1_Offset + DAC_Align)) = (uint32_t)Data;
}
/**
* @brief Set the specified data holding register value for DAC channel2.
* @param DAC_Align: Specifies the data alignement for DAC channel2.
* This parameter can be one of the following values:
* @arg DAC_Align_8b_R: 8bit right data alignement selected
* @arg DAC_Align_12b_L: 12bit left data alignement selected
* @arg DAC_Align_12b_R: 12bit right data alignement selected
* @param Data : Data to be loaded in the selected data holding
* register.
* @retval : None
*/
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
{
/* Check the parameters */
assert_param(IS_DAC_ALIGN(DAC_Align));
assert_param(IS_DAC_DATA(Data));
/* Set the DAC channel2 selected data holding register */
*((__IO uint32_t *)(DAC_BASE + DHR12R2_Offset + DAC_Align)) = (uint32_t)Data;
}
/**
* @brief Set the specified data holding register value for dual channel
* DAC.
* @param DAC_Align: Specifies the data alignement for dual channel DAC.
* This parameter can be one of the following values:
* @arg DAC_Align_8b_R: 8bit right data alignement selected
* @arg DAC_Align_12b_L: 12bit left data alignement selected
* @arg DAC_Align_12b_R: 12bit right data alignement selected
* @param Data2: Data for DAC Channel2 to be loaded in the selected data
* holding register.
* @param Data1: Data for DAC Channel1 to be loaded in the selected data
* holding register.
* @retval : None
*/
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
{
uint32_t data = 0;
/* Check the parameters */
assert_param(IS_DAC_ALIGN(DAC_Align));
assert_param(IS_DAC_DATA(Data1));
assert_param(IS_DAC_DATA(Data2));
/* Calculate and set dual DAC data holding register value */
if (DAC_Align == DAC_Align_8b_R)
{
data = ((uint32_t)Data2 << 8) | Data1;
}
else
{
data = ((uint32_t)Data2 << 16) | Data1;
}
/* Set the dual DAC selected data holding register */
*((__IO uint32_t *)(DAC_BASE + DHR12RD_Offset + DAC_Align)) = data;
}
/**
* @brief Returns the last data output value of the selected DAC cahnnel.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @retval : The selected DAC channel data output value.
*/
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
/* Returns the DAC channel data output register value */
return (uint16_t) (*(__IO uint32_t*)(DAC_BASE + DOR_Offset + ((uint32_t)DAC_Channel >> 2)));
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_dac.c | C | oos | 13,723 |
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32fxxx_eth.c
* Author : MCD Application Team
* Version : V1.0.0
* Date : 12/17/2008
* Updates : 05/2009 Driver optimization.
* - No copy. DMA directly uses Stack packets.
* Desciption : This file provides all the ETHERNET firmware functions.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* For the delays. */
#include "FreeRTOS.h"
#include "task.h"
/* Includes ------------------------------------------------------------------*/
#include "stm32fxxx_eth.h"
#include "stm32f10x_rcc.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */
ETH_DMADESCTypeDef *DMATxDescToSet;
ETH_DMADESCTypeDef *DMARxDescToGet;
ETH_DMADESCTypeDef *DMAPTPTxDescToSet;
ETH_DMADESCTypeDef *DMAPTPRxDescToGet;
/* ETHERNET MAC address offsets */
#define ETH_MAC_AddrHighBase (ETH_MAC_BASE + 0x40) /* ETHERNET MAC address high offset */
#define ETH_MAC_AddrLowBase (ETH_MAC_BASE + 0x44) /* ETHERNET MAC address low offset */
/* ETHERNET MACMIIAR register Mask */
#define MACMIIAR_CR_Mask ((u32)0xFFFFFFE3)
/* ETHERNET MACCR register Mask */
#define MACCR_CLEAR_Mask ((u32)0xFF20810F)
/* ETHERNET MACFCR register Mask */
#define MACFCR_CLEAR_Mask ((u32)0x0000FF41)
/* ETHERNET DMAOMR register Mask */
#define DMAOMR_CLEAR_Mask ((u32)0xF8DE3F23)
/* ETHERNET Remote Wake-up frame register length */
#define ETH_WakeupRegisterLength 8
/* ETHERNET Missed frames counter Shift */
#define ETH_DMA_RxOverflowMissedFramesCounterShift 17
/* ETHERNET DMA Tx descriptors Collision Count Shift */
#define ETH_DMATxDesc_CollisionCountShift 3
/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
#define ETH_DMATxDesc_BufferSize2Shift 16
/* ETHERNET DMA Rx descriptors Frame Length Shift */
#define ETH_DMARxDesc_FrameLengthShift 16
/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
#define ETH_DMARxDesc_Buffer2SizeShift 16
/* ETHERNET errors */
#define ETH_ERROR ((u32)0)
#define ETH_SUCCESS ((u32)1)
#define ethFIVE_SECONDS ( 5000 / portTICK_RATE_MS )
#define ethHUNDRED_MS ( 100 / portTICK_RATE_MS )
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : ETH_DeInit
* Desciption : Deinitializes the ETHERNET peripheral registers to their
* default reset values.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void ETH_DeInit(void)
{
// RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, ENABLE);
// RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, DISABLE);
}
/*******************************************************************************
* Function Name : ETH_Init
* Desciption : Initializes the ETHERNET peripheral according to the specified
* parameters in the ETH_InitStruct .
* Input : - ETH_InitStruct: pointer to a ETH_InitTypeDef structure
* that contains the configuration information for the
* specified ETHERNET peripheral.
* Output : None
* Return : None
*******************************************************************************/
u32 ETH_Init(ETH_InitTypeDef* ETH_InitStruct, u16 PHYAddress)
{
u32 RegValue = 0, tmpreg = 0;
RCC_ClocksTypeDef rcc_clocks;
u32 hclk = 60000000;
u32 timeout = 0;
/* Check the parameters */
/* MAC --------------------------*/
eth_assert_param(IS_ETH_AUTONEGOTIATION(ETH_InitStruct->ETH_AutoNegotiation));
eth_assert_param(IS_ETH_WATCHDOG(ETH_InitStruct->ETH_Watchdog));
eth_assert_param(IS_ETH_JABBER(ETH_InitStruct->ETH_Jabber));
eth_assert_param(IS_ETH_JUMBO_FRAME(ETH_InitStruct->ETH_JumboFrame));
eth_assert_param(IS_ETH_INTER_FRAME_GAP(ETH_InitStruct->ETH_InterFrameGap));
eth_assert_param(IS_ETH_CARRIER_SENSE(ETH_InitStruct->ETH_CarrierSense));
eth_assert_param(IS_ETH_SPEED(ETH_InitStruct->ETH_Speed));
eth_assert_param(IS_ETH_RECEIVE_OWN(ETH_InitStruct->ETH_ReceiveOwn));
eth_assert_param(IS_ETH_LOOPBACK_MODE(ETH_InitStruct->ETH_LoopbackMode));
eth_assert_param(IS_ETH_DUPLEX_MODE(ETH_InitStruct->ETH_Mode));
eth_assert_param(IS_ETH_CHECKSUM_OFFLOAD(ETH_InitStruct->ETH_ChecksumOffload));
eth_assert_param(IS_ETH_RETRY_TRANSMISSION(ETH_InitStruct->ETH_RetryTransmission));
eth_assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(ETH_InitStruct->ETH_AutomaticPadCRCStrip));
eth_assert_param(IS_ETH_BACKOFF_LIMIT(ETH_InitStruct->ETH_BackOffLimit));
eth_assert_param(IS_ETH_DEFERRAL_CHECK(ETH_InitStruct->ETH_DeferralCheck));
eth_assert_param(IS_ETH_RECEIVE_ALL(ETH_InitStruct->ETH_ReceiveAll));
eth_assert_param(IS_ETH_SOURCE_ADDR_FILTER(ETH_InitStruct->ETH_SourceAddrFilter));
eth_assert_param(IS_ETH_CONTROL_FRAMES(ETH_InitStruct->ETH_PassControlFrames));
eth_assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(ETH_InitStruct->ETH_BroadcastFramesReception));
eth_assert_param(IS_ETH_DESTINATION_ADDR_FILTER(ETH_InitStruct->ETH_DestinationAddrFilter));
eth_assert_param(IS_ETH_PROMISCUOUS_MODE(ETH_InitStruct->ETH_PromiscuousMode));
eth_assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(ETH_InitStruct->ETH_MulticastFramesFilter));
eth_assert_param(IS_ETH_UNICAST_FRAMES_FILTER(ETH_InitStruct->ETH_UnicastFramesFilter));
eth_assert_param(IS_ETH_PAUSE_TIME(ETH_InitStruct->ETH_PauseTime));
eth_assert_param(IS_ETH_ZEROQUANTA_PAUSE(ETH_InitStruct->ETH_ZeroQuantaPause));
eth_assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(ETH_InitStruct->ETH_PauseLowThreshold));
eth_assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(ETH_InitStruct->ETH_UnicastPauseFrameDetect));
eth_assert_param(IS_ETH_RECEIVE_FLOWCONTROL(ETH_InitStruct->ETH_ReceiveFlowControl));
eth_assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(ETH_InitStruct->ETH_TransmitFlowControl));
eth_assert_param(IS_ETH_VLAN_TAG_COMPARISON(ETH_InitStruct->ETH_VLANTagComparison));
eth_assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(ETH_InitStruct->ETH_VLANTagIdentifier));
/* DMA --------------------------*/
eth_assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame));
eth_assert_param(IS_ETH_RECEIVE_STORE_FORWARD(ETH_InitStruct->ETH_ReceiveStoreForward));
eth_assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(ETH_InitStruct->ETH_FlushReceivedFrame));
eth_assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(ETH_InitStruct->ETH_TransmitStoreForward));
eth_assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(ETH_InitStruct->ETH_TransmitThresholdControl));
eth_assert_param(IS_ETH_FORWARD_ERROR_FRAMES(ETH_InitStruct->ETH_ForwardErrorFrames));
eth_assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(ETH_InitStruct->ETH_ForwardUndersizedGoodFrames));
eth_assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(ETH_InitStruct->ETH_ReceiveThresholdControl));
eth_assert_param(IS_ETH_SECOND_FRAME_OPERATE(ETH_InitStruct->ETH_SecondFrameOperate));
eth_assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(ETH_InitStruct->ETH_AddressAlignedBeats));
eth_assert_param(IS_ETH_FIXED_BURST(ETH_InitStruct->ETH_FixedBurst));
eth_assert_param(IS_ETH_RXDMA_BURST_LENGTH(ETH_InitStruct->ETH_RxDMABurstLength));
eth_assert_param(IS_ETH_TXDMA_BURST_LENGTH(ETH_InitStruct->ETH_TxDMABurstLength));
eth_assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(ETH_InitStruct->ETH_DescriptorSkipLength));
eth_assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(ETH_InitStruct->ETH_DMAArbitration));
/*--------------------------------- MAC Config -------------------------------*/
/*----------------------- ETHERNET MACMIIAR Configuration --------------------*/
/* Get the ETHERNET MACMIIAR value */
tmpreg = ETH_MAC->MACMIIAR;
/* Clear CSR Clock Range CR[2:0] bits */
tmpreg &= MACMIIAR_CR_Mask;
/* Get hclk frequency value */
RCC_GetClocksFreq(&rcc_clocks);
hclk = rcc_clocks.HCLK_Frequency;
/* Set CR bits depending on hclk value */
if((hclk >= 20000000)&&(hclk < 35000000))
{
/* CSR Clock Range between 20-35 MHz */
tmpreg |= (u32)ETH_MACMIIAR_CR_Div16;
}
else if((hclk >= 35000000)&&(hclk < 60000000))
{
/* CSR Clock Range between 35-60 MHz */
tmpreg |= (u32)ETH_MACMIIAR_CR_Div26;
}
else /* ((hclk >= 60000000)&&(hclk <= 72000000)) */
{
/* CSR Clock Range between 60-72 MHz */
tmpreg |= (u32)ETH_MACMIIAR_CR_Div42;
}
/* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
ETH_MAC->MACMIIAR = (u32)tmpreg;
/*--------------------- PHY initialization and configuration -----------------*/
/* Put the PHY in reset mode */
if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset)))
{
/* Return ERROR in case of write timeout */
return ETH_ERROR;
}
/* Delay to assure PHY reset */
vTaskDelay( 250 / portTICK_RATE_MS );
if(ETH_InitStruct->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable)
{
/* We wait for linked satus... */
timeout = 0;
do
{
/* Wait 100ms before checking for a link again. */
vTaskDelay( ethHUNDRED_MS );
timeout++;
/* Don't wait any longer than 5 seconds. */
} while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_Linked_Status) && (timeout < ( ethFIVE_SECONDS / ethHUNDRED_MS ) ) );
/* Return ERROR in case of timeout */
if(timeout == ( ethFIVE_SECONDS / ethHUNDRED_MS ))
{
return ETH_ERROR;
}
/* Enable Auto-Negotiation */
if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_AutoNegotiation)))
{
/* Return ERROR in case of write timeout */
return ETH_ERROR;
}
/* Reset Timeout counter */
timeout = 0;
/* Wait until the autonegotiation will be completed */
do
{
/* Wait 100ms before checking for negotiation to complete. */
vTaskDelay( ethHUNDRED_MS );
timeout++;
/* Don't wait longer than 5 seconds. */
} while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < ( ethFIVE_SECONDS / ethHUNDRED_MS ) ) );
/* Return ERROR in case of timeout */
if(timeout == ( ethFIVE_SECONDS / ethHUNDRED_MS ))
{
return ETH_ERROR;
}
/* Reset Timeout counter */
timeout = 0;
/* Read the result of the autonegotiation */
RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_SR);
/* Configure the MAC with the Duplex Mode fixed by the autonegotiation process */
if((RegValue & PHY_Duplex_Status) != (u32)RESET)
{
/* Set Ethernet duplex mode to FullDuplex following the autonegotiation */
ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex;
}
else
{
/* Set Ethernet duplex mode to HalfDuplex following the autonegotiation */
ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;
}
/* Configure the MAC with the speed fixed by the autonegotiation process */
if(RegValue & PHY_Speed_Status)
{
/* Set Ethernet speed to 100M following the autonegotiation */
ETH_InitStruct->ETH_Speed = ETH_Speed_10M;
}
else
{
/* Set Ethernet speed to 10M following the autonegotiation */
ETH_InitStruct->ETH_Speed = ETH_Speed_100M;
}
}
// else
{
if(!ETH_WritePHYRegister(PHYAddress, PHY_BCR, ((u16)(ETH_InitStruct->ETH_Mode >> 3) |
(u16)(ETH_InitStruct->ETH_Speed >> 1))))
{
/* Return ERROR in case of write timeout */
return ETH_ERROR;
}
vTaskDelay( 250 / portTICK_RATE_MS );
}
/*------------------------- ETHERNET MACCR Configuration ---------------------*/
/* Get the ETHERNET MACCR value */
tmpreg = ETH_MAC->MACCR;
/* Clear WD, PCE, PS, TE and RE bits */
tmpreg &= MACCR_CLEAR_Mask;
/* Set the WD bit according to ETH_Watchdog value */
/* Set the JD: bit according to ETH_Jabber value */
/* Set the JE bit according to ETH_JumboFrame value */
/* Set the IFG bit according to ETH_InterFrameGap value */
/* Set the DCRS bit according to ETH_CarrierSense value */
/* Set the FES bit according to ETH_Speed value */
/* Set the DO bit according to ETH_ReceiveOwn value */
/* Set the LM bit according to ETH_LoopbackMode value */
/* Set the DM bit according to ETH_Mode value */
/* Set the IPC bit according to ETH_ChecksumOffload value */
/* Set the DR bit according to ETH_RetryTransmission value */
/* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */
/* Set the BL bit according to ETH_BackOffLimit value */
/* Set the DC bit according to ETH_DeferralCheck value */
tmpreg |= (u32)(ETH_InitStruct->ETH_Watchdog |
ETH_InitStruct->ETH_Jabber |
ETH_InitStruct->ETH_JumboFrame |
ETH_InitStruct->ETH_InterFrameGap |
ETH_InitStruct->ETH_CarrierSense |
ETH_InitStruct->ETH_Speed |
ETH_InitStruct->ETH_ReceiveOwn |
ETH_InitStruct->ETH_LoopbackMode |
ETH_InitStruct->ETH_Mode |
ETH_InitStruct->ETH_ChecksumOffload |
ETH_InitStruct->ETH_RetryTransmission |
ETH_InitStruct->ETH_AutomaticPadCRCStrip |
ETH_InitStruct->ETH_BackOffLimit |
ETH_InitStruct->ETH_DeferralCheck);
/* Write to ETHERNET MACCR */
ETH_MAC->MACCR = (u32)tmpreg;
/*------------------------ ETHERNET MACFFR Configuration ---------------------*/
/* Set the RA bit according to ETH_ReceiveAll value */
/* Set the SAF and SAIF bits according to ETH_SourceAddrFilter value */
/* Set the PCF bit according to ETH_PassControlFrames value */
/* Set the DBF bit according to ETH_BroadcastFramesReception value */
/* Set the DAIF bit according to ETH_DestinationAddrFilter value */
/* Set the PR bit according to ETH_PromiscuousMode value */
/* Set the PM, HMC and HPF bits according to ETH_MulticastFramesFilter value */
/* Set the HUC and HPF bits according to ETH_UnicastFramesFilter value */
/* Write to ETHERNET MACFFR */
ETH_MAC->MACFFR = (u32)(ETH_InitStruct->ETH_ReceiveAll |
ETH_InitStruct->ETH_SourceAddrFilter |
ETH_InitStruct->ETH_PassControlFrames |
ETH_InitStruct->ETH_BroadcastFramesReception |
ETH_InitStruct->ETH_DestinationAddrFilter |
ETH_InitStruct->ETH_PromiscuousMode |
ETH_InitStruct->ETH_MulticastFramesFilter |
ETH_InitStruct->ETH_UnicastFramesFilter);
/*---------------- ETHERNET MACHTHR and MACHTLR Configuration ----------------*/
/* Write to ETHERNET MACHTHR */
ETH_MAC->MACHTHR = (u32)ETH_InitStruct->ETH_HashTableHigh;
/* Write to ETHERNET MACHTLR */
ETH_MAC->MACHTLR = (u32)ETH_InitStruct->ETH_HashTableLow;
/*------------------------ ETHERNET MACFCR Configuration ---------------------*/
/* Get the ETHERNET MACFCR value */
tmpreg = ETH_MAC->MACFCR;
/* Clear xx bits */
tmpreg &= MACFCR_CLEAR_Mask;
/* Set the PT bit according to ETH_PauseTime value */
/* Set the DZPQ bit according to ETH_ZeroQuantaPause value */
/* Set the PLT bit according to ETH_PauseLowThreshold value */
/* Set the UP bit according to ETH_UnicastPauseFrameDetect value */
/* Set the RFE bit according to ETH_ReceiveFlowControl value */
/* Set the TFE bit according to ETH_TransmitFlowControl value */
tmpreg |= (u32)((ETH_InitStruct->ETH_PauseTime << 16) |
ETH_InitStruct->ETH_ZeroQuantaPause |
ETH_InitStruct->ETH_PauseLowThreshold |
ETH_InitStruct->ETH_UnicastPauseFrameDetect |
ETH_InitStruct->ETH_ReceiveFlowControl |
ETH_InitStruct->ETH_TransmitFlowControl);
/* Write to ETHERNET MACFCR */
ETH_MAC->MACFCR = (u32)tmpreg;
/*------------------------ ETHERNET MACVLANTR Configuration ------------------*/
/* Set the ETV bit according to ETH_VLANTagComparison value */
/* Set the VL bit according to ETH_VLANTagIdentifier value */
ETH_MAC->MACVLANTR = (u32)(ETH_InitStruct->ETH_VLANTagComparison |
ETH_InitStruct->ETH_VLANTagIdentifier);
#ifdef _ETH_DMA
/*--------------------------------- DMA Config -------------------------------*/
/*------------------------ ETHERNET DMAOMR Configuration ---------------------*/
/* Get the ETHERNET DMAOMR value */
tmpreg = ETH_DMA->DMAOMR;
/* Clear xx bits */
tmpreg &= DMAOMR_CLEAR_Mask;
/* Set the DT bit according to ETH_DropTCPIPChecksumErrorFrame value */
/* Set the RSF bit according to ETH_ReceiveStoreForward value */
/* Set the DFF bit according to ETH_FlushReceivedFrame value */
/* Set the TSF bit according to ETH_TransmitStoreForward value */
/* Set the TTC bit according to ETH_TransmitThresholdControl value */
/* Set the FEF bit according to ETH_ForwardErrorFrames value */
/* Set the FUF bit according to ETH_ForwardUndersizedGoodFrames value */
/* Set the RTC bit according to ETH_ReceiveThresholdControl value */
/* Set the OSF bit according to ETH_SecondFrameOperate value */
tmpreg |= (u32)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame |
ETH_InitStruct->ETH_ReceiveStoreForward |
ETH_InitStruct->ETH_FlushReceivedFrame |
ETH_InitStruct->ETH_TransmitStoreForward |
ETH_InitStruct->ETH_TransmitThresholdControl |
ETH_InitStruct->ETH_ForwardErrorFrames |
ETH_InitStruct->ETH_ForwardUndersizedGoodFrames |
ETH_InitStruct->ETH_ReceiveThresholdControl |
ETH_InitStruct->ETH_SecondFrameOperate);
/* Write to ETHERNET DMAOMR */
ETH_DMA->DMAOMR = (u32)tmpreg;
/*------------------------ ETHERNET DMABMR Configuration ---------------------*/
/* Set the AAL bit according to ETH_AddressAlignedBeats value */
/* Set the FB bit according to ETH_FixedBurst value */
/* Set the RPBL and 4*PBL bits according to ETH_RxDMABurstLength value */
/* Set the PBL and 4*PBL bits according to ETH_TxDMABurstLength value */
/* Set the DSL bit according to ETH_DesciptorSkipLength value */
/* Set the PR and DA bits according to ETH_DMAArbitration value */
ETH_DMA->DMABMR = (u32)(ETH_InitStruct->ETH_AddressAlignedBeats |
ETH_InitStruct->ETH_FixedBurst |
ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
ETH_InitStruct->ETH_TxDMABurstLength |
(ETH_InitStruct->ETH_DescriptorSkipLength << 2) |
ETH_InitStruct->ETH_DMAArbitration |
ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
#endif /* _ETH_DMA */
/* Return Ethernet configuration success */
return ETH_SUCCESS;
}
/*******************************************************************************
* Function Name : ETH_StructInit
* Desciption : Fills each ETH_InitStruct member with its default value.
* Input : - ETH_InitStruct: pointer to a ETH_InitTypeDef structure
* which will be initialized.
* Output : None
* Return : None
*******************************************************************************/
void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct)
{
/* ETH_InitStruct members default value */
/*------------------------ MAC -----------------------------------*/
ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Disable;
ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable;
ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable;
ETH_InitStruct->ETH_JumboFrame = ETH_JumboFrame_Disable;
ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit;
ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable;
ETH_InitStruct->ETH_Speed = ETH_Speed_10M;
ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable;
ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable;
ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;
ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable;
ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable;
ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10;
ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable;
ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable;
ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable;
ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll;
ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;
ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal;
ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
ETH_InitStruct->ETH_HashTableHigh = 0x0;
ETH_InitStruct->ETH_HashTableLow = 0x0;
ETH_InitStruct->ETH_PauseTime = 0x0;
ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable;
ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4;
ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable;
ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable;
ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable;
ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit;
ETH_InitStruct->ETH_VLANTagIdentifier = 0x0;
#ifdef _ETH_DMA
/*------------------------ DMA -----------------------------------*/
ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable;
ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Disable;
ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes;
ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes;
ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable;
ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Disable;
ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat;
ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat;
ETH_InitStruct->ETH_DescriptorSkipLength = 0x0;
ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1;
#endif /* _ETH_DMA */
}
/*******************************************************************************
* Function Name : ETH_Start
* Desciption : Enables ENET MAC and DMA reception/transmission
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void ETH_Start(void)
{
/* Enable transmit state machine of the MAC for transmission on the MII */
ETH_MACTransmissionCmd(ENABLE);
/* Flush Transmit FIFO */
ETH_FlushTransmitFIFO();
/* Enable receive state machine of the MAC for reception from the MII */
ETH_MACReceptionCmd(ENABLE);
#ifdef _ETH_DMA
/* Start DMA transmission */
ETH_DMATransmissionCmd(ENABLE);
/* Start DMA reception */
ETH_DMAReceptionCmd(ENABLE);
#endif /* _ETH_DMA */
}
#ifdef _ETH_DMA
/*******************************************************************************
* Function Name : ETH_HandleTxPkt
* Desciption : Transmits a packet, from application buffer, pointed by ppkt.
* Input : - ppkt: pointer to application packet Buffer.
* - FrameLength: Tx Packet size.
* Output : None
* Return : ETH_ERROR: in case of Tx desc owned by DMA
* ETH_SUCCESS: for correct transmission
*******************************************************************************/
u32 ETH_HandleTxPkt(u32 addr, u16 FrameLength)
{
// Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset)
if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (u32)RESET)
{
// Return ERROR: OWN bit set
return ETH_ERROR;
}
//Set the DMA buffer address to send to the Packet we received from stack
DMATxDescToSet->Buffer1Addr = (u32)addr;
// Setting the Frame Length: bits[12:0]
DMATxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1);
// Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor)
DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
// Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA
DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
// When Tx Buffer unavailable flag is set: clear it and resume transmission
if ((ETH_DMA->DMASR & ETH_DMASR_TBUS) != (u32)RESET)
{
// Clear TBUS ETHERNET DMA flag
ETH_DMA->DMASR = ETH_DMASR_TBUS;
// Resume DMA transmission
ETH_DMA->DMATPDR = 0;
}
// Update the ETHERNET DMA global Tx descriptor with next Tx decriptor
// Chained Mode
if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (u32)RESET)
{
// Selects the next DMA Tx descriptor list for next buffer to send
DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr);
}
else // Ring Mode
{
if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (u32)RESET)
{
// Selects the first DMA Tx descriptor for next buffer to send: last Tx descriptor was used
DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH_DMA->DMATDLAR);
}
else
{
// Selects the next DMA Tx descriptor list for next buffer to send
DMATxDescToSet = (ETH_DMADESCTypeDef*) ((u32)DMATxDescToSet + 0x10 + ((ETH_DMA->DMABMR & ETH_DMABMR_DSL) >> 2));
}
}
// Return SUCCESS
return ETH_SUCCESS;
}
/*******************************************************************************
* Function Name : ETH_HandleRxPkt
* Desciption : Receives a packet and copies it to memory pointed by ppkt.
* Input : None
* Output : ppkt: pointer on application receive buffer.
* Return : ETH_ERROR: if there is error in reception
* Received packet size: if packet reception is correct
*******************************************************************************/
u32 ETH_HandleRxPkt(u32 addr)
{
// Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset)
if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (u32)RESET)
{
// Return error: OWN bit set
return ETH_ERROR;
}
//Set the buffer address to rcv frame for the same descriptor (reserved packet)
DMARxDescToGet->Buffer1Addr = addr;
if(addr) {
// Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA
DMARxDescToGet->Status = ETH_DMARxDesc_OWN;
}
// Update the ETHERNET DMA global Rx descriptor with next Rx decriptor
// Chained Mode
if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (u32)RESET)
{
// Selects the next DMA Rx descriptor list for next buffer to read
DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
}
else // Ring Mode
{
if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (u32)RESET)
{
// Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used
DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH_DMA->DMARDLAR);
}
else
{
// Selects the next DMA Rx descriptor list for next buffer to read
DMARxDescToGet = (ETH_DMADESCTypeDef*) ((u32)DMARxDescToGet + 0x10 + ((ETH_DMA->DMABMR & ETH_DMABMR_DSL) >> 2));
}
}
return(1);
}
/*******************************************************************************
* Function Name : ETH_GetRxPktSize
* Desciption : Get the size of received the received packet.
* Input : None
* Output : None
* Return : Rx packet size
*******************************************************************************/
u32 ETH_GetRxPktSize(void)
{
u32 FrameLength = 0;
//Test DMARxDescToGet is not NULL
if(DMARxDescToGet)
{
/* Get the size of the packet: including 4 bytes of the CRC */
FrameLength = ETH_GetDMARxDescFrameLength(DMARxDescToGet);
}
/* Return Frame Length */
return FrameLength;
}
/*******************************************************************************
* Function Name : ETH_DropRxPkt
* Desciption : Drop a Received packet (too small packet, etc...)
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void ETH_DropRxPkt(void)
{
// Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA
DMARxDescToGet->Status = ETH_DMARxDesc_OWN;
// Chained Mode
if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (u32)RESET)
{
// Selects the next DMA Rx descriptor list for next buffer read
DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
}
else // Ring Mode
{
if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (u32)RESET)
{
// Selects the next DMA Rx descriptor list for next buffer read: this will
// be the first Rx descriptor in this case
DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH_DMA->DMARDLAR);
}
else
{
// Selects the next DMA Rx descriptor list for next buffer read
DMARxDescToGet = (ETH_DMADESCTypeDef*) ((u32)DMARxDescToGet + 0x10 + ((ETH_DMA->DMABMR & ETH_DMABMR_DSL) >> 2));
}
}
}
#endif /* _ETH_DMA */
/*--------------------------------- PHY ------------------------------------*/
/*******************************************************************************
* Function Name : ETH_ReadPHYRegister
* Desciption : Read a PHY register
* Input : - PHYAddress: PHY device address, is the index of one of supported
* 32 PHY devices.
* This parameter can be one of the following values: 0,..,31
* - PHYReg: PHY register address, is the index of one of the 32
* PHY register.
* This parameter can be one of the following values:
* - PHY_BCR : Tranceiver Basic Control Register
* - PHY_BSR : Tranceiver Basic Status Register
* - PHY_SR : Tranceiver Status Register
* - More PHY register could be read depending on the used PHY
* Output : None
* Return : ETH_ERROR: in case of timeout
* Data read from the selected PHY register: for correct read
*******************************************************************************/
u16 ETH_ReadPHYRegister(u16 PHYAddress, u16 PHYReg)
{
u32 tmpreg = 0;
u32 timeout = 0;
/* Check the parameters */
eth_assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
eth_assert_param(IS_ETH_PHY_REG(PHYReg));
/* Get the ETHERNET MACMIIAR value */
tmpreg = ETH_MAC->MACMIIAR;
/* Keep only the CSR Clock Range CR[2:0] bits value */
tmpreg &= ~MACMIIAR_CR_Mask;
/* Prepare the MII address register value */
tmpreg |=(((u32)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
tmpreg |=(((u32)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
/* Write the result value into the MII Address register */
ETH_MAC->MACMIIAR = tmpreg;
/* Check for the Busy flag */
do
{
timeout++;
tmpreg = ETH_MAC->MACMIIAR;
} while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (u32)PHY_READ_TO));
/* Return ERROR in case of timeout */
if(timeout == PHY_READ_TO)
{
return (u16)ETH_ERROR;
}
/* Return data register value */
return (u16)(ETH_MAC->MACMIIDR);
}
/*******************************************************************************
* Function Name : ETH_WritePHYRegister
* Desciption : Write to a PHY register
* Input : - PHYAddress: PHY device address, is the index of one of supported
* 32 PHY devices.
* This parameter can be one of the following values: 0,..,31
* - PHYReg: PHY register address, is the index of one of the 32
* PHY register.
* This parameter can be one of the following values:
* - PHY_BCR : Tranceiver Control Register
* - More PHY register could be written depending on the used PHY
* - PHYValue: the value to write
* Output : None
* Return : ETH_ERROR: in case of timeout
* ETH_SUCCESS: for correct read
*******************************************************************************/
u32 ETH_WritePHYRegister(u16 PHYAddress, u16 PHYReg, u16 PHYValue)
{
u32 tmpreg = 0;
u32 timeout = 0;
/* Check the parameters */
eth_assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
eth_assert_param(IS_ETH_PHY_REG(PHYReg));
/* Get the ETHERNET MACMIIAR value */
tmpreg = ETH_MAC->MACMIIAR;
/* Keep only the CSR Clock Range CR[2:0] bits value */
tmpreg &= ~MACMIIAR_CR_Mask;
/* Prepare the MII register address value */
tmpreg |=(((u32)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
tmpreg |=(((u32)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
/* Give the value to the MII data register */
ETH_MAC->MACMIIDR = PHYValue;
/* Write the result value into the MII Address register */
ETH_MAC->MACMIIAR = tmpreg;
/* Check for the Busy flag */
do
{
timeout++;
tmpreg = ETH_MAC->MACMIIAR;
} while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (u32)PHY_WRITE_TO));
/* Return ERROR in case of timeout */
if(timeout == PHY_WRITE_TO)
{
return ETH_ERROR;
}
/* Return SUCCESS */
return ETH_SUCCESS;
}
/*******************************************************************************
* Function Name : ETH_PHYLoopBackCmd
* Desciption : Enables or disables the PHY loopBack mode.
* Input : - PHYAddress: PHY device address, is the index of one of supported
* 32 PHY devices.
* This parameter can be one of the following values:
* - NewState: new state of the PHY loopBack mode.
* This parameter can be: ENABLE or DISABLE.
* Note: Don't be confused with ETH_MACLoopBackCmd function
* which enables internal loopback at MII level
* Output : None
* Return : None
*******************************************************************************/
u32 ETH_PHYLoopBackCmd(u16 PHYAddress, FunctionalState NewState)
{
u16 tmpreg = 0;
/* Check the parameters */
eth_assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
/* Get the PHY configuration to update it */
tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR);
if (NewState != DISABLE)
{
/* Enable the PHY loopback mode */
tmpreg |= PHY_Loopback;
}
else
{
/* Disable the PHY loopback mode: normal mode */
tmpreg &= (u16)(~(u16)PHY_Loopback);
}
/* Update the PHY control register with the new configuration */
if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (u32)RESET)
{
return ETH_SUCCESS;
}
else
{
/* Return SUCCESS */
return ETH_ERROR;
}
}
/*--------------------------------- MAC ------------------------------------*/
/*******************************************************************************
* Function Name : ETH_MACTransmissionCmd
* Desciption : Enables or disables the MAC transmission.
* Input : - NewState: new state of the MAC transmission.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void ETH_MACTransmissionCmd(FunctionalState NewState)
{
/* Check the parameters */
eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the MAC transmission */
ETH_MAC->MACCR |= ETH_MACCR_TE;
}
else
{
/* Disable the MAC transmission */
ETH_MAC->MACCR &= ~ETH_MACCR_TE;
}
}
/*******************************************************************************
* Function Name : ETH_MACReceptionCmd
* Desciption : Enables or disables the MAC reception.
* Input : - NewState: new state of the MAC reception.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void ETH_MACReceptionCmd(FunctionalState NewState)
{
/* Check the parameters */
eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the MAC reception */
ETH_MAC->MACCR |= ETH_MACCR_RE;
}
else
{
/* Disable the MAC reception */
ETH_MAC->MACCR &= ~ETH_MACCR_RE;
}
}
/*******************************************************************************
* Function Name : ETH_GetFlowControlBusyStatus
* Desciption : Checks whether the ETHERNET flow control busy bit is set or not.
* Input : None
* Output : None
* Return : The new state of flow control busy status bit (SET or RESET).
*******************************************************************************/
FlagStatus ETH_GetFlowControlBusyStatus(void)
{
FlagStatus bitstatus = RESET;
/* The Flow Control register should not be written to until this bit is cleared */
if ((ETH_MAC->MACFCR & ETH_MACFCR_FCBBPA) != (u32)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : ETH_InitiatePauseControlFrame
* Desciption : Initiate a Pause Control Frame (Full-duplex only).
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void ETH_InitiatePauseControlFrame(void)
{
/* When Set In full duplex MAC initiates pause control frame */
ETH_MAC->MACFCR |= ETH_MACFCR_FCBBPA;
}
/*******************************************************************************
* Function Name : ETH_BackPressureActivationCmd
* Desciption : Enables or disables the MAC BackPressure operation activation (Half-duplex only).
* Input : - NewState: new state of the MAC BackPressure operation activation.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void ETH_BackPressureActivationCmd(FunctionalState NewState)
{
/* Check the parameters */
eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Activate the MAC BackPressure operation */
/* In Half duplex: during backpressure, when the MAC receives a new frame,
the transmitter starts sending a JAM pattern resulting in a collision */
ETH_MAC->MACFCR |= ETH_MACFCR_FCBBPA;
}
else
{
/* Desactivate the MAC BackPressure operation */
ETH_MAC->MACFCR &= ~ETH_MACFCR_FCBBPA;
}
}
/*******************************************************************************
* Function Name : ETH_GetMACFlagStatus
* Desciption : Checks whether the specified ETHERNET MAC flag is set or not.
* Input : - ETH_MAC_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* - ETH_MAC_FLAG_TST : Time stamp trigger flag
* - ETH_MAC_FLAG_MMCT : MMC transmit flag
* - ETH_MAC_FLAG_MMCR : MMC receive flag
* - ETH_MAC_FLAG_MMC : MMC flag
* - ETH_MAC_FLAG_PMT : PMT flag
* Output : None
* Return : The new state of ETHERNET MAC flag (SET or RESET).
*******************************************************************************/
FlagStatus ETH_GetMACFlagStatus(u32 ETH_MAC_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
eth_assert_param(IS_ETH_MAC_GET_FLAG(ETH_MAC_FLAG));
if ((ETH_MAC->MACSR & ETH_MAC_FLAG) != (u32)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : ETH_GetMACITStatus
* Desciption : Checks whether the specified ETHERNET MAC interrupt has occurred or not.
* Input : - ETH_MAC_IT: specifies the interrupt source to check.
* This parameter can be one of the following values:
* - ETH_MAC_IT_TST : Time stamp trigger interrupt
* - ETH_MAC_IT_MMCT : MMC transmit interrupt
* - ETH_MAC_IT_MMCR : MMC receive interrupt
* - ETH_MAC_IT_MMC : MMC interrupt
* - ETH_MAC_IT_PMT : PMT interrupt
* Output : None
* Return : The new state of ETHERNET MAC interrupt (SET or RESET).
*******************************************************************************/
ITStatus ETH_GetMACITStatus(u32 ETH_MAC_IT)
{
ITStatus bitstatus = RESET;
/* Check the parameters */
eth_assert_param(IS_ETH_MAC_GET_IT(ETH_MAC_IT));
if ((ETH_MAC->MACSR & ETH_MAC_IT) != (u32)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : ETH_MACITConfig
* Desciption : Enables or disables the specified ETHERNET MAC interrupts.
* Input : - ETH_MAC_IT: specifies the ETHERNET MAC interrupt sources to be
* enabled or disabled.
* This parameter can be any combination of the following values:
* - ETH_MAC_IT_TST : Time stamp trigger interrupt
* - ETH_MAC_IT_PMT : PMT interrupt
* - NewState: new state of the specified ETHERNET MAC interrupts.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void ETH_MACITConfig(u32 ETH_MAC_IT, FunctionalState NewState)
{
/* Check the parameters */
eth_assert_param(IS_ETH_MAC_IT(ETH_MAC_IT));
eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected ETHERNET MAC interrupts */
ETH_MAC->MACIMR &= (~(u32)ETH_MAC_IT);
}
else
{
/* Disable the selected ETHERNET MAC interrupts */
ETH_MAC->MACIMR |= ETH_MAC_IT;
}
}
/*******************************************************************************
* Function Name : ETH_MACAddressConfig
* Desciption : Configures the selected MAC address.
* Input : - MacAddr: The MAC addres to configure.
* This parameter can be one of the following values:
* - ETH_MAC_Address0 : MAC Address0
* - ETH_MAC_Address1 : MAC Address1
* - ETH_MAC_Address2 : MAC Address2
* - ETH_MAC_Address3 : MAC Address3
* - Addr: Pointer on MAC address buffer data (6 bytes).
* Output : None
* Return : None
*******************************************************************************/
void ETH_MACAddressConfig(u32 MacAddr, u8 *Addr)
{
u32 tmpreg;
/* Check the parameters */
eth_assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
/* Calculate the selectecd MAC address high register */
tmpreg = ((u32)Addr[5] << 8) | (u32)Addr[4];
/* Load the selectecd MAC address high register */
(*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) = tmpreg;
/* Calculate the selectecd MAC address low register */
tmpreg = ((u32)Addr[3] << 24) | ((u32)Addr[2] << 16) | ((u32)Addr[1] << 8) | Addr[0];
/* Load the selectecd MAC address low register */
(*(vu32 *) (ETH_MAC_AddrLowBase + MacAddr)) = tmpreg;
}
/*******************************************************************************
* Function Name : ETH_GetMACAddress
* Desciption : Get the selected MAC address.
* Input : - MacAddr: The MAC addres to return.
* This parameter can be one of the following values:
* - ETH_MAC_Address0 : MAC Address0
* - ETH_MAC_Address1 : MAC Address1
* - ETH_MAC_Address2 : MAC Address2
* - ETH_MAC_Address3 : MAC Address3
* - Addr: Pointer on MAC address buffer data (6 bytes).
* Output : None
* Return : None
*******************************************************************************/
void ETH_GetMACAddress(u32 MacAddr, u8 *Addr)
{
u32 tmpreg;
/* Check the parameters */
eth_assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
/* Get the selectecd MAC address high register */
tmpreg =(*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr));
/* Calculate the selectecd MAC address buffer */
Addr[5] = ((tmpreg >> 8) & (u8)0xFF);
Addr[4] = (tmpreg & (u8)0xFF);
/* Load the selectecd MAC address low register */
tmpreg =(*(vu32 *) (ETH_MAC_AddrLowBase + MacAddr));
/* Calculate the selectecd MAC address buffer */
Addr[3] = ((tmpreg >> 24) & (u8)0xFF);
Addr[2] = ((tmpreg >> 16) & (u8)0xFF);
Addr[1] = ((tmpreg >> 8 ) & (u8)0xFF);
Addr[0] = (tmpreg & (u8)0xFF);
}
/*******************************************************************************
* Function Name : ETH_MACAddressPerfectFilterCmd
* Desciption : Enables or disables the Address filter module uses the specified
* ETHERNET MAC address for perfect filtering
* Input : - MacAddr: specifies the ETHERNET MAC address to be used for prfect filtering.
* This parameter can be one of the following values:
* - ETH_MAC_Address1 : MAC Address1
* - ETH_MAC_Address2 : MAC Address2
* - ETH_MAC_Address3 : MAC Address3
* - NewState: new state of the specified ETHERNET MAC address use.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void ETH_MACAddressPerfectFilterCmd(u32 MacAddr, FunctionalState NewState)
{
/* Check the parameters */
eth_assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected ETHERNET MAC address for perfect filtering */
(*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) |= ETH_MACA1HR_AE;
}
else
{
/* Disable the selected ETHERNET MAC address for perfect filtering */
(*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(u32)ETH_MACA1HR_AE);
}
}
/*******************************************************************************
* Function Name : ETH_MACAddressFilterConfig
* Desciption : Set the filter type for the specified ETHERNET MAC address
* Input : - MacAddr: specifies the ETHERNET MAC address
* This parameter can be one of the following values:
* - ETH_MAC_Address1 : MAC Address1
* - ETH_MAC_Address2 : MAC Address2
* - ETH_MAC_Address3 : MAC Address3
* - Filter: specifies the used frame received field for comparaison
* This parameter can be one of the following values:
* - ETH_MAC_AddressFilter_SA : MAC Address is used to compare
* with the SA fields of the received frame.
* - ETH_MAC_AddressFilter_DA : MAC Address is used to compare
* with the DA fields of the received frame.
* Output : None
* Return : None
*******************************************************************************/
void ETH_MACAddressFilterConfig(u32 MacAddr, u32 Filter)
{
/* Check the parameters */
eth_assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
eth_assert_param(IS_ETH_MAC_ADDRESS_FILTER(Filter));
if (Filter != ETH_MAC_AddressFilter_DA)
{
/* The selected ETHERNET MAC address is used to compare with the SA fields of the
received frame. */
(*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) |= ETH_MACA1HR_SA;
}
else
{
/* The selected ETHERNET MAC address is used to compare with the DA fields of the
received frame. */
(*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(u32)ETH_MACA1HR_SA);
}
}
/*******************************************************************************
* Function Name : ETH_MACAddressMaskBytesFilterConfig
* Desciption : Set the filter type for the specified ETHERNET MAC address
* Input : - MacAddr: specifies the ETHERNET MAC address
* This parameter can be one of the following values:
* - ETH_MAC_Address1 : MAC Address1
* - ETH_MAC_Address2 : MAC Address2
* - ETH_MAC_Address3 : MAC Address3
* - MaskByte: specifies the used address bytes for comparaison
* This parameter can be any combination of the following values:
* - ETH_MAC_AddressMask_Byte6 : Mask MAC Address high reg bits [15:8].
* - ETH_MAC_AddressMask_Byte5 : Mask MAC Address high reg bits [7:0].
* - ETH_MAC_AddressMask_Byte4 : Mask MAC Address low reg bits [31:24].
* - ETH_MAC_AddressMask_Byte3 : Mask MAC Address low reg bits [23:16].
* - ETH_MAC_AddressMask_Byte2 : Mask MAC Address low reg bits [15:8].
* - ETH_MAC_AddressMask_Byte1 : Mask MAC Address low reg bits [7:0].
* Output : None
* Return : None
*******************************************************************************/
void ETH_MACAddressMaskBytesFilterConfig(u32 MacAddr, u32 MaskByte)
{
/* Check the parameters */
eth_assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
eth_assert_param(IS_ETH_MAC_ADDRESS_MASK(MaskByte));
/* Clear MBC bits in the selected MAC address high register */
(*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(u32)ETH_MACA1HR_MBC);
/* Set the selected Filetr mask bytes */
(*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) |= MaskByte;
}
/*------------------------ DMA Tx/Rx Desciptors ----------------------------*/
#ifdef _ETH_DMA
/*******************************************************************************
* Function Name : ETH_DMATxDescChainInit
* Desciption : Initializes the DMA Tx descriptors in chain mode.
* Input : - DMATxDescTab: Pointer on the first Tx desc list
* - TxBuff: Pointer on the first TxBuffer list
* - TxBuffCount: Number of the used Tx desc in the list
* Output : None
* Return : None
*******************************************************************************/
void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, u8* TxBuff, u32 TxBuffCount)
{
u32 i = 0;
ETH_DMADESCTypeDef *DMATxDesc;
/* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
DMATxDescToSet = DMATxDescTab;
/* Fill each DMATxDesc descriptor with the right values */
for(i=0; i < TxBuffCount; i++)
{
/* Get the pointer on the ith member of the Tx Desc list */
DMATxDesc = DMATxDescTab + i;
/* Set Second Address Chained bit */
DMATxDesc->Status = ETH_DMATxDesc_TCH;
/* Set Buffer1 address pointer */
DMATxDesc->Buffer1Addr = (u32)*((u32*)TxBuff + i);
/* Initialize the next descriptor with the Next Desciptor Polling Enable */
if(i < (TxBuffCount-1))
{
/* Set next descriptor address register with next descriptor base address */
DMATxDesc->Buffer2NextDescAddr = (u32)(DMATxDescTab+i+1);
}
else
{
/* For last descriptor, set next descriptor address register equal to the first descriptor base address */
DMATxDesc->Buffer2NextDescAddr = (u32) DMATxDescTab;
}
}
/* Set Transmit Desciptor List Address Register */
ETH_DMA->DMATDLAR = (u32) DMATxDescTab;
}
/*******************************************************************************
* Function Name : ETH_DMATxDescRingInit
* Desciption : Initializes the DMA Tx descriptors in ring mode.
* Input : - DMATxDescTab: Pointer on the first Tx desc list
* - TxBuff1: Pointer on the first TxBuffer1 list
* - TxBuff2: Pointer on the first TxBuffer2 list
* - TxBuffCount: Number of the used Tx desc in the list
* Note: see decriptor skip length defined in ETH_DMA_InitStruct
for the number of Words to skip between two unchained descriptors.
* Output : None
* Return : None
*******************************************************************************/
void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff1, u8 *TxBuff2, u32 TxBuffCount)
{
u32 i = 0;
ETH_DMADESCTypeDef *DMATxDesc;
/* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
DMATxDescToSet = DMATxDescTab;
/* Fill each DMATxDesc descriptor with the right values */
for(i=0; i < TxBuffCount; i++)
{
/* Get the pointer on the ith member of the Tx Desc list */
DMATxDesc = DMATxDescTab + i;
/* Set Buffer1 address pointer */
DMATxDesc->Buffer1Addr = (u32)(&TxBuff1[i*ETH_MAX_PACKET_SIZE]);
/* Set Buffer2 address pointer */
DMATxDesc->Buffer2NextDescAddr = (u32)(&TxBuff2[i*ETH_MAX_PACKET_SIZE]);
/* Set Transmit End of Ring bit for last descriptor: The DMA returns to the base
address of the list, creating a Desciptor Ring */
if(i == (TxBuffCount-1))
{
/* Set Transmit End of Ring bit */
DMATxDesc->Status = ETH_DMATxDesc_TER;
}
}
/* Set Transmit Desciptor List Address Register */
ETH_DMA->DMATDLAR = (u32) DMATxDescTab;
}
/*******************************************************************************
* Function Name : ETH_GetDMATxDescFlagStatus
* Desciption : Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
* Input : - DMATxDesc: pointer on a DMA Tx descriptor
* - ETH_DMATxDescFlag: specifies the flag to check.
* This parameter can be one of the following values:
* - ETH_DMATxDesc_OWN : OWN bit: descriptor is owned by DMA engine
* - ETH_DMATxDesc_IC : Interrupt on completetion
* - ETH_DMATxDesc_LS : Last Segment
* - ETH_DMATxDesc_FS : First Segment
* - ETH_DMATxDesc_DC : Disable CRC
* - ETH_DMATxDesc_DP : Disable Pad
* - ETH_DMATxDesc_TTSE: Transmit Time Stamp Enable
* - ETH_DMATxDesc_TER : Transmit End of Ring
* - ETH_DMATxDesc_TCH : Second Address Chained
* - ETH_DMATxDesc_TTSS: Tx Time Stamp Status
* - ETH_DMATxDesc_IHE : IP Header Error
* - ETH_DMATxDesc_ES : Error summary
* - ETH_DMATxDesc_JT : Jabber Timeout
* - ETH_DMATxDesc_FF : Frame Flushed: DMA/MTL flushed the frame due to SW flush
* - ETH_DMATxDesc_PCE : Payload Checksum Error
* - ETH_DMATxDesc_LCA : Loss of Carrier: carrier lost during tramsmission
* - ETH_DMATxDesc_NC : No Carrier: no carrier signal from the tranceiver
* - ETH_DMATxDesc_LCO : Late Collision: transmission aborted due to collision
* - ETH_DMATxDesc_EC : Excessive Collision: transmission aborted after 16 collisions
* - ETH_DMATxDesc_VF : VLAN Frame
* - ETH_DMATxDesc_CC : Collision Count
* - ETH_DMATxDesc_ED : Excessive Deferral
* - ETH_DMATxDesc_UF : Underflow Error: late data arrival from the memory
* - ETH_DMATxDesc_DB : Deferred Bit
* Output : None
* Return : The new state of ETH_DMATxDescFlag (SET or RESET).
*******************************************************************************/
FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, u32 ETH_DMATxDescFlag)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
eth_assert_param(IS_ETH_DMATxDESC_GET_FLAG(ETH_DMATxDescFlag));
if ((DMATxDesc->Status & ETH_DMATxDescFlag) != (u32)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : ETH_GetDMATxDescCollisionCount
* Desciption : Returns the specified ETHERNET DMA Tx Desc collision count.
* Input : - DMATxDesc: pointer on a DMA Tx descriptor
* Output : None
* Return : The Transmit descriptor collision counter value.
*******************************************************************************/
u32 ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc)
{
/* Return the Receive descriptor frame length */
return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATxDesc_CollisionCountShift);
}
/*******************************************************************************
* Function Name : ETH_SetDMATxDescOwnBit
* Desciption : Set the specified DMA Tx Desc Own bit.
* Input : - DMATxDesc: Pointer on a Tx desc
* Output : None
* Return : None
*******************************************************************************/
void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc)
{
/* Set the DMA Tx Desc Own bit */
DMATxDesc->Status |= ETH_DMATxDesc_OWN;
}
/*******************************************************************************
* Function Name : ETH_DMATxDescTransmitITConfig
* Desciption : Enables or disables the specified DMA Tx Desc Transmit interrupt.
* Input : - DMATxDesc: Pointer on a Tx desc
* - NewState: new state of the DMA Tx Desc transmit interrupt.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
{
/* Check the parameters */
eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the DMA Tx Desc Transmit interrupt */
DMATxDesc->Status |= ETH_DMATxDesc_IC;
}
else
{
/* Disable the DMA Tx Desc Transmit interrupt */
DMATxDesc->Status &=(~(u32)ETH_DMATxDesc_IC);
}
}
/*******************************************************************************
* Function Name : ETH_DMATxDescFrameSegmentConfig
* Desciption : Enables or disables the specified DMA Tx Desc Transmit interrupt.
* Input : - DMATxDesc: Pointer on a Tx desc
* - FrameSegment: specifies is the actual Tx desc contain last or first segment.
* This parameter can be one of the following values:
* - ETH_DMATxDesc_LastSegment : actual Tx desc contain last segment
* - ETH_DMATxDesc_FirstSegment : actual Tx desc contain first segment
* Output : None
* Return : None
*******************************************************************************/
void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 DMATxDesc_FrameSegment)
{
/* Check the parameters */
eth_assert_param(IS_ETH_DMA_TXDESC_SEGMENT(DMATxDesc_FrameSegment));
/* Selects the DMA Tx Desc Frame segment */
DMATxDesc->Status |= DMATxDesc_FrameSegment;
}
/*******************************************************************************
* Function Name : ETH_DMATxDescChecksumInsertionConfig
* Desciption : Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
* Input : - DMATxDesc: pointer on a DMA Tx descriptor
* - Checksum: specifies is the DMA Tx desc checksum insertion.
* This parameter can be one of the following values:
* - ETH_DMATxDesc_ChecksumByPass : Checksum bypass
* - ETH_DMATxDesc_ChecksumIPV4Header : IPv4 header checksum
* - ETH_DMATxDesc_ChecksumTCPUDPICMPSegment : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
* - ETH_DMATxDesc_ChecksumTCPUDPICMPFull : TCP/UDP/ICMP checksum fully in hardware including pseudo header
* Output : None
* Return : The Transmit descriptor collision.
*******************************************************************************/
void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 DMATxDesc_Checksum)
{
/* Check the parameters */
eth_assert_param(IS_ETH_DMA_TXDESC_CHECKSUM(DMATxDesc_Checksum));
/* Set the selected DMA Tx desc checksum insertion control */
DMATxDesc->Status |= DMATxDesc_Checksum;
}
/*******************************************************************************
* Function Name : ETH_DMATxDescCRCCmd
* Desciption : Enables or disables the DMA Tx Desc CRC.
* Input : - DMATxDesc: pointer on a DMA Tx descriptor
* - NewState: new state of the specified DMA Tx Desc CRC.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
{
/* Check the parameters */
eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DMA Tx Desc CRC */
DMATxDesc->Status &= (~(u32)ETH_DMATxDesc_DC);
}
else
{
/* Disable the selected DMA Tx Desc CRC */
DMATxDesc->Status |= ETH_DMATxDesc_DC;
}
}
/*******************************************************************************
* Function Name : ETH_DMATxDescEndOfRingCmd
* Desciption : Enables or disables the DMA Tx Desc end of ring.
* Input : - DMATxDesc: pointer on a DMA Tx descriptor
* - NewState: new state of the specified DMA Tx Desc end of ring.
* This parameter can be: ENABLE or DISABLE.
* Output : NoneH
* Return : None
*******************************************************************************/
void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
{
/* Check the parameters */
eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DMA Tx Desc end of ring */
DMATxDesc->Status |= ETH_DMATxDesc_TER;
}
else
{
/* Disable the selected DMA Tx Desc end of ring */
DMATxDesc->Status &= (~(u32)ETH_DMATxDesc_TER);
}
}
/*******************************************************************************
* Function Name : ETH_DMATxDescSecondAddressChainedCmd
* Desciption : Enables or disables the DMA Tx Desc second address chained.
* Input : - DMATxDesc: pointer on a DMA Tx descriptor
* - NewState: new state of the specified DMA Tx Desc second address chained.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
{
/* Check the parameters */
eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DMA Tx Desc second address chained */
DMATxDesc->Status |= ETH_DMATxDesc_TCH;
}
else
{
/* Disable the selected DMA Tx Desc second address chained */
DMATxDesc->Status &=(~(u32)ETH_DMATxDesc_TCH);
}
}
/*******************************************************************************
* Function Name : ETH_DMATxDescShortFramePaddingCmd
* Desciption : Enables or disables the DMA Tx Desc padding for frame shorter than 64 bytes.
* Input : - DMATxDesc: pointer on a DMA Tx descriptor
* - NewState: new state of the specified DMA Tx Desc padding for
* frame shorter than 64 bytes.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
{
/* Check the parameters */
eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DMA Tx Desc padding for frame shorter than 64 bytes */
DMATxDesc->Status &= (~(u32)ETH_DMATxDesc_DP);
}
else
{
/* Disable the selected DMA Tx Desc padding for frame shorter than 64 bytes*/
DMATxDesc->Status |= ETH_DMATxDesc_DP;
}
}
/*******************************************************************************
* Function Name : ETH_DMATxDescTimeStampCmd
* Desciption : Enables or disables the DMA Tx Desc time stamp.
* Input : - DMATxDesc: pointer on a DMA Tx descriptor
* - NewState: new state of the specified DMA Tx Desc time stamp.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
{
/* Check the parameters */
eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DMA Tx Desc time stamp */
DMATxDesc->Status |= ETH_DMATxDesc_TTSE;
}
else
{
/* Disable the selected DMA Tx Desc time stamp */
DMATxDesc->Status &=(~(u32)ETH_DMATxDesc_TTSE);
}
}
/*******************************************************************************
* Function Name : ETH_DMATxDescBufferSizeConfig
* Desciption : Configures the specified DMA Tx Desc buffer1 and buffer2 sizes.
* Input : - DMATxDesc: Pointer on a Tx desc
* - BufferSize1: specifies the Tx desc buffer1 size.
* - BufferSize2: specifies the Tx desc buffer2 size (put "0" if not used).
* Output : None
* Return : None
*******************************************************************************/
void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 BufferSize1, u32 BufferSize2)
{
/* Check the parameters */
eth_assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize1));
eth_assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize2));
/* Set the DMA Tx Desc buffer1 and buffer2 sizes values */
DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATxDesc_BufferSize2Shift));
}
/*******************************************************************************
* Function Name : ETH_DMARxDescChainInit
* Desciption : Initializes the DMA Rx descriptors in chain mode.
* Input : - DMARxDescTab: Pointer on the first Rx desc list
* - RxBuff: Pointer on the first RxBuffer list
* - RxBuffCount: Number of the used Rx desc in the list
* Output : None
* Return : None
*******************************************************************************/
void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff, u32 RxBuffCount)
{
u32 i = 0;
ETH_DMADESCTypeDef *DMARxDesc;
/* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
DMARxDescToGet = DMARxDescTab;
/* Fill each DMARxDesc descriptor with the right values */
for(i=0; i < RxBuffCount; i++)
{
/* Get the pointer on the ith member of the Rx Desc list */
DMARxDesc = DMARxDescTab+i;
/* Set Own bit of the Rx descriptor Status */
DMARxDesc->Status = ETH_DMARxDesc_OWN;
// DMARxDesc->Status = 0;
/* Set Buffer1 size and Second Address Chained bit */
DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (u32)ETH_MAX_PACKET_SIZE;
/* Set Buffer1 address pointer */
DMARxDesc->Buffer1Addr = (u32)*((u32*)RxBuff + i);
/* Initialize the next descriptor with the Next Desciptor Polling Enable */
if(i < (RxBuffCount-1))
{
/* Set next descriptor address register with next descriptor base address */
DMARxDesc->Buffer2NextDescAddr = (u32)(DMARxDescTab+i+1);
}
else
{
/* For last descriptor, set next descriptor address register equal to the first descriptor base address */
DMARxDesc->Buffer2NextDescAddr = (u32)(DMARxDescTab);
}
}
/* Set Receive Desciptor List Address Register */
ETH_DMA->DMARDLAR = (u32) DMARxDescTab;
}
/*******************************************************************************
* Function Name : ETH_DMARxDescRingInit
* Desciption : Initializes the DMA Rx descriptors in ring mode.
* Input : - DMARxDescTab: Pointer on the first Rx desc list
* - RxBuff1: Pointer on the first RxBuffer1 list
* - RxBuff2: Pointer on the first RxBuffer2 list
* - RxBuffCount: Number of the used Rx desc in the list
* Note: see decriptor skip length defined in ETH_DMA_InitStruct
for the number of Words to skip between two unchained descriptors.
* Output : None
* Return : None
*******************************************************************************/
void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff1, u8 *RxBuff2, u32 RxBuffCount)
{
u32 i = 0;
ETH_DMADESCTypeDef *DMARxDesc;
/* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
DMARxDescToGet = DMARxDescTab;
/* Fill each DMARxDesc descriptor with the right values */
for(i=0; i < RxBuffCount; i++)
{
/* Get the pointer on the ith member of the Rx Desc list */
DMARxDesc = DMARxDescTab+i;
/* Set Own bit of the Rx descriptor Status */
DMARxDesc->Status = ETH_DMARxDesc_OWN;
/* Set Buffer1 size */
DMARxDesc->ControlBufferSize = ETH_MAX_PACKET_SIZE;
/* Set Buffer1 address pointer */
DMARxDesc->Buffer1Addr = (u32)(&RxBuff1[i*ETH_MAX_PACKET_SIZE]);
/* Set Buffer2 address pointer */
DMARxDesc->Buffer2NextDescAddr = (u32)(&RxBuff2[i*ETH_MAX_PACKET_SIZE]);
/* Set Receive End of Ring bit for last descriptor: The DMA returns to the base
address of the list, creating a Desciptor Ring */
if(i == (RxBuffCount-1))
{
/* Set Receive End of Ring bit */
DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER;
}
}
/* Set Receive Desciptor List Address Register */
ETH_DMA->DMARDLAR = (u32) DMARxDescTab;
}
/*******************************************************************************
* Function Name : ETH_GetDMARxDescFlagStatus
* Desciption : Checks whether the specified ETHERNET Rx Desc flag is set or not.
* Input : - DMARxDesc: pointer on a DMA Rx descriptor
* - ETH_DMARxDescFlag: specifies the flag to check.
* This parameter can be one of the following values:
* - ETH_DMARxDesc_OWN: OWN bit: descriptor is owned by DMA engine
* - ETH_DMARxDesc_AFM: DA Filter Fail for the rx frame
* - ETH_DMARxDesc_ES: Error summary
* - ETH_DMARxDesc_DE: Desciptor error: no more descriptors for receive frame
* - ETH_DMARxDesc_SAF: SA Filter Fail for the received frame
* - ETH_DMARxDesc_LE: Frame size not matching with length field
* - ETH_DMARxDesc_OE: Overflow Error: Frame was damaged due to buffer overflow
* - ETH_DMARxDesc_VLAN: VLAN Tag: received frame is a VLAN frame
* - ETH_DMARxDesc_FS: First descriptor of the frame
* - ETH_DMARxDesc_LS: Last descriptor of the frame
* - ETH_DMARxDesc_IPV4HCE: IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error
* - ETH_DMARxDesc_RxLongFrame: (Giant Frame)Rx - frame is longer than 1518/1522
* - ETH_DMARxDesc_LC: Late collision occurred during reception
* - ETH_DMARxDesc_FT: Frame type - Ethernet, otherwise 802.3
* - ETH_DMARxDesc_RWT: Receive Watchdog Timeout: watchdog timer expired during reception
* - ETH_DMARxDesc_RE: Receive error: error reported by MII interface
* - ETH_DMARxDesc_DE: Dribble bit error: frame contains non int multiple of 8 bits
* - ETH_DMARxDesc_CE: CRC error
* - ETH_DMARxDesc_MAMPCE: Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error
* Output : None
* Return : The new state of ETH_DMARxDescFlag (SET or RESET).
*******************************************************************************/
FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, u32 ETH_DMARxDescFlag)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
eth_assert_param(IS_ETH_DMARxDESC_GET_FLAG(ETH_DMARxDescFlag));
if ((DMARxDesc->Status & ETH_DMARxDescFlag) != (u32)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : ETH_SetDMARxDescOwnBit
* Desciption : Set the specified DMA Rx Desc Own bit.
* Input : - DMARxDesc: Pointer on a Rx desc
* Output : None
* Return : None
*******************************************************************************/
void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc)
{
/* Set the DMA Rx Desc Own bit */
DMARxDesc->Status |= ETH_DMARxDesc_OWN;
}
/*******************************************************************************
* Function Name : ETH_GetDMARxDescFrameLength
* Desciption : Returns the specified DMA Rx Desc frame length.
* Input : - DMARxDesc: pointer on a DMA Rx descriptor
* Output : None
* Return : The Rx descriptor received frame length.
*******************************************************************************/
u32 ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc)
{
/* Return the Receive descriptor frame length */
return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift);
}
/*******************************************************************************
* Function Name : ETH_DMARxDescReceiveITConfig
* Desciption : Enables or disables the specified DMA Rx Desc receive interrupt.
* Input : - DMARxDesc: Pointer on a Rx desc
* - NewState: new state of the specified DMA Rx Desc interrupt.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
{
/* Check the parameters */
eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the DMA Rx Desc receive interrupt */
DMARxDesc->ControlBufferSize &=(~(u32)ETH_DMARxDesc_DIC);
}
else
{
/* Disable the DMA Rx Desc receive interrupt */
DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_DIC;
}
}
/*******************************************************************************
* Function Name : ETH_DMARxDescEndOfRingCmd
* Desciption : Enables or disables the DMA Rx Desc end of ring.
* Input : - DMARxDesc: pointer on a DMA Rx descriptor
* - NewState: new state of the specified DMA Rx Desc end of ring.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
{
/* Check the parameters */
eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DMA Rx Desc end of ring */
DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER;
}
else
{
/* Disable the selected DMA Rx Desc end of ring */
DMARxDesc->ControlBufferSize &=(~(u32)ETH_DMARxDesc_RER);
}
}
/*******************************************************************************
* Function Name : ETH_DMARxDescSecondAddressChainedCmd
* Desciption : Enables or disables the DMA Rx Desc second address chained.
* Input : - DMARxDesc: pointer on a DMA Rx descriptor
* - NewState: new state of the specified DMA Rx Desc second address chained.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
{
/* Check the parameters */
eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DMA Rx Desc second address chained */
DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RCH;
}
else
{
/* Disable the selected DMA Rx Desc second address chained */
DMARxDesc->ControlBufferSize &=(~(u32)ETH_DMARxDesc_RCH);
}
}
/*******************************************************************************
* Function Name : ETH_GetDMARxDescBufferSize
* Desciption : Returns the specified ETHERNET DMA Rx Desc buffer size.
* Input : - DMARxDesc: pointer on a DMA Rx descriptor
* - DMARxDesc_Buffer: specifies the DMA Rx Desc buffer.
* This parameter can be any one of the following values:
* - ETH_DMARxDesc_Buffer1 : DMA Rx Desc Buffer1
* - ETH_DMARxDesc_Buffer2 : DMA Rx Desc Buffer2
* Output : None
* Return : The Receive descriptor frame length.
*******************************************************************************/
u32 ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, u32 DMARxDesc_Buffer)
{
/* Check the parameters */
eth_assert_param(IS_ETH_DMA_RXDESC_BUFFER(DMARxDesc_Buffer));
if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1)
{
/* Return the DMA Rx Desc buffer2 size */
return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARxDesc_Buffer2SizeShift);
}
else
{
/* Return the DMA Rx Desc buffer1 size */
return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1);
}
}
/*--------------------------------- DMA ------------------------------------*/
/*******************************************************************************
* Function Name : ETH_SoftwareReset
* Desciption : Resets all MAC subsystem internal registers and logic.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void ETH_SoftwareReset(void)
{
/* Set the SWR bit: resets all MAC subsystem internal registers and logic */
/* After reset all the registers holds their respective reset values */
ETH_DMA->DMABMR |= ETH_DMABMR_SR;
}
/*******************************************************************************
* Function Name : ETH_GetSoftwareResetStatus
* Desciption : Checks whether the ETHERNET software reset bit is set or not.
* Input : None
* Output : None
* Return : The new state of DMA Bus Mode register SR bit (SET or RESET).
*******************************************************************************/
FlagStatus ETH_GetSoftwareResetStatus(void)
{
FlagStatus bitstatus = RESET;
if((ETH_DMA->DMABMR & ETH_DMABMR_SR) != (u32)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : ETH_GetDMAFlagStatus
* Desciption : Checks whether the specified ETHERNET DMA flag is set or not.
* Input : - ETH_DMA_IT: specifies the flag to check.
* This parameter can be one of the following values:
* - ETH_DMA_FLAG_TST : Time-stamp trigger flag
* - ETH_DMA_FLAG_PMT : PMT flag
* - ETH_DMA_FLAG_MMC : MMC flag
* - ETH_DMA_FLAG_DataTransferError : Error bits 0-data buffer, 1-desc. access
* - ETH_DMA_FLAG_ReadWriteError : Error bits 0-write trnsf, 1-read transfr
* - ETH_DMA_FLAG_AccessError : Error bits 0-Rx DMA, 1-Tx DMA
* - ETH_DMA_FLAG_NIS : Normal interrupt summary flag
* - ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag
* - ETH_DMA_FLAG_ER : Early receive flag
* - ETH_DMA_FLAG_FBE : Fatal bus error flag
* - ETH_DMA_FLAG_ET : Early transmit flag
* - ETH_DMA_FLAG_RWT : Receive watchdog timeout flag
* - ETH_DMA_FLAG_RPS : Receive process stopped flag
* - ETH_DMA_FLAG_RBU : Receive buffer unavailable flag
* - ETH_DMA_FLAG_R : Receive flag
* - ETH_DMA_FLAG_TU : Underflow flag
* - ETH_DMA_FLAG_RO : Overflow flag
* - ETH_DMA_FLAG_TJT : Transmit jabber timeout flag
* - ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag
* - ETH_DMA_FLAG_TPS : Transmit process stopped flag
* - ETH_DMA_FLAG_T : Transmit flag
* Output : None
* Return : The new state of ETH_DMA_FLAG (SET or RESET).
*******************************************************************************/
FlagStatus ETH_GetDMAFlagStatus(u32 ETH_DMA_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
eth_assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_FLAG));
if ((ETH_DMA->DMASR & ETH_DMA_FLAG) != (u32)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : ETH_DMAClearFlag
* Desciption : Clears the ETHERNET?s DMA pending flag.
* Input : - ETH_DMA_FLAG: specifies the flag to clear.
* This parameter can be any combination of the following values:
* - ETH_DMA_FLAG_NIS : Normal interrupt summary flag
* - ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag
* - ETH_DMA_FLAG_ER : Early receive flag
* - ETH_DMA_FLAG_FBE : Fatal bus error flag
* - ETH_DMA_FLAG_ETI : Early transmit flag
* - ETH_DMA_FLAG_RWT : Receive watchdog timeout flag
* - ETH_DMA_FLAG_RPS : Receive process stopped flag
* - ETH_DMA_FLAG_RBU : Receive buffer unavailable flag
* - ETH_DMA_FLAG_R : Receive flag
* - ETH_DMA_FLAG_TU : Transmit Underflow flag
* - ETH_DMA_FLAG_RO : Receive Overflow flag
* - ETH_DMA_FLAG_TJT : Transmit jabber timeout flag
* - ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag
* - ETH_DMA_FLAG_TPS : Transmit process stopped flag
* - ETH_DMA_FLAG_T : Transmit flag
* Output : None
* Return : None
*******************************************************************************/
void ETH_DMAClearFlag(u32 ETH_DMA_FLAG)
{
/* Check the parameters */
eth_assert_param(IS_ETH_DMA_FLAG(ETH_DMA_FLAG));
/* Clear the selected ETHERNET DMA FLAG */
ETH_DMA->DMASR = (u32) ETH_DMA_FLAG;
}
/*******************************************************************************
* Function Name : ETH_GetDMAITStatus
* Desciption : Checks whether the specified ETHERNET DMA interrupt has occured or not.
* Input : - ETH_DMA_IT: specifies the interrupt source to check.
* This parameter can be one of the following values:
* - ETH_DMA_IT_TST : Time-stamp trigger interrupt
* - ETH_DMA_IT_PMT : PMT interrupt
* - ETH_DMA_IT_MMC : MMC interrupt
* - ETH_DMA_IT_NIS : Normal interrupt summary
* - ETH_DMA_IT_AIS : Abnormal interrupt summary
* - ETH_DMA_IT_ER : Early receive interrupt
* - ETH_DMA_IT_FBE : Fatal bus error interrupt
* - ETH_DMA_IT_ET : Early transmit interrupt
* - ETH_DMA_IT_RWT : Receive watchdog timeout interrupt
* - ETH_DMA_IT_RPS : Receive process stopped interrupt
* - ETH_DMA_IT_RBU : Receive buffer unavailable interrupt
* - ETH_DMA_IT_R : Receive interrupt
* - ETH_DMA_IT_TU : Underflow interrupt
* - ETH_DMA_IT_RO : Overflow interrupt
* - ETH_DMA_IT_TJT : Transmit jabber timeout interrupt
* - ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt
* - ETH_DMA_IT_TPS : Transmit process stopped interrupt
* - ETH_DMA_IT_T : Transmit interrupt
* Output : None
* Return : The new state of ETH_DMA_IT (SET or RESET).
*******************************************************************************/
ITStatus ETH_GetDMAITStatus(u32 ETH_DMA_IT)
{
ITStatus bitstatus = RESET;
/* Check the parameters */
eth_assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_IT));
if ((ETH_DMA->DMASR & ETH_DMA_IT) != (u32)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : ETH_DMAClearITPendingBit
* Desciption : Clears the ETHERNET?s DMA IT pending bit.
* Input : - ETH_DMA_IT: specifies the interrupt pending bit to clear.
* This parameter can be any combination of the following values:
* - ETH_DMA_IT_NIS : Normal interrupt summary
* - ETH_DMA_IT_AIS : Abnormal interrupt summary
* - ETH_DMA_IT_ER : Early receive interrupt
* - ETH_DMA_IT_FBE : Fatal bus error interrupt
* - ETH_DMA_IT_ETI : Early transmit interrupt
* - ETH_DMA_IT_RWT : Receive watchdog timeout interrupt
* - ETH_DMA_IT_RPS : Receive process stopped interrupt
* - ETH_DMA_IT_RBU : Receive buffer unavailable interrupt
* - ETH_DMA_IT_R : Receive interrupt
* - ETH_DMA_IT_TU : Transmit Underflow interrupt
* - ETH_DMA_IT_RO : Receive Overflow interrupt
* - ETH_DMA_IT_TJT : Transmit jabber timeout interrupt
* - ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt
* - ETH_DMA_IT_TPS : Transmit process stopped interrupt
* - ETH_DMA_IT_T : Transmit interrupt
* Output : None
* Return : None
*******************************************************************************/
void ETH_DMAClearITPendingBit(u32 ETH_DMA_IT)
{
/* Check the parameters */
eth_assert_param(IS_ETH_DMA_IT(ETH_DMA_IT));
/* Clear the selected ETHERNET DMA IT */
ETH_DMA->DMASR = (u32) ETH_DMA_IT;
}
/*******************************************************************************
* Function Name : ETH_GetDMATransmitProcessState
* Desciption : Returns the ETHERNET DMA Transmit Process State.
* Input : None
* Output : None
* Return : The new ETHERNET DMA Transmit Process State:
* This can be one of the following values:
* - ETH_DMA_TransmitProcess_Stopped : Stopped - Reset or Stop Tx Command issued
* - ETH_DMA_TransmitProcess_Fetching : Running - fetching the Tx descriptor
* - ETH_DMA_TransmitProcess_Waiting : Running - waiting for status
* - ETH_DMA_TransmitProcess_Reading : unning - reading the data from host memory
* - ETH_DMA_TransmitProcess_Suspended : Suspended - Tx Desciptor unavailabe
* - ETH_DMA_TransmitProcess_Closing : Running - closing Rx descriptor
*******************************************************************************/
u32 ETH_GetTransmitProcessState(void)
{
return ((u32)(ETH_DMA->DMASR & ETH_DMASR_TS));
}
/*******************************************************************************
* Function Name : ETH_GetDMAReceiveProcessState
* Desciption : Returns the ETHERNET DMA Receive Process State.
* Input : None
* Output : None
* Return : The new ETHERNET DMA Receive Process State:
* This can be one of the following values:
* - ETH_DMA_ReceiveProcess_Stopped : Stopped - Reset or Stop Rx Command issued
* - ETH_DMA_ReceiveProcess_Fetching : Running - fetching the Rx descriptor
* - ETH_DMA_ReceiveProcess_Waiting : Running - waiting for packet
* - ETH_DMA_ReceiveProcess_Suspended : Suspended - Rx Desciptor unavailable
* - ETH_DMA_ReceiveProcess_Closing : Running - closing descriptor
* - ETH_DMA_ReceiveProcess_Queuing : Running - queuing the recieve frame into host memory
*******************************************************************************/
u32 ETH_GetReceiveProcessState(void)
{
return ((u32)(ETH_DMA->DMASR & ETH_DMASR_RS));
}
/*******************************************************************************
* Function Name : ETH_FlushTransmitFIFO
* Desciption : Clears the ETHERNET transmit FIFO.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void ETH_FlushTransmitFIFO(void)
{
/* Set the Flush Transmit FIFO bit */
ETH_DMA->DMAOMR |= ETH_DMAOMR_FTF;
}
/*******************************************************************************
* Function Name : ETH_GetFlushTransmitFIFOStatus
* Desciption : Checks whether the ETHERNET transmit FIFO bit is cleared or not.
* Input : None
* Output : None
* Return : The new state of ETHERNET flush transmit FIFO bit (SET or RESET).
*******************************************************************************/
FlagStatus ETH_GetFlushTransmitFIFOStatus(void)
{
FlagStatus bitstatus = RESET;
if ((ETH_DMA->DMAOMR & ETH_DMAOMR_FTF) != (u32)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : ETH_DMATransmissionCmd
* Desciption : Enables or disables the DMA transmission.
* Input : - NewState: new state of the DMA transmission.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void ETH_DMATransmissionCmd(FunctionalState NewState)
{
/* Check the parameters */
eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the DMA transmission */
ETH_DMA->DMAOMR |= ETH_DMAOMR_ST;
}
else
{
/* Disable the DMA transmission */
ETH_DMA->DMAOMR &= ~ETH_DMAOMR_ST;
}
}
/*******************************************************************************
* Function Name : ETH_DMAReceptionCmd
* Desciption : Enables or disables the DMA reception.
* Input : - NewState: new state of the DMA reception.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void ETH_DMAReceptionCmd(FunctionalState NewState)
{
/* Check the parameters */
eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the DMA reception */
ETH_DMA->DMAOMR |= ETH_DMAOMR_SR;
}
else
{
/* Disable the DMA reception */
ETH_DMA->DMAOMR &= ~ETH_DMAOMR_SR;
}
}
/*******************************************************************************
* Function Name : ETH_DMAITConfig
* Desciption : Enables or disables the specified ETHERNET DMA interrupts.
* Input : - ETH_DMA_IT: specifies the ETHERNET DMA interrupt sources to be
* enabled or disabled.
* This parameter can be any combination of the following values:
* - ETH_DMA_IT_NIS : Normal interrupt summary
* - ETH_DMA_IT_AIS : Abnormal interrupt summary
* - ETH_DMA_IT_ER : Early receive interrupt
* - ETH_DMA_IT_FBE : Fatal bus error interrupt
* - ETH_DMA_IT_ET : Early transmit interrupt
* - ETH_DMA_IT_RWT : Receive watchdog timeout interrupt
* - ETH_DMA_IT_RPS : Receive process stopped interrupt
* - ETH_DMA_IT_RBU : Receive buffer unavailable interrupt
* - ETH_DMA_IT_R : Receive interrupt
* - ETH_DMA_IT_TU : Underflow interrupt
* - ETH_DMA_IT_RO : Overflow interrupt
* - ETH_DMA_IT_TJT : Transmit jabber timeout interrupt
* - ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt
* - ETH_DMA_IT_TPS : Transmit process stopped interrupt
* - ETH_DMA_IT_T : Transmit interrupt
* - NewState: new state of the specified ETHERNET DMA interrupts.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void ETH_DMAITConfig(u32 ETH_DMA_IT, FunctionalState NewState)
{
/* Check the parameters */
eth_assert_param(IS_ETH_DMA_IT(ETH_DMA_IT));
eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected ETHERNET DMA interrupts */
ETH_DMA->DMAIER |= ETH_DMA_IT;
}
else
{
/* Disable the selected ETHERNET DMA interrupts */
ETH_DMA->DMAIER &=(~(u32)ETH_DMA_IT);
}
}
/*******************************************************************************
* Function Name : ETH_GetDMAOverflowStatus
* Desciption : Checks whether the specified ETHERNET DMA overflow flag is set or not.
* Input : - ETH_DMA_Overflow: specifies the DMA overflow flag to check.
* This parameter can be one of the following values:
* - ETH_DMA_Overflow_RxFIFOCounter : Overflow for FIFO Overflow Counter
* - ETH_DMA_Overflow_MissedFrameCounter : Overflow for Missed Frame Counter
* Output : None
* Return : The new state of ETHERNET DMA overflow Flag (SET or RESET).
*******************************************************************************/
FlagStatus ETH_GetDMAOverflowStatus(u32 ETH_DMA_Overflow)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
eth_assert_param(IS_ETH_DMA_GET_OVERFLOW(ETH_DMA_Overflow));
if ((ETH_DMA->DMAMFBOCR & ETH_DMA_Overflow) != (u32)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : ETH_GetRxOverflowMissedFrameCounter
* Desciption : Get the ETHERNET DMA Rx Overflow Missed Frame Counter value.
* Input : None
* Output : None
* Return : The value of Rx overflow Missed Frame Counter.
*******************************************************************************/
u32 ETH_GetRxOverflowMissedFrameCounter(void)
{
return ((u32)((ETH_DMA->DMAMFBOCR & ETH_DMAMFBOCR_MFA)>>ETH_DMA_RxOverflowMissedFramesCounterShift));
}
/*******************************************************************************
* Function Name : ETH_GetBufferUnavailableMissedFrameCounter
* Desciption : Get the ETHERNET DMA Buffer Unavailable Missed Frame Counter value.
* Input : None
* Output : None
* Return : The value of Buffer unavailable Missed Frame Counter.
*******************************************************************************/
u32 ETH_GetBufferUnavailableMissedFrameCounter(void)
{
return ((u32)(ETH_DMA->DMAMFBOCR) & ETH_DMAMFBOCR_MFC);
}
/*******************************************************************************
* Function Name : ETH_GetCurrentTxDescStartAddress
* Desciption : Get the ETHERNET DMA DMACHTDR register value.
* Input : None
* Output : None
* Return : The value of the current Tx desc start address.
*******************************************************************************/
u32 ETH_GetCurrentTxDescStartAddress(void)
{
return ((u32)(ETH_DMA->DMACHTDR));
}
/*******************************************************************************
* Function Name : ETH_GetCurrentRxDescStartAddress
* Desciption : Get the ETHERNET DMA DMACHRDR register value.
* Input : None
* Output : None
* Return : The value of the current Rx desc start address.
*******************************************************************************/
u32 ETH_GetCurrentRxDescStartAddress(void)
{
return ((u32)(ETH_DMA->DMACHRDR));
}
/*******************************************************************************
* Function Name : ETH_GetCurrentTxBufferAddress
* Desciption : Get the ETHERNET DMA DMACHTBAR register value.
* Input : None
* Output : None
* Return : The value of the current Tx desc buffer address.
*******************************************************************************/
u32 ETH_GetCurrentTxBufferAddress(void)
{
return ((u32)(ETH_DMA->DMACHTBAR));
}
/*******************************************************************************
* Function Name : ETH_GetCurrentRxBufferAddress
* Desciption : Get the ETHERNET DMA DMACHRBAR register value.
* Input : None
* Output : None
* Return : The value of the current Rx desc buffer address.
*******************************************************************************/
u32 ETH_GetCurrentRxBufferAddress(void)
{
return ((u32)(ETH_DMA->DMACHRBAR));
}
/*******************************************************************************
* Function Name : ETH_ResumeDMATransmission
* Desciption : Resumes the DMA Transmission by writing to the DmaTxPollDemand
* register: (the data written could be anything). This forces
* the DMA to resume transmission.
* Input : None
* Output : None
* Return : None.
*******************************************************************************/
void ETH_ResumeDMATransmission(void)
{
ETH_DMA->DMATPDR = 0;
}
/*******************************************************************************
* Function Name : ETH_ResumeDMAReception
* Desciption : Resumes the DMA Transmission by writing to the DmaRxPollDemand
* register: (the data written could be anything). This forces
* the DMA to resume reception.
* Input : None
* Output : None
* Return : None.
*******************************************************************************/
void ETH_ResumeDMAReception(void)
{
ETH_DMA->DMARPDR = 0;
}
#endif /* _ETH_DMA */
/*--------------------------------- PMT ------------------------------------*/
/*******************************************************************************
* Function Name : ETH_ResetWakeUpFrameFilterRegisterPointer
* Desciption : Reset Wakeup frame filter register pointer.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void ETH_ResetWakeUpFrameFilterRegisterPointer(void)
{
/* Resets the Remote Wake-up Frame Filter register pointer to 0x0000 */
ETH_MAC->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR;
}
/*******************************************************************************
* Function Name : ETH_SetWakeUpFrameFilterRegister
* Desciption : Populates the remote wakeup frame registers.
* Input : - Buffer: Pointer on remote WakeUp Frame Filter Register buffer
* data (8 words).
* Output : None
* Return : None
*******************************************************************************/
void ETH_SetWakeUpFrameFilterRegister(u32 *Buffer)
{
u32 i = 0;
/* Fill Remote Wake-up Frame Filter register with Buffer data */
for(i =0; i<ETH_WakeupRegisterLength; i++)
{
/* Write each time to the same register */
ETH_MAC->MACRWUFFR = Buffer[i];
}
}
/*******************************************************************************
* Function Name : ETH_GlobalUnicastWakeUpCmd
* Desciption : Enables or disables any unicast packet filtered by the MAC
* (DAF) address recognition to be a wake-up frame.
* Input : - NewState: new state of the MAC Global Unicast Wake-Up.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState)
{
/* Check the parameters */
eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the MAC Global Unicast Wake-Up */
ETH_MAC->MACPMTCSR |= ETH_MACPMTCSR_GU;
}
else
{
/* Disable the MAC Global Unicast Wake-Up */
ETH_MAC->MACPMTCSR &= ~ETH_MACPMTCSR_GU;
}
}
/*******************************************************************************
* Function Name : ETH_GetPMTFlagStatus
* Desciption : Checks whether the specified ETHERNET PMT flag is set or not.
* Input : - ETH_PMT_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* - ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Poniter Reset
* - ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
* - ETH_PMT_FLAG_MPR : Magic Packet Received
* Output : None
* Return : The new state of ETHERNET PMT Flag (SET or RESET).
*******************************************************************************/
FlagStatus ETH_GetPMTFlagStatus(u32 ETH_PMT_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
eth_assert_param(IS_ETH_PMT_GET_FLAG(ETH_PMT_FLAG));
if ((ETH_MAC->MACPMTCSR & ETH_PMT_FLAG) != (u32)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : ETH_WakeUpFrameDetectionCmd
* Desciption : Enables or disables the MAC Wake-Up Frame Detection.
* Input : - NewState: new state of the MAC Wake-Up Frame Detection.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState)
{
/* Check the parameters */
eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the MAC Wake-Up Frame Detection */
ETH_MAC->MACPMTCSR |= ETH_MACPMTCSR_WFE;
}
else
{
/* Disable the MAC Wake-Up Frame Detection */
ETH_MAC->MACPMTCSR &= ~ETH_MACPMTCSR_WFE;
}
}
/*******************************************************************************
* Function Name : ETH_MagicPacketDetectionCmd
* Desciption : Enables or disables the MAC Magic Packet Detection.
* Input : - NewState: new state of the MAC Magic Packet Detection.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void ETH_MagicPacketDetectionCmd(FunctionalState NewState)
{
/* Check the parameters */
eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the MAC Magic Packet Detection */
ETH_MAC->MACPMTCSR |= ETH_MACPMTCSR_MPE;
}
else
{
/* Disable the MAC Magic Packet Detection */
ETH_MAC->MACPMTCSR &= ~ETH_MACPMTCSR_MPE;
}
}
/*******************************************************************************
* Function Name : ETH_PowerDownCmd
* Desciption : Enables or disables the MAC Power Down.
* Input : - NewState: new state of the MAC Power Down.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void ETH_PowerDownCmd(FunctionalState NewState)
{
/* Check the parameters */
eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the MAC Power Down */
/* This puts the MAC in power down mode */
ETH_MAC->MACPMTCSR |= ETH_MACPMTCSR_PD;
}
else
{
/* Disable the MAC Power Down */
ETH_MAC->MACPMTCSR &= ~ETH_MACPMTCSR_PD;
}
}
/*--------------------------------- MMC ------------------------------------*/
#ifdef _ETH_MMC
/*******************************************************************************
* Function Name : ETH_MMCCounterFreezeCmd
* Desciption : Enables or disables the MMC Counter Freeze.
* Input : - NewState: new state of the MMC Counter Freeze.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void ETH_MMCCounterFreezeCmd(FunctionalState NewState)
{
/* Check the parameters */
eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the MMC Counter Freeze */
ETH_MMC->MMCCR |= ETH_MMCCR_MCF;
}
else
{
/* Disable the MMC Counter Freeze */
ETH_MMC->MMCCR &= ~ETH_MMCCR_MCF;
}
}
/*******************************************************************************
* Function Name : ETH_MMCResetOnReadCmd
* Desciption : Enables or disables the MMC Reset On Read.
* Input : - NewState: new state of the MMC Reset On Read.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void ETH_MMCResetOnReadCmd(FunctionalState NewState)
{
/* Check the parameters */
eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the MMC Counter reset on read */
ETH_MMC->MMCCR |= ETH_MMCCR_ROR;
}
else
{
/* Disable the MMC Counter reset on read */
ETH_MMC->MMCCR &= ~ETH_MMCCR_ROR;
}
}
/*******************************************************************************
* Function Name : ETH_MMCCounterRolloverCmd
* Desciption : Enables or disables the MMC Counter Stop Rollover.
* Input : - NewState: new state of the MMC Counter Stop Rollover.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void ETH_MMCCounterRolloverCmd(FunctionalState NewState)
{
/* Check the parameters */
eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Disable the MMC Counter Stop Rollover */
ETH_MMC->MMCCR &= ~ETH_MMCCR_CSR;
}
else
{
/* Enable the MMC Counter Stop Rollover */
ETH_MMC->MMCCR |= ETH_MMCCR_CSR;
}
}
/*******************************************************************************
* Function Name : ETH_MMCCountersReset
* Desciption : Resets the MMC Counters.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void ETH_MMCCountersReset(void)
{
/* Resets the MMC Counters */
ETH_MMC->MMCCR |= ETH_MMCCR_CR;
}
/*******************************************************************************
* Function Name : ETH_MMCITConfig
* Desciption : Enables or disables the specified ETHERNET MMC interrupts.
* Input : - ETH_MMC_IT: specifies the ETHERNET MMC interrupt
* sources to be enabled or disabled.
* This parameter can be any combination of Tx interrupt or
* any combination of Rx interrupt (but not both)of the following values:
* - ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
* - ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
* - ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
* - ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
* - ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
* - ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
* - NewState: new state of the specified ETHERNET MMC interrupts.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void ETH_MMCITConfig(u32 ETH_MMC_IT, FunctionalState NewState)
{
/* Check the parameters */
eth_assert_param(IS_ETH_MMC_IT(ETH_MMC_IT));
eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
if ((ETH_MMC_IT & (u32)0x10000000) != (u32)RESET)
{
/* Remove egister mak from IT */
ETH_MMC_IT &= 0xEFFFFFFF;
/* ETHERNET MMC Rx interrupts selected */
if (NewState != DISABLE)
{
/* Enable the selected ETHERNET MMC interrupts */
ETH_MMC->MMCRIMR &=(~(u32)ETH_MMC_IT);
}
else
{
/* Disable the selected ETHERNET MMC interrupts */
ETH_MMC->MMCRIMR |= ETH_MMC_IT;
}
}
else
{
/* ETHERNET MMC Tx interrupts selected */
if (NewState != DISABLE)
{
/* Enable the selected ETHERNET MMC interrupts */
ETH_MMC->MMCTIMR &=(~(u32)ETH_MMC_IT);
}
else
{
/* Disable the selected ETHERNET MMC interrupts */
ETH_MMC->MMCTIMR |= ETH_MMC_IT;
}
}
}
/*******************************************************************************
* Function Name : ETH_GetMMCITStatus
* Desciption : Checks whether the specified ETHERNET MMC IT is set or not.
* Input : - ETH_MMC_IT: specifies the ETHERNET MMC interrupt.
* This parameter can be one of the following values:
* - ETH_MMC_IT_TxFCGC: When Tx good frame counter reaches half the maximum value
* - ETH_MMC_IT_TxMCGC: When Tx good multi col counter reaches half the maximum value
* - ETH_MMC_IT_TxSCGC: When Tx good single col counter reaches half the maximum value
* - ETH_MMC_IT_RxUGFC: When Rx good unicast frames counter reaches half the maximum value
* - ETH_MMC_IT_RxAEC : When Rx alignment error counter reaches half the maximum value
* - ETH_MMC_IT_RxCEC : When Rx crc error counter reaches half the maximum value
* Output : None
* Return : The value of ETHERNET MMC IT (SET or RESET).
*******************************************************************************/
ITStatus ETH_GetMMCITStatus(u32 ETH_MMC_IT)
{
ITStatus bitstatus = RESET;
/* Check the parameters */
eth_assert_param(IS_ETH_MMC_GET_IT(ETH_MMC_IT));
if ((ETH_MMC_IT & (u32)0x10000000) != (u32)RESET)
{
/* ETHERNET MMC Rx interrupts selected */
/* Check if the ETHERNET MMC Rx selected interrupt is enabled and occured */
if ((((ETH_MMC->MMCRIR & ETH_MMC_IT) != (u32)RESET)) && ((ETH_MMC->MMCRIMR & ETH_MMC_IT) != (u32)RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
}
else
{
/* ETHERNET MMC Tx interrupts selected */
/* Check if the ETHERNET MMC Tx selected interrupt is enabled and occured */
if ((((ETH_MMC->MMCTIR & ETH_MMC_IT) != (u32)RESET)) && ((ETH_MMC->MMCRIMR & ETH_MMC_IT) != (u32)RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
}
return bitstatus;
}
/*******************************************************************************
* Function Name : ETH_GetMMCRegister
* Desciption : Get the specified ETHERNET MMC register value.
* Input : - ETH_MMCReg: specifies the ETHERNET MMC register.
* This parameter can be one of the following values:
* - ETH_MMCCR : MMC CR register
* - ETH_MMCRIR : MMC RIR register
* - ETH_MMCTIR : MMC TIR register
* - ETH_MMCRIMR : MMC RIMR register
* - ETH_MMCTIMR : MMC TIMR register
* - ETH_MMCTGFSCCR : MMC TGFSCCR register
* - ETH_MMCTGFMSCCR: MMC TGFMSCCR register
* - ETH_MMCTGFCR : MMC TGFCR register
* - ETH_MMCRFCECR : MMC RFCECR register
* - ETH_MMCRFAECR : MMC RFAECR register
* - ETH_MMCRGUFCR : MMC RGUFCRregister
* Output : None
* Return : The value of ETHERNET MMC Register value.
*******************************************************************************/
u32 ETH_GetMMCRegister(u32 ETH_MMCReg)
{
/* Check the parameters */
eth_assert_param(IS_ETH_MMC_REGISTER(ETH_MMCReg));
/* Return the selected register value */
return (*(vu32 *)(ETH_MAC_BASE + ETH_MMCReg));
}
#endif /* _ETH_MMC */
/*--------------------------------- PTP ------------------------------------*/
#ifdef _ETH_PTP
/*******************************************************************************
* Function Name : ETH_EnablePTPTimeStampAddend
* Desciption : Updated the PTP block for fine correction with the Time Stamp
* Addend register value.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void ETH_EnablePTPTimeStampAddend(void)
{
/* Enable the PTP block update with the Time Stamp Addend register value */
ETH_PTP->PTPTSCR |= ETH_PTPTSCR_TSARU;
}
/*******************************************************************************
* Function Name : ETH_EnablePTPTimeStampInterruptTrigger
* Desciption : Enable the PTP Time Stamp interrupt trigger
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void ETH_EnablePTPTimeStampInterruptTrigger(void)
{
/* Enable the PTP target time interrupt */
ETH_PTP->PTPTSCR |= ETH_PTPTSCR_TSITE;
}
/*******************************************************************************
* Function Name : ETH_EnablePTPTimeStampUpdate
* Desciption : Updated the PTP system time with the Time Stamp Update register
* value.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void ETH_EnablePTPTimeStampUpdate(void)
{
/* Enable the PTP system time update with the Time Stamp Update register value */
ETH_PTP->PTPTSCR |= ETH_PTPTSCR_TSSTU;
}
/*******************************************************************************
* Function Name : ETH_InitializePTPTimeStamp
* Desciption : Initialize the PTP Time Stamp
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void ETH_InitializePTPTimeStamp(void)
{
/* Initialize the PTP Time Stamp */
ETH_PTP->PTPTSCR |= ETH_PTPTSCR_TSSTI;
}
/*******************************************************************************
* Function Name : ETH_PTPUpdateMethodConfig
* Desciption : Selects the PTP Update method
* Input : - UpdateMethod: the PTP Update method
* This parameter can be one of the following values:
* - ETH_PTP_FineUpdate : Fine Update method
* - ETH_PTP_CoarseUpdate : Coarse Update method
* Output : None
* Return : None
*******************************************************************************/
void ETH_PTPUpdateMethodConfig(u32 UpdateMethod)
{
/* Check the parameters */
eth_assert_param(IS_ETH_PTP_UPDATE(UpdateMethod));
if (UpdateMethod != ETH_PTP_CoarseUpdate)
{
/* Enable the PTP Fine Update method */
ETH_PTP->PTPTSCR |= ETH_PTPTSCR_TSFCU;
}
else
{
/* Disable the PTP Coarse Update method */
ETH_PTP->PTPTSCR &= (~(u32)ETH_PTPTSCR_TSFCU);
}
}
/*******************************************************************************
* Function Name : ETH_PTPTimeStampCmd
* Desciption : Enables or disables the PTP time stamp for transmit and receive frames.
* Input : - NewState: new state of the PTP time stamp for transmit and receive frames
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void ETH_PTPTimeStampCmd(FunctionalState NewState)
{
/* Check the parameters */
eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the PTP time stamp for transmit and receive frames */
ETH_PTP->PTPTSCR |= ETH_PTPTSCR_TSE;
}
else
{
/* Disable the PTP time stamp for transmit and receive frames */
ETH_PTP->PTPTSCR &= (~(u32)ETH_PTPTSCR_TSE);
}
}
/*******************************************************************************
* Function Name : ETH_GetPTPFlagStatus
* Desciption : Checks whether the specified ETHERNET PTP flag is set or not.
* Input : - ETH_PTP_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* - ETH_PTP_FLAG_TSARU : Addend Register Update
* - ETH_PTP_FLAG_TSITE : Time Stamp Interrupt Trigger Enable
* - ETH_PTP_FLAG_TSSTU : Time Stamp Update
* - ETH_PTP_FLAG_TSSTI : Time Stamp Initialize
* Output : None
* Return : The new state of ETHERNET PTP Flag (SET or RESET).
*******************************************************************************/
FlagStatus ETH_GetPTPFlagStatus(u32 ETH_PTP_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
eth_assert_param(IS_ETH_PTP_GET_FLAG(ETH_PTP_FLAG));
if ((ETH_PTP->PTPTSCR & ETH_PTP_FLAG) != (u32)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : ETH_SetPTPSubSecondIncrement
* Desciption : Sets the system time Sub-Second Increment value.
* Input : - SubSecondValue: specifies the PTP Sub-Second Increment Register value.
* Output : None
* Return : None
*******************************************************************************/
void ETH_SetPTPSubSecondIncrement(u32 SubSecondValue)
{
/* Check the parameters */
eth_assert_param(IS_ETH_PTP_SUBSECOND_INCREMENT(SubSecondValue));
/* Set the PTP Sub-Second Increment Register */
ETH_PTP->PTPSSIR = SubSecondValue;
}
/*******************************************************************************
* Function Name : ETH_SetPTPTimeStampUpdate
* Desciption : Sets the Time Stamp update sign and values.
* Input : - Sign: specifies the PTP Time update value sign.
* This parameter can be one of the following values:
* - ETH_PTP_PositiveTime : positive time value.
* - ETH_PTP_NegativeTime : negative time value.
* - SecondValue: specifies the PTP Time update second value.
* - SubSecondValue: specifies the PTP Time update sub-second value.
* this is a 31 bit value. bit32 correspond to the sign.
* Output : None
* Return : None
*******************************************************************************/
void ETH_SetPTPTimeStampUpdate(u32 Sign, u32 SecondValue, u32 SubSecondValue)
{
/* Check the parameters */
eth_assert_param(IS_ETH_PTP_TIME_SIGN(Sign));
eth_assert_param(IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SubSecondValue));
/* Set the PTP Time Update High Register */
ETH_PTP->PTPTSHUR = SecondValue;
/* Set the PTP Time Update Low Register with sign */
ETH_PTP->PTPTSLUR = Sign | SubSecondValue;
}
/*******************************************************************************
* Function Name : ETH_SetPTPTimeStampAddend
* Desciption : Sets the Time Stamp Addend value.
* Input : - Value: specifies the PTP Time Stamp Addend Register value.
* Output : None
* Return : None
*******************************************************************************/
void ETH_SetPTPTimeStampAddend(u32 Value)
{
/* Set the PTP Time Stamp Addend Register */
ETH_PTP->PTPTSAR = Value;
}
/*******************************************************************************
* Function Name : ETH_SetPTPTargetTime
* Desciption : Sets the Target Time registers values.
* Input : - HighValue: specifies the PTP Target Time High Register value.
* - LowValue: specifies the PTP Target Time Low Register value.
* Output : None
* Return : None
*******************************************************************************/
void ETH_SetPTPTargetTime(u32 HighValue, u32 LowValue)
{
/* Set the PTP Target Time High Register */
ETH_PTP->PTPTTHR = HighValue;
/* Set the PTP Target Time Low Register */
ETH_PTP->PTPTTLR = LowValue;
}
/*******************************************************************************
* Function Name : ETH_GetPTPRegister
* Desciption : Get the specified ETHERNET PTP register value.
* Input : - ETH_PTPReg: specifies the ETHERNET PTP register.
* This parameter can be one of the following values:
* - ETH_PTPTSCR : Sub-Second Increment Register
* - ETH_PTPSSIR : Sub-Second Increment Register
* - ETH_PTPTSHR : Time Stamp High Register
* - ETH_PTPTSLR : Time Stamp Low Register
* - ETH_PTPTSHUR : Time Stamp High Update Register
* - ETH_PTPTSLUR : Time Stamp Low Update Register
* - ETH_PTPTSAR : Time Stamp Addend Register
* - ETH_PTPTTHR : Target Time High Register
* - ETH_PTPTTLR : Target Time Low Register
* Output : None
* Return : The value of ETHERNET PTP Register value.
*******************************************************************************/
u32 ETH_GetPTPRegister(u32 ETH_PTPReg)
{
/* Check the parameters */
eth_assert_param(IS_ETH_PTP_REGISTER(ETH_PTPReg));
/* Return the selected register value */
return (*(vu32 *)(ETH_MAC_BASE + ETH_PTPReg));
}
/*******************************************************************************
* Function Name : ETH_DMAPTPTxDescChainInit
* Desciption : Initializes the DMA Tx descriptors in chain mode with PTP.
* Input : - DMATxDescTab: Pointer on the first Tx desc list
* - DMAPTPTxDescTab: Pointer on the first PTP Tx desc list
* - TxBuff: Pointer on the first TxBuffer list
* - TxBuffCount: Number of the used Tx desc in the list
* Output : None
* Return : None
*******************************************************************************/
void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, u8* TxBuff, u32 TxBuffCount)
{
u32 i = 0;
ETH_DMADESCTypeDef *DMATxDesc;
/* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
DMATxDescToSet = DMATxDescTab;
DMAPTPTxDescToSet = DMAPTPTxDescTab;
/* Fill each DMATxDesc descriptor with the right values */
for(i=0; i < TxBuffCount; i++)
{
/* Get the pointer on the ith member of the Tx Desc list */
DMATxDesc = DMATxDescTab+i;
/* Set Second Address Chained bit and enable PTP */
DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_TTSE;
/* Set Buffer1 address pointer */
DMATxDesc->Buffer1Addr =(u32)(&TxBuff[i*ETH_MAX_PACKET_SIZE]);
/* Initialize the next descriptor with the Next Desciptor Polling Enable */
if(i < (TxBuffCount-1))
{
/* Set next descriptor address register with next descriptor base address */
DMATxDesc->Buffer2NextDescAddr = (u32)(DMATxDescTab+i+1);
}
else
{
/* For last descriptor, set next descriptor address register equal to the first descriptor base address */
DMATxDesc->Buffer2NextDescAddr = (u32) DMATxDescTab;
}
/* make DMAPTPTxDescTab points to the same addresses as DMATxDescTab */
(&DMAPTPTxDescTab[i])->Buffer1Addr = DMATxDesc->Buffer1Addr;
(&DMAPTPTxDescTab[i])->Buffer2NextDescAddr = DMATxDesc->Buffer2NextDescAddr;
}
/* Store on the last DMAPTPTxDescTab desc status record the first list address */
(&DMAPTPTxDescTab[i-1])->Status = (u32) DMAPTPTxDescTab;
/* Set Transmit Desciptor List Address Register */
ETH_DMA->DMATDLAR = (u32) DMATxDescTab;
}
/*******************************************************************************
* Function Name : ETH_DMAPTPRxDescChainInit
* Desciption : Initializes the DMA Rx descriptors in chain mode.
* Input : - DMARxDescTab: Pointer on the first Rx desc list
* - DMAPTPRxDescTab: Pointer on the first PTP Rx desc list
* - RxBuff: Pointer on the first RxBuffer list
* - RxBuffCount: Number of the used Rx desc in the list
* Output : None
* Return : None
*******************************************************************************/
void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, u8 *RxBuff, u32 RxBuffCount)
{
u32 i = 0;
ETH_DMADESCTypeDef *DMARxDesc;
/* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
DMARxDescToGet = DMARxDescTab;
DMAPTPRxDescToGet = DMAPTPRxDescTab;
/* Fill each DMARxDesc descriptor with the right values */
for(i=0; i < RxBuffCount; i++)
{
/* Get the pointer on the ith member of the Rx Desc list */
DMARxDesc = DMARxDescTab+i;
/* Set Own bit of the Rx descriptor Status */
DMARxDesc->Status = ETH_DMARxDesc_OWN;
/* Set Buffer1 size and Second Address Chained bit */
DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (u32)ETH_MAX_PACKET_SIZE;
/* Set Buffer1 address pointer */
DMARxDesc->Buffer1Addr = (u32)(&RxBuff[i*ETH_MAX_PACKET_SIZE]);
/* Initialize the next descriptor with the Next Desciptor Polling Enable */
if(i < (RxBuffCount-1))
{
/* Set next descriptor address register with next descriptor base address */
DMARxDesc->Buffer2NextDescAddr = (u32)(DMARxDescTab+i+1);
}
else
{
/* For last descriptor, set next descriptor address register equal to the first descriptor base address */
DMARxDesc->Buffer2NextDescAddr = (u32)(DMARxDescTab);
}
/* Make DMAPTPRxDescTab points to the same addresses as DMARxDescTab */
(&DMAPTPRxDescTab[i])->Buffer1Addr = DMARxDesc->Buffer1Addr;
(&DMAPTPRxDescTab[i])->Buffer2NextDescAddr = DMARxDesc->Buffer2NextDescAddr;
}
/* Store on the last DMAPTPRxDescTab desc status record the first list address */
(&DMAPTPRxDescTab[i-1])->Status = (u32) DMAPTPRxDescTab;
/* Set Receive Desciptor List Address Register */
ETH_DMA->DMARDLAR = (u32) DMARxDescTab;
}
/*******************************************************************************
* Function Name : ETH_HandlePTPTxPkt
* Desciption : Transmits a packet, from application buffer, pointed by ppkt with
* Time Stamp values.
* Input : - ppkt: pointer to application packet Buffer.
* - FrameLength: Tx Packet size.
* - PTPTxTab: Pointer on the first PTP Tx table to store Time stamp values.
* Output : None
* Return : ETH_ERROR: in case of Tx desc owned by DMA
* ETH_SUCCESS: for correct transmission
*******************************************************************************/
u32 ETH_HandlePTPTxPkt(u8 *ppkt, u16 FrameLength, u32 *PTPTxTab)
{
u32 offset = 0, timeout = 0;
/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (u32)RESET)
{
/* Return ERROR: OWN bit set */
return ETH_ERROR;
}
/* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */
for(offset=0; offset<FrameLength; offset++)
{
(*(vu8 *)((DMAPTPTxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset));
}
/* Setting the Frame Length: bits[12:0] */
DMATxDescToSet->ControlBufferSize = (FrameLength & (u32)0x1FFF);
/* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */
DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
/* When Tx Buffer unavailable flag is set: clear it and resume transmission */
if ((ETH_DMA->DMASR & ETH_DMASR_TBUS) != (u32)RESET)
{
/* Clear TBUS ETHERNET DMA flag */
ETH_DMA->DMASR = ETH_DMASR_TBUS;
/* Resume DMA transmission*/
ETH_DMA->DMATPDR = 0;
}
/* Wait for ETH_DMATxDesc_TTSS flag to be set */
do
{
timeout++;
} while (!(DMATxDescToSet->Status & ETH_DMATxDesc_TTSS) && (timeout < 0xFFFF));
/* Return ERROR in case of timeout */
if(timeout == PHY_READ_TO)
{
return ETH_ERROR;
}
*PTPTxTab++ = DMATxDescToSet->Buffer1Addr;
*PTPTxTab = DMATxDescToSet->Buffer2NextDescAddr;
/* Update the ENET DMA current descriptor */
/* Chained Mode */
if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (u32)RESET)
{
/* Selects the next DMA Tx descriptor list for next buffer read */
DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Buffer2NextDescAddr);
if(DMAPTPTxDescToSet->Status != 0)
{
DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Status);
}
else
{
DMAPTPTxDescToSet++;
}
}
else /* Ring Mode */
{
if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (u32)RESET)
{
/* Selects the next DMA Tx descriptor list for next buffer read: this will
be the first Tx descriptor in this case */
DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH_DMA->DMATDLAR);
DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (ETH_DMA->DMATDLAR);
}
else
{
/* Selects the next DMA Tx descriptor list for next buffer read */
DMATxDescToSet = (ETH_DMADESCTypeDef*) ((u32)DMATxDescToSet + 0x10 + ((ETH_DMA->DMABMR & ETH_DMABMR_DSL) >> 2));
DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) ((u32)DMAPTPTxDescToSet + 0x10 + ((ETH_DMA->DMABMR & ETH_DMABMR_DSL) >> 2));
}
}
/* Return SUCCESS */
return ETH_SUCCESS;
}
/*******************************************************************************
* Function Name : ETH_HandlePTPRxPkt
* Desciption : Receives a packet and copies it to memory pointed by ppkt with
* Time Stamp values.
* Input : - PTPRxTab: Pointer on the first PTP Rx table to store Time stamp values.
* Output : ppkt: pointer on application receive buffer.
* Return : ETH_ERROR: if there is error in reception
* Received packet size: if packet reception is correct
*******************************************************************************/
u32 ETH_HandlePTPRxPkt(u8 *ppkt, u32 *PTPRxTab)
{
u32 offset = 0, FrameLength = 0;
/* Check if the descriptor is owned by the ENET or CPU */
if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (u32)RESET)
{
/* Return error: OWN bit set */
return ETH_ERROR;
}
if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (u32)RESET) &&
((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (u32)RESET) &&
((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (u32)RESET))
{
/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
FrameLength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4;
/* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */
for(offset=0; offset<FrameLength; offset++)
{
(*(ppkt + offset)) = (*(vu8 *)((DMAPTPRxDescToGet->Buffer1Addr) + offset));
}
}
else
{
/* Return ERROR */
FrameLength = ETH_ERROR;
}
/* When Rx Buffer unavailable flag is set: clear it and resume reception */
if ((ETH_DMA->DMASR & ETH_DMASR_RBUS) != (u32)RESET)
{
/* Clear RBUS ETHERNET DMA flag */
ETH_DMA->DMASR = ETH_DMASR_RBUS;
/* Resume DMA reception */
ETH_DMA->DMARPDR = 0;
}
*PTPRxTab++ = DMARxDescToGet->Buffer1Addr;
*PTPRxTab = DMARxDescToGet->Buffer2NextDescAddr;
/* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */
DMARxDescToGet->Status |= ETH_DMARxDesc_OWN;
/* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */
/* Chained Mode */
if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (u32)RESET)
{
/* Selects the next DMA Rx descriptor list for next buffer read */
DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Buffer2NextDescAddr);
if(DMAPTPRxDescToGet->Status != 0)
{
DMAPTPRxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Status);
}
else
{
DMAPTPRxDescToGet++;
}
}
else /* Ring Mode */
{
if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (u32)RESET)
{
/* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */
DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH_DMA->DMARDLAR);
}
else
{
/* Selects the next DMA Rx descriptor list for next buffer to read */
DMARxDescToGet = (ETH_DMADESCTypeDef*) ((u32)DMARxDescToGet + 0x10 + ((ETH_DMA->DMABMR & ETH_DMABMR_DSL) >> 2));
}
}
/* Return Frame Length/ERROR */
return (FrameLength);
}
#endif /* _ETH_PTP */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32fxxx_eth.c | C | oos | 141,788 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_pwr.c
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file provides all the PWR firmware functions.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* --------- PWR registers bit address in the alias region ---------- */
#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
/* --- CR Register ---*/
/* Alias word address of DBP bit */
#define CR_OFFSET (PWR_OFFSET + 0x00)
#define DBP_BitNumber 0x08
#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
/* Alias word address of PVDE bit */
#define PVDE_BitNumber 0x04
#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
/* --- CSR Register ---*/
/* Alias word address of EWUP bit */
#define CSR_OFFSET (PWR_OFFSET + 0x04)
#define EWUP_BitNumber 0x08
#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
/* ------------------ PWR registers bit mask ------------------------ */
/* CR register bit mask */
#define CR_PDDS_Set ((u32)0x00000002)
#define CR_DS_Mask ((u32)0xFFFFFFFC)
#define CR_CWUF_Set ((u32)0x00000004)
#define CR_PLS_Mask ((u32)0xFFFFFF1F)
/* --------- Cortex System Control register bit mask ---------------- */
/* Cortex System Control register address */
#define SCB_SysCtrl ((u32)0xE000ED10)
/* SLEEPDEEP bit mask */
#define SysCtrl_SLEEPDEEP_Set ((u32)0x00000004)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : PWR_DeInit
* Description : Deinitializes the PWR peripheral registers to their default
* reset values.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void PWR_DeInit(void)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
}
/*******************************************************************************
* Function Name : PWR_BackupAccessCmd
* Description : Enables or disables access to the RTC and backup registers.
* Input : - NewState: new state of the access to the RTC and backup
* registers. This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void PWR_BackupAccessCmd(FunctionalState NewState)
{
/* Check the parameters */
assert(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) CR_DBP_BB = (u32)NewState;
}
/*******************************************************************************
* Function Name : PWR_PVDCmd
* Description : Enables or disables the Power Voltage Detector(PVD).
* Input : - NewState: new state of the PVD.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void PWR_PVDCmd(FunctionalState NewState)
{
/* Check the parameters */
assert(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) CR_PVDE_BB = (u32)NewState;
}
/*******************************************************************************
* Function Name : PWR_PVDLevelConfig
* Description : Configures the value detected by the Power Voltage Detector(PVD).
* Input : - PWR_PVDLevel: specifies the PVD detection level
* This parameter can be one of the following values:
* - PWR_PVDLevel_2V2: PVD detection level set to 2.2V
* - PWR_PVDLevel_2V3: PVD detection level set to 2.3V
* - PWR_PVDLevel_2V4: PVD detection level set to 2.4V
* - PWR_PVDLevel_2V5: PVD detection level set to 2.5V
* - PWR_PVDLevel_2V6: PVD detection level set to 2.6V
* - PWR_PVDLevel_2V7: PVD detection level set to 2.7V
* - PWR_PVDLevel_2V8: PVD detection level set to 2.8V
* - PWR_PVDLevel_2V9: PVD detection level set to 2.9V
* Output : None
* Return : None
*******************************************************************************/
void PWR_PVDLevelConfig(u32 PWR_PVDLevel)
{
u32 tmpreg = 0;
/* Check the parameters */
assert(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
tmpreg = PWR->CR;
/* Clear PLS[7:5] bits */
tmpreg &= CR_PLS_Mask;
/* Set PLS[7:5] bits according to PWR_PVDLevel value */
tmpreg |= PWR_PVDLevel;
/* Store the new value */
PWR->CR = tmpreg;
}
/*******************************************************************************
* Function Name : PWR_WakeUpPinCmd
* Description : Enables or disables the WakeUp Pin functionality.
* Input : - NewState: new state of the WakeUp Pin functionality.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void PWR_WakeUpPinCmd(FunctionalState NewState)
{
/* Check the parameters */
assert(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) CSR_EWUP_BB = (u32)NewState;
}
/*******************************************************************************
* Function Name : PWR_EnterSTOPMode
* Description : Enters STOP mode.
* Input : - PWR_Regulator: specifies the regulator state in STOP mode.
* This parameter can be one of the following values:
* - PWR_Regulator_ON: STOP mode with regulator ON
* - PWR_Regulator_LowPower: STOP mode with
* regulator in low power mode
* - PWR_STOPEntry: specifies if STOP mode in entered with WFI or
* WFE instruction.
* This parameter can be one of the following values:
* - PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
* - PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
* Output : None
* Return : None
*******************************************************************************/
void PWR_EnterSTOPMode(u32 PWR_Regulator, u8 PWR_STOPEntry)
{
u32 tmpreg = 0;
/* Check the parameters */
assert(IS_PWR_REGULATOR(PWR_Regulator));
assert(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
/* Select the regulator state in STOP mode ---------------------------------*/
tmpreg = PWR->CR;
/* Clear PDDS and LPDS bits */
tmpreg &= CR_DS_Mask;
/* Set LPDS bit according to PWR_Regulator value */
tmpreg |= PWR_Regulator;
/* Store the new value */
PWR->CR = tmpreg;
/* Set SLEEPDEEP bit of Cortex System Control Register */
*(vu32 *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;
/* Select STOP mode entry --------------------------------------------------*/
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
/* Request Wait For Event */
__WFE();
}
}
/*******************************************************************************
* Function Name : PWR_EnterSTANDBYMode
* Description : Enters STANDBY mode.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void PWR_EnterSTANDBYMode(void)
{
/* Clear Wake-up flag */
PWR->CR |= CR_CWUF_Set;
/* Select STANDBY mode */
PWR->CR |= CR_PDDS_Set;
/* Set SLEEPDEEP bit of Cortex System Control Register */
*(vu32 *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;
/* Request Wait For Interrupt */
__WFI();
}
/*******************************************************************************
* Function Name : PWR_GetFlagStatus
* Description : Checks whether the specified PWR flag is set or not.
* Input : - PWR_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* - PWR_FLAG_WU: Wake Up flag
* - PWR_FLAG_SB: StandBy flag
* - PWR_FLAG_PVDO: PVD Output
* Output : None
* Return : The new state of PWR_FLAG (SET or RESET).
*******************************************************************************/
FlagStatus PWR_GetFlagStatus(u32 PWR_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert(IS_PWR_GET_FLAG(PWR_FLAG));
if ((PWR->CSR & PWR_FLAG) != (u32)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
/* Return the flag status */
return bitstatus;
}
/*******************************************************************************
* Function Name : PWR_ClearFlag
* Description : Clears the PWR's pending flags.
* Input : - PWR_FLAG: specifies the flag to clear.
* This parameter can be one of the following values:
* - PWR_FLAG_WU: Wake Up flag
* - PWR_FLAG_SB: StandBy flag
* Output : None
* Return : None
*******************************************************************************/
void PWR_ClearFlag(u32 PWR_FLAG)
{
/* Check the parameters */
assert(IS_PWR_CLEAR_FLAG(PWR_FLAG));
PWR->CR |= PWR_FLAG << 2;
}
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_pwr.c | C | oos | 11,242 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_systick.c
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file provides all the SysTick firmware functions.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_systick.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ---------------------- SysTick registers bit mask -------------------- */
/* CTRL TICKINT Mask */
#define CTRL_TICKINT_Set ((u32)0x00000002)
#define CTRL_TICKINT_Reset ((u32)0xFFFFFFFD)
/* SysTick Flag Mask */
#define FLAG_Mask ((u8)0x1F)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : SysTick_CLKSourceConfig
* Description : Configures the SysTick clock source.
* Input : - SysTick_CLKSource: specifies the SysTick clock source.
* This parameter can be one of the following values:
* - SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8
* selected as SysTick clock source.
* - SysTick_CLKSource_HCLK: AHB clock selected as
* SysTick clock source.
* Output : None
* Return : None
*******************************************************************************/
void SysTick_CLKSourceConfig(u32 SysTick_CLKSource)
{
/* Check the parameters */
assert(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
{
SysTick->CTRL |= SysTick_CLKSource_HCLK;
}
else
{
SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
}
}
/*******************************************************************************
* Function Name : SysTick_SetReload
* Description : Sets SysTick Reload value.
* Input : - Reload: SysTick Reload new value.
* This parameter must be a number between 1 and 0xFFFFFF.
* Output : None
* Return : None
*******************************************************************************/
void SysTick_SetReload(u32 Reload)
{
/* Check the parameters */
assert(IS_SYSTICK_RELOAD(Reload));
SysTick->LOAD = Reload;
}
/*******************************************************************************
* Function Name : SysTick_CounterCmd
* Description : Enables or disables the SysTick counter.
* Input : - SysTick_Counter: new state of the SysTick counter.
* This parameter can be one of the following values:
* - SysTick_Counter_Disable: Disable counter
* - SysTick_Counter_Enable: Enable counter
* - SysTick_Counter_Clear: Clear counter value to 0
* Output : None
* Return : None
*******************************************************************************/
void SysTick_CounterCmd(u32 SysTick_Counter)
{
/* Check the parameters */
assert(IS_SYSTICK_COUNTER(SysTick_Counter));
if (SysTick_Counter == SysTick_Counter_Clear)
{
SysTick->VAL = SysTick_Counter_Clear;
}
else
{
if (SysTick_Counter == SysTick_Counter_Enable)
{
SysTick->CTRL |= SysTick_Counter_Enable;
}
else
{
SysTick->CTRL &= SysTick_Counter_Disable;
}
}
}
/*******************************************************************************
* Function Name : SysTick_ITConfig
* Description : Enables or disables the SysTick Interrupt.
* Input : - NewState: new state of the SysTick Interrupt.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void SysTick_ITConfig(FunctionalState NewState)
{
/* Check the parameters */
assert(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
SysTick->CTRL |= CTRL_TICKINT_Set;
}
else
{
SysTick->CTRL &= CTRL_TICKINT_Reset;
}
}
/*******************************************************************************
* Function Name : SysTick_GetCounter
* Description : Gets SysTick counter value.
* Input : None
* Output : None
* Return : SysTick current value
*******************************************************************************/
u32 SysTick_GetCounter(void)
{
return(SysTick->VAL);
}
/*******************************************************************************
* Function Name : SysTick_GetFlagStatus
* Description : Checks whether the specified SysTick flag is set or not.
* Input : - SysTick_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* - SysTick_FLAG_COUNT
* - SysTick_FLAG_SKEW
* - SysTick_FLAG_NOREF
* Output : None
* Return : None
*******************************************************************************/
FlagStatus SysTick_GetFlagStatus(u8 SysTick_FLAG)
{
u32 tmp = 0;
u32 statusreg = 0;
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert(IS_SYSTICK_FLAG(SysTick_FLAG));
/* Get the SysTick register index */
tmp = SysTick_FLAG >> 5;
if (tmp == 1) /* The flag to check is in CTRL register */
{
statusreg = SysTick->CTRL;
}
else /* The flag to check is in CALIB register */
{
statusreg = SysTick->CALIB;
}
/* Get the flag position */
tmp = SysTick_FLAG & FLAG_Mask;
if ((statusreg & ((u32)1 << tmp)) != (u32)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_systick.c | C | oos | 7,196 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_gpio.c
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file provides all the GPIO firmware functions.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_gpio.h"
#include "stm32f10x_rcc.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ------------ RCC registers bit address in the alias region ----------- */
#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)
/* --- EVENTCR Register ---*/
/* Alias word address of EVOE bit */
#define EVCR_OFFSET (AFIO_OFFSET + 0x00)
#define EVOE_BitNumber ((u8)0x07)
#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
#define EVCR_PORTPINCONFIG_MASK ((u16)0xFF80)
#define LSB_MASK ((u16)0xFFFF)
#define DBGAFR_POSITION_MASK ((u32)0x000F0000)
#define DBGAFR_SWJCFG_MASK ((u32)0xF8FFFFFF)
#define DBGAFR_LOCATION_MASK ((u32)0x00200000)
#define DBGAFR_NUMBITS_MASK ((u32)0x00100000)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : GPIO_DeInit
* Description : Deinitializes the GPIOx peripheral registers to their default
* reset values.
* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
* Output : None
* Return : None
*******************************************************************************/
void GPIO_DeInit(GPIO_TypeDef* GPIOx)
{
switch (*(u32*)&GPIOx)
{
case GPIOA_BASE:
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
break;
case GPIOB_BASE:
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
break;
case GPIOC_BASE:
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
break;
case GPIOD_BASE:
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
break;
case GPIOE_BASE:
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
break;
default:
break;
}
}
/*******************************************************************************
* Function Name : GPIO_AFIODeInit
* Description : Deinitializes the Alternate Functions (remap, event control
* and EXTI configuration) registers to their default reset
* values.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void GPIO_AFIODeInit(void)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
}
/*******************************************************************************
* Function Name : GPIO_Init
* Description : Initializes the GPIOx peripheral according to the specified
* parameters in the GPIO_InitStruct.
* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
* - GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
* contains the configuration information for the specified GPIO
* peripheral.
* Output : None
* Return : None
*******************************************************************************/
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
{
u32 currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
u32 tmpreg = 0x00, pinmask = 0x00;
/* Check the parameters */
assert(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
assert(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
/*---------------------------- GPIO Mode Configuration -----------------------*/
currentmode = ((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x0F);
if ((((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x10)) != 0x00)
{
/* Check the parameters */
assert(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
/* Output mode */
currentmode |= (u32)GPIO_InitStruct->GPIO_Speed;
}
/*---------------------------- GPIO CRL Configuration ------------------------*/
/* Configure the eight low port pins */
if (((u32)GPIO_InitStruct->GPIO_Pin & ((u32)0x00FF)) != 0x00)
{
tmpreg = GPIOx->CRL;
for (pinpos = 0x00; pinpos < 0x08; pinpos++)
{
pos = ((u32)0x01) << pinpos;
/* Get the port pins position */
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
if (currentpin == pos)
{
pos = pinpos << 2;
/* Clear the corresponding low control register bits */
pinmask = ((u32)0x0F) << pos;
tmpreg &= ~pinmask;
/* Write the mode configuration in the corresponding bits */
tmpreg |= (currentmode << pos);
/* Reset the corresponding ODR bit */
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
{
GPIOx->BRR = (((u32)0x01) << pinpos);
}
/* Set the corresponding ODR bit */
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
{
GPIOx->BSRR = (((u32)0x01) << pinpos);
}
}
}
GPIOx->CRL = tmpreg;
tmpreg = 0;
}
/*---------------------------- GPIO CRH Configuration ------------------------*/
/* Configure the eight high port pins */
if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
{
tmpreg = GPIOx->CRH;
for (pinpos = 0x00; pinpos < 0x08; pinpos++)
{
pos = (((u32)0x01) << (pinpos + 0x08));
/* Get the port pins position */
currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
if (currentpin == pos)
{
pos = pinpos << 2;
/* Clear the corresponding high control register bits */
pinmask = ((u32)0x0F) << pos;
tmpreg &= ~pinmask;
/* Write the mode configuration in the corresponding bits */
tmpreg |= (currentmode << pos);
/* Reset the corresponding ODR bit */
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
{
GPIOx->BRR = (((u32)0x01) << (pinpos + 0x08));
}
/* Set the corresponding ODR bit */
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
{
GPIOx->BSRR = (((u32)0x01) << (pinpos + 0x08));
}
}
}
GPIOx->CRH = tmpreg;
}
}
/*******************************************************************************
* Function Name : GPIO_StructInit
* Description : Fills each GPIO_InitStruct member with its default value.
* Input : - GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure
* which will be initialized.
* Output : None
* Return : None
*******************************************************************************/
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
{
/* Reset GPIO init structure parameters values */
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
}
/*******************************************************************************
* Function Name : GPIO_ReadInputDataBit
* Description : Reads the specified input port pin.
* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
* : - GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_Pin_x where x can be (0..15).
* Output : None
* Return : The input port pin value.
*******************************************************************************/
u8 GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)
{
u8 bitstatus = 0x00;
/* Check the parameters */
assert(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != (u32)Bit_RESET)
{
bitstatus = (u8)Bit_SET;
}
else
{
bitstatus = (u8)Bit_RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : GPIO_ReadInputData
* Description : Reads the specified GPIO input data port.
* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
* Output : None
* Return : GPIO input data port value.
*******************************************************************************/
u16 GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
{
return ((u16)GPIOx->IDR);
}
/*******************************************************************************
* Function Name : GPIO_ReadOutputDataBit
* Description : Reads the specified output data port bit.
* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
* : - GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_Pin_x where x can be (0..15).
* Output : None
* Return : The output port pin value.
*******************************************************************************/
u8 GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)
{
u8 bitstatus = 0x00;
/* Check the parameters */
assert(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->ODR & GPIO_Pin) != (u32)Bit_RESET)
{
bitstatus = (u8)Bit_SET;
}
else
{
bitstatus = (u8)Bit_RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : GPIO_ReadOutputData
* Description : Reads the specified GPIO output data port.
* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
* Output : None
* Return : GPIO output data port value.
*******************************************************************************/
u16 GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
{
return ((u16)GPIOx->ODR);
}
/*******************************************************************************
* Function Name : GPIO_WriteBit
* Description : Sets or clears the selected data port bit.
* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
* - GPIO_Pin: specifies the port bit to be written.
* This parameter can be GPIO_Pin_x where x can be (0..15).
* - BitVal: specifies the value to be written to the selected bit.
* This parameter can be one of the BitAction enum values:
* - Bit_RESET: to clear the port pin
* - Bit_SET: to set the port pin
* Output : None
* Return : None
*******************************************************************************/
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin, BitAction BitVal)
{
/* Check the parameters */
assert(IS_GPIO_PIN(GPIO_Pin));
assert(IS_GPIO_BIT_ACTION(BitVal));
if (BitVal != Bit_RESET)
{
GPIOx->BSRR = GPIO_Pin;
}
else
{
GPIOx->BRR = GPIO_Pin;
}
}
/*******************************************************************************
* Function Name : GPIO_Write
* Description : Writes data to the specified GPIO data port.
* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
* - PortVal: specifies the value to be written to the port output
* data register.
* Output : None
* Return : None
*******************************************************************************/
void GPIO_Write(GPIO_TypeDef* GPIOx, u16 PortVal)
{
GPIOx->ODR = PortVal;
}
/*******************************************************************************
* Function Name : GPIO_PinLockConfig
* Description : Locks GPIO Pins configuration registers.
* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
* - GPIO_Pin: specifies the port bit to be written.
* This parameter can be GPIO_Pin_x where x can be (0..15).
* Output : None
* Return : None
*******************************************************************************/
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)
{
u32 tmp = 0x00010000;
/* Check the parameters */
assert(IS_GPIO_PIN(GPIO_Pin));
tmp |= GPIO_Pin;
/* Set LCKK bit */
GPIOx->LCKR = tmp;
/* Reset LCKK bit */
GPIOx->LCKR = GPIO_Pin;
/* Set LCKK bit */
GPIOx->LCKR = tmp;
/* Read LCKK bit*/
tmp = GPIOx->LCKR;
/* Read LCKK bit*/
tmp = GPIOx->LCKR;
}
/*******************************************************************************
* Function Name : GPIO_EventOutputConfig
* Description : Selects the GPIO pin used as Event output.
* Input : - GPIO_PortSource: selects the GPIO port to be used as source
* for Event output.
* This parameter can be GPIO_PortSourceGPIOx where x can be
* (A..E).
* - GPIO_PinSource: specifies the pin for the Event output.
* This parameter can be GPIO_PinSourcex where x can be (0..15).
* Output : None
* Return : None
*******************************************************************************/
void GPIO_EventOutputConfig(u8 GPIO_PortSource, u8 GPIO_PinSource)
{
u32 tmpreg = 0x00;
/* Check the parameters */
assert(IS_GPIO_PORT_SOURCE(GPIO_PortSource));
assert(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
tmpreg = AFIO->EVCR;
/* Clear the PORT[6:4] and PIN[3:0] bits */
tmpreg &= EVCR_PORTPINCONFIG_MASK;
tmpreg |= (u32)GPIO_PortSource << 0x04;
tmpreg |= GPIO_PinSource;
AFIO->EVCR = tmpreg;
}
/*******************************************************************************
* Function Name : GPIO_EventOutputCmd
* Description : Enables or disables the Event Output.
* Input : - NewState: new state of the Event output.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void GPIO_EventOutputCmd(FunctionalState NewState)
{
/* Check the parameters */
assert(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) EVCR_EVOE_BB = (u32)NewState;
}
/*******************************************************************************
* Function Name : GPIO_PinRemapConfig
* Description : Changes the mapping of the specified pin.
* Input : - GPIO_Remap: selects the pin to remap.
* This parameter can be one of the following values:
* - GPIO_Remap_SPI1
* - GPIO_Remap_I2C1
* - GPIO_Remap_USART1
* - GPIO_Remap_USART2
* - GPIO_PartialRemap_USART3
* - GPIO_FullRemap_USART3
* - GPIO_PartialRemap_TIM1
* - GPIO_FullRemap_TIM1
* - GPIO_PartialRemap1_TIM2
* - GPIO_PartialRemap2_TIM2
* - GPIO_FullRemap_TIM2
* - GPIO_PartialRemap_TIM3
* - GPIO_FullRemap_TIM3
* - GPIO_Remap_TIM4
* - GPIO_Remap1_CAN
* - GPIO_Remap2_CAN
* - GPIO_Remap_PD01
* - GPIO_Remap_SWJ_NoJTRST
* - GPIO_Remap_SWJ_JTAGDisable
* - GPIO_Remap_SWJ_Disable
* - NewState: new state of the port pin remapping.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void GPIO_PinRemapConfig(u32 GPIO_Remap, FunctionalState NewState)
{
u32 tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
/* Check the parameters */
assert(IS_GPIO_REMAP(GPIO_Remap));
assert(IS_FUNCTIONAL_STATE(NewState));
tmpreg = AFIO->MAPR;
tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
tmp = GPIO_Remap & LSB_MASK;
if ((GPIO_Remap & DBGAFR_LOCATION_MASK) == DBGAFR_LOCATION_MASK)
{
tmpreg &= DBGAFR_SWJCFG_MASK;
}
else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)
{
tmp1 = ((u32)0x03) << tmpmask;
tmpreg &= ~tmp1;
}
else
{
tmpreg &= ~tmp;
}
if (NewState != DISABLE)
{
if ((GPIO_Remap & DBGAFR_LOCATION_MASK) == DBGAFR_LOCATION_MASK)
{
tmpreg |= (tmp << 0x10);
}
else
{
tmpreg |= tmp;
}
}
AFIO->MAPR = tmpreg;
}
/*******************************************************************************
* Function Name : GPIO_EXTILineConfig
* Description : Selects the GPIO pin used as EXTI Line.
* Input : - GPIO_PortSource: selects the GPIO port to be used as
* source for EXTI lines.
* - GPIO_PinSource: specifies the EXTI line to be configured.
* This parameter can be GPIO_PinSourcex where x can be (0..15).
* Output : None
* Return : None
*******************************************************************************/
void GPIO_EXTILineConfig(u8 GPIO_PortSource, u8 GPIO_PinSource)
{
u32 tmp = 0x00;
/* Check the parameters */
assert(IS_GPIO_PORT_SOURCE(GPIO_PortSource));
assert(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
tmp = ((u32)0x0F) << (0x04 * (GPIO_PinSource & (u8)0x03));
AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((u32)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (u8)0x03)));
}
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_gpio.c | C | oos | 19,602 |
/**
******************************************************************************
* @file stm32f10x_dbgmcu.c
* @author MCD Application Team
* @version V3.0.0
* @date 04/06/2009
* @brief This file provides all the DBGMCU firmware functions.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_dbgmcu.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @defgroup DBGMCU
* @brief DBGMCU driver modules
* @{
*/
/** @defgroup DBGMCU_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup DBGMCU_Private_Defines
* @{
*/
#define IDCODE_DEVID_Mask ((uint32_t)0x00000FFF)
/**
* @}
*/
/** @defgroup DBGMCU_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup DBGMCU_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup DBGMCU_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup DBGMCU_Private_Functions
* @{
*/
/**
* @brief Returns the device revision identifier.
* @param None
* @retval : Device revision identifier
*/
uint32_t DBGMCU_GetREVID(void)
{
return(DBGMCU->IDCODE >> 16);
}
/**
* @brief Returns the device identifier.
* @param None
* @retval : Device identifier
*/
uint32_t DBGMCU_GetDEVID(void)
{
return(DBGMCU->IDCODE & IDCODE_DEVID_Mask);
}
/**
* @brief Configures the specified peripheral and low power mode behavior
* when the MCU under Debug mode.
* @param DBGMCU_Periph: specifies the peripheral and low power mode.
* This parameter can be any combination of the following values:
* @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
* @arg DBGMCU_STOP: Keep debugger connection during STOP mode
* @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
* @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
* @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
* @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
* @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
* @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
* @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
* @arg DBGMCU_CAN1_STOP: Debug CAN 1 stopped when Core is halted
* @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is
* halted
* @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is
* halted
* @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
* @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
* @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
* @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
* @param NewState: new state of the specified peripheral in Debug mode.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
*/
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
DBGMCU->CR |= DBGMCU_Periph;
}
else
{
DBGMCU->CR &= ~DBGMCU_Periph;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_dbgmcu.c | C | oos | 4,310 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_wwdg.c
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file provides all the WWDG firmware functions.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_wwdg.h"
#include "stm32f10x_rcc.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ----------- WWDG registers bit address in the alias region ----------- */
#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)
/* Alias word address of EWI bit */
#define CFR_OFFSET (WWDG_OFFSET + 0x04)
#define EWI_BitNumber 0x09
#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
/* Alias word address of EWIF bit */
#define SR_OFFSET (WWDG_OFFSET + 0x08)
#define EWIF_BitNumber 0x00
#define SR_EWIF_BB (PERIPH_BB_BASE + (SR_OFFSET * 32) + (EWIF_BitNumber * 4))
/* --------------------- WWDG registers bit mask ------------------------ */
/* CR register bit mask */
#define CR_WDGA_Set ((u32)0x00000080)
/* CFR register bit mask */
#define CFR_WDGTB_Mask ((u32)0xFFFFFE7F)
#define CFR_W_Mask ((u32)0xFFFFFF80)
#define BIT_Mask ((u8)0x7F)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : WWDG_DeInit
* Description : Deinitializes the WWDG peripheral registers to their default
* reset values.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void WWDG_DeInit(void)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
}
/*******************************************************************************
* Function Name : WWDG_SetPrescaler
* Description : Sets the WWDG Prescaler.
* Input : - WWDG_Prescaler: specifies the WWDG Prescaler.
* This parameter can be one of the following values:
* - WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
* - WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
* - WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
* - WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
* Output : None
* Return : None
*******************************************************************************/
void WWDG_SetPrescaler(u32 WWDG_Prescaler)
{
u32 tmpreg = 0;
/* Check the parameters */
assert(IS_WWDG_PRESCALER(WWDG_Prescaler));
/* Clear WDGTB[8:7] bits */
tmpreg = WWDG->CFR & CFR_WDGTB_Mask;
/* Set WDGTB[8:7] bits according to WWDG_Prescaler value */
tmpreg |= WWDG_Prescaler;
/* Store the new value */
WWDG->CFR = tmpreg;
}
/*******************************************************************************
* Function Name : WWDG_SetWindowValue
* Description : Sets the WWDG window value.
* Input : - WindowValue: specifies the window value to be compared to
* the downcounter.
* This parameter value must be lower than 0x80.
* Output : None
* Return : None
*******************************************************************************/
void WWDG_SetWindowValue(u8 WindowValue)
{
u32 tmpreg = 0;
/* Check the parameters */
assert(IS_WWDG_WINDOW_VALUE(WindowValue));
/* Clear W[6:0] bits */
tmpreg = WWDG->CFR & CFR_W_Mask;
/* Set W[6:0] bits according to WindowValue value */
tmpreg |= WindowValue & BIT_Mask;
/* Store the new value */
WWDG->CFR = tmpreg;
}
/*******************************************************************************
* Function Name : WWDG_EnableIT
* Description : Enables the WWDG Early Wakeup interrupt(EWI).
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void WWDG_EnableIT(void)
{
*(vu32 *) CFR_EWI_BB = (u32)ENABLE;
}
/*******************************************************************************
* Function Name : WWDG_SetCounter
* Description : Sets the WWDG counter value.
* Input : - Counter: specifies the watchdog counter value.
* This parameter must be a number between 0x40 and 0x7F.
* Output : None
* Return : None
*******************************************************************************/
void WWDG_SetCounter(u8 Counter)
{
/* Check the parameters */
assert(IS_WWDG_COUNTER(Counter));
/* Write to T[6:0] bits to configure the counter value, no need to do
a read-modify-write; writing a 0 to WDGA bit does nothing */
WWDG->CR = Counter & BIT_Mask;
}
/*******************************************************************************
* Function Name : WWDG_Enable
* Description : Enables WWDG and load the counter value.
* - Counter: specifies the watchdog counter value.
* This parameter must be a number between 0x40 and 0x7F.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void WWDG_Enable(u8 Counter)
{
/* Check the parameters */
assert(IS_WWDG_COUNTER(Counter));
WWDG->CR = CR_WDGA_Set | Counter;
}
/*******************************************************************************
* Function Name : WWDG_GetFlagStatus
* Description : Checks whether the Early Wakeup interrupt flag is set or not.
* Input : None
* Output : None
* Return : The new state of the Early Wakeup interrupt flag (SET or RESET)
*******************************************************************************/
FlagStatus WWDG_GetFlagStatus(void)
{
return (FlagStatus)(*(vu32 *) SR_EWIF_BB);
}
/*******************************************************************************
* Function Name : WWDG_ClearFlag
* Description : Clears Early Wakeup interrupt flag.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void WWDG_ClearFlag(void)
{
WWDG->SR = (u32)RESET;
}
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_wwdg.c | C | oos | 7,816 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_iwdg.c
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file provides all the IWDG firmware functions.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_iwdg.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ---------------------- IWDG registers bit mask ------------------------ */
/* KR register bit mask */
#define KR_Reload ((u16)0xAAAA)
#define KR_Enable ((u16)0xCCCC)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : IWDG_WriteAccessCmd
* Description : Enables or disables write access to IWDG_PR and IWDG_RLR
* registers.
* Input : - IWDG_WriteAccess: new state of write access to IWDG_PR and
* IWDG_RLR registers.
* This parameter can be one of the following values:
* - IWDG_WriteAccess_Enable: Enable write access to
* IWDG_PR and IWDG_RLR registers
* - IWDG_WriteAccess_Disable: Disable write access to
* IWDG_PR and IWDG_RLR registers
* Output : None
* Return : None
*******************************************************************************/
void IWDG_WriteAccessCmd(u16 IWDG_WriteAccess)
{
/* Check the parameters */
assert(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
IWDG->KR = IWDG_WriteAccess;
}
/*******************************************************************************
* Function Name : IWDG_SetPrescaler
* Description : Sets IWDG Prescaler value.
* Input : - IWDG_Prescaler: specifies the IWDG Prescaler value.
* This parameter can be one of the following values:
* - IWDG_Prescaler_4: IWDG prescaler set to 4
* - IWDG_Prescaler_8: IWDG prescaler set to 8
* - IWDG_Prescaler_16: IWDG prescaler set to 16
* - IWDG_Prescaler_32: IWDG prescaler set to 32
* - IWDG_Prescaler_64: IWDG prescaler set to 64
* - IWDG_Prescaler_128: IWDG prescaler set to 128
* - IWDG_Prescaler_256: IWDG prescaler set to 256
* Output : None
* Return : None
*******************************************************************************/
void IWDG_SetPrescaler(u8 IWDG_Prescaler)
{
/* Check the parameters */
assert(IS_IWDG_PRESCALER(IWDG_Prescaler));
IWDG->PR = IWDG_Prescaler;
}
/*******************************************************************************
* Function Name : IWDG_SetReload
* Description : Sets IWDG Reload value.
* Input : - Reload: specifies the IWDG Reload value.
* This parameter must be a number between 0 and 0x0FFF.
* Output : None
* Return : None
*******************************************************************************/
void IWDG_SetReload(u16 Reload)
{
/* Check the parameters */
assert(IS_IWDG_RELOAD(Reload));
IWDG->RLR = Reload;
}
/*******************************************************************************
* Function Name : IWDG_ReloadCounter
* Description : Reloads IWDG counter with value defined in the reload register
* (write access to IWDG_PR and IWDG_RLR registers disabled).
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void IWDG_ReloadCounter(void)
{
IWDG->KR = KR_Reload;
}
/*******************************************************************************
* Function Name : IWDG_Enable
* Description : Enables IWDG (write access to IWDG_PR and IWDG_RLR registers
* disabled).
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void IWDG_Enable(void)
{
IWDG->KR = KR_Enable;
}
/*******************************************************************************
* Function Name : IWDG_GetFlagStatus
* Description : Checks whether the specified IWDG flag is set or not.
* Input : - IWDG_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* - IWDG_FLAG_PVU: Prescaler Value Update on going
* - IWDG_FLAG_RVU: Reload Value Update on going
* Output : None
* Return : The new state of IWDG_FLAG (SET or RESET).
*******************************************************************************/
FlagStatus IWDG_GetFlagStatus(u16 IWDG_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert(IS_IWDG_FLAG(IWDG_FLAG));
if ((IWDG->SR & IWDG_FLAG) != (u32)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
/* Return the flag status */
return bitstatus;
}
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_iwdg.c | C | oos | 6,515 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_lib.c
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file provides all peripherals pointers initialization.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#define EXT
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_lib.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
#ifdef DEBUG
/*******************************************************************************
* Function Name : debug
* Description : This function initialize peripherals pointers.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void debug(void)
{
/************************************* ADC ************************************/
#ifdef _ADC1
ADC1 = (ADC_TypeDef *) ADC1_BASE;
#endif /*_ADC1 */
#ifdef _ADC2
ADC2 = (ADC_TypeDef *) ADC2_BASE;
#endif /*_ADC2 */
/************************************* BKP ************************************/
#ifdef _BKP
BKP = (BKP_TypeDef *) BKP_BASE;
#endif /*_BKP */
/************************************* CAN ************************************/
#ifdef _CAN
CAN = (CAN_TypeDef *) CAN_BASE;
#endif /*_CAN */
/************************************* DMA ************************************/
#ifdef _DMA
DMA = (DMA_TypeDef *) DMA_BASE;
#endif /*_DMA */
#ifdef _DMA_Channel1
DMA_Channel1 = (DMA_Channel_TypeDef *) DMA_Channel1_BASE;
#endif /*_DMA_Channel1 */
#ifdef _DMA_Channel2
DMA_Channel2 = (DMA_Channel_TypeDef *) DMA_Channel2_BASE;
#endif /*_DMA_Channel2 */
#ifdef _DMA_Channel3
DMA_Channel3 = (DMA_Channel_TypeDef *) DMA_Channel3_BASE;
#endif /*_DMA_Channel3 */
#ifdef _DMA_Channel4
DMA_Channel4 = (DMA_Channel_TypeDef *) DMA_Channel4_BASE;
#endif /*_DMA_Channel4 */
#ifdef _DMA_Channel5
DMA_Channel5 = (DMA_Channel_TypeDef *) DMA_Channel5_BASE;
#endif /*_DMA_Channel5 */
#ifdef _DMA_Channel6
DMA_Channel6 = (DMA_Channel_TypeDef *) DMA_Channel6_BASE;
#endif /*_DMA_Channel6 */
#ifdef _DMA_Channel7
DMA_Channel7 = (DMA_Channel_TypeDef *) DMA_Channel7_BASE;
#endif /*_DMA_Channel7 */
/************************************* EXTI ***********************************/
#ifdef _EXTI
EXTI = (EXTI_TypeDef *) EXTI_BASE;
#endif /*_EXTI */
/************************************* FLASH and Option Bytes *****************/
#ifdef _FLASH
FLASH = (FLASH_TypeDef *) FLASH_BASE;
OB = (OB_TypeDef *) OB_BASE;
#endif /*_FLASH */
/************************************* GPIO ***********************************/
#ifdef _GPIOA
GPIOA = (GPIO_TypeDef *) GPIOA_BASE;
#endif /*_GPIOA */
#ifdef _GPIOB
GPIOB = (GPIO_TypeDef *) GPIOB_BASE;
#endif /*_GPIOB */
#ifdef _GPIOC
GPIOC = (GPIO_TypeDef *) GPIOC_BASE;
#endif /*_GPIOC */
#ifdef _GPIOD
GPIOD = (GPIO_TypeDef *) GPIOD_BASE;
#endif /*_GPIOD */
#ifdef _GPIOE
GPIOE = (GPIO_TypeDef *) GPIOE_BASE;
#endif /*_GPIOE */
#ifdef _AFIO
AFIO = (AFIO_TypeDef *) AFIO_BASE;
#endif /*_AFIO */
/************************************* I2C ************************************/
#ifdef _I2C1
I2C1 = (I2C_TypeDef *) I2C1_BASE;
#endif /*_I2C1 */
#ifdef _I2C2
I2C2 = (I2C_TypeDef *) I2C2_BASE;
#endif /*_I2C2 */
/************************************* IWDG ***********************************/
#ifdef _IWDG
IWDG = (IWDG_TypeDef *) IWDG_BASE;
#endif /*_IWDG */
/************************************* NVIC ***********************************/
#ifdef _NVIC
NVIC = (NVIC_TypeDef *) NVIC_BASE;
#endif /*_NVIC */
#ifdef _SCB
SCB = (SCB_TypeDef *) SCB_BASE;
#endif /*_SCB */
/************************************* PWR ************************************/
#ifdef _PWR
PWR = (PWR_TypeDef *) PWR_BASE;
#endif /*_PWR */
/************************************* RCC ************************************/
#ifdef _RCC
RCC = (RCC_TypeDef *) RCC_BASE;
#endif /*_RCC */
/************************************* RTC ************************************/
#ifdef _RTC
RTC = (RTC_TypeDef *) RTC_BASE;
#endif /*_RTC */
/************************************* SPI ************************************/
#ifdef _SPI1
SPI1 = (SPI_TypeDef *) SPI1_BASE;
#endif /*_SPI1 */
#ifdef _SPI2
SPI2 = (SPI_TypeDef *) SPI2_BASE;
#endif /*_SPI2 */
/************************************* SysTick ********************************/
#ifdef _SysTick
SysTick = (SysTick_TypeDef *) SysTick_BASE;
#endif /*_SysTick */
/************************************* TIM1 ***********************************/
#ifdef _TIM1
TIM1 = (TIM1_TypeDef *) TIM1_BASE;
#endif /*_TIM1 */
/************************************* TIM ************************************/
#ifdef _TIM2
TIM2 = (TIM_TypeDef *) TIM2_BASE;
#endif /*_TIM2 */
#ifdef _TIM3
TIM3 = (TIM_TypeDef *) TIM3_BASE;
#endif /*_TIM3 */
#ifdef _TIM4
TIM4 = (TIM_TypeDef *) TIM4_BASE;
#endif /*_TIM4 */
/************************************* USART **********************************/
#ifdef _USART1
USART1 = (USART_TypeDef *) USART1_BASE;
#endif /*_USART1 */
#ifdef _USART2
USART2 = (USART_TypeDef *) USART2_BASE;
#endif /*_USART2 */
#ifdef _USART3
USART3 = (USART_TypeDef *) USART3_BASE;
#endif /*_USART3 */
/************************************* WWDG ***********************************/
#ifdef _WWDG
WWDG = (WWDG_TypeDef *) WWDG_BASE;
#endif /*_WWDG */
}
#endif
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_lib.c | C | oos | 6,921 |
//*****************************************************************************
//
// i2c.h - Prototypes for the I2C Driver.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __I2C_H__
#define __I2C_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Defines for the API.
//
//*****************************************************************************
//*****************************************************************************
//
// Interrupt defines.
//
//*****************************************************************************
#define I2C_INT_MASTER 0x00000001
#define I2C_INT_SLAVE 0x00000002
//*****************************************************************************
//
// I2C Master commands.
//
//*****************************************************************************
#define I2C_MASTER_CMD_SINGLE_SEND 0x00000007
#define I2C_MASTER_CMD_SINGLE_RECEIVE 0x00000007
#define I2C_MASTER_CMD_BURST_SEND_START 0x00000003
#define I2C_MASTER_CMD_BURST_SEND_CONT 0x00000001
#define I2C_MASTER_CMD_BURST_SEND_FINISH 0x00000005
#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP 0x00000004
#define I2C_MASTER_CMD_BURST_RECEIVE_START 0x0000000b
#define I2C_MASTER_CMD_BURST_RECEIVE_CONT 0x00000009
#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH 0x00000005
#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP 0x00000005
//*****************************************************************************
//
// I2C Master error status.
//
//*****************************************************************************
#define I2C_MASTER_ERR_NONE 0
#define I2C_MASTER_ERR_ADDR_ACK 0x00000004
#define I2C_MASTER_ERR_DATA_ACK 0x00000008
#define I2C_MASTER_ERR_ARB_LOST 0x00000010
//*****************************************************************************
//
// I2C Slave action requests
//
//*****************************************************************************
#define I2C_SLAVE_ACT_NONE 0
#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data
#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data
#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte
//*****************************************************************************
//
// Miscellaneous I2C driver definitions.
//
//*****************************************************************************
#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void));
extern void I2CIntUnregister(unsigned long ulBase);
extern tBoolean I2CMasterBusBusy(unsigned long ulBase);
extern tBoolean I2CMasterBusy(unsigned long ulBase);
extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd);
extern unsigned long I2CMasterDataGet(unsigned long ulBase);
extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData);
extern void I2CMasterDisable(unsigned long ulBase);
extern void I2CMasterEnable(unsigned long ulBase);
extern unsigned long I2CMasterErr(unsigned long ulBase);
extern void I2CMasterInitExpClk(unsigned long ulBase, unsigned long ulI2CClk,
tBoolean bFast);
extern void I2CMasterIntClear(unsigned long ulBase);
extern void I2CMasterIntDisable(unsigned long ulBase);
extern void I2CMasterIntEnable(unsigned long ulBase);
extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void I2CMasterSlaveAddrSet(unsigned long ulBase,
unsigned char ucSlaveAddr,
tBoolean bReceive);
extern unsigned long I2CSlaveDataGet(unsigned long ulBase);
extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData);
extern void I2CSlaveDisable(unsigned long ulBase);
extern void I2CSlaveEnable(unsigned long ulBase);
extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr);
extern void I2CSlaveIntClear(unsigned long ulBase);
extern void I2CSlaveIntDisable(unsigned long ulBase);
extern void I2CSlaveIntEnable(unsigned long ulBase);
extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked);
extern unsigned long I2CSlaveStatus(unsigned long ulBase);
//*****************************************************************************
//
// Several I2C APIs have been renamed, with the original function name being
// deprecated. These defines provide backward compatibility.
//
//*****************************************************************************
#ifndef DEPRECATED
#include "sysctl.h"
#define I2CMasterInit(a, b) \
I2CMasterInitExpClk(a, SysCtlClockGet(), b)
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __I2C_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/i2c.h | C | oos | 6,843 |
//*****************************************************************************
//
// rit128x96x4.h - Prototypes for the driver for the RITEK 128x96x4 graphical
// OLED display.
//
// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __RIT128X96X4_H__
#define __RIT128X96X4_H__
//*****************************************************************************
//
// Prototypes for the driver APIs.
//
//*****************************************************************************
extern void RIT128x96x4Clear(void);
extern void RIT128x96x4StringDraw(const char *pcStr,
unsigned long ulX,
unsigned long ulY,
unsigned char ucLevel);
extern void RIT128x96x4ImageDraw(const unsigned char *pucImage,
unsigned long ulX,
unsigned long ulY,
unsigned long ulWidth,
unsigned long ulHeight);
extern void RIT128x96x4Init(unsigned long ulFrequency);
extern void RIT128x96x4Enable(unsigned long ulFrequency);
extern void RIT128x96x4Disable(void);
extern void RIT128x96x4DisplayOn(void);
extern void RIT128x96x4DisplayOff(void);
#endif // __RIT128X96X4_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/rit128x96x4.h | C | oos | 2,429 |
//*****************************************************************************
//
// rom.h - Macros to facilitate calling functions in the ROM.
//
// Copyright (c) 2007-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __ROM_H__
#define __ROM_H__
//*****************************************************************************
//
// Pointers to the main API tables.
//
//*****************************************************************************
#define ROM_APITABLE ((unsigned long *)0x01000010)
#define ROM_VERSION (ROM_APITABLE[0])
#define ROM_UARTTABLE ((unsigned long *)(ROM_APITABLE[1]))
#define ROM_SSITABLE ((unsigned long *)(ROM_APITABLE[2]))
#define ROM_I2CTABLE ((unsigned long *)(ROM_APITABLE[3]))
#define ROM_GPIOTABLE ((unsigned long *)(ROM_APITABLE[4]))
#define ROM_ADCTABLE ((unsigned long *)(ROM_APITABLE[5]))
#define ROM_COMPARATORTABLE ((unsigned long *)(ROM_APITABLE[6]))
#define ROM_FLASHTABLE ((unsigned long *)(ROM_APITABLE[7]))
#define ROM_PWMTABLE ((unsigned long *)(ROM_APITABLE[8]))
#define ROM_QEITABLE ((unsigned long *)(ROM_APITABLE[9]))
#define ROM_SYSTICKTABLE ((unsigned long *)(ROM_APITABLE[10]))
#define ROM_TIMERTABLE ((unsigned long *)(ROM_APITABLE[11]))
#define ROM_WATCHDOGTABLE ((unsigned long *)(ROM_APITABLE[12]))
#define ROM_SYSCTLTABLE ((unsigned long *)(ROM_APITABLE[13]))
#define ROM_INTERRUPTTABLE ((unsigned long *)(ROM_APITABLE[14]))
//*****************************************************************************
//
// Macros for calling ROM functions in the ADC API.
//
//*****************************************************************************
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_ADCSequenceDataGet \
((long (*)(unsigned long ulBase, \
unsigned long ulSequenceNum, \
unsigned long *pulBuffer))ROM_ADCTABLE[0])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_ADCIntDisable \
((void (*)(unsigned long ulBase, \
unsigned long ulSequenceNum))ROM_ADCTABLE[1])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_ADCIntEnable \
((void (*)(unsigned long ulBase, \
unsigned long ulSequenceNum))ROM_ADCTABLE[2])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_ADCIntStatus \
((unsigned long (*)(unsigned long ulBase, \
unsigned long ulSequenceNum, \
tBoolean bMasked))ROM_ADCTABLE[3])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_ADCIntClear \
((void (*)(unsigned long ulBase, \
unsigned long ulSequenceNum))ROM_ADCTABLE[4])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_ADCSequenceEnable \
((void (*)(unsigned long ulBase, \
unsigned long ulSequenceNum))ROM_ADCTABLE[5])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_ADCSequenceDisable \
((void (*)(unsigned long ulBase, \
unsigned long ulSequenceNum))ROM_ADCTABLE[6])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_ADCSequenceConfigure \
((void (*)(unsigned long ulBase, \
unsigned long ulSequenceNum, \
unsigned long ulTrigger, \
unsigned long ulPriority))ROM_ADCTABLE[7])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_ADCSequenceStepConfigure \
((void (*)(unsigned long ulBase, \
unsigned long ulSequenceNum, \
unsigned long ulStep, \
unsigned long ulConfig))ROM_ADCTABLE[8])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_ADCSequenceOverflow \
((long (*)(unsigned long ulBase, \
unsigned long ulSequenceNum))ROM_ADCTABLE[9])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_ADCSequenceOverflowClear \
((void (*)(unsigned long ulBase, \
unsigned long ulSequenceNum))ROM_ADCTABLE[10])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_ADCSequenceUnderflow \
((long (*)(unsigned long ulBase, \
unsigned long ulSequenceNum))ROM_ADCTABLE[11])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_ADCSequenceUnderflowClear \
((void (*)(unsigned long ulBase, \
unsigned long ulSequenceNum))ROM_ADCTABLE[12])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_ADCProcessorTrigger \
((void (*)(unsigned long ulBase, \
unsigned long ulSequenceNum))ROM_ADCTABLE[13])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_ADCHardwareOversampleConfigure \
((void (*)(unsigned long ulBase, \
unsigned long ulFactor))ROM_ADCTABLE[14])
#endif
//*****************************************************************************
//
// Macros for calling ROM functions in the Comparator API.
//
//*****************************************************************************
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_ComparatorIntClear \
((void (*)(unsigned long ulBase, \
unsigned long ulComp))ROM_COMPARATORTABLE[0])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_ComparatorConfigure \
((void (*)(unsigned long ulBase, \
unsigned long ulComp, \
unsigned long ulConfig))ROM_COMPARATORTABLE[1])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_ComparatorRefSet \
((void (*)(unsigned long ulBase, \
unsigned long ulRef))ROM_COMPARATORTABLE[2])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_ComparatorValueGet \
((tBoolean (*)(unsigned long ulBase, \
unsigned long ulComp))ROM_COMPARATORTABLE[3])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_ComparatorIntEnable \
((void (*)(unsigned long ulBase, \
unsigned long ulComp))ROM_COMPARATORTABLE[4])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_ComparatorIntDisable \
((void (*)(unsigned long ulBase, \
unsigned long ulComp))ROM_COMPARATORTABLE[5])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_ComparatorIntStatus \
((tBoolean (*)(unsigned long ulBase, \
unsigned long ulComp, \
tBoolean bMasked))ROM_COMPARATORTABLE[6])
#endif
//*****************************************************************************
//
// Macros for calling ROM functions in the Flash API.
//
//*****************************************************************************
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_FlashProgram \
((long (*)(unsigned long *pulData, \
unsigned long ulAddress, \
unsigned long ulCount))ROM_FLASHTABLE[0])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_FlashUsecGet \
((unsigned long (*)(void))ROM_FLASHTABLE[1])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_FlashUsecSet \
((void (*)(unsigned long ulClocks))ROM_FLASHTABLE[2])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_FlashErase \
((long (*)(unsigned long ulAddress))ROM_FLASHTABLE[3])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_FlashProtectGet \
((tFlashProtection (*)(unsigned long ulAddress))ROM_FLASHTABLE[4])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_FlashProtectSet \
((long (*)(unsigned long ulAddress, \
tFlashProtection eProtect))ROM_FLASHTABLE[5])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_FlashProtectSave \
((long (*)(void))ROM_FLASHTABLE[6])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_FlashUserGet \
((long (*)(unsigned long *pulUser0, \
unsigned long *pulUser1))ROM_FLASHTABLE[7])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_FlashUserSet \
((long (*)(unsigned long ulUser0, \
unsigned long ulUser1))ROM_FLASHTABLE[8])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_FlashUserSave \
((long (*)(void))ROM_FLASHTABLE[9])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_FlashIntEnable \
((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[10])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_FlashIntDisable \
((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[11])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_FlashIntGetStatus \
((unsigned long (*)(tBoolean bMasked))ROM_FLASHTABLE[12])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_FlashIntClear \
((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[13])
#endif
//*****************************************************************************
//
// Macros for calling ROM functions in the GPIO API.
//
//*****************************************************************************
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_GPIOPinWrite \
((void (*)(unsigned long ulPort, \
unsigned char ucPins, \
unsigned char ucVal))ROM_GPIOTABLE[0])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_GPIODirModeSet \
((void (*)(unsigned long ulPort, \
unsigned char ucPins, \
unsigned long ulPinIO))ROM_GPIOTABLE[1])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_GPIODirModeGet \
((unsigned long (*)(unsigned long ulPort, \
unsigned char ucPin))ROM_GPIOTABLE[2])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_GPIOIntTypeSet \
((void (*)(unsigned long ulPort, \
unsigned char ucPins, \
unsigned long ulIntType))ROM_GPIOTABLE[3])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_GPIOIntTypeGet \
((unsigned long (*)(unsigned long ulPort, \
unsigned char ucPin))ROM_GPIOTABLE[4])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_GPIOPadConfigSet \
((void (*)(unsigned long ulPort, \
unsigned char ucPins, \
unsigned long ulStrength, \
unsigned long ulPadType))ROM_GPIOTABLE[5])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_GPIOPadConfigGet \
((void (*)(unsigned long ulPort, \
unsigned char ucPin, \
unsigned long *pulStrength, \
unsigned long *pulPadType))ROM_GPIOTABLE[6])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_GPIOPinIntEnable \
((void (*)(unsigned long ulPort, \
unsigned char ucPins))ROM_GPIOTABLE[7])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_GPIOPinIntDisable \
((void (*)(unsigned long ulPort, \
unsigned char ucPins))ROM_GPIOTABLE[8])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_GPIOPinIntStatus \
((long (*)(unsigned long ulPort, \
tBoolean bMasked))ROM_GPIOTABLE[9])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_GPIOPinIntClear \
((void (*)(unsigned long ulPort, \
unsigned char ucPins))ROM_GPIOTABLE[10])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_GPIOPinRead \
((long (*)(unsigned long ulPort, \
unsigned char ucPins))ROM_GPIOTABLE[11])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_GPIOPinTypeCAN \
((void (*)(unsigned long ulPort, \
unsigned char ucPins))ROM_GPIOTABLE[12])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_GPIOPinTypeComparator \
((void (*)(unsigned long ulPort, \
unsigned char ucPins))ROM_GPIOTABLE[13])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_GPIOPinTypeGPIOInput \
((void (*)(unsigned long ulPort, \
unsigned char ucPins))ROM_GPIOTABLE[14])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_GPIOPinTypeGPIOOutput \
((void (*)(unsigned long ulPort, \
unsigned char ucPins))ROM_GPIOTABLE[15])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_GPIOPinTypeI2C \
((void (*)(unsigned long ulPort, \
unsigned char ucPins))ROM_GPIOTABLE[16])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_GPIOPinTypePWM \
((void (*)(unsigned long ulPort, \
unsigned char ucPins))ROM_GPIOTABLE[17])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_GPIOPinTypeQEI \
((void (*)(unsigned long ulPort, \
unsigned char ucPins))ROM_GPIOTABLE[18])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_GPIOPinTypeSSI \
((void (*)(unsigned long ulPort, \
unsigned char ucPins))ROM_GPIOTABLE[19])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_GPIOPinTypeTimer \
((void (*)(unsigned long ulPort, \
unsigned char ucPins))ROM_GPIOTABLE[20])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_GPIOPinTypeUART \
((void (*)(unsigned long ulPort, \
unsigned char ucPins))ROM_GPIOTABLE[21])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_GPIOPinTypeGPIOOutputOD \
((void (*)(unsigned long ulPort, \
unsigned char ucPins))ROM_GPIOTABLE[22])
#endif
//*****************************************************************************
//
// Macros for calling ROM functions in the I2C API.
//
//*****************************************************************************
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_I2CMasterDataPut \
((void (*)(unsigned long ulBase, \
unsigned char ucData))ROM_I2CTABLE[0])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_I2CMasterInitExpClk \
((void (*)(unsigned long ulBase, \
unsigned long ulI2CClk, \
tBoolean bFast))ROM_I2CTABLE[1])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_I2CSlaveInit \
((void (*)(unsigned long ulBase, \
unsigned char ucSlaveAddr))ROM_I2CTABLE[2])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_I2CMasterEnable \
((void (*)(unsigned long ulBase))ROM_I2CTABLE[3])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_I2CSlaveEnable \
((void (*)(unsigned long ulBase))ROM_I2CTABLE[4])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_I2CMasterDisable \
((void (*)(unsigned long ulBase))ROM_I2CTABLE[5])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_I2CSlaveDisable \
((void (*)(unsigned long ulBase))ROM_I2CTABLE[6])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_I2CMasterIntEnable \
((void (*)(unsigned long ulBase))ROM_I2CTABLE[7])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_I2CSlaveIntEnable \
((void (*)(unsigned long ulBase))ROM_I2CTABLE[8])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_I2CMasterIntDisable \
((void (*)(unsigned long ulBase))ROM_I2CTABLE[9])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_I2CSlaveIntDisable \
((void (*)(unsigned long ulBase))ROM_I2CTABLE[10])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_I2CMasterIntStatus \
((tBoolean (*)(unsigned long ulBase, \
tBoolean bMasked))ROM_I2CTABLE[11])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_I2CSlaveIntStatus \
((tBoolean (*)(unsigned long ulBase, \
tBoolean bMasked))ROM_I2CTABLE[12])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_I2CMasterIntClear \
((void (*)(unsigned long ulBase))ROM_I2CTABLE[13])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_I2CSlaveIntClear \
((void (*)(unsigned long ulBase))ROM_I2CTABLE[14])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_I2CMasterSlaveAddrSet \
((void (*)(unsigned long ulBase, \
unsigned char ucSlaveAddr, \
tBoolean bReceive))ROM_I2CTABLE[15])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_I2CMasterBusy \
((tBoolean (*)(unsigned long ulBase))ROM_I2CTABLE[16])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_I2CMasterBusBusy \
((tBoolean (*)(unsigned long ulBase))ROM_I2CTABLE[17])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_I2CMasterControl \
((void (*)(unsigned long ulBase, \
unsigned long ulCmd))ROM_I2CTABLE[18])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_I2CMasterErr \
((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[19])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_I2CMasterDataGet \
((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[20])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_I2CSlaveStatus \
((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[21])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_I2CSlaveDataPut \
((void (*)(unsigned long ulBase, \
unsigned char ucData))ROM_I2CTABLE[22])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_I2CSlaveDataGet \
((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[23])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_UpdateI2C \
((void (*)(void))ROM_I2CTABLE[24])
#endif
//*****************************************************************************
//
// Macros for calling ROM functions in the Interrupt API.
//
//*****************************************************************************
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_IntEnable \
((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[0])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_IntDisable \
((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[3])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_IntPriorityGroupingSet \
((void (*)(unsigned long ulBits))ROM_INTERRUPTTABLE[4])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_IntPriorityGroupingGet \
((unsigned long (*)(void))ROM_INTERRUPTTABLE[5])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_IntPrioritySet \
((void (*)(unsigned long ulInterrupt, \
unsigned char ucPriority))ROM_INTERRUPTTABLE[6])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_IntPriorityGet \
((long (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[7])
#endif
//*****************************************************************************
//
// Macros for calling ROM functions in the PWM API.
//
//*****************************************************************************
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_PWMPulseWidthSet \
((void (*)(unsigned long ulBase, \
unsigned long ulPWMOut, \
unsigned long ulWidth))ROM_PWMTABLE[0])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_PWMGenConfigure \
((void (*)(unsigned long ulBase, \
unsigned long ulGen, \
unsigned long ulConfig))ROM_PWMTABLE[1])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_PWMGenPeriodSet \
((void (*)(unsigned long ulBase, \
unsigned long ulGen, \
unsigned long ulPeriod))ROM_PWMTABLE[2])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_PWMGenPeriodGet \
((unsigned long (*)(unsigned long ulBase, \
unsigned long ulGen))ROM_PWMTABLE[3])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_PWMGenEnable \
((void (*)(unsigned long ulBase, \
unsigned long ulGen))ROM_PWMTABLE[4])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_PWMGenDisable \
((void (*)(unsigned long ulBase, \
unsigned long ulGen))ROM_PWMTABLE[5])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_PWMPulseWidthGet \
((unsigned long (*)(unsigned long ulBase, \
unsigned long ulPWMOut))ROM_PWMTABLE[6])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_PWMDeadBandEnable \
((void (*)(unsigned long ulBase, \
unsigned long ulGen, \
unsigned short usRise, \
unsigned short usFall))ROM_PWMTABLE[7])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_PWMDeadBandDisable \
((void (*)(unsigned long ulBase, \
unsigned long ulGen))ROM_PWMTABLE[8])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_PWMSyncUpdate \
((void (*)(unsigned long ulBase, \
unsigned long ulGenBits))ROM_PWMTABLE[9])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_PWMSyncTimeBase \
((void (*)(unsigned long ulBase, \
unsigned long ulGenBits))ROM_PWMTABLE[10])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_PWMOutputState \
((void (*)(unsigned long ulBase, \
unsigned long ulPWMOutBits, \
tBoolean bEnable))ROM_PWMTABLE[11])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_PWMOutputInvert \
((void (*)(unsigned long ulBase, \
unsigned long ulPWMOutBits, \
tBoolean bInvert))ROM_PWMTABLE[12])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_PWMOutputFault \
((void (*)(unsigned long ulBase, \
unsigned long ulPWMOutBits, \
tBoolean bFaultSuppress))ROM_PWMTABLE[13])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_PWMGenIntTrigEnable \
((void (*)(unsigned long ulBase, \
unsigned long ulGen, \
unsigned long ulIntTrig))ROM_PWMTABLE[14])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_PWMGenIntTrigDisable \
((void (*)(unsigned long ulBase, \
unsigned long ulGen, \
unsigned long ulIntTrig))ROM_PWMTABLE[15])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_PWMGenIntStatus \
((unsigned long (*)(unsigned long ulBase, \
unsigned long ulGen, \
tBoolean bMasked))ROM_PWMTABLE[16])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_PWMGenIntClear \
((void (*)(unsigned long ulBase, \
unsigned long ulGen, \
unsigned long ulInts))ROM_PWMTABLE[17])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_PWMIntEnable \
((void (*)(unsigned long ulBase, \
unsigned long ulGenFault))ROM_PWMTABLE[18])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_PWMIntDisable \
((void (*)(unsigned long ulBase, \
unsigned long ulGenFault))ROM_PWMTABLE[19])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_PWMFaultIntClear \
((void (*)(unsigned long ulBase))ROM_PWMTABLE[20])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_PWMIntStatus \
((unsigned long (*)(unsigned long ulBase, \
tBoolean bMasked))ROM_PWMTABLE[21])
#endif
//*****************************************************************************
//
// Macros for calling ROM functions in the QEI API.
//
//*****************************************************************************
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_QEIPositionGet \
((unsigned long (*)(unsigned long ulBase))ROM_QEITABLE[0])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_QEIEnable \
((void (*)(unsigned long ulBase))ROM_QEITABLE[1])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_QEIDisable \
((void (*)(unsigned long ulBase))ROM_QEITABLE[2])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_QEIConfigure \
((void (*)(unsigned long ulBase, \
unsigned long ulConfig, \
unsigned long ulMaxPosition))ROM_QEITABLE[3])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_QEIPositionSet \
((void (*)(unsigned long ulBase, \
unsigned long ulPosition))ROM_QEITABLE[4])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_QEIDirectionGet \
((long (*)(unsigned long ulBase))ROM_QEITABLE[5])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_QEIErrorGet \
((tBoolean (*)(unsigned long ulBase))ROM_QEITABLE[6])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_QEIVelocityEnable \
((void (*)(unsigned long ulBase))ROM_QEITABLE[7])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_QEIVelocityDisable \
((void (*)(unsigned long ulBase))ROM_QEITABLE[8])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_QEIVelocityConfigure \
((void (*)(unsigned long ulBase, \
unsigned long ulPreDiv, \
unsigned long ulPeriod))ROM_QEITABLE[9])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_QEIVelocityGet \
((unsigned long (*)(unsigned long ulBase))ROM_QEITABLE[10])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_QEIIntEnable \
((void (*)(unsigned long ulBase, \
unsigned long ulIntFlags))ROM_QEITABLE[11])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_QEIIntDisable \
((void (*)(unsigned long ulBase, \
unsigned long ulIntFlags))ROM_QEITABLE[12])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_QEIIntStatus \
((unsigned long (*)(unsigned long ulBase, \
tBoolean bMasked))ROM_QEITABLE[13])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_QEIIntClear \
((void (*)(unsigned long ulBase, \
unsigned long ulIntFlags))ROM_QEITABLE[14])
#endif
//*****************************************************************************
//
// Macros for calling ROM functions in the SSI API.
//
//*****************************************************************************
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SSIDataPut \
((void (*)(unsigned long ulBase, \
unsigned long ulData))ROM_SSITABLE[0])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SSIConfigSetExpClk \
((void (*)(unsigned long ulBase, \
unsigned long ulSSIClk, \
unsigned long ulProtocol, \
unsigned long ulMode, \
unsigned long ulBitRate, \
unsigned long ulDataWidth))ROM_SSITABLE[1])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SSIEnable \
((void (*)(unsigned long ulBase))ROM_SSITABLE[2])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SSIDisable \
((void (*)(unsigned long ulBase))ROM_SSITABLE[3])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SSIIntEnable \
((void (*)(unsigned long ulBase, \
unsigned long ulIntFlags))ROM_SSITABLE[4])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SSIIntDisable \
((void (*)(unsigned long ulBase, \
unsigned long ulIntFlags))ROM_SSITABLE[5])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SSIIntStatus \
((unsigned long (*)(unsigned long ulBase, \
tBoolean bMasked))ROM_SSITABLE[6])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SSIIntClear \
((void (*)(unsigned long ulBase, \
unsigned long ulIntFlags))ROM_SSITABLE[7])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SSIDataPutNonBlocking \
((long (*)(unsigned long ulBase, \
unsigned long ulData))ROM_SSITABLE[8])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SSIDataGet \
((void (*)(unsigned long ulBase, \
unsigned long *pulData))ROM_SSITABLE[9])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SSIDataGetNonBlocking \
((long (*)(unsigned long ulBase, \
unsigned long *pulData))ROM_SSITABLE[10])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_UpdateSSI \
((void (*)(void))ROM_SSITABLE[11])
#endif
//*****************************************************************************
//
// Macros for calling ROM functions in the SysCtl API.
//
//*****************************************************************************
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysCtlSleep \
((void (*)(void))ROM_SYSCTLTABLE[0])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysCtlSRAMSizeGet \
((unsigned long (*)(void))ROM_SYSCTLTABLE[1])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysCtlFlashSizeGet \
((unsigned long (*)(void))ROM_SYSCTLTABLE[2])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysCtlPinPresent \
((tBoolean (*)(unsigned long ulPin))ROM_SYSCTLTABLE[3])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysCtlPeripheralPresent \
((tBoolean (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[4])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysCtlPeripheralReset \
((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[5])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysCtlPeripheralEnable \
((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[6])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysCtlPeripheralDisable \
((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[7])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysCtlPeripheralSleepEnable \
((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[8])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysCtlPeripheralSleepDisable \
((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[9])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysCtlPeripheralDeepSleepEnable \
((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[10])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysCtlPeripheralDeepSleepDisable \
((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[11])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysCtlPeripheralClockGating \
((void (*)(tBoolean bEnable))ROM_SYSCTLTABLE[12])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysCtlIntEnable \
((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[13])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysCtlIntDisable \
((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[14])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysCtlIntClear \
((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[15])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysCtlIntStatus \
((unsigned long (*)(tBoolean bMasked))ROM_SYSCTLTABLE[16])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysCtlLDOSet \
((void (*)(unsigned long ulVoltage))ROM_SYSCTLTABLE[17])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysCtlLDOGet \
((unsigned long (*)(void))ROM_SYSCTLTABLE[18])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysCtlReset \
((void (*)(void))ROM_SYSCTLTABLE[19])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysCtlDeepSleep \
((void (*)(void))ROM_SYSCTLTABLE[20])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysCtlResetCauseGet \
((unsigned long (*)(void))ROM_SYSCTLTABLE[21])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysCtlResetCauseClear \
((void (*)(unsigned long ulCauses))ROM_SYSCTLTABLE[22])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysCtlClockSet \
((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[23])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysCtlClockGet \
((unsigned long (*)(void))ROM_SYSCTLTABLE[24])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysCtlPWMClockSet \
((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[25])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysCtlPWMClockGet \
((unsigned long (*)(void))ROM_SYSCTLTABLE[26])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysCtlADCSpeedSet \
((void (*)(unsigned long ulSpeed))ROM_SYSCTLTABLE[27])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysCtlADCSpeedGet \
((unsigned long (*)(void))ROM_SYSCTLTABLE[28])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysCtlGPIOAHBEnable \
((void (*)(unsigned long ulGPIOPeripheral))ROM_SYSCTLTABLE[29])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysCtlGPIOAHBDisable \
((void (*)(unsigned long ulGPIOPeripheral))ROM_SYSCTLTABLE[30])
#endif
//*****************************************************************************
//
// Macros for calling ROM functions in the SysTick API.
//
//*****************************************************************************
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysTickValueGet \
((unsigned long (*)(void))ROM_SYSTICKTABLE[0])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysTickEnable \
((void (*)(void))ROM_SYSTICKTABLE[1])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysTickDisable \
((void (*)(void))ROM_SYSTICKTABLE[2])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysTickIntEnable \
((void (*)(void))ROM_SYSTICKTABLE[3])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysTickIntDisable \
((void (*)(void))ROM_SYSTICKTABLE[4])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysTickPeriodSet \
((void (*)(unsigned long ulPeriod))ROM_SYSTICKTABLE[5])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_SysTickPeriodGet \
((unsigned long (*)(void))ROM_SYSTICKTABLE[6])
#endif
//*****************************************************************************
//
// Macros for calling ROM functions in the Timer API.
//
//*****************************************************************************
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_TimerIntClear \
((void (*)(unsigned long ulBase, \
unsigned long ulIntFlags))ROM_TIMERTABLE[0])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_TimerEnable \
((void (*)(unsigned long ulBase, \
unsigned long ulTimer))ROM_TIMERTABLE[1])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_TimerDisable \
((void (*)(unsigned long ulBase, \
unsigned long ulTimer))ROM_TIMERTABLE[2])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_TimerConfigure \
((void (*)(unsigned long ulBase, \
unsigned long ulConfig))ROM_TIMERTABLE[3])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_TimerControlLevel \
((void (*)(unsigned long ulBase, \
unsigned long ulTimer, \
tBoolean bInvert))ROM_TIMERTABLE[4])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_TimerControlTrigger \
((void (*)(unsigned long ulBase, \
unsigned long ulTimer, \
tBoolean bEnable))ROM_TIMERTABLE[5])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_TimerControlEvent \
((void (*)(unsigned long ulBase, \
unsigned long ulTimer, \
unsigned long ulEvent))ROM_TIMERTABLE[6])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_TimerControlStall \
((void (*)(unsigned long ulBase, \
unsigned long ulTimer, \
tBoolean bStall))ROM_TIMERTABLE[7])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_TimerRTCEnable \
((void (*)(unsigned long ulBase))ROM_TIMERTABLE[8])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_TimerRTCDisable \
((void (*)(unsigned long ulBase))ROM_TIMERTABLE[9])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_TimerPrescaleSet \
((void (*)(unsigned long ulBase, \
unsigned long ulTimer, \
unsigned long ulValue))ROM_TIMERTABLE[10])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_TimerPrescaleGet \
((unsigned long (*)(unsigned long ulBase, \
unsigned long ulTimer))ROM_TIMERTABLE[11])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_TimerLoadSet \
((void (*)(unsigned long ulBase, \
unsigned long ulTimer, \
unsigned long ulValue))ROM_TIMERTABLE[14])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_TimerLoadGet \
((unsigned long (*)(unsigned long ulBase, \
unsigned long ulTimer))ROM_TIMERTABLE[15])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_TimerValueGet \
((unsigned long (*)(unsigned long ulBase, \
unsigned long ulTimer))ROM_TIMERTABLE[16])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_TimerMatchSet \
((void (*)(unsigned long ulBase, \
unsigned long ulTimer, \
unsigned long ulValue))ROM_TIMERTABLE[17])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_TimerMatchGet \
((unsigned long (*)(unsigned long ulBase, \
unsigned long ulTimer))ROM_TIMERTABLE[18])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_TimerIntEnable \
((void (*)(unsigned long ulBase, \
unsigned long ulIntFlags))ROM_TIMERTABLE[19])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_TimerIntDisable \
((void (*)(unsigned long ulBase, \
unsigned long ulIntFlags))ROM_TIMERTABLE[20])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_TimerIntStatus \
((unsigned long (*)(unsigned long ulBase, \
tBoolean bMasked))ROM_TIMERTABLE[21])
#endif
//*****************************************************************************
//
// Macros for calling ROM functions in the UART API.
//
//*****************************************************************************
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_UARTCharPut \
((void (*)(unsigned long ulBase, \
unsigned char ucData))ROM_UARTTABLE[0])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_UARTParityModeSet \
((void (*)(unsigned long ulBase, \
unsigned long ulParity))ROM_UARTTABLE[1])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_UARTParityModeGet \
((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[2])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_UARTFIFOLevelSet \
((void (*)(unsigned long ulBase, \
unsigned long ulTxLevel, \
unsigned long ulRxLevel))ROM_UARTTABLE[3])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_UARTFIFOLevelGet \
((void (*)(unsigned long ulBase, \
unsigned long *pulTxLevel, \
unsigned long *pulRxLevel))ROM_UARTTABLE[4])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_UARTConfigSetExpClk \
((void (*)(unsigned long ulBase, \
unsigned long ulUARTClk, \
unsigned long ulBaud, \
unsigned long ulConfig))ROM_UARTTABLE[5])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_UARTConfigGetExpClk \
((void (*)(unsigned long ulBase, \
unsigned long ulUARTClk, \
unsigned long *pulBaud, \
unsigned long *pulConfig))ROM_UARTTABLE[6])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_UARTEnable \
((void (*)(unsigned long ulBase))ROM_UARTTABLE[7])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_UARTDisable \
((void (*)(unsigned long ulBase))ROM_UARTTABLE[8])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_UARTEnableSIR \
((void (*)(unsigned long ulBase, \
tBoolean bLowPower))ROM_UARTTABLE[9])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_UARTDisableSIR \
((void (*)(unsigned long ulBase))ROM_UARTTABLE[10])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_UARTCharsAvail \
((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[11])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_UARTSpaceAvail \
((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[12])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_UARTCharGetNonBlocking \
((long (*)(unsigned long ulBase))ROM_UARTTABLE[13])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_UARTCharGet \
((long (*)(unsigned long ulBase))ROM_UARTTABLE[14])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_UARTCharPutNonBlocking \
((tBoolean (*)(unsigned long ulBase, \
unsigned char ucData))ROM_UARTTABLE[15])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_UARTBreakCtl \
((void (*)(unsigned long ulBase, \
tBoolean bBreakState))ROM_UARTTABLE[16])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_UARTIntEnable \
((void (*)(unsigned long ulBase, \
unsigned long ulIntFlags))ROM_UARTTABLE[17])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_UARTIntDisable \
((void (*)(unsigned long ulBase, \
unsigned long ulIntFlags))ROM_UARTTABLE[18])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_UARTIntStatus \
((unsigned long (*)(unsigned long ulBase, \
tBoolean bMasked))ROM_UARTTABLE[19])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_UARTIntClear \
((void (*)(unsigned long ulBase, \
unsigned long ulIntFlags))ROM_UARTTABLE[20])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_UpdateUART \
((void (*)(void))ROM_UARTTABLE[21])
#endif
//*****************************************************************************
//
// Macros for calling ROM functions in the Watchdog API.
//
//*****************************************************************************
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_WatchdogIntClear \
((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[0])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_WatchdogRunning \
((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[1])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_WatchdogEnable \
((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[2])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_WatchdogResetEnable \
((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[3])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_WatchdogResetDisable \
((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[4])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_WatchdogLock \
((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[5])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_WatchdogUnlock \
((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[6])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_WatchdogLockState \
((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[7])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_WatchdogReloadSet \
((void (*)(unsigned long ulBase, \
unsigned long ulLoadVal))ROM_WATCHDOGTABLE[8])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_WatchdogReloadGet \
((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[9])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_WatchdogValueGet \
((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[10])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_WatchdogIntEnable \
((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[11])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_WatchdogIntStatus \
((unsigned long (*)(unsigned long ulBase, \
tBoolean bMasked))ROM_WATCHDOGTABLE[12])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_WatchdogStallEnable \
((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[13])
#endif
#if defined(TARGET_IS_DUSTDEVIL_RA0)
#define ROM_WatchdogStallDisable \
((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[14])
#endif
#endif // __ROM_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/rom.h | C | oos | 64,611 |
//*****************************************************************************
//
// ethernet.h - Defines and Macros for the ethernet module.
//
// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __ETHERNET_H__
#define __ETHERNET_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to EthernetConfigSet as the ulConfig value, and
// returned from EthernetConfigGet.
//
//*****************************************************************************
#define ETH_CFG_TS_TSEN 0x010000 // Enable Timestamp (CCP)
#define ETH_CFG_RX_BADCRCDIS 0x000800 // Disable RX BAD CRC Packets
#define ETH_CFG_RX_PRMSEN 0x000400 // Enable RX Promiscuous
#define ETH_CFG_RX_AMULEN 0x000200 // Enable RX Multicast
#define ETH_CFG_TX_DPLXEN 0x000010 // Enable TX Duplex Mode
#define ETH_CFG_TX_CRCEN 0x000004 // Enable TX CRC Generation
#define ETH_CFG_TX_PADEN 0x000002 // Enable TX Padding
//*****************************************************************************
//
// Values that can be passed to EthernetIntEnable, EthernetIntDisable, and
// EthernetIntClear as the ulIntFlags parameter, and returned from
// EthernetIntStatus.
//
//*****************************************************************************
#define ETH_INT_PHY 0x040 // PHY Event/Interrupt
#define ETH_INT_MDIO 0x020 // Management Transaction
#define ETH_INT_RXER 0x010 // RX Error
#define ETH_INT_RXOF 0x008 // RX FIFO Overrun
#define ETH_INT_TX 0x004 // TX Complete
#define ETH_INT_TXER 0x002 // TX Error
#define ETH_INT_RX 0x001 // RX Complete
//*****************************************************************************
//
// Helper Macros for Ethernet Processing
//
//*****************************************************************************
//
// htonl/ntohl - big endian/little endian byte swapping macros for
// 32-bit (long) values
//
//*****************************************************************************
#ifndef htonl
#define htonl(a) \
((((a) >> 24) & 0x000000ff) | \
(((a) >> 8) & 0x0000ff00) | \
(((a) << 8) & 0x00ff0000) | \
(((a) << 24) & 0xff000000))
#endif
#ifndef ntohl
#define ntohl(a) htonl((a))
#endif
//*****************************************************************************
//
// htons/ntohs - big endian/little endian byte swapping macros for
// 16-bit (short) values
//
//*****************************************************************************
#ifndef htons
#define htons(a) \
((((a) >> 8) & 0x00ff) | \
(((a) << 8) & 0xff00))
#endif
#ifndef ntohs
#define ntohs(a) htons((a))
#endif
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void EthernetInitExpClk(unsigned long ulBase, unsigned long ulEthClk);
extern void EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig);
extern unsigned long EthernetConfigGet(unsigned long ulBase);
extern void EthernetMACAddrSet(unsigned long ulBase,
unsigned char *pucMACAddr);
extern void EthernetMACAddrGet(unsigned long ulBase,
unsigned char *pucMACAddr);
extern void EthernetEnable(unsigned long ulBase);
extern void EthernetDisable(unsigned long ulBase);
extern tBoolean EthernetPacketAvail(unsigned long ulBase);
extern tBoolean EthernetSpaceAvail(unsigned long ulBase);
extern long EthernetPacketGetNonBlocking(unsigned long ulBase,
unsigned char *pucBuf,
long lBufLen);
extern long EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf,
long lBufLen);
extern long EthernetPacketPutNonBlocking(unsigned long ulBase,
unsigned char *pucBuf,
long lBufLen);
extern long EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf,
long lBufLen);
extern void EthernetIntRegister(unsigned long ulBase,
void (*pfnHandler)(void));
extern void EthernetIntUnregister(unsigned long ulBase);
extern void EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long EthernetIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr,
unsigned long ulData);
extern unsigned long EthernetPHYRead(unsigned long ulBase,
unsigned char ucRegAddr);
//*****************************************************************************
//
// Several Ethernet APIs have been renamed, with the original function name
// being deprecated. These defines provide backward compatibility.
//
//*****************************************************************************
#ifndef DEPRECATED
#include "sysctl.h"
#define EthernetInit(a) \
EthernetInitExpClk(a, SysCtlClockGet())
#define EthernetPacketNonBlockingGet(a, b, c) \
EthernetPacketGetNonBlocking(a, b, c)
#define EthernetPacketNonBlockingPut(a, b, c) \
EthernetPacketPutNonBlocking(a, b, c)
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __ETHERNET_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/ethernet.h | C | oos | 7,657 |
//*****************************************************************************
//
// hw_udma.h - Macros for use in accessing the UDMA registers.
//
// Copyright (c) 2007-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_UDMA_H__
#define __HW_UDMA_H__
//*****************************************************************************
//
// The following are defines for the Micro Direct Memory Access (uDMA) offsets.
//
//*****************************************************************************
#define UDMA_STAT 0x400FF000 // DMA Status
#define UDMA_CFG 0x400FF004 // DMA Configuration
#define UDMA_CTLBASE 0x400FF008 // DMA Channel Control Base Pointer
#define UDMA_ALTBASE 0x400FF00C // DMA Alternate Channel Control
// Base Pointer
#define UDMA_WAITSTAT 0x400FF010 // DMA Channel Wait on Request
// Status
#define UDMA_SWREQ 0x400FF014 // DMA Channel Software Request
#define UDMA_USEBURSTSET 0x400FF018 // DMA Channel Useburst Set
#define UDMA_USEBURSTCLR 0x400FF01C // DMA Channel Useburst Clear
#define UDMA_REQMASKSET 0x400FF020 // DMA Channel Request Mask Set
#define UDMA_REQMASKCLR 0x400FF024 // DMA Channel Request Mask Clear
#define UDMA_ENASET 0x400FF028 // DMA Channel Enable Set
#define UDMA_ENACLR 0x400FF02C // DMA Channel Enable Clear
#define UDMA_ALTSET 0x400FF030 // DMA Channel Primary Alternate
// Set
#define UDMA_ALTCLR 0x400FF034 // DMA Channel Primary Alternate
// Clear
#define UDMA_PRIOSET 0x400FF038 // DMA Channel Priority Set
#define UDMA_PRIOCLR 0x400FF03C // DMA Channel Priority Clear
#define UDMA_ERRCLR 0x400FF04C // DMA Bus Error Clear
//*****************************************************************************
//
// Micro Direct Memory Access (uDMA) offsets.
//
//*****************************************************************************
#define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End
// Pointer
#define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address
// End Pointer
#define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_SRCENDP register.
//
//*****************************************************************************
#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer.
#define UDMA_SRCENDP_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_STAT register.
//
//*****************************************************************************
#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available DMA Channels Minus 1.
#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine State.
#define UDMA_STAT_STATE_IDLE 0x00000000 // Idle
#define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data
#define UDMA_STAT_STATE_RD_SRCENDP \
0x00000020 // Reading source end pointer
#define UDMA_STAT_STATE_RD_DSTENDP \
0x00000030 // Reading destination end pointer
#define UDMA_STAT_STATE_RD_SRCDAT \
0x00000040 // Reading source data
#define UDMA_STAT_STATE_WR_DSTDAT \
0x00000050 // Writing destination data
#define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for DMA request to clear
#define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data
#define UDMA_STAT_STATE_STALL 0x00000080 // Stalled
#define UDMA_STAT_STATE_DONE 0x00000090 // Done
#define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined
#define UDMA_STAT_MASTEN 0x00000001 // Master Enable.
#define UDMA_STAT_DMACHANS_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_DSTENDP register.
//
//*****************************************************************************
#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer.
#define UDMA_DSTENDP_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CFG register.
//
//*****************************************************************************
#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable.
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CTLBASE register.
//
//*****************************************************************************
#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address.
#define UDMA_CTLBASE_ADDR_S 10
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_CHCTL register.
//
//*****************************************************************************
#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment.
#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte
#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word
#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word
#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment
#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size.
#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte
#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word
#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word
#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment.
#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte
#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word
#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word
#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment
#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size.
#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte
#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word
#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word
#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size.
#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer
#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers
#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers
#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers
#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers
#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers
#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers
#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers
#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers
#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers
#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers
#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1).
#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst.
#define UDMA_CHCTL_XFERMODE_M 0x00000007 // DMA Transfer Mode.
#define UDMA_CHCTL_XFERMODE_STOP \
0x00000000 // Stop
#define UDMA_CHCTL_XFERMODE_BASIC \
0x00000001 // Basic
#define UDMA_CHCTL_XFERMODE_AUTO \
0x00000002 // Auto-Request
#define UDMA_CHCTL_XFERMODE_PINGPONG \
0x00000003 // Ping-Pong
#define UDMA_CHCTL_XFERMODE_MEM_SG \
0x00000004 // Memory Scatter-Gather
#define UDMA_CHCTL_XFERMODE_MEM_SGA \
0x00000005 // Alternate Memory Scatter-Gather
#define UDMA_CHCTL_XFERMODE_PER_SG \
0x00000006 // Peripheral Scatter-Gather
#define UDMA_CHCTL_XFERMODE_PER_SGA \
0x00000007 // Alternate Peripheral
// Scatter-Gather
#define UDMA_CHCTL_XFERSIZE_S 4
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ALTBASE register.
//
//*****************************************************************************
#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address
// Pointer.
#define UDMA_ALTBASE_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_WAITSTAT register.
//
//*****************************************************************************
#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status.
#define UDMA_WAITSTAT_WAITREQ_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_SWREQ register.
//
//*****************************************************************************
#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request.
#define UDMA_SWREQ_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_USEBURSTSET
// register.
//
//*****************************************************************************
#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set.
#define UDMA_USEBURSTSET_SET__0 0x00000000 // No Effect
#define UDMA_USEBURSTSET_SET__1 0x00000001 // Burst Only
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_USEBURSTCLR
// register.
//
//*****************************************************************************
#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear.
#define UDMA_USEBURSTCLR_CLR__0 0x00000000 // No Effect
#define UDMA_USEBURSTCLR_CLR__1 0x00000001 // Single and Burst
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_REQMASKSET
// register.
//
//*****************************************************************************
#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set.
#define UDMA_REQMASKSET_SET__0 0x00000000 // No Effect
#define UDMA_REQMASKSET_SET__1 0x00000001 // Masked
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_REQMASKCLR
// register.
//
//*****************************************************************************
#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear.
#define UDMA_REQMASKCLR_CLR__0 0x00000000 // No Effect
#define UDMA_REQMASKCLR_CLR__1 0x00000001 // Clear Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ENASET register.
//
//*****************************************************************************
#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set.
#define UDMA_ENASET_SET__0 0x00000000 // Disabled
#define UDMA_ENASET_SET__1 0x00000001 // Enabled
#define UDMA_ENASET_CHENSET_M 0xFFFFFFFF // Channel [n] Enable Set.
#define UDMA_ENASET_CHENSET__0 0x00000000 // No Effect
#define UDMA_ENASET_CHENSET__1 0x00000001 // Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ENACLR register.
//
//*****************************************************************************
#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable.
#define UDMA_ENACLR_CLR__0 0x00000000 // No Effect
#define UDMA_ENACLR_CLR__1 0x00000001 // Disable
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ALTSET register.
//
//*****************************************************************************
#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set.
#define UDMA_ALTSET_SET__0 0x00000000 // No Effect
#define UDMA_ALTSET_SET__1 0x00000001 // Alternate
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ALTCLR register.
//
//*****************************************************************************
#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear.
#define UDMA_ALTCLR_CLR__0 0x00000000 // No Effect
#define UDMA_ALTCLR_CLR__1 0x00000001 // Primary
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_PRIOSET register.
//
//*****************************************************************************
#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set.
#define UDMA_PRIOSET_SET__0 0x00000000 // No Effect
#define UDMA_PRIOSET_SET__1 0x00000001 // High Priority
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_PRIOCLR register.
//
//*****************************************************************************
#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear.
#define UDMA_PRIOCLR_CLR__0 0x00000000 // No Effect
#define UDMA_PRIOCLR_CLR__1 0x00000001 // Default Priority
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ERRCLR register.
//
//*****************************************************************************
#define UDMA_ERRCLR_ERRCLR 0x00000001 // DMA Bus Error Status.
#endif // __HW_UDMA_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/hw_udma.h | C | oos | 15,888 |
//*****************************************************************************
//
// hw_uart.h - Macros and defines used when accessing the UART hardware
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_UART_H__
#define __HW_UART_H__
//*****************************************************************************
//
// The following are defines for the UART Register offsets.
//
//*****************************************************************************
#define UART_O_DR 0x00000000 // Data Register
#define UART_O_RSR 0x00000004 // Receive Status Register (read)
#define UART_O_ECR 0x00000004 // Error Clear Register (write)
#define UART_O_FR 0x00000018 // Flag Register (read only)
#define UART_O_ILPR 0x00000020 // UART IrDA Low-Power Register
#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg
#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg
#define UART_O_LCRH 0x0000002C // UART Line Control
#define UART_O_CTL 0x00000030 // Control Register
#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg
#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg
#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register
#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register
#define UART_O_ICR 0x00000044 // Interrupt Clear Register
#define UART_O_DMACTL 0x00000048 // UART DMA Control
//*****************************************************************************
//
// The following are defines for the Data Register bits
//
//*****************************************************************************
#define UART_DR_OE 0x00000800 // Overrun Error
#define UART_DR_BE 0x00000400 // Break Error
#define UART_DR_PE 0x00000200 // Parity Error
#define UART_DR_FE 0x00000100 // Framing Error
#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received.
#define UART_DR_DATA_S 0
//*****************************************************************************
//
// The following are defines for the Receive Status Register bits
//
//*****************************************************************************
#define UART_RSR_OE 0x00000008 // Overrun Error
#define UART_RSR_BE 0x00000004 // Break Error
#define UART_RSR_PE 0x00000002 // Parity Error
#define UART_RSR_FE 0x00000001 // Framing Error
//*****************************************************************************
//
// The following are defines for the Flag Register bits
//
//*****************************************************************************
#define UART_FR_TXFE 0x00000080 // TX FIFO Empty
#define UART_FR_RXFF 0x00000040 // RX FIFO Full
#define UART_FR_TXFF 0x00000020 // TX FIFO Full
#define UART_FR_RXFE 0x00000010 // RX FIFO Empty
#define UART_FR_BUSY 0x00000008 // UART Busy
//*****************************************************************************
//
// The following are defines for the Integer baud-rate divisor
//
//*****************************************************************************
#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor.
#define UART_IBRD_DIVINT_S 0
//*****************************************************************************
//
// The following are defines for the Fractional baud-rate divisor
//
//*****************************************************************************
#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor.
#define UART_FBRD_DIVFRAC_S 0
//*****************************************************************************
//
// The following are defines for the Control Register bits
//
//*****************************************************************************
#define UART_CTL_RXE 0x00000200 // Receive Enable
#define UART_CTL_TXE 0x00000100 // Transmit Enable
#define UART_CTL_LBE 0x00000080 // Loopback Enable
#define UART_CTL_SIRLP 0x00000004 // SIR (IrDA) Low Power Enable
#define UART_CTL_SIREN 0x00000002 // SIR (IrDA) Enable
#define UART_CTL_UARTEN 0x00000001 // UART Enable
//*****************************************************************************
//
// The following are defines for the Interrupt FIFO Level Select Register bits
//
//*****************************************************************************
#define UART_IFLS_RX_M 0x00000038 // RX FIFO Level Interrupt Mask
#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full
#define UART_IFLS_RX2_8 0x00000008 // 1/4 Full
#define UART_IFLS_RX4_8 0x00000010 // 1/2 Full
#define UART_IFLS_RX6_8 0x00000018 // 3/4 Full
#define UART_IFLS_RX7_8 0x00000020 // 7/8 Full
#define UART_IFLS_TX_M 0x00000007 // TX FIFO Level Interrupt Mask
#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full
#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full
#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full
#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full
#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full
//*****************************************************************************
//
// The following are defines for the Interrupt Mask Set/Clear Register bits
//
//*****************************************************************************
#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask
#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask
#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask
#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask
#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask
#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask
#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask
//*****************************************************************************
//
// The following are defines for the Raw Interrupt Status Register
//
//*****************************************************************************
#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status
#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status
#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status
#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status
#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status
#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status
#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status
//*****************************************************************************
//
// The following are defines for the Masked Interrupt Status Register
//
//*****************************************************************************
#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status
#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status
#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status
#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status
#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status
#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status
#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status
//*****************************************************************************
//
// The following are defines for the Interrupt Clear Register bits
//
//*****************************************************************************
#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear
#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear
#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear
#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear
#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear
#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear
#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_ECR register.
//
//*****************************************************************************
#define UART_ECR_DATA_M 0x000000FF // Error Clear.
#define UART_ECR_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_LCRH register.
//
//*****************************************************************************
#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select.
#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length.
#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default)
#define UART_LCRH_WLEN_6 0x00000020 // 6 bits
#define UART_LCRH_WLEN_7 0x00000040 // 7 bits
#define UART_LCRH_WLEN_8 0x00000060 // 8 bits
#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs.
#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select.
#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select.
#define UART_LCRH_PEN 0x00000002 // UART Parity Enable.
#define UART_LCRH_BRK 0x00000001 // UART Send Break.
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_ILPR register.
//
//*****************************************************************************
#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor.
#define UART_ILPR_ILPDVSR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_DMACTL register.
//
//*****************************************************************************
#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error.
#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable.
#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable.
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the UART Register offsets.
//
//*****************************************************************************
#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte
#define UART_O_PeriphID4 0x00000FD0
#define UART_O_PeriphID5 0x00000FD4
#define UART_O_PeriphID6 0x00000FD8
#define UART_O_PeriphID7 0x00000FDC
#define UART_O_PeriphID0 0x00000FE0
#define UART_O_PeriphID1 0x00000FE4
#define UART_O_PeriphID2 0x00000FE8
#define UART_O_PeriphID3 0x00000FEC
#define UART_O_PCellID0 0x00000FF0
#define UART_O_PCellID1 0x00000FF4
#define UART_O_PCellID2 0x00000FF8
#define UART_O_PCellID3 0x00000FFC
//*****************************************************************************
//
// The following are deprecated defines for the Data Register bits
//
//*****************************************************************************
#define UART_DR_DATA_MASK 0x000000FF // UART data
//*****************************************************************************
//
// The following are deprecated defines for the Integer baud-rate divisor
//
//*****************************************************************************
#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor
//*****************************************************************************
//
// The following are deprecated defines for the Fractional baud-rate divisor
//
//*****************************************************************************
#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor
//*****************************************************************************
//
// The following are deprecated defines for the Line Control Register High bits
//
//*****************************************************************************
#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select
#define UART_LCR_H_WLEN 0x00000060 // Word length
#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data
#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data
#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data
#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data
#define UART_LCR_H_FEN 0x00000010 // Enable FIFO
#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select
#define UART_LCR_H_EPS 0x00000004 // Even Parity Select
#define UART_LCR_H_PEN 0x00000002 // Parity Enable
#define UART_LCR_H_BRK 0x00000001 // Send Break
//*****************************************************************************
//
// The following are deprecated defines for the Interrupt FIFO Level Select
// Register bits
//
//*****************************************************************************
#define UART_IFLS_RX_MASK 0x00000038 // RX FIFO level mask
#define UART_IFLS_TX_MASK 0x00000007 // TX FIFO level mask
//*****************************************************************************
//
// The following are deprecated defines for the Interrupt Clear Register bits
//
//*****************************************************************************
#define UART_RSR_ANY (UART_RSR_OE | UART_RSR_BE | UART_RSR_PE | \
UART_RSR_FE)
//*****************************************************************************
//
// The following are deprecated defines for the Reset Values for UART
// Registers.
//
//*****************************************************************************
#define UART_RV_CTL 0x00000300
#define UART_RV_PCellID1 0x000000F0
#define UART_RV_PCellID3 0x000000B1
#define UART_RV_FR 0x00000090
#define UART_RV_PeriphID2 0x00000018
#define UART_RV_IFLS 0x00000012
#define UART_RV_PeriphID0 0x00000011
#define UART_RV_PCellID0 0x0000000D
#define UART_RV_PCellID2 0x00000005
#define UART_RV_PeriphID3 0x00000001
#define UART_RV_PeriphID4 0x00000000
#define UART_RV_LCR_H 0x00000000
#define UART_RV_PeriphID6 0x00000000
#define UART_RV_DR 0x00000000
#define UART_RV_RSR 0x00000000
#define UART_RV_ECR 0x00000000
#define UART_RV_PeriphID5 0x00000000
#define UART_RV_RIS 0x00000000
#define UART_RV_FBRD 0x00000000
#define UART_RV_IM 0x00000000
#define UART_RV_MIS 0x00000000
#define UART_RV_ICR 0x00000000
#define UART_RV_PeriphID1 0x00000000
#define UART_RV_PeriphID7 0x00000000
#define UART_RV_IBRD 0x00000000
#endif
#endif // __HW_UART_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/hw_uart.h | C | oos | 17,084 |
//*****************************************************************************
//
// hibernate.h - API definition for the Hibernation module.
//
// Copyright (c) 2007-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HIBERNATE_H__
#define __HIBERNATE_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Macros needed for selecting the clock source for HibernateClockSelect()
//
//*****************************************************************************
#define HIBERNATE_CLOCK_SEL_RAW 0x04
#define HIBERNATE_CLOCK_SEL_DIV128 0x00
//*****************************************************************************
//
// Macros need to configure wake events for HibernateWakeSet()
//
//*****************************************************************************
#define HIBERNATE_WAKE_PIN 0x10
#define HIBERNATE_WAKE_RTC 0x08
//*****************************************************************************
//
// Macros needed to configure low battery detect for HibernateLowBatSet()
//
//*****************************************************************************
#define HIBERNATE_LOW_BAT_DETECT 0x20
#define HIBERNATE_LOW_BAT_ABORT 0xA0
//*****************************************************************************
//
// Macros defining interrupt source bits for the interrupt functions.
//
//*****************************************************************************
#define HIBERNATE_INT_PIN_WAKE 0x08
#define HIBERNATE_INT_LOW_BAT 0x04
#define HIBERNATE_INT_RTC_MATCH_0 0x01
#define HIBERNATE_INT_RTC_MATCH_1 0x02
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void HibernateEnableExpClk(unsigned long ulHibClk);
extern void HibernateDisable(void);
extern void HibernateClockSelect(unsigned long ulClockInput);
extern void HibernateRTCEnable(void);
extern void HibernateRTCDisable(void);
extern void HibernateWakeSet(unsigned long ulWakeFlags);
extern unsigned long HibernateWakeGet(void);
extern void HibernateLowBatSet(unsigned long ulLowBatFlags);
extern unsigned long HibernateLowBatGet(void);
extern void HibernateRTCSet(unsigned long ulRTCValue);
extern unsigned long HibernateRTCGet(void);
extern void HibernateRTCMatch0Set(unsigned long ulMatch);
extern unsigned long HibernateRTCMatch0Get(void);
extern void HibernateRTCMatch1Set(unsigned long ulMatch);
extern unsigned long HibernateRTCMatch1Get(void);
extern void HibernateRTCTrimSet(unsigned long ulTrim);
extern unsigned long HibernateRTCTrimGet(void);
extern void HibernateDataSet(unsigned long *pulData, unsigned long ulCount);
extern void HibernateDataGet(unsigned long *pulData, unsigned long ulCount);
extern void HibernateRequest(void);
extern void HibernateIntEnable(unsigned long ulIntFlags);
extern void HibernateIntDisable(unsigned long ulIntFlags);
extern void HibernateIntRegister(void (*pfnHandler)(void));
extern void HibernateIntUnregister(void);
extern unsigned long HibernateIntStatus(tBoolean bMasked);
extern void HibernateIntClear(unsigned long ulIntFlags);
extern unsigned int HibernateIsActive(void);
//*****************************************************************************
//
// Several Hibernate module APIs have been renamed, with the original function
// name being deprecated. These defines provide backward compatibility.
//
//*****************************************************************************
#ifndef DEPRECATED
#include "sysctl.h"
#define HibernateEnable(a) \
HibernateEnableExpClk(a, SysCtlClockGet())
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __HIBERNATE_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/hibernate.h | C | oos | 5,634 |
//*****************************************************************************
//
// watchdog.h - Prototypes for the Watchdog Timer API
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __WATCHDOG_H__
#define __WATCHDOG_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern tBoolean WatchdogRunning(unsigned long ulBase);
extern void WatchdogEnable(unsigned long ulBase);
extern void WatchdogResetEnable(unsigned long ulBase);
extern void WatchdogResetDisable(unsigned long ulBase);
extern void WatchdogLock(unsigned long ulBase);
extern void WatchdogUnlock(unsigned long ulBase);
extern tBoolean WatchdogLockState(unsigned long ulBase);
extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal);
extern unsigned long WatchdogReloadGet(unsigned long ulBase);
extern unsigned long WatchdogValueGet(unsigned long ulBase);
extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern void WatchdogIntUnregister(unsigned long ulBase);
extern void WatchdogIntEnable(unsigned long ulBase);
extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void WatchdogIntClear(unsigned long ulBase);
extern void WatchdogStallEnable(unsigned long ulBase);
extern void WatchdogStallDisable(unsigned long ulBase);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __WATCHDOG_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/watchdog.h | C | oos | 3,273 |
//*****************************************************************************
//
// qei.h - Prototypes for the Quadrature Encoder Driver.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __QEI_H__
#define __QEI_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to QEIConfigure as the ulConfig paramater.
//
//*****************************************************************************
#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only
#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges
#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse
#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse
#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature
#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir
#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB
#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB
//*****************************************************************************
//
// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter.
//
//*****************************************************************************
#define QEI_VELDIV_1 0x00000000 // Predivide by 1
#define QEI_VELDIV_2 0x00000040 // Predivide by 2
#define QEI_VELDIV_4 0x00000080 // Predivide by 4
#define QEI_VELDIV_8 0x000000C0 // Predivide by 8
#define QEI_VELDIV_16 0x00000100 // Predivide by 16
#define QEI_VELDIV_32 0x00000140 // Predivide by 32
#define QEI_VELDIV_64 0x00000180 // Predivide by 64
#define QEI_VELDIV_128 0x000001C0 // Predivide by 128
//*****************************************************************************
//
// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts
// as the ulIntFlags parameter, and returned by QEIGetIntStatus.
//
//*****************************************************************************
#define QEI_INTERROR 0x00000008 // Phase error detected
#define QEI_INTDIR 0x00000004 // Direction change
#define QEI_INTTIMER 0x00000002 // Velocity timer expired
#define QEI_INTINDEX 0x00000001 // Index pulse detected
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void QEIEnable(unsigned long ulBase);
extern void QEIDisable(unsigned long ulBase);
extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig,
unsigned long ulMaxPosition);
extern unsigned long QEIPositionGet(unsigned long ulBase);
extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition);
extern long QEIDirectionGet(unsigned long ulBase);
extern tBoolean QEIErrorGet(unsigned long ulBase);
extern void QEIVelocityEnable(unsigned long ulBase);
extern void QEIVelocityDisable(unsigned long ulBase);
extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv,
unsigned long ulPeriod);
extern unsigned long QEIVelocityGet(unsigned long ulBase);
extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern void QEIIntUnregister(unsigned long ulBase);
extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __QEI_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/qei.h | C | oos | 5,631 |
//*****************************************************************************
//
// hw_ssi.h - Macros used when accessing the SSI hardware.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_SSI_H__
#define __HW_SSI_H__
//*****************************************************************************
//
// The following are defines for the SSI register offsets.
//
//*****************************************************************************
#define SSI_O_CR0 0x00000000 // Control register 0
#define SSI_O_CR1 0x00000004 // Control register 1
#define SSI_O_DR 0x00000008 // Data register
#define SSI_O_SR 0x0000000C // Status register
#define SSI_O_CPSR 0x00000010 // Clock prescale register
#define SSI_O_IM 0x00000014 // Int mask set and clear register
#define SSI_O_RIS 0x00000018 // Raw interrupt register
#define SSI_O_MIS 0x0000001C // Masked interrupt register
#define SSI_O_ICR 0x00000020 // Interrupt clear register
#define SSI_O_DMACTL 0x00000024 // SSI DMA Control
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI Control register 0.
//
//*****************************************************************************
#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate.
#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase
#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity
#define SSI_CR0_FRF_M 0x00000030 // Frame format mask
#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format
#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format
#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format
#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select.
#define SSI_CR0_DSS_4 0x00000003 // 4 bit data
#define SSI_CR0_DSS_5 0x00000004 // 5 bit data
#define SSI_CR0_DSS_6 0x00000005 // 6 bit data
#define SSI_CR0_DSS_7 0x00000006 // 7 bit data
#define SSI_CR0_DSS_8 0x00000007 // 8 bit data
#define SSI_CR0_DSS_9 0x00000008 // 9 bit data
#define SSI_CR0_DSS_10 0x00000009 // 10 bit data
#define SSI_CR0_DSS_11 0x0000000A // 11 bit data
#define SSI_CR0_DSS_12 0x0000000B // 12 bit data
#define SSI_CR0_DSS_13 0x0000000C // 13 bit data
#define SSI_CR0_DSS_14 0x0000000D // 14 bit data
#define SSI_CR0_DSS_15 0x0000000E // 15 bit data
#define SSI_CR0_DSS_16 0x0000000F // 16 bit data
#define SSI_CR0_SCR_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI Control register 1.
//
//*****************************************************************************
#define SSI_CR1_SOD 0x00000008 // Slave mode output disable
#define SSI_CR1_MS 0x00000004 // Master or slave mode select
#define SSI_CR1_SSE 0x00000002 // Sync serial port enable
#define SSI_CR1_LBM 0x00000001 // Loopback mode
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI Status register.
//
//*****************************************************************************
#define SSI_SR_BSY 0x00000010 // SSI busy
#define SSI_SR_RFF 0x00000008 // RX FIFO full
#define SSI_SR_RNE 0x00000004 // RX FIFO not empty
#define SSI_SR_TNF 0x00000002 // TX FIFO not full
#define SSI_SR_TFE 0x00000001 // TX FIFO empty
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI clock prescale
// register.
//
//*****************************************************************************
#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor.
#define SSI_CPSR_CPSDVSR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_DR register.
//
//*****************************************************************************
#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data.
#define SSI_DR_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_IM register.
//
//*****************************************************************************
#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt
// Mask.
#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask.
#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt
// Mask.
#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt
// Mask.
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_RIS register.
//
//*****************************************************************************
#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt
// Status.
#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt
// Status.
#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw
// Interrupt Status.
#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw
// Interrupt Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_MIS register.
//
//*****************************************************************************
#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked
// Interrupt Status.
#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked
// Interrupt Status.
#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked
// Interrupt Status.
#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked
// Interrupt Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_ICR register.
//
//*****************************************************************************
#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt
// Clear.
#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt
// Clear.
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_DMACTL register.
//
//*****************************************************************************
#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable.
#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable.
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the SSI Control
// register 0.
//
//*****************************************************************************
#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate
#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask
#define SSI_CR0_DSS 0x0000000F // Data size select
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the SSI clock
// prescale register.
//
//*****************************************************************************
#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale
//*****************************************************************************
//
// The following are deprecated defines for the SSI controller's FIFO size.
//
//*****************************************************************************
#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO
#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the interrupt
// mask set and clear, raw interrupt, masked interrupt, and interrupt clear
// registers.
//
//*****************************************************************************
#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt
#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt
#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt
#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt
#endif
#endif // __HW_SSI_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/hw_ssi.h | C | oos | 11,146 |
//*****************************************************************************
//
// sysctl.h - Prototypes for the system control driver.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __SYSCTL_H__
#define __SYSCTL_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following are values that can be passed to the
// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),
// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the
// ulPeripheral parameter. The peripherals in the fourth group (upper nibble
// is 3) can only be used with the SysCtlPeripheralPresent() API.
//
//*****************************************************************************
#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog
#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module
#define SYSCTL_PERIPH_ADC 0x00100001 // ADC
#define SYSCTL_PERIPH_PWM 0x00100010 // PWM
#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0
#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1
#define SYSCTL_PERIPH_CAN2 0x00100400 // CAN 2
#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0
#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1
#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2
#ifndef DEPRECATED
#define SYSCTL_PERIPH_SSI 0x10000010 // SSI
#endif
#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0
#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1
#ifndef DEPRECATED
#define SYSCTL_PERIPH_QEI 0x10000100 // QEI
#endif
#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0
#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1
#ifndef DEPRECATED
#define SYSCTL_PERIPH_I2C 0x10001000 // I2C
#endif
#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0
#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1
#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0
#define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1
#define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2
#define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3
#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0
#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1
#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2
#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A
#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B
#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C
#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D
#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E
#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F
#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G
#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H
#define SYSCTL_PERIPH_UDMA 0x20002000 // uDMA
#define SYSCTL_PERIPH_USB0 0x20100001 // USB0
#define SYSCTL_PERIPH_ETH 0x20105000 // ETH
#define SYSCTL_PERIPH_IEEE1588 0x20100100 // IEEE1588
#define SYSCTL_PERIPH_PLL 0x30000010 // PLL
#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor
#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex-M3 MPU
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlPinPresent() API
// as the ulPin parameter.
//
//*****************************************************************************
#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin
#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin
#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin
#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin
#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin
#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin
#define SYSCTL_PIN_PWM6 0x00000040 // PWM6 pin
#define SYSCTL_PIN_PWM7 0x00000080 // PWM7 pin
#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin
#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin
#define SYSCTL_PIN_C0O 0x00000100 // C0o pin
#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin
#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin
#define SYSCTL_PIN_C1O 0x00000800 // C1o pin
#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin
#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin
#define SYSCTL_PIN_C2O 0x00004000 // C2o pin
#define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin
#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin
#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin
#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin
#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin
#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin
#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin
#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin
#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin
#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin
#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin
#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin
#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin
#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin
#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin
#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlLDOSet() API as
// the ulVoltage value, or returned by the SysCtlLDOGet() API.
//
//*****************************************************************************
#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V
#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V
#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V
#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V
#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V
#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V
#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V
#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V
#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V
#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V
#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlLDOConfigSet() API.
//
//*****************************************************************************
#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset
#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlIntEnable(),
// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask
// by the SysCtlIntStatus() API.
//
//*****************************************************************************
#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt
#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int
#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt
#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlResetCauseClear()
// API or returned by the SysCtlResetCauseGet() API.
//
//*****************************************************************************
#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset
#define SYSCTL_CAUSE_SW 0x00000010 // Software reset
#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset
#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset
#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset
#define SYSCTL_CAUSE_EXT 0x00000001 // External reset
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlBrownOutConfigSet()
// API as the ulConfig parameter.
//
//*****************************************************************************
#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting
#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlPWMClockSet() API
// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet()
// API.
//
//*****************************************************************************
#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1
#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2
#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4
#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8
#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16
#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32
#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlADCSpeedSet() API
// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet()
// API.
//
//*****************************************************************************
#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second
#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second
#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second
#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlClockSet() API as
// the ulConfig parameter.
//
//*****************************************************************************
#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1
#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2
#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3
#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4
#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5
#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6
#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7
#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8
#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9
#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10
#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11
#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12
#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13
#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14
#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15
#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16
#define SYSCTL_SYSDIV_17 0x88400000 // Processor clock is osc/pll /17
#define SYSCTL_SYSDIV_18 0x88C00000 // Processor clock is osc/pll /18
#define SYSCTL_SYSDIV_19 0x89400000 // Processor clock is osc/pll /19
#define SYSCTL_SYSDIV_20 0x89C00000 // Processor clock is osc/pll /20
#define SYSCTL_SYSDIV_21 0x8A400000 // Processor clock is osc/pll /21
#define SYSCTL_SYSDIV_22 0x8AC00000 // Processor clock is osc/pll /22
#define SYSCTL_SYSDIV_23 0x8B400000 // Processor clock is osc/pll /23
#define SYSCTL_SYSDIV_24 0x8BC00000 // Processor clock is osc/pll /24
#define SYSCTL_SYSDIV_25 0x8C400000 // Processor clock is osc/pll /25
#define SYSCTL_SYSDIV_26 0x8CC00000 // Processor clock is osc/pll /26
#define SYSCTL_SYSDIV_27 0x8D400000 // Processor clock is osc/pll /27
#define SYSCTL_SYSDIV_28 0x8DC00000 // Processor clock is osc/pll /28
#define SYSCTL_SYSDIV_29 0x8E400000 // Processor clock is osc/pll /29
#define SYSCTL_SYSDIV_30 0x8EC00000 // Processor clock is osc/pll /30
#define SYSCTL_SYSDIV_31 0x8F400000 // Processor clock is osc/pll /31
#define SYSCTL_SYSDIV_32 0x8FC00000 // Processor clock is osc/pll /32
#define SYSCTL_SYSDIV_33 0x90400000 // Processor clock is osc/pll /33
#define SYSCTL_SYSDIV_34 0x90C00000 // Processor clock is osc/pll /34
#define SYSCTL_SYSDIV_35 0x91400000 // Processor clock is osc/pll /35
#define SYSCTL_SYSDIV_36 0x91C00000 // Processor clock is osc/pll /36
#define SYSCTL_SYSDIV_37 0x92400000 // Processor clock is osc/pll /37
#define SYSCTL_SYSDIV_38 0x92C00000 // Processor clock is osc/pll /38
#define SYSCTL_SYSDIV_39 0x93400000 // Processor clock is osc/pll /39
#define SYSCTL_SYSDIV_40 0x93C00000 // Processor clock is osc/pll /40
#define SYSCTL_SYSDIV_41 0x94400000 // Processor clock is osc/pll /41
#define SYSCTL_SYSDIV_42 0x94C00000 // Processor clock is osc/pll /42
#define SYSCTL_SYSDIV_43 0x95400000 // Processor clock is osc/pll /43
#define SYSCTL_SYSDIV_44 0x95C00000 // Processor clock is osc/pll /44
#define SYSCTL_SYSDIV_45 0x96400000 // Processor clock is osc/pll /45
#define SYSCTL_SYSDIV_46 0x96C00000 // Processor clock is osc/pll /46
#define SYSCTL_SYSDIV_47 0x97400000 // Processor clock is osc/pll /47
#define SYSCTL_SYSDIV_48 0x97C00000 // Processor clock is osc/pll /48
#define SYSCTL_SYSDIV_49 0x98400000 // Processor clock is osc/pll /49
#define SYSCTL_SYSDIV_50 0x98C00000 // Processor clock is osc/pll /50
#define SYSCTL_SYSDIV_51 0x99400000 // Processor clock is osc/pll /51
#define SYSCTL_SYSDIV_52 0x99C00000 // Processor clock is osc/pll /52
#define SYSCTL_SYSDIV_53 0x9A400000 // Processor clock is osc/pll /53
#define SYSCTL_SYSDIV_54 0x9AC00000 // Processor clock is osc/pll /54
#define SYSCTL_SYSDIV_55 0x9B400000 // Processor clock is osc/pll /55
#define SYSCTL_SYSDIV_56 0x9BC00000 // Processor clock is osc/pll /56
#define SYSCTL_SYSDIV_57 0x9C400000 // Processor clock is osc/pll /57
#define SYSCTL_SYSDIV_58 0x9CC00000 // Processor clock is osc/pll /58
#define SYSCTL_SYSDIV_59 0x9D400000 // Processor clock is osc/pll /59
#define SYSCTL_SYSDIV_60 0x9DC00000 // Processor clock is osc/pll /60
#define SYSCTL_SYSDIV_61 0x9E400000 // Processor clock is osc/pll /61
#define SYSCTL_SYSDIV_62 0x9EC00000 // Processor clock is osc/pll /62
#define SYSCTL_SYSDIV_63 0x9F400000 // Processor clock is osc/pll /63
#define SYSCTL_SYSDIV_64 0x9FC00000 // Processor clock is osc/pll /64
#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock
#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock
#define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz
#define SYSCTL_XTAL_1_84MHZ 0x00000040 // External crystal is 1.8432MHz
#define SYSCTL_XTAL_2MHZ 0x00000080 // External crystal is 2MHz
#define SYSCTL_XTAL_2_45MHZ 0x000000C0 // External crystal is 2.4576MHz
#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz
#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz
#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz
#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz
#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz
#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz
#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz
#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz
#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz
#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz
#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz
#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz
#define SYSCTL_XTAL_10MHZ 0x00000400 // External crystal is 10 MHz
#define SYSCTL_XTAL_12MHZ 0x00000440 // External crystal is 12 MHz
#define SYSCTL_XTAL_12_2MHZ 0x00000480 // External crystal is 12.288 MHz
#define SYSCTL_XTAL_13_5MHZ 0x000004C0 // External crystal is 13.56 MHz
#define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz
#define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz
#define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz
#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc
#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc
#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4
#define SYSCTL_OSC_INT30 0x80000030 // Oscillator source is int. 30 KHz
#define SYSCTL_OSC_EXT32 0x80000038 // Oscillator source is ext. 32 KHz
#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator
#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern unsigned long SysCtlSRAMSizeGet(void);
extern unsigned long SysCtlFlashSizeGet(void);
extern tBoolean SysCtlPinPresent(unsigned long ulPin);
extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);
extern void SysCtlPeripheralReset(unsigned long ulPeripheral);
extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);
extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral);
extern void SysCtlPeripheralClockGating(tBoolean bEnable);
extern void SysCtlIntRegister(void (*pfnHandler)(void));
extern void SysCtlIntUnregister(void);
extern void SysCtlIntEnable(unsigned long ulInts);
extern void SysCtlIntDisable(unsigned long ulInts);
extern void SysCtlIntClear(unsigned long ulInts);
extern unsigned long SysCtlIntStatus(tBoolean bMasked);
extern void SysCtlLDOSet(unsigned long ulVoltage);
extern unsigned long SysCtlLDOGet(void);
extern void SysCtlLDOConfigSet(unsigned long ulConfig);
extern void SysCtlReset(void);
extern void SysCtlSleep(void);
extern void SysCtlDeepSleep(void);
extern unsigned long SysCtlResetCauseGet(void);
extern void SysCtlResetCauseClear(unsigned long ulCauses);
extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,
unsigned long ulDelay);
extern void SysCtlDelay(unsigned long ulCount);
extern void SysCtlClockSet(unsigned long ulConfig);
extern unsigned long SysCtlClockGet(void);
extern void SysCtlPWMClockSet(unsigned long ulConfig);
extern unsigned long SysCtlPWMClockGet(void);
extern void SysCtlADCSpeedSet(unsigned long ulSpeed);
extern unsigned long SysCtlADCSpeedGet(void);
extern void SysCtlIOSCVerificationSet(tBoolean bEnable);
extern void SysCtlMOSCVerificationSet(tBoolean bEnable);
extern void SysCtlPLLVerificationSet(tBoolean bEnable);
extern void SysCtlClkVerificationClear(void);
extern void SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral);
extern void SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral);
extern void SysCtlUSBPLLEnable(void);
extern void SysCtlUSBPLLDisable(void);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __SYSCTL_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/sysctl.h | C | oos | 22,420 |