code stringlengths 1 2.01M | repo_name stringlengths 3 62 | path stringlengths 1 267 | language stringclasses 231 values | license stringclasses 13 values | size int64 1 2.01M |
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//*****************************************************************************
//
// timer.h - Prototypes for the timer module
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __TIMER_H__
#define __TIMER_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to TimerConfigure as the ulConfig parameter.
//
//*****************************************************************************
#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer
#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer
#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer
#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers
#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer
#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer
#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter
#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer
#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output
#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer
#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer
#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter
#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer
#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output
//*****************************************************************************
//
// Values that can be passed to TimerIntEnable, TimerIntDisable, and
// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.
//
//*****************************************************************************
#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt
#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt
#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt
#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask
#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt
#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt
#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt
//*****************************************************************************
//
// Values that can be passed to TimerControlEvent as the ulEvent parameter.
//
//*****************************************************************************
#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges
#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges
#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges
//*****************************************************************************
//
// Values that can be passed to most of the timer APIs as the ulTimer
// parameter.
//
//*****************************************************************************
#define TIMER_A 0x000000ff // Timer A
#define TIMER_B 0x0000ff00 // Timer B
#define TIMER_BOTH 0x0000ffff // Timer Both
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);
extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);
extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);
extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,
tBoolean bInvert);
extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,
tBoolean bEnable);
extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulEvent);
extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
tBoolean bStall);
extern void TimerRTCEnable(unsigned long ulBase);
extern void TimerRTCDisable(unsigned long ulBase);
extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerPrescaleGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);
extern unsigned long TimerValueGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerMatchGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
void (*pfnHandler)(void));
extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);
extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);
//*****************************************************************************
//
// TimerQuiesce() has been deprecated. SysCtlPeripheralReset() should be used
// instead to return the timer to its reset state.
//
//*****************************************************************************
#ifndef DEPRECATED
extern void TimerQuiesce(unsigned long ulBase);
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __TIMER_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/timer.h | C | oos | 7,703 |
//*****************************************************************************
//
// flash.h - Prototypes for the flash driver.
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __FLASH_H__
#define __FLASH_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to FlashProtectSet(), and returned by
// FlashProtectGet().
//
//*****************************************************************************
typedef enum
{
FlashReadWrite, // Flash can be read and written
FlashReadOnly, // Flash can only be read
FlashExecuteOnly // Flash can only be executed
}
tFlashProtection;
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern unsigned long FlashUsecGet(void);
extern void FlashUsecSet(unsigned long ulClocks);
extern long FlashErase(unsigned long ulAddress);
extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,
unsigned long ulCount);
extern tFlashProtection FlashProtectGet(unsigned long ulAddress);
extern long FlashProtectSet(unsigned long ulAddress,
tFlashProtection eProtect);
extern long FlashProtectSave(void);
extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1);
extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1);
extern long FlashUserSave(void);
extern void FlashIntRegister(void (*pfnHandler)(void));
extern void FlashIntUnregister(void);
extern void FlashIntEnable(unsigned long ulIntFlags);
extern void FlashIntDisable(unsigned long ulIntFlags);
extern unsigned long FlashIntGetStatus(tBoolean bMasked);
extern void FlashIntClear(unsigned long ulIntFlags);
#ifdef __cplusplus
}
#endif
#endif // __FLASH_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/lmi_flash.h | C | oos | 3,135 |
//*****************************************************************************
//
// mpu.h - Defines and Macros for the memory protection unit.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __MPU_H__
#define __MPU_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Flags that can be passed to MPUEnable..
//
//*****************************************************************************
#define MPU_CONFIG_PRIV_DEFAULT 4
#define MPU_CONFIG_HARDFLT_NMI 2
#define MPU_CONFIG_NONE 0
//*****************************************************************************
//
// Flags for the region size to be passed to MPURegionSet.
//
//*****************************************************************************
#define MPU_RGN_SIZE_32B (4 << 1)
#define MPU_RGN_SIZE_64B (5 << 1)
#define MPU_RGN_SIZE_128B (6 << 1)
#define MPU_RGN_SIZE_256B (7 << 1)
#define MPU_RGN_SIZE_512B (8 << 1)
#define MPU_RGN_SIZE_1K (9 << 1)
#define MPU_RGN_SIZE_2K (10 << 1)
#define MPU_RGN_SIZE_4K (11 << 1)
#define MPU_RGN_SIZE_8K (12 << 1)
#define MPU_RGN_SIZE_16K (13 << 1)
#define MPU_RGN_SIZE_32K (14 << 1)
#define MPU_RGN_SIZE_64K (15 << 1)
#define MPU_RGN_SIZE_128K (16 << 1)
#define MPU_RGN_SIZE_256K (17 << 1)
#define MPU_RGN_SIZE_512K (18 << 1)
#define MPU_RGN_SIZE_1M (19 << 1)
#define MPU_RGN_SIZE_2M (20 << 1)
#define MPU_RGN_SIZE_4M (21 << 1)
#define MPU_RGN_SIZE_8M (22 << 1)
#define MPU_RGN_SIZE_16M (23 << 1)
#define MPU_RGN_SIZE_32M (24 << 1)
#define MPU_RGN_SIZE_64M (25 << 1)
#define MPU_RGN_SIZE_128M (26 << 1)
#define MPU_RGN_SIZE_256M (27 << 1)
#define MPU_RGN_SIZE_512M (28 << 1)
#define MPU_RGN_SIZE_1G (29 << 1)
#define MPU_RGN_SIZE_2G (30 << 1)
#define MPU_RGN_SIZE_4G (31 << 1)
//*****************************************************************************
//
// Flags for the permissions to be passed to MPURegionSet.
//
//*****************************************************************************
#define MPU_RGN_PERM_EXEC 0x00000000
#define MPU_RGN_PERM_NOEXEC 0x10000000
#define MPU_RGN_PERM_PRV_NO_USR_NO 0x00000000
#define MPU_RGN_PERM_PRV_RW_USR_NO 0x01000000
#define MPU_RGN_PERM_PRV_RW_USR_RO 0x02000000
#define MPU_RGN_PERM_PRV_RW_USR_RW 0x03000000
#define MPU_RGN_PERM_PRV_RO_USR_NO 0x05000000
#define MPU_RGN_PERM_PRV_RO_USR_RO 0x06000000
//*****************************************************************************
//
// Flags for the sub-region to be passed to MPURegionSet.
//
//*****************************************************************************
#define MPU_SUB_RGN_DISABLE_0 0x00000100
#define MPU_SUB_RGN_DISABLE_1 0x00000200
#define MPU_SUB_RGN_DISABLE_2 0x00000400
#define MPU_SUB_RGN_DISABLE_3 0x00000800
#define MPU_SUB_RGN_DISABLE_4 0x00001000
#define MPU_SUB_RGN_DISABLE_5 0x00002000
#define MPU_SUB_RGN_DISABLE_6 0x00004000
#define MPU_SUB_RGN_DISABLE_7 0x00008000
//*****************************************************************************
//
// Flags to enable or disable a region, to be passed to MPURegionSet.
//
//*****************************************************************************
#define MPU_RGN_ENABLE 1
#define MPU_RGN_DISABLE 0
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void MPUEnable(unsigned long ulMPUConfig);
extern void MPUDisable(void);
extern unsigned long MPURegionCountGet(void);
extern void MPURegionEnable(unsigned long ulRegion);
extern void MPURegionDisable(unsigned long ulRegion);
extern void MPURegionSet(unsigned long ulRegion, unsigned long ulAddr,
unsigned long ulFlags);
extern void MPURegionGet(unsigned long ulRegion, unsigned long *pulAddr,
unsigned long *pulFlags);
extern void MPUIntRegister(void (*pfnHandler)(void));
extern void MPUIntUnregister(void);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __MPU_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/mpu.h | C | oos | 6,255 |
//*****************************************************************************
//
// ustdlib.c - Simple standard library functions.
//
// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
//*****************************************************************************
#include <stdarg.h>
#include <string.h>
#include "debug.h"
//*****************************************************************************
//
//! \addtogroup utilities_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// A mapping from an integer between 0 and 15 to its ASCII character
// equivalent.
//
//*****************************************************************************
static const char * const g_pcHex = "0123456789abcdef";
//*****************************************************************************
//
//! A simple vsnprintf function supporting \%c, \%d, \%s, \%u, \%x, and \%X.
//!
//! \param pcBuf points to the buffer where the converted string is stored.
//! \param ulSize is the size of the buffer.
//! \param pcString is the format string.
//! \param vaArgP is the list of optional arguments, which depend on the
//! contents of the format string.
//!
//! This function is very similar to the C library <tt>vsnprintf()</tt>
//! function. Only the following formatting characters are supported:
//!
//! - \%c to print a character
//! - \%d to print a decimal value
//! - \%s to print a string
//! - \%u to print an unsigned decimal value
//! - \%x to print a hexadecimal value using lower case letters
//! - \%X to print a hexadecimal value using lower case letters (not upper case
//! letters as would typically be used)
//! - \%\% to print out a \% character
//!
//! For \%d, \%u, \%x, and \%X, an optional number may reside between the \%
//! and the format character, which specifies the minimum number of characters
//! to use for that value; if preceeded by a 0 then the extra characters will
//! be filled with zeros instead of spaces. For example, ``\%8d'' will use
//! eight characters to print the decimal value with spaces added to reach
//! eight; ``\%08d'' will use eight characters as well but will add zeros
//! instead of spaces.
//!
//! The type of the arguments after \b pcString must match the requirements of
//! the format string. For example, if an integer was passed where a string
//! was expected, an error of some kind will most likely occur.
//!
//! The \b ulSize parameter limits the number of characters that will be
//! stored in the buffer pointed to by \b pcBuf to prevent the possibility
//! of a buffer overflow. The buffer size should be large enough to hold
//! the expected converted output string, including the null termination
//! character.
//!
//! The function will return the number of characters that would be
//! converted as if there were no limit on the buffer size. Therefore
//! it is possible for the function to return a count that is greater than
//! the specified buffer size. If this happens, it means that the output
//! was truncated.
//!
//! \return the number of characters that were to be stored, not including
//! the NULL termination character, regardless of space in the buffer.
//
//*****************************************************************************
int
uvsnprintf(char *pcBuf, unsigned long ulSize, const char *pcString,
va_list vaArgP)
{
unsigned long ulIdx, ulValue, ulCount, ulBase;
char *pcStr, cFill;
int iConvertCount = 0;
//
// Check the arguments.
//
ASSERT(pcString != 0);
ASSERT(pcBuf != 0);
ASSERT(ulSize != 0);
//
// Adjust buffer size limit to allow one space for null termination.
//
if(ulSize)
{
ulSize--;
}
//
// Initialize the count of characters converted.
//
iConvertCount = 0;
//
// Loop while there are more characters in the format string.
//
while(*pcString)
{
//
// Find the first non-% character, or the end of the string.
//
for(ulIdx = 0; (pcString[ulIdx] != '%') && (pcString[ulIdx] != '\0');
ulIdx++)
{
}
//
// Write this portion of the string to the output buffer. If
// there are more characters to write than there is space in the
// buffer, then only write as much as will fit in the buffer.
//
if(ulIdx > ulSize)
{
strncpy(pcBuf, pcString, ulSize);
pcBuf += ulSize;
ulSize = 0;
}
else
{
strncpy(pcBuf, pcString, ulIdx);
pcBuf += ulIdx;
ulSize -= ulIdx;
}
//
// Update the conversion count. This will be the number of
// characters that should have been written, even if there was
// not room in the buffer.
//
iConvertCount += ulIdx;
//
// Skip the portion of the format string that was written.
//
pcString += ulIdx;
//
// See if the next character is a %.
//
if(*pcString == '%')
{
//
// Skip the %.
//
pcString++;
//
// Set the digit count to zero, and the fill character to space
// (i.e. to the defaults).
//
ulCount = 0;
cFill = ' ';
//
// It may be necessary to get back here to process more characters.
// Goto's aren't pretty, but effective. I feel extremely dirty for
// using not one but two of the beasts.
//
again:
//
// Determine how to handle the next character.
//
switch(*pcString++)
{
//
// Handle the digit characters.
//
case '0':
case '1':
case '2':
case '3':
case '4':
case '5':
case '6':
case '7':
case '8':
case '9':
{
//
// If this is a zero, and it is the first digit, then the
// fill character is a zero instead of a space.
//
if((pcString[-1] == '0') && (ulCount == 0))
{
cFill = '0';
}
//
// Update the digit count.
//
ulCount *= 10;
ulCount += pcString[-1] - '0';
//
// Get the next character.
//
goto again;
}
//
// Handle the %c command.
//
case 'c':
{
//
// Get the value from the varargs.
//
ulValue = va_arg(vaArgP, unsigned long);
//
// Copy the character to the output buffer, if
// there is room. Update the buffer size remaining.
//
if(ulSize != 0)
{
*pcBuf++ = (char)ulValue;
ulSize--;
}
//
// Update the conversion count.
//
iConvertCount++;
//
// This command has been handled.
//
break;
}
//
// Handle the %d command.
//
case 'd':
{
//
// Get the value from the varargs.
//
ulValue = va_arg(vaArgP, unsigned long);
//
// If the value is negative, make it positive and stick a
// minus sign in the beginning of the buffer.
//
if((long)ulValue < 0)
{
ulValue = -(long)ulValue;
if(ulSize != 0)
{
*pcBuf++ = '-';
ulSize--;
}
//
// Update the conversion count.
//
iConvertCount++;
}
//
// Set the base to 10.
//
ulBase = 10;
//
// Convert the value to ASCII.
//
goto convert;
}
//
// Handle the %s command.
//
case 's':
{
//
// Get the string pointer from the varargs.
//
pcStr = va_arg(vaArgP, char *);
//
// Determine the length of the string.
//
for(ulIdx = 0; pcStr[ulIdx] != '\0'; ulIdx++)
{
}
//
// Copy the string to the output buffer. Only copy
// as much as will fit in the buffer. Update the
// output buffer pointer and the space remaining.
//
if(ulIdx > ulSize)
{
strncpy(pcBuf, pcStr, ulSize);
pcBuf += ulSize;
ulSize = 0;
}
else
{
strncpy(pcBuf, pcStr, ulIdx);
pcBuf += ulIdx;
ulSize -= ulIdx;
}
//
// Update the conversion count. This will be the number of
// characters that should have been written, even if there
// was not room in the buffer.
//
iConvertCount += ulIdx;
//
//
// This command has been handled.
//
break;
}
//
// Handle the %u command.
//
case 'u':
{
//
// Get the value from the varargs.
//
ulValue = va_arg(vaArgP, unsigned long);
//
// Set the base to 10.
//
ulBase = 10;
//
// Convert the value to ASCII.
//
goto convert;
}
//
// Handle the %x and %X commands. Note that they are treated
// identically; i.e. %X will use lower case letters for a-f
// instead of the upper case letters is should use.
//
case 'x':
case 'X':
{
//
// Get the value from the varargs.
//
ulValue = va_arg(vaArgP, unsigned long);
//
// Set the base to 16.
//
ulBase = 16;
//
// Determine the number of digits in the string version of
// the value.
//
convert:
for(ulIdx = 1;
(((ulIdx * ulBase) <= ulValue) &&
(((ulIdx * ulBase) / ulBase) == ulIdx));
ulIdx *= ulBase, ulCount--)
{
}
//
// Provide additional padding at the beginning of the
// string conversion if needed.
//
if((ulCount > 1) && (ulCount < 16))
{
for(ulCount--; ulCount; ulCount--)
{
//
// Copy the character to the output buffer if
// there is room.
//
if(ulSize != 0)
{
*pcBuf++ = cFill;
ulSize--;
}
//
// Update the conversion count.
//
iConvertCount++;
}
}
//
// Convert the value into a string.
//
for(; ulIdx; ulIdx /= ulBase)
{
//
// Copy the character to the output buffer if
// there is room.
//
if(ulSize != 0)
{
*pcBuf++ = g_pcHex[(ulValue / ulIdx) % ulBase];
ulSize--;
}
//
// Update the conversion count.
//
iConvertCount++;
}
//
// This command has been handled.
//
break;
}
//
// Handle the %% command.
//
case '%':
{
//
// Simply write a single %.
//
if(ulSize != 0)
{
*pcBuf++ = pcString[-1];
ulSize--;
}
//
// Update the conversion count.
//
iConvertCount++;
//
// This command has been handled.
//
break;
}
//
// Handle all other commands.
//
default:
{
//
// Indicate an error.
//
if(ulSize >= 5)
{
strncpy(pcBuf, "ERROR", 5);
pcBuf += 5;
ulSize -= 5;
}
else
{
strncpy(pcBuf, "ERROR", ulSize);
pcBuf += ulSize;
ulSize = 0;
}
//
// Update the conversion count.
//
iConvertCount += 5;
//
// This command has been handled.
//
break;
}
}
}
}
//
// Null terminate the string in the buffer.
//
*pcBuf = 0;
return(iConvertCount);
}
//*****************************************************************************
//
//! A simple sprintf function supporting \%c, \%d, \%s, \%u, \%x, and \%X.
//!
//! \param pcBuf is the buffer where the converted string is stored.
//! \param pcString is the format string.
//! \param ... are the optional arguments, which depend on the contents of the
//! format string.
//!
//! This function is very similar to the C library <tt>sprintf()</tt> function.
//! Only the following formatting characters are supported:
//!
//! - \%c to print a character
//! - \%d to print a decimal value
//! - \%s to print a string
//! - \%u to print an unsigned decimal value
//! - \%x to print a hexadecimal value using lower case letters
//! - \%X to print a hexadecimal value using lower case letters (not upper case
//! letters as would typically be used)
//! - \%\% to print out a \% character
//!
//! For \%d, \%u, \%x, and \%X, an optional number may reside between the \%
//! and the format character, which specifies the minimum number of characters
//! to use for that value; if preceeded by a 0 then the extra characters will
//! be filled with zeros instead of spaces. For example, ``\%8d'' will use
//! eight characters to print the decimal value with spaces added to reach
//! eight; ``\%08d'' will use eight characters as well but will add zeros
//! instead of spaces.
//!
//! The type of the arguments after \b pcString must match the requirements of
//! the format string. For example, if an integer was passed where a string
//! was expected, an error of some kind will most likely occur.
//!
//! The caller must ensure that the buffer pcBuf is large enough to hold the
//! entire converted string, including the null termination character.
//!
//! \return The count of characters that were written to the output buffer,
//! not including the NULL termination character.
//
//*****************************************************************************
int
usprintf(char *pcBuf, const char *pcString, ...)
{
va_list vaArgP;
int iRet;
//
// Start the varargs processing.
//
va_start(vaArgP, pcString);
//
// Call vsnprintf to perform the conversion. Use a
// large number for the buffer size.
//
iRet = uvsnprintf(pcBuf, 0xffff, pcString, vaArgP);
//
// End the varargs processing.
//
va_end(vaArgP);
//
// Return the conversion count.
//
return(iRet);
}
//*****************************************************************************
//
//! A simple snprintf function supporting \%c, \%d, \%s, \%u, \%x, and \%X.
//!
//! \param pcBuf is the buffer where the converted string is stored.
//! \param ulSize is the size of the buffer.
//! \param pcString is the format string.
//! \param ... are the optional arguments, which depend on the contents of the
//! format string.
//!
//! This function is very similar to the C library <tt>sprintf()</tt> function.
//! Only the following formatting characters are supported:
//!
//! - \%c to print a character
//! - \%d to print a decimal value
//! - \%s to print a string
//! - \%u to print an unsigned decimal value
//! - \%x to print a hexadecimal value using lower case letters
//! - \%X to print a hexadecimal value using lower case letters (not upper case
//! letters as would typically be used)
//! - \%\% to print out a \% character
//!
//! For \%d, \%u, \%x, and \%X, an optional number may reside between the \%
//! and the format character, which specifies the minimum number of characters
//! to use for that value; if preceeded by a 0 then the extra characters will
//! be filled with zeros instead of spaces. For example, ``\%8d'' will use
//! eight characters to print the decimal value with spaces added to reach
//! eight; ``\%08d'' will use eight characters as well but will add zeros
//! instead of spaces.
//!
//! The type of the arguments after \b pcString must match the requirements of
//! the format string. For example, if an integer was passed where a string
//! was expected, an error of some kind will most likely occur.
//!
//! The function will copy at most \b ulSize - 1 characters into the
//! buffer \b pcBuf. One space is reserved in the buffer for the null
//! termination character.
//!
//! The function will return the number of characters that would be
//! converted as if there were no limit on the buffer size. Therefore
//! it is possible for the function to return a count that is greater than
//! the specified buffer size. If this happens, it means that the output
//! was truncated.
//!
//! \return the number of characters that were to be stored, not including
//! the NULL termination character, regardless of space in the buffer.
//
//*****************************************************************************
int
usnprintf(char *pcBuf, unsigned long ulSize, const char *pcString, ...)
{
int iRet;
va_list vaArgP;
//
// Start the varargs processing.
//
va_start(vaArgP, pcString);
//
// Call vsnprintf to perform the conversion.
//
iRet = uvsnprintf(pcBuf, ulSize, pcString, vaArgP);
//
// End the varargs processing.
//
va_end(vaArgP);
//
// Return the conversion count.
//
return(iRet);
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/ustdlib.c | C | oos | 22,782 |
//*****************************************************************************
//
// debug.h - Macros for assisting debug of the driver library.
//
// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DEBUG_H__
#define __DEBUG_H__
//*****************************************************************************
//
// Prototype for the function that is called when an invalid argument is passed
// to an API. This is only used when doing a DEBUG build.
//
//*****************************************************************************
extern void __error__(char *pcFilename, unsigned long ulLine);
//*****************************************************************************
//
// The ASSERT macro, which does the actual assertion checking. Typically, this
// will be for procedure arguments.
//
//*****************************************************************************
#ifdef DEBUG
#define ASSERT(expr) { \
if(!(expr)) \
{ \
__error__(__FILE__, __LINE__); \
} \
}
#else
#define ASSERT(expr)
#endif
#endif // __DEBUG_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/debug.h | C | oos | 2,525 |
//*****************************************************************************
//
// ssi.h - Prototypes for the Synchronous Serial Interface Driver.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __SSI_H__
#define __SSI_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear
// as the ulIntFlags parameter, and returned by SSIIntStatus.
//
//*****************************************************************************
#define SSI_TXFF 0x00000008 // TX FIFO half empty or less
#define SSI_RXFF 0x00000004 // RX FIFO half full or less
#define SSI_RXTO 0x00000002 // RX timeout
#define SSI_RXOR 0x00000001 // RX overrun
//*****************************************************************************
//
// Values that can be passed to SSIConfigSetExpClk.
//
//*****************************************************************************
#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0
#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1
#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0
#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1
#define SSI_FRF_TI 0x00000010 // TI frame format
#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format
#define SSI_MODE_MASTER 0x00000000 // SSI master
#define SSI_MODE_SLAVE 0x00000001 // SSI slave
#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled
//*****************************************************************************
//
// Values that can be passed to SSIDMAEnable() and SSIDMADisable().
//
//*****************************************************************************
#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit
#define SSI_DMA_RX 0x00000001 // Enable DMA for receive
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk,
unsigned long ulProtocol, unsigned long ulMode,
unsigned long ulBitRate,
unsigned long ulDataWidth);
extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData);
extern long SSIDataGetNonBlocking(unsigned long ulBase,
unsigned long *pulData);
extern void SSIDataPut(unsigned long ulBase, unsigned long ulData);
extern long SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData);
extern void SSIDisable(unsigned long ulBase);
extern void SSIEnable(unsigned long ulBase);
extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void SSIIntUnregister(unsigned long ulBase);
extern void SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
extern void SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
//*****************************************************************************
//
// Several SSI APIs have been renamed, with the original function name being
// deprecated. These defines provide backward compatibility.
//
//*****************************************************************************
#ifndef DEPRECATED
#include "sysctl.h"
#define SSIConfig(a, b, c, d, e) \
SSIConfigSetExpClk(a, SysCtlClockGet(), b, c, d, e)
#define SSIDataNonBlockingGet(a, b) \
SSIDataGetNonBlocking(a, b)
#define SSIDataNonBlockingPut(a, b) \
SSIDataPutNonBlocking(a, b)
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __SSI_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/ssi.h | C | oos | 6,016 |
//*****************************************************************************
//
// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_I2C_H__
#define __HW_I2C_H__
//*****************************************************************************
//
// The following are defines for the offsets between the I2C master and slave
// registers.
//
//*****************************************************************************
#define I2C_O_MSA 0x00000000 // I2C Master Slave Address
#define I2C_O_SOAR 0x00000000 // I2C Slave Own Address
#define I2C_O_SCSR 0x00000004 // I2C Slave Control/Status
#define I2C_O_MCS 0x00000004 // I2C Master Control/Status
#define I2C_O_SDR 0x00000008 // I2C Slave Data
#define I2C_O_MDR 0x00000008 // I2C Master Data
#define I2C_O_MTPR 0x0000000C // I2C Master Timer Period
#define I2C_O_SIMR 0x0000000C // I2C Slave Interrupt Mask
#define I2C_O_SRIS 0x00000010 // I2C Slave Raw Interrupt Status
#define I2C_O_MIMR 0x00000010 // I2C Master Interrupt Mask
#define I2C_O_MRIS 0x00000014 // I2C Master Raw Interrupt Status
#define I2C_O_SMIS 0x00000014 // I2C Slave Masked Interrupt
// Status
#define I2C_O_SICR 0x00000018 // I2C Slave Interrupt Clear
#define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt
// Status
#define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear
#define I2C_O_MCR 0x00000020 // I2C Master Configuration
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MSA register.
//
//*****************************************************************************
#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address.
#define I2C_MSA_RS 0x00000001 // Receive not Send
#define I2C_MSA_SA_S 1
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SOAR register.
//
//*****************************************************************************
#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address.
#define I2C_SOAR_OAR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SCSR register.
//
//*****************************************************************************
#define I2C_SCSR_FBR 0x00000004 // First Byte Received.
#define I2C_SCSR_TREQ 0x00000002 // Transmit Request.
#define I2C_SCSR_DA 0x00000001 // Device Active.
#define I2C_SCSR_RREQ 0x00000001 // Receive Request.
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MCS register.
//
//*****************************************************************************
#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy.
#define I2C_MCS_IDLE 0x00000020 // I2C Idle.
#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost.
#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable.
#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data.
#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address.
#define I2C_MCS_STOP 0x00000004 // Generate STOP.
#define I2C_MCS_START 0x00000002 // Generate START.
#define I2C_MCS_ERROR 0x00000002 // Error.
#define I2C_MCS_RUN 0x00000001 // I2C Master Enable.
#define I2C_MCS_BUSY 0x00000001 // I2C Busy.
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SDR register.
//
//*****************************************************************************
#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer.
#define I2C_SDR_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MDR register.
//
//*****************************************************************************
#define I2C_MDR_DATA_M 0x000000FF // Data Transferred.
#define I2C_MDR_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MTPR register.
//
//*****************************************************************************
#define I2C_MTPR_TPR_M 0x000000FF // SCL Clock Period.
#define I2C_MTPR_TPR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SIMR register.
//
//*****************************************************************************
#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask.
#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask.
#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask.
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SRIS register.
//
//*****************************************************************************
#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt
// Status.
#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt
// Status.
#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MIMR register.
//
//*****************************************************************************
#define I2C_MIMR_IM 0x00000001 // Interrupt Mask.
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MRIS register.
//
//*****************************************************************************
#define I2C_MRIS_RIS 0x00000001 // Raw Interrupt Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SMIS register.
//
//*****************************************************************************
#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt
// Status.
#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt
// Status.
#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SICR register.
//
//*****************************************************************************
#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear.
#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear.
#define I2C_SICR_DATAIC 0x00000001 // Data Clear Interrupt.
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MMIS register.
//
//*****************************************************************************
#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MICR register.
//
//*****************************************************************************
#define I2C_MICR_IC 0x00000001 // Interrupt Clear.
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MCR register.
//
//*****************************************************************************
#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable.
#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable.
#define I2C_MCR_LPBK 0x00000001 // I2C Loopback.
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the offsets between the I2C master
// and slave registers.
//
//*****************************************************************************
#define I2C_O_SLAVE 0x00000800 // Offset from master to slave
//*****************************************************************************
//
// The following are deprecated defines for the I2C master register offsets.
//
//*****************************************************************************
#define I2C_MASTER_O_SA 0x00000000 // Slave address register
#define I2C_MASTER_O_CS 0x00000004 // Control and Status register
#define I2C_MASTER_O_DR 0x00000008 // Data register
#define I2C_MASTER_O_TPR 0x0000000C // Timer period register
#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register
#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register
#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg
#define I2C_MASTER_O_MICR 0x0000001C // Interrupt clear register
#define I2C_MASTER_O_CR 0x00000020 // Configuration register
//*****************************************************************************
//
// The following are deprecated defines for the I2C slave register offsets.
//
//*****************************************************************************
#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register
#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg
#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register
#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register
#define I2C_SLAVE_O_DR 0x00000008 // Data register
#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register
#define I2C_SLAVE_O_OAR 0x00000000 // Own address register
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C master
// slave address register.
//
//*****************************************************************************
#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address
#define I2C_MASTER_SA_RS 0x00000001 // Receive/send
#define I2C_MASTER_SA_SA_SHIFT 1
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Master
// Control and Status register.
//
//*****************************************************************************
#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy
#define I2C_MASTER_CS_IDLE 0x00000020 // Idle
#define I2C_MASTER_CS_ERR_MASK 0x0000001C
#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data
#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred
#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged
#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged
#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration
#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde
#define I2C_MASTER_CS_STOP 0x00000004 // Stop
#define I2C_MASTER_CS_START 0x00000002 // Start
#define I2C_MASTER_CS_RUN 0x00000001 // Run
//*****************************************************************************
//
// The following are deprecated defines for the values used in determining the
// contents of the I2C Master Timer Period register.
//
//*****************************************************************************
#define I2C_SCL_FAST 400000 // SCL fast frequency
#define I2C_SCL_STANDARD 100000 // SCL standard frequency
#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period
#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period
#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Master
// Interrupt Mask register.
//
//*****************************************************************************
#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Master
// Raw Interrupt Status register.
//
//*****************************************************************************
#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Master
// Masked Interrupt Status register.
//
//*****************************************************************************
#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Master
// Interrupt Clear register.
//
//*****************************************************************************
#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Master
// Configuration register.
//
//*****************************************************************************
#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable
#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable
#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Slave Own
// Address register.
//
//*****************************************************************************
#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Slave
// Control/Status register.
//
//*****************************************************************************
#define I2C_SLAVE_CSR_FBR 0x00000004 // First byte received from master
#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received
#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device
#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Slave
// Interrupt Mask register.
//
//*****************************************************************************
#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Slave Raw
// Interrupt Status register.
//
//*****************************************************************************
#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Slave
// Masked Interrupt Status register.
//
//*****************************************************************************
#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Slave
// Interrupt Clear register.
//
//*****************************************************************************
#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C_O_SIMR
// register.
//
//*****************************************************************************
#define I2C_SIMR_IM 0x00000001 // Interrupt Mask.
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C_O_SRIS
// register.
//
//*****************************************************************************
#define I2C_SRIS_RIS 0x00000001 // Raw Interrupt Status.
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C_O_SMIS
// register.
//
//*****************************************************************************
#define I2C_SMIS_MIS 0x00000001 // Masked Interrupt Status.
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C_O_SICR
// register.
//
//*****************************************************************************
#define I2C_SICR_IC 0x00000001 // Clear Interrupt.
#endif
#endif // __HW_I2C_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/hw_i2c.h | C | oos | 20,101 |
//*****************************************************************************
//
// hw_usb.h - Macros for use in accessing the USB registers.
//
// Copyright (c) 2007-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_USB_H__
#define __HW_USB_H__
//*****************************************************************************
//
// The following are defines for the Univeral Serial Bus (USB) Controller
// offsets.
//
//*****************************************************************************
#define USB_O_FADDR 0x00000000 // USB Device Functional Address
#define USB_O_POWER 0x00000001 // USB Power
#define USB_O_TXIS 0x00000002 // USB Transmit Interrupt Status
#define USB_O_RXIS 0x00000004 // USB Receive Interrupt Status
#define USB_O_TXIE 0x00000006 // USB Transmit Interrupt Enable
#define USB_O_RXIE 0x00000008 // USB Receive Interrupt Enable
#define USB_O_IS 0x0000000A // USB General Interrupt Status
#define USB_O_IE 0x0000000B // USB Interrupt Enable
#define USB_O_FRAME 0x0000000C // USB Frame Value
#define USB_O_EPIDX 0x0000000E // USB Endpoint Index
#define USB_O_TEST 0x0000000F // USB Test Mode
#define USB_O_FIFO0 0x00000020 // USB FIFO Endpoint 0
#define USB_O_FIFO1 0x00000024 // USB FIFO Endpoint 1
#define USB_O_FIFO2 0x00000028 // USB FIFO Endpoint 2
#define USB_O_FIFO3 0x0000002C // USB FIFO Endpoint 3
#define USB_O_DEVCTL 0x00000060 // USB Device Control
#define USB_O_TXFIFOSZ 0x00000062 // USB Transmit Dynamic FIFO Sizing
#define USB_O_RXFIFOSZ 0x00000063 // USB Receive Dynamic FIFO Sizing
#define USB_O_TXFIFOADD 0x00000064 // USB Transmit FIFO Start Address
#define USB_O_RXFIFOADD 0x00000066 // USB Receive FIFO Start Address
#define USB_O_CONTIM 0x0000007A // USB Connect Timing
#define USB_O_VPLEN 0x0000007B // USB OTG VBus Pulse Timing
#define USB_O_FSEOF 0x0000007D // USB Full-Speed Last Transaction
// to End of Frame Timing
#define USB_O_LSEOF 0x0000007E // USB Low-Speed Last Transaction
// to End of Frame Timing
#define USB_O_TXFUNCADDR0 0x00000080 // USB Transmit Functional Address
// Endpoint 0
#define USB_O_TXHUBADDR0 0x00000082 // USB Transmit Hub Address
// Endpoint 0
#define USB_O_TXHUBPORT0 0x00000083 // USB Transmit Hub Port Endpoint 0
#define USB_O_TXFUNCADDR1 0x00000088 // USB Transmit Functional Address
// Endpoint 1
#define USB_O_TXHUBADDR1 0x0000008A // USB Transmit Hub Address
// Endpoint 1
#define USB_O_TXHUBPORT1 0x0000008B // USB Transmit Hub Port Endpoint 1
#define USB_O_RXFUNCADDR1 0x0000008C // USB Receive Functional Address
// Endpoint 1
#define USB_O_RXHUBADDR1 0x0000008E // USB Receive Hub Address Endpoint
// 1
#define USB_O_RXHUBPORT1 0x0000008F // USB Receive Hub Port Endpoint 1
#define USB_O_TXFUNCADDR2 0x00000090 // USB Transmit Functional Address
// Endpoint 2
#define USB_O_TXHUBADDR2 0x00000092 // USB Transmit Hub Address
// Endpoint 2
#define USB_O_TXHUBPORT2 0x00000093 // USB Transmit Hub Port Endpoint 2
#define USB_O_RXFUNCADDR2 0x00000094 // USB Receive Functional Address
// Endpoint 2
#define USB_O_RXHUBADDR2 0x00000096 // USB Receive Hub Address Endpoint
// 2
#define USB_O_RXHUBPORT2 0x00000097 // USB Receive Hub Port Endpoint 2
#define USB_O_TXFUNCADDR3 0x00000098 // USB Transmit Functional Address
// Endpoint 3
#define USB_O_TXHUBADDR3 0x0000009A // USB Transmit Hub Address
// Endpoint 3
#define USB_O_TXHUBPORT3 0x0000009B // USB Transmit Hub Port Endpoint 3
#define USB_O_RXFUNCADDR3 0x0000009C // USB Receive Functional Address
// Endpoint 3
#define USB_O_RXHUBADDR3 0x0000009E // USB Receive Hub Address Endpoint
// 3
#define USB_O_RXHUBPORT3 0x0000009F // USB Receive Hub Port Endpoint 3
#define USB_O_CSRL0 0x00000102 // USB Control and Status Endpoint
// 0 Low
#define USB_O_CSRH0 0x00000103 // USB Control and Status Endpoint
// 0 High
#define USB_O_COUNT0 0x00000108 // USB Receive Byte Count Endpoint
// 0
#define USB_O_TYPE0 0x0000010A // USB Type Endpoint 0
#define USB_O_NAKLMT 0x0000010B // USB NAK Limit
#define USB_O_TXMAXP1 0x00000110 // USB Maximum Transmit Data
// Endpoint 1
#define USB_O_TXCSRL1 0x00000112 // USB Transmit Control and Status
// Endpoint 1 Low
#define USB_O_TXCSRH1 0x00000113 // USB Transmit Control and Status
// Endpoint 1 High
#define USB_O_RXMAXP1 0x00000114 // USB Maximum Receive Data
// Endpoint 1
#define USB_O_RXCSRL1 0x00000116 // USB Receive Control and Status
// Endpoint 1 Low
#define USB_O_RXCSRH1 0x00000117 // USB Receive Control and Status
// Endpoint 1 High
#define USB_O_RXCOUNT1 0x00000118 // USB Receive Byte Count Endpoint
// 1
#define USB_O_TXTYPE1 0x0000011A // USB Host Transmit Configure Type
// Endpoint 1
#define USB_O_TXINTERVAL1 0x0000011B // USB Host Transmit Interval
// Endpoint 1
#define USB_O_RXTYPE1 0x0000011C // USB Host Configure Receive Type
// Endpoint 1
#define USB_O_RXINTERVAL1 0x0000011D // USB Host Receive Polling
// Interval Endpoint 1
#define USB_O_TXMAXP2 0x00000120 // USB Maximum Transmit Data
// Endpoint 2
#define USB_O_TXCSRL2 0x00000122 // USB Transmit Control and Status
// Endpoint 2 Low
#define USB_O_TXCSRH2 0x00000123 // USB Transmit Control and Status
// Endpoint 2 High
#define USB_O_RXMAXP2 0x00000124 // USB Maximum Receive Data
// Endpoint 2
#define USB_O_RXCSRL2 0x00000126 // USB Receive Control and Status
// Endpoint 2 Low
#define USB_O_RXCSRH2 0x00000127 // USB Receive Control and Status
// Endpoint 2 High
#define USB_O_RXCOUNT2 0x00000128 // USB Receive Byte Count Endpoint
// 2
#define USB_O_TXTYPE2 0x0000012A // USB Host Transmit Configure Type
// Endpoint 2
#define USB_O_TXINTERVAL2 0x0000012B // USB Host Transmit Interval
// Endpoint 2
#define USB_O_RXTYPE2 0x0000012C // USB Host Configure Receive Type
// Endpoint 2
#define USB_O_RXINTERVAL2 0x0000012D // USB Host Receive Polling
// Interval Endpoint 2
#define USB_O_TXMAXP3 0x00000130 // USB Maximum Transmit Data
// Endpoint 3
#define USB_O_TXCSRL3 0x00000132 // USB Transmit Control and Status
// Endpoint 3 Low
#define USB_O_TXCSRH3 0x00000133 // USB Transmit Control and Status
// Endpoint 3 High
#define USB_O_RXMAXP3 0x00000134 // USB Maximum Receive Data
// Endpoint 3
#define USB_O_RXCSRL3 0x00000136 // USB Receive Control and Status
// Endpoint 3 Low
#define USB_O_RXCSRH3 0x00000137 // USB Receive Control and Status
// Endpoint 3 High
#define USB_O_RXCOUNT3 0x00000138 // USB Receive Byte Count Endpoint
// 3
#define USB_O_TXTYPE3 0x0000013A // USB Host Transmit Configure Type
// Endpoint 3
#define USB_O_TXINTERVAL3 0x0000013B // USB Host Transmit Interval
// Endpoint 3
#define USB_O_RXTYPE3 0x0000013C // USB Host Configure Receive Type
// Endpoint 3
#define USB_O_RXINTERVAL3 0x0000013D // USB Host Receive Polling
// Interval Endpoint 3
#define USB_O_RQPKTCOUNT1 0x00000304 // USB Request Packet Count in
// Block Transfer Endpoint 1
#define USB_O_RQPKTCOUNT2 0x00000308 // USB Request Packet Count in
// Block Transfer Endpoint 2
#define USB_O_RQPKTCOUNT3 0x0000030C // USB Request Packet Count in
// Block Transfer Endpoint 3
#define USB_O_RXDPKTBUFDIS 0x00000340 // USB Receive Double Packet Buffer
// Disable
#define USB_O_TXDPKTBUFDIS 0x00000342 // USB Transmit Double Packet
// Buffer Disable
#define USB_O_EPC 0x00000400 // USB External Power Control
#define USB_O_EPCRIS 0x00000404 // USB External Power Control Raw
// Interrupt Status
#define USB_O_EPCIM 0x00000408 // USB External Power Control
// Interrupt Mask
#define USB_O_EPCISC 0x0000040C // USB External Power Control
// Interrupt Status and Clear
#define USB_O_DRRIS 0x00000410 // USB Device Resume Raw Interrupt
// Status
#define USB_O_DRIM 0x00000414 // USB Device Resume Interrupt Mask
#define USB_O_DRISC 0x00000418 // USB Device Resume Interrupt
// Status and Clear
#define USB_O_GPCS 0x0000041C // USB General-Purpose Control and
// Status
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_FADDR register.
//
//*****************************************************************************
#define USB_FADDR_M 0x0000007F // Function Address.
#define USB_FADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_POWER register.
//
//*****************************************************************************
#define USB_POWER_ISOUP 0x00000080 // ISO Update.
#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect.
#define USB_POWER_RESET 0x00000008 // Reset.
#define USB_POWER_RESUME 0x00000004 // Resume Signaling.
#define USB_POWER_SUSPEND 0x00000002 // Suspend Mode.
#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXIS register.
//
//*****************************************************************************
#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt.
#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt.
#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt.
#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXIS register.
//
//*****************************************************************************
#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt.
#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt.
#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXIE register.
//
//*****************************************************************************
#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable.
#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable.
#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable.
#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt
// Enable.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXIE register.
//
//*****************************************************************************
#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable.
#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable.
#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_IS register.
//
//*****************************************************************************
#define USB_IS_VBUSERR 0x00000080 // VBus Error.
#define USB_IS_SESREQ 0x00000040 // Session Request.
#define USB_IS_DISCON 0x00000020 // Session Disconnect.
#define USB_IS_CONN 0x00000010 // Session Connect.
#define USB_IS_SOF 0x00000008 // Start of Frame.
#define USB_IS_BABBLE 0x00000004 // Babble Detected.
#define USB_IS_RESET 0x00000004 // Reset Signal Detected.
#define USB_IS_RESUME 0x00000002 // Resume Signal Detected.
#define USB_IS_SUSPEND 0x00000001 // Suspend Signal Detected.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_IE register.
//
//*****************************************************************************
#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt.
#define USB_IE_SESREQ 0x00000040 // Enable Session Request
// Interrupt.
#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt.
#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt.
#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt.
#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt.
#define USB_IE_RESET 0x00000004 // Enable Reset Interrupt.
#define USB_IE_RESUME 0x00000002 // Enable Resume Interrupt.
#define USB_IE_SUSPND 0x00000001 // Enable Suspend Interrupt.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_FRAME register.
//
//*****************************************************************************
#define USB_FRAME_M 0x000007FF // Frame Number.
#define USB_FRAME_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_EPIDX register.
//
//*****************************************************************************
#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index.
#define USB_EPIDX_EPIDX_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TEST register.
//
//*****************************************************************************
#define USB_TEST_FORCEH 0x00000080 // Force Host Mode.
#define USB_TEST_FIFOACC 0x00000040 // FIFO Access.
#define USB_TEST_FORCEFS 0x00000020 // Force Full Speed.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_FIFO0 register.
//
//*****************************************************************************
#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data.
#define USB_FIFO0_EPDATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_FIFO1 register.
//
//*****************************************************************************
#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data.
#define USB_FIFO1_EPDATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_FIFO2 register.
//
//*****************************************************************************
#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data.
#define USB_FIFO2_EPDATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_FIFO3 register.
//
//*****************************************************************************
#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data.
#define USB_FIFO3_EPDATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_DEVCTL register.
//
//*****************************************************************************
#define USB_DEVCTL_DEV 0x00000080 // Device Mode.
#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected.
#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected.
#define USB_DEVCTL_VBUS_M 0x00000018 // VBus Level.
#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd
#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid
#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBusValid
#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBusValid
#define USB_DEVCTL_HOST 0x00000004 // Host Mode.
#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request.
#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXFIFOSZ register.
//
//*****************************************************************************
#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support.
#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size.
#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8
#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16
#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32
#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64
#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128
#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256
#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512
#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024
#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXFIFOSZ register.
//
//*****************************************************************************
#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support.
#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size.
#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8
#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16
#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32
#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64
#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128
#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256
#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512
#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024
#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXFIFOADD
// register.
//
//*****************************************************************************
#define USB_TXFIFOADD_ADDR_M 0x00001FFF // Transmit/Receive Start Address.
#define USB_TXFIFOADD_ADDR_0 0x00000000 // 0
#define USB_TXFIFOADD_ADDR_8 0x00000001 // 8
#define USB_TXFIFOADD_ADDR_16 0x00000002 // 16
#define USB_TXFIFOADD_ADDR_32 0x00000003 // 32
#define USB_TXFIFOADD_ADDR_64 0x00000004 // 64
#define USB_TXFIFOADD_ADDR_128 0x00000005 // 128
#define USB_TXFIFOADD_ADDR_256 0x00000006 // 256
#define USB_TXFIFOADD_ADDR_512 0x00000007 // 512
#define USB_TXFIFOADD_ADDR_1024 0x00000008 // 1024
#define USB_TXFIFOADD_ADDR_2048 0x00000009 // 2048
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXFIFOADD
// register.
//
//*****************************************************************************
#define USB_RXFIFOADD_ADDR_M 0x00001FFF // Transmit/Receive Start Address.
#define USB_RXFIFOADD_ADDR_0 0x00000000 // 0
#define USB_RXFIFOADD_ADDR_8 0x00000001 // 8
#define USB_RXFIFOADD_ADDR_16 0x00000002 // 16
#define USB_RXFIFOADD_ADDR_32 0x00000003 // 32
#define USB_RXFIFOADD_ADDR_64 0x00000004 // 64
#define USB_RXFIFOADD_ADDR_128 0x00000005 // 128
#define USB_RXFIFOADD_ADDR_256 0x00000006 // 256
#define USB_RXFIFOADD_ADDR_512 0x00000007 // 512
#define USB_RXFIFOADD_ADDR_1024 0x00000008 // 1024
#define USB_RXFIFOADD_ADDR_2048 0x00000009 // 2048
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_CONTIM register.
//
//*****************************************************************************
#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait.
#define USB_CONTIM_WTID_M 0x0000000F // Wait ID.
#define USB_CONTIM_WTCON_S 4
#define USB_CONTIM_WTID_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_FSEOF register.
//
//*****************************************************************************
#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap.
#define USB_FSEOF_FSEOFG_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_LSEOF register.
//
//*****************************************************************************
#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap.
#define USB_LSEOF_LSEOFG_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXFUNCADDR0
// register.
//
//*****************************************************************************
#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address.
#define USB_TXFUNCADDR0_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBADDR0
// register.
//
//*****************************************************************************
#define USB_TXHUBADDR0_MULTTRAN 0x00000080 // Multiple Translators.
#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address.
#define USB_TXHUBADDR0_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBPORT0
// register.
//
//*****************************************************************************
#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port.
#define USB_TXHUBPORT0_PORT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXFUNCADDR1
// register.
//
//*****************************************************************************
#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address.
#define USB_TXFUNCADDR1_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBADDR1
// register.
//
//*****************************************************************************
#define USB_TXHUBADDR1_MULTTRAN 0x00000080 // Multiple Translators.
#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address.
#define USB_TXHUBADDR1_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBPORT1
// register.
//
//*****************************************************************************
#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port.
#define USB_TXHUBPORT1_PORT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXFUNCADDR1
// register.
//
//*****************************************************************************
#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address.
#define USB_RXFUNCADDR1_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBADDR1
// register.
//
//*****************************************************************************
#define USB_RXHUBADDR1_MULTTRAN 0x00000080 // Multiple Translators.
#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address.
#define USB_RXHUBADDR1_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBPORT1
// register.
//
//*****************************************************************************
#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port.
#define USB_RXHUBPORT1_PORT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXFUNCADDR2
// register.
//
//*****************************************************************************
#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address.
#define USB_TXFUNCADDR2_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBADDR2
// register.
//
//*****************************************************************************
#define USB_TXHUBADDR2_MULTTRAN 0x00000080 // Multiple Translators.
#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address.
#define USB_TXHUBADDR2_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBPORT2
// register.
//
//*****************************************************************************
#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port.
#define USB_TXHUBPORT2_PORT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXFUNCADDR2
// register.
//
//*****************************************************************************
#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address.
#define USB_RXFUNCADDR2_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBADDR2
// register.
//
//*****************************************************************************
#define USB_RXHUBADDR2_MULTTRAN 0x00000080 // Multiple Translators.
#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address.
#define USB_RXHUBADDR2_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBPORT2
// register.
//
//*****************************************************************************
#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port.
#define USB_RXHUBPORT2_PORT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXFUNCADDR3
// register.
//
//*****************************************************************************
#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address.
#define USB_TXFUNCADDR3_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBADDR3
// register.
//
//*****************************************************************************
#define USB_TXHUBADDR3_MULTTRAN 0x00000080 // Multiple Translators.
#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address.
#define USB_TXHUBADDR3_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBPORT3
// register.
//
//*****************************************************************************
#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port.
#define USB_TXHUBPORT3_PORT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXFUNCADDR3
// register.
//
//*****************************************************************************
#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address.
#define USB_RXFUNCADDR3_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBADDR3
// register.
//
//*****************************************************************************
#define USB_RXHUBADDR3_MULTTRAN 0x00000080 // Multiple Translators.
#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address.
#define USB_RXHUBADDR3_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBPORT3
// register.
//
//*****************************************************************************
#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port.
#define USB_RXHUBPORT3_PORT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_CSRL0 register.
//
//*****************************************************************************
#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout.
#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear.
#define USB_CSRL0_STATUS 0x00000040 // Status Packet.
#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear.
#define USB_CSRL0_REQPKT 0x00000020 // Request Packet.
#define USB_CSRL0_STALL 0x00000020 // Send Stall.
#define USB_CSRL0_SETEND 0x00000010 // Setup End.
#define USB_CSRL0_ERROR 0x00000010 // Error.
#define USB_CSRL0_DATAEND 0x00000008 // Data End.
#define USB_CSRL0_SETUP 0x00000008 // Setup Packet.
#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled.
#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready.
#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_CSRH0 register.
//
//*****************************************************************************
#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable.
#define USB_CSRH0_DT 0x00000002 // Data Toggle.
#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_COUNT0 register.
//
//*****************************************************************************
#define USB_COUNT0_COUNT_M 0x0000007F // Count.
#define USB_COUNT0_COUNT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TYPE0 register.
//
//*****************************************************************************
#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed.
#define USB_TYPE0_SPEED_FULL 0x00000080 // Full
#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_NAKLMT register.
//
//*****************************************************************************
#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit.
#define USB_NAKLMT_NAKLMT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXMAXP1 register.
//
//*****************************************************************************
#define USB_TXMAXP1_MULT_M 0x0000F800 // Multiplier.
#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload.
#define USB_TXMAXP1_MULT_S 11
#define USB_TXMAXP1_MAXLOAD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRL1 register.
//
//*****************************************************************************
#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout
#define USB_TXCSRL1_INCTX 0x00000080 // Incomplete Transmit.
#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle.
#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled.
#define USB_TXCSRL1_STALL 0x00000010 // Send Stall.
#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet.
#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO.
#define USB_TXCSRL1_ERROR 0x00000004 // Error.
#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun.
#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty.
#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRH1 register.
//
//*****************************************************************************
#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set.
#define USB_TXCSRH1_ISO 0x00000040 // ISO.
#define USB_TXCSRH1_MODE 0x00000020 // Mode.
#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable.
#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle.
#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode.
#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable.
#define USB_TXCSRH1_DT 0x00000001 // Data Toggle.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXMAXP1 register.
//
//*****************************************************************************
#define USB_RXMAXP1_MULT_M 0x0000F800 // Multiplier.
#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload.
#define USB_RXMAXP1_MULT_S 11
#define USB_RXMAXP1_MAXLOAD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRL1 register.
//
//*****************************************************************************
#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle.
#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled.
#define USB_RXCSRL1_STALL 0x00000020 // Send Stall.
#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet.
#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO.
#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error.
#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout.
#define USB_RXCSRL1_OVER 0x00000004 // Overrun.
#define USB_RXCSRL1_ERROR 0x00000004 // Error.
#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full.
#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRH1 register.
//
//*****************************************************************************
#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear.
#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request.
#define USB_RXCSRH1_ISO 0x00000040 // ISO.
#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable.
#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET
#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error.
#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode.
#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable.
#define USB_RXCSRH1_DT 0x00000002 // Data Toggle.
#define USB_RXCSRH1_INCRX 0x00000001 // Incomplete Receive.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCOUNT1 register.
//
//*****************************************************************************
#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count.
#define USB_RXCOUNT1_COUNT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXTYPE1 register.
//
//*****************************************************************************
#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed.
#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default
#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full
#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low
#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol.
#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control
#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous
#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk
#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt
#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number.
#define USB_TXTYPE1_TEP_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXINTERVAL1
// register.
//
//*****************************************************************************
#define USB_TXINTERVAL1_NAKLMT_M \
0x000000FF // NAK Limit.
#define USB_TXINTERVAL1_TXPOLL_M \
0x000000FF // TX Polling
#define USB_TXINTERVAL1_TXPOLL_S \
0
#define USB_TXINTERVAL1_NAKLMT_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXTYPE1 register.
//
//*****************************************************************************
#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed.
#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default
#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full
#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low
#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol.
#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control
#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous
#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk
#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt
#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number.
#define USB_RXTYPE1_TEP_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXINTERVAL1
// register.
//
//*****************************************************************************
#define USB_RXINTERVAL1_TXPOLL_M \
0x000000FF // RX Polling
#define USB_RXINTERVAL1_NAKLMT_M \
0x000000FF // NAK Limit.
#define USB_RXINTERVAL1_TXPOLL_S \
0
#define USB_RXINTERVAL1_NAKLMT_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXMAXP2 register.
//
//*****************************************************************************
#define USB_TXMAXP2_MULT_M 0x0000F800 // Multiplier.
#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload.
#define USB_TXMAXP2_MULT_S 11
#define USB_TXMAXP2_MAXLOAD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRL2 register.
//
//*****************************************************************************
#define USB_TXCSRL2_INCTX 0x00000080 // Incomplete Transmit.
#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout
#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle.
#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled.
#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet.
#define USB_TXCSRL2_STALL 0x00000010 // Send Stall.
#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO.
#define USB_TXCSRL2_ERROR 0x00000004 // Error.
#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun.
#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty.
#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRH2 register.
//
//*****************************************************************************
#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set.
#define USB_TXCSRH2_ISO 0x00000040 // ISO.
#define USB_TXCSRH2_MODE 0x00000020 // Mode.
#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable.
#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle.
#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode.
#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable.
#define USB_TXCSRH2_DT 0x00000001 // Data Toggle.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXMAXP2 register.
//
//*****************************************************************************
#define USB_RXMAXP2_MULT_M 0x0000F800 // Multiplier.
#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload.
#define USB_RXMAXP2_MULT_S 11
#define USB_RXMAXP2_MAXLOAD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRL2 register.
//
//*****************************************************************************
#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle.
#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled.
#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet.
#define USB_RXCSRL2_STALL 0x00000020 // Send Stall.
#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO.
#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error.
#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout.
#define USB_RXCSRL2_ERROR 0x00000004 // Error.
#define USB_RXCSRL2_OVER 0x00000004 // Overrun.
#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full.
#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRH2 register.
//
//*****************************************************************************
#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear.
#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request.
#define USB_RXCSRH2_ISO 0x00000040 // ISO.
#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable.
#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET
#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error.
#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode.
#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable.
#define USB_RXCSRH2_DT 0x00000002 // Data Toggle.
#define USB_RXCSRH2_INCRX 0x00000001 // Incomplete Receive.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCOUNT2 register.
//
//*****************************************************************************
#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count.
#define USB_RXCOUNT2_COUNT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXTYPE2 register.
//
//*****************************************************************************
#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed.
#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default
#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full
#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low
#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol.
#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control
#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous
#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk
#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt
#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number.
#define USB_TXTYPE2_TEP_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXINTERVAL2
// register.
//
//*****************************************************************************
#define USB_TXINTERVAL2_TXPOLL_M \
0x000000FF // TX Polling
#define USB_TXINTERVAL2_NAKLMT_M \
0x000000FF // NAK Limit.
#define USB_TXINTERVAL2_NAKLMT_S \
0
#define USB_TXINTERVAL2_TXPOLL_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXTYPE2 register.
//
//*****************************************************************************
#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed.
#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default
#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full
#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low
#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol.
#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control
#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous
#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk
#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt
#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number.
#define USB_RXTYPE2_TEP_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXINTERVAL2
// register.
//
//*****************************************************************************
#define USB_RXINTERVAL2_TXPOLL_M \
0x000000FF // RX Polling
#define USB_RXINTERVAL2_NAKLMT_M \
0x000000FF // NAK Limit.
#define USB_RXINTERVAL2_TXPOLL_S \
0
#define USB_RXINTERVAL2_NAKLMT_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXMAXP3 register.
//
//*****************************************************************************
#define USB_TXMAXP3_MULT_M 0x0000F800 // Multiplier.
#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload.
#define USB_TXMAXP3_MULT_S 11
#define USB_TXMAXP3_MAXLOAD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRL3 register.
//
//*****************************************************************************
#define USB_TXCSRL3_INCTX 0x00000080 // Incomplete Transmit.
#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout
#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle.
#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled.
#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet.
#define USB_TXCSRL3_STALL 0x00000010 // Send Stall.
#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO.
#define USB_TXCSRL3_ERROR 0x00000004 // Error.
#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun.
#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty.
#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRH3 register.
//
//*****************************************************************************
#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set.
#define USB_TXCSRH3_ISO 0x00000040 // ISO.
#define USB_TXCSRH3_MODE 0x00000020 // Mode.
#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable.
#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle.
#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode.
#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable.
#define USB_TXCSRH3_DT 0x00000001 // Data Toggle.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXMAXP3 register.
//
//*****************************************************************************
#define USB_RXMAXP3_MULT_M 0x0000F800 // Multiplier.
#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload.
#define USB_RXMAXP3_MULT_S 11
#define USB_RXMAXP3_MAXLOAD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRL3 register.
//
//*****************************************************************************
#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle.
#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled.
#define USB_RXCSRL3_STALL 0x00000020 // Send Stall.
#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet.
#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO.
#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error.
#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout.
#define USB_RXCSRL3_ERROR 0x00000004 // Error.
#define USB_RXCSRL3_OVER 0x00000004 // Overrun.
#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full.
#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRH3 register.
//
//*****************************************************************************
#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear.
#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request.
#define USB_RXCSRH3_ISO 0x00000040 // ISO.
#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable.
#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET
#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error.
#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode.
#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable.
#define USB_RXCSRH3_DT 0x00000002 // Data Toggle.
#define USB_RXCSRH3_INCRX 0x00000001 // Incomplete Receive.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCOUNT3 register.
//
//*****************************************************************************
#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count.
#define USB_RXCOUNT3_COUNT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXTYPE3 register.
//
//*****************************************************************************
#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed.
#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default
#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full
#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low
#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol.
#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control
#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous
#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk
#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt
#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number.
#define USB_TXTYPE3_TEP_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXINTERVAL3
// register.
//
//*****************************************************************************
#define USB_TXINTERVAL3_TXPOLL_M \
0x000000FF // TX Polling
#define USB_TXINTERVAL3_NAKLMT_M \
0x000000FF // NAK Limit.
#define USB_TXINTERVAL3_TXPOLL_S \
0
#define USB_TXINTERVAL3_NAKLMT_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXTYPE3 register.
//
//*****************************************************************************
#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed.
#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default
#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full
#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low
#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol.
#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control
#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous
#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk
#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt
#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number.
#define USB_RXTYPE3_TEP_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXINTERVAL3
// register.
//
//*****************************************************************************
#define USB_RXINTERVAL3_TXPOLL_M \
0x000000FF // RX Polling
#define USB_RXINTERVAL3_NAKLMT_M \
0x000000FF // NAK Limit.
#define USB_RXINTERVAL3_TXPOLL_S \
0
#define USB_RXINTERVAL3_NAKLMT_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1
// register.
//
//*****************************************************************************
#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count.
#define USB_RQPKTCOUNT1_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2
// register.
//
//*****************************************************************************
#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count.
#define USB_RQPKTCOUNT2_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3
// register.
//
//*****************************************************************************
#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count.
#define USB_RQPKTCOUNT3_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS
// register.
//
//*****************************************************************************
#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer
// Disable.
#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer
// Disable.
#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer
// Disable.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS
// register.
//
//*****************************************************************************
#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer
// Disable.
#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer
// Disable.
#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer
// Disable.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_EPC register.
//
//*****************************************************************************
#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action.
#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged
#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate
#define USB_EPC_PFLTACT_LOW 0x00000200 // Low
#define USB_EPC_PFLTACT_HIGH 0x00000300 // High
#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable.
#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense.
#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable.
#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable.
#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable
// Configuration.
#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low
#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High
#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low
#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_EPCRIS register.
//
//*****************************************************************************
#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt
// Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_EPCIM register.
//
//*****************************************************************************
#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_EPCISC register.
//
//*****************************************************************************
#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status
// and Clear.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_DRRIS register.
//
//*****************************************************************************
#define USB_DRRIS_RESUME 0x00000001 // Resume Interrupt Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_DRIM register.
//
//*****************************************************************************
#define USB_DRIM_RESUME 0x00000001 // Resume Interrupt Mask.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_DRISC register.
//
//*****************************************************************************
#define USB_DRISC_RESUME 0x00000001 // Resume Interrupt Status and
// Clear.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_GPCS register.
//
//*****************************************************************************
#define USB_GPCS_DEVMOD 0x00000001 // Device Mode.
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_VPLEN register.
//
//*****************************************************************************
#define USB_VPLEN_VPLEN_M 0x000000FF // VBus Pulse Length.
#define USB_VPLEN_VPLEN_S 0
#endif // __HW_USB_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/hw_usb.h | C | oos | 66,068 |
//*****************************************************************************
//
// hw_types.h - Common types and macros.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_TYPES_H__
#define __HW_TYPES_H__
//*****************************************************************************
//
// Define a boolean type, and values for true and false.
//
//*****************************************************************************
typedef unsigned char tBoolean;
#ifndef true
#define true 1
#endif
#ifndef false
#define false 0
#endif
//*****************************************************************************
//
// Macros for hardware access, both direct and via the bit-band region.
//
//*****************************************************************************
#define HWREG(x) \
(*((volatile unsigned long *)(x)))
#define HWREGH(x) \
(*((volatile unsigned short *)(x)))
#define HWREGB(x) \
(*((volatile unsigned char *)(x)))
#define HWREGBITW(x, b) \
HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
#define HWREGBITH(x, b) \
HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
#define HWREGBITB(x, b) \
HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
//*****************************************************************************
//
// Helper Macros for determining silicon revisions, etc.
//
// These macros will be used by Driverlib at "run-time" to create necessary
// conditional code blocks that will allow a single version of the Driverlib
// "binary" code to support multiple(all) Stellaris silicon revisions.
//
// It is expected that these macros will be used inside of a standard 'C'
// conditional block of code, e.g.
//
// if(CLASS_IS_SANDSTORM)
// {
// do some Sandstorm-class specific code here.
// }
//
// By default, these macros will be defined as run-time checks of the
// appropriate register(s) to allow creation of run-time conditional code
// blocks for a common DriverLib across the entire Stellaris family.
//
// However, if code-space optimization is required, these macros can be "hard-
// coded" for a specific version of Stellaris silicon. Many compilers will
// then detect the "hard-coded" conditionals, and appropriately optimize the
// code blocks, eliminating any "unreachable" code. This would result in
// a smaller Driverlib, thus producing a smaller final application size, but
// at the cost of limiting the Driverlib binary to a specific Stellaris
// silicon revision.
//
//*****************************************************************************
#ifndef CLASS_IS_SANDSTORM
#define CLASS_IS_SANDSTORM \
(((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_M) == SYSCTL_DID0_VER_0) || \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_SANDSTORM)))
#endif
#ifndef CLASS_IS_FURY
#define CLASS_IS_FURY \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_FURY))
#endif
#ifndef CLASS_IS_DUSTDEVIL
#define CLASS_IS_DUSTDEVIL \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_DUSTDEVIL))
#endif
#ifndef REVISION_IS_A0
#define REVISION_IS_A0 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
#endif
#ifndef REVISION_IS_A2
#define REVISION_IS_A2 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_2))
#endif
#ifndef REVISION_IS_C1
#define REVISION_IS_C1 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_1))
#endif
#ifndef REVISION_IS_C2
#define REVISION_IS_C2 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_2))
#endif
//*****************************************************************************
//
// Deprecated silicon class and revision detection macros.
//
//*****************************************************************************
#ifndef DEPRECATED
#define DEVICE_IS_SANDSTORM CLASS_IS_SANDSTORM
#define DEVICE_IS_FURY CLASS_IS_FURY
#define DEVICE_IS_REVA2 REVISION_IS_A2
#define DEVICE_IS_REVC1 REVISION_IS_C1
#define DEVICE_IS_REVC2 REVISION_IS_C2
#endif
#endif // __HW_TYPES_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/hw_types.h | C | oos | 6,842 |
//*****************************************************************************
//
// adc.h - ADC headers for using the ADC driver functions.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __ADC_H__
#define __ADC_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to ADCSequenceConfigure as the ulTrigger
// parameter.
//
//*****************************************************************************
#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event
#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event
#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event
#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event
#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event
#define ADC_TRIGGER_TIMER 0x00000005 // Timer event
#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event
#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event
#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event
#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event
//*****************************************************************************
//
// Values that can be passed to ADCSequenceStepConfigure as the ulConfig
// parameter.
//
//*****************************************************************************
#define ADC_CTL_TS 0x00000080 // Temperature sensor select
#define ADC_CTL_IE 0x00000040 // Interrupt enable
#define ADC_CTL_END 0x00000020 // Sequence end select
#define ADC_CTL_D 0x00000010 // Differential select
#define ADC_CTL_CH0 0x00000000 // Input channel 0
#define ADC_CTL_CH1 0x00000001 // Input channel 1
#define ADC_CTL_CH2 0x00000002 // Input channel 2
#define ADC_CTL_CH3 0x00000003 // Input channel 3
#define ADC_CTL_CH4 0x00000004 // Input channel 4
#define ADC_CTL_CH5 0x00000005 // Input channel 5
#define ADC_CTL_CH6 0x00000006 // Input channel 6
#define ADC_CTL_CH7 0x00000007 // Input channel 7
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,
void (*pfnHandler)(void));
extern void ADCIntUnregister(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum);
extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum);
extern unsigned long ADCIntStatus(unsigned long ulBase,
unsigned long ulSequenceNum,
tBoolean bMasked);
extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum);
extern void ADCSequenceEnable(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSequenceDisable(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSequenceConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulTrigger,
unsigned long ulPriority);
extern void ADCSequenceStepConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulStep,
unsigned long ulConfig);
extern long ADCSequenceOverflow(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSequenceOverflowClear(unsigned long ulBase,
unsigned long ulSequenceNum);
extern long ADCSequenceUnderflow(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSequenceUnderflowClear(unsigned long ulBase,
unsigned long ulSequenceNum);
extern long ADCSequenceDataGet(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long *pulBuffer);
extern void ADCProcessorTrigger(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSoftwareOversampleConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulFactor);
extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulStep,
unsigned long ulConfig);
extern void ADCSoftwareOversampleDataGet(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long *pulBuffer,
unsigned long ulCount);
extern void ADCHardwareOversampleConfigure(unsigned long ulBase,
unsigned long ulFactor);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __ADC_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/adc.h | C | oos | 7,258 |
//*****************************************************************************
//
// comp.h - Prototypes for the analog comparator driver.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __COMP_H__
#define __COMP_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to ComparatorConfigure() as the ulConfig
// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of
// the values may be selected and combined together with values from the other
// groups via a logical OR.
//
//*****************************************************************************
#define COMP_TRIG_NONE 0x00000000 // No ADC trigger
#define COMP_TRIG_HIGH 0x00000880 // Trigger when high
#define COMP_TRIG_LOW 0x00000800 // Trigger when low
#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge
#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge
#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges
#define COMP_INT_HIGH 0x00000010 // Interrupt when high
#define COMP_INT_LOW 0x00000000 // Interrupt when low
#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge
#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge
#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges
#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin
#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin
#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference
#ifndef DEPRECATED
#define COMP_OUTPUT_NONE 0x00000000 // No comparator output
#endif
#define COMP_OUTPUT_NORMAL 0x00000000 // Comparator output normal
#define COMP_OUTPUT_INVERT 0x00000002 // Comparator output inverted
//*****************************************************************************
//
// Values that can be passed to ComparatorSetRef() as the ulRef parameter.
//
//*****************************************************************************
#define COMP_REF_OFF 0x00000000 // Turn off the internal reference
#define COMP_REF_0V 0x00000300 // Internal reference of 0V
#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V
#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V
#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V
#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V
#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V
#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V
#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V
#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V
#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V
#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V
#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V
#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V
#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V
#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V
#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V
#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V
#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V
#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V
#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V
#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V
#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V
#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V
#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V
#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V
#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V
#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V
#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
unsigned long ulConfig);
extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef);
extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp);
extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,
void (*pfnHandler)(void));
extern void ComparatorIntUnregister(unsigned long ulBase,
unsigned long ulComp);
extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp);
extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp);
extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,
tBoolean bMasked);
extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __COMP_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/comp.h | C | oos | 7,319 |
//*****************************************************************************
//
// hw_flash.h - Macros used when accessing the flash controller.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_FLASH_H__
#define __HW_FLASH_H__
//*****************************************************************************
//
// The following are defines for the FLASH register offsets.
//
//*****************************************************************************
#define FLASH_FMA 0x400FD000 // Memory address register
#define FLASH_FMD 0x400FD004 // Memory data register
#define FLASH_FMC 0x400FD008 // Memory control register
#define FLASH_FCRIS 0x400FD00C // Raw interrupt status register
#define FLASH_FCIM 0x400FD010 // Interrupt mask register
#define FLASH_FCMISC 0x400FD014 // Interrupt status register
#define FLASH_RMCTL 0x400FE0F0 // ROM Control
#define FLASH_RMVER 0x400FE0F4 // ROM Version Register
#define FLASH_FMPRE 0x400FE130 // FLASH read protect register
#define FLASH_FMPPE 0x400FE134 // FLASH program protect register
#define FLASH_USECRL 0x400FE140 // uSec reload register
#define FLASH_USERDBG 0x400FE1D0 // User Debug
#define FLASH_USERREG0 0x400FE1E0 // User Register 0
#define FLASH_USERREG1 0x400FE1E4 // User Register 1
#define FLASH_USERREG2 0x400FE1E8 // User Register 2
#define FLASH_USERREG3 0x400FE1EC // User Register 3
#define FLASH_FMPRE0 0x400FE200 // FLASH read protect register 0
#define FLASH_FMPRE1 0x400FE204 // FLASH read protect register 1
#define FLASH_FMPRE2 0x400FE208 // FLASH read protect register 2
#define FLASH_FMPRE3 0x400FE20C // FLASH read protect register 3
#define FLASH_FMPPE0 0x400FE400 // FLASH program protect register 0
#define FLASH_FMPPE1 0x400FE404 // FLASH program protect register 1
#define FLASH_FMPPE2 0x400FE408 // FLASH program protect register 2
#define FLASH_FMPPE3 0x400FE40C // FLASH program protect register 3
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMC register.
//
//*****************************************************************************
#define FLASH_FMC_WRKEY_M 0xFFFF0000 // FLASH write key mask
#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key
#define FLASH_FMC_COMT 0x00000008 // Commit user register
#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH
#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page
#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word
#define FLASH_FMC_WRKEY_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FCRIS register.
//
//*****************************************************************************
#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt
// Status.
#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FCIM register.
//
//*****************************************************************************
#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask.
#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask.
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMIS register.
//
//*****************************************************************************
#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt
// Status and Clear.
#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status
// and Clear.
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMPRE and
// FLASH_FMPPE registers.
//
//*****************************************************************************
#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31
#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30
#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29
#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28
#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27
#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26
#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25
#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24
#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23
#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22
#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21
#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20
#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19
#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18
#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17
#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16
#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15
#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14
#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13
#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12
#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11
#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10
#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9
#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8
#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7
#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6
#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5
#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4
#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3
#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2
#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1
#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_USECRL register.
//
//*****************************************************************************
#define FLASH_USECRL_M 0x000000FF // Microsecond Reload Value.
#define FLASH_USECRL_S 0
//*****************************************************************************
//
// The following are defines for the erase size of the FLASH block that is
// erased by an erase operation, and the protect size is the size of the FLASH
// block that is protected by each protection register.
//
//*****************************************************************************
#define FLASH_PROTECT_SIZE 0x00000800
#define FLASH_ERASE_SIZE 0x00000400
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMA register.
//
//*****************************************************************************
#define FLASH_FMA_OFFSET_M 0x0003FFFF // Address Offset.
#define FLASH_FMA_OFFSET_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMD register.
//
//*****************************************************************************
#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value.
#define FLASH_FMD_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_USERDBG register.
//
//*****************************************************************************
#define FLASH_USERDBG_NW 0x80000000 // User Debug Not Written.
#define FLASH_USERDBG_DATA_M 0x7FFFFFFC // User Data.
#define FLASH_USERDBG_DBG1 0x00000002 // Debug Control 1.
#define FLASH_USERDBG_DBG0 0x00000001 // Debug Control 0.
#define FLASH_USERDBG_DATA_S 2
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_USERREG0 register.
//
//*****************************************************************************
#define FLASH_USERREG0_NW 0x80000000 // Not Written.
#define FLASH_USERREG0_DATA_M 0x7FFFFFFF // User Data.
#define FLASH_USERREG0_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_USERREG1 register.
//
//*****************************************************************************
#define FLASH_USERREG1_NW 0x80000000 // Not Written.
#define FLASH_USERREG1_DATA_M 0x7FFFFFFF // User Data.
#define FLASH_USERREG1_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_RMCTL register.
//
//*****************************************************************************
#define FLASH_RMCTL_BA 0x00000001 // Boot Alias.
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_RMVER register.
//
//*****************************************************************************
#define FLASH_RMVER_CONT_M 0xFF000000 // ROM Contents.
#define FLASH_RMVER_CONT_LM 0x00000000 // Boot Loader & DriverLib
#define FLASH_RMVER_SIZE_M 0x00FF0000 // ROM Size.
#define FLASH_RMVER_SIZE_11K 0x00000000 // 11KB Size
#define FLASH_RMVER_VER_M 0x0000FF00 // ROM Version.
#define FLASH_RMVER_REV_M 0x000000FF // ROM Revision.
#define FLASH_RMVER_VER_S 8
#define FLASH_RMVER_REV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_USERREG2 register.
//
//*****************************************************************************
#define FLASH_USERREG2_NW 0x80000000 // Not Written.
#define FLASH_USERREG2_DATA_M 0x7FFFFFFF // User Data.
#define FLASH_USERREG2_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_USERREG3 register.
//
//*****************************************************************************
#define FLASH_USERREG3_NW 0x80000000 // Not Written.
#define FLASH_USERREG3_DATA_M 0x7FFFFFFF // User Data.
#define FLASH_USERREG3_DATA_S 0
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the FLASH_FMC
// register.
//
//*****************************************************************************
#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the FLASH_FCRIS
// register.
//
//*****************************************************************************
#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status
#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the FLASH_FCIM
// register.
//
//*****************************************************************************
#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask
#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the FLASH_FMIS
// register.
//
//*****************************************************************************
#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status
#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the FLASH_USECRL
// register.
//
//*****************************************************************************
#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec
#define FLASH_USECRL_SHIFT 0
#endif
#endif // __HW_FLASH_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/hw_flash.h | C | oos | 14,805 |
//*****************************************************************************
//
// hw_comp.h - Macros used when accessing the comparator hardware.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_COMP_H__
#define __HW_COMP_H__
//*****************************************************************************
//
// The following are defines for the comparator register offsets.
//
//*****************************************************************************
#define COMP_O_ACMIS 0x00000000 // Analog Comparator Masked
// Interrupt Status
#define COMP_O_ACRIS 0x00000004 // Analog Comparator Raw Interrupt
// Status
#define COMP_O_ACINTEN 0x00000008 // Analog Comparator Interrupt
// Enable
#define COMP_O_ACREFCTL 0x00000010 // Analog Comparator Reference
// Voltage Control
#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register
#define COMP_O_ACCTL0 0x00000024 // Comp0 control register
#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register
#define COMP_O_ACCTL1 0x00000044 // Comp1 control register
#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register
#define COMP_O_ACCTL2 0x00000064 // Comp2 control register
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACMIS register.
//
//*****************************************************************************
#define COMP_ACMIS_IN2 0x00000004 // Comparator 2 Masked Interrupt
// Status.
#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt
// Status.
#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt
// Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACRIS register.
//
//*****************************************************************************
#define COMP_ACRIS_IN2 0x00000004 // Comparator 2 Interrupt Status.
#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status.
#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACINTEN register.
//
//*****************************************************************************
#define COMP_ACINTEN_IN2 0x00000004 // Comparator 2 Interrupt Enable.
#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable.
#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable.
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACREFCTL
// register.
//
//*****************************************************************************
#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable.
#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range.
#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref.
#define COMP_ACREFCTL_VREF_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
//
//*****************************************************************************
#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value.
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACCTL0 register.
//
//*****************************************************************************
#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable.
#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive.
#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value
#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+
#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference
#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value.
#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense.
#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge
#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge
#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge
#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value.
#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense.
#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge
#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge
#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge
#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert.
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
//
//*****************************************************************************
#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value.
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACCTL1 register.
//
//*****************************************************************************
#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable.
#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive.
#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value
#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+
#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference
#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value.
#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense.
#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge
#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge
#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge
#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value.
#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense.
#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge
#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge
#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge
#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert.
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACSTAT2 register.
//
//*****************************************************************************
#define COMP_ACSTAT2_OVAL 0x00000002 // Comparator Output Value.
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACCTL2 register.
//
//*****************************************************************************
#define COMP_ACCTL2_TOEN 0x00000800 // Trigger Output Enable.
#define COMP_ACCTL2_ASRCP_M 0x00000600 // Analog Source Positive.
#define COMP_ACCTL2_ASRCP_PIN 0x00000000 // Pin value
#define COMP_ACCTL2_ASRCP_PIN0 0x00000200 // Pin value of C0+
#define COMP_ACCTL2_ASRCP_REF 0x00000400 // Internal voltage reference
#define COMP_ACCTL2_TSLVAL 0x00000080 // Trigger Sense Level Value.
#define COMP_ACCTL2_TSEN_M 0x00000060 // Trigger Sense.
#define COMP_ACCTL2_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
#define COMP_ACCTL2_TSEN_FALL 0x00000020 // Falling edge
#define COMP_ACCTL2_TSEN_RISE 0x00000040 // Rising edge
#define COMP_ACCTL2_TSEN_BOTH 0x00000060 // Either edge
#define COMP_ACCTL2_ISLVAL 0x00000010 // Interrupt Sense Level Value.
#define COMP_ACCTL2_ISEN_M 0x0000000C // Interrupt Sense.
#define COMP_ACCTL2_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
#define COMP_ACCTL2_ISEN_FALL 0x00000004 // Falling edge
#define COMP_ACCTL2_ISEN_RISE 0x00000008 // Rising edge
#define COMP_ACCTL2_ISEN_BOTH 0x0000000C // Either edge
#define COMP_ACCTL2_CINV 0x00000002 // Comparator Output Invert.
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the comparator register offsets.
//
//*****************************************************************************
#define COMP_O_MIS 0x00000000 // Interrupt status register
#define COMP_O_RIS 0x00000004 // Raw interrupt status register
#define COMP_O_INTEN 0x00000008 // Interrupt enable register
#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg.
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the COMP_MIS,
// COMP_RIS, and COMP_INTEN registers.
//
//*****************************************************************************
#define COMP_INT_2 0x00000004 // Comp2 interrupt
#define COMP_INT_1 0x00000002 // Comp1 interrupt
#define COMP_INT_0 0x00000001 // Comp0 interrupt
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the COMP_REFCTL
// register.
//
//*****************************************************************************
#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable
#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range
#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask
#define COMP_REFCTL_VREF_SHIFT 0
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the COMP_ACSTAT0,
// COMP_ACSTAT1, and COMP_ACSTAT2 registers.
//
//*****************************************************************************
#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the COMP_ACCTL0,
// COMP_ACCTL1, and COMP_ACCTL2 registers.
//
//*****************************************************************************
#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable
#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask
#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin
#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin
#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference
#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved
#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable
#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select
#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask
#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense
#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge
#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge
#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges
#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select
#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask
#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense
#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge
#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge
#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges
#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert
//*****************************************************************************
//
// The following are deprecated defines for the reset values for the comparator
// registers.
//
//*****************************************************************************
#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register
#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register
#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register
#define COMP_RV_RIS 0x00000000 // Raw interrupt status register
#define COMP_RV_INTEN 0x00000000 // Interrupt enable register
#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register
#define COMP_RV_MIS 0x00000000 // Interrupt status register
#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register
#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register
#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg.
#endif
#endif // __HW_COMP_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/hw_comp.h | C | oos | 15,033 |
//*****************************************************************************
//
// hw_ints.h - Macros that define the interrupt assignment on Stellaris.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_INTS_H__
#define __HW_INTS_H__
//*****************************************************************************
//
// The following are defines for the fault assignments.
//
//*****************************************************************************
#define FAULT_NMI 2 // NMI fault
#define FAULT_HARD 3 // Hard fault
#define FAULT_MPU 4 // MPU fault
#define FAULT_BUS 5 // Bus fault
#define FAULT_USAGE 6 // Usage fault
#define FAULT_SVCALL 11 // SVCall
#define FAULT_DEBUG 12 // Debug monitor
#define FAULT_PENDSV 14 // PendSV
#define FAULT_SYSTICK 15 // System Tick
//*****************************************************************************
//
// The following are defines for the interrupt assignments.
//
//*****************************************************************************
#define INT_GPIOA 16 // GPIO Port A
#define INT_GPIOB 17 // GPIO Port B
#define INT_GPIOC 18 // GPIO Port C
#define INT_GPIOD 19 // GPIO Port D
#define INT_GPIOE 20 // GPIO Port E
#define INT_UART0 21 // UART0 Rx and Tx
#define INT_UART1 22 // UART1 Rx and Tx
#define INT_SSI0 23 // SSI0 Rx and Tx
#define INT_I2C0 24 // I2C0 Master and Slave
#define INT_PWM_FAULT 25 // PWM Fault
#define INT_PWM0 26 // PWM Generator 0
#define INT_PWM1 27 // PWM Generator 1
#define INT_PWM2 28 // PWM Generator 2
#define INT_QEI0 29 // Quadrature Encoder 0
#define INT_ADC0 30 // ADC Sequence 0
#define INT_ADC1 31 // ADC Sequence 1
#define INT_ADC2 32 // ADC Sequence 2
#define INT_ADC3 33 // ADC Sequence 3
#define INT_WATCHDOG 34 // Watchdog timer
#define INT_TIMER0A 35 // Timer 0 subtimer A
#define INT_TIMER0B 36 // Timer 0 subtimer B
#define INT_TIMER1A 37 // Timer 1 subtimer A
#define INT_TIMER1B 38 // Timer 1 subtimer B
#define INT_TIMER2A 39 // Timer 2 subtimer A
#define INT_TIMER2B 40 // Timer 2 subtimer B
#define INT_COMP0 41 // Analog Comparator 0
#define INT_COMP1 42 // Analog Comparator 1
#define INT_COMP2 43 // Analog Comparator 2
#define INT_SYSCTL 44 // System Control (PLL, OSC, BO)
#define INT_FLASH 45 // FLASH Control
#define INT_GPIOF 46 // GPIO Port F
#define INT_GPIOG 47 // GPIO Port G
#define INT_GPIOH 48 // GPIO Port H
#define INT_UART2 49 // UART2 Rx and Tx
#define INT_SSI1 50 // SSI1 Rx and Tx
#define INT_TIMER3A 51 // Timer 3 subtimer A
#define INT_TIMER3B 52 // Timer 3 subtimer B
#define INT_I2C1 53 // I2C1 Master and Slave
#define INT_QEI1 54 // Quadrature Encoder 1
#define INT_CAN0 55 // CAN0
#define INT_CAN1 56 // CAN1
#define INT_CAN2 57 // CAN2
#define INT_ETH 58 // Ethernet
#define INT_HIBERNATE 59 // Hibernation module
#define INT_USB0 60 // USB 0 Controller
#define INT_PWM3 61 // PWM Generator 3
#define INT_UDMA 62 // uDMA controller
#define INT_UDMAERR 63 // uDMA Error
//*****************************************************************************
//
// The following are defines for the total number of interrupts.
//
//*****************************************************************************
#define NUM_INTERRUPTS 64
//*****************************************************************************
//
// The following are defines for the total number of priority levels.
//
//*****************************************************************************
#define NUM_PRIORITY 8
#define NUM_PRIORITY_BITS 3
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the interrupt assignments.
//
//*****************************************************************************
#define INT_SSI 23 // SSI Rx and Tx
#define INT_I2C 24 // I2C Master and Slave
#define INT_QEI 29 // Quadrature Encoder
#endif
#endif // __HW_INTS_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/hw_ints.h | C | oos | 6,804 |
//*****************************************************************************
//
// cpu.h - Prototypes for the CPU instruction wrapper functions.
//
// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __CPU_H__
#define __CPU_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes.
//
//*****************************************************************************
extern unsigned long CPUcpsid(void);
extern unsigned long CPUcpsie(void);
extern void CPUwfi(void);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __CPU_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/cpu.h | C | oos | 2,337 |
//*****************************************************************************
//
// uart.h - Defines and Macros for the UART.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __UART_H__
#define __UART_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear
// as the ulIntFlags parameter, and returned from UARTIntStatus.
//
//*****************************************************************************
#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask
#define UART_INT_BE 0x200 // Break Error Interrupt Mask
#define UART_INT_PE 0x100 // Parity Error Interrupt Mask
#define UART_INT_FE 0x080 // Framing Error Interrupt Mask
#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask
#define UART_INT_TX 0x020 // Transmit Interrupt Mask
#define UART_INT_RX 0x010 // Receive Interrupt Mask
//*****************************************************************************
//
// Values that can be passed to UARTConfigSetExpClk as the ulConfig parameter
// and returned by UARTConfigGetExpClk in the pulConfig parameter.
// Additionally, the UART_CONFIG_PAR_* subset can be passed to
// UARTParityModeSet as the ulParity parameter, and are returned by
// UARTParityModeGet.
//
//*****************************************************************************
#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length
#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data
#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data
#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data
#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data
#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits
#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit
#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits
#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity
#define UART_CONFIG_PAR_NONE 0x00000000 // No parity
#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity
#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity
#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one
#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero
//*****************************************************************************
//
// Values that can be passed to UARTFIFOLevelSet as the ulTxLevel parameter and
// returned by UARTFIFOLevelGet in the pulTxLevel.
//
//*****************************************************************************
#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full
#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full
#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full
#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full
#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full
//*****************************************************************************
//
// Values that can be passed to UARTFIFOLevelSet as the ulRxLevel parameter and
// returned by UARTFIFOLevelGet in the pulRxLevel.
//
//*****************************************************************************
#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full
#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full
#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full
#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full
#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full
//*****************************************************************************
//
// Values that can be passed to UARTDMAEnable() and UARTDMADisable().
//
//*****************************************************************************
#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error
#define UART_DMA_TX 0x00000002 // Enable DMA for transmit
#define UART_DMA_RX 0x00000001 // Enable DMA for receive
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);
extern unsigned long UARTParityModeGet(unsigned long ulBase);
extern void UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
unsigned long ulRxLevel);
extern void UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
unsigned long *pulRxLevel);
extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
unsigned long ulBaud, unsigned long ulConfig);
extern void UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
unsigned long *pulBaud,
unsigned long *pulConfig);
extern void UARTEnable(unsigned long ulBase);
extern void UARTDisable(unsigned long ulBase);
extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower);
extern void UARTDisableSIR(unsigned long ulBase);
extern tBoolean UARTCharsAvail(unsigned long ulBase);
extern tBoolean UARTSpaceAvail(unsigned long ulBase);
extern long UARTCharGetNonBlocking(unsigned long ulBase);
extern long UARTCharGet(unsigned long ulBase);
extern tBoolean UARTCharPutNonBlocking(unsigned long ulBase,
unsigned char ucData);
extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);
extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);
extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern void UARTIntUnregister(unsigned long ulBase);
extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
extern void UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
//*****************************************************************************
//
// Several UART APIs have been renamed, with the original function name being
// deprecated. These defines provide backward compatibility.
//
//*****************************************************************************
#ifndef DEPRECATED
#include "sysctl.h"
#define UARTConfigSet(a, b, c) \
UARTConfigSetExpClk(a, SysCtlClockGet(), b, c)
#define UARTConfigGet(a, b, c) \
UARTConfigGetExpClk(a, SysCtlClockGet(), b, c)
#define UARTCharNonBlockingGet(a) \
UARTCharGetNonBlocking(a)
#define UARTCharNonBlockingPut(a, b) \
UARTCharPutNonBlocking(a, b)
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __UART_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/uart.h | C | oos | 9,110 |
//*****************************************************************************
//
// gpio.h - Defines and Macros for GPIO API.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __GPIO_H__
#define __GPIO_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following values define the bit field for the ucPins argument to several
// of the APIs.
//
//*****************************************************************************
#define GPIO_PIN_0 0x00000001 // GPIO pin 0
#define GPIO_PIN_1 0x00000002 // GPIO pin 1
#define GPIO_PIN_2 0x00000004 // GPIO pin 2
#define GPIO_PIN_3 0x00000008 // GPIO pin 3
#define GPIO_PIN_4 0x00000010 // GPIO pin 4
#define GPIO_PIN_5 0x00000020 // GPIO pin 5
#define GPIO_PIN_6 0x00000040 // GPIO pin 6
#define GPIO_PIN_7 0x00000080 // GPIO pin 7
//*****************************************************************************
//
// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and
// returned from GPIODirModeGet.
//
//*****************************************************************************
#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input
#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output
#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function
//*****************************************************************************
//
// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and
// returned from GPIOIntTypeGet.
//
//*****************************************************************************
#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge
#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge
#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges
#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level
#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level
//*****************************************************************************
//
// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter,
// and returned by GPIOPadConfigGet in the *pulStrength parameter.
//
//*****************************************************************************
#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength
#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength
#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength
#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control
//*****************************************************************************
//
// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,
// and returned by GPIOPadConfigGet in the *pulPadType parameter.
//
//*****************************************************************************
#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull
#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up
#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down
#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain
#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up
#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down
#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulPinIO);
extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);
extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulIntType);
extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);
extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulStrength,
unsigned long ulPadType);
extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,
unsigned long *pulStrength,
unsigned long *pulPadType);
extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins);
extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);
extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPortIntRegister(unsigned long ulPort,
void (*pfnIntHandler)(void));
extern void GPIOPortIntUnregister(unsigned long ulPort);
extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,
unsigned char ucVal);
extern void GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeGPIOOutputOD(unsigned long ulPort,
unsigned char ucPins);
extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __GPIO_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/gpio.h | C | oos | 8,002 |
//*****************************************************************************
//
// hw_nvic.h - Macros used when accessing the NVIC hardware.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_NVIC_H__
#define __HW_NVIC_H__
//*****************************************************************************
//
// The following are defines for the NVIC register addresses.
//
//*****************************************************************************
#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg.
#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg.
#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register
#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register
#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg.
#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register
#define NVIC_EN1 0xE000E104 // IRQ 32 to 63 Set Enable Register
#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg.
#define NVIC_DIS1 0xE000E184 // IRQ 32 to 63 Clear Enable Reg.
#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register
#define NVIC_PEND1 0xE000E204 // IRQ 32 to 63 Set Pending Reg.
#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg.
#define NVIC_UNPEND1 0xE000E284 // IRQ 32 to 63 Clear Pending Reg.
#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register
#define NVIC_ACTIVE1 0xE000E304 // IRQ 32 to 63 Active Register
#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register
#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register
#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register
#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register
#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register
#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register
#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register
#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register
#define NVIC_PRI8 0xE000E420 // IRQ 32 to 35 Priority Register
#define NVIC_PRI9 0xE000E424 // IRQ 36 to 39 Priority Register
#define NVIC_PRI10 0xE000E428 // IRQ 40 to 43 Priority Register
#define NVIC_PRI11 0xE000E42C // IRQ 44 to 47 Priority Register
#define NVIC_CPUID 0xE000ED00 // CPUID Base Register
#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register
#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register
#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg.
#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register
#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register
#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority
#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority
#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority
#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State
#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg.
#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register
#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register
#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register
#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register
#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register
#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register
#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register
#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register
#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg.
#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg.
#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select
#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data
#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control
#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg.
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_INT_TYPE register.
//
//*****************************************************************************
#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)
#define NVIC_INT_TYPE_LINES_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_ST_CTRL register.
//
//*****************************************************************************
#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag
#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source
#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable
#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_ST_RELOAD register.
//
//*****************************************************************************
#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value
#define NVIC_ST_RELOAD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_ST_CURRENT
// register.
//
//*****************************************************************************
#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value
#define NVIC_ST_CURRENT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_ST_CAL register.
//
//*****************************************************************************
#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock
#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew
#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value
#define NVIC_ST_CAL_ONEMS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_EN0 register.
//
//*****************************************************************************
#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable
#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable
#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable
#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable
#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable
#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable
#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable
#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable
#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable
#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable
#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable
#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable
#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable
#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable
#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable
#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable
#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable
#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable
#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable
#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable
#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable
#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable
#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable
#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable
#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable
#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable
#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable
#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable
#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable
#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable
#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable
#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_EN1 register.
//
//*****************************************************************************
#define NVIC_EN1_INT59 0x08000000 // Interrupt 59 enable
#define NVIC_EN1_INT58 0x04000000 // Interrupt 58 enable
#define NVIC_EN1_INT57 0x02000000 // Interrupt 57 enable
#define NVIC_EN1_INT56 0x01000000 // Interrupt 56 enable
#define NVIC_EN1_INT55 0x00800000 // Interrupt 55 enable
#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable
#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable
#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable
#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable
#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable
#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable
#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable
#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable
#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable
#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable
#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable
#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable
#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable
#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable
#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable
#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable
#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable
#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable
#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable
#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable
#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable
#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable
#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_DIS0 register.
//
//*****************************************************************************
#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable
#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable
#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable
#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable
#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable
#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable
#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable
#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable
#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable
#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable
#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable
#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable
#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable
#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable
#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable
#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable
#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable
#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable
#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable
#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable
#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable
#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable
#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable
#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable
#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable
#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable
#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable
#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable
#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable
#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable
#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable
#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_DIS1 register.
//
//*****************************************************************************
#define NVIC_DIS1_INT59 0x08000000 // Interrupt 59 disable
#define NVIC_DIS1_INT58 0x04000000 // Interrupt 58 disable
#define NVIC_DIS1_INT57 0x02000000 // Interrupt 57 disable
#define NVIC_DIS1_INT56 0x01000000 // Interrupt 56 disable
#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable
#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable
#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable
#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable
#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable
#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable
#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable
#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable
#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable
#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable
#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable
#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable
#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable
#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable
#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable
#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable
#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable
#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable
#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable
#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable
#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable
#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable
#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable
#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PEND0 register.
//
//*****************************************************************************
#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend
#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend
#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend
#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend
#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend
#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend
#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend
#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend
#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend
#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend
#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend
#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend
#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend
#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend
#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend
#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend
#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend
#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend
#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend
#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend
#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend
#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend
#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend
#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend
#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend
#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend
#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend
#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend
#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend
#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend
#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend
#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PEND1 register.
//
//*****************************************************************************
#define NVIC_PEND1_INT59 0x08000000 // Interrupt 59 pend
#define NVIC_PEND1_INT58 0x04000000 // Interrupt 58 pend
#define NVIC_PEND1_INT57 0x02000000 // Interrupt 57 pend
#define NVIC_PEND1_INT56 0x01000000 // Interrupt 56 pend
#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend
#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend
#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend
#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend
#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend
#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend
#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend
#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend
#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend
#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend
#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend
#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend
#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend
#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend
#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend
#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend
#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend
#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend
#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend
#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend
#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend
#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend
#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend
#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_UNPEND0 register.
//
//*****************************************************************************
#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend
#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend
#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend
#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend
#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend
#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend
#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend
#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend
#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend
#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend
#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend
#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend
#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend
#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend
#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend
#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend
#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend
#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend
#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend
#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend
#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend
#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend
#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend
#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend
#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend
#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend
#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend
#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend
#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend
#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend
#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend
#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_UNPEND1 register.
//
//*****************************************************************************
#define NVIC_UNPEND1_INT59 0x08000000 // Interrupt 59 unpend
#define NVIC_UNPEND1_INT58 0x04000000 // Interrupt 58 unpend
#define NVIC_UNPEND1_INT57 0x02000000 // Interrupt 57 unpend
#define NVIC_UNPEND1_INT56 0x01000000 // Interrupt 56 unpend
#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend
#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend
#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend
#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend
#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend
#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend
#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend
#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend
#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend
#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend
#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend
#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend
#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend
#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend
#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend
#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend
#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend
#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend
#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend
#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend
#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend
#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend
#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend
#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_ACTIVE0 register.
//
//*****************************************************************************
#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active
#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active
#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active
#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active
#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active
#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active
#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active
#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active
#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active
#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active
#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active
#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active
#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active
#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active
#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active
#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active
#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active
#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active
#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active
#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active
#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active
#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active
#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active
#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active
#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active
#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active
#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active
#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active
#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active
#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active
#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active
#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_ACTIVE1 register.
//
//*****************************************************************************
#define NVIC_ACTIVE1_INT59 0x08000000 // Interrupt 59 active
#define NVIC_ACTIVE1_INT58 0x04000000 // Interrupt 58 active
#define NVIC_ACTIVE1_INT57 0x02000000 // Interrupt 57 active
#define NVIC_ACTIVE1_INT56 0x01000000 // Interrupt 56 active
#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active
#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active
#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active
#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active
#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active
#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active
#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active
#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active
#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active
#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active
#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active
#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active
#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active
#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active
#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active
#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active
#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active
#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active
#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active
#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active
#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active
#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active
#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active
#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI0 register.
//
//*****************************************************************************
#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask
#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask
#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask
#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask
#define NVIC_PRI0_INT3_S 24
#define NVIC_PRI0_INT2_S 16
#define NVIC_PRI0_INT1_S 8
#define NVIC_PRI0_INT0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI1 register.
//
//*****************************************************************************
#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask
#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask
#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask
#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask
#define NVIC_PRI1_INT7_S 24
#define NVIC_PRI1_INT6_S 16
#define NVIC_PRI1_INT5_S 8
#define NVIC_PRI1_INT4_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI2 register.
//
//*****************************************************************************
#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask
#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask
#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask
#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask
#define NVIC_PRI2_INT11_S 24
#define NVIC_PRI2_INT10_S 16
#define NVIC_PRI2_INT9_S 8
#define NVIC_PRI2_INT8_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI3 register.
//
//*****************************************************************************
#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask
#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask
#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask
#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask
#define NVIC_PRI3_INT15_S 24
#define NVIC_PRI3_INT14_S 16
#define NVIC_PRI3_INT13_S 8
#define NVIC_PRI3_INT12_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI4 register.
//
//*****************************************************************************
#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask
#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask
#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask
#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask
#define NVIC_PRI4_INT19_S 24
#define NVIC_PRI4_INT18_S 16
#define NVIC_PRI4_INT17_S 8
#define NVIC_PRI4_INT16_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI5 register.
//
//*****************************************************************************
#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask
#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask
#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask
#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask
#define NVIC_PRI5_INT23_S 24
#define NVIC_PRI5_INT22_S 16
#define NVIC_PRI5_INT21_S 8
#define NVIC_PRI5_INT20_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI6 register.
//
//*****************************************************************************
#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask
#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask
#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask
#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask
#define NVIC_PRI6_INT27_S 24
#define NVIC_PRI6_INT26_S 16
#define NVIC_PRI6_INT25_S 8
#define NVIC_PRI6_INT24_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI7 register.
//
//*****************************************************************************
#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask
#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask
#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask
#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask
#define NVIC_PRI7_INT31_S 24
#define NVIC_PRI7_INT30_S 16
#define NVIC_PRI7_INT29_S 8
#define NVIC_PRI7_INT28_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI8 register.
//
//*****************************************************************************
#define NVIC_PRI8_INT35_M 0xFF000000 // Interrupt 35 priority mask
#define NVIC_PRI8_INT34_M 0x00FF0000 // Interrupt 34 priority mask
#define NVIC_PRI8_INT33_M 0x0000FF00 // Interrupt 33 priority mask
#define NVIC_PRI8_INT32_M 0x000000FF // Interrupt 32 priority mask
#define NVIC_PRI8_INT35_S 24
#define NVIC_PRI8_INT34_S 16
#define NVIC_PRI8_INT33_S 8
#define NVIC_PRI8_INT32_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI9 register.
//
//*****************************************************************************
#define NVIC_PRI9_INT39_M 0xFF000000 // Interrupt 39 priority mask
#define NVIC_PRI9_INT38_M 0x00FF0000 // Interrupt 38 priority mask
#define NVIC_PRI9_INT37_M 0x0000FF00 // Interrupt 37 priority mask
#define NVIC_PRI9_INT36_M 0x000000FF // Interrupt 36 priority mask
#define NVIC_PRI9_INT39_S 24
#define NVIC_PRI9_INT38_S 16
#define NVIC_PRI9_INT37_S 8
#define NVIC_PRI9_INT36_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI10 register.
//
//*****************************************************************************
#define NVIC_PRI10_INT43_M 0xFF000000 // Interrupt 43 priority mask
#define NVIC_PRI10_INT42_M 0x00FF0000 // Interrupt 42 priority mask
#define NVIC_PRI10_INT41_M 0x0000FF00 // Interrupt 41 priority mask
#define NVIC_PRI10_INT40_M 0x000000FF // Interrupt 40 priority mask
#define NVIC_PRI10_INT43_S 24
#define NVIC_PRI10_INT42_S 16
#define NVIC_PRI10_INT41_S 8
#define NVIC_PRI10_INT40_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_CPUID register.
//
//*****************************************************************************
#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer
#define NVIC_CPUID_VAR_M 0x00F00000 // Variant
#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number
#define NVIC_CPUID_REV_M 0x0000000F // Revision
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_INT_CTRL register.
//
//*****************************************************************************
#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI
#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV
#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV
#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling
#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending
#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception
#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base
#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception
#define NVIC_INT_CTRL_VEC_PEN_S 12
#define NVIC_INT_CTRL_VEC_ACT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_VTABLE register.
//
//*****************************************************************************
#define NVIC_VTABLE_BASE 0x20000000 // Vector table base
#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset
#define NVIC_VTABLE_OFFSET_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_APINT register.
//
//*****************************************************************************
#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask
#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key
#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess
#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group
#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split
#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split
#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split
#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split
#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split
#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split
#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split
#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request
#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info
#define NVIC_APINT_VECT_RESET 0x00000001 // System reset
#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_SYS_CTRL register.
//
//*****************************************************************************
#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend
#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable
#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_CFG_CTRL register.
//
//*****************************************************************************
#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault
#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0
#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access
#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger
#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger
#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
//
//*****************************************************************************
#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler
#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler
#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler
#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler
#define NVIC_SYS_PRI1_USAGE_S 16
#define NVIC_SYS_PRI1_BUS_S 8
#define NVIC_SYS_PRI1_MEM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
//
//*****************************************************************************
#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler
#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers
#define NVIC_SYS_PRI2_SVC_S 24
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
//
//*****************************************************************************
#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler
#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler
#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler
#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler
#define NVIC_SYS_PRI3_TICK_S 24
#define NVIC_SYS_PRI3_PENDSV_S 16
#define NVIC_SYS_PRI3_DEBUG_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL
// register.
//
//*****************************************************************************
#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable
#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable
#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable
#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended
#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended
#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active
#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active
#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active
#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active
#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active
#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active
#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_FAULT_STAT
// register.
//
//*****************************************************************************
#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault
#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault
#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault
#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault
#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault
#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault
#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid
#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault
#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault
#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error
#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error
#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault
#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid
#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation
#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation
#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation
#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_HFAULT_STAT
// register.
//
//*****************************************************************************
#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event
#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler
#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_DEBUG_STAT
// register.
//
//*****************************************************************************
#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted
#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch
#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match
#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction
#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_MM_ADDR register.
//
//*****************************************************************************
#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address
#define NVIC_MM_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_FAULT_ADDR
// register.
//
//*****************************************************************************
#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address
#define NVIC_FAULT_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_MPU_TYPE register.
//
//*****************************************************************************
#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions
#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions
#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU
#define NVIC_MPU_TYPE_IREGION_S 16
#define NVIC_MPU_TYPE_DREGION_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_MPU_CTRL register.
//
//*****************************************************************************
#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU default region in priv mode
#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults
#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_MPU_NUMBER
// register.
//
//*****************************************************************************
#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access
#define NVIC_MPU_NUMBER_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_MPU_BASE register.
//
//*****************************************************************************
#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base address mask
#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid
#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number
#define NVIC_MPU_BASE_ADDR_S 8
#define NVIC_MPU_BASE_REGION_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_MPU_ATTR register.
//
//*****************************************************************************
#define NVIC_MPU_ATTR_M 0xFFFF0000 // Attributes
#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access
#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable
#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable
#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable
#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type extension mask
#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none
#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only
#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw
#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none
#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro
#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access permissions mask
#define NVIC_MPU_ATTR_XN 0x10000000 // Execute disable
#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Sub-region disable mask
#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable
#define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable
#define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable
#define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable
#define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable
#define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable
#define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable
#define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable
#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region size mask
#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes
#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes
#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes
#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes
#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes
#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes
#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes
#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes
#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes
#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes
#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes
#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes
#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes
#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes
#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes
#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes
#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes
#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes
#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes
#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes
#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes
#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes
#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes
#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes
#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes
#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes
#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes
#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes
#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region enable
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_DBG_CTRL register.
//
//*****************************************************************************
#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask
#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key
#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor
#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request
#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable
#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core
#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping
#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt
#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available
#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up
#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core
#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping
#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core
#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core
#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_DBG_XFER register.
//
//*****************************************************************************
#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read
#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register
#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask
#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP
#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP
#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP
#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register
#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15
#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14
#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13
#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12
#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11
#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10
#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9
#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8
#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7
#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6
#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5
#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4
#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3
#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2
#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1
#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_DBG_DATA register.
//
//*****************************************************************************
#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache
#define NVIC_DBG_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_DBG_INT register.
//
//*****************************************************************************
#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault
#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors
#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error
#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state
#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check
#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error
#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault
#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status
#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset
#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending
#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_SW_TRIG register.
//
//*****************************************************************************
#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger
#define NVIC_SW_TRIG_INTID_S 0
#endif // __HW_NVIC_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/hw_nvic.h | C | oos | 58,773 |
//*****************************************************************************
//
// grlib.h - Prototypes for the low level primitives provided by the graphics
// library.
//
// Copyright (c) 2007-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Graphics Library.
//
//*****************************************************************************
#ifndef __GRLIB_H__
#define __GRLIB_H__
//*****************************************************************************
//
//! \addtogroup primitives_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
//! This structure defines the extents of a rectangle. All points greater than
//! or equal to the minimum and less than or equal to the maximum are part of
//! the rectangle.
//
//*****************************************************************************
typedef struct
{
//
//! The minimum X coordinate of the rectangle.
//
short sXMin;
//
//! The minimum Y coordinate of the rectangle.
//
short sYMin;
//
//! The maximum X coordinate of the rectangle.
//
short sXMax;
//
//! The maximum Y coordinate of the rectangle.
//
short sYMax;
}
tRectangle;
//*****************************************************************************
//
//! This structure defines the characteristics of a display driver.
//
//*****************************************************************************
typedef struct
{
//
//! The size of this structure.
//
long lSize;
//
//! A pointer to display driver-specific data.
//
void *pvDisplayData;
//
//! The width of this display.
//
unsigned short usWidth;
//
//! The height of this display.
//
unsigned short usHeight;
//
//! A pointer to the function to draw a pixel on this display.
//
void (*pfnPixelDraw)(void *pvDisplayData, long lX, long lY,
unsigned long ulValue);
//
//! A pointer to the function to draw multiple pixels on this display.
//
void (*pfnPixelDrawMultiple)(void *pvDisplayData, long lX, long lY,
long lX0, long lCount, long lBPP,
const unsigned char *pucData,
const unsigned char *pucPalette);
//
//! A pointer to the function to draw a horizontal line on this display.
//
void (*pfnLineDrawH)(void *pvDisplayData, long lX1, long lX2, long lY,
unsigned long ulValue);
//
//! A pointer to the function to draw a vertical line on this display.
//
void (*pfnLineDrawV)(void *pvDisplayData, long lX, long lY1, long lY2,
unsigned long ulValue);
//
//! A pointer to the function to draw a filled rectangle on this display.
//
void (*pfnRectFill)(void *pvDisplayData, const tRectangle *pRect,
unsigned long ulValue);
//
//! A pointer to the function to translate 24-bit RGB colors to
//! display-specific colors.
//
unsigned long (*pfnColorTranslate)(void *pvDisplayData,
unsigned long ulValue);
//
//! A pointer to the function to flush any cached drawing operations on
//! this display.
//
void (*pfnFlush)(void *pvDisplayData);
}
tDisplay;
//*****************************************************************************
//
//! This structure describes a font used for drawing text onto the screen.
//
//*****************************************************************************
typedef struct
{
//
//! The format of the font. Can be one of FONT_FMT_UNCOMPRESSED or
//! FONT_FMT_PIXEL_RLE.
//
unsigned char ucFormat;
//
//! The maximum width of a character; this is the width of the widest
//! character in the font, though any individual character may be narrower
//! than this width.
//
unsigned char ucMaxWidth;
//
//! The height of the character cell; this may be taller than the font data
//! for the characters (to provide inter-line spacing).
//
unsigned char ucHeight;
//
//! The offset between the top of the character cell and the baseline of
//! the glyph. The baseline is the bottom row of a capital letter, below
//! which only the descenders of the lower case letters occur.
//
unsigned char ucBaseline;
//
//! The offset within pucData to the data for each character in the font.
//
unsigned short pusOffset[96];
//
//! A pointer to the data for the font.
//
const unsigned char *pucData;
}
tFont;
//*****************************************************************************
//
//! Indicates that the font data is stored in an uncompressed format.
//
//*****************************************************************************
#define FONT_FMT_UNCOMPRESSED 0x00
//*****************************************************************************
//
//! Indicates that the font data is stored using a pixel-based RLE format.
//
//*****************************************************************************
#define FONT_FMT_PIXEL_RLE 0x01
//*****************************************************************************
//
//! Indicates that the image data is not compressed and represents each pixel
//! with a single bit.
//
//*****************************************************************************
#define IMAGE_FMT_1BPP_UNCOMP 0x01
//*****************************************************************************
//
//! Indicates that the image data is not compressed and represents each pixel
//! with four bits.
//
//*****************************************************************************
#define IMAGE_FMT_4BPP_UNCOMP 0x04
//*****************************************************************************
//
//! Indicates that the image data is not compressed and represents each pixel
//! with eight bits.
//
//*****************************************************************************
#define IMAGE_FMT_8BPP_UNCOMP 0x08
//*****************************************************************************
//
//! Indicates that the image data is compressed and represents each pixel with
//! a single bit.
//
//*****************************************************************************
#define IMAGE_FMT_1BPP_COMP 0x81
//*****************************************************************************
//
//! Indicates that the image data is compressed and represents each pixel with
//! four bits.
//
//*****************************************************************************
#define IMAGE_FMT_4BPP_COMP 0x84
//*****************************************************************************
//
//! Indicates that the image data is compressed and represents each pixel with
//! eight bits.
//
//*****************************************************************************
#define IMAGE_FMT_8BPP_COMP 0x88
//*****************************************************************************
//
//! This structure defines a drawing context to be used to draw onto the
//! screen. Multiple drawing contexts may exist at any time.
//
//*****************************************************************************
typedef struct
{
//
//! The size of this structure.
//
long lSize;
//
//! The screen onto which drawing operations are performed.
//
const tDisplay *pDisplay;
//
//! The clipping region to be used when drawing onto the screen.
//
tRectangle sClipRegion;
//
//! The color used to draw primitives onto the screen.
//
unsigned long ulForeground;
//
//! The background color used to draw primitives onto the screen.
//
unsigned long ulBackground;
//
//! The font used to render text onto the screen.
//
const tFont *pFont;
}
tContext;
//*****************************************************************************
//
//! Sets the background color to be used.
//!
//! \param pContext is a pointer to the drawing context to modify.
//! \param ulValue is the 24-bit RGB color to be used.
//!
//! This function sets the background color to be used for drawing operations
//! in the specified drawing context.
//!
//! \return None.
//
//*****************************************************************************
#define GrContextBackgroundSet(pContext, ulValue) \
do \
{ \
tContext *pC = pContext; \
pC->ulBackground = DpyColorTranslate(pC->pDisplay, ulValue); \
} \
while(0)
//*****************************************************************************
//
//! Sets the background color to be used.
//!
//! \param pContext is a pointer to the drawing context to modify.
//! \param ulValue is the display driver-specific color to be used.
//!
//! This function sets the background color to be used for drawing operations
//! in the specified drawing context, using a color that has been previously
//! translated to a driver-specific color (for example, via
//! DpyColorTranslate()).
//!
//! \return None.
//
//*****************************************************************************
#define GrContextBackgroundSetTranslated(pContext, ulValue) \
do \
{ \
tContext *pC = pContext; \
pC->ulBackground = ulValue; \
} \
while(0)
//*****************************************************************************
//
//! Gets the width of the display being used by this drawing context.
//!
//! \param pContext is a pointer to the drawing context to query.
//!
//! This function returns the width of the display that is being used by this
//! drawing context.
//!
//! \return Returns the width of the display in pixels.
//
//*****************************************************************************
#define GrContextDpyWidthGet(pContext) \
(DpyWidthGet((pContext)->pDisplay))
//*****************************************************************************
//
//! Gets the height of the display being used by this drawing context.
//!
//! \param pContext is a pointer to the drawing context to query.
//!
//! This function returns the height of the display that is being used by this
//! drawing context.
//!
//! \return Returns the height of the display in pixels.
//
//*****************************************************************************
#define GrContextDpyHeightGet(pContext) \
(DpyHeightGet((pContext)->pDisplay))
//*****************************************************************************
//
//! Sets the font to be used.
//!
//! \param pContext is a pointer to the drawing context to modify.
//! \param pFnt is a pointer to the font to be used.
//!
//! This function sets the font to be used for string drawing operations in the
//! specified drawing context.
//!
//! \return None.
//
//*****************************************************************************
#define GrContextFontSet(pContext, pFnt) \
do \
{ \
tContext *pC = pContext; \
const tFont *pF = pFnt; \
pC->pFont = pF; \
} \
while(0)
//*****************************************************************************
//
//! Sets the foreground color to be used.
//!
//! \param pContext is a pointer to the drawing context to modify.
//! \param ulValue is the 24-bit RGB color to be used.
//!
//! This function sets the color to be used for drawing operations in the
//! specified drawing context.
//!
//! \return None.
//
//*****************************************************************************
#define GrContextForegroundSet(pContext, ulValue) \
do \
{ \
tContext *pC = pContext; \
pC->ulForeground = DpyColorTranslate(pC->pDisplay, ulValue); \
} \
while(0)
//*****************************************************************************
//
//! Sets the foreground color to be used.
//!
//! \param pContext is a pointer to the drawing context to modify.
//! \param ulValue is the display driver-specific color to be used.
//!
//! This function sets the foreground color to be used for drawing operations
//! in the specified drawing context, using a color that has been previously
//! translated to a driver-specific color (for example, via
//! DpyColorTranslate()).
//!
//! \return None.
//
//*****************************************************************************
#define GrContextForegroundSetTranslated(pContext, ulValue) \
do \
{ \
tContext *pC = pContext; \
pC->ulForeground = ulValue; \
} \
while(0)
//*****************************************************************************
//
//! Flushes any cached drawing operations.
//!
//! \param pContext is a pointer to the drawing context to use.
//!
//! This function flushes any cached drawing operations. For display drivers
//! that draw into a local frame buffer before writing to the actual display,
//! calling this function will cause the display to be updated to match the
//! contents of the local frame buffer.
//!
//! \return None.
//
//*****************************************************************************
#define GrFlush(pContext) \
do \
{ \
const tContext *pC = pContext; \
DpyFlush(pC->pDisplay); \
} \
while(0)
//*****************************************************************************
//
//! Gets the baseline of a font.
//!
//! \param pFont is a pointer to the font to query.
//!
//! This function determines the baseline position of a font. The baseline is
//! the offset between the top of the font and the bottom of the capital
//! letters. The only font data that exists below the baseline are the
//! descenders on some lower-case letters (such as ``y'').
//!
//! \return Returns the baseline of the font, in pixels.
//
//*****************************************************************************
#define GrFontBaselineGet(pFont) \
((pFont)->ucBaseline)
//*****************************************************************************
//
//! Gets the height of a font.
//!
//! \param pFont is a pointer to the font to query.
//!
//! This function determines the height of a font. The height is the offset
//! between the top of the font and the bottom of the font, including any
//! ascenders and descenders.
//!
//! \return Returns the height of the font, in pixels.
//
//*****************************************************************************
#define GrFontHeightGet(pFont) \
((pFont)->ucHeight)
//*****************************************************************************
//
//! Gets the maximum width of a font.
//!
//! \param pFont is a pointer to the font to query.
//!
//! This function determines the maximum width of a font. The maximum width is
//! the width of the widest individual character in the font.
//!
//! \return Returns the maximum width of the font, in pixels.
//
//*****************************************************************************
#define GrFontMaxWidthGet(pFont) \
((pFont)->ucMaxWidth)
//*****************************************************************************
//
//! Gets the number of colors in an image.
//!
//! \param pucImage is a pointer to the image to query.
//!
//! This function determines the number of colors in the palette of an image.
//! This is only valid for 4bpp and 8bpp images; 1bpp images do not contain a
//! palette.
//!
//! \return Returns the number of colors in the image.
//
//*****************************************************************************
#define GrImageColorsGet(pucImage) \
(((unsigned char *)pucImage)[5] + 1)
//*****************************************************************************
//
//! Gets the height of an image.
//!
//! \param pucImage is a pointer to the image to query.
//!
//! This function determines the height of an image in pixels.
//!
//! \return Returns the height of the image in pixels.
//
//*****************************************************************************
#define GrImageHeightGet(pucImage) \
(*(unsigned short *)(pucImage + 3))
//*****************************************************************************
//
//! Gets the width of an image.
//!
//! \param pucImage is a pointer to the image to query.
//!
//! This function determines the width of an image in pixels.
//!
//! \return Returns the width of the image in pixels.
//
//*****************************************************************************
#define GrImageWidthGet(pucImage) \
(*(unsigned short *)(pucImage + 1))
//*****************************************************************************
//
//! Determines the size of the buffer for a 1 BPP off-screen image.
//!
//! \param lWidth is the width of the image in pixels.
//! \param lHeight is the height of the image in pixels.
//!
//! This function determines the size of the memory buffer required to hold a
//! 1 BPP off-screen image of the specified geometry.
//!
//! \return Returns the number of bytes required by the image.
//
//*****************************************************************************
#define GrOffScreen1BPPSize(lWidth, lHeight) \
(5 + (((lWidth + 7) / 8) * lHeight))
//*****************************************************************************
//
//! Determines the size of the buffer for a 4 BPP off-screen image.
//!
//! \param lWidth is the width of the image in pixels.
//! \param lHeight is the height of the image in pixels.
//!
//! This function determines the size of the memory buffer required to hold a
//! 4 BPP off-screen image of the specified geometry.
//!
//! \return Returns the number of bytes required by the image.
//
//*****************************************************************************
#define GrOffScreen4BPPSize(lWidth, lHeight) \
(6 + (16 * 3) + (((lWidth + 1) / 2) * lHeight))
//*****************************************************************************
//
//! Determines the size of the buffer for an 8 BPP off-screen image.
//!
//! \param lWidth is the width of the image in pixels.
//! \param lHeight is the height of the image in pixels.
//!
//! This function determines the size of the memory buffer required to hold an
//! 8 BPP off-screen image of the specified geometry.
//!
//! \return Returns the number of bytes required by the image.
//
//*****************************************************************************
#define GrOffScreen8BPPSize(lWidth, lHeight) \
(6 + (256 * 3) + (lWidth * lHeight))
//*****************************************************************************
//
//! Draws a pixel.
//!
//! \param pContext is a pointer to the drawing context to use.
//! \param lX is the X coordinate of the pixel.
//! \param lY is the Y coordinate of the pixel.
//!
//! This function draws a pixel if it resides within the clipping region.
//!
//! \return None.
//
//*****************************************************************************
#define GrPixelDraw(pContext, lX, lY) \
do \
{ \
const tContext *pC = pContext; \
if((lX >= pC->sClipRegion.sXMin) && \
(lX <= pC->sClipRegion.sXMax) && \
(lY >= pC->sClipRegion.sYMin) && \
(lY <= pC->sClipRegion.sYMax)) \
{ \
DpyPixelDraw(pC->pDisplay, lX, lY, pC->ulForeground); \
} \
} \
while(0)
//*****************************************************************************
//
//! Gets the baseline of a string.
//!
//! \param pContext is a pointer to the drawing context to query.
//!
//! This function determines the baseline position of a string. The baseline
//! is the offset between the top of the string and the bottom of the capital
//! letters. The only string data that exists below the baseline are the
//! descenders on some lower-case letters (such as ``y'').
//!
//! \return Returns the baseline of the string, in pixels.
//
//*****************************************************************************
#define GrStringBaselineGet(pContext) \
((pContext)->pFont->ucBaseline)
//*****************************************************************************
//
//! Draws a centered string.
//!
//! \param pContext is a pointer to the drawing context to use.
//! \param pcString is a pointer to the string to be drawn.
//! \param lLength is the number of characters from the string that should be
//! drawn on the screen.
//! \param lX is the X coordinate of the center of the string position on the
//! screen.
//! \param lY is the Y coordinate of the center of the string position on the
//! screen.
//! \param bOpaque is \b true if the background of each character should be
//! drawn and \b false if it should not (leaving the background as is).
//!
//! This function draws a string of test on the screen centered upon the
//! provided position. The \e lLength parameter allows a portion of the
//! string to be examined without having to insert a NULL character at the
//! stopping point (which would not be possible if the string was located in
//! flash); specifying a length of -1 will cause the entire string to be
//! rendered (subject to clipping).
//!
//! \return None.
//
//*****************************************************************************
#define GrStringDrawCentered(pContext, pcString, lLength, lX, lY, bOpaque) \
do \
{ \
const tContext *pC = pContext; \
const char *pcStr = pcString; \
\
GrStringDraw(pC, pcStr, lLength, \
(lX) - (GrStringWidthGet(pC, pcStr, lLength) / 2), \
(lY) - (pC->pFont->ucBaseline / 2), bOpaque); \
} \
while(0)
//*****************************************************************************
//
//! Gets the height of a string.
//!
//! \param pContext is a pointer to the drawing context to query.
//!
//! This function determines the height of a string. The height is the offset
//! between the top of the string and the bottom of the string, including any
//! ascenders and descenders. Note that this will not account for the case
//! where the string in question does not have any characters that use
//! descenders but the font in the drawing context does contain characters with
//! descenders.
//!
//! \return Returns the height of the string, in pixels.
//
//*****************************************************************************
#define GrStringHeightGet(pContext) \
((pContext)->pFont->ucHeight)
//*****************************************************************************
//
//! Gets the maximum width of a character in a string.
//!
//! \param pContext is a pointer to the drawing context to query.
//!
//! This function determines the maximum width of a character in a string. The
//! maximum width is the width of the widest individual character in the font
//! used to render the string, which may be wider than the widest character
//! that is used to render a particular string.
//!
//! \return Returns the maximum width of a character in a string, in pixels.
//
//*****************************************************************************
#define GrStringMaxWidthGet(pContext) \
((pContext)->pFont->ucMaxWidth)
//*****************************************************************************
//
// A set of color definitions. This set is the subset of the X11 colors (from
// rgb.txt) that are supported by typical web browsers.
//
//*****************************************************************************
#define ClrAliceBlue 0x00F0F8FF
#define ClrAntiqueWhite 0x00FAEBD7
#define ClrAqua 0x0000FFFF
#define ClrAquamarine 0x007FFFD4
#define ClrAzure 0x00F0FFFF
#define ClrBeige 0x00F5F5DC
#define ClrBisque 0x00FFE4C4
#define ClrBlack 0x00000000
#define ClrBlanchedAlmond 0x00FFEBCD
#define ClrBlue 0x000000FF
#define ClrBlueViolet 0x008A2BE2
#define ClrBrown 0x00A52A2A
#define ClrBurlyWood 0x00DEB887
#define ClrCadetBlue 0x005F9EA0
#define ClrChartreuse 0x007FFF00
#define ClrChocolate 0x00D2691E
#define ClrCoral 0x00FF7F50
#define ClrCornflowerBlue 0x006495ED
#define ClrCornsilk 0x00FFF8DC
#define ClrCrimson 0x00DC143C
#define ClrCyan 0x0000FFFF
#define ClrDarkBlue 0x0000008B
#define ClrDarkCyan 0x00008B8B
#define ClrDarkGoldenrod 0x00B8860B
#define ClrDarkGray 0x00A9A9A9
#define ClrDarkGreen 0x00006400
#define ClrDarkKhaki 0x00BDB76B
#define ClrDarkMagenta 0x008B008B
#define ClrDarkOliveGreen 0x00556B2F
#define ClrDarkOrange 0x00FF8C00
#define ClrDarkOrchid 0x009932CC
#define ClrDarkRed 0x008B0000
#define ClrDarkSalmon 0x00E9967A
#define ClrDarkSeaGreen 0x008FBC8F
#define ClrDarkSlateBlue 0x00483D8B
#define ClrDarkSlateGray 0x002F4F4F
#define ClrDarkTurquoise 0x0000CED1
#define ClrDarkViolet 0x009400D3
#define ClrDeepPink 0x00FF1493
#define ClrDeepSkyBlue 0x0000BFFF
#define ClrDimGray 0x00696969
#define ClrDodgerBlue 0x001E90FF
#define ClrFireBrick 0x00B22222
#define ClrFloralWhite 0x00FFFAF0
#define ClrForestGreen 0x00228B22
#define ClrFuchsia 0x00FF00FF
#define ClrGainsboro 0x00DCDCDC
#define ClrGhostWhite 0x00F8F8FF
#define ClrGold 0x00FFD700
#define ClrGoldenrod 0x00DAA520
#define ClrGray 0x00808080
#define ClrGreen 0x00008000
#define ClrGreenYellow 0x00ADFF2F
#define ClrHoneydew 0x00F0FFF0
#define ClrHotPink 0x00FF69B4
#define ClrIndianRed 0x00CD5C5C
#define ClrIndigo 0x004B0082
#define ClrIvory 0x00FFFFF0
#define ClrKhaki 0x00F0E68C
#define ClrLavender 0x00E6E6FA
#define ClrLavenderBlush 0x00FFF0F5
#define ClrLawnGreen 0x007CFC00
#define ClrLemonChiffon 0x00FFFACD
#define ClrLightBlue 0x00ADD8E6
#define ClrLightCoral 0x00F08080
#define ClrLightCyan 0x00E0FFFF
#define ClrLightGoldenrodYellow 0x00FAFAD2
#define ClrLightGreen 0x0090EE90
#define ClrLightGrey 0x00D3D3D3
#define ClrLightPink 0x00FFB6C1
#define ClrLightSalmon 0x00FFA07A
#define ClrLightSeaGreen 0x0020B2AA
#define ClrLightSkyBlue 0x0087CEFA
#define ClrLightSlateGray 0x00778899
#define ClrLightSteelBlue 0x00B0C4DE
#define ClrLightYellow 0x00FFFFE0
#define ClrLime 0x0000FF00
#define ClrLimeGreen 0x0032CD32
#define ClrLinen 0x00FAF0E6
#define ClrMagenta 0x00FF00FF
#define ClrMaroon 0x00800000
#define ClrMediumAquamarine 0x0066CDAA
#define ClrMediumBlue 0x000000CD
#define ClrMediumOrchid 0x00BA55D3
#define ClrMediumPurple 0x009370DB
#define ClrMediumSeaGreen 0x003CB371
#define ClrMediumSlateBlue 0x007B68EE
#define ClrMediumSpringGreen 0x0000FA9A
#define ClrMediumTurquoise 0x0048D1CC
#define ClrMediumVioletRed 0x00C71585
#define ClrMidnightBlue 0x00191970
#define ClrMintCream 0x00F5FFFA
#define ClrMistyRose 0x00FFE4E1
#define ClrMoccasin 0x00FFE4B5
#define ClrNavajoWhite 0x00FFDEAD
#define ClrNavy 0x00000080
#define ClrOldLace 0x00FDF5E6
#define ClrOlive 0x00808000
#define ClrOliveDrab 0x006B8E23
#define ClrOrange 0x00FFA500
#define ClrOrangeRed 0x00FF4500
#define ClrOrchid 0x00DA70D6
#define ClrPaleGoldenrod 0x00EEE8AA
#define ClrPaleGreen 0x0098FB98
#define ClrPaleTurquoise 0x00AFEEEE
#define ClrPaleVioletRed 0x00DB7093
#define ClrPapayaWhip 0x00FFEFD5
#define ClrPeachPuff 0x00FFDAB9
#define ClrPeru 0x00CD853F
#define ClrPink 0x00FFC0CB
#define ClrPlum 0x00DDA0DD
#define ClrPowderBlue 0x00B0E0E6
#define ClrPurple 0x00800080
#define ClrRed 0x00FF0000
#define ClrRosyBrown 0x00BC8F8F
#define ClrRoyalBlue 0x004169E1
#define ClrSaddleBrown 0x008B4513
#define ClrSalmon 0x00FA8072
#define ClrSandyBrown 0x00F4A460
#define ClrSeaGreen 0x002E8B57
#define ClrSeashell 0x00FFF5EE
#define ClrSienna 0x00A0522D
#define ClrSilver 0x00C0C0C0
#define ClrSkyBlue 0x0087CEEB
#define ClrSlateBlue 0x006A5ACD
#define ClrSlateGray 0x00708090
#define ClrSnow 0x00FFFAFA
#define ClrSpringGreen 0x0000FF7F
#define ClrSteelBlue 0x004682B4
#define ClrTan 0x00D2B48C
#define ClrTeal 0x00008080
#define ClrThistle 0x00D8BFD8
#define ClrTomato 0x00FF6347
#define ClrTurquoise 0x0040E0D0
#define ClrViolet 0x00EE82EE
#define ClrWheat 0x00F5DEB3
#define ClrWhite 0x00FFFFFF
#define ClrWhiteSmoke 0x00F5F5F5
#define ClrYellow 0x00FFFF00
#define ClrYellowGreen 0x009ACD32
//*****************************************************************************
//
// Masks and shifts to aid in color format translation by drivers.
//
//*****************************************************************************
#define ClrRedMask 0x00FF0000
#define ClrRedShift 16
#define ClrGreenMask 0x0000FF00
#define ClrGreenShift 8
#define ClrBlueMask 0x000000FF
#define ClrBlueShift 0
//*****************************************************************************
//
// Prototypes for the predefined fonts in the graphics library. ..Cm.. is the
// computer modern font, which is a serif font. ..Cmsc.. is the computer
// modern small-caps font, which is also a serif font. ..Cmss.. is the
// computer modern sans-serif font.
//
//*****************************************************************************
extern const tFont g_sFontCm12;
extern const tFont g_sFontCm12b;
extern const tFont g_sFontCm12i;
extern const tFont g_sFontCm14;
extern const tFont g_sFontCm14b;
extern const tFont g_sFontCm14i;
extern const tFont g_sFontCm16;
extern const tFont g_sFontCm16b;
extern const tFont g_sFontCm16i;
extern const tFont g_sFontCm18;
extern const tFont g_sFontCm18b;
extern const tFont g_sFontCm18i;
extern const tFont g_sFontCm20;
extern const tFont g_sFontCm20b;
extern const tFont g_sFontCm20i;
extern const tFont g_sFontCm22;
extern const tFont g_sFontCm22b;
extern const tFont g_sFontCm22i;
extern const tFont g_sFontCm24;
extern const tFont g_sFontCm24b;
extern const tFont g_sFontCm24i;
extern const tFont g_sFontCm26;
extern const tFont g_sFontCm26b;
extern const tFont g_sFontCm26i;
extern const tFont g_sFontCm28;
extern const tFont g_sFontCm28b;
extern const tFont g_sFontCm28i;
extern const tFont g_sFontCm30;
extern const tFont g_sFontCm30b;
extern const tFont g_sFontCm30i;
extern const tFont g_sFontCm32;
extern const tFont g_sFontCm32b;
extern const tFont g_sFontCm32i;
extern const tFont g_sFontCm34;
extern const tFont g_sFontCm34b;
extern const tFont g_sFontCm34i;
extern const tFont g_sFontCm36;
extern const tFont g_sFontCm36b;
extern const tFont g_sFontCm36i;
extern const tFont g_sFontCm38;
extern const tFont g_sFontCm38b;
extern const tFont g_sFontCm38i;
extern const tFont g_sFontCm40;
extern const tFont g_sFontCm40b;
extern const tFont g_sFontCm40i;
extern const tFont g_sFontCm42;
extern const tFont g_sFontCm42b;
extern const tFont g_sFontCm42i;
extern const tFont g_sFontCm44;
extern const tFont g_sFontCm44b;
extern const tFont g_sFontCm44i;
extern const tFont g_sFontCm46;
extern const tFont g_sFontCm46b;
extern const tFont g_sFontCm46i;
extern const tFont g_sFontCm48;
extern const tFont g_sFontCm48b;
extern const tFont g_sFontCm48i;
extern const tFont g_sFontCmsc12;
extern const tFont g_sFontCmsc14;
extern const tFont g_sFontCmsc16;
extern const tFont g_sFontCmsc18;
extern const tFont g_sFontCmsc20;
extern const tFont g_sFontCmsc22;
extern const tFont g_sFontCmsc24;
extern const tFont g_sFontCmsc26;
extern const tFont g_sFontCmsc28;
extern const tFont g_sFontCmsc30;
extern const tFont g_sFontCmsc32;
extern const tFont g_sFontCmsc34;
extern const tFont g_sFontCmsc36;
extern const tFont g_sFontCmsc38;
extern const tFont g_sFontCmsc40;
extern const tFont g_sFontCmsc42;
extern const tFont g_sFontCmsc44;
extern const tFont g_sFontCmsc46;
extern const tFont g_sFontCmsc48;
extern const tFont g_sFontCmss12;
extern const tFont g_sFontCmss12b;
extern const tFont g_sFontCmss12i;
extern const tFont g_sFontCmss14;
extern const tFont g_sFontCmss14b;
extern const tFont g_sFontCmss14i;
extern const tFont g_sFontCmss16;
extern const tFont g_sFontCmss16b;
extern const tFont g_sFontCmss16i;
extern const tFont g_sFontCmss18;
extern const tFont g_sFontCmss18b;
extern const tFont g_sFontCmss18i;
extern const tFont g_sFontCmss20;
extern const tFont g_sFontCmss20b;
extern const tFont g_sFontCmss20i;
extern const tFont g_sFontCmss22;
extern const tFont g_sFontCmss22b;
extern const tFont g_sFontCmss22i;
extern const tFont g_sFontCmss24;
extern const tFont g_sFontCmss24b;
extern const tFont g_sFontCmss24i;
extern const tFont g_sFontCmss26;
extern const tFont g_sFontCmss26b;
extern const tFont g_sFontCmss26i;
extern const tFont g_sFontCmss28;
extern const tFont g_sFontCmss28b;
extern const tFont g_sFontCmss28i;
extern const tFont g_sFontCmss30;
extern const tFont g_sFontCmss30b;
extern const tFont g_sFontCmss30i;
extern const tFont g_sFontCmss32;
extern const tFont g_sFontCmss32b;
extern const tFont g_sFontCmss32i;
extern const tFont g_sFontCmss34;
extern const tFont g_sFontCmss34b;
extern const tFont g_sFontCmss34i;
extern const tFont g_sFontCmss36;
extern const tFont g_sFontCmss36b;
extern const tFont g_sFontCmss36i;
extern const tFont g_sFontCmss38;
extern const tFont g_sFontCmss38b;
extern const tFont g_sFontCmss38i;
extern const tFont g_sFontCmss40;
extern const tFont g_sFontCmss40b;
extern const tFont g_sFontCmss40i;
extern const tFont g_sFontCmss42;
extern const tFont g_sFontCmss42b;
extern const tFont g_sFontCmss42i;
extern const tFont g_sFontCmss44;
extern const tFont g_sFontCmss44b;
extern const tFont g_sFontCmss44i;
extern const tFont g_sFontCmss46;
extern const tFont g_sFontCmss46b;
extern const tFont g_sFontCmss46i;
extern const tFont g_sFontCmss48;
extern const tFont g_sFontCmss48b;
extern const tFont g_sFontCmss48i;
extern const tFont g_sFontFixed6x8;
//*****************************************************************************
//
//! Translates a 24-bit RGB color to a display driver-specific color.
//!
//! \param pDisplay is the pointer to the display driver structure for the
//! display to operate upon.
//! \param ulValue is the 24-bit RGB color. The least-significant byte is the
//! blue channel, the next byte is the green channel, and the third byte is the
//! red channel.
//!
//! This function translates a 24-bit RGB color into a value that can be
//! written into the display's frame buffer in order to reproduce that color,
//! or the closest possible approximation of that color.
//!
//! \return Returns the display-driver specific color.
//
//*****************************************************************************
#define DpyColorTranslate(pDisplay, ulValue) \
((pDisplay)->pfnColorTranslate((pDisplay)->pvDisplayData, ulValue))
//*****************************************************************************
//
//! Flushes cached drawing operations.
//!
//! \param pDisplay is the pointer to the display driver structure for the
//! display to operate upon.
//!
//! This function flushes any cached drawing operations on a display.
//!
//! \return None.
//
//*****************************************************************************
#define DpyFlush(pDisplay) \
do \
{ \
const tDisplay *pD = pDisplay; \
pD->pfnFlush(pD->pvDisplayData); \
} \
while(0)
//*****************************************************************************
//
//! Gets the height of the display.
//!
//! \param pDisplay is a pointer to the display driver structure for the
//! display to query.
//!
//! This function determines the height of the display.
//!
//! \return Returns the height of the display in pixels.
//
//*****************************************************************************
#define DpyHeightGet(pDisplay) \
((pDisplay)->usHeight)
//*****************************************************************************
//
//! Draws a horizontal line on a display.
//!
//! \param pDisplay is the pointer to the display driver structure for the
//! display to operate upon.
//! \param lX1 is the starting X coordinate of the line.
//! \param lX2 is the ending X coordinate of the line.
//! \param lY is the Y coordinate of the line.
//! \param ulValue is the color to draw the line.
//!
//! This function draws a horizontal line on a display. This assumes that
//! clipping has already been performed, and that both end points of the line
//! are within the extents of the display.
//!
//! \return None.
//
//*****************************************************************************
#define DpyLineDrawH(pDisplay, lX1, lX2, lY, ulValue) \
do \
{ \
const tDisplay *pD = pDisplay; \
pD->pfnLineDrawH(pD->pvDisplayData, lX1, lX2, lY, ulValue); \
} \
while(0)
//*****************************************************************************
//
//! Draws a vertical line on a display.
//!
//! \param pDisplay is the pointer to the display driver structure for the
//! display to operate upon.
//! \param lX is the X coordinate of the line.
//! \param lY1 is the starting Y coordinate of the line.
//! \param lY2 is the ending Y coordinate of the line.
//! \param ulValue is the color to draw the line.
//!
//! This function draws a vertical line on a display. This assumes that
//! clipping has already been performed, and that both end points of the line
//! are within the extents of the display.
//!
//! \return None.
//
//*****************************************************************************
#define DpyLineDrawV(pDisplay, lX, lY1, lY2, ulValue) \
do \
{ \
const tDisplay *pD = pDisplay; \
pD->pfnLineDrawV(pD->pvDisplayData, lX, lY1, lY2, ulValue); \
} \
while(0)
//*****************************************************************************
//
//! Draws a pixel on a display.
//!
//! \param pDisplay is the pointer to the display driver structure for the
//! display to operate upon.
//! \param lX is the X coordinate of the pixel.
//! \param lY is the Y coordinate of the pixel.
//! \param ulValue is the color to draw the pixel.
//!
//! This function draws a pixel on a display. This assumes that clipping has
//! already been performed.
//!
//! \return None.
//
//*****************************************************************************
#define DpyPixelDraw(pDisplay, lX, lY, ulValue) \
do \
{ \
const tDisplay *pD = pDisplay; \
pD->pfnPixelDraw(pD->pvDisplayData, lX, lY, ulValue); \
} \
while(0)
//*****************************************************************************
//
//! Draws a horizontal sequence of pixels on a display.
//!
//! \param pDisplay is the pointer to the display driver structure for the
//! display to operate upon.
//! \param lX is the X coordinate of the first pixel.
//! \param lY is the Y coordinate of the first pixel.
//! \param lX0 is sub-pixel offset within the pixel data, which is valid for 1
//! or 4 bit per pixel formats.
//! \param lCount is the number of pixels to draw.
//! \param lBPP is the number of bits per pixel; must be 1, 4, or 8.
//! \param pucData is a pointer to the pixel data. For 1 and 4 bit per pixel
//! formats, the most significant bit(s) represent the left-most pixel.
//! \param pucPalette is a pointer to the palette used to draw the pixels.
//!
//! This function draws a horizontal sequence of pixels on a display, using the
//! supplied palette. For 1 bit per pixel format, the palette contains
//! pre-translated colors; for 4 and 8 bit per pixel formats, the palette
//! contains 24-bit RGB values that must be translated before being written to
//! the display.
//!
//! \return None.
//
//*****************************************************************************
#define DpyPixelDrawMultiple(pDisplay, lX, lY, lX0, lCount, lBPP, pucData, \
pucPalette) \
do \
{ \
const tDisplay *pD = pDisplay; \
pD->pfnPixelDrawMultiple(pD->pvDisplayData, lX, lY, lX0, lCount, \
lBPP, pucData, pucPalette); \
} \
while(0)
//*****************************************************************************
//
//! Fills a rectangle on a display.
//!
//! \param pDisplay is the pointer to the display driver structure for the
//! display to operate upon.
//! \param pRect is a pointer to the structure describing the rectangle to
//! fill.
//! \param ulValue is the color to fill the rectangle.
//!
//! This function fills a rectangle on the display. This assumes that clipping
//! has already been performed, and that all sides of the rectangle are within
//! the extents of the display.
//!
//! \return None.
//
//*****************************************************************************
#define DpyRectFill(pDisplay, pRect, ulValue) \
do \
{ \
const tDisplay *pD = pDisplay; \
pD->pfnRectFill(pD->pvDisplayData, pRect, ulValue); \
} \
while(0)
//*****************************************************************************
//
//! Gets the width of the display.
//!
//! \param pDisplay is a pointer to the display driver structure for the
//! display to query.
//!
//! This function determines the width of the display.
//!
//! \return Returns the width of the display in pixels.
//
//*****************************************************************************
#define DpyWidthGet(pDisplay) \
((pDisplay)->usWidth)
//*****************************************************************************
//
// Prototypes for the graphics library functions.
//
//*****************************************************************************
extern void GrCircleDraw(const tContext *pContext, long lX, long lY,
long lRadius);
extern void GrCircleFill(const tContext *pContext, long lX, long lY,
long lRadius);
extern void GrContextClipRegionSet(tContext *pContext, tRectangle *pRect);
extern void GrContextInit(tContext *pContext, const tDisplay *pDisplay);
extern void GrImageDraw(const tContext *pContext,
const unsigned char *pucImage, long lX, long lY);
extern void GrLineDraw(const tContext *pContext, long lX1, long lY1, long lX2,
long lY2);
extern void GrLineDrawH(const tContext *pContext, long lX1, long lX2, long lY);
extern void GrLineDrawV(const tContext *pContext, long lX, long lY1, long lY2);
extern void GrOffScreen1BPPInit(tDisplay *pDisplay, unsigned char *pucImage,
long lWidth, long lHeight);
extern void GrOffScreen4BPPInit(tDisplay *pDisplay, unsigned char *pucImage,
long lWidth, long lHeight);
extern void GrOffScreen4BPPPaletteSet(tDisplay *pDisplay,
unsigned long *pulPalette,
unsigned long ulOffset,
unsigned long ulCount);
extern void GrOffScreen8BPPInit(tDisplay *pDisplay, unsigned char *pucImage,
long lWidth, long lHeight);
extern void GrOffScreen8BPPPaletteSet(tDisplay *pDisplay,
unsigned long *pulPalette,
unsigned long ulOffset,
unsigned long ulCount);
extern void GrRectDraw(const tContext *pContext, const tRectangle *pRect);
extern void GrRectFill(const tContext *pContext, const tRectangle *pRect);
extern void GrStringDraw(const tContext *pContext, const char *pcString,
long lLength, long lX, long lY,
unsigned long bOpaque);
extern long GrStringWidthGet(const tContext *pContext, const char *pcString,
long lLength);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
#endif // __GRLIB_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/grlib.h | C | oos | 51,784 |
//*****************************************************************************
//
// hw_ethernet.h - Macros used when accessing the Ethernet hardware.
//
// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_ETHERNET_H__
#define __HW_ETHERNET_H__
//*****************************************************************************
//
// The following are defines for the MAC register offsets in the Ethernet
// Controller.
//
//*****************************************************************************
#define MAC_O_RIS 0x00000000 // Ethernet MAC Raw Interrupt
// Status
#define MAC_O_IACK 0x00000000 // Interrupt Acknowledge Register
#define MAC_O_IM 0x00000004 // Interrupt Mask Register
#define MAC_O_RCTL 0x00000008 // Receive Control Register
#define MAC_O_TCTL 0x0000000C // Transmit Control Register
#define MAC_O_DATA 0x00000010 // Data Register
#define MAC_O_IA0 0x00000014 // Individual Address Register 0
#define MAC_O_IA1 0x00000018 // Individual Address Register 1
#define MAC_O_THR 0x0000001C // Threshold Register
#define MAC_O_MCTL 0x00000020 // Management Control Register
#define MAC_O_MDV 0x00000024 // Management Divider Register
#define MAC_O_MTXD 0x0000002C // Management Transmit Data Reg
#define MAC_O_MRXD 0x00000030 // Management Receive Data Reg
#define MAC_O_NP 0x00000034 // Number of Packets Register
#define MAC_O_TR 0x00000038 // Transmission Request Register
#define MAC_O_TS 0x0000003C // Timer Support Register
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_IACK register.
//
//*****************************************************************************
#define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt
#define MAC_IACK_MDINT 0x00000020 // Clear MDI Transaction Complete
#define MAC_IACK_RXER 0x00000010 // Clear RX Error
#define MAC_IACK_FOV 0x00000008 // Clear RX FIFO Overrun
#define MAC_IACK_TXEMP 0x00000004 // Clear TX FIFO Empy
#define MAC_IACK_TXER 0x00000002 // Clear TX Error
#define MAC_IACK_RXINT 0x00000001 // Clear RX Packet Available
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_IM register.
//
//*****************************************************************************
#define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt
#define MAC_IM_MDINTM 0x00000020 // Mask MDI Transaction Complete
#define MAC_IM_RXERM 0x00000010 // Mask RX Error
#define MAC_IM_FOVM 0x00000008 // Mask RX FIFO Overrun
#define MAC_IM_TXEMPM 0x00000004 // Mask TX FIFO Empy
#define MAC_IM_TXERM 0x00000002 // Mask TX Error
#define MAC_IM_RXINTM 0x00000001 // Mask RX Packet Available
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_RCTL register.
//
//*****************************************************************************
#define MAC_RCTL_RSTFIFO 0x00000010 // Clear the Receive FIFO
#define MAC_RCTL_BADCRC 0x00000008 // Reject Packets With Bad CRC
#define MAC_RCTL_PRMS 0x00000004 // Enable Promiscuous Mode
#define MAC_RCTL_AMUL 0x00000002 // Enable Multicast Packets
#define MAC_RCTL_RXEN 0x00000001 // Enable Ethernet Receiver
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_TCTL register.
//
//*****************************************************************************
#define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex mode
#define MAC_TCTL_CRC 0x00000004 // Enable CRC Generation
#define MAC_TCTL_PADEN 0x00000002 // Enable Automatic Padding
#define MAC_TCTL_TXEN 0x00000001 // Enable Ethernet Transmitter
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_IA0 register.
//
//*****************************************************************************
#define MAC_IA0_MACOCT4_M 0xFF000000 // MAC Address Octet 4.
#define MAC_IA0_MACOCT3_M 0x00FF0000 // MAC Address Octet 3.
#define MAC_IA0_MACOCT2_M 0x0000FF00 // MAC Address Octet 2.
#define MAC_IA0_MACOCT1_M 0x000000FF // MAC Address Octet 1.
#define MAC_IA0_MACOCT4_S 24
#define MAC_IA0_MACOCT3_S 16
#define MAC_IA0_MACOCT2_S 8
#define MAC_IA0_MACOCT1_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_IA1 register.
//
//*****************************************************************************
#define MAC_IA1_MACOCT6_M 0x0000FF00 // MAC Address Octet 6.
#define MAC_IA1_MACOCT5_M 0x000000FF // MAC Address Octet 5.
#define MAC_IA1_MACOCT6_S 8
#define MAC_IA1_MACOCT5_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_TXTH register.
//
//*****************************************************************************
#define MAC_THR_THRESH_M 0x0000003F // Threshold Value.
#define MAC_THR_THRESH_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_MCTL register.
//
//*****************************************************************************
#define MAC_MCTL_REGADR_M 0x000000F8 // MII Register Address.
#define MAC_MCTL_WRITE 0x00000002 // Next MII Transaction is Write
#define MAC_MCTL_START 0x00000001 // Start MII Transaction
#define MAC_MCTL_REGADR_S 3
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_MDV register.
//
//*****************************************************************************
#define MAC_MDV_DIV_M 0x000000FF // Clock Divider.
#define MAC_MDV_DIV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_MTXD register.
//
//*****************************************************************************
#define MAC_MTXD_MDTX_M 0x0000FFFF // MII Register Transmit Data.
#define MAC_MTXD_MDTX_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_MRXD register.
//
//*****************************************************************************
#define MAC_MRXD_MDRX_M 0x0000FFFF // MII Register Receive Data.
#define MAC_MRXD_MDRX_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_NP register.
//
//*****************************************************************************
#define MAC_NP_NPR_M 0x0000003F // Number of Packets in Receive
// FIFO.
#define MAC_NP_NPR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_TXRQ register.
//
//*****************************************************************************
#define MAC_TR_NEWTX 0x00000001 // Start an Ethernet Transmission
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_TS register.
//
//*****************************************************************************
#define MAC_TS_TSEN 0x00000001 // Enable Timestamp Logic
//*****************************************************************************
//
// The following are defines for the Ethernet Controller PHY registers.
//
//*****************************************************************************
#define PHY_MR24 0x00000018 // Ethernet PHY Management Register
// 24 -MDI/MDIX Control
#define PHY_MR23 0x00000017 // Ethernet PHY Management Register
// 23 - LED Configuration
#define PHY_MR19 0x00000013 // Ethernet PHY Management Register
// 19 - Transceiver Control
#define PHY_MR18 0x00000012 // Ethernet PHY Management Register
// 18 - Diagnostic
#define PHY_MR17 0x00000011 // Ethernet PHY Management Register
// 17 - Interrupt Control/Status
#define PHY_MR16 0x00000010 // Ethernet PHY Management Register
// 16 - Vendor-Specific
#define PHY_MR6 0x00000006 // Ethernet PHY Management Register
// 6 - Auto-Negotiation Expansion
#define PHY_MR5 0x00000005 // Ethernet PHY Management Register
// 5 - Auto-Negotiation Link
// Partner Base Page Ability
#define PHY_MR4 0x00000004 // Ethernet PHY Management Register
// 4 - Auto-Negotiation
// Advertisement
#define PHY_MR3 0x00000003 // Ethernet PHY Management Register
// 3 - PHY Identifier 2
#define PHY_MR2 0x00000002 // Ethernet PHY Management Register
// 2 - PHY Identifier 1
#define PHY_MR1 0x00000001 // Ethernet PHY Management Register
// 1 - Status
#define PHY_MR0 0x00000000 // Ethernet PHY Management Register
// 0 - Control
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR0 register.
//
//*****************************************************************************
#define PHY_MR0_RESET 0x00008000 // Reset Registers.
#define PHY_MR0_LOOPBK 0x00004000 // Loopback Mode.
#define PHY_MR0_SPEEDSL 0x00002000 // Speed Select.
#define PHY_MR0_ANEGEN 0x00001000 // Auto-Negotiation Enable.
#define PHY_MR0_PWRDN 0x00000800 // Power Down.
#define PHY_MR0_ISO 0x00000400 // Isolate.
#define PHY_MR0_RANEG 0x00000200 // Restart Auto-Negotiation.
#define PHY_MR0_DUPLEX 0x00000100 // Set Duplex Mode.
#define PHY_MR0_COLT 0x00000080 // Collision Test.
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_O_RIS register.
//
//*****************************************************************************
#define MAC_RIS_PHYINT 0x00000040 // PHY Interrupt.
#define MAC_RIS_MDINT 0x00000020 // MII Transaction Complete.
#define MAC_RIS_RXER 0x00000010 // Receive Error.
#define MAC_RIS_FOV 0x00000008 // FIFO Overrrun.
#define MAC_RIS_TXEMP 0x00000004 // Transmit FIFO Empty.
#define MAC_RIS_TXER 0x00000002 // Transmit Error.
#define MAC_RIS_RXINT 0x00000001 // Packet Received.
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR1 register.
//
//*****************************************************************************
#define PHY_MR1_100X_F 0x00004000 // 100BASE-TX Full-Duplex Mode.
#define PHY_MR1_100X_H 0x00002000 // 100BASE-TX Half-Duplex Mode.
#define PHY_MR1_10T_F 0x00001000 // 10BASE-T Full-Duplex Mode.
#define PHY_MR1_10T_H 0x00000800 // 10BASE-T Half-Duplex Mode.
#define PHY_MR1_MFPS 0x00000040 // Management Frames with Preamble
// Suppressed.
#define PHY_MR1_ANEGC 0x00000020 // Auto-Negotiation Complete.
#define PHY_MR1_RFAULT 0x00000010 // Remote Fault.
#define PHY_MR1_ANEGA 0x00000008 // Auto-Negotiation.
#define PHY_MR1_LINK 0x00000004 // Link Made.
#define PHY_MR1_JAB 0x00000002 // Jabber Condition.
#define PHY_MR1_EXTD 0x00000001 // Extended Capabilities.
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR2 register.
//
//*****************************************************************************
#define PHY_MR2_OUI_M 0x0000FFFF // Organizationally Unique
// Identifier[21:6].
#define PHY_MR2_OUI_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR3 register.
//
//*****************************************************************************
#define PHY_MR3_OUI_M 0x0000FC00 // Organizationally Unique
// Identifier[5:0].
#define PHY_MR3_MN_M 0x000003F0 // Model Number.
#define PHY_MR3_RN_M 0x0000000F // Revision Number.
#define PHY_MR3_OUI_S 10
#define PHY_MR3_MN_S 4
#define PHY_MR3_RN_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR4 register.
//
//*****************************************************************************
#define PHY_MR4_NP 0x00008000 // Next Page.
#define PHY_MR4_RF 0x00002000 // Remote Fault.
#define PHY_MR4_A3 0x00000100 // Technology Ability Field[3].
#define PHY_MR4_A2 0x00000080 // Technology Ability Field[2].
#define PHY_MR4_A1 0x00000040 // Technology Ability Field[1].
#define PHY_MR4_A0 0x00000020 // Technology Ability Field[0].
#define PHY_MR4_S_M 0x0000001F // Selector Field.
#define PHY_MR4_S_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR5 register.
//
//*****************************************************************************
#define PHY_MR5_NP 0x00008000 // Next Page.
#define PHY_MR5_ACK 0x00004000 // Acknowledge.
#define PHY_MR5_RF 0x00002000 // Remote Fault.
#define PHY_MR5_A_M 0x00001FE0 // Technology Ability Field.
#define PHY_MR5_S_M 0x0000001F // Selector Field.
#define PHY_MR5_S_8023 0x00000001 // IEEE Std 802.3
#define PHY_MR5_S_8029 0x00000002 // IEEE Std 802.9 ISLAN-16T
#define PHY_MR5_S_8025 0x00000003 // IEEE Std 802.5
#define PHY_MR5_S_1394 0x00000004 // IEEE Std 1394
#define PHY_MR5_A_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR6 register.
//
//*****************************************************************************
#define PHY_MR6_PDF 0x00000010 // Parallel Detection Fault.
#define PHY_MR6_LPNPA 0x00000008 // Link Partner is Next Page Able.
#define PHY_MR6_PRX 0x00000002 // New Page Received.
#define PHY_MR6_LPANEGA 0x00000001 // Link Partner is Auto-Negotiation
// Able.
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_O_DATA register.
//
//*****************************************************************************
#define MAC_DATA_TXDATA_M 0xFFFFFFFF // Transmit FIFO Data.
#define MAC_DATA_RXDATA_M 0xFFFFFFFF // Receive FIFO Data.
#define MAC_DATA_RXDATA_S 0
#define MAC_DATA_TXDATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR16 register.
//
//*****************************************************************************
#define PHY_MR16_RPTR 0x00008000 // Repeater Mode.
#define PHY_MR16_INPOL 0x00004000 // Interrupt Polarity.
#define PHY_MR16_TXHIM 0x00001000 // Transmit High Impedance Mode.
#define PHY_MR16_SQEI 0x00000800 // SQE Inhibit Testing.
#define PHY_MR16_NL10 0x00000400 // Natural Loopback Mode.
#define PHY_MR16_APOL 0x00000020 // Auto-Polarity Disable.
#define PHY_MR16_RVSPOL 0x00000010 // Receive Data Polarity.
#define PHY_MR16_PCSBP 0x00000002 // PCS Bypass.
#define PHY_MR16_RXCC 0x00000001 // Receive Clock Control.
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR17 register.
//
//*****************************************************************************
#define PHY_MR17_JABBER_IE 0x00008000 // Jabber Interrupt Enable.
#define PHY_MR17_RXER_IE 0x00004000 // Receive Error Interrupt Enable.
#define PHY_MR17_PRX_IE 0x00002000 // Page Received Interrupt Enable.
#define PHY_MR17_PDF_IE 0x00001000 // Parallel Detection Fault
// Interrupt Enable.
#define PHY_MR17_LPACK_IE 0x00000800 // LP Acknowledge Interrupt Enable.
#define PHY_MR17_LSCHG_IE 0x00000400 // Link Status Change Interrupt
// Enable.
#define PHY_MR17_RFAULT_IE 0x00000200 // Remote Fault Interrupt Enable.
#define PHY_MR17_ANEGCOMP_IE 0x00000100 // Auto-Negotiation Complete
// Interrupt Enable.
#define PHY_MR17_JABBER_INT 0x00000080 // Jabber Event Interrupt.
#define PHY_MR17_RXER_INT 0x00000040 // Receive Error Interrupt.
#define PHY_MR17_PRX_INT 0x00000020 // Page Receive Interrupt.
#define PHY_MR17_PDF_INT 0x00000010 // Parallel Detection Fault
// Interrupt.
#define PHY_MR17_LPACK_INT 0x00000008 // LP Acknowledge Interrupt.
#define PHY_MR17_LSCHG_INT 0x00000004 // Link Status Change Interrupt.
#define PHY_MR17_RFAULT_INT 0x00000002 // Remote Fault Interrupt.
#define PHY_MR17_ANEGCOMP_INT 0x00000001 // Auto-Negotiation Complete
// Interrupt.
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR18 register.
//
//*****************************************************************************
#define PHY_MR18_ANEGF 0x00001000 // Auto-Negotiation Failure.
#define PHY_MR18_DPLX 0x00000800 // Duplex Mode.
#define PHY_MR18_RATE 0x00000400 // Rate.
#define PHY_MR18_RXSD 0x00000200 // Receive Detection.
#define PHY_MR18_RX_LOCK 0x00000100 // Receive PLL Lock.
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR19 register.
//
//*****************************************************************************
#define PHY_MR19_TXO_M 0x0000C000 // Transmit Amplitude Selection.
#define PHY_MR19_TXO_00DB 0x00000000 // Gain set for 0.0dB of insertion
// loss
#define PHY_MR19_TXO_04DB 0x00004000 // Gain set for 0.4dB of insertion
// loss
#define PHY_MR19_TXO_08DB 0x00008000 // Gain set for 0.8dB of insertion
// loss
#define PHY_MR19_TXO_12DB 0x0000C000 // Gain set for 1.2dB of insertion
// loss
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR23 register.
//
//*****************************************************************************
#define PHY_MR23_LED1_M 0x000000F0 // LED1 Source.
#define PHY_MR23_LED1_LINK 0x00000000 // Link OK
#define PHY_MR23_LED1_RXTX 0x00000010 // RX or TX Activity (Default LED1)
#define PHY_MR23_LED1_TX 0x00000020 // TX Activity
#define PHY_MR23_LED1_RX 0x00000030 // RX Activity
#define PHY_MR23_LED1_COL 0x00000040 // Collision
#define PHY_MR23_LED1_100 0x00000050 // 100BASE-TX mode
#define PHY_MR23_LED1_10 0x00000060 // 10BASE-T mode
#define PHY_MR23_LED1_DUPLEX 0x00000070 // Full-Duplex
#define PHY_MR23_LED1_LINKACT 0x00000080 // Link OK & Blink=RX or TX
// Activity
#define PHY_MR23_LED0_M 0x0000000F // LED0 Source.
#define PHY_MR23_LED0_LINK 0x00000000 // Link OK (Default LED0)
#define PHY_MR23_LED0_RXTX 0x00000001 // RX or TX Activity
#define PHY_MR23_LED0_TX 0x00000002 // TX Activity
#define PHY_MR23_LED0_RX 0x00000003 // RX Activity
#define PHY_MR23_LED0_COL 0x00000004 // Collision
#define PHY_MR23_LED0_100 0x00000005 // 100BASE-TX mode
#define PHY_MR23_LED0_10 0x00000006 // 10BASE-T mode
#define PHY_MR23_LED0_DUPLEX 0x00000007 // Full-Duplex
#define PHY_MR23_LED0_LINKACT 0x00000008 // Link OK & Blink=RX or TX
// Activity
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR24 register.
//
//*****************************************************************************
#define PHY_MR24_PD_MODE 0x00000080 // Parallel Detection Mode.
#define PHY_MR24_AUTO_SW 0x00000040 // Auto-Switching Enable.
#define PHY_MR24_MDIX 0x00000020 // Auto-Switching Configuration.
#define PHY_MR24_MDIX_CM 0x00000010 // Auto-Switching Complete.
#define PHY_MR24_MDIX_SD_M 0x0000000F // Auto-Switching Seed.
#define PHY_MR24_MDIX_SD_S 0
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the MAC register offsets in the
// Ethernet Controller.
//
//*****************************************************************************
#define MAC_O_IS 0x00000000 // Interrupt Status Register
#define MAC_O_MADD 0x00000028 // Management Address Register
//*****************************************************************************
//
// The following are deprecated defines for the reset values of the MAC
// registers.
//
//*****************************************************************************
#define MAC_RV_MDV 0x00000080
#define MAC_RV_IM 0x0000007F
#define MAC_RV_THR 0x0000003F
#define MAC_RV_RCTL 0x00000008
#define MAC_RV_IA0 0x00000000
#define MAC_RV_TCTL 0x00000000
#define MAC_RV_DATA 0x00000000
#define MAC_RV_MRXD 0x00000000
#define MAC_RV_TR 0x00000000
#define MAC_RV_IS 0x00000000
#define MAC_RV_NP 0x00000000
#define MAC_RV_MCTL 0x00000000
#define MAC_RV_MTXD 0x00000000
#define MAC_RV_IA1 0x00000000
#define MAC_RV_IACK 0x00000000
#define MAC_RV_MADD 0x00000000
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the MAC_IS
// register.
//
//*****************************************************************************
#define MAC_IS_PHYINT 0x00000040 // PHY Interrupt
#define MAC_IS_MDINT 0x00000020 // MDI Transaction Complete
#define MAC_IS_RXER 0x00000010 // RX Error
#define MAC_IS_FOV 0x00000008 // RX FIFO Overrun
#define MAC_IS_TXEMP 0x00000004 // TX FIFO Empy
#define MAC_IS_TXER 0x00000002 // TX Error
#define MAC_IS_RXINT 0x00000001 // RX Packet Available
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the MAC_IA0
// register.
//
//*****************************************************************************
#define MAC_IA0_MACOCT4 0xFF000000 // 4th Octet of MAC address
#define MAC_IA0_MACOCT3 0x00FF0000 // 3rd Octet of MAC address
#define MAC_IA0_MACOCT2 0x0000FF00 // 2nd Octet of MAC address
#define MAC_IA0_MACOCT1 0x000000FF // 1st Octet of MAC address
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the MAC_IA1
// register.
//
//*****************************************************************************
#define MAC_IA1_MACOCT6 0x0000FF00 // 6th Octet of MAC address
#define MAC_IA1_MACOCT5 0x000000FF // 5th Octet of MAC address
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the MAC_TXTH
// register.
//
//*****************************************************************************
#define MAC_THR_THRESH 0x0000003F // Transmit Threshold Value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the MAC_MCTL
// register.
//
//*****************************************************************************
#define MAC_MCTL_REGADR 0x000000F8 // Address for Next MII Transaction
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the MAC_MDV
// register.
//
//*****************************************************************************
#define MAC_MDV_DIV 0x000000FF // Clock Divider for MDC for TX
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the MAC_MTXD
// register.
//
//*****************************************************************************
#define MAC_MTXD_MDTX 0x0000FFFF // Data for Next MII Transaction
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the MAC_MRXD
// register.
//
//*****************************************************************************
#define MAC_MRXD_MDRX 0x0000FFFF // Data Read from Last MII Trans.
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the MAC_NP
// register.
//
//*****************************************************************************
#define MAC_NP_NPR 0x0000003F // Number of RX Frames in FIFO
#endif
#endif // __HW_ETHERNET_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/hw_ethernet.h | C | oos | 30,024 |
//*****************************************************************************
//
// hw_hibernate.h - Defines and Macros for the Hibernation module.
//
// Copyright (c) 2007-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_HIBERNATE_H__
#define __HW_HIBERNATE_H__
//*****************************************************************************
//
// The following are defines for the Hibernation module register addresses.
//
//*****************************************************************************
#define HIB_RTCC 0x400FC000 // Hibernate RTC counter
#define HIB_RTCM0 0x400FC004 // Hibernate RTC match 0
#define HIB_RTCM1 0x400FC008 // Hibernate RTC match 1
#define HIB_RTCLD 0x400FC00C // Hibernate RTC load
#define HIB_CTL 0x400FC010 // Hibernate RTC control
#define HIB_IM 0x400FC014 // Hibernate interrupt mask
#define HIB_RIS 0x400FC018 // Hibernate raw interrupt status
#define HIB_MIS 0x400FC01C // Hibernate masked interrupt stat
#define HIB_IC 0x400FC020 // Hibernate interrupt clear
#define HIB_RTCT 0x400FC024 // Hibernate RTC trim
#define HIB_DATA 0x400FC030 // Hibernate data area
//*****************************************************************************
//
// The following are defines for the bit fields in the Hibernate RTC counter
// register.
//
//*****************************************************************************
#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter.
#define HIB_RTCC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the Hibernate RTC match 0
// register.
//
//*****************************************************************************
#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0.
#define HIB_RTCM0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the Hibernate RTC match 1
// register.
//
//*****************************************************************************
#define HIB_RTCM1_M 0xFFFFFFFF // RTC Match 1.
#define HIB_RTCM1_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the Hibernate RTC load
// register.
//
//*****************************************************************************
#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load.
#define HIB_RTCLD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the Hibernate control
// register
//
//*****************************************************************************
#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable.
#define HIB_CTL_VABORT 0x00000080 // low bat abort
#define HIB_CTL_CLK32EN 0x00000040 // enable clock/oscillator
#define HIB_CTL_LOWBATEN 0x00000020 // enable low battery detect
#define HIB_CTL_PINWEN 0x00000010 // enable wake on WAKE pin
#define HIB_CTL_RTCWEN 0x00000008 // enable wake on RTC match
#define HIB_CTL_CLKSEL 0x00000004 // clock input selection
#define HIB_CTL_HIBREQ 0x00000002 // request hibernation
#define HIB_CTL_RTCEN 0x00000001 // RTC enable
//*****************************************************************************
//
// The following are defines for the bit fields in the Hibernate interrupt mask
// reg.
//
//*****************************************************************************
#define HIB_IM_EXTW 0x00000008 // wake from external pin interrupt
#define HIB_IM_LOWBAT 0x00000004 // low battery interrupt
#define HIB_IM_RTCALT1 0x00000002 // RTC match 1 interrupt
#define HIB_IM_RTCALT0 0x00000001 // RTC match 0 interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the Hibernate raw interrupt
// status.
//
//*****************************************************************************
#define HIB_RIS_EXTW 0x00000008 // wake from external pin interrupt
#define HIB_RIS_LOWBAT 0x00000004 // low battery interrupt
#define HIB_RIS_RTCALT1 0x00000002 // RTC match 1 interrupt
#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert0 Raw Interrupt Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the Hibernate masked int
// status.
//
//*****************************************************************************
#define HIB_MIS_EXTW 0x00000008 // wake from external pin interrupt
#define HIB_MIS_LOWBAT 0x00000004 // low battery interrupt
#define HIB_MIS_RTCALT1 0x00000002 // RTC match 1 interrupt
#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt
// Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the Hibernate interrupt
// clear reg.
//
//*****************************************************************************
#define HIB_IC_EXTW 0x00000008 // wake from external pin interrupt
#define HIB_IC_LOWBAT 0x00000004 // low battery interrupt
#define HIB_IC_RTCALT1 0x00000002 // RTC match 1 interrupt
#define HIB_IC_RTCALT0 0x00000001 // RTC match 0 interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the Hibernate RTC trim
// register.
//
//*****************************************************************************
#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value.
#define HIB_RTCT_TRIM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the Hibernate data register.
//
//*****************************************************************************
#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV
// Registers[63:0].
#define HIB_DATA_RTD_S 0
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the Hibernation module register
// addresses.
//
//*****************************************************************************
#define HIB_DATA_END 0x400FC130 // end of data area, exclusive
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the Hibernate RTC
// counter register.
//
//*****************************************************************************
#define HIB_RTCC_MASK 0xFFFFFFFF // RTC counter mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the Hibernate RTC
// match 0 register.
//
//*****************************************************************************
#define HIB_RTCM0_MASK 0xFFFFFFFF // RTC match 0 mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the Hibernate RTC
// match 1 register.
//
//*****************************************************************************
#define HIB_RTCM1_MASK 0xFFFFFFFF // RTC match 1 mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the Hibernate RTC
// load register.
//
//*****************************************************************************
#define HIB_RTCLD_MASK 0xFFFFFFFF // RTC load mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the Hibernate raw
// interrupt status.
//
//*****************************************************************************
#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the Hibernate
// masked int status.
//
//*****************************************************************************
#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the Hibernate RTC
// trim register.
//
//*****************************************************************************
#define HIB_RTCT_MASK 0x0000FFFF // RTC trim mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the Hibernate
// data register.
//
//*****************************************************************************
#define HIB_DATA_MASK 0xFFFFFFFF // NV memory data mask
#endif
#endif // __HW_HIBERNATE_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/hw_hibernate.h | C | oos | 11,214 |
//*****************************************************************************
//
// systick.h - Prototypes for the SysTick driver.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __SYSTICK_H__
#define __SYSTICK_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void SysTickEnable(void);
extern void SysTickDisable(void);
extern void SysTickIntRegister(void (*pfnHandler)(void));
extern void SysTickIntUnregister(void);
extern void SysTickIntEnable(void);
extern void SysTickIntDisable(void);
extern void SysTickPeriodSet(unsigned long ulPeriod);
extern unsigned long SysTickPeriodGet(void);
extern unsigned long SysTickValueGet(void);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __SYSTICK_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/systick.h | C | oos | 2,634 |
//*****************************************************************************
//
// hw_sysctl.h - Macros used when accessing the system control hardware.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_SYSCTL_H__
#define __HW_SYSCTL_H__
//*****************************************************************************
//
// The following are defines for the system control register addresses.
//
//*****************************************************************************
#define SYSCTL_DID0 0x400FE000 // Device identification register 0
#define SYSCTL_DID1 0x400FE004 // Device identification register 1
#define SYSCTL_DC0 0x400FE008 // Device capabilities register 0
#define SYSCTL_DC1 0x400FE010 // Device capabilities register 1
#define SYSCTL_DC2 0x400FE014 // Device capabilities register 2
#define SYSCTL_DC3 0x400FE018 // Device capabilities register 3
#define SYSCTL_DC4 0x400FE01C // Device capabilities register 4
#define SYSCTL_DC5 0x400FE020 // Device capabilities register 5
#define SYSCTL_DC6 0x400FE024 // Device capabilities register 6
#define SYSCTL_DC7 0x400FE028 // Device capabilities register 7
#define SYSCTL_PBORCTL 0x400FE030 // POR/BOR reset control register
#define SYSCTL_LDOPCTL 0x400FE034 // LDO power control register
#define SYSCTL_SRCR0 0x400FE040 // Software reset control reg 0
#define SYSCTL_SRCR1 0x400FE044 // Software reset control reg 1
#define SYSCTL_SRCR2 0x400FE048 // Software reset control reg 2
#define SYSCTL_RIS 0x400FE050 // Raw interrupt status register
#define SYSCTL_IMC 0x400FE054 // Interrupt mask/control register
#define SYSCTL_MISC 0x400FE058 // Interrupt status register
#define SYSCTL_RESC 0x400FE05C // Reset cause register
#define SYSCTL_RCC 0x400FE060 // Run-mode clock config register
#define SYSCTL_PLLCFG 0x400FE064 // PLL configuration register
#define SYSCTL_GPIOHSCTL 0x400FE06C // GPIO High Speed Control
#define SYSCTL_RCC2 0x400FE070 // Run-mode clock config register 2
#define SYSCTL_MOSCCTL 0x400FE07C // Main Oscillator Control
#define SYSCTL_RCGC0 0x400FE100 // Run-mode clock gating register 0
#define SYSCTL_RCGC1 0x400FE104 // Run-mode clock gating register 1
#define SYSCTL_RCGC2 0x400FE108 // Run-mode clock gating register 2
#define SYSCTL_SCGC0 0x400FE110 // Sleep-mode clock gating reg 0
#define SYSCTL_SCGC1 0x400FE114 // Sleep-mode clock gating reg 1
#define SYSCTL_SCGC2 0x400FE118 // Sleep-mode clock gating reg 2
#define SYSCTL_DCGC0 0x400FE120 // Deep Sleep-mode clock gate reg 0
#define SYSCTL_DCGC1 0x400FE124 // Deep Sleep-mode clock gate reg 1
#define SYSCTL_DCGC2 0x400FE128 // Deep Sleep-mode clock gate reg 2
#define SYSCTL_DSLPCLKCFG 0x400FE144 // Deep Sleep-mode clock config reg
#define SYSCTL_CLKVCLR 0x400FE150 // Clock verifcation clear register
#define SYSCTL_LDOARST 0x400FE160 // LDO reset control register
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_DID0 register.
//
//*****************************************************************************
#define SYSCTL_DID0_VER_M 0x70000000 // DID0 version mask
#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0
#define SYSCTL_DID0_VER_1 0x10000000 // DID0 version 1
#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class
#define SYSCTL_DID0_CLASS_SANDSTORM \
0x00000000 // Sandstorm-class Device
#define SYSCTL_DID0_CLASS_FURY 0x00010000 // Fury-class Device
#define SYSCTL_DID0_CLASS_DUSTDEVIL \
0x00030000 // DustDevil-class Device
#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major revision mask
#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device)
#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer
// revision)
#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer
// revision)
#define SYSCTL_DID0_MIN_M 0x000000FF // Minor revision mask
#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0
#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1
#define SYSCTL_DID0_MIN_2 0x00000002 // Minor revision 2
#define SYSCTL_DID0_MIN_3 0x00000003 // Minor revision 3
#define SYSCTL_DID0_MIN_4 0x00000004 // Minor revision 4
#define SYSCTL_DID0_MIN_5 0x00000005 // Minor revision 5
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_DID1 register.
//
//*****************************************************************************
#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version.
#define SYSCTL_DID1_VER_0 0x00000000 // Initial DID1 register format
// definition, indicating a
// Stellaris LM3Snnn device.
#define SYSCTL_DID1_VER_1 0x10000000 // First revision of the DID1
// register format, indicating a
// Stellaris Fury-class device.
#define SYSCTL_DID1_FAM_M 0x0F000000 // Family.
#define SYSCTL_DID1_FAM_STELLARIS \
0x00000000 // Stellaris family of
// microcontollers, that is, all
// devices with external part
// numbers starting with LM3S.
#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part number mask
#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101
#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102
#define SYSCTL_DID1_PRTNO_300 0x00190000 // LM3S300
#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301
#define SYSCTL_DID1_PRTNO_308 0x001A0000 // LM3S308
#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310
#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315
#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316
#define SYSCTL_DID1_PRTNO_317 0x00170000 // LM3S317
#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328
#define SYSCTL_DID1_PRTNO_600 0x002A0000 // LM3S600
#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601
#define SYSCTL_DID1_PRTNO_608 0x002B0000 // LM3S608
#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610
#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611
#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612
#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613
#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615
#define SYSCTL_DID1_PRTNO_617 0x00280000 // LM3S617
#define SYSCTL_DID1_PRTNO_618 0x00290000 // LM3S618
#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628
#define SYSCTL_DID1_PRTNO_800 0x00380000 // LM3S800
#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801
#define SYSCTL_DID1_PRTNO_808 0x00390000 // LM3S808
#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811
#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812
#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815
#define SYSCTL_DID1_PRTNO_817 0x00360000 // LM3S817
#define SYSCTL_DID1_PRTNO_818 0x00370000 // LM3S818
#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828
#define SYSCTL_DID1_PRTNO_1110 0x00BF0000 // LM3S1110
#define SYSCTL_DID1_PRTNO_1133 0x00C30000 // LM3S1133
#define SYSCTL_DID1_PRTNO_1138 0x00C50000 // LM3S1138
#define SYSCTL_DID1_PRTNO_1150 0x00C10000 // LM3S1150
#define SYSCTL_DID1_PRTNO_1162 0x00C40000 // LM3S1162
#define SYSCTL_DID1_PRTNO_1165 0x00C20000 // LM3S1165
#define SYSCTL_DID1_PRTNO_1332 0x00C60000 // LM3S1332
#define SYSCTL_DID1_PRTNO_1435 0x00BC0000 // LM3S1435
#define SYSCTL_DID1_PRTNO_1439 0x00BA0000 // LM3S1439
#define SYSCTL_DID1_PRTNO_1512 0x00BB0000 // LM3S1512
#define SYSCTL_DID1_PRTNO_1538 0x00C70000 // LM3S1538
#define SYSCTL_DID1_PRTNO_1601 0x00DB0000 // LM3S1601
#define SYSCTL_DID1_PRTNO_1607 0x00060000 // LM3S1607
#define SYSCTL_DID1_PRTNO_1608 0x00DA0000 // LM3S1608
#define SYSCTL_DID1_PRTNO_1620 0x00C00000 // LM3S1620
#define SYSCTL_DID1_PRTNO_1625 0x00030000 // LM3S1625
#define SYSCTL_DID1_PRTNO_1626 0x00040000 // LM3S1626
#define SYSCTL_DID1_PRTNO_1627 0x00050000 // LM3S1627
#define SYSCTL_DID1_PRTNO_1635 0x00B30000 // LM3S1635
#define SYSCTL_DID1_PRTNO_1637 0x00BD0000 // LM3S1637
#define SYSCTL_DID1_PRTNO_1751 0x00B90000 // LM3S1751
#define SYSCTL_DID1_PRTNO_1776 0x00100000 // LM3S1776
#define SYSCTL_DID1_PRTNO_1850 0x00B40000 // LM3S1850
#define SYSCTL_DID1_PRTNO_1911 0x00DD0000 // LM3S1911
#define SYSCTL_DID1_PRTNO_1918 0x00DC0000 // LM3S1918
#define SYSCTL_DID1_PRTNO_1937 0x00B70000 // LM3S1937
#define SYSCTL_DID1_PRTNO_1958 0x00BE0000 // LM3S1958
#define SYSCTL_DID1_PRTNO_1960 0x00B50000 // LM3S1960
#define SYSCTL_DID1_PRTNO_1968 0x00B80000 // LM3S1968
#define SYSCTL_DID1_PRTNO_2110 0x00510000 // LM3S2110
#define SYSCTL_DID1_PRTNO_2139 0x00840000 // LM3S2139
#define SYSCTL_DID1_PRTNO_2276 0x00390000 // LM3S2276
#define SYSCTL_DID1_PRTNO_2410 0x00A20000 // LM3S2410
#define SYSCTL_DID1_PRTNO_2412 0x00590000 // LM3S2412
#define SYSCTL_DID1_PRTNO_2432 0x00560000 // LM3S2432
#define SYSCTL_DID1_PRTNO_2533 0x005A0000 // LM3S2533
#define SYSCTL_DID1_PRTNO_2601 0x00E10000 // LM3S2601
#define SYSCTL_DID1_PRTNO_2608 0x00E00000 // LM3S2608
#define SYSCTL_DID1_PRTNO_2616 0x00330000 // LM3S2616
#define SYSCTL_DID1_PRTNO_2620 0x00570000 // LM3S2620
#define SYSCTL_DID1_PRTNO_2637 0x00850000 // LM3S2637
#define SYSCTL_DID1_PRTNO_2651 0x00530000 // LM3S2651
#define SYSCTL_DID1_PRTNO_2671 0x00800000 // LM3S2671
#define SYSCTL_DID1_PRTNO_2678 0x00500000 // LM3S2678
#define SYSCTL_DID1_PRTNO_2730 0x00A40000 // LM3S2730
#define SYSCTL_DID1_PRTNO_2739 0x00520000 // LM3S2739
#define SYSCTL_DID1_PRTNO_2776 0x003A0000 // LM3S2776
#define SYSCTL_DID1_PRTNO_2911 0x00E30000 // LM3S2911
#define SYSCTL_DID1_PRTNO_2918 0x00E20000 // LM3S2918
#define SYSCTL_DID1_PRTNO_2939 0x00540000 // LM3S2939
#define SYSCTL_DID1_PRTNO_2948 0x008F0000 // LM3S2948
#define SYSCTL_DID1_PRTNO_2950 0x00580000 // LM3S2950
#define SYSCTL_DID1_PRTNO_2965 0x00550000 // LM3S2965
#define SYSCTL_DID1_PRTNO_3651 0x00430000 // LM3S3651
#define SYSCTL_DID1_PRTNO_3739 0x00440000 // LM3S3739
#define SYSCTL_DID1_PRTNO_3748 0x00490000 // LM3S3748
#define SYSCTL_DID1_PRTNO_3749 0x00450000 // LM3S3749
#define SYSCTL_DID1_PRTNO_3759 0x00460000 // LM3S3759
#define SYSCTL_DID1_PRTNO_3768 0x00480000 // LM3S3768
#define SYSCTL_DID1_PRTNO_5632 0x00810000 // LM3S5632
#define SYSCTL_DID1_PRTNO_5652 0x008A0000 // LM3S5652
#define SYSCTL_DID1_PRTNO_5662 0x00910000 // LM3S5662
#define SYSCTL_DID1_PRTNO_5732 0x00960000 // LM3S5732
#define SYSCTL_DID1_PRTNO_5737 0x00970000 // LM3S5737
#define SYSCTL_DID1_PRTNO_5739 0x00A00000 // LM3S5739
#define SYSCTL_DID1_PRTNO_5747 0x00990000 // LM3S5747
#define SYSCTL_DID1_PRTNO_5749 0x00A70000 // LM3S5749
#define SYSCTL_DID1_PRTNO_5752 0x009A0000 // LM3S5752
#define SYSCTL_DID1_PRTNO_5757 0x009B0000 // LM3S5757
#define SYSCTL_DID1_PRTNO_5762 0x009C0000 // LM3S5762
#define SYSCTL_DID1_PRTNO_5767 0x009D0000 // LM3S5767
#define SYSCTL_DID1_PRTNO_5768 0x00A90000 // LM3S5768
#define SYSCTL_DID1_PRTNO_5769 0x00A80000 // LM3S5769
#define SYSCTL_DID1_PRTNO_6100 0x00A10000 // LM3S6100
#define SYSCTL_DID1_PRTNO_6110 0x00740000 // LM3S6110
#define SYSCTL_DID1_PRTNO_6420 0x00A50000 // LM3S6420
#define SYSCTL_DID1_PRTNO_6422 0x00820000 // LM3S6422
#define SYSCTL_DID1_PRTNO_6432 0x00750000 // LM3S6432
#define SYSCTL_DID1_PRTNO_6537 0x00760000 // LM3S6537
#define SYSCTL_DID1_PRTNO_6610 0x00710000 // LM3S6610
#define SYSCTL_DID1_PRTNO_6611 0x00E70000 // LM3S6611
#define SYSCTL_DID1_PRTNO_6618 0x00E60000 // LM3S6618
#define SYSCTL_DID1_PRTNO_6633 0x00830000 // LM3S6633
#define SYSCTL_DID1_PRTNO_6637 0x008B0000 // LM3S6637
#define SYSCTL_DID1_PRTNO_6730 0x00A30000 // LM3S6730
#define SYSCTL_DID1_PRTNO_6753 0x00770000 // LM3S6753
#define SYSCTL_DID1_PRTNO_6911 0x00E90000 // LM3S6911
#define SYSCTL_DID1_PRTNO_6918 0x00E80000 // LM3S6918
#define SYSCTL_DID1_PRTNO_6938 0x00890000 // LM3S6938
#define SYSCTL_DID1_PRTNO_6950 0x00720000 // LM3S6950
#define SYSCTL_DID1_PRTNO_6952 0x00780000 // LM3S6952
#define SYSCTL_DID1_PRTNO_6965 0x00730000 // LM3S6965
#define SYSCTL_DID1_PRTNO_8530 0x00640000 // LM3S8530
#define SYSCTL_DID1_PRTNO_8538 0x008E0000 // LM3S8538
#define SYSCTL_DID1_PRTNO_8630 0x00610000 // LM3S8630
#define SYSCTL_DID1_PRTNO_8730 0x00630000 // LM3S8730
#define SYSCTL_DID1_PRTNO_8733 0x008D0000 // LM3S8733
#define SYSCTL_DID1_PRTNO_8738 0x00860000 // LM3S8738
#define SYSCTL_DID1_PRTNO_8930 0x00650000 // LM3S8930
#define SYSCTL_DID1_PRTNO_8933 0x008C0000 // LM3S8933
#define SYSCTL_DID1_PRTNO_8938 0x00880000 // LM3S8938
#define SYSCTL_DID1_PRTNO_8962 0x00A60000 // LM3S8962
#define SYSCTL_DID1_PRTNO_8970 0x00620000 // LM3S8970
#define SYSCTL_DID1_PRTNO_8971 0x00D70000 // LM3S8971
#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count.
#define SYSCTL_DID1_PINCNT_28 0x00000000 // 28 pin package
#define SYSCTL_DID1_PINCNT_48 0x00002000 // 48 pin package
#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100 pin package
#define SYSCTL_DID1_PINCNT_64 0x00006000 // 64 pin package
#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature range mask
#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C)
#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C)
#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range (-40C
// to 105C)
#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type.
#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package
#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC
#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP
#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant
#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification status mask
#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified)
#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified)
#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified
#define SYSCTL_DID1_PRTNO_S 16 // Part number shift
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_DC0 register.
//
//*****************************************************************************
#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM size mask
#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM
#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash size mask
#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of flash
#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of flash
#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of flash
#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of flash
#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of flash
#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of flash
#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of flash
#define SYSCTL_DC0_SRAMSZ_S 16 // SRAM size shift
#define SYSCTL_DC0_FLASHSZ_S 0 // Flash size shift
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_DC1 register.
//
//*****************************************************************************
#define SYSCTL_DC1_CAN2 0x04000000 // CAN2 module present
#define SYSCTL_DC1_CAN1 0x02000000 // CAN1 module present
#define SYSCTL_DC1_CAN0 0x01000000 // CAN0 module present
#define SYSCTL_DC1_PWM 0x00100000 // PWM module present
#define SYSCTL_DC1_ADC 0x00010000 // ADC module present
#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider.
#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock
// with a PLL divider of 4.
#define SYSCTL_DC1_MINSYSDIV_25 0x00007000 // Specifies a 25-MHz clock with a
// PLL divider of 8.
#define SYSCTL_DC1_MINSYSDIV_20 0x00009000 // Specifies a 20-MHz clock with a
// PLL divider of 10.
#define SYSCTL_DC1_ADCSPD_M 0x00000F00 // ADC speed mask
#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC
#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC
#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC
#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC
#define SYSCTL_DC1_MPU 0x00000080 // Cortex-M3 MPU present
#define SYSCTL_DC1_HIB 0x00000040 // Hibernation module present
#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present
#define SYSCTL_DC1_PLL 0x00000010 // PLL present
#define SYSCTL_DC1_WDT 0x00000008 // Watchdog Timer Present.
#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present
#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present
#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_DC2 register.
//
//*****************************************************************************
#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present
#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present
#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present
#define SYSCTL_DC2_TIMER3 0x00080000 // Timer 3 present
#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present
#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present
#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present
#define SYSCTL_DC2_I2C1 0x00004000 // I2C 1 present
#define SYSCTL_DC2_I2C0 0x00001000 // I2C 0 present
#define SYSCTL_DC2_QEI1 0x00000200 // QEI 1 present
#define SYSCTL_DC2_QEI0 0x00000100 // QEI 0 present
#define SYSCTL_DC2_SSI1 0x00000020 // SSI 1 present
#define SYSCTL_DC2_SSI0 0x00000010 // SSI 0 present
#define SYSCTL_DC2_UART2 0x00000004 // UART 2 present
#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present
#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_DC3 register.
//
//*****************************************************************************
#define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Pin Present.
#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present
#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present
#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present
#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present
#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present
#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present
#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present
#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present
#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present
#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present
#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present
#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present
#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present
#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present
#define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present.
#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present
#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present
#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present
#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present
#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present
#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present
#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present
#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present
#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present
#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present
#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present
#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present
#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present
#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present
#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_DC4 register.
//
//*****************************************************************************
#define SYSCTL_DC4_ETH 0x50000000 // Ethernet present
#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY0 Present.
#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC0 Present.
#define SYSCTL_DC4_E1588 0x01000000 // 1588 Capable.
#define SYSCTL_DC4_CCP7 0x00008000 // CCP7 Pin Present.
#define SYSCTL_DC4_CCP6 0x00004000 // CCP6 Pin Present.
#define SYSCTL_DC4_UDMA 0x00002000 // Micro-DMA is present.
#define SYSCTL_DC4_ROM 0x00001000 // Internal Code ROM is present.
#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO port H present
#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO port G present
#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO port F present
#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present
#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present
#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present
#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present
#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_PBORCTL register.
//
//*****************************************************************************
#define SYSCTL_PBORCTL_BORTIM_M 0x0000FFFC // BOR Time Delay.
#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset
#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise
#define SYSCTL_PBORCTL_BORTIM_S 2
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_LDOPCTL register.
//
//*****************************************************************************
#define SYSCTL_LDOPCTL_M 0x0000003F // LDO Output Voltage.
#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V
#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V
#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V
#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V
#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V
#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V
#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V
#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V
#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V
#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V
#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_RESC register.
//
//*****************************************************************************
#define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset.
#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset
#define SYSCTL_RESC_SW 0x00000010 // Software reset
#define SYSCTL_RESC_WDT 0x00000008 // Watchdog Timer Reset.
#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset
#define SYSCTL_RESC_POR 0x00000002 // Power on reset
#define SYSCTL_RESC_EXT 0x00000001 // External reset
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_RCC register.
//
//*****************************************************************************
#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating
#define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor.
#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2
#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3
#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4
#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5
#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6
#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7
#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8
#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9
#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10
#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11
#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12
#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13
#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14
#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15
#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16
#define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider.
#define SYSCTL_RCC_USEPWMDIV 0x00100000 // Enable PWM Clock Divisor.
#define SYSCTL_RCC_PWMDIV_M 0x000E0000 // PWM clock divider
#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2
#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4
#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8
#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16
#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32
#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64
#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down
#define SYSCTL_RCC_OEN 0x00001000 // PLL Output Enable.
#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass
#define SYSCTL_RCC_XTAL_M 0x000007C0 // Crystal attached to main osc
#define SYSCTL_RCC_XTAL_1MHZ 0x00000000 // Using a 1MHz crystal
#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040 // Using a 1.8432MHz crystal
#define SYSCTL_RCC_XTAL_2MHZ 0x00000080 // Using a 2MHz crystal
#define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0 // Using a 2.4576MHz crystal
#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal
#define SYSCTL_RCC_XTAL_3_68MHZ 0x00000140 // Using a 3.6864MHz crystal
#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // Using a 4MHz crystal
#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal
#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal
#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal
#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal
#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal
#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal
#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal
#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal
#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal
#define SYSCTL_RCC_XTAL_10MHZ 0x00000400 // 10.0 MHz (USB)
#define SYSCTL_RCC_XTAL_12MHZ 0x00000440 // 12.0 MHz (USB)
#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 // 12.288 MHz
#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 // 13.56 MHz
#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 // 14.31818 MHz
#define SYSCTL_RCC_XTAL_16MHZ 0x00000540 // 16.0 MHz (USB)
#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 // 16.384 MHz
#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable
#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator input select
#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator
#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator
#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4
#define SYSCTL_RCC_OSCSRC_30 0x00000030 // 30 KHz internal oscillator
#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en
#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en
#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable
#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable
#define SYSCTL_RCC_SYSDIV_S 23 // Shift to the SYSDIV field
#define SYSCTL_RCC_PWMDIV_S 17 // Shift to the PWMDIV field
#define SYSCTL_RCC_XTAL_S 6 // Shift to the XTAL field
#define SYSCTL_RCC_OSCSRC_S 4 // Shift to the OSCSRC field
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_PLLCFG register.
//
//*****************************************************************************
#define SYSCTL_PLLCFG_OD_M 0x0000C000 // Output divider
#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1
#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2
#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4
#define SYSCTL_PLLCFG_F_M 0x00003FE0 // PLL F Value.
#define SYSCTL_PLLCFG_R_M 0x0000001F // PLL R Value.
#define SYSCTL_PLLCFG_F_S 5
#define SYSCTL_PLLCFG_R_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_RCC2 register.
//
//*****************************************************************************
#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2
#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System clock divider
#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2
#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3
#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4
#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5
#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6
#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7
#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8
#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9
#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10
#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11
#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12
#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13
#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14
#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15
#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16
#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17
#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18
#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19
#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20
#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21
#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22
#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23
#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24
#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25
#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26
#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27
#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28
#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29
#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30
#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31
#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32
#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33
#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34
#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35
#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36
#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37
#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38
#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39
#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40
#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41
#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42
#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43
#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44
#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45
#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46
#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47
#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48
#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49
#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50
#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51
#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52
#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53
#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54
#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55
#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56
#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57
#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58
#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59
#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60
#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61
#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62
#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63
#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64
#define SYSCTL_RCC2_USBPWRDN 0x00004000 // Power-Down USB PLL.
#define SYSCTL_RCC2_PWRDN2 0x00002000 // PLL power down
#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL bypass
#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // System Clock Source.
#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // Use the main oscillator
#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // Use the internal oscillator
#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // Use the internal oscillator / 4
#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // Use the 30 KHz internal osc.
#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // Use the 32 KHz external osc.
#define SYSCTL_RCC2_SYSDIV2_S 23 // Shift to the SYSDIV2 field
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG
// register.
//
//*****************************************************************************
#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override.
#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2
#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3
#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4
#define SYSCTL_DSLPCLKCFG_D_5 0x02000000 // System clock /5
#define SYSCTL_DSLPCLKCFG_D_6 0x02800000 // System clock /6
#define SYSCTL_DSLPCLKCFG_D_7 0x03000000 // System clock /7
#define SYSCTL_DSLPCLKCFG_D_8 0x03800000 // System clock /8
#define SYSCTL_DSLPCLKCFG_D_9 0x04000000 // System clock /9
#define SYSCTL_DSLPCLKCFG_D_10 0x04800000 // System clock /10
#define SYSCTL_DSLPCLKCFG_D_11 0x05000000 // System clock /11
#define SYSCTL_DSLPCLKCFG_D_12 0x05800000 // System clock /12
#define SYSCTL_DSLPCLKCFG_D_13 0x06000000 // System clock /13
#define SYSCTL_DSLPCLKCFG_D_14 0x06800000 // System clock /14
#define SYSCTL_DSLPCLKCFG_D_15 0x07000000 // System clock /15
#define SYSCTL_DSLPCLKCFG_D_16 0x07800000 // System clock /16
#define SYSCTL_DSLPCLKCFG_D_17 0x08000000 // System clock /17
#define SYSCTL_DSLPCLKCFG_D_18 0x08800000 // System clock /18
#define SYSCTL_DSLPCLKCFG_D_19 0x09000000 // System clock /19
#define SYSCTL_DSLPCLKCFG_D_20 0x09800000 // System clock /20
#define SYSCTL_DSLPCLKCFG_D_21 0x0A000000 // System clock /21
#define SYSCTL_DSLPCLKCFG_D_22 0x0A800000 // System clock /22
#define SYSCTL_DSLPCLKCFG_D_23 0x0B000000 // System clock /23
#define SYSCTL_DSLPCLKCFG_D_24 0x0B800000 // System clock /24
#define SYSCTL_DSLPCLKCFG_D_25 0x0C000000 // System clock /25
#define SYSCTL_DSLPCLKCFG_D_26 0x0C800000 // System clock /26
#define SYSCTL_DSLPCLKCFG_D_27 0x0D000000 // System clock /27
#define SYSCTL_DSLPCLKCFG_D_28 0x0D800000 // System clock /28
#define SYSCTL_DSLPCLKCFG_D_29 0x0E000000 // System clock /29
#define SYSCTL_DSLPCLKCFG_D_30 0x0E800000 // System clock /30
#define SYSCTL_DSLPCLKCFG_D_31 0x0F000000 // System clock /31
#define SYSCTL_DSLPCLKCFG_D_32 0x0F800000 // System clock /32
#define SYSCTL_DSLPCLKCFG_D_33 0x10000000 // System clock /33
#define SYSCTL_DSLPCLKCFG_D_34 0x10800000 // System clock /34
#define SYSCTL_DSLPCLKCFG_D_35 0x11000000 // System clock /35
#define SYSCTL_DSLPCLKCFG_D_36 0x11800000 // System clock /36
#define SYSCTL_DSLPCLKCFG_D_37 0x12000000 // System clock /37
#define SYSCTL_DSLPCLKCFG_D_38 0x12800000 // System clock /38
#define SYSCTL_DSLPCLKCFG_D_39 0x13000000 // System clock /39
#define SYSCTL_DSLPCLKCFG_D_40 0x13800000 // System clock /40
#define SYSCTL_DSLPCLKCFG_D_41 0x14000000 // System clock /41
#define SYSCTL_DSLPCLKCFG_D_42 0x14800000 // System clock /42
#define SYSCTL_DSLPCLKCFG_D_43 0x15000000 // System clock /43
#define SYSCTL_DSLPCLKCFG_D_44 0x15800000 // System clock /44
#define SYSCTL_DSLPCLKCFG_D_45 0x16000000 // System clock /45
#define SYSCTL_DSLPCLKCFG_D_46 0x16800000 // System clock /46
#define SYSCTL_DSLPCLKCFG_D_47 0x17000000 // System clock /47
#define SYSCTL_DSLPCLKCFG_D_48 0x17800000 // System clock /48
#define SYSCTL_DSLPCLKCFG_D_49 0x18000000 // System clock /49
#define SYSCTL_DSLPCLKCFG_D_50 0x18800000 // System clock /50
#define SYSCTL_DSLPCLKCFG_D_51 0x19000000 // System clock /51
#define SYSCTL_DSLPCLKCFG_D_52 0x19800000 // System clock /52
#define SYSCTL_DSLPCLKCFG_D_53 0x1A000000 // System clock /53
#define SYSCTL_DSLPCLKCFG_D_54 0x1A800000 // System clock /54
#define SYSCTL_DSLPCLKCFG_D_55 0x1B000000 // System clock /55
#define SYSCTL_DSLPCLKCFG_D_56 0x1B800000 // System clock /56
#define SYSCTL_DSLPCLKCFG_D_57 0x1C000000 // System clock /57
#define SYSCTL_DSLPCLKCFG_D_58 0x1C800000 // System clock /58
#define SYSCTL_DSLPCLKCFG_D_59 0x1D000000 // System clock /59
#define SYSCTL_DSLPCLKCFG_D_60 0x1D800000 // System clock /60
#define SYSCTL_DSLPCLKCFG_D_61 0x1E000000 // System clock /61
#define SYSCTL_DSLPCLKCFG_D_62 0x1E800000 // System clock /62
#define SYSCTL_DSLPCLKCFG_D_63 0x1F000000 // System clock /63
#define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64
#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source.
#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // Do not override
#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // Use the internal oscillator
#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // Use the 30 KHz internal osc.
#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // Use the 32 KHz external osc.
#define SYSCTL_DSLPCLKCFG_IOSC 0x00000001 // IOSC Clock Source.
#define SYSCTL_DSLPCLKCFG_D_S 23
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_CLKVCLR register.
//
//*****************************************************************************
#define SYSCTL_CLKVCLR_VERCLR 0x00000001 // Clock Verification Clear.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_LDOARST register.
//
//*****************************************************************************
#define SYSCTL_LDOARST_LDOARST 0x00000001 // LDO Reset.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_SRCR0 register.
//
//*****************************************************************************
#define SYSCTL_SRCR0_CAN2 0x04000000 // CAN2 Reset Control.
#define SYSCTL_SRCR0_CAN1 0x02000000 // CAN1 Reset Control.
#define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control.
#define SYSCTL_SRCR0_PWM 0x00100000 // PWM Reset Control.
#define SYSCTL_SRCR0_ADC 0x00010000 // ADC0 Reset Control.
#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control.
#define SYSCTL_SRCR0_WDT 0x00000008 // WDT Reset Control.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_SRCR1 register.
//
//*****************************************************************************
#define SYSCTL_SRCR1_COMP2 0x04000000 // Analog Comp 2 Reset Control.
#define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control.
#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control.
#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control.
#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control.
#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control.
#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control.
#define SYSCTL_SRCR1_I2C1 0x00004000 // I2C1 Reset Control.
#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control.
#define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control.
#define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control.
#define SYSCTL_SRCR1_SSI1 0x00000020 // SSI1 Reset Control.
#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control.
#define SYSCTL_SRCR1_UART2 0x00000004 // UART2 Reset Control.
#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control.
#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_SRCR2 register.
//
//*****************************************************************************
#define SYSCTL_SRCR2_EPHY0 0x40000000 // PHY0 Reset Control.
#define SYSCTL_SRCR2_EMAC0 0x10000000 // MAC0 Reset Control.
#define SYSCTL_SRCR2_USB0 0x00010000 // USB0 Reset Control.
#define SYSCTL_SRCR2_UDMA 0x00002000 // UDMA Reset Control.
#define SYSCTL_SRCR2_GPIOH 0x00000080 // Port H Reset Control.
#define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control.
#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control.
#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control.
#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control.
#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control.
#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control.
#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_RIS register.
//
//*****************************************************************************
#define SYSCTL_RIS_MOSCPUPRIS 0x00000100 // MOSC Power Up Raw Interrupt
// Status.
#define SYSCTL_RIS_USBPLLLRIS 0x00000080 // USB PLL Lock Raw Interrupt
// Status.
#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status.
#define SYSCTL_RIS_CLRIS 0x00000020 // Current Limit Raw Interrupt
// Status.
#define SYSCTL_RIS_IOFRIS 0x00000010 // Internal Oscillator Fault Raw
// Interrupt Status.
#define SYSCTL_RIS_MOFRIS 0x00000008 // Main Oscillator Fault Raw
// Interrupt Status.
#define SYSCTL_RIS_LDORIS 0x00000004 // LDO Power Unregulated Raw
// Interrupt Status.
#define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt
// Status.
#define SYSCTL_RIS_PLLFRIS 0x00000001 // PLL Fault Raw Interrupt Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_IMC register.
//
//*****************************************************************************
#define SYSCTL_IMC_MOSCPUPIM 0x00000100 // MOSC Power Up Interrupt Mask.
#define SYSCTL_IMC_USBPLLLIM 0x00000080 // USB PLL Lock Interrupt Mask.
#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask.
#define SYSCTL_IMC_CLIM 0x00000020 // Current Limit Interrupt Mask.
#define SYSCTL_IMC_IOFIM 0x00000010 // Internal Oscillator Fault
// Interrupt Mask.
#define SYSCTL_IMC_MOFIM 0x00000008 // Main Oscillator Fault Interrupt
// Mask.
#define SYSCTL_IMC_LDOIM 0x00000004 // LDO Power Unregulated Interrupt
// Mask.
#define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask.
#define SYSCTL_IMC_PLLFIM 0x00000001 // PLL Fault Interrupt Mask.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_MISC register.
//
//*****************************************************************************
#define SYSCTL_MISC_MOSCPUPMIS 0x00000100 // MOSC Power Up Masked Interrupt
// Status.
#define SYSCTL_MISC_USBPLLLMIS 0x00000080 // USB PLL Lock Masked Interrupt
// Status.
#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt
// Status.
#define SYSCTL_MISC_CLMIS 0x00000020 // Current Limit Masked Interrupt
// Status.
#define SYSCTL_MISC_IOFMIS 0x00000010 // Internal Oscillator Fault Masked
// Interrupt Status.
#define SYSCTL_MISC_MOFMIS 0x00000008 // Main Oscillator Fault Masked
// Interrupt Status.
#define SYSCTL_MISC_LDOMIS 0x00000004 // LDO Power Unregulated Masked
// Interrupt Status.
#define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_RCGC0 register.
//
//*****************************************************************************
#define SYSCTL_RCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control.
#define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control.
#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control.
#define SYSCTL_RCGC0_PWM 0x00100000 // PWM Clock Gating Control.
#define SYSCTL_RCGC0_ADC 0x00010000 // ADC0 Clock Gating Control.
#define SYSCTL_RCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed.
#define SYSCTL_RCGC0_ADCSPD125K 0x00000000 // 125K samples/second
#define SYSCTL_RCGC0_ADCSPD250K 0x00000100 // 250K samples/second
#define SYSCTL_RCGC0_ADCSPD500K 0x00000200 // 500K samples/second
#define SYSCTL_RCGC0_ADCSPD1M 0x00000300 // 1M samples/second
#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control.
#define SYSCTL_RCGC0_WDT 0x00000008 // WDT Clock Gating Control.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_RCGC1 register.
//
//*****************************************************************************
#define SYSCTL_RCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock
// Gating.
#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock
// Gating.
#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock
// Gating.
#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control.
#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control.
#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control.
#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control.
#define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control.
#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control.
#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control.
#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control.
#define SYSCTL_RCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control.
#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control.
#define SYSCTL_RCGC1_UART2 0x00000004 // UART2 Clock Gating Control.
#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control.
#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_RCGC2 register.
//
//*****************************************************************************
#define SYSCTL_RCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control.
#define SYSCTL_RCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control.
#define SYSCTL_RCGC2_USB0 0x00010000 // USB0 Clock Gating Control.
#define SYSCTL_RCGC2_UDMA 0x00002000 // UDMA Clock Gating Control.
#define SYSCTL_RCGC2_GPIOH 0x00000080 // Port H Clock Gating Control.
#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control.
#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control.
#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control.
#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control.
#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control.
#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control.
#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_SCGC0 register.
//
//*****************************************************************************
#define SYSCTL_SCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control.
#define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control.
#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control.
#define SYSCTL_SCGC0_PWM 0x00100000 // PWM Clock Gating Control.
#define SYSCTL_SCGC0_ADC 0x00010000 // ADC0 Clock Gating Control.
#define SYSCTL_SCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed.
#define SYSCTL_SCGC0_ADCSPD125K 0x00000000 // 125K samples/second
#define SYSCTL_SCGC0_ADCSPD250K 0x00000100 // 250K samples/second
#define SYSCTL_SCGC0_ADCSPD500K 0x00000200 // 500K samples/second
#define SYSCTL_SCGC0_ADCSPD1M 0x00000300 // 1M samples/second
#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control.
#define SYSCTL_SCGC0_WDT 0x00000008 // WDT Clock Gating Control.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_SCGC1 register.
//
//*****************************************************************************
#define SYSCTL_SCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock
// Gating.
#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock
// Gating.
#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock
// Gating.
#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control.
#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control.
#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control.
#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control.
#define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control.
#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control.
#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control.
#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control.
#define SYSCTL_SCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control.
#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control.
#define SYSCTL_SCGC1_UART2 0x00000004 // UART2 Clock Gating Control.
#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control.
#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_SCGC2 register.
//
//*****************************************************************************
#define SYSCTL_SCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control.
#define SYSCTL_SCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control.
#define SYSCTL_SCGC2_USB0 0x00010000 // USB0 Clock Gating Control.
#define SYSCTL_SCGC2_UDMA 0x00002000 // UDMA Clock Gating Control.
#define SYSCTL_SCGC2_GPIOH 0x00000080 // Port H Clock Gating Control.
#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control.
#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control.
#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control.
#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control.
#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control.
#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control.
#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_DCGC0 register.
//
//*****************************************************************************
#define SYSCTL_DCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control.
#define SYSCTL_DCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control.
#define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control.
#define SYSCTL_DCGC0_PWM 0x00100000 // PWM Clock Gating Control.
#define SYSCTL_DCGC0_ADC 0x00010000 // ADC0 Clock Gating Control.
#define SYSCTL_DCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed.
#define SYSCTL_DCGC0_ADCSPD125K 0x00000000 // 125K samples/second
#define SYSCTL_DCGC0_ADCSPD250K 0x00000100 // 250K samples/second
#define SYSCTL_DCGC0_ADCSPD500K 0x00000200 // 500K samples/second
#define SYSCTL_DCGC0_ADCSPD1M 0x00000300 // 1M samples/second
#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control.
#define SYSCTL_DCGC0_WDT 0x00000008 // WDT Clock Gating Control.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_DCGC1 register.
//
//*****************************************************************************
#define SYSCTL_DCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock
// Gating.
#define SYSCTL_DCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock
// Gating.
#define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock
// Gating.
#define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control.
#define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control.
#define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control.
#define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control.
#define SYSCTL_DCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control.
#define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control.
#define SYSCTL_DCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control.
#define SYSCTL_DCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control.
#define SYSCTL_DCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control.
#define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control.
#define SYSCTL_DCGC1_UART2 0x00000004 // UART2 Clock Gating Control.
#define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control.
#define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_DCGC2 register.
//
//*****************************************************************************
#define SYSCTL_DCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control.
#define SYSCTL_DCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control.
#define SYSCTL_DCGC2_USB0 0x00010000 // USB0 Clock Gating Control.
#define SYSCTL_DCGC2_UDMA 0x00002000 // UDMA Clock Gating Control.
#define SYSCTL_DCGC2_GPIOH 0x00000080 // Port H Clock Gating Control.
#define SYSCTL_DCGC2_GPIOG 0x00000040 // Port G Clock Gating Control.
#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control.
#define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control.
#define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control.
#define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control.
#define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control.
#define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_DC5 register.
//
//*****************************************************************************
#define SYSCTL_DC5_PWMFAULT3 0x08000000 // PWM Fault 3 Pin Present.
#define SYSCTL_DC5_PWMFAULT2 0x04000000 // PWM Fault 2 Pin Present.
#define SYSCTL_DC5_PWMFAULT1 0x02000000 // PWM Fault 1 Pin Present.
#define SYSCTL_DC5_PWMFAULT0 0x01000000 // PWM Fault 0 Pin Present.
#define SYSCTL_DC5_PWMEFLT 0x00200000 // PWM Extended Fault feature is
// active.
#define SYSCTL_DC5_PWMESYNC 0x00100000 // PWM Extended SYNC feature is
// active.
#define SYSCTL_DC5_PWM7 0x00000080 // PWM7 Pin Present.
#define SYSCTL_DC5_PWM6 0x00000040 // PWM6 Pin Present.
#define SYSCTL_DC5_PWM5 0x00000020 // PWM5 Pin Present.
#define SYSCTL_DC5_PWM4 0x00000010 // PWM4 Pin Present.
#define SYSCTL_DC5_PWM3 0x00000008 // PWM3 Pin Present.
#define SYSCTL_DC5_PWM2 0x00000004 // PWM2 Pin Present.
#define SYSCTL_DC5_PWM1 0x00000002 // PWM1 Pin Present.
#define SYSCTL_DC5_PWM0 0x00000001 // PWM0 Pin Present.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_DC6 register.
//
//*****************************************************************************
#define SYSCTL_DC6_USB0_M 0x00000003 // This specifies that USB0 is
// present and its capability.
#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002 // USB is DEVICE or HOST
#define SYSCTL_DC6_USB0_OTG 0x00000003 // USB is OTG
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_GPIOHSCTL
// register.
//
//*****************************************************************************
#define SYSCTL_GPIOHSCTL_PORTH 0x00000080 // Port H High-Speed.
#define SYSCTL_GPIOHSCTL_PORTG 0x00000040 // Port G High-Speed.
#define SYSCTL_GPIOHSCTL_PORTF 0x00000020 // Port F High-Speed.
#define SYSCTL_GPIOHSCTL_PORTE 0x00000010 // Port E High-Speed.
#define SYSCTL_GPIOHSCTL_PORTD 0x00000008 // Port D High-Speed.
#define SYSCTL_GPIOHSCTL_PORTC 0x00000004 // Port C High-Speed.
#define SYSCTL_GPIOHSCTL_PORTB 0x00000002 // Port B High-Speed.
#define SYSCTL_GPIOHSCTL_PORTA 0x00000001 // Port A High-Speed.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_MOSCCTL register.
//
//*****************************************************************************
#define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_DC7 register.
//
//*****************************************************************************
#define SYSCTL_DC7_SSI1_TX 0x02000000 // SSI1 TX on uDMA Ch25.
#define SYSCTL_DC7_SSI1_RX 0x01000000 // SSI1 RX on uDMA Ch24.
#define SYSCTL_DC7_UART1_TX 0x00800000 // UART1 TX on uDMA Ch23.
#define SYSCTL_DC7_UART1_RX 0x00400000 // UART1 RX on uDMA Ch22.
#define SYSCTL_DC7_SSI0_TX 0x00000800 // SSI0 TX on uDMA Ch11.
#define SYSCTL_DC7_SSI0_RX 0x00000400 // SSI0 RX on uDMA Ch10.
#define SYSCTL_DC7_UART0_TX 0x00000200 // UART0 TX on uDMA Ch9.
#define SYSCTL_DC7_UART0_RX 0x00000100 // UART0 RX on uDMA Ch8.
#define SYSCTL_DC7_USB_EP3_TX 0x00000020 // USB EP3 TX on uDMA Ch5.
#define SYSCTL_DC7_USB_EP3_RX 0x00000010 // USB EP3 RX on uDMA Ch4.
#define SYSCTL_DC7_USB_EP2_TX 0x00000008 // USB EP2 TX on uDMA Ch3.
#define SYSCTL_DC7_USB_EP2_RX 0x00000004 // USB EP2 RX on uDMA Ch2.
#define SYSCTL_DC7_USB_EP1_TX 0x00000002 // USB EP1 TX on uDMA Ch1.
#define SYSCTL_DC7_USB_EP1_RX 0x00000001 // USB EP1 RX on uDMA Ch0.
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the system control register
// addresses.
//
//*****************************************************************************
#define SYSCTL_USER0 0x400FE1E0 // NV User Register 0
#define SYSCTL_USER1 0x400FE1E4 // NV User Register 1
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the SYSCTL_DID0
// register.
//
//*****************************************************************************
#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask
#define SYSCTL_DID0_CLASS_MASK 0x00FF0000 // Device Class
#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask
#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A
#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B
#define SYSCTL_DID0_MAJ_C 0x00000200 // Major revision C
#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the SYSCTL_DID1
// register.
//
//*****************************************************************************
#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask
#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask
#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family
#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask
#define SYSCTL_DID1_PINCNT_MASK 0x0000E000 // Pin count
#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask
#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask
#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask
#define SYSCTL_DID1_PRTNO_SHIFT 16
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the SYSCTL_DC0
// register.
//
//*****************************************************************************
#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask
#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the SYSCTL_DC1
// register.
//
//*****************************************************************************
#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask
#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask
#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the SYSCTL_DC2
// register.
//
//*****************************************************************************
#define SYSCTL_DC2_I2C 0x00001000 // I2C present
#define SYSCTL_DC2_QEI 0x00000100 // QEI present
#define SYSCTL_DC2_SSI 0x00000010 // SSI present
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the SYSCTL_DC3
// register.
//
//*****************************************************************************
#define SYSCTL_DC3_MC_FAULT0 0x00008000 // MC0 fault pin present
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the
// SYSCTL_PBORCTL register.
//
//*****************************************************************************
#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer
#define SYSCTL_PBORCTL_BOR_SH 2
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the
// SYSCTL_LDOPCTL register.
//
//*****************************************************************************
#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the SYSCTL_SRCR0,
// SYSCTL_RCGC0, SYSCTL_SCGC0, and SYSCTL_DCGC0 registers.
//
//*****************************************************************************
#define SYSCTL_SET0_CAN2 0x04000000 // CAN 2 module
#define SYSCTL_SET0_CAN1 0x02000000 // CAN 1 module
#define SYSCTL_SET0_CAN0 0x01000000 // CAN 0 module
#define SYSCTL_SET0_PWM 0x00100000 // PWM module
#define SYSCTL_SET0_ADC 0x00010000 // ADC module
#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask
#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC
#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC
#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC
#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC
#define SYSCTL_SET0_HIB 0x00000040 // Hibernation module
#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the SYSCTL_SRCR1,
// SYSCTL_RCGC1, SYSCTL_SCGC1, and SYSCTL_DCGC1 registers.
//
//*****************************************************************************
#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2
#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1
#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0
#define SYSCTL_SET1_TIMER3 0x00080000 // Timer module 3
#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2
#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1
#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0
#define SYSCTL_SET1_I2C1 0x00002000 // I2C module 1
#define SYSCTL_SET1_I2C0 0x00001000 // I2C module 0
#define SYSCTL_SET1_I2C 0x00001000 // I2C module
#define SYSCTL_SET1_QEI1 0x00000200 // QEI module 1
#define SYSCTL_SET1_QEI 0x00000100 // QEI module
#define SYSCTL_SET1_QEI0 0x00000100 // QEI module 0
#define SYSCTL_SET1_SSI1 0x00000020 // SSI module 1
#define SYSCTL_SET1_SSI0 0x00000010 // SSI module 0
#define SYSCTL_SET1_SSI 0x00000010 // SSI module
#define SYSCTL_SET1_UART2 0x00000004 // UART module 2
#define SYSCTL_SET1_UART1 0x00000002 // UART module 1
#define SYSCTL_SET1_UART0 0x00000001 // UART module 0
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the SYSCTL_SRCR2,
// SYSCTL_RCGC2, SYSCTL_SCGC2, and SYSCTL_DCGC2 registers.
//
//*****************************************************************************
#define SYSCTL_SET2_ETH 0x50000000 // ETH module
#define SYSCTL_SET2_GPIOH 0x00000080 // GPIO H module
#define SYSCTL_SET2_GPIOG 0x00000040 // GPIO G module
#define SYSCTL_SET2_GPIOF 0x00000020 // GPIO F module
#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module
#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module
#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module
#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module
#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the SYSCTL_RIS,
// SYSCTL_IMC, and SYSCTL_IMS registers.
//
//*****************************************************************************
#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt
#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int
#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt
#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the SYSCTL_RESC
// register.
//
//*****************************************************************************
#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the SYSCTL_RCC
// register.
//
//*****************************************************************************
#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider
#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider
#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider
#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider
#define SYSCTL_RCC_OE 0x00001000 // PLL output enable
#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864 MHz crystal
#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4 MHz crystal
#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc
#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select
#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field
#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field
#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field
#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the SYSCTL_PLLCFG
// register.
//
//*****************************************************************************
#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider
#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier
#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider
#define SYSCTL_PLLCFG_F_SHIFT 5
#define SYSCTL_PLLCFG_R_SHIFT 0
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the SYSCTL_RCC2
// register.
//
//*****************************************************************************
#define SYSCTL_RCC2_SYSDIV2_MSK 0x1F800000 // System clock divider
#define SYSCTL_RCC2_OSCSRC2_MSK 0x00000070 // Oscillator input select
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the
// SYSCTL_DSLPCLKCFG register.
//
//*****************************************************************************
#define SYSCTL_DSLPCLKCFG_D_MSK 0x1F800000 // Deep sleep system clock override
#define SYSCTL_DSLPCLKCFG_O_MSK 0x00000070 // Deep sleep oscillator override
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the
// SYSCTL_CLKVCLR register.
//
//*****************************************************************************
#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the
// SYSCTL_LDOARST register.
//
//*****************************************************************************
#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device
#endif
#endif // __HW_SYSCTL_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/hw_sysctl.h | C | oos | 78,370 |
//*****************************************************************************
//
// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __INTERRUPT_H__
#define __INTERRUPT_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Macro to generate an interrupt priority mask based on the number of bits
// of priority supported by the hardware.
//
//*****************************************************************************
#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF)
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern tBoolean IntMasterEnable(void);
extern tBoolean IntMasterDisable(void);
extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));
extern void IntUnregister(unsigned long ulInterrupt);
extern void IntPriorityGroupingSet(unsigned long ulBits);
extern unsigned long IntPriorityGroupingGet(void);
extern void IntPrioritySet(unsigned long ulInterrupt,
unsigned char ucPriority);
extern long IntPriorityGet(unsigned long ulInterrupt);
extern void IntEnable(unsigned long ulInterrupt);
extern void IntDisable(unsigned long ulInterrupt);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __INTERRUPT_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/interrupt.h | C | oos | 3,233 |
//*****************************************************************************
//
// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_WATCHDOG_H__
#define __HW_WATCHDOG_H__
//*****************************************************************************
//
// The following are defines for the Watchdog Timer register offsets.
//
//*****************************************************************************
#define WDT_O_LOAD 0x00000000 // Load register
#define WDT_O_VALUE 0x00000004 // Current value register
#define WDT_O_CTL 0x00000008 // Control register
#define WDT_O_ICR 0x0000000C // Interrupt clear register
#define WDT_O_RIS 0x00000010 // Raw interrupt status register
#define WDT_O_MIS 0x00000014 // Masked interrupt status register
#define WDT_O_TEST 0x00000418 // Test register
#define WDT_O_LOCK 0x00000C00 // Lock register
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_CTL register.
//
//*****************************************************************************
#define WDT_CTL_RESEN 0x00000002 // Enable reset output
#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and
// WDT_MIS registers.
//
//*****************************************************************************
#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_TEST register.
//
//*****************************************************************************
#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_LOCK register.
//
//*****************************************************************************
#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock.
#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer
#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked
#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_LOAD register.
//
//*****************************************************************************
#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value.
#define WDT_LOAD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_VALUE register.
//
//*****************************************************************************
#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value.
#define WDT_VALUE_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_ICR register.
//
//*****************************************************************************
#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear.
#define WDT_ICR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_RIS register.
//
//*****************************************************************************
#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_MIS register.
//
//*****************************************************************************
#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt
// Status.
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the Watchdog Timer register
// offsets.
//
//*****************************************************************************
#define WDT_O_PeriphID4 0x00000FD0
#define WDT_O_PeriphID5 0x00000FD4
#define WDT_O_PeriphID6 0x00000FD8
#define WDT_O_PeriphID7 0x00000FDC
#define WDT_O_PeriphID0 0x00000FE0
#define WDT_O_PeriphID1 0x00000FE4
#define WDT_O_PeriphID2 0x00000FE8
#define WDT_O_PeriphID3 0x00000FEC
#define WDT_O_PCellID0 0x00000FF0
#define WDT_O_PCellID1 0x00000FF4
#define WDT_O_PCellID2 0x00000FF8
#define WDT_O_PCellID3 0x00000FFC
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the WDT_TEST
// register.
//
//*****************************************************************************
#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable
//*****************************************************************************
//
// The following are deprecated defines for the reset values for the WDT
// registers.
//
//*****************************************************************************
#define WDT_RV_VALUE 0xFFFFFFFF // Current value register
#define WDT_RV_LOAD 0xFFFFFFFF // Load register
#define WDT_RV_PCellID1 0x000000F0
#define WDT_RV_PCellID3 0x000000B1
#define WDT_RV_PeriphID1 0x00000018
#define WDT_RV_PeriphID2 0x00000018
#define WDT_RV_PCellID0 0x0000000D
#define WDT_RV_PCellID2 0x00000005
#define WDT_RV_PeriphID0 0x00000005
#define WDT_RV_PeriphID3 0x00000001
#define WDT_RV_PeriphID5 0x00000000
#define WDT_RV_RIS 0x00000000 // Raw interrupt status register
#define WDT_RV_CTL 0x00000000 // Control register
#define WDT_RV_PeriphID4 0x00000000
#define WDT_RV_PeriphID6 0x00000000
#define WDT_RV_PeriphID7 0x00000000
#define WDT_RV_LOCK 0x00000000 // Lock register
#define WDT_RV_MIS 0x00000000 // Masked interrupt status register
#endif
#endif // __HW_WATCHDOG_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/hw_watchdog.h | C | oos | 8,220 |
//*****************************************************************************
//
// hw_memmap.h - Macros defining the memory map of Stellaris.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_MEMMAP_H__
#define __HW_MEMMAP_H__
//*****************************************************************************
//
// The following are defines for the base address of the memories and
// peripherals.
//
//*****************************************************************************
#define FLASH_BASE 0x00000000 // FLASH memory
#define SRAM_BASE 0x20000000 // SRAM memory
#define WATCHDOG_BASE 0x40000000 // Watchdog
#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A
#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B
#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C
#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D
#define SSI0_BASE 0x40008000 // SSI0
#define SSI1_BASE 0x40009000 // SSI1
#define UART0_BASE 0x4000C000 // UART0
#define UART1_BASE 0x4000D000 // UART1
#define UART2_BASE 0x4000E000 // UART2
#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master
#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave
#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master
#define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave
#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E
#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F
#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G
#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H
#define PWM_BASE 0x40028000 // PWM
#define QEI0_BASE 0x4002C000 // QEI0
#define QEI1_BASE 0x4002D000 // QEI1
#define TIMER0_BASE 0x40030000 // Timer0
#define TIMER1_BASE 0x40031000 // Timer1
#define TIMER2_BASE 0x40032000 // Timer2
#define TIMER3_BASE 0x40033000 // Timer3
#define ADC_BASE 0x40038000 // ADC
#define COMP_BASE 0x4003C000 // Analog comparators
#define CAN0_BASE 0x40040000 // CAN0
#define CAN1_BASE 0x40041000 // CAN1
#define CAN2_BASE 0x40042000 // CAN2
#define ETH_BASE 0x40048000 // Ethernet
#define MAC_BASE 0x40048000 // Ethernet
#define USB0_BASE 0x40050000 // USB 0 Controller
#define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed)
#define GPIO_PORTB_AHB_BASE 0x40059000 // GPIO Port B (high speed)
#define GPIO_PORTC_AHB_BASE 0x4005A000 // GPIO Port C (high speed)
#define GPIO_PORTD_AHB_BASE 0x4005B000 // GPIO Port D (high speed)
#define GPIO_PORTE_AHB_BASE 0x4005C000 // GPIO Port E (high speed)
#define GPIO_PORTF_AHB_BASE 0x4005D000 // GPIO Port F (high speed)
#define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed)
#define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed)
#define HIB_BASE 0x400FC000 // Hibernation Module
#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller
#define SYSCTL_BASE 0x400FE000 // System Control
#define UDMA_BASE 0x400FF000 // uDMA Controller
#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell
#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace
#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint
#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl
#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the base address of the memories
// and peripherals.
//
//*****************************************************************************
#define SSI_BASE 0x40008000 // SSI
#define I2C_MASTER_BASE 0x40020000 // I2C Master
#define I2C_SLAVE_BASE 0x40020800 // I2C Slave
#define QEI_BASE 0x4002C000 // QEI
#endif
#endif // __HW_MEMMAP_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/hw_memmap.h | C | oos | 5,703 |
//*****************************************************************************
//
// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_PWM_H__
#define __HW_PWM_H__
//*****************************************************************************
//
// The following are defines for the PWM Module Register offsets.
//
//*****************************************************************************
#define PWM_O_CTL 0x00000000 // PWM Master Control register
#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register
#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register
#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register
#define PWM_O_FAULT 0x00000010 // PWM Output Fault register
#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register
#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg.
#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register
#define PWM_O_STATUS 0x00000020 // PWM Status register
#define PWM_O_FAULTVAL 0x00000024 // PWM Fault Condition Value
#define PWM_O_0_CTL 0x00000040 // PWM0 Control
#define PWM_O_0_INTEN 0x00000044 // PWM0 Interrupt and Trigger
// Enable
#define PWM_O_0_RIS 0x00000048 // PWM0 Raw Interrupt Status
#define PWM_O_0_ISC 0x0000004C // PWM0 Interrupt Status and Clear
#define PWM_O_0_LOAD 0x00000050 // PWM0 Load
#define PWM_O_0_COUNT 0x00000054 // PWM0 Counter
#define PWM_O_0_CMPA 0x00000058 // PWM0 Compare A
#define PWM_O_0_CMPB 0x0000005C // PWM0 Compare B
#define PWM_O_0_GENA 0x00000060 // PWM0 Generator A Control
#define PWM_O_0_GENB 0x00000064 // PWM0 Generator B Control
#define PWM_O_0_DBCTL 0x00000068 // PWM0 Dead-Band Control
#define PWM_O_0_DBRISE 0x0000006C // PWM0 Dead-Band Rising-Edge Delay
#define PWM_O_0_DBFALL 0x00000070 // PWM0 Dead-Band
// Falling-Edge-Delay
#define PWM_O_0_FLTSRC0 0x00000074 // PWM0 Fault Source 0
#define PWM_O_0_MINFLTPER 0x0000007C // PWM0 Minimum Fault Period
#define PWM_O_1_CTL 0x00000080 // PWM1 Control
#define PWM_O_1_INTEN 0x00000084 // PWM1 Interrupt Enable
#define PWM_O_1_RIS 0x00000088 // PWM1 Raw Interrupt Status
#define PWM_O_1_ISC 0x0000008C // PWM1 Interrupt Status and Clear
#define PWM_O_1_LOAD 0x00000090 // PWM1 Load
#define PWM_O_1_COUNT 0x00000094 // PWM1 Counter
#define PWM_O_1_CMPA 0x00000098 // PWM1 Compare A
#define PWM_O_1_CMPB 0x0000009C // PWM1 Compare B
#define PWM_O_1_GENA 0x000000A0 // PWM1 Generator A Control
#define PWM_O_1_GENB 0x000000A4 // PWM1 Generator B Control
#define PWM_O_1_DBCTL 0x000000A8 // PWM1 Dead-Band Control
#define PWM_O_1_DBRISE 0x000000AC // PWM1 Dead-Band Rising-Edge Delay
#define PWM_O_1_DBFALL 0x000000B0 // PWM1 Dead-Band
// Falling-Edge-Delay
#define PWM_O_1_FLTSRC0 0x000000B4 // PWM1 Fault Source 0
#define PWM_O_1_MINFLTPER 0x000000BC // PWM1 Minimum Fault Period
#define PWM_O_2_CTL 0x000000C0 // PWM2 Control
#define PWM_O_2_INTEN 0x000000C4 // PWM2 InterruptEnable
#define PWM_O_2_RIS 0x000000C8 // PWM2 Raw Interrupt Status
#define PWM_O_2_ISC 0x000000CC // PWM2 Interrupt Status and Clear
#define PWM_O_2_LOAD 0x000000D0 // PWM2 Load
#define PWM_O_2_COUNT 0x000000D4 // PWM2 Counter
#define PWM_O_2_CMPA 0x000000D8 // PWM2 Compare A
#define PWM_O_2_CMPB 0x000000DC // PWM2 Compare B
#define PWM_O_2_GENA 0x000000E0 // PWM2 Generator A Control
#define PWM_O_2_GENB 0x000000E4 // PWM2 Generator B Control
#define PWM_O_2_DBCTL 0x000000E8 // PWM2 Dead-Band Control
#define PWM_O_2_DBRISE 0x000000EC // PWM2 Dead-Band Rising-Edge Delay
#define PWM_O_2_DBFALL 0x000000F0 // PWM2 Dead-Band
// Falling-Edge-Delay
#define PWM_O_2_FLTSRC0 0x000000F4 // PWM2 Fault Source 0
#define PWM_O_2_MINFLTPER 0x000000FC // PWM2 Minimum Fault Period
#define PWM_O_3_CTL 0x00000100 // PWM3 Control
#define PWM_O_3_INTEN 0x00000104 // PWM3 Interrupt and Trigger
// Enable
#define PWM_O_3_RIS 0x00000108 // PWM3 Raw Interrupt Status
#define PWM_O_3_ISC 0x0000010C // PWM3 Interrupt Status and Clear
#define PWM_O_3_LOAD 0x00000110 // PWM3 Load
#define PWM_O_3_COUNT 0x00000114 // PWM3 Counter
#define PWM_O_3_CMPA 0x00000118 // PWM3 Compare A
#define PWM_O_3_CMPB 0x0000011C // PWM3 Compare B
#define PWM_O_3_GENA 0x00000120 // PWM3 Generator A Control
#define PWM_O_3_GENB 0x00000124 // PWM3 Generator B Control
#define PWM_O_3_DBCTL 0x00000128 // PWM3 Dead-Band Control
#define PWM_O_3_DBRISE 0x0000012C // PWM3 Dead-Band Rising-Edge Delay
#define PWM_O_3_DBFALL 0x00000130 // PWM3 Dead-Band
// Falling-Edge-Delay
#define PWM_O_3_FLTSRC0 0x00000134 // PWM3 Fault Source 0
#define PWM_O_3_MINFLTPER 0x0000013C // PWM3 Minimum Fault Period
#define PWM_O_0_FLTSEN 0x00000800 // PWM0 Fault Pin Logic Sense
#define PWM_O_0_FLTSTAT0 0x00000804 // PWM0 Fault Status 0
#define PWM_O_1_FLTSEN 0x00000880 // PWM1 Fault Pin Logic Sense
#define PWM_O_1_FLTSTAT0 0x00000884 // PWM1 Fault Status 0
#define PWM_O_2_FLTSEN 0x00000900 // PWM2 Fault Pin Logic Sense
#define PWM_O_2_FLTSTAT0 0x00000904 // PWM2 Fault Status 0
#define PWM_O_3_FLTSEN 0x00000980 // PWM3 Fault Pin Logic Sense
#define PWM_O_3_FLTSTAT0 0x00000984 // PWM3 Fault Status 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM Master Control
// register.
//
//*****************************************************************************
#define PWM_CTL_GLOBALSYNC3 0x00000008 // Update PWM Generator 3.
#define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2.
#define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1.
#define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0.
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM Time Base Sync
// register.
//
//*****************************************************************************
#define PWM_SYNC_SYNC3 0x00000008 // Reset generator 3 counter
#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter
#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter
#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM Output Enable
// register.
//
//*****************************************************************************
#define PWM_ENABLE_PWM7EN 0x00000080 // PWM7 pin enable
#define PWM_ENABLE_PWM6EN 0x00000040 // PWM6 pin enable
#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable
#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable
#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable
#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable
#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable
#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM Inversion register.
//
//*****************************************************************************
#define PWM_INVERT_PWM7INV 0x00000080 // PWM7 pin invert
#define PWM_INVERT_PWM6INV 0x00000040 // PWM6 pin invert
#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert
#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert
#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert
#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert
#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert
#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM Fault register.
//
//*****************************************************************************
#define PWM_FAULT_FAULT7 0x00000080 // PWM7 pin fault
#define PWM_FAULT_FAULT6 0x00000040 // PWM6 pin fault
#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault
#define PWM_FAULT_FAULT4 0x00000010 // PWM4 pin fault
#define PWM_FAULT_FAULT3 0x00000008 // PWM3 pin fault
#define PWM_FAULT_FAULT2 0x00000004 // PWM2 pin fault
#define PWM_FAULT_FAULT1 0x00000002 // PWM1 pin fault
#define PWM_FAULT_FAULT0 0x00000001 // PWM0 pin fault
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM Status register.
//
//*****************************************************************************
#define PWM_STATUS_FAULT3 0x00000008 // Fault3 Interrupt Status.
#define PWM_STATUS_FAULT2 0x00000004 // Fault2 Interrupt Status.
#define PWM_STATUS_FAULT1 0x00000002 // Fault1 Interrupt Status.
#define PWM_STATUS_FAULT0 0x00000001 // Fault0 Interrupt Status.
//*****************************************************************************
//
// The following are defines for the PWM Generator standard offsets.
//
//*****************************************************************************
#define PWM_O_X_CTL 0x00000000 // Gen Control Reg
#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg
#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg
#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg
#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg
#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg
#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg
#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg
#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg
#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg
#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg
#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg
#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg
#define PWM_O_X_FLTSRC0 0x00000034 // Fault pin, comparator condition
#define PWM_O_X_MINFLTPER 0x0000003C // Fault minimum period extension
#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base
#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base
#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base
#define PWM_GEN_3_OFFSET 0x00000100 // PWM3 base
//*****************************************************************************
//
// The following are defines for the PWM_X Control Register bit definitions.
//
//*****************************************************************************
#define PWM_X_CTL_LATCH 0x00040000 // Latch Fault Input.
#define PWM_X_CTL_MINFLTPER 0x00020000 // Minimum fault period enabled
#define PWM_X_CTL_FLTSRC 0x00010000 // Fault Condition Source.
#define PWM_X_CTL_DBFALLUPD_M 0x0000C000 // Specifies the update mode for
// the PWMnDBFALL register.
#define PWM_X_CTL_DBFALLUPD_I 0x00000000 // Immediate
#define PWM_X_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
#define PWM_X_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
#define PWM_X_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode.
#define PWM_X_CTL_DBRISEUPD_I 0x00000000 // Immediate
#define PWM_X_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
#define PWM_X_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
#define PWM_X_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode.
#define PWM_X_CTL_DBCTLUPD_I 0x00000000 // Immediate
#define PWM_X_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
#define PWM_X_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
#define PWM_X_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode.
#define PWM_X_CTL_GENBUPD_I 0x00000000 // Immediate
#define PWM_X_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
#define PWM_X_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
#define PWM_X_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode.
#define PWM_X_CTL_GENAUPD_I 0x00000000 // Immediate
#define PWM_X_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
#define PWM_X_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg
#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg
#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg
#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode
#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down
#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block
//*****************************************************************************
//
// The following are defines for the PWM Generator extended offsets.
//
//*****************************************************************************
#define PWM_O_X_FLTSEN 0x00000000 // Fault logic sense
#define PWM_O_X_FLTSTAT0 0x00000004 // Pin and comparator status
#define PWM_EXT_0_OFFSET 0x00000800 // PWM0 extended base
#define PWM_EXT_1_OFFSET 0x00000880 // PWM1 extended base
#define PWM_EXT_2_OFFSET 0x00000900 // PWM2 extended base
#define PWM_EXT_3_OFFSET 0x00000980 // PWM3 extended base
//*****************************************************************************
//
// The following are defines for the PWM_X Interrupt/Trigger Enable Register
// bit definitions.
//
//*****************************************************************************
#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D
#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U
#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D
#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U
#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD
#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0
#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D
#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U
#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D
#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U
#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD
#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0
//*****************************************************************************
//
// The following are defines for the PWM_X Raw Interrupt Status Register bit
// definitions.
//
//*****************************************************************************
#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int
#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int
#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int
#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int
#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int
#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_INTEN register.
//
//*****************************************************************************
#define PWM_INTEN_INTFAULT3 0x00080000 // Interrupt Fault 3.
#define PWM_INTEN_INTFAULT2 0x00040000 // Interrupt Fault 2.
#define PWM_INTEN_INTFAULT1 0x00020000 // Interrupt Fault 1.
#define PWM_INTEN_INTFAULT 0x00010000 // Fault Interrupt Enable.
#define PWM_INTEN_INTFAULT0 0x00010000 // Interrupt Fault 0.
#define PWM_INTEN_INTPWM3 0x00000008 // PWM3 Interrupt Enable.
#define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable.
#define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable.
#define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable.
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_RIS register.
//
//*****************************************************************************
#define PWM_RIS_INTFAULT3 0x00080000 // Interrupt Fault PWM 3.
#define PWM_RIS_INTFAULT2 0x00040000 // Interrupt Fault PWM 2.
#define PWM_RIS_INTFAULT1 0x00020000 // Interrupt Fault PWM 1.
#define PWM_RIS_INTFAULT0 0x00010000 // Interrupt Fault PWM 0.
#define PWM_RIS_INTFAULT 0x00010000 // Fault Interrupt Asserted.
#define PWM_RIS_INTPWM3 0x00000008 // PWM3 Interrupt Asserted.
#define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted.
#define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted.
#define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted.
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_ISC register.
//
//*****************************************************************************
#define PWM_ISC_INTFAULT3 0x00080000 // FAULT3 Interrupt Asserted.
#define PWM_ISC_INTFAULT2 0x00040000 // FAULT2 Interrupt Asserted.
#define PWM_ISC_INTFAULT1 0x00020000 // FAULT1 Interrupt Asserted.
#define PWM_ISC_INTFAULT 0x00010000 // Fault Interrupt Asserted.
#define PWM_ISC_INTFAULT0 0x00010000 // FAULT0 Interrupt Asserted.
#define PWM_ISC_INTPWM3 0x00000008 // PWM3 Interrupt Status.
#define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status.
#define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status.
#define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_ISC register.
//
//*****************************************************************************
#define PWM_X_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt.
#define PWM_X_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt.
#define PWM_X_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt.
#define PWM_X_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt.
#define PWM_X_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt.
#define PWM_X_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt.
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_LOAD register.
//
//*****************************************************************************
#define PWM_X_LOAD_M 0x0000FFFF // Counter Load Value.
#define PWM_X_LOAD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_COUNT register.
//
//*****************************************************************************
#define PWM_X_COUNT_M 0x0000FFFF // Counter Value.
#define PWM_X_COUNT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_CMPA register.
//
//*****************************************************************************
#define PWM_X_CMPA_M 0x0000FFFF // Comparator A Value.
#define PWM_X_CMPA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_CMPB register.
//
//*****************************************************************************
#define PWM_X_CMPB_M 0x0000FFFF // Comparator B Value.
#define PWM_X_CMPB_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_GENA register.
//
//*****************************************************************************
#define PWM_X_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down.
#define PWM_X_GENA_ACTCMPBD_NONE \
0x00000000 // Do nothing.
#define PWM_X_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal.
#define PWM_X_GENA_ACTCMPBD_ZERO \
0x00000800 // Set the output signal to 0.
#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1.
#define PWM_X_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up.
#define PWM_X_GENA_ACTCMPBU_NONE \
0x00000000 // Do nothing.
#define PWM_X_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal.
#define PWM_X_GENA_ACTCMPBU_ZERO \
0x00000200 // Set the output signal to 0.
#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1.
#define PWM_X_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down.
#define PWM_X_GENA_ACTCMPAD_NONE \
0x00000000 // Do nothing.
#define PWM_X_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal.
#define PWM_X_GENA_ACTCMPAD_ZERO \
0x00000080 // Set the output signal to 0.
#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1.
#define PWM_X_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up.
#define PWM_X_GENA_ACTCMPAU_NONE \
0x00000000 // Do nothing.
#define PWM_X_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal.
#define PWM_X_GENA_ACTCMPAU_ZERO \
0x00000020 // Set the output signal to 0.
#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1.
#define PWM_X_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load.
#define PWM_X_GENA_ACTLOAD_NONE 0x00000000 // Do nothing.
#define PWM_X_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal.
#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0.
#define PWM_X_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1.
#define PWM_X_GENA_ACTZERO_M 0x00000003 // Action for Counter=0.
#define PWM_X_GENA_ACTZERO_NONE 0x00000000 // Do nothing.
#define PWM_X_GENA_ACTZERO_INV 0x00000001 // Invert the output signal.
#define PWM_X_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0.
#define PWM_X_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1.
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_GENB register.
//
//*****************************************************************************
#define PWM_X_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down.
#define PWM_X_GENB_ACTCMPBD_NONE \
0x00000000 // Do nothing.
#define PWM_X_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal.
#define PWM_X_GENB_ACTCMPBD_ZERO \
0x00000800 // Set the output signal to 0.
#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1.
#define PWM_X_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up.
#define PWM_X_GENB_ACTCMPBU_NONE \
0x00000000 // Do nothing.
#define PWM_X_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal.
#define PWM_X_GENB_ACTCMPBU_ZERO \
0x00000200 // Set the output signal to 0.
#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1.
#define PWM_X_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down.
#define PWM_X_GENB_ACTCMPAD_NONE \
0x00000000 // Do nothing.
#define PWM_X_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal.
#define PWM_X_GENB_ACTCMPAD_ZERO \
0x00000080 // Set the output signal to 0.
#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1.
#define PWM_X_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up.
#define PWM_X_GENB_ACTCMPAU_NONE \
0x00000000 // Do nothing.
#define PWM_X_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal.
#define PWM_X_GENB_ACTCMPAU_ZERO \
0x00000020 // Set the output signal to 0.
#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1.
#define PWM_X_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load.
#define PWM_X_GENB_ACTLOAD_NONE 0x00000000 // Do nothing.
#define PWM_X_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal.
#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0.
#define PWM_X_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1.
#define PWM_X_GENB_ACTZERO_M 0x00000003 // Action for Counter=0.
#define PWM_X_GENB_ACTZERO_NONE 0x00000000 // Do nothing.
#define PWM_X_GENB_ACTZERO_INV 0x00000001 // Invert the output signal.
#define PWM_X_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0.
#define PWM_X_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1.
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_DBCTL register.
//
//*****************************************************************************
#define PWM_X_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable.
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_DBRISE register.
//
//*****************************************************************************
#define PWM_X_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay.
#define PWM_X_DBRISE_DELAY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_DBFALL register.
//
//*****************************************************************************
#define PWM_X_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay.
#define PWM_X_DBFALL_DELAY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_FAULTVAL register.
//
//*****************************************************************************
#define PWM_FAULTVAL_PWM7 0x00000080 // PWM7 Fault Value.
#define PWM_FAULTVAL_PWM6 0x00000040 // PWM6 Fault Value.
#define PWM_FAULTVAL_PWM5 0x00000020 // PWM5 Fault Value.
#define PWM_FAULTVAL_PWM4 0x00000010 // PWM4 Fault Value.
#define PWM_FAULTVAL_PWM3 0x00000008 // PWM3 Fault Value.
#define PWM_FAULTVAL_PWM2 0x00000004 // PWM2 Fault Value.
#define PWM_FAULTVAL_PWM1 0x00000002 // PWM1 Fault Value.
#define PWM_FAULTVAL_PWM0 0x00000001 // PWM0 Fault Value.
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_MINFLTPER
// register.
//
//*****************************************************************************
#define PWM_X_MINFLTPER_M 0x0000FFFF // Minimum Fault Period.
#define PWM_X_MINFLTPER_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_FLTSEN register.
//
//*****************************************************************************
#define PWM_X_FLTSEN_FAULT3 0x00000008 // Fault3 Sense.
#define PWM_X_FLTSEN_FAULT2 0x00000004 // Fault2 Sense.
#define PWM_X_FLTSEN_FAULT1 0x00000002 // Fault1 Sense.
#define PWM_X_FLTSEN_FAULT0 0x00000001 // Fault0 Sense.
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_FLTSRC0
// register.
//
//*****************************************************************************
#define PWM_X_FLTSRC0_FAULT3 0x00000008 // Fault3.
#define PWM_X_FLTSRC0_FAULT2 0x00000004 // Fault2.
#define PWM_X_FLTSRC0_FAULT1 0x00000002 // Fault1.
#define PWM_X_FLTSRC0_FAULT0 0x00000001 // Fault0.
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_FLTSTAT0
// register.
//
//*****************************************************************************
#define PWM_X_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3.
#define PWM_X_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2.
#define PWM_X_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1.
#define PWM_X_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0.
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the PWM Master
// Control register.
//
//*****************************************************************************
#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2
#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1
#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0
//*****************************************************************************
//
// The following are deprecated defines for the PWM Interrupt Register bit
// definitions.
//
//*****************************************************************************
#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the PWM Status
// register.
//
//*****************************************************************************
#define PWM_STATUS_FAULT 0x00000001 // Fault status
//*****************************************************************************
//
// The following are deprecated defines for the PWM_X Interrupt Status Register
// bit definitions.
//
//*****************************************************************************
#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd
#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd
#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd
#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd
#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd
#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received
//*****************************************************************************
//
// The following are deprecated defines for the PWM_X Generator A/B Control
// Register bit definitions.
//
//*****************************************************************************
#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D
#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U
#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D
#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U
#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD
#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0
//*****************************************************************************
//
// The following are deprecated defines for the PWM_X Generator A/B Control
// Register action definitions.
//
//*****************************************************************************
#define PWM_GEN_ACT_ONE 0x00000003 // Set the output signal to one
#define PWM_GEN_ACT_ZERO 0x00000002 // Set the output signal to zero
#define PWM_GEN_ACT_INV 0x00000001 // Invert the output signal
#define PWM_GEN_ACT_NONE 0x00000000 // Do nothing
#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action
#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action
#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action
#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action
#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action
#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action
//*****************************************************************************
//
// The following are deprecated defines for the PWM_X Dead Band Control
// Register bit definitions.
//
//*****************************************************************************
#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion
//*****************************************************************************
//
// The following are deprecated defines for the PWM Register reset values.
//
//*****************************************************************************
#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator
#define PWM_RV_STATUS 0x00000000 // Status
#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing
#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status
#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM
// generator block
#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators
#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay
// count
#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable
#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter
#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A
#define PWM_RV_CTL 0x00000000 // Master control of the PWM module
#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM
// output pins
#define PWM_RV_RIS 0x00000000 // Raw interrupt status
#define PWM_RV_X_CMPA 0x00000000 // The comparator A value
#define PWM_RV_INVERT 0x00000000 // Inversion control for PWM output
// pins
#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay
// count
#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM output
// pins
#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B
#define PWM_RV_X_CMPB 0x00000000 // The comparator B value
#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing
#define PWM_RV_INTEN 0x00000000 // Interrupt enable
#define PWM_RV_X_COUNT 0x00000000 // The current counter value
#endif
#endif // __HW_PWM_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/hw_pwm.h | C | oos | 38,243 |
//*****************************************************************************
//
// hw_qei.h - Macros used when accessing the QEI hardware.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_QEI_H__
#define __HW_QEI_H__
//*****************************************************************************
//
// The following are defines for the QEI register offsets.
//
//*****************************************************************************
#define QEI_O_CTL 0x00000000 // Configuration and control reg.
#define QEI_O_STAT 0x00000004 // Status register
#define QEI_O_POS 0x00000008 // Current position register
#define QEI_O_MAXPOS 0x0000000C // Maximum position register
#define QEI_O_LOAD 0x00000010 // Velocity timer load register
#define QEI_O_TIME 0x00000014 // Velocity timer register
#define QEI_O_COUNT 0x00000018 // Velocity pulse count register
#define QEI_O_SPEED 0x0000001C // Velocity speed register
#define QEI_O_INTEN 0x00000020 // Interrupt enable register
#define QEI_O_RIS 0x00000024 // Raw interrupt status register
#define QEI_O_ISC 0x00000028 // Interrupt status register
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_CTL register.
//
//*****************************************************************************
#define QEI_CTL_STALLEN 0x00001000 // Stall enable
#define QEI_CTL_INVI 0x00000800 // Invert Index input
#define QEI_CTL_INVB 0x00000400 // Invert PhB input
#define QEI_CTL_INVA 0x00000200 // Invert PhA input
#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask
#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1
#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2
#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4
#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8
#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16
#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32
#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64
#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128
#define QEI_CTL_VELEN 0x00000020 // Velocity enable
#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode
#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode
#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode
#define QEI_CTL_SWAP 0x00000002 // Swap input signals
#define QEI_CTL_ENABLE 0x00000001 // QEI enable
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_STAT register.
//
//*****************************************************************************
#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation
#define QEI_STAT_ERROR 0x00000001 // Signalling error detected
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_POS register.
//
//*****************************************************************************
#define QEI_POS_M 0xFFFFFFFF // Current encoder position
#define QEI_POS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_MAXPOS register.
//
//*****************************************************************************
#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position
#define QEI_MAXPOS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_LOAD register.
//
//*****************************************************************************
#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value
#define QEI_LOAD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_TIME register.
//
//*****************************************************************************
#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value
#define QEI_TIME_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_COUNT register.
//
//*****************************************************************************
#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count
#define QEI_COUNT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_SPEED register.
//
//*****************************************************************************
#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count
#define QEI_SPEED_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_INTEN register.
//
//*****************************************************************************
#define QEI_INTEN_ERROR 0x00000008 // Phase error detected
#define QEI_INTEN_DIR 0x00000004 // Direction change
#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired
#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_RIS register.
//
//*****************************************************************************
#define QEI_RIS_ERROR 0x00000008 // Phase error detected
#define QEI_RIS_DIR 0x00000004 // Direction change
#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired
#define QEI_RIS_INDEX 0x00000001 // Index pulse detected
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_ISC register.
//
//*****************************************************************************
#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt.
#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt.
#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired
// Interrupt.
#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt.
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the QEI_ISC
// register.
//
//*****************************************************************************
#define QEI_INT_ERROR 0x00000008 // Phase error detected
#define QEI_INT_DIR 0x00000004 // Direction change
#define QEI_INT_TIMER 0x00000002 // Velocity timer expired
#define QEI_INT_INDEX 0x00000001 // Index pulse detected
//*****************************************************************************
//
// The following are deprecated defines for the reset values for the QEI
// registers.
//
//*****************************************************************************
#define QEI_RV_POS 0x00000000 // Current position register
#define QEI_RV_LOAD 0x00000000 // Velocity timer load register
#define QEI_RV_CTL 0x00000000 // Configuration and control reg.
#define QEI_RV_RIS 0x00000000 // Raw interrupt status register
#define QEI_RV_ISC 0x00000000 // Interrupt status register
#define QEI_RV_SPEED 0x00000000 // Velocity speed register
#define QEI_RV_INTEN 0x00000000 // Interrupt enable register
#define QEI_RV_STAT 0x00000000 // Status register
#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register
#define QEI_RV_MAXPOS 0x00000000 // Maximum position register
#define QEI_RV_TIME 0x00000000 // Velocity timer register
#endif
#endif // __HW_QEI_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/hw_qei.h | C | oos | 10,029 |
//*****************************************************************************
//
// hw_timer.h - Defines and macros used when accessing the timer.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_TIMER_H__
#define __HW_TIMER_H__
//*****************************************************************************
//
// The following are defines for the timer register offsets.
//
//*****************************************************************************
#define TIMER_O_CFG 0x00000000 // Configuration register
#define TIMER_O_TAMR 0x00000004 // TimerA mode register
#define TIMER_O_TBMR 0x00000008 // TimerB mode register
#define TIMER_O_CTL 0x0000000C // Control register
#define TIMER_O_IMR 0x00000018 // Interrupt mask register
#define TIMER_O_RIS 0x0000001C // Interrupt status register
#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg.
#define TIMER_O_ICR 0x00000024 // Interrupt clear register
#define TIMER_O_TAILR 0x00000028 // TimerA interval load register
#define TIMER_O_TBILR 0x0000002C // TimerB interval load register
#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register
#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register
#define TIMER_O_TAPR 0x00000038 // TimerA prescale register
#define TIMER_O_TBPR 0x0000003C // TimerB prescale register
#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register
#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register
#define TIMER_O_TAR 0x00000048 // TimerA register
#define TIMER_O_TBR 0x0000004C // TimerB register
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_CFG register.
//
//*****************************************************************************
#define TIMER_CFG_M 0x00000007 // GPTM Configuration.
#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers
#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC
#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_CTL register.
//
//*****************************************************************************
#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert
#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable
#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge
#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge
#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges
#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM TimerB Event Mode.
#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable
#define TIMER_CTL_TBEN 0x00000100 // TimerB enable
#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert
#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable
#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable
#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM TimerA Event Mode.
#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge
#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge
#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges
#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable
#define TIMER_CTL_TAEN 0x00000001 // TimerA enable
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_IMR register.
//
//*****************************************************************************
#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask
#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask
#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask
#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask
#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask
#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask
#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_RIS register.
//
//*****************************************************************************
#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status
#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status
#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status
#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status
#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status
#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status
#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_ICR register.
//
//*****************************************************************************
#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear
#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear
#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear
#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear
#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear
#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear
#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_TAILR register.
//
//*****************************************************************************
#define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM TimerA Interval Load
// Register High.
#define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM TimerA Interval Load
// Register Low.
#define TIMER_TAILR_TAILRH_S 16
#define TIMER_TAILR_TAILRL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_TBILR register.
//
//*****************************************************************************
#define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM TimerB Interval Load
// Register.
#define TIMER_TBILR_TBILRL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_TAMATCHR register.
//
//*****************************************************************************
#define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM TimerA Match Register High.
#define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM TimerA Match Register Low.
#define TIMER_TAMATCHR_TAMRH_S 16
#define TIMER_TAMATCHR_TAMRL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_TBMATCHR register.
//
//*****************************************************************************
#define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM TimerB Match Register Low.
#define TIMER_TBMATCHR_TBMRL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_TAR register.
//
//*****************************************************************************
#define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM TimerA Register High.
#define TIMER_TAR_TARL_M 0x0000FFFF // GPTM TimerA Register Low.
#define TIMER_TAR_TARH_S 16
#define TIMER_TAR_TARL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_TBR register.
//
//*****************************************************************************
#define TIMER_TBR_TBRL_M 0x0000FFFF // GPTM TimerB.
#define TIMER_TBR_TBRL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAMR register.
//
//*****************************************************************************
#define TIMER_TAMR_TAAMS 0x00000008 // GPTM TimerA Alternate Mode
// Select.
#define TIMER_TAMR_TACMR 0x00000004 // GPTM TimerA Capture Mode.
#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM TimerA Mode.
#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode.
#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode.
#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode.
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBMR register.
//
//*****************************************************************************
#define TIMER_TBMR_TBAMS 0x00000008 // GPTM TimerB Alternate Mode
// Select.
#define TIMER_TBMR_TBCMR 0x00000004 // GPTM TimerB Capture Mode.
#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM TimerB Mode.
#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode.
#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode.
#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode.
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_MIS register.
//
//*****************************************************************************
#define TIMER_MIS_CBEMIS 0x00000400 // GPTM CaptureB Event Masked
// Interrupt.
#define TIMER_MIS_CBMMIS 0x00000200 // GPTM CaptureB Match Masked
// Interrupt.
#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM TimerB Time-Out Masked
// Interrupt.
#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt.
#define TIMER_MIS_CAEMIS 0x00000004 // GPTM CaptureA Event Masked
// Interrupt.
#define TIMER_MIS_CAMMIS 0x00000002 // GPTM CaptureA Match Masked
// Interrupt.
#define TIMER_MIS_TATOMIS 0x00000001 // GPTM TimerA Time-Out Masked
// Interrupt.
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAPR register.
//
//*****************************************************************************
#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM TimerA Prescale.
#define TIMER_TAPR_TAPSR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBPR register.
//
//*****************************************************************************
#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM TimerB Prescale.
#define TIMER_TBPR_TBPSR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAPMR register.
//
//*****************************************************************************
#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match.
#define TIMER_TAPMR_TAPSMR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBPMR register.
//
//*****************************************************************************
#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match.
#define TIMER_TBPMR_TBPSMR_S 0
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the reset values of the timer
// registers.
//
//*****************************************************************************
#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV
#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV
#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV
#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV
#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV
#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV
#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV
#define TIMER_RV_CFG 0x00000000 // Configuration register RV
#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV
#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV
#define TIMER_RV_CTL 0x00000000 // Control register RV
#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV
#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV
#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV
#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV
#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV
#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV
#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_CFG
// register.
//
//*****************************************************************************
#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_TnMR
// register.
//
//*****************************************************************************
#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select
#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time
#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask
#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot
#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic
#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_CTL
// register.
//
//*****************************************************************************
#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask
#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_MIS
// register.
//
//*****************************************************************************
#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status
#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status
#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat
#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status
#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status
#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status
#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_TAILR
// register.
//
//*****************************************************************************
#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode
#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_TBILR
// register.
//
//*****************************************************************************
#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the
// TIMER_TAMATCHR register.
//
//*****************************************************************************
#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode
#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the
// TIMER_TBMATCHR register.
//
//*****************************************************************************
#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_TnPR
// register.
//
//*****************************************************************************
#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_TnPMR
// register.
//
//*****************************************************************************
#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_TAR
// register.
//
//*****************************************************************************
#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode
#define TIMER_TAR_TARL 0x0000FFFF // TimerA value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_TBR
// register.
//
//*****************************************************************************
#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value
#endif
#endif // __HW_TIMER_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/hw_timer.h | C | oos | 21,041 |
//*****************************************************************************
//
// hw_adc.h - Macros used when accessing the ADC hardware.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_ADC_H__
#define __HW_ADC_H__
//*****************************************************************************
//
// The following are defines for the ADC register offsets.
//
//*****************************************************************************
#define ADC_O_ACTSS 0x00000000 // Active sample register
#define ADC_O_RIS 0x00000004 // Raw interrupt status register
#define ADC_O_IM 0x00000008 // Interrupt mask register
#define ADC_O_ISC 0x0000000C // Interrupt status/clear register
#define ADC_O_OSTAT 0x00000010 // Overflow status register
#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg.
#define ADC_O_USTAT 0x00000018 // Underflow status register
#define ADC_O_SSPRI 0x00000020 // Channel priority register
#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg.
#define ADC_O_SAC 0x00000030 // Sample Averaging Control reg.
#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register
#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg.
#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register
#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register
#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register
#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg.
#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register
#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register
#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register
#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg.
#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register
#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register
#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register
#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg.
#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register
#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register
#define ADC_O_TMLB 0x00000100 // Test mode loopback register
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_ACTSS register.
//
//*****************************************************************************
#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable
#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable
#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable
#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_RIS register.
//
//*****************************************************************************
#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt
#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt
#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt
#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_IM register.
//
//*****************************************************************************
#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask
#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask
#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask
#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_ISC register.
//
//*****************************************************************************
#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt
#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt
#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt
#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_OSTAT register.
//
//*****************************************************************************
#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow
#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow
#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow
#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_EMUX register.
//
//*****************************************************************************
#define ADC_EMUX_EM3_M 0x0000F000 // Event mux 3 mask
#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event
#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event
#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event
#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event
#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event
#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event
#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event
#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event
#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event
#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event
#define ADC_EMUX_EM2_M 0x00000F00 // Event mux 2 mask
#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event
#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event
#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event
#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event
#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event
#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event
#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event
#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event
#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event
#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event
#define ADC_EMUX_EM1_M 0x000000F0 // Event mux 1 mask
#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event
#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event
#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event
#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event
#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event
#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event
#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event
#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event
#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event
#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event
#define ADC_EMUX_EM0_M 0x0000000F // Event mux 0 mask
#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event
#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event
#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event
#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event
#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event
#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event
#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event
#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event
#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event
#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_USTAT register.
//
//*****************************************************************************
#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow
#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow
#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow
#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_SSPRI register.
//
//*****************************************************************************
#define ADC_SSPRI_SS3_M 0x00003000 // Sequencer 3 priority mask
#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority
#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority
#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority
#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority
#define ADC_SSPRI_SS2_M 0x00000300 // Sequencer 2 priority mask
#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority
#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority
#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority
#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority
#define ADC_SSPRI_SS1_M 0x00000030 // Sequencer 1 priority mask
#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority
#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority
#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority
#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority
#define ADC_SSPRI_SS0_M 0x00000003 // Sequencer 0 priority mask
#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority
#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority
#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority
#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_PSSI register.
//
//*****************************************************************************
#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3
#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2
#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1
#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_SAC register.
//
//*****************************************************************************
#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control.
#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling
#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling
#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling
#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling
#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling
#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling
#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_TMLB register.
//
//*****************************************************************************
#define ADC_TMLB_CNT_M 0x000003C0 // Continuous Sample Counter.
#define ADC_TMLB_CONT 0x00000020 // Continuation Sample Indicator.
#define ADC_TMLB_DIFF 0x00000010 // Differential Sample Indicator.
#define ADC_TMLB_TS 0x00000008 // Temp Sensor Sample Indicator.
#define ADC_TMLB_MUX_M 0x00000007 // Analog Input Indicator.
#define ADC_TMLB_LB 0x00000001 // Loopback control signals
#define ADC_TMLB_CNT_S 6 // Sample counter shift
#define ADC_TMLB_MUX_S 0 // Input channel number shift
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSMUX0 register.
//
//*****************************************************************************
#define ADC_SSMUX0_MUX7_M 0x70000000 // 8th Sample Input Select.
#define ADC_SSMUX0_MUX6_M 0x07000000 // 7th Sample Input Select.
#define ADC_SSMUX0_MUX5_M 0x00700000 // 6th Sample Input Select.
#define ADC_SSMUX0_MUX4_M 0x00070000 // 5th Sample Input Select.
#define ADC_SSMUX0_MUX3_M 0x00007000 // 4th Sample Input Select.
#define ADC_SSMUX0_MUX2_M 0x00000700 // 3rd Sample Input Select.
#define ADC_SSMUX0_MUX1_M 0x00000070 // 2nd Sample Input Select.
#define ADC_SSMUX0_MUX0_M 0x00000007 // 1st Sample Input Select.
#define ADC_SSMUX0_MUX7_S 28
#define ADC_SSMUX0_MUX6_S 24
#define ADC_SSMUX0_MUX5_S 20
#define ADC_SSMUX0_MUX4_S 16
#define ADC_SSMUX0_MUX3_S 12
#define ADC_SSMUX0_MUX2_S 8
#define ADC_SSMUX0_MUX1_S 4
#define ADC_SSMUX0_MUX0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSCTL0 register.
//
//*****************************************************************************
#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select.
#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable.
#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence.
#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Diff Input Select.
#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select.
#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable.
#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence.
#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Diff Input Select.
#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select.
#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable.
#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence.
#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Diff Input Select.
#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select.
#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable.
#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence.
#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Diff Input Select.
#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select.
#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable.
#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence.
#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Diff Input Select.
#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select.
#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable.
#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence.
#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Diff Input Select.
#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select.
#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable.
#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence.
#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Diff Input Select.
#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select.
#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable.
#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence.
#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Diff Input Select.
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
//
//*****************************************************************************
#define ADC_SSFIFO0_DATA_M 0x000003FF // Conversion Result Data.
#define ADC_SSFIFO0_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
//
//*****************************************************************************
#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full.
#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty.
#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer.
#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer.
#define ADC_SSFSTAT0_HPTR_S 4
#define ADC_SSFSTAT0_TPTR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSMUX1 register.
//
//*****************************************************************************
#define ADC_SSMUX1_MUX3_M 0x00007000 // 4th Sample Input Select.
#define ADC_SSMUX1_MUX2_M 0x00000700 // 3rd Sample Input Select.
#define ADC_SSMUX1_MUX1_M 0x00000070 // 2nd Sample Input Select.
#define ADC_SSMUX1_MUX0_M 0x00000007 // 1st Sample Input Select.
#define ADC_SSMUX1_MUX3_S 12
#define ADC_SSMUX1_MUX2_S 8
#define ADC_SSMUX1_MUX1_S 4
#define ADC_SSMUX1_MUX0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSCTL1 register.
//
//*****************************************************************************
#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select.
#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable.
#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence.
#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Diff Input Select.
#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select.
#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable.
#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence.
#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Diff Input Select.
#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select.
#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable.
#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence.
#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Diff Input Select.
#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select.
#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable.
#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence.
#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Diff Input Select.
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
//
//*****************************************************************************
#define ADC_SSFIFO1_DATA_M 0x000003FF // Conversion Result Data.
#define ADC_SSFIFO1_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
//
//*****************************************************************************
#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full.
#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty.
#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer.
#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer.
#define ADC_SSFSTAT1_HPTR_S 4
#define ADC_SSFSTAT1_TPTR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSMUX2 register.
//
//*****************************************************************************
#define ADC_SSMUX2_MUX3_M 0x00007000 // 4th Sample Input Select.
#define ADC_SSMUX2_MUX2_M 0x00000700 // 3rd Sample Input Select.
#define ADC_SSMUX2_MUX1_M 0x00000070 // 2nd Sample Input Select.
#define ADC_SSMUX2_MUX0_M 0x00000007 // 1st Sample Input Select.
#define ADC_SSMUX2_MUX3_S 12
#define ADC_SSMUX2_MUX2_S 8
#define ADC_SSMUX2_MUX1_S 4
#define ADC_SSMUX2_MUX0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSCTL2 register.
//
//*****************************************************************************
#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select.
#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable.
#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence.
#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Diff Input Select.
#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select.
#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable.
#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence.
#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Diff Input Select.
#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select.
#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable.
#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence.
#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Diff Input Select.
#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select.
#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable.
#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence.
#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Diff Input Select.
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
//
//*****************************************************************************
#define ADC_SSFIFO2_DATA_M 0x000003FF // Conversion Result Data.
#define ADC_SSFIFO2_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
//
//*****************************************************************************
#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full.
#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty.
#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer.
#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer.
#define ADC_SSFSTAT2_HPTR_S 4
#define ADC_SSFSTAT2_TPTR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSMUX3 register.
//
//*****************************************************************************
#define ADC_SSMUX3_MUX0_M 0x00000007 // 1st Sample Input Select.
#define ADC_SSMUX3_MUX0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSCTL3 register.
//
//*****************************************************************************
#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select.
#define ADC_SSCTL3_IE0 0x00000004 // 1st Sample Interrupt Enable.
#define ADC_SSCTL3_END0 0x00000002 // 1st Sample is End of Sequence.
#define ADC_SSCTL3_D0 0x00000001 // 1st Sample Diff Input Select.
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
//
//*****************************************************************************
#define ADC_SSFIFO3_DATA_M 0x000003FF // Conversion Result Data.
#define ADC_SSFIFO3_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
//
//*****************************************************************************
#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full.
#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty.
#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer.
#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer.
#define ADC_SSFSTAT3_HPTR_S 4
#define ADC_SSFSTAT3_TPTR_S 0
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the ADC sequence register offsets.
//
//*****************************************************************************
#define ADC_O_SEQ 0x00000040 // Offset to the first sequence
#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence
#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register
#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register
#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register
#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the ADC_EMUX
// register.
//
//*****************************************************************************
#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask
#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask
#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask
#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask
#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event
#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event
#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event
#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the ADC_SSPRI
// register.
//
//*****************************************************************************
#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask
#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask
#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask
#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the ADC_SSMUX0,
// ADC_SSMUX1, ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present
// in all registers.
//
//*****************************************************************************
#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask
#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask
#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask
#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask
#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask
#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask
#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask
#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask
#define ADC_SSMUX_MUX7_SHIFT 28
#define ADC_SSMUX_MUX6_SHIFT 24
#define ADC_SSMUX_MUX5_SHIFT 20
#define ADC_SSMUX_MUX4_SHIFT 16
#define ADC_SSMUX_MUX3_SHIFT 12
#define ADC_SSMUX_MUX2_SHIFT 8
#define ADC_SSMUX_MUX1_SHIFT 4
#define ADC_SSMUX_MUX0_SHIFT 0
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the ADC_SSCTL0,
// ADC_SSCTL1, ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present
// in all registers.
//
//*****************************************************************************
#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select
#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable
#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select
#define ADC_SSCTL_D7 0x10000000 // 8th differential select
#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select
#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable
#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select
#define ADC_SSCTL_D6 0x01000000 // 7th differential select
#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select
#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable
#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select
#define ADC_SSCTL_D5 0x00100000 // 6th differential select
#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select
#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable
#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select
#define ADC_SSCTL_D4 0x00010000 // 5th differential select
#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select
#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable
#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select
#define ADC_SSCTL_D3 0x00001000 // 4th differential select
#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select
#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable
#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select
#define ADC_SSCTL_D2 0x00000100 // 3rd differential select
#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select
#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable
#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select
#define ADC_SSCTL_D1 0x00000010 // 2nd differential select
#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select
#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable
#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select
#define ADC_SSCTL_D0 0x00000001 // 1st differential select
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the ADC_SSFIFO0,
// ADC_SSFIFO1, ADC_SSFIFO2, and ADC_SSFIFO3 registers.
//
//*****************************************************************************
#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data
#define ADC_SSFIFO_DATA_SHIFT 0
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the ADC_SSFSTAT0,
// ADC_SSFSTAT1, ADC_SSFSTAT2, and ADC_SSFSTAT3 registers.
//
//*****************************************************************************
#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full
#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty
#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer
#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the loopback ADC
// data.
//
//*****************************************************************************
#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask
#define ADC_LB_CONT 0x00000020 // Continuation sample
#define ADC_LB_DIFF 0x00000010 // Differential sample
#define ADC_LB_TS 0x00000008 // Temperature sensor sample
#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask
#define ADC_LB_CNT_SHIFT 6 // Sample counter shift
#define ADC_LB_MUX_SHIFT 0 // Input channel number shift
#endif
#endif // __HW_ADC_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/hw_adc.h | C | oos | 34,735 |
//*****************************************************************************
//
// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __PWM_H__
#define __PWM_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following defines are passed to PWMGenConfigure() as the ulConfig
// parameter and specify the configuration of the PWM generator.
//
//*****************************************************************************
#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode
#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode
#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates
#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates
#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode
#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode
#define PWM_GEN_MODE_FAULT_LATCHED \
0x00040000 // Fault is latched
#define PWM_GEN_MODE_FAULT_UNLATCHED \
0x00000000 // Fault is not latched
#define PWM_GEN_MODE_FAULT_MINPER \
0x00020000 // Enable min fault period
#define PWM_GEN_MODE_FAULT_NO_MINPER \
0x00000000 // Disable min fault period
#define PWM_GEN_MODE_FAULT_EXT 0x00010000 // Enable extended fault support
#define PWM_GEN_MODE_FAULT_LEGACY \
0x00000000 // Disable extended fault support
#define PWM_GEN_MODE_DB_NO_SYNC 0x00000000 // Deadband updates occur
// immediately
#define PWM_GEN_MODE_DB_SYNC_LOCAL \
0x0000A800 // Deadband updates locally
// synchronized
#define PWM_GEN_MODE_DB_SYNC_GLOBAL \
0x0000FC00 // Deadband updates globally
// synchronized
#define PWM_GEN_MODE_GEN_NO_SYNC \
0x00000000 // Generator mode updates occur
// immediately
#define PWM_GEN_MODE_GEN_SYNC_LOCAL \
0x00000280 // Generator mode updates locally
// synchronized
#define PWM_GEN_MODE_GEN_SYNC_GLOBAL \
0x000003C0 // Generator mode updates globally
// synchronized
//*****************************************************************************
//
// Defines for enabling, disabling, and clearing PWM generator interrupts and
// triggers.
//
//*****************************************************************************
#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0
#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD
#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U
#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D
#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U
#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D
#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0
#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD
#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U
#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D
#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U
#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D
//*****************************************************************************
//
// Defines for enabling, disabling, and clearing PWM interrupts.
//
//*****************************************************************************
#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt
#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt
#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt
#define PWM_INT_GEN_3 0x00000008 // Generator 3 interrupt
#ifndef DEPRECATED
#define PWM_INT_FAULT 0x00010000 // Fault interrupt
#endif
#define PWM_INT_FAULT0 0x00010000 // Fault0 interrupt
#define PWM_INT_FAULT1 0x00020000 // Fault1 interrupt
#define PWM_INT_FAULT2 0x00040000 // Fault2 interrupt
#define PWM_INT_FAULT3 0x00080000 // Fault3 interrupt
#define PWM_INT_FAULT_M 0x000F0000 // Fault interrupt source mask
//*****************************************************************************
//
// Defines to identify the generators within a module.
//
//*****************************************************************************
#define PWM_GEN_0 0x00000040 // Offset address of Gen0
#define PWM_GEN_1 0x00000080 // Offset address of Gen1
#define PWM_GEN_2 0x000000C0 // Offset address of Gen2
#define PWM_GEN_3 0x00000100 // Offset address of Gen3
#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0
#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1
#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2
#define PWM_GEN_3_BIT 0x00000008 // Bit-wise ID for Gen3
#define PWM_GEN_EXT_0 0x00000800 // Offset of Gen0 ext address range
#define PWM_GEN_EXT_1 0x00000880 // Offset of Gen1 ext address range
#define PWM_GEN_EXT_2 0x00000900 // Offset of Gen2 ext address range
#define PWM_GEN_EXT_3 0x00000980 // Offset of Gen3 ext address range
//*****************************************************************************
//
// Defines to identify the outputs within a module.
//
//*****************************************************************************
#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0
#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1
#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2
#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3
#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4
#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5
#define PWM_OUT_6 0x00000106 // Encoded offset address of PWM6
#define PWM_OUT_7 0x00000107 // Encoded offset address of PWM7
#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0
#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1
#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2
#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3
#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4
#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5
#define PWM_OUT_6_BIT 0x00000040 // Bit-wise ID for PWM6
#define PWM_OUT_7_BIT 0x00000080 // Bit-wise ID for PWM7
//*****************************************************************************
//
// Defines to identify each of the possible fault trigger conditions in
// PWM_FAULT_GROUP_0
//
//*****************************************************************************
#define PWM_FAULT_GROUP_0 0
#define PWM_FAULT_FAULT0 0x00000001
#define PWM_FAULT_FAULT1 0x00000002
#define PWM_FAULT_FAULT2 0x00000004
#define PWM_FAULT_FAULT3 0x00000008
#define PWM_FAULT_ACMP0 0x00010000
#define PWM_FAULT_ACMP1 0x00020000
#define PWM_FAULT_ACMP2 0x00040000
//*****************************************************************************
//
// Defines to identify the sense of each of the external FAULTn signals
//
//*****************************************************************************
#define PWM_FAULT0_SENSE_HIGH 0x00000000
#define PWM_FAULT0_SENSE_LOW 0x00000001
#define PWM_FAULT1_SENSE_HIGH 0x00000000
#define PWM_FAULT1_SENSE_LOW 0x00000002
#define PWM_FAULT2_SENSE_HIGH 0x00000000
#define PWM_FAULT2_SENSE_LOW 0x00000004
#define PWM_FAULT3_SENSE_HIGH 0x00000000
#define PWM_FAULT3_SENSE_LOW 0x00000008
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,
unsigned long ulConfig);
extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,
unsigned long ulPeriod);
extern unsigned long PWMGenPeriodGet(unsigned long ulBase,
unsigned long ulGen);
extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen);
extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen);
extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,
unsigned long ulWidth);
extern unsigned long PWMPulseWidthGet(unsigned long ulBase,
unsigned long ulPWMOut);
extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,
unsigned short usRise, unsigned short usFall);
extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen);
extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits);
extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits);
extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,
tBoolean bEnable);
extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,
tBoolean bInvert);
extern void PWMOutputFaultLevel(unsigned long ulBase,
unsigned long ulPWMOutBits,
tBoolean bDriveHigh);
extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,
tBoolean bFaultSuppress);
extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,
void (*pfnIntHandler)(void));
extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen);
extern void PWMFaultIntRegister(unsigned long ulBase,
void (*pfnIntHandler)(void));
extern void PWMFaultIntUnregister(unsigned long ulBase);
extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,
unsigned long ulIntTrig);
extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,
unsigned long ulIntTrig);
extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen,
tBoolean bMasked);
extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen,
unsigned long ulInts);
extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault);
extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault);
extern void PWMFaultIntClear(unsigned long ulBase);
extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void PWMFaultIntClearExt(unsigned long ulBase,
unsigned long ulFaultInts);
extern void PWMGenFaultConfigure(unsigned long ulBase, unsigned long ulGen,
unsigned long ulMinFaultPeriod,
unsigned long ulFaultSenses);
extern void PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen,
unsigned long ulGroup,
unsigned long ulFaultTriggers);
extern unsigned long PWMGenFaultTriggerGet(unsigned long ulBase,
unsigned long ulGen,
unsigned long ulGroup);
extern unsigned long PWMGenFaultStatus(unsigned long ulBase,
unsigned long ulGen,
unsigned long ulGroup);
extern void PWMGenFaultClear(unsigned long ulBase, unsigned long ulGen,
unsigned long ulGroup,
unsigned long ulFaultTriggers);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __PWM_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/pwm.h | C | oos | 14,389 |
//*****************************************************************************
//
// can.h - Defines and Macros for the CAN controller.
//
// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __CAN_H__
#define __CAN_H__
//*****************************************************************************
//
//! \addtogroup can_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Miscellaneous defines for Message ID Types
//
//*****************************************************************************
//*****************************************************************************
//
//! These are the flags used by the tCANMsgObject variable when calling the
//! CANMessageSet() and CANMessageGet() functions.
//
//*****************************************************************************
typedef enum
{
//
//! This indicates that transmit interrupts should be enabled, or are
//! enabled.
//
MSG_OBJ_TX_INT_ENABLE = 0x00000001,
//
//! This indicates that receive interrupts should be enabled, or are
//! enabled.
//
MSG_OBJ_RX_INT_ENABLE = 0x00000002,
//
//! This indicates that a message object will use or is using an extended
//! identifier.
//
MSG_OBJ_EXTENDED_ID = 0x00000004,
//
//! This indicates that a message object will use or is using filtering
//! based on the object's message identifier.
//
MSG_OBJ_USE_ID_FILTER = 0x00000008,
//
//! This indicates that new data was available in the message object.
//
MSG_OBJ_NEW_DATA = 0x00000080,
//
//! This indicates that data was lost since this message object was last
//! read.
//
MSG_OBJ_DATA_LOST = 0x00000100,
//
//! This indicates that a message object will use or is using filtering
//! based on the direction of the transfer. If the direction filtering is
//! used, then ID filtering must also be enabled.
//
MSG_OBJ_USE_DIR_FILTER = (0x00000010 | MSG_OBJ_USE_ID_FILTER),
//
//! This indicates that a message object will use or is using message
//! identifier filtering based on the extended identifier. If the extended
//! identifier filtering is used, then ID filtering must also be enabled.
//
MSG_OBJ_USE_EXT_FILTER = (0x00000020 | MSG_OBJ_USE_ID_FILTER),
//
//! This indicates that a message object is a remote frame.
//
MSG_OBJ_REMOTE_FRAME = 0x00000040,
//
//! This indicates that a message object has no flags set.
//
MSG_OBJ_NO_FLAGS = 0x00000000
}
tCANObjFlags;
//*****************************************************************************
//
//! This define is used with the #tCANObjFlags enumerated values to allow
//! checking only status flags and not configuration flags.
//
//*****************************************************************************
#define MSG_OBJ_STATUS_MASK (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST)
//*****************************************************************************
//
//! The structure used for encapsulating all the items associated with a CAN
//! message object in the CAN controller.
//
//*****************************************************************************
typedef struct
{
//
//! The CAN message identifier used for 11 or 29 bit identifiers.
//
unsigned long ulMsgID;
//
//! The message identifier mask used when identifier filtering is enabled.
//
unsigned long ulMsgIDMask;
//
//! This value holds various status flags and settings specified by
//! tCANObjFlags.
//
unsigned long ulFlags;
//
//! This value is the number of bytes of data in the message object.
//
unsigned long ulMsgLen;
//
//! This is a pointer to the message object's data.
//
unsigned char *pucMsgData;
}
tCANMsgObject;
//*****************************************************************************
//
//! This structure is used for encapsulating the values associated with setting
//! up the bit timing for a CAN controller. The structure is used when calling
//! the CANGetBitTiming and CANSetBitTiming functions.
//
//*****************************************************************************
typedef struct
{
//
//! This value holds the sum of the Synchronization, Propagation, and Phase
//! Buffer 1 segments, measured in time quanta. The valid values for this
//! setting range from 2 to 16.
//
unsigned int uSyncPropPhase1Seg;
//
//! This value holds the Phase Buffer 2 segment in time quanta. The valid
//! values for this setting range from 1 to 8.
//
unsigned int uPhase2Seg;
//
//! This value holds the Resynchronization Jump Width in time quanta. The
//! valid values for this setting range from 1 to 4.
//
unsigned int uSJW;
//
//! This value holds the CAN_CLK divider used to determine time quanta.
//! The valid values for this setting range from 1 to 1023.
//
unsigned int uQuantumPrescaler;
}
tCANBitClkParms;
//*****************************************************************************
//
//! This data type is used to identify the interrupt status register. This is
//! used when calling the CANIntStatus() function.
//
//*****************************************************************************
typedef enum
{
//
//! Read the CAN interrupt status information.
//
CAN_INT_STS_CAUSE,
//
//! Read a message object's interrupt status.
//
CAN_INT_STS_OBJECT
}
tCANIntStsReg;
//*****************************************************************************
//
//! This data type is used to identify which of several status registers to
//! read when calling the CANStatusGet() function.
//
//*****************************************************************************
typedef enum
{
//
//! Read the full CAN controller status.
//
CAN_STS_CONTROL,
//
//! Read the full 32-bit mask of message objects with a transmit request
//! set.
//
CAN_STS_TXREQUEST,
//
//! Read the full 32-bit mask of message objects with new data available.
//
CAN_STS_NEWDAT,
//
//! Read the full 32-bit mask of message objects that are enabled.
//
CAN_STS_MSGVAL
}
tCANStsReg;
//*****************************************************************************
//
//! These definitions are used to specify interrupt sources to CANIntEnable()
//! and CANIntDisable().
//
//*****************************************************************************
typedef enum
{
//
//! This flag is used to allow a CAN controller to generate error
//! interrupts.
//
CAN_INT_ERROR = 0x00000008,
//
//! This flag is used to allow a CAN controller to generate status
//! interrupts.
//
CAN_INT_STATUS = 0x00000004,
//
//! This flag is used to allow a CAN controller to generate any CAN
//! interrupts. If this is not set, then no interrupts will be generated
//! by the CAN controller.
//
CAN_INT_MASTER = 0x00000002
}
tCANIntFlags;
//*****************************************************************************
//
//! This definition is used to determine the type of message object that will
//! be set up via a call to the CANMessageSet() API.
//
//*****************************************************************************
typedef enum
{
//
//! Transmit message object.
//
MSG_OBJ_TYPE_TX,
//
//! Transmit remote request message object
//
MSG_OBJ_TYPE_TX_REMOTE,
//
//! Receive message object.
//
MSG_OBJ_TYPE_RX,
//
//! Receive remote request message object.
//
MSG_OBJ_TYPE_RX_REMOTE,
//
//! Remote frame receive remote, with auto-transmit message object.
//
MSG_OBJ_TYPE_RXTX_REMOTE
}
tMsgObjType;
//*****************************************************************************
//
//! The following enumeration contains all error or status indicators that can
//! be returned when calling the CANStatusGet() function.
//
//*****************************************************************************
typedef enum
{
//
//! CAN controller has entered a Bus Off state.
//
CAN_STATUS_BUS_OFF = 0x00000080,
//
//! CAN controller error level has reached warning level.
//
CAN_STATUS_EWARN = 0x00000040,
//
//! CAN controller error level has reached error passive level.
//
CAN_STATUS_EPASS = 0x00000020,
//
//! A message was received successfully since the last read of this status.
//
CAN_STATUS_RXOK = 0x00000010,
//
//! A message was transmitted successfully since the last read of this
//! status.
//
CAN_STATUS_TXOK = 0x00000008,
//
//! This is the mask for the last error code field.
//
CAN_STATUS_LEC_MSK = 0x00000007,
//
//! There was no error.
//
CAN_STATUS_LEC_NONE = 0x00000000,
//
//! A bit stuffing error has occurred.
//
CAN_STATUS_LEC_STUFF = 0x00000001,
//
//! A formatting error has occurred.
//
CAN_STATUS_LEC_FORM = 0x00000002,
//
//! An acknowledge error has occurred.
//
CAN_STATUS_LEC_ACK = 0x00000003,
//
//! The bus remained a bit level of 1 for longer than is allowed.
//
CAN_STATUS_LEC_BIT1 = 0x00000004,
//
//! The bus remained a bit level of 0 for longer than is allowed.
//
CAN_STATUS_LEC_BIT0 = 0x00000005,
//
//! A CRC error has occurred.
//
CAN_STATUS_LEC_CRC = 0x00000006,
//
//! This is the mask for the CAN Last Error Code (LEC).
//
CAN_STATUS_LEC_MASK = 0x00000007
}
tCANStatusCtrl;
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void CANInit(unsigned long ulBase);
extern void CANEnable(unsigned long ulBase);
extern void CANDisable(unsigned long ulBase);
extern void CANSetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms);
extern void CANGetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms);
extern unsigned long CANReadReg(unsigned long ulRegAddress);
extern void CANWriteReg(unsigned long ulRegAddress, unsigned long ulRegValue);
extern void CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
tCANMsgObject *pMsgObject, tMsgObjType eMsgType);
extern void CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
tCANMsgObject *pMsgObject, tBoolean bClrPendingInt);
extern unsigned long CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg);
extern void CANMessageClear(unsigned long ulBase, unsigned long ulObjID);
extern void CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern void CANIntUnregister(unsigned long ulBase);
extern void CANIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern void CANIntClear(unsigned long ulBase, unsigned long ulIntClr);
extern unsigned long CANIntStatus(unsigned long ulBase,
tCANIntStsReg eIntStsReg);
extern tBoolean CANRetryGet(unsigned long ulBase);
extern void CANRetrySet(unsigned long ulBase, tBoolean bAutoRetry);
extern tBoolean CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount,
unsigned long *pulTxCount);
extern long CANGetIntNumber(unsigned long ulBase);
extern void CANReadDataReg(unsigned char *pucData, unsigned long *pulRegister,
int iSize);
extern void CANWriteDataReg(unsigned char *pucData, unsigned long *pulRegister,
int iSize);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
#endif // __CAN_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/can.h | C | oos | 14,537 |
//*****************************************************************************
//
// hw_can.h - Defines and macros used when accessing the can.
//
// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_CAN_H__
#define __HW_CAN_H__
//*****************************************************************************
//
// The following are defines for the CAN register offsets.
//
//*****************************************************************************
#define CAN_O_CTL 0x00000000 // Control register
#define CAN_O_STS 0x00000004 // Status register
#define CAN_O_ERR 0x00000008 // Error register
#define CAN_O_BIT 0x0000000C // Bit Timing register
#define CAN_O_INT 0x00000010 // Interrupt register
#define CAN_O_TST 0x00000014 // Test register
#define CAN_O_BRPE 0x00000018 // Baud Rate Prescaler register
#define CAN_O_IF1CRQ 0x00000020 // Interface 1 Command Request reg.
#define CAN_O_IF1CMSK 0x00000024 // Interface 1 Command Mask reg.
#define CAN_O_IF1MSK1 0x00000028 // Interface 1 Mask 1 register
#define CAN_O_IF1MSK2 0x0000002C // Interface 1 Mask 2 register
#define CAN_O_IF1ARB1 0x00000030 // Interface 1 Arbitration 1 reg.
#define CAN_O_IF1ARB2 0x00000034 // Interface 1 Arbitration 2 reg.
#define CAN_O_IF1MCTL 0x00000038 // Interface 1 Message Control reg.
#define CAN_O_IF1DA1 0x0000003C // Interface 1 DataA 1 register
#define CAN_O_IF1DA2 0x00000040 // Interface 1 DataA 2 register
#define CAN_O_IF1DB1 0x00000044 // Interface 1 DataB 1 register
#define CAN_O_IF1DB2 0x00000048 // Interface 1 DataB 2 register
#define CAN_O_IF2CRQ 0x00000080 // Interface 2 Command Request reg.
#define CAN_O_IF2CMSK 0x00000084 // Interface 2 Command Mask reg.
#define CAN_O_IF2MSK1 0x00000088 // Interface 2 Mask 1 register
#define CAN_O_IF2MSK2 0x0000008C // Interface 2 Mask 2 register
#define CAN_O_IF2ARB1 0x00000090 // Interface 2 Arbitration 1 reg.
#define CAN_O_IF2ARB2 0x00000094 // Interface 2 Arbitration 2 reg.
#define CAN_O_IF2MCTL 0x00000098 // Interface 2 Message Control reg.
#define CAN_O_IF2DA1 0x0000009C // Interface 2 DataA 1 register
#define CAN_O_IF2DA2 0x000000A0 // Interface 2 DataA 2 register
#define CAN_O_IF2DB1 0x000000A4 // Interface 2 DataB 1 register
#define CAN_O_IF2DB2 0x000000A8 // Interface 2 DataB 2 register
#define CAN_O_TXRQ1 0x00000100 // Transmission Request 1 register
#define CAN_O_TXRQ2 0x00000104 // Transmission Request 2 register
#define CAN_O_NWDA1 0x00000120 // New Data 1 register
#define CAN_O_NWDA2 0x00000124 // New Data 2 register
#define CAN_O_MSG1INT 0x00000140 // CAN Message 1 Interrupt Pending
#define CAN_O_MSG2INT 0x00000144 // CAN Message 2 Interrupt Pending
#define CAN_O_MSG1VAL 0x00000160 // CAN Message 1 Valid
#define CAN_O_MSG2VAL 0x00000164 // CAN Message 2 Valid
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_CTL register.
//
//*****************************************************************************
#define CAN_CTL_TEST 0x00000080 // Test mode enable
#define CAN_CTL_CCE 0x00000040 // Configuration change enable
#define CAN_CTL_DAR 0x00000020 // Disable automatic retransmission
#define CAN_CTL_EIE 0x00000008 // Error interrupt enable
#define CAN_CTL_SIE 0x00000004 // Status change interrupt enable
#define CAN_CTL_IE 0x00000002 // Module interrupt enable
#define CAN_CTL_INIT 0x00000001 // Initialization
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_STS register.
//
//*****************************************************************************
#define CAN_STS_BOFF 0x00000080 // Bus Off status
#define CAN_STS_EWARN 0x00000040 // Error Warning status
#define CAN_STS_EPASS 0x00000020 // Error Passive status
#define CAN_STS_RXOK 0x00000010 // Received Message Successful
#define CAN_STS_TXOK 0x00000008 // Transmitted Message Successful
#define CAN_STS_LEC_M 0x00000007 // Last Error Code
#define CAN_STS_LEC_NONE 0x00000000 // No error
#define CAN_STS_LEC_STUFF 0x00000001 // Stuff error
#define CAN_STS_LEC_FORM 0x00000002 // Form(at) error
#define CAN_STS_LEC_ACK 0x00000003 // Ack error
#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 error
#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 error
#define CAN_STS_LEC_CRC 0x00000006 // CRC error
#define CAN_STS_LEC_NOEVENT 0x00000007 // Unused
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_ERR register.
//
//*****************************************************************************
#define CAN_ERR_RP 0x00008000 // Receive error passive status
#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter.
#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter.
#define CAN_ERR_REC_S 8 // Receive error counter bit pos
#define CAN_ERR_TEC_S 0 // Transmit error counter bit pos
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_BIT register.
//
//*****************************************************************************
#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point.
#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample
// Point.
#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width.
#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescalar.
#define CAN_BIT_TSEG2_S 12
#define CAN_BIT_TSEG1_S 8
#define CAN_BIT_SJW_S 6
#define CAN_BIT_BRP_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_INT register.
//
//*****************************************************************************
#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier.
#define CAN_INT_INTID_NONE 0x00000000 // No Interrupt Pending
#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_TST register.
//
//*****************************************************************************
#define CAN_TST_RX 0x00000080 // CAN_RX pin status
#define CAN_TST_TX_M 0x00000060 // Overide control of CAN_TX pin
#define CAN_TST_TX_CANCTL 0x00000000 // CAN core controls CAN_TX
#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point on CAN_TX
#define CAN_TST_TX_DOMINANT 0x00000040 // Dominant value on CAN_TX
#define CAN_TST_TX_RECESSIVE 0x00000060 // Recessive value on CAN_TX
#define CAN_TST_LBACK 0x00000010 // Loop back mode
#define CAN_TST_SILENT 0x00000008 // Silent mode
#define CAN_TST_BASIC 0x00000004 // Basic mode
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_BRPE register.
//
//*****************************************************************************
#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescalar Extension.
#define CAN_BRPE_BRPE_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_TXRQ1 register.
//
//*****************************************************************************
#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits.
#define CAN_TXRQ1_TXRQST_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_TXRQ2 register.
//
//*****************************************************************************
#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits.
#define CAN_TXRQ2_TXRQST_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_NWDA1 register.
//
//*****************************************************************************
#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits.
#define CAN_NWDA1_NEWDAT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_NWDA2 register.
//
//*****************************************************************************
#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits.
#define CAN_NWDA2_NEWDAT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1CRQ register.
//
//*****************************************************************************
#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag.
#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number.
#define CAN_IF1CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number;
// it is interpreted as 0x20, or
// object 32.
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1CMSK register.
//
//*****************************************************************************
#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read.
#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits.
#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits.
#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits.
#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit.
#define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data.
#define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request.
#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3.
#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7.
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1MSK1 register.
//
//*****************************************************************************
#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask.
#define CAN_IF1MSK1_IDMSK_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1MSK2 register.
//
//*****************************************************************************
#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier.
#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction.
#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask.
#define CAN_IF1MSK2_IDMSK_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1ARB1 register.
//
//*****************************************************************************
#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier.
#define CAN_IF1ARB1_ID_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1ARB2 register.
//
//*****************************************************************************
#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid.
#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier.
#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction.
#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier.
#define CAN_IF1ARB2_ID_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1MCTL register.
//
//*****************************************************************************
#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data.
#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost.
#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending.
#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask.
#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable.
#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable.
#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable.
#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request.
#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer.
#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code.
#define CAN_IF1MCTL_DLC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1DA1 register.
//
//*****************************************************************************
#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data.
#define CAN_IF1DA1_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1DA2 register.
//
//*****************************************************************************
#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data.
#define CAN_IF1DA2_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1DB1 register.
//
//*****************************************************************************
#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data.
#define CAN_IF1DB1_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1DB2 register.
//
//*****************************************************************************
#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data.
#define CAN_IF1DB2_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2CRQ register.
//
//*****************************************************************************
#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag.
#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number.
#define CAN_IF2CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number;
// it is interpreted as 0x20, or
// object 32.
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2CMSK register.
//
//*****************************************************************************
#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read.
#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits.
#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits.
#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits.
#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit.
#define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data.
#define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request.
#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3.
#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7.
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2MSK1 register.
//
//*****************************************************************************
#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask.
#define CAN_IF2MSK1_IDMSK_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2MSK2 register.
//
//*****************************************************************************
#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier.
#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction.
#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask.
#define CAN_IF2MSK2_IDMSK_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2ARB1 register.
//
//*****************************************************************************
#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier.
#define CAN_IF2ARB1_ID_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2ARB2 register.
//
//*****************************************************************************
#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid.
#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier.
#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction.
#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier.
#define CAN_IF2ARB2_ID_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2MCTL register.
//
//*****************************************************************************
#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data.
#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost.
#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending.
#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask.
#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable.
#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable.
#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable.
#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request.
#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer.
#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code.
#define CAN_IF2MCTL_DLC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2DA1 register.
//
//*****************************************************************************
#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data.
#define CAN_IF2DA1_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2DA2 register.
//
//*****************************************************************************
#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data.
#define CAN_IF2DA2_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2DB1 register.
//
//*****************************************************************************
#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data.
#define CAN_IF2DB1_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2DB2 register.
//
//*****************************************************************************
#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data.
#define CAN_IF2DB2_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_MSG1INT register.
//
//*****************************************************************************
#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits.
#define CAN_MSG1INT_INTPND_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_MSG2INT register.
//
//*****************************************************************************
#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits.
#define CAN_MSG2INT_INTPND_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_MSG1VAL register.
//
//*****************************************************************************
#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits.
#define CAN_MSG1VAL_MSGVAL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_MSG2VAL register.
//
//*****************************************************************************
#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits.
#define CAN_MSG2VAL_MSGVAL_S 0
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the CAN register offsets.
//
//*****************************************************************************
#define CAN_O_MSGINT1 0x00000140 // Intr. Pending in Msg Obj 1 reg.
#define CAN_O_MSGINT2 0x00000144 // Intr. Pending in Msg Obj 2 reg.
#define CAN_O_MSGVAL1 0x00000160 // Message Valid in Msg Obj 1 reg.
#define CAN_O_MSGVAL2 0x00000164 // Message Valid in Msg Obj 2 reg.
//*****************************************************************************
//
// The following are deprecated defines for the reset values of the can
// registers.
//
//*****************************************************************************
#define CAN_RV_IF1MSK2 0x0000FFFF
#define CAN_RV_IF1MSK1 0x0000FFFF
#define CAN_RV_IF2MSK1 0x0000FFFF
#define CAN_RV_IF2MSK2 0x0000FFFF
#define CAN_RV_BIT 0x00002301
#define CAN_RV_CTL 0x00000001
#define CAN_RV_IF1CRQ 0x00000001
#define CAN_RV_IF2CRQ 0x00000001
#define CAN_RV_TXRQ2 0x00000000
#define CAN_RV_IF2DB1 0x00000000
#define CAN_RV_INT 0x00000000
#define CAN_RV_IF1DB2 0x00000000
#define CAN_RV_BRPE 0x00000000
#define CAN_RV_IF2DA2 0x00000000
#define CAN_RV_MSGVAL2 0x00000000
#define CAN_RV_TXRQ1 0x00000000
#define CAN_RV_IF1MCTL 0x00000000
#define CAN_RV_IF1DB1 0x00000000
#define CAN_RV_STS 0x00000000
#define CAN_RV_MSGINT1 0x00000000
#define CAN_RV_IF1DA2 0x00000000
#define CAN_RV_TST 0x00000000
#define CAN_RV_IF1ARB1 0x00000000
#define CAN_RV_IF1ARB2 0x00000000
#define CAN_RV_NWDA2 0x00000000
#define CAN_RV_IF2CMSK 0x00000000
#define CAN_RV_NWDA1 0x00000000
#define CAN_RV_IF1DA1 0x00000000
#define CAN_RV_IF2DA1 0x00000000
#define CAN_RV_IF2MCTL 0x00000000
#define CAN_RV_MSGVAL1 0x00000000
#define CAN_RV_IF1CMSK 0x00000000
#define CAN_RV_ERR 0x00000000
#define CAN_RV_IF2ARB2 0x00000000
#define CAN_RV_MSGINT2 0x00000000
#define CAN_RV_IF2ARB1 0x00000000
#define CAN_RV_IF2DB2 0x00000000
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_STS
// register.
//
//*****************************************************************************
#define CAN_STS_LEC_MSK 0x00000007 // Last Error Code
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_ERR
// register.
//
//*****************************************************************************
#define CAN_ERR_REC_MASK 0x00007F00 // Receive error counter status
#define CAN_ERR_TEC_MASK 0x000000FF // Transmit error counter status
#define CAN_ERR_REC_SHIFT 8 // Receive error counter bit pos
#define CAN_ERR_TEC_SHIFT 0 // Transmit error counter bit pos
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_BIT
// register.
//
//*****************************************************************************
#define CAN_BIT_TSEG2 0x00007000 // Time segment after sample point
#define CAN_BIT_TSEG1 0x00000F00 // Time segment before sample point
#define CAN_BIT_SJW 0x000000C0 // (Re)Synchronization jump width
#define CAN_BIT_BRP 0x0000003F // Baud rate prescaler
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_INT
// register.
//
//*****************************************************************************
#define CAN_INT_INTID_MSK 0x0000FFFF // Interrupt Identifier
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_TST
// register.
//
//*****************************************************************************
#define CAN_TST_TX_MSK 0x00000060 // Overide control of CAN_TX pin
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_BRPE
// register.
//
//*****************************************************************************
#define CAN_BRPE_BRPE 0x0000000F // Baud rate prescaler extension
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1CRQ
// and CAN_IF1CRQ registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFCRQ_BUSY 0x00008000 // Busy flag status
#define CAN_IFCRQ_MNUM_MSK 0x0000003F // Message Number
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1CMSK
// and CAN_IF2CMSK registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFCMSK_WRNRD 0x00000080 // Write, not Read
#define CAN_IFCMSK_MASK 0x00000040 // Access Mask Bits
#define CAN_IFCMSK_ARB 0x00000020 // Access Arbitration Bits
#define CAN_IFCMSK_CONTROL 0x00000010 // Access Control Bits
#define CAN_IFCMSK_CLRINTPND 0x00000008 // Clear interrupt pending Bit
#define CAN_IFCMSK_TXRQST 0x00000004 // Access Tx request bit (WRNRD=1)
#define CAN_IFCMSK_NEWDAT 0x00000004 // Access New Data bit (WRNRD=0)
#define CAN_IFCMSK_DATAA 0x00000002 // DataA access - bytes 0 to 3
#define CAN_IFCMSK_DATAB 0x00000001 // DataB access - bytes 4 to 7
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1MSK1
// and CAN_IF2MSK1 registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFMSK1_MSK 0x0000FFFF // Identifier Mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1MSK2
// and CAN_IF2MSK2 registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFMSK2_MXTD 0x00008000 // Mask extended identifier
#define CAN_IFMSK2_MDIR 0x00004000 // Mask message direction
#define CAN_IFMSK2_MSK 0x00001FFF // Mask identifier
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1ARB1
// and CAN_IF2ARB1 registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFARB1_ID 0x0000FFFF // Identifier
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1ARB2
// and CAN_IF2ARB2 registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFARB2_MSGVAL 0x00008000 // Message valid
#define CAN_IFARB2_XTD 0x00004000 // Extended identifier
#define CAN_IFARB2_DIR 0x00002000 // Message direction
#define CAN_IFARB2_ID 0x00001FFF // Message identifier
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1MCTL
// and CAN_IF2MCTL registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFMCTL_NEWDAT 0x00008000 // New Data
#define CAN_IFMCTL_MSGLST 0x00004000 // Message lost
#define CAN_IFMCTL_INTPND 0x00002000 // Interrupt pending
#define CAN_IFMCTL_UMASK 0x00001000 // Use acceptance mask
#define CAN_IFMCTL_TXIE 0x00000800 // Transmit interrupt enable
#define CAN_IFMCTL_RXIE 0x00000400 // Receive interrupt enable
#define CAN_IFMCTL_RMTEN 0x00000200 // Remote enable
#define CAN_IFMCTL_TXRQST 0x00000100 // Transmit request
#define CAN_IFMCTL_EOB 0x00000080 // End of buffer
#define CAN_IFMCTL_DLC 0x0000000F // Data length code
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1DA1
// and CAN_IF2DA1 registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFDA1_DATA 0x0000FFFF // Data - bytes 1 and 0
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1DA2
// and CAN_IF2DA2 registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFDA2_DATA 0x0000FFFF // Data - bytes 3 and 2
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1DB1
// and CAN_IF2DB1 registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFDB1_DATA 0x0000FFFF // Data - bytes 5 and 4
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1DB2
// and CAN_IF2DB2 registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFDB2_DATA 0x0000FFFF // Data - bytes 7 and 6
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_TXRQ1
// register.
//
//*****************************************************************************
#define CAN_TXRQ1_TXRQST 0x0000FFFF // Transmission Request Bits
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_TXRQ2
// register.
//
//*****************************************************************************
#define CAN_TXRQ2_TXRQST 0x0000FFFF // Transmission Request Bits
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_NWDA1
// register.
//
//*****************************************************************************
#define CAN_NWDA1_NEWDATA 0x0000FFFF // New Data Bits
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_NWDA2
// register.
//
//*****************************************************************************
#define CAN_NWDA2_NEWDATA 0x0000FFFF // New Data Bits
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_MSGINT1
// register.
//
//*****************************************************************************
#define CAN_MSGINT1_INTPND 0x0000FFFF // Interrupt Pending Bits
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_MSGINT2
// register.
//
//*****************************************************************************
#define CAN_MSGINT2_INTPND 0x0000FFFF // Interrupt Pending Bits
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_MSGVAL1
// register.
//
//*****************************************************************************
#define CAN_MSGVAL1_MSGVAL 0x0000FFFF // Message Valid Bits
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_MSGVAL2
// register.
//
//*****************************************************************************
#define CAN_MSGVAL2_MSGVAL 0x0000FFFF // Message Valid Bits
#endif
#endif // __HW_CAN_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/hw_can.h | C | oos | 37,208 |
//*****************************************************************************
//
// hw_gpio.h - Defines and Macros for GPIO hardware.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HW_GPIO_H__
#define __HW_GPIO_H__
//*****************************************************************************
//
// The following are defines for the GPIO Register offsets.
//
//*****************************************************************************
#define GPIO_O_DATA 0x00000000 // Data register.
#define GPIO_O_DIR 0x00000400 // Data direction register.
#define GPIO_O_IS 0x00000404 // Interrupt sense register.
#define GPIO_O_IBE 0x00000408 // Interrupt both edges register.
#define GPIO_O_IEV 0x0000040C // Interrupt event register.
#define GPIO_O_IM 0x00000410 // Interrupt mask register.
#define GPIO_O_RIS 0x00000414 // Raw interrupt status register.
#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg.
#define GPIO_O_ICR 0x0000041C // Interrupt clear register.
#define GPIO_O_AFSEL 0x00000420 // Mode control select register.
#define GPIO_O_DR2R 0x00000500 // 2ma drive select register.
#define GPIO_O_DR4R 0x00000504 // 4ma drive select register.
#define GPIO_O_DR8R 0x00000508 // 8ma drive select register.
#define GPIO_O_ODR 0x0000050C // Open drain select register.
#define GPIO_O_PUR 0x00000510 // Pull up select register.
#define GPIO_O_PDR 0x00000514 // Pull down select register.
#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg.
#define GPIO_O_DEN 0x0000051C // Digital input enable register.
#define GPIO_O_LOCK 0x00000520 // Lock register.
#define GPIO_O_CR 0x00000524 // Commit register.
#define GPIO_O_AMSEL 0x00000528 // GPIO Analog Mode Select
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_LOCK register.
//
//*****************************************************************************
#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock.
#define GPIO_LOCK_UNLOCKED 0x00000000 // GPIO_CR register is unlocked
#define GPIO_LOCK_LOCKED 0x00000001 // GPIO_CR register is locked
#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register
#define GPIO_LOCK_KEY_DD 0x4C4F434B // Unlocks the GPIO_CR register on
// DustDevil-class devices and
// later.
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the GPIO Register offsets.
//
//*****************************************************************************
#define GPIO_O_PeriphID4 0x00000FD0
#define GPIO_O_PeriphID5 0x00000FD4
#define GPIO_O_PeriphID6 0x00000FD8
#define GPIO_O_PeriphID7 0x00000FDC
#define GPIO_O_PeriphID0 0x00000FE0
#define GPIO_O_PeriphID1 0x00000FE4
#define GPIO_O_PeriphID2 0x00000FE8
#define GPIO_O_PeriphID3 0x00000FEC
#define GPIO_O_PCellID0 0x00000FF0
#define GPIO_O_PCellID1 0x00000FF4
#define GPIO_O_PCellID2 0x00000FF8
#define GPIO_O_PCellID3 0x00000FFC
//*****************************************************************************
//
// The following are deprecated defines for the GPIO Register reset values.
//
//*****************************************************************************
#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV.
#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV.
#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV.
#define GPIO_RV_PCellID1 0x000000F0
#define GPIO_RV_PCellID3 0x000000B1
#define GPIO_RV_PeriphID0 0x00000061
#define GPIO_RV_PeriphID1 0x00000010
#define GPIO_RV_PCellID0 0x0000000D
#define GPIO_RV_PCellID2 0x00000005
#define GPIO_RV_PeriphID2 0x00000004
#define GPIO_RV_LOCK 0x00000001 // Lock register RV.
#define GPIO_RV_PeriphID7 0x00000000
#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV.
#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV.
#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV.
#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV.
#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV.
#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV.
#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV.
#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV.
#define GPIO_RV_PeriphID4 0x00000000
#define GPIO_RV_PeriphID5 0x00000000
#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV.
#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV.
#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV.
#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV.
#define GPIO_RV_DIR 0x00000000 // Data direction reg RV.
#define GPIO_RV_PeriphID6 0x00000000
#define GPIO_RV_PeriphID3 0x00000000
#define GPIO_RV_DATA 0x00000000 // Data register reset value.
#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV.
#endif
#endif // __HW_GPIO_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/hw_gpio.h | C | oos | 7,195 |
//*****************************************************************************
//
// timer.h - Prototypes for the timer module
//
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __TIMER_H__
#define __TIMER_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to TimerConfigure as the ulConfig parameter.
//
//*****************************************************************************
#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer
#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer
#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer
#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers
#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer
#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer
#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter
#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer
#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output
#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer
#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer
#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter
#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer
#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output
//*****************************************************************************
//
// Values that can be passed to TimerIntEnable, TimerIntDisable, and
// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.
//
//*****************************************************************************
#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt
#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt
#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt
#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask
#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt
#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt
#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt
//*****************************************************************************
//
// Values that can be passed to TimerControlEvent as the ulEvent parameter.
//
//*****************************************************************************
#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges
#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges
#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges
//*****************************************************************************
//
// Values that can be passed to most of the timer APIs as the ulTimer
// parameter.
//
//*****************************************************************************
#define TIMER_A 0x000000ff // Timer A
#define TIMER_B 0x0000ff00 // Timer B
#define TIMER_BOTH 0x0000ffff // Timer Both
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);
extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);
extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);
extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,
tBoolean bInvert);
extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,
tBoolean bEnable);
extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulEvent);
extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
tBoolean bStall);
extern void TimerRTCEnable(unsigned long ulBase);
extern void TimerRTCDisable(unsigned long ulBase);
extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerPrescaleGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);
extern unsigned long TimerValueGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerMatchGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
void (*pfnHandler)(void));
extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);
extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void TimerQuiesce(unsigned long ulBase);
#ifdef __cplusplus
}
#endif
#endif // __TIMER_H__
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/LuminaryMicro/lmi_timer.h | C | oos | 7,032 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/*
Title: LED implementation
About: Purpose
Implementation of LED-related functionalities.
*/
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include "led.h"
#include <board.h>
#include <pio/pio.h>
//------------------------------------------------------------------------------
// Internal variables
//------------------------------------------------------------------------------
#ifdef PINS_LEDS
static const Pin pinsLeds[] = {PINS_LEDS};
static const unsigned int numLeds = PIO_LISTSIZE(pinsLeds);
#endif
//------------------------------------------------------------------------------
// Exported functions
//------------------------------------------------------------------------------
/*
Function: LED_Configure
Configures the pin associated with the given LED number.
Parameters:
led - Number of the LED to configure.
Returns:
1 if the LED exists and has been configured; otherwise 0.
*/
unsigned char LED_Configure(unsigned int led)
{
#ifdef PINS_LEDS
// Check that LED exists
if (led >= numLeds) {
return 0;
}
// Configure LED
return (PIO_Configure(&pinsLeds[led], 1));
#else
return 0;
#endif
}
/*
Function: LED_Set
Turns a LED on.
Parameters:
led - Number of the LED to turn on.
Returns:
1 if the LED has been turned on; 0 otherwise.
*/
unsigned char LED_Set(unsigned int led)
{
#ifdef PINS_LEDS
// Check if LED exists
if (led >= numLeds) {
return 0;
}
// Turn LED on
if (pinsLeds[led].type == PIO_OUTPUT_0) {
PIO_Set(&pinsLeds[led]);
}
else {
PIO_Clear(&pinsLeds[led]);
}
return 1;
#else
return 0;
#endif
}
/*
Function: LED_Clear
Turns a LED off.
Parameters:
led - Number of the LED to turn off.
Returns:
1 if the LED has been turned off; 0 otherwise.
*/
unsigned char LED_Clear(unsigned int led)
{
#ifdef PINS_LEDS
// Check if LED exists
if (led >= numLeds) {
return 0;
}
// Turn LED off
if (pinsLeds[led].type == PIO_OUTPUT_0) {
PIO_Clear(&pinsLeds[led]);
}
else {
PIO_Set(&pinsLeds[led]);
}
return 1;
#else
return 0;
#endif
}
/*
Function: LED_Toggle
Toggles the current state of a LED.
Parameters:
led - Number of the LED to toggle.
Returns:
1 if the LED has been toggled; otherwise 0.
*/
unsigned char LED_Toggle(unsigned int led)
{
#ifdef PINS_LEDS
// Check if LED exists
if (led >= numLeds) {
return 0;
}
// Toggle LED
if (PIO_GetOutputDataStatus(&pinsLeds[led])) {
PIO_Clear(&pinsLeds[led]);
}
else {
PIO_Set(&pinsLeds[led]);
}
return 1;
#else
return 0;
#endif
}
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/utility/led.c | C | oos | 4,681 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/*
Title: Assert
About: Purpose
Definition of the ASSERT() macro, which is used for runtime condition
verifying.
About: Usage
1 - Use <ASSERT> in your code to check the value of function parameters,
return values, etc. *Warning:* the ASSERT condition must not have
any side-effect; otherwise, the program may not work properly
anymore when assertions are disabled.
2 - Use SANITY_CHECK to perform checks with a default error message
(outputs the file and line number where the error occured). This
reduces memory overhead caused by assertion error strings.
3 - Initialize the <DBGU> to see failed assertions at run-time.
4 - Disable assertions by defining the NOASSERT symbol at compilation
time.
*/
#ifndef ASSERT_H
#define ASSERT_H
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include <stdio.h>
//------------------------------------------------------------------------------
// Definitions
//------------------------------------------------------------------------------
/*
Macro: ASSERT
Check that the given condition is true, otherwise displays an error
message and stops the program execution.
Parameters:
condition - Condition to verify.
string - Formatted string to output if the condition fails.
... - Additional arguments depending on the formatted string.
*/
#if !defined(NOASSERT) && !defined(NOTRACE)
//char sanityError[] = "Sanity check failed at %s:%d\n\r";
#define ASSERT(condition, ...) { \
if (!(condition)) { \
printf(__VA_ARGS__); \
while (1); \
} \
}
#define SANITY_ERROR "Sanity check failed at %s:%d\n\r"
#define SANITY_CHECK(condition) ASSERT(condition, SANITY_ERROR, __FILE__, __LINE__)
#else
#define ASSERT(...)
#define SANITY_CHECK(...)
#endif
#endif //#ifndef ASSERT_H
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/utility/assert.h | C | oos | 3,746 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/*
Title: Trace
About: Purpose
Standard output methods for reporting debug information, warnings and
errors, which can be turned on/off.
About: Usage
1 - Initialize the DBGU using <trace_CONFIGURE>.
2 - Uses the <trace_LOG> macro to output traces throughout the program.
3 - Turn off all traces by defining the NOTRACE symbol during
compilation.
4 - Disable a group of trace by changing the value of <trace_LEVEL>
during compilation; traces with a level below <trace_LEVEL> are not
generated.
*/
#ifndef TRACE_H
#define TRACE_H
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#if !defined(NOTRACE)
#include <board.h>
#include <dbgu/dbgu.h>
#include <pio/pio.h>
#include <stdio.h>
#endif
//------------------------------------------------------------------------------
// Definitions
//------------------------------------------------------------------------------
/*
Constants: Trace levels
trace_FATAL - Indicates a major error which prevents the program from
going any further.
trace_ERROR - Indicates an error which may not stop the program
execution, but which indicates there is a problem with the code.
trace_WARNING - Indicates that a minor error has happened. In most case
it can be discarded safely; it may even be expected.
trace_INFO - Informational trace about the program execution. Should
enable the user to see the execution flow.
trace_DEBUG - Traces whose only purpose is for debugging the program,
and which do not produce meaningful information otherwise.
*/
#define trace_DEBUG 0
#define trace_INFO 1
#define trace_WARNING 2
#define trace_ERROR 3
#define trace_FATAL 4
/*
Constant: trace_LEVEL
Minimum level of traces that are output. By default, all traces are
output; change the value of this symbol during compilation for a more
restrictive behavior.
*/
#if !defined(trace_LEVEL)
#define trace_LEVEL 0
#endif
/*
Macro: trace_CONFIGURE
Initializes the DBGU unless the NOTRACE symbol has been defined.
Parameters:
mode - DBGU mode.
baudrate - DBGU baudrate.
mck - Master clock frequency.
*/
#if !defined(NOTRACE)
#define trace_CONFIGURE(mode, baudrate, mck) { \
const Pin pinsDbgu[] = {PINS_DBGU}; \
PIO_Configure(pinsDbgu, PIO_LISTSIZE(pinsDbgu)); \
DBGU_Configure(mode, baudrate, mck); \
}
#else
#define trace_CONFIGURE(...)
#endif
/*
Macro: trace_LOG
Outputs a formatted string using <printf> if the log level is high
enough. Can be disabled by defining the NOTRACE symbol during
compilation.
Parameters:
level - Trace level (see <Trace levels>).
format - Formatted string to output.
... - Additional parameters, depending on the formatted string.
*/
#if !defined(NOTRACE)
#define trace_LOG(level, ...) { \
if (level >= trace_LEVEL) { \
printf(__VA_ARGS__); \
} \
}
#else
#define trace_LOG(...)
#endif
#endif //#ifndef TRACE_H
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/utility/trace.h | C | oos | 5,120 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/*
Title: LED
About: Purpose
Small set of functions for simple and portable LED usage.
About: Usage
1 - Configure one or more LEDs using <LED_Configure> and
<LED_ConfigureAll>.
2 - Set, clear and toggle LEDs using <LED_Set>, <LED_Clear> and
<LED_Toggle>.
3 - Get the current status of a LED using <LED_Get>.
LEDs are numbered starting from 0; the number of LEDs depend on the
board being used. All the functions defined here will compile properly
regardless of whether the LED is defined or not; they will simply
return 0 when a LED which does not exist is given as an argument.
Also, these functions take into account how each LED is connected on to
board; thus, <LED_Set> might change the level on the corresponding pin
to 0 or 1, but it will always light the LED on; same thing for the other
methods.
*/
#ifndef LED_H
#define LED_H
//------------------------------------------------------------------------------
// Exported functions
//------------------------------------------------------------------------------
extern unsigned char LED_Configure(unsigned int led);
extern unsigned char LED_Set(unsigned int led);
extern unsigned char LED_Clear(unsigned int led);
extern unsigned char LED_Toggle(unsigned int led);
#endif //#ifndef LED_H
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/utility/led.h | C | oos | 3,001 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef BOARD_MEMORIES_H
#define BOARD_MEMORIES_H
//------------------------------------------------------------------------------
// Global functions
//------------------------------------------------------------------------------
extern void BOARD_RemapRom(void);
extern void BOARD_RemapRam(void);
extern void BOARD_ConfigureSdram(void);
extern void BOARD_ConfigureSdram48MHz(void);
extern void BOARD_ConfigureNandFlash(unsigned char busWidth);
extern void BOARD_ConfigureNandFlash48MHz(unsigned char busWidth);
extern void BOARD_ConfigureNorFlash48MHz(unsigned char busWidth);
extern void BOARD_ConfigureFlash48MHz(void);
#endif //#ifndef BOARD_MEMORIES_H
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board_memories.h | C | oos | 2,274 |
// ----------------------------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ----------------------------------------------------------------------------
// Copyright (c) 2006, Atmel Corporation
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the disclaimer below.
//
// - Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the disclaimer below in the documentation and/or
// other materials provided with the distribution.
//
// Atmel's name may not be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ----------------------------------------------------------------------------
// File Name : AT91SAM9XE256.h
// Object : AT91SAM9XE256 definitions
// Generated : AT91 SW Application Group 02/13/2008 (18:26:11)
//
// CVS Reference : /AT91SAM9XE256.pl/1.3/Wed Jan 30 13:59:12 2008//
// CVS Reference : /SYS_SAM9260.pl/1.2/Wed Feb 13 13:29:23 2008//
// CVS Reference : /HMATRIX1_SAM9260.pl/1.7/Mon Apr 23 10:39:45 2007//
// CVS Reference : /CCR_SAM9260.pl/1.2/Mon Apr 16 10:47:39 2007//
// CVS Reference : /PMC_SAM9262.pl/1.4/Mon Mar 7 18:03:13 2005//
// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//
// CVS Reference : /HSDRAMC1_6100A.pl/1.2/Mon Aug 9 10:52:25 2004//
// CVS Reference : /HSMC3_6105A.pl/1.4/Tue Nov 16 09:16:23 2004//
// CVS Reference : /AIC_6075A.pl/1.1/Mon Jul 12 17:04:01 2004//
// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005//
// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005//
// CVS Reference : /RSTC_6098A.pl/1.3/Thu Nov 4 13:57:00 2004//
// CVS Reference : /SHDWC_6122A.pl/1.3/Wed Oct 6 14:16:58 2004//
// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004//
// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004//
// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004//
// CVS Reference : /EFC2_IGS036.pl/1.2/Fri Nov 10 10:47:53 2006//
// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005//
// CVS Reference : /MCI_6101E.pl/1.1/Fri Jun 3 13:20:23 2005//
// CVS Reference : /TWI_6061B.pl/1.2/Fri Aug 4 08:53:02 2006//
// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004//
// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
// CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005//
// CVS Reference : /UDP_6ept_puon.pl/1.1/Wed Aug 30 14:20:53 2006//
// CVS Reference : /UHP_6127A.pl/1.1/Wed Feb 23 16:03:17 2005//
// CVS Reference : /EBI_SAM9260.pl/1.1/Fri Sep 30 12:12:14 2005//
// CVS Reference : /HECC_6143A.pl/1.1/Wed Feb 9 17:16:57 2005//
// CVS Reference : /ISI_xxxxx.pl/1.3/Thu Mar 3 11:11:48 2005//
// ----------------------------------------------------------------------------
#ifndef AT91SAM9XE256_H
#define AT91SAM9XE256_H
#ifndef __ASSEMBLY__
typedef volatile unsigned int AT91_REG;// Hardware register definition
#define AT91_CAST(a) (a)
#else
#define AT91_CAST(a)
#endif
// *****************************************************************************
// SOFTWARE API DEFINITION FOR System Peripherals
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_SYS {
AT91_REG Reserved0[2560]; //
AT91_REG ECC_CR; // ECC reset register
AT91_REG ECC_MR; // ECC Page size register
AT91_REG ECC_SR; // ECC Status register
AT91_REG ECC_PR; // ECC Parity register
AT91_REG ECC_NPR; // ECC Parity N register
AT91_REG Reserved1[58]; //
AT91_REG ECC_VR; // ECC Version register
AT91_REG Reserved2[64]; //
AT91_REG SDRAMC_MR; // SDRAM Controller Mode Register
AT91_REG SDRAMC_TR; // SDRAM Controller Refresh Timer Register
AT91_REG SDRAMC_CR; // SDRAM Controller Configuration Register
AT91_REG SDRAMC_HSR; // SDRAM Controller High Speed Register
AT91_REG SDRAMC_LPR; // SDRAM Controller Low Power Register
AT91_REG SDRAMC_IER; // SDRAM Controller Interrupt Enable Register
AT91_REG SDRAMC_IDR; // SDRAM Controller Interrupt Disable Register
AT91_REG SDRAMC_IMR; // SDRAM Controller Interrupt Mask Register
AT91_REG SDRAMC_ISR; // SDRAM Controller Interrupt Mask Register
AT91_REG SDRAMC_MDR; // SDRAM Memory Device Register
AT91_REG Reserved3[118]; //
AT91_REG SMC_SETUP0; // Setup Register for CS 0
AT91_REG SMC_PULSE0; // Pulse Register for CS 0
AT91_REG SMC_CYCLE0; // Cycle Register for CS 0
AT91_REG SMC_CTRL0; // Control Register for CS 0
AT91_REG SMC_SETUP1; // Setup Register for CS 1
AT91_REG SMC_PULSE1; // Pulse Register for CS 1
AT91_REG SMC_CYCLE1; // Cycle Register for CS 1
AT91_REG SMC_CTRL1; // Control Register for CS 1
AT91_REG SMC_SETUP2; // Setup Register for CS 2
AT91_REG SMC_PULSE2; // Pulse Register for CS 2
AT91_REG SMC_CYCLE2; // Cycle Register for CS 2
AT91_REG SMC_CTRL2; // Control Register for CS 2
AT91_REG SMC_SETUP3; // Setup Register for CS 3
AT91_REG SMC_PULSE3; // Pulse Register for CS 3
AT91_REG SMC_CYCLE3; // Cycle Register for CS 3
AT91_REG SMC_CTRL3; // Control Register for CS 3
AT91_REG SMC_SETUP4; // Setup Register for CS 4
AT91_REG SMC_PULSE4; // Pulse Register for CS 4
AT91_REG SMC_CYCLE4; // Cycle Register for CS 4
AT91_REG SMC_CTRL4; // Control Register for CS 4
AT91_REG SMC_SETUP5; // Setup Register for CS 5
AT91_REG SMC_PULSE5; // Pulse Register for CS 5
AT91_REG SMC_CYCLE5; // Cycle Register for CS 5
AT91_REG SMC_CTRL5; // Control Register for CS 5
AT91_REG SMC_SETUP6; // Setup Register for CS 6
AT91_REG SMC_PULSE6; // Pulse Register for CS 6
AT91_REG SMC_CYCLE6; // Cycle Register for CS 6
AT91_REG SMC_CTRL6; // Control Register for CS 6
AT91_REG SMC_SETUP7; // Setup Register for CS 7
AT91_REG SMC_PULSE7; // Pulse Register for CS 7
AT91_REG SMC_CYCLE7; // Cycle Register for CS 7
AT91_REG SMC_CTRL7; // Control Register for CS 7
AT91_REG Reserved4[96]; //
AT91_REG MATRIX_MCFG0; // Master Configuration Register 0 (ram96k)
AT91_REG MATRIX_MCFG1; // Master Configuration Register 1 (rom)
AT91_REG MATRIX_MCFG2; // Master Configuration Register 2 (hperiphs)
AT91_REG MATRIX_MCFG3; // Master Configuration Register 3 (ebi)
AT91_REG MATRIX_MCFG4; // Master Configuration Register 4 (bridge)
AT91_REG MATRIX_MCFG5; // Master Configuration Register 5 (mailbox)
AT91_REG MATRIX_MCFG6; // Master Configuration Register 6 (ram16k)
AT91_REG MATRIX_MCFG7; // Master Configuration Register 7 (teak_prog)
AT91_REG Reserved5[8]; //
AT91_REG MATRIX_SCFG0; // Slave Configuration Register 0 (ram96k)
AT91_REG MATRIX_SCFG1; // Slave Configuration Register 1 (rom)
AT91_REG MATRIX_SCFG2; // Slave Configuration Register 2 (hperiphs)
AT91_REG MATRIX_SCFG3; // Slave Configuration Register 3 (ebi)
AT91_REG MATRIX_SCFG4; // Slave Configuration Register 4 (bridge)
AT91_REG Reserved6[11]; //
AT91_REG MATRIX_PRAS0; // PRAS0 (ram0)
AT91_REG MATRIX_PRBS0; // PRBS0 (ram0)
AT91_REG MATRIX_PRAS1; // PRAS1 (ram1)
AT91_REG MATRIX_PRBS1; // PRBS1 (ram1)
AT91_REG MATRIX_PRAS2; // PRAS2 (ram2)
AT91_REG MATRIX_PRBS2; // PRBS2 (ram2)
AT91_REG MATRIX_PRAS3; // PRAS3 : usb_dev_hs
AT91_REG MATRIX_PRBS3; // PRBS3 : usb_dev_hs
AT91_REG MATRIX_PRAS4; // PRAS4 : ebi
AT91_REG MATRIX_PRBS4; // PRBS4 : ebi
AT91_REG Reserved7[22]; //
AT91_REG MATRIX_MRCR; // Master Remp Control Register
AT91_REG Reserved8[6]; //
AT91_REG CCFG_EBICSA; // EBI Chip Select Assignement Register
AT91_REG Reserved9[3]; //
AT91_REG MATRIX_TEAKCFG; // Slave 7 (teak_prog) Special Function Register
AT91_REG Reserved10[51]; //
AT91_REG CCFG_MATRIXVERSION; // Version Register
AT91_REG AIC_SMR[32]; // Source Mode Register
AT91_REG AIC_SVR[32]; // Source Vector Register
AT91_REG AIC_IVR; // IRQ Vector Register
AT91_REG AIC_FVR; // FIQ Vector Register
AT91_REG AIC_ISR; // Interrupt Status Register
AT91_REG AIC_IPR; // Interrupt Pending Register
AT91_REG AIC_IMR; // Interrupt Mask Register
AT91_REG AIC_CISR; // Core Interrupt Status Register
AT91_REG Reserved11[2]; //
AT91_REG AIC_IECR; // Interrupt Enable Command Register
AT91_REG AIC_IDCR; // Interrupt Disable Command Register
AT91_REG AIC_ICCR; // Interrupt Clear Command Register
AT91_REG AIC_ISCR; // Interrupt Set Command Register
AT91_REG AIC_EOICR; // End of Interrupt Command Register
AT91_REG AIC_SPU; // Spurious Vector Register
AT91_REG AIC_DCR; // Debug Control Register (Protect)
AT91_REG Reserved12[1]; //
AT91_REG AIC_FFER; // Fast Forcing Enable Register
AT91_REG AIC_FFDR; // Fast Forcing Disable Register
AT91_REG AIC_FFSR; // Fast Forcing Status Register
AT91_REG Reserved13[45]; //
AT91_REG DBGU_CR; // Control Register
AT91_REG DBGU_MR; // Mode Register
AT91_REG DBGU_IER; // Interrupt Enable Register
AT91_REG DBGU_IDR; // Interrupt Disable Register
AT91_REG DBGU_IMR; // Interrupt Mask Register
AT91_REG DBGU_CSR; // Channel Status Register
AT91_REG DBGU_RHR; // Receiver Holding Register
AT91_REG DBGU_THR; // Transmitter Holding Register
AT91_REG DBGU_BRGR; // Baud Rate Generator Register
AT91_REG Reserved14[7]; //
AT91_REG DBGU_CIDR; // Chip ID Register
AT91_REG DBGU_EXID; // Chip ID Extension Register
AT91_REG DBGU_FNTR; // Force NTRST Register
AT91_REG Reserved15[45]; //
AT91_REG DBGU_RPR; // Receive Pointer Register
AT91_REG DBGU_RCR; // Receive Counter Register
AT91_REG DBGU_TPR; // Transmit Pointer Register
AT91_REG DBGU_TCR; // Transmit Counter Register
AT91_REG DBGU_RNPR; // Receive Next Pointer Register
AT91_REG DBGU_RNCR; // Receive Next Counter Register
AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
AT91_REG DBGU_TNCR; // Transmit Next Counter Register
AT91_REG DBGU_PTCR; // PDC Transfer Control Register
AT91_REG DBGU_PTSR; // PDC Transfer Status Register
AT91_REG Reserved16[54]; //
AT91_REG PIOA_PER; // PIO Enable Register
AT91_REG PIOA_PDR; // PIO Disable Register
AT91_REG PIOA_PSR; // PIO Status Register
AT91_REG Reserved17[1]; //
AT91_REG PIOA_OER; // Output Enable Register
AT91_REG PIOA_ODR; // Output Disable Registerr
AT91_REG PIOA_OSR; // Output Status Register
AT91_REG Reserved18[1]; //
AT91_REG PIOA_IFER; // Input Filter Enable Register
AT91_REG PIOA_IFDR; // Input Filter Disable Register
AT91_REG PIOA_IFSR; // Input Filter Status Register
AT91_REG Reserved19[1]; //
AT91_REG PIOA_SODR; // Set Output Data Register
AT91_REG PIOA_CODR; // Clear Output Data Register
AT91_REG PIOA_ODSR; // Output Data Status Register
AT91_REG PIOA_PDSR; // Pin Data Status Register
AT91_REG PIOA_IER; // Interrupt Enable Register
AT91_REG PIOA_IDR; // Interrupt Disable Register
AT91_REG PIOA_IMR; // Interrupt Mask Register
AT91_REG PIOA_ISR; // Interrupt Status Register
AT91_REG PIOA_MDER; // Multi-driver Enable Register
AT91_REG PIOA_MDDR; // Multi-driver Disable Register
AT91_REG PIOA_MDSR; // Multi-driver Status Register
AT91_REG Reserved20[1]; //
AT91_REG PIOA_PPUDR; // Pull-up Disable Register
AT91_REG PIOA_PPUER; // Pull-up Enable Register
AT91_REG PIOA_PPUSR; // Pull-up Status Register
AT91_REG Reserved21[1]; //
AT91_REG PIOA_ASR; // Select A Register
AT91_REG PIOA_BSR; // Select B Register
AT91_REG PIOA_ABSR; // AB Select Status Register
AT91_REG Reserved22[9]; //
AT91_REG PIOA_OWER; // Output Write Enable Register
AT91_REG PIOA_OWDR; // Output Write Disable Register
AT91_REG PIOA_OWSR; // Output Write Status Register
AT91_REG Reserved23[213]; //
AT91_REG PIOB_PER; // PIO Enable Register
AT91_REG PIOB_PDR; // PIO Disable Register
AT91_REG PIOB_PSR; // PIO Status Register
AT91_REG Reserved24[1]; //
AT91_REG PIOB_OER; // Output Enable Register
AT91_REG PIOB_ODR; // Output Disable Registerr
AT91_REG PIOB_OSR; // Output Status Register
AT91_REG Reserved25[1]; //
AT91_REG PIOB_IFER; // Input Filter Enable Register
AT91_REG PIOB_IFDR; // Input Filter Disable Register
AT91_REG PIOB_IFSR; // Input Filter Status Register
AT91_REG Reserved26[1]; //
AT91_REG PIOB_SODR; // Set Output Data Register
AT91_REG PIOB_CODR; // Clear Output Data Register
AT91_REG PIOB_ODSR; // Output Data Status Register
AT91_REG PIOB_PDSR; // Pin Data Status Register
AT91_REG PIOB_IER; // Interrupt Enable Register
AT91_REG PIOB_IDR; // Interrupt Disable Register
AT91_REG PIOB_IMR; // Interrupt Mask Register
AT91_REG PIOB_ISR; // Interrupt Status Register
AT91_REG PIOB_MDER; // Multi-driver Enable Register
AT91_REG PIOB_MDDR; // Multi-driver Disable Register
AT91_REG PIOB_MDSR; // Multi-driver Status Register
AT91_REG Reserved27[1]; //
AT91_REG PIOB_PPUDR; // Pull-up Disable Register
AT91_REG PIOB_PPUER; // Pull-up Enable Register
AT91_REG PIOB_PPUSR; // Pull-up Status Register
AT91_REG Reserved28[1]; //
AT91_REG PIOB_ASR; // Select A Register
AT91_REG PIOB_BSR; // Select B Register
AT91_REG PIOB_ABSR; // AB Select Status Register
AT91_REG Reserved29[9]; //
AT91_REG PIOB_OWER; // Output Write Enable Register
AT91_REG PIOB_OWDR; // Output Write Disable Register
AT91_REG PIOB_OWSR; // Output Write Status Register
AT91_REG Reserved30[85]; //
AT91_REG PIOC_PER; // PIO Enable Register
AT91_REG PIOC_PDR; // PIO Disable Register
AT91_REG PIOC_PSR; // PIO Status Register
AT91_REG Reserved31[1]; //
AT91_REG PIOC_OER; // Output Enable Register
AT91_REG PIOC_ODR; // Output Disable Registerr
AT91_REG PIOC_OSR; // Output Status Register
AT91_REG Reserved32[1]; //
AT91_REG PIOC_IFER; // Input Filter Enable Register
AT91_REG PIOC_IFDR; // Input Filter Disable Register
AT91_REG PIOC_IFSR; // Input Filter Status Register
AT91_REG Reserved33[1]; //
AT91_REG PIOC_SODR; // Set Output Data Register
AT91_REG PIOC_CODR; // Clear Output Data Register
AT91_REG PIOC_ODSR; // Output Data Status Register
AT91_REG PIOC_PDSR; // Pin Data Status Register
AT91_REG PIOC_IER; // Interrupt Enable Register
AT91_REG PIOC_IDR; // Interrupt Disable Register
AT91_REG PIOC_IMR; // Interrupt Mask Register
AT91_REG PIOC_ISR; // Interrupt Status Register
AT91_REG PIOC_MDER; // Multi-driver Enable Register
AT91_REG PIOC_MDDR; // Multi-driver Disable Register
AT91_REG PIOC_MDSR; // Multi-driver Status Register
AT91_REG Reserved34[1]; //
AT91_REG PIOC_PPUDR; // Pull-up Disable Register
AT91_REG PIOC_PPUER; // Pull-up Enable Register
AT91_REG PIOC_PPUSR; // Pull-up Status Register
AT91_REG Reserved35[1]; //
AT91_REG PIOC_ASR; // Select A Register
AT91_REG PIOC_BSR; // Select B Register
AT91_REG PIOC_ABSR; // AB Select Status Register
AT91_REG Reserved36[9]; //
AT91_REG PIOC_OWER; // Output Write Enable Register
AT91_REG PIOC_OWDR; // Output Write Disable Register
AT91_REG PIOC_OWSR; // Output Write Status Register
AT91_REG Reserved37[85]; //
AT91_REG PMC_SCER; // System Clock Enable Register
AT91_REG PMC_SCDR; // System Clock Disable Register
AT91_REG PMC_SCSR; // System Clock Status Register
AT91_REG Reserved38[1]; //
AT91_REG PMC_PCER; // Peripheral Clock Enable Register
AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
AT91_REG PMC_PCSR; // Peripheral Clock Status Register
AT91_REG Reserved39[1]; //
AT91_REG PMC_MOR; // Main Oscillator Register
AT91_REG PMC_MCFR; // Main Clock Frequency Register
AT91_REG PMC_PLLAR; // PLL A Register
AT91_REG PMC_PLLBR; // PLL B Register
AT91_REG PMC_MCKR; // Master Clock Register
AT91_REG Reserved40[3]; //
AT91_REG PMC_PCKR[8]; // Programmable Clock Register
AT91_REG PMC_IER; // Interrupt Enable Register
AT91_REG PMC_IDR; // Interrupt Disable Register
AT91_REG PMC_SR; // Status Register
AT91_REG PMC_IMR; // Interrupt Mask Register
AT91_REG Reserved41[36]; //
AT91_REG RSTC_RCR; // Reset Control Register
AT91_REG RSTC_RSR; // Reset Status Register
AT91_REG RSTC_RMR; // Reset Mode Register
AT91_REG Reserved42[1]; //
AT91_REG SHDWC_SHCR; // Shut Down Control Register
AT91_REG SHDWC_SHMR; // Shut Down Mode Register
AT91_REG SHDWC_SHSR; // Shut Down Status Register
AT91_REG Reserved43[1]; //
AT91_REG RTTC_RTMR; // Real-time Mode Register
AT91_REG RTTC_RTAR; // Real-time Alarm Register
AT91_REG RTTC_RTVR; // Real-time Value Register
AT91_REG RTTC_RTSR; // Real-time Status Register
AT91_REG PITC_PIMR; // Period Interval Mode Register
AT91_REG PITC_PISR; // Period Interval Status Register
AT91_REG PITC_PIVR; // Period Interval Value Register
AT91_REG PITC_PIIR; // Period Interval Image Register
AT91_REG WDTC_WDCR; // Watchdog Control Register
AT91_REG WDTC_WDMR; // Watchdog Mode Register
AT91_REG WDTC_WDSR; // Watchdog Status Register
AT91_REG Reserved44[1]; //
AT91_REG SYS_GPBR[4]; // General Purpose Register
} AT91S_SYS, *AT91PS_SYS;
#else
#define SYS_GPBR (AT91_CAST(AT91_REG *) 0x00003D50) // (SYS_GPBR) General Purpose Register
#endif
// -------- GPBR : (SYS Offset: 0x3d50) GPBR General Purpose Register --------
#define AT91C_GPBR_GPRV (0x0 << 0) // (SYS) General Purpose Register Value
// *****************************************************************************
// SOFTWARE API DEFINITION FOR External Bus Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_EBI {
AT91_REG EBI_DUMMY; // Dummy register - Do not use
} AT91S_EBI, *AT91PS_EBI;
#else
#define EBI_DUMMY (AT91_CAST(AT91_REG *) 0x00000000) // (EBI_DUMMY) Dummy register - Do not use
#endif
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Error Correction Code controller
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_ECC {
AT91_REG ECC_CR; // ECC reset register
AT91_REG ECC_MR; // ECC Page size register
AT91_REG ECC_SR; // ECC Status register
AT91_REG ECC_PR; // ECC Parity register
AT91_REG ECC_NPR; // ECC Parity N register
AT91_REG Reserved0[58]; //
AT91_REG ECC_VR; // ECC Version register
} AT91S_ECC, *AT91PS_ECC;
#else
#define ECC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ECC_CR) ECC reset register
#define ECC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ECC_MR) ECC Page size register
#define ECC_SR (AT91_CAST(AT91_REG *) 0x00000008) // (ECC_SR) ECC Status register
#define ECC_PR (AT91_CAST(AT91_REG *) 0x0000000C) // (ECC_PR) ECC Parity register
#define ECC_NPR (AT91_CAST(AT91_REG *) 0x00000010) // (ECC_NPR) ECC Parity N register
#define ECC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (ECC_VR) ECC Version register
#endif
// -------- ECC_CR : (ECC Offset: 0x0) ECC reset register --------
#define AT91C_ECC_RST (0x1 << 0) // (ECC) ECC reset parity
// -------- ECC_MR : (ECC Offset: 0x4) ECC page size register --------
#define AT91C_ECC_PAGE_SIZE (0x3 << 0) // (ECC) Nand Flash page size
// -------- ECC_SR : (ECC Offset: 0x8) ECC status register --------
#define AT91C_ECC_RECERR (0x1 << 0) // (ECC) ECC error
#define AT91C_ECC_ECCERR (0x1 << 1) // (ECC) ECC single error
#define AT91C_ECC_MULERR (0x1 << 2) // (ECC) ECC_MULERR
// -------- ECC_PR : (ECC Offset: 0xc) ECC parity register --------
#define AT91C_ECC_BITADDR (0xF << 0) // (ECC) Bit address error
#define AT91C_ECC_WORDADDR (0xFFF << 4) // (ECC) address of the failing bit
// -------- ECC_NPR : (ECC Offset: 0x10) ECC N parity register --------
#define AT91C_ECC_NPARITY (0xFFFF << 0) // (ECC) ECC parity N
// -------- ECC_VR : (ECC Offset: 0xfc) ECC version register --------
#define AT91C_ECC_VR (0xF << 0) // (ECC) ECC version register
// *****************************************************************************
// SOFTWARE API DEFINITION FOR SDRAM Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_SDRAMC {
AT91_REG SDRAMC_MR; // SDRAM Controller Mode Register
AT91_REG SDRAMC_TR; // SDRAM Controller Refresh Timer Register
AT91_REG SDRAMC_CR; // SDRAM Controller Configuration Register
AT91_REG SDRAMC_HSR; // SDRAM Controller High Speed Register
AT91_REG SDRAMC_LPR; // SDRAM Controller Low Power Register
AT91_REG SDRAMC_IER; // SDRAM Controller Interrupt Enable Register
AT91_REG SDRAMC_IDR; // SDRAM Controller Interrupt Disable Register
AT91_REG SDRAMC_IMR; // SDRAM Controller Interrupt Mask Register
AT91_REG SDRAMC_ISR; // SDRAM Controller Interrupt Mask Register
AT91_REG SDRAMC_MDR; // SDRAM Memory Device Register
} AT91S_SDRAMC, *AT91PS_SDRAMC;
#else
#define SDRAMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (SDRAMC_MR) SDRAM Controller Mode Register
#define SDRAMC_TR (AT91_CAST(AT91_REG *) 0x00000004) // (SDRAMC_TR) SDRAM Controller Refresh Timer Register
#define SDRAMC_CR (AT91_CAST(AT91_REG *) 0x00000008) // (SDRAMC_CR) SDRAM Controller Configuration Register
#define SDRAMC_HSR (AT91_CAST(AT91_REG *) 0x0000000C) // (SDRAMC_HSR) SDRAM Controller High Speed Register
#define SDRAMC_LPR (AT91_CAST(AT91_REG *) 0x00000010) // (SDRAMC_LPR) SDRAM Controller Low Power Register
#define SDRAMC_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SDRAMC_IER) SDRAM Controller Interrupt Enable Register
#define SDRAMC_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SDRAMC_IDR) SDRAM Controller Interrupt Disable Register
#define SDRAMC_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SDRAMC_IMR) SDRAM Controller Interrupt Mask Register
#define SDRAMC_ISR (AT91_CAST(AT91_REG *) 0x00000020) // (SDRAMC_ISR) SDRAM Controller Interrupt Mask Register
#define SDRAMC_MDR (AT91_CAST(AT91_REG *) 0x00000024) // (SDRAMC_MDR) SDRAM Memory Device Register
#endif
// -------- SDRAMC_MR : (SDRAMC Offset: 0x0) SDRAM Controller Mode Register --------
#define AT91C_SDRAMC_MODE (0xF << 0) // (SDRAMC) Mode
#define AT91C_SDRAMC_MODE_NORMAL_CMD (0x0) // (SDRAMC) Normal Mode
#define AT91C_SDRAMC_MODE_NOP_CMD (0x1) // (SDRAMC) Issue a NOP Command at every access
#define AT91C_SDRAMC_MODE_PRCGALL_CMD (0x2) // (SDRAMC) Issue a All Banks Precharge Command at every access
#define AT91C_SDRAMC_MODE_LMR_CMD (0x3) // (SDRAMC) Issue a Load Mode Register at every access
#define AT91C_SDRAMC_MODE_RFSH_CMD (0x4) // (SDRAMC) Issue a Refresh
#define AT91C_SDRAMC_MODE_EXT_LMR_CMD (0x5) // (SDRAMC) Issue an Extended Load Mode Register
#define AT91C_SDRAMC_MODE_DEEP_CMD (0x6) // (SDRAMC) Enter Deep Power Mode
// -------- SDRAMC_TR : (SDRAMC Offset: 0x4) SDRAMC Refresh Timer Register --------
#define AT91C_SDRAMC_COUNT (0xFFF << 0) // (SDRAMC) Refresh Counter
// -------- SDRAMC_CR : (SDRAMC Offset: 0x8) SDRAM Configuration Register --------
#define AT91C_SDRAMC_NC (0x3 << 0) // (SDRAMC) Number of Column Bits
#define AT91C_SDRAMC_NC_8 (0x0) // (SDRAMC) 8 Bits
#define AT91C_SDRAMC_NC_9 (0x1) // (SDRAMC) 9 Bits
#define AT91C_SDRAMC_NC_10 (0x2) // (SDRAMC) 10 Bits
#define AT91C_SDRAMC_NC_11 (0x3) // (SDRAMC) 11 Bits
#define AT91C_SDRAMC_NR (0x3 << 2) // (SDRAMC) Number of Row Bits
#define AT91C_SDRAMC_NR_11 (0x0 << 2) // (SDRAMC) 11 Bits
#define AT91C_SDRAMC_NR_12 (0x1 << 2) // (SDRAMC) 12 Bits
#define AT91C_SDRAMC_NR_13 (0x2 << 2) // (SDRAMC) 13 Bits
#define AT91C_SDRAMC_NB (0x1 << 4) // (SDRAMC) Number of Banks
#define AT91C_SDRAMC_NB_2_BANKS (0x0 << 4) // (SDRAMC) 2 banks
#define AT91C_SDRAMC_NB_4_BANKS (0x1 << 4) // (SDRAMC) 4 banks
#define AT91C_SDRAMC_CAS (0x3 << 5) // (SDRAMC) CAS Latency
#define AT91C_SDRAMC_CAS_2 (0x2 << 5) // (SDRAMC) 2 cycles
#define AT91C_SDRAMC_CAS_3 (0x3 << 5) // (SDRAMC) 3 cycles
#define AT91C_SDRAMC_DBW (0x1 << 7) // (SDRAMC) Data Bus Width
#define AT91C_SDRAMC_DBW_32_BITS (0x0 << 7) // (SDRAMC) 32 Bits datas bus
#define AT91C_SDRAMC_DBW_16_BITS (0x1 << 7) // (SDRAMC) 16 Bits datas bus
#define AT91C_SDRAMC_TWR (0xF << 8) // (SDRAMC) Number of Write Recovery Time Cycles
#define AT91C_SDRAMC_TWR_0 (0x0 << 8) // (SDRAMC) Value : 0
#define AT91C_SDRAMC_TWR_1 (0x1 << 8) // (SDRAMC) Value : 1
#define AT91C_SDRAMC_TWR_2 (0x2 << 8) // (SDRAMC) Value : 2
#define AT91C_SDRAMC_TWR_3 (0x3 << 8) // (SDRAMC) Value : 3
#define AT91C_SDRAMC_TWR_4 (0x4 << 8) // (SDRAMC) Value : 4
#define AT91C_SDRAMC_TWR_5 (0x5 << 8) // (SDRAMC) Value : 5
#define AT91C_SDRAMC_TWR_6 (0x6 << 8) // (SDRAMC) Value : 6
#define AT91C_SDRAMC_TWR_7 (0x7 << 8) // (SDRAMC) Value : 7
#define AT91C_SDRAMC_TWR_8 (0x8 << 8) // (SDRAMC) Value : 8
#define AT91C_SDRAMC_TWR_9 (0x9 << 8) // (SDRAMC) Value : 9
#define AT91C_SDRAMC_TWR_10 (0xA << 8) // (SDRAMC) Value : 10
#define AT91C_SDRAMC_TWR_11 (0xB << 8) // (SDRAMC) Value : 11
#define AT91C_SDRAMC_TWR_12 (0xC << 8) // (SDRAMC) Value : 12
#define AT91C_SDRAMC_TWR_13 (0xD << 8) // (SDRAMC) Value : 13
#define AT91C_SDRAMC_TWR_14 (0xE << 8) // (SDRAMC) Value : 14
#define AT91C_SDRAMC_TWR_15 (0xF << 8) // (SDRAMC) Value : 15
#define AT91C_SDRAMC_TRC (0xF << 12) // (SDRAMC) Number of RAS Cycle Time Cycles
#define AT91C_SDRAMC_TRC_0 (0x0 << 12) // (SDRAMC) Value : 0
#define AT91C_SDRAMC_TRC_1 (0x1 << 12) // (SDRAMC) Value : 1
#define AT91C_SDRAMC_TRC_2 (0x2 << 12) // (SDRAMC) Value : 2
#define AT91C_SDRAMC_TRC_3 (0x3 << 12) // (SDRAMC) Value : 3
#define AT91C_SDRAMC_TRC_4 (0x4 << 12) // (SDRAMC) Value : 4
#define AT91C_SDRAMC_TRC_5 (0x5 << 12) // (SDRAMC) Value : 5
#define AT91C_SDRAMC_TRC_6 (0x6 << 12) // (SDRAMC) Value : 6
#define AT91C_SDRAMC_TRC_7 (0x7 << 12) // (SDRAMC) Value : 7
#define AT91C_SDRAMC_TRC_8 (0x8 << 12) // (SDRAMC) Value : 8
#define AT91C_SDRAMC_TRC_9 (0x9 << 12) // (SDRAMC) Value : 9
#define AT91C_SDRAMC_TRC_10 (0xA << 12) // (SDRAMC) Value : 10
#define AT91C_SDRAMC_TRC_11 (0xB << 12) // (SDRAMC) Value : 11
#define AT91C_SDRAMC_TRC_12 (0xC << 12) // (SDRAMC) Value : 12
#define AT91C_SDRAMC_TRC_13 (0xD << 12) // (SDRAMC) Value : 13
#define AT91C_SDRAMC_TRC_14 (0xE << 12) // (SDRAMC) Value : 14
#define AT91C_SDRAMC_TRC_15 (0xF << 12) // (SDRAMC) Value : 15
#define AT91C_SDRAMC_TRP (0xF << 16) // (SDRAMC) Number of RAS Precharge Time Cycles
#define AT91C_SDRAMC_TRP_0 (0x0 << 16) // (SDRAMC) Value : 0
#define AT91C_SDRAMC_TRP_1 (0x1 << 16) // (SDRAMC) Value : 1
#define AT91C_SDRAMC_TRP_2 (0x2 << 16) // (SDRAMC) Value : 2
#define AT91C_SDRAMC_TRP_3 (0x3 << 16) // (SDRAMC) Value : 3
#define AT91C_SDRAMC_TRP_4 (0x4 << 16) // (SDRAMC) Value : 4
#define AT91C_SDRAMC_TRP_5 (0x5 << 16) // (SDRAMC) Value : 5
#define AT91C_SDRAMC_TRP_6 (0x6 << 16) // (SDRAMC) Value : 6
#define AT91C_SDRAMC_TRP_7 (0x7 << 16) // (SDRAMC) Value : 7
#define AT91C_SDRAMC_TRP_8 (0x8 << 16) // (SDRAMC) Value : 8
#define AT91C_SDRAMC_TRP_9 (0x9 << 16) // (SDRAMC) Value : 9
#define AT91C_SDRAMC_TRP_10 (0xA << 16) // (SDRAMC) Value : 10
#define AT91C_SDRAMC_TRP_11 (0xB << 16) // (SDRAMC) Value : 11
#define AT91C_SDRAMC_TRP_12 (0xC << 16) // (SDRAMC) Value : 12
#define AT91C_SDRAMC_TRP_13 (0xD << 16) // (SDRAMC) Value : 13
#define AT91C_SDRAMC_TRP_14 (0xE << 16) // (SDRAMC) Value : 14
#define AT91C_SDRAMC_TRP_15 (0xF << 16) // (SDRAMC) Value : 15
#define AT91C_SDRAMC_TRCD (0xF << 20) // (SDRAMC) Number of RAS to CAS Delay Cycles
#define AT91C_SDRAMC_TRCD_0 (0x0 << 20) // (SDRAMC) Value : 0
#define AT91C_SDRAMC_TRCD_1 (0x1 << 20) // (SDRAMC) Value : 1
#define AT91C_SDRAMC_TRCD_2 (0x2 << 20) // (SDRAMC) Value : 2
#define AT91C_SDRAMC_TRCD_3 (0x3 << 20) // (SDRAMC) Value : 3
#define AT91C_SDRAMC_TRCD_4 (0x4 << 20) // (SDRAMC) Value : 4
#define AT91C_SDRAMC_TRCD_5 (0x5 << 20) // (SDRAMC) Value : 5
#define AT91C_SDRAMC_TRCD_6 (0x6 << 20) // (SDRAMC) Value : 6
#define AT91C_SDRAMC_TRCD_7 (0x7 << 20) // (SDRAMC) Value : 7
#define AT91C_SDRAMC_TRCD_8 (0x8 << 20) // (SDRAMC) Value : 8
#define AT91C_SDRAMC_TRCD_9 (0x9 << 20) // (SDRAMC) Value : 9
#define AT91C_SDRAMC_TRCD_10 (0xA << 20) // (SDRAMC) Value : 10
#define AT91C_SDRAMC_TRCD_11 (0xB << 20) // (SDRAMC) Value : 11
#define AT91C_SDRAMC_TRCD_12 (0xC << 20) // (SDRAMC) Value : 12
#define AT91C_SDRAMC_TRCD_13 (0xD << 20) // (SDRAMC) Value : 13
#define AT91C_SDRAMC_TRCD_14 (0xE << 20) // (SDRAMC) Value : 14
#define AT91C_SDRAMC_TRCD_15 (0xF << 20) // (SDRAMC) Value : 15
#define AT91C_SDRAMC_TRAS (0xF << 24) // (SDRAMC) Number of RAS Active Time Cycles
#define AT91C_SDRAMC_TRAS_0 (0x0 << 24) // (SDRAMC) Value : 0
#define AT91C_SDRAMC_TRAS_1 (0x1 << 24) // (SDRAMC) Value : 1
#define AT91C_SDRAMC_TRAS_2 (0x2 << 24) // (SDRAMC) Value : 2
#define AT91C_SDRAMC_TRAS_3 (0x3 << 24) // (SDRAMC) Value : 3
#define AT91C_SDRAMC_TRAS_4 (0x4 << 24) // (SDRAMC) Value : 4
#define AT91C_SDRAMC_TRAS_5 (0x5 << 24) // (SDRAMC) Value : 5
#define AT91C_SDRAMC_TRAS_6 (0x6 << 24) // (SDRAMC) Value : 6
#define AT91C_SDRAMC_TRAS_7 (0x7 << 24) // (SDRAMC) Value : 7
#define AT91C_SDRAMC_TRAS_8 (0x8 << 24) // (SDRAMC) Value : 8
#define AT91C_SDRAMC_TRAS_9 (0x9 << 24) // (SDRAMC) Value : 9
#define AT91C_SDRAMC_TRAS_10 (0xA << 24) // (SDRAMC) Value : 10
#define AT91C_SDRAMC_TRAS_11 (0xB << 24) // (SDRAMC) Value : 11
#define AT91C_SDRAMC_TRAS_12 (0xC << 24) // (SDRAMC) Value : 12
#define AT91C_SDRAMC_TRAS_13 (0xD << 24) // (SDRAMC) Value : 13
#define AT91C_SDRAMC_TRAS_14 (0xE << 24) // (SDRAMC) Value : 14
#define AT91C_SDRAMC_TRAS_15 (0xF << 24) // (SDRAMC) Value : 15
#define AT91C_SDRAMC_TXSR (0xF << 28) // (SDRAMC) Number of Command Recovery Time Cycles
#define AT91C_SDRAMC_TXSR_0 (0x0 << 28) // (SDRAMC) Value : 0
#define AT91C_SDRAMC_TXSR_1 (0x1 << 28) // (SDRAMC) Value : 1
#define AT91C_SDRAMC_TXSR_2 (0x2 << 28) // (SDRAMC) Value : 2
#define AT91C_SDRAMC_TXSR_3 (0x3 << 28) // (SDRAMC) Value : 3
#define AT91C_SDRAMC_TXSR_4 (0x4 << 28) // (SDRAMC) Value : 4
#define AT91C_SDRAMC_TXSR_5 (0x5 << 28) // (SDRAMC) Value : 5
#define AT91C_SDRAMC_TXSR_6 (0x6 << 28) // (SDRAMC) Value : 6
#define AT91C_SDRAMC_TXSR_7 (0x7 << 28) // (SDRAMC) Value : 7
#define AT91C_SDRAMC_TXSR_8 (0x8 << 28) // (SDRAMC) Value : 8
#define AT91C_SDRAMC_TXSR_9 (0x9 << 28) // (SDRAMC) Value : 9
#define AT91C_SDRAMC_TXSR_10 (0xA << 28) // (SDRAMC) Value : 10
#define AT91C_SDRAMC_TXSR_11 (0xB << 28) // (SDRAMC) Value : 11
#define AT91C_SDRAMC_TXSR_12 (0xC << 28) // (SDRAMC) Value : 12
#define AT91C_SDRAMC_TXSR_13 (0xD << 28) // (SDRAMC) Value : 13
#define AT91C_SDRAMC_TXSR_14 (0xE << 28) // (SDRAMC) Value : 14
#define AT91C_SDRAMC_TXSR_15 (0xF << 28) // (SDRAMC) Value : 15
// -------- SDRAMC_HSR : (SDRAMC Offset: 0xc) SDRAM Controller High Speed Register --------
#define AT91C_SDRAMC_DA (0x1 << 0) // (SDRAMC) Decode Cycle Enable Bit
#define AT91C_SDRAMC_DA_DISABLE (0x0) // (SDRAMC) Disable Decode Cycle
#define AT91C_SDRAMC_DA_ENABLE (0x1) // (SDRAMC) Enable Decode Cycle
// -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAM Controller Low-power Register --------
#define AT91C_SDRAMC_LPCB (0x3 << 0) // (SDRAMC) Low-power Configurations
#define AT91C_SDRAMC_LPCB_DISABLE (0x0) // (SDRAMC) Disable Low Power Features
#define AT91C_SDRAMC_LPCB_SELF_REFRESH (0x1) // (SDRAMC) Enable SELF_REFRESH
#define AT91C_SDRAMC_LPCB_POWER_DOWN (0x2) // (SDRAMC) Enable POWER_DOWN
#define AT91C_SDRAMC_LPCB_DEEP_POWER_DOWN (0x3) // (SDRAMC) Enable DEEP_POWER_DOWN
#define AT91C_SDRAMC_PASR (0x7 << 4) // (SDRAMC) Partial Array Self Refresh (only for Low Power SDRAM)
#define AT91C_SDRAMC_TCSR (0x3 << 8) // (SDRAMC) Temperature Compensated Self Refresh (only for Low Power SDRAM)
#define AT91C_SDRAMC_DS (0x3 << 10) // (SDRAMC) Drive Strenght (only for Low Power SDRAM)
#define AT91C_SDRAMC_TIMEOUT (0x3 << 12) // (SDRAMC) Time to define when Low Power Mode is enabled
#define AT91C_SDRAMC_TIMEOUT_0_CLK_CYCLES (0x0 << 12) // (SDRAMC) Activate SDRAM Low Power Mode Immediately
#define AT91C_SDRAMC_TIMEOUT_64_CLK_CYCLES (0x1 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer
#define AT91C_SDRAMC_TIMEOUT_128_CLK_CYCLES (0x2 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer
// -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAM Controller Interrupt Enable Register --------
#define AT91C_SDRAMC_RES (0x1 << 0) // (SDRAMC) Refresh Error Status
// -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAM Controller Interrupt Disable Register --------
// -------- SDRAMC_IMR : (SDRAMC Offset: 0x1c) SDRAM Controller Interrupt Mask Register --------
// -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAM Controller Interrupt Status Register --------
// -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAM Controller Memory Device Register --------
#define AT91C_SDRAMC_MD (0x3 << 0) // (SDRAMC) Memory Device Type
#define AT91C_SDRAMC_MD_SDRAM (0x0) // (SDRAMC) SDRAM Mode
#define AT91C_SDRAMC_MD_LOW_POWER_SDRAM (0x1) // (SDRAMC) SDRAM Low Power Mode
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Static Memory Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_SMC {
AT91_REG SMC_SETUP0; // Setup Register for CS 0
AT91_REG SMC_PULSE0; // Pulse Register for CS 0
AT91_REG SMC_CYCLE0; // Cycle Register for CS 0
AT91_REG SMC_CTRL0; // Control Register for CS 0
AT91_REG SMC_SETUP1; // Setup Register for CS 1
AT91_REG SMC_PULSE1; // Pulse Register for CS 1
AT91_REG SMC_CYCLE1; // Cycle Register for CS 1
AT91_REG SMC_CTRL1; // Control Register for CS 1
AT91_REG SMC_SETUP2; // Setup Register for CS 2
AT91_REG SMC_PULSE2; // Pulse Register for CS 2
AT91_REG SMC_CYCLE2; // Cycle Register for CS 2
AT91_REG SMC_CTRL2; // Control Register for CS 2
AT91_REG SMC_SETUP3; // Setup Register for CS 3
AT91_REG SMC_PULSE3; // Pulse Register for CS 3
AT91_REG SMC_CYCLE3; // Cycle Register for CS 3
AT91_REG SMC_CTRL3; // Control Register for CS 3
AT91_REG SMC_SETUP4; // Setup Register for CS 4
AT91_REG SMC_PULSE4; // Pulse Register for CS 4
AT91_REG SMC_CYCLE4; // Cycle Register for CS 4
AT91_REG SMC_CTRL4; // Control Register for CS 4
AT91_REG SMC_SETUP5; // Setup Register for CS 5
AT91_REG SMC_PULSE5; // Pulse Register for CS 5
AT91_REG SMC_CYCLE5; // Cycle Register for CS 5
AT91_REG SMC_CTRL5; // Control Register for CS 5
AT91_REG SMC_SETUP6; // Setup Register for CS 6
AT91_REG SMC_PULSE6; // Pulse Register for CS 6
AT91_REG SMC_CYCLE6; // Cycle Register for CS 6
AT91_REG SMC_CTRL6; // Control Register for CS 6
AT91_REG SMC_SETUP7; // Setup Register for CS 7
AT91_REG SMC_PULSE7; // Pulse Register for CS 7
AT91_REG SMC_CYCLE7; // Cycle Register for CS 7
AT91_REG SMC_CTRL7; // Control Register for CS 7
} AT91S_SMC, *AT91PS_SMC;
#else
#define SETUP0 (AT91_CAST(AT91_REG *) 0x00000000) // (SETUP0) Setup Register for CS 0
#define PULSE0 (AT91_CAST(AT91_REG *) 0x00000004) // (PULSE0) Pulse Register for CS 0
#define CYCLE0 (AT91_CAST(AT91_REG *) 0x00000008) // (CYCLE0) Cycle Register for CS 0
#define CTRL0 (AT91_CAST(AT91_REG *) 0x0000000C) // (CTRL0) Control Register for CS 0
#define SETUP1 (AT91_CAST(AT91_REG *) 0x00000010) // (SETUP1) Setup Register for CS 1
#define PULSE1 (AT91_CAST(AT91_REG *) 0x00000014) // (PULSE1) Pulse Register for CS 1
#define CYCLE1 (AT91_CAST(AT91_REG *) 0x00000018) // (CYCLE1) Cycle Register for CS 1
#define CTRL1 (AT91_CAST(AT91_REG *) 0x0000001C) // (CTRL1) Control Register for CS 1
#define SETUP2 (AT91_CAST(AT91_REG *) 0x00000020) // (SETUP2) Setup Register for CS 2
#define PULSE2 (AT91_CAST(AT91_REG *) 0x00000024) // (PULSE2) Pulse Register for CS 2
#define CYCLE2 (AT91_CAST(AT91_REG *) 0x00000028) // (CYCLE2) Cycle Register for CS 2
#define CTRL2 (AT91_CAST(AT91_REG *) 0x0000002C) // (CTRL2) Control Register for CS 2
#define SETUP3 (AT91_CAST(AT91_REG *) 0x00000030) // (SETUP3) Setup Register for CS 3
#define PULSE3 (AT91_CAST(AT91_REG *) 0x00000034) // (PULSE3) Pulse Register for CS 3
#define CYCLE3 (AT91_CAST(AT91_REG *) 0x00000038) // (CYCLE3) Cycle Register for CS 3
#define CTRL3 (AT91_CAST(AT91_REG *) 0x0000003C) // (CTRL3) Control Register for CS 3
#define SETUP4 (AT91_CAST(AT91_REG *) 0x00000040) // (SETUP4) Setup Register for CS 4
#define PULSE4 (AT91_CAST(AT91_REG *) 0x00000044) // (PULSE4) Pulse Register for CS 4
#define CYCLE4 (AT91_CAST(AT91_REG *) 0x00000048) // (CYCLE4) Cycle Register for CS 4
#define CTRL4 (AT91_CAST(AT91_REG *) 0x0000004C) // (CTRL4) Control Register for CS 4
#define SETUP5 (AT91_CAST(AT91_REG *) 0x00000050) // (SETUP5) Setup Register for CS 5
#define PULSE5 (AT91_CAST(AT91_REG *) 0x00000054) // (PULSE5) Pulse Register for CS 5
#define CYCLE5 (AT91_CAST(AT91_REG *) 0x00000058) // (CYCLE5) Cycle Register for CS 5
#define CTRL5 (AT91_CAST(AT91_REG *) 0x0000005C) // (CTRL5) Control Register for CS 5
#define SETUP6 (AT91_CAST(AT91_REG *) 0x00000060) // (SETUP6) Setup Register for CS 6
#define PULSE6 (AT91_CAST(AT91_REG *) 0x00000064) // (PULSE6) Pulse Register for CS 6
#define CYCLE6 (AT91_CAST(AT91_REG *) 0x00000068) // (CYCLE6) Cycle Register for CS 6
#define CTRL6 (AT91_CAST(AT91_REG *) 0x0000006C) // (CTRL6) Control Register for CS 6
#define SETUP7 (AT91_CAST(AT91_REG *) 0x00000070) // (SETUP7) Setup Register for CS 7
#define PULSE7 (AT91_CAST(AT91_REG *) 0x00000074) // (PULSE7) Pulse Register for CS 7
#define CYCLE7 (AT91_CAST(AT91_REG *) 0x00000078) // (CYCLE7) Cycle Register for CS 7
#define CTRL7 (AT91_CAST(AT91_REG *) 0x0000007C) // (CTRL7) Control Register for CS 7
#endif
// -------- SMC_SETUP : (SMC Offset: 0x0) Setup Register for CS x --------
#define AT91C_SMC_NWESETUP (0x3F << 0) // (SMC) NWE Setup Length
#define AT91C_SMC_NCSSETUPWR (0x3F << 8) // (SMC) NCS Setup Length in WRite Access
#define AT91C_SMC_NRDSETUP (0x3F << 16) // (SMC) NRD Setup Length
#define AT91C_SMC_NCSSETUPRD (0x3F << 24) // (SMC) NCS Setup Length in ReaD Access
// -------- SMC_PULSE : (SMC Offset: 0x4) Pulse Register for CS x --------
#define AT91C_SMC_NWEPULSE (0x7F << 0) // (SMC) NWE Pulse Length
#define AT91C_SMC_NCSPULSEWR (0x7F << 8) // (SMC) NCS Pulse Length in WRite Access
#define AT91C_SMC_NRDPULSE (0x7F << 16) // (SMC) NRD Pulse Length
#define AT91C_SMC_NCSPULSERD (0x7F << 24) // (SMC) NCS Pulse Length in ReaD Access
// -------- SMC_CYC : (SMC Offset: 0x8) Cycle Register for CS x --------
#define AT91C_SMC_NWECYCLE (0x1FF << 0) // (SMC) Total Write Cycle Length
#define AT91C_SMC_NRDCYCLE (0x1FF << 16) // (SMC) Total Read Cycle Length
// -------- SMC_CTRL : (SMC Offset: 0xc) Control Register for CS x --------
#define AT91C_SMC_READMODE (0x1 << 0) // (SMC) Read Mode
#define AT91C_SMC_WRITEMODE (0x1 << 1) // (SMC) Write Mode
#define AT91C_SMC_NWAITM (0x3 << 4) // (SMC) NWAIT Mode
#define AT91C_SMC_NWAITM_NWAIT_DISABLE (0x0 << 4) // (SMC) External NWAIT disabled.
#define AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN (0x2 << 4) // (SMC) External NWAIT enabled in frozen mode.
#define AT91C_SMC_NWAITM_NWAIT_ENABLE_READY (0x3 << 4) // (SMC) External NWAIT enabled in ready mode.
#define AT91C_SMC_BAT (0x1 << 8) // (SMC) Byte Access Type
#define AT91C_SMC_BAT_BYTE_SELECT (0x0 << 8) // (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.
#define AT91C_SMC_BAT_BYTE_WRITE (0x1 << 8) // (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.
#define AT91C_SMC_DBW (0x3 << 12) // (SMC) Data Bus Width
#define AT91C_SMC_DBW_WIDTH_EIGTH_BITS (0x0 << 12) // (SMC) 8 bits.
#define AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS (0x1 << 12) // (SMC) 16 bits.
#define AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) // (SMC) 32 bits.
#define AT91C_SMC_TDF (0xF << 16) // (SMC) Data Float Time.
#define AT91C_SMC_TDFEN (0x1 << 20) // (SMC) TDF Enabled.
#define AT91C_SMC_PMEN (0x1 << 24) // (SMC) Page Mode Enabled.
#define AT91C_SMC_PS (0x3 << 28) // (SMC) Page Size
#define AT91C_SMC_PS_SIZE_FOUR_BYTES (0x0 << 28) // (SMC) 4 bytes.
#define AT91C_SMC_PS_SIZE_EIGHT_BYTES (0x1 << 28) // (SMC) 8 bytes.
#define AT91C_SMC_PS_SIZE_SIXTEEN_BYTES (0x2 << 28) // (SMC) 16 bytes.
#define AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) // (SMC) 32 bytes.
// -------- SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR AHB Matrix Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_MATRIX {
AT91_REG MATRIX_MCFG0; // Master Configuration Register 0 (ram96k)
AT91_REG MATRIX_MCFG1; // Master Configuration Register 1 (rom)
AT91_REG MATRIX_MCFG2; // Master Configuration Register 2 (hperiphs)
AT91_REG MATRIX_MCFG3; // Master Configuration Register 3 (ebi)
AT91_REG MATRIX_MCFG4; // Master Configuration Register 4 (bridge)
AT91_REG MATRIX_MCFG5; // Master Configuration Register 5 (mailbox)
AT91_REG MATRIX_MCFG6; // Master Configuration Register 6 (ram16k)
AT91_REG MATRIX_MCFG7; // Master Configuration Register 7 (teak_prog)
AT91_REG Reserved0[8]; //
AT91_REG MATRIX_SCFG0; // Slave Configuration Register 0 (ram96k)
AT91_REG MATRIX_SCFG1; // Slave Configuration Register 1 (rom)
AT91_REG MATRIX_SCFG2; // Slave Configuration Register 2 (hperiphs)
AT91_REG MATRIX_SCFG3; // Slave Configuration Register 3 (ebi)
AT91_REG MATRIX_SCFG4; // Slave Configuration Register 4 (bridge)
AT91_REG Reserved1[11]; //
AT91_REG MATRIX_PRAS0; // PRAS0 (ram0)
AT91_REG MATRIX_PRBS0; // PRBS0 (ram0)
AT91_REG MATRIX_PRAS1; // PRAS1 (ram1)
AT91_REG MATRIX_PRBS1; // PRBS1 (ram1)
AT91_REG MATRIX_PRAS2; // PRAS2 (ram2)
AT91_REG MATRIX_PRBS2; // PRBS2 (ram2)
AT91_REG MATRIX_PRAS3; // PRAS3 : usb_dev_hs
AT91_REG MATRIX_PRBS3; // PRBS3 : usb_dev_hs
AT91_REG MATRIX_PRAS4; // PRAS4 : ebi
AT91_REG MATRIX_PRBS4; // PRBS4 : ebi
AT91_REG Reserved2[22]; //
AT91_REG MATRIX_MRCR; // Master Remp Control Register
AT91_REG Reserved3[6]; //
AT91_REG MATRIX_EBI; // Slave 3 (ebi) Special Function Register
AT91_REG Reserved4[3]; //
AT91_REG MATRIX_TEAKCFG; // Slave 7 (teak_prog) Special Function Register
AT91_REG Reserved5[51]; //
AT91_REG MATRIX_VERSION; // Version Register
} AT91S_MATRIX, *AT91PS_MATRIX;
#else
#define MATRIX_MCFG0 (AT91_CAST(AT91_REG *) 0x00000000) // (MATRIX_MCFG0) Master Configuration Register 0 (ram96k)
#define MATRIX_MCFG1 (AT91_CAST(AT91_REG *) 0x00000004) // (MATRIX_MCFG1) Master Configuration Register 1 (rom)
#define MATRIX_MCFG2 (AT91_CAST(AT91_REG *) 0x00000008) // (MATRIX_MCFG2) Master Configuration Register 2 (hperiphs)
#define MATRIX_MCFG3 (AT91_CAST(AT91_REG *) 0x0000000C) // (MATRIX_MCFG3) Master Configuration Register 3 (ebi)
#define MATRIX_MCFG4 (AT91_CAST(AT91_REG *) 0x00000010) // (MATRIX_MCFG4) Master Configuration Register 4 (bridge)
#define MATRIX_MCFG5 (AT91_CAST(AT91_REG *) 0x00000014) // (MATRIX_MCFG5) Master Configuration Register 5 (mailbox)
#define MATRIX_MCFG6 (AT91_CAST(AT91_REG *) 0x00000018) // (MATRIX_MCFG6) Master Configuration Register 6 (ram16k)
#define MATRIX_MCFG7 (AT91_CAST(AT91_REG *) 0x0000001C) // (MATRIX_MCFG7) Master Configuration Register 7 (teak_prog)
#define MATRIX_SCFG0 (AT91_CAST(AT91_REG *) 0x00000040) // (MATRIX_SCFG0) Slave Configuration Register 0 (ram96k)
#define MATRIX_SCFG1 (AT91_CAST(AT91_REG *) 0x00000044) // (MATRIX_SCFG1) Slave Configuration Register 1 (rom)
#define MATRIX_SCFG2 (AT91_CAST(AT91_REG *) 0x00000048) // (MATRIX_SCFG2) Slave Configuration Register 2 (hperiphs)
#define MATRIX_SCFG3 (AT91_CAST(AT91_REG *) 0x0000004C) // (MATRIX_SCFG3) Slave Configuration Register 3 (ebi)
#define MATRIX_SCFG4 (AT91_CAST(AT91_REG *) 0x00000050) // (MATRIX_SCFG4) Slave Configuration Register 4 (bridge)
#define MATRIX_PRAS0 (AT91_CAST(AT91_REG *) 0x00000080) // (MATRIX_PRAS0) PRAS0 (ram0)
#define MATRIX_PRBS0 (AT91_CAST(AT91_REG *) 0x00000084) // (MATRIX_PRBS0) PRBS0 (ram0)
#define MATRIX_PRAS1 (AT91_CAST(AT91_REG *) 0x00000088) // (MATRIX_PRAS1) PRAS1 (ram1)
#define MATRIX_PRBS1 (AT91_CAST(AT91_REG *) 0x0000008C) // (MATRIX_PRBS1) PRBS1 (ram1)
#define MATRIX_PRAS2 (AT91_CAST(AT91_REG *) 0x00000090) // (MATRIX_PRAS2) PRAS2 (ram2)
#define MATRIX_PRBS2 (AT91_CAST(AT91_REG *) 0x00000094) // (MATRIX_PRBS2) PRBS2 (ram2)
#define MATRIX_PRAS3 (AT91_CAST(AT91_REG *) 0x00000098) // (MATRIX_PRAS3) PRAS3 : usb_dev_hs
#define MATRIX_PRBS3 (AT91_CAST(AT91_REG *) 0x0000009C) // (MATRIX_PRBS3) PRBS3 : usb_dev_hs
#define MATRIX_PRAS4 (AT91_CAST(AT91_REG *) 0x000000A0) // (MATRIX_PRAS4) PRAS4 : ebi
#define MATRIX_PRBS4 (AT91_CAST(AT91_REG *) 0x000000A4) // (MATRIX_PRBS4) PRBS4 : ebi
#define MATRIX_MRCR (AT91_CAST(AT91_REG *) 0x00000100) // (MATRIX_MRCR) Master Remp Control Register
#define MATRIX_EBI (AT91_CAST(AT91_REG *) 0x0000011C) // (MATRIX_EBI) Slave 3 (ebi) Special Function Register
#define MATRIX_TEAKCFG (AT91_CAST(AT91_REG *) 0x0000012C) // (MATRIX_TEAKCFG) Slave 7 (teak_prog) Special Function Register
#define MATRIX_VERSION (AT91_CAST(AT91_REG *) 0x000001FC) // (MATRIX_VERSION) Version Register
#endif
// -------- MATRIX_SCFG0 : (MATRIX Offset: 0x40) Slave Configuration Register 0 --------
#define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0) // (MATRIX) Maximum Number of Allowed Cycles for a Burst
#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) // (MATRIX) Default Master Type
#define AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR (0x0 << 16) // (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.
#define AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR (0x1 << 16) // (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.
#define AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR (0x2 << 16) // (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.
#define AT91C_MATRIX_FIXED_DEFMSTR0 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master
// -------- MATRIX_SCFG1 : (MATRIX Offset: 0x44) Slave Configuration Register 1 --------
#define AT91C_MATRIX_FIXED_DEFMSTR1 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master
// -------- MATRIX_SCFG2 : (MATRIX Offset: 0x48) Slave Configuration Register 2 --------
#define AT91C_MATRIX_FIXED_DEFMSTR2 (0x1 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
// -------- MATRIX_SCFG3 : (MATRIX Offset: 0x4c) Slave Configuration Register 3 --------
#define AT91C_MATRIX_FIXED_DEFMSTR3 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master
// -------- MATRIX_SCFG4 : (MATRIX Offset: 0x50) Slave Configuration Register 4 --------
#define AT91C_MATRIX_FIXED_DEFMSTR4 (0x3 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR4_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
// -------- MATRIX_PRAS0 : (MATRIX Offset: 0x80) PRAS0 Register --------
#define AT91C_MATRIX_M0PR (0x3 << 0) // (MATRIX) ARM926EJ-S Instruction priority
#define AT91C_MATRIX_M1PR (0x3 << 4) // (MATRIX) ARM926EJ-S Data priority
#define AT91C_MATRIX_M2PR (0x3 << 8) // (MATRIX) PDC priority
#define AT91C_MATRIX_M3PR (0x3 << 12) // (MATRIX) LCDC priority
#define AT91C_MATRIX_M4PR (0x3 << 16) // (MATRIX) 2DGC priority
#define AT91C_MATRIX_M5PR (0x3 << 20) // (MATRIX) ISI priority
#define AT91C_MATRIX_M6PR (0x3 << 24) // (MATRIX) DMA priority
#define AT91C_MATRIX_M7PR (0x3 << 28) // (MATRIX) EMAC priority
// -------- MATRIX_PRBS0 : (MATRIX Offset: 0x84) PRBS0 Register --------
#define AT91C_MATRIX_M8PR (0x3 << 0) // (MATRIX) USB priority
// -------- MATRIX_PRAS1 : (MATRIX Offset: 0x88) PRAS1 Register --------
// -------- MATRIX_PRBS1 : (MATRIX Offset: 0x8c) PRBS1 Register --------
// -------- MATRIX_PRAS2 : (MATRIX Offset: 0x90) PRAS2 Register --------
// -------- MATRIX_PRBS2 : (MATRIX Offset: 0x94) PRBS2 Register --------
// -------- MATRIX_PRAS3 : (MATRIX Offset: 0x98) PRAS3 Register --------
// -------- MATRIX_PRBS3 : (MATRIX Offset: 0x9c) PRBS3 Register --------
// -------- MATRIX_PRAS4 : (MATRIX Offset: 0xa0) PRAS4 Register --------
// -------- MATRIX_PRBS4 : (MATRIX Offset: 0xa4) PRBS4 Register --------
// -------- MATRIX_MRCR : (MATRIX Offset: 0x100) MRCR Register --------
#define AT91C_MATRIX_RCA926I (0x1 << 0) // (MATRIX) Remap Command for ARM926EJ-S Instruction Master
#define AT91C_MATRIX_RCA926D (0x1 << 1) // (MATRIX) Remap Command for ARM926EJ-S Data Master
// -------- MATRIX_EBI : (MATRIX Offset: 0x11c) EBI (Slave 3) Special Function Register --------
#define AT91C_MATRIX_CS1A (0x1 << 1) // (MATRIX) Chip Select 1 Assignment
#define AT91C_MATRIX_CS1A_SMC (0x0 << 1) // (MATRIX) Chip Select 1 is assigned to the Static Memory Controller.
#define AT91C_MATRIX_CS1A_SDRAMC (0x1 << 1) // (MATRIX) Chip Select 1 is assigned to the SDRAM Controller.
#define AT91C_MATRIX_CS3A (0x1 << 3) // (MATRIX) Chip Select 3 Assignment
#define AT91C_MATRIX_CS3A_SMC (0x0 << 3) // (MATRIX) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.
#define AT91C_MATRIX_CS3A_SM (0x1 << 3) // (MATRIX) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
#define AT91C_MATRIX_CS4A (0x1 << 4) // (MATRIX) Chip Select 4 Assignment
#define AT91C_MATRIX_CS4A_SMC (0x0 << 4) // (MATRIX) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.
#define AT91C_MATRIX_CS4A_CF (0x1 << 4) // (MATRIX) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.
#define AT91C_MATRIX_CS5A (0x1 << 5) // (MATRIX) Chip Select 5 Assignment
#define AT91C_MATRIX_CS5A_SMC (0x0 << 5) // (MATRIX) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC
#define AT91C_MATRIX_CS5A_CF (0x1 << 5) // (MATRIX) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.
#define AT91C_MATRIX_DBPUC (0x1 << 8) // (MATRIX) Data Bus Pull-up Configuration
// -------- MATRIX_TEAKCFG : (MATRIX Offset: 0x12c) Slave 7 Special Function Register --------
#define AT91C_TEAK_PROGRAM_ACCESS (0x1 << 0) // (MATRIX) TEAK program memory access from AHB
#define AT91C_TEAK_PROGRAM_ACCESS_DISABLED (0x0) // (MATRIX) TEAK program access disabled
#define AT91C_TEAK_PROGRAM_ACCESS_ENABLED (0x1) // (MATRIX) TEAK program access enabled
#define AT91C_TEAK_BOOT (0x1 << 1) // (MATRIX) TEAK program start from boot routine
#define AT91C_TEAK_BOOT_DISABLED (0x0 << 1) // (MATRIX) TEAK program starts from boot routine disabled
#define AT91C_TEAK_BOOT_ENABLED (0x1 << 1) // (MATRIX) TEAK program starts from boot routine enabled
#define AT91C_TEAK_NRESET (0x1 << 2) // (MATRIX) active low TEAK reset
#define AT91C_TEAK_NRESET_ENABLED (0x0 << 2) // (MATRIX) active low TEAK reset enabled
#define AT91C_TEAK_NRESET_DISABLED (0x1 << 2) // (MATRIX) active low TEAK reset disabled
#define AT91C_TEAK_LVECTORP (0x3FFFF << 14) // (MATRIX) boot routine start address
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Chip Configuration Registers
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_CCFG {
AT91_REG Reserved0[3]; //
AT91_REG CCFG_EBICSA; // EBI Chip Select Assignement Register
AT91_REG Reserved1[55]; //
AT91_REG CCFG_MATRIXVERSION; // Version Register
} AT91S_CCFG, *AT91PS_CCFG;
#else
#define CCFG_EBICSA (AT91_CAST(AT91_REG *) 0x0000000C) // (CCFG_EBICSA) EBI Chip Select Assignement Register
#define CCFG_MATRIXVERSION (AT91_CAST(AT91_REG *) 0x000000EC) // (CCFG_MATRIXVERSION) Version Register
#endif
// -------- CCFG_EBICSA : (CCFG Offset: 0xc) EBI Chip Select Assignement Register --------
#define AT91C_EBI_CS1A (0x1 << 1) // (CCFG) Chip Select 1 Assignment
#define AT91C_EBI_CS1A_SMC (0x0 << 1) // (CCFG) Chip Select 1 is assigned to the Static Memory Controller.
#define AT91C_EBI_CS1A_SDRAMC (0x1 << 1) // (CCFG) Chip Select 1 is assigned to the SDRAM Controller.
#define AT91C_EBI_CS3A (0x1 << 3) // (CCFG) Chip Select 3 Assignment
#define AT91C_EBI_CS3A_SMC (0x0 << 3) // (CCFG) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.
#define AT91C_EBI_CS3A_SM (0x1 << 3) // (CCFG) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
#define AT91C_EBI_CS4A (0x1 << 4) // (CCFG) Chip Select 4 Assignment
#define AT91C_EBI_CS4A_SMC (0x0 << 4) // (CCFG) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.
#define AT91C_EBI_CS4A_CF (0x1 << 4) // (CCFG) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.
#define AT91C_EBI_CS5A (0x1 << 5) // (CCFG) Chip Select 5 Assignment
#define AT91C_EBI_CS5A_SMC (0x0 << 5) // (CCFG) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC
#define AT91C_EBI_CS5A_CF (0x1 << 5) // (CCFG) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.
#define AT91C_EBI_DBPUC (0x1 << 8) // (CCFG) Data Bus Pull-up Configuration
#define AT91C_EBI_SUPPLY (0x1 << 16) // (CCFG) EBI supply selection
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_PDC {
AT91_REG PDC_RPR; // Receive Pointer Register
AT91_REG PDC_RCR; // Receive Counter Register
AT91_REG PDC_TPR; // Transmit Pointer Register
AT91_REG PDC_TCR; // Transmit Counter Register
AT91_REG PDC_RNPR; // Receive Next Pointer Register
AT91_REG PDC_RNCR; // Receive Next Counter Register
AT91_REG PDC_TNPR; // Transmit Next Pointer Register
AT91_REG PDC_TNCR; // Transmit Next Counter Register
AT91_REG PDC_PTCR; // PDC Transfer Control Register
AT91_REG PDC_PTSR; // PDC Transfer Status Register
} AT91S_PDC, *AT91PS_PDC;
#else
#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register
#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register
#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register
#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register
#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register
#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register
#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register
#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register
#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register
#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register
#endif
// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable
#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable
#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable
#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable
// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Debug Unit
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_DBGU {
AT91_REG DBGU_CR; // Control Register
AT91_REG DBGU_MR; // Mode Register
AT91_REG DBGU_IER; // Interrupt Enable Register
AT91_REG DBGU_IDR; // Interrupt Disable Register
AT91_REG DBGU_IMR; // Interrupt Mask Register
AT91_REG DBGU_CSR; // Channel Status Register
AT91_REG DBGU_RHR; // Receiver Holding Register
AT91_REG DBGU_THR; // Transmitter Holding Register
AT91_REG DBGU_BRGR; // Baud Rate Generator Register
AT91_REG Reserved0[7]; //
AT91_REG DBGU_CIDR; // Chip ID Register
AT91_REG DBGU_EXID; // Chip ID Extension Register
AT91_REG DBGU_FNTR; // Force NTRST Register
AT91_REG Reserved1[45]; //
AT91_REG DBGU_RPR; // Receive Pointer Register
AT91_REG DBGU_RCR; // Receive Counter Register
AT91_REG DBGU_TPR; // Transmit Pointer Register
AT91_REG DBGU_TCR; // Transmit Counter Register
AT91_REG DBGU_RNPR; // Receive Next Pointer Register
AT91_REG DBGU_RNCR; // Receive Next Counter Register
AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
AT91_REG DBGU_TNCR; // Transmit Next Counter Register
AT91_REG DBGU_PTCR; // PDC Transfer Control Register
AT91_REG DBGU_PTSR; // PDC Transfer Status Register
} AT91S_DBGU, *AT91PS_DBGU;
#else
#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register
#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register
#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register
#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register
#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register
#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register
#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register
#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register
#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register
#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register
#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register
#endif
// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver
#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter
#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable
#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable
#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable
#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable
#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits
// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type
#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity
#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity
#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)
#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity
#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode
#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode
#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt
#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt
#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt
#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt
#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt
#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt
#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt
#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt
#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt
#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt
#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt
// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_AIC {
AT91_REG AIC_SMR[32]; // Source Mode Register
AT91_REG AIC_SVR[32]; // Source Vector Register
AT91_REG AIC_IVR; // IRQ Vector Register
AT91_REG AIC_FVR; // FIQ Vector Register
AT91_REG AIC_ISR; // Interrupt Status Register
AT91_REG AIC_IPR; // Interrupt Pending Register
AT91_REG AIC_IMR; // Interrupt Mask Register
AT91_REG AIC_CISR; // Core Interrupt Status Register
AT91_REG Reserved0[2]; //
AT91_REG AIC_IECR; // Interrupt Enable Command Register
AT91_REG AIC_IDCR; // Interrupt Disable Command Register
AT91_REG AIC_ICCR; // Interrupt Clear Command Register
AT91_REG AIC_ISCR; // Interrupt Set Command Register
AT91_REG AIC_EOICR; // End of Interrupt Command Register
AT91_REG AIC_SPU; // Spurious Vector Register
AT91_REG AIC_DCR; // Debug Control Register (Protect)
AT91_REG Reserved1[1]; //
AT91_REG AIC_FFER; // Fast Forcing Enable Register
AT91_REG AIC_FFDR; // Fast Forcing Disable Register
AT91_REG AIC_FFSR; // Fast Forcing Status Register
} AT91S_AIC, *AT91PS_AIC;
#else
#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register
#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register
#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register
#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register
#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register
#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register
#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register
#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register
#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register
#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register
#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register
#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register
#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register
#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register
#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect)
#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register
#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register
#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register
#endif
// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level
#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level
#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level
#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type
#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive
#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered
#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive
#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered
// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status
#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status
// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode
#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_PIO {
AT91_REG PIO_PER; // PIO Enable Register
AT91_REG PIO_PDR; // PIO Disable Register
AT91_REG PIO_PSR; // PIO Status Register
AT91_REG Reserved0[1]; //
AT91_REG PIO_OER; // Output Enable Register
AT91_REG PIO_ODR; // Output Disable Registerr
AT91_REG PIO_OSR; // Output Status Register
AT91_REG Reserved1[1]; //
AT91_REG PIO_IFER; // Input Filter Enable Register
AT91_REG PIO_IFDR; // Input Filter Disable Register
AT91_REG PIO_IFSR; // Input Filter Status Register
AT91_REG Reserved2[1]; //
AT91_REG PIO_SODR; // Set Output Data Register
AT91_REG PIO_CODR; // Clear Output Data Register
AT91_REG PIO_ODSR; // Output Data Status Register
AT91_REG PIO_PDSR; // Pin Data Status Register
AT91_REG PIO_IER; // Interrupt Enable Register
AT91_REG PIO_IDR; // Interrupt Disable Register
AT91_REG PIO_IMR; // Interrupt Mask Register
AT91_REG PIO_ISR; // Interrupt Status Register
AT91_REG PIO_MDER; // Multi-driver Enable Register
AT91_REG PIO_MDDR; // Multi-driver Disable Register
AT91_REG PIO_MDSR; // Multi-driver Status Register
AT91_REG Reserved3[1]; //
AT91_REG PIO_PPUDR; // Pull-up Disable Register
AT91_REG PIO_PPUER; // Pull-up Enable Register
AT91_REG PIO_PPUSR; // Pull-up Status Register
AT91_REG Reserved4[1]; //
AT91_REG PIO_ASR; // Select A Register
AT91_REG PIO_BSR; // Select B Register
AT91_REG PIO_ABSR; // AB Select Status Register
AT91_REG Reserved5[9]; //
AT91_REG PIO_OWER; // Output Write Enable Register
AT91_REG PIO_OWDR; // Output Write Disable Register
AT91_REG PIO_OWSR; // Output Write Status Register
} AT91S_PIO, *AT91PS_PIO;
#else
#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register
#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register
#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register
#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register
#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr
#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register
#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register
#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register
#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register
#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register
#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register
#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register
#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register
#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register
#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register
#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register
#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register
#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register
#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register
#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register
#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register
#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register
#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register
#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register
#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register
#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register
#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register
#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register
#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register
#endif
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Embedded Flash Controller 2.0
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_EFC {
AT91_REG EFC_FMR; // EFC Flash Mode Register
AT91_REG EFC_FCR; // EFC Flash Command Register
AT91_REG EFC_FSR; // EFC Flash Status Register
AT91_REG EFC_FRR; // EFC Flash Result Register
AT91_REG EFC_FVR; // EFC Flash Version Register
} AT91S_EFC, *AT91PS_EFC;
#else
#define EFC_FMR (AT91_CAST(AT91_REG *) 0x00000000) // (EFC_FMR) EFC Flash Mode Register
#define EFC_FCR (AT91_CAST(AT91_REG *) 0x00000004) // (EFC_FCR) EFC Flash Command Register
#define EFC_FSR (AT91_CAST(AT91_REG *) 0x00000008) // (EFC_FSR) EFC Flash Status Register
#define EFC_FRR (AT91_CAST(AT91_REG *) 0x0000000C) // (EFC_FRR) EFC Flash Result Register
#define EFC_FVR (AT91_CAST(AT91_REG *) 0x00000010) // (EFC_FVR) EFC Flash Version Register
#endif
// -------- EFC_FMR : (EFC Offset: 0x0) EFC Flash Mode Register --------
#define AT91C_EFC_FRDY (0x1 << 0) // (EFC) Ready Interrupt Enable
#define AT91C_EFC_FWS (0xF << 8) // (EFC) Flash Wait State.
#define AT91C_EFC_FWS_0WS (0x0 << 8) // (EFC) 0 Wait State
#define AT91C_EFC_FWS_1WS (0x1 << 8) // (EFC) 1 Wait State
#define AT91C_EFC_FWS_2WS (0x2 << 8) // (EFC) 2 Wait States
#define AT91C_EFC_FWS_3WS (0x3 << 8) // (EFC) 3 Wait States
// -------- EFC_FCR : (EFC Offset: 0x4) EFC Flash Command Register --------
#define AT91C_EFC_FCMD (0xFF << 0) // (EFC) Flash Command
#define AT91C_EFC_FCMD_GETD (0x0) // (EFC) Get Flash Descriptor
#define AT91C_EFC_FCMD_WP (0x1) // (EFC) Write Page
#define AT91C_EFC_FCMD_WPL (0x2) // (EFC) Write Page and Lock
#define AT91C_EFC_FCMD_EWP (0x3) // (EFC) Erase Page and Write Page
#define AT91C_EFC_FCMD_EWPL (0x4) // (EFC) Erase Page and Write Page then Lock
#define AT91C_EFC_FCMD_EA (0x5) // (EFC) Erase All
#define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase Plane
#define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase Pages
#define AT91C_EFC_FCMD_SLB (0x8) // (EFC) Set Lock Bit
#define AT91C_EFC_FCMD_CLB (0x9) // (EFC) Clear Lock Bit
#define AT91C_EFC_FCMD_GLB (0xA) // (EFC) Get Lock Bit
#define AT91C_EFC_FCMD_SFB (0xB) // (EFC) Set Fuse Bit
#define AT91C_EFC_FCMD_CFB (0xC) // (EFC) Clear Fuse Bit
#define AT91C_EFC_FCMD_GFB (0xD) // (EFC) Get Fuse Bit
#define AT91C_EFC_FARG (0xFFFF << 8) // (EFC) Flash Command Argument
#define AT91C_EFC_FKEY (0xFF << 24) // (EFC) Flash Writing Protection Key
// -------- EFC_FSR : (EFC Offset: 0x8) EFC Flash Status Register --------
#define AT91C_EFC_FRDY_S (0x1 << 0) // (EFC) Flash Ready Status
#define AT91C_EFC_FCMDE (0x1 << 1) // (EFC) Flash Command Error Status
#define AT91C_EFC_LOCKE (0x1 << 2) // (EFC) Flash Lock Error Status
// -------- EFC_FRR : (EFC Offset: 0xc) EFC Flash Result Register --------
#define AT91C_EFC_FVALUE (0x0 << 0) // (EFC) Flash Result Value
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Clock Generator Controler
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_CKGR {
AT91_REG CKGR_MOR; // Main Oscillator Register
AT91_REG CKGR_MCFR; // Main Clock Frequency Register
AT91_REG CKGR_PLLAR; // PLL A Register
AT91_REG CKGR_PLLBR; // PLL B Register
} AT91S_CKGR, *AT91PS_CKGR;
#else
#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register
#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register
#define CKGR_PLLAR (AT91_CAST(AT91_REG *) 0x00000008) // (CKGR_PLLAR) PLL A Register
#define CKGR_PLLBR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLBR) PLL B Register
#endif
// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable
#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass
#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time
// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency
#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready
// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register --------
#define AT91C_CKGR_DIVA (0xFF << 0) // (CKGR) Divider A Selected
#define AT91C_CKGR_DIVA_0 (0x0) // (CKGR) Divider A output is 0
#define AT91C_CKGR_DIVA_BYPASS (0x1) // (CKGR) Divider A is bypassed
#define AT91C_CKGR_PLLACOUNT (0x3F << 8) // (CKGR) PLL A Counter
#define AT91C_CKGR_OUTA (0x3 << 14) // (CKGR) PLL A Output Frequency Range
#define AT91C_CKGR_OUTA_0 (0x0 << 14) // (CKGR) Please refer to the PLLA datasheet
#define AT91C_CKGR_OUTA_1 (0x1 << 14) // (CKGR) Please refer to the PLLA datasheet
#define AT91C_CKGR_OUTA_2 (0x2 << 14) // (CKGR) Please refer to the PLLA datasheet
#define AT91C_CKGR_OUTA_3 (0x3 << 14) // (CKGR) Please refer to the PLLA datasheet
#define AT91C_CKGR_MULA (0x7FF << 16) // (CKGR) PLL A Multiplier
#define AT91C_CKGR_SRCA (0x1 << 29) // (CKGR)
// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register --------
#define AT91C_CKGR_DIVB (0xFF << 0) // (CKGR) Divider B Selected
#define AT91C_CKGR_DIVB_0 (0x0) // (CKGR) Divider B output is 0
#define AT91C_CKGR_DIVB_BYPASS (0x1) // (CKGR) Divider B is bypassed
#define AT91C_CKGR_PLLBCOUNT (0x3F << 8) // (CKGR) PLL B Counter
#define AT91C_CKGR_OUTB (0x3 << 14) // (CKGR) PLL B Output Frequency Range
#define AT91C_CKGR_OUTB_0 (0x0 << 14) // (CKGR) Please refer to the PLLB datasheet
#define AT91C_CKGR_OUTB_1 (0x1 << 14) // (CKGR) Please refer to the PLLB datasheet
#define AT91C_CKGR_OUTB_2 (0x2 << 14) // (CKGR) Please refer to the PLLB datasheet
#define AT91C_CKGR_OUTB_3 (0x3 << 14) // (CKGR) Please refer to the PLLB datasheet
#define AT91C_CKGR_MULB (0x7FF << 16) // (CKGR) PLL B Multiplier
#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks
#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output
#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Power Management Controler
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_PMC {
AT91_REG PMC_SCER; // System Clock Enable Register
AT91_REG PMC_SCDR; // System Clock Disable Register
AT91_REG PMC_SCSR; // System Clock Status Register
AT91_REG Reserved0[1]; //
AT91_REG PMC_PCER; // Peripheral Clock Enable Register
AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
AT91_REG PMC_PCSR; // Peripheral Clock Status Register
AT91_REG Reserved1[1]; //
AT91_REG PMC_MOR; // Main Oscillator Register
AT91_REG PMC_MCFR; // Main Clock Frequency Register
AT91_REG PMC_PLLAR; // PLL A Register
AT91_REG PMC_PLLBR; // PLL B Register
AT91_REG PMC_MCKR; // Master Clock Register
AT91_REG Reserved2[3]; //
AT91_REG PMC_PCKR[8]; // Programmable Clock Register
AT91_REG PMC_IER; // Interrupt Enable Register
AT91_REG PMC_IDR; // Interrupt Disable Register
AT91_REG PMC_SR; // Status Register
AT91_REG PMC_IMR; // Interrupt Mask Register
} AT91S_PMC, *AT91PS_PMC;
#else
#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register
#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register
#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register
#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register
#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register
#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register
#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register
#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register
#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register
#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register
#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register
#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register
#endif
// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock
#define AT91C_PMC_OTG (0x1 << 5) // (PMC) USB OTG Clock
#define AT91C_PMC_UHP (0x1 << 6) // (PMC) USB Host Port Clock
#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock
#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output
// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
// -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register --------
// -------- CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register --------
// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection
#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected
#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected
#define AT91C_PMC_CSS_PLLA_CLK (0x2) // (PMC) Clock from PLL A is selected
#define AT91C_PMC_CSS_PLLB_CLK (0x3) // (PMC) Clock from PLL B is selected
#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler
#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock
#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2
#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4
#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8
#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16
#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32
#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64
#define AT91C_PMC_MDIV (0x3 << 8) // (PMC) Master Clock Division
#define AT91C_PMC_MDIV_1 (0x0 << 8) // (PMC) The master clock and the processor clock are the same
#define AT91C_PMC_MDIV_2 (0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock
#define AT91C_PMC_MDIV_3 (0x2 << 8) // (PMC) The processor clock is four times faster than the master clock
// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
#define AT91C_PMC_LOCKA (0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask
#define AT91C_PMC_LOCKB (0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask
#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) Master Clock Status/Enable/Disable/Mask
#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Reset Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_RSTC {
AT91_REG RSTC_RCR; // Reset Control Register
AT91_REG RSTC_RSR; // Reset Status Register
AT91_REG RSTC_RMR; // Reset Mode Register
} AT91S_RSTC, *AT91PS_RSTC;
#else
#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register
#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register
#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register
#endif
// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset
#define AT91C_RSTC_ICERST (0x1 << 1) // (RSTC) ICE Interface Reset
#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset
#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset
#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password
// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status
#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type
#define AT91C_RSTC_RSTTYP_GENERAL (0x0 << 8) // (RSTC) General reset. Both VDDCORE and VDDBU rising.
#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level
#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.
// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable
#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable
#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Shut Down Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_SHDWC {
AT91_REG SHDWC_SHCR; // Shut Down Control Register
AT91_REG SHDWC_SHMR; // Shut Down Mode Register
AT91_REG SHDWC_SHSR; // Shut Down Status Register
} AT91S_SHDWC, *AT91PS_SHDWC;
#else
#define SHDWC_SHCR (AT91_CAST(AT91_REG *) 0x00000000) // (SHDWC_SHCR) Shut Down Control Register
#define SHDWC_SHMR (AT91_CAST(AT91_REG *) 0x00000004) // (SHDWC_SHMR) Shut Down Mode Register
#define SHDWC_SHSR (AT91_CAST(AT91_REG *) 0x00000008) // (SHDWC_SHSR) Shut Down Status Register
#endif
// -------- SHDWC_SHCR : (SHDWC Offset: 0x0) Shut Down Control Register --------
#define AT91C_SHDWC_SHDW (0x1 << 0) // (SHDWC) Processor Reset
#define AT91C_SHDWC_KEY (0xFF << 24) // (SHDWC) Shut down KEY Password
// -------- SHDWC_SHMR : (SHDWC Offset: 0x4) Shut Down Mode Register --------
#define AT91C_SHDWC_WKMODE0 (0x3 << 0) // (SHDWC) Wake Up 0 Mode Selection
#define AT91C_SHDWC_WKMODE0_NONE (0x0) // (SHDWC) None. No detection is performed on the wake up input.
#define AT91C_SHDWC_WKMODE0_HIGH (0x1) // (SHDWC) High Level.
#define AT91C_SHDWC_WKMODE0_LOW (0x2) // (SHDWC) Low Level.
#define AT91C_SHDWC_WKMODE0_ANYLEVEL (0x3) // (SHDWC) Any level change.
#define AT91C_SHDWC_CPTWK0 (0xF << 4) // (SHDWC) Counter On Wake Up 0
#define AT91C_SHDWC_WKMODE1 (0x3 << 8) // (SHDWC) Wake Up 1 Mode Selection
#define AT91C_SHDWC_WKMODE1_NONE (0x0 << 8) // (SHDWC) None. No detection is performed on the wake up input.
#define AT91C_SHDWC_WKMODE1_HIGH (0x1 << 8) // (SHDWC) High Level.
#define AT91C_SHDWC_WKMODE1_LOW (0x2 << 8) // (SHDWC) Low Level.
#define AT91C_SHDWC_WKMODE1_ANYLEVEL (0x3 << 8) // (SHDWC) Any level change.
#define AT91C_SHDWC_CPTWK1 (0xF << 12) // (SHDWC) Counter On Wake Up 1
#define AT91C_SHDWC_RTTWKEN (0x1 << 16) // (SHDWC) Real Time Timer Wake Up Enable
#define AT91C_SHDWC_RTCWKEN (0x1 << 17) // (SHDWC) Real Time Clock Wake Up Enable
// -------- SHDWC_SHSR : (SHDWC Offset: 0x8) Shut Down Status Register --------
#define AT91C_SHDWC_WAKEUP0 (0x1 << 0) // (SHDWC) Wake Up 0 Status
#define AT91C_SHDWC_WAKEUP1 (0x1 << 1) // (SHDWC) Wake Up 1 Status
#define AT91C_SHDWC_FWKUP (0x1 << 2) // (SHDWC) Force Wake Up Status
#define AT91C_SHDWC_RTTWK (0x1 << 16) // (SHDWC) Real Time Timer wake Up
#define AT91C_SHDWC_RTCWK (0x1 << 17) // (SHDWC) Real Time Clock wake Up
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_RTTC {
AT91_REG RTTC_RTMR; // Real-time Mode Register
AT91_REG RTTC_RTAR; // Real-time Alarm Register
AT91_REG RTTC_RTVR; // Real-time Value Register
AT91_REG RTTC_RTSR; // Real-time Status Register
} AT91S_RTTC, *AT91PS_RTTC;
#else
#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register
#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register
#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register
#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register
#endif
// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable
#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart
// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value
// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value
// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status
#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_PITC {
AT91_REG PITC_PIMR; // Period Interval Mode Register
AT91_REG PITC_PISR; // Period Interval Status Register
AT91_REG PITC_PIVR; // Period Interval Value Register
AT91_REG PITC_PIIR; // Period Interval Image Register
} AT91S_PITC, *AT91PS_PITC;
#else
#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register
#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register
#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register
#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register
#endif
// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value
#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status
// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value
#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter
// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_WDTC {
AT91_REG WDTC_WDCR; // Watchdog Control Register
AT91_REG WDTC_WDMR; // Watchdog Mode Register
AT91_REG WDTC_WDSR; // Watchdog Status Register
} AT91S_WDTC, *AT91PS_WDTC;
#else
#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register
#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register
#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register
#endif
// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart
#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password
// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart
#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable
#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart
#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable
#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value
#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt
#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt
// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow
#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_TC {
AT91_REG TC_CCR; // Channel Control Register
AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
AT91_REG Reserved0[2]; //
AT91_REG TC_CV; // Counter Value
AT91_REG TC_RA; // Register A
AT91_REG TC_RB; // Register B
AT91_REG TC_RC; // Register C
AT91_REG TC_SR; // Status Register
AT91_REG TC_IER; // Interrupt Enable Register
AT91_REG TC_IDR; // Interrupt Disable Register
AT91_REG TC_IMR; // Interrupt Mask Register
} AT91S_TC, *AT91PS_TC;
#else
#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register
#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)
#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value
#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A
#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B
#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C
#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register
#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register
#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register
#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register
#endif
// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command
#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command
#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command
// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection
#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0
#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1
#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2
#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert
#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection
#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal
#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock
#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock
#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock
#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare
#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection
#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None
#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection
#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None
#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection
#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable
#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection
#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable
#define AT91C_TC_WAVE (0x1 << 15) // (TC)
#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA
#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none
#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set
#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear
#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle
#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection
#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None
#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA
#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA
#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA
#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA
#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none
#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set
#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear
#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle
#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection
#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None
#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA
#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA
#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA
#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA
#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none
#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set
#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear
#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle
#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA
#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none
#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set
#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear
#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle
#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB
#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none
#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set
#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear
#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle
#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB
#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none
#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set
#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear
#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle
#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB
#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none
#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set
#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear
#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle
#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB
#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none
#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set
#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear
#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle
// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow
#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun
#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare
#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare
#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare
#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading
#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading
#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger
#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling
#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror
#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror
// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Timer Counter Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_TCB {
AT91S_TC TCB_TC0; // TC Channel 0
AT91_REG Reserved0[4]; //
AT91S_TC TCB_TC1; // TC Channel 1
AT91_REG Reserved1[4]; //
AT91S_TC TCB_TC2; // TC Channel 2
AT91_REG Reserved2[4]; //
AT91_REG TCB_BCR; // TC Block Control Register
AT91_REG TCB_BMR; // TC Block Mode Register
} AT91S_TCB, *AT91PS_TCB;
#else
#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register
#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register
#endif
// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command
// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection
#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0
#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0
#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0
#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0
#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection
#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1
#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1
#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1
#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1
#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection
#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2
#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2
#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2
#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Multimedia Card Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_MCI {
AT91_REG MCI_CR; // MCI Control Register
AT91_REG MCI_MR; // MCI Mode Register
AT91_REG MCI_DTOR; // MCI Data Timeout Register
AT91_REG MCI_SDCR; // MCI SD Card Register
AT91_REG MCI_ARGR; // MCI Argument Register
AT91_REG MCI_CMDR; // MCI Command Register
AT91_REG MCI_BLKR; // MCI Block Register
AT91_REG Reserved0[1]; //
AT91_REG MCI_RSPR[4]; // MCI Response Register
AT91_REG MCI_RDR; // MCI Receive Data Register
AT91_REG MCI_TDR; // MCI Transmit Data Register
AT91_REG Reserved1[2]; //
AT91_REG MCI_SR; // MCI Status Register
AT91_REG MCI_IER; // MCI Interrupt Enable Register
AT91_REG MCI_IDR; // MCI Interrupt Disable Register
AT91_REG MCI_IMR; // MCI Interrupt Mask Register
AT91_REG Reserved2[43]; //
AT91_REG MCI_VR; // MCI Version Register
AT91_REG MCI_RPR; // Receive Pointer Register
AT91_REG MCI_RCR; // Receive Counter Register
AT91_REG MCI_TPR; // Transmit Pointer Register
AT91_REG MCI_TCR; // Transmit Counter Register
AT91_REG MCI_RNPR; // Receive Next Pointer Register
AT91_REG MCI_RNCR; // Receive Next Counter Register
AT91_REG MCI_TNPR; // Transmit Next Pointer Register
AT91_REG MCI_TNCR; // Transmit Next Counter Register
AT91_REG MCI_PTCR; // PDC Transfer Control Register
AT91_REG MCI_PTSR; // PDC Transfer Status Register
} AT91S_MCI, *AT91PS_MCI;
#else
#define MCI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (MCI_CR) MCI Control Register
#define MCI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (MCI_MR) MCI Mode Register
#define MCI_DTOR (AT91_CAST(AT91_REG *) 0x00000008) // (MCI_DTOR) MCI Data Timeout Register
#define MCI_SDCR (AT91_CAST(AT91_REG *) 0x0000000C) // (MCI_SDCR) MCI SD Card Register
#define MCI_ARGR (AT91_CAST(AT91_REG *) 0x00000010) // (MCI_ARGR) MCI Argument Register
#define MCI_CMDR (AT91_CAST(AT91_REG *) 0x00000014) // (MCI_CMDR) MCI Command Register
#define MCI_BLKR (AT91_CAST(AT91_REG *) 0x00000018) // (MCI_BLKR) MCI Block Register
#define MCI_RSPR (AT91_CAST(AT91_REG *) 0x00000020) // (MCI_RSPR) MCI Response Register
#define MCI_RDR (AT91_CAST(AT91_REG *) 0x00000030) // (MCI_RDR) MCI Receive Data Register
#define MCI_TDR (AT91_CAST(AT91_REG *) 0x00000034) // (MCI_TDR) MCI Transmit Data Register
#define MCI_SR (AT91_CAST(AT91_REG *) 0x00000040) // (MCI_SR) MCI Status Register
#define MCI_IER (AT91_CAST(AT91_REG *) 0x00000044) // (MCI_IER) MCI Interrupt Enable Register
#define MCI_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (MCI_IDR) MCI Interrupt Disable Register
#define MCI_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (MCI_IMR) MCI Interrupt Mask Register
#define MCI_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (MCI_VR) MCI Version Register
#endif
// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register --------
#define AT91C_MCI_MCIEN (0x1 << 0) // (MCI) Multimedia Interface Enable
#define AT91C_MCI_MCIDIS (0x1 << 1) // (MCI) Multimedia Interface Disable
#define AT91C_MCI_PWSEN (0x1 << 2) // (MCI) Power Save Mode Enable
#define AT91C_MCI_PWSDIS (0x1 << 3) // (MCI) Power Save Mode Disable
#define AT91C_MCI_SWRST (0x1 << 7) // (MCI) MCI Software reset
// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register --------
#define AT91C_MCI_CLKDIV (0xFF << 0) // (MCI) Clock Divider
#define AT91C_MCI_PWSDIV (0x7 << 8) // (MCI) Power Saving Divider
#define AT91C_MCI_RDPROOF (0x1 << 11) // (MCI) Read Proof Enable
#define AT91C_MCI_WRPROOF (0x1 << 12) // (MCI) Write Proof Enable
#define AT91C_MCI_PDCFBYTE (0x1 << 13) // (MCI) PDC Force Byte Transfer
#define AT91C_MCI_PDCPADV (0x1 << 14) // (MCI) PDC Padding Value
#define AT91C_MCI_PDCMODE (0x1 << 15) // (MCI) PDC Oriented Mode
#define AT91C_MCI_BLKLEN (0xFFFF << 16) // (MCI) Data Block Length
// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register --------
#define AT91C_MCI_DTOCYC (0xF << 0) // (MCI) Data Timeout Cycle Number
#define AT91C_MCI_DTOMUL (0x7 << 4) // (MCI) Data Timeout Multiplier
#define AT91C_MCI_DTOMUL_1 (0x0 << 4) // (MCI) DTOCYC x 1
#define AT91C_MCI_DTOMUL_16 (0x1 << 4) // (MCI) DTOCYC x 16
#define AT91C_MCI_DTOMUL_128 (0x2 << 4) // (MCI) DTOCYC x 128
#define AT91C_MCI_DTOMUL_256 (0x3 << 4) // (MCI) DTOCYC x 256
#define AT91C_MCI_DTOMUL_1024 (0x4 << 4) // (MCI) DTOCYC x 1024
#define AT91C_MCI_DTOMUL_4096 (0x5 << 4) // (MCI) DTOCYC x 4096
#define AT91C_MCI_DTOMUL_65536 (0x6 << 4) // (MCI) DTOCYC x 65536
#define AT91C_MCI_DTOMUL_1048576 (0x7 << 4) // (MCI) DTOCYC x 1048576
// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register --------
#define AT91C_MCI_SCDSEL (0x3 << 0) // (MCI) SD Card Selector
#define AT91C_MCI_SCDBUS (0x1 << 7) // (MCI) SDCard/SDIO Bus Width
// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register --------
#define AT91C_MCI_CMDNB (0x3F << 0) // (MCI) Command Number
#define AT91C_MCI_RSPTYP (0x3 << 6) // (MCI) Response Type
#define AT91C_MCI_RSPTYP_NO (0x0 << 6) // (MCI) No response
#define AT91C_MCI_RSPTYP_48 (0x1 << 6) // (MCI) 48-bit response
#define AT91C_MCI_RSPTYP_136 (0x2 << 6) // (MCI) 136-bit response
#define AT91C_MCI_SPCMD (0x7 << 8) // (MCI) Special CMD
#define AT91C_MCI_SPCMD_NONE (0x0 << 8) // (MCI) Not a special CMD
#define AT91C_MCI_SPCMD_INIT (0x1 << 8) // (MCI) Initialization CMD
#define AT91C_MCI_SPCMD_SYNC (0x2 << 8) // (MCI) Synchronized CMD
#define AT91C_MCI_SPCMD_IT_CMD (0x4 << 8) // (MCI) Interrupt command
#define AT91C_MCI_SPCMD_IT_REP (0x5 << 8) // (MCI) Interrupt response
#define AT91C_MCI_OPDCMD (0x1 << 11) // (MCI) Open Drain Command
#define AT91C_MCI_MAXLAT (0x1 << 12) // (MCI) Maximum Latency for Command to respond
#define AT91C_MCI_TRCMD (0x3 << 16) // (MCI) Transfer CMD
#define AT91C_MCI_TRCMD_NO (0x0 << 16) // (MCI) No transfer
#define AT91C_MCI_TRCMD_START (0x1 << 16) // (MCI) Start transfer
#define AT91C_MCI_TRCMD_STOP (0x2 << 16) // (MCI) Stop transfer
#define AT91C_MCI_TRDIR (0x1 << 18) // (MCI) Transfer Direction
#define AT91C_MCI_TRTYP (0x7 << 19) // (MCI) Transfer Type
#define AT91C_MCI_TRTYP_BLOCK (0x0 << 19) // (MCI) MMC/SDCard Single Block Transfer type
#define AT91C_MCI_TRTYP_MULTIPLE (0x1 << 19) // (MCI) MMC/SDCard Multiple Block transfer type
#define AT91C_MCI_TRTYP_STREAM (0x2 << 19) // (MCI) MMC Stream transfer type
#define AT91C_MCI_TRTYP_SDIO_BYTE (0x4 << 19) // (MCI) SDIO Byte transfer type
#define AT91C_MCI_TRTYP_SDIO_BLOCK (0x5 << 19) // (MCI) SDIO Block transfer type
#define AT91C_MCI_IOSPCMD (0x3 << 24) // (MCI) SDIO Special Command
#define AT91C_MCI_IOSPCMD_NONE (0x0 << 24) // (MCI) NOT a special command
#define AT91C_MCI_IOSPCMD_SUSPEND (0x1 << 24) // (MCI) SDIO Suspend Command
#define AT91C_MCI_IOSPCMD_RESUME (0x2 << 24) // (MCI) SDIO Resume Command
// -------- MCI_BLKR : (MCI Offset: 0x18) MCI Block Register --------
#define AT91C_MCI_BCNT (0xFFFF << 0) // (MCI) MMC/SDIO Block Count / SDIO Byte Count
// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register --------
#define AT91C_MCI_CMDRDY (0x1 << 0) // (MCI) Command Ready flag
#define AT91C_MCI_RXRDY (0x1 << 1) // (MCI) RX Ready flag
#define AT91C_MCI_TXRDY (0x1 << 2) // (MCI) TX Ready flag
#define AT91C_MCI_BLKE (0x1 << 3) // (MCI) Data Block Transfer Ended flag
#define AT91C_MCI_DTIP (0x1 << 4) // (MCI) Data Transfer in Progress flag
#define AT91C_MCI_NOTBUSY (0x1 << 5) // (MCI) Data Line Not Busy flag
#define AT91C_MCI_ENDRX (0x1 << 6) // (MCI) End of RX Buffer flag
#define AT91C_MCI_ENDTX (0x1 << 7) // (MCI) End of TX Buffer flag
#define AT91C_MCI_SDIOIRQA (0x1 << 8) // (MCI) SDIO Interrupt for Slot A
#define AT91C_MCI_SDIOIRQB (0x1 << 9) // (MCI) SDIO Interrupt for Slot B
#define AT91C_MCI_SDIOIRQC (0x1 << 10) // (MCI) SDIO Interrupt for Slot C
#define AT91C_MCI_SDIOIRQD (0x1 << 11) // (MCI) SDIO Interrupt for Slot D
#define AT91C_MCI_RXBUFF (0x1 << 14) // (MCI) RX Buffer Full flag
#define AT91C_MCI_TXBUFE (0x1 << 15) // (MCI) TX Buffer Empty flag
#define AT91C_MCI_RINDE (0x1 << 16) // (MCI) Response Index Error flag
#define AT91C_MCI_RDIRE (0x1 << 17) // (MCI) Response Direction Error flag
#define AT91C_MCI_RCRCE (0x1 << 18) // (MCI) Response CRC Error flag
#define AT91C_MCI_RENDE (0x1 << 19) // (MCI) Response End Bit Error flag
#define AT91C_MCI_RTOE (0x1 << 20) // (MCI) Response Time-out Error flag
#define AT91C_MCI_DCRCE (0x1 << 21) // (MCI) data CRC Error flag
#define AT91C_MCI_DTOE (0x1 << 22) // (MCI) Data timeout Error flag
#define AT91C_MCI_OVRE (0x1 << 30) // (MCI) Overrun flag
#define AT91C_MCI_UNRE (0x1 << 31) // (MCI) Underrun flag
// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register --------
// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register --------
// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Two-wire Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_TWI {
AT91_REG TWI_CR; // Control Register
AT91_REG TWI_MMR; // Master Mode Register
AT91_REG TWI_SMR; // Slave Mode Register
AT91_REG TWI_IADR; // Internal Address Register
AT91_REG TWI_CWGR; // Clock Waveform Generator Register
AT91_REG Reserved0[3]; //
AT91_REG TWI_SR; // Status Register
AT91_REG TWI_IER; // Interrupt Enable Register
AT91_REG TWI_IDR; // Interrupt Disable Register
AT91_REG TWI_IMR; // Interrupt Mask Register
AT91_REG TWI_RHR; // Receive Holding Register
AT91_REG TWI_THR; // Transmit Holding Register
AT91_REG Reserved1[50]; //
AT91_REG TWI_RPR; // Receive Pointer Register
AT91_REG TWI_RCR; // Receive Counter Register
AT91_REG TWI_TPR; // Transmit Pointer Register
AT91_REG TWI_TCR; // Transmit Counter Register
AT91_REG TWI_RNPR; // Receive Next Pointer Register
AT91_REG TWI_RNCR; // Receive Next Counter Register
AT91_REG TWI_TNPR; // Transmit Next Pointer Register
AT91_REG TWI_TNCR; // Transmit Next Counter Register
AT91_REG TWI_PTCR; // PDC Transfer Control Register
AT91_REG TWI_PTSR; // PDC Transfer Status Register
} AT91S_TWI, *AT91PS_TWI;
#else
#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register
#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register
#define TWI_SMR (AT91_CAST(AT91_REG *) 0x00000008) // (TWI_SMR) Slave Mode Register
#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register
#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register
#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register
#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register
#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register
#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register
#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register
#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register
#endif
// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition
#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition
#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled
#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled
#define AT91C_TWI_SVEN (0x1 << 4) // (TWI) TWI Slave mode Enabled
#define AT91C_TWI_SVDIS (0x1 << 5) // (TWI) TWI Slave mode Disabled
#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset
// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size
#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address
#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address
#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address
#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address
#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction
#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address
// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register --------
#define AT91C_TWI_SADR (0x7F << 16) // (TWI) Slave Address
// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider
#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider
#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider
// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
#define AT91C_TWI_TXCOMP_SLAVE (0x1 << 0) // (TWI) Transmission Completed
#define AT91C_TWI_TXCOMP_MASTER (0x1 << 0) // (TWI) Transmission Completed
#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY
#define AT91C_TWI_TXRDY_MASTER (0x1 << 2) // (TWI) Transmit holding register ReaDY
#define AT91C_TWI_TXRDY_SLAVE (0x1 << 2) // (TWI) Transmit holding register ReaDY
#define AT91C_TWI_SVREAD (0x1 << 3) // (TWI) Slave READ (used only in Slave mode)
#define AT91C_TWI_SVACC (0x1 << 4) // (TWI) Slave ACCess (used only in Slave mode)
#define AT91C_TWI_GACC (0x1 << 5) // (TWI) General Call ACcess (used only in Slave mode)
#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error (used only in Master and Multi-master mode)
#define AT91C_TWI_NACK_SLAVE (0x1 << 8) // (TWI) Not Acknowledged
#define AT91C_TWI_NACK_MASTER (0x1 << 8) // (TWI) Not Acknowledged
#define AT91C_TWI_ARBLST_MULTI_MASTER (0x1 << 9) // (TWI) Arbitration Lost (used only in Multimaster mode)
#define AT91C_TWI_SCLWS (0x1 << 10) // (TWI) Clock Wait State (used only in Slave mode)
#define AT91C_TWI_EOSACC (0x1 << 11) // (TWI) End Of Slave ACCess (used only in Slave mode)
#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) End of Receiver Transfer
#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) End of Receiver Transfer
#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) RXBUFF Interrupt
#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) TXBUFE Interrupt
// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Usart
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_USART {
AT91_REG US_CR; // Control Register
AT91_REG US_MR; // Mode Register
AT91_REG US_IER; // Interrupt Enable Register
AT91_REG US_IDR; // Interrupt Disable Register
AT91_REG US_IMR; // Interrupt Mask Register
AT91_REG US_CSR; // Channel Status Register
AT91_REG US_RHR; // Receiver Holding Register
AT91_REG US_THR; // Transmitter Holding Register
AT91_REG US_BRGR; // Baud Rate Generator Register
AT91_REG US_RTOR; // Receiver Time-out Register
AT91_REG US_TTGR; // Transmitter Time-guard Register
AT91_REG Reserved0[5]; //
AT91_REG US_FIDI; // FI_DI_Ratio Register
AT91_REG US_NER; // Nb Errors Register
AT91_REG Reserved1[1]; //
AT91_REG US_IF; // IRDA_FILTER Register
AT91_REG Reserved2[44]; //
AT91_REG US_RPR; // Receive Pointer Register
AT91_REG US_RCR; // Receive Counter Register
AT91_REG US_TPR; // Transmit Pointer Register
AT91_REG US_TCR; // Transmit Counter Register
AT91_REG US_RNPR; // Receive Next Pointer Register
AT91_REG US_RNCR; // Receive Next Counter Register
AT91_REG US_TNPR; // Transmit Next Pointer Register
AT91_REG US_TNCR; // Transmit Next Counter Register
AT91_REG US_PTCR; // PDC Transfer Control Register
AT91_REG US_PTSR; // PDC Transfer Status Register
} AT91S_USART, *AT91PS_USART;
#else
#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register
#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register
#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register
#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register
#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register
#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register
#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register
#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register
#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register
#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register
#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register
#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register
#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register
#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register
#endif
// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break
#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break
#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out
#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address
#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations
#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge
#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out
#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable
#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable
#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable
#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable
// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode
#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal
#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485
#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking
#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem
#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0
#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1
#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA
#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking
#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock
#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1
#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)
#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)
#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits
#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits
#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits
#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits
#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select
#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits
#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit
#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits
#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order
#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length
#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select
#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode
#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge
#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK
#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions
#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter
// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break
#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out
#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached
#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge
#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag
#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag
#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag
#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag
// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input
#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input
#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input
#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_SSC {
AT91_REG SSC_CR; // Control Register
AT91_REG SSC_CMR; // Clock Mode Register
AT91_REG Reserved0[2]; //
AT91_REG SSC_RCMR; // Receive Clock ModeRegister
AT91_REG SSC_RFMR; // Receive Frame Mode Register
AT91_REG SSC_TCMR; // Transmit Clock Mode Register
AT91_REG SSC_TFMR; // Transmit Frame Mode Register
AT91_REG SSC_RHR; // Receive Holding Register
AT91_REG SSC_THR; // Transmit Holding Register
AT91_REG Reserved1[2]; //
AT91_REG SSC_RSHR; // Receive Sync Holding Register
AT91_REG SSC_TSHR; // Transmit Sync Holding Register
AT91_REG Reserved2[2]; //
AT91_REG SSC_SR; // Status Register
AT91_REG SSC_IER; // Interrupt Enable Register
AT91_REG SSC_IDR; // Interrupt Disable Register
AT91_REG SSC_IMR; // Interrupt Mask Register
AT91_REG Reserved3[44]; //
AT91_REG SSC_RPR; // Receive Pointer Register
AT91_REG SSC_RCR; // Receive Counter Register
AT91_REG SSC_TPR; // Transmit Pointer Register
AT91_REG SSC_TCR; // Transmit Counter Register
AT91_REG SSC_RNPR; // Receive Next Pointer Register
AT91_REG SSC_RNCR; // Receive Next Counter Register
AT91_REG SSC_TNPR; // Transmit Next Pointer Register
AT91_REG SSC_TNCR; // Transmit Next Counter Register
AT91_REG SSC_PTCR; // PDC Transfer Control Register
AT91_REG SSC_PTSR; // PDC Transfer Status Register
} AT91S_SSC, *AT91PS_SSC;
#else
#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register
#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register
#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister
#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register
#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register
#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register
#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register
#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register
#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register
#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register
#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register
#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register
#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register
#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register
#endif
// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable
#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable
#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable
#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable
#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset
// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection
#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock
#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal
#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin
#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection
#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start
#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input
#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input
#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input
#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input
#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input
#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input
#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0
#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay
#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length
#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode
#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First
#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame
#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection
// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value
#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable
// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready
#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty
#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission
#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty
#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready
#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun
#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception
#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full
#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync
#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync
#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable
#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable
// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Serial Parallel Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_SPI {
AT91_REG SPI_CR; // Control Register
AT91_REG SPI_MR; // Mode Register
AT91_REG SPI_RDR; // Receive Data Register
AT91_REG SPI_TDR; // Transmit Data Register
AT91_REG SPI_SR; // Status Register
AT91_REG SPI_IER; // Interrupt Enable Register
AT91_REG SPI_IDR; // Interrupt Disable Register
AT91_REG SPI_IMR; // Interrupt Mask Register
AT91_REG Reserved0[4]; //
AT91_REG SPI_CSR[4]; // Chip Select Register
AT91_REG Reserved1[48]; //
AT91_REG SPI_RPR; // Receive Pointer Register
AT91_REG SPI_RCR; // Receive Counter Register
AT91_REG SPI_TPR; // Transmit Pointer Register
AT91_REG SPI_TCR; // Transmit Counter Register
AT91_REG SPI_RNPR; // Receive Next Pointer Register
AT91_REG SPI_RNCR; // Receive Next Counter Register
AT91_REG SPI_TNPR; // Transmit Next Pointer Register
AT91_REG SPI_TNCR; // Transmit Next Counter Register
AT91_REG SPI_PTCR; // PDC Transfer Control Register
AT91_REG SPI_PTSR; // PDC Transfer Status Register
} AT91S_SPI, *AT91PS_SPI;
#else
#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register
#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register
#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register
#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register
#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register
#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register
#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register
#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register
#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register
#endif
// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable
#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable
#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset
#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer
// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode
#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select
#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select
#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select
#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode
#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection
#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection
#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection
#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select
#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects
// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data
#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data
#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full
#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty
#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error
#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status
#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer
#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer
#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt
#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt
#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt
#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt
#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status
// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity
#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase
#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer
#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer
#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer
#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer
#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer
#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer
#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer
#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer
#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer
#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer
#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer
#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate
#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK
#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_ADC {
AT91_REG ADC_CR; // ADC Control Register
AT91_REG ADC_MR; // ADC Mode Register
AT91_REG Reserved0[2]; //
AT91_REG ADC_CHER; // ADC Channel Enable Register
AT91_REG ADC_CHDR; // ADC Channel Disable Register
AT91_REG ADC_CHSR; // ADC Channel Status Register
AT91_REG ADC_SR; // ADC Status Register
AT91_REG ADC_LCDR; // ADC Last Converted Data Register
AT91_REG ADC_IER; // ADC Interrupt Enable Register
AT91_REG ADC_IDR; // ADC Interrupt Disable Register
AT91_REG ADC_IMR; // ADC Interrupt Mask Register
AT91_REG ADC_CDR0; // ADC Channel Data Register 0
AT91_REG ADC_CDR1; // ADC Channel Data Register 1
AT91_REG ADC_CDR2; // ADC Channel Data Register 2
AT91_REG ADC_CDR3; // ADC Channel Data Register 3
AT91_REG ADC_CDR4; // ADC Channel Data Register 4
AT91_REG ADC_CDR5; // ADC Channel Data Register 5
AT91_REG ADC_CDR6; // ADC Channel Data Register 6
AT91_REG ADC_CDR7; // ADC Channel Data Register 7
AT91_REG Reserved1[44]; //
AT91_REG ADC_RPR; // Receive Pointer Register
AT91_REG ADC_RCR; // Receive Counter Register
AT91_REG ADC_TPR; // Transmit Pointer Register
AT91_REG ADC_TCR; // Transmit Counter Register
AT91_REG ADC_RNPR; // Receive Next Pointer Register
AT91_REG ADC_RNCR; // Receive Next Counter Register
AT91_REG ADC_TNPR; // Transmit Next Pointer Register
AT91_REG ADC_TNCR; // Transmit Next Counter Register
AT91_REG ADC_PTCR; // PDC Transfer Control Register
AT91_REG ADC_PTSR; // PDC Transfer Status Register
} AT91S_ADC, *AT91PS_ADC;
#else
#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register
#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register
#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register
#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register
#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register
#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register
#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register
#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register
#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register
#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register
#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0
#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1
#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2
#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3
#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4
#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5
#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6
#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7
#endif
// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset
#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion
// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable
#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection
#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.
#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution
#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution
#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode
#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode
#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode
#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection
#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time
#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time
// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0
#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1
#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2
#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3
#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4
#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5
#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6
#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7
// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion
#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion
#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion
#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion
#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion
#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion
#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion
#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion
#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error
#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error
#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error
#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error
#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error
#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error
#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error
#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error
#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready
#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun
#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer
#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt
// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted
// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data
// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_EMAC {
AT91_REG EMAC_NCR; // Network Control Register
AT91_REG EMAC_NCFGR; // Network Configuration Register
AT91_REG EMAC_NSR; // Network Status Register
AT91_REG Reserved0[2]; //
AT91_REG EMAC_TSR; // Transmit Status Register
AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer
AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer
AT91_REG EMAC_RSR; // Receive Status Register
AT91_REG EMAC_ISR; // Interrupt Status Register
AT91_REG EMAC_IER; // Interrupt Enable Register
AT91_REG EMAC_IDR; // Interrupt Disable Register
AT91_REG EMAC_IMR; // Interrupt Mask Register
AT91_REG EMAC_MAN; // PHY Maintenance Register
AT91_REG EMAC_PTR; // Pause Time Register
AT91_REG EMAC_PFR; // Pause Frames received Register
AT91_REG EMAC_FTO; // Frames Transmitted OK Register
AT91_REG EMAC_SCF; // Single Collision Frame Register
AT91_REG EMAC_MCF; // Multiple Collision Frame Register
AT91_REG EMAC_FRO; // Frames Received OK Register
AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register
AT91_REG EMAC_ALE; // Alignment Error Register
AT91_REG EMAC_DTF; // Deferred Transmission Frame Register
AT91_REG EMAC_LCOL; // Late Collision Register
AT91_REG EMAC_ECOL; // Excessive Collision Register
AT91_REG EMAC_TUND; // Transmit Underrun Error Register
AT91_REG EMAC_CSE; // Carrier Sense Error Register
AT91_REG EMAC_RRE; // Receive Ressource Error Register
AT91_REG EMAC_ROV; // Receive Overrun Errors Register
AT91_REG EMAC_RSE; // Receive Symbol Errors Register
AT91_REG EMAC_ELE; // Excessive Length Errors Register
AT91_REG EMAC_RJA; // Receive Jabbers Register
AT91_REG EMAC_USF; // Undersize Frames Register
AT91_REG EMAC_STE; // SQE Test Error Register
AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register
AT91_REG EMAC_TPF; // Transmitted Pause Frames Register
AT91_REG EMAC_HRB; // Hash Address Bottom[31:0]
AT91_REG EMAC_HRT; // Hash Address Top[63:32]
AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes
AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes
AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes
AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes
AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes
AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes
AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes
AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes
AT91_REG EMAC_TID; // Type ID Checking Register
AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register
AT91_REG EMAC_USRIO; // USER Input/Output Register
AT91_REG EMAC_WOL; // Wake On LAN Register
AT91_REG Reserved1[13]; //
AT91_REG EMAC_REV; // Revision Register
} AT91S_EMAC, *AT91PS_EMAC;
#else
#define EMAC_NCR (AT91_CAST(AT91_REG *) 0x00000000) // (EMAC_NCR) Network Control Register
#define EMAC_NCFGR (AT91_CAST(AT91_REG *) 0x00000004) // (EMAC_NCFGR) Network Configuration Register
#define EMAC_NSR (AT91_CAST(AT91_REG *) 0x00000008) // (EMAC_NSR) Network Status Register
#define EMAC_TSR (AT91_CAST(AT91_REG *) 0x00000014) // (EMAC_TSR) Transmit Status Register
#define EMAC_RBQP (AT91_CAST(AT91_REG *) 0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer
#define EMAC_TBQP (AT91_CAST(AT91_REG *) 0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer
#define EMAC_RSR (AT91_CAST(AT91_REG *) 0x00000020) // (EMAC_RSR) Receive Status Register
#define EMAC_ISR (AT91_CAST(AT91_REG *) 0x00000024) // (EMAC_ISR) Interrupt Status Register
#define EMAC_IER (AT91_CAST(AT91_REG *) 0x00000028) // (EMAC_IER) Interrupt Enable Register
#define EMAC_IDR (AT91_CAST(AT91_REG *) 0x0000002C) // (EMAC_IDR) Interrupt Disable Register
#define EMAC_IMR (AT91_CAST(AT91_REG *) 0x00000030) // (EMAC_IMR) Interrupt Mask Register
#define EMAC_MAN (AT91_CAST(AT91_REG *) 0x00000034) // (EMAC_MAN) PHY Maintenance Register
#define EMAC_PTR (AT91_CAST(AT91_REG *) 0x00000038) // (EMAC_PTR) Pause Time Register
#define EMAC_PFR (AT91_CAST(AT91_REG *) 0x0000003C) // (EMAC_PFR) Pause Frames received Register
#define EMAC_FTO (AT91_CAST(AT91_REG *) 0x00000040) // (EMAC_FTO) Frames Transmitted OK Register
#define EMAC_SCF (AT91_CAST(AT91_REG *) 0x00000044) // (EMAC_SCF) Single Collision Frame Register
#define EMAC_MCF (AT91_CAST(AT91_REG *) 0x00000048) // (EMAC_MCF) Multiple Collision Frame Register
#define EMAC_FRO (AT91_CAST(AT91_REG *) 0x0000004C) // (EMAC_FRO) Frames Received OK Register
#define EMAC_FCSE (AT91_CAST(AT91_REG *) 0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register
#define EMAC_ALE (AT91_CAST(AT91_REG *) 0x00000054) // (EMAC_ALE) Alignment Error Register
#define EMAC_DTF (AT91_CAST(AT91_REG *) 0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register
#define EMAC_LCOL (AT91_CAST(AT91_REG *) 0x0000005C) // (EMAC_LCOL) Late Collision Register
#define EMAC_ECOL (AT91_CAST(AT91_REG *) 0x00000060) // (EMAC_ECOL) Excessive Collision Register
#define EMAC_TUND (AT91_CAST(AT91_REG *) 0x00000064) // (EMAC_TUND) Transmit Underrun Error Register
#define EMAC_CSE (AT91_CAST(AT91_REG *) 0x00000068) // (EMAC_CSE) Carrier Sense Error Register
#define EMAC_RRE (AT91_CAST(AT91_REG *) 0x0000006C) // (EMAC_RRE) Receive Ressource Error Register
#define EMAC_ROV (AT91_CAST(AT91_REG *) 0x00000070) // (EMAC_ROV) Receive Overrun Errors Register
#define EMAC_RSE (AT91_CAST(AT91_REG *) 0x00000074) // (EMAC_RSE) Receive Symbol Errors Register
#define EMAC_ELE (AT91_CAST(AT91_REG *) 0x00000078) // (EMAC_ELE) Excessive Length Errors Register
#define EMAC_RJA (AT91_CAST(AT91_REG *) 0x0000007C) // (EMAC_RJA) Receive Jabbers Register
#define EMAC_USF (AT91_CAST(AT91_REG *) 0x00000080) // (EMAC_USF) Undersize Frames Register
#define EMAC_STE (AT91_CAST(AT91_REG *) 0x00000084) // (EMAC_STE) SQE Test Error Register
#define EMAC_RLE (AT91_CAST(AT91_REG *) 0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register
#define EMAC_TPF (AT91_CAST(AT91_REG *) 0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register
#define EMAC_HRB (AT91_CAST(AT91_REG *) 0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0]
#define EMAC_HRT (AT91_CAST(AT91_REG *) 0x00000094) // (EMAC_HRT) Hash Address Top[63:32]
#define EMAC_SA1L (AT91_CAST(AT91_REG *) 0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes
#define EMAC_SA1H (AT91_CAST(AT91_REG *) 0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes
#define EMAC_SA2L (AT91_CAST(AT91_REG *) 0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes
#define EMAC_SA2H (AT91_CAST(AT91_REG *) 0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes
#define EMAC_SA3L (AT91_CAST(AT91_REG *) 0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes
#define EMAC_SA3H (AT91_CAST(AT91_REG *) 0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes
#define EMAC_SA4L (AT91_CAST(AT91_REG *) 0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes
#define EMAC_SA4H (AT91_CAST(AT91_REG *) 0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes
#define EMAC_TID (AT91_CAST(AT91_REG *) 0x000000B8) // (EMAC_TID) Type ID Checking Register
#define EMAC_TPQ (AT91_CAST(AT91_REG *) 0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register
#define EMAC_USRIO (AT91_CAST(AT91_REG *) 0x000000C0) // (EMAC_USRIO) USER Input/Output Register
#define EMAC_WOL (AT91_CAST(AT91_REG *) 0x000000C4) // (EMAC_WOL) Wake On LAN Register
#define EMAC_REV (AT91_CAST(AT91_REG *) 0x000000FC) // (EMAC_REV) Revision Register
#endif
// -------- EMAC_NCR : (EMAC Offset: 0x0) --------
#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local.
#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable.
#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable.
#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable.
#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers.
#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers.
#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers.
#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure.
#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission.
#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt.
#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame
#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame
// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed.
#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex.
#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames.
#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames.
#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast.
#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable
#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable.
#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes.
#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable.
#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC)
#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8
#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16
#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32
#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64
#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC)
#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC)
#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC)
#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer
#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer
#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable
#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS
#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC)
#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS
// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC)
#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC)
#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC)
// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC)
#define AT91C_EMAC_COL (0x1 << 1) // (EMAC)
#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC)
#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go
#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame
#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC)
#define AT91C_EMAC_UND (0x1 << 6) // (EMAC)
// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC)
#define AT91C_EMAC_REC (0x1 << 1) // (EMAC)
#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC)
// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC)
#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC)
#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC)
#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC)
#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC)
#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC)
#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC)
#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC)
#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC)
#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC)
#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC)
#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC)
#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC)
// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC)
#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC)
#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC)
#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC)
#define AT91C_EMAC_RW (0x3 << 28) // (EMAC)
#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC)
// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII
#define AT91C_EMAC_CLKEN (0x1 << 1) // (EMAC) Clock Enable
// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address
#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable
#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable
#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable
// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC)
#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC)
// *****************************************************************************
// SOFTWARE API DEFINITION FOR USB Device Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_UDP {
AT91_REG UDP_NUM; // Frame Number Register
AT91_REG UDP_GLBSTATE; // Global State Register
AT91_REG UDP_FADDR; // Function Address Register
AT91_REG Reserved0[1]; //
AT91_REG UDP_IER; // Interrupt Enable Register
AT91_REG UDP_IDR; // Interrupt Disable Register
AT91_REG UDP_IMR; // Interrupt Mask Register
AT91_REG UDP_ISR; // Interrupt Status Register
AT91_REG UDP_ICR; // Interrupt Clear Register
AT91_REG Reserved1[1]; //
AT91_REG UDP_RSTEP; // Reset Endpoint Register
AT91_REG Reserved2[1]; //
AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register
AT91_REG Reserved3[2]; //
AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register
AT91_REG Reserved4[3]; //
AT91_REG UDP_TXVC; // Transceiver Control Register
} AT91S_UDP, *AT91PS_UDP;
#else
#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register
#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register
#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register
#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register
#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register
#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register
#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register
#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register
#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register
#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register
#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register
#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register
#endif
// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error
#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK
// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable
#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured
#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume
#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable
// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value
#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable
// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt
#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt
#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt
#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt
#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt
#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt
#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt
#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt
#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt
#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt
#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt
// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0
#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1
#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2
#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3
#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4
#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5
// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0
#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints)
#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready
#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction
#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type
#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control
#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT
#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT
#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT
#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN
#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN
#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN
#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle
#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable
#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP)
#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON
// *****************************************************************************
// SOFTWARE API DEFINITION FOR USB Host Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_UHP {
AT91_REG UHP_HcRevision; // Revision
AT91_REG UHP_HcControl; // Operating modes for the Host Controller
AT91_REG UHP_HcCommandStatus; // Command & status Register
AT91_REG UHP_HcInterruptStatus; // Interrupt Status Register
AT91_REG UHP_HcInterruptEnable; // Interrupt Enable Register
AT91_REG UHP_HcInterruptDisable; // Interrupt Disable Register
AT91_REG UHP_HcHCCA; // Pointer to the Host Controller Communication Area
AT91_REG UHP_HcPeriodCurrentED; // Current Isochronous or Interrupt Endpoint Descriptor
AT91_REG UHP_HcControlHeadED; // First Endpoint Descriptor of the Control list
AT91_REG UHP_HcControlCurrentED; // Endpoint Control and Status Register
AT91_REG UHP_HcBulkHeadED; // First endpoint register of the Bulk list
AT91_REG UHP_HcBulkCurrentED; // Current endpoint of the Bulk list
AT91_REG UHP_HcBulkDoneHead; // Last completed transfer descriptor
AT91_REG UHP_HcFmInterval; // Bit time between 2 consecutive SOFs
AT91_REG UHP_HcFmRemaining; // Bit time remaining in the current Frame
AT91_REG UHP_HcFmNumber; // Frame number
AT91_REG UHP_HcPeriodicStart; // Periodic Start
AT91_REG UHP_HcLSThreshold; // LS Threshold
AT91_REG UHP_HcRhDescriptorA; // Root Hub characteristics A
AT91_REG UHP_HcRhDescriptorB; // Root Hub characteristics B
AT91_REG UHP_HcRhStatus; // Root Hub Status register
AT91_REG UHP_HcRhPortStatus[2]; // Root Hub Port Status Register
} AT91S_UHP, *AT91PS_UHP;
#else
#define HcRevision (AT91_CAST(AT91_REG *) 0x00000000) // (HcRevision) Revision
#define HcControl (AT91_CAST(AT91_REG *) 0x00000004) // (HcControl) Operating modes for the Host Controller
#define HcCommandStatus (AT91_CAST(AT91_REG *) 0x00000008) // (HcCommandStatus) Command & status Register
#define HcInterruptStatus (AT91_CAST(AT91_REG *) 0x0000000C) // (HcInterruptStatus) Interrupt Status Register
#define HcInterruptEnable (AT91_CAST(AT91_REG *) 0x00000010) // (HcInterruptEnable) Interrupt Enable Register
#define HcInterruptDisable (AT91_CAST(AT91_REG *) 0x00000014) // (HcInterruptDisable) Interrupt Disable Register
#define HcHCCA (AT91_CAST(AT91_REG *) 0x00000018) // (HcHCCA) Pointer to the Host Controller Communication Area
#define HcPeriodCurrentED (AT91_CAST(AT91_REG *) 0x0000001C) // (HcPeriodCurrentED) Current Isochronous or Interrupt Endpoint Descriptor
#define HcControlHeadED (AT91_CAST(AT91_REG *) 0x00000020) // (HcControlHeadED) First Endpoint Descriptor of the Control list
#define HcControlCurrentED (AT91_CAST(AT91_REG *) 0x00000024) // (HcControlCurrentED) Endpoint Control and Status Register
#define HcBulkHeadED (AT91_CAST(AT91_REG *) 0x00000028) // (HcBulkHeadED) First endpoint register of the Bulk list
#define HcBulkCurrentED (AT91_CAST(AT91_REG *) 0x0000002C) // (HcBulkCurrentED) Current endpoint of the Bulk list
#define HcBulkDoneHead (AT91_CAST(AT91_REG *) 0x00000030) // (HcBulkDoneHead) Last completed transfer descriptor
#define HcFmInterval (AT91_CAST(AT91_REG *) 0x00000034) // (HcFmInterval) Bit time between 2 consecutive SOFs
#define HcFmRemaining (AT91_CAST(AT91_REG *) 0x00000038) // (HcFmRemaining) Bit time remaining in the current Frame
#define HcFmNumber (AT91_CAST(AT91_REG *) 0x0000003C) // (HcFmNumber) Frame number
#define HcPeriodicStart (AT91_CAST(AT91_REG *) 0x00000040) // (HcPeriodicStart) Periodic Start
#define HcLSThreshold (AT91_CAST(AT91_REG *) 0x00000044) // (HcLSThreshold) LS Threshold
#define HcRhDescriptorA (AT91_CAST(AT91_REG *) 0x00000048) // (HcRhDescriptorA) Root Hub characteristics A
#define HcRhDescriptorB (AT91_CAST(AT91_REG *) 0x0000004C) // (HcRhDescriptorB) Root Hub characteristics B
#define HcRhStatus (AT91_CAST(AT91_REG *) 0x00000050) // (HcRhStatus) Root Hub Status register
#define HcRhPortStatus (AT91_CAST(AT91_REG *) 0x00000054) // (HcRhPortStatus) Root Hub Port Status Register
#endif
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Image Sensor Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_ISI {
AT91_REG ISI_CR1; // Control Register 1
AT91_REG ISI_CR2; // Control Register 2
AT91_REG ISI_SR; // Status Register
AT91_REG ISI_IER; // Interrupt Enable Register
AT91_REG ISI_IDR; // Interrupt Disable Register
AT91_REG ISI_IMR; // Interrupt Mask Register
AT91_REG Reserved0[2]; //
AT91_REG ISI_PSIZE; // Preview Size Register
AT91_REG ISI_PDECF; // Preview Decimation Factor Register
AT91_REG ISI_PFBD; // Preview Frame Buffer Address Register
AT91_REG ISI_CDBA; // Codec Dma Address Register
AT91_REG ISI_Y2RSET0; // Color Space Conversion Register
AT91_REG ISI_Y2RSET1; // Color Space Conversion Register
AT91_REG ISI_R2YSET0; // Color Space Conversion Register
AT91_REG ISI_R2YSET1; // Color Space Conversion Register
AT91_REG ISI_R2YSET2; // Color Space Conversion Register
} AT91S_ISI, *AT91PS_ISI;
#else
#define ISI_CR1 (AT91_CAST(AT91_REG *) 0x00000000) // (ISI_CR1) Control Register 1
#define ISI_CR2 (AT91_CAST(AT91_REG *) 0x00000004) // (ISI_CR2) Control Register 2
#define ISI_SR (AT91_CAST(AT91_REG *) 0x00000008) // (ISI_SR) Status Register
#define ISI_IER (AT91_CAST(AT91_REG *) 0x0000000C) // (ISI_IER) Interrupt Enable Register
#define ISI_IDR (AT91_CAST(AT91_REG *) 0x00000010) // (ISI_IDR) Interrupt Disable Register
#define ISI_IMR (AT91_CAST(AT91_REG *) 0x00000014) // (ISI_IMR) Interrupt Mask Register
#define ISI_PSIZE (AT91_CAST(AT91_REG *) 0x00000020) // (ISI_PSIZE) Preview Size Register
#define ISI_PDECF (AT91_CAST(AT91_REG *) 0x00000024) // (ISI_PDECF) Preview Decimation Factor Register
#define ISI_PFBD (AT91_CAST(AT91_REG *) 0x00000028) // (ISI_PFBD) Preview Frame Buffer Address Register
#define ISI_CDBA (AT91_CAST(AT91_REG *) 0x0000002C) // (ISI_CDBA) Codec Dma Address Register
#define ISI_Y2RSET0 (AT91_CAST(AT91_REG *) 0x00000030) // (ISI_Y2RSET0) Color Space Conversion Register
#define ISI_Y2RSET1 (AT91_CAST(AT91_REG *) 0x00000034) // (ISI_Y2RSET1) Color Space Conversion Register
#define ISI_R2YSET0 (AT91_CAST(AT91_REG *) 0x00000038) // (ISI_R2YSET0) Color Space Conversion Register
#define ISI_R2YSET1 (AT91_CAST(AT91_REG *) 0x0000003C) // (ISI_R2YSET1) Color Space Conversion Register
#define ISI_R2YSET2 (AT91_CAST(AT91_REG *) 0x00000040) // (ISI_R2YSET2) Color Space Conversion Register
#endif
// -------- ISI_CR1 : (ISI Offset: 0x0) ISI Control Register 1 --------
#define AT91C_ISI_RST (0x1 << 0) // (ISI) Image sensor interface reset
#define AT91C_ISI_DISABLE (0x1 << 1) // (ISI) image sensor disable.
#define AT91C_ISI_HSYNC_POL (0x1 << 2) // (ISI) Horizontal synchronisation polarity
#define AT91C_ISI_PIXCLK_POL (0x1 << 4) // (ISI) Pixel Clock Polarity
#define AT91C_ISI_EMB_SYNC (0x1 << 6) // (ISI) Embedded synchronisation
#define AT91C_ISI_CRC_SYNC (0x1 << 7) // (ISI) CRC correction
#define AT91C_ISI_FULL (0x1 << 12) // (ISI) Full mode is allowed
#define AT91C_ISI_THMASK (0x3 << 13) // (ISI) DMA Burst Mask
#define AT91C_ISI_THMASK_4_8_16_BURST (0x0 << 13) // (ISI) 4,8 and 16 AHB burst are allowed
#define AT91C_ISI_THMASK_8_16_BURST (0x1 << 13) // (ISI) 8 and 16 AHB burst are allowed
#define AT91C_ISI_THMASK_16_BURST (0x2 << 13) // (ISI) Only 16 AHB burst are allowed
#define AT91C_ISI_CODEC_ON (0x1 << 15) // (ISI) Enable the codec path
#define AT91C_ISI_SLD (0xFF << 16) // (ISI) Start of Line Delay
#define AT91C_ISI_SFD (0xFF << 24) // (ISI) Start of frame Delay
// -------- ISI_CR2 : (ISI Offset: 0x4) ISI Control Register 2 --------
#define AT91C_ISI_IM_VSIZE (0x7FF << 0) // (ISI) Vertical size of the Image sensor [0..2047]
#define AT91C_ISI_GS_MODE (0x1 << 11) // (ISI) Grayscale Memory Mode
#define AT91C_ISI_RGB_MODE (0x3 << 12) // (ISI) RGB mode
#define AT91C_ISI_RGB_MODE_RGB_888 (0x0 << 12) // (ISI) RGB 8:8:8 24 bits
#define AT91C_ISI_RGB_MODE_RGB_565 (0x1 << 12) // (ISI) RGB 5:6:5 16 bits
#define AT91C_ISI_RGB_MODE_RGB_555 (0x2 << 12) // (ISI) RGB 5:5:5 16 bits
#define AT91C_ISI_GRAYSCALE (0x1 << 13) // (ISI) Grayscale Mode
#define AT91C_ISI_RGB_SWAP (0x1 << 14) // (ISI) RGB Swap
#define AT91C_ISI_COL_SPACE (0x1 << 15) // (ISI) Color space for the image data
#define AT91C_ISI_IM_HSIZE (0x7FF << 16) // (ISI) Horizontal size of the Image sensor [0..2047]
#define AT91C_ISI_RGB_MODE_YCC_DEF (0x0 << 28) // (ISI) Cb(i) Y(i) Cr(i) Y(i+1)
#define AT91C_ISI_RGB_MODE_YCC_MOD1 (0x1 << 28) // (ISI) Cr(i) Y(i) Cb(i) Y(i+1)
#define AT91C_ISI_RGB_MODE_YCC_MOD2 (0x2 << 28) // (ISI) Y(i) Cb(i) Y(i+1) Cr(i)
#define AT91C_ISI_RGB_MODE_YCC_MOD3 (0x3 << 28) // (ISI) Y(i) Cr(i) Y(i+1) Cb(i)
#define AT91C_ISI_RGB_CFG (0x3 << 30) // (ISI) RGB configuration
#define AT91C_ISI_RGB_CFG_RGB_DEF (0x0 << 30) // (ISI) R/G(MSB) G(LSB)/B R/G(MSB) G(LSB)/B
#define AT91C_ISI_RGB_CFG_RGB_MOD1 (0x1 << 30) // (ISI) B/G(MSB) G(LSB)/R B/G(MSB) G(LSB)/R
#define AT91C_ISI_RGB_CFG_RGB_MOD2 (0x2 << 30) // (ISI) G(LSB)/R B/G(MSB) G(LSB)/R B/G(MSB)
#define AT91C_ISI_RGB_CFG_RGB_MOD3 (0x3 << 30) // (ISI) G(LSB)/B R/G(MSB) G(LSB)/B R/G(MSB)
// -------- ISI_SR : (ISI Offset: 0x8) ISI Status Register --------
#define AT91C_ISI_SOF (0x1 << 0) // (ISI) Start of Frame
#define AT91C_ISI_DIS (0x1 << 1) // (ISI) Image Sensor Interface disable
#define AT91C_ISI_SOFTRST (0x1 << 2) // (ISI) Software Reset
#define AT91C_ISI_CRC_ERR (0x1 << 4) // (ISI) CRC synchronisation error
#define AT91C_ISI_FO_C_OVF (0x1 << 5) // (ISI) Fifo Codec Overflow
#define AT91C_ISI_FO_P_OVF (0x1 << 6) // (ISI) Fifo Preview Overflow
#define AT91C_ISI_FO_P_EMP (0x1 << 7) // (ISI) Fifo Preview Empty
#define AT91C_ISI_FO_C_EMP (0x1 << 8) // (ISI) Fifo Codec Empty
#define AT91C_ISI_FR_OVR (0x1 << 9) // (ISI) Frame rate overun
// -------- ISI_IER : (ISI Offset: 0xc) ISI Interrupt Enable Register --------
// -------- ISI_IDR : (ISI Offset: 0x10) ISI Interrupt Disable Register --------
// -------- ISI_IMR : (ISI Offset: 0x14) ISI Interrupt Mask Register --------
// -------- ISI_PSIZE : (ISI Offset: 0x20) ISI Preview Register --------
#define AT91C_ISI_PREV_VSIZE (0x3FF << 0) // (ISI) Vertical size for the preview path
#define AT91C_ISI_PREV_HSIZE (0x3FF << 16) // (ISI) Horizontal size for the preview path
// -------- ISI_Y2R_SET0 : (ISI Offset: 0x30) Color Space Conversion YCrCb to RGB Register --------
#define AT91C_ISI_Y2R_C0 (0xFF << 0) // (ISI) Color Space Conversion Matrix Coefficient C0
#define AT91C_ISI_Y2R_C1 (0xFF << 8) // (ISI) Color Space Conversion Matrix Coefficient C1
#define AT91C_ISI_Y2R_C2 (0xFF << 16) // (ISI) Color Space Conversion Matrix Coefficient C2
#define AT91C_ISI_Y2R_C3 (0xFF << 24) // (ISI) Color Space Conversion Matrix Coefficient C3
// -------- ISI_Y2R_SET1 : (ISI Offset: 0x34) ISI Color Space Conversion YCrCb to RGB set 1 Register --------
#define AT91C_ISI_Y2R_C4 (0x1FF << 0) // (ISI) Color Space Conversion Matrix Coefficient C4
#define AT91C_ISI_Y2R_YOFF (0xFF << 12) // (ISI) Color Space Conversion Luninance default offset
#define AT91C_ISI_Y2R_CROFF (0xFF << 13) // (ISI) Color Space Conversion Red Chrominance default offset
#define AT91C_ISI_Y2R_CBFF (0xFF << 14) // (ISI) Color Space Conversion Luninance default offset
// -------- ISI_R2Y_SET0 : (ISI Offset: 0x38) Color Space Conversion RGB to YCrCb set 0 register --------
#define AT91C_ISI_R2Y_C0 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C0
#define AT91C_ISI_R2Y_C1 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C1
#define AT91C_ISI_R2Y_C2 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C2
#define AT91C_ISI_R2Y_ROFF (0x1 << 4) // (ISI) Color Space Conversion Red component offset
// -------- ISI_R2Y_SET1 : (ISI Offset: 0x3c) Color Space Conversion RGB to YCrCb set 1 register --------
#define AT91C_ISI_R2Y_C3 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C3
#define AT91C_ISI_R2Y_C4 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C4
#define AT91C_ISI_R2Y_C5 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C5
#define AT91C_ISI_R2Y_GOFF (0x1 << 4) // (ISI) Color Space Conversion Green component offset
// -------- ISI_R2Y_SET2 : (ISI Offset: 0x40) Color Space Conversion RGB to YCrCb set 2 register --------
#define AT91C_ISI_R2Y_C6 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C6
#define AT91C_ISI_R2Y_C7 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C7
#define AT91C_ISI_R2Y_C8 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C8
#define AT91C_ISI_R2Y_BOFF (0x1 << 4) // (ISI) Color Space Conversion Blue component offset
// *****************************************************************************
// REGISTER ADDRESS DEFINITION FOR AT91SAM9XE256
// *****************************************************************************
// ========== Register definition for SYS peripheral ==========
#define AT91C_SYS_GPBR (AT91_CAST(AT91_REG *) 0xFFFFFFFF) // (SYS) General Purpose Register
// ========== Register definition for EBI peripheral ==========
#define AT91C_EBI_DUMMY (AT91_CAST(AT91_REG *) 0xFFFFEA00) // (EBI) Dummy register - Do not use
// ========== Register definition for HECC peripheral ==========
#define AT91C_HECC_VR (AT91_CAST(AT91_REG *) 0xFFFFE8FC) // (HECC) ECC Version register
#define AT91C_HECC_NPR (AT91_CAST(AT91_REG *) 0xFFFFE810) // (HECC) ECC Parity N register
#define AT91C_HECC_SR (AT91_CAST(AT91_REG *) 0xFFFFE808) // (HECC) ECC Status register
#define AT91C_HECC_PR (AT91_CAST(AT91_REG *) 0xFFFFE80C) // (HECC) ECC Parity register
#define AT91C_HECC_MR (AT91_CAST(AT91_REG *) 0xFFFFE804) // (HECC) ECC Page size register
#define AT91C_HECC_CR (AT91_CAST(AT91_REG *) 0xFFFFE800) // (HECC) ECC reset register
// ========== Register definition for SDRAMC peripheral ==========
#define AT91C_SDRAMC_MR (AT91_CAST(AT91_REG *) 0xFFFFEA00) // (SDRAMC) SDRAM Controller Mode Register
#define AT91C_SDRAMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFEA1C) // (SDRAMC) SDRAM Controller Interrupt Mask Register
#define AT91C_SDRAMC_LPR (AT91_CAST(AT91_REG *) 0xFFFFEA10) // (SDRAMC) SDRAM Controller Low Power Register
#define AT91C_SDRAMC_ISR (AT91_CAST(AT91_REG *) 0xFFFFEA20) // (SDRAMC) SDRAM Controller Interrupt Mask Register
#define AT91C_SDRAMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFEA18) // (SDRAMC) SDRAM Controller Interrupt Disable Register
#define AT91C_SDRAMC_CR (AT91_CAST(AT91_REG *) 0xFFFFEA08) // (SDRAMC) SDRAM Controller Configuration Register
#define AT91C_SDRAMC_TR (AT91_CAST(AT91_REG *) 0xFFFFEA04) // (SDRAMC) SDRAM Controller Refresh Timer Register
#define AT91C_SDRAMC_MDR (AT91_CAST(AT91_REG *) 0xFFFFEA24) // (SDRAMC) SDRAM Memory Device Register
#define AT91C_SDRAMC_HSR (AT91_CAST(AT91_REG *) 0xFFFFEA0C) // (SDRAMC) SDRAM Controller High Speed Register
#define AT91C_SDRAMC_IER (AT91_CAST(AT91_REG *) 0xFFFFEA14) // (SDRAMC) SDRAM Controller Interrupt Enable Register
// ========== Register definition for SMC peripheral ==========
#define AT91C_SMC_CTRL1 (AT91_CAST(AT91_REG *) 0xFFFFEC1C) // (SMC) Control Register for CS 1
#define AT91C_SMC_PULSE7 (AT91_CAST(AT91_REG *) 0xFFFFEC74) // (SMC) Pulse Register for CS 7
#define AT91C_SMC_PULSE6 (AT91_CAST(AT91_REG *) 0xFFFFEC64) // (SMC) Pulse Register for CS 6
#define AT91C_SMC_SETUP4 (AT91_CAST(AT91_REG *) 0xFFFFEC40) // (SMC) Setup Register for CS 4
#define AT91C_SMC_PULSE3 (AT91_CAST(AT91_REG *) 0xFFFFEC34) // (SMC) Pulse Register for CS 3
#define AT91C_SMC_CYCLE5 (AT91_CAST(AT91_REG *) 0xFFFFEC58) // (SMC) Cycle Register for CS 5
#define AT91C_SMC_CYCLE2 (AT91_CAST(AT91_REG *) 0xFFFFEC28) // (SMC) Cycle Register for CS 2
#define AT91C_SMC_CTRL2 (AT91_CAST(AT91_REG *) 0xFFFFEC2C) // (SMC) Control Register for CS 2
#define AT91C_SMC_CTRL0 (AT91_CAST(AT91_REG *) 0xFFFFEC0C) // (SMC) Control Register for CS 0
#define AT91C_SMC_PULSE5 (AT91_CAST(AT91_REG *) 0xFFFFEC54) // (SMC) Pulse Register for CS 5
#define AT91C_SMC_PULSE1 (AT91_CAST(AT91_REG *) 0xFFFFEC14) // (SMC) Pulse Register for CS 1
#define AT91C_SMC_PULSE0 (AT91_CAST(AT91_REG *) 0xFFFFEC04) // (SMC) Pulse Register for CS 0
#define AT91C_SMC_CYCLE7 (AT91_CAST(AT91_REG *) 0xFFFFEC78) // (SMC) Cycle Register for CS 7
#define AT91C_SMC_CTRL4 (AT91_CAST(AT91_REG *) 0xFFFFEC4C) // (SMC) Control Register for CS 4
#define AT91C_SMC_CTRL3 (AT91_CAST(AT91_REG *) 0xFFFFEC3C) // (SMC) Control Register for CS 3
#define AT91C_SMC_SETUP7 (AT91_CAST(AT91_REG *) 0xFFFFEC70) // (SMC) Setup Register for CS 7
#define AT91C_SMC_CTRL7 (AT91_CAST(AT91_REG *) 0xFFFFEC7C) // (SMC) Control Register for CS 7
#define AT91C_SMC_SETUP1 (AT91_CAST(AT91_REG *) 0xFFFFEC10) // (SMC) Setup Register for CS 1
#define AT91C_SMC_CYCLE0 (AT91_CAST(AT91_REG *) 0xFFFFEC08) // (SMC) Cycle Register for CS 0
#define AT91C_SMC_CTRL5 (AT91_CAST(AT91_REG *) 0xFFFFEC5C) // (SMC) Control Register for CS 5
#define AT91C_SMC_CYCLE1 (AT91_CAST(AT91_REG *) 0xFFFFEC18) // (SMC) Cycle Register for CS 1
#define AT91C_SMC_CTRL6 (AT91_CAST(AT91_REG *) 0xFFFFEC6C) // (SMC) Control Register for CS 6
#define AT91C_SMC_SETUP0 (AT91_CAST(AT91_REG *) 0xFFFFEC00) // (SMC) Setup Register for CS 0
#define AT91C_SMC_PULSE4 (AT91_CAST(AT91_REG *) 0xFFFFEC44) // (SMC) Pulse Register for CS 4
#define AT91C_SMC_SETUP5 (AT91_CAST(AT91_REG *) 0xFFFFEC50) // (SMC) Setup Register for CS 5
#define AT91C_SMC_SETUP2 (AT91_CAST(AT91_REG *) 0xFFFFEC20) // (SMC) Setup Register for CS 2
#define AT91C_SMC_CYCLE3 (AT91_CAST(AT91_REG *) 0xFFFFEC38) // (SMC) Cycle Register for CS 3
#define AT91C_SMC_CYCLE6 (AT91_CAST(AT91_REG *) 0xFFFFEC68) // (SMC) Cycle Register for CS 6
#define AT91C_SMC_SETUP6 (AT91_CAST(AT91_REG *) 0xFFFFEC60) // (SMC) Setup Register for CS 6
#define AT91C_SMC_CYCLE4 (AT91_CAST(AT91_REG *) 0xFFFFEC48) // (SMC) Cycle Register for CS 4
#define AT91C_SMC_PULSE2 (AT91_CAST(AT91_REG *) 0xFFFFEC24) // (SMC) Pulse Register for CS 2
#define AT91C_SMC_SETUP3 (AT91_CAST(AT91_REG *) 0xFFFFEC30) // (SMC) Setup Register for CS 3
// ========== Register definition for MATRIX peripheral ==========
#define AT91C_MATRIX_MCFG0 (AT91_CAST(AT91_REG *) 0xFFFFEE00) // (MATRIX) Master Configuration Register 0 (ram96k)
#define AT91C_MATRIX_MCFG7 (AT91_CAST(AT91_REG *) 0xFFFFEE1C) // (MATRIX) Master Configuration Register 7 (teak_prog)
#define AT91C_MATRIX_SCFG1 (AT91_CAST(AT91_REG *) 0xFFFFEE44) // (MATRIX) Slave Configuration Register 1 (rom)
#define AT91C_MATRIX_MCFG4 (AT91_CAST(AT91_REG *) 0xFFFFEE10) // (MATRIX) Master Configuration Register 4 (bridge)
#define AT91C_MATRIX_VERSION (AT91_CAST(AT91_REG *) 0xFFFFEFFC) // (MATRIX) Version Register
#define AT91C_MATRIX_MCFG2 (AT91_CAST(AT91_REG *) 0xFFFFEE08) // (MATRIX) Master Configuration Register 2 (hperiphs)
#define AT91C_MATRIX_PRBS4 (AT91_CAST(AT91_REG *) 0xFFFFEEA4) // (MATRIX) PRBS4 : ebi
#define AT91C_MATRIX_PRBS0 (AT91_CAST(AT91_REG *) 0xFFFFEE84) // (MATRIX) PRBS0 (ram0)
#define AT91C_MATRIX_SCFG3 (AT91_CAST(AT91_REG *) 0xFFFFEE4C) // (MATRIX) Slave Configuration Register 3 (ebi)
#define AT91C_MATRIX_MCFG6 (AT91_CAST(AT91_REG *) 0xFFFFEE18) // (MATRIX) Master Configuration Register 6 (ram16k)
#define AT91C_MATRIX_EBI (AT91_CAST(AT91_REG *) 0xFFFFEF1C) // (MATRIX) Slave 3 (ebi) Special Function Register
#define AT91C_MATRIX_SCFG0 (AT91_CAST(AT91_REG *) 0xFFFFEE40) // (MATRIX) Slave Configuration Register 0 (ram96k)
#define AT91C_MATRIX_PRBS3 (AT91_CAST(AT91_REG *) 0xFFFFEE9C) // (MATRIX) PRBS3 : usb_dev_hs
#define AT91C_MATRIX_PRAS3 (AT91_CAST(AT91_REG *) 0xFFFFEE98) // (MATRIX) PRAS3 : usb_dev_hs
#define AT91C_MATRIX_PRAS0 (AT91_CAST(AT91_REG *) 0xFFFFEE80) // (MATRIX) PRAS0 (ram0)
#define AT91C_MATRIX_MCFG3 (AT91_CAST(AT91_REG *) 0xFFFFEE0C) // (MATRIX) Master Configuration Register 3 (ebi)
#define AT91C_MATRIX_PRAS1 (AT91_CAST(AT91_REG *) 0xFFFFEE88) // (MATRIX) PRAS1 (ram1)
#define AT91C_MATRIX_PRAS2 (AT91_CAST(AT91_REG *) 0xFFFFEE90) // (MATRIX) PRAS2 (ram2)
#define AT91C_MATRIX_SCFG2 (AT91_CAST(AT91_REG *) 0xFFFFEE48) // (MATRIX) Slave Configuration Register 2 (hperiphs)
#define AT91C_MATRIX_MCFG5 (AT91_CAST(AT91_REG *) 0xFFFFEE14) // (MATRIX) Master Configuration Register 5 (mailbox)
#define AT91C_MATRIX_MCFG1 (AT91_CAST(AT91_REG *) 0xFFFFEE04) // (MATRIX) Master Configuration Register 1 (rom)
#define AT91C_MATRIX_PRAS4 (AT91_CAST(AT91_REG *) 0xFFFFEEA0) // (MATRIX) PRAS4 : ebi
#define AT91C_MATRIX_MRCR (AT91_CAST(AT91_REG *) 0xFFFFEF00) // (MATRIX) Master Remp Control Register
#define AT91C_MATRIX_PRBS2 (AT91_CAST(AT91_REG *) 0xFFFFEE94) // (MATRIX) PRBS2 (ram2)
#define AT91C_MATRIX_SCFG4 (AT91_CAST(AT91_REG *) 0xFFFFEE50) // (MATRIX) Slave Configuration Register 4 (bridge)
#define AT91C_MATRIX_TEAKCFG (AT91_CAST(AT91_REG *) 0xFFFFEF2C) // (MATRIX) Slave 7 (teak_prog) Special Function Register
#define AT91C_MATRIX_PRBS1 (AT91_CAST(AT91_REG *) 0xFFFFEE8C) // (MATRIX) PRBS1 (ram1)
// ========== Register definition for CCFG peripheral ==========
#define AT91C_CCFG_MATRIXVERSION (AT91_CAST(AT91_REG *) 0xFFFFEFFC) // (CCFG) Version Register
#define AT91C_CCFG_EBICSA (AT91_CAST(AT91_REG *) 0xFFFFEF1C) // (CCFG) EBI Chip Select Assignement Register
// ========== Register definition for PDC_DBGU peripheral ==========
#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
// ========== Register definition for DBGU peripheral ==========
#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
// ========== Register definition for AIC peripheral ==========
#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
// ========== Register definition for PIOA peripheral ==========
#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
// ========== Register definition for PIOB peripheral ==========
#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register
#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register
#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register
#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register
#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register
#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register
#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register
#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register
#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register
#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register
#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register
#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register
#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register
#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register
#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register
#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register
#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr
#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register
#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register
#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register
#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register
#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register
#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register
#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register
#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register
#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register
#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register
#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register
#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register
// ========== Register definition for PIOC peripheral ==========
#define AT91C_PIOC_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF8A4) // (PIOC) Output Write Disable Register
#define AT91C_PIOC_SODR (AT91_CAST(AT91_REG *) 0xFFFFF830) // (PIOC) Set Output Data Register
#define AT91C_PIOC_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF864) // (PIOC) Pull-up Enable Register
#define AT91C_PIOC_CODR (AT91_CAST(AT91_REG *) 0xFFFFF834) // (PIOC) Clear Output Data Register
#define AT91C_PIOC_PSR (AT91_CAST(AT91_REG *) 0xFFFFF808) // (PIOC) PIO Status Register
#define AT91C_PIOC_PDR (AT91_CAST(AT91_REG *) 0xFFFFF804) // (PIOC) PIO Disable Register
#define AT91C_PIOC_ODR (AT91_CAST(AT91_REG *) 0xFFFFF814) // (PIOC) Output Disable Registerr
#define AT91C_PIOC_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF868) // (PIOC) Pull-up Status Register
#define AT91C_PIOC_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF878) // (PIOC) AB Select Status Register
#define AT91C_PIOC_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF828) // (PIOC) Input Filter Status Register
#define AT91C_PIOC_OER (AT91_CAST(AT91_REG *) 0xFFFFF810) // (PIOC) Output Enable Register
#define AT91C_PIOC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF848) // (PIOC) Interrupt Mask Register
#define AT91C_PIOC_ASR (AT91_CAST(AT91_REG *) 0xFFFFF870) // (PIOC) Select A Register
#define AT91C_PIOC_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF854) // (PIOC) Multi-driver Disable Register
#define AT91C_PIOC_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF8A8) // (PIOC) Output Write Status Register
#define AT91C_PIOC_PER (AT91_CAST(AT91_REG *) 0xFFFFF800) // (PIOC) PIO Enable Register
#define AT91C_PIOC_IDR (AT91_CAST(AT91_REG *) 0xFFFFF844) // (PIOC) Interrupt Disable Register
#define AT91C_PIOC_MDER (AT91_CAST(AT91_REG *) 0xFFFFF850) // (PIOC) Multi-driver Enable Register
#define AT91C_PIOC_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF83C) // (PIOC) Pin Data Status Register
#define AT91C_PIOC_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF858) // (PIOC) Multi-driver Status Register
#define AT91C_PIOC_OWER (AT91_CAST(AT91_REG *) 0xFFFFF8A0) // (PIOC) Output Write Enable Register
#define AT91C_PIOC_BSR (AT91_CAST(AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register
#define AT91C_PIOC_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF860) // (PIOC) Pull-up Disable Register
#define AT91C_PIOC_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF824) // (PIOC) Input Filter Disable Register
#define AT91C_PIOC_IER (AT91_CAST(AT91_REG *) 0xFFFFF840) // (PIOC) Interrupt Enable Register
#define AT91C_PIOC_OSR (AT91_CAST(AT91_REG *) 0xFFFFF818) // (PIOC) Output Status Register
#define AT91C_PIOC_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF838) // (PIOC) Output Data Status Register
#define AT91C_PIOC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF84C) // (PIOC) Interrupt Status Register
#define AT91C_PIOC_IFER (AT91_CAST(AT91_REG *) 0xFFFFF820) // (PIOC) Input Filter Enable Register
// ========== Register definition for EFC peripheral ==========
#define AT91C_EFC_FVR (AT91_CAST(AT91_REG *) 0xFFFFFA10) // (EFC) EFC Flash Version Register
#define AT91C_EFC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFA04) // (EFC) EFC Flash Command Register
#define AT91C_EFC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFA00) // (EFC) EFC Flash Mode Register
#define AT91C_EFC_FRR (AT91_CAST(AT91_REG *) 0xFFFFFA0C) // (EFC) EFC Flash Result Register
#define AT91C_EFC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFA08) // (EFC) EFC Flash Status Register
// ========== Register definition for CKGR peripheral ==========
#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
#define AT91C_CKGR_PLLBR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL B Register
#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
#define AT91C_CKGR_PLLAR (AT91_CAST(AT91_REG *) 0xFFFFFC28) // (CKGR) PLL A Register
// ========== Register definition for PMC peripheral ==========
#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
#define AT91C_PMC_PLLAR (AT91_CAST(AT91_REG *) 0xFFFFFC28) // (PMC) PLL A Register
#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
#define AT91C_PMC_PLLBR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL B Register
#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
// ========== Register definition for RSTC peripheral ==========
#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
// ========== Register definition for SHDWC peripheral ==========
#define AT91C_SHDWC_SHSR (AT91_CAST(AT91_REG *) 0xFFFFFD18) // (SHDWC) Shut Down Status Register
#define AT91C_SHDWC_SHMR (AT91_CAST(AT91_REG *) 0xFFFFFD14) // (SHDWC) Shut Down Mode Register
#define AT91C_SHDWC_SHCR (AT91_CAST(AT91_REG *) 0xFFFFFD10) // (SHDWC) Shut Down Control Register
// ========== Register definition for RTTC peripheral ==========
#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
// ========== Register definition for PITC peripheral ==========
#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
// ========== Register definition for WDTC peripheral ==========
#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
// ========== Register definition for TC0 peripheral ==========
#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register
#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C
#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B
#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A
#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
// ========== Register definition for TC1 peripheral ==========
#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B
#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register
#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A
#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C
#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
// ========== Register definition for TC2 peripheral ==========
#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A
#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B
#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C
#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
// ========== Register definition for TC3 peripheral ==========
#define AT91C_TC3_IER (AT91_CAST(AT91_REG *) 0xFFFDC024) // (TC3) Interrupt Enable Register
#define AT91C_TC3_RB (AT91_CAST(AT91_REG *) 0xFFFDC018) // (TC3) Register B
#define AT91C_TC3_CMR (AT91_CAST(AT91_REG *) 0xFFFDC004) // (TC3) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC3_RC (AT91_CAST(AT91_REG *) 0xFFFDC01C) // (TC3) Register C
#define AT91C_TC3_CCR (AT91_CAST(AT91_REG *) 0xFFFDC000) // (TC3) Channel Control Register
#define AT91C_TC3_SR (AT91_CAST(AT91_REG *) 0xFFFDC020) // (TC3) Status Register
#define AT91C_TC3_CV (AT91_CAST(AT91_REG *) 0xFFFDC010) // (TC3) Counter Value
#define AT91C_TC3_RA (AT91_CAST(AT91_REG *) 0xFFFDC014) // (TC3) Register A
#define AT91C_TC3_IDR (AT91_CAST(AT91_REG *) 0xFFFDC028) // (TC3) Interrupt Disable Register
#define AT91C_TC3_IMR (AT91_CAST(AT91_REG *) 0xFFFDC02C) // (TC3) Interrupt Mask Register
// ========== Register definition for TC4 peripheral ==========
#define AT91C_TC4_CMR (AT91_CAST(AT91_REG *) 0xFFFDC044) // (TC4) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC4_RC (AT91_CAST(AT91_REG *) 0xFFFDC05C) // (TC4) Register C
#define AT91C_TC4_SR (AT91_CAST(AT91_REG *) 0xFFFDC060) // (TC4) Status Register
#define AT91C_TC4_RB (AT91_CAST(AT91_REG *) 0xFFFDC058) // (TC4) Register B
#define AT91C_TC4_IER (AT91_CAST(AT91_REG *) 0xFFFDC064) // (TC4) Interrupt Enable Register
#define AT91C_TC4_CV (AT91_CAST(AT91_REG *) 0xFFFDC050) // (TC4) Counter Value
#define AT91C_TC4_RA (AT91_CAST(AT91_REG *) 0xFFFDC054) // (TC4) Register A
#define AT91C_TC4_IDR (AT91_CAST(AT91_REG *) 0xFFFDC068) // (TC4) Interrupt Disable Register
#define AT91C_TC4_IMR (AT91_CAST(AT91_REG *) 0xFFFDC06C) // (TC4) Interrupt Mask Register
#define AT91C_TC4_CCR (AT91_CAST(AT91_REG *) 0xFFFDC040) // (TC4) Channel Control Register
// ========== Register definition for TC5 peripheral ==========
#define AT91C_TC5_RB (AT91_CAST(AT91_REG *) 0xFFFDC098) // (TC5) Register B
#define AT91C_TC5_RA (AT91_CAST(AT91_REG *) 0xFFFDC094) // (TC5) Register A
#define AT91C_TC5_CV (AT91_CAST(AT91_REG *) 0xFFFDC090) // (TC5) Counter Value
#define AT91C_TC5_CCR (AT91_CAST(AT91_REG *) 0xFFFDC080) // (TC5) Channel Control Register
#define AT91C_TC5_SR (AT91_CAST(AT91_REG *) 0xFFFDC0A0) // (TC5) Status Register
#define AT91C_TC5_IER (AT91_CAST(AT91_REG *) 0xFFFDC0A4) // (TC5) Interrupt Enable Register
#define AT91C_TC5_IDR (AT91_CAST(AT91_REG *) 0xFFFDC0A8) // (TC5) Interrupt Disable Register
#define AT91C_TC5_RC (AT91_CAST(AT91_REG *) 0xFFFDC09C) // (TC5) Register C
#define AT91C_TC5_IMR (AT91_CAST(AT91_REG *) 0xFFFDC0AC) // (TC5) Interrupt Mask Register
#define AT91C_TC5_CMR (AT91_CAST(AT91_REG *) 0xFFFDC084) // (TC5) Channel Mode Register (Capture Mode / Waveform Mode)
// ========== Register definition for TCB0 peripheral ==========
#define AT91C_TCB0_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB0) TC Block Mode Register
#define AT91C_TCB0_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB0) TC Block Control Register
// ========== Register definition for TCB1 peripheral ==========
#define AT91C_TCB1_BCR (AT91_CAST(AT91_REG *) 0xFFFDC0C0) // (TCB1) TC Block Control Register
#define AT91C_TCB1_BMR (AT91_CAST(AT91_REG *) 0xFFFDC0C4) // (TCB1) TC Block Mode Register
// ========== Register definition for PDC_MCI peripheral ==========
#define AT91C_MCI_RNCR (AT91_CAST(AT91_REG *) 0xFFFA8114) // (PDC_MCI) Receive Next Counter Register
#define AT91C_MCI_TCR (AT91_CAST(AT91_REG *) 0xFFFA810C) // (PDC_MCI) Transmit Counter Register
#define AT91C_MCI_RCR (AT91_CAST(AT91_REG *) 0xFFFA8104) // (PDC_MCI) Receive Counter Register
#define AT91C_MCI_TNPR (AT91_CAST(AT91_REG *) 0xFFFA8118) // (PDC_MCI) Transmit Next Pointer Register
#define AT91C_MCI_RNPR (AT91_CAST(AT91_REG *) 0xFFFA8110) // (PDC_MCI) Receive Next Pointer Register
#define AT91C_MCI_RPR (AT91_CAST(AT91_REG *) 0xFFFA8100) // (PDC_MCI) Receive Pointer Register
#define AT91C_MCI_TNCR (AT91_CAST(AT91_REG *) 0xFFFA811C) // (PDC_MCI) Transmit Next Counter Register
#define AT91C_MCI_TPR (AT91_CAST(AT91_REG *) 0xFFFA8108) // (PDC_MCI) Transmit Pointer Register
#define AT91C_MCI_PTSR (AT91_CAST(AT91_REG *) 0xFFFA8124) // (PDC_MCI) PDC Transfer Status Register
#define AT91C_MCI_PTCR (AT91_CAST(AT91_REG *) 0xFFFA8120) // (PDC_MCI) PDC Transfer Control Register
// ========== Register definition for MCI peripheral ==========
#define AT91C_MCI_RDR (AT91_CAST(AT91_REG *) 0xFFFA8030) // (MCI) MCI Receive Data Register
#define AT91C_MCI_CMDR (AT91_CAST(AT91_REG *) 0xFFFA8014) // (MCI) MCI Command Register
#define AT91C_MCI_VR (AT91_CAST(AT91_REG *) 0xFFFA80FC) // (MCI) MCI Version Register
#define AT91C_MCI_IDR (AT91_CAST(AT91_REG *) 0xFFFA8048) // (MCI) MCI Interrupt Disable Register
#define AT91C_MCI_DTOR (AT91_CAST(AT91_REG *) 0xFFFA8008) // (MCI) MCI Data Timeout Register
#define AT91C_MCI_TDR (AT91_CAST(AT91_REG *) 0xFFFA8034) // (MCI) MCI Transmit Data Register
#define AT91C_MCI_IER (AT91_CAST(AT91_REG *) 0xFFFA8044) // (MCI) MCI Interrupt Enable Register
#define AT91C_MCI_BLKR (AT91_CAST(AT91_REG *) 0xFFFA8018) // (MCI) MCI Block Register
#define AT91C_MCI_MR (AT91_CAST(AT91_REG *) 0xFFFA8004) // (MCI) MCI Mode Register
#define AT91C_MCI_IMR (AT91_CAST(AT91_REG *) 0xFFFA804C) // (MCI) MCI Interrupt Mask Register
#define AT91C_MCI_CR (AT91_CAST(AT91_REG *) 0xFFFA8000) // (MCI) MCI Control Register
#define AT91C_MCI_ARGR (AT91_CAST(AT91_REG *) 0xFFFA8010) // (MCI) MCI Argument Register
#define AT91C_MCI_SDCR (AT91_CAST(AT91_REG *) 0xFFFA800C) // (MCI) MCI SD Card Register
#define AT91C_MCI_SR (AT91_CAST(AT91_REG *) 0xFFFA8040) // (MCI) MCI Status Register
#define AT91C_MCI_RSPR (AT91_CAST(AT91_REG *) 0xFFFA8020) // (MCI) MCI Response Register
// ========== Register definition for PDC_TWI0 peripheral ==========
#define AT91C_TWI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFAC124) // (PDC_TWI0) PDC Transfer Status Register
#define AT91C_TWI0_RPR (AT91_CAST(AT91_REG *) 0xFFFAC100) // (PDC_TWI0) Receive Pointer Register
#define AT91C_TWI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFAC114) // (PDC_TWI0) Receive Next Counter Register
#define AT91C_TWI0_RCR (AT91_CAST(AT91_REG *) 0xFFFAC104) // (PDC_TWI0) Receive Counter Register
#define AT91C_TWI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFAC120) // (PDC_TWI0) PDC Transfer Control Register
#define AT91C_TWI0_TPR (AT91_CAST(AT91_REG *) 0xFFFAC108) // (PDC_TWI0) Transmit Pointer Register
#define AT91C_TWI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFAC110) // (PDC_TWI0) Receive Next Pointer Register
#define AT91C_TWI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFAC118) // (PDC_TWI0) Transmit Next Pointer Register
#define AT91C_TWI0_TCR (AT91_CAST(AT91_REG *) 0xFFFAC10C) // (PDC_TWI0) Transmit Counter Register
#define AT91C_TWI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFAC11C) // (PDC_TWI0) Transmit Next Counter Register
// ========== Register definition for TWI0 peripheral ==========
#define AT91C_TWI0_THR (AT91_CAST(AT91_REG *) 0xFFFAC034) // (TWI0) Transmit Holding Register
#define AT91C_TWI0_IDR (AT91_CAST(AT91_REG *) 0xFFFAC028) // (TWI0) Interrupt Disable Register
#define AT91C_TWI0_SMR (AT91_CAST(AT91_REG *) 0xFFFAC008) // (TWI0) Slave Mode Register
#define AT91C_TWI0_CWGR (AT91_CAST(AT91_REG *) 0xFFFAC010) // (TWI0) Clock Waveform Generator Register
#define AT91C_TWI0_IADR (AT91_CAST(AT91_REG *) 0xFFFAC00C) // (TWI0) Internal Address Register
#define AT91C_TWI0_RHR (AT91_CAST(AT91_REG *) 0xFFFAC030) // (TWI0) Receive Holding Register
#define AT91C_TWI0_IER (AT91_CAST(AT91_REG *) 0xFFFAC024) // (TWI0) Interrupt Enable Register
#define AT91C_TWI0_MMR (AT91_CAST(AT91_REG *) 0xFFFAC004) // (TWI0) Master Mode Register
#define AT91C_TWI0_SR (AT91_CAST(AT91_REG *) 0xFFFAC020) // (TWI0) Status Register
#define AT91C_TWI0_IMR (AT91_CAST(AT91_REG *) 0xFFFAC02C) // (TWI0) Interrupt Mask Register
#define AT91C_TWI0_CR (AT91_CAST(AT91_REG *) 0xFFFAC000) // (TWI0) Control Register
// ========== Register definition for PDC_TWI1 peripheral ==========
#define AT91C_TWI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_TWI1) PDC Transfer Status Register
#define AT91C_TWI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_TWI1) PDC Transfer Control Register
#define AT91C_TWI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_TWI1) Transmit Next Pointer Register
#define AT91C_TWI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_TWI1) Transmit Next Counter Register
#define AT91C_TWI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_TWI1) Receive Next Pointer Register
#define AT91C_TWI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_TWI1) Receive Next Counter Register
#define AT91C_TWI1_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_TWI1) Receive Pointer Register
#define AT91C_TWI1_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_TWI1) Transmit Counter Register
#define AT91C_TWI1_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_TWI1) Transmit Pointer Register
#define AT91C_TWI1_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_TWI1) Receive Counter Register
// ========== Register definition for TWI1 peripheral ==========
#define AT91C_TWI1_RHR (AT91_CAST(AT91_REG *) 0xFFFD8030) // (TWI1) Receive Holding Register
#define AT91C_TWI1_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (TWI1) Interrupt Enable Register
#define AT91C_TWI1_CWGR (AT91_CAST(AT91_REG *) 0xFFFD8010) // (TWI1) Clock Waveform Generator Register
#define AT91C_TWI1_MMR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (TWI1) Master Mode Register
#define AT91C_TWI1_IADR (AT91_CAST(AT91_REG *) 0xFFFD800C) // (TWI1) Internal Address Register
#define AT91C_TWI1_THR (AT91_CAST(AT91_REG *) 0xFFFD8034) // (TWI1) Transmit Holding Register
#define AT91C_TWI1_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (TWI1) Interrupt Mask Register
#define AT91C_TWI1_SR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (TWI1) Status Register
#define AT91C_TWI1_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (TWI1) Interrupt Disable Register
#define AT91C_TWI1_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (TWI1) Control Register
#define AT91C_TWI1_SMR (AT91_CAST(AT91_REG *) 0xFFFD8008) // (TWI1) Slave Mode Register
// ========== Register definition for PDC_US0 peripheral ==========
#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFB010C) // (PDC_US0) Transmit Counter Register
#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFB0120) // (PDC_US0) PDC Transfer Control Register
#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFB0114) // (PDC_US0) Receive Next Counter Register
#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFB0124) // (PDC_US0) PDC Transfer Status Register
#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFB011C) // (PDC_US0) Transmit Next Counter Register
#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFB0110) // (PDC_US0) Receive Next Pointer Register
#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFB0104) // (PDC_US0) Receive Counter Register
#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFB0108) // (PDC_US0) Transmit Pointer Register
#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFB0118) // (PDC_US0) Transmit Next Pointer Register
#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFB0100) // (PDC_US0) Receive Pointer Register
// ========== Register definition for US0 peripheral ==========
#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (US0) Receiver Holding Register
#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFB0044) // (US0) Nb Errors Register
#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFB0008) // (US0) Interrupt Enable Register
#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFB0000) // (US0) Control Register
#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (US0) Transmitter Holding Register
#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (US0) Channel Status Register
#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (US0) Baud Rate Generator Register
#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFB0024) // (US0) Receiver Time-out Register
#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFB0028) // (US0) Transmitter Time-guard Register
#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFB000C) // (US0) Interrupt Disable Register
#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFB0004) // (US0) Mode Register
#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFB004C) // (US0) IRDA_FILTER Register
#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFB0040) // (US0) FI_DI_Ratio Register
#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFB0010) // (US0) Interrupt Mask Register
// ========== Register definition for PDC_US1 peripheral ==========
#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFB4120) // (PDC_US1) PDC Transfer Control Register
#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFB4104) // (PDC_US1) Receive Counter Register
#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFB4100) // (PDC_US1) Receive Pointer Register
#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFB4124) // (PDC_US1) PDC Transfer Status Register
#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFB4108) // (PDC_US1) Transmit Pointer Register
#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFB410C) // (PDC_US1) Transmit Counter Register
#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFB4110) // (PDC_US1) Receive Next Pointer Register
#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFB411C) // (PDC_US1) Transmit Next Counter Register
#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFB4114) // (PDC_US1) Receive Next Counter Register
#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFB4118) // (PDC_US1) Transmit Next Pointer Register
// ========== Register definition for US1 peripheral ==========
#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFB401C) // (US1) Transmitter Holding Register
#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFB4028) // (US1) Transmitter Time-guard Register
#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFB4020) // (US1) Baud Rate Generator Register
#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFB400C) // (US1) Interrupt Disable Register
#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFB4004) // (US1) Mode Register
#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFB4024) // (US1) Receiver Time-out Register
#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFB4000) // (US1) Control Register
#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFB4010) // (US1) Interrupt Mask Register
#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFB4040) // (US1) FI_DI_Ratio Register
#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFB4018) // (US1) Receiver Holding Register
#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFB4008) // (US1) Interrupt Enable Register
#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFB4014) // (US1) Channel Status Register
#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFB404C) // (US1) IRDA_FILTER Register
#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFB4044) // (US1) Nb Errors Register
// ========== Register definition for PDC_US2 peripheral ==========
#define AT91C_US2_TNCR (AT91_CAST(AT91_REG *) 0xFFFB811C) // (PDC_US2) Transmit Next Counter Register
#define AT91C_US2_RNCR (AT91_CAST(AT91_REG *) 0xFFFB8114) // (PDC_US2) Receive Next Counter Register
#define AT91C_US2_TNPR (AT91_CAST(AT91_REG *) 0xFFFB8118) // (PDC_US2) Transmit Next Pointer Register
#define AT91C_US2_PTCR (AT91_CAST(AT91_REG *) 0xFFFB8120) // (PDC_US2) PDC Transfer Control Register
#define AT91C_US2_TCR (AT91_CAST(AT91_REG *) 0xFFFB810C) // (PDC_US2) Transmit Counter Register
#define AT91C_US2_RPR (AT91_CAST(AT91_REG *) 0xFFFB8100) // (PDC_US2) Receive Pointer Register
#define AT91C_US2_TPR (AT91_CAST(AT91_REG *) 0xFFFB8108) // (PDC_US2) Transmit Pointer Register
#define AT91C_US2_RCR (AT91_CAST(AT91_REG *) 0xFFFB8104) // (PDC_US2) Receive Counter Register
#define AT91C_US2_PTSR (AT91_CAST(AT91_REG *) 0xFFFB8124) // (PDC_US2) PDC Transfer Status Register
#define AT91C_US2_RNPR (AT91_CAST(AT91_REG *) 0xFFFB8110) // (PDC_US2) Receive Next Pointer Register
// ========== Register definition for US2 peripheral ==========
#define AT91C_US2_RTOR (AT91_CAST(AT91_REG *) 0xFFFB8024) // (US2) Receiver Time-out Register
#define AT91C_US2_CSR (AT91_CAST(AT91_REG *) 0xFFFB8014) // (US2) Channel Status Register
#define AT91C_US2_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (US2) Control Register
#define AT91C_US2_BRGR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (US2) Baud Rate Generator Register
#define AT91C_US2_NER (AT91_CAST(AT91_REG *) 0xFFFB8044) // (US2) Nb Errors Register
#define AT91C_US2_FIDI (AT91_CAST(AT91_REG *) 0xFFFB8040) // (US2) FI_DI_Ratio Register
#define AT91C_US2_TTGR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (US2) Transmitter Time-guard Register
#define AT91C_US2_RHR (AT91_CAST(AT91_REG *) 0xFFFB8018) // (US2) Receiver Holding Register
#define AT91C_US2_IDR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (US2) Interrupt Disable Register
#define AT91C_US2_THR (AT91_CAST(AT91_REG *) 0xFFFB801C) // (US2) Transmitter Holding Register
#define AT91C_US2_MR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (US2) Mode Register
#define AT91C_US2_IMR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (US2) Interrupt Mask Register
#define AT91C_US2_IF (AT91_CAST(AT91_REG *) 0xFFFB804C) // (US2) IRDA_FILTER Register
#define AT91C_US2_IER (AT91_CAST(AT91_REG *) 0xFFFB8008) // (US2) Interrupt Enable Register
// ========== Register definition for PDC_US3 peripheral ==========
#define AT91C_US3_RNPR (AT91_CAST(AT91_REG *) 0xFFFD0110) // (PDC_US3) Receive Next Pointer Register
#define AT91C_US3_RNCR (AT91_CAST(AT91_REG *) 0xFFFD0114) // (PDC_US3) Receive Next Counter Register
#define AT91C_US3_PTSR (AT91_CAST(AT91_REG *) 0xFFFD0124) // (PDC_US3) PDC Transfer Status Register
#define AT91C_US3_PTCR (AT91_CAST(AT91_REG *) 0xFFFD0120) // (PDC_US3) PDC Transfer Control Register
#define AT91C_US3_TCR (AT91_CAST(AT91_REG *) 0xFFFD010C) // (PDC_US3) Transmit Counter Register
#define AT91C_US3_TNPR (AT91_CAST(AT91_REG *) 0xFFFD0118) // (PDC_US3) Transmit Next Pointer Register
#define AT91C_US3_RCR (AT91_CAST(AT91_REG *) 0xFFFD0104) // (PDC_US3) Receive Counter Register
#define AT91C_US3_TPR (AT91_CAST(AT91_REG *) 0xFFFD0108) // (PDC_US3) Transmit Pointer Register
#define AT91C_US3_TNCR (AT91_CAST(AT91_REG *) 0xFFFD011C) // (PDC_US3) Transmit Next Counter Register
#define AT91C_US3_RPR (AT91_CAST(AT91_REG *) 0xFFFD0100) // (PDC_US3) Receive Pointer Register
// ========== Register definition for US3 peripheral ==========
#define AT91C_US3_NER (AT91_CAST(AT91_REG *) 0xFFFD0044) // (US3) Nb Errors Register
#define AT91C_US3_RTOR (AT91_CAST(AT91_REG *) 0xFFFD0024) // (US3) Receiver Time-out Register
#define AT91C_US3_IDR (AT91_CAST(AT91_REG *) 0xFFFD000C) // (US3) Interrupt Disable Register
#define AT91C_US3_MR (AT91_CAST(AT91_REG *) 0xFFFD0004) // (US3) Mode Register
#define AT91C_US3_FIDI (AT91_CAST(AT91_REG *) 0xFFFD0040) // (US3) FI_DI_Ratio Register
#define AT91C_US3_BRGR (AT91_CAST(AT91_REG *) 0xFFFD0020) // (US3) Baud Rate Generator Register
#define AT91C_US3_THR (AT91_CAST(AT91_REG *) 0xFFFD001C) // (US3) Transmitter Holding Register
#define AT91C_US3_CR (AT91_CAST(AT91_REG *) 0xFFFD0000) // (US3) Control Register
#define AT91C_US3_IF (AT91_CAST(AT91_REG *) 0xFFFD004C) // (US3) IRDA_FILTER Register
#define AT91C_US3_IER (AT91_CAST(AT91_REG *) 0xFFFD0008) // (US3) Interrupt Enable Register
#define AT91C_US3_TTGR (AT91_CAST(AT91_REG *) 0xFFFD0028) // (US3) Transmitter Time-guard Register
#define AT91C_US3_RHR (AT91_CAST(AT91_REG *) 0xFFFD0018) // (US3) Receiver Holding Register
#define AT91C_US3_IMR (AT91_CAST(AT91_REG *) 0xFFFD0010) // (US3) Interrupt Mask Register
#define AT91C_US3_CSR (AT91_CAST(AT91_REG *) 0xFFFD0014) // (US3) Channel Status Register
// ========== Register definition for PDC_US4 peripheral ==========
#define AT91C_US4_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_US4) Transmit Next Counter Register
#define AT91C_US4_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_US4) Receive Pointer Register
#define AT91C_US4_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_US4) Receive Next Counter Register
#define AT91C_US4_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_US4) Transmit Pointer Register
#define AT91C_US4_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_US4) PDC Transfer Control Register
#define AT91C_US4_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_US4) Transmit Counter Register
#define AT91C_US4_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_US4) Receive Counter Register
#define AT91C_US4_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_US4) Receive Next Pointer Register
#define AT91C_US4_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_US4) Transmit Next Pointer Register
#define AT91C_US4_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_US4) PDC Transfer Status Register
// ========== Register definition for US4 peripheral ==========
#define AT91C_US4_BRGR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (US4) Baud Rate Generator Register
#define AT91C_US4_THR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (US4) Transmitter Holding Register
#define AT91C_US4_RTOR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (US4) Receiver Time-out Register
#define AT91C_US4_IMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (US4) Interrupt Mask Register
#define AT91C_US4_NER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (US4) Nb Errors Register
#define AT91C_US4_TTGR (AT91_CAST(AT91_REG *) 0xFFFD4028) // (US4) Transmitter Time-guard Register
#define AT91C_US4_FIDI (AT91_CAST(AT91_REG *) 0xFFFD4040) // (US4) FI_DI_Ratio Register
#define AT91C_US4_MR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (US4) Mode Register
#define AT91C_US4_IER (AT91_CAST(AT91_REG *) 0xFFFD4008) // (US4) Interrupt Enable Register
#define AT91C_US4_RHR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (US4) Receiver Holding Register
#define AT91C_US4_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (US4) Control Register
#define AT91C_US4_IF (AT91_CAST(AT91_REG *) 0xFFFD404C) // (US4) IRDA_FILTER Register
#define AT91C_US4_IDR (AT91_CAST(AT91_REG *) 0xFFFD400C) // (US4) Interrupt Disable Register
#define AT91C_US4_CSR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (US4) Channel Status Register
// ========== Register definition for PDC_SSC0 peripheral ==========
#define AT91C_SSC0_TNPR (AT91_CAST(AT91_REG *) 0xFFFBC118) // (PDC_SSC0) Transmit Next Pointer Register
#define AT91C_SSC0_TCR (AT91_CAST(AT91_REG *) 0xFFFBC10C) // (PDC_SSC0) Transmit Counter Register
#define AT91C_SSC0_RNCR (AT91_CAST(AT91_REG *) 0xFFFBC114) // (PDC_SSC0) Receive Next Counter Register
#define AT91C_SSC0_RPR (AT91_CAST(AT91_REG *) 0xFFFBC100) // (PDC_SSC0) Receive Pointer Register
#define AT91C_SSC0_TPR (AT91_CAST(AT91_REG *) 0xFFFBC108) // (PDC_SSC0) Transmit Pointer Register
#define AT91C_SSC0_RCR (AT91_CAST(AT91_REG *) 0xFFFBC104) // (PDC_SSC0) Receive Counter Register
#define AT91C_SSC0_RNPR (AT91_CAST(AT91_REG *) 0xFFFBC110) // (PDC_SSC0) Receive Next Pointer Register
#define AT91C_SSC0_PTCR (AT91_CAST(AT91_REG *) 0xFFFBC120) // (PDC_SSC0) PDC Transfer Control Register
#define AT91C_SSC0_TNCR (AT91_CAST(AT91_REG *) 0xFFFBC11C) // (PDC_SSC0) Transmit Next Counter Register
#define AT91C_SSC0_PTSR (AT91_CAST(AT91_REG *) 0xFFFBC124) // (PDC_SSC0) PDC Transfer Status Register
// ========== Register definition for SSC0 peripheral ==========
#define AT91C_SSC0_IMR (AT91_CAST(AT91_REG *) 0xFFFBC04C) // (SSC0) Interrupt Mask Register
#define AT91C_SSC0_RFMR (AT91_CAST(AT91_REG *) 0xFFFBC014) // (SSC0) Receive Frame Mode Register
#define AT91C_SSC0_CR (AT91_CAST(AT91_REG *) 0xFFFBC000) // (SSC0) Control Register
#define AT91C_SSC0_TFMR (AT91_CAST(AT91_REG *) 0xFFFBC01C) // (SSC0) Transmit Frame Mode Register
#define AT91C_SSC0_CMR (AT91_CAST(AT91_REG *) 0xFFFBC004) // (SSC0) Clock Mode Register
#define AT91C_SSC0_IER (AT91_CAST(AT91_REG *) 0xFFFBC044) // (SSC0) Interrupt Enable Register
#define AT91C_SSC0_RHR (AT91_CAST(AT91_REG *) 0xFFFBC020) // (SSC0) Receive Holding Register
#define AT91C_SSC0_RCMR (AT91_CAST(AT91_REG *) 0xFFFBC010) // (SSC0) Receive Clock ModeRegister
#define AT91C_SSC0_SR (AT91_CAST(AT91_REG *) 0xFFFBC040) // (SSC0) Status Register
#define AT91C_SSC0_RSHR (AT91_CAST(AT91_REG *) 0xFFFBC030) // (SSC0) Receive Sync Holding Register
#define AT91C_SSC0_THR (AT91_CAST(AT91_REG *) 0xFFFBC024) // (SSC0) Transmit Holding Register
#define AT91C_SSC0_TCMR (AT91_CAST(AT91_REG *) 0xFFFBC018) // (SSC0) Transmit Clock Mode Register
#define AT91C_SSC0_IDR (AT91_CAST(AT91_REG *) 0xFFFBC048) // (SSC0) Interrupt Disable Register
#define AT91C_SSC0_TSHR (AT91_CAST(AT91_REG *) 0xFFFBC034) // (SSC0) Transmit Sync Holding Register
// ========== Register definition for PDC_SPI0 peripheral ==========
#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC8120) // (PDC_SPI0) PDC Transfer Control Register
#define AT91C_SPI0_TCR (AT91_CAST(AT91_REG *) 0xFFFC810C) // (PDC_SPI0) Transmit Counter Register
#define AT91C_SPI0_RPR (AT91_CAST(AT91_REG *) 0xFFFC8100) // (PDC_SPI0) Receive Pointer Register
#define AT91C_SPI0_TPR (AT91_CAST(AT91_REG *) 0xFFFC8108) // (PDC_SPI0) Transmit Pointer Register
#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC8124) // (PDC_SPI0) PDC Transfer Status Register
#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC8114) // (PDC_SPI0) Receive Next Counter Register
#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC8118) // (PDC_SPI0) Transmit Next Pointer Register
#define AT91C_SPI0_RCR (AT91_CAST(AT91_REG *) 0xFFFC8104) // (PDC_SPI0) Receive Counter Register
#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC8110) // (PDC_SPI0) Receive Next Pointer Register
#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC811C) // (PDC_SPI0) Transmit Next Counter Register
// ========== Register definition for SPI0 peripheral ==========
#define AT91C_SPI0_IDR (AT91_CAST(AT91_REG *) 0xFFFC8018) // (SPI0) Interrupt Disable Register
#define AT91C_SPI0_TDR (AT91_CAST(AT91_REG *) 0xFFFC800C) // (SPI0) Transmit Data Register
#define AT91C_SPI0_SR (AT91_CAST(AT91_REG *) 0xFFFC8010) // (SPI0) Status Register
#define AT91C_SPI0_CR (AT91_CAST(AT91_REG *) 0xFFFC8000) // (SPI0) Control Register
#define AT91C_SPI0_CSR (AT91_CAST(AT91_REG *) 0xFFFC8030) // (SPI0) Chip Select Register
#define AT91C_SPI0_RDR (AT91_CAST(AT91_REG *) 0xFFFC8008) // (SPI0) Receive Data Register
#define AT91C_SPI0_MR (AT91_CAST(AT91_REG *) 0xFFFC8004) // (SPI0) Mode Register
#define AT91C_SPI0_IER (AT91_CAST(AT91_REG *) 0xFFFC8014) // (SPI0) Interrupt Enable Register
#define AT91C_SPI0_IMR (AT91_CAST(AT91_REG *) 0xFFFC801C) // (SPI0) Interrupt Mask Register
// ========== Register definition for PDC_SPI1 peripheral ==========
#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFCC120) // (PDC_SPI1) PDC Transfer Control Register
#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFCC110) // (PDC_SPI1) Receive Next Pointer Register
#define AT91C_SPI1_RCR (AT91_CAST(AT91_REG *) 0xFFFCC104) // (PDC_SPI1) Receive Counter Register
#define AT91C_SPI1_TPR (AT91_CAST(AT91_REG *) 0xFFFCC108) // (PDC_SPI1) Transmit Pointer Register
#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFCC124) // (PDC_SPI1) PDC Transfer Status Register
#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFCC11C) // (PDC_SPI1) Transmit Next Counter Register
#define AT91C_SPI1_RPR (AT91_CAST(AT91_REG *) 0xFFFCC100) // (PDC_SPI1) Receive Pointer Register
#define AT91C_SPI1_TCR (AT91_CAST(AT91_REG *) 0xFFFCC10C) // (PDC_SPI1) Transmit Counter Register
#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFCC114) // (PDC_SPI1) Receive Next Counter Register
#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFCC118) // (PDC_SPI1) Transmit Next Pointer Register
// ========== Register definition for SPI1 peripheral ==========
#define AT91C_SPI1_IER (AT91_CAST(AT91_REG *) 0xFFFCC014) // (SPI1) Interrupt Enable Register
#define AT91C_SPI1_RDR (AT91_CAST(AT91_REG *) 0xFFFCC008) // (SPI1) Receive Data Register
#define AT91C_SPI1_SR (AT91_CAST(AT91_REG *) 0xFFFCC010) // (SPI1) Status Register
#define AT91C_SPI1_IMR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (SPI1) Interrupt Mask Register
#define AT91C_SPI1_TDR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (SPI1) Transmit Data Register
#define AT91C_SPI1_IDR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (SPI1) Interrupt Disable Register
#define AT91C_SPI1_CSR (AT91_CAST(AT91_REG *) 0xFFFCC030) // (SPI1) Chip Select Register
#define AT91C_SPI1_CR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (SPI1) Control Register
#define AT91C_SPI1_MR (AT91_CAST(AT91_REG *) 0xFFFCC004) // (SPI1) Mode Register
// ========== Register definition for PDC_ADC peripheral ==========
#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_ADC) PDC Transfer Control Register
#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_ADC) Transmit Pointer Register
#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_ADC) Transmit Counter Register
#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_ADC) Receive Counter Register
#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_ADC) PDC Transfer Status Register
#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_ADC) Receive Next Pointer Register
#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_ADC) Receive Pointer Register
#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_ADC) Transmit Next Counter Register
#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_ADC) Receive Next Counter Register
#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_ADC) Transmit Next Pointer Register
// ========== Register definition for ADC peripheral ==========
#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFE0014) // (ADC) ADC Channel Disable Register
#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFE003C) // (ADC) ADC Channel Data Register 3
#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (ADC) ADC Control Register
#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFE002C) // (ADC) ADC Interrupt Mask Register
#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFE0038) // (ADC) ADC Channel Data Register 2
#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (ADC) ADC Status Register
#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFE0024) // (ADC) ADC Interrupt Enable Register
#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFE004C) // (ADC) ADC Channel Data Register 7
#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFE0030) // (ADC) ADC Channel Data Register 0
#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFE0044) // (ADC) ADC Channel Data Register 5
#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFE0040) // (ADC) ADC Channel Data Register 4
#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFE0010) // (ADC) ADC Channel Enable Register
#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (ADC) ADC Channel Status Register
#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (ADC) ADC Mode Register
#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFE0048) // (ADC) ADC Channel Data Register 6
#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFE0020) // (ADC) ADC Last Converted Data Register
#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFE0034) // (ADC) ADC Channel Data Register 1
#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFE0028) // (ADC) ADC Interrupt Disable Register
// ========== Register definition for EMACB peripheral ==========
#define AT91C_EMACB_USRIO (AT91_CAST(AT91_REG *) 0xFFFC40C0) // (EMACB) USER Input/Output Register
#define AT91C_EMACB_RSE (AT91_CAST(AT91_REG *) 0xFFFC4074) // (EMACB) Receive Symbol Errors Register
#define AT91C_EMACB_SCF (AT91_CAST(AT91_REG *) 0xFFFC4044) // (EMACB) Single Collision Frame Register
#define AT91C_EMACB_STE (AT91_CAST(AT91_REG *) 0xFFFC4084) // (EMACB) SQE Test Error Register
#define AT91C_EMACB_SA1H (AT91_CAST(AT91_REG *) 0xFFFC409C) // (EMACB) Specific Address 1 Top, Last 2 bytes
#define AT91C_EMACB_ROV (AT91_CAST(AT91_REG *) 0xFFFC4070) // (EMACB) Receive Overrun Errors Register
#define AT91C_EMACB_TBQP (AT91_CAST(AT91_REG *) 0xFFFC401C) // (EMACB) Transmit Buffer Queue Pointer
#define AT91C_EMACB_IMR (AT91_CAST(AT91_REG *) 0xFFFC4030) // (EMACB) Interrupt Mask Register
#define AT91C_EMACB_IER (AT91_CAST(AT91_REG *) 0xFFFC4028) // (EMACB) Interrupt Enable Register
#define AT91C_EMACB_REV (AT91_CAST(AT91_REG *) 0xFFFC40FC) // (EMACB) Revision Register
#define AT91C_EMACB_SA3L (AT91_CAST(AT91_REG *) 0xFFFC40A8) // (EMACB) Specific Address 3 Bottom, First 4 bytes
#define AT91C_EMACB_ELE (AT91_CAST(AT91_REG *) 0xFFFC4078) // (EMACB) Excessive Length Errors Register
#define AT91C_EMACB_HRT (AT91_CAST(AT91_REG *) 0xFFFC4094) // (EMACB) Hash Address Top[63:32]
#define AT91C_EMACB_SA2L (AT91_CAST(AT91_REG *) 0xFFFC40A0) // (EMACB) Specific Address 2 Bottom, First 4 bytes
#define AT91C_EMACB_RRE (AT91_CAST(AT91_REG *) 0xFFFC406C) // (EMACB) Receive Ressource Error Register
#define AT91C_EMACB_FRO (AT91_CAST(AT91_REG *) 0xFFFC404C) // (EMACB) Frames Received OK Register
#define AT91C_EMACB_TPQ (AT91_CAST(AT91_REG *) 0xFFFC40BC) // (EMACB) Transmit Pause Quantum Register
#define AT91C_EMACB_ISR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (EMACB) Interrupt Status Register
#define AT91C_EMACB_TSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (EMACB) Transmit Status Register
#define AT91C_EMACB_RLE (AT91_CAST(AT91_REG *) 0xFFFC4088) // (EMACB) Receive Length Field Mismatch Register
#define AT91C_EMACB_USF (AT91_CAST(AT91_REG *) 0xFFFC4080) // (EMACB) Undersize Frames Register
#define AT91C_EMACB_WOL (AT91_CAST(AT91_REG *) 0xFFFC40C4) // (EMACB) Wake On LAN Register
#define AT91C_EMACB_TPF (AT91_CAST(AT91_REG *) 0xFFFC408C) // (EMACB) Transmitted Pause Frames Register
#define AT91C_EMACB_PTR (AT91_CAST(AT91_REG *) 0xFFFC4038) // (EMACB) Pause Time Register
#define AT91C_EMACB_TUND (AT91_CAST(AT91_REG *) 0xFFFC4064) // (EMACB) Transmit Underrun Error Register
#define AT91C_EMACB_MAN (AT91_CAST(AT91_REG *) 0xFFFC4034) // (EMACB) PHY Maintenance Register
#define AT91C_EMACB_RJA (AT91_CAST(AT91_REG *) 0xFFFC407C) // (EMACB) Receive Jabbers Register
#define AT91C_EMACB_SA4L (AT91_CAST(AT91_REG *) 0xFFFC40B0) // (EMACB) Specific Address 4 Bottom, First 4 bytes
#define AT91C_EMACB_CSE (AT91_CAST(AT91_REG *) 0xFFFC4068) // (EMACB) Carrier Sense Error Register
#define AT91C_EMACB_HRB (AT91_CAST(AT91_REG *) 0xFFFC4090) // (EMACB) Hash Address Bottom[31:0]
#define AT91C_EMACB_ALE (AT91_CAST(AT91_REG *) 0xFFFC4054) // (EMACB) Alignment Error Register
#define AT91C_EMACB_SA1L (AT91_CAST(AT91_REG *) 0xFFFC4098) // (EMACB) Specific Address 1 Bottom, First 4 bytes
#define AT91C_EMACB_NCR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (EMACB) Network Control Register
#define AT91C_EMACB_FTO (AT91_CAST(AT91_REG *) 0xFFFC4040) // (EMACB) Frames Transmitted OK Register
#define AT91C_EMACB_ECOL (AT91_CAST(AT91_REG *) 0xFFFC4060) // (EMACB) Excessive Collision Register
#define AT91C_EMACB_DTF (AT91_CAST(AT91_REG *) 0xFFFC4058) // (EMACB) Deferred Transmission Frame Register
#define AT91C_EMACB_SA4H (AT91_CAST(AT91_REG *) 0xFFFC40B4) // (EMACB) Specific Address 4 Top, Last 2 bytes
#define AT91C_EMACB_FCSE (AT91_CAST(AT91_REG *) 0xFFFC4050) // (EMACB) Frame Check Sequence Error Register
#define AT91C_EMACB_TID (AT91_CAST(AT91_REG *) 0xFFFC40B8) // (EMACB) Type ID Checking Register
#define AT91C_EMACB_PFR (AT91_CAST(AT91_REG *) 0xFFFC403C) // (EMACB) Pause Frames received Register
#define AT91C_EMACB_IDR (AT91_CAST(AT91_REG *) 0xFFFC402C) // (EMACB) Interrupt Disable Register
#define AT91C_EMACB_SA3H (AT91_CAST(AT91_REG *) 0xFFFC40AC) // (EMACB) Specific Address 3 Top, Last 2 bytes
#define AT91C_EMACB_NSR (AT91_CAST(AT91_REG *) 0xFFFC4008) // (EMACB) Network Status Register
#define AT91C_EMACB_MCF (AT91_CAST(AT91_REG *) 0xFFFC4048) // (EMACB) Multiple Collision Frame Register
#define AT91C_EMACB_RBQP (AT91_CAST(AT91_REG *) 0xFFFC4018) // (EMACB) Receive Buffer Queue Pointer
#define AT91C_EMACB_RSR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (EMACB) Receive Status Register
#define AT91C_EMACB_SA2H (AT91_CAST(AT91_REG *) 0xFFFC40A4) // (EMACB) Specific Address 2 Top, Last 2 bytes
#define AT91C_EMACB_NCFGR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (EMACB) Network Configuration Register
#define AT91C_EMACB_LCOL (AT91_CAST(AT91_REG *) 0xFFFC405C) // (EMACB) Late Collision Register
// ========== Register definition for UDP peripheral ==========
#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFA4004) // (UDP) Global State Register
#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFA4050) // (UDP) Endpoint FIFO Data Register
#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFA4028) // (UDP) Reset Endpoint Register
#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFA4008) // (UDP) Function Address Register
#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFA4000) // (UDP) Frame Number Register
#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFA4014) // (UDP) Interrupt Disable Register
#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFA4018) // (UDP) Interrupt Mask Register
#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFA4030) // (UDP) Endpoint Control and Status Register
#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFA4010) // (UDP) Interrupt Enable Register
#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFA4020) // (UDP) Interrupt Clear Register
#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFA4074) // (UDP) Transceiver Control Register
#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFA401C) // (UDP) Interrupt Status Register
// ========== Register definition for UHP peripheral ==========
#define AT91C_UHP_HcInterruptStatus (AT91_CAST(AT91_REG *) 0x0050000C) // (UHP) Interrupt Status Register
#define AT91C_UHP_HcCommandStatus (AT91_CAST(AT91_REG *) 0x00500008) // (UHP) Command & status Register
#define AT91C_UHP_HcRhStatus (AT91_CAST(AT91_REG *) 0x00500050) // (UHP) Root Hub Status register
#define AT91C_UHP_HcInterruptDisable (AT91_CAST(AT91_REG *) 0x00500014) // (UHP) Interrupt Disable Register
#define AT91C_UHP_HcPeriodicStart (AT91_CAST(AT91_REG *) 0x00500040) // (UHP) Periodic Start
#define AT91C_UHP_HcControlCurrentED (AT91_CAST(AT91_REG *) 0x00500024) // (UHP) Endpoint Control and Status Register
#define AT91C_UHP_HcPeriodCurrentED (AT91_CAST(AT91_REG *) 0x0050001C) // (UHP) Current Isochronous or Interrupt Endpoint Descriptor
#define AT91C_UHP_HcBulkHeadED (AT91_CAST(AT91_REG *) 0x00500028) // (UHP) First endpoint register of the Bulk list
#define AT91C_UHP_HcRevision (AT91_CAST(AT91_REG *) 0x00500000) // (UHP) Revision
#define AT91C_UHP_HcBulkCurrentED (AT91_CAST(AT91_REG *) 0x0050002C) // (UHP) Current endpoint of the Bulk list
#define AT91C_UHP_HcRhDescriptorB (AT91_CAST(AT91_REG *) 0x0050004C) // (UHP) Root Hub characteristics B
#define AT91C_UHP_HcControlHeadED (AT91_CAST(AT91_REG *) 0x00500020) // (UHP) First Endpoint Descriptor of the Control list
#define AT91C_UHP_HcFmRemaining (AT91_CAST(AT91_REG *) 0x00500038) // (UHP) Bit time remaining in the current Frame
#define AT91C_UHP_HcHCCA (AT91_CAST(AT91_REG *) 0x00500018) // (UHP) Pointer to the Host Controller Communication Area
#define AT91C_UHP_HcLSThreshold (AT91_CAST(AT91_REG *) 0x00500044) // (UHP) LS Threshold
#define AT91C_UHP_HcRhPortStatus (AT91_CAST(AT91_REG *) 0x00500054) // (UHP) Root Hub Port Status Register
#define AT91C_UHP_HcInterruptEnable (AT91_CAST(AT91_REG *) 0x00500010) // (UHP) Interrupt Enable Register
#define AT91C_UHP_HcFmNumber (AT91_CAST(AT91_REG *) 0x0050003C) // (UHP) Frame number
#define AT91C_UHP_HcFmInterval (AT91_CAST(AT91_REG *) 0x00500034) // (UHP) Bit time between 2 consecutive SOFs
#define AT91C_UHP_HcControl (AT91_CAST(AT91_REG *) 0x00500004) // (UHP) Operating modes for the Host Controller
#define AT91C_UHP_HcBulkDoneHead (AT91_CAST(AT91_REG *) 0x00500030) // (UHP) Last completed transfer descriptor
#define AT91C_UHP_HcRhDescriptorA (AT91_CAST(AT91_REG *) 0x00500048) // (UHP) Root Hub characteristics A
// ========== Register definition for HECC peripheral ==========
// ========== Register definition for HISI peripheral ==========
#define AT91C_HISI_PSIZE (AT91_CAST(AT91_REG *) 0xFFFC0020) // (HISI) Preview Size Register
#define AT91C_HISI_CR1 (AT91_CAST(AT91_REG *) 0xFFFC0000) // (HISI) Control Register 1
#define AT91C_HISI_R2YSET1 (AT91_CAST(AT91_REG *) 0xFFFC003C) // (HISI) Color Space Conversion Register
#define AT91C_HISI_CDBA (AT91_CAST(AT91_REG *) 0xFFFC002C) // (HISI) Codec Dma Address Register
#define AT91C_HISI_IDR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (HISI) Interrupt Disable Register
#define AT91C_HISI_R2YSET2 (AT91_CAST(AT91_REG *) 0xFFFC0040) // (HISI) Color Space Conversion Register
#define AT91C_HISI_Y2RSET1 (AT91_CAST(AT91_REG *) 0xFFFC0034) // (HISI) Color Space Conversion Register
#define AT91C_HISI_PFBD (AT91_CAST(AT91_REG *) 0xFFFC0028) // (HISI) Preview Frame Buffer Address Register
#define AT91C_HISI_CR2 (AT91_CAST(AT91_REG *) 0xFFFC0004) // (HISI) Control Register 2
#define AT91C_HISI_Y2RSET0 (AT91_CAST(AT91_REG *) 0xFFFC0030) // (HISI) Color Space Conversion Register
#define AT91C_HISI_PDECF (AT91_CAST(AT91_REG *) 0xFFFC0024) // (HISI) Preview Decimation Factor Register
#define AT91C_HISI_IMR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (HISI) Interrupt Mask Register
#define AT91C_HISI_IER (AT91_CAST(AT91_REG *) 0xFFFC000C) // (HISI) Interrupt Enable Register
#define AT91C_HISI_R2YSET0 (AT91_CAST(AT91_REG *) 0xFFFC0038) // (HISI) Color Space Conversion Register
#define AT91C_HISI_SR (AT91_CAST(AT91_REG *) 0xFFFC0008) // (HISI) Status Register
// *****************************************************************************
// PIO DEFINITIONS FOR AT91SAM9XE256
// *****************************************************************************
#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0
#define AT91C_PA0_SPI0_MISO (AT91C_PIO_PA0) // SPI 0 Master In Slave
#define AT91C_PA0_MCDB0 (AT91C_PIO_PA0) // Multimedia Card B Data 0
#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1
#define AT91C_PA1_SPI0_MOSI (AT91C_PIO_PA1) // SPI 0 Master Out Slave
#define AT91C_PA1_MCCDB (AT91C_PIO_PA1) // Multimedia Card B Command
#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10
#define AT91C_PA10_MCDA2 (AT91C_PIO_PA10) // Multimedia Card A Data 2
#define AT91C_PA10_ETX2_0 (AT91C_PIO_PA10) // Ethernet MAC Transmit Data 2
#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11
#define AT91C_PA11_MCDA3 (AT91C_PIO_PA11) // Multimedia Card A Data 3
#define AT91C_PA11_ETX3_0 (AT91C_PIO_PA11) // Ethernet MAC Transmit Data 3
#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12
#define AT91C_PA12_ETX0 (AT91C_PIO_PA12) // Ethernet MAC Transmit Data 0
#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13
#define AT91C_PA13_ETX1 (AT91C_PIO_PA13) // Ethernet MAC Transmit Data 1
#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14
#define AT91C_PA14_ERX0 (AT91C_PIO_PA14) // Ethernet MAC Receive Data 0
#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15
#define AT91C_PA15_ERX1 (AT91C_PIO_PA15) // Ethernet MAC Receive Data 1
#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16
#define AT91C_PA16_ETXEN (AT91C_PIO_PA16) // Ethernet MAC Transmit Enable
#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17
#define AT91C_PA17_ERXDV (AT91C_PIO_PA17) // Ethernet MAC Receive Data Valid
#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18
#define AT91C_PA18_ERXER (AT91C_PIO_PA18) // Ethernet MAC Receive Error
#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19
#define AT91C_PA19_ETXCK (AT91C_PIO_PA19) // Ethernet MAC Transmit Clock/Reference Clock
#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2
#define AT91C_PA2_SPI0_SPCK (AT91C_PIO_PA2) // SPI 0 Serial Clock
#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20
#define AT91C_PA20_EMDC (AT91C_PIO_PA20) // Ethernet MAC Management Data Clock
#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21
#define AT91C_PA21_EMDIO (AT91C_PIO_PA21) // Ethernet MAC Management Data Input/Output
#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22
#define AT91C_PA22_ADTRG (AT91C_PIO_PA22) // ADC Trigger
#define AT91C_PA22_ETXER (AT91C_PIO_PA22) // Ethernet MAC Transmikt Coding Error
#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23
#define AT91C_PA23_TWD0 (AT91C_PIO_PA23) // TWI Two-wire Serial Data 0
#define AT91C_PA23_ETX2_1 (AT91C_PIO_PA23) // Ethernet MAC Transmit Data 2
#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24
#define AT91C_PA24_TWCK0 (AT91C_PIO_PA24) // TWI Two-wire Serial Clock 0
#define AT91C_PA24_ETX3_1 (AT91C_PIO_PA24) // Ethernet MAC Transmit Data 3
#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25
#define AT91C_PA25_TCLK0 (AT91C_PIO_PA25) // Timer Counter 0 external clock input
#define AT91C_PA25_ERX2 (AT91C_PIO_PA25) // Ethernet MAC Receive Data 2
#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26
#define AT91C_PA26_TIOA0 (AT91C_PIO_PA26) // Timer Counter 0 Multipurpose Timer I/O Pin A
#define AT91C_PA26_ERX3 (AT91C_PIO_PA26) // Ethernet MAC Receive Data 3
#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27
#define AT91C_PA27_TIOA1 (AT91C_PIO_PA27) // Timer Counter 1 Multipurpose Timer I/O Pin A
#define AT91C_PA27_ERXCK (AT91C_PIO_PA27) // Ethernet MAC Receive Clock
#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28
#define AT91C_PA28_TIOA2 (AT91C_PIO_PA28) // Timer Counter 2 Multipurpose Timer I/O Pin A
#define AT91C_PA28_ECRS (AT91C_PIO_PA28) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29
#define AT91C_PA29_SCK1 (AT91C_PIO_PA29) // USART 1 Serial Clock
#define AT91C_PA29_ECOL (AT91C_PIO_PA29) // Ethernet MAC Collision Detected
#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3
#define AT91C_PA3_SPI0_NPCS0 (AT91C_PIO_PA3) // SPI 0 Peripheral Chip Select 0
#define AT91C_PA3_MCDB3 (AT91C_PIO_PA3) // Multimedia Card B Data 3
#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30
#define AT91C_PA30_SCK2 (AT91C_PIO_PA30) // USART 2 Serial Clock
#define AT91C_PA30_RXD4 (AT91C_PIO_PA30) // USART 4 Receive Data
#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31
#define AT91C_PA31_SCK0 (AT91C_PIO_PA31) // USART 0 Serial Clock
#define AT91C_PA31_TXD4 (AT91C_PIO_PA31) // USART 4 Transmit Data
#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4
#define AT91C_PA4_RTS2 (AT91C_PIO_PA4) // USART 2 Ready To Send
#define AT91C_PA4_MCDB2 (AT91C_PIO_PA4) // Multimedia Card B Data 2
#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5
#define AT91C_PA5_CTS2 (AT91C_PIO_PA5) // USART 2 Clear To Send
#define AT91C_PA5_MCDB1 (AT91C_PIO_PA5) // Multimedia Card B Data 1
#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6
#define AT91C_PA6_MCDA0 (AT91C_PIO_PA6) // Multimedia Card A Data 0
#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7
#define AT91C_PA7_MCCDA (AT91C_PIO_PA7) // Multimedia Card A Command
#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8
#define AT91C_PA8_MCCK (AT91C_PIO_PA8) // Multimedia Card Clock
#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9
#define AT91C_PA9_MCDA1 (AT91C_PIO_PA9) // Multimedia Card A Data 1
#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0
#define AT91C_PB0_SPI1_MISO (AT91C_PIO_PB0) // SPI 1 Master In Slave
#define AT91C_PB0_TIOA3 (AT91C_PIO_PB0) // Timer Counter 3 Multipurpose Timer I/O Pin A
#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1
#define AT91C_PB1_SPI1_MOSI (AT91C_PIO_PB1) // SPI 1 Master Out Slave
#define AT91C_PB1_TIOB3 (AT91C_PIO_PB1) // Timer Counter 3 Multipurpose Timer I/O Pin B
#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10
#define AT91C_PB10_TXD3 (AT91C_PIO_PB10) // USART 3 Transmit Data
#define AT91C_PB10_ISI_D8 (AT91C_PIO_PB10) // Image Sensor Data 8
#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11
#define AT91C_PB11_RXD3 (AT91C_PIO_PB11) // USART 3 Receive Data
#define AT91C_PB11_ISI_D9 (AT91C_PIO_PB11) // Image Sensor Data 9
#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12
#define AT91C_PB12_TWD1 (AT91C_PIO_PB12) // TWI Two-wire Serial Data 1
#define AT91C_PB12_ISI_D10 (AT91C_PIO_PB12) // Image Sensor Data 10
#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13
#define AT91C_PB13_TWCK1 (AT91C_PIO_PB13) // TWI Two-wire Serial Clock 1
#define AT91C_PB13_ISI_D11 (AT91C_PIO_PB13) // Image Sensor Data 11
#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14
#define AT91C_PB14_DRXD (AT91C_PIO_PB14) // DBGU Debug Receive Data
#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15
#define AT91C_PB15_DTXD (AT91C_PIO_PB15) // DBGU Debug Transmit Data
#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16
#define AT91C_PB16_TK0 (AT91C_PIO_PB16) // SSC0 Transmit Clock
#define AT91C_PB16_TCLK3 (AT91C_PIO_PB16) // Timer Counter 3 external clock input
#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17
#define AT91C_PB17_TF0 (AT91C_PIO_PB17) // SSC0 Transmit Frame Sync
#define AT91C_PB17_TCLK4 (AT91C_PIO_PB17) // Timer Counter 4 external clock input
#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18
#define AT91C_PB18_TD0 (AT91C_PIO_PB18) // SSC0 Transmit data
#define AT91C_PB18_TIOB4 (AT91C_PIO_PB18) // Timer Counter 4 Multipurpose Timer I/O Pin B
#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19
#define AT91C_PB19_RD0 (AT91C_PIO_PB19) // SSC0 Receive Data
#define AT91C_PB19_TIOB5 (AT91C_PIO_PB19) // Timer Counter 5 Multipurpose Timer I/O Pin B
#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2
#define AT91C_PB2_SPI1_SPCK (AT91C_PIO_PB2) // SPI 1 Serial Clock
#define AT91C_PB2_TIOA4 (AT91C_PIO_PB2) // Timer Counter 4 Multipurpose Timer I/O Pin A
#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20
#define AT91C_PB20_RK0 (AT91C_PIO_PB20) // SSC0 Receive Clock
#define AT91C_PB20_ISI_D0 (AT91C_PIO_PB20) // Image Sensor Data 0
#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21
#define AT91C_PB21_RF0 (AT91C_PIO_PB21) // SSC0 Receive Frame Sync
#define AT91C_PB21_ISI_D1 (AT91C_PIO_PB21) // Image Sensor Data 1
#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22
#define AT91C_PB22_DSR0 (AT91C_PIO_PB22) // USART 0 Data Set ready
#define AT91C_PB22_ISI_D2 (AT91C_PIO_PB22) // Image Sensor Data 2
#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23
#define AT91C_PB23_DCD0 (AT91C_PIO_PB23) // USART 0 Data Carrier Detect
#define AT91C_PB23_ISI_D3 (AT91C_PIO_PB23) // Image Sensor Data 3
#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24
#define AT91C_PB24_DTR0 (AT91C_PIO_PB24) // USART 0 Data Terminal ready
#define AT91C_PB24_ISI_D4 (AT91C_PIO_PB24) // Image Sensor Data 4
#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25
#define AT91C_PB25_RI0 (AT91C_PIO_PB25) // USART 0 Ring Indicator
#define AT91C_PB25_ISI_D5 (AT91C_PIO_PB25) // Image Sensor Data 5
#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26
#define AT91C_PB26_RTS0 (AT91C_PIO_PB26) // USART 0 Ready To Send
#define AT91C_PB26_ISI_D6 (AT91C_PIO_PB26) // Image Sensor Data 6
#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27
#define AT91C_PB27_CTS0 (AT91C_PIO_PB27) // USART 0 Clear To Send
#define AT91C_PB27_ISI_D7 (AT91C_PIO_PB27) // Image Sensor Data 7
#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28
#define AT91C_PB28_RTS1 (AT91C_PIO_PB28) // USART 1 Ready To Send
#define AT91C_PB28_ISI_PCK (AT91C_PIO_PB28) // Image Sensor Data Clock
#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29
#define AT91C_PB29_CTS1 (AT91C_PIO_PB29) // USART 1 Clear To Send
#define AT91C_PB29_ISI_VSYNC (AT91C_PIO_PB29) // Image Sensor Vertical Synchro
#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3
#define AT91C_PB3_SPI1_NPCS0 (AT91C_PIO_PB3) // SPI 1 Peripheral Chip Select 0
#define AT91C_PB3_TIOA5 (AT91C_PIO_PB3) // Timer Counter 5 Multipurpose Timer I/O Pin A
#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30
#define AT91C_PB30_PCK0_0 (AT91C_PIO_PB30) // PMC Programmable Clock Output 0
#define AT91C_PB30_ISI_HSYNC (AT91C_PIO_PB30) // Image Sensor Horizontal Synchro
#define AT91C_PIO_PB31 (1 << 31) // Pin Controlled by PB31
#define AT91C_PB31_PCK1_0 (AT91C_PIO_PB31) // PMC Programmable Clock Output 1
#define AT91C_PB31_ISI_MCK (AT91C_PIO_PB31) // Image Sensor Reference Clock
#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4
#define AT91C_PB4_TXD0 (AT91C_PIO_PB4) // USART 0 Transmit Data
#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5
#define AT91C_PB5_RXD0 (AT91C_PIO_PB5) // USART 0 Receive Data
#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6
#define AT91C_PB6_TXD1 (AT91C_PIO_PB6) // USART 1 Transmit Data
#define AT91C_PB6_TCLK1 (AT91C_PIO_PB6) // Timer Counter 1 external clock input
#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7
#define AT91C_PB7_RXD1 (AT91C_PIO_PB7) // USART 1 Receive Data
#define AT91C_PB7_TCLK2 (AT91C_PIO_PB7) // Timer Counter 2 external clock input
#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8
#define AT91C_PB8_TXD2 (AT91C_PIO_PB8) // USART 2 Transmit Data
#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9
#define AT91C_PB9_RXD2 (AT91C_PIO_PB9) // USART 2 Receive Data
#define AT91C_PIO_PC0 (1 << 0) // Pin Controlled by PC0
#define AT91C_PC0_AD0 (AT91C_PIO_PC0) // ADC Analog Input 0
#define AT91C_PC0_SCK3 (AT91C_PIO_PC0) // USART 3 Serial Clock
#define AT91C_PIO_PC1 (1 << 1) // Pin Controlled by PC1
#define AT91C_PC1_AD1 (AT91C_PIO_PC1) // ADC Analog Input 1
#define AT91C_PC1_PCK0 (AT91C_PIO_PC1) // PMC Programmable Clock Output 0
#define AT91C_PIO_PC10 (1 << 10) // Pin Controlled by PC10
#define AT91C_PC10_A25_CFRNW (AT91C_PIO_PC10) // Address Bus[25]
#define AT91C_PC10_CTS3 (AT91C_PIO_PC10) // USART 3 Clear To Send
#define AT91C_PIO_PC11 (1 << 11) // Pin Controlled by PC11
#define AT91C_PC11_NCS2 (AT91C_PIO_PC11) // Chip Select Line 2
#define AT91C_PC11_SPI0_NPCS1 (AT91C_PIO_PC11) // SPI 0 Peripheral Chip Select 1
#define AT91C_PIO_PC12 (1 << 12) // Pin Controlled by PC12
#define AT91C_PC12_IRQ0 (AT91C_PIO_PC12) // External Interrupt 0
#define AT91C_PC12_NCS7 (AT91C_PIO_PC12) // Chip Select Line 7
#define AT91C_PIO_PC13 (1 << 13) // Pin Controlled by PC13
#define AT91C_PC13_FIQ (AT91C_PIO_PC13) // AIC Fast Interrupt Input
#define AT91C_PC13_NCS6 (AT91C_PIO_PC13) // Chip Select Line 6
#define AT91C_PIO_PC14 (1 << 14) // Pin Controlled by PC14
#define AT91C_PC14_NCS3_NANDCS (AT91C_PIO_PC14) // Chip Select Line 3
#define AT91C_PC14_IRQ2 (AT91C_PIO_PC14) // External Interrupt 2
#define AT91C_PIO_PC15 (1 << 15) // Pin Controlled by PC15
#define AT91C_PC15_NWAIT (AT91C_PIO_PC15) // External Wait Signal
#define AT91C_PC15_IRQ1 (AT91C_PIO_PC15) // External Interrupt 1
#define AT91C_PIO_PC16 (1 << 16) // Pin Controlled by PC16
#define AT91C_PC16_D16 (AT91C_PIO_PC16) // Data Bus[16]
#define AT91C_PC16_SPI0_NPCS2 (AT91C_PIO_PC16) // SPI 0 Peripheral Chip Select 2
#define AT91C_PIO_PC17 (1 << 17) // Pin Controlled by PC17
#define AT91C_PC17_D17 (AT91C_PIO_PC17) // Data Bus[17]
#define AT91C_PC17_SPI0_NPCS3 (AT91C_PIO_PC17) // SPI 0 Peripheral Chip Select 3
#define AT91C_PIO_PC18 (1 << 18) // Pin Controlled by PC18
#define AT91C_PC18_D18 (AT91C_PIO_PC18) // Data Bus[18]
#define AT91C_PC18_SPI1_NPCS1_1 (AT91C_PIO_PC18) // SPI 1 Peripheral Chip Select 1
#define AT91C_PIO_PC19 (1 << 19) // Pin Controlled by PC19
#define AT91C_PC19_D19 (AT91C_PIO_PC19) // Data Bus[19]
#define AT91C_PC19_SPI1_NPCS2_1 (AT91C_PIO_PC19) // SPI 1 Peripheral Chip Select 2
#define AT91C_PIO_PC2 (1 << 2) // Pin Controlled by PC2
#define AT91C_PC2_AD2 (AT91C_PIO_PC2) // ADC Analog Input 2
#define AT91C_PC2_PCK1 (AT91C_PIO_PC2) // PMC Programmable Clock Output 1
#define AT91C_PIO_PC20 (1 << 20) // Pin Controlled by PC20
#define AT91C_PC20_D20 (AT91C_PIO_PC20) // Data Bus[20]
#define AT91C_PC20_SPI1_NPCS3_1 (AT91C_PIO_PC20) // SPI 1 Peripheral Chip Select 3
#define AT91C_PIO_PC21 (1 << 21) // Pin Controlled by PC21
#define AT91C_PC21_D21 (AT91C_PIO_PC21) // Data Bus[21]
#define AT91C_PC21_EF100 (AT91C_PIO_PC21) // Ethernet MAC Force 100 Mbits/sec
#define AT91C_PIO_PC22 (1 << 22) // Pin Controlled by PC22
#define AT91C_PC22_D22 (AT91C_PIO_PC22) // Data Bus[22]
#define AT91C_PC22_TCLK5 (AT91C_PIO_PC22) // Timer Counter 5 external clock input
#define AT91C_PIO_PC23 (1 << 23) // Pin Controlled by PC23
#define AT91C_PC23_D23 (AT91C_PIO_PC23) // Data Bus[23]
#define AT91C_PIO_PC24 (1 << 24) // Pin Controlled by PC24
#define AT91C_PC24_D24 (AT91C_PIO_PC24) // Data Bus[24]
#define AT91C_PIO_PC25 (1 << 25) // Pin Controlled by PC25
#define AT91C_PC25_D25 (AT91C_PIO_PC25) // Data Bus[25]
#define AT91C_PIO_PC26 (1 << 26) // Pin Controlled by PC26
#define AT91C_PC26_D26 (AT91C_PIO_PC26) // Data Bus[26]
#define AT91C_PIO_PC27 (1 << 27) // Pin Controlled by PC27
#define AT91C_PC27_D27 (AT91C_PIO_PC27) // Data Bus[27]
#define AT91C_PIO_PC28 (1 << 28) // Pin Controlled by PC28
#define AT91C_PC28_D28 (AT91C_PIO_PC28) // Data Bus[28]
#define AT91C_PIO_PC29 (1 << 29) // Pin Controlled by PC29
#define AT91C_PC29_D29 (AT91C_PIO_PC29) // Data Bus[29]
#define AT91C_PIO_PC3 (1 << 3) // Pin Controlled by PC3
#define AT91C_PC3_AD3 (AT91C_PIO_PC3) // ADC Analog Input 3
#define AT91C_PC3_SPI1_NPCS3_0 (AT91C_PIO_PC3) // SPI 1 Peripheral Chip Select 3
#define AT91C_PIO_PC30 (1 << 30) // Pin Controlled by PC30
#define AT91C_PC30_D30 (AT91C_PIO_PC30) // Data Bus[30]
#define AT91C_PIO_PC31 (1 << 31) // Pin Controlled by PC31
#define AT91C_PC31_D31 (AT91C_PIO_PC31) // Data Bus[31]
#define AT91C_PIO_PC4 (1 << 4) // Pin Controlled by PC4
#define AT91C_PC4_A23 (AT91C_PIO_PC4) // Address Bus[23]
#define AT91C_PC4_SPI1_NPCS2_0 (AT91C_PIO_PC4) // SPI 1 Peripheral Chip Select 2
#define AT91C_PIO_PC5 (1 << 5) // Pin Controlled by PC5
#define AT91C_PC5_A24 (AT91C_PIO_PC5) // Address Bus[24]
#define AT91C_PC5_SPI1_NPCS1_0 (AT91C_PIO_PC5) // SPI 1 Peripheral Chip Select 1
#define AT91C_PIO_PC6 (1 << 6) // Pin Controlled by PC6
#define AT91C_PC6_TIOB2 (AT91C_PIO_PC6) // Timer Counter 2 Multipurpose Timer I/O Pin B
#define AT91C_PC6_CFCE1 (AT91C_PIO_PC6) // Compact Flash Enable 1
#define AT91C_PIO_PC7 (1 << 7) // Pin Controlled by PC7
#define AT91C_PC7_TIOB1 (AT91C_PIO_PC7) // Timer Counter 1 Multipurpose Timer I/O Pin B
#define AT91C_PC7_CFCE2 (AT91C_PIO_PC7) // Compact Flash Enable 2
#define AT91C_PIO_PC8 (1 << 8) // Pin Controlled by PC8
#define AT91C_PC8_NCS4_CFCS0 (AT91C_PIO_PC8) // Chip Select Line 4
#define AT91C_PC8_RTS3 (AT91C_PIO_PC8) // USART 3 Ready To Send
#define AT91C_PIO_PC9 (1 << 9) // Pin Controlled by PC9
#define AT91C_PC9_NCS5_CFCS1 (AT91C_PIO_PC9) // Chip Select Line 5
#define AT91C_PC9_TIOB0 (AT91C_PIO_PC9) // Timer Counter 0 Multipurpose Timer I/O Pin B
// *****************************************************************************
// PERIPHERAL ID DEFINITIONS FOR AT91SAM9XE256
// *****************************************************************************
#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)
#define AT91C_ID_SYS ( 1) // System Controller
#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A
#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B
#define AT91C_ID_PIOC ( 4) // Parallel IO Controller C
#define AT91C_ID_ADC ( 5) // ADC
#define AT91C_ID_US0 ( 6) // USART 0
#define AT91C_ID_US1 ( 7) // USART 1
#define AT91C_ID_US2 ( 8) // USART 2
#define AT91C_ID_MCI ( 9) // Multimedia Card Interface 0
#define AT91C_ID_UDP (10) // USB Device Port
#define AT91C_ID_TWI0 (11) // Two-Wire Interface 0
#define AT91C_ID_SPI0 (12) // Serial Peripheral Interface 0
#define AT91C_ID_SPI1 (13) // Serial Peripheral Interface 1
#define AT91C_ID_SSC0 (14) // Serial Synchronous Controller 0
#define AT91C_ID_TC0 (17) // Timer Counter 0
#define AT91C_ID_TC1 (18) // Timer Counter 1
#define AT91C_ID_TC2 (19) // Timer Counter 2
#define AT91C_ID_UHP (20) // USB Host Port
#define AT91C_ID_EMAC (21) // Ethernet Mac
#define AT91C_ID_HISI (22) // Image Sensor Interface
#define AT91C_ID_US3 (23) // USART 3
#define AT91C_ID_US4 (24) // USART 4
#define AT91C_ID_TWI1 (25) // Two-Wire Interface 1
#define AT91C_ID_TC3 (26) // Timer Counter 3
#define AT91C_ID_TC4 (27) // Timer Counter 4
#define AT91C_ID_TC5 (28) // Timer Counter 5
#define AT91C_ID_IRQ0 (29) // Advanced Interrupt Controller (IRQ0)
#define AT91C_ID_IRQ1 (30) // Advanced Interrupt Controller (IRQ1)
#define AT91C_ID_IRQ2 (31) // Advanced Interrupt Controller (IRQ2)
#define AT91C_ALL_INT (0xFFFE7FFF) // ALL VALID INTERRUPTS
// *****************************************************************************
// BASE ADDRESS DEFINITIONS FOR AT91SAM9XE256
// *****************************************************************************
#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFFD00) // (SYS) Base Address
#define AT91C_BASE_EBI (AT91_CAST(AT91PS_EBI) 0xFFFFEA00) // (EBI) Base Address
#define AT91C_BASE_HECC (AT91_CAST(AT91PS_ECC) 0xFFFFE800) // (HECC) Base Address
#define AT91C_BASE_SDRAMC (AT91_CAST(AT91PS_SDRAMC) 0xFFFFEA00) // (SDRAMC) Base Address
#define AT91C_BASE_SMC (AT91_CAST(AT91PS_SMC) 0xFFFFEC00) // (SMC) Base Address
#define AT91C_BASE_MATRIX (AT91_CAST(AT91PS_MATRIX) 0xFFFFEE00) // (MATRIX) Base Address
#define AT91C_BASE_CCFG (AT91_CAST(AT91PS_CCFG) 0xFFFFEF10) // (CCFG) Base Address
#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address
#define AT91C_BASE_PIOC (AT91_CAST(AT91PS_PIO) 0xFFFFF800) // (PIOC) Base Address
#define AT91C_BASE_EFC (AT91_CAST(AT91PS_EFC) 0xFFFFFA00) // (EFC) Base Address
#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
#define AT91C_BASE_SHDWC (AT91_CAST(AT91PS_SHDWC) 0xFFFFFD10) // (SHDWC) Base Address
#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
#define AT91C_BASE_TC3 (AT91_CAST(AT91PS_TC) 0xFFFDC000) // (TC3) Base Address
#define AT91C_BASE_TC4 (AT91_CAST(AT91PS_TC) 0xFFFDC040) // (TC4) Base Address
#define AT91C_BASE_TC5 (AT91_CAST(AT91PS_TC) 0xFFFDC080) // (TC5) Base Address
#define AT91C_BASE_TCB0 (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB0) Base Address
#define AT91C_BASE_TCB1 (AT91_CAST(AT91PS_TCB) 0xFFFDC000) // (TCB1) Base Address
#define AT91C_BASE_PDC_MCI (AT91_CAST(AT91PS_PDC) 0xFFFA8100) // (PDC_MCI) Base Address
#define AT91C_BASE_MCI (AT91_CAST(AT91PS_MCI) 0xFFFA8000) // (MCI) Base Address
#define AT91C_BASE_PDC_TWI0 (AT91_CAST(AT91PS_PDC) 0xFFFAC100) // (PDC_TWI0) Base Address
#define AT91C_BASE_TWI0 (AT91_CAST(AT91PS_TWI) 0xFFFAC000) // (TWI0) Base Address
#define AT91C_BASE_PDC_TWI1 (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_TWI1) Base Address
#define AT91C_BASE_TWI1 (AT91_CAST(AT91PS_TWI) 0xFFFD8000) // (TWI1) Base Address
#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFB0100) // (PDC_US0) Base Address
#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFB0000) // (US0) Base Address
#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFB4100) // (PDC_US1) Base Address
#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFB4000) // (US1) Base Address
#define AT91C_BASE_PDC_US2 (AT91_CAST(AT91PS_PDC) 0xFFFB8100) // (PDC_US2) Base Address
#define AT91C_BASE_US2 (AT91_CAST(AT91PS_USART) 0xFFFB8000) // (US2) Base Address
#define AT91C_BASE_PDC_US3 (AT91_CAST(AT91PS_PDC) 0xFFFD0100) // (PDC_US3) Base Address
#define AT91C_BASE_US3 (AT91_CAST(AT91PS_USART) 0xFFFD0000) // (US3) Base Address
#define AT91C_BASE_PDC_US4 (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_US4) Base Address
#define AT91C_BASE_US4 (AT91_CAST(AT91PS_USART) 0xFFFD4000) // (US4) Base Address
#define AT91C_BASE_PDC_SSC0 (AT91_CAST(AT91PS_PDC) 0xFFFBC100) // (PDC_SSC0) Base Address
#define AT91C_BASE_SSC0 (AT91_CAST(AT91PS_SSC) 0xFFFBC000) // (SSC0) Base Address
#define AT91C_BASE_PDC_SPI0 (AT91_CAST(AT91PS_PDC) 0xFFFC8100) // (PDC_SPI0) Base Address
#define AT91C_BASE_SPI0 (AT91_CAST(AT91PS_SPI) 0xFFFC8000) // (SPI0) Base Address
#define AT91C_BASE_PDC_SPI1 (AT91_CAST(AT91PS_PDC) 0xFFFCC100) // (PDC_SPI1) Base Address
#define AT91C_BASE_SPI1 (AT91_CAST(AT91PS_SPI) 0xFFFCC000) // (SPI1) Base Address
#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_ADC) Base Address
#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFE0000) // (ADC) Base Address
#define AT91C_BASE_EMACB (AT91_CAST(AT91PS_EMAC) 0xFFFC4000) // (EMACB) Base Address
#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFA4000) // (UDP) Base Address
#define AT91C_BASE_UHP (AT91_CAST(AT91PS_UHP) 0x00500000) // (UHP) Base Address
#define AT91C_BASE_HISI (AT91_CAST(AT91PS_ISI) 0xFFFC0000) // (HISI) Base Address
// *****************************************************************************
// MEMORY MAPPING DEFINITIONS FOR AT91SAM9XE256
// *****************************************************************************
// IROM
#define AT91C_IROM (0x00100000) // Internal ROM base address
#define AT91C_IROM_SIZE (0x00008000) // Internal ROM size in byte (32 Kbytes)
// ISRAM
#define AT91C_ISRAM (0x00300000) // Maximum IRAM Area : 32Kbyte base address
#define AT91C_ISRAM_SIZE (0x00008000) // Maximum IRAM Area : 32Kbyte size in byte (32 Kbytes)
// ISRAM_MIN
#define AT91C_ISRAM_MIN (0x00300000) // Minimun IRAM Area : 32Kbyte base address
#define AT91C_ISRAM_MIN_SIZE (0x00008000) // Minimun IRAM Area : 32Kbyte size in byte (32 Kbytes)
// IFLASH
#define AT91C_IFLASH (0x00200000) // Maximum IFLASH Area : 256Kbyte base address
#define AT91C_IFLASH_SIZE (0x00040000) // Maximum IFLASH Area : 256Kbyte size in byte (256 Kbytes)
#define AT91C_IFLASH_PAGE_SIZE (512) // Maximum IFLASH Area : 256Kbyte Page Size: 512 bytes
#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Maximum IFLASH Area : 256Kbyte Lock Region Size: 16 Kbytes
#define AT91C_IFLASH_NB_OF_PAGES (512) // Maximum IFLASH Area : 256Kbyte Number of Pages: 512 bytes
#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Maximum IFLASH Area : 256Kbyte Number of Lock Bits: 16 bytes
// EBI_CS0
#define AT91C_EBI_CS0 (0x10000000) // EBI Chip Select 0 base address
#define AT91C_EBI_CS0_SIZE (0x10000000) // EBI Chip Select 0 size in byte (262144 Kbytes)
// EBI_CS1
#define AT91C_EBI_CS1 (0x20000000) // EBI Chip Select 1 base address
#define AT91C_EBI_CS1_SIZE (0x10000000) // EBI Chip Select 1 size in byte (262144 Kbytes)
// EBI_SDRAM
#define AT91C_EBI_SDRAM (0x20000000) // SDRAM on EBI Chip Select 1 base address
#define AT91C_EBI_SDRAM_SIZE (0x10000000) // SDRAM on EBI Chip Select 1 size in byte (262144 Kbytes)
// EBI_SDRAM_16BIT
#define AT91C_EBI_SDRAM_16BIT (0x20000000) // SDRAM on EBI Chip Select 1 base address
#define AT91C_EBI_SDRAM_16BIT_SIZE (0x02000000) // SDRAM on EBI Chip Select 1 size in byte (32768 Kbytes)
// EBI_SDRAM_32BIT
#define AT91C_EBI_SDRAM_32BIT (0x20000000) // SDRAM on EBI Chip Select 1 base address
#define AT91C_EBI_SDRAM_32BIT_SIZE (0x04000000) // SDRAM on EBI Chip Select 1 size in byte (65536 Kbytes)
// EBI_CS2
#define AT91C_EBI_CS2 (0x30000000) // EBI Chip Select 2 base address
#define AT91C_EBI_CS2_SIZE (0x10000000) // EBI Chip Select 2 size in byte (262144 Kbytes)
// EBI_CS3
#define AT91C_EBI_CS3 (0x40000000) // EBI Chip Select 3 base address
#define AT91C_EBI_CS3_SIZE (0x10000000) // EBI Chip Select 3 size in byte (262144 Kbytes)
// EBI_SM
#define AT91C_EBI_SM (0x40000000) // SmartMedia on Chip Select 3 base address
#define AT91C_EBI_SM_SIZE (0x10000000) // SmartMedia on Chip Select 3 size in byte (262144 Kbytes)
// EBI_CS4
#define AT91C_EBI_CS4 (0x50000000) // EBI Chip Select 4 base address
#define AT91C_EBI_CS4_SIZE (0x10000000) // EBI Chip Select 4 size in byte (262144 Kbytes)
// EBI_CF0
#define AT91C_EBI_CF0 (0x50000000) // CompactFlash 0 on Chip Select 4 base address
#define AT91C_EBI_CF0_SIZE (0x10000000) // CompactFlash 0 on Chip Select 4 size in byte (262144 Kbytes)
// EBI_CS5
#define AT91C_EBI_CS5 (0x60000000) // EBI Chip Select 5 base address
#define AT91C_EBI_CS5_SIZE (0x10000000) // EBI Chip Select 5 size in byte (262144 Kbytes)
// EBI_CF1
#define AT91C_EBI_CF1 (0x60000000) // CompactFlash 1 on Chip Select 5 base address
#define AT91C_EBI_CF1_SIZE (0x10000000) // CompactFlash 1 on Chip Select 5 size in byte (262144 Kbytes)
// EBI_CS6
#define AT91C_EBI_CS6 (0x70000000) // EBI Chip Select 6 base address
#define AT91C_EBI_CS6_SIZE (0x10000000) // EBI Chip Select 6 size in byte (262144 Kbytes)
// EBI_CS7
#define AT91C_EBI_CS7 (0x80000000) // EBI Chip Select 7 base address
#define AT91C_EBI_CS7_SIZE (0x10000000) // EBI Chip Select 7 size in byte (262144 Kbytes)
#endif
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe256/AT91SAM9XE256.h | C | oos | 306,022 |
// ----------------------------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ----------------------------------------------------------------------------
// Copyright (c) 2006, Atmel Corporation
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the disclaimer below.
//
// - Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the disclaimer below in the documentation and/or
// other materials provided with the distribution.
//
// Atmel's name may not be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ----------------------------------------------------------------------------
// File Name : AT91SAM9XE512.h
// Object : AT91SAM9XE512 definitions
// Generated : AT91 SW Application Group 02/13/2008 (18:25:59)
//
// CVS Reference : /AT91SAM9XE512.pl/1.16/Wed Jan 30 14:02:22 2008//
// CVS Reference : /SYS_SAM9260.pl/1.2/Wed Feb 13 13:29:23 2008//
// CVS Reference : /HMATRIX1_SAM9260.pl/1.7/Mon Apr 23 10:39:45 2007//
// CVS Reference : /CCR_SAM9260.pl/1.2/Mon Apr 16 10:47:39 2007//
// CVS Reference : /PMC_SAM9262.pl/1.4/Mon Mar 7 18:03:13 2005//
// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//
// CVS Reference : /HSDRAMC1_6100A.pl/1.2/Mon Aug 9 10:52:25 2004//
// CVS Reference : /HSMC3_6105A.pl/1.4/Tue Nov 16 09:16:23 2004//
// CVS Reference : /AIC_6075A.pl/1.1/Mon Jul 12 17:04:01 2004//
// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005//
// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005//
// CVS Reference : /RSTC_6098A.pl/1.3/Thu Nov 4 13:57:00 2004//
// CVS Reference : /SHDWC_6122A.pl/1.3/Wed Oct 6 14:16:58 2004//
// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004//
// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004//
// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004//
// CVS Reference : /EFC2_IGS036.pl/1.2/Fri Nov 10 10:47:53 2006//
// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005//
// CVS Reference : /MCI_6101E.pl/1.1/Fri Jun 3 13:20:23 2005//
// CVS Reference : /TWI_6061B.pl/1.2/Fri Aug 4 08:53:02 2006//
// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004//
// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
// CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005//
// CVS Reference : /UDP_6ept_puon.pl/1.1/Wed Aug 30 14:20:53 2006//
// CVS Reference : /UHP_6127A.pl/1.1/Wed Feb 23 16:03:17 2005//
// CVS Reference : /EBI_SAM9260.pl/1.1/Fri Sep 30 12:12:14 2005//
// CVS Reference : /HECC_6143A.pl/1.1/Wed Feb 9 17:16:57 2005//
// CVS Reference : /ISI_xxxxx.pl/1.3/Thu Mar 3 11:11:48 2005//
// ----------------------------------------------------------------------------
#ifndef AT91SAM9XE512_H
#define AT91SAM9XE512_H
#ifndef __ASSEMBLY__
typedef volatile unsigned int AT91_REG;// Hardware register definition
#define AT91_CAST(a) (a)
#else
#define AT91_CAST(a)
#endif
// *****************************************************************************
// SOFTWARE API DEFINITION FOR System Peripherals
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_SYS {
AT91_REG Reserved0[2560]; //
AT91_REG ECC_CR; // ECC reset register
AT91_REG ECC_MR; // ECC Page size register
AT91_REG ECC_SR; // ECC Status register
AT91_REG ECC_PR; // ECC Parity register
AT91_REG ECC_NPR; // ECC Parity N register
AT91_REG Reserved1[58]; //
AT91_REG ECC_VR; // ECC Version register
AT91_REG Reserved2[64]; //
AT91_REG SDRAMC_MR; // SDRAM Controller Mode Register
AT91_REG SDRAMC_TR; // SDRAM Controller Refresh Timer Register
AT91_REG SDRAMC_CR; // SDRAM Controller Configuration Register
AT91_REG SDRAMC_HSR; // SDRAM Controller High Speed Register
AT91_REG SDRAMC_LPR; // SDRAM Controller Low Power Register
AT91_REG SDRAMC_IER; // SDRAM Controller Interrupt Enable Register
AT91_REG SDRAMC_IDR; // SDRAM Controller Interrupt Disable Register
AT91_REG SDRAMC_IMR; // SDRAM Controller Interrupt Mask Register
AT91_REG SDRAMC_ISR; // SDRAM Controller Interrupt Mask Register
AT91_REG SDRAMC_MDR; // SDRAM Memory Device Register
AT91_REG Reserved3[118]; //
AT91_REG SMC_SETUP0; // Setup Register for CS 0
AT91_REG SMC_PULSE0; // Pulse Register for CS 0
AT91_REG SMC_CYCLE0; // Cycle Register for CS 0
AT91_REG SMC_CTRL0; // Control Register for CS 0
AT91_REG SMC_SETUP1; // Setup Register for CS 1
AT91_REG SMC_PULSE1; // Pulse Register for CS 1
AT91_REG SMC_CYCLE1; // Cycle Register for CS 1
AT91_REG SMC_CTRL1; // Control Register for CS 1
AT91_REG SMC_SETUP2; // Setup Register for CS 2
AT91_REG SMC_PULSE2; // Pulse Register for CS 2
AT91_REG SMC_CYCLE2; // Cycle Register for CS 2
AT91_REG SMC_CTRL2; // Control Register for CS 2
AT91_REG SMC_SETUP3; // Setup Register for CS 3
AT91_REG SMC_PULSE3; // Pulse Register for CS 3
AT91_REG SMC_CYCLE3; // Cycle Register for CS 3
AT91_REG SMC_CTRL3; // Control Register for CS 3
AT91_REG SMC_SETUP4; // Setup Register for CS 4
AT91_REG SMC_PULSE4; // Pulse Register for CS 4
AT91_REG SMC_CYCLE4; // Cycle Register for CS 4
AT91_REG SMC_CTRL4; // Control Register for CS 4
AT91_REG SMC_SETUP5; // Setup Register for CS 5
AT91_REG SMC_PULSE5; // Pulse Register for CS 5
AT91_REG SMC_CYCLE5; // Cycle Register for CS 5
AT91_REG SMC_CTRL5; // Control Register for CS 5
AT91_REG SMC_SETUP6; // Setup Register for CS 6
AT91_REG SMC_PULSE6; // Pulse Register for CS 6
AT91_REG SMC_CYCLE6; // Cycle Register for CS 6
AT91_REG SMC_CTRL6; // Control Register for CS 6
AT91_REG SMC_SETUP7; // Setup Register for CS 7
AT91_REG SMC_PULSE7; // Pulse Register for CS 7
AT91_REG SMC_CYCLE7; // Cycle Register for CS 7
AT91_REG SMC_CTRL7; // Control Register for CS 7
AT91_REG Reserved4[96]; //
AT91_REG MATRIX_MCFG0; // Master Configuration Register 0 (ram96k)
AT91_REG MATRIX_MCFG1; // Master Configuration Register 1 (rom)
AT91_REG MATRIX_MCFG2; // Master Configuration Register 2 (hperiphs)
AT91_REG MATRIX_MCFG3; // Master Configuration Register 3 (ebi)
AT91_REG MATRIX_MCFG4; // Master Configuration Register 4 (bridge)
AT91_REG MATRIX_MCFG5; // Master Configuration Register 5 (mailbox)
AT91_REG MATRIX_MCFG6; // Master Configuration Register 6 (ram16k)
AT91_REG MATRIX_MCFG7; // Master Configuration Register 7 (teak_prog)
AT91_REG Reserved5[8]; //
AT91_REG MATRIX_SCFG0; // Slave Configuration Register 0 (ram96k)
AT91_REG MATRIX_SCFG1; // Slave Configuration Register 1 (rom)
AT91_REG MATRIX_SCFG2; // Slave Configuration Register 2 (hperiphs)
AT91_REG MATRIX_SCFG3; // Slave Configuration Register 3 (ebi)
AT91_REG MATRIX_SCFG4; // Slave Configuration Register 4 (bridge)
AT91_REG Reserved6[11]; //
AT91_REG MATRIX_PRAS0; // PRAS0 (ram0)
AT91_REG MATRIX_PRBS0; // PRBS0 (ram0)
AT91_REG MATRIX_PRAS1; // PRAS1 (ram1)
AT91_REG MATRIX_PRBS1; // PRBS1 (ram1)
AT91_REG MATRIX_PRAS2; // PRAS2 (ram2)
AT91_REG MATRIX_PRBS2; // PRBS2 (ram2)
AT91_REG MATRIX_PRAS3; // PRAS3 : usb_dev_hs
AT91_REG MATRIX_PRBS3; // PRBS3 : usb_dev_hs
AT91_REG MATRIX_PRAS4; // PRAS4 : ebi
AT91_REG MATRIX_PRBS4; // PRBS4 : ebi
AT91_REG Reserved7[22]; //
AT91_REG MATRIX_MRCR; // Master Remp Control Register
AT91_REG Reserved8[6]; //
AT91_REG CCFG_EBICSA; // EBI Chip Select Assignement Register
AT91_REG Reserved9[3]; //
AT91_REG MATRIX_TEAKCFG; // Slave 7 (teak_prog) Special Function Register
AT91_REG Reserved10[51]; //
AT91_REG CCFG_MATRIXVERSION; // Version Register
AT91_REG AIC_SMR[32]; // Source Mode Register
AT91_REG AIC_SVR[32]; // Source Vector Register
AT91_REG AIC_IVR; // IRQ Vector Register
AT91_REG AIC_FVR; // FIQ Vector Register
AT91_REG AIC_ISR; // Interrupt Status Register
AT91_REG AIC_IPR; // Interrupt Pending Register
AT91_REG AIC_IMR; // Interrupt Mask Register
AT91_REG AIC_CISR; // Core Interrupt Status Register
AT91_REG Reserved11[2]; //
AT91_REG AIC_IECR; // Interrupt Enable Command Register
AT91_REG AIC_IDCR; // Interrupt Disable Command Register
AT91_REG AIC_ICCR; // Interrupt Clear Command Register
AT91_REG AIC_ISCR; // Interrupt Set Command Register
AT91_REG AIC_EOICR; // End of Interrupt Command Register
AT91_REG AIC_SPU; // Spurious Vector Register
AT91_REG AIC_DCR; // Debug Control Register (Protect)
AT91_REG Reserved12[1]; //
AT91_REG AIC_FFER; // Fast Forcing Enable Register
AT91_REG AIC_FFDR; // Fast Forcing Disable Register
AT91_REG AIC_FFSR; // Fast Forcing Status Register
AT91_REG Reserved13[45]; //
AT91_REG DBGU_CR; // Control Register
AT91_REG DBGU_MR; // Mode Register
AT91_REG DBGU_IER; // Interrupt Enable Register
AT91_REG DBGU_IDR; // Interrupt Disable Register
AT91_REG DBGU_IMR; // Interrupt Mask Register
AT91_REG DBGU_CSR; // Channel Status Register
AT91_REG DBGU_RHR; // Receiver Holding Register
AT91_REG DBGU_THR; // Transmitter Holding Register
AT91_REG DBGU_BRGR; // Baud Rate Generator Register
AT91_REG Reserved14[7]; //
AT91_REG DBGU_CIDR; // Chip ID Register
AT91_REG DBGU_EXID; // Chip ID Extension Register
AT91_REG DBGU_FNTR; // Force NTRST Register
AT91_REG Reserved15[45]; //
AT91_REG DBGU_RPR; // Receive Pointer Register
AT91_REG DBGU_RCR; // Receive Counter Register
AT91_REG DBGU_TPR; // Transmit Pointer Register
AT91_REG DBGU_TCR; // Transmit Counter Register
AT91_REG DBGU_RNPR; // Receive Next Pointer Register
AT91_REG DBGU_RNCR; // Receive Next Counter Register
AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
AT91_REG DBGU_TNCR; // Transmit Next Counter Register
AT91_REG DBGU_PTCR; // PDC Transfer Control Register
AT91_REG DBGU_PTSR; // PDC Transfer Status Register
AT91_REG Reserved16[54]; //
AT91_REG PIOA_PER; // PIO Enable Register
AT91_REG PIOA_PDR; // PIO Disable Register
AT91_REG PIOA_PSR; // PIO Status Register
AT91_REG Reserved17[1]; //
AT91_REG PIOA_OER; // Output Enable Register
AT91_REG PIOA_ODR; // Output Disable Registerr
AT91_REG PIOA_OSR; // Output Status Register
AT91_REG Reserved18[1]; //
AT91_REG PIOA_IFER; // Input Filter Enable Register
AT91_REG PIOA_IFDR; // Input Filter Disable Register
AT91_REG PIOA_IFSR; // Input Filter Status Register
AT91_REG Reserved19[1]; //
AT91_REG PIOA_SODR; // Set Output Data Register
AT91_REG PIOA_CODR; // Clear Output Data Register
AT91_REG PIOA_ODSR; // Output Data Status Register
AT91_REG PIOA_PDSR; // Pin Data Status Register
AT91_REG PIOA_IER; // Interrupt Enable Register
AT91_REG PIOA_IDR; // Interrupt Disable Register
AT91_REG PIOA_IMR; // Interrupt Mask Register
AT91_REG PIOA_ISR; // Interrupt Status Register
AT91_REG PIOA_MDER; // Multi-driver Enable Register
AT91_REG PIOA_MDDR; // Multi-driver Disable Register
AT91_REG PIOA_MDSR; // Multi-driver Status Register
AT91_REG Reserved20[1]; //
AT91_REG PIOA_PPUDR; // Pull-up Disable Register
AT91_REG PIOA_PPUER; // Pull-up Enable Register
AT91_REG PIOA_PPUSR; // Pull-up Status Register
AT91_REG Reserved21[1]; //
AT91_REG PIOA_ASR; // Select A Register
AT91_REG PIOA_BSR; // Select B Register
AT91_REG PIOA_ABSR; // AB Select Status Register
AT91_REG Reserved22[9]; //
AT91_REG PIOA_OWER; // Output Write Enable Register
AT91_REG PIOA_OWDR; // Output Write Disable Register
AT91_REG PIOA_OWSR; // Output Write Status Register
AT91_REG Reserved23[213]; //
AT91_REG PIOB_PER; // PIO Enable Register
AT91_REG PIOB_PDR; // PIO Disable Register
AT91_REG PIOB_PSR; // PIO Status Register
AT91_REG Reserved24[1]; //
AT91_REG PIOB_OER; // Output Enable Register
AT91_REG PIOB_ODR; // Output Disable Registerr
AT91_REG PIOB_OSR; // Output Status Register
AT91_REG Reserved25[1]; //
AT91_REG PIOB_IFER; // Input Filter Enable Register
AT91_REG PIOB_IFDR; // Input Filter Disable Register
AT91_REG PIOB_IFSR; // Input Filter Status Register
AT91_REG Reserved26[1]; //
AT91_REG PIOB_SODR; // Set Output Data Register
AT91_REG PIOB_CODR; // Clear Output Data Register
AT91_REG PIOB_ODSR; // Output Data Status Register
AT91_REG PIOB_PDSR; // Pin Data Status Register
AT91_REG PIOB_IER; // Interrupt Enable Register
AT91_REG PIOB_IDR; // Interrupt Disable Register
AT91_REG PIOB_IMR; // Interrupt Mask Register
AT91_REG PIOB_ISR; // Interrupt Status Register
AT91_REG PIOB_MDER; // Multi-driver Enable Register
AT91_REG PIOB_MDDR; // Multi-driver Disable Register
AT91_REG PIOB_MDSR; // Multi-driver Status Register
AT91_REG Reserved27[1]; //
AT91_REG PIOB_PPUDR; // Pull-up Disable Register
AT91_REG PIOB_PPUER; // Pull-up Enable Register
AT91_REG PIOB_PPUSR; // Pull-up Status Register
AT91_REG Reserved28[1]; //
AT91_REG PIOB_ASR; // Select A Register
AT91_REG PIOB_BSR; // Select B Register
AT91_REG PIOB_ABSR; // AB Select Status Register
AT91_REG Reserved29[9]; //
AT91_REG PIOB_OWER; // Output Write Enable Register
AT91_REG PIOB_OWDR; // Output Write Disable Register
AT91_REG PIOB_OWSR; // Output Write Status Register
AT91_REG Reserved30[85]; //
AT91_REG PIOC_PER; // PIO Enable Register
AT91_REG PIOC_PDR; // PIO Disable Register
AT91_REG PIOC_PSR; // PIO Status Register
AT91_REG Reserved31[1]; //
AT91_REG PIOC_OER; // Output Enable Register
AT91_REG PIOC_ODR; // Output Disable Registerr
AT91_REG PIOC_OSR; // Output Status Register
AT91_REG Reserved32[1]; //
AT91_REG PIOC_IFER; // Input Filter Enable Register
AT91_REG PIOC_IFDR; // Input Filter Disable Register
AT91_REG PIOC_IFSR; // Input Filter Status Register
AT91_REG Reserved33[1]; //
AT91_REG PIOC_SODR; // Set Output Data Register
AT91_REG PIOC_CODR; // Clear Output Data Register
AT91_REG PIOC_ODSR; // Output Data Status Register
AT91_REG PIOC_PDSR; // Pin Data Status Register
AT91_REG PIOC_IER; // Interrupt Enable Register
AT91_REG PIOC_IDR; // Interrupt Disable Register
AT91_REG PIOC_IMR; // Interrupt Mask Register
AT91_REG PIOC_ISR; // Interrupt Status Register
AT91_REG PIOC_MDER; // Multi-driver Enable Register
AT91_REG PIOC_MDDR; // Multi-driver Disable Register
AT91_REG PIOC_MDSR; // Multi-driver Status Register
AT91_REG Reserved34[1]; //
AT91_REG PIOC_PPUDR; // Pull-up Disable Register
AT91_REG PIOC_PPUER; // Pull-up Enable Register
AT91_REG PIOC_PPUSR; // Pull-up Status Register
AT91_REG Reserved35[1]; //
AT91_REG PIOC_ASR; // Select A Register
AT91_REG PIOC_BSR; // Select B Register
AT91_REG PIOC_ABSR; // AB Select Status Register
AT91_REG Reserved36[9]; //
AT91_REG PIOC_OWER; // Output Write Enable Register
AT91_REG PIOC_OWDR; // Output Write Disable Register
AT91_REG PIOC_OWSR; // Output Write Status Register
AT91_REG Reserved37[85]; //
AT91_REG PMC_SCER; // System Clock Enable Register
AT91_REG PMC_SCDR; // System Clock Disable Register
AT91_REG PMC_SCSR; // System Clock Status Register
AT91_REG Reserved38[1]; //
AT91_REG PMC_PCER; // Peripheral Clock Enable Register
AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
AT91_REG PMC_PCSR; // Peripheral Clock Status Register
AT91_REG Reserved39[1]; //
AT91_REG PMC_MOR; // Main Oscillator Register
AT91_REG PMC_MCFR; // Main Clock Frequency Register
AT91_REG PMC_PLLAR; // PLL A Register
AT91_REG PMC_PLLBR; // PLL B Register
AT91_REG PMC_MCKR; // Master Clock Register
AT91_REG Reserved40[3]; //
AT91_REG PMC_PCKR[8]; // Programmable Clock Register
AT91_REG PMC_IER; // Interrupt Enable Register
AT91_REG PMC_IDR; // Interrupt Disable Register
AT91_REG PMC_SR; // Status Register
AT91_REG PMC_IMR; // Interrupt Mask Register
AT91_REG Reserved41[36]; //
AT91_REG RSTC_RCR; // Reset Control Register
AT91_REG RSTC_RSR; // Reset Status Register
AT91_REG RSTC_RMR; // Reset Mode Register
AT91_REG Reserved42[1]; //
AT91_REG SHDWC_SHCR; // Shut Down Control Register
AT91_REG SHDWC_SHMR; // Shut Down Mode Register
AT91_REG SHDWC_SHSR; // Shut Down Status Register
AT91_REG Reserved43[1]; //
AT91_REG RTTC_RTMR; // Real-time Mode Register
AT91_REG RTTC_RTAR; // Real-time Alarm Register
AT91_REG RTTC_RTVR; // Real-time Value Register
AT91_REG RTTC_RTSR; // Real-time Status Register
AT91_REG PITC_PIMR; // Period Interval Mode Register
AT91_REG PITC_PISR; // Period Interval Status Register
AT91_REG PITC_PIVR; // Period Interval Value Register
AT91_REG PITC_PIIR; // Period Interval Image Register
AT91_REG WDTC_WDCR; // Watchdog Control Register
AT91_REG WDTC_WDMR; // Watchdog Mode Register
AT91_REG WDTC_WDSR; // Watchdog Status Register
AT91_REG Reserved44[1]; //
AT91_REG SYS_GPBR[4]; // General Purpose Register
} AT91S_SYS, *AT91PS_SYS;
#else
#define SYS_GPBR (AT91_CAST(AT91_REG *) 0x00003D50) // (SYS_GPBR) General Purpose Register
#endif
// -------- GPBR : (SYS Offset: 0x3d50) GPBR General Purpose Register --------
#define AT91C_GPBR_GPRV (0x0 << 0) // (SYS) General Purpose Register Value
// *****************************************************************************
// SOFTWARE API DEFINITION FOR External Bus Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_EBI {
AT91_REG EBI_DUMMY; // Dummy register - Do not use
} AT91S_EBI, *AT91PS_EBI;
#else
#define EBI_DUMMY (AT91_CAST(AT91_REG *) 0x00000000) // (EBI_DUMMY) Dummy register - Do not use
#endif
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Error Correction Code controller
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_ECC {
AT91_REG ECC_CR; // ECC reset register
AT91_REG ECC_MR; // ECC Page size register
AT91_REG ECC_SR; // ECC Status register
AT91_REG ECC_PR; // ECC Parity register
AT91_REG ECC_NPR; // ECC Parity N register
AT91_REG Reserved0[58]; //
AT91_REG ECC_VR; // ECC Version register
} AT91S_ECC, *AT91PS_ECC;
#else
#define ECC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ECC_CR) ECC reset register
#define ECC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ECC_MR) ECC Page size register
#define ECC_SR (AT91_CAST(AT91_REG *) 0x00000008) // (ECC_SR) ECC Status register
#define ECC_PR (AT91_CAST(AT91_REG *) 0x0000000C) // (ECC_PR) ECC Parity register
#define ECC_NPR (AT91_CAST(AT91_REG *) 0x00000010) // (ECC_NPR) ECC Parity N register
#define ECC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (ECC_VR) ECC Version register
#endif
// -------- ECC_CR : (ECC Offset: 0x0) ECC reset register --------
#define AT91C_ECC_RST (0x1 << 0) // (ECC) ECC reset parity
// -------- ECC_MR : (ECC Offset: 0x4) ECC page size register --------
#define AT91C_ECC_PAGE_SIZE (0x3 << 0) // (ECC) Nand Flash page size
// -------- ECC_SR : (ECC Offset: 0x8) ECC status register --------
#define AT91C_ECC_RECERR (0x1 << 0) // (ECC) ECC error
#define AT91C_ECC_ECCERR (0x1 << 1) // (ECC) ECC single error
#define AT91C_ECC_MULERR (0x1 << 2) // (ECC) ECC_MULERR
// -------- ECC_PR : (ECC Offset: 0xc) ECC parity register --------
#define AT91C_ECC_BITADDR (0xF << 0) // (ECC) Bit address error
#define AT91C_ECC_WORDADDR (0xFFF << 4) // (ECC) address of the failing bit
// -------- ECC_NPR : (ECC Offset: 0x10) ECC N parity register --------
#define AT91C_ECC_NPARITY (0xFFFF << 0) // (ECC) ECC parity N
// -------- ECC_VR : (ECC Offset: 0xfc) ECC version register --------
#define AT91C_ECC_VR (0xF << 0) // (ECC) ECC version register
// *****************************************************************************
// SOFTWARE API DEFINITION FOR SDRAM Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_SDRAMC {
AT91_REG SDRAMC_MR; // SDRAM Controller Mode Register
AT91_REG SDRAMC_TR; // SDRAM Controller Refresh Timer Register
AT91_REG SDRAMC_CR; // SDRAM Controller Configuration Register
AT91_REG SDRAMC_HSR; // SDRAM Controller High Speed Register
AT91_REG SDRAMC_LPR; // SDRAM Controller Low Power Register
AT91_REG SDRAMC_IER; // SDRAM Controller Interrupt Enable Register
AT91_REG SDRAMC_IDR; // SDRAM Controller Interrupt Disable Register
AT91_REG SDRAMC_IMR; // SDRAM Controller Interrupt Mask Register
AT91_REG SDRAMC_ISR; // SDRAM Controller Interrupt Mask Register
AT91_REG SDRAMC_MDR; // SDRAM Memory Device Register
} AT91S_SDRAMC, *AT91PS_SDRAMC;
#else
#define SDRAMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (SDRAMC_MR) SDRAM Controller Mode Register
#define SDRAMC_TR (AT91_CAST(AT91_REG *) 0x00000004) // (SDRAMC_TR) SDRAM Controller Refresh Timer Register
#define SDRAMC_CR (AT91_CAST(AT91_REG *) 0x00000008) // (SDRAMC_CR) SDRAM Controller Configuration Register
#define SDRAMC_HSR (AT91_CAST(AT91_REG *) 0x0000000C) // (SDRAMC_HSR) SDRAM Controller High Speed Register
#define SDRAMC_LPR (AT91_CAST(AT91_REG *) 0x00000010) // (SDRAMC_LPR) SDRAM Controller Low Power Register
#define SDRAMC_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SDRAMC_IER) SDRAM Controller Interrupt Enable Register
#define SDRAMC_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SDRAMC_IDR) SDRAM Controller Interrupt Disable Register
#define SDRAMC_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SDRAMC_IMR) SDRAM Controller Interrupt Mask Register
#define SDRAMC_ISR (AT91_CAST(AT91_REG *) 0x00000020) // (SDRAMC_ISR) SDRAM Controller Interrupt Mask Register
#define SDRAMC_MDR (AT91_CAST(AT91_REG *) 0x00000024) // (SDRAMC_MDR) SDRAM Memory Device Register
#endif
// -------- SDRAMC_MR : (SDRAMC Offset: 0x0) SDRAM Controller Mode Register --------
#define AT91C_SDRAMC_MODE (0xF << 0) // (SDRAMC) Mode
#define AT91C_SDRAMC_MODE_NORMAL_CMD (0x0) // (SDRAMC) Normal Mode
#define AT91C_SDRAMC_MODE_NOP_CMD (0x1) // (SDRAMC) Issue a NOP Command at every access
#define AT91C_SDRAMC_MODE_PRCGALL_CMD (0x2) // (SDRAMC) Issue a All Banks Precharge Command at every access
#define AT91C_SDRAMC_MODE_LMR_CMD (0x3) // (SDRAMC) Issue a Load Mode Register at every access
#define AT91C_SDRAMC_MODE_RFSH_CMD (0x4) // (SDRAMC) Issue a Refresh
#define AT91C_SDRAMC_MODE_EXT_LMR_CMD (0x5) // (SDRAMC) Issue an Extended Load Mode Register
#define AT91C_SDRAMC_MODE_DEEP_CMD (0x6) // (SDRAMC) Enter Deep Power Mode
// -------- SDRAMC_TR : (SDRAMC Offset: 0x4) SDRAMC Refresh Timer Register --------
#define AT91C_SDRAMC_COUNT (0xFFF << 0) // (SDRAMC) Refresh Counter
// -------- SDRAMC_CR : (SDRAMC Offset: 0x8) SDRAM Configuration Register --------
#define AT91C_SDRAMC_NC (0x3 << 0) // (SDRAMC) Number of Column Bits
#define AT91C_SDRAMC_NC_8 (0x0) // (SDRAMC) 8 Bits
#define AT91C_SDRAMC_NC_9 (0x1) // (SDRAMC) 9 Bits
#define AT91C_SDRAMC_NC_10 (0x2) // (SDRAMC) 10 Bits
#define AT91C_SDRAMC_NC_11 (0x3) // (SDRAMC) 11 Bits
#define AT91C_SDRAMC_NR (0x3 << 2) // (SDRAMC) Number of Row Bits
#define AT91C_SDRAMC_NR_11 (0x0 << 2) // (SDRAMC) 11 Bits
#define AT91C_SDRAMC_NR_12 (0x1 << 2) // (SDRAMC) 12 Bits
#define AT91C_SDRAMC_NR_13 (0x2 << 2) // (SDRAMC) 13 Bits
#define AT91C_SDRAMC_NB (0x1 << 4) // (SDRAMC) Number of Banks
#define AT91C_SDRAMC_NB_2_BANKS (0x0 << 4) // (SDRAMC) 2 banks
#define AT91C_SDRAMC_NB_4_BANKS (0x1 << 4) // (SDRAMC) 4 banks
#define AT91C_SDRAMC_CAS (0x3 << 5) // (SDRAMC) CAS Latency
#define AT91C_SDRAMC_CAS_2 (0x2 << 5) // (SDRAMC) 2 cycles
#define AT91C_SDRAMC_CAS_3 (0x3 << 5) // (SDRAMC) 3 cycles
#define AT91C_SDRAMC_DBW (0x1 << 7) // (SDRAMC) Data Bus Width
#define AT91C_SDRAMC_DBW_32_BITS (0x0 << 7) // (SDRAMC) 32 Bits datas bus
#define AT91C_SDRAMC_DBW_16_BITS (0x1 << 7) // (SDRAMC) 16 Bits datas bus
#define AT91C_SDRAMC_TWR (0xF << 8) // (SDRAMC) Number of Write Recovery Time Cycles
#define AT91C_SDRAMC_TWR_0 (0x0 << 8) // (SDRAMC) Value : 0
#define AT91C_SDRAMC_TWR_1 (0x1 << 8) // (SDRAMC) Value : 1
#define AT91C_SDRAMC_TWR_2 (0x2 << 8) // (SDRAMC) Value : 2
#define AT91C_SDRAMC_TWR_3 (0x3 << 8) // (SDRAMC) Value : 3
#define AT91C_SDRAMC_TWR_4 (0x4 << 8) // (SDRAMC) Value : 4
#define AT91C_SDRAMC_TWR_5 (0x5 << 8) // (SDRAMC) Value : 5
#define AT91C_SDRAMC_TWR_6 (0x6 << 8) // (SDRAMC) Value : 6
#define AT91C_SDRAMC_TWR_7 (0x7 << 8) // (SDRAMC) Value : 7
#define AT91C_SDRAMC_TWR_8 (0x8 << 8) // (SDRAMC) Value : 8
#define AT91C_SDRAMC_TWR_9 (0x9 << 8) // (SDRAMC) Value : 9
#define AT91C_SDRAMC_TWR_10 (0xA << 8) // (SDRAMC) Value : 10
#define AT91C_SDRAMC_TWR_11 (0xB << 8) // (SDRAMC) Value : 11
#define AT91C_SDRAMC_TWR_12 (0xC << 8) // (SDRAMC) Value : 12
#define AT91C_SDRAMC_TWR_13 (0xD << 8) // (SDRAMC) Value : 13
#define AT91C_SDRAMC_TWR_14 (0xE << 8) // (SDRAMC) Value : 14
#define AT91C_SDRAMC_TWR_15 (0xF << 8) // (SDRAMC) Value : 15
#define AT91C_SDRAMC_TRC (0xF << 12) // (SDRAMC) Number of RAS Cycle Time Cycles
#define AT91C_SDRAMC_TRC_0 (0x0 << 12) // (SDRAMC) Value : 0
#define AT91C_SDRAMC_TRC_1 (0x1 << 12) // (SDRAMC) Value : 1
#define AT91C_SDRAMC_TRC_2 (0x2 << 12) // (SDRAMC) Value : 2
#define AT91C_SDRAMC_TRC_3 (0x3 << 12) // (SDRAMC) Value : 3
#define AT91C_SDRAMC_TRC_4 (0x4 << 12) // (SDRAMC) Value : 4
#define AT91C_SDRAMC_TRC_5 (0x5 << 12) // (SDRAMC) Value : 5
#define AT91C_SDRAMC_TRC_6 (0x6 << 12) // (SDRAMC) Value : 6
#define AT91C_SDRAMC_TRC_7 (0x7 << 12) // (SDRAMC) Value : 7
#define AT91C_SDRAMC_TRC_8 (0x8 << 12) // (SDRAMC) Value : 8
#define AT91C_SDRAMC_TRC_9 (0x9 << 12) // (SDRAMC) Value : 9
#define AT91C_SDRAMC_TRC_10 (0xA << 12) // (SDRAMC) Value : 10
#define AT91C_SDRAMC_TRC_11 (0xB << 12) // (SDRAMC) Value : 11
#define AT91C_SDRAMC_TRC_12 (0xC << 12) // (SDRAMC) Value : 12
#define AT91C_SDRAMC_TRC_13 (0xD << 12) // (SDRAMC) Value : 13
#define AT91C_SDRAMC_TRC_14 (0xE << 12) // (SDRAMC) Value : 14
#define AT91C_SDRAMC_TRC_15 (0xF << 12) // (SDRAMC) Value : 15
#define AT91C_SDRAMC_TRP (0xF << 16) // (SDRAMC) Number of RAS Precharge Time Cycles
#define AT91C_SDRAMC_TRP_0 (0x0 << 16) // (SDRAMC) Value : 0
#define AT91C_SDRAMC_TRP_1 (0x1 << 16) // (SDRAMC) Value : 1
#define AT91C_SDRAMC_TRP_2 (0x2 << 16) // (SDRAMC) Value : 2
#define AT91C_SDRAMC_TRP_3 (0x3 << 16) // (SDRAMC) Value : 3
#define AT91C_SDRAMC_TRP_4 (0x4 << 16) // (SDRAMC) Value : 4
#define AT91C_SDRAMC_TRP_5 (0x5 << 16) // (SDRAMC) Value : 5
#define AT91C_SDRAMC_TRP_6 (0x6 << 16) // (SDRAMC) Value : 6
#define AT91C_SDRAMC_TRP_7 (0x7 << 16) // (SDRAMC) Value : 7
#define AT91C_SDRAMC_TRP_8 (0x8 << 16) // (SDRAMC) Value : 8
#define AT91C_SDRAMC_TRP_9 (0x9 << 16) // (SDRAMC) Value : 9
#define AT91C_SDRAMC_TRP_10 (0xA << 16) // (SDRAMC) Value : 10
#define AT91C_SDRAMC_TRP_11 (0xB << 16) // (SDRAMC) Value : 11
#define AT91C_SDRAMC_TRP_12 (0xC << 16) // (SDRAMC) Value : 12
#define AT91C_SDRAMC_TRP_13 (0xD << 16) // (SDRAMC) Value : 13
#define AT91C_SDRAMC_TRP_14 (0xE << 16) // (SDRAMC) Value : 14
#define AT91C_SDRAMC_TRP_15 (0xF << 16) // (SDRAMC) Value : 15
#define AT91C_SDRAMC_TRCD (0xF << 20) // (SDRAMC) Number of RAS to CAS Delay Cycles
#define AT91C_SDRAMC_TRCD_0 (0x0 << 20) // (SDRAMC) Value : 0
#define AT91C_SDRAMC_TRCD_1 (0x1 << 20) // (SDRAMC) Value : 1
#define AT91C_SDRAMC_TRCD_2 (0x2 << 20) // (SDRAMC) Value : 2
#define AT91C_SDRAMC_TRCD_3 (0x3 << 20) // (SDRAMC) Value : 3
#define AT91C_SDRAMC_TRCD_4 (0x4 << 20) // (SDRAMC) Value : 4
#define AT91C_SDRAMC_TRCD_5 (0x5 << 20) // (SDRAMC) Value : 5
#define AT91C_SDRAMC_TRCD_6 (0x6 << 20) // (SDRAMC) Value : 6
#define AT91C_SDRAMC_TRCD_7 (0x7 << 20) // (SDRAMC) Value : 7
#define AT91C_SDRAMC_TRCD_8 (0x8 << 20) // (SDRAMC) Value : 8
#define AT91C_SDRAMC_TRCD_9 (0x9 << 20) // (SDRAMC) Value : 9
#define AT91C_SDRAMC_TRCD_10 (0xA << 20) // (SDRAMC) Value : 10
#define AT91C_SDRAMC_TRCD_11 (0xB << 20) // (SDRAMC) Value : 11
#define AT91C_SDRAMC_TRCD_12 (0xC << 20) // (SDRAMC) Value : 12
#define AT91C_SDRAMC_TRCD_13 (0xD << 20) // (SDRAMC) Value : 13
#define AT91C_SDRAMC_TRCD_14 (0xE << 20) // (SDRAMC) Value : 14
#define AT91C_SDRAMC_TRCD_15 (0xF << 20) // (SDRAMC) Value : 15
#define AT91C_SDRAMC_TRAS (0xF << 24) // (SDRAMC) Number of RAS Active Time Cycles
#define AT91C_SDRAMC_TRAS_0 (0x0 << 24) // (SDRAMC) Value : 0
#define AT91C_SDRAMC_TRAS_1 (0x1 << 24) // (SDRAMC) Value : 1
#define AT91C_SDRAMC_TRAS_2 (0x2 << 24) // (SDRAMC) Value : 2
#define AT91C_SDRAMC_TRAS_3 (0x3 << 24) // (SDRAMC) Value : 3
#define AT91C_SDRAMC_TRAS_4 (0x4 << 24) // (SDRAMC) Value : 4
#define AT91C_SDRAMC_TRAS_5 (0x5 << 24) // (SDRAMC) Value : 5
#define AT91C_SDRAMC_TRAS_6 (0x6 << 24) // (SDRAMC) Value : 6
#define AT91C_SDRAMC_TRAS_7 (0x7 << 24) // (SDRAMC) Value : 7
#define AT91C_SDRAMC_TRAS_8 (0x8 << 24) // (SDRAMC) Value : 8
#define AT91C_SDRAMC_TRAS_9 (0x9 << 24) // (SDRAMC) Value : 9
#define AT91C_SDRAMC_TRAS_10 (0xA << 24) // (SDRAMC) Value : 10
#define AT91C_SDRAMC_TRAS_11 (0xB << 24) // (SDRAMC) Value : 11
#define AT91C_SDRAMC_TRAS_12 (0xC << 24) // (SDRAMC) Value : 12
#define AT91C_SDRAMC_TRAS_13 (0xD << 24) // (SDRAMC) Value : 13
#define AT91C_SDRAMC_TRAS_14 (0xE << 24) // (SDRAMC) Value : 14
#define AT91C_SDRAMC_TRAS_15 (0xF << 24) // (SDRAMC) Value : 15
#define AT91C_SDRAMC_TXSR (0xF << 28) // (SDRAMC) Number of Command Recovery Time Cycles
#define AT91C_SDRAMC_TXSR_0 (0x0 << 28) // (SDRAMC) Value : 0
#define AT91C_SDRAMC_TXSR_1 (0x1 << 28) // (SDRAMC) Value : 1
#define AT91C_SDRAMC_TXSR_2 (0x2 << 28) // (SDRAMC) Value : 2
#define AT91C_SDRAMC_TXSR_3 (0x3 << 28) // (SDRAMC) Value : 3
#define AT91C_SDRAMC_TXSR_4 (0x4 << 28) // (SDRAMC) Value : 4
#define AT91C_SDRAMC_TXSR_5 (0x5 << 28) // (SDRAMC) Value : 5
#define AT91C_SDRAMC_TXSR_6 (0x6 << 28) // (SDRAMC) Value : 6
#define AT91C_SDRAMC_TXSR_7 (0x7 << 28) // (SDRAMC) Value : 7
#define AT91C_SDRAMC_TXSR_8 (0x8 << 28) // (SDRAMC) Value : 8
#define AT91C_SDRAMC_TXSR_9 (0x9 << 28) // (SDRAMC) Value : 9
#define AT91C_SDRAMC_TXSR_10 (0xA << 28) // (SDRAMC) Value : 10
#define AT91C_SDRAMC_TXSR_11 (0xB << 28) // (SDRAMC) Value : 11
#define AT91C_SDRAMC_TXSR_12 (0xC << 28) // (SDRAMC) Value : 12
#define AT91C_SDRAMC_TXSR_13 (0xD << 28) // (SDRAMC) Value : 13
#define AT91C_SDRAMC_TXSR_14 (0xE << 28) // (SDRAMC) Value : 14
#define AT91C_SDRAMC_TXSR_15 (0xF << 28) // (SDRAMC) Value : 15
// -------- SDRAMC_HSR : (SDRAMC Offset: 0xc) SDRAM Controller High Speed Register --------
#define AT91C_SDRAMC_DA (0x1 << 0) // (SDRAMC) Decode Cycle Enable Bit
#define AT91C_SDRAMC_DA_DISABLE (0x0) // (SDRAMC) Disable Decode Cycle
#define AT91C_SDRAMC_DA_ENABLE (0x1) // (SDRAMC) Enable Decode Cycle
// -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAM Controller Low-power Register --------
#define AT91C_SDRAMC_LPCB (0x3 << 0) // (SDRAMC) Low-power Configurations
#define AT91C_SDRAMC_LPCB_DISABLE (0x0) // (SDRAMC) Disable Low Power Features
#define AT91C_SDRAMC_LPCB_SELF_REFRESH (0x1) // (SDRAMC) Enable SELF_REFRESH
#define AT91C_SDRAMC_LPCB_POWER_DOWN (0x2) // (SDRAMC) Enable POWER_DOWN
#define AT91C_SDRAMC_LPCB_DEEP_POWER_DOWN (0x3) // (SDRAMC) Enable DEEP_POWER_DOWN
#define AT91C_SDRAMC_PASR (0x7 << 4) // (SDRAMC) Partial Array Self Refresh (only for Low Power SDRAM)
#define AT91C_SDRAMC_TCSR (0x3 << 8) // (SDRAMC) Temperature Compensated Self Refresh (only for Low Power SDRAM)
#define AT91C_SDRAMC_DS (0x3 << 10) // (SDRAMC) Drive Strenght (only for Low Power SDRAM)
#define AT91C_SDRAMC_TIMEOUT (0x3 << 12) // (SDRAMC) Time to define when Low Power Mode is enabled
#define AT91C_SDRAMC_TIMEOUT_0_CLK_CYCLES (0x0 << 12) // (SDRAMC) Activate SDRAM Low Power Mode Immediately
#define AT91C_SDRAMC_TIMEOUT_64_CLK_CYCLES (0x1 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer
#define AT91C_SDRAMC_TIMEOUT_128_CLK_CYCLES (0x2 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer
// -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAM Controller Interrupt Enable Register --------
#define AT91C_SDRAMC_RES (0x1 << 0) // (SDRAMC) Refresh Error Status
// -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAM Controller Interrupt Disable Register --------
// -------- SDRAMC_IMR : (SDRAMC Offset: 0x1c) SDRAM Controller Interrupt Mask Register --------
// -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAM Controller Interrupt Status Register --------
// -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAM Controller Memory Device Register --------
#define AT91C_SDRAMC_MD (0x3 << 0) // (SDRAMC) Memory Device Type
#define AT91C_SDRAMC_MD_SDRAM (0x0) // (SDRAMC) SDRAM Mode
#define AT91C_SDRAMC_MD_LOW_POWER_SDRAM (0x1) // (SDRAMC) SDRAM Low Power Mode
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Static Memory Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_SMC {
AT91_REG SMC_SETUP0; // Setup Register for CS 0
AT91_REG SMC_PULSE0; // Pulse Register for CS 0
AT91_REG SMC_CYCLE0; // Cycle Register for CS 0
AT91_REG SMC_CTRL0; // Control Register for CS 0
AT91_REG SMC_SETUP1; // Setup Register for CS 1
AT91_REG SMC_PULSE1; // Pulse Register for CS 1
AT91_REG SMC_CYCLE1; // Cycle Register for CS 1
AT91_REG SMC_CTRL1; // Control Register for CS 1
AT91_REG SMC_SETUP2; // Setup Register for CS 2
AT91_REG SMC_PULSE2; // Pulse Register for CS 2
AT91_REG SMC_CYCLE2; // Cycle Register for CS 2
AT91_REG SMC_CTRL2; // Control Register for CS 2
AT91_REG SMC_SETUP3; // Setup Register for CS 3
AT91_REG SMC_PULSE3; // Pulse Register for CS 3
AT91_REG SMC_CYCLE3; // Cycle Register for CS 3
AT91_REG SMC_CTRL3; // Control Register for CS 3
AT91_REG SMC_SETUP4; // Setup Register for CS 4
AT91_REG SMC_PULSE4; // Pulse Register for CS 4
AT91_REG SMC_CYCLE4; // Cycle Register for CS 4
AT91_REG SMC_CTRL4; // Control Register for CS 4
AT91_REG SMC_SETUP5; // Setup Register for CS 5
AT91_REG SMC_PULSE5; // Pulse Register for CS 5
AT91_REG SMC_CYCLE5; // Cycle Register for CS 5
AT91_REG SMC_CTRL5; // Control Register for CS 5
AT91_REG SMC_SETUP6; // Setup Register for CS 6
AT91_REG SMC_PULSE6; // Pulse Register for CS 6
AT91_REG SMC_CYCLE6; // Cycle Register for CS 6
AT91_REG SMC_CTRL6; // Control Register for CS 6
AT91_REG SMC_SETUP7; // Setup Register for CS 7
AT91_REG SMC_PULSE7; // Pulse Register for CS 7
AT91_REG SMC_CYCLE7; // Cycle Register for CS 7
AT91_REG SMC_CTRL7; // Control Register for CS 7
} AT91S_SMC, *AT91PS_SMC;
#else
#define SETUP0 (AT91_CAST(AT91_REG *) 0x00000000) // (SETUP0) Setup Register for CS 0
#define PULSE0 (AT91_CAST(AT91_REG *) 0x00000004) // (PULSE0) Pulse Register for CS 0
#define CYCLE0 (AT91_CAST(AT91_REG *) 0x00000008) // (CYCLE0) Cycle Register for CS 0
#define CTRL0 (AT91_CAST(AT91_REG *) 0x0000000C) // (CTRL0) Control Register for CS 0
#define SETUP1 (AT91_CAST(AT91_REG *) 0x00000010) // (SETUP1) Setup Register for CS 1
#define PULSE1 (AT91_CAST(AT91_REG *) 0x00000014) // (PULSE1) Pulse Register for CS 1
#define CYCLE1 (AT91_CAST(AT91_REG *) 0x00000018) // (CYCLE1) Cycle Register for CS 1
#define CTRL1 (AT91_CAST(AT91_REG *) 0x0000001C) // (CTRL1) Control Register for CS 1
#define SETUP2 (AT91_CAST(AT91_REG *) 0x00000020) // (SETUP2) Setup Register for CS 2
#define PULSE2 (AT91_CAST(AT91_REG *) 0x00000024) // (PULSE2) Pulse Register for CS 2
#define CYCLE2 (AT91_CAST(AT91_REG *) 0x00000028) // (CYCLE2) Cycle Register for CS 2
#define CTRL2 (AT91_CAST(AT91_REG *) 0x0000002C) // (CTRL2) Control Register for CS 2
#define SETUP3 (AT91_CAST(AT91_REG *) 0x00000030) // (SETUP3) Setup Register for CS 3
#define PULSE3 (AT91_CAST(AT91_REG *) 0x00000034) // (PULSE3) Pulse Register for CS 3
#define CYCLE3 (AT91_CAST(AT91_REG *) 0x00000038) // (CYCLE3) Cycle Register for CS 3
#define CTRL3 (AT91_CAST(AT91_REG *) 0x0000003C) // (CTRL3) Control Register for CS 3
#define SETUP4 (AT91_CAST(AT91_REG *) 0x00000040) // (SETUP4) Setup Register for CS 4
#define PULSE4 (AT91_CAST(AT91_REG *) 0x00000044) // (PULSE4) Pulse Register for CS 4
#define CYCLE4 (AT91_CAST(AT91_REG *) 0x00000048) // (CYCLE4) Cycle Register for CS 4
#define CTRL4 (AT91_CAST(AT91_REG *) 0x0000004C) // (CTRL4) Control Register for CS 4
#define SETUP5 (AT91_CAST(AT91_REG *) 0x00000050) // (SETUP5) Setup Register for CS 5
#define PULSE5 (AT91_CAST(AT91_REG *) 0x00000054) // (PULSE5) Pulse Register for CS 5
#define CYCLE5 (AT91_CAST(AT91_REG *) 0x00000058) // (CYCLE5) Cycle Register for CS 5
#define CTRL5 (AT91_CAST(AT91_REG *) 0x0000005C) // (CTRL5) Control Register for CS 5
#define SETUP6 (AT91_CAST(AT91_REG *) 0x00000060) // (SETUP6) Setup Register for CS 6
#define PULSE6 (AT91_CAST(AT91_REG *) 0x00000064) // (PULSE6) Pulse Register for CS 6
#define CYCLE6 (AT91_CAST(AT91_REG *) 0x00000068) // (CYCLE6) Cycle Register for CS 6
#define CTRL6 (AT91_CAST(AT91_REG *) 0x0000006C) // (CTRL6) Control Register for CS 6
#define SETUP7 (AT91_CAST(AT91_REG *) 0x00000070) // (SETUP7) Setup Register for CS 7
#define PULSE7 (AT91_CAST(AT91_REG *) 0x00000074) // (PULSE7) Pulse Register for CS 7
#define CYCLE7 (AT91_CAST(AT91_REG *) 0x00000078) // (CYCLE7) Cycle Register for CS 7
#define CTRL7 (AT91_CAST(AT91_REG *) 0x0000007C) // (CTRL7) Control Register for CS 7
#endif
// -------- SMC_SETUP : (SMC Offset: 0x0) Setup Register for CS x --------
#define AT91C_SMC_NWESETUP (0x3F << 0) // (SMC) NWE Setup Length
#define AT91C_SMC_NCSSETUPWR (0x3F << 8) // (SMC) NCS Setup Length in WRite Access
#define AT91C_SMC_NRDSETUP (0x3F << 16) // (SMC) NRD Setup Length
#define AT91C_SMC_NCSSETUPRD (0x3F << 24) // (SMC) NCS Setup Length in ReaD Access
// -------- SMC_PULSE : (SMC Offset: 0x4) Pulse Register for CS x --------
#define AT91C_SMC_NWEPULSE (0x7F << 0) // (SMC) NWE Pulse Length
#define AT91C_SMC_NCSPULSEWR (0x7F << 8) // (SMC) NCS Pulse Length in WRite Access
#define AT91C_SMC_NRDPULSE (0x7F << 16) // (SMC) NRD Pulse Length
#define AT91C_SMC_NCSPULSERD (0x7F << 24) // (SMC) NCS Pulse Length in ReaD Access
// -------- SMC_CYC : (SMC Offset: 0x8) Cycle Register for CS x --------
#define AT91C_SMC_NWECYCLE (0x1FF << 0) // (SMC) Total Write Cycle Length
#define AT91C_SMC_NRDCYCLE (0x1FF << 16) // (SMC) Total Read Cycle Length
// -------- SMC_CTRL : (SMC Offset: 0xc) Control Register for CS x --------
#define AT91C_SMC_READMODE (0x1 << 0) // (SMC) Read Mode
#define AT91C_SMC_WRITEMODE (0x1 << 1) // (SMC) Write Mode
#define AT91C_SMC_NWAITM (0x3 << 4) // (SMC) NWAIT Mode
#define AT91C_SMC_NWAITM_NWAIT_DISABLE (0x0 << 4) // (SMC) External NWAIT disabled.
#define AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN (0x2 << 4) // (SMC) External NWAIT enabled in frozen mode.
#define AT91C_SMC_NWAITM_NWAIT_ENABLE_READY (0x3 << 4) // (SMC) External NWAIT enabled in ready mode.
#define AT91C_SMC_BAT (0x1 << 8) // (SMC) Byte Access Type
#define AT91C_SMC_BAT_BYTE_SELECT (0x0 << 8) // (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.
#define AT91C_SMC_BAT_BYTE_WRITE (0x1 << 8) // (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.
#define AT91C_SMC_DBW (0x3 << 12) // (SMC) Data Bus Width
#define AT91C_SMC_DBW_WIDTH_EIGTH_BITS (0x0 << 12) // (SMC) 8 bits.
#define AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS (0x1 << 12) // (SMC) 16 bits.
#define AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) // (SMC) 32 bits.
#define AT91C_SMC_TDF (0xF << 16) // (SMC) Data Float Time.
#define AT91C_SMC_TDFEN (0x1 << 20) // (SMC) TDF Enabled.
#define AT91C_SMC_PMEN (0x1 << 24) // (SMC) Page Mode Enabled.
#define AT91C_SMC_PS (0x3 << 28) // (SMC) Page Size
#define AT91C_SMC_PS_SIZE_FOUR_BYTES (0x0 << 28) // (SMC) 4 bytes.
#define AT91C_SMC_PS_SIZE_EIGHT_BYTES (0x1 << 28) // (SMC) 8 bytes.
#define AT91C_SMC_PS_SIZE_SIXTEEN_BYTES (0x2 << 28) // (SMC) 16 bytes.
#define AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) // (SMC) 32 bytes.
// -------- SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR AHB Matrix Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_MATRIX {
AT91_REG MATRIX_MCFG0; // Master Configuration Register 0 (ram96k)
AT91_REG MATRIX_MCFG1; // Master Configuration Register 1 (rom)
AT91_REG MATRIX_MCFG2; // Master Configuration Register 2 (hperiphs)
AT91_REG MATRIX_MCFG3; // Master Configuration Register 3 (ebi)
AT91_REG MATRIX_MCFG4; // Master Configuration Register 4 (bridge)
AT91_REG MATRIX_MCFG5; // Master Configuration Register 5 (mailbox)
AT91_REG MATRIX_MCFG6; // Master Configuration Register 6 (ram16k)
AT91_REG MATRIX_MCFG7; // Master Configuration Register 7 (teak_prog)
AT91_REG Reserved0[8]; //
AT91_REG MATRIX_SCFG0; // Slave Configuration Register 0 (ram96k)
AT91_REG MATRIX_SCFG1; // Slave Configuration Register 1 (rom)
AT91_REG MATRIX_SCFG2; // Slave Configuration Register 2 (hperiphs)
AT91_REG MATRIX_SCFG3; // Slave Configuration Register 3 (ebi)
AT91_REG MATRIX_SCFG4; // Slave Configuration Register 4 (bridge)
AT91_REG Reserved1[11]; //
AT91_REG MATRIX_PRAS0; // PRAS0 (ram0)
AT91_REG MATRIX_PRBS0; // PRBS0 (ram0)
AT91_REG MATRIX_PRAS1; // PRAS1 (ram1)
AT91_REG MATRIX_PRBS1; // PRBS1 (ram1)
AT91_REG MATRIX_PRAS2; // PRAS2 (ram2)
AT91_REG MATRIX_PRBS2; // PRBS2 (ram2)
AT91_REG MATRIX_PRAS3; // PRAS3 : usb_dev_hs
AT91_REG MATRIX_PRBS3; // PRBS3 : usb_dev_hs
AT91_REG MATRIX_PRAS4; // PRAS4 : ebi
AT91_REG MATRIX_PRBS4; // PRBS4 : ebi
AT91_REG Reserved2[22]; //
AT91_REG MATRIX_MRCR; // Master Remp Control Register
AT91_REG Reserved3[6]; //
AT91_REG MATRIX_EBI; // Slave 3 (ebi) Special Function Register
AT91_REG Reserved4[3]; //
AT91_REG MATRIX_TEAKCFG; // Slave 7 (teak_prog) Special Function Register
AT91_REG Reserved5[51]; //
AT91_REG MATRIX_VERSION; // Version Register
} AT91S_MATRIX, *AT91PS_MATRIX;
#else
#define MATRIX_MCFG0 (AT91_CAST(AT91_REG *) 0x00000000) // (MATRIX_MCFG0) Master Configuration Register 0 (ram96k)
#define MATRIX_MCFG1 (AT91_CAST(AT91_REG *) 0x00000004) // (MATRIX_MCFG1) Master Configuration Register 1 (rom)
#define MATRIX_MCFG2 (AT91_CAST(AT91_REG *) 0x00000008) // (MATRIX_MCFG2) Master Configuration Register 2 (hperiphs)
#define MATRIX_MCFG3 (AT91_CAST(AT91_REG *) 0x0000000C) // (MATRIX_MCFG3) Master Configuration Register 3 (ebi)
#define MATRIX_MCFG4 (AT91_CAST(AT91_REG *) 0x00000010) // (MATRIX_MCFG4) Master Configuration Register 4 (bridge)
#define MATRIX_MCFG5 (AT91_CAST(AT91_REG *) 0x00000014) // (MATRIX_MCFG5) Master Configuration Register 5 (mailbox)
#define MATRIX_MCFG6 (AT91_CAST(AT91_REG *) 0x00000018) // (MATRIX_MCFG6) Master Configuration Register 6 (ram16k)
#define MATRIX_MCFG7 (AT91_CAST(AT91_REG *) 0x0000001C) // (MATRIX_MCFG7) Master Configuration Register 7 (teak_prog)
#define MATRIX_SCFG0 (AT91_CAST(AT91_REG *) 0x00000040) // (MATRIX_SCFG0) Slave Configuration Register 0 (ram96k)
#define MATRIX_SCFG1 (AT91_CAST(AT91_REG *) 0x00000044) // (MATRIX_SCFG1) Slave Configuration Register 1 (rom)
#define MATRIX_SCFG2 (AT91_CAST(AT91_REG *) 0x00000048) // (MATRIX_SCFG2) Slave Configuration Register 2 (hperiphs)
#define MATRIX_SCFG3 (AT91_CAST(AT91_REG *) 0x0000004C) // (MATRIX_SCFG3) Slave Configuration Register 3 (ebi)
#define MATRIX_SCFG4 (AT91_CAST(AT91_REG *) 0x00000050) // (MATRIX_SCFG4) Slave Configuration Register 4 (bridge)
#define MATRIX_PRAS0 (AT91_CAST(AT91_REG *) 0x00000080) // (MATRIX_PRAS0) PRAS0 (ram0)
#define MATRIX_PRBS0 (AT91_CAST(AT91_REG *) 0x00000084) // (MATRIX_PRBS0) PRBS0 (ram0)
#define MATRIX_PRAS1 (AT91_CAST(AT91_REG *) 0x00000088) // (MATRIX_PRAS1) PRAS1 (ram1)
#define MATRIX_PRBS1 (AT91_CAST(AT91_REG *) 0x0000008C) // (MATRIX_PRBS1) PRBS1 (ram1)
#define MATRIX_PRAS2 (AT91_CAST(AT91_REG *) 0x00000090) // (MATRIX_PRAS2) PRAS2 (ram2)
#define MATRIX_PRBS2 (AT91_CAST(AT91_REG *) 0x00000094) // (MATRIX_PRBS2) PRBS2 (ram2)
#define MATRIX_PRAS3 (AT91_CAST(AT91_REG *) 0x00000098) // (MATRIX_PRAS3) PRAS3 : usb_dev_hs
#define MATRIX_PRBS3 (AT91_CAST(AT91_REG *) 0x0000009C) // (MATRIX_PRBS3) PRBS3 : usb_dev_hs
#define MATRIX_PRAS4 (AT91_CAST(AT91_REG *) 0x000000A0) // (MATRIX_PRAS4) PRAS4 : ebi
#define MATRIX_PRBS4 (AT91_CAST(AT91_REG *) 0x000000A4) // (MATRIX_PRBS4) PRBS4 : ebi
#define MATRIX_MRCR (AT91_CAST(AT91_REG *) 0x00000100) // (MATRIX_MRCR) Master Remp Control Register
#define MATRIX_EBI (AT91_CAST(AT91_REG *) 0x0000011C) // (MATRIX_EBI) Slave 3 (ebi) Special Function Register
#define MATRIX_TEAKCFG (AT91_CAST(AT91_REG *) 0x0000012C) // (MATRIX_TEAKCFG) Slave 7 (teak_prog) Special Function Register
#define MATRIX_VERSION (AT91_CAST(AT91_REG *) 0x000001FC) // (MATRIX_VERSION) Version Register
#endif
// -------- MATRIX_SCFG0 : (MATRIX Offset: 0x40) Slave Configuration Register 0 --------
#define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0) // (MATRIX) Maximum Number of Allowed Cycles for a Burst
#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) // (MATRIX) Default Master Type
#define AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR (0x0 << 16) // (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.
#define AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR (0x1 << 16) // (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.
#define AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR (0x2 << 16) // (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.
#define AT91C_MATRIX_FIXED_DEFMSTR0 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master
// -------- MATRIX_SCFG1 : (MATRIX Offset: 0x44) Slave Configuration Register 1 --------
#define AT91C_MATRIX_FIXED_DEFMSTR1 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master
// -------- MATRIX_SCFG2 : (MATRIX Offset: 0x48) Slave Configuration Register 2 --------
#define AT91C_MATRIX_FIXED_DEFMSTR2 (0x1 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
// -------- MATRIX_SCFG3 : (MATRIX Offset: 0x4c) Slave Configuration Register 3 --------
#define AT91C_MATRIX_FIXED_DEFMSTR3 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master
// -------- MATRIX_SCFG4 : (MATRIX Offset: 0x50) Slave Configuration Register 4 --------
#define AT91C_MATRIX_FIXED_DEFMSTR4 (0x3 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR4_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
// -------- MATRIX_PRAS0 : (MATRIX Offset: 0x80) PRAS0 Register --------
#define AT91C_MATRIX_M0PR (0x3 << 0) // (MATRIX) ARM926EJ-S Instruction priority
#define AT91C_MATRIX_M1PR (0x3 << 4) // (MATRIX) ARM926EJ-S Data priority
#define AT91C_MATRIX_M2PR (0x3 << 8) // (MATRIX) PDC priority
#define AT91C_MATRIX_M3PR (0x3 << 12) // (MATRIX) LCDC priority
#define AT91C_MATRIX_M4PR (0x3 << 16) // (MATRIX) 2DGC priority
#define AT91C_MATRIX_M5PR (0x3 << 20) // (MATRIX) ISI priority
#define AT91C_MATRIX_M6PR (0x3 << 24) // (MATRIX) DMA priority
#define AT91C_MATRIX_M7PR (0x3 << 28) // (MATRIX) EMAC priority
// -------- MATRIX_PRBS0 : (MATRIX Offset: 0x84) PRBS0 Register --------
#define AT91C_MATRIX_M8PR (0x3 << 0) // (MATRIX) USB priority
// -------- MATRIX_PRAS1 : (MATRIX Offset: 0x88) PRAS1 Register --------
// -------- MATRIX_PRBS1 : (MATRIX Offset: 0x8c) PRBS1 Register --------
// -------- MATRIX_PRAS2 : (MATRIX Offset: 0x90) PRAS2 Register --------
// -------- MATRIX_PRBS2 : (MATRIX Offset: 0x94) PRBS2 Register --------
// -------- MATRIX_PRAS3 : (MATRIX Offset: 0x98) PRAS3 Register --------
// -------- MATRIX_PRBS3 : (MATRIX Offset: 0x9c) PRBS3 Register --------
// -------- MATRIX_PRAS4 : (MATRIX Offset: 0xa0) PRAS4 Register --------
// -------- MATRIX_PRBS4 : (MATRIX Offset: 0xa4) PRBS4 Register --------
// -------- MATRIX_MRCR : (MATRIX Offset: 0x100) MRCR Register --------
#define AT91C_MATRIX_RCA926I (0x1 << 0) // (MATRIX) Remap Command for ARM926EJ-S Instruction Master
#define AT91C_MATRIX_RCA926D (0x1 << 1) // (MATRIX) Remap Command for ARM926EJ-S Data Master
// -------- MATRIX_EBI : (MATRIX Offset: 0x11c) EBI (Slave 3) Special Function Register --------
#define AT91C_MATRIX_CS1A (0x1 << 1) // (MATRIX) Chip Select 1 Assignment
#define AT91C_MATRIX_CS1A_SMC (0x0 << 1) // (MATRIX) Chip Select 1 is assigned to the Static Memory Controller.
#define AT91C_MATRIX_CS1A_SDRAMC (0x1 << 1) // (MATRIX) Chip Select 1 is assigned to the SDRAM Controller.
#define AT91C_MATRIX_CS3A (0x1 << 3) // (MATRIX) Chip Select 3 Assignment
#define AT91C_MATRIX_CS3A_SMC (0x0 << 3) // (MATRIX) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.
#define AT91C_MATRIX_CS3A_SM (0x1 << 3) // (MATRIX) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
#define AT91C_MATRIX_CS4A (0x1 << 4) // (MATRIX) Chip Select 4 Assignment
#define AT91C_MATRIX_CS4A_SMC (0x0 << 4) // (MATRIX) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.
#define AT91C_MATRIX_CS4A_CF (0x1 << 4) // (MATRIX) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.
#define AT91C_MATRIX_CS5A (0x1 << 5) // (MATRIX) Chip Select 5 Assignment
#define AT91C_MATRIX_CS5A_SMC (0x0 << 5) // (MATRIX) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC
#define AT91C_MATRIX_CS5A_CF (0x1 << 5) // (MATRIX) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.
#define AT91C_MATRIX_DBPUC (0x1 << 8) // (MATRIX) Data Bus Pull-up Configuration
// -------- MATRIX_TEAKCFG : (MATRIX Offset: 0x12c) Slave 7 Special Function Register --------
#define AT91C_TEAK_PROGRAM_ACCESS (0x1 << 0) // (MATRIX) TEAK program memory access from AHB
#define AT91C_TEAK_PROGRAM_ACCESS_DISABLED (0x0) // (MATRIX) TEAK program access disabled
#define AT91C_TEAK_PROGRAM_ACCESS_ENABLED (0x1) // (MATRIX) TEAK program access enabled
#define AT91C_TEAK_BOOT (0x1 << 1) // (MATRIX) TEAK program start from boot routine
#define AT91C_TEAK_BOOT_DISABLED (0x0 << 1) // (MATRIX) TEAK program starts from boot routine disabled
#define AT91C_TEAK_BOOT_ENABLED (0x1 << 1) // (MATRIX) TEAK program starts from boot routine enabled
#define AT91C_TEAK_NRESET (0x1 << 2) // (MATRIX) active low TEAK reset
#define AT91C_TEAK_NRESET_ENABLED (0x0 << 2) // (MATRIX) active low TEAK reset enabled
#define AT91C_TEAK_NRESET_DISABLED (0x1 << 2) // (MATRIX) active low TEAK reset disabled
#define AT91C_TEAK_LVECTORP (0x3FFFF << 14) // (MATRIX) boot routine start address
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Chip Configuration Registers
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_CCFG {
AT91_REG Reserved0[3]; //
AT91_REG CCFG_EBICSA; // EBI Chip Select Assignement Register
AT91_REG Reserved1[55]; //
AT91_REG CCFG_MATRIXVERSION; // Version Register
} AT91S_CCFG, *AT91PS_CCFG;
#else
#define CCFG_EBICSA (AT91_CAST(AT91_REG *) 0x0000000C) // (CCFG_EBICSA) EBI Chip Select Assignement Register
#define CCFG_MATRIXVERSION (AT91_CAST(AT91_REG *) 0x000000EC) // (CCFG_MATRIXVERSION) Version Register
#endif
// -------- CCFG_EBICSA : (CCFG Offset: 0xc) EBI Chip Select Assignement Register --------
#define AT91C_EBI_CS1A (0x1 << 1) // (CCFG) Chip Select 1 Assignment
#define AT91C_EBI_CS1A_SMC (0x0 << 1) // (CCFG) Chip Select 1 is assigned to the Static Memory Controller.
#define AT91C_EBI_CS1A_SDRAMC (0x1 << 1) // (CCFG) Chip Select 1 is assigned to the SDRAM Controller.
#define AT91C_EBI_CS3A (0x1 << 3) // (CCFG) Chip Select 3 Assignment
#define AT91C_EBI_CS3A_SMC (0x0 << 3) // (CCFG) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.
#define AT91C_EBI_CS3A_SM (0x1 << 3) // (CCFG) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
#define AT91C_EBI_CS4A (0x1 << 4) // (CCFG) Chip Select 4 Assignment
#define AT91C_EBI_CS4A_SMC (0x0 << 4) // (CCFG) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.
#define AT91C_EBI_CS4A_CF (0x1 << 4) // (CCFG) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.
#define AT91C_EBI_CS5A (0x1 << 5) // (CCFG) Chip Select 5 Assignment
#define AT91C_EBI_CS5A_SMC (0x0 << 5) // (CCFG) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC
#define AT91C_EBI_CS5A_CF (0x1 << 5) // (CCFG) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.
#define AT91C_EBI_DBPUC (0x1 << 8) // (CCFG) Data Bus Pull-up Configuration
#define AT91C_EBI_SUPPLY (0x1 << 16) // (CCFG) EBI supply selection
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_PDC {
AT91_REG PDC_RPR; // Receive Pointer Register
AT91_REG PDC_RCR; // Receive Counter Register
AT91_REG PDC_TPR; // Transmit Pointer Register
AT91_REG PDC_TCR; // Transmit Counter Register
AT91_REG PDC_RNPR; // Receive Next Pointer Register
AT91_REG PDC_RNCR; // Receive Next Counter Register
AT91_REG PDC_TNPR; // Transmit Next Pointer Register
AT91_REG PDC_TNCR; // Transmit Next Counter Register
AT91_REG PDC_PTCR; // PDC Transfer Control Register
AT91_REG PDC_PTSR; // PDC Transfer Status Register
} AT91S_PDC, *AT91PS_PDC;
#else
#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register
#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register
#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register
#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register
#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register
#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register
#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register
#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register
#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register
#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register
#endif
// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable
#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable
#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable
#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable
// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Debug Unit
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_DBGU {
AT91_REG DBGU_CR; // Control Register
AT91_REG DBGU_MR; // Mode Register
AT91_REG DBGU_IER; // Interrupt Enable Register
AT91_REG DBGU_IDR; // Interrupt Disable Register
AT91_REG DBGU_IMR; // Interrupt Mask Register
AT91_REG DBGU_CSR; // Channel Status Register
AT91_REG DBGU_RHR; // Receiver Holding Register
AT91_REG DBGU_THR; // Transmitter Holding Register
AT91_REG DBGU_BRGR; // Baud Rate Generator Register
AT91_REG Reserved0[7]; //
AT91_REG DBGU_CIDR; // Chip ID Register
AT91_REG DBGU_EXID; // Chip ID Extension Register
AT91_REG DBGU_FNTR; // Force NTRST Register
AT91_REG Reserved1[45]; //
AT91_REG DBGU_RPR; // Receive Pointer Register
AT91_REG DBGU_RCR; // Receive Counter Register
AT91_REG DBGU_TPR; // Transmit Pointer Register
AT91_REG DBGU_TCR; // Transmit Counter Register
AT91_REG DBGU_RNPR; // Receive Next Pointer Register
AT91_REG DBGU_RNCR; // Receive Next Counter Register
AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
AT91_REG DBGU_TNCR; // Transmit Next Counter Register
AT91_REG DBGU_PTCR; // PDC Transfer Control Register
AT91_REG DBGU_PTSR; // PDC Transfer Status Register
} AT91S_DBGU, *AT91PS_DBGU;
#else
#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register
#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register
#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register
#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register
#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register
#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register
#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register
#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register
#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register
#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register
#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register
#endif
// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver
#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter
#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable
#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable
#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable
#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable
#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits
// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type
#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity
#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity
#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)
#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity
#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode
#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode
#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt
#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt
#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt
#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt
#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt
#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt
#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt
#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt
#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt
#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt
#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt
// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_AIC {
AT91_REG AIC_SMR[32]; // Source Mode Register
AT91_REG AIC_SVR[32]; // Source Vector Register
AT91_REG AIC_IVR; // IRQ Vector Register
AT91_REG AIC_FVR; // FIQ Vector Register
AT91_REG AIC_ISR; // Interrupt Status Register
AT91_REG AIC_IPR; // Interrupt Pending Register
AT91_REG AIC_IMR; // Interrupt Mask Register
AT91_REG AIC_CISR; // Core Interrupt Status Register
AT91_REG Reserved0[2]; //
AT91_REG AIC_IECR; // Interrupt Enable Command Register
AT91_REG AIC_IDCR; // Interrupt Disable Command Register
AT91_REG AIC_ICCR; // Interrupt Clear Command Register
AT91_REG AIC_ISCR; // Interrupt Set Command Register
AT91_REG AIC_EOICR; // End of Interrupt Command Register
AT91_REG AIC_SPU; // Spurious Vector Register
AT91_REG AIC_DCR; // Debug Control Register (Protect)
AT91_REG Reserved1[1]; //
AT91_REG AIC_FFER; // Fast Forcing Enable Register
AT91_REG AIC_FFDR; // Fast Forcing Disable Register
AT91_REG AIC_FFSR; // Fast Forcing Status Register
} AT91S_AIC, *AT91PS_AIC;
#else
#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register
#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register
#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register
#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register
#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register
#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register
#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register
#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register
#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register
#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register
#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register
#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register
#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register
#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register
#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect)
#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register
#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register
#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register
#endif
// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level
#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level
#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level
#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type
#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive
#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered
#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive
#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered
// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status
#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status
// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode
#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_PIO {
AT91_REG PIO_PER; // PIO Enable Register
AT91_REG PIO_PDR; // PIO Disable Register
AT91_REG PIO_PSR; // PIO Status Register
AT91_REG Reserved0[1]; //
AT91_REG PIO_OER; // Output Enable Register
AT91_REG PIO_ODR; // Output Disable Registerr
AT91_REG PIO_OSR; // Output Status Register
AT91_REG Reserved1[1]; //
AT91_REG PIO_IFER; // Input Filter Enable Register
AT91_REG PIO_IFDR; // Input Filter Disable Register
AT91_REG PIO_IFSR; // Input Filter Status Register
AT91_REG Reserved2[1]; //
AT91_REG PIO_SODR; // Set Output Data Register
AT91_REG PIO_CODR; // Clear Output Data Register
AT91_REG PIO_ODSR; // Output Data Status Register
AT91_REG PIO_PDSR; // Pin Data Status Register
AT91_REG PIO_IER; // Interrupt Enable Register
AT91_REG PIO_IDR; // Interrupt Disable Register
AT91_REG PIO_IMR; // Interrupt Mask Register
AT91_REG PIO_ISR; // Interrupt Status Register
AT91_REG PIO_MDER; // Multi-driver Enable Register
AT91_REG PIO_MDDR; // Multi-driver Disable Register
AT91_REG PIO_MDSR; // Multi-driver Status Register
AT91_REG Reserved3[1]; //
AT91_REG PIO_PPUDR; // Pull-up Disable Register
AT91_REG PIO_PPUER; // Pull-up Enable Register
AT91_REG PIO_PPUSR; // Pull-up Status Register
AT91_REG Reserved4[1]; //
AT91_REG PIO_ASR; // Select A Register
AT91_REG PIO_BSR; // Select B Register
AT91_REG PIO_ABSR; // AB Select Status Register
AT91_REG Reserved5[9]; //
AT91_REG PIO_OWER; // Output Write Enable Register
AT91_REG PIO_OWDR; // Output Write Disable Register
AT91_REG PIO_OWSR; // Output Write Status Register
} AT91S_PIO, *AT91PS_PIO;
#else
#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register
#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register
#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register
#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register
#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr
#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register
#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register
#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register
#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register
#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register
#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register
#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register
#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register
#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register
#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register
#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register
#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register
#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register
#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register
#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register
#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register
#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register
#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register
#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register
#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register
#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register
#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register
#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register
#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register
#endif
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Embedded Flash Controller 2.0
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_EFC {
AT91_REG EFC_FMR; // EFC Flash Mode Register
AT91_REG EFC_FCR; // EFC Flash Command Register
AT91_REG EFC_FSR; // EFC Flash Status Register
AT91_REG EFC_FRR; // EFC Flash Result Register
AT91_REG EFC_FVR; // EFC Flash Version Register
} AT91S_EFC, *AT91PS_EFC;
#else
#define EFC_FMR (AT91_CAST(AT91_REG *) 0x00000000) // (EFC_FMR) EFC Flash Mode Register
#define EFC_FCR (AT91_CAST(AT91_REG *) 0x00000004) // (EFC_FCR) EFC Flash Command Register
#define EFC_FSR (AT91_CAST(AT91_REG *) 0x00000008) // (EFC_FSR) EFC Flash Status Register
#define EFC_FRR (AT91_CAST(AT91_REG *) 0x0000000C) // (EFC_FRR) EFC Flash Result Register
#define EFC_FVR (AT91_CAST(AT91_REG *) 0x00000010) // (EFC_FVR) EFC Flash Version Register
#endif
// -------- EFC_FMR : (EFC Offset: 0x0) EFC Flash Mode Register --------
#define AT91C_EFC_FRDY (0x1 << 0) // (EFC) Ready Interrupt Enable
#define AT91C_EFC_FWS (0xF << 8) // (EFC) Flash Wait State.
#define AT91C_EFC_FWS_0WS (0x0 << 8) // (EFC) 0 Wait State
#define AT91C_EFC_FWS_1WS (0x1 << 8) // (EFC) 1 Wait State
#define AT91C_EFC_FWS_2WS (0x2 << 8) // (EFC) 2 Wait States
#define AT91C_EFC_FWS_3WS (0x3 << 8) // (EFC) 3 Wait States
// -------- EFC_FCR : (EFC Offset: 0x4) EFC Flash Command Register --------
#define AT91C_EFC_FCMD (0xFF << 0) // (EFC) Flash Command
#define AT91C_EFC_FCMD_GETD (0x0) // (EFC) Get Flash Descriptor
#define AT91C_EFC_FCMD_WP (0x1) // (EFC) Write Page
#define AT91C_EFC_FCMD_WPL (0x2) // (EFC) Write Page and Lock
#define AT91C_EFC_FCMD_EWP (0x3) // (EFC) Erase Page and Write Page
#define AT91C_EFC_FCMD_EWPL (0x4) // (EFC) Erase Page and Write Page then Lock
#define AT91C_EFC_FCMD_EA (0x5) // (EFC) Erase All
#define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase Plane
#define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase Pages
#define AT91C_EFC_FCMD_SLB (0x8) // (EFC) Set Lock Bit
#define AT91C_EFC_FCMD_CLB (0x9) // (EFC) Clear Lock Bit
#define AT91C_EFC_FCMD_GLB (0xA) // (EFC) Get Lock Bit
#define AT91C_EFC_FCMD_SFB (0xB) // (EFC) Set Fuse Bit
#define AT91C_EFC_FCMD_CFB (0xC) // (EFC) Clear Fuse Bit
#define AT91C_EFC_FCMD_GFB (0xD) // (EFC) Get Fuse Bit
#define AT91C_EFC_FARG (0xFFFF << 8) // (EFC) Flash Command Argument
#define AT91C_EFC_FKEY (0xFF << 24) // (EFC) Flash Writing Protection Key
// -------- EFC_FSR : (EFC Offset: 0x8) EFC Flash Status Register --------
#define AT91C_EFC_FRDY_S (0x1 << 0) // (EFC) Flash Ready Status
#define AT91C_EFC_FCMDE (0x1 << 1) // (EFC) Flash Command Error Status
#define AT91C_EFC_LOCKE (0x1 << 2) // (EFC) Flash Lock Error Status
// -------- EFC_FRR : (EFC Offset: 0xc) EFC Flash Result Register --------
#define AT91C_EFC_FVALUE (0x0 << 0) // (EFC) Flash Result Value
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Clock Generator Controler
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_CKGR {
AT91_REG CKGR_MOR; // Main Oscillator Register
AT91_REG CKGR_MCFR; // Main Clock Frequency Register
AT91_REG CKGR_PLLAR; // PLL A Register
AT91_REG CKGR_PLLBR; // PLL B Register
} AT91S_CKGR, *AT91PS_CKGR;
#else
#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register
#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register
#define CKGR_PLLAR (AT91_CAST(AT91_REG *) 0x00000008) // (CKGR_PLLAR) PLL A Register
#define CKGR_PLLBR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLBR) PLL B Register
#endif
// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable
#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass
#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time
// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency
#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready
// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register --------
#define AT91C_CKGR_DIVA (0xFF << 0) // (CKGR) Divider A Selected
#define AT91C_CKGR_DIVA_0 (0x0) // (CKGR) Divider A output is 0
#define AT91C_CKGR_DIVA_BYPASS (0x1) // (CKGR) Divider A is bypassed
#define AT91C_CKGR_PLLACOUNT (0x3F << 8) // (CKGR) PLL A Counter
#define AT91C_CKGR_OUTA (0x3 << 14) // (CKGR) PLL A Output Frequency Range
#define AT91C_CKGR_OUTA_0 (0x0 << 14) // (CKGR) Please refer to the PLLA datasheet
#define AT91C_CKGR_OUTA_1 (0x1 << 14) // (CKGR) Please refer to the PLLA datasheet
#define AT91C_CKGR_OUTA_2 (0x2 << 14) // (CKGR) Please refer to the PLLA datasheet
#define AT91C_CKGR_OUTA_3 (0x3 << 14) // (CKGR) Please refer to the PLLA datasheet
#define AT91C_CKGR_MULA (0x7FF << 16) // (CKGR) PLL A Multiplier
#define AT91C_CKGR_SRCA (0x1 << 29) // (CKGR)
// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register --------
#define AT91C_CKGR_DIVB (0xFF << 0) // (CKGR) Divider B Selected
#define AT91C_CKGR_DIVB_0 (0x0) // (CKGR) Divider B output is 0
#define AT91C_CKGR_DIVB_BYPASS (0x1) // (CKGR) Divider B is bypassed
#define AT91C_CKGR_PLLBCOUNT (0x3F << 8) // (CKGR) PLL B Counter
#define AT91C_CKGR_OUTB (0x3 << 14) // (CKGR) PLL B Output Frequency Range
#define AT91C_CKGR_OUTB_0 (0x0 << 14) // (CKGR) Please refer to the PLLB datasheet
#define AT91C_CKGR_OUTB_1 (0x1 << 14) // (CKGR) Please refer to the PLLB datasheet
#define AT91C_CKGR_OUTB_2 (0x2 << 14) // (CKGR) Please refer to the PLLB datasheet
#define AT91C_CKGR_OUTB_3 (0x3 << 14) // (CKGR) Please refer to the PLLB datasheet
#define AT91C_CKGR_MULB (0x7FF << 16) // (CKGR) PLL B Multiplier
#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks
#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output
#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Power Management Controler
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_PMC {
AT91_REG PMC_SCER; // System Clock Enable Register
AT91_REG PMC_SCDR; // System Clock Disable Register
AT91_REG PMC_SCSR; // System Clock Status Register
AT91_REG Reserved0[1]; //
AT91_REG PMC_PCER; // Peripheral Clock Enable Register
AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
AT91_REG PMC_PCSR; // Peripheral Clock Status Register
AT91_REG Reserved1[1]; //
AT91_REG PMC_MOR; // Main Oscillator Register
AT91_REG PMC_MCFR; // Main Clock Frequency Register
AT91_REG PMC_PLLAR; // PLL A Register
AT91_REG PMC_PLLBR; // PLL B Register
AT91_REG PMC_MCKR; // Master Clock Register
AT91_REG Reserved2[3]; //
AT91_REG PMC_PCKR[8]; // Programmable Clock Register
AT91_REG PMC_IER; // Interrupt Enable Register
AT91_REG PMC_IDR; // Interrupt Disable Register
AT91_REG PMC_SR; // Status Register
AT91_REG PMC_IMR; // Interrupt Mask Register
} AT91S_PMC, *AT91PS_PMC;
#else
#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register
#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register
#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register
#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register
#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register
#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register
#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register
#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register
#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register
#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register
#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register
#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register
#endif
// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock
#define AT91C_PMC_OTG (0x1 << 5) // (PMC) USB OTG Clock
#define AT91C_PMC_UHP (0x1 << 6) // (PMC) USB Host Port Clock
#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock
#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output
// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
// -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register --------
// -------- CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register --------
// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection
#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected
#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected
#define AT91C_PMC_CSS_PLLA_CLK (0x2) // (PMC) Clock from PLL A is selected
#define AT91C_PMC_CSS_PLLB_CLK (0x3) // (PMC) Clock from PLL B is selected
#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler
#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock
#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2
#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4
#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8
#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16
#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32
#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64
#define AT91C_PMC_MDIV (0x3 << 8) // (PMC) Master Clock Division
#define AT91C_PMC_MDIV_1 (0x0 << 8) // (PMC) The master clock and the processor clock are the same
#define AT91C_PMC_MDIV_2 (0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock
#define AT91C_PMC_MDIV_3 (0x2 << 8) // (PMC) The processor clock is four times faster than the master clock
// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
#define AT91C_PMC_LOCKA (0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask
#define AT91C_PMC_LOCKB (0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask
#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) Master Clock Status/Enable/Disable/Mask
#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Reset Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_RSTC {
AT91_REG RSTC_RCR; // Reset Control Register
AT91_REG RSTC_RSR; // Reset Status Register
AT91_REG RSTC_RMR; // Reset Mode Register
} AT91S_RSTC, *AT91PS_RSTC;
#else
#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register
#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register
#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register
#endif
// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset
#define AT91C_RSTC_ICERST (0x1 << 1) // (RSTC) ICE Interface Reset
#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset
#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset
#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password
// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status
#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type
#define AT91C_RSTC_RSTTYP_GENERAL (0x0 << 8) // (RSTC) General reset. Both VDDCORE and VDDBU rising.
#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level
#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.
// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable
#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable
#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Shut Down Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_SHDWC {
AT91_REG SHDWC_SHCR; // Shut Down Control Register
AT91_REG SHDWC_SHMR; // Shut Down Mode Register
AT91_REG SHDWC_SHSR; // Shut Down Status Register
} AT91S_SHDWC, *AT91PS_SHDWC;
#else
#define SHDWC_SHCR (AT91_CAST(AT91_REG *) 0x00000000) // (SHDWC_SHCR) Shut Down Control Register
#define SHDWC_SHMR (AT91_CAST(AT91_REG *) 0x00000004) // (SHDWC_SHMR) Shut Down Mode Register
#define SHDWC_SHSR (AT91_CAST(AT91_REG *) 0x00000008) // (SHDWC_SHSR) Shut Down Status Register
#endif
// -------- SHDWC_SHCR : (SHDWC Offset: 0x0) Shut Down Control Register --------
#define AT91C_SHDWC_SHDW (0x1 << 0) // (SHDWC) Processor Reset
#define AT91C_SHDWC_KEY (0xFF << 24) // (SHDWC) Shut down KEY Password
// -------- SHDWC_SHMR : (SHDWC Offset: 0x4) Shut Down Mode Register --------
#define AT91C_SHDWC_WKMODE0 (0x3 << 0) // (SHDWC) Wake Up 0 Mode Selection
#define AT91C_SHDWC_WKMODE0_NONE (0x0) // (SHDWC) None. No detection is performed on the wake up input.
#define AT91C_SHDWC_WKMODE0_HIGH (0x1) // (SHDWC) High Level.
#define AT91C_SHDWC_WKMODE0_LOW (0x2) // (SHDWC) Low Level.
#define AT91C_SHDWC_WKMODE0_ANYLEVEL (0x3) // (SHDWC) Any level change.
#define AT91C_SHDWC_CPTWK0 (0xF << 4) // (SHDWC) Counter On Wake Up 0
#define AT91C_SHDWC_WKMODE1 (0x3 << 8) // (SHDWC) Wake Up 1 Mode Selection
#define AT91C_SHDWC_WKMODE1_NONE (0x0 << 8) // (SHDWC) None. No detection is performed on the wake up input.
#define AT91C_SHDWC_WKMODE1_HIGH (0x1 << 8) // (SHDWC) High Level.
#define AT91C_SHDWC_WKMODE1_LOW (0x2 << 8) // (SHDWC) Low Level.
#define AT91C_SHDWC_WKMODE1_ANYLEVEL (0x3 << 8) // (SHDWC) Any level change.
#define AT91C_SHDWC_CPTWK1 (0xF << 12) // (SHDWC) Counter On Wake Up 1
#define AT91C_SHDWC_RTTWKEN (0x1 << 16) // (SHDWC) Real Time Timer Wake Up Enable
#define AT91C_SHDWC_RTCWKEN (0x1 << 17) // (SHDWC) Real Time Clock Wake Up Enable
// -------- SHDWC_SHSR : (SHDWC Offset: 0x8) Shut Down Status Register --------
#define AT91C_SHDWC_WAKEUP0 (0x1 << 0) // (SHDWC) Wake Up 0 Status
#define AT91C_SHDWC_WAKEUP1 (0x1 << 1) // (SHDWC) Wake Up 1 Status
#define AT91C_SHDWC_FWKUP (0x1 << 2) // (SHDWC) Force Wake Up Status
#define AT91C_SHDWC_RTTWK (0x1 << 16) // (SHDWC) Real Time Timer wake Up
#define AT91C_SHDWC_RTCWK (0x1 << 17) // (SHDWC) Real Time Clock wake Up
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_RTTC {
AT91_REG RTTC_RTMR; // Real-time Mode Register
AT91_REG RTTC_RTAR; // Real-time Alarm Register
AT91_REG RTTC_RTVR; // Real-time Value Register
AT91_REG RTTC_RTSR; // Real-time Status Register
} AT91S_RTTC, *AT91PS_RTTC;
#else
#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register
#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register
#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register
#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register
#endif
// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable
#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart
// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value
// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value
// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status
#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_PITC {
AT91_REG PITC_PIMR; // Period Interval Mode Register
AT91_REG PITC_PISR; // Period Interval Status Register
AT91_REG PITC_PIVR; // Period Interval Value Register
AT91_REG PITC_PIIR; // Period Interval Image Register
} AT91S_PITC, *AT91PS_PITC;
#else
#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register
#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register
#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register
#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register
#endif
// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value
#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status
// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value
#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter
// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_WDTC {
AT91_REG WDTC_WDCR; // Watchdog Control Register
AT91_REG WDTC_WDMR; // Watchdog Mode Register
AT91_REG WDTC_WDSR; // Watchdog Status Register
} AT91S_WDTC, *AT91PS_WDTC;
#else
#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register
#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register
#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register
#endif
// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart
#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password
// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart
#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable
#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart
#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable
#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value
#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt
#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt
// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow
#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_TC {
AT91_REG TC_CCR; // Channel Control Register
AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
AT91_REG Reserved0[2]; //
AT91_REG TC_CV; // Counter Value
AT91_REG TC_RA; // Register A
AT91_REG TC_RB; // Register B
AT91_REG TC_RC; // Register C
AT91_REG TC_SR; // Status Register
AT91_REG TC_IER; // Interrupt Enable Register
AT91_REG TC_IDR; // Interrupt Disable Register
AT91_REG TC_IMR; // Interrupt Mask Register
} AT91S_TC, *AT91PS_TC;
#else
#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register
#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)
#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value
#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A
#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B
#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C
#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register
#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register
#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register
#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register
#endif
// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command
#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command
#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command
// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection
#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0
#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1
#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2
#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert
#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection
#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal
#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock
#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock
#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock
#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare
#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection
#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None
#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection
#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None
#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection
#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable
#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection
#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable
#define AT91C_TC_WAVE (0x1 << 15) // (TC)
#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA
#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none
#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set
#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear
#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle
#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection
#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None
#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA
#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA
#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA
#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA
#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none
#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set
#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear
#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle
#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection
#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None
#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA
#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA
#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA
#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA
#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none
#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set
#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear
#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle
#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA
#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none
#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set
#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear
#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle
#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB
#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none
#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set
#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear
#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle
#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB
#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none
#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set
#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear
#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle
#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB
#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none
#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set
#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear
#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle
#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB
#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none
#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set
#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear
#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle
// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow
#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun
#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare
#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare
#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare
#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading
#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading
#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger
#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling
#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror
#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror
// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Timer Counter Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_TCB {
AT91S_TC TCB_TC0; // TC Channel 0
AT91_REG Reserved0[4]; //
AT91S_TC TCB_TC1; // TC Channel 1
AT91_REG Reserved1[4]; //
AT91S_TC TCB_TC2; // TC Channel 2
AT91_REG Reserved2[4]; //
AT91_REG TCB_BCR; // TC Block Control Register
AT91_REG TCB_BMR; // TC Block Mode Register
} AT91S_TCB, *AT91PS_TCB;
#else
#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register
#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register
#endif
// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command
// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection
#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0
#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0
#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0
#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0
#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection
#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1
#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1
#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1
#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1
#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection
#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2
#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2
#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2
#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Multimedia Card Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_MCI {
AT91_REG MCI_CR; // MCI Control Register
AT91_REG MCI_MR; // MCI Mode Register
AT91_REG MCI_DTOR; // MCI Data Timeout Register
AT91_REG MCI_SDCR; // MCI SD Card Register
AT91_REG MCI_ARGR; // MCI Argument Register
AT91_REG MCI_CMDR; // MCI Command Register
AT91_REG MCI_BLKR; // MCI Block Register
AT91_REG Reserved0[1]; //
AT91_REG MCI_RSPR[4]; // MCI Response Register
AT91_REG MCI_RDR; // MCI Receive Data Register
AT91_REG MCI_TDR; // MCI Transmit Data Register
AT91_REG Reserved1[2]; //
AT91_REG MCI_SR; // MCI Status Register
AT91_REG MCI_IER; // MCI Interrupt Enable Register
AT91_REG MCI_IDR; // MCI Interrupt Disable Register
AT91_REG MCI_IMR; // MCI Interrupt Mask Register
AT91_REG Reserved2[43]; //
AT91_REG MCI_VR; // MCI Version Register
AT91_REG MCI_RPR; // Receive Pointer Register
AT91_REG MCI_RCR; // Receive Counter Register
AT91_REG MCI_TPR; // Transmit Pointer Register
AT91_REG MCI_TCR; // Transmit Counter Register
AT91_REG MCI_RNPR; // Receive Next Pointer Register
AT91_REG MCI_RNCR; // Receive Next Counter Register
AT91_REG MCI_TNPR; // Transmit Next Pointer Register
AT91_REG MCI_TNCR; // Transmit Next Counter Register
AT91_REG MCI_PTCR; // PDC Transfer Control Register
AT91_REG MCI_PTSR; // PDC Transfer Status Register
} AT91S_MCI, *AT91PS_MCI;
#else
#define MCI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (MCI_CR) MCI Control Register
#define MCI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (MCI_MR) MCI Mode Register
#define MCI_DTOR (AT91_CAST(AT91_REG *) 0x00000008) // (MCI_DTOR) MCI Data Timeout Register
#define MCI_SDCR (AT91_CAST(AT91_REG *) 0x0000000C) // (MCI_SDCR) MCI SD Card Register
#define MCI_ARGR (AT91_CAST(AT91_REG *) 0x00000010) // (MCI_ARGR) MCI Argument Register
#define MCI_CMDR (AT91_CAST(AT91_REG *) 0x00000014) // (MCI_CMDR) MCI Command Register
#define MCI_BLKR (AT91_CAST(AT91_REG *) 0x00000018) // (MCI_BLKR) MCI Block Register
#define MCI_RSPR (AT91_CAST(AT91_REG *) 0x00000020) // (MCI_RSPR) MCI Response Register
#define MCI_RDR (AT91_CAST(AT91_REG *) 0x00000030) // (MCI_RDR) MCI Receive Data Register
#define MCI_TDR (AT91_CAST(AT91_REG *) 0x00000034) // (MCI_TDR) MCI Transmit Data Register
#define MCI_SR (AT91_CAST(AT91_REG *) 0x00000040) // (MCI_SR) MCI Status Register
#define MCI_IER (AT91_CAST(AT91_REG *) 0x00000044) // (MCI_IER) MCI Interrupt Enable Register
#define MCI_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (MCI_IDR) MCI Interrupt Disable Register
#define MCI_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (MCI_IMR) MCI Interrupt Mask Register
#define MCI_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (MCI_VR) MCI Version Register
#endif
// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register --------
#define AT91C_MCI_MCIEN (0x1 << 0) // (MCI) Multimedia Interface Enable
#define AT91C_MCI_MCIDIS (0x1 << 1) // (MCI) Multimedia Interface Disable
#define AT91C_MCI_PWSEN (0x1 << 2) // (MCI) Power Save Mode Enable
#define AT91C_MCI_PWSDIS (0x1 << 3) // (MCI) Power Save Mode Disable
#define AT91C_MCI_SWRST (0x1 << 7) // (MCI) MCI Software reset
// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register --------
#define AT91C_MCI_CLKDIV (0xFF << 0) // (MCI) Clock Divider
#define AT91C_MCI_PWSDIV (0x7 << 8) // (MCI) Power Saving Divider
#define AT91C_MCI_RDPROOF (0x1 << 11) // (MCI) Read Proof Enable
#define AT91C_MCI_WRPROOF (0x1 << 12) // (MCI) Write Proof Enable
#define AT91C_MCI_PDCFBYTE (0x1 << 13) // (MCI) PDC Force Byte Transfer
#define AT91C_MCI_PDCPADV (0x1 << 14) // (MCI) PDC Padding Value
#define AT91C_MCI_PDCMODE (0x1 << 15) // (MCI) PDC Oriented Mode
#define AT91C_MCI_BLKLEN (0xFFFF << 16) // (MCI) Data Block Length
// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register --------
#define AT91C_MCI_DTOCYC (0xF << 0) // (MCI) Data Timeout Cycle Number
#define AT91C_MCI_DTOMUL (0x7 << 4) // (MCI) Data Timeout Multiplier
#define AT91C_MCI_DTOMUL_1 (0x0 << 4) // (MCI) DTOCYC x 1
#define AT91C_MCI_DTOMUL_16 (0x1 << 4) // (MCI) DTOCYC x 16
#define AT91C_MCI_DTOMUL_128 (0x2 << 4) // (MCI) DTOCYC x 128
#define AT91C_MCI_DTOMUL_256 (0x3 << 4) // (MCI) DTOCYC x 256
#define AT91C_MCI_DTOMUL_1024 (0x4 << 4) // (MCI) DTOCYC x 1024
#define AT91C_MCI_DTOMUL_4096 (0x5 << 4) // (MCI) DTOCYC x 4096
#define AT91C_MCI_DTOMUL_65536 (0x6 << 4) // (MCI) DTOCYC x 65536
#define AT91C_MCI_DTOMUL_1048576 (0x7 << 4) // (MCI) DTOCYC x 1048576
// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register --------
#define AT91C_MCI_SCDSEL (0x3 << 0) // (MCI) SD Card Selector
#define AT91C_MCI_SCDBUS (0x1 << 7) // (MCI) SDCard/SDIO Bus Width
// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register --------
#define AT91C_MCI_CMDNB (0x3F << 0) // (MCI) Command Number
#define AT91C_MCI_RSPTYP (0x3 << 6) // (MCI) Response Type
#define AT91C_MCI_RSPTYP_NO (0x0 << 6) // (MCI) No response
#define AT91C_MCI_RSPTYP_48 (0x1 << 6) // (MCI) 48-bit response
#define AT91C_MCI_RSPTYP_136 (0x2 << 6) // (MCI) 136-bit response
#define AT91C_MCI_SPCMD (0x7 << 8) // (MCI) Special CMD
#define AT91C_MCI_SPCMD_NONE (0x0 << 8) // (MCI) Not a special CMD
#define AT91C_MCI_SPCMD_INIT (0x1 << 8) // (MCI) Initialization CMD
#define AT91C_MCI_SPCMD_SYNC (0x2 << 8) // (MCI) Synchronized CMD
#define AT91C_MCI_SPCMD_IT_CMD (0x4 << 8) // (MCI) Interrupt command
#define AT91C_MCI_SPCMD_IT_REP (0x5 << 8) // (MCI) Interrupt response
#define AT91C_MCI_OPDCMD (0x1 << 11) // (MCI) Open Drain Command
#define AT91C_MCI_MAXLAT (0x1 << 12) // (MCI) Maximum Latency for Command to respond
#define AT91C_MCI_TRCMD (0x3 << 16) // (MCI) Transfer CMD
#define AT91C_MCI_TRCMD_NO (0x0 << 16) // (MCI) No transfer
#define AT91C_MCI_TRCMD_START (0x1 << 16) // (MCI) Start transfer
#define AT91C_MCI_TRCMD_STOP (0x2 << 16) // (MCI) Stop transfer
#define AT91C_MCI_TRDIR (0x1 << 18) // (MCI) Transfer Direction
#define AT91C_MCI_TRTYP (0x7 << 19) // (MCI) Transfer Type
#define AT91C_MCI_TRTYP_BLOCK (0x0 << 19) // (MCI) MMC/SDCard Single Block Transfer type
#define AT91C_MCI_TRTYP_MULTIPLE (0x1 << 19) // (MCI) MMC/SDCard Multiple Block transfer type
#define AT91C_MCI_TRTYP_STREAM (0x2 << 19) // (MCI) MMC Stream transfer type
#define AT91C_MCI_TRTYP_SDIO_BYTE (0x4 << 19) // (MCI) SDIO Byte transfer type
#define AT91C_MCI_TRTYP_SDIO_BLOCK (0x5 << 19) // (MCI) SDIO Block transfer type
#define AT91C_MCI_IOSPCMD (0x3 << 24) // (MCI) SDIO Special Command
#define AT91C_MCI_IOSPCMD_NONE (0x0 << 24) // (MCI) NOT a special command
#define AT91C_MCI_IOSPCMD_SUSPEND (0x1 << 24) // (MCI) SDIO Suspend Command
#define AT91C_MCI_IOSPCMD_RESUME (0x2 << 24) // (MCI) SDIO Resume Command
// -------- MCI_BLKR : (MCI Offset: 0x18) MCI Block Register --------
#define AT91C_MCI_BCNT (0xFFFF << 0) // (MCI) MMC/SDIO Block Count / SDIO Byte Count
// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register --------
#define AT91C_MCI_CMDRDY (0x1 << 0) // (MCI) Command Ready flag
#define AT91C_MCI_RXRDY (0x1 << 1) // (MCI) RX Ready flag
#define AT91C_MCI_TXRDY (0x1 << 2) // (MCI) TX Ready flag
#define AT91C_MCI_BLKE (0x1 << 3) // (MCI) Data Block Transfer Ended flag
#define AT91C_MCI_DTIP (0x1 << 4) // (MCI) Data Transfer in Progress flag
#define AT91C_MCI_NOTBUSY (0x1 << 5) // (MCI) Data Line Not Busy flag
#define AT91C_MCI_ENDRX (0x1 << 6) // (MCI) End of RX Buffer flag
#define AT91C_MCI_ENDTX (0x1 << 7) // (MCI) End of TX Buffer flag
#define AT91C_MCI_SDIOIRQA (0x1 << 8) // (MCI) SDIO Interrupt for Slot A
#define AT91C_MCI_SDIOIRQB (0x1 << 9) // (MCI) SDIO Interrupt for Slot B
#define AT91C_MCI_SDIOIRQC (0x1 << 10) // (MCI) SDIO Interrupt for Slot C
#define AT91C_MCI_SDIOIRQD (0x1 << 11) // (MCI) SDIO Interrupt for Slot D
#define AT91C_MCI_RXBUFF (0x1 << 14) // (MCI) RX Buffer Full flag
#define AT91C_MCI_TXBUFE (0x1 << 15) // (MCI) TX Buffer Empty flag
#define AT91C_MCI_RINDE (0x1 << 16) // (MCI) Response Index Error flag
#define AT91C_MCI_RDIRE (0x1 << 17) // (MCI) Response Direction Error flag
#define AT91C_MCI_RCRCE (0x1 << 18) // (MCI) Response CRC Error flag
#define AT91C_MCI_RENDE (0x1 << 19) // (MCI) Response End Bit Error flag
#define AT91C_MCI_RTOE (0x1 << 20) // (MCI) Response Time-out Error flag
#define AT91C_MCI_DCRCE (0x1 << 21) // (MCI) data CRC Error flag
#define AT91C_MCI_DTOE (0x1 << 22) // (MCI) Data timeout Error flag
#define AT91C_MCI_OVRE (0x1 << 30) // (MCI) Overrun flag
#define AT91C_MCI_UNRE (0x1 << 31) // (MCI) Underrun flag
// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register --------
// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register --------
// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Two-wire Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_TWI {
AT91_REG TWI_CR; // Control Register
AT91_REG TWI_MMR; // Master Mode Register
AT91_REG TWI_SMR; // Slave Mode Register
AT91_REG TWI_IADR; // Internal Address Register
AT91_REG TWI_CWGR; // Clock Waveform Generator Register
AT91_REG Reserved0[3]; //
AT91_REG TWI_SR; // Status Register
AT91_REG TWI_IER; // Interrupt Enable Register
AT91_REG TWI_IDR; // Interrupt Disable Register
AT91_REG TWI_IMR; // Interrupt Mask Register
AT91_REG TWI_RHR; // Receive Holding Register
AT91_REG TWI_THR; // Transmit Holding Register
AT91_REG Reserved1[50]; //
AT91_REG TWI_RPR; // Receive Pointer Register
AT91_REG TWI_RCR; // Receive Counter Register
AT91_REG TWI_TPR; // Transmit Pointer Register
AT91_REG TWI_TCR; // Transmit Counter Register
AT91_REG TWI_RNPR; // Receive Next Pointer Register
AT91_REG TWI_RNCR; // Receive Next Counter Register
AT91_REG TWI_TNPR; // Transmit Next Pointer Register
AT91_REG TWI_TNCR; // Transmit Next Counter Register
AT91_REG TWI_PTCR; // PDC Transfer Control Register
AT91_REG TWI_PTSR; // PDC Transfer Status Register
} AT91S_TWI, *AT91PS_TWI;
#else
#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register
#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register
#define TWI_SMR (AT91_CAST(AT91_REG *) 0x00000008) // (TWI_SMR) Slave Mode Register
#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register
#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register
#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register
#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register
#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register
#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register
#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register
#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register
#endif
// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition
#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition
#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled
#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled
#define AT91C_TWI_SVEN (0x1 << 4) // (TWI) TWI Slave mode Enabled
#define AT91C_TWI_SVDIS (0x1 << 5) // (TWI) TWI Slave mode Disabled
#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset
// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size
#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address
#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address
#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address
#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address
#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction
#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address
// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register --------
#define AT91C_TWI_SADR (0x7F << 16) // (TWI) Slave Address
// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider
#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider
#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider
// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
#define AT91C_TWI_TXCOMP_SLAVE (0x1 << 0) // (TWI) Transmission Completed
#define AT91C_TWI_TXCOMP_MASTER (0x1 << 0) // (TWI) Transmission Completed
#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY
#define AT91C_TWI_TXRDY_MASTER (0x1 << 2) // (TWI) Transmit holding register ReaDY
#define AT91C_TWI_TXRDY_SLAVE (0x1 << 2) // (TWI) Transmit holding register ReaDY
#define AT91C_TWI_SVREAD (0x1 << 3) // (TWI) Slave READ (used only in Slave mode)
#define AT91C_TWI_SVACC (0x1 << 4) // (TWI) Slave ACCess (used only in Slave mode)
#define AT91C_TWI_GACC (0x1 << 5) // (TWI) General Call ACcess (used only in Slave mode)
#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error (used only in Master and Multi-master mode)
#define AT91C_TWI_NACK_SLAVE (0x1 << 8) // (TWI) Not Acknowledged
#define AT91C_TWI_NACK_MASTER (0x1 << 8) // (TWI) Not Acknowledged
#define AT91C_TWI_ARBLST_MULTI_MASTER (0x1 << 9) // (TWI) Arbitration Lost (used only in Multimaster mode)
#define AT91C_TWI_SCLWS (0x1 << 10) // (TWI) Clock Wait State (used only in Slave mode)
#define AT91C_TWI_EOSACC (0x1 << 11) // (TWI) End Of Slave ACCess (used only in Slave mode)
#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) End of Receiver Transfer
#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) End of Receiver Transfer
#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) RXBUFF Interrupt
#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) TXBUFE Interrupt
// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Usart
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_USART {
AT91_REG US_CR; // Control Register
AT91_REG US_MR; // Mode Register
AT91_REG US_IER; // Interrupt Enable Register
AT91_REG US_IDR; // Interrupt Disable Register
AT91_REG US_IMR; // Interrupt Mask Register
AT91_REG US_CSR; // Channel Status Register
AT91_REG US_RHR; // Receiver Holding Register
AT91_REG US_THR; // Transmitter Holding Register
AT91_REG US_BRGR; // Baud Rate Generator Register
AT91_REG US_RTOR; // Receiver Time-out Register
AT91_REG US_TTGR; // Transmitter Time-guard Register
AT91_REG Reserved0[5]; //
AT91_REG US_FIDI; // FI_DI_Ratio Register
AT91_REG US_NER; // Nb Errors Register
AT91_REG Reserved1[1]; //
AT91_REG US_IF; // IRDA_FILTER Register
AT91_REG Reserved2[44]; //
AT91_REG US_RPR; // Receive Pointer Register
AT91_REG US_RCR; // Receive Counter Register
AT91_REG US_TPR; // Transmit Pointer Register
AT91_REG US_TCR; // Transmit Counter Register
AT91_REG US_RNPR; // Receive Next Pointer Register
AT91_REG US_RNCR; // Receive Next Counter Register
AT91_REG US_TNPR; // Transmit Next Pointer Register
AT91_REG US_TNCR; // Transmit Next Counter Register
AT91_REG US_PTCR; // PDC Transfer Control Register
AT91_REG US_PTSR; // PDC Transfer Status Register
} AT91S_USART, *AT91PS_USART;
#else
#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register
#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register
#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register
#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register
#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register
#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register
#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register
#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register
#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register
#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register
#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register
#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register
#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register
#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register
#endif
// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break
#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break
#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out
#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address
#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations
#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge
#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out
#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable
#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable
#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable
#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable
// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode
#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal
#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485
#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking
#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem
#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0
#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1
#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA
#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking
#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock
#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1
#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)
#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)
#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits
#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits
#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits
#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits
#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select
#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits
#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit
#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits
#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order
#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length
#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select
#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode
#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge
#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK
#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions
#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter
// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break
#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out
#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached
#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge
#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag
#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag
#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag
#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag
// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input
#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input
#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input
#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_SSC {
AT91_REG SSC_CR; // Control Register
AT91_REG SSC_CMR; // Clock Mode Register
AT91_REG Reserved0[2]; //
AT91_REG SSC_RCMR; // Receive Clock ModeRegister
AT91_REG SSC_RFMR; // Receive Frame Mode Register
AT91_REG SSC_TCMR; // Transmit Clock Mode Register
AT91_REG SSC_TFMR; // Transmit Frame Mode Register
AT91_REG SSC_RHR; // Receive Holding Register
AT91_REG SSC_THR; // Transmit Holding Register
AT91_REG Reserved1[2]; //
AT91_REG SSC_RSHR; // Receive Sync Holding Register
AT91_REG SSC_TSHR; // Transmit Sync Holding Register
AT91_REG Reserved2[2]; //
AT91_REG SSC_SR; // Status Register
AT91_REG SSC_IER; // Interrupt Enable Register
AT91_REG SSC_IDR; // Interrupt Disable Register
AT91_REG SSC_IMR; // Interrupt Mask Register
AT91_REG Reserved3[44]; //
AT91_REG SSC_RPR; // Receive Pointer Register
AT91_REG SSC_RCR; // Receive Counter Register
AT91_REG SSC_TPR; // Transmit Pointer Register
AT91_REG SSC_TCR; // Transmit Counter Register
AT91_REG SSC_RNPR; // Receive Next Pointer Register
AT91_REG SSC_RNCR; // Receive Next Counter Register
AT91_REG SSC_TNPR; // Transmit Next Pointer Register
AT91_REG SSC_TNCR; // Transmit Next Counter Register
AT91_REG SSC_PTCR; // PDC Transfer Control Register
AT91_REG SSC_PTSR; // PDC Transfer Status Register
} AT91S_SSC, *AT91PS_SSC;
#else
#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register
#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register
#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister
#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register
#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register
#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register
#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register
#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register
#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register
#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register
#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register
#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register
#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register
#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register
#endif
// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable
#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable
#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable
#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable
#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset
// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection
#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock
#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal
#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin
#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection
#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start
#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input
#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input
#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input
#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input
#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input
#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input
#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0
#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay
#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length
#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode
#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First
#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame
#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection
// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value
#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable
// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready
#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty
#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission
#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty
#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready
#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun
#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception
#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full
#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync
#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync
#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable
#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable
// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Serial Parallel Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_SPI {
AT91_REG SPI_CR; // Control Register
AT91_REG SPI_MR; // Mode Register
AT91_REG SPI_RDR; // Receive Data Register
AT91_REG SPI_TDR; // Transmit Data Register
AT91_REG SPI_SR; // Status Register
AT91_REG SPI_IER; // Interrupt Enable Register
AT91_REG SPI_IDR; // Interrupt Disable Register
AT91_REG SPI_IMR; // Interrupt Mask Register
AT91_REG Reserved0[4]; //
AT91_REG SPI_CSR[4]; // Chip Select Register
AT91_REG Reserved1[48]; //
AT91_REG SPI_RPR; // Receive Pointer Register
AT91_REG SPI_RCR; // Receive Counter Register
AT91_REG SPI_TPR; // Transmit Pointer Register
AT91_REG SPI_TCR; // Transmit Counter Register
AT91_REG SPI_RNPR; // Receive Next Pointer Register
AT91_REG SPI_RNCR; // Receive Next Counter Register
AT91_REG SPI_TNPR; // Transmit Next Pointer Register
AT91_REG SPI_TNCR; // Transmit Next Counter Register
AT91_REG SPI_PTCR; // PDC Transfer Control Register
AT91_REG SPI_PTSR; // PDC Transfer Status Register
} AT91S_SPI, *AT91PS_SPI;
#else
#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register
#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register
#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register
#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register
#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register
#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register
#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register
#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register
#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register
#endif
// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable
#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable
#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset
#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer
// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode
#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select
#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select
#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select
#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode
#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection
#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection
#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection
#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select
#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects
// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data
#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data
#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full
#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty
#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error
#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status
#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer
#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer
#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt
#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt
#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt
#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt
#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status
// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity
#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase
#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer
#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer
#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer
#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer
#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer
#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer
#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer
#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer
#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer
#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer
#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer
#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate
#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK
#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_ADC {
AT91_REG ADC_CR; // ADC Control Register
AT91_REG ADC_MR; // ADC Mode Register
AT91_REG Reserved0[2]; //
AT91_REG ADC_CHER; // ADC Channel Enable Register
AT91_REG ADC_CHDR; // ADC Channel Disable Register
AT91_REG ADC_CHSR; // ADC Channel Status Register
AT91_REG ADC_SR; // ADC Status Register
AT91_REG ADC_LCDR; // ADC Last Converted Data Register
AT91_REG ADC_IER; // ADC Interrupt Enable Register
AT91_REG ADC_IDR; // ADC Interrupt Disable Register
AT91_REG ADC_IMR; // ADC Interrupt Mask Register
AT91_REG ADC_CDR0; // ADC Channel Data Register 0
AT91_REG ADC_CDR1; // ADC Channel Data Register 1
AT91_REG ADC_CDR2; // ADC Channel Data Register 2
AT91_REG ADC_CDR3; // ADC Channel Data Register 3
AT91_REG ADC_CDR4; // ADC Channel Data Register 4
AT91_REG ADC_CDR5; // ADC Channel Data Register 5
AT91_REG ADC_CDR6; // ADC Channel Data Register 6
AT91_REG ADC_CDR7; // ADC Channel Data Register 7
AT91_REG Reserved1[44]; //
AT91_REG ADC_RPR; // Receive Pointer Register
AT91_REG ADC_RCR; // Receive Counter Register
AT91_REG ADC_TPR; // Transmit Pointer Register
AT91_REG ADC_TCR; // Transmit Counter Register
AT91_REG ADC_RNPR; // Receive Next Pointer Register
AT91_REG ADC_RNCR; // Receive Next Counter Register
AT91_REG ADC_TNPR; // Transmit Next Pointer Register
AT91_REG ADC_TNCR; // Transmit Next Counter Register
AT91_REG ADC_PTCR; // PDC Transfer Control Register
AT91_REG ADC_PTSR; // PDC Transfer Status Register
} AT91S_ADC, *AT91PS_ADC;
#else
#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register
#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register
#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register
#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register
#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register
#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register
#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register
#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register
#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register
#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register
#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0
#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1
#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2
#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3
#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4
#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5
#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6
#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7
#endif
// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset
#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion
// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable
#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection
#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.
#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution
#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution
#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode
#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode
#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode
#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection
#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time
#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time
// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0
#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1
#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2
#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3
#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4
#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5
#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6
#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7
// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion
#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion
#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion
#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion
#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion
#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion
#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion
#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion
#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error
#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error
#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error
#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error
#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error
#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error
#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error
#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error
#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready
#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun
#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer
#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt
// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted
// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data
// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_EMAC {
AT91_REG EMAC_NCR; // Network Control Register
AT91_REG EMAC_NCFGR; // Network Configuration Register
AT91_REG EMAC_NSR; // Network Status Register
AT91_REG Reserved0[2]; //
AT91_REG EMAC_TSR; // Transmit Status Register
AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer
AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer
AT91_REG EMAC_RSR; // Receive Status Register
AT91_REG EMAC_ISR; // Interrupt Status Register
AT91_REG EMAC_IER; // Interrupt Enable Register
AT91_REG EMAC_IDR; // Interrupt Disable Register
AT91_REG EMAC_IMR; // Interrupt Mask Register
AT91_REG EMAC_MAN; // PHY Maintenance Register
AT91_REG EMAC_PTR; // Pause Time Register
AT91_REG EMAC_PFR; // Pause Frames received Register
AT91_REG EMAC_FTO; // Frames Transmitted OK Register
AT91_REG EMAC_SCF; // Single Collision Frame Register
AT91_REG EMAC_MCF; // Multiple Collision Frame Register
AT91_REG EMAC_FRO; // Frames Received OK Register
AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register
AT91_REG EMAC_ALE; // Alignment Error Register
AT91_REG EMAC_DTF; // Deferred Transmission Frame Register
AT91_REG EMAC_LCOL; // Late Collision Register
AT91_REG EMAC_ECOL; // Excessive Collision Register
AT91_REG EMAC_TUND; // Transmit Underrun Error Register
AT91_REG EMAC_CSE; // Carrier Sense Error Register
AT91_REG EMAC_RRE; // Receive Ressource Error Register
AT91_REG EMAC_ROV; // Receive Overrun Errors Register
AT91_REG EMAC_RSE; // Receive Symbol Errors Register
AT91_REG EMAC_ELE; // Excessive Length Errors Register
AT91_REG EMAC_RJA; // Receive Jabbers Register
AT91_REG EMAC_USF; // Undersize Frames Register
AT91_REG EMAC_STE; // SQE Test Error Register
AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register
AT91_REG EMAC_TPF; // Transmitted Pause Frames Register
AT91_REG EMAC_HRB; // Hash Address Bottom[31:0]
AT91_REG EMAC_HRT; // Hash Address Top[63:32]
AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes
AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes
AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes
AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes
AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes
AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes
AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes
AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes
AT91_REG EMAC_TID; // Type ID Checking Register
AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register
AT91_REG EMAC_USRIO; // USER Input/Output Register
AT91_REG EMAC_WOL; // Wake On LAN Register
AT91_REG Reserved1[13]; //
AT91_REG EMAC_REV; // Revision Register
} AT91S_EMAC, *AT91PS_EMAC;
#else
#define EMAC_NCR (AT91_CAST(AT91_REG *) 0x00000000) // (EMAC_NCR) Network Control Register
#define EMAC_NCFGR (AT91_CAST(AT91_REG *) 0x00000004) // (EMAC_NCFGR) Network Configuration Register
#define EMAC_NSR (AT91_CAST(AT91_REG *) 0x00000008) // (EMAC_NSR) Network Status Register
#define EMAC_TSR (AT91_CAST(AT91_REG *) 0x00000014) // (EMAC_TSR) Transmit Status Register
#define EMAC_RBQP (AT91_CAST(AT91_REG *) 0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer
#define EMAC_TBQP (AT91_CAST(AT91_REG *) 0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer
#define EMAC_RSR (AT91_CAST(AT91_REG *) 0x00000020) // (EMAC_RSR) Receive Status Register
#define EMAC_ISR (AT91_CAST(AT91_REG *) 0x00000024) // (EMAC_ISR) Interrupt Status Register
#define EMAC_IER (AT91_CAST(AT91_REG *) 0x00000028) // (EMAC_IER) Interrupt Enable Register
#define EMAC_IDR (AT91_CAST(AT91_REG *) 0x0000002C) // (EMAC_IDR) Interrupt Disable Register
#define EMAC_IMR (AT91_CAST(AT91_REG *) 0x00000030) // (EMAC_IMR) Interrupt Mask Register
#define EMAC_MAN (AT91_CAST(AT91_REG *) 0x00000034) // (EMAC_MAN) PHY Maintenance Register
#define EMAC_PTR (AT91_CAST(AT91_REG *) 0x00000038) // (EMAC_PTR) Pause Time Register
#define EMAC_PFR (AT91_CAST(AT91_REG *) 0x0000003C) // (EMAC_PFR) Pause Frames received Register
#define EMAC_FTO (AT91_CAST(AT91_REG *) 0x00000040) // (EMAC_FTO) Frames Transmitted OK Register
#define EMAC_SCF (AT91_CAST(AT91_REG *) 0x00000044) // (EMAC_SCF) Single Collision Frame Register
#define EMAC_MCF (AT91_CAST(AT91_REG *) 0x00000048) // (EMAC_MCF) Multiple Collision Frame Register
#define EMAC_FRO (AT91_CAST(AT91_REG *) 0x0000004C) // (EMAC_FRO) Frames Received OK Register
#define EMAC_FCSE (AT91_CAST(AT91_REG *) 0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register
#define EMAC_ALE (AT91_CAST(AT91_REG *) 0x00000054) // (EMAC_ALE) Alignment Error Register
#define EMAC_DTF (AT91_CAST(AT91_REG *) 0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register
#define EMAC_LCOL (AT91_CAST(AT91_REG *) 0x0000005C) // (EMAC_LCOL) Late Collision Register
#define EMAC_ECOL (AT91_CAST(AT91_REG *) 0x00000060) // (EMAC_ECOL) Excessive Collision Register
#define EMAC_TUND (AT91_CAST(AT91_REG *) 0x00000064) // (EMAC_TUND) Transmit Underrun Error Register
#define EMAC_CSE (AT91_CAST(AT91_REG *) 0x00000068) // (EMAC_CSE) Carrier Sense Error Register
#define EMAC_RRE (AT91_CAST(AT91_REG *) 0x0000006C) // (EMAC_RRE) Receive Ressource Error Register
#define EMAC_ROV (AT91_CAST(AT91_REG *) 0x00000070) // (EMAC_ROV) Receive Overrun Errors Register
#define EMAC_RSE (AT91_CAST(AT91_REG *) 0x00000074) // (EMAC_RSE) Receive Symbol Errors Register
#define EMAC_ELE (AT91_CAST(AT91_REG *) 0x00000078) // (EMAC_ELE) Excessive Length Errors Register
#define EMAC_RJA (AT91_CAST(AT91_REG *) 0x0000007C) // (EMAC_RJA) Receive Jabbers Register
#define EMAC_USF (AT91_CAST(AT91_REG *) 0x00000080) // (EMAC_USF) Undersize Frames Register
#define EMAC_STE (AT91_CAST(AT91_REG *) 0x00000084) // (EMAC_STE) SQE Test Error Register
#define EMAC_RLE (AT91_CAST(AT91_REG *) 0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register
#define EMAC_TPF (AT91_CAST(AT91_REG *) 0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register
#define EMAC_HRB (AT91_CAST(AT91_REG *) 0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0]
#define EMAC_HRT (AT91_CAST(AT91_REG *) 0x00000094) // (EMAC_HRT) Hash Address Top[63:32]
#define EMAC_SA1L (AT91_CAST(AT91_REG *) 0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes
#define EMAC_SA1H (AT91_CAST(AT91_REG *) 0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes
#define EMAC_SA2L (AT91_CAST(AT91_REG *) 0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes
#define EMAC_SA2H (AT91_CAST(AT91_REG *) 0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes
#define EMAC_SA3L (AT91_CAST(AT91_REG *) 0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes
#define EMAC_SA3H (AT91_CAST(AT91_REG *) 0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes
#define EMAC_SA4L (AT91_CAST(AT91_REG *) 0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes
#define EMAC_SA4H (AT91_CAST(AT91_REG *) 0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes
#define EMAC_TID (AT91_CAST(AT91_REG *) 0x000000B8) // (EMAC_TID) Type ID Checking Register
#define EMAC_TPQ (AT91_CAST(AT91_REG *) 0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register
#define EMAC_USRIO (AT91_CAST(AT91_REG *) 0x000000C0) // (EMAC_USRIO) USER Input/Output Register
#define EMAC_WOL (AT91_CAST(AT91_REG *) 0x000000C4) // (EMAC_WOL) Wake On LAN Register
#define EMAC_REV (AT91_CAST(AT91_REG *) 0x000000FC) // (EMAC_REV) Revision Register
#endif
// -------- EMAC_NCR : (EMAC Offset: 0x0) --------
#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local.
#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable.
#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable.
#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable.
#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers.
#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers.
#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers.
#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure.
#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission.
#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt.
#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame
#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame
// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed.
#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex.
#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames.
#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames.
#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast.
#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable
#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable.
#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes.
#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable.
#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC)
#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8
#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16
#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32
#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64
#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC)
#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC)
#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC)
#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer
#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer
#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable
#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS
#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC)
#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS
// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC)
#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC)
#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC)
// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC)
#define AT91C_EMAC_COL (0x1 << 1) // (EMAC)
#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC)
#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go
#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame
#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC)
#define AT91C_EMAC_UND (0x1 << 6) // (EMAC)
// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC)
#define AT91C_EMAC_REC (0x1 << 1) // (EMAC)
#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC)
// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC)
#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC)
#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC)
#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC)
#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC)
#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC)
#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC)
#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC)
#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC)
#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC)
#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC)
#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC)
#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC)
// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC)
#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC)
#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC)
#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC)
#define AT91C_EMAC_RW (0x3 << 28) // (EMAC)
#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC)
// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII
#define AT91C_EMAC_CLKEN (0x1 << 1) // (EMAC) Clock Enable
// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address
#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable
#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable
#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable
// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC)
#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC)
// *****************************************************************************
// SOFTWARE API DEFINITION FOR USB Device Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_UDP {
AT91_REG UDP_NUM; // Frame Number Register
AT91_REG UDP_GLBSTATE; // Global State Register
AT91_REG UDP_FADDR; // Function Address Register
AT91_REG Reserved0[1]; //
AT91_REG UDP_IER; // Interrupt Enable Register
AT91_REG UDP_IDR; // Interrupt Disable Register
AT91_REG UDP_IMR; // Interrupt Mask Register
AT91_REG UDP_ISR; // Interrupt Status Register
AT91_REG UDP_ICR; // Interrupt Clear Register
AT91_REG Reserved1[1]; //
AT91_REG UDP_RSTEP; // Reset Endpoint Register
AT91_REG Reserved2[1]; //
AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register
AT91_REG Reserved3[2]; //
AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register
AT91_REG Reserved4[3]; //
AT91_REG UDP_TXVC; // Transceiver Control Register
} AT91S_UDP, *AT91PS_UDP;
#else
#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register
#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register
#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register
#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register
#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register
#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register
#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register
#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register
#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register
#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register
#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register
#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register
#endif
// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error
#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK
// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable
#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured
#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume
#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable
// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value
#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable
// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt
#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt
#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt
#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt
#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt
#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt
#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt
#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt
#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt
#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt
#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt
// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0
#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1
#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2
#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3
#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4
#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5
// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0
#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints)
#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready
#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction
#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type
#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control
#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT
#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT
#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT
#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN
#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN
#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN
#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle
#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable
#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP)
#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON
// *****************************************************************************
// SOFTWARE API DEFINITION FOR USB Host Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_UHP {
AT91_REG UHP_HcRevision; // Revision
AT91_REG UHP_HcControl; // Operating modes for the Host Controller
AT91_REG UHP_HcCommandStatus; // Command & status Register
AT91_REG UHP_HcInterruptStatus; // Interrupt Status Register
AT91_REG UHP_HcInterruptEnable; // Interrupt Enable Register
AT91_REG UHP_HcInterruptDisable; // Interrupt Disable Register
AT91_REG UHP_HcHCCA; // Pointer to the Host Controller Communication Area
AT91_REG UHP_HcPeriodCurrentED; // Current Isochronous or Interrupt Endpoint Descriptor
AT91_REG UHP_HcControlHeadED; // First Endpoint Descriptor of the Control list
AT91_REG UHP_HcControlCurrentED; // Endpoint Control and Status Register
AT91_REG UHP_HcBulkHeadED; // First endpoint register of the Bulk list
AT91_REG UHP_HcBulkCurrentED; // Current endpoint of the Bulk list
AT91_REG UHP_HcBulkDoneHead; // Last completed transfer descriptor
AT91_REG UHP_HcFmInterval; // Bit time between 2 consecutive SOFs
AT91_REG UHP_HcFmRemaining; // Bit time remaining in the current Frame
AT91_REG UHP_HcFmNumber; // Frame number
AT91_REG UHP_HcPeriodicStart; // Periodic Start
AT91_REG UHP_HcLSThreshold; // LS Threshold
AT91_REG UHP_HcRhDescriptorA; // Root Hub characteristics A
AT91_REG UHP_HcRhDescriptorB; // Root Hub characteristics B
AT91_REG UHP_HcRhStatus; // Root Hub Status register
AT91_REG UHP_HcRhPortStatus[2]; // Root Hub Port Status Register
} AT91S_UHP, *AT91PS_UHP;
#else
#define HcRevision (AT91_CAST(AT91_REG *) 0x00000000) // (HcRevision) Revision
#define HcControl (AT91_CAST(AT91_REG *) 0x00000004) // (HcControl) Operating modes for the Host Controller
#define HcCommandStatus (AT91_CAST(AT91_REG *) 0x00000008) // (HcCommandStatus) Command & status Register
#define HcInterruptStatus (AT91_CAST(AT91_REG *) 0x0000000C) // (HcInterruptStatus) Interrupt Status Register
#define HcInterruptEnable (AT91_CAST(AT91_REG *) 0x00000010) // (HcInterruptEnable) Interrupt Enable Register
#define HcInterruptDisable (AT91_CAST(AT91_REG *) 0x00000014) // (HcInterruptDisable) Interrupt Disable Register
#define HcHCCA (AT91_CAST(AT91_REG *) 0x00000018) // (HcHCCA) Pointer to the Host Controller Communication Area
#define HcPeriodCurrentED (AT91_CAST(AT91_REG *) 0x0000001C) // (HcPeriodCurrentED) Current Isochronous or Interrupt Endpoint Descriptor
#define HcControlHeadED (AT91_CAST(AT91_REG *) 0x00000020) // (HcControlHeadED) First Endpoint Descriptor of the Control list
#define HcControlCurrentED (AT91_CAST(AT91_REG *) 0x00000024) // (HcControlCurrentED) Endpoint Control and Status Register
#define HcBulkHeadED (AT91_CAST(AT91_REG *) 0x00000028) // (HcBulkHeadED) First endpoint register of the Bulk list
#define HcBulkCurrentED (AT91_CAST(AT91_REG *) 0x0000002C) // (HcBulkCurrentED) Current endpoint of the Bulk list
#define HcBulkDoneHead (AT91_CAST(AT91_REG *) 0x00000030) // (HcBulkDoneHead) Last completed transfer descriptor
#define HcFmInterval (AT91_CAST(AT91_REG *) 0x00000034) // (HcFmInterval) Bit time between 2 consecutive SOFs
#define HcFmRemaining (AT91_CAST(AT91_REG *) 0x00000038) // (HcFmRemaining) Bit time remaining in the current Frame
#define HcFmNumber (AT91_CAST(AT91_REG *) 0x0000003C) // (HcFmNumber) Frame number
#define HcPeriodicStart (AT91_CAST(AT91_REG *) 0x00000040) // (HcPeriodicStart) Periodic Start
#define HcLSThreshold (AT91_CAST(AT91_REG *) 0x00000044) // (HcLSThreshold) LS Threshold
#define HcRhDescriptorA (AT91_CAST(AT91_REG *) 0x00000048) // (HcRhDescriptorA) Root Hub characteristics A
#define HcRhDescriptorB (AT91_CAST(AT91_REG *) 0x0000004C) // (HcRhDescriptorB) Root Hub characteristics B
#define HcRhStatus (AT91_CAST(AT91_REG *) 0x00000050) // (HcRhStatus) Root Hub Status register
#define HcRhPortStatus (AT91_CAST(AT91_REG *) 0x00000054) // (HcRhPortStatus) Root Hub Port Status Register
#endif
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Image Sensor Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_ISI {
AT91_REG ISI_CR1; // Control Register 1
AT91_REG ISI_CR2; // Control Register 2
AT91_REG ISI_SR; // Status Register
AT91_REG ISI_IER; // Interrupt Enable Register
AT91_REG ISI_IDR; // Interrupt Disable Register
AT91_REG ISI_IMR; // Interrupt Mask Register
AT91_REG Reserved0[2]; //
AT91_REG ISI_PSIZE; // Preview Size Register
AT91_REG ISI_PDECF; // Preview Decimation Factor Register
AT91_REG ISI_PFBD; // Preview Frame Buffer Address Register
AT91_REG ISI_CDBA; // Codec Dma Address Register
AT91_REG ISI_Y2RSET0; // Color Space Conversion Register
AT91_REG ISI_Y2RSET1; // Color Space Conversion Register
AT91_REG ISI_R2YSET0; // Color Space Conversion Register
AT91_REG ISI_R2YSET1; // Color Space Conversion Register
AT91_REG ISI_R2YSET2; // Color Space Conversion Register
} AT91S_ISI, *AT91PS_ISI;
#else
#define ISI_CR1 (AT91_CAST(AT91_REG *) 0x00000000) // (ISI_CR1) Control Register 1
#define ISI_CR2 (AT91_CAST(AT91_REG *) 0x00000004) // (ISI_CR2) Control Register 2
#define ISI_SR (AT91_CAST(AT91_REG *) 0x00000008) // (ISI_SR) Status Register
#define ISI_IER (AT91_CAST(AT91_REG *) 0x0000000C) // (ISI_IER) Interrupt Enable Register
#define ISI_IDR (AT91_CAST(AT91_REG *) 0x00000010) // (ISI_IDR) Interrupt Disable Register
#define ISI_IMR (AT91_CAST(AT91_REG *) 0x00000014) // (ISI_IMR) Interrupt Mask Register
#define ISI_PSIZE (AT91_CAST(AT91_REG *) 0x00000020) // (ISI_PSIZE) Preview Size Register
#define ISI_PDECF (AT91_CAST(AT91_REG *) 0x00000024) // (ISI_PDECF) Preview Decimation Factor Register
#define ISI_PFBD (AT91_CAST(AT91_REG *) 0x00000028) // (ISI_PFBD) Preview Frame Buffer Address Register
#define ISI_CDBA (AT91_CAST(AT91_REG *) 0x0000002C) // (ISI_CDBA) Codec Dma Address Register
#define ISI_Y2RSET0 (AT91_CAST(AT91_REG *) 0x00000030) // (ISI_Y2RSET0) Color Space Conversion Register
#define ISI_Y2RSET1 (AT91_CAST(AT91_REG *) 0x00000034) // (ISI_Y2RSET1) Color Space Conversion Register
#define ISI_R2YSET0 (AT91_CAST(AT91_REG *) 0x00000038) // (ISI_R2YSET0) Color Space Conversion Register
#define ISI_R2YSET1 (AT91_CAST(AT91_REG *) 0x0000003C) // (ISI_R2YSET1) Color Space Conversion Register
#define ISI_R2YSET2 (AT91_CAST(AT91_REG *) 0x00000040) // (ISI_R2YSET2) Color Space Conversion Register
#endif
// -------- ISI_CR1 : (ISI Offset: 0x0) ISI Control Register 1 --------
#define AT91C_ISI_RST (0x1 << 0) // (ISI) Image sensor interface reset
#define AT91C_ISI_DISABLE (0x1 << 1) // (ISI) image sensor disable.
#define AT91C_ISI_HSYNC_POL (0x1 << 2) // (ISI) Horizontal synchronisation polarity
#define AT91C_ISI_PIXCLK_POL (0x1 << 4) // (ISI) Pixel Clock Polarity
#define AT91C_ISI_EMB_SYNC (0x1 << 6) // (ISI) Embedded synchronisation
#define AT91C_ISI_CRC_SYNC (0x1 << 7) // (ISI) CRC correction
#define AT91C_ISI_FULL (0x1 << 12) // (ISI) Full mode is allowed
#define AT91C_ISI_THMASK (0x3 << 13) // (ISI) DMA Burst Mask
#define AT91C_ISI_THMASK_4_8_16_BURST (0x0 << 13) // (ISI) 4,8 and 16 AHB burst are allowed
#define AT91C_ISI_THMASK_8_16_BURST (0x1 << 13) // (ISI) 8 and 16 AHB burst are allowed
#define AT91C_ISI_THMASK_16_BURST (0x2 << 13) // (ISI) Only 16 AHB burst are allowed
#define AT91C_ISI_CODEC_ON (0x1 << 15) // (ISI) Enable the codec path
#define AT91C_ISI_SLD (0xFF << 16) // (ISI) Start of Line Delay
#define AT91C_ISI_SFD (0xFF << 24) // (ISI) Start of frame Delay
// -------- ISI_CR2 : (ISI Offset: 0x4) ISI Control Register 2 --------
#define AT91C_ISI_IM_VSIZE (0x7FF << 0) // (ISI) Vertical size of the Image sensor [0..2047]
#define AT91C_ISI_GS_MODE (0x1 << 11) // (ISI) Grayscale Memory Mode
#define AT91C_ISI_RGB_MODE (0x3 << 12) // (ISI) RGB mode
#define AT91C_ISI_RGB_MODE_RGB_888 (0x0 << 12) // (ISI) RGB 8:8:8 24 bits
#define AT91C_ISI_RGB_MODE_RGB_565 (0x1 << 12) // (ISI) RGB 5:6:5 16 bits
#define AT91C_ISI_RGB_MODE_RGB_555 (0x2 << 12) // (ISI) RGB 5:5:5 16 bits
#define AT91C_ISI_GRAYSCALE (0x1 << 13) // (ISI) Grayscale Mode
#define AT91C_ISI_RGB_SWAP (0x1 << 14) // (ISI) RGB Swap
#define AT91C_ISI_COL_SPACE (0x1 << 15) // (ISI) Color space for the image data
#define AT91C_ISI_IM_HSIZE (0x7FF << 16) // (ISI) Horizontal size of the Image sensor [0..2047]
#define AT91C_ISI_RGB_MODE_YCC_DEF (0x0 << 28) // (ISI) Cb(i) Y(i) Cr(i) Y(i+1)
#define AT91C_ISI_RGB_MODE_YCC_MOD1 (0x1 << 28) // (ISI) Cr(i) Y(i) Cb(i) Y(i+1)
#define AT91C_ISI_RGB_MODE_YCC_MOD2 (0x2 << 28) // (ISI) Y(i) Cb(i) Y(i+1) Cr(i)
#define AT91C_ISI_RGB_MODE_YCC_MOD3 (0x3 << 28) // (ISI) Y(i) Cr(i) Y(i+1) Cb(i)
#define AT91C_ISI_RGB_CFG (0x3 << 30) // (ISI) RGB configuration
#define AT91C_ISI_RGB_CFG_RGB_DEF (0x0 << 30) // (ISI) R/G(MSB) G(LSB)/B R/G(MSB) G(LSB)/B
#define AT91C_ISI_RGB_CFG_RGB_MOD1 (0x1 << 30) // (ISI) B/G(MSB) G(LSB)/R B/G(MSB) G(LSB)/R
#define AT91C_ISI_RGB_CFG_RGB_MOD2 (0x2 << 30) // (ISI) G(LSB)/R B/G(MSB) G(LSB)/R B/G(MSB)
#define AT91C_ISI_RGB_CFG_RGB_MOD3 (0x3 << 30) // (ISI) G(LSB)/B R/G(MSB) G(LSB)/B R/G(MSB)
// -------- ISI_SR : (ISI Offset: 0x8) ISI Status Register --------
#define AT91C_ISI_SOF (0x1 << 0) // (ISI) Start of Frame
#define AT91C_ISI_DIS (0x1 << 1) // (ISI) Image Sensor Interface disable
#define AT91C_ISI_SOFTRST (0x1 << 2) // (ISI) Software Reset
#define AT91C_ISI_CRC_ERR (0x1 << 4) // (ISI) CRC synchronisation error
#define AT91C_ISI_FO_C_OVF (0x1 << 5) // (ISI) Fifo Codec Overflow
#define AT91C_ISI_FO_P_OVF (0x1 << 6) // (ISI) Fifo Preview Overflow
#define AT91C_ISI_FO_P_EMP (0x1 << 7) // (ISI) Fifo Preview Empty
#define AT91C_ISI_FO_C_EMP (0x1 << 8) // (ISI) Fifo Codec Empty
#define AT91C_ISI_FR_OVR (0x1 << 9) // (ISI) Frame rate overun
// -------- ISI_IER : (ISI Offset: 0xc) ISI Interrupt Enable Register --------
// -------- ISI_IDR : (ISI Offset: 0x10) ISI Interrupt Disable Register --------
// -------- ISI_IMR : (ISI Offset: 0x14) ISI Interrupt Mask Register --------
// -------- ISI_PSIZE : (ISI Offset: 0x20) ISI Preview Register --------
#define AT91C_ISI_PREV_VSIZE (0x3FF << 0) // (ISI) Vertical size for the preview path
#define AT91C_ISI_PREV_HSIZE (0x3FF << 16) // (ISI) Horizontal size for the preview path
// -------- ISI_Y2R_SET0 : (ISI Offset: 0x30) Color Space Conversion YCrCb to RGB Register --------
#define AT91C_ISI_Y2R_C0 (0xFF << 0) // (ISI) Color Space Conversion Matrix Coefficient C0
#define AT91C_ISI_Y2R_C1 (0xFF << 8) // (ISI) Color Space Conversion Matrix Coefficient C1
#define AT91C_ISI_Y2R_C2 (0xFF << 16) // (ISI) Color Space Conversion Matrix Coefficient C2
#define AT91C_ISI_Y2R_C3 (0xFF << 24) // (ISI) Color Space Conversion Matrix Coefficient C3
// -------- ISI_Y2R_SET1 : (ISI Offset: 0x34) ISI Color Space Conversion YCrCb to RGB set 1 Register --------
#define AT91C_ISI_Y2R_C4 (0x1FF << 0) // (ISI) Color Space Conversion Matrix Coefficient C4
#define AT91C_ISI_Y2R_YOFF (0xFF << 12) // (ISI) Color Space Conversion Luninance default offset
#define AT91C_ISI_Y2R_CROFF (0xFF << 13) // (ISI) Color Space Conversion Red Chrominance default offset
#define AT91C_ISI_Y2R_CBFF (0xFF << 14) // (ISI) Color Space Conversion Luninance default offset
// -------- ISI_R2Y_SET0 : (ISI Offset: 0x38) Color Space Conversion RGB to YCrCb set 0 register --------
#define AT91C_ISI_R2Y_C0 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C0
#define AT91C_ISI_R2Y_C1 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C1
#define AT91C_ISI_R2Y_C2 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C2
#define AT91C_ISI_R2Y_ROFF (0x1 << 4) // (ISI) Color Space Conversion Red component offset
// -------- ISI_R2Y_SET1 : (ISI Offset: 0x3c) Color Space Conversion RGB to YCrCb set 1 register --------
#define AT91C_ISI_R2Y_C3 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C3
#define AT91C_ISI_R2Y_C4 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C4
#define AT91C_ISI_R2Y_C5 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C5
#define AT91C_ISI_R2Y_GOFF (0x1 << 4) // (ISI) Color Space Conversion Green component offset
// -------- ISI_R2Y_SET2 : (ISI Offset: 0x40) Color Space Conversion RGB to YCrCb set 2 register --------
#define AT91C_ISI_R2Y_C6 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C6
#define AT91C_ISI_R2Y_C7 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C7
#define AT91C_ISI_R2Y_C8 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C8
#define AT91C_ISI_R2Y_BOFF (0x1 << 4) // (ISI) Color Space Conversion Blue component offset
// *****************************************************************************
// REGISTER ADDRESS DEFINITION FOR AT91SAM9XE512
// *****************************************************************************
// ========== Register definition for SYS peripheral ==========
#define AT91C_SYS_GPBR (AT91_CAST(AT91_REG *) 0xFFFFFFFF) // (SYS) General Purpose Register
// ========== Register definition for EBI peripheral ==========
#define AT91C_EBI_DUMMY (AT91_CAST(AT91_REG *) 0xFFFFEA00) // (EBI) Dummy register - Do not use
// ========== Register definition for HECC peripheral ==========
#define AT91C_HECC_VR (AT91_CAST(AT91_REG *) 0xFFFFE8FC) // (HECC) ECC Version register
#define AT91C_HECC_NPR (AT91_CAST(AT91_REG *) 0xFFFFE810) // (HECC) ECC Parity N register
#define AT91C_HECC_SR (AT91_CAST(AT91_REG *) 0xFFFFE808) // (HECC) ECC Status register
#define AT91C_HECC_PR (AT91_CAST(AT91_REG *) 0xFFFFE80C) // (HECC) ECC Parity register
#define AT91C_HECC_MR (AT91_CAST(AT91_REG *) 0xFFFFE804) // (HECC) ECC Page size register
#define AT91C_HECC_CR (AT91_CAST(AT91_REG *) 0xFFFFE800) // (HECC) ECC reset register
// ========== Register definition for SDRAMC peripheral ==========
#define AT91C_SDRAMC_MR (AT91_CAST(AT91_REG *) 0xFFFFEA00) // (SDRAMC) SDRAM Controller Mode Register
#define AT91C_SDRAMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFEA1C) // (SDRAMC) SDRAM Controller Interrupt Mask Register
#define AT91C_SDRAMC_LPR (AT91_CAST(AT91_REG *) 0xFFFFEA10) // (SDRAMC) SDRAM Controller Low Power Register
#define AT91C_SDRAMC_ISR (AT91_CAST(AT91_REG *) 0xFFFFEA20) // (SDRAMC) SDRAM Controller Interrupt Mask Register
#define AT91C_SDRAMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFEA18) // (SDRAMC) SDRAM Controller Interrupt Disable Register
#define AT91C_SDRAMC_CR (AT91_CAST(AT91_REG *) 0xFFFFEA08) // (SDRAMC) SDRAM Controller Configuration Register
#define AT91C_SDRAMC_TR (AT91_CAST(AT91_REG *) 0xFFFFEA04) // (SDRAMC) SDRAM Controller Refresh Timer Register
#define AT91C_SDRAMC_MDR (AT91_CAST(AT91_REG *) 0xFFFFEA24) // (SDRAMC) SDRAM Memory Device Register
#define AT91C_SDRAMC_HSR (AT91_CAST(AT91_REG *) 0xFFFFEA0C) // (SDRAMC) SDRAM Controller High Speed Register
#define AT91C_SDRAMC_IER (AT91_CAST(AT91_REG *) 0xFFFFEA14) // (SDRAMC) SDRAM Controller Interrupt Enable Register
// ========== Register definition for SMC peripheral ==========
#define AT91C_SMC_CTRL1 (AT91_CAST(AT91_REG *) 0xFFFFEC1C) // (SMC) Control Register for CS 1
#define AT91C_SMC_PULSE7 (AT91_CAST(AT91_REG *) 0xFFFFEC74) // (SMC) Pulse Register for CS 7
#define AT91C_SMC_PULSE6 (AT91_CAST(AT91_REG *) 0xFFFFEC64) // (SMC) Pulse Register for CS 6
#define AT91C_SMC_SETUP4 (AT91_CAST(AT91_REG *) 0xFFFFEC40) // (SMC) Setup Register for CS 4
#define AT91C_SMC_PULSE3 (AT91_CAST(AT91_REG *) 0xFFFFEC34) // (SMC) Pulse Register for CS 3
#define AT91C_SMC_CYCLE5 (AT91_CAST(AT91_REG *) 0xFFFFEC58) // (SMC) Cycle Register for CS 5
#define AT91C_SMC_CYCLE2 (AT91_CAST(AT91_REG *) 0xFFFFEC28) // (SMC) Cycle Register for CS 2
#define AT91C_SMC_CTRL2 (AT91_CAST(AT91_REG *) 0xFFFFEC2C) // (SMC) Control Register for CS 2
#define AT91C_SMC_CTRL0 (AT91_CAST(AT91_REG *) 0xFFFFEC0C) // (SMC) Control Register for CS 0
#define AT91C_SMC_PULSE5 (AT91_CAST(AT91_REG *) 0xFFFFEC54) // (SMC) Pulse Register for CS 5
#define AT91C_SMC_PULSE1 (AT91_CAST(AT91_REG *) 0xFFFFEC14) // (SMC) Pulse Register for CS 1
#define AT91C_SMC_PULSE0 (AT91_CAST(AT91_REG *) 0xFFFFEC04) // (SMC) Pulse Register for CS 0
#define AT91C_SMC_CYCLE7 (AT91_CAST(AT91_REG *) 0xFFFFEC78) // (SMC) Cycle Register for CS 7
#define AT91C_SMC_CTRL4 (AT91_CAST(AT91_REG *) 0xFFFFEC4C) // (SMC) Control Register for CS 4
#define AT91C_SMC_CTRL3 (AT91_CAST(AT91_REG *) 0xFFFFEC3C) // (SMC) Control Register for CS 3
#define AT91C_SMC_SETUP7 (AT91_CAST(AT91_REG *) 0xFFFFEC70) // (SMC) Setup Register for CS 7
#define AT91C_SMC_CTRL7 (AT91_CAST(AT91_REG *) 0xFFFFEC7C) // (SMC) Control Register for CS 7
#define AT91C_SMC_SETUP1 (AT91_CAST(AT91_REG *) 0xFFFFEC10) // (SMC) Setup Register for CS 1
#define AT91C_SMC_CYCLE0 (AT91_CAST(AT91_REG *) 0xFFFFEC08) // (SMC) Cycle Register for CS 0
#define AT91C_SMC_CTRL5 (AT91_CAST(AT91_REG *) 0xFFFFEC5C) // (SMC) Control Register for CS 5
#define AT91C_SMC_CYCLE1 (AT91_CAST(AT91_REG *) 0xFFFFEC18) // (SMC) Cycle Register for CS 1
#define AT91C_SMC_CTRL6 (AT91_CAST(AT91_REG *) 0xFFFFEC6C) // (SMC) Control Register for CS 6
#define AT91C_SMC_SETUP0 (AT91_CAST(AT91_REG *) 0xFFFFEC00) // (SMC) Setup Register for CS 0
#define AT91C_SMC_PULSE4 (AT91_CAST(AT91_REG *) 0xFFFFEC44) // (SMC) Pulse Register for CS 4
#define AT91C_SMC_SETUP5 (AT91_CAST(AT91_REG *) 0xFFFFEC50) // (SMC) Setup Register for CS 5
#define AT91C_SMC_SETUP2 (AT91_CAST(AT91_REG *) 0xFFFFEC20) // (SMC) Setup Register for CS 2
#define AT91C_SMC_CYCLE3 (AT91_CAST(AT91_REG *) 0xFFFFEC38) // (SMC) Cycle Register for CS 3
#define AT91C_SMC_CYCLE6 (AT91_CAST(AT91_REG *) 0xFFFFEC68) // (SMC) Cycle Register for CS 6
#define AT91C_SMC_SETUP6 (AT91_CAST(AT91_REG *) 0xFFFFEC60) // (SMC) Setup Register for CS 6
#define AT91C_SMC_CYCLE4 (AT91_CAST(AT91_REG *) 0xFFFFEC48) // (SMC) Cycle Register for CS 4
#define AT91C_SMC_PULSE2 (AT91_CAST(AT91_REG *) 0xFFFFEC24) // (SMC) Pulse Register for CS 2
#define AT91C_SMC_SETUP3 (AT91_CAST(AT91_REG *) 0xFFFFEC30) // (SMC) Setup Register for CS 3
// ========== Register definition for MATRIX peripheral ==========
#define AT91C_MATRIX_MCFG0 (AT91_CAST(AT91_REG *) 0xFFFFEE00) // (MATRIX) Master Configuration Register 0 (ram96k)
#define AT91C_MATRIX_MCFG7 (AT91_CAST(AT91_REG *) 0xFFFFEE1C) // (MATRIX) Master Configuration Register 7 (teak_prog)
#define AT91C_MATRIX_SCFG1 (AT91_CAST(AT91_REG *) 0xFFFFEE44) // (MATRIX) Slave Configuration Register 1 (rom)
#define AT91C_MATRIX_MCFG4 (AT91_CAST(AT91_REG *) 0xFFFFEE10) // (MATRIX) Master Configuration Register 4 (bridge)
#define AT91C_MATRIX_VERSION (AT91_CAST(AT91_REG *) 0xFFFFEFFC) // (MATRIX) Version Register
#define AT91C_MATRIX_MCFG2 (AT91_CAST(AT91_REG *) 0xFFFFEE08) // (MATRIX) Master Configuration Register 2 (hperiphs)
#define AT91C_MATRIX_PRBS4 (AT91_CAST(AT91_REG *) 0xFFFFEEA4) // (MATRIX) PRBS4 : ebi
#define AT91C_MATRIX_PRBS0 (AT91_CAST(AT91_REG *) 0xFFFFEE84) // (MATRIX) PRBS0 (ram0)
#define AT91C_MATRIX_SCFG3 (AT91_CAST(AT91_REG *) 0xFFFFEE4C) // (MATRIX) Slave Configuration Register 3 (ebi)
#define AT91C_MATRIX_MCFG6 (AT91_CAST(AT91_REG *) 0xFFFFEE18) // (MATRIX) Master Configuration Register 6 (ram16k)
#define AT91C_MATRIX_EBI (AT91_CAST(AT91_REG *) 0xFFFFEF1C) // (MATRIX) Slave 3 (ebi) Special Function Register
#define AT91C_MATRIX_SCFG0 (AT91_CAST(AT91_REG *) 0xFFFFEE40) // (MATRIX) Slave Configuration Register 0 (ram96k)
#define AT91C_MATRIX_PRBS3 (AT91_CAST(AT91_REG *) 0xFFFFEE9C) // (MATRIX) PRBS3 : usb_dev_hs
#define AT91C_MATRIX_PRAS3 (AT91_CAST(AT91_REG *) 0xFFFFEE98) // (MATRIX) PRAS3 : usb_dev_hs
#define AT91C_MATRIX_PRAS0 (AT91_CAST(AT91_REG *) 0xFFFFEE80) // (MATRIX) PRAS0 (ram0)
#define AT91C_MATRIX_MCFG3 (AT91_CAST(AT91_REG *) 0xFFFFEE0C) // (MATRIX) Master Configuration Register 3 (ebi)
#define AT91C_MATRIX_PRAS1 (AT91_CAST(AT91_REG *) 0xFFFFEE88) // (MATRIX) PRAS1 (ram1)
#define AT91C_MATRIX_PRAS2 (AT91_CAST(AT91_REG *) 0xFFFFEE90) // (MATRIX) PRAS2 (ram2)
#define AT91C_MATRIX_SCFG2 (AT91_CAST(AT91_REG *) 0xFFFFEE48) // (MATRIX) Slave Configuration Register 2 (hperiphs)
#define AT91C_MATRIX_MCFG5 (AT91_CAST(AT91_REG *) 0xFFFFEE14) // (MATRIX) Master Configuration Register 5 (mailbox)
#define AT91C_MATRIX_MCFG1 (AT91_CAST(AT91_REG *) 0xFFFFEE04) // (MATRIX) Master Configuration Register 1 (rom)
#define AT91C_MATRIX_PRAS4 (AT91_CAST(AT91_REG *) 0xFFFFEEA0) // (MATRIX) PRAS4 : ebi
#define AT91C_MATRIX_MRCR (AT91_CAST(AT91_REG *) 0xFFFFEF00) // (MATRIX) Master Remp Control Register
#define AT91C_MATRIX_PRBS2 (AT91_CAST(AT91_REG *) 0xFFFFEE94) // (MATRIX) PRBS2 (ram2)
#define AT91C_MATRIX_SCFG4 (AT91_CAST(AT91_REG *) 0xFFFFEE50) // (MATRIX) Slave Configuration Register 4 (bridge)
#define AT91C_MATRIX_TEAKCFG (AT91_CAST(AT91_REG *) 0xFFFFEF2C) // (MATRIX) Slave 7 (teak_prog) Special Function Register
#define AT91C_MATRIX_PRBS1 (AT91_CAST(AT91_REG *) 0xFFFFEE8C) // (MATRIX) PRBS1 (ram1)
// ========== Register definition for CCFG peripheral ==========
#define AT91C_CCFG_MATRIXVERSION (AT91_CAST(AT91_REG *) 0xFFFFEFFC) // (CCFG) Version Register
#define AT91C_CCFG_EBICSA (AT91_CAST(AT91_REG *) 0xFFFFEF1C) // (CCFG) EBI Chip Select Assignement Register
// ========== Register definition for PDC_DBGU peripheral ==========
#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
// ========== Register definition for DBGU peripheral ==========
#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
// ========== Register definition for AIC peripheral ==========
#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
// ========== Register definition for PIOA peripheral ==========
#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
// ========== Register definition for PIOB peripheral ==========
#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register
#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register
#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register
#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register
#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register
#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register
#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register
#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register
#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register
#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register
#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register
#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register
#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register
#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register
#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register
#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register
#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr
#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register
#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register
#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register
#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register
#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register
#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register
#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register
#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register
#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register
#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register
#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register
#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register
// ========== Register definition for PIOC peripheral ==========
#define AT91C_PIOC_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF8A4) // (PIOC) Output Write Disable Register
#define AT91C_PIOC_SODR (AT91_CAST(AT91_REG *) 0xFFFFF830) // (PIOC) Set Output Data Register
#define AT91C_PIOC_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF864) // (PIOC) Pull-up Enable Register
#define AT91C_PIOC_CODR (AT91_CAST(AT91_REG *) 0xFFFFF834) // (PIOC) Clear Output Data Register
#define AT91C_PIOC_PSR (AT91_CAST(AT91_REG *) 0xFFFFF808) // (PIOC) PIO Status Register
#define AT91C_PIOC_PDR (AT91_CAST(AT91_REG *) 0xFFFFF804) // (PIOC) PIO Disable Register
#define AT91C_PIOC_ODR (AT91_CAST(AT91_REG *) 0xFFFFF814) // (PIOC) Output Disable Registerr
#define AT91C_PIOC_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF868) // (PIOC) Pull-up Status Register
#define AT91C_PIOC_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF878) // (PIOC) AB Select Status Register
#define AT91C_PIOC_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF828) // (PIOC) Input Filter Status Register
#define AT91C_PIOC_OER (AT91_CAST(AT91_REG *) 0xFFFFF810) // (PIOC) Output Enable Register
#define AT91C_PIOC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF848) // (PIOC) Interrupt Mask Register
#define AT91C_PIOC_ASR (AT91_CAST(AT91_REG *) 0xFFFFF870) // (PIOC) Select A Register
#define AT91C_PIOC_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF854) // (PIOC) Multi-driver Disable Register
#define AT91C_PIOC_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF8A8) // (PIOC) Output Write Status Register
#define AT91C_PIOC_PER (AT91_CAST(AT91_REG *) 0xFFFFF800) // (PIOC) PIO Enable Register
#define AT91C_PIOC_IDR (AT91_CAST(AT91_REG *) 0xFFFFF844) // (PIOC) Interrupt Disable Register
#define AT91C_PIOC_MDER (AT91_CAST(AT91_REG *) 0xFFFFF850) // (PIOC) Multi-driver Enable Register
#define AT91C_PIOC_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF83C) // (PIOC) Pin Data Status Register
#define AT91C_PIOC_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF858) // (PIOC) Multi-driver Status Register
#define AT91C_PIOC_OWER (AT91_CAST(AT91_REG *) 0xFFFFF8A0) // (PIOC) Output Write Enable Register
#define AT91C_PIOC_BSR (AT91_CAST(AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register
#define AT91C_PIOC_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF860) // (PIOC) Pull-up Disable Register
#define AT91C_PIOC_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF824) // (PIOC) Input Filter Disable Register
#define AT91C_PIOC_IER (AT91_CAST(AT91_REG *) 0xFFFFF840) // (PIOC) Interrupt Enable Register
#define AT91C_PIOC_OSR (AT91_CAST(AT91_REG *) 0xFFFFF818) // (PIOC) Output Status Register
#define AT91C_PIOC_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF838) // (PIOC) Output Data Status Register
#define AT91C_PIOC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF84C) // (PIOC) Interrupt Status Register
#define AT91C_PIOC_IFER (AT91_CAST(AT91_REG *) 0xFFFFF820) // (PIOC) Input Filter Enable Register
// ========== Register definition for EFC peripheral ==========
#define AT91C_EFC_FVR (AT91_CAST(AT91_REG *) 0xFFFFFA10) // (EFC) EFC Flash Version Register
#define AT91C_EFC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFA04) // (EFC) EFC Flash Command Register
#define AT91C_EFC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFA00) // (EFC) EFC Flash Mode Register
#define AT91C_EFC_FRR (AT91_CAST(AT91_REG *) 0xFFFFFA0C) // (EFC) EFC Flash Result Register
#define AT91C_EFC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFA08) // (EFC) EFC Flash Status Register
// ========== Register definition for CKGR peripheral ==========
#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
#define AT91C_CKGR_PLLBR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL B Register
#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
#define AT91C_CKGR_PLLAR (AT91_CAST(AT91_REG *) 0xFFFFFC28) // (CKGR) PLL A Register
// ========== Register definition for PMC peripheral ==========
#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
#define AT91C_PMC_PLLAR (AT91_CAST(AT91_REG *) 0xFFFFFC28) // (PMC) PLL A Register
#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
#define AT91C_PMC_PLLBR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL B Register
#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
// ========== Register definition for RSTC peripheral ==========
#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
// ========== Register definition for SHDWC peripheral ==========
#define AT91C_SHDWC_SHSR (AT91_CAST(AT91_REG *) 0xFFFFFD18) // (SHDWC) Shut Down Status Register
#define AT91C_SHDWC_SHMR (AT91_CAST(AT91_REG *) 0xFFFFFD14) // (SHDWC) Shut Down Mode Register
#define AT91C_SHDWC_SHCR (AT91_CAST(AT91_REG *) 0xFFFFFD10) // (SHDWC) Shut Down Control Register
// ========== Register definition for RTTC peripheral ==========
#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
// ========== Register definition for PITC peripheral ==========
#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
// ========== Register definition for WDTC peripheral ==========
#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
// ========== Register definition for TC0 peripheral ==========
#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register
#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C
#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B
#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A
#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
// ========== Register definition for TC1 peripheral ==========
#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B
#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register
#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A
#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C
#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
// ========== Register definition for TC2 peripheral ==========
#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A
#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B
#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C
#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
// ========== Register definition for TC3 peripheral ==========
#define AT91C_TC3_IER (AT91_CAST(AT91_REG *) 0xFFFDC024) // (TC3) Interrupt Enable Register
#define AT91C_TC3_RB (AT91_CAST(AT91_REG *) 0xFFFDC018) // (TC3) Register B
#define AT91C_TC3_CMR (AT91_CAST(AT91_REG *) 0xFFFDC004) // (TC3) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC3_RC (AT91_CAST(AT91_REG *) 0xFFFDC01C) // (TC3) Register C
#define AT91C_TC3_CCR (AT91_CAST(AT91_REG *) 0xFFFDC000) // (TC3) Channel Control Register
#define AT91C_TC3_SR (AT91_CAST(AT91_REG *) 0xFFFDC020) // (TC3) Status Register
#define AT91C_TC3_CV (AT91_CAST(AT91_REG *) 0xFFFDC010) // (TC3) Counter Value
#define AT91C_TC3_RA (AT91_CAST(AT91_REG *) 0xFFFDC014) // (TC3) Register A
#define AT91C_TC3_IDR (AT91_CAST(AT91_REG *) 0xFFFDC028) // (TC3) Interrupt Disable Register
#define AT91C_TC3_IMR (AT91_CAST(AT91_REG *) 0xFFFDC02C) // (TC3) Interrupt Mask Register
// ========== Register definition for TC4 peripheral ==========
#define AT91C_TC4_CMR (AT91_CAST(AT91_REG *) 0xFFFDC044) // (TC4) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC4_RC (AT91_CAST(AT91_REG *) 0xFFFDC05C) // (TC4) Register C
#define AT91C_TC4_SR (AT91_CAST(AT91_REG *) 0xFFFDC060) // (TC4) Status Register
#define AT91C_TC4_RB (AT91_CAST(AT91_REG *) 0xFFFDC058) // (TC4) Register B
#define AT91C_TC4_IER (AT91_CAST(AT91_REG *) 0xFFFDC064) // (TC4) Interrupt Enable Register
#define AT91C_TC4_CV (AT91_CAST(AT91_REG *) 0xFFFDC050) // (TC4) Counter Value
#define AT91C_TC4_RA (AT91_CAST(AT91_REG *) 0xFFFDC054) // (TC4) Register A
#define AT91C_TC4_IDR (AT91_CAST(AT91_REG *) 0xFFFDC068) // (TC4) Interrupt Disable Register
#define AT91C_TC4_IMR (AT91_CAST(AT91_REG *) 0xFFFDC06C) // (TC4) Interrupt Mask Register
#define AT91C_TC4_CCR (AT91_CAST(AT91_REG *) 0xFFFDC040) // (TC4) Channel Control Register
// ========== Register definition for TC5 peripheral ==========
#define AT91C_TC5_RB (AT91_CAST(AT91_REG *) 0xFFFDC098) // (TC5) Register B
#define AT91C_TC5_RA (AT91_CAST(AT91_REG *) 0xFFFDC094) // (TC5) Register A
#define AT91C_TC5_CV (AT91_CAST(AT91_REG *) 0xFFFDC090) // (TC5) Counter Value
#define AT91C_TC5_CCR (AT91_CAST(AT91_REG *) 0xFFFDC080) // (TC5) Channel Control Register
#define AT91C_TC5_SR (AT91_CAST(AT91_REG *) 0xFFFDC0A0) // (TC5) Status Register
#define AT91C_TC5_IER (AT91_CAST(AT91_REG *) 0xFFFDC0A4) // (TC5) Interrupt Enable Register
#define AT91C_TC5_IDR (AT91_CAST(AT91_REG *) 0xFFFDC0A8) // (TC5) Interrupt Disable Register
#define AT91C_TC5_RC (AT91_CAST(AT91_REG *) 0xFFFDC09C) // (TC5) Register C
#define AT91C_TC5_IMR (AT91_CAST(AT91_REG *) 0xFFFDC0AC) // (TC5) Interrupt Mask Register
#define AT91C_TC5_CMR (AT91_CAST(AT91_REG *) 0xFFFDC084) // (TC5) Channel Mode Register (Capture Mode / Waveform Mode)
// ========== Register definition for TCB0 peripheral ==========
#define AT91C_TCB0_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB0) TC Block Mode Register
#define AT91C_TCB0_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB0) TC Block Control Register
// ========== Register definition for TCB1 peripheral ==========
#define AT91C_TCB1_BCR (AT91_CAST(AT91_REG *) 0xFFFDC0C0) // (TCB1) TC Block Control Register
#define AT91C_TCB1_BMR (AT91_CAST(AT91_REG *) 0xFFFDC0C4) // (TCB1) TC Block Mode Register
// ========== Register definition for PDC_MCI peripheral ==========
#define AT91C_MCI_RNCR (AT91_CAST(AT91_REG *) 0xFFFA8114) // (PDC_MCI) Receive Next Counter Register
#define AT91C_MCI_TCR (AT91_CAST(AT91_REG *) 0xFFFA810C) // (PDC_MCI) Transmit Counter Register
#define AT91C_MCI_RCR (AT91_CAST(AT91_REG *) 0xFFFA8104) // (PDC_MCI) Receive Counter Register
#define AT91C_MCI_TNPR (AT91_CAST(AT91_REG *) 0xFFFA8118) // (PDC_MCI) Transmit Next Pointer Register
#define AT91C_MCI_RNPR (AT91_CAST(AT91_REG *) 0xFFFA8110) // (PDC_MCI) Receive Next Pointer Register
#define AT91C_MCI_RPR (AT91_CAST(AT91_REG *) 0xFFFA8100) // (PDC_MCI) Receive Pointer Register
#define AT91C_MCI_TNCR (AT91_CAST(AT91_REG *) 0xFFFA811C) // (PDC_MCI) Transmit Next Counter Register
#define AT91C_MCI_TPR (AT91_CAST(AT91_REG *) 0xFFFA8108) // (PDC_MCI) Transmit Pointer Register
#define AT91C_MCI_PTSR (AT91_CAST(AT91_REG *) 0xFFFA8124) // (PDC_MCI) PDC Transfer Status Register
#define AT91C_MCI_PTCR (AT91_CAST(AT91_REG *) 0xFFFA8120) // (PDC_MCI) PDC Transfer Control Register
// ========== Register definition for MCI peripheral ==========
#define AT91C_MCI_RDR (AT91_CAST(AT91_REG *) 0xFFFA8030) // (MCI) MCI Receive Data Register
#define AT91C_MCI_CMDR (AT91_CAST(AT91_REG *) 0xFFFA8014) // (MCI) MCI Command Register
#define AT91C_MCI_VR (AT91_CAST(AT91_REG *) 0xFFFA80FC) // (MCI) MCI Version Register
#define AT91C_MCI_IDR (AT91_CAST(AT91_REG *) 0xFFFA8048) // (MCI) MCI Interrupt Disable Register
#define AT91C_MCI_DTOR (AT91_CAST(AT91_REG *) 0xFFFA8008) // (MCI) MCI Data Timeout Register
#define AT91C_MCI_TDR (AT91_CAST(AT91_REG *) 0xFFFA8034) // (MCI) MCI Transmit Data Register
#define AT91C_MCI_IER (AT91_CAST(AT91_REG *) 0xFFFA8044) // (MCI) MCI Interrupt Enable Register
#define AT91C_MCI_BLKR (AT91_CAST(AT91_REG *) 0xFFFA8018) // (MCI) MCI Block Register
#define AT91C_MCI_MR (AT91_CAST(AT91_REG *) 0xFFFA8004) // (MCI) MCI Mode Register
#define AT91C_MCI_IMR (AT91_CAST(AT91_REG *) 0xFFFA804C) // (MCI) MCI Interrupt Mask Register
#define AT91C_MCI_CR (AT91_CAST(AT91_REG *) 0xFFFA8000) // (MCI) MCI Control Register
#define AT91C_MCI_ARGR (AT91_CAST(AT91_REG *) 0xFFFA8010) // (MCI) MCI Argument Register
#define AT91C_MCI_SDCR (AT91_CAST(AT91_REG *) 0xFFFA800C) // (MCI) MCI SD Card Register
#define AT91C_MCI_SR (AT91_CAST(AT91_REG *) 0xFFFA8040) // (MCI) MCI Status Register
#define AT91C_MCI_RSPR (AT91_CAST(AT91_REG *) 0xFFFA8020) // (MCI) MCI Response Register
// ========== Register definition for PDC_TWI0 peripheral ==========
#define AT91C_TWI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFAC124) // (PDC_TWI0) PDC Transfer Status Register
#define AT91C_TWI0_RPR (AT91_CAST(AT91_REG *) 0xFFFAC100) // (PDC_TWI0) Receive Pointer Register
#define AT91C_TWI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFAC114) // (PDC_TWI0) Receive Next Counter Register
#define AT91C_TWI0_RCR (AT91_CAST(AT91_REG *) 0xFFFAC104) // (PDC_TWI0) Receive Counter Register
#define AT91C_TWI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFAC120) // (PDC_TWI0) PDC Transfer Control Register
#define AT91C_TWI0_TPR (AT91_CAST(AT91_REG *) 0xFFFAC108) // (PDC_TWI0) Transmit Pointer Register
#define AT91C_TWI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFAC110) // (PDC_TWI0) Receive Next Pointer Register
#define AT91C_TWI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFAC118) // (PDC_TWI0) Transmit Next Pointer Register
#define AT91C_TWI0_TCR (AT91_CAST(AT91_REG *) 0xFFFAC10C) // (PDC_TWI0) Transmit Counter Register
#define AT91C_TWI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFAC11C) // (PDC_TWI0) Transmit Next Counter Register
// ========== Register definition for TWI0 peripheral ==========
#define AT91C_TWI0_THR (AT91_CAST(AT91_REG *) 0xFFFAC034) // (TWI0) Transmit Holding Register
#define AT91C_TWI0_IDR (AT91_CAST(AT91_REG *) 0xFFFAC028) // (TWI0) Interrupt Disable Register
#define AT91C_TWI0_SMR (AT91_CAST(AT91_REG *) 0xFFFAC008) // (TWI0) Slave Mode Register
#define AT91C_TWI0_CWGR (AT91_CAST(AT91_REG *) 0xFFFAC010) // (TWI0) Clock Waveform Generator Register
#define AT91C_TWI0_IADR (AT91_CAST(AT91_REG *) 0xFFFAC00C) // (TWI0) Internal Address Register
#define AT91C_TWI0_RHR (AT91_CAST(AT91_REG *) 0xFFFAC030) // (TWI0) Receive Holding Register
#define AT91C_TWI0_IER (AT91_CAST(AT91_REG *) 0xFFFAC024) // (TWI0) Interrupt Enable Register
#define AT91C_TWI0_MMR (AT91_CAST(AT91_REG *) 0xFFFAC004) // (TWI0) Master Mode Register
#define AT91C_TWI0_SR (AT91_CAST(AT91_REG *) 0xFFFAC020) // (TWI0) Status Register
#define AT91C_TWI0_IMR (AT91_CAST(AT91_REG *) 0xFFFAC02C) // (TWI0) Interrupt Mask Register
#define AT91C_TWI0_CR (AT91_CAST(AT91_REG *) 0xFFFAC000) // (TWI0) Control Register
// ========== Register definition for PDC_TWI1 peripheral ==========
#define AT91C_TWI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_TWI1) PDC Transfer Status Register
#define AT91C_TWI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_TWI1) PDC Transfer Control Register
#define AT91C_TWI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_TWI1) Transmit Next Pointer Register
#define AT91C_TWI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_TWI1) Transmit Next Counter Register
#define AT91C_TWI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_TWI1) Receive Next Pointer Register
#define AT91C_TWI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_TWI1) Receive Next Counter Register
#define AT91C_TWI1_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_TWI1) Receive Pointer Register
#define AT91C_TWI1_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_TWI1) Transmit Counter Register
#define AT91C_TWI1_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_TWI1) Transmit Pointer Register
#define AT91C_TWI1_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_TWI1) Receive Counter Register
// ========== Register definition for TWI1 peripheral ==========
#define AT91C_TWI1_RHR (AT91_CAST(AT91_REG *) 0xFFFD8030) // (TWI1) Receive Holding Register
#define AT91C_TWI1_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (TWI1) Interrupt Enable Register
#define AT91C_TWI1_CWGR (AT91_CAST(AT91_REG *) 0xFFFD8010) // (TWI1) Clock Waveform Generator Register
#define AT91C_TWI1_MMR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (TWI1) Master Mode Register
#define AT91C_TWI1_IADR (AT91_CAST(AT91_REG *) 0xFFFD800C) // (TWI1) Internal Address Register
#define AT91C_TWI1_THR (AT91_CAST(AT91_REG *) 0xFFFD8034) // (TWI1) Transmit Holding Register
#define AT91C_TWI1_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (TWI1) Interrupt Mask Register
#define AT91C_TWI1_SR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (TWI1) Status Register
#define AT91C_TWI1_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (TWI1) Interrupt Disable Register
#define AT91C_TWI1_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (TWI1) Control Register
#define AT91C_TWI1_SMR (AT91_CAST(AT91_REG *) 0xFFFD8008) // (TWI1) Slave Mode Register
// ========== Register definition for PDC_US0 peripheral ==========
#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFB010C) // (PDC_US0) Transmit Counter Register
#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFB0120) // (PDC_US0) PDC Transfer Control Register
#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFB0114) // (PDC_US0) Receive Next Counter Register
#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFB0124) // (PDC_US0) PDC Transfer Status Register
#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFB011C) // (PDC_US0) Transmit Next Counter Register
#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFB0110) // (PDC_US0) Receive Next Pointer Register
#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFB0104) // (PDC_US0) Receive Counter Register
#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFB0108) // (PDC_US0) Transmit Pointer Register
#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFB0118) // (PDC_US0) Transmit Next Pointer Register
#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFB0100) // (PDC_US0) Receive Pointer Register
// ========== Register definition for US0 peripheral ==========
#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (US0) Receiver Holding Register
#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFB0044) // (US0) Nb Errors Register
#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFB0008) // (US0) Interrupt Enable Register
#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFB0000) // (US0) Control Register
#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (US0) Transmitter Holding Register
#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (US0) Channel Status Register
#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (US0) Baud Rate Generator Register
#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFB0024) // (US0) Receiver Time-out Register
#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFB0028) // (US0) Transmitter Time-guard Register
#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFB000C) // (US0) Interrupt Disable Register
#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFB0004) // (US0) Mode Register
#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFB004C) // (US0) IRDA_FILTER Register
#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFB0040) // (US0) FI_DI_Ratio Register
#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFB0010) // (US0) Interrupt Mask Register
// ========== Register definition for PDC_US1 peripheral ==========
#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFB4120) // (PDC_US1) PDC Transfer Control Register
#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFB4104) // (PDC_US1) Receive Counter Register
#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFB4100) // (PDC_US1) Receive Pointer Register
#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFB4124) // (PDC_US1) PDC Transfer Status Register
#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFB4108) // (PDC_US1) Transmit Pointer Register
#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFB410C) // (PDC_US1) Transmit Counter Register
#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFB4110) // (PDC_US1) Receive Next Pointer Register
#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFB411C) // (PDC_US1) Transmit Next Counter Register
#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFB4114) // (PDC_US1) Receive Next Counter Register
#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFB4118) // (PDC_US1) Transmit Next Pointer Register
// ========== Register definition for US1 peripheral ==========
#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFB401C) // (US1) Transmitter Holding Register
#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFB4028) // (US1) Transmitter Time-guard Register
#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFB4020) // (US1) Baud Rate Generator Register
#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFB400C) // (US1) Interrupt Disable Register
#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFB4004) // (US1) Mode Register
#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFB4024) // (US1) Receiver Time-out Register
#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFB4000) // (US1) Control Register
#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFB4010) // (US1) Interrupt Mask Register
#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFB4040) // (US1) FI_DI_Ratio Register
#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFB4018) // (US1) Receiver Holding Register
#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFB4008) // (US1) Interrupt Enable Register
#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFB4014) // (US1) Channel Status Register
#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFB404C) // (US1) IRDA_FILTER Register
#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFB4044) // (US1) Nb Errors Register
// ========== Register definition for PDC_US2 peripheral ==========
#define AT91C_US2_TNCR (AT91_CAST(AT91_REG *) 0xFFFB811C) // (PDC_US2) Transmit Next Counter Register
#define AT91C_US2_RNCR (AT91_CAST(AT91_REG *) 0xFFFB8114) // (PDC_US2) Receive Next Counter Register
#define AT91C_US2_TNPR (AT91_CAST(AT91_REG *) 0xFFFB8118) // (PDC_US2) Transmit Next Pointer Register
#define AT91C_US2_PTCR (AT91_CAST(AT91_REG *) 0xFFFB8120) // (PDC_US2) PDC Transfer Control Register
#define AT91C_US2_TCR (AT91_CAST(AT91_REG *) 0xFFFB810C) // (PDC_US2) Transmit Counter Register
#define AT91C_US2_RPR (AT91_CAST(AT91_REG *) 0xFFFB8100) // (PDC_US2) Receive Pointer Register
#define AT91C_US2_TPR (AT91_CAST(AT91_REG *) 0xFFFB8108) // (PDC_US2) Transmit Pointer Register
#define AT91C_US2_RCR (AT91_CAST(AT91_REG *) 0xFFFB8104) // (PDC_US2) Receive Counter Register
#define AT91C_US2_PTSR (AT91_CAST(AT91_REG *) 0xFFFB8124) // (PDC_US2) PDC Transfer Status Register
#define AT91C_US2_RNPR (AT91_CAST(AT91_REG *) 0xFFFB8110) // (PDC_US2) Receive Next Pointer Register
// ========== Register definition for US2 peripheral ==========
#define AT91C_US2_RTOR (AT91_CAST(AT91_REG *) 0xFFFB8024) // (US2) Receiver Time-out Register
#define AT91C_US2_CSR (AT91_CAST(AT91_REG *) 0xFFFB8014) // (US2) Channel Status Register
#define AT91C_US2_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (US2) Control Register
#define AT91C_US2_BRGR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (US2) Baud Rate Generator Register
#define AT91C_US2_NER (AT91_CAST(AT91_REG *) 0xFFFB8044) // (US2) Nb Errors Register
#define AT91C_US2_FIDI (AT91_CAST(AT91_REG *) 0xFFFB8040) // (US2) FI_DI_Ratio Register
#define AT91C_US2_TTGR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (US2) Transmitter Time-guard Register
#define AT91C_US2_RHR (AT91_CAST(AT91_REG *) 0xFFFB8018) // (US2) Receiver Holding Register
#define AT91C_US2_IDR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (US2) Interrupt Disable Register
#define AT91C_US2_THR (AT91_CAST(AT91_REG *) 0xFFFB801C) // (US2) Transmitter Holding Register
#define AT91C_US2_MR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (US2) Mode Register
#define AT91C_US2_IMR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (US2) Interrupt Mask Register
#define AT91C_US2_IF (AT91_CAST(AT91_REG *) 0xFFFB804C) // (US2) IRDA_FILTER Register
#define AT91C_US2_IER (AT91_CAST(AT91_REG *) 0xFFFB8008) // (US2) Interrupt Enable Register
// ========== Register definition for PDC_US3 peripheral ==========
#define AT91C_US3_RNPR (AT91_CAST(AT91_REG *) 0xFFFD0110) // (PDC_US3) Receive Next Pointer Register
#define AT91C_US3_RNCR (AT91_CAST(AT91_REG *) 0xFFFD0114) // (PDC_US3) Receive Next Counter Register
#define AT91C_US3_PTSR (AT91_CAST(AT91_REG *) 0xFFFD0124) // (PDC_US3) PDC Transfer Status Register
#define AT91C_US3_PTCR (AT91_CAST(AT91_REG *) 0xFFFD0120) // (PDC_US3) PDC Transfer Control Register
#define AT91C_US3_TCR (AT91_CAST(AT91_REG *) 0xFFFD010C) // (PDC_US3) Transmit Counter Register
#define AT91C_US3_TNPR (AT91_CAST(AT91_REG *) 0xFFFD0118) // (PDC_US3) Transmit Next Pointer Register
#define AT91C_US3_RCR (AT91_CAST(AT91_REG *) 0xFFFD0104) // (PDC_US3) Receive Counter Register
#define AT91C_US3_TPR (AT91_CAST(AT91_REG *) 0xFFFD0108) // (PDC_US3) Transmit Pointer Register
#define AT91C_US3_TNCR (AT91_CAST(AT91_REG *) 0xFFFD011C) // (PDC_US3) Transmit Next Counter Register
#define AT91C_US3_RPR (AT91_CAST(AT91_REG *) 0xFFFD0100) // (PDC_US3) Receive Pointer Register
// ========== Register definition for US3 peripheral ==========
#define AT91C_US3_NER (AT91_CAST(AT91_REG *) 0xFFFD0044) // (US3) Nb Errors Register
#define AT91C_US3_RTOR (AT91_CAST(AT91_REG *) 0xFFFD0024) // (US3) Receiver Time-out Register
#define AT91C_US3_IDR (AT91_CAST(AT91_REG *) 0xFFFD000C) // (US3) Interrupt Disable Register
#define AT91C_US3_MR (AT91_CAST(AT91_REG *) 0xFFFD0004) // (US3) Mode Register
#define AT91C_US3_FIDI (AT91_CAST(AT91_REG *) 0xFFFD0040) // (US3) FI_DI_Ratio Register
#define AT91C_US3_BRGR (AT91_CAST(AT91_REG *) 0xFFFD0020) // (US3) Baud Rate Generator Register
#define AT91C_US3_THR (AT91_CAST(AT91_REG *) 0xFFFD001C) // (US3) Transmitter Holding Register
#define AT91C_US3_CR (AT91_CAST(AT91_REG *) 0xFFFD0000) // (US3) Control Register
#define AT91C_US3_IF (AT91_CAST(AT91_REG *) 0xFFFD004C) // (US3) IRDA_FILTER Register
#define AT91C_US3_IER (AT91_CAST(AT91_REG *) 0xFFFD0008) // (US3) Interrupt Enable Register
#define AT91C_US3_TTGR (AT91_CAST(AT91_REG *) 0xFFFD0028) // (US3) Transmitter Time-guard Register
#define AT91C_US3_RHR (AT91_CAST(AT91_REG *) 0xFFFD0018) // (US3) Receiver Holding Register
#define AT91C_US3_IMR (AT91_CAST(AT91_REG *) 0xFFFD0010) // (US3) Interrupt Mask Register
#define AT91C_US3_CSR (AT91_CAST(AT91_REG *) 0xFFFD0014) // (US3) Channel Status Register
// ========== Register definition for PDC_US4 peripheral ==========
#define AT91C_US4_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_US4) Transmit Next Counter Register
#define AT91C_US4_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_US4) Receive Pointer Register
#define AT91C_US4_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_US4) Receive Next Counter Register
#define AT91C_US4_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_US4) Transmit Pointer Register
#define AT91C_US4_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_US4) PDC Transfer Control Register
#define AT91C_US4_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_US4) Transmit Counter Register
#define AT91C_US4_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_US4) Receive Counter Register
#define AT91C_US4_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_US4) Receive Next Pointer Register
#define AT91C_US4_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_US4) Transmit Next Pointer Register
#define AT91C_US4_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_US4) PDC Transfer Status Register
// ========== Register definition for US4 peripheral ==========
#define AT91C_US4_BRGR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (US4) Baud Rate Generator Register
#define AT91C_US4_THR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (US4) Transmitter Holding Register
#define AT91C_US4_RTOR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (US4) Receiver Time-out Register
#define AT91C_US4_IMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (US4) Interrupt Mask Register
#define AT91C_US4_NER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (US4) Nb Errors Register
#define AT91C_US4_TTGR (AT91_CAST(AT91_REG *) 0xFFFD4028) // (US4) Transmitter Time-guard Register
#define AT91C_US4_FIDI (AT91_CAST(AT91_REG *) 0xFFFD4040) // (US4) FI_DI_Ratio Register
#define AT91C_US4_MR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (US4) Mode Register
#define AT91C_US4_IER (AT91_CAST(AT91_REG *) 0xFFFD4008) // (US4) Interrupt Enable Register
#define AT91C_US4_RHR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (US4) Receiver Holding Register
#define AT91C_US4_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (US4) Control Register
#define AT91C_US4_IF (AT91_CAST(AT91_REG *) 0xFFFD404C) // (US4) IRDA_FILTER Register
#define AT91C_US4_IDR (AT91_CAST(AT91_REG *) 0xFFFD400C) // (US4) Interrupt Disable Register
#define AT91C_US4_CSR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (US4) Channel Status Register
// ========== Register definition for PDC_SSC0 peripheral ==========
#define AT91C_SSC0_TNPR (AT91_CAST(AT91_REG *) 0xFFFBC118) // (PDC_SSC0) Transmit Next Pointer Register
#define AT91C_SSC0_TCR (AT91_CAST(AT91_REG *) 0xFFFBC10C) // (PDC_SSC0) Transmit Counter Register
#define AT91C_SSC0_RNCR (AT91_CAST(AT91_REG *) 0xFFFBC114) // (PDC_SSC0) Receive Next Counter Register
#define AT91C_SSC0_RPR (AT91_CAST(AT91_REG *) 0xFFFBC100) // (PDC_SSC0) Receive Pointer Register
#define AT91C_SSC0_TPR (AT91_CAST(AT91_REG *) 0xFFFBC108) // (PDC_SSC0) Transmit Pointer Register
#define AT91C_SSC0_RCR (AT91_CAST(AT91_REG *) 0xFFFBC104) // (PDC_SSC0) Receive Counter Register
#define AT91C_SSC0_RNPR (AT91_CAST(AT91_REG *) 0xFFFBC110) // (PDC_SSC0) Receive Next Pointer Register
#define AT91C_SSC0_PTCR (AT91_CAST(AT91_REG *) 0xFFFBC120) // (PDC_SSC0) PDC Transfer Control Register
#define AT91C_SSC0_TNCR (AT91_CAST(AT91_REG *) 0xFFFBC11C) // (PDC_SSC0) Transmit Next Counter Register
#define AT91C_SSC0_PTSR (AT91_CAST(AT91_REG *) 0xFFFBC124) // (PDC_SSC0) PDC Transfer Status Register
// ========== Register definition for SSC0 peripheral ==========
#define AT91C_SSC0_IMR (AT91_CAST(AT91_REG *) 0xFFFBC04C) // (SSC0) Interrupt Mask Register
#define AT91C_SSC0_RFMR (AT91_CAST(AT91_REG *) 0xFFFBC014) // (SSC0) Receive Frame Mode Register
#define AT91C_SSC0_CR (AT91_CAST(AT91_REG *) 0xFFFBC000) // (SSC0) Control Register
#define AT91C_SSC0_TFMR (AT91_CAST(AT91_REG *) 0xFFFBC01C) // (SSC0) Transmit Frame Mode Register
#define AT91C_SSC0_CMR (AT91_CAST(AT91_REG *) 0xFFFBC004) // (SSC0) Clock Mode Register
#define AT91C_SSC0_IER (AT91_CAST(AT91_REG *) 0xFFFBC044) // (SSC0) Interrupt Enable Register
#define AT91C_SSC0_RHR (AT91_CAST(AT91_REG *) 0xFFFBC020) // (SSC0) Receive Holding Register
#define AT91C_SSC0_RCMR (AT91_CAST(AT91_REG *) 0xFFFBC010) // (SSC0) Receive Clock ModeRegister
#define AT91C_SSC0_SR (AT91_CAST(AT91_REG *) 0xFFFBC040) // (SSC0) Status Register
#define AT91C_SSC0_RSHR (AT91_CAST(AT91_REG *) 0xFFFBC030) // (SSC0) Receive Sync Holding Register
#define AT91C_SSC0_THR (AT91_CAST(AT91_REG *) 0xFFFBC024) // (SSC0) Transmit Holding Register
#define AT91C_SSC0_TCMR (AT91_CAST(AT91_REG *) 0xFFFBC018) // (SSC0) Transmit Clock Mode Register
#define AT91C_SSC0_IDR (AT91_CAST(AT91_REG *) 0xFFFBC048) // (SSC0) Interrupt Disable Register
#define AT91C_SSC0_TSHR (AT91_CAST(AT91_REG *) 0xFFFBC034) // (SSC0) Transmit Sync Holding Register
// ========== Register definition for PDC_SPI0 peripheral ==========
#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC8120) // (PDC_SPI0) PDC Transfer Control Register
#define AT91C_SPI0_TCR (AT91_CAST(AT91_REG *) 0xFFFC810C) // (PDC_SPI0) Transmit Counter Register
#define AT91C_SPI0_RPR (AT91_CAST(AT91_REG *) 0xFFFC8100) // (PDC_SPI0) Receive Pointer Register
#define AT91C_SPI0_TPR (AT91_CAST(AT91_REG *) 0xFFFC8108) // (PDC_SPI0) Transmit Pointer Register
#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC8124) // (PDC_SPI0) PDC Transfer Status Register
#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC8114) // (PDC_SPI0) Receive Next Counter Register
#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC8118) // (PDC_SPI0) Transmit Next Pointer Register
#define AT91C_SPI0_RCR (AT91_CAST(AT91_REG *) 0xFFFC8104) // (PDC_SPI0) Receive Counter Register
#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC8110) // (PDC_SPI0) Receive Next Pointer Register
#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC811C) // (PDC_SPI0) Transmit Next Counter Register
// ========== Register definition for SPI0 peripheral ==========
#define AT91C_SPI0_IDR (AT91_CAST(AT91_REG *) 0xFFFC8018) // (SPI0) Interrupt Disable Register
#define AT91C_SPI0_TDR (AT91_CAST(AT91_REG *) 0xFFFC800C) // (SPI0) Transmit Data Register
#define AT91C_SPI0_SR (AT91_CAST(AT91_REG *) 0xFFFC8010) // (SPI0) Status Register
#define AT91C_SPI0_CR (AT91_CAST(AT91_REG *) 0xFFFC8000) // (SPI0) Control Register
#define AT91C_SPI0_CSR (AT91_CAST(AT91_REG *) 0xFFFC8030) // (SPI0) Chip Select Register
#define AT91C_SPI0_RDR (AT91_CAST(AT91_REG *) 0xFFFC8008) // (SPI0) Receive Data Register
#define AT91C_SPI0_MR (AT91_CAST(AT91_REG *) 0xFFFC8004) // (SPI0) Mode Register
#define AT91C_SPI0_IER (AT91_CAST(AT91_REG *) 0xFFFC8014) // (SPI0) Interrupt Enable Register
#define AT91C_SPI0_IMR (AT91_CAST(AT91_REG *) 0xFFFC801C) // (SPI0) Interrupt Mask Register
// ========== Register definition for PDC_SPI1 peripheral ==========
#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFCC120) // (PDC_SPI1) PDC Transfer Control Register
#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFCC110) // (PDC_SPI1) Receive Next Pointer Register
#define AT91C_SPI1_RCR (AT91_CAST(AT91_REG *) 0xFFFCC104) // (PDC_SPI1) Receive Counter Register
#define AT91C_SPI1_TPR (AT91_CAST(AT91_REG *) 0xFFFCC108) // (PDC_SPI1) Transmit Pointer Register
#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFCC124) // (PDC_SPI1) PDC Transfer Status Register
#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFCC11C) // (PDC_SPI1) Transmit Next Counter Register
#define AT91C_SPI1_RPR (AT91_CAST(AT91_REG *) 0xFFFCC100) // (PDC_SPI1) Receive Pointer Register
#define AT91C_SPI1_TCR (AT91_CAST(AT91_REG *) 0xFFFCC10C) // (PDC_SPI1) Transmit Counter Register
#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFCC114) // (PDC_SPI1) Receive Next Counter Register
#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFCC118) // (PDC_SPI1) Transmit Next Pointer Register
// ========== Register definition for SPI1 peripheral ==========
#define AT91C_SPI1_IER (AT91_CAST(AT91_REG *) 0xFFFCC014) // (SPI1) Interrupt Enable Register
#define AT91C_SPI1_RDR (AT91_CAST(AT91_REG *) 0xFFFCC008) // (SPI1) Receive Data Register
#define AT91C_SPI1_SR (AT91_CAST(AT91_REG *) 0xFFFCC010) // (SPI1) Status Register
#define AT91C_SPI1_IMR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (SPI1) Interrupt Mask Register
#define AT91C_SPI1_TDR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (SPI1) Transmit Data Register
#define AT91C_SPI1_IDR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (SPI1) Interrupt Disable Register
#define AT91C_SPI1_CSR (AT91_CAST(AT91_REG *) 0xFFFCC030) // (SPI1) Chip Select Register
#define AT91C_SPI1_CR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (SPI1) Control Register
#define AT91C_SPI1_MR (AT91_CAST(AT91_REG *) 0xFFFCC004) // (SPI1) Mode Register
// ========== Register definition for PDC_ADC peripheral ==========
#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_ADC) PDC Transfer Control Register
#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_ADC) Transmit Pointer Register
#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_ADC) Transmit Counter Register
#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_ADC) Receive Counter Register
#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_ADC) PDC Transfer Status Register
#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_ADC) Receive Next Pointer Register
#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_ADC) Receive Pointer Register
#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_ADC) Transmit Next Counter Register
#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_ADC) Receive Next Counter Register
#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_ADC) Transmit Next Pointer Register
// ========== Register definition for ADC peripheral ==========
#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFE0014) // (ADC) ADC Channel Disable Register
#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFE003C) // (ADC) ADC Channel Data Register 3
#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (ADC) ADC Control Register
#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFE002C) // (ADC) ADC Interrupt Mask Register
#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFE0038) // (ADC) ADC Channel Data Register 2
#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (ADC) ADC Status Register
#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFE0024) // (ADC) ADC Interrupt Enable Register
#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFE004C) // (ADC) ADC Channel Data Register 7
#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFE0030) // (ADC) ADC Channel Data Register 0
#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFE0044) // (ADC) ADC Channel Data Register 5
#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFE0040) // (ADC) ADC Channel Data Register 4
#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFE0010) // (ADC) ADC Channel Enable Register
#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (ADC) ADC Channel Status Register
#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (ADC) ADC Mode Register
#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFE0048) // (ADC) ADC Channel Data Register 6
#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFE0020) // (ADC) ADC Last Converted Data Register
#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFE0034) // (ADC) ADC Channel Data Register 1
#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFE0028) // (ADC) ADC Interrupt Disable Register
// ========== Register definition for EMACB peripheral ==========
#define AT91C_EMACB_USRIO (AT91_CAST(AT91_REG *) 0xFFFC40C0) // (EMACB) USER Input/Output Register
#define AT91C_EMACB_RSE (AT91_CAST(AT91_REG *) 0xFFFC4074) // (EMACB) Receive Symbol Errors Register
#define AT91C_EMACB_SCF (AT91_CAST(AT91_REG *) 0xFFFC4044) // (EMACB) Single Collision Frame Register
#define AT91C_EMACB_STE (AT91_CAST(AT91_REG *) 0xFFFC4084) // (EMACB) SQE Test Error Register
#define AT91C_EMACB_SA1H (AT91_CAST(AT91_REG *) 0xFFFC409C) // (EMACB) Specific Address 1 Top, Last 2 bytes
#define AT91C_EMACB_ROV (AT91_CAST(AT91_REG *) 0xFFFC4070) // (EMACB) Receive Overrun Errors Register
#define AT91C_EMACB_TBQP (AT91_CAST(AT91_REG *) 0xFFFC401C) // (EMACB) Transmit Buffer Queue Pointer
#define AT91C_EMACB_IMR (AT91_CAST(AT91_REG *) 0xFFFC4030) // (EMACB) Interrupt Mask Register
#define AT91C_EMACB_IER (AT91_CAST(AT91_REG *) 0xFFFC4028) // (EMACB) Interrupt Enable Register
#define AT91C_EMACB_REV (AT91_CAST(AT91_REG *) 0xFFFC40FC) // (EMACB) Revision Register
#define AT91C_EMACB_SA3L (AT91_CAST(AT91_REG *) 0xFFFC40A8) // (EMACB) Specific Address 3 Bottom, First 4 bytes
#define AT91C_EMACB_ELE (AT91_CAST(AT91_REG *) 0xFFFC4078) // (EMACB) Excessive Length Errors Register
#define AT91C_EMACB_HRT (AT91_CAST(AT91_REG *) 0xFFFC4094) // (EMACB) Hash Address Top[63:32]
#define AT91C_EMACB_SA2L (AT91_CAST(AT91_REG *) 0xFFFC40A0) // (EMACB) Specific Address 2 Bottom, First 4 bytes
#define AT91C_EMACB_RRE (AT91_CAST(AT91_REG *) 0xFFFC406C) // (EMACB) Receive Ressource Error Register
#define AT91C_EMACB_FRO (AT91_CAST(AT91_REG *) 0xFFFC404C) // (EMACB) Frames Received OK Register
#define AT91C_EMACB_TPQ (AT91_CAST(AT91_REG *) 0xFFFC40BC) // (EMACB) Transmit Pause Quantum Register
#define AT91C_EMACB_ISR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (EMACB) Interrupt Status Register
#define AT91C_EMACB_TSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (EMACB) Transmit Status Register
#define AT91C_EMACB_RLE (AT91_CAST(AT91_REG *) 0xFFFC4088) // (EMACB) Receive Length Field Mismatch Register
#define AT91C_EMACB_USF (AT91_CAST(AT91_REG *) 0xFFFC4080) // (EMACB) Undersize Frames Register
#define AT91C_EMACB_WOL (AT91_CAST(AT91_REG *) 0xFFFC40C4) // (EMACB) Wake On LAN Register
#define AT91C_EMACB_TPF (AT91_CAST(AT91_REG *) 0xFFFC408C) // (EMACB) Transmitted Pause Frames Register
#define AT91C_EMACB_PTR (AT91_CAST(AT91_REG *) 0xFFFC4038) // (EMACB) Pause Time Register
#define AT91C_EMACB_TUND (AT91_CAST(AT91_REG *) 0xFFFC4064) // (EMACB) Transmit Underrun Error Register
#define AT91C_EMACB_MAN (AT91_CAST(AT91_REG *) 0xFFFC4034) // (EMACB) PHY Maintenance Register
#define AT91C_EMACB_RJA (AT91_CAST(AT91_REG *) 0xFFFC407C) // (EMACB) Receive Jabbers Register
#define AT91C_EMACB_SA4L (AT91_CAST(AT91_REG *) 0xFFFC40B0) // (EMACB) Specific Address 4 Bottom, First 4 bytes
#define AT91C_EMACB_CSE (AT91_CAST(AT91_REG *) 0xFFFC4068) // (EMACB) Carrier Sense Error Register
#define AT91C_EMACB_HRB (AT91_CAST(AT91_REG *) 0xFFFC4090) // (EMACB) Hash Address Bottom[31:0]
#define AT91C_EMACB_ALE (AT91_CAST(AT91_REG *) 0xFFFC4054) // (EMACB) Alignment Error Register
#define AT91C_EMACB_SA1L (AT91_CAST(AT91_REG *) 0xFFFC4098) // (EMACB) Specific Address 1 Bottom, First 4 bytes
#define AT91C_EMACB_NCR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (EMACB) Network Control Register
#define AT91C_EMACB_FTO (AT91_CAST(AT91_REG *) 0xFFFC4040) // (EMACB) Frames Transmitted OK Register
#define AT91C_EMACB_ECOL (AT91_CAST(AT91_REG *) 0xFFFC4060) // (EMACB) Excessive Collision Register
#define AT91C_EMACB_DTF (AT91_CAST(AT91_REG *) 0xFFFC4058) // (EMACB) Deferred Transmission Frame Register
#define AT91C_EMACB_SA4H (AT91_CAST(AT91_REG *) 0xFFFC40B4) // (EMACB) Specific Address 4 Top, Last 2 bytes
#define AT91C_EMACB_FCSE (AT91_CAST(AT91_REG *) 0xFFFC4050) // (EMACB) Frame Check Sequence Error Register
#define AT91C_EMACB_TID (AT91_CAST(AT91_REG *) 0xFFFC40B8) // (EMACB) Type ID Checking Register
#define AT91C_EMACB_PFR (AT91_CAST(AT91_REG *) 0xFFFC403C) // (EMACB) Pause Frames received Register
#define AT91C_EMACB_IDR (AT91_CAST(AT91_REG *) 0xFFFC402C) // (EMACB) Interrupt Disable Register
#define AT91C_EMACB_SA3H (AT91_CAST(AT91_REG *) 0xFFFC40AC) // (EMACB) Specific Address 3 Top, Last 2 bytes
#define AT91C_EMACB_NSR (AT91_CAST(AT91_REG *) 0xFFFC4008) // (EMACB) Network Status Register
#define AT91C_EMACB_MCF (AT91_CAST(AT91_REG *) 0xFFFC4048) // (EMACB) Multiple Collision Frame Register
#define AT91C_EMACB_RBQP (AT91_CAST(AT91_REG *) 0xFFFC4018) // (EMACB) Receive Buffer Queue Pointer
#define AT91C_EMACB_RSR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (EMACB) Receive Status Register
#define AT91C_EMACB_SA2H (AT91_CAST(AT91_REG *) 0xFFFC40A4) // (EMACB) Specific Address 2 Top, Last 2 bytes
#define AT91C_EMACB_NCFGR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (EMACB) Network Configuration Register
#define AT91C_EMACB_LCOL (AT91_CAST(AT91_REG *) 0xFFFC405C) // (EMACB) Late Collision Register
// ========== Register definition for UDP peripheral ==========
#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFA4004) // (UDP) Global State Register
#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFA4050) // (UDP) Endpoint FIFO Data Register
#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFA4028) // (UDP) Reset Endpoint Register
#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFA4008) // (UDP) Function Address Register
#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFA4000) // (UDP) Frame Number Register
#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFA4014) // (UDP) Interrupt Disable Register
#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFA4018) // (UDP) Interrupt Mask Register
#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFA4030) // (UDP) Endpoint Control and Status Register
#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFA4010) // (UDP) Interrupt Enable Register
#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFA4020) // (UDP) Interrupt Clear Register
#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFA4074) // (UDP) Transceiver Control Register
#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFA401C) // (UDP) Interrupt Status Register
// ========== Register definition for UHP peripheral ==========
#define AT91C_UHP_HcInterruptStatus (AT91_CAST(AT91_REG *) 0x0050000C) // (UHP) Interrupt Status Register
#define AT91C_UHP_HcCommandStatus (AT91_CAST(AT91_REG *) 0x00500008) // (UHP) Command & status Register
#define AT91C_UHP_HcRhStatus (AT91_CAST(AT91_REG *) 0x00500050) // (UHP) Root Hub Status register
#define AT91C_UHP_HcInterruptDisable (AT91_CAST(AT91_REG *) 0x00500014) // (UHP) Interrupt Disable Register
#define AT91C_UHP_HcPeriodicStart (AT91_CAST(AT91_REG *) 0x00500040) // (UHP) Periodic Start
#define AT91C_UHP_HcControlCurrentED (AT91_CAST(AT91_REG *) 0x00500024) // (UHP) Endpoint Control and Status Register
#define AT91C_UHP_HcPeriodCurrentED (AT91_CAST(AT91_REG *) 0x0050001C) // (UHP) Current Isochronous or Interrupt Endpoint Descriptor
#define AT91C_UHP_HcBulkHeadED (AT91_CAST(AT91_REG *) 0x00500028) // (UHP) First endpoint register of the Bulk list
#define AT91C_UHP_HcRevision (AT91_CAST(AT91_REG *) 0x00500000) // (UHP) Revision
#define AT91C_UHP_HcBulkCurrentED (AT91_CAST(AT91_REG *) 0x0050002C) // (UHP) Current endpoint of the Bulk list
#define AT91C_UHP_HcRhDescriptorB (AT91_CAST(AT91_REG *) 0x0050004C) // (UHP) Root Hub characteristics B
#define AT91C_UHP_HcControlHeadED (AT91_CAST(AT91_REG *) 0x00500020) // (UHP) First Endpoint Descriptor of the Control list
#define AT91C_UHP_HcFmRemaining (AT91_CAST(AT91_REG *) 0x00500038) // (UHP) Bit time remaining in the current Frame
#define AT91C_UHP_HcHCCA (AT91_CAST(AT91_REG *) 0x00500018) // (UHP) Pointer to the Host Controller Communication Area
#define AT91C_UHP_HcLSThreshold (AT91_CAST(AT91_REG *) 0x00500044) // (UHP) LS Threshold
#define AT91C_UHP_HcRhPortStatus (AT91_CAST(AT91_REG *) 0x00500054) // (UHP) Root Hub Port Status Register
#define AT91C_UHP_HcInterruptEnable (AT91_CAST(AT91_REG *) 0x00500010) // (UHP) Interrupt Enable Register
#define AT91C_UHP_HcFmNumber (AT91_CAST(AT91_REG *) 0x0050003C) // (UHP) Frame number
#define AT91C_UHP_HcFmInterval (AT91_CAST(AT91_REG *) 0x00500034) // (UHP) Bit time between 2 consecutive SOFs
#define AT91C_UHP_HcControl (AT91_CAST(AT91_REG *) 0x00500004) // (UHP) Operating modes for the Host Controller
#define AT91C_UHP_HcBulkDoneHead (AT91_CAST(AT91_REG *) 0x00500030) // (UHP) Last completed transfer descriptor
#define AT91C_UHP_HcRhDescriptorA (AT91_CAST(AT91_REG *) 0x00500048) // (UHP) Root Hub characteristics A
// ========== Register definition for HECC peripheral ==========
// ========== Register definition for HISI peripheral ==========
#define AT91C_HISI_PSIZE (AT91_CAST(AT91_REG *) 0xFFFC0020) // (HISI) Preview Size Register
#define AT91C_HISI_CR1 (AT91_CAST(AT91_REG *) 0xFFFC0000) // (HISI) Control Register 1
#define AT91C_HISI_R2YSET1 (AT91_CAST(AT91_REG *) 0xFFFC003C) // (HISI) Color Space Conversion Register
#define AT91C_HISI_CDBA (AT91_CAST(AT91_REG *) 0xFFFC002C) // (HISI) Codec Dma Address Register
#define AT91C_HISI_IDR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (HISI) Interrupt Disable Register
#define AT91C_HISI_R2YSET2 (AT91_CAST(AT91_REG *) 0xFFFC0040) // (HISI) Color Space Conversion Register
#define AT91C_HISI_Y2RSET1 (AT91_CAST(AT91_REG *) 0xFFFC0034) // (HISI) Color Space Conversion Register
#define AT91C_HISI_PFBD (AT91_CAST(AT91_REG *) 0xFFFC0028) // (HISI) Preview Frame Buffer Address Register
#define AT91C_HISI_CR2 (AT91_CAST(AT91_REG *) 0xFFFC0004) // (HISI) Control Register 2
#define AT91C_HISI_Y2RSET0 (AT91_CAST(AT91_REG *) 0xFFFC0030) // (HISI) Color Space Conversion Register
#define AT91C_HISI_PDECF (AT91_CAST(AT91_REG *) 0xFFFC0024) // (HISI) Preview Decimation Factor Register
#define AT91C_HISI_IMR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (HISI) Interrupt Mask Register
#define AT91C_HISI_IER (AT91_CAST(AT91_REG *) 0xFFFC000C) // (HISI) Interrupt Enable Register
#define AT91C_HISI_R2YSET0 (AT91_CAST(AT91_REG *) 0xFFFC0038) // (HISI) Color Space Conversion Register
#define AT91C_HISI_SR (AT91_CAST(AT91_REG *) 0xFFFC0008) // (HISI) Status Register
// *****************************************************************************
// PIO DEFINITIONS FOR AT91SAM9XE512
// *****************************************************************************
#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0
#define AT91C_PA0_SPI0_MISO (AT91C_PIO_PA0) // SPI 0 Master In Slave
#define AT91C_PA0_MCDB0 (AT91C_PIO_PA0) // Multimedia Card B Data 0
#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1
#define AT91C_PA1_SPI0_MOSI (AT91C_PIO_PA1) // SPI 0 Master Out Slave
#define AT91C_PA1_MCCDB (AT91C_PIO_PA1) // Multimedia Card B Command
#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10
#define AT91C_PA10_MCDA2 (AT91C_PIO_PA10) // Multimedia Card A Data 2
#define AT91C_PA10_ETX2_0 (AT91C_PIO_PA10) // Ethernet MAC Transmit Data 2
#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11
#define AT91C_PA11_MCDA3 (AT91C_PIO_PA11) // Multimedia Card A Data 3
#define AT91C_PA11_ETX3_0 (AT91C_PIO_PA11) // Ethernet MAC Transmit Data 3
#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12
#define AT91C_PA12_ETX0 (AT91C_PIO_PA12) // Ethernet MAC Transmit Data 0
#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13
#define AT91C_PA13_ETX1 (AT91C_PIO_PA13) // Ethernet MAC Transmit Data 1
#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14
#define AT91C_PA14_ERX0 (AT91C_PIO_PA14) // Ethernet MAC Receive Data 0
#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15
#define AT91C_PA15_ERX1 (AT91C_PIO_PA15) // Ethernet MAC Receive Data 1
#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16
#define AT91C_PA16_ETXEN (AT91C_PIO_PA16) // Ethernet MAC Transmit Enable
#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17
#define AT91C_PA17_ERXDV (AT91C_PIO_PA17) // Ethernet MAC Receive Data Valid
#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18
#define AT91C_PA18_ERXER (AT91C_PIO_PA18) // Ethernet MAC Receive Error
#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19
#define AT91C_PA19_ETXCK (AT91C_PIO_PA19) // Ethernet MAC Transmit Clock/Reference Clock
#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2
#define AT91C_PA2_SPI0_SPCK (AT91C_PIO_PA2) // SPI 0 Serial Clock
#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20
#define AT91C_PA20_EMDC (AT91C_PIO_PA20) // Ethernet MAC Management Data Clock
#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21
#define AT91C_PA21_EMDIO (AT91C_PIO_PA21) // Ethernet MAC Management Data Input/Output
#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22
#define AT91C_PA22_ADTRG (AT91C_PIO_PA22) // ADC Trigger
#define AT91C_PA22_ETXER (AT91C_PIO_PA22) // Ethernet MAC Transmikt Coding Error
#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23
#define AT91C_PA23_TWD0 (AT91C_PIO_PA23) // TWI Two-wire Serial Data 0
#define AT91C_PA23_ETX2_1 (AT91C_PIO_PA23) // Ethernet MAC Transmit Data 2
#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24
#define AT91C_PA24_TWCK0 (AT91C_PIO_PA24) // TWI Two-wire Serial Clock 0
#define AT91C_PA24_ETX3_1 (AT91C_PIO_PA24) // Ethernet MAC Transmit Data 3
#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25
#define AT91C_PA25_TCLK0 (AT91C_PIO_PA25) // Timer Counter 0 external clock input
#define AT91C_PA25_ERX2 (AT91C_PIO_PA25) // Ethernet MAC Receive Data 2
#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26
#define AT91C_PA26_TIOA0 (AT91C_PIO_PA26) // Timer Counter 0 Multipurpose Timer I/O Pin A
#define AT91C_PA26_ERX3 (AT91C_PIO_PA26) // Ethernet MAC Receive Data 3
#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27
#define AT91C_PA27_TIOA1 (AT91C_PIO_PA27) // Timer Counter 1 Multipurpose Timer I/O Pin A
#define AT91C_PA27_ERXCK (AT91C_PIO_PA27) // Ethernet MAC Receive Clock
#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28
#define AT91C_PA28_TIOA2 (AT91C_PIO_PA28) // Timer Counter 2 Multipurpose Timer I/O Pin A
#define AT91C_PA28_ECRS (AT91C_PIO_PA28) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29
#define AT91C_PA29_SCK1 (AT91C_PIO_PA29) // USART 1 Serial Clock
#define AT91C_PA29_ECOL (AT91C_PIO_PA29) // Ethernet MAC Collision Detected
#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3
#define AT91C_PA3_SPI0_NPCS0 (AT91C_PIO_PA3) // SPI 0 Peripheral Chip Select 0
#define AT91C_PA3_MCDB3 (AT91C_PIO_PA3) // Multimedia Card B Data 3
#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30
#define AT91C_PA30_SCK2 (AT91C_PIO_PA30) // USART 2 Serial Clock
#define AT91C_PA30_RXD4 (AT91C_PIO_PA30) // USART 4 Receive Data
#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31
#define AT91C_PA31_SCK0 (AT91C_PIO_PA31) // USART 0 Serial Clock
#define AT91C_PA31_TXD4 (AT91C_PIO_PA31) // USART 4 Transmit Data
#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4
#define AT91C_PA4_RTS2 (AT91C_PIO_PA4) // USART 2 Ready To Send
#define AT91C_PA4_MCDB2 (AT91C_PIO_PA4) // Multimedia Card B Data 2
#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5
#define AT91C_PA5_CTS2 (AT91C_PIO_PA5) // USART 2 Clear To Send
#define AT91C_PA5_MCDB1 (AT91C_PIO_PA5) // Multimedia Card B Data 1
#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6
#define AT91C_PA6_MCDA0 (AT91C_PIO_PA6) // Multimedia Card A Data 0
#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7
#define AT91C_PA7_MCCDA (AT91C_PIO_PA7) // Multimedia Card A Command
#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8
#define AT91C_PA8_MCCK (AT91C_PIO_PA8) // Multimedia Card Clock
#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9
#define AT91C_PA9_MCDA1 (AT91C_PIO_PA9) // Multimedia Card A Data 1
#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0
#define AT91C_PB0_SPI1_MISO (AT91C_PIO_PB0) // SPI 1 Master In Slave
#define AT91C_PB0_TIOA3 (AT91C_PIO_PB0) // Timer Counter 3 Multipurpose Timer I/O Pin A
#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1
#define AT91C_PB1_SPI1_MOSI (AT91C_PIO_PB1) // SPI 1 Master Out Slave
#define AT91C_PB1_TIOB3 (AT91C_PIO_PB1) // Timer Counter 3 Multipurpose Timer I/O Pin B
#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10
#define AT91C_PB10_TXD3 (AT91C_PIO_PB10) // USART 3 Transmit Data
#define AT91C_PB10_ISI_D8 (AT91C_PIO_PB10) // Image Sensor Data 8
#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11
#define AT91C_PB11_RXD3 (AT91C_PIO_PB11) // USART 3 Receive Data
#define AT91C_PB11_ISI_D9 (AT91C_PIO_PB11) // Image Sensor Data 9
#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12
#define AT91C_PB12_TWD1 (AT91C_PIO_PB12) // TWI Two-wire Serial Data 1
#define AT91C_PB12_ISI_D10 (AT91C_PIO_PB12) // Image Sensor Data 10
#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13
#define AT91C_PB13_TWCK1 (AT91C_PIO_PB13) // TWI Two-wire Serial Clock 1
#define AT91C_PB13_ISI_D11 (AT91C_PIO_PB13) // Image Sensor Data 11
#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14
#define AT91C_PB14_DRXD (AT91C_PIO_PB14) // DBGU Debug Receive Data
#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15
#define AT91C_PB15_DTXD (AT91C_PIO_PB15) // DBGU Debug Transmit Data
#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16
#define AT91C_PB16_TK0 (AT91C_PIO_PB16) // SSC0 Transmit Clock
#define AT91C_PB16_TCLK3 (AT91C_PIO_PB16) // Timer Counter 3 external clock input
#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17
#define AT91C_PB17_TF0 (AT91C_PIO_PB17) // SSC0 Transmit Frame Sync
#define AT91C_PB17_TCLK4 (AT91C_PIO_PB17) // Timer Counter 4 external clock input
#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18
#define AT91C_PB18_TD0 (AT91C_PIO_PB18) // SSC0 Transmit data
#define AT91C_PB18_TIOB4 (AT91C_PIO_PB18) // Timer Counter 4 Multipurpose Timer I/O Pin B
#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19
#define AT91C_PB19_RD0 (AT91C_PIO_PB19) // SSC0 Receive Data
#define AT91C_PB19_TIOB5 (AT91C_PIO_PB19) // Timer Counter 5 Multipurpose Timer I/O Pin B
#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2
#define AT91C_PB2_SPI1_SPCK (AT91C_PIO_PB2) // SPI 1 Serial Clock
#define AT91C_PB2_TIOA4 (AT91C_PIO_PB2) // Timer Counter 4 Multipurpose Timer I/O Pin A
#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20
#define AT91C_PB20_RK0 (AT91C_PIO_PB20) // SSC0 Receive Clock
#define AT91C_PB20_ISI_D0 (AT91C_PIO_PB20) // Image Sensor Data 0
#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21
#define AT91C_PB21_RF0 (AT91C_PIO_PB21) // SSC0 Receive Frame Sync
#define AT91C_PB21_ISI_D1 (AT91C_PIO_PB21) // Image Sensor Data 1
#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22
#define AT91C_PB22_DSR0 (AT91C_PIO_PB22) // USART 0 Data Set ready
#define AT91C_PB22_ISI_D2 (AT91C_PIO_PB22) // Image Sensor Data 2
#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23
#define AT91C_PB23_DCD0 (AT91C_PIO_PB23) // USART 0 Data Carrier Detect
#define AT91C_PB23_ISI_D3 (AT91C_PIO_PB23) // Image Sensor Data 3
#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24
#define AT91C_PB24_DTR0 (AT91C_PIO_PB24) // USART 0 Data Terminal ready
#define AT91C_PB24_ISI_D4 (AT91C_PIO_PB24) // Image Sensor Data 4
#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25
#define AT91C_PB25_RI0 (AT91C_PIO_PB25) // USART 0 Ring Indicator
#define AT91C_PB25_ISI_D5 (AT91C_PIO_PB25) // Image Sensor Data 5
#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26
#define AT91C_PB26_RTS0 (AT91C_PIO_PB26) // USART 0 Ready To Send
#define AT91C_PB26_ISI_D6 (AT91C_PIO_PB26) // Image Sensor Data 6
#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27
#define AT91C_PB27_CTS0 (AT91C_PIO_PB27) // USART 0 Clear To Send
#define AT91C_PB27_ISI_D7 (AT91C_PIO_PB27) // Image Sensor Data 7
#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28
#define AT91C_PB28_RTS1 (AT91C_PIO_PB28) // USART 1 Ready To Send
#define AT91C_PB28_ISI_PCK (AT91C_PIO_PB28) // Image Sensor Data Clock
#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29
#define AT91C_PB29_CTS1 (AT91C_PIO_PB29) // USART 1 Clear To Send
#define AT91C_PB29_ISI_VSYNC (AT91C_PIO_PB29) // Image Sensor Vertical Synchro
#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3
#define AT91C_PB3_SPI1_NPCS0 (AT91C_PIO_PB3) // SPI 1 Peripheral Chip Select 0
#define AT91C_PB3_TIOA5 (AT91C_PIO_PB3) // Timer Counter 5 Multipurpose Timer I/O Pin A
#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30
#define AT91C_PB30_PCK0_0 (AT91C_PIO_PB30) // PMC Programmable Clock Output 0
#define AT91C_PB30_ISI_HSYNC (AT91C_PIO_PB30) // Image Sensor Horizontal Synchro
#define AT91C_PIO_PB31 (1 << 31) // Pin Controlled by PB31
#define AT91C_PB31_PCK1_0 (AT91C_PIO_PB31) // PMC Programmable Clock Output 1
#define AT91C_PB31_ISI_MCK (AT91C_PIO_PB31) // Image Sensor Reference Clock
#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4
#define AT91C_PB4_TXD0 (AT91C_PIO_PB4) // USART 0 Transmit Data
#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5
#define AT91C_PB5_RXD0 (AT91C_PIO_PB5) // USART 0 Receive Data
#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6
#define AT91C_PB6_TXD1 (AT91C_PIO_PB6) // USART 1 Transmit Data
#define AT91C_PB6_TCLK1 (AT91C_PIO_PB6) // Timer Counter 1 external clock input
#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7
#define AT91C_PB7_RXD1 (AT91C_PIO_PB7) // USART 1 Receive Data
#define AT91C_PB7_TCLK2 (AT91C_PIO_PB7) // Timer Counter 2 external clock input
#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8
#define AT91C_PB8_TXD2 (AT91C_PIO_PB8) // USART 2 Transmit Data
#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9
#define AT91C_PB9_RXD2 (AT91C_PIO_PB9) // USART 2 Receive Data
#define AT91C_PIO_PC0 (1 << 0) // Pin Controlled by PC0
#define AT91C_PC0_AD0 (AT91C_PIO_PC0) // ADC Analog Input 0
#define AT91C_PC0_SCK3 (AT91C_PIO_PC0) // USART 3 Serial Clock
#define AT91C_PIO_PC1 (1 << 1) // Pin Controlled by PC1
#define AT91C_PC1_AD1 (AT91C_PIO_PC1) // ADC Analog Input 1
#define AT91C_PC1_PCK0 (AT91C_PIO_PC1) // PMC Programmable Clock Output 0
#define AT91C_PIO_PC10 (1 << 10) // Pin Controlled by PC10
#define AT91C_PC10_A25_CFRNW (AT91C_PIO_PC10) // Address Bus[25]
#define AT91C_PC10_CTS3 (AT91C_PIO_PC10) // USART 3 Clear To Send
#define AT91C_PIO_PC11 (1 << 11) // Pin Controlled by PC11
#define AT91C_PC11_NCS2 (AT91C_PIO_PC11) // Chip Select Line 2
#define AT91C_PC11_SPI0_NPCS1 (AT91C_PIO_PC11) // SPI 0 Peripheral Chip Select 1
#define AT91C_PIO_PC12 (1 << 12) // Pin Controlled by PC12
#define AT91C_PC12_IRQ0 (AT91C_PIO_PC12) // External Interrupt 0
#define AT91C_PC12_NCS7 (AT91C_PIO_PC12) // Chip Select Line 7
#define AT91C_PIO_PC13 (1 << 13) // Pin Controlled by PC13
#define AT91C_PC13_FIQ (AT91C_PIO_PC13) // AIC Fast Interrupt Input
#define AT91C_PC13_NCS6 (AT91C_PIO_PC13) // Chip Select Line 6
#define AT91C_PIO_PC14 (1 << 14) // Pin Controlled by PC14
#define AT91C_PC14_NCS3_NANDCS (AT91C_PIO_PC14) // Chip Select Line 3
#define AT91C_PC14_IRQ2 (AT91C_PIO_PC14) // External Interrupt 2
#define AT91C_PIO_PC15 (1 << 15) // Pin Controlled by PC15
#define AT91C_PC15_NWAIT (AT91C_PIO_PC15) // External Wait Signal
#define AT91C_PC15_IRQ1 (AT91C_PIO_PC15) // External Interrupt 1
#define AT91C_PIO_PC16 (1 << 16) // Pin Controlled by PC16
#define AT91C_PC16_D16 (AT91C_PIO_PC16) // Data Bus[16]
#define AT91C_PC16_SPI0_NPCS2 (AT91C_PIO_PC16) // SPI 0 Peripheral Chip Select 2
#define AT91C_PIO_PC17 (1 << 17) // Pin Controlled by PC17
#define AT91C_PC17_D17 (AT91C_PIO_PC17) // Data Bus[17]
#define AT91C_PC17_SPI0_NPCS3 (AT91C_PIO_PC17) // SPI 0 Peripheral Chip Select 3
#define AT91C_PIO_PC18 (1 << 18) // Pin Controlled by PC18
#define AT91C_PC18_D18 (AT91C_PIO_PC18) // Data Bus[18]
#define AT91C_PC18_SPI1_NPCS1_1 (AT91C_PIO_PC18) // SPI 1 Peripheral Chip Select 1
#define AT91C_PIO_PC19 (1 << 19) // Pin Controlled by PC19
#define AT91C_PC19_D19 (AT91C_PIO_PC19) // Data Bus[19]
#define AT91C_PC19_SPI1_NPCS2_1 (AT91C_PIO_PC19) // SPI 1 Peripheral Chip Select 2
#define AT91C_PIO_PC2 (1 << 2) // Pin Controlled by PC2
#define AT91C_PC2_AD2 (AT91C_PIO_PC2) // ADC Analog Input 2
#define AT91C_PC2_PCK1 (AT91C_PIO_PC2) // PMC Programmable Clock Output 1
#define AT91C_PIO_PC20 (1 << 20) // Pin Controlled by PC20
#define AT91C_PC20_D20 (AT91C_PIO_PC20) // Data Bus[20]
#define AT91C_PC20_SPI1_NPCS3_1 (AT91C_PIO_PC20) // SPI 1 Peripheral Chip Select 3
#define AT91C_PIO_PC21 (1 << 21) // Pin Controlled by PC21
#define AT91C_PC21_D21 (AT91C_PIO_PC21) // Data Bus[21]
#define AT91C_PC21_EF100 (AT91C_PIO_PC21) // Ethernet MAC Force 100 Mbits/sec
#define AT91C_PIO_PC22 (1 << 22) // Pin Controlled by PC22
#define AT91C_PC22_D22 (AT91C_PIO_PC22) // Data Bus[22]
#define AT91C_PC22_TCLK5 (AT91C_PIO_PC22) // Timer Counter 5 external clock input
#define AT91C_PIO_PC23 (1 << 23) // Pin Controlled by PC23
#define AT91C_PC23_D23 (AT91C_PIO_PC23) // Data Bus[23]
#define AT91C_PIO_PC24 (1 << 24) // Pin Controlled by PC24
#define AT91C_PC24_D24 (AT91C_PIO_PC24) // Data Bus[24]
#define AT91C_PIO_PC25 (1 << 25) // Pin Controlled by PC25
#define AT91C_PC25_D25 (AT91C_PIO_PC25) // Data Bus[25]
#define AT91C_PIO_PC26 (1 << 26) // Pin Controlled by PC26
#define AT91C_PC26_D26 (AT91C_PIO_PC26) // Data Bus[26]
#define AT91C_PIO_PC27 (1 << 27) // Pin Controlled by PC27
#define AT91C_PC27_D27 (AT91C_PIO_PC27) // Data Bus[27]
#define AT91C_PIO_PC28 (1 << 28) // Pin Controlled by PC28
#define AT91C_PC28_D28 (AT91C_PIO_PC28) // Data Bus[28]
#define AT91C_PIO_PC29 (1 << 29) // Pin Controlled by PC29
#define AT91C_PC29_D29 (AT91C_PIO_PC29) // Data Bus[29]
#define AT91C_PIO_PC3 (1 << 3) // Pin Controlled by PC3
#define AT91C_PC3_AD3 (AT91C_PIO_PC3) // ADC Analog Input 3
#define AT91C_PC3_SPI1_NPCS3_0 (AT91C_PIO_PC3) // SPI 1 Peripheral Chip Select 3
#define AT91C_PIO_PC30 (1 << 30) // Pin Controlled by PC30
#define AT91C_PC30_D30 (AT91C_PIO_PC30) // Data Bus[30]
#define AT91C_PIO_PC31 (1 << 31) // Pin Controlled by PC31
#define AT91C_PC31_D31 (AT91C_PIO_PC31) // Data Bus[31]
#define AT91C_PIO_PC4 (1 << 4) // Pin Controlled by PC4
#define AT91C_PC4_A23 (AT91C_PIO_PC4) // Address Bus[23]
#define AT91C_PC4_SPI1_NPCS2_0 (AT91C_PIO_PC4) // SPI 1 Peripheral Chip Select 2
#define AT91C_PIO_PC5 (1 << 5) // Pin Controlled by PC5
#define AT91C_PC5_A24 (AT91C_PIO_PC5) // Address Bus[24]
#define AT91C_PC5_SPI1_NPCS1_0 (AT91C_PIO_PC5) // SPI 1 Peripheral Chip Select 1
#define AT91C_PIO_PC6 (1 << 6) // Pin Controlled by PC6
#define AT91C_PC6_TIOB2 (AT91C_PIO_PC6) // Timer Counter 2 Multipurpose Timer I/O Pin B
#define AT91C_PC6_CFCE1 (AT91C_PIO_PC6) // Compact Flash Enable 1
#define AT91C_PIO_PC7 (1 << 7) // Pin Controlled by PC7
#define AT91C_PC7_TIOB1 (AT91C_PIO_PC7) // Timer Counter 1 Multipurpose Timer I/O Pin B
#define AT91C_PC7_CFCE2 (AT91C_PIO_PC7) // Compact Flash Enable 2
#define AT91C_PIO_PC8 (1 << 8) // Pin Controlled by PC8
#define AT91C_PC8_NCS4_CFCS0 (AT91C_PIO_PC8) // Chip Select Line 4
#define AT91C_PC8_RTS3 (AT91C_PIO_PC8) // USART 3 Ready To Send
#define AT91C_PIO_PC9 (1 << 9) // Pin Controlled by PC9
#define AT91C_PC9_NCS5_CFCS1 (AT91C_PIO_PC9) // Chip Select Line 5
#define AT91C_PC9_TIOB0 (AT91C_PIO_PC9) // Timer Counter 0 Multipurpose Timer I/O Pin B
// *****************************************************************************
// PERIPHERAL ID DEFINITIONS FOR AT91SAM9XE512
// *****************************************************************************
#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)
#define AT91C_ID_SYS ( 1) // System Controller
#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A
#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B
#define AT91C_ID_PIOC ( 4) // Parallel IO Controller C
#define AT91C_ID_ADC ( 5) // ADC
#define AT91C_ID_US0 ( 6) // USART 0
#define AT91C_ID_US1 ( 7) // USART 1
#define AT91C_ID_US2 ( 8) // USART 2
#define AT91C_ID_MCI ( 9) // Multimedia Card Interface 0
#define AT91C_ID_UDP (10) // USB Device Port
#define AT91C_ID_TWI0 (11) // Two-Wire Interface 0
#define AT91C_ID_SPI0 (12) // Serial Peripheral Interface 0
#define AT91C_ID_SPI1 (13) // Serial Peripheral Interface 1
#define AT91C_ID_SSC0 (14) // Serial Synchronous Controller 0
#define AT91C_ID_TC0 (17) // Timer Counter 0
#define AT91C_ID_TC1 (18) // Timer Counter 1
#define AT91C_ID_TC2 (19) // Timer Counter 2
#define AT91C_ID_UHP (20) // USB Host Port
#define AT91C_ID_EMAC (21) // Ethernet Mac
#define AT91C_ID_HISI (22) // Image Sensor Interface
#define AT91C_ID_US3 (23) // USART 3
#define AT91C_ID_US4 (24) // USART 4
#define AT91C_ID_TWI1 (25) // Two-Wire Interface 1
#define AT91C_ID_TC3 (26) // Timer Counter 3
#define AT91C_ID_TC4 (27) // Timer Counter 4
#define AT91C_ID_TC5 (28) // Timer Counter 5
#define AT91C_ID_IRQ0 (29) // Advanced Interrupt Controller (IRQ0)
#define AT91C_ID_IRQ1 (30) // Advanced Interrupt Controller (IRQ1)
#define AT91C_ID_IRQ2 (31) // Advanced Interrupt Controller (IRQ2)
#define AT91C_ALL_INT (0xFFFE7FFF) // ALL VALID INTERRUPTS
// *****************************************************************************
// BASE ADDRESS DEFINITIONS FOR AT91SAM9XE512
// *****************************************************************************
#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFFD00) // (SYS) Base Address
#define AT91C_BASE_EBI (AT91_CAST(AT91PS_EBI) 0xFFFFEA00) // (EBI) Base Address
#define AT91C_BASE_HECC (AT91_CAST(AT91PS_ECC) 0xFFFFE800) // (HECC) Base Address
#define AT91C_BASE_SDRAMC (AT91_CAST(AT91PS_SDRAMC) 0xFFFFEA00) // (SDRAMC) Base Address
#define AT91C_BASE_SMC (AT91_CAST(AT91PS_SMC) 0xFFFFEC00) // (SMC) Base Address
#define AT91C_BASE_MATRIX (AT91_CAST(AT91PS_MATRIX) 0xFFFFEE00) // (MATRIX) Base Address
#define AT91C_BASE_CCFG (AT91_CAST(AT91PS_CCFG) 0xFFFFEF10) // (CCFG) Base Address
#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address
#define AT91C_BASE_PIOC (AT91_CAST(AT91PS_PIO) 0xFFFFF800) // (PIOC) Base Address
#define AT91C_BASE_EFC (AT91_CAST(AT91PS_EFC) 0xFFFFFA00) // (EFC) Base Address
#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
#define AT91C_BASE_SHDWC (AT91_CAST(AT91PS_SHDWC) 0xFFFFFD10) // (SHDWC) Base Address
#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
#define AT91C_BASE_TC3 (AT91_CAST(AT91PS_TC) 0xFFFDC000) // (TC3) Base Address
#define AT91C_BASE_TC4 (AT91_CAST(AT91PS_TC) 0xFFFDC040) // (TC4) Base Address
#define AT91C_BASE_TC5 (AT91_CAST(AT91PS_TC) 0xFFFDC080) // (TC5) Base Address
#define AT91C_BASE_TCB0 (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB0) Base Address
#define AT91C_BASE_TCB1 (AT91_CAST(AT91PS_TCB) 0xFFFDC000) // (TCB1) Base Address
#define AT91C_BASE_PDC_MCI (AT91_CAST(AT91PS_PDC) 0xFFFA8100) // (PDC_MCI) Base Address
#define AT91C_BASE_MCI (AT91_CAST(AT91PS_MCI) 0xFFFA8000) // (MCI) Base Address
#define AT91C_BASE_PDC_TWI0 (AT91_CAST(AT91PS_PDC) 0xFFFAC100) // (PDC_TWI0) Base Address
#define AT91C_BASE_TWI0 (AT91_CAST(AT91PS_TWI) 0xFFFAC000) // (TWI0) Base Address
#define AT91C_BASE_PDC_TWI1 (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_TWI1) Base Address
#define AT91C_BASE_TWI1 (AT91_CAST(AT91PS_TWI) 0xFFFD8000) // (TWI1) Base Address
#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFB0100) // (PDC_US0) Base Address
#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFB0000) // (US0) Base Address
#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFB4100) // (PDC_US1) Base Address
#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFB4000) // (US1) Base Address
#define AT91C_BASE_PDC_US2 (AT91_CAST(AT91PS_PDC) 0xFFFB8100) // (PDC_US2) Base Address
#define AT91C_BASE_US2 (AT91_CAST(AT91PS_USART) 0xFFFB8000) // (US2) Base Address
#define AT91C_BASE_PDC_US3 (AT91_CAST(AT91PS_PDC) 0xFFFD0100) // (PDC_US3) Base Address
#define AT91C_BASE_US3 (AT91_CAST(AT91PS_USART) 0xFFFD0000) // (US3) Base Address
#define AT91C_BASE_PDC_US4 (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_US4) Base Address
#define AT91C_BASE_US4 (AT91_CAST(AT91PS_USART) 0xFFFD4000) // (US4) Base Address
#define AT91C_BASE_PDC_SSC0 (AT91_CAST(AT91PS_PDC) 0xFFFBC100) // (PDC_SSC0) Base Address
#define AT91C_BASE_SSC0 (AT91_CAST(AT91PS_SSC) 0xFFFBC000) // (SSC0) Base Address
#define AT91C_BASE_PDC_SPI0 (AT91_CAST(AT91PS_PDC) 0xFFFC8100) // (PDC_SPI0) Base Address
#define AT91C_BASE_SPI0 (AT91_CAST(AT91PS_SPI) 0xFFFC8000) // (SPI0) Base Address
#define AT91C_BASE_PDC_SPI1 (AT91_CAST(AT91PS_PDC) 0xFFFCC100) // (PDC_SPI1) Base Address
#define AT91C_BASE_SPI1 (AT91_CAST(AT91PS_SPI) 0xFFFCC000) // (SPI1) Base Address
#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_ADC) Base Address
#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFE0000) // (ADC) Base Address
#define AT91C_BASE_EMACB (AT91_CAST(AT91PS_EMAC) 0xFFFC4000) // (EMACB) Base Address
#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFA4000) // (UDP) Base Address
#define AT91C_BASE_UHP (AT91_CAST(AT91PS_UHP) 0x00500000) // (UHP) Base Address
#define AT91C_BASE_HISI (AT91_CAST(AT91PS_ISI) 0xFFFC0000) // (HISI) Base Address
// *****************************************************************************
// MEMORY MAPPING DEFINITIONS FOR AT91SAM9XE512
// *****************************************************************************
// IROM
#define AT91C_IROM (0x00100000) // Internal ROM base address
#define AT91C_IROM_SIZE (0x00008000) // Internal ROM size in byte (32 Kbytes)
// ISRAM
#define AT91C_ISRAM (0x00300000) // Maximum IRAM Area : 32Kbyte base address
#define AT91C_ISRAM_SIZE (0x00008000) // Maximum IRAM Area : 32Kbyte size in byte (32 Kbytes)
// ISRAM_MIN
#define AT91C_ISRAM_MIN (0x00300000) // Minimun IRAM Area : 32Kbyte base address
#define AT91C_ISRAM_MIN_SIZE (0x00008000) // Minimun IRAM Area : 32Kbyte size in byte (32 Kbytes)
// IFLASH
#define AT91C_IFLASH (0x00200000) // Maximum IFLASH Area : 512Kbyte base address
#define AT91C_IFLASH_SIZE (0x00080000) // Maximum IFLASH Area : 512Kbyte size in byte (512 Kbytes)
#define AT91C_IFLASH_PAGE_SIZE (512) // Maximum IFLASH Area : 512Kbyte Page Size: 512 bytes
#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Maximum IFLASH Area : 512Kbyte Lock Region Size: 16 Kbytes
#define AT91C_IFLASH_NB_OF_PAGES (1024) // Maximum IFLASH Area : 512Kbyte Number of Pages: 1024 bytes
#define AT91C_IFLASH_NB_OF_LOCK_BITS (32) // Maximum IFLASH Area : 512Kbyte Number of Lock Bits: 32 bytes
// EBI_CS0
#define AT91C_EBI_CS0 (0x10000000) // EBI Chip Select 0 base address
#define AT91C_EBI_CS0_SIZE (0x10000000) // EBI Chip Select 0 size in byte (262144 Kbytes)
// EBI_CS1
#define AT91C_EBI_CS1 (0x20000000) // EBI Chip Select 1 base address
#define AT91C_EBI_CS1_SIZE (0x10000000) // EBI Chip Select 1 size in byte (262144 Kbytes)
// EBI_SDRAM
#define AT91C_EBI_SDRAM (0x20000000) // SDRAM on EBI Chip Select 1 base address
#define AT91C_EBI_SDRAM_SIZE (0x10000000) // SDRAM on EBI Chip Select 1 size in byte (262144 Kbytes)
// EBI_SDRAM_16BIT
#define AT91C_EBI_SDRAM_16BIT (0x20000000) // SDRAM on EBI Chip Select 1 base address
#define AT91C_EBI_SDRAM_16BIT_SIZE (0x02000000) // SDRAM on EBI Chip Select 1 size in byte (32768 Kbytes)
// EBI_SDRAM_32BIT
#define AT91C_EBI_SDRAM_32BIT (0x20000000) // SDRAM on EBI Chip Select 1 base address
#define AT91C_EBI_SDRAM_32BIT_SIZE (0x04000000) // SDRAM on EBI Chip Select 1 size in byte (65536 Kbytes)
// EBI_CS2
#define AT91C_EBI_CS2 (0x30000000) // EBI Chip Select 2 base address
#define AT91C_EBI_CS2_SIZE (0x10000000) // EBI Chip Select 2 size in byte (262144 Kbytes)
// EBI_CS3
#define AT91C_EBI_CS3 (0x40000000) // EBI Chip Select 3 base address
#define AT91C_EBI_CS3_SIZE (0x10000000) // EBI Chip Select 3 size in byte (262144 Kbytes)
// EBI_SM
#define AT91C_EBI_SM (0x40000000) // SmartMedia on Chip Select 3 base address
#define AT91C_EBI_SM_SIZE (0x10000000) // SmartMedia on Chip Select 3 size in byte (262144 Kbytes)
// EBI_CS4
#define AT91C_EBI_CS4 (0x50000000) // EBI Chip Select 4 base address
#define AT91C_EBI_CS4_SIZE (0x10000000) // EBI Chip Select 4 size in byte (262144 Kbytes)
// EBI_CF0
#define AT91C_EBI_CF0 (0x50000000) // CompactFlash 0 on Chip Select 4 base address
#define AT91C_EBI_CF0_SIZE (0x10000000) // CompactFlash 0 on Chip Select 4 size in byte (262144 Kbytes)
// EBI_CS5
#define AT91C_EBI_CS5 (0x60000000) // EBI Chip Select 5 base address
#define AT91C_EBI_CS5_SIZE (0x10000000) // EBI Chip Select 5 size in byte (262144 Kbytes)
// EBI_CF1
#define AT91C_EBI_CF1 (0x60000000) // CompactFlash 1 on Chip Select 5 base address
#define AT91C_EBI_CF1_SIZE (0x10000000) // CompactFlash 1 on Chip Select 5 size in byte (262144 Kbytes)
// EBI_CS6
#define AT91C_EBI_CS6 (0x70000000) // EBI Chip Select 6 base address
#define AT91C_EBI_CS6_SIZE (0x10000000) // EBI Chip Select 6 size in byte (262144 Kbytes)
// EBI_CS7
#define AT91C_EBI_CS7 (0x80000000) // EBI Chip Select 7 base address
#define AT91C_EBI_CS7_SIZE (0x10000000) // EBI Chip Select 7 size in byte (262144 Kbytes)
#endif
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe512/AT91SAM9XE512.h | C | oos | 306,025 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#include "ISR_Support.h"
/*
IAR startup file for AT91SAM9XE microcontrollers.
*/
MODULE ?cstartup
;; Forward declaration of sections.
SECTION IRQ_STACK:DATA:NOROOT(2)
SECTION CSTACK:DATA:NOROOT(3)
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#define __ASSEMBLY__
#include "board.h"
//------------------------------------------------------------------------------
// Definitions
//------------------------------------------------------------------------------
#define ARM_MODE_ABT 0x17
#define ARM_MODE_FIQ 0x11
#define ARM_MODE_IRQ 0x12
#define ARM_MODE_SVC 0x13
#define ARM_MODE_SYS 0x1F
#define I_BIT 0x80
#define F_BIT 0x40
//------------------------------------------------------------------------------
// Startup routine
//------------------------------------------------------------------------------
/*
Exception vectors
*/
SECTION .vectors:CODE:NOROOT(2)
PUBLIC resetVector
PUBLIC irqHandler
EXTERN Undefined_Handler
EXTERN vPortYieldProcessor
EXTERN Prefetch_Handler
EXTERN Abort_Handler
EXTERN FIQ_Handler
ARM
__iar_init$$done: ; The interrupt vector is not needed
; until after copy initialization is done
resetVector:
; All default exception handlers (except reset) are
; defined as weak symbol definitions.
; If a handler is defined by the application it will take precedence.
LDR pc, =resetHandler ; Reset
LDR pc, Undefined_Addr ; Undefined instructions
LDR pc, SWI_Addr ; Software interrupt (SWI/SVC)
LDR pc, Prefetch_Addr ; Prefetch abort
LDR pc, Abort_Addr ; Data abort
B . ; RESERVED
LDR pc, =irqHandler ; IRQ
LDR pc, FIQ_Addr ; FIQ
Undefined_Addr: DCD Undefined_Handler
SWI_Addr: DCD vPortYieldProcessor
Prefetch_Addr: DCD Prefetch_Handler
Abort_Addr: DCD Abort_Handler
FIQ_Addr: DCD FIQ_Handler
/*
Handles incoming interrupt requests by branching to the corresponding
handler, as defined in the AIC. Supports interrupt nesting.
*/
irqHandler:
portSAVE_CONTEXT
/* Write in the IVR to support Protect Mode */
LDR lr, =AT91C_BASE_AIC
LDR r0, [r14, #AIC_IVR]
STR lr, [r14, #AIC_IVR]
/* Branch to C portion of the interrupt handler */
MOV lr, pc
BX r0
/* Acknowledge interrupt */
LDR lr, =AT91C_BASE_AIC
STR lr, [r14, #AIC_EOICR]
portRESTORE_CONTEXT
/*
After a reset, execution starts here, the mode is ARM, supervisor
with interrupts disabled.
Initializes the chip and branches to the main() function.
*/
SECTION .cstartup:CODE:NOROOT(2)
PUBLIC resetHandler
EXTERN LowLevelInit
EXTERN ?main
REQUIRE resetVector
ARM
resetHandler:
/* Set pc to actual code location (i.e. not in remap zone) */
LDR pc, =label
/* Perform low-level initialization of the chip using LowLevelInit() */
label:
LDR r0, =LowLevelInit
LDR r4, =SFE(CSTACK)
MOV sp, r4
MOV lr, pc
BX r0
/* Set up the interrupt stack pointer. */
MSR cpsr_c, #ARM_MODE_IRQ | I_BIT | F_BIT ; Change the mode
LDR sp, =SFE(IRQ_STACK)
/* Set up the SVC stack pointer. */
MSR cpsr_c, #ARM_MODE_SVC | F_BIT ; Change the mode
LDR sp, =SFE(CSTACK)
/* Branch to main() */
LDR r0, =?main
MOV lr, pc
BX r0
/* Loop indefinitely when program is finished */
loop4:
B loop4
END
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board_cstartup_iar.s | Motorola 68K Assembly | oos | 5,791 |
// ----------------------------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ----------------------------------------------------------------------------
// Copyright (c) 2006, Atmel Corporation
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the disclaimer below.
//
// - Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the disclaimer below in the documentation and/or
// other materials provided with the distribution.
//
// Atmel's name may not be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ----------------------------------------------------------------------------
// File Name : AT91SAM9XE128.h
// Object : AT91SAM9XE128 definitions
// Generated : AT91 SW Application Group 02/13/2008 (18:26:05)
//
// CVS Reference : /AT91SAM9XE128.pl/1.3/Wed Jan 30 13:58:28 2008//
// CVS Reference : /SYS_SAM9260.pl/1.2/Wed Feb 13 13:29:23 2008//
// CVS Reference : /HMATRIX1_SAM9260.pl/1.7/Mon Apr 23 10:39:45 2007//
// CVS Reference : /CCR_SAM9260.pl/1.2/Mon Apr 16 10:47:39 2007//
// CVS Reference : /PMC_SAM9262.pl/1.4/Mon Mar 7 18:03:13 2005//
// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//
// CVS Reference : /HSDRAMC1_6100A.pl/1.2/Mon Aug 9 10:52:25 2004//
// CVS Reference : /HSMC3_6105A.pl/1.4/Tue Nov 16 09:16:23 2004//
// CVS Reference : /AIC_6075A.pl/1.1/Mon Jul 12 17:04:01 2004//
// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005//
// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005//
// CVS Reference : /RSTC_6098A.pl/1.3/Thu Nov 4 13:57:00 2004//
// CVS Reference : /SHDWC_6122A.pl/1.3/Wed Oct 6 14:16:58 2004//
// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004//
// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004//
// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004//
// CVS Reference : /EFC2_IGS036.pl/1.2/Fri Nov 10 10:47:53 2006//
// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005//
// CVS Reference : /MCI_6101E.pl/1.1/Fri Jun 3 13:20:23 2005//
// CVS Reference : /TWI_6061B.pl/1.2/Fri Aug 4 08:53:02 2006//
// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004//
// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
// CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005//
// CVS Reference : /UDP_6ept_puon.pl/1.1/Wed Aug 30 14:20:53 2006//
// CVS Reference : /UHP_6127A.pl/1.1/Wed Feb 23 16:03:17 2005//
// CVS Reference : /EBI_SAM9260.pl/1.1/Fri Sep 30 12:12:14 2005//
// CVS Reference : /HECC_6143A.pl/1.1/Wed Feb 9 17:16:57 2005//
// CVS Reference : /ISI_xxxxx.pl/1.3/Thu Mar 3 11:11:48 2005//
// ----------------------------------------------------------------------------
#ifndef AT91SAM9XE128_H
#define AT91SAM9XE128_H
#ifndef __ASSEMBLY__
typedef volatile unsigned int AT91_REG;// Hardware register definition
#define AT91_CAST(a) (a)
#else
#define AT91_CAST(a)
#endif
// *****************************************************************************
// SOFTWARE API DEFINITION FOR System Peripherals
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_SYS {
AT91_REG Reserved0[2560]; //
AT91_REG ECC_CR; // ECC reset register
AT91_REG ECC_MR; // ECC Page size register
AT91_REG ECC_SR; // ECC Status register
AT91_REG ECC_PR; // ECC Parity register
AT91_REG ECC_NPR; // ECC Parity N register
AT91_REG Reserved1[58]; //
AT91_REG ECC_VR; // ECC Version register
AT91_REG Reserved2[64]; //
AT91_REG SDRAMC_MR; // SDRAM Controller Mode Register
AT91_REG SDRAMC_TR; // SDRAM Controller Refresh Timer Register
AT91_REG SDRAMC_CR; // SDRAM Controller Configuration Register
AT91_REG SDRAMC_HSR; // SDRAM Controller High Speed Register
AT91_REG SDRAMC_LPR; // SDRAM Controller Low Power Register
AT91_REG SDRAMC_IER; // SDRAM Controller Interrupt Enable Register
AT91_REG SDRAMC_IDR; // SDRAM Controller Interrupt Disable Register
AT91_REG SDRAMC_IMR; // SDRAM Controller Interrupt Mask Register
AT91_REG SDRAMC_ISR; // SDRAM Controller Interrupt Mask Register
AT91_REG SDRAMC_MDR; // SDRAM Memory Device Register
AT91_REG Reserved3[118]; //
AT91_REG SMC_SETUP0; // Setup Register for CS 0
AT91_REG SMC_PULSE0; // Pulse Register for CS 0
AT91_REG SMC_CYCLE0; // Cycle Register for CS 0
AT91_REG SMC_CTRL0; // Control Register for CS 0
AT91_REG SMC_SETUP1; // Setup Register for CS 1
AT91_REG SMC_PULSE1; // Pulse Register for CS 1
AT91_REG SMC_CYCLE1; // Cycle Register for CS 1
AT91_REG SMC_CTRL1; // Control Register for CS 1
AT91_REG SMC_SETUP2; // Setup Register for CS 2
AT91_REG SMC_PULSE2; // Pulse Register for CS 2
AT91_REG SMC_CYCLE2; // Cycle Register for CS 2
AT91_REG SMC_CTRL2; // Control Register for CS 2
AT91_REG SMC_SETUP3; // Setup Register for CS 3
AT91_REG SMC_PULSE3; // Pulse Register for CS 3
AT91_REG SMC_CYCLE3; // Cycle Register for CS 3
AT91_REG SMC_CTRL3; // Control Register for CS 3
AT91_REG SMC_SETUP4; // Setup Register for CS 4
AT91_REG SMC_PULSE4; // Pulse Register for CS 4
AT91_REG SMC_CYCLE4; // Cycle Register for CS 4
AT91_REG SMC_CTRL4; // Control Register for CS 4
AT91_REG SMC_SETUP5; // Setup Register for CS 5
AT91_REG SMC_PULSE5; // Pulse Register for CS 5
AT91_REG SMC_CYCLE5; // Cycle Register for CS 5
AT91_REG SMC_CTRL5; // Control Register for CS 5
AT91_REG SMC_SETUP6; // Setup Register for CS 6
AT91_REG SMC_PULSE6; // Pulse Register for CS 6
AT91_REG SMC_CYCLE6; // Cycle Register for CS 6
AT91_REG SMC_CTRL6; // Control Register for CS 6
AT91_REG SMC_SETUP7; // Setup Register for CS 7
AT91_REG SMC_PULSE7; // Pulse Register for CS 7
AT91_REG SMC_CYCLE7; // Cycle Register for CS 7
AT91_REG SMC_CTRL7; // Control Register for CS 7
AT91_REG Reserved4[96]; //
AT91_REG MATRIX_MCFG0; // Master Configuration Register 0 (ram96k)
AT91_REG MATRIX_MCFG1; // Master Configuration Register 1 (rom)
AT91_REG MATRIX_MCFG2; // Master Configuration Register 2 (hperiphs)
AT91_REG MATRIX_MCFG3; // Master Configuration Register 3 (ebi)
AT91_REG MATRIX_MCFG4; // Master Configuration Register 4 (bridge)
AT91_REG MATRIX_MCFG5; // Master Configuration Register 5 (mailbox)
AT91_REG MATRIX_MCFG6; // Master Configuration Register 6 (ram16k)
AT91_REG MATRIX_MCFG7; // Master Configuration Register 7 (teak_prog)
AT91_REG Reserved5[8]; //
AT91_REG MATRIX_SCFG0; // Slave Configuration Register 0 (ram96k)
AT91_REG MATRIX_SCFG1; // Slave Configuration Register 1 (rom)
AT91_REG MATRIX_SCFG2; // Slave Configuration Register 2 (hperiphs)
AT91_REG MATRIX_SCFG3; // Slave Configuration Register 3 (ebi)
AT91_REG MATRIX_SCFG4; // Slave Configuration Register 4 (bridge)
AT91_REG Reserved6[11]; //
AT91_REG MATRIX_PRAS0; // PRAS0 (ram0)
AT91_REG MATRIX_PRBS0; // PRBS0 (ram0)
AT91_REG MATRIX_PRAS1; // PRAS1 (ram1)
AT91_REG MATRIX_PRBS1; // PRBS1 (ram1)
AT91_REG MATRIX_PRAS2; // PRAS2 (ram2)
AT91_REG MATRIX_PRBS2; // PRBS2 (ram2)
AT91_REG MATRIX_PRAS3; // PRAS3 : usb_dev_hs
AT91_REG MATRIX_PRBS3; // PRBS3 : usb_dev_hs
AT91_REG MATRIX_PRAS4; // PRAS4 : ebi
AT91_REG MATRIX_PRBS4; // PRBS4 : ebi
AT91_REG Reserved7[22]; //
AT91_REG MATRIX_MRCR; // Master Remp Control Register
AT91_REG Reserved8[6]; //
AT91_REG CCFG_EBICSA; // EBI Chip Select Assignement Register
AT91_REG Reserved9[3]; //
AT91_REG MATRIX_TEAKCFG; // Slave 7 (teak_prog) Special Function Register
AT91_REG Reserved10[51]; //
AT91_REG CCFG_MATRIXVERSION; // Version Register
AT91_REG AIC_SMR[32]; // Source Mode Register
AT91_REG AIC_SVR[32]; // Source Vector Register
AT91_REG AIC_IVR; // IRQ Vector Register
AT91_REG AIC_FVR; // FIQ Vector Register
AT91_REG AIC_ISR; // Interrupt Status Register
AT91_REG AIC_IPR; // Interrupt Pending Register
AT91_REG AIC_IMR; // Interrupt Mask Register
AT91_REG AIC_CISR; // Core Interrupt Status Register
AT91_REG Reserved11[2]; //
AT91_REG AIC_IECR; // Interrupt Enable Command Register
AT91_REG AIC_IDCR; // Interrupt Disable Command Register
AT91_REG AIC_ICCR; // Interrupt Clear Command Register
AT91_REG AIC_ISCR; // Interrupt Set Command Register
AT91_REG AIC_EOICR; // End of Interrupt Command Register
AT91_REG AIC_SPU; // Spurious Vector Register
AT91_REG AIC_DCR; // Debug Control Register (Protect)
AT91_REG Reserved12[1]; //
AT91_REG AIC_FFER; // Fast Forcing Enable Register
AT91_REG AIC_FFDR; // Fast Forcing Disable Register
AT91_REG AIC_FFSR; // Fast Forcing Status Register
AT91_REG Reserved13[45]; //
AT91_REG DBGU_CR; // Control Register
AT91_REG DBGU_MR; // Mode Register
AT91_REG DBGU_IER; // Interrupt Enable Register
AT91_REG DBGU_IDR; // Interrupt Disable Register
AT91_REG DBGU_IMR; // Interrupt Mask Register
AT91_REG DBGU_CSR; // Channel Status Register
AT91_REG DBGU_RHR; // Receiver Holding Register
AT91_REG DBGU_THR; // Transmitter Holding Register
AT91_REG DBGU_BRGR; // Baud Rate Generator Register
AT91_REG Reserved14[7]; //
AT91_REG DBGU_CIDR; // Chip ID Register
AT91_REG DBGU_EXID; // Chip ID Extension Register
AT91_REG DBGU_FNTR; // Force NTRST Register
AT91_REG Reserved15[45]; //
AT91_REG DBGU_RPR; // Receive Pointer Register
AT91_REG DBGU_RCR; // Receive Counter Register
AT91_REG DBGU_TPR; // Transmit Pointer Register
AT91_REG DBGU_TCR; // Transmit Counter Register
AT91_REG DBGU_RNPR; // Receive Next Pointer Register
AT91_REG DBGU_RNCR; // Receive Next Counter Register
AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
AT91_REG DBGU_TNCR; // Transmit Next Counter Register
AT91_REG DBGU_PTCR; // PDC Transfer Control Register
AT91_REG DBGU_PTSR; // PDC Transfer Status Register
AT91_REG Reserved16[54]; //
AT91_REG PIOA_PER; // PIO Enable Register
AT91_REG PIOA_PDR; // PIO Disable Register
AT91_REG PIOA_PSR; // PIO Status Register
AT91_REG Reserved17[1]; //
AT91_REG PIOA_OER; // Output Enable Register
AT91_REG PIOA_ODR; // Output Disable Registerr
AT91_REG PIOA_OSR; // Output Status Register
AT91_REG Reserved18[1]; //
AT91_REG PIOA_IFER; // Input Filter Enable Register
AT91_REG PIOA_IFDR; // Input Filter Disable Register
AT91_REG PIOA_IFSR; // Input Filter Status Register
AT91_REG Reserved19[1]; //
AT91_REG PIOA_SODR; // Set Output Data Register
AT91_REG PIOA_CODR; // Clear Output Data Register
AT91_REG PIOA_ODSR; // Output Data Status Register
AT91_REG PIOA_PDSR; // Pin Data Status Register
AT91_REG PIOA_IER; // Interrupt Enable Register
AT91_REG PIOA_IDR; // Interrupt Disable Register
AT91_REG PIOA_IMR; // Interrupt Mask Register
AT91_REG PIOA_ISR; // Interrupt Status Register
AT91_REG PIOA_MDER; // Multi-driver Enable Register
AT91_REG PIOA_MDDR; // Multi-driver Disable Register
AT91_REG PIOA_MDSR; // Multi-driver Status Register
AT91_REG Reserved20[1]; //
AT91_REG PIOA_PPUDR; // Pull-up Disable Register
AT91_REG PIOA_PPUER; // Pull-up Enable Register
AT91_REG PIOA_PPUSR; // Pull-up Status Register
AT91_REG Reserved21[1]; //
AT91_REG PIOA_ASR; // Select A Register
AT91_REG PIOA_BSR; // Select B Register
AT91_REG PIOA_ABSR; // AB Select Status Register
AT91_REG Reserved22[9]; //
AT91_REG PIOA_OWER; // Output Write Enable Register
AT91_REG PIOA_OWDR; // Output Write Disable Register
AT91_REG PIOA_OWSR; // Output Write Status Register
AT91_REG Reserved23[213]; //
AT91_REG PIOB_PER; // PIO Enable Register
AT91_REG PIOB_PDR; // PIO Disable Register
AT91_REG PIOB_PSR; // PIO Status Register
AT91_REG Reserved24[1]; //
AT91_REG PIOB_OER; // Output Enable Register
AT91_REG PIOB_ODR; // Output Disable Registerr
AT91_REG PIOB_OSR; // Output Status Register
AT91_REG Reserved25[1]; //
AT91_REG PIOB_IFER; // Input Filter Enable Register
AT91_REG PIOB_IFDR; // Input Filter Disable Register
AT91_REG PIOB_IFSR; // Input Filter Status Register
AT91_REG Reserved26[1]; //
AT91_REG PIOB_SODR; // Set Output Data Register
AT91_REG PIOB_CODR; // Clear Output Data Register
AT91_REG PIOB_ODSR; // Output Data Status Register
AT91_REG PIOB_PDSR; // Pin Data Status Register
AT91_REG PIOB_IER; // Interrupt Enable Register
AT91_REG PIOB_IDR; // Interrupt Disable Register
AT91_REG PIOB_IMR; // Interrupt Mask Register
AT91_REG PIOB_ISR; // Interrupt Status Register
AT91_REG PIOB_MDER; // Multi-driver Enable Register
AT91_REG PIOB_MDDR; // Multi-driver Disable Register
AT91_REG PIOB_MDSR; // Multi-driver Status Register
AT91_REG Reserved27[1]; //
AT91_REG PIOB_PPUDR; // Pull-up Disable Register
AT91_REG PIOB_PPUER; // Pull-up Enable Register
AT91_REG PIOB_PPUSR; // Pull-up Status Register
AT91_REG Reserved28[1]; //
AT91_REG PIOB_ASR; // Select A Register
AT91_REG PIOB_BSR; // Select B Register
AT91_REG PIOB_ABSR; // AB Select Status Register
AT91_REG Reserved29[9]; //
AT91_REG PIOB_OWER; // Output Write Enable Register
AT91_REG PIOB_OWDR; // Output Write Disable Register
AT91_REG PIOB_OWSR; // Output Write Status Register
AT91_REG Reserved30[85]; //
AT91_REG PIOC_PER; // PIO Enable Register
AT91_REG PIOC_PDR; // PIO Disable Register
AT91_REG PIOC_PSR; // PIO Status Register
AT91_REG Reserved31[1]; //
AT91_REG PIOC_OER; // Output Enable Register
AT91_REG PIOC_ODR; // Output Disable Registerr
AT91_REG PIOC_OSR; // Output Status Register
AT91_REG Reserved32[1]; //
AT91_REG PIOC_IFER; // Input Filter Enable Register
AT91_REG PIOC_IFDR; // Input Filter Disable Register
AT91_REG PIOC_IFSR; // Input Filter Status Register
AT91_REG Reserved33[1]; //
AT91_REG PIOC_SODR; // Set Output Data Register
AT91_REG PIOC_CODR; // Clear Output Data Register
AT91_REG PIOC_ODSR; // Output Data Status Register
AT91_REG PIOC_PDSR; // Pin Data Status Register
AT91_REG PIOC_IER; // Interrupt Enable Register
AT91_REG PIOC_IDR; // Interrupt Disable Register
AT91_REG PIOC_IMR; // Interrupt Mask Register
AT91_REG PIOC_ISR; // Interrupt Status Register
AT91_REG PIOC_MDER; // Multi-driver Enable Register
AT91_REG PIOC_MDDR; // Multi-driver Disable Register
AT91_REG PIOC_MDSR; // Multi-driver Status Register
AT91_REG Reserved34[1]; //
AT91_REG PIOC_PPUDR; // Pull-up Disable Register
AT91_REG PIOC_PPUER; // Pull-up Enable Register
AT91_REG PIOC_PPUSR; // Pull-up Status Register
AT91_REG Reserved35[1]; //
AT91_REG PIOC_ASR; // Select A Register
AT91_REG PIOC_BSR; // Select B Register
AT91_REG PIOC_ABSR; // AB Select Status Register
AT91_REG Reserved36[9]; //
AT91_REG PIOC_OWER; // Output Write Enable Register
AT91_REG PIOC_OWDR; // Output Write Disable Register
AT91_REG PIOC_OWSR; // Output Write Status Register
AT91_REG Reserved37[85]; //
AT91_REG PMC_SCER; // System Clock Enable Register
AT91_REG PMC_SCDR; // System Clock Disable Register
AT91_REG PMC_SCSR; // System Clock Status Register
AT91_REG Reserved38[1]; //
AT91_REG PMC_PCER; // Peripheral Clock Enable Register
AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
AT91_REG PMC_PCSR; // Peripheral Clock Status Register
AT91_REG Reserved39[1]; //
AT91_REG PMC_MOR; // Main Oscillator Register
AT91_REG PMC_MCFR; // Main Clock Frequency Register
AT91_REG PMC_PLLAR; // PLL A Register
AT91_REG PMC_PLLBR; // PLL B Register
AT91_REG PMC_MCKR; // Master Clock Register
AT91_REG Reserved40[3]; //
AT91_REG PMC_PCKR[8]; // Programmable Clock Register
AT91_REG PMC_IER; // Interrupt Enable Register
AT91_REG PMC_IDR; // Interrupt Disable Register
AT91_REG PMC_SR; // Status Register
AT91_REG PMC_IMR; // Interrupt Mask Register
AT91_REG Reserved41[36]; //
AT91_REG RSTC_RCR; // Reset Control Register
AT91_REG RSTC_RSR; // Reset Status Register
AT91_REG RSTC_RMR; // Reset Mode Register
AT91_REG Reserved42[1]; //
AT91_REG SHDWC_SHCR; // Shut Down Control Register
AT91_REG SHDWC_SHMR; // Shut Down Mode Register
AT91_REG SHDWC_SHSR; // Shut Down Status Register
AT91_REG Reserved43[1]; //
AT91_REG RTTC_RTMR; // Real-time Mode Register
AT91_REG RTTC_RTAR; // Real-time Alarm Register
AT91_REG RTTC_RTVR; // Real-time Value Register
AT91_REG RTTC_RTSR; // Real-time Status Register
AT91_REG PITC_PIMR; // Period Interval Mode Register
AT91_REG PITC_PISR; // Period Interval Status Register
AT91_REG PITC_PIVR; // Period Interval Value Register
AT91_REG PITC_PIIR; // Period Interval Image Register
AT91_REG WDTC_WDCR; // Watchdog Control Register
AT91_REG WDTC_WDMR; // Watchdog Mode Register
AT91_REG WDTC_WDSR; // Watchdog Status Register
AT91_REG Reserved44[1]; //
AT91_REG SYS_GPBR[4]; // General Purpose Register
} AT91S_SYS, *AT91PS_SYS;
#else
#define SYS_GPBR (AT91_CAST(AT91_REG *) 0x00003D50) // (SYS_GPBR) General Purpose Register
#endif
// -------- GPBR : (SYS Offset: 0x3d50) GPBR General Purpose Register --------
#define AT91C_GPBR_GPRV (0x0 << 0) // (SYS) General Purpose Register Value
// *****************************************************************************
// SOFTWARE API DEFINITION FOR External Bus Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_EBI {
AT91_REG EBI_DUMMY; // Dummy register - Do not use
} AT91S_EBI, *AT91PS_EBI;
#else
#define EBI_DUMMY (AT91_CAST(AT91_REG *) 0x00000000) // (EBI_DUMMY) Dummy register - Do not use
#endif
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Error Correction Code controller
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_ECC {
AT91_REG ECC_CR; // ECC reset register
AT91_REG ECC_MR; // ECC Page size register
AT91_REG ECC_SR; // ECC Status register
AT91_REG ECC_PR; // ECC Parity register
AT91_REG ECC_NPR; // ECC Parity N register
AT91_REG Reserved0[58]; //
AT91_REG ECC_VR; // ECC Version register
} AT91S_ECC, *AT91PS_ECC;
#else
#define ECC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ECC_CR) ECC reset register
#define ECC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ECC_MR) ECC Page size register
#define ECC_SR (AT91_CAST(AT91_REG *) 0x00000008) // (ECC_SR) ECC Status register
#define ECC_PR (AT91_CAST(AT91_REG *) 0x0000000C) // (ECC_PR) ECC Parity register
#define ECC_NPR (AT91_CAST(AT91_REG *) 0x00000010) // (ECC_NPR) ECC Parity N register
#define ECC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (ECC_VR) ECC Version register
#endif
// -------- ECC_CR : (ECC Offset: 0x0) ECC reset register --------
#define AT91C_ECC_RST (0x1 << 0) // (ECC) ECC reset parity
// -------- ECC_MR : (ECC Offset: 0x4) ECC page size register --------
#define AT91C_ECC_PAGE_SIZE (0x3 << 0) // (ECC) Nand Flash page size
// -------- ECC_SR : (ECC Offset: 0x8) ECC status register --------
#define AT91C_ECC_RECERR (0x1 << 0) // (ECC) ECC error
#define AT91C_ECC_ECCERR (0x1 << 1) // (ECC) ECC single error
#define AT91C_ECC_MULERR (0x1 << 2) // (ECC) ECC_MULERR
// -------- ECC_PR : (ECC Offset: 0xc) ECC parity register --------
#define AT91C_ECC_BITADDR (0xF << 0) // (ECC) Bit address error
#define AT91C_ECC_WORDADDR (0xFFF << 4) // (ECC) address of the failing bit
// -------- ECC_NPR : (ECC Offset: 0x10) ECC N parity register --------
#define AT91C_ECC_NPARITY (0xFFFF << 0) // (ECC) ECC parity N
// -------- ECC_VR : (ECC Offset: 0xfc) ECC version register --------
#define AT91C_ECC_VR (0xF << 0) // (ECC) ECC version register
// *****************************************************************************
// SOFTWARE API DEFINITION FOR SDRAM Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_SDRAMC {
AT91_REG SDRAMC_MR; // SDRAM Controller Mode Register
AT91_REG SDRAMC_TR; // SDRAM Controller Refresh Timer Register
AT91_REG SDRAMC_CR; // SDRAM Controller Configuration Register
AT91_REG SDRAMC_HSR; // SDRAM Controller High Speed Register
AT91_REG SDRAMC_LPR; // SDRAM Controller Low Power Register
AT91_REG SDRAMC_IER; // SDRAM Controller Interrupt Enable Register
AT91_REG SDRAMC_IDR; // SDRAM Controller Interrupt Disable Register
AT91_REG SDRAMC_IMR; // SDRAM Controller Interrupt Mask Register
AT91_REG SDRAMC_ISR; // SDRAM Controller Interrupt Mask Register
AT91_REG SDRAMC_MDR; // SDRAM Memory Device Register
} AT91S_SDRAMC, *AT91PS_SDRAMC;
#else
#define SDRAMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (SDRAMC_MR) SDRAM Controller Mode Register
#define SDRAMC_TR (AT91_CAST(AT91_REG *) 0x00000004) // (SDRAMC_TR) SDRAM Controller Refresh Timer Register
#define SDRAMC_CR (AT91_CAST(AT91_REG *) 0x00000008) // (SDRAMC_CR) SDRAM Controller Configuration Register
#define SDRAMC_HSR (AT91_CAST(AT91_REG *) 0x0000000C) // (SDRAMC_HSR) SDRAM Controller High Speed Register
#define SDRAMC_LPR (AT91_CAST(AT91_REG *) 0x00000010) // (SDRAMC_LPR) SDRAM Controller Low Power Register
#define SDRAMC_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SDRAMC_IER) SDRAM Controller Interrupt Enable Register
#define SDRAMC_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SDRAMC_IDR) SDRAM Controller Interrupt Disable Register
#define SDRAMC_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SDRAMC_IMR) SDRAM Controller Interrupt Mask Register
#define SDRAMC_ISR (AT91_CAST(AT91_REG *) 0x00000020) // (SDRAMC_ISR) SDRAM Controller Interrupt Mask Register
#define SDRAMC_MDR (AT91_CAST(AT91_REG *) 0x00000024) // (SDRAMC_MDR) SDRAM Memory Device Register
#endif
// -------- SDRAMC_MR : (SDRAMC Offset: 0x0) SDRAM Controller Mode Register --------
#define AT91C_SDRAMC_MODE (0xF << 0) // (SDRAMC) Mode
#define AT91C_SDRAMC_MODE_NORMAL_CMD (0x0) // (SDRAMC) Normal Mode
#define AT91C_SDRAMC_MODE_NOP_CMD (0x1) // (SDRAMC) Issue a NOP Command at every access
#define AT91C_SDRAMC_MODE_PRCGALL_CMD (0x2) // (SDRAMC) Issue a All Banks Precharge Command at every access
#define AT91C_SDRAMC_MODE_LMR_CMD (0x3) // (SDRAMC) Issue a Load Mode Register at every access
#define AT91C_SDRAMC_MODE_RFSH_CMD (0x4) // (SDRAMC) Issue a Refresh
#define AT91C_SDRAMC_MODE_EXT_LMR_CMD (0x5) // (SDRAMC) Issue an Extended Load Mode Register
#define AT91C_SDRAMC_MODE_DEEP_CMD (0x6) // (SDRAMC) Enter Deep Power Mode
// -------- SDRAMC_TR : (SDRAMC Offset: 0x4) SDRAMC Refresh Timer Register --------
#define AT91C_SDRAMC_COUNT (0xFFF << 0) // (SDRAMC) Refresh Counter
// -------- SDRAMC_CR : (SDRAMC Offset: 0x8) SDRAM Configuration Register --------
#define AT91C_SDRAMC_NC (0x3 << 0) // (SDRAMC) Number of Column Bits
#define AT91C_SDRAMC_NC_8 (0x0) // (SDRAMC) 8 Bits
#define AT91C_SDRAMC_NC_9 (0x1) // (SDRAMC) 9 Bits
#define AT91C_SDRAMC_NC_10 (0x2) // (SDRAMC) 10 Bits
#define AT91C_SDRAMC_NC_11 (0x3) // (SDRAMC) 11 Bits
#define AT91C_SDRAMC_NR (0x3 << 2) // (SDRAMC) Number of Row Bits
#define AT91C_SDRAMC_NR_11 (0x0 << 2) // (SDRAMC) 11 Bits
#define AT91C_SDRAMC_NR_12 (0x1 << 2) // (SDRAMC) 12 Bits
#define AT91C_SDRAMC_NR_13 (0x2 << 2) // (SDRAMC) 13 Bits
#define AT91C_SDRAMC_NB (0x1 << 4) // (SDRAMC) Number of Banks
#define AT91C_SDRAMC_NB_2_BANKS (0x0 << 4) // (SDRAMC) 2 banks
#define AT91C_SDRAMC_NB_4_BANKS (0x1 << 4) // (SDRAMC) 4 banks
#define AT91C_SDRAMC_CAS (0x3 << 5) // (SDRAMC) CAS Latency
#define AT91C_SDRAMC_CAS_2 (0x2 << 5) // (SDRAMC) 2 cycles
#define AT91C_SDRAMC_CAS_3 (0x3 << 5) // (SDRAMC) 3 cycles
#define AT91C_SDRAMC_DBW (0x1 << 7) // (SDRAMC) Data Bus Width
#define AT91C_SDRAMC_DBW_32_BITS (0x0 << 7) // (SDRAMC) 32 Bits datas bus
#define AT91C_SDRAMC_DBW_16_BITS (0x1 << 7) // (SDRAMC) 16 Bits datas bus
#define AT91C_SDRAMC_TWR (0xF << 8) // (SDRAMC) Number of Write Recovery Time Cycles
#define AT91C_SDRAMC_TWR_0 (0x0 << 8) // (SDRAMC) Value : 0
#define AT91C_SDRAMC_TWR_1 (0x1 << 8) // (SDRAMC) Value : 1
#define AT91C_SDRAMC_TWR_2 (0x2 << 8) // (SDRAMC) Value : 2
#define AT91C_SDRAMC_TWR_3 (0x3 << 8) // (SDRAMC) Value : 3
#define AT91C_SDRAMC_TWR_4 (0x4 << 8) // (SDRAMC) Value : 4
#define AT91C_SDRAMC_TWR_5 (0x5 << 8) // (SDRAMC) Value : 5
#define AT91C_SDRAMC_TWR_6 (0x6 << 8) // (SDRAMC) Value : 6
#define AT91C_SDRAMC_TWR_7 (0x7 << 8) // (SDRAMC) Value : 7
#define AT91C_SDRAMC_TWR_8 (0x8 << 8) // (SDRAMC) Value : 8
#define AT91C_SDRAMC_TWR_9 (0x9 << 8) // (SDRAMC) Value : 9
#define AT91C_SDRAMC_TWR_10 (0xA << 8) // (SDRAMC) Value : 10
#define AT91C_SDRAMC_TWR_11 (0xB << 8) // (SDRAMC) Value : 11
#define AT91C_SDRAMC_TWR_12 (0xC << 8) // (SDRAMC) Value : 12
#define AT91C_SDRAMC_TWR_13 (0xD << 8) // (SDRAMC) Value : 13
#define AT91C_SDRAMC_TWR_14 (0xE << 8) // (SDRAMC) Value : 14
#define AT91C_SDRAMC_TWR_15 (0xF << 8) // (SDRAMC) Value : 15
#define AT91C_SDRAMC_TRC (0xF << 12) // (SDRAMC) Number of RAS Cycle Time Cycles
#define AT91C_SDRAMC_TRC_0 (0x0 << 12) // (SDRAMC) Value : 0
#define AT91C_SDRAMC_TRC_1 (0x1 << 12) // (SDRAMC) Value : 1
#define AT91C_SDRAMC_TRC_2 (0x2 << 12) // (SDRAMC) Value : 2
#define AT91C_SDRAMC_TRC_3 (0x3 << 12) // (SDRAMC) Value : 3
#define AT91C_SDRAMC_TRC_4 (0x4 << 12) // (SDRAMC) Value : 4
#define AT91C_SDRAMC_TRC_5 (0x5 << 12) // (SDRAMC) Value : 5
#define AT91C_SDRAMC_TRC_6 (0x6 << 12) // (SDRAMC) Value : 6
#define AT91C_SDRAMC_TRC_7 (0x7 << 12) // (SDRAMC) Value : 7
#define AT91C_SDRAMC_TRC_8 (0x8 << 12) // (SDRAMC) Value : 8
#define AT91C_SDRAMC_TRC_9 (0x9 << 12) // (SDRAMC) Value : 9
#define AT91C_SDRAMC_TRC_10 (0xA << 12) // (SDRAMC) Value : 10
#define AT91C_SDRAMC_TRC_11 (0xB << 12) // (SDRAMC) Value : 11
#define AT91C_SDRAMC_TRC_12 (0xC << 12) // (SDRAMC) Value : 12
#define AT91C_SDRAMC_TRC_13 (0xD << 12) // (SDRAMC) Value : 13
#define AT91C_SDRAMC_TRC_14 (0xE << 12) // (SDRAMC) Value : 14
#define AT91C_SDRAMC_TRC_15 (0xF << 12) // (SDRAMC) Value : 15
#define AT91C_SDRAMC_TRP (0xF << 16) // (SDRAMC) Number of RAS Precharge Time Cycles
#define AT91C_SDRAMC_TRP_0 (0x0 << 16) // (SDRAMC) Value : 0
#define AT91C_SDRAMC_TRP_1 (0x1 << 16) // (SDRAMC) Value : 1
#define AT91C_SDRAMC_TRP_2 (0x2 << 16) // (SDRAMC) Value : 2
#define AT91C_SDRAMC_TRP_3 (0x3 << 16) // (SDRAMC) Value : 3
#define AT91C_SDRAMC_TRP_4 (0x4 << 16) // (SDRAMC) Value : 4
#define AT91C_SDRAMC_TRP_5 (0x5 << 16) // (SDRAMC) Value : 5
#define AT91C_SDRAMC_TRP_6 (0x6 << 16) // (SDRAMC) Value : 6
#define AT91C_SDRAMC_TRP_7 (0x7 << 16) // (SDRAMC) Value : 7
#define AT91C_SDRAMC_TRP_8 (0x8 << 16) // (SDRAMC) Value : 8
#define AT91C_SDRAMC_TRP_9 (0x9 << 16) // (SDRAMC) Value : 9
#define AT91C_SDRAMC_TRP_10 (0xA << 16) // (SDRAMC) Value : 10
#define AT91C_SDRAMC_TRP_11 (0xB << 16) // (SDRAMC) Value : 11
#define AT91C_SDRAMC_TRP_12 (0xC << 16) // (SDRAMC) Value : 12
#define AT91C_SDRAMC_TRP_13 (0xD << 16) // (SDRAMC) Value : 13
#define AT91C_SDRAMC_TRP_14 (0xE << 16) // (SDRAMC) Value : 14
#define AT91C_SDRAMC_TRP_15 (0xF << 16) // (SDRAMC) Value : 15
#define AT91C_SDRAMC_TRCD (0xF << 20) // (SDRAMC) Number of RAS to CAS Delay Cycles
#define AT91C_SDRAMC_TRCD_0 (0x0 << 20) // (SDRAMC) Value : 0
#define AT91C_SDRAMC_TRCD_1 (0x1 << 20) // (SDRAMC) Value : 1
#define AT91C_SDRAMC_TRCD_2 (0x2 << 20) // (SDRAMC) Value : 2
#define AT91C_SDRAMC_TRCD_3 (0x3 << 20) // (SDRAMC) Value : 3
#define AT91C_SDRAMC_TRCD_4 (0x4 << 20) // (SDRAMC) Value : 4
#define AT91C_SDRAMC_TRCD_5 (0x5 << 20) // (SDRAMC) Value : 5
#define AT91C_SDRAMC_TRCD_6 (0x6 << 20) // (SDRAMC) Value : 6
#define AT91C_SDRAMC_TRCD_7 (0x7 << 20) // (SDRAMC) Value : 7
#define AT91C_SDRAMC_TRCD_8 (0x8 << 20) // (SDRAMC) Value : 8
#define AT91C_SDRAMC_TRCD_9 (0x9 << 20) // (SDRAMC) Value : 9
#define AT91C_SDRAMC_TRCD_10 (0xA << 20) // (SDRAMC) Value : 10
#define AT91C_SDRAMC_TRCD_11 (0xB << 20) // (SDRAMC) Value : 11
#define AT91C_SDRAMC_TRCD_12 (0xC << 20) // (SDRAMC) Value : 12
#define AT91C_SDRAMC_TRCD_13 (0xD << 20) // (SDRAMC) Value : 13
#define AT91C_SDRAMC_TRCD_14 (0xE << 20) // (SDRAMC) Value : 14
#define AT91C_SDRAMC_TRCD_15 (0xF << 20) // (SDRAMC) Value : 15
#define AT91C_SDRAMC_TRAS (0xF << 24) // (SDRAMC) Number of RAS Active Time Cycles
#define AT91C_SDRAMC_TRAS_0 (0x0 << 24) // (SDRAMC) Value : 0
#define AT91C_SDRAMC_TRAS_1 (0x1 << 24) // (SDRAMC) Value : 1
#define AT91C_SDRAMC_TRAS_2 (0x2 << 24) // (SDRAMC) Value : 2
#define AT91C_SDRAMC_TRAS_3 (0x3 << 24) // (SDRAMC) Value : 3
#define AT91C_SDRAMC_TRAS_4 (0x4 << 24) // (SDRAMC) Value : 4
#define AT91C_SDRAMC_TRAS_5 (0x5 << 24) // (SDRAMC) Value : 5
#define AT91C_SDRAMC_TRAS_6 (0x6 << 24) // (SDRAMC) Value : 6
#define AT91C_SDRAMC_TRAS_7 (0x7 << 24) // (SDRAMC) Value : 7
#define AT91C_SDRAMC_TRAS_8 (0x8 << 24) // (SDRAMC) Value : 8
#define AT91C_SDRAMC_TRAS_9 (0x9 << 24) // (SDRAMC) Value : 9
#define AT91C_SDRAMC_TRAS_10 (0xA << 24) // (SDRAMC) Value : 10
#define AT91C_SDRAMC_TRAS_11 (0xB << 24) // (SDRAMC) Value : 11
#define AT91C_SDRAMC_TRAS_12 (0xC << 24) // (SDRAMC) Value : 12
#define AT91C_SDRAMC_TRAS_13 (0xD << 24) // (SDRAMC) Value : 13
#define AT91C_SDRAMC_TRAS_14 (0xE << 24) // (SDRAMC) Value : 14
#define AT91C_SDRAMC_TRAS_15 (0xF << 24) // (SDRAMC) Value : 15
#define AT91C_SDRAMC_TXSR (0xF << 28) // (SDRAMC) Number of Command Recovery Time Cycles
#define AT91C_SDRAMC_TXSR_0 (0x0 << 28) // (SDRAMC) Value : 0
#define AT91C_SDRAMC_TXSR_1 (0x1 << 28) // (SDRAMC) Value : 1
#define AT91C_SDRAMC_TXSR_2 (0x2 << 28) // (SDRAMC) Value : 2
#define AT91C_SDRAMC_TXSR_3 (0x3 << 28) // (SDRAMC) Value : 3
#define AT91C_SDRAMC_TXSR_4 (0x4 << 28) // (SDRAMC) Value : 4
#define AT91C_SDRAMC_TXSR_5 (0x5 << 28) // (SDRAMC) Value : 5
#define AT91C_SDRAMC_TXSR_6 (0x6 << 28) // (SDRAMC) Value : 6
#define AT91C_SDRAMC_TXSR_7 (0x7 << 28) // (SDRAMC) Value : 7
#define AT91C_SDRAMC_TXSR_8 (0x8 << 28) // (SDRAMC) Value : 8
#define AT91C_SDRAMC_TXSR_9 (0x9 << 28) // (SDRAMC) Value : 9
#define AT91C_SDRAMC_TXSR_10 (0xA << 28) // (SDRAMC) Value : 10
#define AT91C_SDRAMC_TXSR_11 (0xB << 28) // (SDRAMC) Value : 11
#define AT91C_SDRAMC_TXSR_12 (0xC << 28) // (SDRAMC) Value : 12
#define AT91C_SDRAMC_TXSR_13 (0xD << 28) // (SDRAMC) Value : 13
#define AT91C_SDRAMC_TXSR_14 (0xE << 28) // (SDRAMC) Value : 14
#define AT91C_SDRAMC_TXSR_15 (0xF << 28) // (SDRAMC) Value : 15
// -------- SDRAMC_HSR : (SDRAMC Offset: 0xc) SDRAM Controller High Speed Register --------
#define AT91C_SDRAMC_DA (0x1 << 0) // (SDRAMC) Decode Cycle Enable Bit
#define AT91C_SDRAMC_DA_DISABLE (0x0) // (SDRAMC) Disable Decode Cycle
#define AT91C_SDRAMC_DA_ENABLE (0x1) // (SDRAMC) Enable Decode Cycle
// -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAM Controller Low-power Register --------
#define AT91C_SDRAMC_LPCB (0x3 << 0) // (SDRAMC) Low-power Configurations
#define AT91C_SDRAMC_LPCB_DISABLE (0x0) // (SDRAMC) Disable Low Power Features
#define AT91C_SDRAMC_LPCB_SELF_REFRESH (0x1) // (SDRAMC) Enable SELF_REFRESH
#define AT91C_SDRAMC_LPCB_POWER_DOWN (0x2) // (SDRAMC) Enable POWER_DOWN
#define AT91C_SDRAMC_LPCB_DEEP_POWER_DOWN (0x3) // (SDRAMC) Enable DEEP_POWER_DOWN
#define AT91C_SDRAMC_PASR (0x7 << 4) // (SDRAMC) Partial Array Self Refresh (only for Low Power SDRAM)
#define AT91C_SDRAMC_TCSR (0x3 << 8) // (SDRAMC) Temperature Compensated Self Refresh (only for Low Power SDRAM)
#define AT91C_SDRAMC_DS (0x3 << 10) // (SDRAMC) Drive Strenght (only for Low Power SDRAM)
#define AT91C_SDRAMC_TIMEOUT (0x3 << 12) // (SDRAMC) Time to define when Low Power Mode is enabled
#define AT91C_SDRAMC_TIMEOUT_0_CLK_CYCLES (0x0 << 12) // (SDRAMC) Activate SDRAM Low Power Mode Immediately
#define AT91C_SDRAMC_TIMEOUT_64_CLK_CYCLES (0x1 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer
#define AT91C_SDRAMC_TIMEOUT_128_CLK_CYCLES (0x2 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer
// -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAM Controller Interrupt Enable Register --------
#define AT91C_SDRAMC_RES (0x1 << 0) // (SDRAMC) Refresh Error Status
// -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAM Controller Interrupt Disable Register --------
// -------- SDRAMC_IMR : (SDRAMC Offset: 0x1c) SDRAM Controller Interrupt Mask Register --------
// -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAM Controller Interrupt Status Register --------
// -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAM Controller Memory Device Register --------
#define AT91C_SDRAMC_MD (0x3 << 0) // (SDRAMC) Memory Device Type
#define AT91C_SDRAMC_MD_SDRAM (0x0) // (SDRAMC) SDRAM Mode
#define AT91C_SDRAMC_MD_LOW_POWER_SDRAM (0x1) // (SDRAMC) SDRAM Low Power Mode
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Static Memory Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_SMC {
AT91_REG SMC_SETUP0; // Setup Register for CS 0
AT91_REG SMC_PULSE0; // Pulse Register for CS 0
AT91_REG SMC_CYCLE0; // Cycle Register for CS 0
AT91_REG SMC_CTRL0; // Control Register for CS 0
AT91_REG SMC_SETUP1; // Setup Register for CS 1
AT91_REG SMC_PULSE1; // Pulse Register for CS 1
AT91_REG SMC_CYCLE1; // Cycle Register for CS 1
AT91_REG SMC_CTRL1; // Control Register for CS 1
AT91_REG SMC_SETUP2; // Setup Register for CS 2
AT91_REG SMC_PULSE2; // Pulse Register for CS 2
AT91_REG SMC_CYCLE2; // Cycle Register for CS 2
AT91_REG SMC_CTRL2; // Control Register for CS 2
AT91_REG SMC_SETUP3; // Setup Register for CS 3
AT91_REG SMC_PULSE3; // Pulse Register for CS 3
AT91_REG SMC_CYCLE3; // Cycle Register for CS 3
AT91_REG SMC_CTRL3; // Control Register for CS 3
AT91_REG SMC_SETUP4; // Setup Register for CS 4
AT91_REG SMC_PULSE4; // Pulse Register for CS 4
AT91_REG SMC_CYCLE4; // Cycle Register for CS 4
AT91_REG SMC_CTRL4; // Control Register for CS 4
AT91_REG SMC_SETUP5; // Setup Register for CS 5
AT91_REG SMC_PULSE5; // Pulse Register for CS 5
AT91_REG SMC_CYCLE5; // Cycle Register for CS 5
AT91_REG SMC_CTRL5; // Control Register for CS 5
AT91_REG SMC_SETUP6; // Setup Register for CS 6
AT91_REG SMC_PULSE6; // Pulse Register for CS 6
AT91_REG SMC_CYCLE6; // Cycle Register for CS 6
AT91_REG SMC_CTRL6; // Control Register for CS 6
AT91_REG SMC_SETUP7; // Setup Register for CS 7
AT91_REG SMC_PULSE7; // Pulse Register for CS 7
AT91_REG SMC_CYCLE7; // Cycle Register for CS 7
AT91_REG SMC_CTRL7; // Control Register for CS 7
} AT91S_SMC, *AT91PS_SMC;
#else
#define SETUP0 (AT91_CAST(AT91_REG *) 0x00000000) // (SETUP0) Setup Register for CS 0
#define PULSE0 (AT91_CAST(AT91_REG *) 0x00000004) // (PULSE0) Pulse Register for CS 0
#define CYCLE0 (AT91_CAST(AT91_REG *) 0x00000008) // (CYCLE0) Cycle Register for CS 0
#define CTRL0 (AT91_CAST(AT91_REG *) 0x0000000C) // (CTRL0) Control Register for CS 0
#define SETUP1 (AT91_CAST(AT91_REG *) 0x00000010) // (SETUP1) Setup Register for CS 1
#define PULSE1 (AT91_CAST(AT91_REG *) 0x00000014) // (PULSE1) Pulse Register for CS 1
#define CYCLE1 (AT91_CAST(AT91_REG *) 0x00000018) // (CYCLE1) Cycle Register for CS 1
#define CTRL1 (AT91_CAST(AT91_REG *) 0x0000001C) // (CTRL1) Control Register for CS 1
#define SETUP2 (AT91_CAST(AT91_REG *) 0x00000020) // (SETUP2) Setup Register for CS 2
#define PULSE2 (AT91_CAST(AT91_REG *) 0x00000024) // (PULSE2) Pulse Register for CS 2
#define CYCLE2 (AT91_CAST(AT91_REG *) 0x00000028) // (CYCLE2) Cycle Register for CS 2
#define CTRL2 (AT91_CAST(AT91_REG *) 0x0000002C) // (CTRL2) Control Register for CS 2
#define SETUP3 (AT91_CAST(AT91_REG *) 0x00000030) // (SETUP3) Setup Register for CS 3
#define PULSE3 (AT91_CAST(AT91_REG *) 0x00000034) // (PULSE3) Pulse Register for CS 3
#define CYCLE3 (AT91_CAST(AT91_REG *) 0x00000038) // (CYCLE3) Cycle Register for CS 3
#define CTRL3 (AT91_CAST(AT91_REG *) 0x0000003C) // (CTRL3) Control Register for CS 3
#define SETUP4 (AT91_CAST(AT91_REG *) 0x00000040) // (SETUP4) Setup Register for CS 4
#define PULSE4 (AT91_CAST(AT91_REG *) 0x00000044) // (PULSE4) Pulse Register for CS 4
#define CYCLE4 (AT91_CAST(AT91_REG *) 0x00000048) // (CYCLE4) Cycle Register for CS 4
#define CTRL4 (AT91_CAST(AT91_REG *) 0x0000004C) // (CTRL4) Control Register for CS 4
#define SETUP5 (AT91_CAST(AT91_REG *) 0x00000050) // (SETUP5) Setup Register for CS 5
#define PULSE5 (AT91_CAST(AT91_REG *) 0x00000054) // (PULSE5) Pulse Register for CS 5
#define CYCLE5 (AT91_CAST(AT91_REG *) 0x00000058) // (CYCLE5) Cycle Register for CS 5
#define CTRL5 (AT91_CAST(AT91_REG *) 0x0000005C) // (CTRL5) Control Register for CS 5
#define SETUP6 (AT91_CAST(AT91_REG *) 0x00000060) // (SETUP6) Setup Register for CS 6
#define PULSE6 (AT91_CAST(AT91_REG *) 0x00000064) // (PULSE6) Pulse Register for CS 6
#define CYCLE6 (AT91_CAST(AT91_REG *) 0x00000068) // (CYCLE6) Cycle Register for CS 6
#define CTRL6 (AT91_CAST(AT91_REG *) 0x0000006C) // (CTRL6) Control Register for CS 6
#define SETUP7 (AT91_CAST(AT91_REG *) 0x00000070) // (SETUP7) Setup Register for CS 7
#define PULSE7 (AT91_CAST(AT91_REG *) 0x00000074) // (PULSE7) Pulse Register for CS 7
#define CYCLE7 (AT91_CAST(AT91_REG *) 0x00000078) // (CYCLE7) Cycle Register for CS 7
#define CTRL7 (AT91_CAST(AT91_REG *) 0x0000007C) // (CTRL7) Control Register for CS 7
#endif
// -------- SMC_SETUP : (SMC Offset: 0x0) Setup Register for CS x --------
#define AT91C_SMC_NWESETUP (0x3F << 0) // (SMC) NWE Setup Length
#define AT91C_SMC_NCSSETUPWR (0x3F << 8) // (SMC) NCS Setup Length in WRite Access
#define AT91C_SMC_NRDSETUP (0x3F << 16) // (SMC) NRD Setup Length
#define AT91C_SMC_NCSSETUPRD (0x3F << 24) // (SMC) NCS Setup Length in ReaD Access
// -------- SMC_PULSE : (SMC Offset: 0x4) Pulse Register for CS x --------
#define AT91C_SMC_NWEPULSE (0x7F << 0) // (SMC) NWE Pulse Length
#define AT91C_SMC_NCSPULSEWR (0x7F << 8) // (SMC) NCS Pulse Length in WRite Access
#define AT91C_SMC_NRDPULSE (0x7F << 16) // (SMC) NRD Pulse Length
#define AT91C_SMC_NCSPULSERD (0x7F << 24) // (SMC) NCS Pulse Length in ReaD Access
// -------- SMC_CYC : (SMC Offset: 0x8) Cycle Register for CS x --------
#define AT91C_SMC_NWECYCLE (0x1FF << 0) // (SMC) Total Write Cycle Length
#define AT91C_SMC_NRDCYCLE (0x1FF << 16) // (SMC) Total Read Cycle Length
// -------- SMC_CTRL : (SMC Offset: 0xc) Control Register for CS x --------
#define AT91C_SMC_READMODE (0x1 << 0) // (SMC) Read Mode
#define AT91C_SMC_WRITEMODE (0x1 << 1) // (SMC) Write Mode
#define AT91C_SMC_NWAITM (0x3 << 4) // (SMC) NWAIT Mode
#define AT91C_SMC_NWAITM_NWAIT_DISABLE (0x0 << 4) // (SMC) External NWAIT disabled.
#define AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN (0x2 << 4) // (SMC) External NWAIT enabled in frozen mode.
#define AT91C_SMC_NWAITM_NWAIT_ENABLE_READY (0x3 << 4) // (SMC) External NWAIT enabled in ready mode.
#define AT91C_SMC_BAT (0x1 << 8) // (SMC) Byte Access Type
#define AT91C_SMC_BAT_BYTE_SELECT (0x0 << 8) // (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.
#define AT91C_SMC_BAT_BYTE_WRITE (0x1 << 8) // (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.
#define AT91C_SMC_DBW (0x3 << 12) // (SMC) Data Bus Width
#define AT91C_SMC_DBW_WIDTH_EIGTH_BITS (0x0 << 12) // (SMC) 8 bits.
#define AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS (0x1 << 12) // (SMC) 16 bits.
#define AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) // (SMC) 32 bits.
#define AT91C_SMC_TDF (0xF << 16) // (SMC) Data Float Time.
#define AT91C_SMC_TDFEN (0x1 << 20) // (SMC) TDF Enabled.
#define AT91C_SMC_PMEN (0x1 << 24) // (SMC) Page Mode Enabled.
#define AT91C_SMC_PS (0x3 << 28) // (SMC) Page Size
#define AT91C_SMC_PS_SIZE_FOUR_BYTES (0x0 << 28) // (SMC) 4 bytes.
#define AT91C_SMC_PS_SIZE_EIGHT_BYTES (0x1 << 28) // (SMC) 8 bytes.
#define AT91C_SMC_PS_SIZE_SIXTEEN_BYTES (0x2 << 28) // (SMC) 16 bytes.
#define AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) // (SMC) 32 bytes.
// -------- SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR AHB Matrix Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_MATRIX {
AT91_REG MATRIX_MCFG0; // Master Configuration Register 0 (ram96k)
AT91_REG MATRIX_MCFG1; // Master Configuration Register 1 (rom)
AT91_REG MATRIX_MCFG2; // Master Configuration Register 2 (hperiphs)
AT91_REG MATRIX_MCFG3; // Master Configuration Register 3 (ebi)
AT91_REG MATRIX_MCFG4; // Master Configuration Register 4 (bridge)
AT91_REG MATRIX_MCFG5; // Master Configuration Register 5 (mailbox)
AT91_REG MATRIX_MCFG6; // Master Configuration Register 6 (ram16k)
AT91_REG MATRIX_MCFG7; // Master Configuration Register 7 (teak_prog)
AT91_REG Reserved0[8]; //
AT91_REG MATRIX_SCFG0; // Slave Configuration Register 0 (ram96k)
AT91_REG MATRIX_SCFG1; // Slave Configuration Register 1 (rom)
AT91_REG MATRIX_SCFG2; // Slave Configuration Register 2 (hperiphs)
AT91_REG MATRIX_SCFG3; // Slave Configuration Register 3 (ebi)
AT91_REG MATRIX_SCFG4; // Slave Configuration Register 4 (bridge)
AT91_REG Reserved1[11]; //
AT91_REG MATRIX_PRAS0; // PRAS0 (ram0)
AT91_REG MATRIX_PRBS0; // PRBS0 (ram0)
AT91_REG MATRIX_PRAS1; // PRAS1 (ram1)
AT91_REG MATRIX_PRBS1; // PRBS1 (ram1)
AT91_REG MATRIX_PRAS2; // PRAS2 (ram2)
AT91_REG MATRIX_PRBS2; // PRBS2 (ram2)
AT91_REG MATRIX_PRAS3; // PRAS3 : usb_dev_hs
AT91_REG MATRIX_PRBS3; // PRBS3 : usb_dev_hs
AT91_REG MATRIX_PRAS4; // PRAS4 : ebi
AT91_REG MATRIX_PRBS4; // PRBS4 : ebi
AT91_REG Reserved2[22]; //
AT91_REG MATRIX_MRCR; // Master Remp Control Register
AT91_REG Reserved3[6]; //
AT91_REG MATRIX_EBI; // Slave 3 (ebi) Special Function Register
AT91_REG Reserved4[3]; //
AT91_REG MATRIX_TEAKCFG; // Slave 7 (teak_prog) Special Function Register
AT91_REG Reserved5[51]; //
AT91_REG MATRIX_VERSION; // Version Register
} AT91S_MATRIX, *AT91PS_MATRIX;
#else
#define MATRIX_MCFG0 (AT91_CAST(AT91_REG *) 0x00000000) // (MATRIX_MCFG0) Master Configuration Register 0 (ram96k)
#define MATRIX_MCFG1 (AT91_CAST(AT91_REG *) 0x00000004) // (MATRIX_MCFG1) Master Configuration Register 1 (rom)
#define MATRIX_MCFG2 (AT91_CAST(AT91_REG *) 0x00000008) // (MATRIX_MCFG2) Master Configuration Register 2 (hperiphs)
#define MATRIX_MCFG3 (AT91_CAST(AT91_REG *) 0x0000000C) // (MATRIX_MCFG3) Master Configuration Register 3 (ebi)
#define MATRIX_MCFG4 (AT91_CAST(AT91_REG *) 0x00000010) // (MATRIX_MCFG4) Master Configuration Register 4 (bridge)
#define MATRIX_MCFG5 (AT91_CAST(AT91_REG *) 0x00000014) // (MATRIX_MCFG5) Master Configuration Register 5 (mailbox)
#define MATRIX_MCFG6 (AT91_CAST(AT91_REG *) 0x00000018) // (MATRIX_MCFG6) Master Configuration Register 6 (ram16k)
#define MATRIX_MCFG7 (AT91_CAST(AT91_REG *) 0x0000001C) // (MATRIX_MCFG7) Master Configuration Register 7 (teak_prog)
#define MATRIX_SCFG0 (AT91_CAST(AT91_REG *) 0x00000040) // (MATRIX_SCFG0) Slave Configuration Register 0 (ram96k)
#define MATRIX_SCFG1 (AT91_CAST(AT91_REG *) 0x00000044) // (MATRIX_SCFG1) Slave Configuration Register 1 (rom)
#define MATRIX_SCFG2 (AT91_CAST(AT91_REG *) 0x00000048) // (MATRIX_SCFG2) Slave Configuration Register 2 (hperiphs)
#define MATRIX_SCFG3 (AT91_CAST(AT91_REG *) 0x0000004C) // (MATRIX_SCFG3) Slave Configuration Register 3 (ebi)
#define MATRIX_SCFG4 (AT91_CAST(AT91_REG *) 0x00000050) // (MATRIX_SCFG4) Slave Configuration Register 4 (bridge)
#define MATRIX_PRAS0 (AT91_CAST(AT91_REG *) 0x00000080) // (MATRIX_PRAS0) PRAS0 (ram0)
#define MATRIX_PRBS0 (AT91_CAST(AT91_REG *) 0x00000084) // (MATRIX_PRBS0) PRBS0 (ram0)
#define MATRIX_PRAS1 (AT91_CAST(AT91_REG *) 0x00000088) // (MATRIX_PRAS1) PRAS1 (ram1)
#define MATRIX_PRBS1 (AT91_CAST(AT91_REG *) 0x0000008C) // (MATRIX_PRBS1) PRBS1 (ram1)
#define MATRIX_PRAS2 (AT91_CAST(AT91_REG *) 0x00000090) // (MATRIX_PRAS2) PRAS2 (ram2)
#define MATRIX_PRBS2 (AT91_CAST(AT91_REG *) 0x00000094) // (MATRIX_PRBS2) PRBS2 (ram2)
#define MATRIX_PRAS3 (AT91_CAST(AT91_REG *) 0x00000098) // (MATRIX_PRAS3) PRAS3 : usb_dev_hs
#define MATRIX_PRBS3 (AT91_CAST(AT91_REG *) 0x0000009C) // (MATRIX_PRBS3) PRBS3 : usb_dev_hs
#define MATRIX_PRAS4 (AT91_CAST(AT91_REG *) 0x000000A0) // (MATRIX_PRAS4) PRAS4 : ebi
#define MATRIX_PRBS4 (AT91_CAST(AT91_REG *) 0x000000A4) // (MATRIX_PRBS4) PRBS4 : ebi
#define MATRIX_MRCR (AT91_CAST(AT91_REG *) 0x00000100) // (MATRIX_MRCR) Master Remp Control Register
#define MATRIX_EBI (AT91_CAST(AT91_REG *) 0x0000011C) // (MATRIX_EBI) Slave 3 (ebi) Special Function Register
#define MATRIX_TEAKCFG (AT91_CAST(AT91_REG *) 0x0000012C) // (MATRIX_TEAKCFG) Slave 7 (teak_prog) Special Function Register
#define MATRIX_VERSION (AT91_CAST(AT91_REG *) 0x000001FC) // (MATRIX_VERSION) Version Register
#endif
// -------- MATRIX_SCFG0 : (MATRIX Offset: 0x40) Slave Configuration Register 0 --------
#define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0) // (MATRIX) Maximum Number of Allowed Cycles for a Burst
#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) // (MATRIX) Default Master Type
#define AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR (0x0 << 16) // (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.
#define AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR (0x1 << 16) // (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.
#define AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR (0x2 << 16) // (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.
#define AT91C_MATRIX_FIXED_DEFMSTR0 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master
// -------- MATRIX_SCFG1 : (MATRIX Offset: 0x44) Slave Configuration Register 1 --------
#define AT91C_MATRIX_FIXED_DEFMSTR1 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master
// -------- MATRIX_SCFG2 : (MATRIX Offset: 0x48) Slave Configuration Register 2 --------
#define AT91C_MATRIX_FIXED_DEFMSTR2 (0x1 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
// -------- MATRIX_SCFG3 : (MATRIX Offset: 0x4c) Slave Configuration Register 3 --------
#define AT91C_MATRIX_FIXED_DEFMSTR3 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master
// -------- MATRIX_SCFG4 : (MATRIX Offset: 0x50) Slave Configuration Register 4 --------
#define AT91C_MATRIX_FIXED_DEFMSTR4 (0x3 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR4_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
// -------- MATRIX_PRAS0 : (MATRIX Offset: 0x80) PRAS0 Register --------
#define AT91C_MATRIX_M0PR (0x3 << 0) // (MATRIX) ARM926EJ-S Instruction priority
#define AT91C_MATRIX_M1PR (0x3 << 4) // (MATRIX) ARM926EJ-S Data priority
#define AT91C_MATRIX_M2PR (0x3 << 8) // (MATRIX) PDC priority
#define AT91C_MATRIX_M3PR (0x3 << 12) // (MATRIX) LCDC priority
#define AT91C_MATRIX_M4PR (0x3 << 16) // (MATRIX) 2DGC priority
#define AT91C_MATRIX_M5PR (0x3 << 20) // (MATRIX) ISI priority
#define AT91C_MATRIX_M6PR (0x3 << 24) // (MATRIX) DMA priority
#define AT91C_MATRIX_M7PR (0x3 << 28) // (MATRIX) EMAC priority
// -------- MATRIX_PRBS0 : (MATRIX Offset: 0x84) PRBS0 Register --------
#define AT91C_MATRIX_M8PR (0x3 << 0) // (MATRIX) USB priority
// -------- MATRIX_PRAS1 : (MATRIX Offset: 0x88) PRAS1 Register --------
// -------- MATRIX_PRBS1 : (MATRIX Offset: 0x8c) PRBS1 Register --------
// -------- MATRIX_PRAS2 : (MATRIX Offset: 0x90) PRAS2 Register --------
// -------- MATRIX_PRBS2 : (MATRIX Offset: 0x94) PRBS2 Register --------
// -------- MATRIX_PRAS3 : (MATRIX Offset: 0x98) PRAS3 Register --------
// -------- MATRIX_PRBS3 : (MATRIX Offset: 0x9c) PRBS3 Register --------
// -------- MATRIX_PRAS4 : (MATRIX Offset: 0xa0) PRAS4 Register --------
// -------- MATRIX_PRBS4 : (MATRIX Offset: 0xa4) PRBS4 Register --------
// -------- MATRIX_MRCR : (MATRIX Offset: 0x100) MRCR Register --------
#define AT91C_MATRIX_RCA926I (0x1 << 0) // (MATRIX) Remap Command for ARM926EJ-S Instruction Master
#define AT91C_MATRIX_RCA926D (0x1 << 1) // (MATRIX) Remap Command for ARM926EJ-S Data Master
// -------- MATRIX_EBI : (MATRIX Offset: 0x11c) EBI (Slave 3) Special Function Register --------
#define AT91C_MATRIX_CS1A (0x1 << 1) // (MATRIX) Chip Select 1 Assignment
#define AT91C_MATRIX_CS1A_SMC (0x0 << 1) // (MATRIX) Chip Select 1 is assigned to the Static Memory Controller.
#define AT91C_MATRIX_CS1A_SDRAMC (0x1 << 1) // (MATRIX) Chip Select 1 is assigned to the SDRAM Controller.
#define AT91C_MATRIX_CS3A (0x1 << 3) // (MATRIX) Chip Select 3 Assignment
#define AT91C_MATRIX_CS3A_SMC (0x0 << 3) // (MATRIX) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.
#define AT91C_MATRIX_CS3A_SM (0x1 << 3) // (MATRIX) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
#define AT91C_MATRIX_CS4A (0x1 << 4) // (MATRIX) Chip Select 4 Assignment
#define AT91C_MATRIX_CS4A_SMC (0x0 << 4) // (MATRIX) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.
#define AT91C_MATRIX_CS4A_CF (0x1 << 4) // (MATRIX) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.
#define AT91C_MATRIX_CS5A (0x1 << 5) // (MATRIX) Chip Select 5 Assignment
#define AT91C_MATRIX_CS5A_SMC (0x0 << 5) // (MATRIX) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC
#define AT91C_MATRIX_CS5A_CF (0x1 << 5) // (MATRIX) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.
#define AT91C_MATRIX_DBPUC (0x1 << 8) // (MATRIX) Data Bus Pull-up Configuration
// -------- MATRIX_TEAKCFG : (MATRIX Offset: 0x12c) Slave 7 Special Function Register --------
#define AT91C_TEAK_PROGRAM_ACCESS (0x1 << 0) // (MATRIX) TEAK program memory access from AHB
#define AT91C_TEAK_PROGRAM_ACCESS_DISABLED (0x0) // (MATRIX) TEAK program access disabled
#define AT91C_TEAK_PROGRAM_ACCESS_ENABLED (0x1) // (MATRIX) TEAK program access enabled
#define AT91C_TEAK_BOOT (0x1 << 1) // (MATRIX) TEAK program start from boot routine
#define AT91C_TEAK_BOOT_DISABLED (0x0 << 1) // (MATRIX) TEAK program starts from boot routine disabled
#define AT91C_TEAK_BOOT_ENABLED (0x1 << 1) // (MATRIX) TEAK program starts from boot routine enabled
#define AT91C_TEAK_NRESET (0x1 << 2) // (MATRIX) active low TEAK reset
#define AT91C_TEAK_NRESET_ENABLED (0x0 << 2) // (MATRIX) active low TEAK reset enabled
#define AT91C_TEAK_NRESET_DISABLED (0x1 << 2) // (MATRIX) active low TEAK reset disabled
#define AT91C_TEAK_LVECTORP (0x3FFFF << 14) // (MATRIX) boot routine start address
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Chip Configuration Registers
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_CCFG {
AT91_REG Reserved0[3]; //
AT91_REG CCFG_EBICSA; // EBI Chip Select Assignement Register
AT91_REG Reserved1[55]; //
AT91_REG CCFG_MATRIXVERSION; // Version Register
} AT91S_CCFG, *AT91PS_CCFG;
#else
#define CCFG_EBICSA (AT91_CAST(AT91_REG *) 0x0000000C) // (CCFG_EBICSA) EBI Chip Select Assignement Register
#define CCFG_MATRIXVERSION (AT91_CAST(AT91_REG *) 0x000000EC) // (CCFG_MATRIXVERSION) Version Register
#endif
// -------- CCFG_EBICSA : (CCFG Offset: 0xc) EBI Chip Select Assignement Register --------
#define AT91C_EBI_CS1A (0x1 << 1) // (CCFG) Chip Select 1 Assignment
#define AT91C_EBI_CS1A_SMC (0x0 << 1) // (CCFG) Chip Select 1 is assigned to the Static Memory Controller.
#define AT91C_EBI_CS1A_SDRAMC (0x1 << 1) // (CCFG) Chip Select 1 is assigned to the SDRAM Controller.
#define AT91C_EBI_CS3A (0x1 << 3) // (CCFG) Chip Select 3 Assignment
#define AT91C_EBI_CS3A_SMC (0x0 << 3) // (CCFG) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.
#define AT91C_EBI_CS3A_SM (0x1 << 3) // (CCFG) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
#define AT91C_EBI_CS4A (0x1 << 4) // (CCFG) Chip Select 4 Assignment
#define AT91C_EBI_CS4A_SMC (0x0 << 4) // (CCFG) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.
#define AT91C_EBI_CS4A_CF (0x1 << 4) // (CCFG) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.
#define AT91C_EBI_CS5A (0x1 << 5) // (CCFG) Chip Select 5 Assignment
#define AT91C_EBI_CS5A_SMC (0x0 << 5) // (CCFG) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC
#define AT91C_EBI_CS5A_CF (0x1 << 5) // (CCFG) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.
#define AT91C_EBI_DBPUC (0x1 << 8) // (CCFG) Data Bus Pull-up Configuration
#define AT91C_EBI_SUPPLY (0x1 << 16) // (CCFG) EBI supply selection
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_PDC {
AT91_REG PDC_RPR; // Receive Pointer Register
AT91_REG PDC_RCR; // Receive Counter Register
AT91_REG PDC_TPR; // Transmit Pointer Register
AT91_REG PDC_TCR; // Transmit Counter Register
AT91_REG PDC_RNPR; // Receive Next Pointer Register
AT91_REG PDC_RNCR; // Receive Next Counter Register
AT91_REG PDC_TNPR; // Transmit Next Pointer Register
AT91_REG PDC_TNCR; // Transmit Next Counter Register
AT91_REG PDC_PTCR; // PDC Transfer Control Register
AT91_REG PDC_PTSR; // PDC Transfer Status Register
} AT91S_PDC, *AT91PS_PDC;
#else
#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register
#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register
#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register
#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register
#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register
#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register
#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register
#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register
#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register
#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register
#endif
// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable
#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable
#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable
#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable
// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Debug Unit
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_DBGU {
AT91_REG DBGU_CR; // Control Register
AT91_REG DBGU_MR; // Mode Register
AT91_REG DBGU_IER; // Interrupt Enable Register
AT91_REG DBGU_IDR; // Interrupt Disable Register
AT91_REG DBGU_IMR; // Interrupt Mask Register
AT91_REG DBGU_CSR; // Channel Status Register
AT91_REG DBGU_RHR; // Receiver Holding Register
AT91_REG DBGU_THR; // Transmitter Holding Register
AT91_REG DBGU_BRGR; // Baud Rate Generator Register
AT91_REG Reserved0[7]; //
AT91_REG DBGU_CIDR; // Chip ID Register
AT91_REG DBGU_EXID; // Chip ID Extension Register
AT91_REG DBGU_FNTR; // Force NTRST Register
AT91_REG Reserved1[45]; //
AT91_REG DBGU_RPR; // Receive Pointer Register
AT91_REG DBGU_RCR; // Receive Counter Register
AT91_REG DBGU_TPR; // Transmit Pointer Register
AT91_REG DBGU_TCR; // Transmit Counter Register
AT91_REG DBGU_RNPR; // Receive Next Pointer Register
AT91_REG DBGU_RNCR; // Receive Next Counter Register
AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
AT91_REG DBGU_TNCR; // Transmit Next Counter Register
AT91_REG DBGU_PTCR; // PDC Transfer Control Register
AT91_REG DBGU_PTSR; // PDC Transfer Status Register
} AT91S_DBGU, *AT91PS_DBGU;
#else
#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register
#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register
#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register
#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register
#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register
#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register
#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register
#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register
#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register
#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register
#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register
#endif
// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver
#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter
#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable
#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable
#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable
#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable
#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits
// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type
#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity
#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity
#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)
#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity
#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode
#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode
#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt
#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt
#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt
#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt
#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt
#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt
#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt
#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt
#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt
#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt
#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt
// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_AIC {
AT91_REG AIC_SMR[32]; // Source Mode Register
AT91_REG AIC_SVR[32]; // Source Vector Register
AT91_REG AIC_IVR; // IRQ Vector Register
AT91_REG AIC_FVR; // FIQ Vector Register
AT91_REG AIC_ISR; // Interrupt Status Register
AT91_REG AIC_IPR; // Interrupt Pending Register
AT91_REG AIC_IMR; // Interrupt Mask Register
AT91_REG AIC_CISR; // Core Interrupt Status Register
AT91_REG Reserved0[2]; //
AT91_REG AIC_IECR; // Interrupt Enable Command Register
AT91_REG AIC_IDCR; // Interrupt Disable Command Register
AT91_REG AIC_ICCR; // Interrupt Clear Command Register
AT91_REG AIC_ISCR; // Interrupt Set Command Register
AT91_REG AIC_EOICR; // End of Interrupt Command Register
AT91_REG AIC_SPU; // Spurious Vector Register
AT91_REG AIC_DCR; // Debug Control Register (Protect)
AT91_REG Reserved1[1]; //
AT91_REG AIC_FFER; // Fast Forcing Enable Register
AT91_REG AIC_FFDR; // Fast Forcing Disable Register
AT91_REG AIC_FFSR; // Fast Forcing Status Register
} AT91S_AIC, *AT91PS_AIC;
#else
#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register
#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register
#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register
#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register
#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register
#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register
#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register
#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register
#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register
#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register
#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register
#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register
#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register
#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register
#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect)
#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register
#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register
#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register
#endif
// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level
#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level
#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level
#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type
#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive
#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered
#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive
#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered
// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status
#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status
// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode
#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_PIO {
AT91_REG PIO_PER; // PIO Enable Register
AT91_REG PIO_PDR; // PIO Disable Register
AT91_REG PIO_PSR; // PIO Status Register
AT91_REG Reserved0[1]; //
AT91_REG PIO_OER; // Output Enable Register
AT91_REG PIO_ODR; // Output Disable Registerr
AT91_REG PIO_OSR; // Output Status Register
AT91_REG Reserved1[1]; //
AT91_REG PIO_IFER; // Input Filter Enable Register
AT91_REG PIO_IFDR; // Input Filter Disable Register
AT91_REG PIO_IFSR; // Input Filter Status Register
AT91_REG Reserved2[1]; //
AT91_REG PIO_SODR; // Set Output Data Register
AT91_REG PIO_CODR; // Clear Output Data Register
AT91_REG PIO_ODSR; // Output Data Status Register
AT91_REG PIO_PDSR; // Pin Data Status Register
AT91_REG PIO_IER; // Interrupt Enable Register
AT91_REG PIO_IDR; // Interrupt Disable Register
AT91_REG PIO_IMR; // Interrupt Mask Register
AT91_REG PIO_ISR; // Interrupt Status Register
AT91_REG PIO_MDER; // Multi-driver Enable Register
AT91_REG PIO_MDDR; // Multi-driver Disable Register
AT91_REG PIO_MDSR; // Multi-driver Status Register
AT91_REG Reserved3[1]; //
AT91_REG PIO_PPUDR; // Pull-up Disable Register
AT91_REG PIO_PPUER; // Pull-up Enable Register
AT91_REG PIO_PPUSR; // Pull-up Status Register
AT91_REG Reserved4[1]; //
AT91_REG PIO_ASR; // Select A Register
AT91_REG PIO_BSR; // Select B Register
AT91_REG PIO_ABSR; // AB Select Status Register
AT91_REG Reserved5[9]; //
AT91_REG PIO_OWER; // Output Write Enable Register
AT91_REG PIO_OWDR; // Output Write Disable Register
AT91_REG PIO_OWSR; // Output Write Status Register
} AT91S_PIO, *AT91PS_PIO;
#else
#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register
#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register
#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register
#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register
#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr
#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register
#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register
#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register
#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register
#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register
#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register
#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register
#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register
#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register
#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register
#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register
#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register
#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register
#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register
#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register
#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register
#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register
#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register
#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register
#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register
#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register
#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register
#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register
#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register
#endif
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Embedded Flash Controller 2.0
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_EFC {
AT91_REG EFC_FMR; // EFC Flash Mode Register
AT91_REG EFC_FCR; // EFC Flash Command Register
AT91_REG EFC_FSR; // EFC Flash Status Register
AT91_REG EFC_FRR; // EFC Flash Result Register
AT91_REG EFC_FVR; // EFC Flash Version Register
} AT91S_EFC, *AT91PS_EFC;
#else
#define EFC_FMR (AT91_CAST(AT91_REG *) 0x00000000) // (EFC_FMR) EFC Flash Mode Register
#define EFC_FCR (AT91_CAST(AT91_REG *) 0x00000004) // (EFC_FCR) EFC Flash Command Register
#define EFC_FSR (AT91_CAST(AT91_REG *) 0x00000008) // (EFC_FSR) EFC Flash Status Register
#define EFC_FRR (AT91_CAST(AT91_REG *) 0x0000000C) // (EFC_FRR) EFC Flash Result Register
#define EFC_FVR (AT91_CAST(AT91_REG *) 0x00000010) // (EFC_FVR) EFC Flash Version Register
#endif
// -------- EFC_FMR : (EFC Offset: 0x0) EFC Flash Mode Register --------
#define AT91C_EFC_FRDY (0x1 << 0) // (EFC) Ready Interrupt Enable
#define AT91C_EFC_FWS (0xF << 8) // (EFC) Flash Wait State.
#define AT91C_EFC_FWS_0WS (0x0 << 8) // (EFC) 0 Wait State
#define AT91C_EFC_FWS_1WS (0x1 << 8) // (EFC) 1 Wait State
#define AT91C_EFC_FWS_2WS (0x2 << 8) // (EFC) 2 Wait States
#define AT91C_EFC_FWS_3WS (0x3 << 8) // (EFC) 3 Wait States
// -------- EFC_FCR : (EFC Offset: 0x4) EFC Flash Command Register --------
#define AT91C_EFC_FCMD (0xFF << 0) // (EFC) Flash Command
#define AT91C_EFC_FCMD_GETD (0x0) // (EFC) Get Flash Descriptor
#define AT91C_EFC_FCMD_WP (0x1) // (EFC) Write Page
#define AT91C_EFC_FCMD_WPL (0x2) // (EFC) Write Page and Lock
#define AT91C_EFC_FCMD_EWP (0x3) // (EFC) Erase Page and Write Page
#define AT91C_EFC_FCMD_EWPL (0x4) // (EFC) Erase Page and Write Page then Lock
#define AT91C_EFC_FCMD_EA (0x5) // (EFC) Erase All
#define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase Plane
#define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase Pages
#define AT91C_EFC_FCMD_SLB (0x8) // (EFC) Set Lock Bit
#define AT91C_EFC_FCMD_CLB (0x9) // (EFC) Clear Lock Bit
#define AT91C_EFC_FCMD_GLB (0xA) // (EFC) Get Lock Bit
#define AT91C_EFC_FCMD_SFB (0xB) // (EFC) Set Fuse Bit
#define AT91C_EFC_FCMD_CFB (0xC) // (EFC) Clear Fuse Bit
#define AT91C_EFC_FCMD_GFB (0xD) // (EFC) Get Fuse Bit
#define AT91C_EFC_FARG (0xFFFF << 8) // (EFC) Flash Command Argument
#define AT91C_EFC_FKEY (0xFF << 24) // (EFC) Flash Writing Protection Key
// -------- EFC_FSR : (EFC Offset: 0x8) EFC Flash Status Register --------
#define AT91C_EFC_FRDY_S (0x1 << 0) // (EFC) Flash Ready Status
#define AT91C_EFC_FCMDE (0x1 << 1) // (EFC) Flash Command Error Status
#define AT91C_EFC_LOCKE (0x1 << 2) // (EFC) Flash Lock Error Status
// -------- EFC_FRR : (EFC Offset: 0xc) EFC Flash Result Register --------
#define AT91C_EFC_FVALUE (0x0 << 0) // (EFC) Flash Result Value
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Clock Generator Controler
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_CKGR {
AT91_REG CKGR_MOR; // Main Oscillator Register
AT91_REG CKGR_MCFR; // Main Clock Frequency Register
AT91_REG CKGR_PLLAR; // PLL A Register
AT91_REG CKGR_PLLBR; // PLL B Register
} AT91S_CKGR, *AT91PS_CKGR;
#else
#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register
#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register
#define CKGR_PLLAR (AT91_CAST(AT91_REG *) 0x00000008) // (CKGR_PLLAR) PLL A Register
#define CKGR_PLLBR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLBR) PLL B Register
#endif
// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable
#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass
#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time
// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency
#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready
// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register --------
#define AT91C_CKGR_DIVA (0xFF << 0) // (CKGR) Divider A Selected
#define AT91C_CKGR_DIVA_0 (0x0) // (CKGR) Divider A output is 0
#define AT91C_CKGR_DIVA_BYPASS (0x1) // (CKGR) Divider A is bypassed
#define AT91C_CKGR_PLLACOUNT (0x3F << 8) // (CKGR) PLL A Counter
#define AT91C_CKGR_OUTA (0x3 << 14) // (CKGR) PLL A Output Frequency Range
#define AT91C_CKGR_OUTA_0 (0x0 << 14) // (CKGR) Please refer to the PLLA datasheet
#define AT91C_CKGR_OUTA_1 (0x1 << 14) // (CKGR) Please refer to the PLLA datasheet
#define AT91C_CKGR_OUTA_2 (0x2 << 14) // (CKGR) Please refer to the PLLA datasheet
#define AT91C_CKGR_OUTA_3 (0x3 << 14) // (CKGR) Please refer to the PLLA datasheet
#define AT91C_CKGR_MULA (0x7FF << 16) // (CKGR) PLL A Multiplier
#define AT91C_CKGR_SRCA (0x1 << 29) // (CKGR)
// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register --------
#define AT91C_CKGR_DIVB (0xFF << 0) // (CKGR) Divider B Selected
#define AT91C_CKGR_DIVB_0 (0x0) // (CKGR) Divider B output is 0
#define AT91C_CKGR_DIVB_BYPASS (0x1) // (CKGR) Divider B is bypassed
#define AT91C_CKGR_PLLBCOUNT (0x3F << 8) // (CKGR) PLL B Counter
#define AT91C_CKGR_OUTB (0x3 << 14) // (CKGR) PLL B Output Frequency Range
#define AT91C_CKGR_OUTB_0 (0x0 << 14) // (CKGR) Please refer to the PLLB datasheet
#define AT91C_CKGR_OUTB_1 (0x1 << 14) // (CKGR) Please refer to the PLLB datasheet
#define AT91C_CKGR_OUTB_2 (0x2 << 14) // (CKGR) Please refer to the PLLB datasheet
#define AT91C_CKGR_OUTB_3 (0x3 << 14) // (CKGR) Please refer to the PLLB datasheet
#define AT91C_CKGR_MULB (0x7FF << 16) // (CKGR) PLL B Multiplier
#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks
#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output
#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Power Management Controler
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_PMC {
AT91_REG PMC_SCER; // System Clock Enable Register
AT91_REG PMC_SCDR; // System Clock Disable Register
AT91_REG PMC_SCSR; // System Clock Status Register
AT91_REG Reserved0[1]; //
AT91_REG PMC_PCER; // Peripheral Clock Enable Register
AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
AT91_REG PMC_PCSR; // Peripheral Clock Status Register
AT91_REG Reserved1[1]; //
AT91_REG PMC_MOR; // Main Oscillator Register
AT91_REG PMC_MCFR; // Main Clock Frequency Register
AT91_REG PMC_PLLAR; // PLL A Register
AT91_REG PMC_PLLBR; // PLL B Register
AT91_REG PMC_MCKR; // Master Clock Register
AT91_REG Reserved2[3]; //
AT91_REG PMC_PCKR[8]; // Programmable Clock Register
AT91_REG PMC_IER; // Interrupt Enable Register
AT91_REG PMC_IDR; // Interrupt Disable Register
AT91_REG PMC_SR; // Status Register
AT91_REG PMC_IMR; // Interrupt Mask Register
} AT91S_PMC, *AT91PS_PMC;
#else
#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register
#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register
#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register
#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register
#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register
#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register
#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register
#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register
#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register
#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register
#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register
#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register
#endif
// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock
#define AT91C_PMC_OTG (0x1 << 5) // (PMC) USB OTG Clock
#define AT91C_PMC_UHP (0x1 << 6) // (PMC) USB Host Port Clock
#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock
#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output
// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
// -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register --------
// -------- CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register --------
// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection
#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected
#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected
#define AT91C_PMC_CSS_PLLA_CLK (0x2) // (PMC) Clock from PLL A is selected
#define AT91C_PMC_CSS_PLLB_CLK (0x3) // (PMC) Clock from PLL B is selected
#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler
#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock
#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2
#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4
#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8
#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16
#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32
#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64
#define AT91C_PMC_MDIV (0x3 << 8) // (PMC) Master Clock Division
#define AT91C_PMC_MDIV_1 (0x0 << 8) // (PMC) The master clock and the processor clock are the same
#define AT91C_PMC_MDIV_2 (0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock
#define AT91C_PMC_MDIV_3 (0x2 << 8) // (PMC) The processor clock is four times faster than the master clock
// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
#define AT91C_PMC_LOCKA (0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask
#define AT91C_PMC_LOCKB (0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask
#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) Master Clock Status/Enable/Disable/Mask
#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Reset Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_RSTC {
AT91_REG RSTC_RCR; // Reset Control Register
AT91_REG RSTC_RSR; // Reset Status Register
AT91_REG RSTC_RMR; // Reset Mode Register
} AT91S_RSTC, *AT91PS_RSTC;
#else
#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register
#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register
#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register
#endif
// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset
#define AT91C_RSTC_ICERST (0x1 << 1) // (RSTC) ICE Interface Reset
#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset
#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset
#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password
// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status
#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type
#define AT91C_RSTC_RSTTYP_GENERAL (0x0 << 8) // (RSTC) General reset. Both VDDCORE and VDDBU rising.
#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level
#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.
// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable
#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable
#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Shut Down Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_SHDWC {
AT91_REG SHDWC_SHCR; // Shut Down Control Register
AT91_REG SHDWC_SHMR; // Shut Down Mode Register
AT91_REG SHDWC_SHSR; // Shut Down Status Register
} AT91S_SHDWC, *AT91PS_SHDWC;
#else
#define SHDWC_SHCR (AT91_CAST(AT91_REG *) 0x00000000) // (SHDWC_SHCR) Shut Down Control Register
#define SHDWC_SHMR (AT91_CAST(AT91_REG *) 0x00000004) // (SHDWC_SHMR) Shut Down Mode Register
#define SHDWC_SHSR (AT91_CAST(AT91_REG *) 0x00000008) // (SHDWC_SHSR) Shut Down Status Register
#endif
// -------- SHDWC_SHCR : (SHDWC Offset: 0x0) Shut Down Control Register --------
#define AT91C_SHDWC_SHDW (0x1 << 0) // (SHDWC) Processor Reset
#define AT91C_SHDWC_KEY (0xFF << 24) // (SHDWC) Shut down KEY Password
// -------- SHDWC_SHMR : (SHDWC Offset: 0x4) Shut Down Mode Register --------
#define AT91C_SHDWC_WKMODE0 (0x3 << 0) // (SHDWC) Wake Up 0 Mode Selection
#define AT91C_SHDWC_WKMODE0_NONE (0x0) // (SHDWC) None. No detection is performed on the wake up input.
#define AT91C_SHDWC_WKMODE0_HIGH (0x1) // (SHDWC) High Level.
#define AT91C_SHDWC_WKMODE0_LOW (0x2) // (SHDWC) Low Level.
#define AT91C_SHDWC_WKMODE0_ANYLEVEL (0x3) // (SHDWC) Any level change.
#define AT91C_SHDWC_CPTWK0 (0xF << 4) // (SHDWC) Counter On Wake Up 0
#define AT91C_SHDWC_WKMODE1 (0x3 << 8) // (SHDWC) Wake Up 1 Mode Selection
#define AT91C_SHDWC_WKMODE1_NONE (0x0 << 8) // (SHDWC) None. No detection is performed on the wake up input.
#define AT91C_SHDWC_WKMODE1_HIGH (0x1 << 8) // (SHDWC) High Level.
#define AT91C_SHDWC_WKMODE1_LOW (0x2 << 8) // (SHDWC) Low Level.
#define AT91C_SHDWC_WKMODE1_ANYLEVEL (0x3 << 8) // (SHDWC) Any level change.
#define AT91C_SHDWC_CPTWK1 (0xF << 12) // (SHDWC) Counter On Wake Up 1
#define AT91C_SHDWC_RTTWKEN (0x1 << 16) // (SHDWC) Real Time Timer Wake Up Enable
#define AT91C_SHDWC_RTCWKEN (0x1 << 17) // (SHDWC) Real Time Clock Wake Up Enable
// -------- SHDWC_SHSR : (SHDWC Offset: 0x8) Shut Down Status Register --------
#define AT91C_SHDWC_WAKEUP0 (0x1 << 0) // (SHDWC) Wake Up 0 Status
#define AT91C_SHDWC_WAKEUP1 (0x1 << 1) // (SHDWC) Wake Up 1 Status
#define AT91C_SHDWC_FWKUP (0x1 << 2) // (SHDWC) Force Wake Up Status
#define AT91C_SHDWC_RTTWK (0x1 << 16) // (SHDWC) Real Time Timer wake Up
#define AT91C_SHDWC_RTCWK (0x1 << 17) // (SHDWC) Real Time Clock wake Up
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_RTTC {
AT91_REG RTTC_RTMR; // Real-time Mode Register
AT91_REG RTTC_RTAR; // Real-time Alarm Register
AT91_REG RTTC_RTVR; // Real-time Value Register
AT91_REG RTTC_RTSR; // Real-time Status Register
} AT91S_RTTC, *AT91PS_RTTC;
#else
#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register
#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register
#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register
#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register
#endif
// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable
#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart
// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value
// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value
// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status
#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_PITC {
AT91_REG PITC_PIMR; // Period Interval Mode Register
AT91_REG PITC_PISR; // Period Interval Status Register
AT91_REG PITC_PIVR; // Period Interval Value Register
AT91_REG PITC_PIIR; // Period Interval Image Register
} AT91S_PITC, *AT91PS_PITC;
#else
#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register
#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register
#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register
#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register
#endif
// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value
#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status
// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value
#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter
// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_WDTC {
AT91_REG WDTC_WDCR; // Watchdog Control Register
AT91_REG WDTC_WDMR; // Watchdog Mode Register
AT91_REG WDTC_WDSR; // Watchdog Status Register
} AT91S_WDTC, *AT91PS_WDTC;
#else
#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register
#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register
#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register
#endif
// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart
#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password
// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart
#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable
#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart
#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable
#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value
#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt
#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt
// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow
#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_TC {
AT91_REG TC_CCR; // Channel Control Register
AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
AT91_REG Reserved0[2]; //
AT91_REG TC_CV; // Counter Value
AT91_REG TC_RA; // Register A
AT91_REG TC_RB; // Register B
AT91_REG TC_RC; // Register C
AT91_REG TC_SR; // Status Register
AT91_REG TC_IER; // Interrupt Enable Register
AT91_REG TC_IDR; // Interrupt Disable Register
AT91_REG TC_IMR; // Interrupt Mask Register
} AT91S_TC, *AT91PS_TC;
#else
#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register
#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)
#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value
#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A
#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B
#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C
#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register
#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register
#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register
#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register
#endif
// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command
#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command
#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command
// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection
#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0
#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1
#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2
#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert
#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection
#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal
#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock
#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock
#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock
#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare
#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection
#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None
#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection
#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None
#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection
#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable
#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection
#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable
#define AT91C_TC_WAVE (0x1 << 15) // (TC)
#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA
#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none
#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set
#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear
#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle
#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection
#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None
#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA
#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA
#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA
#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA
#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none
#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set
#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear
#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle
#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection
#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None
#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA
#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA
#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA
#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA
#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none
#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set
#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear
#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle
#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA
#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none
#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set
#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear
#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle
#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB
#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none
#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set
#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear
#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle
#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB
#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none
#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set
#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear
#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle
#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB
#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none
#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set
#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear
#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle
#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB
#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none
#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set
#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear
#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle
// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow
#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun
#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare
#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare
#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare
#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading
#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading
#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger
#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling
#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror
#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror
// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Timer Counter Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_TCB {
AT91S_TC TCB_TC0; // TC Channel 0
AT91_REG Reserved0[4]; //
AT91S_TC TCB_TC1; // TC Channel 1
AT91_REG Reserved1[4]; //
AT91S_TC TCB_TC2; // TC Channel 2
AT91_REG Reserved2[4]; //
AT91_REG TCB_BCR; // TC Block Control Register
AT91_REG TCB_BMR; // TC Block Mode Register
} AT91S_TCB, *AT91PS_TCB;
#else
#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register
#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register
#endif
// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command
// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection
#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0
#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0
#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0
#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0
#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection
#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1
#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1
#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1
#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1
#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection
#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2
#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2
#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2
#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Multimedia Card Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_MCI {
AT91_REG MCI_CR; // MCI Control Register
AT91_REG MCI_MR; // MCI Mode Register
AT91_REG MCI_DTOR; // MCI Data Timeout Register
AT91_REG MCI_SDCR; // MCI SD Card Register
AT91_REG MCI_ARGR; // MCI Argument Register
AT91_REG MCI_CMDR; // MCI Command Register
AT91_REG MCI_BLKR; // MCI Block Register
AT91_REG Reserved0[1]; //
AT91_REG MCI_RSPR[4]; // MCI Response Register
AT91_REG MCI_RDR; // MCI Receive Data Register
AT91_REG MCI_TDR; // MCI Transmit Data Register
AT91_REG Reserved1[2]; //
AT91_REG MCI_SR; // MCI Status Register
AT91_REG MCI_IER; // MCI Interrupt Enable Register
AT91_REG MCI_IDR; // MCI Interrupt Disable Register
AT91_REG MCI_IMR; // MCI Interrupt Mask Register
AT91_REG Reserved2[43]; //
AT91_REG MCI_VR; // MCI Version Register
AT91_REG MCI_RPR; // Receive Pointer Register
AT91_REG MCI_RCR; // Receive Counter Register
AT91_REG MCI_TPR; // Transmit Pointer Register
AT91_REG MCI_TCR; // Transmit Counter Register
AT91_REG MCI_RNPR; // Receive Next Pointer Register
AT91_REG MCI_RNCR; // Receive Next Counter Register
AT91_REG MCI_TNPR; // Transmit Next Pointer Register
AT91_REG MCI_TNCR; // Transmit Next Counter Register
AT91_REG MCI_PTCR; // PDC Transfer Control Register
AT91_REG MCI_PTSR; // PDC Transfer Status Register
} AT91S_MCI, *AT91PS_MCI;
#else
#define MCI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (MCI_CR) MCI Control Register
#define MCI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (MCI_MR) MCI Mode Register
#define MCI_DTOR (AT91_CAST(AT91_REG *) 0x00000008) // (MCI_DTOR) MCI Data Timeout Register
#define MCI_SDCR (AT91_CAST(AT91_REG *) 0x0000000C) // (MCI_SDCR) MCI SD Card Register
#define MCI_ARGR (AT91_CAST(AT91_REG *) 0x00000010) // (MCI_ARGR) MCI Argument Register
#define MCI_CMDR (AT91_CAST(AT91_REG *) 0x00000014) // (MCI_CMDR) MCI Command Register
#define MCI_BLKR (AT91_CAST(AT91_REG *) 0x00000018) // (MCI_BLKR) MCI Block Register
#define MCI_RSPR (AT91_CAST(AT91_REG *) 0x00000020) // (MCI_RSPR) MCI Response Register
#define MCI_RDR (AT91_CAST(AT91_REG *) 0x00000030) // (MCI_RDR) MCI Receive Data Register
#define MCI_TDR (AT91_CAST(AT91_REG *) 0x00000034) // (MCI_TDR) MCI Transmit Data Register
#define MCI_SR (AT91_CAST(AT91_REG *) 0x00000040) // (MCI_SR) MCI Status Register
#define MCI_IER (AT91_CAST(AT91_REG *) 0x00000044) // (MCI_IER) MCI Interrupt Enable Register
#define MCI_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (MCI_IDR) MCI Interrupt Disable Register
#define MCI_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (MCI_IMR) MCI Interrupt Mask Register
#define MCI_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (MCI_VR) MCI Version Register
#endif
// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register --------
#define AT91C_MCI_MCIEN (0x1 << 0) // (MCI) Multimedia Interface Enable
#define AT91C_MCI_MCIDIS (0x1 << 1) // (MCI) Multimedia Interface Disable
#define AT91C_MCI_PWSEN (0x1 << 2) // (MCI) Power Save Mode Enable
#define AT91C_MCI_PWSDIS (0x1 << 3) // (MCI) Power Save Mode Disable
#define AT91C_MCI_SWRST (0x1 << 7) // (MCI) MCI Software reset
// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register --------
#define AT91C_MCI_CLKDIV (0xFF << 0) // (MCI) Clock Divider
#define AT91C_MCI_PWSDIV (0x7 << 8) // (MCI) Power Saving Divider
#define AT91C_MCI_RDPROOF (0x1 << 11) // (MCI) Read Proof Enable
#define AT91C_MCI_WRPROOF (0x1 << 12) // (MCI) Write Proof Enable
#define AT91C_MCI_PDCFBYTE (0x1 << 13) // (MCI) PDC Force Byte Transfer
#define AT91C_MCI_PDCPADV (0x1 << 14) // (MCI) PDC Padding Value
#define AT91C_MCI_PDCMODE (0x1 << 15) // (MCI) PDC Oriented Mode
#define AT91C_MCI_BLKLEN (0xFFFF << 16) // (MCI) Data Block Length
// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register --------
#define AT91C_MCI_DTOCYC (0xF << 0) // (MCI) Data Timeout Cycle Number
#define AT91C_MCI_DTOMUL (0x7 << 4) // (MCI) Data Timeout Multiplier
#define AT91C_MCI_DTOMUL_1 (0x0 << 4) // (MCI) DTOCYC x 1
#define AT91C_MCI_DTOMUL_16 (0x1 << 4) // (MCI) DTOCYC x 16
#define AT91C_MCI_DTOMUL_128 (0x2 << 4) // (MCI) DTOCYC x 128
#define AT91C_MCI_DTOMUL_256 (0x3 << 4) // (MCI) DTOCYC x 256
#define AT91C_MCI_DTOMUL_1024 (0x4 << 4) // (MCI) DTOCYC x 1024
#define AT91C_MCI_DTOMUL_4096 (0x5 << 4) // (MCI) DTOCYC x 4096
#define AT91C_MCI_DTOMUL_65536 (0x6 << 4) // (MCI) DTOCYC x 65536
#define AT91C_MCI_DTOMUL_1048576 (0x7 << 4) // (MCI) DTOCYC x 1048576
// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register --------
#define AT91C_MCI_SCDSEL (0x3 << 0) // (MCI) SD Card Selector
#define AT91C_MCI_SCDBUS (0x1 << 7) // (MCI) SDCard/SDIO Bus Width
// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register --------
#define AT91C_MCI_CMDNB (0x3F << 0) // (MCI) Command Number
#define AT91C_MCI_RSPTYP (0x3 << 6) // (MCI) Response Type
#define AT91C_MCI_RSPTYP_NO (0x0 << 6) // (MCI) No response
#define AT91C_MCI_RSPTYP_48 (0x1 << 6) // (MCI) 48-bit response
#define AT91C_MCI_RSPTYP_136 (0x2 << 6) // (MCI) 136-bit response
#define AT91C_MCI_SPCMD (0x7 << 8) // (MCI) Special CMD
#define AT91C_MCI_SPCMD_NONE (0x0 << 8) // (MCI) Not a special CMD
#define AT91C_MCI_SPCMD_INIT (0x1 << 8) // (MCI) Initialization CMD
#define AT91C_MCI_SPCMD_SYNC (0x2 << 8) // (MCI) Synchronized CMD
#define AT91C_MCI_SPCMD_IT_CMD (0x4 << 8) // (MCI) Interrupt command
#define AT91C_MCI_SPCMD_IT_REP (0x5 << 8) // (MCI) Interrupt response
#define AT91C_MCI_OPDCMD (0x1 << 11) // (MCI) Open Drain Command
#define AT91C_MCI_MAXLAT (0x1 << 12) // (MCI) Maximum Latency for Command to respond
#define AT91C_MCI_TRCMD (0x3 << 16) // (MCI) Transfer CMD
#define AT91C_MCI_TRCMD_NO (0x0 << 16) // (MCI) No transfer
#define AT91C_MCI_TRCMD_START (0x1 << 16) // (MCI) Start transfer
#define AT91C_MCI_TRCMD_STOP (0x2 << 16) // (MCI) Stop transfer
#define AT91C_MCI_TRDIR (0x1 << 18) // (MCI) Transfer Direction
#define AT91C_MCI_TRTYP (0x7 << 19) // (MCI) Transfer Type
#define AT91C_MCI_TRTYP_BLOCK (0x0 << 19) // (MCI) MMC/SDCard Single Block Transfer type
#define AT91C_MCI_TRTYP_MULTIPLE (0x1 << 19) // (MCI) MMC/SDCard Multiple Block transfer type
#define AT91C_MCI_TRTYP_STREAM (0x2 << 19) // (MCI) MMC Stream transfer type
#define AT91C_MCI_TRTYP_SDIO_BYTE (0x4 << 19) // (MCI) SDIO Byte transfer type
#define AT91C_MCI_TRTYP_SDIO_BLOCK (0x5 << 19) // (MCI) SDIO Block transfer type
#define AT91C_MCI_IOSPCMD (0x3 << 24) // (MCI) SDIO Special Command
#define AT91C_MCI_IOSPCMD_NONE (0x0 << 24) // (MCI) NOT a special command
#define AT91C_MCI_IOSPCMD_SUSPEND (0x1 << 24) // (MCI) SDIO Suspend Command
#define AT91C_MCI_IOSPCMD_RESUME (0x2 << 24) // (MCI) SDIO Resume Command
// -------- MCI_BLKR : (MCI Offset: 0x18) MCI Block Register --------
#define AT91C_MCI_BCNT (0xFFFF << 0) // (MCI) MMC/SDIO Block Count / SDIO Byte Count
// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register --------
#define AT91C_MCI_CMDRDY (0x1 << 0) // (MCI) Command Ready flag
#define AT91C_MCI_RXRDY (0x1 << 1) // (MCI) RX Ready flag
#define AT91C_MCI_TXRDY (0x1 << 2) // (MCI) TX Ready flag
#define AT91C_MCI_BLKE (0x1 << 3) // (MCI) Data Block Transfer Ended flag
#define AT91C_MCI_DTIP (0x1 << 4) // (MCI) Data Transfer in Progress flag
#define AT91C_MCI_NOTBUSY (0x1 << 5) // (MCI) Data Line Not Busy flag
#define AT91C_MCI_ENDRX (0x1 << 6) // (MCI) End of RX Buffer flag
#define AT91C_MCI_ENDTX (0x1 << 7) // (MCI) End of TX Buffer flag
#define AT91C_MCI_SDIOIRQA (0x1 << 8) // (MCI) SDIO Interrupt for Slot A
#define AT91C_MCI_SDIOIRQB (0x1 << 9) // (MCI) SDIO Interrupt for Slot B
#define AT91C_MCI_SDIOIRQC (0x1 << 10) // (MCI) SDIO Interrupt for Slot C
#define AT91C_MCI_SDIOIRQD (0x1 << 11) // (MCI) SDIO Interrupt for Slot D
#define AT91C_MCI_RXBUFF (0x1 << 14) // (MCI) RX Buffer Full flag
#define AT91C_MCI_TXBUFE (0x1 << 15) // (MCI) TX Buffer Empty flag
#define AT91C_MCI_RINDE (0x1 << 16) // (MCI) Response Index Error flag
#define AT91C_MCI_RDIRE (0x1 << 17) // (MCI) Response Direction Error flag
#define AT91C_MCI_RCRCE (0x1 << 18) // (MCI) Response CRC Error flag
#define AT91C_MCI_RENDE (0x1 << 19) // (MCI) Response End Bit Error flag
#define AT91C_MCI_RTOE (0x1 << 20) // (MCI) Response Time-out Error flag
#define AT91C_MCI_DCRCE (0x1 << 21) // (MCI) data CRC Error flag
#define AT91C_MCI_DTOE (0x1 << 22) // (MCI) Data timeout Error flag
#define AT91C_MCI_OVRE (0x1 << 30) // (MCI) Overrun flag
#define AT91C_MCI_UNRE (0x1 << 31) // (MCI) Underrun flag
// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register --------
// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register --------
// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Two-wire Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_TWI {
AT91_REG TWI_CR; // Control Register
AT91_REG TWI_MMR; // Master Mode Register
AT91_REG TWI_SMR; // Slave Mode Register
AT91_REG TWI_IADR; // Internal Address Register
AT91_REG TWI_CWGR; // Clock Waveform Generator Register
AT91_REG Reserved0[3]; //
AT91_REG TWI_SR; // Status Register
AT91_REG TWI_IER; // Interrupt Enable Register
AT91_REG TWI_IDR; // Interrupt Disable Register
AT91_REG TWI_IMR; // Interrupt Mask Register
AT91_REG TWI_RHR; // Receive Holding Register
AT91_REG TWI_THR; // Transmit Holding Register
AT91_REG Reserved1[50]; //
AT91_REG TWI_RPR; // Receive Pointer Register
AT91_REG TWI_RCR; // Receive Counter Register
AT91_REG TWI_TPR; // Transmit Pointer Register
AT91_REG TWI_TCR; // Transmit Counter Register
AT91_REG TWI_RNPR; // Receive Next Pointer Register
AT91_REG TWI_RNCR; // Receive Next Counter Register
AT91_REG TWI_TNPR; // Transmit Next Pointer Register
AT91_REG TWI_TNCR; // Transmit Next Counter Register
AT91_REG TWI_PTCR; // PDC Transfer Control Register
AT91_REG TWI_PTSR; // PDC Transfer Status Register
} AT91S_TWI, *AT91PS_TWI;
#else
#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register
#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register
#define TWI_SMR (AT91_CAST(AT91_REG *) 0x00000008) // (TWI_SMR) Slave Mode Register
#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register
#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register
#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register
#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register
#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register
#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register
#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register
#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register
#endif
// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition
#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition
#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled
#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled
#define AT91C_TWI_SVEN (0x1 << 4) // (TWI) TWI Slave mode Enabled
#define AT91C_TWI_SVDIS (0x1 << 5) // (TWI) TWI Slave mode Disabled
#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset
// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size
#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address
#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address
#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address
#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address
#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction
#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address
// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register --------
#define AT91C_TWI_SADR (0x7F << 16) // (TWI) Slave Address
// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider
#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider
#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider
// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
#define AT91C_TWI_TXCOMP_SLAVE (0x1 << 0) // (TWI) Transmission Completed
#define AT91C_TWI_TXCOMP_MASTER (0x1 << 0) // (TWI) Transmission Completed
#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY
#define AT91C_TWI_TXRDY_MASTER (0x1 << 2) // (TWI) Transmit holding register ReaDY
#define AT91C_TWI_TXRDY_SLAVE (0x1 << 2) // (TWI) Transmit holding register ReaDY
#define AT91C_TWI_SVREAD (0x1 << 3) // (TWI) Slave READ (used only in Slave mode)
#define AT91C_TWI_SVACC (0x1 << 4) // (TWI) Slave ACCess (used only in Slave mode)
#define AT91C_TWI_GACC (0x1 << 5) // (TWI) General Call ACcess (used only in Slave mode)
#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error (used only in Master and Multi-master mode)
#define AT91C_TWI_NACK_SLAVE (0x1 << 8) // (TWI) Not Acknowledged
#define AT91C_TWI_NACK_MASTER (0x1 << 8) // (TWI) Not Acknowledged
#define AT91C_TWI_ARBLST_MULTI_MASTER (0x1 << 9) // (TWI) Arbitration Lost (used only in Multimaster mode)
#define AT91C_TWI_SCLWS (0x1 << 10) // (TWI) Clock Wait State (used only in Slave mode)
#define AT91C_TWI_EOSACC (0x1 << 11) // (TWI) End Of Slave ACCess (used only in Slave mode)
#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) End of Receiver Transfer
#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) End of Receiver Transfer
#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) RXBUFF Interrupt
#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) TXBUFE Interrupt
// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Usart
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_USART {
AT91_REG US_CR; // Control Register
AT91_REG US_MR; // Mode Register
AT91_REG US_IER; // Interrupt Enable Register
AT91_REG US_IDR; // Interrupt Disable Register
AT91_REG US_IMR; // Interrupt Mask Register
AT91_REG US_CSR; // Channel Status Register
AT91_REG US_RHR; // Receiver Holding Register
AT91_REG US_THR; // Transmitter Holding Register
AT91_REG US_BRGR; // Baud Rate Generator Register
AT91_REG US_RTOR; // Receiver Time-out Register
AT91_REG US_TTGR; // Transmitter Time-guard Register
AT91_REG Reserved0[5]; //
AT91_REG US_FIDI; // FI_DI_Ratio Register
AT91_REG US_NER; // Nb Errors Register
AT91_REG Reserved1[1]; //
AT91_REG US_IF; // IRDA_FILTER Register
AT91_REG Reserved2[44]; //
AT91_REG US_RPR; // Receive Pointer Register
AT91_REG US_RCR; // Receive Counter Register
AT91_REG US_TPR; // Transmit Pointer Register
AT91_REG US_TCR; // Transmit Counter Register
AT91_REG US_RNPR; // Receive Next Pointer Register
AT91_REG US_RNCR; // Receive Next Counter Register
AT91_REG US_TNPR; // Transmit Next Pointer Register
AT91_REG US_TNCR; // Transmit Next Counter Register
AT91_REG US_PTCR; // PDC Transfer Control Register
AT91_REG US_PTSR; // PDC Transfer Status Register
} AT91S_USART, *AT91PS_USART;
#else
#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register
#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register
#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register
#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register
#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register
#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register
#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register
#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register
#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register
#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register
#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register
#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register
#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register
#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register
#endif
// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break
#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break
#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out
#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address
#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations
#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge
#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out
#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable
#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable
#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable
#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable
// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode
#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal
#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485
#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking
#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem
#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0
#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1
#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA
#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking
#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock
#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1
#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)
#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)
#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits
#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits
#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits
#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits
#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select
#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits
#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit
#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits
#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order
#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length
#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select
#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode
#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge
#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK
#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions
#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter
// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break
#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out
#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached
#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge
#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag
#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag
#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag
#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag
// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input
#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input
#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input
#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_SSC {
AT91_REG SSC_CR; // Control Register
AT91_REG SSC_CMR; // Clock Mode Register
AT91_REG Reserved0[2]; //
AT91_REG SSC_RCMR; // Receive Clock ModeRegister
AT91_REG SSC_RFMR; // Receive Frame Mode Register
AT91_REG SSC_TCMR; // Transmit Clock Mode Register
AT91_REG SSC_TFMR; // Transmit Frame Mode Register
AT91_REG SSC_RHR; // Receive Holding Register
AT91_REG SSC_THR; // Transmit Holding Register
AT91_REG Reserved1[2]; //
AT91_REG SSC_RSHR; // Receive Sync Holding Register
AT91_REG SSC_TSHR; // Transmit Sync Holding Register
AT91_REG Reserved2[2]; //
AT91_REG SSC_SR; // Status Register
AT91_REG SSC_IER; // Interrupt Enable Register
AT91_REG SSC_IDR; // Interrupt Disable Register
AT91_REG SSC_IMR; // Interrupt Mask Register
AT91_REG Reserved3[44]; //
AT91_REG SSC_RPR; // Receive Pointer Register
AT91_REG SSC_RCR; // Receive Counter Register
AT91_REG SSC_TPR; // Transmit Pointer Register
AT91_REG SSC_TCR; // Transmit Counter Register
AT91_REG SSC_RNPR; // Receive Next Pointer Register
AT91_REG SSC_RNCR; // Receive Next Counter Register
AT91_REG SSC_TNPR; // Transmit Next Pointer Register
AT91_REG SSC_TNCR; // Transmit Next Counter Register
AT91_REG SSC_PTCR; // PDC Transfer Control Register
AT91_REG SSC_PTSR; // PDC Transfer Status Register
} AT91S_SSC, *AT91PS_SSC;
#else
#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register
#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register
#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister
#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register
#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register
#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register
#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register
#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register
#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register
#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register
#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register
#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register
#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register
#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register
#endif
// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable
#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable
#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable
#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable
#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset
// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection
#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock
#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal
#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin
#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection
#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start
#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input
#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input
#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input
#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input
#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input
#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input
#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0
#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay
#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length
#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode
#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First
#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame
#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection
// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value
#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable
// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready
#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty
#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission
#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty
#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready
#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun
#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception
#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full
#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync
#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync
#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable
#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable
// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Serial Parallel Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_SPI {
AT91_REG SPI_CR; // Control Register
AT91_REG SPI_MR; // Mode Register
AT91_REG SPI_RDR; // Receive Data Register
AT91_REG SPI_TDR; // Transmit Data Register
AT91_REG SPI_SR; // Status Register
AT91_REG SPI_IER; // Interrupt Enable Register
AT91_REG SPI_IDR; // Interrupt Disable Register
AT91_REG SPI_IMR; // Interrupt Mask Register
AT91_REG Reserved0[4]; //
AT91_REG SPI_CSR[4]; // Chip Select Register
AT91_REG Reserved1[48]; //
AT91_REG SPI_RPR; // Receive Pointer Register
AT91_REG SPI_RCR; // Receive Counter Register
AT91_REG SPI_TPR; // Transmit Pointer Register
AT91_REG SPI_TCR; // Transmit Counter Register
AT91_REG SPI_RNPR; // Receive Next Pointer Register
AT91_REG SPI_RNCR; // Receive Next Counter Register
AT91_REG SPI_TNPR; // Transmit Next Pointer Register
AT91_REG SPI_TNCR; // Transmit Next Counter Register
AT91_REG SPI_PTCR; // PDC Transfer Control Register
AT91_REG SPI_PTSR; // PDC Transfer Status Register
} AT91S_SPI, *AT91PS_SPI;
#else
#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register
#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register
#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register
#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register
#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register
#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register
#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register
#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register
#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register
#endif
// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable
#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable
#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset
#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer
// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode
#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select
#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select
#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select
#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode
#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection
#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection
#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection
#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select
#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects
// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data
#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data
#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full
#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty
#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error
#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status
#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer
#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer
#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt
#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt
#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt
#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt
#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status
// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity
#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase
#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer
#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer
#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer
#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer
#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer
#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer
#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer
#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer
#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer
#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer
#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer
#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate
#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK
#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_ADC {
AT91_REG ADC_CR; // ADC Control Register
AT91_REG ADC_MR; // ADC Mode Register
AT91_REG Reserved0[2]; //
AT91_REG ADC_CHER; // ADC Channel Enable Register
AT91_REG ADC_CHDR; // ADC Channel Disable Register
AT91_REG ADC_CHSR; // ADC Channel Status Register
AT91_REG ADC_SR; // ADC Status Register
AT91_REG ADC_LCDR; // ADC Last Converted Data Register
AT91_REG ADC_IER; // ADC Interrupt Enable Register
AT91_REG ADC_IDR; // ADC Interrupt Disable Register
AT91_REG ADC_IMR; // ADC Interrupt Mask Register
AT91_REG ADC_CDR0; // ADC Channel Data Register 0
AT91_REG ADC_CDR1; // ADC Channel Data Register 1
AT91_REG ADC_CDR2; // ADC Channel Data Register 2
AT91_REG ADC_CDR3; // ADC Channel Data Register 3
AT91_REG ADC_CDR4; // ADC Channel Data Register 4
AT91_REG ADC_CDR5; // ADC Channel Data Register 5
AT91_REG ADC_CDR6; // ADC Channel Data Register 6
AT91_REG ADC_CDR7; // ADC Channel Data Register 7
AT91_REG Reserved1[44]; //
AT91_REG ADC_RPR; // Receive Pointer Register
AT91_REG ADC_RCR; // Receive Counter Register
AT91_REG ADC_TPR; // Transmit Pointer Register
AT91_REG ADC_TCR; // Transmit Counter Register
AT91_REG ADC_RNPR; // Receive Next Pointer Register
AT91_REG ADC_RNCR; // Receive Next Counter Register
AT91_REG ADC_TNPR; // Transmit Next Pointer Register
AT91_REG ADC_TNCR; // Transmit Next Counter Register
AT91_REG ADC_PTCR; // PDC Transfer Control Register
AT91_REG ADC_PTSR; // PDC Transfer Status Register
} AT91S_ADC, *AT91PS_ADC;
#else
#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register
#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register
#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register
#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register
#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register
#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register
#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register
#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register
#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register
#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register
#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0
#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1
#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2
#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3
#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4
#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5
#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6
#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7
#endif
// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset
#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion
// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable
#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection
#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.
#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution
#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution
#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode
#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode
#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode
#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection
#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time
#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time
// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0
#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1
#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2
#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3
#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4
#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5
#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6
#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7
// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion
#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion
#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion
#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion
#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion
#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion
#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion
#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion
#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error
#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error
#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error
#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error
#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error
#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error
#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error
#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error
#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready
#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun
#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer
#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt
// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted
// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data
// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_EMAC {
AT91_REG EMAC_NCR; // Network Control Register
AT91_REG EMAC_NCFGR; // Network Configuration Register
AT91_REG EMAC_NSR; // Network Status Register
AT91_REG Reserved0[2]; //
AT91_REG EMAC_TSR; // Transmit Status Register
AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer
AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer
AT91_REG EMAC_RSR; // Receive Status Register
AT91_REG EMAC_ISR; // Interrupt Status Register
AT91_REG EMAC_IER; // Interrupt Enable Register
AT91_REG EMAC_IDR; // Interrupt Disable Register
AT91_REG EMAC_IMR; // Interrupt Mask Register
AT91_REG EMAC_MAN; // PHY Maintenance Register
AT91_REG EMAC_PTR; // Pause Time Register
AT91_REG EMAC_PFR; // Pause Frames received Register
AT91_REG EMAC_FTO; // Frames Transmitted OK Register
AT91_REG EMAC_SCF; // Single Collision Frame Register
AT91_REG EMAC_MCF; // Multiple Collision Frame Register
AT91_REG EMAC_FRO; // Frames Received OK Register
AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register
AT91_REG EMAC_ALE; // Alignment Error Register
AT91_REG EMAC_DTF; // Deferred Transmission Frame Register
AT91_REG EMAC_LCOL; // Late Collision Register
AT91_REG EMAC_ECOL; // Excessive Collision Register
AT91_REG EMAC_TUND; // Transmit Underrun Error Register
AT91_REG EMAC_CSE; // Carrier Sense Error Register
AT91_REG EMAC_RRE; // Receive Ressource Error Register
AT91_REG EMAC_ROV; // Receive Overrun Errors Register
AT91_REG EMAC_RSE; // Receive Symbol Errors Register
AT91_REG EMAC_ELE; // Excessive Length Errors Register
AT91_REG EMAC_RJA; // Receive Jabbers Register
AT91_REG EMAC_USF; // Undersize Frames Register
AT91_REG EMAC_STE; // SQE Test Error Register
AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register
AT91_REG EMAC_TPF; // Transmitted Pause Frames Register
AT91_REG EMAC_HRB; // Hash Address Bottom[31:0]
AT91_REG EMAC_HRT; // Hash Address Top[63:32]
AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes
AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes
AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes
AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes
AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes
AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes
AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes
AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes
AT91_REG EMAC_TID; // Type ID Checking Register
AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register
AT91_REG EMAC_USRIO; // USER Input/Output Register
AT91_REG EMAC_WOL; // Wake On LAN Register
AT91_REG Reserved1[13]; //
AT91_REG EMAC_REV; // Revision Register
} AT91S_EMAC, *AT91PS_EMAC;
#else
#define EMAC_NCR (AT91_CAST(AT91_REG *) 0x00000000) // (EMAC_NCR) Network Control Register
#define EMAC_NCFGR (AT91_CAST(AT91_REG *) 0x00000004) // (EMAC_NCFGR) Network Configuration Register
#define EMAC_NSR (AT91_CAST(AT91_REG *) 0x00000008) // (EMAC_NSR) Network Status Register
#define EMAC_TSR (AT91_CAST(AT91_REG *) 0x00000014) // (EMAC_TSR) Transmit Status Register
#define EMAC_RBQP (AT91_CAST(AT91_REG *) 0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer
#define EMAC_TBQP (AT91_CAST(AT91_REG *) 0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer
#define EMAC_RSR (AT91_CAST(AT91_REG *) 0x00000020) // (EMAC_RSR) Receive Status Register
#define EMAC_ISR (AT91_CAST(AT91_REG *) 0x00000024) // (EMAC_ISR) Interrupt Status Register
#define EMAC_IER (AT91_CAST(AT91_REG *) 0x00000028) // (EMAC_IER) Interrupt Enable Register
#define EMAC_IDR (AT91_CAST(AT91_REG *) 0x0000002C) // (EMAC_IDR) Interrupt Disable Register
#define EMAC_IMR (AT91_CAST(AT91_REG *) 0x00000030) // (EMAC_IMR) Interrupt Mask Register
#define EMAC_MAN (AT91_CAST(AT91_REG *) 0x00000034) // (EMAC_MAN) PHY Maintenance Register
#define EMAC_PTR (AT91_CAST(AT91_REG *) 0x00000038) // (EMAC_PTR) Pause Time Register
#define EMAC_PFR (AT91_CAST(AT91_REG *) 0x0000003C) // (EMAC_PFR) Pause Frames received Register
#define EMAC_FTO (AT91_CAST(AT91_REG *) 0x00000040) // (EMAC_FTO) Frames Transmitted OK Register
#define EMAC_SCF (AT91_CAST(AT91_REG *) 0x00000044) // (EMAC_SCF) Single Collision Frame Register
#define EMAC_MCF (AT91_CAST(AT91_REG *) 0x00000048) // (EMAC_MCF) Multiple Collision Frame Register
#define EMAC_FRO (AT91_CAST(AT91_REG *) 0x0000004C) // (EMAC_FRO) Frames Received OK Register
#define EMAC_FCSE (AT91_CAST(AT91_REG *) 0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register
#define EMAC_ALE (AT91_CAST(AT91_REG *) 0x00000054) // (EMAC_ALE) Alignment Error Register
#define EMAC_DTF (AT91_CAST(AT91_REG *) 0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register
#define EMAC_LCOL (AT91_CAST(AT91_REG *) 0x0000005C) // (EMAC_LCOL) Late Collision Register
#define EMAC_ECOL (AT91_CAST(AT91_REG *) 0x00000060) // (EMAC_ECOL) Excessive Collision Register
#define EMAC_TUND (AT91_CAST(AT91_REG *) 0x00000064) // (EMAC_TUND) Transmit Underrun Error Register
#define EMAC_CSE (AT91_CAST(AT91_REG *) 0x00000068) // (EMAC_CSE) Carrier Sense Error Register
#define EMAC_RRE (AT91_CAST(AT91_REG *) 0x0000006C) // (EMAC_RRE) Receive Ressource Error Register
#define EMAC_ROV (AT91_CAST(AT91_REG *) 0x00000070) // (EMAC_ROV) Receive Overrun Errors Register
#define EMAC_RSE (AT91_CAST(AT91_REG *) 0x00000074) // (EMAC_RSE) Receive Symbol Errors Register
#define EMAC_ELE (AT91_CAST(AT91_REG *) 0x00000078) // (EMAC_ELE) Excessive Length Errors Register
#define EMAC_RJA (AT91_CAST(AT91_REG *) 0x0000007C) // (EMAC_RJA) Receive Jabbers Register
#define EMAC_USF (AT91_CAST(AT91_REG *) 0x00000080) // (EMAC_USF) Undersize Frames Register
#define EMAC_STE (AT91_CAST(AT91_REG *) 0x00000084) // (EMAC_STE) SQE Test Error Register
#define EMAC_RLE (AT91_CAST(AT91_REG *) 0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register
#define EMAC_TPF (AT91_CAST(AT91_REG *) 0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register
#define EMAC_HRB (AT91_CAST(AT91_REG *) 0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0]
#define EMAC_HRT (AT91_CAST(AT91_REG *) 0x00000094) // (EMAC_HRT) Hash Address Top[63:32]
#define EMAC_SA1L (AT91_CAST(AT91_REG *) 0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes
#define EMAC_SA1H (AT91_CAST(AT91_REG *) 0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes
#define EMAC_SA2L (AT91_CAST(AT91_REG *) 0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes
#define EMAC_SA2H (AT91_CAST(AT91_REG *) 0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes
#define EMAC_SA3L (AT91_CAST(AT91_REG *) 0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes
#define EMAC_SA3H (AT91_CAST(AT91_REG *) 0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes
#define EMAC_SA4L (AT91_CAST(AT91_REG *) 0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes
#define EMAC_SA4H (AT91_CAST(AT91_REG *) 0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes
#define EMAC_TID (AT91_CAST(AT91_REG *) 0x000000B8) // (EMAC_TID) Type ID Checking Register
#define EMAC_TPQ (AT91_CAST(AT91_REG *) 0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register
#define EMAC_USRIO (AT91_CAST(AT91_REG *) 0x000000C0) // (EMAC_USRIO) USER Input/Output Register
#define EMAC_WOL (AT91_CAST(AT91_REG *) 0x000000C4) // (EMAC_WOL) Wake On LAN Register
#define EMAC_REV (AT91_CAST(AT91_REG *) 0x000000FC) // (EMAC_REV) Revision Register
#endif
// -------- EMAC_NCR : (EMAC Offset: 0x0) --------
#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local.
#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable.
#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable.
#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable.
#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers.
#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers.
#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers.
#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure.
#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission.
#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt.
#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame
#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame
// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed.
#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex.
#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames.
#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames.
#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast.
#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable
#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable.
#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes.
#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable.
#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC)
#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8
#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16
#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32
#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64
#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC)
#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC)
#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC)
#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer
#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer
#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable
#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS
#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC)
#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS
// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC)
#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC)
#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC)
// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC)
#define AT91C_EMAC_COL (0x1 << 1) // (EMAC)
#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC)
#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go
#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame
#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC)
#define AT91C_EMAC_UND (0x1 << 6) // (EMAC)
// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC)
#define AT91C_EMAC_REC (0x1 << 1) // (EMAC)
#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC)
// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC)
#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC)
#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC)
#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC)
#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC)
#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC)
#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC)
#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC)
#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC)
#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC)
#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC)
#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC)
#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC)
// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC)
#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC)
#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC)
#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC)
#define AT91C_EMAC_RW (0x3 << 28) // (EMAC)
#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC)
// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII
#define AT91C_EMAC_CLKEN (0x1 << 1) // (EMAC) Clock Enable
// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address
#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable
#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable
#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable
// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC)
#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC)
// *****************************************************************************
// SOFTWARE API DEFINITION FOR USB Device Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_UDP {
AT91_REG UDP_NUM; // Frame Number Register
AT91_REG UDP_GLBSTATE; // Global State Register
AT91_REG UDP_FADDR; // Function Address Register
AT91_REG Reserved0[1]; //
AT91_REG UDP_IER; // Interrupt Enable Register
AT91_REG UDP_IDR; // Interrupt Disable Register
AT91_REG UDP_IMR; // Interrupt Mask Register
AT91_REG UDP_ISR; // Interrupt Status Register
AT91_REG UDP_ICR; // Interrupt Clear Register
AT91_REG Reserved1[1]; //
AT91_REG UDP_RSTEP; // Reset Endpoint Register
AT91_REG Reserved2[1]; //
AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register
AT91_REG Reserved3[2]; //
AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register
AT91_REG Reserved4[3]; //
AT91_REG UDP_TXVC; // Transceiver Control Register
} AT91S_UDP, *AT91PS_UDP;
#else
#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register
#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register
#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register
#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register
#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register
#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register
#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register
#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register
#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register
#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register
#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register
#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register
#endif
// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error
#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK
// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable
#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured
#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume
#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable
// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value
#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable
// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt
#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt
#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt
#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt
#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt
#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt
#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt
#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt
#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt
#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt
#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt
// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0
#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1
#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2
#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3
#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4
#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5
// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0
#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints)
#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready
#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction
#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type
#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control
#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT
#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT
#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT
#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN
#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN
#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN
#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle
#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable
#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP)
#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON
// *****************************************************************************
// SOFTWARE API DEFINITION FOR USB Host Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_UHP {
AT91_REG UHP_HcRevision; // Revision
AT91_REG UHP_HcControl; // Operating modes for the Host Controller
AT91_REG UHP_HcCommandStatus; // Command & status Register
AT91_REG UHP_HcInterruptStatus; // Interrupt Status Register
AT91_REG UHP_HcInterruptEnable; // Interrupt Enable Register
AT91_REG UHP_HcInterruptDisable; // Interrupt Disable Register
AT91_REG UHP_HcHCCA; // Pointer to the Host Controller Communication Area
AT91_REG UHP_HcPeriodCurrentED; // Current Isochronous or Interrupt Endpoint Descriptor
AT91_REG UHP_HcControlHeadED; // First Endpoint Descriptor of the Control list
AT91_REG UHP_HcControlCurrentED; // Endpoint Control and Status Register
AT91_REG UHP_HcBulkHeadED; // First endpoint register of the Bulk list
AT91_REG UHP_HcBulkCurrentED; // Current endpoint of the Bulk list
AT91_REG UHP_HcBulkDoneHead; // Last completed transfer descriptor
AT91_REG UHP_HcFmInterval; // Bit time between 2 consecutive SOFs
AT91_REG UHP_HcFmRemaining; // Bit time remaining in the current Frame
AT91_REG UHP_HcFmNumber; // Frame number
AT91_REG UHP_HcPeriodicStart; // Periodic Start
AT91_REG UHP_HcLSThreshold; // LS Threshold
AT91_REG UHP_HcRhDescriptorA; // Root Hub characteristics A
AT91_REG UHP_HcRhDescriptorB; // Root Hub characteristics B
AT91_REG UHP_HcRhStatus; // Root Hub Status register
AT91_REG UHP_HcRhPortStatus[2]; // Root Hub Port Status Register
} AT91S_UHP, *AT91PS_UHP;
#else
#define HcRevision (AT91_CAST(AT91_REG *) 0x00000000) // (HcRevision) Revision
#define HcControl (AT91_CAST(AT91_REG *) 0x00000004) // (HcControl) Operating modes for the Host Controller
#define HcCommandStatus (AT91_CAST(AT91_REG *) 0x00000008) // (HcCommandStatus) Command & status Register
#define HcInterruptStatus (AT91_CAST(AT91_REG *) 0x0000000C) // (HcInterruptStatus) Interrupt Status Register
#define HcInterruptEnable (AT91_CAST(AT91_REG *) 0x00000010) // (HcInterruptEnable) Interrupt Enable Register
#define HcInterruptDisable (AT91_CAST(AT91_REG *) 0x00000014) // (HcInterruptDisable) Interrupt Disable Register
#define HcHCCA (AT91_CAST(AT91_REG *) 0x00000018) // (HcHCCA) Pointer to the Host Controller Communication Area
#define HcPeriodCurrentED (AT91_CAST(AT91_REG *) 0x0000001C) // (HcPeriodCurrentED) Current Isochronous or Interrupt Endpoint Descriptor
#define HcControlHeadED (AT91_CAST(AT91_REG *) 0x00000020) // (HcControlHeadED) First Endpoint Descriptor of the Control list
#define HcControlCurrentED (AT91_CAST(AT91_REG *) 0x00000024) // (HcControlCurrentED) Endpoint Control and Status Register
#define HcBulkHeadED (AT91_CAST(AT91_REG *) 0x00000028) // (HcBulkHeadED) First endpoint register of the Bulk list
#define HcBulkCurrentED (AT91_CAST(AT91_REG *) 0x0000002C) // (HcBulkCurrentED) Current endpoint of the Bulk list
#define HcBulkDoneHead (AT91_CAST(AT91_REG *) 0x00000030) // (HcBulkDoneHead) Last completed transfer descriptor
#define HcFmInterval (AT91_CAST(AT91_REG *) 0x00000034) // (HcFmInterval) Bit time between 2 consecutive SOFs
#define HcFmRemaining (AT91_CAST(AT91_REG *) 0x00000038) // (HcFmRemaining) Bit time remaining in the current Frame
#define HcFmNumber (AT91_CAST(AT91_REG *) 0x0000003C) // (HcFmNumber) Frame number
#define HcPeriodicStart (AT91_CAST(AT91_REG *) 0x00000040) // (HcPeriodicStart) Periodic Start
#define HcLSThreshold (AT91_CAST(AT91_REG *) 0x00000044) // (HcLSThreshold) LS Threshold
#define HcRhDescriptorA (AT91_CAST(AT91_REG *) 0x00000048) // (HcRhDescriptorA) Root Hub characteristics A
#define HcRhDescriptorB (AT91_CAST(AT91_REG *) 0x0000004C) // (HcRhDescriptorB) Root Hub characteristics B
#define HcRhStatus (AT91_CAST(AT91_REG *) 0x00000050) // (HcRhStatus) Root Hub Status register
#define HcRhPortStatus (AT91_CAST(AT91_REG *) 0x00000054) // (HcRhPortStatus) Root Hub Port Status Register
#endif
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Image Sensor Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_ISI {
AT91_REG ISI_CR1; // Control Register 1
AT91_REG ISI_CR2; // Control Register 2
AT91_REG ISI_SR; // Status Register
AT91_REG ISI_IER; // Interrupt Enable Register
AT91_REG ISI_IDR; // Interrupt Disable Register
AT91_REG ISI_IMR; // Interrupt Mask Register
AT91_REG Reserved0[2]; //
AT91_REG ISI_PSIZE; // Preview Size Register
AT91_REG ISI_PDECF; // Preview Decimation Factor Register
AT91_REG ISI_PFBD; // Preview Frame Buffer Address Register
AT91_REG ISI_CDBA; // Codec Dma Address Register
AT91_REG ISI_Y2RSET0; // Color Space Conversion Register
AT91_REG ISI_Y2RSET1; // Color Space Conversion Register
AT91_REG ISI_R2YSET0; // Color Space Conversion Register
AT91_REG ISI_R2YSET1; // Color Space Conversion Register
AT91_REG ISI_R2YSET2; // Color Space Conversion Register
} AT91S_ISI, *AT91PS_ISI;
#else
#define ISI_CR1 (AT91_CAST(AT91_REG *) 0x00000000) // (ISI_CR1) Control Register 1
#define ISI_CR2 (AT91_CAST(AT91_REG *) 0x00000004) // (ISI_CR2) Control Register 2
#define ISI_SR (AT91_CAST(AT91_REG *) 0x00000008) // (ISI_SR) Status Register
#define ISI_IER (AT91_CAST(AT91_REG *) 0x0000000C) // (ISI_IER) Interrupt Enable Register
#define ISI_IDR (AT91_CAST(AT91_REG *) 0x00000010) // (ISI_IDR) Interrupt Disable Register
#define ISI_IMR (AT91_CAST(AT91_REG *) 0x00000014) // (ISI_IMR) Interrupt Mask Register
#define ISI_PSIZE (AT91_CAST(AT91_REG *) 0x00000020) // (ISI_PSIZE) Preview Size Register
#define ISI_PDECF (AT91_CAST(AT91_REG *) 0x00000024) // (ISI_PDECF) Preview Decimation Factor Register
#define ISI_PFBD (AT91_CAST(AT91_REG *) 0x00000028) // (ISI_PFBD) Preview Frame Buffer Address Register
#define ISI_CDBA (AT91_CAST(AT91_REG *) 0x0000002C) // (ISI_CDBA) Codec Dma Address Register
#define ISI_Y2RSET0 (AT91_CAST(AT91_REG *) 0x00000030) // (ISI_Y2RSET0) Color Space Conversion Register
#define ISI_Y2RSET1 (AT91_CAST(AT91_REG *) 0x00000034) // (ISI_Y2RSET1) Color Space Conversion Register
#define ISI_R2YSET0 (AT91_CAST(AT91_REG *) 0x00000038) // (ISI_R2YSET0) Color Space Conversion Register
#define ISI_R2YSET1 (AT91_CAST(AT91_REG *) 0x0000003C) // (ISI_R2YSET1) Color Space Conversion Register
#define ISI_R2YSET2 (AT91_CAST(AT91_REG *) 0x00000040) // (ISI_R2YSET2) Color Space Conversion Register
#endif
// -------- ISI_CR1 : (ISI Offset: 0x0) ISI Control Register 1 --------
#define AT91C_ISI_RST (0x1 << 0) // (ISI) Image sensor interface reset
#define AT91C_ISI_DISABLE (0x1 << 1) // (ISI) image sensor disable.
#define AT91C_ISI_HSYNC_POL (0x1 << 2) // (ISI) Horizontal synchronisation polarity
#define AT91C_ISI_PIXCLK_POL (0x1 << 4) // (ISI) Pixel Clock Polarity
#define AT91C_ISI_EMB_SYNC (0x1 << 6) // (ISI) Embedded synchronisation
#define AT91C_ISI_CRC_SYNC (0x1 << 7) // (ISI) CRC correction
#define AT91C_ISI_FULL (0x1 << 12) // (ISI) Full mode is allowed
#define AT91C_ISI_THMASK (0x3 << 13) // (ISI) DMA Burst Mask
#define AT91C_ISI_THMASK_4_8_16_BURST (0x0 << 13) // (ISI) 4,8 and 16 AHB burst are allowed
#define AT91C_ISI_THMASK_8_16_BURST (0x1 << 13) // (ISI) 8 and 16 AHB burst are allowed
#define AT91C_ISI_THMASK_16_BURST (0x2 << 13) // (ISI) Only 16 AHB burst are allowed
#define AT91C_ISI_CODEC_ON (0x1 << 15) // (ISI) Enable the codec path
#define AT91C_ISI_SLD (0xFF << 16) // (ISI) Start of Line Delay
#define AT91C_ISI_SFD (0xFF << 24) // (ISI) Start of frame Delay
// -------- ISI_CR2 : (ISI Offset: 0x4) ISI Control Register 2 --------
#define AT91C_ISI_IM_VSIZE (0x7FF << 0) // (ISI) Vertical size of the Image sensor [0..2047]
#define AT91C_ISI_GS_MODE (0x1 << 11) // (ISI) Grayscale Memory Mode
#define AT91C_ISI_RGB_MODE (0x3 << 12) // (ISI) RGB mode
#define AT91C_ISI_RGB_MODE_RGB_888 (0x0 << 12) // (ISI) RGB 8:8:8 24 bits
#define AT91C_ISI_RGB_MODE_RGB_565 (0x1 << 12) // (ISI) RGB 5:6:5 16 bits
#define AT91C_ISI_RGB_MODE_RGB_555 (0x2 << 12) // (ISI) RGB 5:5:5 16 bits
#define AT91C_ISI_GRAYSCALE (0x1 << 13) // (ISI) Grayscale Mode
#define AT91C_ISI_RGB_SWAP (0x1 << 14) // (ISI) RGB Swap
#define AT91C_ISI_COL_SPACE (0x1 << 15) // (ISI) Color space for the image data
#define AT91C_ISI_IM_HSIZE (0x7FF << 16) // (ISI) Horizontal size of the Image sensor [0..2047]
#define AT91C_ISI_RGB_MODE_YCC_DEF (0x0 << 28) // (ISI) Cb(i) Y(i) Cr(i) Y(i+1)
#define AT91C_ISI_RGB_MODE_YCC_MOD1 (0x1 << 28) // (ISI) Cr(i) Y(i) Cb(i) Y(i+1)
#define AT91C_ISI_RGB_MODE_YCC_MOD2 (0x2 << 28) // (ISI) Y(i) Cb(i) Y(i+1) Cr(i)
#define AT91C_ISI_RGB_MODE_YCC_MOD3 (0x3 << 28) // (ISI) Y(i) Cr(i) Y(i+1) Cb(i)
#define AT91C_ISI_RGB_CFG (0x3 << 30) // (ISI) RGB configuration
#define AT91C_ISI_RGB_CFG_RGB_DEF (0x0 << 30) // (ISI) R/G(MSB) G(LSB)/B R/G(MSB) G(LSB)/B
#define AT91C_ISI_RGB_CFG_RGB_MOD1 (0x1 << 30) // (ISI) B/G(MSB) G(LSB)/R B/G(MSB) G(LSB)/R
#define AT91C_ISI_RGB_CFG_RGB_MOD2 (0x2 << 30) // (ISI) G(LSB)/R B/G(MSB) G(LSB)/R B/G(MSB)
#define AT91C_ISI_RGB_CFG_RGB_MOD3 (0x3 << 30) // (ISI) G(LSB)/B R/G(MSB) G(LSB)/B R/G(MSB)
// -------- ISI_SR : (ISI Offset: 0x8) ISI Status Register --------
#define AT91C_ISI_SOF (0x1 << 0) // (ISI) Start of Frame
#define AT91C_ISI_DIS (0x1 << 1) // (ISI) Image Sensor Interface disable
#define AT91C_ISI_SOFTRST (0x1 << 2) // (ISI) Software Reset
#define AT91C_ISI_CRC_ERR (0x1 << 4) // (ISI) CRC synchronisation error
#define AT91C_ISI_FO_C_OVF (0x1 << 5) // (ISI) Fifo Codec Overflow
#define AT91C_ISI_FO_P_OVF (0x1 << 6) // (ISI) Fifo Preview Overflow
#define AT91C_ISI_FO_P_EMP (0x1 << 7) // (ISI) Fifo Preview Empty
#define AT91C_ISI_FO_C_EMP (0x1 << 8) // (ISI) Fifo Codec Empty
#define AT91C_ISI_FR_OVR (0x1 << 9) // (ISI) Frame rate overun
// -------- ISI_IER : (ISI Offset: 0xc) ISI Interrupt Enable Register --------
// -------- ISI_IDR : (ISI Offset: 0x10) ISI Interrupt Disable Register --------
// -------- ISI_IMR : (ISI Offset: 0x14) ISI Interrupt Mask Register --------
// -------- ISI_PSIZE : (ISI Offset: 0x20) ISI Preview Register --------
#define AT91C_ISI_PREV_VSIZE (0x3FF << 0) // (ISI) Vertical size for the preview path
#define AT91C_ISI_PREV_HSIZE (0x3FF << 16) // (ISI) Horizontal size for the preview path
// -------- ISI_Y2R_SET0 : (ISI Offset: 0x30) Color Space Conversion YCrCb to RGB Register --------
#define AT91C_ISI_Y2R_C0 (0xFF << 0) // (ISI) Color Space Conversion Matrix Coefficient C0
#define AT91C_ISI_Y2R_C1 (0xFF << 8) // (ISI) Color Space Conversion Matrix Coefficient C1
#define AT91C_ISI_Y2R_C2 (0xFF << 16) // (ISI) Color Space Conversion Matrix Coefficient C2
#define AT91C_ISI_Y2R_C3 (0xFF << 24) // (ISI) Color Space Conversion Matrix Coefficient C3
// -------- ISI_Y2R_SET1 : (ISI Offset: 0x34) ISI Color Space Conversion YCrCb to RGB set 1 Register --------
#define AT91C_ISI_Y2R_C4 (0x1FF << 0) // (ISI) Color Space Conversion Matrix Coefficient C4
#define AT91C_ISI_Y2R_YOFF (0xFF << 12) // (ISI) Color Space Conversion Luninance default offset
#define AT91C_ISI_Y2R_CROFF (0xFF << 13) // (ISI) Color Space Conversion Red Chrominance default offset
#define AT91C_ISI_Y2R_CBFF (0xFF << 14) // (ISI) Color Space Conversion Luninance default offset
// -------- ISI_R2Y_SET0 : (ISI Offset: 0x38) Color Space Conversion RGB to YCrCb set 0 register --------
#define AT91C_ISI_R2Y_C0 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C0
#define AT91C_ISI_R2Y_C1 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C1
#define AT91C_ISI_R2Y_C2 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C2
#define AT91C_ISI_R2Y_ROFF (0x1 << 4) // (ISI) Color Space Conversion Red component offset
// -------- ISI_R2Y_SET1 : (ISI Offset: 0x3c) Color Space Conversion RGB to YCrCb set 1 register --------
#define AT91C_ISI_R2Y_C3 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C3
#define AT91C_ISI_R2Y_C4 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C4
#define AT91C_ISI_R2Y_C5 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C5
#define AT91C_ISI_R2Y_GOFF (0x1 << 4) // (ISI) Color Space Conversion Green component offset
// -------- ISI_R2Y_SET2 : (ISI Offset: 0x40) Color Space Conversion RGB to YCrCb set 2 register --------
#define AT91C_ISI_R2Y_C6 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C6
#define AT91C_ISI_R2Y_C7 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C7
#define AT91C_ISI_R2Y_C8 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C8
#define AT91C_ISI_R2Y_BOFF (0x1 << 4) // (ISI) Color Space Conversion Blue component offset
// *****************************************************************************
// REGISTER ADDRESS DEFINITION FOR AT91SAM9XE128
// *****************************************************************************
// ========== Register definition for SYS peripheral ==========
#define AT91C_SYS_GPBR (AT91_CAST(AT91_REG *) 0xFFFFFFFF) // (SYS) General Purpose Register
// ========== Register definition for EBI peripheral ==========
#define AT91C_EBI_DUMMY (AT91_CAST(AT91_REG *) 0xFFFFEA00) // (EBI) Dummy register - Do not use
// ========== Register definition for HECC peripheral ==========
#define AT91C_HECC_VR (AT91_CAST(AT91_REG *) 0xFFFFE8FC) // (HECC) ECC Version register
#define AT91C_HECC_NPR (AT91_CAST(AT91_REG *) 0xFFFFE810) // (HECC) ECC Parity N register
#define AT91C_HECC_SR (AT91_CAST(AT91_REG *) 0xFFFFE808) // (HECC) ECC Status register
#define AT91C_HECC_PR (AT91_CAST(AT91_REG *) 0xFFFFE80C) // (HECC) ECC Parity register
#define AT91C_HECC_MR (AT91_CAST(AT91_REG *) 0xFFFFE804) // (HECC) ECC Page size register
#define AT91C_HECC_CR (AT91_CAST(AT91_REG *) 0xFFFFE800) // (HECC) ECC reset register
// ========== Register definition for SDRAMC peripheral ==========
#define AT91C_SDRAMC_MR (AT91_CAST(AT91_REG *) 0xFFFFEA00) // (SDRAMC) SDRAM Controller Mode Register
#define AT91C_SDRAMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFEA1C) // (SDRAMC) SDRAM Controller Interrupt Mask Register
#define AT91C_SDRAMC_LPR (AT91_CAST(AT91_REG *) 0xFFFFEA10) // (SDRAMC) SDRAM Controller Low Power Register
#define AT91C_SDRAMC_ISR (AT91_CAST(AT91_REG *) 0xFFFFEA20) // (SDRAMC) SDRAM Controller Interrupt Mask Register
#define AT91C_SDRAMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFEA18) // (SDRAMC) SDRAM Controller Interrupt Disable Register
#define AT91C_SDRAMC_CR (AT91_CAST(AT91_REG *) 0xFFFFEA08) // (SDRAMC) SDRAM Controller Configuration Register
#define AT91C_SDRAMC_TR (AT91_CAST(AT91_REG *) 0xFFFFEA04) // (SDRAMC) SDRAM Controller Refresh Timer Register
#define AT91C_SDRAMC_MDR (AT91_CAST(AT91_REG *) 0xFFFFEA24) // (SDRAMC) SDRAM Memory Device Register
#define AT91C_SDRAMC_HSR (AT91_CAST(AT91_REG *) 0xFFFFEA0C) // (SDRAMC) SDRAM Controller High Speed Register
#define AT91C_SDRAMC_IER (AT91_CAST(AT91_REG *) 0xFFFFEA14) // (SDRAMC) SDRAM Controller Interrupt Enable Register
// ========== Register definition for SMC peripheral ==========
#define AT91C_SMC_CTRL1 (AT91_CAST(AT91_REG *) 0xFFFFEC1C) // (SMC) Control Register for CS 1
#define AT91C_SMC_PULSE7 (AT91_CAST(AT91_REG *) 0xFFFFEC74) // (SMC) Pulse Register for CS 7
#define AT91C_SMC_PULSE6 (AT91_CAST(AT91_REG *) 0xFFFFEC64) // (SMC) Pulse Register for CS 6
#define AT91C_SMC_SETUP4 (AT91_CAST(AT91_REG *) 0xFFFFEC40) // (SMC) Setup Register for CS 4
#define AT91C_SMC_PULSE3 (AT91_CAST(AT91_REG *) 0xFFFFEC34) // (SMC) Pulse Register for CS 3
#define AT91C_SMC_CYCLE5 (AT91_CAST(AT91_REG *) 0xFFFFEC58) // (SMC) Cycle Register for CS 5
#define AT91C_SMC_CYCLE2 (AT91_CAST(AT91_REG *) 0xFFFFEC28) // (SMC) Cycle Register for CS 2
#define AT91C_SMC_CTRL2 (AT91_CAST(AT91_REG *) 0xFFFFEC2C) // (SMC) Control Register for CS 2
#define AT91C_SMC_CTRL0 (AT91_CAST(AT91_REG *) 0xFFFFEC0C) // (SMC) Control Register for CS 0
#define AT91C_SMC_PULSE5 (AT91_CAST(AT91_REG *) 0xFFFFEC54) // (SMC) Pulse Register for CS 5
#define AT91C_SMC_PULSE1 (AT91_CAST(AT91_REG *) 0xFFFFEC14) // (SMC) Pulse Register for CS 1
#define AT91C_SMC_PULSE0 (AT91_CAST(AT91_REG *) 0xFFFFEC04) // (SMC) Pulse Register for CS 0
#define AT91C_SMC_CYCLE7 (AT91_CAST(AT91_REG *) 0xFFFFEC78) // (SMC) Cycle Register for CS 7
#define AT91C_SMC_CTRL4 (AT91_CAST(AT91_REG *) 0xFFFFEC4C) // (SMC) Control Register for CS 4
#define AT91C_SMC_CTRL3 (AT91_CAST(AT91_REG *) 0xFFFFEC3C) // (SMC) Control Register for CS 3
#define AT91C_SMC_SETUP7 (AT91_CAST(AT91_REG *) 0xFFFFEC70) // (SMC) Setup Register for CS 7
#define AT91C_SMC_CTRL7 (AT91_CAST(AT91_REG *) 0xFFFFEC7C) // (SMC) Control Register for CS 7
#define AT91C_SMC_SETUP1 (AT91_CAST(AT91_REG *) 0xFFFFEC10) // (SMC) Setup Register for CS 1
#define AT91C_SMC_CYCLE0 (AT91_CAST(AT91_REG *) 0xFFFFEC08) // (SMC) Cycle Register for CS 0
#define AT91C_SMC_CTRL5 (AT91_CAST(AT91_REG *) 0xFFFFEC5C) // (SMC) Control Register for CS 5
#define AT91C_SMC_CYCLE1 (AT91_CAST(AT91_REG *) 0xFFFFEC18) // (SMC) Cycle Register for CS 1
#define AT91C_SMC_CTRL6 (AT91_CAST(AT91_REG *) 0xFFFFEC6C) // (SMC) Control Register for CS 6
#define AT91C_SMC_SETUP0 (AT91_CAST(AT91_REG *) 0xFFFFEC00) // (SMC) Setup Register for CS 0
#define AT91C_SMC_PULSE4 (AT91_CAST(AT91_REG *) 0xFFFFEC44) // (SMC) Pulse Register for CS 4
#define AT91C_SMC_SETUP5 (AT91_CAST(AT91_REG *) 0xFFFFEC50) // (SMC) Setup Register for CS 5
#define AT91C_SMC_SETUP2 (AT91_CAST(AT91_REG *) 0xFFFFEC20) // (SMC) Setup Register for CS 2
#define AT91C_SMC_CYCLE3 (AT91_CAST(AT91_REG *) 0xFFFFEC38) // (SMC) Cycle Register for CS 3
#define AT91C_SMC_CYCLE6 (AT91_CAST(AT91_REG *) 0xFFFFEC68) // (SMC) Cycle Register for CS 6
#define AT91C_SMC_SETUP6 (AT91_CAST(AT91_REG *) 0xFFFFEC60) // (SMC) Setup Register for CS 6
#define AT91C_SMC_CYCLE4 (AT91_CAST(AT91_REG *) 0xFFFFEC48) // (SMC) Cycle Register for CS 4
#define AT91C_SMC_PULSE2 (AT91_CAST(AT91_REG *) 0xFFFFEC24) // (SMC) Pulse Register for CS 2
#define AT91C_SMC_SETUP3 (AT91_CAST(AT91_REG *) 0xFFFFEC30) // (SMC) Setup Register for CS 3
// ========== Register definition for MATRIX peripheral ==========
#define AT91C_MATRIX_MCFG0 (AT91_CAST(AT91_REG *) 0xFFFFEE00) // (MATRIX) Master Configuration Register 0 (ram96k)
#define AT91C_MATRIX_MCFG7 (AT91_CAST(AT91_REG *) 0xFFFFEE1C) // (MATRIX) Master Configuration Register 7 (teak_prog)
#define AT91C_MATRIX_SCFG1 (AT91_CAST(AT91_REG *) 0xFFFFEE44) // (MATRIX) Slave Configuration Register 1 (rom)
#define AT91C_MATRIX_MCFG4 (AT91_CAST(AT91_REG *) 0xFFFFEE10) // (MATRIX) Master Configuration Register 4 (bridge)
#define AT91C_MATRIX_VERSION (AT91_CAST(AT91_REG *) 0xFFFFEFFC) // (MATRIX) Version Register
#define AT91C_MATRIX_MCFG2 (AT91_CAST(AT91_REG *) 0xFFFFEE08) // (MATRIX) Master Configuration Register 2 (hperiphs)
#define AT91C_MATRIX_PRBS4 (AT91_CAST(AT91_REG *) 0xFFFFEEA4) // (MATRIX) PRBS4 : ebi
#define AT91C_MATRIX_PRBS0 (AT91_CAST(AT91_REG *) 0xFFFFEE84) // (MATRIX) PRBS0 (ram0)
#define AT91C_MATRIX_SCFG3 (AT91_CAST(AT91_REG *) 0xFFFFEE4C) // (MATRIX) Slave Configuration Register 3 (ebi)
#define AT91C_MATRIX_MCFG6 (AT91_CAST(AT91_REG *) 0xFFFFEE18) // (MATRIX) Master Configuration Register 6 (ram16k)
#define AT91C_MATRIX_EBI (AT91_CAST(AT91_REG *) 0xFFFFEF1C) // (MATRIX) Slave 3 (ebi) Special Function Register
#define AT91C_MATRIX_SCFG0 (AT91_CAST(AT91_REG *) 0xFFFFEE40) // (MATRIX) Slave Configuration Register 0 (ram96k)
#define AT91C_MATRIX_PRBS3 (AT91_CAST(AT91_REG *) 0xFFFFEE9C) // (MATRIX) PRBS3 : usb_dev_hs
#define AT91C_MATRIX_PRAS3 (AT91_CAST(AT91_REG *) 0xFFFFEE98) // (MATRIX) PRAS3 : usb_dev_hs
#define AT91C_MATRIX_PRAS0 (AT91_CAST(AT91_REG *) 0xFFFFEE80) // (MATRIX) PRAS0 (ram0)
#define AT91C_MATRIX_MCFG3 (AT91_CAST(AT91_REG *) 0xFFFFEE0C) // (MATRIX) Master Configuration Register 3 (ebi)
#define AT91C_MATRIX_PRAS1 (AT91_CAST(AT91_REG *) 0xFFFFEE88) // (MATRIX) PRAS1 (ram1)
#define AT91C_MATRIX_PRAS2 (AT91_CAST(AT91_REG *) 0xFFFFEE90) // (MATRIX) PRAS2 (ram2)
#define AT91C_MATRIX_SCFG2 (AT91_CAST(AT91_REG *) 0xFFFFEE48) // (MATRIX) Slave Configuration Register 2 (hperiphs)
#define AT91C_MATRIX_MCFG5 (AT91_CAST(AT91_REG *) 0xFFFFEE14) // (MATRIX) Master Configuration Register 5 (mailbox)
#define AT91C_MATRIX_MCFG1 (AT91_CAST(AT91_REG *) 0xFFFFEE04) // (MATRIX) Master Configuration Register 1 (rom)
#define AT91C_MATRIX_PRAS4 (AT91_CAST(AT91_REG *) 0xFFFFEEA0) // (MATRIX) PRAS4 : ebi
#define AT91C_MATRIX_MRCR (AT91_CAST(AT91_REG *) 0xFFFFEF00) // (MATRIX) Master Remp Control Register
#define AT91C_MATRIX_PRBS2 (AT91_CAST(AT91_REG *) 0xFFFFEE94) // (MATRIX) PRBS2 (ram2)
#define AT91C_MATRIX_SCFG4 (AT91_CAST(AT91_REG *) 0xFFFFEE50) // (MATRIX) Slave Configuration Register 4 (bridge)
#define AT91C_MATRIX_TEAKCFG (AT91_CAST(AT91_REG *) 0xFFFFEF2C) // (MATRIX) Slave 7 (teak_prog) Special Function Register
#define AT91C_MATRIX_PRBS1 (AT91_CAST(AT91_REG *) 0xFFFFEE8C) // (MATRIX) PRBS1 (ram1)
// ========== Register definition for CCFG peripheral ==========
#define AT91C_CCFG_MATRIXVERSION (AT91_CAST(AT91_REG *) 0xFFFFEFFC) // (CCFG) Version Register
#define AT91C_CCFG_EBICSA (AT91_CAST(AT91_REG *) 0xFFFFEF1C) // (CCFG) EBI Chip Select Assignement Register
// ========== Register definition for PDC_DBGU peripheral ==========
#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
// ========== Register definition for DBGU peripheral ==========
#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
// ========== Register definition for AIC peripheral ==========
#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
// ========== Register definition for PIOA peripheral ==========
#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
// ========== Register definition for PIOB peripheral ==========
#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register
#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register
#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register
#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register
#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register
#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register
#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register
#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register
#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register
#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register
#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register
#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register
#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register
#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register
#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register
#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register
#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr
#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register
#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register
#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register
#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register
#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register
#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register
#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register
#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register
#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register
#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register
#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register
#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register
// ========== Register definition for PIOC peripheral ==========
#define AT91C_PIOC_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF8A4) // (PIOC) Output Write Disable Register
#define AT91C_PIOC_SODR (AT91_CAST(AT91_REG *) 0xFFFFF830) // (PIOC) Set Output Data Register
#define AT91C_PIOC_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF864) // (PIOC) Pull-up Enable Register
#define AT91C_PIOC_CODR (AT91_CAST(AT91_REG *) 0xFFFFF834) // (PIOC) Clear Output Data Register
#define AT91C_PIOC_PSR (AT91_CAST(AT91_REG *) 0xFFFFF808) // (PIOC) PIO Status Register
#define AT91C_PIOC_PDR (AT91_CAST(AT91_REG *) 0xFFFFF804) // (PIOC) PIO Disable Register
#define AT91C_PIOC_ODR (AT91_CAST(AT91_REG *) 0xFFFFF814) // (PIOC) Output Disable Registerr
#define AT91C_PIOC_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF868) // (PIOC) Pull-up Status Register
#define AT91C_PIOC_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF878) // (PIOC) AB Select Status Register
#define AT91C_PIOC_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF828) // (PIOC) Input Filter Status Register
#define AT91C_PIOC_OER (AT91_CAST(AT91_REG *) 0xFFFFF810) // (PIOC) Output Enable Register
#define AT91C_PIOC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF848) // (PIOC) Interrupt Mask Register
#define AT91C_PIOC_ASR (AT91_CAST(AT91_REG *) 0xFFFFF870) // (PIOC) Select A Register
#define AT91C_PIOC_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF854) // (PIOC) Multi-driver Disable Register
#define AT91C_PIOC_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF8A8) // (PIOC) Output Write Status Register
#define AT91C_PIOC_PER (AT91_CAST(AT91_REG *) 0xFFFFF800) // (PIOC) PIO Enable Register
#define AT91C_PIOC_IDR (AT91_CAST(AT91_REG *) 0xFFFFF844) // (PIOC) Interrupt Disable Register
#define AT91C_PIOC_MDER (AT91_CAST(AT91_REG *) 0xFFFFF850) // (PIOC) Multi-driver Enable Register
#define AT91C_PIOC_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF83C) // (PIOC) Pin Data Status Register
#define AT91C_PIOC_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF858) // (PIOC) Multi-driver Status Register
#define AT91C_PIOC_OWER (AT91_CAST(AT91_REG *) 0xFFFFF8A0) // (PIOC) Output Write Enable Register
#define AT91C_PIOC_BSR (AT91_CAST(AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register
#define AT91C_PIOC_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF860) // (PIOC) Pull-up Disable Register
#define AT91C_PIOC_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF824) // (PIOC) Input Filter Disable Register
#define AT91C_PIOC_IER (AT91_CAST(AT91_REG *) 0xFFFFF840) // (PIOC) Interrupt Enable Register
#define AT91C_PIOC_OSR (AT91_CAST(AT91_REG *) 0xFFFFF818) // (PIOC) Output Status Register
#define AT91C_PIOC_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF838) // (PIOC) Output Data Status Register
#define AT91C_PIOC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF84C) // (PIOC) Interrupt Status Register
#define AT91C_PIOC_IFER (AT91_CAST(AT91_REG *) 0xFFFFF820) // (PIOC) Input Filter Enable Register
// ========== Register definition for EFC peripheral ==========
#define AT91C_EFC_FVR (AT91_CAST(AT91_REG *) 0xFFFFFA10) // (EFC) EFC Flash Version Register
#define AT91C_EFC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFA04) // (EFC) EFC Flash Command Register
#define AT91C_EFC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFA00) // (EFC) EFC Flash Mode Register
#define AT91C_EFC_FRR (AT91_CAST(AT91_REG *) 0xFFFFFA0C) // (EFC) EFC Flash Result Register
#define AT91C_EFC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFA08) // (EFC) EFC Flash Status Register
// ========== Register definition for CKGR peripheral ==========
#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
#define AT91C_CKGR_PLLBR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL B Register
#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
#define AT91C_CKGR_PLLAR (AT91_CAST(AT91_REG *) 0xFFFFFC28) // (CKGR) PLL A Register
// ========== Register definition for PMC peripheral ==========
#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
#define AT91C_PMC_PLLAR (AT91_CAST(AT91_REG *) 0xFFFFFC28) // (PMC) PLL A Register
#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
#define AT91C_PMC_PLLBR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL B Register
#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
// ========== Register definition for RSTC peripheral ==========
#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
// ========== Register definition for SHDWC peripheral ==========
#define AT91C_SHDWC_SHSR (AT91_CAST(AT91_REG *) 0xFFFFFD18) // (SHDWC) Shut Down Status Register
#define AT91C_SHDWC_SHMR (AT91_CAST(AT91_REG *) 0xFFFFFD14) // (SHDWC) Shut Down Mode Register
#define AT91C_SHDWC_SHCR (AT91_CAST(AT91_REG *) 0xFFFFFD10) // (SHDWC) Shut Down Control Register
// ========== Register definition for RTTC peripheral ==========
#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
// ========== Register definition for PITC peripheral ==========
#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
// ========== Register definition for WDTC peripheral ==========
#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
// ========== Register definition for TC0 peripheral ==========
#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register
#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C
#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B
#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A
#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
// ========== Register definition for TC1 peripheral ==========
#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B
#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register
#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A
#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C
#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
// ========== Register definition for TC2 peripheral ==========
#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A
#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B
#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C
#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
// ========== Register definition for TC3 peripheral ==========
#define AT91C_TC3_IER (AT91_CAST(AT91_REG *) 0xFFFDC024) // (TC3) Interrupt Enable Register
#define AT91C_TC3_RB (AT91_CAST(AT91_REG *) 0xFFFDC018) // (TC3) Register B
#define AT91C_TC3_CMR (AT91_CAST(AT91_REG *) 0xFFFDC004) // (TC3) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC3_RC (AT91_CAST(AT91_REG *) 0xFFFDC01C) // (TC3) Register C
#define AT91C_TC3_CCR (AT91_CAST(AT91_REG *) 0xFFFDC000) // (TC3) Channel Control Register
#define AT91C_TC3_SR (AT91_CAST(AT91_REG *) 0xFFFDC020) // (TC3) Status Register
#define AT91C_TC3_CV (AT91_CAST(AT91_REG *) 0xFFFDC010) // (TC3) Counter Value
#define AT91C_TC3_RA (AT91_CAST(AT91_REG *) 0xFFFDC014) // (TC3) Register A
#define AT91C_TC3_IDR (AT91_CAST(AT91_REG *) 0xFFFDC028) // (TC3) Interrupt Disable Register
#define AT91C_TC3_IMR (AT91_CAST(AT91_REG *) 0xFFFDC02C) // (TC3) Interrupt Mask Register
// ========== Register definition for TC4 peripheral ==========
#define AT91C_TC4_CMR (AT91_CAST(AT91_REG *) 0xFFFDC044) // (TC4) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC4_RC (AT91_CAST(AT91_REG *) 0xFFFDC05C) // (TC4) Register C
#define AT91C_TC4_SR (AT91_CAST(AT91_REG *) 0xFFFDC060) // (TC4) Status Register
#define AT91C_TC4_RB (AT91_CAST(AT91_REG *) 0xFFFDC058) // (TC4) Register B
#define AT91C_TC4_IER (AT91_CAST(AT91_REG *) 0xFFFDC064) // (TC4) Interrupt Enable Register
#define AT91C_TC4_CV (AT91_CAST(AT91_REG *) 0xFFFDC050) // (TC4) Counter Value
#define AT91C_TC4_RA (AT91_CAST(AT91_REG *) 0xFFFDC054) // (TC4) Register A
#define AT91C_TC4_IDR (AT91_CAST(AT91_REG *) 0xFFFDC068) // (TC4) Interrupt Disable Register
#define AT91C_TC4_IMR (AT91_CAST(AT91_REG *) 0xFFFDC06C) // (TC4) Interrupt Mask Register
#define AT91C_TC4_CCR (AT91_CAST(AT91_REG *) 0xFFFDC040) // (TC4) Channel Control Register
// ========== Register definition for TC5 peripheral ==========
#define AT91C_TC5_RB (AT91_CAST(AT91_REG *) 0xFFFDC098) // (TC5) Register B
#define AT91C_TC5_RA (AT91_CAST(AT91_REG *) 0xFFFDC094) // (TC5) Register A
#define AT91C_TC5_CV (AT91_CAST(AT91_REG *) 0xFFFDC090) // (TC5) Counter Value
#define AT91C_TC5_CCR (AT91_CAST(AT91_REG *) 0xFFFDC080) // (TC5) Channel Control Register
#define AT91C_TC5_SR (AT91_CAST(AT91_REG *) 0xFFFDC0A0) // (TC5) Status Register
#define AT91C_TC5_IER (AT91_CAST(AT91_REG *) 0xFFFDC0A4) // (TC5) Interrupt Enable Register
#define AT91C_TC5_IDR (AT91_CAST(AT91_REG *) 0xFFFDC0A8) // (TC5) Interrupt Disable Register
#define AT91C_TC5_RC (AT91_CAST(AT91_REG *) 0xFFFDC09C) // (TC5) Register C
#define AT91C_TC5_IMR (AT91_CAST(AT91_REG *) 0xFFFDC0AC) // (TC5) Interrupt Mask Register
#define AT91C_TC5_CMR (AT91_CAST(AT91_REG *) 0xFFFDC084) // (TC5) Channel Mode Register (Capture Mode / Waveform Mode)
// ========== Register definition for TCB0 peripheral ==========
#define AT91C_TCB0_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB0) TC Block Mode Register
#define AT91C_TCB0_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB0) TC Block Control Register
// ========== Register definition for TCB1 peripheral ==========
#define AT91C_TCB1_BCR (AT91_CAST(AT91_REG *) 0xFFFDC0C0) // (TCB1) TC Block Control Register
#define AT91C_TCB1_BMR (AT91_CAST(AT91_REG *) 0xFFFDC0C4) // (TCB1) TC Block Mode Register
// ========== Register definition for PDC_MCI peripheral ==========
#define AT91C_MCI_RNCR (AT91_CAST(AT91_REG *) 0xFFFA8114) // (PDC_MCI) Receive Next Counter Register
#define AT91C_MCI_TCR (AT91_CAST(AT91_REG *) 0xFFFA810C) // (PDC_MCI) Transmit Counter Register
#define AT91C_MCI_RCR (AT91_CAST(AT91_REG *) 0xFFFA8104) // (PDC_MCI) Receive Counter Register
#define AT91C_MCI_TNPR (AT91_CAST(AT91_REG *) 0xFFFA8118) // (PDC_MCI) Transmit Next Pointer Register
#define AT91C_MCI_RNPR (AT91_CAST(AT91_REG *) 0xFFFA8110) // (PDC_MCI) Receive Next Pointer Register
#define AT91C_MCI_RPR (AT91_CAST(AT91_REG *) 0xFFFA8100) // (PDC_MCI) Receive Pointer Register
#define AT91C_MCI_TNCR (AT91_CAST(AT91_REG *) 0xFFFA811C) // (PDC_MCI) Transmit Next Counter Register
#define AT91C_MCI_TPR (AT91_CAST(AT91_REG *) 0xFFFA8108) // (PDC_MCI) Transmit Pointer Register
#define AT91C_MCI_PTSR (AT91_CAST(AT91_REG *) 0xFFFA8124) // (PDC_MCI) PDC Transfer Status Register
#define AT91C_MCI_PTCR (AT91_CAST(AT91_REG *) 0xFFFA8120) // (PDC_MCI) PDC Transfer Control Register
// ========== Register definition for MCI peripheral ==========
#define AT91C_MCI_RDR (AT91_CAST(AT91_REG *) 0xFFFA8030) // (MCI) MCI Receive Data Register
#define AT91C_MCI_CMDR (AT91_CAST(AT91_REG *) 0xFFFA8014) // (MCI) MCI Command Register
#define AT91C_MCI_VR (AT91_CAST(AT91_REG *) 0xFFFA80FC) // (MCI) MCI Version Register
#define AT91C_MCI_IDR (AT91_CAST(AT91_REG *) 0xFFFA8048) // (MCI) MCI Interrupt Disable Register
#define AT91C_MCI_DTOR (AT91_CAST(AT91_REG *) 0xFFFA8008) // (MCI) MCI Data Timeout Register
#define AT91C_MCI_TDR (AT91_CAST(AT91_REG *) 0xFFFA8034) // (MCI) MCI Transmit Data Register
#define AT91C_MCI_IER (AT91_CAST(AT91_REG *) 0xFFFA8044) // (MCI) MCI Interrupt Enable Register
#define AT91C_MCI_BLKR (AT91_CAST(AT91_REG *) 0xFFFA8018) // (MCI) MCI Block Register
#define AT91C_MCI_MR (AT91_CAST(AT91_REG *) 0xFFFA8004) // (MCI) MCI Mode Register
#define AT91C_MCI_IMR (AT91_CAST(AT91_REG *) 0xFFFA804C) // (MCI) MCI Interrupt Mask Register
#define AT91C_MCI_CR (AT91_CAST(AT91_REG *) 0xFFFA8000) // (MCI) MCI Control Register
#define AT91C_MCI_ARGR (AT91_CAST(AT91_REG *) 0xFFFA8010) // (MCI) MCI Argument Register
#define AT91C_MCI_SDCR (AT91_CAST(AT91_REG *) 0xFFFA800C) // (MCI) MCI SD Card Register
#define AT91C_MCI_SR (AT91_CAST(AT91_REG *) 0xFFFA8040) // (MCI) MCI Status Register
#define AT91C_MCI_RSPR (AT91_CAST(AT91_REG *) 0xFFFA8020) // (MCI) MCI Response Register
// ========== Register definition for PDC_TWI0 peripheral ==========
#define AT91C_TWI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFAC124) // (PDC_TWI0) PDC Transfer Status Register
#define AT91C_TWI0_RPR (AT91_CAST(AT91_REG *) 0xFFFAC100) // (PDC_TWI0) Receive Pointer Register
#define AT91C_TWI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFAC114) // (PDC_TWI0) Receive Next Counter Register
#define AT91C_TWI0_RCR (AT91_CAST(AT91_REG *) 0xFFFAC104) // (PDC_TWI0) Receive Counter Register
#define AT91C_TWI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFAC120) // (PDC_TWI0) PDC Transfer Control Register
#define AT91C_TWI0_TPR (AT91_CAST(AT91_REG *) 0xFFFAC108) // (PDC_TWI0) Transmit Pointer Register
#define AT91C_TWI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFAC110) // (PDC_TWI0) Receive Next Pointer Register
#define AT91C_TWI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFAC118) // (PDC_TWI0) Transmit Next Pointer Register
#define AT91C_TWI0_TCR (AT91_CAST(AT91_REG *) 0xFFFAC10C) // (PDC_TWI0) Transmit Counter Register
#define AT91C_TWI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFAC11C) // (PDC_TWI0) Transmit Next Counter Register
// ========== Register definition for TWI0 peripheral ==========
#define AT91C_TWI0_THR (AT91_CAST(AT91_REG *) 0xFFFAC034) // (TWI0) Transmit Holding Register
#define AT91C_TWI0_IDR (AT91_CAST(AT91_REG *) 0xFFFAC028) // (TWI0) Interrupt Disable Register
#define AT91C_TWI0_SMR (AT91_CAST(AT91_REG *) 0xFFFAC008) // (TWI0) Slave Mode Register
#define AT91C_TWI0_CWGR (AT91_CAST(AT91_REG *) 0xFFFAC010) // (TWI0) Clock Waveform Generator Register
#define AT91C_TWI0_IADR (AT91_CAST(AT91_REG *) 0xFFFAC00C) // (TWI0) Internal Address Register
#define AT91C_TWI0_RHR (AT91_CAST(AT91_REG *) 0xFFFAC030) // (TWI0) Receive Holding Register
#define AT91C_TWI0_IER (AT91_CAST(AT91_REG *) 0xFFFAC024) // (TWI0) Interrupt Enable Register
#define AT91C_TWI0_MMR (AT91_CAST(AT91_REG *) 0xFFFAC004) // (TWI0) Master Mode Register
#define AT91C_TWI0_SR (AT91_CAST(AT91_REG *) 0xFFFAC020) // (TWI0) Status Register
#define AT91C_TWI0_IMR (AT91_CAST(AT91_REG *) 0xFFFAC02C) // (TWI0) Interrupt Mask Register
#define AT91C_TWI0_CR (AT91_CAST(AT91_REG *) 0xFFFAC000) // (TWI0) Control Register
// ========== Register definition for PDC_TWI1 peripheral ==========
#define AT91C_TWI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_TWI1) PDC Transfer Status Register
#define AT91C_TWI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_TWI1) PDC Transfer Control Register
#define AT91C_TWI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_TWI1) Transmit Next Pointer Register
#define AT91C_TWI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_TWI1) Transmit Next Counter Register
#define AT91C_TWI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_TWI1) Receive Next Pointer Register
#define AT91C_TWI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_TWI1) Receive Next Counter Register
#define AT91C_TWI1_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_TWI1) Receive Pointer Register
#define AT91C_TWI1_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_TWI1) Transmit Counter Register
#define AT91C_TWI1_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_TWI1) Transmit Pointer Register
#define AT91C_TWI1_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_TWI1) Receive Counter Register
// ========== Register definition for TWI1 peripheral ==========
#define AT91C_TWI1_RHR (AT91_CAST(AT91_REG *) 0xFFFD8030) // (TWI1) Receive Holding Register
#define AT91C_TWI1_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (TWI1) Interrupt Enable Register
#define AT91C_TWI1_CWGR (AT91_CAST(AT91_REG *) 0xFFFD8010) // (TWI1) Clock Waveform Generator Register
#define AT91C_TWI1_MMR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (TWI1) Master Mode Register
#define AT91C_TWI1_IADR (AT91_CAST(AT91_REG *) 0xFFFD800C) // (TWI1) Internal Address Register
#define AT91C_TWI1_THR (AT91_CAST(AT91_REG *) 0xFFFD8034) // (TWI1) Transmit Holding Register
#define AT91C_TWI1_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (TWI1) Interrupt Mask Register
#define AT91C_TWI1_SR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (TWI1) Status Register
#define AT91C_TWI1_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (TWI1) Interrupt Disable Register
#define AT91C_TWI1_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (TWI1) Control Register
#define AT91C_TWI1_SMR (AT91_CAST(AT91_REG *) 0xFFFD8008) // (TWI1) Slave Mode Register
// ========== Register definition for PDC_US0 peripheral ==========
#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFB010C) // (PDC_US0) Transmit Counter Register
#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFB0120) // (PDC_US0) PDC Transfer Control Register
#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFB0114) // (PDC_US0) Receive Next Counter Register
#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFB0124) // (PDC_US0) PDC Transfer Status Register
#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFB011C) // (PDC_US0) Transmit Next Counter Register
#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFB0110) // (PDC_US0) Receive Next Pointer Register
#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFB0104) // (PDC_US0) Receive Counter Register
#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFB0108) // (PDC_US0) Transmit Pointer Register
#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFB0118) // (PDC_US0) Transmit Next Pointer Register
#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFB0100) // (PDC_US0) Receive Pointer Register
// ========== Register definition for US0 peripheral ==========
#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (US0) Receiver Holding Register
#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFB0044) // (US0) Nb Errors Register
#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFB0008) // (US0) Interrupt Enable Register
#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFB0000) // (US0) Control Register
#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (US0) Transmitter Holding Register
#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (US0) Channel Status Register
#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (US0) Baud Rate Generator Register
#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFB0024) // (US0) Receiver Time-out Register
#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFB0028) // (US0) Transmitter Time-guard Register
#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFB000C) // (US0) Interrupt Disable Register
#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFB0004) // (US0) Mode Register
#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFB004C) // (US0) IRDA_FILTER Register
#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFB0040) // (US0) FI_DI_Ratio Register
#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFB0010) // (US0) Interrupt Mask Register
// ========== Register definition for PDC_US1 peripheral ==========
#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFB4120) // (PDC_US1) PDC Transfer Control Register
#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFB4104) // (PDC_US1) Receive Counter Register
#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFB4100) // (PDC_US1) Receive Pointer Register
#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFB4124) // (PDC_US1) PDC Transfer Status Register
#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFB4108) // (PDC_US1) Transmit Pointer Register
#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFB410C) // (PDC_US1) Transmit Counter Register
#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFB4110) // (PDC_US1) Receive Next Pointer Register
#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFB411C) // (PDC_US1) Transmit Next Counter Register
#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFB4114) // (PDC_US1) Receive Next Counter Register
#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFB4118) // (PDC_US1) Transmit Next Pointer Register
// ========== Register definition for US1 peripheral ==========
#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFB401C) // (US1) Transmitter Holding Register
#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFB4028) // (US1) Transmitter Time-guard Register
#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFB4020) // (US1) Baud Rate Generator Register
#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFB400C) // (US1) Interrupt Disable Register
#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFB4004) // (US1) Mode Register
#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFB4024) // (US1) Receiver Time-out Register
#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFB4000) // (US1) Control Register
#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFB4010) // (US1) Interrupt Mask Register
#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFB4040) // (US1) FI_DI_Ratio Register
#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFB4018) // (US1) Receiver Holding Register
#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFB4008) // (US1) Interrupt Enable Register
#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFB4014) // (US1) Channel Status Register
#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFB404C) // (US1) IRDA_FILTER Register
#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFB4044) // (US1) Nb Errors Register
// ========== Register definition for PDC_US2 peripheral ==========
#define AT91C_US2_TNCR (AT91_CAST(AT91_REG *) 0xFFFB811C) // (PDC_US2) Transmit Next Counter Register
#define AT91C_US2_RNCR (AT91_CAST(AT91_REG *) 0xFFFB8114) // (PDC_US2) Receive Next Counter Register
#define AT91C_US2_TNPR (AT91_CAST(AT91_REG *) 0xFFFB8118) // (PDC_US2) Transmit Next Pointer Register
#define AT91C_US2_PTCR (AT91_CAST(AT91_REG *) 0xFFFB8120) // (PDC_US2) PDC Transfer Control Register
#define AT91C_US2_TCR (AT91_CAST(AT91_REG *) 0xFFFB810C) // (PDC_US2) Transmit Counter Register
#define AT91C_US2_RPR (AT91_CAST(AT91_REG *) 0xFFFB8100) // (PDC_US2) Receive Pointer Register
#define AT91C_US2_TPR (AT91_CAST(AT91_REG *) 0xFFFB8108) // (PDC_US2) Transmit Pointer Register
#define AT91C_US2_RCR (AT91_CAST(AT91_REG *) 0xFFFB8104) // (PDC_US2) Receive Counter Register
#define AT91C_US2_PTSR (AT91_CAST(AT91_REG *) 0xFFFB8124) // (PDC_US2) PDC Transfer Status Register
#define AT91C_US2_RNPR (AT91_CAST(AT91_REG *) 0xFFFB8110) // (PDC_US2) Receive Next Pointer Register
// ========== Register definition for US2 peripheral ==========
#define AT91C_US2_RTOR (AT91_CAST(AT91_REG *) 0xFFFB8024) // (US2) Receiver Time-out Register
#define AT91C_US2_CSR (AT91_CAST(AT91_REG *) 0xFFFB8014) // (US2) Channel Status Register
#define AT91C_US2_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (US2) Control Register
#define AT91C_US2_BRGR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (US2) Baud Rate Generator Register
#define AT91C_US2_NER (AT91_CAST(AT91_REG *) 0xFFFB8044) // (US2) Nb Errors Register
#define AT91C_US2_FIDI (AT91_CAST(AT91_REG *) 0xFFFB8040) // (US2) FI_DI_Ratio Register
#define AT91C_US2_TTGR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (US2) Transmitter Time-guard Register
#define AT91C_US2_RHR (AT91_CAST(AT91_REG *) 0xFFFB8018) // (US2) Receiver Holding Register
#define AT91C_US2_IDR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (US2) Interrupt Disable Register
#define AT91C_US2_THR (AT91_CAST(AT91_REG *) 0xFFFB801C) // (US2) Transmitter Holding Register
#define AT91C_US2_MR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (US2) Mode Register
#define AT91C_US2_IMR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (US2) Interrupt Mask Register
#define AT91C_US2_IF (AT91_CAST(AT91_REG *) 0xFFFB804C) // (US2) IRDA_FILTER Register
#define AT91C_US2_IER (AT91_CAST(AT91_REG *) 0xFFFB8008) // (US2) Interrupt Enable Register
// ========== Register definition for PDC_US3 peripheral ==========
#define AT91C_US3_RNPR (AT91_CAST(AT91_REG *) 0xFFFD0110) // (PDC_US3) Receive Next Pointer Register
#define AT91C_US3_RNCR (AT91_CAST(AT91_REG *) 0xFFFD0114) // (PDC_US3) Receive Next Counter Register
#define AT91C_US3_PTSR (AT91_CAST(AT91_REG *) 0xFFFD0124) // (PDC_US3) PDC Transfer Status Register
#define AT91C_US3_PTCR (AT91_CAST(AT91_REG *) 0xFFFD0120) // (PDC_US3) PDC Transfer Control Register
#define AT91C_US3_TCR (AT91_CAST(AT91_REG *) 0xFFFD010C) // (PDC_US3) Transmit Counter Register
#define AT91C_US3_TNPR (AT91_CAST(AT91_REG *) 0xFFFD0118) // (PDC_US3) Transmit Next Pointer Register
#define AT91C_US3_RCR (AT91_CAST(AT91_REG *) 0xFFFD0104) // (PDC_US3) Receive Counter Register
#define AT91C_US3_TPR (AT91_CAST(AT91_REG *) 0xFFFD0108) // (PDC_US3) Transmit Pointer Register
#define AT91C_US3_TNCR (AT91_CAST(AT91_REG *) 0xFFFD011C) // (PDC_US3) Transmit Next Counter Register
#define AT91C_US3_RPR (AT91_CAST(AT91_REG *) 0xFFFD0100) // (PDC_US3) Receive Pointer Register
// ========== Register definition for US3 peripheral ==========
#define AT91C_US3_NER (AT91_CAST(AT91_REG *) 0xFFFD0044) // (US3) Nb Errors Register
#define AT91C_US3_RTOR (AT91_CAST(AT91_REG *) 0xFFFD0024) // (US3) Receiver Time-out Register
#define AT91C_US3_IDR (AT91_CAST(AT91_REG *) 0xFFFD000C) // (US3) Interrupt Disable Register
#define AT91C_US3_MR (AT91_CAST(AT91_REG *) 0xFFFD0004) // (US3) Mode Register
#define AT91C_US3_FIDI (AT91_CAST(AT91_REG *) 0xFFFD0040) // (US3) FI_DI_Ratio Register
#define AT91C_US3_BRGR (AT91_CAST(AT91_REG *) 0xFFFD0020) // (US3) Baud Rate Generator Register
#define AT91C_US3_THR (AT91_CAST(AT91_REG *) 0xFFFD001C) // (US3) Transmitter Holding Register
#define AT91C_US3_CR (AT91_CAST(AT91_REG *) 0xFFFD0000) // (US3) Control Register
#define AT91C_US3_IF (AT91_CAST(AT91_REG *) 0xFFFD004C) // (US3) IRDA_FILTER Register
#define AT91C_US3_IER (AT91_CAST(AT91_REG *) 0xFFFD0008) // (US3) Interrupt Enable Register
#define AT91C_US3_TTGR (AT91_CAST(AT91_REG *) 0xFFFD0028) // (US3) Transmitter Time-guard Register
#define AT91C_US3_RHR (AT91_CAST(AT91_REG *) 0xFFFD0018) // (US3) Receiver Holding Register
#define AT91C_US3_IMR (AT91_CAST(AT91_REG *) 0xFFFD0010) // (US3) Interrupt Mask Register
#define AT91C_US3_CSR (AT91_CAST(AT91_REG *) 0xFFFD0014) // (US3) Channel Status Register
// ========== Register definition for PDC_US4 peripheral ==========
#define AT91C_US4_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_US4) Transmit Next Counter Register
#define AT91C_US4_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_US4) Receive Pointer Register
#define AT91C_US4_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_US4) Receive Next Counter Register
#define AT91C_US4_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_US4) Transmit Pointer Register
#define AT91C_US4_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_US4) PDC Transfer Control Register
#define AT91C_US4_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_US4) Transmit Counter Register
#define AT91C_US4_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_US4) Receive Counter Register
#define AT91C_US4_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_US4) Receive Next Pointer Register
#define AT91C_US4_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_US4) Transmit Next Pointer Register
#define AT91C_US4_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_US4) PDC Transfer Status Register
// ========== Register definition for US4 peripheral ==========
#define AT91C_US4_BRGR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (US4) Baud Rate Generator Register
#define AT91C_US4_THR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (US4) Transmitter Holding Register
#define AT91C_US4_RTOR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (US4) Receiver Time-out Register
#define AT91C_US4_IMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (US4) Interrupt Mask Register
#define AT91C_US4_NER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (US4) Nb Errors Register
#define AT91C_US4_TTGR (AT91_CAST(AT91_REG *) 0xFFFD4028) // (US4) Transmitter Time-guard Register
#define AT91C_US4_FIDI (AT91_CAST(AT91_REG *) 0xFFFD4040) // (US4) FI_DI_Ratio Register
#define AT91C_US4_MR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (US4) Mode Register
#define AT91C_US4_IER (AT91_CAST(AT91_REG *) 0xFFFD4008) // (US4) Interrupt Enable Register
#define AT91C_US4_RHR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (US4) Receiver Holding Register
#define AT91C_US4_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (US4) Control Register
#define AT91C_US4_IF (AT91_CAST(AT91_REG *) 0xFFFD404C) // (US4) IRDA_FILTER Register
#define AT91C_US4_IDR (AT91_CAST(AT91_REG *) 0xFFFD400C) // (US4) Interrupt Disable Register
#define AT91C_US4_CSR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (US4) Channel Status Register
// ========== Register definition for PDC_SSC0 peripheral ==========
#define AT91C_SSC0_TNPR (AT91_CAST(AT91_REG *) 0xFFFBC118) // (PDC_SSC0) Transmit Next Pointer Register
#define AT91C_SSC0_TCR (AT91_CAST(AT91_REG *) 0xFFFBC10C) // (PDC_SSC0) Transmit Counter Register
#define AT91C_SSC0_RNCR (AT91_CAST(AT91_REG *) 0xFFFBC114) // (PDC_SSC0) Receive Next Counter Register
#define AT91C_SSC0_RPR (AT91_CAST(AT91_REG *) 0xFFFBC100) // (PDC_SSC0) Receive Pointer Register
#define AT91C_SSC0_TPR (AT91_CAST(AT91_REG *) 0xFFFBC108) // (PDC_SSC0) Transmit Pointer Register
#define AT91C_SSC0_RCR (AT91_CAST(AT91_REG *) 0xFFFBC104) // (PDC_SSC0) Receive Counter Register
#define AT91C_SSC0_RNPR (AT91_CAST(AT91_REG *) 0xFFFBC110) // (PDC_SSC0) Receive Next Pointer Register
#define AT91C_SSC0_PTCR (AT91_CAST(AT91_REG *) 0xFFFBC120) // (PDC_SSC0) PDC Transfer Control Register
#define AT91C_SSC0_TNCR (AT91_CAST(AT91_REG *) 0xFFFBC11C) // (PDC_SSC0) Transmit Next Counter Register
#define AT91C_SSC0_PTSR (AT91_CAST(AT91_REG *) 0xFFFBC124) // (PDC_SSC0) PDC Transfer Status Register
// ========== Register definition for SSC0 peripheral ==========
#define AT91C_SSC0_IMR (AT91_CAST(AT91_REG *) 0xFFFBC04C) // (SSC0) Interrupt Mask Register
#define AT91C_SSC0_RFMR (AT91_CAST(AT91_REG *) 0xFFFBC014) // (SSC0) Receive Frame Mode Register
#define AT91C_SSC0_CR (AT91_CAST(AT91_REG *) 0xFFFBC000) // (SSC0) Control Register
#define AT91C_SSC0_TFMR (AT91_CAST(AT91_REG *) 0xFFFBC01C) // (SSC0) Transmit Frame Mode Register
#define AT91C_SSC0_CMR (AT91_CAST(AT91_REG *) 0xFFFBC004) // (SSC0) Clock Mode Register
#define AT91C_SSC0_IER (AT91_CAST(AT91_REG *) 0xFFFBC044) // (SSC0) Interrupt Enable Register
#define AT91C_SSC0_RHR (AT91_CAST(AT91_REG *) 0xFFFBC020) // (SSC0) Receive Holding Register
#define AT91C_SSC0_RCMR (AT91_CAST(AT91_REG *) 0xFFFBC010) // (SSC0) Receive Clock ModeRegister
#define AT91C_SSC0_SR (AT91_CAST(AT91_REG *) 0xFFFBC040) // (SSC0) Status Register
#define AT91C_SSC0_RSHR (AT91_CAST(AT91_REG *) 0xFFFBC030) // (SSC0) Receive Sync Holding Register
#define AT91C_SSC0_THR (AT91_CAST(AT91_REG *) 0xFFFBC024) // (SSC0) Transmit Holding Register
#define AT91C_SSC0_TCMR (AT91_CAST(AT91_REG *) 0xFFFBC018) // (SSC0) Transmit Clock Mode Register
#define AT91C_SSC0_IDR (AT91_CAST(AT91_REG *) 0xFFFBC048) // (SSC0) Interrupt Disable Register
#define AT91C_SSC0_TSHR (AT91_CAST(AT91_REG *) 0xFFFBC034) // (SSC0) Transmit Sync Holding Register
// ========== Register definition for PDC_SPI0 peripheral ==========
#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC8120) // (PDC_SPI0) PDC Transfer Control Register
#define AT91C_SPI0_TCR (AT91_CAST(AT91_REG *) 0xFFFC810C) // (PDC_SPI0) Transmit Counter Register
#define AT91C_SPI0_RPR (AT91_CAST(AT91_REG *) 0xFFFC8100) // (PDC_SPI0) Receive Pointer Register
#define AT91C_SPI0_TPR (AT91_CAST(AT91_REG *) 0xFFFC8108) // (PDC_SPI0) Transmit Pointer Register
#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC8124) // (PDC_SPI0) PDC Transfer Status Register
#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC8114) // (PDC_SPI0) Receive Next Counter Register
#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC8118) // (PDC_SPI0) Transmit Next Pointer Register
#define AT91C_SPI0_RCR (AT91_CAST(AT91_REG *) 0xFFFC8104) // (PDC_SPI0) Receive Counter Register
#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC8110) // (PDC_SPI0) Receive Next Pointer Register
#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC811C) // (PDC_SPI0) Transmit Next Counter Register
// ========== Register definition for SPI0 peripheral ==========
#define AT91C_SPI0_IDR (AT91_CAST(AT91_REG *) 0xFFFC8018) // (SPI0) Interrupt Disable Register
#define AT91C_SPI0_TDR (AT91_CAST(AT91_REG *) 0xFFFC800C) // (SPI0) Transmit Data Register
#define AT91C_SPI0_SR (AT91_CAST(AT91_REG *) 0xFFFC8010) // (SPI0) Status Register
#define AT91C_SPI0_CR (AT91_CAST(AT91_REG *) 0xFFFC8000) // (SPI0) Control Register
#define AT91C_SPI0_CSR (AT91_CAST(AT91_REG *) 0xFFFC8030) // (SPI0) Chip Select Register
#define AT91C_SPI0_RDR (AT91_CAST(AT91_REG *) 0xFFFC8008) // (SPI0) Receive Data Register
#define AT91C_SPI0_MR (AT91_CAST(AT91_REG *) 0xFFFC8004) // (SPI0) Mode Register
#define AT91C_SPI0_IER (AT91_CAST(AT91_REG *) 0xFFFC8014) // (SPI0) Interrupt Enable Register
#define AT91C_SPI0_IMR (AT91_CAST(AT91_REG *) 0xFFFC801C) // (SPI0) Interrupt Mask Register
// ========== Register definition for PDC_SPI1 peripheral ==========
#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFCC120) // (PDC_SPI1) PDC Transfer Control Register
#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFCC110) // (PDC_SPI1) Receive Next Pointer Register
#define AT91C_SPI1_RCR (AT91_CAST(AT91_REG *) 0xFFFCC104) // (PDC_SPI1) Receive Counter Register
#define AT91C_SPI1_TPR (AT91_CAST(AT91_REG *) 0xFFFCC108) // (PDC_SPI1) Transmit Pointer Register
#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFCC124) // (PDC_SPI1) PDC Transfer Status Register
#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFCC11C) // (PDC_SPI1) Transmit Next Counter Register
#define AT91C_SPI1_RPR (AT91_CAST(AT91_REG *) 0xFFFCC100) // (PDC_SPI1) Receive Pointer Register
#define AT91C_SPI1_TCR (AT91_CAST(AT91_REG *) 0xFFFCC10C) // (PDC_SPI1) Transmit Counter Register
#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFCC114) // (PDC_SPI1) Receive Next Counter Register
#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFCC118) // (PDC_SPI1) Transmit Next Pointer Register
// ========== Register definition for SPI1 peripheral ==========
#define AT91C_SPI1_IER (AT91_CAST(AT91_REG *) 0xFFFCC014) // (SPI1) Interrupt Enable Register
#define AT91C_SPI1_RDR (AT91_CAST(AT91_REG *) 0xFFFCC008) // (SPI1) Receive Data Register
#define AT91C_SPI1_SR (AT91_CAST(AT91_REG *) 0xFFFCC010) // (SPI1) Status Register
#define AT91C_SPI1_IMR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (SPI1) Interrupt Mask Register
#define AT91C_SPI1_TDR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (SPI1) Transmit Data Register
#define AT91C_SPI1_IDR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (SPI1) Interrupt Disable Register
#define AT91C_SPI1_CSR (AT91_CAST(AT91_REG *) 0xFFFCC030) // (SPI1) Chip Select Register
#define AT91C_SPI1_CR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (SPI1) Control Register
#define AT91C_SPI1_MR (AT91_CAST(AT91_REG *) 0xFFFCC004) // (SPI1) Mode Register
// ========== Register definition for PDC_ADC peripheral ==========
#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_ADC) PDC Transfer Control Register
#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_ADC) Transmit Pointer Register
#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_ADC) Transmit Counter Register
#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_ADC) Receive Counter Register
#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_ADC) PDC Transfer Status Register
#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_ADC) Receive Next Pointer Register
#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_ADC) Receive Pointer Register
#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_ADC) Transmit Next Counter Register
#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_ADC) Receive Next Counter Register
#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_ADC) Transmit Next Pointer Register
// ========== Register definition for ADC peripheral ==========
#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFE0014) // (ADC) ADC Channel Disable Register
#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFE003C) // (ADC) ADC Channel Data Register 3
#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (ADC) ADC Control Register
#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFE002C) // (ADC) ADC Interrupt Mask Register
#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFE0038) // (ADC) ADC Channel Data Register 2
#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (ADC) ADC Status Register
#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFE0024) // (ADC) ADC Interrupt Enable Register
#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFE004C) // (ADC) ADC Channel Data Register 7
#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFE0030) // (ADC) ADC Channel Data Register 0
#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFE0044) // (ADC) ADC Channel Data Register 5
#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFE0040) // (ADC) ADC Channel Data Register 4
#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFE0010) // (ADC) ADC Channel Enable Register
#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (ADC) ADC Channel Status Register
#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (ADC) ADC Mode Register
#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFE0048) // (ADC) ADC Channel Data Register 6
#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFE0020) // (ADC) ADC Last Converted Data Register
#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFE0034) // (ADC) ADC Channel Data Register 1
#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFE0028) // (ADC) ADC Interrupt Disable Register
// ========== Register definition for EMACB peripheral ==========
#define AT91C_EMACB_USRIO (AT91_CAST(AT91_REG *) 0xFFFC40C0) // (EMACB) USER Input/Output Register
#define AT91C_EMACB_RSE (AT91_CAST(AT91_REG *) 0xFFFC4074) // (EMACB) Receive Symbol Errors Register
#define AT91C_EMACB_SCF (AT91_CAST(AT91_REG *) 0xFFFC4044) // (EMACB) Single Collision Frame Register
#define AT91C_EMACB_STE (AT91_CAST(AT91_REG *) 0xFFFC4084) // (EMACB) SQE Test Error Register
#define AT91C_EMACB_SA1H (AT91_CAST(AT91_REG *) 0xFFFC409C) // (EMACB) Specific Address 1 Top, Last 2 bytes
#define AT91C_EMACB_ROV (AT91_CAST(AT91_REG *) 0xFFFC4070) // (EMACB) Receive Overrun Errors Register
#define AT91C_EMACB_TBQP (AT91_CAST(AT91_REG *) 0xFFFC401C) // (EMACB) Transmit Buffer Queue Pointer
#define AT91C_EMACB_IMR (AT91_CAST(AT91_REG *) 0xFFFC4030) // (EMACB) Interrupt Mask Register
#define AT91C_EMACB_IER (AT91_CAST(AT91_REG *) 0xFFFC4028) // (EMACB) Interrupt Enable Register
#define AT91C_EMACB_REV (AT91_CAST(AT91_REG *) 0xFFFC40FC) // (EMACB) Revision Register
#define AT91C_EMACB_SA3L (AT91_CAST(AT91_REG *) 0xFFFC40A8) // (EMACB) Specific Address 3 Bottom, First 4 bytes
#define AT91C_EMACB_ELE (AT91_CAST(AT91_REG *) 0xFFFC4078) // (EMACB) Excessive Length Errors Register
#define AT91C_EMACB_HRT (AT91_CAST(AT91_REG *) 0xFFFC4094) // (EMACB) Hash Address Top[63:32]
#define AT91C_EMACB_SA2L (AT91_CAST(AT91_REG *) 0xFFFC40A0) // (EMACB) Specific Address 2 Bottom, First 4 bytes
#define AT91C_EMACB_RRE (AT91_CAST(AT91_REG *) 0xFFFC406C) // (EMACB) Receive Ressource Error Register
#define AT91C_EMACB_FRO (AT91_CAST(AT91_REG *) 0xFFFC404C) // (EMACB) Frames Received OK Register
#define AT91C_EMACB_TPQ (AT91_CAST(AT91_REG *) 0xFFFC40BC) // (EMACB) Transmit Pause Quantum Register
#define AT91C_EMACB_ISR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (EMACB) Interrupt Status Register
#define AT91C_EMACB_TSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (EMACB) Transmit Status Register
#define AT91C_EMACB_RLE (AT91_CAST(AT91_REG *) 0xFFFC4088) // (EMACB) Receive Length Field Mismatch Register
#define AT91C_EMACB_USF (AT91_CAST(AT91_REG *) 0xFFFC4080) // (EMACB) Undersize Frames Register
#define AT91C_EMACB_WOL (AT91_CAST(AT91_REG *) 0xFFFC40C4) // (EMACB) Wake On LAN Register
#define AT91C_EMACB_TPF (AT91_CAST(AT91_REG *) 0xFFFC408C) // (EMACB) Transmitted Pause Frames Register
#define AT91C_EMACB_PTR (AT91_CAST(AT91_REG *) 0xFFFC4038) // (EMACB) Pause Time Register
#define AT91C_EMACB_TUND (AT91_CAST(AT91_REG *) 0xFFFC4064) // (EMACB) Transmit Underrun Error Register
#define AT91C_EMACB_MAN (AT91_CAST(AT91_REG *) 0xFFFC4034) // (EMACB) PHY Maintenance Register
#define AT91C_EMACB_RJA (AT91_CAST(AT91_REG *) 0xFFFC407C) // (EMACB) Receive Jabbers Register
#define AT91C_EMACB_SA4L (AT91_CAST(AT91_REG *) 0xFFFC40B0) // (EMACB) Specific Address 4 Bottom, First 4 bytes
#define AT91C_EMACB_CSE (AT91_CAST(AT91_REG *) 0xFFFC4068) // (EMACB) Carrier Sense Error Register
#define AT91C_EMACB_HRB (AT91_CAST(AT91_REG *) 0xFFFC4090) // (EMACB) Hash Address Bottom[31:0]
#define AT91C_EMACB_ALE (AT91_CAST(AT91_REG *) 0xFFFC4054) // (EMACB) Alignment Error Register
#define AT91C_EMACB_SA1L (AT91_CAST(AT91_REG *) 0xFFFC4098) // (EMACB) Specific Address 1 Bottom, First 4 bytes
#define AT91C_EMACB_NCR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (EMACB) Network Control Register
#define AT91C_EMACB_FTO (AT91_CAST(AT91_REG *) 0xFFFC4040) // (EMACB) Frames Transmitted OK Register
#define AT91C_EMACB_ECOL (AT91_CAST(AT91_REG *) 0xFFFC4060) // (EMACB) Excessive Collision Register
#define AT91C_EMACB_DTF (AT91_CAST(AT91_REG *) 0xFFFC4058) // (EMACB) Deferred Transmission Frame Register
#define AT91C_EMACB_SA4H (AT91_CAST(AT91_REG *) 0xFFFC40B4) // (EMACB) Specific Address 4 Top, Last 2 bytes
#define AT91C_EMACB_FCSE (AT91_CAST(AT91_REG *) 0xFFFC4050) // (EMACB) Frame Check Sequence Error Register
#define AT91C_EMACB_TID (AT91_CAST(AT91_REG *) 0xFFFC40B8) // (EMACB) Type ID Checking Register
#define AT91C_EMACB_PFR (AT91_CAST(AT91_REG *) 0xFFFC403C) // (EMACB) Pause Frames received Register
#define AT91C_EMACB_IDR (AT91_CAST(AT91_REG *) 0xFFFC402C) // (EMACB) Interrupt Disable Register
#define AT91C_EMACB_SA3H (AT91_CAST(AT91_REG *) 0xFFFC40AC) // (EMACB) Specific Address 3 Top, Last 2 bytes
#define AT91C_EMACB_NSR (AT91_CAST(AT91_REG *) 0xFFFC4008) // (EMACB) Network Status Register
#define AT91C_EMACB_MCF (AT91_CAST(AT91_REG *) 0xFFFC4048) // (EMACB) Multiple Collision Frame Register
#define AT91C_EMACB_RBQP (AT91_CAST(AT91_REG *) 0xFFFC4018) // (EMACB) Receive Buffer Queue Pointer
#define AT91C_EMACB_RSR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (EMACB) Receive Status Register
#define AT91C_EMACB_SA2H (AT91_CAST(AT91_REG *) 0xFFFC40A4) // (EMACB) Specific Address 2 Top, Last 2 bytes
#define AT91C_EMACB_NCFGR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (EMACB) Network Configuration Register
#define AT91C_EMACB_LCOL (AT91_CAST(AT91_REG *) 0xFFFC405C) // (EMACB) Late Collision Register
// ========== Register definition for UDP peripheral ==========
#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFA4004) // (UDP) Global State Register
#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFA4050) // (UDP) Endpoint FIFO Data Register
#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFA4028) // (UDP) Reset Endpoint Register
#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFA4008) // (UDP) Function Address Register
#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFA4000) // (UDP) Frame Number Register
#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFA4014) // (UDP) Interrupt Disable Register
#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFA4018) // (UDP) Interrupt Mask Register
#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFA4030) // (UDP) Endpoint Control and Status Register
#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFA4010) // (UDP) Interrupt Enable Register
#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFA4020) // (UDP) Interrupt Clear Register
#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFA4074) // (UDP) Transceiver Control Register
#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFA401C) // (UDP) Interrupt Status Register
// ========== Register definition for UHP peripheral ==========
#define AT91C_UHP_HcInterruptStatus (AT91_CAST(AT91_REG *) 0x0050000C) // (UHP) Interrupt Status Register
#define AT91C_UHP_HcCommandStatus (AT91_CAST(AT91_REG *) 0x00500008) // (UHP) Command & status Register
#define AT91C_UHP_HcRhStatus (AT91_CAST(AT91_REG *) 0x00500050) // (UHP) Root Hub Status register
#define AT91C_UHP_HcInterruptDisable (AT91_CAST(AT91_REG *) 0x00500014) // (UHP) Interrupt Disable Register
#define AT91C_UHP_HcPeriodicStart (AT91_CAST(AT91_REG *) 0x00500040) // (UHP) Periodic Start
#define AT91C_UHP_HcControlCurrentED (AT91_CAST(AT91_REG *) 0x00500024) // (UHP) Endpoint Control and Status Register
#define AT91C_UHP_HcPeriodCurrentED (AT91_CAST(AT91_REG *) 0x0050001C) // (UHP) Current Isochronous or Interrupt Endpoint Descriptor
#define AT91C_UHP_HcBulkHeadED (AT91_CAST(AT91_REG *) 0x00500028) // (UHP) First endpoint register of the Bulk list
#define AT91C_UHP_HcRevision (AT91_CAST(AT91_REG *) 0x00500000) // (UHP) Revision
#define AT91C_UHP_HcBulkCurrentED (AT91_CAST(AT91_REG *) 0x0050002C) // (UHP) Current endpoint of the Bulk list
#define AT91C_UHP_HcRhDescriptorB (AT91_CAST(AT91_REG *) 0x0050004C) // (UHP) Root Hub characteristics B
#define AT91C_UHP_HcControlHeadED (AT91_CAST(AT91_REG *) 0x00500020) // (UHP) First Endpoint Descriptor of the Control list
#define AT91C_UHP_HcFmRemaining (AT91_CAST(AT91_REG *) 0x00500038) // (UHP) Bit time remaining in the current Frame
#define AT91C_UHP_HcHCCA (AT91_CAST(AT91_REG *) 0x00500018) // (UHP) Pointer to the Host Controller Communication Area
#define AT91C_UHP_HcLSThreshold (AT91_CAST(AT91_REG *) 0x00500044) // (UHP) LS Threshold
#define AT91C_UHP_HcRhPortStatus (AT91_CAST(AT91_REG *) 0x00500054) // (UHP) Root Hub Port Status Register
#define AT91C_UHP_HcInterruptEnable (AT91_CAST(AT91_REG *) 0x00500010) // (UHP) Interrupt Enable Register
#define AT91C_UHP_HcFmNumber (AT91_CAST(AT91_REG *) 0x0050003C) // (UHP) Frame number
#define AT91C_UHP_HcFmInterval (AT91_CAST(AT91_REG *) 0x00500034) // (UHP) Bit time between 2 consecutive SOFs
#define AT91C_UHP_HcControl (AT91_CAST(AT91_REG *) 0x00500004) // (UHP) Operating modes for the Host Controller
#define AT91C_UHP_HcBulkDoneHead (AT91_CAST(AT91_REG *) 0x00500030) // (UHP) Last completed transfer descriptor
#define AT91C_UHP_HcRhDescriptorA (AT91_CAST(AT91_REG *) 0x00500048) // (UHP) Root Hub characteristics A
// ========== Register definition for HECC peripheral ==========
// ========== Register definition for HISI peripheral ==========
#define AT91C_HISI_PSIZE (AT91_CAST(AT91_REG *) 0xFFFC0020) // (HISI) Preview Size Register
#define AT91C_HISI_CR1 (AT91_CAST(AT91_REG *) 0xFFFC0000) // (HISI) Control Register 1
#define AT91C_HISI_R2YSET1 (AT91_CAST(AT91_REG *) 0xFFFC003C) // (HISI) Color Space Conversion Register
#define AT91C_HISI_CDBA (AT91_CAST(AT91_REG *) 0xFFFC002C) // (HISI) Codec Dma Address Register
#define AT91C_HISI_IDR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (HISI) Interrupt Disable Register
#define AT91C_HISI_R2YSET2 (AT91_CAST(AT91_REG *) 0xFFFC0040) // (HISI) Color Space Conversion Register
#define AT91C_HISI_Y2RSET1 (AT91_CAST(AT91_REG *) 0xFFFC0034) // (HISI) Color Space Conversion Register
#define AT91C_HISI_PFBD (AT91_CAST(AT91_REG *) 0xFFFC0028) // (HISI) Preview Frame Buffer Address Register
#define AT91C_HISI_CR2 (AT91_CAST(AT91_REG *) 0xFFFC0004) // (HISI) Control Register 2
#define AT91C_HISI_Y2RSET0 (AT91_CAST(AT91_REG *) 0xFFFC0030) // (HISI) Color Space Conversion Register
#define AT91C_HISI_PDECF (AT91_CAST(AT91_REG *) 0xFFFC0024) // (HISI) Preview Decimation Factor Register
#define AT91C_HISI_IMR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (HISI) Interrupt Mask Register
#define AT91C_HISI_IER (AT91_CAST(AT91_REG *) 0xFFFC000C) // (HISI) Interrupt Enable Register
#define AT91C_HISI_R2YSET0 (AT91_CAST(AT91_REG *) 0xFFFC0038) // (HISI) Color Space Conversion Register
#define AT91C_HISI_SR (AT91_CAST(AT91_REG *) 0xFFFC0008) // (HISI) Status Register
// *****************************************************************************
// PIO DEFINITIONS FOR AT91SAM9XE128
// *****************************************************************************
#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0
#define AT91C_PA0_SPI0_MISO (AT91C_PIO_PA0) // SPI 0 Master In Slave
#define AT91C_PA0_MCDB0 (AT91C_PIO_PA0) // Multimedia Card B Data 0
#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1
#define AT91C_PA1_SPI0_MOSI (AT91C_PIO_PA1) // SPI 0 Master Out Slave
#define AT91C_PA1_MCCDB (AT91C_PIO_PA1) // Multimedia Card B Command
#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10
#define AT91C_PA10_MCDA2 (AT91C_PIO_PA10) // Multimedia Card A Data 2
#define AT91C_PA10_ETX2_0 (AT91C_PIO_PA10) // Ethernet MAC Transmit Data 2
#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11
#define AT91C_PA11_MCDA3 (AT91C_PIO_PA11) // Multimedia Card A Data 3
#define AT91C_PA11_ETX3_0 (AT91C_PIO_PA11) // Ethernet MAC Transmit Data 3
#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12
#define AT91C_PA12_ETX0 (AT91C_PIO_PA12) // Ethernet MAC Transmit Data 0
#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13
#define AT91C_PA13_ETX1 (AT91C_PIO_PA13) // Ethernet MAC Transmit Data 1
#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14
#define AT91C_PA14_ERX0 (AT91C_PIO_PA14) // Ethernet MAC Receive Data 0
#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15
#define AT91C_PA15_ERX1 (AT91C_PIO_PA15) // Ethernet MAC Receive Data 1
#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16
#define AT91C_PA16_ETXEN (AT91C_PIO_PA16) // Ethernet MAC Transmit Enable
#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17
#define AT91C_PA17_ERXDV (AT91C_PIO_PA17) // Ethernet MAC Receive Data Valid
#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18
#define AT91C_PA18_ERXER (AT91C_PIO_PA18) // Ethernet MAC Receive Error
#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19
#define AT91C_PA19_ETXCK (AT91C_PIO_PA19) // Ethernet MAC Transmit Clock/Reference Clock
#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2
#define AT91C_PA2_SPI0_SPCK (AT91C_PIO_PA2) // SPI 0 Serial Clock
#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20
#define AT91C_PA20_EMDC (AT91C_PIO_PA20) // Ethernet MAC Management Data Clock
#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21
#define AT91C_PA21_EMDIO (AT91C_PIO_PA21) // Ethernet MAC Management Data Input/Output
#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22
#define AT91C_PA22_ADTRG (AT91C_PIO_PA22) // ADC Trigger
#define AT91C_PA22_ETXER (AT91C_PIO_PA22) // Ethernet MAC Transmikt Coding Error
#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23
#define AT91C_PA23_TWD0 (AT91C_PIO_PA23) // TWI Two-wire Serial Data 0
#define AT91C_PA23_ETX2_1 (AT91C_PIO_PA23) // Ethernet MAC Transmit Data 2
#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24
#define AT91C_PA24_TWCK0 (AT91C_PIO_PA24) // TWI Two-wire Serial Clock 0
#define AT91C_PA24_ETX3_1 (AT91C_PIO_PA24) // Ethernet MAC Transmit Data 3
#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25
#define AT91C_PA25_TCLK0 (AT91C_PIO_PA25) // Timer Counter 0 external clock input
#define AT91C_PA25_ERX2 (AT91C_PIO_PA25) // Ethernet MAC Receive Data 2
#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26
#define AT91C_PA26_TIOA0 (AT91C_PIO_PA26) // Timer Counter 0 Multipurpose Timer I/O Pin A
#define AT91C_PA26_ERX3 (AT91C_PIO_PA26) // Ethernet MAC Receive Data 3
#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27
#define AT91C_PA27_TIOA1 (AT91C_PIO_PA27) // Timer Counter 1 Multipurpose Timer I/O Pin A
#define AT91C_PA27_ERXCK (AT91C_PIO_PA27) // Ethernet MAC Receive Clock
#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28
#define AT91C_PA28_TIOA2 (AT91C_PIO_PA28) // Timer Counter 2 Multipurpose Timer I/O Pin A
#define AT91C_PA28_ECRS (AT91C_PIO_PA28) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29
#define AT91C_PA29_SCK1 (AT91C_PIO_PA29) // USART 1 Serial Clock
#define AT91C_PA29_ECOL (AT91C_PIO_PA29) // Ethernet MAC Collision Detected
#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3
#define AT91C_PA3_SPI0_NPCS0 (AT91C_PIO_PA3) // SPI 0 Peripheral Chip Select 0
#define AT91C_PA3_MCDB3 (AT91C_PIO_PA3) // Multimedia Card B Data 3
#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30
#define AT91C_PA30_SCK2 (AT91C_PIO_PA30) // USART 2 Serial Clock
#define AT91C_PA30_RXD4 (AT91C_PIO_PA30) // USART 4 Receive Data
#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31
#define AT91C_PA31_SCK0 (AT91C_PIO_PA31) // USART 0 Serial Clock
#define AT91C_PA31_TXD4 (AT91C_PIO_PA31) // USART 4 Transmit Data
#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4
#define AT91C_PA4_RTS2 (AT91C_PIO_PA4) // USART 2 Ready To Send
#define AT91C_PA4_MCDB2 (AT91C_PIO_PA4) // Multimedia Card B Data 2
#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5
#define AT91C_PA5_CTS2 (AT91C_PIO_PA5) // USART 2 Clear To Send
#define AT91C_PA5_MCDB1 (AT91C_PIO_PA5) // Multimedia Card B Data 1
#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6
#define AT91C_PA6_MCDA0 (AT91C_PIO_PA6) // Multimedia Card A Data 0
#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7
#define AT91C_PA7_MCCDA (AT91C_PIO_PA7) // Multimedia Card A Command
#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8
#define AT91C_PA8_MCCK (AT91C_PIO_PA8) // Multimedia Card Clock
#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9
#define AT91C_PA9_MCDA1 (AT91C_PIO_PA9) // Multimedia Card A Data 1
#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0
#define AT91C_PB0_SPI1_MISO (AT91C_PIO_PB0) // SPI 1 Master In Slave
#define AT91C_PB0_TIOA3 (AT91C_PIO_PB0) // Timer Counter 3 Multipurpose Timer I/O Pin A
#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1
#define AT91C_PB1_SPI1_MOSI (AT91C_PIO_PB1) // SPI 1 Master Out Slave
#define AT91C_PB1_TIOB3 (AT91C_PIO_PB1) // Timer Counter 3 Multipurpose Timer I/O Pin B
#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10
#define AT91C_PB10_TXD3 (AT91C_PIO_PB10) // USART 3 Transmit Data
#define AT91C_PB10_ISI_D8 (AT91C_PIO_PB10) // Image Sensor Data 8
#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11
#define AT91C_PB11_RXD3 (AT91C_PIO_PB11) // USART 3 Receive Data
#define AT91C_PB11_ISI_D9 (AT91C_PIO_PB11) // Image Sensor Data 9
#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12
#define AT91C_PB12_TWD1 (AT91C_PIO_PB12) // TWI Two-wire Serial Data 1
#define AT91C_PB12_ISI_D10 (AT91C_PIO_PB12) // Image Sensor Data 10
#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13
#define AT91C_PB13_TWCK1 (AT91C_PIO_PB13) // TWI Two-wire Serial Clock 1
#define AT91C_PB13_ISI_D11 (AT91C_PIO_PB13) // Image Sensor Data 11
#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14
#define AT91C_PB14_DRXD (AT91C_PIO_PB14) // DBGU Debug Receive Data
#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15
#define AT91C_PB15_DTXD (AT91C_PIO_PB15) // DBGU Debug Transmit Data
#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16
#define AT91C_PB16_TK0 (AT91C_PIO_PB16) // SSC0 Transmit Clock
#define AT91C_PB16_TCLK3 (AT91C_PIO_PB16) // Timer Counter 3 external clock input
#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17
#define AT91C_PB17_TF0 (AT91C_PIO_PB17) // SSC0 Transmit Frame Sync
#define AT91C_PB17_TCLK4 (AT91C_PIO_PB17) // Timer Counter 4 external clock input
#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18
#define AT91C_PB18_TD0 (AT91C_PIO_PB18) // SSC0 Transmit data
#define AT91C_PB18_TIOB4 (AT91C_PIO_PB18) // Timer Counter 4 Multipurpose Timer I/O Pin B
#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19
#define AT91C_PB19_RD0 (AT91C_PIO_PB19) // SSC0 Receive Data
#define AT91C_PB19_TIOB5 (AT91C_PIO_PB19) // Timer Counter 5 Multipurpose Timer I/O Pin B
#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2
#define AT91C_PB2_SPI1_SPCK (AT91C_PIO_PB2) // SPI 1 Serial Clock
#define AT91C_PB2_TIOA4 (AT91C_PIO_PB2) // Timer Counter 4 Multipurpose Timer I/O Pin A
#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20
#define AT91C_PB20_RK0 (AT91C_PIO_PB20) // SSC0 Receive Clock
#define AT91C_PB20_ISI_D0 (AT91C_PIO_PB20) // Image Sensor Data 0
#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21
#define AT91C_PB21_RF0 (AT91C_PIO_PB21) // SSC0 Receive Frame Sync
#define AT91C_PB21_ISI_D1 (AT91C_PIO_PB21) // Image Sensor Data 1
#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22
#define AT91C_PB22_DSR0 (AT91C_PIO_PB22) // USART 0 Data Set ready
#define AT91C_PB22_ISI_D2 (AT91C_PIO_PB22) // Image Sensor Data 2
#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23
#define AT91C_PB23_DCD0 (AT91C_PIO_PB23) // USART 0 Data Carrier Detect
#define AT91C_PB23_ISI_D3 (AT91C_PIO_PB23) // Image Sensor Data 3
#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24
#define AT91C_PB24_DTR0 (AT91C_PIO_PB24) // USART 0 Data Terminal ready
#define AT91C_PB24_ISI_D4 (AT91C_PIO_PB24) // Image Sensor Data 4
#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25
#define AT91C_PB25_RI0 (AT91C_PIO_PB25) // USART 0 Ring Indicator
#define AT91C_PB25_ISI_D5 (AT91C_PIO_PB25) // Image Sensor Data 5
#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26
#define AT91C_PB26_RTS0 (AT91C_PIO_PB26) // USART 0 Ready To Send
#define AT91C_PB26_ISI_D6 (AT91C_PIO_PB26) // Image Sensor Data 6
#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27
#define AT91C_PB27_CTS0 (AT91C_PIO_PB27) // USART 0 Clear To Send
#define AT91C_PB27_ISI_D7 (AT91C_PIO_PB27) // Image Sensor Data 7
#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28
#define AT91C_PB28_RTS1 (AT91C_PIO_PB28) // USART 1 Ready To Send
#define AT91C_PB28_ISI_PCK (AT91C_PIO_PB28) // Image Sensor Data Clock
#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29
#define AT91C_PB29_CTS1 (AT91C_PIO_PB29) // USART 1 Clear To Send
#define AT91C_PB29_ISI_VSYNC (AT91C_PIO_PB29) // Image Sensor Vertical Synchro
#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3
#define AT91C_PB3_SPI1_NPCS0 (AT91C_PIO_PB3) // SPI 1 Peripheral Chip Select 0
#define AT91C_PB3_TIOA5 (AT91C_PIO_PB3) // Timer Counter 5 Multipurpose Timer I/O Pin A
#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30
#define AT91C_PB30_PCK0_0 (AT91C_PIO_PB30) // PMC Programmable Clock Output 0
#define AT91C_PB30_ISI_HSYNC (AT91C_PIO_PB30) // Image Sensor Horizontal Synchro
#define AT91C_PIO_PB31 (1 << 31) // Pin Controlled by PB31
#define AT91C_PB31_PCK1_0 (AT91C_PIO_PB31) // PMC Programmable Clock Output 1
#define AT91C_PB31_ISI_MCK (AT91C_PIO_PB31) // Image Sensor Reference Clock
#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4
#define AT91C_PB4_TXD0 (AT91C_PIO_PB4) // USART 0 Transmit Data
#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5
#define AT91C_PB5_RXD0 (AT91C_PIO_PB5) // USART 0 Receive Data
#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6
#define AT91C_PB6_TXD1 (AT91C_PIO_PB6) // USART 1 Transmit Data
#define AT91C_PB6_TCLK1 (AT91C_PIO_PB6) // Timer Counter 1 external clock input
#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7
#define AT91C_PB7_RXD1 (AT91C_PIO_PB7) // USART 1 Receive Data
#define AT91C_PB7_TCLK2 (AT91C_PIO_PB7) // Timer Counter 2 external clock input
#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8
#define AT91C_PB8_TXD2 (AT91C_PIO_PB8) // USART 2 Transmit Data
#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9
#define AT91C_PB9_RXD2 (AT91C_PIO_PB9) // USART 2 Receive Data
#define AT91C_PIO_PC0 (1 << 0) // Pin Controlled by PC0
#define AT91C_PC0_AD0 (AT91C_PIO_PC0) // ADC Analog Input 0
#define AT91C_PC0_SCK3 (AT91C_PIO_PC0) // USART 3 Serial Clock
#define AT91C_PIO_PC1 (1 << 1) // Pin Controlled by PC1
#define AT91C_PC1_AD1 (AT91C_PIO_PC1) // ADC Analog Input 1
#define AT91C_PC1_PCK0 (AT91C_PIO_PC1) // PMC Programmable Clock Output 0
#define AT91C_PIO_PC10 (1 << 10) // Pin Controlled by PC10
#define AT91C_PC10_A25_CFRNW (AT91C_PIO_PC10) // Address Bus[25]
#define AT91C_PC10_CTS3 (AT91C_PIO_PC10) // USART 3 Clear To Send
#define AT91C_PIO_PC11 (1 << 11) // Pin Controlled by PC11
#define AT91C_PC11_NCS2 (AT91C_PIO_PC11) // Chip Select Line 2
#define AT91C_PC11_SPI0_NPCS1 (AT91C_PIO_PC11) // SPI 0 Peripheral Chip Select 1
#define AT91C_PIO_PC12 (1 << 12) // Pin Controlled by PC12
#define AT91C_PC12_IRQ0 (AT91C_PIO_PC12) // External Interrupt 0
#define AT91C_PC12_NCS7 (AT91C_PIO_PC12) // Chip Select Line 7
#define AT91C_PIO_PC13 (1 << 13) // Pin Controlled by PC13
#define AT91C_PC13_FIQ (AT91C_PIO_PC13) // AIC Fast Interrupt Input
#define AT91C_PC13_NCS6 (AT91C_PIO_PC13) // Chip Select Line 6
#define AT91C_PIO_PC14 (1 << 14) // Pin Controlled by PC14
#define AT91C_PC14_NCS3_NANDCS (AT91C_PIO_PC14) // Chip Select Line 3
#define AT91C_PC14_IRQ2 (AT91C_PIO_PC14) // External Interrupt 2
#define AT91C_PIO_PC15 (1 << 15) // Pin Controlled by PC15
#define AT91C_PC15_NWAIT (AT91C_PIO_PC15) // External Wait Signal
#define AT91C_PC15_IRQ1 (AT91C_PIO_PC15) // External Interrupt 1
#define AT91C_PIO_PC16 (1 << 16) // Pin Controlled by PC16
#define AT91C_PC16_D16 (AT91C_PIO_PC16) // Data Bus[16]
#define AT91C_PC16_SPI0_NPCS2 (AT91C_PIO_PC16) // SPI 0 Peripheral Chip Select 2
#define AT91C_PIO_PC17 (1 << 17) // Pin Controlled by PC17
#define AT91C_PC17_D17 (AT91C_PIO_PC17) // Data Bus[17]
#define AT91C_PC17_SPI0_NPCS3 (AT91C_PIO_PC17) // SPI 0 Peripheral Chip Select 3
#define AT91C_PIO_PC18 (1 << 18) // Pin Controlled by PC18
#define AT91C_PC18_D18 (AT91C_PIO_PC18) // Data Bus[18]
#define AT91C_PC18_SPI1_NPCS1_1 (AT91C_PIO_PC18) // SPI 1 Peripheral Chip Select 1
#define AT91C_PIO_PC19 (1 << 19) // Pin Controlled by PC19
#define AT91C_PC19_D19 (AT91C_PIO_PC19) // Data Bus[19]
#define AT91C_PC19_SPI1_NPCS2_1 (AT91C_PIO_PC19) // SPI 1 Peripheral Chip Select 2
#define AT91C_PIO_PC2 (1 << 2) // Pin Controlled by PC2
#define AT91C_PC2_AD2 (AT91C_PIO_PC2) // ADC Analog Input 2
#define AT91C_PC2_PCK1 (AT91C_PIO_PC2) // PMC Programmable Clock Output 1
#define AT91C_PIO_PC20 (1 << 20) // Pin Controlled by PC20
#define AT91C_PC20_D20 (AT91C_PIO_PC20) // Data Bus[20]
#define AT91C_PC20_SPI1_NPCS3_1 (AT91C_PIO_PC20) // SPI 1 Peripheral Chip Select 3
#define AT91C_PIO_PC21 (1 << 21) // Pin Controlled by PC21
#define AT91C_PC21_D21 (AT91C_PIO_PC21) // Data Bus[21]
#define AT91C_PC21_EF100 (AT91C_PIO_PC21) // Ethernet MAC Force 100 Mbits/sec
#define AT91C_PIO_PC22 (1 << 22) // Pin Controlled by PC22
#define AT91C_PC22_D22 (AT91C_PIO_PC22) // Data Bus[22]
#define AT91C_PC22_TCLK5 (AT91C_PIO_PC22) // Timer Counter 5 external clock input
#define AT91C_PIO_PC23 (1 << 23) // Pin Controlled by PC23
#define AT91C_PC23_D23 (AT91C_PIO_PC23) // Data Bus[23]
#define AT91C_PIO_PC24 (1 << 24) // Pin Controlled by PC24
#define AT91C_PC24_D24 (AT91C_PIO_PC24) // Data Bus[24]
#define AT91C_PIO_PC25 (1 << 25) // Pin Controlled by PC25
#define AT91C_PC25_D25 (AT91C_PIO_PC25) // Data Bus[25]
#define AT91C_PIO_PC26 (1 << 26) // Pin Controlled by PC26
#define AT91C_PC26_D26 (AT91C_PIO_PC26) // Data Bus[26]
#define AT91C_PIO_PC27 (1 << 27) // Pin Controlled by PC27
#define AT91C_PC27_D27 (AT91C_PIO_PC27) // Data Bus[27]
#define AT91C_PIO_PC28 (1 << 28) // Pin Controlled by PC28
#define AT91C_PC28_D28 (AT91C_PIO_PC28) // Data Bus[28]
#define AT91C_PIO_PC29 (1 << 29) // Pin Controlled by PC29
#define AT91C_PC29_D29 (AT91C_PIO_PC29) // Data Bus[29]
#define AT91C_PIO_PC3 (1 << 3) // Pin Controlled by PC3
#define AT91C_PC3_AD3 (AT91C_PIO_PC3) // ADC Analog Input 3
#define AT91C_PC3_SPI1_NPCS3_0 (AT91C_PIO_PC3) // SPI 1 Peripheral Chip Select 3
#define AT91C_PIO_PC30 (1 << 30) // Pin Controlled by PC30
#define AT91C_PC30_D30 (AT91C_PIO_PC30) // Data Bus[30]
#define AT91C_PIO_PC31 (1 << 31) // Pin Controlled by PC31
#define AT91C_PC31_D31 (AT91C_PIO_PC31) // Data Bus[31]
#define AT91C_PIO_PC4 (1 << 4) // Pin Controlled by PC4
#define AT91C_PC4_A23 (AT91C_PIO_PC4) // Address Bus[23]
#define AT91C_PC4_SPI1_NPCS2_0 (AT91C_PIO_PC4) // SPI 1 Peripheral Chip Select 2
#define AT91C_PIO_PC5 (1 << 5) // Pin Controlled by PC5
#define AT91C_PC5_A24 (AT91C_PIO_PC5) // Address Bus[24]
#define AT91C_PC5_SPI1_NPCS1_0 (AT91C_PIO_PC5) // SPI 1 Peripheral Chip Select 1
#define AT91C_PIO_PC6 (1 << 6) // Pin Controlled by PC6
#define AT91C_PC6_TIOB2 (AT91C_PIO_PC6) // Timer Counter 2 Multipurpose Timer I/O Pin B
#define AT91C_PC6_CFCE1 (AT91C_PIO_PC6) // Compact Flash Enable 1
#define AT91C_PIO_PC7 (1 << 7) // Pin Controlled by PC7
#define AT91C_PC7_TIOB1 (AT91C_PIO_PC7) // Timer Counter 1 Multipurpose Timer I/O Pin B
#define AT91C_PC7_CFCE2 (AT91C_PIO_PC7) // Compact Flash Enable 2
#define AT91C_PIO_PC8 (1 << 8) // Pin Controlled by PC8
#define AT91C_PC8_NCS4_CFCS0 (AT91C_PIO_PC8) // Chip Select Line 4
#define AT91C_PC8_RTS3 (AT91C_PIO_PC8) // USART 3 Ready To Send
#define AT91C_PIO_PC9 (1 << 9) // Pin Controlled by PC9
#define AT91C_PC9_NCS5_CFCS1 (AT91C_PIO_PC9) // Chip Select Line 5
#define AT91C_PC9_TIOB0 (AT91C_PIO_PC9) // Timer Counter 0 Multipurpose Timer I/O Pin B
// *****************************************************************************
// PERIPHERAL ID DEFINITIONS FOR AT91SAM9XE128
// *****************************************************************************
#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)
#define AT91C_ID_SYS ( 1) // System Controller
#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A
#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B
#define AT91C_ID_PIOC ( 4) // Parallel IO Controller C
#define AT91C_ID_ADC ( 5) // ADC
#define AT91C_ID_US0 ( 6) // USART 0
#define AT91C_ID_US1 ( 7) // USART 1
#define AT91C_ID_US2 ( 8) // USART 2
#define AT91C_ID_MCI ( 9) // Multimedia Card Interface 0
#define AT91C_ID_UDP (10) // USB Device Port
#define AT91C_ID_TWI0 (11) // Two-Wire Interface 0
#define AT91C_ID_SPI0 (12) // Serial Peripheral Interface 0
#define AT91C_ID_SPI1 (13) // Serial Peripheral Interface 1
#define AT91C_ID_SSC0 (14) // Serial Synchronous Controller 0
#define AT91C_ID_TC0 (17) // Timer Counter 0
#define AT91C_ID_TC1 (18) // Timer Counter 1
#define AT91C_ID_TC2 (19) // Timer Counter 2
#define AT91C_ID_UHP (20) // USB Host Port
#define AT91C_ID_EMAC (21) // Ethernet Mac
#define AT91C_ID_HISI (22) // Image Sensor Interface
#define AT91C_ID_US3 (23) // USART 3
#define AT91C_ID_US4 (24) // USART 4
#define AT91C_ID_TWI1 (25) // Two-Wire Interface 1
#define AT91C_ID_TC3 (26) // Timer Counter 3
#define AT91C_ID_TC4 (27) // Timer Counter 4
#define AT91C_ID_TC5 (28) // Timer Counter 5
#define AT91C_ID_IRQ0 (29) // Advanced Interrupt Controller (IRQ0)
#define AT91C_ID_IRQ1 (30) // Advanced Interrupt Controller (IRQ1)
#define AT91C_ID_IRQ2 (31) // Advanced Interrupt Controller (IRQ2)
#define AT91C_ALL_INT (0xFFFE7FFF) // ALL VALID INTERRUPTS
// *****************************************************************************
// BASE ADDRESS DEFINITIONS FOR AT91SAM9XE128
// *****************************************************************************
#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFFD00) // (SYS) Base Address
#define AT91C_BASE_EBI (AT91_CAST(AT91PS_EBI) 0xFFFFEA00) // (EBI) Base Address
#define AT91C_BASE_HECC (AT91_CAST(AT91PS_ECC) 0xFFFFE800) // (HECC) Base Address
#define AT91C_BASE_SDRAMC (AT91_CAST(AT91PS_SDRAMC) 0xFFFFEA00) // (SDRAMC) Base Address
#define AT91C_BASE_SMC (AT91_CAST(AT91PS_SMC) 0xFFFFEC00) // (SMC) Base Address
#define AT91C_BASE_MATRIX (AT91_CAST(AT91PS_MATRIX) 0xFFFFEE00) // (MATRIX) Base Address
#define AT91C_BASE_CCFG (AT91_CAST(AT91PS_CCFG) 0xFFFFEF10) // (CCFG) Base Address
#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address
#define AT91C_BASE_PIOC (AT91_CAST(AT91PS_PIO) 0xFFFFF800) // (PIOC) Base Address
#define AT91C_BASE_EFC (AT91_CAST(AT91PS_EFC) 0xFFFFFA00) // (EFC) Base Address
#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
#define AT91C_BASE_SHDWC (AT91_CAST(AT91PS_SHDWC) 0xFFFFFD10) // (SHDWC) Base Address
#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
#define AT91C_BASE_TC3 (AT91_CAST(AT91PS_TC) 0xFFFDC000) // (TC3) Base Address
#define AT91C_BASE_TC4 (AT91_CAST(AT91PS_TC) 0xFFFDC040) // (TC4) Base Address
#define AT91C_BASE_TC5 (AT91_CAST(AT91PS_TC) 0xFFFDC080) // (TC5) Base Address
#define AT91C_BASE_TCB0 (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB0) Base Address
#define AT91C_BASE_TCB1 (AT91_CAST(AT91PS_TCB) 0xFFFDC000) // (TCB1) Base Address
#define AT91C_BASE_PDC_MCI (AT91_CAST(AT91PS_PDC) 0xFFFA8100) // (PDC_MCI) Base Address
#define AT91C_BASE_MCI (AT91_CAST(AT91PS_MCI) 0xFFFA8000) // (MCI) Base Address
#define AT91C_BASE_PDC_TWI0 (AT91_CAST(AT91PS_PDC) 0xFFFAC100) // (PDC_TWI0) Base Address
#define AT91C_BASE_TWI0 (AT91_CAST(AT91PS_TWI) 0xFFFAC000) // (TWI0) Base Address
#define AT91C_BASE_PDC_TWI1 (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_TWI1) Base Address
#define AT91C_BASE_TWI1 (AT91_CAST(AT91PS_TWI) 0xFFFD8000) // (TWI1) Base Address
#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFB0100) // (PDC_US0) Base Address
#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFB0000) // (US0) Base Address
#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFB4100) // (PDC_US1) Base Address
#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFB4000) // (US1) Base Address
#define AT91C_BASE_PDC_US2 (AT91_CAST(AT91PS_PDC) 0xFFFB8100) // (PDC_US2) Base Address
#define AT91C_BASE_US2 (AT91_CAST(AT91PS_USART) 0xFFFB8000) // (US2) Base Address
#define AT91C_BASE_PDC_US3 (AT91_CAST(AT91PS_PDC) 0xFFFD0100) // (PDC_US3) Base Address
#define AT91C_BASE_US3 (AT91_CAST(AT91PS_USART) 0xFFFD0000) // (US3) Base Address
#define AT91C_BASE_PDC_US4 (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_US4) Base Address
#define AT91C_BASE_US4 (AT91_CAST(AT91PS_USART) 0xFFFD4000) // (US4) Base Address
#define AT91C_BASE_PDC_SSC0 (AT91_CAST(AT91PS_PDC) 0xFFFBC100) // (PDC_SSC0) Base Address
#define AT91C_BASE_SSC0 (AT91_CAST(AT91PS_SSC) 0xFFFBC000) // (SSC0) Base Address
#define AT91C_BASE_PDC_SPI0 (AT91_CAST(AT91PS_PDC) 0xFFFC8100) // (PDC_SPI0) Base Address
#define AT91C_BASE_SPI0 (AT91_CAST(AT91PS_SPI) 0xFFFC8000) // (SPI0) Base Address
#define AT91C_BASE_PDC_SPI1 (AT91_CAST(AT91PS_PDC) 0xFFFCC100) // (PDC_SPI1) Base Address
#define AT91C_BASE_SPI1 (AT91_CAST(AT91PS_SPI) 0xFFFCC000) // (SPI1) Base Address
#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_ADC) Base Address
#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFE0000) // (ADC) Base Address
#define AT91C_BASE_EMACB (AT91_CAST(AT91PS_EMAC) 0xFFFC4000) // (EMACB) Base Address
#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFA4000) // (UDP) Base Address
#define AT91C_BASE_UHP (AT91_CAST(AT91PS_UHP) 0x00500000) // (UHP) Base Address
#define AT91C_BASE_HISI (AT91_CAST(AT91PS_ISI) 0xFFFC0000) // (HISI) Base Address
// *****************************************************************************
// MEMORY MAPPING DEFINITIONS FOR AT91SAM9XE128
// *****************************************************************************
// IROM
#define AT91C_IROM (0x00100000) // Internal ROM base address
#define AT91C_IROM_SIZE (0x00008000) // Internal ROM size in byte (32 Kbytes)
// ISRAM
#define AT91C_ISRAM (0x00300000) // Maximum IRAM Area : 16Kbyte base address
#define AT91C_ISRAM_SIZE (0x00004000) // Maximum IRAM Area : 16Kbyte size in byte (16 Kbytes)
// ISRAM_MIN
#define AT91C_ISRAM_MIN (0x00300000) // Minimun IRAM Area : 16Kbyte base address
#define AT91C_ISRAM_MIN_SIZE (0x00004000) // Minimun IRAM Area : 16Kbyte size in byte (16 Kbytes)
// IFLASH
#define AT91C_IFLASH (0x00200000) // Maximum IFLASH Area : 128Kbyte base address
#define AT91C_IFLASH_SIZE (0x00020000) // Maximum IFLASH Area : 128Kbyte size in byte (128 Kbytes)
#define AT91C_IFLASH_PAGE_SIZE (512) // Maximum IFLASH Area : 128Kbyte Page Size: 512 bytes
#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Maximum IFLASH Area : 128Kbyte Lock Region Size: 16 Kbytes
#define AT91C_IFLASH_NB_OF_PAGES (256) // Maximum IFLASH Area : 128Kbyte Number of Pages: 256 bytes
#define AT91C_IFLASH_NB_OF_LOCK_BITS (8) // Maximum IFLASH Area : 128Kbyte Number of Lock Bits: 8 bytes
// EBI_CS0
#define AT91C_EBI_CS0 (0x10000000) // EBI Chip Select 0 base address
#define AT91C_EBI_CS0_SIZE (0x10000000) // EBI Chip Select 0 size in byte (262144 Kbytes)
// EBI_CS1
#define AT91C_EBI_CS1 (0x20000000) // EBI Chip Select 1 base address
#define AT91C_EBI_CS1_SIZE (0x10000000) // EBI Chip Select 1 size in byte (262144 Kbytes)
// EBI_SDRAM
#define AT91C_EBI_SDRAM (0x20000000) // SDRAM on EBI Chip Select 1 base address
#define AT91C_EBI_SDRAM_SIZE (0x10000000) // SDRAM on EBI Chip Select 1 size in byte (262144 Kbytes)
// EBI_SDRAM_16BIT
#define AT91C_EBI_SDRAM_16BIT (0x20000000) // SDRAM on EBI Chip Select 1 base address
#define AT91C_EBI_SDRAM_16BIT_SIZE (0x02000000) // SDRAM on EBI Chip Select 1 size in byte (32768 Kbytes)
// EBI_SDRAM_32BIT
#define AT91C_EBI_SDRAM_32BIT (0x20000000) // SDRAM on EBI Chip Select 1 base address
#define AT91C_EBI_SDRAM_32BIT_SIZE (0x04000000) // SDRAM on EBI Chip Select 1 size in byte (65536 Kbytes)
// EBI_CS2
#define AT91C_EBI_CS2 (0x30000000) // EBI Chip Select 2 base address
#define AT91C_EBI_CS2_SIZE (0x10000000) // EBI Chip Select 2 size in byte (262144 Kbytes)
// EBI_CS3
#define AT91C_EBI_CS3 (0x40000000) // EBI Chip Select 3 base address
#define AT91C_EBI_CS3_SIZE (0x10000000) // EBI Chip Select 3 size in byte (262144 Kbytes)
// EBI_SM
#define AT91C_EBI_SM (0x40000000) // SmartMedia on Chip Select 3 base address
#define AT91C_EBI_SM_SIZE (0x10000000) // SmartMedia on Chip Select 3 size in byte (262144 Kbytes)
// EBI_CS4
#define AT91C_EBI_CS4 (0x50000000) // EBI Chip Select 4 base address
#define AT91C_EBI_CS4_SIZE (0x10000000) // EBI Chip Select 4 size in byte (262144 Kbytes)
// EBI_CF0
#define AT91C_EBI_CF0 (0x50000000) // CompactFlash 0 on Chip Select 4 base address
#define AT91C_EBI_CF0_SIZE (0x10000000) // CompactFlash 0 on Chip Select 4 size in byte (262144 Kbytes)
// EBI_CS5
#define AT91C_EBI_CS5 (0x60000000) // EBI Chip Select 5 base address
#define AT91C_EBI_CS5_SIZE (0x10000000) // EBI Chip Select 5 size in byte (262144 Kbytes)
// EBI_CF1
#define AT91C_EBI_CF1 (0x60000000) // CompactFlash 1 on Chip Select 5 base address
#define AT91C_EBI_CF1_SIZE (0x10000000) // CompactFlash 1 on Chip Select 5 size in byte (262144 Kbytes)
// EBI_CS6
#define AT91C_EBI_CS6 (0x70000000) // EBI Chip Select 6 base address
#define AT91C_EBI_CS6_SIZE (0x10000000) // EBI Chip Select 6 size in byte (262144 Kbytes)
// EBI_CS7
#define AT91C_EBI_CS7 (0x80000000) // EBI Chip Select 7 base address
#define AT91C_EBI_CS7_SIZE (0x10000000) // EBI Chip Select 7 size in byte (262144 Kbytes)
#endif
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe128/AT91SAM9XE128.h | C | oos | 306,020 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
/// \dir
/// !Purpose
///
/// Definition and functions for using AT91SAM9XE-related features, such
/// has PIO pins, memories, etc.
///
/// !Usage
/// -# The code for booting the board is provided by board_cstartup.S and
/// board_lowlevel.c.
/// -# For using board PIOs, board characteristics (clock, etc.) and external
/// components, see board.h.
/// -# For manipulating memories (remapping, SDRAM, etc.), see board_memories.h.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// \unit
/// !Purpose
///
/// Definition of AT91SAM9XE-EK characteristics, AT91SAM9XE-dependant PIOs and
/// external components interfacing.
///
/// !Usage
/// -# For operating frequency information, see "SAM9XE-EK - Operating frequencies".
/// -# For using portable PIO definitions, see "SAM9XE-EK - PIO definitions".
/// -# Several USB definitions are included here (see "SAM9XE-EK - USB device").
/// -# For external components definitions, see "SAM79260-EK - External components".
/// -# For memory-related definitions, see "SAM79260-EK - Memories".
//------------------------------------------------------------------------------
#ifndef BOARD_H
#define BOARD_H
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#if defined(at91sam9xe128)
#include "at91sam9xe128/AT91SAM9XE128.h"
#elif defined(at91sam9xe256)
#include "at91sam9xe256/AT91SAM9XE256.h"
#elif defined(at91sam9xe512)
#include "at91sam9xe512/AT91SAM9XE512.h"
#else
#error Board does not support the specified chip.
#endif
//------------------------------------------------------------------------------
// Definitions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// \page "SAM9XE-EK - Board Description"
/// This page lists several definition related to the board description.
///
/// !Definitions
/// - BOARD_NAME
/// Name of the board.
#define BOARD_NAME "AT91SAM9XE-EK"
/// Board definition.
#define at91sam9xeek
/// Family definition.
#define at91sam9xe
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// \page "SAM9XE-EK - Operating frequencies"
/// This page lists several definition related to the board operating frequency
/// (when using the initialization done by board_lowlevel.c).
///
/// !Definitions
/// - BOARD_MAINOSC
/// - BOARD_MCK
/// Frequency of the board main oscillator.
#define BOARD_MAINOSC 18432000
/// Master clock frequency (when using board_lowlevel.c).
#define BOARD_MCK ((18432000 * 97 / 9) / 2)
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// \page "SAM9XE-EK - USB device"
/// This page lists constants describing several characteristics (controller
/// type, D+ pull-up type, etc.) of the USB device controller of the chip/board.
///
/// !Constants
/// - BOARD_USB_UDP
/// - BOARD_USB_PULLUP_INTERNAL
/// - BOARD_USB_NUMENDPOINTS
/// - BOARD_USB_ENDPOINTS_MAXPACKETSIZE
/// - BOARD_USB_ENDPOINTS_BANKS
/// - BOARD_USB_BMATTRIBUTES
/// Chip has a UDP controller.
#define BOARD_USB_UDP
/// Indicates the D+ pull-up is internal to the USB controller.
#define BOARD_USB_PULLUP_INTERNAL
/// Number of endpoints in the USB controller.
#define BOARD_USB_NUMENDPOINTS 6
/// Returns the maximum packet size of the given endpoint.
#define BOARD_USB_ENDPOINTS_MAXPACKETSIZE(i) ((i >= 4) ? 512 : 64)
#define BOARD_USB_ENDPOINTS_MAXPACKETSIZE_FS 64
/// Returns the number of FIFO banks for the given endpoint.
#define BOARD_USB_ENDPOINTS_BANKS(i) (((i == 0) || (i == 3)) ? 1 : 2)
/// USB attributes configuration descriptor (bus or self powered, remote wakeup)
#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// \page "SAM9XE-EK - PIO definitions"
/// This pages lists all the pio definitions contained in board.h. The constants
/// are named using the following convention: PIN_* for a constant which defines
/// a single Pin instance (but may include several PIOs sharing the same
/// controller), and PINS_* for a list of Pin instances.
///
/// !DBGU
/// - PINS_DBGU
///
/// !LEDs
/// - PIN_LED_0
/// - PIN_LED_1
/// - PINS_LEDS
/// - LED_POWER
/// - LED_DS1
///
/// !Push buttons
/// - PIN_PUSHBUTTON_1
/// - PIN_PUSHBUTTON_2
/// - PINS_PUSHBUTTONS
/// - PUSHBUTTON_BP1
/// - PUSHBUTTON_BP2
///
/// !USART0
/// - PIN_USART0_RXD
/// - PIN_USART0_TXD
/// - PIN_USART0_SCK
///
/// !SPI0
/// - PIN_SPI0_MISO
/// - PIN_SPI0_MOSI
/// - PIN_SPI0_SPCK
/// - PINS_SPI0
/// - PIN_SPI0_NPCS0
/// - PIN_SPI0_NPCS1
///
/// !SSC
/// - PINS_SSC_TX
///
/// !USB
/// - PIN_USB_VBUS
///
/// !MCI
/// - PINS_MCI
///
/// !TWI0
/// - PINS_TWI0
/// List of all DBGU pin definitions.
#define PINS_DBGU {(1<<14) | (1<<15), AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
/// LED #0 pin definition.
#define PIN_LED_0 {1 << 9, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT}
/// LED #1 pin definition.
#define PIN_LED_1 {1 << 6, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT}
/// List of all LED definitions.
#define PINS_LEDS PIN_LED_0, PIN_LED_1
/// Power LED index.
#define LED_POWER 0
/// DS1 LED index.
#define LED_DS1 1
/// Push button #1 pin definition.
#define PIN_PUSHBUTTON_1 {1 << 30, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_PULLUP}
/// Pusb button #2 pin definition.
#define PIN_PUSHBUTTON_2 {1UL << 31, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_PULLUP}
/// List of all pushbutton pin definitions.
#define PINS_PUSHBUTTONS PIN_PUSHBUTTON_1, PIN_PUSHBUTTON_2
/// Push button #1 index.
#define PUSHBUTTON_BP1 0
/// Push button #2 index.
#define PUSHBUTTON_BP2 1
/// USART0 TXD pin definition.
#define PIN_USART0_TXD {1 << 4, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
/// USART0 RXD pin definition.
#define PIN_USART0_RXD {1 << 5, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
/// USART0 RTS pin definition.
#define PIN_USART0_RTS {1 << 26, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
/// USART0 CTS pin definition.
#define PIN_USART0_CTS {1 << 27, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
/// USART0 SCK pin definition.
#define PIN_USART0_SCK {1UL << 31, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
/// SPI0 MISO pin definition.
#define PIN_SPI0_MISO {1 << 0, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_PULLUP}
/// SPI0 MOSI pin definition.
#define PIN_SPI0_MOSI {1 << 1, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
/// SPI0 SPCK pin definition.
#define PIN_SPI0_SPCK {1 << 2, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
/// List of SPI0 pin definitions (MISO, MOSI & SPCK).
#define PINS_SPI0 PIN_SPI0_MISO, PIN_SPI0_MOSI, PIN_SPI0_SPCK
/// SPI0 chip select 0 pin definition.
#define PIN_SPI0_NPCS0 {AT91C_PA3_SPI0_NPCS0, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
/// SPI0 chip select 1 pin definition.
#define PIN_SPI0_NPCS1 {AT91C_PC11_SPI0_NPCS1, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}
/// SSC transmitter pins definition.
#define PINS_SSC_TX {0x00038000, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
/// USB VBus monitoring pin definition.
#define PIN_USB_VBUS {1 << 5, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_INPUT, PIO_DEFAULT}
/// List of MCI pins definitions.
#define PINS_MCI {0x0000003B, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}, \
{1 << 8, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
/// TWI0 pins definition.
#define PINS_TWI0 {0x01800000, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// \page "SAM9XE-EK - External components"
/// This page lists the definitions related to external on-board components
/// located in the board.h file for the AT91SAM9XE-EK.
///
/// !AT45 Dataflash Card (A)
/// - BOARD_AT45_A_SPI_BASE
/// - BOARD_AT45_A_SPI_ID
/// - BOARD_AT45_A_SPI_PINS
/// - BOARD_AT45_A_SPI
/// - BOARD_AT45_A_NPCS
/// - BOARD_AT45_A_NPCS_PIN
///
/// !AT45 Dataflash (B)
/// - BOARD_AT45_B_SPI_BASE
/// - BOARD_AT45_B_SPI_ID
/// - BOARD_AT45_B_SPI_PINS
/// - BOARD_AT45_B_SPI
/// - BOARD_AT45_B_NPCS
/// - BOARD_AT45_B_NPCS_PIN
///
/// !SD Card
/// - BOARD_SD_MCI_BASE
/// - BOARD_SD_MCI_ID
/// - BOARD_SD_PINS
/// - BOARD_SD_SLOT
///
///
/// !EMAC
/// - AT91C_BASE_EMAC
/// - BOARD_EMAC_POWER_ALWAYS_ON
/// - BOARD_EMAC_MODE_RMII
/// - BOARD_EMAC_PINS
/// - BOARD_EMAC_PIN_TEST
/// - BOARD_EMAC_PIN_RPTR
/// - BOARD_EMAC_RST_PINS
/// - BOARD_EMAC_RUN_PINS
/// Base address of SPI peripheral connected to the dataflash.
#define BOARD_AT45_A_SPI_BASE AT91C_BASE_SPI0
/// Identifier of SPI peripheral connected to the dataflash.
#define BOARD_AT45_A_SPI_ID AT91C_ID_SPI0
/// Pins of the SPI peripheral connected to the dataflash.
#define BOARD_AT45_A_SPI_PINS PINS_SPI0
/// Dataflahs SPI number.
#define BOARD_AT45_A_SPI 0
/// Chip select connected to the dataflash.
#define BOARD_AT45_A_NPCS 0
/// Chip select pin connected to the dataflash.
#define BOARD_AT45_A_NPCS_PIN PIN_SPI0_NPCS0
/// Base address of SPI peripheral connected to the dataflash.
#define BOARD_AT45_B_SPI_BASE AT91C_BASE_SPI0
/// Identifier of SPI peripheral connected to the dataflash.
#define BOARD_AT45_B_SPI_ID AT91C_ID_SPI0
/// Pins of the SPI peripheral connected to the dataflash.
#define BOARD_AT45_B_SPI_PINS PINS_SPI0
/// Dataflahs SPI number.
#define BOARD_AT45_B_SPI 0
/// Chip select connected to the dataflash.
#define BOARD_AT45_B_NPCS 1
/// Chip select pin connected to the dataflash.
#define BOARD_AT45_B_NPCS_PIN PIN_SPI0_NPCS1
/// Base address of SPI peripheral connected to the serialflash.
#define BOARD_AT26_A_SPI_BASE AT91C_BASE_SPI0
/// Identifier of SPI peripheral connected to the dataflash.
#define BOARD_AT26_A_SPI_ID AT91C_ID_SPI0
/// Pins of the SPI peripheral connected to the dataflash.
#define BOARD_AT26_A_SPI_PINS PINS_SPI0
/// Dataflahs SPI number.
#define BOARD_AT26_A_SPI 0
/// Chip select connected to the dataflash.
#define BOARD_AT26_A_NPCS 0
/// Chip select pin connected to the dataflash.
#define BOARD_AT26_A_NPCS_PIN PIN_SPI0_NPCS0
/// Base address of the MCI peripheral connected to the SD card.
#define BOARD_SD_MCI_BASE AT91C_BASE_MCI
/// Peripheral identifier of the MCI connected to the SD card.
#define BOARD_SD_MCI_ID AT91C_ID_MCI
/// MCI pins that shall be configured to access the SD card.
#define BOARD_SD_PINS PINS_MCI
/// MCI slot to which the SD card is connected to.
#define BOARD_SD_SLOT MCI_SD_SLOTB
/// Board EMAC base address
#if !defined(AT91C_BASE_EMAC) && defined(AT91C_BASE_EMACB)
#define AT91C_BASE_EMAC AT91C_BASE_EMACB
#endif
/// Board EMAC power control - ALWAYS ON
#define BOARD_EMAC_POWER_ALWAYS_ON
/// Board EMAC work mode - RMII/MII ( 1 / 0 )
#define BOARD_EMAC_MODE_RMII 1
/// The PIN list of PIO for EMAC
#define BOARD_EMAC_PINS { ((1<<19)|(1<<13)|(1<<12)|(1<<16)|(1<<15)|(1<<14)\
|(1<<17)|(1<<18)|(1<<20)|(1<<21)|(1<<7)),\
AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT},\
{ ((1<<11)|(1<<10)|(1<<26)|(1<<25)|(1<<27)|(1<<22)\
|(1<<29)|(1<<28)),\
AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}
/// The power up reset latch PIO for PHY
#define BOARD_EMAC_PIN_TEST {(1<<17), AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT}
//#define BOARD_EMAC_PIN_RMII : connected to 3v3 (RMII)
// We force the address
// (1<<14) PHY address 0, (1<<15) PHY address 1 (PIO A, perih A)
// (1<<25) PHY address 2, (1<<26) PHY address 3 (PIO A, perih B)
#define BOARD_EMAC_PINS_PHYAD { ((1<<14)|(1<<15)),\
AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT},\
{ ((1<<25)|(1<<26)),\
AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT}
//#define BOARD_EMAC_PIN_10BT : not connected
#define BOARD_EMAC_PIN_RPTR {(1<<27), AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT}
/// The PIN Configure list for EMAC on power up reset
#define BOARD_EMAC_RST_PINS BOARD_EMAC_PINS_PHYAD,\
BOARD_EMAC_PIN_TEST,\
BOARD_EMAC_PIN_RPTR
/// The runtime pin configure list for EMAC
#define BOARD_EMAC_RUN_PINS BOARD_EMAC_PINS
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// \page "SAM9XE-EK - Memories"
/// This page lists definitions related to external on-board memories.
///
/// !Embedded Flash
/// - BOARD_FLASH_EEFC
///
/// !SDRAM
/// - BOARD_SDRAM_SIZE
/// - PINS_SDRAM
///
/// !Nandflash
/// - PINS_NANDFLASH
/// - BOARD_NF_COMMAND_ADDR
/// - BOARD_NF_ADDRESS_ADDR
/// - BOARD_NF_DATA_ADDR
/// - BOARD_NF_CE_PIN
/// - BOARD_NF_RB_PIN
/// Indicates chip has an Enhanced EFC.
#define BOARD_FLASH_EEFC
/// Address of the IAP function in ROM.
#define BOARD_FLASH_IAP_ADDRESS 0x100008
/// Board SDRAM size
#define BOARD_SDRAM_SIZE 0x02000000
/// List of all SDRAM pins definitions.
#define PINS_SDRAM {0xFFFF0000, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}
/// Nandflash controller peripheral pins definition.
#define PINS_NANDFLASH BOARD_NF_CE_PIN, BOARD_NF_RB_PIN
/// Nandflash chip enable pin definition.
#define BOARD_NF_CE_PIN {1 << 14, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT}
/// Nandflash ready/busy pin definition.
#define BOARD_NF_RB_PIN {1 << 13, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_INPUT, PIO_PULLUP}
/// Address for transferring command bytes to the nandflash.
#define BOARD_NF_COMMAND_ADDR 0x40400000
/// Address for transferring address bytes to the nandflash.
#define BOARD_NF_ADDRESS_ADDR 0x40200000
/// Address for transferring data bytes to the nandflash.
#define BOARD_NF_DATA_ADDR 0x40000000
/// Address for transferring command bytes to the norflash.
#define BOARD_NORFLASH_ADDR 0x10000000
//------------------------------------------------------------------------------
#endif //#ifndef BOARD_H
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board.h | C | oos | 17,281 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include <board.h>
#include <pio/pio.h>
//------------------------------------------------------------------------------
// Local macros
//------------------------------------------------------------------------------
/// Reads a register value. Useful to add trace information to read accesses.
#define READ(peripheral, register) (peripheral->register)
/// Writes data in a register. Useful to add trace information to write accesses.
#define WRITE(peripheral, register, value) (peripheral->register = value)
//------------------------------------------------------------------------------
// Global functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// Changes the mapping of the chip so that the remap area mirrors the
/// internal ROM or the EBI CS0 (depending on the BMS input).
//------------------------------------------------------------------------------
void BOARD_RemapRom(void)
{
WRITE(AT91C_BASE_MATRIX, MATRIX_MRCR, 0);
}
//------------------------------------------------------------------------------
/// Changes the mapping of the chip so that the remap area mirrors the
/// internal RAM.
//------------------------------------------------------------------------------
void BOARD_RemapRam(void)
{
WRITE(AT91C_BASE_MATRIX,
MATRIX_MRCR,
(AT91C_MATRIX_RCA926I | AT91C_MATRIX_RCA926D));
}
//------------------------------------------------------------------------------
/// Initialize and configure the external SDRAM.
//------------------------------------------------------------------------------
void BOARD_ConfigureSdram(void)
{
volatile unsigned int i;
static const Pin pinsSdram = PINS_SDRAM;
volatile unsigned int *pSdram = (unsigned int *) AT91C_EBI_SDRAM;
// Enable corresponding PIOs
PIO_Configure(&pinsSdram, 1);
// Enable EBI chip select for the SDRAM
WRITE(AT91C_BASE_MATRIX, MATRIX_EBI, AT91C_MATRIX_CS1A_SDRAMC);
// CFG Control Register
WRITE(AT91C_BASE_SDRAMC, SDRAMC_CR, AT91C_SDRAMC_NC_9
| AT91C_SDRAMC_NR_13
| AT91C_SDRAMC_CAS_2
| AT91C_SDRAMC_NB_4_BANKS
| AT91C_SDRAMC_DBW_32_BITS
| AT91C_SDRAMC_TWR_2
| AT91C_SDRAMC_TRC_7
| AT91C_SDRAMC_TRP_2
| AT91C_SDRAMC_TRCD_2
| AT91C_SDRAMC_TRAS_5
| AT91C_SDRAMC_TXSR_8);
for (i = 0; i < 1000; i++);
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NOP_CMD); // Perform NOP
pSdram[0] = 0x00000000;
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_PRCGALL_CMD); // Set PRCHG AL
pSdram[0] = 0x00000000; // Perform PRCHG
for (i = 0; i < 10000; i++);
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 1st CBR
pSdram[1] = 0x00000001; // Perform CBR
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 2 CBR
pSdram[2] = 0x00000002; // Perform CBR
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 3 CBR
pSdram[3] = 0x00000003; // Perform CBR
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 4 CBR
pSdram[4] = 0x00000004; // Perform CBR
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 5 CBR
pSdram[5] = 0x00000005; // Perform CBR
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 6 CBR
pSdram[6] = 0x00000006; // Perform CBR
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 7 CBR
pSdram[7] = 0x00000007; // Perform CBR
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 8 CBR
pSdram[8] = 0x00000008; // Perform CBR
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_LMR_CMD); // Set LMR operation
pSdram[9] = 0xcafedede; // Perform LMR burst=1, lat=2
WRITE(AT91C_BASE_SDRAMC, SDRAMC_TR, (BOARD_MCK * 7) / 1000000); // Set Refresh Timer
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NORMAL_CMD); // Set Normal mode
pSdram[0] = 0x00000000; // Perform Normal mode
}
//------------------------------------------------------------------------------
/// Initialize and configure the SDRAM for a 48 MHz MCK (ROM code clock settings).
//------------------------------------------------------------------------------
void BOARD_ConfigureSdram48MHz(void)
{
volatile unsigned int i;
static const Pin pinsSdram = PINS_SDRAM;
volatile unsigned int *pSdram = (unsigned int *) AT91C_EBI_SDRAM;
// Enable corresponding PIOs
PIO_Configure(&pinsSdram, 1);
// Enable EBI chip select for the SDRAM
WRITE(AT91C_BASE_MATRIX, MATRIX_EBI, AT91C_MATRIX_CS1A_SDRAMC);
// CFG Control Register
WRITE(AT91C_BASE_SDRAMC, SDRAMC_CR, AT91C_SDRAMC_NC_9
| AT91C_SDRAMC_NR_13
| AT91C_SDRAMC_CAS_2
| AT91C_SDRAMC_NB_4_BANKS
| AT91C_SDRAMC_DBW_32_BITS
| AT91C_SDRAMC_TWR_1
| AT91C_SDRAMC_TRC_4
| AT91C_SDRAMC_TRP_1
| AT91C_SDRAMC_TRCD_1
| AT91C_SDRAMC_TRAS_2
| AT91C_SDRAMC_TXSR_3);
for (i = 0; i < 1000; i++);
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NOP_CMD); // Perform NOP
pSdram[0] = 0x00000000;
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_PRCGALL_CMD); // Set PRCHG AL
pSdram[0] = 0x00000000; // Perform PRCHG
for (i = 0; i < 10000; i++);
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 1st CBR
pSdram[1] = 0x00000001; // Perform CBR
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 2 CBR
pSdram[2] = 0x00000002; // Perform CBR
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 3 CBR
pSdram[3] = 0x00000003; // Perform CBR
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 4 CBR
pSdram[4] = 0x00000004; // Perform CBR
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 5 CBR
pSdram[5] = 0x00000005; // Perform CBR
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 6 CBR
pSdram[6] = 0x00000006; // Perform CBR
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 7 CBR
pSdram[7] = 0x00000007; // Perform CBR
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 8 CBR
pSdram[8] = 0x00000008; // Perform CBR
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_LMR_CMD); // Set LMR operation
pSdram[9] = 0xcafedede; // Perform LMR burst=1, lat=2
WRITE(AT91C_BASE_SDRAMC, SDRAMC_TR, (48000000 * 7) / 1000000); // Set Refresh Timer
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NORMAL_CMD); // Set Normal mode
pSdram[0] = 0x00000000; // Perform Normal mode
}
//------------------------------------------------------------------------------
/// Configures the EBI for NandFlash access. Pins must be configured after or
/// before calling this function.
//------------------------------------------------------------------------------
void BOARD_ConfigureNandFlash(unsigned char busWidth)
{
// Configure EBI
AT91C_BASE_MATRIX->MATRIX_EBI |= AT91C_MATRIX_CS3A_SM;
// Configure SMC
AT91C_BASE_SMC->SMC_SETUP3 = 0x00000000;
AT91C_BASE_SMC->SMC_PULSE3 = 0x00030003;
AT91C_BASE_SMC->SMC_CYCLE3 = 0x00050005;
AT91C_BASE_SMC->SMC_CTRL3 = 0x00002003;
if (busWidth == 8) {
AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_EIGTH_BITS;
}
else if (busWidth == 16) {
AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS;
}
}
//------------------------------------------------------------------------------
/// Configures the EBI for NandFlash access at 48MHz. Pins must be configured
/// after or before calling this function.
//------------------------------------------------------------------------------
void BOARD_ConfigureNandFlash48MHz(unsigned char busWidth)
{
// Configure EBI
AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_CS3A_SM;
// Configure SMC
AT91C_BASE_SMC->SMC_SETUP3 = 0x00010001;
AT91C_BASE_SMC->SMC_PULSE3 = 0x04030302;
AT91C_BASE_SMC->SMC_CYCLE3 = 0x00070004;
AT91C_BASE_SMC->SMC_CTRL3 = (AT91C_SMC_READMODE
| AT91C_SMC_WRITEMODE
| AT91C_SMC_NWAITM_NWAIT_DISABLE
| ((0x1 << 16) & AT91C_SMC_TDF));
if (busWidth == 8) {
AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_EIGTH_BITS;
}
else if (busWidth == 16) {
AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS;
}
}
//------------------------------------------------------------------------------
/// Configures the EBI for NorFlash access at 48MHz.
/// \Param busWidth Bus width
//------------------------------------------------------------------------------
void BOARD_ConfigureNorFlash48MHz(unsigned char busWidth)
{
// Configure SMC
AT91C_BASE_SMC->SMC_SETUP0 = 0x00000001;
AT91C_BASE_SMC->SMC_PULSE0 = 0x07070703;
AT91C_BASE_SMC->SMC_CYCLE0 = 0x00070007;
AT91C_BASE_SMC->SMC_CTRL0 = (AT91C_SMC_READMODE
| AT91C_SMC_WRITEMODE
| AT91C_SMC_NWAITM_NWAIT_DISABLE
| ((0x1 << 16) & AT91C_SMC_TDF));
if (busWidth == 8) {
AT91C_BASE_SMC->SMC_CTRL0 |= AT91C_SMC_DBW_WIDTH_EIGTH_BITS;
}
else if (busWidth == 16) {
AT91C_BASE_SMC->SMC_CTRL0 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS;
}
else if (busWidth == 32) {
AT91C_BASE_SMC->SMC_CTRL0 |= AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS;
}
}
//------------------------------------------------------------------------------
/// Set flash wait states in the EFC for 48MHz
//------------------------------------------------------------------------------
void BOARD_ConfigureFlash48MHz(void)
{
// Set flash wait states
//----------------------
AT91C_BASE_EFC->EFC_FMR = 6 << 8;
}
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board_memories.c | C | oos | 12,891 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include "board.h"
#include "board_memories.h"
//------------------------------------------------------------------------------
// Local definitions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// \page "SAM9XE - Oscillator & PLL Parameters"
/// This page lists the parameters which are set for the PLL and main
/// oscillator configuration.
///
/// !Parameters
/// - BOARD_OSCOUNT
/// - BOARD_CKGR_PLLA
/// - BOARD_PLLACOUNT
/// - BOARD_MULA
/// - BOARD_DIVA
/// - BOARD_CKGR_PLLB
/// - BOARD_PLLBCOUNT
/// - BOARD_MULB
/// - BOARD_DIVB
/// - BOARD_USBDIV
/// - BOARD_PRESCALER
/// Main oscillator startup time (in number of slow clock ticks).
#define BOARD_OSCOUNT (AT91C_CKGR_OSCOUNT & (64 << 8))
/// PLLA frequency range.
#define BOARD_CKGR_PLLA (AT91C_CKGR_SRCA | AT91C_CKGR_OUTA_2)
/// PLLA startup time (in number of slow clock ticks).
#define BOARD_PLLACOUNT (63 << 8)
/// PLLA MUL value.
#define BOARD_MULA (AT91C_CKGR_MULA & (96 << 16))
/// PLLA DIV value.
#define BOARD_DIVA (AT91C_CKGR_DIVA & 9)
/// PLLB frequency range
#define BOARD_CKGR_PLLB AT91C_CKGR_OUTB_1
/// PLLB startup time (in number of slow clock ticks).
#define BOARD_PLLBCOUNT BOARD_PLLACOUNT
/// PLLB MUL value.
#define BOARD_MULB (124 << 16)
/// PLLB DIV value.
#define BOARD_DIVB 12
/// USB PLL divisor value to obtain a 48MHz clock.
#define BOARD_USBDIV AT91C_CKGR_USBDIV_2
/// Master clock prescaler value.
#define BOARD_PRESCALER AT91C_PMC_MDIV_2
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Local functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// Default spurious interrupt handler
//------------------------------------------------------------------------------
void DefaultSpuriousHandler(void)
{
while (1);
}
//------------------------------------------------------------------------------
/// Default handler for fast interrupt requests.
//------------------------------------------------------------------------------
void DefaultFiqHandler(void)
{
while (1);
}
//------------------------------------------------------------------------------
/// Default handler for standard interrupt requests.
//------------------------------------------------------------------------------
void DefaultIrqHandler(void)
{
while (1);
}
//------------------------------------------------------------------------------
// Global functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// Performs the low-level initialization of the chip.
//------------------------------------------------------------------------------
void LowLevelInit(void)
{
unsigned char i;
// Set flash wait states
//----------------------
AT91C_BASE_EFC->EFC_FMR = 6 << 8;
//#if !defined(sdram)
// Initialize main oscillator
//---------------------------
AT91C_BASE_PMC->PMC_MOR = BOARD_OSCOUNT | AT91C_CKGR_MOSCEN;
while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS));
// Initialize PLLA at 200MHz (198.656)
AT91C_BASE_PMC->PMC_PLLAR = BOARD_CKGR_PLLA
| BOARD_PLLACOUNT
| BOARD_MULA
| BOARD_DIVA;
while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA));
// Initialize PLLB for USB usage
AT91C_BASE_PMC->PMC_PLLBR = BOARD_USBDIV
| BOARD_CKGR_PLLB
| BOARD_PLLBCOUNT
| BOARD_MULB
| BOARD_DIVB;
while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKB));
// Wait for the master clock if it was already initialized
while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
// Switch to fast clock
//---------------------
// Switch to main oscillator + prescaler
AT91C_BASE_PMC->PMC_MCKR = BOARD_PRESCALER;
while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
// Switch to PLL + prescaler
AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLLA_CLK;
while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
//#endif //#if !defined(sdram)
// Initialize AIC
//---------------
AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF;
AT91C_BASE_AIC->AIC_SVR[0] = (unsigned int) DefaultFiqHandler;
for (i = 1; i < 31; i++) {
AT91C_BASE_AIC->AIC_SVR[i] = (unsigned int) DefaultIrqHandler;
}
AT91C_BASE_AIC->AIC_SPU = (unsigned int) DefaultSpuriousHandler;
// Unstack nested interrupts
for (i = 0; i < 8 ; i++) {
AT91C_BASE_AIC->AIC_EOICR = 0;
}
// Watchdog initialization
//------------------------
AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
// Remap
//------
BOARD_RemapRam();
// Disable RTT and PIT interrupts (potential problem when program A
// configures RTT, then program B wants to use PIT only, interrupts
// from the RTT will still occur since they both use AT91C_ID_SYS)
AT91C_BASE_RTTC->RTTC_RTMR &= ~(AT91C_RTTC_ALMIEN | AT91C_RTTC_RTTINCIEN);
AT91C_BASE_PITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;
}
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board_lowlevel.c | C | oos | 7,499 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef SUPC_H
#define SUPC_H
//------------------------------------------------------------------------------
// Global functions
//------------------------------------------------------------------------------
extern void SUPC_EnableSlcd(unsigned char internal);
extern void SUPC_DisableSlcd(void);
extern void SUPC_SetSlcdVoltage(unsigned int voltage);
extern
#ifdef __ICCARM__
__ramfunc // IAR
#endif
void SUPC_EnableFlash(unsigned int time);
extern
#ifdef __ICCARM__
__ramfunc // IAR
#endif
void SUPC_DisableFlash(void);
extern void SUPC_SetVoltageOutput(unsigned int voltage);
extern void SUPC_EnableDeepMode(void);
extern void SUPC_EnableSram(void);
extern void SUPC_DisableSram(void);
extern void SUPC_EnableRtc(void);
extern void SUPC_DisableRtc(void);
extern void SUPC_SetBodSampling(unsigned int mode);
extern void SUPC_DisableDeepMode(void);
extern void SUPC_DisableVoltageRegulator(void);
extern void SUPC_Shutdown(void);
extern void SUPC_SetWakeUpSources(unsigned int sources);
extern void SUPC_SetWakeUpInputs(unsigned int inputs);
#endif //#ifndef SUPC_H
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/supc/supc.h | C | oos | 2,721 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include "supc.h"
#include <board.h>
#include <utility/assert.h>
//------------------------------------------------------------------------------
// Local definitions
//------------------------------------------------------------------------------
/// Key value for the SUPC_MR register.
#define SUPC_KEY ((unsigned int) (0xA5 << 24))
//------------------------------------------------------------------------------
// Global functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// Enables the SLCD power supply.
/// \param internal If 1, the power supply is configured as internal; otherwise
/// it is set at external.
//------------------------------------------------------------------------------
void SUPC_EnableSlcd(unsigned char internal)
{
if (internal) {
AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_LCDMODE) | AT91C_SUPC_LCDMODE_INTERNAL;
}
else {
AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_LCDMODE) | AT91C_SUPC_LCDMODE_EXTERNAL;
}
while ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_LCDS) != AT91C_SUPC_LCDS);
}
//------------------------------------------------------------------------------
/// Disables the SLCD power supply.
//------------------------------------------------------------------------------
void SUPC_DisableSlcd(void)
{
AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_LCDMODE);
while ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_LCDS) == AT91C_SUPC_LCDS);
}
//------------------------------------------------------------------------------
/// Sets the output voltage of the SLCD charge pump.
/// \param voltage Output voltage.
//------------------------------------------------------------------------------
void SUPC_SetSlcdVoltage(unsigned int voltage)
{
SANITY_CHECK((voltage & ~AT91C_SUPC_LCDOUT) == 0);
AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_LCDOUT) | voltage;
}
#if !defined(__ICCARM__)
__attribute__ ((section (".ramfunc"))) // GCC
#endif
//------------------------------------------------------------------------------
/// Enables the flash power supply with the given wake-up setting.
/// \param time Wake-up time.
//------------------------------------------------------------------------------
void SUPC_EnableFlash(unsigned int time)
{
AT91C_BASE_SUPC->SUPC_FWUTR = time;
AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | AT91C_BASE_SUPC->SUPC_MR | AT91C_SUPC_FLASHON;
while ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_FLASHS) != AT91C_SUPC_FLASHS);
}
#if !defined(__ICCARM__)
__attribute__ ((section (".ramfunc"))) // GCC
#endif
//------------------------------------------------------------------------------
/// Disables the flash power supply.
//------------------------------------------------------------------------------
void SUPC_DisableFlash(void)
{
AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_FLASHON);
while ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_FLASHS) == AT91C_SUPC_FLASHS);
}
//------------------------------------------------------------------------------
/// Sets the voltage regulator output voltage.
/// \param voltage Voltage to set.
//------------------------------------------------------------------------------
void SUPC_SetVoltageOutput(unsigned int voltage)
{
SANITY_CHECK((voltage & ~AT91C_SUPC_VRVDD) == 0);
AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_VRVDD) | voltage;
}
//------------------------------------------------------------------------------
/// Puts the voltage regulator in deep mode.
//------------------------------------------------------------------------------
void SUPC_EnableDeepMode(void)
{
AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | AT91C_BASE_SUPC->SUPC_MR | AT91C_SUPC_VRDEEP;
}
//------------------------------------------------------------------------------
/// Puts the voltage regulator in normal mode.
//------------------------------------------------------------------------------
void SUPC_DisableDeepMode(void)
{
AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_VRDEEP);
}
//-----------------------------------------------------------------------------
/// Enables the backup SRAM power supply, so its data is saved while the device
/// is in backup mode.
//-----------------------------------------------------------------------------
void SUPC_EnableSram(void)
{
AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | AT91C_BASE_SUPC->SUPC_MR | AT91C_SUPC_SRAMON;
}
//-----------------------------------------------------------------------------
/// Disables the backup SRAM power supply.
//-----------------------------------------------------------------------------
void SUPC_DisableSram(void)
{
AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_SRAMON);
}
//-----------------------------------------------------------------------------
/// Enables the RTC power supply.
//-----------------------------------------------------------------------------
void SUPC_EnableRtc(void)
{
AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | AT91C_BASE_SUPC->SUPC_MR | AT91C_SUPC_RTCON;
while ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_RTS) != AT91C_SUPC_RTS);
}
//-----------------------------------------------------------------------------
/// Disables the RTC power supply.
//-----------------------------------------------------------------------------
void SUPC_DisableRtc(void)
{
AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_RTCON);
while ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_RTS) == AT91C_SUPC_RTS);
}
//-----------------------------------------------------------------------------
/// Sets the BOD sampling mode (or disables it).
/// \param mode BOD sampling mode.
//-----------------------------------------------------------------------------
void SUPC_SetBodSampling(unsigned int mode)
{
SANITY_CHECK((mode & ~AT91C_SUPC_BODSMPL) == 0);
AT91C_BASE_SUPC->SUPC_BOMR &= ~AT91C_SUPC_BODSMPL;
AT91C_BASE_SUPC->SUPC_BOMR |= mode;
}
//------------------------------------------------------------------------------
/// Disables the voltage regulator, which makes the device enter backup mode.
//------------------------------------------------------------------------------
void SUPC_DisableVoltageRegulator(void)
{
AT91C_BASE_SUPC->SUPC_CR = SUPC_KEY | AT91C_SUPC_VROFF;
while (1);
}
//------------------------------------------------------------------------------
/// Shuts the device down so it enters Off mode.
//------------------------------------------------------------------------------
void SUPC_Shutdown(void)
{
AT91C_BASE_SUPC->SUPC_CR = SUPC_KEY | AT91C_SUPC_SHDW;
while (1);
}
//------------------------------------------------------------------------------
/// Sets the wake-up sources when in backup mode.
/// \param sources Wake-up sources to enable.
//------------------------------------------------------------------------------
void SUPC_SetWakeUpSources(unsigned int sources)
{
SANITY_CHECK((sources & ~0x0000000B) == 0);
AT91C_BASE_SUPC->SUPC_WUMR &= ~0x0000000B;
AT91C_BASE_SUPC->SUPC_WUMR |= sources;
}
//------------------------------------------------------------------------------
/// Sets the wake-up inputs when in backup mode.
/// \param inputs Wake up inputs to enable.
//------------------------------------------------------------------------------
void SUPC_SetWakeUpInputs(unsigned int inputs)
{
SANITY_CHECK((inputs & ~0xFFFF) == 0);
AT91C_BASE_SUPC->SUPC_WUIR &= ~0xFFFF;
AT91C_BASE_SUPC->SUPC_WUIR |= inputs;
}
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/supc/supc.c | C | oos | 9,793 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include "slcdc.h"
#include <board.h>
#include <utility/assert.h>
#include <string.h>
//------------------------------------------------------------------------------
// Local definitions
//------------------------------------------------------------------------------
/// Size of SLCDC buffer in bytes.
#define BUFFER_SIZE 320
//------------------------------------------------------------------------------
// Global functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// Initializes the Segment LCD controller.
/// \param commons Number of commons used by the display.
/// \param segments Number of segments used by the display.
/// \param bias Bias value.
/// \param timeSetting Buffer timing value.
//------------------------------------------------------------------------------
void SLCDC_Configure(
unsigned int commons,
unsigned int segments,
unsigned int bias,
unsigned int timeSetting)
{
SANITY_CHECK((commons > 0) && (commons <= 10));
SANITY_CHECK((segments > 0) && (segments <= 40));
SANITY_CHECK((bias & ~AT91C_SLCDC_BIAS) == 0);
SANITY_CHECK((timeSetting & ~(0xF << 16)) == 0);
SANITY_CHECK((timeSetting >> 16) < 0x0A);
// Enable peripheral clock
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SLCD;
AT91C_BASE_SLCDC->SLCDC_MR = (commons - 1) | ((segments - 1) << 8) | bias | timeSetting;
}
//------------------------------------------------------------------------------
/// Clears the SLCD display buffer.
//------------------------------------------------------------------------------
void SLCDC_Clear(void)
{
memset((void *) AT91C_BASE_SLCDC->SLCDC_MEM, 0, BUFFER_SIZE);
}
//------------------------------------------------------------------------------
/// Enables the SLCD controller.
//------------------------------------------------------------------------------
void SLCDC_Enable(void)
{
AT91C_BASE_SLCDC->SLCDC_CR = AT91C_SLCDC_LCDEN;
while (AT91C_BASE_SLCDC -> SLCDC_SR != AT91C_SLCDC_ENA);
}
//------------------------------------------------------------------------------
/// Disables the SLCD controller.
//------------------------------------------------------------------------------
void SLCDC_Disable(void)
{
AT91C_BASE_SLCDC->SLCDC_CR = AT91C_SLCDC_LCDDIS;
}
//------------------------------------------------------------------------------
/// Enables the SLCD low power mode.
//------------------------------------------------------------------------------
void SLCDC_EnableLowPowerMode(void)
{
unsigned int value;
value = AT91C_BASE_SLCDC->SLCDC_MR;
value &= ~AT91C_SLCDC_LPMODE;
value |=AT91C_SLCDC_LPMODE;
AT91C_BASE_SLCDC->SLCDC_MR = value;
}
//------------------------------------------------------------------------------
/// Disables the SLCD low power mode
//------------------------------------------------------------------------------
void SLCDC_DisableLowPowerMode(void)
{
unsigned int value;
value = AT91C_BASE_SLCDC->SLCDC_MR;
value &= ~AT91C_SLCDC_LPMODE;
AT91C_BASE_SLCDC->SLCDC_MR = value;
}
//------------------------------------------------------------------------------
/// Adjusts the frame frequency. Frequency = FsCLK / (prescaler * divider . NCOM)
/// \param prescalerValue Prescaler value
/// \param dividerValue Divider value
//------------------------------------------------------------------------------
void SLCDC_SetFrameFreq(unsigned int prescalerValue, unsigned int dividerValue)
{
SANITY_CHECK((prescalerValue & ~AT91C_SLCDC_PRESC) == 0);
SANITY_CHECK((dividerValue & (~(0x07 << 8))) == 0);
AT91C_BASE_SLCDC->SLCDC_FRR = prescalerValue | dividerValue;
}
//------------------------------------------------------------------------------
/// Sets the display mode (normal/force off/force on/blinking).
/// \param mode Display mode to be set
//------------------------------------------------------------------------------
void SLCDC_SetDisplayMode(unsigned int mode)
{
unsigned int value;
SANITY_CHECK(mode < 8);
value = AT91C_BASE_SLCDC->SLCDC_DR;
value &= ~AT91C_SLCDC_DISPMODE;
value |= mode;
AT91C_BASE_SLCDC->SLCDC_DR = value;
}
//------------------------------------------------------------------------------
/// Adjusts the display blinking frequency.
/// Blinking frequency = Frame Frequency / LCDBLKFREQ.
/// \param frequency Frequency value.
//------------------------------------------------------------------------------
void SLCDC_SetBlinkFreq(unsigned int frequency)
{
unsigned int value;
SANITY_CHECK((frequency & ~(0xFF << 8)) == 0);
value = AT91C_BASE_SLCDC->SLCDC_DR;
value &= ~AT91C_SLCDC_BLKFREQ;
value |= frequency;
AT91C_BASE_SLCDC->SLCDC_DR = frequency;
}
//------------------------------------------------------------------------------
/// Enables the selected SLCDC interrupt sources.
/// \param sources Interrupt sources to enable.
//------------------------------------------------------------------------------
void SLCDC_EnableInterrupts(unsigned int sources)
{
SANITY_CHECK((sources & 0xFFFFFFFA) == 0);
AT91C_BASE_SLCDC->SLCDC_IER = sources;
}
//------------------------------------------------------------------------------
/// Disables the selected SLCDC interrupt sources.
/// \param sources Interrupt sources to disable.
//------------------------------------------------------------------------------
void SLCDC_DisableInterrupts(unsigned int sources)
{
SANITY_CHECK((sources & 0xFFFFFFFA) == 0);
AT91C_BASE_SLCDC->SLCDC_IDR = sources;
}
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/slcdc/slcdc.c | C | oos | 7,627 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef SLCDC_H
#define SLCDC_H
//------------------------------------------------------------------------------
// Global definitions
//------------------------------------------------------------------------------
/// Number of segments in SLCD.
#define S7LEKLCD_NUM_SEGMENTS 40
/// Number of commons in SLCD.
#define S7LEKLCD_NUM_COMMONS 10
//------------------------------------------------------------------------------
// Global functions
//------------------------------------------------------------------------------
extern void SLCDC_Configure(
unsigned int commons,
unsigned int segments,
unsigned int bias,
unsigned int timeSetting);
extern void SLCDC_Clear(void);
extern void SLCDC_Enable(void);
extern void SLCDC_Disable(void);
extern void SLCDC_SetFrameFreq(
unsigned int prescalerValue,
unsigned int dividerValue);
extern void SLCDC_SetDisplayMode(unsigned int mode);
extern void SLCDC_SetBlinkFreq(unsigned int frequency);
extern void SLCDC_EnableInterrupts(unsigned int sources);
extern void SLCDC_DisableInterrupts(unsigned int sources);
#endif //#ifndef SLCDC_H
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/slcdc/slcdc.h | C | oos | 2,762 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include "ssc.h"
#include <utility/trace.h>
//------------------------------------------------------------------------------
// Exported functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// Configures a SSC peripheral. If the divided clock is not used, the master
/// clock frequency can be set to 0.
/// \note The emitter and transmitter are disabled by this function.
/// \param ssc Pointer to an AT91S_SSC instance.
/// \param id Peripheral ID of the SSC.
//------------------------------------------------------------------------------
void SSC_Configure(AT91S_SSC *ssc,
unsigned int id,
unsigned int bitRate,
unsigned int masterClock)
{
// Enable SSC peripheral clock
AT91C_BASE_PMC->PMC_PCER = 1 << id;
// Reset, disable receiver & transmitter
ssc->SSC_CR = AT91C_SSC_RXDIS | AT91C_SSC_TXDIS | AT91C_SSC_SWRST;
ssc->SSC_PTCR = AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS;
// Configure clock frequency
if (bitRate != 0) {
ssc->SSC_CMR = masterClock / (2 * bitRate);
}
else {
ssc->SSC_CMR = 0;
}
}
//------------------------------------------------------------------------------
/// Configures the transmitter of a SSC peripheral. Several macros can be used
/// to compute the values of the Transmit Clock Mode Register (TCMR) and the
/// Transmit Frame Mode Register (TFMR) (see "SSC configuration macros").
/// \param ssc Pointer to a AT91S_SSC instance.
/// \param tcmr Transmit Clock Mode Register value.
/// \param tfmr Transmit Frame Mode Register value.
//------------------------------------------------------------------------------
void SSC_ConfigureTransmitter(AT91S_SSC *ssc,
unsigned int tcmr,
unsigned int tfmr)
{
ssc->SSC_TCMR = tcmr;
ssc->SSC_TFMR = tfmr;
}
//------------------------------------------------------------------------------
/// Configures the receiver of a SSC peripheral. Several macros can be used
/// to compute the values of the Receive Clock Mode Register (TCMR) and the
/// Receive Frame Mode Register (TFMR) (see "SSC configuration macros").
/// \param ssc Pointer to a AT91S_SSC instance.
/// \param rcmr Receive Clock Mode Register value.
/// \param rfmr Receive Frame Mode Register value.
//------------------------------------------------------------------------------
void SSC_ConfigureReceiver(AT91S_SSC *ssc,
unsigned int rcmr,
unsigned int rfmr)
{
ssc->SSC_RCMR = rcmr;
ssc->SSC_RFMR = rfmr;
}
//------------------------------------------------------------------------------
/// Enables the transmitter of a SSC peripheral.
/// \param ssc Pointer to an AT91S_SSC instance.
//------------------------------------------------------------------------------
void SSC_EnableTransmitter(AT91S_SSC *ssc)
{
ssc->SSC_CR = AT91C_SSC_TXEN;
}
//------------------------------------------------------------------------------
/// Disables the transmitter of a SSC peripheral.
/// \param ssc Pointer to an AT91S_SSC instance.
//------------------------------------------------------------------------------
void SSC_DisableTransmitter(AT91S_SSC *ssc)
{
ssc->SSC_CR = AT91C_SSC_TXDIS;
}
//------------------------------------------------------------------------------
/// Enables the receiver of a SSC peripheral.
/// \param ssc Pointer to an AT91S_SSC instance.
//------------------------------------------------------------------------------
void SSC_EnableReceiver(AT91S_SSC *ssc)
{
ssc->SSC_CR = AT91C_SSC_RXEN;
}
//------------------------------------------------------------------------------
/// Disables the receiver of a SSC peripheral.
/// \param ssc Pointer to an AT91S_SSC instance.
//------------------------------------------------------------------------------
void SSC_DisableReceiver(AT91S_SSC *ssc)
{
ssc->SSC_CR = AT91C_SSC_RXDIS;
}
//------------------------------------------------------------------------------
/// Enables one or more interrupt sources of a SSC peripheral.
/// \param ssc Pointer to an AT91S_SSC instance.
/// \param sources Interrupt sources to enable.
//------------------------------------------------------------------------------
void SSC_EnableInterrupts(AT91S_SSC *ssc, unsigned int sources)
{
ssc->SSC_IER = sources;
}
//------------------------------------------------------------------------------
/// Disables one or more interrupt sources of a SSC peripheral.
/// \param ssc Pointer to an AT91S_SSC instance.
/// \param sources Interrupt source to disable.
//------------------------------------------------------------------------------
void SSC_DisableInterrupts(AT91S_SSC *ssc, unsigned int sources)
{
ssc->SSC_IDR = sources;
}
//------------------------------------------------------------------------------
/// Sends one data frame through a SSC peripheral. If another frame is currently
/// being sent, this function waits for the previous transfer to complete.
/// \param ssc Pointer to an AT91S_SSC instance.
/// \param frame Data frame to send.
//------------------------------------------------------------------------------
void SSC_Write(AT91S_SSC *ssc, unsigned int frame)
{
while ((ssc->SSC_SR & AT91C_SSC_TXRDY) == 0);
ssc->SSC_THR = frame;
}
//------------------------------------------------------------------------------
/// Sends the contents of a data buffer a SSC peripheral, using the PDC. Returns
/// true if the buffer has been queued for transmission; otherwise returns
/// false.
/// \param ssc Pointer to an AT91S_SSC instance.
/// \param buffer Data buffer to send.
/// \param length Size of the data buffer.
//------------------------------------------------------------------------------
unsigned char SSC_WriteBuffer(AT91S_SSC *ssc,
void *buffer,
unsigned int length)
{
// Check if first bank is free
if (ssc->SSC_TCR == 0) {
ssc->SSC_TPR = (unsigned int) buffer;
ssc->SSC_TCR = length;
ssc->SSC_PTCR = AT91C_PDC_TXTEN;
return 1;
}
// Check if second bank is free
else if (ssc->SSC_TNCR == 0) {
ssc->SSC_TNPR = (unsigned int) buffer;
ssc->SSC_TNCR = length;
return 1;
}
// No free banks
return 0;
}
//------------------------------------------------------------------------------
/// Waits until one frame is received on a SSC peripheral, and returns it.
/// \param ssc Pointer to an AT91S_SSC instance.
//------------------------------------------------------------------------------
unsigned int SSC_Read(AT91S_SSC *ssc)
{
while ((ssc->SSC_SR & AT91C_SSC_RXRDY) == 0);
return ssc->SSC_RHR;
}
//------------------------------------------------------------------------------
/// Reads data coming from a SSC peripheral receiver and stores it into the
/// provided buffer. Returns true if the buffer has been queued for reception;
/// otherwise returns false.
/// \param ssc Pointer to an AT91S_SSC instance.
/// \param buffer Data buffer used for reception.
/// \param length Size in bytes of the data buffer.
//------------------------------------------------------------------------------
unsigned char SSC_ReadBuffer(AT91S_SSC *ssc,
void *buffer,
unsigned int length)
{
// Check if the first bank is free
if (ssc->SSC_RCR == 0) {
ssc->SSC_RPR = (unsigned int) buffer;
ssc->SSC_RCR = length;
ssc->SSC_PTCR = AT91C_PDC_RXTEN;
return 1;
}
// Check if second bank is free
else if (ssc->SSC_RNCR == 0) {
ssc->SSC_RNPR = (unsigned int) buffer;
ssc->SSC_RNCR = length;
return 1;
}
// No free bank
return 0;
}
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/ssc/ssc.c | C | oos | 10,024 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
/// \dir
/// !Purpose
///
/// Set of functions and definition for using a SSC
/// peripheral.
///
/// !Usage
///
/// -# Configure the SSC to operate at a specific frequency by calling
/// SSC_Configure(). This function enables the peripheral clock of the SSC,
/// but not its PIOs.
/// -# Configure the transmitter and/or the receiver using the
/// SSC_ConfigureTransmitter() and SSC_ConfigureEmitter() functions.
/// -# Enable the PIOs or the transmitter and/or the received using
/// CHIP_EnableSSCTransmitter() and CHIP_EnableSSCReceiver().
/// -# Enable the transmitter and/or the receiver using SSC_EnableTransmitter()
/// and SSC_EnableReceiver()
/// -# Send data through the transmitter using SSC_Write() and SSC_WriteBuffer()
/// -# Receive data from the receiver using SSC_Read() and SSC_ReadBuffer()
/// -# Disable the transmitter and/or the receiver using SSC_DisableTransmitter()
/// and SSC_DisableReceiver()
//------------------------------------------------------------------------------
#ifndef SSC_H
#define SSC_H
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include <board.h>
//------------------------------------------------------------------------------
// Definitions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// \page "SSC configuration macros"
/// This page lists several macros which are used when configuring a SSC
/// peripheral.
///
/// !Macros
/// - SSC_STTDLY
/// - SSC_PERIOD
/// - SSC_DATLEN
/// - SSC_DATNB
/// - SSC_FSLEN
/// Calculates the value of the STTDLY field given the number of clock cycles
/// before the first bit of a new frame is transmitted.
#define SSC_STTDLY(bits) (bits << 16)
/// Calculates the value of the PERIOD field of the Transmit Clock Mode Register
/// of an SSC interface, given the desired clock divider.
#define SSC_PERIOD(divider) (((divider / 2) - 1) << 24)
/// Calculates the value of the DATLEN field of the Transmit Frame Mode Register
/// of an SSC interface, given the number of bits in one sample.
#define SSC_DATLEN(bits) (bits - 1)
/// Calculates the value of the DATNB field of the Transmit Frame Mode Register
/// of an SSC interface, given the number of samples in one frame.
#define SSC_DATNB(samples) ((samples -1) << 8)
/// Calculates the value of the FSLEN field of the Transmit Frame Mode Register
/// of an SSC interface, given the number of transmit clock periods that the
/// frame sync signal should take.
#define SSC_FSLEN(periods) ((periods - 1) << 16)
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Exported functions
//------------------------------------------------------------------------------
extern void SSC_Configure(AT91S_SSC *ssc,
unsigned int id,
unsigned int bitRate,
unsigned int masterClock);
extern void SSC_ConfigureTransmitter(AT91S_SSC *ssc,
unsigned int tcmr,
unsigned int tfmr);
extern void SSC_ConfigureReceiver(AT91S_SSC *ssc,
unsigned int rcmr,
unsigned int rfmr);
extern void SSC_EnableTransmitter(AT91S_SSC *ssc);
extern void SSC_DisableTransmitter(AT91S_SSC *ssc);
extern void SSC_EnableReceiver(AT91S_SSC *ssc);
extern void SSC_DisableReceiver(AT91S_SSC *ssc);
extern void SSC_EnableInterrupts(AT91S_SSC *ssc, unsigned int sources);
extern void SSC_DisableInterrupts(AT91S_SSC *ssc, unsigned int sources);
extern void SSC_Write(AT91S_SSC *ssc, unsigned int frame);
extern unsigned char SSC_WriteBuffer(AT91S_SSC *ssc,
void *buffer,
unsigned int length);
extern unsigned int SSC_Read(AT91S_SSC *ssc);
extern unsigned char SSC_ReadBuffer(AT91S_SSC *ssc,
void *buffer,
unsigned int length);
#endif //#ifndef SSC_H
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/ssc/ssc.h | C | oos | 6,181 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef RTT_H
#define RTT_H
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include <board.h>
//------------------------------------------------------------------------------
// Definitions
//------------------------------------------------------------------------------
#ifndef AT91C_BASE_RTTC
#define AT91C_BASE_RTTC AT91C_BASE_RTTC0
#endif
//------------------------------------------------------------------------------
// Exported functions
//------------------------------------------------------------------------------
extern void RTT_SetPrescaler(AT91S_RTTC *rtt, unsigned short prescaler);
extern unsigned int RTT_GetTime(AT91S_RTTC *rtt);
extern void RTT_EnableIT(AT91S_RTTC *rtt, unsigned int sources);
extern unsigned int RTT_GetStatus(AT91S_RTTC *rtt);
extern void RTT_SetAlarm(AT91S_RTTC *pRtt, unsigned int time);
#endif //#ifndef RTT_H
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/rtt/rtt.h | C | oos | 2,631 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include "rtt.h"
#include <utility/assert.h>
//------------------------------------------------------------------------------
// Exported functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// Changes the prescaler value of the given RTT and restarts it. This function
/// disables RTT interrupt sources.
/// \param rtt Pointer to a AT91S_RTTC instance.
/// \param prescaler Prescaler value for the RTT.
//------------------------------------------------------------------------------
void RTT_SetPrescaler(AT91S_RTTC *rtt, unsigned short prescaler)
{
rtt->RTTC_RTMR = (prescaler | AT91C_RTTC_RTTRST);
}
//------------------------------------------------------------------------------
/// Returns the current value of the RTT timer value.
/// \param rtt Pointer to a AT91S_RTTC instance.
//------------------------------------------------------------------------------
unsigned int RTT_GetTime(AT91S_RTTC *rtt)
{
return rtt->RTTC_RTVR;
}
//------------------------------------------------------------------------------
/// Enables the specified RTT interrupt sources.
/// \param rtt Pointer to a AT91S_RTTC instance.
/// \param sources Bitmask of interrupts to enable.
//------------------------------------------------------------------------------
void RTT_EnableIT(AT91S_RTTC *rtt, unsigned int sources)
{
ASSERT((sources & 0x0004FFFF) == 0,
"RTT_EnableIT: Wrong sources value.\n\r");
rtt->RTTC_RTMR |= sources;
}
//------------------------------------------------------------------------------
/// Returns the status register value of the given RTT.
/// \param rtt Pointer to an AT91S_RTTC instance.
//------------------------------------------------------------------------------
unsigned int RTT_GetStatus(AT91S_RTTC *rtt)
{
return rtt->RTTC_RTSR;
}
//------------------------------------------------------------------------------
/// Configures the RTT to generate an alarm at the given time.
/// \param pRtt Pointer to an AT91S_RTTC instance.
/// \param time Alarm time.
//------------------------------------------------------------------------------
void RTT_SetAlarm(AT91S_RTTC *pRtt, unsigned int time)
{
SANITY_CHECK(time > 0);
pRtt->RTTC_RTAR = time - 1;
}
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/rtt/rtt.c | C | oos | 4,172 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef RTC_H
#define RTC_H
//------------------------------------------------------------------------------
// Exported functions
//------------------------------------------------------------------------------
extern void RTC_SetHourMode(unsigned int mode);
extern void RTC_EnableIt(unsigned int sources);
extern void RTC_DisableIt(unsigned int sources);
extern void RTC_SetTime(
unsigned char hour,
unsigned char minute,
unsigned char second);
extern void RTC_GetTime(
unsigned char *pHour,
unsigned char *pMinute,
unsigned char *pSecond);
extern void RTC_SetTimeAlarm(
unsigned char *pHour,
unsigned char *pMinute,
unsigned char *pSecond);
void RTC_GetDate(
unsigned short *pYear,
unsigned char *pMonth,
unsigned char *pDay,
unsigned char *pWeek);
extern void RTC_SetDate(
unsigned short year,
unsigned char month,
unsigned char day,
unsigned char week);
extern void RTC_SetDateAlarm(unsigned char *pMonth, unsigned char *pDay);
#endif //#ifndef RTC_H
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/rtc/rtc.h | C | oos | 2,632 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef trace_LEVEL
#define trace_LEVEL trace_INFO
#endif
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include "rtc.h"
#include <board.h>
#include <utility/assert.h>
#include <utility/trace.h>
//------------------------------------------------------------------------------
// Exported functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// Sets the RTC in either 12- or 24-hour mode.
/// \param mode Hour mode.
//------------------------------------------------------------------------------
void RTC_SetHourMode(unsigned int mode)
{
SANITY_CHECK((mode & 0xFFFFFFFE) == 0);
trace_LOG(trace_DEBUG, "-D- RTC_SetHourMode()\n\r");
AT91C_BASE_RTC->RTC_MR = mode;
}
//------------------------------------------------------------------------------
/// Enables the selected interrupt sources of the RTC.
/// \param sources Interrupt sources to enable.
//------------------------------------------------------------------------------
void RTC_EnableIt(unsigned int sources)
{
SANITY_CHECK((sources & ~0x1F) == 0);
trace_LOG(trace_DEBUG, "-D- RTC_EnableIt()\n\r");
AT91C_BASE_RTC->RTC_IER = sources;
}
//------------------------------------------------------------------------------
/// Disables the selected interrupt sources of the RTC.
/// \param sources Interrupt sources to disable.
//------------------------------------------------------------------------------
void RTC_DisableIt(unsigned int sources)
{
SANITY_CHECK((sources & ~0x1F) == 0);
trace_LOG(trace_DEBUG, "-D- RTC_DisableIt()\n\r");
AT91C_BASE_RTC->RTC_IDR = sources;
}
//------------------------------------------------------------------------------
/// Sets the current time in the RTC.
/// \param hour Current hour.
/// \param minute Current minute.
/// \param second Current second.
//------------------------------------------------------------------------------
void RTC_SetTime(unsigned char hour, unsigned char minute, unsigned char second)
{
unsigned int time;
SANITY_CHECK(hour < 24);
SANITY_CHECK(minute < 60);
SANITY_CHECK(second < 60);
trace_LOG(trace_DEBUG, "-D- RTC_SetTime(%02d:%02d:%02d)\n\r", hour, minute, second);
time = (second % 10) | ((second / 10) << 4)
| ((minute % 10) << 8) | ((minute / 10) << 12);
// 12-hour mode
if ((AT91C_BASE_RTC->RTC_MR & AT91C_RTC_HRMOD) == AT91C_RTC_HRMOD) {
if (hour > 12) {
hour -= 12;
time |= AT91C_RTC_AMPM;
}
}
time |= ((hour % 10) << 16) | ((hour / 10) << 20);
// Set time
AT91C_BASE_RTC->RTC_CR |= AT91C_RTC_UPDTIM;
while ((AT91C_BASE_RTC->RTC_SR & AT91C_RTC_ACKUPD) != AT91C_RTC_ACKUPD);
AT91C_BASE_RTC->RTC_SCCR = AT91C_RTC_ACKUPD;
AT91C_BASE_RTC->RTC_TIMR = time;
AT91C_BASE_RTC->RTC_CR &= ~AT91C_RTC_UPDTIM;
SANITY_CHECK((AT91C_BASE_RTC->RTC_CR & AT91C_RTC_UPDTIM) != AT91C_RTC_UPDTIM);
}
//------------------------------------------------------------------------------
/// Retrieves the current time as stored in the RTC in several variables.
/// \param pHour If not null, current hour is stored in this variable.
/// \param pMinute If not null, current minute is stored in this variable.
/// \param pSecond If not null, current second is stored in this variable.
//------------------------------------------------------------------------------
void RTC_GetTime(
unsigned char *pHour,
unsigned char *pMinute,
unsigned char *pSecond)
{
unsigned int time;
SANITY_CHECK(pHour || pMinute || pSecond);
trace_LOG(trace_DEBUG, "-D- RTC_GetTime()\n\r");
// Get current RTC time
time = AT91C_BASE_RTC->RTC_TIMR;
while (time != AT91C_BASE_RTC->RTC_TIMR) {
time = AT91C_BASE_RTC->RTC_TIMR;
}
// Hour
if (pHour) {
*pHour = ((time & 0x00300000) >> 20) * 10
+ ((time & 0x000F0000) >> 16);
if ((time & AT91C_RTC_AMPM) == AT91C_RTC_AMPM) {
*pHour += 12;
}
}
// Minute
if (pMinute) {
*pMinute = ((time & 0x00007000) >> 12) * 10
+ ((time & 0x00000F00) >> 8);
}
// Second
if (pSecond) {
*pSecond = ((time & 0x00000070) >> 4) * 10
+ (time & 0x0000000F);
}
}
//------------------------------------------------------------------------------
/// Sets a time alarm on the RTC. The match is performed only on the provided
/// variables; setting all pointers to 0 disables the time alarm.
/// Note: in AM/PM mode, the hour value must have bit #7 set for PM, cleared for
/// AM (as expected in the time registers).
/// \param pHour If not null, the time alarm will hour-match this value.
/// \param pMinute If not null, the time alarm will minute-match this value.
/// \param pSecond If not null, the time alarm will second-match this value.
//------------------------------------------------------------------------------
void RTC_SetTimeAlarm(
unsigned char *pHour,
unsigned char *pMinute,
unsigned char *pSecond)
{
unsigned int alarm = 0;
SANITY_CHECK(!pHour || ((*pHour & 0x80) == 0));
SANITY_CHECK(!pMinute || (*pMinute < 60));
SANITY_CHECK(!pSecond || (*pSecond < 60));
trace_LOG(trace_DEBUG, "-D- RTC_SetTimeAlarm()\n\r");
// Hour
if (pHour) {
alarm |= AT91C_RTC_HOUREN | ((*pHour / 10) << 20) | ((*pHour % 10) << 16);
}
// Minute
if (pMinute) {
alarm |= AT91C_RTC_MINEN | ((*pMinute / 10) << 12) | ((*pMinute % 10) << 8);
}
// Second
if (pSecond) {
alarm |= AT91C_RTC_SECEN | ((*pSecond / 10) << 4) | (*pSecond % 10);
}
AT91C_BASE_RTC->RTC_TIMALR = alarm;
}
//------------------------------------------------------------------------------
/// Retrieves the current year, month and day from the RTC. Month, day and week
/// values are numbered starting at 1.
/// \param pYear Current year (optional).
/// \param pMonth Current month (optional).
/// \param pDay Current day (optional).
/// \param pWeek Current day in current week (optional).
//------------------------------------------------------------------------------
void RTC_GetDate(
unsigned short *pYear,
unsigned char *pMonth,
unsigned char *pDay,
unsigned char *pWeek)
{
unsigned int date;
// Get current date (multiple reads are necessary to insure a stable value)
do {
date = AT91C_BASE_RTC->RTC_CALR;
}
while (date != AT91C_BASE_RTC->RTC_CALR);
// Retrieve year
if (pYear) {
*pYear = (((date >> 4) & 0x7) * 1000)
+ ((date & 0xF) * 100)
+ (((date >> 12) & 0xF) * 10)
+ ((date >> 8) & 0xF);
}
// Retrieve month
if (pMonth) {
*pMonth = (((date >> 20) & 1) * 10) + ((date >> 16) & 0xF);
}
// Retrieve day
if (pDay) {
*pDay = (((date >> 28) & 0x3) * 10) + ((date >> 24) & 0xF);
}
// Retrieve week
if (pWeek) {
*pWeek = ((date >> 21) & 0x7);
}
}
//------------------------------------------------------------------------------
/// Sets the current year, month and day in the RTC. Month, day and week values
/// must be numbered starting from 1.
/// \param year Current year.
/// \param month Current month.
/// \param day Current day.
/// \param week Day number in current week.
//------------------------------------------------------------------------------
void RTC_SetDate(
unsigned short year,
unsigned char month,
unsigned char day,
unsigned char week)
{
unsigned int date;
SANITY_CHECK((year >= 1900) && (year <= 2099));
SANITY_CHECK((month >= 1) && (month <= 12));
SANITY_CHECK((day >= 1) && (day <= 31));
SANITY_CHECK((week >= 1) && (week <= 7));
// Convert values to date register value
date = ((year / 100) % 10)
| ((year / 1000) << 4)
| ((year % 10) << 8)
| (((year / 10) % 10) << 12)
| ((month % 10) << 16)
| ((month / 10) << 20)
| (week << 21)
| ((day % 10) << 24)
| ((day / 10) << 28);
// Update calendar register
AT91C_BASE_RTC->RTC_CR |= AT91C_RTC_UPDCAL;
while ((AT91C_BASE_RTC->RTC_SR & AT91C_RTC_ACKUPD) != AT91C_RTC_ACKUPD);
AT91C_BASE_RTC->RTC_SCCR = AT91C_RTC_ACKUPD;
AT91C_BASE_RTC->RTC_CALR = date;
AT91C_BASE_RTC->RTC_CR &= ~AT91C_RTC_UPDCAL;
}
//------------------------------------------------------------------------------
/// Sets a date alarm in the RTC. The alarm will match only the provided values;
/// passing a null-pointer disables the corresponding field match.
/// \param pMonth If not null, the RTC alarm will month-match this value.
/// \param pDay If not null, the RTC alarm will day-match this value.
//------------------------------------------------------------------------------
void RTC_SetDateAlarm(unsigned char *pMonth, unsigned char *pDay)
{
unsigned int alarm = 0;
SANITY_CHECK(!pMonth || ((*pMonth >= 1) && (*pMonth <= 12)));
SANITY_CHECK(!pDay || ((*pDay >= 1) && (*pDay <= 31)));
trace_LOG(trace_DEBUG, "-D- RTC_SetDateAlarm()\n\r");
// Compute alarm field value
if (pMonth) {
alarm |= AT91C_RTC_MONTHEN | ((*pMonth / 10) << 20) | ((*pMonth % 10) << 16);
}
if (pDay) {
alarm |= AT91C_RTC_DATEEN | ((*pDay / 10) << 28) | ((*pDay % 10) << 24);
}
// Set alarm
AT91C_BASE_RTC->RTC_CALALR = alarm;
}
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/rtc/rtc.c | C | oos | 11,293 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef trace_LEVEL
#define trace_LEVEL 1
#endif
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include "tdes.h"
#include <board.h>
#include <utility/assert.h>
#include <utility/trace.h>
//------------------------------------------------------------------------------
// Global functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// Configures the triple-DES peripheral to cipher/decipher, use single-DES or
/// triple-DES, use two or three keys (when in triple-DES mode), start manually,
/// automatically or via the PDC and use the given operating mode (ECB, CBC,
/// CFB or OFB).
/// \param cipher Encrypts if 1, decrypts if 0.
/// \param tdesmod Single- or triple-DES mode.
/// \param keymod Use two or three keys (must be 0 in single-DES mode).
/// \param smod Start mode.
/// \param opmod Encryption/decryption mode.
//------------------------------------------------------------------------------
void TDES_Configure(
unsigned char cipher,
unsigned int tdesmod,
unsigned int keymod,
unsigned int smod,
unsigned int opmod)
{
trace_LOG(trace_DEBUG, "-D- TDES_Configure()\n\r");
SANITY_CHECK((cipher & 0xFFFFFFFE) == 0);
SANITY_CHECK((tdesmod & 0xFFFFFFFD) == 0);
SANITY_CHECK((keymod & 0xFFFFFFEF) == 0);
SANITY_CHECK((smod & 0xFFFFFCFF) == 0);
SANITY_CHECK((opmod & 0xFFFFCFFF) == 0);
// Reset peripheral
AT91C_BASE_TDES->TDES_CR = AT91C_TDES_SWRST;
// Configure mode register
AT91C_BASE_TDES->TDES_MR = cipher | tdesmod | keymod | smod | opmod;
}
//------------------------------------------------------------------------------
/// Starts the encryption or decryption process if the TDES peripheral is
/// configured in manual or PDC mode.
//------------------------------------------------------------------------------
void TDES_Start(void)
{
trace_LOG(trace_DEBUG, "-D- TDES_Start()\n\r");
SANITY_CHECK(((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_SMOD) == AT91C_TDES_SMOD_MANUAL)
|| ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_SMOD) == AT91C_TDES_SMOD_PDC));
// Manual mode
if ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_SMOD) == AT91C_TDES_SMOD_MANUAL) {
AT91C_BASE_TDES->TDES_CR = AT91C_TDES_START;
}
// PDC mode
else {
AT91C_BASE_TDES->TDES_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN;
}
}
//------------------------------------------------------------------------------
/// Returns the current status register value of the TDES peripheral.
//------------------------------------------------------------------------------
unsigned int TDES_GetStatus(void)
{
trace_LOG(trace_DEBUG, "-D- TDES_GetStatus()\n\r");
return AT91C_BASE_TDES->TDES_ISR;
}
//------------------------------------------------------------------------------
/// Sets the 64-bits keys (one, two or three depending on the configuration)
/// that shall be used by the TDES algorithm.
/// \param pKey1 Pointer to key #1.
/// \param pKey2 Pointer to key #2 (shall be 0 in single-DES mode).
/// \param pKey3 Pointer to key #3 (shall be 0 when using two keys).
//------------------------------------------------------------------------------
void TDES_SetKeys(
const unsigned int *pKey1,
const unsigned int *pKey2,
const unsigned int *pKey3)
{
trace_LOG(trace_DEBUG, "-D- TDES_SetKeys()\n\r");
SANITY_CHECK(pKey1);
SANITY_CHECK((pKey2 && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_TDESMOD) == AT91C_TDES_TDESMOD))
|| (!pKey2 && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_TDESMOD) == 0)));
SANITY_CHECK((pKey3
&& ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_TDESMOD) == AT91C_TDES_TDESMOD)
&& ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_KEYMOD) == 0))
||
(!pKey3
&& ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_TDESMOD) == AT91C_TDES_TDESMOD)
&& ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_KEYMOD) == AT91C_TDES_KEYMOD))
||
(!pKey3
&& ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_TDESMOD) == 0)
&& ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_KEYMOD) == 0)));
// Write key #1
if (pKey1) {
AT91C_BASE_TDES->TDES_KEY1WxR[0] = pKey1[0];
AT91C_BASE_TDES->TDES_KEY1WxR[1] = pKey1[1];
}
// Write key #2
if (pKey1) {
AT91C_BASE_TDES->TDES_KEY2WxR[0] = pKey2[0];
AT91C_BASE_TDES->TDES_KEY2WxR[1] = pKey2[1];
}
// Write key #2
if (pKey1) {
AT91C_BASE_TDES->TDES_KEY3WxR[0] = pKey3[0];
AT91C_BASE_TDES->TDES_KEY3WxR[1] = pKey3[1];
}
}
//------------------------------------------------------------------------------
/// Sets the input data to encrypt/decrypt using TDES.
/// \param pInput Pointer to the 64-bits input data.
//------------------------------------------------------------------------------
void TDES_SetInputData(const unsigned int *pInput)
{
trace_LOG(trace_DEBUG, "-D- TDES_SetInputData()\n\r");
SANITY_CHECK(pInput);
AT91C_BASE_TDES->TDES_IDATAxR[0] = pInput[0];
AT91C_BASE_TDES->TDES_IDATAxR[1] = pInput[1];
}
//------------------------------------------------------------------------------
/// Sets the input data buffer to encrypt/decrypt when in PDC mode.
/// \param pInput Pointer to the input data.
/// \param size Size of buffer in bytes.
//------------------------------------------------------------------------------
void TDES_SetInputBuffer(const unsigned int *pInput, unsigned int size)
{
trace_LOG(trace_DEBUG, "-D- TDES_SetInputBuffer()\n\r");
SANITY_CHECK(pInput);
SANITY_CHECK((size > 0) && ((size % 8) == 0));
AT91C_BASE_TDES->TDES_TPR = (unsigned int) pInput;
AT91C_BASE_TDES->TDES_TCR = size / 4;
}
//------------------------------------------------------------------------------
/// Stores the output data from the last TDES operation into the given 64-bits
/// buffers.
/// \param pOutput Pointer to a 64-bits output buffer.
//------------------------------------------------------------------------------
void TDES_GetOutputData(unsigned int *pOutput)
{
trace_LOG(trace_DEBUG, "-D- TDES_GetOutputData()\n\r");
SANITY_CHECK(pOutput);
pOutput[0] = AT91C_BASE_TDES->TDES_ODATAxR[0];
pOutput[1] = AT91C_BASE_TDES->TDES_ODATAxR[1];
}
//------------------------------------------------------------------------------
/// Sets the output buffer which will receive the encrypted/decrypted data when
/// using the PDC.
/// \param pOutput Pointer to the output data.
/// \param size Size of buffer in bytes.
//------------------------------------------------------------------------------
void TDES_SetOutputBuffer(unsigned int *pOutput, unsigned int size)
{
trace_LOG(trace_DEBUG, "-D- TDES_SetOutputBuffer()\n\r");
SANITY_CHECK(pOutput);
SANITY_CHECK((size > 0) && ((size % 8) == 0));
AT91C_BASE_TDES->TDES_RPR = (unsigned int) pOutput;
AT91C_BASE_TDES->TDES_RCR = size / 4;
}
//------------------------------------------------------------------------------
/// Sets the initialization vector to use when the TDES algorithm is configured
/// in a chained block mode (CBC, CFB or OFB).
/// \param pVector Pointer to the 64-bits vector.
//------------------------------------------------------------------------------
void TDES_SetVector(const unsigned int *pVector)
{
trace_LOG(trace_DEBUG, "-D- TDES_SetVector()\n\r");
SANITY_CHECK(pVector);
AT91C_BASE_TDES->TDES_IVxR[0] = pVector[0];
AT91C_BASE_TDES->TDES_IVxR[1] = pVector[1];
}
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/tdes/tdes.c | C | oos | 9,595 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef TDES_H
#define TDES_H
//------------------------------------------------------------------------------
// Global functions
//------------------------------------------------------------------------------
extern void TDES_Configure(
unsigned char cipher,
unsigned int tdesmod,
unsigned int keymod,
unsigned int smod,
unsigned int opmod);
extern void TDES_Start(void);
extern unsigned int TDES_GetStatus(void);
extern void TDES_SetKeys(
const unsigned int *pKey1,
const unsigned int *pKey2,
const unsigned int *pKey3);
extern void TDES_SetInputData(const unsigned int *pInput);
extern void TDES_SetInputBuffer(const unsigned int *pInput, unsigned int size);
extern void TDES_GetOutputData(unsigned int *pOutput);
extern void TDES_SetOutputBuffer(unsigned int *pOutput, unsigned int size);
extern void TDES_SetVector(const unsigned int *pVector);
#endif //#ifndef TDES_H
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/tdes/tdes.h | C | oos | 2,532 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef AES_H
#define AES_H
//------------------------------------------------------------------------------
// Global functions
//------------------------------------------------------------------------------
extern void AES_Configure(
unsigned char cipher,
unsigned int smode,
unsigned int opmode);
extern void AES_SetKey(const unsigned int *pKey);
extern void AES_SetVector(const unsigned int *pVector);
extern void AES_SetInputData(const unsigned int *pData);
extern void AES_GetOutputData(unsigned int *pData);
extern void AES_SetInputBuffer(const unsigned int *pInput);
extern void AES_SetOutputBuffer(unsigned int *pOutput);
extern void AES_Start(void);
extern unsigned int AES_GetStatus(void);
#endif //#ifndef AES_H
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/aes/aes.h | C | oos | 2,358 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef trace_LEVEL
#define trace_LEVEL 1
#endif
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include "aes.h"
#include <board.h>
#include <utility/trace.h>
#include <utility/assert.h>
//------------------------------------------------------------------------------
// Global functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// Configures the AES peripheral to encrypt/decrypt, start mode (manual, auto,
/// PDC) and operating mode (ECB, CBC, OFB, CFB, CTR).
/// \param cipher Indicates if the peripheral should encrypt or decrypt data.
/// \param smode Start mode.
/// \param opmode Operating mode.
//------------------------------------------------------------------------------
void AES_Configure(
unsigned char cipher,
unsigned int smode,
unsigned int opmode)
{
trace_LOG(trace_DEBUG, "-D- AES_Configure()\n\r");
SANITY_CHECK((cipher & 0xFFFFFFFE) == 0);
SANITY_CHECK((smode & 0xFFFFFCFF) == 0);
SANITY_CHECK((opmode & 0xFFFF8FFF) == 0);
// Reset the peripheral first
AT91C_BASE_AES->AES_CR = AT91C_AES_SWRST;
// Configure mode register
AT91C_BASE_AES->AES_MR = cipher | smode | opmode;
}
//------------------------------------------------------------------------------
/// Sets the key used by the AES algorithm to cipher the plain text or
/// decipher the encrypted text.
/// \param pKey Pointer to a 16-bytes cipher key.
//------------------------------------------------------------------------------
void AES_SetKey(const unsigned int *pKey)
{
trace_LOG(trace_DEBUG, "-D- AES_SetKey()\n\r");
SANITY_CHECK(pKey);
AT91C_BASE_AES->AES_KEYWxR[0] = pKey[0];
AT91C_BASE_AES->AES_KEYWxR[1] = pKey[1];
AT91C_BASE_AES->AES_KEYWxR[2] = pKey[2];
AT91C_BASE_AES->AES_KEYWxR[3] = pKey[3];
}
//------------------------------------------------------------------------------
/// Sets the initialization vector that is used to encrypt the plain text or
/// decrypt the cipher text in chained block modes (CBC, CFB, OFB & CTR).
/// \param pVector Pointer to a 16-bytes initialization vector.
//------------------------------------------------------------------------------
void AES_SetVector(const unsigned int *pVector)
{
trace_LOG(trace_DEBUG, "-D- AES_SetVector()\n\r");
SANITY_CHECK(pVector);
AT91C_BASE_AES->AES_IVxR[0] = pVector[0];
AT91C_BASE_AES->AES_IVxR[1] = pVector[1];
AT91C_BASE_AES->AES_IVxR[2] = pVector[2];
AT91C_BASE_AES->AES_IVxR[3] = pVector[3];
}
//------------------------------------------------------------------------------
/// Sets the input data of the AES algorithm (i.e. plain text in cipher mode,
/// ciphered text in decipher mode). If auto mode is active, the encryption is
/// started automatically after writing the last word.
/// \param pData Pointer to the 16-bytes data to cipher/decipher.
//------------------------------------------------------------------------------
void AES_SetInputData(const unsigned int *pData)
{
trace_LOG(trace_DEBUG, "-D- AES_SetInputData()\n\r");
SANITY_CHECK(pData);
AT91C_BASE_AES->AES_IDATAxR[0] = pData[0];
AT91C_BASE_AES->AES_IDATAxR[1] = pData[1];
AT91C_BASE_AES->AES_IDATAxR[2] = pData[2];
AT91C_BASE_AES->AES_IDATAxR[3] = pData[3];
}
//------------------------------------------------------------------------------
/// Stores the result of the last AES operation (encrypt/decrypt) in the
/// provided buffer.
/// \param pData Pointer to a 16-bytes buffer.
//------------------------------------------------------------------------------
void AES_GetOutputData(unsigned int *pData)
{
trace_LOG(trace_DEBUG, "-D- AES_GetOutputData()\n\r");
SANITY_CHECK(pData);
pData[0] = AT91C_BASE_AES->AES_ODATAxR[0];
pData[1] = AT91C_BASE_AES->AES_ODATAxR[1];
pData[2] = AT91C_BASE_AES->AES_ODATAxR[2];
pData[3] = AT91C_BASE_AES->AES_ODATAxR[3];
}
//------------------------------------------------------------------------------
/// Sets the input buffer to use when in PDC mode.
/// \param pInput Pointer to the input buffer.
//------------------------------------------------------------------------------
void AES_SetInputBuffer(const unsigned int *pInput)
{
trace_LOG(trace_DEBUG, "-D- AES_SetInputBuffer()\n\r");
SANITY_CHECK(pInput);
AT91C_BASE_AES->AES_TPR = (unsigned int) pInput;
AT91C_BASE_AES->AES_TCR = 4;
}
//------------------------------------------------------------------------------
/// Sets the output buffer to use when in PDC mode.
/// \param pOutput Pointer to the output buffer.
//------------------------------------------------------------------------------
void AES_SetOutputBuffer(unsigned int *pOutput)
{
trace_LOG(trace_DEBUG, "-D- AES_SetOutputBuffer()\n\r");
SANITY_CHECK(pOutput);
AT91C_BASE_AES->AES_RPR = (unsigned int) pOutput;
AT91C_BASE_AES->AES_RCR = 4;
}
//------------------------------------------------------------------------------
/// Starts the encryption/decryption process when in manual or PDC mode. In
/// manual mode, the key and input data must have been entered using
/// AES_SetKey() and AES_SetInputData(). In PDC mode, the key, input & output
/// buffer must have been set using AES_SetKey(), AES_SetInputBuffer() and
/// AES_SetOutputBuffer().
//------------------------------------------------------------------------------
void AES_Start(void)
{
trace_LOG(trace_DEBUG, "AES_Start()\n\r");
SANITY_CHECK(((AT91C_BASE_AES->AES_MR & AT91C_AES_SMOD) == AT91C_AES_SMOD_MANUAL)
|| ((AT91C_BASE_AES->AES_MR & AT91C_AES_SMOD) == AT91C_AES_SMOD_PDC));
// Manual mode
if ((AT91C_BASE_AES->AES_MR & AT91C_AES_SMOD) == AT91C_AES_SMOD_MANUAL) {
AT91C_BASE_AES->AES_CR = AT91C_AES_START;
}
// PDC
else {
AT91C_BASE_AES->AES_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN;
}
}
//------------------------------------------------------------------------------
/// Returns the current value of the AES interrupt status register.
//------------------------------------------------------------------------------
unsigned int AES_GetStatus(void)
{
trace_LOG(trace_DEBUG, "-D- AES_GetStatus()\n\r");
return AT91C_BASE_AES->AES_ISR;
}
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/aes/aes.c | C | oos | 8,205 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include "pmc.h"
#include <board.h>
#include <utility/assert.h>
#include <utility/trace.h>
//------------------------------------------------------------------------------
// Global functions
//------------------------------------------------------------------------------
#if defined(at91sam7l64) || defined(at91sam7l128)
//------------------------------------------------------------------------------
/// Sets the fast wake-up inputs that can get the device out of Wait mode.
/// \param inputs Fast wake-up inputs to enable.
//------------------------------------------------------------------------------
void PMC_SetFastWakeUpInputs(unsigned int inputs)
{
SANITY_CHECK((inputs & ~0xFF) == 0);
AT91C_BASE_PMC->PMC_FSMR = inputs;
}
#if !defined(__ICCARM__)
__attribute__ ((section (".ramfunc"))) // GCC
#endif
//------------------------------------------------------------------------------
/// Disables the main oscillator, making the device enter Wait mode.
//------------------------------------------------------------------------------
void PMC_DisableMainOscillatorForWaitMode(void)
{
AT91C_BASE_PMC->PMC_MOR = 0x37 << 16;
while ((AT91C_BASE_PMC->PMC_MOR & AT91C_PMC_MAINSELS) != AT91C_PMC_MAINSELS);
}
#endif
#if defined(at91sam7l)
//------------------------------------------------------------------------------
/// Disables the main oscillator when NOT running on it.
//------------------------------------------------------------------------------
void PMC_DisableMainOscillator(void)
{
AT91C_BASE_PMC->PMC_MOR = 0x37 << 16;
while ((AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MAINSELS) == AT91C_PMC_MAINSELS);
}
#endif
//------------------------------------------------------------------------------
/// Disables the processor clock, making the device enter Idle mode.
//------------------------------------------------------------------------------
void PMC_DisableProcessorClock(void)
{
AT91C_BASE_PMC->PMC_SCDR = AT91C_PMC_PCK;
while ((AT91C_BASE_PMC->PMC_SCSR & AT91C_PMC_PCK) != AT91C_PMC_PCK);
}
//------------------------------------------------------------------------------
/// Enables the clock of a peripheral. The peripheral ID (AT91C_ID_xxx) is used
/// to identify which peripheral is targetted.
/// Note that the ID must NOT be shifted (i.e. 1 << AT91C_ID_xxx).
/// \param id Peripheral ID (AT91C_ID_xxx).
//------------------------------------------------------------------------------
void PMC_EnablePeripheral(unsigned int id)
{
SANITY_CHECK(id < 32);
if ((AT91C_BASE_PMC->PMC_PCSR & (1 << id)) == (1 << id)) {
trace_LOG(trace_INFO,
"-I- PMC_EnablePeripheral: clock of peripheral"
" %u is already enabled\n\r",
id);
}
else {
AT91C_BASE_PMC->PMC_PCER = 1 << id;
}
}
//------------------------------------------------------------------------------
/// Disables the clock of a peripheral. The peripheral ID (AT91C_ID_xxx) is used
/// to identify which peripheral is targetted.
/// Note that the ID must NOT be shifted (i.e. 1 << AT91C_ID_xxx).
/// \param id Peripheral ID (AT91C_ID_xxx).
//------------------------------------------------------------------------------
void PMC_DisablePeripheral(unsigned int id)
{
SANITY_CHECK(id < 32);
if ((AT91C_BASE_PMC->PMC_PCSR & (1 << id)) != (1 << id)) {
trace_LOG(trace_INFO,
"-I- PMC_DisablePeripheral: clock of peripheral"
" %u is not enabled\n\r",
id);
}
else {
AT91C_BASE_PMC->PMC_PCDR = 1 << id;
}
}
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/pmc/pmc.c | C | oos | 5,463 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef PMC_H
#define PMC_H
//------------------------------------------------------------------------------
// Global functions
//------------------------------------------------------------------------------
#if defined(at91sam7l64) || defined(at91sam7l128)
extern void PMC_SetFastWakeUpInputs(unsigned int inputs);
extern void PMC_DisableMainOscillator(void);
extern
#ifdef __ICCARM__
__ramfunc
#endif
void PMC_DisableMainOscillatorForWaitMode(void);
#endif
extern void PMC_DisableProcessorClock(void);
extern void PMC_EnablePeripheral(unsigned int id);
extern void PMC_DisablePeripheral(unsigned int id);
#endif //#ifndef PMC_H
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/pmc/pmc.h | C | oos | 2,241 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include "tc.h"
//------------------------------------------------------------------------------
// Global functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// Configures a Timer Counter to operate in the given mode. Timer is stopped
/// after configuration and must be restarted with TC_Start().
/// to obtain the target frequency.
/// \param pTc Pointer to an AT91S_TC instance.
/// \param mode Operating mode.
//------------------------------------------------------------------------------
void TC_Configure(AT91S_TC *pTc, unsigned int mode)
{
// Disable TC clock
pTc->TC_CCR = AT91C_TC_CLKDIS;
// Disable interrupts
pTc->TC_IDR = 0xFFFFFFFF;
// Clear status register
pTc->TC_SR;
// Set mode
pTc->TC_CMR = mode;
}
//------------------------------------------------------------------------------
/// Starts the timer clock.
/// \param pTc Pointer to an AT91S_TC instance.
//------------------------------------------------------------------------------
void TC_Start(AT91S_TC *pTc)
{
pTc->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
}
//------------------------------------------------------------------------------
/// Stops the timer clock.
/// \param pTc Pointer to an AT91S_TC instance.
//------------------------------------------------------------------------------
void TC_Stop(AT91S_TC *pTc)
{
pTc->TC_CCR = AT91C_TC_CLKDIS;
}
//------------------------------------------------------------------------------
/// Finds the best MCK divisor given the timer frequency and MCK. The result
/// is guaranteed to satisfy the following equation:
/// (MCK / (DIV * 65536)) <= freq <= (MCK / DIV)
/// with DIV being the highest possible value.
/// Returns 1 if a divisor could be found; otherwise returns 0.
/// \param freq Desired timer frequency.
/// \param mck Master clock frequency.
/// \param div Divisor value.
/// \param tcclks TCCLKS field value for divisor.
//------------------------------------------------------------------------------
unsigned char TC_FindMckDivisor(
unsigned int freq,
unsigned int mck,
unsigned int *div,
unsigned int *tcclks)
{
const unsigned int divisors[5] = {2, 8, 32, 128,
#if defined(at91sam9260) || defined(at91sam9261) || defined(at91sam9263) \
|| defined(at91sam9xe) || defined(at91sam9rl64) || defined(at91cap9)
BOARD_MCK / 32768};
#else
1024};
#endif
unsigned int index = 0;
// Satisfy lower bound
while (freq < ((mck / divisors[index]) / 65536)) {
index++;
// If no divisor can be found, return 0
if (index == 5) {
return 0;
}
}
// Try to maximise DIV while satisfying upper bound
while (index < 4) {
if (freq > (mck / divisors[index + 1])) {
break;
}
index++;
}
// Store results
if (div) {
*div = divisors[index];
}
if (tcclks) {
*tcclks = index;
}
return 1;
}
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/tc/tc.c | C | oos | 4,959 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef TC_H
#define TC_H
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include <board.h>
#if !defined(AT91C_ID_TC0) && defined(AT91C_ID_TC012)
#define AT91C_ID_TC0 AT91C_ID_TC012
#endif
//------------------------------------------------------------------------------
// Global functions
//------------------------------------------------------------------------------
extern void TC_Configure(AT91S_TC *pTc, unsigned int mode);
extern void TC_Start(AT91S_TC *pTc);
extern void TC_Stop(AT91S_TC *pTc);
extern unsigned char TC_FindMckDivisor(
unsigned int freq,
unsigned int mck,
unsigned int *div,
unsigned int *tcclks);
#endif //#ifndef TC_H
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/tc/tc.h | C | oos | 2,419 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _RSTC_H
#define _RSTC_H
//-----------------------------------------------------------------------------
// Exported functions
//-----------------------------------------------------------------------------
extern void RSTC_ConfigureMode(AT91PS_RSTC rstc, unsigned int rmr);
extern void RSTC_SetUserResetEnable(AT91PS_RSTC rstc, unsigned char enable);
extern void RSTC_SetUserResetInterruptEnable(AT91PS_RSTC rstc,
unsigned char enable);
extern void RSTC_SetExtResetLength(AT91PS_RSTC rstc, unsigned char powl);
extern void RSTC_ProcessorReset(AT91PS_RSTC rstc);
extern void RSTC_PeripheralReset(AT91PS_RSTC rstc);
extern void RSTC_ExtReset(AT91PS_RSTC rstc);
extern unsigned char RSTC_GetNrstLevel(AT91PS_RSTC rstc);
extern unsigned char RSTC_IsUserReseetDetected(AT91PS_RSTC rstc);
extern unsigned char RSTC_IsBusy(AT91PS_RSTC rstc);
#endif // #ifndef _RSTC_H
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/rstc/rstc.h | C | oos | 2,534 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//-----------------------------------------------------------------------------
// Headers
//-----------------------------------------------------------------------------
#include <board.h>
//-----------------------------------------------------------------------------
// Macros
//-----------------------------------------------------------------------------
/// WRITE_RSTC: Write RSTC register
#define WRITE_RSTC(pRstc, regName, value) pRstc->regName = (value)
/// READ_RSTC: Read RSTC registers
#define READ_RSTC(pRstc, regName) (pRstc->regName)
//-----------------------------------------------------------------------------
// Defines
//-----------------------------------------------------------------------------
/// Keywords to write to the reset registers
#define RSTC_KEY_PASSWORD (0xA5UL << 24)
//-----------------------------------------------------------------------------
// Exported functions
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
/// Configure the mode of the RSTC peripheral.
/// The configuration is computed by the lib (AT91C_RSTC_*).
/// \param rstc Pointer to an RSTC peripheral.
/// \param rmr Desired mode configuration.
//-----------------------------------------------------------------------------
void RSTC_ConfigureMode(AT91PS_RSTC rstc, unsigned int rmr)
{
rmr &= ~AT91C_RSTC_KEY;
WRITE_RSTC(rstc, RSTC_RMR, rmr | RSTC_KEY_PASSWORD);
}
//-----------------------------------------------------------------------------
/// Enable/Disable the detection of a low level on the pin NRST as User Reset
/// \param rstc Pointer to an RSTC peripheral.
/// \param enable 1 to enable & 0 to disable.
//-----------------------------------------------------------------------------
void RSTC_SetUserResetEnable(AT91PS_RSTC rstc, unsigned char enable)
{
unsigned int rmr = READ_RSTC(rstc, RSTC_RMR) & (~AT91C_RSTC_KEY);
if (enable) {
rmr |= AT91C_RSTC_URSTEN;
}
else {
rmr &= ~AT91C_RSTC_URSTEN;
}
WRITE_RSTC(rstc, RSTC_RMR, rmr | RSTC_KEY_PASSWORD);
}
//-----------------------------------------------------------------------------
/// Enable/Disable the interrupt of a User Reset (USRTS bit in RSTC_RST).
/// \param rstc Pointer to an RSTC peripheral.
/// \param enable 1 to enable & 0 to disable.
//-----------------------------------------------------------------------------
void RSTC_SetUserResetInterruptEnable(AT91PS_RSTC rstc, unsigned char enable)
{
unsigned int rmr = READ_RSTC(rstc, RSTC_RMR) & (~AT91C_RSTC_KEY);
if (enable) {
rmr |= AT91C_RSTC_URSTIEN;
}
else {
rmr &= ~AT91C_RSTC_URSTIEN;
}
WRITE_RSTC(rstc, RSTC_RMR, rmr | RSTC_KEY_PASSWORD);
}
//-----------------------------------------------------------------------------
/// Setup the external reset length. The length is asserted during a time of
/// pow(2, powl+1) Slow Clock(32KHz). The duration is between 60us and 2s.
/// \param rstc Pointer to an RSTC peripheral.
/// \param powl Power length defined.
//-----------------------------------------------------------------------------
void RSTC_SetExtResetLength(AT91PS_RSTC rstc, unsigned char powl)
{
unsigned int rmr = READ_RSTC(rstc, RSTC_RMR);
rmr &= ~(AT91C_RSTC_KEY | AT91C_RSTC_ERSTL);
rmr |= (powl << 8) & AT91C_RSTC_ERSTL;
WRITE_RSTC(rstc, RSTC_RMR, rmr | RSTC_KEY_PASSWORD);
}
//-----------------------------------------------------------------------------
/// Resets the processor.
/// \param rstc Pointer to an RSTC peripheral.
//-----------------------------------------------------------------------------
void RSTC_ProcessorReset(AT91PS_RSTC rstc)
{
WRITE_RSTC(rstc, RSTC_RCR, AT91C_RSTC_PROCRST | RSTC_KEY_PASSWORD);
}
//-----------------------------------------------------------------------------
/// Resets the peripherals.
/// \param rstc Pointer to an RSTC peripheral.
//-----------------------------------------------------------------------------
void RSTC_PeripheralReset(AT91PS_RSTC rstc)
{
WRITE_RSTC(rstc, RSTC_RCR, AT91C_RSTC_PERRST | RSTC_KEY_PASSWORD);
}
//-----------------------------------------------------------------------------
/// Asserts the NRST pin for external resets.
/// \param rstc Pointer to an RSTC peripheral.
//-----------------------------------------------------------------------------
void RSTC_ExtReset(AT91PS_RSTC rstc)
{
WRITE_RSTC(rstc, RSTC_RCR, AT91C_RSTC_EXTRST | RSTC_KEY_PASSWORD);
}
//-----------------------------------------------------------------------------
/// Return NRST pin level ( 1 or 0 ).
/// \param rstc Pointer to an RSTC peripheral.
//-----------------------------------------------------------------------------
unsigned char RSTC_GetNrstLevel(AT91PS_RSTC rstc)
{
if (READ_RSTC(rstc, RSTC_RSR) & AT91C_RSTC_NRSTL) {
return 1;
}
return 0;
}
//-----------------------------------------------------------------------------
/// Returns 1 if at least one high-to-low transition of NRST (User Reset) has
/// been detected since the last read of RSTC_RSR.
/// \param rstc Pointer to an RSTC peripheral.
//-----------------------------------------------------------------------------
unsigned char RSTC_IsUserReseetDetected(AT91PS_RSTC rstc)
{
if (READ_RSTC(rstc, RSTC_RSR) & AT91C_RSTC_URSTS) {
return 1;
}
return 0;
}
//-----------------------------------------------------------------------------
/// Return 1 if a software reset command is being performed by the reset
/// controller. The reset controller is busy.
/// \param rstc Pointer to an RSTC peripheral.
//-----------------------------------------------------------------------------
unsigned char RSTC_IsBusy(AT91PS_RSTC rstc)
{
if (READ_RSTC(rstc, RSTC_RSR) & AT91C_RSTC_SRCMP) {
return 1;
}
return 0;
}
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/rstc/rstc.c | C | oos | 7,684 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
/// \dir
/// !Purpose
///
/// This module provides several definitions and methods for using an USART
/// peripheral.
///
/// !Usage
/// -# Enable the USART peripheral clock in the PMC.
/// -# Enable the required USART PIOs (see pio.h).
/// -# Configure the UART by calling USART_Configure.
/// -# Enable the transmitter and/or the receiver of the USART using
/// USART_SetTransmitterEnabled and USART_SetReceiverEnabled.
/// -# Send data through the USART using the USART_Write and
/// USART_WriteBuffer methods.
/// -# Receive data from the USART using the USART_Read and
/// USART_ReadBuffer functions; the availability of data can be polled
/// with USART_IsDataAvailable.
/// -# Disable the transmitter and/or the receiver of the USART with
/// USART_SetTransmitterEnabled and USART_SetReceiverEnabled.
//------------------------------------------------------------------------------
#ifndef USART_H
#define USART_H
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include <board.h>
//------------------------------------------------------------------------------
// Definitions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// \page "USART modes"
/// This page lists several common operating modes for an USART peripheral.
///
/// !Modes
/// - USART_MODE_ASYNCHRONOUS
/// Basic asynchronous mode, i.e. 8 bits no parity.
#define USART_MODE_ASYNCHRONOUS (AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE)
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Exported functions
//------------------------------------------------------------------------------
extern void USART_Configure(
AT91S_USART *usart,
unsigned int mode,
unsigned int baudrate,
unsigned int masterClock);
extern void USART_SetTransmitterEnabled(AT91S_USART *usart, unsigned char enabled);
extern void USART_SetReceiverEnabled(AT91S_USART *usart, unsigned char enabled);
extern void USART_Write(
AT91S_USART *usart,
unsigned short data,
volatile unsigned int timeOut);
extern unsigned char USART_WriteBuffer(
AT91S_USART *usart,
void *buffer,
unsigned int size);
extern unsigned short USART_Read(
AT91S_USART *usart,
volatile unsigned int timeOut);
extern unsigned char USART_ReadBuffer(
AT91S_USART *usart,
void *buffer,
unsigned int size);
extern unsigned char USART_IsDataAvailable(AT91S_USART *usart);
#endif //#ifndef USART_H
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/usart/usart.h | C | oos | 4,511 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include "usart.h"
#include <utility/trace.h>
//------------------------------------------------------------------------------
// Exported functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// Configures an USART peripheral with the specified parameters.
/// \param usart Pointer to the USART peripheral to configure.
/// \param mode Desired value for the USART mode register (see the datasheet).
/// \param baudrate Baudrate at which the USART should operate (in Hz).
/// \param masterClock Frequency of the system master clock (in Hz).
//------------------------------------------------------------------------------
void USART_Configure(AT91S_USART *usart,
unsigned int mode,
unsigned int baudrate,
unsigned int masterClock)
{
// Reset and disable receiver & transmitter
usart->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX
| AT91C_US_RXDIS | AT91C_US_TXDIS;
// Configure mode
usart->US_MR = mode;
// Configure baudrate
// Asynchronous, no oversampling
if (((mode & AT91C_US_SYNC) == 0)
&& ((mode & AT91C_US_OVER) == 0)) {
usart->US_BRGR = (masterClock / baudrate) / 16;
}
// TODO other modes
}
//------------------------------------------------------------------------------
/// Enables or disables the transmitter of an USART peripheral.
/// \param usart Pointer to an USART peripheral
/// \param enabled If true, the transmitter is enabled; otherwise it is
/// disabled.
//------------------------------------------------------------------------------
void USART_SetTransmitterEnabled(AT91S_USART *usart,
unsigned char enabled)
{
if (enabled) {
usart->US_CR = AT91C_US_TXEN;
}
else {
usart->US_CR = AT91C_US_TXDIS;
}
}
//------------------------------------------------------------------------------
/// Enables or disables the receiver of an USART peripheral
/// \param usart Pointer to an USART peripheral
/// \param enabled If true, the receiver is enabled; otherwise it is disabled.
//------------------------------------------------------------------------------
void USART_SetReceiverEnabled(AT91S_USART *usart,
unsigned char enabled)
{
if (enabled) {
usart->US_CR = AT91C_US_RXEN;
}
else {
usart->US_CR = AT91C_US_RXDIS;
}
}
//------------------------------------------------------------------------------
/// Sends one packet of data through the specified USART peripheral. This
/// function operates synchronously, so it only returns when the data has been
/// actually sent.
/// \param usart Pointer to an USART peripheral.
/// \param data Data to send including 9nth bit and sync field if necessary (in
/// the same format as the US_THR register in the datasheet).
/// \param timeOut Time out value (0 = no timeout).
//------------------------------------------------------------------------------
void USART_Write(
AT91S_USART *usart,
unsigned short data,
volatile unsigned int timeOut)
{
if (timeOut == 0) {
while ((usart->US_CSR & AT91C_US_TXEMPTY) == 0);
}
else {
while ((usart->US_CSR & AT91C_US_TXEMPTY) == 0) {
if (timeOut == 0) {
trace_LOG(trace_ERROR, "-E- USART_Write: Timed out.\n\r");
return;
}
timeOut--;
}
}
usart->US_THR = data;
}
//------------------------------------------------------------------------------
/// Sends the contents of a data buffer through the specified USART peripheral.
/// This function returns immediately (1 if the buffer has been queued, 0
/// otherwise); poll the ENDTX and TXBUFE bits of the USART status register
/// to check for the transfer completion.
/// \param usart Pointer to an USART peripheral.
/// \param buffer Pointer to the data buffer to send.
/// \param size Size of the data buffer (in bytes).
//------------------------------------------------------------------------------
unsigned char USART_WriteBuffer(
AT91S_USART *usart,
void *buffer,
unsigned int size)
{
// Check if the first PDC bank is free
if ((usart->US_TCR == 0) && (usart->US_TNCR == 0)) {
usart->US_TPR = (unsigned int) buffer;
usart->US_TCR = size;
usart->US_PTCR = AT91C_PDC_TXTEN;
return 1;
}
// Check if the second PDC bank is free
else if (usart->US_TNCR == 0) {
usart->US_TNPR = (unsigned int) buffer;
usart->US_TNCR = size;
return 1;
}
else {
return 0;
}
}
//------------------------------------------------------------------------------
/// Reads and return a packet of data on the specified USART peripheral. This
/// function operates asynchronously, so it waits until some data has been
/// received.
/// \param usart Pointer to an USART peripheral.
/// \param timeOut Time out value (0 -> no timeout).
//------------------------------------------------------------------------------
unsigned short USART_Read(
AT91S_USART *usart,
volatile unsigned int timeOut)
{
if (timeOut == 0) {
while ((usart->US_CSR & AT91C_US_RXRDY) == 0);
}
else {
while ((usart->US_CSR & AT91C_US_RXRDY) == 0) {
if (timeOut == 0) {
trace_LOG(trace_ERROR, "-E- USART_Read: Timed out.\n\r");
return 0;
}
timeOut--;
}
}
return usart->US_RHR;
}
//------------------------------------------------------------------------------
/// Reads data from an USART peripheral, filling the provided buffer until it
/// becomes full. This function returns immediately with 1 if the buffer has
/// been queued for transmission; otherwise 0.
/// \param usart Pointer to an USART peripheral.
/// \param buffer Pointer to the buffer where the received data will be stored.
/// \param size Size of the data buffer (in bytes).
//------------------------------------------------------------------------------
unsigned char USART_ReadBuffer(AT91S_USART *usart,
void *buffer,
unsigned int size)
{
// Check if the first PDC bank is free
if ((usart->US_RCR == 0) && (usart->US_RNCR == 0)) {
usart->US_RPR = (unsigned int) buffer;
usart->US_RCR = size;
usart->US_PTCR = AT91C_PDC_RXTEN;
return 1;
}
// Check if the second PDC bank is free
else if (usart->US_RNCR == 0) {
usart->US_RNPR = (unsigned int) buffer;
usart->US_RNCR = size;
return 1;
}
else {
return 0;
}
}
//------------------------------------------------------------------------------
/// Returns 1 if some data has been received and can be read from an USART;
/// otherwise returns 0.
/// \param usart Pointer to an AT91S_USART instance.
//------------------------------------------------------------------------------
unsigned char USART_IsDataAvailable(AT91S_USART *usart)
{
if ((usart->US_CSR & AT91C_US_RXRDY) != 0) {
return 1;
}
else {
return 0;
}
}
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/usart/usart.c | C | oos | 9,371 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef EFC_H
#define EFC_H
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include <board.h>
#ifdef BOARD_FLASH_EFC
//------------------------------------------------------------------------------
// Constants
//------------------------------------------------------------------------------
/// Number of GPNVMs available on each chip.
#if defined(at91sam7s16) || defined(at91sam7s161) || defined(at91sam7s32) \
|| defined(at91sam7s321) || defined(at91sam7s64) || defined(at91sam7s128) \
|| defined(at91sam7s256) || defined(at91sam7s512)
#define EFC_NUM_GPNVMS 2
#elif defined(at91sam7se32) || defined(at91sam7se256) || defined(at91sam7se512) \
|| defined(at91sam7x128) || defined(at91sam7x256) || defined(at91sam7x512) \
|| defined(at91sam7xc128) || defined(at91sam7xc256) || defined(at91sam7xc512) \
#define EFC_NUM_GPNVMS 3
#elif defined(at91sam7a3)
#define EFC_NUM_GPNVMS 0
#endif
// Missing FRDY bit for SAM7A3
#if defined(at91sam7a3)
#define AT91C_MC_FRDY (AT91C_MC_EOP | AT91C_MC_EOL)
#endif
// No security bit on SAM7A3
#if defined(at91sam7a3)
#define EFC_NO_SECURITY_BIT
#endif
//------------------------------------------------------------------------------
// Types
//------------------------------------------------------------------------------
// For chips which do not define AT91S_EFC
#if !defined(AT91C_BASE_EFC) && !defined(AT91C_BASE_EFC0)
typedef struct _AT91S_EFC {
AT91_REG EFC_FMR;
AT91_REG EFC_FCR;
AT91_REG EFC_FSR;
} AT91S_EFC, *AT91PS_EFC;
#define AT91C_BASE_EFC (AT91_CAST(AT91PS_EFC) 0xFFFFFF60)
#endif
//------------------------------------------------------------------------------
// Functions
//------------------------------------------------------------------------------
extern void EFC_SetMasterClock(unsigned int mck);
extern void EFC_EnableIt(AT91S_EFC *pEfc, unsigned int sources);
extern void EFC_DisableIt(AT91S_EFC *pEfc, unsigned int sources);
extern void EFC_SetEraseBeforeProgramming(AT91S_EFC *pEfc, unsigned char enable);
extern void EFC_TranslateAddress(
unsigned int address,
AT91S_EFC **ppEfc,
unsigned short *pPage,
unsigned short *pOffset);
extern void EFC_ComputeAddress(
AT91S_EFC *pEfc,
unsigned short page,
unsigned short offset,
unsigned int *pAddress);
extern void EFC_StartCommand(
AT91S_EFC *pEfc,
unsigned char command,
unsigned short argument);
extern unsigned char EFC_PerformCommand(
AT91S_EFC *pEfc,
unsigned char command,
unsigned short argument);
extern unsigned int EFC_GetStatus(AT91S_EFC *pEfc);
#endif //#ifdef BOARD_FLASH_EFC
#endif //#ifndef EFC_H
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/efc/efc.h | C | oos | 4,528 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef trace_LEVEL
#define trace_LEVEL trace_INFO
#endif
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include "efc.h"
#ifdef BOARD_FLASH_EFC
#include <utility/assert.h>
#include <utility/trace.h>
//------------------------------------------------------------------------------
// Local definitions
//------------------------------------------------------------------------------
// Round a number to the nearest integral value (number must have been
// multiplied by 10, e.g. to round 10.3 enter 103).
#define ROUND(n) ((((n) % 10) >= 5) ? (((n) / 10) + 1) : ((n) / 10))
// Returns the FMCN field value when manipulating lock bits, given MCK.
#if defined(at91sam7a3)
#define FMCN_BITS(mck) (ROUND((mck) / 100000) << 16) // <- Not correct according to the datasheet but it works
#else
#define FMCN_BITS(mck) (ROUND((mck) / 100000) << 16)
#endif
// Returns the FMCN field value when manipulating the rest of the flash.
#define FMCN_FLASH(mck) ((((mck) / 2000000) * 3) << 16)
//------------------------------------------------------------------------------
// Local functions
//------------------------------------------------------------------------------
/// Master clock frequency, used to infer the value of the FMCN field.
static unsigned int lMck;
/// Calculated value of the FMCN field base on Master clock frequency.
static unsigned int lMckFMCN;
//------------------------------------------------------------------------------
// Global functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// Sets the system master clock so the FMCN field of the EFC(s) can be
/// programmed properly.
/// \param mck Master clock frequency in Hz.
//------------------------------------------------------------------------------
void EFC_SetMasterClock(unsigned int mck)
{
lMck = mck;
lMckFMCN = FMCN_BITS(lMck);
}
//------------------------------------------------------------------------------
/// Enables the given interrupt sources on an EFC peripheral.
/// \param pEfc Pointer to an AT91S_EFC structure.
/// \param sources Interrupt sources to enable.
//------------------------------------------------------------------------------
void EFC_EnableIt(AT91S_EFC *pEfc, unsigned int sources)
{
SANITY_CHECK(pEfc);
SANITY_CHECK((sources & ~0x0000000D) == 0);
pEfc->EFC_FMR |= sources;
}
//------------------------------------------------------------------------------
/// Disables the given interrupt sources on an EFC peripheral.
/// \param pEfc Pointer to an AT91S_EFC structure.
/// \param sources Interrupt sources to disable.
//------------------------------------------------------------------------------
void EFC_DisableIt(AT91S_EFC *pEfc, unsigned int sources)
{
SANITY_CHECK(pEfc);
SANITY_CHECK((sources & ~(AT91C_MC_FRDY | AT91C_MC_LOCKE | AT91C_MC_PROGE)) == 0);
pEfc->EFC_FMR &= ~sources;
}
//------------------------------------------------------------------------------
/// Enables or disable the "Erase before programming" feature of an EFC.
/// \param pEfc Pointer to an AT91S_EFC structure.
/// \param enable If 1, the feature is enabled; otherwise it is disabled.
//------------------------------------------------------------------------------
void EFC_SetEraseBeforeProgramming(AT91S_EFC *pEfc, unsigned char enable)
{
SANITY_CHECK(pEfc);
if (enable) {
pEfc->EFC_FMR &= ~AT91C_MC_NEBP;
}
else {
pEfc->EFC_FMR |= AT91C_MC_NEBP;
}
}
//------------------------------------------------------------------------------
/// Translates the given address into EFC, page and offset values. The resulting
/// values are stored in the provided variables if they are not null.
/// \param address Address to translate.
/// \param ppEfc Pointer to target EFC peripheral.
/// \param pPage First page accessed.
/// \param pOffset Byte offset in first page.
//------------------------------------------------------------------------------
void EFC_TranslateAddress(
unsigned int address,
AT91S_EFC **ppEfc,
unsigned short *pPage,
unsigned short *pOffset)
{
AT91S_EFC *pEfc;
unsigned short page;
unsigned short offset;
SANITY_CHECK(address >= AT91C_IFLASH);
SANITY_CHECK(address <= (AT91C_IFLASH + AT91C_IFLASH_SIZE));
#if defined(AT91C_BASE_EFC0)
if (address >= (AT91C_IFLASH + AT91C_IFLASH_SIZE / 2)) {
pEfc = AT91C_BASE_EFC1;
page = (address - AT91C_IFLASH - AT91C_IFLASH_SIZE / 2) / AT91C_IFLASH_PAGE_SIZE;
offset = (address - AT91C_IFLASH - AT91C_IFLASH_SIZE / 2) % AT91C_IFLASH_PAGE_SIZE;
}
else {
pEfc = AT91C_BASE_EFC0;
page = (address - AT91C_IFLASH) / AT91C_IFLASH_PAGE_SIZE;
offset = (address - AT91C_IFLASH) % AT91C_IFLASH_PAGE_SIZE;
}
#else
pEfc = AT91C_BASE_EFC;
page = (address - AT91C_IFLASH) / AT91C_IFLASH_PAGE_SIZE;
offset = (address - AT91C_IFLASH) % AT91C_IFLASH_PAGE_SIZE;
#endif
trace_LOG(trace_DEBUG,
"-D- Translated 0x%08X to EFC=0x%08X, page=%d and offset=%d\n\r",
address, (unsigned int) pEfc, page, offset);
// Store values
if (ppEfc) {
*ppEfc = pEfc;
}
if (pPage) {
*pPage = page;
}
if (pOffset) {
*pOffset = offset;
}
}
//------------------------------------------------------------------------------
/// Computes the address of a flash access given the EFC, page and offset.
/// \param pEfc Pointer to an AT91S_EFC structure.
/// \param page Page number.
/// \param offset Byte offset inside page.
/// \param pAddress Computed address (optional).
//------------------------------------------------------------------------------
void EFC_ComputeAddress(
AT91S_EFC *pEfc,
unsigned short page,
unsigned short offset,
unsigned int *pAddress)
{
unsigned int address;
SANITY_CHECK(pEfc);
#if defined(AT91C_BASE_EFC1)
SANITY_CHECK(page <= (AT91C_IFLASH_NB_OF_PAGES / 2));
#else
SANITY_CHECK(page <= AT91C_IFLASH_NB_OF_PAGES);
#endif
SANITY_CHECK(offset < AT91C_IFLASH_PAGE_SIZE);
// Compute address
address = AT91C_IFLASH + page * AT91C_IFLASH_PAGE_SIZE + offset;
#if defined(AT91C_BASE_EFC1)
if (pEfc == AT91C_BASE_EFC1) {
address += AT91C_IFLASH_SIZE / 2;
}
#endif
// Store result
if (pAddress) {
*pAddress = address;
}
}
//------------------------------------------------------------------------------
/// Starts the executing the given command on an EFC. This function returns
/// as soon as the command is started. It does NOT set the FMCN field automatically.
/// \param pEfc Pointer to an AT91S_EFC structure.
/// \param command Command to execute.
/// \param argument Command argument (should be 0 if not used).
//------------------------------------------------------------------------------
void EFC_StartCommand(
AT91S_EFC *pEfc,
unsigned char command,
unsigned short argument)
{
SANITY_CHECK(pEfc);
ASSERT(lMck != 0, "-F- Master clock not set.\n\r");
// Check command & argument
switch (command) {
case AT91C_MC_FCMD_PROG_AND_LOCK:
ASSERT(0, "-F- Write and lock command cannot be carried out.\n\r");
break;
case AT91C_MC_FCMD_START_PROG:
case AT91C_MC_FCMD_LOCK:
case AT91C_MC_FCMD_UNLOCK:
ASSERT(argument < AT91C_IFLASH_NB_OF_PAGES,
"-F- Maximum number of pages is %d (argument was %d)\n\r",
AT91C_IFLASH_NB_OF_PAGES,
argument);
break;
#if (EFC_NUM_GPNVMS > 0)
case AT91C_MC_FCMD_SET_GP_NVM:
case AT91C_MC_FCMD_CLR_GP_NVM:
ASSERT(argument < EFC_NUM_GPNVMS, "-F- A maximum of %d GPNVMs are available on the chip.\n\r", EFC_NUM_GPNVMS);
break;
#endif
case AT91C_MC_FCMD_ERASE_ALL:
#if !defined(EFC_NO_SECURITY_BIT)
case AT91C_MC_FCMD_SET_SECURITY:
#endif
ASSERT(argument == 0, "-F- Argument is meaningless for the given command\n\r");
break;
default: ASSERT(0, "-F- Unknown command %d\n\r", command);
}
// Set FMCN
switch (command) {
case AT91C_MC_FCMD_LOCK:
case AT91C_MC_FCMD_UNLOCK:
#if (EFC_NUM_GPNVMS > 0)
case AT91C_MC_FCMD_SET_GP_NVM:
case AT91C_MC_FCMD_CLR_GP_NVM:
#endif
#if !defined(EFC_NO_SECURITY_BIT)
case AT91C_MC_FCMD_SET_SECURITY:
#endif
pEfc->EFC_FMR = (pEfc->EFC_FMR & ~AT91C_MC_FMCN) | lMckFMCN;
break;
case AT91C_MC_FCMD_START_PROG:
case AT91C_MC_FCMD_ERASE_ALL:
pEfc->EFC_FMR = (pEfc->EFC_FMR & ~AT91C_MC_FMCN) | lMckFMCN;
break;
}
// Start command
ASSERT((pEfc->EFC_FSR & AT91C_MC_FRDY) != 0, "-F- Efc is not ready\n\r");
pEfc->EFC_FCR = (0x5A << 24) | (argument << 8) | command;
}
//------------------------------------------------------------------------------
/// Performs the given command and wait until its completion (or an error).
/// Returns 0 if successful; otherwise returns an error code.
/// \param pEfc Pointer to an AT91S_EFC structure.
/// \param command Command to perform.
/// \param argument Optional command argument.
//------------------------------------------------------------------------------
#ifdef __ICCARM__
__ramfunc
#else
__attribute__ ((section (".ramfunc")))
#endif
unsigned char EFC_PerformCommand(
AT91S_EFC *pEfc,
unsigned char command,
unsigned short argument)
{
unsigned int status;
// Set FMCN
switch (command) {
case AT91C_MC_FCMD_LOCK:
case AT91C_MC_FCMD_UNLOCK:
#if (EFC_NUM_GPNVMS > 0)
case AT91C_MC_FCMD_SET_GP_NVM:
case AT91C_MC_FCMD_CLR_GP_NVM:
#endif
#if !defined(EFC_NO_SECURITY_BIT)
case AT91C_MC_FCMD_SET_SECURITY:
#endif
pEfc->EFC_FMR = (pEfc->EFC_FMR & ~AT91C_MC_FMCN) | lMckFMCN;
break;
case AT91C_MC_FCMD_START_PROG:
case AT91C_MC_FCMD_ERASE_ALL:
pEfc->EFC_FMR = (pEfc->EFC_FMR & ~AT91C_MC_FMCN) | lMckFMCN;
break;
}
#ifdef BOARD_FLASH_IAP_ADDRESS
// Pointer on IAP function in ROM
static void (*IAP_PerformCommand)(unsigned int, unsigned int);
unsigned int index = 0;
#ifdef AT91C_BASE_EFC1
if (pEfc == AT91C_BASE_EFC1) {
index = 1;
}
#endif
IAP_PerformCommand = (void (*)(unsigned int, unsigned int)) *((unsigned int *) BOARD_FLASH_IAP_ADDRESS);
// Check if IAP function is implemented (opcode in SWI != 'b' or 'ldr') */
if ((((((unsigned long) IAP_PerformCommand >> 24) & 0xFF) != 0xEA) &&
(((unsigned long) IAP_PerformCommand >> 24) & 0xFF) != 0xE5)) {
IAP_PerformCommand(index, (0x5A << 24) | (argument << 8) | command);
return (pEfc->EFC_FSR & (AT91C_MC_LOCKE | AT91C_MC_PROGE));
}
#endif
pEfc->EFC_FCR = (0x5A << 24) | (argument << 8) | command;
do {
status = pEfc->EFC_FSR;
}
while ((status & AT91C_MC_FRDY) == 0);
return (status & (AT91C_MC_PROGE | AT91C_MC_LOCKE));
}
//------------------------------------------------------------------------------
/// Returns the current status of an EFC. Keep in mind that this function clears
/// the value of some status bits (LOCKE, PROGE).
/// \param pEfc Pointer to an AT91S_EFC structure.
//------------------------------------------------------------------------------
unsigned int EFC_GetStatus(AT91S_EFC *pEfc)
{
return pEfc->EFC_FSR;
}
#endif //#ifdef BOARD_FLASH_EFC
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/efc/efc.c | C | oos | 13,715 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef trace_LEVEL
#define trace_LEVEL 1
#endif
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include "twi.h"
#include <utility/math.h>
#include <utility/assert.h>
#include <utility/trace.h>
//------------------------------------------------------------------------------
// Global functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// Configures a TWI peripheral to operate in master mode, at the given
/// frequency (in Hz). The duty cycle of the TWI clock is set to 50%.
/// \param pTwi Pointer to an AT91S_TWI instance.
/// \param twck Desired TWI clock frequency.
/// \param mck Master clock frequency.
//------------------------------------------------------------------------------
void TWI_Configure(AT91S_TWI *pTwi, unsigned int twck, unsigned int mck)
{
unsigned int ckdiv = 0;
unsigned int cldiv;
unsigned char ok = 0;
trace_LOG(trace_DEBUG, "-D- TWI_Configure()\n\r");
SANITY_CHECK(pTwi);
// Reset the TWI
pTwi->TWI_CR = AT91C_TWI_SWRST;
// Set master mode
pTwi->TWI_CR = AT91C_TWI_MSEN;
// Configure clock
while (!ok) {
cldiv = ((mck / (2 * twck)) - 3) / power(2, ckdiv);
if (cldiv <= 255) {
ok = 1;
}
else {
ckdiv++;
}
}
ASSERT(ckdiv < 8, "-F- Cannot find valid TWI clock parameters\n\r");
trace_LOG(trace_INFO, "-D- Using CKDIV = %u and CLDIV/CHDIV = %u\n\r", ckdiv, cldiv);
pTwi->TWI_CWGR = (ckdiv << 16) | (cldiv << 8) | cldiv;
}
//------------------------------------------------------------------------------
/// Sends a STOP condition on the TWI.
/// \param pTwi Pointer to an AT91S_TWI instance.
//------------------------------------------------------------------------------
void TWI_Stop(AT91S_TWI *pTwi)
{
SANITY_CHECK(pTwi);
pTwi->TWI_CR = AT91C_TWI_STOP;
}
//------------------------------------------------------------------------------
/// Starts a read operation on the TWI bus with the specified slave, and returns
/// immediately. Data must then be read using TWI_ReadByte() whenever a byte is
/// available (poll using TWI_ByteReceived()).
/// \param pTwi Pointer to an AT91S_TWI instance.
/// \param address Slave address on the bus.
/// \param iaddress Optional internal address bytes.
/// \param isize Number of internal address bytes.
//-----------------------------------------------------------------------------
void TWI_StartRead(
AT91S_TWI *pTwi,
unsigned char address,
unsigned int iaddress,
unsigned char isize)
{
trace_LOG(trace_DEBUG, "-D- TWI_StartRead()\n\r");
SANITY_CHECK(pTwi);
SANITY_CHECK((address & 0x80) == 0);
SANITY_CHECK((iaddress & 0xFF000000) == 0);
SANITY_CHECK(isize < 4);
// Set slave address and number of internal address bytes
pTwi->TWI_MMR = (isize << 8) | AT91C_TWI_MREAD | (address << 16);
// Set internal address bytes
pTwi->TWI_IADR = iaddress;
// Send START condition
pTwi->TWI_CR = AT91C_TWI_START;
}
//-----------------------------------------------------------------------------
/// Reads a byte from the TWI bus. The read operation must have been started
/// using TWI_StartRead() and a byte must be available (check with
/// TWI_ByteReceived()).
/// Returns the byte read.
/// \param pTwi Pointer to an AT91S_TWI instance.
//-----------------------------------------------------------------------------
unsigned char TWI_ReadByte(AT91S_TWI *pTwi)
{
SANITY_CHECK(pTwi);
return pTwi->TWI_RHR;
}
//-----------------------------------------------------------------------------
/// Sends a byte of data to one of the TWI slaves on the bus. This function
/// must be called once before TWI_StartWrite() with the first byte of data
/// to send, then it shall be called repeatedly after that to send the
/// remaining bytes.
/// \param pTwi Pointer to an AT91S_TWI instance.
/// \param byte Byte to send.
//-----------------------------------------------------------------------------
void TWI_WriteByte(AT91S_TWI *pTwi, unsigned char byte)
{
SANITY_CHECK(pTwi);
pTwi->TWI_THR = byte;
}
//-----------------------------------------------------------------------------
/// Starts a write operation on the TWI to access the selected slave, then
/// returns immediately. A byte of data must be provided to start the write;
/// other bytes are written next.
/// \param pTwi Pointer to an AT91S_TWI instance.
/// \param address Address of slave to acccess on the bus.
/// \param iaddress Optional slave internal address.
/// \param isize Number of internal address bytes.
/// \param byte First byte to send.
//-----------------------------------------------------------------------------
void TWI_StartWrite(
AT91S_TWI *pTwi,
unsigned char address,
unsigned int iaddress,
unsigned char isize,
unsigned char byte)
{
trace_LOG(trace_DEBUG, "-D- TWI_StartWrite()\n\r");
SANITY_CHECK(pTwi);
SANITY_CHECK((address & 0x80) == 0);
SANITY_CHECK((iaddress & 0xFF000000) == 0);
SANITY_CHECK(isize < 4);
// Set slave address and number of internal address bytes
pTwi->TWI_MMR = (isize << 8) | (address << 16);
// Set internal address bytes
pTwi->TWI_IADR = iaddress;
// Write first byte to send
TWI_WriteByte(pTwi, byte);
}
//-----------------------------------------------------------------------------
/// Returns 1 if a byte has been received and can be read on the given TWI
/// peripheral; otherwise, returns 0. This function resets the status register
/// of the TWI.
/// \param pTwi Pointer to an AT91S_TWI instance.
//-----------------------------------------------------------------------------
unsigned char TWI_ByteReceived(AT91S_TWI *pTwi)
{
return ((pTwi->TWI_SR & AT91C_TWI_RXRDY) == AT91C_TWI_RXRDY);
}
//-----------------------------------------------------------------------------
/// Returns 1 if a byte has been sent, so another one can be stored for
/// transmission; otherwise returns 0. This function clears the status register
/// of the TWI.
/// \param pTwi Pointer to an AT91S_TWI instance.
//-----------------------------------------------------------------------------
unsigned char TWI_ByteSent(AT91S_TWI *pTwi)
{
return ((pTwi->TWI_SR & AT91C_TWI_TXRDY) == AT91C_TWI_TXRDY);
}
//-----------------------------------------------------------------------------
/// Returns 1 if the current transmission is complete (the STOP has been sent);
/// otherwise returns 0.
/// \param pTwi Pointer to an AT91S_TWI instance.
//-----------------------------------------------------------------------------
unsigned char TWI_TransferComplete(AT91S_TWI *pTwi)
{
return ((pTwi->TWI_SR & AT91C_TWI_TXCOMP) == AT91C_TWI_TXCOMP);
}
//-----------------------------------------------------------------------------
/// Enables the selected interrupts sources on a TWI peripheral.
/// \param pTwi Pointer to an AT91S_TWI instance.
/// \param sources Bitwise OR of selected interrupt sources.
//-----------------------------------------------------------------------------
void TWI_EnableIt(AT91S_TWI *pTwi, unsigned int sources)
{
SANITY_CHECK(pTwi);
SANITY_CHECK((sources & 0xFFFFFEF8) == 0);
pTwi->TWI_IER = sources;
}
//-----------------------------------------------------------------------------
/// Disables the selected interrupts sources on a TWI peripheral.
/// \param pTwi Pointer to an AT91S_TWI instance.
/// \param sources Bitwise OR of selected interrupt sources.
//-----------------------------------------------------------------------------
void TWI_DisableIt(AT91S_TWI *pTwi, unsigned int sources)
{
SANITY_CHECK(pTwi);
SANITY_CHECK((sources & 0xFFFFFEF8) == 0);
pTwi->TWI_IDR = sources;
}
//-----------------------------------------------------------------------------
/// Returns the current status register of the given TWI peripheral. This
/// resets the internal value of the status register, so further read may yield
/// different values.
/// \param pTwi Pointer to an AT91S_TWI instance.
//-----------------------------------------------------------------------------
unsigned int TWI_GetStatus(AT91S_TWI *pTwi)
{
SANITY_CHECK(pTwi);
return pTwi->TWI_SR;
}
//-----------------------------------------------------------------------------
/// Returns the current status register of the given TWI peripheral, but
/// masking interrupt sources which are not currently enabled.
/// This resets the internal value of the status register, so further read may
/// yield different values.
/// \param pTwi Pointer to an AT91S_TWI instance.
//-----------------------------------------------------------------------------
unsigned int TWI_GetMaskedStatus(AT91S_TWI *pTwi)
{
unsigned int status;
SANITY_CHECK(pTwi);
status = pTwi->TWI_SR;
status &= pTwi->TWI_IMR;
return status;
}
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/twi/twi.c | C | oos | 10,963 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef TWI_H
#define TWI_H
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include <board.h>
//------------------------------------------------------------------------------
// Global definitions
//------------------------------------------------------------------------------
// Missing AT91C_TWI_TXRDY definition.
#ifndef AT91C_TWI_TXRDY
#define AT91C_TWI_TXRDY AT91C_TWI_TXRDY_MASTER
#endif
// Missing AT91C_TWI_TXCOMP definition.
#ifndef AT91C_TWI_TXCOMP
#define AT91C_TWI_TXCOMP AT91C_TWI_TXCOMP_MASTER
#endif
//------------------------------------------------------------------------------
// Global macros
//------------------------------------------------------------------------------
/// Returns 1 if the TXRDY bit (ready to transmit data) is set in the given
/// status register value.
#define TWI_STATUS_TXRDY(status) ((status & AT91C_TWI_TXRDY) == AT91C_TWI_TXRDY)
/// Returns 1 if the RXRDY bit (ready to receive data) is set in the given
/// status register value.
#define TWI_STATUS_RXRDY(status) ((status & AT91C_TWI_RXRDY) == AT91C_TWI_RXRDY)
/// Returns 1 if the TXCOMP bit (transfer complete) is set in the given
/// status register value.
#define TWI_STATUS_TXCOMP(status) ((status & AT91C_TWI_TXCOMP) == AT91C_TWI_TXCOMP)
//------------------------------------------------------------------------------
// Global functions
//------------------------------------------------------------------------------
extern void TWI_Configure(AT91S_TWI *pTwi, unsigned int twck, unsigned int mck);
extern void TWI_Stop(AT91S_TWI *pTwi);
extern void TWI_StartRead(
AT91S_TWI *pTwi,
unsigned char address,
unsigned int iaddress,
unsigned char isize);
extern unsigned char TWI_ReadByte(AT91S_TWI *pTwi);
extern void TWI_WriteByte(AT91S_TWI *pTwi, unsigned char byte);
extern void TWI_StartWrite(
AT91S_TWI *pTwi,
unsigned char address,
unsigned int iaddress,
unsigned char isize,
unsigned char byte);
extern unsigned char TWI_ByteReceived(AT91S_TWI *pTwi);
extern unsigned char TWI_ByteSent(AT91S_TWI *pTwi);
extern unsigned char TWI_TransferComplete(AT91S_TWI *pTwi);
extern void TWI_EnableIt(AT91S_TWI *pTwi, unsigned int sources);
extern void TWI_DisableIt(AT91S_TWI *pTwi, unsigned int sources);
extern unsigned int TWI_GetStatus(AT91S_TWI *pTwi);
extern unsigned int TWI_GetMaskedStatus(AT91S_TWI *pTwi);
#endif //#ifndef TWI_H
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/twi/twi.h | C | oos | 4,219 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef trace_LEVEL
#define trace_LEVEL trace_INFO
#endif
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include "eefc.h"
#ifdef BOARD_FLASH_EEFC
#include <utility/assert.h>
#include <utility/trace.h>
//------------------------------------------------------------------------------
// Global functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// Enables the flash ready interrupt source on the EEFC peripheral.
//------------------------------------------------------------------------------
void EFC_EnableFrdyIt(void)
{
AT91C_BASE_EFC->EFC_FMR |= AT91C_EFC_FRDY;
}
//------------------------------------------------------------------------------
/// Disables the flash ready interrupt source on the EEFC peripheral.
//------------------------------------------------------------------------------
void EFC_DisableFrdyIt(void)
{
AT91C_BASE_EFC->EFC_FMR &= ~AT91C_EFC_FRDY;
}
//------------------------------------------------------------------------------
/// Translates the given address page and offset values. The resulting
/// values are stored in the provided variables if they are not null.
/// \param address Address to translate.
/// \param pPage First page accessed.
/// \param pOffset Byte offset in first page.
//------------------------------------------------------------------------------
void EFC_TranslateAddress(
unsigned int address,
unsigned short *pPage,
unsigned short *pOffset)
{
unsigned short page;
unsigned short offset;
SANITY_CHECK(address >= AT91C_IFLASH);
SANITY_CHECK(address <= (AT91C_IFLASH + AT91C_IFLASH_SIZE));
// Calculate page & offset
page = (address - AT91C_IFLASH) / AT91C_IFLASH_PAGE_SIZE;
offset = (address - AT91C_IFLASH) % AT91C_IFLASH_PAGE_SIZE;
trace_LOG(trace_DEBUG,
"-D- Translated 0x%08X to page=%d and offset=%d\n\r",
address, page, offset);
// Store values
if (pPage) {
*pPage = page;
}
if (pOffset) {
*pOffset = offset;
}
}
//------------------------------------------------------------------------------
/// Computes the address of a flash access given the page and offset.
/// \param page Page number.
/// \param offset Byte offset inside page.
/// \param pAddress Computed address (optional).
//------------------------------------------------------------------------------
void EFC_ComputeAddress(
unsigned short page,
unsigned short offset,
unsigned int *pAddress)
{
unsigned int address;
SANITY_CHECK(page <= AT91C_IFLASH_NB_OF_PAGES);
SANITY_CHECK(offset < AT91C_IFLASH_PAGE_SIZE);
// Compute address
address = AT91C_IFLASH + page * AT91C_IFLASH_PAGE_SIZE + offset;
// Store result
if (pAddress) {
*pAddress = address;
}
}
//------------------------------------------------------------------------------
/// Starts the executing the given command on the EEFC. This function returns
/// as soon as the command is started. It does NOT set the FMCN field automatically.
/// \param command Command to execute.
/// \param argument Command argument (should be 0 if not used).
//------------------------------------------------------------------------------
void EFC_StartCommand(unsigned char command, unsigned short argument)
{
// Check command & argument
switch (command) {
case AT91C_EFC_FCMD_WP:
case AT91C_EFC_FCMD_WPL:
case AT91C_EFC_FCMD_EWP:
case AT91C_EFC_FCMD_EWPL:
case AT91C_EFC_FCMD_EPL:
case AT91C_EFC_FCMD_EPA:
case AT91C_EFC_FCMD_SLB:
case AT91C_EFC_FCMD_CLB:
ASSERT(argument < AT91C_IFLASH_NB_OF_PAGES,
"-F- Embedded flash has only %d pages\n\r",
AT91C_IFLASH_NB_OF_PAGES);
break;
case AT91C_EFC_FCMD_SFB:
case AT91C_EFC_FCMD_CFB:
ASSERT(argument < EFC_NUM_GPNVMS, "-F- Embedded flash has only %d GPNVMs\n\r", EFC_NUM_GPNVMS);
break;
case AT91C_EFC_FCMD_GETD:
case AT91C_EFC_FCMD_EA:
case AT91C_EFC_FCMD_GLB:
case AT91C_EFC_FCMD_GFB:
ASSERT(argument == 0, "-F- Argument is meaningless for the given command.\n\r");
break;
default: ASSERT(0, "-F- Unknown command %d\n\r", command);
}
// Start commandEmbedded flash
ASSERT((AT91C_BASE_EFC->EFC_FSR & AT91C_EFC_FRDY) == AT91C_EFC_FRDY, "-F- EEFC is not ready\n\r");
AT91C_BASE_EFC->EFC_FCR = (0x5A << 24) | (argument << 8) | command;
}
//------------------------------------------------------------------------------
/// Performs the given command and wait until its completion (or an error).
/// Returns 0 if successful; otherwise returns an error code.
/// \param command Command to perform.
/// \param argument Optional command argument.
//------------------------------------------------------------------------------
#ifdef __ICCARM__
__ramfunc
#else
__attribute__ ((section (".ramfunc")))
#endif
unsigned char EFC_PerformCommand(unsigned char command, unsigned short argument)
{
unsigned int status;
#ifdef BOARD_FLASH_IAP_ADDRESS
// Pointer on IAP function in ROM
static void (*IAP_PerformCommand)(unsigned int);
IAP_PerformCommand = (void (*)(unsigned int)) *((unsigned int *) BOARD_FLASH_IAP_ADDRESS);
// Check if IAP function is implemented (opcode in SWI != 'b' or 'ldr') */
if ((((((unsigned long) IAP_PerformCommand >> 24) & 0xFF) != 0xEA) &&
(((unsigned long) IAP_PerformCommand >> 24) & 0xFF) != 0xE5)) {
IAP_PerformCommand((0x5A << 24) | (argument << 8) | command);
return (AT91C_BASE_EFC->EFC_FSR & (AT91C_EFC_LOCKE | AT91C_EFC_FCMDE));
}
#endif
AT91C_BASE_EFC->EFC_FCR = (0x5A << 24) | (argument << 8) | command;
do {
status = AT91C_BASE_EFC->EFC_FSR;
}
while ((status & AT91C_EFC_FRDY) != AT91C_EFC_FRDY);
return (status & (AT91C_EFC_LOCKE | AT91C_EFC_FCMDE));
}
//------------------------------------------------------------------------------
/// Returns the current status of the EEFC. Keep in mind that this function clears
/// the value of some status bits (LOCKE, PROGE).
//------------------------------------------------------------------------------
unsigned int EFC_GetStatus(void)
{
return AT91C_BASE_EFC->EFC_FSR;
}
//------------------------------------------------------------------------------
/// Returns the result of the last executed command.
//------------------------------------------------------------------------------
unsigned int EFC_GetResult(void) {
return AT91C_BASE_EFC->EFC_FRR;
}
#endif //#ifdef BOARD_FLASH_EEFC
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/eefc/eefc.c | C | oos | 8,678 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef EEFC_H
#define EEFC_H
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include <board.h>
#ifdef BOARD_FLASH_EEFC
//------------------------------------------------------------------------------
// Constants
//------------------------------------------------------------------------------
/// Number of GPNVMs available on each chip.
#if defined(at91sam7l64) || defined(at91sam7l128)
#define EFC_NUM_GPNVMS 2
#elif defined(at91sam9xe128) || defined(at91sam9xe256) || defined(at91sam9xe512)
#define EFC_NUM_GPNVMS 17
#endif
//------------------------------------------------------------------------------
// Types
//------------------------------------------------------------------------------
// Needed when EEFC is integrated in MC.
#if !defined(AT91C_BASE_EFC) && defined(AT91C_BASE_MC)
typedef struct _AT91S_EFC {
AT91_REG EFC_FMR; // EFC Flash Mode Register
AT91_REG EFC_FCR; // EFC Flash Command Register
AT91_REG EFC_FSR; // EFC Flash Status Register
AT91_REG EFC_FRR; // EFC Flash Result Register
AT91_REG EFC_FVR; // EFC Flash Version Register
} AT91S_EFC, *AT91PS_EFC;
#define AT91C_EFC_FRDY AT91C_MC_FRDY
#define AT91C_EFC_FWS AT91C_MC_FWS
#define AT91C_EFC_FWS_0WS AT91C_MC_FWS_0WS
#define AT91C_EFC_FWS_1WS AT91C_MC_FWS_1WS
#define AT91C_EFC_FWS_2WS AT91C_MC_FWS_2WS
#define AT91C_EFC_FWS_3WS AT91C_MC_FWS_3WS
#define AT91C_EFC_FCMD AT91C_MC_FCMD
#define AT91C_EFC_FCMD_GETD AT91C_MC_FCMD_GETD
#define AT91C_EFC_FCMD_WP AT91C_MC_FCMD_WP
#define AT91C_EFC_FCMD_WPL AT91C_MC_FCMD_WPL
#define AT91C_EFC_FCMD_EWP AT91C_MC_FCMD_EWP
#define AT91C_EFC_FCMD_EWPL AT91C_MC_FCMD_EWPL
#define AT91C_EFC_FCMD_EA AT91C_MC_FCMD_EA
#define AT91C_EFC_FCMD_EPL AT91C_MC_FCMD_EPL
#define AT91C_EFC_FCMD_EPA AT91C_MC_FCMD_EPA
#define AT91C_EFC_FCMD_SLB AT91C_MC_FCMD_SLB
#define AT91C_EFC_FCMD_CLB AT91C_MC_FCMD_CLB
#define AT91C_EFC_FCMD_GLB AT91C_MC_FCMD_GLB
#define AT91C_EFC_FCMD_SFB AT91C_MC_FCMD_SFB
#define AT91C_EFC_FCMD_CFB AT91C_MC_FCMD_CFB
#define AT91C_EFC_FCMD_GFB AT91C_MC_FCMD_GFB
#define AT91C_EFC_FARG AT91C_MC_FARG
#define AT91C_EFC_FKEY AT91C_MC_FKEY
#define AT91C_EFC_FRDY_S AT91C_MC_FRDY_S
#define AT91C_EFC_FCMDE AT91C_MC_FCMDE
#define AT91C_EFC_LOCKE AT91C_MC_LOCKE
#define AT91C_EFC_FVALUE AT91C_MC_FVALUE
#define AT91C_BASE_EFC (AT91_CAST(AT91PS_EFC) 0xFFFFFF60)
#endif //#if !defined(AT91C_BASE_EFC) && defined(AT91C_BASE_MC)
//------------------------------------------------------------------------------
// Functions
//------------------------------------------------------------------------------
extern void EFC_EnableFrdyIt(void);
extern void EFC_DisableFrdyIt(void);
extern void EFC_TranslateAddress(
unsigned int address,
unsigned short *pPage,
unsigned short *pOffset);
extern void EFC_ComputeAddress(
unsigned short page,
unsigned short offset,
unsigned int *pAddress);
extern void EFC_StartCommand(
unsigned char command,
unsigned short argument);
extern unsigned char EFC_PerformCommand(
unsigned char command,
unsigned short argument);
extern unsigned int EFC_GetStatus(void);
extern unsigned int EFC_GetResult(void);
#endif //#ifdef BOARD_FLASH_EEFC
#endif //#ifndef EEFC_H
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/eefc/eefc.h | C | oos | 5,385 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include "lcd.h"
#include <board.h>
#include <utility/assert.h>
//------------------------------------------------------------------------------
// Exported functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// Enables the LCD controller, after waiting for the specified number of
/// frames.
/// \param frames Number of frames before the LCD is enabled.
//------------------------------------------------------------------------------
void LCD_Enable(unsigned int frames)
{
ASSERT((frames & 0xFFFFFF80) == 0,
"LCD_Enable: Wrong frames value.\n\r");
AT91C_BASE_LCDC->LCDC_PWRCON = AT91C_LCDC_PWR | (frames << 1);
}
//------------------------------------------------------------------------------
/// Disables the LCD controller, after waiting for the specified number of
/// frames.
/// \param frames Number of frames before the LCD is shut down.
//------------------------------------------------------------------------------
void LCD_Disable(unsigned int frames)
{
ASSERT((frames & 0xFFFFFF80) == 0,
"LCD_Disable: Wrong frames value.\n\r");
AT91C_BASE_LCDC->LCDC_PWRCON = frames << 1;
}
//------------------------------------------------------------------------------
/// Enables the DMA of the LCD controller.
//------------------------------------------------------------------------------
void LCD_EnableDma()
{
AT91C_BASE_LCDC->LCDC_DMACON = AT91C_LCDC_DMAEN;
}
//------------------------------------------------------------------------------
/// Disables the DMA of the LCD controller.
//------------------------------------------------------------------------------
void LCD_DisableDma()
{
AT91C_BASE_LCDC->LCDC_DMACON = 0;
}
//------------------------------------------------------------------------------
/// Configures the internal clock of the LCD controller given the master clock of
/// the system and the desired pixel clock in MHz.
/// \param masterClock Master clock frequency.
/// \param pixelClock Pixel clock frequency.
//------------------------------------------------------------------------------
void LCD_SetPixelClock(unsigned int masterClock, unsigned int pixelClock)
{
AT91C_BASE_LCDC->LCDC_LCDCON1 = ((masterClock / (2 * pixelClock)) - 1) << 12;
}
//------------------------------------------------------------------------------
/// Sets the type of display used with the LCD controller.
/// \param displayType Type of display used.
//------------------------------------------------------------------------------
void LCD_SetDisplayType(unsigned int displayType)
{
unsigned int value;
ASSERT((displayType & ~AT91C_LCDC_DISTYPE) == 0,
"LCD_SetDisplayType: Wrong display type value.\n\r");
value = AT91C_BASE_LCDC->LCDC_LCDCON2;
value &= ~AT91C_LCDC_DISTYPE;
value |= displayType;
AT91C_BASE_LCDC->LCDC_LCDCON2 = value;
}
//------------------------------------------------------------------------------
/// Sets the scan mode used by the LCD (either single scan or double-scan).
/// \param scanMode Scan mode to use.
//------------------------------------------------------------------------------
void LCD_SetScanMode(unsigned int scanMode)
{
unsigned int value;
ASSERT((scanMode & ~AT91C_LCDC_SCANMOD) == 0,
"LCD_SetScanMode: Wrong scan mode value.\n\r");
value = AT91C_BASE_LCDC->LCDC_LCDCON2;
value &= ~AT91C_LCDC_SCANMOD;
value |= scanMode;
AT91C_BASE_LCDC->LCDC_LCDCON2 = value;
}
//------------------------------------------------------------------------------
/// Sets the number of bits per pixel used by the LCD display.
/// \param bitsPerPixel Number of bits per pixel to use.
//------------------------------------------------------------------------------
void LCD_SetBitsPerPixel(unsigned int bitsPerPixel)
{
unsigned int value;
ASSERT((bitsPerPixel & ~AT91C_LCDC_PIXELSIZE) == 0,
"LCD_SetScanMode: Wrong bitsPerPixel value.\n\r");
value = AT91C_BASE_LCDC->LCDC_LCDCON2;
value &= ~AT91C_LCDC_PIXELSIZE;
value |= bitsPerPixel;
AT91C_BASE_LCDC->LCDC_LCDCON2 = value;
}
//------------------------------------------------------------------------------
/// Sets the LCDD, LCDVSYNC, LCDHSYNC, LCDDOTCLK and LCDDEN signal polarities.
/// \param lcdd LCDD signal polarity.
/// \param lcdvsync LCDVSYNC signal polarity.
/// \param lcdhsync LCDHSYNC signal polarity.
/// \param lcddotclk LCDDOTCLK signal polarity.
/// \param lcdden LCDDEN signal polarity.
//------------------------------------------------------------------------------
void LCD_SetPolarities(
unsigned int lcdd,
unsigned int lcdvsync,
unsigned int lcdhsync,
unsigned int lcddotclk,
unsigned int lcdden)
{
unsigned int value;
ASSERT((lcdd & ~AT91C_LCDC_INVVD) == 0,
"LCD_SetPolarities: Wrong lcdd value.\n\r");
ASSERT((lcdvsync & ~AT91C_LCDC_INVFRAME) == 0,
"LCD_SetPolarities: Wrong lcdvsync value.\n\r");
ASSERT((lcdhsync & ~AT91C_LCDC_INVLINE) == 0,
"LCD_SetPolarities: Wrong lcdhsync value.\n\r");
ASSERT((lcddotclk & ~AT91C_LCDC_INVCLK) == 0,
"LCD_SetPolarities: Wrong lcddotclk value.\n\r");
ASSERT((lcdden & ~AT91C_LCDC_INVDVAL) == 0,
"LCD_SetPolarities: Wrong lcdden value.\n\r");
value = AT91C_BASE_LCDC->LCDC_LCDCON2;
value &= 0xFFFFE0FF;
value |= lcdd | lcdvsync | lcdhsync | lcddotclk | lcdden;
AT91C_BASE_LCDC->LCDC_LCDCON2 = value;
}
//------------------------------------------------------------------------------
/// Sets the LCD clock mode, i.e. always active or active only during display
/// period.
/// \param clockMode Clock mode to use.
//------------------------------------------------------------------------------
void LCD_SetClockMode(unsigned int clockMode)
{
unsigned int value;
ASSERT((clockMode & ~AT91C_LCDC_CLKMOD) == 0,
"LCD_SetScanMode: Wrong scan mode value.\n\r");
value = AT91C_BASE_LCDC->LCDC_LCDCON2;
value &= ~AT91C_LCDC_CLKMOD;
value |= clockMode;
AT91C_BASE_LCDC->LCDC_LCDCON2 = value;
}
//------------------------------------------------------------------------------
/// Sets the format of the frame buffer memory.
/// \param format Memory ordering format.
//------------------------------------------------------------------------------
void LCD_SetMemoryFormat(unsigned int format)
{
unsigned int value;
ASSERT((format & ~AT91C_LCDC_MEMOR) == 0,
"LCD_SetMemoryFormat: Wrong memory format value.\n\r");
value = AT91C_BASE_LCDC->LCDC_LCDCON2;
value &= ~AT91C_LCDC_MEMOR;
value |= format;
AT91C_BASE_LCDC->LCDC_LCDCON2 = value;
}
//------------------------------------------------------------------------------
/// Sets the size in pixel of the LCD display.
/// \param width Width in pixel of the LCD display.
/// \param height Height in pixel of the LCD display.
//------------------------------------------------------------------------------
void LCD_SetSize(unsigned int width, unsigned int height)
{
ASSERT(((width - 1) & 0xFFFFF800) == 0,
"LCD_SetSize: Wrong width value.\n\r");
ASSERT(((height - 1) & 0xFFFFF800) == 0,
"LCD_SetSize: Wrong height value.\n\r");
AT91C_BASE_LCDC->LCDC_LCDFRCFG = ((width - 1) << 21) | (height - 1);
}
//------------------------------------------------------------------------------
/// Sets the vertical timings of the LCD controller. Only meaningful when
/// using a TFT display.
/// \param vfp Number of idle lines at the end of a frame.
/// \param vbp Number of idle lines at the beginning of a frame.
/// \param vpw Vertical synchronization pulse width in number of lines.
/// \param vhdly Delay between LCDVSYNC edge and LCDHSYNC rising edge, in
/// LCDDOTCLK cycles.
//------------------------------------------------------------------------------
void LCD_SetVerticalTimings(
unsigned int vfp,
unsigned int vbp,
unsigned int vpw,
unsigned int vhdly)
{
ASSERT((vfp & 0xFFFFFF00) == 0,
"LCD_SetVerticalTimings: Wrong vfp value.\n\r");
ASSERT((vbp & 0xFFFFFF00) == 0,
"LCD_SetVerticalTimings: Wrong vbp value.\n\r");
ASSERT(((vpw-1) & 0xFFFFFFC0) == 0,
"LCD_SetVerticalTimings: Wrong vpw value.\n\r");
ASSERT(((vhdly-1) & 0xFFFFFFF0) == 0,
"LCD_SetVerticalTimings: Wrong vhdly value.\n\r");
AT91C_BASE_LCDC->LCDC_TIM1 = vfp
| (vbp << 8)
| ((vpw-1) << 16)
| ((vhdly-1) << 24);
}
//------------------------------------------------------------------------------
/// Sets the horizontal timings of the LCD controller. Meaningful for both
/// STN and TFT displays.
/// \param hbp Number of idle LCDDOTCLK cycles at the beginning of a line.
/// \param hpw Width of the LCDHSYNC pulse, in LCDDOTCLK cycles.
/// \param hfp Number of idel LCDDOTCLK cycles at the end of a line.
//------------------------------------------------------------------------------
void LCD_SetHorizontalTimings(
unsigned int hbp,
unsigned int hpw,
unsigned int hfp)
{
ASSERT(((hbp-1) & 0xFFFFFF00) == 0,
"LCD_SetHorizontalTimings: Wrong hbp value.\n\r");
ASSERT(((hpw-1) & 0xFFFFFFC0) == 0,
"LCD_SetHorizontalTimings: Wrong hpw value.\n\r");
ASSERT(((hfp-1) & 0xFFFFFF00) == 0,
"LCD_SetHorizontalTimings: Wrong hfp value.\n\r");
AT91C_BASE_LCDC->LCDC_TIM2 = (hbp-1) | ((hpw-1) << 8) | ((hfp-1) << 24);
}
//------------------------------------------------------------------------------
/// Sets the address of the frame buffer in the LCD controller DMA. When using
/// dual-scan mode, this is the upper frame buffer.
/// \param address Frame buffer address.
//------------------------------------------------------------------------------
void LCD_SetFrameBufferAddress(void *address)
{
AT91C_BASE_LCDC->LCDC_BA1 = (unsigned int) address;
}
//------------------------------------------------------------------------------
/// Sets the size in pixels of a frame (height * width * bpp).
/// \param frameSize Size of frame in pixels.
//------------------------------------------------------------------------------
void LCD_SetFrameSize(unsigned int frameSize)
{
ASSERT((frameSize & 0xFF800000) == 0,
"LCD_SetFrameSize: Wrong frameSize value.\n\r");
AT91C_BASE_LCDC->LCDC_FRMCFG = frameSize | (AT91C_BASE_LCDC->LCDC_FRMCFG & 0xFF000000);
}
//------------------------------------------------------------------------------
/// Sets the DMA controller burst length.
/// \param burstLength Desired burst length.
//------------------------------------------------------------------------------
void LCD_SetBurstLength(unsigned int burstLength)
{
ASSERT(((burstLength-1) & 0xFFFFFF80) == 0,
"LCD_SetBurstLength: Wrong burstLength value.\n\r");
AT91C_BASE_LCDC->LCDC_FRMCFG &= 0x00FFFFFF;
AT91C_BASE_LCDC->LCDC_FRMCFG |= ((burstLength-1) << 24);
AT91C_BASE_LCDC->LCDC_FIFO = 2048 - (2 * burstLength + 3);
}
//------------------------------------------------------------------------------
/// Sets the prescaler value of the contrast control PWM.
/// \param prescaler Desired prescaler value.
//------------------------------------------------------------------------------
void LCD_SetContrastPrescaler(unsigned int prescaler)
{
ASSERT((prescaler & ~AT91C_LCDC_PS) == 0,
"LCD_SetContrastPrescaler: Wrong prescaler value\n\r");
AT91C_BASE_LCDC->LCDC_CTRSTCON &= ~AT91C_LCDC_PS;
AT91C_BASE_LCDC->LCDC_CTRSTCON |= prescaler;
}
//------------------------------------------------------------------------------
/// Sets the polarity of the contrast PWM.
/// \param polarity PWM polarity
//------------------------------------------------------------------------------
void LCD_SetContrastPolarity(unsigned int polarity)
{
ASSERT((polarity & ~AT91C_LCDC_POL) == 0,
"LCD_SetContrastPolarity: Wrong polarity value\n\r");
AT91C_BASE_LCDC->LCDC_CTRSTCON &= ~AT91C_LCDC_POL;
AT91C_BASE_LCDC->LCDC_CTRSTCON |= polarity;
}
//------------------------------------------------------------------------------
/// Sets the threshold value of the constrast PWM.
/// \param value PWM threshold value.
//------------------------------------------------------------------------------
void LCD_SetContrastValue(unsigned int value)
{
ASSERT((value & ~AT91C_LCDC_CVAL) == 0,
"LCD_SetContrastValue: Wrong value.\n\r");
AT91C_BASE_LCDC->LCDC_CTRSTVAL = value;
}
//------------------------------------------------------------------------------
/// Enables the contrast PWM generator.
//------------------------------------------------------------------------------
void LCD_EnableContrast()
{
AT91C_BASE_LCDC->LCDC_CTRSTCON |= AT91C_LCDC_ENA_PWMGEMENABLED;
}
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/lcd/lcd.c | C | oos | 15,109 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef LCD_H
#define LCD_H
//------------------------------------------------------------------------------
// Exported functions
//------------------------------------------------------------------------------
extern void LCD_Enable(unsigned int frames);
extern void LCD_Disable(unsigned int frames);
extern void LCD_EnableDma();
extern void LCD_DisableDma();
extern void LCD_SetPixelClock(unsigned int masterClock, unsigned int pixelClock);
extern void LCD_SetDisplayType(unsigned int displayType);
extern void LCD_SetScanMode(unsigned int scanMode);
extern void LCD_SetBitsPerPixel(unsigned int bitsPerPixel);
extern void LCD_SetPolarities(
unsigned int lcdd,
unsigned int lcdvsync,
unsigned int lcdhsync,
unsigned int lcddotclk,
unsigned int lcdden);
extern void LCD_SetClockMode(unsigned int clockMode);
extern void LCD_SetMemoryFormat(unsigned int format);
extern void LCD_SetSize(unsigned int width, unsigned int height);
extern void LCD_SetVerticalTimings(
unsigned int vfp,
unsigned int vbp,
unsigned int vpw,
unsigned int vhdly);
extern void LCD_SetHorizontalTimings(
unsigned int hbp,
unsigned int hpw,
unsigned int hfp);
extern void LCD_SetFrameBufferAddress(void *address);
extern void LCD_SetFrameSize(unsigned int frameSize);
extern void LCD_SetBurstLength(unsigned int burstLength);
extern void LCD_SetContrastPrescaler(unsigned int prescaler);
extern void LCD_SetContrastPolarity(unsigned int polarity);
extern void LCD_SetContrastValue(unsigned int value);
extern void LCD_EnableContrast();
#endif //#ifndef LCD_H
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/lcd/lcd.h | C | oos | 3,247 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include "dbgu.h"
#include <stdarg.h>
#include <board.h>
//------------------------------------------------------------------------------
// Exported functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// Initializes the DBGU with the given parameters, and enables both the
/// transmitter and the receiver.
/// \param mode Operating mode to configure (see <Modes>).
/// \param baudrate Desired baudrate.
/// \param mck Frequency of the system master clock.
//------------------------------------------------------------------------------
void DBGU_Configure(unsigned int mode,
unsigned int baudrate,
unsigned int mck)
{
// Reset & disable receiver and transmitter, disable interrupts
AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RSTRX | AT91C_US_RSTTX;
AT91C_BASE_DBGU->DBGU_IDR = 0xFFFFFFFF;
// Configure baud rate
AT91C_BASE_DBGU->DBGU_BRGR = mck / (baudrate * 16);
// Configure mode register
AT91C_BASE_DBGU->DBGU_MR = mode;
// Disable DMA channel
AT91C_BASE_DBGU->DBGU_PTCR = AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS;
// Enable receiver and transmitter
AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RXEN | AT91C_US_TXEN;
}
//------------------------------------------------------------------------------
/// Outputs a character on the DBGU line.
/// \param c Character to send.
//------------------------------------------------------------------------------
static void DBGU_PutChar(unsigned char c)
{
// Wait for the transmitter to be ready
while ((AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_TXEMPTY) == 0);
// Send character
AT91C_BASE_DBGU->DBGU_THR = c;
// Wait for the transfer to complete
while ((AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_TXEMPTY) == 0);
}
//------------------------------------------------------------------------------
/// Reads and returns a character from the DBGU.
//------------------------------------------------------------------------------
unsigned char DBGU_GetChar()
{
while ((AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_RXRDY) == 0);
return AT91C_BASE_DBGU->DBGU_RHR;
}
#ifndef NOFPUT
#include <stdio.h>
//------------------------------------------------------------------------------
/// Implementation of fputc using the DBGU as the standard output. Required
/// for printf().
/// Returns the character written if successful, or -1 if the output stream is
/// not stdout or stderr.
/// \param c Character to write.
/// \param pStream Output stream.
//------------------------------------------------------------------------------
signed int fputc(signed int c, FILE *pStream)
{
if ((pStream == stdout) || (pStream == stderr)) {
DBGU_PutChar(c);
return c;
}
else {
return EOF;
}
}
//------------------------------------------------------------------------------
/// Implementation of fputs using the DBGU as the standard output. Required
/// for printf(). Does NOT currently use the PDC.
/// Returns the number of characters written if successful, or -1 if the output
/// stream is not stdout or stderr.
/// \param pStr String to write.
/// \param pStream Output stream.
//------------------------------------------------------------------------------
signed int fputs(const char *pStr, FILE *pStream)
{
signed int num = 0;
while (*pStr != 0) {
if (fputc(*pStr, pStream) == -1) {
return -1;
}
num++;
pStr++;
}
return num;
}
#undef putchar
//------------------------------------------------------------------------------
/// Outputs a character on the DBGU. Returns the character itself.
/// \param c Character to output.
//------------------------------------------------------------------------------
signed int putchar(signed int c)
{
return fputc(c, stdout);
}
#endif //#ifndef NOFPUT
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/dbgu/dbgu.c | C | oos | 5,898 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
/// \dir
/// !Purpose
///
/// This module provides definitions and functions for using the DBGU.
///
/// !Usage
///
/// -# Enable the DBGU pins (see pio.h).
/// -# Configure the DBGU using DBGU_Configure.
///
/// \note Unless specified, all the functions defined here operate synchronously;
/// i.e. they all wait the data is sent/received before returning.
//------------------------------------------------------------------------------
#ifndef DBGU_H
#define DBGU_H
//------------------------------------------------------------------------------
// Definitions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// \page Modes
/// This page lists several common operating modes for the DBGU.
/// !Modes
/// - DBGU_STANDARD
/// Standard operating mode (asynchronous, 8bit, no parity)
#define DBGU_STANDARD AT91C_US_PAR_NONE
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Exported functions
//------------------------------------------------------------------------------
extern void DBGU_Configure(unsigned int mode,
unsigned int baudrate,
unsigned int mck);
extern unsigned char DBGU_GetChar();
#endif //#ifndef DBGU_H
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/dbgu/dbgu.h | C | oos | 3,136 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef AC97C_H
#define AC97C_H
//------------------------------------------------------------------------------
// Constants
//------------------------------------------------------------------------------
/// The channel is already busy with a transfer.
#define AC97C_ERROR_BUSY 1
/// The transfer has been stopped by the user.
#define AC97C_ERROR_STOPPED 2
/// Codec channel index.
#define AC97C_CHANNEL_CODEC 0
/// Channel A index.
#define AC97C_CHANNEL_A 1
/// Channel B index.
#define AC97C_CHANNEL_B 2
/// Codec transmit/receive transfer index.
#define AC97C_CODEC_TRANSFER 0
/// Channel A receive transfer index.
#define AC97C_CHANNEL_A_RECEIVE 1
/// Channel A transmit transfer index.
#define AC97C_CHANNEL_A_TRANSMIT 2
/// Channel B receive transfer index.
#define AC97C_CHANNEL_B_RECEIVE 3
/// Channel B transmit transfer index.
#define AC97C_CHANNEL_B_TRANSMIT 4
//------------------------------------------------------------------------------
// Types
//------------------------------------------------------------------------------
/// AC97C transfer callback function.
typedef void (*Ac97Callback)(void *pArg,
unsigned char status,
unsigned int remaining);
//------------------------------------------------------------------------------
// Exported functions
//------------------------------------------------------------------------------
extern void AC97C_Configure();
extern void AC97C_ConfigureChannel(unsigned char channel, unsigned int cfg);
extern void AC97C_AssignInputSlots(unsigned char channel, unsigned int slots);
extern void AC97C_AssignOutputSlots(unsigned char channel, unsigned int slots);
extern unsigned char AC97C_Transfer(
unsigned char channel,
unsigned char *pBuffer,
unsigned int numSamples,
Ac97Callback callback,
void *pArg);
extern unsigned char AC97C_IsFinished(unsigned char channel);
extern void AC97C_WriteCodec(unsigned char address, unsigned short data);
extern unsigned short AC97C_ReadCodec(unsigned char address);
extern void AC97C_SetChannelSize(unsigned char channel, unsigned char size);
extern void AC97C_CancelTransfer(unsigned char channel);
#endif //#ifndef AC97C_H
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/ac97c/ac97c.h | C | oos | 3,961 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include "ac97c.h"
#include <board.h>
#include <aic/aic.h>
#include <utility/assert.h>
#include <utility/trace.h>
#include <utility/math.h>
//------------------------------------------------------------------------------
// Local constants
//------------------------------------------------------------------------------
/// Maximum size of one PDC buffer (in bytes).
#define MAX_PDC_COUNTER 65535
//------------------------------------------------------------------------------
// Local types
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// AC97 transfer descriptor. Tracks the status and parameters of a transfer
/// on the AC97 bus.
//------------------------------------------------------------------------------
typedef struct _Ac97Transfer {
/// Buffer containing the slots to send.
unsigned char *pBuffer;
/// Total number of samples to send.
volatile unsigned int numSamples;
/// Optional callback function.
Ac97Callback callback;
/// Optional argument to the callback function.
void *pArg;
} Ac97Transfer;
//------------------------------------------------------------------------------
/// AC97 controller driver structure. Monitors the status of transfers on all
/// AC97 channels.
//------------------------------------------------------------------------------
typedef struct _Ac97c {
/// List of transfers occuring on each channel.
Ac97Transfer transfers[5];
} Ac97c;
//------------------------------------------------------------------------------
// Local variables
//------------------------------------------------------------------------------
/// Global AC97 controller instance.
static Ac97c ac97c;
//------------------------------------------------------------------------------
// Local functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// Returns the size of one sample (in bytes) on the given channel.
/// \param channel Channel number.
//------------------------------------------------------------------------------
static unsigned char GetSampleSize(unsigned char channel)
{
unsigned int size = 0;
SANITY_CHECK((channel == AC97C_CHANNEL_A)
|| (channel == AC97C_CHANNEL_B)
|| (channel == AC97C_CHANNEL_CODEC));
// Check selected channel
switch (channel) {
case AC97C_CHANNEL_CODEC: return 2;
case AC97C_CHANNEL_A: size = (AT91C_BASE_AC97C->AC97C_CAMR & AT91C_AC97C_SIZE) >> 16; break;
case AC97C_CHANNEL_B: size = (AT91C_BASE_AC97C->AC97C_CBMR & AT91C_AC97C_SIZE) >> 16; break;
}
// Compute size in bytes given SIZE field
if ((size & 2) != 0) {
return 2;
}
else {
return 4;
}
}
//------------------------------------------------------------------------------
/// Interrupt service routine for Codec, is invoked by AC97C_Handler.
//------------------------------------------------------------------------------
static void CodecHandler(void)
{
unsigned int status;
unsigned int data;
Ac97Transfer *pTransfer = &(ac97c.transfers[AC97C_CODEC_TRANSFER]);
// Read CODEC status register
status = AT91C_BASE_AC97C->AC97C_COSR;
status &= AT91C_BASE_AC97C->AC97C_COMR;
// A sample has been transmitted
if (status & AT91C_AC97C_TXRDY) {
pTransfer->numSamples--;
// If there are remaining samples, transmit one
if (pTransfer->numSamples > 0) {
data = *((unsigned int *) pTransfer->pBuffer);
AT91C_BASE_AC97C->AC97C_COMR &= ~(AT91C_AC97C_TXRDY);
AT91C_BASE_AC97C->AC97C_COTHR = data;
// Check if transfer is read or write
if ((data & AT91C_AC97C_READ) != 0) {
AT91C_BASE_AC97C->AC97C_COMR |= AT91C_AC97C_RXRDY;
}
else {
pTransfer->pBuffer += sizeof(unsigned int);
AT91C_BASE_AC97C->AC97C_COMR |= AT91C_AC97C_TXRDY;
}
}
// Transfer finished
else {
AT91C_BASE_AC97C->AC97C_IDR = AT91C_AC97C_COEVT;
AT91C_BASE_AC97C->AC97C_COMR &= ~(AT91C_AC97C_TXRDY);
if (pTransfer->callback) {
pTransfer->callback(pTransfer->pArg, 0, 0);
}
}
}
// A sample has been received
if (status & AT91C_AC97C_RXRDY) {
// Store sample
data = AT91C_BASE_AC97C->AC97C_CORHR;
*((unsigned int *) pTransfer->pBuffer) = data;
pTransfer->pBuffer += sizeof(unsigned int);
pTransfer->numSamples--;
// Transfer finished
if (pTransfer->numSamples > 0) {
data = *((unsigned int *) pTransfer->pBuffer);
AT91C_BASE_AC97C->AC97C_COMR &= ~(AT91C_AC97C_RXRDY);
AT91C_BASE_AC97C->AC97C_COTHR = data;
// Check if transfer is read or write
if ((data & AT91C_AC97C_READ) != 0) {
AT91C_BASE_AC97C->AC97C_COMR |= AT91C_AC97C_RXRDY;
}
else {
pTransfer->pBuffer += sizeof(unsigned int);
AT91C_BASE_AC97C->AC97C_COMR |= AT91C_AC97C_TXRDY;
}
}
else {
AT91C_BASE_AC97C->AC97C_IDR = AT91C_AC97C_COEVT;
AT91C_BASE_AC97C->AC97C_COMR &= ~(AT91C_AC97C_RXRDY);
if (pTransfer->callback) {
pTransfer->callback(pTransfer->pArg, 0, 0);
}
}
}
}
//------------------------------------------------------------------------------
/// Interrupt service routine for channel A, is invoked by AC97C_Handler.
//------------------------------------------------------------------------------
static void ChannelAHandler(void)
{
unsigned int status;
Ac97Transfer *pTransmit = &(ac97c.transfers[AC97C_CHANNEL_A_TRANSMIT]);
Ac97Transfer *pReceive = &(ac97c.transfers[AC97C_CHANNEL_A_RECEIVE]);
// Read channel A status register
status = AT91C_BASE_AC97C->AC97C_CASR;
// A buffer has been transmitted
if ((status & AT91C_AC97C_ENDTX) != 0) {
// Update transfer information
if (pTransmit->numSamples > MAX_PDC_COUNTER) {
pTransmit->numSamples -= MAX_PDC_COUNTER;
}
else {
pTransmit->numSamples = 0;
}
// Transmit new buffers if necessary
if (pTransmit->numSamples > MAX_PDC_COUNTER) {
// Fill next PDC
AT91C_BASE_AC97C->AC97C_TNPR = (unsigned int) pTransmit->pBuffer;
if (pTransmit->numSamples > 2 * MAX_PDC_COUNTER) {
AT91C_BASE_AC97C->AC97C_TNCR = MAX_PDC_COUNTER;
pTransmit->pBuffer += MAX_PDC_COUNTER * GetSampleSize(AC97C_CHANNEL_A);
}
else {
AT91C_BASE_AC97C->AC97C_TNCR = pTransmit->numSamples - MAX_PDC_COUNTER;
}
}
// Only one buffer remaining
else {
AT91C_BASE_AC97C->AC97C_CAMR &= ~AT91C_AC97C_ENDTX;
AT91C_BASE_AC97C->AC97C_CAMR |= AT91C_AC97C_TXBUFE;
}
}
// Transmit completed
if ((status & AT91C_AC97C_TXBUFE) != 0) {
pTransmit->numSamples = 0;
AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_TXTDIS;
AT91C_BASE_AC97C->AC97C_CAMR &= ~AT91C_AC97C_TXBUFE;
if (pTransmit->callback) {
pTransmit->callback(pTransmit->pArg, 0, 0);
}
}
// A buffer has been received
if (status & AT91C_AC97C_ENDRX) {
if (pReceive->numSamples > MAX_PDC_COUNTER) {
pReceive->numSamples -= MAX_PDC_COUNTER;
}
else {
pReceive->numSamples = 0;
}
// Transfer remaining samples
if (pReceive->numSamples > MAX_PDC_COUNTER) {
AT91C_BASE_AC97C->AC97C_RNPR = (unsigned int) pReceive->pBuffer;
if (pReceive->numSamples > 2 * MAX_PDC_COUNTER) {
AT91C_BASE_AC97C->AC97C_RNCR = MAX_PDC_COUNTER;
pReceive->pBuffer += MAX_PDC_COUNTER * GetSampleSize(AC97C_CHANNEL_A);
}
else {
AT91C_BASE_AC97C->AC97C_RNCR = pReceive->numSamples - MAX_PDC_COUNTER;
}
}
// Only one buffer remaining
else {
AT91C_BASE_AC97C->AC97C_CAMR &= ~(AT91C_AC97C_ENDRX);
AT91C_BASE_AC97C->AC97C_CAMR |= AT91C_AC97C_RXBUFF;
}
}
// Receive complete
if ((status & AT91C_AC97C_RXBUFF) != 0) {
pReceive->numSamples = 0;
AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_RXTDIS;
AT91C_BASE_AC97C->AC97C_CAMR &= ~AT91C_AC97C_RXBUFF;
if (pReceive->callback) {
pReceive->callback(pReceive->pArg, 0, 0);
}
}
}
//------------------------------------------------------------------------------
// Exported functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// This handler function must be called by the AC97C interrupt service routine.
/// Identifies which event was activated and calls the associated function.
//------------------------------------------------------------------------------
void AC97C_Handler(void)
{
unsigned int status;
// Get the real interrupt source
status = AT91C_BASE_AC97C->AC97C_SR;
status &= AT91C_BASE_AC97C->AC97C_IMR;
// Check if an event on the codec channel is active
if ((status & AT91C_AC97C_COEVT) != 0) {
CodecHandler();
}
// Check if an event on channel A is active
if ((status & AT91C_AC97C_CAEVT) != 0) {
ChannelAHandler();
}
}
//------------------------------------------------------------------------------
/// Starts a read or write transfer on the given channel
/// \param channel particular channel (AC97C_CHANNEL_A or AC97C_CHANNEL_B).
/// \param pBuffer buffer containing the slots to send.
/// \param numSamples total number of samples to send.
/// \param callback optional callback function.
/// \param pArg optional argument to the callback function.
//------------------------------------------------------------------------------
unsigned char AC97C_Transfer(
unsigned char channel,
unsigned char *pBuffer,
unsigned int numSamples,
Ac97Callback callback,
void *pArg)
{
unsigned int size;
unsigned int data;
Ac97Transfer *pTransfer;
SANITY_CHECK(channel <= 5);
SANITY_CHECK(pBuffer);
SANITY_CHECK(numSamples > 0);
// Check that no transfer is pending on the channel
pTransfer = &(ac97c.transfers[channel]);
if (pTransfer->numSamples > 0) {
trace_LOG(trace_WARNING, "-W- AC97C_Transfer: Channel %d is busy\n\r", channel);
return AC97C_ERROR_BUSY;
}
// Fill transfer information
pTransfer->pBuffer = pBuffer;
pTransfer->numSamples = numSamples;
pTransfer->callback = callback;
pTransfer->pArg = pArg;
// Transmit or receive over codec channel
if (channel == AC97C_CODEC_TRANSFER) {
// Send command
data = *((unsigned int *) pTransfer->pBuffer);
AT91C_BASE_AC97C->AC97C_COTHR = data;
// Check if transfer is read or write
if ((data & AT91C_AC97C_READ) != 0) {
AT91C_BASE_AC97C->AC97C_COMR |= AT91C_AC97C_RXRDY;
}
else {
pTransfer->pBuffer += sizeof(unsigned int);
AT91C_BASE_AC97C->AC97C_COMR |= AT91C_AC97C_TXRDY;
}
// Enable interrupts
AT91C_BASE_AC97C->AC97C_IER |= AT91C_AC97C_COEVT;
}
// Transmit over channel A
else if (channel == AC97C_CHANNEL_A_TRANSMIT) {
// Disable PDC
AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_TXTDIS;
// Fill PDC buffers
size = min(pTransfer->numSamples, MAX_PDC_COUNTER);
AT91C_BASE_AC97C->AC97C_TPR = (unsigned int) pTransfer->pBuffer;
AT91C_BASE_AC97C->AC97C_TCR = size;
pTransfer->pBuffer += size * GetSampleSize(AC97C_CHANNEL_A);
size = min(pTransfer->numSamples - size, MAX_PDC_COUNTER);
if (size > 0) {
AT91C_BASE_AC97C->AC97C_TNPR = (unsigned int) pTransfer->pBuffer;
AT91C_BASE_AC97C->AC97C_TNCR = size;
pTransfer->pBuffer += size * GetSampleSize(AC97C_CHANNEL_A);
}
// Enable interrupts
AT91C_BASE_AC97C->AC97C_CAMR |= AT91C_AC97C_PDCEN | AT91C_AC97C_ENDTX;
AT91C_BASE_AC97C->AC97C_IER |= AT91C_AC97C_CAEVT;
// Start transfer
AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_TXTEN;
}
// Receive over channel A
else if (channel == AC97C_CHANNEL_A_RECEIVE) {
// Disable PDC
AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_RXTDIS;
// Fill PDC buffers
size = min(pTransfer->numSamples, MAX_PDC_COUNTER);
AT91C_BASE_AC97C->AC97C_RPR = (unsigned int) pTransfer->pBuffer;
AT91C_BASE_AC97C->AC97C_RCR = size;
pTransfer->pBuffer += size * GetSampleSize(AC97C_CHANNEL_A);
size = min(pTransfer->numSamples - size, MAX_PDC_COUNTER);
if (size > 0) {
AT91C_BASE_AC97C->AC97C_RNPR = (unsigned int) pTransfer->pBuffer;
AT91C_BASE_AC97C->AC97C_RNCR = size;
pTransfer->pBuffer += size * GetSampleSize(AC97C_CHANNEL_A);
}
// Enable interrupts
AT91C_BASE_AC97C->AC97C_CAMR |= AT91C_AC97C_PDCEN | AT91C_AC97C_ENDRX;
AT91C_BASE_AC97C->AC97C_IER |= AT91C_AC97C_CAEVT;
// Start transfer
AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_RXTEN;
}
return 0;
}
//------------------------------------------------------------------------------
/// Stop read or write transfer on the given channel.
/// \param channel Channel number.
//------------------------------------------------------------------------------
void AC97C_CancelTransfer(unsigned char channel)
{
unsigned int size = 0;
Ac97Transfer *pTransfer;
SANITY_CHECK(channel <= AC97C_CHANNEL_B_TRANSMIT);
// Save remaining size
pTransfer = &(ac97c.transfers[channel]);
size = pTransfer->numSamples;
pTransfer->numSamples = 0;
// Stop PDC
if (channel == AC97C_CHANNEL_A_TRANSMIT) {
AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_TXTDIS;
size -= min(size, MAX_PDC_COUNTER) - AT91C_BASE_AC97C->AC97C_TCR;
}
if (channel == AC97C_CHANNEL_A_RECEIVE) {
AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_RXTDIS;
size -= min(size, MAX_PDC_COUNTER) - AT91C_BASE_AC97C->AC97C_RCR;
}
// Invoke callback if provided
if (pTransfer->callback) {
pTransfer->callback(pTransfer->pArg, AC97C_ERROR_STOPPED, size);
}
}
//------------------------------------------------------------------------------
/// Initializes the AC97 controller.
//------------------------------------------------------------------------------
void AC97C_Configure(void)
{
unsigned char channel;
// Enable the AC97 controller peripheral clock
AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_AC97C);
// Enable the peripheral and variable rate adjustment
AT91C_BASE_AC97C->AC97C_MR = AT91C_AC97C_ENA | AT91C_AC97C_VRA;
// Unassigns all input & output slots
AC97C_AssignInputSlots(0, 0xFFFF);
AC97C_AssignOutputSlots(0, 0xFFFF);
// Install the AC97C interrupt handler
AT91C_BASE_AC97C->AC97C_IDR = 0xFFFFFFFF;
AIC_ConfigureIT(AT91C_ID_AC97C, 0, AC97C_Handler);
AIC_EnableIT(AT91C_ID_AC97C);
// Disable PDC transfers
AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_TXTDIS | AT91C_PDC_RXTDIS;
// Clear channel transfers
for (channel = 0; channel < AC97C_CHANNEL_B_TRANSMIT; channel++) {
ac97c.transfers[channel].numSamples = 0;
}
}
//------------------------------------------------------------------------------
/// Configures the desired channel with the given value.
/// \param channel Channel number.
/// \param cfg Configuration value.
//------------------------------------------------------------------------------
void AC97C_ConfigureChannel(unsigned char channel, unsigned int cfg)
{
SANITY_CHECK((channel == AC97C_CHANNEL_A) || (channel == AC97C_CHANNEL_B));
if (channel == AC97C_CHANNEL_A) {
AT91C_BASE_AC97C->AC97C_CAMR = cfg;
}
else {
AT91C_BASE_AC97C->AC97C_CBMR = cfg;
}
}
//------------------------------------------------------------------------------
/// Assigns the desired input slots to a particular channel.
/// \param channel Channel number (or 0 to unassign slots).
/// \param slots Bitfield value of slots to assign.
//------------------------------------------------------------------------------
void AC97C_AssignInputSlots(unsigned char channel, unsigned int slots)
{
unsigned int value;
unsigned int i;
SANITY_CHECK(channel <= AC97C_CHANNEL_B);
// Assign all slots
slots >>= 3;
for (i = 3; i < 15; i++) {
// Check if slots is selected
if (slots & 1) {
value = AT91C_BASE_AC97C->AC97C_ICA;
value &= ~(0x07 << ((i - 3) * 3));
value |= channel << ((i - 3) * 3);
AT91C_BASE_AC97C->AC97C_ICA = value;
}
slots >>= 1;
}
}
//------------------------------------------------------------------------------
/// Assigns the desired output slots to a particular channel.
/// \param channel Channel number (or 0 to unassign slots).
/// \param slots Bitfield value of slots to assign.
//------------------------------------------------------------------------------
void AC97C_AssignOutputSlots(unsigned char channel, unsigned int slots)
{
unsigned int value;
unsigned int i;
SANITY_CHECK(channel <= AC97C_CHANNEL_B);
// Assign all slots
slots >>= 3;
for (i = 3; i < 15; i++) {
// Check if slots is selected
if (slots & 1) {
value = AT91C_BASE_AC97C->AC97C_OCA;
value &= ~(0x07 << ((i - 3) * 3));
value |= channel << ((i - 3) * 3);
AT91C_BASE_AC97C->AC97C_OCA = value;
}
slots >>= 1;
}
}
//------------------------------------------------------------------------------
/// Returns 1 if no transfer is currently pending on the given channel;
/// otherwise, returns 0.
/// \param channel Channel number.
//------------------------------------------------------------------------------
unsigned char AC97C_IsFinished(unsigned char channel)
{
SANITY_CHECK(channel <= AC97C_CHANNEL_B_TRANSMIT);
if (ac97c.transfers[channel].numSamples > 0) {
return 0;
}
else {
return 1;
}
}
//------------------------------------------------------------------------------
/// Convenience function for synchronously sending commands to the codec.
/// \param address Register address.
/// \param data Command data.
//------------------------------------------------------------------------------
void AC97C_WriteCodec(unsigned char address, unsigned short data)
{
unsigned int sample;
sample = (address << 16) | data;
AC97C_Transfer(AC97C_CODEC_TRANSFER, (unsigned char *) &sample, 1, 0, 0);
while (!AC97C_IsFinished(AC97C_CODEC_TRANSFER));
}
//------------------------------------------------------------------------------
/// Convenience function for receiving data from the AC97 codec.
/// \param address Register address.
//------------------------------------------------------------------------------
unsigned short AC97C_ReadCodec(unsigned char address)
{
unsigned int sample;
sample = AT91C_AC97C_READ | (address << 16);
AC97C_Transfer(AC97C_CODEC_TRANSFER, (unsigned char *) &sample, 1, 0, 0);
while (!AC97C_IsFinished(AC97C_CODEC_TRANSFER));
return sample;
}
//------------------------------------------------------------------------------
/// Sets the size in bits of one sample on the given channel.
/// \param channel Channel number.
/// \param size Size of one sample in bits (10, 16, 18 or 24).
//------------------------------------------------------------------------------
void AC97C_SetChannelSize(unsigned char channel, unsigned char size)
{
unsigned int bits = 0;
SANITY_CHECK((size == 10) || (size == 16) || (size == 18) || (size == 24));
SANITY_CHECK((channel == AC97C_CHANNEL_A) || (channel == AC97C_CHANNEL_B));
switch (size) {
case 10 : bits = AT91C_AC97C_SIZE_10_BITS; break;
case 16 : bits = AT91C_AC97C_SIZE_16_BITS; break;
case 18 : bits = AT91C_AC97C_SIZE_18_BITS; break;
case 20 : bits = AT91C_AC97C_SIZE_20_BITS; break;
}
if (channel == AC97C_CHANNEL_A) {
AT91C_BASE_AC97C->AC97C_CAMR &= ~(AT91C_AC97C_SIZE);
AT91C_BASE_AC97C->AC97C_CAMR |= bits;
}
else {
AT91C_BASE_AC97C->AC97C_CBMR &= ~(AT91C_AC97C_SIZE);
AT91C_BASE_AC97C->AC97C_CBMR |= bits;
}
}
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/ac97c/ac97c.c | C | oos | 23,492 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
/// \dir
/// !Purpose
///
/// Definitions for SPI peripheral usage.
///
/// !Usage
///
/// -# Enable the SPI pins required by the application (see pio.h).
/// -# Configure the SPI using the SPI_Configure function. This enables the
/// peripheral clock. The mode register is loaded with the given value.
/// -# Configure all the necessary chip selects with SPI_ConfigureNPCS.
/// -# Enable the SPI by calling SPI_Enable.
/// -# Send/receive data using SPI_Write and SPI_Read. Note that SPI_Read
/// must be called after SPI_Write to retrieve the last value read.
/// -# Send/receive data using the PDC with the SPI_WriteBuffer and
/// SPI_ReadBuffer functions.
/// -# Disable the SPI by calling SPI_Disable.
//------------------------------------------------------------------------------
#ifndef SPI_H
#define SPI_H
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include <board.h>
//------------------------------------------------------------------------------
// Definitions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// \page "SPI configuration macros"
/// This page lists several macros which should be used when configuring a SPI
/// peripheral.
///
/// !Macros
/// - SPI_PCS
/// - SPI_SCBR
/// - SPI_DLYBS
/// - SPI_DLYBCT
/// Calculate the PCS field value given the chip select NPCS value
#define SPI_PCS(npcs) ((~(1 << npcs) & 0xF) << 16)
/// Calculates the value of the CSR SCBR field given the baudrate and MCK.
#define SPI_SCBR(baudrate, masterClock) \
((unsigned int) (masterClock / baudrate) << 8)
/// Calculates the value of the CSR DLYBS field given the desired delay (in ns)
#define SPI_DLYBS(delay, masterClock) \
((unsigned int) (((masterClock / 1000000) * delay) / 1000) << 16)
/// Calculates the value of the CSR DLYBCT field given the desired delay (in ns)
#define SPI_DLYBCT(delay, masterClock) \
((unsigned int) (((masterClock / 1000000) * delay) / 32000) << 16)
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Exported functions
//------------------------------------------------------------------------------
extern void SPI_Enable(AT91S_SPI *spi);
extern void SPI_Disable(AT91S_SPI *spi);
extern void SPI_Configure(AT91S_SPI *spi,
unsigned int id,
unsigned int configuration);
extern void SPI_ConfigureNPCS(AT91S_SPI *spi,
unsigned int npcs,
unsigned int configuration);
extern void SPI_Write(AT91S_SPI *spi, unsigned int npcs, unsigned short data);
extern unsigned char SPI_WriteBuffer(AT91S_SPI *spi,
void *buffer,
unsigned int length);
extern unsigned char SPI_IsFinished(AT91S_SPI *pSpi);
extern unsigned short SPI_Read(AT91S_SPI *spi);
extern unsigned char SPI_ReadBuffer(AT91S_SPI *spi,
void *buffer,
unsigned int length);
#endif //#ifndef SPI_H
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/spi/spi.h | C | oos | 5,184 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include "spi.h"
//------------------------------------------------------------------------------
// Exported functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// Enables a SPI peripheral
/// \param spi Pointer to an AT91S_SPI instance.
//------------------------------------------------------------------------------
void SPI_Enable(AT91S_SPI *spi)
{
spi->SPI_CR = AT91C_SPI_SPIEN;
}
//------------------------------------------------------------------------------
/// Disables a SPI peripheral.
/// \param spi Pointer to an AT91S_SPI instance.
//------------------------------------------------------------------------------
void SPI_Disable(AT91S_SPI *spi)
{
spi->SPI_CR = AT91C_SPI_SPIDIS;
}
//------------------------------------------------------------------------------
/// Configures a SPI peripheral as specified. The configuration can be computed
/// using several macros (see "SPI configuration macros") and the constants
/// defined in LibV3 (AT91C_SPI_*).
/// \param spi Pointer to an AT91S_SPI instance.
/// \param id Peripheral ID of the SPI.
/// \param configuration Value of the SPI configuration register.
//------------------------------------------------------------------------------
void SPI_Configure(AT91S_SPI *spi,
unsigned int id,
unsigned int configuration)
{
AT91C_BASE_PMC->PMC_PCER = 1 << id;
spi->SPI_CR = AT91C_SPI_SPIDIS | AT91C_SPI_SWRST;
spi->SPI_MR = configuration;
}
//------------------------------------------------------------------------------
/// Configures a chip select of a SPI peripheral. The chip select configuration
/// is computed using the definition provided by the LibV3 (AT91C_SPI_*).
/// \param spi Pointer to an AT91S_SPI instance.
/// \param npcs Chip select to configure (1, 2, 3 or 4).
/// \param configuration Desired chip select configuration.
//------------------------------------------------------------------------------
void SPI_ConfigureNPCS(AT91S_SPI *spi,
unsigned int npcs,
unsigned int configuration)
{
spi->SPI_CSR[npcs] = configuration;
}
//------------------------------------------------------------------------------
/// Sends data through a SPI peripheral. If the SPI is configured to use a fixed
/// peripheral select, the npcs value is meaningless. Otherwise, it identifies
/// the component which shall be addressed.
/// \param spi Pointer to an AT91S_SPI instance.
/// \param npcs Chip select of the component to address (1, 2, 3 or 4).
/// \param data Word of data to send.
//------------------------------------------------------------------------------
void SPI_Write(AT91S_SPI *spi, unsigned int npcs, unsigned short data)
{
// Discard contents of RDR register
//volatile unsigned int discard = spi->SPI_RDR;
// Send data
while ((spi->SPI_SR & AT91C_SPI_TXEMPTY) == 0);
spi->SPI_TDR = data | SPI_PCS(npcs);
while ((spi->SPI_SR & AT91C_SPI_TDRE) == 0);
}
//------------------------------------------------------------------------------
/// Sends the contents of buffer through a SPI peripheral, using the PDC to
/// take care of the transfer.
/// \param spi Pointer to an AT91S_SPI instance.
/// \param buffer Data buffer to send.
/// \param length Length of the data buffer.
//------------------------------------------------------------------------------
unsigned char SPI_WriteBuffer(AT91S_SPI *spi,
void *buffer,
unsigned int length)
{
// Check if first bank is free
if (spi->SPI_TCR == 0) {
spi->SPI_TPR = (unsigned int) buffer;
spi->SPI_TCR = length;
spi->SPI_PTCR = AT91C_PDC_TXTEN;
return 1;
}
// Check if second bank is free
else if (spi->SPI_TNCR == 0) {
spi->SPI_TNPR = (unsigned int) buffer;
spi->SPI_TNCR = length;
return 1;
}
// No free banks
return 0;
}
//------------------------------------------------------------------------------
/// Returns 1 if there is no pending write operation on the SPI; otherwise
/// returns 0.
/// \param pSpi Pointer to an AT91S_SPI instance.
//------------------------------------------------------------------------------
unsigned char SPI_IsFinished(AT91S_SPI *pSpi)
{
return ((pSpi->SPI_SR & AT91C_SPI_TXEMPTY) != 0);
}
//------------------------------------------------------------------------------
/// Reads and returns the last word of data received by a SPI peripheral. This
/// method must be called after a successful SPI_Write call.
/// \param spi Pointer to an AT91S_SPI instance.
//------------------------------------------------------------------------------
unsigned short SPI_Read(AT91S_SPI *spi)
{
while ((spi->SPI_SR & AT91C_SPI_RDRF) == 0);
return spi->SPI_RDR & 0xFFFF;
}
//------------------------------------------------------------------------------
/// Reads data from a SPI peripheral until the provided buffer is filled. This
/// method does NOT need to be called after SPI_Write or SPI_WriteBuffer.
/// \param spi Pointer to an AT91S_SPI instance.
/// \param buffer Data buffer to store incoming bytes.
/// \param length Length in bytes of the data buffer.
//------------------------------------------------------------------------------
unsigned char SPI_ReadBuffer(AT91S_SPI *spi,
void *buffer,
unsigned int length)
{
// Check if the first bank is free
if (spi->SPI_RCR == 0) {
spi->SPI_RPR = (unsigned int) buffer;
spi->SPI_RCR = length;
spi->SPI_PTCR = AT91C_PDC_RXTEN;
return 1;
}
// Check if second bank is free
else if (spi->SPI_RNCR == 0) {
spi->SPI_RNPR = (unsigned int) buffer;
spi->SPI_RNCR = length;
return 1;
}
// No free bank
return 0;
}
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/spi/spi.c | C | oos | 7,992 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
// peripherals/emac/emac.h
#ifndef EMAC_H
#define EMAC_H
//-----------------------------------------------------------------------------
/// \dir
/// !Purpose
///
/// Definition of methods and structures for using EMAC
///
/// !Usage
///
/// -# Initialize EMAC with EMAC_Init.
/// -# Setup EMAC with EMAC_SetupTx, EMAC_SetupRx, EMAC_SetupMacAddress
/// and EMAC_SetupStack.
/// -# Drive the EMAC status machine by EMAC_Task.
/// -# EMAC_GetStatus give EMAC status machine current status
/// -# Send a packet to network with EMAC_SendPacket.
/// -# Get a packet from network with EMAC_GetPacket.
///
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Headers
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Definitions
//-----------------------------------------------------------------------------
/// Number of buffer for RX, be carreful: MUST be 2^n
#define RX_BUFFERS 16
/// Number of buffer for TX, be carreful: MUST be 2^n
#define TX_BUFFERS 8
/// Buffer Size
#define EMAC_RX_UNITSIZE 128 /// Fixed size for RX buffer
#define EMAC_TX_UNITSIZE 1518 /// Size for ETH frame length
// The MAC can support frame lengths up to 1536 bytes.
#define EMAC_FRAME_LENTGH_MAX 1536
//-----------------------------------------------------------------------------
// Types
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
/// Describes the statistics of the EMAC.
//-----------------------------------------------------------------------------
typedef struct _EmacStats {
// TX errors
unsigned int tx_packets; /// Total Number of packets sent
unsigned int tx_comp; /// Packet complete
unsigned int tx_errors; /// TX errors ( Retry Limit Exceed )
unsigned int collisions; /// Collision
unsigned int tx_exausts; /// Buffer exhausted
unsigned int tx_underruns; /// Under Run, not able to read from memory
// RX errors
unsigned int rx_packets; /// Total Number of packets RX
unsigned int rx_eof; /// No EOF error
unsigned int rx_ovrs; /// Over Run, not able to store to memory
unsigned int rx_bnas; /// Buffer is not available
} EmacStats, *PEmacStats;
//-----------------------------------------------------------------------------
// PHY Exported functions
//-----------------------------------------------------------------------------
extern unsigned char EMAC_SetMdcClock( unsigned int mck );
extern void EMAC_EnableMdio( void );
extern void EMAC_DisableMdio( void );
extern void EMAC_EnableMII( void );
extern void EMAC_EnableRMII( void );
extern unsigned char EMAC_ReadPhy(unsigned char PhyAddress,
unsigned char Address,
unsigned int *pValue,
unsigned int retry);
extern unsigned char EMAC_WritePhy(unsigned char PhyAddress,
unsigned char Address,
unsigned int Value,
unsigned int retry);
extern void EMAC_SetLinkSpeed(unsigned char speed,
unsigned char fullduplex);
//-----------------------------------------------------------------------------
// EMAC Exported functions
//-----------------------------------------------------------------------------
/// Callback used by send function
typedef void (*EMAC_TxCallback)(unsigned int status);
typedef void (*EMAC_RxCallback)(unsigned int status);
typedef void (*EMAC_WakeupCallback)(void);
extern void EMAC_Init( unsigned char id, const unsigned char *pMacAddress,
unsigned char enableCAF, unsigned char enableNBC );
#define EMAC_CAF_DISABLE 0
#define EMAC_CAF_ENABLE 1
#define EMAC_NBC_DISABLE 0
#define EMAC_NBC_ENABLE 1
extern void EMAC_Handler(void);
extern unsigned char EMAC_Send(void *pBuffer,
unsigned int size,
EMAC_TxCallback fEMAC_TxCallback);
/// Return for EMAC_Send function
#define EMAC_TX_OK 0
#define EMAC_TX_BUFFER_BUSY 1
#define EMAC_TX_INVALID_PACKET 2
extern unsigned char EMAC_Poll(unsigned char *pFrame,
unsigned int frameSize,
unsigned int *pRcvSize);
/// Return for EMAC_Poll function
#define EMAC_RX_OK 0
#define EMAC_RX_NO_DATA 1
#define EMAC_RX_FRAME_SIZE_TOO_SMALL 2
extern void EMAC_GetStatistics(EmacStats *pStats, unsigned char reset);
#endif // #ifndef EMAC_H
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/emac/emac.h | C | oos | 6,643 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//-----------------------------------------------------------------------------
// Headers
//-----------------------------------------------------------------------------
#include <board.h>
#include "emac.h"
#include <utility/trace.h>
#include <utility/assert.h>
#include <string.h>
//------------------------------------------------------------------------------
// Definitions
//------------------------------------------------------------------------------
/// The buffer addresses written into the descriptors must be aligned so the
/// last few bits are zero. These bits have special meaning for the EMAC
/// peripheral and cannot be used as part of the address.
#define EMAC_ADDRESS_MASK ((unsigned int)0xFFFFFFFC)
#define EMAC_LENGTH_FRAME ((unsigned int)0x0FFF) /// Length of frame mask
// receive buffer descriptor bits
#define EMAC_RX_OWNERSHIP_BIT (1UL << 0)
#define EMAC_RX_WRAP_BIT (1UL << 1)
#define EMAC_RX_SOF_BIT (1UL << 14)
#define EMAC_RX_EOF_BIT (1UL << 15)
// Transmit buffer descriptor bits
#define EMAC_TX_LAST_BUFFER_BIT (1UL << 15)
#define EMAC_TX_WRAP_BIT (1UL << 30)
#define EMAC_TX_USED_BIT (1UL << 31)
//-----------------------------------------------------------------------------
// Circular buffer management
//-----------------------------------------------------------------------------
// Return count in buffer
#define CIRC_CNT(head,tail,size) (((head) - (tail)) & ((size)-1))
// Return space available, 0..size-1
// We always leave one free char as a completely full buffer
// has head == tail, which is the same as empty
#define CIRC_SPACE(head,tail,size) CIRC_CNT((tail),((head)+1),(size))
// Return count up to the end of the buffer.
// Carefully avoid accessing head and tail more than once,
// so they can change underneath us without returning inconsistent results
#define CIRC_CNT_TO_END(head,tail,size) \
({int end = (size) - (tail); \
int n = ((head) + end) & ((size)-1); \
n < end ? n : end;})
// Return space available up to the end of the buffer
#define CIRC_SPACE_TO_END(head,tail,size) \
({int end = (size) - 1 - (head); \
int n = (end + (tail)) & ((size)-1); \
n <= end ? n : end+1;})
// Increment head or tail
#define CIRC_INC(headortail,size) \
headortail++; \
if(headortail >= size) { \
headortail = 0; \
}
#define CIRC_EMPTY(circ) ((circ)->head == (circ)->tail)
#define CIRC_CLEAR(circ) ((circ)->head = (circ)->tail = 0)
//------------------------------------------------------------------------------
// Structures
//------------------------------------------------------------------------------
#ifdef __ICCARM__ // IAR
#pragma pack(4) // IAR
#define __attribute__(...) // IAR
#endif // IAR
/// Describes the type and attribute of Receive Transfer descriptor.
typedef struct _EmacRxTDescriptor {
unsigned int addr;
unsigned int status;
} __attribute__((packed, aligned(8))) EmacRxTDescriptor, *PEmacRxTDescriptor;
/// Describes the type and attribute of Transmit Transfer descriptor.
typedef struct _EmacTxTDescriptor {
unsigned int addr;
unsigned int status;
} __attribute__((packed, aligned(8))) EmacTxTDescriptor, *PEmacTxTDescriptor;
#ifdef __ICCARM__ // IAR
#pragma pack() // IAR
#endif // IAR
/// Descriptors for RX (required aligned by 8)
typedef struct {
volatile EmacRxTDescriptor td[RX_BUFFERS];
EMAC_RxCallback rxCb; /// Callback function to be invoked once a frame has been received
unsigned short idx;
} RxTd;
/// Descriptors for TX (required aligned by 8)
typedef struct {
volatile EmacTxTDescriptor td[TX_BUFFERS];
EMAC_TxCallback txCb[TX_BUFFERS]; /// Callback function to be invoked once TD has been processed
EMAC_WakeupCallback wakeupCb; /// Callback function to be invoked once several TD have been released
unsigned short wakeupThreshold; /// Number of free TD before wakeupCb is invoked
unsigned short head; /// Circular buffer head pointer incremented by the upper layer (buffer to be sent)
unsigned short tail; /// Circular buffer head pointer incremented by the IT handler (buffer sent)
} TxTd;
//------------------------------------------------------------------------------
// Internal variables
//------------------------------------------------------------------------------
// Receive Transfer Descriptor buffer
#ifdef __ICCARM__ // IAR
#pragma data_alignment=8 // IAR
#endif // IAR
static volatile RxTd rxTd;
// Transmit Transfer Descriptor buffer
#ifdef __ICCARM__ // IAR
#pragma data_alignment=8 // IAR
#endif // IAR
static volatile TxTd txTd;
/// Send Buffer
// Section 3.6 of AMBA 2.0 spec states that burst should not cross 1K Boundaries.
// Receive buffer manager writes are burst of 2 words => 3 lsb bits of the address shall be set to 0
#ifdef __ICCARM__ // IAR
#pragma data_alignment=8 // IAR
#endif // IAR
static volatile unsigned char pTxBuffer[TX_BUFFERS * EMAC_TX_UNITSIZE] __attribute__((aligned(8)));
#ifdef __ICCARM__ // IAR
#pragma data_alignment=8 // IAR
#endif // IAR
/// Receive Buffer
static volatile unsigned char pRxBuffer[RX_BUFFERS * EMAC_RX_UNITSIZE] __attribute__((aligned(8)));
/// Statistics
static volatile EmacStats EmacStatistics;
//-----------------------------------------------------------------------------
// Internal functions
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
/// Wait PHY operation complete.
/// Return 1 if the operation completed successfully.
/// May be need to re-implemented to reduce CPU load.
/// \param retry: the retry times, 0 to wait forever until complete.
//-----------------------------------------------------------------------------
static unsigned char EMAC_WaitPhy( unsigned int retry )
{
unsigned int retry_count = 0;
while((AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE) == 0) {
// Dead LOOP!
if (retry == 0) {
continue;
}
// Timeout check
retry_count++;
if(retry_count >= retry) {
trace_LOG(trace_ERROR, "E: Wait PHY time out\n\r");
return 0;
}
}
return 1;
}
//-----------------------------------------------------------------------------
// Exported functions
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// PHY management functions
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
/// Set MDC clock according to current board clock. Per 802.3, MDC should be
/// less then 2.5MHz.
/// Return 1 if successfully, 0 if MDC clock not found.
//-----------------------------------------------------------------------------
unsigned char EMAC_SetMdcClock( unsigned int mck )
{
int clock_dividor;
if (mck <= 20000000) {
clock_dividor = AT91C_EMAC_CLK_HCLK_8; /// MDC clock = MCK/8
}
else if (mck <= 40000000) {
clock_dividor = AT91C_EMAC_CLK_HCLK_16; /// MDC clock = MCK/16
}
else if (mck <= 80000000) {
clock_dividor = AT91C_EMAC_CLK_HCLK_32; /// MDC clock = MCK/32
}
else if (mck <= 160000000) {
clock_dividor = AT91C_EMAC_CLK_HCLK_64; /// MDC clock = MCK/64
}
else {
trace_LOG(trace_ERROR, "E: No valid MDC clock.\n\r");
return 0;
}
AT91C_BASE_EMAC->EMAC_NCFGR = (AT91C_BASE_EMAC->EMAC_NCFGR & (~AT91C_EMAC_CLK))
| clock_dividor;
return 1;
}
//-----------------------------------------------------------------------------
/// Enable MDI with PHY
//-----------------------------------------------------------------------------
void EMAC_EnableMdio( void )
{
AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
}
//-----------------------------------------------------------------------------
/// Enable MDI with PHY
//-----------------------------------------------------------------------------
void EMAC_DisableMdio( void )
{
AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
}
//-----------------------------------------------------------------------------
/// Enable MII mode for EMAC, called once after autonegotiate
//-----------------------------------------------------------------------------
void EMAC_EnableMII( void )
{
AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN;
}
//-----------------------------------------------------------------------------
/// Enable RMII mode for EMAC, called once after autonegotiate
//-----------------------------------------------------------------------------
void EMAC_EnableRMII( void )
{
AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN | AT91C_EMAC_RMII;
}
//-----------------------------------------------------------------------------
/// Read PHY register.
/// Return 1 if successfully, 0 if timeout.
/// \param PhyAddress PHY Address
/// \param Address Register Address
/// \param pValue Pointer to a 32 bit location to store read data
/// \param retry The retry times, 0 to wait forever until complete.
//-----------------------------------------------------------------------------
unsigned char EMAC_ReadPhy(unsigned char PhyAddress,
unsigned char Address,
unsigned int *pValue,
unsigned int retry)
{
AT91C_BASE_EMAC->EMAC_MAN = (AT91C_EMAC_SOF & (0x01 << 30))
| (AT91C_EMAC_CODE & (2 << 16))
| (AT91C_EMAC_RW & (2 << 28))
| (AT91C_EMAC_PHYA & ((PhyAddress & 0x1f) << 23))
| (AT91C_EMAC_REGA & (Address << 18));
if ( EMAC_WaitPhy(retry) == 0 ) {
trace_LOG(trace_ERROR, "TimeOut EMAC_ReadPhy\n\r");
return 0;
}
*pValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff );
return 1;
}
//-----------------------------------------------------------------------------
/// Write PHY register
/// Return 1 if successfully, 0 if timeout.
/// \param PhyAddress PHY Address
/// \param Address Register Address
/// \param Value Data to write ( Actually 16 bit data )
/// \param retry The retry times, 0 to wait forever until complete.
//-----------------------------------------------------------------------------
unsigned char EMAC_WritePhy(unsigned char PhyAddress,
unsigned char Address,
unsigned int Value,
unsigned int retry)
{
AT91C_BASE_EMAC->EMAC_MAN = (AT91C_EMAC_SOF & (0x01 << 30))
| (AT91C_EMAC_CODE & (2 << 16))
| (AT91C_EMAC_RW & (1 << 28))
| (AT91C_EMAC_PHYA & ((PhyAddress & 0x1f) << 23))
| (AT91C_EMAC_REGA & (Address << 18))
| (AT91C_EMAC_DATA & Value) ;
if ( EMAC_WaitPhy(retry) == 0 ) {
trace_LOG(trace_ERROR, "TimeOut EMAC_WritePhy\n\r");
return 0;
}
return 1;
}
//-----------------------------------------------------------------------------
/// Setup the EMAC for the link : speed 100M/10M and Full/Half duplex
/// \param speed Link speed, 0 for 10M, 1 for 100M
/// \param fullduplex 1 for Full Duplex mode
//-----------------------------------------------------------------------------
void EMAC_SetLinkSpeed(unsigned char speed, unsigned char fullduplex)
{
unsigned int ncfgr;
ncfgr = AT91C_BASE_EMAC->EMAC_NCFGR;
ncfgr &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
if (speed) {
ncfgr |= AT91C_EMAC_SPD;
}
if (fullduplex) {
ncfgr |= AT91C_EMAC_FD;
}
AT91C_BASE_EMAC->EMAC_NCFGR = ncfgr;
}
//-----------------------------------------------------------------------------
// EMAC functions
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
/// EMAC Interrupt handler
//-----------------------------------------------------------------------------
void EMAC_Handler(void)
{
volatile EmacTxTDescriptor *pTxTd;
volatile EMAC_TxCallback *pTxCb;
unsigned int isr;
unsigned int rsr;
unsigned int tsr;
unsigned int rxStatusFlag;
unsigned int txStatusFlag;
//trace_LOG(trace_DEBUG, "EMAC_Handler\n\r");
isr = AT91C_BASE_EMAC->EMAC_ISR & AT91C_BASE_EMAC->EMAC_IMR;
rsr = AT91C_BASE_EMAC->EMAC_RSR;
tsr = AT91C_BASE_EMAC->EMAC_TSR;
// RX packet
if ((isr & AT91C_EMAC_RCOMP) || (rsr & AT91C_EMAC_REC)) {
rxStatusFlag = AT91C_EMAC_REC;
// Frame received
EmacStatistics.rx_packets++;
// Check OVR
if (rsr & AT91C_EMAC_OVR) {
rxStatusFlag |= AT91C_EMAC_OVR;
EmacStatistics.rx_ovrs++;
}
// Check BNA
if (rsr & AT91C_EMAC_BNA) {
rxStatusFlag |= AT91C_EMAC_BNA;
EmacStatistics.rx_bnas++;
}
// Clear status
AT91C_BASE_EMAC->EMAC_RSR |= rxStatusFlag;
// Invoke callbacks
if (rxTd.rxCb) {
rxTd.rxCb(rxStatusFlag);
}
}
// TX packet
if ((isr & AT91C_EMAC_TCOMP) || (tsr & AT91C_EMAC_COMP)) {
txStatusFlag = AT91C_EMAC_COMP;
EmacStatistics.tx_comp ++;
// A frame transmitted
// Check RLE
if (tsr & AT91C_EMAC_RLES) {
txStatusFlag |= AT91C_EMAC_RLES;
EmacStatistics.tx_errors++;
}
// Check COL
if (tsr & AT91C_EMAC_COL) {
txStatusFlag |= AT91C_EMAC_COL;
EmacStatistics.collisions++;
}
// Check BEX
if (tsr & AT91C_EMAC_BEX) {
txStatusFlag |= AT91C_EMAC_BEX;
EmacStatistics.tx_exausts++;
}
// Check UND
if (tsr & AT91C_EMAC_UND) {
txStatusFlag |= AT91C_EMAC_UND;
EmacStatistics.tx_underruns++;
}
// Clear status
AT91C_BASE_EMAC->EMAC_TSR |= txStatusFlag;
// Sanity check: Tx buffers have to be scheduled
ASSERT(!CIRC_EMPTY(&txTd),
"-F- EMAC Tx interrupt received meanwhile no TX buffers has been scheduled\n\r");
// Check the buffers
while (CIRC_CNT(txTd.head, txTd.tail, TX_BUFFERS)) {
pTxTd = txTd.td + txTd.tail;
pTxCb = txTd.txCb + txTd.tail;
// Exit if buffer has not been sent yet
if ((pTxTd->status & EMAC_TX_USED_BIT) == 0) {
break;
}
// Notify upper layer that packet has been sent
if (*pTxCb) {
(*pTxCb)(txStatusFlag);
}
CIRC_INC( txTd.tail, TX_BUFFERS );
}
// If a wakeup has been scheduled, notify upper layer that it can send
// other packets, send will be successfull.
if( (CIRC_SPACE(txTd.head, txTd.tail, TX_BUFFERS) >= txTd.wakeupThreshold)
&& txTd.wakeupCb) {
txTd.wakeupCb();
}
}
}
//-----------------------------------------------------------------------------
/// Initialize the EMAC with the emac controller address
/// \param id HW ID for power management
/// \param pTxWakeUpfct Thresold TX Wakeup Callback
/// \param pRxfct RX Wakeup Callback
/// \param pMacAddress Mac Address
/// \param enableCAF enable AT91C_EMAC_CAF if needed by application
/// \param enableNBC AT91C_EMAC_NBC if needed by application
//-----------------------------------------------------------------------------
void EMAC_Init( unsigned char id, const unsigned char *pMacAddress,
unsigned char enableCAF, unsigned char enableNBC )
{
int Index;
unsigned int Address;
// Check parameters
ASSERT(RX_BUFFERS * EMAC_RX_UNITSIZE > EMAC_FRAME_LENTGH_MAX,
"E: RX buffers too small\n\r");
trace_LOG(trace_DEBUG, "EMAC_Init\n\r");
// Power ON
AT91C_BASE_PMC->PMC_PCER = 1 << id;
// Disable TX & RX and more
AT91C_BASE_EMAC->EMAC_NCR = 0;
// disable
AT91C_BASE_EMAC->EMAC_IDR = ~0;
rxTd.idx = 0;
CIRC_CLEAR(&txTd);
// Setup the RX descriptors.
for(Index = 0; Index < RX_BUFFERS; Index++) {
Address = (unsigned int)(&(pRxBuffer[Index * EMAC_RX_UNITSIZE]));
// Remove EMAC_RX_OWNERSHIP_BIT and EMAC_RX_WRAP_BIT
rxTd.td[Index].addr = Address & EMAC_ADDRESS_MASK;
rxTd.td[Index].status = 0;
}
rxTd.td[RX_BUFFERS - 1].addr |= EMAC_RX_WRAP_BIT;
// Setup the TX descriptors.
for(Index = 0; Index < TX_BUFFERS; Index++) {
Address = (unsigned int)(&(pTxBuffer[Index * EMAC_TX_UNITSIZE]));
txTd.td[Index].addr = Address;
txTd.td[Index].status = EMAC_TX_USED_BIT;
}
txTd.td[TX_BUFFERS - 1].status = EMAC_TX_USED_BIT | EMAC_TX_WRAP_BIT;
// Set the MAC address
if( pMacAddress != (unsigned char *)0 ) {
AT91C_BASE_EMAC->EMAC_SA1L = ( ((unsigned int)pMacAddress[3] << 24)
| ((unsigned int)pMacAddress[2] << 16)
| ((unsigned int)pMacAddress[1] << 8 )
| pMacAddress[0] );
AT91C_BASE_EMAC->EMAC_SA1H = ( ((unsigned int)pMacAddress[5] << 8 )
| pMacAddress[4] );
}
// Now setup the descriptors
// Receive Buffer Queue Pointer Register
AT91C_BASE_EMAC->EMAC_RBQP = (unsigned int) (rxTd.td);
// Transmit Buffer Queue Pointer Register
AT91C_BASE_EMAC->EMAC_TBQP = (unsigned int) (txTd.td);
AT91C_BASE_EMAC->EMAC_NCR = AT91C_EMAC_CLRSTAT;
// Clear all status bits in the receive status register.
AT91C_BASE_EMAC->EMAC_RSR = (AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);
// Clear all status bits in the transmit status register
AT91C_BASE_EMAC->EMAC_TSR = ( AT91C_EMAC_UBR | AT91C_EMAC_COL | AT91C_EMAC_RLES
| AT91C_EMAC_BEX | AT91C_EMAC_COMP
| AT91C_EMAC_UND );
// Clear interrupts
AT91C_BASE_EMAC->EMAC_ISR;
// Enable the copy of data into the buffers
// ignore broadcasts, and don't copy FCS.
AT91C_BASE_EMAC->EMAC_NCFGR |= (AT91C_EMAC_DRFCS | AT91C_EMAC_PAE);
if( enableCAF == EMAC_CAF_ENABLE ) {
AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_CAF;
}
if( enableNBC == EMAC_NBC_ENABLE ) {
AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_NBC;
}
// Enable Rx and Tx, plus the stats register.
AT91C_BASE_EMAC->EMAC_NCR |= (AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT);
// Setup the interrupts for TX (and errors)
AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RXUBR
| AT91C_EMAC_TUNDR
| AT91C_EMAC_RLEX
| AT91C_EMAC_TXERR
| AT91C_EMAC_TCOMP
| AT91C_EMAC_ROVR
| AT91C_EMAC_HRESP;
}
//-----------------------------------------------------------------------------
/// Get the statstic information & reset it
/// \param pStats Pointer to EmacStats structure to copy the informations
/// \param reset Reset the statistics after copy it
//-----------------------------------------------------------------------------
void EMAC_GetStatistics(EmacStats *pStats, unsigned char reset)
{
unsigned int ncrBackup = 0;
trace_LOG(trace_DEBUG, "EMAC_GetStatistics\n\r");
// Sanity check
if (pStats == (EmacStats *) 0) {
return;
}
ncrBackup = AT91C_BASE_EMAC->EMAC_NCR & (AT91C_EMAC_TE | AT91C_EMAC_RE);
// Disable TX/RX
AT91C_BASE_EMAC->EMAC_NCR = ncrBackup & ~(AT91C_EMAC_TE | AT91C_EMAC_RE);
// Copy the informations
memcpy(pStats, (void*)&EmacStatistics, sizeof(EmacStats));
// Reset the statistics
if (reset) {
memset((void*)&EmacStatistics, 0x00, sizeof(EmacStats));
AT91C_BASE_EMAC->EMAC_NCR = ncrBackup | AT91C_EMAC_CLRSTAT;
}
// restore NCR
AT91C_BASE_EMAC->EMAC_NCR = ncrBackup;
}
//-----------------------------------------------------------------------------
/// Send a packet with EMAC.
/// If the packet size is larger than transfer buffer size error returned.
/// \param buffer The buffer to be send
/// \param size The size of buffer to be send
/// \param fEMAC_TxCallback Threshold Wakeup callback
/// \param fWakeUpCb TX Wakeup
/// \return OK, Busy or invalid packet
//-----------------------------------------------------------------------------
unsigned char EMAC_Send(void *pBuffer,
unsigned int size,
EMAC_TxCallback fEMAC_TxCallback)
{
volatile EmacTxTDescriptor *pTxTd;
volatile EMAC_TxCallback *pTxCb;
//trace_LOG(trace_DEBUG, "EMAC_Send\n\r");
// Check parameter
if (size > EMAC_TX_UNITSIZE) {
trace_LOG(trace_ERROR, "-E- EMAC driver does not split send packets.");
trace_LOG(trace_ERROR, " It can send %d bytes max in one packet (%u bytes requested)\n\r",
EMAC_TX_UNITSIZE, size);
return EMAC_TX_INVALID_PACKET;
}
// If no free TxTd, buffer can't be sent, schedule the wakeup callback
if( CIRC_SPACE(txTd.head, txTd.tail, TX_BUFFERS) == 0) {
return EMAC_TX_BUFFER_BUSY;
}
// Pointers to the current TxTd
pTxTd = txTd.td + txTd.head;
pTxCb = txTd.txCb + txTd.head;
// Sanity check
ASSERT((pTxTd->status & EMAC_TX_USED_BIT) != 0,
"-F- Buffer is still under EMAC control\n\r");
// Setup/Copy data to transmition buffer
if (pBuffer && size) {
// Driver manage the ring buffer
memcpy((void *)pTxTd->addr, pBuffer, size);
}
// Tx Callback
*pTxCb = fEMAC_TxCallback;
// Update TD status
// The buffer size defined is length of ethernet frame
// so it's always the last buffer of the frame.
if (txTd.head == TX_BUFFERS-1) {
pTxTd->status =
(size & EMAC_LENGTH_FRAME) | EMAC_TX_LAST_BUFFER_BIT | EMAC_TX_WRAP_BIT;
}
else {
pTxTd->status = (size & EMAC_LENGTH_FRAME) | EMAC_TX_LAST_BUFFER_BIT;
}
CIRC_INC(txTd.head, TX_BUFFERS)
// Tx packets count
EmacStatistics.tx_packets++;
// Now start to transmit if it is not already done
AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
return EMAC_TX_OK;
}
//-----------------------------------------------------------------------------
/// Receive a packet with EMAC
/// If not enough buffer for the packet, the remaining data is lost but right
/// frame length is returned.
/// \param pFrame Buffer to store the frame
/// \param frameSize Size of the frame
/// \param pRcvSize Received size
/// \return OK, no data, or frame too small
//-----------------------------------------------------------------------------
unsigned char EMAC_Poll(unsigned char *pFrame,
unsigned int frameSize,
unsigned int *pRcvSize)
{
unsigned short bufferLength;
unsigned int tmpFrameSize=0;
unsigned char *pTmpFrame=0;
unsigned int tmpIdx = rxTd.idx;
volatile EmacRxTDescriptor *pRxTd = rxTd.td + rxTd.idx;
ASSERT(pFrame, "F: EMAC_Poll\n\r");
char isFrame = 0;
// Set the default return value
*pRcvSize = 0;
// Process received RxTd
while ((pRxTd->addr & EMAC_RX_OWNERSHIP_BIT) == EMAC_RX_OWNERSHIP_BIT) {
// A start of frame has been received, discard previous fragments
if ((pRxTd->status & EMAC_RX_SOF_BIT) == EMAC_RX_SOF_BIT) {
// Skip previous fragment
while (tmpIdx != rxTd.idx) {
pRxTd = rxTd.td + rxTd.idx;
pRxTd->addr &= ~(EMAC_RX_OWNERSHIP_BIT);
CIRC_INC(rxTd.idx, RX_BUFFERS);
}
// Reset the temporary frame pointer
pTmpFrame = pFrame;
tmpFrameSize = 0;
// Start to gather buffers in a frame
isFrame = 1;
}
// Increment the pointer
CIRC_INC(tmpIdx, RX_BUFFERS);
// Copy data in the frame buffer
if (isFrame) {
if (tmpIdx == rxTd.idx) {
trace_LOG(trace_INFO,
"I: no EOF (Invalid of buffers too small)\n\r");
do {
pRxTd = rxTd.td + rxTd.idx;
pRxTd->addr &= ~(EMAC_RX_OWNERSHIP_BIT);
CIRC_INC(rxTd.idx, RX_BUFFERS);
} while(tmpIdx != rxTd.idx);
return EMAC_RX_NO_DATA;
}
// Copy the buffer into the application frame
bufferLength = EMAC_RX_UNITSIZE;
if ((tmpFrameSize + bufferLength) > frameSize) {
bufferLength = frameSize - tmpFrameSize;
}
memcpy(pTmpFrame, (void*)(pRxTd->addr & EMAC_ADDRESS_MASK), bufferLength);
pTmpFrame += bufferLength;
tmpFrameSize += bufferLength;
// An end of frame has been received, return the data
if ((pRxTd->status & EMAC_RX_EOF_BIT) == EMAC_RX_EOF_BIT) {
// Frame size from the EMAC
*pRcvSize = (pRxTd->status & EMAC_LENGTH_FRAME);
// Application frame buffer is too small all data have not been copied
if (tmpFrameSize < *pRcvSize) {
printf("size req %u size allocated %u\n\r", *pRcvSize, frameSize);
return EMAC_RX_FRAME_SIZE_TOO_SMALL;
}
trace_LOG(trace_INFO, "packet %d-%u (%u)\n\r", rxTd.idx, tmpIdx, *pRcvSize);
// All data have been copied in the application frame buffer => release TD
while (rxTd.idx != tmpIdx) {
pRxTd = rxTd.td + rxTd.idx;
pRxTd->addr &= ~(EMAC_RX_OWNERSHIP_BIT);
CIRC_INC(rxTd.idx, RX_BUFFERS);
}
EmacStatistics.rx_packets++;
return EMAC_RX_OK;
}
}
// SOF has not been detected, skip the fragment
else {
pRxTd->addr &= ~(EMAC_RX_OWNERSHIP_BIT);
rxTd.idx = tmpIdx;
}
// Process the next buffer
pRxTd = rxTd.td + tmpIdx;
}
//trace_LOG(trace_DEBUG, "E");
return EMAC_RX_NO_DATA;
}
//-----------------------------------------------------------------------------
/// Registers pRxCb callback. Callback will be invoked after the next received
/// frame.
/// When EMAC_Poll() returns EMAC_RX_NO_DATA the application task call EMAC_Set_RxCb()
/// to register pRxCb() callback and enters suspend state. The callback is in charge
/// to resume the task once a new frame has been received. The next time EMAC_Poll()
/// is called, it will be successfull.
/// \param pRxCb Pointer to callback function
//-----------------------------------------------------------------------------
void EMAC_Set_RxCb(EMAC_RxCallback pRxCb)
{
rxTd.rxCb = pRxCb;
AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP;
}
//-----------------------------------------------------------------------------
/// Remove the RX callback function.
/// This function is usually invoked from the RX callback itself. Once the callback
/// has resumed the application task, there is no need to invoke the callback again.
//-----------------------------------------------------------------------------
void EMAC_Clear_RxCb(void)
{
AT91C_BASE_EMAC->EMAC_IDR = AT91C_EMAC_RCOMP;
rxTd.rxCb = (EMAC_RxCallback) 0;
}
//-----------------------------------------------------------------------------
/// Registers TX wakeup callback callback. Callback will be invoked once several
/// transfer descriptors are available.
/// When EMAC_Send() returns EMAC_TX_BUFFER_BUSY (all TD busy) the application
/// task calls EMAC_Set_TxWakeUpCb() to register pTxWakeUpCb() callback and
/// enters suspend state. The callback is in charge to resume the task once
/// several TD have been released. The next time EMAC_Send() will be called, it
/// shall be successfull.
/// \param pTxWakeUpCb Pointer to callback function
/// \param threshold Minimum number of available transfer descriptors before pTxWakeUpCb() is invoked
/// \return 0= success, 1 = threshold exceeds nuber of transfer descriptors
//-----------------------------------------------------------------------------
char EMAC_Set_TxWakeUpCb(EMAC_WakeupCallback pTxWakeUpCb, unsigned short threshold)
{
if (threshold <= TX_BUFFERS) {
txTd.wakeupCb = pTxWakeUpCb;
txTd.wakeupThreshold = threshold;
return 0;
}
return 1;
}
//-----------------------------------------------------------------------------
/// Remove the TX wakeup callback function.
/// This function is usually invoked from the TX wakeup callback itself. Once the callback
/// has resumed the application task, there is no need to invoke the callback again.
//-----------------------------------------------------------------------------
void EMAC_Clear_TxWakeUpCb(void)
{
txTd.wakeupCb = (EMAC_WakeupCallback) 0;
}
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/emac/emac.c | C | oos | 32,096 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include <board.h>
#include <pio/pio.h>
#include <utility/trace.h>
#include <aic/aic.h>
#include "can.h"
//------------------------------------------------------------------------------
// Local definitions
//------------------------------------------------------------------------------
// CAN state
#define CAN_DISABLED 0
#define CAN_HALTED 1
#define CAN_IDLE 2
#define CAN_SENDING 3
#define CAN_RECEIVING 4
// MOT: Mailbox Object Type
#define CAN_MOT_DISABLE 0 // Mailbox is disabled
#define CAN_MOT_RECEPT 1 // Reception Mailbox
#define CAN_MOT_RECEPT_OW 2 // Reception mailbox with overwrite
#define CAN_MOT_TRANSMIT 3 // Transmit mailbox
#define CAN_MOT_CONSUMER 4 // Consumer mailbox
#define CAN_MOT_PRODUCER 5 // Producer mailbox
//------------------------------------------------------------------------------
// Local variables
//------------------------------------------------------------------------------
#if defined (PINS_CAN_TRANSCEIVER_TXD)
static const Pin pins_can_transceiver_txd[] = {PINS_CAN_TRANSCEIVER_TXD};
#endif
#if defined (PINS_CAN_TRANSCEIVER_RXD)
static const Pin pins_can_transceiver_rxd[] = {PINS_CAN_TRANSCEIVER_RXD};
#endif
static const Pin pin_can_transceiver_rs = PIN_CAN_TRANSCEIVER_RS;
#if defined (PIN_CAN_TRANSCEIVER_RXEN)
static const Pin pin_can_transceiver_rxen = PIN_CAN_TRANSCEIVER_RXEN;
#endif
static CanTransfer *pCAN0Transfer=NULL;
#ifdef AT91C_BASE_CAN1
static CanTransfer *pCAN1Transfer=NULL;
#endif
//------------------------------------------------------------------------------
// Local functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// CAN Error Detection
/// \param status error type
/// \param can_number can nulber
//------------------------------------------------------------------------------
static void CAN_ErrorHandling( unsigned int status, unsigned char can_number)
{
if( (status&AT91C_CAN_ERRA) == AT91C_CAN_ERRA) {
trace_LOG( trace_ERROR, "-E- (CAN) CAN is in active Error Active mode\n\r");
}
else if( (status&AT91C_CAN_ERRP) == AT91C_CAN_ERRP) {
trace_LOG( trace_ERROR, "-E- (CAN) CAN is in Error Passive mode\n\r");
}
else if( (status&AT91C_CAN_BOFF) == AT91C_CAN_BOFF) {
trace_LOG( trace_ERROR, "-E- (CAN) CAN is in Buff Off mode\n\r");
// CAN reset
trace_LOG( trace_ERROR, "-E- (CAN) CAN%d reset\n\r", can_number);
// CAN Controller Disable
if (can_number == 0) {
AT91C_BASE_CAN0->CAN_MR &= ~AT91C_CAN_CANEN;
// CAN Controller Enable
AT91C_BASE_CAN0->CAN_MR |= AT91C_CAN_CANEN;
}
#ifdef AT91C_BASE_CAN1
else if (can_number == 1) {
AT91C_BASE_CAN1->CAN_MR &= ~AT91C_CAN_CANEN;
// CAN Controller Enable
AT91C_BASE_CAN1->CAN_MR |= AT91C_CAN_CANEN;
}
#endif
}
// Error for Frame dataframe
// CRC error
if( (status&AT91C_CAN_CERR) == AT91C_CAN_CERR) {
trace_LOG( trace_ERROR, "-E- (CAN) CRC Error\n\r");
}
// Bit-stuffing error
else if( (status&AT91C_CAN_SERR) == AT91C_CAN_SERR) {
trace_LOG( trace_ERROR, "-E- (CAN) Stuffing Error\n\r");
}
// Bit error
else if( (status&AT91C_CAN_BERR) == AT91C_CAN_BERR) {
trace_LOG( trace_ERROR, "-E- (CAN) Bit Error\n\r");
}
// Form error
else if( (status&AT91C_CAN_FERR) == AT91C_CAN_FERR) {
trace_LOG( trace_ERROR, "-E- (CAN) Form Error\n\r");
}
// Acknowledgment error
else if( (status&AT91C_CAN_AERR) == AT91C_CAN_AERR) {
trace_LOG( trace_ERROR, "-E- (CAN) Acknowledgment Error\n\r");
}
// Error interrupt handler
// Represent the current status of the CAN bus and are not latched.
// See CAN, par. Error Interrupt Handler
// AT91C_CAN_WARN
// AT91C_CAN_ERRA
}
//------------------------------------------------------------------------------
// Generic CAN Interrupt handler
/// \param can_number can nulber
//------------------------------------------------------------------------------
static void CAN_Handler( unsigned char can_number )
{
AT91PS_CAN base_can;
AT91PS_CAN_MB CAN_Mailbox;
unsigned int status;
unsigned int can_msr;
unsigned int* pCan_mcr;
unsigned int message_mode;
unsigned char numMailbox;
unsigned char state0;
unsigned char state1;
if( can_number == 0 ) {
base_can = AT91C_BASE_CAN0;
CAN_Mailbox = AT91C_BASE_CAN0_MB0;
state0 = pCAN0Transfer->state;
}
#ifdef AT91C_BASE_CAN1
else {
base_can = AT91C_BASE_CAN1;
CAN_Mailbox = AT91C_BASE_CAN1_MB0;
state1 = pCAN1Transfer->state;
}
#endif
status = (base_can->CAN_SR) & (base_can->CAN_IMR);
base_can->CAN_IDR = status;
trace_LOG( trace_DEBUG, "CAN0 status=0x%X\n\r", status);
if(status & AT91C_CAN_WAKEUP) {
if( can_number == 0 ) {
pCAN0Transfer->test_can = AT91C_TEST_OK;
pCAN0Transfer->state = CAN_IDLE;
}
#ifdef AT91C_BASE_CAN1
else {
pCAN1Transfer->test_can = AT91C_TEST_OK;
pCAN1Transfer->state = CAN_IDLE;
}
#endif
}
// Mailbox event ?
else if ((status&0x0000FFFF) != 0) {
trace_LOG( trace_DEBUG, "Mailbox event\n\r");
// Handle Mailbox interrupts
for (numMailbox = 0; numMailbox < NUM_MAILBOX_MAX; numMailbox++) {
can_msr = *(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x10+(0x20*numMailbox)));
if ((AT91C_CAN_MRDY & can_msr) == AT91C_CAN_MRDY) {
// Mailbox object type
message_mode = ((*(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x00+(0x20*numMailbox))))>>24)&0x7;
trace_LOG( trace_DEBUG, "message_mode 0x%X\n\r", message_mode);
trace_LOG( trace_DEBUG, "numMailbox 0x%X\n\r", numMailbox);
if( message_mode == 0 ) {
trace_LOG( trace_ERROR, "-E-Error in MOT\n\r");
}
else if( ( message_mode == CAN_MOT_RECEPT )
|| ( message_mode == CAN_MOT_RECEPT_OW )
|| ( message_mode == CAN_MOT_PRODUCER ) ) {
trace_LOG( trace_DEBUG, "Mailbox is in RECEPTION\n\r");
trace_LOG( trace_DEBUG, "Length 0x%X\n\r", (can_msr>>16)&0xF);
trace_LOG( trace_DEBUG, "CAN_MB_MID 0x%X\n\r", ((*(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x08+(0x20*numMailbox)))&AT91C_CAN_MIDvA)>>18));
trace_LOG( trace_DEBUG, "can_number %d\n\r", can_number);
if( can_number == 0 ) {
//CAN_MB_MDLx
pCAN0Transfer->data_low_reg =
(*(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x14+(0x20*numMailbox))));
//CAN_MB_MDHx
pCAN0Transfer->data_high_reg =
(*(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x18+(0x20*numMailbox))));
pCAN0Transfer->size = (can_msr>>16)&0xF;
pCAN0Transfer->mailbox_number = numMailbox;
state0 = CAN_IDLE;
}
#ifdef AT91C_BASE_CAN1
else {
//CAN_MB_MDLx
pCAN1Transfer->data_low_reg =
(*(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x14+(0x20*numMailbox))));
//CAN_MB_MDHx
pCAN1Transfer->data_high_reg =
(*(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x18+(0x20*numMailbox))));
pCAN1Transfer->size = (can_msr>>16)&0xF;
pCAN1Transfer->mailbox_number = numMailbox;
state1 = CAN_IDLE;
}
#endif
// Message Data has been received
pCan_mcr = (unsigned int*)((unsigned int)CAN_Mailbox+0x1C+(0x20*numMailbox));
*pCan_mcr = AT91C_CAN_MTCR;
}
else {
trace_LOG( trace_DEBUG, "Mailbox is in TRANSMIT\n\r");
trace_LOG( trace_DEBUG, "Length 0x%X\n\r", (can_msr>>16)&0xF);
trace_LOG( trace_DEBUG, "can_number %d\n\r", can_number);
if( can_number == 0 ) {
state0 = CAN_IDLE;
}
else {
state1 = CAN_IDLE;
}
}
}
}
if( can_number == 0 ) {
pCAN0Transfer->state = state0;
}
#ifdef AT91C_BASE_CAN1
else {
pCAN1Transfer->state = state1;
}
#endif
}
if ((status&0xFFCF0000) != 0) {
CAN_ErrorHandling(status, 0);
}
}
//------------------------------------------------------------------------------
/// CAN 0 Interrupt handler
//------------------------------------------------------------------------------
static void CAN0_Handler(void)
{
CAN_Handler( 0 );
}
//------------------------------------------------------------------------------
/// CAN 1 Interrupt handler
//------------------------------------------------------------------------------
#if defined AT91C_BASE_CAN1
static void CAN1_Handler(void)
{
CAN_Handler( 1 );
}
#endif
//------------------------------------------------------------------------------
// Global functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// Configure the corresponding mailbox
/// \param pTransfer can transfer structure
//------------------------------------------------------------------------------
void CAN_InitMailboxRegisters( CanTransfer *pTransfer )
{
AT91PS_CAN base_can;
AT91PS_CAN_MB CAN_Mailbox;
if( pTransfer->can_number == 0 ) {
base_can = AT91C_BASE_CAN0;
CAN_Mailbox = AT91C_BASE_CAN0_MB0;
}
#ifdef AT91C_BASE_CAN1
else {
base_can = AT91C_BASE_CAN1;
CAN_Mailbox = AT91C_BASE_CAN1_MB0;
}
#endif
CAN_Mailbox = (AT91PS_CAN_MB)((unsigned int)CAN_Mailbox+(unsigned int)(0x20*pTransfer->mailbox_number));
pTransfer->mailbox_in_use |= 1<<(pTransfer->mailbox_number);
// MailBox Control Register
CAN_Mailbox->CAN_MB_MCR = 0x0;
// MailBox Mode Register
CAN_Mailbox->CAN_MB_MMR = 0x00;
// CAN Message Acceptance Mask Register
CAN_Mailbox->CAN_MB_MAM = pTransfer->acceptance_mask_reg;
// MailBox ID Register
// Disable the mailbox before writing to CAN_MIDx registers
if( pTransfer->identifier != 0 ) {
CAN_Mailbox->CAN_MB_MAM |= AT91C_CAN_MIDE;
CAN_Mailbox->CAN_MB_MID = pTransfer->identifier;
}
else {
CAN_Mailbox->CAN_MB_MAM &= ~AT91C_CAN_MIDE;
}
// MailBox Mode Register
CAN_Mailbox->CAN_MB_MMR = pTransfer->mode_reg;
// MailBox Data Low Register
CAN_Mailbox->CAN_MB_MDL = pTransfer->data_low_reg;
// MailBox Data High Register
CAN_Mailbox->CAN_MB_MDH = pTransfer->data_high_reg;
// MailBox Control Register
CAN_Mailbox->CAN_MB_MCR = pTransfer->control_reg;
}
//------------------------------------------------------------------------------
/// Reset the MBx
//------------------------------------------------------------------------------
void CAN_ResetAllMailbox( void )
{
unsigned char i;
#if defined (AT91C_BASE_CAN0_MB0)
CAN_ResetTransfer( pCAN0Transfer );
for( i=0; i<8; i++ ) {
pCAN0Transfer->can_number = 0;
pCAN0Transfer->mailbox_number = i;
pCAN0Transfer->mode_reg = AT91C_CAN_MOT_DIS;
pCAN0Transfer->acceptance_mask_reg = 0;
pCAN0Transfer->identifier = 0;
pCAN0Transfer->data_low_reg = 0x00000000;
pCAN0Transfer->data_high_reg = 0x00000000;
pCAN0Transfer->control_reg = 0x00000000;
CAN_InitMailboxRegisters( pCAN0Transfer );
}
#endif
#if defined (AT91C_BASE_CAN0_MB8)
for( i=0; i<8; i++ ) {
pCAN0Transfer->can_number = 0;
pCAN0Transfer->mailbox_number = i+8;
pCAN0Transfer->mode_reg = AT91C_CAN_MOT_DIS;
pCAN0Transfer->acceptance_mask_reg = 0;
pCAN0Transfer->identifier = 0;
pCAN0Transfer->data_low_reg = 0x00000000;
pCAN0Transfer->data_high_reg = 0x00000000;
pCAN0Transfer->control_reg = 0x00000000;
CAN_InitMailboxRegisters( pCAN0Transfer );
}
#endif
#if defined (AT91C_BASE_CAN1_MB0)
if( pCAN1Transfer != NULL ) {
CAN_ResetTransfer( pCAN1Transfer );
for( i=0; i<8; i++ ) {
pCAN1Transfer->can_number = 1;
pCAN1Transfer->mailbox_number = i;
pCAN1Transfer->mode_reg = AT91C_CAN_MOT_DIS;
pCAN1Transfer->acceptance_mask_reg = 0;
pCAN1Transfer->identifier = 0;
pCAN1Transfer->data_low_reg = 0x00000000;
pCAN1Transfer->data_high_reg = 0x00000000;
pCAN1Transfer->control_reg = 0x00000000;
CAN_InitMailboxRegisters( pCAN1Transfer );
}
}
#endif
#if defined (AT91C_BASE_CAN1_MB8)
if( pCAN1Transfer != NULL ) {
for( i=0; i<8; i++ ) {
pCAN1Transfer->can_number = 1;
pCAN1Transfer->mailbox_number = i+8;
pCAN1Transfer->mode_reg = AT91C_CAN_MOT_DIS;
pCAN1Transfer->acceptance_mask_reg = 0;
pCAN1Transfer->identifier = 0;
pCAN1Transfer->data_low_reg = 0x00000000;
pCAN1Transfer->data_high_reg = 0x00000000;
pCAN1Transfer->control_reg = 0x00000000;
CAN_InitMailboxRegisters( pCAN1Transfer );
}
}
#endif
}
//------------------------------------------------------------------------------
/// CAN reset Transfer descriptor
/// \param pTransfer can transfer structure
//------------------------------------------------------------------------------
void CAN_ResetTransfer( CanTransfer *pTransfer )
{
pTransfer->state = CAN_IDLE;
pTransfer->can_number = 0;
pTransfer->mailbox_number = 0;
pTransfer->test_can = 0;
pTransfer->mode_reg = 0;
pTransfer->acceptance_mask_reg = 0;
pTransfer->identifier = 0;
pTransfer->data_low_reg = 0;
pTransfer->data_high_reg = 0;
pTransfer->control_reg = 0;
pTransfer->mailbox_in_use = 0;
pTransfer->size = 0;
}
//------------------------------------------------------------------------------
/// Wait for CAN synchronisation
/// \return return 1 for good initialisation, otherwise return 0
//------------------------------------------------------------------------------
static unsigned char CAN_Synchronisation( void )
{
unsigned int tick=0;
trace_LOG( trace_INFO, "CAN_Synchronisation\n\r");
pCAN0Transfer->test_can = AT91C_TEST_NOK;
#ifdef AT91C_BASE_CAN1
if( pCAN1Transfer != NULL ) {
pCAN1Transfer->test_can = AT91C_TEST_NOK;
}
#endif
// Enable CAN and Wait for WakeUp Interrupt
AT91C_BASE_CAN0->CAN_IER = AT91C_CAN_WAKEUP;
// CAN Controller Enable
AT91C_BASE_CAN0->CAN_MR = AT91C_CAN_CANEN;
// Enable Autobaud/Listen mode
// dangerous, CAN not answer in this mode
while( (pCAN0Transfer->test_can != AT91C_TEST_OK)
&& (tick < AT91C_CAN_TIMEOUT) ) {
tick++;
}
if (tick == AT91C_CAN_TIMEOUT) {
trace_LOG( trace_ERROR, "-E- CAN0 Initialisations FAILED\n\r");
return 0;
} else {
trace_LOG( trace_INFO, "-I- CAN0 Initialisations Completed\n\r");
}
#if defined AT91C_BASE_CAN1
if( pCAN1Transfer != NULL ) {
AT91C_BASE_CAN1->CAN_IER = AT91C_CAN_WAKEUP;
// CAN Controller Enable
AT91C_BASE_CAN1->CAN_MR = AT91C_CAN_CANEN;
tick = 0;
// Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver
while( ((pCAN1Transfer->test_can != AT91C_TEST_OK))
&& (tick < AT91C_CAN_TIMEOUT) ) {
tick++;
}
if (tick == AT91C_CAN_TIMEOUT) {
trace_LOG( trace_ERROR, "-E- CAN1 Initialisations FAILED\n\r");
return 0;
} else {
trace_LOG( trace_INFO, "-I- CAN1 Initialisations Completed\n\r");
}
}
#endif
return 1;
}
//------------------------------------------------------------------------------
/// Write a CAN transfer
/// \param pTransfer can transfer structure
/// \return return CAN_STATUS_SUCCESS if command passed, otherwise
/// return CAN_STATUS_LOCKED
//------------------------------------------------------------------------------
unsigned char CAN_Write( CanTransfer *pTransfer )
{
AT91PS_CAN base_can;
if (pTransfer->state == CAN_RECEIVING) {
pTransfer->state = CAN_IDLE;
}
if (pTransfer->state != CAN_IDLE) {
return CAN_STATUS_LOCKED;
}
trace_LOG( trace_DEBUG, "CAN_Write\n\r");
pTransfer->state = CAN_SENDING;
if( pTransfer->can_number == 0 ) {
base_can = AT91C_BASE_CAN0;
}
#ifdef AT91C_BASE_CAN1
else {
base_can = AT91C_BASE_CAN1;
}
#endif
base_can->CAN_TCR = pTransfer->mailbox_in_use;
base_can->CAN_IER = pTransfer->mailbox_in_use;
return CAN_STATUS_SUCCESS;
}
//------------------------------------------------------------------------------
/// Read a CAN transfer
/// \param pTransfer can transfer structure
/// \return return CAN_STATUS_SUCCESS if command passed, otherwise
/// return CAN_STATUS_LOCKED
//------------------------------------------------------------------------------
unsigned char CAN_Read( CanTransfer *pTransfer )
{
AT91PS_CAN base_can;
if (pTransfer->state != CAN_IDLE) {
return CAN_STATUS_LOCKED;
}
trace_LOG( trace_DEBUG, "CAN_Read\n\r");
pTransfer->state = CAN_RECEIVING;
if( pTransfer->can_number == 0 ) {
base_can = AT91C_BASE_CAN0;
}
#ifdef AT91C_BASE_CAN1
else {
base_can = AT91C_BASE_CAN1;
}
#endif
// enable interrupt
base_can->CAN_IER = pTransfer->mailbox_in_use;
return CAN_STATUS_SUCCESS;
}
//------------------------------------------------------------------------------
/// Test if CAN is in IDLE state
/// \param pTransfer can transfer structure
/// \return return 0 if CAN is in IDLE, otherwise return 1
//------------------------------------------------------------------------------
unsigned char CAN_IsInIdle( CanTransfer *pTransfer )
{
return( pTransfer->state != CAN_IDLE );
}
//------------------------------------------------------------------------------
/// Basic CAN test without Interrupt
//------------------------------------------------------------------------------
void CAN_BasicTestSuiteWithoutInterrupt(void)
{
#if defined AT91C_BASE_CAN1
unsigned int status;
unsigned int tick=0;
trace_LOG( trace_INFO, "Without Interrupt ");
trace_LOG( trace_INFO, "CAN0 Mailbox 0 transmitting to CAN1 Mailbox 0\n\r");
// Init CAN0 Mailbox 0, transmit
CAN_ResetTransfer( pCAN0Transfer );
pCAN0Transfer->can_number = 0;
pCAN0Transfer->mailbox_number = 0;
pCAN0Transfer->mode_reg = AT91C_CAN_MOT_TX | AT91C_CAN_PRIOR;
pCAN0Transfer->acceptance_mask_reg = 0x00000000;
pCAN0Transfer->identifier = AT91C_CAN_MIDvA & (0x07<<18);
pCAN0Transfer->data_low_reg = 0x11223344;
pCAN0Transfer->data_high_reg = 0x01234567;
pCAN0Transfer->control_reg = (AT91C_CAN_MDLC & (0x8<<16));
CAN_InitMailboxRegisters( pCAN0Transfer );
// Init CAN1 Mailbox 0, receive,
CAN_ResetTransfer( pCAN1Transfer );
pCAN1Transfer->can_number = 1;
pCAN1Transfer->mailbox_number = 0;
pCAN1Transfer->mode_reg = AT91C_CAN_MOT_RX;
pCAN1Transfer->acceptance_mask_reg = AT91C_CAN_MIDvA | AT91C_CAN_MIDvB;
pCAN1Transfer->identifier = AT91C_CAN_MIDvA & (0x07<<18);
pCAN1Transfer->data_low_reg = 0x00000000;
pCAN1Transfer->data_high_reg = 0x00000000;
pCAN1Transfer->control_reg = 0x00000000;
CAN_InitMailboxRegisters( pCAN1Transfer );
// Transfer Request for Mailbox 0
AT91C_BASE_CAN0->CAN_TCR = AT91C_CAN_MB0;
tick = 0;
do {
// CAN Message Status Register
status = AT91C_BASE_CAN0_MB0->CAN_MB_MSR;
}
while( !(status & AT91C_CAN_MRDY) && (++tick < AT91C_CAN_TIMEOUT) );
if (tick == AT91C_CAN_TIMEOUT) {
trace_LOG( trace_ERROR, "-E- Test FAILED\n\r");
}
else {
trace_LOG( trace_DEBUG, "-I- Transfer completed: CAN1 Mailbox 0 MRDY flag has raised\n\r");
if( AT91C_BASE_CAN0_MB0->CAN_MB_MDL != AT91C_BASE_CAN1_MB0->CAN_MB_MDL ) {
trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r");
}
else if( AT91C_BASE_CAN0_MB0->CAN_MB_MDH != AT91C_BASE_CAN1_MB0->CAN_MB_MDH ) {
trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r");
}
else {
trace_LOG( trace_INFO, "Test passed\n\r");
}
}
CAN_ResetAllMailbox();
trace_LOG( trace_INFO, "Without Interrupt ");
trace_LOG( trace_INFO, "CAN0 Mailboxes 1 & 2 transmitting to CAN1 Mailbox 15\n\r");
// Init CAN0 Mailbox 1, transmit
CAN_ResetTransfer( pCAN0Transfer );
pCAN0Transfer->can_number = 0;
pCAN0Transfer->mailbox_number = 1;
pCAN0Transfer->mode_reg = AT91C_CAN_MOT_TX | AT91C_CAN_PRIOR;
pCAN0Transfer->acceptance_mask_reg = 0x00000000;
pCAN0Transfer->identifier = AT91C_CAN_MIDvA & (0x09<<18); // ID 9
pCAN0Transfer->data_low_reg = 0xAABBCCDD;
pCAN0Transfer->data_high_reg = 0xCAFEDECA;
pCAN0Transfer->control_reg = (AT91C_CAN_MDLC & (0x8<<16)); // Mailbox Data Length Code
CAN_InitMailboxRegisters( pCAN0Transfer );
// Init CAN0 Mailbox 2, transmit
pCAN0Transfer->can_number = 0;
pCAN0Transfer->mailbox_number = 2;
pCAN0Transfer->mode_reg = AT91C_CAN_MOT_TX | (AT91C_CAN_PRIOR-(1<<16));
pCAN0Transfer->acceptance_mask_reg = 0x00000000;
pCAN0Transfer->identifier = AT91C_CAN_MIDvA & (0x0A<<18); // ID 10
pCAN0Transfer->data_low_reg = 0x55667788;
pCAN0Transfer->data_high_reg = 0x99AABBCC;
pCAN0Transfer->control_reg = (AT91C_CAN_MDLC & (0x8<<16)); // Mailbox Data Length Code
CAN_InitMailboxRegisters( pCAN0Transfer );
// Init CAN1 Mailbox 15, reception with overwrite
CAN_ResetTransfer( pCAN1Transfer );
pCAN1Transfer->can_number = 1;
pCAN1Transfer->mailbox_number = 15;
pCAN1Transfer->mode_reg = AT91C_CAN_MOT_RXOVERWRITE;
pCAN1Transfer->acceptance_mask_reg = 0;
pCAN1Transfer->identifier = 0x0;
pCAN1Transfer->data_low_reg = 0x00000000;
pCAN1Transfer->data_high_reg = 0x00000000;
pCAN1Transfer->control_reg = 0x00000000;
CAN_InitMailboxRegisters( pCAN1Transfer );
// Ask Transmissions on Mailbox 1 & 2 --> AT91C_CAN_MRDY & AT91C_CAN_MMI raises for Mailbox 15 CAN_MB_SR
AT91C_BASE_CAN0->CAN_TCR = AT91C_CAN_MB1 | AT91C_CAN_MB2;
// Wait for Last Transmit Mailbox
tick = 0;
do {
status = AT91C_BASE_CAN1_MB15->CAN_MB_MSR;
}
while( !(status & AT91C_CAN_MMI) && (++tick < AT91C_CAN_TIMEOUT) );
if (tick == AT91C_CAN_TIMEOUT) {
}
else {
trace_LOG( trace_DEBUG, "-I- Transfer completed: CAN1 Mailbox 15 MRDY and MMI flags have raised\n\r");
if( AT91C_BASE_CAN0_MB1->CAN_MB_MDL != AT91C_BASE_CAN1_MB15->CAN_MB_MDL ) {
trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r");
}
else if( AT91C_BASE_CAN0_MB1->CAN_MB_MDH != AT91C_BASE_CAN1_MB15->CAN_MB_MDH ) {
trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r");
}
else {
trace_LOG( trace_INFO, "Test passed\n\r");
}
}
CAN_ResetAllMailbox();
trace_LOG( trace_INFO, "Without Interrupt ");
trace_LOG( trace_INFO, "CAN0 Mailboxes 1 & 2 transmitting to CAN1 Mailbox 15\n\r");
// Init CAN0 Mailbox 1, transmit
CAN_ResetTransfer( pCAN0Transfer );
pCAN0Transfer->can_number = 0;
pCAN0Transfer->mailbox_number = 1;
pCAN0Transfer->mode_reg = AT91C_CAN_MOT_TX | AT91C_CAN_PRIOR;
pCAN0Transfer->acceptance_mask_reg = 0x00000000;
pCAN0Transfer->identifier = AT91C_CAN_MIDvA & (0x09<<18); // ID 9
pCAN0Transfer->data_low_reg = 0xAABBCCDD;
pCAN0Transfer->data_high_reg = 0xCAFEDECA;
pCAN0Transfer->control_reg = (AT91C_CAN_MDLC & (0x8<<16)); // Mailbox Data Length Code
CAN_InitMailboxRegisters( pCAN0Transfer );
// Init CAN0 Mailbox 2, transmit
pCAN0Transfer->can_number = 0;
pCAN0Transfer->mailbox_number = 2;
pCAN0Transfer->mode_reg = AT91C_CAN_MOT_TX | (AT91C_CAN_PRIOR-(1<<16));
pCAN0Transfer->acceptance_mask_reg = 0x00000000;
pCAN0Transfer->identifier = AT91C_CAN_MIDvA & (0x0A<<18); // ID 10
pCAN0Transfer->data_low_reg = 0x55667788;
pCAN0Transfer->data_high_reg = 0x99AABBCC;
pCAN0Transfer->control_reg = (AT91C_CAN_MDLC & (0x8<<16)); // Mailbox Data Length Code
CAN_InitMailboxRegisters( pCAN0Transfer );
// Init CAN1 Mailbox 15, reception with overwrite
CAN_ResetTransfer( pCAN1Transfer );
pCAN1Transfer->can_number = 1;
pCAN1Transfer->mailbox_number = 15;
pCAN1Transfer->mode_reg = AT91C_CAN_MOT_RX;
pCAN1Transfer->acceptance_mask_reg = 0;
pCAN1Transfer->identifier = 0x0;
pCAN1Transfer->data_low_reg = 0x00000000;
pCAN1Transfer->data_high_reg = 0x00000000;
pCAN1Transfer->control_reg = 0x00000000;
CAN_InitMailboxRegisters( pCAN1Transfer );
// Ask Transmissions on Mailbox 1 & 2 --> AT91C_CAN_MRDY & AT91C_CAN_MMI raises for Mailbox 15 CAN_MB_SR
AT91C_BASE_CAN0->CAN_TCR = AT91C_CAN_MB1 | AT91C_CAN_MB2;
// Wait for Last Transmit Mailbox
tick = 0;
do {
status = AT91C_BASE_CAN1_MB15->CAN_MB_MSR;
}
while( !(status & AT91C_CAN_MMI) && (++tick < AT91C_CAN_TIMEOUT) );
if (tick == AT91C_CAN_TIMEOUT) {
trace_LOG( trace_ERROR, "-E- Test FAILED\n\r");
}
else {
trace_LOG( trace_DEBUG, "Transfer completed: CAN1 Mailbox 15 MRDY and MMI flags have raised\n\r");
trace_LOG( trace_DEBUG, "MB_MDL: 0x%X\n\r", AT91C_BASE_CAN1_MB15->CAN_MB_MDL);
trace_LOG( trace_DEBUG, "MB_MDLH: 0x%X\n\r", AT91C_BASE_CAN1_MB15->CAN_MB_MDH);
if( AT91C_BASE_CAN0_MB2->CAN_MB_MDL != AT91C_BASE_CAN1_MB15->CAN_MB_MDL ) {
trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r");
}
else if( AT91C_BASE_CAN0_MB2->CAN_MB_MDH != AT91C_BASE_CAN1_MB15->CAN_MB_MDH ) {
trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r");
}
else {
trace_LOG( trace_INFO, "Test passed\n\r");
}
}
CAN_ResetAllMailbox();
trace_LOG( trace_INFO, "Without Interrupt ");
trace_LOG( trace_INFO, "CAN0 Mailbox 3 asking for CAN1 Mailbox 3 transmission\n\r");
// Init CAN0 Mailbox 3, consumer mailbox
// Sends a remote frame and waits for an answer
CAN_ResetTransfer( pCAN0Transfer );
pCAN0Transfer->can_number = 0;
pCAN0Transfer->mailbox_number = 3;
pCAN0Transfer->mode_reg = AT91C_CAN_MOT_CONSUMER | AT91C_CAN_PRIOR;
pCAN0Transfer->acceptance_mask_reg = AT91C_CAN_MIDvA | AT91C_CAN_MIDvB;
pCAN0Transfer->identifier = AT91C_CAN_MIDvA & (0x0B<<18); // ID 11
pCAN0Transfer->data_low_reg = 0x00000000;
pCAN0Transfer->data_high_reg = 0x00000000;
pCAN0Transfer->control_reg = 0x00000000;
CAN_InitMailboxRegisters( pCAN0Transfer );
// Init CAN1 Mailbox 3, porducer mailbox
// Waits to receive a Remote Frame before sending its contents
CAN_ResetTransfer( pCAN1Transfer );
pCAN1Transfer->can_number = 1;
pCAN1Transfer->mailbox_number = 3;
pCAN1Transfer->mode_reg = AT91C_CAN_MOT_PRODUCER | AT91C_CAN_PRIOR;
pCAN1Transfer->acceptance_mask_reg = 0;
pCAN1Transfer->identifier = AT91C_CAN_MIDvA & (0x0B<<18); // ID 11
pCAN1Transfer->data_low_reg = 0xEEDDFF00;
pCAN1Transfer->data_high_reg = 0x34560022;
pCAN1Transfer->control_reg = (AT91C_CAN_MDLC & (0x8<<16));
CAN_InitMailboxRegisters( pCAN1Transfer );
// Ask Transmissions on Mailbox 3 --> AT91C_CAN_MRDY raises for Mailbox 3 CAN_MB_SR
AT91C_BASE_CAN1->CAN_TCR = AT91C_CAN_MB3;
AT91C_BASE_CAN0->CAN_TCR = AT91C_CAN_MB3;
// Wait for Last Transmit Mailbox
tick = 0;
do {
status = AT91C_BASE_CAN0_MB3->CAN_MB_MSR;
}
while( !(status & AT91C_CAN_MRDY) && (++tick < AT91C_CAN_TIMEOUT) );
if (tick == AT91C_CAN_TIMEOUT) {
trace_LOG( trace_ERROR, "-E- Test FAILED\n\r");
}
else {
trace_LOG( trace_DEBUG, "-I- Transfer Completed: CAN0 & CAN1 Mailboxes 3 MRDY flags have raised\n\r");
if( AT91C_BASE_CAN0_MB3->CAN_MB_MDL != AT91C_BASE_CAN1_MB3->CAN_MB_MDL ) {
trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r");
}
else if( AT91C_BASE_CAN0_MB3->CAN_MB_MDH != AT91C_BASE_CAN1_MB3->CAN_MB_MDH ) {
trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r");
}
else {
trace_LOG( trace_INFO, "Test passed\n\r");
}
}
#endif // AT91C_BASE_CAN1
return;
}
//------------------------------------------------------------------------------
/// Disable CAN and enter in low power
//------------------------------------------------------------------------------
void CAN_disable( void )
{
// Disable the interrupt on the interrupt controller
AIC_DisableIT(AT91C_ID_CAN0);
// disable all IT
AT91C_BASE_CAN0->CAN_IDR = 0x1FFFFFFF;
#if defined AT91C_BASE_CAN1
AIC_DisableIT(AT91C_ID_CAN1);
// disable all IT
AT91C_BASE_CAN1->CAN_IDR = 0x1FFFFFFF;
#endif
// Enable Low Power mode
AT91C_BASE_CAN0->CAN_MR |= AT91C_CAN_LPM;
// Disable CANs Transceivers
// Enter standby mode
PIO_Set(&pin_can_transceiver_rs);
#if defined (PIN_CAN_TRANSCEIVER_RXEN)
// Enable ultra Low Power mode
PIO_Clear(&pin_can_transceiver_rxen);
#endif
// Disable clock for CAN PIO
AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_PIOA);
// Disable the CAN0 controller peripheral clock
AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_CAN0);
}
//------------------------------------------------------------------------------
/// baudrate calcul
/// \param base_CAN CAN base address
/// \param baudrate Baudrate value
/// allowed values: 1000, 800, 500, 250, 125, 50, 25, 10
/// \return return 1 in success, otherwise return 0
//------------------------------------------------------------------------------
unsigned char CAN_BaudRateCalculate( AT91PS_CAN base_CAN,
unsigned int baudrate )
{
unsigned int BRP;
unsigned int PROPAG;
unsigned int PHASE1;
unsigned int PHASE2;
unsigned int SJW;
unsigned int t1t2;
base_CAN->CAN_BR = 0;
BRP = (BOARD_MCK / (baudrate*1000*16))-1;
//trace_LOG( trace_DEBUG, "BRP = 0x%X\n\r", BRP);
// timing Delay:
// Delay Bus Driver: 50 ns
// Delay Receiver: 30 ns
// Delay Bus Line: 110 ns
if( (16*baudrate*2*(50+30+110)/1000000) >= 1) {
PROPAG = (16*baudrate*2*(50+30+110)/1000000)-1;
}
else {
PROPAG = 0;
}
//trace_LOG( trace_DEBUG, "PROPAG = 0x%X\n\r", PROPAG);
t1t2 = 15-(PROPAG+1);
//trace_LOG( trace_DEBUG, "t1t2 = 0x%X\n\r", t1t2);
if( (t1t2 & 0x01) == 0x01 ) {
// ODD
//trace_LOG( trace_DEBUG, "ODD\n\r");
PHASE1 = ((t1t2-1)/2)-1;
PHASE2 = PHASE1+1;
}
else {
// EVEN
//trace_LOG( trace_DEBUG, "EVEN\n\r");
PHASE1 = (t1t2/2)-1;
PHASE2 = PHASE1;
}
//trace_LOG( trace_DEBUG, "PHASE1 = 0x%X\n\r", PHASE1);
//trace_LOG( trace_DEBUG, "PHASE2 = 0x%X\n\r", PHASE2);
if( 1 > (4/(PHASE1+1)) ) {
//trace_LOG( trace_DEBUG, "4*Tcsc\n\r");
SJW = 3;
}
else {
//trace_LOG( trace_DEBUG, "Tphs1\n\r");
SJW = PHASE1;
}
//trace_LOG( trace_DEBUG, "SJW = 0x%X\n\r", SJW);
// Verif
if( BRP == 0 ) {
trace_LOG( trace_DEBUG, "BRP = 0 is not authorized\n\r");
return 0;
}
if( (PROPAG + PHASE1 + PHASE2) != 12 ) {
trace_LOG( trace_DEBUG, "(PROPAG + PHASE1 + PHASE2) != 12\n\r");
return 0;
}
base_CAN->CAN_BR = (AT91C_CAN_PHASE2 & (PHASE2 << 0))
+ (AT91C_CAN_PHASE1 & (PHASE1 << 4))
+ (AT91C_CAN_PROPAG & (PROPAG << 8))
+ (AT91C_CAN_SYNC & (SJW << 12))
+ (AT91C_CAN_BRP & (BRP << 16))
+ (AT91C_CAN_SMP & (0 << 24));
return 1;
}
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// Init of the CAN peripheral
/// \param baudrate Baudrate value
/// allowed values: 1000, 800, 500, 250, 125, 50, 25, 10
/// \param canTransfer0 CAN0 structure transfer
/// \param canTransfer1 CAN1 structure transfer
/// \return return 1 if CAN has good baudrate and CAN is synchronized,
/// otherwise return 0
//------------------------------------------------------------------------------
unsigned char CAN_Init( unsigned int baudrate,
CanTransfer *canTransfer0,
CanTransfer *canTransfer1 )
{
unsigned char ret;
// CAN Transmit Serial Data
#if defined (PINS_CAN_TRANSCEIVER_TXD)
PIO_Configure(pins_can_transceiver_txd, PIO_LISTSIZE(pins_can_transceiver_txd));
#endif
#if defined (PINS_CAN_TRANSCEIVER_RXD)
// CAN Receive Serial Data
PIO_Configure(pins_can_transceiver_rxd, PIO_LISTSIZE(pins_can_transceiver_rxd));
#endif
// CAN RS
PIO_Configure(&pin_can_transceiver_rs, PIO_LISTSIZE(pin_can_transceiver_rs));
#if defined (PIN_CAN_TRANSCEIVER_RXEN)
// CAN RXEN
PIO_Configure(&pin_can_transceiver_rxen, PIO_LISTSIZE(pin_can_transceiver_rxen));
#endif
// Enable clock for CAN PIO
AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_PIOA);
// Enable the CAN0 controller peripheral clock
AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_CAN0);
// disable all IT
AT91C_BASE_CAN0->CAN_IDR = 0x1FFFFFFF;
// Enable CANs Transceivers
#if defined (PIN_CAN_TRANSCEIVER_RXEN)
// Disable ultra Low Power mode
PIO_Set(&pin_can_transceiver_rxen);
#endif
// Normal Mode (versus Standby mode)
PIO_Clear(&pin_can_transceiver_rs);
// Configure the AIC for CAN interrupts
AIC_ConfigureIT(AT91C_ID_CAN0, AT91C_AIC_PRIOR_HIGHEST, CAN0_Handler);
// Enable the interrupt on the interrupt controller
AIC_EnableIT(AT91C_ID_CAN0);
if( CAN_BaudRateCalculate(AT91C_BASE_CAN0, baudrate) == 0 ) {
// Baudrate problem
trace_LOG( trace_DEBUG, "Baudrate CAN0 problem\n\r");
return 0;
}
pCAN0Transfer = canTransfer0;
#if defined AT91C_BASE_CAN1
if( canTransfer1 != NULL ) {
pCAN1Transfer = canTransfer1;
// Enable CAN1 Clocks
AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_CAN1);
// disable all IT
AT91C_BASE_CAN1->CAN_IDR = 0x1FFFFFFF;
// Configure the AIC for CAN interrupts
AIC_ConfigureIT(AT91C_ID_CAN1, AT91C_AIC_PRIOR_HIGHEST, CAN1_Handler);
// Enable the interrupt on the interrupt controller
AIC_EnableIT(AT91C_ID_CAN1);
if( CAN_BaudRateCalculate(AT91C_BASE_CAN1, baudrate) == 0 ) {
// Baudrate problem
trace_LOG( trace_DEBUG, "Baudrate CAN1 problem\n\r");
return 0;
}
}
#endif
// Reset all mailbox
CAN_ResetAllMailbox();
// Enable the interrupt with all error cases
AT91C_BASE_CAN0->CAN_IER = AT91C_CAN_CERR // (CAN) CRC Error
| AT91C_CAN_SERR // (CAN) Stuffing Error
| AT91C_CAN_BERR // (CAN) Bit Error
| AT91C_CAN_FERR // (CAN) Form Error
| AT91C_CAN_AERR; // (CAN) Acknowledgment Error
#if defined AT91C_BASE_CAN1
if( canTransfer1 != NULL ) {
AT91C_BASE_CAN1->CAN_IER = AT91C_CAN_CERR // (CAN) CRC Error
| AT91C_CAN_SERR // (CAN) Stuffing Error
| AT91C_CAN_BERR // (CAN) Bit Error
| AT91C_CAN_FERR // (CAN) Form Error
| AT91C_CAN_AERR; // (CAN) Acknowledgment Error
}
#endif
// Wait for CAN synchronisation
if( CAN_Synchronisation( ) == 1 ) {
ret = 1;
}
else {
ret = 0;
}
return ret;
}
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/can/can.c | C | oos | 39,626 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _CAN_H
#define _CAN_H
//------------------------------------------------------------------------------
// Definitions
//------------------------------------------------------------------------------
#define AT91C_CAN_TIMEOUT 100000
#define AT91C_TEST_NOK 0
#define AT91C_TEST_OK 1
#define CAN_STATUS_SUCCESS 0
#define CAN_STATUS_LOCKED 1
#define CAN_STATUS_ABORTED 2
#define CAN_STATUS_RESET 3
#if defined (AT91C_BASE_CAN)
#define AT91C_BASE_CAN0 AT91C_BASE_CAN
#endif
#if defined (AT91C_ID_CAN)
#define AT91C_ID_CAN0 AT91C_ID_CAN
#endif
#if defined (AT91C_BASE_CAN_MB0)
#define AT91C_BASE_CAN0_MB0 AT91C_BASE_CAN_MB0
#define AT91C_BASE_CAN0_MB1 AT91C_BASE_CAN_MB1
#define AT91C_BASE_CAN0_MB2 AT91C_BASE_CAN_MB2
#define AT91C_BASE_CAN0_MB3 AT91C_BASE_CAN_MB3
#define AT91C_BASE_CAN0_MB4 AT91C_BASE_CAN_MB4
#define AT91C_BASE_CAN0_MB5 AT91C_BASE_CAN_MB5
#define AT91C_BASE_CAN0_MB6 AT91C_BASE_CAN_MB6
#define AT91C_BASE_CAN0_MB7 AT91C_BASE_CAN_MB7
#endif
#if defined (AT91C_BASE_CAN_MB8)
#define AT91C_BASE_CAN0_MB8 AT91C_BASE_CAN_MB8
#define AT91C_BASE_CAN0_MB9 AT91C_BASE_CAN_MB9
#define AT91C_BASE_CAN0_MB10 AT91C_BASE_CAN_MB10
#define AT91C_BASE_CAN0_MB11 AT91C_BASE_CAN_MB11
#define AT91C_BASE_CAN0_MB12 AT91C_BASE_CAN_MB12
#define AT91C_BASE_CAN0_MB13 AT91C_BASE_CAN_MB13
#define AT91C_BASE_CAN0_MB14 AT91C_BASE_CAN_MB14
#define AT91C_BASE_CAN0_MB15 AT91C_BASE_CAN_MB15
#endif
#define NUM_MAILBOX_MAX 16
//------------------------------------------------------------------------------
// Types
//------------------------------------------------------------------------------
typedef struct
{
volatile unsigned char state;
volatile unsigned char can_number;
volatile unsigned char mailbox_number;
volatile unsigned char test_can;
volatile unsigned int mode_reg;
volatile unsigned int acceptance_mask_reg;
volatile unsigned int identifier;
volatile unsigned int data_low_reg;
volatile unsigned int data_high_reg;
volatile unsigned int control_reg;
volatile unsigned int mailbox_in_use;
volatile int size;
} CanTransfer;
//------------------------------------------------------------------------------
// Exported functions
//------------------------------------------------------------------------------
extern unsigned char CAN_Init( unsigned int baudrate,
CanTransfer *canTransferRead,
CanTransfer *canTransferWrite );
extern void CAN_BasicTestSuite(void);
extern void CAN_disable( void );
extern void CAN_ResetAllMailbox( void );
extern void CAN_ResetTransfer( CanTransfer *pTransfer );
extern void CAN_InitMailboxRegisters( CanTransfer *pTransfer );
extern unsigned char CAN_IsInIdle( CanTransfer *pTransfer );
extern unsigned char CAN_Write( CanTransfer *pTransfer );
extern unsigned char CAN_Read( CanTransfer *pTransfer );
extern void CAN_BasicTestSuiteWithoutInterrupt( void );
extern unsigned char CAN_IsInIdle( CanTransfer *pTransfer );
#endif // _CAN_H
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/can/can.h | C | oos | 4,884 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include "pwmc.h"
#include <board.h>
#include <utility/assert.h>
#include <utility/trace.h>
//------------------------------------------------------------------------------
// Local functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// Finds a prescaler/divisor couple to generate the desired frequency from
/// MCK.
/// Returns the value to enter in PWMC_MR or 0 if the configuration cannot be
/// met.
/// \param frequency Desired frequency in Hz.
/// \param mck Master clock frequency in Hz.
//------------------------------------------------------------------------------
static unsigned short FindClockConfiguration(
unsigned int frequency,
unsigned int mck)
{
unsigned int divisors[11] = {1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024};
unsigned char divisor = 0;
unsigned int prescaler;
SANITY_CHECK(frequency < mck);
// Find prescaler and divisor values
prescaler = (mck / divisors[divisor]) / frequency;
while ((prescaler > 255) && (divisor < 11)) {
divisor++;
prescaler = (mck / divisors[divisor]) / frequency;
}
// Return result
if (divisor < 11) {
trace_LOG(trace_DEBUG, "-D- Found divisor=%u and prescaler=%u for freq=%uHz\n\r",
divisors[divisor], prescaler, frequency);
return prescaler | (divisor << 8);
}
else {
return 0;
}
}
//------------------------------------------------------------------------------
// Global functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// Configures PWM a channel with the given parameters.
/// The PWM controller must have been clocked in the PMC prior to calling this
/// function.
/// \param channel Channel number.
/// \param prescaler Channel prescaler.
/// \param alignment Channel alignment.
/// \param polarity Channel polarity.
//------------------------------------------------------------------------------
void PWMC_ConfigureChannel(
unsigned char channel,
unsigned int prescaler,
unsigned int alignment,
unsigned int polarity)
{
SANITY_CHECK(prescaler < AT91C_PWMC_CPRE_MCKB);
SANITY_CHECK((alignment & ~AT91C_PWMC_CALG) == 0);
SANITY_CHECK((polarity & ~AT91C_PWMC_CPOL) == 0);
// Disable channel
AT91C_BASE_PWMC->PWMC_DIS = 1 << channel;
// Configure channel
AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CMR = prescaler | alignment | polarity;
}
//------------------------------------------------------------------------------
/// Configures PWM clocks A & B to run at the given frequencies. This function
/// finds the best MCK divisor and prescaler values automatically.
/// \param clka Desired clock A frequency (0 if not used).
/// \param clkb Desired clock B frequency (0 if not used).
/// \param mck Master clock frequency.
//------------------------------------------------------------------------------
void PWMC_ConfigureClocks(unsigned int clka, unsigned int clkb, unsigned int mck)
{
unsigned int mode = 0;
unsigned int result;
// Clock A
if (clka != 0) {
result = FindClockConfiguration(clka, mck);
ASSERT(result != 0, "-F- Could not generate the desired PWM frequency (%uHz)\n\r", clka);
mode |= result;
}
// Clock B
if (clkb != 0) {
result = FindClockConfiguration(clkb, mck);
ASSERT(result != 0, "-F- Could not generate the desired PWM frequency (%uHz)\n\r", clkb);
mode |= (result << 16);
}
// Configure clocks
trace_LOG(trace_DEBUG, "-D- Setting PWMC_MR = 0x%08X\n\r", mode);
AT91C_BASE_PWMC->PWMC_MR = mode;
}
//------------------------------------------------------------------------------
/// Sets the period value used by a PWM channel. This function writes directly
/// to the CPRD register if the channel is disabled; otherwise, it uses the
/// update register CUPD.
/// \param channel Channel number.
/// \param period Period value.
//------------------------------------------------------------------------------
void PWMC_SetPeriod(unsigned char channel, unsigned short period)
{
// If channel is disabled, write to CPRD
if ((AT91C_BASE_PWMC->PWMC_SR & (1 << channel)) == 0) {
AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CPRDR = period;
}
// Otherwise use update register
else {
AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CMR |= AT91C_PWMC_CPD;
AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CUPDR = period;
}
}
//------------------------------------------------------------------------------
/// Sets the duty cycle used by a PWM channel. This function writes directly to
/// the CDTY register if the channel is disabled; otherwise it uses the
/// update register CUPD.
/// Note that the duty cycle must always be inferior or equal to the channel
/// period.
/// \param channel Channel number.
/// \param duty Duty cycle value.
//------------------------------------------------------------------------------
void PWMC_SetDutyCycle(unsigned char channel, unsigned short duty)
{
SANITY_CHECK(duty <= AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CPRDR);
// SAM7S errata
#if defined(at91sam7s16) || defined(at91sam7s161) || defined(at91sam7s32) \
|| defined(at91sam7s321) || defined(at91sam7s64) || defined(at91sam7s128) \
|| defined(at91sam7s256) || defined(at91sam7s512)
ASSERT(duty > 0, "-F- Duty cycle value 0 is not permitted on SAM7S chips.\n\r");
ASSERT((duty > 1) || (AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CMR & AT91C_PWMC_CALG),
"-F- Duty cycle value 1 is not permitted in left-aligned mode on SAM7S chips.\n\r");
#endif
// If channel is disabled, write to CDTY
if ((AT91C_BASE_PWMC->PWMC_SR & (1 << channel)) == 0) {
AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CDTYR = duty;
}
// Otherwise use update register
else {
AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CMR &= ~AT91C_PWMC_CPD;
AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CUPDR = duty;
}
}
//------------------------------------------------------------------------------
/// Enables the given PWM channel. This does NOT enable the corresponding pin;
/// this must be done in the user code.
/// \param channel Channel number.
//------------------------------------------------------------------------------
void PWMC_EnableChannel(unsigned char channel)
{
AT91C_BASE_PWMC->PWMC_ENA = 1 << channel;
}
//------------------------------------------------------------------------------
/// Disables the given PWM channel.
/// \param channel Channel number.
//------------------------------------------------------------------------------
void PWMC_DisableChannel(unsigned char channel)
{
AT91C_BASE_PWMC->PWMC_DIS = 1 << channel;
}
//------------------------------------------------------------------------------
/// Enables the period interrupt for the given PWM channel.
/// \param channel Channel number.
//------------------------------------------------------------------------------
void PWMC_EnableChannelIt(unsigned char channel)
{
AT91C_BASE_PWMC->PWMC_IER = 1 << channel;
}
//------------------------------------------------------------------------------
/// Disables the period interrupt for the given PWM channel.
/// \param channel Channel number.
//------------------------------------------------------------------------------
void PWMC_DisableChannelIt(unsigned char channel)
{
AT91C_BASE_PWMC->PWMC_IDR = 1 << channel;
}
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/pwmc/pwmc.c | C | oos | 9,611 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef PWMC_H
#define PWMC_H
//------------------------------------------------------------------------------
// Global functions
//------------------------------------------------------------------------------
extern void PWMC_ConfigureChannel(
unsigned char channel,
unsigned int prescaler,
unsigned int alignment,
unsigned int polarity);
extern void PWMC_ConfigureClocks
(unsigned int clka,
unsigned int clkb,
unsigned int mck);
extern void PWMC_SetPeriod(unsigned char channel, unsigned short period);
extern void PWMC_SetDutyCycle(unsigned char channel, unsigned short duty);
extern void PWMC_EnableChannel(unsigned char channel);
extern void PWMC_DisableChannel(unsigned char channel);
extern void PWMC_EnableChannelIt(unsigned char channel);
extern void PWMC_DisableChannelIt(unsigned char channel);
#endif //#ifndef PWMC_H
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/pwmc/pwmc.h | C | oos | 2,484 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support - ROUSSET -
* ----------------------------------------------------------------------------
* Copyright (c) 2006, Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* - Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the disclaimer below in the documentation and/or
* other materials provided with the distribution.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef MCI_H
#define MCI_H
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include <board.h>
//------------------------------------------------------------------------------
// Constants
//------------------------------------------------------------------------------
/// Transfer is pending.
#define MCI_STATUS_PENDING 1
/// Transfer has been aborted because an error occured.
#define MCI_STATUS_ERROR 2
/// Card did not answer command.
#define MCI_STATUS_NORESPONSE 3
/// MCI driver is currently in use.
#define MCI_ERROR_LOCK 1
/// MCI configuration with 1-bit data bus on slot A (for MMC cards).
#define MCI_MMC_SLOTA 0
/// MCI configuration with 1-bit data bus on slot B (for MMC cards).
#define MCI_MMC_SLOTB 1
/// MCI configuration with 4-bit data bus on slot A (for SD cards).
#define MCI_SD_SLOTA AT91C_MCI_SCDBUS
/// MCI configuration with 4-bit data bus on slot B (for SD cards).
#define MCI_SD_SLOTB (AT91C_MCI_SCDBUS | 1)
/// Start new data transfer
#define MCI_NEW_TRANSFER 0
/// Continue data transfer
#define MCI_CONTINUE_TRANSFER 1
/// MCI SD Bus Width 1-bit
#define MCI_SDCBUS_1BIT (0 << 7)
/// MCI SD Bus Width 4-bit
#define MCI_SDCBUS_4BIT (1 << 7)
//------------------------------------------------------------------------------
// Types
//------------------------------------------------------------------------------
/// MCI end-of-transfer callback function.
typedef void (*MciCallback)(unsigned char status, void *pCommand);
//------------------------------------------------------------------------------
/// MCI Transfer Request prepared by the application upper layer. This structure
/// is sent to the MCI_SendCommand function to start the transfer. At the end of
/// the transfer, the callback is invoked by the interrupt handler.
//------------------------------------------------------------------------------
typedef struct _MciCmd {
/// Command status.
volatile char status;
/// Command code.
unsigned int cmd;
/// Command argument.
unsigned int arg;
/// Data buffer.
unsigned char *pData;
/// Size of data buffer in bytes.
unsigned short blockSize;
/// Number of blocks to be transfered
unsigned short nbBlock;
/// Indicate if continue to transfer data
unsigned char conTrans;
/// Indicates if the command is a read operation.
unsigned char isRead;
/// Response buffer.
unsigned int *pResp;
/// Size of SD card response in bytes.
unsigned char resSize;
/// Optional user-provided callback function.
MciCallback callback;
/// Optional argument to the callback function.
void *pArg;
} MciCmd;
//------------------------------------------------------------------------------
/// MCI driver structure. Holds the internal state of the MCI driver and
/// prevents parallel access to a MCI peripheral.
//------------------------------------------------------------------------------
typedef struct {
/// Pointer to a MCI peripheral.
AT91S_MCI *pMciHw;
/// MCI peripheral identifier.
unsigned char mciId;
/// Pointer to currently executing command.
MciCmd *pCommand;
/// Mutex.
volatile char semaphore;
} Mci;
//------------------------------------------------------------------------------
// Global functions
//------------------------------------------------------------------------------
extern void MCI_Init(
Mci *pMci,
AT91PS_MCI pMciHw,
unsigned char mciId,
unsigned int mode);
extern void MCI_SetSpeed(Mci *pMci, unsigned int mciSpeed);
extern unsigned char MCI_SendCommand(Mci *pMci, MciCmd *pMciCmd);
extern void MCI_Handler(Mci *pMci);
extern unsigned char MCI_IsTxComplete(MciCmd *pMciCmd);
extern unsigned char MCI_CheckBusy(Mci *pMci);
extern void MCI_Close(Mci *pMci);
extern void MCI_SetBusWidth(Mci *pMci, unsigned char busWidth);
#endif //#ifndef MCI_H
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/mci/mci.h | C | oos | 5,961 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support - ROUSSET -
* ----------------------------------------------------------------------------
* Copyright (c) 2006, Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* - Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the disclaimer below in the documentation and/or
* other materials provided with the distribution.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include "mci.h"
#include <utility/assert.h>
#include <utility/trace.h>
//------------------------------------------------------------------------------
// Local constants
//------------------------------------------------------------------------------
/// Bit mask for status register errors.
#define STATUS_ERRORS (AT91C_MCI_UNRE \
| AT91C_MCI_OVRE \
| AT91C_MCI_DTOE \
| AT91C_MCI_DCRCE \
| AT91C_MCI_RTOE \
| AT91C_MCI_RENDE \
| AT91C_MCI_RCRCE \
| AT91C_MCI_RDIRE \
| AT91C_MCI_RINDE)
/// MCI data timeout configuration with 1048576 MCK cycles between 2 data transfers.
#define DTOR_1MEGA_CYCLES (AT91C_MCI_DTOCYC | AT91C_MCI_DTOMUL)
#define SDCARD_APP_OP_COND_CMD (41 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO )
#define MMC_SEND_OP_COND_CMD (1 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_OPDCMD)
#define DISABLE 0 // Disable MCI interface
#define ENABLE 1 // Enable MCI interface
//------------------------------------------------------------------------------
// Local macros
//------------------------------------------------------------------------------
/// Used to write in PMC registers.
#define WRITE_PMC(pPmc, regName, value) pPmc->regName = (value)
/// Used to write in MCI registers.
#define WRITE_MCI(pMci, regName, value) pMci->regName = (value)
/// Used to read from MCI registers.
#define READ_MCI(pMci, regName) (pMci->regName)
//------------------------------------------------------------------------------
// Global functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// Enable/disable a MCI driver instance.
/// \param pMci Pointer to a MCI driver instance.
/// \param enb 0 for disable MCI and 1 for enable MCI.
//------------------------------------------------------------------------------
void MCI_Enable(Mci *pMci, unsigned char enb)
{
AT91S_MCI *pMciHw = pMci->pMciHw;
SANITY_CHECK(pMci);
SANITY_CHECK(pMci->pMciHw);
// Set the Control Register: Enable/Disable MCI interface clock
if(enb == DISABLE) {
WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIDIS);
}
else {
WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIEN);
}
}
//------------------------------------------------------------------------------
/// Initializes a MCI driver instance and the underlying peripheral.
/// \param pMci Pointer to a MCI driver instance.
/// \param pMciHw Pointer to a MCI peripheral.
/// \param mciId MCI peripheral identifier.
/// \param mode Slot and type of connected card.
//------------------------------------------------------------------------------
void MCI_Init(
Mci *pMci,
AT91S_MCI *pMciHw,
unsigned char mciId,
unsigned int mode)
{
unsigned short clkDiv;
SANITY_CHECK(pMci);
SANITY_CHECK(pMciHw);
SANITY_CHECK((mode == MCI_MMC_SLOTA) || (mode == MCI_MMC_SLOTB)
|| (mode == MCI_SD_SLOTA) || (mode == MCI_SD_SLOTB));
// Initialize the MCI driver structure
pMci->pMciHw = pMciHw;
pMci->mciId = mciId;
pMci->semaphore = 1;
pMci->pCommand = 0;
// Enable the MCI clock
WRITE_PMC(AT91C_BASE_PMC, PMC_PCER, (1 << mciId));
// Reset the MCI
WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_SWRST);
// Disable the MCI
WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIDIS | AT91C_MCI_PWSDIS);
// Disable all the interrupts
WRITE_MCI(pMciHw, MCI_IDR, 0xFFFFFFFF);
// Set the Data Timeout Register
WRITE_MCI(pMciHw, MCI_DTOR, DTOR_1MEGA_CYCLES);
// Set the Mode Register: 400KHz for MCK = 48MHz (CLKDIV = 58)
clkDiv = (BOARD_MCK / (400000 * 2)) - 1;
WRITE_MCI(pMciHw, MCI_MR, (clkDiv | (AT91C_MCI_PWSDIV & (0x7 << 8))));
// Set the SDCard Register
WRITE_MCI(pMciHw, MCI_SDCR, mode);
// Enable the MCI and the Power Saving
WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIEN);
// Disable the MCI peripheral clock.
WRITE_PMC(AT91C_BASE_PMC, PMC_PCDR, (1 << mciId));
}
//------------------------------------------------------------------------------
/// Close a MCI driver instance and the underlying peripheral.
/// \param pMci Pointer to a MCI driver instance.
/// \param pMciHw Pointer to a MCI peripheral.
/// \param mciId MCI peripheral identifier.
//------------------------------------------------------------------------------
void MCI_Close(Mci *pMci)
{
AT91S_MCI *pMciHw = pMci->pMciHw;
SANITY_CHECK(pMci);
SANITY_CHECK(pMciHw);
// Initialize the MCI driver structure
pMci->semaphore = 1;
pMci->pCommand = 0;
// Disable the MCI peripheral clock.
WRITE_PMC(AT91C_BASE_PMC, PMC_PCDR, (1 << pMci->mciId));
// Disable the MCI
WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIDIS);
// Disable all the interrupts
WRITE_MCI(pMciHw, MCI_IDR, 0xFFFFFFFF);
}
//------------------------------------------------------------------------------
/// Configure the MCI CLKDIV in the MCI_MR register. The max. for MCI clock is
/// MCK/2 and corresponds to CLKDIV = 0
/// \param pMci Pointer to the low level MCI driver.
/// \param mciSpeed MCI clock speed in Hz.
//------------------------------------------------------------------------------
void MCI_SetSpeed(Mci *pMci, unsigned int mciSpeed)
{
AT91S_MCI *pMciHw = pMci->pMciHw;
unsigned int mciMr;
unsigned short clkdiv;
SANITY_CHECK(pMci);
SANITY_CHECK(pMci->pMciHw);
// Set the Mode Register: 400KHz for MCK = 48MHz (CLKDIV = 58)
mciMr = READ_MCI(pMciHw, MCI_MR) & (~AT91C_MCI_CLKDIV);
// Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)
// divided by (2*(CLKDIV+1))
if (mciSpeed > 0) {
clkdiv = (BOARD_MCK / (mciSpeed * 2));
if (clkdiv > 0) {
clkdiv -= 1;
}
}
else {
clkdiv = 0;
}
WRITE_MCI(pMciHw, MCI_MR, mciMr | clkdiv);
}
//------------------------------------------------------------------------------
/// Configure the MCI SDCBUS in the MCI_SDCR register. Only two modes available
///
/// \param pMci Pointer to the low level MCI driver.
/// \param busWidth MCI bus width mode.
//------------------------------------------------------------------------------
void MCI_SetBusWidth(Mci *pMci, unsigned char busWidth)
{
AT91S_MCI *pMciHw = pMci->pMciHw;
unsigned int mciSdcr;
SANITY_CHECK(pMci);
SANITY_CHECK(pMci->pMciHw);
mciSdcr = (READ_MCI(pMciHw, MCI_SDCR) & ~(AT91C_MCI_SCDBUS));
WRITE_MCI(pMciHw, MCI_SDCR, mciSdcr | busWidth);
}
//------------------------------------------------------------------------------
/// Starts a MCI transfer. This is a non blocking function. It will return
/// as soon as the transfer is started.
/// Return 0 if successful; otherwise returns MCI_ERROR_LOCK if the driver is
/// already in use.
/// \param pMci Pointer to an MCI driver instance.
/// \param pCommand Pointer to the command to execute.
//------------------------------------------------------------------------------
unsigned char MCI_SendCommand(Mci *pMci, MciCmd *pCommand)
{
AT91PS_MCI pMciHw = pMci->pMciHw;
unsigned int mciIer, mciMr;
SANITY_CHECK(pMci);
SANITY_CHECK(pMciHw);
SANITY_CHECK(pCommand);
// Try to acquire the MCI semaphore
if (pMci->semaphore == 0) {
return MCI_ERROR_LOCK;
}
pMci->semaphore--;
// trace_LOG(trace_DEBUG, "MCI_SendCommand %x %d\n\r", READ_MCI(pMciHw, MCI_SR), pCommand->cmd & 0x3f);
// Command is now being executed
pMci->pCommand = pCommand;
pCommand->status = MCI_STATUS_PENDING;
// Enable the MCI clock
WRITE_PMC(AT91C_BASE_PMC, PMC_PCER, (1 << pMci->mciId));
//Disable MCI clock, for multi-block data transfer
MCI_Enable(pMci, DISABLE);
// Set PDC data transfer direction
if(pCommand->blockSize > 0) {
if(pCommand->isRead) {
WRITE_MCI(pMciHw, MCI_PTCR, AT91C_PDC_RXTEN);
}
else {
WRITE_MCI(pMciHw, MCI_PTCR, AT91C_PDC_TXTEN);
}
}
// Disable transmitter and receiver
WRITE_MCI(pMciHw, MCI_PTCR, AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS);
mciMr = READ_MCI(pMciHw, MCI_MR) & (~(AT91C_MCI_BLKLEN | AT91C_MCI_PDCMODE));
// Command with DATA stage
if (pCommand->blockSize > 0) {
// Enable PDC mode and set block size
if(pCommand->conTrans != MCI_CONTINUE_TRANSFER) {
WRITE_MCI(pMciHw, MCI_MR, mciMr | AT91C_MCI_PDCMODE | (pCommand->blockSize << 16));
}
// DATA transfer from card to host
if (pCommand->isRead) {
WRITE_MCI(pMciHw, MCI_RPR, (int) pCommand->pData);
// If Multiblock command set the BLKR register
/* if (pCommand->nbBlock > 1) {
WRITE_MCI(pMciHw, MCI_BLKR, pCommand->nbBlock | (pCommand->blockSize << 16));
}
else {
WRITE_MCI(pMciHw, MCI_BLKR, (pCommand->blockSize << 16));
}*/
// Sanity check
if (pCommand->nbBlock == 0)
pCommand->nbBlock = 1;
////////
if ((pCommand->blockSize & 0x3) != 0) {
WRITE_MCI(pMciHw, MCI_RCR, (pCommand->nbBlock * pCommand->blockSize) / 4 + 1);
}
else {
WRITE_MCI(pMciHw, MCI_RCR, (pCommand->nbBlock * pCommand->blockSize) / 4);
}
WRITE_MCI(pMciHw, MCI_PTCR, AT91C_PDC_RXTEN);
mciIer = AT91C_MCI_ENDRX | STATUS_ERRORS;
// mciIer = AT91C_MCI_RXBUFF | STATUS_ERRORS;
}
// DATA transfer from host to card
else {
// Sanity check
if (pCommand->nbBlock == 0)
pCommand->nbBlock = 1;
WRITE_MCI(pMciHw, MCI_TPR, (int) pCommand->pData);
// Update the PDC counter
if ((pCommand->blockSize & 0x3) != 0) {
WRITE_MCI(pMciHw, MCI_TCR, (pCommand->nbBlock * pCommand->blockSize) / 4 + 1);
}
else {
WRITE_MCI(pMciHw, MCI_TCR, (pCommand->nbBlock * pCommand->blockSize) / 4);
}
// MCI_BLKE notifies the end of Multiblock command
mciIer = AT91C_MCI_BLKE | STATUS_ERRORS;
}
}
// No data transfer: stop at the end of the command
else {
WRITE_MCI(pMciHw, MCI_MR, mciMr);
mciIer = AT91C_MCI_CMDRDY | STATUS_ERRORS;
}
// Enable MCI clock
MCI_Enable(pMci, ENABLE);
// Send the command
if((pCommand->conTrans != MCI_CONTINUE_TRANSFER)
|| (pCommand->blockSize == 0)) {
WRITE_MCI(pMciHw, MCI_ARGR, pCommand->arg);
WRITE_MCI(pMciHw, MCI_CMDR, pCommand->cmd);
}
// In case of transmit, the PDC shall be enabled after sending the command
if ((pCommand->blockSize > 0) && !(pCommand->isRead)) {
WRITE_MCI(pMciHw, MCI_PTCR, AT91C_PDC_TXTEN);
}
// Ignore data error
// if (pCommand->blockSize == 0) {
{
mciIer &= ~(AT91C_MCI_UNRE | AT91C_MCI_OVRE \
| AT91C_MCI_DTOE | AT91C_MCI_DCRCE);
}
// Interrupt enable shall be done after PDC TXTEN and RXTEN
WRITE_MCI(pMciHw, MCI_IER, mciIer);
return 0;
}
//------------------------------------------------------------------------------
/// Check NOTBUSY and DTIP bits of status register on the given MCI driver.
/// Return value, 0 for bus ready, 1 for bus busy
/// \param pMci Pointer to a MCI driver instance.
//------------------------------------------------------------------------------
unsigned char MCI_CheckBusy(Mci *pMci)
{
AT91S_MCI *pMciHw = pMci->pMciHw;
unsigned int status;
// Enable MCI clock
MCI_Enable(pMci, ENABLE);
status = READ_MCI(pMciHw, MCI_SR);
// trace_LOG(trace_DEBUG, "status %x\n\r",status);
if(((status & AT91C_MCI_NOTBUSY)!=0)
&& ((status & AT91C_MCI_DTIP)==0)) {
// Disable MCI clock
MCI_Enable(pMci, DISABLE);
return 0;
}
else {
return 1;
}
}
//------------------------------------------------------------------------------
/// Check BLKE bit of status register on the given MCI driver.
/// \param pMci Pointer to a MCI driver instance.
//------------------------------------------------------------------------------
unsigned char MCI_CheckBlke(Mci *pMci)
{
AT91S_MCI *pMciHw = pMci->pMciHw;
unsigned int status;
status = READ_MCI(pMciHw, MCI_SR);
// trace_LOG(trace_DEBUG, "status %x\n\r",status);
if((status & AT91C_MCI_BLKE)!=0) {
return 0;
}
else {
return 1;
}
}
//------------------------------------------------------------------------------
/// Processes pending events on the given MCI driver.
/// \param pMci Pointer to a MCI driver instance.
//------------------------------------------------------------------------------
void MCI_Handler(Mci *pMci)
{
AT91S_MCI *pMciHw = pMci->pMciHw;
MciCmd *pCommand = pMci->pCommand;
unsigned int status;
unsigned char i;
#if defined(at91rm9200)
unsigned int mciCr, mciSdcr, mciMr, mciDtor;
#endif
SANITY_CHECK(pMci);
SANITY_CHECK(pMciHw);
SANITY_CHECK(pCommand);
// Read the status register
status = READ_MCI(pMciHw, MCI_SR) & READ_MCI(pMciHw, MCI_IMR);
// trace_LOG(trace_DEBUG, "status %x\n\r", status);
// Check if an error has occured
if ((status & STATUS_ERRORS) != 0) {
// Check error code
if ((status & STATUS_ERRORS) == AT91C_MCI_RTOE) {
pCommand->status = MCI_STATUS_NORESPONSE;
}
// if the command is SEND_OP_COND the CRC error flag is always present
// (cf : R3 response)
else if (((status & STATUS_ERRORS) != AT91C_MCI_RCRCE)
|| ((pCommand->cmd != SDCARD_APP_OP_COND_CMD)
&& (pCommand->cmd != MMC_SEND_OP_COND_CMD))) {
pCommand->status = MCI_STATUS_ERROR;
}
}
// Check if a transfer has been completed
if (((status & AT91C_MCI_CMDRDY) != 0)
|| ((status & AT91C_MCI_ENDRX) != 0)
|| ((status & AT91C_MCI_RXBUFF) != 0)
|| ((status & AT91C_MCI_ENDTX) != 0)
|| ((status & AT91C_MCI_BLKE) != 0)
|| ((status & AT91C_MCI_RTOE) != 0)) {
if (((status & AT91C_MCI_ENDRX) != 0)
|| ((status & AT91C_MCI_RXBUFF) != 0)
|| ((status & AT91C_MCI_ENDTX) != 0)) {
MCI_Enable(pMci, DISABLE);
}
/// On AT91RM9200-EK, if stop transmission, software reset MCI.
#if defined(at91rm9200)
if ((pCommand->cmd & AT91C_MCI_TRCMD_STOP) != 0) {
mciMr = READ_MCI(pMciHw, MCI_MR);
mciSdcr = READ_MCI(pMciHw, MCI_SDCR);
mciDtor = READ_MCI(pMciHw, MCI_DTOR);
WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_SWRST);
// trace_LOG(trace_DEBUG, "reset MCI\n\r");
WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIDIS | AT91C_MCI_PWSDIS);
WRITE_MCI(pMciHw, MCI_MR, mciMr);
WRITE_MCI(pMciHw, MCI_SDCR, mciSdcr);
WRITE_MCI(pMciHw, MCI_DTOR, mciDtor);
}
#endif
// If no error occured, the transfer is successful
if (pCommand->status == MCI_STATUS_PENDING) {
pCommand->status = 0;
}
#if 0
if ((status & AT91C_MCI_CMDRDY) != 0)
trace_LOG(trace_DEBUG, ".");
if ((status & AT91C_MCI_ENDRX) != 0)
trace_LOG(trace_DEBUG, "<");
if ((status & AT91C_MCI_ENDTX) != 0)
trace_LOG(trace_DEBUG, "-");
if ((status & AT91C_MCI_BLKE) != 0)
trace_LOG(trace_DEBUG, ">");
trace_LOG(trace_DEBUG, "\n\r");
#endif
// Store the card response in the provided buffer
if (pCommand->pResp) {
for (i=0; i < pCommand->resSize; i++) {
pCommand->pResp[i] = READ_MCI(pMciHw, MCI_RSPR[0]);
}
}
// Disable interrupts
WRITE_MCI(pMciHw, MCI_IDR, READ_MCI(pMciHw, MCI_IMR));
// Release the semaphore
pMci->semaphore++;
// Invoke the callback associated with the current command (if any)
if (pCommand->callback) {
(pCommand->callback)(pCommand->status, pCommand);
}
}
}
//------------------------------------------------------------------------------
/// Returns 1 if the given MCI transfer is complete; otherwise returns 0.
/// \param pCommand Pointer to a MciCmd instance.
//------------------------------------------------------------------------------
unsigned char MCI_IsTxComplete(MciCmd *pCommand)
{
if (pCommand->status != MCI_STATUS_PENDING) {
if (pCommand->status != 0)
printf("MCI_IsTxComplete %d\n\r", pCommand->status);
return 1;
}
else {
return 0;
}
}
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/mci/mci.c | C | oos | 19,631 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include "aic.h"
#include <board.h>
//------------------------------------------------------------------------------
// Exported functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// Configures the interrupt associated with the given source, using the
/// specified mode and interrupt handler.
/// \param source Interrupt source to configure.
/// \param mode Triggering mode of the interrupt.
/// \param handler Interrupt handler function.
//------------------------------------------------------------------------------
void AIC_ConfigureIT(unsigned int source,
unsigned int mode,
void (*handler)( void ))
{
// Disable the interrupt first
AT91C_BASE_AIC->AIC_IDCR = 1 << source;
// Configure mode and handler
AT91C_BASE_AIC->AIC_SMR[source] = mode;
AT91C_BASE_AIC->AIC_SVR[source] = (unsigned int) handler;
// Clear interrupt
AT91C_BASE_AIC->AIC_ICCR = 1 << source;
}
//------------------------------------------------------------------------------
/// Enables interrupts coming from the given (unique) source.
/// \param source Interrupt source to enable.
//------------------------------------------------------------------------------
void AIC_EnableIT(unsigned int source)
{
AT91C_BASE_AIC->AIC_IECR = 1 << source;
}
//------------------------------------------------------------------------------
/// Disables interrupts coming from the given (unique) source.
/// \param source Interrupt source to enable.
//------------------------------------------------------------------------------
void AIC_DisableIT(unsigned int source)
{
AT91C_BASE_AIC->AIC_IDCR = 1 << source;
}
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/aic/aic.c | C | oos | 3,615 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
/// \dir
/// !Purpose
///
/// Methods and definitions for configuring interrupts using the Advanced
/// Interrupt Controller (AIC).
///
/// !Usage
/// -# Configure an interrupt source using AIC_ConfigureIT
/// -# Enable or disable interrupt generation of a particular source with
/// AIC_EnableIT and AIC_DisableIT.
//------------------------------------------------------------------------------
#ifndef AIC_H
#define AIC_H
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include <board.h>
//------------------------------------------------------------------------------
// Definitions
//------------------------------------------------------------------------------
#ifndef AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL
/// Redefinition of missing constant.
#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE
#endif
//------------------------------------------------------------------------------
// Global functions
//------------------------------------------------------------------------------
extern void AIC_ConfigureIT(unsigned int source,
unsigned int mode,
void (*handler)( void ));
extern void AIC_EnableIT(unsigned int source);
extern void AIC_DisableIT(unsigned int source);
#endif //#ifndef AIC_H
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/aic/aic.h | C | oos | 3,168 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/// Disable traces for this file
#ifndef NOTRACE
#define NOTRACE
#endif
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include "pio_it.h"
#include "pio.h"
#include <aic/aic.h>
#include <board.h>
#include <utility/assert.h>
#include <utility/trace.h>
//------------------------------------------------------------------------------
// Local definitions
//------------------------------------------------------------------------------
/// Returns the current value of a register.
#define READ(peripheral, register) (peripheral->register)
/// Modifies the current value of a register.
#define WRITE(peripheral, register, value) (peripheral->register = value)
/// Maximum number of interrupt sources that can be defined.
#define MAX_INTERRUPT_SOURCES 7
//------------------------------------------------------------------------------
// Local types
//------------------------------------------------------------------------------
/// Describes a PIO interrupt source, including the PIO instance triggering the
/// interrupt and the associated interrupt handler.
typedef struct _InterruptSource {
/// Interrupt source pin.
const Pin *pPin;
/// Interrupt handler.
void (*handler)(const Pin *);
} InterruptSource;
//------------------------------------------------------------------------------
// Local variables
//------------------------------------------------------------------------------
/// List of interrupt sources.
static InterruptSource pSources[MAX_INTERRUPT_SOURCES];
/// Number of currently defined interrupt sources.
static unsigned int numSources;
//------------------------------------------------------------------------------
// Local functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// Handles all interrupts on the given PIO controller.
/// \param id PIO controller ID.
/// \param pBase PIO controller base address.
//------------------------------------------------------------------------------
void PioInterruptHandler(unsigned int id, AT91S_PIO *pBase)
{
unsigned int status;
unsigned int i;
// Check PIO controller status
status = pBase->PIO_ISR;
status &= pBase->PIO_IMR;
if (status != 0) {
trace_LOG(trace_DEBUG, "-D- PIO interrupt on PIO controller #%d\n\r", id);
// Check all sources
i = 0;
while (status != 0) {
// There cannot be an unconfigured source enabled.
SANITY_CHECK(i < numSources);
// Source if configured on PIOA
if (pSources[i].pPin->id == id) {
// Source has PIOs which have changed
if ((status & pSources[i].pPin->mask) != 0) {
trace_LOG(trace_DEBUG, "-D- Interrupt source #%d triggered\n\r", i);
pSources[i].handler(pSources[i].pPin);
status &= ~(pSources[i].pPin->mask);
}
}
i++;
}
}
}
//------------------------------------------------------------------------------
/// Generic PIO interrupt handler. Single entry point for interrupts coming
/// from any PIO controller (PIO A, B, C ...). Dispatches the interrupt to
/// the user-configured handlers.
//------------------------------------------------------------------------------
void InterruptHandler()
{
#if defined(AT91C_ID_PIOA)
// Treat PIOA interrupts
PioInterruptHandler(AT91C_ID_PIOA, AT91C_BASE_PIOA);
#endif
#if defined(AT91C_ID_PIOB)
// Treat PIOB interrupts
PioInterruptHandler(AT91C_ID_PIOB, AT91C_BASE_PIOB);
#endif
#if defined(AT91C_ID_PIOC)
// Treat PIOC interrupts
PioInterruptHandler(AT91C_ID_PIOC, AT91C_BASE_PIOC);
#endif
#if defined(AT91C_ID_PIOD)
// Treat PIOD interrupts
PioInterruptHandler(AT91C_ID_PIOD, AT91C_BASE_PIOD);
#endif
#if defined(AT91C_ID_PIOE)
// Treat PIOE interrupts
PioInterruptHandler(AT91C_ID_PIOE, AT91C_BASE_PIOE);
#endif
#if defined(AT91C_ID_PIOABCD)
// Treat PIOABCD interrupts
#if !defined(AT91C_ID_PIOA)
PioInterruptHandler(AT91C_ID_PIOABCD, AT91C_BASE_PIOA);
#endif
#if !defined(AT91C_ID_PIOB)
PioInterruptHandler(AT91C_ID_PIOABCD, AT91C_BASE_PIOB);
#endif
#if !defined(AT91C_ID_PIOC)
PioInterruptHandler(AT91C_ID_PIOABCD, AT91C_BASE_PIOC);
#endif
#if !defined(AT91C_ID_PIOD)
PioInterruptHandler(AT91C_ID_PIOABCD, AT91C_BASE_PIOD);
#endif
#endif
#if defined(AT91C_ID_PIOABCDE)
// Treat PIOABCDE interrupts
#if !defined(AT91C_ID_PIOA)
PioInterruptHandler(AT91C_ID_PIOABCDE, AT91C_BASE_PIOA);
#endif
#if !defined(AT91C_ID_PIOB)
PioInterruptHandler(AT91C_ID_PIOABCDE, AT91C_BASE_PIOB);
#endif
#if !defined(AT91C_ID_PIOC)
PioInterruptHandler(AT91C_ID_PIOABCDE, AT91C_BASE_PIOC);
#endif
#if !defined(AT91C_ID_PIOD)
PioInterruptHandler(AT91C_ID_PIOABCDE, AT91C_BASE_PIOD);
#endif
#if !defined(AT91C_ID_PIOE)
PioInterruptHandler(AT91C_ID_PIOABCDE, AT91C_BASE_PIOE);
#endif
#endif
#if defined(AT91C_ID_PIOCDE)
// Treat PIOCDE interrupts
#if !defined(AT91C_ID_PIOC)
PioInterruptHandler(AT91C_ID_PIOCDE, AT91C_BASE_PIOC);
#endif
#if !defined(AT91C_ID_PIOD)
PioInterruptHandler(AT91C_ID_PIOCDE, AT91C_BASE_PIOD);
#endif
#if !defined(AT91C_ID_PIOE)
PioInterruptHandler(AT91C_ID_PIOCDE, AT91C_BASE_PIOE);
#endif
#endif
}
//------------------------------------------------------------------------------
// Global functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// Initializes the PIO interrupt management logic.
/// \param priority PIO controller interrupts priority.
//------------------------------------------------------------------------------
void PIO_InitializeInterrupts(unsigned int priority)
{
trace_LOG(trace_DEBUG, "-D- PIO_Initialize()\n\r");
SANITY_CHECK((priority & ~AT91C_AIC_PRIOR) == 0);
// Reset sources
numSources = 0;
#ifdef AT91C_ID_PIOA
// Configure PIO interrupt sources
trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOA\n\r");
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOA;
AT91C_BASE_PIOA->PIO_ISR;
AT91C_BASE_PIOA->PIO_IDR = 0xFFFFFFFF;
AIC_ConfigureIT(AT91C_ID_PIOA, priority, InterruptHandler);
AIC_EnableIT(AT91C_ID_PIOA);
#endif
#ifdef AT91C_ID_PIOB
trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOB\n\r");
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOB;
AT91C_BASE_PIOB->PIO_ISR;
AT91C_BASE_PIOB->PIO_IDR = 0xFFFFFFFF;
AIC_ConfigureIT(AT91C_ID_PIOB, priority, InterruptHandler);
AIC_EnableIT(AT91C_ID_PIOB);
#endif
#ifdef AT91C_ID_PIOC
trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOC\n\r");
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOC;
AT91C_BASE_PIOC->PIO_ISR;
AT91C_BASE_PIOC->PIO_IDR = 0xFFFFFFFF;
AIC_ConfigureIT(AT91C_ID_PIOC, priority, InterruptHandler);
AIC_EnableIT(AT91C_ID_PIOC);
#endif
#ifdef AT91C_ID_PIOD
trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOD\n\r");
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOD;
AT91C_BASE_PIOC->PIO_ISR;
AT91C_BASE_PIOC->PIO_IDR = 0xFFFFFFFF;
AIC_ConfigureIT(AT91C_ID_PIOD, priority, InterruptHandler);
AIC_EnableIT(AT91C_ID_PIOD);
#endif
#ifdef AT91C_ID_PIOE
trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOE\n\r");
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOE;
AT91C_BASE_PIOC->PIO_ISR;
AT91C_BASE_PIOC->PIO_IDR = 0xFFFFFFFF;
AIC_ConfigureIT(AT91C_ID_PIOE, priority, InterruptHandler);
AIC_EnableIT(AT91C_ID_PIOE);
#endif
#if defined(AT91C_ID_PIOABCD)
// Treat PIOABCD interrupts
#if !defined(AT91C_ID_PIOA) \
&& !defined(AT91C_ID_PIOB) \
&& !defined(AT91C_ID_PIOC) \
&& !defined(AT91C_ID_PIOD)
trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOABCD\n\r");
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCD;
AT91C_BASE_PIOA->PIO_ISR;
AT91C_BASE_PIOA->PIO_IDR = 0xFFFFFFFF;
AIC_ConfigureIT(AT91C_ID_PIOABCD, priority, InterruptHandler);
AIC_EnableIT(AT91C_ID_PIOABCD);
#endif
#endif
#if defined(AT91C_ID_PIOABCDE)
// Treat PIOABCDE interrupts
#if !defined(AT91C_ID_PIOA) \
&& !defined(AT91C_ID_PIOB) \
&& !defined(AT91C_ID_PIOC) \
&& !defined(AT91C_ID_PIOD) \
&& !defined(AT91C_ID_PIOE)
trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOABCDE\n\r");
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCDE;
AT91C_BASE_PIOA->PIO_ISR;
AT91C_BASE_PIOA->PIO_IDR = 0xFFFFFFFF;
AIC_ConfigureIT(AT91C_ID_PIOABCDE, priority, InterruptHandler);
AIC_EnableIT(AT91C_ID_PIOABCDE);
#endif
#endif
#if defined(AT91C_ID_PIOCDE)
// Treat PIOCDE interrupts
#if !defined(AT91C_ID_PIOC) \
&& !defined(AT91C_ID_PIOD) \
&& !defined(AT91C_ID_PIOE)
trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOC\n\r");
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOCDE;
AT91C_BASE_PIOC->PIO_ISR;
AT91C_BASE_PIOC->PIO_IDR = 0xFFFFFFFF;
AIC_ConfigureIT(AT91C_ID_PIOCDE, priority, InterruptHandler);
AIC_EnableIT(AT91C_ID_PIOCDE);
#endif
#endif
}
//------------------------------------------------------------------------------
/// Configures an interrupt source.
/// \param pPin Interrupt source.
/// \param handler Desired interrupt handler for the source.
//------------------------------------------------------------------------------
void PIO_ConfigureIt(const Pin *pPin, void (*handler)(const Pin *))
{
InterruptSource *pSource;
trace_LOG(trace_DEBUG, "-D- PIO_ConfigureIt()\n\r");
SANITY_CHECK(pPin);
ASSERT(numSources < MAX_INTERRUPT_SOURCES,
"-F- PIO_ConfigureIt: Increase MAX_INTERRUPT_SOURCES\n\r");
// Define new source
trace_LOG(trace_DEBUG, "-D- PIO_ConfigureIt: Defining new source #%d.\n\r", numSources);
pSource = &(pSources[numSources]);
pSource->pPin = pPin;
pSource->handler = handler;
numSources++;
}
//------------------------------------------------------------------------------
/// Enables the given interrupt source if it has been configured.
/// \param pPin Interrupt source to enable.
//------------------------------------------------------------------------------
void PIO_EnableIt(const Pin *pPin)
{
trace_LOG(trace_DEBUG, "-D- PIO_EnableIt()\n\r");
SANITY_CHECK(pPin);
#ifndef NOASSERT
unsigned int i = 0;
unsigned char found = 0;
while ((i < numSources) && !found) {
if (pSources[i].pPin == pPin) {
found = 1;
}
i++;
}
ASSERT(found, "-F- PIO_EnableIt: Interrupt source has not been configured\n\r");
#endif
pPin->pio->PIO_ISR;
pPin->pio->PIO_IER = pPin->mask;
}
//------------------------------------------------------------------------------
/// Disables a given interrupt source.
/// \param pPin Interrupt source to disable.
//------------------------------------------------------------------------------
void PIO_DisableIt(const Pin *pPin)
{
SANITY_CHECK(pPin);
trace_LOG(trace_DEBUG, "-D- PIO_DisableIt()\n\r");
pPin->pio->PIO_IDR = pPin->mask;
}
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/pio/pio_it.c | C | oos | 13,582 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
/// \dir
/// !Purpose
///
/// Definition of methods and structures for using PIOs in a transparent
/// way. The main purpose is to allow portability between several boards.
///
/// !Usage
///
/// -# To configure and use pins, see pio.h.
/// -# To enable and use interrupt generation on PIO status change, see
/// pio_it.h.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// \unit
/// !Purpose
///
/// Simple & portable usage of PIO pins.
///
/// !Usage
///
/// -# Define a constant pin description array such as the following one:
/// \code
/// const Pin at91board_dbgu[] = {
/// {AT91C_BASE_PIOA, (1 << 30), PIO_PERIPH_A, PIO_DEFAULT},
/// {AT91C_BASE_PIOA, (1 << 31), PIO_PERIPH_A, PIO_DEFAULT},
/// };
/// \endcode
/// Alternatively, constants defined in the piodefs.h header file of the
/// board module can be used:
/// \code
/// const Pin at91board_dbgu[] = {PINS_DBGU};
/// const Pin at91board_usart[] = {PIN_USART0_RXD, PIN_USART0_TXD};
/// \endcode
/// It is possible to group multiple pins if they share the same
/// attributes, to save memory. Here is the previous DBGU example
/// rewritten in such a way:
/// \code
/// const Pin at91board_dbgu[] = {
/// {AT91C_BASE_PIOA, 0xC0000000, PIO_PERIPH_A, PIO_DEFAULT}
/// };
/// \endcode
/// -# For pins configured as inputs, the PIO controller must be enabled
/// in the PMC (*enabled by PIO_Configure at the moment*).
/// -# Configure a pin array by calling PIO_Configure, using
/// the PIO_LISTSIZE macro to calculate the array size if needed. Do not
/// forget to check the return value for any error.
/// -# Set and get the value of a pin using the PIO_Set, PIO_Clear and
/// PIO_Get methods.
//------------------------------------------------------------------------------
#ifndef PIO_H
#define PIO_H
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include <board.h>
//------------------------------------------------------------------------------
// Definitions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// \page "Pin types"
/// This page lists the available types for a Pin instance (in its type field).
/// !Types
/// - PIO_PERIPH_A
/// - PIO_PERIPH_B
/// - PIO_INPUT
/// - PIO_OUTPUT_0
/// - PIO_OUTPUT_1
/// The pin is controlled by the associated signal of peripheral A.
#define PIO_PERIPH_A 0
/// The pin is controlled by the associated signal of peripheral B.
#define PIO_PERIPH_B 1
/// The pin is an input.
#define PIO_INPUT 2
/// The pin is an output and has a default level of 0.
#define PIO_OUTPUT_0 3
/// The pin is an output and has a default level of 1.
#define PIO_OUTPUT_1 4
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// \page "Pin attributes"
/// This page lists the valid values for the attribute field of a Pin instance.
/// !Attributes
/// - PIO_DEFAULT
/// - PIO_PULLUP
/// - PIO_DEGLITCH
/// - PIO_OPENDRAIN
/// Default pin configuration (no attribute).
#define PIO_DEFAULT (0 << 0)
/// The internal pin pull-up is active.
#define PIO_PULLUP (1 << 0)
/// The internal glitch filter is active.
#define PIO_DEGLITCH (1 << 1)
/// The pin is open-drain.
#define PIO_OPENDRAIN (1 << 2)
//------------------------------------------------------------------------------
/// Calculates the size of a Pin instances array. The array must be local (i.e.
/// not a pointer), otherwise the computation will not be correct.
#define PIO_LISTSIZE(list) (sizeof(list) / sizeof(Pin))
//------------------------------------------------------------------------------
// Types
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// Describes the type and attribute of one PIO pin or a group of similar pins.
typedef struct {
/// Bitmask indicating which pin(s) to configure.
unsigned int mask;
/// Pointer to the PIO controller which has the pin(s).
AT91S_PIO *pio;
/// Peripheral ID of the PIO controller which has the pin(s).
unsigned char id;
/// Pin type (see "Pin types").
unsigned char type;
/// Pin attribute (see "Pin attributes").
unsigned char attribute;
} Pin;
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Exported functions
//------------------------------------------------------------------------------
extern unsigned char PIO_Configure(const Pin *list, unsigned int size);
extern void PIO_Set(const Pin *pin );
extern void PIO_Clear(const Pin *pin);
extern unsigned char PIO_Get(const Pin *pin);
extern unsigned int PIO_GetISR(const Pin *pin);
extern unsigned char PIO_GetOutputDataStatus(const Pin *pin);
#endif //#ifndef PIO_H
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/pio/pio.h | C | oos | 7,276 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include "pio.h"
#include <board.h>
//------------------------------------------------------------------------------
// Internal definitions
//------------------------------------------------------------------------------
/// \internal Returns the current value of a register.
#define READ(peripheral, register) (peripheral->register)
/// \internal Modifies the current value of a register.
#define WRITE(peripheral, register, value) (peripheral->register = value)
//------------------------------------------------------------------------------
// Internal functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// Configures one or more pin(s) of a PIO controller as being controlled by
/// peripheral A. Optionally, the corresponding internal pull-up(s) can be
/// enabled.
/// \param pio Pointer to a PIO controller.
/// \param mask Bitmask of one or more pin(s) to configure.
/// \param enablePullUp Indicates if the pin(s) internal pull-up shall be
/// configured.
//------------------------------------------------------------------------------
static void PIO_SetPeripheralA(AT91S_PIO *pio,
unsigned int mask,
unsigned char enablePullUp)
{
// Disable interrupts on the pin(s)
WRITE(pio, PIO_IDR, mask);
// Enable the pull-up(s) if necessary
if (enablePullUp) {
WRITE(pio, PIO_PPUER, mask);
}
else {
WRITE(pio, PIO_PPUDR, mask);
}
// Configure pin
WRITE(pio, PIO_ASR, mask);
WRITE(pio, PIO_PDR, mask);
}
//------------------------------------------------------------------------------
/// Configures one or more pin(s) of a PIO controller as being controlled by
/// peripheral A. Optionally, the corresponding internal pull-up(s) can be
/// enabled.
/// \param pio Pointer to a PIO controller.
/// \param mask Bitmask of one or more pin(s) to configure.
/// \param enablePullUp Indicates if the pin(s) internal pull-up shall be
/// configured.
//------------------------------------------------------------------------------
static void PIO_SetPeripheralB(AT91S_PIO *pio,
unsigned int mask,
unsigned char enablePullUp)
{
// Disable interrupts on the pin(s)
WRITE(pio, PIO_IDR, mask);
// Enable the pull-up(s) if necessary
if (enablePullUp) {
WRITE(pio, PIO_PPUER, mask);
}
else {
WRITE(pio, PIO_PPUDR, mask);
}
// Configure pin
WRITE(pio, PIO_BSR, mask);
WRITE(pio, PIO_PDR, mask);
}
//------------------------------------------------------------------------------
/// Configures one or more pin(s) or a PIO controller as inputs. Optionally,
/// the corresponding internal pull-up(s) and glitch filter(s) can be
/// enabled.
/// \param pio Pointer to a PIO controller.
/// \param mask Bitmask indicating which pin(s) to configure as input(s).
/// \param enablePullUp Indicates if the internal pull-up(s) must be enabled.
/// \param enableFilter Indicates if the glitch filter(s) must be enabled.
//------------------------------------------------------------------------------
static void PIO_SetInput(AT91S_PIO *pio,
unsigned int mask,
unsigned char enablePullUp,
unsigned char enableFilter)
{
// Disable interrupts
WRITE(pio, PIO_IDR, mask);
// Enable pull-up(s) if necessary
if (enablePullUp) {
WRITE(pio, PIO_PPUER, mask);
}
else {
WRITE(pio, PIO_PPUDR, mask);
}
// Enable filter(s) if necessary
if (enableFilter) {
WRITE(pio, PIO_IFER, mask);
}
else {
WRITE(pio, PIO_IFDR, mask);
}
// Configure pin as input
WRITE(pio, PIO_ODR, mask);
WRITE(pio, PIO_PER, mask);
}
//------------------------------------------------------------------------------
/// Configures one or more pin(s) of a PIO controller as outputs, with the
/// given default value. Optionally, the multi-drive feature can be enabled
/// on the pin(s).
/// \param pio Pointer to a PIO controller.
/// \param mask Bitmask indicating which pin(s) to configure.
/// \param defaultValue Default level on the pin(s).
/// \param enableMultiDrive Indicates if the pin(s) shall be configured as
/// open-drain.
/// \param enablePullUp Indicates if the pin shall have its pull-up activated.
//------------------------------------------------------------------------------
static void PIO_SetOutput(AT91S_PIO *pio,
unsigned int mask,
unsigned char defaultValue,
unsigned char enableMultiDrive,
unsigned char enablePullUp)
{
// Disable interrupts
WRITE(pio, PIO_IDR, mask);
// Enable pull-up(s) if necessary
if (enablePullUp) {
WRITE(pio, PIO_PPUER, mask);
}
else {
WRITE(pio, PIO_PPUDR, mask);
}
// Enable multi-drive if necessary
if (enableMultiDrive) {
WRITE(pio, PIO_MDER, mask);
}
else {
WRITE(pio, PIO_MDDR, mask);
}
// Set default value
if (defaultValue) {
WRITE(pio, PIO_SODR, mask);
}
else {
WRITE(pio, PIO_CODR, mask);
}
// Configure pin(s) as output(s)
WRITE(pio, PIO_OER, mask);
WRITE(pio, PIO_PER, mask);
}
//------------------------------------------------------------------------------
// Exported functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
/// Configures a list of Pin instances, which can either hold a single pin or a
/// group of pins, depending on the mask value; all pins are configured by this
/// function.
/// Returns 1 if the configuration has been performed successfully; otherwise 0.
/// \param list Pointer to a list of Pin instances.
/// \param size Size of the Pin list (see <PIO_LISTSIZE>).
//------------------------------------------------------------------------------
unsigned char PIO_Configure(const Pin *list, unsigned int size)
{
// Configure pins
while (size > 0) {
switch (list->type) {
case PIO_PERIPH_A:
PIO_SetPeripheralA(list->pio,
list->mask,
(list->attribute & PIO_PULLUP) ? 1 : 0);
break;
case PIO_PERIPH_B:
PIO_SetPeripheralB(list->pio,
list->mask,
(list->attribute & PIO_PULLUP) ? 1 : 0);
break;
case PIO_INPUT:
AT91C_BASE_PMC->PMC_PCER = 1 << list->id;
PIO_SetInput(list->pio,
list->mask,
(list->attribute & PIO_PULLUP) ? 1 : 0,
(list->attribute & PIO_DEGLITCH)? 1 : 0);
break;
case PIO_OUTPUT_0:
case PIO_OUTPUT_1:
PIO_SetOutput(list->pio,
list->mask,
(list->type == PIO_OUTPUT_1),
(list->attribute & PIO_OPENDRAIN) ? 1 : 0,
(list->attribute & PIO_PULLUP) ? 1 : 0);
break;
default: return 0;
}
list++;
size--;
}
return 1;
}
//------------------------------------------------------------------------------
/// Sets a high output level on one or more pin(s) (if configured as output(s)).
/// \param pin Pointer to a Pin instance describing one or more pins.
//------------------------------------------------------------------------------
void PIO_Set(const Pin *pin)
{
WRITE(pin->pio, PIO_SODR, pin->mask);
}
//------------------------------------------------------------------------------
/// Sets a low output level on one or more pin(s) (if configured as output(s)).
/// \param pin Pointer to a Pin instance describing one or more pins.
//------------------------------------------------------------------------------
void PIO_Clear(const Pin *pin)
{
WRITE(pin->pio, PIO_CODR, pin->mask);
}
//------------------------------------------------------------------------------
/// Returns 1 if one or more PIO of the given Pin instance currently have a high
/// level; otherwise returns 0.
/// \param pin Pointer to a Pin instance describing one or more pins.
//------------------------------------------------------------------------------
unsigned char PIO_Get(const Pin *pin)
{
unsigned int reg;
if ((pin->type == PIO_OUTPUT_0) || (pin->type == PIO_OUTPUT_1)) {
reg = READ(pin->pio, PIO_ODSR);
}
else {
reg = READ(pin->pio, PIO_PDSR);
}
if ((reg & pin->mask) == 0) {
return 0;
}
else {
return 1;
}
}
//------------------------------------------------------------------------------
/// Returns 1 if one or more PIO of the given Pin data to be driven on the I/O line
/// level; otherwise returns 0.
/// \param pin Pointer to a Pin instance describing one or more pins.
//------------------------------------------------------------------------------
unsigned char PIO_GetOutputDataStatus(const Pin *pin)
{
if ((READ(pin->pio, PIO_ODSR) & pin->mask) == 0) {
return 0;
}
else {
return 1;
}
}
//------------------------------------------------------------------------------
/// Returns the value of ISR for the PIO controller of the pin.
/// Reading this register acknoledges all the ITs.
/// \param pin Pointer to a Pin instance describing one or more pins.
//------------------------------------------------------------------------------
unsigned int PIO_GetISR(const Pin *pin)
{
return (READ(pin->pio, PIO_ISR));
}
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/pio/pio.c | C | oos | 12,227 |
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
/// \unit
/// !Purpose
///
/// Configuration and handling of interrupts on PIO status changes.
///
/// !Usage
///
/// -# Configure an status change interrupt on one or more pin(s) with
/// PIO_ConfigureIt.
/// -# Enable & disable interrupts on pins using PIO_EnableIt and
/// PIO_DisableIt.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include "pio.h"
//------------------------------------------------------------------------------
// Global functions
//------------------------------------------------------------------------------
extern void PIO_InitializeInterrupts(unsigned int priority);
extern void PIO_ConfigureIt(const Pin *pPin, void (*handler)(const Pin *));
extern void PIO_EnableIt(const Pin *pPin);
extern void PIO_DisableIt(const Pin *pPin);
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/drivers/Atmel/at91lib/peripherals/pio/pio_it.h | C | oos | 2,685 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/*
* The first test creates three tasks - two counter tasks (one continuous count
* and one limited count) and one controller. A "count" variable is shared
* between all three tasks. The two counter tasks should never be in a "ready"
* state at the same time. The controller task runs at the same priority as
* the continuous count task, and at a lower priority than the limited count
* task.
*
* One counter task loops indefinitely, incrementing the shared count variable
* on each iteration. To ensure it has exclusive access to the variable it
* raises it's priority above that of the controller task before each
* increment, lowering it again to it's original priority before starting the
* next iteration.
*
* The other counter task increments the shared count variable on each
* iteration of it's loop until the count has reached a limit of 0xff - at
* which point it suspends itself. It will not start a new loop until the
* controller task has made it "ready" again by calling vTaskResume ().
* This second counter task operates at a higher priority than controller
* task so does not need to worry about mutual exclusion of the counter
* variable.
*
* The controller task is in two sections. The first section controls and
* monitors the continuous count task. When this section is operational the
* limited count task is suspended. Likewise, the second section controls
* and monitors the limited count task. When this section is operational the
* continuous count task is suspended.
*
* In the first section the controller task first takes a copy of the shared
* count variable. To ensure mutual exclusion on the count variable it
* suspends the continuous count task, resuming it again when the copy has been
* taken. The controller task then sleeps for a fixed period - during which
* the continuous count task will execute and increment the shared variable.
* When the controller task wakes it checks that the continuous count task
* has executed by comparing the copy of the shared variable with its current
* value. This time, to ensure mutual exclusion, the scheduler itself is
* suspended with a call to vTaskSuspendAll (). This is for demonstration
* purposes only and is not a recommended technique due to its inefficiency.
*
* After a fixed number of iterations the controller task suspends the
* continuous count task, and moves on to its second section.
*
* At the start of the second section the shared variable is cleared to zero.
* The limited count task is then woken from it's suspension by a call to
* vTaskResume (). As this counter task operates at a higher priority than
* the controller task the controller task should not run again until the
* shared variable has been counted up to the limited value causing the counter
* task to suspend itself. The next line after vTaskResume () is therefore
* a check on the shared variable to ensure everything is as expected.
*
*
* The second test consists of a couple of very simple tasks that post onto a
* queue while the scheduler is suspended. This test was added to test parts
* of the scheduler not exercised by the first test.
*
*/
#include <stdlib.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
/* Demo app include files. */
#include "dynamic.h"
/* Function that implements the "limited count" task as described above. */
static portTASK_FUNCTION_PROTO( vLimitedIncrementTask, pvParameters );
/* Function that implements the "continuous count" task as described above. */
static portTASK_FUNCTION_PROTO( vContinuousIncrementTask, pvParameters );
/* Function that implements the controller task as described above. */
static portTASK_FUNCTION_PROTO( vCounterControlTask, pvParameters );
static portTASK_FUNCTION_PROTO( vQueueReceiveWhenSuspendedTask, pvParameters );
static portTASK_FUNCTION_PROTO( vQueueSendWhenSuspendedTask, pvParameters );
/* Demo task specific constants. */
#define priSTACK_SIZE ( configMINIMAL_STACK_SIZE )
#define priSLEEP_TIME ( ( portTickType ) 128 / portTICK_RATE_MS )
#define priLOOPS ( 5 )
#define priMAX_COUNT ( ( unsigned long ) 0xff )
#define priNO_BLOCK ( ( portTickType ) 0 )
#define priSUSPENDED_QUEUE_LENGTH ( 1 )
/*-----------------------------------------------------------*/
/* Handles to the two counter tasks. These could be passed in as parameters
to the controller task to prevent them having to be file scope. */
static xTaskHandle xContinousIncrementHandle, xLimitedIncrementHandle;
/* The shared counter variable. This is passed in as a parameter to the two
counter variables for demonstration purposes. */
static unsigned long ulCounter;
/* Variables used to check that the tasks are still operating without error.
Each complete iteration of the controller task increments this variable
provided no errors have been found. The variable maintaining the same value
is therefore indication of an error. */
static volatile unsigned short usCheckVariable = ( unsigned short ) 0;
static volatile portBASE_TYPE xSuspendedQueueSendError = pdFALSE;
static volatile portBASE_TYPE xSuspendedQueueReceiveError = pdFALSE;
/* Queue used by the second test. */
xQueueHandle xSuspendedTestQueue;
/*-----------------------------------------------------------*/
/*
* Start the three tasks as described at the top of the file.
* Note that the limited count task is given a higher priority.
*/
void vStartDynamicPriorityTasks( void )
{
xSuspendedTestQueue = xQueueCreate( priSUSPENDED_QUEUE_LENGTH, sizeof( unsigned long ) );
/* vQueueAddToRegistry() adds the queue to the queue registry, if one is
in use. The queue registry is provided as a means for kernel aware
debuggers to locate queues and has no purpose if a kernel aware debugger
is not being used. The call to vQueueAddToRegistry() will be removed
by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is
defined to be less than 1. */
vQueueAddToRegistry( xSuspendedTestQueue, ( signed char * ) "Suspended_Test_Queue" );
xTaskCreate( vContinuousIncrementTask, ( signed char * ) "CNT_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY, &xContinousIncrementHandle );
xTaskCreate( vLimitedIncrementTask, ( signed char * ) "LIM_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY + 1, &xLimitedIncrementHandle );
xTaskCreate( vCounterControlTask, ( signed char * ) "C_CTRL", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
xTaskCreate( vQueueSendWhenSuspendedTask, ( signed char * ) "SUSP_TX", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
xTaskCreate( vQueueReceiveWhenSuspendedTask, ( signed char * ) "SUSP_RX", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
}
/*-----------------------------------------------------------*/
/*
* Just loops around incrementing the shared variable until the limit has been
* reached. Once the limit has been reached it suspends itself.
*/
static portTASK_FUNCTION( vLimitedIncrementTask, pvParameters )
{
unsigned long *pulCounter;
/* Take a pointer to the shared variable from the parameters passed into
the task. */
pulCounter = ( unsigned long * ) pvParameters;
/* This will run before the control task, so the first thing it does is
suspend - the control task will resume it when ready. */
vTaskSuspend( NULL );
for( ;; )
{
/* Just count up to a value then suspend. */
( *pulCounter )++;
if( *pulCounter >= priMAX_COUNT )
{
vTaskSuspend( NULL );
}
}
}
/*-----------------------------------------------------------*/
/*
* Just keep counting the shared variable up. The control task will suspend
* this task when it wants.
*/
static portTASK_FUNCTION( vContinuousIncrementTask, pvParameters )
{
unsigned long *pulCounter;
unsigned portBASE_TYPE uxOurPriority;
/* Take a pointer to the shared variable from the parameters passed into
the task. */
pulCounter = ( unsigned long * ) pvParameters;
/* Query our priority so we can raise it when exclusive access to the
shared variable is required. */
uxOurPriority = uxTaskPriorityGet( NULL );
for( ;; )
{
/* Raise our priority above the controller task to ensure a context
switch does not occur while we are accessing this variable. */
vTaskPrioritySet( NULL, uxOurPriority + 1 );
( *pulCounter )++;
vTaskPrioritySet( NULL, uxOurPriority );
}
}
/*-----------------------------------------------------------*/
/*
* Controller task as described above.
*/
static portTASK_FUNCTION( vCounterControlTask, pvParameters )
{
unsigned long ulLastCounter;
short sLoops;
short sError = pdFALSE;
/* Just to stop warning messages. */
( void ) pvParameters;
for( ;; )
{
/* Start with the counter at zero. */
ulCounter = ( unsigned long ) 0;
/* First section : */
/* Check the continuous count task is running. */
for( sLoops = 0; sLoops < priLOOPS; sLoops++ )
{
/* Suspend the continuous count task so we can take a mirror of the
shared variable without risk of corruption. */
vTaskSuspend( xContinousIncrementHandle );
ulLastCounter = ulCounter;
vTaskResume( xContinousIncrementHandle );
/* Now delay to ensure the other task has processor time. */
vTaskDelay( priSLEEP_TIME );
/* Check the shared variable again. This time to ensure mutual
exclusion the whole scheduler will be locked. This is just for
demo purposes! */
vTaskSuspendAll();
{
if( ulLastCounter == ulCounter )
{
/* The shared variable has not changed. There is a problem
with the continuous count task so flag an error. */
sError = pdTRUE;
}
}
xTaskResumeAll();
}
/* Second section: */
/* Suspend the continuous counter task so it stops accessing the shared variable. */
vTaskSuspend( xContinousIncrementHandle );
/* Reset the variable. */
ulCounter = ( unsigned long ) 0;
/* Resume the limited count task which has a higher priority than us.
We should therefore not return from this call until the limited count
task has suspended itself with a known value in the counter variable. */
vTaskResume( xLimitedIncrementHandle );
/* Does the counter variable have the expected value? */
if( ulCounter != priMAX_COUNT )
{
sError = pdTRUE;
}
if( sError == pdFALSE )
{
/* If no errors have occurred then increment the check variable. */
portENTER_CRITICAL();
usCheckVariable++;
portEXIT_CRITICAL();
}
/* Resume the continuous count task and do it all again. */
vTaskResume( xContinousIncrementHandle );
}
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vQueueSendWhenSuspendedTask, pvParameters )
{
static unsigned long ulValueToSend = ( unsigned long ) 0;
/* Just to stop warning messages. */
( void ) pvParameters;
for( ;; )
{
vTaskSuspendAll();
{
/* We must not block while the scheduler is suspended! */
if( xQueueSend( xSuspendedTestQueue, ( void * ) &ulValueToSend, priNO_BLOCK ) != pdTRUE )
{
xSuspendedQueueSendError = pdTRUE;
}
}
xTaskResumeAll();
vTaskDelay( priSLEEP_TIME );
++ulValueToSend;
}
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vQueueReceiveWhenSuspendedTask, pvParameters )
{
static unsigned long ulExpectedValue = ( unsigned long ) 0, ulReceivedValue;
portBASE_TYPE xGotValue;
/* Just to stop warning messages. */
( void ) pvParameters;
for( ;; )
{
do
{
/* Suspending the scheduler here is fairly pointless and
undesirable for a normal application. It is done here purely
to test the scheduler. The inner xTaskResumeAll() should
never return pdTRUE as the scheduler is still locked by the
outer call. */
vTaskSuspendAll();
{
vTaskSuspendAll();
{
xGotValue = xQueueReceive( xSuspendedTestQueue, ( void * ) &ulReceivedValue, priNO_BLOCK );
}
if( xTaskResumeAll() )
{
xSuspendedQueueReceiveError = pdTRUE;
}
}
xTaskResumeAll();
#if configUSE_PREEMPTION == 0
{
taskYIELD();
}
#endif
} while( xGotValue == pdFALSE );
if( ulReceivedValue != ulExpectedValue )
{
xSuspendedQueueReceiveError = pdTRUE;
}
++ulExpectedValue;
}
}
/*-----------------------------------------------------------*/
/* Called to check that all the created tasks are still running without error. */
portBASE_TYPE xAreDynamicPriorityTasksStillRunning( void )
{
/* Keep a history of the check variables so we know if it has been incremented
since the last call. */
static unsigned short usLastTaskCheck = ( unsigned short ) 0;
portBASE_TYPE xReturn = pdTRUE;
/* Check the tasks are still running by ensuring the check variable
is still incrementing. */
if( usCheckVariable == usLastTaskCheck )
{
/* The check has not incremented so an error exists. */
xReturn = pdFALSE;
}
if( xSuspendedQueueSendError == pdTRUE )
{
xReturn = pdFALSE;
}
if( xSuspendedQueueReceiveError == pdTRUE )
{
xReturn = pdFALSE;
}
usLastTaskCheck = usCheckVariable;
return xReturn;
}
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/Minimal/dynamic.c | C | oos | 16,403 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/*
* This demo application file demonstrates the use of queues to pass data
* between co-routines.
*
* N represents the number of 'fixed delay' co-routines that are created and
* is set during initialisation.
*
* N 'fixed delay' co-routines are created that just block for a fixed
* period then post the number of an LED onto a queue. Each such co-routine
* uses a different block period. A single 'flash' co-routine is also created
* that blocks on the same queue, waiting for the number of the next LED it
* should flash. Upon receiving a number it simply toggle the instructed LED
* then blocks on the queue once more. In this manner each LED from LED 0 to
* LED N-1 is caused to flash at a different rate.
*
* The 'fixed delay' co-routines are created with co-routine priority 0. The
* flash co-routine is created with co-routine priority 1. This means that
* the queue should never contain more than a single item. This is because
* posting to the queue will unblock the 'flash' co-routine, and as this has
* a priority greater than the tasks posting to the queue it is guaranteed to
* have emptied the queue and blocked once again before the queue can contain
* any more date. An error is indicated if an attempt to post data to the
* queue fails - indicating that the queue is already full.
*
*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "croutine.h"
#include "queue.h"
/* Demo application includes. */
#include "partest.h"
#include "crflash.h"
/* The queue should only need to be of length 1. See the description at the
top of the file. */
#define crfQUEUE_LENGTH 1
#define crfFIXED_DELAY_PRIORITY 0
#define crfFLASH_PRIORITY 1
/* Only one flash co-routine is created so the index is not significant. */
#define crfFLASH_INDEX 0
/* Don't allow more than crfMAX_FLASH_TASKS 'fixed delay' co-routines to be
created. */
#define crfMAX_FLASH_TASKS 8
/* We don't want to block when posting to the queue. */
#define crfPOSTING_BLOCK_TIME 0
/*
* The 'fixed delay' co-routine as described at the top of the file.
*/
static void prvFixedDelayCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex );
/*
* The 'flash' co-routine as described at the top of the file.
*/
static void prvFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex );
/* The queue used to pass data between the 'fixed delay' co-routines and the
'flash' co-routine. */
static xQueueHandle xFlashQueue;
/* This will be set to pdFALSE if we detect an error. */
static portBASE_TYPE xCoRoutineFlashStatus = pdPASS;
/*-----------------------------------------------------------*/
/*
* See the header file for details.
*/
void vStartFlashCoRoutines( unsigned portBASE_TYPE uxNumberToCreate )
{
unsigned portBASE_TYPE uxIndex;
if( uxNumberToCreate > crfMAX_FLASH_TASKS )
{
uxNumberToCreate = crfMAX_FLASH_TASKS;
}
/* Create the queue used to pass data between the co-routines. */
xFlashQueue = xQueueCreate( crfQUEUE_LENGTH, sizeof( unsigned portBASE_TYPE ) );
if( xFlashQueue )
{
/* Create uxNumberToCreate 'fixed delay' co-routines. */
for( uxIndex = 0; uxIndex < uxNumberToCreate; uxIndex++ )
{
xCoRoutineCreate( prvFixedDelayCoRoutine, crfFIXED_DELAY_PRIORITY, uxIndex );
}
/* Create the 'flash' co-routine. */
xCoRoutineCreate( prvFlashCoRoutine, crfFLASH_PRIORITY, crfFLASH_INDEX );
}
}
/*-----------------------------------------------------------*/
static void prvFixedDelayCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
{
/* Even though this is a co-routine the xResult variable does not need to be
static as we do not need it to maintain its state between blocks. */
signed portBASE_TYPE xResult;
/* The uxIndex parameter of the co-routine function is used as an index into
the xFlashRates array to obtain the delay period to use. */
static const portTickType xFlashRates[ crfMAX_FLASH_TASKS ] = { 150 / portTICK_RATE_MS,
200 / portTICK_RATE_MS,
250 / portTICK_RATE_MS,
300 / portTICK_RATE_MS,
350 / portTICK_RATE_MS,
400 / portTICK_RATE_MS,
450 / portTICK_RATE_MS,
500 / portTICK_RATE_MS };
/* Co-routines MUST start with a call to crSTART. */
crSTART( xHandle );
for( ;; )
{
/* Post our uxIndex value onto the queue. This is used as the LED to
flash. */
crQUEUE_SEND( xHandle, xFlashQueue, ( void * ) &uxIndex, crfPOSTING_BLOCK_TIME, &xResult );
if( xResult != pdPASS )
{
/* For the reasons stated at the top of the file we should always
find that we can post to the queue. If we could not then an error
has occurred. */
xCoRoutineFlashStatus = pdFAIL;
}
crDELAY( xHandle, xFlashRates[ uxIndex ] );
}
/* Co-routines MUST end with a call to crEND. */
crEND();
}
/*-----------------------------------------------------------*/
static void prvFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
{
/* Even though this is a co-routine the variable do not need to be
static as we do not need it to maintain their state between blocks. */
signed portBASE_TYPE xResult;
unsigned portBASE_TYPE uxLEDToFlash;
/* Co-routines MUST start with a call to crSTART. */
crSTART( xHandle );
( void ) uxIndex;
for( ;; )
{
/* Block to wait for the number of the LED to flash. */
crQUEUE_RECEIVE( xHandle, xFlashQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
if( xResult != pdPASS )
{
/* We would not expect to wake unless we received something. */
xCoRoutineFlashStatus = pdFAIL;
}
else
{
/* We received the number of an LED to flash - flash it! */
vParTestToggleLED( uxLEDToFlash );
}
}
/* Co-routines MUST end with a call to crEND. */
crEND();
}
/*-----------------------------------------------------------*/
portBASE_TYPE xAreFlashCoRoutinesStillRunning( void )
{
/* Return pdPASS or pdFAIL depending on whether an error has been detected
or not. */
return xCoRoutineFlashStatus;
}
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/Minimal/crflash.c | C | oos | 9,178 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
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contact details.
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*/
/*
* This file implements the same demo and test as GenQTest.c, but uses the
* light weight API in place of the fully featured API.
*
* See the comments at the top of GenQTest.c for a description.
*/
#include <stdlib.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
#include "semphr.h"
/* Demo program include files. */
#include "AltQTest.h"
#define genqQUEUE_LENGTH ( 5 )
#define genqNO_BLOCK ( 0 )
#define genqMUTEX_LOW_PRIORITY ( tskIDLE_PRIORITY )
#define genqMUTEX_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define genqMUTEX_MEDIUM_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define genqMUTEX_HIGH_PRIORITY ( tskIDLE_PRIORITY + 3 )
/*-----------------------------------------------------------*/
/*
* Tests the behaviour of the xQueueAltSendToFront() and xQueueAltSendToBack()
* macros by using both to fill a queue, then reading from the queue to
* check the resultant queue order is as expected. Queue data is also
* peeked.
*/
static void prvSendFrontAndBackTest( void *pvParameters );
/*
* The following three tasks are used to demonstrate the mutex behaviour.
* Each task is given a different priority to demonstrate the priority
* inheritance mechanism.
*
* The low priority task obtains a mutex. After this a high priority task
* attempts to obtain the same mutex, causing its priority to be inherited
* by the low priority task. The task with the inherited high priority then
* resumes a medium priority task to ensure it is not blocked by the medium
* priority task while it holds the inherited high priority. Once the mutex
* is returned the task with the inherited priority returns to its original
* low priority, and is therefore immediately preempted by first the high
* priority task and then the medium prioroity task before it can continue.
*/
static void prvLowPriorityMutexTask( void *pvParameters );
static void prvMediumPriorityMutexTask( void *pvParameters );
static void prvHighPriorityMutexTask( void *pvParameters );
/*-----------------------------------------------------------*/
/* Flag that will be latched to pdTRUE should any unexpected behaviour be
detected in any of the tasks. */
static portBASE_TYPE xErrorDetected = pdFALSE;
/* Counters that are incremented on each cycle of a test. This is used to
detect a stalled task - a test that is no longer running. */
static volatile unsigned portLONG ulLoopCounter = 0;
static volatile unsigned portLONG ulLoopCounter2 = 0;
/* The variable that is guarded by the mutex in the mutex demo tasks. */
static volatile unsigned portLONG ulGuardedVariable = 0;
/* Handles used in the mutext test to suspend and resume the high and medium
priority mutex test tasks. */
static xTaskHandle xHighPriorityMutexTask, xMediumPriorityMutexTask;
/*-----------------------------------------------------------*/
void vStartAltGenericQueueTasks( unsigned portBASE_TYPE uxPriority )
{
xQueueHandle xQueue;
xSemaphoreHandle xMutex;
/* Create the queue that we are going to use for the
prvSendFrontAndBackTest demo. */
xQueue = xQueueCreate( genqQUEUE_LENGTH, sizeof( unsigned portLONG ) );
/* vQueueAddToRegistry() adds the queue to the queue registry, if one is
in use. The queue registry is provided as a means for kernel aware
debuggers to locate queues and has no purpose if a kernel aware debugger
is not being used. The call to vQueueAddToRegistry() will be removed
by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is
defined to be less than 1. */
vQueueAddToRegistry( xQueue, ( signed portCHAR * ) "Alt_Gen_Test_Queue" );
/* Create the demo task and pass it the queue just created. We are
passing the queue handle by value so it does not matter that it is
declared on the stack here. */
xTaskCreate( prvSendFrontAndBackTest, ( signed portCHAR * ) "FGenQ", configMINIMAL_STACK_SIZE, ( void * ) xQueue, uxPriority, NULL );
/* Create the mutex used by the prvMutexTest task. */
xMutex = xSemaphoreCreateMutex();
/* vQueueAddToRegistry() adds the mutex to the registry, if one is
in use. The registry is provided as a means for kernel aware
debuggers to locate mutex and has no purpose if a kernel aware debugger
is not being used. The call to vQueueAddToRegistry() will be removed
by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is
defined to be less than 1. */
vQueueAddToRegistry( ( xQueueHandle ) xMutex, ( signed portCHAR * ) "Alt_Q_Mutex" );
/* Create the mutex demo tasks and pass it the mutex just created. We are
passing the mutex handle by value so it does not matter that it is declared
on the stack here. */
xTaskCreate( prvLowPriorityMutexTask, ( signed portCHAR * ) "FMuLow", configMINIMAL_STACK_SIZE, ( void * ) xMutex, genqMUTEX_LOW_PRIORITY, NULL );
xTaskCreate( prvMediumPriorityMutexTask, ( signed portCHAR * ) "FMuMed", configMINIMAL_STACK_SIZE, NULL, genqMUTEX_MEDIUM_PRIORITY, &xMediumPriorityMutexTask );
xTaskCreate( prvHighPriorityMutexTask, ( signed portCHAR * ) "FMuHigh", configMINIMAL_STACK_SIZE, ( void * ) xMutex, genqMUTEX_HIGH_PRIORITY, &xHighPriorityMutexTask );
}
/*-----------------------------------------------------------*/
static void prvSendFrontAndBackTest( void *pvParameters )
{
unsigned portLONG ulData, ulData2;
xQueueHandle xQueue;
#ifdef USE_STDIO
void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend );
const portCHAR * const pcTaskStartMsg = "Alt queue SendToFront/SendToBack/Peek test started.\r\n";
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
#endif
xQueue = ( xQueueHandle ) pvParameters;
for( ;; )
{
/* The queue is empty, so sending an item to the back of the queue
should have the same efect as sending it to the front of the queue.
First send to the front and check everything is as expected. */
xQueueAltSendToFront( xQueue, ( void * ) &ulLoopCounter, genqNO_BLOCK );
if( uxQueueMessagesWaiting( xQueue ) != 1 )
{
xErrorDetected = pdTRUE;
}
if( xQueueAltReceive( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
/* The data we sent to the queue should equal the data we just received
from the queue. */
if( ulLoopCounter != ulData )
{
xErrorDetected = pdTRUE;
}
/* Then do the same, sending the data to the back, checking everything
is as expected. */
if( uxQueueMessagesWaiting( xQueue ) != 0 )
{
xErrorDetected = pdTRUE;
}
xQueueAltSendToBack( xQueue, ( void * ) &ulLoopCounter, genqNO_BLOCK );
if( uxQueueMessagesWaiting( xQueue ) != 1 )
{
xErrorDetected = pdTRUE;
}
if( xQueueAltReceive( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
if( uxQueueMessagesWaiting( xQueue ) != 0 )
{
xErrorDetected = pdTRUE;
}
/* The data we sent to the queue should equal the data we just received
from the queue. */
if( ulLoopCounter != ulData )
{
xErrorDetected = pdTRUE;
}
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
/* Place 2, 3, 4 into the queue, adding items to the back of the queue. */
for( ulData = 2; ulData < 5; ulData++ )
{
xQueueAltSendToBack( xQueue, ( void * ) &ulData, genqNO_BLOCK );
}
/* Now the order in the queue should be 2, 3, 4, with 2 being the first
thing to be read out. Now add 1 then 0 to the front of the queue. */
if( uxQueueMessagesWaiting( xQueue ) != 3 )
{
xErrorDetected = pdTRUE;
}
ulData = 1;
xQueueAltSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK );
ulData = 0;
xQueueAltSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK );
/* Now the queue should be full, and when we read the data out we
should receive 0, 1, 2, 3, 4. */
if( uxQueueMessagesWaiting( xQueue ) != 5 )
{
xErrorDetected = pdTRUE;
}
if( xQueueAltSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL )
{
xErrorDetected = pdTRUE;
}
if( xQueueAltSendToBack( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL )
{
xErrorDetected = pdTRUE;
}
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
/* Check the data we read out is in the expected order. */
for( ulData = 0; ulData < genqQUEUE_LENGTH; ulData++ )
{
/* Try peeking the data first. */
if( xQueueAltPeek( xQueue, &ulData2, genqNO_BLOCK ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
if( ulData != ulData2 )
{
xErrorDetected = pdTRUE;
}
/* Now try receiving the data for real. The value should be the
same. Clobber the value first so we know we really received it. */
ulData2 = ~ulData2;
if( xQueueAltReceive( xQueue, &ulData2, genqNO_BLOCK ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
if( ulData != ulData2 )
{
xErrorDetected = pdTRUE;
}
}
/* The queue should now be empty again. */
if( uxQueueMessagesWaiting( xQueue ) != 0 )
{
xErrorDetected = pdTRUE;
}
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
/* Our queue is empty once more, add 10, 11 to the back. */
ulData = 10;
if( xQueueAltSendToBack( xQueue, &ulData, genqNO_BLOCK ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
ulData = 11;
if( xQueueAltSendToBack( xQueue, &ulData, genqNO_BLOCK ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
if( uxQueueMessagesWaiting( xQueue ) != 2 )
{
xErrorDetected = pdTRUE;
}
/* Now we should have 10, 11 in the queue. Add 7, 8, 9 to the
front. */
for( ulData = 9; ulData >= 7; ulData-- )
{
if( xQueueAltSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
}
/* Now check that the queue is full, and that receiving data provides
the expected sequence of 7, 8, 9, 10, 11. */
if( uxQueueMessagesWaiting( xQueue ) != 5 )
{
xErrorDetected = pdTRUE;
}
if( xQueueAltSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL )
{
xErrorDetected = pdTRUE;
}
if( xQueueAltSendToBack( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL )
{
xErrorDetected = pdTRUE;
}
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
/* Check the data we read out is in the expected order. */
for( ulData = 7; ulData < ( 7 + genqQUEUE_LENGTH ); ulData++ )
{
if( xQueueAltReceive( xQueue, &ulData2, genqNO_BLOCK ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
if( ulData != ulData2 )
{
xErrorDetected = pdTRUE;
}
}
if( uxQueueMessagesWaiting( xQueue ) != 0 )
{
xErrorDetected = pdTRUE;
}
ulLoopCounter++;
}
}
/*-----------------------------------------------------------*/
static void prvLowPriorityMutexTask( void *pvParameters )
{
xSemaphoreHandle xMutex = ( xSemaphoreHandle ) pvParameters;
#ifdef USE_STDIO
void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend );
const portCHAR * const pcTaskStartMsg = "Fast mutex with priority inheritance test started.\r\n";
/* Queue a message for printing to say the task has started. */
vPrintDisplayMessage( &pcTaskStartMsg );
#endif
( void ) pvParameters;
for( ;; )
{
/* Take the mutex. It should be available now. */
if( xSemaphoreAltTake( xMutex, genqNO_BLOCK ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
/* Set our guarded variable to a known start value. */
ulGuardedVariable = 0;
/* Our priority should be as per that assigned when the task was
created. */
if( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY )
{
xErrorDetected = pdTRUE;
}
/* Now unsuspend the high priority task. This will attempt to take the
mutex, and block when it finds it cannot obtain it. */
vTaskResume( xHighPriorityMutexTask );
/* We should now have inherited the prioritoy of the high priority task,
as by now it will have attempted to get the mutex. */
if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )
{
xErrorDetected = pdTRUE;
}
/* We can attempt to set our priority to the test priority - between the
idle priority and the medium/high test priorities, but our actual
prioroity should remain at the high priority. */
vTaskPrioritySet( NULL, genqMUTEX_TEST_PRIORITY );
if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )
{
xErrorDetected = pdTRUE;
}
/* Now unsuspend the medium priority task. This should not run as our
inherited priority is above that of the medium priority task. */
vTaskResume( xMediumPriorityMutexTask );
/* If the did run then it will have incremented our guarded variable. */
if( ulGuardedVariable != 0 )
{
xErrorDetected = pdTRUE;
}
/* When we give back the semaphore our priority should be disinherited
back to the priority to which we attempted to set ourselves. This means
that when the high priority task next blocks, the medium priority task
should execute and increment the guarded variable. When we next run
both the high and medium priority tasks will have been suspended again. */
if( xSemaphoreAltGive( xMutex ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
/* Check that the guarded variable did indeed increment... */
if( ulGuardedVariable != 1 )
{
xErrorDetected = pdTRUE;
}
/* ... and that our priority has been disinherited to
genqMUTEX_TEST_PRIORITY. */
if( uxTaskPriorityGet( NULL ) != genqMUTEX_TEST_PRIORITY )
{
xErrorDetected = pdTRUE;
}
/* Set our priority back to our original priority ready for the next
loop around this test. */
vTaskPrioritySet( NULL, genqMUTEX_LOW_PRIORITY );
/* Just to show we are still running. */
ulLoopCounter2++;
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
}
}
/*-----------------------------------------------------------*/
static void prvMediumPriorityMutexTask( void *pvParameters )
{
( void ) pvParameters;
for( ;; )
{
/* The medium priority task starts by suspending itself. The low
priority task will unsuspend this task when required. */
vTaskSuspend( NULL );
/* When this task unsuspends all it does is increment the guarded
variable, this is so the low priority task knows that it has
executed. */
ulGuardedVariable++;
}
}
/*-----------------------------------------------------------*/
static void prvHighPriorityMutexTask( void *pvParameters )
{
xSemaphoreHandle xMutex = ( xSemaphoreHandle ) pvParameters;
( void ) pvParameters;
for( ;; )
{
/* The high priority task starts by suspending itself. The low
priority task will unsuspend this task when required. */
vTaskSuspend( NULL );
/* When this task unsuspends all it does is attempt to obtain
the mutex. It should find the mutex is not available so a
block time is specified. */
if( xSemaphoreAltTake( xMutex, portMAX_DELAY ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
/* When we eventually obtain the mutex we just give it back then
return to suspend ready for the next test. */
if( xSemaphoreAltGive( xMutex ) != pdPASS )
{
xErrorDetected = pdTRUE;
}
}
}
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running. */
portBASE_TYPE xAreAltGenericQueueTasksStillRunning( void )
{
static unsigned portLONG ulLastLoopCounter = 0, ulLastLoopCounter2 = 0;
/* If the demo task is still running then we expect the loopcounters to
have incremented since this function was last called. */
if( ulLastLoopCounter == ulLoopCounter )
{
xErrorDetected = pdTRUE;
}
if( ulLastLoopCounter2 == ulLoopCounter2 )
{
xErrorDetected = pdTRUE;
}
ulLastLoopCounter = ulLoopCounter;
ulLastLoopCounter2 = ulLoopCounter2;
/* Errors detected in the task itself will have latched xErrorDetected
to true. */
return !xErrorDetected;
}
| zz314326255--adkping | adkping/iNEMO-accessory/FreeRTOSv7.0.2/Demo/Common/Minimal/AltQTest.c | C | oos | 19,252 |