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b61a0bf651537071c0010f2ac77f17ba | 103 813 | 3.1 Terms | For the purposes of the present document, the terms given in ETSI TS 103 713 [1] and the following apply: JTAG: Joint Test Action Group, synonym for IEEE 1149.1-2013 [3] SPI Master: expression used to describe the Master entity connected to an SPI NOTE: Descriptive text may use "master" or "SPI_M" as synonyms. SPI Slav... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 3.2 Symbols | For the purposes of the present document, the symbols given in ETSI TS 103 713 [1] apply. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 3.3 Abbreviations | For the purposes of the present document, the abbreviations given in ETSI TS 103 713 [1] and the following apply: ATS Abstract Test Suite ICS Implementation Conformance Statement PCB Printed Circuit Board POT Power On Time SPI_M SPI Master SPI_S SPI Slave SUT System Under Test ETSI ETSI TS 103 813 V15.1.0 (2022-02) 16 ... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 3.4 Formats | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 3.4.1 Format of the table of optional features | The columns in the optional features table, Table 4.1, have the following meaning: Column Meaning Item Item number, incrementing with each item added to the table Option Description of the optional feature that might be supported by the implementation Status The status of the optional feature is described following not... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 3.4.2 Format of the applicability table | The columns in the applicability tables, Table 4.2a, Table 4.3a and Table 4.4, have the following meaning: Column Meaning Test/Seq. A reference to the test case number(s) detailed in the present document and required to validate the implementation of the corresponding item in the "Description" column. Tests consisting ... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 3.4.3 Format of the conformance requirements tables | The columns in the requirement tables in clause 5 have the following meaning: Column Meaning Req.ID This column shows the ordinal term assigned to a requirement identified in the referenced specification. The following syntax has been used to define the unique R(equirement) terms: R<n><XX><YY>_<ZZZ> n: Identification l... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 3.4.4 Numbers and Strings | The conventions used for decimal numbers, binary numbers and strings. Table 3.1: Convention of Numbering and Strings Convention Description nnnnn A decimal number, e.g. PIN value or phone number 'b' A single digit binary number 'bbbbbbbb' An 8-bit binary number 'hh' A single octet hexadecimal number 'hh hh…hh' A multi-... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 3.4.5 Format of the sequences in the test procedure | The columns in the sequence tables for the test procedures have the following meaning: Column Meaning Step The "Step" column contains a step number, incrementing with each step added to the test procedure. A step may include a number of actions that have to be executed in parallel e.g.: on different instances. In such ... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 4 Test environments | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 4.0 Description of the test environments | The test environment shall comply with the requirements specified in to ETSI TS 103 713 [1]. The tests are executed in dedicated test environments, offering interfaces to the SUT to activate, operate and trace the communication on the SUT. The tests are performed at open standardized interfaces that are not accessible ... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 4.1 Testing architectures | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 4.1.0 Description of the testing architectures | ETSI TS 103 713 [1] defines two different implementations of the SPI: • SPI with a physical interface using 5 signals (see ETSI TS 103 713 [1], clause 6.2); • SPI with a physical interface using 4 signals (see ETSI TS 103 713 [1], clause 6.3). For testing the SPI, the test tool is connected to all SPI signals and to th... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 4.1.1 Testing architecture - SPI with an electrical interface using 5 signals | The testing architectures for a 5 signals SPI with connection and emulation options are shown in Figure 4.3. Figure 4.3: Testing architecture - 5 signals SPI |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 4.1.2 Testing architecture - SPI with an electrical interface using 4 signals | The testing architecture for a 4 signals SPI with connection and emulation options are shown in Figure 4.4. Figure 4.4: Testing architecture - 4 signals SPI ETSI ETSI TS 103 813 V15.1.0 (2022-02) 21 Release 15 |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 4.2 Test tool | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 4.2.0 Capabilities of the test tool | The test tool shall provide emulation capabilities for the master and the slave: • In cases where the TT acts as a master it shall be able to adjust the communication to the parameters provided by the slave (e.g. SPI_CLK). • In cases where the TT acts as a slave it shall be able to receive the data sent by the master i... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 4.2.1 Adaption of the test tool | For the electrical characteristics input and output values are defined. An appropriate measurement can only be performed if the measurement equipment can be directly connected to the buffer under test. It is assumed that the TT is connected to the SPI signal lines via one single connector. Thus, separate measurement of... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 4.3 Table of optional features | The product vendor shall declare which optional features are supported by their implementation. ICS relevant optional features are listed in Table 4.1. See clause 3.4.1 for the format of the table. Table 4.1: Table of optional features Item Option Status Release Support Mnemonic 1 Physical Interface with 5 signals Rel-... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 4.4 Applicability tables | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 4.4.1 Applicability table - testing of the SPI Master | Table 4.2a specifies the applicability of each test case to the SUT in accordance to Figure 4.1. For testing in accordance to Table 4.2a the SPI master is the SUT, testing is performed with an emulated SPI slave. The applicability table in this clause is formatted as described in clause 3.4.2. Table 4.2a: Applicability... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 4.4.2 Applicability table - testing of the SPI Slave | Table 4.3a specifies the applicability of each test case to the SUT in accordance to Figure 4.2. For testing in accordance to Table 4.3a the SPI slave is the SUT, testing is performed with an emulated master. The applicability table in this clause is formatted as described in clause 3.4.2. Table 4.3a: Applicability tab... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 4.4.3 Applicability table - Higher level protocol testing | Table 4.4 specifies the applicability for higher level protocol testing (e.g. SHDLC). For those test cases no differentiation between SPI master and SPI slave is made as the communication can be started at either endpoint. These test cases use endpoints named 'SUT' for the System Under Test and 'TT' for the Test Tool w... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 4.5 Test cases and test case description | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 4.5.1 Common conditions and test steps | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 4.5.1.1 Group specific initial conditions | To execute a test case defined in the present document, predefined initial conditions for the test case and the test case group may need to be fulfilled. Group specific initial conditions may contain descriptions of specific states, execution instructions and/or a reference to group common test steps that need to be ex... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 4.5.1.2 Group common test steps | To avoid the repetition of test steps that are common to test cases of a particular group, those test steps are defined in a separate clause. Group common test steps may need to be executed before the test steps listed in the test procedure, or afterwards. Test steps to be executed before Step 1 are numbered: 0.1 to 0.... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 4.5.2 Test case description | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 4.5.2.0 Structure and description of a test case | Test cases defined in the present document are written in prose. Test case descriptions are available and specific for each test case. The test case description as used for the test cases defined within the present document consist of: • Test purpose; • Initial conditions; • Test procedure; • Post conditions (optional)... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 4.5.2.1 Test purpose | The test purpose is a concise and unambiguous description of what is to be tested. The test purpose description should be based on testable requirements identified in the specification named in the related conformance requirement section. If no directly testable requirement could be identified, requirements implicitly ... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 4.5.2.2 Initial conditions | In addition to a reference to the common initial conditions and/or the group specific initial conditions the test case description may contain specific initial conditions that apply to the current test case only. The test case specific initial conditions in this clause may contain descriptions of specific states and/or... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 4.5.2.3 Test procedure | Following the common initial, the group test initial and the test case specific initial conditions, the steps listed in the test procedure define the specific part of the test execution. The test procedure is given in a table format. Each table row consists of the columns: • Step • Direction • Action/Task • Description... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 4.5.2.4 Post conditions | The post conditions, if present, describe actions to be carried out and/or the status of the TT and/or the SUT after the test procedure. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 4.6 Implicit testing | For some requirements identified in ETSI TS 103 713 [1], conformance is not verified explicitly in the present document. This does not imply that correct functioning of the described procedures and related features is not essential, but that these are implicitly tested to a sufficient degree. Descriptive requirements i... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 4.7 Pass criterion | Pass criterions are identified in accordance to ISO/IEC 9646-7 [2]: • A test execution is considered as successful only if the test procedure was fully carried out successfully. • A test execution is considered as failed if the tested feature provides an unexpected behaviour. • A test execution is considered as inconcl... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 5 Conformance requirements | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 5.0 Conformance requirement references | The conformance requirements that apply to the test cases within the present document are derived from the specification named in the reference text preceding each conformance requirement listing. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 5.1 Electrical interfaces | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 5.1.0 Electrical interfaces - common requirements | Reference: ETSI TS 103 713 [1], clause 6.1. Req.ID Clause Description RQ0601_001 6.1 An SPI interface implementation shall allow bi-directional communication. RQ0601_002 6.1 The slave shall be able to initiate communication with the master when it has data available without a prior command from master. ETSI ETSI TS 103... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 5.1.1 Physical interface with 5 signals | Reference: ETSI TS 103 713 [1], clause 6.2. Req.ID Clause Description RQ0602_003 6.2 SPI_NSS signal used for the selection of a Slave Endpoint among N slaves sharing the same bus. RQ0602_004 6.2 SPI_NSS is considered active or asserted at low voltage level. RQ0602_005 6.2 SPI_MISO, SPI_MOSI and SPI_CLK can be shared be... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 5.1.2 Physical interface with 4 signals | Reference: ETSI TS 103 713 [1], clause 6.3. Req.ID Clause Description RQ0603_001 6.3 SPI_NSS is considered active or asserted at low voltage level. SPI_NSS requires a bidirectional IO implementing an Open Drain (OD) interface for both master and slave. This configuration allows driving the SPI_NSS signal to low voltage... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 5.1.3 Electrical characteristics | Reference: ETSI TS 103 713 [1], clause 6.4. Req.ID Clause Description 6.4.1 - DC characteristics RQ0604_001 6.4.1 The SPI Electrical specification interface shall be defined for VDD operational voltage classes B and C as defined in ETSI TS 103 666-1 [4], clause 6.2.2.3. RQ0604_002 6.4.1 In voltage class B the VIH shall... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 5.1.4 Slave state | Reference: ETSI TS 103 713 [1], clause 6.5. Req.ID Clause Description 6.5.1 - Slave state definitions RQ0605_001 6.5.1 As soon as the slave is powered on and VDD is valid it enters the Initial state. RQ0605_002 6.5.1 After a reset the slave enters the Initial state. RQ0605_003 6.5.1 After the POT time, following VDD va... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 5.2 Data link layer | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 5.2.0 Overview | Reference: ETSI TS 103 713 [1], clause 7. Req.ID Clause Description 7.1 - Overview RQ0701_001 7.1 Clause 9.1 in ETSI TS 102 613 [5] shall apply. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 5.2.1 MAC layer | Reference: ETSI TS 103 713 [1], clause 7.2. Req.ID Clause Description 7.2.2 - Timing 7.2.2.2 - T1 = Slave Ready Time RQ0702_001 7.2.2.2 T1 is the MAC phase time required by the slave to get configured and enabled at the end of the MAC phase. The slave shall be ready for the data transfer phase after T1 (i.e. when the S... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 5.2.2 Link layer frame | Reference: ETSI TS 103 713 [1], clause 7.3. Req.ID Clause Description 7.3.1 - Overview RQ0703_001 7.3.1 The format of the frames generated by master and slave is determined by the link layer and it is shown in ETSI TS 103 713 [1], figure 7.8. All bytes shall be transmitted with MSB first (most significant bit first). R... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 5.2.3 LLC layers | Reference: ETSI TS 103 713 [1], clause 7.4. Req.ID Clause Description RQ0704_001 7.4 Support of SHDLC layer as defined in ETSI TS 102 613 [5], clause 10, is mandatory for the master and the slave. The first byte of the LPDU is defined in table 7.3 of ETSI TS 103 713 [1]. RQ0704_002 7.4 Support of CLT layer as defined i... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 5.2.4 Interworking of the LLC layers | Reference: ETSI TS 103 713 [1], clause 7.5. Req.ID Clause Description RQ0705_001 7.5 After MAC activation, the SHDLC link shall not be established and no CLT session shall be open. Only the MCT LLC shall be used by the master and by the slave for the SPI interface initialization. RQ0705_002 7.5 The master shall take th... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 5.2.5 MCT LLC definition | Reference: ETSI TS 103 713 [1], clause 7.6. Req.ID Clause Description 7.6.1 - MCT LPDU structure RQ0706_001 7.6.1 The MCT LPDU shall be structured according to ETSI TS 103 713 [1], figure 7.12. The meaning of MCT_CTRL and MCT_DATA is given in ETSI TS 103 713 [1], table 7.4. RQ0706_002 7.6.1 The MCT LPDU length shall be... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 5.2.6 SHDLC LLC definition | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 5.2.6.1 General SHDLC LLC requirements for SPI implementations | Reference: ETSI TS 103 713 [1], clause 7.7. Req.ID Clause Description 7.7.1 - SHDLC overview RQ0707_001 7.7.1 The provisions of ETSI TS 102 613 [5], clause 10.1 shall apply. The SWP SHDLC layer is replaced by the SPI SHDLC layer defined in ETSI TS 103 713 [1]. The SHDLC layer shall ensure that data passed up to the nex... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 5.2.6.2 Specific SHDLC LLC requirements for SPI implementations | Reference: ETSI TS 102 613 [5], clause 10 and subclauses. Req.ID Clause Description 10 - SHDLC LLC definition 10.1 - SHDLC overview RX1001_001 10.1 The SHDLC layer in an endpoint shall ensure that data passed up to the next layer has been received exactly as transmitted (i.e. error free, without loss and in the correct... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 5.2.7 Power management | Reference: ETSI TS 103 713 [1], clause 7.8. Req.ID Clause Description 7.8.1 - Power saving mode RQ0708_001 7.8.1 The master and the slave shall both resume from power saving mode in the same LLC context following the master or the slave resumption. 7.8.2 - Conditions for entering power saving mode RQ0708_002 7.8.2.1 Th... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6 Test cases for electrical interfaces | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.0 Initial conditions for tests of the electrical interfaces | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.0.1 Common initial conditions for tests of the electrical interfaces | The Test Tool (TT) is connected to the signal lines of the SPI. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.0.2 Pre-conditions for the measurement of DC characteristics | For the measurement of the DC characteristics: • when measuring the Output high voltage, the Output high current (IOH) is limited to -100 µA; • when measuring the Output low voltage, the Output low current (IOL) is limited to 1 mA; • the test environment shown in Figure 4.1 is used, where the SPI master is the SUT; • t... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.0.3 Pre-conditions for the measurement of AC characteristics | For the measurement of the AC characteristics: • The SPI mode 0 has to be supported and used for all measurements of AC characteristics (CPOL = 0 and CPHA = 0). • As for testing purposes control and signalling on the SPI bus has to be initiated by a specified entity, the related AC testing has to be executed using the ... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.0.4 Preparation procedure - SPI master AC testing | For SPI master testing, a test environment where the SPI master is the SUT and the TT is emulating an SPI slave is used (see Figure 4.1). Step Direction Action/Task Description/Expectation 0.1 TT/Tester Power on The power supply of the PCB hosting the SPI is switched on 0.2 SPI_M → TT(SPI_S) Run MAC activation A 5 sign... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.0.5 Preparation procedure - SPI slave AC testing | For SPI slave testing, a test environment where the SPI slave is the SUT and the TT is emulating an SPI master is used (see Figure 4.2). Step Direction Action/Task Description/Expectation 0.1 TT/Tester Power on The power supply of the PCB hosting the SPI is switched on 0.2 TT(SPI_M) → SPI_S Run MAC activation The TT(SP... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.0.6 Post-processing procedure | The post-processing procedure for electrical testing shall ensure that all measurements performed by the TT can be completed and that the associated SPI master slave connection under test is securely deactivated and powered down. Step Direction Action/Task Description/Expectation n.1 TT Wait for 10 s TT and power suppl... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.1 Electrical characteristics - 5 signals SPI - SPI Master testing | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.1.1 5 signals SPI - DC characteristics for operational voltage class B | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.1.1.1 Test purpose | The SPI electrical specification interface shall be defined for VDD operational voltage classes B and C as defined in ETSI TS 103 666-1 [4], clause 6.2.2.3. For the SPI physical interface with 5 signals operating in voltage class B (3,0 V) the DC characteristics defined in ETSI TS 103 713 [1], table 6.2 apply, except f... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.1.1.2 Initial conditions | 1) The initial conditions listed in clause 6.0.1 and clause 6.0.2 apply. 2) The technology dependent high impedance values for the input and output buffers connected to the SPI are used to adjust the slave emulation characteristics of the TT. ETSI ETSI TS 103 813 V15.1.0 (2022-02) 42 Release 15 |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.1.1.3 Test procedure | Sequence 1 Step Direction Action/Task Description/Expectation REQ 1 SPI_M → TT(SPI_S) Run MAC activation The SPI_M runs a MAC activation as defined in Annex C, clause C.1.1 RQ0702_018 2 TT Run voltage measurement on VDD VDD*1 is within the limits defined for voltage class B (2,7 V - 3,3 V) RQ0604_001 3 TT Run voltage m... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.1.1.4 Post conditions | The SPI is powered off, i.e. the power supply for the PCB or chip hosting the SPI is switched off. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.1.2 5 signals SPI - DC characteristics for operational voltage class C | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.1.2.1 Test purpose | The SPI Electrical specification interface shall be defined for VDD operational voltage classes B and C as defined in ETSI TS 103 666-1 [4], clause 6.2.2.3. For the SPI physical interface with 5 signals operating in voltage class C (1,8 V) the DC characteristics defined in ETSI TS 103 713 [1], table 6.3 apply, except f... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.1.2.2 Initial conditions | 1) The initial conditions listed in clause 6.0.1 and clause 6.0.2 apply. 2) The technology dependent high impedance values for the input and output buffers connected to the SPI are used to adjust the slave emulation characteristics of the TT. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.1.2.3 Test procedure | Sequence 1 Step Direction Action/Task Description/Expectation REQ 1 SPI_M → TT(SPI_S) Run MAC activation The SPI_M runs a MAC activation as defined in Annex C, clause C.1.1 RQ0702_018 2 TT Run voltage measurement on VDD VDD*1 is within the limits defined for voltage class C (1,68 V - 1,92 V) RQ0604_001 ETSI ETSI TS 103... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.1.2.4 Post conditions | The SPI is powered off, i.e. the power supply for the PCB or chip hosting the SPI is switched off. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.1.3 5 signals SPI - AC characteristics for operational voltage class B | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.1.3.1 Test purpose | To comply to ETSI TS 103 713 [1] an SPI bus shall have implemented the SPI mode 0 according to the industry de-facto SPI specification. Timing parameters indicated in ETSI TS 103 713 [1], table 6.4 are reference values for generic SPI slaves and therefore have to be supported by the SPI master. To allow determination o... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.1.3.2 Initial conditions | 1) The initial conditions listed in clause 6.0.1 and clause 6.0.3 apply. ETSI ETSI TS 103 813 V15.1.0 (2022-02) 44 Release 15 2) The preparation procedure for SPI master AC testing from clause 6.0.4 is executed. 3) The SPI slave asserts SPI_INT for a 1 µs pulse (or known duration T2) for a MAC access request. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.1.3.3 Test procedure | Sequence 1 - Determination of clock specific AC characteristics Step Direction Action/Task Description/Expectation REQ 1 SPI_M → TT(SPI_S) Run MAC activation The SPI_M runs a MAC activation as defined in Annex C, clause C.1.1 with the values provided by the SPI_S in MCT_READY RQ0604_015 2 SPI_M → TT(SPI_S) Assert SPI_N... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.1.3.4 Post condition | All sequences of this test case require the post-processing procedure defined in clause 6.0.6 to be executed. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.1.4 5 signals SPI - AC characteristics for operational voltage class C | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.1.4.1 Test purpose | To comply to ETSI TS 103 713 [1] an SPI bus shall have implemented the SPI mode 0 according to the industry de-facto SPI specification. Timing parameters indicated in ETSI TS 103 713 [1], table 6.4 are reference values for generic SPI slaves and therefore have to be supported by the SPI master. For determination of AC ... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.1.4.2 Initial conditions | The initial conditions listed in clause 6.0.1 and clause 6.0.3 apply: 1) The preparation procedure for SPI master AC testing from clause 6.0.4 is executed. 2) The SPI slave asserts SPI_INT for a 1 µs pulse (or known duration T2) for a MAC access request. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.1.4.3 Test procedure | Sequence 1 - Determination of clock specific AC characteristics Step Direction Action/Task Description/Expectation REQ 1 SPI_M → TT(SPI_S) Run MAC activation The SPI_M runs a MAC activation as defined in Annex C, clause C.1.1 with the values provided by the SPI_S in MCT_READY RQ0604_015 2 SPI_M → TT(SPI_S) Assert SPI_N... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.1.4.4 Post condition | All sequences of this test case require the post-processing procedure defined in clause 6.0.6 to be executed. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.2 Electrical characteristics - 5 signals SPI - SPI Slave testing | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.2.1 5 signals SPI - Class B, AC characteristics for slave driven signals | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.2.1.1 Test purpose | To comply to ETSI TS 103 713 [1] an SPI bus shall have implemented the SPI mode 0 according to the industry de- facto SPI specification. Timing parameters indicated in ETSI TS 103 713 [1], table 6.4 are reference values for generic SPI slaves and therefore have to be supported by the SPI slave. To allow determination o... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.2.1.2 Initial conditions | 1) The initial conditions listed in clause 6.0.1 and clause 6.0.3 apply. 2) The preparation procedure for SPI slave AC testing from clause 6.0.5 is executed. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.2.1.3 Test procedure | Sequence 1 Step Direction Action/Task Description/Expectation REQ 1 TT(SPI_M) → SPI_S Run MAC activation The SPI_M runs a MAC activation as defined in Annex C, clause C.1.1 with the values provided by the SPI_S in MCT_READY RQ0604_015 2 TT(SPI_M) → SPI_S Assert SPI_NSS The SPI_M asserts SPI_NSS The TT stores time stamp... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.2.1.4 Post condition | The post-processing procedure defined in clause 6.0.6 shall be executed. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.2.2 5 signals SPI - Class C, AC characteristics for slave driven signals | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.2.2.1 Test purpose | To comply to ETSI TS 103 713 [1] an SPI bus shall have implemented the SPI mode 0 according to the industry de-facto SPI specification. Timing parameters indicated in ETSI TS 103 713 [1], table 6.4 are reference values for generic SPI slaves and therefore have to be supported by the SPI slave. For determination of AC c... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.2.2.2 Initial conditions | 1) The initial conditions listed in clause 6.0.1 and clause 6.0.3 apply. 2) The preparation procedure for SPI slave AC testing from clause 6.0.5 is executed. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.2.2.3 Test procedure | Sequence 1 Step Direction Action/Task Description/Expectation REQ 1 TT(SPI_M) Run MAC activation The SPI_M runs a MAC activation as defined in Annex C, clause C.1.1 with the values provided by the SPI_S in MCT_READY RQ0604_015 2 TT(SPI_M) Assert SPI_NSS The SPI_M asserts SPI_NSS The TT stores time stamp #1 3 SPI_S → TT... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.2.2.4 Post condition | The post-processing procedure defined in clause 6.0.6 shall be executed. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.3 Electrical characteristics - 4 signals SPI - SPI Master testing | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.3.1 4 signals SPI - DC characteristics for operational voltage class B | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.3.1.1 Test purpose | The SPI Electrical specification interface shall be defined for VDD operational voltage classes B and C as defined in ETSI TS 103 666-1 [4], clause 6.2.2.3. For the SPI physical interface with 4 signals operating in voltage class B the DC characteristics defined in ETSI TS 103 713 [1], table 6.2 apply. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.3.1.2 Initial conditions | 1) The initial conditions listed in clause 6.0.1 and clause 6.0.2 apply. 2) The technology dependent high impedance values for the input and output buffers connected to the SPI are used to adjust the slave emulation characteristics of the TT. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.3.1.3 Test procedure | Sequence 1 Step Direction Action/Task Description/Expectation REQ 1 SPI_M → TT(SPI_S) Run MAC activation The SPI_M runs a MAC activation as defined in Annex C, clause C.2.1 RQ0702_038 TT Run voltage measurement on VDD VDD*1 is within the limits defined for voltage class B (2,7 V - 3,3 V) RQ0604_001 2 TT Run voltage mea... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.3.1.4 Post conditions | The SPI is powered off, i.e. the power supply for the PCB or chip hosting the SPI is switched off. |
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