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b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.3.2 4 signals SPI - DC characteristics for operational voltage class C | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.3.2.1 Test purpose | The SPI Electrical specification interface shall be defined for VDD operational voltage classes B and C as defined in ETSI TS 103 666-1 [4], clause 6.2.2.3. For the SPI physical interface with 4 signals operating in voltage class C the DC characteristics defined in ETSI TS 103 713 [1], table 6.3 apply. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.3.2.2 Initial conditions | 1) The initial conditions listed in clause 6.0.1 and clause 6.0.2 apply. 2) The technology dependent high impedance values for the input and output buffers connected to the SPI are used to adjust the slave emulation characteristics of the TT. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.3.2.3 Test procedure | Sequence 1 Step Direction Action/Task Description/Expectation REQ 1 SPI_M → TT(SPI_S) Run MAC activation The SPI_M runs a MAC activation as defined in Annex C, clause C.2.1 RQ0702_038 TT Run voltage measurement on VDD VDD*1 is within the limits defined for voltage class C (1,62 V - 1,98 V) RQ0604_001 2 TT Run voltage m... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.3.2.4 Post conditions | The SPI is powered off, i.e. the power supply for the PCB or chip hosting the SPI is switched off. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.3.3 4 signals SPI - AC characteristics for operational voltage class B | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.3.3.1 Test purpose | To comply to ETSI TS 103 713 [1] an SPI bus shall have implemented the SPI mode 0 according to the industry de- facto SPI specification. Timing parameters indicated in ETSI TS 103 713 [1], Table 6.4 are reference values for generic SPI slaves and therefore have to be supported by the SPI master. For determination of AC... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.3.3.2 Initial conditions | 1) The initial conditions listed in clause 6.0.1 and clause 6.0.3 apply. 2) The preparation procedure for SPI master AC testing from clause 6.0.4 is executed. 3) The SPI slave asserts SPI_NSS for a 1 µs pulse (or known duration T2) for a MAC access request. ETSI ETSI TS 103 813 V15.1.0 (2022-02) 54 Release 15 |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.3.3.3 Test procedure | Sequence 1 - Determination of clock specific AC characteristics See clause 6.1.3.3 - Sequence 1. The test procedure is identical for 4 signals and for 5 signals SPI. Sequence 2 - Determination of assertion related AC characteristics See clause 6.1.3.3 - Sequence 2. The test procedure is identical for 4 signals and for ... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.3.3.4 Post condition | All sequences of this test case require the post-processing procedure defined in clause 6.0.6 to be executed. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.3.4 4 signals SPI - AC characteristics for operational voltage class C | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.3.4.1 Test purpose | To comply to ETSI TS 103 713 [1] an SPI bus shall have implemented the SPI mode 0 according to the industry de-facto SPI specification. Timing parameters indicated in ETSI TS 103 713 [1], Table 6.4 are reference values for generic SPI slaves and therefore have to be supported by the SPI master. For determination of AC ... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.3.4.2 Initial conditions | 1) The initial conditions listed in clause 6.0.1 and clause 6.0.3 apply. 2) The preparation procedure for SPI master AC testing from clause 6.0.4 is executed. 3) The SPI slave asserts SPI_NSS for a 1 µs pulse (or known duration T2) for a MAC access request. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.3.4.3 Test procedure | Sequence 1 - Determination of clock specific AC characteristics See clause 6.1.4.3 - Sequence 1. The test procedure is identical for 4 signals and for 5 signals SPI. Sequence 2 - Determination of assertion related AC characteristics See clause 6.1.4.3 - Sequence 2. The test procedure is identical for 4 signals and for ... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.3.4.4 Post condition | The post-processing procedure defined in clause 6.0.6 shall be executed. ETSI ETSI TS 103 813 V15.1.0 (2022-02) 55 Release 15 |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.4 Electrical characteristics - 4 signals SPI - SPI Slave testing | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.4.1 4 signals SPI - Class B, AC characteristics for slave driven signals | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.4.1.1 Test purpose | To comply to ETSI TS 103 713 [1] an SPI bus shall have implemented the SPI mode 0 according to the industry de-facto SPI specification. Timing parameters indicated in ETSI TS 103 713 [1], table 6.4 are reference values for generic SPI slaves and therefore have to be supported by the SPI slave. For determination of AC c... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.4.1.2 Initial conditions | 1) The initial conditions listed in clause 6.0.1 and clause 6.0.3 apply. 2) The preparation procedure for SPI slave AC testing from clause 6.0.5 is executed. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.4.1.3 Test procedure | Sequence 1 See clause 6.2.1.3. The test procedure is identical for 4 signals and for 5 signals SPI. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.4.1.4 Post condition | The post-processing procedure defined in clause 6.0.6 shall be executed. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.4.2 4 signals SPI - Class C, AC characteristics for slave driven signals | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.4.2.1 Test purpose | To comply to ETSI TS 103 713 [1] an SPI bus shall have implemented the SPI mode 0 according to the industry de-facto SPI specification. Timing parameters indicated in ETSI TS 103 713 [1], table 6.4 are reference values for generic SPI slaves and therefore have to be supported by the SPI slave. For determination of AC c... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.4.2.2 Initial conditions | 1) The initial conditions listed in clause 6.0.1 and clause 6.0.3 apply. 2) The preparation procedure for SPI slave AC testing from clause 6.0.5 is executed. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.4.2.3 Test procedure | Sequence 1 See clause 6.2.2.3. The test procedure is identical for 4 signals and for 5 signals SPI. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.4.2.4 Post condition | The post-processing procedure defined in clause 6.0.6 shall be executed. ETSI ETSI TS 103 813 V15.1.0 (2022-02) 56 Release 15 |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.5 Verification of slave states - SPI Slave testing | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.5.0 Explanation of slave states | The slave allows SPI shared bus and states. Thus, the signals SPI_MISO, SPI_MOSI and SPI_CLK may be shared between multiple slaves. However, each slave has a dedicated SPI_NSS. To allow proper operation the slave shall be in one of the following states: • Initial state • Configured state • Pro-active state • Busy state... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.5.1 Initial state | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.5.1.1 Test purpose | The slave enters the initial state as soon as it is powered on and VDD is valid or after a reset. In this state, the slave is not initialized and the SPI module is not ready to send or receive any data. The master shall not perform any SPI access while the slave is in this state. The initial state is tested implicitly ... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.5.1.2 Initial condition | 1) The test environment shown in Figure 4.2 is used. 2) Depending on the architecture of the SPI the TT Connector either supports the testing architecture shown in Figure 4.4 for a 4 signals SPI or the testing architecture shown in Figure 4.3 for a 5 signals SPI. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.5.1.3 Test procedure | Sequence 1 - Initial state after VDD valid Step Direction Action/Task Description/Expectation REQ 1 TT(SPI_M) → SPI_S Run MAC activation The SPI_M runs a MAC activation as defined in Annex C, clause C.1.1 (5 signals SPI) or C.2.1 (4 signals SPI) TT Trace activities on SPI_MISO, SPI_NSS and SPI_INT (if available) for at... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.5.2 Configured state | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.5.2.1 Test purpose | The slave in configured state has two sub states. In de-selected sub-state, the slave SPI module is enabled, i.e. it shall not ignore SPI_NSS assertion by master and shall be ready for an SPI access. The slave is waiting for a master access. As a consequence, the slave shall have SPI_MISO in high impedance and shall ig... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.5.2.2 Initial condition | 1) The test environment shown in Figure 4.2 is used. 2) Depending on the architecture of the SPI the TT Connector either supports the testing architecture shown in Figure 4.4 for a 4 signals SPI or the testing architecture shown in Figure 4.3 for a 5 signals SPI. ETSI ETSI TS 103 813 V15.1.0 (2022-02) 58 Release 15 |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.5.2.3 Test procedure | Sequence 1 - Configured state, de-selected sub-state during activation Step Direction Action/Task Description/Expectation REQ 1 TT(SPI_M) → SPI_S Run MAC activation SPI_M runs a MAC activation as defined in Annex C, clause C.1.1 (5 signals SPI) or C.2.1 (4 signals SPI) 2 SPI_S Switch to state configured/de- selected Af... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.5.3 5 signals SPI - Pro-active state | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.5.3.1 Test purpose | The Pro-active state is entered by the slave when data need to be sent. The slave in a 5 signal SPI issues a MAC access request by asserting SPI_INT. The slave enters this state for the duration of T2, as described in ETSI TS 103 713 [1] clause 7.2.3.2. The slave exits this state on its own after T2, regardless of the ... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.5.3.2 Initial condition | 1) The test environment shown in Figure 4.2 is used. 2) The TT Connector supports the testing architectures shown in Figure 4.3 for a 5 signals SPI. ETSI ETSI TS 103 813 V15.1.0 (2022-02) 61 Release 15 |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.5.3.3 Test procedure | Sequence 1 - Pro-active state, MAC access request from slave, return to configured/de-selected state Step Direction Action/Task Description/Expectation REQ 1 TT(SPI_M) → SPI_S Run MAC activation The SPI_M runs a MAC activation as defined in Annex C, clause C.1.1 2 TT(SPI_M) → SPI_S Assert SPI_NSS Activate SPI_CLK (1 MH... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.5.4 4 signals SPI - Pro-active state | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.5.4.1 Test purpose | The Pro-active state is entered by the slave when data need to be sent. The slave in a 4 signals SPI issues a MAC access request by asserting the SPI_NSS. The slave enters this state for the duration of T2, as described in ETSI TS 103 713 [1] clause 7.2.4.3. The slave exits this state on its own after T2, regardless of... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.5.4.2 Initial condition | 1) The test environment shown in Figure 4.2 is used. 2) The TT Connector supports the testing architectures shown in Figure 4.4 for a 4 signals SPI. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.5.4.3 Test procedure | Sequence 1 - Pro-active state, MAC access request from slave, return to configured/de-selected state Step Direction Action/Task Description/Expectation REQ 1 TT(SPI_M) → SPI_S Run MAC activation The SPI_M runs a MAC activation as defined in Annex C, clause C.2.1 2 TT(SPI_M) → SPI_S Assert SPI_NSS Activate SPI_CLK (1 MH... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.5.5 4 signals SPI - Busy state | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.5.5.1 Test purpose | The busy state is an optional state applicable for the 4 signal SPI only when the slave performs the optional slave driven flow control by keeping SPI_NSS asserted following the configured/selected state. FFS |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.5.6 Power saving mode state | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 6.5.6.1 Test purpose | The Power saving mode state is entered by the slave to reduce the power consumption. Entry and exit conditions are described in ETSI TS 103 713 [1] clause 7.8. Tests appropriate for the power saving mode and power saving mode state are defined in clause 13 - Power management. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7 Test cases for data link layer- MAC Layer | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.0 Common conditions for data link layer test cases | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.0.1 Pre-condition for data link layer test cases | A master is connected to a single slave in accordance to the definitions given in ETSI TS 103 713 [1] for 4 signals or 5 signals SPI. The SPI test tool (TT) is connected as defined in the testing architectures in clause 4.1.1 or 4.1.2. ETSI ETSI TS 103 813 V15.1.0 (2022-02) 64 Release 15 |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.0.2 MAC parameter determination procedure - SPI Master testing | Step Direction Action/Task Description/Expectation 0.1 TT/Tester Power on The power supply of the PCB hosting the SPI is switched on 0.2 SPI_M → TT(SPI_S) Run MAC activation The SPI_M runs a MAC activation as defined in Annex C, clause C.1.1 (5 signals SPI) or C.2.1 (4 signals SPI) 0.3 SPI_M → TT(SPI_S) Activate SPI_CL... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.0.3 MAC parameter determination procedure - SPI Slave testing | Step Direction Action/Task Description/Expectation 0.1 TT/Tester Power on The power supply of the PCB hosting the SPI is switched on 0.2 TT(SPI_M) → SPI_S Run MAC activation The SPI_M runs a MAC activation as defined in Annex C, clause C.1.1 (5 signals SPI) or C.2.1 (4 signals SPI) 0.3 TT(SPI_M) → SPI_S Activate SPI_CL... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.0.4 Post-condition for data link layer test cases | Step Direction Action/Task Description/Expectation REQ n.1 SPI_M → SPI_S Run MAC deactivation SPI The SPI_M runs a MAC deactivation as defined in Annex C, clause C.1.2 (5 signals SPI) or C.2.2 (4 signals SPI) ETSI ETSI TS 103 813 V15.1.0 (2022-02) 65 Release 15 |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.1 MAC Layer - 5 signals SPI - SPI Master testing | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.1.1 5 signals SPI - Master behaviour during initial data transfer initiation | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.1.1.1 Test purpose | After powering on the SPI the MCT is executed. Timing values and the behaviour of the master during initial MCT and the following data transfer phase is checked. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.1.1.2 Initial conditions | 1) The test environment shown in Figure 4.1 is used. - The slave is emulated to ensure that the specific parameters given in the MCT_READY_CONF frame are send during MCT LLC setup. 2) The testing architecture described in Figure 4.3 is used. 3) Initial parameters shall be considered: - POT: 1 s - SPI_CLK: 1 MHz - T1: 2... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.1.1.3 Test procedure | Sequence 1 Step Direction Action/Task Description/Expectation REQ 1 TT/Tester Power on The power supply of the PCB hosting the SPI is switched on 2 SPI_M → TT(SPI_S) Run MAC activation The SPI_M runs a MAC activation as defined in Annex C, clause C.1.1 RQ0702_001 RQ0702_018 TT Generate time stamp for switching on VDD 3... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.1.1.4 Post-condition | The general post-condition for data link layer test cases as defined in clause 7.0.4 shall be executed at the end the sequence. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.1.2 5 signals SPI - Master behaviour during data transfer initiation | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.1.2.1 Test purpose | After powering on the SPI the MCT is executed. Timing values and the behaviour of the master during MCT and the following data transfer phase is checked. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.1.2.2 Initial conditions | 1) The test environment shown in Figure 4.1 is used. - The slave is emulated to ensure that the specific parameters given in the MCT_READY_CONF frame are sent during MCT LLC setup. 2) The testing architecture described in Figure 4.3 is used. 3) Parameters negotiated in the initial MCT phase shall be considered, where t... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.1.2.3 Test procedure | Sequence 1 - Data transfer initiation with formerly negotiated MCT_DATA Step Direction Action/Task Description/Expectation REQ 1 SPI_M → TT(SPI_S) Run MAC activation The SPI_M runs a MAC activation as defined in Annex C, clause C.1.1 RQ0702_001 RQ0702_018 TT Generate time stamp for switching on VDD 2 SPI_M → TT(SPI_S) ... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.1.2.4 Post-condition | The general post-condition for data link layer test cases as defined in clause 7.0.4 shall be executed at the end the sequence. 7.1.3 5 signals SPI - Master behaviour during simultaneous data transfer initiation |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.1.3.1 Test purpose | After SPI activation the MCT is executed. SPI master behaviour is tested during the simultaneous initiations from the master and the slave. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.1.3.2 Initial conditions | 1) The test environment shown in Figure 4.1 is used. - The slave is emulated to ensure that the specific parameters given in the MCT_READY frame can be fulfilled. 2) To properly handle the SPI master parameters either test case 7.1.1 or the MAC parameter determination procedure from clause 7.0.2 shall be executed. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.1.3.3 Test procedure | Sequence 1 Step Direction Action/Task Description/Expectation REQ 1 SPI_M → TT(SPI_S) Run MAC activation The SPI_M runs a MAC activation as defined in Annex C, clause C.1.1 RQ0702_018 RQ0702_001 2 SPI_M → TT(SPI_S) Send MCT_MASTER_REQ The SPI_S receives the MCT_MASTER_REQ RQ0706_004 3 TT(SPI_S) Wait for MCT_SLAVE_TIMEO... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.1.3.4 Post-condition | The general post-condition for data link layer test cases as defined in clause 7.0.2 is executed at the end of the test case. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.1.4 5 signals SPI - MAC deactivation | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.1.4.1 Test purpose | The SPI master behaviour during power off is tested. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.1.4.2 Initial conditions | 1) The test environment shown in Figure 4.1 is used. - The slave is emulated to ensure that no signal line is asserted by the slave during testing. - The SPI master is the SUT. 2) To properly handle the SPI master parameters either test case 7.1.1 or the MAC parameter determination procedure from clause 7.0.2 shall be ... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.1.4.3 Test procedure | Sequence 1 Step Direction Action/Task Description/Expectation REQ 1 SPI_M → TT(SPI_S) Run MAC activation The SPI_M runs a MAC activation as defined in Annex C, clause C.1.1 RQ0702_018 RQ0702_001 2 SPI_M → TT(SPI_S) Send MCT_MASTER_REQ The SPI_S receives the MCT_MASTER_REQ RQ0706_004 3 TT(SPI_S) → SPI_M Send MCT_READY_D... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.1.4.4 Post-condition | The general post-condition for data link layer test cases as defined in clause 7.0.4 is executed at the end of the test case. ETSI ETSI TS 103 813 V15.1.0 (2022-02) 69 Release 15 |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.2 MAC Layer - 5 signals SPI - SPI Slave testing | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.2.1 5 signals SPI - Slave behaviour at initial MAC activation | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.2.1.1 Test purpose | The initial MAC activation is executed. The slave behaviour is tested for an initial MCT phase performed with SPI_CLK = 1 MHz and POT = 1 s. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.2.1.2 Initial conditions | 1) The test environment shown in Figure 4.2 is used. - The master is emulated to ensure that default parameters are used during initial MAC activation and data transfer. - The SPI slave is the SUT. 2) To properly handle the SPI slave parameters the MAC parameter determination procedure from clause 7.0.3 shall be execut... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.2.1.3 Test procedure | Sequence 1 Step Direction Action/Task Description/Expectation REQ 1 TT(SPI_M) → SPI_S Run MAC activation The SPI_M runs a MAC activation as defined in Annex C, clause C.1.1 2 TT(SPI_M) → SPI_S Initiate a data transfer for the MAC phase Toggle SPI_CLK with 1 MHz after a delay of 1 s (POT) after switching on VDD 3 TT(SPI... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.2.1.4 Post-condition | The general post-condition for data link layer test cases as defined in clause 7.0.4 is executed at the end of the test case. ETSI ETSI TS 103 813 V15.1.0 (2022-02) 70 Release 15 7.2.2 5 signals SPI - Slave behaviour during data transfer initiation - nominal test |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.2.2.1 Test purpose | The MAC activation is executed. The slave behaviour during data transfer initiation with negotiated MCT timing is tested. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.2.2.2 Initial conditions | 1) The test environment shown in Figure 4.2 is used. - The master is emulated to ensure that the parameters provided in the initial MCT_READY are used during MAC activation and data transfer. - The SPI slave is the SUT. 2) To properly handle the SPI slave parameters the MAC parameter determination procedure from clause... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.2.2.3 Test procedure | Sequence 1 Step Direction Action/Task Description/Expectation REQ 1 TT(SPI_M) → SPI_S Run MAC activation The SPI_M runs a MAC activation as defined in Annex C, clause C.1.1 2 TT(SPI_M) → SPI_S Send MCT_MASTER_REQ_DEF The SPI_S receives the predefined MCT_MASTER_REQ 3 TT(SPI_M) → SPI_S De-assert SPI_NSS After the data t... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.2.2.4 Post-condition | The general post-condition for data link layer test cases as defined in clause 7.0.4 is executed at the end of the test case. 7.2.3 5 signals SPI - Slave behaviour during data transfer initiation by the slave |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.2.3.1 Test purpose | After MCT_MASTER_REQ is sent the master keeps the NSS line asserted. The slave shall not assert the SPI_INT while the NSS is asserted. ETSI ETSI TS 103 813 V15.1.0 (2022-02) 71 Release 15 |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.2.3.2 Initial conditions | 1) The test environment shown in Figure 4.2 is used. - The master is emulated to ensure that default parameters are used during initial MAC activation and data transfer. - The SPI slave is the SUT. 2) To properly handle the SPI slave parameters the MAC parameter determination procedure from clause 7.0.3 shall be execut... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.2.3.3 Test procedure | Sequence 1 Step Direction Action/Task Description/Expectation REQ 1 TT(SPI_M) → SPI_S Run MAC activation The SPI_M runs a MAC activation as defined in Annex C, clause C.1.1 2 TT(SPI_M) → SPI_S Send MCT_MASTER_REQ_DEF frame The SPI_S receives the pre-defined MCT_MASTER_REQ frame 3 TT(SPI_M) → SPI_S Keep SPI_NSS asserted... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.2.3.4 Post-condition | The general post-condition for data link layer test cases as defined in clause 7.0.2 is executed at the end of the test case. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.3 MAC Layer - 4 signals SPI - SPI Master testing | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.3.1 4 signals SPI - Master behaviour during initial data transfer initiation | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.3.1.1 Test purpose | After powering on the SPI the MCT is executed. Timing values and the behaviour of the master during initial MCT and the following data transfer phase is checked. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.3.1.2 Initial conditions | 1) The test environment shown in Figure 4.1 is used. - The slave is emulated to ensure that the specific parameters given in the MCT_READY_CONF frame are sent during MCT LLC setup. ETSI ETSI TS 103 813 V15.1.0 (2022-02) 72 Release 15 2) The testing architecture described in Figure 4.4 is used. 3) Initial parameters sha... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.3.1.3 Test procedure | Sequence 1 Step Direction Action/Task Description/Expectation REQ 1 TT/Tester Power on The power supply of the PCB hosting the SPI is switched on 2 SPI_M → TT(SPI_S) Run MAC activation The SPI_M runs a MAC activation as defined in Annex C, clause C.2.1 RQ0702_019 RQ0702_038 TT Generate time stamp for switching on VDD 3... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.3.1.4 Post-condition | The general post-condition for data link layer test cases as defined in clause 7.0.4 shall be executed at the end of the sequence. |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.3.2 4 signal SPI - Master behaviour during data transfer initiation | |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.3.2.1 Test purpose | After powering on the SPI the MCT is executed. Timing values and the behaviour of the master during MCT and the following data transfer phase is checked. ETSI ETSI TS 103 813 V15.1.0 (2022-02) 73 Release 15 |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.3.2.2 Initial conditions | 1) The test environment shown in Figure 4.1 is used. - The slave is emulated to ensure that the specific parameters given in the MCT_READY_CONF frame are send during MCT LLC setup. 2) The testing architectures described in Figure 4.4 are used. 3) Parameters negotiated in the initial MCT phase shall be considered, where... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.3.2.3 Test procedure | Sequence 1 - Data transfer initiation with formerly negotiated MCT_DATA Step Direction Action/Task Description/Expectation REQ 1 SPI_M → TT(SPI_S) Run MAC activation The SPI_M runs a MAC activation as defined in Annex C, clause C.2.1 RQ0702_038 TT Generate time stamp for switching on VDD 2 SPI_M → TT(SPI_S) Assert SPI_... |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.3.2.4 Post-condition | The general post-condition for data link layer test cases as defined in clause 7.0.4 shall be executed at the end of the sequence. 7.3.3 4 signal SPI - Master behaviour during simultaneous data transfer initiation |
b61a0bf651537071c0010f2ac77f17ba | 103 813 | 7.3.3.1 Test purpose | After SPI activation the MCT is executed. SPI master behaviour is tested during the simultaneous initiations from the master and the slave. |
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