hash
stringlengths
32
32
doc_id
stringlengths
7
13
section
stringlengths
3
121
content
stringlengths
0
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9.1.3.4 Post conditions
The SPI is powered off, i.e. the power supply for the PCB or chip hosting the SPI is switched off.
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10 Test cases for interworking of the LLC layers
FFS.
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11 Test cases for MCT LLC
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11.1 MCT LLC - SPI Master testing
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11.1.1 Behaviour during MCT activation - no MCT_READY response
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11.1.1.1 Test purpose
SPI master behaviour is tested during the MCT activation when the slave does not send MCT_READY response within MCT_SLAVE_TIMEOUT.
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11.1.1.2 Initial conditions
The test environment shown in Figure 4.1 is used. β€’ The slave is emulated to ensure that no MCT_READY frame is sent during MCT LLC setup.
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11.1.1.3 Test procedure
Sequence 1 Step Direction Action/Task Description/Expectation REQ 1 SPI_M β†’ TT(SPI_S) Run MAC activation The SPI_M runs a MAC activation as defined in Annex C, clause C.1.1 or clause C.2.1 RQ0702_018 RQ0702_038 2 SPI_M β†’ TT(SPI_S) Send MCT_MASTER_REQ The SPI_S receives the MCT_MASTER_REQ 3 TT(SPI_S) Wait for a period l...
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11.1.1.4 Post conditions
The SPI is powered off, i.e. the power supply for the PCB or chip hosting the SPI is switched off.
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11.1.2 MCT_MASTER_REQ values
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11.1.2.1 Test purpose
Some MCT_MASTER_REQ values are read and compared to the IUT options declared by the vendor.
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11.1.2.2 Initial conditions
The test environment shown in Figure 4.1 is used. β€’ The slave is emulated to ensure that the MCT_READY frame is not limiting the data transfer suggested by the master.
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11.1.2.3 Test procedure
Sequence 1 Step Direction Action/Task Description/Expectation REQ 1 SPI_ M β†’ TT(SPI_S) Run MAC activation The SPI_M runs a MAC activation as defined in Annex C, clause C.1.1 or clause C.2.1 RQ0702_018 RQ0702_038 2 SPI_M β†’ TT(SPI_S) Send MCT_MASTER_REQ frame The SPI_S receives the MCT_MASTER_REQ frame with Master-specif...
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11.1.2.4 Post conditions
The SPI is powered off, i.e. the power supply for the PCB or chip hosting the SPI is switched off.
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11.2 MCT LLC - SPI Slave testing
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11.2.1 MCT activation - corrupted MCT_MASTER_REQ response
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11.2.1.1 Test purpose
SPI slave behaviour is tested during the MCT activation when the master sends a corrupted MCT_MASTER_REQ.
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11.2.1.2 Initial conditions
The test environment shown in Figure 4.2 is used. β€’ The master is emulated to ensure that a corrupted MCT_MASTER_REQ_NC frame and a correct MCT_MASTER_REQ can be send.
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11.2.1.3 Test procedure
Sequence 1 Step Direction Action/Task Description/Expectation REQ 1 TT(SPI_M) β†’ SPI_S Run MAC activation The SPI_M runs a MAC activation as defined in Annex C, clause C.1.1 or clause C.2.1 2 TT(SPI_M) β†’ SPI_S Send MCT_MASTER_REQ_NC 3 SPI_S Wait No MCT_READY is received by the master within MCT_SLAVE_TIMEOUT RQ0706_021 ...
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11.2.1.4 Post conditions
The SPI is powered off, i.e. the power supply for the PCB or chip hosting the SPI is switched off. ETSI ETSI TS 103 813 V15.1.0 (2022-02) 91 Release 15
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11.2.2 MCT_READY values
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11.2.2.1 Test purpose
Some MCT_READY values are read and compared to the SUT options declared by the vendor.
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11.2.2.2 Initial conditions
The test environment shown in Figure 4.2 is used. β€’ The master is emulated to ensure that the MCT_MASTER_CONF frame can be sent to not limit the capabilities that are returned in the MCT_READY.
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11.2.2.3 Test procedure
Sequence 1 Step Direction Action/Task Description/Expectation REQ 1 TT(SPI_M) β†’ SPI_S Run MAC activation The SPI_M runs a MAC activation as defined in Annex C, clause C.1.1 or clause C.2.1 2 TT(SPI_M) β†’ SPI_S Send MCT_MASTER_REQ_CONF The SPI_S receives a predefined MCT_MASTER_REQ 3 SPI_S β†’ TT(SPI_M) Send MCT_READY fram...
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11.2.2.4 Post conditions
The SPI is powered off, i.e. the power supply for the PCB or chip hosting the SPI is switched off. ETSI ETSI TS 103 813 V15.1.0 (2022-02) 92 Release 15
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12 Test cases for SHDLC LLC
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12.0 SHDLC LLC Overview
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12.0.1 General considerations
SHDLC LLC testing is using endpoints. For the endpoints, definitions from Annex A, clause A.4 apply: β€’ The SUT may be either the master endpoint or the slave endpoint. β€’ The TT may be either the master endpoint or the slave endpoint. NOTE: The requirements for this clause are taken from ETSI TS 102 613 [5].
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12.1 SHDLC LLC Data handling
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12.1.1 Error management - corrupted I-frame
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12.1.1.1 Test purpose
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12.1.1.2 Initial Conditions
SHDLC link is established and idle, i.e. no further communication is expected.
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12.1.1.3 Test procedure
Sequence 1 Step Direction Action/Task Description/Expectation REQ 1 SUT οƒ  TT Send a corrupted I-frame(NS0_S,x) 2 TT οƒ  SUT The TT does not send an acknowledgment RX1001_002 3 SUT οƒ  TT The SUT waits 10 ms and sends a correct I-frame(NS0_S,x) 4 TT οƒ  SUT Acknowledge the received I-frame
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12.1.2 Error management - corrupted RR frame
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12.1.2.1 Test purpose
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12.1.2.2 Initial Conditions
SHDLC link is established and idle, i.e. no further communication is expected.
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12.1.2.3 Test procedure
Sequence 1 Step Direction Action/Task Description/Expectation REQ 1 SUT οƒ  TT Trigger the TT to send an I-frame 2 TT οƒ  SUT Send I(NS0_T,x) RX1001_002 3 SUT οƒ  TT Send a corrupted RR(NS0_T+1) frame 4 SUT Wait T2 time and do not acknowledge the received frame ETSI ETSI TS 103 813 V15.1.0 (2022-02) 93 Release 15 Step Direct...
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12.2 SHDLC context
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12.2.1 Initial state at link reset - reset by the SUT
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12.2.1.1 Test purpose
To ascertain that the SUT is in the correct initial state when the link is reset by the SUT.
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12.2.1.2 Initial conditions
SHDLC link is established and idle, i.e. no further communication is expected.
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12.2.1.3 Test procedure
Sequence 1 Step Direction Action/Task Description/Expectation REQ 1 SUT οƒ  TT Send RSET(Ws=2, SREJ=0) 2 TT οƒ  SUT Send UA 3 Conditional TT sends I-frame after link establishment or when triggered. If the TT does not immediately send I-frames after SHDLC link establishment, trigger the TT to send an I-frame. If the trigge...
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12.3 SHDLC sequence of frames
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12.3.1 Link establishment by the SUT with default sliding window size
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12.3.1.1 Test purpose
To ensure the SUT establishes a link with default sliding window sizes.
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12.3.1.2 Initial conditions
SHDLC link is established and idle, i.e. no further communication is expected.
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12.3.1.3 Test procedure
The test procedure shall only be executed for RSET values, from the following table, that are supported by the SUT. ETSI ETSI TS 103 813 V15.1.0 (2022-02) 94 Release 15 RSET() RSET(2) RSET(3) RSET(4) RSET(2, SREJ=0) RSET(2, SREJ=1) RSET(3, SREJ=0) RSET(3, SREJ=1) RSET(4, SREJ=0) RSET(4, SREJ=1) SREJ should be tested on...
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12.3.2 Link establishment and connection time out
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12.3.2.1 Test purpose
To ensure the correct time outs are applied by the SUT after a link is established.
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12.3.2.2 Initial conditions
None of the SUT contacts is activated.
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12.3.2.3 Test procedure
Sequence 1 Step Direction Action/Task Description/Expectation REQ 1 TT Trigger the TT Activate SPI interface 2 SUT οƒŸοƒ  TT Perform SPI interface activation 3 TT οƒ  SUT Send RSET RX1007_001 4 SUT Do not send a UA frame 5 TT οƒ  SUT Send RSET After at least T3 time after execution of step 3 RX1006_004 6 SUT οƒ  TT Send an I-fra...
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12.3.3.1 Test purpose
To ensure that the SUT accepts correct window size values when the link is reset.
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12.3.3.2 Initial conditions
SHDLC link is established.
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12.3.3.3 Test procedure
Run sequence 1 for every row in the table below. If the SUT supports window size 4, the first row (RSET()) shall be skipped. RSET frame to be sent in step 1 Valid RSET frames which can be received in step 2 RSET() RSET(3) RSET(2) RSET(3, SREJ=0) RSET(2, SREJ=0) RSET(4, SREJ=1) RSET() RSET(4) RSET(4, SREJ=0) RSET(3) RSE...
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12.3.4 Discard buffered frames on link re-establishment
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12.3.4.1 Test purpose
To ensure the SUT discards buffer frames when a link is re-established.
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12.3.4.2 Initial conditions
1) The SHDLC link is established with SREJ support. 2) SHDLC link is idle, i.e. no further communication expected. ETSI ETSI TS 103 813 V15.1.0 (2022-02) 96 Release 15
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12.3.4.3 Test procedure
Sequence 1 Step Direction Action/Task Description/Expectation REQ 1 SUT οƒ  TT Send I-frame(NS0_S,x) 2 TT οƒ  SUT Acknowledges I-frame(NS0_S,x) 3 SUT οƒ  TT Send I-frame(NS0_S+2,x) 4 TT οƒ  SUT Send SREJ(NS0_S+1) 5 SUT οƒŸοƒ  TT Re-establish SHDLC link 6 SUT οƒŸ οƒ  TT SUT sends I-frame(0,NR) to I-frame(NS0_S+1,NR) TT acknowledges the...
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12.4 Data flow
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12.4.1 I-frame transmission
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12.4.1.1 Test purpose
To ensure the SUT correctly handles I-frame transmission.
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12.4.1.2 Initial conditions
1) SHDLC link is established with the window size indicated in the test execution clause. 2) SHDLC link is idle, i.e. no further communication is expected.
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12.4.1.3 Test procedure
Run sequence 1 for: β€’ Every supported window size: - Every I-frame is acknowledged individually by the ES. Sequence 1 Step Direction Action/Task Description/Expectation REQ 1 User οƒ  TT Trigger the TT Send 9 I-frames 2 TT οƒ  SUT SUT οƒ  TT TT send I-frames as indicated in step 1 SUT acknowledges these frames using the ackn...
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12.4.2 I-frame reception - single I-Frame reception
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12.4.2.1 Test purpose
To ensure the SUT correctly sends a number of I-frames one at a time.
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12.4.2.2 Initial conditions
SHDLC link is established and idle, i.e. no further communication is expected. ETSI ETSI TS 103 813 V15.1.0 (2022-02) 97 Release 15
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12.4.2.3 Test procedure
Sequence 1 Step Direction Action/Task Description/Expectation REQ 1 SUT οƒ TT Send 10 I-frames Wait for the acknowledgement of the previously sent I-frame before sending the next I-frame 2 TT οƒ  SUT TT acknowledges these I-frames RX1007_009 RX1006_008 3 conditional If retransmission occurs, perform steps 4 and 5 4 SUT οƒ TT...
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12.4.3 I-frame reception - multiple I-Frame reception
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12.4.3.1 Test purpose
To ensure the SUT correctly sends multiple I-frames with the correct time span.
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12.4.3.2 Initial conditions
1) SHDLC link is established with the window size indicated in the test execution clause. 2) SHDLC link is idle, i.e. no further communication is expected.
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12.4.3.3 Test procedure
Run sequence 1 for every supported window size. Sequence 1 Step Direction Action/Task Description/Expectation REQ 1 SUT οƒ  TT Send 10 I-frames The SUT shall send each I-frame within T1, without waiting for the acknowledgement of the previously sent I-frame, while still complying to the negotiated window size. There shal...
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12.5 Reject (go N back)
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12.5.1 REJ transmission - multiple I-frames received
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12.5.1.1 Test purpose
To ensure the SUT correctly handles REJ transmission with multiple I-frames received.
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12.5.1.2 Initial conditions
1) SHDLC link is established with WS=3 and without SREJ support. 2) SHDLC link is idle, i.e. no further communication is expected.
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12.5.1.3 Test procedure
Sequence 1 Step Direction Action/Task Description/Expectation REQ 1 SUT οƒ  TT Send I-frame(NS0_S,x) 2 TT οƒ  SUT Acknowledge I-frame(NS0_S,x) 3 SUT οƒ  TT Send I-frame(NS0_S+2,x) followed immediately by I-frame(NS0_S+3,x) 4 TT οƒ  SUT Send REJ(NS0_S+1) The SUT is allowed to send additional REJ(NS0_S+1), in response to any add...
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12.5.2 REJ reception
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12.5.2.1 Test purpose
To ensure the SUT correctly handles REJ reception.
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12.5.2.2 Initial conditions
1) SHDLC link is established without SREJ support. 2) SHDLC link is idle, i.e. no further communication is expected.
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12.5.2.3 Test procedure
Sequence 1 Step Direction Action/Task Description/Expectation REQ 1 TT Trigger the TT to send I-frames The TT shall be triggered such that it streams I-frames, as described in B_STREAM_IFRAMES 2 TT οƒ  SUT Send I-frame(NS0_TT, y) 3 SUT Do not acknowledge I-frame(NS0_TT,y) 4 TT οƒ  SUT Send I-frame(NS0_TT+1,y) 5 SUT οƒ  TT Se...
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12.6 Last Frame Loss
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12.6.1 Retransmission of multiple frames
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12.6.1.1 Test purpose
To ensure the SUT correctly manages the retransmission of multiple frames.
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12.6.1.2 Initial conditions
1) SHDLC link is established without SREJ support. 2) SHDLC link is idle, i.e. no further communication is expected.
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12.6.1.3 Test procedure
Run sequence 1 for: β€’ Every supported window size: - I-frames are acknowledged by the ES just before T1 expires and using the maximum allowed value for NR. Sequence 1 Step Direction Action/Task Description/Expectation REQ 1 User οƒ  TT Trigger the TT to send 9 I-frames 2 TT οƒ  SUT TT send I-frames As indicated in step 1, ...
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12.7 Receive and not ready
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12.7.1 RNR reception
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12.7.1.1 Test purpose
To ensure the SUT correctly manages RNR reception.
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12.7.1.2 Initial conditions
SHDLC link is established and idle, i.e. no further communication is expected. ETSI ETSI TS 103 813 V15.1.0 (2022-02) 100 Release 15
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12.7.1.3 Test procedure
Sequence 1 Step Direction Action/Task Description/Expectation REQ 1 TT Trigger the TT Send 9 non-empty I-frames 2 TT οƒ  SUT Start sending I-frames 3 SUT οƒ  TT Acknowledge the first received I-frame(NSa_TT,x) with RNR(NSa_TT+1) 4 SUT Wait 100 ms RX1007_018 TT οƒ  SUT The TT may send further I-frames within the negotiated WS...
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12.7.2 Empty I-frame transmission
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12.7.2.1 Test purpose
To ensure the SUT correctly manages empty I-frame transmission.
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12.7.2.2 Initial conditions
SHDLC link is established and idle, i.e. no further communication is expected.
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12.7.2.3 Test procedure
Sequence 1 Step Direction Action/Task Description/Expectation REQ 1 TT Trigger the TT Send 1 I-frame 2 TT  SUT Send I-frame(NSa_TT,x) 3 SUT  TT Acknowledge I-frames(NSa_TT,x) with RNR(NSa_tT+1) 4 SUT TT Send RR(NSa_TT+1) 5 TT  SUT Send empty I-frame(NSa_TT+1,x) RX1007_017 6 SUT  TT Send acknowledgement of I-frame(...
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12.8 Selective reject
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12.8.1 SREJ transmission
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12.8.1.1 Test purpose
To ensure the SUT correctly manages SREJ transmission.
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12.8.1.2 Initial conditions
1) The SHDLC link is established with SREJ support. 2) SHDLC link is idle, i.e. no further communication is expected. ETSI ETSI TS 103 813 V15.1.0 (2022-02) 101 Release 15
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12.8.1.3 Test procedure
Sequence 1 Step Direction Action/Task Description/Expectation REQ 1 SUT οƒ  TT Send I-frame(NS0_S,x) 2 TT οƒ  SUT Acknowledge I-frame(NS0_S,x) 3 SUT οƒ  TT Send I-frame(NS0_S+2,x) 4 TT οƒ  SUT Send SREJ(NS0_S+1) RX1008_001 5 SUT οƒ  TT Sends I-frame(NS0_S+1,x) 6 TT οƒ  SUT Acknowledges I-frame(NS0_S+1,x) and I-frame(NS0_S+2,x) 7 S...
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12.8.2 SREJ reception