Add complete 511-case testbench suite
#5
by Zanehpn - opened
No description provided.
Cannot merge
This branch has merge conflicts in the following files:
- testbench/FPGA-MAFIA_fpga_mafia_pr655/open_tool_p2p_buggy.log
- testbench/FPGA-MAFIA_fpga_mafia_pr655/open_tool_p2p_fixed.log
- testbench/FPGA-MAFIA_fpga_mafia_pr655/verilator_buggy_build.log
- testbench/FPGA-MAFIA_fpga_mafia_pr655/verilator_fixed.log
- testbench/FPGA-MAFIA_fpga_mafia_pr655/verilator_fixed_build.log
- testbench/FPGA-MAFIA_fpga_mafia_pr655/verilator_fixed_coverage.info
- testbench/MiSTer-devel_C64_MiSTer_pr142/verilator_buggy_build.log
- testbench/MiSTer-devel_C64_MiSTer_pr142/verilator_fixed_build.log
- testbench/MiSTer-devel_C64_MiSTer_pr142/verilator_fixed_coverage.info
- testbench/MiSTer-devel_NES_MiSTer_pr448/verilator_buggy.log
- testbench/MiSTer-devel_NES_MiSTer_pr448/verilator_buggy_build.log
- testbench/MiSTer-devel_NES_MiSTer_pr448/verilator_fixed.log
- testbench/MiSTer-devel_NES_MiSTer_pr448/verilator_fixed_build.log
- testbench/MiSTer-devel_NES_MiSTer_pr448/verilator_fixed_coverage.info
- testbench/UTOSS_risc-v_pr138/verilator_buggy_build.log
- testbench/UTOSS_risc-v_pr138/verilator_fixed_build.log
- testbench/UTOSS_risc-v_pr138/verilator_fixed_coverage.info
- testbench/alexforencich_verilog-pcie_pr20/verilator_buggy.log
- testbench/alexforencich_verilog-pcie_pr20/verilator_fixed.log
- testbench/alexforencich_verilog-pcie_pr20/verilator_fixed_build.log
- testbench/alexforencich_verilog-pcie_pr20/verilator_fixed_coverage.info
- testbench/alexforencich_verilog-pcie_pr20/yosys_buggy.log
- testbench/alexforencich_verilog-pcie_pr20/yosys_fixed.log
- testbench/bensampson5_libsv_pr100/open_tool_p2p_buggy.log
- testbench/bensampson5_libsv_pr100/open_tool_p2p_fixed.log
- testbench/bensampson5_libsv_pr100/verilator_buggy_build.log
- testbench/bensampson5_libsv_pr100/verilator_fixed.log
- testbench/bensampson5_libsv_pr100/verilator_fixed_build.log
- testbench/bensampson5_libsv_pr100/verilator_fixed_coverage.info
- testbench/bensampson5_libsv_pr106/verilator_buggy_build.log
- testbench/bensampson5_libsv_pr106/verilator_fixed.log
- testbench/bensampson5_libsv_pr106/verilator_fixed_build.log
- testbench/bensampson5_libsv_pr106/verilator_fixed_coverage.info
- testbench/bensampson5_libsv_pr109/open_tool_p2p_buggy.log
- testbench/bensampson5_libsv_pr109/open_tool_p2p_fixed.log
- testbench/bensampson5_libsv_pr109/verilator_buggy_build.log
- testbench/bensampson5_libsv_pr109/verilator_fixed.log
- testbench/bensampson5_libsv_pr109/verilator_fixed_build.log
- testbench/bensampson5_libsv_pr109/verilator_fixed_coverage.info
- testbench/buppu3_tnCart_pr17/verilator_buggy_build.log
- testbench/buppu3_tnCart_pr17/verilator_fixed.log
- testbench/buppu3_tnCart_pr17/verilator_fixed_build.log
- testbench/buppu3_tnCart_pr17/verilator_fixed_coverage.info
- testbench/chipsalliance_Cores-VeeR-EL2_pr151/verilator_buggy_build.log
- testbench/chipsalliance_Cores-VeeR-EL2_pr151/verilator_fixed.log
- testbench/chipsalliance_Cores-VeeR-EL2_pr151/verilator_fixed_build.log
- testbench/chipsalliance_adams-bridge_pr77/open_tool_p2p_buggy.log
- testbench/chipsalliance_adams-bridge_pr77/open_tool_p2p_fixed.log
- testbench/chipsalliance_adams-bridge_pr77/verilator_buggy_build.log
- testbench/chipsalliance_adams-bridge_pr77/verilator_fixed.log
- testbench/chipsalliance_adams-bridge_pr77/verilator_fixed_build.log
- testbench/chipsalliance_adams-bridge_pr77/verilator_fixed_coverage.info
- testbench/jotego_jtcores_pr1169/verilator_buggy_build.log
- testbench/jotego_jtcores_pr1169/verilator_fixed.log
- testbench/jotego_jtcores_pr1169/verilator_fixed_build.log
- testbench/jotego_jtcores_pr1169/verilator_fixed_coverage.info
- testbench/jotego_jtcores_pr1191/verilator_buggy.log
- testbench/jotego_jtcores_pr1191/verilator_buggy_build.log
- testbench/jotego_jtcores_pr1191/verilator_fixed.log
- testbench/jotego_jtcores_pr1191/verilator_fixed_build.log
- testbench/jotego_jtcores_pr1191/verilator_fixed_coverage.info
- testbench/muneeb-mbytes_pulpino__spi_master__ip_verification_pr61/open_tool_p2p_buggy.log
- testbench/muneeb-mbytes_pulpino__spi_master__ip_verification_pr61/open_tool_p2p_fixed.log
- testbench/muneeb-mbytes_pulpino__spi_master__ip_verification_pr61/verilator_fixed_build.log
- testbench/openhwgroup_cve2_pr139/verilator_buggy.log
- testbench/openhwgroup_cve2_pr139/verilator_buggy_build.log
- testbench/openhwgroup_cve2_pr139/verilator_fixed.log
- testbench/openhwgroup_cve2_pr139/verilator_fixed_build.log
- testbench/openhwgroup_cve2_pr139/verilator_fixed_coverage.info
- testbench/pulp-platform_axi_pr224/open_tool_p2p_buggy.log
- testbench/pulp-platform_axi_pr224/open_tool_p2p_fixed.log
- testbench/pulp-platform_axi_pr224/verilator_buggy_build.log
- testbench/pulp-platform_axi_pr224/verilator_fixed.log
- testbench/pulp-platform_axi_pr224/verilator_fixed_build.log
- testbench/pulp-platform_axi_pr224/verilator_fixed_coverage.info
- testbench/pulp-platform_register_interface_pr26/open_tool_p2p_buggy.log
- testbench/pulp-platform_register_interface_pr26/open_tool_p2p_fixed.log
- testbench/pulp-platform_register_interface_pr26/verilator_buggy_build.log
- testbench/pulp-platform_register_interface_pr26/verilator_fixed.log
- testbench/pulp-platform_register_interface_pr26/verilator_fixed_build.log
- testbench/pulp-platform_register_interface_pr26/verilator_fixed_coverage.info
- testbench/pulp-platform_riscv-dbg_pr155/open_tool_p2p_buggy.log
- testbench/pulp-platform_riscv-dbg_pr155/verilator_buggy_build.log
- testbench/pulp-platform_riscv-dbg_pr155/verilator_fixed_coverage.info
- testbench/svunit_svunit_pr113/verilator_buggy_build.log