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<|fim_prefix|>/*
* Copyright (c) 2019 Vestas Wind Systems A/S
* Copyright (c) 2020 Innoseis BV
* Copyright (c) 2023 Cruise LLC
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/adc.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/kerne... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Testo SE & Co. KGaA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/adc.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Vestas Wind Systems A/S
* Copyright (c) 2020 Innoseis BV
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/adc.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/kernel... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Linumiz
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/adc.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/logging/log.h>
#include <zephyr/kernel.h>
#include <ze... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* TI ADS1X1X ADC
*
* Copyright (c) 2021 Facebook, Inc
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdbool.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/adc.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/gp... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>R_IDACMUX_SET_DEFAULTS(idac_mux);
if (channel_cfg->channel_id != 0) {
LOG_ERR("%s: only one channel is supported", dev->name);
return -EINVAL;
}
/* The ADS114 uses samples per seconds units with the lowest being 2.5SPS
* and with acquisition_time only having 14b for time, this will not fit
* ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* TI ADS7052 ADC
*
* Copyright (c) 2023 Google, LLC
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ti_ads7052
#include <zephyr/device.h>
#include <zephyr/drivers/adc.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/logging/log.h>
#include <zephyr/kernel.h>
LOG_MODULE_REGISTER... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* TI ADS79xx Series ADCs
*
* Copyright (c) 2026 James Walmsley <james@fullfat-fs.co.uk>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/drivers/adc.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/logging/log.h>
#include <zephyr/kernel.h>
#include <sys/errn... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Ambiq Micro Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ambiq_adc
#include <zephyr/drivers/adc.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/pm/device.h>
#include <zephyr/pm/device_runtime.h>
#include <zephyr/kernel.h>
#include <zephyr/cach... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>re_scale_e pre_scale;
adc_sample_cycle_e sample_cycl;
adc_input_pin_def_e input_positive;
adc_input_pin_def_e input_negative;
struct b91_adc_data *data = dev->data;
const struct b91_adc_cfg *config = dev->config;
/* Check channel ID */
if (channel_cfg->channel_id > 0) {
LOG_ERR("Only channel 0 i... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>mp &= ~AON_GPADC_NEG_SEL_MASK;
tmp |= (ADC_INPUT_ID_GND << AON_GPADC_POS_SEL_SHIFT);
tmp |= (ADC_INPUT_ID_GND << AON_GPADC_NEG_SEL_SHIFT);
sys_write32(tmp, cfg->reg_AON + AON_GPADC_REG_CMD_OFFSET);
tmp = sys_read32(cfg->reg_GPIP + GPIP_GPADC_CONFIG_OFFSET);
tmp |= GPIP_GPADC_FIFO_CLR;
sys_write32(t... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2022 Florin Stancu <niflostancu@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ti_cc13xx_cc26xx_adc
#include <errno.h>
#define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(adc_cc13xx_cc26xx);
#include <zephyr/device.h>
#includ... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2024 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ti_cc23x0_adc
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(adc_cc23x0, CONFIG_ADC_LOG_LEVEL);
#include <zephyr/device.h>
#include <zephyr/drivers/adc.h>
#include <zephyr/drivers/dma.h>
#include <zephyr/d... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Pavlo Hamov <pasha.gamov@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ti_cc32xx_adc
#include <errno.h>
#include <zephyr/drivers/adc.h>
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/init.h>
#include <soc.h>
/* Driverlib... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
\
DEVICE_DT_INST_DEFINE(n, adc_ch32v00x_init, NULL, NULL, &adc_ch32v00x_config_##n, \
POST_KERNEL, CONFIG_ADC_INIT_PRIORITY, &adc_ch32v00x_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>= 5, .div = 4},
[ADC_GAIN_1] = {.mul = 1, .div = 1},
[ADC_GAIN_2] = {.mul = 1, .div = 2},
[ADC_GAIN_3] = {.mul = 1, .div = 3},
[ADC_GAIN_4] = {.mul = 1, .div = 4},
[ADC_GAIN_6] = {.mul = 1, .div = 6},
[ADC_GAIN_8] = {.mul = 1, .div = 8},
[ADC_GAIN_12] = {.mul = 1, .div = 12},
[ADC_GAIN_16] = {.mul... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_read(struct adc_context *ctx,
const struct adc_sequence *sequence)
{
ctx->sequence = *sequence;
ctx->status = 0;
if (sequence->options) {
ctx->options = *sequence->options;
ctx->sequence.options = &ctx->options;
ctx->sampling_index = 0U;
if (ctx->options.interval_us != 0U) {
atomic... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/**
* @file
*
* @brief Emulated ADC driver
*/
/*
* Copyright 2021 Google LLC
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT zephyr_adc_emul
#include <zephyr/drivers/adc.h>
#include <zephyr/drivers/adc/adc_emul.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#incl... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
static int cmd_adc_emul_raw(const struct shell *sh, size_t argc, char **argv)
{
ARG_UNUSED(argc);
const struct device *dev = get_adc_emul(argv[-1]);
char *endptr;
unsigned long chan_ul;
unsigned long raw_ul;
int ret;
if (!device_is_ready(dev)) {
shell_error(sh, "ADC emulator device not ready"... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>or;
adc_context_lock(&data->ctx, false, NULL);
error = adc_kb106x_start_read(dev, sequence);
adc_context_release(&data->ctx, error);
return error;
}
#if defined(CONFIG_ADC_ASYNC)
static int adc_kb106x_read_async(const struct device *dev, const struct adc_sequence *sequence,
struct k_poll_signa... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 ENE Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ene_kb1200_adc
#include <zephyr/kernel.h>
#include <zephyr/drivers/adc.h>
#include <zephyr/drivers/pinctrl.h>
#include <errno.h>
#include <reg/adc.h>
#include <zephyr/logging/log.h>
#define ... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT espressif_esp32_adc
#include <esp_clk_tree.h>
#include <esp_private/sar_periph_ctrl.h>
#include <esp_private/adc_share_hw_ctrl.h>
#include "adc_esp32.h"
#include <zephyr/drivers/gpio.h>
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ct device *gpio_port;
#if defined(CONFIG_ADC_ESP32_DMA) && SOC_GDMA_SUPPORTED
const struct device *dma_dev;
uint8_t dma_channel;
#endif /* defined(CONFIG_ADC_ESP32_DMA) && SOC_GDMA_SUPPORTED */
};
struct adc_esp32_data {
adc_oneshot_hal_ctx_t hal;
adc_atten_t attenuation[ADC_LL_MAX_CHANNEL_NUM];
uin... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>();
}
static void adc_esp32_fill_seq_buffer(const void *seq_buffer, const void *dma_buffer,
uint32_t number_of_samples)
{
uint16_t *sample = (uint16_t *)seq_buffer;
adc_digi_output_data_t *digi_data = (adc_digi_output_data_t *)dma_buffer;
for (uint32_t k = 0; k < number_of_samples; k++) {
#... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2022 BrainCo Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT gd_gd32_adc
#include <errno.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/gd32.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/adc.h>
#include <zephyr/driver... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>T(n), 0); \
irq_enable(DT_INST_IRQN(n)); \
}; \
DEVICE_DT_INST_DEFINE(n, \
adc_gecko_init, NULL, \
&adc_gecko_data_##n, &adc_gecko_config_##n,\
POST_KERNEL, CONFIG_ADC_INIT_PRIORITY, \
&api_gecko_adc_driver_api);
DT_INST_FOREACH_STATUS_OKAY(GECKO_ADC_INIT)... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/adc.h>
#include <zephyr/internal/syscall_handler.h>
#include <zephyr/kernel.h>
static inline int z_vrfy_adc_channel_setup(const struct device *dev,
const struct adc_channel_cfg *user... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief ADC driver for Infineon CAT1 MCU family.
*/
#define DT_DRV_COMPAT infineon_adc
#include <zephyr/drivers/a... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: <text>Copyright (c) 2026 Infineon Technologies AG,
* or an affiliate of Infineon Technologies AG. All rights reserved.</text>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief ADC driver for Infineon AutAnalog SAR ADC used by Edge MCU family.
*/
#define DT_DRV_C... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>HPPASS_SAR_ADC_INIT(n) \
ADC_IFX_HPPASS_SAR_DRIVER_API(n); \
static void ifx_hppass_sar_adc_config_func_##n(void); \
static const struct ifx_hppa... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>nal = COND_CODE_1(DT_INST_ENUM_HAS_VALUE(n, vref_src, vdda_by_2), \
(DT_INST_PROP(n, vref_mv) / 2), \
(COND_CODE_1(DT_INST_ENUM_HAS_VALUE(n, vref_src, \
internal), \
(IFX_SAR_REF_INTERNAL_MV), \
(DT_INST_PROP(n, vref_mv)))))... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>it51xxx_cfg *config = dev->config;
return sys_read8(config->base + VCH0CTL) & IT51XXX_ADC_DATVAL;
}
/* Get result for each ADC selected channel. */
static void adc_it51xxx_get_sample(const struct device *dev)
{
struct adc_it51xxx_data *data = dev->data;
const struct adc_it51xxx_cfg *config = dev->con... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 ITE Corporation. All Rights Reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ite_it8xxx2_adc
#define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(adc_ite_it8xxx2);
#include <zephyr/drivers/adc.h>
#include <zephy... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>{
uint8_t channels = 0;
size_t needed;
uint32_t mask;
for (mask = BIT(LMP90XXX_MAX_CHANNELS - 1); mask != 0; mask >>= 1) {
if (mask & sequence->channels) {
channels++;
}
}
needed = channels * sizeof(int32_t);
if (sequence->options) {
needed *= (1 + sequence->options->extra_samplings);
}... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* LLTC LTC2451 ADC
*
* Copyright (c) 2023 Brill Power Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/drivers/adc.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/byteorder.h>
LOG_MODULE_REGISTER(ltc2451, CONFIG_ADC... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>RNAL_MV,
};
static int adc_m5pm1_init(const struct device *dev)
{
const struct adc_m5pm1_config *config = dev->config;
struct adc_m5pm1_data *data = dev->data;
if (!device_is_ready(config->mfd)) {
LOG_ERR_DEVICE_NOT_READY(config->mfd);
return -ENODEV;
}
k_mutex_init(&data->lock);
return 0;
}... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2023 SILA Embedded Solutions GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/adc.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/logging/log.h>
#include <zephyr/kernel.h>
#inclu... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Mustafa Abdullah Kus, Sparse Technology
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdbool.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/adc.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/ke... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Gabriele Zampieri <opensource@arsenaling.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/adc.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/spi.h>
#... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023-2024 Analog Devices, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT adi_max32_adc
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/adc.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>;
if (ret != 0) {
LOG_ERR("Invalid oversampling : %d\n", sequence->oversampling);
return ret;
}
/* Set Resolution */
ret = adc_set_resolution(ADC_REGS, sequence->resolution, sequence->oversampling);
if (ret != 0) {
LOG_ERR("Invalid resolution : %d\n", sequence->resolution);
return ret;
}
... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2019 Intel Corporation.
* Copyright (c) 2023 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT microchip_xec_adc
#include <errno.h>
#include <soc.h>
#include <zephyr/drivers/adc.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/dt-bindings/interru... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>annel %d (err %d)",
channel, err);
adc_context_complete(&data->ctx, err);
break;
}
LOG_DBG("read channel %d, result = %d", channel,
result);
*data->buffer++ = result;
WRITE_BIT(data->channels, channel, 0);
}
adc_context_on_sampling_done(&data->ctx, data->dev);
}
}
sta... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>nc ? true : false, async);
err = mcp3221_start_read(dev, sequence);
adc_context_release(&data->ctx, err);
return err;
}
static int mcp3221_read(const struct device *dev, const struct adc_sequence *sequence)
{
return mcp3221_read_async(dev, sequence, NULL);
}
static void adc_context_start_sampling(s... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/**
* Copyright (c) 2024 Syslinbit SCOP SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ADC driver for the MCP3561R/2R/4R ADCs.
*/
#define DT_DRV_COMPAT microchip_mcp356xr
#include <zephyr/drivers/spi.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/adc.h>
#includ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>US_OKAY(ACD_MCUX_12B1MSPS_SAR_INIT)
<|fim_prefix|>/*
* Copyright (c) 2021, STRIM LLC
*
* Based on adc_mcux_adc12.c, which are:
* Copyright (c) 2017-2018, NXP
* Copyright (c) 2019 Vestas Wind Systems A/S
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_mcux_12b1msps_sar
#inclu... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>in && val <= max, str)
#define ASSERT_ADC12_CLK_DIV_VALID(val, str) \
BUILD_ASSERT(val == 1 || val == 2 || val == 4 || val == 8, str)
#define TO_ADC12_CLOCK_SRC(val) _DO_CONCAT(kADC12_ClockSourceAlt, val)
#define TO_ADC12_CLOCK_DIV(val) _DO_CONCAT(kADC12_ClockDivider, val)
#define ADC12_REF_SRC(n) ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>->adc_dma_config.dma_channel =
dma_request_channel(data->dev_dma, (void *)&adc_filter);
} else {
enum dma_channel_filter adc_filter = DMA_CHANNEL_NORMAL;
data->adc_dma_config.dma_channel =
dma_request_channel(data->dev_dma, (void *)&adc_filter);
}
if (data->adc_dma_config.dma_channel == -EIN... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> in this driver; zephyr seems to use 16 bit */
adc_config.resultWidth = kADC_ResultWidth16;
adc_config.enableDMA = false;
adc_config.enableADC = true;
ADC_Init(base, &adc_config);
if (ADC_DoAutoCalibration(base, config->cal_volt)) {
LOG_WRN("Calibration of ADC failed!");
}
ADC_ClearStatusFlags... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2023-2024, 2026 NXP
* Copyright (c) 2020 Toby Firth
*
* Based on adc_mcux_adc16.c and adc_mcux_adc12.c, which are:
* Copyright (c) 2017-2018, NXP
* Copyright (c) 2019 Vestas Wind Systems A/S
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_lpc_lpadc
#include <... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 Texas Instruments
* copyright (c) 2026 Linumiz
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ti_mspm0_adc12
#include <errno.h>
#define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(adc_mspm0);
#include <zephyr/device.h... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2020 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nuvoton_npcx_adc
#include <assert.h>
#include <zephyr/drivers/adc.h>
#include <zephyr/drivers/adc/adc_npcx_threshold.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/pinctr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>alid in the future, we use
* a BUILD_ASSERT().
*/
#define ADC_INIT(inst) \
BUILD_ASSERT((inst) == 0, \
"multiple instances not supported"); \
DEVICE_DT_INST_DEFINE(0, \
init_adc, NULL, NULL, NULL, \
POST_KERNEL, \
CONFIG_ADC_INIT_PRIORITY, \
&ad... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>, NULL,
NULL, POST_KERNEL, CONFIG_ADC_INIT_PRIORITY,
&adc_nrfx_driver_api);
<|fim_prefix|>/*
* Copyright (c) 2018 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "adc_context.h"
#include <nrfx_saadc.h>
#include <zephyr/dt-bindings/adc/nrf-saadc.h>
#include... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
LOG_DBG("Configure resolution=%d", sequence->resolution);
/* Enable the A/D converter */
if (data->is_differential) {
EADC_Open(eadc, EADC_CTL_DIFFEN_DIFFERENTIAL);
} else {
EADC_Open(eadc, EADC_CTL_DIFFEN_SINGLE_END);
}
data->buffer = sequence->buffer;
data->buf_end = data->buffer + sequenc... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>*sequence)
{
return adc_nxp_s32_read_async(dev, sequence, NULL);
}
static void adc_nxp_s32_isr(const struct device *dev)
{
const struct adc_nxp_s32_config *config = dev->config;
Adc_Sar_Ip_IRQHandler(config->instance);
}
#define ADC_NXP_S32_DRIVER_API(n) \
static DEVICE_API(adc, adc_nxp_s32_dr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>CH_MASK;
}
#else
ARG_UNUSED(enable_ech_irq);
#endif
base->MCR |= ADC_MCR_NSTART_MASK;
}
static inline uint16_t nxp_sar_adc_read_cdata(const struct nxp_sar_adc_config *config,
ADC_Type *base, uint8_t hw_ch)
{
uint32_t reg_index = NXP_SAR_ADC_REGINDEX(hw_ch);
uint32_t bit_index = NXP_SAR_ADC_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Realtek, SIBG-SD7
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT realtek_rts5912_adc
#include <zephyr/drivers/adc.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/clock_control_rts5912.h>
#include <zephyr/drivers/pinctrl.h>... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024-2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/adc.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/reset.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT renesas_rx_adc
#include <zephyr/drivers/adc.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/reset.h>
#include <zephyr/irq... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>onst struct device *dev, const struct adc_sequence *sequence,
struct k_poll_signal *async)
{
struct adc_rz_data *data = dev->data;
int err;
adc_context_lock(&data->ctx, async ? true : false, async);
err = adc_rz_start_read(dev, sequence);
adc_context_release(&data->ctx, err);
return err;
}... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT renesas_rza2m_adc
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/interrupt_controller/gic.h>
#include <zephyr/logging/log.h>
#... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2021 Google LLC
* Copyright 2022 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_C<|fim_suffix|> \
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022, Basalte bv
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT atmel_sam_adc
#include <soc.h>
#include <zephyr/drivers/adc.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control/atmel_sam_pmc.h>
#define ADC_CONTEXT_USES_KERNEL_TIMER
#incl... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ged) {
data->reference_changed = 0;
LOG_DBG("Discarded initial conversion due to reference change");
adc_sam0_start_conversion(dev);
return;
}
#endif
*data->buffer++ = result;
adc_context_on_sampling_done(&data->ctx, dev);
}
static int adc_sam0_init(const struct device *dev)
{
const struct ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> &adc##n##_sam_cfg, POST_KERNEL, \
CONFIG_ADC_INIT_PRIORITY, \
&adc_sam_api); \
\
static void adc##n##_sam_cfg_func(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
adc_sam_isr, \
DEVICE_DT_INST_GET(n), 0); ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025, Qingsong Gou <gouqs@hotmail.com>
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT sifli_sf32lb_gpadc
#include <zephyr/kernel.h>
#include <zephyr/drivers/adc.h>
#include <zephyr/drivers/clock_control/sf32lb.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>);
SHELL_STATIC_SUBCMD_SET_CREATE(sub_adc_cmds,
/* Alphabetically sorted. */
SHELL_CMD_ARG(acq_time, NULL, CMD_HELP_ACQ_TIME, cmd_adc_acq, 3, 0),
SHELL_CMD_ARG(channel, &sub_channel_cmds, CMD_HELP_CHANNEL, NULL, 3, 0),
SHELL_CMD(gain, &sub_gain_cmds, CMD_HELP_GAIN, NULL),
SHELL_CMD_ARG(print, NULL, ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
ADC_CONTEXT_INIT_TIMER(iadc_data_##n, ctx), \
ADC_CONTEXT_INIT_LOCK(iadc_data_##n, ctx), \
ADC_CONTEXT_INIT_SYNC(iadc_data_##n, ctx), \
IADC_DMA_CHANNEL(n) ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Silicon Laboratories Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT silabs_siwx91x_adc
#define ADC_CONTEXT_USES_KERNEL_TIMER
#include <zephyr/drivers/adc.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/cloc... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>size = active_channels * sizeof(uint16_t);
if (sequence->options) {
needed_buffer_size *= (1 + sequence->options->extra_samplings);
}
if (sequence->buffer_size < needed_buffer_size) {
LOG_ERR("Provided buffer is too small (%u/%u)",
sequence->buffer_size, needed_buffer_size);
return -ENOMEM;
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>t), \
&sdadc_smartbond_data_##inst, \
&sdadc_smartbond_cfg_##inst, \
POST_KERNEL, \
CONFIG_ADC_INIT_PRIORITY, \
&sdadc_smartbond_driver_api);
DT_INST_FOREACH_STATUS_OKAY(SDADC_INIT)
<|fim_prefix|>/*
* Copyright (c) 2023 Renesas Electronics Corpor... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 Kokoon Technology Limited
* Copyright (c) 2019 Song Qiang <songqiang1304521@gmail.com>
* Copyright (c) 2019 Endre Karlson
* Copyright (c) 2020 Teslabs Engineering S.L.
* Copyright (c) 2021 Marius Scholtz, RIC Electronics
* Copyright (c) 2023 Hein Wessels, Nobleo Technology
*... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>int err;
/* Turn on ADC digital clock (always on) */
err = clock_control_on(clk,
(clock_control_subsys_t)&config->dig_clk);
if (err < 0) {
LOG_ERR("failed to turn on ADC digital clock (%d)", err);
return err;
}
/* Configure DT-provided signals when available */
err = pinctrl_apply_state(conf... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>NE(n, NULL, NULL, NULL, NULL, \
POST_KERNEL, \
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&vnd_adc_api);
DT_INST_FOREACH_STATUS_OKAY(VND_ADC_INIT)
<|fim_prefix|>/*
* Copyright (c) 2021, Commonwealth Scientific and Industrial Research
* Organisation (CSIRO) ABN 41 687 119 230... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>fer size is too small (%zu/%zu)", sequence->buffer_size, required_size);
return -ENOMEM;
}
data->buffer = sequence->buffer;
data->repeat_buffer = sequence->buffer;
adc_context_start_read(&data->ctx, sequence);
return adc_context_wait_for_completion(&data->ctx);
}
static int ti_adc_read_async(co... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Caspar Friedrich <c.s.w.friedrich@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/adc.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zeph... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Antonio Tessarolo
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_vf610_adc
#include <errno.h>
#include <zephyr/drivers/adc.h>
#include <adc_imx6sx.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(vf610_adc, CONFIG_ADC_LOG_LEVEL);
#define ADC_CONTEXT... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ed */
adc_global_ptr->GLOBRCR = 0;
/* global bound register is unused */
adc_global_ptr->GLOBBOUND = 0;
adc_global_init = true;
}
adc_group->ARBCFG = 0;
adc_group->BOUND = 0;
XMC_VADC_GROUP_SetPowerMode(adc_group, XMC_VADC_GROUP_POWERMODE_NORMAL);
/* Initiate calibration. It is initialize... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Google LLC.
* Copyright (c) 2024 Croxel Inc.
* Copyright (c) 2025 Analog Devices, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/adc.h>
#include <zephyr/logging/log.h>
#include <zephyr/rtio/work.h>
LOG_MODULE_REGISTER(adc_compat, CONFIG_ADC_LOG_LEV... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>d", reg, ret);
}
end:
k_mutex_unlock(&data->lock);
return ret;
}
static int aw88298_get_sample_rate_code(uint32_t sample_rate, uint16_t *code)
{
switch (sample_rate) {
case AUDIO_PCM_RATE_8K:
*code = 0x0U;
break;
case AUDIO_PCM_RATE_11P025K:
*code = 0x1U;
break;
case AUDIO_PCM_RATE_16K:
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>#inst; \
DEVICE_DT_INST_DEFINE(inst, dummy_codec_init, NULL, \
&dummy_codec_data_##inst, NULL, \
POST_KERNEL, \
CONFIG_AUDIO_CODEC_INIT_PRIORITY, \
&dummy_codec_api)
/* clang-format on */
DT_INST_FOREACH_STATUS_OKAY(DUMMY_CODEC_DEFINE)
<|fim_prefix|>/*
* Copyright 20... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2023 Centralp
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/audio/codec.h>
#include <zephyr/device.h>
#include <zephyr/shell/shell.h>
#include <stdlib.h>
#define CODEC_START_HELP \
SHELL_HELP("Start output ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> wordlen = WORDLEN_24;
break;
case 32:
wordlen = WORDLEN_32;
break;
default:
return -ENOTSUP;
}
}
if (cs43l22_soft_power_down(&cfg->i2c)) {
return -EIO;
}
/* Set automatic clock detection */
if (cs43l22_write(&cfg->i2c, REG_CLOCKING_CTL, (1 << 7))) {
return -EIO;
}
/* Set i... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/audio/codec.h>
#include <zephyr/devicetree/clocks.h>
#include <zephyr/sys/util.h>
#include <zephy... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>212_ALC_NOISE 0x9C */
#define DIALOG7212_ALC_NOISE_MASK (0x3F)
#define DIALOG7212_ALC_NOISE_SHIFT (0U)
#define DIALOG7212_ALC_NOISE_VAL(x) ((x) << DIALOG7212_ALC_NOISE_SHIFT)
/* DIALOG7212_ALC_TARGET_MIN 0x9D */
#define DIALOG7212_ALC_TARGET_MIN_THRESHOLD_M... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Ambiq Micro Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/kernel.h>
#include <soc.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
#include <zephyr/audio/dmic.h>
#include <zephyr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>;
}
<|fim_prefix|>/*
* SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors
* SPDX-License-Identifier: Apache-2.0
*/
#include <stddef.h>
#include <stdint.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/util.h>
#include <zephyr/audio/dmic.h>
#include "dmic_capture.h"
/* Bounded drain... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> dmic_capture *cap, const struct device *dev,
const struct dmic_capture_cfg *cfg);
/**
* @brief Read one captured block.
*
* @param cap Running capture.
* @param[out] buf Receives a pointer to the captured block.
* @param[out] size Receives the block size in bytes.
* @param timeo... | fim | zephyrproject-rtos/zephyr | c |
/*
* SPDX-FileCopyrightText: <text>Copyright (c) 2026 Infineon Technologies AG,
* or an affiliate of Infineon Technologies AG. All rights reserved.</text>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT infineon_pdm
#include <zephyr/audio/dmic.h>
#include <zephyr/drivers/pinctrl.h>
#include <zep... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2023 NXP
* Copyright (c) 2021 Nordic Semiconductor ASA
*
* based on dmic_nrfx_pdm.c
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/dma.h>
#include <zephyr/audio/dmic.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/timer/system_timer.h>
#include <zephyr/drivers... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>TYY_MAX_PDM_FREQ ||
cfg->io.max_pdm_clk_freq < cfg->io.min_pdm_clk_freq) {
return -EINVAL;
}
factor = sw_filter_lib_init(dev, cfg);
if (factor == 0U) {
return -EINVAL;
}
/* configure I2S channels */
struct i2s_config i2s_cfg;
i2s_cfg.word_size = chan_size;
i2s_cfg.channels = cfg->chann... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>chan;
pdm_filter[i].In_MicChannels = cfg->channel.req_num_chan;
pdm_filter[i].Decimation = factor;
pdm_filter[i].MaxVolume = 64;
Open_PDM_Filter_Init(&data->pdm_filter[i]);
}
return factor;
}
int sw_filter_lib_run(TPDMFilter_InitStruct *pdm_filter,
void *pdm_block, void *pcm_block,
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_AUDIO_DMIC_MPXXDTYY_H_
#define ZEPHYR_DRIVERS_AUDIO_DMIC_MPXXDTYY_H_
#include <zephyr/audio/dmic.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include "OpenPDMFilter.h"
#ifdef __... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2026 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT zephyr_native_sim_dmic
#include <nsi_errno.h>
#include <stdint.h>
#include <string.h>
#include <sys/types.h>
#include <nsi_host_trampolines.h>
#include <nsi_hw_scheduler.h>
#include "cmdline.h"
#include "dmic_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2026 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <errno.h>
#include <fcntl.h>
#include <string.h>
#include <unistd.h>
#include <nsi_errno.h>
#include <nsi_tracing.h>
int ns_dmic_open_file_bottom(const char *pathname)
{
int fd = open(pathname, O_RDONLY);
if (fd < 0) {
... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2026 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_AUDIO_DMIC_NATIVE_SIM_BOTTOM_H_
#define ZEPHYR_DRIVERS_AUDIO_DMIC_NATIVE_SIM_BOTTOM_H_
#ifdef __cplusplus
extern "C" {
#endif
int ns_dmic_open_file_bottom(const char *pathname);
#ifdef __cplusplus
}
#endif
#endif /* ZEPHY... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nordic_nrf_pdm
#include <zephyr/audio/dmic.h>
#include <zephyr/drivers/clock_control/nrf_clock_control.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/dt-bindings/clock/nrf-auxpl... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>clock_rate = cfg->sample_rate * real_osr * 8U;
if (clk_rate < micfil_clock_rate) {
LOG_ERR("Clock rate %u too low for sample rate %u (OSR=%u)",
clk_rate, cfg->sample_rate, real_osr);
return -EINVAL;
}
uint32_t reg_div = clk_rate / micfil_clock_rate;
if (reg_div == 0U) {
reg_div = ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <zephyr/kernel.h>
#include <zephyr/shell/shell.h>
#include <zephyr/shell/shell_string_conv.h>
#include <zephyr/audio/dmic... | fim | zephyrproject-rtos/zephyr | c |
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