text stringlengths 14 100k | source stringclasses 1
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/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/drivers/cache.h>
#include <zephyr/logging/log.h>
#include <fsl_cache_lpcac.h>
void cache_instr_enable(void)
{
L1CACHE_EnableCodeCache();
}
void cache_instr_disable(void)
{
L1CACHE_DisableCodeCache();
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/drivers/cache.h>
#include <zephyr/logging/log.h>
#include <soc.h>
#include <fsl_cache.h>
LOG_MODULE_REGISTER(cache_nxp_xcache, CONFIG_CACHE_LOG_LEVEL);
#if !defined(NXP_XCACHE_INSTR)
#defi... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2025 Henrik Lindblom <henrik.lindblom@vaisala.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/spinlock.h>
#include <zephyr/drivers/cache.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/math_extras.h>
#include <stm32_ll_dcache.h>
#include <stm32_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>);
if (ret < 0) {
return ret;
}
if (ret > CONFIG_CAN_SAMPLE_POINT_MARGIN) {
return -ERANGE;
}
return can_set_timing_data(dev, &timing_data);
}
#endif /* CONFIG_CAN_FD_MODE */
<|fim_prefix|>/*
* Copyright (c) 2019 Alexander Wachter
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>EACH_STATUS_OKAY(CAN_ESP32_TWAI_INIT)
<|fim_prefix|>/*
* Copyright (c) 2022 Henrik Brix Andersen <henrik@brixandersen.dk>
* Copyright (c) 2022 Martin Jäger <martin@libre.solar>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT espressif_esp32_twai
#include "can_sja1000.h"
#include <... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Vestas Wind Systems A/S
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/drivers/can.h>
#include <zephyr/drivers/can/can_fake.h>
#include <zephyr/fff.h>
#include <zephyr/sys/util.h>
#ifdef CONFIG_ZTEST
#include <zephyr/ztest.h>
#endif /* ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
return z_impl_can_stats_get_rx_overruns(dev);
}
#include <zephyr/syscalls/can_stats_get_rx_overruns_mrsh.c>
#endif /* CONFIG_CAN_STATS */
<|fim_prefix|>/*
* Copyright (c) 2018 Alexander Wachter
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/internal/syscall_handler.h>
#include <zephy... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 Linumiz
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/can.h>
#include "can_mcan.h"
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
#include <zephyr/sys/util.h>
#include <infineon_kcon... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2022 Henrik Brix Andersen <henrik@brixandersen.dk>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT kvaser_pcican
#include "can_sja1000.h"
#include <zephyr/drivers/can.h>
#include <zephyr/drivers/pcie/pcie.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/util.h>
LOG_MOD... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Vestas Wind Systems A/S
* Copyright (c) 2018 Alexander Wachter
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT zephyr_can_loopback
#include <stdbool.h>
#include <string.h>
#include <zephyr/drivers/can.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/l... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>data;
struct can_bus_err_cnt err_cnt;
enum can_state new_state;
can_state_change_callback_t state_change_cb;
state_change_cb = dev_data->common.state_change_cb;
can_get_state(dev, &new_state, &err_cnt);
if (old_state != new_state) {
if (state_change_cb) {
state_change_cb(dev, new_state, err_c... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ot supported in non-FD mode");
return -ENOTSUP;
}
#else /* CONFIG_CAN_FD_MODE */
if ((frame->flags & ~(CAN_FRAME_IDE | CAN_FRAME_RTR)) != 0U) {
LOG_ERR("unsupported CAN frame flags 0x%02x", frame->flags);
return -ENOTSUP;
}
#endif /* !CONFIG_CAN_FD_MODE */
if (data_length > sizeof(frame->data)... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>N_DT_MRAM_OFFSET(node_id) == 0, "offset must be 0"); \
static char __nocache_noinit __aligned(4) _name[CAN_MCAN_DT_MRAM_ELEMENTS_SIZE(node_id)];
/**
* @brief Assert that the Message RAM configuration meets the Bosch M_CAN IP core restrictions
*
* @param node_id node identifier
*/
#... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 Karsten Koenig
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT microchip_mcp2515
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/can/transceiver.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/drivers/gpio.h>
#include <zephy... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ers */
#define MCP2515_ADDR_CANSTAT 0x0E
#define MCP2515_ADDR_CANCTRL 0x0F
#define MCP2515_ADDR_TEC 0x1C
#define MCP2515_ADDR_REC 0x1D
#define MCP2515_ADDR_CNF3 0x28
#define MCP2515_ADDR_CNF2 0x29
#define MCP2515_ADDR_CNF1 0x2A
#define MCP2515_ADDR_CANINTE 0x2B
#define MCP2515_ADD... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2020 Abram Early
* Copyright (c) 2023 Andriy Gelman
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT microchip_mcp251xfd
#include "can_mcp251xfd.h"
#include <zephyr/device.h>
#include <zephyr/drivers/can/transceiver.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
#define MCP251XFD_MAX_READ_CRC_BUF_SIZE \
(MCP251XFD_SPI_CRC_LEN + 2 * MCP251XFD_REG_SIZE)
#define MCP251XFD_SPI_BUF_SIZE \
MAX(MCP251XFD_MAX_READ_FIFO_BUF_SIZE, MCP251XFD_MA... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ING;
} else {
*state = CAN_STATE_ERROR_ACTIVE;
}
}
}
if (err_cnt != NULL) {
FLEXCAN_GetBusErrCount(base, &err_cnt->tx_err_cnt,
&err_cnt->rx_err_cnt);
}
return 0;
}
static int mcux_flexcan_send(const struct device *dev,
const struct can_frame *frame,
k_timeou... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 Texas Instruments
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/irq.h>
#include <zephyr/drivers/can.h>
#include "can_mcan.h"
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_c... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>DY;
}
data->common.started = true;
return 0;
}
static int can_native_linux_stop(const struct device *dev)
{
struct can_native_linux_data *data = dev->data;
if (!data->common.started) {
return -EALREADY;
}
data->common.started = false;
return 0;
}
static int can_native_linux_set_mode(const... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Intel Corporation
* Copyright (c) 2022 Martin Jäger <martin@libre.solar>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
*
* Routines setting up the host system. Those are placed in separate file
* because there is naming conflicts between host and zephyr network s... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* C<|fim_suffix|>r.
*/
#ifndef ZEPHYR_DRIVERS_CAN_NATIVE_LINUX_ADAPT_H_
#define ZEPHYR_DRIVERS_CAN_NATIVE_LINUX_ADAPT_H_
int linux_socketcan_iface_open(const char *if_name);
int linux_socketcan_iface_close(int fd);
int linux_socketcan_poll_data(int fd);
int linux_socketcan_read_data(int fd, void... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>tom;
return can_mcan_sys_write_reg(config->mcan, reg, val);
}
static int can_nrf_read_mram(const struct device *dev, uint16_t offset, void *dst, size_t len)
{
const struct can_mcan_config *mcan_config = dev->config;
const struct can_nrf_config *config = mcan_config->custom;
return can_mcan_sys_read... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
return -ENODEV;
}
if (!device_is_ready(config->clk_dev)) {
LOG_ERR_DEVICE_NOT_READY(config->clk_dev);
return -ENODEV;
}
SYS_UnlockReg();
rc = can_numaker_init_unlocked(dev);
SYS_LockReg();
return rc;
}
static DEVICE_API(can, can_numaker_driver_api) = {
.get_capabilities = can_mcan_get_c... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>bug
* regarding the maximum value for data phase segment 2. Valid register
* values are 0 to 31.
*/
.timing_data_min = CAN_MCAN_TIMING_DATA_MIN_INITIALIZER,
.timing_data_max = CAN_MCAN_TIMING_DATA_MAX_INITIALIZER,
#endif /* CONFIG_CAN_FD_MODE */
};
static const struct can_mcan_ops nxp_lpc_mcan_op... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2022-2024,2026 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/sys/atomic.h>
#include <zephyr/drivers/can.h>
#include <zephyr/drivers/can/transceiver.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/device.h>
#include <zephyr/drivers/pinctrl.h>... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> to enter operation mode (err %d)", ret);
if (config->common.phy != NULL) {
/* Attempt to disable the CAN transceiver in case of error */
(void)can_transceiver_disable(config->common.phy);
}
} else {
data->common.started = true;
}
k_mutex_unlock(&data->inst_mutex);
return ret;
}
static... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Renesas Electronics Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#include <soc.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/clock_control/renesas_ra_cgc.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/can.h>
#include <zephyr/drivers/can/tr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>R_Msk)) /* Bit 0 Error */
!= 0) {
can_renesas_rz_call_tx_cb(dev, -EIO);
}
}
default:
break;
}
}
static inline int can_renesas_rz_apply_default_config(const struct device *dev)
{
struct can_renesas_rz_cfg *cfg = (struct can_renesas_rz_cfg *)dev->config;
int ret;
struct can_timing timin... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2022 Vestas Wind Systems A/S
* Copyright (c) 2021 Alexander Wachter
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/can.h>
#include "can_mcan.h"
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control/atmel_sam_pmc.h>
#include <soc.h>
#include <zephyr/kern... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>r);
#endif
return 0;
}
static void can_sam0_clock_enable(const struct can_sam0_config *cfg)
{
uint8_t gen_index = cfg->gclk_gen;
*cfg->mclk |= cfg->mclk_mask;
GCLK->PCHCTRL[cfg->gclk_id].reg = GCLK_PCHCTRL_CHEN
| GCLK_PCHCTRL_GEN(gen_index);
/* Enable the GLCK<gen_index> with DIV*/
#if defi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Vestas Wind Systems A/S
* Copyright (c) 2019 Alexander Wachter
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdlib.h>
#include <stdio.h>
#include <zephyr/device.h>
#include <zephyr/drivers/can.h>
#include <zephyr/logging/log.h>
#include <zephyr/shell/shell.h>
LOG_MO... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Henrik Brix Andersen <henrik@brixandersen.dk>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "can_sja1000.h"
#include "can_sja1000_priv.h"
#include <zephyr/drivers/can.h>
#include <zephyr/drivers/can/transceiver.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(can... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
*
* @param dev Pointer to the device structure for the driver instance.
*/
int can_sja1000_init(const struct device *dev);
#endif /* ZEPHYR_DRIVERS_CAN_CAN_SJA1000_H_ */
<|fim_prefix|>/*
* Copyright (c) 2022 Henrik Brix Andersen <henrik@brixandersen.dk>
*
* SPDX-License-Identifier: Apache-2.0
*/
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>CAN_SJA1000_ECC_SEG_ACK_DELIM FIELD_PREP(CAN_SJA1000_ECC_SEG_MASK, 27U)
#define CAN_SJA1000_ECC_SEG_EOF FIELD_PREP(CAN_SJA1000_ECC_SEG_MASK, 26U)
#define CAN_SJA1000_ECC_SEG_INTERMISSION FIELD_PREP(CAN_SJA1000_ECC_SEG_MASK, 18U)
#define CAN_SJA1000_ECC_SEG_ACTIVE_ERROR_FLAG FIELD_PREP(CAN_SJA1000_ECC_S... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 Alexander Wachter
* Copyright (c) 2022 Martin Jäger <martin@libre.solar>
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Include soc.h prior to Zephyr CAN headers to pull in HAL fixups */
#include <soc.h>
#include <zephyr/drivers/can.h>
#include <zephyr/drivers/can/transceiver.... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>,
.timing_data_min = CAN_MCAN_TIMING_DATA_MIN_INITIALIZER,
.timing_data_max = CAN_MCAN_TIMING_DATA_MAX_INITIALIZER,
#endif /* CONFIG_CAN_FD_MODE */
};
static const struct can_mcan_ops can_stm32fd_ops = {
.read_reg = can_stm32fd_read_reg,
.write_reg = can_stm32fd_write_reg,
.read_mram = can_stm32fd_r... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ne_0_isr, DEVICE_DT_INST_GET(n), 0); \
irq_enable(DT_INST_IRQ_BY_NAME(n, int0, irq)); \
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(n, int1, irq), \
DT_INST_IRQ_BY_NAME(n, int1, priority), \
can_mcan_line_1_isr, DEVICE_DT_INST_GET(n), 0); \
irq_enable(DT_INST_IRQ_BY_NAME(n, int1, ir... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Vestas Wind Systems A/S
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/drivers/can.h>
#include "can_mcan.h"
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/byteorder.h... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Andriy Gelman
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT infineon_xmc4xxx_can_node
#include <zephyr/device.h>
#include <zephyr/drivers/can.h>
#include <zephyr/drivers/can/transceiver.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/kernel.h>
#incl... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Vestas Wind Systems A/S
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT can_transceiver_gpio
#include <zephyr/device.h>
#include <zephyr/drivers/can/transceiver.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(can_trans... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2023 Cirrus Logic, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_CHARGER_BQ24190_H_
#define ZEPHYR_DRIVERS_CHARGER_BQ24190_H_
/* Input Source Control */
#define BQ24190_REG_ISC 0x00
#define BQ24190_REG_ISC_EN_HIZ_MASK BIT(7)
#define BQ24190_REG_I... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> = charger_adp5360_init_bat_prot_oc_dischg(dev);
if (ret) {
return ret;
}
ret = charger_adp5360_init_bat_prot_ov(dev);
if (ret) {
return ret;
}
ret = charger_adp5360_init_bat_prot_oc_chg(dev);
if (ret) {
return ret;
}
return 0;
}
static DEVICE_API(charger, adp5360_charger_driver_api) = ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2025 BayLibre SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT x_powers_axp2101_charger
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/drivers/charger.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/util.h>
#inclu... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>0_set_constant_charge_current(dev, val->const_charge_current_ua);
case CHARGER_PROP_CONSTANT_CHARGE_VOLTAGE_UV:
return bq24190_set_constant_charge_voltage(dev, val->const_charge_voltage_uv);
default:
return -ENOTSUP;
}
}
static int bq24190_charge_enable(const struct device *dev, const bool enable)... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ctrl = \
(DT_INST_PROP(inst, re_charge_threshold_millivolt) == 100 \
? BQ2518X_IC_CTRL_VRCH_100 \
: BQ2518X_IC_CTRL_VRCH_200) | \
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
\
DEVICE_DT_INST_DEFINE(inst, bq25713_init, NULL, NULL, &bq25713_config_##inst, POST_KERNEL, \
CONFIG_CHARGER_INIT_PRIORITY, &bq7513_driver_api);
DT_INS... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>r_gpio
struct charger_gpio_config {
struct gpio_dt_spec ctrl_gpio;
};
static int charger_gpio_get_prop(const struct device *dev, charger_prop_t prop,
union charger_propval *val)
{
ARG_UNUSED(dev);
ARG_UNUSED(prop);
ARG_UNUSED(val);
return -ENOTSUP;
}
static int charger_gpio_set_prop(const st... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_charger_charge_enable(dev, enable);
}
#include <zephyr/syscalls/charger_charge_enable_mrsh.c>
<|fim_prefix|>/*
* Copyright 2023 Cirrus Logic, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/internal/syscall_handler.h>
#include <zephyr/drivers/charger.h>
static inline int z_vrfy_ch... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>0335_config *const config = dev->config;
data->charger_enabled = enable;
return i2c_reg_update_byte_dt(&config->bus,
MAX20335_REG_CHGCNTLA,
MAX20335_CHGCNTLA_CHRGEN_MASK,
enable ? MAX20335_CHGCNTLA_CHRGEN : 0);
}
static int max20335_get_interrupt_source(const struct devi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ulation_voltage_uv);
}
val->input_voltage_regulation_voltage_uv = 0;
return 0;
default:
LOG_ERR("Unsupported property %u", prop);
return -ENOTSUP;
}
return 0;
}
static int npm10xx_charger_set_prop(const struct device *dev, const charger_prop_t prop,
const union charger_propval *val... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>->status = data->status;
}
return ret;
case CHARGER_PROP_CONSTANT_CHARGE_CURRENT_UA:
val->const_charge_current_ua = data->i_fast_chg_ua;
return 0;
case CHARGER_PROP_CONSTANT_CHARGE_VOLTAGE_UV:
val->const_charge_voltage_uv = data->vbat_reg_uv;
return 0;
case CHARGER_PROP_PRECHARGE_CURRENT_UA... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2024 Arduino SA
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_pf1550_charger
#include <zephyr/device.h>
#include <zephyr/drivers/charger.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/util.h>
#... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> SY6974B_REG09_WATCHDOG_FAULT) {
*health = CHARGER_HEALTH_WATCHDOG_TIMER_EXPIRE;
return 0;
}
*health = CHARGER_HEALTH_GOOD;
return 0;
}
static int sy6974b_get_prop(const struct device *dev, charger_prop_t prop,
union charger_propval *val)
{
switch (prop) {
case CHARGER_PROP_ONLINE:
ret... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2023 Cirrus Logic, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* Emulator for SBS 1.1 compliant smart battery charger.
*/
#define DT_DRV_COMPAT sbs_sbs_charger
#include <zephyr/device.h>
#include <zephyr/drivers/emul.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/i2c_emul.h>
#incl... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2023 Cirrus Logic, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT sbs_sbs_charger
#include <zephyr/drivers/charger.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/byteorder.h>
#include "sbs_charger.h"
struct sbs_charger_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>efine SBS_CHARGER_STATUS_BATTERY_PRESENT BIT(14)
#define SBS_CHARGER_STATUS_AC_PRESENT BIT(15)
#define SBS_CHARGER_POLL_TIME 500
<|fim_prefix|>/*
* Copyright 2023 Cirrus Logic, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define SBS_CHARGER_REG_SPEC_INFO 0x11
#define SBS_CHARGER_REG_C... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> (struct arm_clock_control_t *)(sub_system);
uint8_t bit = 0U;
switch (beetle_cc->bus) {
case CMSDK_AHB:
bit = (beetle_cc->device - _BEETLE_AHB_BASE) >> 12;
beetle_ahb_set_clock_off(bit, beetle_cc->state);
break;
case CMSDK_APB:
bit = (beetle_cc->device - _BEETLE_APB_BASE) >> 12;
beetle_ap... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright (C) 2021-2022, Intel Corporation
*
*/
#include <zephyr/drivers/clock_control.h>
#include <zephyr/dt-bindings/clock/intel_socfpga_clock.h>
#include "clock_agilex_ll.h"
static int clk_get_rate(const struct device *dev,
clock_control_subsys_t ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019-2021, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/arch/cpu.h>
#include <zephyr/arch/common/sys_bitops.h>
#include <socfpga_system_manager.h>
#include "clock_agilex_ll.h"
/*
* Intel SoC re-use Arm Trusted Firmware (ATF)... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_CLOCK_CONTROL_CLOCK_AGILEX_LL_H
#define ZEPHYR_DRIVERS_CLOCK_CONTROL_CLOCK_AGILEX_LL_H
#include <socfpga_handoff.h>
/* Clock Manager Registers */
#define CLKMGR_OF... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>OC level driver.
*/
return 0;
}
static DEVICE_API(clock_control, cavs_clock_api) = {
.set_rate = cavs_clock_ctrl_set_rate
};
DEVICE_DT_DEFINE(DT_NODELABEL(clkctl), cavs_clock_ctrl_init, NULL,
NULL, NULL, POST_KERNEL,
CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &cavs_clock_api);
<|fim_prefix|>/*
* Cop... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright (C) 2022-2023, Intel Corporation
*
*/
#include <zephyr/drivers/clock_control.h>
#include <zephyr/dt-bindings/clock/intel_socfpga_clock.h>
#include <zephyr/logging/log.h>
#include "clock_control_agilex5_ll.h"
#define DT_DRV_COMPAT intel_agilex5... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022-2024, Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/arch/cpu.h>
#include <socfpga_system_manager.h>
#include <zephyr/sys/__assert.h>
#include "clock_control_agilex5_ll.h"
LOG_MODULE_R... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>CTRL_PERPLL(_reg) (CLKCTRL_PERPLL_BASE_ADDR + CLKCTRL_PERPLL_##_reg)
/* Clock manager/control controller group register offsets */
#define CLKCTRL_CTLGRP_OFFSET 0xD0
#define CLKCTRL_CTLGRP_JTAG 0x00
#define CLKCTRL_CTLGRP_EMACACTR 0x04
#define CLKCTRL_CTLGRP_EMACBCTR 0x08
#define CLKCTRL_CTLGRP... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ether the clock is currently enabled or disabled.
* Always-on clocks always return ON status.
*
* @param dev Clock control device (unused)
* @param sub_system Encoded clock ID from device tree
* @return CLOCK_CONTROL_STATUS_ON if enabled, CLOCK_CONTROL_STATUS_OFF if disabled
*/
static enum clock_con... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> &ambiq_clock_driver_api);
DT_INST_FOREACH_STATUS_OKAY(AMBIQ_CLOCK_INIT)
<|fim_prefix|>/*
* Copyright 2023 Ambiq Micro Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ambiq_clkctrl
#include <errno.h>
#include <zephyr/init.h>
#include <zephyr/drivers/clock_control.h>
#includ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>dle->fen, phandle->cke, DISABLE);
return 0;
}
/**
* @brief Get clock status.
*
* @param dev Device.
* @param sub_system clock idx.
*
* @return Status, if the clock is enabled, return on(2), else off(1).
*/
static enum clock_control_status ameba_clock_get_status(const struct device *dev,
c... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2024-2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/firmware/scmi/clk.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(arm_scmi_clock);
#define DT_DRV_COMPAT arm_scmi_clock
struct scmi_clock_data {
uint32... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 ASPEED Technology Inc.
*
* SPDX-License-Identifier:<|fim_suffix|> \
static const struct clock_aspeed_config clock_aspeed_cfg_##n = { \
.syscon = DEVICE_DT_GET(DT_NODELABEL(syscon)), ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>apb_table[id].apbperiph & (0xff));
uint32_t clk_func = bee_apb_table[id].apbperiph_clk;
if (bee_apb_table[id].apbperiph == APBPeriph_CODEC) {
if (sys_test_bit(PERIBLKCTRL_AUDIO_REG_BASE + apb_reg_off, clk_func) != 0) {
return CLOCK_CONTROL_STATUS_ON;
}
} else {
if (sys_test_bit(config->reg + ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>date_clocks(dev);
if (ret < 0) {
data->crystal_enabled = true;
}
}
} else if ((enum bl60x_clkid)sys == bl60x_clkid_clk_pll) {
if (!data->pll.enabled) {
ret = 0;
} else {
data->pll.enabled = false;
ret = clock_control_bl60x_update_clocks(dev);
if (ret < 0) {
data->pll.enabl... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025-2026 MASSDRIVER EI (massdriver.space)
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT bflb_bl61x_clock_controller
#include <zephyr/kernel.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/otp.h>
#include <zephyr/sys/util.h>
#include <zephy... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025-2026 MASSDRIVER EI (massdriver.space)
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT bflb_bl70x_l_clock_controller
#include <zephyr/kernel.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/otp.h>
#include <zephyr/sys/util.h>
#include <zep... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> .source = bl808_clkid_clk_xtal32k,
#else
.source = bl808_clkid_clk_rc32k,
#endif
.xtal_enabled =
DT_NODE_HAS_STATUS_OKAY(DT_INST_CLOCKS_CTLR_BY_NAME(0, xtal32k)),
},
.mm = {
#if CLK_SRC_IS(mm, wifipll_top)
.source = bl808_clkid_clk_wifipll,
#elif CLK_SRC_IS(mm, aupll_top)
.source = b... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2020 Mohamed ElShahawi.
* Copyright (c) 2021-2025 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT espressif_esp32_clock
#define CPU_RESET_REASON RTC_SW_CPU_RESET
#if defined(CONFIG_SOC_SERIES_ESP32)
#define DT_CPU_COMPAT espressif_xtensa... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright (C) 2022 Google, LLC
*
*/
#include <zephyr/drivers/clock_control.h>
#define DT_DRV_COMPAT fixed_clock
struct fixed_rate_clock_config {
uint32_t rate;
};
static int fixed_rate_clk_on(const struct device *dev,
clock_control_subsys_t sy... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025, FocalTech Systems CO.,Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT focaltech_ft9001_cpm
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/sys/<|fim_suffix|> * @param sys Clock subsyste... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>rol_gd32_get_rate(const struct device *dev,
clock_control_subsys_t sys,
uint32_t *rate)
{
const struct clock_control_gd32_config *config = dev->config;
uint16_t id = *(uint16_t *)sys;
uint32_t cfg;
uint8_t psc;
cfg = sys_read32(config->base + RCU_CFG0_OFFSET);
switch (GD32_CL... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Clock control driver for Infineon CAT1 MCU family.
*/
#include <zephyr/drivers/clock_control.h>
#include <... | fim | zephyrproject-rtos/zephyr | c |
/*
* SPDX-FileCopyrightText: <text>Copyright (c) 2026 Infineon Technologies AG,
* or an affiliate of Infineon Technologies AG. All rights reserved.</text>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Clock control driver for Infineon CAT1 MCU family.
*/
#include <infineon_kconfig.h>
#include <zephyr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: <text>Copyright (c) 2026 Infineon Technologies AG,
* or an affiliate of Infineon Technologies AG. All rights reserved.</text>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Clock control driver for Infineon CAT1 MCU family.
*/
#include <zephyr/drivers/clock_c... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: <text>Copyright (c) 2026 Infineon Technologies AG,
* or an affiliate of Infineon Technologies AG. All rights reserved.</text>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Peripheral Clock control driver for Infineon CAT1 MCU family.
*/
#define DT_DRV_COMPAT... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>y the respective module. */
autocg = sys_read8(config->ecpm_base + ECPM_AUTOCG);
sys_write8(autocg & ~(ECPM_AUART1CG | ECPM_AUART2CG | ECPM_ASSPICG | ECPM_ACIRCG),
config->ecpm_base + ECPM_AUTOCG);
/* The following modules are gated in the initial state */
sys_write8(ECPM_CIRCG | ECPM_SWUCCG, co... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2020 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/types.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/clock_control_litex.h>
#include "clock_control_litex.h"... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef LITEX_MMCM_H
#define LITEX_MMCM_H
#include <zephyr/sys/util.h>
#include <zephyr/types.h>
/* Common values */
#define PICOS_IN_SEC 1000000000000
/* MMCM specific numbers */
#define CLKOUT_MAX 7
#... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020, Seagate Technology LLC
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_lpc11u6x_syscon
#include <zephyr/devicetree.h>
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/clock_control/lpc11u6x_clock_control.h>
#include "clock... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>le const uint32_t reserved14[3];
volatile uint32_t starterp1; /* Start logic 1 int wake-up */
volatile const uint32_t reserved15[6];
volatile uint32_t pd_sleep_cfg; /* Deep-sleep power-down
* states
*/
volatile uint32_t pd_awake_cfg; /* Power-down states for
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ph_clock_t)(perclk->bit + 32));
break;
case ADI_MAX32_CLOCK_BUS2:
MXC_SYS_ClockDisable((mxc_sys_periph_clock_t)(perclk->bit + 64));
break;
default:
return -EINVAL;
}
return 0;
}
static int api_get_rate(const struct device *dev, clock_control_subsys_t clkcfg, uint32_t *rate)
{
ARG_UNUSED(dev... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>f (osc32k_init->enable != 0) {
if ((osc32k_init->osc32k_32khz_en != 0) ||
(osc32k_init->osc32k_1khz_en != 0)) {
if (WAIT_FOR(((osc32kctrl_regs->OSC32KCTRL_STATUS &
OSC32KCTRL_STATUS_OSC32KRDY_Msk) != 0),
TIMEOUT_OSC32KCTRL_RDY, NULL) == false) {
LOG_ERR("OSC32KCTRL... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>t32_t *mask_reg;
subsys.val = subsys_val;
mask = BIT(subsys.bits.mclkmaskbit);
mask_reg = get_mclkbus_mask_reg(config->mclk_regs, subsys.bits.mclkbus);
if (mask_reg != NULL) {
if (enable != 0) {
*mask_reg |= mask;
} else {
*mask_reg &= ~mask;
}
}
}
#define CLOCK_MCHP_PROCESS_OSCHF(nod... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
static const struct clock_mchp_config clock_config = { \
.on_timeout_ms = DT_PROP_OR(CLOCK_NODE, on_timeout_ms, 5), \
.mclk_regs = (mclk_registers_t *)DT_REG_ADDR_BY_NAME(CLOCK_NODE, mclk), \
.osc... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file clock_control_mchp_sam_d5x_e5x.c
* @brief Clock control driver for sam_d5x_e5x family devices.
*/
#include <stdbool.h>
#include <string.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_ISTS_STALL)) {
rc = -EBUSY;
break;
}
status = pcr->CLK32K_MON_ISTS;
}
pcr->CNT32K_CTRL = 0u;
htmr0->PRLD = 0;
girq23->SRC = BIT(XEC_CC_HTMR_0_GIRQ23_POS);
return rc;
}
/*
* Set the clock source for either PLL or Peripheral-32K clock domain.
* The source must be a stable 32 KHz input:... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2017, 2024-2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_imx_ccm
#include <errno.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/dt-bindings/clock/imx_ccm.h>
#include <fsl_clock.h>
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2021,2024-2026 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_imx_ccm_rev2
#include <errno.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
#include <fsl_clock.h>
#if defined(CONFIG_SOC_MIMX9352)
#include <soc.h>
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>("Unsupported clock name");
return -EINVAL;
break;
}
*rate = CLOCK_GetFreq(clock_name);
return 0;
}
static DEVICE_API(clock_control, mcux_mcg_driver_api) = {
.on = mcux_mcg_on,
.off = mcux_mcg_off,
.get_rate = mcux_mcg_get_rate,
};
DEVICE_DT_INST_DEFINE(0, NULL, NULL, NULL, NULL, PRE_KERNEL_1... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ne MCUX_PCC_INIT(inst) \
static const struct mcux_pcc_config mcux_pcc##inst##_config = { \
.base_address = DT_INST_REG_ADDR(inst), \
.clocks = clocks, \
.clock_num = ARRAY_SIZE(clocks), \
}; \
\
DEVICE_DT_INST_DEFINE(inst, \
mcux_pcc_init, \
NULL,... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>OCK_ScgSysOscAsyncDiv2Clk;
break;
#if (defined(FSL_FEATURE_SCG_HAS_SIRCDIV1) && FSL_FEATURE_SCG_HAS_SIRCDIV1)
case KINETIS_SCG_SIRC_ASYNC_DIV1_CLK:
clock_name = kCLOCK_ScgSircAsyncDiv1Clk;
break;
#endif /* (defined(FSL_FEATURE_SCG_HAS_SIRCDIV1) && FSL_FEATURE_SCG_HAS_SIRCDIV1) */
case KINETIS_SCG_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* C<|fim_suffix|>ight (c) 2019-2021 Vestas Wind Systems A/S
* Copyright (c) 2017, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_scg_k4
#include <zephyr/drivers/clock_control.h>
#include <zephyr/dt-bindings/clock/scg_k4.h>
#include <soc.h>
#include <fsl_clock.h>
#defin... | fim | zephyrproject-rtos/zephyr | c |
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