text stringlengths 14 100k | source stringclasses 1
value | repo stringclasses 810
values | language stringclasses 13
values |
|---|---|---|---|
<|fim_suffix|>int8_t *)pixels, num_pixels * config->num_colors);
}
static size_t ws2812_gpio_length(const struct device *dev)
{
const struct ws2812_gpio_cfg *config = dev->config;
return config->length;
}
static DEVICE_API(led_strip, ws2812_gpio_api) = {
.update_rgb = ws2812_gpio_update_rgb,
.length = ws2812_gpi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Jonathan Rico
*
* Adapted from the SPI driver, using the procedure in this blog post:
* https://electronut.in/nrf52-i2s-ws2812/
*
* Note: the word "word" refers to a 32-bit integer unless otherwise stated.
*
* WS/LRCK frequency:
* This refers to the "I2S word or channel se... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>, \
CONFIG_LED_STRIP_INIT_PRIORITY, NULL);
DT_INST_FOREACH_STATUS_OKAY(WS2812_RPI_PICO_PIO_INIT)
<|fim_prefix|>/*
* Copyright (c) 2023 TOKITA Hiroshi
* Copyright (c) 2025 The Zephyr Project Contributors
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/g... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 Linaro Limited
* Copyright (c) 2019, Nordic Semiconductor ASA
* Copyright (c) 2021 Seagate Technology LLC
* Copyright (c) 2025 Google LLC
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT worldsemi_ws2812_spi
#include <zephyr/drivers/led_strip.h>
#include <... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Google LLC
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* @file
* @brief WS2812 LED strip driver using a UART peripheral
*
* This driver uses a UART's asynchronous API to generate the precise,
* high-speed signal required by WS2812 and compatible LEDs.
*
* The driver e... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>N;
}
return ret;
}
static void op_done_async_rx(const struct device *dev)
{
const struct lbm_lora_config_common *config = dev->config;
struct lbm_lora_data_common *data = dev->data;
ral_lora_rx_pkt_status_t pkt_status;
uint8_t rx_buffer[CONFIG_LORA_BASICS_MODEM_ASYNC_RX_MAX_PAYLOAD];
ral_status_t... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> on first configuration to defer radio
* initialization until needed. Each driver must implement this function.
*
* @param dev Modem to initialize
*
* @retval 0 On success
* @retval -errno On failure
*/
int lbm_driver_radio_init(const struct device *dev);
/**
* @brief Configure modem for a given ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> struct lbm_sx126x_config *config = dev->config;
int ret;
if (!device_is_ready(dev)) {
return -ENODEV;
}
if (callback == NULL || handler == NULL) {
return -EINVAL;
}
gpio_init_callback(callback, handler, BIT(config->dio1.pin));
ret = gpio_add_callback(config->dio1.port, callback);
if (ret ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_id), \
}; \
DEVICE_DT_DEFINE(node_id, sx127x_driver_init, NULL, &data_##node_id, &config_##node_id, \
POST_KERNEL, CONFIG_LORA_INIT_PRIORITY, &lbm_lora_api)
DT_FOREACH_STA... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Manivannan Sadhasivam
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <timer.h>
static void timer_work_handler(struct k_work *work);
K_WORK_DEFINE(timer_work, timer_work_handler);
static uint32_t saved_time;
/* TODO: Use Non-volatile memory fo... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> LOG_DBG("Writing buffers @ 0x%" PRIx8 " (%" PRIu8 " bytes)",
offset, size);
sx126x_spi_transceive(req, NULL, sizeof(req), buffer, NULL, size);
}
void SX126xAntSwOn(void)
{
#if HAVE_GPIO_ANTENNA_ENABLE
LOG_DBG("Enabling antenna switch");
gpio_pin_set_dt(&dev_config.antenna_enable, 1);
#else
LOG_DBG... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Manivannan Sadhasivam
* Copyright (c) 2020 Andreas Sandberg
* Copyright (c) 2021 Fabio Baltieri
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_SX126X_COMMON_H_
#define ZEPHYR_DRIVERS_SX126X_COMMON_H_
#include <zephyr/types.h>
#include <zephyr/drivers/gpio... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>xSetTxParams(power, ramp_time);
}
int sx126x_variant_init(const struct device *dev)
{
struct sx126x_data *dev_data = dev->data;
if (gpio_pin_configure_dt(&sx126x_gpio_reset, GPIO_OUTPUT_ACTIVE) ||
gpio_pin_configure_dt(&sx126x_gpio_busy, GPIO_INPUT) ||
gpio_pin_configure_dt(&sx126x_gpio_dio1... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> *dev)
{
struct sx126x_data *dev_data = dev->data;
irq_disable(DT_INST_IRQN(0));
k_work_submit(&dev_data->dio1_irq_work);
}
int sx126x_variant_init(const struct device *dev)
{
IRQ_CONNECT(DT_INST_IRQN(0),
DT_INST_IRQ(0, priority),
radio_isr, DEVICE_DT_INST_GET(0), 0);
LL_EXTI_EnableIT_3... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Manivannan Sadhasivam
* Copyright (c) 2020 Grinn
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/lora.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/kernel.h>
#include "sx12xx_common.h"
#include <zephyr/logging/log.h... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Manivannan Sadhasivam
* Copyright (c) 2020 Grinn
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/lora.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/atomic.h>
#include <zephyr/kernel.h>
/* LoRaMac-node specific in... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 Andreas Sandberg
* Copyright (c) 2020 Grinn
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_SX12XX_COMMON_H_
#define ZEPHYR_DRIVERS_SX12XX_COMMON_H_
#include <zephyr/types.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/lora.h>
#include <zephyr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>;
k_mutex_unlock(&data->lock);
return ret;
}
/* Enable antenna and set RX path */
sx126x_set_rf_path(dev, true, false);
/* Start continuous reception */
ret = sx126x_set_rx(dev, 0);
if (ret < 0) {
data->rx_cb = NULL;
sx126x_set_sleep(dev);
k_mutex_unlock(&data->lock);
return ret;
}
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>lora_recv_cb rx_cb;
void *rx_cb_user_data;
/* RX duty cycle parameters (in SX126x timeout ticks) */
struct {
uint32_t rx_period;
uint32_t sleep_period;
} duty_cycle;
/* Async TX signal */
struct k_poll_signal *tx_async_signal;
/* Deferred work for interrupt handling */
struct k_work irq_wor... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 Carlo Caione <ccaione@baylibre.com>
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/spi.h>
#inc<|fim_suffix|>_hal_data(const struct device *dev)
{
struct sx126x_data *data = dev->data;
return &data->hal;... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>struct device *dev, uint8_t offset,
const uint8_t *data, size_t len);
int sx126x_hal_read_buffer(const struct device *dev, uint8_t offset,
uint8_t *data, size_t len);
int sx126x_hal_set_dio1_callback(const struct device *dev,
void (*callback)(const struct device *dev));
void sx126x_ha... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 Carlo Caione <ccaione@baylibre.com><|fim_suffix|>T_TIMEOUT);
}
int sx126x_hal_read_buffer(const struct device *dev, uint8_t offset,
uint8_t *data, size_t len)
{
const struct sx126x_hal_config *config = dev->config;
uint8_t hdr[3] = { SX126X_CMD_READ_BUFFER, offset, 0x00 }... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 Carlo Caione <ccaione@baylibre.com>
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/irq.h>
#include <stm32_ll_exti.h>
#include <stm32_ll_pwr.h>
#inc... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> Type (for SET_PACKET_PARAMS) */
#define SX126X_LORA_HEADER_EXPLICIT 0x00
#define SX126X_LORA_HEADER_IMPLICIT 0x01
/* LoRa CRC Mode (for SET_PACKET_PARAMS) */
#define SX126X_LORA_CRC_OFF 0x00
#define SX126X_LORA_CRC_ON 0x01
/* LoRa IQ Mode (for SET_PACKET... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>atarate < 7 || datarate > 12) {
LOG_ERR("datarate/spread factor must be between 7 and 12 inclusive");
return -EINVAL;
}
if (coding_rate < 1 || coding_rate > 4) {
LOG_ERR("coding rate must be between 1 and 4 inclusive");
return -EINVAL;
}
if (preamble_length < 4 || preamble_length > 7) {
LO... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>, 0),
SHELL_CMD_ARG(recv, NULL,
SHELL_HELP("Receive a LoRa packet", "[timeout (ms)]"),
cmd_lora_recv, 1, 1),
SHELL_CMD_ARG(test_cw, NULL,
SHELL_HELP("Send a continuous wave",
"<freq (Hz)> <power (dBm)> <duration (s)>"),
cmd_lora_test_cw, 4, 0),
SHELL_SUBCMD_SET_END ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Analog Devices, Inc
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT adi_mbox_max32_sema
#include <zephyr/kernel.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/mbox.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Andes Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/mbox.h>
#define LOG_LEVEL CONFIG_MBOX_LOG_LEVEL
#include <zephyr/logging/log.h>
#include <zephyr/spinlock.h>
#include <zephyr/drivers/interrupt_controller/riscv_plic.h>
LOG_MODUL... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2025 Yoan Dumas.
* Copyright (c) 2026 Muhammad Waleed Badar
*
* SPDX-License-Identifier: Apache-2.0
*
* Mailboxes Reference:
* https://github.com/raspberrypi/firmware/wiki/Mailboxes
*
*/
#define DT_DRV_COMPAT brcm_bcm2711_mbox
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#inclu... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>id *user_data)
{
ARG_UNUSED(channel);
struct esp32_mbox_data *data = (struct esp32_mbox_data *)dev->data;
if (!cb) {
LOG_ERR("Must provide callback");
return -EINVAL;
}
uint32_t key = irq_lock();
data->cb = cb;
data->user_data = user_data;
irq_unlock(key);
return 0;
}
static int esp32_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/internal/syscall_handler.h>
#include <zephyr/drivers/m<|fim_suffix|>
{
K_OOPS(K_SYSCALL_DRIVER_MBOX(dev, max_channels_get));
return z_impl_mbox_max_channels_get(dev);
}
#include ... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2024 Felipe Neves.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT linaro_ivshmem_mbox
#include <stdint.h>
#include <string.h>
#include <zephyr/device.h>
#include <zephyr/drivers/mbox.h>
#include <zephyr/drivers/virtualization/ivshmem.h>
#include <zephyr/logging/log.h>
LOG_MODU... | fim | zephyrproject-rtos/zephyr | c |
/*
* SPDX-FileCopyrightText: <text>Copyright 2024-2025 Arm Limited and/or its
* affiliates <open-source-office@arm.com></text>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT arm_mhuv3
#include <zephyr/drivers/mbox.h>
#include <zephyr/irq.h>
#include <zephyr/kernel.h>
#define LOG_LEVEL CONFIG_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
(IRQ_CONNECT(DT_INST_IRQ_BY_NAME(0, name, irq), \
DT_INST_IRQ_BY_NAME(0, name, priority), bellboard_rx_isr, \
(const void *)idx, 0); \
irq_enable(DT_INST_IRQ_BY_N... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nordic_nrf_bellboard_tx
#include <zephyr/devicetree.h>
#include <zephyr/drivers/mbox.h>
#include <haly/nrfy_bellboard.h>
struct mbox_bellboard_tx_conf {
NRF_BELLBOARD_Type *bellboard;
};
static int b... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nordic_nrf_vevif_event_rx
#include <zephyr/devicetree.h>
#include <zephyr/drivers/mbox.h>
#include <haly/nrfy_vpr.h>
#define EVENTS_IDX_MIN NRF_VPR_EVENTS_TRIGGERED_MIN
#define EVENTS_IDX... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nordic_nrf_vevif_event_tx
#include <zephyr/devicetree.h>
#include <zephyr/drivers/mbox.h>
#include <hal/nrf_vpr.h>
#include <hal/nrf_vpr_csr.h>
#include <hal/nrf_vpr_csr_vevif.h>
#define EVENTS_IDX_MAX... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
IRQ_DIRECT_CONNECT(DT_INST_IRQ_BY_IDX(0, idx, irq), DT_INST_IRQ_BY_IDX(0, idx, priority), \
vevif_task_##idx##_rx_isr, 0)
#endif
static int vevif_task_rx_init(const struct device *dev)
{
nrf_vpr_csr_vevif_tasks_clear(NRF_VPR_TASK_TRIGGER_ALL_MASK);
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nordic_nrf_vevif_task_tx
#include <zephyr/kernel.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/mbox.h>
#include <haly/nrfy_vpr.h>
#define TASKS_IDX_MAX NRF_VPR_TASKS_TRIGGER_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ruct device *dev, uint32_t channel,
mbox_callback_t cb, void *user_data)
{
struct mbox_nrf_data *data = dev->data;
if (channel >= IPC_CONF_NUM) {
return -EINVAL;
}
data->cb[channel] = cb;
data->user_data[channel] = user_data;
return 0;
}
static int mbox_nrf_mtu_get(const struct devic... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
static int nxp_imx_mu_##idx##_init(const struct device *dev) \
{ \
DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE)... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>a, \
&nxp_mailbox_##idx##_config, POST_KERNEL, CONFIG_MBOX_INIT_PRIORITY, \
&nxp_mailbox_driver_api)
#define MAILBOX_INST(idx) MAILBOX_INSTANCE_DEFINE(idx);
DT_INST_FOREACH_STATUS_OKAY(MAILBOX_INST)
<|fim_prefix|>/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2022-2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_s32_mru
#include <zephyr/drivers/mbox.h>
#include <zephyr/irq.h>
#include <zephyr/sys/util_macro.h>
#include <Mru_Ip.h>
#define LOG_LEVEL CONFIG_MBOX_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODUL... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT renesas_ra_ipc_mbox
#include <zephyr/devicetree.h>
#include <zephyr/logging/log.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/mbox.h>
#include <zephyr/irq.h>
#include <soc.... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>he write access control register (WACNTR)
*/
wacntr_val = RCAR_MFIS_WACNTR_CODEVAL(channel) |
(offs & RCAR_MFIS_WACNTR_REGADDR_MASK(channel));
rcar_mfis_write(dev, RCAR_MFIS_WACNTR(channel), wacntr_val);
/* Write register */
rcar_mfis_write(dev, offs, value);
}
static void rcar_mfis_isr(con... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> NULL) {
/* Maximum size allowed is 4 bytes */
if (msg->size > config->mhu_ch_size) {
LOG_ERR("Size %d is not valid. Maximum size is 4 bytes", msg->size);
return -EMSGSIZE;
}
if (msg->data && msg->size) {
/* Copy message */
memcpy(&message, msg->data, msg->size);
} else {
/* Clea... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>send IP signal", mbox_sio_hw->cpuid);
mbox_sio_hw->fifo_wr = 0;
__SEV();
return 0;
}
if (msg->size > MAILBOX_MBOX_SIZE) {
return -EMSGSIZE;
}
LOG_DBG("CPU %d: send IP data: %d", mbox_sio_hw->cpuid, *((int *)msg->data));
mbox_sio_hw->fifo_wr = *((uint32_t *)(msg->data));
__SEV();
return 0;... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Celina Sophie Kalus <hello@celinakalus.de>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/drivers/mbox.h>
#include <zephyr/irq.h>
#inc... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Texas Instruments Incorporated.
*
* TI OMAP Mailbox driver for Zephyr's MBOX model.
*/
#include <zephyr/devicetree.h>
#include <zephyr/drivers/mbox.h>
#include <zephyr/irq.h>
#include <zephyr/spinlock.h>
#define LOG_LEVEL CONFIG_MBOX_LOG_LEVEL
#include <zephyr/logging/log.h>
L... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Texas Instruments Incorporated.
*
* TI Secureproxy Mailbox driver for Zephyr's MBOX model.
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/spinlock.h>
#include <zephyr/kernel.h>
#include <stdio.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/mbox.h>
#incl... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Advanced Micro Devices, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/devicetree.h>
#include <zephyr/kernel.h>
#include <zephyr/irq.h>
#include <zephyr/drivers/mbox.h>
#include <zephyr/sys/util_macro.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(mb... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>imed out");
return err;
}
tmp = sys_read32(cfg->base + PSRAM_ROUGH_DELAY_CTRL5_OFFSET);
tmp &= PSRAM_REG_ROUGH_SEL_I_DQS0_UMSK;
tmp |= dqs_d_t << PSRAM_REG_ROUGH_SEL_I_DQS0_POS;
sys_write32(tmp, cfg->base + PSRAM_ROUGH_DELAY_CTRL5_OFFSET);
tmp = sys_read32(cfg->base + PSRAM_CONFIGURE_OFFSET);
t... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Analog Devices, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <soc.h>
#include <zephyr/drivers/clock_control/adi_max32_clock_control.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h>
LOG_M<|fim_suffix|>== DT_PROP_LE... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2020-2023,2026 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_imx_flexspi
#include <zephyr/logging/log.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/pm/device.h>
#include <soc.h>... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> const uint32_t *lut_ptr, uint8_t lut_count);
<|fim_prefix|>/*
* Copyright 2020,2023,2026 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <sys/types.h>
#include <fsl_flexspi.h>
/* Size of a command in the LUT table */
#define MEMC_FLEXSPI_CMD_SIZE 4U
/* Number of ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Based on memc_mcux_flexspi_s27ks0641, which is: Copyright 2021 Basalte bv
*/
#define DT_DRV_COMPAT nxp_imx_flexspi_aps6404l
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/util.h>
#inc... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2022 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Based on memc_mcux_flexspi_s27ks0641, which is: Copyright 2021 Basalte bv
*/
#define DT_DRV_COMPAT nxp_imx_flexspi_aps6408l
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/util.h>
#inc... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2023 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_imx_flexspi_is66wvq8m4
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/util.h>
#include "memc_mcux_flexspi.h"
LOG_MODULE_REGISTER(memc_flexspi_is66wvq8m4, CONFIG_MEMC_L... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_imx_flexspi_is66wvs8m8
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/util.h>
#include "memc_mcux_flexspi.h"
LOG_MODULE_REGISTER(memc_flexspi_is66wvs8m8, CONFIG_MEMC_LOG_LE... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>41_config_##n, \
POST_KERNEL, \
CONFIG_MEMC_INIT_PRIORITY, \
NULL);
DT_INST_FOREACH_STATUS_OKAY(MEMC_FLEXSPI_S27KS0641)
<|fim_prefix|>/*
* Copyright 2021 Basalte bv
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_imx_flexspi_s27ks0641
#include ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023, ithinx GmbH
* Copyright (c) 2023, Tonies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Based on memc_mcux_flexspi_s27ks0641, which is: Copyright 2021 Basalte bv
*/
#define DT_DRV_COMPAT nxp_imx_flexspi_w956a8mbya
#include <zephyr/logging/log.h>
#include <zeph... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2025 NXP
*
* SPDX-License-Ident<|fim_suffix|>ARDSRSeqIndex = 0, \
.blockRead = false, \
.blockSequenceWrite = false, \
} : NULL, \
}, \
.ptrIpAccessConfig = &(xspi_ip_access_config_t){ \
.ipAccessTimeoutValue = 0xFFFFFFFF, \
.ptrSfpFradConfig = NULL, \
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ux_xspi_update_device_addr_mode(const struct device *dev,
xspi_device_addr_mode_t addr_mode);
/**
* @brief Get XSPI root clock frequency with Hz.
*
* @return 0 on success, negative value on failure
*/
int memc_mcux_xspi_get_root_clock(const struct device *dev, uint32_t *clock_rate);
/**
* @br... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_xspi_psram
#include <zephyr/logging/log.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/pm/device.h>
#include <soc.h>
#include "memc_mcux_xspi.h"
LOG_MODULE_REGIST... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>%u", buffer, __LINE__);
*vendor_id = buffer & 0xff;
return ret;
}
#if CONFIG_PM_DEVICE
static int memc_mspi_aps6404l_half_sleep_enter(const struct device *psram)
{
int ret;
LOG_DBG("Putting aps6404l to half sleep/%u", __LINE__);
ret = memc_mspi_aps6404l_command_write(psram, APS6404L_HALF_SLEEP_ENT... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_LOW, \
.dqs_enable = DT_INST_PROP(n, mspi_dqs_enable), \
.rx_dummy = MEMC_MSPI_APS_Z8_RX_DUMMY_DEFAULT, \
.tx_dummy = MEMC_MSPI_APS_Z8_TX_DUMMY_DEFAULT, \
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> /* [2..2] Burst type */
uint8_t RBX: 1; /* [3..3] Row Boundary Crossing Read EN */
uint8_t: 2;
uint8_t IOM: 1; /* [6..6] IO mode */
uint8_t: 1;
} MR8_b;
};
};
enum memc_aps_version {
MEMC_DEFAULT,
MEMC_APS25... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>BUFFERS, \
"ahb-buffers-sizes must be of size QSPI_IP_AHB_BUFFERS"); \
BUILD_ASSERT( \
_CONCAT(FEATURE_QSPI_, DT_INST_STRING_UPPER_TOKEN(n, a_rx_clock_source)) == 1,\
"a-rx-clock-source source mode selected is not supported"); \
\
static const Qspi_Ip_ControllerConfigType ... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2023 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <sys/types.h>
#include <Qspi_Ip.h>
/**
* @brief Build a QSPI Look-up Table (LUT) sequence entry.
*
* @param inst instruction
* @param pads pad information
* @param op operand
*/
#define QSPI_LUT_OP(inst, ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>dTime = DT_INST_PROP(n, cs_hold_time), \
.csSetupTime = DT_INST_PROP(n, cs_setup_time), \
.sampleDelay = XSPI_SAMPLE_DELAY(n), \
.samplePhase = XSPI_SAMPLE_PHASE(n), \
.ahbConfig = XSPI_AHB_BUFFERS(n), \
XSPI_SIDE_CFG(n, a, A) \
XSPI_DATA_CFG(n) \
XSPI_ADDR_CFG(... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ERS_MEMC_MEMC_NXP_S32_XSPI_H_ */
<|fim_prefix|>/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_MEMC_MEMC_NXP_S32_XSPI_H_
#define ZEPHYR_DRIVERS_MEMC_MEMC_NXP_S32_XSPI_H_
#include <zephyr/device.h>
#include <sys/types.h>
/**
* @brief Get the XSPI peripheral... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ST_DEFINE(0);
static const struct memc_renesas_ra_sdram_config config = {
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
};
DEVICE_DT_INST_DEFINE(0, renesas_ra_sdram_init, NULL, NULL, &config, POST_KERNEL,
CONFIG_MEMC_INIT_PRIORITY, NULL);
<|fim_prefix|>/*
* Copyright (c) 2024 Renesas Electronics... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ng, 1))
#define BANK_CONFIG(node_id) \
{ \
.cs = DT_REG_ADDR(node_id), \
.mode = COND_CODE_1(DT_ENUM_IDX(node_id, atmel_smc_write_mode), \
(SMC_MODE_WRITE_MODE), (0)) \
| COND_CODE_1(DT_ENUM_IDX(node_id, atmel_smc_read_mode), \
(SMC_MODE_READ_MODE), (0))... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* Copyright (c) 2025 Silicon Laboratories Inc.
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT silabs_siwx91x_qspi_memory
#include <zephyr/logging/log.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/sys/util.h>
#include <zephyr/device.h>... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT renesas_smartbond_nor_psram
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/irq.h>
#include <DA1469xAB.h>
#include <zephyr/pm/device.h>
#include <da1469x_qs... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ot select FMC clock (%d)", r);
return r;
}
}
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_fmc)
#if (DT_ENUM_IDX(DT_DRV_INST(0), st_mem_swap) == 1)
/* sdram-sram */
stm32_reg_modify_bits(&FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP, FMC_BCR1_BMAP_0);
#elif (DT_ENUM_IDX(DT_DRV_INST(0), st_mem_swap) == 2)
/* s... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Georgij Cernysiov
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT st_stm32_fmc_nor_psram
#include <soc.h>
#include <zephyr/device.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(memc_stm32_nor_psram, CONFIG_MEMC_LOG_LEVEL);
/** FMC NOR/PSRAM controlle... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>lock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
(clock_control_subsys_t)&dev_cfg->pclken, &ahb_clock_freq) < 0) {
return -EIO;
}
#endif
#if DT_CLOCKS_HAS_NAME(STM32_OSPI_NODE, ospi_mgr)
if (clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
(clock_control_subsys_t)... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>X(node_id, st_sdram_timing, 1), \
.SelfRefreshTime = DT_PROP_BY_IDX(node_id, st_sdram_timing, 2), \
.RowCycleDelay = DT_PROP_BY_IDX(node_id, st_sdram_timing, 3), \
.WriteRecoveryTime = DT_PROP_BY_IDX(node_id, st_sdram_timing, 4), \
.RPDelay = DT_PROP_BY_IDX(n... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> &memc_stm32_xspi_data, &memc_stm32_xspi_cfg,
POST_KERNEL, CONFIG_MEMC_INIT_PRIORITY,
NULL);
<|fim_prefix|>/*
* Copyright (c) 2025 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT st_stm32_xspi_psram
#include <errno.h>
#include <soc.h>
#includ... | fim | zephyrproject-rtos/zephyr | c |
/*
* (C) Copyright 2020-2021 SiFive, Inc.
* (C) Copyright 2023 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*
* Based on implementation of fsbl in:
* https://github.com/sifive/freedom-u540-c000-bootloader
*/
#define DT_DRV_COMPAT sifive_fu740_c000_ddr
#include <zephyr/init.h>
#include <... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>0, /* DENALI_PHY_1179_DATA */
0x00000000, /* DENALI_PHY_1180_DATA */
0x00000803, /* DENALI_PHY_1181_DATA */
0x223FFF00, /* DENALI_PHY_1182_DATA */
0x000008FF, /* DENALI_PHY_1183_DATA */
0x0000057F, /* DENALI_PHY_1184_DATA */
0x0000057F, /* DENALI_PHY_1185_DATA */
0x00037FFF, /* DENALI_PHY_1186_DATA... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ret;
ret = config->bus_init(dev);
if (ret < 0) {
return ret;
}
if (config->reset_gpio.port) {
if (!gpio_is_ready_dt(&config->reset_gpio)) {
return -ENODEV;
}
ret = gpio_pin_configure_dt(&config->reset_gpio, GPIO_OUTPUT_INACTIVE);
if (ret < 0) {
return ret;
}
}
ret = mfd_add559x... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Prevas A/S
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_MFD_AD559X_H_
#define ZEPHYR_DRIVERS_MFD_AD559X_H_
#ifdef __cplusplus
extern "C" {
#endif
#define DT_DRV_COMPAT adi_ad559x
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#if DT_ANY_INST_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>onst struct mfd_ad559x_transfer_function mfd_ad559x_i2c_transfer_function = {
.read_raw = mfd_ad559x_i2c_read_raw,
.write_raw = mfd_ad559x_i2c_write_raw,
.read_reg = mfd_ad559x_i2c_read_reg,
.write_reg = mfd_ad559x_i2c_write_reg,
};
int mfd_ad559x_i2c_init(const struct device *dev)
{
const struct mf... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Grinn
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/drivers/mfd/ad559x.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/sys/byteorder.h>
#include "mfd_ad559x.h"
static int mfd_ad559x_spi_read_raw(const struct device *dev, uint8_t *va... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>egister (0x36) bit 0.
* 3. enable MR shipment mode in supervisory register (0x2D) bit 1,
* pull MR down for 12 seconds and then release.
*
* This implements method 2.
*/
return mfd_adp5360_reg_write(dev, ADP5360_MFD_REG_SHIPMENT, 1U);
}
int mfd_adp5360_shipment_mode_disable(const struct dev... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ndler */
#if defined(CONFIG_ADP5360_TRIGGER_OWN_THREAD)
K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_ADP5360_THREAD_STACK_SIZE);
K_KERNEL_STACK_MEMBER(pgood1_thread_stack, CONFIG_ADP5360_THREAD_STACK_SIZE);
K_KERNEL_STACK_MEMBER(pgood2_thread_stack, CONFIG_ADP5360_THREAD_STACK_SIZE);
K_KERNEL_STACK_MEMB... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 Analog Devices Inc.
* SPDX-License-Identifier: Apache-2.0
*/
#include <errno.h>
#include <zephyr/drivers/mfd/adp5360.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/logging/log.h>
#include "mfd_adp5360.h"
LOG_MODULE_REGISTER(mfd_adp5360_trig, CONFIG_MFD_LOG_LEVEL);
#def... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>oat */
if (gpio_is_ready_dt(&config->reset_gpio)) {
ret = gpio_pin_configure_dt(&config->reset_gpio, GPIO_OUTPUT_INACTIVE);
if (ret) {
LOG_ERR("%s: configure reset pin failed: %d", dev->name, ret);
return ret;
}
} else {
LOG_WRN("%s: reset pin not configured", dev->name);
}
ret = mfd_ad... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>3B_ID_VALUE) {
return -1;
}
return 0;
}
struct k_sem *aw9523b_get_lock(const struct device *dev)
{
struct mfd_aw9523b_data *data = dev->data;
return &data->lock;
}
#define MFD_AW9523B_DEFINE(inst) \
static const struct mfd_aw9523... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Martin Kiepfer <mrmarteng@teleschirm.org>
* SPDX-License-Identifier: Apache-2.0
*/
#include <errno.h>
#include <stdbool.h>
#include <zephyr/drivers/mfd/axp192.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/sys/util.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(m... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
\
DEVICE_DT_DEFINE(node, mfd_axp2101_init, NULL, \
COND_CODE_1(MFD_AXP2101_INTERRUPT, (&data##node), (NULL)), \
&config##node, PO... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2024 SILA Embedded Solutions GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT rohm_bd8lb600fs
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/drivers... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> mfd_ds3231_conf config##inst = {.i2c_bus = \
I2C_DT_SPEC_INST_GET(inst)}; \
static struct mfd_ds3231_data data##inst; \
DEVICE_DT_INST_DEFINE(inst, &mfd_ds3231_init, NULL, &data##inst, &config##inst, \... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: <text>Copyright (c) 2026 Infineon Technologies AG,
* or an affiliate of Infineon Technologies AG. All rights reserved.</text>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief MFD driver for Infineon AutAnalog subsystem.
*
* The AutAnalog (Autonomous Analog) sub... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>fx_autanalog_set_irq_handler(cfg->parent, dev, periph, autanalog_ctb_isr);
LOG_DBG("AutAnalog CTB%u MFD initialized", cfg->ctb_idx);
return 0;
}
/* clang-format off */
#define IFX_AUTANALOG_CTB_INIT(n) \
static struct ifx_autanalog_ctb_dat... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: <text>Copyright (c) 2026 Infineon Technologies AG,
* or an affiliate of Infineon Technologies AG. All rights reserved.</text>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief MFD driver for Infineon AutAnalog PRB (Programmable Reference Block).
*
* The PRB cont... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: <text>Copyright (c) 2026 Infineon Technologies AG,
* or an affiliate of Infineon Technologies AG. All rights reserved.</text>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief MFD driver for Infineon AutAnalog PTComp (Programmable Threshold Comparator).
*
* The ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
static void ifx_hppass_mfd_irq_config_##n(const struct device *dev); \
\
static const struct ifx_hppass_mfd_config ifx_hppass_mfd_con... | fim | zephyrproject-rtos/zephyr | c |
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