text stringlengths 14 100k | source stringclasses 1
value | repo stringclasses 810
values | language stringclasses 13
values |
|---|---|---|---|
<|fim_prefix|>/*
* Copyright 2021 BayLibre, SAS
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(intc_gicv3_its, LOG_LEVEL_ERR);
#include <zephyr/cache.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/interrupt_co... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>IG_GIC_V3_ITS
void its_rdist_map(void);
void its_rdist_invall(void);
extern atomic_t nlpi_intid;
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_INTC_GICV3_PRIV_H_ */
<|fim_prefix|>/*
* Copyright 2020 Broadcom
* Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
*
* SPDX-License-I... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2016 Open-RnD Sp. z o.o.
* Copyright (c) 2017 RnDity Sp. z o.o.
* Copyright (c) 2019-23 Linaro Limited
* Copyright (C) 2025 Savoir-faire Linux, Inc.
* Copyright (c) 2025 Alexander Kozhinov <ak.alexander.kozhinov@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brie... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>io_intc_init,
NULL, &gpio_intc_data, NULL, PRE_KERNEL_1,
CONFIG_INTC_INIT_PRIORITY, NULL);
/**
* @brief STM32 GPIO interrupt controller API implementation
*/
/**
* @internal
* STM32WB0 GPIO interrupt controller driver:
* The type @ref stm32_gpio_irq_line_t is used to hold the LL_EXTI_LINE_Pxy... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Andrew Featherstone
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT hazard3_hazard3_intc
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/irq.h>
#include <zephyr/device.h>
#include <zephyr/types.h>
#include <zephyr/arch/riscv/csr.h>
#i... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 Intel Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT intel_vt_d
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <soc.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <string.h>
#include <zephyr/... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 Intel Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_INTEL_VTD_H_
#define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_INTEL_VTD_H_
#define VTD_INT_SHV BIT(3)
#define VTD_INT_FORMAT BIT(4)
/* We don't care about int_idx[15], ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>evice *dev,
enum pm_device_action action)
{
int ret = 0;
switch (action) {
case PM_DEVICE_ACTION_RESUME:
ret = ioapic_resume_from_suspend(dev);
break;
case PM_DEVICE_ACTION_SUSPEND:
ret = ioapic_suspend(dev);
break;
default:
ret = -ENOTSUP;
}
return ret;
}
#endif /*CONFIG_PM_DE... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>OAPIC_VEC_MASK 0x000000ff
/* VTD related macros */
#define IOAPIC_VTD_REMAP_FORMAT BIT(16)
/* We care only about the first 14 bits.
* The 15th bits is in the first 32bits of RTE but since
* we don't go up to that value, let's ignore it.
*/
#define IOAPIC_VTD_INDEX(index) (index << 17)
#endif /* ZEPH... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019-2020 Cobham Gaisler AB
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* This is a driver for the GRLIB IRQMP interrupt controller common in LEON
* systems.
*
* Interrupt level 1..15 are SPARC interrupts. Interrupt level 16..31, if
* implemented in the interrupt controller,... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>C interrupt status of the pin */
sys_write8(BIT(i), intc_base + INTC_GRPNISR(g));
}
int ite_intc_irq_is_enable(unsigned int irq)
{
uint32_t g, i;
uint8_t en;
if (irq > CONFIG_NUM_IRQS) {
return 0;
}
g = irq / MAX_REGISR_IRQ_NUM;
i = irq % MAX_REGISR_IRQ_NUM;
en = sys_read8(intc_base + INTC_GR... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 ITE Corporation. All Rights Reserved
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/arch/riscv/irq.h>
#include <zephyr/init.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(intc_it8xxx2, LOG_LEVEL_DBG);... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
*<|fim_suffix|> ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_ITE_IT8XXX2_H_
#include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
#include <ilm.h>
#include <soc.h>
#endif /* ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_ITE_IT8XXX2_H_ */
<|fim_middle|> Copyright (c) 2020 ITE Corporation. All Rights R... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>irq / MAX_REGISR_IRQ_NUM;
index = irq % MAX_REGISR_IRQ_NUM;
return IS_MASK_SET(IT8XXX2_INTC_IER(group), BIT(index));
}
ite_irq_t __soc_ram_code ite_intc_get_irq_num(void)
{
return intc_irq;
}
bool __soc_ram_code ite_intc_no_irq(void)
{
return (IVECT == IVECT_OFFSET_WITH_IRQ);
}
unsigned long __soc... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 1984-2008, 2011-2015 Wind River Systems, Inc.
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT intel_loapic
/*
* driver for x86 CPU local APIC (as an interrupt controller)
*/
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/pm/device.h>
#in... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>t val = source % 32;
volatile rv32_intc_grp_t *int_grp = ®s->intr[grp];
volatile rv32_intc_grp_t *event_grp = ®s->event[grp];
unsigned int key;
key = arch_irq_lock();
int_grp->clear_pending |= BIT(val);
event_grp->clear_pending |= BIT(val);
arch_irq_unlock(key);
}
uint32_t max32_rv32_intc_g... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>isable and clear all interrupts initially */
for (i = 0; i < AIC_SSR_Msk + 1; i++) {
aic->AIC_SSR = AIC_SSR_INTSEL(i);
aic->AIC_IDCR = AIC_IDCR_INTD_Msk;
aic->AIC_ICCR = AIC_ICCR_INTCLR_Msk;
}
k_spin_unlock(&lock, key);
return 0;
}
#define MCHP_AIC_INIT(n) \
BUILD_ASSERT(n < AIC_TYPE... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Driver for External interrupt controller in Microchip XEC devices
*
* Driver is currently implemented to support MEC172x ECIA GIRQs
*/
#define DT_DRV_COMPAT microchip_xec_ecia
#include <zep... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ters_t *regs, uint8_t eic_line)
{
uint16_t pin_mask = BIT(eic_line);
regs->EIC_INTFLAG = pin_mask;
regs->EIC_INTENSET |= pin_mask;
}
static void disable_interrupt_line(eic_registers_t *regs, uint8_t eic_line)
{
regs->EIC_INTENCLR = BIT(eic_line);
}
int eic_mchp_disable_interrupt(struct eic_config_pa... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2020 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nuvoton_npcx_miwu
/**
* @file
* @brief Nuvoton NPCX MIWU driver
*
* The device Multi-Input Wake-Up Unit (MIWU) supports the Nuvoton embedded
* controller (EC) to exit 'Sleep' or 'Deep Slee... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>q = DT_INST_IRQN(N), \
.irq_mask = DT_INST_PROP(N, mask), \
.sw_isr_off = (N + 1) * 32, \
.enable_reg = (void *)DT_INST_REG_ADDR(N), \
.status_reg = (void *)DT_INST_PROP(N, status_reg) }; \
DEVICE_DT_INST_DEFINE(N, NULL, NULL, NULL, &dev_cfg##N, PRE_KERNEL_1, 0, NULL);
DT_INST_FOREACH_STAT... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024, Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/drivers/interrupt_controller/riscv_clic.h>
#include <hal/nrf_vpr_clic.h>
void riscv_clic_irq_enable(uint32_t irq)
{
nrf_vpr_clic_int_enable_set(NRF_VPRCLIC, irq, ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2026 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <soc.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/sys/util.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/interrupt_controller/intc_nxp_gint.h>
#include <zephyr/drivers/reset.h>
#incl... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_unlocked(&dispatchers[i], level2_irq);
} else {
irqstr_release_irq_unlocked(&dispatchers[i], level2_irq);
}
}
return;
}
}
void z_soc_irq_enable(uint32_t irq)
{
z_soc_irq_enable_disable(irq, true);
}
void z_soc_irq_disable(uint32_t irq)
{
z_soc_irq_enable_disable(irq, false);
}
int z_... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2023 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Based on STM32 EXTI driver, which is (c) 2016 Open-RnD Sp. z o.o. */
#include <zephyr/device.h>
#include <zephyr/irq.h>
#include <errno.h>
#include <zephyr/drivers/interrupt_controller/nxp_pint.h>
#include <zephyr/pm/device.h>
#include <fsl_in... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
}; \
static int nxp_siul2_eirq_init_##n(const struct device *dev) \
{ ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
* Copyright (c) 2023 Meta
* Contributors: 2018 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT sifive_plic_1_0_0
/**
* @brief Platform Level Interrupt Controller (PLIC) driver
* ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ROUP_INTERRUPT_ENABLE,
(void *)&group_priority);
} else {
err = R_BSP_InterruptControl(vector, BSP_INT_CMD_GROUP_INTERRUPT_DISABLE, NULL);
}
if (err != BSP_INT_SUCCESS) {
k_spin_unlock(&data->lock, key);
return -EINVAL;
}
k_spin_unlock(&data->lock, key);
return 0;
}
int rx_grp_in... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT renesas_rx_icu
#include <zephyr/device.h>
#include <zephyr/irq.h>
#include <soc.h>
#include <zephyr/spinlock.h>
#include <zephyr/drivers/interrupt_controller/intc_rx_icu.h>
#include ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024-2026 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT renesas_rz_ext_irq
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/irq.h>
#include <... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT renesas_rz_icu_v2
#include <zephyr/device.h>
#include <zephyr/irq.h>
#include <zephyr/drivers/interrupt_controller/intc_rz_icu.h>
#include <zephyr/drivers/interrupt_controller/gic... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>rite
*/
TINT_STATUS_READ(tint);
}
int intc_rz_tint_enable(const struct device *dev)
{
const struct intc_rz_tint_config *config = dev->config;
irq_enable(config->irq);
return 0;
}
int intc_rz_tint_disable(const struct device *dev)
{
const struct intc_rz_tint_config *config = dev->config;
irq_d... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Unified AIA coordinator - wraps APLIC and IMSIC for Zephyr integration.
*
* This driver presents AIA (APLIC + IMSIC) as a single interrupt controller
* to Zephyr, hiding the interna... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT riscv_aplic
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/drivers/interrupt_controller/riscv_aplic.h>
#ifdef CONFIG_R... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ivery_off(cpu), APLIC_IDC_IDELIVERY_ENABLE);
/* ithreshold = 0b0 -- All enabled sources can signal */
wr32(cfg->base, aplic_ithreshold_off(cpu), APLIC_IDC_ITHRESHOLD);
}
/* Configure IRQ for APLIC driver */
cfg->irq_config_func();
return 0;
}
<|fim_prefix|>/*
* Copyright (c) Qualcomm Technologi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ruct aplic_data *data = dev->data;
k_spinlock_key_t key = k_spin_lock(&data->lock);
wr32(cfg->base, APLIC_GENMSI, genmsi_val);
k_spin_unlock(&data->lock, key);
LOG_DBG("GENMSI injection: hart=%u context=%u eiid=%u, wrote=0x%08x readback=0x%08x",
hart_id, context, eiid, genmsi_val, rd32(cfg->base,... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>RISCV_APLIC_MSI is enabled.
* Configures MSI address registers and enables MSI delivery.
*
* @param dev APLIC device
* @return 0 on success, negative error code on failure
*/
int aplic_msi_init(const struct device *dev);
#endif /* CONFIG_RISCV_APLIC_MSI */
#endif /* ZEPHYR_DRIVERS_INTERRUPT_CONTROLL... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Synopsys, Inc.
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT riscv_imsic
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#if defined(CONFIG_RISCV_AIA)
#include <zephyr/drivers/interrupt_controller/riscv_aia.h>
#endif
#include <ze... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 Foundries.io
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT openisa_rv32m1_intmux
/**
* @file
* @brief RV32M1 INTMUX (interrupt multiplexer) driver
*
* This driver provides support for level 2 interrupts on the RV32M1
* SoC using the INTMUX peripheral.
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Derek Hageman <hageman@inthat.cloud>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT atmel_sam0_eic
#include <zephyr/device.h>
#include <zephyr/irq.h>
#include <soc.h>
#include <zephyr/drivers/interrupt_controller/sam0_eic.h>
#include "intc_sam0_eic_priv.h"
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Derek Hageman <hageman@inthat.cloud>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_SAM0_EIC_PRIV_H_
#define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_SAM0_EIC_PRIV_H_
#include <errno.h>
#include <zephyr/types.h>
#include <soc.h>
/... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2015 - 2023 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT shared_irq
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/shared_irq.h>
#include <zephyr/init.h>
#include <zephyr/sys/sys_io.h>
#include <zep... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Western Digital Corporation or its affiliates
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifdef CONFIG_DT_HAS_SWERV_PIC_ENABLED
#define DT_DRV_COMPAT swerv_pic
#else
#define DT_DRV_COMPAT cdns_swerv_pic
#endif
/**
* @brief SweRV PIC driver
*/
#include <zephyr/kernel.h>
#in... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_COUNT) - 1)
/**
* @brief Program interrupt controller
*
* This routine programs the interrupt controller with the given vector
* based on the given IRQ parameter.
*
* Drivers call this routine instead of IRQ_CONNECT() when interrupts are
* configured statically.
*
* The Galileo board virtualize... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>riscv/irq.h>
#define IRQ_MASK DT_INST_REG_ADDR_BY_NAME(0, irq_mask)
#define IRQ_PENDING DT_INST_REG_ADDR_BY_NAME(0, irq_pending)
static inline void vexriscv_litex_irq_setmask(uint32_t mask)
{
__asm__ volatile ("csrw %0, %1" :: "i"(IRQ_MASK), "r"(mask));
}
static inline uint32_t vexriscv_litex_irq_ge... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* Copyright (C) 2023 BeagleBoard.org Foundation
* Copyright (C) 2023 S Prashanth
* Copyright (C) 2025 Siemens Mobility GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ti_vim
#include <stdint.h>
#include <zephyr/arch/arm/irq.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/de... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2025 Michael Hope <michaelh@juju.nz>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT wch_exti
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/irq.h>
#include <zephyr/sys/util_macro.h>
#include <zephyr/drivers/interrupt_controller/wch_exti.h>
#include <hal_ch32f... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2024 Michael Hope
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT wch_pfic
#include <hal_ch32fun.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/init.h>
#include <zephyr/irq.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/util.h>
#define SEVONPEND BIT(4)
#define WFITOWFE ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2023-2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_s32_wkpu
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/irq.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/sys/math_extras.h>
#include <zephyr/drivers/interrupt_controller/in... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>T_REG_ADDR_BY_NAME(0, eru0),
(XMC_ERU_t *)DT_INST_REG_ADDR_BY_NAME(0, eru1),
},
};
DEVICE_DT_INST_DEFINE(0, intc_xmc4xxx_init, NULL,
&intc_xmc4xxx_data0, &intc_xmc4xxx_config0, PRE_KERNEL_1,
CONFIG_INTC_INIT_PRIORITY, NULL);
<|fim_prefix|>/*
* Copyright (c) 2022 Schlumberger
*
* SPDX-License-Id... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>c_cfg_##inst = { \
.reg_wuemr = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 0), \
.reg_wuesr = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 1), \
.reg_wuenr = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 2), ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 ITE Corporation. All Rights Reserved
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ite_it8xxx2_wuc
#include <zephyr/device.h>
#include <zephyr/drivers/interrupt_controller/wuc_ite_it8xxx2.h>
#include <zephyr/dt-bindings/interrupt-controller/it8xxx2-wuc.h>
#... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT espressif_esp32_ipm
#include "soc/dport_reg.h"
#include "soc/gpio_periph.h"
#include <stdint.h>
#include <string.h>
#include <zephyr/device.h>
#include <zephyr/drivers/ipm.... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>onst struct device *dev)
{
K_OOPS(K_SYSCALL_DRIVER_IPM(dev, max_id_val_get));
return z_impl_ipm_max_id_val_get((const struct device *)dev);
}
#include <zephyr/syscalls/ipm_max_id_val_get_mrsh.c>
static inline int z_vrfy_ipm_set_enabled(const struct device *dev, int enable)
{
K_OOPS(K_SYSCALL_DRIVER_IP... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2018,2023 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_imx_mu
#include <errno.h>
#include <string.h>
#include <zephyr/device.h>
#include <soc.h>
#include <zephyr/drivers/ipm.h>
#include <zephyr/irq.h>
#include <zephyr/sys/barrier.h>
#ifdef CONFIG_HAS_MCUX
/* MCUX HAL us... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> &ivshmem_ipm_driver_api); \
DT_INST_FOREACH_STATUS_OKAY(IPM_IVSHMEM_INIT);
<|fim_prefix|>/*
* Copyright (c) 2023 Linaro.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT linaro_ivshmem_ipm
#include <stdint.h>
#include <string.h>
#include <zephyr/device.h>
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>BOX_DEV_DEFINE)
<|fim_prefix|>/*
* Copyright (c) 2024 Texas Instruments Incorporated
* Andrew Davis <afd@ti.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT zephyr_mbox_ipm
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/ipm.h>
#include <zephyr/dr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017-2018, 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_lpc_mailbox
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/drivers/ipm.h>
#include <fsl_mailbox.h>
#include <fsl_clock.h>
#include <soc.h>
#include <zephyr/irq.h>
#include <zep... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> &ipm_mhu_driver_api);
static void ipm_mhu_irq_config_func_0(const struct device *d)
{
ARG_UNUSED(d);
IRQ_CONNECT(DT_INST_IRQN(0),
DT_INST_IRQ(0, priority),
ipm_mhu_isr,
DEVICE_DT_INST_GET(0),
0);
irq_enable(DT_INST_IRQN(0));
}
static void ipm_mhu_irq_config_func_1(const struct device *d... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>t Status Register */
volatile uint32_t cpu0intr_stat;
volatile uint32_t cpu0intr_set; /* ( /W) CPU 0 Interrupt Set Register */
volatile uint32_t cpu0intr_clr; /* ( /W) CPU 0 Interrupt Clear Register */
volatile uint32_t reserved0;
/* (R/ ) CPU 1 Interrupt Status Register */
volatile uint32_t cpu1i... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019, Nordic Semiconductor
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nordic_nrf_ipc
#include <string.h>
#include <zephyr/drivers/ipm.h>
#include <nrfx_ipc.h>
#include "ipm_nrfx_ipc.h"
#define LOG_LEVEL CONFIG_IPM_LOG_LEVEL
#include <zephyr/logging/log.h>
#i... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>nabled = IPC_EVENT_BITS,
};
<|fim_prefix|>/*
* Copyright (c) 2019, Nordic Semiconductor
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <nrfx_ipc.h>
#define NRFX_IPC_ID_MAX_VALUE IPC_CONF_NUM
/*
* Group IPC signals, events and channels into message channels.
* Message channels are one-way co... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020-2023 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT intel_sedi_ipm
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/pm/device.h>
#include <zephyr/drivers/ipm.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(ipm_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020-2023 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __DRIVERS_IPM_SEDI_H
#define __DRIVERS_IPM_SEDI_H
#ifdef __cplusplus
extern "C" {
#endif
#include "sedi_driver_common.h"
#include "sedi_driver_ipc.h"
#include <zephyr/sys/atomic.h>
/*
* bit 31 indicate... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>clearflag_cicr(HSEM, mask_semid);
}
static void stm32_hsem_mailbox_irq_config_func(const struct device *dev)
{
ARG_UNUSED(dev);
IRQ_CONNECT(DT_INST_IRQN(0),
DT_INST_IRQ(0, priority),
stm32_hsem_mailbox_ipm_rx_isr, DEVICE_DT_INST_GET(0), 0);
irq_enable(DT_INST_IRQN(0));
}
int stm32_hsem_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 ST Microelectronics Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT st_stm32_ipcc_mailbox
#include <zephyr/drivers/clock_control.h>
#include <zephyr/device.h>
#include <errno.h>
#include <zephyr/drivers/ipm.h>
#include <soc.h>
#include <stm32_ll_ipcc.... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Advanced Micro Devices, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT xlnx_zynqmp_ipi_mailbox
#include "ipm_xlnx_ipi.h"
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/drivers/ipm.h>
#include <zephyr/irq.h>
#include <zephyr/logging/log... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023, Advanced Micro Devices Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _IPM_XLNX_IPI_H_
#define _IPM_XLNX_IPI_H_
/* IPI Channel ID bits */
#define IPI_CH0_BIT 0
#define IPI_CH1_BIT 8
#define IPI_CH2_BIT 9
#define IPI_CH3_BIT 16
#define IPI_CH4_BIT 17
#define IPI... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
&ht16k33_##id##_cfg, POST_KERNEL, \
CONFIG_LED_INIT_PRIORITY, &ht16k33_leds_api)
#else /* ! CONFIG_HT16K33_KEYSCAN */
#define HT16K33_DEVICE_WITH_IRQ(id) HT16K33_DEVICE(id)
#endif /* ! CONFIG_HT16K33_KEYSCAN */
#define HT16K33_INSTANTIATE(id) \
COND_CODE_1(DT_INST_NODE_HAS_PROP(id,... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>is31fl319##id##_config_##n, POST_KERNEL, \
CONFIG_LED_INIT_PRIORITY, &is31fl319x_led_api);
#define DT_DRV_COMPAT issi_is31fl3194
DT_INST_FOREACH_STATUS_OKAY_VARGS(IS31FL319X_DEVICE, 4, IS31FL3194_CHANNEL_COUNT,
&is31f13194_model)
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT issi_is31fl3197... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>16a_cfg is31fl3216a_##id##_cfg = { \
.i2c = I2C_DT_SPEC_INST_GET(id), \
}; \
DEVICE_DT_INST_DEFINE(id, &is31fl3216a_init, NULL, NULL, \
&is31fl3216a_##id##_cfg, POST_KERNEL, \
CONFIG_LED_INIT_PRIORITY, &is31fl3216a_led_api);
DT_INST_FOREACH_STATUS_OKAY(IS31FL3216A_INIT)
<|fim_prefix|>/... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2022-2023 Daniel DeGrasse <daniel@degrasse.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT issi_is31fl3733
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/led.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/led/is3... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>se CHGLED_CTRL_TYPE_A:
case CHGLED_CTRL_TYPE_B:
case CHGLED_CTRL_BY_REG:
case CHGLED_CTRL_BY_CHARGE:
return i2c_reg_update_byte_dt(&config->i2c, config->addr,
config->mode_mask << config->mode_offset,
config->mode << config->mode_offset);
}
return -EINVAL;
}
#define LED_AXPX... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Prevas A/S
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT dac_leds
#include <errno.h>
#include <stdint.h>
#include <zephyr/device.h>
#include <zephyr/drivers/dac.h>
#include <zephyr/drivers/led.h>
#include <zephyr/sys/math_extras.h>
struct led_dac_leds {
cons... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: Copyright (c) 2026 Henrik Brix Andersen <henrik@brixandersen.dk>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/drivers/led.h>
#include <zephyr/drivers/led/led_fake.h>
#include <zephyr/fff.h>
#include <zephyr/sys/util.h>
#ifdef CON... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>led = &config->led[i];
if (device_is_ready(led->port)) {
err = gpio_pin_configure_dt(led, GPIO_OUTPUT_INACTIVE);
if (err) {
LOG_ERR("Cannot configure GPIO (err %d)", err);
}
} else {
LOG_ERR("%s: GPIO device not ready", dev->name);
err = -ENODEV;
}
}
return err;
}
static DEV... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ss));
return z_impl_led_set_brightness((const struct device *)dev, led,
value);
}
#include <zephyr/syscalls/led_set_brightness_mrsh.c>
static inline int
z_vrfy_led_write_channels(const struct device *dev, uint32_t start_channel,
uint32_t num_channels, const uint8_t *buf)
{
K_OOPS(K_SYSCALL_O... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2022 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT microchip_xec_bbled
/**
* @file
* @brief Microchip Breathing-Blinking LED controller
*/
#include <soc.h>
#ifndef CONFIG_SOC_SERIES_MEC15XX
#include <zephyr/drivers/clock_control/mchp_xec_clock_co... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
DEVICE_DT_INST_DEFINE(n, &led_npm10xx_init, NULL, &led_npm10xx_data##n, \
&led_npm10xx_config##n, POST_KERNEL, CONFIG_LED_INIT_PRIORITY, \
&led_npm10xx_api);
DT_INST_FOREACH_STATUS_OKAY(LED_NPM10XX_DEFINE)
<|fim_prefix|>/*
* Copyright (c) 202... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/drivers/led.h>
#include <zephyr/drivers/mfd/npm13xx.h>
/* nPM13xx LED base address */
#define NPM_LED_BASE 0x0AU
/* nPM13xx LED register offsets *... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_SPEC_GET, (,)) \
}; \
\
static const struct led_pwm_config led_pwm_config_##id = { \
.num_leds = ARRAY_SIZE(led_pwm_##id), \
.led = led_pwm_##id, \
}; \
\
PM_DEVICE_DT_INST_DEFINE(id, led_pwm_pm_action); \
\
DEVICE_DT_INST_DEFINE(id, &led_pwm_init, \
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>r;
}
static int
cmd_write_channels(const struct shell *sh, size_t argc, char **argv)
{
const struct device *dev;
uint32_t start_channel;
int err;
size_t num_channels;
uint8_t i;
uint8_t value[MAX_CHANNEL_ARGS];
err = parse_common_args(sh, argv, &dev, &start_channel);
if (err < 0) {
return err;... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> const struct leds_group_multicolor_config *config = dev->config;
for (uint8_t i = 0; i < config->num_leds; i++) {
const struct led_dt_spec *led = &config->led[i];
if (!led_is_ready_dt(led)) {
LOG_ERR("%s: LED device %s is not ready", dev->name, led->dev->name);
return -ENODEV;
}
}
retur... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>D reg update failed");
return -EIO;
}
return 0;
}
static inline int lp3943_led_off(const struct device *dev, uint32_t led)
{
const struct lp3943_config *config = dev->config;
int ret;
uint8_t reg;
ret = lp3943_get_led_reg(&led, ®);
if (ret) {
return ret;
}
/* Set LED state to OFF */
i... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
PM_DEVICE_DT_INST_DEFINE(n, lp50xx_pm_action); \
\
DEVICE_DT_INST_DEFINE(n, \
lp50xx_init, \
PM_DEVICE_DT_INST_GET(n), \
&lp##id##_data_##n, \
&lp##id##_config_##n, \
POST_KERNEL, CONFIG_LED_INIT_PRIORITY, \
&lp50xx_l... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 Workaround GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ti_lp5562
/**
* @file
* @brief LP5562 LED driver
*
* The LP5562 is a 4-channel LED driver that communicates over I2C. The four
* channels are expected to be connected to a red, green, blue a... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
.bus = I2C_DT_SPEC_INST_GET(id), \
.enable_gpio = GPIO_DT_SPEC_INST_GET_OR(id, enable_gpios, {0}), \
.cp_mode = DT_ENUM_IDX(DT_DRV_INST(id), charge_pump_mode), \
}; ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>60, 11)
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT ti_lp5861
DT_INST_FOREACH_STATUS_OKAY_VARGS(LP586X_DEVICE, 5861, 1)
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT ti_lp5862
DT_INST_FOREACH_STATUS_OKAY_VARGS(LP586X_DEVICE, 5862, 2)
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT ti_lp5864
DT_INST_FOREACH_STAT... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2025 Google LLC
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT arduino_modulino_buttons_leds
#include <zephyr/device.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/led.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(mod... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 NXP Semiconductors
* Copyright (c) 2023 Cognipilot Foundation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT onnn_ncp5623
/**
* @file
* @brief NCP5623 LED driver
*
* The NCP5623 is a 3-channel LED driver that communicates over I2C.
*/
#include <zephyr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_PSC;
data->pwm_val[ch] = duty;
}
/* Bind LED to new engine and update hardware */
LOG_DBG("LED%u uses engine %u (duty %u)", led, ch, duty);
engine_release(data, led);
engine_bind(data, led, ch);
return ls_update(&config->i2c, led, ch ? LS_FUNC_PWM1 : LS_FUNC_PWM0);
}
static int pca9533_led_blin... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>eturn 0;
}
static int pca9633_led_init(const struct device *dev)
{
const struct pca9633_config *config = dev->config;
if (!device_is_ready(config->i2c.bus)) {
LOG_ERR("I2C bus is not ready");
return -ENODEV;
}
/*
* Take the LED driver out from Sleep mode and disable All Call Address
* if sp... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Hubert Miś
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT sct_sct2024
/**
* @file
* @brief LED driver for the SCT2024 LED driver
*/
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/led.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/logging/... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Sky Hero SA
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ti_tlc59108
/**
* @file
* @brief LED driver for the TLC59108 I2C LED driver
*/
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/led.h>
#include <zephy... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
&apa102_##idx##_config, \
POST_KERNEL, \
CONFIG_LED_STRIP_INIT_PRIORITY, \
&apa102_api);
DT_INST_FOREACH_STATUS_OKAY(APA102_DEVICE)
<|fim_prefix|>/*
* Copyright (c) 2018 Google LLC.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT a... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Dmitrii Sharshakov <d3dx12.xx@gmail.com>
*
* Based on drivers/led/led_shell.c which is:
* Copyright (c) 2020 Seagate Technology LLC
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdlib.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/minmax.h>
#include <zephyr/sys/... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ast byte of pixel data is displayed. */
.buf = &last,
.len = sizeof(last)
}
};
const struct spi_buf_set tx = {
.buffers = bufs,
.count = 3
};
size_t rc;
(void)memset(reset_buf, 0x00, reset_size);
rc = spi_write_dt(&config->bus, &tx);
if (rc) {
LOG_ERR("can't update strip: %zu", rc)... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2025 Google LLC
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT arduino_modulino_pixels
#include <zephyr/device.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/led_strip.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/byt... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2022 Esco Medical ApS
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ti_tlc5971
#include <zephyr/kernel.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/drivers/led_strip.h>
#include <zephyr/drivers/led_strip/tlc5971.h>
#include <zephyr/dt-bindings/led/led.h>
#include <zeph... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ddress
* for a single chip, and T_H1 to complete the write for all chips.
*/
#include <zephyr/drivers/led_strip.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(tlc59731, CONFIG_LED_STRIP_LOG_LEVEL);
/* Pulse... | fim | zephyrproject-rtos/zephyr | c |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.