text stringlengths 14 100k | source stringclasses 1
value | repo stringclasses 810
values | language stringclasses 13
values |
|---|---|---|---|
<|fim_suffix|>i = 0; i < tx_buf->len - 1; i++) {
if (!(regs->STATUS2 & MCHP_PECI_STS2_WFF)) {
regs->WR_DATA = tx_buf->buf[i];
}
}
}
/* Check bus is idle before starting a new transfer */
ret = check_bus_idle(regs);
if (ret) {
return ret;
}
regs->CONTROL |= MCHP_PECI_CTRL_TXEN;
k_busy_wait(PECI_IO... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nuvoton_npcx_peci
#include <errno.h>
#include <soc.h>
#include <zephyr/device.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/peci.h>
#include <zephyr/driver... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/pinctrl.h>
int pinctrl_lookup_state(const struct pinctrl_dev_config *config, uint8_t id,
const struct pinctr<|fim_suffix|>inctrl_state *states,
uint8_t state_cnt)
{
uint8_t ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uintptr_t reg)
{
ARG_UNUSED(reg);
const struct device *dev = pins->dev;
struct pinctrl_aesc_data *data = DEV_DATA(dev);
volatile struct pinctrl_aesc_regs *regs =
(volatile struct pinctrl_aesc_regs *)data->reg_base;
for (uint8_t i = 0; i <... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> (uint8_t i = 0; i < pin_cnt; i++) {
alif_pinctrl_configure_pin(&pins[i]);
}
return 0;
}
<|fim_prefix|>/*
* Copyright (c) 2025 Alif Semiconductor
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Alif pinctrl driver
*
* This driver provides pin control functionality for Alif So... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Antmicro <www.antmicro.com>
* Copyright (c) 2025 Linumiz GmbH
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/pinctrl.h>
/* ambiq-sdk includes */
#include <soc.h>
#if defined(CONFIG_SOC_SERIES_APOLLO2X)
static void pinctrl_configure_pin(const pinctrl_soc_p... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>SchmitCtrl(gpio_pin, DISABLE);
}
if (pin->swd_off) {
Pinmux_Swdoff();
}
return 0;
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
{
int ret;
ARG_UNUSED(reg);
for (int i = 0; i < pin_cnt; i++) {
ret = ameba_configure_pin(&pins[i]);
if (ret < 0)... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>NODELABEL(gpio1)),
DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpio2)),
DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpio3)),
};
static int pinctrl_configure_pin(const pinctrl_soc_pin_t *pin)
{
uint32_t flags = pin->input_enable ? GPIO_INPUT : GPIO_OUTPUT;
/* Each gpio has 16 pins, so divide by 16 to get specific gpio... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>/gpio_cmsdk_ahb.h>
static const struct device *const gpio_ports[] = {DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpio0)),
DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpio1)),
DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpio2))};
static int pinctrl_configure_pin(const pinctrl_soc_pin_t *pin)
{
uint32_t flags = pin... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "zephyr/device.h"
#include "zephyr/drivers/gpio.h"
#include <zephyr/dri<|fim_suffix|>lags);
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_c... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "zephyr/device.h"
#include "zephyr/drivers/gpio.h"
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/devicetree/gpio.h>
#include <zephyr/drivers/gpio/gpio_cmsdk_ah... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>0-3]
* pin_mux + 3: PORT_B[4-7]
* pin_mux + 4: PORT_C[0-3]
* pin_mux + 5: PORT_C[4-7]
* pin_mux + 6: PORT_D[0-3]
* pin_mux + 7: PORT_D[4-7]
* pin_mux + 0x20: PORT_E[0-3]
* pin_mux + 0x21: PORT_E[4-7]
* pin_mux + 0x26: PORT_F[0-... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> return -EINVAL;
}
bcm2711_pinctrl_set_func(base, pin, pins[i].func);
bcm2711_pinctrl_set_pull(base, pin, pins[i].pull);
}
return 0;
}
<|fim_prefix|>/*
* Copyright (c) 2025 Muhammad Waleed Badar
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT brcm_bcm2711_pinctrl
#include... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026, Realtek Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/pinctrl.h>
#if defined(CONFIG_SOC_SERIES_RTL87X2G)
#include <rtl_pinmu<|fim_suffix|>ENABLE : PAD_OUT_DISABLE;
uint8_t cfg_drv = pin[0].drive ? PAD_OUT_HIGH : PAD_OUT_LOW;
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021-2025 Gerson Fernando Budke <nandojve@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/dt-bindings/pinctrl/bflb-common-pinctrl.h>
#if defined(CONFIG_SOC_SERIES_BL60X)
#include <zephyr/dt-bind... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025-2026 MASSDRIVER EI (massdriver.space)
<|fim_suffix|>UNC_KEY_SCAN_IN 21
#define GLB_GPIO_FUNC_KEY_SCAN_DRV 22
#define BFLB_CLK_OUT_SEL_MSK 0x3
void pinctrl_bflb_configure_uart(uint8_t pin, uint8_t func)
{
uint32_t regval;
uint8_t sig;
uint8_t sig_pos;
regval = sys_read32(GL... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
<|fim_suffix|>UX_GET_FUN(pin);
mode = BFLB_PINMUX_GET_MODE(pin);
drive = BFLB_PINMUX_GET_DRIVER_STRENGTH(pin);
/* gpio pad check goes here */
/* disable RC32K muxing */
if (real_pin == 16) {
*(volatile uint32_t *)(HBN_BASE + HBN_PAD_CTRL_0... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Vaishnav Achath
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ti_cc13x<|fim_suffix|>nt32_t func, uint32_t mode)
{
if (pin >= NUM_IO_MAX || func >= NUM_IO_PORTS) {
return -EINVAL;
}
IOCPortConfigureSet(pin, func, mode);
return 0;
}
int pinctrl_config... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Texas Instruments Incorporated
* Copyright (c) 2024 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ti_cc23x0_pinctrl
#include <zephyr/driv<|fim_suffix|>32_t) * (index)))
static int pinctrl_cc23x0_set(uint32_t pin, uint32_t func, uint32_t mode... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>L0_OFFSET)
#define ARDUINO_CFG0_UART ((1) << MUX_SEL0_OFFSET) /* io_uart0 */
#define ARDUINO_CFG1_GPIO ((0) << MUX_SEL1_OFFSET)
#define ARDUINO_CFG1_PWM ((1) << MUX_SEL1_OFFSET)
#define ARDUINO_CFG2_GPIO ((0) << MUX_SEL2_OFFSET)
#define ARDUINO_CFG2_PWM ((1) << MUX_SEL2_OFFSET)
#define ARDUINO_CFG3_G... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>.h>
#include <zephyr/sys/util.h>
#include <reg/gcfg.h>
#include <reg/gpio.h>
/*
* PINMUX_FUNC_A : GPIO Function
* PINMUX_FUNC_B : AltOutput 1 Function
* PINMUX_FUNC_C : AltOutput 2 Function
* PINMUX_FUNC_D : AltOutput 3 Function
* PINMUX_FUNC_E : AltOutput 4 Function
*
* GPIO Alternat... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>1200_PINMUX_PIN(p) FIELD_GET(GENMASK(4, 0), p)
#define ENE_KB1200_PINMUX_PORT(p) FIELD_GET(GENMASK(7, 5), p)
#define ENE_KB1200_PINMUX_FUNC(p) FIELD_GET(GENMASK(11, 8), p)
#define ENE_KB1200_PINMUX_PORT_PIN(p) FIELD_GET(GENMASK(7, 0), p)
static const uint32_t gcfg_reg_addr = DT_REG_ADDR(... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>("Selected drive-strength is not supported: %d\n", pin->drive_strength);
}
/* Enable pull-up by default; overwrite if any setting was chosen. */
WRITE_BIT(reg_value, PAD_PULL_UP_BIT, 1);
WRITE_BIT(reg_value, PAD_PULL_DOWN_BIT, 0);
if (pin->high_impedance) {
WRITE_BIT(reg_value, PAD_PULL_UP_BIT, 0)... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>in_is_output_capable(uint32_t pin)
{
return ((BIT64(pin) & SOC_GPIO_VALID_OUTPUT_GPIO_MASK) != 0);
}
static int esp32_pin_apply_config(uint32_t pin, uint32_t flags)
{
gpio_dev_t *const gpio_base = (gpio_dev_t *)DT_REG_ADDR(DT_NODELABEL(gpio0));
uint32_t io_pin = (uint32_t) pin + ((ESP32_PORT_IDX(pin) ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/gd32.h>
#include <zephyr/drivers/pinctrl.h>
#include <gd32_gpio.h>
BUILD_ASSERT((GD32_PUPD_NONE == GPIO_PUPD_NONE) &&
(G... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/init.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/gd32.h>
#include <zephyr/drivers/pinctrl.h>
#include <gd32_gpio.h>
/** AFIO DT node */
#define AFIO_N... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Silicon Labs
* Copyright (c) 2024 Capgemini
*
* SPDX-License-Identifier: Apache<|fim_suffix|> << _USART_ROUTELOC0_RXLOC_SHIFT);
break;
case GECKO_FUN_SPI_CS_LOC:
base->ROUTEPEN |= USART_ROUTEPEN_CSPEN;
base->ROUTELOC0 &= ~_USART_ROUTELOC0_CSLOC_MASK;
base->ROUTEL... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2022, 2024-2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/arch/cpu.h>
#include <zephyr/init.h>
#include <zephyr/drivers/pinctrl.h>
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uintptr_t reg)
{
/* configure all pins */
for (ui... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>t < 0) {
return ret;
}
}
return 0;
}
<|fim_prefix|>/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/firmware/scmi/pinctrl.h>
static int scmi_pinctrl_configure_pin(const pinctrl_soc_pin_t *pin)
{
struct scmi_pinctr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2023 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/pinctrl.h>
#include <svc/pad/pad_api.h>
#include <main/ipc.h>
int pinctrl_configure_pins<|fim_suffix|>on (no OD)
* 2) ISO off
* 3) Pull select and drive strength initialized by another
* entity (e.g:... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>PORT_ENTRIES
};
/* @brief This function returns gpio drive mode, according to.
* bias and drive mode params defined in pinctrl node.
*
* @param flags - bias and drive mode flags from pinctrl node.
*/
static uint32_t soc_gpio_get_drv_mode(uint32_t flags)
{
uint32_t drv_mode = CY_GPIO_DM_ANALOG;
uint... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 ITE Corporation. All Rights Reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ite_it8xxx2_pinctrl_func
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h>
#include <chip_chipregs.h>
LOG_MODULE_REGISTE... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2022,2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/device.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/reset.h>
#include <zephyr/init.h>
#include <zephyr/sys/util.h>
#if !defined(CONFIG_SOC_SERIE<|fim_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ET_PORT_ADDR_OR_NONE(gpio3)
ADI_MAX32_GET_PORT_ADDR_OR_NONE(gpio4)
ADI_MAX32_GET_PORT_ADDR_OR_NONE(gpio5)
};
static int pinctrl_configure_pin(pinctrl_soc_pin_t soc_pin)
{
uint32_t port;
uint32_t pin;
uint32_t afx;
int pincfg;
mxc_gpio_cfg_t gpio_cfg;
port = MAX32_PINMUX_PORT(soc_pin.pinmux);
pi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>G[pin_num] & ~PORT_PINCFG_SLEWLIM_Msk) |
PORT_PINCFG_SLEWLIM(slewrate_val);
#endif /* CONFIG_PIN_SLEW_RATE */
#ifdef CONFIG_PIN_DRIVE_STRENGTH
/* if drive strength is enabled, set the corresponding bit in PORT_PINCFG reg */
if ((pin->pinflag & MCHP_PINCTRL_DRIVESTRENGTH) != 0) {
pRegister->PORT... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> MEC_GPIO_CR1_DIR_SET(MEC_GPIO_CR1_DIR_OUT);
}
/* Touch output state? Bit can be set even if the direction is input only */
if (p->out_lo != 0) {
pcr1 &= ~(MEC_GPIO_CR1_ODAT_MSK);
pcr1 |= MEC_GPIO_CR1_ODAT_SET(MEC_GPIO_CR1_ODAT_LO);
}
if (p->out_hi != 0) {
pcr1 &= ~(MEC_GPIO_CR1_ODAT_MSK);
... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2022, 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/pinctrl.h>
#include <soc.h>
#define NO_FORCE_OUTPUT 2
static MCI_IO_MUX_Type *mci_iomux =
(MCI_IO_MUX_Type *)DT_REG_ADDR(DT_NODELABEL(pinctrl));
static SOCCIU_Type *soc_ctrl =
(SOCCIU_Type *)DT_REG_ADDR(DT_NODELA... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>) {
LOG_ERR("Pin CM%d: Cannot enable both pull-up and pull-down "
"simultaneously", pin_cm);
return -EINVAL;
}
if (pin_function == 0x00) {
DL_GPIO_initPeripheralAnalogFunction(pin_cm);
} else {
DL_GPIO_initPeripheralFunction(pin_cm,
(iomux | pin_function));
}
}
ret... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>tionality */
npcx_periph_configure(&pins[i], reg);
} else if (pins[i].flags.type == NPCX_PINCTRL_TYPE_DEVICE_CTRL) {
/* Configure device's io characteristics */
npcx_device_control_configure(&pins[i]);
} else if (pins[i].flags.type == NPCX_PINCTRL_TYPE_PSL_IN) {
/* Configure SPL input's de... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>if /* defined(NRF_PSEL_TWIM) */
#if defined(NRF_PSEL_I2S)
case NRF_FUN_I2S_SCK_M:
NRF_PSEL_I2S(reg, SCK) = psel;
write = 0U;
dir = NRF_GPIO_PIN_DIR_OUTPUT;
input = NRF_GPIO_PIN_INPUT_DISCONNECT;
break;
case NRF_FUN_I2S_SCK_S:
NRF_PSEL_I2S(reg, SCK) = psel;
dir = NRF_GPIO_PIN_DIR_I... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nuvoton_numaker_pinctrl
#include <zephyr/drivers/pinctrl.h>
#include <NuMicro.h>
/* Get mfp_base, it should be == (&SYS->GPA_MFP0) */
#define MFP_BASE DT_INST_REG_ADDR_BY_NAME... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 SEAL AG
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nuvoton_numicro_pinctrl
#include <stdint.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/dt-bindings/pinctrl/numicro-pinctrl.h>
#include <NuMicro.h>
<|fim_suffix|> ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ig, \
PRE_KERNEL_1, \
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
NULL);
DT_INST_FOREACH_STATUS_OKAY(PINCTRL_MCUX_INIT)
<|fim_prefix|>/*
* Copyright 2022-2026 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_port_pinmux
#include <zephyr/drivers/clock_co<... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2022, 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/drivers/pinctrl.h>
/* SIUL2 Multiplexed Signal Configuration Register */
#define SIUL2_MSCR(n) (0x240 + 0x4 * (n))
/* SIUL2 Input Multiplexed Signal Configuration Register */
#define SIUL2_IMCR(n) ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7
* Author: Lin Yu-Cheng <lin_yu_cheng@realtek.com>
*/
#define DT_DRV_COMPAT realtek_rts5<|fim_suffix|>reg_gpio.h>
#define REALTEK_RTS5912_PINMUX_GET_GPIO_PIN(n) ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>gure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uintptr_t reg)
{
ARG_UNUSED(reg);
for (uint8_t i = 0U; i < pin_cnt; i++) {
pinctrl_configure_pin(pins++);
}
return 0;
}
<|fim_prefix|>/*
* Copyright (c) 2021 Yonatan Schachter
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Realtek Semiconductor, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/dt-bindings/pinctrl/rts5817_pinctrl.h>
#include "pinctrl_rts5817<|fim_suffix|>
base = DT_REG_ADDR_BY_IDX(DT_NODELABEL(pinctr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>)
#define GPIO_SVIO_H3L1_OFFSET 5
#define GPIO_SVIO_H3L1_MASK BIT(5)
#define GPIO_SVIO_IEV18_OFFSET 6
#define GPIO_SVIO_IEV18_MASK BIT(6)
#define GPIO_SVIO_PULLCTL_OFFSET 8
#define GPIO_SVIO_PULLCTL_MASK GENMASK(9, 8)
#define GPIO_SVIO_INT_EN_RISE_OFFSET 10
#define GPIO_SVIO_INT_EN_RISE_MASK B... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Henrik Brix Andersen <henrik@brixandersen.dk>
* Copyright (c) 2022 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT openisa_rv32m1_pinmux
#include <zephyr/drivers/pinctrl.h>
#include <fsl_clock.h>
#include <soc.h>
/* Port register addresses. */
static P... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>rl_soc_pin_t *pins, uint8_t pin_cnt,
uintptr_t reg)
{
ARG_UNUSED(reg);
for (uint8_t i = 0U; i < pin_cnt; i++) {
pinctrl_configure_pin(*pins++);
}
return 0;
}
<|fim_prefix|>/*
* Copyright (c) 2022-2023, Gerson Fernando Budke <nandojve@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2022, Gerson Fernando Budke <nandojve@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/pinctrl.h>
#include <soc_port.h>
/** Utility macro that expands to the PORT port address if it exists */
#define SAM_PORT_ADDR_OR_NONE(nodelabel) \
IF_ENABLED(DT_NODE_EXISTS... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries
*
* SPDX-License-Identifier: Apache-2.0
*
*/
#include <zephyr/drivers/pinctrl.h>
#include <soc.h>
#define SAM_PIO_NPINS_PER_BANK 32
#define SAM_PIO_BANK(pin_id) (pin_id / SAM_PIO_NPINS_PER_BANK)
#define SAM_PIO_LINE(pin_id... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Core Devices LLC
* Copyright (c) 2025 SiFli Technologies(Nanjing) Co., Ltd
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT sifli_sf32lb52x_pinmux
#include <zephyr/arch/cpu.h>
#include <zephyr/devicetree.h>
#include <zephyr/dt-bindings/pinctrl/sf32lb52x-pinctrl.... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>in_cnt; i++) {
pinctrl_sifive_set(pins[i].pin, pins[i].iof);
}
return 0;
}
<|fim_prefix|>/*
* Copyright (c) 2022 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT sifive_pinctrl
#include <zephyr/arch/cpu.h>
#include <zephyr/devicetree.h>
#include <zeph... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> 0;
}
<|fim_prefix|>/*
* Copyright (c) 2024 Silicon Laboratories Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/arch/cpu.h>
#include <em_gpio.h>
#define DT_DRV_COMPAT silabs_dbus_pinctrl
#define PIN_MASK 0xF0000UL
#define ABUS_MASK(i) GENM... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2023 Antmicro
* Copyright (c) 2024 Silicon Laboratories Inc.
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT silabs_siwx91x_pinctrl
#include <zephyr/drivers/pinctrl.h>
#include "sl_si91x_peripheral_gpio.h"
#define MODE_COUNT 16
#define HP_PERIPHERAL_ON_ULP_PIN 6
#d... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2016 Open-RnD Sp. z o.o.
* Copyright (c) 2021 Linaro Limited
* Copyright (c) 2021 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/init.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/drivers/pinctrl.h>
#includ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_io.h>
static uint32_t pinctrl0_base_addr = DT_REG_ADDR(DT_NODELABEL(pinctrl));
static uint32_t pinctrl0_base_mask = DT_REG_SIZE(DT_NODELABEL(pinctrl)) - 1;
/**
* @brief Configure a pin.
*
* @param pin The pin to configure.
*/
static int pinctrl_configure_pin(const pinctrl_soc_pin_t *pin)
{
uint32_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>bit = SRXXX_PINMUX_BIT(soc_pin.pinmux);
mode = SRXXX_PINMUX_MODE(soc_pin.pinmux);
value = sys_read32(ctrl->mux + reg);
value = (value & ~(mask << bit)) | (mode << bit);
sys_write32(value, ctrl->mux + reg);
}
if (soc_pin.port != 0) {
reg = SRXXX_PINMUX_REG(soc_pin.port);
bit = SRXXX_PINMUX_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>NFIG_MSK, DT_INST_REG_ADDR(0) + (pin2pad[pin] << 2U));
return 0;
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
{
ARG_UNUSED(reg);
for (uint8_t i = 0U; i < pin_cnt; i++) {
int ret;
ret = pinctrl_configure_pin(pins[i]);
if (ret < 0) {
return ret;... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Enphase Energy
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ti_k3_pinctrl
#include <zephyr/arch/cpu.h>
#include <zephyr/drivers/pinctrl.h>
struct pinctrl_ti_k3_data {
DEVICE_MMIO_RAM;
};
struct pinctrl_ti_k3_cfg {
DEVICE_MMIO_ROM;
};
int pinctrl_confi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Michael Hope <michaelh@juju.nz>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT wch_00x_afio
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/dt-bindings/pinctrl/ch32v00x-pinctrl.h>
#include <hal_ch32fun.h>
stat... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 MASSDRIVER EI (massdriver.space)
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT wch_20x_30x_afio
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/dt-bindings/pinctrl/ch32v20x_30x-pinctrl.h>
#include <hal_ch32fun... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2024 Michael Hope
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT wch_afio
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/dt-bindings/pinctrl/ch32v003-pinctrl.h>
#include <hal_ch32fun.h>
static GPIO_TypeDef *const wch_afio_pinct... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
val |= pins[i].val;
LOG_DBG("0x%04x w: 0x%08x", addr, val);
err = syscon_write_reg(slcr, addr, val);
if (err != 0) {
LOG_ERR("failed to write SLCR addr 0x%04x (err %d)", addr, err);
break;
}
}
k_sem_give(&pinctrl_lock);
return err;
}
<|fim_prefix|>/*
* Copyright (c) 2022 Henrik Br... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_t *pins, uint8_t pin_cnt, uintptr_t reg)
{
for (uint8_t i = 0U; i < pin_cnt; i++) {
uint32_t sel = 0;
switch (pins[i].func) {
case UART_FUNCTION: {
sel = UARTX_SEL;
break;
}
default: {
LOG_ERR("Unsupported function enum was selected");
break;
}
}
sys_write32(sel, ba... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Schlumberger
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT infineon_xmc4xxx_pinctrl
#include <zephyr/devicetree.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/dt-bindings/pinctrl/xmc4xxx-pinctrl.h>
#include <xmc_gpio.h>
#define GPIO_REG_SIZE 0x10... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/pinctrl.h>
#include <soc.h>
#define PORT_POS (8)
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
{
bsp_io_port_pin_t port_pin;
R_B... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021-2023 IoT.bzh
*
* SPDX-License-Identifier: Apache-2.0
*
*/
#include <pinctrl_soc.h>
#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a77951.h>
const struct pfc_drive_reg pfc_drive_regs[] = {
/* DRVCTRL0 */
{ 0x0300, {
{ PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>, 28, 3 }, /* USB0_OVC */
{ RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
{ RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
{ RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
{ RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
{ RCAR_GP_PIN(6, 30), 8, 3 }, ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> RCAR_GP_PIN(7, 23), /* CAN11RX/INTP11 */
[24] = RCAR_GP_PIN(7, 24), /* CAN12TX */
[25] = RCAR_GP_PIN(7, 25), /* CAN12RX/INTP12 */
[26] = RCAR_GP_PIN(7, 26), /* CAN13TX */
[27] = RCAR_GP_PIN(7, 27), /* CAN13RX/INTP13 */
[28] = RCAR_GP_PIN(7, 28), /* CAN14TX */
[29] = RCAR_GP_PIN(7, 29), /* CAN... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> */
{RCAR_GP_PIN(6, 16), 0, 3}, /* AVB1_TD2 */
}},
/* DRV0CTRL7 */
{ 0x80, {
{RCAR_GP_PIN(7, 7), 28, 3}, /* AVB0_TD1 */
{RCAR_GP_PIN(7, 6), 24, 3}, /* AVB0_TD2 */
{RCAR_GP_PIN(7, 5), 20, 3}, /* AVB0_PHY_INT */
{RCAR_GP_PIN(7, 4), 16, 3}, /* AVB0_LINK */
{RCAR_GP_PIN(7, 3), 12, 3}, /* AVB0_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*
*/
#include <pinctrl_soc.h>
#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a78000.h>
#define PFC_DRIVE_REG(r1, r2, r3) \
.drvctrl0 = r1, \
.drvctrl1 = r2, \
.drvctrl2 = r3, \
.p... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>c_base + bias_reg->puen);
if ((flags & RCAR_PIN_FLAGS_PUEN) == 0U) {
sys_write32(val & ~BIT(bit), pfc_base + bias_reg->puen);
return 0;
}
sys_write32(val | BIT(bit), pfc_base + bias_reg->puen);
/* pull - up/down */
val = sys_read32(pfc_base + bias_reg->pud);
if (flags & RCAR_PIN_FLAGS_PUD) {
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>eg_index(uint16_t pin, uint8_t *reg_index);
#endif /* ZEPHYR_DRIVERS_PINCTRL_PFC_RCAR_H_ */
<|fim_prefix|>/*
* Copyright (c) 2023 IoT.bzh
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_PINCTRL_PFC_RCAR_H_
#define ZEPHYR<|fim_middle|>_DRIVERS_PINCTRL_PFC_RCAR_H_
#include <stdint.h... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>gure_pin(&pins[i]);
if (ret < 0) {
return ret;
}
}
return 0;
}
<|fim_prefix|>/*
* Copyright (c) 2026 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*
*/
#define DT_DRV_COMPAT renesas_rcar_pfc_x5h
#include "pfc_rcar.h"
#include <zephyr/arch/cpu.h>
#include <zephyr/devicetree.h>
#inc... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ntrol(
port_pin, (value ? GPIO_CMD_OUT_OPEN_DRAIN_N_CHAN : GPIO_CMD_OUT_CMOS));
}
return ret;
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
{
gpio_port_pin_t port_pin;
mpc_config_t pconfig = {
.pin_function = 0x0,
.irq_enable = false,
.analog_en... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Renesas Electronics Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/pinctrl.h>
#include "r_ioport.h"
static void pinctrl_configure_pin(const pinctrl_soc_p<|fim_suffix|>, uint8_t pin_cnt, uintptr_t reg)
{
ARG_UNUSED(reg);
for (uint8_t i = 0U; i ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>utex_lock(&rza2m_pinctrl_data.lock, K_FOREVER);
switch (pin.pin) {
case PIN_POSEL:
ppoc_val = ((pin.func & 0x1) << RZA2M_PPOC_POC0_SHIFT) |
(((pin.func & 0x2) >> 1) << RZA2M_PPOC_POCSEL0_SHIFT);
/* Set POC0 and POCSEL0 */
reg_32 = sys_read32(RZA2M_PPOC);
reg_32 &= ~(RZA2M_PPOC_POC0 & RZA... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT renesas_rzt2m_pinctrl
#include <zephyr/arch/cpu.h>
#i<|fim_suffix|>)
/* Port m region select register */
#define RSELP(port) (PTADR + port)
#define DRCTL_DRIVE_STRENGTH(val) (va... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>id pinctrl_configure_pin(const pinctrl_soc_pin_t *pin)
{
volatile uint32_t *reg;
uint32_t reg_val;
__ASSERT_NO_MSG(pin->port < ARRAY_SIZE(smartbond_gpio_ports));
__ASSERT_NO_MSG(pin->pin < smartbond_gpio_ports[pin->port].pin_count);
reg = (volatile uint32_t *)smartbond_gpio_ports[pin->port].p0_mode... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 BayLibre SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT arm_fvp_pwrc
#define LOG_LEVEL CONFIG_PM_CPU_OPS_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(fvp_pm_cpu_ops);
#include <zephyr/kernel.h>
#include <zephyr/drivers/pm_cpu_ops.h>
#in... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>fn_smc(unsigned long function_id,
unsigned long arg0,
unsigned long arg1,
unsigned long arg2)
{
struct arm_smccc_res res;
arm_smccc_smc(function_id, arg0, arg1, arg2, 0, 0, 0, 0, &res);
return res.a0;
}
static uint32_t psci_get_version(void)
{
return psci_data.invoke_psci_fn(PSC... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2020 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_PSCI_PSCI_H_
#define ZEPHYR_DRIVERS_PSCI_PSCI_H_
#include <zephyr/drivers/pm_cpu_ops/psci.h>
#ifdef CONFIG_64BIT
#define PSCI_FN_NATIVE(version, name) PSCI_##version##_FN64_##na... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>.h>
int __weak pm_cpu_on(unsigned long cpuid, uintptr_t entry_point)
{
return -ENOTSUP;
}
int __weak pm_cpu_off(void)
{
return -ENOTSUP;
}
<|fim_prefix|>/*
* Copyright (c) 2021 Carlo Caione <ccaione@baylibre.com>
*
* SP<|fim_middle|>DX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel<|en... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>esult = pm_cpu_on((unsigned long)cpu_id, (uintptr_t)&__start);
return result;
}
SHELL_STATIC_SUBCMD_SET_CREATE(
sub_reboot,
SHELL_CMD_ARG(warm, NULL,
SHELL_HELP("System warm reset", NULL),
cmd_reboot_warm, 1, 0),
SHELL_CMD_ARG(cold, NULL,
SHELL_HELP("System cold reset", NULL)... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2026 NXP
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT arm_scmi_power_domain
#include <zephyr/kernel.h>
#include <zephyr/pm/device.h>
#include <zephyr/pm/device_runtime.h>
#include <zephyr/drivers/firmware/scmi/power.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGI... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022, Commonwealth Scientific and Industrial Research
* Organisation (CSIRO) ABN 41 687 119 230.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT power_domain_gpio
#include <zephyr/kernel.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/pm/device.h>
#include <... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ak;
}
return 0;
}
#ifdef CONFIG_POWER_DOMAIN_GPIO_MONITOR_INITIAL_READ
static int pd_gpio_monitor_initial_read(void)
{
/* For each power-domain-gpio-monitor device */
ARRAY_FOR_EACH(domain_devs, i) {
if (!device_is_ready(domain_devs[i])) {
continue;
}
/* read GPIO and handle state */
pd_u... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/pm/device.h>
#include <zephyr/pm/device_runtime.h>
#include <adsp_shim.h>
#include <adsp_power.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(power_domain_intel_a... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>e), \
&DOMAIN_NODE_SYMNAME(node, data), \
&DOMAIN_NODE_SYMNAME(node, config), \
PRE_KERNEL_1, \
0, \
NULL \
);
DT_INST_FOREACH_CHILD(0, DOMAIN_DEFINE)
<|fim_prefix|>/*
* Copyright (c) 2025 Nordic Semicon<|fim_middle|>ductor ASA
*
* SPDX-License-Ide... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nordic_nrfs_swext
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/pm/device.h>
#include <zephyr/logging/log.h>
#include <nrfs_swext.h>
#include <nrfs_backend_ipc_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/pm/device_runtime.h>
#include <zephyr/pm/device.h>
#include <zephyr/logging/log.h>
#include <main/ipc.h>
#include <svc/pm/pm_api.h>
#include <zephyr/dt-bindings/power/imx_scu_rsrc.h>
LOG_MODULE_REGISTER(nxp_scu_pd);
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Silicon Laboratories Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/pm/device.h>
#include <zephyr/pm/policy.h>
#define DT_DRV_COMPAT silabs_siwx91x_power_<|fim_suffix|>IT)
<|fim_middle|>domain
static int siwx91x_pd_pm_action(const struct device *dev, enum p... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2024-25 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/pm/device.h>
#include <zephyr/pm/device_runtime.h>
#include <zephyr/pm/pm.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(power_domain_soc_state_change, CONFIG_POWER_DOMAIN_LOG_LEV... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
PM_DEVICE_DT_INST_DEFINE(inst, tisci_pd_pm_action); \
DEVICE_DT_INST_DEFINE(inst, tisci_pd_init, PM_DEVICE_DT_INST_GET(inst), NULL, \
&power_domain_data_##inst, PRE_KERNEL_1, ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>, disable_callback));
return z_impl_ps2_disable_callback(dev);
}
#include <zephyr/syscalls/ps2_disable_callback_mrsh.c>
<|fim_prefix|>/*
* Copyright (c) 2019 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/ps2.h>
#include <zephyr/internal/syscall_handler.h>
sta... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>DATA_REG));
} else {
LOG_INF("isr: %s: rx 0x%x", dev->name,
sys_read8(cfg->base + ITE_PS20C_DATA_REG));
}
}
}
out:
if (xfer_is_tx) {
k_sem_give(&data->tx_sem);
} else {
it51xxx_ps2_inhibit_bus(dev, false);
}
}
#ifdef CONFIG_PM_DEVICE
static inline int it51xxx_ps2_pm_action(const... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>;
k_sem_init(&data->tx_lock, 0, 1);
cfg->irq_config_func();
return 0;
}
/* To enable wakeup on the PS2, the DTS needs to have two entries defined
* in the corresponding PS2 node in the DTS specifying it as a wake source
* and specifying the PS2DAT GPIO; example as below
*
* wakerx-gpios = <MCHP... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> device not ready", config->ps2_ctrl->name);
return -ENODEV;
}
/* Configure pin-mux for PS/2 device */
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
LOG_ERR("PS2 pinctrl setup failed (%d)", ret);
return ret;
}
return 0;
}
static DEVICE_API(ps2, ps2_channel_n... | fim | zephyrproject-rtos/zephyr | c |
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