text stringlengths 14 100k | source stringclasses 1
value | repo stringclasses 810
values | language stringclasses 13
values |
|---|---|---|---|
/*
* Copyright (c) 2021 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nuvoton_npcx_ps2_ctrl
/**
* @file
* @brief Nuvoton NPCX PS/2 module (controller) driver
*
* This file contains the driver of PS/2 module (controller) which provides a
* hardware accelerato... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2021 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_PS2_PS2_NPCX_CONTROLLER_H_
#define ZEPHYR_DRIVERS_PS2_PS2_NPCX_CONTROLLER_H_
#include <zephyr/device.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Write @p value to a PS/2 device v... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_s32_psi5
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(nxp_s32_psi5, CONFIG_PSI5_LOG_LEVEL);
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/psi5... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>me)) != 0) {
return 0;
}
return ret;
}
#include <zephyr/syscalls/ptp_clock_get_mrsh.c>
#endif /* CONFIG_USERSPACE */
<|fim_prefix|>/*
* Copyright (c) 2019 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/internal/syscall_handler.h>
#include <zephyr/drivers/ptp_clock... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 Intel Corporation
* Copyright (c) 2026 The Zephyr Project Contributors
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT zephyr_native_ptp_clock
#include <zephyr/drivers/ptp_clock.h>
<|fim_suffix|>m_mid(-ret);
}
return 0;
}
static int ptp_clock_adjust_nati... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 Intel Corporation
* Copyright (c) 2026 The Zephyr Project Contributors
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include <time.h>
#include <errno.h>
#include "nsi_errno.h"
#include "ptp_clock_native_bottom.h"
int ptp_clock_native_gettime(uint64_t *seco... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2018 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_PTP_CLOCK_PTP_CLOCK_NATIVE_BOTTOM_H_
#define ZEPHYR_DRIVERS_PTP_CLOCK_PTP_CLOCK_NATIVE_BOTTOM_H_
#include <stdint.h>
int ptp_clock_native_gettime(uint64_t *second, uint32_t *nanosecond);
#endif /* ZEPHYR_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>##_data, \
&ptp_clock_nxp_enet_##n##_config, \
POST_KERNEL, CONFIG_PTP_CLOCK_INIT_PRIORITY, \
&ptp_clock_nxp_enet_api);
DT_INST_FOREACH_STATUS_OKAY(PTP_CLOCK_NXP_ENET_INIT)
<|fim_prefix|>/*
* Copyright 2023-2024 NXP
*
* Based on a commit to drivers/ethernet/eth_mcux.c which was:
* Copy... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>dend;
data->base->MAC_TIMESTAMP_CONTROL |= ENET_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK;
while (data->base->MAC_TIMESTAMP_CONTROL & ENET_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK) {
}
return 0;
}
static DEVICE_API(ptp_clock, ptp_clock_nxp_enet_qos_api) = {
.set = ptp_clock_nxp_enet_qos_set,
.get = ptp_clock... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_netc_p<|fim_suffix|> 0;
}
static int ptp_clock_nxp_netc_init(const struct device *dev)
{
const struct ptp_clock_nxp_netc_config *config = dev->config;
struct ptp_clock_nxp_netc_data *data = dev->data;
net... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ck_rate_adjust(dev, 1.0 + ((double)freq / 1000000000.0));
if (ret < 0) {
shell_print(sh, "failed to adjust rate");
return ret;
}
shell_print(sh, "test2: adjust frequency %d ppb (ratio %f), delay %d seconds...",
freq, 1.0 + ((double)freq / 1000000000.0), delay);
k_sleep(K_SECONDS(delay));
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Ambiq
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ambiq_ctimer_pwm
#include <errno.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control.h>
#include <am_mcu_apollo.h>
#include <zephyr/logging/log.h>... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Ambiq
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ambiq_timer_pwm
#include <errno.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control.h>
#include <am_mcu_apollo.h>
#include <zephyr/logging/log.h>
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Telink Semiconductor
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT telink_b91_pwm
#include <pwm.h>
#include <clock.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/drivers/pinctrl.h>
struct pwm_b91_config {
const struct pinctrl_dev_config *pcfg;
uint3... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
.clock_div = CONCAT(TIM_CLOCK_DIVIDER_, DT_PROP(PWM_BEE_PARENT_NODE(index), prescaler))
#endif
#define PWM_BEE_INIT(index) \
static struct pwm_bee_data pwm_bee_data_##index; ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>32(cfg->base + PWM0_CONFIG_OFFSET + ch * PWM_CH_OFFSET_MUL);
} while (tmp & PWM_STS_TOP && !sys_timepoint_expired(end_timeout));
if (sys_timepoint_expired(end_timeout)) {
return -ETIMEDOUT;
}
data->period_cycles[ch] = period_cycles;
}
return 0;
}
static DEVICE_API(pwm, pwm_bflb_driver_api) =... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
*
* SPDX-Li<|fim_suffix|>data;
k_timepoint_t end_timeout =
sys_timepoint_calc(K_MSEC(PWM_WAIT_TIMEOUT_MS));
volatile uint32_t tmp;
uint32_t pulse, divider;
uint16_t period;
if (ch >= CHANNELS) {
return -EINVAL;
}
divider = period_cyc... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: Copyright (c) 2026 Siemens
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT zephyr_pwm_bitbang
#include <zephyr/device.h>
#include <zephyr/drivers/counter.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/logging/log.h>
#in... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2020-2021 Vestas Wind Systems A/S
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_capture, CONFIG_PWM_LOG_LEVEL);
struct z_pwm_capture_cb_data {
uint32_t period;
uint32_t pulse;
st... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Zephyr Project
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ti_cc13xx_cc26xx_timer_pwm
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/pwm.h>
#include <driverlib/gpio.h>
#include <driverlib/prcm.h>
#include <dr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>BASE, lgpt_clk_id);
}
return 0;
}
#ifdef CONFIG_PM_DEVICE
static int pwm_cc23x0_pm_action(const struct device *dev, enum pm_device_action action)
{
switch (action) {
case PM_DEVICE_ACTION_SUSPEND:
pwm_cc23x0_clock_action(dev, false);
return 0;
case PM_DEVICE_ACTION_RESUME:
pwm_cc23x0_clock_a... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>RL_DT_INST_DEV_CONFIG_GET(inst), \
}; \
static struct pwm_kb106x_data pwm_kb106x_data_##inst; \
DEVICE_DT_INST_DEFINE(inst, &pwm_kb106x_init,... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>)DT_INST_REG_ADDR(inst), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
}; \
static struct pwm_kb1200_data pwm_kb1200_data_##inst; ... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2024 Kickmaker
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/drivers/pwm/pwm_fake.h>
#include <zephyr/fff.h>
#include <zephyr/sys/util.h>
#ifdef CONFIG_ZTEST
#include <zephyr/ztest.h>
#endif /* CONFIG_ZTEST */
#define DT_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT gd_gd32_pwm
#include <errno.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/gd32.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/drivers/pinctrl.... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Sun Amar.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT silabs_gecko_pwm
#include <zephyr/drivers/pwm.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <em_cmu.h>
#include <em_timer.h>
/** PWM configuration. */
struct pwm_gecko_config {
TIMER_TypeDef *t... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> channel);
}
#include <zephyr/syscalls/pwm_enable_capture_mrsh.c>
static inline int z_vrfy_pwm_disable_capture(const struct device *dev,
uint32_t channel)
{
K_OOPS(K_SYSCALL_DRIVER_PWM(dev, disable_capture));
return z_impl_pwm_disable_capture((const struct device *)dev, channel);
}
#include <... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018, Die<|fim_suffix|>zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_imx, CONFIG_PWM_LOG_LEVEL);
#define PWM_PWMSR_FIFOAV_4WORDS 0x4
#define PWM_PWMCR_SWR(x) (((uint32_t)(((uint32_t)(x)) \
<<PWM_PWMCR_SWR_SHIFT))&PWM_PWMCR_SWR_MASK)
struct i... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: <text>Copyright (c) 2026 Infineon Technologies AG,
* or an affiliate of Infineon Technologies AG. All rights reserved.</text>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT infineon_tcpwm_pwm
#include <zephyr/drivers/pwm.h>
#include <zephyr/drivers/pin... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: <text>Copyright (c) 2026 Infineon Technologies AG,
* or an affiliate of Infineon Technologies AG. All rights reserved.</text>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* PWM driver for Infineon MCUs using the TCPWM block.
*/
#define DT_DRV_COMPAT infineon_tcpwm_p... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT intel_blinky_pwm
#include <errno.h>
#include <soc.h>
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/init.h>
#include <zephyr/sys/util.h>
#include <zephyr/devicetree.h>
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>-EINVAL;
}
deviation = (target_freq / 100) + 1;
reg_val = sys_read8(base_prs + REG_PWM_PXCSS_L(prs_sel));
if (target_freq <= 324) {
/*
* Default clock source setting is 9.2MHz. When ITE chip is in power
* saving mode, 9.2MHz clock source will be gated (32.768KHz won't).
* So if we still n... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> ret;
uint8_t duty, mask;
/* Enable PWM output push-pull */
if (flags & PWM_IT8801_PUSH_PULL) {
mask = it8801_pwm_gpio_map[ch].pushpull_en;
ret = i2c_reg_update_byte_dt(&config->i2c_dev, IT8801_REG_PWMODDSR, mask, mask);
if (ret != 0) {
LOG_ERR("Failed to set push-pull (ret %d)", ret);
re... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
if (target_freq < 1) {
LOG_ERR("PWM output frequency is < 1 !");
return -EINVAL;
}
deviation = (target_freq / 100) + 1;
/*
* Default clock source setting is 8MHz, when ITE chip is in power
* saving mode, clock source 8MHz will be gated (32.768KHz won't).
* So if we still need pwm output i... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2017 Vitor Massaru Iha <vitor@massaru.org>
* Copyright (c) 2025-2026 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT espressif_esp32_ledc
#include <hal/ledc_hal.h>
#include <hal/ledc_ll.h>
#include <hal/ledc_types.h>
#include <esp_clk_tre... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> pwm_litex_cfg_##n = { \
.reg_en = DT_INST_REG_ADDR_BY_NAME(n, enable), \
.reg_width = DT_INST_REG_ADDR_BY_NAME(n, width), \
.reg_period = DT_INST_REG_ADDR_BY_NAME(n, period), \
}; \
\
DEVICE_DT_INST_DEFINE(n, \
pwm_lite... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Analog Devices Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT adi_max2221x_pwm
#include <stdlib.h>
#include <stdint.h>
#include <zephyr/drivers/mfd/max2221x.h>
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/pwm.h>
#includ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>te_dt(&config->i2c, buffer, sizeof(buffer));
}
if (result != 0) {
return result;
}
result = i2c_reg_write_byte_dt(&config->i2c, MAX37190_REGISTER_FANCONFIGURATION(channel),
value_fan_configuration);
if (result != 0) {
return result;
}
result = i2c_reg_write_byte_dt(&config->i2c, M... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023-2026 Analog Devices, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT adi_max32_pwm
#include <errno.h>
#include <zephyr/drivers/clock_control/adi_max32_clock_control.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/s... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>FUNC(idx); \
static struct mcpwm_esp32_data mcpwm_esp32_data_##idx = { \
.hal = \
{ ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>PRESC);
PWM_MODE16(pwm_reg)->TC_CTRLA = reg_val;
break;
case BIT_MODE_32:
reg_val = PWM_MODE32(pwm_reg)->TC_CTRLA;
reg_val &= ~(TC_CTRLA_PRESCSYNC_Msk | TC_CTRLA_PRESCALER_Msk);
reg_val |= (prescaler | TC_CTRLA_PRESCSYNC_PRESC);
PWM_MODE32(pwm_reg)->TC_CTRLA = reg_val;
break;
default:
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>gurations for the PWM device, including the
* host core synchronous clock, and
* peripheral asynchronous clock (conditionally).
*
* @param n Device tree node number.
*
* @note This macro conditionally includes peripheral asynchronous clock configurations based on
* the presence of relevant device ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Intel Corporation
* Copyright (c) 2022 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT microchip_xec_pwm
#include <errno.h>
#include <stdlib.h>
#include <stdint.h>
#include <zephyr/device.h>
#include <zephyr/drivers/pwm.h>
#include... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Microchip Technololgy Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT microchip_xec_pwmbbled
#include <errno.h>
#include <stdlib.h>
#include <stdint.h>
#include <zephyr/device.h>
#include <zephyr/drivers/pwm.h>
#ifdef CONFIG_SOC_SERIES_MEC172X
#include ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ERR("Could not get clock frequency");
return -EINVAL;
}
err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
if (err < 0) {
return err;
}
LOG_DBG("Set prescaler %d, reload mode %d",
1 << config->prescale, config->reload);
PWM_GetDefaultConfig(&pwm_config);
pwm_config.prescale... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>fresh */
CTIMER_StopTimer(base);
CTIMER_Reset(base);
CTIMER_ClearStatusFlags(base, CTIMER_IR_CR0INT_MASK << capture->capture_channel);
capture->first_edge_seen = false;
capture->active = true;
/* CCR: select capture edge for this channel, enable capture interrupt */
CTIMER_SetupCapture(base, ch, ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2017, 2024 NXP
* Copyright (c) 2020-2021 Vestas Wind Systems A/S
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_ftm_pwm
#include <zephyr/drivers/clock_control.h>
#include <errno.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/irq.h>
#include <soc.h>
#include... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Vestas Wind Systems A/S
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_kinetis_pwt
#include <zephyr/drivers/clock_control.h>
#include <errno.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/irq.h>
#include <soc.h>
#include <fsl_p... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>INIT_CFG(n);
DT_INST_FOREACH_STATUS_OKAY(QTMR_DEVICE)
<|fim_prefix|>/*
* Copyright (c) 2024-2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_qtmr_pwm
#include <errno.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/irq.h>
#include <fsl_qtmr.h>
#include <fsl_clock.h>
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021, 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_sctimer_pwm
#include <errno.h>
#include <zephyr/pm/device.h>
#include <zephyr/drivers/pwm.h>
#include <fsl_sctimer.h>
#include <fsl_clock.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/dr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2019 Henrik Brix Andersen <henrik@brixandersen.dk>
* Copyright 2020, 2024-2026 NXP
*
* Heavily based on pwm_mcux_ftm.c, which is:
* Copyright (c) 2017, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_kinetis_tpm
#include <zephyr/drivers/clock_control.h>
#i... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025, Linumiz GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ti_mspm0_timer_pwm
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/mspm0_clock_control.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/pwm.h>
#inclu... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Henrik Brix Andersen <henrik@brixandersen.dk>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT neorv32_pwm
#include <zephyr/device.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/drivers/syscon.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/sys/util.h>... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nuvoton_npcx_pwm
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/dt-bindings/clock/npcx_clock.h>
#include <zephyr/drivers/clock_control.h>
#in... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nordic_nrf_sw_pwm
#include <soc.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <nrfx_gpiote.h>
#include <helpers/nrfx_gppi.h>
#include <hal/nrf_gpi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018, Cue Health Inc
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nordic_nrf_pwm
#include <nrfx_pwm.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/pm/device.h>
#include <zephyr/drivers/pinctrl.h>
#include <soc.h>
#include <hal/nrf_gpio.h>
#include <stdbool... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>;
err = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_DEFAULT);
if (err) {
LOG_ERR("Failed to apply pinctrl state");
goto done;
}
/* Reset PWM to default state, same as BSP's SYS_ResetModule(id_rst) */
reset_line_toggle_dt(&cfg->reset);
/* Configure PWM device initially */
pwm_numaker_confi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2024, 2026 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_flexio_pwm
#include <errno.h>
#include <zephyr/drivers/pwm.h>
#include <fsl_flexio.h>
#include <fsl_clock.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control.h>
#include <zep... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>PWMB mode, Output = Cn[EDPOL]. Unless 100% pulse cycle is
* expected, Cn[EDPOL] is set to complement value (i.e 0 if active high and
* 1 if active low).
*/
if (pulse_cycles == period_cycles) {
config->base->CH.UC[channel].C |= eMIOS_C_EDPOL(polarity);
} else {
config->base->CH.UC[channe... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ST_PROP(inst, och_on_ack), \
}; \
\
static struct pca9685_data pca9685_##inst##_data; \
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>;
}
return 0;
}
static DEVICE_API(pwm, pwm_rcar_driver_api) = {
.set_cycles = pwm_rcar_set_cycles,
.get_cycles_per_sec = pwm_rcar_get_cycles_per_sec,
};
/* Device Instantiation */
#define PWM_DEVICE_RCAR_INIT(n) \
PINCTRL_DT_INST_D... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Realtek, SIBG-SD7
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT realtek_rts5912_pwm
#include <zephyr/drivers/pwm.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024-2026 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/irq.h>
#include <zephyr/drivers/clock_control/renesas_ra_cgc.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/drivers/pwm/pw... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/irq.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/dt-bindings/pwm/rx_mtu_pwm.h>
#include <zephyr/drivers/pinctrl.h>
#include ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024-2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/irq.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/dt-bindings/pwm/renesas_rz_pwm.h>
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>DIV) == 256 ? 0x4 \
: ((CH) == 3 || (CH) == 4 || (CH) == 6 || (CH) == 7 || (CH) == 8) && (DIV) == 1024 ? 0x5 \
: (DIV) == 1 ? 0x0 \
: (DIV) == 2 ? 0x8 \
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/irq.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control.h>
#include <zeph... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022, Joep Buruma
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT raspberrypi_pico_pwm
#include <zephyr/device.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/reset.h<|fim_suf... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2019 Henrik Brix Andersen <henrik@brixandersen.dk>
*
* Heavily based on pwm_mcux_ftm.c, which is:
* Copyright (c) 2017, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT openisa_rv32m1_tpm
#include <zephyr/drivers/clock_control.h>
#include <errno.h>
#include <zep... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Aurelien Jarno
* Copyright (c) 2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT atmel_sam_pwm
#include <zephyr/device.h>
#include <errno.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Daikin Comfort Technologies North America, Inc.
*
* Heavily based on pwm_sam0_tcc.c, which is:
* Copyright (c) 2020 Google LLC.
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* PWM driver using the SAM0 Timer/Counter (TC) Supports the SAMD21 and SAMD5x series,
* 8 and 16 b... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>el >= cfg->channels) {
return -EINVAL;
}
if (period_cycles >= top || pulse_cycles >= top) {
return -EINVAL;
}
/*
* Update the buffered width and period. These will be automatically
* loaded on the next cycle.
*/
#ifdef TCC_PERBUF_PERBUF
/* SAME51 naming */
regs->CCBUF[channel].reg = TCC_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>;
ccmr |= FIELD_PREP(ATIM_CCMR1_OC2M_Msk, ATIM_PWM_MODE1);
ccmr |= ATIM_CCMR1_OC2PE;
sys_write32(ccmr, cfg->base + CCMRX(channel));
break;
case 2:
sys_write32(pulse_cycles, cfg->base + CCR3);
ccmr = sys_read32(cfg->base + CCMRX(channel));
ccmr &= ~ATIM_CCMR2_OC3M_Msk;
ccmr |= FIELD_PREP(A... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ne GPT_OCMODE_PWM1 (GPT_CCMR1_OC1M_1 | GPT_CCMR1_OC1M_2)
#define MAX_CH_NUM (4U)
LOG_MODULE_REGISTER(pwm_sf32lb, CONFIG_PWM_LOG_LEVEL);
struct pwm_sf32lb_config {
uintptr_t base;
const struct pinctrl_dev_config *pcfg;
struct sf32lb_clock_dt_spec clock;
uint16_t prescaler;
};
static int pwm_sf32lb_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Vestas Wind Systems A/S
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief PWM shell commands.
*/
#include <zephyr/shell/shell.h>
#include <zephyr/drivers/pwm.h>
#include <stdlib.h>
struct args_index {
uint8_t device;
uint8_t channel;
uint8_t period;
uint... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 SiFive Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT sifive_pwm0
#include <zephyr/arch/cpu.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/device.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/pwm.h>
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Silicon Laboratories Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT silabs_letimer_pwm
#include <errno.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/clock_control_silabs.h>
#include <zephyr/drivers/pinctrl.h>
#inclu... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Silicon Laboratories Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <errno.h>
#include <zephyr/irq.h>
#include <zephyr/sys/util.h>
#include <zephyr/sys/util_macro.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/pwm.h>
#include <z... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Silicon Laboratories Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT silabs_timer_pwm
#include <errno.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/clock_control_silabs.h>
#include <zephyr/drivers/pinctrl.h>
#include... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2016 Linaro Limited.
* Copyright (c) 2020 Teslabs Engineering S.L.
* Copyright (c) 2023 Nobleo Technology
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT st_stm32_pwm
#include <errno.h>
#include <soc.h>
#include <stm32_ll_rcc.h>
#include <stm32_ll_tim.h>
#inclu... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>annel, uint64_t *cycles)
{
return -ENOTSUP;
}
static DEVICE_API(pwm, vnd_pwm_api) = {
.set_cycles = vnd_pwm_set_cycles,
#ifdef CONFIG_PWM_CAPTURE
.configure_capture = vnd_pwm_configure_capture,
.enable_capture = vnd_pwm_enable_capture,
.disable_capture = vnd_pwm_disable_capture,
#endif /* CONFIG_PWM... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
PINCTRL_DT_INST_DEFINE(idx); \
\
static const struct pwm_wch_gptm_config pwm_wch_gptm_##idx##_config = { ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>\
"xlnx,one-timer-only must be 0 for pwm"); \
\
static struct xlnx_axi_timer_config xlnx_axi_timer_config_##n = { \
.base = DT_INST_REG_ADDR(n), \
.freq = DT_INST_PROP(n, clock_frequency), \
.cycles_max = \
GENMASK(DT_INST_PROP(n, xlnx_count_width) - 1, 0), \
}; ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
.slice_prescaler = DT_INST_PROP(n, slice_prescaler)}; \
\
DEVICE_DT_INST_DEFINE(n, pwm_xmc4xxx_ccu4_init, NULL, NULL, &config##n, POST_KERNEL, \
CONFIG_PWM_INIT_PRIORITY, &pwm_xmc4xxx_ccu4_driver_api);
DT_I... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 SLB
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT infineon_xmc4xxx_ccu8_pwm
#include <soc.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/drivers/pinctrl.h>
#include <xmc_ccu8.h>
#include <xmc_scu.h>
#include <z... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>static int regulator_adp5360_set_active_discharge(const struct device *dev, bool active_discharge)
{
const struct regulator_adp5360_config *config = dev->config;
return mfd_adp5360_reg_update(config->mfd_dev, config->desc->cfg_reg,
ADP5360_BUCK_CFG_DISCHG_MSK, active_discharge);
}
static int... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 NXP
* Copyright (c) 2023 Martin Kiepfer <mrmarteng@teleschirm.org>
* Copyright (c) 2024 Lothar Felten <lothar.felten@gmail.com>
* SPDX-License-Identifier: Apache-2.0
*/
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/reg... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 MASSDRIVER EI (massdriver.space)
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/devicetree.h>
#include <zephyr/drivers/regulator.h>
#include <zephyr/sys/linear_range.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(regulator_bflb, CONFIG_REGULATOR_LOG_LEVEL);
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>pply if it is */
for (uint8_t i = 0U; i < config->allowed_modes_cnt; i++) {
if (mode == config->allowed_modes[i]) {
return api->set_mode(dev, mode);
}
}
return -ENOTSUP;
}
<|fim_prefix|>/*
* Copyright 2022 Nordic Semiconductor ASA
* Copyright 2023 Meta Platforms
* SPDX-License-Identifier: Ap... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Cirrus Logic, Inc.
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT cirrus_cp9314
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>t */
reg_val = *config->desc->dcdc_register & ~(DCDC_DCDC_V14_REG_DCDC_V14_CUR_LIM_MAX_HV_Msk |
DCDC_DCDC_V14_REG_DCDC_V14_CUR_LIM_MAX_LV_Msk |
DCDC_DCDC_V14_REG_DCDC_V14_CUR_LIM_MIN_Msk);
reg_val |= FIELD_PREP(DCDC_DCDC_V14_REG_DCDC_V14_CUR_LIM_MAX_HV_Msk, idx);
reg_val |= FIELD_PREP... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 Espressif Systems (Shanghai) Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT espressif_esp32_regulator
#include <zephyr/device.h>
#include <zephyr/drivers/regulator.h>
#include <zephyr/logging/log.h>
#include <hal/ldo_ll.h>
LOG_MODULE_REGISTER(regulat... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>dev->config;
regulator_common_data_init(dev);
return regulator_common_init(dev, config->is_enabled);
}
/* parent regulator */
DEFINE_FAKE_VALUE_FUNC(int, regulator_parent_fake_dvs_state_set,
const struct device *, regulator_dvs_state_t);
DEFINE_FAKE_VALUE_FUNC(int, regulator_parent_fake_sh... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> ®ulator_fixed_api);
DT_INST_FOREACH_STATUS_OKAY(REGULATOR_FIXED_DEFINE)
<|fim_prefix|>/*
* Copyright 2019-2020 Peter Bigot Consulting, LLC
* Copyright 2022 Nordic Semiconductor ASA
* Copyright 2023 EPAM Systems
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT regulator_fixed
#inc... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 Aleksandr Senin <al@meshium.net>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT gd_gd32_bldo
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/gd32.h>
#include <zephyr/drivers/regu... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2023 EPAM Systems
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT regulator_gpio
#include <stdint.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/regulator.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(regulator_gpio, CONFIG_REGULATOR... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: <text>Copyright (c) 2026 Infineon Technologies AG,
* or an affiliate of Infineon Technologies AG. All rights reserved.</text>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Regulator driver for Infineon AutAnalog PRB voltage references.
*
* Each instance repr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
static struct regulator_m5pm1_data data_##id; \
static const struct regulator_m5pm1_config config_##id = { \
.common = REGULATOR_DT_COMMON_CONFIG_INIT(node_id), \
.desc = &m5pm1_##id##_desc... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Grinn
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT maxim_max20335_regulator
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/regulator.h>
#include <zephyr/dt-bindings/regulator/max20335.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/linear_range.h... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2026 Silicon Labs
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT arduino_modulino_latch_relay
#include <zephyr/device.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/regulator.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(arduino_modulino_latch_relay, CONF... | fim | zephyrproject-rtos/zephyr | c |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.