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/*
* Copyright (c) 2025 NVIDIA Corporation <jholdsworth@nvidia.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief OpenRISC public exception handling
*/
#ifndef ZEPHYR_INCLUDE_ARCH_OPENRISC_EXCEPTION_H_
#define ZEPHYR_INCLUDE_ARCH_OPENRISC_EXCEPTION_H_
#ifndef _ASMLANGUAGE
#include <zephyr/ty... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 NVIDIA Corporation <jholdsworth@nvidia.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief OpenRISC public interrupt handling
*/
#ifndef ZEPHYR_INCLUDE_ARCH_OR1K_IRQ_H_
#define ZEPHYR_INCLUDE_ARCH_OR1K_IRQ_H_
#include <openrisc/openriscregs.h>
#define SP... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 NVIDIA Corporation <jholdsworth@nvidia.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief OpenRISC specific syscall header
*
* This header contains the OpenRISC specific syscall interface. It is
* included by the syscall interface architecture-abstracti... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 NVIDIA Corporation
*
* based on include/arch/mips/thread.h
*
* SPDX-License-Identifier: Apache-2.0
*/
/**<|fim_suffix|>;
#endif /* _ASMLANGUAGE */
#endif /* ZEPHYR_INCLUDE_ARCH_OPENRISC_THREAD_H_ */
<|fim_middle|>
* @file
* @brief Per-arch thread definition
*
* This fi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2010-2014 Wind River Systems, Inc.
* Copyright (c) 2017 Oticon A/S
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief POSIX arch specific kernel in<|fim_suffix|>_irq_unlocked(unsigned int key)
{
return key == false;
}
static ALWAYS_INLINE unsigned int arch_irq_loc... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>RCH_POSIX_ARCH_INLINES_H */
<|fim_prefix|>/*
* Copyright (c) 2022 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_POSIX_ARCH_INLINES_H
<|fim_middle|>#define ZEPHYR_INCLUDE_ARCH_POSIX_ARCH_INLINES_H
#include <zephyr/kernel_structs.h>
static ALWAYS_INLINE unsi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* POSIX inline "assembler" functions and macros for public functions */
/*
* Copyright (c) 2015, Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_POSIX_ASM_INLINE_H_
#define ZEPHYR_INCLUDE_ARCH_POSIX_ASM_INLINE_H_
/*
* The file must not be included d... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>rch/common/sys_bitops.h>
#include <zephyr/arch/common/sys_io.h>
#include <zephyr/arch/common/ffs.h>
#include <zephyr/arch/posix/posix_soc_if.h>
#endif /* _ASMLANGUAGE */
#endif /* ZEPHYR_INCLUDE_ARCH_POSIX_ASM_INLINE_GCC_H_ */
<|fim_prefix|>/*
* Copyright (c) 2015, Wind River Systems, Inc.
* Copyright... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2010-2014 Wind River Systems, Inc.
* Copyright (c) 2017 Oticon A/S
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEP<|fim_suffix|>UDE_ARCH_POSIX_EXCEPTION_H_
#define ZEPHYR_INCLUDE_ARCH_POSIX_EXCEPTION_H_
#ifndef _ASMLANGUAGE
#include <zephyr/types.h>
#ifdef __cplusplus
ext... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> IRQn);
void posix_sw_clear_pending_IRQ(unsigned int IRQn);
#ifdef CONFIG_IRQ_OFFLOAD
void posix_irq_offload(void (*routine)(const void *), const void *parameter);
#endif
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_ARCH_POSIX_POSIX_SOC_IF_H_ */
<|fim_prefix|>/*
* Copyright (c) 2017 Oticon A<|f... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 Oticon A/S
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_POSIX_POSIX_TRACE_H_
#define ZEPHYR_INCLUDE_ARCH_POSIX_POSIX_TRACE_H_
#include <stdarg.h>
#ifdef __cplusplus
extern "C" {
#endif
void posix_vprint_error_and_exit(const char *fo<|fim_suffix|>out... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 Intel Corporation
* Copyright (c) 2017 Oticon A/S
*
* SPDX-License-Identifier<|fim_suffix|>endif
#endif /* _ASMLANGUAGE */
#endif /* ZEPHYR_INCLUDE_ARCH_POSIX_THREAD_H_ */
<|fim_middle|>: Apache-2.0
*/
/**
* @file
* @brief Per-arch thread definition
*
* This file contai... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
* Contributors: 2018 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief RISCV specific kernel interface header
*
* This header contains the RISCV specific kernel interface. It is
* inclu... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2021 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_RISCV_ARCH_INLINES_H_
#define ZEPHYR_INCLUDE_ARCH_RISCV_ARCH_INLINES_H_
#ifndef _ASMLANGUAGE
#include <zephyr/kernel_structs.h>
#include "csr.h"
static ALWAYS_INLINE uint32_t arch_proc_id(void)
{
#if... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> : "r"(value), "A"(*target)
: "memory");
return ret;
}
static ALWAYS_INLINE unsigned long atomic_maxu(unsigned long *target, unsigned long value)
{
unsigned long ret;
__asm__ volatile("amomaxu.w.aq %0, %1, %2"
: "=r"(ret)
: "r"(value), "A"(*target)
: "memory");
return ret;
}
st... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 NXP Semicondutors
*
* SPDX-License-Identifier: Apache-2.0
*/
#<|fim_suffix|>NCLUDE_ARCH_ARM_CFI_H_ */
<|fim_middle|>ifndef ZEPHYR_INCLUDE_ARCH_RISCV_CFI_H_
#define ZEPHYR_INCLUDE_ARCH_RISCV_CFI_H_
#define ARCH_CFI_UNDEFINED_RETURN_ADDRESS() __asm__ volatile(".cfi_undefined ra... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>SE_HWBP 2
#define DCSR_CAUSE_DEBUGINT 3
#define DCSR_CAUSE_STEP 4
#define DCSR_CAUSE_HALT 5
#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4))
#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5))
#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
#define MCONTROL_SELECT (1<<19)
#define MCONTROL_TIMING ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>) << 23) | (R_RISCV_IMM8_GET_BIT(imm8, 2) << 22) | \
(R_RISCV_IMM8_GET_BIT(imm8, 1) << 21) | (R_RISCV_IMM8_GET_BIT(imm8, 11) << 20) | \
(R_RISCV_IMM8_GET_BIT(imm8, 19) << 19) | (R_RISCV_IMM8_GET_BIT(imm8, 18) << 18) | \
(R_RISCV_IMM8_GET_BIT(imm8, 17) << 17) | (R_RISCV_IMM... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief RISCV public error handling
*
* RISCV-specif<|fim_suffix|> \
if (k_is_user_context()) { \
arch_syscall_invoke1(reason_p, \
K_SYSCALL_USER_FAULT); \
} else { \
registe... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>RUPT_LEVEL */
unsigned long mepc; /* machine exception program counter */
unsigned long mstatus; /* machine status register */
unsigned long s0; /* callee-saved s0 */
#ifdef CONFIG_USERSPACE
unsigned long sp; /* preserved (user or kernel) stack pointer */
#endif
#ifdef CONFIG_EXCEPTION_DEBUG
_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ear(unsigned int index, unsigned long mask)
{
unsigned int key = irq_lock();
csr_write(MISELECT, index);
unsigned long val = csr_read_clear(MIREG2, mask);
irq_unlock(key);
return val;
}
#endif /* CONFIG_RISCV_ISA_EXT_SMCSRIND */
#endif /* ZEPHYR_INCLUDE_ARCH_RISCV_ICSR_H_ */
<|fim_prefix|>/*
* S... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2022 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief RISC-V public interrupt handling
*
* RISC-V-specific kernel interrupt handling interface.
*/
#ifndef ZEPHYR_INCLUDE_ARCH_RISCV_IRQ_H_
#define ZEPHYR_INCLUDE_ARCH_RISCV_IRQ_H_
#ifdef __... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Google LLC
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_RISCV_PMP_H_
#define ZEPHYR_INCLUDE_RISCV_PMP_H_
#include <zephyr/arch/riscv/arch.h>
#include <zephyr/sys/iterable_sections.h>
/**
* @brief SoC-specific PMP region descriptor.
*
* SoCs can define... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
* Contributors: 2018 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_RISCV_RISCV_PRIVILEGED_ASM_INLINE_H_
#define ZEPHYR_INCLUDE_ARCH_RISCV_RISCV_PRIVILEGED_ASM_INLINE_H_
/*
* The file must not ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_RISCV_RISCV_PRIVILEGED_ASM_INLINE_GCC_H_
#define ZEPHYR_INCLUDE_ARCH<|fim_suffix|> */
<|fim_middle|>_RISCV_RISCV_PRIVILEGED_ASM_INLINE_GCC_H_
/*
* The file must ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>t timer deadline */
#define SBI_FUNC_SET_TIMER 0
/** @brief SBI extension ID for the System Reset extension (SRST) */
#define SBI_EXT_SRST 0x53525354
/** @brief SBI_EXT_SRST function ID: reset or power off the system */
#define SBI_FUNC_SYSTEM_RESET 0
/** @brief SBI_EXT_SRST reset type: clean shutd... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>exc_sp;
unsigned long user_exc_tmp0;
unsigned long user_exc_tmp1;
#endif
#if defined(CONFIG_SMP) || (CONFIG_MP_MAX_NUM_CPUS > 1)
unsigned long hartid;
bool online;
#endif
#ifdef CONFIG_FPU_SHARING
atomic_ptr_val_t fpu_owner;
uint32_t fpu_state;
#endif
#if defined(CONFIG_CPP) && !defined(CONFIG_USERS... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>r_t addr)
{
z_soc_sys_write16(data, addr);
}
static ALWAYS_INLINE uint32_t sys_read32(mem_addr_t addr)
{
return z_soc_sys_read32(addr);
}
static ALWAYS_INLINE void sys_write32(uint32_t data, mem_addr_t addr)
{
z_soc_sys_write32(data, addr);
}
static ALWAYS_INLINE uint64_t sys_read64(mem_addr_t addr)... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2020 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief RISCV specific syscall header
*
* This header contains the RISCV specific syscall interface. It is
* included by the syscall interface architecture-abstraction header
* (include/arch/syscall.h)
*/
#ifndef... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Per-arch thread definition
*
* This file contains definitions for
*
* struct _thread_arch
* struct _callee_saved
*
* <|fim_suffix|>YPE uint32_t
#endif
#endif
struct z_riscv_fp_context... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH
* Copyright (c) 2024 Renesas Electronics Corporation
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Renesas RX specific kernel interface header
*
* This header contains the Renesas RX specific kernel interface. It is
* included by... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>structs.h>
static ALWAYS_INLINE unsigned int arch_num_cpus(void)
{
return CONFIG_MP_MAX_NUM_CPUS;
}
#endif /* ZEPHYR_INCLUDE_ARCH_RX_INLINES_H */
<|fim_prefix|>/*
* Copyright (c) 2024 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.<|fim_middle|>0
*/
#ifndef ZEPHYR_INCLUDE_AR... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
do { \
arch_irq_unlock(0); \
__asm__ volatile("mov %[_reason], r1\n\t" \
"int #2\n\t" ::[_reason] "r"(reason_p) \
: "r1", "memory"); \
} while (false)
#ifdef __cplusplus
}
#en... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>15;
uint32_t entry_point;
uint32_t psw;
};
#ifdef __cplusplus
}
#endif
#endif /* _ASMLANGUAGE */
#endif /* ZEPHYR_INCLUDE_ARCH_RX_INLINES_H_ */
<|fim_prefix|>/*
* Copyright (c) 2024 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_RX_INLINES_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH
* Copyright (c) 2024 Renesas Electronics Corporation
*
* SPDX-License-Identifier: A<|fim_suffix|>* @brief Renesas RX public kernel miscellaneous
*
* Renesas RX-specific kernel miscellaneous interface. Included by arch/rx/arch.h.
*/
#... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_RX_SW_NMI_TABLE_H
#define ZEPHYR_INCLUDE_ARCH_RX_SW_NMI_TABLE_H
#include <stdint.h>
#include <soc.h>
#define NMI_TABLE_SIZE (5)
typedef void (*nmi_callback_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH
* Copyright (c) 2024 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_RX_THREAD_H_
#define ZEPHYR_INCLUDE_ARCH_RX_THREAD_H_
#ifndef _ASM<|fim_suffix|> callee-saved registers */
};
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019-2020 Cobham Gaisler AB
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief SPARC specific kernel interface header
*
* This header contains the SPARC specific kernel interface. It is
* included by the kernel interface architecture-abstraction header
* (includ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|><zephyr/kernel_structs.h>
static ALWAYS_INLINE unsigned int arch_num_cpus(void)
{
return CONFIG_MP_MAX_NUM_CPUS;
}
#endif /* ZEPHYR_INCLUDE_ARCH_SPARC_ARCH_INLINES_H */
<|fim_prefix|>/*
* Copyright (c) 2022 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_SP... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*<|fim_suffix|>_t npc;
uint32_t wim;
uint32_t tbr;
uint32_t y;
};
#ifdef __cplusplus
}
#endif
#endif /* _ASMLANGUAGE */
#endif /* ZEPHYR_INCLUDE_ARCH_SPARC_EXCEPTION_H_ */
<|fim_middle|>
* Copyright (c) 2019-2020 Cobham Gaisler AB
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLU... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>INCLUDE_ARCH_SPARC_SPARC_H_ */
<|fim_prefix|>/*
* Copyright (c) 2019-2020 Cobham Gaisler AB
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_SPARC_SPARC_H_
#define ZEPHYR_INCLUDE_ARCH_SPARC_SPARC_H_
/*
* @file
* @brief Definitions for the SPARC V8 architecture.
*/
/* Proces... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019-2020 Cobham Gaisler AB
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Per-arch thread definition
*
* This file contains definitions for
*
* struct _thread_arch
* struct _callee_saved
*
* necessary to instantiate instances of struct k_thread.
*/
#i... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) BayLibre SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* The purpose of this file is to provide essential/minimal architecture-
* specific structure definitions to be included in generic kernel
* structures.
*
* The following rules must be observed:
* 1. arch/structs.h s... | fim | zephyrproject-rtos/zephyr | c |
/* syscall.h - automatically selects the correct syscall.h file to include */
/*
* Copyright (c) 1997-2014 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_SYSCALL_H_
#define ZEPHYR_INCLUDE_ARCH_SYSCALL_H_
#if defined(CONFIG_X86_64)
#include <zephyr/arch/x86/intel64... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>r_bit(mem_addr_t addr, unsigned int bit)
{
__asm__ volatile("btrl %1, %0"
: "+m" (*(volatile uint8_t *) (addr))
: "Ir" (bit));
}
static ALWAYS_INLINE int sys_test_bit(mem_addr_t addr, unsigned int bit)
{
int ret;
__asm__ volatile("btl %2, %1;"
"sbb %0, %0"
: "=r" (ret), "+m" (*(volati... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Intel Corporation
* Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_X86_ARCH_INLINES_H_
#define ZEPHYR_INCLUDE_ARCH_X86_ARCH_INLINES_H_
#ifndef _ASMLANGUAGE
#include <zephyr/arch/x86/x86_acpi.... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>[size / sizeof(arch_thread_hw_shadow_stack_t) - 2] = \
(uintptr_t)X86_KERNEL_CS }
#else /* CONFIG_X86_64 */
#ifdef CONFIG_X86_DEBUG_INFO
extern void z_x86_thread_entry_wrapper(k_thread_entry_t entry,
void *p1, void *p2, void *p3);
#define ___x86_entry_point z_x86_thread_entry_wrapper
#els... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Intel Corp.
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_X86_CPUID_H_
#define ZEPHYR_INCLUDE_ARCH_X86_CPUID_H_
#include <stdint.h>
#ifndef _ASMLANGUAGE
#ifdef __cplusplus
extern "C" {
#endif
#define CPUID_BASIC_INFO_1 0x01
#define CPUID_EXTENDED_FEA... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>truct efi_boot_arg *efi_arg);
/** @brief Get the ACPI RSDP table pointer from EFI boot argument
*
* @return A valid pointer to ACPI RSDP table or NULL otherwise.
*/
void *efi_get_acpi_rsdp(void);
#else /* CONFIG_X86_EFI */
#define efi_init(...)
#define efi_get_acpi_rsdp(...) NULL
#endif /* CONFIG_X... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2010-2014 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief IA-32 specific kernel interface header
*
* This header contains the IA-32 portion of the X86 specific kernel
* interface (see include/zephyr/arch/x86/cpu.h).
*/
#ifndef ZEPHYR_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ser_always
#else
#define KPTI_IRET iret
#define KPTI_IRET_USER iret
#endif /* CONFIG_X86_KPTI */
#endif /* _ASMLANGUAGE */
#endif /* ZEPHYR_INCLUDE_ARCH_X86_IA32_ASM_H_ */
<|fim_prefix|>/* asm.h - x86 tool dependent headers */
/*
* Copyright (c) 2007-2014 Wind River Systems, Inc.
*
* SPDX-License-Id... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2025 NXP Semicondutors
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_X86_IA32_CFI_H_
#define ZEPHYR_INCLUDE_ARCH_X86_IA32_CFI_H_
#define ARCH_CFI_UNDEFINED_RETURN_ADDRESS() __asm__ volatile(".cfi_undefined eip")
#endif /* ZEPHYR_INCLUDE_ARCH_X86_IA32_CFI_H_ */
<|endoft... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ent if cs = USER_CODE_SEG */
uint32_t esp;
uint32_t ss;
};
#ifdef __cplusplus
}
#endif
#endif /* _ASMLANGUAGE */
#endif /* ZEPHYR_INCLUDE_ARCH_X86_IA32_EXCEPTION_H_ */
<|fim_prefix|>/*
* Copyright (c) 2010-2014 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_IN... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief IA-32 specific gdbstub interface header
*/
#ifndef ZEPHYR_INCLUDE_ARCH_X86_GDBSTUB_SYS_H_
#define ZEPHYR_INCLUDE_ARCH_X86_GDBSTUB_SYS_H_
#ifndef _ASMLANGUAGE
#include <stdint.h>
#include <... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>es */
uint8_t reserved_or_param:5;
/* Bits 5-7 0 0 0 per CPU manual */
uint8_t always_0_0:3;
};
};
/* Second DWORD: 8-15 */
union {
/* Code or data Segments */
struct {
/* Set by the processor, init to 0 */
uint8_t accessed:1;
/* executable ? readable : writable */
uint8_t... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Intel
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEP<|fim_suffix|> into 2 distinct blocks owned by differing threads. In
* other words, given that the 'fxnsave/fxrstor' instructions
* save/restore both the X87 FPU and XMM registers, it's not possible
* for a thread... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>1, %0\n\t"
"btl %2, %0\n\t"
: "=a" (ret)
: "Nd" (port), "Ir" (bit));
return (ret & 1U);
}
static ALWAYS_INLINE
int sys_io_test_and_set_bit(io_port_t port, unsigned int bit)
{
int ret;
ret = sys_io_test_bit(port, bit);
sys_io_set_bit(port, bit);
return ret;
}
static ALWAYS_INLINE
in... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>2,
uintptr_t arg3,
uintptr_t call_id)
{
uint32_t ret;
__asm__ volatile("int $0x80"
: "=a" (ret)
: "S" (call_id), "a" (arg1), "d" (arg2), "c" (arg3)
: "memory");
return ret;
}
__pinned_func
static inline uintptr_t arch_syscall_invoke2(uintptr_t arg1, uintptr_t arg2,
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>bytes: name of register */
unsigned short fcw; /* 2 : x87 FPU control word */
unsigned short pad1; /* 2 : N/A */
unsigned short fsw; /* 2 : x87 FPU status word */
unsigned short pad2; /* 2 : N/A */
unsigned short ftw; /* 2 : x87 FPU tag word */
unsigned short pad3; /*... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>NTEL64_ARCH_H_ */
<|fim_prefix|>/*
* Copyright (c) 2019 Intel Corp.
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Intel-64 specific kernel interface header
*
* This header contains the Intel-64 portion of the X86 specific kernel
* interface (see include/zephyr/arch/x86/cpu.h).
*/... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2025 NXP Semicondutors
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_X86_INTEL64_CFI_H_
#define ZEPHYR_INCLUDE_ARCH_X86_INTEL64_CFI_H_
#define ARCH_CFI_UNDEFINED_RETURN_ADDRESS() __asm__ volatile(".cfi_undefined rip")
#endif /* ZEPHYR_INCLUDE_ARCH_X86_INTEL64_CFI_H_ */... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Intel Corp.
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_X86_INTEL64_EXCEPTION_H_
#define ZEPHYR_INCLUDE_ARCH_X86_INTEL64_EXCEPTION_H_
#ifndef _ASMLANGUAGE
#include <zephyr/arch/x86/intel64/thread.h>
#ifdef __cplusplus
extern "C" {
#endif
/*
* the ex... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2019 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief x86 (INTEL64) specific syscall header
*
* This header contains the x86 specific syscall interface. It is
* included by the syscall interface architecture-abstraction header
* (include/arch/syscall.h)
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>rs for this thread when restoring context */
uint64_t ss;
uint64_t cs;
#endif
#ifdef CONFIG_HW_SHADOW_STACK
uintptr_t *shstk_addr;
uintptr_t *shstk_base;
size_t shstk_size;
#endif
uint64_t rax;
uint64_t rcx;
uint64_t rdx;
uint64_t rsi;
uint64_t rdi;
uint64_t r8;
uint64_t r9;
uint64_t r10;
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>efine VTD_CAP_FRO(cap) \
(((uint64_t)cap & VTD_CAP_FRO_MASK) >> VTD_CAP_FRO_POS)
/* Extended Capability Register details */
#define VTD_ECAP_C BIT(0)
/* Global Command Register details */
#define VTD_GCMD_CFI 23
#define VTD_GCMD_SIRTP 24
#define VTD_GCMD_IRE 25
#define VTD_GCMD_QIE 26
#define ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>IOS_H_
#define ZEPHYR_ARCH_X86_INCLUDE_LEGACY_BIOS_H_
void *bios_acpi_rsdp_get(void);
#endif /* ZEPHYR_ARCH_X86_INCLUDE_LEGACY_BIOS_H_ */
<|fim_prefix|>/*
* Copyright (c) 2023 Intel Corporatio<|fim_middle|>n
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_ARCH_X86_INCLUDE_LEGACY_B<|endoft... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ally-initialized arrays behave as expected.
*/
X86_MEMMAP_ENTRY_UNUSED, /* this entry is unused/invalid */
X86_MEMMAP_ENTRY_RAM, /* available RAM */
X86_MEMMAP_ENTRY_ACPI, /* reserved for ACPI */
X86_MEMMAP_ENTRY_NVS, /* preserve during hibernation */
X86_MEMMAP_ENTRY_DEFECTIVE, /* bad memory m... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>mask */
#define K_MEM_PARTITION_PERM_MASK (Z_X86_MMU_RW | Z_X86_MMU_US | \
Z_X86_MMU_XD)
#ifndef _ASMLANGUAGE
#include <zephyr/sys/slist.h>
/* Page table entry data type at all levels. Defined here due to
* k_mem_partition_attr_t, eventually move to private x86_mmu.h
*/
#if defined(CONFIG_X86_64... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Intel Corp.
* SPD<|fim_suffix|>C0000101U
#define X86_KERNEL_GS_BASE 0xC0000102U
#ifndef _ASMLANGUAGE
#ifdef __cplusplus
extern "C" {
#endif
/*
* z_x86_msr_write() is shared between 32- and 64-bit implementations, but
* due to ABI differences with long return values, z_x86_ms... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>fine MULTIBOOT_INFO_FB_TYPE_RGB 1
#endif /* ZEPHYR_INCLUDE_ARCH_X86_MULTIBOOT_H_ */
<|fim_prefix|>/*
* Copyright (c) 2019 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_X86_MULTIBOOT_H_
#define ZEPHYR_I<|fim_middle|>NCLUDE_ARCH_X86_MULTIBOOT_H_
#ifndef _ASM... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>length;
uint32_t mmap_addr;
uint32_t unused2[9];
uint32_t fb_addr_lo;
uint32_t fb_addr_hi;
uint32_t fb_pitch;
uint32_t fb_width;
uint32_t fb_height;
uint8_t fb_bpp;
uint8_t fb_type;
uint8_t fb_color_info[6];
};
typedef struct multiboot_info multiboot_info_t;
#endif
<|fim_prefix|>/*
* Copyr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_X86_THREAD_STACK_H
#define ZEPHYR_INCLUDE_ARCH_X86_THREAD_STACK_H
#include <zephyr/arch/x86/mmustructs.h>
#ifdef CONFIG_X86_64
#define ARCH_STACK_PTR_ALIGN 16UL
#else
#define ARCH_STACK_P... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>am trigger the interrupt level received from ACPICA lib
* @return return encoded interrupt flag
*/
uint32_t arch_acpi_encode_irq_flags(uint8_t polarity, uint8_t trigger);
<|fim_prefix|>/*
* Copyright (c) 2023, Intel Corporation
*
* SPDX-License-Identifier: Apac<|fim_middle|>he-2.0
*/
/**
* @brief ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> return z_tsc_read();
}
#endif /* ZEPHYR_ARCH_X86_INCLUDE_X86_ACPI_H_ */
<|fim_prefix|>/*
* Copyright (c) 2023 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/arch/x86/efi.h>
#include <zephyr/arch/x86/legacy_bios.h>
#ifndef ZEPHYR_ARCH_X86_INCLUDE_X86_ACPI_H_
#define ZEP... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>else
#define ARCH_EXCEPT(reason_p) do { \
xtensa_arch_except(reason_p); \
CODE_UNREACHABLE; \
} while (false)
#endif
__syscall void xtensa_user_fault(unsigned int reason);
#include <zephyr/syscalls/arch.h>
/* internal routine documented in C file, needed by IRQ_CONNECT() macro */
void z_irq_prio... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>FIG_MP_MAX_NUM_CPUS;
#endif
}
#endif /* !_ASMLANGUAGE */
#endif /* ZEPHYR_INCLUDE_ARCH_XTENSA_ARCH_INLINES_H_ */
<|fim_prefix|>/*
* Copyright (c) 2016 Cadence Design Systems, Inc.
* Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright<|fim_suffix|>value)
{
return Z__GEN_ATOMXCHG(value);
}
/** Implementation of @ref atomic_add. */
static ALWAYS_INLINE
atomic_val_t atomic_add(atomic_t *target, atomic_val_t value)
{
return Z__GEN_ATOMXCHG(cur + value);
}
/** Implementation of @ref atomic_sub. */
static ALWAYS_INLINE
at... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2021 Intel Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_XTENSA_CACHE_H_
#define ZEPHYR_INCLUDE_ARCH_XTENSA_CACHE_H_
#include <xtensa/config/core-isa.h>
#include <zephyr/toolchain.h>
#include <zephyr/sys/util.h>
#include <zephyr/debug/sparse.h>
#includ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2014 Wind River Systems, Inc.
* Copyright (c) 2016 Cadence Design Systems, Inc.
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Xtensa public exception handling
*
* Xtensa-specific kernel exception handling interface. Included by
* arch/xtensa/arch.h.
*/
<|fim_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>r is A0 - A15
* @retval false if register is not A0 - A15
*/
static inline bool gdb_xtensa_is_logical_addr_reg(struct xtensa_register *reg)
{
if (reg->regno < 16) {
return true;
} else {
return false;
}
}
/**
* Test if the register is a address register (AR0 - AR31/AR63).
*
* @retval true if... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2016 Cadence Design Systems, Inc.
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_XTENSA_XTENSA_IRQ_H_
#define ZEPHYR_INCLUDE_ARCH_XTENSA_XTENSA_IRQ_H_
#include <stdint.h>
#include <zephyr/toolchain.h>
#include <xtensa/config/core-isa.h>
#define CONFIG_GEN_IR... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2023 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include <zephyr/toolchain.h>
#include <zephyr/sys/util_macro.h>
#include <xtensa/config/core-isa.h>
#ifndef ZEPHYR_INCLUDE_ARCH_XTENSA_XTENSA_MPU_H
#define ZEPHYR_INCLUDE_ARCH_XTENSA_XTENSA_MPU_H
/**
* @d... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_XTENSA_STRUCTS_H_
#define ZEPHYR<|fim_suffix|>NSA_STRUCTS_H_
/* Per CPU architecture specifics */
struct _cpu_arch {
#if defined(CONFIG_XTENSA_LAZY_HIFI_SHARING)
atomic_ptr_val_t hifi_owner; /* Ow... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Xtensa specific syscall header
*
* This header contains the Xtensa specific syscall interface. It is
* included by the syscall interface architecture-abstraction header
* (include/arch/sy... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_XTENSA_THREAD_H_
#define ZEPHYR_INCLUDE_ARCH_XTENSA_THREAD_H_
#include <stdint.h>
#ifndef _ASMLANGUAGE
#ifdef CONFIG_XTENSA_MPU
#include <zephyr/arch/xtensa/mpu.h>
#endif
#ifdef CONFIG_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_XTENSA_THREAD_STACK_H_
#define ZEPHYR_INCLUDE_ARCH_XTENSA_THREAD_STACK_H_
#include <xtensa/config/core-isa.h>
#include <zephyr/toolchain.h>
#include <zephyr/sys/util.h>
#ifdef CONFIG_KER... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2022 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#ifndef ZEPHYR_INCLUDE_ARCH_XTENSA_XTENSA_MMU_H
#define ZEPHYR_INCLUDE_ARCH_XTENSA_XTENSA_MMU_H
/**
* @defgroup xtensa_mmu_apis Xtensa Memory Management Unit (MMU) APIs
* @ingroup xtensa_apis
* @{
*/
/**... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>dev, cb);
}
/**
* @brief Sets up signal routing for a given input channel.
*
* Some codecs can do input routing (multiplexing) from a chosen set of
* physical inputs. This function maps a given audio (stream) channel to
* a given physical input terminal.
*
* @param dev Pointer to the audio codec d... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>pcm_rate or \ref pcm_width is set to 0 for a stream,
* the stream would be disabled
*/
struct pcm_stream_cfg {
/** PCM sample rate of stream */
uint32_t pcm_rate;
/** PCM sample width of stream */
uint8_t pcm_width;
/** PCM sample block size per transfer */
uint16_t block_size;
/** Gain to apply ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>e Notification */
#define UMP_EP_DISC_FILTER_EP_NAME BIT(2)
/** Requesting a Product Instance Id Notification */
#define UMP_EP_DISC_FILTER_PRODUCT_ID BIT(3)
/** Requesting a Stream Configuration Notification */
#define UMP_EP_DISC_FILTER_STREAM_CFG BIT(4)
/** @} */
/**
* @brief Filter bitmap of... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Yonatan Schachter
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Header file for binary descriptors
* @ingroup bindesc
*/
#ifndef ZEPHYR_INCLUDE_ZEPHYR_BINDESC_H_
#define ZEPHYR_INCLUDE_ZEPHYR_BINDESC_H_
/**
* @defgroup bindesc Binary Descriptors
* @in... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/** @file
* @brief Bluetooth device address definitions and utilities.
*/
/*
* Copyright (c) 2019 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_BLUETOOTH_ADDR_H_
#define ZEPHYR_INCLUDE_BLUETOOTH_ADDR_H_
#include <stdint.h>
#include <string.h>
#include... | fim | zephyrproject-rtos/zephyr | c |
/** @file
* @brief Bluetooth Assigned Numbers, codes and identifiers.
*/
/*
* Copyright (c) 2015-2025 Intel Corporation
* Copyright (c) 2017-2026 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_BLUETOOTH_ASSIGNED_NUMBERS_H_
#define ZEPHYR_INCLUDE_BLUETOOTH_ASSIGNED_N... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/** @file
* @brief Attribute Protocol handling.
*/
/*
* Copyright (c) 2016 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_BLUETOOTH_ATT_H_
#define ZEPHYR_INCLUDE_BLUETOOTH_ATT_H_
/**
* @brief Attribute Protocol (ATT)
* @defgroup bt_att Attribute Protocol (AT... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> has changed */
bt_aics_gain_setting_cb gain_setting;
/** The audio input type has changed */
bt_aics_type_cb type;
/** The audio input status has changed */
bt_aics_status_cb status;
/** The audio input description has changed */
bt_aics_description_cb ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/**
* @file
* @brief Bluetooth Audio Stream Control Service (ASCS) APIs.
*/
/*
* Copyright (c) 2026 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_BLUETOOTH_AUDIO_ASCS_H_
#define ZEPHYR_INCLUDE_BLUETOOTH_AUDIO_ASCS_H_
/**
* @brief Audio Stream Control... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_AUDIO_LOCATION_TOP_FRONT_CENTER:
return "Top front center";
case BT_AUDIO_LOCATION_TOP_CENTER:
return "Top center";
case BT_AUDIO_LOCATION_TOP_BACK_LEFT:
return "Top back left";
case BT_AUDIO_LOCATION_TOP_BACK_RIGHT:
return "Top back right";
case BT_AUDIO_LOCATION_TOP_SIDE_LEFT:
return "Top... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/**
* @file
* @brief Header for Bluetooth BAP LC3 presets.
*
* Copyright (c) 2023-2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_BLUETOOTH_AUDIO_BAP_LC3_PRESET_
#define ZEPHYR_INCLUDE_BLUETOOTH_AUDIO_BAP_LC3_PRESET_
/**
* @brief Basic Audio Profil... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/**
* @file
* @brief Bluetooth Common Audio Profile (CAP) APIs.
*/
/*
* Copyright (c) 2022-2025 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_BLUETOOTH_AUDIO_CAP_H_
#define ZEPHYR_INCLUDE_BLUETOOTH_AUDIO_CAP_H_
/**
* @brief Common Audio Profile (CAP)... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/**
* @file
* @brief Header for Bluetooth Audio Content Control Identifier.
*
* Copyright (c) 2020 Bose Corporation
* Copyright (c) 2021-2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_BLUETOOTH_AUDIO_CCID_H_
#define ZEPHYR_INCLUDE_BLUETOOTH_AUDIO_C... | fim | zephyrproject-rtos/zephyr | c |
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