text stringlengths 14 100k | source stringclasses 1
value | repo stringclasses 810
values | language stringclasses 13
values |
|---|---|---|---|
<|fim_suffix|>U_SET_DEST 0x76
#define ARC_CONNECT_CMD_IDU_READ_DEST 0x77
#define ARC_CONNECT_CMD_IDU_GEN_CIRQ 0x78
#define ARC_CONNECT_CMD_IDU_ACK_CIRQ 0x79
#define ARC_CONNECT_CMD_IDU_CHECK_STATUS 0x7a
#define ARC_CONNECT_CMD_IDU_CHECK_SOURCE 0x7b
#define ARC_CONNECT_CMD_IDU_SET_MASK 0x7c
#define ARC_CONNE... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* arcv2_irq_unit.h - ARCv2 Interrupt Unit device driver */
/*
* Copyright (c) 2014 Wind River Systems, Inc.
* Copyright (c) 2020 Synopsys.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_ARC_V2_ARCV2_IRQ_UNIT_H_
#define ZEPHYR_INCLUDE_ARCH_ARC_V2_ARCV2_IRQ_UNIT_H_
#ifdef __... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* asm_inline.h - ARC inline assembler and macros for public functions */
/*
* Copyright (c) 2015 Intel Corporation.
*
* SPDX-License-Ide<|fim_suffix|>SM_INLINE_H_
#define ZEPHYR_INCLUDE_ARCH_ARC_V2_ASM_INLINE_H_
/*
* The file must not be included directly
* Include kernel.h instead
*/
#if define... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* asm_inline_gcc.h - ARC inline assembler and macros for public functions */
/*
* Copyright (c) 2015 Intel Corporation.
*
* SPDX-License-Identifier<|fim_suffix|>nclude <zephyr/types.h>
#include <stddef.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief read timestamp register (CPU frequency)... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ARCv2 auxiliary registers definitions
*
*
* Definitions for auxiliary registers.
*/
#ifndef ZEPHYR_INCLUDE_ARCH_ARC_V2_AUX_REGS_H_
#define ZEPHYR_INCLUDE_ARCH_ARC_V2_AUX_REGS_H_
#i... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Synopsys.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_ARC_V2_DSP_ARC_DSP_H_
#define ZEPHYR_INCLUDE_ARCH_ARC_V2_DSP_ARC_DSP_H_
/**
* @brief Disable dsp context preservation
*
* The function is used to disable the preservation of dsp
* and agu cont... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2014 Wind River Systems, Inc.
*<|fim_suffix|>ing interface. Included by arc/arch.h.
*/
#ifndef ZEPHYR_INCLUDE_ARCH_ARC_V2_ERROR_H_
#define ZEPHYR_INCLUDE_ARCH_ARC_V2_ERROR_H_
#include <zephyr/arch/arc/syscall.h>
#include <zephyr/arch/exception.h>
#include <stdbool.h>
#ifdef __cplu... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ARCv2 public exception handling
*
* ARC-specific kernel exception handling interface. Included by arc/arch.h.
*/
#ifndef ZEPHYR_INCLUDE_ARCH_ARC_V2_EXCEPTION_H_
#define ZEPHYR_INCLUD... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>atic ALWAYS_INLINE bool arch_cpu_irqs_are_enabled(void)
{
/* Probe the live STATUS32 register. IE lives at bit 31 there,
* unlike the bit 4 position used in the packed value returned
* by "clri" above.
*/
return (z_arc_v2_aux_reg_read(_ARC_V2_STATUS32) & _ARC_V2_STATUS32_IE) != 0;
}
#endif /* _AS... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* SPDX-License-Ident<|fim_suffix|>cle_get_64(void);
static inline uint64_t arch_k_cycle_get_64(void)
{
return sys_clock_cycle_get_64();
}
#endif
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_ARCH_ARC_V2_MISC_H_ */
<|fim_middle|>ifier: Apache... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 Synopsys.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_ARC_V2_MPU_ARC_CORE_MPU_H_
#define ZEPHYR_INCLUDE_ARCH_ARC_V2_MPU_ARC_CORE_MPU_H_
#ifdef __cplusplus
extern "C" {
#endif
/*
* The defines below represent the region types. The MPU driver is resp... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2017 Synopsys.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_ARC_V2_MPU_ARC_MPU_H_
#define ZEPHYR_INCLUDE_ARCH_ARC_V2_MPU_ARC_MPU_H_
#define AUX_MPU_ATTR_UE 0x008 /* allow user execution */
#define AUX_MPU_ATTR_UW 0x010 /* allow user write */
#define AUX_MPU_AT... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 Synopsys, Inc. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_ARC_V2_SJLI_H
#define ZEPHYR_INCLUDE_ARCH_ARC_V2_SJLI_H
#define SJLI_CALL_ARC_SECURE 0
#define ARC_S_CALL_AUX_READ 0
#define ARC_S_CALL_AUX_WRITE 1
#define ARC_S_CALL... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>, %1, %2\n"
"sr %1, [%0];\n\t"
:
: "ir" (port),
"r" (reg), "ir" (bit)
: "memory", "cc");
}
static ALWAYS_INLINE
void sys_io_clear_bit(io_port_t port, unsigned int bit)
{
uint32_t reg = 0;
__asm__ volatile("lr %1, [%0]\n"
"bclr %1, %1, %2\n"
"sr %1, [%0];\n\t"
:
:... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Synopsys.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_ARC_V2_VPX_ARC_VPX_H_
#define ZEPHYR_INCLUDE_ARCH_ARC_V2_VPX_ARC_VPX_H_
#include <zephyr/sys_clock.h>
/**
* @brief Obtain a cooperative lock on the VPX vector registers
*
* This function is u... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* arch_inlines.h - automatically selects the correct arch_inlines.h file to
* include based on the selected architecture.
*/
/*
* Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_INLINES_H_
#define ZEPH<|fim_suf... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @defgroup arch-interface Architecture Interface
* @ingroup internal_api
* @brief Internal kernel APIs with public scope
*
* Any public kernel APIs that are implemented as inline functions and need to
* c... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>tely.
*/
#define ARCH_KERNEL_STACK_RESERVED MPU_GUARD_ALIGN_AND_SIZE
#define ARCH_KERNEL_STACK_OBJ_ALIGN Z_MPU_GUARD_ALIGN
#endif
/* On arm, all MPU guards are carve-outs. */
#define ARCH_THREAD_STACK_RESERVED 0
/* Legacy case: retain containing extern "C" with C++ */
#ifdef CONFIG_ARM_MPU
#ifdef CONFI... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>fic call to get processor ID
*/
return arch_curr_cpu()->id;
}
static ALWAYS_INLINE unsigned int arch_num_cpus(void)
{
return CONFIG_MP_MAX_NUM_CPUS;
}
#endif /* ZEPHYR_INCLUDE_ARCH_ARM_ARCH_INLINES_H */
<|fim_prefix|>/*
* Copyright 2022 IoT.bzh
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_tls_ptr = _current->tls;
#endif
#if defined(CONFIG_USERSPACE) && defined(CONFIG_USE_SWITCH)
/* Set things up to write the CONTROL.nPRIV bit. We know the outgoing
* thread is in privileged mode (because you can't reach a
* context switch unless you're in the kernel!).
*/
extern uint32_t arm_m_sw... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>H_ARM_ASM_INLINE_H_ */
<|fim_prefix|>/* ARM AArch32 inline assembler functions and macros for public functions */
/*
* Copyright (c) 2015, Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_ARM_ASM_INLINE_H_
#d<|fim_middle|>efine ZEPHYR_INCLUDE_ARCH_ARM_A... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>else
#error "Cortex-M0 and Cortex-M0+ require SoC specific support for cross core synchronisation."
#endif
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
key = __get_BASEPRI();
__set_BASEPRI_MAX(_EXC_IRQ_DEFAULT_PRIO);
__ISB();
#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \
|| defi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>nce_full(void)
{
__DMB();
}
static ALWAYS_INLINE void z_barrier_dsync_fence_full(void)
{
__DSB();
}
static ALWAYS_INLINE void z_barrier_isync_fence_full(void)
{
__ISB();
}
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_BARRIER_ARM_H_ */
<|fim_prefix|>/**
* Copyright (c) 2023 Carlo Caione <cc... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 NXP Semicondutors
*
* SPDX-License-Ident<|fim_suffix|>m__ volatile(".cfi_undefined lr")
#endif /* ZEPHYR_INCLUDE_ARCH_ARM_CFI_H_ */
<|fim_middle|>ifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_ARM_CFI_H_
#define ZEPHYR_INCLUDE_ARCH_ARM_CFI_H_
#define ARCH_CFI_UNDEFINED_RET... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>);
}
static ALWAYS_INLINE void arm_arch_timer_enable(unsigned char enable)
{
uint64_t cntv_ctl;
cntv_ctl = read_cntv_ctl();
if (enable) {
cntv_ctl |= CNTV_CTL_ENABLE_BIT;
} else {
cntv_ctl &= ~CNTV_CTL_ENABLE_BIT;
}
write_cntv_ctl(cntv_ctl);
}
static ALWAYS_INLINE void arm_arch_timer_set_ir... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>define SCTLR_I_BIT BIT(12)
/* Armv8-R Cortex-R52 Cache Segregation Control Register */
#define IMP_CSCTLR_DFLW_SHIFT (0)
#define IMP_CSCTLR_IFLW_SHIFT (8)
#define IMP_CSCTLR(iway, dway) ((iway << IMP_CSCTLR_IFLW_SHIFT) | \
((dway << IMP_CSCTLR_DFLW_SHIFT)))
/* Hyp System Control Register */
#defin... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> */
struct __fpu_sf {
uint32_t s[16]; /* s0~s15 (d0-d7) */
#ifdef CONFIG_VFP_FEATURE_REGS_S64_D32
uint64_t d[16]; /* d16~d31 */
#endif
uint32_t fpscr;
uint32_t undefined;
};
#endif
/* Additional register state that is not stacked by hardware on exception
* entry.
*
* These fields are ONLY valid in... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2022 IoT.bzh
*
* SPDX-License-Identifier: Apache-2.0
*
* Armv8-R AArch32 architecture helpers.
*
*/
#ifndef ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_LIB_HELPERS_H_
#define ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_LIB_HELPERS_H_
#ifndef _ASMLANGUAGE
#include <stdint.h>
#define read_sysreg32(op1, CRn, C... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>RTEX_R8)
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U)
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U)
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U)
#endif
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U)
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U)
#def... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>INLINE void sys_write16(uint16_t data, mem_addr_t addr)
{
barrier_dmem_fence_full();
__asm__ volatile("strh %0, [%1]" : : "r" (data), "r" (addr));
}
static ALWAYS_INLINE uint32_t sys_read32(mem_addr_t addr)
{
uint32_t val;
__asm__ volatile("ldr %0, [%1]" : "=r" (val) : "r" (addr));
barrier_dmem_fe... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 IoT.bzh
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_TIMER_H_
#define ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_TIMER_H_
#ifdef CONFIG_ARM_ARCH_TIMER
#ifndef _ASMLANGUAGE
#include <zephyr/drivers/timer/arm_arch_timer.h>
#include <zephyr/sys... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Arm Limited (or its affiliates). All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief tpidruro bits allocation
*
* Among other things, the tpidruro holds the address for the current
* CPU's <|fim_suffix|>R_TPIDRURO_H_
#define ZEPHYR_INCLUDE_AR... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>hardware-saved exception stack frame (no FPU context):
* R0-R3 (4 x 4B = 16B)
* R12 (4B)
* LR (4B)
* Return address (4B)
* RETPSR (4B)
*--------------------------
* Total: 32 bytes
*/
#define _EXC_HW_SAVED_BASIC_SF_SIZE (32)
#define _EXC_HW_SAVED_BASIC_SF_RETADDR_OFFSET (24)
#define _EXC... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ARM AArch32 Cortex-M public exception handling
*/
#ifndef ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_EXCEPTION_H_
#define ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_EXCEPTION_H_
#include <zephyr/dev... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>);
#endif /* ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_FPU_H_ */
<|fim_prefix|>/*
* Copyright (c) 2021, Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_FPU_H_
#define ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_FPU_H_
#include <stdint.h>
#include <stdbool.h>... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ARM CORTEX-M memory map
*
* This module contains definitions for the memory map of the CORTEX-M series of
* processors.
*/
#ifndef ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_MEMORY_MAP_H_
#de... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>#define NVIC_NODEID DT_INST(0, arm_v7m_nvic)
#elif defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#define NVIC_NODEID DT_INST(0, arm_v6m_nvic)
#endif
#define NUM_IRQ_PRIO_BITS DT_PROP(NVIC_NODEID, arm_num_irq_priority_bits)
#endif /* ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_NVIC_H_ */
<|fim_prefix|>/*
* Copyright (c... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>tor Table Offset Register */
#endif
uint32_t aircr; /*!< Application Interrupt and Reset Control Register */
uint32_t scr; /*!< System Control Register */
uint32_t ccr; /*!< Configuration Control Register */
uint32_t shpr[SHPR_SIZE_W]; /*!< System Handler Priority Registers */
uint32_t shcsr; ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
* Copyright 2023, 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ARM AArch32 public error handling
*
* ARM AArch32-specific kernel error handling interface. ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ARM AArch32 public exception handling
*
* ARM AArch32-specific kernel exception handling interface. Included by
* arm/arch.h.
*/
#ifndef ZEPHYR_IN<|fim_suffix|>d(CONFIG_CPU_AAR... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> 5
/* Debug Breakpoint Control Register constants */
#define DBGDBCR_MEANING_MASK 0x7
#define DBGDBCR_MEANING_SHIFT 20
#define DBGDBCR_MEANING_ADDR_MISMATCH 0x4
#define DBGDBCR_BYTE_ADDR_MASK 0xF
#define DBGDBCR_BYTE_ADDR_SHIFT 5
#define DBGDBCR_BRK_EN_MASK ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
* Copyright (c) 2019 Nordic Semiconductor ASA.
* Copyright 2026 Arm Limited and/or its affiliates <open-source-office@arm.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ARM AArch32 public interrupt handling
*
* ARM AArc... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ARM AArch32 public kernel miscellaneous
*
* ARM AArch32-specific kernel miscellaneous interface. Included by arm/arch.<|fim_suffix|>k_cycle_get_32();
}
extern uint64_t sys_clock_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyri<|fim_suffix|>ZEPHYR_INCLUDE_ARCH_ARM_ARM_MEM_H_
#define ZEPHYR_INCLUDE_ARCH_ARM_ARM_MEM_H_
/*
* Define ARM specific memory flags used by k_mem_map_phys_bare()
* followed public definitions in include/kernel/mm.h.
*/
/** ARM Specific flags: normal memory with Non-cacheable */
#define K_ME... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ON_SECURE BIT(7)
#define MATTR_NON_GLOBAL BIT(8)
#define MATTR_SHARED BIT(9)
#define MATTR_CACHE_OUTER_WB_WA BIT(10)
#define MATTR_CACHE_OUTER_WT_nWA BIT(11)
#define MATTR_CACHE_OUTER_WB_nWA BIT(12)
#define MATTR_CACHE_INNER_WB_WA BIT(13)
#define MATTR_CACHE_INNER_WT_nWA BIT(14)
#define MATTR_CACHE_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
.name = _name, \
.base = _base, \
.size = _size, \
.attr = _attr, ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 Linaro Limited.
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _INCLUDE_ZEPHYR_ARCH_ARM_MPU_MEM_CFG_H_
#define _INCLUDE_ZEPHYR_ARCH_ARM_MPU_MEM_CFG_H_
#include <zephyr/arch/arm/mpu/arm_mpu.h>
#if !defined(CONFIG_ARMV8_M_BASELINE) && !defined(CONFIG_A... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 Linaro Limited.
* Copyright (c) 2018 Nordic Semiconductor ASA.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ASMLANGUAGE
#include <cmsis_core.h>
/* Convenience macros to represent the ARMv7-M-specific
* configuration for memory access permission and
* cache-ability ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 Linaro Limited.
* Copyright (c) 2018 Nordic Semiconductor ASA.
* Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ASMLANGUAGE
/* Convenience macros to represent the ARMv8-M-specific
* configur... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2017 Linaro Limited.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_ARM_MPU_NXP_MPU_H_
#define ZEPHYR_INCLUDE_ARCH_ARM_MPU_NXP_MPU_H_
#ifndef _ASMLANGUAGE
#define NXP_MPU_REGION_NUMBER 12
/* Bus Master User Mode Access */
#define UM_READ 4
#define UM_WRITE 2
#define UM... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_INCLUDE_ARCH_ARM_NMI_H_ */
<|fim_prefix|>/**
* @file
*
* @brief ARM AArch32 NMI routines
*/
/*
* Copyright (c) 2015 Intel Corporation
*
* SPDX-License-Identifier: Apache-<|fim_middle|>2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_ARM_NMI_H_
#define ZEPHYR_INCLUDE_ARCH_ARM_NMI_H_
#ifdef __cplusplus
extern... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Arm Limited (or its affiliat<|fim_suffix|>is struct will have a size 0 in C which is not allowed in C++ (it'll have a size 1). To
* prevent this, we add a 1 byte dummy variable.
*/
uint8_t dummy;
#endif
};
#endif
#endif /* ZEPHYR_INCLUDE_ARM_STRUCTS_H_ */
<|fim_middle|>es).... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>le("svc %[svid]\n"
IF_ENABLED(CONFIG_ARM_BTI, ("bti\n"))
: "=r"(ret)
: [svid] "i" (_SVC_CALL_SYSTEM_CALL),
"r" (ret), "r" (r6)
: "r8", "memory", "r1", "r2", "r3", "ip");
return ret;
}
static inline bool arch_is_user_context(void)
{
#if defined(CONFIG_CPU_CORTEX_M)
uint32_t value;... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>RD)
#define Z_ARM_MODE_MPU_GUARD_FLOAT_Msk (1 << 3)
#endif
typedef struct _thread_arch _thread_arch_t;
#endif /* _ASMLANGUAGE */
#endif /* ZEPHYR_INCLUDE_ARCH_ARM_THREAD_H_ */
<|fim_prefix|>/*
* Copyright (c) 2017 Intel Corporation
* Copyright 2025-2026 Arm Limited and/or its affiliates <open-source-o... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apac<|fim_suffix|>
*/
/**
* @file
* @brief ARM64 specific kernel interface header
*
* This header contains the ARM64 specific kernel interface. It is
* included by the kernel interface architecture-abstract... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2020 NXP
*
* SPDX-License-Identifie<|fim_suffix|>ad_tpidrro_el0() & TPIDRROEL0_CURR_CPU);
}
static ALWAYS_INLINE int arch_exception_depth(void)
{
return (read_tpidrro_el0() & TPIDRROEL0_EXC_DEPTH) / TPIDRROEL0_EXC_UNIT;
}
static ALWAYS_INLINE uint32_t arch_proc_id(void)
{
uint64_t cp... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>arm_smccc_conduit {
SMCCC_CONDUIT_NONE,
SMCCC_CONDUIT_SMC,
SMCCC_CONDUIT_HVC,
};
/*
* @brief Make HVC calls
*
* @param a0 function identifier
* @param a1-a7 parameters registers
* @param res results
*/
void arm_smccc_hvc(unsigned long a0, unsigned long a1,
unsigned long a2, unsigned long a3... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>3
/** ARM64 Specific flags: device memory with GRE */
#define K_MEM_ARM_DEVICE_GRE 4
/** ARM64 Specific flags: normal memory with Non-cacheable */
#define K_MEM_ARM_NORMAL_NC 5
#endif /* ZEPHYR_INCLUDE_ARCH_ARM64_ARM_MEM_H_ */
<|fim_prefix|>/*
* Copyright 2022 NXP
*
* SPDX-License-Ide<|fim_middle|>n... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>GION_DT_FLAT_ENTRY
*/
#define MMU_REGION_DT_COMPAT_FOREACH_FLAT_ENTRY(compat, attr) \
DT_FOREACH_STATUS_OKAY_VARGS(compat, \
MMU_REGION_DT_FLAT_ENTRY, attr)
/**
* @brief Extract ARM64 architecture bits from a DT memory attribute value.
*
* @param dt_attr The DT memory attribute value.
*/
#define _... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_ARM64_ASM_INLINE_H_
#define ZEPHYR_INCLUDE_ARCH_ARM64_ASM_INLINE_H_
/*
* The file must not be included directly
* Include kernel.h instead
*/
#if defined(__GNUC__)
#include <zephyr/arch/arm64/asm_inline_gcc.h>
#else
#include <arch/arm/asm_inlin... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Either public functions or macros or invoked by public functions */
#ifndef ZEPHYR_INCLUDE_ARCH_ARM64_ASM_INLINE_GCC_H_
#define ZEPHYR_INCLUDE_ARCH_ARM64_ASM_INLINE_GCC_H_
/*
* The file must n... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_BARRIER_ARM64_H_ */
<|fim_prefix|>/**
* Copyright (c) 2023 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2.0
*<|fim_middle|>/
#ifndef ZEPHYR_INCLUDE_BARRIER_ARM64_H_
#define ZEPHYR_INCLUDE_BARRIER_ARM64_H_
#ifndef ZEPHYR_INCLUDE_SYS_BARRIER_H_
#error Please include <zephyr/... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2022 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_ARM64_CACHE_H_
#define ZEPHYR_INCLUDE_ARCH_ARM64_CACHE_H_
#ifndef _ASMLANGUAGE
#include <zephyr/types.h>
#include <zephyr/s<|fim_suffix|> invalidate
* K_CACHE_WB: clean
*... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyrigh<|fim_suffix|> NXP Semicondutors
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_ARM64_CFI_H_
#define ZEPHYR_INCLUDE_ARCH_ARM64_CFI_H_
#define ARCH_CFI_UNDEFINED_RETURN_ADDRESS() __asm__ volatile(".cfi_undefined lr")
#endif /* ZEPHYR_INCLUDE_ARCH_ARM64_CFI_H_ */
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 Linaro Limited.
* Copyright (c) 2018 Nordic Semiconductor ASA.
* Copyright (c) 2021-2023 Arm Limited (or its affiliates). All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_ARM64_CORTEX_R_MPU_ARM_MPU_H_
#define ZEPHYR_INCLUDE_ARCH_ARM6... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>GIR_TGT_MASK (0xffff)
#define SGIR_AFF1_SHIFT (16)
#define SGIR_AFF2_SHIFT (32)
#define SGIR_AFF3_SHIFT (48)
#define SGIR_AFF_MASK (0xff)
#define SGIR_INTID_SHIFT (24)
#define SGIR_INTID_MASK (0xf)
#define SGIR_IRM_SHIFT (40)
#define SGIR_IRM_MASK (0x1)
#define SGIR_IRM_TO_AFF (0)
#define GICV3_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ARM AArch64 public error handling
*
* ARM AArch64-specific kernel error handling interface. Incl<|fim_suffix|>h.h.
*/
#ifndef ZEPHYR_INCLUDE_ARCH_ARM64_ERROR_H_
#define ZE... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>EPTION_H_
#define ZEPHYR_INCLUDE_ARCH_ARM64_EXCEPTION_H_
/* for assembler, only works with constants */
#ifdef _ASMLANGUAGE
#else
#include <zephyr/types.h>
#ifdef __cplusplus
extern "C" {
#endif
struct arch_esf {
uint64_t x0;
uint64_t x1;
uint64_t x2;
uint64_t x3;
uint64_t x4;
uint64_t x5;
uint... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>YPERVISOR_dm_op(domid_t domid, unsigned int nr_bufs, struct xen_dm_op_buf *bufs);
int HYPERVISOR_xen_version(int op, void *param);
#ifdef CONFIG_XEN_DOM0
int HYPERVISOR_domctl(void *param);
int HYPERVISOR_sysctl(void *param);
#endif
#endif /* ZEPHYR_INCLUDE_ARCH_ARM64_HYPERCALL_H_ */
<|fim_prefix|>/* SP... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>on with the interrupt's
* parameters, which will then be used by gen_irq_tables.py to create
* the vector table and the software ISR table. This is all done at
* build-time.
*
* We additionally set the priority in the interrupt controller at
* runtime.
*/
#define ARCH_IRQ_CONNECT(irq_p, priority_p,... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_ARM64_LIB_HELPERS_H_
#define ZEPHYR_INCLUDE_ARCH_<|fim_suffix|>v) : "memory")
#define wfit(v) __asm__ volatile("msr S0_3_C1_C0_1, %0" :: "r"(v) : "memory")
static inline... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2<|fim_suffix|>UDE_ARCH_ARM64_MISC_H_
#define ZEPHYR_INCLUDE_ARCH_ARM64_MISC_H_
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _ASMLANGUAGE
extern uint32_t sys_clock_cycle_get_32(void);
static inline uint... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_ARM64_MM_H_
#define ZEPHYR_INCLUDE_ARCH_ARM64_MM_H_
#if defined(CONFIG_ARM_MMU)
#include <zephyr/arch/arm64/arm_mmu.h>
/*
* When mmu enabled, some sect... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 BayLibre SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ARM64 Pointer Authentication (PAC) internal APIs
*
* Internal kernel APIs for PAC key management. Not for application use.
*/
#ifndef ZEPHYR_INCLUDE_ARCH_ARM64_PAC_H_
#define ZEPHYR_INCLUDE_ARCH... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ack pointer when stack overflow, else 0 */
uint64_t corrupted_sp;
#endif
};
#endif /* ZEPHYR_INCLUDE_ARM64_STRUCTS_H_ */
<|fim_prefix|>/*
* Copyright (c) BayLibre SAS
*
* SPDX-License-Identifier<|fim_middle|>: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARM64_STRUCTS_H_
#define ZEPHYR_INCLUDE_ARM64_STRUCT... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> (addr));
}
static ALWAYS_INLINE uint16_t sys_read16(mem_addr_t addr)
{
uint16_t val;
__asm__ volatile("ldrh %w0, [%1]" : "=r" (val) : "r" (addr));
barrier_dmem_fence_full();
return val;
}
static ALWAYS_INLINE void sys_write16(uint16_t data, mem_addr_t addr)
{
barrier_dmem_fence_full();
__asm__ ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
: [svid] "i" (_SVC_CALL_SYSTEM_CALL),
"r" (ret), "r" (r1), "r" (r8)
: "memory");
return ret;
}
static inline uintptr_t arch_syscall_invoke1(uintptr_t arg1,
uintptr_t call_id)
{
register uint64_t ret __asm__("x0") = arg1;
register uint64_t r8 __asm__("x8") = call_id;
__asm__... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>tion_depth;
/* Keep large structures at the end to avoid offset issues */
#ifdef CONFIG_FPU_SHARING
struct z_arm64_fp_context saved_fp_context;
#endif
#ifdef CONFIG_ARM_PAC_PER_THREAD
struct pac_keys pac_keys;
#endif
};
typedef struct _thread_arch _thread_arch_t;
#endif /* _ASMLANGUAGE */
#endif /* ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 Carlo Caione <ccaione@baylibre.com>
*
* SP<|fim_suffix|>---------------+ <- thread stack limit (update on every context switch)
* | Stack guard | } Z_ARM64_STACK_GUARD_SIZE (protected by MMU/MPU)
* +-------------------+ <- thread.stack_obj
*
* Low Memory addresses
*/
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>}
static ALWAYS_INLINE void arm_arch_timer_set_irq_mask(bool mask)
{
uint64_t cntv_ctl;
cntv_ctl = read_cntv_ctl_el0();
if (mask) {
cntv_ctl |= CNTV_CTL_IMASK_BIT;
} else {
cntv_ctl &= ~CNTV_CTL_IMASK_BIT;
}
write_cntv_ctl_el0(cntv_ctl);
}
static ALWAYS_INLINE uint64_t arm_arch_timer_count(... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>L0_H_ */
<|fim_prefix|>/*
* Copyright (c) 2021 BayLibre SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief tpidrro_el0 bits allocation
*
* Among other things, the tpidrro_el0 holds the address for the current
* CPU's struct _cpu instance. But such a pointer is at least 8-bytes
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>lush_and_invd_all(void);
#define cache_instr_flush_and_invd_all arch_icache_flush_and_invd_all
/**
* @brief Flush an address range in the i-cache
*
* Flush the specified address range of the instruction cache.
*
* @note the cache operations act on cache line. When multiple data structures
* ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 NXP Semicondutors
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* DWARF Control Flow Integrity (CFI) support for architectures.
*/
#ifndef ZEPHYR_INCLUDE_CFI_H_
#define ZEPHYR_INCLUDE_CFI_H_
#include <zephyr/arch/arch_interface.h>
#if defined(__GNUC__) || defined(__clang_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_t;
typedef void *vaddr_t;
#endif
#endif /* ZEPHYR_INCLUDE_ARCH_X86_ADDR_TYPES_H_ */
<|fim_prefix|>/* x86 address types (virtual, physical, etc) definitions */
/*
* Copyright (c) 2015 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_<|fim_middle|>INCLUDE_ARCH_X86_A... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
void *start;
void *end;
void *fixup;
};
#define Z_EXC_HANDLE(name) \
{ name ## _fault_start, name ## _fault_end, name ## _fixup }
#define Z_EXC_DECLARE(name) \
void name ## _fault_start(void); \
void name ## _fault_end(void); \
void name ## _fixup(void)
#endif /* ZEPHYR_INCLUDE_EXC_H... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2015, Wind River Systems, Inc.
* Copyright (c) 2017, Oticon A/S
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_COMMON_FFS_H_
#define ZEPHYR_INCLUDE_ARCH_COMMON_FFS_H_
#ifndef _ASMLANGUAGE
#include <zephyr/types.h>
#include <zephyr/toolchain.h>
#ifdef __c... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/**
* SPDX-License-Identifier: Apache-2.0
* Copyright The Zephyr Project Contributors
<|fim_suffix|>ON_INIT_H_
#define ZEPHYR_ARCH_COMMON_INIT_H_
FUNC_NORETURN void z_cstart(void);
/* Early boot functions */
void arch_early_memset(void *dst, int c, size_t n);
void arch_early_memcpy(void *dst, const v... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>(pm_s2ram_system_off_fn_t system_off);
/**
* @brief Mark that core is entering suspend-to-RAM state.
*
* Function is called when system state is stored to RAM, just before going to system
* off.
*
* Default implementation is setting a magic word in RAM used if
* CONFIG_HAS_PM_S2RAM_CUSTOM_MARKING ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022, Commonwealth Scientific and Industrial Research
* Organisation (CSIRO) ABN 41 687 119 230.
*
* SPDX-License-Identifier: Apache-2.0
*
* Based on the ARM semihosting API from:
* https://github.com/ARM-software/abi-aa/blob/main/semihosting/semihosting.rst
*
* RISC-V semihost... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020, Wind River Systems, Inc.
* Copyright (c) 2017, Oticon A/S
* Copyrigh<|fim_suffix|>_
#ifndef _ASMLANGUAGE
#include <zephyr/toolchain.h>
#include <zephyr/types.h>
#include <zephyr/sys/sys_io.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @cond INTERNAL_HIDDEN
* Memory bits... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2015, Wind River Systems, Inc.
* Copyright (c) 2017, Oticon A/S
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Memory mapped registers I/O functions in non-arch-specific C code */
#ifndef ZEPHYR_INCLUDE_ARCH_COMMON_SYS_IO_H_
#define ZEPHYR_INCLUDE_ARCH_COMMON_SYS_IO_H_
#ifndef _A... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>fine ZEPHYR_ARCH_INCLUDE_XIP_H_
#ifndef _ASMLANGUAGE
#ifdef __cplusplus
extern "C" {
#endif
#ifdef CONFIG_XIP
void arch_data_copy(void);
#else
static inline void arch_data_copy(void)
{
/* Do nothing */
}
#endif /* CONFIG_XIP */
#ifdef __cplusplus
}
#endif
#endif /* _ASMLANGUAGE */
#endif /* ZEPHYR_ARC... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ARM64)
#include <zephyr/arch/arm64/arch.h>
#elif defined(CONFIG_ARM)
#include <zephyr/arch/arm/arch.h>
#elif defined(CONFIG_ARC)
#include <zephyr/arch/arc/arch.h>
#elif defined(CONFIG_RISCV)
#include <zephyr/arch/riscv/arch.h>
#elif defined(CONFIG_XTENSA)
#include <zephyr/arch/xtensa/arch.h>
#elif defined... | fim | zephyrproject-rtos/zephyr | c |
/* exception.h - automatically selects the correct exception.h file to include */
/*
* Copyright (c) 2024 Meta Platforms
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_EXCEPTION_H_
#define ZEPHYR_INCLUDE_ARCH_EXCEPTION_H_
#ifndef _ASMLANGUAGE
#if defined(CONFIG_EXCEPTION_DUMP_HOOK)
#includ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>void arch_irq_unlock(unsigned int key)
{
uint32_t status = read_c0_status();
if (key) {
status |= ST0_IE;
} else {
status &= ~ST0_IE;
}
write_c0_status(status);
}
static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key)
{
return key != 0;
}
/** Implementation of @ref arch_cpu_irqs_are_e... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/<|fim_suffix|>ine ZEPHYR_INCLUDE_ARCH_MIPS_ARCH_INLINES_H
#include <zephyr/kernel_structs.h>
static ALWAYS_INLINE unsigned int arch_num_cpus(void)
{
return CONFIG_MP_MAX_NUM_CPUS;
}
#endif /* ZEPHYR_INCLUDE_ARCH_MI... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> value */
unsigned long v1; /* return value */
unsigned long at; /* assembly temporary */
unsigned long epc;
unsigned long badvaddr;
unsigned long hi;
unsigned long lo;
unsigned long status;
unsigned long cause;
};
#ifdef __cplusplus
}
#endif
#endif /* _ASMLANGUAGE */
#endif /* ZEPHYR_INCLU... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>arch_t;
#endif /* _ASMLANGUAGE */
#endif /* ZEPHYR_INCLUDE_ARCH_MIPS_THREAD_H_ */
<|fim_prefix|>/*
* Copyright (c) 2020 Antony Pavlov <antonynpavlov@gmail.com>
*
* based on include/arch/riscv/thread.h
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Per-arch thread definition
*
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025<|fim_suffix|>d time.
*
* @param irq_p IRQ line number
* @param priority_p Interrupt priority
* @param isr_p Interrupt service routine
* @param isr_param_p ISR parameter
* @param flags_p IRQ options
*
* @return The vector assigned to this interrupt
*/
#define ARCH_IRQ_CON... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2025 NVIDIA Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief OpenRISC arch-specific inline function implementations.
*/
#ifndef ZEPHYR_INCLUDE_ARCH_OPENRISC_ARCH_INLINES_H
#define ZEPHYR_INCLUDE_ARCH_OPENRISC_ARCH_INLINES_H
#include <zephyr/kernel_structs.h>
stat... | fim | zephyrproject-rtos/zephyr | c |
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