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You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include<iostream> #include<string> #include<hip/hip_runtime.h> using namespace std; int main(){ struct hipDeviceProp_t prop; hipError_t err; err = hipGetDeviceProperties(&prop,0); if(err!=hipSuccess){ cout<<"Get failed. Exiting."<<endl; } else{ cout<<"Name : "<<string(prop.name)<<endl; cout<<"Total global memory : "<<prop.totalGlobalMem/(1024*1024*1024.0)<<" GB"<<endl; cout<<"Shared memmory per block : "<<prop.sharedMemPerBlock/(1024.0)<<" KB"<<endl; cout<<"32 bit registers per block : "<<prop.regsPerBlock<<endl; cout<<"Warp size (in threads) : "<<prop.warpSize<<endl; cout<<"Max pitch allowed by mem copy : "<<prop.memPitch/(1024*1024*1024.0)<<" GB"<<endl; cout<<"Max threads per block : "<<prop.maxThreadsPerBlock<<endl; cout<<"Max thread dimensions : "<<"("<<prop.maxThreadsDim[0]<<","<<prop.maxThreadsDim[1]<<","<<prop.maxThreadsDim[2]<<")"<<endl; cout<<"Max grid dimensions : "<<"("<<prop.maxGridSize[0]<<","<<prop.maxGridSize[1]<<","<<prop.maxGridSize[2]<<")"<<endl; cout<<"Max const memory : "<<prop.totalConstMem/1024.0<<" KB"<<endl; cout<<"Major compute capability : "<<prop.major<<endl; cout<<"Minor compute capability : "<<prop.minor<<endl; cout<<"Clock frequency : "<<prop.clockRate/1000.0<<" MHz"<<endl; cout<<"Alignment requirement for textures : "<<prop.textureAlignment<<endl; cout<<"Device can concurrently copy memory and execute a kernel : "<<(bool)prop.deviceOverlap<<endl; cout<<"Number of multiprocessors on device : "<<prop.multiProcessorCount<<endl; cout<<"Specified whether there is a run time limit on kernels : "<<(bool)prop.kernelExecTimeoutEnabled<<endl; cout<<"Integrated : "<<(bool)prop.integrated<<endl; cout<<"Can map host memory : "<<(bool)prop.canMapHostMemory<<endl; cout<<"Compute Mode : "<<prop.computeMode<<endl; cout<<"Concurrent kernels : "<<(bool)prop.concurrentKernels<<endl; cout<<"ECC support : "<<(bool)prop.ECCEnabled<<endl; cout<<"PCI bus id : "<<prop.pciBusID<<endl; cout<<"PCI device id : "<<prop.pciDeviceID<<endl; cout<<"TCC Driver : "<<(bool)prop.tccDriver<<endl; } return 0; }
.text .file "test2.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .section .rodata.cst16,"aM",@progbits,16 .p2align 4, 0x0 # -- Begin function main .LCPI0_0: .long 1127219200 # 0x43300000 .long 1160773632 # 0x45300000 .long 0 # 0x0 .long 0 # 0x0 .LCPI0_1: .quad 0x4330000000000000 # double 4503599627370496 .quad 0x4530000000000000 # double 1.9342813113834067E+25 .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 .LCPI0_2: .quad 0x3e10000000000000 # double 9.3132257461547852E-10 .LCPI0_3: .quad 0x3f50000000000000 # double 9.765625E-4 .LCPI0_4: .quad 0x408f400000000000 # double 1000 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .Lfunc_begin0: .cfi_startproc .cfi_personality 3, __gxx_personality_v0 .cfi_lsda 3, .Lexception0 # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 subq $1504, %rsp # imm = 0x5E0 .cfi_def_cfa_offset 1536 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 32(%rsp), %rdi xorl %esi, %esi callq hipGetDevicePropertiesR0600 movl $_ZSt4cout, %edi testl %eax, %eax je .LBB0_7 # %bb.1: movl $.L.str, %esi movl $20, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %rbx testq %rbx, %rbx je .LBB0_127 # %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%rbx) je .LBB0_4 # %bb.3: movzbl 67(%rbx), %eax jmp .LBB0_5 .LBB0_7: movl $.L.str.1, %esi movl $11, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l leaq 16(%rsp), %r15 movq %r15, (%rsp) leaq 32(%rsp), %rdi callq strlen movq %rax, %rbx cmpq $16, %rax jb .LBB0_11 # %bb.8: testq %rbx, %rbx js .LBB0_128 # %bb.9: movq %rbx, %rdi incq %rdi js .LBB0_129 # %bb.10: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i callq _Znwm movq %rax, (%rsp) movq %rbx, 16(%rsp) .LBB0_11: testq %rbx, %rbx je .LBB0_15 # %bb.12: movq (%rsp), %rdi cmpq $1, %rbx jne .LBB0_14 # %bb.13: movzbl 32(%rsp), %eax movb %al, (%rdi) jmp .LBB0_15 .LBB0_4: movq %rbx, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) .LBB0_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit movsbl %al, %esi movl $_ZSt4cout, %edi jmp .LBB0_6 .LBB0_14: leaq 32(%rsp), %rsi movq %rbx, %rdx callq memcpy@PLT .LBB0_15: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit movq %rbx, 8(%rsp) movq (%rsp), %rax movb $0, (%rax,%rbx) movq (%rsp), %rsi movq 8(%rsp), %rdx .Ltmp0: movl $_ZSt4cout, %edi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Ltmp1: # %bb.16: # %_ZStlsIcSt11char_traitsIcESaIcEERSt13basic_ostreamIT_T0_ES7_RKNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit movq %rax, %rbx movq (%rax), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %r14 testq %r14, %r14 je .LBB0_17 # %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i12 cmpb $0, 56(%r14) je .LBB0_21 # %bb.20: movzbl 67(%r14), %eax jmp .LBB0_23 .LBB0_21: .Ltmp2: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv .Ltmp3: # %bb.22: # %.noexc16 movq (%r14), %rax .Ltmp4: movq %r14, %rdi movl $10, %esi callq *48(%rax) .Ltmp5: .LBB0_23: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i .Ltmp6: movsbl %al, %esi movq %rbx, %rdi callq _ZNSo3putEc .Ltmp7: # %bb.24: # %.noexc18 .Ltmp8: movq %rax, %rdi callq _ZNSo5flushEv .Ltmp9: # %bb.25: # %_ZNSolsEPFRSoS_E.exit movq (%rsp), %rdi cmpq %r15, %rdi je .LBB0_27 # %bb.26: # %.critedge.i.i callq _ZdlPv .LBB0_27: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit movl $_ZSt4cout, %edi movl $.L.str.2, %esi movl $26, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movsd 320(%rsp), %xmm1 # xmm1 = mem[0],zero unpcklps .LCPI0_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1] subpd .LCPI0_1(%rip), %xmm1 movapd %xmm1, %xmm0 unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1] addsd %xmm1, %xmm0 mulsd .LCPI0_2(%rip), %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %rbx movl $.L.str.3, %esi movl $3, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq (%rbx), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %r14 testq %r14, %r14 je .LBB0_127 # %bb.28: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i22 cmpb $0, 56(%r14) je .LBB0_30 # %bb.29: movzbl 67(%r14), %eax jmp .LBB0_31 .LBB0_30: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB0_31: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit26 movsbl %al, %esi movq %rbx, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.4, %esi movl $31, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movsd 328(%rsp), %xmm1 # xmm1 = mem[0],zero unpcklps .LCPI0_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1] subpd .LCPI0_1(%rip), %xmm1 movapd %xmm1, %xmm0 unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1] addsd %xmm1, %xmm0 mulsd .LCPI0_3(%rip), %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %rbx movl $.L.str.5, %esi movl $3, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq (%rbx), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %r14 testq %r14, %r14 je .LBB0_127 # %bb.32: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i28 cmpb $0, 56(%r14) je .LBB0_34 # %bb.33: movzbl 67(%r14), %eax jmp .LBB0_35 .LBB0_34: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB0_35: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit32 movsbl %al, %esi movq %rbx, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.6, %esi movl $33, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl 336(%rsp), %esi movl $_ZSt4cout, %edi callq _ZNSolsEi movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %rbx testq %rbx, %rbx je .LBB0_127 # %bb.36: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i34 cmpb $0, 56(%rbx) je .LBB0_38 # %bb.37: movzbl 67(%rbx), %ecx jmp .LBB0_39 .LBB0_38: movq %rbx, %rdi movq %rax, %r14 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r14, %rax .LBB0_39: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit38 movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.7, %esi movl $29, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl 340(%rsp), %esi movl $_ZSt4cout, %edi callq _ZNSolsEi movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %rbx testq %rbx, %rbx je .LBB0_127 # %bb.40: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i40 cmpb $0, 56(%rbx) je .LBB0_42 # %bb.41: movzbl 67(%rbx), %ecx jmp .LBB0_43 .LBB0_42: movq %rbx, %rdi movq %rax, %r14 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r14, %rax .LBB0_43: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit44 movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.8, %esi movl $36, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movsd 344(%rsp), %xmm1 # xmm1 = mem[0],zero unpcklps .LCPI0_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1] subpd .LCPI0_1(%rip), %xmm1 movapd %xmm1, %xmm0 unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1] addsd %xmm1, %xmm0 mulsd .LCPI0_2(%rip), %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %rbx movl $.L.str.3, %esi movl $3, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq (%rbx), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %r14 testq %r14, %r14 je .LBB0_127 # %bb.44: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i46 cmpb $0, 56(%r14) je .LBB0_46 # %bb.45: movzbl 67(%r14), %eax jmp .LBB0_47 .LBB0_46: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB0_47: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit50 movsbl %al, %esi movq %rbx, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.9, %esi movl $28, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl 352(%rsp), %esi movl $_ZSt4cout, %edi callq _ZNSolsEi movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %rbx testq %rbx, %rbx je .LBB0_127 # %bb.48: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i52 cmpb $0, 56(%rbx) je .LBB0_50 # %bb.49: movzbl 67(%rbx), %ecx jmp .LBB0_51 .LBB0_50: movq %rbx, %rdi movq %rax, %r14 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r14, %rax .LBB0_51: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit56 movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.10, %esi movl $28, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi movl $.L.str.11, %esi movl $1, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl 356(%rsp), %esi movl $_ZSt4cout, %edi callq _ZNSolsEi movq %rax, %rbx movl $.L.str.12, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl 360(%rsp), %esi movq %rbx, %rdi callq _ZNSolsEi movq %rax, %rbx movl $.L.str.12, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl 364(%rsp), %esi movq %rbx, %rdi callq _ZNSolsEi movq %rax, %rbx movl $.L.str.13, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq (%rbx), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %r14 testq %r14, %r14 je .LBB0_127 # %bb.52: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i58 cmpb $0, 56(%r14) je .LBB0_54 # %bb.53: movzbl 67(%r14), %eax jmp .LBB0_55 .LBB0_54: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB0_55: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit62 movsbl %al, %esi movq %rbx, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.14, %esi movl $26, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi movl $.L.str.11, %esi movl $1, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl 368(%rsp), %esi movl $_ZSt4cout, %edi callq _ZNSolsEi movq %rax, %rbx movl $.L.str.12, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl 372(%rsp), %esi movq %rbx, %rdi callq _ZNSolsEi movq %rax, %rbx movl $.L.str.12, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl 376(%rsp), %esi movq %rbx, %rdi callq _ZNSolsEi movq %rax, %rbx movl $.L.str.13, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq (%rbx), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %r14 testq %r14, %r14 je .LBB0_127 # %bb.56: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i64 cmpb $0, 56(%r14) je .LBB0_58 # %bb.57: movzbl 67(%r14), %eax jmp .LBB0_59 .LBB0_58: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB0_59: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit68 movsbl %al, %esi movq %rbx, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.15, %esi movl $23, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movsd 384(%rsp), %xmm1 # xmm1 = mem[0],zero unpcklps .LCPI0_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1] subpd .LCPI0_1(%rip), %xmm1 movapd %xmm1, %xmm0 unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1] addsd %xmm1, %xmm0 mulsd .LCPI0_3(%rip), %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %rbx movl $.L.str.5, %esi movl $3, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq (%rbx), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %r14 testq %r14, %r14 je .LBB0_127 # %bb.60: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i70 cmpb $0, 56(%r14) je .LBB0_62 # %bb.61: movzbl 67(%r14), %eax jmp .LBB0_63 .LBB0_62: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB0_63: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit74 movsbl %al, %esi movq %rbx, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.16, %esi movl $31, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl 392(%rsp), %esi movl $_ZSt4cout, %edi callq _ZNSolsEi movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %rbx testq %rbx, %rbx je .LBB0_127 # %bb.64: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i76 cmpb $0, 56(%rbx) je .LBB0_66 # %bb.65: movzbl 67(%rbx), %ecx jmp .LBB0_67 .LBB0_66: movq %rbx, %rdi movq %rax, %r14 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r14, %rax .LBB0_67: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit80 movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.17, %esi movl $31, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl 396(%rsp), %esi movl $_ZSt4cout, %edi callq _ZNSolsEi movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %rbx testq %rbx, %rbx je .LBB0_127 # %bb.68: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i82 cmpb $0, 56(%rbx) je .LBB0_70 # %bb.69: movzbl 67(%rbx), %ecx jmp .LBB0_71 .LBB0_70: movq %rbx, %rdi movq %rax, %r14 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r14, %rax .LBB0_71: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit86 movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.18, %esi movl $22, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l cvtsi2sdl 380(%rsp), %xmm0 divsd .LCPI0_4(%rip), %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %rbx movl $.L.str.19, %esi movl $4, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq (%rbx), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %r14 testq %r14, %r14 je .LBB0_127 # %bb.72: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i88 cmpb $0, 56(%r14) je .LBB0_74 # %bb.73: movzbl 67(%r14), %eax jmp .LBB0_75 .LBB0_74: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB0_75: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit92 movsbl %al, %esi movq %rbx, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.20, %esi movl $41, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq 400(%rsp), %rsi movl $_ZSt4cout, %edi callq _ZNSo9_M_insertImEERSoT_ movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %rbx testq %rbx, %rbx je .LBB0_127 # %bb.76: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i94 cmpb $0, 56(%rbx) je .LBB0_78 # %bb.77: movzbl 67(%rbx), %ecx jmp .LBB0_79 .LBB0_78: movq %rbx, %rdi movq %rax, %r14 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r14, %rax .LBB0_79: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit98 movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.21, %esi movl $63, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorl %esi, %esi cmpl $0, 416(%rsp) setne %sil movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIbEERSoT_ movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %rbx testq %rbx, %rbx je .LBB0_127 # %bb.80: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i100 cmpb $0, 56(%rbx) je .LBB0_82 # %bb.81: movzbl 67(%rbx), %ecx jmp .LBB0_83 .LBB0_82: movq %rbx, %rdi movq %rax, %r14 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r14, %rax .LBB0_83: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit104 movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.22, %esi movl $42, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl 420(%rsp), %esi movl $_ZSt4cout, %edi callq _ZNSolsEi movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %rbx testq %rbx, %rbx je .LBB0_127 # %bb.84: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i106 cmpb $0, 56(%rbx) je .LBB0_86 # %bb.85: movzbl 67(%rbx), %ecx jmp .LBB0_87 .LBB0_86: movq %rbx, %rdi movq %rax, %r14 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r14, %rax .LBB0_87: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit110 movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.23, %esi movl $61, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorl %esi, %esi cmpl $0, 424(%rsp) setne %sil movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIbEERSoT_ movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %rbx testq %rbx, %rbx je .LBB0_127 # %bb.88: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i112 cmpb $0, 56(%rbx) je .LBB0_90 # %bb.89: movzbl 67(%rbx), %ecx jmp .LBB0_91 .LBB0_90: movq %rbx, %rdi movq %rax, %r14 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r14, %rax .LBB0_91: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit116 movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.24, %esi movl $17, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorl %esi, %esi cmpl $0, 428(%rsp) setne %sil movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIbEERSoT_ movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %rbx testq %rbx, %rbx je .LBB0_127 # %bb.92: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i118 cmpb $0, 56(%rbx) je .LBB0_94 # %bb.93: movzbl 67(%rbx), %ecx jmp .LBB0_95 .LBB0_94: movq %rbx, %rdi movq %rax, %r14 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r14, %rax .LBB0_95: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit122 movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.25, %esi movl $26, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorl %esi, %esi cmpl $0, 432(%rsp) setne %sil movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIbEERSoT_ movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %rbx testq %rbx, %rbx je .LBB0_127 # %bb.96: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i124 cmpb $0, 56(%rbx) je .LBB0_98 # %bb.97: movzbl 67(%rbx), %ecx jmp .LBB0_99 .LBB0_98: movq %rbx, %rdi movq %rax, %r14 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r14, %rax .LBB0_99: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit128 movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.26, %esi movl $19, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl 436(%rsp), %esi movl $_ZSt4cout, %edi callq _ZNSolsEi movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %rbx testq %rbx, %rbx je .LBB0_127 # %bb.100: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i130 cmpb $0, 56(%rbx) je .LBB0_102 # %bb.101: movzbl 67(%rbx), %ecx jmp .LBB0_103 .LBB0_102: movq %rbx, %rdi movq %rax, %r14 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r14, %rax .LBB0_103: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit134 movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.27, %esi movl $25, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorl %esi, %esi cmpl $0, 608(%rsp) setne %sil movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIbEERSoT_ movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %rbx testq %rbx, %rbx je .LBB0_127 # %bb.104: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i136 cmpb $0, 56(%rbx) je .LBB0_106 # %bb.105: movzbl 67(%rbx), %ecx jmp .LBB0_107 .LBB0_106: movq %rbx, %rdi movq %rax, %r14 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r14, %rax .LBB0_107: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit140 movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.28, %esi movl $18, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorl %esi, %esi cmpl $0, 612(%rsp) setne %sil movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIbEERSoT_ movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %rbx testq %rbx, %rbx je .LBB0_127 # %bb.108: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i142 cmpb $0, 56(%rbx) je .LBB0_110 # %bb.109: movzbl 67(%rbx), %ecx jmp .LBB0_111 .LBB0_110: movq %rbx, %rdi movq %rax, %r14 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r14, %rax .LBB0_111: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit146 movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.29, %esi movl $17, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl 616(%rsp), %esi movl $_ZSt4cout, %edi callq _ZNSolsEi movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %rbx testq %rbx, %rbx je .LBB0_127 # %bb.112: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i148 cmpb $0, 56(%rbx) je .LBB0_114 # %bb.113: movzbl 67(%rbx), %ecx jmp .LBB0_115 .LBB0_114: movq %rbx, %rdi movq %rax, %r14 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r14, %rax .LBB0_115: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit152 movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.30, %esi movl $20, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl 620(%rsp), %esi movl $_ZSt4cout, %edi callq _ZNSolsEi movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %rbx testq %rbx, %rbx je .LBB0_127 # %bb.116: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i154 cmpb $0, 56(%rbx) je .LBB0_118 # %bb.117: movzbl 67(%rbx), %ecx jmp .LBB0_119 .LBB0_118: movq %rbx, %rdi movq %rax, %r14 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r14, %rax .LBB0_119: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit158 movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $_ZSt4cout, %edi movl $.L.str.31, %esi movl $17, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorl %esi, %esi cmpl $0, 628(%rsp) setne %sil movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIbEERSoT_ movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %rbx testq %rbx, %rbx je .LBB0_127 # %bb.120: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i160 cmpb $0, 56(%rbx) je .LBB0_122 # %bb.121: movzbl 67(%rbx), %ecx jmp .LBB0_123 .LBB0_122: movq %rbx, %rdi movq %rax, %r14 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r14, %rax .LBB0_123: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit164 movsbl %cl, %esi movq %rax, %rdi .LBB0_6: callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv xorl %eax, %eax addq $1504, %rsp # imm = 0x5E0 .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .LBB0_129: # %.noexc11.i .cfi_def_cfa_offset 1536 callq _ZSt17__throw_bad_allocv .LBB0_127: callq _ZSt16__throw_bad_castv .LBB0_17: .Ltmp10: callq _ZSt16__throw_bad_castv .Ltmp11: # %bb.18: # %.noexc15 .LBB0_128: # %.noexc.i movl $.L.str.33, %edi callq _ZSt20__throw_length_errorPKc .LBB0_124: .Ltmp12: movq %rax, %rbx movq (%rsp), %rdi cmpq %r15, %rdi je .LBB0_126 # %bb.125: # %.critedge.i.i8 callq _ZdlPv .LBB0_126: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit10 movq %rbx, %rdi callq _Unwind_Resume@PLT .Lfunc_end0: .size main, .Lfunc_end0-main .cfi_endproc .section .gcc_except_table,"a",@progbits .p2align 2, 0x0 GCC_except_table0: .Lexception0: .byte 255 # @LPStart Encoding = omit .byte 255 # @TType Encoding = omit .byte 1 # Call site Encoding = uleb128 .uleb128 .Lcst_end0-.Lcst_begin0 .Lcst_begin0: .uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 << .uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 << .uleb128 .Ltmp9-.Ltmp0 # Call between .Ltmp0 and .Ltmp9 .uleb128 .Ltmp12-.Lfunc_begin0 # jumps to .Ltmp12 .byte 0 # On action: cleanup .uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 3 << .uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10 .byte 0 # has no landing pad .byte 0 # On action: cleanup .uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 4 << .uleb128 .Ltmp11-.Ltmp10 # Call between .Ltmp10 and .Ltmp11 .uleb128 .Ltmp12-.Lfunc_begin0 # jumps to .Ltmp12 .byte 0 # On action: cleanup .uleb128 .Ltmp11-.Lfunc_begin0 # >> Call Site 5 << .uleb128 .Lfunc_end0-.Ltmp11 # Call between .Ltmp11 and .Lfunc_end0 .byte 0 # has no landing pad .byte 0 # On action: cleanup .Lcst_end0: .p2align 2, 0x0 # -- End function .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Get failed. Exiting." .size .L.str, 21 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Name : " .size .L.str.1, 12 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Total global memory : " .size .L.str.2, 27 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz " GB" .size .L.str.3, 4 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Shared memmory per block : " .size .L.str.4, 32 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz " KB" .size .L.str.5, 4 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "32 bit registers per block : " .size .L.str.6, 34 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "Warp size (in threads) : " .size .L.str.7, 30 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "Max pitch allowed by mem copy : " .size .L.str.8, 37 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "Max threads per block : " .size .L.str.9, 29 .type .L.str.10,@object # @.str.10 .L.str.10: .asciz "Max thread dimensions : " .size .L.str.10, 29 .type .L.str.11,@object # @.str.11 .L.str.11: .asciz "(" .size .L.str.11, 2 .type .L.str.12,@object # @.str.12 .L.str.12: .asciz "," .size .L.str.12, 2 .type .L.str.13,@object # @.str.13 .L.str.13: .asciz ")" .size .L.str.13, 2 .type .L.str.14,@object # @.str.14 .L.str.14: .asciz "Max grid dimensions : " .size .L.str.14, 27 .type .L.str.15,@object # @.str.15 .L.str.15: .asciz "Max const memory : " .size .L.str.15, 24 .type .L.str.16,@object # @.str.16 .L.str.16: .asciz "Major compute capability : " .size .L.str.16, 32 .type .L.str.17,@object # @.str.17 .L.str.17: .asciz "Minor compute capability : " .size .L.str.17, 32 .type .L.str.18,@object # @.str.18 .L.str.18: .asciz "Clock frequency : " .size .L.str.18, 23 .type .L.str.19,@object # @.str.19 .L.str.19: .asciz " MHz" .size .L.str.19, 5 .type .L.str.20,@object # @.str.20 .L.str.20: .asciz "Alignment requirement for textures : " .size .L.str.20, 42 .type .L.str.21,@object # @.str.21 .L.str.21: .asciz "Device can concurrently copy memory and execute a kernel : " .size .L.str.21, 64 .type .L.str.22,@object # @.str.22 .L.str.22: .asciz "Number of multiprocessors on device : " .size .L.str.22, 43 .type .L.str.23,@object # @.str.23 .L.str.23: .asciz "Specified whether there is a run time limit on kernels : " .size .L.str.23, 62 .type .L.str.24,@object # @.str.24 .L.str.24: .asciz "Integrated : " .size .L.str.24, 18 .type .L.str.25,@object # @.str.25 .L.str.25: .asciz "Can map host memory : " .size .L.str.25, 27 .type .L.str.26,@object # @.str.26 .L.str.26: .asciz "Compute Mode : " .size .L.str.26, 20 .type .L.str.27,@object # @.str.27 .L.str.27: .asciz "Concurrent kernels : " .size .L.str.27, 26 .type .L.str.28,@object # @.str.28 .L.str.28: .asciz "ECC support : " .size .L.str.28, 19 .type .L.str.29,@object # @.str.29 .L.str.29: .asciz "PCI bus id : " .size .L.str.29, 18 .type .L.str.30,@object # @.str.30 .L.str.30: .asciz "PCI device id : " .size .L.str.30, 21 .type .L.str.31,@object # @.str.31 .L.str.31: .asciz "TCC Driver : " .size .L.str.31, 18 .type .L.str.33,@object # @.str.33 .L.str.33: .asciz "basic_string::_M_create" .size .L.str.33, 24 .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __gxx_personality_v0 .addrsig_sym _Unwind_Resume .addrsig_sym _ZSt4cout .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80
.text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .amdgpu_metadata --- amdhsa.kernels: [] amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include "includes.h" __global__ void windowKernel(float* idata, float* window, int width, int height) { int tidx = threadIdx.x + blockIdx.x*blockDim.x; int tidy = threadIdx.y + blockIdx.y*blockDim.y; if(tidx < width && tidy < height) { idata[tidy * width + tidx] = window[tidx] * idata[tidy * width + tidx]; } }
code for sm_80 Function : _Z12windowKernelPfS_ii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */ /* 0x000e280000002600 */ /*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */ /* 0x000e280000002200 */ /*0030*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */ /* 0x000e680000002100 */ /*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */ /* 0x000e620000002500 */ /*0050*/ IMAD R3, R3, c[0x0][0x4], R0 ; /* 0x0000010003037a24 */ /* 0x001fca00078e0200 */ /*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */ /* 0x000fe20003f06270 */ /*0070*/ IMAD R2, R5, c[0x0][0x0], R2 ; /* 0x0000000005027a24 */ /* 0x002fca00078e0202 */ /*0080*/ ISETP.GE.OR P0, PT, R2, c[0x0][0x170], P0 ; /* 0x00005c0002007a0c */ /* 0x000fda0000706670 */ /*0090*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */ /* 0x000fe200000001ff */ /*00b0*/ IMAD R4, R3, c[0x0][0x170], R2 ; /* 0x00005c0003047a24 */ /* 0x000fe200078e0202 */ /*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd00000000a00 */ /*00d0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */ /* 0x000fc800078e0205 */ /*00e0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */ /* 0x000fe400078e0205 */ /*00f0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */ /* 0x000ea8000c1e1900 */ /*0100*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */ /* 0x000ea4000c1e1900 */ /*0110*/ FMUL R7, R0, R3 ; /* 0x0000000300077220 */ /* 0x004fca0000400000 */ /*0120*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */ /* 0x000fe2000c101904 */ /*0130*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0140*/ BRA 0x140; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include "includes.h" __global__ void windowKernel(float* idata, float* window, int width, int height) { int tidx = threadIdx.x + blockIdx.x*blockDim.x; int tidy = threadIdx.y + blockIdx.y*blockDim.y; if(tidx < width && tidy < height) { idata[tidy * width + tidx] = window[tidx] * idata[tidy * width + tidx]; } }
.file "tmpxft_000ceb12_00000000-6_windowKernel.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z36__device_stub__Z12windowKernelPfS_iiPfS_ii .type _Z36__device_stub__Z12windowKernelPfS_iiPfS_ii, @function _Z36__device_stub__Z12windowKernelPfS_iiPfS_ii: .LFB2051: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z12windowKernelPfS_ii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z36__device_stub__Z12windowKernelPfS_iiPfS_ii, .-_Z36__device_stub__Z12windowKernelPfS_iiPfS_ii .globl _Z12windowKernelPfS_ii .type _Z12windowKernelPfS_ii, @function _Z12windowKernelPfS_ii: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z36__device_stub__Z12windowKernelPfS_iiPfS_ii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z12windowKernelPfS_ii, .-_Z12windowKernelPfS_ii .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z12windowKernelPfS_ii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z12windowKernelPfS_ii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include "includes.h" __global__ void windowKernel(float* idata, float* window, int width, int height) { int tidx = threadIdx.x + blockIdx.x*blockDim.x; int tidy = threadIdx.y + blockIdx.y*blockDim.y; if(tidx < width && tidy < height) { idata[tidy * width + tidx] = window[tidx] * idata[tidy * width + tidx]; } }
#include <hip/hip_runtime.h> #include "includes.h" __global__ void windowKernel(float* idata, float* window, int width, int height) { int tidx = threadIdx.x + blockIdx.x*blockDim.x; int tidy = threadIdx.y + blockIdx.y*blockDim.y; if(tidx < width && tidy < height) { idata[tidy * width + tidx] = window[tidx] * idata[tidy * width + tidx]; } }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void windowKernel(float* idata, float* window, int width, int height) { int tidx = threadIdx.x + blockIdx.x*blockDim.x; int tidy = threadIdx.y + blockIdx.y*blockDim.y; if(tidx < width && tidy < height) { idata[tidy * width + tidx] = window[tidx] * idata[tidy * width + tidx]; } }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z12windowKernelPfS_ii .globl _Z12windowKernelPfS_ii .p2align 8 .type _Z12windowKernelPfS_ii,@function _Z12windowKernelPfS_ii: s_clause 0x1 s_load_b32 s2, s[0:1], 0x24 s_load_b64 s[4:5], s[0:1], 0x10 v_and_b32_e32 v2, 0x3ff, v0 v_bfe_u32 v4, v0, 10, 10 s_waitcnt lgkmcnt(0) s_and_b32 s3, s2, 0xffff s_lshr_b32 s2, s2, 16 v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3] v_mad_u64_u32 v[2:3], null, s15, s2, v[4:5] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_gt_i32_e32 vcc_lo, s4, v0 v_cmp_gt_i32_e64 s2, s5, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s2, vcc_lo, s2 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_2 v_ashrrev_i32_e32 v1, 31, v0 s_load_b128 s[0:3], s[0:1], 0x0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mad_u64_u32 v[3:4], null, v2, s4, v[0:1] v_lshlrev_b64 v[0:1], 2, v[0:1] v_ashrrev_i32_e32 v4, 31, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_lshlrev_b64 v[2:3], 2, v[3:4] s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s2, v0 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo v_add_co_u32 v2, vcc_lo, s0, v2 s_delay_alu instid0(VALU_DEP_4) v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo global_load_b32 v0, v[0:1], off global_load_b32 v1, v[2:3], off s_waitcnt vmcnt(0) v_mul_f32_e32 v0, v0, v1 global_store_b32 v[2:3], v0, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z12windowKernelPfS_ii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z12windowKernelPfS_ii, .Lfunc_end0-_Z12windowKernelPfS_ii .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z12windowKernelPfS_ii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z12windowKernelPfS_ii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void windowKernel(float* idata, float* window, int width, int height) { int tidx = threadIdx.x + blockIdx.x*blockDim.x; int tidy = threadIdx.y + blockIdx.y*blockDim.y; if(tidx < width && tidy < height) { idata[tidy * width + tidx] = window[tidx] * idata[tidy * width + tidx]; } }
.text .file "windowKernel.hip" .globl _Z27__device_stub__windowKernelPfS_ii # -- Begin function _Z27__device_stub__windowKernelPfS_ii .p2align 4, 0x90 .type _Z27__device_stub__windowKernelPfS_ii,@function _Z27__device_stub__windowKernelPfS_ii: # @_Z27__device_stub__windowKernelPfS_ii .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z12windowKernelPfS_ii, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z27__device_stub__windowKernelPfS_ii, .Lfunc_end0-_Z27__device_stub__windowKernelPfS_ii .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z12windowKernelPfS_ii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z12windowKernelPfS_ii,@object # @_Z12windowKernelPfS_ii .section .rodata,"a",@progbits .globl _Z12windowKernelPfS_ii .p2align 3, 0x0 _Z12windowKernelPfS_ii: .quad _Z27__device_stub__windowKernelPfS_ii .size _Z12windowKernelPfS_ii, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z12windowKernelPfS_ii" .size .L__unnamed_1, 23 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z27__device_stub__windowKernelPfS_ii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z12windowKernelPfS_ii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z12windowKernelPfS_ii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */ /* 0x000e280000002600 */ /*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */ /* 0x000e280000002200 */ /*0030*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */ /* 0x000e680000002100 */ /*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */ /* 0x000e620000002500 */ /*0050*/ IMAD R3, R3, c[0x0][0x4], R0 ; /* 0x0000010003037a24 */ /* 0x001fca00078e0200 */ /*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */ /* 0x000fe20003f06270 */ /*0070*/ IMAD R2, R5, c[0x0][0x0], R2 ; /* 0x0000000005027a24 */ /* 0x002fca00078e0202 */ /*0080*/ ISETP.GE.OR P0, PT, R2, c[0x0][0x170], P0 ; /* 0x00005c0002007a0c */ /* 0x000fda0000706670 */ /*0090*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */ /* 0x000fe200000001ff */ /*00b0*/ IMAD R4, R3, c[0x0][0x170], R2 ; /* 0x00005c0003047a24 */ /* 0x000fe200078e0202 */ /*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd00000000a00 */ /*00d0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */ /* 0x000fc800078e0205 */ /*00e0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */ /* 0x000fe400078e0205 */ /*00f0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */ /* 0x000ea8000c1e1900 */ /*0100*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */ /* 0x000ea4000c1e1900 */ /*0110*/ FMUL R7, R0, R3 ; /* 0x0000000300077220 */ /* 0x004fca0000400000 */ /*0120*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */ /* 0x000fe2000c101904 */ /*0130*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0140*/ BRA 0x140; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z12windowKernelPfS_ii .globl _Z12windowKernelPfS_ii .p2align 8 .type _Z12windowKernelPfS_ii,@function _Z12windowKernelPfS_ii: s_clause 0x1 s_load_b32 s2, s[0:1], 0x24 s_load_b64 s[4:5], s[0:1], 0x10 v_and_b32_e32 v2, 0x3ff, v0 v_bfe_u32 v4, v0, 10, 10 s_waitcnt lgkmcnt(0) s_and_b32 s3, s2, 0xffff s_lshr_b32 s2, s2, 16 v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3] v_mad_u64_u32 v[2:3], null, s15, s2, v[4:5] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_gt_i32_e32 vcc_lo, s4, v0 v_cmp_gt_i32_e64 s2, s5, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s2, vcc_lo, s2 s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_2 v_ashrrev_i32_e32 v1, 31, v0 s_load_b128 s[0:3], s[0:1], 0x0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mad_u64_u32 v[3:4], null, v2, s4, v[0:1] v_lshlrev_b64 v[0:1], 2, v[0:1] v_ashrrev_i32_e32 v4, 31, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_lshlrev_b64 v[2:3], 2, v[3:4] s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s2, v0 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo v_add_co_u32 v2, vcc_lo, s0, v2 s_delay_alu instid0(VALU_DEP_4) v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo global_load_b32 v0, v[0:1], off global_load_b32 v1, v[2:3], off s_waitcnt vmcnt(0) v_mul_f32_e32 v0, v0, v1 global_store_b32 v[2:3], v0, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z12windowKernelPfS_ii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z12windowKernelPfS_ii, .Lfunc_end0-_Z12windowKernelPfS_ii .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z12windowKernelPfS_ii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z12windowKernelPfS_ii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_000ceb12_00000000-6_windowKernel.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z36__device_stub__Z12windowKernelPfS_iiPfS_ii .type _Z36__device_stub__Z12windowKernelPfS_iiPfS_ii, @function _Z36__device_stub__Z12windowKernelPfS_iiPfS_ii: .LFB2051: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z12windowKernelPfS_ii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z36__device_stub__Z12windowKernelPfS_iiPfS_ii, .-_Z36__device_stub__Z12windowKernelPfS_iiPfS_ii .globl _Z12windowKernelPfS_ii .type _Z12windowKernelPfS_ii, @function _Z12windowKernelPfS_ii: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z36__device_stub__Z12windowKernelPfS_iiPfS_ii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z12windowKernelPfS_ii, .-_Z12windowKernelPfS_ii .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z12windowKernelPfS_ii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z12windowKernelPfS_ii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "windowKernel.hip" .globl _Z27__device_stub__windowKernelPfS_ii # -- Begin function _Z27__device_stub__windowKernelPfS_ii .p2align 4, 0x90 .type _Z27__device_stub__windowKernelPfS_ii,@function _Z27__device_stub__windowKernelPfS_ii: # @_Z27__device_stub__windowKernelPfS_ii .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z12windowKernelPfS_ii, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z27__device_stub__windowKernelPfS_ii, .Lfunc_end0-_Z27__device_stub__windowKernelPfS_ii .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z12windowKernelPfS_ii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z12windowKernelPfS_ii,@object # @_Z12windowKernelPfS_ii .section .rodata,"a",@progbits .globl _Z12windowKernelPfS_ii .p2align 3, 0x0 _Z12windowKernelPfS_ii: .quad _Z27__device_stub__windowKernelPfS_ii .size _Z12windowKernelPfS_ii, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z12windowKernelPfS_ii" .size .L__unnamed_1, 23 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z27__device_stub__windowKernelPfS_ii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z12windowKernelPfS_ii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
/** * Copyright 1993-2012 NVIDIA Corporation. All rights reserved. * * Please refer to the NVIDIA end user license agreement (EULA) associated * with this source code for terms and conditions that govern your use of * this software. Any use, reproduction, disclosure, or distribution of * this software and related documentation outside the terms of the EULA * is strictly prohibited. */ /* * cudaFPHI.cu * Primary Author: Brian Donohue * Date: 12/05/2015 * Email: bdono09@gmail.edu */ /* * To whoever wishes to modify and redistribute this file please write your name the date * and an explanation of the modification. * Modifications: * */ #include<iostream> #include<cstdlib> #include<time.h> #include<stdio.h> #include "cudafPHI.cuh" #include <cuda_runtime.h> extern size_t iterations; extern size_t batch_size; extern size_t free_voxels; static inline void printError(cudaError_t error, const char * functionMess, const char * opMess, int Line) { if (error == 0){ return; }else{ fclose(stderr); freopen("cudafPHI.err", "w", stderr); std::cout << functionMess << " " << opMess << " Line- " << Line << ": " << cudaGetErrorString(error) << "\n"; std::cerr << functionMess << " " << opMess << " Line- " << Line << ": " << cudaGetErrorString(error) << "\n"; fclose(stderr); cudaDeviceReset(); exit(0); } } static __global__ void calculate_ZTZ(float * d_Z, float * ZTZI, size_t n_subjects) { size_t rowIdx = threadIdx.x + blockDim.x * blockIdx.x; size_t tIdx = threadIdx.x; __shared__ float shared_ZTZI_0[BLOCK_SIZE_1]; __shared__ float shared_ZTZI_2[BLOCK_SIZE_1]; __shared__ float shared_ZTZI_3[BLOCK_SIZE_1]; if (rowIdx < n_subjects) { shared_ZTZI_0[tIdx] = d_Z[rowIdx] * d_Z[rowIdx]; shared_ZTZI_2[tIdx] = d_Z[rowIdx + n_subjects] * d_Z[rowIdx]; shared_ZTZI_3[tIdx] = d_Z[rowIdx + n_subjects] * d_Z[rowIdx + n_subjects]; }else{ shared_ZTZI_0[tIdx] = 0.f; shared_ZTZI_2[tIdx] = 0.f; shared_ZTZI_3[tIdx] = 0.f; } __syncthreads(); for(unsigned int stride = BLOCK_SIZE_1/2 ; stride > 0 ; stride >>=1){ if(threadIdx.x < stride && (rowIdx+stride < n_subjects)){ shared_ZTZI_0[tIdx] += shared_ZTZI_0[tIdx + stride]; shared_ZTZI_2[tIdx] += shared_ZTZI_2[tIdx + stride]; shared_ZTZI_3[tIdx] += shared_ZTZI_3[tIdx + stride]; } __syncthreads(); } if((tIdx == 0) && (rowIdx < n_subjects)){ atomicAdd(&ZTZI[0], shared_ZTZI_0[0]); atomicAdd(&ZTZI[1], shared_ZTZI_2[0]); atomicAdd(&ZTZI[2], shared_ZTZI_2[0]); atomicAdd(&ZTZI[3], shared_ZTZI_3[0]); } } static __global__ void Inv4by4(float * ZTZI) { float a = ZTZI[0]; float b = ZTZI[1]; float c = ZTZI[2]; float d = ZTZI[3]; float det = a * d - b * c; ZTZI[0] = d / det; ZTZI[1] = -c / det; ZTZI[2] = -b / det; ZTZI[3] = a / det; } /* static int calculate_batch_size(size_t n_voxels, size_t n_subjects, size_t * batch_size, unsigned int * iterations, size_t * free_voxels){ *batch_size = n_voxels; *iterations = 1; *free_voxels = 0; size_t freeMem; size_t totalMem; // cudaMemGetInfo(&freeMem, &totalMem); float data_size = 0.f; data_size += float(sizeof(float)*n_subjects); data_size += float(sizeof(float)*n_subjects); data_size += float(sizeof(float)); data_size += float(sizeof(float)); data_size += float(sizeof(bool)); *batch_size = floor((float(float(freeMem)))/data_size); *batch_size = n_voxels; if(*batch_size >= n_voxels){ *batch_size = n_voxels; *iterations = 1; *free_voxels = n_voxels; return 1; } if(*batch_size == 0) return 0; *free_voxels = n_voxels%*batch_size; *iterations = ceil(float(n_voxels)/float(*batch_size)); return 1; }*/ void * run_compute_F_pthread(void * run_compute_F_args){ const char * file_name = "cudafPHI.cu"; cudafPHI_variables * cudafPHI_vars = (cudafPHI_variables *)run_compute_F_args; cudaSetDevice(cudafPHI_vars->device); printf("berfore]\n"); printError(cudaMemsetAsync(cudafPHI_vars->d_F, 0, sizeof(float)*batch_size*cudafPHI_vars->n_subjects, cudafPHI_vars->stream), file_name, "cudaMemset-d_F", __LINE__); printf("after]\n"); if(cudafPHI_vars->stream_number == (iterations - 1)){ printError(cudaMemcpyAsync(cudafPHI_vars->d_sy, cudafPHI_vars->h_y + batch_size*cudafPHI_vars->stream_number*cudafPHI_vars->n_subjects, sizeof(float)*cudafPHI_vars->n_subjects*free_voxels, cudaMemcpyHostToDevice, cudafPHI_vars->stream), file_name, "cudaMemcpy-h_sy to d_sy", __LINE__); compute_F(cudafPHI_vars->d_hat, cudafPHI_vars->d_sy, cudafPHI_vars->d_evectors,cudafPHI_vars->d_F, cudafPHI_vars->compute_F_vars, cudafPHI_vars->covariates, cudafPHI_vars->n_subjects,free_voxels, cudafPHI_vars->stream); }else{ printError(cudaMemcpyAsync(cudafPHI_vars->d_sy, cudafPHI_vars->h_y + batch_size*cudafPHI_vars->stream_number*cudafPHI_vars->n_subjects, sizeof(float)*cudafPHI_vars->n_subjects*batch_size, cudaMemcpyHostToDevice, cudafPHI_vars->stream), file_name, "cudaMemcpy-h_sy to d_sy", __LINE__); compute_F(cudafPHI_vars->d_hat, cudafPHI_vars->d_sy, cudafPHI_vars->d_evectors,cudafPHI_vars->d_F, cudafPHI_vars->compute_F_vars, cudafPHI_vars->covariates, cudafPHI_vars->n_subjects,batch_size, cudafPHI_vars->stream); } cudaStreamSynchronize(cudafPHI_vars->stream); } void * run_compute_h2_pthread(void * run_compute_h2_args){ cudafPHI_variables * cudafPHI_vars = (cudafPHI_variables *)run_compute_h2_args; cudaSetDevice(cudafPHI_vars->device); const char * file_name = "cudafPHI.cu"; if(cudafPHI_vars->stream_number == (iterations - 1)){ compute_h2(cudafPHI_vars->d_F, cudafPHI_vars->d_h2, cudafPHI_vars->d_indicator, cudafPHI_vars->d_boolean_score, cudafPHI_vars->compute_h2_vars, cudafPHI_vars->aux_vars, cudafPHI_vars->n_subjects, free_voxels, cudafPHI_vars->stream); printError(cudaMemcpyAsync(&cudafPHI_vars->h2[cudafPHI_vars->stream_number*batch_size], cudafPHI_vars->d_h2, sizeof(float)*free_voxels, cudaMemcpyDeviceToHost, cudafPHI_vars->stream), file_name, "cudaMemcpy-d_h2 to h_h2", __LINE__); // printError(cudaMemcpyAsync(h_boolean_score, d_boolean_score, sizeof(bool)*batch_size, cudaMemcpyDeviceToHost, stream), file_name, // "cudaMemcpy-h_boolean to d_boolean", __LINE__); printError(cudaMemcpyAsync(&cudafPHI_vars->indicator[cudafPHI_vars->stream_number*batch_size], cudafPHI_vars->d_indicator, sizeof(float)*free_voxels, cudaMemcpyDeviceToHost, cudafPHI_vars->stream), file_name, "cudaMemcpy-d_indicator to h_indicator", __LINE__); }else{ compute_h2(cudafPHI_vars->d_F, cudafPHI_vars->d_h2, cudafPHI_vars->d_indicator, cudafPHI_vars->d_boolean_score, cudafPHI_vars->compute_h2_vars, cudafPHI_vars->aux_vars, cudafPHI_vars->n_subjects, batch_size, cudafPHI_vars->stream); printError(cudaMemcpyAsync(&cudafPHI_vars->h2[cudafPHI_vars->stream_number*batch_size], cudafPHI_vars->d_h2, sizeof(float)*batch_size, cudaMemcpyDeviceToHost, cudafPHI_vars->stream), file_name, "cudaMemcpy-d_h2 to h_h2", __LINE__); // printError(cudaMemcpyAsync(h_boolean_score, d_boolean_score, sizeof(bool)*batch_size, cudaMemcpyDeviceToHost, stream), file_name, // "cudaMemcpy-h_boolean to d_boolean", __LINE__); printError(cudaMemcpyAsync(&cudafPHI_vars->indicator[cudafPHI_vars->stream_number*batch_size], cudafPHI_vars->d_indicator, sizeof(float)*batch_size, cudaMemcpyDeviceToHost, cudafPHI_vars->stream), file_name, "cudaMemcpy-d_indicator to h_indicator", __LINE__); } cudaStreamSynchronize(cudafPHI_vars->stream); } void * run_compute_pval_pthread(void * run_compute_pval_args){ cudafPHI_variables * cudafPHI_vars = (cudafPHI_variables *)run_compute_pval_args; cudaSetDevice(cudafPHI_vars->device); const char * file_name = "cudafPHI.cu"; if (cudafPHI_vars->stream_number == (iterations - 1)){ printError(cudaMemsetAsync(cudafPHI_vars->d_pvals, 0, sizeof(float)*batch_size, cudafPHI_vars->stream), file_name, "cudaMemset-d_F", __LINE__); compute_pvals(cudafPHI_vars->d_sy, cudafPHI_vars->d_F, cudafPHI_vars->d_hat, cudafPHI_vars->compute_h2_vars.d_Sigma_P, cudafPHI_vars->compute_h2_vars.d_Sigma_P, cudafPHI_vars->d_pvals, cudafPHI_vars->d_pmatrix, cudafPHI_vars->d_boolean_score, cudafPHI_vars->aux_vars, cudafPHI_vars->pval_vars, cudafPHI_vars->covariates, cudafPHI_vars->n_subjects, free_voxels, cudafPHI_vars->n_permutations, cudafPHI_vars->stream); printError(cudaMemcpyAsync(&cudafPHI_vars->pvals[cudafPHI_vars->stream_number*batch_size], cudafPHI_vars->d_pvals, sizeof(float)*free_voxels, cudaMemcpyDeviceToHost, cudafPHI_vars->stream), file_name, "cudaMemcpy-d_pvals to h_pvals", __LINE__); }else{ printError(cudaMemsetAsync(cudafPHI_vars->d_pvals, 0, sizeof(float)*batch_size, cudafPHI_vars->stream), file_name, "cudaMemset-d_F", __LINE__); compute_pvals(cudafPHI_vars->d_sy, cudafPHI_vars->d_F, cudafPHI_vars->d_hat, cudafPHI_vars->compute_h2_vars.d_Sigma_P, cudafPHI_vars->compute_h2_vars.d_Sigma_P, cudafPHI_vars->d_pvals, cudafPHI_vars->d_pmatrix, cudafPHI_vars->d_boolean_score, cudafPHI_vars->aux_vars, cudafPHI_vars->pval_vars, cudafPHI_vars->covariates, cudafPHI_vars->n_subjects, batch_size, cudafPHI_vars->n_permutations, cudafPHI_vars->stream); printError(cudaMemcpyAsync(&cudafPHI_vars->pvals[cudafPHI_vars->stream_number*batch_size], cudafPHI_vars->d_pvals, sizeof(float)*batch_size, cudaMemcpyDeviceToHost, cudafPHI_vars->stream), file_name, "cudaMemcpy-d_pvals to h_pvals", __LINE__); } cudaStreamSynchronize(cudafPHI_vars->stream); } static void cudafPHI(float * h_y, float * h2, float * indicator, float * pvals,float * d_sy,float * d_F,float * d_hat, float * d_evectors, float * d_h2, float * d_indicator, float * d_pvals, unsigned int * d_pmatrix, compute_F_variables compute_F_vars, aux_variables aux_vars, compute_h2_variables compute_h2_vars, pval_variables pval_vars, bool covariates, bool get_pval, bool * d_boolean_score, size_t n_voxels, size_t n_subjects, size_t n_permutations, int current_stream_number, int device, cudaStream_t stream){ // cudaSetDevice(gpu); const char * file_name = "cudafPHI.cu"; // cudaSetDevice(gpu); if(current_stream_number == (iterations - 1)){ printError(cudaMemcpyAsync(d_sy, h_y + batch_size*current_stream_number*n_subjects, sizeof(float)*n_subjects*free_voxels, cudaMemcpyHostToDevice, stream), file_name, "cudaMemcpy-h_sy to d_sy", __LINE__); }else{ printError(cudaMemcpyAsync(d_sy, h_y + batch_size*current_stream_number*n_subjects, sizeof(float)*n_subjects*batch_size, cudaMemcpyHostToDevice, stream), file_name, "cudaMemcpy-h_sy to d_sy", __LINE__); } // cudaDeviceSynchronize(); // cudaDeviceSynchronize() printError(cudaMemsetAsync(d_F, 0, sizeof(float)*batch_size*n_subjects, stream), file_name, "cudaMemset-d_F", __LINE__); if(current_stream_number == (iterations - 1)){ compute_F(d_hat, d_sy, d_evectors,d_F, compute_F_vars, covariates, n_subjects,free_voxels, stream); compute_h2(d_F, d_h2, d_indicator, d_boolean_score, compute_h2_vars, aux_vars, n_subjects, free_voxels, stream); printError(cudaMemcpyAsync(&h2[current_stream_number*batch_size], d_h2, sizeof(float)*free_voxels, cudaMemcpyDeviceToHost, stream), file_name, "cudaMemcpy-d_h2 to h_h2", __LINE__); // printError(cudaMemcpyAsync(h_boolean_score, d_boolean_score, sizeof(bool)*batch_size, cudaMemcpyDeviceToHost, stream), file_name, // "cudaMemcpy-h_boolean to d_boolean", __LINE__); printError(cudaMemcpyAsync(&indicator[current_stream_number*batch_size], d_indicator, sizeof(float)*free_voxels, cudaMemcpyDeviceToHost, stream), file_name, "cudaMemcpy-d_indicator to h_indicator", __LINE__); // cudaStreamSynchronize(stream); if(get_pval){ printError(cudaMemsetAsync(d_pvals, 0, sizeof(float)*batch_size, stream), file_name, "cudaMemset-d_F", __LINE__); compute_pvals(d_sy, d_F, d_hat, compute_h2_vars.d_Sigma_P, compute_h2_vars.d_Sigma_P, d_pvals, d_pmatrix, d_boolean_score, aux_vars, pval_vars, covariates, n_subjects, free_voxels, n_permutations, stream); printError(cudaMemcpyAsync(&pvals[current_stream_number*batch_size], d_pvals, sizeof(float)*free_voxels, cudaMemcpyDeviceToHost, stream), file_name, "cudaMemcpy-d_pvals to h_pvals", __LINE__); // cudaStreamSynchronize(stream); } }else{ compute_F(d_hat, d_sy, d_evectors,d_F, compute_F_vars, covariates, n_subjects, batch_size, stream); compute_h2(d_F, d_h2, d_indicator, d_boolean_score, compute_h2_vars, aux_vars, n_subjects, batch_size, stream); printError(cudaMemcpyAsync(&h2[current_stream_number*batch_size], d_h2, sizeof(float)*batch_size, cudaMemcpyDeviceToHost, stream), file_name, "cudaMemcpy-d_h2 to h_h2", __LINE__); //printError(cudaMemcpyAsync(h_boolean_score, d_boolean_score, sizeof(bool)*batch_size, cudaMemcpyDeviceToHost, stream), file_name, // "cudaMemcpy-h_boolean to d_boolean", __LINE__); printError(cudaMemcpyAsync(&indicator[current_stream_number*batch_size], d_indicator, sizeof(float)*batch_size, cudaMemcpyDeviceToHost, stream), file_name, "cudaMemcpy-d_indicator to h_indicator", __LINE__); // cudaStreamSynchronize(stream); if(get_pval){ printError(cudaMemsetAsync(d_pvals, 0, sizeof(float)*batch_size, stream), file_name, "cudaMemset-d_F", __LINE__); compute_pvals(d_sy, d_F, d_hat, compute_h2_vars.d_Sigma_P, compute_h2_vars.d_Sigma_P, d_pvals, d_pmatrix, d_boolean_score, aux_vars, pval_vars, covariates, n_subjects, batch_size, n_permutations, stream); printError(cudaMemcpyAsync(&pvals[current_stream_number*batch_size], d_pvals, sizeof(float)*batch_size, cudaMemcpyDeviceToHost, stream), file_name, "cudaMemcpy-d_pvals to h_pvals", __LINE__); // cudaStreamSynchronize(stream); } // } // cudaStreamSynchronize(stream); // printf ("It took %f seconds.\n", (((float)(clock()-timer))/CLOCKS_PER_SEC)); //for(unsigned int i = 0 ; i < n_voxels ; i++){ // std::cout << indicator[i] << " " << h2[i] << " " << pvals[i] << "\n"; // h2[iteration*batch_size + i] = h_h2[i]; // indicator[iteration*batch_size + i] = h_h2[i]; // if(get_pval == true) //pvals[iteration*batch_size + i] = h_pvals[i]} // } // cudaStreamDestroy(stream); // cudaDeviceReset(); } void run_cudafPHI_loop(void * cudafPHI_args){ const char * file_name = "cudafPHI.cu"; cudafPHI_variables * cudafPHI_vars; cudafPHI_vars = (cudafPHI_variables *)cudafPHI_args; printError(cudaMalloc((void**)&cudafPHI_vars->aux_vars.d_Z, sizeof(float)*2*cudafPHI_vars->n_subjects), file_name, "cudaMalloc-d_Z", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->aux_vars.d_ZTZI, sizeof(float)*4), file_name, "cudaMalloc-d_ZTZI", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_F_vars.d_Y, sizeof(float)*cudafPHI_vars->n_subjects), file_name, "cudaMalloc-d_Y", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_F_vars.mean, sizeof(float)), file_name, "cudaMalloc-mean", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_h2_vars.d_A, sizeof(float)), file_name, "cudaMalloc-d_A", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_h2_vars.d_B, sizeof(float)), file_name, "cudaMalloc-d_B", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_h2_vars.d_C, sizeof(float)), file_name, "cudaMalloc-d_C", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_h2_vars.d_D, sizeof(float)), file_name, "cudaMalloc-d_D", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_h2_vars.d_E, sizeof(float)), file_name, "cudaMalloc-d_E", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_h2_vars.d_Sigma_P, sizeof(float)), file_name, "cudaMalloc-d_Sigma_P", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_h2_vars.d_score, sizeof(float)), file_name, "cudaMalloc-d_score", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_h2_vars.d_theta, sizeof(float)*2), file_name, "cudaMalloc-d_theta", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_h2_vars.d_weights, sizeof(float)*cudafPHI_vars->n_subjects), file_name, "cudaMalloc-d_weights", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->pval_vars.syP, sizeof(float)*cudafPHI_vars->n_subjects*(cudafPHI_vars->n_permutations + 1)), file_name, "cudaMalloc-d_syP", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->pval_vars.d_F, sizeof(float)*cudafPHI_vars->n_subjects*(cudafPHI_vars->n_permutations + 1)), file_name, "cudaMalloc-d_F", __LINE__); printError(cudaMalloc((void**) &cudafPHI_vars->pval_vars.d_score, sizeof(float) * (cudafPHI_vars->n_permutations + 1)), file_name, "cudaMalloc-d_score", __LINE__); printError(cudaMalloc((void**) &cudafPHI_vars->pval_vars.d_Ts, sizeof(float) * (cudafPHI_vars->n_permutations + 1)), file_name, "cudaMalloc-d_Ts", __LINE__); printError(cudaMalloc((void**) &cudafPHI_vars->pval_vars.d_a, sizeof(float) * (cudafPHI_vars->n_permutations + 1) * 2), file_name, "cudaMalloc-d_a", __LINE__); printError(cudaMalloc((void**) &cudafPHI_vars->pval_vars.d_sigmaP, sizeof(float)*(cudafPHI_vars->n_permutations + 1)), file_name, "cudaMalloc-d_sigmaP", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->d_hat, sizeof(float)*cudafPHI_vars->n_subjects*cudafPHI_vars->n_subjects), file_name, "cudaMalloc-d_hat", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->d_evectors, sizeof(float)*cudafPHI_vars->n_subjects*cudafPHI_vars->n_subjects), file_name, "cudaMalloc-d_evectors", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->d_pmatrix, sizeof(float)*cudafPHI_vars->n_subjects*(cudafPHI_vars->n_permutations + 1)), file_name, "cudaMalloc-d_pmatrix", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->d_sy, sizeof(float)*cudafPHI_vars->n_subjects*batch_size),file_name, "cudaMalloc-d_sy", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->d_F, sizeof(float)*batch_size*cudafPHI_vars->n_subjects), file_name, "cudaMalloc-d_F", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->d_indicator, sizeof(float)*batch_size), file_name, "cudaMalloc-d_indicator", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->d_h2, sizeof(float)*batch_size), file_name, "cudaMalloc-d_F", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->d_pvals, sizeof(float)*batch_size), file_name, "cudaMalloc-d_pvals", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->d_boolean_score, sizeof(bool)*batch_size), file_name, "cudaMalloc-d_boolean_score", __LINE__); cudaStream_t stream; cudaStreamCreate(&stream); printError(cudaMemcpyAsync(cudafPHI_vars->d_pmatrix, cudafPHI_vars->h_pmatrix, sizeof(float)*cudafPHI_vars->n_subjects*(cudafPHI_vars->n_permutations + 1), cudaMemcpyHostToDevice, stream), file_name, "cudaMemcpy-h_pmatrix to d_pmatrix", __LINE__); printError(cudaMemcpyAsync(cudafPHI_vars->d_evectors, cudafPHI_vars->h_evectors, sizeof(float)*cudafPHI_vars->n_subjects*cudafPHI_vars->n_subjects, cudaMemcpyHostToDevice, stream), file_name, "cudaMemcpy-evectors to d_evectors", __LINE__); printError(cudaMemcpyAsync(cudafPHI_vars->d_hat, cudafPHI_vars->h_hat, sizeof(float)*cudafPHI_vars->n_subjects*cudafPHI_vars->n_subjects, cudaMemcpyHostToDevice,stream), file_name, "cudaMemcpy-h_hat to d_hat", __LINE__); printError(cudaMemcpyAsync(cudafPHI_vars->aux_vars.d_Z, cudafPHI_vars->h_Z, sizeof(float)*cudafPHI_vars->n_subjects*2, cudaMemcpyHostToDevice, stream), file_name, "cudaMemcpy-h_Z to d_Z", __LINE__); dim3 blockSize(BLOCK_SIZE_1, 1, 1); dim3 gridSize(ceil(float(cudafPHI_vars->n_subjects) / float(BLOCK_SIZE_1)), 1, 1); printError(cudaMemsetAsync(cudafPHI_vars->aux_vars.d_ZTZI, 0, sizeof(float)*4, stream), file_name, "cudaMemset-d_ZTZI", __LINE__); calculate_ZTZ<<<gridSize, blockSize, 0, stream>>>(cudafPHI_vars->aux_vars.d_Z, cudafPHI_vars->aux_vars.d_ZTZI, cudafPHI_vars->n_subjects); Inv4by4<<<1, 1, 0, stream>>>(cudafPHI_vars->aux_vars.d_ZTZI); for(size_t iteration = 0 ; iteration < iterations ; iteration++){ cudafPHI(cudafPHI_vars->h_y, cudafPHI_vars->h2, cudafPHI_vars->indicator, cudafPHI_vars->pvals,cudafPHI_vars->d_sy, cudafPHI_vars->d_F,cudafPHI_vars->d_hat, cudafPHI_vars->d_evectors, cudafPHI_vars->d_h2, cudafPHI_vars->d_indicator, cudafPHI_vars->d_pvals, cudafPHI_vars->d_pmatrix, cudafPHI_vars->compute_F_vars, cudafPHI_vars->aux_vars, cudafPHI_vars->compute_h2_vars, cudafPHI_vars->pval_vars, cudafPHI_vars->covariates, cudafPHI_vars->get_pval, cudafPHI_vars->d_boolean_score, cudafPHI_vars->n_voxels, cudafPHI_vars->n_subjects, cudafPHI_vars->n_permutations, iteration, cudafPHI_vars->device, stream); cudaStreamSynchronize(stream); } cudaStreamDestroy(stream); cudaDeviceReset(); } void * run_cudafPHI_thread(void * cudafPHI_args){ } void * run_allocation_test(void * cudafPHI_args){ const char * file_name = "cudafPHI.cu"; cudafPHI_variables * cudafPHI_vars; cudafPHI_vars = (cudafPHI_variables *)cudafPHI_args; cudaSetDevice(cudafPHI_vars->device); printError(cudaMalloc((void**)&cudafPHI_vars->aux_vars.d_Z, sizeof(float)*2*cudafPHI_vars->n_subjects), file_name, "cudaMalloc-d_Z", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->aux_vars.d_ZTZI, sizeof(float)*4), file_name, "cudaMalloc-d_ZTZI", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_F_vars.d_Y, sizeof(float)*cudafPHI_vars->n_subjects*batch_size), file_name, "cudaMalloc-d_Y", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_F_vars.mean, sizeof(float)*batch_size), file_name, "cudaMalloc-mean", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_h2_vars.d_A, sizeof(float)), file_name, "cudaMalloc-d_A", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_h2_vars.d_B, sizeof(float)), file_name, "cudaMalloc-d_B", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_h2_vars.d_C, sizeof(float)), file_name, "cudaMalloc-d_C", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_h2_vars.d_D, sizeof(float)), file_name, "cudaMalloc-d_D", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_h2_vars.d_E, sizeof(float)), file_name, "cudaMalloc-d_E", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_h2_vars.d_Sigma_P, sizeof(float)), file_name, "cudaMalloc-d_Sigma_P", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_h2_vars.d_score, sizeof(float)), file_name, "cudaMalloc-d_score", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_h2_vars.d_theta, sizeof(float)*2), file_name, "cudaMalloc-d_theta", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_h2_vars.d_weights, sizeof(float)*cudafPHI_vars->n_subjects), file_name, "cudaMalloc-d_weights", __LINE__); if(cudafPHI_vars->get_pval){ printError(cudaMalloc((void**)&cudafPHI_vars->pval_vars.syP, sizeof(float)*cudafPHI_vars->n_subjects*(cudafPHI_vars->n_permutations + 1)), file_name, "cudaMalloc-d_syP", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->pval_vars.d_F, sizeof(float)*cudafPHI_vars->n_subjects*(cudafPHI_vars->n_permutations + 1)), file_name, "cudaMalloc-d_F", __LINE__); printError(cudaMalloc((void**) &cudafPHI_vars->pval_vars.d_score, sizeof(float) * (cudafPHI_vars->n_permutations + 1)), file_name, "cudaMalloc-d_score", __LINE__); printError(cudaMalloc((void**) &cudafPHI_vars->pval_vars.d_Ts, sizeof(float) * (cudafPHI_vars->n_permutations + 1)), file_name, "cudaMalloc-d_Ts", __LINE__); printError(cudaMalloc((void**) &cudafPHI_vars->pval_vars.d_a, sizeof(float) * (cudafPHI_vars->n_permutations + 1) * 2), file_name, "cudaMalloc-d_a", __LINE__); printError(cudaMalloc((void**) &cudafPHI_vars->pval_vars.d_sigmaP, sizeof(float)*(cudafPHI_vars->n_permutations + 1)), file_name, "cudaMalloc-d_sigmaP", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->d_pmatrix, sizeof(float)*cudafPHI_vars->n_subjects*(cudafPHI_vars->n_permutations + 1)), file_name, "cudaMalloc-d_pmatrix", __LINE__); } if(cudafPHI_vars->covariates){ printError(cudaMalloc((void**)&cudafPHI_vars->d_hat, sizeof(float)*cudafPHI_vars->n_subjects*cudafPHI_vars->n_subjects), file_name, "cudaMalloc-d_hat", __LINE__); } printError(cudaMalloc((void**)&cudafPHI_vars->d_evectors, sizeof(float)*cudafPHI_vars->n_subjects*cudafPHI_vars->n_subjects), file_name, "cudaMalloc-d_evectors", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->d_sy, sizeof(float)*cudafPHI_vars->n_subjects*batch_size),file_name, "cudaMalloc-d_sy", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->d_F, sizeof(float)*batch_size*cudafPHI_vars->n_subjects), file_name, "cudaMalloc-d_F", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->d_indicator, sizeof(float)*batch_size), file_name, "cudaMalloc-d_indicator", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->d_h2, sizeof(float)*batch_size), file_name, "cudaMalloc-d_F", __LINE__); if(cudafPHI_vars->get_pval){ printError(cudaMalloc((void**)&cudafPHI_vars->d_pvals, sizeof(float)*batch_size), file_name, "cudaMalloc-d_pvals", __LINE__); } printError(cudaMalloc((void**)&cudafPHI_vars->d_boolean_score, sizeof(bool)*batch_size), file_name, "cudaMalloc-d_boolean_score", __LINE__); } void * run_cudafPHI_pthread(void * cudafPHI_args){ const char * file_name = "cudafPHI.cu"; cudafPHI_variables * cudafPHI_vars; cudafPHI_vars = (cudafPHI_variables *)cudafPHI_args; cudaSetDevice(cudafPHI_vars->device); printError(cudaMalloc((void**)&cudafPHI_vars->aux_vars.d_Z, sizeof(float)*2*cudafPHI_vars->n_subjects), file_name, "cudaMalloc-d_Z", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->aux_vars.d_ZTZI, sizeof(float)*4), file_name, "cudaMalloc-d_ZTZI", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_F_vars.d_Y, sizeof(float)*cudafPHI_vars->n_subjects*batch_size), file_name, "cudaMalloc-d_Y", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_F_vars.mean, sizeof(float)*batch_size), file_name, "cudaMalloc-mean", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_h2_vars.d_A, sizeof(float)), file_name, "cudaMalloc-d_A", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_h2_vars.d_B, sizeof(float)), file_name, "cudaMalloc-d_B", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_h2_vars.d_C, sizeof(float)), file_name, "cudaMalloc-d_C", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_h2_vars.d_D, sizeof(float)), file_name, "cudaMalloc-d_D", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_h2_vars.d_E, sizeof(float)), file_name, "cudaMalloc-d_E", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_h2_vars.d_Sigma_P, sizeof(float)), file_name, "cudaMalloc-d_Sigma_P", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_h2_vars.d_score, sizeof(float)), file_name, "cudaMalloc-d_score", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_h2_vars.d_theta, sizeof(float)*2), file_name, "cudaMalloc-d_theta", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->compute_h2_vars.d_weights, sizeof(float)*cudafPHI_vars->n_subjects), file_name, "cudaMalloc-d_weights", __LINE__); if(cudafPHI_vars->get_pval == true){ printError(cudaMalloc((void**)&cudafPHI_vars->pval_vars.syP, sizeof(float)*cudafPHI_vars->n_subjects*(cudafPHI_vars->n_permutations + 1)), file_name, "cudaMalloc-d_syP", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->pval_vars.d_F, sizeof(float)*cudafPHI_vars->n_subjects*(cudafPHI_vars->n_permutations + 1)), file_name, "cudaMalloc-d_F", __LINE__); printError(cudaMalloc((void**) &cudafPHI_vars->pval_vars.d_score, sizeof(float) * (cudafPHI_vars->n_permutations + 1)), file_name, "cudaMalloc-d_score", __LINE__); printError(cudaMalloc((void**) &cudafPHI_vars->pval_vars.d_Ts, sizeof(float) * (cudafPHI_vars->n_permutations + 1)), file_name, "cudaMalloc-d_Ts", __LINE__); printError(cudaMalloc((void**) &cudafPHI_vars->pval_vars.d_a, sizeof(float) * (cudafPHI_vars->n_permutations + 1) * 2), file_name, "cudaMalloc-d_a", __LINE__); printError(cudaMalloc((void**) &cudafPHI_vars->pval_vars.d_sigmaP, sizeof(float)*(cudafPHI_vars->n_permutations + 1)), file_name, "cudaMalloc-d_sigmaP", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->d_pmatrix, sizeof(float)*cudafPHI_vars->n_subjects*(cudafPHI_vars->n_permutations + 1)), file_name, "cudaMalloc-d_pmatrix", __LINE__); } if(cudafPHI_vars->covariates == true){ printError(cudaMalloc((void**)&cudafPHI_vars->d_hat, sizeof(float)*cudafPHI_vars->n_subjects*cudafPHI_vars->n_subjects), file_name, "cudaMalloc-d_hat", __LINE__); } printError(cudaMalloc((void**)&cudafPHI_vars->d_evectors, sizeof(float)*cudafPHI_vars->n_subjects*cudafPHI_vars->n_subjects), file_name, "cudaMalloc-d_evectors", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->d_sy, sizeof(float)*cudafPHI_vars->n_subjects*batch_size),file_name, "cudaMalloc-d_sy", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->d_F, sizeof(float)*batch_size*cudafPHI_vars->n_subjects), file_name, "cudaMalloc-d_F", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->d_indicator, sizeof(float)*batch_size), file_name, "cudaMalloc-d_indicator", __LINE__); printError(cudaMalloc((void**)&cudafPHI_vars->d_h2, sizeof(float)*batch_size), file_name, "cudaMalloc-d_F", __LINE__); if(cudafPHI_vars->get_pval == true){ printError(cudaMalloc((void**)&cudafPHI_vars->d_pvals, sizeof(float)*batch_size), file_name, "cudaMalloc-d_pvals", __LINE__); } printError(cudaMalloc((void**)&cudafPHI_vars->d_boolean_score, sizeof(bool)*batch_size), file_name, "cudaMalloc-d_boolean_score", __LINE__); cudaStream_t stream; cudaStreamCreate(&cudafPHI_vars->stream); if(cudafPHI_vars->get_pval == true){ printError(cudaMemcpyAsync(cudafPHI_vars->d_pmatrix, cudafPHI_vars->h_pmatrix, sizeof(float)*cudafPHI_vars->n_subjects*(cudafPHI_vars->n_permutations + 1), cudaMemcpyHostToDevice, stream), file_name, "cudaMemcpy-h_pmatrix to d_pmatrix", __LINE__); } printError(cudaMemcpyAsync(cudafPHI_vars->d_evectors, cudafPHI_vars->h_evectors, sizeof(float)*cudafPHI_vars->n_subjects*cudafPHI_vars->n_subjects, cudaMemcpyHostToDevice, stream), file_name, "cudaMemcpy-evectors to d_evectors", __LINE__); if(cudafPHI_vars->covariates == true){ printError(cudaMemcpyAsync(cudafPHI_vars->d_hat, cudafPHI_vars->h_hat, sizeof(float)*cudafPHI_vars->n_subjects*cudafPHI_vars->n_subjects, cudaMemcpyHostToDevice,stream), file_name, "cudaMemcpy-h_hat to d_hat", __LINE__); } printError(cudaMemcpyAsync(cudafPHI_vars->aux_vars.d_Z, cudafPHI_vars->h_Z, sizeof(float)*cudafPHI_vars->n_subjects*2, cudaMemcpyHostToDevice, stream), file_name, "cudaMemcpy-h_Z to d_Z", __LINE__); dim3 blockSize(BLOCK_SIZE_1, 1, 1); dim3 gridSize(ceil(float(cudafPHI_vars->n_subjects) / float(BLOCK_SIZE_1)), 1, 1); calculate_ZTZ<<<gridSize, blockSize, 0, stream>>>(cudafPHI_vars->aux_vars.d_Z, cudafPHI_vars->aux_vars.d_ZTZI, cudafPHI_vars->n_subjects); Inv4by4<<<1, 1, 0, stream>>>(cudafPHI_vars->aux_vars.d_ZTZI); cudafPHI(cudafPHI_vars->h_y, cudafPHI_vars->h2, cudafPHI_vars->indicator, cudafPHI_vars->pvals,cudafPHI_vars->d_sy, cudafPHI_vars->d_F,cudafPHI_vars->d_hat, cudafPHI_vars->d_evectors, cudafPHI_vars->d_h2, cudafPHI_vars->d_indicator, cudafPHI_vars->d_pvals, cudafPHI_vars->d_pmatrix, cudafPHI_vars->compute_F_vars, cudafPHI_vars->aux_vars, cudafPHI_vars->compute_h2_vars, cudafPHI_vars->pval_vars, cudafPHI_vars->covariates, cudafPHI_vars->get_pval, cudafPHI_vars->d_boolean_score, cudafPHI_vars->n_voxels, cudafPHI_vars->n_subjects, cudafPHI_vars->n_permutations, cudafPHI_vars->stream_number, cudafPHI_vars->device, cudafPHI_vars->stream); cudaStreamDestroy(cudafPHI_vars->stream); }
/* * cudafPHI.cuh * * Created on: Aug 6, 2016 * Author: brian */ #include <hip/hip_runtime.h> #include <vector> #ifndef CUDAFPHI_CUH_ #define CUDAFPHI_CUH_ #define BLOCK_SIZE_1 256 #define BLOCK_SIZE_2 1024 #define BLOCK_SIZE_3 512 #define BLOCK_SIZE_HAT 16 typedef struct { float * d_theta; float * d_weights; float * d_A, * d_B, * d_C, * d_D, * d_E; float * d_score; float * d_Sigma_P; }compute_h2_variables; typedef struct { float * mean; float * d_Y; }compute_F_variables; typedef struct{ float * h_y; float * d_hat; float * d_sy; float * d_evectors; float * d_F; compute_F_variables compute_F_vars; bool covariates; size_t n_subjects; int current_stream_number; hipStream_t stream; }run_compute_F_variables; typedef struct { float * d_Z; float * d_ZTZI; }aux_variables; typedef struct{ float * d_F; float * d_h2; float * d_indicator; float * d_boolean_score; float * indicator; float * h2; compute_h2_variables compute_h2_vars; aux_variables aux_vars; size_t n_subjects; int stream_number; hipStream_t stream; }run_compute_h2_variables; typedef struct{ float * syP; float * d_F; float * d_score; float * d_Ts; float * d_a; float * d_sigmaP; }pval_variables; typedef struct{ float * d_F; float * d_pvals; float * d_boolean_score; float * pvals; float * d_hat; compute_h2_variables compute_h2_vars; aux_variables aux_vars; pval_variables pval_vars; size_t n_subjects; size_t n_permutations; int stream_number; bool covariates; hipStream_t stream; }run_compute_pval_variables; typedef struct{ float * h_y; float * h2; float * indicator; float * pvals; float * d_sy; float * d_F; float * d_hat; float * d_evectors; float * d_h2; float * d_indicator; float * d_pvals; float * h_evectors; float * h_hat; float * h_Z; unsigned int * h_pmatrix; unsigned int * d_pmatrix; compute_F_variables compute_F_vars; aux_variables aux_vars; compute_h2_variables compute_h2_vars; pval_variables pval_vars; bool covariates; bool get_pval; bool * d_boolean_score; size_t n_voxels; size_t n_subjects; size_t n_permutations; // size_t voxels_used; int device; hipStream_t stream; int stream_number; }cudafPHI_variables; int compute_h2(float * d_F, float * d_h2, float * d_indicator, bool * d_boolean_score, compute_h2_variables vars, aux_variables aux_vars, size_t n_subjects, size_t n_voxels, hipStream_t stream); int compute_F(float * d_hat, float* d_sy, float *d_evectors, float * d_F, compute_F_variables vars, bool covariates, size_t n_subjects, size_t n_voxels, hipStream_t stream); int compute_pvals(float * d_sy, float * d_res, float * d_hat, float * d_sigma_E, float * d_sigma_A, float * d_pvals, unsigned int * d_pmatrix, bool * h_boolean_score, aux_variables aux_vars, pval_variables pval_vars, bool covariate, size_t n_subjects, size_t n_voxels, size_t n_permutations, hipStream_t stream); void * run_cudafPHI_pthread(void * cudafPHI_args); void run_cudafPHI_loop(void * cudafPHI_args); void * run_compute_F_pthread(void * run_compute_F_args); void * run_compute_h2_pthread(void * run_compute_F_args); void * run_compute_pval_pthread(void * run_compute_F_args); void * run_allocation_test(void * cudafPHI_args); #endif /* CUDAFPHI_H_ */
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
/* * cudafPHI.cuh * * Created on: Aug 6, 2016 * Author: brian */ #include <hip/hip_runtime.h> #include <vector> #ifndef CUDAFPHI_CUH_ #define CUDAFPHI_CUH_ #define BLOCK_SIZE_1 256 #define BLOCK_SIZE_2 1024 #define BLOCK_SIZE_3 512 #define BLOCK_SIZE_HAT 16 typedef struct { float * d_theta; float * d_weights; float * d_A, * d_B, * d_C, * d_D, * d_E; float * d_score; float * d_Sigma_P; }compute_h2_variables; typedef struct { float * mean; float * d_Y; }compute_F_variables; typedef struct{ float * h_y; float * d_hat; float * d_sy; float * d_evectors; float * d_F; compute_F_variables compute_F_vars; bool covariates; size_t n_subjects; int current_stream_number; hipStream_t stream; }run_compute_F_variables; typedef struct { float * d_Z; float * d_ZTZI; }aux_variables; typedef struct{ float * d_F; float * d_h2; float * d_indicator; float * d_boolean_score; float * indicator; float * h2; compute_h2_variables compute_h2_vars; aux_variables aux_vars; size_t n_subjects; int stream_number; hipStream_t stream; }run_compute_h2_variables; typedef struct{ float * syP; float * d_F; float * d_score; float * d_Ts; float * d_a; float * d_sigmaP; }pval_variables; typedef struct{ float * d_F; float * d_pvals; float * d_boolean_score; float * pvals; float * d_hat; compute_h2_variables compute_h2_vars; aux_variables aux_vars; pval_variables pval_vars; size_t n_subjects; size_t n_permutations; int stream_number; bool covariates; hipStream_t stream; }run_compute_pval_variables; typedef struct{ float * h_y; float * h2; float * indicator; float * pvals; float * d_sy; float * d_F; float * d_hat; float * d_evectors; float * d_h2; float * d_indicator; float * d_pvals; float * h_evectors; float * h_hat; float * h_Z; unsigned int * h_pmatrix; unsigned int * d_pmatrix; compute_F_variables compute_F_vars; aux_variables aux_vars; compute_h2_variables compute_h2_vars; pval_variables pval_vars; bool covariates; bool get_pval; bool * d_boolean_score; size_t n_voxels; size_t n_subjects; size_t n_permutations; // size_t voxels_used; int device; hipStream_t stream; int stream_number; }cudafPHI_variables; int compute_h2(float * d_F, float * d_h2, float * d_indicator, bool * d_boolean_score, compute_h2_variables vars, aux_variables aux_vars, size_t n_subjects, size_t n_voxels, hipStream_t stream); int compute_F(float * d_hat, float* d_sy, float *d_evectors, float * d_F, compute_F_variables vars, bool covariates, size_t n_subjects, size_t n_voxels, hipStream_t stream); int compute_pvals(float * d_sy, float * d_res, float * d_hat, float * d_sigma_E, float * d_sigma_A, float * d_pvals, unsigned int * d_pmatrix, bool * h_boolean_score, aux_variables aux_vars, pval_variables pval_vars, bool covariate, size_t n_subjects, size_t n_voxels, size_t n_permutations, hipStream_t stream); void * run_cudafPHI_pthread(void * cudafPHI_args); void run_cudafPHI_loop(void * cudafPHI_args); void * run_compute_F_pthread(void * run_compute_F_args); void * run_compute_h2_pthread(void * run_compute_F_args); void * run_compute_pval_pthread(void * run_compute_F_args); void * run_allocation_test(void * cudafPHI_args); #endif /* CUDAFPHI_H_ */
.text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .amdgpu_metadata --- amdhsa.kernels: [] amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
/* * cudafPHI.cuh * * Created on: Aug 6, 2016 * Author: brian */ #include <hip/hip_runtime.h> #include <vector> #ifndef CUDAFPHI_CUH_ #define CUDAFPHI_CUH_ #define BLOCK_SIZE_1 256 #define BLOCK_SIZE_2 1024 #define BLOCK_SIZE_3 512 #define BLOCK_SIZE_HAT 16 typedef struct { float * d_theta; float * d_weights; float * d_A, * d_B, * d_C, * d_D, * d_E; float * d_score; float * d_Sigma_P; }compute_h2_variables; typedef struct { float * mean; float * d_Y; }compute_F_variables; typedef struct{ float * h_y; float * d_hat; float * d_sy; float * d_evectors; float * d_F; compute_F_variables compute_F_vars; bool covariates; size_t n_subjects; int current_stream_number; hipStream_t stream; }run_compute_F_variables; typedef struct { float * d_Z; float * d_ZTZI; }aux_variables; typedef struct{ float * d_F; float * d_h2; float * d_indicator; float * d_boolean_score; float * indicator; float * h2; compute_h2_variables compute_h2_vars; aux_variables aux_vars; size_t n_subjects; int stream_number; hipStream_t stream; }run_compute_h2_variables; typedef struct{ float * syP; float * d_F; float * d_score; float * d_Ts; float * d_a; float * d_sigmaP; }pval_variables; typedef struct{ float * d_F; float * d_pvals; float * d_boolean_score; float * pvals; float * d_hat; compute_h2_variables compute_h2_vars; aux_variables aux_vars; pval_variables pval_vars; size_t n_subjects; size_t n_permutations; int stream_number; bool covariates; hipStream_t stream; }run_compute_pval_variables; typedef struct{ float * h_y; float * h2; float * indicator; float * pvals; float * d_sy; float * d_F; float * d_hat; float * d_evectors; float * d_h2; float * d_indicator; float * d_pvals; float * h_evectors; float * h_hat; float * h_Z; unsigned int * h_pmatrix; unsigned int * d_pmatrix; compute_F_variables compute_F_vars; aux_variables aux_vars; compute_h2_variables compute_h2_vars; pval_variables pval_vars; bool covariates; bool get_pval; bool * d_boolean_score; size_t n_voxels; size_t n_subjects; size_t n_permutations; // size_t voxels_used; int device; hipStream_t stream; int stream_number; }cudafPHI_variables; int compute_h2(float * d_F, float * d_h2, float * d_indicator, bool * d_boolean_score, compute_h2_variables vars, aux_variables aux_vars, size_t n_subjects, size_t n_voxels, hipStream_t stream); int compute_F(float * d_hat, float* d_sy, float *d_evectors, float * d_F, compute_F_variables vars, bool covariates, size_t n_subjects, size_t n_voxels, hipStream_t stream); int compute_pvals(float * d_sy, float * d_res, float * d_hat, float * d_sigma_E, float * d_sigma_A, float * d_pvals, unsigned int * d_pmatrix, bool * h_boolean_score, aux_variables aux_vars, pval_variables pval_vars, bool covariate, size_t n_subjects, size_t n_voxels, size_t n_permutations, hipStream_t stream); void * run_cudafPHI_pthread(void * cudafPHI_args); void run_cudafPHI_loop(void * cudafPHI_args); void * run_compute_F_pthread(void * run_compute_F_args); void * run_compute_h2_pthread(void * run_compute_F_args); void * run_compute_pval_pthread(void * run_compute_F_args); void * run_allocation_test(void * cudafPHI_args); #endif /* CUDAFPHI_H_ */
.text .file "cudafPHI.hip" .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include "includes.h" __global__ void reduce(float* d_out, float* d_in) { // Parallel summation: steps = O(log(N)), work = O(N * log(N)) extern __shared__ float sdata[]; int globId = blockDim.x * blockIdx.x + threadIdx.x; int tid = threadIdx.x; sdata[tid] = d_in[globId]; __syncthreads(); int s = blockDim.x >> 1; while (s > 0) { if (tid < s) { sdata[tid] += sdata[tid + s]; } __syncthreads(); s >>= 1; } if (tid == 0) { d_out[blockIdx.x] = sdata[0]; } }
code for sm_80 Function : _Z6reducePfS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */ /* 0x000e220000002500 */ /*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */ /* 0x000fe200078e00ff */ /*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */ /* 0x000fe40000000a00 */ /*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */ /* 0x000e240000002100 */ /*0050*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */ /* 0x001fc800078e0207 */ /*0060*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */ /* 0x000fcc00078e0203 */ /*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */ /* 0x000ea2000c1e1900 */ /*0080*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */ /* 0x000fe20000000800 */ /*0090*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */ /* 0x000fe20003f05270 */ /*00a0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */ /* 0x000fcc0008011604 */ /*00b0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */ /* 0x000fe2000bf25270 */ /*00c0*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */ /* 0x0041e80000004800 */ /*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000ff00000010000 */ /*00e0*/ @!P1 BRA 0x1b0 ; /* 0x000000c000009947 */ /* 0x000fea0003800000 */ /*00f0*/ SHF.L.U32 R0, R7, 0x2, RZ ; /* 0x0000000207007819 */ /* 0x001fe200000006ff */ /*0100*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */ /* 0x000fca000f8e00ff */ /*0110*/ ISETP.GE.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */ /* 0x000fda0003f26270 */ /*0120*/ @!P1 LEA R2, R3, R0, 0x2 ; /* 0x0000000003029211 */ /* 0x000fe200078e10ff */ /*0130*/ @!P1 LDS R4, [R7.X4] ; /* 0x0000000007049984 */ /* 0x000fe20000004800 */ /*0140*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */ /* 0x000fc60000011603 */ /*0150*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */ /* 0x000e240000000800 */ /*0160*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */ /* 0x001fca0000000000 */ /*0170*/ @!P1 STS [R7.X4], R4 ; /* 0x0000000407009388 */ /* 0x0001e80000004800 */ /*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fe20000010000 */ /*0190*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */ /* 0x000fda0003f25270 */ /*01a0*/ @P1 BRA 0x110 ; /* 0xffffff6000001947 */ /* 0x001fea000383ffff */ /*01b0*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x001fea0003800000 */ /*01c0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */ /* 0x000e220000000800 */ /*01d0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */ /* 0x000fd400000001ff */ /*01e0*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x160] ; /* 0x0000580006027625 */ /* 0x000fca00078e0003 */ /*01f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */ /* 0x001fe2000c101906 */ /*0200*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0210*/ BRA 0x210; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0220*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0230*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0240*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0250*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0260*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0270*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0280*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0290*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include "includes.h" __global__ void reduce(float* d_out, float* d_in) { // Parallel summation: steps = O(log(N)), work = O(N * log(N)) extern __shared__ float sdata[]; int globId = blockDim.x * blockIdx.x + threadIdx.x; int tid = threadIdx.x; sdata[tid] = d_in[globId]; __syncthreads(); int s = blockDim.x >> 1; while (s > 0) { if (tid < s) { sdata[tid] += sdata[tid + s]; } __syncthreads(); s >>= 1; } if (tid == 0) { d_out[blockIdx.x] = sdata[0]; } }
.file "tmpxft_001ad25b_00000000-6_reduce.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z27__device_stub__Z6reducePfS_PfS_ .type _Z27__device_stub__Z6reducePfS_PfS_, @function _Z27__device_stub__Z6reducePfS_PfS_: .LFB2051: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z6reducePfS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z27__device_stub__Z6reducePfS_PfS_, .-_Z27__device_stub__Z6reducePfS_PfS_ .globl _Z6reducePfS_ .type _Z6reducePfS_, @function _Z6reducePfS_: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z27__device_stub__Z6reducePfS_PfS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z6reducePfS_, .-_Z6reducePfS_ .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z6reducePfS_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z6reducePfS_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include "includes.h" __global__ void reduce(float* d_out, float* d_in) { // Parallel summation: steps = O(log(N)), work = O(N * log(N)) extern __shared__ float sdata[]; int globId = blockDim.x * blockIdx.x + threadIdx.x; int tid = threadIdx.x; sdata[tid] = d_in[globId]; __syncthreads(); int s = blockDim.x >> 1; while (s > 0) { if (tid < s) { sdata[tid] += sdata[tid + s]; } __syncthreads(); s >>= 1; } if (tid == 0) { d_out[blockIdx.x] = sdata[0]; } }
#include <hip/hip_runtime.h> #include "includes.h" __global__ void reduce(float* d_out, float* d_in) { // Parallel summation: steps = O(log(N)), work = O(N * log(N)) extern __shared__ float sdata[]; int globId = blockDim.x * blockIdx.x + threadIdx.x; int tid = threadIdx.x; sdata[tid] = d_in[globId]; __syncthreads(); int s = blockDim.x >> 1; while (s > 0) { if (tid < s) { sdata[tid] += sdata[tid + s]; } __syncthreads(); s >>= 1; } if (tid == 0) { d_out[blockIdx.x] = sdata[0]; } }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void reduce(float* d_out, float* d_in) { // Parallel summation: steps = O(log(N)), work = O(N * log(N)) extern __shared__ float sdata[]; int globId = blockDim.x * blockIdx.x + threadIdx.x; int tid = threadIdx.x; sdata[tid] = d_in[globId]; __syncthreads(); int s = blockDim.x >> 1; while (s > 0) { if (tid < s) { sdata[tid] += sdata[tid + s]; } __syncthreads(); s >>= 1; } if (tid == 0) { d_out[blockIdx.x] = sdata[0]; } }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z6reducePfS_ .globl _Z6reducePfS_ .p2align 8 .type _Z6reducePfS_,@function _Z6reducePfS_: s_clause 0x1 s_load_b32 s3, s[0:1], 0x1c s_load_b64 s[4:5], s[0:1], 0x8 s_mov_b32 s2, s15 s_waitcnt lgkmcnt(0) s_and_b32 s3, s3, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1] s_cmp_lt_u32 s3, 2 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[1:2], 2, v[1:2] v_add_co_u32 v1, vcc_lo, s4, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo global_load_b32 v2, v[1:2], off v_lshl_add_u32 v1, v0, 2, 0 s_waitcnt vmcnt(0) ds_store_b32 v1, v2 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_cbranch_scc0 .LBB0_5 .LBB0_1: s_mov_b32 s3, exec_lo v_cmpx_eq_u32_e32 0, v0 s_cbranch_execz .LBB0_3 v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0 s_load_b64 s[0:1], s[0:1], 0x0 s_mov_b32 s3, 0 s_delay_alu instid0(SALU_CYCLE_1) s_lshl_b64 s[2:3], s[2:3], 2 ds_load_b32 v0, v0 s_waitcnt lgkmcnt(0) s_add_u32 s0, s0, s2 s_addc_u32 s1, s1, s3 global_store_b32 v1, v0, s[0:1] .LBB0_3: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .p2align 6 .LBB0_4: s_or_b32 exec_lo, exec_lo, s5 s_cmp_gt_u32 s3, 3 s_mov_b32 s3, s4 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_cbranch_scc0 .LBB0_1 .LBB0_5: s_lshr_b32 s4, s3, 1 s_mov_b32 s5, exec_lo v_cmpx_gt_u32_e64 s4, v0 s_cbranch_execz .LBB0_4 v_add_nc_u32_e32 v2, s4, v0 s_delay_alu instid0(VALU_DEP_1) v_lshl_add_u32 v2, v2, 2, 0 ds_load_b32 v2, v2 ds_load_b32 v3, v1 s_waitcnt lgkmcnt(0) v_add_f32_e32 v2, v2, v3 ds_store_b32 v1, v2 s_branch .LBB0_4 .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z6reducePfS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z6reducePfS_, .Lfunc_end0-_Z6reducePfS_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims - .offset: 136 .size: 4 .value_kind: hidden_dynamic_lds_size .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z6reducePfS_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z6reducePfS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void reduce(float* d_out, float* d_in) { // Parallel summation: steps = O(log(N)), work = O(N * log(N)) extern __shared__ float sdata[]; int globId = blockDim.x * blockIdx.x + threadIdx.x; int tid = threadIdx.x; sdata[tid] = d_in[globId]; __syncthreads(); int s = blockDim.x >> 1; while (s > 0) { if (tid < s) { sdata[tid] += sdata[tid + s]; } __syncthreads(); s >>= 1; } if (tid == 0) { d_out[blockIdx.x] = sdata[0]; } }
.text .file "reduce.hip" .globl _Z21__device_stub__reducePfS_ # -- Begin function _Z21__device_stub__reducePfS_ .p2align 4, 0x90 .type _Z21__device_stub__reducePfS_,@function _Z21__device_stub__reducePfS_: # @_Z21__device_stub__reducePfS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z6reducePfS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z21__device_stub__reducePfS_, .Lfunc_end0-_Z21__device_stub__reducePfS_ .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z6reducePfS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z6reducePfS_,@object # @_Z6reducePfS_ .section .rodata,"a",@progbits .globl _Z6reducePfS_ .p2align 3, 0x0 _Z6reducePfS_: .quad _Z21__device_stub__reducePfS_ .size _Z6reducePfS_, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z6reducePfS_" .size .L__unnamed_1, 14 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z21__device_stub__reducePfS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z6reducePfS_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z6reducePfS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */ /* 0x000e220000002500 */ /*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */ /* 0x000fe200078e00ff */ /*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */ /* 0x000fe40000000a00 */ /*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */ /* 0x000e240000002100 */ /*0050*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */ /* 0x001fc800078e0207 */ /*0060*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */ /* 0x000fcc00078e0203 */ /*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */ /* 0x000ea2000c1e1900 */ /*0080*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */ /* 0x000fe20000000800 */ /*0090*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */ /* 0x000fe20003f05270 */ /*00a0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */ /* 0x000fcc0008011604 */ /*00b0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */ /* 0x000fe2000bf25270 */ /*00c0*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */ /* 0x0041e80000004800 */ /*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000ff00000010000 */ /*00e0*/ @!P1 BRA 0x1b0 ; /* 0x000000c000009947 */ /* 0x000fea0003800000 */ /*00f0*/ SHF.L.U32 R0, R7, 0x2, RZ ; /* 0x0000000207007819 */ /* 0x001fe200000006ff */ /*0100*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */ /* 0x000fca000f8e00ff */ /*0110*/ ISETP.GE.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */ /* 0x000fda0003f26270 */ /*0120*/ @!P1 LEA R2, R3, R0, 0x2 ; /* 0x0000000003029211 */ /* 0x000fe200078e10ff */ /*0130*/ @!P1 LDS R4, [R7.X4] ; /* 0x0000000007049984 */ /* 0x000fe20000004800 */ /*0140*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */ /* 0x000fc60000011603 */ /*0150*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */ /* 0x000e240000000800 */ /*0160*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */ /* 0x001fca0000000000 */ /*0170*/ @!P1 STS [R7.X4], R4 ; /* 0x0000000407009388 */ /* 0x0001e80000004800 */ /*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fe20000010000 */ /*0190*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */ /* 0x000fda0003f25270 */ /*01a0*/ @P1 BRA 0x110 ; /* 0xffffff6000001947 */ /* 0x001fea000383ffff */ /*01b0*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x001fea0003800000 */ /*01c0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */ /* 0x000e220000000800 */ /*01d0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */ /* 0x000fd400000001ff */ /*01e0*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x160] ; /* 0x0000580006027625 */ /* 0x000fca00078e0003 */ /*01f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */ /* 0x001fe2000c101906 */ /*0200*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0210*/ BRA 0x210; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0220*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0230*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0240*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0250*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0260*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0270*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0280*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0290*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z6reducePfS_ .globl _Z6reducePfS_ .p2align 8 .type _Z6reducePfS_,@function _Z6reducePfS_: s_clause 0x1 s_load_b32 s3, s[0:1], 0x1c s_load_b64 s[4:5], s[0:1], 0x8 s_mov_b32 s2, s15 s_waitcnt lgkmcnt(0) s_and_b32 s3, s3, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1] s_cmp_lt_u32 s3, 2 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[1:2], 2, v[1:2] v_add_co_u32 v1, vcc_lo, s4, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo global_load_b32 v2, v[1:2], off v_lshl_add_u32 v1, v0, 2, 0 s_waitcnt vmcnt(0) ds_store_b32 v1, v2 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_cbranch_scc0 .LBB0_5 .LBB0_1: s_mov_b32 s3, exec_lo v_cmpx_eq_u32_e32 0, v0 s_cbranch_execz .LBB0_3 v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0 s_load_b64 s[0:1], s[0:1], 0x0 s_mov_b32 s3, 0 s_delay_alu instid0(SALU_CYCLE_1) s_lshl_b64 s[2:3], s[2:3], 2 ds_load_b32 v0, v0 s_waitcnt lgkmcnt(0) s_add_u32 s0, s0, s2 s_addc_u32 s1, s1, s3 global_store_b32 v1, v0, s[0:1] .LBB0_3: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .p2align 6 .LBB0_4: s_or_b32 exec_lo, exec_lo, s5 s_cmp_gt_u32 s3, 3 s_mov_b32 s3, s4 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_cbranch_scc0 .LBB0_1 .LBB0_5: s_lshr_b32 s4, s3, 1 s_mov_b32 s5, exec_lo v_cmpx_gt_u32_e64 s4, v0 s_cbranch_execz .LBB0_4 v_add_nc_u32_e32 v2, s4, v0 s_delay_alu instid0(VALU_DEP_1) v_lshl_add_u32 v2, v2, 2, 0 ds_load_b32 v2, v2 ds_load_b32 v3, v1 s_waitcnt lgkmcnt(0) v_add_f32_e32 v2, v2, v3 ds_store_b32 v1, v2 s_branch .LBB0_4 .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z6reducePfS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z6reducePfS_, .Lfunc_end0-_Z6reducePfS_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims - .offset: 136 .size: 4 .value_kind: hidden_dynamic_lds_size .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z6reducePfS_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z6reducePfS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_001ad25b_00000000-6_reduce.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z27__device_stub__Z6reducePfS_PfS_ .type _Z27__device_stub__Z6reducePfS_PfS_, @function _Z27__device_stub__Z6reducePfS_PfS_: .LFB2051: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z6reducePfS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z27__device_stub__Z6reducePfS_PfS_, .-_Z27__device_stub__Z6reducePfS_PfS_ .globl _Z6reducePfS_ .type _Z6reducePfS_, @function _Z6reducePfS_: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z27__device_stub__Z6reducePfS_PfS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z6reducePfS_, .-_Z6reducePfS_ .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z6reducePfS_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z6reducePfS_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "reduce.hip" .globl _Z21__device_stub__reducePfS_ # -- Begin function _Z21__device_stub__reducePfS_ .p2align 4, 0x90 .type _Z21__device_stub__reducePfS_,@function _Z21__device_stub__reducePfS_: # @_Z21__device_stub__reducePfS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z6reducePfS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z21__device_stub__reducePfS_, .Lfunc_end0-_Z21__device_stub__reducePfS_ .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z6reducePfS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z6reducePfS_,@object # @_Z6reducePfS_ .section .rodata,"a",@progbits .globl _Z6reducePfS_ .p2align 3, 0x0 _Z6reducePfS_: .quad _Z21__device_stub__reducePfS_ .size _Z6reducePfS_, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z6reducePfS_" .size .L__unnamed_1, 14 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z21__device_stub__reducePfS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z6reducePfS_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include <stdio.h> #include <stdlib.h> #include <time.h> #include "cuda.h" #include "cuda_runtime.h" #include "device_launch_parameters.h" __global__ void codeWithoutDivergence(){ int gid = blockIdx.x * blockDim.x + threadIdx.x; int a, b; a = b = 0; int warpId = gid / 32; if(warpId % 2 == 0){ a = 100; b = 50; } else { a = 200; b = 75; } } __global__ void codeWithDivergence(){ int gid = blockIdx.x * blockDim.x + threadIdx.x; int a, b; a = b = 0; if(gid % 2 == 0){ a = 100; b = 50; } else { a = 200; b = 75; } } int main(){ int size = 1 << 22; dim3 blockSize(128); dim3 gridSize((size + blockSize.x - 1)/blockSize.x); codeWithoutDivergence <<<gridSize, blockSize>>>(); cudaDeviceSynchronize(); codeWithDivergence <<<gridSize, blockSize>>>(); cudaDeviceReset(); return 0; }
code for sm_80 Function : _Z18codeWithDivergencev .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0020*/ BRA 0x20; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0030*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0040*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0050*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0060*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0070*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0080*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0090*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ .......... Function : _Z21codeWithoutDivergencev .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0020*/ BRA 0x20; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0030*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0040*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0050*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0060*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0070*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0080*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0090*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include <stdio.h> #include <stdlib.h> #include <time.h> #include "cuda.h" #include "cuda_runtime.h" #include "device_launch_parameters.h" __global__ void codeWithoutDivergence(){ int gid = blockIdx.x * blockDim.x + threadIdx.x; int a, b; a = b = 0; int warpId = gid / 32; if(warpId % 2 == 0){ a = 100; b = 50; } else { a = 200; b = 75; } } __global__ void codeWithDivergence(){ int gid = blockIdx.x * blockDim.x + threadIdx.x; int a, b; a = b = 0; if(gid % 2 == 0){ a = 100; b = 50; } else { a = 200; b = 75; } } int main(){ int size = 1 << 22; dim3 blockSize(128); dim3 gridSize((size + blockSize.x - 1)/blockSize.x); codeWithoutDivergence <<<gridSize, blockSize>>>(); cudaDeviceSynchronize(); codeWithDivergence <<<gridSize, blockSize>>>(); cudaDeviceReset(); return 0; }
.file "tmpxft_0002b22b_00000000-6_warpDivergence.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z40__device_stub__Z21codeWithoutDivergencevv .type _Z40__device_stub__Z21codeWithoutDivergencevv, @function _Z40__device_stub__Z21codeWithoutDivergencevv: .LFB2082: .cfi_startproc endbr64 subq $88, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax movl $1, 16(%rsp) movl $1, 20(%rsp) movl $1, 24(%rsp) movl $1, 28(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) leaq 8(%rsp), %rcx movq %rsp, %rdx leaq 28(%rsp), %rsi leaq 16(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 72(%rsp), %rax subq %fs:40, %rax jne .L8 addq $88, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 8(%rsp) .cfi_def_cfa_offset 104 pushq 8(%rsp) .cfi_def_cfa_offset 112 leaq 80(%rsp), %r9 movq 44(%rsp), %rcx movl 52(%rsp), %r8d movq 32(%rsp), %rsi movl 40(%rsp), %edx leaq _Z21codeWithoutDivergencev(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 96 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z40__device_stub__Z21codeWithoutDivergencevv, .-_Z40__device_stub__Z21codeWithoutDivergencevv .globl _Z21codeWithoutDivergencev .type _Z21codeWithoutDivergencev, @function _Z21codeWithoutDivergencev: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z40__device_stub__Z21codeWithoutDivergencevv addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z21codeWithoutDivergencev, .-_Z21codeWithoutDivergencev .globl _Z37__device_stub__Z18codeWithDivergencevv .type _Z37__device_stub__Z18codeWithDivergencevv, @function _Z37__device_stub__Z18codeWithDivergencevv: .LFB2084: .cfi_startproc endbr64 subq $88, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax movl $1, 16(%rsp) movl $1, 20(%rsp) movl $1, 24(%rsp) movl $1, 28(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) leaq 8(%rsp), %rcx movq %rsp, %rdx leaq 28(%rsp), %rsi leaq 16(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L15 .L11: movq 72(%rsp), %rax subq %fs:40, %rax jne .L16 addq $88, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state pushq 8(%rsp) .cfi_def_cfa_offset 104 pushq 8(%rsp) .cfi_def_cfa_offset 112 leaq 80(%rsp), %r9 movq 44(%rsp), %rcx movl 52(%rsp), %r8d movq 32(%rsp), %rsi movl 40(%rsp), %edx leaq _Z18codeWithDivergencev(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 96 jmp .L11 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE2084: .size _Z37__device_stub__Z18codeWithDivergencevv, .-_Z37__device_stub__Z18codeWithDivergencevv .globl _Z18codeWithDivergencev .type _Z18codeWithDivergencev, @function _Z18codeWithDivergencev: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z37__device_stub__Z18codeWithDivergencevv addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _Z18codeWithDivergencev, .-_Z18codeWithDivergencev .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 subq $40, %rsp .cfi_def_cfa_offset 48 movl $1, 12(%rsp) movl $1, 16(%rsp) movl $32768, 20(%rsp) movl $1, 24(%rsp) movl $1, 28(%rsp) movl $128, 8(%rsp) movl $0, %r9d movl $0, %r8d movq 8(%rsp), %rdx movl $1, %ecx movq 20(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L23 .L20: call cudaDeviceSynchronize@PLT movl 16(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 8(%rsp), %rdx movq 20(%rsp), %rdi movl 28(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L24 .L21: call cudaDeviceReset@PLT movl $0, %eax addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L23: .cfi_restore_state call _Z40__device_stub__Z21codeWithoutDivergencevv jmp .L20 .L24: call _Z37__device_stub__Z18codeWithDivergencevv jmp .L21 .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z18codeWithDivergencev" .LC1: .string "_Z21codeWithoutDivergencev" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2087: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z18codeWithDivergencev(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _Z21codeWithoutDivergencev(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2087: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include <stdio.h> #include <stdlib.h> #include <time.h> #include "cuda.h" #include "cuda_runtime.h" #include "device_launch_parameters.h" __global__ void codeWithoutDivergence(){ int gid = blockIdx.x * blockDim.x + threadIdx.x; int a, b; a = b = 0; int warpId = gid / 32; if(warpId % 2 == 0){ a = 100; b = 50; } else { a = 200; b = 75; } } __global__ void codeWithDivergence(){ int gid = blockIdx.x * blockDim.x + threadIdx.x; int a, b; a = b = 0; if(gid % 2 == 0){ a = 100; b = 50; } else { a = 200; b = 75; } } int main(){ int size = 1 << 22; dim3 blockSize(128); dim3 gridSize((size + blockSize.x - 1)/blockSize.x); codeWithoutDivergence <<<gridSize, blockSize>>>(); cudaDeviceSynchronize(); codeWithDivergence <<<gridSize, blockSize>>>(); cudaDeviceReset(); return 0; }
#include <stdio.h> #include <stdlib.h> #include <time.h> #include "hip/hip_runtime.h" __global__ void codeWithoutDivergence(){ int gid = blockIdx.x * blockDim.x + threadIdx.x; int a, b; a = b = 0; int warpId = gid / 32; if(warpId % 2 == 0){ a = 100; b = 50; } else { a = 200; b = 75; } } __global__ void codeWithDivergence(){ int gid = blockIdx.x * blockDim.x + threadIdx.x; int a, b; a = b = 0; if(gid % 2 == 0){ a = 100; b = 50; } else { a = 200; b = 75; } } int main(){ int size = 1 << 22; dim3 blockSize(128); dim3 gridSize((size + blockSize.x - 1)/blockSize.x); codeWithoutDivergence <<<gridSize, blockSize>>>(); hipDeviceSynchronize(); codeWithDivergence <<<gridSize, blockSize>>>(); hipDeviceReset(); return 0; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <stdio.h> #include <stdlib.h> #include <time.h> #include "hip/hip_runtime.h" __global__ void codeWithoutDivergence(){ int gid = blockIdx.x * blockDim.x + threadIdx.x; int a, b; a = b = 0; int warpId = gid / 32; if(warpId % 2 == 0){ a = 100; b = 50; } else { a = 200; b = 75; } } __global__ void codeWithDivergence(){ int gid = blockIdx.x * blockDim.x + threadIdx.x; int a, b; a = b = 0; if(gid % 2 == 0){ a = 100; b = 50; } else { a = 200; b = 75; } } int main(){ int size = 1 << 22; dim3 blockSize(128); dim3 gridSize((size + blockSize.x - 1)/blockSize.x); codeWithoutDivergence <<<gridSize, blockSize>>>(); hipDeviceSynchronize(); codeWithDivergence <<<gridSize, blockSize>>>(); hipDeviceReset(); return 0; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z21codeWithoutDivergencev .globl _Z21codeWithoutDivergencev .p2align 8 .type _Z21codeWithoutDivergencev,@function _Z21codeWithoutDivergencev: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z21codeWithoutDivergencev .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 0 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 0 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 1 .amdhsa_next_free_sgpr 1 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z21codeWithoutDivergencev, .Lfunc_end0-_Z21codeWithoutDivergencev .section .AMDGPU.csdata,"",@progbits .text .protected _Z18codeWithDivergencev .globl _Z18codeWithDivergencev .p2align 8 .type _Z18codeWithDivergencev,@function _Z18codeWithDivergencev: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z18codeWithDivergencev .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 0 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 0 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 1 .amdhsa_next_free_sgpr 1 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z18codeWithDivergencev, .Lfunc_end1-_Z18codeWithDivergencev .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: [] .group_segment_fixed_size: 0 .kernarg_segment_align: 4 .kernarg_segment_size: 0 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z21codeWithoutDivergencev .private_segment_fixed_size: 0 .sgpr_count: 0 .sgpr_spill_count: 0 .symbol: _Z21codeWithoutDivergencev.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 0 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: [] .group_segment_fixed_size: 0 .kernarg_segment_align: 4 .kernarg_segment_size: 0 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z18codeWithDivergencev .private_segment_fixed_size: 0 .sgpr_count: 0 .sgpr_spill_count: 0 .symbol: _Z18codeWithDivergencev.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 0 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <stdio.h> #include <stdlib.h> #include <time.h> #include "hip/hip_runtime.h" __global__ void codeWithoutDivergence(){ int gid = blockIdx.x * blockDim.x + threadIdx.x; int a, b; a = b = 0; int warpId = gid / 32; if(warpId % 2 == 0){ a = 100; b = 50; } else { a = 200; b = 75; } } __global__ void codeWithDivergence(){ int gid = blockIdx.x * blockDim.x + threadIdx.x; int a, b; a = b = 0; if(gid % 2 == 0){ a = 100; b = 50; } else { a = 200; b = 75; } } int main(){ int size = 1 << 22; dim3 blockSize(128); dim3 gridSize((size + blockSize.x - 1)/blockSize.x); codeWithoutDivergence <<<gridSize, blockSize>>>(); hipDeviceSynchronize(); codeWithDivergence <<<gridSize, blockSize>>>(); hipDeviceReset(); return 0; }
.text .file "warpDivergence.hip" .globl _Z36__device_stub__codeWithoutDivergencev # -- Begin function _Z36__device_stub__codeWithoutDivergencev .p2align 4, 0x90 .type _Z36__device_stub__codeWithoutDivergencev,@function _Z36__device_stub__codeWithoutDivergencev: # @_Z36__device_stub__codeWithoutDivergencev .cfi_startproc # %bb.0: subq $56, %rsp .cfi_def_cfa_offset 64 leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 48(%rsp), %r9 movl $_Z21codeWithoutDivergencev, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $72, %rsp .cfi_adjust_cfa_offset -72 retq .Lfunc_end0: .size _Z36__device_stub__codeWithoutDivergencev, .Lfunc_end0-_Z36__device_stub__codeWithoutDivergencev .cfi_endproc # -- End function .globl _Z33__device_stub__codeWithDivergencev # -- Begin function _Z33__device_stub__codeWithDivergencev .p2align 4, 0x90 .type _Z33__device_stub__codeWithDivergencev,@function _Z33__device_stub__codeWithDivergencev: # @_Z33__device_stub__codeWithDivergencev .cfi_startproc # %bb.0: subq $56, %rsp .cfi_def_cfa_offset 64 leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 48(%rsp), %r9 movl $_Z18codeWithDivergencev, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $72, %rsp .cfi_adjust_cfa_offset -72 retq .Lfunc_end1: .size _Z33__device_stub__codeWithDivergencev, .Lfunc_end1-_Z33__device_stub__codeWithDivergencev .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $56, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movabsq $4294967424, %rbx # imm = 0x100000080 leaq 32640(%rbx), %r14 movq %r14, %rdi movl $1, %esi movq %rbx, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_2 # %bb.1: leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 48(%rsp), %r9 movl $_Z21codeWithoutDivergencev, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB2_2: callq hipDeviceSynchronize movq %r14, %rdi movl $1, %esi movq %rbx, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_4 # %bb.3: leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 48(%rsp), %r9 movl $_Z18codeWithDivergencev, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB2_4: callq hipDeviceReset xorl %eax, %eax addq $56, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z21codeWithoutDivergencev, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z18codeWithDivergencev, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z21codeWithoutDivergencev,@object # @_Z21codeWithoutDivergencev .section .rodata,"a",@progbits .globl _Z21codeWithoutDivergencev .p2align 3, 0x0 _Z21codeWithoutDivergencev: .quad _Z36__device_stub__codeWithoutDivergencev .size _Z21codeWithoutDivergencev, 8 .type _Z18codeWithDivergencev,@object # @_Z18codeWithDivergencev .globl _Z18codeWithDivergencev .p2align 3, 0x0 _Z18codeWithDivergencev: .quad _Z33__device_stub__codeWithDivergencev .size _Z18codeWithDivergencev, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z21codeWithoutDivergencev" .size .L__unnamed_1, 27 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z18codeWithDivergencev" .size .L__unnamed_2, 24 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z36__device_stub__codeWithoutDivergencev .addrsig_sym _Z33__device_stub__codeWithDivergencev .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z21codeWithoutDivergencev .addrsig_sym _Z18codeWithDivergencev .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z18codeWithDivergencev .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0020*/ BRA 0x20; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0030*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0040*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0050*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0060*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0070*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0080*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0090*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ .......... Function : _Z21codeWithoutDivergencev .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0020*/ BRA 0x20; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0030*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0040*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0050*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0060*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0070*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0080*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0090*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z21codeWithoutDivergencev .globl _Z21codeWithoutDivergencev .p2align 8 .type _Z21codeWithoutDivergencev,@function _Z21codeWithoutDivergencev: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z21codeWithoutDivergencev .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 0 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 0 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 1 .amdhsa_next_free_sgpr 1 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z21codeWithoutDivergencev, .Lfunc_end0-_Z21codeWithoutDivergencev .section .AMDGPU.csdata,"",@progbits .text .protected _Z18codeWithDivergencev .globl _Z18codeWithDivergencev .p2align 8 .type _Z18codeWithDivergencev,@function _Z18codeWithDivergencev: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z18codeWithDivergencev .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 0 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 0 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 1 .amdhsa_next_free_sgpr 1 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z18codeWithDivergencev, .Lfunc_end1-_Z18codeWithDivergencev .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: [] .group_segment_fixed_size: 0 .kernarg_segment_align: 4 .kernarg_segment_size: 0 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z21codeWithoutDivergencev .private_segment_fixed_size: 0 .sgpr_count: 0 .sgpr_spill_count: 0 .symbol: _Z21codeWithoutDivergencev.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 0 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: [] .group_segment_fixed_size: 0 .kernarg_segment_align: 4 .kernarg_segment_size: 0 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z18codeWithDivergencev .private_segment_fixed_size: 0 .sgpr_count: 0 .sgpr_spill_count: 0 .symbol: _Z18codeWithDivergencev.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 0 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_0002b22b_00000000-6_warpDivergence.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z40__device_stub__Z21codeWithoutDivergencevv .type _Z40__device_stub__Z21codeWithoutDivergencevv, @function _Z40__device_stub__Z21codeWithoutDivergencevv: .LFB2082: .cfi_startproc endbr64 subq $88, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax movl $1, 16(%rsp) movl $1, 20(%rsp) movl $1, 24(%rsp) movl $1, 28(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) leaq 8(%rsp), %rcx movq %rsp, %rdx leaq 28(%rsp), %rsi leaq 16(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 72(%rsp), %rax subq %fs:40, %rax jne .L8 addq $88, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 8(%rsp) .cfi_def_cfa_offset 104 pushq 8(%rsp) .cfi_def_cfa_offset 112 leaq 80(%rsp), %r9 movq 44(%rsp), %rcx movl 52(%rsp), %r8d movq 32(%rsp), %rsi movl 40(%rsp), %edx leaq _Z21codeWithoutDivergencev(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 96 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z40__device_stub__Z21codeWithoutDivergencevv, .-_Z40__device_stub__Z21codeWithoutDivergencevv .globl _Z21codeWithoutDivergencev .type _Z21codeWithoutDivergencev, @function _Z21codeWithoutDivergencev: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z40__device_stub__Z21codeWithoutDivergencevv addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z21codeWithoutDivergencev, .-_Z21codeWithoutDivergencev .globl _Z37__device_stub__Z18codeWithDivergencevv .type _Z37__device_stub__Z18codeWithDivergencevv, @function _Z37__device_stub__Z18codeWithDivergencevv: .LFB2084: .cfi_startproc endbr64 subq $88, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax movl $1, 16(%rsp) movl $1, 20(%rsp) movl $1, 24(%rsp) movl $1, 28(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) leaq 8(%rsp), %rcx movq %rsp, %rdx leaq 28(%rsp), %rsi leaq 16(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L15 .L11: movq 72(%rsp), %rax subq %fs:40, %rax jne .L16 addq $88, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state pushq 8(%rsp) .cfi_def_cfa_offset 104 pushq 8(%rsp) .cfi_def_cfa_offset 112 leaq 80(%rsp), %r9 movq 44(%rsp), %rcx movl 52(%rsp), %r8d movq 32(%rsp), %rsi movl 40(%rsp), %edx leaq _Z18codeWithDivergencev(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 96 jmp .L11 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE2084: .size _Z37__device_stub__Z18codeWithDivergencevv, .-_Z37__device_stub__Z18codeWithDivergencevv .globl _Z18codeWithDivergencev .type _Z18codeWithDivergencev, @function _Z18codeWithDivergencev: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z37__device_stub__Z18codeWithDivergencevv addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _Z18codeWithDivergencev, .-_Z18codeWithDivergencev .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 subq $40, %rsp .cfi_def_cfa_offset 48 movl $1, 12(%rsp) movl $1, 16(%rsp) movl $32768, 20(%rsp) movl $1, 24(%rsp) movl $1, 28(%rsp) movl $128, 8(%rsp) movl $0, %r9d movl $0, %r8d movq 8(%rsp), %rdx movl $1, %ecx movq 20(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L23 .L20: call cudaDeviceSynchronize@PLT movl 16(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 8(%rsp), %rdx movq 20(%rsp), %rdi movl 28(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L24 .L21: call cudaDeviceReset@PLT movl $0, %eax addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L23: .cfi_restore_state call _Z40__device_stub__Z21codeWithoutDivergencevv jmp .L20 .L24: call _Z37__device_stub__Z18codeWithDivergencevv jmp .L21 .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z18codeWithDivergencev" .LC1: .string "_Z21codeWithoutDivergencev" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2087: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z18codeWithDivergencev(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _Z21codeWithoutDivergencev(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2087: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "warpDivergence.hip" .globl _Z36__device_stub__codeWithoutDivergencev # -- Begin function _Z36__device_stub__codeWithoutDivergencev .p2align 4, 0x90 .type _Z36__device_stub__codeWithoutDivergencev,@function _Z36__device_stub__codeWithoutDivergencev: # @_Z36__device_stub__codeWithoutDivergencev .cfi_startproc # %bb.0: subq $56, %rsp .cfi_def_cfa_offset 64 leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 48(%rsp), %r9 movl $_Z21codeWithoutDivergencev, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $72, %rsp .cfi_adjust_cfa_offset -72 retq .Lfunc_end0: .size _Z36__device_stub__codeWithoutDivergencev, .Lfunc_end0-_Z36__device_stub__codeWithoutDivergencev .cfi_endproc # -- End function .globl _Z33__device_stub__codeWithDivergencev # -- Begin function _Z33__device_stub__codeWithDivergencev .p2align 4, 0x90 .type _Z33__device_stub__codeWithDivergencev,@function _Z33__device_stub__codeWithDivergencev: # @_Z33__device_stub__codeWithDivergencev .cfi_startproc # %bb.0: subq $56, %rsp .cfi_def_cfa_offset 64 leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 48(%rsp), %r9 movl $_Z18codeWithDivergencev, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $72, %rsp .cfi_adjust_cfa_offset -72 retq .Lfunc_end1: .size _Z33__device_stub__codeWithDivergencev, .Lfunc_end1-_Z33__device_stub__codeWithDivergencev .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $56, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movabsq $4294967424, %rbx # imm = 0x100000080 leaq 32640(%rbx), %r14 movq %r14, %rdi movl $1, %esi movq %rbx, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_2 # %bb.1: leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 48(%rsp), %r9 movl $_Z21codeWithoutDivergencev, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB2_2: callq hipDeviceSynchronize movq %r14, %rdi movl $1, %esi movq %rbx, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_4 # %bb.3: leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 48(%rsp), %r9 movl $_Z18codeWithDivergencev, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB2_4: callq hipDeviceReset xorl %eax, %eax addq $56, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z21codeWithoutDivergencev, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z18codeWithDivergencev, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z21codeWithoutDivergencev,@object # @_Z21codeWithoutDivergencev .section .rodata,"a",@progbits .globl _Z21codeWithoutDivergencev .p2align 3, 0x0 _Z21codeWithoutDivergencev: .quad _Z36__device_stub__codeWithoutDivergencev .size _Z21codeWithoutDivergencev, 8 .type _Z18codeWithDivergencev,@object # @_Z18codeWithDivergencev .globl _Z18codeWithDivergencev .p2align 3, 0x0 _Z18codeWithDivergencev: .quad _Z33__device_stub__codeWithDivergencev .size _Z18codeWithDivergencev, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z21codeWithoutDivergencev" .size .L__unnamed_1, 27 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z18codeWithDivergencev" .size .L__unnamed_2, 24 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z36__device_stub__codeWithoutDivergencev .addrsig_sym _Z33__device_stub__codeWithDivergencev .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z21codeWithoutDivergencev .addrsig_sym _Z18codeWithDivergencev .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include "includes.h" __global__ void cuda_deactivateTanh(double* pE, const double* pA, int n) { int id = blockIdx.x * blockDim.x + threadIdx.x; if (id < n) { pE[id] *= (1.0 - (pA[id] * pA[id])); } }
code for sm_80 Function : _Z19cuda_deactivateTanhPdPKdi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */ /* 0x000e280000002500 */ /*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */ /* 0x001fca00078e0203 */ /*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */ /* 0x000fda0003f06270 */ /*0050*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */ /* 0x000fe200000001ff */ /*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd20000000a00 */ /*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */ /* 0x000fc800078e0207 */ /*0090*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */ /* 0x000fe400078e0207 */ /*00a0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x000ea8000c1e1b00 */ /*00b0*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */ /* 0x000ee2000c1e1b00 */ /*00c0*/ DFMA R4, -R2, R2, 1 ; /* 0x3ff000000204742b */ /* 0x004ecc0000000102 */ /*00d0*/ DMUL R4, R4, R8 ; /* 0x0000000804047228 */ /* 0x008e0e0000000000 */ /*00e0*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */ /* 0x001fe2000c101b04 */ /*00f0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0100*/ BRA 0x100; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0110*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0120*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0130*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include "includes.h" __global__ void cuda_deactivateTanh(double* pE, const double* pA, int n) { int id = blockIdx.x * blockDim.x + threadIdx.x; if (id < n) { pE[id] *= (1.0 - (pA[id] * pA[id])); } }
.file "tmpxft_0013402f_00000000-6_cuda_deactivateTanh.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z43__device_stub__Z19cuda_deactivateTanhPdPKdiPdPKdi .type _Z43__device_stub__Z19cuda_deactivateTanhPdPKdiPdPKdi, @function _Z43__device_stub__Z19cuda_deactivateTanhPdPKdiPdPKdi: .LFB2051: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 120(%rsp), %rax subq %fs:40, %rax jne .L8 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z19cuda_deactivateTanhPdPKdi(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z43__device_stub__Z19cuda_deactivateTanhPdPKdiPdPKdi, .-_Z43__device_stub__Z19cuda_deactivateTanhPdPKdiPdPKdi .globl _Z19cuda_deactivateTanhPdPKdi .type _Z19cuda_deactivateTanhPdPKdi, @function _Z19cuda_deactivateTanhPdPKdi: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z43__device_stub__Z19cuda_deactivateTanhPdPKdiPdPKdi addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z19cuda_deactivateTanhPdPKdi, .-_Z19cuda_deactivateTanhPdPKdi .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z19cuda_deactivateTanhPdPKdi" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z19cuda_deactivateTanhPdPKdi(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include "includes.h" __global__ void cuda_deactivateTanh(double* pE, const double* pA, int n) { int id = blockIdx.x * blockDim.x + threadIdx.x; if (id < n) { pE[id] *= (1.0 - (pA[id] * pA[id])); } }
#include <hip/hip_runtime.h> #include "includes.h" __global__ void cuda_deactivateTanh(double* pE, const double* pA, int n) { int id = blockIdx.x * blockDim.x + threadIdx.x; if (id < n) { pE[id] *= (1.0 - (pA[id] * pA[id])); } }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void cuda_deactivateTanh(double* pE, const double* pA, int n) { int id = blockIdx.x * blockDim.x + threadIdx.x; if (id < n) { pE[id] *= (1.0 - (pA[id] * pA[id])); } }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z19cuda_deactivateTanhPdPKdi .globl _Z19cuda_deactivateTanhPdPKdi .p2align 8 .type _Z19cuda_deactivateTanhPdPKdi,@function _Z19cuda_deactivateTanhPdPKdi: s_clause 0x1 s_load_b32 s2, s[0:1], 0x24 s_load_b32 s3, s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_2 s_load_b128 s[0:3], s[0:1], 0x0 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 3, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s2, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_load_b64 v[2:3], v[2:3], off global_load_b64 v[4:5], v[0:1], off s_waitcnt vmcnt(1) v_fma_f64 v[2:3], -v[2:3], v[2:3], 1.0 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) v_mul_f64 v[2:3], v[4:5], v[2:3] global_store_b64 v[0:1], v[2:3], off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z19cuda_deactivateTanhPdPKdi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z19cuda_deactivateTanhPdPKdi, .Lfunc_end0-_Z19cuda_deactivateTanhPdPKdi .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z19cuda_deactivateTanhPdPKdi .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z19cuda_deactivateTanhPdPKdi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void cuda_deactivateTanh(double* pE, const double* pA, int n) { int id = blockIdx.x * blockDim.x + threadIdx.x; if (id < n) { pE[id] *= (1.0 - (pA[id] * pA[id])); } }
.text .file "cuda_deactivateTanh.hip" .globl _Z34__device_stub__cuda_deactivateTanhPdPKdi # -- Begin function _Z34__device_stub__cuda_deactivateTanhPdPKdi .p2align 4, 0x90 .type _Z34__device_stub__cuda_deactivateTanhPdPKdi,@function _Z34__device_stub__cuda_deactivateTanhPdPKdi: # @_Z34__device_stub__cuda_deactivateTanhPdPKdi .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z19cuda_deactivateTanhPdPKdi, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z34__device_stub__cuda_deactivateTanhPdPKdi, .Lfunc_end0-_Z34__device_stub__cuda_deactivateTanhPdPKdi .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z19cuda_deactivateTanhPdPKdi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z19cuda_deactivateTanhPdPKdi,@object # @_Z19cuda_deactivateTanhPdPKdi .section .rodata,"a",@progbits .globl _Z19cuda_deactivateTanhPdPKdi .p2align 3, 0x0 _Z19cuda_deactivateTanhPdPKdi: .quad _Z34__device_stub__cuda_deactivateTanhPdPKdi .size _Z19cuda_deactivateTanhPdPKdi, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z19cuda_deactivateTanhPdPKdi" .size .L__unnamed_1, 30 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z34__device_stub__cuda_deactivateTanhPdPKdi .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z19cuda_deactivateTanhPdPKdi .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z19cuda_deactivateTanhPdPKdi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */ /* 0x000e280000002500 */ /*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */ /* 0x001fca00078e0203 */ /*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */ /* 0x000fda0003f06270 */ /*0050*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */ /* 0x000fe200000001ff */ /*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd20000000a00 */ /*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */ /* 0x000fc800078e0207 */ /*0090*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */ /* 0x000fe400078e0207 */ /*00a0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x000ea8000c1e1b00 */ /*00b0*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */ /* 0x000ee2000c1e1b00 */ /*00c0*/ DFMA R4, -R2, R2, 1 ; /* 0x3ff000000204742b */ /* 0x004ecc0000000102 */ /*00d0*/ DMUL R4, R4, R8 ; /* 0x0000000804047228 */ /* 0x008e0e0000000000 */ /*00e0*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */ /* 0x001fe2000c101b04 */ /*00f0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0100*/ BRA 0x100; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0110*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0120*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0130*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z19cuda_deactivateTanhPdPKdi .globl _Z19cuda_deactivateTanhPdPKdi .p2align 8 .type _Z19cuda_deactivateTanhPdPKdi,@function _Z19cuda_deactivateTanhPdPKdi: s_clause 0x1 s_load_b32 s2, s[0:1], 0x24 s_load_b32 s3, s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_2 s_load_b128 s[0:3], s[0:1], 0x0 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 3, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s2, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_load_b64 v[2:3], v[2:3], off global_load_b64 v[4:5], v[0:1], off s_waitcnt vmcnt(1) v_fma_f64 v[2:3], -v[2:3], v[2:3], 1.0 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) v_mul_f64 v[2:3], v[4:5], v[2:3] global_store_b64 v[0:1], v[2:3], off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z19cuda_deactivateTanhPdPKdi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z19cuda_deactivateTanhPdPKdi, .Lfunc_end0-_Z19cuda_deactivateTanhPdPKdi .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z19cuda_deactivateTanhPdPKdi .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z19cuda_deactivateTanhPdPKdi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_0013402f_00000000-6_cuda_deactivateTanh.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z43__device_stub__Z19cuda_deactivateTanhPdPKdiPdPKdi .type _Z43__device_stub__Z19cuda_deactivateTanhPdPKdiPdPKdi, @function _Z43__device_stub__Z19cuda_deactivateTanhPdPKdiPdPKdi: .LFB2051: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 120(%rsp), %rax subq %fs:40, %rax jne .L8 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z19cuda_deactivateTanhPdPKdi(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z43__device_stub__Z19cuda_deactivateTanhPdPKdiPdPKdi, .-_Z43__device_stub__Z19cuda_deactivateTanhPdPKdiPdPKdi .globl _Z19cuda_deactivateTanhPdPKdi .type _Z19cuda_deactivateTanhPdPKdi, @function _Z19cuda_deactivateTanhPdPKdi: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z43__device_stub__Z19cuda_deactivateTanhPdPKdiPdPKdi addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z19cuda_deactivateTanhPdPKdi, .-_Z19cuda_deactivateTanhPdPKdi .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z19cuda_deactivateTanhPdPKdi" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z19cuda_deactivateTanhPdPKdi(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "cuda_deactivateTanh.hip" .globl _Z34__device_stub__cuda_deactivateTanhPdPKdi # -- Begin function _Z34__device_stub__cuda_deactivateTanhPdPKdi .p2align 4, 0x90 .type _Z34__device_stub__cuda_deactivateTanhPdPKdi,@function _Z34__device_stub__cuda_deactivateTanhPdPKdi: # @_Z34__device_stub__cuda_deactivateTanhPdPKdi .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z19cuda_deactivateTanhPdPKdi, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z34__device_stub__cuda_deactivateTanhPdPKdi, .Lfunc_end0-_Z34__device_stub__cuda_deactivateTanhPdPKdi .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z19cuda_deactivateTanhPdPKdi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z19cuda_deactivateTanhPdPKdi,@object # @_Z19cuda_deactivateTanhPdPKdi .section .rodata,"a",@progbits .globl _Z19cuda_deactivateTanhPdPKdi .p2align 3, 0x0 _Z19cuda_deactivateTanhPdPKdi: .quad _Z34__device_stub__cuda_deactivateTanhPdPKdi .size _Z19cuda_deactivateTanhPdPKdi, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z19cuda_deactivateTanhPdPKdi" .size .L__unnamed_1, 30 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z34__device_stub__cuda_deactivateTanhPdPKdi .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z19cuda_deactivateTanhPdPKdi .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
__global__ void t_sum(float *a, float *out, int n_elements) { const int i = blockDim.x * blockIdx.x + threadIdx.x; if (i == 0) out[0] = 0; __syncthreads(); if (i < n_elements) atomicAdd(out, a[i]); }
code for sm_80 Function : _Z5t_sumPfS_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */ /* 0x000e220000002500 */ /*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */ /* 0x000fe200078e00ff */ /*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe40000000a00 */ /*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */ /* 0x001fe200078e0203 */ /*0060*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */ /* 0x000fc80000000f00 */ /*0070*/ ISETP.NE.AND P0, PT, R4.reuse, RZ, PT ; /* 0x000000ff0400720c */ /* 0x040fe40003f05270 */ /*0080*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */ /* 0x000fd60003f26270 */ /*0090*/ @!P0 STG.E [R2.64], RZ ; /* 0x000000ff02008986 */ /* 0x0001e8000c101904 */ /*00a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*00b0*/ @P1 EXIT ; /* 0x000000000000194d */ /* 0x000fea0003800000 */ /*00c0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */ /* 0x001fd400000001ff */ /*00d0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */ /* 0x000fcc00078e0205 */ /*00e0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */ /* 0x000ea8000c1e1900 */ /*00f0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */ /* 0x004fe2000c10e784 */ /*0100*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0110*/ BRA 0x110; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0120*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0130*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
__global__ void t_sum(float *a, float *out, int n_elements) { const int i = blockDim.x * blockIdx.x + threadIdx.x; if (i == 0) out[0] = 0; __syncthreads(); if (i < n_elements) atomicAdd(out, a[i]); }
.file "tmpxft_00010d30_00000000-6_t_sum.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z27__device_stub__Z5t_sumPfS_iPfS_i .type _Z27__device_stub__Z5t_sumPfS_iPfS_i, @function _Z27__device_stub__Z5t_sumPfS_iPfS_i: .LFB2051: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 120(%rsp), %rax subq %fs:40, %rax jne .L8 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z5t_sumPfS_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z27__device_stub__Z5t_sumPfS_iPfS_i, .-_Z27__device_stub__Z5t_sumPfS_iPfS_i .globl _Z5t_sumPfS_i .type _Z5t_sumPfS_i, @function _Z5t_sumPfS_i: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z27__device_stub__Z5t_sumPfS_iPfS_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z5t_sumPfS_i, .-_Z5t_sumPfS_i .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z5t_sumPfS_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z5t_sumPfS_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
__global__ void t_sum(float *a, float *out, int n_elements) { const int i = blockDim.x * blockIdx.x + threadIdx.x; if (i == 0) out[0] = 0; __syncthreads(); if (i < n_elements) atomicAdd(out, a[i]); }
#include <hip/hip_runtime.h> __global__ void t_sum(float *a, float *out, int n_elements) { const int i = blockDim.x * blockIdx.x + threadIdx.x; if (i == 0) out[0] = 0; __syncthreads(); if (i < n_elements) atomicAdd(out, a[i]); }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> __global__ void t_sum(float *a, float *out, int n_elements) { const int i = blockDim.x * blockIdx.x + threadIdx.x; if (i == 0) out[0] = 0; __syncthreads(); if (i < n_elements) atomicAdd(out, a[i]); }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z5t_sumPfS_i .globl _Z5t_sumPfS_i .p2align 8 .type _Z5t_sumPfS_i,@function _Z5t_sumPfS_i: s_clause 0x1 s_load_b32 s4, s[0:1], 0x24 s_load_b64 s[2:3], s[0:1], 0x8 s_waitcnt lgkmcnt(0) s_and_b32 s4, s4, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1] s_mov_b32 s4, exec_lo v_cmpx_eq_u32_e32 0, v1 s_cbranch_execz .LBB0_2 v_mov_b32_e32 v0, 0 global_store_b32 v0, v0, s[2:3] .LBB0_2: s_or_b32 exec_lo, exec_lo, s4 s_load_b32 s4, s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv v_cmp_gt_i32_e32 vcc_lo, s4, v1 s_and_saveexec_b32 s4, vcc_lo s_cbranch_execz .LBB0_8 s_load_b64 s[0:1], s[0:1], 0x0 v_ashrrev_i32_e32 v2, 31, v1 s_mov_b32 s4, exec_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_lshlrev_b64 v[0:1], 2, v[1:2] v_bfrev_b32_e32 v2, 1 s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_3) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_load_b32 v0, v[0:1], off .LBB0_4: s_ctz_i32_b32 s0, s4 s_waitcnt vmcnt(0) v_readlane_b32 s1, v0, s0 s_lshl_b32 s0, 1, s0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_not1_b32 s4, s4, s0 s_cmp_lg_u32 s4, 0 s_delay_alu instid0(VALU_DEP_1) v_add_f32_e32 v2, s1, v2 s_cbranch_scc1 .LBB0_4 v_mbcnt_lo_u32_b32 v0, exec_lo, 0 s_mov_b32 s0, 0 s_mov_b32 s1, exec_lo s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v0 s_xor_b32 s1, exec_lo, s1 s_cbranch_execz .LBB0_8 v_mov_b32_e32 v3, 0 global_load_b32 v1, v3, s[2:3] .LBB0_7: s_waitcnt vmcnt(0) v_add_f32_e32 v0, v1, v2 global_atomic_cmpswap_b32 v0, v3, v[0:1], s[2:3] glc s_waitcnt vmcnt(0) v_cmp_eq_u32_e32 vcc_lo, v0, v1 v_mov_b32_e32 v1, v0 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB0_7 .LBB0_8: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z5t_sumPfS_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z5t_sumPfS_i, .Lfunc_end0-_Z5t_sumPfS_i .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z5t_sumPfS_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z5t_sumPfS_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> __global__ void t_sum(float *a, float *out, int n_elements) { const int i = blockDim.x * blockIdx.x + threadIdx.x; if (i == 0) out[0] = 0; __syncthreads(); if (i < n_elements) atomicAdd(out, a[i]); }
.text .file "t_sum.hip" .globl _Z20__device_stub__t_sumPfS_i # -- Begin function _Z20__device_stub__t_sumPfS_i .p2align 4, 0x90 .type _Z20__device_stub__t_sumPfS_i,@function _Z20__device_stub__t_sumPfS_i: # @_Z20__device_stub__t_sumPfS_i .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z5t_sumPfS_i, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z20__device_stub__t_sumPfS_i, .Lfunc_end0-_Z20__device_stub__t_sumPfS_i .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z5t_sumPfS_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z5t_sumPfS_i,@object # @_Z5t_sumPfS_i .section .rodata,"a",@progbits .globl _Z5t_sumPfS_i .p2align 3, 0x0 _Z5t_sumPfS_i: .quad _Z20__device_stub__t_sumPfS_i .size _Z5t_sumPfS_i, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z5t_sumPfS_i" .size .L__unnamed_1, 14 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z20__device_stub__t_sumPfS_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z5t_sumPfS_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z5t_sumPfS_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */ /* 0x000e220000002500 */ /*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */ /* 0x000fe200078e00ff */ /*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe40000000a00 */ /*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */ /* 0x001fe200078e0203 */ /*0060*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */ /* 0x000fc80000000f00 */ /*0070*/ ISETP.NE.AND P0, PT, R4.reuse, RZ, PT ; /* 0x000000ff0400720c */ /* 0x040fe40003f05270 */ /*0080*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */ /* 0x000fd60003f26270 */ /*0090*/ @!P0 STG.E [R2.64], RZ ; /* 0x000000ff02008986 */ /* 0x0001e8000c101904 */ /*00a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*00b0*/ @P1 EXIT ; /* 0x000000000000194d */ /* 0x000fea0003800000 */ /*00c0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */ /* 0x001fd400000001ff */ /*00d0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */ /* 0x000fcc00078e0205 */ /*00e0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */ /* 0x000ea8000c1e1900 */ /*00f0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */ /* 0x004fe2000c10e784 */ /*0100*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0110*/ BRA 0x110; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0120*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0130*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z5t_sumPfS_i .globl _Z5t_sumPfS_i .p2align 8 .type _Z5t_sumPfS_i,@function _Z5t_sumPfS_i: s_clause 0x1 s_load_b32 s4, s[0:1], 0x24 s_load_b64 s[2:3], s[0:1], 0x8 s_waitcnt lgkmcnt(0) s_and_b32 s4, s4, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1] s_mov_b32 s4, exec_lo v_cmpx_eq_u32_e32 0, v1 s_cbranch_execz .LBB0_2 v_mov_b32_e32 v0, 0 global_store_b32 v0, v0, s[2:3] .LBB0_2: s_or_b32 exec_lo, exec_lo, s4 s_load_b32 s4, s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv v_cmp_gt_i32_e32 vcc_lo, s4, v1 s_and_saveexec_b32 s4, vcc_lo s_cbranch_execz .LBB0_8 s_load_b64 s[0:1], s[0:1], 0x0 v_ashrrev_i32_e32 v2, 31, v1 s_mov_b32 s4, exec_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_lshlrev_b64 v[0:1], 2, v[1:2] v_bfrev_b32_e32 v2, 1 s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_3) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_load_b32 v0, v[0:1], off .LBB0_4: s_ctz_i32_b32 s0, s4 s_waitcnt vmcnt(0) v_readlane_b32 s1, v0, s0 s_lshl_b32 s0, 1, s0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_not1_b32 s4, s4, s0 s_cmp_lg_u32 s4, 0 s_delay_alu instid0(VALU_DEP_1) v_add_f32_e32 v2, s1, v2 s_cbranch_scc1 .LBB0_4 v_mbcnt_lo_u32_b32 v0, exec_lo, 0 s_mov_b32 s0, 0 s_mov_b32 s1, exec_lo s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v0 s_xor_b32 s1, exec_lo, s1 s_cbranch_execz .LBB0_8 v_mov_b32_e32 v3, 0 global_load_b32 v1, v3, s[2:3] .LBB0_7: s_waitcnt vmcnt(0) v_add_f32_e32 v0, v1, v2 global_atomic_cmpswap_b32 v0, v3, v[0:1], s[2:3] glc s_waitcnt vmcnt(0) v_cmp_eq_u32_e32 vcc_lo, v0, v1 v_mov_b32_e32 v1, v0 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB0_7 .LBB0_8: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z5t_sumPfS_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z5t_sumPfS_i, .Lfunc_end0-_Z5t_sumPfS_i .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z5t_sumPfS_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z5t_sumPfS_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_00010d30_00000000-6_t_sum.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z27__device_stub__Z5t_sumPfS_iPfS_i .type _Z27__device_stub__Z5t_sumPfS_iPfS_i, @function _Z27__device_stub__Z5t_sumPfS_iPfS_i: .LFB2051: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 120(%rsp), %rax subq %fs:40, %rax jne .L8 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z5t_sumPfS_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z27__device_stub__Z5t_sumPfS_iPfS_i, .-_Z27__device_stub__Z5t_sumPfS_iPfS_i .globl _Z5t_sumPfS_i .type _Z5t_sumPfS_i, @function _Z5t_sumPfS_i: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z27__device_stub__Z5t_sumPfS_iPfS_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z5t_sumPfS_i, .-_Z5t_sumPfS_i .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z5t_sumPfS_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z5t_sumPfS_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "t_sum.hip" .globl _Z20__device_stub__t_sumPfS_i # -- Begin function _Z20__device_stub__t_sumPfS_i .p2align 4, 0x90 .type _Z20__device_stub__t_sumPfS_i,@function _Z20__device_stub__t_sumPfS_i: # @_Z20__device_stub__t_sumPfS_i .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z5t_sumPfS_i, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z20__device_stub__t_sumPfS_i, .Lfunc_end0-_Z20__device_stub__t_sumPfS_i .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z5t_sumPfS_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z5t_sumPfS_i,@object # @_Z5t_sumPfS_i .section .rodata,"a",@progbits .globl _Z5t_sumPfS_i .p2align 3, 0x0 _Z5t_sumPfS_i: .quad _Z20__device_stub__t_sumPfS_i .size _Z5t_sumPfS_i, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z5t_sumPfS_i" .size .L__unnamed_1, 14 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z20__device_stub__t_sumPfS_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z5t_sumPfS_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
/* * ABCTE.cpp * * Created on: 01 февр. 2016 г. * Author: aleksandr */ #include "ABCTE.h" #include <iostream> ABCTE::ABCTE(GridTE* _grid) : EyLeft((_grid->sizeY-1)*6, 0), EyRight((_grid->sizeY-1)*6, 0), ExTop((_grid->sizeX-1)*6, 0), ExBottom((_grid->sizeX-1)*6, 0), coeff0(0), coeff1(0), coeff2(0), grid(_grid), coeffDevice(3, 0) { float temp1 = grid->S; float temp2 = 1.0 / temp1 + 2.0 + temp1; coeff0 = -(1.0 / temp1 - 2.0 + temp1) / temp2; coeff1 = -2.0 * (temp1 - 1.0 / temp1) / temp2; coeff2 = 4.0 * (temp1 + 1.0 / temp1) / temp2; int sizeX = grid->sizeX; int sizeY = grid->sizeY; std::vector<float> coeffHost(3, 0); coeffHost[0] = coeff0; coeffHost[1] = coeff1; coeffHost[2] = coeff2; coeffDevice = coeffHost; leftUpdater.setParams(grid->Ey.getDevicePtr(), EyLeft.getDevicePtr(), coeffDevice.data(), sizeX, sizeY); rightUpdater.setParams(grid->Ey.getDevicePtr(), EyRight.getDevicePtr(), coeffDevice.data(), sizeX, sizeY); topUpdater.setParams(grid->Ex.getDevicePtr(), ExTop.getDevicePtr(), coeffDevice.data(), sizeX, sizeY); bottomUpdater.setParams(grid->Ex.getDevicePtr(), ExBottom.getDevicePtr(), coeffDevice.data(), sizeX, sizeY); std::cout << "Absorption boundary conditions initialized \n"; }
code for sm_80 Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIfEEfEEEEvT0_T1_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */ /* 0x000e220000002500 */ /*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fc60000000a00 */ /*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */ /* 0x000e620000002100 */ /*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */ /* 0x001fca00078e00ff */ /*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */ /* 0x040fe40007f3e1ff */ /*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */ /* 0x002fe40007f5e0ff */ /*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */ /* 0x000fe40003f04070 */ /*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */ /* 0x000fe20000ffe5ff */ /*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */ /* 0x000fe200010e0603 */ /*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */ /* 0x000fe400078210ff */ /*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */ /* 0x000fc40003f04100 */ /*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */ /* 0x000fd600008f1403 */ /*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */ /* 0x000fea0003800000 */ /*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */ /* 0x000fe40003f04070 */ /*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */ /* 0x000fe40000011404 */ /*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */ /* 0x000fe40007ffe0ff */ /*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */ /* 0x000fda0003f04100 */ /*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */ /* 0x000fca00078e00ff */ /*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */ /* 0x0001e2000c101904 */ /*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */ /* 0x000fc80003f04070 */ /*0150*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */ /* 0x000fda0003f04100 */ /*0160*/ @!P0 EXIT ; /* 0x000000000000894d */ /* 0x000fea0003800000 */ /*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */ /* 0x001fca00078e00ff */ /*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */ /* 0x000fe2000c101904 */ /*0190*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */ /* 0x000fca00078e00ff */ /*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */ /* 0x000fe8000c101904 */ /*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */ /* 0x000fe2000c101904 */ /*01d0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0200*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0210*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0220*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0230*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0240*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0250*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0260*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0270*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ .......... Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0020*/ BRA 0x20; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0030*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0040*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0050*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0060*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0070*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0080*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0090*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
/* * ABCTE.cpp * * Created on: 01 февр. 2016 г. * Author: aleksandr */ #include "ABCTE.h" #include <iostream> ABCTE::ABCTE(GridTE* _grid) : EyLeft((_grid->sizeY-1)*6, 0), EyRight((_grid->sizeY-1)*6, 0), ExTop((_grid->sizeX-1)*6, 0), ExBottom((_grid->sizeX-1)*6, 0), coeff0(0), coeff1(0), coeff2(0), grid(_grid), coeffDevice(3, 0) { float temp1 = grid->S; float temp2 = 1.0 / temp1 + 2.0 + temp1; coeff0 = -(1.0 / temp1 - 2.0 + temp1) / temp2; coeff1 = -2.0 * (temp1 - 1.0 / temp1) / temp2; coeff2 = 4.0 * (temp1 + 1.0 / temp1) / temp2; int sizeX = grid->sizeX; int sizeY = grid->sizeY; std::vector<float> coeffHost(3, 0); coeffHost[0] = coeff0; coeffHost[1] = coeff1; coeffHost[2] = coeff2; coeffDevice = coeffHost; leftUpdater.setParams(grid->Ey.getDevicePtr(), EyLeft.getDevicePtr(), coeffDevice.data(), sizeX, sizeY); rightUpdater.setParams(grid->Ey.getDevicePtr(), EyRight.getDevicePtr(), coeffDevice.data(), sizeX, sizeY); topUpdater.setParams(grid->Ex.getDevicePtr(), ExTop.getDevicePtr(), coeffDevice.data(), sizeX, sizeY); bottomUpdater.setParams(grid->Ex.getDevicePtr(), ExBottom.getDevicePtr(), coeffDevice.data(), sizeX, sizeY); std::cout << "Absorption boundary conditions initialized \n"; }
/* * ABCTE.cpp * * Created on: 01 февр. 2016 г. * Author: aleksandr */ #include <hip/hip_runtime.h> #include "ABCTE.h" #include <iostream> ABCTE::ABCTE(GridTE* _grid) : EyLeft((_grid->sizeY-1)*6, 0), EyRight((_grid->sizeY-1)*6, 0), ExTop((_grid->sizeX-1)*6, 0), ExBottom((_grid->sizeX-1)*6, 0), coeff0(0), coeff1(0), coeff2(0), grid(_grid), coeffDevice(3, 0) { float temp1 = grid->S; float temp2 = 1.0 / temp1 + 2.0 + temp1; coeff0 = -(1.0 / temp1 - 2.0 + temp1) / temp2; coeff1 = -2.0 * (temp1 - 1.0 / temp1) / temp2; coeff2 = 4.0 * (temp1 + 1.0 / temp1) / temp2; int sizeX = grid->sizeX; int sizeY = grid->sizeY; std::vector<float> coeffHost(3, 0); coeffHost[0] = coeff0; coeffHost[1] = coeff1; coeffHost[2] = coeff2; coeffDevice = coeffHost; leftUpdater.setParams(grid->Ey.getDevicePtr(), EyLeft.getDevicePtr(), coeffDevice.data(), sizeX, sizeY); rightUpdater.setParams(grid->Ey.getDevicePtr(), EyRight.getDevicePtr(), coeffDevice.data(), sizeX, sizeY); topUpdater.setParams(grid->Ex.getDevicePtr(), ExTop.getDevicePtr(), coeffDevice.data(), sizeX, sizeY); bottomUpdater.setParams(grid->Ex.getDevicePtr(), ExBottom.getDevicePtr(), coeffDevice.data(), sizeX, sizeY); std::cout << "Absorption boundary conditions initialized \n"; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
/* * ABCTE.cpp * * Created on: 01 февр. 2016 г. * Author: aleksandr */ #include <hip/hip_runtime.h> #include "ABCTE.h" #include <iostream> ABCTE::ABCTE(GridTE* _grid) : EyLeft((_grid->sizeY-1)*6, 0), EyRight((_grid->sizeY-1)*6, 0), ExTop((_grid->sizeX-1)*6, 0), ExBottom((_grid->sizeX-1)*6, 0), coeff0(0), coeff1(0), coeff2(0), grid(_grid), coeffDevice(3, 0) { float temp1 = grid->S; float temp2 = 1.0 / temp1 + 2.0 + temp1; coeff0 = -(1.0 / temp1 - 2.0 + temp1) / temp2; coeff1 = -2.0 * (temp1 - 1.0 / temp1) / temp2; coeff2 = 4.0 * (temp1 + 1.0 / temp1) / temp2; int sizeX = grid->sizeX; int sizeY = grid->sizeY; std::vector<float> coeffHost(3, 0); coeffHost[0] = coeff0; coeffHost[1] = coeff1; coeffHost[2] = coeff2; coeffDevice = coeffHost; leftUpdater.setParams(grid->Ey.getDevicePtr(), EyLeft.getDevicePtr(), coeffDevice.data(), sizeX, sizeY); rightUpdater.setParams(grid->Ey.getDevicePtr(), EyRight.getDevicePtr(), coeffDevice.data(), sizeX, sizeY); topUpdater.setParams(grid->Ex.getDevicePtr(), ExTop.getDevicePtr(), coeffDevice.data(), sizeX, sizeY); bottomUpdater.setParams(grid->Ex.getDevicePtr(), ExBottom.getDevicePtr(), coeffDevice.data(), sizeX, sizeY); std::cout << "Absorption boundary conditions initialized \n"; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat .protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_ .globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_ .p2align 8 .type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,@function _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_: s_load_b128 s[4:7], s[0:1], 0x10 s_lshl_b32 s2, s15, 8 s_waitcnt lgkmcnt(0) s_add_u32 s2, s2, s6 s_addc_u32 s3, 0, s7 s_sub_u32 s4, s4, s2 s_subb_u32 s5, s5, s3 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_u64_e64 s5, 0x100, s[4:5] s_and_b32 s5, s5, exec_lo s_cselect_b32 s4, s4, 0x100 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_cmp_gt_u32_e32 vcc_lo, s4, v0 s_cmpk_eq_i32 s4, 0x100 s_cselect_b32 s4, -1, 0 s_or_b32 s4, s4, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s5, s4 s_cbranch_execz .LBB0_2 s_clause 0x1 s_load_b64 s[4:5], s[0:1], 0x0 s_load_b32 s6, s[0:1], 0x8 v_lshlrev_b32_e32 v0, 2, v0 s_lshl_b64 s[0:1], s[2:3], 2 s_waitcnt lgkmcnt(0) s_add_u32 s0, s4, s0 s_addc_u32 s1, s5, s1 v_add_co_u32 v0, s0, s0, v0 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v1, null, s1, 0, s0 v_mov_b32_e32 v2, s6 flat_store_b32 v[0:1], v2 .LBB0_2: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 32 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 3 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat .Lfunc_end0: .size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 16 .value_kind: by_value - .offset: 16 .size: 8 .value_kind: by_value - .offset: 24 .size: 8 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 32 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 256 .name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 3 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIfEEfEEEEvT0_T1_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */ /* 0x000e220000002500 */ /*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fc60000000a00 */ /*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */ /* 0x000e620000002100 */ /*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */ /* 0x001fca00078e00ff */ /*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */ /* 0x040fe40007f3e1ff */ /*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */ /* 0x002fe40007f5e0ff */ /*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */ /* 0x000fe40003f04070 */ /*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */ /* 0x000fe20000ffe5ff */ /*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */ /* 0x000fe200010e0603 */ /*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */ /* 0x000fe400078210ff */ /*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */ /* 0x000fc40003f04100 */ /*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */ /* 0x000fd600008f1403 */ /*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */ /* 0x000fea0003800000 */ /*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */ /* 0x000fe40003f04070 */ /*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */ /* 0x000fe40000011404 */ /*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */ /* 0x000fe40007ffe0ff */ /*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */ /* 0x000fda0003f04100 */ /*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */ /* 0x000fca00078e00ff */ /*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */ /* 0x0001e2000c101904 */ /*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */ /* 0x000fc80003f04070 */ /*0150*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */ /* 0x000fda0003f04100 */ /*0160*/ @!P0 EXIT ; /* 0x000000000000894d */ /* 0x000fea0003800000 */ /*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */ /* 0x001fca00078e00ff */ /*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */ /* 0x000fe2000c101904 */ /*0190*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */ /* 0x000fca00078e00ff */ /*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */ /* 0x000fe8000c101904 */ /*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */ /* 0x000fe2000c101904 */ /*01d0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0200*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0210*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0220*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0230*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0240*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0250*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0260*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0270*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ .......... Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0020*/ BRA 0x20; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0030*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0040*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0050*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0060*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0070*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0080*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0090*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat .protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_ .globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_ .p2align 8 .type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,@function _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_: s_load_b128 s[4:7], s[0:1], 0x10 s_lshl_b32 s2, s15, 8 s_waitcnt lgkmcnt(0) s_add_u32 s2, s2, s6 s_addc_u32 s3, 0, s7 s_sub_u32 s4, s4, s2 s_subb_u32 s5, s5, s3 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_u64_e64 s5, 0x100, s[4:5] s_and_b32 s5, s5, exec_lo s_cselect_b32 s4, s4, 0x100 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_cmp_gt_u32_e32 vcc_lo, s4, v0 s_cmpk_eq_i32 s4, 0x100 s_cselect_b32 s4, -1, 0 s_or_b32 s4, s4, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s5, s4 s_cbranch_execz .LBB0_2 s_clause 0x1 s_load_b64 s[4:5], s[0:1], 0x0 s_load_b32 s6, s[0:1], 0x8 v_lshlrev_b32_e32 v0, 2, v0 s_lshl_b64 s[0:1], s[2:3], 2 s_waitcnt lgkmcnt(0) s_add_u32 s0, s4, s0 s_addc_u32 s1, s5, s1 v_add_co_u32 v0, s0, s0, v0 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v1, null, s1, 0, s0 v_mov_b32_e32 v2, s6 flat_store_b32 v[0:1], v2 .LBB0_2: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 32 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 3 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat .Lfunc_end0: .size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 16 .value_kind: by_value - .offset: 16 .size: 8 .value_kind: by_value - .offset: 24 .size: 8 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 32 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 256 .name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 3 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include <stdio.h> #include <stdlib.h> #include <sys/time.h> #include <time.h> #define ANCHOMATRIZ 64 // Definición del kernel __global__ void matrixMul(float *a, float *b, float *c) { int row = blockIdx.y * blockDim.y + threadIdx.y; int col = blockIdx.x * blockDim.x + threadIdx.x; if (row < ANCHOMATRIZ && col < ANCHOMATRIZ) { float sum = 0.0f; for (int i = 0; i < ANCHOMATRIZ; i++) { sum += a[row * ANCHOMATRIZ + i] * b[i * ANCHOMATRIZ + col]; } c[row * ANCHOMATRIZ + col] = sum; } } void matrixMul_CPU(float *a, float *b, float *c) { float acum; for (int i = 0 ; i<ANCHOMATRIZ ; i++) { for (int j = 0 ; j<ANCHOMATRIZ ; j++) { acum = 0; for (int k = 0 ; k<ANCHOMATRIZ ; k++) { acum = acum + a[i*ANCHOMATRIZ + k]*b[k*ANCHOMATRIZ + j]; } c[i*ANCHOMATRIZ+j] = acum; } } } long long milisegundos() // Devuelve el tiempo en milisegundos desde la época Unix (01/01/1970) { struct timeval t; gettimeofday(&t, NULL); return t.tv_sec*1000 + t.tv_usec/1000; } int main(void) { int numElementos = ANCHOMATRIZ*ANCHOMATRIZ; size_t tamano = numElementos * sizeof(int); // Reservamos memoria host (memoria principal) float *h_a = (float *)malloc(tamano); float *h_b = (float *)malloc(tamano); float *h_c = (float *)malloc(tamano); long long ti,tf; // Inicializar con números arbitrarios for (int i = 0; i < ANCHOMATRIZ; ++i) { for (int j = 0; j < ANCHOMATRIZ; j++) { h_a[i*ANCHOMATRIZ+j] = rand()/(float)RAND_MAX; h_b[i*ANCHOMATRIZ+j] = rand()/(float)RAND_MAX; } } ti=milisegundos(); //tiempo inicial // Ejecutamos la multiplicación de matrices matrixMul_CPU(h_a, h_b, h_c); tf=milisegundos(); //tiempo final printf("Tiempo invertido en multiplicar CPU: %f\n", (tf-ti)); printf("------- CPU --------\n"); for (int i = 0; i < 10; ++i) { printf("Componente [%d] = %f\n", i, h_c[i]); } //Crear variables para la parte device (d_a, d_b, d_c) float *d_a, *d_b, *d_c; // Reservar memoria en la parte device cudaMalloc(&d_a, tamano); cudaMalloc(&d_b, tamano); cudaMalloc(&d_c, tamano); //Pasar datos de la memoria host a memoria device cudaMemcpy(d_a, h_a, tamano, cudaMemcpyHostToDevice); cudaMemcpy(d_b, h_b, tamano, cudaMemcpyHostToDevice); cudaMemcpy(d_c, h_c, tamano, cudaMemcpyHostToDevice); // Cada bloque tendrá 256 hilos y habrá 4096 bloques dim3 dimBlock(16,16); dim3 dimGrid(64,64); ti=milisegundos(); //tiempo inicial // Lanzar Kernel matrixMul<<<dimGrid, dimBlock>>>(d_a, d_b, d_c); //Pasar datos de la memoria device a memoria host cudaMemcpy(h_c, d_c, tamano, cudaMemcpyDeviceToHost); tf=milisegundos(); //tiempo final printf("Tiempo invertido en multiplicar GPU: %f\n", (tf-ti)); // Verificamos los primeros valores printf("------- GPU --------\n"); for (int i = 0; i < 10; ++i) { printf("Componente [%d] = %f\n", i, h_c[i]); } // Liberamos memoria device cudaFree(d_a); cudaFree(d_b); cudaFree(d_c); // Liberamos memoria host free(h_a); free(h_b); free(h_c); return 0; }
code for sm_80 Function : _Z9matrixMulPfS_S_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */ /* 0x000e280000002500 */ /*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */ /* 0x000e280000002100 */ /*0030*/ S2R R13, SR_CTAID.Y ; /* 0x00000000000d7919 */ /* 0x000e680000002600 */ /*0040*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */ /* 0x000e620000002200 */ /*0050*/ IMAD R11, R11, c[0x0][0x0], R2 ; /* 0x000000000b0b7a24 */ /* 0x001fca00078e0202 */ /*0060*/ ISETP.GT.AND P0, PT, R11, 0x3f, PT ; /* 0x0000003f0b00780c */ /* 0x000fe20003f04270 */ /*0070*/ IMAD R13, R13, c[0x0][0x4], R0 ; /* 0x000001000d0d7a24 */ /* 0x002fca00078e0200 */ /*0080*/ ISETP.GT.OR P0, PT, R13, 0x3f, P0 ; /* 0x0000003f0d00780c */ /* 0x000fda0000704670 */ /*0090*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*00a0*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */ /* 0x000fe200000001ff */ /*00b0*/ SHF.L.U32 R13, R13, 0x6, RZ ; /* 0x000000060d0d7819 */ /* 0x000fe200000006ff */ /*00c0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */ /* 0x000fe40000000a00 */ /*00d0*/ ULDC.64 UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */ /* 0x000fe20000000a00 */ /*00e0*/ IADD3 R27, R13, 0x1, RZ ; /* 0x000000010d1b7810 */ /* 0x000fe20007ffe0ff */ /*00f0*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */ /* 0x000fc80000000a00 */ /*0100*/ IMAD.WIDE R2, R13, R0, c[0x0][0x160] ; /* 0x000058000d027625 */ /* 0x000fc800078e0200 */ /*0110*/ IMAD.WIDE R28, R11, R0.reuse, c[0x0][0x168] ; /* 0x00005a000b1c7625 */ /* 0x080fe200078e0200 */ /*0120*/ LDG.E R15, [R2.64] ; /* 0x00000008020f7981 */ /* 0x0000a6000c1e1900 */ /*0130*/ IMAD.WIDE R8, R27, R0, c[0x0][0x160] ; /* 0x000058001b087625 */ /* 0x000fe200078e0200 */ /*0140*/ LDG.E R10, [R28.64] ; /* 0x000000081c0a7981 */ /* 0x000ea8000c1e1900 */ /*0150*/ LDG.E R25, [R28.64+0x100] ; /* 0x000100081c197981 */ /* 0x000ee8000c1e1900 */ /*0160*/ LDG.E R20, [R8.64] ; /* 0x0000000808147981 */ /* 0x000ee8000c1e1900 */ /*0170*/ LDG.E R17, [R28.64+0x200] ; /* 0x000200081c117981 */ /* 0x000f28000c1e1900 */ /*0180*/ LDG.E R12, [R8.64+0x4] ; /* 0x00000408080c7981 */ /* 0x000f28000c1e1900 */ /*0190*/ LDG.E R14, [R28.64+0x300] ; /* 0x000300081c0e7981 */ /* 0x000f68000c1e1900 */ /*01a0*/ LDG.E R19, [R8.64+0x8] ; /* 0x0000080808137981 */ /* 0x000f68000c1e1900 */ /*01b0*/ LDG.E R16, [R28.64+0x400] ; /* 0x000400081c107981 */ /* 0x000f68000c1e1900 */ /*01c0*/ LDG.E R21, [R8.64+0xc] ; /* 0x00000c0808157981 */ /* 0x000f68000c1e1900 */ /*01d0*/ LDG.E R2, [R28.64+0x500] ; /* 0x000500081c027981 */ /* 0x001f68000c1e1900 */ /*01e0*/ LDG.E R3, [R8.64+0x10] ; /* 0x0000100808037981 */ /* 0x000f68000c1e1900 */ /*01f0*/ LDG.E R4, [R28.64+0x600] ; /* 0x000600081c047981 */ /* 0x000f68000c1e1900 */ /*0200*/ LDG.E R5, [R8.64+0x14] ; /* 0x0000140808057981 */ /* 0x000f68000c1e1900 */ /*0210*/ LDG.E R6, [R28.64+0x700] ; /* 0x000700081c067981 */ /* 0x000f68000c1e1900 */ /*0220*/ LDG.E R7, [R8.64+0x18] ; /* 0x0000180808077981 */ /* 0x000f68000c1e1900 */ /*0230*/ LDG.E R18, [R28.64+0x800] ; /* 0x000800081c127981 */ /* 0x000f68000c1e1900 */ /*0240*/ LDG.E R23, [R8.64+0x1c] ; /* 0x00001c0808177981 */ /* 0x000f62000c1e1900 */ /*0250*/ UIADD3 UR4, UP0, UR4, 0x1000, URZ ; /* 0x0000100004047890 */ /* 0x000fc4000ff1e03f */ /*0260*/ UIADD3 UR6, UP1, UR6, 0x40, URZ ; /* 0x0000004006067890 */ /* 0x000fe2000ff3e03f */ /*0270*/ LDG.E R22, [R28.64+0xe00] ; /* 0x000e00081c167981 */ /* 0x000168000c1e1900 */ /*0280*/ LDG.E R24, [R28.64+0xf00] ; /* 0x000f00081c187981 */ /* 0x000168000c1e1900 */ /*0290*/ LDG.E R26, [R8.64+0x38] ; /* 0x00003808081a7981 */ /* 0x000362000c1e1900 */ /*02a0*/ FFMA R10, R10, R15, RZ ; /* 0x0000000f0a0a7223 */ /* 0x004fc600000000ff */ /*02b0*/ LDG.E R15, [R8.64+0x20] ; /* 0x00002008080f7981 */ /* 0x0002a2000c1e1900 */ /*02c0*/ FFMA R20, R25, R20, R10 ; /* 0x0000001419147223 */ /* 0x008fc6000000000a */ /*02d0*/ LDG.E R10, [R28.64+0x900] ; /* 0x000900081c0a7981 */ /* 0x0000a2000c1e1900 */ /*02e0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */ /* 0x000fe400087fe43f */ /*02f0*/ UIADD3.X UR7, URZ, UR7, URZ, UP1, !UPT ; /* 0x000000073f077290 */ /* 0x000fe20008ffe43f */ /*0300*/ LDG.E R25, [R8.64+0x34] ; /* 0x0000340808197981 */ /* 0x0002e2000c1e1900 */ /*0310*/ FFMA R20, R17, R12, R20 ; /* 0x0000000c11147223 */ /* 0x010fc60000000014 */ /*0320*/ LDG.E R12, [R28.64+0xa00] ; /* 0x000a00081c0c7981 */ /* 0x000128000c1e1900 */ /*0330*/ LDG.E R17, [R8.64+0x24] ; /* 0x0000240808117981 */ /* 0x000322000c1e1900 */ /*0340*/ FFMA R20, R14, R19, R20 ; /* 0x000000130e147223 */ /* 0x020fc60000000014 */ /*0350*/ LDG.E R14, [R28.64+0xb00] ; /* 0x000b00081c0e7981 */ /* 0x000168000c1e1900 */ /*0360*/ LDG.E R19, [R8.64+0x28] ; /* 0x0000280808137981 */ /* 0x000362000c1e1900 */ /*0370*/ FFMA R20, R16, R21, R20 ; /* 0x0000001510147223 */ /* 0x000fc60000000014 */ /*0380*/ LDG.E R16, [R28.64+0xc00] ; /* 0x000c00081c107981 */ /* 0x0000e8000c1e1900 */ /*0390*/ LDG.E R21, [R8.64+0x2c] ; /* 0x00002c0808157981 */ /* 0x0002e2000c1e1900 */ /*03a0*/ FFMA R2, R2, R3, R20 ; /* 0x0000000302027223 */ /* 0x000fc60000000014 */ /*03b0*/ LDG.E R20, [R28.64+0xd00] ; /* 0x000d00081c147981 */ /* 0x0000e2000c1e1900 */ /*03c0*/ FFMA R2, R4, R5, R2 ; /* 0x0000000504027223 */ /* 0x000fc80000000002 */ /*03d0*/ FFMA R2, R6, R7, R2 ; /* 0x0000000706027223 */ /* 0x000fe20000000002 */ /*03e0*/ MOV R4, UR4 ; /* 0x0000000400047c02 */ /* 0x000fe40008000f00 */ /*03f0*/ MOV R3, UR7 ; /* 0x0000000700037c02 */ /* 0x000fe20008000f00 */ /*0400*/ FFMA R18, R18, R23, R2 ; /* 0x0000001712127223 */ /* 0x000fe40000000002 */ /*0410*/ LDG.E R23, [R8.64+0x30] ; /* 0x0000300808177981 */ /* 0x0002e2000c1e1900 */ /*0420*/ MOV R2, UR6 ; /* 0x0000000600027c02 */ /* 0x000fe40008000f00 */ /*0430*/ MOV R5, UR5 ; /* 0x0000000500057c02 */ /* 0x000fc60008000f00 */ /*0440*/ IMAD.WIDE R6, R13, 0x4, R2 ; /* 0x000000040d067825 */ /* 0x000fc800078e0202 */ /*0450*/ IMAD.WIDE R4, R11, 0x4, R4 ; /* 0x000000040b047825 */ /* 0x000fc800078e0204 */ /*0460*/ IMAD.WIDE R2, R27, 0x4, R2 ; /* 0x000000041b027825 */ /* 0x000fe200078e0202 */ /*0470*/ LDG.E R9, [R4.64+0x300] ; /* 0x0003000804097981 */ /* 0x002ee8000c1e1900 */ /*0480*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040802087981 */ /* 0x000ee8000c1e1900 */ /*0490*/ LDG.E R27, [R4.64+0xc00] ; /* 0x000c0008041b7981 */ /* 0x000ee8000c1e1900 */ /*04a0*/ LDG.E R29, [R2.64+0xb0] ; /* 0x0000b008021d7981 */ /* 0x0010e2000c1e1900 */ /*04b0*/ FFMA R18, R10, R15, R18 ; /* 0x0000000f0a127223 */ /* 0x004fc60000000012 */ /*04c0*/ LDG.E R15, [R4.64] ; /* 0x00000008040f7981 */ /* 0x000ea8000c1e1900 */ /*04d0*/ LDG.E R10, [R6.64] ; /* 0x00000008060a7981 */ /* 0x000ea2000c1e1900 */ /*04e0*/ FFMA R18, R12, R17, R18 ; /* 0x000000110c127223 */ /* 0x010fc60000000012 */ /*04f0*/ LDG.E R12, [R4.64+0x100] ; /* 0x00010008040c7981 */ /* 0x000f28000c1e1900 */ /*0500*/ LDG.E R17, [R2.64] ; /* 0x0000000802117981 */ /* 0x000f22000c1e1900 */ /*0510*/ FFMA R18, R14, R19, R18 ; /* 0x000000130e127223 */ /* 0x020fc60000000012 */ /*0520*/ LDG.E R19, [R4.64+0x200] ; /* 0x0002000804137981 */ /* 0x000f68000c1e1900 */ /*0530*/ LDG.E R14, [R2.64+0x8] ; /* 0x00000808020e7981 */ /* 0x000f62000c1e1900 */ /*0540*/ FFMA R18, R16, R21, R18 ; /* 0x0000001510127223 */ /* 0x008fc60000000012 */ /*0550*/ LDG.E R16, [R4.64+0x400] ; /* 0x0004000804107981 */ /* 0x000ee8000c1e1900 */ /*0560*/ LDG.E R21, [R2.64+0xc] ; /* 0x00000c0802157981 */ /* 0x000ee2000c1e1900 */ /*0570*/ FFMA R18, R20, R23, R18 ; /* 0x0000001714127223 */ /* 0x000fc60000000012 */ /*0580*/ LDG.E R23, [R2.64+0x10] ; /* 0x0000100802177981 */ /* 0x000ee2000c1e1900 */ /*0590*/ FFMA R25, R22, R25, R18 ; /* 0x0000001916197223 */ /* 0x000fc60000000012 */ /*05a0*/ LDG.E R18, [R4.64+0x500] ; /* 0x0005000804127981 */ /* 0x000ee2000c1e1900 */ /*05b0*/ FFMA R24, R24, R26, R25 ; /* 0x0000001a18187223 */ /* 0x000fc60000000019 */ /*05c0*/ LDG.E R20, [R4.64+0x600] ; /* 0x0006000804147981 */ /* 0x000ee8000c1e1900 */ /*05d0*/ LDG.E R25, [R2.64+0x14] ; /* 0x0000140802197981 */ /* 0x000ee8000c1e1900 */ /*05e0*/ LDG.E R22, [R2.64+0x28] ; /* 0x0000280802167981 */ /* 0x000ee2000c1e1900 */ /*05f0*/ FFMA R24, R15, R10, R24 ; /* 0x0000000a0f187223 */ /* 0x004fc60000000018 */ /*0600*/ LDG.E R15, [R4.64+0x700] ; /* 0x00070008040f7981 */ /* 0x000ea8000c1e1900 */ /*0610*/ LDG.E R10, [R2.64+0x18] ; /* 0x00001808020a7981 */ /* 0x000ea2000c1e1900 */ /*0620*/ FFMA R24, R12, R17, R24 ; /* 0x000000110c187223 */ /* 0x010fc60000000018 */ /*0630*/ LDG.E R12, [R4.64+0x800] ; /* 0x00080008040c7981 */ /* 0x000f28000c1e1900 */ /*0640*/ LDG.E R17, [R2.64+0x1c] ; /* 0x00001c0802117981 */ /* 0x000f22000c1e1900 */ /*0650*/ FFMA R24, R19, R8, R24 ; /* 0x0000000813187223 */ /* 0x020fc60000000018 */ /*0660*/ LDG.E R19, [R4.64+0x900] ; /* 0x0009000804137981 */ /* 0x000f68000c1e1900 */ /*0670*/ LDG.E R8, [R2.64+0x20] ; /* 0x0000200802087981 */ /* 0x000f62000c1e1900 */ /*0680*/ FFMA R24, R9, R14, R24 ; /* 0x0000000e09187223 */ /* 0x000fc60000000018 */ /*0690*/ LDG.E R14, [R4.64+0xa00] ; /* 0x000a0008040e7981 */ /* 0x000f68000c1e1900 */ /*06a0*/ LDG.E R9, [R2.64+0x24] ; /* 0x0000240802097981 */ /* 0x000f62000c1e1900 */ /*06b0*/ FFMA R24, R16, R21, R24 ; /* 0x0000001510187223 */ /* 0x008fc60000000018 */ /*06c0*/ LDG.E R21, [R4.64+0xb00] ; /* 0x000b000804157981 */ /* 0x000ee8000c1e1900 */ /*06d0*/ LDG.E R16, [R2.64+0x2c] ; /* 0x00002c0802107981 */ /* 0x000ee2000c1e1900 */ /*06e0*/ FFMA R18, R18, R23, R24 ; /* 0x0000001712127223 */ /* 0x000fc60000000018 */ /*06f0*/ LDG.E R23, [R2.64+0x30] ; /* 0x0000300802177981 */ /* 0x000ee2000c1e1900 */ /*0700*/ FFMA R20, R20, R25, R18 ; /* 0x0000001914147223 */ /* 0x000fc60000000012 */ /*0710*/ LDG.E R18, [R4.64+0xd00] ; /* 0x000d000804127981 */ /* 0x000ee8000c1e1900 */ /*0720*/ LDG.E R25, [R2.64+0x48] ; /* 0x0000480802197981 */ /* 0x000ee2000c1e1900 */ /*0730*/ FFMA R20, R15, R10, R20 ; /* 0x0000000a0f147223 */ /* 0x004fc60000000014 */ /*0740*/ LDG.E R15, [R4.64+0xe00] ; /* 0x000e0008040f7981 */ /* 0x000ea8000c1e1900 */ /*0750*/ LDG.E R10, [R2.64+0x34] ; /* 0x00003408020a7981 */ /* 0x000ea2000c1e1900 */ /*0760*/ FFMA R20, R12, R17, R20 ; /* 0x000000110c147223 */ /* 0x010fc60000000014 */ /*0770*/ LDG.E R12, [R4.64+0xf00] ; /* 0x000f0008040c7981 */ /* 0x000f28000c1e1900 */ /*0780*/ LDG.E R17, [R2.64+0x38] ; /* 0x0000380802117981 */ /* 0x000f22000c1e1900 */ /*0790*/ FFMA R20, R19, R8, R20 ; /* 0x0000000813147223 */ /* 0x020fc60000000014 */ /*07a0*/ LDG.E R8, [R6.64+0x40] ; /* 0x0000400806087981 */ /* 0x000368000c1e1900 */ /*07b0*/ LDG.E R19, [R4.64+0x1000] ; /* 0x0010000804137981 */ /* 0x000f62000c1e1900 */ /*07c0*/ FFMA R20, R14, R9, R20 ; /* 0x000000090e147223 */ /* 0x000fc60000000014 */ /*07d0*/ LDG.E R14, [R4.64+0x1100] ; /* 0x00110008040e7981 */ /* 0x000f68000c1e1900 */ /*07e0*/ LDG.E R9, [R2.64+0x40] ; /* 0x0000400802097981 */ /* 0x000f62000c1e1900 */ /*07f0*/ FFMA R22, R21, R22, R20 ; /* 0x0000001615167223 */ /* 0x008fc60000000014 */ /*0800*/ LDG.E R20, [R4.64+0x1200] ; /* 0x0012000804147981 */ /* 0x000ee2000c1e1900 */ /*0810*/ FFMA R24, R27, R16, R22 ; /* 0x000000101b187223 */ /* 0x000fc60000000016 */ /*0820*/ LDG.E R21, [R2.64+0x44] ; /* 0x0000440802157981 */ /* 0x000ee8000c1e1900 */ /*0830*/ LDG.E R16, [R4.64+0x1300] ; /* 0x0013000804107981 */ /* 0x000ee8000c1e1900 */ /*0840*/ LDG.E R22, [R4.64+0x1400] ; /* 0x0014000804167981 */ /* 0x000ee8000c1e1900 */ /*0850*/ LDG.E R27, [R2.64+0x4c] ; /* 0x00004c08021b7981 */ /* 0x000ee8000c1e1900 */ /*0860*/ LDG.E R6, [R6.64+0x80] ; /* 0x0000800806067981 */ /* 0x0022e2000c1e1900 */ /*0870*/ FFMA R18, R18, R23, R24 ; /* 0x0000001712127223 */ /* 0x000fc60000000018 */ /*0880*/ LDG.E R23, [R4.64+0x1a00] ; /* 0x001a000804177981 */ /* 0x000ee8000c1e1900 */ /*0890*/ LDG.E R7, [R2.64+0x90] ; /* 0x0000900802077981 */ /* 0x002ee2000c1e1900 */ /*08a0*/ FFMA R18, R15, R10, R18 ; /* 0x0000000a0f127223 */ /* 0x004fc60000000012 */ /*08b0*/ LDG.E R15, [R4.64+0x1500] ; /* 0x00150008040f7981 */ /* 0x000ea8000c1e1900 */ /*08c0*/ LDG.E R10, [R2.64+0x50] ; /* 0x00005008020a7981 */ /* 0x000ea2000c1e1900 */ /*08d0*/ FFMA R18, R12, R17, R18 ; /* 0x000000110c127223 */ /* 0x010fc60000000012 */ /*08e0*/ LDG.E R12, [R4.64+0x1600] ; /* 0x00160008040c7981 */ /* 0x000f28000c1e1900 */ /*08f0*/ LDG.E R17, [R2.64+0x54] ; /* 0x0000540802117981 */ /* 0x000f22000c1e1900 */ /*0900*/ FFMA R18, R19, R8, R18 ; /* 0x0000000813127223 */ /* 0x020fc60000000012 */ /*0910*/ LDG.E R8, [R4.64+0x1700] ; /* 0x0017000804087981 */ /* 0x000f68000c1e1900 */ /*0920*/ LDG.E R19, [R2.64+0x58] ; /* 0x0000580802137981 */ /* 0x000f62000c1e1900 */ /*0930*/ FFMA R18, R14, R9, R18 ; /* 0x000000090e127223 */ /* 0x000fc60000000012 */ /*0940*/ LDG.E R14, [R4.64+0x1800] ; /* 0x00180008040e7981 */ /* 0x000f68000c1e1900 */ /*0950*/ LDG.E R9, [R2.64+0x5c] ; /* 0x00005c0802097981 */ /* 0x000f62000c1e1900 */ /*0960*/ FFMA R20, R20, R21, R18 ; /* 0x0000001514147223 */ /* 0x008fc60000000012 */ /*0970*/ LDG.E R21, [R4.64+0x1900] ; /* 0x0019000804157981 */ /* 0x000ee8000c1e1900 */ /*0980*/ LDG.E R18, [R2.64+0x60] ; /* 0x0000600802127981 */ /* 0x000ee2000c1e1900 */ /*0990*/ FFMA R20, R16, R25, R20 ; /* 0x0000001910147223 */ /* 0x000fc60000000014 */ /*09a0*/ LDG.E R16, [R2.64+0x64] ; /* 0x0000640802107981 */ /* 0x000ee2000c1e1900 */ /*09b0*/ FFMA R24, R22, R27, R20 ; /* 0x0000001b16187223 */ /* 0x000fc60000000014 */ /*09c0*/ LDG.E R22, [R4.64+0x1b00] ; /* 0x001b000804167981 */ /* 0x000ee8000c1e1900 */ /*09d0*/ LDG.E R27, [R2.64+0x68] ; /* 0x00006808021b7981 */ /* 0x000ee8000c1e1900 */ /*09e0*/ LDG.E R20, [R4.64+0x1c00] ; /* 0x001c000804147981 */ /* 0x000ee8000c1e1900 */ /*09f0*/ LDG.E R25, [R2.64+0x6c] ; /* 0x00006c0802197981 */ /* 0x000ee2000c1e1900 */ /*0a00*/ FFMA R10, R15, R10, R24 ; /* 0x0000000a0f0a7223 */ /* 0x004fc60000000018 */ /*0a10*/ LDG.E R15, [R4.64+0x1d00] ; /* 0x001d0008040f7981 */ /* 0x000ea2000c1e1900 */ /*0a20*/ FFMA R12, R12, R17, R10 ; /* 0x000000110c0c7223 */ /* 0x010fc6000000000a */ /*0a30*/ LDG.E R10, [R2.64+0x70] ; /* 0x00007008020a7981 */ /* 0x000ea8000c1e1900 */ /*0a40*/ LDG.E R17, [R2.64+0x74] ; /* 0x0000740802117981 */ /* 0x000f22000c1e1900 */ /*0a50*/ FFMA R12, R8, R19, R12 ; /* 0x00000013080c7223 */ /* 0x020fc6000000000c */ /*0a60*/ LDG.E R8, [R4.64+0x1e00] ; /* 0x001e000804087981 */ /* 0x000f28000c1e1900 */ /*0a70*/ LDG.E R19, [R4.64+0x2000] ; /* 0x0020000804137981 */ /* 0x000f62000c1e1900 */ /*0a80*/ FFMA R14, R14, R9, R12 ; /* 0x000000090e0e7223 */ /* 0x000fc6000000000c */ /*0a90*/ LDG.E R9, [R4.64+0x1f00] ; /* 0x001f000804097981 */ /* 0x000f68000c1e1900 */ /*0aa0*/ LDG.E R12, [R2.64+0x78] ; /* 0x00007808020c7981 */ /* 0x000f62000c1e1900 */ /*0ab0*/ FFMA R18, R21, R18, R14 ; /* 0x0000001215127223 */ /* 0x008fc6000000000e */ /*0ac0*/ LDG.E R21, [R4.64+0x2100] ; /* 0x0021000804157981 */ /* 0x000ee2000c1e1900 */ /*0ad0*/ FFMA R18, R23, R16, R18 ; /* 0x0000001017127223 */ /* 0x000fc60000000012 */ /*0ae0*/ LDG.E R14, [R2.64+0x80] ; /* 0x00008008020e7981 */ /* 0x000ee8000c1e1900 */ /*0af0*/ LDG.E R23, [R4.64+0x2200] ; /* 0x0022000804177981 */ /* 0x000ee2000c1e1900 */ /*0b00*/ FFMA R22, R22, R27, R18 ; /* 0x0000001b16167223 */ /* 0x000fc60000000012 */ /*0b10*/ LDG.E R16, [R2.64+0x84] ; /* 0x0000840802107981 */ /* 0x000ee8000c1e1900 */ /*0b20*/ LDG.E R27, [R4.64+0x2300] ; /* 0x00230008041b7981 */ /* 0x000ee8000c1e1900 */ /*0b30*/ LDG.E R18, [R2.64+0x88] ; /* 0x0000880802127981 */ /* 0x000ee2000c1e1900 */ /*0b40*/ FFMA R24, R20, R25, R22 ; /* 0x0000001914187223 */ /* 0x000fc60000000016 */ /*0b50*/ LDG.E R25, [R4.64+0x2400] ; /* 0x0024000804197981 */ /* 0x000ee8000c1e1900 */ /*0b60*/ LDG.E R22, [R2.64+0x8c] ; /* 0x00008c0802167981 */ /* 0x000ee8000c1e1900 */ /*0b70*/ LDG.E R20, [R4.64+0x2500] ; /* 0x0025000804147981 */ /* 0x000ee2000c1e1900 */ /*0b80*/ FFMA R10, R15, R10, R24 ; /* 0x0000000a0f0a7223 */ /* 0x004fc60000000018 */ /*0b90*/ LDG.E R15, [R4.64+0x2600] ; /* 0x00260008040f7981 */ /* 0x000ea8000c1e1900 */ /*0ba0*/ LDG.E R24, [R2.64+0xb8] ; /* 0x0000b80802187981 */ /* 0x0000a2000c1e1900 */ /*0bb0*/ FFMA R10, R8, R17, R10 ; /* 0x00000011080a7223 */ /* 0x010fc6000000000a */ /*0bc0*/ LDG.E R8, [R2.64+0x94] ; /* 0x0000940802087981 */ /* 0x0000a8000c1e1900 */ /*0bd0*/ LDG.E R17, [R2.64+0x9c] ; /* 0x00009c0802117981 */ /* 0x000122000c1e1900 */ /*0be0*/ FFMA R12, R9, R12, R10 ; /* 0x0000000c090c7223 */ /* 0x020fc6000000000a */ /*0bf0*/ LDG.E R9, [R4.64+0x2700] ; /* 0x0027000804097981 */ /* 0x000f62000c1e1900 */ /*0c00*/ FFMA R19, R19, R6, R12 ; /* 0x0000000613137223 */ /* 0x000fc6000000000c */ /*0c10*/ LDG.E R10, [R2.64+0x98] ; /* 0x00009808020a7981 */ /* 0x000162000c1e1900 */ /*0c20*/ FFMA R14, R21, R14, R19 ; /* 0x0000000e150e7223 */ /* 0x008fc60000000013 */ /*0c30*/ LDG.E R6, [R4.64+0x2800] ; /* 0x0028000804067981 */ /* 0x000f28000c1e1900 */ /*0c40*/ LDG.E R12, [R4.64+0x2900] ; /* 0x00290008040c7981 */ /* 0x000ee2000c1e1900 */ /*0c50*/ FFMA R16, R23, R16, R14 ; /* 0x0000001017107223 */ /* 0x000fc6000000000e */ /*0c60*/ LDG.E R19, [R2.64+0xa0] ; /* 0x0000a00802137981 */ /* 0x0000e8000c1e1900 */ /*0c70*/ LDG.E R14, [R4.64+0x2a00] ; /* 0x002a0008040e7981 */ /* 0x000ee2000c1e1900 */ /*0c80*/ FFMA R18, R27, R18, R16 ; /* 0x000000121b127223 */ /* 0x000fc60000000010 */ /*0c90*/ LDG.E R21, [R2.64+0xa4] ; /* 0x0000a40802157981 */ /* 0x0000e8000c1e1900 */ /*0ca0*/ LDG.E R16, [R4.64+0x2b00] ; /* 0x002b000804107981 */ /* 0x000ee2000c1e1900 */ /*0cb0*/ FFMA R22, R25, R22, R18 ; /* 0x0000001619167223 */ /* 0x000fc60000000012 */ /*0cc0*/ LDG.E R23, [R2.64+0xa8] ; /* 0x0000a80802177981 */ /* 0x0000e8000c1e1900 */ /*0cd0*/ LDG.E R18, [R4.64+0x2c00] ; /* 0x002c000804127981 */ /* 0x000ee2000c1e1900 */ /*0ce0*/ FFMA R26, R20, R7, R22 ; /* 0x00000007141a7223 */ /* 0x000fc60000000016 */ /*0cf0*/ LDG.E R25, [R2.64+0xac] ; /* 0x0000ac0802197981 */ /* 0x0000e8000c1e1900 */ /*0d00*/ LDG.E R22, [R4.64+0x2d00] ; /* 0x002d000804167981 */ /* 0x000ee8000c1e1900 */ /*0d10*/ LDG.E R20, [R4.64+0x2e00] ; /* 0x002e000804147981 */ /* 0x000ee8000c1e1900 */ /*0d20*/ LDG.E R27, [R2.64+0xb4] ; /* 0x0000b408021b7981 */ /* 0x0000e8000c1e1900 */ /*0d30*/ LDG.E R7, [R4.64+0x2f00] ; /* 0x002f000804077981 */ /* 0x000ee2000c1e1900 */ /*0d40*/ IADD3 R11, R11, R13, RZ ; /* 0x0000000d0b0b7210 */ /* 0x000fca0007ffe0ff */ /*0d50*/ IMAD.WIDE R2, R11, R0, c[0x0][0x170] ; /* 0x00005c000b027625 */ /* 0x001fc800078e0200 */ /*0d60*/ FFMA R8, R15, R8, R26 ; /* 0x000000080f087223 */ /* 0x004fc8000000001a */ /*0d70*/ FFMA R8, R9, R10, R8 ; /* 0x0000000a09087223 */ /* 0x020fc80000000008 */ /*0d80*/ FFMA R6, R6, R17, R8 ; /* 0x0000001106067223 */ /* 0x010fc80000000008 */ /*0d90*/ FFMA R6, R12, R19, R6 ; /* 0x000000130c067223 */ /* 0x008fc80000000006 */ /*0da0*/ FFMA R6, R14, R21, R6 ; /* 0x000000150e067223 */ /* 0x000fc80000000006 */ /*0db0*/ FFMA R6, R16, R23, R6 ; /* 0x0000001710067223 */ /* 0x000fc80000000006 */ /*0dc0*/ FFMA R6, R18, R25, R6 ; /* 0x0000001912067223 */ /* 0x000fc80000000006 */ /*0dd0*/ FFMA R6, R22, R29, R6 ; /* 0x0000001d16067223 */ /* 0x000fc80000000006 */ /*0de0*/ FFMA R6, R20, R27, R6 ; /* 0x0000001b14067223 */ /* 0x000fc80000000006 */ /*0df0*/ FFMA R7, R7, R24, R6 ; /* 0x0000001807077223 */ /* 0x000fca0000000006 */ /*0e00*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */ /* 0x000fe2000c101908 */ /*0e10*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0e20*/ BRA 0xe20; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0e30*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0e40*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0e50*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0e60*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0e70*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0e80*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0e90*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0ea0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0eb0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0ec0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0ed0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0ee0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0ef0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include <stdio.h> #include <stdlib.h> #include <sys/time.h> #include <time.h> #define ANCHOMATRIZ 64 // Definición del kernel __global__ void matrixMul(float *a, float *b, float *c) { int row = blockIdx.y * blockDim.y + threadIdx.y; int col = blockIdx.x * blockDim.x + threadIdx.x; if (row < ANCHOMATRIZ && col < ANCHOMATRIZ) { float sum = 0.0f; for (int i = 0; i < ANCHOMATRIZ; i++) { sum += a[row * ANCHOMATRIZ + i] * b[i * ANCHOMATRIZ + col]; } c[row * ANCHOMATRIZ + col] = sum; } } void matrixMul_CPU(float *a, float *b, float *c) { float acum; for (int i = 0 ; i<ANCHOMATRIZ ; i++) { for (int j = 0 ; j<ANCHOMATRIZ ; j++) { acum = 0; for (int k = 0 ; k<ANCHOMATRIZ ; k++) { acum = acum + a[i*ANCHOMATRIZ + k]*b[k*ANCHOMATRIZ + j]; } c[i*ANCHOMATRIZ+j] = acum; } } } long long milisegundos() // Devuelve el tiempo en milisegundos desde la época Unix (01/01/1970) { struct timeval t; gettimeofday(&t, NULL); return t.tv_sec*1000 + t.tv_usec/1000; } int main(void) { int numElementos = ANCHOMATRIZ*ANCHOMATRIZ; size_t tamano = numElementos * sizeof(int); // Reservamos memoria host (memoria principal) float *h_a = (float *)malloc(tamano); float *h_b = (float *)malloc(tamano); float *h_c = (float *)malloc(tamano); long long ti,tf; // Inicializar con números arbitrarios for (int i = 0; i < ANCHOMATRIZ; ++i) { for (int j = 0; j < ANCHOMATRIZ; j++) { h_a[i*ANCHOMATRIZ+j] = rand()/(float)RAND_MAX; h_b[i*ANCHOMATRIZ+j] = rand()/(float)RAND_MAX; } } ti=milisegundos(); //tiempo inicial // Ejecutamos la multiplicación de matrices matrixMul_CPU(h_a, h_b, h_c); tf=milisegundos(); //tiempo final printf("Tiempo invertido en multiplicar CPU: %f\n", (tf-ti)); printf("------- CPU --------\n"); for (int i = 0; i < 10; ++i) { printf("Componente [%d] = %f\n", i, h_c[i]); } //Crear variables para la parte device (d_a, d_b, d_c) float *d_a, *d_b, *d_c; // Reservar memoria en la parte device cudaMalloc(&d_a, tamano); cudaMalloc(&d_b, tamano); cudaMalloc(&d_c, tamano); //Pasar datos de la memoria host a memoria device cudaMemcpy(d_a, h_a, tamano, cudaMemcpyHostToDevice); cudaMemcpy(d_b, h_b, tamano, cudaMemcpyHostToDevice); cudaMemcpy(d_c, h_c, tamano, cudaMemcpyHostToDevice); // Cada bloque tendrá 256 hilos y habrá 4096 bloques dim3 dimBlock(16,16); dim3 dimGrid(64,64); ti=milisegundos(); //tiempo inicial // Lanzar Kernel matrixMul<<<dimGrid, dimBlock>>>(d_a, d_b, d_c); //Pasar datos de la memoria device a memoria host cudaMemcpy(h_c, d_c, tamano, cudaMemcpyDeviceToHost); tf=milisegundos(); //tiempo final printf("Tiempo invertido en multiplicar GPU: %f\n", (tf-ti)); // Verificamos los primeros valores printf("------- GPU --------\n"); for (int i = 0; i < 10; ++i) { printf("Componente [%d] = %f\n", i, h_c[i]); } // Liberamos memoria device cudaFree(d_a); cudaFree(d_b); cudaFree(d_c); // Liberamos memoria host free(h_a); free(h_b); free(h_c); return 0; }
.file "tmpxft_001a2703_00000000-6_matrixmul_CPU.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2062: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2062: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z13matrixMul_CPUPfS_S_ .type _Z13matrixMul_CPUPfS_S_, @function _Z13matrixMul_CPUPfS_S_: .LFB2057: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movq %rdi, %rbx movq %rsi, %r11 movq %rdx, %r10 movl $0, %r9d .L4: leaq 16384(%r11), %rcx movq %r9, %rdi salq $8, %rdi leaq (%rbx,%rdi), %r8 addq %r10, %rdi movl $0, %esi .L8: leaq -16384(%rcx), %rax movq %r8, %rdx pxor %xmm1, %xmm1 .L5: movss (%rdx), %xmm0 mulss (%rax), %xmm0 addss %xmm0, %xmm1 addq $4, %rdx addq $256, %rax cmpq %rcx, %rax jne .L5 movss %xmm1, (%rdi,%rsi,4) addq $1, %rsi addq $4, %rcx cmpq $64, %rsi jne .L8 addq $1, %r9 cmpq $64, %r9 jne .L4 popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2057: .size _Z13matrixMul_CPUPfS_S_, .-_Z13matrixMul_CPUPfS_S_ .globl _Z12milisegundosv .type _Z12milisegundosv, @function _Z12milisegundosv: .LFB2058: .cfi_startproc endbr64 subq $40, %rsp .cfi_def_cfa_offset 48 movq %fs:40, %rax movq %rax, 24(%rsp) xorl %eax, %eax movq %rsp, %rdi movl $0, %esi call gettimeofday@PLT imulq $1000, (%rsp), %rsi movq 8(%rsp), %rcx movabsq $2361183241434822607, %rdx movq %rcx, %rax imulq %rdx sarq $7, %rdx sarq $63, %rcx subq %rcx, %rdx leaq (%rsi,%rdx), %rax movq 24(%rsp), %rdx subq %fs:40, %rdx jne .L14 addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L14: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2058: .size _Z12milisegundosv, .-_Z12milisegundosv .globl _Z32__device_stub__Z9matrixMulPfS_S_PfS_S_ .type _Z32__device_stub__Z9matrixMulPfS_S_PfS_S_, @function _Z32__device_stub__Z9matrixMulPfS_S_PfS_S_: .LFB2084: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L19 .L15: movq 120(%rsp), %rax subq %fs:40, %rax jne .L20 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L19: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z9matrixMulPfS_S_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L15 .L20: call __stack_chk_fail@PLT .cfi_endproc .LFE2084: .size _Z32__device_stub__Z9matrixMulPfS_S_PfS_S_, .-_Z32__device_stub__Z9matrixMulPfS_S_PfS_S_ .globl _Z9matrixMulPfS_S_ .type _Z9matrixMulPfS_S_, @function _Z9matrixMulPfS_S_: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z32__device_stub__Z9matrixMulPfS_S_PfS_S_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _Z9matrixMulPfS_S_, .-_Z9matrixMulPfS_S_ .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC2: .string "Tiempo invertido en multiplicar CPU: %f\n" .section .rodata.str1.1,"aMS",@progbits,1 .LC3: .string "------- CPU --------\n" .LC4: .string "Componente [%d] = %f\n" .section .rodata.str1.8 .align 8 .LC5: .string "Tiempo invertido en multiplicar GPU: %f\n" .section .rodata.str1.1 .LC6: .string "------- GPU --------\n" .text .globl main .type main, @function main: .LFB2059: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $88, %rsp .cfi_def_cfa_offset 144 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax movl $16384, %edi call malloc@PLT movq %rax, %r15 movl $16384, %edi call malloc@PLT movq %rax, %r12 movq %rax, 8(%rsp) movl $16384, %edi call malloc@PLT movq %rax, %r14 movq %r15, %rbp leaq 16384(%r15), %r13 .L24: movl $0, %ebx .L25: call rand@PLT pxor %xmm0, %xmm0 cvtsi2ssl %eax, %xmm0 mulss .LC1(%rip), %xmm0 movss %xmm0, 0(%rbp,%rbx) call rand@PLT pxor %xmm0, %xmm0 cvtsi2ssl %eax, %xmm0 mulss .LC1(%rip), %xmm0 movss %xmm0, (%r12,%rbx) addq $4, %rbx cmpq $256, %rbx jne .L25 addq $256, %rbp addq $256, %r12 cmpq %r13, %rbp jne .L24 call _Z12milisegundosv movq %rax, %rbx movq %r14, %rdx movq 8(%rsp), %rsi movq %r15, %rdi call _Z13matrixMul_CPUPfS_S_ call _Z12milisegundosv subq %rbx, %rax movq %rax, %rdx leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq .LC3(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $0, %ebx leaq .LC4(%rip), %rbp .L27: pxor %xmm0, %xmm0 cvtss2sd (%r14,%rbx,4), %xmm0 movl %ebx, %edx movq %rbp, %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT addq $1, %rbx cmpq $10, %rbx jne .L27 leaq 24(%rsp), %rdi movl $16384, %esi call cudaMalloc@PLT leaq 32(%rsp), %rdi movl $16384, %esi call cudaMalloc@PLT leaq 40(%rsp), %rdi movl $16384, %esi call cudaMalloc@PLT movl $1, %ecx movl $16384, %edx movq %r15, %rsi movq 24(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movl $16384, %edx movq 8(%rsp), %rsi movq 32(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movl $16384, %edx movq %r14, %rsi movq 40(%rsp), %rdi call cudaMemcpy@PLT movl $16, 48(%rsp) movl $16, 52(%rsp) movl $1, 56(%rsp) movl $64, 60(%rsp) movl $64, 64(%rsp) movl $1, 68(%rsp) call _Z12milisegundosv movq %rax, %rbx movl 56(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 48(%rsp), %rdx movq 60(%rsp), %rdi movl 68(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L35 .L28: movl $2, %ecx movl $16384, %edx movq 40(%rsp), %rsi movq %r14, %rdi call cudaMemcpy@PLT call _Z12milisegundosv subq %rbx, %rax movq %rax, %rdx leaq .LC5(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq .LC6(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $0, %ebx leaq .LC4(%rip), %rbp .L29: pxor %xmm0, %xmm0 cvtss2sd (%r14,%rbx,4), %xmm0 movl %ebx, %edx movq %rbp, %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT addq $1, %rbx cmpq $10, %rbx jne .L29 movq 24(%rsp), %rdi call cudaFree@PLT movq 32(%rsp), %rdi call cudaFree@PLT movq 40(%rsp), %rdi call cudaFree@PLT movq %r15, %rdi call free@PLT movq 8(%rsp), %rdi call free@PLT movq %r14, %rdi call free@PLT movq 72(%rsp), %rax subq %fs:40, %rax jne .L36 movl $0, %eax addq $88, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L35: .cfi_restore_state movq 40(%rsp), %rdx movq 32(%rsp), %rsi movq 24(%rsp), %rdi call _Z32__device_stub__Z9matrixMulPfS_S_PfS_S_ jmp .L28 .L36: call __stack_chk_fail@PLT .cfi_endproc .LFE2059: .size main, .-main .section .rodata.str1.1 .LC7: .string "_Z9matrixMulPfS_S_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2087: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC7(%rip), %rdx movq %rdx, %rcx leaq _Z9matrixMulPfS_S_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2087: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC1: .long 805306368 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include <stdio.h> #include <stdlib.h> #include <sys/time.h> #include <time.h> #define ANCHOMATRIZ 64 // Definición del kernel __global__ void matrixMul(float *a, float *b, float *c) { int row = blockIdx.y * blockDim.y + threadIdx.y; int col = blockIdx.x * blockDim.x + threadIdx.x; if (row < ANCHOMATRIZ && col < ANCHOMATRIZ) { float sum = 0.0f; for (int i = 0; i < ANCHOMATRIZ; i++) { sum += a[row * ANCHOMATRIZ + i] * b[i * ANCHOMATRIZ + col]; } c[row * ANCHOMATRIZ + col] = sum; } } void matrixMul_CPU(float *a, float *b, float *c) { float acum; for (int i = 0 ; i<ANCHOMATRIZ ; i++) { for (int j = 0 ; j<ANCHOMATRIZ ; j++) { acum = 0; for (int k = 0 ; k<ANCHOMATRIZ ; k++) { acum = acum + a[i*ANCHOMATRIZ + k]*b[k*ANCHOMATRIZ + j]; } c[i*ANCHOMATRIZ+j] = acum; } } } long long milisegundos() // Devuelve el tiempo en milisegundos desde la época Unix (01/01/1970) { struct timeval t; gettimeofday(&t, NULL); return t.tv_sec*1000 + t.tv_usec/1000; } int main(void) { int numElementos = ANCHOMATRIZ*ANCHOMATRIZ; size_t tamano = numElementos * sizeof(int); // Reservamos memoria host (memoria principal) float *h_a = (float *)malloc(tamano); float *h_b = (float *)malloc(tamano); float *h_c = (float *)malloc(tamano); long long ti,tf; // Inicializar con números arbitrarios for (int i = 0; i < ANCHOMATRIZ; ++i) { for (int j = 0; j < ANCHOMATRIZ; j++) { h_a[i*ANCHOMATRIZ+j] = rand()/(float)RAND_MAX; h_b[i*ANCHOMATRIZ+j] = rand()/(float)RAND_MAX; } } ti=milisegundos(); //tiempo inicial // Ejecutamos la multiplicación de matrices matrixMul_CPU(h_a, h_b, h_c); tf=milisegundos(); //tiempo final printf("Tiempo invertido en multiplicar CPU: %f\n", (tf-ti)); printf("------- CPU --------\n"); for (int i = 0; i < 10; ++i) { printf("Componente [%d] = %f\n", i, h_c[i]); } //Crear variables para la parte device (d_a, d_b, d_c) float *d_a, *d_b, *d_c; // Reservar memoria en la parte device cudaMalloc(&d_a, tamano); cudaMalloc(&d_b, tamano); cudaMalloc(&d_c, tamano); //Pasar datos de la memoria host a memoria device cudaMemcpy(d_a, h_a, tamano, cudaMemcpyHostToDevice); cudaMemcpy(d_b, h_b, tamano, cudaMemcpyHostToDevice); cudaMemcpy(d_c, h_c, tamano, cudaMemcpyHostToDevice); // Cada bloque tendrá 256 hilos y habrá 4096 bloques dim3 dimBlock(16,16); dim3 dimGrid(64,64); ti=milisegundos(); //tiempo inicial // Lanzar Kernel matrixMul<<<dimGrid, dimBlock>>>(d_a, d_b, d_c); //Pasar datos de la memoria device a memoria host cudaMemcpy(h_c, d_c, tamano, cudaMemcpyDeviceToHost); tf=milisegundos(); //tiempo final printf("Tiempo invertido en multiplicar GPU: %f\n", (tf-ti)); // Verificamos los primeros valores printf("------- GPU --------\n"); for (int i = 0; i < 10; ++i) { printf("Componente [%d] = %f\n", i, h_c[i]); } // Liberamos memoria device cudaFree(d_a); cudaFree(d_b); cudaFree(d_c); // Liberamos memoria host free(h_a); free(h_b); free(h_c); return 0; }
#include <hip/hip_runtime.h> #include <stdio.h> #include <stdlib.h> #include <sys/time.h> #include <time.h> #define ANCHOMATRIZ 64 // Definición del kernel __global__ void matrixMul(float *a, float *b, float *c) { int row = blockIdx.y * blockDim.y + threadIdx.y; int col = blockIdx.x * blockDim.x + threadIdx.x; if (row < ANCHOMATRIZ && col < ANCHOMATRIZ) { float sum = 0.0f; for (int i = 0; i < ANCHOMATRIZ; i++) { sum += a[row * ANCHOMATRIZ + i] * b[i * ANCHOMATRIZ + col]; } c[row * ANCHOMATRIZ + col] = sum; } } void matrixMul_CPU(float *a, float *b, float *c) { float acum; for (int i = 0 ; i<ANCHOMATRIZ ; i++) { for (int j = 0 ; j<ANCHOMATRIZ ; j++) { acum = 0; for (int k = 0 ; k<ANCHOMATRIZ ; k++) { acum = acum + a[i*ANCHOMATRIZ + k]*b[k*ANCHOMATRIZ + j]; } c[i*ANCHOMATRIZ+j] = acum; } } } long long milisegundos() // Devuelve el tiempo en milisegundos desde la época Unix (01/01/1970) { struct timeval t; gettimeofday(&t, NULL); return t.tv_sec*1000 + t.tv_usec/1000; } int main(void) { int numElementos = ANCHOMATRIZ*ANCHOMATRIZ; size_t tamano = numElementos * sizeof(int); // Reservamos memoria host (memoria principal) float *h_a = (float *)malloc(tamano); float *h_b = (float *)malloc(tamano); float *h_c = (float *)malloc(tamano); long long ti,tf; // Inicializar con números arbitrarios for (int i = 0; i < ANCHOMATRIZ; ++i) { for (int j = 0; j < ANCHOMATRIZ; j++) { h_a[i*ANCHOMATRIZ+j] = rand()/(float)RAND_MAX; h_b[i*ANCHOMATRIZ+j] = rand()/(float)RAND_MAX; } } ti=milisegundos(); //tiempo inicial // Ejecutamos la multiplicación de matrices matrixMul_CPU(h_a, h_b, h_c); tf=milisegundos(); //tiempo final printf("Tiempo invertido en multiplicar CPU: %f\n", (tf-ti)); printf("------- CPU --------\n"); for (int i = 0; i < 10; ++i) { printf("Componente [%d] = %f\n", i, h_c[i]); } //Crear variables para la parte device (d_a, d_b, d_c) float *d_a, *d_b, *d_c; // Reservar memoria en la parte device hipMalloc(&d_a, tamano); hipMalloc(&d_b, tamano); hipMalloc(&d_c, tamano); //Pasar datos de la memoria host a memoria device hipMemcpy(d_a, h_a, tamano, hipMemcpyHostToDevice); hipMemcpy(d_b, h_b, tamano, hipMemcpyHostToDevice); hipMemcpy(d_c, h_c, tamano, hipMemcpyHostToDevice); // Cada bloque tendrá 256 hilos y habrá 4096 bloques dim3 dimBlock(16,16); dim3 dimGrid(64,64); ti=milisegundos(); //tiempo inicial // Lanzar Kernel matrixMul<<<dimGrid, dimBlock>>>(d_a, d_b, d_c); //Pasar datos de la memoria device a memoria host hipMemcpy(h_c, d_c, tamano, hipMemcpyDeviceToHost); tf=milisegundos(); //tiempo final printf("Tiempo invertido en multiplicar GPU: %f\n", (tf-ti)); // Verificamos los primeros valores printf("------- GPU --------\n"); for (int i = 0; i < 10; ++i) { printf("Componente [%d] = %f\n", i, h_c[i]); } // Liberamos memoria device hipFree(d_a); hipFree(d_b); hipFree(d_c); // Liberamos memoria host free(h_a); free(h_b); free(h_c); return 0; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include <stdio.h> #include <stdlib.h> #include <sys/time.h> #include <time.h> #define ANCHOMATRIZ 64 // Definición del kernel __global__ void matrixMul(float *a, float *b, float *c) { int row = blockIdx.y * blockDim.y + threadIdx.y; int col = blockIdx.x * blockDim.x + threadIdx.x; if (row < ANCHOMATRIZ && col < ANCHOMATRIZ) { float sum = 0.0f; for (int i = 0; i < ANCHOMATRIZ; i++) { sum += a[row * ANCHOMATRIZ + i] * b[i * ANCHOMATRIZ + col]; } c[row * ANCHOMATRIZ + col] = sum; } } void matrixMul_CPU(float *a, float *b, float *c) { float acum; for (int i = 0 ; i<ANCHOMATRIZ ; i++) { for (int j = 0 ; j<ANCHOMATRIZ ; j++) { acum = 0; for (int k = 0 ; k<ANCHOMATRIZ ; k++) { acum = acum + a[i*ANCHOMATRIZ + k]*b[k*ANCHOMATRIZ + j]; } c[i*ANCHOMATRIZ+j] = acum; } } } long long milisegundos() // Devuelve el tiempo en milisegundos desde la época Unix (01/01/1970) { struct timeval t; gettimeofday(&t, NULL); return t.tv_sec*1000 + t.tv_usec/1000; } int main(void) { int numElementos = ANCHOMATRIZ*ANCHOMATRIZ; size_t tamano = numElementos * sizeof(int); // Reservamos memoria host (memoria principal) float *h_a = (float *)malloc(tamano); float *h_b = (float *)malloc(tamano); float *h_c = (float *)malloc(tamano); long long ti,tf; // Inicializar con números arbitrarios for (int i = 0; i < ANCHOMATRIZ; ++i) { for (int j = 0; j < ANCHOMATRIZ; j++) { h_a[i*ANCHOMATRIZ+j] = rand()/(float)RAND_MAX; h_b[i*ANCHOMATRIZ+j] = rand()/(float)RAND_MAX; } } ti=milisegundos(); //tiempo inicial // Ejecutamos la multiplicación de matrices matrixMul_CPU(h_a, h_b, h_c); tf=milisegundos(); //tiempo final printf("Tiempo invertido en multiplicar CPU: %f\n", (tf-ti)); printf("------- CPU --------\n"); for (int i = 0; i < 10; ++i) { printf("Componente [%d] = %f\n", i, h_c[i]); } //Crear variables para la parte device (d_a, d_b, d_c) float *d_a, *d_b, *d_c; // Reservar memoria en la parte device hipMalloc(&d_a, tamano); hipMalloc(&d_b, tamano); hipMalloc(&d_c, tamano); //Pasar datos de la memoria host a memoria device hipMemcpy(d_a, h_a, tamano, hipMemcpyHostToDevice); hipMemcpy(d_b, h_b, tamano, hipMemcpyHostToDevice); hipMemcpy(d_c, h_c, tamano, hipMemcpyHostToDevice); // Cada bloque tendrá 256 hilos y habrá 4096 bloques dim3 dimBlock(16,16); dim3 dimGrid(64,64); ti=milisegundos(); //tiempo inicial // Lanzar Kernel matrixMul<<<dimGrid, dimBlock>>>(d_a, d_b, d_c); //Pasar datos de la memoria device a memoria host hipMemcpy(h_c, d_c, tamano, hipMemcpyDeviceToHost); tf=milisegundos(); //tiempo final printf("Tiempo invertido en multiplicar GPU: %f\n", (tf-ti)); // Verificamos los primeros valores printf("------- GPU --------\n"); for (int i = 0; i < 10; ++i) { printf("Componente [%d] = %f\n", i, h_c[i]); } // Liberamos memoria device hipFree(d_a); hipFree(d_b); hipFree(d_c); // Liberamos memoria host free(h_a); free(h_b); free(h_c); return 0; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z9matrixMulPfS_S_ .globl _Z9matrixMulPfS_S_ .p2align 8 .type _Z9matrixMulPfS_S_,@function _Z9matrixMulPfS_S_: s_load_b32 s2, s[0:1], 0x24 v_bfe_u32 v2, v0, 10, 10 v_and_b32_e32 v3, 0x3ff, v0 s_waitcnt lgkmcnt(0) s_lshr_b32 s3, s2, 16 s_and_b32 s2, s2, 0xffff s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3] v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4] s_mov_b32 s2, exec_lo v_max_i32_e32 v2, v0, v1 s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_i32_e32 64, v2 s_cbranch_execz .LBB0_4 s_load_b128 s[4:7], s[0:1], 0x0 v_lshlrev_b32_e32 v2, 6, v0 v_mov_b32_e32 v4, 0 s_mov_b64 s[2:3], 0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v3, 31, v2 v_lshlrev_b64 v[2:3], 2, v[2:3] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v5, vcc_lo, s4, v2 v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo v_mov_b32_e32 v2, v1 .p2align 6 .LBB0_2: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) v_ashrrev_i32_e32 v3, 31, v2 v_add_co_u32 v7, vcc_lo, v5, s2 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e32 v8, vcc_lo, s3, v6, vcc_lo v_lshlrev_b64 v[9:10], 2, v[2:3] v_add_nc_u32_e32 v2, 64, v2 s_add_u32 s2, s2, 4 s_addc_u32 s3, s3, 0 s_cmpk_eq_i32 s2, 0x100 s_delay_alu instid0(VALU_DEP_2) v_add_co_u32 v9, vcc_lo, s6, v9 v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo global_load_b32 v3, v[7:8], off global_load_b32 v7, v[9:10], off s_waitcnt vmcnt(0) v_fmac_f32_e32 v4, v3, v7 s_cbranch_scc0 .LBB0_2 s_load_b64 s[0:1], s[0:1], 0x10 v_lshl_add_u32 v0, v0, 6, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v1, 31, v0 v_lshlrev_b64 v[0:1], 2, v[0:1] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_store_b32 v[0:1], v4, off .LBB0_4: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9matrixMulPfS_S_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 11 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z9matrixMulPfS_S_, .Lfunc_end0-_Z9matrixMulPfS_S_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9matrixMulPfS_S_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z9matrixMulPfS_S_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 11 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include <stdio.h> #include <stdlib.h> #include <sys/time.h> #include <time.h> #define ANCHOMATRIZ 64 // Definición del kernel __global__ void matrixMul(float *a, float *b, float *c) { int row = blockIdx.y * blockDim.y + threadIdx.y; int col = blockIdx.x * blockDim.x + threadIdx.x; if (row < ANCHOMATRIZ && col < ANCHOMATRIZ) { float sum = 0.0f; for (int i = 0; i < ANCHOMATRIZ; i++) { sum += a[row * ANCHOMATRIZ + i] * b[i * ANCHOMATRIZ + col]; } c[row * ANCHOMATRIZ + col] = sum; } } void matrixMul_CPU(float *a, float *b, float *c) { float acum; for (int i = 0 ; i<ANCHOMATRIZ ; i++) { for (int j = 0 ; j<ANCHOMATRIZ ; j++) { acum = 0; for (int k = 0 ; k<ANCHOMATRIZ ; k++) { acum = acum + a[i*ANCHOMATRIZ + k]*b[k*ANCHOMATRIZ + j]; } c[i*ANCHOMATRIZ+j] = acum; } } } long long milisegundos() // Devuelve el tiempo en milisegundos desde la época Unix (01/01/1970) { struct timeval t; gettimeofday(&t, NULL); return t.tv_sec*1000 + t.tv_usec/1000; } int main(void) { int numElementos = ANCHOMATRIZ*ANCHOMATRIZ; size_t tamano = numElementos * sizeof(int); // Reservamos memoria host (memoria principal) float *h_a = (float *)malloc(tamano); float *h_b = (float *)malloc(tamano); float *h_c = (float *)malloc(tamano); long long ti,tf; // Inicializar con números arbitrarios for (int i = 0; i < ANCHOMATRIZ; ++i) { for (int j = 0; j < ANCHOMATRIZ; j++) { h_a[i*ANCHOMATRIZ+j] = rand()/(float)RAND_MAX; h_b[i*ANCHOMATRIZ+j] = rand()/(float)RAND_MAX; } } ti=milisegundos(); //tiempo inicial // Ejecutamos la multiplicación de matrices matrixMul_CPU(h_a, h_b, h_c); tf=milisegundos(); //tiempo final printf("Tiempo invertido en multiplicar CPU: %f\n", (tf-ti)); printf("------- CPU --------\n"); for (int i = 0; i < 10; ++i) { printf("Componente [%d] = %f\n", i, h_c[i]); } //Crear variables para la parte device (d_a, d_b, d_c) float *d_a, *d_b, *d_c; // Reservar memoria en la parte device hipMalloc(&d_a, tamano); hipMalloc(&d_b, tamano); hipMalloc(&d_c, tamano); //Pasar datos de la memoria host a memoria device hipMemcpy(d_a, h_a, tamano, hipMemcpyHostToDevice); hipMemcpy(d_b, h_b, tamano, hipMemcpyHostToDevice); hipMemcpy(d_c, h_c, tamano, hipMemcpyHostToDevice); // Cada bloque tendrá 256 hilos y habrá 4096 bloques dim3 dimBlock(16,16); dim3 dimGrid(64,64); ti=milisegundos(); //tiempo inicial // Lanzar Kernel matrixMul<<<dimGrid, dimBlock>>>(d_a, d_b, d_c); //Pasar datos de la memoria device a memoria host hipMemcpy(h_c, d_c, tamano, hipMemcpyDeviceToHost); tf=milisegundos(); //tiempo final printf("Tiempo invertido en multiplicar GPU: %f\n", (tf-ti)); // Verificamos los primeros valores printf("------- GPU --------\n"); for (int i = 0; i < 10; ++i) { printf("Componente [%d] = %f\n", i, h_c[i]); } // Liberamos memoria device hipFree(d_a); hipFree(d_b); hipFree(d_c); // Liberamos memoria host free(h_a); free(h_b); free(h_c); return 0; }
.text .file "matrixmul_CPU.hip" .globl _Z24__device_stub__matrixMulPfS_S_ # -- Begin function _Z24__device_stub__matrixMulPfS_S_ .p2align 4, 0x90 .type _Z24__device_stub__matrixMulPfS_S_,@function _Z24__device_stub__matrixMulPfS_S_: # @_Z24__device_stub__matrixMulPfS_S_ .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z9matrixMulPfS_S_, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z24__device_stub__matrixMulPfS_S_, .Lfunc_end0-_Z24__device_stub__matrixMulPfS_S_ .cfi_endproc # -- End function .globl _Z13matrixMul_CPUPfS_S_ # -- Begin function _Z13matrixMul_CPUPfS_S_ .p2align 4, 0x90 .type _Z13matrixMul_CPUPfS_S_,@function _Z13matrixMul_CPUPfS_S_: # @_Z13matrixMul_CPUPfS_S_ .cfi_startproc # %bb.0: xorl %eax, %eax .p2align 4, 0x90 .LBB1_1: # %.preheader19 # =>This Loop Header: Depth=1 # Child Loop BB1_2 Depth 2 # Child Loop BB1_3 Depth 3 movq %rax, %rcx shlq $8, %rcx addq %rdx, %rcx movq %rsi, %r8 xorl %r9d, %r9d .p2align 4, 0x90 .LBB1_2: # %.preheader # Parent Loop BB1_1 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB1_3 Depth 3 xorps %xmm0, %xmm0 movq %r8, %r10 xorl %r11d, %r11d .p2align 4, 0x90 .LBB1_3: # Parent Loop BB1_1 Depth=1 # Parent Loop BB1_2 Depth=2 # => This Inner Loop Header: Depth=3 movss (%rdi,%r11,4), %xmm1 # xmm1 = mem[0],zero,zero,zero mulss (%r10), %xmm1 addss %xmm1, %xmm0 incq %r11 addq $256, %r10 # imm = 0x100 cmpq $64, %r11 jne .LBB1_3 # %bb.4: # in Loop: Header=BB1_2 Depth=2 movss %xmm0, (%rcx,%r9,4) incq %r9 addq $4, %r8 cmpq $64, %r9 jne .LBB1_2 # %bb.5: # in Loop: Header=BB1_1 Depth=1 incq %rax addq $256, %rdi # imm = 0x100 cmpq $64, %rax jne .LBB1_1 # %bb.6: retq .Lfunc_end1: .size _Z13matrixMul_CPUPfS_S_, .Lfunc_end1-_Z13matrixMul_CPUPfS_S_ .cfi_endproc # -- End function .globl _Z12milisegundosv # -- Begin function _Z12milisegundosv .p2align 4, 0x90 .type _Z12milisegundosv,@function _Z12milisegundosv: # @_Z12milisegundosv .cfi_startproc # %bb.0: subq $24, %rsp .cfi_def_cfa_offset 32 leaq 8(%rsp), %rdi xorl %esi, %esi callq gettimeofday imulq $1000, 8(%rsp), %rcx # imm = 0x3E8 movabsq $2361183241434822607, %rax # imm = 0x20C49BA5E353F7CF imulq 16(%rsp) movq %rdx, %rax shrq $63, %rax sarq $7, %rdx addq %rdx, %rax addq %rcx, %rax addq $24, %rsp .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size _Z12milisegundosv, .Lfunc_end2-_Z12milisegundosv .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI3_0: .long 0x30000000 # float 4.65661287E-10 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $136, %rsp .cfi_def_cfa_offset 192 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $16384, %edi # imm = 0x4000 callq malloc movq %rax, %r13 movl $16384, %edi # imm = 0x4000 callq malloc movq %rax, %r14 movl $16384, %edi # imm = 0x4000 callq malloc movq %rax, %r15 xorl %r12d, %r12d movq %r13, 40(%rsp) # 8-byte Spill movq %r14, %rbp .p2align 4, 0x90 .LBB3_1: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB3_2 Depth 2 xorl %ebx, %ebx .p2align 4, 0x90 .LBB3_2: # Parent Loop BB3_1 Depth=1 # => This Inner Loop Header: Depth=2 callq rand xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 mulss .LCPI3_0(%rip), %xmm0 movss %xmm0, (%r13,%rbx,4) callq rand movss .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 mulss %xmm1, %xmm0 movss %xmm0, (%rbp,%rbx,4) incq %rbx cmpq $64, %rbx jne .LBB3_2 # %bb.3: # in Loop: Header=BB3_1 Depth=1 incq %r12 addq $256, %rbp # imm = 0x100 addq $256, %r13 # imm = 0x100 cmpq $64, %r12 jne .LBB3_1 # %bb.4: xorl %r12d, %r12d movq %rsp, %rdi xorl %esi, %esi callq gettimeofday movq (%rsp), %r13 movq 8(%rsp), %rax movq 40(%rsp), %rcx # 8-byte Reload .p2align 4, 0x90 .LBB3_5: # %.preheader19.i # =>This Loop Header: Depth=1 # Child Loop BB3_6 Depth 2 # Child Loop BB3_7 Depth 3 movq %r12, %rdx shlq $8, %rdx addq %r15, %rdx movq %r14, %rsi xorl %edi, %edi .p2align 4, 0x90 .LBB3_6: # %.preheader.i # Parent Loop BB3_5 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB3_7 Depth 3 xorps %xmm0, %xmm0 movq %rsi, %r8 xorl %r9d, %r9d .p2align 4, 0x90 .LBB3_7: # Parent Loop BB3_5 Depth=1 # Parent Loop BB3_6 Depth=2 # => This Inner Loop Header: Depth=3 movss (%rcx,%r9,4), %xmm1 # xmm1 = mem[0],zero,zero,zero mulss (%r8), %xmm1 addss %xmm1, %xmm0 incq %r9 addq $256, %r8 # imm = 0x100 cmpq $64, %r9 jne .LBB3_7 # %bb.8: # in Loop: Header=BB3_6 Depth=2 movss %xmm0, (%rdx,%rdi,4) incq %rdi addq $4, %rsi cmpq $64, %rdi jne .LBB3_6 # %bb.9: # in Loop: Header=BB3_5 Depth=1 incq %r12 addq $256, %rcx # imm = 0x100 cmpq $64, %r12 jne .LBB3_5 # %bb.10: # %_Z13matrixMul_CPUPfS_S_.exit movabsq $-2361183241434822607, %rcx # imm = 0xDF3B645A1CAC0831 imulq %rcx movq %rdx, %rbx shrq $63, %rbx sarq $7, %rdx addq %rdx, %rbx xorl %r12d, %r12d movq %rsp, %rdi xorl %esi, %esi callq gettimeofday movq (%rsp), %rcx subq %r13, %rcx movabsq $2361183241434822607, %rax # imm = 0x20C49BA5E353F7CF imulq 8(%rsp) movq %rdx, %rax shrq $63, %rax sarq $7, %rdx addq %rdx, %rax addq %rbx, %rax imulq $1000, %rcx, %rsi # imm = 0x3E8 addq %rax, %rsi movl $.L.str, %edi xorl %eax, %eax callq printf movl $.Lstr, %edi callq puts@PLT .p2align 4, 0x90 .LBB3_11: # =>This Inner Loop Header: Depth=1 movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str.2, %edi movl %r12d, %esi movb $1, %al callq printf incq %r12 cmpq $10, %r12 jne .LBB3_11 # %bb.12: leaq 56(%rsp), %rdi movl $16384, %esi # imm = 0x4000 callq hipMalloc leaq 48(%rsp), %rdi movl $16384, %esi # imm = 0x4000 callq hipMalloc leaq 32(%rsp), %rdi movl $16384, %esi # imm = 0x4000 callq hipMalloc movq 56(%rsp), %rdi movl $16384, %edx # imm = 0x4000 movq 40(%rsp), %rsi # 8-byte Reload movl $1, %ecx callq hipMemcpy movq 48(%rsp), %rdi movl $16384, %edx # imm = 0x4000 movq %r14, %rsi movl $1, %ecx callq hipMemcpy movq 32(%rsp), %rdi movl $16384, %edx # imm = 0x4000 movq %r15, %rsi movl $1, %ecx callq hipMemcpy movq %rsp, %rdi xorl %esi, %esi callq gettimeofday movq (%rsp), %rbp movabsq $-2361183241434822607, %rax # imm = 0xDF3B645A1CAC0831 imulq 8(%rsp) movq %rdx, %r12 movq %rdx, %rax shrq $63, %rax sarq $7, %r12 addq %rax, %r12 movabsq $274877907008, %rdi # imm = 0x4000000040 movabsq $68719476752, %rdx # imm = 0x1000000010 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_14 # %bb.13: movq 56(%rsp), %rax movq 48(%rsp), %rcx movq 32(%rsp), %rdx movq %rax, 128(%rsp) movq %rcx, 120(%rsp) movq %rdx, 112(%rsp) leaq 128(%rsp), %rax movq %rax, (%rsp) leaq 120(%rsp), %rax movq %rax, 8(%rsp) leaq 112(%rsp), %rax movq %rax, 16(%rsp) leaq 96(%rsp), %rdi leaq 80(%rsp), %rsi leaq 72(%rsp), %rdx leaq 64(%rsp), %rcx callq __hipPopCallConfiguration movq 96(%rsp), %rsi movl 104(%rsp), %edx movq 80(%rsp), %rcx movl 88(%rsp), %r8d movq %rsp, %r9 movl $_Z9matrixMulPfS_S_, %edi pushq 64(%rsp) .cfi_adjust_cfa_offset 8 pushq 80(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB3_14: movq 32(%rsp), %rsi movl $16384, %edx # imm = 0x4000 movq %r15, %rdi movl $2, %ecx callq hipMemcpy xorl %r13d, %r13d movq %rsp, %rdi xorl %esi, %esi callq gettimeofday movq (%rsp), %rcx subq %rbp, %rcx movabsq $2361183241434822607, %rax # imm = 0x20C49BA5E353F7CF imulq 8(%rsp) movq %rdx, %rax shrq $63, %rax sarq $7, %rdx addq %rdx, %rax addq %r12, %rax imulq $1000, %rcx, %rsi # imm = 0x3E8 addq %rax, %rsi movl $.L.str.3, %edi xorl %eax, %eax callq printf movl $.Lstr.1, %edi callq puts@PLT .p2align 4, 0x90 .LBB3_15: # =>This Inner Loop Header: Depth=1 movss (%r15,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str.2, %edi movl %r13d, %esi movb $1, %al callq printf incq %r13 cmpq $10, %r13 jne .LBB3_15 # %bb.16: movq 56(%rsp), %rdi callq hipFree movq 48(%rsp), %rdi callq hipFree movq 32(%rsp), %rdi callq hipFree movq 40(%rsp), %rdi # 8-byte Reload callq free movq %r14, %rdi callq free movq %r15, %rdi callq free xorl %eax, %eax addq $136, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end3: .size main, .Lfunc_end3-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB4_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB4_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9matrixMulPfS_S_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end4: .size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB5_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB5_2: retq .Lfunc_end5: .size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor .cfi_endproc # -- End function .type _Z9matrixMulPfS_S_,@object # @_Z9matrixMulPfS_S_ .section .rodata,"a",@progbits .globl _Z9matrixMulPfS_S_ .p2align 3, 0x0 _Z9matrixMulPfS_S_: .quad _Z24__device_stub__matrixMulPfS_S_ .size _Z9matrixMulPfS_S_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Tiempo invertido en multiplicar CPU: %f\n" .size .L.str, 41 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Componente [%d] = %f\n" .size .L.str.2, 22 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Tiempo invertido en multiplicar GPU: %f\n" .size .L.str.3, 41 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z9matrixMulPfS_S_" .size .L__unnamed_1, 19 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "------- CPU --------" .size .Lstr, 21 .type .Lstr.1,@object # @str.1 .Lstr.1: .asciz "------- GPU --------" .size .Lstr.1, 21 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z24__device_stub__matrixMulPfS_S_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z9matrixMulPfS_S_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z9matrixMulPfS_S_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */ /* 0x000e280000002500 */ /*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */ /* 0x000e280000002100 */ /*0030*/ S2R R13, SR_CTAID.Y ; /* 0x00000000000d7919 */ /* 0x000e680000002600 */ /*0040*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */ /* 0x000e620000002200 */ /*0050*/ IMAD R11, R11, c[0x0][0x0], R2 ; /* 0x000000000b0b7a24 */ /* 0x001fca00078e0202 */ /*0060*/ ISETP.GT.AND P0, PT, R11, 0x3f, PT ; /* 0x0000003f0b00780c */ /* 0x000fe20003f04270 */ /*0070*/ IMAD R13, R13, c[0x0][0x4], R0 ; /* 0x000001000d0d7a24 */ /* 0x002fca00078e0200 */ /*0080*/ ISETP.GT.OR P0, PT, R13, 0x3f, P0 ; /* 0x0000003f0d00780c */ /* 0x000fda0000704670 */ /*0090*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*00a0*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */ /* 0x000fe200000001ff */ /*00b0*/ SHF.L.U32 R13, R13, 0x6, RZ ; /* 0x000000060d0d7819 */ /* 0x000fe200000006ff */ /*00c0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */ /* 0x000fe40000000a00 */ /*00d0*/ ULDC.64 UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */ /* 0x000fe20000000a00 */ /*00e0*/ IADD3 R27, R13, 0x1, RZ ; /* 0x000000010d1b7810 */ /* 0x000fe20007ffe0ff */ /*00f0*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */ /* 0x000fc80000000a00 */ /*0100*/ IMAD.WIDE R2, R13, R0, c[0x0][0x160] ; /* 0x000058000d027625 */ /* 0x000fc800078e0200 */ /*0110*/ IMAD.WIDE R28, R11, R0.reuse, c[0x0][0x168] ; /* 0x00005a000b1c7625 */ /* 0x080fe200078e0200 */ /*0120*/ LDG.E R15, [R2.64] ; /* 0x00000008020f7981 */ /* 0x0000a6000c1e1900 */ /*0130*/ IMAD.WIDE R8, R27, R0, c[0x0][0x160] ; /* 0x000058001b087625 */ /* 0x000fe200078e0200 */ /*0140*/ LDG.E R10, [R28.64] ; /* 0x000000081c0a7981 */ /* 0x000ea8000c1e1900 */ /*0150*/ LDG.E R25, [R28.64+0x100] ; /* 0x000100081c197981 */ /* 0x000ee8000c1e1900 */ /*0160*/ LDG.E R20, [R8.64] ; /* 0x0000000808147981 */ /* 0x000ee8000c1e1900 */ /*0170*/ LDG.E R17, [R28.64+0x200] ; /* 0x000200081c117981 */ /* 0x000f28000c1e1900 */ /*0180*/ LDG.E R12, [R8.64+0x4] ; /* 0x00000408080c7981 */ /* 0x000f28000c1e1900 */ /*0190*/ LDG.E R14, [R28.64+0x300] ; /* 0x000300081c0e7981 */ /* 0x000f68000c1e1900 */ /*01a0*/ LDG.E R19, [R8.64+0x8] ; /* 0x0000080808137981 */ /* 0x000f68000c1e1900 */ /*01b0*/ LDG.E R16, [R28.64+0x400] ; /* 0x000400081c107981 */ /* 0x000f68000c1e1900 */ /*01c0*/ LDG.E R21, [R8.64+0xc] ; /* 0x00000c0808157981 */ /* 0x000f68000c1e1900 */ /*01d0*/ LDG.E R2, [R28.64+0x500] ; /* 0x000500081c027981 */ /* 0x001f68000c1e1900 */ /*01e0*/ LDG.E R3, [R8.64+0x10] ; /* 0x0000100808037981 */ /* 0x000f68000c1e1900 */ /*01f0*/ LDG.E R4, [R28.64+0x600] ; /* 0x000600081c047981 */ /* 0x000f68000c1e1900 */ /*0200*/ LDG.E R5, [R8.64+0x14] ; /* 0x0000140808057981 */ /* 0x000f68000c1e1900 */ /*0210*/ LDG.E R6, [R28.64+0x700] ; /* 0x000700081c067981 */ /* 0x000f68000c1e1900 */ /*0220*/ LDG.E R7, [R8.64+0x18] ; /* 0x0000180808077981 */ /* 0x000f68000c1e1900 */ /*0230*/ LDG.E R18, [R28.64+0x800] ; /* 0x000800081c127981 */ /* 0x000f68000c1e1900 */ /*0240*/ LDG.E R23, [R8.64+0x1c] ; /* 0x00001c0808177981 */ /* 0x000f62000c1e1900 */ /*0250*/ UIADD3 UR4, UP0, UR4, 0x1000, URZ ; /* 0x0000100004047890 */ /* 0x000fc4000ff1e03f */ /*0260*/ UIADD3 UR6, UP1, UR6, 0x40, URZ ; /* 0x0000004006067890 */ /* 0x000fe2000ff3e03f */ /*0270*/ LDG.E R22, [R28.64+0xe00] ; /* 0x000e00081c167981 */ /* 0x000168000c1e1900 */ /*0280*/ LDG.E R24, [R28.64+0xf00] ; /* 0x000f00081c187981 */ /* 0x000168000c1e1900 */ /*0290*/ LDG.E R26, [R8.64+0x38] ; /* 0x00003808081a7981 */ /* 0x000362000c1e1900 */ /*02a0*/ FFMA R10, R10, R15, RZ ; /* 0x0000000f0a0a7223 */ /* 0x004fc600000000ff */ /*02b0*/ LDG.E R15, [R8.64+0x20] ; /* 0x00002008080f7981 */ /* 0x0002a2000c1e1900 */ /*02c0*/ FFMA R20, R25, R20, R10 ; /* 0x0000001419147223 */ /* 0x008fc6000000000a */ /*02d0*/ LDG.E R10, [R28.64+0x900] ; /* 0x000900081c0a7981 */ /* 0x0000a2000c1e1900 */ /*02e0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */ /* 0x000fe400087fe43f */ /*02f0*/ UIADD3.X UR7, URZ, UR7, URZ, UP1, !UPT ; /* 0x000000073f077290 */ /* 0x000fe20008ffe43f */ /*0300*/ LDG.E R25, [R8.64+0x34] ; /* 0x0000340808197981 */ /* 0x0002e2000c1e1900 */ /*0310*/ FFMA R20, R17, R12, R20 ; /* 0x0000000c11147223 */ /* 0x010fc60000000014 */ /*0320*/ LDG.E R12, [R28.64+0xa00] ; /* 0x000a00081c0c7981 */ /* 0x000128000c1e1900 */ /*0330*/ LDG.E R17, [R8.64+0x24] ; /* 0x0000240808117981 */ /* 0x000322000c1e1900 */ /*0340*/ FFMA R20, R14, R19, R20 ; /* 0x000000130e147223 */ /* 0x020fc60000000014 */ /*0350*/ LDG.E R14, [R28.64+0xb00] ; /* 0x000b00081c0e7981 */ /* 0x000168000c1e1900 */ /*0360*/ LDG.E R19, [R8.64+0x28] ; /* 0x0000280808137981 */ /* 0x000362000c1e1900 */ /*0370*/ FFMA R20, R16, R21, R20 ; /* 0x0000001510147223 */ /* 0x000fc60000000014 */ /*0380*/ LDG.E R16, [R28.64+0xc00] ; /* 0x000c00081c107981 */ /* 0x0000e8000c1e1900 */ /*0390*/ LDG.E R21, [R8.64+0x2c] ; /* 0x00002c0808157981 */ /* 0x0002e2000c1e1900 */ /*03a0*/ FFMA R2, R2, R3, R20 ; /* 0x0000000302027223 */ /* 0x000fc60000000014 */ /*03b0*/ LDG.E R20, [R28.64+0xd00] ; /* 0x000d00081c147981 */ /* 0x0000e2000c1e1900 */ /*03c0*/ FFMA R2, R4, R5, R2 ; /* 0x0000000504027223 */ /* 0x000fc80000000002 */ /*03d0*/ FFMA R2, R6, R7, R2 ; /* 0x0000000706027223 */ /* 0x000fe20000000002 */ /*03e0*/ MOV R4, UR4 ; /* 0x0000000400047c02 */ /* 0x000fe40008000f00 */ /*03f0*/ MOV R3, UR7 ; /* 0x0000000700037c02 */ /* 0x000fe20008000f00 */ /*0400*/ FFMA R18, R18, R23, R2 ; /* 0x0000001712127223 */ /* 0x000fe40000000002 */ /*0410*/ LDG.E R23, [R8.64+0x30] ; /* 0x0000300808177981 */ /* 0x0002e2000c1e1900 */ /*0420*/ MOV R2, UR6 ; /* 0x0000000600027c02 */ /* 0x000fe40008000f00 */ /*0430*/ MOV R5, UR5 ; /* 0x0000000500057c02 */ /* 0x000fc60008000f00 */ /*0440*/ IMAD.WIDE R6, R13, 0x4, R2 ; /* 0x000000040d067825 */ /* 0x000fc800078e0202 */ /*0450*/ IMAD.WIDE R4, R11, 0x4, R4 ; /* 0x000000040b047825 */ /* 0x000fc800078e0204 */ /*0460*/ IMAD.WIDE R2, R27, 0x4, R2 ; /* 0x000000041b027825 */ /* 0x000fe200078e0202 */ /*0470*/ LDG.E R9, [R4.64+0x300] ; /* 0x0003000804097981 */ /* 0x002ee8000c1e1900 */ /*0480*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040802087981 */ /* 0x000ee8000c1e1900 */ /*0490*/ LDG.E R27, [R4.64+0xc00] ; /* 0x000c0008041b7981 */ /* 0x000ee8000c1e1900 */ /*04a0*/ LDG.E R29, [R2.64+0xb0] ; /* 0x0000b008021d7981 */ /* 0x0010e2000c1e1900 */ /*04b0*/ FFMA R18, R10, R15, R18 ; /* 0x0000000f0a127223 */ /* 0x004fc60000000012 */ /*04c0*/ LDG.E R15, [R4.64] ; /* 0x00000008040f7981 */ /* 0x000ea8000c1e1900 */ /*04d0*/ LDG.E R10, [R6.64] ; /* 0x00000008060a7981 */ /* 0x000ea2000c1e1900 */ /*04e0*/ FFMA R18, R12, R17, R18 ; /* 0x000000110c127223 */ /* 0x010fc60000000012 */ /*04f0*/ LDG.E R12, [R4.64+0x100] ; /* 0x00010008040c7981 */ /* 0x000f28000c1e1900 */ /*0500*/ LDG.E R17, [R2.64] ; /* 0x0000000802117981 */ /* 0x000f22000c1e1900 */ /*0510*/ FFMA R18, R14, R19, R18 ; /* 0x000000130e127223 */ /* 0x020fc60000000012 */ /*0520*/ LDG.E R19, [R4.64+0x200] ; /* 0x0002000804137981 */ /* 0x000f68000c1e1900 */ /*0530*/ LDG.E R14, [R2.64+0x8] ; /* 0x00000808020e7981 */ /* 0x000f62000c1e1900 */ /*0540*/ FFMA R18, R16, R21, R18 ; /* 0x0000001510127223 */ /* 0x008fc60000000012 */ /*0550*/ LDG.E R16, [R4.64+0x400] ; /* 0x0004000804107981 */ /* 0x000ee8000c1e1900 */ /*0560*/ LDG.E R21, [R2.64+0xc] ; /* 0x00000c0802157981 */ /* 0x000ee2000c1e1900 */ /*0570*/ FFMA R18, R20, R23, R18 ; /* 0x0000001714127223 */ /* 0x000fc60000000012 */ /*0580*/ LDG.E R23, [R2.64+0x10] ; /* 0x0000100802177981 */ /* 0x000ee2000c1e1900 */ /*0590*/ FFMA R25, R22, R25, R18 ; /* 0x0000001916197223 */ /* 0x000fc60000000012 */ /*05a0*/ LDG.E R18, [R4.64+0x500] ; /* 0x0005000804127981 */ /* 0x000ee2000c1e1900 */ /*05b0*/ FFMA R24, R24, R26, R25 ; /* 0x0000001a18187223 */ /* 0x000fc60000000019 */ /*05c0*/ LDG.E R20, [R4.64+0x600] ; /* 0x0006000804147981 */ /* 0x000ee8000c1e1900 */ /*05d0*/ LDG.E R25, [R2.64+0x14] ; /* 0x0000140802197981 */ /* 0x000ee8000c1e1900 */ /*05e0*/ LDG.E R22, [R2.64+0x28] ; /* 0x0000280802167981 */ /* 0x000ee2000c1e1900 */ /*05f0*/ FFMA R24, R15, R10, R24 ; /* 0x0000000a0f187223 */ /* 0x004fc60000000018 */ /*0600*/ LDG.E R15, [R4.64+0x700] ; /* 0x00070008040f7981 */ /* 0x000ea8000c1e1900 */ /*0610*/ LDG.E R10, [R2.64+0x18] ; /* 0x00001808020a7981 */ /* 0x000ea2000c1e1900 */ /*0620*/ FFMA R24, R12, R17, R24 ; /* 0x000000110c187223 */ /* 0x010fc60000000018 */ /*0630*/ LDG.E R12, [R4.64+0x800] ; /* 0x00080008040c7981 */ /* 0x000f28000c1e1900 */ /*0640*/ LDG.E R17, [R2.64+0x1c] ; /* 0x00001c0802117981 */ /* 0x000f22000c1e1900 */ /*0650*/ FFMA R24, R19, R8, R24 ; /* 0x0000000813187223 */ /* 0x020fc60000000018 */ /*0660*/ LDG.E R19, [R4.64+0x900] ; /* 0x0009000804137981 */ /* 0x000f68000c1e1900 */ /*0670*/ LDG.E R8, [R2.64+0x20] ; /* 0x0000200802087981 */ /* 0x000f62000c1e1900 */ /*0680*/ FFMA R24, R9, R14, R24 ; /* 0x0000000e09187223 */ /* 0x000fc60000000018 */ /*0690*/ LDG.E R14, [R4.64+0xa00] ; /* 0x000a0008040e7981 */ /* 0x000f68000c1e1900 */ /*06a0*/ LDG.E R9, [R2.64+0x24] ; /* 0x0000240802097981 */ /* 0x000f62000c1e1900 */ /*06b0*/ FFMA R24, R16, R21, R24 ; /* 0x0000001510187223 */ /* 0x008fc60000000018 */ /*06c0*/ LDG.E R21, [R4.64+0xb00] ; /* 0x000b000804157981 */ /* 0x000ee8000c1e1900 */ /*06d0*/ LDG.E R16, [R2.64+0x2c] ; /* 0x00002c0802107981 */ /* 0x000ee2000c1e1900 */ /*06e0*/ FFMA R18, R18, R23, R24 ; /* 0x0000001712127223 */ /* 0x000fc60000000018 */ /*06f0*/ LDG.E R23, [R2.64+0x30] ; /* 0x0000300802177981 */ /* 0x000ee2000c1e1900 */ /*0700*/ FFMA R20, R20, R25, R18 ; /* 0x0000001914147223 */ /* 0x000fc60000000012 */ /*0710*/ LDG.E R18, [R4.64+0xd00] ; /* 0x000d000804127981 */ /* 0x000ee8000c1e1900 */ /*0720*/ LDG.E R25, [R2.64+0x48] ; /* 0x0000480802197981 */ /* 0x000ee2000c1e1900 */ /*0730*/ FFMA R20, R15, R10, R20 ; /* 0x0000000a0f147223 */ /* 0x004fc60000000014 */ /*0740*/ LDG.E R15, [R4.64+0xe00] ; /* 0x000e0008040f7981 */ /* 0x000ea8000c1e1900 */ /*0750*/ LDG.E R10, [R2.64+0x34] ; /* 0x00003408020a7981 */ /* 0x000ea2000c1e1900 */ /*0760*/ FFMA R20, R12, R17, R20 ; /* 0x000000110c147223 */ /* 0x010fc60000000014 */ /*0770*/ LDG.E R12, [R4.64+0xf00] ; /* 0x000f0008040c7981 */ /* 0x000f28000c1e1900 */ /*0780*/ LDG.E R17, [R2.64+0x38] ; /* 0x0000380802117981 */ /* 0x000f22000c1e1900 */ /*0790*/ FFMA R20, R19, R8, R20 ; /* 0x0000000813147223 */ /* 0x020fc60000000014 */ /*07a0*/ LDG.E R8, [R6.64+0x40] ; /* 0x0000400806087981 */ /* 0x000368000c1e1900 */ /*07b0*/ LDG.E R19, [R4.64+0x1000] ; /* 0x0010000804137981 */ /* 0x000f62000c1e1900 */ /*07c0*/ FFMA R20, R14, R9, R20 ; /* 0x000000090e147223 */ /* 0x000fc60000000014 */ /*07d0*/ LDG.E R14, [R4.64+0x1100] ; /* 0x00110008040e7981 */ /* 0x000f68000c1e1900 */ /*07e0*/ LDG.E R9, [R2.64+0x40] ; /* 0x0000400802097981 */ /* 0x000f62000c1e1900 */ /*07f0*/ FFMA R22, R21, R22, R20 ; /* 0x0000001615167223 */ /* 0x008fc60000000014 */ /*0800*/ LDG.E R20, [R4.64+0x1200] ; /* 0x0012000804147981 */ /* 0x000ee2000c1e1900 */ /*0810*/ FFMA R24, R27, R16, R22 ; /* 0x000000101b187223 */ /* 0x000fc60000000016 */ /*0820*/ LDG.E R21, [R2.64+0x44] ; /* 0x0000440802157981 */ /* 0x000ee8000c1e1900 */ /*0830*/ LDG.E R16, [R4.64+0x1300] ; /* 0x0013000804107981 */ /* 0x000ee8000c1e1900 */ /*0840*/ LDG.E R22, [R4.64+0x1400] ; /* 0x0014000804167981 */ /* 0x000ee8000c1e1900 */ /*0850*/ LDG.E R27, [R2.64+0x4c] ; /* 0x00004c08021b7981 */ /* 0x000ee8000c1e1900 */ /*0860*/ LDG.E R6, [R6.64+0x80] ; /* 0x0000800806067981 */ /* 0x0022e2000c1e1900 */ /*0870*/ FFMA R18, R18, R23, R24 ; /* 0x0000001712127223 */ /* 0x000fc60000000018 */ /*0880*/ LDG.E R23, [R4.64+0x1a00] ; /* 0x001a000804177981 */ /* 0x000ee8000c1e1900 */ /*0890*/ LDG.E R7, [R2.64+0x90] ; /* 0x0000900802077981 */ /* 0x002ee2000c1e1900 */ /*08a0*/ FFMA R18, R15, R10, R18 ; /* 0x0000000a0f127223 */ /* 0x004fc60000000012 */ /*08b0*/ LDG.E R15, [R4.64+0x1500] ; /* 0x00150008040f7981 */ /* 0x000ea8000c1e1900 */ /*08c0*/ LDG.E R10, [R2.64+0x50] ; /* 0x00005008020a7981 */ /* 0x000ea2000c1e1900 */ /*08d0*/ FFMA R18, R12, R17, R18 ; /* 0x000000110c127223 */ /* 0x010fc60000000012 */ /*08e0*/ LDG.E R12, [R4.64+0x1600] ; /* 0x00160008040c7981 */ /* 0x000f28000c1e1900 */ /*08f0*/ LDG.E R17, [R2.64+0x54] ; /* 0x0000540802117981 */ /* 0x000f22000c1e1900 */ /*0900*/ FFMA R18, R19, R8, R18 ; /* 0x0000000813127223 */ /* 0x020fc60000000012 */ /*0910*/ LDG.E R8, [R4.64+0x1700] ; /* 0x0017000804087981 */ /* 0x000f68000c1e1900 */ /*0920*/ LDG.E R19, [R2.64+0x58] ; /* 0x0000580802137981 */ /* 0x000f62000c1e1900 */ /*0930*/ FFMA R18, R14, R9, R18 ; /* 0x000000090e127223 */ /* 0x000fc60000000012 */ /*0940*/ LDG.E R14, [R4.64+0x1800] ; /* 0x00180008040e7981 */ /* 0x000f68000c1e1900 */ /*0950*/ LDG.E R9, [R2.64+0x5c] ; /* 0x00005c0802097981 */ /* 0x000f62000c1e1900 */ /*0960*/ FFMA R20, R20, R21, R18 ; /* 0x0000001514147223 */ /* 0x008fc60000000012 */ /*0970*/ LDG.E R21, [R4.64+0x1900] ; /* 0x0019000804157981 */ /* 0x000ee8000c1e1900 */ /*0980*/ LDG.E R18, [R2.64+0x60] ; /* 0x0000600802127981 */ /* 0x000ee2000c1e1900 */ /*0990*/ FFMA R20, R16, R25, R20 ; /* 0x0000001910147223 */ /* 0x000fc60000000014 */ /*09a0*/ LDG.E R16, [R2.64+0x64] ; /* 0x0000640802107981 */ /* 0x000ee2000c1e1900 */ /*09b0*/ FFMA R24, R22, R27, R20 ; /* 0x0000001b16187223 */ /* 0x000fc60000000014 */ /*09c0*/ LDG.E R22, [R4.64+0x1b00] ; /* 0x001b000804167981 */ /* 0x000ee8000c1e1900 */ /*09d0*/ LDG.E R27, [R2.64+0x68] ; /* 0x00006808021b7981 */ /* 0x000ee8000c1e1900 */ /*09e0*/ LDG.E R20, [R4.64+0x1c00] ; /* 0x001c000804147981 */ /* 0x000ee8000c1e1900 */ /*09f0*/ LDG.E R25, [R2.64+0x6c] ; /* 0x00006c0802197981 */ /* 0x000ee2000c1e1900 */ /*0a00*/ FFMA R10, R15, R10, R24 ; /* 0x0000000a0f0a7223 */ /* 0x004fc60000000018 */ /*0a10*/ LDG.E R15, [R4.64+0x1d00] ; /* 0x001d0008040f7981 */ /* 0x000ea2000c1e1900 */ /*0a20*/ FFMA R12, R12, R17, R10 ; /* 0x000000110c0c7223 */ /* 0x010fc6000000000a */ /*0a30*/ LDG.E R10, [R2.64+0x70] ; /* 0x00007008020a7981 */ /* 0x000ea8000c1e1900 */ /*0a40*/ LDG.E R17, [R2.64+0x74] ; /* 0x0000740802117981 */ /* 0x000f22000c1e1900 */ /*0a50*/ FFMA R12, R8, R19, R12 ; /* 0x00000013080c7223 */ /* 0x020fc6000000000c */ /*0a60*/ LDG.E R8, [R4.64+0x1e00] ; /* 0x001e000804087981 */ /* 0x000f28000c1e1900 */ /*0a70*/ LDG.E R19, [R4.64+0x2000] ; /* 0x0020000804137981 */ /* 0x000f62000c1e1900 */ /*0a80*/ FFMA R14, R14, R9, R12 ; /* 0x000000090e0e7223 */ /* 0x000fc6000000000c */ /*0a90*/ LDG.E R9, [R4.64+0x1f00] ; /* 0x001f000804097981 */ /* 0x000f68000c1e1900 */ /*0aa0*/ LDG.E R12, [R2.64+0x78] ; /* 0x00007808020c7981 */ /* 0x000f62000c1e1900 */ /*0ab0*/ FFMA R18, R21, R18, R14 ; /* 0x0000001215127223 */ /* 0x008fc6000000000e */ /*0ac0*/ LDG.E R21, [R4.64+0x2100] ; /* 0x0021000804157981 */ /* 0x000ee2000c1e1900 */ /*0ad0*/ FFMA R18, R23, R16, R18 ; /* 0x0000001017127223 */ /* 0x000fc60000000012 */ /*0ae0*/ LDG.E R14, [R2.64+0x80] ; /* 0x00008008020e7981 */ /* 0x000ee8000c1e1900 */ /*0af0*/ LDG.E R23, [R4.64+0x2200] ; /* 0x0022000804177981 */ /* 0x000ee2000c1e1900 */ /*0b00*/ FFMA R22, R22, R27, R18 ; /* 0x0000001b16167223 */ /* 0x000fc60000000012 */ /*0b10*/ LDG.E R16, [R2.64+0x84] ; /* 0x0000840802107981 */ /* 0x000ee8000c1e1900 */ /*0b20*/ LDG.E R27, [R4.64+0x2300] ; /* 0x00230008041b7981 */ /* 0x000ee8000c1e1900 */ /*0b30*/ LDG.E R18, [R2.64+0x88] ; /* 0x0000880802127981 */ /* 0x000ee2000c1e1900 */ /*0b40*/ FFMA R24, R20, R25, R22 ; /* 0x0000001914187223 */ /* 0x000fc60000000016 */ /*0b50*/ LDG.E R25, [R4.64+0x2400] ; /* 0x0024000804197981 */ /* 0x000ee8000c1e1900 */ /*0b60*/ LDG.E R22, [R2.64+0x8c] ; /* 0x00008c0802167981 */ /* 0x000ee8000c1e1900 */ /*0b70*/ LDG.E R20, [R4.64+0x2500] ; /* 0x0025000804147981 */ /* 0x000ee2000c1e1900 */ /*0b80*/ FFMA R10, R15, R10, R24 ; /* 0x0000000a0f0a7223 */ /* 0x004fc60000000018 */ /*0b90*/ LDG.E R15, [R4.64+0x2600] ; /* 0x00260008040f7981 */ /* 0x000ea8000c1e1900 */ /*0ba0*/ LDG.E R24, [R2.64+0xb8] ; /* 0x0000b80802187981 */ /* 0x0000a2000c1e1900 */ /*0bb0*/ FFMA R10, R8, R17, R10 ; /* 0x00000011080a7223 */ /* 0x010fc6000000000a */ /*0bc0*/ LDG.E R8, [R2.64+0x94] ; /* 0x0000940802087981 */ /* 0x0000a8000c1e1900 */ /*0bd0*/ LDG.E R17, [R2.64+0x9c] ; /* 0x00009c0802117981 */ /* 0x000122000c1e1900 */ /*0be0*/ FFMA R12, R9, R12, R10 ; /* 0x0000000c090c7223 */ /* 0x020fc6000000000a */ /*0bf0*/ LDG.E R9, [R4.64+0x2700] ; /* 0x0027000804097981 */ /* 0x000f62000c1e1900 */ /*0c00*/ FFMA R19, R19, R6, R12 ; /* 0x0000000613137223 */ /* 0x000fc6000000000c */ /*0c10*/ LDG.E R10, [R2.64+0x98] ; /* 0x00009808020a7981 */ /* 0x000162000c1e1900 */ /*0c20*/ FFMA R14, R21, R14, R19 ; /* 0x0000000e150e7223 */ /* 0x008fc60000000013 */ /*0c30*/ LDG.E R6, [R4.64+0x2800] ; /* 0x0028000804067981 */ /* 0x000f28000c1e1900 */ /*0c40*/ LDG.E R12, [R4.64+0x2900] ; /* 0x00290008040c7981 */ /* 0x000ee2000c1e1900 */ /*0c50*/ FFMA R16, R23, R16, R14 ; /* 0x0000001017107223 */ /* 0x000fc6000000000e */ /*0c60*/ LDG.E R19, [R2.64+0xa0] ; /* 0x0000a00802137981 */ /* 0x0000e8000c1e1900 */ /*0c70*/ LDG.E R14, [R4.64+0x2a00] ; /* 0x002a0008040e7981 */ /* 0x000ee2000c1e1900 */ /*0c80*/ FFMA R18, R27, R18, R16 ; /* 0x000000121b127223 */ /* 0x000fc60000000010 */ /*0c90*/ LDG.E R21, [R2.64+0xa4] ; /* 0x0000a40802157981 */ /* 0x0000e8000c1e1900 */ /*0ca0*/ LDG.E R16, [R4.64+0x2b00] ; /* 0x002b000804107981 */ /* 0x000ee2000c1e1900 */ /*0cb0*/ FFMA R22, R25, R22, R18 ; /* 0x0000001619167223 */ /* 0x000fc60000000012 */ /*0cc0*/ LDG.E R23, [R2.64+0xa8] ; /* 0x0000a80802177981 */ /* 0x0000e8000c1e1900 */ /*0cd0*/ LDG.E R18, [R4.64+0x2c00] ; /* 0x002c000804127981 */ /* 0x000ee2000c1e1900 */ /*0ce0*/ FFMA R26, R20, R7, R22 ; /* 0x00000007141a7223 */ /* 0x000fc60000000016 */ /*0cf0*/ LDG.E R25, [R2.64+0xac] ; /* 0x0000ac0802197981 */ /* 0x0000e8000c1e1900 */ /*0d00*/ LDG.E R22, [R4.64+0x2d00] ; /* 0x002d000804167981 */ /* 0x000ee8000c1e1900 */ /*0d10*/ LDG.E R20, [R4.64+0x2e00] ; /* 0x002e000804147981 */ /* 0x000ee8000c1e1900 */ /*0d20*/ LDG.E R27, [R2.64+0xb4] ; /* 0x0000b408021b7981 */ /* 0x0000e8000c1e1900 */ /*0d30*/ LDG.E R7, [R4.64+0x2f00] ; /* 0x002f000804077981 */ /* 0x000ee2000c1e1900 */ /*0d40*/ IADD3 R11, R11, R13, RZ ; /* 0x0000000d0b0b7210 */ /* 0x000fca0007ffe0ff */ /*0d50*/ IMAD.WIDE R2, R11, R0, c[0x0][0x170] ; /* 0x00005c000b027625 */ /* 0x001fc800078e0200 */ /*0d60*/ FFMA R8, R15, R8, R26 ; /* 0x000000080f087223 */ /* 0x004fc8000000001a */ /*0d70*/ FFMA R8, R9, R10, R8 ; /* 0x0000000a09087223 */ /* 0x020fc80000000008 */ /*0d80*/ FFMA R6, R6, R17, R8 ; /* 0x0000001106067223 */ /* 0x010fc80000000008 */ /*0d90*/ FFMA R6, R12, R19, R6 ; /* 0x000000130c067223 */ /* 0x008fc80000000006 */ /*0da0*/ FFMA R6, R14, R21, R6 ; /* 0x000000150e067223 */ /* 0x000fc80000000006 */ /*0db0*/ FFMA R6, R16, R23, R6 ; /* 0x0000001710067223 */ /* 0x000fc80000000006 */ /*0dc0*/ FFMA R6, R18, R25, R6 ; /* 0x0000001912067223 */ /* 0x000fc80000000006 */ /*0dd0*/ FFMA R6, R22, R29, R6 ; /* 0x0000001d16067223 */ /* 0x000fc80000000006 */ /*0de0*/ FFMA R6, R20, R27, R6 ; /* 0x0000001b14067223 */ /* 0x000fc80000000006 */ /*0df0*/ FFMA R7, R7, R24, R6 ; /* 0x0000001807077223 */ /* 0x000fca0000000006 */ /*0e00*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */ /* 0x000fe2000c101908 */ /*0e10*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0e20*/ BRA 0xe20; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0e30*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0e40*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0e50*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0e60*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0e70*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0e80*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0e90*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0ea0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0eb0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0ec0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0ed0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0ee0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0ef0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z9matrixMulPfS_S_ .globl _Z9matrixMulPfS_S_ .p2align 8 .type _Z9matrixMulPfS_S_,@function _Z9matrixMulPfS_S_: s_load_b32 s2, s[0:1], 0x24 v_bfe_u32 v2, v0, 10, 10 v_and_b32_e32 v3, 0x3ff, v0 s_waitcnt lgkmcnt(0) s_lshr_b32 s3, s2, 16 s_and_b32 s2, s2, 0xffff s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3] v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4] s_mov_b32 s2, exec_lo v_max_i32_e32 v2, v0, v1 s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_i32_e32 64, v2 s_cbranch_execz .LBB0_4 s_load_b128 s[4:7], s[0:1], 0x0 v_lshlrev_b32_e32 v2, 6, v0 v_mov_b32_e32 v4, 0 s_mov_b64 s[2:3], 0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v3, 31, v2 v_lshlrev_b64 v[2:3], 2, v[2:3] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v5, vcc_lo, s4, v2 v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo v_mov_b32_e32 v2, v1 .p2align 6 .LBB0_2: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) v_ashrrev_i32_e32 v3, 31, v2 v_add_co_u32 v7, vcc_lo, v5, s2 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e32 v8, vcc_lo, s3, v6, vcc_lo v_lshlrev_b64 v[9:10], 2, v[2:3] v_add_nc_u32_e32 v2, 64, v2 s_add_u32 s2, s2, 4 s_addc_u32 s3, s3, 0 s_cmpk_eq_i32 s2, 0x100 s_delay_alu instid0(VALU_DEP_2) v_add_co_u32 v9, vcc_lo, s6, v9 v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo global_load_b32 v3, v[7:8], off global_load_b32 v7, v[9:10], off s_waitcnt vmcnt(0) v_fmac_f32_e32 v4, v3, v7 s_cbranch_scc0 .LBB0_2 s_load_b64 s[0:1], s[0:1], 0x10 v_lshl_add_u32 v0, v0, 6, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v1, 31, v0 v_lshlrev_b64 v[0:1], 2, v[0:1] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_store_b32 v[0:1], v4, off .LBB0_4: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9matrixMulPfS_S_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 11 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z9matrixMulPfS_S_, .Lfunc_end0-_Z9matrixMulPfS_S_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9matrixMulPfS_S_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z9matrixMulPfS_S_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 11 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_001a2703_00000000-6_matrixmul_CPU.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2062: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2062: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z13matrixMul_CPUPfS_S_ .type _Z13matrixMul_CPUPfS_S_, @function _Z13matrixMul_CPUPfS_S_: .LFB2057: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movq %rdi, %rbx movq %rsi, %r11 movq %rdx, %r10 movl $0, %r9d .L4: leaq 16384(%r11), %rcx movq %r9, %rdi salq $8, %rdi leaq (%rbx,%rdi), %r8 addq %r10, %rdi movl $0, %esi .L8: leaq -16384(%rcx), %rax movq %r8, %rdx pxor %xmm1, %xmm1 .L5: movss (%rdx), %xmm0 mulss (%rax), %xmm0 addss %xmm0, %xmm1 addq $4, %rdx addq $256, %rax cmpq %rcx, %rax jne .L5 movss %xmm1, (%rdi,%rsi,4) addq $1, %rsi addq $4, %rcx cmpq $64, %rsi jne .L8 addq $1, %r9 cmpq $64, %r9 jne .L4 popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2057: .size _Z13matrixMul_CPUPfS_S_, .-_Z13matrixMul_CPUPfS_S_ .globl _Z12milisegundosv .type _Z12milisegundosv, @function _Z12milisegundosv: .LFB2058: .cfi_startproc endbr64 subq $40, %rsp .cfi_def_cfa_offset 48 movq %fs:40, %rax movq %rax, 24(%rsp) xorl %eax, %eax movq %rsp, %rdi movl $0, %esi call gettimeofday@PLT imulq $1000, (%rsp), %rsi movq 8(%rsp), %rcx movabsq $2361183241434822607, %rdx movq %rcx, %rax imulq %rdx sarq $7, %rdx sarq $63, %rcx subq %rcx, %rdx leaq (%rsi,%rdx), %rax movq 24(%rsp), %rdx subq %fs:40, %rdx jne .L14 addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L14: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2058: .size _Z12milisegundosv, .-_Z12milisegundosv .globl _Z32__device_stub__Z9matrixMulPfS_S_PfS_S_ .type _Z32__device_stub__Z9matrixMulPfS_S_PfS_S_, @function _Z32__device_stub__Z9matrixMulPfS_S_PfS_S_: .LFB2084: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L19 .L15: movq 120(%rsp), %rax subq %fs:40, %rax jne .L20 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L19: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z9matrixMulPfS_S_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L15 .L20: call __stack_chk_fail@PLT .cfi_endproc .LFE2084: .size _Z32__device_stub__Z9matrixMulPfS_S_PfS_S_, .-_Z32__device_stub__Z9matrixMulPfS_S_PfS_S_ .globl _Z9matrixMulPfS_S_ .type _Z9matrixMulPfS_S_, @function _Z9matrixMulPfS_S_: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z32__device_stub__Z9matrixMulPfS_S_PfS_S_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _Z9matrixMulPfS_S_, .-_Z9matrixMulPfS_S_ .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC2: .string "Tiempo invertido en multiplicar CPU: %f\n" .section .rodata.str1.1,"aMS",@progbits,1 .LC3: .string "------- CPU --------\n" .LC4: .string "Componente [%d] = %f\n" .section .rodata.str1.8 .align 8 .LC5: .string "Tiempo invertido en multiplicar GPU: %f\n" .section .rodata.str1.1 .LC6: .string "------- GPU --------\n" .text .globl main .type main, @function main: .LFB2059: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $88, %rsp .cfi_def_cfa_offset 144 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax movl $16384, %edi call malloc@PLT movq %rax, %r15 movl $16384, %edi call malloc@PLT movq %rax, %r12 movq %rax, 8(%rsp) movl $16384, %edi call malloc@PLT movq %rax, %r14 movq %r15, %rbp leaq 16384(%r15), %r13 .L24: movl $0, %ebx .L25: call rand@PLT pxor %xmm0, %xmm0 cvtsi2ssl %eax, %xmm0 mulss .LC1(%rip), %xmm0 movss %xmm0, 0(%rbp,%rbx) call rand@PLT pxor %xmm0, %xmm0 cvtsi2ssl %eax, %xmm0 mulss .LC1(%rip), %xmm0 movss %xmm0, (%r12,%rbx) addq $4, %rbx cmpq $256, %rbx jne .L25 addq $256, %rbp addq $256, %r12 cmpq %r13, %rbp jne .L24 call _Z12milisegundosv movq %rax, %rbx movq %r14, %rdx movq 8(%rsp), %rsi movq %r15, %rdi call _Z13matrixMul_CPUPfS_S_ call _Z12milisegundosv subq %rbx, %rax movq %rax, %rdx leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq .LC3(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $0, %ebx leaq .LC4(%rip), %rbp .L27: pxor %xmm0, %xmm0 cvtss2sd (%r14,%rbx,4), %xmm0 movl %ebx, %edx movq %rbp, %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT addq $1, %rbx cmpq $10, %rbx jne .L27 leaq 24(%rsp), %rdi movl $16384, %esi call cudaMalloc@PLT leaq 32(%rsp), %rdi movl $16384, %esi call cudaMalloc@PLT leaq 40(%rsp), %rdi movl $16384, %esi call cudaMalloc@PLT movl $1, %ecx movl $16384, %edx movq %r15, %rsi movq 24(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movl $16384, %edx movq 8(%rsp), %rsi movq 32(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movl $16384, %edx movq %r14, %rsi movq 40(%rsp), %rdi call cudaMemcpy@PLT movl $16, 48(%rsp) movl $16, 52(%rsp) movl $1, 56(%rsp) movl $64, 60(%rsp) movl $64, 64(%rsp) movl $1, 68(%rsp) call _Z12milisegundosv movq %rax, %rbx movl 56(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 48(%rsp), %rdx movq 60(%rsp), %rdi movl 68(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L35 .L28: movl $2, %ecx movl $16384, %edx movq 40(%rsp), %rsi movq %r14, %rdi call cudaMemcpy@PLT call _Z12milisegundosv subq %rbx, %rax movq %rax, %rdx leaq .LC5(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq .LC6(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $0, %ebx leaq .LC4(%rip), %rbp .L29: pxor %xmm0, %xmm0 cvtss2sd (%r14,%rbx,4), %xmm0 movl %ebx, %edx movq %rbp, %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT addq $1, %rbx cmpq $10, %rbx jne .L29 movq 24(%rsp), %rdi call cudaFree@PLT movq 32(%rsp), %rdi call cudaFree@PLT movq 40(%rsp), %rdi call cudaFree@PLT movq %r15, %rdi call free@PLT movq 8(%rsp), %rdi call free@PLT movq %r14, %rdi call free@PLT movq 72(%rsp), %rax subq %fs:40, %rax jne .L36 movl $0, %eax addq $88, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L35: .cfi_restore_state movq 40(%rsp), %rdx movq 32(%rsp), %rsi movq 24(%rsp), %rdi call _Z32__device_stub__Z9matrixMulPfS_S_PfS_S_ jmp .L28 .L36: call __stack_chk_fail@PLT .cfi_endproc .LFE2059: .size main, .-main .section .rodata.str1.1 .LC7: .string "_Z9matrixMulPfS_S_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2087: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC7(%rip), %rdx movq %rdx, %rcx leaq _Z9matrixMulPfS_S_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2087: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC1: .long 805306368 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "matrixmul_CPU.hip" .globl _Z24__device_stub__matrixMulPfS_S_ # -- Begin function _Z24__device_stub__matrixMulPfS_S_ .p2align 4, 0x90 .type _Z24__device_stub__matrixMulPfS_S_,@function _Z24__device_stub__matrixMulPfS_S_: # @_Z24__device_stub__matrixMulPfS_S_ .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z9matrixMulPfS_S_, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z24__device_stub__matrixMulPfS_S_, .Lfunc_end0-_Z24__device_stub__matrixMulPfS_S_ .cfi_endproc # -- End function .globl _Z13matrixMul_CPUPfS_S_ # -- Begin function _Z13matrixMul_CPUPfS_S_ .p2align 4, 0x90 .type _Z13matrixMul_CPUPfS_S_,@function _Z13matrixMul_CPUPfS_S_: # @_Z13matrixMul_CPUPfS_S_ .cfi_startproc # %bb.0: xorl %eax, %eax .p2align 4, 0x90 .LBB1_1: # %.preheader19 # =>This Loop Header: Depth=1 # Child Loop BB1_2 Depth 2 # Child Loop BB1_3 Depth 3 movq %rax, %rcx shlq $8, %rcx addq %rdx, %rcx movq %rsi, %r8 xorl %r9d, %r9d .p2align 4, 0x90 .LBB1_2: # %.preheader # Parent Loop BB1_1 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB1_3 Depth 3 xorps %xmm0, %xmm0 movq %r8, %r10 xorl %r11d, %r11d .p2align 4, 0x90 .LBB1_3: # Parent Loop BB1_1 Depth=1 # Parent Loop BB1_2 Depth=2 # => This Inner Loop Header: Depth=3 movss (%rdi,%r11,4), %xmm1 # xmm1 = mem[0],zero,zero,zero mulss (%r10), %xmm1 addss %xmm1, %xmm0 incq %r11 addq $256, %r10 # imm = 0x100 cmpq $64, %r11 jne .LBB1_3 # %bb.4: # in Loop: Header=BB1_2 Depth=2 movss %xmm0, (%rcx,%r9,4) incq %r9 addq $4, %r8 cmpq $64, %r9 jne .LBB1_2 # %bb.5: # in Loop: Header=BB1_1 Depth=1 incq %rax addq $256, %rdi # imm = 0x100 cmpq $64, %rax jne .LBB1_1 # %bb.6: retq .Lfunc_end1: .size _Z13matrixMul_CPUPfS_S_, .Lfunc_end1-_Z13matrixMul_CPUPfS_S_ .cfi_endproc # -- End function .globl _Z12milisegundosv # -- Begin function _Z12milisegundosv .p2align 4, 0x90 .type _Z12milisegundosv,@function _Z12milisegundosv: # @_Z12milisegundosv .cfi_startproc # %bb.0: subq $24, %rsp .cfi_def_cfa_offset 32 leaq 8(%rsp), %rdi xorl %esi, %esi callq gettimeofday imulq $1000, 8(%rsp), %rcx # imm = 0x3E8 movabsq $2361183241434822607, %rax # imm = 0x20C49BA5E353F7CF imulq 16(%rsp) movq %rdx, %rax shrq $63, %rax sarq $7, %rdx addq %rdx, %rax addq %rcx, %rax addq $24, %rsp .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size _Z12milisegundosv, .Lfunc_end2-_Z12milisegundosv .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI3_0: .long 0x30000000 # float 4.65661287E-10 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $136, %rsp .cfi_def_cfa_offset 192 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $16384, %edi # imm = 0x4000 callq malloc movq %rax, %r13 movl $16384, %edi # imm = 0x4000 callq malloc movq %rax, %r14 movl $16384, %edi # imm = 0x4000 callq malloc movq %rax, %r15 xorl %r12d, %r12d movq %r13, 40(%rsp) # 8-byte Spill movq %r14, %rbp .p2align 4, 0x90 .LBB3_1: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB3_2 Depth 2 xorl %ebx, %ebx .p2align 4, 0x90 .LBB3_2: # Parent Loop BB3_1 Depth=1 # => This Inner Loop Header: Depth=2 callq rand xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 mulss .LCPI3_0(%rip), %xmm0 movss %xmm0, (%r13,%rbx,4) callq rand movss .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 mulss %xmm1, %xmm0 movss %xmm0, (%rbp,%rbx,4) incq %rbx cmpq $64, %rbx jne .LBB3_2 # %bb.3: # in Loop: Header=BB3_1 Depth=1 incq %r12 addq $256, %rbp # imm = 0x100 addq $256, %r13 # imm = 0x100 cmpq $64, %r12 jne .LBB3_1 # %bb.4: xorl %r12d, %r12d movq %rsp, %rdi xorl %esi, %esi callq gettimeofday movq (%rsp), %r13 movq 8(%rsp), %rax movq 40(%rsp), %rcx # 8-byte Reload .p2align 4, 0x90 .LBB3_5: # %.preheader19.i # =>This Loop Header: Depth=1 # Child Loop BB3_6 Depth 2 # Child Loop BB3_7 Depth 3 movq %r12, %rdx shlq $8, %rdx addq %r15, %rdx movq %r14, %rsi xorl %edi, %edi .p2align 4, 0x90 .LBB3_6: # %.preheader.i # Parent Loop BB3_5 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB3_7 Depth 3 xorps %xmm0, %xmm0 movq %rsi, %r8 xorl %r9d, %r9d .p2align 4, 0x90 .LBB3_7: # Parent Loop BB3_5 Depth=1 # Parent Loop BB3_6 Depth=2 # => This Inner Loop Header: Depth=3 movss (%rcx,%r9,4), %xmm1 # xmm1 = mem[0],zero,zero,zero mulss (%r8), %xmm1 addss %xmm1, %xmm0 incq %r9 addq $256, %r8 # imm = 0x100 cmpq $64, %r9 jne .LBB3_7 # %bb.8: # in Loop: Header=BB3_6 Depth=2 movss %xmm0, (%rdx,%rdi,4) incq %rdi addq $4, %rsi cmpq $64, %rdi jne .LBB3_6 # %bb.9: # in Loop: Header=BB3_5 Depth=1 incq %r12 addq $256, %rcx # imm = 0x100 cmpq $64, %r12 jne .LBB3_5 # %bb.10: # %_Z13matrixMul_CPUPfS_S_.exit movabsq $-2361183241434822607, %rcx # imm = 0xDF3B645A1CAC0831 imulq %rcx movq %rdx, %rbx shrq $63, %rbx sarq $7, %rdx addq %rdx, %rbx xorl %r12d, %r12d movq %rsp, %rdi xorl %esi, %esi callq gettimeofday movq (%rsp), %rcx subq %r13, %rcx movabsq $2361183241434822607, %rax # imm = 0x20C49BA5E353F7CF imulq 8(%rsp) movq %rdx, %rax shrq $63, %rax sarq $7, %rdx addq %rdx, %rax addq %rbx, %rax imulq $1000, %rcx, %rsi # imm = 0x3E8 addq %rax, %rsi movl $.L.str, %edi xorl %eax, %eax callq printf movl $.Lstr, %edi callq puts@PLT .p2align 4, 0x90 .LBB3_11: # =>This Inner Loop Header: Depth=1 movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str.2, %edi movl %r12d, %esi movb $1, %al callq printf incq %r12 cmpq $10, %r12 jne .LBB3_11 # %bb.12: leaq 56(%rsp), %rdi movl $16384, %esi # imm = 0x4000 callq hipMalloc leaq 48(%rsp), %rdi movl $16384, %esi # imm = 0x4000 callq hipMalloc leaq 32(%rsp), %rdi movl $16384, %esi # imm = 0x4000 callq hipMalloc movq 56(%rsp), %rdi movl $16384, %edx # imm = 0x4000 movq 40(%rsp), %rsi # 8-byte Reload movl $1, %ecx callq hipMemcpy movq 48(%rsp), %rdi movl $16384, %edx # imm = 0x4000 movq %r14, %rsi movl $1, %ecx callq hipMemcpy movq 32(%rsp), %rdi movl $16384, %edx # imm = 0x4000 movq %r15, %rsi movl $1, %ecx callq hipMemcpy movq %rsp, %rdi xorl %esi, %esi callq gettimeofday movq (%rsp), %rbp movabsq $-2361183241434822607, %rax # imm = 0xDF3B645A1CAC0831 imulq 8(%rsp) movq %rdx, %r12 movq %rdx, %rax shrq $63, %rax sarq $7, %r12 addq %rax, %r12 movabsq $274877907008, %rdi # imm = 0x4000000040 movabsq $68719476752, %rdx # imm = 0x1000000010 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_14 # %bb.13: movq 56(%rsp), %rax movq 48(%rsp), %rcx movq 32(%rsp), %rdx movq %rax, 128(%rsp) movq %rcx, 120(%rsp) movq %rdx, 112(%rsp) leaq 128(%rsp), %rax movq %rax, (%rsp) leaq 120(%rsp), %rax movq %rax, 8(%rsp) leaq 112(%rsp), %rax movq %rax, 16(%rsp) leaq 96(%rsp), %rdi leaq 80(%rsp), %rsi leaq 72(%rsp), %rdx leaq 64(%rsp), %rcx callq __hipPopCallConfiguration movq 96(%rsp), %rsi movl 104(%rsp), %edx movq 80(%rsp), %rcx movl 88(%rsp), %r8d movq %rsp, %r9 movl $_Z9matrixMulPfS_S_, %edi pushq 64(%rsp) .cfi_adjust_cfa_offset 8 pushq 80(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB3_14: movq 32(%rsp), %rsi movl $16384, %edx # imm = 0x4000 movq %r15, %rdi movl $2, %ecx callq hipMemcpy xorl %r13d, %r13d movq %rsp, %rdi xorl %esi, %esi callq gettimeofday movq (%rsp), %rcx subq %rbp, %rcx movabsq $2361183241434822607, %rax # imm = 0x20C49BA5E353F7CF imulq 8(%rsp) movq %rdx, %rax shrq $63, %rax sarq $7, %rdx addq %rdx, %rax addq %r12, %rax imulq $1000, %rcx, %rsi # imm = 0x3E8 addq %rax, %rsi movl $.L.str.3, %edi xorl %eax, %eax callq printf movl $.Lstr.1, %edi callq puts@PLT .p2align 4, 0x90 .LBB3_15: # =>This Inner Loop Header: Depth=1 movss (%r15,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str.2, %edi movl %r13d, %esi movb $1, %al callq printf incq %r13 cmpq $10, %r13 jne .LBB3_15 # %bb.16: movq 56(%rsp), %rdi callq hipFree movq 48(%rsp), %rdi callq hipFree movq 32(%rsp), %rdi callq hipFree movq 40(%rsp), %rdi # 8-byte Reload callq free movq %r14, %rdi callq free movq %r15, %rdi callq free xorl %eax, %eax addq $136, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end3: .size main, .Lfunc_end3-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB4_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB4_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9matrixMulPfS_S_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end4: .size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB5_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB5_2: retq .Lfunc_end5: .size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor .cfi_endproc # -- End function .type _Z9matrixMulPfS_S_,@object # @_Z9matrixMulPfS_S_ .section .rodata,"a",@progbits .globl _Z9matrixMulPfS_S_ .p2align 3, 0x0 _Z9matrixMulPfS_S_: .quad _Z24__device_stub__matrixMulPfS_S_ .size _Z9matrixMulPfS_S_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Tiempo invertido en multiplicar CPU: %f\n" .size .L.str, 41 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Componente [%d] = %f\n" .size .L.str.2, 22 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Tiempo invertido en multiplicar GPU: %f\n" .size .L.str.3, 41 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z9matrixMulPfS_S_" .size .L__unnamed_1, 19 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "------- CPU --------" .size .Lstr, 21 .type .Lstr.1,@object # @str.1 .Lstr.1: .asciz "------- GPU --------" .size .Lstr.1, 21 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z24__device_stub__matrixMulPfS_S_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z9matrixMulPfS_S_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include "includes.h" __global__ void PrepareDerivativesKernel(float* input, float* lastInput, float* derivatives, int inputWidth, int inputHeight) { int id = blockDim.x * blockIdx.y * gridDim.x + blockDim.x * blockIdx.x + threadIdx.x; int size = inputWidth * inputHeight; if (id < size) { float mul = 100000; //I_x, I_y float I_x = mul * derivatives[id]; float I_y = mul * derivatives[size + id]; //I_t float input_dt = mul * (input[id] - lastInput[id]); lastInput[id] = input[id]; // I_x * I_y derivatives[2 * size + id] = I_x * I_y; // I_x * I_t derivatives[3 * size + id] = I_x * input_dt; // I_x * I_t derivatives[4 * size + id] = I_y * input_dt; // I_x ^ 2 derivatives[id] = I_x * I_x; // I_y ^ 2 derivatives[size + id] = I_y * I_y; } }
code for sm_80 Function : _Z24PrepareDerivativesKernelPfS_S_ii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */ /* 0x000e220000002600 */ /*0020*/ MOV R15, c[0x0][0x17c] ; /* 0x00005f00000f7a02 */ /* 0x000fc60000000f00 */ /*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */ /* 0x000e240000002500 */ /*0040*/ IMAD R15, R15, c[0x0][0x178], RZ ; /* 0x00005e000f0f7a24 */ /* 0x000fe400078e02ff */ /*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */ /* 0x000e620000002100 */ /*0060*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */ /* 0x001fc800078e0203 */ /*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */ /* 0x002fca00078e0205 */ /*0080*/ ISETP.GE.AND P0, PT, R0, R15, PT ; /* 0x0000000f0000720c */ /* 0x000fda0003f06270 */ /*0090*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*00a0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */ /* 0x000fe200000001ff */ /*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd20000000a00 */ /*00c0*/ IMAD.WIDE R4, R0, R9, c[0x0][0x170] ; /* 0x00005c0000047625 */ /* 0x000fc800078e0209 */ /*00d0*/ IMAD.WIDE R12, R0.reuse, R9.reuse, c[0x0][0x160] ; /* 0x00005800000c7625 */ /* 0x0c0fe200078e0209 */ /*00e0*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */ /* 0x000ea6000c1e1900 */ /*00f0*/ IMAD.WIDE R6, R0, R9, c[0x0][0x168] ; /* 0x00005a0000067625 */ /* 0x000fe200078e0209 */ /*0100*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */ /* 0x0000e6000c1e1900 */ /*0110*/ IMAD.WIDE R2, R15.reuse, 0x4, R4 ; /* 0x000000040f027825 */ /* 0x040fe200078e0204 */ /*0120*/ LDG.E R17, [R6.64] ; /* 0x0000000406117981 */ /* 0x000ee8000c1e1900 */ /*0130*/ LDG.E R16, [R2.64] ; /* 0x0000000402107981 */ /* 0x000f22000c1e1900 */ /*0140*/ IADD3 R8, R15, R15, R0 ; /* 0x0000000f0f087210 */ /* 0x000fca0007ffe000 */ /*0150*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */ /* 0x000fcc00078e0209 */ /*0160*/ IMAD.WIDE R10, R15, 0x4, R8 ; /* 0x000000040f0a7825 */ /* 0x000fcc00078e0208 */ /*0170*/ IMAD.WIDE R12, R15, 0x4, R10 ; /* 0x000000040f0c7825 */ /* 0x001fc800078e020a */ /*0180*/ FMUL R14, R14, 100000 ; /* 0x47c350000e0e7820 */ /* 0x004fe40000400000 */ /*0190*/ FADD R0, -R17, R18 ; /* 0x0000001211007221 */ /* 0x008fe40000000100 */ /*01a0*/ FMUL R17, R16, 100000 ; /* 0x47c3500010117820 */ /* 0x010fe40000400000 */ /*01b0*/ FMUL R0, R0, 100000 ; /* 0x47c3500000007820 */ /* 0x000fe40000400000 */ /*01c0*/ FMUL R15, R14.reuse, R17 ; /* 0x000000110e0f7220 */ /* 0x040fe40000400000 */ /*01d0*/ FMUL R19, R14, R0 ; /* 0x000000000e137220 */ /* 0x000fc40000400000 */ /*01e0*/ FMUL R21, R17.reuse, R0 ; /* 0x0000000011157220 */ /* 0x040fe20000400000 */ /*01f0*/ STG.E [R6.64], R18 ; /* 0x0000001206007986 */ /* 0x000fe2000c101904 */ /*0200*/ FMUL R23, R14, R14 ; /* 0x0000000e0e177220 */ /* 0x000fe40000400000 */ /*0210*/ FMUL R17, R17, R17 ; /* 0x0000001111117220 */ /* 0x000fe20000400000 */ /*0220*/ STG.E [R8.64], R15 ; /* 0x0000000f08007986 */ /* 0x000fe8000c101904 */ /*0230*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */ /* 0x000fe8000c101904 */ /*0240*/ STG.E [R12.64], R21 ; /* 0x000000150c007986 */ /* 0x000fe8000c101904 */ /*0250*/ STG.E [R4.64], R23 ; /* 0x0000001704007986 */ /* 0x000fe8000c101904 */ /*0260*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */ /* 0x000fe2000c101904 */ /*0270*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0280*/ BRA 0x280; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0290*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0300*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0310*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0320*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0330*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0340*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0350*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0360*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0370*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include "includes.h" __global__ void PrepareDerivativesKernel(float* input, float* lastInput, float* derivatives, int inputWidth, int inputHeight) { int id = blockDim.x * blockIdx.y * gridDim.x + blockDim.x * blockIdx.x + threadIdx.x; int size = inputWidth * inputHeight; if (id < size) { float mul = 100000; //I_x, I_y float I_x = mul * derivatives[id]; float I_y = mul * derivatives[size + id]; //I_t float input_dt = mul * (input[id] - lastInput[id]); lastInput[id] = input[id]; // I_x * I_y derivatives[2 * size + id] = I_x * I_y; // I_x * I_t derivatives[3 * size + id] = I_x * input_dt; // I_x * I_t derivatives[4 * size + id] = I_y * input_dt; // I_x ^ 2 derivatives[id] = I_x * I_x; // I_y ^ 2 derivatives[size + id] = I_y * I_y; } }
.file "tmpxft_000f89b7_00000000-6_PrepareDerivativesKernel.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z50__device_stub__Z24PrepareDerivativesKernelPfS_S_iiPfS_S_ii .type _Z50__device_stub__Z24PrepareDerivativesKernelPfS_S_iiPfS_S_ii, @function _Z50__device_stub__Z24PrepareDerivativesKernelPfS_S_iiPfS_S_ii: .LFB2051: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movl %r8d, (%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movq %rsp, %rax movq %rax, 128(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z24PrepareDerivativesKernelPfS_S_ii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z50__device_stub__Z24PrepareDerivativesKernelPfS_S_iiPfS_S_ii, .-_Z50__device_stub__Z24PrepareDerivativesKernelPfS_S_iiPfS_S_ii .globl _Z24PrepareDerivativesKernelPfS_S_ii .type _Z24PrepareDerivativesKernelPfS_S_ii, @function _Z24PrepareDerivativesKernelPfS_S_ii: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z50__device_stub__Z24PrepareDerivativesKernelPfS_S_iiPfS_S_ii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z24PrepareDerivativesKernelPfS_S_ii, .-_Z24PrepareDerivativesKernelPfS_S_ii .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "_Z24PrepareDerivativesKernelPfS_S_ii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z24PrepareDerivativesKernelPfS_S_ii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include "includes.h" __global__ void PrepareDerivativesKernel(float* input, float* lastInput, float* derivatives, int inputWidth, int inputHeight) { int id = blockDim.x * blockIdx.y * gridDim.x + blockDim.x * blockIdx.x + threadIdx.x; int size = inputWidth * inputHeight; if (id < size) { float mul = 100000; //I_x, I_y float I_x = mul * derivatives[id]; float I_y = mul * derivatives[size + id]; //I_t float input_dt = mul * (input[id] - lastInput[id]); lastInput[id] = input[id]; // I_x * I_y derivatives[2 * size + id] = I_x * I_y; // I_x * I_t derivatives[3 * size + id] = I_x * input_dt; // I_x * I_t derivatives[4 * size + id] = I_y * input_dt; // I_x ^ 2 derivatives[id] = I_x * I_x; // I_y ^ 2 derivatives[size + id] = I_y * I_y; } }
#include <hip/hip_runtime.h> #include "includes.h" __global__ void PrepareDerivativesKernel(float* input, float* lastInput, float* derivatives, int inputWidth, int inputHeight) { int id = blockDim.x * blockIdx.y * gridDim.x + blockDim.x * blockIdx.x + threadIdx.x; int size = inputWidth * inputHeight; if (id < size) { float mul = 100000; //I_x, I_y float I_x = mul * derivatives[id]; float I_y = mul * derivatives[size + id]; //I_t float input_dt = mul * (input[id] - lastInput[id]); lastInput[id] = input[id]; // I_x * I_y derivatives[2 * size + id] = I_x * I_y; // I_x * I_t derivatives[3 * size + id] = I_x * input_dt; // I_x * I_t derivatives[4 * size + id] = I_y * input_dt; // I_x ^ 2 derivatives[id] = I_x * I_x; // I_y ^ 2 derivatives[size + id] = I_y * I_y; } }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void PrepareDerivativesKernel(float* input, float* lastInput, float* derivatives, int inputWidth, int inputHeight) { int id = blockDim.x * blockIdx.y * gridDim.x + blockDim.x * blockIdx.x + threadIdx.x; int size = inputWidth * inputHeight; if (id < size) { float mul = 100000; //I_x, I_y float I_x = mul * derivatives[id]; float I_y = mul * derivatives[size + id]; //I_t float input_dt = mul * (input[id] - lastInput[id]); lastInput[id] = input[id]; // I_x * I_y derivatives[2 * size + id] = I_x * I_y; // I_x * I_t derivatives[3 * size + id] = I_x * input_dt; // I_x * I_t derivatives[4 * size + id] = I_y * input_dt; // I_x ^ 2 derivatives[id] = I_x * I_x; // I_y ^ 2 derivatives[size + id] = I_y * I_y; } }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z24PrepareDerivativesKernelPfS_S_ii .globl _Z24PrepareDerivativesKernelPfS_S_ii .p2align 8 .type _Z24PrepareDerivativesKernelPfS_S_ii,@function _Z24PrepareDerivativesKernelPfS_S_ii: s_clause 0x2 s_load_b32 s4, s[0:1], 0x20 s_load_b32 s5, s[0:1], 0x2c s_load_b64 s[2:3], s[0:1], 0x18 s_waitcnt lgkmcnt(0) s_mul_i32 s4, s4, s15 s_and_b32 s5, s5, 0xffff s_add_i32 s4, s4, s14 s_mul_i32 s2, s3, s2 v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1] s_mov_b32 s3, exec_lo s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_i32_e64 s2, v1 s_cbranch_execz .LBB0_2 s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[0:1], s[0:1], 0x10 v_ashrrev_i32_e32 v2, 31, v1 v_add_nc_u32_e32 v3, s2, v1 v_lshl_add_u32 v0, s2, 1, v1 v_lshl_add_u32 v11, s2, 2, v1 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_lshlrev_b64 v[5:6], 2, v[1:2] v_ashrrev_i32_e32 v4, 31, v3 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v12, 31, v11 v_lshlrev_b64 v[2:3], 2, v[3:4] s_delay_alu instid0(VALU_DEP_2) v_lshlrev_b64 v[11:12], 2, v[11:12] s_waitcnt lgkmcnt(0) v_add_co_u32 v7, vcc_lo, s4, v5 v_add_co_ci_u32_e32 v8, vcc_lo, s5, v6, vcc_lo v_add_co_u32 v9, vcc_lo, s6, v5 v_add_co_ci_u32_e32 v10, vcc_lo, s7, v6, vcc_lo v_add_co_u32 v4, vcc_lo, s0, v5 v_add_co_ci_u32_e32 v5, vcc_lo, s1, v6, vcc_lo v_add_co_u32 v2, vcc_lo, s0, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo global_load_b32 v8, v[7:8], off global_load_b32 v13, v[9:10], off s_clause 0x1 global_load_b32 v14, v[4:5], off global_load_b32 v15, v[2:3], off v_mad_u64_u32 v[6:7], null, s2, 3, v[1:2] v_ashrrev_i32_e32 v1, 31, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_lshlrev_b64 v[0:1], 2, v[0:1] v_ashrrev_i32_e32 v7, 31, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_lshlrev_b64 v[6:7], 2, v[6:7] v_add_co_u32 v0, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_4) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo v_add_co_u32 v11, vcc_lo, s0, v11 v_add_co_ci_u32_e32 v12, vcc_lo, s1, v12, vcc_lo v_add_co_u32 v6, vcc_lo, s0, v6 v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo s_waitcnt vmcnt(3) global_store_b32 v[9:10], v8, off s_waitcnt vmcnt(0) v_dual_mul_f32 v14, 0x47c35000, v14 :: v_dual_mul_f32 v15, 0x47c35000, v15 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_sub_f32 v13, v8, v13 :: v_dual_mul_f32 v8, v14, v15 v_mul_f32_e32 v13, 0x47c35000, v13 s_delay_alu instid0(VALU_DEP_1) v_mul_f32_e32 v9, v14, v13 v_dual_mul_f32 v10, v15, v13 :: v_dual_mul_f32 v13, v14, v14 v_mul_f32_e32 v14, v15, v15 s_clause 0x4 global_store_b32 v[0:1], v8, off global_store_b32 v[6:7], v9, off global_store_b32 v[11:12], v10, off global_store_b32 v[4:5], v13, off global_store_b32 v[2:3], v14, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z24PrepareDerivativesKernelPfS_S_ii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 16 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z24PrepareDerivativesKernelPfS_S_ii, .Lfunc_end0-_Z24PrepareDerivativesKernelPfS_S_ii .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z24PrepareDerivativesKernelPfS_S_ii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z24PrepareDerivativesKernelPfS_S_ii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 16 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void PrepareDerivativesKernel(float* input, float* lastInput, float* derivatives, int inputWidth, int inputHeight) { int id = blockDim.x * blockIdx.y * gridDim.x + blockDim.x * blockIdx.x + threadIdx.x; int size = inputWidth * inputHeight; if (id < size) { float mul = 100000; //I_x, I_y float I_x = mul * derivatives[id]; float I_y = mul * derivatives[size + id]; //I_t float input_dt = mul * (input[id] - lastInput[id]); lastInput[id] = input[id]; // I_x * I_y derivatives[2 * size + id] = I_x * I_y; // I_x * I_t derivatives[3 * size + id] = I_x * input_dt; // I_x * I_t derivatives[4 * size + id] = I_y * input_dt; // I_x ^ 2 derivatives[id] = I_x * I_x; // I_y ^ 2 derivatives[size + id] = I_y * I_y; } }
.text .file "PrepareDerivativesKernel.hip" .globl _Z39__device_stub__PrepareDerivativesKernelPfS_S_ii # -- Begin function _Z39__device_stub__PrepareDerivativesKernelPfS_S_ii .p2align 4, 0x90 .type _Z39__device_stub__PrepareDerivativesKernelPfS_S_ii,@function _Z39__device_stub__PrepareDerivativesKernelPfS_S_ii: # @_Z39__device_stub__PrepareDerivativesKernelPfS_S_ii .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) movl %r8d, (%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) movq %rsp, %rax movq %rax, 112(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z24PrepareDerivativesKernelPfS_S_ii, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z39__device_stub__PrepareDerivativesKernelPfS_S_ii, .Lfunc_end0-_Z39__device_stub__PrepareDerivativesKernelPfS_S_ii .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z24PrepareDerivativesKernelPfS_S_ii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z24PrepareDerivativesKernelPfS_S_ii,@object # @_Z24PrepareDerivativesKernelPfS_S_ii .section .rodata,"a",@progbits .globl _Z24PrepareDerivativesKernelPfS_S_ii .p2align 3, 0x0 _Z24PrepareDerivativesKernelPfS_S_ii: .quad _Z39__device_stub__PrepareDerivativesKernelPfS_S_ii .size _Z24PrepareDerivativesKernelPfS_S_ii, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z24PrepareDerivativesKernelPfS_S_ii" .size .L__unnamed_1, 37 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z39__device_stub__PrepareDerivativesKernelPfS_S_ii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z24PrepareDerivativesKernelPfS_S_ii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z24PrepareDerivativesKernelPfS_S_ii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */ /* 0x000e220000002600 */ /*0020*/ MOV R15, c[0x0][0x17c] ; /* 0x00005f00000f7a02 */ /* 0x000fc60000000f00 */ /*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */ /* 0x000e240000002500 */ /*0040*/ IMAD R15, R15, c[0x0][0x178], RZ ; /* 0x00005e000f0f7a24 */ /* 0x000fe400078e02ff */ /*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */ /* 0x000e620000002100 */ /*0060*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */ /* 0x001fc800078e0203 */ /*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */ /* 0x002fca00078e0205 */ /*0080*/ ISETP.GE.AND P0, PT, R0, R15, PT ; /* 0x0000000f0000720c */ /* 0x000fda0003f06270 */ /*0090*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*00a0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */ /* 0x000fe200000001ff */ /*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd20000000a00 */ /*00c0*/ IMAD.WIDE R4, R0, R9, c[0x0][0x170] ; /* 0x00005c0000047625 */ /* 0x000fc800078e0209 */ /*00d0*/ IMAD.WIDE R12, R0.reuse, R9.reuse, c[0x0][0x160] ; /* 0x00005800000c7625 */ /* 0x0c0fe200078e0209 */ /*00e0*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */ /* 0x000ea6000c1e1900 */ /*00f0*/ IMAD.WIDE R6, R0, R9, c[0x0][0x168] ; /* 0x00005a0000067625 */ /* 0x000fe200078e0209 */ /*0100*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */ /* 0x0000e6000c1e1900 */ /*0110*/ IMAD.WIDE R2, R15.reuse, 0x4, R4 ; /* 0x000000040f027825 */ /* 0x040fe200078e0204 */ /*0120*/ LDG.E R17, [R6.64] ; /* 0x0000000406117981 */ /* 0x000ee8000c1e1900 */ /*0130*/ LDG.E R16, [R2.64] ; /* 0x0000000402107981 */ /* 0x000f22000c1e1900 */ /*0140*/ IADD3 R8, R15, R15, R0 ; /* 0x0000000f0f087210 */ /* 0x000fca0007ffe000 */ /*0150*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */ /* 0x000fcc00078e0209 */ /*0160*/ IMAD.WIDE R10, R15, 0x4, R8 ; /* 0x000000040f0a7825 */ /* 0x000fcc00078e0208 */ /*0170*/ IMAD.WIDE R12, R15, 0x4, R10 ; /* 0x000000040f0c7825 */ /* 0x001fc800078e020a */ /*0180*/ FMUL R14, R14, 100000 ; /* 0x47c350000e0e7820 */ /* 0x004fe40000400000 */ /*0190*/ FADD R0, -R17, R18 ; /* 0x0000001211007221 */ /* 0x008fe40000000100 */ /*01a0*/ FMUL R17, R16, 100000 ; /* 0x47c3500010117820 */ /* 0x010fe40000400000 */ /*01b0*/ FMUL R0, R0, 100000 ; /* 0x47c3500000007820 */ /* 0x000fe40000400000 */ /*01c0*/ FMUL R15, R14.reuse, R17 ; /* 0x000000110e0f7220 */ /* 0x040fe40000400000 */ /*01d0*/ FMUL R19, R14, R0 ; /* 0x000000000e137220 */ /* 0x000fc40000400000 */ /*01e0*/ FMUL R21, R17.reuse, R0 ; /* 0x0000000011157220 */ /* 0x040fe20000400000 */ /*01f0*/ STG.E [R6.64], R18 ; /* 0x0000001206007986 */ /* 0x000fe2000c101904 */ /*0200*/ FMUL R23, R14, R14 ; /* 0x0000000e0e177220 */ /* 0x000fe40000400000 */ /*0210*/ FMUL R17, R17, R17 ; /* 0x0000001111117220 */ /* 0x000fe20000400000 */ /*0220*/ STG.E [R8.64], R15 ; /* 0x0000000f08007986 */ /* 0x000fe8000c101904 */ /*0230*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */ /* 0x000fe8000c101904 */ /*0240*/ STG.E [R12.64], R21 ; /* 0x000000150c007986 */ /* 0x000fe8000c101904 */ /*0250*/ STG.E [R4.64], R23 ; /* 0x0000001704007986 */ /* 0x000fe8000c101904 */ /*0260*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */ /* 0x000fe2000c101904 */ /*0270*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0280*/ BRA 0x280; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0290*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0300*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0310*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0320*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0330*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0340*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0350*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0360*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0370*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z24PrepareDerivativesKernelPfS_S_ii .globl _Z24PrepareDerivativesKernelPfS_S_ii .p2align 8 .type _Z24PrepareDerivativesKernelPfS_S_ii,@function _Z24PrepareDerivativesKernelPfS_S_ii: s_clause 0x2 s_load_b32 s4, s[0:1], 0x20 s_load_b32 s5, s[0:1], 0x2c s_load_b64 s[2:3], s[0:1], 0x18 s_waitcnt lgkmcnt(0) s_mul_i32 s4, s4, s15 s_and_b32 s5, s5, 0xffff s_add_i32 s4, s4, s14 s_mul_i32 s2, s3, s2 v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1] s_mov_b32 s3, exec_lo s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_i32_e64 s2, v1 s_cbranch_execz .LBB0_2 s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[0:1], s[0:1], 0x10 v_ashrrev_i32_e32 v2, 31, v1 v_add_nc_u32_e32 v3, s2, v1 v_lshl_add_u32 v0, s2, 1, v1 v_lshl_add_u32 v11, s2, 2, v1 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_lshlrev_b64 v[5:6], 2, v[1:2] v_ashrrev_i32_e32 v4, 31, v3 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v12, 31, v11 v_lshlrev_b64 v[2:3], 2, v[3:4] s_delay_alu instid0(VALU_DEP_2) v_lshlrev_b64 v[11:12], 2, v[11:12] s_waitcnt lgkmcnt(0) v_add_co_u32 v7, vcc_lo, s4, v5 v_add_co_ci_u32_e32 v8, vcc_lo, s5, v6, vcc_lo v_add_co_u32 v9, vcc_lo, s6, v5 v_add_co_ci_u32_e32 v10, vcc_lo, s7, v6, vcc_lo v_add_co_u32 v4, vcc_lo, s0, v5 v_add_co_ci_u32_e32 v5, vcc_lo, s1, v6, vcc_lo v_add_co_u32 v2, vcc_lo, s0, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo global_load_b32 v8, v[7:8], off global_load_b32 v13, v[9:10], off s_clause 0x1 global_load_b32 v14, v[4:5], off global_load_b32 v15, v[2:3], off v_mad_u64_u32 v[6:7], null, s2, 3, v[1:2] v_ashrrev_i32_e32 v1, 31, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_lshlrev_b64 v[0:1], 2, v[0:1] v_ashrrev_i32_e32 v7, 31, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_lshlrev_b64 v[6:7], 2, v[6:7] v_add_co_u32 v0, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_4) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo v_add_co_u32 v11, vcc_lo, s0, v11 v_add_co_ci_u32_e32 v12, vcc_lo, s1, v12, vcc_lo v_add_co_u32 v6, vcc_lo, s0, v6 v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo s_waitcnt vmcnt(3) global_store_b32 v[9:10], v8, off s_waitcnt vmcnt(0) v_dual_mul_f32 v14, 0x47c35000, v14 :: v_dual_mul_f32 v15, 0x47c35000, v15 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_sub_f32 v13, v8, v13 :: v_dual_mul_f32 v8, v14, v15 v_mul_f32_e32 v13, 0x47c35000, v13 s_delay_alu instid0(VALU_DEP_1) v_mul_f32_e32 v9, v14, v13 v_dual_mul_f32 v10, v15, v13 :: v_dual_mul_f32 v13, v14, v14 v_mul_f32_e32 v14, v15, v15 s_clause 0x4 global_store_b32 v[0:1], v8, off global_store_b32 v[6:7], v9, off global_store_b32 v[11:12], v10, off global_store_b32 v[4:5], v13, off global_store_b32 v[2:3], v14, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z24PrepareDerivativesKernelPfS_S_ii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 16 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z24PrepareDerivativesKernelPfS_S_ii, .Lfunc_end0-_Z24PrepareDerivativesKernelPfS_S_ii .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z24PrepareDerivativesKernelPfS_S_ii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z24PrepareDerivativesKernelPfS_S_ii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 16 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_000f89b7_00000000-6_PrepareDerivativesKernel.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z50__device_stub__Z24PrepareDerivativesKernelPfS_S_iiPfS_S_ii .type _Z50__device_stub__Z24PrepareDerivativesKernelPfS_S_iiPfS_S_ii, @function _Z50__device_stub__Z24PrepareDerivativesKernelPfS_S_iiPfS_S_ii: .LFB2051: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movl %r8d, (%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movq %rsp, %rax movq %rax, 128(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z24PrepareDerivativesKernelPfS_S_ii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z50__device_stub__Z24PrepareDerivativesKernelPfS_S_iiPfS_S_ii, .-_Z50__device_stub__Z24PrepareDerivativesKernelPfS_S_iiPfS_S_ii .globl _Z24PrepareDerivativesKernelPfS_S_ii .type _Z24PrepareDerivativesKernelPfS_S_ii, @function _Z24PrepareDerivativesKernelPfS_S_ii: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z50__device_stub__Z24PrepareDerivativesKernelPfS_S_iiPfS_S_ii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z24PrepareDerivativesKernelPfS_S_ii, .-_Z24PrepareDerivativesKernelPfS_S_ii .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "_Z24PrepareDerivativesKernelPfS_S_ii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z24PrepareDerivativesKernelPfS_S_ii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "PrepareDerivativesKernel.hip" .globl _Z39__device_stub__PrepareDerivativesKernelPfS_S_ii # -- Begin function _Z39__device_stub__PrepareDerivativesKernelPfS_S_ii .p2align 4, 0x90 .type _Z39__device_stub__PrepareDerivativesKernelPfS_S_ii,@function _Z39__device_stub__PrepareDerivativesKernelPfS_S_ii: # @_Z39__device_stub__PrepareDerivativesKernelPfS_S_ii .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) movl %r8d, (%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) movq %rsp, %rax movq %rax, 112(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z24PrepareDerivativesKernelPfS_S_ii, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z39__device_stub__PrepareDerivativesKernelPfS_S_ii, .Lfunc_end0-_Z39__device_stub__PrepareDerivativesKernelPfS_S_ii .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z24PrepareDerivativesKernelPfS_S_ii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z24PrepareDerivativesKernelPfS_S_ii,@object # @_Z24PrepareDerivativesKernelPfS_S_ii .section .rodata,"a",@progbits .globl _Z24PrepareDerivativesKernelPfS_S_ii .p2align 3, 0x0 _Z24PrepareDerivativesKernelPfS_S_ii: .quad _Z39__device_stub__PrepareDerivativesKernelPfS_S_ii .size _Z24PrepareDerivativesKernelPfS_S_ii, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z24PrepareDerivativesKernelPfS_S_ii" .size .L__unnamed_1, 37 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z39__device_stub__PrepareDerivativesKernelPfS_S_ii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z24PrepareDerivativesKernelPfS_S_ii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include <stdlib.h> #include <stdio.h> #include <fstream> #include <cuda.h> #include <iostream> #include <iomanip> #include <time.h> using namespace std; #define TILE 16 /* LU Decomposition using Shared Memory \ \ CUDA \ \ \ \ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ //Initialize a 2D matrix void initialize_matrices(double** a, double** l, double** u, int size) { //for each row in the 2d array, initialize the values for (int i = 0; i < size; ++i) { a[i] = new double[size]; l[i] = new double[size]; u[i] = new double[size]; } } //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // Scale the index for threads to get pivot starting and ending points //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ __global__ void scaleIndex(double *matrix, int n, int index){ int start=(index*n+index); int end=(index*n+n); for(int i= start+1 ; i<end; ++i){ matrix[i]=(matrix[i]/matrix[start]); } } //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // Row elimination Kernel - takes matrix, dimension, currect row index, and block size //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ __global__ void elim(double *A, int n, int index, int bsize){ extern __shared__ double pivot[]; int idThread=threadIdx.x; int idBlock=blockIdx.x; int blockSize=bsize; if(idThread==0){ for(int i=index;i<n;i++) pivot[i]=A[(index*n)+i]; } __syncthreads(); //Varitables for pivot, row, start and end int pivotRow=(index*n); int currentRow=(((blockSize*idBlock) + idThread)*n); int start=currentRow+index; int end=currentRow+n; //If greater than pivot row, loop from start index + 1(next row) to end of column if(currentRow >pivotRow){ for(int i= start+1; i<end; ++i){ //Set the matrix value of next row and its column - pivot A[i]=A[i]-(A[start]*pivot[i-currentRow]); } } } //Randomly generated diagonal dominant (non-singular) matrix - 1D void fillMatrix(double* a, int n){ // Fill the matrix for (int i = 0; i <= (n*n); ++i) { a[i] =((rand()%10)+1); } //Make the matrix diagonally dominant to guarantee it is non-singular (invertible) int diagCount = 0; double sum = 0; for(int i = 0; i < n; ++i){ //Iterate through the row, add all the values, remove the diagonal value for(int j = i*n; j < i*n + n; ++j){ sum += abs(a[j]); //printf("%f +", sum); } ///Remove the diagonal value //i*n gives us the current row, then add diagCount to get to correct column sum -= abs(a[i*n + diagCount]); //Add random value to the new sum, this guarantees diagonal is now larger than row sum a[i*n + diagCount] = sum + ((rand()%5)+1); ++diagCount; sum = 0; } } //----------------------------------------------------------------------- //Print 1D Matrix //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ void printMatrix(double* a, int n){ for(int i=0; i<(n*n); ++i){ if(i%n==0) cout << endl << left << setw(9) << setprecision(3) << a[i] << left << setw(9); else cout << left << setw(9) << setprecision(3) << a[i] << left << setw(9); } printf("\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n"); cout << endl; } //----------------------------------------------------------------------- //Print 2D Matrix //----------------------------------------------------------------------- void print2D(double** matrix, int size) { //for each row... for (int i = 0; i < size; i++) { //for each column for (int j = 0; j < size; j++) { //print out the cell cout << left << setw(9) << setprecision(3) << matrix[i][j] << left << setw(9); } //new line when ever row is done cout << endl; } } int main(int argc, char** argv){ //Matrix dimension will be n*n int n = atoi(argv[1]); srand(1); //Allocate A matrix, U, and L for CPU double *a = new double[n*n]; double *ret=new double[n*n]; //Fill in diagonal dominant matrix, then print fillMatrix(a, n); //Allocate GPU memory for A matrix, get number of blocks double *da; int numblock = n/TILE + ((n%TILE)?1:0); double runtime; runtime = clock()/(double)CLOCKS_PER_SEC; cudaMalloc(&da, n*n* sizeof (double)); cudaMemcpy(da, a, n*n*sizeof(double), cudaMemcpyHostToDevice); for(int i=0; i<n; ++i){ scaleIndex<<<1,1>>>(da,n,i); elim<<<numblock,TILE,n*sizeof(double)>>>(da,n,i,TILE); } cudaMemcpy(ret, da, n*n*sizeof(double),cudaMemcpyDeviceToHost ); //printf("Returned Matrix\n"); //printMatrix(ret,n); runtime = clock() - runtime; printf("For %u x %u Matrix\n",n,n); cout << "Runtime for LU Decomposition is: " << (runtime)/float(CLOCKS_PER_SEC) << endl; //Create 2D matrices for the L and U double** A = new double* [n]; double** u = new double* [n]; double** l = new double* [n]; //Initialize these matrices, and transfer ret values into A initialize_matrices(A,u,l,n); for(int i = 0 ;i < n ; ++i){ for(int j= 0; j < n; ++j){ A[i][j]=ret[i*n+j]; } } //Take values diagonal values from returned array and pull L and U for(int i=0; i<n; i++){ for(int j=0; j<n; j++){ //Find diagonals for(int k=0; k<n; k++){ //If the outermost for loop is larger or equal to k, then grab L values if(i>=k) l[i][k] = A[i][k]; //Else the rest of the array is zeroes else l[i][k] = 0; //If loops at diagonal then enter 1 for U, if j > k then we're on upper part //of Matrix so fill in values, if(k==j)u[k][j] = 1; else if(k<j)u[k][j] = A[k][j]; else u[k][j] = 0.0; } } } //Print L and U if user specified if(atoi(argv[2]) == 1){ printf("Matrix 'A' is:\n"); printMatrix(a,n); printf("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n"); printf("Matrix 'L' is:\n"); print2D(l,n); printf("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n"); printf("Matrix 'U' is: \n"); print2D(u,n); } //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ //Code from here on out is borrowed from Lab 1 to check for validity of L and U //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ cudaFree(da); cudaFree(ret); delete[] a; delete[] ret; return 0; }
.file "tmpxft_000b3b7f_00000000-6_luCuda.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB4046: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4046: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z19initialize_matricesPPdS0_S0_i .type _Z19initialize_matricesPPdS0_S0_i, @function _Z19initialize_matricesPPdS0_S0_i: .LFB4039: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 movq %rdi, %r14 movq %rsi, %r13 movq %rdx, %r12 movslq %ecx, %rbp salq $3, %rbp movl $0, %ebx testl %ecx, %ecx jle .L3 .L6: movq %rbp, %rdi call _Znam@PLT movq %rax, (%r14,%rbx) movq %rbp, %rdi call _Znam@PLT movq %rax, 0(%r13,%rbx) movq %rbp, %rdi call _Znam@PLT movq %rax, (%r12,%rbx) addq $8, %rbx cmpq %rbx, %rbp jne .L6 .L3: popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4039: .size _Z19initialize_matricesPPdS0_S0_i, .-_Z19initialize_matricesPPdS0_S0_i .globl _Z10fillMatrixPdi .type _Z10fillMatrixPdi, @function _Z10fillMatrixPdi: .LFB4040: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $40, %rsp .cfi_def_cfa_offset 96 movq %rdi, %rbx movl %esi, %r14d movq %rdi, %rbp movl %esi, %eax imull %esi, %eax leaq 8(%rdi,%rax,8), %r13 movq %rdi, %r12 .L11: call rand@PLT movslq %eax, %rdx imulq $1717986919, %rdx, %rdx sarq $34, %rdx movl %eax, %ecx sarl $31, %ecx subl %ecx, %edx leal (%rdx,%rdx,4), %edx addl %edx, %edx subl %edx, %eax addl $1, %eax pxor %xmm0, %xmm0 cvtsi2sdl %eax, %xmm0 movsd %xmm0, (%r12) addq $8, %r12 cmpq %r13, %r12 jne .L11 testl %r14d, %r14d jle .L10 movslq %r14d, %rax movq %rax, 8(%rsp) leaq 8(,%rax,8), %rax movq %rax, 16(%rsp) movl %r14d, %edx movl $0, %r13d movl $0, %r12d leal (%r14,%r14), %eax movl %eax, 28(%rsp) .L14: movl %edx, %r15d subl %r14d, %r15d movq %r13, %rax pxor %xmm1, %xmm1 .L13: movsd (%rbx,%rax,8), %xmm0 andpd .LC1(%rip), %xmm0 addsd %xmm0, %xmm1 addq $1, %rax cmpl %eax, %edx jg .L13 movsd 0(%rbp), %xmm0 andpd .LC1(%rip), %xmm0 subsd %xmm0, %xmm1 movsd %xmm1, (%rsp) call rand@PLT movslq %eax, %rdx imulq $1717986919, %rdx, %rdx sarq $33, %rdx movl %eax, %ecx sarl $31, %ecx subl %ecx, %edx leal (%rdx,%rdx,4), %edx subl %edx, %eax addl $1, %eax pxor %xmm0, %xmm0 cvtsi2sdl %eax, %xmm0 addsd (%rsp), %xmm0 movsd %xmm0, 0(%rbp) addl $1, %r12d movq 16(%rsp), %rax addq %rax, %rbp movq 8(%rsp), %rax addq %rax, %r13 movl 28(%rsp), %eax leal (%rax,%r15), %edx cmpl %r12d, %r14d jne .L14 .L10: addq $40, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4040: .size _Z10fillMatrixPdi, .-_Z10fillMatrixPdi .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC2: .string "\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n" .text .globl _Z11printMatrixPdi .type _Z11printMatrixPdi, @function _Z11printMatrixPdi: .LFB4041: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $8, %rsp .cfi_def_cfa_offset 64 movl %esi, %r13d imull %esi, %r13d testl %r13d, %r13d jle .L20 movq %rdi, %r14 movl %esi, %r12d movslq %r13d, %r13 movl $0, %ebx leaq _ZSt4cout(%rip), %rbp jmp .L26 .L32: call _ZSt16__throw_bad_castv@PLT .L23: movq %r15, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq (%r15), %rax movl $10, %esi movq %r15, %rdi call *48(%rax) movl %eax, %esi jmp .L24 .L21: movq 0(%rbp), %rdx movq %rbp, %rcx addq -24(%rdx), %rcx movl 24(%rcx), %eax andb $79, %al orl $32, %eax movl %eax, 24(%rcx) movq -24(%rdx), %rax movq $9, 16(%rbp,%rax) movq -24(%rdx), %rax movq $3, 8(%rbp,%rax) movsd (%r14,%rbx,8), %xmm0 movq %rbp, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq (%rax), %rdx movq %rax, %rcx addq -24(%rdx), %rcx movl 24(%rcx), %edx andb $79, %dl orl $32, %edx movl %edx, 24(%rcx) movq (%rax), %rdx movq -24(%rdx), %rdx movq $9, 16(%rax,%rdx) .L25: addq $1, %rbx cmpq %r13, %rbx je .L20 .L26: movl %ebx, %eax cltd idivl %r12d testl %edx, %edx jne .L21 movq 0(%rbp), %rax movq -24(%rax), %rax movq 240(%rbp,%rax), %r15 testq %r15, %r15 je .L32 cmpb $0, 56(%r15) je .L23 movzbl 67(%r15), %esi .L24: movsbl %sil, %esi movq %rbp, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movq %rax, %rdi movq (%rax), %rax movq %rdi, %rdx addq -24(%rax), %rdx movl 24(%rdx), %eax andb $79, %al orl $32, %eax movl %eax, 24(%rdx) movq (%rdi), %rax movq -24(%rax), %rax movq $9, 16(%rdi,%rax) movq (%rdi), %rax movq -24(%rax), %rax movq $3, 8(%rdi,%rax) movsd (%r14,%rbx,8), %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq (%rax), %rdx movq %rax, %rcx addq -24(%rdx), %rcx movl 24(%rcx), %edx andb $79, %dl orl $32, %edx movl %edx, 24(%rcx) movq (%rax), %rdx movq -24(%rdx), %rdx movq $9, 16(%rax,%rdx) jmp .L25 .L20: leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cout(%rip), %rdx movq 240(%rdx,%rax), %rbx testq %rbx, %rbx je .L33 cmpb $0, 56(%rbx) je .L28 movzbl 67(%rbx), %esi .L29: movsbl %sil, %esi leaq _ZSt4cout(%rip), %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L33: .cfi_restore_state call _ZSt16__throw_bad_castv@PLT .L28: movq %rbx, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq (%rbx), %rax movl $10, %esi movq %rbx, %rdi call *48(%rax) movl %eax, %esi jmp .L29 .cfi_endproc .LFE4041: .size _Z11printMatrixPdi, .-_Z11printMatrixPdi .globl _Z7print2DPPdi .type _Z7print2DPPdi, @function _Z7print2DPPdi: .LFB4042: .cfi_startproc endbr64 testl %esi, %esi jle .L43 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 movq %rdi, %r12 movslq %esi, %rsi leaq 0(,%rsi,8), %r13 leaq (%rdi,%r13), %r14 leaq _ZSt4cout(%rip), %rbx jmp .L36 .L46: call _ZSt16__throw_bad_castv@PLT .L39: movq %rbp, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq 0(%rbp), %rax movl $10, %esi movq %rbp, %rdi call *48(%rax) movl %eax, %esi .L40: movsbl %sil, %esi movq %rbx, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT addq $8, %r12 cmpq %r14, %r12 je .L34 .L36: movl $0, %ebp .L37: movq (%rbx), %rdx movq %rbx, %rcx addq -24(%rdx), %rcx movl 24(%rcx), %eax andb $79, %al orl $32, %eax movl %eax, 24(%rcx) movq -24(%rdx), %rax movq $9, 16(%rbx,%rax) movq -24(%rdx), %rax movq $3, 8(%rbx,%rax) movq (%r12), %rax movsd (%rax,%rbp), %xmm0 movq %rbx, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq (%rax), %rdx movq %rax, %rcx addq -24(%rdx), %rcx movl 24(%rcx), %edx andb $79, %dl orl $32, %edx movl %edx, 24(%rcx) movq (%rax), %rdx movq -24(%rdx), %rdx movq $9, 16(%rax,%rdx) addq $8, %rbp cmpq %r13, %rbp jne .L37 movq (%rbx), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbp testq %rbp, %rbp je .L46 cmpb $0, 56(%rbp) je .L39 movzbl 67(%rbp), %esi jmp .L40 .L34: popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L43: .cfi_restore 3 .cfi_restore 6 .cfi_restore 12 .cfi_restore 13 .cfi_restore 14 ret .cfi_endproc .LFE4042: .size _Z7print2DPPdi, .-_Z7print2DPPdi .globl _Z32__device_stub__Z10scaleIndexPdiiPdii .type _Z32__device_stub__Z10scaleIndexPdiiPdii, @function _Z32__device_stub__Z10scaleIndexPdiiPdii: .LFB4068: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movl %esi, 4(%rsp) movl %edx, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) leaq 4(%rsp), %rax movq %rax, 88(%rsp) movq %rsp, %rax movq %rax, 96(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L51 .L47: movq 104(%rsp), %rax subq %fs:40, %rax jne .L52 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L51: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z10scaleIndexPdii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L47 .L52: call __stack_chk_fail@PLT .cfi_endproc .LFE4068: .size _Z32__device_stub__Z10scaleIndexPdiiPdii, .-_Z32__device_stub__Z10scaleIndexPdiiPdii .globl _Z10scaleIndexPdii .type _Z10scaleIndexPdii, @function _Z10scaleIndexPdii: .LFB4069: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z32__device_stub__Z10scaleIndexPdiiPdii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4069: .size _Z10scaleIndexPdii, .-_Z10scaleIndexPdii .globl _Z26__device_stub__Z4elimPdiiiPdiii .type _Z26__device_stub__Z4elimPdiiiPdiii, @function _Z26__device_stub__Z4elimPdiiiPdiii: .LFB4070: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movl %esi, 20(%rsp) movl %edx, 16(%rsp) movl %ecx, 12(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 20(%rsp), %rax movq %rax, 104(%rsp) leaq 16(%rsp), %rax movq %rax, 112(%rsp) leaq 12(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L59 .L55: movq 136(%rsp), %rax subq %fs:40, %rax jne .L60 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L59: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z4elimPdiii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L55 .L60: call __stack_chk_fail@PLT .cfi_endproc .LFE4070: .size _Z26__device_stub__Z4elimPdiiiPdiii, .-_Z26__device_stub__Z4elimPdiiiPdiii .globl _Z4elimPdiii .type _Z4elimPdiii, @function _Z4elimPdiii: .LFB4071: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z26__device_stub__Z4elimPdiiiPdiii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4071: .size _Z4elimPdiii, .-_Z4elimPdiii .section .rodata.str1.1,"aMS",@progbits,1 .LC4: .string "For %u x %u Matrix\n" .section .rodata.str1.8 .align 8 .LC5: .string "Runtime for LU Decomposition is: " .section .rodata.str1.1 .LC7: .string "Matrix 'A' is:\n" .section .rodata.str1.8 .align 8 .LC8: .string "~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n" .section .rodata.str1.1 .LC9: .string "Matrix 'L' is:\n" .LC10: .string "Matrix 'U' is: \n" .text .globl main .type main, @function main: .LFB4043: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $88, %rsp .cfi_def_cfa_offset 144 movq %rsi, 24(%rsp) movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax movq 8(%rsi), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movq %rax, %rbx movl %eax, %ebp movl $1, %edi call srand@PLT movl %ebx, %r15d imull %ebx, %r15d movslq %r15d, %r15 salq $3, %r15 movq %r15, %rdi call _Znam@PLT movq %rax, %r13 movq %rax, 8(%rsp) movq %r15, %rdi call _Znam@PLT movq %rax, (%rsp) movl %ebx, %esi movq %r13, %rdi call _Z10fillMatrixPdi testb $15, %bl setne %r14b movzbl %r14b, %r14d leal 15(%rbx), %eax testl %ebx, %ebx cmovns %ebx, %eax sarl $4, %eax addl %eax, %r14d call clock@PLT pxor %xmm0, %xmm0 cvtsi2sdq %rax, %xmm0 divsd .LC3(%rip), %xmm0 movsd %xmm0, 16(%rsp) leaq 40(%rsp), %rdi movq %r15, %rsi call cudaMalloc@PLT movl $1, %ecx movq %r15, %rdx movq %r13, %rsi movq 40(%rsp), %rdi call cudaMemcpy@PLT testl %ebx, %ebx jle .L64 movslq %ebx, %r13 salq $3, %r13 movl $0, %r12d jmp .L67 .L95: movl %r12d, %edx movl %ebp, %esi movq 40(%rsp), %rdi call _Z32__device_stub__Z10scaleIndexPdiiPdii jmp .L65 .L66: addl $1, %r12d cmpl %ebp, %r12d je .L94 .L67: movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $0, %r9d movl $0, %r8d movq 60(%rsp), %rdx movl $1, %ecx movq 48(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L95 .L65: movl $16, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl %r14d, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $0, %r9d movq %r13, %r8 movq 60(%rsp), %rdx movl $1, %ecx movq 48(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L66 movl $16, %ecx movl %r12d, %edx movl %ebp, %esi movq 40(%rsp), %rdi call _Z26__device_stub__Z4elimPdiiiPdiii jmp .L66 .L64: movl $2, %ecx movq %r15, %rdx movq 40(%rsp), %rsi movq (%rsp), %rdi call cudaMemcpy@PLT call clock@PLT pxor %xmm0, %xmm0 cvtsi2sdq %rax, %xmm0 subsd 16(%rsp), %xmm0 movq %xmm0, %r12 movl %ebx, %ecx movl %ebx, %edx leaq .LC4(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq .LC5(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movq %r12, %xmm0 divsd .LC3(%rip), %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movslq %ebx, %r14 movabsq $1152921504606846975, %rax cmpq %r14, %rax jnb .L85 movq 72(%rsp), %rax subq %fs:40, %rax je .L72 call __stack_chk_fail@PLT .L72: call __cxa_throw_bad_array_new_length@PLT .L76: movq (%r8), %r9 movq $0x000000000, (%r9,%rax,8) jmp .L77 .L97: movq (%r12,%rax,8), %rdx movsd %xmm1, (%rdx,%rsi) jmp .L79 .L80: movq (%r12,%rax,8), %rdx movq $0x000000000, (%rdx,%rsi) .L79: addq $1, %rax cmpq %rbx, %rax je .L96 .L81: movl %eax, %edx cmpl %edi, %eax jg .L76 movq (%r10), %r9 movsd (%r9,%rax,8), %xmm0 movq (%r8), %r9 movsd %xmm0, (%r9,%rax,8) .L77: cmpl %ecx, %edx je .L97 jge .L80 movq 0(%r13,%rax,8), %rdx movsd (%rdx,%rsi), %xmm0 movq (%r12,%rax,8), %rdx movsd %xmm0, (%rdx,%rsi) jmp .L79 .L96: addl $1, %ecx addq $8, %rsi cmpl %ebp, %ecx je .L82 .L83: movl $0, %eax jmp .L81 .L82: addl $1, %edi addq $8, %r10 addq $8, %r8 cmpl %ebp, %edi je .L70 .L75: movl $0, %esi movl $0, %ecx jmp .L83 .L70: movq 24(%rsp), %rax movq 16(%rax), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT cmpl $1, %eax je .L98 .L84: movq 40(%rsp), %rdi call cudaFree@PLT movq (%rsp), %rbx movq %rbx, %rdi call cudaFree@PLT movq 8(%rsp), %rdi call _ZdaPv@PLT movq %rbx, %rdi call _ZdaPv@PLT movq 72(%rsp), %rax subq %fs:40, %rax jne .L99 movl $0, %eax addq $88, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L98: .cfi_restore_state leaq .LC7(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl %ebp, %esi movq 8(%rsp), %rdi call _Z11printMatrixPdi leaq .LC8(%rip), %rbx movq %rbx, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq .LC9(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl %ebp, %esi movq %r15, %rdi call _Z7print2DPPdi movq %rbx, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq .LC10(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl %ebp, %esi movq %r12, %rdi call _Z7print2DPPdi jmp .L84 .L94: movl $2, %ecx movq %r15, %rdx movq 40(%rsp), %rsi movq (%rsp), %rdi call cudaMemcpy@PLT call clock@PLT pxor %xmm0, %xmm0 cvtsi2sdq %rax, %xmm0 subsd 16(%rsp), %xmm0 movq %xmm0, %r12 movl %ebp, %ecx movl %ebp, %edx leaq .LC4(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq .LC5(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movq %r12, %xmm0 divsd .LC3(%rip), %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movslq %ebx, %r14 .L85: salq $3, %r14 movq %r14, %rdi call _Znam@PLT movq %rax, %r13 movq %r14, %rdi call _Znam@PLT movq %rax, %r12 movq %r14, %rdi call _Znam@PLT movq %rax, %r15 movl %ebp, %ecx movq %rax, %rdx movq %r12, %rsi movq %r13, %rdi call _Z19initialize_matricesPPdS0_S0_i testl %ebx, %ebx jle .L70 movq %r13, %r10 movq (%rsp), %rdx movl %ebx, %eax leaq 0(%r13,%rax,8), %rdi movq %r13, %rsi movl %ebx, %ebx .L71: movq (%rsi), %rcx movl $0, %eax .L73: movsd (%rdx,%rax,8), %xmm0 movsd %xmm0, (%rcx,%rax,8) addq $1, %rax cmpq %rbx, %rax jne .L73 addq $8, %rsi addq %r14, %rdx cmpq %rdi, %rsi jne .L71 movq %r15, %r8 movl $0, %edi movsd .LC6(%rip), %xmm1 jmp .L75 .L99: call __stack_chk_fail@PLT .cfi_endproc .LFE4043: .size main, .-main .section .rodata.str1.1 .LC11: .string "_Z4elimPdiii" .LC12: .string "_Z10scaleIndexPdii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB4073: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC11(%rip), %rdx movq %rdx, %rcx leaq _Z4elimPdiii(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC12(%rip), %rdx movq %rdx, %rcx leaq _Z10scaleIndexPdii(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4073: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst16,"aM",@progbits,16 .align 16 .LC1: .long -1 .long 2147483647 .long 0 .long 0 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC3: .long 0 .long 1093567616 .align 8 .LC6: .long 0 .long 1072693248 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include <stdlib.h> #include <stdio.h> #include <fstream> #include <cuda.h> #include <iostream> #include <iomanip> #include <time.h> using namespace std; #define TILE 16 /* LU Decomposition using Shared Memory \ \ CUDA \ \ \ \ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ //Initialize a 2D matrix void initialize_matrices(double** a, double** l, double** u, int size) { //for each row in the 2d array, initialize the values for (int i = 0; i < size; ++i) { a[i] = new double[size]; l[i] = new double[size]; u[i] = new double[size]; } } //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // Scale the index for threads to get pivot starting and ending points //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ __global__ void scaleIndex(double *matrix, int n, int index){ int start=(index*n+index); int end=(index*n+n); for(int i= start+1 ; i<end; ++i){ matrix[i]=(matrix[i]/matrix[start]); } } //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // Row elimination Kernel - takes matrix, dimension, currect row index, and block size //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ __global__ void elim(double *A, int n, int index, int bsize){ extern __shared__ double pivot[]; int idThread=threadIdx.x; int idBlock=blockIdx.x; int blockSize=bsize; if(idThread==0){ for(int i=index;i<n;i++) pivot[i]=A[(index*n)+i]; } __syncthreads(); //Varitables for pivot, row, start and end int pivotRow=(index*n); int currentRow=(((blockSize*idBlock) + idThread)*n); int start=currentRow+index; int end=currentRow+n; //If greater than pivot row, loop from start index + 1(next row) to end of column if(currentRow >pivotRow){ for(int i= start+1; i<end; ++i){ //Set the matrix value of next row and its column - pivot A[i]=A[i]-(A[start]*pivot[i-currentRow]); } } } //Randomly generated diagonal dominant (non-singular) matrix - 1D void fillMatrix(double* a, int n){ // Fill the matrix for (int i = 0; i <= (n*n); ++i) { a[i] =((rand()%10)+1); } //Make the matrix diagonally dominant to guarantee it is non-singular (invertible) int diagCount = 0; double sum = 0; for(int i = 0; i < n; ++i){ //Iterate through the row, add all the values, remove the diagonal value for(int j = i*n; j < i*n + n; ++j){ sum += abs(a[j]); //printf("%f +", sum); } ///Remove the diagonal value //i*n gives us the current row, then add diagCount to get to correct column sum -= abs(a[i*n + diagCount]); //Add random value to the new sum, this guarantees diagonal is now larger than row sum a[i*n + diagCount] = sum + ((rand()%5)+1); ++diagCount; sum = 0; } } //----------------------------------------------------------------------- //Print 1D Matrix //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ void printMatrix(double* a, int n){ for(int i=0; i<(n*n); ++i){ if(i%n==0) cout << endl << left << setw(9) << setprecision(3) << a[i] << left << setw(9); else cout << left << setw(9) << setprecision(3) << a[i] << left << setw(9); } printf("\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n"); cout << endl; } //----------------------------------------------------------------------- //Print 2D Matrix //----------------------------------------------------------------------- void print2D(double** matrix, int size) { //for each row... for (int i = 0; i < size; i++) { //for each column for (int j = 0; j < size; j++) { //print out the cell cout << left << setw(9) << setprecision(3) << matrix[i][j] << left << setw(9); } //new line when ever row is done cout << endl; } } int main(int argc, char** argv){ //Matrix dimension will be n*n int n = atoi(argv[1]); srand(1); //Allocate A matrix, U, and L for CPU double *a = new double[n*n]; double *ret=new double[n*n]; //Fill in diagonal dominant matrix, then print fillMatrix(a, n); //Allocate GPU memory for A matrix, get number of blocks double *da; int numblock = n/TILE + ((n%TILE)?1:0); double runtime; runtime = clock()/(double)CLOCKS_PER_SEC; cudaMalloc(&da, n*n* sizeof (double)); cudaMemcpy(da, a, n*n*sizeof(double), cudaMemcpyHostToDevice); for(int i=0; i<n; ++i){ scaleIndex<<<1,1>>>(da,n,i); elim<<<numblock,TILE,n*sizeof(double)>>>(da,n,i,TILE); } cudaMemcpy(ret, da, n*n*sizeof(double),cudaMemcpyDeviceToHost ); //printf("Returned Matrix\n"); //printMatrix(ret,n); runtime = clock() - runtime; printf("For %u x %u Matrix\n",n,n); cout << "Runtime for LU Decomposition is: " << (runtime)/float(CLOCKS_PER_SEC) << endl; //Create 2D matrices for the L and U double** A = new double* [n]; double** u = new double* [n]; double** l = new double* [n]; //Initialize these matrices, and transfer ret values into A initialize_matrices(A,u,l,n); for(int i = 0 ;i < n ; ++i){ for(int j= 0; j < n; ++j){ A[i][j]=ret[i*n+j]; } } //Take values diagonal values from returned array and pull L and U for(int i=0; i<n; i++){ for(int j=0; j<n; j++){ //Find diagonals for(int k=0; k<n; k++){ //If the outermost for loop is larger or equal to k, then grab L values if(i>=k) l[i][k] = A[i][k]; //Else the rest of the array is zeroes else l[i][k] = 0; //If loops at diagonal then enter 1 for U, if j > k then we're on upper part //of Matrix so fill in values, if(k==j)u[k][j] = 1; else if(k<j)u[k][j] = A[k][j]; else u[k][j] = 0.0; } } } //Print L and U if user specified if(atoi(argv[2]) == 1){ printf("Matrix 'A' is:\n"); printMatrix(a,n); printf("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n"); printf("Matrix 'L' is:\n"); print2D(l,n); printf("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n"); printf("Matrix 'U' is: \n"); print2D(u,n); } //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ //Code from here on out is borrowed from Lab 1 to check for validity of L and U //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ cudaFree(da); cudaFree(ret); delete[] a; delete[] ret; return 0; }
#include <stdlib.h> #include <stdio.h> #include <fstream> #include <hip/hip_runtime.h> #include <iostream> #include <iomanip> #include <time.h> using namespace std; #define TILE 16 /* LU Decomposition using Shared Memory \ \ CUDA \ \ \ \ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ //Initialize a 2D matrix void initialize_matrices(double** a, double** l, double** u, int size) { //for each row in the 2d array, initialize the values for (int i = 0; i < size; ++i) { a[i] = new double[size]; l[i] = new double[size]; u[i] = new double[size]; } } //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // Scale the index for threads to get pivot starting and ending points //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ __global__ void scaleIndex(double *matrix, int n, int index){ int start=(index*n+index); int end=(index*n+n); for(int i= start+1 ; i<end; ++i){ matrix[i]=(matrix[i]/matrix[start]); } } //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // Row elimination Kernel - takes matrix, dimension, currect row index, and block size //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ __global__ void elim(double *A, int n, int index, int bsize){ extern __shared__ double pivot[]; int idThread=threadIdx.x; int idBlock=blockIdx.x; int blockSize=bsize; if(idThread==0){ for(int i=index;i<n;i++) pivot[i]=A[(index*n)+i]; } __syncthreads(); //Varitables for pivot, row, start and end int pivotRow=(index*n); int currentRow=(((blockSize*idBlock) + idThread)*n); int start=currentRow+index; int end=currentRow+n; //If greater than pivot row, loop from start index + 1(next row) to end of column if(currentRow >pivotRow){ for(int i= start+1; i<end; ++i){ //Set the matrix value of next row and its column - pivot A[i]=A[i]-(A[start]*pivot[i-currentRow]); } } } //Randomly generated diagonal dominant (non-singular) matrix - 1D void fillMatrix(double* a, int n){ // Fill the matrix for (int i = 0; i <= (n*n); ++i) { a[i] =((rand()%10)+1); } //Make the matrix diagonally dominant to guarantee it is non-singular (invertible) int diagCount = 0; double sum = 0; for(int i = 0; i < n; ++i){ //Iterate through the row, add all the values, remove the diagonal value for(int j = i*n; j < i*n + n; ++j){ sum += abs(a[j]); //printf("%f +", sum); } ///Remove the diagonal value //i*n gives us the current row, then add diagCount to get to correct column sum -= abs(a[i*n + diagCount]); //Add random value to the new sum, this guarantees diagonal is now larger than row sum a[i*n + diagCount] = sum + ((rand()%5)+1); ++diagCount; sum = 0; } } //----------------------------------------------------------------------- //Print 1D Matrix //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ void printMatrix(double* a, int n){ for(int i=0; i<(n*n); ++i){ if(i%n==0) cout << endl << left << setw(9) << setprecision(3) << a[i] << left << setw(9); else cout << left << setw(9) << setprecision(3) << a[i] << left << setw(9); } printf("\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n"); cout << endl; } //----------------------------------------------------------------------- //Print 2D Matrix //----------------------------------------------------------------------- void print2D(double** matrix, int size) { //for each row... for (int i = 0; i < size; i++) { //for each column for (int j = 0; j < size; j++) { //print out the cell cout << left << setw(9) << setprecision(3) << matrix[i][j] << left << setw(9); } //new line when ever row is done cout << endl; } } int main(int argc, char** argv){ //Matrix dimension will be n*n int n = atoi(argv[1]); srand(1); //Allocate A matrix, U, and L for CPU double *a = new double[n*n]; double *ret=new double[n*n]; //Fill in diagonal dominant matrix, then print fillMatrix(a, n); //Allocate GPU memory for A matrix, get number of blocks double *da; int numblock = n/TILE + ((n%TILE)?1:0); double runtime; runtime = clock()/(double)CLOCKS_PER_SEC; hipMalloc(&da, n*n* sizeof (double)); hipMemcpy(da, a, n*n*sizeof(double), hipMemcpyHostToDevice); for(int i=0; i<n; ++i){ scaleIndex<<<1,1>>>(da,n,i); elim<<<numblock,TILE,n*sizeof(double)>>>(da,n,i,TILE); } hipMemcpy(ret, da, n*n*sizeof(double),hipMemcpyDeviceToHost ); //printf("Returned Matrix\n"); //printMatrix(ret,n); runtime = clock() - runtime; printf("For %u x %u Matrix\n",n,n); cout << "Runtime for LU Decomposition is: " << (runtime)/float(CLOCKS_PER_SEC) << endl; //Create 2D matrices for the L and U double** A = new double* [n]; double** u = new double* [n]; double** l = new double* [n]; //Initialize these matrices, and transfer ret values into A initialize_matrices(A,u,l,n); for(int i = 0 ;i < n ; ++i){ for(int j= 0; j < n; ++j){ A[i][j]=ret[i*n+j]; } } //Take values diagonal values from returned array and pull L and U for(int i=0; i<n; i++){ for(int j=0; j<n; j++){ //Find diagonals for(int k=0; k<n; k++){ //If the outermost for loop is larger or equal to k, then grab L values if(i>=k) l[i][k] = A[i][k]; //Else the rest of the array is zeroes else l[i][k] = 0; //If loops at diagonal then enter 1 for U, if j > k then we're on upper part //of Matrix so fill in values, if(k==j)u[k][j] = 1; else if(k<j)u[k][j] = A[k][j]; else u[k][j] = 0.0; } } } //Print L and U if user specified if(atoi(argv[2]) == 1){ printf("Matrix 'A' is:\n"); printMatrix(a,n); printf("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n"); printf("Matrix 'L' is:\n"); print2D(l,n); printf("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n"); printf("Matrix 'U' is: \n"); print2D(u,n); } //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ //Code from here on out is borrowed from Lab 1 to check for validity of L and U //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ hipFree(da); hipFree(ret); delete[] a; delete[] ret; return 0; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <stdlib.h> #include <stdio.h> #include <fstream> #include <hip/hip_runtime.h> #include <iostream> #include <iomanip> #include <time.h> using namespace std; #define TILE 16 /* LU Decomposition using Shared Memory \ \ CUDA \ \ \ \ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ //Initialize a 2D matrix void initialize_matrices(double** a, double** l, double** u, int size) { //for each row in the 2d array, initialize the values for (int i = 0; i < size; ++i) { a[i] = new double[size]; l[i] = new double[size]; u[i] = new double[size]; } } //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // Scale the index for threads to get pivot starting and ending points //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ __global__ void scaleIndex(double *matrix, int n, int index){ int start=(index*n+index); int end=(index*n+n); for(int i= start+1 ; i<end; ++i){ matrix[i]=(matrix[i]/matrix[start]); } } //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // Row elimination Kernel - takes matrix, dimension, currect row index, and block size //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ __global__ void elim(double *A, int n, int index, int bsize){ extern __shared__ double pivot[]; int idThread=threadIdx.x; int idBlock=blockIdx.x; int blockSize=bsize; if(idThread==0){ for(int i=index;i<n;i++) pivot[i]=A[(index*n)+i]; } __syncthreads(); //Varitables for pivot, row, start and end int pivotRow=(index*n); int currentRow=(((blockSize*idBlock) + idThread)*n); int start=currentRow+index; int end=currentRow+n; //If greater than pivot row, loop from start index + 1(next row) to end of column if(currentRow >pivotRow){ for(int i= start+1; i<end; ++i){ //Set the matrix value of next row and its column - pivot A[i]=A[i]-(A[start]*pivot[i-currentRow]); } } } //Randomly generated diagonal dominant (non-singular) matrix - 1D void fillMatrix(double* a, int n){ // Fill the matrix for (int i = 0; i <= (n*n); ++i) { a[i] =((rand()%10)+1); } //Make the matrix diagonally dominant to guarantee it is non-singular (invertible) int diagCount = 0; double sum = 0; for(int i = 0; i < n; ++i){ //Iterate through the row, add all the values, remove the diagonal value for(int j = i*n; j < i*n + n; ++j){ sum += abs(a[j]); //printf("%f +", sum); } ///Remove the diagonal value //i*n gives us the current row, then add diagCount to get to correct column sum -= abs(a[i*n + diagCount]); //Add random value to the new sum, this guarantees diagonal is now larger than row sum a[i*n + diagCount] = sum + ((rand()%5)+1); ++diagCount; sum = 0; } } //----------------------------------------------------------------------- //Print 1D Matrix //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ void printMatrix(double* a, int n){ for(int i=0; i<(n*n); ++i){ if(i%n==0) cout << endl << left << setw(9) << setprecision(3) << a[i] << left << setw(9); else cout << left << setw(9) << setprecision(3) << a[i] << left << setw(9); } printf("\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n"); cout << endl; } //----------------------------------------------------------------------- //Print 2D Matrix //----------------------------------------------------------------------- void print2D(double** matrix, int size) { //for each row... for (int i = 0; i < size; i++) { //for each column for (int j = 0; j < size; j++) { //print out the cell cout << left << setw(9) << setprecision(3) << matrix[i][j] << left << setw(9); } //new line when ever row is done cout << endl; } } int main(int argc, char** argv){ //Matrix dimension will be n*n int n = atoi(argv[1]); srand(1); //Allocate A matrix, U, and L for CPU double *a = new double[n*n]; double *ret=new double[n*n]; //Fill in diagonal dominant matrix, then print fillMatrix(a, n); //Allocate GPU memory for A matrix, get number of blocks double *da; int numblock = n/TILE + ((n%TILE)?1:0); double runtime; runtime = clock()/(double)CLOCKS_PER_SEC; hipMalloc(&da, n*n* sizeof (double)); hipMemcpy(da, a, n*n*sizeof(double), hipMemcpyHostToDevice); for(int i=0; i<n; ++i){ scaleIndex<<<1,1>>>(da,n,i); elim<<<numblock,TILE,n*sizeof(double)>>>(da,n,i,TILE); } hipMemcpy(ret, da, n*n*sizeof(double),hipMemcpyDeviceToHost ); //printf("Returned Matrix\n"); //printMatrix(ret,n); runtime = clock() - runtime; printf("For %u x %u Matrix\n",n,n); cout << "Runtime for LU Decomposition is: " << (runtime)/float(CLOCKS_PER_SEC) << endl; //Create 2D matrices for the L and U double** A = new double* [n]; double** u = new double* [n]; double** l = new double* [n]; //Initialize these matrices, and transfer ret values into A initialize_matrices(A,u,l,n); for(int i = 0 ;i < n ; ++i){ for(int j= 0; j < n; ++j){ A[i][j]=ret[i*n+j]; } } //Take values diagonal values from returned array and pull L and U for(int i=0; i<n; i++){ for(int j=0; j<n; j++){ //Find diagonals for(int k=0; k<n; k++){ //If the outermost for loop is larger or equal to k, then grab L values if(i>=k) l[i][k] = A[i][k]; //Else the rest of the array is zeroes else l[i][k] = 0; //If loops at diagonal then enter 1 for U, if j > k then we're on upper part //of Matrix so fill in values, if(k==j)u[k][j] = 1; else if(k<j)u[k][j] = A[k][j]; else u[k][j] = 0.0; } } } //Print L and U if user specified if(atoi(argv[2]) == 1){ printf("Matrix 'A' is:\n"); printMatrix(a,n); printf("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n"); printf("Matrix 'L' is:\n"); print2D(l,n); printf("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n"); printf("Matrix 'U' is: \n"); print2D(u,n); } //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ //Code from here on out is borrowed from Lab 1 to check for validity of L and U //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ hipFree(da); hipFree(ret); delete[] a; delete[] ret; return 0; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z10scaleIndexPdii .globl _Z10scaleIndexPdii .p2align 8 .type _Z10scaleIndexPdii,@function _Z10scaleIndexPdii: s_load_b64 s[4:5], s[0:1], 0x8 s_waitcnt lgkmcnt(0) s_mul_i32 s3, s5, s4 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) s_add_i32 s2, s3, s5 s_add_i32 s4, s3, s4 s_add_i32 s5, s2, 1 s_cmp_ge_i32 s5, s4 s_cbranch_scc1 .LBB0_3 s_load_b64 s[0:1], s[0:1], 0x0 s_ashr_i32 s3, s2, 31 v_mov_b32_e32 v0, 0 s_lshl_b64 s[2:3], s[2:3], 3 s_waitcnt lgkmcnt(0) s_add_u32 s0, s2, s0 s_addc_u32 s1, s3, s1 s_add_u32 s2, s0, 8 s_addc_u32 s3, s1, 0 .p2align 6 .LBB0_2: s_clause 0x1 global_load_b64 v[1:2], v0, s[2:3] global_load_b64 v[3:4], v0, s[0:1] s_add_i32 s5, s5, 1 s_waitcnt vmcnt(0) v_div_scale_f64 v[5:6], null, v[3:4], v[3:4], v[1:2] v_div_scale_f64 v[11:12], vcc_lo, v[1:2], v[3:4], v[1:2] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f64_e32 v[7:8], v[5:6] s_waitcnt_depctr 0xfff v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0 v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0 v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[9:10], v[11:12], v[7:8] v_fma_f64 v[5:6], -v[5:6], v[9:10], v[11:12] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f64 v[5:6], v[5:6], v[7:8], v[9:10] v_div_fixup_f64 v[1:2], v[5:6], v[3:4], v[1:2] global_store_b64 v0, v[1:2], s[2:3] s_add_u32 s2, s2, 8 s_addc_u32 s3, s3, 0 s_cmp_ge_i32 s5, s4 s_cbranch_scc0 .LBB0_2 .LBB0_3: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z10scaleIndexPdii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 13 .amdhsa_next_free_sgpr 6 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z10scaleIndexPdii, .Lfunc_end0-_Z10scaleIndexPdii .section .AMDGPU.csdata,"",@progbits .text .protected _Z4elimPdiii .globl _Z4elimPdiii .p2align 8 .type _Z4elimPdiii,@function _Z4elimPdiii: s_load_b128 s[4:7], s[0:1], 0x0 v_cmp_eq_u32_e32 vcc_lo, 0, v0 s_waitcnt lgkmcnt(0) s_cmp_lt_i32 s7, s6 s_cselect_b32 s2, -1, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s2, vcc_lo, s2 s_and_saveexec_b32 s8, s2 s_cbranch_execz .LBB1_3 s_add_i32 s2, s6, 1 s_mov_b32 s10, s7 s_mul_i32 s2, s7, s2 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_ashr_i32 s3, s2, 31 s_lshl_b64 s[2:3], s[2:3], 3 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) s_add_u32 s2, s4, s2 s_addc_u32 s3, s5, s3 s_lshl_b32 s9, s7, 3 s_add_i32 s9, s9, 0 .LBB1_2: s_load_b64 s[12:13], s[2:3], 0x0 v_mov_b32_e32 v3, s9 s_add_i32 s10, s10, 1 s_add_u32 s2, s2, 8 s_addc_u32 s3, s3, 0 s_add_i32 s9, s9, 8 s_cmp_lt_i32 s10, s6 s_waitcnt lgkmcnt(0) v_dual_mov_b32 v1, s12 :: v_dual_mov_b32 v2, s13 ds_store_b64 v3, v[1:2] s_cbranch_scc1 .LBB1_2 .LBB1_3: s_or_b32 exec_lo, exec_lo, s8 s_load_b32 s0, s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1] s_mul_i32 s0, s7, s6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v0, v1, s6 v_cmp_lt_i32_e32 vcc_lo, s0, v0 s_and_saveexec_b32 s0, vcc_lo s_cbranch_execz .LBB1_7 v_add_nc_u32_e32 v2, s7, v0 v_add_nc_u32_e32 v5, s6, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v0, 1, v2 v_cmp_lt_i32_e32 vcc_lo, v0, v5 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB1_7 v_ashrrev_i32_e32 v3, 31, v2 v_ashrrev_i32_e32 v1, 31, v0 s_lshl_b32 s0, s7, 3 s_mov_b32 s1, 0 s_add_i32 s0, s0, 0 v_lshlrev_b64 v[2:3], 3, v[2:3] v_lshlrev_b64 v[6:7], 3, v[0:1] s_add_i32 s2, s0, 8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v1, vcc_lo, s4, v2 v_add_co_ci_u32_e32 v2, vcc_lo, s5, v3, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_co_u32 v3, vcc_lo, s4, v6 v_add_co_ci_u32_e32 v4, vcc_lo, s5, v7, vcc_lo .p2align 6 .LBB1_6: global_load_b64 v[6:7], v[3:4], off global_load_b64 v[8:9], v[1:2], off v_mov_b32_e32 v10, s2 v_add_nc_u32_e32 v0, 1, v0 s_add_i32 s2, s2, 8 ds_load_b64 v[10:11], v10 v_cmp_ge_i32_e32 vcc_lo, v0, v5 s_or_b32 s1, vcc_lo, s1 s_waitcnt vmcnt(0) lgkmcnt(0) v_fma_f64 v[6:7], -v[8:9], v[10:11], v[6:7] global_store_b64 v[3:4], v[6:7], off v_add_co_u32 v3, s0, v3, 8 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v4, s0, 0, v4, s0 s_and_not1_b32 exec_lo, exec_lo, s1 s_cbranch_execnz .LBB1_6 .LBB1_7: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z4elimPdiii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 20 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 12 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z4elimPdiii, .Lfunc_end1-_Z4elimPdiii .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .offset: 12 .size: 4 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z10scaleIndexPdii .private_segment_fixed_size: 0 .sgpr_count: 8 .sgpr_spill_count: 0 .symbol: _Z10scaleIndexPdii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 13 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .offset: 12 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 20 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z4elimPdiii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z4elimPdiii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 12 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <stdlib.h> #include <stdio.h> #include <fstream> #include <hip/hip_runtime.h> #include <iostream> #include <iomanip> #include <time.h> using namespace std; #define TILE 16 /* LU Decomposition using Shared Memory \ \ CUDA \ \ \ \ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ //Initialize a 2D matrix void initialize_matrices(double** a, double** l, double** u, int size) { //for each row in the 2d array, initialize the values for (int i = 0; i < size; ++i) { a[i] = new double[size]; l[i] = new double[size]; u[i] = new double[size]; } } //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // Scale the index for threads to get pivot starting and ending points //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ __global__ void scaleIndex(double *matrix, int n, int index){ int start=(index*n+index); int end=(index*n+n); for(int i= start+1 ; i<end; ++i){ matrix[i]=(matrix[i]/matrix[start]); } } //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // Row elimination Kernel - takes matrix, dimension, currect row index, and block size //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ __global__ void elim(double *A, int n, int index, int bsize){ extern __shared__ double pivot[]; int idThread=threadIdx.x; int idBlock=blockIdx.x; int blockSize=bsize; if(idThread==0){ for(int i=index;i<n;i++) pivot[i]=A[(index*n)+i]; } __syncthreads(); //Varitables for pivot, row, start and end int pivotRow=(index*n); int currentRow=(((blockSize*idBlock) + idThread)*n); int start=currentRow+index; int end=currentRow+n; //If greater than pivot row, loop from start index + 1(next row) to end of column if(currentRow >pivotRow){ for(int i= start+1; i<end; ++i){ //Set the matrix value of next row and its column - pivot A[i]=A[i]-(A[start]*pivot[i-currentRow]); } } } //Randomly generated diagonal dominant (non-singular) matrix - 1D void fillMatrix(double* a, int n){ // Fill the matrix for (int i = 0; i <= (n*n); ++i) { a[i] =((rand()%10)+1); } //Make the matrix diagonally dominant to guarantee it is non-singular (invertible) int diagCount = 0; double sum = 0; for(int i = 0; i < n; ++i){ //Iterate through the row, add all the values, remove the diagonal value for(int j = i*n; j < i*n + n; ++j){ sum += abs(a[j]); //printf("%f +", sum); } ///Remove the diagonal value //i*n gives us the current row, then add diagCount to get to correct column sum -= abs(a[i*n + diagCount]); //Add random value to the new sum, this guarantees diagonal is now larger than row sum a[i*n + diagCount] = sum + ((rand()%5)+1); ++diagCount; sum = 0; } } //----------------------------------------------------------------------- //Print 1D Matrix //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ void printMatrix(double* a, int n){ for(int i=0; i<(n*n); ++i){ if(i%n==0) cout << endl << left << setw(9) << setprecision(3) << a[i] << left << setw(9); else cout << left << setw(9) << setprecision(3) << a[i] << left << setw(9); } printf("\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n"); cout << endl; } //----------------------------------------------------------------------- //Print 2D Matrix //----------------------------------------------------------------------- void print2D(double** matrix, int size) { //for each row... for (int i = 0; i < size; i++) { //for each column for (int j = 0; j < size; j++) { //print out the cell cout << left << setw(9) << setprecision(3) << matrix[i][j] << left << setw(9); } //new line when ever row is done cout << endl; } } int main(int argc, char** argv){ //Matrix dimension will be n*n int n = atoi(argv[1]); srand(1); //Allocate A matrix, U, and L for CPU double *a = new double[n*n]; double *ret=new double[n*n]; //Fill in diagonal dominant matrix, then print fillMatrix(a, n); //Allocate GPU memory for A matrix, get number of blocks double *da; int numblock = n/TILE + ((n%TILE)?1:0); double runtime; runtime = clock()/(double)CLOCKS_PER_SEC; hipMalloc(&da, n*n* sizeof (double)); hipMemcpy(da, a, n*n*sizeof(double), hipMemcpyHostToDevice); for(int i=0; i<n; ++i){ scaleIndex<<<1,1>>>(da,n,i); elim<<<numblock,TILE,n*sizeof(double)>>>(da,n,i,TILE); } hipMemcpy(ret, da, n*n*sizeof(double),hipMemcpyDeviceToHost ); //printf("Returned Matrix\n"); //printMatrix(ret,n); runtime = clock() - runtime; printf("For %u x %u Matrix\n",n,n); cout << "Runtime for LU Decomposition is: " << (runtime)/float(CLOCKS_PER_SEC) << endl; //Create 2D matrices for the L and U double** A = new double* [n]; double** u = new double* [n]; double** l = new double* [n]; //Initialize these matrices, and transfer ret values into A initialize_matrices(A,u,l,n); for(int i = 0 ;i < n ; ++i){ for(int j= 0; j < n; ++j){ A[i][j]=ret[i*n+j]; } } //Take values diagonal values from returned array and pull L and U for(int i=0; i<n; i++){ for(int j=0; j<n; j++){ //Find diagonals for(int k=0; k<n; k++){ //If the outermost for loop is larger or equal to k, then grab L values if(i>=k) l[i][k] = A[i][k]; //Else the rest of the array is zeroes else l[i][k] = 0; //If loops at diagonal then enter 1 for U, if j > k then we're on upper part //of Matrix so fill in values, if(k==j)u[k][j] = 1; else if(k<j)u[k][j] = A[k][j]; else u[k][j] = 0.0; } } } //Print L and U if user specified if(atoi(argv[2]) == 1){ printf("Matrix 'A' is:\n"); printMatrix(a,n); printf("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n"); printf("Matrix 'L' is:\n"); print2D(l,n); printf("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n"); printf("Matrix 'U' is: \n"); print2D(u,n); } //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ //Code from here on out is borrowed from Lab 1 to check for validity of L and U //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ hipFree(da); hipFree(ret); delete[] a; delete[] ret; return 0; }
.text .file "luCuda.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z19initialize_matricesPPdS0_S0_i # -- Begin function _Z19initialize_matricesPPdS0_S0_i .p2align 4, 0x90 .type _Z19initialize_matricesPPdS0_S0_i,@function _Z19initialize_matricesPPdS0_S0_i: # @_Z19initialize_matricesPPdS0_S0_i .cfi_startproc # %bb.0: testl %ecx, %ecx jle .LBB0_4 # %bb.1: # %.lr.ph pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 pushq %rax .cfi_def_cfa_offset 64 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rdx, %rbx movq %rsi, %r14 movq %rdi, %r15 movl %ecx, %r13d leaq (,%r13,8), %r12 xorl %ebp, %ebp .p2align 4, 0x90 .LBB0_2: # =>This Inner Loop Header: Depth=1 movq %r12, %rdi callq _Znam movq %rax, (%r15,%rbp,8) movq %r12, %rdi callq _Znam movq %rax, (%r14,%rbp,8) movq %r12, %rdi callq _Znam movq %rax, (%rbx,%rbp,8) incq %rbp cmpq %rbp, %r13 jne .LBB0_2 # %bb.3: addq $8, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 .cfi_restore %rbx .cfi_restore %r12 .cfi_restore %r13 .cfi_restore %r14 .cfi_restore %r15 .cfi_restore %rbp .LBB0_4: # %._crit_edge retq .Lfunc_end0: .size _Z19initialize_matricesPPdS0_S0_i, .Lfunc_end0-_Z19initialize_matricesPPdS0_S0_i .cfi_endproc # -- End function .globl _Z25__device_stub__scaleIndexPdii # -- Begin function _Z25__device_stub__scaleIndexPdii .p2align 4, 0x90 .type _Z25__device_stub__scaleIndexPdii,@function _Z25__device_stub__scaleIndexPdii: # @_Z25__device_stub__scaleIndexPdii .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movl %esi, 4(%rsp) movl %edx, (%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 4(%rsp), %rax movq %rax, 72(%rsp) movq %rsp, %rax movq %rax, 80(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z10scaleIndexPdii, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end1: .size _Z25__device_stub__scaleIndexPdii, .Lfunc_end1-_Z25__device_stub__scaleIndexPdii .cfi_endproc # -- End function .globl _Z19__device_stub__elimPdiii # -- Begin function _Z19__device_stub__elimPdiii .p2align 4, 0x90 .type _Z19__device_stub__elimPdiii,@function _Z19__device_stub__elimPdiii: # @_Z19__device_stub__elimPdiii .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movl %esi, 20(%rsp) movl %edx, 16(%rsp) movl %ecx, 12(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 20(%rsp), %rax movq %rax, 88(%rsp) leaq 16(%rsp), %rax movq %rax, 96(%rsp) leaq 12(%rsp), %rax movq %rax, 104(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z4elimPdiii, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end2: .size _Z19__device_stub__elimPdiii, .Lfunc_end2-_Z19__device_stub__elimPdiii .cfi_endproc # -- End function .section .rodata.cst16,"aM",@progbits,16 .p2align 4, 0x0 # -- Begin function _Z10fillMatrixPdi .LCPI3_0: .quad 0x7fffffffffffffff # double NaN .quad 0x7fffffffffffffff # double NaN .text .globl _Z10fillMatrixPdi .p2align 4, 0x90 .type _Z10fillMatrixPdi,@function _Z10fillMatrixPdi: # @_Z10fillMatrixPdi .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $24, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rdi, %r14 movl %esi, 12(%rsp) # 4-byte Spill movl %esi, %r15d imull %r15d, %r15d incl %r15d xorl %r12d, %r12d .p2align 4, 0x90 .LBB3_1: # =>This Inner Loop Header: Depth=1 callq rand cltq imulq $1717986919, %rax, %rcx # imm = 0x66666667 movq %rcx, %rdx shrq $63, %rdx sarq $34, %rcx addl %edx, %ecx addl %ecx, %ecx leal (%rcx,%rcx,4), %ecx negl %ecx addl %ecx, %eax incl %eax xorps %xmm0, %xmm0 cvtsi2sd %eax, %xmm0 movsd %xmm0, (%r14,%r12,8) incq %r12 cmpq %r12, %r15 jne .LBB3_1 # %bb.2: # %.preheader cmpl $0, 12(%rsp) # 4-byte Folded Reload jle .LBB3_7 # %bb.3: # %.lr.ph39.preheader movabsq $4294967296, %r15 # imm = 0x100000000 movl 12(%rsp), %r12d # 4-byte Reload xorl %r13d, %r13d movapd .LCPI3_0(%rip), %xmm1 # xmm1 = [NaN,NaN] xorl %ebp, %ebp .p2align 4, 0x90 .LBB3_4: # %.lr.ph39 # =>This Loop Header: Depth=1 # Child Loop BB3_5 Depth 2 movl %ebp, %eax leaq (%r14,%rax,8), %rcx shlq $32, %rax addq %r15, %rax movq %r13, %rdx imulq %r12, %rdx leaq (%rdx,%r12), %rsi xorpd %xmm2, %xmm2 .p2align 4, 0x90 .LBB3_5: # %.lr.ph # Parent Loop BB3_4 Depth=1 # => This Inner Loop Header: Depth=2 movsd (%rcx), %xmm0 # xmm0 = mem[0],zero andpd %xmm1, %xmm0 addsd %xmm0, %xmm2 movq %rax, %rdi sarq $32, %rdi addq $8, %rcx addq %r15, %rax cmpq %rsi, %rdi jl .LBB3_5 # %bb.6: # %._crit_edge # in Loop: Header=BB3_4 Depth=1 leaq (%r14,%rdx,8), %rbx movsd (%rbx,%r13,8), %xmm0 # xmm0 = mem[0],zero andpd %xmm1, %xmm0 subsd %xmm0, %xmm2 movsd %xmm2, 16(%rsp) # 8-byte Spill callq rand movapd .LCPI3_0(%rip), %xmm1 # xmm1 = [NaN,NaN] cltq imulq $1717986919, %rax, %rcx # imm = 0x66666667 movq %rcx, %rdx shrq $63, %rdx sarq $33, %rcx addl %edx, %ecx leal (%rcx,%rcx,4), %ecx negl %ecx addl %ecx, %eax incl %eax xorps %xmm0, %xmm0 cvtsi2sd %eax, %xmm0 addsd 16(%rsp), %xmm0 # 8-byte Folded Reload movsd %xmm0, (%rbx,%r13,8) incq %r13 addl 12(%rsp), %ebp # 4-byte Folded Reload cmpq %r12, %r13 jne .LBB3_4 .LBB3_7: # %._crit_edge40 addq $24, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end3: .size _Z10fillMatrixPdi, .Lfunc_end3-_Z10fillMatrixPdi .cfi_endproc # -- End function .globl _Z11printMatrixPdi # -- Begin function _Z11printMatrixPdi .p2align 4, 0x90 .type _Z11printMatrixPdi,@function _Z11printMatrixPdi: # @_Z11printMatrixPdi .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 pushq %rax .cfi_def_cfa_offset 64 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 testl %esi, %esi je .LBB4_6 # %bb.1: # %.lr.ph.preheader movl %esi, %ebx movq %rdi, %r14 movl %esi, %r13d imull %r13d, %r13d cmpl $1, %r13d adcl $0, %r13d xorl %r15d, %r15d movl $-177, %ebp jmp .LBB4_2 .p2align 4, 0x90 .LBB4_13: # in Loop: Header=BB4_2 Depth=1 movl $_ZSt4cout, %edi movl _ZSt4cout+24(%rcx), %edx andl %ebp, %edx orl $32, %edx movl %edx, _ZSt4cout+24(%rcx) movq -24(%rax), %rcx movq $9, _ZSt4cout+16(%rcx) movq -24(%rax), %rax movl $_ZSt4cout+8, %ecx addq %rcx, %rax .LBB4_14: # in Loop: Header=BB4_2 Depth=1 movq $3, (%rax) movsd (%r14,%r15,8), %xmm0 # xmm0 = mem[0],zero callq _ZNSo9_M_insertIdEERSoT_ movq (%rax), %rcx movq -24(%rcx), %rdx movl 24(%rax,%rdx), %esi andl %ebp, %esi orl $32, %esi movl %esi, 24(%rax,%rdx) movq -24(%rcx), %rcx movq $9, 16(%rax,%rcx) incq %r15 cmpq %r15, %r13 je .LBB4_6 .LBB4_2: # %.lr.ph # =>This Inner Loop Header: Depth=1 movl %r15d, %eax cltd idivl %ebx movq _ZSt4cout(%rip), %rax movq -24(%rax), %rcx testl %edx, %edx jne .LBB4_13 # %bb.3: # in Loop: Header=BB4_2 Depth=1 movq _ZSt4cout+240(%rcx), %r12 testq %r12, %r12 je .LBB4_15 # %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i15 # in Loop: Header=BB4_2 Depth=1 cmpb $0, 56(%r12) je .LBB4_11 # %bb.5: # in Loop: Header=BB4_2 Depth=1 movzbl 67(%r12), %eax jmp .LBB4_12 .LBB4_11: # in Loop: Header=BB4_2 Depth=1 movq %r12, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r12), %rax movq %r12, %rdi movl $10, %esi callq *48(%rax) .LBB4_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit18 # in Loop: Header=BB4_2 Depth=1 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq %rax, %rdi movq (%rax), %rax movq -24(%rax), %rcx movl 24(%rdi,%rcx), %edx andl %ebp, %edx orl $32, %edx movl %edx, 24(%rdi,%rcx) movq -24(%rax), %rcx movq $9, 16(%rdi,%rcx) movq -24(%rax), %rax addq %rdi, %rax addq $8, %rax jmp .LBB4_14 .LBB4_6: # %._crit_edge movl $.Lstr, %edi callq puts@PLT movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %rbx testq %rbx, %rbx je .LBB4_15 # %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%rbx) je .LBB4_9 # %bb.8: movzbl 67(%rbx), %eax jmp .LBB4_10 .LBB4_9: movq %rbx, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) .LBB4_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi addq $8, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 jmp _ZNSo5flushEv # TAILCALL .LBB4_15: .cfi_def_cfa_offset 64 callq _ZSt16__throw_bad_castv .Lfunc_end4: .size _Z11printMatrixPdi, .Lfunc_end4-_Z11printMatrixPdi .cfi_endproc # -- End function .globl _Z7print2DPPdi # -- Begin function _Z7print2DPPdi .p2align 4, 0x90 .type _Z7print2DPPdi,@function _Z7print2DPPdi: # @_Z7print2DPPdi .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 testl %esi, %esi jle .LBB5_9 # %bb.1: # %.preheader.lr.ph movq %rdi, %rbx movl %esi, %r15d xorl %r12d, %r12d movl $-177, %ebp jmp .LBB5_2 .p2align 4, 0x90 .LBB5_7: # in Loop: Header=BB5_2 Depth=1 movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB5_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit # in Loop: Header=BB5_2 Depth=1 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv incq %r12 cmpq %r15, %r12 je .LBB5_9 .LBB5_2: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB5_3 Depth 2 xorl %r14d, %r14d .p2align 4, 0x90 .LBB5_3: # Parent Loop BB5_2 Depth=1 # => This Inner Loop Header: Depth=2 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rcx movl _ZSt4cout+24(%rcx), %edx andl %ebp, %edx orl $32, %edx movl %edx, _ZSt4cout+24(%rcx) movq -24(%rax), %rcx movq $9, _ZSt4cout+16(%rcx) movq -24(%rax), %rax movq $3, _ZSt4cout+8(%rax) movq (%rbx,%r12,8), %rax movsd (%rax,%r14,8), %xmm0 # xmm0 = mem[0],zero movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movq (%rax), %rcx movq -24(%rcx), %rdx movl 24(%rax,%rdx), %esi andl %ebp, %esi orl $32, %esi movl %esi, 24(%rax,%rdx) movq -24(%rcx), %rcx movq $9, 16(%rax,%rcx) incq %r14 cmpq %r14, %r15 jne .LBB5_3 # %bb.4: # %._crit_edge # in Loop: Header=BB5_2 Depth=1 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r14 testq %r14, %r14 je .LBB5_10 # %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i # in Loop: Header=BB5_2 Depth=1 cmpb $0, 56(%r14) je .LBB5_7 # %bb.6: # in Loop: Header=BB5_2 Depth=1 movzbl 67(%r14), %eax jmp .LBB5_8 .LBB5_9: # %._crit_edge17 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB5_10: .cfi_def_cfa_offset 48 callq _ZSt16__throw_bad_castv .Lfunc_end5: .size _Z7print2DPPdi, .Lfunc_end5-_Z7print2DPPdi .cfi_endproc # -- End function .section .rodata.cst16,"aM",@progbits,16 .p2align 4, 0x0 # -- Begin function main .LCPI6_0: .quad 0x7fffffffffffffff # double NaN .quad 0x7fffffffffffffff # double NaN .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 .LCPI6_1: .quad 0x412e848000000000 # double 1.0E+6 .LCPI6_2: .quad 0x3ff0000000000000 # double 1 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $152, %rsp .cfi_def_cfa_offset 208 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rsi, 144(%rsp) # 8-byte Spill movq 8(%rsi), %rdi xorl %r14d, %r14d xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, %rbx movl $1, %edi callq srand movl %ebx, %r15d imull %r15d, %r15d leaq (,%r15,8), %r12 movq %r12, %rdi callq _Znam movq %rax, %r13 movq %r12, 104(%rsp) # 8-byte Spill movq %r12, %rdi callq _Znam movq %rax, 96(%rsp) # 8-byte Spill incl %r15d .p2align 4, 0x90 .LBB6_1: # =>This Inner Loop Header: Depth=1 callq rand cltq imulq $1717986919, %rax, %rcx # imm = 0x66666667 movq %rcx, %rdx shrq $63, %rdx sarq $34, %rcx addl %edx, %ecx addl %ecx, %ecx leal (%rcx,%rcx,4), %ecx negl %ecx addl %ecx, %eax incl %eax xorps %xmm0, %xmm0 cvtsi2sd %eax, %xmm0 movsd %xmm0, (%r13,%r14,8) incq %r14 cmpq %r14, %r15 jne .LBB6_1 # %bb.2: # %.preheader.i movabsq $4294967296, %rbp # imm = 0x100000000 testl %ebx, %ebx movq %r13, 24(%rsp) # 8-byte Spill jle .LBB6_7 # %bb.3: # %.lr.ph39.preheader.i movl %ebx, %r14d xorl %r15d, %r15d movapd .LCPI6_0(%rip), %xmm1 # xmm1 = [NaN,NaN] xorl %r12d, %r12d .p2align 4, 0x90 .LBB6_4: # %.lr.ph39.i # =>This Loop Header: Depth=1 # Child Loop BB6_5 Depth 2 movl %r12d, %eax leaq (,%rax,8), %rcx addq %r13, %rcx shlq $32, %rax addq %rbp, %rax movq %r15, %rdx imulq %r14, %rdx leaq (%rdx,%r14), %rsi xorpd %xmm2, %xmm2 .p2align 4, 0x90 .LBB6_5: # %.lr.ph.i # Parent Loop BB6_4 Depth=1 # => This Inner Loop Header: Depth=2 movsd (%rcx), %xmm0 # xmm0 = mem[0],zero andpd %xmm1, %xmm0 addsd %xmm0, %xmm2 movq %rax, %rdi sarq $32, %rdi addq %rbp, %rax addq $8, %rcx cmpq %rsi, %rdi jl .LBB6_5 # %bb.6: # %._crit_edge.i # in Loop: Header=BB6_4 Depth=1 movq 24(%rsp), %rax # 8-byte Reload leaq (%rax,%rdx,8), %r13 movsd (%r13,%r15,8), %xmm0 # xmm0 = mem[0],zero andpd %xmm1, %xmm0 subsd %xmm0, %xmm2 movsd %xmm2, (%rsp) # 8-byte Spill callq rand movapd .LCPI6_0(%rip), %xmm1 # xmm1 = [NaN,NaN] cltq imulq $1717986919, %rax, %rcx # imm = 0x66666667 movq %rcx, %rdx shrq $63, %rdx sarq $33, %rcx addl %edx, %ecx leal (%rcx,%rcx,4), %ecx negl %ecx addl %ecx, %eax incl %eax xorps %xmm0, %xmm0 cvtsi2sd %eax, %xmm0 addsd (%rsp), %xmm0 # 8-byte Folded Reload movsd %xmm0, (%r13,%r15,8) movq 24(%rsp), %r13 # 8-byte Reload incq %r15 addl %ebx, %r12d cmpq %r14, %r15 jne .LBB6_4 .LBB6_7: # %_Z10fillMatrixPdi.exit callq clock xorps %xmm0, %xmm0 cvtsi2sd %rax, %xmm0 divsd .LCPI6_1(%rip), %xmm0 movsd %xmm0, (%rsp) # 8-byte Spill leaq 16(%rsp), %rdi movq 104(%rsp), %r14 # 8-byte Reload movq %r14, %rsi callq hipMalloc movq 16(%rsp), %rdi movq %r13, %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy testl %ebx, %ebx jle .LBB6_14 # %bb.8: # %.lr.ph movl %ebx, %eax andl $15, %eax movl %ebx, %r12d shrl $4, %r12d cmpl $1, %eax sbbl $-1, %r12d movslq %ebx, %r13 shlq $3, %r13 orq %rbp, %r12 xorl %r14d, %r14d leaq 1(%rbp), %r15 addq $16, %rbp jmp .LBB6_9 .p2align 4, 0x90 .LBB6_13: # in Loop: Header=BB6_9 Depth=1 incl %r14d cmpl %r14d, %ebx je .LBB6_14 .LBB6_9: # =>This Inner Loop Header: Depth=1 movq %r15, %rdi movl $1, %esi movq %r15, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB6_11 # %bb.10: # in Loop: Header=BB6_9 Depth=1 movq 16(%rsp), %rax movq %rax, 80(%rsp) movl %ebx, 12(%rsp) movl %r14d, 8(%rsp) leaq 80(%rsp), %rax movq %rax, 112(%rsp) leaq 12(%rsp), %rax movq %rax, 120(%rsp) leaq 8(%rsp), %rax movq %rax, 128(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d movl $_Z10scaleIndexPdii, %edi leaq 112(%rsp), %r9 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB6_11: # in Loop: Header=BB6_9 Depth=1 movq %r12, %rdi movl $1, %esi movq %rbp, %rdx movl $1, %ecx movq %r13, %r8 xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB6_13 # %bb.12: # in Loop: Header=BB6_9 Depth=1 movq 16(%rsp), %rax movq %rax, 80(%rsp) movl %ebx, 12(%rsp) movl %r14d, 8(%rsp) movl $16, 92(%rsp) leaq 80(%rsp), %rax movq %rax, 112(%rsp) leaq 12(%rsp), %rax movq %rax, 120(%rsp) leaq 8(%rsp), %rax movq %rax, 128(%rsp) leaq 92(%rsp), %rax movq %rax, 136(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d movl $_Z4elimPdiii, %edi leaq 112(%rsp), %r9 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 jmp .LBB6_13 .LBB6_14: # %._crit_edge movq 16(%rsp), %rsi movq 96(%rsp), %rdi # 8-byte Reload movq 104(%rsp), %rdx # 8-byte Reload movl $2, %ecx callq hipMemcpy callq clock xorps %xmm0, %xmm0 cvtsi2sd %rax, %xmm0 subsd (%rsp), %xmm0 # 8-byte Folded Reload movsd %xmm0, (%rsp) # 8-byte Spill movl $.L.str.1, %edi movl %ebx, %esi movl %ebx, %edx xorl %eax, %eax callq printf movl $_ZSt4cout, %edi movl $.L.str.2, %esi movl $33, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movsd (%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero divsd .LCPI6_1(%rip), %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %r15 testq %r15, %r15 je .LBB6_41 # %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%r15) je .LBB6_17 # %bb.16: movzbl 67(%r15), %ecx jmp .LBB6_18 .LBB6_17: movq %r15, %rdi movq %rbx, %r14 movq %rax, %rbx callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r15), %rax movq %r15, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %rbx, %rax movq %r14, %rbx .LBB6_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movslq %ebx, %rax shlq $3, %rax testl %ebx, %ebx movq $-1, %r15 cmovnsq %rax, %r15 movq %r15, %rdi callq _Znam movq %rax, %r12 movq %r15, %rdi callq _Znam movq %rax, %r13 movq %r15, %rdi callq _Znam movq %rax, %rbp movq %rbx, (%rsp) # 8-byte Spill testl %ebx, %ebx jle .LBB6_21 # %bb.19: # %.lr.ph.i116 movl (%rsp), %r14d # 4-byte Reload leaq (,%r14,8), %r15 xorl %ebx, %ebx .p2align 4, 0x90 .LBB6_20: # =>This Inner Loop Header: Depth=1 movq %r15, %rdi callq _Znam movq %rax, (%r12,%rbx,8) movq %r15, %rdi callq _Znam movq %rax, (%r13,%rbx,8) movq %r15, %rdi callq _Znam movq %rax, (%rbp,%rbx,8) incq %rbx cmpq %rbx, %r14 jne .LBB6_20 .LBB6_21: # %_Z19initialize_matricesPPdS0_S0_i.exit movq (%rsp), %rbx # 8-byte Reload testl %ebx, %ebx movq 96(%rsp), %r14 # 8-byte Reload jle .LBB6_26 # %bb.22: # %.preheader139.lr.ph movl %ebx, %eax xorl %ecx, %ecx xorl %edx, %edx .p2align 4, 0x90 .LBB6_23: # %.preheader139 # =>This Loop Header: Depth=1 # Child Loop BB6_24 Depth 2 movl %ecx, %esi leaq (%r14,%rsi,8), %rsi movq (%r12,%rdx,8), %rdi xorl %r8d, %r8d .p2align 4, 0x90 .LBB6_24: # Parent Loop BB6_23 Depth=1 # => This Inner Loop Header: Depth=2 movsd (%rsi,%r8,8), %xmm0 # xmm0 = mem[0],zero movsd %xmm0, (%rdi,%r8,8) incq %r8 cmpq %r8, %rax jne .LBB6_24 # %bb.25: # %._crit_edge143 # in Loop: Header=BB6_23 Depth=1 incq %rdx addl %ebx, %ecx cmpq %rax, %rdx jne .LBB6_23 .LBB6_26: # %.preheader138 testl %ebx, %ebx jle .LBB6_38 # %bb.27: # %.preheader137.lr.ph movl %ebx, %eax xorl %ecx, %ecx movsd .LCPI6_2(%rip), %xmm0 # xmm0 = mem[0],zero jmp .LBB6_28 .p2align 4, 0x90 .LBB6_37: # %._crit_edge149 # in Loop: Header=BB6_28 Depth=1 incq %rcx cmpq %rax, %rcx je .LBB6_38 .LBB6_28: # %.preheader137 # =>This Loop Header: Depth=1 # Child Loop BB6_29 Depth 2 # Child Loop BB6_30 Depth 3 movq (%rbp,%rcx,8), %rdx xorl %esi, %esi jmp .LBB6_29 .p2align 4, 0x90 .LBB6_36: # %._crit_edge147 # in Loop: Header=BB6_29 Depth=2 incq %rsi cmpq %rax, %rsi je .LBB6_37 .LBB6_29: # %.preheader # Parent Loop BB6_28 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB6_30 Depth 3 xorl %edi, %edi jmp .LBB6_30 .p2align 4, 0x90 .LBB6_35: # in Loop: Header=BB6_30 Depth=3 movq (%r13,%rdi,8), %r8 movsd %xmm1, (%r8,%rsi,8) incq %rdi cmpq %rdi, %rax je .LBB6_36 .LBB6_30: # Parent Loop BB6_28 Depth=1 # Parent Loop BB6_29 Depth=2 # => This Inner Loop Header: Depth=3 xorpd %xmm1, %xmm1 cmpq %rdi, %rcx jb .LBB6_32 # %bb.31: # in Loop: Header=BB6_30 Depth=3 movq (%r12,%rcx,8), %r8 movsd (%r8,%rdi,8), %xmm1 # xmm1 = mem[0],zero .LBB6_32: # in Loop: Header=BB6_30 Depth=3 movsd %xmm1, (%rdx,%rdi,8) movapd %xmm0, %xmm1 cmpq %rdi, %rsi je .LBB6_35 # %bb.33: # in Loop: Header=BB6_30 Depth=3 xorpd %xmm1, %xmm1 jbe .LBB6_35 # %bb.34: # in Loop: Header=BB6_30 Depth=3 movq (%r12,%rdi,8), %r8 movsd (%r8,%rsi,8), %xmm1 # xmm1 = mem[0],zero jmp .LBB6_35 .LBB6_38: # %._crit_edge151 movq 144(%rsp), %rax # 8-byte Reload movq 16(%rax), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol cmpl $1, %eax jne .LBB6_40 # %bb.39: movl $.Lstr.1, %edi callq puts@PLT movq 24(%rsp), %rdi # 8-byte Reload movl %ebx, %esi callq _Z11printMatrixPdi movl $.Lstr.4, %edi callq puts@PLT movl $.Lstr.3, %edi callq puts@PLT movq %rbp, %rdi movl %ebx, %esi callq _Z7print2DPPdi movl $.Lstr.4, %edi callq puts@PLT movl $.Lstr.5, %edi callq puts@PLT movq %r13, %rdi movl %ebx, %esi callq _Z7print2DPPdi .LBB6_40: movq 16(%rsp), %rdi callq hipFree movq %r14, %rdi callq hipFree movq 24(%rsp), %rdi # 8-byte Reload callq _ZdaPv movq %r14, %rdi callq _ZdaPv xorl %eax, %eax addq $152, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB6_41: .cfi_def_cfa_offset 208 callq _ZSt16__throw_bad_castv .Lfunc_end6: .size main, .Lfunc_end6-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB7_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB7_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z10scaleIndexPdii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z4elimPdiii, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end7: .size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB8_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB8_2: retq .Lfunc_end8: .size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor .cfi_endproc # -- End function .type _Z10scaleIndexPdii,@object # @_Z10scaleIndexPdii .section .rodata,"a",@progbits .globl _Z10scaleIndexPdii .p2align 3, 0x0 _Z10scaleIndexPdii: .quad _Z25__device_stub__scaleIndexPdii .size _Z10scaleIndexPdii, 8 .type _Z4elimPdiii,@object # @_Z4elimPdiii .globl _Z4elimPdiii .p2align 3, 0x0 _Z4elimPdiii: .quad _Z19__device_stub__elimPdiii .size _Z4elimPdiii, 8 .type .L.str.1,@object # @.str.1 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.1: .asciz "For %u x %u Matrix\n" .size .L.str.1, 20 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Runtime for LU Decomposition is: " .size .L.str.2, 34 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z10scaleIndexPdii" .size .L__unnamed_1, 19 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z4elimPdiii" .size .L__unnamed_2, 13 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~" .size .Lstr, 81 .type .Lstr.1,@object # @str.1 .Lstr.1: .asciz "Matrix 'A' is:" .size .Lstr.1, 15 .type .Lstr.3,@object # @str.3 .Lstr.3: .asciz "Matrix 'L' is:" .size .Lstr.3, 15 .type .Lstr.4,@object # @str.4 .Lstr.4: .asciz "~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~" .size .Lstr.4, 71 .type .Lstr.5,@object # @str.5 .Lstr.5: .asciz "Matrix 'U' is: " .size .Lstr.5, 16 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z25__device_stub__scaleIndexPdii .addrsig_sym _Z19__device_stub__elimPdiii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z10scaleIndexPdii .addrsig_sym _Z4elimPdiii .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include "includes.h" __global__ void _kpolymap32(int n, float *k, float c, float d) { int i = threadIdx.x + blockIdx.x * blockDim.x; while (i < n) { k[i] = pow(k[i] + c, d); i += blockDim.x * gridDim.x; } }
code for sm_80 Function : _Z11_kpolymap32iPfff .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */ /* 0x000e280000002500 */ /*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */ /* 0x001fca00078e0203 */ /*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */ /* 0x000fda0003f06270 */ /*0050*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0060*/ MOV R2, c[0x0][0x174] ; /* 0x00005d0000027a02 */ /* 0x000fe20000000f00 */ /*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe20000000a00 */ /*0080*/ FSETP.NEU.AND P0, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0b */ /* 0x000fc60003f0d000 */ /*0090*/ FMUL R2, R2, 0.5 ; /* 0x3f00000002027820 */ /* 0x000fcc0000400000 */ /*00a0*/ FRND.TRUNC R2, R2 ; /* 0x0000000200027307 */ /* 0x000e24000020d000 */ /*00b0*/ FADD R4, R2, R2 ; /* 0x0000000202047221 */ /* 0x001fe40000000000 */ /*00c0*/ @!P0 BRA 0x720 ; /* 0x0000065000008947 */ /* 0x000fea0003800000 */ /*00d0*/ FADD R4, -R4, c[0x0][0x174] ; /* 0x00005d0004047621 */ /* 0x000fe40000000100 */ /*00e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */ /* 0x001fd400000001ff */ /*00f0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */ /* 0x000fca00078e0203 */ /*0100*/ LDG.E R14, [R2.64] ; /* 0x00000004020e7981 */ /* 0x000ea2000c1e1900 */ /*0110*/ MOV R15, 0x3a2c32e4 ; /* 0x3a2c32e4000f7802 */ /* 0x000fe20000000f00 */ /*0120*/ BSSY B0, 0x6f0 ; /* 0x000005c000007945 */ /* 0x000fe20003800000 */ /*0130*/ FADD R5, R14, c[0x0][0x170] ; /* 0x00005c000e057621 */ /* 0x004fc80000000000 */ /*0140*/ FMUL R6, |R5|.reuse, 16777216 ; /* 0x4b80000005067820 */ /* 0x040fe20000400200 */ /*0150*/ FSETP.GEU.AND P0, PT, |R5|.reuse, 1.175494350822287508e-38, PT ; /* 0x008000000500780b */ /* 0x040fe40003f0e200 */ /*0160*/ FSETP.NEU.AND P3, PT, R5, 1, PT ; /* 0x3f8000000500780b */ /* 0x000fe40003f6d000 */ /*0170*/ FSEL R6, R6, |R5|, !P0 ; /* 0x4000000506067208 */ /* 0x000fc80004000000 */ /*0180*/ IADD3 R7, R6, -0x3f3504f3, RZ ; /* 0xc0cafb0d06077810 */ /* 0x000fc80007ffe0ff */ /*0190*/ LOP3.LUT R7, R7, 0xff800000, RZ, 0xc0, !PT ; /* 0xff80000007077812 */ /* 0x000fc800078ec0ff */ /*01a0*/ IADD3 R6, R6, -R7, RZ ; /* 0x8000000706067210 */ /* 0x000fe40007ffe0ff */ /*01b0*/ I2F R7, R7 ; /* 0x0000000700077306 */ /* 0x000fe60000201400 */ /*01c0*/ FADD R10, R6.reuse, 1 ; /* 0x3f800000060a7421 */ /* 0x040fe40000000000 */ /*01d0*/ FADD R8, R6, -1 ; /* 0xbf80000006087421 */ /* 0x000fe20000000000 */ /*01e0*/ FSEL R6, RZ, -24, P0 ; /* 0xc1c00000ff067808 */ /* 0x000fc60000000000 */ /*01f0*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */ /* 0x000e220000001000 */ /*0200*/ FADD R9, R8, R8 ; /* 0x0000000808097221 */ /* 0x000fc80000000000 */ /*0210*/ FMUL R11, R10, R9 ; /* 0x000000090a0b7220 */ /* 0x001fe40000400000 */ /*0220*/ FFMA R9, R7, 1.1920928955078125e-07, R6 ; /* 0x3400000007097823 */ /* 0x000fe40000000006 */ /*0230*/ FADD R13, R8, -R11 ; /* 0x8000000b080d7221 */ /* 0x000fe40000000000 */ /*0240*/ FMUL R12, R11.reuse, R11 ; /* 0x0000000b0b0c7220 */ /* 0x040fe40000400000 */ /*0250*/ FFMA R6, R11, 1.4426950216293334961, R9 ; /* 0x3fb8aa3b0b067823 */ /* 0x000fe40000000009 */ /*0260*/ FADD R13, R13, R13 ; /* 0x0000000d0d0d7221 */ /* 0x000fc40000000000 */ /*0270*/ FFMA R7, R12, R15, 0.0032181653659790754318 ; /* 0x3b52e7db0c077423 */ /* 0x000fe4000000000f */ /*0280*/ FADD R16, R9, -R6 ; /* 0x8000000609107221 */ /* 0x000fe40000000000 */ /*0290*/ FFMA R13, R8, -R11, R13 ; /* 0x8000000b080d7223 */ /* 0x000fe4000000000d */ /*02a0*/ FFMA R7, R12, R7, 0.018033718690276145935 ; /* 0x3c93bb730c077423 */ /* 0x000fe40000000007 */ /*02b0*/ FFMA R16, R11, 1.4426950216293334961, R16 ; /* 0x3fb8aa3b0b107823 */ /* 0x000fe40000000010 */ /*02c0*/ FMUL R13, R10, R13 ; /* 0x0000000d0a0d7220 */ /* 0x000fc40000400000 */ /*02d0*/ FFMA R7, R12.reuse, R7, 0.12022458761930465698 ; /* 0x3df6384f0c077423 */ /* 0x040fe40000000007 */ /*02e0*/ FFMA R16, R13, 1.4426950216293334961, R16 ; /* 0x3fb8aa3b0d107823 */ /* 0x000fe40000000010 */ /*02f0*/ FMUL R12, R12, R7 ; /* 0x000000070c0c7220 */ /* 0x000fe40000400000 */ /*0300*/ FFMA R16, R11, 1.9251366722983220825e-08, R16 ; /* 0x32a55e340b107823 */ /* 0x000fe40000000010 */ /*0310*/ FMUL R7, R12, 3 ; /* 0x404000000c077820 */ /* 0x000fc80000400000 */ /*0320*/ FFMA R7, R13, R7, R16 ; /* 0x000000070d077223 */ /* 0x000fe20000000010 */ /*0330*/ MOV R13, c[0x0][0x0] ; /* 0x00000000000d7a02 */ /* 0x000fc60000000f00 */ /*0340*/ FFMA R11, R11, R12, R7 ; /* 0x0000000c0b0b7223 */ /* 0x000fe40000000007 */ /*0350*/ IMAD R0, R13, c[0x0][0xc], R0 ; /* 0x000003000d007a24 */ /* 0x000fe400078e0200 */ /*0360*/ FADD R8, R6, R11 ; /* 0x0000000b06087221 */ /* 0x000fc60000000000 */ /*0370*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */ /* 0x000fe20003f26270 */ /*0380*/ FMUL R7, R8, c[0x0][0x174] ; /* 0x00005d0008077a20 */ /* 0x000fe40000400000 */ /*0390*/ FADD R6, -R6, R8 ; /* 0x0000000806067221 */ /* 0x000fe40000000100 */ /*03a0*/ FRND R10, R7 ; /* 0x00000007000a7307 */ /* 0x000e220000201000 */ /*03b0*/ FFMA R9, R8, c[0x0][0x174], -R7 ; /* 0x00005d0008097a23 */ /* 0x000fe20000000807 */ /*03c0*/ FSETP.GEU.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720b */ /* 0x000fe20003f4e000 */ /*03d0*/ FADD R6, R11, -R6 ; /* 0x800000060b067221 */ /* 0x000fe20000000000 */ /*03e0*/ HFMA2.MMA R11, -RZ, RZ, 0.64013671875, -15.109375 ; /* 0x391fcb8eff0b7435 */ /* 0x000fc600000001ff */ /*03f0*/ FFMA R6, R6, c[0x0][0x174], R9 ; /* 0x00005d0006067a23 */ /* 0x000fe20000000009 */ /*0400*/ F2I.NTZ R8, R7 ; /* 0x0000000700087305 */ /* 0x0002a20000203100 */ /*0410*/ FADD R9, R7, -R10 ; /* 0x8000000a07097221 */ /* 0x001fe20000000000 */ /*0420*/ FSETP.GT.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720b */ /* 0x000fc60003f04000 */ /*0430*/ FADD R6, R6, R9 ; /* 0x0000000906067221 */ /* 0x000fc80000000000 */ /*0440*/ FFMA R9, R6.reuse, R11, 0.0013391353422775864601 ; /* 0x3aaf85ed06097423 */ /* 0x040fe2000000000b */ /*0450*/ SEL R11, RZ, 0x83000000, P0 ; /* 0x83000000ff0b7807 */ /* 0x000fe40000000000 */ /*0460*/ FSETP.GT.AND P0, PT, |R7|, 152, PT ; /* 0x431800000700780b */ /* 0x000fe20003f04200 */ /*0470*/ FFMA R9, R6, R9, 0.0096188392490148544312 ; /* 0x3c1d985606097423 */ /* 0x000fe20000000009 */ /*0480*/ HFMA2.MMA R7, -RZ, RZ, 1.875, 0 ; /* 0x3f800000ff077435 */ /* 0x002fc600000001ff */ /*0490*/ FFMA R9, R6, R9, 0.055503588169813156128 ; /* 0x3d6357bb06097423 */ /* 0x000fc80000000009 */ /*04a0*/ FFMA R9, R6, R9, 0.24022644758224487305 ; /* 0x3e75fdec06097423 */ /* 0x000fc80000000009 */ /*04b0*/ FFMA R9, R6, R9, 0.69314718246459960938 ; /* 0x3f31721806097423 */ /* 0x000fc80000000009 */ /*04c0*/ FFMA R9, R6, R9, 1 ; /* 0x3f80000006097423 */ /* 0x000fe20000000009 */ /*04d0*/ IADD3 R6, R11, 0x7f000000, RZ ; /* 0x7f0000000b067810 */ /* 0x000fe40007ffe0ff */ /*04e0*/ LEA R11, R8, -R11, 0x17 ; /* 0x8000000b080b7211 */ /* 0x004fc600078eb8ff */ /*04f0*/ FMUL R6, R9, R6 ; /* 0x0000000609067220 */ /* 0x000fc80000400000 */ /*0500*/ FMUL R6, R6, R11 ; /* 0x0000000b06067220 */ /* 0x000fe20000400000 */ /*0510*/ @P0 FSEL R6, RZ, +INF , !P2 ; /* 0x7f800000ff060808 */ /* 0x000fe20005000000 */ /*0520*/ @!P3 BRA 0x6e0 ; /* 0x000001b00000b947 */ /* 0x000fea0003800000 */ /*0530*/ MOV R8, c[0x0][0x174] ; /* 0x00005d0000087a02 */ /* 0x000fc80000000f00 */ /*0540*/ FSETP.GTU.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */ /* 0x000fc80003f0c200 */ /*0550*/ FSETP.GTU.OR P0, PT, |R5|, +INF , P0 ; /* 0x7f8000000500780b */ /* 0x000fda000070c600 */ /*0560*/ @P0 BRA 0x6d0 ; /* 0x0000016000000947 */ /* 0x000fea0003800000 */ /*0570*/ FSETP.NEU.AND P0, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */ /* 0x000fc80003f0d200 */ /*0580*/ FSETP.EQ.OR P0, PT, R5, RZ, !P0 ; /* 0x000000ff0500720b */ /* 0x000fda0004702400 */ /*0590*/ @P0 BRA 0x660 ; /* 0x000000c000000947 */ /* 0x000fea0003800000 */ /*05a0*/ FSETP.NEU.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */ /* 0x000fe40003f0d200 */ /*05b0*/ FSETP.EQ.AND P2, PT, R5, -1, PT ; /* 0xbf8000000500780b */ /* 0x000fda0003f42000 */ /*05c0*/ @!P0 BRA P2, 0x6e0 ; /* 0x0000011000008947 */ /* 0x000fea0001000000 */ /*05d0*/ FSETP.GEU.AND P0, PT, R14, -c[0x0][0x170], PT ; /* 0x80005c000e007a0b */ /* 0x000fe40003f0e000 */ /*05e0*/ MOV R7, R6 ; /* 0x0000000600077202 */ /* 0x000fd60000000f00 */ /*05f0*/ @P0 BRA 0x6e0 ; /* 0x000000e000000947 */ /* 0x000fea0003800000 */ /*0600*/ FRND.FLOOR R5, c[0x0][0x174] ; /* 0x00005d0000057b07 */ /* 0x000e220000205000 */ /*0610*/ FSETP.NEU.AND P2, PT, |R4|, 1, PT ; /* 0x3f8000000400780b */ /* 0x000fc80003f4d200 */ /*0620*/ FSEL R7, -R6, R6, !P2 ; /* 0x0000000606077208 */ /* 0x000fe40005000100 */ /*0630*/ FSETP.NEU.AND P0, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0b */ /* 0x001fc80003f0d000 */ /*0640*/ FSEL R7, R7, +QNAN , !P0 ; /* 0x7fffffff07077808 */ /* 0x000fe20004000000 */ /*0650*/ BRA 0x6e0 ; /* 0x0000008000007947 */ /* 0x000fea0003800000 */ /*0660*/ FSETP.LEU.AND P0, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0b */ /* 0x000fe20003f0b000 */ /*0670*/ FADD R5, R5, R5 ; /* 0x0000000505057221 */ /* 0x000fe20000000000 */ /*0680*/ FSETP.NEU.AND P2, PT, |R4|, 1, PT ; /* 0x3f8000000400780b */ /* 0x000fd60003f4d200 */ /*0690*/ @!P0 LOP3.LUT R5, R5, 0x7f800000, RZ, 0x3c, !PT ; /* 0x7f80000005058812 */ /* 0x000fc800078e3cff */ /*06a0*/ @P2 LOP3.LUT R5, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05052812 */ /* 0x000fc800078ec0ff */ /*06b0*/ MOV R7, R5 ; /* 0x0000000500077202 */ /* 0x000fe20000000f00 */ /*06c0*/ BRA 0x6e0 ; /* 0x0000001000007947 */ /* 0x000fea0003800000 */ /*06d0*/ FADD R7, R5, c[0x0][0x174] ; /* 0x00005d0005077621 */ /* 0x000fe40000000000 */ /*06e0*/ BSYNC B0 ; /* 0x0000000000007941 */ /* 0x000fea0003800000 */ /*06f0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */ /* 0x0001e2000c101904 */ /*0700*/ @!P1 BRA 0xe0 ; /* 0xfffff9d000009947 */ /* 0x000fea000383ffff */ /*0710*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0720*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */ /* 0x000fe200000001ff */ /*0730*/ MOV R7, 0x3f800000 ; /* 0x3f80000000077802 */ /* 0x000fe40000000f00 */ /*0740*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */ /* 0x000fce0000000f00 */ /*0750*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */ /* 0x000fc800078e0205 */ /*0760*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */ /* 0x000fe200078e0200 */ /*0770*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */ /* 0x0001e8000c101904 */ /*0780*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */ /* 0x000fda0003f06270 */ /*0790*/ @!P0 BRA 0x750 ; /* 0xffffffb000008947 */ /* 0x001fea000383ffff */ /*07a0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*07b0*/ BRA 0x7b0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*07c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*07d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*07e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*07f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0800*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0810*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0820*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0830*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0840*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0850*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0860*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0870*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include "includes.h" __global__ void _kpolymap32(int n, float *k, float c, float d) { int i = threadIdx.x + blockIdx.x * blockDim.x; while (i < n) { k[i] = pow(k[i] + c, d); i += blockDim.x * gridDim.x; } }
.file "tmpxft_001320c4_00000000-6__kpolymap32.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z34__device_stub__Z11_kpolymap32iPfffiPfff .type _Z34__device_stub__Z11_kpolymap32iPfffiPfff, @function _Z34__device_stub__Z11_kpolymap32iPfffiPfff: .LFB2051: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movl %edi, 28(%rsp) movq %rsi, 16(%rsp) movss %xmm0, 24(%rsp) movss %xmm1, 12(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 28(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 24(%rsp), %rax movq %rax, 112(%rsp) leaq 12(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z11_kpolymap32iPfff(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z34__device_stub__Z11_kpolymap32iPfffiPfff, .-_Z34__device_stub__Z11_kpolymap32iPfffiPfff .globl _Z11_kpolymap32iPfff .type _Z11_kpolymap32iPfff, @function _Z11_kpolymap32iPfff: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z34__device_stub__Z11_kpolymap32iPfffiPfff addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z11_kpolymap32iPfff, .-_Z11_kpolymap32iPfff .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z11_kpolymap32iPfff" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z11_kpolymap32iPfff(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include "includes.h" __global__ void _kpolymap32(int n, float *k, float c, float d) { int i = threadIdx.x + blockIdx.x * blockDim.x; while (i < n) { k[i] = pow(k[i] + c, d); i += blockDim.x * gridDim.x; } }
#include <hip/hip_runtime.h> #include "includes.h" __global__ void _kpolymap32(int n, float *k, float c, float d) { int i = threadIdx.x + blockIdx.x * blockDim.x; while (i < n) { k[i] = pow(k[i] + c, d); i += blockDim.x * gridDim.x; } }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void _kpolymap32(int n, float *k, float c, float d) { int i = threadIdx.x + blockIdx.x * blockDim.x; while (i < n) { k[i] = pow(k[i] + c, d); i += blockDim.x * gridDim.x; } }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z11_kpolymap32iPfff .globl _Z11_kpolymap32iPfff .p2align 8 .type _Z11_kpolymap32iPfff,@function _Z11_kpolymap32iPfff: s_clause 0x1 s_load_b32 s4, s[0:1], 0x24 s_load_b32 s8, s[0:1], 0x0 s_add_u32 s2, s0, 24 s_addc_u32 s3, s1, 0 s_waitcnt lgkmcnt(0) s_and_b32 s9, s4, 0xffff s_mov_b32 s4, exec_lo v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1] s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_i32_e64 s8, v1 s_cbranch_execz .LBB0_3 s_load_b32 s2, s[2:3], 0x0 s_load_b128 s[4:7], s[0:1], 0x8 s_mov_b32 s3, 0 s_mov_b32 s10, 0x3e76c4e1 s_waitcnt lgkmcnt(0) s_mul_i32 s9, s2, s9 .LBB0_2: v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_lshlrev_b64 v[2:3], 2, v[1:2] v_add_nc_u32_e32 v1, s9, v1 v_add_co_u32 v2, vcc_lo, s4, v2 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo global_load_b32 v0, v[2:3], off s_waitcnt vmcnt(0) v_add_f32_e32 v0, s6, v0 v_cmp_neq_f32_e32 vcc_lo, 1.0, v0 v_cndmask_b32_e64 v4, 1.0, s7, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_cmp_neq_f32_e32 vcc_lo, 0, v4 v_cmp_neq_f32_e64 s11, v4, |v4| v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo v_frexp_mant_f32_e64 v5, |v0| s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v5 v_cndmask_b32_e64 v6, 0, 1, vcc_lo v_ldexp_f32 v5, v5, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f32_e32 v6, 1.0, v5 v_add_f32_e32 v8, -1.0, v5 v_add_f32_e32 v10, -1.0, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_sub_f32_e32 v5, v5, v10 v_rcp_f32_e32 v7, v6 s_waitcnt_depctr 0xfff v_mul_f32_e32 v9, v8, v7 v_mul_f32_e32 v11, v6, v9 v_cmp_lt_f32_e64 s12, |v0|, 1.0 v_cmp_eq_f32_e64 s2, 0, v0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f32 v6, v9, v6, -v11 s_xor_b32 s11, s11, s12 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v6, v9, v5 v_add_f32_e32 v5, v11, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_sub_f32 v10, v8, v5 :: v_dual_sub_f32 v11, v5, v11 v_sub_f32_e32 v6, v11, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_f32_e32 v8, v8, v10 v_sub_f32_e32 v5, v8, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v5, v6, v5 v_add_f32_e32 v5, v10, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f32_e32 v5, v7, v5 v_add_f32_e32 v6, v9, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mul_f32_e32 v8, v6, v6 v_sub_f32_e32 v7, v6, v9 v_sub_f32_e32 v5, v5, v7 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f32 v7, v6, v6, -v8 v_add_f32_e32 v9, v5, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v7, v6, v9 v_add_f32_e32 v9, v8, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fmaak_f32 v10, s10, v9, 0x3e91f4c4 v_sub_f32_e32 v8, v9, v8 v_dual_fmaak_f32 v10, v9, v10, 0x3ecccdef :: v_dual_sub_f32 v7, v7, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f32_e32 v11, v9, v10 v_fma_f32 v8, v9, v10, -v11 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v8, v7, v10 v_add_f32_e32 v10, v11, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_sub_f32 v11, v10, v11 :: v_dual_add_f32 v12, 0x3f2aaaaa, v10 v_dual_mul_f32 v13, v6, v9 :: v_dual_sub_f32 v8, v8, v11 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f32 v14, v9, v6, -v13 v_add_f32_e32 v11, 0xbf2aaaaa, v12 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f32_e32 v8, 0x31739010, v8 v_fmac_f32_e32 v14, v9, v5 v_ldexp_f32 v5, v5, 1 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_fmac_f32_e32 v14, v7, v6 v_sub_f32_e32 v10, v10, v11 v_ldexp_f32 v6, v6, 1 v_add_f32_e32 v9, v13, v14 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v8, v8, v10 v_add_f32_e32 v7, v12, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_mul_f32_e32 v11, v9, v7 v_sub_f32_e32 v10, v12, v7 v_sub_f32_e32 v12, v9, v13 v_add_f32_e32 v8, v8, v10 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f32 v10, v9, v7, -v11 v_sub_f32_e32 v12, v14, v12 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fmac_f32_e32 v10, v9, v8 v_frexp_exp_i32_f32_e32 v8, v0 v_fmac_f32_e32 v10, v12, v7 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_subrev_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo v_add_f32_e32 v8, v11, v10 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cvt_f32_i32_e32 v7, v7 v_sub_f32_e32 v11, v8, v11 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_dual_mul_f32 v12, 0x3f317218, v7 :: v_dual_add_f32 v9, v6, v8 v_sub_f32_e32 v10, v10, v11 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f32 v11, v7, 0x3f317218, -v12 v_add_f32_e32 v5, v5, v10 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_fmac_f32 v11, 0xb102e308, v7 :: v_dual_sub_f32 v6, v9, v6 v_sub_f32_e32 v6, v8, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v5, v5, v6 v_dual_add_f32 v7, v9, v5 :: v_dual_add_f32 v6, v12, v11 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_sub_f32 v9, v7, v9 :: v_dual_add_f32 v8, v6, v7 v_dual_sub_f32 v5, v5, v9 :: v_dual_sub_f32 v10, v8, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_sub_f32_e32 v13, v8, v10 v_dual_sub_f32 v7, v7, v10 :: v_dual_sub_f32 v12, v6, v12 v_dual_sub_f32 v6, v6, v13 :: v_dual_sub_f32 v11, v11, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f32_e32 v6, v7, v6 v_add_f32_e32 v9, v11, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_sub_f32_e32 v7, v9, v11 v_add_f32_e32 v6, v9, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_sub_f32_e32 v9, v9, v7 v_sub_f32_e32 v5, v5, v7 v_dual_sub_f32 v7, v11, v9 :: v_dual_add_f32 v10, v8, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_add_f32 v5, v5, v7 :: v_dual_sub_f32 v8, v10, v8 v_sub_f32_e32 v6, v6, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v5, v5, v6 v_add_f32_e32 v6, v10, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_f32_e32 v7, v6, v10 v_dual_mul_f32 v8, v4, v6 :: v_dual_sub_f32 v5, v5, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f32 v6, v4, v6, -v8 v_cmp_class_f32_e64 vcc_lo, v8, 0x204 v_fmac_f32_e32 v6, v4, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v5, v8, v6 v_cndmask_b32_e32 v7, v5, v8, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v7 v_cndmask_b32_e64 v9, 0, 0x37000000, vcc_lo v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v7| v_dual_sub_f32 v10, v7, v9 :: v_dual_sub_f32 v5, v5, v8 v_trunc_f32_e32 v7, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_mul_f32_e32 v11, 0x3fb8aa3b, v10 v_sub_f32_e32 v5, v6, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_fma_f32 v12, v10, 0x3fb8aa3b, -v11 v_rndne_f32_e32 v13, v11 v_cndmask_b32_e32 v5, 0, v5, vcc_lo v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v10 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_dual_fmac_f32 v12, 0x32a5705f, v10 :: v_dual_sub_f32 v11, v11, v13 v_cvt_i32_f32_e32 v8, v13 v_add_f32_e32 v5, v9, v5 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v11, v11, v12 v_exp_f32_e32 v11, v11 s_waitcnt_depctr 0xfff v_ldexp_f32 v6, v11, v8 v_mul_f32_e32 v8, 0.5, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v6, 0, v6, vcc_lo v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v10 v_trunc_f32_e32 v11, v8 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v6, 0x7f800000, v6, vcc_lo v_cmp_eq_f32_e32 vcc_lo, v7, v4 v_cmp_neq_f32_e64 s0, v11, v8 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_fma_f32 v5, v6, v5, v6 v_cmp_eq_f32_e64 s1, 0x7f800000, v6 s_and_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v7, 1.0, v0, s0 v_cndmask_b32_e64 v5, v5, v6, s1 v_cmp_gt_f32_e64 s1, 0, v4 v_cndmask_b32_e64 v6, |v4|, 0, s11 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_bfi_b32 v5, 0x7fffffff, v5, v7 s_xor_b32 s1, s1, s2 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v8, 0x7f800000, 0, s1 v_cmp_eq_f32_e64 s1, |v0|, 1.0 v_cndmask_b32_e32 v7, 0x7fc00000, v5, vcc_lo v_cmp_gt_f32_e32 vcc_lo, 0, v0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v6, v6, |v0|, s1 v_cndmask_b32_e32 v5, v5, v7, vcc_lo v_cndmask_b32_e64 v7, 0, v0, s0 v_cmp_class_f32_e64 vcc_lo, v4, 0x204 v_cmp_class_f32_e64 s0, v0, 0x204 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e32 v5, v5, v6, vcc_lo v_bfi_b32 v6, 0x7fffffff, v8, v7 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) s_or_b32 vcc_lo, s2, s0 v_cmp_o_f32_e64 s0, v0, v4 v_cndmask_b32_e32 v5, v5, v6, vcc_lo v_cmp_le_i32_e32 vcc_lo, s8, v1 s_delay_alu instid0(VALU_DEP_2) v_cndmask_b32_e64 v0, 0x7fc00000, v5, s0 s_or_b32 s3, vcc_lo, s3 global_store_b32 v[2:3], v0, off s_and_not1_b32 exec_lo, exec_lo, s3 s_cbranch_execnz .LBB0_2 .LBB0_3: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z11_kpolymap32iPfff .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 15 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z11_kpolymap32iPfff, .Lfunc_end0-_Z11_kpolymap32iPfff .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 4 .value_kind: by_value - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z11_kpolymap32iPfff .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z11_kpolymap32iPfff.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 15 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void _kpolymap32(int n, float *k, float c, float d) { int i = threadIdx.x + blockIdx.x * blockDim.x; while (i < n) { k[i] = pow(k[i] + c, d); i += blockDim.x * gridDim.x; } }
.text .file "_kpolymap32.hip" .globl _Z26__device_stub___kpolymap32iPfff # -- Begin function _Z26__device_stub___kpolymap32iPfff .p2align 4, 0x90 .type _Z26__device_stub___kpolymap32iPfff,@function _Z26__device_stub___kpolymap32iPfff: # @_Z26__device_stub___kpolymap32iPfff .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movl %edi, 20(%rsp) movq %rsi, 72(%rsp) movss %xmm0, 16(%rsp) movss %xmm1, 12(%rsp) leaq 20(%rsp), %rax movq %rax, 80(%rsp) leaq 72(%rsp), %rax movq %rax, 88(%rsp) leaq 16(%rsp), %rax movq %rax, 96(%rsp) leaq 12(%rsp), %rax movq %rax, 104(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z11_kpolymap32iPfff, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z26__device_stub___kpolymap32iPfff, .Lfunc_end0-_Z26__device_stub___kpolymap32iPfff .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z11_kpolymap32iPfff, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z11_kpolymap32iPfff,@object # @_Z11_kpolymap32iPfff .section .rodata,"a",@progbits .globl _Z11_kpolymap32iPfff .p2align 3, 0x0 _Z11_kpolymap32iPfff: .quad _Z26__device_stub___kpolymap32iPfff .size _Z11_kpolymap32iPfff, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z11_kpolymap32iPfff" .size .L__unnamed_1, 21 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z26__device_stub___kpolymap32iPfff .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z11_kpolymap32iPfff .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z11_kpolymap32iPfff .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */ /* 0x000e280000002500 */ /*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */ /* 0x001fca00078e0203 */ /*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */ /* 0x000fda0003f06270 */ /*0050*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0060*/ MOV R2, c[0x0][0x174] ; /* 0x00005d0000027a02 */ /* 0x000fe20000000f00 */ /*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe20000000a00 */ /*0080*/ FSETP.NEU.AND P0, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0b */ /* 0x000fc60003f0d000 */ /*0090*/ FMUL R2, R2, 0.5 ; /* 0x3f00000002027820 */ /* 0x000fcc0000400000 */ /*00a0*/ FRND.TRUNC R2, R2 ; /* 0x0000000200027307 */ /* 0x000e24000020d000 */ /*00b0*/ FADD R4, R2, R2 ; /* 0x0000000202047221 */ /* 0x001fe40000000000 */ /*00c0*/ @!P0 BRA 0x720 ; /* 0x0000065000008947 */ /* 0x000fea0003800000 */ /*00d0*/ FADD R4, -R4, c[0x0][0x174] ; /* 0x00005d0004047621 */ /* 0x000fe40000000100 */ /*00e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */ /* 0x001fd400000001ff */ /*00f0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */ /* 0x000fca00078e0203 */ /*0100*/ LDG.E R14, [R2.64] ; /* 0x00000004020e7981 */ /* 0x000ea2000c1e1900 */ /*0110*/ MOV R15, 0x3a2c32e4 ; /* 0x3a2c32e4000f7802 */ /* 0x000fe20000000f00 */ /*0120*/ BSSY B0, 0x6f0 ; /* 0x000005c000007945 */ /* 0x000fe20003800000 */ /*0130*/ FADD R5, R14, c[0x0][0x170] ; /* 0x00005c000e057621 */ /* 0x004fc80000000000 */ /*0140*/ FMUL R6, |R5|.reuse, 16777216 ; /* 0x4b80000005067820 */ /* 0x040fe20000400200 */ /*0150*/ FSETP.GEU.AND P0, PT, |R5|.reuse, 1.175494350822287508e-38, PT ; /* 0x008000000500780b */ /* 0x040fe40003f0e200 */ /*0160*/ FSETP.NEU.AND P3, PT, R5, 1, PT ; /* 0x3f8000000500780b */ /* 0x000fe40003f6d000 */ /*0170*/ FSEL R6, R6, |R5|, !P0 ; /* 0x4000000506067208 */ /* 0x000fc80004000000 */ /*0180*/ IADD3 R7, R6, -0x3f3504f3, RZ ; /* 0xc0cafb0d06077810 */ /* 0x000fc80007ffe0ff */ /*0190*/ LOP3.LUT R7, R7, 0xff800000, RZ, 0xc0, !PT ; /* 0xff80000007077812 */ /* 0x000fc800078ec0ff */ /*01a0*/ IADD3 R6, R6, -R7, RZ ; /* 0x8000000706067210 */ /* 0x000fe40007ffe0ff */ /*01b0*/ I2F R7, R7 ; /* 0x0000000700077306 */ /* 0x000fe60000201400 */ /*01c0*/ FADD R10, R6.reuse, 1 ; /* 0x3f800000060a7421 */ /* 0x040fe40000000000 */ /*01d0*/ FADD R8, R6, -1 ; /* 0xbf80000006087421 */ /* 0x000fe20000000000 */ /*01e0*/ FSEL R6, RZ, -24, P0 ; /* 0xc1c00000ff067808 */ /* 0x000fc60000000000 */ /*01f0*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */ /* 0x000e220000001000 */ /*0200*/ FADD R9, R8, R8 ; /* 0x0000000808097221 */ /* 0x000fc80000000000 */ /*0210*/ FMUL R11, R10, R9 ; /* 0x000000090a0b7220 */ /* 0x001fe40000400000 */ /*0220*/ FFMA R9, R7, 1.1920928955078125e-07, R6 ; /* 0x3400000007097823 */ /* 0x000fe40000000006 */ /*0230*/ FADD R13, R8, -R11 ; /* 0x8000000b080d7221 */ /* 0x000fe40000000000 */ /*0240*/ FMUL R12, R11.reuse, R11 ; /* 0x0000000b0b0c7220 */ /* 0x040fe40000400000 */ /*0250*/ FFMA R6, R11, 1.4426950216293334961, R9 ; /* 0x3fb8aa3b0b067823 */ /* 0x000fe40000000009 */ /*0260*/ FADD R13, R13, R13 ; /* 0x0000000d0d0d7221 */ /* 0x000fc40000000000 */ /*0270*/ FFMA R7, R12, R15, 0.0032181653659790754318 ; /* 0x3b52e7db0c077423 */ /* 0x000fe4000000000f */ /*0280*/ FADD R16, R9, -R6 ; /* 0x8000000609107221 */ /* 0x000fe40000000000 */ /*0290*/ FFMA R13, R8, -R11, R13 ; /* 0x8000000b080d7223 */ /* 0x000fe4000000000d */ /*02a0*/ FFMA R7, R12, R7, 0.018033718690276145935 ; /* 0x3c93bb730c077423 */ /* 0x000fe40000000007 */ /*02b0*/ FFMA R16, R11, 1.4426950216293334961, R16 ; /* 0x3fb8aa3b0b107823 */ /* 0x000fe40000000010 */ /*02c0*/ FMUL R13, R10, R13 ; /* 0x0000000d0a0d7220 */ /* 0x000fc40000400000 */ /*02d0*/ FFMA R7, R12.reuse, R7, 0.12022458761930465698 ; /* 0x3df6384f0c077423 */ /* 0x040fe40000000007 */ /*02e0*/ FFMA R16, R13, 1.4426950216293334961, R16 ; /* 0x3fb8aa3b0d107823 */ /* 0x000fe40000000010 */ /*02f0*/ FMUL R12, R12, R7 ; /* 0x000000070c0c7220 */ /* 0x000fe40000400000 */ /*0300*/ FFMA R16, R11, 1.9251366722983220825e-08, R16 ; /* 0x32a55e340b107823 */ /* 0x000fe40000000010 */ /*0310*/ FMUL R7, R12, 3 ; /* 0x404000000c077820 */ /* 0x000fc80000400000 */ /*0320*/ FFMA R7, R13, R7, R16 ; /* 0x000000070d077223 */ /* 0x000fe20000000010 */ /*0330*/ MOV R13, c[0x0][0x0] ; /* 0x00000000000d7a02 */ /* 0x000fc60000000f00 */ /*0340*/ FFMA R11, R11, R12, R7 ; /* 0x0000000c0b0b7223 */ /* 0x000fe40000000007 */ /*0350*/ IMAD R0, R13, c[0x0][0xc], R0 ; /* 0x000003000d007a24 */ /* 0x000fe400078e0200 */ /*0360*/ FADD R8, R6, R11 ; /* 0x0000000b06087221 */ /* 0x000fc60000000000 */ /*0370*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */ /* 0x000fe20003f26270 */ /*0380*/ FMUL R7, R8, c[0x0][0x174] ; /* 0x00005d0008077a20 */ /* 0x000fe40000400000 */ /*0390*/ FADD R6, -R6, R8 ; /* 0x0000000806067221 */ /* 0x000fe40000000100 */ /*03a0*/ FRND R10, R7 ; /* 0x00000007000a7307 */ /* 0x000e220000201000 */ /*03b0*/ FFMA R9, R8, c[0x0][0x174], -R7 ; /* 0x00005d0008097a23 */ /* 0x000fe20000000807 */ /*03c0*/ FSETP.GEU.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720b */ /* 0x000fe20003f4e000 */ /*03d0*/ FADD R6, R11, -R6 ; /* 0x800000060b067221 */ /* 0x000fe20000000000 */ /*03e0*/ HFMA2.MMA R11, -RZ, RZ, 0.64013671875, -15.109375 ; /* 0x391fcb8eff0b7435 */ /* 0x000fc600000001ff */ /*03f0*/ FFMA R6, R6, c[0x0][0x174], R9 ; /* 0x00005d0006067a23 */ /* 0x000fe20000000009 */ /*0400*/ F2I.NTZ R8, R7 ; /* 0x0000000700087305 */ /* 0x0002a20000203100 */ /*0410*/ FADD R9, R7, -R10 ; /* 0x8000000a07097221 */ /* 0x001fe20000000000 */ /*0420*/ FSETP.GT.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720b */ /* 0x000fc60003f04000 */ /*0430*/ FADD R6, R6, R9 ; /* 0x0000000906067221 */ /* 0x000fc80000000000 */ /*0440*/ FFMA R9, R6.reuse, R11, 0.0013391353422775864601 ; /* 0x3aaf85ed06097423 */ /* 0x040fe2000000000b */ /*0450*/ SEL R11, RZ, 0x83000000, P0 ; /* 0x83000000ff0b7807 */ /* 0x000fe40000000000 */ /*0460*/ FSETP.GT.AND P0, PT, |R7|, 152, PT ; /* 0x431800000700780b */ /* 0x000fe20003f04200 */ /*0470*/ FFMA R9, R6, R9, 0.0096188392490148544312 ; /* 0x3c1d985606097423 */ /* 0x000fe20000000009 */ /*0480*/ HFMA2.MMA R7, -RZ, RZ, 1.875, 0 ; /* 0x3f800000ff077435 */ /* 0x002fc600000001ff */ /*0490*/ FFMA R9, R6, R9, 0.055503588169813156128 ; /* 0x3d6357bb06097423 */ /* 0x000fc80000000009 */ /*04a0*/ FFMA R9, R6, R9, 0.24022644758224487305 ; /* 0x3e75fdec06097423 */ /* 0x000fc80000000009 */ /*04b0*/ FFMA R9, R6, R9, 0.69314718246459960938 ; /* 0x3f31721806097423 */ /* 0x000fc80000000009 */ /*04c0*/ FFMA R9, R6, R9, 1 ; /* 0x3f80000006097423 */ /* 0x000fe20000000009 */ /*04d0*/ IADD3 R6, R11, 0x7f000000, RZ ; /* 0x7f0000000b067810 */ /* 0x000fe40007ffe0ff */ /*04e0*/ LEA R11, R8, -R11, 0x17 ; /* 0x8000000b080b7211 */ /* 0x004fc600078eb8ff */ /*04f0*/ FMUL R6, R9, R6 ; /* 0x0000000609067220 */ /* 0x000fc80000400000 */ /*0500*/ FMUL R6, R6, R11 ; /* 0x0000000b06067220 */ /* 0x000fe20000400000 */ /*0510*/ @P0 FSEL R6, RZ, +INF , !P2 ; /* 0x7f800000ff060808 */ /* 0x000fe20005000000 */ /*0520*/ @!P3 BRA 0x6e0 ; /* 0x000001b00000b947 */ /* 0x000fea0003800000 */ /*0530*/ MOV R8, c[0x0][0x174] ; /* 0x00005d0000087a02 */ /* 0x000fc80000000f00 */ /*0540*/ FSETP.GTU.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */ /* 0x000fc80003f0c200 */ /*0550*/ FSETP.GTU.OR P0, PT, |R5|, +INF , P0 ; /* 0x7f8000000500780b */ /* 0x000fda000070c600 */ /*0560*/ @P0 BRA 0x6d0 ; /* 0x0000016000000947 */ /* 0x000fea0003800000 */ /*0570*/ FSETP.NEU.AND P0, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */ /* 0x000fc80003f0d200 */ /*0580*/ FSETP.EQ.OR P0, PT, R5, RZ, !P0 ; /* 0x000000ff0500720b */ /* 0x000fda0004702400 */ /*0590*/ @P0 BRA 0x660 ; /* 0x000000c000000947 */ /* 0x000fea0003800000 */ /*05a0*/ FSETP.NEU.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */ /* 0x000fe40003f0d200 */ /*05b0*/ FSETP.EQ.AND P2, PT, R5, -1, PT ; /* 0xbf8000000500780b */ /* 0x000fda0003f42000 */ /*05c0*/ @!P0 BRA P2, 0x6e0 ; /* 0x0000011000008947 */ /* 0x000fea0001000000 */ /*05d0*/ FSETP.GEU.AND P0, PT, R14, -c[0x0][0x170], PT ; /* 0x80005c000e007a0b */ /* 0x000fe40003f0e000 */ /*05e0*/ MOV R7, R6 ; /* 0x0000000600077202 */ /* 0x000fd60000000f00 */ /*05f0*/ @P0 BRA 0x6e0 ; /* 0x000000e000000947 */ /* 0x000fea0003800000 */ /*0600*/ FRND.FLOOR R5, c[0x0][0x174] ; /* 0x00005d0000057b07 */ /* 0x000e220000205000 */ /*0610*/ FSETP.NEU.AND P2, PT, |R4|, 1, PT ; /* 0x3f8000000400780b */ /* 0x000fc80003f4d200 */ /*0620*/ FSEL R7, -R6, R6, !P2 ; /* 0x0000000606077208 */ /* 0x000fe40005000100 */ /*0630*/ FSETP.NEU.AND P0, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0b */ /* 0x001fc80003f0d000 */ /*0640*/ FSEL R7, R7, +QNAN , !P0 ; /* 0x7fffffff07077808 */ /* 0x000fe20004000000 */ /*0650*/ BRA 0x6e0 ; /* 0x0000008000007947 */ /* 0x000fea0003800000 */ /*0660*/ FSETP.LEU.AND P0, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0b */ /* 0x000fe20003f0b000 */ /*0670*/ FADD R5, R5, R5 ; /* 0x0000000505057221 */ /* 0x000fe20000000000 */ /*0680*/ FSETP.NEU.AND P2, PT, |R4|, 1, PT ; /* 0x3f8000000400780b */ /* 0x000fd60003f4d200 */ /*0690*/ @!P0 LOP3.LUT R5, R5, 0x7f800000, RZ, 0x3c, !PT ; /* 0x7f80000005058812 */ /* 0x000fc800078e3cff */ /*06a0*/ @P2 LOP3.LUT R5, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05052812 */ /* 0x000fc800078ec0ff */ /*06b0*/ MOV R7, R5 ; /* 0x0000000500077202 */ /* 0x000fe20000000f00 */ /*06c0*/ BRA 0x6e0 ; /* 0x0000001000007947 */ /* 0x000fea0003800000 */ /*06d0*/ FADD R7, R5, c[0x0][0x174] ; /* 0x00005d0005077621 */ /* 0x000fe40000000000 */ /*06e0*/ BSYNC B0 ; /* 0x0000000000007941 */ /* 0x000fea0003800000 */ /*06f0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */ /* 0x0001e2000c101904 */ /*0700*/ @!P1 BRA 0xe0 ; /* 0xfffff9d000009947 */ /* 0x000fea000383ffff */ /*0710*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0720*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */ /* 0x000fe200000001ff */ /*0730*/ MOV R7, 0x3f800000 ; /* 0x3f80000000077802 */ /* 0x000fe40000000f00 */ /*0740*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */ /* 0x000fce0000000f00 */ /*0750*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */ /* 0x000fc800078e0205 */ /*0760*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */ /* 0x000fe200078e0200 */ /*0770*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */ /* 0x0001e8000c101904 */ /*0780*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */ /* 0x000fda0003f06270 */ /*0790*/ @!P0 BRA 0x750 ; /* 0xffffffb000008947 */ /* 0x001fea000383ffff */ /*07a0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*07b0*/ BRA 0x7b0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*07c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*07d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*07e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*07f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0800*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0810*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0820*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0830*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0840*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0850*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0860*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0870*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z11_kpolymap32iPfff .globl _Z11_kpolymap32iPfff .p2align 8 .type _Z11_kpolymap32iPfff,@function _Z11_kpolymap32iPfff: s_clause 0x1 s_load_b32 s4, s[0:1], 0x24 s_load_b32 s8, s[0:1], 0x0 s_add_u32 s2, s0, 24 s_addc_u32 s3, s1, 0 s_waitcnt lgkmcnt(0) s_and_b32 s9, s4, 0xffff s_mov_b32 s4, exec_lo v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1] s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_i32_e64 s8, v1 s_cbranch_execz .LBB0_3 s_load_b32 s2, s[2:3], 0x0 s_load_b128 s[4:7], s[0:1], 0x8 s_mov_b32 s3, 0 s_mov_b32 s10, 0x3e76c4e1 s_waitcnt lgkmcnt(0) s_mul_i32 s9, s2, s9 .LBB0_2: v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_lshlrev_b64 v[2:3], 2, v[1:2] v_add_nc_u32_e32 v1, s9, v1 v_add_co_u32 v2, vcc_lo, s4, v2 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo global_load_b32 v0, v[2:3], off s_waitcnt vmcnt(0) v_add_f32_e32 v0, s6, v0 v_cmp_neq_f32_e32 vcc_lo, 1.0, v0 v_cndmask_b32_e64 v4, 1.0, s7, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_cmp_neq_f32_e32 vcc_lo, 0, v4 v_cmp_neq_f32_e64 s11, v4, |v4| v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo v_frexp_mant_f32_e64 v5, |v0| s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v5 v_cndmask_b32_e64 v6, 0, 1, vcc_lo v_ldexp_f32 v5, v5, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_f32_e32 v6, 1.0, v5 v_add_f32_e32 v8, -1.0, v5 v_add_f32_e32 v10, -1.0, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_sub_f32_e32 v5, v5, v10 v_rcp_f32_e32 v7, v6 s_waitcnt_depctr 0xfff v_mul_f32_e32 v9, v8, v7 v_mul_f32_e32 v11, v6, v9 v_cmp_lt_f32_e64 s12, |v0|, 1.0 v_cmp_eq_f32_e64 s2, 0, v0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f32 v6, v9, v6, -v11 s_xor_b32 s11, s11, s12 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v6, v9, v5 v_add_f32_e32 v5, v11, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_sub_f32 v10, v8, v5 :: v_dual_sub_f32 v11, v5, v11 v_sub_f32_e32 v6, v11, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_f32_e32 v8, v8, v10 v_sub_f32_e32 v5, v8, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v5, v6, v5 v_add_f32_e32 v5, v10, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f32_e32 v5, v7, v5 v_add_f32_e32 v6, v9, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mul_f32_e32 v8, v6, v6 v_sub_f32_e32 v7, v6, v9 v_sub_f32_e32 v5, v5, v7 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f32 v7, v6, v6, -v8 v_add_f32_e32 v9, v5, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v7, v6, v9 v_add_f32_e32 v9, v8, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_fmaak_f32 v10, s10, v9, 0x3e91f4c4 v_sub_f32_e32 v8, v9, v8 v_dual_fmaak_f32 v10, v9, v10, 0x3ecccdef :: v_dual_sub_f32 v7, v7, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f32_e32 v11, v9, v10 v_fma_f32 v8, v9, v10, -v11 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v8, v7, v10 v_add_f32_e32 v10, v11, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_sub_f32 v11, v10, v11 :: v_dual_add_f32 v12, 0x3f2aaaaa, v10 v_dual_mul_f32 v13, v6, v9 :: v_dual_sub_f32 v8, v8, v11 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f32 v14, v9, v6, -v13 v_add_f32_e32 v11, 0xbf2aaaaa, v12 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f32_e32 v8, 0x31739010, v8 v_fmac_f32_e32 v14, v9, v5 v_ldexp_f32 v5, v5, 1 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_fmac_f32_e32 v14, v7, v6 v_sub_f32_e32 v10, v10, v11 v_ldexp_f32 v6, v6, 1 v_add_f32_e32 v9, v13, v14 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v8, v8, v10 v_add_f32_e32 v7, v12, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_mul_f32_e32 v11, v9, v7 v_sub_f32_e32 v10, v12, v7 v_sub_f32_e32 v12, v9, v13 v_add_f32_e32 v8, v8, v10 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_fma_f32 v10, v9, v7, -v11 v_sub_f32_e32 v12, v14, v12 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fmac_f32_e32 v10, v9, v8 v_frexp_exp_i32_f32_e32 v8, v0 v_fmac_f32_e32 v10, v12, v7 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_subrev_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo v_add_f32_e32 v8, v11, v10 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cvt_f32_i32_e32 v7, v7 v_sub_f32_e32 v11, v8, v11 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_dual_mul_f32 v12, 0x3f317218, v7 :: v_dual_add_f32 v9, v6, v8 v_sub_f32_e32 v10, v10, v11 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f32 v11, v7, 0x3f317218, -v12 v_add_f32_e32 v5, v5, v10 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_fmac_f32 v11, 0xb102e308, v7 :: v_dual_sub_f32 v6, v9, v6 v_sub_f32_e32 v6, v8, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v5, v5, v6 v_dual_add_f32 v7, v9, v5 :: v_dual_add_f32 v6, v12, v11 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_sub_f32 v9, v7, v9 :: v_dual_add_f32 v8, v6, v7 v_dual_sub_f32 v5, v5, v9 :: v_dual_sub_f32 v10, v8, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_sub_f32_e32 v13, v8, v10 v_dual_sub_f32 v7, v7, v10 :: v_dual_sub_f32 v12, v6, v12 v_dual_sub_f32 v6, v6, v13 :: v_dual_sub_f32 v11, v11, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_f32_e32 v6, v7, v6 v_add_f32_e32 v9, v11, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_sub_f32_e32 v7, v9, v11 v_add_f32_e32 v6, v9, v6 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_sub_f32_e32 v9, v9, v7 v_sub_f32_e32 v5, v5, v7 v_dual_sub_f32 v7, v11, v9 :: v_dual_add_f32 v10, v8, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_add_f32 v5, v5, v7 :: v_dual_sub_f32 v8, v10, v8 v_sub_f32_e32 v6, v6, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v5, v5, v6 v_add_f32_e32 v6, v10, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_f32_e32 v7, v6, v10 v_dual_mul_f32 v8, v4, v6 :: v_dual_sub_f32 v5, v5, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f32 v6, v4, v6, -v8 v_cmp_class_f32_e64 vcc_lo, v8, 0x204 v_fmac_f32_e32 v6, v4, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v5, v8, v6 v_cndmask_b32_e32 v7, v5, v8, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v7 v_cndmask_b32_e64 v9, 0, 0x37000000, vcc_lo v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v7| v_dual_sub_f32 v10, v7, v9 :: v_dual_sub_f32 v5, v5, v8 v_trunc_f32_e32 v7, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_mul_f32_e32 v11, 0x3fb8aa3b, v10 v_sub_f32_e32 v5, v6, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_fma_f32 v12, v10, 0x3fb8aa3b, -v11 v_rndne_f32_e32 v13, v11 v_cndmask_b32_e32 v5, 0, v5, vcc_lo v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v10 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_dual_fmac_f32 v12, 0x32a5705f, v10 :: v_dual_sub_f32 v11, v11, v13 v_cvt_i32_f32_e32 v8, v13 v_add_f32_e32 v5, v9, v5 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f32_e32 v11, v11, v12 v_exp_f32_e32 v11, v11 s_waitcnt_depctr 0xfff v_ldexp_f32 v6, v11, v8 v_mul_f32_e32 v8, 0.5, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v6, 0, v6, vcc_lo v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v10 v_trunc_f32_e32 v11, v8 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v6, 0x7f800000, v6, vcc_lo v_cmp_eq_f32_e32 vcc_lo, v7, v4 v_cmp_neq_f32_e64 s0, v11, v8 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_fma_f32 v5, v6, v5, v6 v_cmp_eq_f32_e64 s1, 0x7f800000, v6 s_and_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v7, 1.0, v0, s0 v_cndmask_b32_e64 v5, v5, v6, s1 v_cmp_gt_f32_e64 s1, 0, v4 v_cndmask_b32_e64 v6, |v4|, 0, s11 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_bfi_b32 v5, 0x7fffffff, v5, v7 s_xor_b32 s1, s1, s2 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v8, 0x7f800000, 0, s1 v_cmp_eq_f32_e64 s1, |v0|, 1.0 v_cndmask_b32_e32 v7, 0x7fc00000, v5, vcc_lo v_cmp_gt_f32_e32 vcc_lo, 0, v0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cndmask_b32_e64 v6, v6, |v0|, s1 v_cndmask_b32_e32 v5, v5, v7, vcc_lo v_cndmask_b32_e64 v7, 0, v0, s0 v_cmp_class_f32_e64 vcc_lo, v4, 0x204 v_cmp_class_f32_e64 s0, v0, 0x204 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e32 v5, v5, v6, vcc_lo v_bfi_b32 v6, 0x7fffffff, v8, v7 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) s_or_b32 vcc_lo, s2, s0 v_cmp_o_f32_e64 s0, v0, v4 v_cndmask_b32_e32 v5, v5, v6, vcc_lo v_cmp_le_i32_e32 vcc_lo, s8, v1 s_delay_alu instid0(VALU_DEP_2) v_cndmask_b32_e64 v0, 0x7fc00000, v5, s0 s_or_b32 s3, vcc_lo, s3 global_store_b32 v[2:3], v0, off s_and_not1_b32 exec_lo, exec_lo, s3 s_cbranch_execnz .LBB0_2 .LBB0_3: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z11_kpolymap32iPfff .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 15 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z11_kpolymap32iPfff, .Lfunc_end0-_Z11_kpolymap32iPfff .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 4 .value_kind: by_value - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z11_kpolymap32iPfff .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z11_kpolymap32iPfff.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 15 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_001320c4_00000000-6__kpolymap32.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z34__device_stub__Z11_kpolymap32iPfffiPfff .type _Z34__device_stub__Z11_kpolymap32iPfffiPfff, @function _Z34__device_stub__Z11_kpolymap32iPfffiPfff: .LFB2051: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movl %edi, 28(%rsp) movq %rsi, 16(%rsp) movss %xmm0, 24(%rsp) movss %xmm1, 12(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 28(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 24(%rsp), %rax movq %rax, 112(%rsp) leaq 12(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z11_kpolymap32iPfff(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z34__device_stub__Z11_kpolymap32iPfffiPfff, .-_Z34__device_stub__Z11_kpolymap32iPfffiPfff .globl _Z11_kpolymap32iPfff .type _Z11_kpolymap32iPfff, @function _Z11_kpolymap32iPfff: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z34__device_stub__Z11_kpolymap32iPfffiPfff addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z11_kpolymap32iPfff, .-_Z11_kpolymap32iPfff .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z11_kpolymap32iPfff" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z11_kpolymap32iPfff(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "_kpolymap32.hip" .globl _Z26__device_stub___kpolymap32iPfff # -- Begin function _Z26__device_stub___kpolymap32iPfff .p2align 4, 0x90 .type _Z26__device_stub___kpolymap32iPfff,@function _Z26__device_stub___kpolymap32iPfff: # @_Z26__device_stub___kpolymap32iPfff .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movl %edi, 20(%rsp) movq %rsi, 72(%rsp) movss %xmm0, 16(%rsp) movss %xmm1, 12(%rsp) leaq 20(%rsp), %rax movq %rax, 80(%rsp) leaq 72(%rsp), %rax movq %rax, 88(%rsp) leaq 16(%rsp), %rax movq %rax, 96(%rsp) leaq 12(%rsp), %rax movq %rax, 104(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z11_kpolymap32iPfff, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z26__device_stub___kpolymap32iPfff, .Lfunc_end0-_Z26__device_stub___kpolymap32iPfff .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z11_kpolymap32iPfff, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z11_kpolymap32iPfff,@object # @_Z11_kpolymap32iPfff .section .rodata,"a",@progbits .globl _Z11_kpolymap32iPfff .p2align 3, 0x0 _Z11_kpolymap32iPfff: .quad _Z26__device_stub___kpolymap32iPfff .size _Z11_kpolymap32iPfff, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z11_kpolymap32iPfff" .size .L__unnamed_1, 21 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z26__device_stub___kpolymap32iPfff .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z11_kpolymap32iPfff .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include "includes.h" __global__ void xvpy_f32 (float* x, float* v, float* y, int len) { int idx = blockIdx.x * blockDim.x + threadIdx.x; if (idx < len) { y[idx] += x[idx] * v[idx]; } }
code for sm_80 Function : _Z8xvpy_f32PfS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */ /* 0x000e280000002500 */ /*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */ /* 0x001fca00078e0203 */ /*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */ /* 0x000fda0003f06270 */ /*0050*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */ /* 0x000fe200000001ff */ /*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd20000000a00 */ /*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */ /* 0x000fc800078e0207 */ /*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */ /* 0x0c0fe400078e0207 */ /*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */ /* 0x000ea4000c1e1900 */ /*00b0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */ /* 0x000fe400078e0207 */ /*00c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */ /* 0x000ea8000c1e1900 */ /*00d0*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */ /* 0x000ea4000c1e1900 */ /*00e0*/ FFMA R9, R4, R3, R0 ; /* 0x0000000304097223 */ /* 0x004fca0000000000 */ /*00f0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */ /* 0x000fe2000c101904 */ /*0100*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0110*/ BRA 0x110; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0120*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0130*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include "includes.h" __global__ void xvpy_f32 (float* x, float* v, float* y, int len) { int idx = blockIdx.x * blockDim.x + threadIdx.x; if (idx < len) { y[idx] += x[idx] * v[idx]; } }
.file "tmpxft_0013f7da_00000000-6_xvpy_f32.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z32__device_stub__Z8xvpy_f32PfS_S_iPfS_S_i .type _Z32__device_stub__Z8xvpy_f32PfS_S_iPfS_S_i, @function _Z32__device_stub__Z8xvpy_f32PfS_S_iPfS_S_i: .LFB2051: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z8xvpy_f32PfS_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z32__device_stub__Z8xvpy_f32PfS_S_iPfS_S_i, .-_Z32__device_stub__Z8xvpy_f32PfS_S_iPfS_S_i .globl _Z8xvpy_f32PfS_S_i .type _Z8xvpy_f32PfS_S_i, @function _Z8xvpy_f32PfS_S_i: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z32__device_stub__Z8xvpy_f32PfS_S_iPfS_S_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z8xvpy_f32PfS_S_i, .-_Z8xvpy_f32PfS_S_i .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z8xvpy_f32PfS_S_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z8xvpy_f32PfS_S_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include "includes.h" __global__ void xvpy_f32 (float* x, float* v, float* y, int len) { int idx = blockIdx.x * blockDim.x + threadIdx.x; if (idx < len) { y[idx] += x[idx] * v[idx]; } }
#include <hip/hip_runtime.h> #include "includes.h" __global__ void xvpy_f32 (float* x, float* v, float* y, int len) { int idx = blockIdx.x * blockDim.x + threadIdx.x; if (idx < len) { y[idx] += x[idx] * v[idx]; } }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void xvpy_f32 (float* x, float* v, float* y, int len) { int idx = blockIdx.x * blockDim.x + threadIdx.x; if (idx < len) { y[idx] += x[idx] * v[idx]; } }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z8xvpy_f32PfS_S_i .globl _Z8xvpy_f32PfS_S_i .p2align 8 .type _Z8xvpy_f32PfS_S_i,@function _Z8xvpy_f32PfS_S_i: s_clause 0x1 s_load_b32 s2, s[0:1], 0x2c s_load_b32 s3, s[0:1], 0x18 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_2 s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[0:1], s[0:1], 0x10 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v4, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_load_b32 v2, v[2:3], off global_load_b32 v3, v[4:5], off global_load_b32 v4, v[0:1], off s_waitcnt vmcnt(0) v_fmac_f32_e32 v4, v2, v3 global_store_b32 v[0:1], v4, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z8xvpy_f32PfS_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z8xvpy_f32PfS_S_i, .Lfunc_end0-_Z8xvpy_f32PfS_S_i .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z8xvpy_f32PfS_S_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z8xvpy_f32PfS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void xvpy_f32 (float* x, float* v, float* y, int len) { int idx = blockIdx.x * blockDim.x + threadIdx.x; if (idx < len) { y[idx] += x[idx] * v[idx]; } }
.text .file "xvpy_f32.hip" .globl _Z23__device_stub__xvpy_f32PfS_S_i # -- Begin function _Z23__device_stub__xvpy_f32PfS_S_i .p2align 4, 0x90 .type _Z23__device_stub__xvpy_f32PfS_S_i,@function _Z23__device_stub__xvpy_f32PfS_S_i: # @_Z23__device_stub__xvpy_f32PfS_S_i .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z8xvpy_f32PfS_S_i, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z23__device_stub__xvpy_f32PfS_S_i, .Lfunc_end0-_Z23__device_stub__xvpy_f32PfS_S_i .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z8xvpy_f32PfS_S_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z8xvpy_f32PfS_S_i,@object # @_Z8xvpy_f32PfS_S_i .section .rodata,"a",@progbits .globl _Z8xvpy_f32PfS_S_i .p2align 3, 0x0 _Z8xvpy_f32PfS_S_i: .quad _Z23__device_stub__xvpy_f32PfS_S_i .size _Z8xvpy_f32PfS_S_i, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z8xvpy_f32PfS_S_i" .size .L__unnamed_1, 19 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z23__device_stub__xvpy_f32PfS_S_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z8xvpy_f32PfS_S_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z8xvpy_f32PfS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */ /* 0x000e280000002500 */ /*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */ /* 0x001fca00078e0203 */ /*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */ /* 0x000fda0003f06270 */ /*0050*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */ /* 0x000fe200000001ff */ /*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd20000000a00 */ /*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */ /* 0x000fc800078e0207 */ /*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */ /* 0x0c0fe400078e0207 */ /*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */ /* 0x000ea4000c1e1900 */ /*00b0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */ /* 0x000fe400078e0207 */ /*00c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */ /* 0x000ea8000c1e1900 */ /*00d0*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */ /* 0x000ea4000c1e1900 */ /*00e0*/ FFMA R9, R4, R3, R0 ; /* 0x0000000304097223 */ /* 0x004fca0000000000 */ /*00f0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */ /* 0x000fe2000c101904 */ /*0100*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0110*/ BRA 0x110; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0120*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0130*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z8xvpy_f32PfS_S_i .globl _Z8xvpy_f32PfS_S_i .p2align 8 .type _Z8xvpy_f32PfS_S_i,@function _Z8xvpy_f32PfS_S_i: s_clause 0x1 s_load_b32 s2, s[0:1], 0x2c s_load_b32 s3, s[0:1], 0x18 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_2 s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[0:1], s[0:1], 0x10 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v4, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_load_b32 v2, v[2:3], off global_load_b32 v3, v[4:5], off global_load_b32 v4, v[0:1], off s_waitcnt vmcnt(0) v_fmac_f32_e32 v4, v2, v3 global_store_b32 v[0:1], v4, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z8xvpy_f32PfS_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z8xvpy_f32PfS_S_i, .Lfunc_end0-_Z8xvpy_f32PfS_S_i .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z8xvpy_f32PfS_S_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z8xvpy_f32PfS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_0013f7da_00000000-6_xvpy_f32.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z32__device_stub__Z8xvpy_f32PfS_S_iPfS_S_i .type _Z32__device_stub__Z8xvpy_f32PfS_S_iPfS_S_i, @function _Z32__device_stub__Z8xvpy_f32PfS_S_iPfS_S_i: .LFB2051: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z8xvpy_f32PfS_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z32__device_stub__Z8xvpy_f32PfS_S_iPfS_S_i, .-_Z32__device_stub__Z8xvpy_f32PfS_S_iPfS_S_i .globl _Z8xvpy_f32PfS_S_i .type _Z8xvpy_f32PfS_S_i, @function _Z8xvpy_f32PfS_S_i: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z32__device_stub__Z8xvpy_f32PfS_S_iPfS_S_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z8xvpy_f32PfS_S_i, .-_Z8xvpy_f32PfS_S_i .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z8xvpy_f32PfS_S_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z8xvpy_f32PfS_S_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "xvpy_f32.hip" .globl _Z23__device_stub__xvpy_f32PfS_S_i # -- Begin function _Z23__device_stub__xvpy_f32PfS_S_i .p2align 4, 0x90 .type _Z23__device_stub__xvpy_f32PfS_S_i,@function _Z23__device_stub__xvpy_f32PfS_S_i: # @_Z23__device_stub__xvpy_f32PfS_S_i .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z8xvpy_f32PfS_S_i, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z23__device_stub__xvpy_f32PfS_S_i, .Lfunc_end0-_Z23__device_stub__xvpy_f32PfS_S_i .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z8xvpy_f32PfS_S_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z8xvpy_f32PfS_S_i,@object # @_Z8xvpy_f32PfS_S_i .section .rodata,"a",@progbits .globl _Z8xvpy_f32PfS_S_i .p2align 3, 0x0 _Z8xvpy_f32PfS_S_i: .quad _Z23__device_stub__xvpy_f32PfS_S_i .size _Z8xvpy_f32PfS_S_i, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z8xvpy_f32PfS_S_i" .size .L__unnamed_1, 19 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z23__device_stub__xvpy_f32PfS_S_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z8xvpy_f32PfS_S_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include <stdio.h> #include <stdlib.h> #include <time.h> #include <sys/time.h> __global__ void flops( float* floats , int n , int m ) { int idx = threadIdx.x + blockIdx.x * blockDim.x ; if( idx >= m ) return ; float temp = 3.14159 * idx ; int i ; for( i = 0 ; i < n ; i++ ) temp = temp + temp/2.0 ; floats[idx] = temp ; } int main( int argc , char** argv ) { cudaDeviceReset() ; struct timeval start, end ; int n = 10 ; if( argc > 1 ) n = atoi(argv[1]) ; else printf( "Optional arguments: (arg1) number of floats to add and divide, (arg2) number of threads \n" ) ; int m = 100 ; if( argc > 2 ) m = atoi(argv[2]) ; int blocks = m/32 + 1 ; float* d_floats ; cudaError_t status = cudaMalloc( &d_floats , m * sizeof(float) ) ; float* h_floats = (float*) malloc( m * sizeof(float) ) ; gettimeofday(&start, NULL) ; if( status == cudaSuccess ) { flops<<< blocks , 32 >>>( d_floats , n , m ) ; status = cudaDeviceSynchronize() ; } gettimeofday(&end, NULL) ; printf("%ld microseconds on GPU\n", ((end.tv_sec * 1000000 + end.tv_usec) - (start.tv_sec * 1000000 + start.tv_usec))); if( status == cudaSuccess ) status = cudaMemcpy( h_floats , d_floats , m * sizeof(float) , cudaMemcpyDeviceToHost ) ; if( status != cudaSuccess ) printf( "ERROR: %s\n" , cudaGetErrorString(status) ) ; float out = 0.0 ; gettimeofday(&start, NULL) ; int i , j ; for( i = 0 ; i < m ; i++ ) { float temp = 3.14159 * i ; for( j = 0 ; j < n ; j++ ) out = temp + temp / 2.0 ; } gettimeofday(&end, NULL) ; printf("%ld microseconds on CPU\n", ((end.tv_sec * 1000000 + end.tv_usec) - (start.tv_sec * 1000000 + start.tv_usec))); out = 0.0 ; for( i = 0 ; i < m ; i++ ) out += h_floats[i] ; printf( "Total val: %f \n" , out ) ; free(h_floats) ; cudaFree(d_floats) ; cudaDeviceReset() ; }
code for sm_80 Function : _Z5flopsPfii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */ /* 0x000e280000002500 */ /*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */ /* 0x001fca00078e0203 */ /*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */ /* 0x000fda0003f06270 */ /*0050*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0060*/ I2F.F64 R2, R0 ; /* 0x0000000000027312 */ /* 0x000e220000201c00 */ /*0070*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */ /* 0x000fe200078e00ff */ /*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fc80000000a00 */ /*0090*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */ /* 0x000fe20003f06270 */ /*00a0*/ DMUL R2, R2, c[0x2][0x0] ; /* 0x0080000002027a28 */ /* 0x001e0c0000000000 */ /*00b0*/ F2F.F32.F64 R15, R2 ; /* 0x00000002000f7310 */ /* 0x00106c0000301000 */ /*00c0*/ @!P0 BRA 0x800 ; /* 0x0000073000008947 */ /* 0x000fea0003800000 */ /*00d0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */ /* 0x041fe40007ffe0ff */ /*00e0*/ LOP3.LUT R3, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304037812 */ /* 0x000fe400078ec0ff */ /*00f0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */ /* 0x000fda0003f06070 */ /*0100*/ @!P0 BRA 0x780 ; /* 0x0000067000008947 */ /* 0x000fea0003800000 */ /*0110*/ IADD3 R2, -R3, c[0x0][0x168], RZ ; /* 0x00005a0003027a10 */ /* 0x000fc80007ffe1ff */ /*0120*/ ISETP.GT.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */ /* 0x000fda0003f04270 */ /*0130*/ @!P0 BRA 0x690 ; /* 0x0000055000008947 */ /* 0x000fea0003800000 */ /*0140*/ ISETP.GT.AND P1, PT, R2, 0xc, PT ; /* 0x0000000c0200780c */ /* 0x000fe40003f24270 */ /*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */ /* 0x000fd60003f0f070 */ /*0160*/ @!P1 BRA 0x4b0 ; /* 0x0000034000009947 */ /* 0x000fea0003800000 */ /*0170*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40003f0e170 */ /*0180*/ F2F.F64.F32 R4, R15 ; /* 0x0000000f00047310 */ /* 0x003e220000201800 */ /*0190*/ IADD3 R2, R2, -0x10, RZ ; /* 0xfffffff002027810 */ /* 0x000fc80007ffe0ff */ /*01a0*/ ISETP.GT.AND P1, PT, R2, 0xc, PT ; /* 0x0000000c0200780c */ /* 0x000fe20003f24270 */ /*01b0*/ DFMA R4, R4, 0.5, R4 ; /* 0x3fe000000404782b */ /* 0x001e140000000004 */ /*01c0*/ F2F.F32.F64 R4, R4 ; /* 0x0000000400047310 */ /* 0x001e300000301000 */ /*01d0*/ F2F.F64.F32 R6, R4 ; /* 0x0000000400067310 */ /* 0x001e240000201800 */ /*01e0*/ DFMA R6, R6, 0.5, R6 ; /* 0x3fe000000606782b */ /* 0x001e140000000006 */ /*01f0*/ F2F.F32.F64 R6, R6 ; /* 0x0000000600067310 */ /* 0x001e300000301000 */ /*0200*/ F2F.F64.F32 R8, R6 ; /* 0x0000000600087310 */ /* 0x001e240000201800 */ /*0210*/ DFMA R8, R8, 0.5, R8 ; /* 0x3fe000000808782b */ /* 0x001e140000000008 */ /*0220*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */ /* 0x001e300000301000 */ /*0230*/ F2F.F64.F32 R10, R8 ; /* 0x00000008000a7310 */ /* 0x001e240000201800 */ /*0240*/ DFMA R10, R10, 0.5, R10 ; /* 0x3fe000000a0a782b */ /* 0x001e14000000000a */ /*0250*/ F2F.F32.F64 R10, R10 ; /* 0x0000000a000a7310 */ /* 0x001e300000301000 */ /*0260*/ F2F.F64.F32 R12, R10 ; /* 0x0000000a000c7310 */ /* 0x001e240000201800 */ /*0270*/ DFMA R12, R12, 0.5, R12 ; /* 0x3fe000000c0c782b */ /* 0x001e14000000000c */ /*0280*/ F2F.F32.F64 R12, R12 ; /* 0x0000000c000c7310 */ /* 0x001e300000301000 */ /*0290*/ F2F.F64.F32 R4, R12 ; /* 0x0000000c00047310 */ /* 0x001e240000201800 */ /*02a0*/ DFMA R4, R4, 0.5, R4 ; /* 0x3fe000000404782b */ /* 0x001e140000000004 */ /*02b0*/ F2F.F32.F64 R4, R4 ; /* 0x0000000400047310 */ /* 0x001e300000301000 */ /*02c0*/ F2F.F64.F32 R6, R4 ; /* 0x0000000400067310 */ /* 0x001e240000201800 */ /*02d0*/ DFMA R6, R6, 0.5, R6 ; /* 0x3fe000000606782b */ /* 0x001e140000000006 */ /*02e0*/ F2F.F32.F64 R6, R6 ; /* 0x0000000600067310 */ /* 0x001e300000301000 */ /*02f0*/ F2F.F64.F32 R8, R6 ; /* 0x0000000600087310 */ /* 0x001e240000201800 */ /*0300*/ DFMA R8, R8, 0.5, R8 ; /* 0x3fe000000808782b */ /* 0x001e140000000008 */ /*0310*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */ /* 0x001e300000301000 */ /*0320*/ F2F.F64.F32 R10, R8 ; /* 0x00000008000a7310 */ /* 0x001e240000201800 */ /*0330*/ DFMA R10, R10, 0.5, R10 ; /* 0x3fe000000a0a782b */ /* 0x001e14000000000a */ /*0340*/ F2F.F32.F64 R10, R10 ; /* 0x0000000a000a7310 */ /* 0x001e300000301000 */ /*0350*/ F2F.F64.F32 R12, R10 ; /* 0x0000000a000c7310 */ /* 0x001e240000201800 */ /*0360*/ DFMA R12, R12, 0.5, R12 ; /* 0x3fe000000c0c782b */ /* 0x001e14000000000c */ /*0370*/ F2F.F32.F64 R12, R12 ; /* 0x0000000c000c7310 */ /* 0x001e300000301000 */ /*0380*/ F2F.F64.F32 R4, R12 ; /* 0x0000000c00047310 */ /* 0x001e240000201800 */ /*0390*/ DFMA R4, R4, 0.5, R4 ; /* 0x3fe000000404782b */ /* 0x001e140000000004 */ /*03a0*/ F2F.F32.F64 R4, R4 ; /* 0x0000000400047310 */ /* 0x001e300000301000 */ /*03b0*/ F2F.F64.F32 R6, R4 ; /* 0x0000000400067310 */ /* 0x001e240000201800 */ /*03c0*/ DFMA R6, R6, 0.5, R6 ; /* 0x3fe000000606782b */ /* 0x001e140000000006 */ /*03d0*/ F2F.F32.F64 R6, R6 ; /* 0x0000000600067310 */ /* 0x001e300000301000 */ /*03e0*/ F2F.F64.F32 R8, R6 ; /* 0x0000000600087310 */ /* 0x001e240000201800 */ /*03f0*/ DFMA R8, R8, 0.5, R8 ; /* 0x3fe000000808782b */ /* 0x001e140000000008 */ /*0400*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */ /* 0x001e300000301000 */ /*0410*/ F2F.F64.F32 R10, R8 ; /* 0x00000008000a7310 */ /* 0x001e240000201800 */ /*0420*/ DFMA R10, R10, 0.5, R10 ; /* 0x3fe000000a0a782b */ /* 0x001e14000000000a */ /*0430*/ F2F.F32.F64 R10, R10 ; /* 0x0000000a000a7310 */ /* 0x001e300000301000 */ /*0440*/ F2F.F64.F32 R12, R10 ; /* 0x0000000a000c7310 */ /* 0x001e240000201800 */ /*0450*/ DFMA R12, R12, 0.5, R12 ; /* 0x3fe000000c0c782b */ /* 0x001e14000000000c */ /*0460*/ F2F.F32.F64 R12, R12 ; /* 0x0000000c000c7310 */ /* 0x001e300000301000 */ /*0470*/ F2F.F64.F32 R4, R12 ; /* 0x0000000c00047310 */ /* 0x001e240000201800 */ /*0480*/ DFMA R4, R4, 0.5, R4 ; /* 0x3fe000000404782b */ /* 0x001e0c0000000004 */ /*0490*/ F2F.F32.F64 R15, R4 ; /* 0x00000004000f7310 */ /* 0x0010620000301000 */ /*04a0*/ @P1 BRA 0x180 ; /* 0xfffffcd000001947 */ /* 0x000fea000383ffff */ /*04b0*/ ISETP.GT.AND P1, PT, R2, 0x4, PT ; /* 0x000000040200780c */ /* 0x000fda0003f24270 */ /*04c0*/ @!P1 BRA 0x670 ; /* 0x000001a000009947 */ /* 0x000fea0003800000 */ /*04d0*/ F2F.F64.F32 R4, R15 ; /* 0x0000000f00047310 */ /* 0x003e220000201800 */ /*04e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40003f0e170 */ /*04f0*/ IADD3 R2, R2, -0x8, RZ ; /* 0xfffffff802027810 */ /* 0x000fe20007ffe0ff */ /*0500*/ DFMA R4, R4, 0.5, R4 ; /* 0x3fe000000404782b */ /* 0x001e140000000004 */ /*0510*/ F2F.F32.F64 R4, R4 ; /* 0x0000000400047310 */ /* 0x001e300000301000 */ /*0520*/ F2F.F64.F32 R6, R4 ; /* 0x0000000400067310 */ /* 0x001e240000201800 */ /*0530*/ DFMA R6, R6, 0.5, R6 ; /* 0x3fe000000606782b */ /* 0x001e140000000006 */ /*0540*/ F2F.F32.F64 R6, R6 ; /* 0x0000000600067310 */ /* 0x001e300000301000 */ /*0550*/ F2F.F64.F32 R8, R6 ; /* 0x0000000600087310 */ /* 0x001e240000201800 */ /*0560*/ DFMA R8, R8, 0.5, R8 ; /* 0x3fe000000808782b */ /* 0x001e140000000008 */ /*0570*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */ /* 0x001e300000301000 */ /*0580*/ F2F.F64.F32 R10, R8 ; /* 0x00000008000a7310 */ /* 0x001e240000201800 */ /*0590*/ DFMA R10, R10, 0.5, R10 ; /* 0x3fe000000a0a782b */ /* 0x001e14000000000a */ /*05a0*/ F2F.F32.F64 R10, R10 ; /* 0x0000000a000a7310 */ /* 0x001e300000301000 */ /*05b0*/ F2F.F64.F32 R12, R10 ; /* 0x0000000a000c7310 */ /* 0x001e240000201800 */ /*05c0*/ DFMA R12, R12, 0.5, R12 ; /* 0x3fe000000c0c782b */ /* 0x001e14000000000c */ /*05d0*/ F2F.F32.F64 R12, R12 ; /* 0x0000000c000c7310 */ /* 0x001e300000301000 */ /*05e0*/ F2F.F64.F32 R4, R12 ; /* 0x0000000c00047310 */ /* 0x001e240000201800 */ /*05f0*/ DFMA R4, R4, 0.5, R4 ; /* 0x3fe000000404782b */ /* 0x001e140000000004 */ /*0600*/ F2F.F32.F64 R4, R4 ; /* 0x0000000400047310 */ /* 0x001e300000301000 */ /*0610*/ F2F.F64.F32 R6, R4 ; /* 0x0000000400067310 */ /* 0x001e240000201800 */ /*0620*/ DFMA R6, R6, 0.5, R6 ; /* 0x3fe000000606782b */ /* 0x001e140000000006 */ /*0630*/ F2F.F32.F64 R6, R6 ; /* 0x0000000600067310 */ /* 0x001e300000301000 */ /*0640*/ F2F.F64.F32 R8, R6 ; /* 0x0000000600087310 */ /* 0x001e240000201800 */ /*0650*/ DFMA R8, R8, 0.5, R8 ; /* 0x3fe000000808782b */ /* 0x001e0c0000000008 */ /*0660*/ F2F.F32.F64 R15, R8 ; /* 0x00000008000f7310 */ /* 0x00106a0000301000 */ /*0670*/ ISETP.NE.OR P0, PT, R2, RZ, P0 ; /* 0x000000ff0200720c */ /* 0x000fda0000705670 */ /*0680*/ @!P0 BRA 0x780 ; /* 0x000000f000008947 */ /* 0x000fea0003800000 */ /*0690*/ F2F.F64.F32 R4, R15 ; /* 0x0000000f00047310 */ /* 0x003e220000201800 */ /*06a0*/ IADD3 R2, R2, -0x4, RZ ; /* 0xfffffffc02027810 */ /* 0x000fc80007ffe0ff */ /*06b0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */ /* 0x000fe20003f05270 */ /*06c0*/ DFMA R4, R4, 0.5, R4 ; /* 0x3fe000000404782b */ /* 0x001e140000000004 */ /*06d0*/ F2F.F32.F64 R4, R4 ; /* 0x0000000400047310 */ /* 0x001e300000301000 */ /*06e0*/ F2F.F64.F32 R6, R4 ; /* 0x0000000400067310 */ /* 0x001e240000201800 */ /*06f0*/ DFMA R6, R6, 0.5, R6 ; /* 0x3fe000000606782b */ /* 0x001e140000000006 */ /*0700*/ F2F.F32.F64 R6, R6 ; /* 0x0000000600067310 */ /* 0x001e300000301000 */ /*0710*/ F2F.F64.F32 R8, R6 ; /* 0x0000000600087310 */ /* 0x001e240000201800 */ /*0720*/ DFMA R8, R8, 0.5, R8 ; /* 0x3fe000000808782b */ /* 0x001e140000000008 */ /*0730*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */ /* 0x001e300000301000 */ /*0740*/ F2F.F64.F32 R10, R8 ; /* 0x00000008000a7310 */ /* 0x001e240000201800 */ /*0750*/ DFMA R10, R10, 0.5, R10 ; /* 0x3fe000000a0a782b */ /* 0x001e0c000000000a */ /*0760*/ F2F.F32.F64 R15, R10 ; /* 0x0000000a000f7310 */ /* 0x0010640000301000 */ /*0770*/ @P0 BRA 0x690 ; /* 0xffffff1000000947 */ /* 0x003fea000383ffff */ /*0780*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */ /* 0x000fda0003f05270 */ /*0790*/ @!P0 BRA 0x800 ; /* 0x0000006000008947 */ /* 0x000fea0003800000 */ /*07a0*/ F2F.F64.F32 R4, R15 ; /* 0x0000000f00047310 */ /* 0x003e220000201800 */ /*07b0*/ IADD3 R3, R3, -0x1, RZ ; /* 0xffffffff03037810 */ /* 0x000fc80007ffe0ff */ /*07c0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */ /* 0x000fe20003f05270 */ /*07d0*/ DFMA R4, R4, 0.5, R4 ; /* 0x3fe000000404782b */ /* 0x001e0c0000000004 */ /*07e0*/ F2F.F32.F64 R15, R4 ; /* 0x00000004000f7310 */ /* 0x00106c0000301000 */ /*07f0*/ @P0 BRA 0x7a0 ; /* 0xffffffa000000947 */ /* 0x000fea000383ffff */ /*0800*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */ /* 0x001fc800078e00ff */ /*0810*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */ /* 0x000fca00078e0203 */ /*0820*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */ /* 0x002fe2000c101904 */ /*0830*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0840*/ BRA 0x840; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0850*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0860*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0870*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0880*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0890*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include <stdio.h> #include <stdlib.h> #include <time.h> #include <sys/time.h> __global__ void flops( float* floats , int n , int m ) { int idx = threadIdx.x + blockIdx.x * blockDim.x ; if( idx >= m ) return ; float temp = 3.14159 * idx ; int i ; for( i = 0 ; i < n ; i++ ) temp = temp + temp/2.0 ; floats[idx] = temp ; } int main( int argc , char** argv ) { cudaDeviceReset() ; struct timeval start, end ; int n = 10 ; if( argc > 1 ) n = atoi(argv[1]) ; else printf( "Optional arguments: (arg1) number of floats to add and divide, (arg2) number of threads \n" ) ; int m = 100 ; if( argc > 2 ) m = atoi(argv[2]) ; int blocks = m/32 + 1 ; float* d_floats ; cudaError_t status = cudaMalloc( &d_floats , m * sizeof(float) ) ; float* h_floats = (float*) malloc( m * sizeof(float) ) ; gettimeofday(&start, NULL) ; if( status == cudaSuccess ) { flops<<< blocks , 32 >>>( d_floats , n , m ) ; status = cudaDeviceSynchronize() ; } gettimeofday(&end, NULL) ; printf("%ld microseconds on GPU\n", ((end.tv_sec * 1000000 + end.tv_usec) - (start.tv_sec * 1000000 + start.tv_usec))); if( status == cudaSuccess ) status = cudaMemcpy( h_floats , d_floats , m * sizeof(float) , cudaMemcpyDeviceToHost ) ; if( status != cudaSuccess ) printf( "ERROR: %s\n" , cudaGetErrorString(status) ) ; float out = 0.0 ; gettimeofday(&start, NULL) ; int i , j ; for( i = 0 ; i < m ; i++ ) { float temp = 3.14159 * i ; for( j = 0 ; j < n ; j++ ) out = temp + temp / 2.0 ; } gettimeofday(&end, NULL) ; printf("%ld microseconds on CPU\n", ((end.tv_sec * 1000000 + end.tv_usec) - (start.tv_sec * 1000000 + start.tv_usec))); out = 0.0 ; for( i = 0 ; i < m ; i++ ) out += h_floats[i] ; printf( "Total val: %f \n" , out ) ; free(h_floats) ; cudaFree(d_floats) ; cudaDeviceReset() ; }
.file "tmpxft_00050952_00000000-6_timeTest.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z26__device_stub__Z5flopsPfiiPfii .type _Z26__device_stub__Z5flopsPfiiPfii, @function _Z26__device_stub__Z5flopsPfiiPfii: .LFB2082: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movl %esi, 4(%rsp) movl %edx, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) leaq 4(%rsp), %rax movq %rax, 88(%rsp) movq %rsp, %rax movq %rax, 96(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z5flopsPfii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z26__device_stub__Z5flopsPfiiPfii, .-_Z26__device_stub__Z5flopsPfiiPfii .globl _Z5flopsPfii .type _Z5flopsPfii, @function _Z5flopsPfii: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z26__device_stub__Z5flopsPfiiPfii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z5flopsPfii, .-_Z5flopsPfii .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC1: .string "Optional arguments: (arg1) number of floats to add and divide, (arg2) number of threads \n" .section .rodata.str1.1,"aMS",@progbits,1 .LC2: .string "%ld microseconds on GPU\n" .LC3: .string "ERROR: %s\n" .LC4: .string "%ld microseconds on CPU\n" .LC5: .string "Total val: %f \n" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $80, %rsp .cfi_def_cfa_offset 128 movl %edi, %ebp movq %rsi, %r12 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax call cudaDeviceReset@PLT cmpl $1, %ebp jle .L12 movq 8(%r12), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movl %eax, %ebx movl $100, %r13d cmpl $2, %ebp jle .L14 movq 16(%r12), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movl %eax, %r13d jmp .L14 .L12: leaq .LC1(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $10, %ebx movl $100, %r13d .L14: movslq %r13d, %r12 salq $2, %r12 leaq 8(%rsp), %rdi movq %r12, %rsi call cudaMalloc@PLT movl %eax, %r14d movq %r12, %rdi call malloc@PLT movq %rax, %rbp leaq 32(%rsp), %rdi movl $0, %esi call gettimeofday@PLT testl %r14d, %r14d je .L36 leaq 48(%rsp), %rdi movl $0, %esi call gettimeofday@PLT imulq $1000000, 48(%rsp), %rdx addq 56(%rsp), %rdx imulq $1000000, 32(%rsp), %rax addq 40(%rsp), %rax subq %rax, %rdx leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT .L17: movl %r14d, %edi call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC3(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT .L18: leaq 32(%rsp), %rdi movl $0, %esi call gettimeofday@PLT movl $0, %ecx testl %r13d, %r13d jg .L19 leaq 48(%rsp), %rdi movl $0, %esi call gettimeofday@PLT imulq $1000000, 48(%rsp), %rdx addq 56(%rsp), %rdx imulq $1000000, 32(%rsp), %rax addq 40(%rsp), %rax subq %rax, %rdx leaq .LC4(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT pxor %xmm0, %xmm0 jmp .L25 .L36: movl $32, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $32, %ecx movl %r13d, %eax cltd idivl %ecx addl $1, %eax movl %eax, 20(%rsp) movl $1, 24(%rsp) movl $0, %r9d movl $0, %r8d movq 48(%rsp), %rdx movl $1, %ecx movq 20(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L37 .L16: call cudaDeviceSynchronize@PLT movl %eax, %r14d leaq 48(%rsp), %rdi movl $0, %esi call gettimeofday@PLT imulq $1000000, 48(%rsp), %rdx addq 56(%rsp), %rdx imulq $1000000, 32(%rsp), %rax addq 40(%rsp), %rax subq %rax, %rdx leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT testl %r14d, %r14d jne .L17 movl $2, %ecx movq %r12, %rdx movq 8(%rsp), %rsi movq %rbp, %rdi call cudaMemcpy@PLT movl %eax, %r14d testl %eax, %eax je .L18 jmp .L17 .L37: movl %r13d, %edx movl %ebx, %esi movq 8(%rsp), %rdi call _Z26__device_stub__Z5flopsPfiiPfii jmp .L16 .L21: addl $1, %edx cmpl %ebx, %edx jne .L21 .L23: addl $1, %ecx cmpl %ecx, %r13d je .L22 .L19: movl $0, %edx testl %ebx, %ebx jg .L21 jmp .L23 .L22: leaq 48(%rsp), %rdi movl $0, %esi call gettimeofday@PLT imulq $1000000, 48(%rsp), %rdx addq 56(%rsp), %rdx imulq $1000000, 32(%rsp), %rax addq 40(%rsp), %rax subq %rax, %rdx leaq .LC4(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq %rbp, %rax addq %rbp, %r12 pxor %xmm0, %xmm0 .L24: addss (%rax), %xmm0 addq $4, %rax cmpq %r12, %rax jne .L24 .L25: cvtss2sd %xmm0, %xmm0 leaq .LC5(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movq %rbp, %rdi call free@PLT movq 8(%rsp), %rdi call cudaFree@PLT call cudaDeviceReset@PLT movq 72(%rsp), %rax subq %fs:40, %rax jne .L38 movl $0, %eax addq $80, %rsp .cfi_remember_state .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L38: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC6: .string "_Z5flopsPfii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC6(%rip), %rdx movq %rdx, %rcx leaq _Z5flopsPfii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include <stdio.h> #include <stdlib.h> #include <time.h> #include <sys/time.h> __global__ void flops( float* floats , int n , int m ) { int idx = threadIdx.x + blockIdx.x * blockDim.x ; if( idx >= m ) return ; float temp = 3.14159 * idx ; int i ; for( i = 0 ; i < n ; i++ ) temp = temp + temp/2.0 ; floats[idx] = temp ; } int main( int argc , char** argv ) { cudaDeviceReset() ; struct timeval start, end ; int n = 10 ; if( argc > 1 ) n = atoi(argv[1]) ; else printf( "Optional arguments: (arg1) number of floats to add and divide, (arg2) number of threads \n" ) ; int m = 100 ; if( argc > 2 ) m = atoi(argv[2]) ; int blocks = m/32 + 1 ; float* d_floats ; cudaError_t status = cudaMalloc( &d_floats , m * sizeof(float) ) ; float* h_floats = (float*) malloc( m * sizeof(float) ) ; gettimeofday(&start, NULL) ; if( status == cudaSuccess ) { flops<<< blocks , 32 >>>( d_floats , n , m ) ; status = cudaDeviceSynchronize() ; } gettimeofday(&end, NULL) ; printf("%ld microseconds on GPU\n", ((end.tv_sec * 1000000 + end.tv_usec) - (start.tv_sec * 1000000 + start.tv_usec))); if( status == cudaSuccess ) status = cudaMemcpy( h_floats , d_floats , m * sizeof(float) , cudaMemcpyDeviceToHost ) ; if( status != cudaSuccess ) printf( "ERROR: %s\n" , cudaGetErrorString(status) ) ; float out = 0.0 ; gettimeofday(&start, NULL) ; int i , j ; for( i = 0 ; i < m ; i++ ) { float temp = 3.14159 * i ; for( j = 0 ; j < n ; j++ ) out = temp + temp / 2.0 ; } gettimeofday(&end, NULL) ; printf("%ld microseconds on CPU\n", ((end.tv_sec * 1000000 + end.tv_usec) - (start.tv_sec * 1000000 + start.tv_usec))); out = 0.0 ; for( i = 0 ; i < m ; i++ ) out += h_floats[i] ; printf( "Total val: %f \n" , out ) ; free(h_floats) ; cudaFree(d_floats) ; cudaDeviceReset() ; }
#include <hip/hip_runtime.h> #include <stdio.h> #include <stdlib.h> #include <time.h> #include <sys/time.h> __global__ void flops( float* floats , int n , int m ) { int idx = threadIdx.x + blockIdx.x * blockDim.x ; if( idx >= m ) return ; float temp = 3.14159 * idx ; int i ; for( i = 0 ; i < n ; i++ ) temp = temp + temp/2.0 ; floats[idx] = temp ; } int main( int argc , char** argv ) { hipDeviceReset() ; struct timeval start, end ; int n = 10 ; if( argc > 1 ) n = atoi(argv[1]) ; else printf( "Optional arguments: (arg1) number of floats to add and divide, (arg2) number of threads \n" ) ; int m = 100 ; if( argc > 2 ) m = atoi(argv[2]) ; int blocks = m/32 + 1 ; float* d_floats ; hipError_t status = hipMalloc( &d_floats , m * sizeof(float) ) ; float* h_floats = (float*) malloc( m * sizeof(float) ) ; gettimeofday(&start, NULL) ; if( status == hipSuccess ) { flops<<< blocks , 32 >>>( d_floats , n , m ) ; status = hipDeviceSynchronize() ; } gettimeofday(&end, NULL) ; printf("%ld microseconds on GPU\n", ((end.tv_sec * 1000000 + end.tv_usec) - (start.tv_sec * 1000000 + start.tv_usec))); if( status == hipSuccess ) status = hipMemcpy( h_floats , d_floats , m * sizeof(float) , hipMemcpyDeviceToHost ) ; if( status != hipSuccess ) printf( "ERROR: %s\n" , hipGetErrorString(status) ) ; float out = 0.0 ; gettimeofday(&start, NULL) ; int i , j ; for( i = 0 ; i < m ; i++ ) { float temp = 3.14159 * i ; for( j = 0 ; j < n ; j++ ) out = temp + temp / 2.0 ; } gettimeofday(&end, NULL) ; printf("%ld microseconds on CPU\n", ((end.tv_sec * 1000000 + end.tv_usec) - (start.tv_sec * 1000000 + start.tv_usec))); out = 0.0 ; for( i = 0 ; i < m ; i++ ) out += h_floats[i] ; printf( "Total val: %f \n" , out ) ; free(h_floats) ; hipFree(d_floats) ; hipDeviceReset() ; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include <stdio.h> #include <stdlib.h> #include <time.h> #include <sys/time.h> __global__ void flops( float* floats , int n , int m ) { int idx = threadIdx.x + blockIdx.x * blockDim.x ; if( idx >= m ) return ; float temp = 3.14159 * idx ; int i ; for( i = 0 ; i < n ; i++ ) temp = temp + temp/2.0 ; floats[idx] = temp ; } int main( int argc , char** argv ) { hipDeviceReset() ; struct timeval start, end ; int n = 10 ; if( argc > 1 ) n = atoi(argv[1]) ; else printf( "Optional arguments: (arg1) number of floats to add and divide, (arg2) number of threads \n" ) ; int m = 100 ; if( argc > 2 ) m = atoi(argv[2]) ; int blocks = m/32 + 1 ; float* d_floats ; hipError_t status = hipMalloc( &d_floats , m * sizeof(float) ) ; float* h_floats = (float*) malloc( m * sizeof(float) ) ; gettimeofday(&start, NULL) ; if( status == hipSuccess ) { flops<<< blocks , 32 >>>( d_floats , n , m ) ; status = hipDeviceSynchronize() ; } gettimeofday(&end, NULL) ; printf("%ld microseconds on GPU\n", ((end.tv_sec * 1000000 + end.tv_usec) - (start.tv_sec * 1000000 + start.tv_usec))); if( status == hipSuccess ) status = hipMemcpy( h_floats , d_floats , m * sizeof(float) , hipMemcpyDeviceToHost ) ; if( status != hipSuccess ) printf( "ERROR: %s\n" , hipGetErrorString(status) ) ; float out = 0.0 ; gettimeofday(&start, NULL) ; int i , j ; for( i = 0 ; i < m ; i++ ) { float temp = 3.14159 * i ; for( j = 0 ; j < n ; j++ ) out = temp + temp / 2.0 ; } gettimeofday(&end, NULL) ; printf("%ld microseconds on CPU\n", ((end.tv_sec * 1000000 + end.tv_usec) - (start.tv_sec * 1000000 + start.tv_usec))); out = 0.0 ; for( i = 0 ; i < m ; i++ ) out += h_floats[i] ; printf( "Total val: %f \n" , out ) ; free(h_floats) ; hipFree(d_floats) ; hipDeviceReset() ; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z5flopsPfii .globl _Z5flopsPfii .p2align 8 .type _Z5flopsPfii,@function _Z5flopsPfii: s_clause 0x1 s_load_b32 s2, s[0:1], 0x1c s_load_b32 s3, s[0:1], 0xc s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_4 v_cvt_f64_i32_e32 v[2:3], v1 s_mov_b32 s3, 0x400921f9 s_mov_b32 s2, 0xf01b866e s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_mul_f64 v[2:3], v[2:3], s[2:3] s_load_b32 s2, s[0:1], 0x8 s_waitcnt lgkmcnt(0) s_cmp_lt_i32 s2, 1 s_delay_alu instid0(VALU_DEP_1) v_cvt_f32_f64_e32 v0, v[2:3] s_cbranch_scc1 .LBB0_3 .LBB0_2: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_cvt_f64_f32_e32 v[2:3], v0 s_add_i32 s2, s2, -1 s_cmp_lg_u32 s2, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[2:3], v[2:3], 0.5, v[2:3] v_cvt_f32_f64_e32 v0, v[2:3] s_cbranch_scc1 .LBB0_2 .LBB0_3: s_load_b64 s[0:1], s[0:1], 0x0 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[1:2], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v1, vcc_lo, s0, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo global_store_b32 v[1:2], v0, off .LBB0_4: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z5flopsPfii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z5flopsPfii, .Lfunc_end0-_Z5flopsPfii .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .offset: 12 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z5flopsPfii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z5flopsPfii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include <stdio.h> #include <stdlib.h> #include <time.h> #include <sys/time.h> __global__ void flops( float* floats , int n , int m ) { int idx = threadIdx.x + blockIdx.x * blockDim.x ; if( idx >= m ) return ; float temp = 3.14159 * idx ; int i ; for( i = 0 ; i < n ; i++ ) temp = temp + temp/2.0 ; floats[idx] = temp ; } int main( int argc , char** argv ) { hipDeviceReset() ; struct timeval start, end ; int n = 10 ; if( argc > 1 ) n = atoi(argv[1]) ; else printf( "Optional arguments: (arg1) number of floats to add and divide, (arg2) number of threads \n" ) ; int m = 100 ; if( argc > 2 ) m = atoi(argv[2]) ; int blocks = m/32 + 1 ; float* d_floats ; hipError_t status = hipMalloc( &d_floats , m * sizeof(float) ) ; float* h_floats = (float*) malloc( m * sizeof(float) ) ; gettimeofday(&start, NULL) ; if( status == hipSuccess ) { flops<<< blocks , 32 >>>( d_floats , n , m ) ; status = hipDeviceSynchronize() ; } gettimeofday(&end, NULL) ; printf("%ld microseconds on GPU\n", ((end.tv_sec * 1000000 + end.tv_usec) - (start.tv_sec * 1000000 + start.tv_usec))); if( status == hipSuccess ) status = hipMemcpy( h_floats , d_floats , m * sizeof(float) , hipMemcpyDeviceToHost ) ; if( status != hipSuccess ) printf( "ERROR: %s\n" , hipGetErrorString(status) ) ; float out = 0.0 ; gettimeofday(&start, NULL) ; int i , j ; for( i = 0 ; i < m ; i++ ) { float temp = 3.14159 * i ; for( j = 0 ; j < n ; j++ ) out = temp + temp / 2.0 ; } gettimeofday(&end, NULL) ; printf("%ld microseconds on CPU\n", ((end.tv_sec * 1000000 + end.tv_usec) - (start.tv_sec * 1000000 + start.tv_usec))); out = 0.0 ; for( i = 0 ; i < m ; i++ ) out += h_floats[i] ; printf( "Total val: %f \n" , out ) ; free(h_floats) ; hipFree(d_floats) ; hipDeviceReset() ; }
.text .file "timeTest.hip" .globl _Z20__device_stub__flopsPfii # -- Begin function _Z20__device_stub__flopsPfii .p2align 4, 0x90 .type _Z20__device_stub__flopsPfii,@function _Z20__device_stub__flopsPfii: # @_Z20__device_stub__flopsPfii .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movl %esi, 4(%rsp) movl %edx, (%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 4(%rsp), %rax movq %rax, 72(%rsp) movq %rsp, %rax movq %rax, 80(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z5flopsPfii, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z20__device_stub__flopsPfii, .Lfunc_end0-_Z20__device_stub__flopsPfii .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $112, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rsi, %rbx movl %edi, %ebp callq hipDeviceReset cmpl $2, %ebp jl .LBB1_2 # %bb.1: movq 8(%rbx), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, %r12 jmp .LBB1_3 .LBB1_2: movl $.Lstr, %edi callq puts@PLT movl $10, %r12d .LBB1_3: movl $100, %r14d cmpl $3, %ebp jl .LBB1_5 # %bb.4: movq 16(%rbx), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, %r14 .LBB1_5: movslq %r14d, %r15 shlq $2, %r15 movq %rsp, %rdi movq %r15, %rsi callq hipMalloc movl %eax, %ebp movq %r15, %rdi callq malloc movq %rax, %rbx leaq 40(%rsp), %rdi xorl %esi, %esi callq gettimeofday testl %ebp, %ebp jne .LBB1_9 # %bb.6: leal 31(%r14), %edi testl %r14d, %r14d cmovnsl %r14d, %edi sarl $5, %edi incl %edi movabsq $4294967296, %rdx # imm = 0x100000000 orq %rdx, %rdi orq $32, %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_8 # %bb.7: movq (%rsp), %rax movq %rax, 104(%rsp) movl %r12d, 12(%rsp) movl %r14d, 8(%rsp) leaq 104(%rsp), %rax movq %rax, 16(%rsp) leaq 12(%rsp), %rax movq %rax, 24(%rsp) leaq 8(%rsp), %rax movq %rax, 32(%rsp) leaq 88(%rsp), %rdi leaq 72(%rsp), %rsi leaq 64(%rsp), %rdx leaq 56(%rsp), %rcx callq __hipPopCallConfiguration movq 88(%rsp), %rsi movl 96(%rsp), %edx movq 72(%rsp), %rcx movl 80(%rsp), %r8d leaq 16(%rsp), %r9 movl $_Z5flopsPfii, %edi pushq 56(%rsp) .cfi_adjust_cfa_offset 8 pushq 72(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_8: callq hipDeviceSynchronize movl %eax, %ebp .LBB1_9: leaq 16(%rsp), %rdi xorl %esi, %esi callq gettimeofday movq 16(%rsp), %rax movq 24(%rsp), %rsi subq 40(%rsp), %rax imulq $1000000, %rax, %rax # imm = 0xF4240 subq 48(%rsp), %rsi addq %rax, %rsi movl $.L.str.1, %edi xorl %eax, %eax callq printf testl %ebp, %ebp jne .LBB1_11 # %bb.10: movq (%rsp), %rsi movq %rbx, %rdi movq %r15, %rdx movl $2, %ecx callq hipMemcpy movl %eax, %ebp .LBB1_11: testl %ebp, %ebp je .LBB1_13 # %bb.12: movl %ebp, %edi callq hipGetErrorString movl $.L.str.2, %edi movq %rax, %rsi xorl %eax, %eax callq printf .LBB1_13: # %._crit_edge leaq 40(%rsp), %rdi xorl %esi, %esi callq gettimeofday leaq 16(%rsp), %rdi xorl %esi, %esi callq gettimeofday movq 16(%rsp), %rax movq 24(%rsp), %rsi subq 40(%rsp), %rax imulq $1000000, %rax, %rax # imm = 0xF4240 subq 48(%rsp), %rsi addq %rax, %rsi movl $.L.str.3, %edi xorl %eax, %eax callq printf testl %r14d, %r14d jle .LBB1_14 # %bb.15: # %.lr.ph.preheader movl %r14d, %eax xorps %xmm0, %xmm0 xorl %ecx, %ecx .p2align 4, 0x90 .LBB1_16: # %.lr.ph # =>This Inner Loop Header: Depth=1 addss (%rbx,%rcx,4), %xmm0 incq %rcx cmpq %rcx, %rax jne .LBB1_16 # %bb.17: # %._crit_edge57.loopexit cvtss2sd %xmm0, %xmm0 jmp .LBB1_18 .LBB1_14: xorps %xmm0, %xmm0 .LBB1_18: # %._crit_edge57 movl $.L.str.4, %edi movb $1, %al callq printf movq %rbx, %rdi callq free movq (%rsp), %rdi callq hipFree callq hipDeviceReset xorl %eax, %eax addq $112, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z5flopsPfii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z5flopsPfii,@object # @_Z5flopsPfii .section .rodata,"a",@progbits .globl _Z5flopsPfii .p2align 3, 0x0 _Z5flopsPfii: .quad _Z20__device_stub__flopsPfii .size _Z5flopsPfii, 8 .type .L.str.1,@object # @.str.1 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.1: .asciz "%ld microseconds on GPU\n" .size .L.str.1, 25 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "ERROR: %s\n" .size .L.str.2, 11 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "%ld microseconds on CPU\n" .size .L.str.3, 25 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Total val: %f \n" .size .L.str.4, 16 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z5flopsPfii" .size .L__unnamed_1, 13 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "Optional arguments: (arg1) number of floats to add and divide, (arg2) number of threads " .size .Lstr, 89 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z20__device_stub__flopsPfii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z5flopsPfii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z5flopsPfii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */ /* 0x000e280000002500 */ /*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */ /* 0x001fca00078e0203 */ /*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */ /* 0x000fda0003f06270 */ /*0050*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0060*/ I2F.F64 R2, R0 ; /* 0x0000000000027312 */ /* 0x000e220000201c00 */ /*0070*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */ /* 0x000fe200078e00ff */ /*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fc80000000a00 */ /*0090*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */ /* 0x000fe20003f06270 */ /*00a0*/ DMUL R2, R2, c[0x2][0x0] ; /* 0x0080000002027a28 */ /* 0x001e0c0000000000 */ /*00b0*/ F2F.F32.F64 R15, R2 ; /* 0x00000002000f7310 */ /* 0x00106c0000301000 */ /*00c0*/ @!P0 BRA 0x800 ; /* 0x0000073000008947 */ /* 0x000fea0003800000 */ /*00d0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */ /* 0x041fe40007ffe0ff */ /*00e0*/ LOP3.LUT R3, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304037812 */ /* 0x000fe400078ec0ff */ /*00f0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */ /* 0x000fda0003f06070 */ /*0100*/ @!P0 BRA 0x780 ; /* 0x0000067000008947 */ /* 0x000fea0003800000 */ /*0110*/ IADD3 R2, -R3, c[0x0][0x168], RZ ; /* 0x00005a0003027a10 */ /* 0x000fc80007ffe1ff */ /*0120*/ ISETP.GT.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */ /* 0x000fda0003f04270 */ /*0130*/ @!P0 BRA 0x690 ; /* 0x0000055000008947 */ /* 0x000fea0003800000 */ /*0140*/ ISETP.GT.AND P1, PT, R2, 0xc, PT ; /* 0x0000000c0200780c */ /* 0x000fe40003f24270 */ /*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */ /* 0x000fd60003f0f070 */ /*0160*/ @!P1 BRA 0x4b0 ; /* 0x0000034000009947 */ /* 0x000fea0003800000 */ /*0170*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40003f0e170 */ /*0180*/ F2F.F64.F32 R4, R15 ; /* 0x0000000f00047310 */ /* 0x003e220000201800 */ /*0190*/ IADD3 R2, R2, -0x10, RZ ; /* 0xfffffff002027810 */ /* 0x000fc80007ffe0ff */ /*01a0*/ ISETP.GT.AND P1, PT, R2, 0xc, PT ; /* 0x0000000c0200780c */ /* 0x000fe20003f24270 */ /*01b0*/ DFMA R4, R4, 0.5, R4 ; /* 0x3fe000000404782b */ /* 0x001e140000000004 */ /*01c0*/ F2F.F32.F64 R4, R4 ; /* 0x0000000400047310 */ /* 0x001e300000301000 */ /*01d0*/ F2F.F64.F32 R6, R4 ; /* 0x0000000400067310 */ /* 0x001e240000201800 */ /*01e0*/ DFMA R6, R6, 0.5, R6 ; /* 0x3fe000000606782b */ /* 0x001e140000000006 */ /*01f0*/ F2F.F32.F64 R6, R6 ; /* 0x0000000600067310 */ /* 0x001e300000301000 */ /*0200*/ F2F.F64.F32 R8, R6 ; /* 0x0000000600087310 */ /* 0x001e240000201800 */ /*0210*/ DFMA R8, R8, 0.5, R8 ; /* 0x3fe000000808782b */ /* 0x001e140000000008 */ /*0220*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */ /* 0x001e300000301000 */ /*0230*/ F2F.F64.F32 R10, R8 ; /* 0x00000008000a7310 */ /* 0x001e240000201800 */ /*0240*/ DFMA R10, R10, 0.5, R10 ; /* 0x3fe000000a0a782b */ /* 0x001e14000000000a */ /*0250*/ F2F.F32.F64 R10, R10 ; /* 0x0000000a000a7310 */ /* 0x001e300000301000 */ /*0260*/ F2F.F64.F32 R12, R10 ; /* 0x0000000a000c7310 */ /* 0x001e240000201800 */ /*0270*/ DFMA R12, R12, 0.5, R12 ; /* 0x3fe000000c0c782b */ /* 0x001e14000000000c */ /*0280*/ F2F.F32.F64 R12, R12 ; /* 0x0000000c000c7310 */ /* 0x001e300000301000 */ /*0290*/ F2F.F64.F32 R4, R12 ; /* 0x0000000c00047310 */ /* 0x001e240000201800 */ /*02a0*/ DFMA R4, R4, 0.5, R4 ; /* 0x3fe000000404782b */ /* 0x001e140000000004 */ /*02b0*/ F2F.F32.F64 R4, R4 ; /* 0x0000000400047310 */ /* 0x001e300000301000 */ /*02c0*/ F2F.F64.F32 R6, R4 ; /* 0x0000000400067310 */ /* 0x001e240000201800 */ /*02d0*/ DFMA R6, R6, 0.5, R6 ; /* 0x3fe000000606782b */ /* 0x001e140000000006 */ /*02e0*/ F2F.F32.F64 R6, R6 ; /* 0x0000000600067310 */ /* 0x001e300000301000 */ /*02f0*/ F2F.F64.F32 R8, R6 ; /* 0x0000000600087310 */ /* 0x001e240000201800 */ /*0300*/ DFMA R8, R8, 0.5, R8 ; /* 0x3fe000000808782b */ /* 0x001e140000000008 */ /*0310*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */ /* 0x001e300000301000 */ /*0320*/ F2F.F64.F32 R10, R8 ; /* 0x00000008000a7310 */ /* 0x001e240000201800 */ /*0330*/ DFMA R10, R10, 0.5, R10 ; /* 0x3fe000000a0a782b */ /* 0x001e14000000000a */ /*0340*/ F2F.F32.F64 R10, R10 ; /* 0x0000000a000a7310 */ /* 0x001e300000301000 */ /*0350*/ F2F.F64.F32 R12, R10 ; /* 0x0000000a000c7310 */ /* 0x001e240000201800 */ /*0360*/ DFMA R12, R12, 0.5, R12 ; /* 0x3fe000000c0c782b */ /* 0x001e14000000000c */ /*0370*/ F2F.F32.F64 R12, R12 ; /* 0x0000000c000c7310 */ /* 0x001e300000301000 */ /*0380*/ F2F.F64.F32 R4, R12 ; /* 0x0000000c00047310 */ /* 0x001e240000201800 */ /*0390*/ DFMA R4, R4, 0.5, R4 ; /* 0x3fe000000404782b */ /* 0x001e140000000004 */ /*03a0*/ F2F.F32.F64 R4, R4 ; /* 0x0000000400047310 */ /* 0x001e300000301000 */ /*03b0*/ F2F.F64.F32 R6, R4 ; /* 0x0000000400067310 */ /* 0x001e240000201800 */ /*03c0*/ DFMA R6, R6, 0.5, R6 ; /* 0x3fe000000606782b */ /* 0x001e140000000006 */ /*03d0*/ F2F.F32.F64 R6, R6 ; /* 0x0000000600067310 */ /* 0x001e300000301000 */ /*03e0*/ F2F.F64.F32 R8, R6 ; /* 0x0000000600087310 */ /* 0x001e240000201800 */ /*03f0*/ DFMA R8, R8, 0.5, R8 ; /* 0x3fe000000808782b */ /* 0x001e140000000008 */ /*0400*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */ /* 0x001e300000301000 */ /*0410*/ F2F.F64.F32 R10, R8 ; /* 0x00000008000a7310 */ /* 0x001e240000201800 */ /*0420*/ DFMA R10, R10, 0.5, R10 ; /* 0x3fe000000a0a782b */ /* 0x001e14000000000a */ /*0430*/ F2F.F32.F64 R10, R10 ; /* 0x0000000a000a7310 */ /* 0x001e300000301000 */ /*0440*/ F2F.F64.F32 R12, R10 ; /* 0x0000000a000c7310 */ /* 0x001e240000201800 */ /*0450*/ DFMA R12, R12, 0.5, R12 ; /* 0x3fe000000c0c782b */ /* 0x001e14000000000c */ /*0460*/ F2F.F32.F64 R12, R12 ; /* 0x0000000c000c7310 */ /* 0x001e300000301000 */ /*0470*/ F2F.F64.F32 R4, R12 ; /* 0x0000000c00047310 */ /* 0x001e240000201800 */ /*0480*/ DFMA R4, R4, 0.5, R4 ; /* 0x3fe000000404782b */ /* 0x001e0c0000000004 */ /*0490*/ F2F.F32.F64 R15, R4 ; /* 0x00000004000f7310 */ /* 0x0010620000301000 */ /*04a0*/ @P1 BRA 0x180 ; /* 0xfffffcd000001947 */ /* 0x000fea000383ffff */ /*04b0*/ ISETP.GT.AND P1, PT, R2, 0x4, PT ; /* 0x000000040200780c */ /* 0x000fda0003f24270 */ /*04c0*/ @!P1 BRA 0x670 ; /* 0x000001a000009947 */ /* 0x000fea0003800000 */ /*04d0*/ F2F.F64.F32 R4, R15 ; /* 0x0000000f00047310 */ /* 0x003e220000201800 */ /*04e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40003f0e170 */ /*04f0*/ IADD3 R2, R2, -0x8, RZ ; /* 0xfffffff802027810 */ /* 0x000fe20007ffe0ff */ /*0500*/ DFMA R4, R4, 0.5, R4 ; /* 0x3fe000000404782b */ /* 0x001e140000000004 */ /*0510*/ F2F.F32.F64 R4, R4 ; /* 0x0000000400047310 */ /* 0x001e300000301000 */ /*0520*/ F2F.F64.F32 R6, R4 ; /* 0x0000000400067310 */ /* 0x001e240000201800 */ /*0530*/ DFMA R6, R6, 0.5, R6 ; /* 0x3fe000000606782b */ /* 0x001e140000000006 */ /*0540*/ F2F.F32.F64 R6, R6 ; /* 0x0000000600067310 */ /* 0x001e300000301000 */ /*0550*/ F2F.F64.F32 R8, R6 ; /* 0x0000000600087310 */ /* 0x001e240000201800 */ /*0560*/ DFMA R8, R8, 0.5, R8 ; /* 0x3fe000000808782b */ /* 0x001e140000000008 */ /*0570*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */ /* 0x001e300000301000 */ /*0580*/ F2F.F64.F32 R10, R8 ; /* 0x00000008000a7310 */ /* 0x001e240000201800 */ /*0590*/ DFMA R10, R10, 0.5, R10 ; /* 0x3fe000000a0a782b */ /* 0x001e14000000000a */ /*05a0*/ F2F.F32.F64 R10, R10 ; /* 0x0000000a000a7310 */ /* 0x001e300000301000 */ /*05b0*/ F2F.F64.F32 R12, R10 ; /* 0x0000000a000c7310 */ /* 0x001e240000201800 */ /*05c0*/ DFMA R12, R12, 0.5, R12 ; /* 0x3fe000000c0c782b */ /* 0x001e14000000000c */ /*05d0*/ F2F.F32.F64 R12, R12 ; /* 0x0000000c000c7310 */ /* 0x001e300000301000 */ /*05e0*/ F2F.F64.F32 R4, R12 ; /* 0x0000000c00047310 */ /* 0x001e240000201800 */ /*05f0*/ DFMA R4, R4, 0.5, R4 ; /* 0x3fe000000404782b */ /* 0x001e140000000004 */ /*0600*/ F2F.F32.F64 R4, R4 ; /* 0x0000000400047310 */ /* 0x001e300000301000 */ /*0610*/ F2F.F64.F32 R6, R4 ; /* 0x0000000400067310 */ /* 0x001e240000201800 */ /*0620*/ DFMA R6, R6, 0.5, R6 ; /* 0x3fe000000606782b */ /* 0x001e140000000006 */ /*0630*/ F2F.F32.F64 R6, R6 ; /* 0x0000000600067310 */ /* 0x001e300000301000 */ /*0640*/ F2F.F64.F32 R8, R6 ; /* 0x0000000600087310 */ /* 0x001e240000201800 */ /*0650*/ DFMA R8, R8, 0.5, R8 ; /* 0x3fe000000808782b */ /* 0x001e0c0000000008 */ /*0660*/ F2F.F32.F64 R15, R8 ; /* 0x00000008000f7310 */ /* 0x00106a0000301000 */ /*0670*/ ISETP.NE.OR P0, PT, R2, RZ, P0 ; /* 0x000000ff0200720c */ /* 0x000fda0000705670 */ /*0680*/ @!P0 BRA 0x780 ; /* 0x000000f000008947 */ /* 0x000fea0003800000 */ /*0690*/ F2F.F64.F32 R4, R15 ; /* 0x0000000f00047310 */ /* 0x003e220000201800 */ /*06a0*/ IADD3 R2, R2, -0x4, RZ ; /* 0xfffffffc02027810 */ /* 0x000fc80007ffe0ff */ /*06b0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */ /* 0x000fe20003f05270 */ /*06c0*/ DFMA R4, R4, 0.5, R4 ; /* 0x3fe000000404782b */ /* 0x001e140000000004 */ /*06d0*/ F2F.F32.F64 R4, R4 ; /* 0x0000000400047310 */ /* 0x001e300000301000 */ /*06e0*/ F2F.F64.F32 R6, R4 ; /* 0x0000000400067310 */ /* 0x001e240000201800 */ /*06f0*/ DFMA R6, R6, 0.5, R6 ; /* 0x3fe000000606782b */ /* 0x001e140000000006 */ /*0700*/ F2F.F32.F64 R6, R6 ; /* 0x0000000600067310 */ /* 0x001e300000301000 */ /*0710*/ F2F.F64.F32 R8, R6 ; /* 0x0000000600087310 */ /* 0x001e240000201800 */ /*0720*/ DFMA R8, R8, 0.5, R8 ; /* 0x3fe000000808782b */ /* 0x001e140000000008 */ /*0730*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */ /* 0x001e300000301000 */ /*0740*/ F2F.F64.F32 R10, R8 ; /* 0x00000008000a7310 */ /* 0x001e240000201800 */ /*0750*/ DFMA R10, R10, 0.5, R10 ; /* 0x3fe000000a0a782b */ /* 0x001e0c000000000a */ /*0760*/ F2F.F32.F64 R15, R10 ; /* 0x0000000a000f7310 */ /* 0x0010640000301000 */ /*0770*/ @P0 BRA 0x690 ; /* 0xffffff1000000947 */ /* 0x003fea000383ffff */ /*0780*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */ /* 0x000fda0003f05270 */ /*0790*/ @!P0 BRA 0x800 ; /* 0x0000006000008947 */ /* 0x000fea0003800000 */ /*07a0*/ F2F.F64.F32 R4, R15 ; /* 0x0000000f00047310 */ /* 0x003e220000201800 */ /*07b0*/ IADD3 R3, R3, -0x1, RZ ; /* 0xffffffff03037810 */ /* 0x000fc80007ffe0ff */ /*07c0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */ /* 0x000fe20003f05270 */ /*07d0*/ DFMA R4, R4, 0.5, R4 ; /* 0x3fe000000404782b */ /* 0x001e0c0000000004 */ /*07e0*/ F2F.F32.F64 R15, R4 ; /* 0x00000004000f7310 */ /* 0x00106c0000301000 */ /*07f0*/ @P0 BRA 0x7a0 ; /* 0xffffffa000000947 */ /* 0x000fea000383ffff */ /*0800*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */ /* 0x001fc800078e00ff */ /*0810*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */ /* 0x000fca00078e0203 */ /*0820*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */ /* 0x002fe2000c101904 */ /*0830*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0840*/ BRA 0x840; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0850*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0860*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0870*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0880*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0890*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z5flopsPfii .globl _Z5flopsPfii .p2align 8 .type _Z5flopsPfii,@function _Z5flopsPfii: s_clause 0x1 s_load_b32 s2, s[0:1], 0x1c s_load_b32 s3, s[0:1], 0xc s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_4 v_cvt_f64_i32_e32 v[2:3], v1 s_mov_b32 s3, 0x400921f9 s_mov_b32 s2, 0xf01b866e s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_mul_f64 v[2:3], v[2:3], s[2:3] s_load_b32 s2, s[0:1], 0x8 s_waitcnt lgkmcnt(0) s_cmp_lt_i32 s2, 1 s_delay_alu instid0(VALU_DEP_1) v_cvt_f32_f64_e32 v0, v[2:3] s_cbranch_scc1 .LBB0_3 .LBB0_2: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_cvt_f64_f32_e32 v[2:3], v0 s_add_i32 s2, s2, -1 s_cmp_lg_u32 s2, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[2:3], v[2:3], 0.5, v[2:3] v_cvt_f32_f64_e32 v0, v[2:3] s_cbranch_scc1 .LBB0_2 .LBB0_3: s_load_b64 s[0:1], s[0:1], 0x0 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[1:2], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v1, vcc_lo, s0, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo global_store_b32 v[1:2], v0, off .LBB0_4: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z5flopsPfii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z5flopsPfii, .Lfunc_end0-_Z5flopsPfii .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .offset: 12 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z5flopsPfii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z5flopsPfii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_00050952_00000000-6_timeTest.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z26__device_stub__Z5flopsPfiiPfii .type _Z26__device_stub__Z5flopsPfiiPfii, @function _Z26__device_stub__Z5flopsPfiiPfii: .LFB2082: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movl %esi, 4(%rsp) movl %edx, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) leaq 4(%rsp), %rax movq %rax, 88(%rsp) movq %rsp, %rax movq %rax, 96(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z5flopsPfii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z26__device_stub__Z5flopsPfiiPfii, .-_Z26__device_stub__Z5flopsPfiiPfii .globl _Z5flopsPfii .type _Z5flopsPfii, @function _Z5flopsPfii: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z26__device_stub__Z5flopsPfiiPfii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z5flopsPfii, .-_Z5flopsPfii .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC1: .string "Optional arguments: (arg1) number of floats to add and divide, (arg2) number of threads \n" .section .rodata.str1.1,"aMS",@progbits,1 .LC2: .string "%ld microseconds on GPU\n" .LC3: .string "ERROR: %s\n" .LC4: .string "%ld microseconds on CPU\n" .LC5: .string "Total val: %f \n" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $80, %rsp .cfi_def_cfa_offset 128 movl %edi, %ebp movq %rsi, %r12 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax call cudaDeviceReset@PLT cmpl $1, %ebp jle .L12 movq 8(%r12), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movl %eax, %ebx movl $100, %r13d cmpl $2, %ebp jle .L14 movq 16(%r12), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movl %eax, %r13d jmp .L14 .L12: leaq .LC1(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $10, %ebx movl $100, %r13d .L14: movslq %r13d, %r12 salq $2, %r12 leaq 8(%rsp), %rdi movq %r12, %rsi call cudaMalloc@PLT movl %eax, %r14d movq %r12, %rdi call malloc@PLT movq %rax, %rbp leaq 32(%rsp), %rdi movl $0, %esi call gettimeofday@PLT testl %r14d, %r14d je .L36 leaq 48(%rsp), %rdi movl $0, %esi call gettimeofday@PLT imulq $1000000, 48(%rsp), %rdx addq 56(%rsp), %rdx imulq $1000000, 32(%rsp), %rax addq 40(%rsp), %rax subq %rax, %rdx leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT .L17: movl %r14d, %edi call cudaGetErrorString@PLT movq %rax, %rdx leaq .LC3(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT .L18: leaq 32(%rsp), %rdi movl $0, %esi call gettimeofday@PLT movl $0, %ecx testl %r13d, %r13d jg .L19 leaq 48(%rsp), %rdi movl $0, %esi call gettimeofday@PLT imulq $1000000, 48(%rsp), %rdx addq 56(%rsp), %rdx imulq $1000000, 32(%rsp), %rax addq 40(%rsp), %rax subq %rax, %rdx leaq .LC4(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT pxor %xmm0, %xmm0 jmp .L25 .L36: movl $32, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $32, %ecx movl %r13d, %eax cltd idivl %ecx addl $1, %eax movl %eax, 20(%rsp) movl $1, 24(%rsp) movl $0, %r9d movl $0, %r8d movq 48(%rsp), %rdx movl $1, %ecx movq 20(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L37 .L16: call cudaDeviceSynchronize@PLT movl %eax, %r14d leaq 48(%rsp), %rdi movl $0, %esi call gettimeofday@PLT imulq $1000000, 48(%rsp), %rdx addq 56(%rsp), %rdx imulq $1000000, 32(%rsp), %rax addq 40(%rsp), %rax subq %rax, %rdx leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT testl %r14d, %r14d jne .L17 movl $2, %ecx movq %r12, %rdx movq 8(%rsp), %rsi movq %rbp, %rdi call cudaMemcpy@PLT movl %eax, %r14d testl %eax, %eax je .L18 jmp .L17 .L37: movl %r13d, %edx movl %ebx, %esi movq 8(%rsp), %rdi call _Z26__device_stub__Z5flopsPfiiPfii jmp .L16 .L21: addl $1, %edx cmpl %ebx, %edx jne .L21 .L23: addl $1, %ecx cmpl %ecx, %r13d je .L22 .L19: movl $0, %edx testl %ebx, %ebx jg .L21 jmp .L23 .L22: leaq 48(%rsp), %rdi movl $0, %esi call gettimeofday@PLT imulq $1000000, 48(%rsp), %rdx addq 56(%rsp), %rdx imulq $1000000, 32(%rsp), %rax addq 40(%rsp), %rax subq %rax, %rdx leaq .LC4(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq %rbp, %rax addq %rbp, %r12 pxor %xmm0, %xmm0 .L24: addss (%rax), %xmm0 addq $4, %rax cmpq %r12, %rax jne .L24 .L25: cvtss2sd %xmm0, %xmm0 leaq .LC5(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movq %rbp, %rdi call free@PLT movq 8(%rsp), %rdi call cudaFree@PLT call cudaDeviceReset@PLT movq 72(%rsp), %rax subq %fs:40, %rax jne .L38 movl $0, %eax addq $80, %rsp .cfi_remember_state .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L38: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC6: .string "_Z5flopsPfii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC6(%rip), %rdx movq %rdx, %rcx leaq _Z5flopsPfii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "timeTest.hip" .globl _Z20__device_stub__flopsPfii # -- Begin function _Z20__device_stub__flopsPfii .p2align 4, 0x90 .type _Z20__device_stub__flopsPfii,@function _Z20__device_stub__flopsPfii: # @_Z20__device_stub__flopsPfii .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movl %esi, 4(%rsp) movl %edx, (%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 4(%rsp), %rax movq %rax, 72(%rsp) movq %rsp, %rax movq %rax, 80(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z5flopsPfii, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z20__device_stub__flopsPfii, .Lfunc_end0-_Z20__device_stub__flopsPfii .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $112, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rsi, %rbx movl %edi, %ebp callq hipDeviceReset cmpl $2, %ebp jl .LBB1_2 # %bb.1: movq 8(%rbx), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, %r12 jmp .LBB1_3 .LBB1_2: movl $.Lstr, %edi callq puts@PLT movl $10, %r12d .LBB1_3: movl $100, %r14d cmpl $3, %ebp jl .LBB1_5 # %bb.4: movq 16(%rbx), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, %r14 .LBB1_5: movslq %r14d, %r15 shlq $2, %r15 movq %rsp, %rdi movq %r15, %rsi callq hipMalloc movl %eax, %ebp movq %r15, %rdi callq malloc movq %rax, %rbx leaq 40(%rsp), %rdi xorl %esi, %esi callq gettimeofday testl %ebp, %ebp jne .LBB1_9 # %bb.6: leal 31(%r14), %edi testl %r14d, %r14d cmovnsl %r14d, %edi sarl $5, %edi incl %edi movabsq $4294967296, %rdx # imm = 0x100000000 orq %rdx, %rdi orq $32, %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_8 # %bb.7: movq (%rsp), %rax movq %rax, 104(%rsp) movl %r12d, 12(%rsp) movl %r14d, 8(%rsp) leaq 104(%rsp), %rax movq %rax, 16(%rsp) leaq 12(%rsp), %rax movq %rax, 24(%rsp) leaq 8(%rsp), %rax movq %rax, 32(%rsp) leaq 88(%rsp), %rdi leaq 72(%rsp), %rsi leaq 64(%rsp), %rdx leaq 56(%rsp), %rcx callq __hipPopCallConfiguration movq 88(%rsp), %rsi movl 96(%rsp), %edx movq 72(%rsp), %rcx movl 80(%rsp), %r8d leaq 16(%rsp), %r9 movl $_Z5flopsPfii, %edi pushq 56(%rsp) .cfi_adjust_cfa_offset 8 pushq 72(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_8: callq hipDeviceSynchronize movl %eax, %ebp .LBB1_9: leaq 16(%rsp), %rdi xorl %esi, %esi callq gettimeofday movq 16(%rsp), %rax movq 24(%rsp), %rsi subq 40(%rsp), %rax imulq $1000000, %rax, %rax # imm = 0xF4240 subq 48(%rsp), %rsi addq %rax, %rsi movl $.L.str.1, %edi xorl %eax, %eax callq printf testl %ebp, %ebp jne .LBB1_11 # %bb.10: movq (%rsp), %rsi movq %rbx, %rdi movq %r15, %rdx movl $2, %ecx callq hipMemcpy movl %eax, %ebp .LBB1_11: testl %ebp, %ebp je .LBB1_13 # %bb.12: movl %ebp, %edi callq hipGetErrorString movl $.L.str.2, %edi movq %rax, %rsi xorl %eax, %eax callq printf .LBB1_13: # %._crit_edge leaq 40(%rsp), %rdi xorl %esi, %esi callq gettimeofday leaq 16(%rsp), %rdi xorl %esi, %esi callq gettimeofday movq 16(%rsp), %rax movq 24(%rsp), %rsi subq 40(%rsp), %rax imulq $1000000, %rax, %rax # imm = 0xF4240 subq 48(%rsp), %rsi addq %rax, %rsi movl $.L.str.3, %edi xorl %eax, %eax callq printf testl %r14d, %r14d jle .LBB1_14 # %bb.15: # %.lr.ph.preheader movl %r14d, %eax xorps %xmm0, %xmm0 xorl %ecx, %ecx .p2align 4, 0x90 .LBB1_16: # %.lr.ph # =>This Inner Loop Header: Depth=1 addss (%rbx,%rcx,4), %xmm0 incq %rcx cmpq %rcx, %rax jne .LBB1_16 # %bb.17: # %._crit_edge57.loopexit cvtss2sd %xmm0, %xmm0 jmp .LBB1_18 .LBB1_14: xorps %xmm0, %xmm0 .LBB1_18: # %._crit_edge57 movl $.L.str.4, %edi movb $1, %al callq printf movq %rbx, %rdi callq free movq (%rsp), %rdi callq hipFree callq hipDeviceReset xorl %eax, %eax addq $112, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z5flopsPfii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z5flopsPfii,@object # @_Z5flopsPfii .section .rodata,"a",@progbits .globl _Z5flopsPfii .p2align 3, 0x0 _Z5flopsPfii: .quad _Z20__device_stub__flopsPfii .size _Z5flopsPfii, 8 .type .L.str.1,@object # @.str.1 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.1: .asciz "%ld microseconds on GPU\n" .size .L.str.1, 25 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "ERROR: %s\n" .size .L.str.2, 11 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "%ld microseconds on CPU\n" .size .L.str.3, 25 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Total val: %f \n" .size .L.str.4, 16 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z5flopsPfii" .size .L__unnamed_1, 13 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "Optional arguments: (arg1) number of floats to add and divide, (arg2) number of threads " .size .Lstr, 89 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z20__device_stub__flopsPfii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z5flopsPfii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include<stdio.h> __managed__ int sum=0; __global__ void Array_sum(int *a,int *n) { int tid=threadIdx.x; if(tid<*n) atomicAdd(&sum,a[tid]); } int main() { int n=10,i; //printf("Enter N:"); //scanf("%d",&n); int a[n]; int *cuda_a,*cuda_n; for(i=0;i<n;i++) { a[i]=rand()%100; printf("%d ",a[i]); } printf("\n"); cudaMalloc((void**)&cuda_a,n*sizeof(int)); cudaMalloc((void**)&cuda_n,sizeof(int)); cudaMemcpy(cuda_a,a,n*sizeof(int),cudaMemcpyHostToDevice); cudaMemcpy(cuda_n,&n,sizeof(int),cudaMemcpyHostToDevice); Array_sum <<<1,n>>>(cuda_a,cuda_n); printf("Sum:%d\n",sum); cudaFree(cuda_a); cudaFree(cuda_n); return 0; }
code for sm_80 Function : _Z9Array_sumPiS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */ /* 0x000fe20000000f00 */ /*0020*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */ /* 0x000fe200078e00ff */ /*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */ /* 0x000fc80000000a00 */ /*0040*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */ /* 0x000ea8000c1e1900 */ /*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */ /* 0x000ea40000002100 */ /*0060*/ ISETP.GE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */ /* 0x004fda0003f06270 */ /*0070*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0080*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */ /* 0x000fd400000001ff */ /*0090*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */ /* 0x000fcc00078e0202 */ /*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */ /* 0x000ea2000c1e1900 */ /*00b0*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */ /* 0x000fe200038e0100 */ /*00c0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x0] ; /* 0x01000000ff047624 */ /* 0x000fe200078e00ff */ /*00d0*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */ /* 0x000fe200080e0000 */ /*00e0*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */ /* 0x000e220000000000 */ /*00f0*/ MOV R5, c[0x4][0x4] ; /* 0x0100010000057a02 */ /* 0x000fc80000000f00 */ /*0100*/ ISETP.EQ.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */ /* 0x001fe2000bf02070 */ /*0110*/ REDUX.SUM UR5, R2 ; /* 0x00000000020573c4 */ /* 0x004e24000000c000 */ /*0120*/ IMAD.U32 R7, RZ, RZ, UR5 ; /* 0x00000005ff077e24 */ /* 0x001fd4000f8e00ff */ /*0130*/ @P0 RED.E.ADD.STRONG.GPU [R4.64], R7 ; /* 0x000000070400098e */ /* 0x000fe2000c10e186 */ /*0140*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0150*/ BRA 0x150; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include<stdio.h> __managed__ int sum=0; __global__ void Array_sum(int *a,int *n) { int tid=threadIdx.x; if(tid<*n) atomicAdd(&sum,a[tid]); } int main() { int n=10,i; //printf("Enter N:"); //scanf("%d",&n); int a[n]; int *cuda_a,*cuda_n; for(i=0;i<n;i++) { a[i]=rand()%100; printf("%d ",a[i]); } printf("\n"); cudaMalloc((void**)&cuda_a,n*sizeof(int)); cudaMalloc((void**)&cuda_n,sizeof(int)); cudaMemcpy(cuda_a,a,n*sizeof(int),cudaMemcpyHostToDevice); cudaMemcpy(cuda_n,&n,sizeof(int),cudaMemcpyHostToDevice); Array_sum <<<1,n>>>(cuda_a,cuda_n); printf("Sum:%d\n",sum); cudaFree(cuda_a); cudaFree(cuda_n); return 0; }
.file "tmpxft_000ace37_00000000-6_q1.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z30__device_stub__Z9Array_sumPiS_PiS_ .type _Z30__device_stub__Z9Array_sumPiS_PiS_, @function _Z30__device_stub__Z9Array_sumPiS_PiS_: .LFB2082: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z9Array_sumPiS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z30__device_stub__Z9Array_sumPiS_PiS_, .-_Z30__device_stub__Z9Array_sumPiS_PiS_ .globl _Z9Array_sumPiS_ .type _Z9Array_sumPiS_, @function _Z9Array_sumPiS_: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z30__device_stub__Z9Array_sumPiS_PiS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z9Array_sumPiS_, .-_Z9Array_sumPiS_ .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "%d " .LC1: .string "\n" .LC2: .string "Sum:%d\n" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $104, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 88(%rsp) xorl %eax, %eax movl $10, 4(%rsp) movl $0, %ebx leaq .LC0(%rip), %rbp .L12: call rand@PLT movslq %eax, %rdx imulq $1374389535, %rdx, %rdx sarq $37, %rdx movl %eax, %ecx sarl $31, %ecx subl %ecx, %edx imull $100, %edx, %ecx subl %ecx, %eax movl %eax, %edx movl %eax, 48(%rsp,%rbx,4) movq %rbp, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $1, %rbx cmpl %ebx, 4(%rsp) jg .L12 leaq .LC1(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movslq 4(%rsp), %rsi salq $2, %rsi leaq 8(%rsp), %rdi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $4, %esi call cudaMalloc@PLT movslq 4(%rsp), %rdx salq $2, %rdx leaq 48(%rsp), %rsi movl $1, %ecx movq 8(%rsp), %rdi call cudaMemcpy@PLT leaq 4(%rsp), %rsi movl $1, %ecx movl $4, %edx movq 16(%rsp), %rdi call cudaMemcpy@PLT movl 4(%rsp), %eax movl %eax, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 24(%rsp) movl $1, 28(%rsp) movl $1, 32(%rsp) movl $0, %r9d movl $0, %r8d movq 36(%rsp), %rdx movl $1, %ecx movq 24(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L18 .L13: cmpb $0, _ZL22__nv_inited_managed_rt(%rip) je .L19 .L14: movq _ZL3sum(%rip), %rax movl (%rax), %edx leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 88(%rsp), %rax subq %fs:40, %rax jne .L20 movl $0, %eax addq $104, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L18: .cfi_restore_state movq 16(%rsp), %rsi movq 8(%rsp), %rdi call _Z30__device_stub__Z9Array_sumPiS_PiS_ jmp .L13 .L19: movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi call __cudaInitModule@PLT movb %al, _ZL22__nv_inited_managed_rt(%rip) jmp .L14 .L20: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC3: .string "_Z9Array_sumPiS_" .LC4: .string "sum" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) movq %rax, _ZL32__nv_fatbinhandle_for_managed_rt(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC3(%rip), %rdx movq %rdx, %rcx leaq _Z9Array_sumPiS_(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $4, %r9d movl $0, %r8d leaq .LC4(%rip), %rdx movq %rdx, %rcx leaq _ZL3sum(%rip), %rsi movq %rbx, %rdi call __cudaRegisterManagedVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section __nv_managed_data__,"aw" .align 8 .type _ZL3sum, @object .size _ZL3sum, 8 _ZL3sum: .zero 8 .local _ZL32__nv_fatbinhandle_for_managed_rt .comm _ZL32__nv_fatbinhandle_for_managed_rt,8,8 .local _ZL22__nv_inited_managed_rt .comm _ZL22__nv_inited_managed_rt,1,1 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include<stdio.h> __managed__ int sum=0; __global__ void Array_sum(int *a,int *n) { int tid=threadIdx.x; if(tid<*n) atomicAdd(&sum,a[tid]); } int main() { int n=10,i; //printf("Enter N:"); //scanf("%d",&n); int a[n]; int *cuda_a,*cuda_n; for(i=0;i<n;i++) { a[i]=rand()%100; printf("%d ",a[i]); } printf("\n"); cudaMalloc((void**)&cuda_a,n*sizeof(int)); cudaMalloc((void**)&cuda_n,sizeof(int)); cudaMemcpy(cuda_a,a,n*sizeof(int),cudaMemcpyHostToDevice); cudaMemcpy(cuda_n,&n,sizeof(int),cudaMemcpyHostToDevice); Array_sum <<<1,n>>>(cuda_a,cuda_n); printf("Sum:%d\n",sum); cudaFree(cuda_a); cudaFree(cuda_n); return 0; }
#include <hip/hip_runtime.h> #include<stdio.h> __managed__ int sum=0; __global__ void Array_sum(int *a,int *n) { int tid=threadIdx.x; if(tid<*n) atomicAdd(&sum,a[tid]); } int main() { int n=10,i; //printf("Enter N:"); //scanf("%d",&n); int a[n]; int *cuda_a,*cuda_n; for(i=0;i<n;i++) { a[i]=rand()%100; printf("%d ",a[i]); } printf("\n"); hipMalloc((void**)&cuda_a,n*sizeof(int)); hipMalloc((void**)&cuda_n,sizeof(int)); hipMemcpy(cuda_a,a,n*sizeof(int),hipMemcpyHostToDevice); hipMemcpy(cuda_n,&n,sizeof(int),hipMemcpyHostToDevice); Array_sum <<<1,n>>>(cuda_a,cuda_n); printf("Sum:%d\n",sum); hipFree(cuda_a); hipFree(cuda_n); return 0; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include<stdio.h> __managed__ int sum=0; __global__ void Array_sum(int *a,int *n) { int tid=threadIdx.x; if(tid<*n) atomicAdd(&sum,a[tid]); } int main() { int n=10,i; //printf("Enter N:"); //scanf("%d",&n); int a[n]; int *cuda_a,*cuda_n; for(i=0;i<n;i++) { a[i]=rand()%100; printf("%d ",a[i]); } printf("\n"); hipMalloc((void**)&cuda_a,n*sizeof(int)); hipMalloc((void**)&cuda_n,sizeof(int)); hipMemcpy(cuda_a,a,n*sizeof(int),hipMemcpyHostToDevice); hipMemcpy(cuda_n,&n,sizeof(int),hipMemcpyHostToDevice); Array_sum <<<1,n>>>(cuda_a,cuda_n); printf("Sum:%d\n",sum); hipFree(cuda_a); hipFree(cuda_n); return 0; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z9Array_sumPiS_ .globl _Z9Array_sumPiS_ .p2align 8 .type _Z9Array_sumPiS_,@function _Z9Array_sumPiS_: s_load_b64 s[2:3], s[0:1], 0x8 s_waitcnt lgkmcnt(0) s_load_b32 s2, s[2:3], 0x0 s_waitcnt lgkmcnt(0) v_cmp_gt_i32_e32 vcc_lo, s2, v0 s_and_saveexec_b32 s2, vcc_lo s_cbranch_execz .LBB0_5 s_load_b64 s[0:1], s[0:1], 0x0 v_lshlrev_b32_e32 v0, 2, v0 s_mov_b32 s3, exec_lo s_mov_b32 s2, 0 s_waitcnt lgkmcnt(0) global_load_b32 v0, v0, s[0:1] s_getpc_b64 s[0:1] s_add_u32 s0, s0, sum@rel32@lo+4 s_addc_u32 s1, s1, sum@rel32@hi+12 s_load_b64 s[0:1], s[0:1], 0x0 .LBB0_2: s_ctz_i32_b32 s4, s3 s_waitcnt vmcnt(0) v_readlane_b32 s5, v0, s4 s_lshl_b32 s4, 1, s4 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_and_not1_b32 s3, s3, s4 s_add_i32 s2, s2, s5 s_cmp_lg_u32 s3, 0 s_cbranch_scc1 .LBB0_2 v_mbcnt_lo_u32_b32 v0, exec_lo, 0 s_mov_b32 s3, exec_lo s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v0 s_xor_b32 s3, exec_lo, s3 s_cbranch_execz .LBB0_5 v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 s_waitcnt lgkmcnt(0) global_atomic_add_u32 v0, v1, s[0:1] .LBB0_5: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9Array_sumPiS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 2 .amdhsa_next_free_sgpr 6 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z9Array_sumPiS_, .Lfunc_end0-_Z9Array_sumPiS_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .protected sum.managed .type sum.managed,@object .section .bss,"aw",@nobits .globl sum.managed .p2align 2, 0x0 sum.managed: .long 0 .size sum.managed, 4 .protected sum .type sum,@object .globl sum .p2align 3, 0x0 sum: .quad 0 .size sum, 8 .type __hip_cuid_,@object .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym sum.managed .addrsig_sym sum .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9Array_sumPiS_ .private_segment_fixed_size: 0 .sgpr_count: 8 .sgpr_spill_count: 0 .symbol: _Z9Array_sumPiS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 2 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include<stdio.h> __managed__ int sum=0; __global__ void Array_sum(int *a,int *n) { int tid=threadIdx.x; if(tid<*n) atomicAdd(&sum,a[tid]); } int main() { int n=10,i; //printf("Enter N:"); //scanf("%d",&n); int a[n]; int *cuda_a,*cuda_n; for(i=0;i<n;i++) { a[i]=rand()%100; printf("%d ",a[i]); } printf("\n"); hipMalloc((void**)&cuda_a,n*sizeof(int)); hipMalloc((void**)&cuda_n,sizeof(int)); hipMemcpy(cuda_a,a,n*sizeof(int),hipMemcpyHostToDevice); hipMemcpy(cuda_n,&n,sizeof(int),hipMemcpyHostToDevice); Array_sum <<<1,n>>>(cuda_a,cuda_n); printf("Sum:%d\n",sum); hipFree(cuda_a); hipFree(cuda_n); return 0; }
.text .file "q1.hip" .globl _Z24__device_stub__Array_sumPiS_ # -- Begin function _Z24__device_stub__Array_sumPiS_ .p2align 4, 0x90 .type _Z24__device_stub__Array_sumPiS_,@function _Z24__device_stub__Array_sumPiS_: # @_Z24__device_stub__Array_sumPiS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z9Array_sumPiS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z24__device_stub__Array_sumPiS_, .Lfunc_end0-_Z24__device_stub__Array_sumPiS_ .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $152, %rsp .cfi_def_cfa_offset 176 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movq %rsp, %rbx movl $10, 12(%rsp) movl $10, %eax testl $10, %eax jle .LBB1_3 # %bb.1: # %.lr.ph.preheader xorl %r14d, %r14d .p2align 4, 0x90 .LBB1_2: # %.lr.ph # =>This Inner Loop Header: Depth=1 callq rand movslq %eax, %rsi imulq $1374389535, %rsi, %rax # imm = 0x51EB851F movq %rax, %rcx shrq $63, %rcx sarq $37, %rax addl %ecx, %eax imull $100, %eax, %eax subl %eax, %esi movl %esi, 112(%rsp,%r14,4) movl $.L.str, %edi # kill: def $esi killed $esi killed $rsi xorl %eax, %eax callq printf incq %r14 movslq 12(%rsp), %rax cmpq %rax, %r14 jl .LBB1_2 .LBB1_3: # %._crit_edge movl $10, %edi callq putchar@PLT movslq 12(%rsp), %rsi shlq $2, %rsi leaq 24(%rsp), %rdi callq hipMalloc leaq 16(%rsp), %rdi movl $4, %esi callq hipMalloc movq 24(%rsp), %rdi movslq 12(%rsp), %rdx shlq $2, %rdx leaq 112(%rsp), %rsi movl $1, %ecx callq hipMemcpy movq 16(%rsp), %rdi leaq 12(%rsp), %rsi movl $4, %edx movl $1, %ecx callq hipMemcpy movl 12(%rsp), %edx movabsq $4294967296, %rdi # imm = 0x100000000 orq %rdi, %rdx orq $1, %rdi movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_5 # %bb.4: movq 24(%rsp), %rax movq 16(%rsp), %rcx movq %rax, 88(%rsp) movq %rcx, 80(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z9Array_sumPiS_, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_5: movq sum(%rip), %rax movl (%rax), %esi movl $.L.str.2, %edi xorl %eax, %eax callq printf movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq %rbx, %rsp xorl %eax, %eax addq $152, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9Array_sumPiS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $sum, %esi movl $sum.managed, %edx movl $.L__unnamed_2, %ecx movl $4, %r8d movq %rbx, %rdi movl $4, %r9d callq __hipRegisterManagedVar movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type sum.managed,@object # @sum.managed .local sum.managed .comm sum.managed,4,4 .type _Z9Array_sumPiS_,@object # @_Z9Array_sumPiS_ .section .rodata,"a",@progbits .globl _Z9Array_sumPiS_ .p2align 3, 0x0 _Z9Array_sumPiS_: .quad _Z24__device_stub__Array_sumPiS_ .size _Z9Array_sumPiS_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "%d " .size .L.str, 4 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Sum:%d\n" .size .L.str.2, 8 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z9Array_sumPiS_" .size .L__unnamed_1, 17 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "sum" .size .L__unnamed_2, 4 .type sum,@object # @sum .local sum .comm sum,8,8 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z24__device_stub__Array_sumPiS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym sum.managed .addrsig_sym _Z9Array_sumPiS_ .addrsig_sym sum .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z9Array_sumPiS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */ /* 0x000fe20000000f00 */ /*0020*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */ /* 0x000fe200078e00ff */ /*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */ /* 0x000fc80000000a00 */ /*0040*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */ /* 0x000ea8000c1e1900 */ /*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */ /* 0x000ea40000002100 */ /*0060*/ ISETP.GE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */ /* 0x004fda0003f06270 */ /*0070*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0080*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */ /* 0x000fd400000001ff */ /*0090*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */ /* 0x000fcc00078e0202 */ /*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */ /* 0x000ea2000c1e1900 */ /*00b0*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */ /* 0x000fe200038e0100 */ /*00c0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x0] ; /* 0x01000000ff047624 */ /* 0x000fe200078e00ff */ /*00d0*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */ /* 0x000fe200080e0000 */ /*00e0*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */ /* 0x000e220000000000 */ /*00f0*/ MOV R5, c[0x4][0x4] ; /* 0x0100010000057a02 */ /* 0x000fc80000000f00 */ /*0100*/ ISETP.EQ.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */ /* 0x001fe2000bf02070 */ /*0110*/ REDUX.SUM UR5, R2 ; /* 0x00000000020573c4 */ /* 0x004e24000000c000 */ /*0120*/ IMAD.U32 R7, RZ, RZ, UR5 ; /* 0x00000005ff077e24 */ /* 0x001fd4000f8e00ff */ /*0130*/ @P0 RED.E.ADD.STRONG.GPU [R4.64], R7 ; /* 0x000000070400098e */ /* 0x000fe2000c10e186 */ /*0140*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0150*/ BRA 0x150; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z9Array_sumPiS_ .globl _Z9Array_sumPiS_ .p2align 8 .type _Z9Array_sumPiS_,@function _Z9Array_sumPiS_: s_load_b64 s[2:3], s[0:1], 0x8 s_waitcnt lgkmcnt(0) s_load_b32 s2, s[2:3], 0x0 s_waitcnt lgkmcnt(0) v_cmp_gt_i32_e32 vcc_lo, s2, v0 s_and_saveexec_b32 s2, vcc_lo s_cbranch_execz .LBB0_5 s_load_b64 s[0:1], s[0:1], 0x0 v_lshlrev_b32_e32 v0, 2, v0 s_mov_b32 s3, exec_lo s_mov_b32 s2, 0 s_waitcnt lgkmcnt(0) global_load_b32 v0, v0, s[0:1] s_getpc_b64 s[0:1] s_add_u32 s0, s0, sum@rel32@lo+4 s_addc_u32 s1, s1, sum@rel32@hi+12 s_load_b64 s[0:1], s[0:1], 0x0 .LBB0_2: s_ctz_i32_b32 s4, s3 s_waitcnt vmcnt(0) v_readlane_b32 s5, v0, s4 s_lshl_b32 s4, 1, s4 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_and_not1_b32 s3, s3, s4 s_add_i32 s2, s2, s5 s_cmp_lg_u32 s3, 0 s_cbranch_scc1 .LBB0_2 v_mbcnt_lo_u32_b32 v0, exec_lo, 0 s_mov_b32 s3, exec_lo s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v0 s_xor_b32 s3, exec_lo, s3 s_cbranch_execz .LBB0_5 v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 s_waitcnt lgkmcnt(0) global_atomic_add_u32 v0, v1, s[0:1] .LBB0_5: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9Array_sumPiS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 2 .amdhsa_next_free_sgpr 6 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z9Array_sumPiS_, .Lfunc_end0-_Z9Array_sumPiS_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .protected sum.managed .type sum.managed,@object .section .bss,"aw",@nobits .globl sum.managed .p2align 2, 0x0 sum.managed: .long 0 .size sum.managed, 4 .protected sum .type sum,@object .globl sum .p2align 3, 0x0 sum: .quad 0 .size sum, 8 .type __hip_cuid_,@object .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym sum.managed .addrsig_sym sum .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9Array_sumPiS_ .private_segment_fixed_size: 0 .sgpr_count: 8 .sgpr_spill_count: 0 .symbol: _Z9Array_sumPiS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 2 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_000ace37_00000000-6_q1.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z30__device_stub__Z9Array_sumPiS_PiS_ .type _Z30__device_stub__Z9Array_sumPiS_PiS_, @function _Z30__device_stub__Z9Array_sumPiS_PiS_: .LFB2082: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z9Array_sumPiS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z30__device_stub__Z9Array_sumPiS_PiS_, .-_Z30__device_stub__Z9Array_sumPiS_PiS_ .globl _Z9Array_sumPiS_ .type _Z9Array_sumPiS_, @function _Z9Array_sumPiS_: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z30__device_stub__Z9Array_sumPiS_PiS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z9Array_sumPiS_, .-_Z9Array_sumPiS_ .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "%d " .LC1: .string "\n" .LC2: .string "Sum:%d\n" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $104, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 88(%rsp) xorl %eax, %eax movl $10, 4(%rsp) movl $0, %ebx leaq .LC0(%rip), %rbp .L12: call rand@PLT movslq %eax, %rdx imulq $1374389535, %rdx, %rdx sarq $37, %rdx movl %eax, %ecx sarl $31, %ecx subl %ecx, %edx imull $100, %edx, %ecx subl %ecx, %eax movl %eax, %edx movl %eax, 48(%rsp,%rbx,4) movq %rbp, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $1, %rbx cmpl %ebx, 4(%rsp) jg .L12 leaq .LC1(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movslq 4(%rsp), %rsi salq $2, %rsi leaq 8(%rsp), %rdi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $4, %esi call cudaMalloc@PLT movslq 4(%rsp), %rdx salq $2, %rdx leaq 48(%rsp), %rsi movl $1, %ecx movq 8(%rsp), %rdi call cudaMemcpy@PLT leaq 4(%rsp), %rsi movl $1, %ecx movl $4, %edx movq 16(%rsp), %rdi call cudaMemcpy@PLT movl 4(%rsp), %eax movl %eax, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 24(%rsp) movl $1, 28(%rsp) movl $1, 32(%rsp) movl $0, %r9d movl $0, %r8d movq 36(%rsp), %rdx movl $1, %ecx movq 24(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L18 .L13: cmpb $0, _ZL22__nv_inited_managed_rt(%rip) je .L19 .L14: movq _ZL3sum(%rip), %rax movl (%rax), %edx leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 88(%rsp), %rax subq %fs:40, %rax jne .L20 movl $0, %eax addq $104, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L18: .cfi_restore_state movq 16(%rsp), %rsi movq 8(%rsp), %rdi call _Z30__device_stub__Z9Array_sumPiS_PiS_ jmp .L13 .L19: movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi call __cudaInitModule@PLT movb %al, _ZL22__nv_inited_managed_rt(%rip) jmp .L14 .L20: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC3: .string "_Z9Array_sumPiS_" .LC4: .string "sum" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) movq %rax, _ZL32__nv_fatbinhandle_for_managed_rt(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC3(%rip), %rdx movq %rdx, %rcx leaq _Z9Array_sumPiS_(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $4, %r9d movl $0, %r8d leaq .LC4(%rip), %rdx movq %rdx, %rcx leaq _ZL3sum(%rip), %rsi movq %rbx, %rdi call __cudaRegisterManagedVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section __nv_managed_data__,"aw" .align 8 .type _ZL3sum, @object .size _ZL3sum, 8 _ZL3sum: .zero 8 .local _ZL32__nv_fatbinhandle_for_managed_rt .comm _ZL32__nv_fatbinhandle_for_managed_rt,8,8 .local _ZL22__nv_inited_managed_rt .comm _ZL22__nv_inited_managed_rt,1,1 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "q1.hip" .globl _Z24__device_stub__Array_sumPiS_ # -- Begin function _Z24__device_stub__Array_sumPiS_ .p2align 4, 0x90 .type _Z24__device_stub__Array_sumPiS_,@function _Z24__device_stub__Array_sumPiS_: # @_Z24__device_stub__Array_sumPiS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z9Array_sumPiS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z24__device_stub__Array_sumPiS_, .Lfunc_end0-_Z24__device_stub__Array_sumPiS_ .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $152, %rsp .cfi_def_cfa_offset 176 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movq %rsp, %rbx movl $10, 12(%rsp) movl $10, %eax testl $10, %eax jle .LBB1_3 # %bb.1: # %.lr.ph.preheader xorl %r14d, %r14d .p2align 4, 0x90 .LBB1_2: # %.lr.ph # =>This Inner Loop Header: Depth=1 callq rand movslq %eax, %rsi imulq $1374389535, %rsi, %rax # imm = 0x51EB851F movq %rax, %rcx shrq $63, %rcx sarq $37, %rax addl %ecx, %eax imull $100, %eax, %eax subl %eax, %esi movl %esi, 112(%rsp,%r14,4) movl $.L.str, %edi # kill: def $esi killed $esi killed $rsi xorl %eax, %eax callq printf incq %r14 movslq 12(%rsp), %rax cmpq %rax, %r14 jl .LBB1_2 .LBB1_3: # %._crit_edge movl $10, %edi callq putchar@PLT movslq 12(%rsp), %rsi shlq $2, %rsi leaq 24(%rsp), %rdi callq hipMalloc leaq 16(%rsp), %rdi movl $4, %esi callq hipMalloc movq 24(%rsp), %rdi movslq 12(%rsp), %rdx shlq $2, %rdx leaq 112(%rsp), %rsi movl $1, %ecx callq hipMemcpy movq 16(%rsp), %rdi leaq 12(%rsp), %rsi movl $4, %edx movl $1, %ecx callq hipMemcpy movl 12(%rsp), %edx movabsq $4294967296, %rdi # imm = 0x100000000 orq %rdi, %rdx orq $1, %rdi movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_5 # %bb.4: movq 24(%rsp), %rax movq 16(%rsp), %rcx movq %rax, 88(%rsp) movq %rcx, 80(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z9Array_sumPiS_, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_5: movq sum(%rip), %rax movl (%rax), %esi movl $.L.str.2, %edi xorl %eax, %eax callq printf movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq %rbx, %rsp xorl %eax, %eax addq $152, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9Array_sumPiS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $sum, %esi movl $sum.managed, %edx movl $.L__unnamed_2, %ecx movl $4, %r8d movq %rbx, %rdi movl $4, %r9d callq __hipRegisterManagedVar movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type sum.managed,@object # @sum.managed .local sum.managed .comm sum.managed,4,4 .type _Z9Array_sumPiS_,@object # @_Z9Array_sumPiS_ .section .rodata,"a",@progbits .globl _Z9Array_sumPiS_ .p2align 3, 0x0 _Z9Array_sumPiS_: .quad _Z24__device_stub__Array_sumPiS_ .size _Z9Array_sumPiS_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "%d " .size .L.str, 4 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Sum:%d\n" .size .L.str.2, 8 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z9Array_sumPiS_" .size .L__unnamed_1, 17 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "sum" .size .L__unnamed_2, 4 .type sum,@object # @sum .local sum .comm sum,8,8 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z24__device_stub__Array_sumPiS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym sum.managed .addrsig_sym _Z9Array_sumPiS_ .addrsig_sym sum .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include <stdio.h> #include <stdlib.h> #include <time.h> #include <assert.h> #include <sys/time.h> // __global__ void merge(float *data, float *work, int k) // { // int index = blockIdx.x * blockDim.x + threadIdx.x; // int l = index * k; // int m = l + k / 2; // int r = l + k; // int first = l; // int second = m; // for (int i = l; i < r; i++) // { // if (first < m && (second >= r || data[first] <= data[second])) // { // work[i] = data[first]; // first += 1; // } // else // { // work[i] = data[second]; // second += 1; // } // } // } // __global__ void parallel_merge(float *data, float *work) // { // uint half = blockDim.x >> 1; // uint pos = blockIdx.x * blockDim.x; // uint left_array = threadIdx.x < half ? 1 : 0; // float cur = data[pos + threadIdx.x]; // uint i = 0; // uint j = half; // if (left_array) // { // while (i < j) // { // uint mid = i + (j - i) / 2; // if (cur <= data[pos + half + mid]) // j = mid; // else // i = mid + 1; // } // work[pos + threadIdx.x + i] = cur; // } // else // { // while (i < j) // { // uint mid = i + (j - i) / 2; // if (cur < data[pos + mid]) // j = mid; // else // i = mid + 1; // } // work[pos + threadIdx.x - half + i] = cur; // } // } __global__ void parallel_merge(float *data, float *work, int stride) { uint index = threadIdx.x * stride; uint pos = blockIdx.x * blockDim.x * stride; uint half = blockDim.x * stride >> 1; uint left_array = index < half ? 1 : 0; for (uint s = 0; s < stride; s++) { float cur = data[pos + index + s]; uint i = 0; uint j = half; if (left_array) { while (i < j) { uint mid = i + (j - i) / 2; if (cur <= data[pos + half + mid]) j = mid; else i = mid + 1; } work[pos + index + s + i] = cur; } else { while (i < j) { uint mid = i + (j - i) / 2; if (cur < data[pos + mid]) j = mid; else i = mid + 1; } work[pos + index + s - half + i] = cur; } } } int cuda_sort(int number_of_elements, float *a) { cudaError_t cudaStatus; cudaStatus = cudaSetDevice(0); if (cudaStatus != cudaSuccess) { fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?"); return 1; } float *d_a, *d_b; cudaMalloc((void **)&d_a, number_of_elements * sizeof(float)); cudaMalloc((void **)&d_b, number_of_elements * sizeof(float)); cudaMemcpy(d_a, a, number_of_elements * sizeof(float), cudaMemcpyHostToDevice); int level = 0; for (int k = 2; k <= number_of_elements; k = 2 * k) { int num_merges = number_of_elements / k; if (k <= 1024) { if (level % 2 == 0) parallel_merge<<<num_merges, k>>>(d_a, d_b, 1); else parallel_merge<<<num_merges, k>>>(d_b, d_a, 1); } else { if (level % 2 == 0) parallel_merge<<<num_merges, 1024>>>(d_a, d_b, k / 1024); else parallel_merge<<<num_merges, 1024>>>(d_b, d_a, k / 1024); } cudaDeviceSynchronize(); level += 1; } if (level % 2 == 0) cudaMemcpy(a, d_a, number_of_elements * sizeof(float), cudaMemcpyDeviceToHost); else cudaMemcpy(a, d_b, number_of_elements * sizeof(float), cudaMemcpyDeviceToHost); cudaFree(d_a); cudaFree(d_b); return 0; }
code for sm_80 Function : _Z14parallel_mergePfS_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */ /* 0x000fda0003f05270 */ /*0020*/ @!P0 EXIT ; /* 0x000000000000894d */ /* 0x000fea0003800000 */ /*0030*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */ /* 0x000fe200078e00ff */ /*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */ /* 0x000e220000002500 */ /*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe40000000a00 */ /*0060*/ IMAD R5, R6, c[0x0][0x0], RZ ; /* 0x0000000006057a24 */ /* 0x000fe200078e02ff */ /*0070*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e680000002100 */ /*0080*/ SHF.R.U32.HI R5, RZ, 0x1, R5 ; /* 0x00000001ff057819 */ /* 0x000fc80000011605 */ /*0090*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */ /* 0x000fe20003f05270 */ /*00a0*/ IMAD R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a24 */ /* 0x001fd800078e02ff */ /*00b0*/ @!P0 BRA 0x3a0 ; /* 0x000002e000008947 */ /* 0x000fea0003800000 */ /*00c0*/ IMAD R2, R3, c[0x0][0x170], RZ ; /* 0x00005c0003027a24 */ /* 0x002fe200078e02ff */ /*00d0*/ IADD3 R13, R0.reuse, R3, RZ ; /* 0x00000003000d7210 */ /* 0x040fe20007ffe0ff */ /*00e0*/ IMAD R3, R0, c[0x0][0x170], R5 ; /* 0x00005c0000037a24 */ /* 0x000fe400078e0205 */ /*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */ /* 0x000fe400078e00ff */ /*0100*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */ /* 0x000fe400078e00ff */ /*0110*/ IMAD R8, R13, c[0x0][0x170], R4 ; /* 0x00005c000d087a24 */ /* 0x000fc800078e0204 */ /*0120*/ IMAD.WIDE.U32 R6, R8, R15, c[0x0][0x160] ; /* 0x0000580008067625 */ /* 0x001fca00078e000f */ /*0130*/ LDG.E R17, [R6.64] ; /* 0x0000000406117981 */ /* 0x000162000c1e1900 */ /*0140*/ ISETP.GE.U32.AND P1, PT, R2, R5, PT ; /* 0x000000050200720c */ /* 0x000fe20003f26070 */ /*0150*/ BSSY B0, 0x350 ; /* 0x000001f000007945 */ /* 0x000fe20003800000 */ /*0160*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */ /* 0x000fe20007ffe0ff */ /*0170*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */ /* 0x000fc600000001ff */ /*0180*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */ /* 0x000fce0003f06070 */ /*0190*/ @!P1 BRA 0x290 ; /* 0x000000f000009947 */ /* 0x000fea0003800000 */ /*01a0*/ BSSY B1, 0x270 ; /* 0x000000c000017945 */ /* 0x001fe20003800000 */ /*01b0*/ IMAD.MOV.U32 R10, RZ, RZ, R5 ; /* 0x000000ffff0a7224 */ /* 0x000fc800078e0005 */ /*01c0*/ IMAD.IADD R6, R10, 0x1, -R9 ; /* 0x000000010a067824 */ /* 0x000fca00078e0a09 */ /*01d0*/ LEA.HI R11, R6, R9, RZ, 0x1f ; /* 0x00000009060b7211 */ /* 0x000fca00078ff8ff */ /*01e0*/ IMAD R6, R0, c[0x0][0x170], R11 ; /* 0x00005c0000067a24 */ /* 0x000fc800078e020b */ /*01f0*/ IMAD.WIDE.U32 R6, R6, R15, c[0x0][0x160] ; /* 0x0000580006067625 */ /* 0x000fcc00078e000f */ /*0200*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */ /* 0x000ea4000c1e1900 */ /*0210*/ FSETP.GEU.AND P1, PT, R17, R6, PT ; /* 0x000000061100720b */ /* 0x024fc80003f2e000 */ /*0220*/ SEL R10, R11, R10, !P1 ; /* 0x0000000a0b0a7207 */ /* 0x000fd20004800000 */ /*0230*/ @P1 IADD3 R9, R11, 0x1, RZ ; /* 0x000000010b091810 */ /* 0x000fc80007ffe0ff */ /*0240*/ ISETP.GT.U32.AND P1, PT, R10, R9, PT ; /* 0x000000090a00720c */ /* 0x000fda0003f24070 */ /*0250*/ @P1 BRA 0x1c0 ; /* 0xffffff6000001947 */ /* 0x000fea000383ffff */ /*0260*/ BSYNC B1 ; /* 0x0000000000017941 */ /* 0x000fea0003800000 */ /*0270*/ IADD3 R8, -R5, R8, RZ ; /* 0x0000000805087210 */ /* 0x000fe20007ffe1ff */ /*0280*/ BRA 0x340 ; /* 0x000000b000007947 */ /* 0x000fea0003800000 */ /*0290*/ IMAD.MOV.U32 R10, RZ, RZ, R5 ; /* 0x000000ffff0a7224 */ /* 0x001fc800078e0005 */ /*02a0*/ IMAD.IADD R6, R10, 0x1, -R9 ; /* 0x000000010a067824 */ /* 0x000fca00078e0a09 */ /*02b0*/ LEA.HI R11, R6, R9, RZ, 0x1f ; /* 0x00000009060b7211 */ /* 0x000fc800078ff8ff */ /*02c0*/ IADD3 R6, R3, R11, RZ ; /* 0x0000000b03067210 */ /* 0x000fca0007ffe0ff */ /*02d0*/ IMAD.WIDE.U32 R6, R6, R15, c[0x0][0x160] ; /* 0x0000580006067625 */ /* 0x000fcc00078e000f */ /*02e0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */ /* 0x000ea4000c1e1900 */ /*02f0*/ FSETP.GTU.AND P1, PT, R17, R6, PT ; /* 0x000000061100720b */ /* 0x024fc80003f2c000 */ /*0300*/ SEL R10, R11, R10, !P1 ; /* 0x0000000a0b0a7207 */ /* 0x000fd20004800000 */ /*0310*/ @P1 IADD3 R9, R11, 0x1, RZ ; /* 0x000000010b091810 */ /* 0x000fc80007ffe0ff */ /*0320*/ ISETP.GT.U32.AND P1, PT, R10, R9, PT ; /* 0x000000090a00720c */ /* 0x000fda0003f24070 */ /*0330*/ @P1 BRA 0x2a0 ; /* 0xffffff6000001947 */ /* 0x000fea000383ffff */ /*0340*/ BSYNC B0 ; /* 0x0000000000007941 */ /* 0x000fea0003800000 */ /*0350*/ IMAD.IADD R6, R9, 0x1, R8 ; /* 0x0000000109067824 */ /* 0x000fc800078e0208 */ /*0360*/ IMAD.WIDE.U32 R6, R6, R15, c[0x0][0x168] ; /* 0x00005a0006067625 */ /* 0x000fca00078e000f */ /*0370*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */ /* 0x0001e2000c101904 */ /*0380*/ @!P0 BRA 0x100 ; /* 0xfffffd7000008947 */ /* 0x000fea000383ffff */ /*0390*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*03a0*/ IADD3 R4, R6.reuse, -0x1, RZ ; /* 0xffffffff06047810 */ /* 0x040fe40007ffe0ff */ /*03b0*/ LOP3.LUT R2, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306027812 */ /* 0x000fe400078ec0ff */ /*03c0*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */ /* 0x000fe20003f26070 */ /*03d0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */ /* 0x000fe200078e00ff */ /*03e0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */ /* 0x000fd60003f05270 */ /*03f0*/ @!P1 BRA 0x5d0 ; /* 0x000001d000009947 */ /* 0x000fea0003800000 */ /*0400*/ IADD3 R7, R0, R3, RZ ; /* 0x0000000300077210 */ /* 0x002fe20007ffe0ff */ /*0410*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */ /* 0x000fe200078e00ff */ /*0420*/ IADD3 R5, R2, -c[0x0][0x170], RZ ; /* 0x80005c0002057a10 */ /* 0x000fc60007ffe0ff */ /*0430*/ IMAD R6, R7, R6, 0x3 ; /* 0x0000000307067424 */ /* 0x000fca00078e0206 */ /*0440*/ IADD3 R10, R6, -0x3, RZ ; /* 0xfffffffd060a7810 */ /* 0x002fe20007ffe0ff */ /*0450*/ IMAD.MOV.U32 R21, RZ, RZ, 0x4 ; /* 0x00000004ff157424 */ /* 0x000fc800078e00ff */ /*0460*/ IMAD.WIDE.U32 R8, R10, R21, c[0x0][0x160] ; /* 0x000058000a087625 */ /* 0x000fca00078e0015 */ /*0470*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */ /* 0x000ea2000c1e1900 */ /*0480*/ IADD3 R14, R6, -0x2, RZ ; /* 0xfffffffe060e7810 */ /* 0x000fe20007ffe0ff */ /*0490*/ IMAD.WIDE.U32 R10, R10, R21, c[0x0][0x168] ; /* 0x00005a000a0a7625 */ /* 0x000fc800078e0015 */ /*04a0*/ IMAD.WIDE.U32 R12, R14, R21.reuse, c[0x0][0x160] ; /* 0x000058000e0c7625 */ /* 0x080fe200078e0015 */ /*04b0*/ IADD3 R18, R6, -0x1, RZ ; /* 0xffffffff06127810 */ /* 0x000fe20007ffe0ff */ /*04c0*/ STG.E [R10.64], R7 ; /* 0x000000070a007986 */ /* 0x0041e8000c101904 */ /*04d0*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */ /* 0x000ea2000c1e1900 */ /*04e0*/ IMAD.WIDE.U32 R14, R14, R21, c[0x0][0x168] ; /* 0x00005a000e0e7625 */ /* 0x000fc800078e0015 */ /*04f0*/ IMAD.WIDE.U32 R16, R18.reuse, R21.reuse, c[0x0][0x160] ; /* 0x0000580012107625 */ /* 0x0c0fe200078e0015 */ /*0500*/ STG.E [R14.64], R13 ; /* 0x0000000d0e007986 */ /* 0x0043ea000c101904 */ /*0510*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */ /* 0x000ea2000c1e1900 */ /*0520*/ IMAD.WIDE.U32 R8, R18, R21, c[0x0][0x168] ; /* 0x00005a0012087625 */ /* 0x000fc800078e0015 */ /*0530*/ IMAD.WIDE.U32 R18, R6.reuse, R21.reuse, c[0x0][0x160] ; /* 0x0000580006127625 */ /* 0x0c0fe200078e0015 */ /*0540*/ STG.E [R8.64], R17 ; /* 0x0000001108007986 */ /* 0x0043ea000c101904 */ /*0550*/ LDG.E R19, [R18.64] ; /* 0x0000000412137981 */ /* 0x000ea2000c1e1900 */ /*0560*/ IMAD.WIDE.U32 R10, R6, R21, c[0x0][0x168] ; /* 0x00005a00060a7625 */ /* 0x001fe200078e0015 */ /*0570*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */ /* 0x000fe40007ffe0ff */ /*0580*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */ /* 0x000fc40007ffe0ff */ /*0590*/ IADD3 R7, R5, R4, RZ ; /* 0x0000000405077210 */ /* 0x000fc80007ffe0ff */ /*05a0*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */ /* 0x000fe20003f25270 */ /*05b0*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */ /* 0x0043d8000c101904 */ /*05c0*/ @P1 BRA 0x440 ; /* 0xfffffe7000001947 */ /* 0x000fea000383ffff */ /*05d0*/ @!P0 EXIT ; /* 0x000000000000894d */ /* 0x000fea0003800000 */ /*05e0*/ IMAD.IADD R3, R0, 0x1, R3 ; /* 0x0000000100037824 */ /* 0x002fc800078e0203 */ /*05f0*/ IMAD R0, R3, c[0x0][0x170], R4 ; /* 0x00005c0003007a24 */ /* 0x000fe400078e0204 */ /*0600*/ MOV R7, 0x4 ; /* 0x0000000400077802 */ /* 0x001fca0000000f00 */ /*0610*/ IMAD.WIDE.U32 R4, R0, R7, c[0x0][0x160] ; /* 0x0000580000047625 */ /* 0x000fcc00078e0007 */ /*0620*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */ /* 0x000ea2000c1e1900 */ /*0630*/ IMAD.WIDE.U32 R6, R0, R7, c[0x0][0x168] ; /* 0x00005a0000067625 */ /* 0x000fe200078e0007 */ /*0640*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */ /* 0x000fe40007ffe0ff */ /*0650*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */ /* 0x000fe40007ffe0ff */ /*0660*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */ /* 0x000fe20003f05270 */ /*0670*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */ /* 0x0041d8000c101904 */ /*0680*/ @P0 BRA 0x600 ; /* 0xffffff7000000947 */ /* 0x000fea000383ffff */ /*0690*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*06a0*/ BRA 0x6a0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*06b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*06c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*06d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*06e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*06f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0700*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0710*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0720*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0730*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0740*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0750*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0760*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0770*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include <stdio.h> #include <stdlib.h> #include <time.h> #include <assert.h> #include <sys/time.h> // __global__ void merge(float *data, float *work, int k) // { // int index = blockIdx.x * blockDim.x + threadIdx.x; // int l = index * k; // int m = l + k / 2; // int r = l + k; // int first = l; // int second = m; // for (int i = l; i < r; i++) // { // if (first < m && (second >= r || data[first] <= data[second])) // { // work[i] = data[first]; // first += 1; // } // else // { // work[i] = data[second]; // second += 1; // } // } // } // __global__ void parallel_merge(float *data, float *work) // { // uint half = blockDim.x >> 1; // uint pos = blockIdx.x * blockDim.x; // uint left_array = threadIdx.x < half ? 1 : 0; // float cur = data[pos + threadIdx.x]; // uint i = 0; // uint j = half; // if (left_array) // { // while (i < j) // { // uint mid = i + (j - i) / 2; // if (cur <= data[pos + half + mid]) // j = mid; // else // i = mid + 1; // } // work[pos + threadIdx.x + i] = cur; // } // else // { // while (i < j) // { // uint mid = i + (j - i) / 2; // if (cur < data[pos + mid]) // j = mid; // else // i = mid + 1; // } // work[pos + threadIdx.x - half + i] = cur; // } // } __global__ void parallel_merge(float *data, float *work, int stride) { uint index = threadIdx.x * stride; uint pos = blockIdx.x * blockDim.x * stride; uint half = blockDim.x * stride >> 1; uint left_array = index < half ? 1 : 0; for (uint s = 0; s < stride; s++) { float cur = data[pos + index + s]; uint i = 0; uint j = half; if (left_array) { while (i < j) { uint mid = i + (j - i) / 2; if (cur <= data[pos + half + mid]) j = mid; else i = mid + 1; } work[pos + index + s + i] = cur; } else { while (i < j) { uint mid = i + (j - i) / 2; if (cur < data[pos + mid]) j = mid; else i = mid + 1; } work[pos + index + s - half + i] = cur; } } } int cuda_sort(int number_of_elements, float *a) { cudaError_t cudaStatus; cudaStatus = cudaSetDevice(0); if (cudaStatus != cudaSuccess) { fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?"); return 1; } float *d_a, *d_b; cudaMalloc((void **)&d_a, number_of_elements * sizeof(float)); cudaMalloc((void **)&d_b, number_of_elements * sizeof(float)); cudaMemcpy(d_a, a, number_of_elements * sizeof(float), cudaMemcpyHostToDevice); int level = 0; for (int k = 2; k <= number_of_elements; k = 2 * k) { int num_merges = number_of_elements / k; if (k <= 1024) { if (level % 2 == 0) parallel_merge<<<num_merges, k>>>(d_a, d_b, 1); else parallel_merge<<<num_merges, k>>>(d_b, d_a, 1); } else { if (level % 2 == 0) parallel_merge<<<num_merges, 1024>>>(d_a, d_b, k / 1024); else parallel_merge<<<num_merges, 1024>>>(d_b, d_a, k / 1024); } cudaDeviceSynchronize(); level += 1; } if (level % 2 == 0) cudaMemcpy(a, d_a, number_of_elements * sizeof(float), cudaMemcpyDeviceToHost); else cudaMemcpy(a, d_b, number_of_elements * sizeof(float), cudaMemcpyDeviceToHost); cudaFree(d_a); cudaFree(d_b); return 0; }
.file "tmpxft_0002443b_00000000-6_cudasort.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z37__device_stub__Z14parallel_mergePfS_iPfS_i .type _Z37__device_stub__Z14parallel_mergePfS_iPfS_i, @function _Z37__device_stub__Z14parallel_mergePfS_iPfS_i: .LFB2082: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 120(%rsp), %rax subq %fs:40, %rax jne .L8 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z14parallel_mergePfS_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z37__device_stub__Z14parallel_mergePfS_iPfS_i, .-_Z37__device_stub__Z14parallel_mergePfS_iPfS_i .globl _Z14parallel_mergePfS_i .type _Z14parallel_mergePfS_i, @function _Z14parallel_mergePfS_i: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z37__device_stub__Z14parallel_mergePfS_iPfS_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z14parallel_mergePfS_i, .-_Z14parallel_mergePfS_i .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?" .text .globl _Z9cuda_sortiPf .type _Z9cuda_sortiPf, @function _Z9cuda_sortiPf: .LFB2057: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $48, %rsp .cfi_def_cfa_offset 96 movl %edi, %ebp movq %rsi, %r14 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax movl $0, %edi call cudaSetDevice@PLT testl %eax, %eax jne .L29 movslq %ebp, %r13 salq $2, %r13 movq %rsp, %rdi movq %r13, %rsi call cudaMalloc@PLT leaq 8(%rsp), %rdi movq %r13, %rsi call cudaMalloc@PLT movl $1, %ecx movq %r13, %rdx movq %r14, %rsi movq (%rsp), %rdi call cudaMemcpy@PLT cmpl $1, %ebp jle .L14 movl $2, %ebx movl $0, %r12d jmp .L23 .L29: leaq .LC0(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %eax jmp .L11 .L16: movl %ebx, 28(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl %eax, 16(%rsp) movl $1, 20(%rsp) movl $1, 24(%rsp) movl $0, %r9d movl $0, %r8d movq 28(%rsp), %rdx movl $1, %ecx movq 16(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L30 .L18: call cudaDeviceSynchronize@PLT addl $1, %r12d addl %ebx, %ebx cmpl %ebx, %ebp jl .L31 .L23: movl %ebp, %eax cltd idivl %ebx cmpl $1024, %ebx jg .L15 testb $1, %r12b jne .L16 movl %ebx, 28(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl %eax, 16(%rsp) movl $1, 20(%rsp) movl $1, 24(%rsp) movl $0, %r9d movl $0, %r8d movq 28(%rsp), %rdx movl $1, %ecx movq 16(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L18 movl $1, %edx movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z37__device_stub__Z14parallel_mergePfS_iPfS_i jmp .L18 .L30: movl $1, %edx movq (%rsp), %rsi movq 8(%rsp), %rdi call _Z37__device_stub__Z14parallel_mergePfS_iPfS_i jmp .L18 .L15: testb $1, %r12b jne .L20 movl $1024, 28(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl %eax, 16(%rsp) movl $1, 20(%rsp) movl $1, 24(%rsp) movl $0, %r9d movl $0, %r8d movq 28(%rsp), %rdx movl $1, %ecx movq 16(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L18 leal 1023(%rbx), %edx testl %ebx, %ebx cmovns %ebx, %edx sarl $10, %edx movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z37__device_stub__Z14parallel_mergePfS_iPfS_i jmp .L18 .L20: movl $1024, 28(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl %eax, 16(%rsp) movl $1, 20(%rsp) movl $1, 24(%rsp) movl $0, %r9d movl $0, %r8d movq 28(%rsp), %rdx movl $1, %ecx movq 16(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L18 leal 1023(%rbx), %edx testl %ebx, %ebx cmovns %ebx, %edx sarl $10, %edx movq (%rsp), %rsi movq 8(%rsp), %rdi call _Z37__device_stub__Z14parallel_mergePfS_iPfS_i jmp .L18 .L31: testb $1, %r12b je .L14 movl $2, %ecx movq %r13, %rdx movq 8(%rsp), %rsi movq %r14, %rdi call cudaMemcpy@PLT jmp .L25 .L14: movl $2, %ecx movq %r13, %rdx movq (%rsp), %rsi movq %r14, %rdi call cudaMemcpy@PLT .L25: movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movl $0, %eax .L11: movq 40(%rsp), %rdx subq %fs:40, %rdx jne .L32 addq $48, %rsp .cfi_remember_state .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L32: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size _Z9cuda_sortiPf, .-_Z9cuda_sortiPf .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "_Z14parallel_mergePfS_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _Z14parallel_mergePfS_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include <stdio.h> #include <stdlib.h> #include <time.h> #include <assert.h> #include <sys/time.h> // __global__ void merge(float *data, float *work, int k) // { // int index = blockIdx.x * blockDim.x + threadIdx.x; // int l = index * k; // int m = l + k / 2; // int r = l + k; // int first = l; // int second = m; // for (int i = l; i < r; i++) // { // if (first < m && (second >= r || data[first] <= data[second])) // { // work[i] = data[first]; // first += 1; // } // else // { // work[i] = data[second]; // second += 1; // } // } // } // __global__ void parallel_merge(float *data, float *work) // { // uint half = blockDim.x >> 1; // uint pos = blockIdx.x * blockDim.x; // uint left_array = threadIdx.x < half ? 1 : 0; // float cur = data[pos + threadIdx.x]; // uint i = 0; // uint j = half; // if (left_array) // { // while (i < j) // { // uint mid = i + (j - i) / 2; // if (cur <= data[pos + half + mid]) // j = mid; // else // i = mid + 1; // } // work[pos + threadIdx.x + i] = cur; // } // else // { // while (i < j) // { // uint mid = i + (j - i) / 2; // if (cur < data[pos + mid]) // j = mid; // else // i = mid + 1; // } // work[pos + threadIdx.x - half + i] = cur; // } // } __global__ void parallel_merge(float *data, float *work, int stride) { uint index = threadIdx.x * stride; uint pos = blockIdx.x * blockDim.x * stride; uint half = blockDim.x * stride >> 1; uint left_array = index < half ? 1 : 0; for (uint s = 0; s < stride; s++) { float cur = data[pos + index + s]; uint i = 0; uint j = half; if (left_array) { while (i < j) { uint mid = i + (j - i) / 2; if (cur <= data[pos + half + mid]) j = mid; else i = mid + 1; } work[pos + index + s + i] = cur; } else { while (i < j) { uint mid = i + (j - i) / 2; if (cur < data[pos + mid]) j = mid; else i = mid + 1; } work[pos + index + s - half + i] = cur; } } } int cuda_sort(int number_of_elements, float *a) { cudaError_t cudaStatus; cudaStatus = cudaSetDevice(0); if (cudaStatus != cudaSuccess) { fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?"); return 1; } float *d_a, *d_b; cudaMalloc((void **)&d_a, number_of_elements * sizeof(float)); cudaMalloc((void **)&d_b, number_of_elements * sizeof(float)); cudaMemcpy(d_a, a, number_of_elements * sizeof(float), cudaMemcpyHostToDevice); int level = 0; for (int k = 2; k <= number_of_elements; k = 2 * k) { int num_merges = number_of_elements / k; if (k <= 1024) { if (level % 2 == 0) parallel_merge<<<num_merges, k>>>(d_a, d_b, 1); else parallel_merge<<<num_merges, k>>>(d_b, d_a, 1); } else { if (level % 2 == 0) parallel_merge<<<num_merges, 1024>>>(d_a, d_b, k / 1024); else parallel_merge<<<num_merges, 1024>>>(d_b, d_a, k / 1024); } cudaDeviceSynchronize(); level += 1; } if (level % 2 == 0) cudaMemcpy(a, d_a, number_of_elements * sizeof(float), cudaMemcpyDeviceToHost); else cudaMemcpy(a, d_b, number_of_elements * sizeof(float), cudaMemcpyDeviceToHost); cudaFree(d_a); cudaFree(d_b); return 0; }
#include <hip/hip_runtime.h> #include <stdio.h> #include <stdlib.h> #include <time.h> #include <assert.h> #include <sys/time.h> // __global__ void merge(float *data, float *work, int k) // { // int index = blockIdx.x * blockDim.x + threadIdx.x; // int l = index * k; // int m = l + k / 2; // int r = l + k; // int first = l; // int second = m; // for (int i = l; i < r; i++) // { // if (first < m && (second >= r || data[first] <= data[second])) // { // work[i] = data[first]; // first += 1; // } // else // { // work[i] = data[second]; // second += 1; // } // } // } // __global__ void parallel_merge(float *data, float *work) // { // uint half = blockDim.x >> 1; // uint pos = blockIdx.x * blockDim.x; // uint left_array = threadIdx.x < half ? 1 : 0; // float cur = data[pos + threadIdx.x]; // uint i = 0; // uint j = half; // if (left_array) // { // while (i < j) // { // uint mid = i + (j - i) / 2; // if (cur <= data[pos + half + mid]) // j = mid; // else // i = mid + 1; // } // work[pos + threadIdx.x + i] = cur; // } // else // { // while (i < j) // { // uint mid = i + (j - i) / 2; // if (cur < data[pos + mid]) // j = mid; // else // i = mid + 1; // } // work[pos + threadIdx.x - half + i] = cur; // } // } __global__ void parallel_merge(float *data, float *work, int stride) { uint index = threadIdx.x * stride; uint pos = blockIdx.x * blockDim.x * stride; uint half = blockDim.x * stride >> 1; uint left_array = index < half ? 1 : 0; for (uint s = 0; s < stride; s++) { float cur = data[pos + index + s]; uint i = 0; uint j = half; if (left_array) { while (i < j) { uint mid = i + (j - i) / 2; if (cur <= data[pos + half + mid]) j = mid; else i = mid + 1; } work[pos + index + s + i] = cur; } else { while (i < j) { uint mid = i + (j - i) / 2; if (cur < data[pos + mid]) j = mid; else i = mid + 1; } work[pos + index + s - half + i] = cur; } } } int cuda_sort(int number_of_elements, float *a) { hipError_t cudaStatus; cudaStatus = hipSetDevice(0); if (cudaStatus != hipSuccess) { fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?"); return 1; } float *d_a, *d_b; hipMalloc((void **)&d_a, number_of_elements * sizeof(float)); hipMalloc((void **)&d_b, number_of_elements * sizeof(float)); hipMemcpy(d_a, a, number_of_elements * sizeof(float), hipMemcpyHostToDevice); int level = 0; for (int k = 2; k <= number_of_elements; k = 2 * k) { int num_merges = number_of_elements / k; if (k <= 1024) { if (level % 2 == 0) parallel_merge<<<num_merges, k>>>(d_a, d_b, 1); else parallel_merge<<<num_merges, k>>>(d_b, d_a, 1); } else { if (level % 2 == 0) parallel_merge<<<num_merges, 1024>>>(d_a, d_b, k / 1024); else parallel_merge<<<num_merges, 1024>>>(d_b, d_a, k / 1024); } hipDeviceSynchronize(); level += 1; } if (level % 2 == 0) hipMemcpy(a, d_a, number_of_elements * sizeof(float), hipMemcpyDeviceToHost); else hipMemcpy(a, d_b, number_of_elements * sizeof(float), hipMemcpyDeviceToHost); hipFree(d_a); hipFree(d_b); return 0; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include <stdio.h> #include <stdlib.h> #include <time.h> #include <assert.h> #include <sys/time.h> // __global__ void merge(float *data, float *work, int k) // { // int index = blockIdx.x * blockDim.x + threadIdx.x; // int l = index * k; // int m = l + k / 2; // int r = l + k; // int first = l; // int second = m; // for (int i = l; i < r; i++) // { // if (first < m && (second >= r || data[first] <= data[second])) // { // work[i] = data[first]; // first += 1; // } // else // { // work[i] = data[second]; // second += 1; // } // } // } // __global__ void parallel_merge(float *data, float *work) // { // uint half = blockDim.x >> 1; // uint pos = blockIdx.x * blockDim.x; // uint left_array = threadIdx.x < half ? 1 : 0; // float cur = data[pos + threadIdx.x]; // uint i = 0; // uint j = half; // if (left_array) // { // while (i < j) // { // uint mid = i + (j - i) / 2; // if (cur <= data[pos + half + mid]) // j = mid; // else // i = mid + 1; // } // work[pos + threadIdx.x + i] = cur; // } // else // { // while (i < j) // { // uint mid = i + (j - i) / 2; // if (cur < data[pos + mid]) // j = mid; // else // i = mid + 1; // } // work[pos + threadIdx.x - half + i] = cur; // } // } __global__ void parallel_merge(float *data, float *work, int stride) { uint index = threadIdx.x * stride; uint pos = blockIdx.x * blockDim.x * stride; uint half = blockDim.x * stride >> 1; uint left_array = index < half ? 1 : 0; for (uint s = 0; s < stride; s++) { float cur = data[pos + index + s]; uint i = 0; uint j = half; if (left_array) { while (i < j) { uint mid = i + (j - i) / 2; if (cur <= data[pos + half + mid]) j = mid; else i = mid + 1; } work[pos + index + s + i] = cur; } else { while (i < j) { uint mid = i + (j - i) / 2; if (cur < data[pos + mid]) j = mid; else i = mid + 1; } work[pos + index + s - half + i] = cur; } } } int cuda_sort(int number_of_elements, float *a) { hipError_t cudaStatus; cudaStatus = hipSetDevice(0); if (cudaStatus != hipSuccess) { fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?"); return 1; } float *d_a, *d_b; hipMalloc((void **)&d_a, number_of_elements * sizeof(float)); hipMalloc((void **)&d_b, number_of_elements * sizeof(float)); hipMemcpy(d_a, a, number_of_elements * sizeof(float), hipMemcpyHostToDevice); int level = 0; for (int k = 2; k <= number_of_elements; k = 2 * k) { int num_merges = number_of_elements / k; if (k <= 1024) { if (level % 2 == 0) parallel_merge<<<num_merges, k>>>(d_a, d_b, 1); else parallel_merge<<<num_merges, k>>>(d_b, d_a, 1); } else { if (level % 2 == 0) parallel_merge<<<num_merges, 1024>>>(d_a, d_b, k / 1024); else parallel_merge<<<num_merges, 1024>>>(d_b, d_a, k / 1024); } hipDeviceSynchronize(); level += 1; } if (level % 2 == 0) hipMemcpy(a, d_a, number_of_elements * sizeof(float), hipMemcpyDeviceToHost); else hipMemcpy(a, d_b, number_of_elements * sizeof(float), hipMemcpyDeviceToHost); hipFree(d_a); hipFree(d_b); return 0; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z14parallel_mergePfS_i .globl _Z14parallel_mergePfS_i .p2align 8 .type _Z14parallel_mergePfS_i,@function _Z14parallel_mergePfS_i: s_load_b32 s2, s[0:1], 0x10 s_mov_b32 s3, 0 s_waitcnt lgkmcnt(0) s_cmp_eq_u32 s2, 0 s_cbranch_scc1 .LBB0_13 s_clause 0x1 s_load_b32 s8, s[0:1], 0x24 s_load_b128 s[4:7], s[0:1], 0x0 v_mul_lo_u32 v0, v0, s2 s_waitcnt lgkmcnt(0) s_and_b32 s0, s8, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_mul_i32 s0, s0, s2 s_mul_i32 s1, s0, s15 s_lshr_b32 s8, s0, 1 s_delay_alu instid0(VALU_DEP_1) v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v4, s1, v0 s_cmp_gt_u32 s0, 1 v_cmp_le_u32_e64 s0, s8, v0 s_cselect_b32 s9, -1, 0 s_add_i32 s10, s1, s8 s_branch .LBB0_3 .LBB0_2: s_or_b32 exec_lo, exec_lo, s11 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_lshlrev_b64 v[5:6], 2, v[0:1] s_add_i32 s3, s3, 1 s_cmp_eq_u32 s3, s2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v5, vcc_lo, s6, v5 v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo s_waitcnt vmcnt(0) global_store_b32 v[5:6], v3, off s_cbranch_scc1 .LBB0_13 .LBB0_3: v_dual_mov_b32 v3, v1 :: v_dual_add_nc_u32 v2, s3, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[5:6], 2, v[2:3] v_add_co_u32 v5, vcc_lo, s4, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo global_load_b32 v3, v[5:6], off s_and_saveexec_b32 s11, s0 s_xor_b32 s11, exec_lo, s11 s_cbranch_execz .LBB0_9 v_mov_b32_e32 v5, 0 s_and_not1_b32 vcc_lo, exec_lo, s9 s_cbranch_vccnz .LBB0_8 v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, s8 s_mov_b32 s12, 0 .p2align 6 .LBB0_6: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v0, v6, v5 v_lshrrev_b32_e32 v0, 1, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v9, v0, v5 v_add_nc_u32_e32 v0, s1, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[7:8], 2, v[0:1] v_add_co_u32 v7, vcc_lo, s4, v7 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo global_load_b32 v0, v[7:8], off v_add_nc_u32_e32 v7, 1, v9 s_waitcnt vmcnt(0) v_cmp_lt_f32_e32 vcc_lo, v3, v0 v_cndmask_b32_e32 v6, v6, v9, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e32 v5, v7, v5, vcc_lo v_cmp_ge_u32_e32 vcc_lo, v5, v6 s_or_b32 s12, vcc_lo, s12 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s12 s_cbranch_execnz .LBB0_6 s_or_b32 exec_lo, exec_lo, s12 .LBB0_8: v_subrev_nc_u32_e32 v0, s8, v2 s_delay_alu instid0(VALU_DEP_1) v_add_nc_u32_e32 v0, v0, v5 .LBB0_9: s_and_not1_saveexec_b32 s11, s11 s_cbranch_execz .LBB0_2 v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, s8 s_mov_b32 s12, 0 .p2align 6 .LBB0_11: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v0, v6, v5 v_lshrrev_b32_e32 v0, 1, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v9, v0, v5 v_add_nc_u32_e32 v0, s10, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[7:8], 2, v[0:1] v_add_co_u32 v7, vcc_lo, s4, v7 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1) v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo global_load_b32 v0, v[7:8], off s_waitcnt vmcnt(0) v_cmp_nle_f32_e32 vcc_lo, v3, v0 v_dual_cndmask_b32 v6, v9, v6 :: v_dual_add_nc_u32 v7, 1, v9 v_cndmask_b32_e32 v5, v5, v7, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_cmp_ge_u32_e32 vcc_lo, v5, v6 s_or_b32 s12, vcc_lo, s12 s_and_not1_b32 exec_lo, exec_lo, s12 s_cbranch_execnz .LBB0_11 s_or_b32 exec_lo, exec_lo, s12 v_add_nc_u32_e32 v0, v5, v2 s_branch .LBB0_2 .LBB0_13: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z14parallel_mergePfS_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 10 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z14parallel_mergePfS_i, .Lfunc_end0-_Z14parallel_mergePfS_i .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z14parallel_mergePfS_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z14parallel_mergePfS_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 10 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include <stdio.h> #include <stdlib.h> #include <time.h> #include <assert.h> #include <sys/time.h> // __global__ void merge(float *data, float *work, int k) // { // int index = blockIdx.x * blockDim.x + threadIdx.x; // int l = index * k; // int m = l + k / 2; // int r = l + k; // int first = l; // int second = m; // for (int i = l; i < r; i++) // { // if (first < m && (second >= r || data[first] <= data[second])) // { // work[i] = data[first]; // first += 1; // } // else // { // work[i] = data[second]; // second += 1; // } // } // } // __global__ void parallel_merge(float *data, float *work) // { // uint half = blockDim.x >> 1; // uint pos = blockIdx.x * blockDim.x; // uint left_array = threadIdx.x < half ? 1 : 0; // float cur = data[pos + threadIdx.x]; // uint i = 0; // uint j = half; // if (left_array) // { // while (i < j) // { // uint mid = i + (j - i) / 2; // if (cur <= data[pos + half + mid]) // j = mid; // else // i = mid + 1; // } // work[pos + threadIdx.x + i] = cur; // } // else // { // while (i < j) // { // uint mid = i + (j - i) / 2; // if (cur < data[pos + mid]) // j = mid; // else // i = mid + 1; // } // work[pos + threadIdx.x - half + i] = cur; // } // } __global__ void parallel_merge(float *data, float *work, int stride) { uint index = threadIdx.x * stride; uint pos = blockIdx.x * blockDim.x * stride; uint half = blockDim.x * stride >> 1; uint left_array = index < half ? 1 : 0; for (uint s = 0; s < stride; s++) { float cur = data[pos + index + s]; uint i = 0; uint j = half; if (left_array) { while (i < j) { uint mid = i + (j - i) / 2; if (cur <= data[pos + half + mid]) j = mid; else i = mid + 1; } work[pos + index + s + i] = cur; } else { while (i < j) { uint mid = i + (j - i) / 2; if (cur < data[pos + mid]) j = mid; else i = mid + 1; } work[pos + index + s - half + i] = cur; } } } int cuda_sort(int number_of_elements, float *a) { hipError_t cudaStatus; cudaStatus = hipSetDevice(0); if (cudaStatus != hipSuccess) { fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?"); return 1; } float *d_a, *d_b; hipMalloc((void **)&d_a, number_of_elements * sizeof(float)); hipMalloc((void **)&d_b, number_of_elements * sizeof(float)); hipMemcpy(d_a, a, number_of_elements * sizeof(float), hipMemcpyHostToDevice); int level = 0; for (int k = 2; k <= number_of_elements; k = 2 * k) { int num_merges = number_of_elements / k; if (k <= 1024) { if (level % 2 == 0) parallel_merge<<<num_merges, k>>>(d_a, d_b, 1); else parallel_merge<<<num_merges, k>>>(d_b, d_a, 1); } else { if (level % 2 == 0) parallel_merge<<<num_merges, 1024>>>(d_a, d_b, k / 1024); else parallel_merge<<<num_merges, 1024>>>(d_b, d_a, k / 1024); } hipDeviceSynchronize(); level += 1; } if (level % 2 == 0) hipMemcpy(a, d_a, number_of_elements * sizeof(float), hipMemcpyDeviceToHost); else hipMemcpy(a, d_b, number_of_elements * sizeof(float), hipMemcpyDeviceToHost); hipFree(d_a); hipFree(d_b); return 0; }
.text .file "cudasort.hip" .globl _Z29__device_stub__parallel_mergePfS_i # -- Begin function _Z29__device_stub__parallel_mergePfS_i .p2align 4, 0x90 .type _Z29__device_stub__parallel_mergePfS_i,@function _Z29__device_stub__parallel_mergePfS_i: # @_Z29__device_stub__parallel_mergePfS_i .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z14parallel_mergePfS_i, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z29__device_stub__parallel_mergePfS_i, .Lfunc_end0-_Z29__device_stub__parallel_mergePfS_i .cfi_endproc # -- End function .globl _Z9cuda_sortiPf # -- Begin function _Z9cuda_sortiPf .p2align 4, 0x90 .type _Z9cuda_sortiPf,@function _Z9cuda_sortiPf: # @_Z9cuda_sortiPf .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $136, %rsp .cfi_def_cfa_offset 192 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rsi, %r12 movl %edi, %ebp xorl %edi, %edi callq hipSetDevice testl %eax, %eax jne .LBB1_1 # %bb.2: movslq %ebp, %r15 leaq (,%r15,4), %r14 leaq 16(%rsp), %rbx movq %rbx, %rdi movq %r14, %rsi callq hipMalloc leaq 88(%rsp), %rdi movq %r14, %rsi callq hipMalloc movq 16(%rsp), %rdi movq %r12, %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy cmpl $2, %r15d jl .LBB1_20 # %bb.3: # %.lr.ph movq %r12, 128(%rsp) # 8-byte Spill movl $2, %ebx movl $-1, %r15d movabsq $4294967296, %r12 # imm = 0x100000000 leaq 1024(%r12), %r13 jmp .LBB1_4 .LBB1_16: # in Loop: Header=BB1_4 Depth=1 movl %ebx, %edx shrl $10, %edx movq %rax, 80(%rsp) movq %rcx, 72(%rsp) movl %edx, 12(%rsp) .LBB1_17: # in Loop: Header=BB1_4 Depth=1 leaq 80(%rsp), %rax movq %rax, 96(%rsp) leaq 72(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d movl $_Z14parallel_mergePfS_i, %edi leaq 96(%rsp), %r9 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_18: # in Loop: Header=BB1_4 Depth=1 callq hipDeviceSynchronize addl %ebx, %ebx cmpl %ebp, %ebx jg .LBB1_19 .LBB1_4: # =>This Inner Loop Header: Depth=1 incl %r15d movl %ebp, %eax xorl %edx, %edx divl %ebx # kill: def $eax killed $eax def $rax orq %r12, %rax cmpl $1024, %ebx # imm = 0x400 ja .LBB1_11 # %bb.5: # in Loop: Header=BB1_4 Depth=1 movl %ebx, %edx orq %r12, %rdx movq %rax, %rdi movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testb $1, %r15b jne .LBB1_9 # %bb.6: # in Loop: Header=BB1_4 Depth=1 testl %eax, %eax jne .LBB1_18 # %bb.7: # in Loop: Header=BB1_4 Depth=1 movq 16(%rsp), %rax movq 88(%rsp), %rcx jmp .LBB1_8 .p2align 4, 0x90 .LBB1_11: # in Loop: Header=BB1_4 Depth=1 movq %rax, %rdi movl $1, %esi movq %r13, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testb $1, %r15b jne .LBB1_14 # %bb.12: # in Loop: Header=BB1_4 Depth=1 testl %eax, %eax jne .LBB1_18 # %bb.13: # in Loop: Header=BB1_4 Depth=1 movq 16(%rsp), %rax movq 88(%rsp), %rcx jmp .LBB1_16 .p2align 4, 0x90 .LBB1_9: # in Loop: Header=BB1_4 Depth=1 testl %eax, %eax jne .LBB1_18 # %bb.10: # in Loop: Header=BB1_4 Depth=1 movq 88(%rsp), %rax movq 16(%rsp), %rcx .LBB1_8: # in Loop: Header=BB1_4 Depth=1 movq %rax, 80(%rsp) movq %rcx, 72(%rsp) movl $1, 12(%rsp) jmp .LBB1_17 .p2align 4, 0x90 .LBB1_14: # in Loop: Header=BB1_4 Depth=1 testl %eax, %eax jne .LBB1_18 # %bb.15: # in Loop: Header=BB1_4 Depth=1 movq 88(%rsp), %rax movq 16(%rsp), %rcx jmp .LBB1_16 .LBB1_19: # %._crit_edge.loopexit testb $1, %r15b leaq 16(%rsp), %rbx leaq 88(%rsp), %rax cmoveq %rax, %rbx movq 128(%rsp), %r12 # 8-byte Reload .LBB1_20: # %.critedge movq (%rbx), %rsi movq %r12, %rdi movq %r14, %rdx movl $2, %ecx callq hipMemcpy movq 16(%rsp), %rdi callq hipFree movq 88(%rsp), %rdi callq hipFree xorl %eax, %eax .LBB1_21: addq $136, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB1_1: .cfi_def_cfa_offset 192 movq stderr(%rip), %rcx movl $.L.str, %edi movl $63, %esi movl $1, %edx callq fwrite@PLT movl $1, %eax jmp .LBB1_21 .Lfunc_end1: .size _Z9cuda_sortiPf, .Lfunc_end1-_Z9cuda_sortiPf .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z14parallel_mergePfS_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z14parallel_mergePfS_i,@object # @_Z14parallel_mergePfS_i .section .rodata,"a",@progbits .globl _Z14parallel_mergePfS_i .p2align 3, 0x0 _Z14parallel_mergePfS_i: .quad _Z29__device_stub__parallel_mergePfS_i .size _Z14parallel_mergePfS_i, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "hipSetDevice failed! Do you have a CUDA-capable GPU installed?" .size .L.str, 64 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z14parallel_mergePfS_i" .size .L__unnamed_1, 24 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z29__device_stub__parallel_mergePfS_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z14parallel_mergePfS_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z14parallel_mergePfS_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */ /* 0x000fda0003f05270 */ /*0020*/ @!P0 EXIT ; /* 0x000000000000894d */ /* 0x000fea0003800000 */ /*0030*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */ /* 0x000fe200078e00ff */ /*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */ /* 0x000e220000002500 */ /*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe40000000a00 */ /*0060*/ IMAD R5, R6, c[0x0][0x0], RZ ; /* 0x0000000006057a24 */ /* 0x000fe200078e02ff */ /*0070*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e680000002100 */ /*0080*/ SHF.R.U32.HI R5, RZ, 0x1, R5 ; /* 0x00000001ff057819 */ /* 0x000fc80000011605 */ /*0090*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */ /* 0x000fe20003f05270 */ /*00a0*/ IMAD R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a24 */ /* 0x001fd800078e02ff */ /*00b0*/ @!P0 BRA 0x3a0 ; /* 0x000002e000008947 */ /* 0x000fea0003800000 */ /*00c0*/ IMAD R2, R3, c[0x0][0x170], RZ ; /* 0x00005c0003027a24 */ /* 0x002fe200078e02ff */ /*00d0*/ IADD3 R13, R0.reuse, R3, RZ ; /* 0x00000003000d7210 */ /* 0x040fe20007ffe0ff */ /*00e0*/ IMAD R3, R0, c[0x0][0x170], R5 ; /* 0x00005c0000037a24 */ /* 0x000fe400078e0205 */ /*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */ /* 0x000fe400078e00ff */ /*0100*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */ /* 0x000fe400078e00ff */ /*0110*/ IMAD R8, R13, c[0x0][0x170], R4 ; /* 0x00005c000d087a24 */ /* 0x000fc800078e0204 */ /*0120*/ IMAD.WIDE.U32 R6, R8, R15, c[0x0][0x160] ; /* 0x0000580008067625 */ /* 0x001fca00078e000f */ /*0130*/ LDG.E R17, [R6.64] ; /* 0x0000000406117981 */ /* 0x000162000c1e1900 */ /*0140*/ ISETP.GE.U32.AND P1, PT, R2, R5, PT ; /* 0x000000050200720c */ /* 0x000fe20003f26070 */ /*0150*/ BSSY B0, 0x350 ; /* 0x000001f000007945 */ /* 0x000fe20003800000 */ /*0160*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */ /* 0x000fe20007ffe0ff */ /*0170*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */ /* 0x000fc600000001ff */ /*0180*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */ /* 0x000fce0003f06070 */ /*0190*/ @!P1 BRA 0x290 ; /* 0x000000f000009947 */ /* 0x000fea0003800000 */ /*01a0*/ BSSY B1, 0x270 ; /* 0x000000c000017945 */ /* 0x001fe20003800000 */ /*01b0*/ IMAD.MOV.U32 R10, RZ, RZ, R5 ; /* 0x000000ffff0a7224 */ /* 0x000fc800078e0005 */ /*01c0*/ IMAD.IADD R6, R10, 0x1, -R9 ; /* 0x000000010a067824 */ /* 0x000fca00078e0a09 */ /*01d0*/ LEA.HI R11, R6, R9, RZ, 0x1f ; /* 0x00000009060b7211 */ /* 0x000fca00078ff8ff */ /*01e0*/ IMAD R6, R0, c[0x0][0x170], R11 ; /* 0x00005c0000067a24 */ /* 0x000fc800078e020b */ /*01f0*/ IMAD.WIDE.U32 R6, R6, R15, c[0x0][0x160] ; /* 0x0000580006067625 */ /* 0x000fcc00078e000f */ /*0200*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */ /* 0x000ea4000c1e1900 */ /*0210*/ FSETP.GEU.AND P1, PT, R17, R6, PT ; /* 0x000000061100720b */ /* 0x024fc80003f2e000 */ /*0220*/ SEL R10, R11, R10, !P1 ; /* 0x0000000a0b0a7207 */ /* 0x000fd20004800000 */ /*0230*/ @P1 IADD3 R9, R11, 0x1, RZ ; /* 0x000000010b091810 */ /* 0x000fc80007ffe0ff */ /*0240*/ ISETP.GT.U32.AND P1, PT, R10, R9, PT ; /* 0x000000090a00720c */ /* 0x000fda0003f24070 */ /*0250*/ @P1 BRA 0x1c0 ; /* 0xffffff6000001947 */ /* 0x000fea000383ffff */ /*0260*/ BSYNC B1 ; /* 0x0000000000017941 */ /* 0x000fea0003800000 */ /*0270*/ IADD3 R8, -R5, R8, RZ ; /* 0x0000000805087210 */ /* 0x000fe20007ffe1ff */ /*0280*/ BRA 0x340 ; /* 0x000000b000007947 */ /* 0x000fea0003800000 */ /*0290*/ IMAD.MOV.U32 R10, RZ, RZ, R5 ; /* 0x000000ffff0a7224 */ /* 0x001fc800078e0005 */ /*02a0*/ IMAD.IADD R6, R10, 0x1, -R9 ; /* 0x000000010a067824 */ /* 0x000fca00078e0a09 */ /*02b0*/ LEA.HI R11, R6, R9, RZ, 0x1f ; /* 0x00000009060b7211 */ /* 0x000fc800078ff8ff */ /*02c0*/ IADD3 R6, R3, R11, RZ ; /* 0x0000000b03067210 */ /* 0x000fca0007ffe0ff */ /*02d0*/ IMAD.WIDE.U32 R6, R6, R15, c[0x0][0x160] ; /* 0x0000580006067625 */ /* 0x000fcc00078e000f */ /*02e0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */ /* 0x000ea4000c1e1900 */ /*02f0*/ FSETP.GTU.AND P1, PT, R17, R6, PT ; /* 0x000000061100720b */ /* 0x024fc80003f2c000 */ /*0300*/ SEL R10, R11, R10, !P1 ; /* 0x0000000a0b0a7207 */ /* 0x000fd20004800000 */ /*0310*/ @P1 IADD3 R9, R11, 0x1, RZ ; /* 0x000000010b091810 */ /* 0x000fc80007ffe0ff */ /*0320*/ ISETP.GT.U32.AND P1, PT, R10, R9, PT ; /* 0x000000090a00720c */ /* 0x000fda0003f24070 */ /*0330*/ @P1 BRA 0x2a0 ; /* 0xffffff6000001947 */ /* 0x000fea000383ffff */ /*0340*/ BSYNC B0 ; /* 0x0000000000007941 */ /* 0x000fea0003800000 */ /*0350*/ IMAD.IADD R6, R9, 0x1, R8 ; /* 0x0000000109067824 */ /* 0x000fc800078e0208 */ /*0360*/ IMAD.WIDE.U32 R6, R6, R15, c[0x0][0x168] ; /* 0x00005a0006067625 */ /* 0x000fca00078e000f */ /*0370*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */ /* 0x0001e2000c101904 */ /*0380*/ @!P0 BRA 0x100 ; /* 0xfffffd7000008947 */ /* 0x000fea000383ffff */ /*0390*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*03a0*/ IADD3 R4, R6.reuse, -0x1, RZ ; /* 0xffffffff06047810 */ /* 0x040fe40007ffe0ff */ /*03b0*/ LOP3.LUT R2, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306027812 */ /* 0x000fe400078ec0ff */ /*03c0*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */ /* 0x000fe20003f26070 */ /*03d0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */ /* 0x000fe200078e00ff */ /*03e0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */ /* 0x000fd60003f05270 */ /*03f0*/ @!P1 BRA 0x5d0 ; /* 0x000001d000009947 */ /* 0x000fea0003800000 */ /*0400*/ IADD3 R7, R0, R3, RZ ; /* 0x0000000300077210 */ /* 0x002fe20007ffe0ff */ /*0410*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */ /* 0x000fe200078e00ff */ /*0420*/ IADD3 R5, R2, -c[0x0][0x170], RZ ; /* 0x80005c0002057a10 */ /* 0x000fc60007ffe0ff */ /*0430*/ IMAD R6, R7, R6, 0x3 ; /* 0x0000000307067424 */ /* 0x000fca00078e0206 */ /*0440*/ IADD3 R10, R6, -0x3, RZ ; /* 0xfffffffd060a7810 */ /* 0x002fe20007ffe0ff */ /*0450*/ IMAD.MOV.U32 R21, RZ, RZ, 0x4 ; /* 0x00000004ff157424 */ /* 0x000fc800078e00ff */ /*0460*/ IMAD.WIDE.U32 R8, R10, R21, c[0x0][0x160] ; /* 0x000058000a087625 */ /* 0x000fca00078e0015 */ /*0470*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */ /* 0x000ea2000c1e1900 */ /*0480*/ IADD3 R14, R6, -0x2, RZ ; /* 0xfffffffe060e7810 */ /* 0x000fe20007ffe0ff */ /*0490*/ IMAD.WIDE.U32 R10, R10, R21, c[0x0][0x168] ; /* 0x00005a000a0a7625 */ /* 0x000fc800078e0015 */ /*04a0*/ IMAD.WIDE.U32 R12, R14, R21.reuse, c[0x0][0x160] ; /* 0x000058000e0c7625 */ /* 0x080fe200078e0015 */ /*04b0*/ IADD3 R18, R6, -0x1, RZ ; /* 0xffffffff06127810 */ /* 0x000fe20007ffe0ff */ /*04c0*/ STG.E [R10.64], R7 ; /* 0x000000070a007986 */ /* 0x0041e8000c101904 */ /*04d0*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */ /* 0x000ea2000c1e1900 */ /*04e0*/ IMAD.WIDE.U32 R14, R14, R21, c[0x0][0x168] ; /* 0x00005a000e0e7625 */ /* 0x000fc800078e0015 */ /*04f0*/ IMAD.WIDE.U32 R16, R18.reuse, R21.reuse, c[0x0][0x160] ; /* 0x0000580012107625 */ /* 0x0c0fe200078e0015 */ /*0500*/ STG.E [R14.64], R13 ; /* 0x0000000d0e007986 */ /* 0x0043ea000c101904 */ /*0510*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */ /* 0x000ea2000c1e1900 */ /*0520*/ IMAD.WIDE.U32 R8, R18, R21, c[0x0][0x168] ; /* 0x00005a0012087625 */ /* 0x000fc800078e0015 */ /*0530*/ IMAD.WIDE.U32 R18, R6.reuse, R21.reuse, c[0x0][0x160] ; /* 0x0000580006127625 */ /* 0x0c0fe200078e0015 */ /*0540*/ STG.E [R8.64], R17 ; /* 0x0000001108007986 */ /* 0x0043ea000c101904 */ /*0550*/ LDG.E R19, [R18.64] ; /* 0x0000000412137981 */ /* 0x000ea2000c1e1900 */ /*0560*/ IMAD.WIDE.U32 R10, R6, R21, c[0x0][0x168] ; /* 0x00005a00060a7625 */ /* 0x001fe200078e0015 */ /*0570*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */ /* 0x000fe40007ffe0ff */ /*0580*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */ /* 0x000fc40007ffe0ff */ /*0590*/ IADD3 R7, R5, R4, RZ ; /* 0x0000000405077210 */ /* 0x000fc80007ffe0ff */ /*05a0*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */ /* 0x000fe20003f25270 */ /*05b0*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */ /* 0x0043d8000c101904 */ /*05c0*/ @P1 BRA 0x440 ; /* 0xfffffe7000001947 */ /* 0x000fea000383ffff */ /*05d0*/ @!P0 EXIT ; /* 0x000000000000894d */ /* 0x000fea0003800000 */ /*05e0*/ IMAD.IADD R3, R0, 0x1, R3 ; /* 0x0000000100037824 */ /* 0x002fc800078e0203 */ /*05f0*/ IMAD R0, R3, c[0x0][0x170], R4 ; /* 0x00005c0003007a24 */ /* 0x000fe400078e0204 */ /*0600*/ MOV R7, 0x4 ; /* 0x0000000400077802 */ /* 0x001fca0000000f00 */ /*0610*/ IMAD.WIDE.U32 R4, R0, R7, c[0x0][0x160] ; /* 0x0000580000047625 */ /* 0x000fcc00078e0007 */ /*0620*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */ /* 0x000ea2000c1e1900 */ /*0630*/ IMAD.WIDE.U32 R6, R0, R7, c[0x0][0x168] ; /* 0x00005a0000067625 */ /* 0x000fe200078e0007 */ /*0640*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */ /* 0x000fe40007ffe0ff */ /*0650*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */ /* 0x000fe40007ffe0ff */ /*0660*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */ /* 0x000fe20003f05270 */ /*0670*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */ /* 0x0041d8000c101904 */ /*0680*/ @P0 BRA 0x600 ; /* 0xffffff7000000947 */ /* 0x000fea000383ffff */ /*0690*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*06a0*/ BRA 0x6a0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*06b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*06c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*06d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*06e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*06f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0700*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0710*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0720*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0730*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0740*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0750*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0760*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0770*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z14parallel_mergePfS_i .globl _Z14parallel_mergePfS_i .p2align 8 .type _Z14parallel_mergePfS_i,@function _Z14parallel_mergePfS_i: s_load_b32 s2, s[0:1], 0x10 s_mov_b32 s3, 0 s_waitcnt lgkmcnt(0) s_cmp_eq_u32 s2, 0 s_cbranch_scc1 .LBB0_13 s_clause 0x1 s_load_b32 s8, s[0:1], 0x24 s_load_b128 s[4:7], s[0:1], 0x0 v_mul_lo_u32 v0, v0, s2 s_waitcnt lgkmcnt(0) s_and_b32 s0, s8, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_mul_i32 s0, s0, s2 s_mul_i32 s1, s0, s15 s_lshr_b32 s8, s0, 1 s_delay_alu instid0(VALU_DEP_1) v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v4, s1, v0 s_cmp_gt_u32 s0, 1 v_cmp_le_u32_e64 s0, s8, v0 s_cselect_b32 s9, -1, 0 s_add_i32 s10, s1, s8 s_branch .LBB0_3 .LBB0_2: s_or_b32 exec_lo, exec_lo, s11 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_lshlrev_b64 v[5:6], 2, v[0:1] s_add_i32 s3, s3, 1 s_cmp_eq_u32 s3, s2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v5, vcc_lo, s6, v5 v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo s_waitcnt vmcnt(0) global_store_b32 v[5:6], v3, off s_cbranch_scc1 .LBB0_13 .LBB0_3: v_dual_mov_b32 v3, v1 :: v_dual_add_nc_u32 v2, s3, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[5:6], 2, v[2:3] v_add_co_u32 v5, vcc_lo, s4, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo global_load_b32 v3, v[5:6], off s_and_saveexec_b32 s11, s0 s_xor_b32 s11, exec_lo, s11 s_cbranch_execz .LBB0_9 v_mov_b32_e32 v5, 0 s_and_not1_b32 vcc_lo, exec_lo, s9 s_cbranch_vccnz .LBB0_8 v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, s8 s_mov_b32 s12, 0 .p2align 6 .LBB0_6: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v0, v6, v5 v_lshrrev_b32_e32 v0, 1, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v9, v0, v5 v_add_nc_u32_e32 v0, s1, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[7:8], 2, v[0:1] v_add_co_u32 v7, vcc_lo, s4, v7 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo global_load_b32 v0, v[7:8], off v_add_nc_u32_e32 v7, 1, v9 s_waitcnt vmcnt(0) v_cmp_lt_f32_e32 vcc_lo, v3, v0 v_cndmask_b32_e32 v6, v6, v9, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e32 v5, v7, v5, vcc_lo v_cmp_ge_u32_e32 vcc_lo, v5, v6 s_or_b32 s12, vcc_lo, s12 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s12 s_cbranch_execnz .LBB0_6 s_or_b32 exec_lo, exec_lo, s12 .LBB0_8: v_subrev_nc_u32_e32 v0, s8, v2 s_delay_alu instid0(VALU_DEP_1) v_add_nc_u32_e32 v0, v0, v5 .LBB0_9: s_and_not1_saveexec_b32 s11, s11 s_cbranch_execz .LBB0_2 v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, s8 s_mov_b32 s12, 0 .p2align 6 .LBB0_11: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v0, v6, v5 v_lshrrev_b32_e32 v0, 1, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v9, v0, v5 v_add_nc_u32_e32 v0, s10, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[7:8], 2, v[0:1] v_add_co_u32 v7, vcc_lo, s4, v7 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1) v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo global_load_b32 v0, v[7:8], off s_waitcnt vmcnt(0) v_cmp_nle_f32_e32 vcc_lo, v3, v0 v_dual_cndmask_b32 v6, v9, v6 :: v_dual_add_nc_u32 v7, 1, v9 v_cndmask_b32_e32 v5, v5, v7, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_cmp_ge_u32_e32 vcc_lo, v5, v6 s_or_b32 s12, vcc_lo, s12 s_and_not1_b32 exec_lo, exec_lo, s12 s_cbranch_execnz .LBB0_11 s_or_b32 exec_lo, exec_lo, s12 v_add_nc_u32_e32 v0, v5, v2 s_branch .LBB0_2 .LBB0_13: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z14parallel_mergePfS_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 10 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z14parallel_mergePfS_i, .Lfunc_end0-_Z14parallel_mergePfS_i .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z14parallel_mergePfS_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z14parallel_mergePfS_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 10 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_0002443b_00000000-6_cudasort.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z37__device_stub__Z14parallel_mergePfS_iPfS_i .type _Z37__device_stub__Z14parallel_mergePfS_iPfS_i, @function _Z37__device_stub__Z14parallel_mergePfS_iPfS_i: .LFB2082: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 120(%rsp), %rax subq %fs:40, %rax jne .L8 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z14parallel_mergePfS_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z37__device_stub__Z14parallel_mergePfS_iPfS_i, .-_Z37__device_stub__Z14parallel_mergePfS_iPfS_i .globl _Z14parallel_mergePfS_i .type _Z14parallel_mergePfS_i, @function _Z14parallel_mergePfS_i: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z37__device_stub__Z14parallel_mergePfS_iPfS_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z14parallel_mergePfS_i, .-_Z14parallel_mergePfS_i .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?" .text .globl _Z9cuda_sortiPf .type _Z9cuda_sortiPf, @function _Z9cuda_sortiPf: .LFB2057: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $48, %rsp .cfi_def_cfa_offset 96 movl %edi, %ebp movq %rsi, %r14 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax movl $0, %edi call cudaSetDevice@PLT testl %eax, %eax jne .L29 movslq %ebp, %r13 salq $2, %r13 movq %rsp, %rdi movq %r13, %rsi call cudaMalloc@PLT leaq 8(%rsp), %rdi movq %r13, %rsi call cudaMalloc@PLT movl $1, %ecx movq %r13, %rdx movq %r14, %rsi movq (%rsp), %rdi call cudaMemcpy@PLT cmpl $1, %ebp jle .L14 movl $2, %ebx movl $0, %r12d jmp .L23 .L29: leaq .LC0(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %eax jmp .L11 .L16: movl %ebx, 28(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl %eax, 16(%rsp) movl $1, 20(%rsp) movl $1, 24(%rsp) movl $0, %r9d movl $0, %r8d movq 28(%rsp), %rdx movl $1, %ecx movq 16(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L30 .L18: call cudaDeviceSynchronize@PLT addl $1, %r12d addl %ebx, %ebx cmpl %ebx, %ebp jl .L31 .L23: movl %ebp, %eax cltd idivl %ebx cmpl $1024, %ebx jg .L15 testb $1, %r12b jne .L16 movl %ebx, 28(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl %eax, 16(%rsp) movl $1, 20(%rsp) movl $1, 24(%rsp) movl $0, %r9d movl $0, %r8d movq 28(%rsp), %rdx movl $1, %ecx movq 16(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L18 movl $1, %edx movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z37__device_stub__Z14parallel_mergePfS_iPfS_i jmp .L18 .L30: movl $1, %edx movq (%rsp), %rsi movq 8(%rsp), %rdi call _Z37__device_stub__Z14parallel_mergePfS_iPfS_i jmp .L18 .L15: testb $1, %r12b jne .L20 movl $1024, 28(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl %eax, 16(%rsp) movl $1, 20(%rsp) movl $1, 24(%rsp) movl $0, %r9d movl $0, %r8d movq 28(%rsp), %rdx movl $1, %ecx movq 16(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L18 leal 1023(%rbx), %edx testl %ebx, %ebx cmovns %ebx, %edx sarl $10, %edx movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z37__device_stub__Z14parallel_mergePfS_iPfS_i jmp .L18 .L20: movl $1024, 28(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl %eax, 16(%rsp) movl $1, 20(%rsp) movl $1, 24(%rsp) movl $0, %r9d movl $0, %r8d movq 28(%rsp), %rdx movl $1, %ecx movq 16(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax jne .L18 leal 1023(%rbx), %edx testl %ebx, %ebx cmovns %ebx, %edx sarl $10, %edx movq (%rsp), %rsi movq 8(%rsp), %rdi call _Z37__device_stub__Z14parallel_mergePfS_iPfS_i jmp .L18 .L31: testb $1, %r12b je .L14 movl $2, %ecx movq %r13, %rdx movq 8(%rsp), %rsi movq %r14, %rdi call cudaMemcpy@PLT jmp .L25 .L14: movl $2, %ecx movq %r13, %rdx movq (%rsp), %rsi movq %r14, %rdi call cudaMemcpy@PLT .L25: movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movl $0, %eax .L11: movq 40(%rsp), %rdx subq %fs:40, %rdx jne .L32 addq $48, %rsp .cfi_remember_state .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L32: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size _Z9cuda_sortiPf, .-_Z9cuda_sortiPf .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "_Z14parallel_mergePfS_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _Z14parallel_mergePfS_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "cudasort.hip" .globl _Z29__device_stub__parallel_mergePfS_i # -- Begin function _Z29__device_stub__parallel_mergePfS_i .p2align 4, 0x90 .type _Z29__device_stub__parallel_mergePfS_i,@function _Z29__device_stub__parallel_mergePfS_i: # @_Z29__device_stub__parallel_mergePfS_i .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z14parallel_mergePfS_i, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z29__device_stub__parallel_mergePfS_i, .Lfunc_end0-_Z29__device_stub__parallel_mergePfS_i .cfi_endproc # -- End function .globl _Z9cuda_sortiPf # -- Begin function _Z9cuda_sortiPf .p2align 4, 0x90 .type _Z9cuda_sortiPf,@function _Z9cuda_sortiPf: # @_Z9cuda_sortiPf .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $136, %rsp .cfi_def_cfa_offset 192 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rsi, %r12 movl %edi, %ebp xorl %edi, %edi callq hipSetDevice testl %eax, %eax jne .LBB1_1 # %bb.2: movslq %ebp, %r15 leaq (,%r15,4), %r14 leaq 16(%rsp), %rbx movq %rbx, %rdi movq %r14, %rsi callq hipMalloc leaq 88(%rsp), %rdi movq %r14, %rsi callq hipMalloc movq 16(%rsp), %rdi movq %r12, %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy cmpl $2, %r15d jl .LBB1_20 # %bb.3: # %.lr.ph movq %r12, 128(%rsp) # 8-byte Spill movl $2, %ebx movl $-1, %r15d movabsq $4294967296, %r12 # imm = 0x100000000 leaq 1024(%r12), %r13 jmp .LBB1_4 .LBB1_16: # in Loop: Header=BB1_4 Depth=1 movl %ebx, %edx shrl $10, %edx movq %rax, 80(%rsp) movq %rcx, 72(%rsp) movl %edx, 12(%rsp) .LBB1_17: # in Loop: Header=BB1_4 Depth=1 leaq 80(%rsp), %rax movq %rax, 96(%rsp) leaq 72(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d movl $_Z14parallel_mergePfS_i, %edi leaq 96(%rsp), %r9 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_18: # in Loop: Header=BB1_4 Depth=1 callq hipDeviceSynchronize addl %ebx, %ebx cmpl %ebp, %ebx jg .LBB1_19 .LBB1_4: # =>This Inner Loop Header: Depth=1 incl %r15d movl %ebp, %eax xorl %edx, %edx divl %ebx # kill: def $eax killed $eax def $rax orq %r12, %rax cmpl $1024, %ebx # imm = 0x400 ja .LBB1_11 # %bb.5: # in Loop: Header=BB1_4 Depth=1 movl %ebx, %edx orq %r12, %rdx movq %rax, %rdi movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testb $1, %r15b jne .LBB1_9 # %bb.6: # in Loop: Header=BB1_4 Depth=1 testl %eax, %eax jne .LBB1_18 # %bb.7: # in Loop: Header=BB1_4 Depth=1 movq 16(%rsp), %rax movq 88(%rsp), %rcx jmp .LBB1_8 .p2align 4, 0x90 .LBB1_11: # in Loop: Header=BB1_4 Depth=1 movq %rax, %rdi movl $1, %esi movq %r13, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testb $1, %r15b jne .LBB1_14 # %bb.12: # in Loop: Header=BB1_4 Depth=1 testl %eax, %eax jne .LBB1_18 # %bb.13: # in Loop: Header=BB1_4 Depth=1 movq 16(%rsp), %rax movq 88(%rsp), %rcx jmp .LBB1_16 .p2align 4, 0x90 .LBB1_9: # in Loop: Header=BB1_4 Depth=1 testl %eax, %eax jne .LBB1_18 # %bb.10: # in Loop: Header=BB1_4 Depth=1 movq 88(%rsp), %rax movq 16(%rsp), %rcx .LBB1_8: # in Loop: Header=BB1_4 Depth=1 movq %rax, 80(%rsp) movq %rcx, 72(%rsp) movl $1, 12(%rsp) jmp .LBB1_17 .p2align 4, 0x90 .LBB1_14: # in Loop: Header=BB1_4 Depth=1 testl %eax, %eax jne .LBB1_18 # %bb.15: # in Loop: Header=BB1_4 Depth=1 movq 88(%rsp), %rax movq 16(%rsp), %rcx jmp .LBB1_16 .LBB1_19: # %._crit_edge.loopexit testb $1, %r15b leaq 16(%rsp), %rbx leaq 88(%rsp), %rax cmoveq %rax, %rbx movq 128(%rsp), %r12 # 8-byte Reload .LBB1_20: # %.critedge movq (%rbx), %rsi movq %r12, %rdi movq %r14, %rdx movl $2, %ecx callq hipMemcpy movq 16(%rsp), %rdi callq hipFree movq 88(%rsp), %rdi callq hipFree xorl %eax, %eax .LBB1_21: addq $136, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB1_1: .cfi_def_cfa_offset 192 movq stderr(%rip), %rcx movl $.L.str, %edi movl $63, %esi movl $1, %edx callq fwrite@PLT movl $1, %eax jmp .LBB1_21 .Lfunc_end1: .size _Z9cuda_sortiPf, .Lfunc_end1-_Z9cuda_sortiPf .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z14parallel_mergePfS_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z14parallel_mergePfS_i,@object # @_Z14parallel_mergePfS_i .section .rodata,"a",@progbits .globl _Z14parallel_mergePfS_i .p2align 3, 0x0 _Z14parallel_mergePfS_i: .quad _Z29__device_stub__parallel_mergePfS_i .size _Z14parallel_mergePfS_i, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "hipSetDevice failed! Do you have a CUDA-capable GPU installed?" .size .L.str, 64 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z14parallel_mergePfS_i" .size .L__unnamed_1, 24 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z29__device_stub__parallel_mergePfS_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z14parallel_mergePfS_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include "includes.h" __global__ void NormalizationExecutionKernel(unsigned char* src, float* dst, const int size, const float alpha, const float beta, const float bias) { int index = blockIdx.x * blockDim.x + threadIdx.x; if(index < size){ dst[index] = (float)(src[index] - alpha) / beta + bias; } }
code for sm_80 Function : _Z28NormalizationExecutionKernelPhPfifff .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */ /* 0x000e280000002500 */ /*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */ /* 0x001fca00078e0203 */ /*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */ /* 0x000fda0003f06270 */ /*0050*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0060*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */ /* 0x000fe20007f1e0ff */ /*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fc60000000a00 */ /*0080*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000037a11 */ /* 0x000fca00000f0eff */ /*0090*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x000ea2000c1e1100 */ /*00a0*/ MUFU.RCP R5, c[0x0][0x178] ; /* 0x00005e0000057b08 */ /* 0x000e220000001000 */ /*00b0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff067624 */ /* 0x000fe200078e00ff */ /*00c0*/ BSSY B0, 0x190 ; /* 0x000000c000007945 */ /* 0x000fe60003800000 */ /*00d0*/ FFMA R6, R5, -R6, 1 ; /* 0x3f80000005067423 */ /* 0x001fc80000000806 */ /*00e0*/ FFMA R5, R5, R6, R5 ; /* 0x0000000605057223 */ /* 0x000fe20000000005 */ /*00f0*/ I2F.U16 R4, R2 ; /* 0x0000000200047306 */ /* 0x004e240000101000 */ /*0100*/ FADD R4, R4, -c[0x0][0x174] ; /* 0x80005d0004047621 */ /* 0x001fcc0000000000 */ /*0110*/ FCHK P0, R4, c[0x0][0x178] ; /* 0x00005e0004007b02 */ /* 0x000e220000000000 */ /*0120*/ FFMA R6, R4, R5, RZ ; /* 0x0000000504067223 */ /* 0x000fc800000000ff */ /*0130*/ FFMA R7, R6, -c[0x0][0x178], R4 ; /* 0x80005e0006077a23 */ /* 0x000fc80000000004 */ /*0140*/ FFMA R5, R5, R7, R6 ; /* 0x0000000705057223 */ /* 0x000fe20000000006 */ /*0150*/ @!P0 BRA 0x180 ; /* 0x0000002000008947 */ /* 0x001fea0003800000 */ /*0160*/ MOV R2, 0x180 ; /* 0x0000018000027802 */ /* 0x000fe40000000f00 */ /*0170*/ CALL.REL.NOINC 0x1e0 ; /* 0x0000006000007944 */ /* 0x000fea0003c00000 */ /*0180*/ BSYNC B0 ; /* 0x0000000000007941 */ /* 0x000fea0003800000 */ /*0190*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */ /* 0x000fe400078e00ff */ /*01a0*/ FADD R5, R5, c[0x0][0x17c] ; /* 0x00005f0005057621 */ /* 0x000fe40000000000 */ /*01b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */ /* 0x000fca00078e0203 */ /*01c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */ /* 0x000fe2000c101904 */ /*01d0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*01e0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff0b7624 */ /* 0x000fe200078e00ff */ /*01f0*/ SHF.R.U32.HI R3, RZ, 0x17, R4.reuse ; /* 0x00000017ff037819 */ /* 0x100fe20000011604 */ /*0200*/ BSSY B1, 0x850 ; /* 0x0000064000017945 */ /* 0x000fe20003800000 */ /*0210*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */ /* 0x000fe400078e0004 */ /*0220*/ SHF.R.U32.HI R5, RZ, 0x17, R11 ; /* 0x00000017ff057819 */ /* 0x000fe2000001160b */ /*0230*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff077624 */ /* 0x000fe200078e00ff */ /*0240*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */ /* 0x000fe400078ec0ff */ /*0250*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */ /* 0x000fc400078ec0ff */ /*0260*/ IADD3 R9, R3, -0x1, RZ ; /* 0xffffffff03097810 */ /* 0x000fe40007ffe0ff */ /*0270*/ IADD3 R10, R5, -0x1, RZ ; /* 0xffffffff050a7810 */ /* 0x000fc80007ffe0ff */ /*0280*/ ISETP.GT.U32.AND P0, PT, R10, 0xfd, PT ; /* 0x000000fd0a00780c */ /* 0x000fc80003f04070 */ /*0290*/ ISETP.GT.U32.OR P0, PT, R9, 0xfd, P0 ; /* 0x000000fd0900780c */ /* 0x000fda0000704470 */ /*02a0*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff088224 */ /* 0x000fe200078e00ff */ /*02b0*/ @!P0 BRA 0x430 ; /* 0x0000017000008947 */ /* 0x000fea0003800000 */ /*02c0*/ FSETP.GTU.FTZ.AND P1, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */ /* 0x000fe40003f3c200 */ /*02d0*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */ /* 0x000fc80003f1c200 */ /*02e0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fda0000703570 */ /*02f0*/ @P0 BRA 0x830 ; /* 0x0000053000000947 */ /* 0x000fea0003800000 */ /*0300*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, R6, 0xc8, !PT ; /* 0x7fffffff07ff7812 */ /* 0x000fda000780c806 */ /*0310*/ @!P0 BRA 0x810 ; /* 0x000004f000008947 */ /* 0x000fea0003800000 */ /*0320*/ FSETP.NEU.FTZ.AND P2, PT, |R4|.reuse, +INF , PT ; /* 0x7f8000000400780b */ /* 0x040fe40003f5d200 */ /*0330*/ FSETP.NEU.FTZ.AND P1, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */ /* 0x000fe40003f3d200 */ /*0340*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */ /* 0x000fd60003f1d200 */ /*0350*/ @!P1 BRA !P2, 0x810 ; /* 0x000004b000009947 */ /* 0x000fea0005000000 */ /*0360*/ LOP3.LUT P2, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */ /* 0x000fc8000784c0ff */ /*0370*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */ /* 0x000fda0000f24572 */ /*0380*/ @P1 BRA 0x7f0 ; /* 0x0000046000001947 */ /* 0x000fea0003800000 */ /*0390*/ LOP3.LUT P1, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */ /* 0x000fc8000782c0ff */ /*03a0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */ /* 0x000fda0000702572 */ /*03b0*/ @P0 BRA 0x7c0 ; /* 0x0000040000000947 */ /* 0x000fea0003800000 */ /*03c0*/ ISETP.GE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */ /* 0x000fe40003f06270 */ /*03d0*/ ISETP.GE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */ /* 0x000fd60003f26270 */ /*03e0*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff080224 */ /* 0x000fe400078e00ff */ /*03f0*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, -0x40 ; /* 0xffffffc0ff088424 */ /* 0x000fe400078e00ff */ /*0400*/ @!P0 FFMA R6, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004068823 */ /* 0x000fe400000000ff */ /*0410*/ @!P1 FFMA R7, R11, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000b079823 */ /* 0x000fe200000000ff */ /*0420*/ @!P1 IADD3 R8, R8, 0x40, RZ ; /* 0x0000004008089810 */ /* 0x000fe40007ffe0ff */ /*0430*/ LEA R4, R5, 0xc0800000, 0x17 ; /* 0xc080000005047811 */ /* 0x000fe200078eb8ff */ /*0440*/ BSSY B2, 0x7b0 ; /* 0x0000036000027945 */ /* 0x000fe80003800000 */ /*0450*/ IMAD.IADD R7, R7, 0x1, -R4 ; /* 0x0000000107077824 */ /* 0x000fe200078e0a04 */ /*0460*/ IADD3 R4, R3, -0x7f, RZ ; /* 0xffffff8103047810 */ /* 0x000fc60007ffe0ff */ /*0470*/ MUFU.RCP R9, R7 ; /* 0x0000000700097308 */ /* 0x000e220000001000 */ /*0480*/ FADD.FTZ R11, -R7, -RZ ; /* 0x800000ff070b7221 */ /* 0x000fe20000010100 */ /*0490*/ IADD3 R5, R4.reuse, 0x7f, -R5 ; /* 0x0000007f04057810 */ /* 0x040fe20007ffe805 */ /*04a0*/ IMAD R6, R4, -0x800000, R6 ; /* 0xff80000004067824 */ /* 0x000fc800078e0206 */ /*04b0*/ IMAD.IADD R5, R5, 0x1, R8 ; /* 0x0000000105057824 */ /* 0x000fe400078e0208 */ /*04c0*/ FFMA R10, R9, R11, 1 ; /* 0x3f800000090a7423 */ /* 0x001fc8000000000b */ /*04d0*/ FFMA R9, R9, R10, R9 ; /* 0x0000000a09097223 */ /* 0x000fc80000000009 */ /*04e0*/ FFMA R3, R6, R9, RZ ; /* 0x0000000906037223 */ /* 0x000fc800000000ff */ /*04f0*/ FFMA R10, R11, R3, R6 ; /* 0x000000030b0a7223 */ /* 0x000fc80000000006 */ /*0500*/ FFMA R10, R9, R10, R3 ; /* 0x0000000a090a7223 */ /* 0x000fc80000000003 */ /*0510*/ FFMA R11, R11, R10, R6 ; /* 0x0000000a0b0b7223 */ /* 0x000fc80000000006 */ /*0520*/ FFMA R3, R9, R11, R10 ; /* 0x0000000b09037223 */ /* 0x000fca000000000a */ /*0530*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */ /* 0x000fc80000011603 */ /*0540*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */ /* 0x000fca00078ec0ff */ /*0550*/ IMAD.IADD R8, R4, 0x1, R5 ; /* 0x0000000104087824 */ /* 0x000fca00078e0205 */ /*0560*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */ /* 0x000fc80007ffe0ff */ /*0570*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */ /* 0x000fda0003f06070 */ /*0580*/ @!P0 BRA 0x790 ; /* 0x0000020000008947 */ /* 0x000fea0003800000 */ /*0590*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */ /* 0x000fda0003f04270 */ /*05a0*/ @P0 BRA 0x760 ; /* 0x000001b000000947 */ /* 0x000fea0003800000 */ /*05b0*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */ /* 0x000fda0003f06270 */ /*05c0*/ @P0 BRA 0x7a0 ; /* 0x000001d000000947 */ /* 0x000fea0003800000 */ /*05d0*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ; /* 0xffffffe80800780c */ /* 0x000fe40003f06270 */ /*05e0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */ /* 0x000fd600078ec0ff */ /*05f0*/ @!P0 BRA 0x7a0 ; /* 0x000001a000008947 */ /* 0x000fea0003800000 */ /*0600*/ FFMA.RZ R4, R9.reuse, R11.reuse, R10.reuse ; /* 0x0000000b09047223 */ /* 0x1c0fe2000000c00a */ /*0610*/ IADD3 R7, R8.reuse, 0x20, RZ ; /* 0x0000002008077810 */ /* 0x040fe20007ffe0ff */ /*0620*/ FFMA.RM R5, R9.reuse, R11.reuse, R10.reuse ; /* 0x0000000b09057223 */ /* 0x1c0fe2000000400a */ /*0630*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */ /* 0x000fe40003f45270 */ /*0640*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */ /* 0x000fe200078ec0ff */ /*0650*/ FFMA.RP R4, R9, R11, R10 ; /* 0x0000000b09047223 */ /* 0x000fe2000000800a */ /*0660*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */ /* 0x000fe20003f25270 */ /*0670*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */ /* 0x000fe200078e0a08 */ /*0680*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */ /* 0x000fe400078efcff */ /*0690*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */ /* 0x000fc40003f1d000 */ /*06a0*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */ /* 0x000fe400000006ff */ /*06b0*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */ /* 0x000fe40001000000 */ /*06c0*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */ /* 0x000fe40000f25270 */ /*06d0*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */ /* 0x000fe40000011606 */ /*06e0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40000703570 */ /*06f0*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */ /* 0x000fc40000011605 */ /*0700*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */ /* 0x000fc80004000000 */ /*0710*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */ /* 0x000fc800078ef807 */ /*0720*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */ /* 0x000fca00078ec0ff */ /*0730*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */ /* 0x000fca00078e0204 */ /*0740*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */ /* 0x000fe200078efcff */ /*0750*/ BRA 0x7a0 ; /* 0x0000004000007947 */ /* 0x000fea0003800000 */ /*0760*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */ /* 0x000fc800078ec0ff */ /*0770*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */ /* 0x000fe200078efcff */ /*0780*/ BRA 0x7a0 ; /* 0x0000001000007947 */ /* 0x000fea0003800000 */ /*0790*/ IMAD R3, R5, 0x800000, R3 ; /* 0x0080000005037824 */ /* 0x000fe400078e0203 */ /*07a0*/ BSYNC B2 ; /* 0x0000000000027941 */ /* 0x000fea0003800000 */ /*07b0*/ BRA 0x840 ; /* 0x0000008000007947 */ /* 0x000fea0003800000 */ /*07c0*/ LOP3.LUT R3, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007037812 */ /* 0x000fc800078e4806 */ /*07d0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */ /* 0x000fe200078efcff */ /*07e0*/ BRA 0x840 ; /* 0x0000005000007947 */ /* 0x000fea0003800000 */ /*07f0*/ LOP3.LUT R3, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007037812 */ /* 0x000fe200078e4806 */ /*0800*/ BRA 0x840 ; /* 0x0000003000007947 */ /* 0x000fea0003800000 */ /*0810*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */ /* 0x000e220000001400 */ /*0820*/ BRA 0x840 ; /* 0x0000001000007947 */ /* 0x000fea0003800000 */ /*0830*/ FADD.FTZ R3, R4, c[0x0][0x178] ; /* 0x00005e0004037621 */ /* 0x000fe40000010000 */ /*0840*/ BSYNC B1 ; /* 0x0000000000017941 */ /* 0x000fea0003800000 */ /*0850*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */ /* 0x001fe400078e0003 */ /*0860*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */ /* 0x000fc800078e00ff */ /*0870*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff78002007950 */ /* 0x000fea0003c3ffff */ /*0880*/ BRA 0x880; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0890*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0900*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0910*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0920*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0930*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0940*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0950*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0960*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0970*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include "includes.h" __global__ void NormalizationExecutionKernel(unsigned char* src, float* dst, const int size, const float alpha, const float beta, const float bias) { int index = blockIdx.x * blockDim.x + threadIdx.x; if(index < size){ dst[index] = (float)(src[index] - alpha) / beta + bias; } }
.file "tmpxft_001510f0_00000000-6_NormalizationExecutionKernel.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z54__device_stub__Z28NormalizationExecutionKernelPhPfifffPhPfifff .type _Z54__device_stub__Z28NormalizationExecutionKernelPhPfifffPhPfifff, @function _Z54__device_stub__Z28NormalizationExecutionKernelPhPfifffPhPfifff: .LFB2051: .cfi_startproc endbr64 subq $168, %rsp .cfi_def_cfa_offset 176 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movss %xmm0, 8(%rsp) movss %xmm1, 4(%rsp) movss %xmm2, (%rsp) movq %fs:40, %rax movq %rax, 152(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) leaq 4(%rsp), %rax movq %rax, 128(%rsp) movq %rsp, %rax movq %rax, 136(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 152(%rsp), %rax subq %fs:40, %rax jne .L8 addq $168, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 184 pushq 40(%rsp) .cfi_def_cfa_offset 192 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z28NormalizationExecutionKernelPhPfifff(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 176 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z54__device_stub__Z28NormalizationExecutionKernelPhPfifffPhPfifff, .-_Z54__device_stub__Z28NormalizationExecutionKernelPhPfifffPhPfifff .globl _Z28NormalizationExecutionKernelPhPfifff .type _Z28NormalizationExecutionKernelPhPfifff, @function _Z28NormalizationExecutionKernelPhPfifff: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z54__device_stub__Z28NormalizationExecutionKernelPhPfifffPhPfifff addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z28NormalizationExecutionKernelPhPfifff, .-_Z28NormalizationExecutionKernelPhPfifff .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "_Z28NormalizationExecutionKernelPhPfifff" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z28NormalizationExecutionKernelPhPfifff(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include "includes.h" __global__ void NormalizationExecutionKernel(unsigned char* src, float* dst, const int size, const float alpha, const float beta, const float bias) { int index = blockIdx.x * blockDim.x + threadIdx.x; if(index < size){ dst[index] = (float)(src[index] - alpha) / beta + bias; } }
#include <hip/hip_runtime.h> #include "includes.h" __global__ void NormalizationExecutionKernel(unsigned char* src, float* dst, const int size, const float alpha, const float beta, const float bias) { int index = blockIdx.x * blockDim.x + threadIdx.x; if(index < size){ dst[index] = (float)(src[index] - alpha) / beta + bias; } }