code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sseqTupleAppender_tTSeq_3_0_Int__n2 (
input [7:0] I0_0,
input [7:0] I0_1,
input [7:0] I1,
output [7:0] O_0,
output [7:0] O_1,
output [7:0] O_2,
output valid_down,
input valid_up
);
assign O_0 = I0_0;
assign O_1 = I0_1;
assign O_2 = I1;
assign valid_down = valid_up;
endmodu... | 7.061223 |
module sseqTupleAppender_tInt_n2 (
input [7:0] I0_0,
input [7:0] I0_1,
input [7:0] I1,
output [7:0] O_0,
output [7:0] O_1,
output [7:0] O_2,
output valid_down,
input valid_up
);
assign O_0 = I0_0;
assign O_1 = I0_1;
assign O_2 = I1;
assign valid_down = valid_up;
endmodule
| 7.061223 |
module corebit_xor (
input in0,
input in1,
output out
);
assign out = in0 ^ in1;
endmodule
| 7.624638 |
module corebit_not (
input in,
output out
);
assign out = ~in;
endmodule
| 8.318293 |
module corebit_eq (
input I0,
input I1,
output O
);
wire not_inst0_out;
wire xor_inst0_out;
corebit_not not_inst0 (
.in (xor_inst0_out),
.out(not_inst0_out)
);
corebit_xor xor_inst0 (
.in0(I0),
.in1(I1),
.out(xor_inst0_out)
);
assign O = not_inst0_out;
endmodule... | 7.456911 |
module corebit_const #(
parameter value = 1
) (
output out
);
assign out = value;
endmodule
| 7.833235 |
module corebit_and (
input in0,
input in1,
output out
);
assign out = in0 & in1;
endmodule
| 8.125026 |
module coreir_ult #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 < in1;
endmodule
| 7.861561 |
module coreir_ugt #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 > in1;
endmodule
| 7.36211 |
module coreir_term #(
parameter width = 1
) (
input [width-1:0] in
);
endmodule
| 6.849594 |
module coreir_slice #(
parameter hi = 1,
parameter lo = 0,
parameter width = 1
) (
input [width-1:0] in,
output [hi-lo-1:0] out
);
assign out = in[hi-1:lo];
endmodule
| 8.799926 |
module coreir_shl #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 << in1;
endmodule
| 8.595943 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_not #(
parameter width = 1
) (
input [width-1:0] in,
output [width-1:0] out
);
assign out = ~in;
endmodule
| 8.534147 |
module coreir_neg #(
parameter width = 1
) (
input [width-1:0] in,
output [width-1:0] out
);
assign out = -in;
endmodule
| 7.306788 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module coreir_mem #(
parameter has_init = 0,
parameter depth = 1,
parameter width = 1
) (
input clk,
input [width-1:0] wdata,
input [$clog2(depth)-1:0] waddr,
input wen,
output [width-1:0] rdata,
input [$clog2(depth)-1:0] raddr
);
reg [width-1:0] data[depth-1:0];
always @(posedge... | 7.482949 |
module coreir_lshr #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 >> in1;
endmodule
| 8.306547 |
module coreir_eq #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 == in1;
endmodule
| 7.939296 |
module coreir_const #(
parameter width = 1,
parameter value = 1
) (
output [width-1:0] out
);
assign out = value;
endmodule
| 8.127638 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module \commonlib_muxn__N2__width8 (
input [7:0] in_data_0,
input [7:0] in_data_1,
input [0:0] in_sel,
output [7:0] out
);
wire [7:0] _join_out;
coreir_mux #(
.width(8)
) _join (
.in0(in_data_0),
.in1(in_data_1),
.out(_join_out),
.sel(in_sel[0])
);
assign out =... | 7.889703 |
module \commonlib_muxn__N4__width8 (
input [7:0] in_data_0,
input [7:0] in_data_1,
input [7:0] in_data_2,
input [7:0] in_data_3,
input [1:0] in_sel,
output [7:0] out
);
wire [7:0] _join_out;
wire [7:0] muxN_0_out;
wire [7:0] muxN_1_out;
wire [0:0] sel_slice0_out;
wire [0:0] sel_sl... | 7.889703 |
module \commonlib_muxn__N2__width4 (
input [3:0] in_data_0,
input [3:0] in_data_1,
input [0:0] in_sel,
output [3:0] out
);
wire [3:0] _join_out;
coreir_mux #(
.width(4)
) _join (
.in0(in_data_0),
.in1(in_data_1),
.out(_join_out),
.sel(in_sel[0])
);
assign out =... | 7.889703 |
module \commonlib_muxn__N2__width3 (
input [2:0] in_data_0,
input [2:0] in_data_1,
input [0:0] in_sel,
output [2:0] out
);
wire [2:0] _join_out;
coreir_mux #(
.width(3)
) _join (
.in0(in_data_0),
.in1(in_data_1),
.out(_join_out),
.sel(in_sel[0])
);
assign out =... | 7.889703 |
module \commonlib_muxn__N2__width2 (
input [1:0] in_data_0,
input [1:0] in_data_1,
input [0:0] in_sel,
output [1:0] out
);
wire [1:0] _join_out;
coreir_mux #(
.width(2)
) _join (
.in0(in_data_0),
.in1(in_data_1),
.out(_join_out),
.sel(in_sel[0])
);
assign out =... | 7.889703 |
module \commonlib_muxn__N2__width1 (
input [0:0] in_data_0,
input [0:0] in_data_1,
input [0:0] in_sel,
output [0:0] out
);
wire [0:0] _join_out;
coreir_mux #(
.width(1)
) _join (
.in0(in_data_0),
.in1(in_data_1),
.out(_join_out),
.sel(in_sel[0])
);
assign out =... | 7.889703 |
module \commonlib_muxn__N1__width8 (
input [7:0] in_data_0,
input [0:0] in_sel,
output [7:0] out
);
corebit_term term_sel (.in(in_sel[0]));
assign out = in_data_0;
endmodule
| 7.889703 |
module \commonlib_muxn__N3__width8 (
input [7:0] in_data_0,
input [7:0] in_data_1,
input [7:0] in_data_2,
input [1:0] in_sel,
output [7:0] out
);
wire [7:0] _join_out;
wire [7:0] muxN_0_out;
wire [7:0] muxN_1_out;
wire [0:0] sel_slice0_out;
wire [0:0] sel_slice1_out;
coreir_mux #(
... | 7.889703 |
module lutN #(
parameter N = 1,
parameter init = 1
) (
input [N-1:0] in,
output out
);
assign out = init[in];
endmodule
| 7.756611 |
module RShift_Atom (
input [7:0] I__0,
input [7:0] I__1,
output [7:0] O,
output valid_down,
input valid_up
);
wire [7:0] lshr8_inst0_out;
coreir_lshr #(
.width(8)
) lshr8_inst0 (
.in0(I__0),
.in1(I__1),
.out(lshr8_inst0_out)
);
assign O = lshr8_inst0_out;
assign v... | 7.73328 |
module RAM3x8 (
input clk,
input [1:0] RADDR,
output [7:0] RDATA,
input [1:0] WADDR,
input [7:0] WDATA,
input WE
);
wire [7:0] coreir_mem3x8_inst0_rdata;
coreir_mem #(
.depth(3),
.has_init(0),
.width(8)
) coreir_mem3x8_inst0 (
.clk (clk),
.raddr(RADDR),
... | 6.959247 |
module Negate8 (
input [7:0] I,
output [7:0] O
);
wire [7:0] coreir_neg_inst0_out;
coreir_neg #(
.width(8)
) coreir_neg_inst0 (
.in (I),
.out(coreir_neg_inst0_out)
);
assign O = coreir_neg_inst0_out;
endmodule
| 7.306678 |
module NativeMapParallel_n4 (
input [7:0] I_0,
input [7:0] I_1,
input [7:0] I_2,
input [7:0] I_3,
output [7:0] out_0,
output [7:0] out_1,
output [7:0] out_2,
output [7:0] out_3
);
wire [7:0] dehydrate_tArray_8_Bit__inst0_out;
wire [7:0] dehydrate_tArray_8_Bit__inst1_out;
wire [... | 7.274395 |
module NativeMapParallel_n3 (
input [7:0] I_0,
input [7:0] I_1,
input [7:0] I_2,
output [7:0] out_0,
output [7:0] out_1,
output [7:0] out_2
);
wire [7:0] dehydrate_tArray_8_Bit__inst0_out;
wire [7:0] dehydrate_tArray_8_Bit__inst1_out;
wire [7:0] dehydrate_tArray_8_Bit__inst2_out;
\aet... | 7.274395 |
module NativeMapParallel_n2_unq1 (
input [7:0] I_0,
input [7:0] I_1,
output [7:0] out_0,
output [7:0] out_1
);
wire [7:0] dehydrate_tArray_8_Out_Bit___inst0_out;
wire [7:0] dehydrate_tArray_8_Out_Bit___inst1_out;
\aetherlinglib_dehydrate__hydratedTypeBit8 dehydrate_tArray_8_Out_Bit___inst0 (
... | 7.274395 |
module NativeMapParallel_n2 (
input [7:0] I_0,
input [7:0] I_1,
output [7:0] out_0,
output [7:0] out_1
);
wire [7:0] dehydrate_tArray_8_Bit__inst0_out;
wire [7:0] dehydrate_tArray_8_Bit__inst1_out;
\aetherlinglib_dehydrate__hydratedTypeBit8 dehydrate_tArray_8_Bit__inst0 (
.in (I_0),
... | 7.274395 |
module Mux_Array_8_Out_Bit__t_2n (
input [7:0] data_0,
input [7:0] data_1,
output [7:0] out,
input [0:0] sel
);
wire [7:0] CommonlibMuxN_n2_w8_inst0_out;
wire [7:0] NativeMapParallel_n2_inst0_out_0;
wire [7:0] NativeMapParallel_n2_inst0_out_1;
wire [7:0] hydrate_tArray_8_Out_Bit___inst0_out;
... | 7.461788 |
module Mux_Array_8_Bit_t_4n (
input [7:0] data_0,
input [7:0] data_1,
input [7:0] data_2,
input [7:0] data_3,
output [7:0] out,
input [1:0] sel
);
wire [7:0] CommonlibMuxN_n4_w8_inst0_out;
wire [7:0] NativeMapParallel_n4_inst0_out_0;
wire [7:0] NativeMapParallel_n4_inst0_out_1;
wire... | 7.171087 |
module Mux_Array_8_Bit_t_3n (
input [7:0] data_0,
input [7:0] data_1,
input [7:0] data_2,
output [7:0] out,
input [1:0] sel
);
wire [7:0] CommonlibMuxN_n3_w8_inst0_out;
wire [7:0] NativeMapParallel_n3_inst0_out_0;
wire [7:0] NativeMapParallel_n3_inst0_out_1;
wire [7:0] NativeMapParallel_... | 7.171087 |
module Mux_Array_8_Bit_t_2n (
input [7:0] data_0,
input [7:0] data_1,
output [7:0] out,
input [0:0] sel
);
wire [7:0] CommonlibMuxN_n2_w8_inst0_out;
wire [7:0] NativeMapParallel_n2_inst0_out_0;
wire [7:0] NativeMapParallel_n2_inst0_out_1;
wire [7:0] hydrate_tArray_8_Bit__inst0_out;
\commonl... | 7.171087 |
module Mux_Array_8_Bit_t_1n (
input [7:0] data_0,
output [7:0] out,
input [0:0] sel
);
Term_Bits_1_t Term_Bits_1_t_inst0 (.I(sel));
assign out = data_0;
endmodule
| 7.171087 |
module Mux2xOutBits4 (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
input S
);
wire [3:0] coreir_commonlib_mux2x4_inst0_out;
\commonlib_muxn__N2__width4 coreir_commonlib_mux2x4_inst0 (
.in_data_0(I0),
.in_data_1(I1),
.in_sel(S),
.out(coreir_commonlib_mux2x4_inst0_out)
);... | 8.005808 |
module Mux2xOutBits3 (
input [2:0] I0,
input [2:0] I1,
output [2:0] O,
input S
);
wire [2:0] coreir_commonlib_mux2x3_inst0_out;
\commonlib_muxn__N2__width3 coreir_commonlib_mux2x3_inst0 (
.in_data_0(I0),
.in_data_1(I1),
.in_sel(S),
.out(coreir_commonlib_mux2x3_inst0_out)
);... | 7.210649 |
module Mux2xOutBits2 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
input S
);
wire [1:0] coreir_commonlib_mux2x2_inst0_out;
\commonlib_muxn__N2__width2 coreir_commonlib_mux2x2_inst0 (
.in_data_0(I0),
.in_data_1(I1),
.in_sel(S),
.out(coreir_commonlib_mux2x2_inst0_out)
);... | 7.816223 |
module Mux2xNone (
input I0,
input I1,
output O,
input S
);
wire [0:0] coreir_commonlib_mux2x1_inst0_out;
\commonlib_muxn__N2__width1 coreir_commonlib_mux2x1_inst0 (
.in_data_0(I0),
.in_data_1(I1),
.in_sel(S),
.out(coreir_commonlib_mux2x1_inst0_out)
);
assign O = corei... | 8.404032 |
module Map_T_n3_i0_unq1 (
input clk,
input [7:0] I0,
input [7:0] I1,
output [7:0] O__0,
output [7:0] O__1,
output valid_down,
input valid_up
);
wire [7:0] Map_T_n3_i0_inst0_O__0;
wire [7:0] Map_T_n3_i0_inst0_O__1;
wire Map_T_n3_i0_inst0_valid_down;
Map_T_n3_i0 Map_T_n3_i0_inst0 (
... | 6.890969 |
module Map_T_n1_i2 (
input clk,
input [7:0] I0,
input [7:0] I1,
output [7:0] O_0,
output [7:0] O_1,
output valid_down,
input valid_up
);
wire [7:0] sseqTupleCreator_tInt_inst0_O_0;
wire [7:0] sseqTupleCreator_tInt_inst0_O_1;
wire sseqTupleCreator_tInt_inst0_valid_down;
sseqTupleCreat... | 7.299216 |
module Map_T_n16_i0_unq4 (
input clk,
input [7:0] I0_0,
input [7:0] I0_1,
input [7:0] I1,
output [7:0] O_0,
output [7:0] O_1,
output [7:0] O_2,
output valid_down,
input valid_up
);
wire [7:0] Map_T_n1_i2_inst0_O_0;
wire [7:0] Map_T_n1_i2_inst0_O_1;
wire [7:0] Map_T_n1_i2_inst0_... | 7.059711 |
module Map_T_n16_i0_unq3 (
input clk,
input [7:0] I0,
input [7:0] I1,
output [7:0] O_0,
output [7:0] O_1,
output valid_down,
input valid_up
);
wire [7:0] Map_T_n1_i2_inst0_O_0;
wire [7:0] Map_T_n1_i2_inst0_O_1;
wire Map_T_n1_i2_inst0_valid_down;
Map_T_n1_i2_unq5 Map_T_n1_i2_inst0 (
... | 7.059711 |
module Map_T_n16_i0_unq1 (
input clk,
input [7:0] I0_0,
input [7:0] I0_1,
input [7:0] I1,
output [7:0] O_0,
output [7:0] O_1,
output [7:0] O_2,
output valid_down,
input valid_up
);
wire [7:0] Map_T_n1_i2_inst0_O_0;
wire [7:0] Map_T_n1_i2_inst0_O_1;
wire [7:0] Map_T_n1_i2_inst0_... | 7.059711 |
module Map_T_n16_i0 (
input clk,
input [7:0] I0,
input [7:0] I1,
output [7:0] O_0,
output [7:0] O_1,
output valid_down,
input valid_up
);
wire [7:0] Map_T_n1_i2_inst0_O_0;
wire [7:0] Map_T_n1_i2_inst0_O_1;
wire Map_T_n1_i2_inst0_valid_down;
Map_T_n1_i2_unq1 Map_T_n1_i2_inst0 (
... | 7.587533 |
module Lt_Atom (
input [7:0] I__0,
input [7:0] I__1,
output [0:0] O,
output valid_down,
input valid_up
);
wire coreir_ult8_inst0_out;
coreir_ult #(
.width(8)
) coreir_ult8_inst0 (
.in0(I__0),
.in1(I__1),
.out(coreir_ult8_inst0_out)
);
assign O = coreir_ult8_inst0_ou... | 7.118379 |
module LUT4_8192 (
input I0,
input I1,
input I2,
input I3,
output O
);
wire coreir_lut4_inst0_out;
lutN #(
.init(16'h2000),
.N(4)
) coreir_lut4_inst0 (
.in ({I3, I2, I1, I0}),
.out(coreir_lut4_inst0_out)
);
assign O = coreir_lut4_inst0_out;
endmodule
| 7.163747 |
module LUT4_256 (
input I0,
input I1,
input I2,
input I3,
output O
);
wire coreir_lut4_inst0_out;
lutN #(
.init(16'h0100),
.N(4)
) coreir_lut4_inst0 (
.in ({I3, I2, I1, I0}),
.out(coreir_lut4_inst0_out)
);
assign O = coreir_lut4_inst0_out;
endmodule
| 7.445537 |
module LUT4_2048 (
input I0,
input I1,
input I2,
input I3,
output O
);
wire coreir_lut4_inst0_out;
lutN #(
.init(16'h0800),
.N(4)
) coreir_lut4_inst0 (
.in ({I3, I2, I1, I0}),
.out(coreir_lut4_inst0_out)
);
assign O = coreir_lut4_inst0_out;
endmodule
| 7.636525 |
module LUT4_170 (
input I0,
input I1,
input I2,
input I3,
output O
);
wire coreir_lut4_inst0_out;
lutN #(
.init(16'h00aa),
.N(4)
) coreir_lut4_inst0 (
.in ({I3, I2, I1, I0}),
.out(coreir_lut4_inst0_out)
);
assign O = coreir_lut4_inst0_out;
endmodule
| 6.844785 |
module LUT4_16384 (
input I0,
input I1,
input I2,
input I3,
output O
);
wire coreir_lut4_inst0_out;
lutN #(
.init(16'h4000),
.N(4)
) coreir_lut4_inst0 (
.in ({I3, I2, I1, I0}),
.out(coreir_lut4_inst0_out)
);
assign O = coreir_lut4_inst0_out;
endmodule
| 7.343121 |
module LUT4_16 (
input I0,
input I1,
input I2,
input I3,
output O
);
wire coreir_lut4_inst0_out;
lutN #(
.init(16'h0010),
.N(4)
) coreir_lut4_inst0 (
.in ({I3, I2, I1, I0}),
.out(coreir_lut4_inst0_out)
);
assign O = coreir_lut4_inst0_out;
endmodule
| 7.23346 |
module LUT4_1024 (
input I0,
input I1,
input I2,
input I3,
output O
);
wire coreir_lut4_inst0_out;
lutN #(
.init(16'h0400),
.N(4)
) coreir_lut4_inst0 (
.in ({I3, I2, I1, I0}),
.out(coreir_lut4_inst0_out)
);
assign O = coreir_lut4_inst0_out;
endmodule
| 7.371496 |
module LUT4_1 (
input I0,
input I1,
input I2,
input I3,
output O
);
wire coreir_lut4_inst0_out;
lutN #(
.init(16'h0001),
.N(4)
) coreir_lut4_inst0 (
.in ({I3, I2, I1, I0}),
.out(coreir_lut4_inst0_out)
);
assign O = coreir_lut4_inst0_out;
endmodule
| 7.01998 |
module LUT4_0 (
input I0,
input I1,
input I2,
input I3,
output O
);
wire coreir_lut4_inst0_out;
lutN #(
.init(16'h0000),
.N(4)
) coreir_lut4_inst0 (
.in ({I3, I2, I1, I0}),
.out(coreir_lut4_inst0_out)
);
assign O = coreir_lut4_inst0_out;
endmodule
| 7.259812 |
module LUT3_128 (
input I0,
input I1,
input I2,
output O
);
wire coreir_lut3_inst0_out;
lutN #(
.init(8'h80),
.N(3)
) coreir_lut3_inst0 (
.in ({I2, I1, I0}),
.out(coreir_lut3_inst0_out)
);
assign O = coreir_lut3_inst0_out;
endmodule
| 7.565933 |
module LUT2_8 (
input I0,
input I1,
output O
);
wire coreir_lut2_inst0_out;
lutN #(
.init(4'h8),
.N(2)
) coreir_lut2_inst0 (
.in ({I1, I0}),
.out(coreir_lut2_inst0_out)
);
assign O = coreir_lut2_inst0_out;
endmodule
| 7.722694 |
module LUT2_4 (
input I0,
input I1,
output O
);
wire coreir_lut2_inst0_out;
lutN #(
.init(4'h4),
.N(2)
) coreir_lut2_inst0 (
.in ({I1, I0}),
.out(coreir_lut2_inst0_out)
);
assign O = coreir_lut2_inst0_out;
endmodule
| 7.674267 |
module LUT2_2 (
input I0,
input I1,
output O
);
wire coreir_lut2_inst0_out;
lutN #(
.init(4'h2),
.N(2)
) coreir_lut2_inst0 (
.in ({I1, I0}),
.out(coreir_lut2_inst0_out)
);
assign O = coreir_lut2_inst0_out;
endmodule
| 7.802919 |
module LUT2_1 (
input I0,
input I1,
output O
);
wire coreir_lut2_inst0_out;
lutN #(
.init(4'h1),
.N(2)
) coreir_lut2_inst0 (
.in ({I1, I0}),
.out(coreir_lut2_inst0_out)
);
assign O = coreir_lut2_inst0_out;
endmodule
| 7.464635 |
module LUT1_1 (
input I0,
output O
);
wire coreir_lut1_inst0_out;
lutN #(
.init(2'h1),
.N(1)
) coreir_lut1_inst0 (
.in (I0),
.out(coreir_lut1_inst0_out)
);
assign O = coreir_lut1_inst0_out;
endmodule
| 7.409016 |
module LUT1_0 (
input I0,
output O
);
wire coreir_lut1_inst0_out;
lutN #(
.init(2'h0),
.N(1)
) coreir_lut1_inst0 (
.in (I0),
.out(coreir_lut1_inst0_out)
);
assign O = coreir_lut1_inst0_out;
endmodule
| 7.399772 |
module LShift_Atom (
input [7:0] I__0,
input [7:0] I__1,
output [7:0] O,
output valid_down,
input valid_up
);
wire [7:0] shl8_inst0_out;
coreir_shl #(
.width(8)
) shl8_inst0 (
.in0(I__0),
.in1(I__1),
.out(shl8_inst0_out)
);
assign O = shl8_inst0_out;
assign valid_... | 8.458485 |
module Map_T_n3_i0_unq2 (
input clk,
input [7:0] I__0,
input [7:0] I__1,
output [7:0] O,
output valid_down,
input valid_up
);
wire [7:0] LShift_Atom_inst0_O;
wire LShift_Atom_inst0_valid_down;
LShift_Atom LShift_Atom_inst0 (
.I__0(I__0),
.I__1(I__1),
.O(LShift_Atom_inst0_... | 6.890969 |
module Map_T_n3_i0_unq3 (
input clk,
input [7:0] I__0,
input [7:0] I__1,
output [7:0] O,
output valid_down,
input valid_up
);
wire [7:0] Map_T_n3_i0_inst0_O;
wire Map_T_n3_i0_inst0_valid_down;
Map_T_n3_i0_unq2 Map_T_n3_i0_inst0 (
.clk(clk),
.I__0(I__0),
.I__1(I__1),
... | 6.890969 |
module If_Atom_Intt (
input [0:0] I__0,
input [7:0] I__1__0,
input [7:0] I__1__1,
output [7:0] O,
output valid_down,
input valid_up
);
wire [7:0] Mux_Array_8_Bit_t_2n_inst0_out;
Mux_Array_8_Bit_t_2n Mux_Array_8_Bit_t_2n_inst0 (
.data_0(I__1__1),
.data_1(I__1__0),
.out(Mux_A... | 7.310169 |
module Register_Array_8_Out_Bit__t_0init_TrueCE_FalseRESET (
input CE,
input clk,
input [7:0] I,
output [7:0] O
);
wire [7:0] Register8CE_inst0_O;
Register8CE Register8CE_inst0 (
.CE (CE),
.clk(clk),
.I (I),
.O (Register8CE_inst0_O)
);
assign O = Register8CE_inst0_O;
en... | 7.102239 |
module Register_Array_8_Bit_t_0init_TrueCE_FalseRESET (
input CE,
input clk,
input [7:0] I,
output [7:0] O
);
wire [7:0] Register8CE_inst0_O;
Register8CE Register8CE_inst0 (
.CE (CE),
.clk(clk),
.I (I),
.O (Register8CE_inst0_O)
);
assign O = Register8CE_inst0_O;
endmodu... | 7.102239 |
module Register8 (
input clk,
input [7:0] I,
output [7:0] O
);
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst0_O;
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst1_O;
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst2_O;
wire DFF_init0_has_ce... | 6.73316 |
module Register_Array_8_Bit_t_0init_FalseCE_FalseRESET (
input clk,
input [7:0] I,
output [7:0] O
);
wire [7:0] Register8_inst0_O;
Register8 Register8_inst0 (
.clk(clk),
.I (I),
.O (Register8_inst0_O)
);
assign O = Register8_inst0_O;
endmodule
| 7.102239 |
module Register_Tuple_0_Array_8_Bit__1_Array_8_Bit__t_0init_FalseCE_FalseRESET (
input clk,
input [7:0] I__0,
input [7:0] I__1,
output [7:0] O__0,
output [7:0] O__1
);
wire [7:0] Register_Array_8_Bit_t_0init_FalseCE_FalseRESET_inst0_O;
wire [7:0] Register_Array_8_Bit_t_0init_FalseCE_FalseRESET_i... | 6.647526 |
module Register_Bitt_0init_FalseCE_FalseRESET (
input clk,
input I,
output O
);
wire [0:0] Register1_inst0_O;
Register1 Register1_inst0 (
.clk(clk),
.I (I),
.O (Register1_inst0_O)
);
assign O = Register1_inst0_O[0];
endmodule
| 7.503354 |
module Counter4_Mod9CE (
input CE,
input clk,
output [3:0] O
);
wire [3:0] Counter4CER_inst0_O;
wire LUT4_256_inst0_O;
wire and_inst0_out;
Counter4CER Counter4CER_inst0 (
.CE(CE),
.clk(clk),
.O(Counter4CER_inst0_O),
.RESET(and_inst0_out)
);
LUT4_256 LUT4_256_inst0 (
... | 6.770512 |
module Counter4_Mod15CE (
input CE,
input clk,
output [3:0] O
);
wire [3:0] Counter4CER_inst0_O;
wire LUT4_16384_inst0_O;
wire and_inst0_out;
Counter4CER Counter4CER_inst0 (
.CE(CE),
.clk(clk),
.O(Counter4CER_inst0_O),
.RESET(and_inst0_out)
);
LUT4_16384 LUT4_16384_inst0 ... | 7.712729 |
module Counter4_Mod14CE (
input CE,
input clk,
output [3:0] O
);
wire [3:0] Counter4CER_inst0_O;
wire LUT4_8192_inst0_O;
wire and_inst0_out;
Counter4CER Counter4CER_inst0 (
.CE(CE),
.clk(clk),
.O(Counter4CER_inst0_O),
.RESET(and_inst0_out)
);
LUT4_8192 LUT4_8192_inst0 (
... | 7.712729 |
module Counter4_Mod12CE (
input CE,
input clk,
output [3:0] O
);
wire [3:0] Counter4CER_inst0_O;
wire LUT4_2048_inst0_O;
wire and_inst0_out;
Counter4CER Counter4CER_inst0 (
.CE(CE),
.clk(clk),
.O(Counter4CER_inst0_O),
.RESET(and_inst0_out)
);
LUT4_2048 LUT4_2048_inst0 (
... | 7.712729 |
module Counter4_Mod11CE (
input CE,
input clk,
output [3:0] O
);
wire [3:0] Counter4CER_inst0_O;
wire LUT4_1024_inst0_O;
wire and_inst0_out;
Counter4CER Counter4CER_inst0 (
.CE(CE),
.clk(clk),
.O(Counter4CER_inst0_O),
.RESET(and_inst0_out)
);
LUT4_1024 LUT4_1024_inst0 (
... | 7.712729 |
module Counter2_Mod4CE (
input CE,
input clk,
output [1:0] O
);
wire [1:0] Counter2CER_inst0_O;
wire LUT2_8_inst0_O;
wire and_inst0_out;
Counter2CER Counter2CER_inst0 (
.CE(CE),
.clk(clk),
.O(Counter2CER_inst0_O),
.RESET(and_inst0_out)
);
LUT2_8 LUT2_8_inst0 (
.I0(C... | 6.745207 |
module Counter2_Mod3CE_COUT (
input CE,
input clk,
output COUT,
output [1:0] O
);
wire [1:0] Counter2CER_inst0_O;
wire LUT2_4_inst0_O;
wire and_inst0_out;
Counter2CER Counter2CER_inst0 (
.CE(CE),
.clk(clk),
.O(Counter2CER_inst0_O),
.RESET(and_inst0_out)
);
LUT2_4 LUT2... | 6.566833 |
module Counter2_Mod3CE (
input CE,
input clk,
output [1:0] O
);
wire [1:0] Counter2CER_inst0_O;
wire LUT2_4_inst0_O;
wire and_inst0_out;
Counter2CER Counter2CER_inst0 (
.CE(CE),
.clk(clk),
.O(Counter2CER_inst0_O),
.RESET(and_inst0_out)
);
LUT2_4 LUT2_4_inst0 (
.I0(C... | 6.566833 |
module Map_T_n16_i0_unq5 (
input clk,
input [7:0] I_0,
input [7:0] I_1,
input [7:0] I_2,
output [7:0] O,
output valid_down,
input valid_up
);
wire [7:0] serialize_tTSeq_3_0_Int__n3_i0_hasRESETFalse_inst0_O;
wire serialize_tTSeq_3_0_Int__n3_i0_hasRESETFalse_inst0_valid_down;
serialize_t... | 7.059711 |
module Map_T_n16_i0_unq2 (
input clk,
input [7:0] I_0,
input [7:0] I_1,
input [7:0] I_2,
output [7:0] O,
output valid_down,
input valid_up
);
wire [7:0] Map_T_n1_i2_inst0_O;
wire Map_T_n1_i2_inst0_valid_down;
Map_T_n1_i2_unq4 Map_T_n1_i2_inst0 (
.clk(clk),
.I_0(I_0),
... | 7.059711 |
module Add_Atom_unq1 (
input [7:0] I__0,
input [7:0] I__1,
output [7:0] O,
output valid_down,
input valid_up
);
wire [7:0] coreir_add8_inst0_out;
coreir_add #(
.width(8)
) coreir_add8_inst0 (
.in0(I__0),
.in1(I__1),
.out(coreir_add8_inst0_out)
);
assign O = coreir_a... | 6.880887 |
module Add_Atom (
input [7:0] I__0,
input [7:0] I__1,
output [7:0] O
);
wire [7:0] coreir_add8_inst0_out;
coreir_add #(
.width(8)
) coreir_add8_inst0 (
.in0(I__0),
.in1(I__1),
.out(coreir_add8_inst0_out)
);
assign O = coreir_add8_inst0_out;
endmodule
| 6.918465 |
module renamedForReduce (
input [7:0] in0,
input [7:0] in1,
output [7:0] out
);
wire [7:0] Add_Atom_inst0_O;
Add_Atom Add_Atom_inst0 (
.I__0(in0),
.I__1(in1),
.O(Add_Atom_inst0_O)
);
assign out = Add_Atom_inst0_O;
endmodule
| 7.384035 |
module Map_T_n3_i0_unq4 (
input clk,
input [7:0] I,
output [7:0] O,
output valid_down,
input valid_up
);
wire [7:0] Reduce_T_n3_i0_inst0_O;
wire Reduce_T_n3_i0_inst0_valid_down;
Reduce_T_n3_i0 Reduce_T_n3_i0_inst0 (
.clk(clk),
.I(I),
.O(Reduce_T_n3_i0_inst0_O),
.valid_d... | 6.890969 |
module renamedForReduce_unq1 (
input clk,
input [7:0] in0,
input [7:0] in1,
output [7:0] out
);
wire [7:0] Map_T_n1_i2_inst0_O;
Map_T_n1_i2_unq7 Map_T_n1_i2_inst0 (
.clk(clk),
.I__0(in0),
.I__1(in1),
.O(Map_T_n1_i2_inst0_O)
);
assign out = Map_T_n1_i2_inst0_O;
endmodule
| 7.384035 |
module Map_T_n16_i0_unq6 (
input clk,
input [7:0] I,
output [7:0] O,
output valid_down,
input valid_up
);
wire [7:0] Module_0_inst0_O;
wire Module_0_inst0_valid_down;
Module_0 Module_0_inst0 (
.clk(clk),
.I(I),
.O(Module_0_inst0_O),
.valid_down(Module_0_inst0_valid_down... | 7.059711 |
module Add8_cin (
input CIN,
input [7:0] I0,
input [7:0] I1,
output [7:0] O
);
wire bit_const_0_None_out;
wire [7:0] coreir_add8_inst0_out;
wire [7:0] coreir_add8_inst1_out;
corebit_const #(.value(0)) bit_const_0_None (.out(bit_const_0_None_out));
coreir_add #(
.width(8)
) coreir_add8_... | 8.416699 |
module Sub_Atom (
input [7:0] I__0,
input [7:0] I__1,
output [7:0] O,
output valid_down,
input valid_up
);
wire [7:0] Sub8_inst0_O;
Sub8 Sub8_inst0 (
.I0(I__0),
.I1(I__1),
.O (Sub8_inst0_O)
);
assign O = Sub8_inst0_O;
assign valid_down = valid_up;
endmodule
| 6.934876 |
module Map_T_n16_i0_unq7 (
input clk,
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output valid_down,
input valid_up
);
wire [7:0] Map_T_n1_i2_inst0_O;
wire Map_T_n1_i2_inst0_valid_down;
Map_T_n1_i2_unq13 Map_T_n1_i2_inst0 (
.clk(clk),
.I0(I0),
.I1(I1),
.O(Map_T_... | 7.059711 |
module Sharpen (
input clk,
input [7:0] I,
output [7:0] O
);
top t (
.clk(clk),
.valid_up(1'd1),
.I(I),
.O(O),
.valid_down()
);
endmodule
| 7.189878 |
module stupleToSSeq_tInt_n3 (
input [7:0] I_0,
input [7:0] I_1,
input [7:0] I_2,
output [7:0] O_0,
output [7:0] O_1,
output [7:0] O_2,
output valid_down,
input valid_up
);
assign O_0 = I_0;
assign O_1 = I_1;
assign O_2 = I_2;
assign valid_down = valid_up;
endmodule
| 6.674959 |
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