code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module: shadow_chain
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module shadow_chain_tb;
localparam SIZE = 8;
// Inputs
reg clk;
reg rst;
reg c_en;
reg d_en;
reg d_clk;
reg [S... | 7.117072 |
module HazardDetection (
input [31:0] io_IF_ID_INST,
input io_ID_EX_MEMREAD,
input [ 4:0] io_ID_EX_REGRD,
input [31:0] io_pc_in,
input [31:0] io_current_pc,
input io_IF_ID_MEMREAD,
output io_inst_forward,
output io_pc_forward,
output io_ctrl_f... | 6.580064 |
module BranchLogic (
input [31:0] io_in_rs1,
input [31:0] io_in_rs2,
input [ 2:0] io_in_func3,
output io_output
);
wire _T = io_in_func3 == 3'h0; // @[BranchLogic.scala 13:20]
wire _T_1 = $signed(io_in_rs1) == $signed(io_in_rs2); // @[BranchLogic.scala 15:20]
wire _T_2 = io_in_func3 ==... | 7.33371 |
module StructuralDetector (
input [4:0] io_rs1_sel,
input [4:0] io_rs2_sel,
input io_MEM_WB_regWr,
input [4:0] io_MEM_WB_REGRD,
input [6:0] io_inst_op_in,
output io_fwd_rs1,
output io_fwd_rs2
);
wire _T_1 = io_MEM_WB_REGRD != 5'h0; // @[StructuralDetector.scala 27:5... | 7.019211 |
module BrqCounter (
input clock,
input reset,
input io_i_counter_inc,
input io_i_counterh_we,
input io_i_counter_we,
input [31:0] io_i_counter_val,
output [63:0] io_o_counter_val
);
`ifdef RANDOMIZE_REG_INIT
reg [63:0] _RAND_0;
`endif // RANDOMIZE_... | 6.53532 |
module ForwardUnit (
input [4:0] io_EX_MEM_REGRD,
input [4:0] io_MEM_WB_REGRD,
input [4:0] io_ID_EX_REGRS1,
input [4:0] io_ID_EX_REGRS2,
input [6:0] io_ID_EX_inst_op,
input io_EX_MEM_REGWR,
input io_MEM_WB_REGWR,
output [1:0] io_forward_a,
output [1:0] io_forward_b... | 6.879476 |
module WriteBack (
input io_MEM_WB_MemToReg,
input [31:0] io_MEM_WB_dataMem_data,
input [31:0] io_MEM_WB_alu_output,
output [31:0] io_write_data
);
assign io_write_data = io_MEM_WB_MemToReg ? $signed(
io_MEM_WB_dataMem_data
) : $signed(
io_MEM_WB_alu_output
);... | 7.550605 |
module TL_Err (
input io_tl_i_a_valid,
input [ 2:0] io_tl_i_a_opcode,
input [31:0] io_tl_i_a_address,
input [ 3:0] io_tl_i_a_mask,
output io_err_o
);
wire op_get = io_tl_i_a_opcode == 3'h4; // @[TL_Err.scala 19:30]
wire op_partial = io_tl_i_a_opcode == 3'h1; // @[TL_Err.scala... | 7.81729 |
module SubRegExt (
input io_we,
input [31:0] io_wd,
input [31:0] io_d,
output io_qe,
output [31:0] io_q,
output [31:0] io_qs
);
assign io_qe = io_we; // @[SubRegExt.scala 24:9]
assign io_q = io_wd; // @[SubRegExt.scala 23:8]
assign io_qs = io_d; // @[SubRegExt.scala 22... | 6.577328 |
module SubRegExt_2 (
input io_we,
input [15:0] io_wd,
input [15:0] io_d,
output io_qe,
output [15:0] io_q,
output [15:0] io_qs
);
assign io_qe = io_we; // @[SubRegExt.scala 24:9]
assign io_q = io_wd; // @[SubRegExt.scala 23:8]
assign io_qs = io_d; // @[SubRegExt.scala ... | 6.705049 |
module TL_HostAdapter (
input io_req_i,
output io_gnt_o,
input [31:0] io_addr_i,
input io_we_i,
input [31:0] io_wdata_i,
input [ 3:0] io_be_i,
output io_valid_o,
output [31:0] io_rdata_o,
output io_tl_o_a_valid,
output [ 2:0] io_tl_o_a_opco... | 7.225329 |
module TL_SramAdapter (
input clock,
input reset,
input io_tl_i_a_valid,
input [ 2:0] io_tl_i_a_opcode,
input [31:0] io_tl_i_a_address,
input [ 3:0] io_tl_i_a_mask,
output io_tl_o_d_valid,
output [31:0] io_tl_o_d_data,
output io_tl_o_a_ready,
... | 6.920884 |
module TL_ErrResp (
input clock,
input reset,
input io_tl_h_i_a_valid,
output io_tl_d_o_d_valid,
output io_tl_d_o_a_ready
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg err_reqPending; // @[TL_ErrResp.scala 15:31]
wire _T = io_tl_h_i_a_valid & io_tl_d_o... | 7.340048 |
module sram_1rw1r_32_256_8_sky130 (
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
addr0,
din0,
dout0
);
parameter NUM_WMASKS = 4;
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 8;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 0;
... | 6.906604 |
module ShamtSignExtend32b (
instruction,
signExtended
);
input wire [31:0] instruction;
output wire [31:0] signExtended;
assign signExtended = {{27{instruction[24]}}, instruction[24:20]};
endmodule
| 7.43101 |
module shamt_extend (
input wire [ 4:0] i_input,
output wire [31:0] o_output
);
assign o_output = {27'b0, i_input};
endmodule
| 6.523774 |
module shape_fir (
clk,
reset_n,
ast_sink_data,
ast_sink_valid,
ast_source_ready,
ast_sink_error,
ast_source_data,
ast_sink_ready,
ast_source_valid,
ast_source_error
);
input clk;
input reset_n;
input [1:0] ast_sink_data;
input ast_sink_valid;
input ast_source_ready;
... | 6.908048 |
module sharedMem32 (
clk,
mem_read,
mem_write,
address,
data_in,
data_out,
sharedAccess,
finalResult,
fR1,
fR2,
fR3,
fR4
);
input clk, mem_read, mem_write;
input [31:0] address, data_in;
output [31:0] data_out;
output [31:0] finalResult, fR1, fR2, fR3, fR4;
reg ... | 8.180389 |
module sharedMemArbiter (
addr1,
data1,
rd1,
wd1,
sbit1,
addr2,
data2,
rd2,
wd2,
sbit2,
addr3,
data3,
rd3,
wd3,
sbit3,
addr4,
data4,
rd4,
wd4,
sbit4,
addr,
data,
rd,
wd,
sharedAccess
);
input [31:0] addr1;
input [31... | 9.080906 |
module shared_ram #(
parameter ADDR_WIDTH = 6
) (
input clk,
input resetn,
// ARM HPS port
input [ 31:0] data_a,
input [(ADDR_WIDTH-1):0] addr_a,
input [ 3:0] we_a,
output [ 31:0] q_a,
... | 8.275451 |
module share_router ( /*AUTOARG*/
// Outputs
tbcstate,
stateout,
tbckey,
keyout,
keycorrect,
// Inputs
statein,
nextstate,
keyin,
nextkey,
pcorrectkey
);
`include "romulus_config_pkg.v"
output [128*STATESHARES-1:0] tbcstate;
output [128*STATESHARES-1:0] stateout;
... | 8.341371 |
module heart_rom #(
parameter WIDTH = 40,
parameter HEIGHT = 40,
LG_SCALE = 2,
parameter LOG_FRAMES = 1
) (
input [10:0] x,
input [9:0] y,
input [2:0] s_type,
input [LOG_FRAMES-1:0] frame,
output reg [11:0] pixel
);
reg [(WIDTH>>LG_SCALE)*12-1:0] horiz; //a horizontal strip of pi... | 8.323995 |
module sseqTupleAppender_tTSeq_3_0_Int__n2 (
input [7:0] I0_0,
input [7:0] I0_1,
input [7:0] I1,
output [7:0] O_0,
output [7:0] O_1,
output [7:0] O_2,
output valid_down,
input valid_up
);
assign O_0 = I0_0;
assign O_1 = I0_1;
assign O_2 = I1;
assign valid_down = valid_up;
endmodu... | 7.061223 |
module sseqTupleAppender_tInt_n2 (
input [7:0] I0_0,
input [7:0] I0_1,
input [7:0] I1,
output [7:0] O_0,
output [7:0] O_1,
output [7:0] O_2,
output valid_down,
input valid_up
);
assign O_0 = I0_0;
assign O_1 = I0_1;
assign O_2 = I1;
assign valid_down = valid_up;
endmodule
| 7.061223 |
module corebit_xor (
input in0,
input in1,
output out
);
assign out = in0 ^ in1;
endmodule
| 7.624638 |
module corebit_not (
input in,
output out
);
assign out = ~in;
endmodule
| 8.318293 |
module corebit_eq (
input I0,
input I1,
output O
);
wire not_inst0_out;
wire xor_inst0_out;
corebit_not not_inst0 (
.in (xor_inst0_out),
.out(not_inst0_out)
);
corebit_xor xor_inst0 (
.in0(I0),
.in1(I1),
.out(xor_inst0_out)
);
assign O = not_inst0_out;
endmodule... | 7.456911 |
module corebit_const #(
parameter value = 1
) (
output out
);
assign out = value;
endmodule
| 7.833235 |
module corebit_and (
input in0,
input in1,
output out
);
assign out = in0 & in1;
endmodule
| 8.125026 |
module coreir_ult #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 < in1;
endmodule
| 7.861561 |
module coreir_ugt #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 > in1;
endmodule
| 7.36211 |
module coreir_term #(
parameter width = 1
) (
input [width-1:0] in
);
endmodule
| 6.849594 |
module coreir_slice #(
parameter hi = 1,
parameter lo = 0,
parameter width = 1
) (
input [width-1:0] in,
output [hi-lo-1:0] out
);
assign out = in[hi-1:lo];
endmodule
| 8.799926 |
module coreir_shl #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 << in1;
endmodule
| 8.595943 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_not #(
parameter width = 1
) (
input [width-1:0] in,
output [width-1:0] out
);
assign out = ~in;
endmodule
| 8.534147 |
module coreir_neg #(
parameter width = 1
) (
input [width-1:0] in,
output [width-1:0] out
);
assign out = -in;
endmodule
| 7.306788 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module coreir_mem #(
parameter has_init = 0,
parameter depth = 1,
parameter width = 1
) (
input clk,
input [width-1:0] wdata,
input [$clog2(depth)-1:0] waddr,
input wen,
output [width-1:0] rdata,
input [$clog2(depth)-1:0] raddr
);
reg [width-1:0] data[depth-1:0];
always @(posedge... | 7.482949 |
module coreir_lshr #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 >> in1;
endmodule
| 8.306547 |
module coreir_eq #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 == in1;
endmodule
| 7.939296 |
module coreir_const #(
parameter width = 1,
parameter value = 1
) (
output [width-1:0] out
);
assign out = value;
endmodule
| 8.127638 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module \commonlib_muxn__N2__width8 (
input [7:0] in_data_0,
input [7:0] in_data_1,
input [0:0] in_sel,
output [7:0] out
);
wire [7:0] _join_out;
coreir_mux #(
.width(8)
) _join (
.in0(in_data_0),
.in1(in_data_1),
.out(_join_out),
.sel(in_sel[0])
);
assign out =... | 7.889703 |
module \commonlib_muxn__N4__width8 (
input [7:0] in_data_0,
input [7:0] in_data_1,
input [7:0] in_data_2,
input [7:0] in_data_3,
input [1:0] in_sel,
output [7:0] out
);
wire [7:0] _join_out;
wire [7:0] muxN_0_out;
wire [7:0] muxN_1_out;
wire [0:0] sel_slice0_out;
wire [0:0] sel_sl... | 7.889703 |
module \commonlib_muxn__N2__width4 (
input [3:0] in_data_0,
input [3:0] in_data_1,
input [0:0] in_sel,
output [3:0] out
);
wire [3:0] _join_out;
coreir_mux #(
.width(4)
) _join (
.in0(in_data_0),
.in1(in_data_1),
.out(_join_out),
.sel(in_sel[0])
);
assign out =... | 7.889703 |
module \commonlib_muxn__N2__width3 (
input [2:0] in_data_0,
input [2:0] in_data_1,
input [0:0] in_sel,
output [2:0] out
);
wire [2:0] _join_out;
coreir_mux #(
.width(3)
) _join (
.in0(in_data_0),
.in1(in_data_1),
.out(_join_out),
.sel(in_sel[0])
);
assign out =... | 7.889703 |
module \commonlib_muxn__N2__width2 (
input [1:0] in_data_0,
input [1:0] in_data_1,
input [0:0] in_sel,
output [1:0] out
);
wire [1:0] _join_out;
coreir_mux #(
.width(2)
) _join (
.in0(in_data_0),
.in1(in_data_1),
.out(_join_out),
.sel(in_sel[0])
);
assign out =... | 7.889703 |
module \commonlib_muxn__N2__width1 (
input [0:0] in_data_0,
input [0:0] in_data_1,
input [0:0] in_sel,
output [0:0] out
);
wire [0:0] _join_out;
coreir_mux #(
.width(1)
) _join (
.in0(in_data_0),
.in1(in_data_1),
.out(_join_out),
.sel(in_sel[0])
);
assign out =... | 7.889703 |
module \commonlib_muxn__N1__width8 (
input [7:0] in_data_0,
input [0:0] in_sel,
output [7:0] out
);
corebit_term term_sel (.in(in_sel[0]));
assign out = in_data_0;
endmodule
| 7.889703 |
module \commonlib_muxn__N3__width8 (
input [7:0] in_data_0,
input [7:0] in_data_1,
input [7:0] in_data_2,
input [1:0] in_sel,
output [7:0] out
);
wire [7:0] _join_out;
wire [7:0] muxN_0_out;
wire [7:0] muxN_1_out;
wire [0:0] sel_slice0_out;
wire [0:0] sel_slice1_out;
coreir_mux #(
... | 7.889703 |
module lutN #(
parameter N = 1,
parameter init = 1
) (
input [N-1:0] in,
output out
);
assign out = init[in];
endmodule
| 7.756611 |
module RShift_Atom (
input [7:0] I__0,
input [7:0] I__1,
output [7:0] O,
output valid_down,
input valid_up
);
wire [7:0] lshr8_inst0_out;
coreir_lshr #(
.width(8)
) lshr8_inst0 (
.in0(I__0),
.in1(I__1),
.out(lshr8_inst0_out)
);
assign O = lshr8_inst0_out;
assign v... | 7.73328 |
module RAM5x8 (
input clk,
input [2:0] RADDR,
output [7:0] RDATA,
input [2:0] WADDR,
input [7:0] WDATA,
input WE
);
wire [7:0] coreir_mem5x8_inst0_rdata;
coreir_mem #(
.depth(5),
.has_init(0),
.width(8)
) coreir_mem5x8_inst0 (
.clk (clk),
.raddr(RADDR),
... | 6.633404 |
module Negate8 (
input [7:0] I,
output [7:0] O
);
wire [7:0] coreir_neg_inst0_out;
coreir_neg #(
.width(8)
) coreir_neg_inst0 (
.in (I),
.out(coreir_neg_inst0_out)
);
assign O = coreir_neg_inst0_out;
endmodule
| 7.306678 |
module NativeMapParallel_n4 (
input [7:0] I_0,
input [7:0] I_1,
input [7:0] I_2,
input [7:0] I_3,
output [7:0] out_0,
output [7:0] out_1,
output [7:0] out_2,
output [7:0] out_3
);
wire [7:0] dehydrate_tArray_8_Bit__inst0_out;
wire [7:0] dehydrate_tArray_8_Bit__inst1_out;
wire [... | 7.274395 |
module NativeMapParallel_n3 (
input [7:0] I_0,
input [7:0] I_1,
input [7:0] I_2,
output [7:0] out_0,
output [7:0] out_1,
output [7:0] out_2
);
wire [7:0] dehydrate_tArray_8_Bit__inst0_out;
wire [7:0] dehydrate_tArray_8_Bit__inst1_out;
wire [7:0] dehydrate_tArray_8_Bit__inst2_out;
\aet... | 7.274395 |
module NativeMapParallel_n2_unq1 (
input [7:0] I_0,
input [7:0] I_1,
output [7:0] out_0,
output [7:0] out_1
);
wire [7:0] dehydrate_tArray_8_Out_Bit___inst0_out;
wire [7:0] dehydrate_tArray_8_Out_Bit___inst1_out;
\aetherlinglib_dehydrate__hydratedTypeBit8 dehydrate_tArray_8_Out_Bit___inst0 (
... | 7.274395 |
module NativeMapParallel_n2 (
input [7:0] I_0,
input [7:0] I_1,
output [7:0] out_0,
output [7:0] out_1
);
wire [7:0] dehydrate_tArray_8_Bit__inst0_out;
wire [7:0] dehydrate_tArray_8_Bit__inst1_out;
\aetherlinglib_dehydrate__hydratedTypeBit8 dehydrate_tArray_8_Bit__inst0 (
.in (I_0),
... | 7.274395 |
module NativeMapParallel_n1_unq2 (
input [7:0] I0_0_0,
input [7:0] I0_0_1,
input [7:0] I1_0,
output [7:0] O_0_0,
output [7:0] O_0_1,
output [7:0] O_0_2,
output valid_down,
input valid_up
);
wire [7:0] sseqTupleAppender_tTSeq_3_0_Int__n2_inst0_O_0;
wire [7:0] sseqTupleAppender_tTSeq_3... | 7.274395 |
module NativeMapParallel_n1_unq1 (
input [7:0] I0_0,
input [7:0] I1_0,
output [7:0] O_0_0,
output [7:0] O_0_1,
output valid_down,
input valid_up
);
wire [7:0] sseqTupleCreator_tTSeq_3_0_Int__inst0_O_0;
wire [7:0] sseqTupleCreator_tTSeq_3_0_Int__inst0_O_1;
wire sseqTupleCreator_tTSeq_3_0_In... | 7.274395 |
module Mux_Array_8_Out_Bit__t_2n (
input [7:0] data_0,
input [7:0] data_1,
output [7:0] out,
input [0:0] sel
);
wire [7:0] CommonlibMuxN_n2_w8_inst0_out;
wire [7:0] NativeMapParallel_n2_inst0_out_0;
wire [7:0] NativeMapParallel_n2_inst0_out_1;
wire [7:0] hydrate_tArray_8_Out_Bit___inst0_out;
... | 7.461788 |
module Mux_Array_8_Bit_t_4n (
input [7:0] data_0,
input [7:0] data_1,
input [7:0] data_2,
input [7:0] data_3,
output [7:0] out,
input [1:0] sel
);
wire [7:0] CommonlibMuxN_n4_w8_inst0_out;
wire [7:0] NativeMapParallel_n4_inst0_out_0;
wire [7:0] NativeMapParallel_n4_inst0_out_1;
wire... | 7.171087 |
module Mux_Array_8_Bit_t_3n (
input [7:0] data_0,
input [7:0] data_1,
input [7:0] data_2,
output [7:0] out,
input [1:0] sel
);
wire [7:0] CommonlibMuxN_n3_w8_inst0_out;
wire [7:0] NativeMapParallel_n3_inst0_out_0;
wire [7:0] NativeMapParallel_n3_inst0_out_1;
wire [7:0] NativeMapParallel_... | 7.171087 |
module Mux_Array_8_Bit_t_2n (
input [7:0] data_0,
input [7:0] data_1,
output [7:0] out,
input [0:0] sel
);
wire [7:0] CommonlibMuxN_n2_w8_inst0_out;
wire [7:0] NativeMapParallel_n2_inst0_out_0;
wire [7:0] NativeMapParallel_n2_inst0_out_1;
wire [7:0] hydrate_tArray_8_Bit__inst0_out;
\commonl... | 7.171087 |
module Mux_Array_8_Bit_t_1n (
input [7:0] data_0,
output [7:0] out,
input [0:0] sel
);
Term_Bits_1_t Term_Bits_1_t_inst0 (.I(sel));
assign out = data_0;
endmodule
| 7.171087 |
module Mux2xOutBits4 (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
input S
);
wire [3:0] coreir_commonlib_mux2x4_inst0_out;
\commonlib_muxn__N2__width4 coreir_commonlib_mux2x4_inst0 (
.in_data_0(I0),
.in_data_1(I1),
.in_sel(S),
.out(coreir_commonlib_mux2x4_inst0_out)
);... | 8.005808 |
module Mux2xOutBits3 (
input [2:0] I0,
input [2:0] I1,
output [2:0] O,
input S
);
wire [2:0] coreir_commonlib_mux2x3_inst0_out;
\commonlib_muxn__N2__width3 coreir_commonlib_mux2x3_inst0 (
.in_data_0(I0),
.in_data_1(I1),
.in_sel(S),
.out(coreir_commonlib_mux2x3_inst0_out)
);... | 7.210649 |
module Mux2xOutBits2 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
input S
);
wire [1:0] coreir_commonlib_mux2x2_inst0_out;
\commonlib_muxn__N2__width2 coreir_commonlib_mux2x2_inst0 (
.in_data_0(I0),
.in_data_1(I1),
.in_sel(S),
.out(coreir_commonlib_mux2x2_inst0_out)
);... | 7.816223 |
module Mux2xOutBits1 (
input [0:0] I0,
input [0:0] I1,
output [0:0] O,
input S
);
wire [0:0] coreir_commonlib_mux2x1_inst0_out;
\commonlib_muxn__N2__width1 coreir_commonlib_mux2x1_inst0 (
.in_data_0(I0),
.in_data_1(I1),
.in_sel(S),
.out(coreir_commonlib_mux2x1_inst0_out)
);... | 7.639545 |
module Mux2xNone (
input I0,
input I1,
output O,
input S
);
wire [0:0] coreir_commonlib_mux2x1_inst0_out;
\commonlib_muxn__N2__width1 coreir_commonlib_mux2x1_inst0 (
.in_data_0(I0),
.in_data_1(I1),
.in_sel(S),
.out(coreir_commonlib_mux2x1_inst0_out)
);
assign O = corei... | 8.404032 |
module NativeMapParallel_n3_unq1 (
input clk,
input [7:0] I0_0,
input [7:0] I0_1,
input [7:0] I0_2,
input [7:0] I1_0,
input [7:0] I1_1,
input [7:0] I1_2,
output [7:0] O_0__0,
output [7:0] O_0__1,
output [7:0] O_1__0,
output [7:0] O_1__1,
output [7:0] O_2__0,
output [7... | 7.274395 |
module Map_T_n1_i2 (
input clk,
input [7:0] I0,
input [7:0] I1,
output [7:0] O_0,
output [7:0] O_1,
output valid_down,
input valid_up
);
wire [7:0] sseqTupleCreator_tInt_inst0_O_0;
wire [7:0] sseqTupleCreator_tInt_inst0_O_1;
wire sseqTupleCreator_tInt_inst0_valid_down;
sseqTupleCreat... | 7.299216 |
module Map_T_n1_i0_unq5 (
input clk,
input [7:0] I__0,
input [7:0] I__1,
output [7:0] O,
output valid_down,
input valid_up
);
wire [7:0] Map_T_n1_i2_inst0_O;
wire Map_T_n1_i2_inst0_valid_down;
Map_T_n1_i2_unq4 Map_T_n1_i2_inst0 (
.clk(clk),
.I__0(I__0),
.I__1(I__1),
... | 7.00322 |
module Map_T_n1_i0_unq4 (
input clk,
input [7:0] I0,
input [7:0] I1,
output [7:0] O__0,
output [7:0] O__1,
output valid_down,
input valid_up
);
wire [7:0] Map_T_n1_i2_inst0_O__0;
wire [7:0] Map_T_n1_i2_inst0_O__1;
wire Map_T_n1_i2_inst0_valid_down;
Map_T_n1_i2_unq3 Map_T_n1_i2_inst0 ... | 7.00322 |
module Map_T_n1_i0 (
input clk,
input [7:0] I0_0,
input [7:0] I0_1,
input [7:0] I0_2,
input [7:0] I1_0,
input [7:0] I1_1,
input [7:0] I1_2,
output [7:0] O_0__0,
output [7:0] O_0__1,
output [7:0] O_1__0,
output [7:0] O_1__1,
output [7:0] O_2__0,
output [7:0] O_2__1,
... | 7.251476 |
module Map_T_n16_i0_unq5 (
input clk,
input [7:0] I_0_0,
input [7:0] I_0_1,
input [7:0] I_0_2,
output [7:0] O_0,
output [7:0] O_1,
output [7:0] O_2,
output valid_down,
input valid_up
);
wire [7:0] Passthrough_tInTSeq_1_0_SSeq_1_STuple_3_TSeq_3_0_Int_____tOutTSeq_1_0_SSeq_3_TSeq_3_0... | 7.059711 |
module Map_T_n16_i0_unq4 (
input clk,
input [7:0] I0_0_0,
input [7:0] I0_0_1,
input [7:0] I1_0,
output [7:0] O_0_0,
output [7:0] O_0_1,
output [7:0] O_0_2,
output valid_down,
input valid_up
);
wire [7:0] NativeMapParallel_n1_inst0_O_0_0;
wire [7:0] NativeMapParallel_n1_inst0_O_0_... | 7.059711 |
module Map_T_n16_i0_unq3 (
input clk,
input [7:0] I0_0,
input [7:0] I1_0,
output [7:0] O_0_0,
output [7:0] O_0_1,
output valid_down,
input valid_up
);
wire [7:0] NativeMapParallel_n1_inst0_O_0_0;
wire [7:0] NativeMapParallel_n1_inst0_O_0_1;
wire NativeMapParallel_n1_inst0_valid_down;
... | 7.059711 |
module Map_T_n16_i0_unq1 (
input clk,
input [7:0] I0_0,
input [7:0] I0_1,
input [7:0] I1,
output [7:0] O_0,
output [7:0] O_1,
output [7:0] O_2,
output valid_down,
input valid_up
);
wire [7:0] Map_T_n1_i2_inst0_O_0;
wire [7:0] Map_T_n1_i2_inst0_O_1;
wire [7:0] Map_T_n1_i2_inst0_... | 7.059711 |
module Map_T_n16_i0 (
input clk,
input [7:0] I0,
input [7:0] I1,
output [7:0] O_0,
output [7:0] O_1,
output valid_down,
input valid_up
);
wire [7:0] Map_T_n1_i2_inst0_O_0;
wire [7:0] Map_T_n1_i2_inst0_O_1;
wire Map_T_n1_i2_inst0_valid_down;
Map_T_n1_i2 Map_T_n1_i2_inst0 (
.clk(... | 7.587533 |
module Lt_Atom (
input [7:0] I__0,
input [7:0] I__1,
output [0:0] O,
output valid_down,
input valid_up
);
wire coreir_ult8_inst0_out;
coreir_ult #(
.width(8)
) coreir_ult8_inst0 (
.in0(I__0),
.in1(I__1),
.out(coreir_ult8_inst0_out)
);
assign O = coreir_ult8_inst0_ou... | 7.118379 |
module LUT4_256 (
input I0,
input I1,
input I2,
input I3,
output O
);
wire coreir_lut4_inst0_out;
lutN #(
.init(16'h0100),
.N(4)
) coreir_lut4_inst0 (
.in ({I3, I2, I1, I0}),
.out(coreir_lut4_inst0_out)
);
assign O = coreir_lut4_inst0_out;
endmodule
| 7.445537 |
module LUT3_32 (
input I0,
input I1,
input I2,
output O
);
wire coreir_lut3_inst0_out;
lutN #(
.init(8'h20),
.N(3)
) coreir_lut3_inst0 (
.in ({I2, I1, I0}),
.out(coreir_lut3_inst0_out)
);
assign O = coreir_lut3_inst0_out;
endmodule
| 6.945181 |
module LUT3_16 (
input I0,
input I1,
input I2,
output O
);
wire coreir_lut3_inst0_out;
lutN #(
.init(8'h10),
.N(3)
) coreir_lut3_inst0 (
.in ({I2, I1, I0}),
.out(coreir_lut3_inst0_out)
);
assign O = coreir_lut3_inst0_out;
endmodule
| 7.554919 |
module LUT3_128 (
input I0,
input I1,
input I2,
output O
);
wire coreir_lut3_inst0_out;
lutN #(
.init(8'h80),
.N(3)
) coreir_lut3_inst0 (
.in ({I2, I1, I0}),
.out(coreir_lut3_inst0_out)
);
assign O = coreir_lut3_inst0_out;
endmodule
| 7.565933 |
module LUT2_8 (
input I0,
input I1,
output O
);
wire coreir_lut2_inst0_out;
lutN #(
.init(4'h8),
.N(2)
) coreir_lut2_inst0 (
.in ({I1, I0}),
.out(coreir_lut2_inst0_out)
);
assign O = coreir_lut2_inst0_out;
endmodule
| 7.722694 |
module LUT2_5 (
input I0,
input I1,
output O
);
wire coreir_lut2_inst0_out;
lutN #(
.init(4'h5),
.N(2)
) coreir_lut2_inst0 (
.in ({I1, I0}),
.out(coreir_lut2_inst0_out)
);
assign O = coreir_lut2_inst0_out;
endmodule
| 7.856271 |
module LUT2_4 (
input I0,
input I1,
output O
);
wire coreir_lut2_inst0_out;
lutN #(
.init(4'h4),
.N(2)
) coreir_lut2_inst0 (
.in ({I1, I0}),
.out(coreir_lut2_inst0_out)
);
assign O = coreir_lut2_inst0_out;
endmodule
| 7.674267 |
module LUT2_2 (
input I0,
input I1,
output O
);
wire coreir_lut2_inst0_out;
lutN #(
.init(4'h2),
.N(2)
) coreir_lut2_inst0 (
.in ({I1, I0}),
.out(coreir_lut2_inst0_out)
);
assign O = coreir_lut2_inst0_out;
endmodule
| 7.802919 |
module LUT2_1 (
input I0,
input I1,
output O
);
wire coreir_lut2_inst0_out;
lutN #(
.init(4'h1),
.N(2)
) coreir_lut2_inst0 (
.in ({I1, I0}),
.out(coreir_lut2_inst0_out)
);
assign O = coreir_lut2_inst0_out;
endmodule
| 7.464635 |
module LUT2_0 (
input I0,
input I1,
output O
);
wire coreir_lut2_inst0_out;
lutN #(
.init(4'h0),
.N(2)
) coreir_lut2_inst0 (
.in ({I1, I0}),
.out(coreir_lut2_inst0_out)
);
assign O = coreir_lut2_inst0_out;
endmodule
| 8.018457 |
module LUT1_2 (
input I0,
output O
);
wire coreir_lut1_inst0_out;
lutN #(
.init(2'h2),
.N(1)
) coreir_lut1_inst0 (
.in (I0),
.out(coreir_lut1_inst0_out)
);
assign O = coreir_lut1_inst0_out;
endmodule
| 8.126826 |
module LUT1_1 (
input I0,
output O
);
wire coreir_lut1_inst0_out;
lutN #(
.init(2'h1),
.N(1)
) coreir_lut1_inst0 (
.in (I0),
.out(coreir_lut1_inst0_out)
);
assign O = coreir_lut1_inst0_out;
endmodule
| 7.409016 |
module LUT1_0 (
input I0,
output O
);
wire coreir_lut1_inst0_out;
lutN #(
.init(2'h0),
.N(1)
) coreir_lut1_inst0 (
.in (I0),
.out(coreir_lut1_inst0_out)
);
assign O = coreir_lut1_inst0_out;
endmodule
| 7.399772 |
module LShift_Atom (
input [7:0] I__0,
input [7:0] I__1,
output [7:0] O,
output valid_down,
input valid_up
);
wire [7:0] shl8_inst0_out;
coreir_shl #(
.width(8)
) shl8_inst0 (
.in0(I__0),
.in1(I__1),
.out(shl8_inst0_out)
);
assign O = shl8_inst0_out;
assign valid_... | 8.458485 |
module Map_T_n3_i0_unq1 (
input clk,
input [7:0] I__0,
input [7:0] I__1,
output [7:0] O,
output valid_down,
input valid_up
);
wire [7:0] LShift_Atom_inst0_O;
wire LShift_Atom_inst0_valid_down;
LShift_Atom LShift_Atom_inst0 (
.I__0(I__0),
.I__1(I__1),
.O(LShift_Atom_inst0_... | 6.890969 |
module NativeMapParallel_n3_unq2 (
input clk,
input [7:0] I_0__0,
input [7:0] I_0__1,
input [7:0] I_1__0,
input [7:0] I_1__1,
input [7:0] I_2__0,
input [7:0] I_2__1,
output [7:0] O_0,
output [7:0] O_1,
output [7:0] O_2,
output valid_down,
input valid_up
);
wire [7:0] Ma... | 7.274395 |
module Map_T_n1_i0_unq1 (
input clk,
input [7:0] I_0__0,
input [7:0] I_0__1,
input [7:0] I_1__0,
input [7:0] I_1__1,
input [7:0] I_2__0,
input [7:0] I_2__1,
output [7:0] O_0,
output [7:0] O_1,
output [7:0] O_2,
output valid_down,
input valid_up
);
wire [7:0] NativeMapPa... | 7.00322 |
module If_Atom_Intt (
input [0:0] I__0,
input [7:0] I__1__0,
input [7:0] I__1__1,
output [7:0] O,
output valid_down,
input valid_up
);
wire [7:0] Mux_Array_8_Bit_t_2n_inst0_out;
Mux_Array_8_Bit_t_2n Mux_Array_8_Bit_t_2n_inst0 (
.data_0(I__1__1),
.data_1(I__1__0),
.out(Mux_A... | 7.310169 |
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