code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Reg4bit (
output wire [3:0] O,
input wire SP,
input wire Is,
input wire [3:0] Ip,
input wire C,
input wire CE,
input wire nCLR
);
wire CCE;
and (CCE, C, CE);
RS1bit r3 (
O[3],
SP,
Is,
Ip[3],
CCE,
nCLR
);
RS1bit r2 (
O[2],
SP,
O[3],
Ip[2],
CCE,
nCLR
);
RS1bit r1 (
O[1],
SP,
O[2],
Ip[1],
CCE,
nCLR
);
RS1bit r0 (
O[0],
SP,
O[1],
Ip[0],
CCE,
nCLR
);
endmodule
| 8.011379 |
module sra (
input wire s, // puesta a '1'
input wire r, // puesta a '0'
output reg q // estado (valor almacenado)
/* Las variables (tipo 'reg') son el único tipo de señal que pueden
* retener su valor y por tanto deben usarse para describir
* comportamiento secuencial (con memoria) */
);
always @(s, r)
case ({
s, r
})
/* La asignación de elementos de memoria debe realizarse
* mediante el operador de asignación no bloqueante ('<=').
* Las diferencias entre el operador '=' y el '<=' se explican
* en la lección 6-3. */
2'b01: q <= 1'b0;
2'b10: q <= 1'b1;
2'b11: q <= 1'bx;
/* El comportamiento secuencial del circuito se deriva de que
* la señal 'q' no se asigna en todos los casos. Cuando 's' y
* 'r' son ambos cero no se asigna ningún valor a 'q' por lo que
* conserva su valor anterior, modelando el comportamiento de
* un elemento de memoria. */
endcase
endmodule
| 7.412971 |
module srl (
input wire ck, // reloj
input wire s, // puesta a '1'
input wire r, // puesta a '0'
output reg q // estado
);
always @(ck, s, r)
case ({
ck, s, r
})
3'b101: q <= 1'b0;
3'b110: q <= 1'b1;
3'b111: q <= 1'bx;
endcase
endmodule
| 7.074097 |
module srms (
input wire ck,
input wire s,
input wire r,
output wire q
);
srl master (
.ck(ck),
.s (s),
.r (r),
.q (qm)
);
/* Las entradas del esclavo se conectan de forma que copien el estado
* del maestro. */
srl slave (
.ck(ck_neg),
.s (qm),
.r (qm_neg),
.q (q)
);
/* Generamos la salida complementada del maestro y la señal de reloj
* invertida para el esclavo. */
assign qm_neg = ~qm;
assign ck_neg = ~ck;
endmodule
| 7.701316 |
module RS_C (
output wire Q,
output wire NQ,
input wire R,
input wire S,
input wire C
);
wire RC, SC;
and (RC, R, C);
and (SC, C, S);
RS rs1 (
Q,
NQ,
RC,
SC
);
endmodule
| 8.080012 |
module RS_CA (
output wire Q,
output wire NQ,
input wire R,
input wire S,
input wire C
);
wire NC, DET;
not #(1) (NC, C);
and (DET, NC, C);
RS_C rs1 (
Q,
NQ,
R,
S,
DET
);
endmodule
| 8.348841 |
module T (
output reg Q,
input wire T
);
initial Q = 0;
always @(negedge T) Q = ~Q;
endmodule
| 7.299747 |
module T (
output reg Q,
output wire nQ,
input wire T,
input wire nPRESET,
input wire nCLEAR
);
initial Q = 0;
not (nQ, Q);
always @(negedge T) if (nPRESET && nCLEAR) Q = ~Q;
always @(nPRESET, nCLEAR)
case ({
nPRESET, nCLEAR
})
2'b01: Q = 1;
2'b10: Q = 0;
endcase
endmodule
| 7.299747 |
module Thold (
output wire Q,
output wire nQ,
input wire T,
input wire nPRESET,
input wire nCLEAR,
input wire nHOLD
);
wire a1s, a2s, o1s, o2s;
T t1 (
Q,
nQ,
T,
a2s,
a1s
);
or (o1s, nHOLD, Q);
or (o2s, nHOLD, nQ);
and (a1s, o1s, nCLEAR);
and (a2s, o2s, nPRESET);
endmodule
| 6.76102 |
module BigALU (
input [31:0] src1,
input [31:0] src2,
input [3:0] alu_ctrl,
output reg zero,
output reg [31:0] alu_out
);
always @* begin
case (alu_ctrl)
4'b0000: alu_out = src1 & src2;
4'b0001: alu_out = src1 | src2;
4'b0010: alu_out = src1 + src2;
4'b0110: alu_out = src1 - src2;
4'b0111: alu_out = $signed(src1) < $signed(src2) ? 32'b1 : 0;
4'b1100: alu_out = src1 ^ src2;
4'b1101: alu_out = $unsigned(src1) >> $unsigned(src2[4:0]);
4'b1110: alu_out = $unsigned(src1) << $unsigned(src2[4:0]);
4'b1111: alu_out = $signed(src1) >>> $unsigned(src2[4:0]);
4'b1000: alu_out = $signed(src1) <<< $unsigned(src2);
4'b1001: alu_out = $unsigned(src1) < $unsigned(src2) ? 32'b1 : 0;
default: alu_out = 0;
endcase
zero = src1 == src2 ? 1 : 0;
end
endmodule
| 8.436403 |
module bigCircle (
input Pi,
input Gi,
input Pprev,
input Gprev,
output P,
output G
);
wire w;
and and0 (P, Pi, Pprev);
and and1 (w, Pi, Gprev);
or or0 (G, Gi, w);
endmodule
| 7.016847 |
module bigfifo (
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
dout,
empty,
full,
wr_data_count
);
input [8 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output [8 : 0] dout;
output empty;
output full;
output [16 : 0] wr_data_count;
// synopsys translate_off
FIFO_GENERATOR_V2_0 #(0, // c_common_clock
0, // c_count_type
2, // c_data_count_width
"BlankString", // c_default_value
9, // c_din_width
"0", // c_dout_rst_val
9, // c_dout_width
0, // c_enable_rlocs
"virtex2p", // c_family
0, // c_has_almost_empty
0, // c_has_almost_full
0, // c_has_backup
0, // c_has_data_count
0, // c_has_meminit_file
0, // c_has_overflow
0, // c_has_rd_data_count
0, // c_has_rd_rst
1, // c_has_rst
0, // c_has_underflow
0, // c_has_valid
0, // c_has_wr_ack
1, // c_has_wr_data_count
0, // c_has_wr_rst
2, // c_implementation_type
0, // c_init_wr_pntr_val
1, // c_memory_type
"BlankString", // c_mif_file_name
0, // c_optimization_mode
0, // c_overflow_low
1, // c_preload_latency
0, // c_preload_regs
2048, // c_prim_fifo_type
256, // c_prog_empty_thresh_assert_val
256, // c_prog_empty_thresh_negate_val
0, // c_prog_empty_type
768, // c_prog_full_thresh_assert_val
768, // c_prog_full_thresh_negate_val
0, // c_prog_full_type
2, // c_rd_data_count_width
131072, // c_rd_depth
17, // c_rd_pntr_width
0, // c_underflow_low
0, // c_valid_low
0, // c_wr_ack_low
17, // c_wr_data_count_width
131072, // c_wr_depth
17, // c_wr_pntr_width
1) // c_wr_response_latency
inst (
.DIN(din),
.RD_CLK(rd_clk),
.RD_EN(rd_en),
.RST(rst),
.WR_CLK(wr_clk),
.WR_EN(wr_en),
.DOUT(dout),
.EMPTY(empty),
.FULL(full),
.WR_DATA_COUNT(wr_data_count),
.CLK(),
.BACKUP(),
.BACKUP_MARKER(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.RD_RST(),
.WR_RST(),
.ALMOST_EMPTY(),
.ALMOST_FULL(),
.DATA_COUNT(),
.OVERFLOW(),
.PROG_EMPTY(),
.PROG_FULL(),
.VALID(),
.RD_DATA_COUNT(),
.UNDERFLOW(),
.WR_ACK()
);
// synopsys translate_on
endmodule
| 7.101283 |
module bigger #(
parameter xDW = 16
) (
input wire en, //使能端，=1工作，=0不工作且输出valid=0&OUT=0
input wire rst_n,
input wire clk, //时钟
input wire signed [(xDW -1 ) : 0] x, //输入16位有符号数
output reg OUT, //输出，判断为真=1，假=0
output reg valid //输出是否有效
);
wire EN;
AND_2_1 AND_2_1_inst (
.IN_1(en),
.IN_0(rst_n),
.OUT (EN)
);
always @(posedge clk) begin
if (EN == 1'b0) valid <= 1'b0;
else valid <= 1'b1;
end
always @(posedge clk) begin
if (EN == 1'b0) OUT <= 1'b0;
else begin
if (x > 0) OUT <= 1'b1;
else OUT <= 1'b0;
end
end
endmodule
| 7.505889 |
module biggerAndSmallerOrEqual #(
parameter xDW = 16
) (
input wire en, //使能端，=1工作，=0不工作且输出valid=0&OUT=0
input wire rst_n,
//input wire clk, //时钟
input wire [(xDW - 1) : 0] a,
input wire [(xDW - 1) : 0] b,
input wire [(xDW - 1) : 0] xAbs, //输入16位无符号数
output reg OUT, //输出，判断为真=1，假=0
output reg valid //输出是否有效
);
wire EN;
AND_2_1 AND_2_1_inst (
.IN_1(en),
.IN_0(rst_n),
.OUT (EN)
);
//always @(posedge clk)begin
always @* begin
if (EN == 1'b0) valid <= 1'b0;
else valid <= 1'b1;
end
//always @(posedge clk)begin
always @* begin
if (EN == 1'b0) OUT <= 1'b0;
else begin
if (a < xAbs && xAbs <= b) OUT <= 1'b1;
else OUT <= 1'b0;
end
end
endmodule
| 7.052223 |
module biggerOrEqual #(
parameter xDW = 16
) (
input wire en, //使能端，=1工作，=0不工作且输出valid=0&OUT=0
input wire rst_n,
input wire clk, //时钟
input wire signed [(xDW -1 ) : 0] x, //输入16位有符号数
output reg OUT, //输出，判断为真=1，假=0
output reg valid //输出是否有效
);
wire EN;
AND_2_1 AND_2_1_inst (
.IN_1(en),
.IN_0(rst_n),
.OUT (EN)
);
always @(posedge clk) begin
if (EN == 1'b0) valid <= 1'b0;
else valid <= 1'b1;
end
always @(posedge clk) begin
if (EN == 1'b0) OUT <= 1'b0;
else begin
if (x >= 0) OUT <= 1'b1;
else OUT <= 1'b0;
end
end
endmodule
| 6.956823 |
module biggerOrEqualAndSmaller #(
parameter xDW = 16
) (
input wire en, //使能端，=1工作，=0不工作且输出valid=0&OUT=0
input wire rst_n,
//input wire clk, //时钟
input wire [(xDW - 1) : 0] a,
input wire [(xDW - 1) : 0] b,
input wire [(xDW - 1) : 0] xAbs, //输入16位无符号数
output reg OUT, //输出，判断为真=1，假=0
output reg valid //输出是否有效
);
wire EN;
AND_2_1 AND_2_1_inst (
.IN_1(en),
.IN_0(rst_n),
.OUT (EN)
);
//always @(posedge clk)begin
always @* begin
if (EN == 1'b0) valid <= 1'b0;
else valid <= 1'b1;
end
//always @(posedge clk)begin
always @* begin
if (EN == 1'b0) OUT <= 1'b0;
else begin
if (a <= xAbs && xAbs < b) OUT <= 1'b1;
else OUT <= 1'b0;
end
end
endmodule
| 6.956823 |
module biggest #(
//parameter N_DATA = 2, // Data's binary repr length
parameter N_KEY = 16 // Key's binary repr length
) (
input clk,
input reset,
input enable,
input [2-1:0] data,
input [N_KEY-1:0] key,
output reg [N_KEY-1:0] max_key
);
reg [2*8-1:0] mem_data;
reg [2-1:0] max_data, next_max_data;
reg [N_KEY-1:0] next_max_key;
always @(posedge clk) begin
if (reset) begin
max_data <= {2{1'b0}};
max_key <= {N_KEY{1'b0}};
end else begin
max_data <= next_max_data;
max_key <= next_max_key;
end
end
always @(posedge clk) begin
mem_data[1:0] <= data;
mem_data[3:2] <= mem_data[1:0];
mem_data[5:4] <= mem_data[3:2];
mem_data[7:6] <= mem_data[5:4];
mem_data[9:8] <= mem_data[7:6];
mem_data[11:10] <= mem_data[9:8];
mem_data[13:12] <= mem_data[11:10];
mem_data[15:14] <= mem_data[13:12];
end
wire [4:0] out;
sum16 sumup (
mem_data,
out
);
always @(*) begin
if (enable && (max_data < out)) begin
next_max_data = out;
next_max_key = key;
end else begin
next_max_data = max_data;
next_max_key = max_key;
end
end
endmodule
| 7.579699 |
module bigmux.v (
input [0:1023] in,
input [0:9] sel,
output y);
assign y= in[sel];
endmodule
| 6.762397 |
module bigproduct (
input [10:0] mantissa_A,
input [10:0] mantissa_B,
output reg [21:0] product
);
always @(mantissa_A, mantissa_B) begin
product = mantissa_A * mantissa_B;
end
endmodule
| 7.062375 |
module bigshift (
clk,
inp,
out
);
parameter BITS = 7500;
input clk;
input inp;
output out;
reg [BITS-1:0] r;
always @(posedge clk) r <= {r[BITS-2:0], inp};
assign out = r[BITS-1];
endmodule
| 7.216364 |
module bigsmpy (
i_clk,
i_sync,
i_sgn,
i_a,
i_b,
o_r,
o_sync
);
parameter NCLOCKS = 1;
input wire i_clk, i_sync, i_sgn;
input wire [31:0] i_a, i_b;
output reg [63:0] o_r;
output reg o_sync;
generate
if (NCLOCKS == 1) begin
wire signed [31:0] w_sa, w_sb;
wire [31:0] w_ua, w_ub;
assign w_sa = i_a;
assign w_sb = i_b;
assign w_ua = i_a;
assign w_ub = i_b;
always @(posedge i_clk) begin
o_sync <= i_sync;
if (i_sgn) o_r <= w_sa * w_sb;
else o_r <= w_ua * w_ub;
end
end else if (NCLOCKS == 2) begin
reg r_sync;
reg signed [31:0] r_sa, r_sb;
wire [31:0] w_ua, w_ub;
initial r_sync = 1'b0;
always @(posedge i_clk) begin
r_sync <= i_sync;
r_sa <= i_a;
r_sb <= i_b;
end
assign w_ua = r_sa;
assign w_ub = r_sb;
always @(posedge i_clk) begin
o_sync <= r_sync;
if (i_sgn) o_r <= r_sa * r_sb;
else o_r <= w_ua * w_ub;
end
end else if (NCLOCKS == 5) begin
//
// A pipeline, shift register, to track our
// synchronization pulse as it transits our pipeline
//
reg [3:0] r_s;
//
// Clock #1: Register our inputs, copy the value of the sign
// bit.
reg r_mpy_signed;
reg [31:0] r_mpy_a_input, r_mpy_b_input;
always @(posedge i_clk) begin
if (i_sgn) begin
// This is about more than making the inputs
// unsigned, as you'll notice it makes positive
// inputs otherwise negative. Instead,
// this is about making the inputs have offset
// mode. Hence
// i_a = r_mpy_a_input - 2^31
// and so forth
r_mpy_a_input <= {(~i_a[31]), i_a[30:0]};
r_mpy_b_input <= {(~i_b[31]), i_b[30:0]};
end else begin
r_mpy_a_input <= i_a[31:0];
r_mpy_b_input <= i_b[31:0];
end
r_mpy_signed <= i_sgn;
r_s[0] <= i_sync;
end
reg [31:0] pp_f, pp_o, pp_i, pp_l;
reg [32:0] pp_s;
always @(posedge i_clk) begin
pp_f <= r_mpy_a_input[31:16] * r_mpy_b_input[31:16];
pp_o <= r_mpy_a_input[31:16] * r_mpy_b_input[15:0];
pp_i <= r_mpy_a_input[15:0] * r_mpy_b_input[31:16];
pp_l <= r_mpy_a_input[15:0] * r_mpy_b_input[15:0];
if (r_mpy_signed) pp_s <= 32'h8000_0000 - (r_mpy_a_input[31:0] + r_mpy_b_input[31:0]);
else pp_s <= 33'h0;
r_s[1] <= r_s[0];
end
reg [32:0] partial_mpy_oi, partial_mpy_lo;
reg [31:0] partial_mpy_hi;
always @(posedge i_clk) begin
partial_mpy_lo[30:0] <= pp_l[30:0];
partial_mpy_lo[32:31] <= pp_s[0] + pp_l[31];
partial_mpy_oi[32:0] <= pp_o + pp_i;
partial_mpy_hi[31:0] <= pp_s[32:1] + pp_f;
r_s[2] <= r_s[1];
end
reg partial_mpy_2cl, partial_mpy_2ch;
reg [31:0] partial_mpy_2lo, partial_mpy_2hi;
always @(posedge i_clk) begin
partial_mpy_2lo[15:0] <= partial_mpy_lo[15:0];
{ partial_mpy_2cl, partial_mpy_2lo[31:16] }
<= { 1'b0, partial_mpy_oi[15:0]}
+ partial_mpy_lo[32:16];
{partial_mpy_2ch, partial_mpy_2hi[16:0]} <= partial_mpy_oi[32:16] + partial_mpy_hi[16:0];
partial_mpy_2hi[31:16] <= {partial_mpy_2hi[31:17], 1'b0};
r_s[3] <= r_s[2];
end
always @(posedge i_clk) begin
o_r[31:0] <= partial_mpy_2lo[31:0];
o_r[63:32] <= partial_mpy_2hi + {14'h0, partial_mpy_2ch, 1'b0, 15'h0, partial_mpy_2cl};
o_sync <= r_s[3];
end
end
endgenerate
endmodule
| 6.787472 |
module bigsum (
input sign_A,
input sign_B,
input [10:0] mantissa_A,
input [10:0] mantissa_B,
output reg sign_res,
output reg [11:0] bigsum12
);
always @(mantissa_A, mantissa_B, sign_A, sign_B) begin
case ({
sign_A, sign_B
})
2'b00, 2'b11: begin
bigsum12 = mantissa_A + mantissa_B;
sign_res = sign_A;
end
2'b01, 2'b10: begin
if (mantissa_A > mantissa_B) begin
bigsum12 = mantissa_A - mantissa_B;
sign_res = sign_A;
end else if (mantissa_B > mantissa_A) begin
bigsum12 = mantissa_B - mantissa_A;
sign_res = sign_B;
end else begin
bigsum12 = 12'b0;
sign_res = 0;
end
end
endcase
end
endmodule
| 6.821909 |
module bigword (
input clk,
input rst,
input newframe,
input [9:0] x, // Current pixel to evaluate
input [9:0] y,
input fizzOrBuzz,
output reg out // 1 = set pixel
);
reg dx, dy; // 1 = increment, 0 = decrement
reg [9:0] xpos; // Position of the moving box
reg [9:0] ypos;
reg [3:0] char; // Character to display
wire [7:0] pixels; // Pixels making up one row of the character
// Figure out which character to display at this position
always @(*) begin
case (xoffset[7:6]) // Each character is 64 pixels wide
2'd0: char = fizzOrBuzz ? 4'd10 : 4'd11; // B or F
2'd1: char = fizzOrBuzz ? 4'd13 : 4'd12; // u or i
2'd2, 2'd3: char = 4'd14; // z
endcase
end
// Character generator
chars chars (
.char (char),
.rownum(yoffset[5:3]),
.pixels(pixels)
);
localparam scale = 8; // Scale character size by 8
wire [10:0] xoffset = x - xpos; // Pixel position relative to box
wire [10:0] yoffset = y - ypos;
// Handle the bouncing rectangle
always @(posedge clk) begin
if (rst) begin
dx <= fizzOrBuzz ? 1'b1 : 1'b0; // Start words in opposite directions
dy <= fizzOrBuzz ? 1'b1 : 1'b0;
xpos <= 10'd320;
ypos <= fizzOrBuzz ? 10'd10 : 10'd300;
end else begin
if (newframe) begin
// Bounce
if (xpos <= 1) dx <= 1;
else if (xpos > 640 - 4 * 8 * scale) dx <= 0;
if (ypos <= 1) dy <= 1;
else if (ypos > 480 - 8 * scale) dy <= 0;
xpos <= dx ? xpos + 1'b1 : xpos - 1'b1;
ypos <= dy ? ypos + 1'b1 : ypos - 1'b1;
end
// Output the pixel if inside the rectangle
if (xoffset >= 0 && xoffset < 4 * 8 * scale && yoffset >= 0 && yoffset < 8 * scale) begin
out <= pixels[7-xoffset[5:3]];
end else begin
out <= 0;
end
end
end
endmodule
| 7.499662 |
module generic_fifo_sc_a #(
parameter dw = 8,
parameter aw = 8
) (
clk,
rst,
clr,
din,
we,
dout,
re,
full,
empty
);
parameter max_size = 1 << aw;
input clk, rst, clr;
input [dw-1:0] din;
input we;
output [dw-1:0] dout;
input wire re;
output full;
output empty;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
wire [dw-1:0] din_nc;
wire [dw-1:0] out_nc;
reg [aw-1:0] wp;
wire [aw-1:0] wp_pl1;
reg [aw-1:0] rp;
wire [aw-1:0] rp_pl1;
reg gb;
////////////////////////////////////////////////////////////////////
//
// Memory Block
//
dpram #(
.AWIDTH(aw),
.DWIDTH(dw)
) u0 (
.clk(clk),
.address_a(rp),
.wren_a(0),
.data_a(din_nc),
.out_a(dout),
.address_b(wp),
.wren_b(we),
.data_b(din),
.out_b(out_nc)
);
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk or posedge rst)
if (rst) wp <= {aw{1'b0}};
else if (clr) wp <= {aw{1'b0}};
else if (we) wp <= wp_pl1;
assign wp_pl1 = wp + {{aw - 1{1'b0}}, 1'b1};
always @(posedge clk or posedge rst)
if (rst) rp <= {aw{1'b0}};
else if (clr) rp <= {aw{1'b0}};
else if (re) rp <= rp_pl1;
assign rp_pl1 = rp + {{aw - 1{1'b0}}, 1'b1};
////////////////////////////////////////////////////////////////////
//
// Combinatorial Full & Empty Flags
//
assign empty = ((wp == rp) & !gb);
assign full = ((wp == rp) & gb);
// Guard Bit ...
always @(posedge clk or posedge rst)
if (rst) gb <= 1'b0;
else if (clr) gb <= 1'b0;
else if ((wp_pl1 == rp) & we) gb <= 1'b1;
else if (re) gb <= 1'b0;
endmodule
| 6.701278 |
module dpram #(
parameter DWIDTH = 32,
parameter AWIDTH = 10
) (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
parameter NUM_WORDS = 1 << AWIDTH;
input clk;
input [(AWIDTH-1):0] address_a;
input [(AWIDTH-1):0] address_b;
input wren_a;
input wren_b;
input [(DWIDTH-1):0] data_a;
input [(DWIDTH-1):0] data_b;
output reg [(DWIDTH-1):0] out_a;
output reg [(DWIDTH-1):0] out_b;
`ifdef SIMULATION
reg [DWIDTH-1:0] ram[NUM_WORDS-1:0];
always @(posedge clk) begin
if (wren_a) begin
ram[address_a] <= data_a;
end else begin
out_a <= ram[address_a];
end
end
always @(posedge clk) begin
if (wren_b) begin
ram[address_b] <= data_b;
end else begin
out_b <= ram[address_b];
end
end
`else
dual_port_ram u_dual_port_ram (
.addr1(address_a),
.we1 (wren_a),
.data1(data_a),
.out1 (out_a),
.addr2(address_b),
.we2 (wren_b),
.data2(data_b),
.out2 (out_b),
.clk (clk)
);
`endif
endmodule
| 7.813216 |
module big_function (
in,
key,
out
);
input [1:32] in;
input [1:48] key;
output [1:32] out;
wire [1:48] expanded;
selection_table uut (
in,
expanded
);
wire [1:6] box1, box2, box3, box4, box5, box6, box7, box8;
assign {box1, box2, box3, box4, box5, box6, box7, box8} = expanded ^ key;
wire [1:4] box1_reduced, box2_reduced, box3_reduced, box4_reduced, box5_reduced, box6_reduced, box7_reduced, box8_reduced;
s1box s1 (
box1,
box1_reduced
);
s2box s2 (
box2,
box2_reduced
);
s3box s3 (
box3,
box3_reduced
);
s4box s4 (
box4,
box4_reduced
);
s5box s5 (
box5,
box5_reduced
);
s6box s6 (
box6,
box6_reduced
);
s7box s7 (
box7,
box7_reduced
);
s8box s8 (
box8,
box8_reduced
);
sbox_perm perm (
{
box1_reduced,
box2_reduced,
box3_reduced,
box4_reduced,
box5_reduced,
box6_reduced,
box7_reduced,
box8_reduced
},
out
);
endmodule
| 7.602803 |
module bijiao (
input [31:0] datatwo,
output dataone
);
assign dataone = ($signed(datatwo) >= 0) ? 1 : 0;
endmodule
| 7.294582 |
module bijiaoqi (
input [31:0] a,
input [31:0] b,
output c
);
assign c = (a == b) ? 1 : 0;
endmodule
| 8.537185 |
module bijiaoqi_bltz (
input [31:0] bltz_data,
output bltz_dataout
);
assign bltz_dataout = ($signed(bltz_data) < 0) ? 1 : 0;
endmodule
| 7.824259 |
module bijiaoqi_bne (
input [31:0] a,
input [31:0] b,
output c
);
assign c = (a != b) ? 1 : 0;
endmodule
| 7.548005 |
module bijiaoqi_movz (
input [31:0] a,
output b
);
assign b = (a == 0) ? 1 : 0;
endmodule
| 7.830266 |
module bijiao_bgtz (
input [31:0] bgtz_data,
output bgtz_dataout
);
assign bgtz_dataout = ($signed(bgtz_data) > 0) ? 1 : 0;
endmodule
| 8.189529 |
module bijiao_blez (
input [31:0] blez_data,
output blez_dataout
);
assign blez_dataout = ($signed(blez_data) <= 0) ? 1 : 0;
endmodule
| 8.071908 |
module ramFifo #(
parameter DATA_WIDTH = 8,
parameter ADDRESS_WIDTH = 8,
parameter BUFFER_SIZE = 3,
parameter BUFFER_SIZE_WIDTH = ((BUFFER_SIZE+1) <= 2) ? 1 : //wide enough to hold value BUFFER_SIZE + 1
((BUFFER_SIZE+1) <= 4) ? 2 :
((BUFFER_SIZE+1) <= 8) ? 3 :
((BUFFER_SIZE+1) <= 16) ? 4 :
((BUFFER_SIZE+1) <= 32) ? 5 :
((BUFFER_SIZE+1) <= 64) ? 6 : 7
) (
input wire clk,
input wire rst,
input wire advanceRead, //Advance selected read RAM by one
input wire advanceWrite, //Advance selected write RAM by one
input wire [ DATA_WIDTH-1:0] writeData,
input wire [ ADDRESS_WIDTH-1:0] writeAddress,
input wire writeEnable,
output reg [BUFFER_SIZE_WIDTH-1:0] fillCount,
output wire [DATA_WIDTH-1:0] readData0, //Read from deepest RAM (earliest data), at readAddress
output wire [DATA_WIDTH-1:0] readData1, //Read from second deepest RAM (second earliest data), at readAddress
output wire [DATA_WIDTH-1:0] readData2, //Read from third deepest RAM (third earliest data), at readAddress
input wire [ADDRESS_WIDTH-1:0] readAddress
);
reg [BUFFER_SIZE-1:0] writeSelect;
reg [BUFFER_SIZE-1:0] readSelect;
//Read select ring register
always @(posedge clk or posedge rst) begin
if (rst) readSelect <= {1'b1, {(BUFFER_SIZE - 1) {1'b0}}}; //Mod for demosaic, normally 1
else begin
if (advanceRead) begin
readSelect <= {readSelect[BUFFER_SIZE-2 : 0], readSelect[BUFFER_SIZE-1]};
end
end
end
//Write select ring register
always @(posedge clk or posedge rst) begin
if (rst) writeSelect <= 1;
else begin
if (advanceWrite) begin
writeSelect <= {writeSelect[BUFFER_SIZE-2 : 0], writeSelect[BUFFER_SIZE-1]};
end
end
end
wire [DATA_WIDTH-1:0] ramDataOut[2**BUFFER_SIZE-1:0];
//Generate to instantiate the RAMs
generate
genvar i;
for (i = 0; i < BUFFER_SIZE; i = i + 1) begin : ram_generate
ramDualPort #(
.DATA_WIDTH(DATA_WIDTH),
.ADDRESS_WIDTH(ADDRESS_WIDTH)
) ram_inst_i (
.clk(clk),
//Port A is written to, port B is read from
.addrA(writeAddress),
.dataA(writeData),
.weA((writeSelect[i] == 1'b1) ? writeEnable : 1'b0),
.qA(),
.addrB(readAddress),
.dataB(0),
.weB(1'b0),
.qB(ramDataOut[2**i])
);
end
endgenerate
//Select which ram to read from
wire [BUFFER_SIZE-1:0] readSelect0 = readSelect;
wire [BUFFER_SIZE-1:0] readSelect1 = (readSelect << 1) | readSelect[BUFFER_SIZE-1];
wire [BUFFER_SIZE-1:0] readSelect2 = (readSelect << 2) | readSelect[BUFFER_SIZE-1:BUFFER_SIZE-2];
//Steer the output data to the right ports
assign readData0 = ramDataOut[readSelect0];
assign readData1 = ramDataOut[readSelect1];
assign readData2 = ramDataOut[readSelect2];
//Keep track of fill level
always @(posedge clk or posedge rst) begin
if (rst) begin
fillCount <= 1; //Mod for demosaic, normally 0. The first line has to come out of readData1, the invalid data from readData0 will be masked
end else begin
if (advanceWrite) begin
if (advanceRead) fillCount <= fillCount;
else fillCount <= fillCount + 1;
end else begin
if (advanceRead) fillCount <= fillCount - 1;
else fillCount <= fillCount;
end
end
end
endmodule
| 8.218147 |
module ramDualPort #(
parameter DATA_WIDTH = 8,
parameter ADDRESS_WIDTH = 8
) (
input wire [(DATA_WIDTH-1):0] dataA,
dataB,
input wire [(ADDRESS_WIDTH-1):0] addrA,
addrB,
input wire weA,
weB,
clk,
output reg [(DATA_WIDTH-1):0] qA,
qB
);
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDRESS_WIDTH-1:0];
//Port A
always @(posedge clk) begin
if (weA) begin
ram[addrA] <= dataA;
qA <= dataA;
end else begin
qA <= ram[addrA];
end
end
//Port B
always @(posedge clk) begin
if (weB) begin
ram[addrB] <= dataB;
qB <= dataB;
end else begin
qB <= ram[addrB];
end
end
endmodule
| 8.70941 |
module bilinearintrp (
u01a,
u01b,
u01c,
v01a,
v01b,
v01c,
u10a,
u10b,
u10c,
v10a,
v10b,
v10c,
selectuv,
ru,
rv,
rw,
gu,
gv,
gw,
bu,
bv,
bw,
r,
g,
b,
clk
);
input [7:0] u01a;
input [7:0] u01b;
input [7:0] u01c;
input [7:0] v01a;
input [7:0] v01b;
input [7:0] v01c;
input [7:0] u10a;
input [7:0] u10b;
input [7:0] u10c;
input [7:0] v10a;
input [7:0] v10b;
input [7:0] v10c;
input [2:0] selectuv;
input [6:0] ru;
input [6:0] rv;
input [6:0] rw;
input [6:0] gu;
input [6:0] gv;
input [6:0] gw;
input [6:0] bu;
input [6:0] bv;
input [6:0] bw;
output [6:0] r;
wire [6:0] r;
output [6:0] g;
wire [6:0] g;
output [6:0] b;
wire [6:0] b;
input clk;
reg [ 7:0] u;
reg [ 7:0] v;
reg [ 7:0] ul;
reg [ 7:0] vl;
reg [ 7:0] wl;
reg [14:0] i1b;
reg [14:0] i2b;
reg [14:0] i3b;
reg [14:0] i1g;
reg [14:0] i2g;
reg [14:0] i3g;
reg [14:0] i1r;
reg [14:0] i2r;
reg [14:0] i3r;
reg [ 6:0] rul;
reg [ 6:0] rvl;
reg [ 6:0] rwl;
reg [ 6:0] gul;
reg [ 6:0] gvl;
reg [ 6:0] gwl;
reg [ 6:0] bul;
reg [ 6:0] bvl;
reg [ 6:0] bwl;
always @(selectuv or u01a or u01b or u01c or v01a or v01b or v01c or u10a or
u10b or u10c or v10a or v10b or v10c)
begin
case (selectuv)
3'b000: begin
u = u01a;
v = v01a;
end
3'b001: begin
u = u01b;
v = v01b;
end
3'b010: begin
u = u01c;
v = v01c;
end
3'b100: begin
u = u10a;
v = v10a;
end
3'b101: begin
u = u10b;
v = v10b;
end
3'b110: begin
u = u10c;
v = v10c;
end
default: begin
u = 0;
v = 0;
end
endcase
end
always @(posedge clk) begin
wl <= 8'b11111111 - u - v;
ul <= u;
vl <= v;
rul <= ru;
rvl <= rv;
rwl <= rw;
gul <= gu;
gvl <= gv;
gwl <= gw;
bul <= bu;
bvl <= bv;
bwl <= bw;
i1r <= ul * rul;
i2r <= vl * rvl;
i3r <= wl * rwl;
i1g <= ul * gul;
i2g <= vl * gvl;
i3g <= wl * gwl;
i1b <= ul * bul;
i2b <= vl * bvl;
i3b <= wl * bwl;
end
assign r = (i1r + i2r + i3r);
assign g = (i1g + i2g + i3g);
assign b = (i1b + i2b + i3b);
endmodule
| 6.725338 |
module bimodal (
in_PC,
in_hit,
in_Clk,
in_Rst_N,
out_prediction
);
input in_hit, in_Clk, in_Rst_N;
input [8:0] in_PC;
output out_prediction;
pht pht_Inst0 (
.in_addr(in_PC),
.in_data(in_hit),
.in_Clk(in_Clk),
.in_Rst_N(in_Rst_N),
.out_prediction(out_prediction)
);
endmodule
| 6.767516 |
module Bimodal_Table (
Clk,
wr,
rd,
index /*pc*/,
rdata_c_bits,
correct_prediction,
inc_counter,
dec_counter,
update_enable
);
parameter IL = 13; //Index size ie number of addresses
parameter CL = 3; //Counter length
reg [CL-1 : 0] c_bits[(1 << IL) - 1 : 0]; //Counter table
output [CL-1 : 0] rdata_c_bits;
reg [CL-1 : 0] rdata_c_bits_reg;
input [IL - 1 : 0] index;
input Clk, rd, wr;
input correct_prediction;
input inc_counter;
input dec_counter;
input update_enable;
integer i, j;
initial begin
for (i = 0; i < (1 << IL); i = i + 1) begin
c_bits[i] = {CL{1'b0}}; //initialize the bits
end
end
// Keep addr and write data
always @(posedge Clk) begin
if (inc_counter == 1'b1 && update_enable == 1'b1 && c_bits[index] != {CL{1'b1}}) begin
c_bits[index] <= c_bits[index] + 1'b1;
end else if (dec_counter == 1'b1 && update_enable == 1'b1 && c_bits[index] != {CL{1'b0}}) begin
c_bits[index] <= c_bits[index] - 1'b1;
end else begin
c_bits[index] <= c_bits[index];
end
end
//
// Read process
// ------------
always @(posedge Clk) begin
if (rd) begin
rdata_c_bits_reg <= c_bits[index];
end else begin
rdata_c_bits_reg <= {CL{1'bX}};
end
end
assign rdata_c_bits = rdata_c_bits_reg;
endmodule
| 6.659628 |
module bimpy #(
// {{{
parameter BW = 18, // Number of bits in i_b
// DESIGN COMPILER MODIFICATON - Parameters must be declared before use
parameter LUTB = 2 // Number of bits in i_a for our LUT multiply
// }}}
) (
// {{{
input wire i_clk,
i_reset,
i_ce,
input wire [(LUTB-1):0] i_a,
input wire [(BW-1):0] i_b,
output reg [(BW+LUTB-1):0] o_r
// }}}
);
// localparam LUTB=2; // Number of bits in i_a for our LUT multiply
// Local declarations
// {{{
wire [(BW+LUTB-2):0] w_r;
wire [(BW+LUTB-3):1] c;
// }}}
assign w_r = {((i_a[1]) ? i_b : {(BW) {1'b0}}), 1'b0} ^ {1'b0, ((i_a[0]) ? i_b : {(BW) {1'b0}})};
assign c = { ((i_a[1])?i_b[(BW-2):0]:{(BW-1){1'b0}}) }
& ((i_a[0])?i_b[(BW-1):1]:{(BW-1){1'b0}});
// o_r
// {{{
initial o_r = 0;
always @(posedge i_clk)
if (i_reset) o_r <= 0;
else if (i_ce) o_r <= w_r + {c, 2'b0};
// }}}
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
// Formal property section
// {{{
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
`ifdef FORMAL
reg f_past_valid;
initial f_past_valid = 1'b0;
always @(posedge i_clk) f_past_valid <= 1'b1;
`define ASSERT assert
always @(posedge i_clk)
if ((!f_past_valid) || ($past(i_reset))) begin
`ASSERT(o_r == 0);
end else if ($past(i_ce)) begin
if ($past(i_a) == 0) begin
`ASSERT(o_r == 0);
end else if ($past(i_a) == 1) `ASSERT(o_r == $past(i_b));
if ($past(i_b) == 0) begin
`ASSERT(o_r == 0);
end else if ($past(i_b) == 1) `ASSERT(o_r[(LUTB-1):0] == $past(i_a));
end
`endif
// }}}
endmodule
| 6.898984 |
module BIN12_to_DEC4 (
input [11:0] BIN,
output wire [15:0] DEC,
input st,
output reg [2:0] ptr_dig = 0, //
input clk,
output reg en_conv = 0
); //
reg [ 3:0] D1dec = 0;
reg [ 3:0] D2dec = 0;
reg [ 3:0] D3dec = 0;
reg [ 3:0] D4dec = 0;
reg [16:0] rest = 0; //
assign DEC = {D4dec, D3dec, D2dec, D1dec};
wire d4 = (ptr_dig == 4);
wire d3 = (ptr_dig == 3);
wire d2 = (ptr_dig == 2);
wire d1 = (ptr_dig == 1);
wire [15:0] Nd = d4 ? 1000 : d3 ? 100 : d2 ? 10 : d1 ? 1 : 0;
wire [16:0] dx = rest - Nd; // di (i=,4,3,2,1)
wire z = dx[16]; //
wire en_inc_dig = en_conv & !z; //
wire en_dec_ptr = en_conv & z; //
always @(posedge clk) begin
en_conv <= st ? 1 : (ptr_dig == 0) ? 0 : en_conv; //
rest <= st ? BIN : en_inc_dig ? dx : rest; //
ptr_dig <= st ? 4 : en_dec_ptr ? ptr_dig - 1 : ptr_dig; //
D4dec <= st ? 0 : (d4 & en_inc_dig) ? D4dec + 1 : D4dec;
D3dec <= st ? 0 : (d3 & en_inc_dig) ? D3dec + 1 : D3dec;
D2dec <= st ? 0 : (d2 & en_inc_dig) ? D2dec + 1 : D2dec;
D1dec <= st ? 0 : (d1 & en_inc_dig) ? D1dec + 1 : D1dec;
//ok <=(ptr_dig==0) & en_conv;
end
endmodule
| 7.018131 |
module BIN16_to_DEC4 (
input [15:0] BIN,
output reg [15:0] DEC = 0,
input clk,
output reg [4:0] ptr_dig = 0, //
input st,
output reg en_conv = 0,
output reg ok = 0
);
//----
reg [3:0] D1dec = 0;
reg [3:0] D2dec = 0;
reg [3:0] D3dec = 0;
reg [3:0] D4dec = 0;
reg q = 0;
reg [16:0] rest; //
wire[15:0]Nd = (ptr_dig==4)? 1000 :
(ptr_dig==3)?100 :
(ptr_dig==2)?10 :
(ptr_dig==1)?1 : 0 ;
wire [16:0] dx = rest - Nd; // di (i=4,3,2,1)
wire z = dx[16]; //
wire en_inc_dig = en_conv & q & !z; //
wire en_dec_ptr = en_conv & !q & z; //
always @(posedge clk) begin
q <= st ? 0 : en_conv ? !q : q; //q -
en_conv <= st ? 1 : (ptr_dig == 0) ? 0 : en_conv; //
rest <= st ? BIN : en_inc_dig ? dx : rest; //
ptr_dig <= st ? 4 : en_dec_ptr ? ptr_dig - 1 : ptr_dig; //
D4dec <= st ? 0 : ((ptr_dig == 4) & en_inc_dig) ? D4dec + 1 : D4dec;
D3dec <= st ? 0 : ((ptr_dig == 3) & en_inc_dig) ? D3dec + 1 : D3dec;
D2dec <= st ? 0 : ((ptr_dig == 2) & en_inc_dig) ? D2dec + 1 : D2dec;
D1dec <= st ? 0 : ((ptr_dig == 1) & en_inc_dig) ? D1dec + 1 : D1dec;
ok <= (ptr_dig == 0) & en_conv;
DEC <= ok ? {D4dec, D3dec, D2dec, D1dec} : DEC;
end
endmodule
| 6.941222 |
module bin2AsciiHex (
output wire [7:0] asciiHex,
input [3:0] hx
);
wire lowerTen;
assign lowerTen = ~hx[3] | ~hx[2] & ~hx[1];
assign asciiHex = lowerTen ?
{4'h3, hx[3:0]} :
{4'h6, 1'b0,
~hx[1] & hx[0] | hx[2] & hx[1],
~hx[1] & ~hx[0] | hx[1] & hx[0],
~hx[0]};
endmodule
| 6.715758 |
module bin2AsciiHex (
// output reg [7:0] asciiHex,
// input [3:0] inVal);
//
// always @(*) begin
// casex (inVal)
// 4'ha : asciiHex = 8'h61;
// 4'hb : asciiHex = 8'h62;
// 4'hc : asciiHex = 8'h63;
// 4'hd : asciiHex = 8'h64;
// 4'he : asciiHex = 8'h65;
// 4'hf : asciiHex = 8'h66;
// default : asciiHex = {4'h3, inVal};
// endcase // casex (inVal)
// end // always @ (*)
//endmodule
| 6.715758 |
module bin2bcd32 (
input CLK,
input RST,
input en,
input [31:0] bin,
output [3:0] bcd0,
output [3:0] bcd1,
output [3:0] bcd2,
output [3:0] bcd3,
output [3:0] bcd4,
output [3:0] bcd5,
output [3:0] bcd6,
output [3:0] bcd7,
output [3:0] bcd8,
output [3:0] bcd9,
output busy,
output fin
);
reg [31:0] bin_r;
reg [4:0] bitcount;
reg [3:0] bcd[0:9];
wire [3:0] bcdp[0:9];
assign bcd0 = bcd[0];
assign bcd1 = bcd[1];
assign bcd2 = bcd[2];
assign bcd3 = bcd[3];
assign bcd4 = bcd[4];
assign bcd5 = bcd[5];
assign bcd6 = bcd[6];
assign bcd7 = bcd[7];
assign bcd8 = bcd[8];
assign bcd9 = bcd[9];
localparam s_idle = 2'b00;
localparam s_busy = 2'b01;
localparam s_fin = 2'b10;
reg [1:0] state;
assign busy = state != s_idle;
assign fin = state == s_fin;
always @(posedge CLK or negedge RST)
if (!RST) begin
state <= s_idle;
end else begin
case (state)
s_idle: if (en) state <= s_busy;
s_busy: if (bitcount == 5'd31) state <= s_fin;
s_fin: state <= s_idle;
default: ;
endcase
end
always @(posedge CLK) begin
case (state)
s_idle: if (en) bin_r <= bin;
s_busy: bin_r <= {bin_r[30:0], 1'b0};
default: ;
endcase
end
always @(posedge CLK or negedge RST)
if (!RST) begin
bitcount <= 5'd0;
end else begin
case (state)
s_busy: bitcount <= bitcount + 5'd1;
default: bitcount <= 5'd0;
endcase
end
generate
genvar g;
for (g = 0; g <= 9; g = g + 1) begin : GEN_BCD
wire [3:0] s;
wire [3:0] prev;
assign bcdp[g] = (bcd[g] >= 4'd5) ? bcd[g] + 4'd3 : bcd[g];
if (g != 0) begin
assign prev = bcdp[g-1];
end else begin // if (g != 0)
assign prev = {bin_r[31], 3'b0};
end
assign s = ((bcdp[g] << 1) | (prev >> 3));
always @(posedge CLK or negedge RST)
if (!RST) begin
bcd[g] <= 4'd0;
end else begin
case (state)
s_idle: bcd[g] <= 4'd0;
s_busy: bcd[g] <= s;
default: ;
endcase
end
end
endgenerate
endmodule
| 6.8071 |
module bin2bcd_12 (
input wire clk,
nrst,
input wire start,
input wire [11:0] bin,
output reg [15:0] bcd,
output reg valid
);
reg [11:0] bin_in;
reg op;
reg [3:0] cnt;
always @(posedge clk or negedge nrst) begin
if (nrst == 0) bin_in <= 0;
else if (start) bin_in <= bin;
end
always @(posedge clk or negedge nrst) begin
if (nrst == 0) op <= 0;
else if (start) op <= 1;
else if (cnt == 12 - 1) op <= 0;
end
always @(posedge clk or negedge nrst) begin
if (nrst == 0) cnt <= 0;
else if (op) cnt <= cnt + 1'b1;
else cnt <= 0;
end
function [3:0] fout(input reg [3:0] fin);
fout = (fin > 4) ? fin + 4'd3 : fin;
endfunction
always @(posedge clk or negedge nrst) begin
if (nrst == 0) bcd <= 0;
else if (op) begin
bcd[0] <= bin_in[11-cnt];
bcd[4:1] <= fout(bcd[3:0]);
bcd[8:5] <= fout(bcd[7:4]);
bcd[12:9] <= fout(bcd[11:8]);
bcd[15:13] <= fout(bcd[15:12]);
end else bcd <= 0;
end
always @(posedge clk or negedge nrst) begin
if (nrst == 0) valid <= 0;
else if (cnt == 12 - 1) valid <= 1;
else valid <= 0;
end
endmodule
| 7.16587 |
module bin2bcd_c (
input wire clk,
nrst,
input wire start,
input wire [11:0] bin,
output reg [15:0] bcd,
output reg valid
);
reg [11:0] bin_in;
reg op;
reg [3:0] cnt;
always @(posedge clk or negedge nrst) begin
if (nrst == 0) bin_in <= 0;
else if (start) bin_in <= bin;
end
always @(posedge clk or negedge nrst) begin
if (nrst == 0) op <= 0;
else if (start) op <= 1;
else if (cnt == 12 - 1) op <= 0;
end
always @(posedge clk or negedge nrst) begin
if (nrst == 0) cnt <= 0;
else if (op) cnt <= cnt + 1'b1;
else cnt <= 0;
end
function [3:0] fout(input reg [3:0] fin);
fout = (fin > 4) ? fin + 4'd3 : fin;
endfunction
always @(posedge clk or negedge nrst) begin
if (nrst == 0) bcd <= 0;
else if (op) begin
bcd[0] <= bin_in[11-cnt];
bcd[4:1] <= fout(bcd[3:0]);
bcd[8:5] <= fout(bcd[7:4]);
bcd[12:9] <= fout(bcd[11:8]);
bcd[15:13] <= fout(bcd[15:12]);
end else bcd <= 0;
end
always @(posedge clk or negedge nrst) begin
if (nrst == 0) valid <= 0;
else if (cnt == 12 - 1) valid <= 1;
else valid <= 0;
end
endmodule
| 7.100714 |
module bcd_digit (
input wire clock,
input wire ce,
input wire init,
input wire mod_in,
output wire mod_out,
output reg [3:0] digit
);
wire fiveOrMore = digit >= 5;
assign mod_out = fiveOrMore & ~init;
always @(posedge clock) begin
if (ce) begin
digit[0] <= mod_in;
digit[1] <= ~init & (~mod_out ? digit[0] : ~digit[0]);
digit[2] <= ~init & (~mod_out ? digit[1] : digit[1] == digit[0]);
digit[3] <= ~init & (~mod_out ? digit[2] : digit[0] & digit[3]);
end
end
endmodule
| 6.918817 |
module bin2bcd_test (
input wire clk,
reset,
input wire btn,
input wire [12:0] sw,
output wire [ 3:0] an,
output wire [ 7:0] sseg,
output wire [ 1:0] led
);
// signal declaration
wire start;
wire [3:0] bcd3, bcd2, bcd1, bcd0;
// instance of debouncer
debounce db_unit (
.clk(clk),
.reset(reset),
.sw(btn),
.db_level(),
.db_tick(start)
);
// instance of binary-to-bcd converter
bin2bcd bin2bcd_unit (
.clk(clk),
.reset(reset),
.start(start),
.bin(sw),
.ready(led[0]),
.done_tick(led[1]),
.bcd3(bcd3),
.bcd2(bcd2),
.bcd1(bcd1),
.bcd0(bcd0)
);
// instance of display unit
disp_hex_mux disp_unit (
.clk(clk),
.reset(reset),
.hex3(bcd3),
.hex2(bcd2),
.hex1(bcd1),
.hex0(bcd0),
.dp_in(4'b1111),
.an(an),
.sseg(sseg)
);
endmodule
| 8.045954 |
module bin2bcd_testbench;
reg [13:0] in;
wire [15:0] out;
integer i;
bin2bcd myConverter (
.binary(in),
.bcd(out)
);
initial begin
in <= 0;
$monitor("in=0x%0h out=%0b", in, out);
for (i = 0; i < 32; i = i + 1) begin
in = i;
#10;
end
#10;
in = 8'b11110011;
#10;
in = 9999;
end
endmodule
| 6.67359 |
module Bin2Chr (
bin,
chr
);
input [2:0] bin;
output reg [7:0] chr;
always @(*) begin
case (bin)
3'b000: chr <= 8'd48; // 0
3'b001: chr <= 8'd49; // 1
3'b010: chr <= 8'd50; // 2
3'b011: chr <= 8'd51; // 3
3'b100: chr <= 8'd52; // 4
3'b101: chr <= 8'd53; // 5
3'b110: chr <= 8'd54; // 6
3'b111: chr <= 8'd55; // 7
default: chr <= 8'd42; // *
endcase
end
endmodule
| 6.62552 |
module bin2comp #(
parameter NUMBER_OF_BITS = 12
) (
bin,
inv_add
);
//Input
input [NUMBER_OF_BITS-1:0] bin;
//Ouput
output [NUMBER_OF_BITS-1:0] inv_add;
assign inv_add = bin[NUMBER_OF_BITS-1] ? (~bin + 1'b1) : bin;
// assign inv_add = (~ bin +1'b1);
endmodule
| 6.990781 |
module bin2gray #(
parameter WIDTH = 8
) (
input [WIDTH-1:0] bin,
output [WIDTH-1:0] gray
);
assign gray = (bin >> 1) ^ bin;
endmodule
| 7.498057 |
module bin2gray_tb;
reg clock = 1;
always #5 clock <= ~clock;
reg reset = 0;
reg [`MSB:0] count_b = 0;
wire [`MSB:0] count_g;
always @(posedge clock)
if (reset) count_b <= 0;
else count_b <= count_b + 1;
initial begin : Sim
$display("%t: Count = %d, Gray = %b", $time, count_b, count_g);
$monitor("%t: Count = %d, Gray = %b", $time, count_b, count_g);
#2 reset <= 1;
#10 reset <= 0;
#600 $finish;
end // Sim
bin2gray #(
.WIDTH(`WIDTH)
) B2G0 (
.bin_i (count_b),
.gray_o(count_g)
);
endmodule
| 6.624144 |
module bin2hex (
input [3:0] in,
output reg [7:0] out
);
always @(in) begin
case (in)
4'h0: out = 7'h30;
4'h1: out = 7'h31;
4'h2: out = 7'h32;
4'h3: out = 7'h33;
4'h4: out = 7'h34;
4'h5: out = 7'h35;
4'h6: out = 7'h36;
4'h7: out = 7'h37;
4'h8: out = 7'h38;
4'h9: out = 7'h39;
4'ha: out = "A";
4'hb: out = "B";
4'hc: out = "C";
4'hd: out = "D";
4'he: out = "E";
4'hf: out = "F";
endcase
end
endmodule
| 7.54151 |
module bin2hex32 (
input wire [31:0] value,
output wire [ 3:0] dig0,
output wire [ 3:0] dig1,
output wire [ 3:0] dig2,
output wire [ 3:0] dig3,
output wire [ 3:0] dig4,
output wire [ 3:0] dig5,
output wire [ 3:0] dig6,
output wire [ 3:0] dig7
);
assign dig0 = value & 4'hFF;
assign dig1 = value >> 4 & 4'hFF;
assign dig2 = value >> 8 & 4'hFF;
assign dig3 = value >> 12 & 4'hFF;
assign dig4 = value >> 16 & 4'hFF;
assign dig5 = value >> 20 & 4'hFF;
assign dig6 = value >> 24 & 4'hFF;
assign dig7 = value >> 28 & 4'hFF;
endmodule
| 6.687659 |
module receives a 4-bit input and converts it to 7-segment
// LED (HEX)
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: INCOMPLETE CODE
//
//////////////////////////////////////////////////////////////////////////////////
module binary_to_segment(
input[2:0] player_score,
input[2:0] cpu_score,
input clk,
output reg [6:0] seven_output,
output reg [3:0] AN
);
reg[6:0] seven_1;
reg[6:0] seven_2;
reg[6:0] seven_3;
reg[6:0] seven_4; //Assume MSB is A, and LSB is G
reg[10:0] clk_count; //25 bits is enough for ~2 cycles/second division
reg[1:0] LED_route;
//assign AN[selection] = 0'b1;
wire count_max = &clk_count;
initial begin //Initial block, used for correct simulations
AN=4'b1111;
clk_count = 0;
LED_route = 0;
seven_1 = 7'b1111110;
seven_2 = 7'b1111110;
seven_3 = 7'b1111110;
seven_4 = 7'b1111110;
end
always @ (posedge clk) begin
if(count_max) begin
clk_count = 0;
case(cpu_score)
0: seven_1 = 7'b0000001;
1: seven_1 = 7'b1001111;
2: seven_1 = 7'b0010010;
3: seven_1 = 7'b0000110;
4: seven_1 = 7'b1001100;
5: seven_1 = 7'b0100100;
6: seven_1 = 7'b0100000;
7: seven_1 = 7'b0001111;
8: seven_1 = 7'b0000000;
9: seven_1 = 7'b0001100;
//15: seven = 7'b0111000; // This will show F
//remember 0 means ‘‘light-up’’
default: seven_1 = 7'b1111110;//Something here
//Something here
endcase
case(player_score)
0: seven_4 = 7'b0000001;
1: seven_4 = 7'b1001111;
2: seven_4 = 7'b0010010;
3: seven_4 = 7'b0000110;
4: seven_4 = 7'b1001100;
5: seven_4 = 7'b0100100;
6: seven_4 = 7'b0100000;
7: seven_4 = 7'b0001111;
8: seven_4 = 7'b0000000;
9: seven_4 = 7'b0001100;
//15: seven = 7'b0111000; // This will show F
//remember 0 means ‘‘light-up’’
default: seven_4 = 7'b1111110;//Something here
//Something here
endcase
case(LED_route)
2'b00:begin AN = 4'b1110; seven_output = seven_1; end
2'b01:begin AN = 4'b1101; seven_output = seven_2; end
2'b10:begin AN = 4'b1011; seven_output = seven_3; end
2'b11:begin AN = 4'b0111; seven_output = seven_4; end
default: AN = 4'b1111;
endcase
LED_route = LED_route + 2'b01;
//AN = 4'b0000;
//AN[selection] = 1'b0;
end
else clk_count = clk_count + 1'b1;
end
endmodule
| 6.985545 |
module bin2onehot #(
parameter DW = 32
) (
input [NB-1:0] bin, // unsigned binary input
output [DW-1:0] onehot // one hot output vector
);
parameter NB = $clog2(DW);
`ifdef OPTIMISED
integer i;
reg [DW-1:0] ronehot;
always @(*) begin
for (i = 0; i < DW; i = i + 1) ronehot[i] = (bin[NB-1:0] == i);
end
assign onehot = ronehot;
`else
assign onehot = (1 << (bin + 1));
`endif
endmodule
| 6.976573 |
module bin2seg (
input wire [3:0] bin,
output reg [7:0] seg
);
always @(bin) begin
case (bin)
4'd0: seg = 8'b0000_0011; // 0
4'd1: seg = 8'b1001_1111; // 1
4'd2: seg = 8'b0010_0101; // 2
4'd3: seg = 8'b0000_1101; // 3
4'd4: seg = 8'b1001_1001; // 4
4'd5: seg = 8'b0100_1001; // 5
4'd6: seg = 8'b0100_0001; // 6
4'd7: seg = 8'b0001_1011; // 7
4'd8: seg = 8'b0000_0001; // 8
4'd9: seg = 8'b0001_1001; // 9
4'd10: seg = 8'b1111_1101; // Dash
default: seg = 8'b0000_0011;
endcase
end
endmodule
| 7.226392 |
module top (
input clock_100Mhz, // 100 Mhz clock source on Basys 3 FPGA
input reset, // reset
output reg [3:0] Anode_Activate, // anode signals of the 7-segment LED display
output reg [6:0] LED_out // cathode patterns of the 7-segment LED display
);
reg [26:0] one_second_counter; // counter for generating 1 second clock enable
wire one_second_enable; // one second enable for counting numbers
reg [15:0] displayed_number; // counting number to be displayed
reg [3:0] LED_BCD;
reg [19:0] refresh_counter; // 20-bit for creating 10.5ms refresh period or 380Hz refresh rate
// the first 2 MSB bits for creating 4 LED-activating signals with 2.6ms digit period
wire [1:0] LED_activating_counter;
// count 0 -> 1 -> 2 -> 3
// activates LED1 LED2 LED3 LED4
// and repeat
always @(posedge clock_100Mhz or posedge reset) begin
if (reset == 1) one_second_counter <= 0;
else begin
if (one_second_counter >= 99999999) one_second_counter <= 0;
else one_second_counter <= one_second_counter + 1;
end
end
assign one_second_enable = (one_second_counter == 99999999) ? 1 : 0;
always @(posedge clock_100Mhz or posedge reset) begin
if (reset == 1) displayed_number <= 0;
else if (one_second_enable == 1) displayed_number <= displayed_number + 1;
end
always @(posedge clock_100Mhz or posedge reset) begin
if (reset == 1) refresh_counter <= 0;
else refresh_counter <= refresh_counter + 1;
end
assign LED_activating_counter = refresh_counter[19:18];
// anode activating signals for 4 LEDs, digit period of 2.6ms
// decoder to generate anode signals
always @(*) begin
case (LED_activating_counter)
2'b00: begin
Anode_Activate = 4'b0111;
// activate LED1 and Deactivate LED2, LED3, LED4
LED_BCD = displayed_number / 1000;
// the first digit of the 16-bit number
end
2'b01: begin
Anode_Activate = 4'b1011;
// activate LED2 and Deactivate LED1, LED3, LED4
LED_BCD = (displayed_number % 1000) / 100;
// the second digit of the 16-bit number
end
2'b10: begin
Anode_Activate = 4'b1101;
// activate LED3 and Deactivate LED2, LED1, LED4
LED_BCD = ((displayed_number % 1000) % 100) / 10;
// the third digit of the 16-bit number
end
2'b11: begin
Anode_Activate = 4'b1110;
// activate LED4 and Deactivate LED2, LED3, LED1
LED_BCD = ((displayed_number % 1000) % 100) % 10;
// the fourth digit of the 16-bit number
end
endcase
end
// Cathode patterns of the 7-segment LED display
always @(*) begin
case (LED_BCD)
4'b0000: LED_out = 7'b0000001; // "0"
4'b0001: LED_out = 7'b1001111; // "1"
4'b0010: LED_out = 7'b0010010; // "2"
4'b0011: LED_out = 7'b0000110; // "3"
4'b0100: LED_out = 7'b1001100; // "4"
4'b0101: LED_out = 7'b0100100; // "5"
4'b0110: LED_out = 7'b0100000; // "6"
4'b0111: LED_out = 7'b0001111; // "7"
4'b1000: LED_out = 7'b0000000; // "8"
4'b1001: LED_out = 7'b0000100; // "9"
default: LED_out = 7'b0000001; // "0"
endcase
end
endmodule
| 7.233807 |
module BIN32_to_DEC8 (
input [31:0] BIN,
output reg [31:0] DEC = 0,
input clk,
output reg [3:0] ptr_dig = 0, //
input st,
output reg en_conv = 0,
output reg ok_conv = 0
);
reg [3:0] D1dec = 0;
reg [3:0] D2dec = 0;
reg [3:0] D3dec = 0;
reg [3:0] D4dec = 0;
reg [3:0] D5dec = 0;
reg [3:0] D6dec = 0;
reg [3:0] D7dec = 0;
reg [3:0] D8dec = 0;
reg q = 0;
reg [27:0] rest = 0; //
wire[26:0]Nd = (ptr_dig==8)?10000000 :
(ptr_dig==7)?1000000 :
(ptr_dig==6)?100000 :
(ptr_dig==5)?10000 :
(ptr_dig==4)?1000 :
(ptr_dig==3)?100 :
(ptr_dig==2)?10 :
(ptr_dig==1)?1 : 0 ;
wire [27:0] dx = rest - Nd;
wire z = dx[27]; //
wire en_inc_dig = en_conv & q & !z; //
wire en_dec_ptr = en_conv & !q & z; //
always @(posedge clk) begin
q <= st ? 0 : en_conv ? !q : q; //q -
en_conv <= st ? 1 : (ptr_dig == 0) ? 0 : en_conv; //
rest <= st ? BIN : en_inc_dig ? dx : rest; //
ptr_dig <= st ? 8 : en_dec_ptr ? ptr_dig - 1 : ptr_dig; //
D8dec <= st ? 0 : ((ptr_dig == 8) & en_inc_dig) ? D8dec + 1 : D8dec;
D7dec <= st ? 0 : ((ptr_dig == 7) & en_inc_dig) ? D7dec + 1 : D7dec;
D6dec <= st ? 0 : ((ptr_dig == 6) & en_inc_dig) ? D6dec + 1 : D6dec;
D5dec <= st ? 0 : ((ptr_dig == 5) & en_inc_dig) ? D5dec + 1 : D5dec;
D4dec <= st ? 0 : ((ptr_dig == 4) & en_inc_dig) ? D4dec + 1 : D4dec;
D3dec <= st ? 0 : ((ptr_dig == 3) & en_inc_dig) ? D3dec + 1 : D3dec;
D2dec <= st ? 0 : ((ptr_dig == 2) & en_inc_dig) ? D2dec + 1 : D2dec;
D1dec <= st ? 0 : ((ptr_dig == 1) & en_inc_dig) ? D1dec + 1 : D1dec;
ok_conv <= st ? 0 : ((ptr_dig == 1) & en_dec_ptr);
DEC <= ok_conv ? {D8dec, D7dec, D6dec, D5dec, D4dec, D3dec, D2dec, D1dec} : DEC;
end
endmodule
| 6.780046 |
module Bin8Bcd10 (
input wire [7:0] b,
output reg [9:0] led
);
reg [17:0] z;
integer i;
always @(*) begin
for (i = 0; i <= 17; i = i + 1) z[i] = 0;
z[10:3] = b;
repeat (5) begin
if (z[11:8] > 4) z[11:8] = z[11:8] + 3;
if (z[15:12] > 4) z[15:12] = z[15:12] + 3;
z[17:1] = z[16:0];
end
led = z[17:8];
end
endmodule
| 6.569694 |
module bin8_to_bcd (
i_bin,
o_bcd
);
input [7:0] i_bin;
output reg [11:0] o_bcd;
integer i;
always @* begin
o_bcd = 0;
for (i = 0; i < 8; i = i + 1) begin
o_bcd = {o_bcd[10:0], i_bin[7-i]};
if (i < 7 && o_bcd[3:0] > 4) o_bcd[3:0] = o_bcd[3:0] + 3;
if (i < 7 && o_bcd[7:4] > 4) o_bcd[7:4] = o_bcd[7:4] + 3;
if (i < 7 && o_bcd[11:8] > 4) o_bcd[11:8] = o_bcd[11:8] + 3;
end
end
endmodule
| 6.948654 |
module bin8_to_bcd_DE10_Lite (
SW,
HEX0,
HEX1,
HEX2
);
input [9:0] SW;
output [6:0] HEX0, HEX1, HEX2;
wire [11:0] bcd;
bin8_to_bcd bin2bcd_inst (
.i_bin(SW[7:0]),
.o_bcd(bcd)
);
dec_7seg bcd0 (
.i_dat(bcd[3:0]),
.o_seg(HEX0)
);
dec_7seg bcd1 (
.i_dat(bcd[7:4]),
.o_seg(HEX1)
);
dec_7seg bcd2 (
.i_dat(bcd[11:8]),
.o_seg(HEX2)
);
endmodule
| 6.715793 |
module testbench;
parameter DELAY = 20;
reg [7:0] bin;
wire [11:0] bcd;
integer i;
bin8_to_bcd bin2bcd_inst (
.i_bin(bin),
.o_bcd(bcd)
);
initial begin
for (i = 0; i < 256; i = i + 1) begin
bin = i;
#DELAY;
end
$finish;
end
endmodule
| 7.015571 |
module binario_bcd (
binario,
unidade,
dezena,
centena,
milhar,
d_milhar,
c_milhar,
milhao,
d_milhao
);
input [31:0] binario;
output reg [3:0] unidade, dezena, centena, milhar, d_milhar, c_milhar, milhao, d_milhao;
integer i;
always @(binario) begin
unidade = 4'b0;
dezena = 4'b0;
centena = 4'b0;
milhar = 4'b0;
d_milhar = 4'b0;
c_milhar = 4'b0;
milhao = 4'b0;
d_milhao = 4'b0;
for (i = 31; i >= 0; i = i - 1) begin
if (unidade >= 5) unidade = unidade + 3;
if (dezena >= 5) dezena = dezena + 3;
if (centena >= 5) centena = centena + 3;
if (milhar >= 5) milhar = milhar + 3;
if (d_milhar >= 5) d_milhar = d_milhar + 3;
if (c_milhar >= 5) c_milhar = c_milhar + 3;
if (milhao >= 5) milhao = milhao + 3;
if (d_milhao >= 5) d_milhao = d_milhao + 3;
d_milhao = d_milhao << 1;
d_milhao[0] = milhao[3];
milhao = milhao << 1;
milhao[0] = c_milhar[3];
c_milhar = c_milhar << 1;
c_milhar[0] = d_milhar[3];
d_milhar = d_milhar << 1;
d_milhar[0] = milhar[3];
milhar = milhar << 1;
milhar[0] = centena[3];
centena = centena << 1;
centena[0] = dezena[3];
dezena = dezena << 1;
dezena[0] = unidade[3];
unidade = unidade << 1;
unidade[0] = binario[i];
end
end
endmodule
| 6.789979 |
module binarization (
input clk, // 时钟信号
input rst_n, // 复位信号，低电平有效
//图像处理前的数据接口
input pre_frame_vsync , // vsync信号
input pre_frame_hsync , // hsync信号
input pre_frame_de , // data enable信号
input [7:0] color ,
//图像处理后的数据接口
output post_frame_vsync, // vsync信号
output post_frame_hsync, // hsync信号
output post_frame_de , // data enable信号
output reg monoc , // monochrome（1=白，0=黑）
output monoc_fall
);
//reg define
reg monoc_d0;
reg pre_frame_vsync_d;
reg pre_frame_hsync_d;
reg pre_frame_de_d;
//*****************************************************
//** main code
//*****************************************************
assign monoc_fall = (!monoc) & monoc_d0; //当像素颜色由白变成黑的时候，这个信号拉高
assign post_frame_vsync = pre_frame_vsync_d;
assign post_frame_hsync = pre_frame_hsync_d;
assign post_frame_de = pre_frame_de_d;
//寄存以找下降沿
always @(posedge clk) begin
monoc_d0 <= monoc;
end
//二值化
always @(posedge clk or negedge rst_n) begin
if (!rst_n) monoc <= 1'd0;
else if (color > 8'd64) //阈值
monoc <= 1'd1;
else monoc <= 1'd0;
end
//延时2拍以同步时钟信号
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
pre_frame_vsync_d <= 1'd0;
pre_frame_hsync_d <= 1'd0;
pre_frame_de_d <= 1'd0;
end else begin
pre_frame_vsync_d <= pre_frame_vsync;
pre_frame_hsync_d <= pre_frame_hsync;
pre_frame_de_d <= pre_frame_de;
end
end
endmodule
| 8.748897 |
module std_mult_pipe (
mul_done,
out_tmp_reg,
Q,
clk,
E,
reset,
do_unsigned_mul_go_in,
rhs_read_data,
lhs_read_data
);
output mul_done;
output [15:0] out_tmp_reg;
output [15:0] Q;
input clk;
input [0:0] E;
input reset;
input do_unsigned_mul_go_in;
input [31:0] rhs_read_data;
input [31:0] lhs_read_data;
wire [0:0] E;
wire [15:0] Q;
wire clk;
wire do_unsigned_mul_go_in;
wire [31:0] lhs_read_data;
wire mul_done;
wire [15:0] out_tmp_reg;
wire reset;
wire [31:0] rhs_read_data;
std_fp_mult_pipe__parameterized0 comp (
.E(E),
.Q(Q),
.clk(clk),
.do_unsigned_mul_go_in(do_unsigned_mul_go_in),
.\done_buf_reg[2]_0 (mul_done),
.lhs_read_data(lhs_read_data),
.out_tmp_reg_0(out_tmp_reg),
.reset(reset),
.rhs_read_data(rhs_read_data)
);
endmodule
| 7.504255 |
module std_sdiv_pipe (
sdiv_done,
signed_mod_write_data,
signed_div_write_data,
SR,
signed_div_write_en,
reset_0,
\quotient_msk_reg[0] ,
Q,
done0,
clk,
E,
srhs_read_data,
slhs_read_data,
running_reg,
do_signed_div_mod_go_in,
\dividend_reg[3] ,
\dividend_reg[3]_0 ,
left_abs__2,
reset,
D
);
output sdiv_done;
output [3:0] signed_mod_write_data;
output [3:0] signed_div_write_data;
output [0:0] SR;
output signed_div_write_en;
output reset_0;
output [0:0] \quotient_msk_reg[0] ;
output [0:0] Q;
input done0;
input clk;
input [0:0] E;
input [3:0] srhs_read_data;
input [1:0] slhs_read_data;
input running_reg;
input do_signed_div_mod_go_in;
input \dividend_reg[3] ;
input \dividend_reg[3]_0 ;
input [1:0] left_abs__2;
input reset;
input [0:0] D;
wire \<const0> ;
wire [0:0] D;
wire [0:0] E;
wire [0:0] Q;
wire [0:0] SR;
wire clk;
wire different_signs__0;
wire \dividend_reg[3] ;
wire \dividend_reg[3]_0 ;
wire do_signed_div_mod_go_in;
wire done0;
wire [1:0] left_abs__2;
wire left_sign;
wire [0:0] \quotient_msk_reg[0] ;
wire reset;
wire reset_0;
wire [3:1] right_abs;
wire [3:0] right_save;
wire right_sign;
wire running_reg;
wire sdiv_done;
wire [3:0] signed_div_write_data;
wire signed_div_write_en;
wire [3:0] signed_mod_write_data;
wire [1:0] slhs_read_data;
wire [3:0] srhs_read_data;
GND GND (.G(\<const0> ));
std_div_pipe comp (
.D(D),
.E(\quotient_msk_reg[0] ),
.Q(right_save),
.SS(SR),
.clk(clk),
.different_signs__0(different_signs__0),
.\dividend_reg[3]_0 (\dividend_reg[3] ),
.\dividend_reg[3]_1 (\dividend_reg[3]_0 ),
.\divisor_reg[6]_0 (Q),
.do_signed_div_mod_go_in(do_signed_div_mod_go_in),
.done0(done0),
.done_reg_0(sdiv_done),
.left_abs__2(left_abs__2),
.left_sign(left_sign),
.reset(reset),
.reset_0(reset_0),
.right_sign(right_sign),
.running_reg_0(running_reg),
.signed_div_write_data(signed_div_write_data),
.signed_div_write_en(signed_div_write_en),
.signed_mod_write_data(signed_mod_write_data),
.slhs_read_data(slhs_read_data[0]),
.srhs_read_data(srhs_read_data)
);
FDRE left_sign_reg (
.C (clk),
.CE(E),
.D (slhs_read_data[1]),
.Q (left_sign),
.R (\<const0> )
);
LUT3 #(
.INIT(8'h6C)
) \right_save[1]_i_1 (
.I0(srhs_read_data[3]),
.I1(srhs_read_data[1]),
.I2(srhs_read_data[0]),
.O (right_abs[1])
);
(* SOFT_HLUTNM = "soft_lutpair235" *)
LUT4 #(
.INIT(16'h1FE0)
) \right_save[2]_i_1 (
.I0(srhs_read_data[1]),
.I1(srhs_read_data[0]),
.I2(srhs_read_data[3]),
.I3(srhs_read_data[2]),
.O (right_abs[2])
);
(* SOFT_HLUTNM = "soft_lutpair235" *)
LUT4 #(
.INIT(16'h0004)
) \right_save[3]_i_1 (
.I0(srhs_read_data[2]),
.I1(srhs_read_data[3]),
.I2(srhs_read_data[0]),
.I3(srhs_read_data[1]),
.O (right_abs[3])
);
FDRE \right_save_reg[0] (
.C (clk),
.CE(E),
.D (srhs_read_data[0]),
.Q (right_save[0]),
.R (\<const0> )
);
FDRE \right_save_reg[1] (
.C (clk),
.CE(E),
.D (right_abs[1]),
.Q (right_save[1]),
.R (\<const0> )
);
FDRE \right_save_reg[2] (
.C (clk),
.CE(E),
.D (right_abs[2]),
.Q (right_save[2]),
.R (\<const0> )
);
FDRE \right_save_reg[3] (
.C (clk),
.CE(E),
.D (right_abs[3]),
.Q (right_save[3]),
.R (\<const0> )
);
FDRE right_sign_reg (
.C (clk),
.CE(E),
.D (srhs_read_data[3]),
.Q (right_sign),
.R (\<const0> )
);
LUT2 #(
.INIT(4'h6)
) \signed_div_write_data[3]_INST_0_i_1 (
.I0(right_sign),
.I1(left_sign),
.O (different_signs__0)
);
endmodule
| 7.505299 |
module std_smult_pipe (
smul_done,
signed_mul_write_data,
clk,
do_signed_mul_go_in,
reset,
D,
\ltmp_reg[3] ,
E
);
output smul_done;
output [3:0] signed_mul_write_data;
input clk;
input do_signed_mul_go_in;
input reset;
input [3:0] D;
input [3:0] \ltmp_reg[3] ;
input [0:0] E;
wire [3:0] D;
wire [0:0] E;
wire clk;
wire do_signed_mul_go_in;
wire [3:0] \ltmp_reg[3] ;
wire reset;
wire [3:0] signed_mul_write_data;
wire smul_done;
std_fp_mult_pipe comp (
.D(D),
.E(E),
.clk(clk),
.do_signed_mul_go_in(do_signed_mul_go_in),
.\ltmp_reg[3]_0 (\ltmp_reg[3] ),
.reset(reset),
.signed_mul_write_data(signed_mul_write_data),
.smul_done(smul_done)
);
endmodule
| 6.968167 |
module std_sub (
out0,
a,
b
);
output [31:0] out0;
input [31:0] a;
input [31:0] b;
wire [31:0] a;
wire [31:0] b;
wire [31:0] out0;
lakeroad_xilinx_ultrascale_plus_sub32_2 _impl (
.a(a),
.b(b),
.out0(out0)
);
endmodule
| 6.592934 |
module std_mult_pipe (
mul_done,
out_tmp_reg,
Q,
clk,
E,
reset,
do_unsigned_mul_go_in,
rhs_read_data,
lhs_read_data
);
output mul_done;
output [15:0] out_tmp_reg;
output [15:0] Q;
input clk;
input [0:0] E;
input reset;
input do_unsigned_mul_go_in;
input [31:0] rhs_read_data;
input [31:0] lhs_read_data;
wire [0:0] E;
wire [15:0] Q;
wire clk;
wire do_unsigned_mul_go_in;
wire [31:0] lhs_read_data;
wire mul_done;
wire [15:0] out_tmp_reg;
wire reset;
wire [31:0] rhs_read_data;
std_fp_mult_pipe__parameterized0 comp (
.E(E),
.Q(Q),
.clk(clk),
.do_unsigned_mul_go_in(do_unsigned_mul_go_in),
.\done_buf_reg[2]_0 (mul_done),
.lhs_read_data(lhs_read_data),
.out_tmp_reg_0(out_tmp_reg),
.reset(reset),
.rhs_read_data(rhs_read_data)
);
endmodule
| 7.504255 |
module std_sdiv_pipe (
sdiv_done,
signed_mod_write_data,
signed_div_write_data,
SR,
signed_div_write_en,
reset_0,
\quotient_msk_reg[0] ,
Q,
done0,
clk,
E,
srhs_read_data,
slhs_read_data,
running_reg,
do_signed_div_mod_go_in,
\dividend_reg[3] ,
\dividend_reg[3]_0 ,
left_abs__2,
reset,
D
);
output sdiv_done;
output [3:0] signed_mod_write_data;
output [3:0] signed_div_write_data;
output [0:0] SR;
output signed_div_write_en;
output reset_0;
output [0:0] \quotient_msk_reg[0] ;
output [0:0] Q;
input done0;
input clk;
input [0:0] E;
input [3:0] srhs_read_data;
input [1:0] slhs_read_data;
input running_reg;
input do_signed_div_mod_go_in;
input \dividend_reg[3] ;
input \dividend_reg[3]_0 ;
input [1:0] left_abs__2;
input reset;
input [0:0] D;
wire \<const0> ;
wire [0:0] D;
wire [0:0] E;
wire [0:0] Q;
wire [0:0] SR;
wire clk;
wire different_signs__0;
wire \dividend_reg[3] ;
wire \dividend_reg[3]_0 ;
wire do_signed_div_mod_go_in;
wire done0;
wire [1:0] left_abs__2;
wire left_sign;
wire [0:0] \quotient_msk_reg[0] ;
wire reset;
wire reset_0;
wire [3:1] right_abs;
wire [3:0] right_save;
wire right_sign;
wire running_reg;
wire sdiv_done;
wire [3:0] signed_div_write_data;
wire signed_div_write_en;
wire [3:0] signed_mod_write_data;
wire [1:0] slhs_read_data;
wire [3:0] srhs_read_data;
GND GND (.G(\<const0> ));
std_div_pipe comp (
.D(D),
.E(\quotient_msk_reg[0] ),
.Q(right_save),
.SS(SR),
.clk(clk),
.different_signs__0(different_signs__0),
.\dividend_reg[3]_0 (\dividend_reg[3] ),
.\dividend_reg[3]_1 (\dividend_reg[3]_0 ),
.\divisor_reg[6]_0 (Q),
.do_signed_div_mod_go_in(do_signed_div_mod_go_in),
.done0(done0),
.done_reg_0(sdiv_done),
.left_abs__2(left_abs__2),
.left_sign(left_sign),
.reset(reset),
.reset_0(reset_0),
.right_sign(right_sign),
.running_reg_0(running_reg),
.signed_div_write_data(signed_div_write_data),
.signed_div_write_en(signed_div_write_en),
.signed_mod_write_data(signed_mod_write_data),
.slhs_read_data(slhs_read_data[0]),
.srhs_read_data(srhs_read_data)
);
FDRE left_sign_reg (
.C (clk),
.CE(E),
.D (slhs_read_data[1]),
.Q (left_sign),
.R (\<const0> )
);
LUT3 #(
.INIT(8'h6C)
) \right_save[1]_i_1 (
.I0(srhs_read_data[3]),
.I1(srhs_read_data[1]),
.I2(srhs_read_data[0]),
.O (right_abs[1])
);
(* SOFT_HLUTNM = "soft_lutpair235" *)
LUT4 #(
.INIT(16'h1FE0)
) \right_save[2]_i_1 (
.I0(srhs_read_data[1]),
.I1(srhs_read_data[0]),
.I2(srhs_read_data[3]),
.I3(srhs_read_data[2]),
.O (right_abs[2])
);
(* SOFT_HLUTNM = "soft_lutpair235" *)
LUT4 #(
.INIT(16'h0004)
) \right_save[3]_i_1 (
.I0(srhs_read_data[2]),
.I1(srhs_read_data[3]),
.I2(srhs_read_data[0]),
.I3(srhs_read_data[1]),
.O (right_abs[3])
);
FDRE \right_save_reg[0] (
.C (clk),
.CE(E),
.D (srhs_read_data[0]),
.Q (right_save[0]),
.R (\<const0> )
);
FDRE \right_save_reg[1] (
.C (clk),
.CE(E),
.D (right_abs[1]),
.Q (right_save[1]),
.R (\<const0> )
);
FDRE \right_save_reg[2] (
.C (clk),
.CE(E),
.D (right_abs[2]),
.Q (right_save[2]),
.R (\<const0> )
);
FDRE \right_save_reg[3] (
.C (clk),
.CE(E),
.D (right_abs[3]),
.Q (right_save[3]),
.R (\<const0> )
);
FDRE right_sign_reg (
.C (clk),
.CE(E),
.D (srhs_read_data[3]),
.Q (right_sign),
.R (\<const0> )
);
LUT2 #(
.INIT(4'h6)
) \signed_div_write_data[3]_INST_0_i_1 (
.I0(right_sign),
.I1(left_sign),
.O (different_signs__0)
);
endmodule
| 7.505299 |
module std_smult_pipe (
smul_done,
signed_mul_write_data,
clk,
do_signed_mul_go_in,
reset,
D,
\ltmp_reg[3] ,
E
);
output smul_done;
output [3:0] signed_mul_write_data;
input clk;
input do_signed_mul_go_in;
input reset;
input [3:0] D;
input [3:0] \ltmp_reg[3] ;
input [0:0] E;
wire [3:0] D;
wire [0:0] E;
wire clk;
wire do_signed_mul_go_in;
wire [3:0] \ltmp_reg[3] ;
wire reset;
wire [3:0] signed_mul_write_data;
wire smul_done;
std_fp_mult_pipe comp (
.D(D),
.E(E),
.clk(clk),
.do_signed_mul_go_in(do_signed_mul_go_in),
.\ltmp_reg[3]_0 (\ltmp_reg[3] ),
.reset(reset),
.signed_mul_write_data(signed_mul_write_data),
.smul_done(smul_done)
);
endmodule
| 6.968167 |
module std_sub (
out0,
a,
b
);
output [31:0] out0;
input [31:0] a;
input [31:0] b;
wire [31:0] a;
wire [31:0] b;
wire [31:0] out0;
lakeroad_xilinx_ultrascale_plus_sub32_2 _impl (
.a(a),
.b(b),
.out0(out0)
);
endmodule
| 6.592934 |
module std_mult_pipe (
mul_done,
out_tmp_reg,
Q,
clk,
E,
reset,
do_unsigned_mul_go_in,
rhs_read_data,
lhs_read_data
);
output mul_done;
output [15:0] out_tmp_reg;
output [15:0] Q;
input clk;
input [0:0] E;
input reset;
input do_unsigned_mul_go_in;
input [31:0] rhs_read_data;
input [31:0] lhs_read_data;
wire [0:0] E;
wire [15:0] Q;
wire clk;
wire do_unsigned_mul_go_in;
wire [31:0] lhs_read_data;
wire mul_done;
wire [15:0] out_tmp_reg;
wire reset;
wire [31:0] rhs_read_data;
std_fp_mult_pipe__parameterized0 comp (
.E(E),
.Q(Q),
.clk(clk),
.do_unsigned_mul_go_in(do_unsigned_mul_go_in),
.\done_buf_reg[2]_0 (mul_done),
.lhs_read_data(lhs_read_data),
.out_tmp_reg_0(out_tmp_reg),
.reset(reset),
.rhs_read_data(rhs_read_data)
);
endmodule
| 7.504255 |
module std_sdiv_pipe (
sdiv_done,
signed_mod_write_data,
signed_div_write_data,
SR,
signed_div_write_en,
reset_0,
\quotient_msk_reg[0] ,
Q,
done0,
clk,
E,
srhs_read_data,
slhs_read_data,
running_reg,
do_signed_div_mod_go_in,
\dividend_reg[3] ,
\dividend_reg[3]_0 ,
left_abs__2,
reset,
D
);
output sdiv_done;
output [3:0] signed_mod_write_data;
output [3:0] signed_div_write_data;
output [0:0] SR;
output signed_div_write_en;
output reset_0;
output [0:0] \quotient_msk_reg[0] ;
output [0:0] Q;
input done0;
input clk;
input [0:0] E;
input [3:0] srhs_read_data;
input [1:0] slhs_read_data;
input running_reg;
input do_signed_div_mod_go_in;
input \dividend_reg[3] ;
input \dividend_reg[3]_0 ;
input [1:0] left_abs__2;
input reset;
input [0:0] D;
wire \<const0> ;
wire [0:0] D;
wire [0:0] E;
wire [0:0] Q;
wire [0:0] SR;
wire clk;
wire different_signs__0;
wire \dividend_reg[3] ;
wire \dividend_reg[3]_0 ;
wire do_signed_div_mod_go_in;
wire done0;
wire [1:0] left_abs__2;
wire left_sign;
wire [0:0] \quotient_msk_reg[0] ;
wire reset;
wire reset_0;
wire [3:1] right_abs;
wire [3:0] right_save;
wire right_sign;
wire running_reg;
wire sdiv_done;
wire [3:0] signed_div_write_data;
wire signed_div_write_en;
wire [3:0] signed_mod_write_data;
wire [1:0] slhs_read_data;
wire [3:0] srhs_read_data;
GND GND (.G(\<const0> ));
std_div_pipe comp (
.D(D),
.E(\quotient_msk_reg[0] ),
.Q(right_save),
.SS(SR),
.clk(clk),
.different_signs__0(different_signs__0),
.\dividend_reg[3]_0 (\dividend_reg[3] ),
.\dividend_reg[3]_1 (\dividend_reg[3]_0 ),
.\divisor_reg[6]_0 (Q),
.do_signed_div_mod_go_in(do_signed_div_mod_go_in),
.done0(done0),
.done_reg_0(sdiv_done),
.left_abs__2(left_abs__2),
.left_sign(left_sign),
.reset(reset),
.reset_0(reset_0),
.right_sign(right_sign),
.running_reg_0(running_reg),
.signed_div_write_data(signed_div_write_data),
.signed_div_write_en(signed_div_write_en),
.signed_mod_write_data(signed_mod_write_data),
.slhs_read_data(slhs_read_data[0]),
.srhs_read_data(srhs_read_data)
);
FDRE left_sign_reg (
.C (clk),
.CE(E),
.D (slhs_read_data[1]),
.Q (left_sign),
.R (\<const0> )
);
LUT3 #(
.INIT(8'h6C)
) \right_save[1]_i_1 (
.I0(srhs_read_data[3]),
.I1(srhs_read_data[1]),
.I2(srhs_read_data[0]),
.O (right_abs[1])
);
(* SOFT_HLUTNM = "soft_lutpair235" *)
LUT4 #(
.INIT(16'h1FE0)
) \right_save[2]_i_1 (
.I0(srhs_read_data[1]),
.I1(srhs_read_data[0]),
.I2(srhs_read_data[3]),
.I3(srhs_read_data[2]),
.O (right_abs[2])
);
(* SOFT_HLUTNM = "soft_lutpair235" *)
LUT4 #(
.INIT(16'h0004)
) \right_save[3]_i_1 (
.I0(srhs_read_data[2]),
.I1(srhs_read_data[3]),
.I2(srhs_read_data[0]),
.I3(srhs_read_data[1]),
.O (right_abs[3])
);
FDRE \right_save_reg[0] (
.C (clk),
.CE(E),
.D (srhs_read_data[0]),
.Q (right_save[0]),
.R (\<const0> )
);
FDRE \right_save_reg[1] (
.C (clk),
.CE(E),
.D (right_abs[1]),
.Q (right_save[1]),
.R (\<const0> )
);
FDRE \right_save_reg[2] (
.C (clk),
.CE(E),
.D (right_abs[2]),
.Q (right_save[2]),
.R (\<const0> )
);
FDRE \right_save_reg[3] (
.C (clk),
.CE(E),
.D (right_abs[3]),
.Q (right_save[3]),
.R (\<const0> )
);
FDRE right_sign_reg (
.C (clk),
.CE(E),
.D (srhs_read_data[3]),
.Q (right_sign),
.R (\<const0> )
);
LUT2 #(
.INIT(4'h6)
) \signed_div_write_data[3]_INST_0_i_1 (
.I0(right_sign),
.I1(left_sign),
.O (different_signs__0)
);
endmodule
| 7.505299 |
module std_smult_pipe (
smul_done,
signed_mul_write_data,
clk,
do_signed_mul_go_in,
reset,
D,
\ltmp_reg[3] ,
E
);
output smul_done;
output [3:0] signed_mul_write_data;
input clk;
input do_signed_mul_go_in;
input reset;
input [3:0] D;
input [3:0] \ltmp_reg[3] ;
input [0:0] E;
wire [3:0] D;
wire [0:0] E;
wire clk;
wire do_signed_mul_go_in;
wire [3:0] \ltmp_reg[3] ;
wire reset;
wire [3:0] signed_mul_write_data;
wire smul_done;
std_fp_mult_pipe comp (
.D(D),
.E(E),
.clk(clk),
.do_signed_mul_go_in(do_signed_mul_go_in),
.\ltmp_reg[3]_0 (\ltmp_reg[3] ),
.reset(reset),
.signed_mul_write_data(signed_mul_write_data),
.smul_done(smul_done)
);
endmodule
| 6.968167 |
module std_sub (
out0,
a,
b
);
output [31:0] out0;
input [31:0] a;
input [31:0] b;
wire [31:0] a;
wire [31:0] b;
wire [31:0] out0;
lakeroad_xilinx_ultrascale_plus_sub32_2 _impl (
.a(a),
.b(b),
.out0(out0)
);
endmodule
| 6.592934 |
module std_mult_pipe (
mul_done,
out_tmp_reg,
Q,
clk,
E,
reset,
do_unsigned_mul_go_in,
rhs_read_data,
lhs_read_data
);
output mul_done;
output [15:0] out_tmp_reg;
output [15:0] Q;
input clk;
input [0:0] E;
input reset;
input do_unsigned_mul_go_in;
input [31:0] rhs_read_data;
input [31:0] lhs_read_data;
wire [0:0] E;
wire [15:0] Q;
wire clk;
wire do_unsigned_mul_go_in;
wire [31:0] lhs_read_data;
wire mul_done;
wire [15:0] out_tmp_reg;
wire reset;
wire [31:0] rhs_read_data;
std_fp_mult_pipe__parameterized0 comp (
.E(E),
.Q(Q),
.clk(clk),
.do_unsigned_mul_go_in(do_unsigned_mul_go_in),
.\done_buf_reg[2]_0 (mul_done),
.lhs_read_data(lhs_read_data),
.out_tmp_reg_0(out_tmp_reg),
.reset(reset),
.rhs_read_data(rhs_read_data)
);
endmodule
| 7.504255 |
module std_sdiv_pipe (
sdiv_done,
signed_mod_write_data,
signed_div_write_data,
SR,
signed_div_write_en,
reset_0,
\quotient_msk_reg[0] ,
Q,
done0,
clk,
E,
srhs_read_data,
slhs_read_data,
running_reg,
do_signed_div_mod_go_in,
\dividend_reg[3] ,
\dividend_reg[3]_0 ,
left_abs__2,
reset,
D
);
output sdiv_done;
output [3:0] signed_mod_write_data;
output [3:0] signed_div_write_data;
output [0:0] SR;
output signed_div_write_en;
output reset_0;
output [0:0] \quotient_msk_reg[0] ;
output [0:0] Q;
input done0;
input clk;
input [0:0] E;
input [3:0] srhs_read_data;
input [1:0] slhs_read_data;
input running_reg;
input do_signed_div_mod_go_in;
input \dividend_reg[3] ;
input \dividend_reg[3]_0 ;
input [1:0] left_abs__2;
input reset;
input [0:0] D;
wire \<const0> ;
wire [0:0] D;
wire [0:0] E;
wire [0:0] Q;
wire [0:0] SR;
wire clk;
wire different_signs__0;
wire \dividend_reg[3] ;
wire \dividend_reg[3]_0 ;
wire do_signed_div_mod_go_in;
wire done0;
wire [1:0] left_abs__2;
wire left_sign;
wire [0:0] \quotient_msk_reg[0] ;
wire reset;
wire reset_0;
wire [3:1] right_abs;
wire [3:0] right_save;
wire right_sign;
wire running_reg;
wire sdiv_done;
wire [3:0] signed_div_write_data;
wire signed_div_write_en;
wire [3:0] signed_mod_write_data;
wire [1:0] slhs_read_data;
wire [3:0] srhs_read_data;
GND GND (.G(\<const0> ));
std_div_pipe comp (
.D(D),
.E(\quotient_msk_reg[0] ),
.Q(right_save),
.SS(SR),
.clk(clk),
.different_signs__0(different_signs__0),
.\dividend_reg[3]_0 (\dividend_reg[3] ),
.\dividend_reg[3]_1 (\dividend_reg[3]_0 ),
.\divisor_reg[6]_0 (Q),
.do_signed_div_mod_go_in(do_signed_div_mod_go_in),
.done0(done0),
.done_reg_0(sdiv_done),
.left_abs__2(left_abs__2),
.left_sign(left_sign),
.reset(reset),
.reset_0(reset_0),
.right_sign(right_sign),
.running_reg_0(running_reg),
.signed_div_write_data(signed_div_write_data),
.signed_div_write_en(signed_div_write_en),
.signed_mod_write_data(signed_mod_write_data),
.slhs_read_data(slhs_read_data[0]),
.srhs_read_data(srhs_read_data)
);
FDRE left_sign_reg (
.C (clk),
.CE(E),
.D (slhs_read_data[1]),
.Q (left_sign),
.R (\<const0> )
);
LUT3 #(
.INIT(8'h6C)
) \right_save[1]_i_1 (
.I0(srhs_read_data[3]),
.I1(srhs_read_data[1]),
.I2(srhs_read_data[0]),
.O (right_abs[1])
);
(* SOFT_HLUTNM = "soft_lutpair235" *)
LUT4 #(
.INIT(16'h1FE0)
) \right_save[2]_i_1 (
.I0(srhs_read_data[1]),
.I1(srhs_read_data[0]),
.I2(srhs_read_data[3]),
.I3(srhs_read_data[2]),
.O (right_abs[2])
);
(* SOFT_HLUTNM = "soft_lutpair235" *)
LUT4 #(
.INIT(16'h0004)
) \right_save[3]_i_1 (
.I0(srhs_read_data[2]),
.I1(srhs_read_data[3]),
.I2(srhs_read_data[0]),
.I3(srhs_read_data[1]),
.O (right_abs[3])
);
FDRE \right_save_reg[0] (
.C (clk),
.CE(E),
.D (srhs_read_data[0]),
.Q (right_save[0]),
.R (\<const0> )
);
FDRE \right_save_reg[1] (
.C (clk),
.CE(E),
.D (right_abs[1]),
.Q (right_save[1]),
.R (\<const0> )
);
FDRE \right_save_reg[2] (
.C (clk),
.CE(E),
.D (right_abs[2]),
.Q (right_save[2]),
.R (\<const0> )
);
FDRE \right_save_reg[3] (
.C (clk),
.CE(E),
.D (right_abs[3]),
.Q (right_save[3]),
.R (\<const0> )
);
FDRE right_sign_reg (
.C (clk),
.CE(E),
.D (srhs_read_data[3]),
.Q (right_sign),
.R (\<const0> )
);
LUT2 #(
.INIT(4'h6)
) \signed_div_write_data[3]_INST_0_i_1 (
.I0(right_sign),
.I1(left_sign),
.O (different_signs__0)
);
endmodule
| 7.505299 |
module std_smult_pipe (
smul_done,
signed_mul_write_data,
clk,
do_signed_mul_go_in,
reset,
D,
\ltmp_reg[3] ,
E
);
output smul_done;
output [3:0] signed_mul_write_data;
input clk;
input do_signed_mul_go_in;
input reset;
input [3:0] D;
input [3:0] \ltmp_reg[3] ;
input [0:0] E;
wire [3:0] D;
wire [0:0] E;
wire clk;
wire do_signed_mul_go_in;
wire [3:0] \ltmp_reg[3] ;
wire reset;
wire [3:0] signed_mul_write_data;
wire smul_done;
std_fp_mult_pipe comp (
.D(D),
.E(E),
.clk(clk),
.do_signed_mul_go_in(do_signed_mul_go_in),
.\ltmp_reg[3]_0 (\ltmp_reg[3] ),
.reset(reset),
.signed_mul_write_data(signed_mul_write_data),
.smul_done(smul_done)
);
endmodule
| 6.968167 |
module std_sub (
out0,
a,
b
);
output [31:0] out0;
input [31:0] a;
input [31:0] b;
wire [31:0] a;
wire [31:0] b;
wire [31:0] out0;
lakeroad_xilinx_ultrascale_plus_sub32_2 _impl (
.a(a),
.b(b),
.out0(out0)
);
endmodule
| 6.592934 |
module std_fp_add #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left + right;
endmodule
| 9.124708 |
module std_fp_sub #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left - right;
endmodule
| 8.85803 |
module std_fp_mult_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16,
parameter SIGNED = 0
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
input logic go,
input logic clk,
input logic reset,
output logic [WIDTH-1:0] out,
output logic done
);
logic [ WIDTH-1:0] rtmp;
logic [ WIDTH-1:0] ltmp;
logic [(WIDTH << 1) - 1:0] out_tmp;
// Buffer used to walk through the 3 cycles of the pipeline.
logic done_buf[2:0];
assign done = done_buf[2];
assign out = out_tmp[(WIDTH<<1)-INT_WIDTH-1 : WIDTH-INT_WIDTH];
// If the done buffer is completely empty and go is high then execution
// just started.
logic start;
assign start = go & done_buf[0] == 0 & done_buf[1] == 0;
// Start sending the done signal.
always_ff @(posedge clk) begin
if (start) done_buf[0] <= 1;
else done_buf[0] <= 0;
end
// Push the done signal through the pipeline.
always_ff @(posedge clk) begin
if (go) begin
done_buf[2] <= done_buf[1];
done_buf[1] <= done_buf[0];
end else begin
done_buf[2] <= 0;
done_buf[1] <= 0;
end
end
// Move the multiplication computation through the pipeline.
always_ff @(posedge clk) begin
if (reset) begin
rtmp <= 0;
ltmp <= 0;
out_tmp <= 0;
end else if (go) begin
if (SIGNED) begin
rtmp <= $signed(right);
ltmp <= $signed(left);
out_tmp <= $signed({{WIDTH{ltmp[WIDTH-1]}}, ltmp} * {{WIDTH{rtmp[WIDTH-1]}}, rtmp});
end else begin
rtmp <= right;
ltmp <= left;
out_tmp <= ltmp * rtmp;
end
end else begin
rtmp <= 0;
ltmp <= 0;
out_tmp <= out_tmp;
end
end
endmodule
| 6.609331 |
module std_fp_div_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic go,
input logic clk,
input logic reset,
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out_remainder,
output logic [WIDTH-1:0] out_quotient,
output logic done
);
localparam ITERATIONS = WIDTH + FRAC_WIDTH;
logic [WIDTH-1:0] quotient, quotient_next;
logic [WIDTH:0] acc, acc_next;
logic [$clog2(ITERATIONS)-1:0] idx;
logic start, running, finished, dividend_is_zero;
assign start = go && !running;
assign dividend_is_zero = start && left == 0;
assign finished = idx == ITERATIONS - 1 && running;
always_ff @(posedge clk) begin
if (reset || finished || dividend_is_zero) running <= 0;
else if (start) running <= 1;
else running <= running;
end
always_comb begin
if (acc >= {1'b0, right}) begin
acc_next = acc - right;
{acc_next, quotient_next} = {acc_next[WIDTH-1:0], quotient, 1'b1};
end else begin
{acc_next, quotient_next} = {acc, quotient} << 1;
end
end
// `done` signaling
always_ff @(posedge clk) begin
if (dividend_is_zero || finished) done <= 1;
else done <= 0;
end
always_ff @(posedge clk) begin
if (running) idx <= idx + 1;
else idx <= 0;
end
always_ff @(posedge clk) begin
if (reset) begin
out_quotient <= 0;
out_remainder <= 0;
end else if (start) begin
out_quotient <= 0;
out_remainder <= left;
end else if (go == 0) begin
out_quotient <= out_quotient;
out_remainder <= out_remainder;
end else if (dividend_is_zero) begin
out_quotient <= 0;
out_remainder <= 0;
end else if (finished) begin
out_quotient <= quotient_next;
out_remainder <= out_remainder;
end else begin
out_quotient <= out_quotient;
if (right <= out_remainder) out_remainder <= out_remainder - right;
else out_remainder <= out_remainder;
end
end
always_ff @(posedge clk) begin
if (reset) begin
acc <= 0;
quotient <= 0;
end else if (start) begin
{acc, quotient} <= {{WIDTH{1'b0}}, left, 1'b0};
end else begin
acc <= acc_next;
quotient <= quotient_next;
end
end
endmodule
| 7.871496 |
module std_fp_gt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic out
);
assign out = left > right;
endmodule
| 8.426383 |
module std_fp_sadd #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left + right);
endmodule
| 8.768295 |
module std_fp_ssub #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left - right);
endmodule
| 8.839041 |
module std_fp_smult_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input [WIDTH-1:0] left,
input [WIDTH-1:0] right,
input logic reset,
input logic go,
input logic clk,
output logic [WIDTH-1:0] out,
output logic done
);
std_fp_mult_pipe #(
.WIDTH(WIDTH),
.INT_WIDTH(INT_WIDTH),
.FRAC_WIDTH(FRAC_WIDTH),
.SIGNED(1)
) comp (
.clk(clk),
.done(done),
.reset(reset),
.go(go),
.left(left),
.right(right),
.out(out)
);
endmodule
| 7.173413 |
module std_fp_sdiv_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input clk,
input go,
input reset,
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out_quotient,
output signed [WIDTH-1:0] out_remainder,
output logic done
);
logic signed [WIDTH-1:0]
left_abs, right_abs, comp_out_q, comp_out_r, right_save, out_rem_intermediate;
// Registers to figure out how to transform outputs.
logic different_signs, left_sign, right_sign;
// Latch the value of control registers so that their available after
// go signal becomes low.
always_ff @(posedge clk) begin
if (go) begin
right_save <= right_abs;
left_sign <= left[WIDTH-1];
right_sign <= right[WIDTH-1];
end else begin
left_sign <= left_sign;
right_save <= right_save;
right_sign <= right_sign;
end
end
assign right_abs = right[WIDTH-1] ? -right : right;
assign left_abs = left[WIDTH-1] ? -left : left;
assign different_signs = left_sign ^ right_sign;
assign out_quotient = different_signs ? -comp_out_q : comp_out_q;
// Remainder is computed as:
// t0 = |left| % |right|
// t1 = if left * right < 0 and t0 != 0 then |right| - t0 else t0
// rem = if right < 0 then -t1 else t1
assign out_rem_intermediate = different_signs & |comp_out_r ? $signed(
right_save - comp_out_r
) : comp_out_r;
assign out_remainder = right_sign ? -out_rem_intermediate : out_rem_intermediate;
std_fp_div_pipe #(
.WIDTH(WIDTH),
.INT_WIDTH(INT_WIDTH),
.FRAC_WIDTH(FRAC_WIDTH)
) comp (
.reset(reset),
.clk(clk),
.done(done),
.go(go),
.left(left_abs),
.right(right_abs),
.out_quotient(comp_out_q),
.out_remainder(comp_out_r)
);
endmodule
| 8.37227 |
module std_fp_sgt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed out
);
assign out = $signed(left > right);
endmodule
| 8.236193 |
module std_fp_slt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed out
);
assign out = $signed(left < right);
endmodule
| 8.595041 |
module std_mult_pipe #(
parameter WIDTH = 32
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
input logic reset,
input logic go,
input logic clk,
output logic [WIDTH-1:0] out,
output logic done
);
std_fp_mult_pipe #(
.WIDTH(WIDTH),
.INT_WIDTH(WIDTH),
.FRAC_WIDTH(0),
.SIGNED(0)
) comp (
.reset(reset),
.clk(clk),
.done(done),
.go(go),
.left(left),
.right(right),
.out(out)
);
endmodule
| 7.504255 |
module std_div_pipe #(
parameter WIDTH = 32
) (
input reset,
input clk,
input go,
input [WIDTH-1:0] left,
input [WIDTH-1:0] right,
output logic [WIDTH-1:0] out_remainder,
output logic [WIDTH-1:0] out_quotient,
output logic done
);
logic [WIDTH-1:0] dividend;
logic [(WIDTH-1)*2:0] divisor;
logic [WIDTH-1:0] quotient;
logic [WIDTH-1:0] quotient_msk;
logic start, running, finished, dividend_is_zero;
assign start = go && !running;
assign finished = quotient_msk == 0 && running;
assign dividend_is_zero = start && left == 0;
always_ff @(posedge clk) begin
// Early return if the divisor is zero.
if (finished || dividend_is_zero) done <= 1;
else done <= 0;
end
always_ff @(posedge clk) begin
if (reset || finished || dividend_is_zero) running <= 0;
else if (start) running <= 1;
else running <= running;
end
// Outputs
always_ff @(posedge clk) begin
if (dividend_is_zero || start) begin
out_quotient <= 0;
out_remainder <= 0;
end else if (finished) begin
out_quotient <= quotient;
out_remainder <= dividend;
end else begin
// Otherwise, explicitly latch the values.
out_quotient <= out_quotient;
out_remainder <= out_remainder;
end
end
// Calculate the quotient mask.
always_ff @(posedge clk) begin
if (start) quotient_msk <= 1 << WIDTH - 1;
else if (running) quotient_msk <= quotient_msk >> 1;
else quotient_msk <= quotient_msk;
end
// Calculate the quotient.
always_ff @(posedge clk) begin
if (start) quotient <= 0;
else if (divisor <= dividend) quotient <= quotient | quotient_msk;
else quotient <= quotient;
end
// Calculate the dividend.
always_ff @(posedge clk) begin
if (start) dividend <= left;
else if (divisor <= dividend) dividend <= dividend - divisor;
else dividend <= dividend;
end
always_ff @(posedge clk) begin
if (start) begin
divisor <= right << WIDTH - 1;
end else if (finished) begin
divisor <= 0;
end else begin
divisor <= divisor >> 1;
end
end
// Simulation self test against unsynthesizable implementation.
`ifdef VERILATOR
logic [WIDTH-1:0] l, r;
always_ff @(posedge clk) begin
if (go) begin
l <= left;
r <= right;
end else begin
l <= l;
r <= r;
end
end
always @(posedge clk) begin
if (done && $unsigned(out_remainder) != $unsigned(l % r))
$error(
"\nstd_div_pipe (Remainder): Computed and golden outputs do not match!\n",
"left: %0d",
$unsigned(
l
),
" right: %0d\n",
$unsigned(
r
),
"expected: %0d",
$unsigned(
l % r
),
" computed: %0d",
$unsigned(
out_remainder
)
);
if (done && $unsigned(out_quotient) != $unsigned(l / r))
$error(
"\nstd_div_pipe (Quotient): Computed and golden outputs do not match!\n",
"left: %0d",
$unsigned(
l
),
" right: %0d\n",
$unsigned(
r
),
"expected: %0d",
$unsigned(
l / r
),
" computed: %0d",
$unsigned(
out_quotient
)
);
end
`endif
endmodule
| 6.929139 |
module std_sadd #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left + right);
endmodule
| 8.670882 |
module std_ssub #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left - right);
endmodule
| 8.103836 |
module std_smult_pipe #(
parameter WIDTH = 32
) (
input logic reset,
input logic go,
input logic clk,
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output logic signed [WIDTH-1:0] out,
output logic done
);
std_fp_mult_pipe #(
.WIDTH(WIDTH),
.INT_WIDTH(WIDTH),
.FRAC_WIDTH(0),
.SIGNED(1)
) comp (
.reset(reset),
.clk(clk),
.done(done),
.go(go),
.left(left),
.right(right),
.out(out)
);
endmodule
| 6.968167 |
module std_sdiv_pipe #(
parameter WIDTH = 32
) (
input reset,
input clk,
input go,
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed [WIDTH-1:0] out_quotient,
output logic signed [WIDTH-1:0] out_remainder,
output logic done
);
logic signed [WIDTH-1:0]
left_abs, right_abs, comp_out_q, comp_out_r, right_save, out_rem_intermediate;
// Registers to figure out how to transform outputs.
logic different_signs, left_sign, right_sign;
// Latch the value of control registers so that their available after
// go signal becomes low.
always_ff @(posedge clk) begin
if (go) begin
right_save <= right_abs;
left_sign <= left[WIDTH-1];
right_sign <= right[WIDTH-1];
end else begin
left_sign <= left_sign;
right_save <= right_save;
right_sign <= right_sign;
end
end
assign right_abs = right[WIDTH-1] ? -right : right;
assign left_abs = left[WIDTH-1] ? -left : left;
assign different_signs = left_sign ^ right_sign;
assign out_quotient = different_signs ? -comp_out_q : comp_out_q;
// Remainder is computed as:
// t0 = |left| % |right|
// t1 = if left * right < 0 and t0 != 0 then |right| - t0 else t0
// rem = if right < 0 then -t1 else t1
assign out_rem_intermediate = different_signs & |comp_out_r ? $signed(
right_save - comp_out_r
) : comp_out_r;
assign out_remainder = right_sign ? -out_rem_intermediate : out_rem_intermediate;
std_div_pipe #(
.WIDTH(WIDTH)
) comp (
.reset(reset),
.clk(clk),
.done(done),
.go(go),
.left(left_abs),
.right(right_abs),
.out_quotient(comp_out_q),
.out_remainder(comp_out_r)
);
// Simulation self test against unsynthesizable implementation.
`ifdef VERILATOR
logic signed [WIDTH-1:0] l, r;
always_ff @(posedge clk) begin
if (go) begin
l <= left;
r <= right;
end else begin
l <= l;
r <= r;
end
end
always @(posedge clk) begin
if (done && out_quotient != $signed(l / r))
$error(
"\nstd_sdiv_pipe (Quotient): Computed and golden outputs do not match!\n",
"left: %0d",
l,
" right: %0d\n",
r,
"expected: %0d",
$signed(
l / r
),
" computed: %0d",
$signed(
out_quotient
),
);
if (done && out_remainder != $signed(((l % r) + r) % r))
$error(
"\nstd_sdiv_pipe (Remainder): Computed and golden outputs do not match!\n",
"left: %0d",
l,
" right: %0d\n",
r,
"expected: %0d",
$signed(
((l % r) + r) % r
),
" computed: %0d",
$signed(
out_remainder
),
);
end
`endif
endmodule
| 7.505299 |
module std_sgt #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left > right);
endmodule
| 7.663941 |
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