code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module binary2seven (
input [3:0] BIN,
output reg [0:6] SEV
);
always @(BIN)
case ({
BIN[3:0]
})
4'b0000: {SEV[0:6]} = 7'b0000001; //0
4'b0001: {SEV[0:6]} = 7'b1001111; //1
4'b0010: {SEV[0:6]} = 7'b0010010; //2
4'b0011: {SEV[0:6]} = 7'b0000110; //3
4'b0100: {SE... | 6.521798 |
module binaryAdderSubtractor_4_bit (
output [3:0] S,
output C4,
V,
input [3:0] A,
B,
input M
);
wire [3:1] C;
wire [3:0] W;
assign W = B ^ M;
fullAdder
FA0 (
S[0],
C[1],
A[0],
W[0],
M
),
FA1 (
S[1],
... | 7.406692 |
module binarycell (
en,
data,
rw,
clk,
out
);
input data, clk, rw, en;
output out;
wire set, reset, ffout;
assign set = data & en & ~rw;
assign reset = ~data & en & ~rw;
assign out = en & ffout & rw;
rsflipflop rsff (
set,
reset,
clk,
ffout
);
endmodul... | 8.053565 |
module BinaryCounter #(
parameter WIDTH = 64
) (
input clk,
enable,
reset_n,
output reg [WIDTH-1:0] count
);
// Reset if needed, or increment if counting is enabled
always @(posedge clk or negedge reset_n) begin
if (!reset_n) count <= 0;
else if (enable == 1'b1) count <= count + 1;
en... | 7.161712 |
module BinaryDisplay (
Ovalue // <i
);
input [7:0] Ovalue;
always @(*) begin
$display("Output = %d", Ovalue);
end
endmodule
| 8.830701 |
module BinaryImage(
iCLK,
iRST,
iDVAL,
iDATA,
oDATA,
oDVAL,
);
parameter threshold = 10'd190;
input iCLK;
input iRST;
input iDVAL;
input[9:0] iDATA;
output reg[9:0] oDATA;
output reg oDVAL;
always@(posedge iCLK or negedge iRST)
begin
if(!iRS... | 6.829797 |
module BinaryRepr (
input clock,
input reset,
input [ 7:0] io_uIn,
input [ 7:0] io_sIn,
input [ 9:0] io_fIn,
output io_uOut,
output io_sOut,
output io_fOut,
output [ 7:0] io_uDiv2,
output [ 7:0] io_sDiv2,
output [ 9:0] io_fDiv2,
out... | 7.252997 |
module BinaryToBCD (
number,
hundreds,
tens,
ones
);
// I/O Signal Definitions
input [7:0] number;
output reg [3:0] hundreds;
output reg [3:0] tens;
output reg [3:0] ones;
// Internal variable for storing bits
reg [19:0] shift;
integer i;
always @(number) begin
// Clear previous ... | 6.668578 |
module binarytogray (
clk,
reset,
binary_input,
gray_output
);
input clk, reset;
input [3:0] binary_input;
output gray_output;
reg [3:0] gray_output;
always @(posedge clk or posedge reset)
if (reset) begin
gray_output <= 4'b0;
end else begin
gray_output[3] <= binary_input[... | 6.858847 |
module BinaryToLEDDisplay (
input wire clk,
input wire rst,
input wire [15:0] value,
output wire [15:0] leds
);
assign leds = value;
//always @(posedge clk or posedge rst) begin
// if (rst) begin
//// leds = 0;
// end
//end
endmodule
| 8.593888 |
module binaryzation (
input clk,
input [11:0] pixel_gray,
output [11:0] pixel_binary
);
reg [11:0] pixel;
always @(posedge clk) begin
if (pixel_gray < 12'b0101_0101_0101) pixel <= 12'b0000_0000_0000;
else pixel <= 12'b1111_1111_1111;
end
assign pixel_binary = pixel;
endmodule
| 9.219348 |
module displayNumber (
input [3:0] decimalNumber,
output reg [0:6] displayer
);
always @(*)
case (decimalNumber)
4'b0000: displayer = 7'b0000001;
4'b0001: displayer = 7'b1001111;
4'b0010: displayer = 7'b0010010;
4'b0011: displayer = 7'b0000110;
4'b0100: displayer = 7'b1001100... | 8.666146 |
module binary_10_bits_BCD (
input [9:0] SW,
output [0:6] HEX0,
HEX1,
HEX2,
HEX3,
output [9:0] LEDR
);
assign LEDR = SW;
integer enteredInput, tenModulo, tenMultiple, hundredMultiple, thousandMultiple;
always @(SW[9:0]) enteredInput = SW[9:0];
reg [3:0] moduloTen, multipleTen, multip... | 6.70284 |
module Binary_to_Gray (
dout,
din
);
output [3:0] dout;
input [3:0] din;
//--solution 1--//
/*
assign dout[3] = din[3];
assign dout[2] = din[3]^din[2];
assign dout[1] = din[2]^din[1];
assign dout[0] = din[1]^din[0];
*/
//-- solution 2--//
assign dout = din ^ (din >> 1);
//--solution 3--//
/*... | 7.437129 |
module displayNumber (
input [3:0] decimalNumber,
output reg [0:6] displayer
);
always @(*)
case (decimalNumber)
4'b0000: displayer = 7'b0000001;
4'b0001: displayer = 7'b1001111;
4'b0010: displayer = 7'b0010010;
4'b0011: displayer = 7'b0000110;
4'b0100: displayer = 7'b1001100... | 8.666146 |
module binary_6_bits_BCD (
input [9:0] SW,
output [0:6] HEX0,
HEX1,
output [9:0] LEDR
);
assign LEDR = SW;
integer enteredInput, tenModulo, tenMultiple;
always @(SW[5:0]) enteredInput = SW[5:0];
reg [3:0] moduloBinary;
reg [3:0] multipleBinary;
always @(*) begin
tenModulo = enter... | 7.090007 |
module binary_7seg_converter (
input clk,
input [15:0] dispNum,
output reg [6:0] segments,
output reg [3:0] segsel
);
reg [6:0] decoder[0:15];
reg [1:0] seg_ctr = 2'b0;
reg [31:1] clk_dvdr = 0;
initial begin
$readmemb("nibble27seg_decoder", decoder);
end
always @(posedge clk) begin
... | 7.018841 |
module displayNumber (
input [3:0] decimalNumber,
output reg [0:6] displayer
);
always @(*)
case (decimalNumber)
4'b0000: displayer = 7'b0000001;
4'b0001: displayer = 7'b1001111;
4'b0010: displayer = 7'b0010010;
4'b0011: displayer = 7'b0000110;
4'b0100: displayer = 7'b1001100... | 8.666146 |
module binary_7_bits_BCD (
input [9:0] SW,
output [0:6] HEX0,
HEX1,
HEX2,
output [9:0] LEDR
);
assign LEDR = SW;
integer enteredInput, tenModulo, tenMultiple, hundredMultiple;
always @(SW[6:0]) enteredInput = SW[6:0];
reg [3:0] moduloTen, multipleTen, multipleHundred;
always @(*) beg... | 6.752796 |
module binary_8421 (
input wire clk, //系统时钟，频率50MHz
input wire rstn, //复位信号，低电平有效
input wire [19:0] data, //输入需要转换的数据
output reg [3:0] unit, //个位BCD码
output reg [3:0] ten, //十位BCD码
output reg [3:0] hun, //百位BCD码
output reg [3:0] tho, //千位BCD码
output reg [3:0... | 7.743115 |
module displayNumber (
input [3:0] decimalNumber,
output reg [0:6] displayer
);
always @(*)
case (decimalNumber)
4'b0000: displayer = 7'b0000001;
4'b0001: displayer = 7'b1001111;
4'b0010: displayer = 7'b0010010;
4'b0011: displayer = 7'b0000110;
4'b0100: displayer = 7'b1001100... | 8.666146 |
module binary_8_bits_BCD (
input [9:0] SW,
output [0:6] HEX0,
HEX1,
HEX2,
output [9:0] LEDR
);
assign LEDR = SW;
integer enteredInput, tenModulo, tenMultiple, hundredMultiple;
always @(SW[7:0]) enteredInput = SW[7:0];
reg [3:0] moduloTen, multipleTen, multipleHundred;
always @(*) beg... | 6.619261 |
module displayNumber (
input [3:0] decimalNumber,
output reg [0:6] displayer
);
always @(*)
case (decimalNumber)
4'b0000: displayer = 7'b0000001;
4'b0001: displayer = 7'b1001111;
4'b0010: displayer = 7'b0010010;
4'b0011: displayer = 7'b0000110;
4'b0100: displayer = 7'b1001100... | 8.666146 |
module tb_binary_array_multiplier_4bit ();
wire [7:0] out;
reg [3:0] x, y;
binary_array_multiplier_4bit uut (
out,
x,
y
);
initial begin
#00 x = 4'b1011;
y = 4'b1110;
#10 $finish;
end
initial begin
$dumpfile("binary_array_multiplier_4bit.vcd");
$dumpvars;
end
en... | 7.496605 |
module half_adder (
sum,
carry,
a,
b
);
output sum, carry;
input a, b;
assign sum = a ^ b;
assign carry = a & b;
endmodule
| 6.966406 |
module add_3 (
in,
out
);
input [3:0] in;
output [3:0] out;
reg [3:0] out;
always @(in)
case (in)
4'b0000: out <= 4'b0000;
4'b0001: out <= 4'b0001;
4'b0010: out <= 4'b0010;
4'b0011: out <= 4'b0011;
4'b0100: out <= 4'b0100;
4'b0101: out <= 4'b1000;
4'b0110: ... | 7.418891 |
module binary_BCD_4_bits (
input [3:0] SW,
output reg [0:6] HEX0,
HEX1
);
always @(SW)
case (SW[3:0])
0: begin
HEX0 = 7'b0000001;
HEX1 = 7'b0000001;
end
1: begin
HEX0 = 7'b1001111;
HEX1 = 7'b0000001;
end
2: begin
HEX0 = 7'b0010010;
... | 6.686256 |
module binary_bcd_4_bits_board (
input [3:0] SW,
output [6:0] HEX0,
output [6:0] HEX1
);
binary_BCD_4_bits(
SW, HEX0, HEX1
);
endmodule
| 8.169419 |
module binary_counter #(
parameter WIDTH = 16
) (
input clk,
enable,
reset,
output reg [WIDTH-1:0] count
);
// Reset if needed, or increment if counting is enabled
always @(posedge clk or posedge reset) begin
if (reset) count <= 0;
else if (enable == 1'b1) count <= count + 1;
end
end... | 6.540334 |
module d_ff_reset_en_tb;
reg clk;
reg reset;
wire [7:0] q;
wire max_tick;
binary_counter circuit1 (
clk,
reset,
q,
max_tick
);
always begin
clk = ~clk;
#10;
end
initial begin
$dumpfile("test.vcd");
$dumpvars(0, binary_counter);
clk <= 0;
reset <= ... | 6.62678 |
module binary_counter_virtex5_11_0_dfcd34dfb8805954 (
ce,
sinit,
clk,
q
) /* synthesis syn_black_box syn_noprune=1 */;
input ce;
input sinit;
input clk;
output [1 : 0] q;
// synthesis translate_off
wire \BU2/N0 ;
wire \BU2/thresh0 ;
wire NLW_VCC_P_UNCONNECTED;
wire NLW_GND_G_UNCONNE... | 6.540334 |
module accepts a binary input of the specified
* width and produces an output of 2^n width. If ACTIVE_HIGH
* is set to 1, the output will be one-hot, otherwise it
* will be one-cold. Due to the parametric nature of this decoder,
* the decoding is performed by shifting a single bit by the input
* value, rather th... | 8.776274 |
module binary_decoder_2x4 (
input en,
input [1:0] a,
output [3:0] bcode
);
assign bcode[0] = en && !a[1] && !a[0],
bcode[1] = en && !a[1] && a[0],
bcode[2] = en && a[1] && !a[0],
bcode[3] = en && a[1] && a[0];
endmodule
| 6.738522 |
module binary_decoder_2x4_TB;
// Inputs
reg en;
reg [1:0] a;
// Outputs
wire [3:0] bcode;
// Instantiate the Unit Under Test (UUT)
binary_decoder_2x4 uut (
.en(en),
.a(a),
.bcode(bcode)
);
reg [3:0] counter;
initial begin
$display("en a[1] a[0] bcode");
for (counter = 0;... | 6.738522 |
module binary_decoder_3x8 (
input [2:0] a,
output [7:0] bcode
);
binary_decoder_2x4 m0 (
.en({!a[2]}),
.a(a[1:0]),
.bcode(bcode[3:0])
);
binary_decoder_2x4 m1 (
.en(a[2]),
.a(a[1:0]),
.bcode(bcode[7:4])
);
endmodule
| 6.738522 |
module binary_decoder_3x8_TB;
// Inputs
reg [2:0] a;
// Outputs
wire [7:0] bcode;
// Instantiate the Unit Under Test (UUT)
binary_decoder_3x8 uut (
.a(a),
.bcode(bcode)
);
reg [3:0] counter;
initial begin
$display("a[2] a[1] a[0] bcode");
for (counter = 0; counter <= 7; counte... | 6.738522 |
module binary_decoder_4x16 (
input [ 3:0] a,
output [15:0] bcode
);
binary_decoder_2x4 m0 (
.en({!a[3] && !a[2]}),
.a(a[1:0]),
.bcode(bcode[3:0])
);
binary_decoder_2x4 m1 (
.en({!a[3] && a[2]}),
.a(a[1:0]),
.bcode(bcode[7:4])
);
binary_decoder_2x4 m2 (
.en(... | 6.738522 |
module binary_decoder_4x16_TB;
// Inputs
reg [ 3:0] a;
// Outputs
wire [15:0] bcode;
// Instantiate the Unit Under Test (UUT)
binary_decoder_4x16 uut (
.a(a),
.bcode(bcode)
);
reg [4:0] counter;
initial begin
$display("a[3] a[2] a[1] a[0] bcode");
for (counter = 0; counter <=... | 6.738522 |
modules/register_file_components/binary_decoder.v"
module binary_decoder_test;
reg [3:0]in;
reg load_enable;
wire [15:0] out;
binary_decoder decoder(out, in, load_enable);
initial #100 $finish;
initial fork
load_enable = 1'b0; #5 load_enable = 1'b1; #90 load_enable = 1'b0;
in... | 7.417915 |
module Binary_Gray #(
parameter N = 2
) (
i_Binary,
o_Gray
);
input wire [N-1:0] i_Binary;
output wire [N-1:0] o_Gray;
assign o_Gray = i_Binary ^ (i_Binary >> 1);
endmodule
| 8.894335 |
module binary_to_gray #(
parameter DATAWIDTH = 1
)(
input [DATAWIDTH-1:0] data_in,
output [DATAWIDTH-1:0] data_out;
);
assign data_out = data_in ^ (data_in >> 1);
endmodule
| 6.958902 |
module gray_to_binary #(
parameter DATAWIDTH = 1
)(
input [DATAWIDTH-1:0] data_in,
output [DATAWIDTH-1:0] data_out;
);
assign data_out[DATAWIDTH-1] = data_in[DATAWIDTH-1];
always @(*) begin
for (int i=DATAWIDTH-2 ; i>-1 ; i--)
data_out[i] = data_out[i+1] ^ data_in[i];
end... | 8.07018 |
module Binary_Gray_t ();
parameter N = 8;
reg [N-1:0] i_Binary;
wire [N-1:0] o_Gray;
Binary_Gray #(N) U1 (
i_Binary,
o_Gray
);
initial begin
#10 i_Binary = 8'b00101110;
end
endmodule
| 7.38161 |
module Binary_to_7Seg (
output reg [7:0] Y,
input [3:0] I
);
always @(I) begin
case (I)
4'b0000: Y = 7'b1111110;
4'b0001: Y = 7'b0110000;
4'b0010: Y = 7'b1101101;
4'b0011: Y = 7'b1111001;
4'b0100: Y = 7'b0110011;
4'b0101: Y = 7'b1011011;
4'b0110: Y = 7'b1011111;
... | 7.358073 |
module Binary_To_7Segment (
input i_Clk,
input [3:0] i_Binary_Num,
output o_Segment_A,
output o_Segment_B,
output o_Segment_C,
output o_Segment_D,
output o_Segment_E,
output o_Segment_F,
output o_Segment_G
);
reg [6:0] r_Hex_Encodi... | 7.259362 |
module binary_to_7_segment (
i,
D,
d,
ctrl
);
input [3:0] i; //i represents for 4-bit binary input
output [7:0] D; //ssd decoder
output [3:0] d; //LED controller
output [3:0] ctrl;
reg [7:0] D;
reg [3:0] d;
reg [3:0] ctrl;
always @* begin
case (i)
4'b0000: D = `SS_0;
4... | 7.316503 |
module binary_to_bcd1 (
clk_i,
ce_i,
rst_i,
start_i,
dat_binary_i,
dat_bcd_o,
done_o
);
parameter BITS_IN_PP = 32; // # of bits of binary input
parameter BCD_DIGITS_OUT_PP = 5; // # of digits of BCD output
parameter BIT_COUNT_WIDTH_PP = 16; // Width of bit counter
// I/O declarat... | 8.011872 |
module binary_to_bcd2 (
clk_i,
ce_i,
rst_i,
start_i,
dat_binary_i,
dat_bcd_o,
done_o
);
parameter BITS_IN_PP = 32; // # of bits of binary input
parameter BCD_DIGITS_OUT_PP = 6; // # of digits of BCD output
parameter BIT_COUNT_WIDTH_PP = 16; // Width of bit counter
// I/O declarat... | 8.011872 |
module binary_to_bcd_24bits (
input [23:0] binary,
output reg [3:0] reg_0,
output reg [3:0] reg_1,
output reg [3:0] reg_2,
output reg [3:0] reg_3,
output reg [3:0] reg_4,
output reg [3:0] reg_5,
output reg [3:0] reg_6,
output reg [3:0] reg_7
);
integer i;
always @(binary) begi... | 8.011872 |
module binary_to_bcd_core (
// signals
input wire clk,
input wire reset,
input wire start_conversion,
output reg end_of_conversion,
// data
input wire [7:0] binary_data, // 8-bit input binary value
output reg [11:0] bcd_data // 12-bit output bcd value
);
// state declarations
loc... | 8.011872 |
module binary_to_bcd_seq (
input [23:0] binary,
output reg [3:0] hundred_thousand,
output reg [3:0] ten_thousand,
output reg [3:0] thousand,
output reg [3:0] hundred,
output reg [3:0] ten,
output reg [3:0] one
);
integer i;
always @(binary) begin
hundred_thousand = 4'd0;
ten_t... | 8.011872 |
module binary_to_bcd_tb;
reg [31:0] ALUoutput;
wire [ 4:0] D1;
wire [ 4:0] D2;
wire [ 4:0] D3;
wire [ 4:0] D4;
wire [ 4:0] D5;
wire [ 4:0] D6;
wire [ 4:0] D7;
wire [ 4:0] D8;
wire [ 4:0] D9;
wire [ 4:0] D10;
sev_seg_disp disp1 (
.ALUoutput(ALUoutput),
.D1(D1),
.D2(D2),
... | 8.011872 |
module binary_to_bcd_transcoder #(
// Input word size.
parameter WIDTH = 8,
// Output word size. User should not change default value as it
// is derived from input width to fit all output BCD digits.
parameter OUT_WIDTH = $rtoi($ceil($log10(2 ** WIDTH - 1))) * 4
) (
// Input binary data.
in... | 8.011872 |
module binary_to_decimal (
input [15:0] in_binary,
output reg [15:0] out_decimal // 4 digits
);
localparam DIGITS = 4;
integer i;
integer scale;
reg [15:0] remainder_after_thousands;
reg [15:0] remainder_after_hundreds;
reg [15:0] remainder_after_tens;
/* Combinational Logic */
alway... | 8.149571 |
module Binary_to_Decimal_TB;
reg [3:0] Number;
wire [3:0] Dec;
integer i;
Binary_to_Decimal uut (
.Number(Number),
.Dec(Dec)
);
initial $monitor("Binary Number = %b | Decimal = %d", Number, Dec);
initial begin
Number = 0000;
for (i = 1; i < 16; i = i + 1) begin
#50 Number = Num... | 7.826153 |
module binary_to_gray (
input [3:0] B,
output [3:0] G
);
assign G[3] = B[3];
xor (G[2], B[3], B[2]);
xor (G[1], B[2], B[1]);
xor (G[0], B[1], B[0]);
endmodule
| 6.958902 |
module binary_to_hex_7segDecoder (
n,
hex_decoder
);
input [3:0] n; // 4 bit binary number
output [6:0] hex_decoder; // to display a single digit of hex number
assign hex_decoder[0] = ~((n[0] & n[2] & (~n[3])) | ((~n[0]) & (~n[2])) | ((~n[0]) & n[3]) | (n[1] & n[2]) | (n[1] & (~n[3])) | ((~n[1]) & (~n[... | 7.148154 |
module binary_to_hex_7segDecoder_BEHAVIOURAL (
num,
hex_decoder
);
input [3:0] num; // 4 bit binary number
output reg [6:0] hex_decoder; // to display a single digit of hex number
always @(*) begin
case (num)
4'b0000: hex_decoder = 7'b0111111; // 0
4'b0001: hex_decoder = 7'b0000110; //... | 7.148154 |
module binary_to_octal (
num,
hex_decoder
);
input [2:0] num;
output reg [6:0] hex_decoder;
always @(*) begin
case (num)
3'b000: hex_decoder = 7'b0111111; // 0
3'b001: hex_decoder = 7'b0000110; // 1
3'b010: hex_decoder = 7'b1011011; // 2
3'b011: hex_decoder = 7'b1001111;... | 8.021909 |
module binary_to_decimal (num, prev_left, prev_mid, hex_decoder);
input [3:0] num; // 4 bit binary number
input prev_left, prev_mid;
output reg [6:0] hex_decoder; // to display a single digit of hex number
wire carryin;
carryin = prev_mid & prev_left;
always @(*) begin
case(num)
4'b0000: hex_decoder = 7... | 8.149571 |
module binary_to_hex_decoder (
cc,
HEXX
);
input [3:0] cc;
output [6:0] HEXX;
//integer HEX;
wire [3:0] c;
assign c = cc;
assign HEXX = HEX;
reg [6:0] HEX;
always @(c)
case (c)
4'b0000: begin
HEX[0] = 0;
HEX[1] = 0;
HEX[2] = 0;
HEX[3] = 0;
HEX[4... | 7.148154 |
module binary_to_hex_decoder_1_bit (
input x,
output reg [0:6] h
);
always @(x)
case (x)
0: h = 7'b1000000;
1: h = 7'b1111001;
endcase
endmodule
| 7.148154 |
module Binary_to_onehot (
dat1,
result1
);
parameter wid = 4;
parameter result_wid = 16;
input [wid-1:0] dat1;
output [result_wid -1:0] result1;
assign result1 = 1'b1 << dat1;
endmodule
| 7.192815 |
module Binary_to_onehot_tb ();
localparam wid = 4;
localparam result_wid = 16;
integer i;
reg [wid-1:0] dat1;
wire [result_wid-1:0] result1;
Binary_to_onehot dut (
dat1,
result1
);
initial begin
for (i = 0; i < 16; i = i + 1) begin
dat1 = i;
#5;
end
end
initial ... | 7.192815 |
module binary_to_seg7 (
output reg [6:0] S,
input [1:0] I
);
always @(I) begin
case (I)
2'b00: S = 7'b1111100;
2'b01: S = 7'b0110000;
2'b10: S = 7'b1101101;
2'b11: S = 7'b1111001;
endcase
end
endmodule
| 6.681969 |
module binary_up_counter (
clk,
rst,
b
);
input clk, rst;
output [3:0] b;
wire clk_out;
reg [3:0] b;
reg [3:0] b_temp;
frequency_divider_exact_1hz(
.clk(clk), .rst(rst), .clk_out(clk_out)
);
always @* begin
b_temp = b + 1'b1;
end
always @(posedge clk_out or negedge rst) beg... | 6.586672 |
module binbcd4 (
input wire [3:0] b,
output wire [4:0] p
);
assign p[4] = b[3] & b[2] | b[3] & b[1];
assign p[3] = b[3] & ~b[2] & ~b[1];
assign p[2] = ~b[3] & b[2] | b[2] & b[1];
assign p[1] = b[3] & b[2] & ~b[1] | ~b[3] & b[1];
assign p[0] = b[0];
endmodule
| 6.502157 |
module binbcd8 (
input wire [7:0] b,
output reg [9:0] p
);
reg [17:0] z;
integer i;
always @(*) begin
for (i = 0; i <= 17; i = i + 1) z[i] = 0;
z[10:3] = b;
repeat (5) begin
if (z[11:8] > 4) z[11:8] = z[11:8] + 3;
if (z[15:12] > 4) z[15:12] = z[15:12] + 3;
z[17:1] = z[16:0]... | 6.582155 |
module binbcd8_top (
input wire clk,
input wire btn,
input wire [7:0] sw,
input wire [7:0] ld,
output wire [6:0] a_to_g,
output wire [3:0] an,
output wire dp
);
wire [15:0] x;
wire [ 9:0] p;
//串联0和binbcd8的输出
assign x = {6'b000000, p};
//在LED上显示开关的二进制值
assign ld = sw;
//在7段数码管上... | 8.300688 |
module bincnt (
out, //counter output
clk, // clock
rst_n //active low reset
);
output [`CNT_BIT_WIDTH-1:0] out; // counter output
input clk; // clock
input rst_n; //active low reset
reg [`CNT_BIT_WIDTH-1:0] out; // counter output
reg [`CNT_BIT_WIDTH-1:0] tmp_cnt;
always @(out) tmp_cnt... | 6.559836 |
module binConv #(
parameter input_width = 25,
parameter popcount_width = 5
) (
input [input_width-1:0] recField,
input [input_width-1:0] weights,
input [popcount_width-1:0] thresh,
input [1:0] sign,
output outmap
);
wire [input_width-1:0] xnor_out;
wire [popcount_width-1:0] popcount_out;... | 7.307653 |
module binenc
#(parameter n = `DEFAULT_WIDTH)
(input [n-1:0] in,
output [$clog2(n)-1:0] out);
wire [$clog2(n)-1:0] o[n:0];
wire [n:0] found;
assign o[n] = 0;
assign found[n] = 0;
assign out = o[0];
generate
genvar i;
for (i = n - 1; i >= 0; i = i - 1)
begin
as... | 6.816267 |
module binenc_tb;
reg [7:0] in;
wire [2:0] out;
binenc #(8) enc (
.in (in),
.out(out)
);
integer i;
initial begin
$monitor("%b %d", in, out);
in = 'b0;
#255 $finish;
end
always #1 in = in + 1;
endmodule
| 6.56182 |
module bing (
input [ 3:0] a,
input [25:0] b,
output [31:0] c
);
assign c = {a, b, 2'b00}; //ڽPC31~28λλinstruct_indexϲ32λַ
endmodule
| 8.21404 |
module add_N_tb ();
// note this only runs for 50 cycles with the below settings
// alter TB_TIMEOUT to run longer
localparam TB_TIMEOUT = 100000;
localparam TB_CLK_PERIOD = 2000;
localparam TB_RST_PERIOD = 4000;
initial #(TB_TIMEOUT) $finish();
// clock
reg tb_clk = 1'b0;
always #(TB_CLK_PERIOD / ... | 6.93342 |
module binops (
in_1,
in_2,
or_o,
nor_o,
and_o,
nand_o,
xor_o,
xnor_o,
add_o,
sub_o,
mul_o,
//div_o,
equ_o,
neq_o,
gt_o,
lt_o,
geq_o,
leq_o
);
input [`BITS-1:0] in_1, in_2;
output [`BITS-1:0] or_o, nor_o, and_o, nand_o, xor_o, xnor_o, add... | 6.506344 |
module binParaBCD (
input [25:0] bin,
output reg [3:0] dezmilhao,
output reg [3:0] milhao,
output reg [3:0] cemmil,
output reg [3:0] dezmil,
output reg [3:0] mil,
output reg [3:0] cem,
output reg [3:0] dez,
output reg [3:0] um
);
integer i;
always @(bin) begin
dezmilhao = ... | 7.023857 |
module topModule (
In,
Clk,
Seg_sel,
Seg_data,
Seg_debug,
LED_on,
Reset
);
input [11:0] In;
input Clk;
input Reset;
output [3:0] Seg_sel;
output [7:0] Seg_data;
// debug output
output [3:0] Seg_debug;
output LED_on;
assign LED_on = 1;
wire [3:0] bcd1, bcd2, bcd3;
... | 7.37158 |
module bcd2SevSeg (
in,
out
);
input [3:0] in;
output reg [7:0] out;
always @(*) begin
case (in)
0: out = 8'b00111111;
1: out = 8'b00000110;
2: out = 8'b01011011;
3: out = 8'b01001111;
4: out = 8'b01100110;
5: out = 8'b01101101;
6: out = 8'b01111101;
... | 6.749872 |
module switch (
clk,
bin1,
bin2,
bin3,
bin4,
seg_data,
seg_sel,
seg_debug,
reset
);
input clk;
input reset;
input [7:0] bin1;
input [7:0] bin2;
input [7:0] bin3;
input [7:0] bin4;
output reg [3:0] seg_debug;
output reg [3:0] seg_sel; //= 4'b0001;
output reg [7:0]... | 6.864438 |
module binto7seg(
input clk,
input [3:0] binary,
output reg [6:0] seg
);
always @(posedge clk)
case (binary)
4'b0000 : //Hexadecimal 0
seg = 7'b1000000;
4'b0001 : //Hexadecimal 1
seg = 7'b1111001;
4'b0010 : // Hexadecimal 2
seg = 7'b0100100;
4'b0011 : // Hexadecimal 3
seg = 7'b0110000;
4'b... | 6.934714 |
module BinToBCD (
Bin,
BCD
); //ת3BCD
integer i;
//
input [31:0] Bin; //Ķ
output [31:0] BCD; //ʮBCD
reg [3:0] Thousands, Hundreds, Tens, Ones; //3BCD
assign BCD = {Thousands, Hundreds, Tens, Ones};
always @(Bin) begin
Thousands = 4'd0;
Hundreds = 4'd0;
Tens = 4'd0;
Ones = 4'd0;... | 6.501169 |
module BinToBCD_8bit (
input [7:0] bin,
output reg [7:0] bcd
);
reg [7:0] binin;
always @bin begin
binin = bin;
bcd[3:0] = binin % 10;
binin = binin / 10;
bcd[7:4] = binin % 10;
end
endmodule
| 7.073231 |
module BinToBCD_m2 (
input [7:0] bin_in,
input sampling,
input clk,
input rst,
output flag,
output [9:0] bcd_out
);
reg [17:0] bcd_out_r;
reg [17:0] tmp_bcd_out_r;
reg [ 5:0] counter;
assign bcd_out = (counter == 5'd15) ? bcd_out_r[17:8] : 'b0;
assign fla... | 6.821071 |
module add (
input [3:0] in,
output reg [3:0] out
);
always @(in)
case (in)
4'b0000: out <= 4'b0000;
4'b0001: out <= 4'b0001;
4'b0010: out <= 4'b0010;
4'b0011: out <= 4'b0011;
4'b0100: out <= 4'b0100;
4'b0101: out <= 4'b1000;
4'b0110: out <= 4'b1001;
4'b011... | 6.686118 |
module bintogray #(
parameter w = 8
) (
bin_i,
gray_o
);
input [w-1:0] bin_i;
output [w-1:0] gray_o;
assign gray_o = (bin_i >> 1) ^ bin_i;
/*assign gray_o[w-1]=bin_i[w-1];
genvar i;
for(i=w-1;i>=0;i--)
assign gray_o[i]=bin_i[i]^bin_i[i+1]*/
endmodule
| 6.889043 |
module Bin2HexConverter (
input wire clk,
input wire reset,
input wire bottom,
// bottom input port
output reg [7:0] to_7_seg_n,
// controlling 7 segment LED to display numbers
output wire [3:0] to_7_seg_sel_n
// control signal connecting to 7 segment LED selection ... | 8.278035 |
module BinToBCD (
input wire clk,
nrst,
input wire start,
output reg valid,
input [27:0] bin,
output reg [47:0] bcd,
output reg [47:0] x
);
reg [27:0] bin_in;
reg op;
reg [3:0] cnt;
always @(posedge clk or negedge nrst) begin
if (nrst == 0) bin_in <= 0;
else if (start) bin_i... | 6.501169 |
module Bin_2_7Seg_Disp (
input [3:0] B,
output reg [6:0] a_2_g
);
always @(*) begin
case (B)
4'b0000: a_2_g = 7'h3f;
4'b0001: a_2_g = 7'h86;
4'b0010: a_2_g = 7'h5b;
4'b0011: a_2_g = 7'h4f;
4'b0100: a_2_g = 7'h66;
4'b0101: a_2_g = 7'h6d;
4'b0110: a_2_g = 7'h7d;
... | 7.211302 |
module Bin_Add_4bit (
a0,
a1,
a2,
a3,
b0,
b1,
b2,
b3,
cin,
c0,
c1,
c2,
c3,
cout
);
input wire a0;
input wire a1;
input wire a2;
input wire a3;
input wire b0;
input wire b1;
input wire b2;
input wire b3;
input wire cin;
output wire c0;
outpu... | 6.893303 |
module top (
//input [3:0] A, B, C, D,
input [12:0] number,
input reset,
input clk,
output [3:0] anode,
output [6:0] seg
);
wire [3:0] A, B, C, D;
bcd bcd (
.number(number),
.thousands(D),
.hundreds(C),
.tens(B),
.ones(A)
);
bcdto7segmentclocked bcdto7se... | 6.966747 |
module bcdto7segmentclocked (
input [3:0] A,
B,
C,
D,
input reset,
input clk,
output [3:0] anode,
output [6:0] seg
);
wire [3:0] x;
wire [3:0] an;
wire [1:0] sel;
wire clk_div;
bcdto7segment_dataflow bcdto7segment (
.x(x),
.an(an),
.anode(anode),
.seg(s... | 7.120176 |
module bcdto7segment_dataflow (
input [3:0] x,
input [3:0] an,
output [3:0] anode,
output reg [6:0] seg
);
//reg [6:0] seg;
assign anode = an;
always @(x or an)
case (x)
0: seg = 7'b0000001;
1: seg = 7'b1001111;
2: seg = 7'b0010010;
3: seg = 7'b0000110;
4: seg =... | 7.120176 |
module mux16to4 (
input [3:0] A,
input [3:0] B,
input [3:0] C,
input [3:0] D,
input [1:0] sel,
output reg [3:0] S
);
always @(A, B, C, D, sel)
case (sel)
0: S = A;
1: S = B;
2: S = C;
3: S = D;
default: S = 0;
endcase
endmodule
| 7.78955 |
module demux4to1 (
input [1:0] sel,
output reg A,
output reg B,
output reg C,
output reg D
);
always @(sel)
case (sel)
0: {D, C, B, A} = ~(4'b0001);
1: {D, C, B, A} = ~(4'b0010);
2: {D, C, B, A} = ~(4'b0100);
3: {D, C, B, A} = ~(4'b1000);
default: {D, C, B, A} = ~... | 7.031285 |
module ClkDivider (
input clk,
input rst,
output reg clk_div
);
localparam constantNumber = 50000; //f=1kHz f=100MHz/(2*constantNumber)
//localparam constantNumber = 25000000;//f=2Hz f=100MHz/(2*constantNumber)
reg [31:0] count;
always @(posedge (clk), posedge (rst)) begin
if (rst == 1'b1)... | 6.643482 |
module = 256, with reverse counting direction.
*/
module bin_counter(i_clk, i_rst, i_mode, o_cnt);
input i_clk; // clock signal
input i_rst; // reset -> i_clear
input i_mode; // 0 - normal mode, 1 - reverse -> i_up_dwn
output reg [7:0] o_cnt; // 0...15
always @(posedge i_clk) begin // synchr reset... | 6.500676 |
module bin_counter_tb3 ();
// declaration
localparam T = 20; // clock period
wire clk, reset;
wire syn_clr, load, en, up;
wire [2:0] d;
wire max_tick, min_tick;
wire [2:0] q;
// uut instantiation
univ_bin_counter #(
.N(3)
) uut (
.clk(clk),
.reset(reset),
.syn_clr(syn_clr... | 7.092307 |
module bdd (
input [3:0] binary,
input enable,
input reset,
output reg [6:0] hex
);
always @(*)
if (~reset) hex <= 7'b1111111;
else if (enable) begin
case (binary)
4'h0: hex <= 7'b1000000;
4'h1: hex <= 7'b1111001;
4'h2: hex <= 7'b0100100;
4'h3: hex <= 7'b... | 7.501913 |
module oh_bin2bin #(
parameter DW = 32 // width of data inputs
) (
input [DW-1:0] in,
output [DW-1:0] out
);
wire [DW-1:0] interm;
oh_bin2gray #(
.DW(DW)
) rd_b2g (
.out(interm),
.in (in)
);
oh_gray2bin #(
.DW(DW)
) rd_g2b (
.out(out),
.in (interm)
);
... | 8.106791 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.