code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sky130_fd_sc_hvl__o22ai_1 (
Y,
A1,
A2,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A1;
input A2;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__o22ai_1 (
Y,
A1,
A2,
B1,
B2
);
output Y;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__o22ai base (
.Y (Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__o22a_1 (
X,
A1,
A2,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1;
input A2;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__o22a_1 (
X,
A1,
A2,
B1,
B2
);
output X;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__o22a base (
.X (X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__or2 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire or0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
or0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__or2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A);
buf buf0 (X, or0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__or2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__or2 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire or0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
or0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__or2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A);
buf buf0 (X, or0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__or2 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__or2 (
//# {{data|Data Signals}}
input A,
input B,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__or2 (
//# {{data|Data Signals}}
input A,
input B,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__or2_1 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__or2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__or3 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire or0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A, C);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
or0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__or3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A, C);
buf buf0 (X, or0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__or3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__or3 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire or0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A, C);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
or0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__or3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A, C);
buf buf0 (X, or0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__or3 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__or3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__or3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__or3_1 (
X,
A,
B,
C,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input C;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__or3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__or3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__or3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__probec_p (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
buf0_out_X,
VPWR,
VGND
);
buf buf1 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__probec_p (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__probec_p (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__probec_p (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
buf0_out_X,
VPWR,
VGND
);
buf buf1 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__probec_p (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__probec_p (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__probec_p (
//# {{data|Data Signals}}
input A,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__probec_p (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__probec_p_8 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__probec_p base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__probec_p_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__probec_p base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__probe_p (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
buf0_out_X,
VPWR,
VGND
);
buf buf1 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__probe_p (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__probe_p (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__probe_p (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
buf0_out_X,
VPWR,
VGND
);
buf buf1 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__probe_p (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__probe_p (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__probe_p (
//# {{data|Data Signals}}
input A,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__probe_p (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__probe_p_8 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__probe_p base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__probe_p_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__probe_p base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__schmittbuf (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
buf0_out_X,
VPWR,
VGND
);
buf buf1 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__schmittbuf (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__schmittbuf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__schmittbuf (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
buf0_out_X,
VPWR,
VGND
);
buf buf1 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__schmittbuf (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__schmittbuf (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__schmittbuf (
//# {{data|Data Signals}}
input A,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__schmittbuf (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__schmittbuf_1 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__schmittbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__schmittbuf_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__schmittbuf base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfrbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire RESET;
wire mux_out;
reg notifier;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire RESET_B_delayed;
wire CLK_delayed;
wire buf0_out_Q;
wire not1_out_qn;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign cond0 = (RESET_B_delayed === 1'b1);
assign cond1 = ((SCE_delayed === 1'b0) & cond0);
assign cond2 = ((SCE_delayed === 1'b1) & cond0);
assign cond3 = ((D_delayed !== SCD_delayed) & cond0);
buf buf0 (buf0_out_Q, buf_Q);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
Q,
buf0_out_Q,
VPWR,
VGND
);
not not1 (not1_out_qn, buf_Q);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (
Q_N,
not1_out_qn,
VPWR,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfrbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
RESET_B
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire RESET;
wire mux_out;
reg notifier;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire RESET_B_delayed;
wire CLK_delayed;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign cond0 = (RESET_B_delayed === 1'b1);
assign cond1 = ((SCE_delayed === 1'b0) & cond0);
assign cond2 = ((SCE_delayed === 1'b1) & cond0);
assign cond3 = ((D_delayed !== SCD_delayed) & cond0);
buf buf0 (Q, buf_Q);
not not1 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfrbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
RESET_B
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
wire buf0_out_Q ;
wire not1_out_qn;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out , D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET, , VPWR, VGND);
buf buf0 (buf0_out_Q , buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
not not1 (not1_out_qn, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (Q_N , not1_out_qn, VPWR, VGND );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfrbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfrbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfrbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfrbp_1 (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfrbp_1 (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
RESET_B
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfrtp (
Q,
CLK,
D,
SCD,
SCE,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire RESET;
wire mux_out;
reg notifier;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire RESET_B_delayed;
wire CLK_delayed;
wire buf0_out_Q;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign cond0 = (RESET_B_delayed === 1'b1);
assign cond1 = ((SCE_delayed === 1'b0) & cond0);
assign cond2 = ((SCE_delayed === 1'b1) & cond0);
assign cond3 = ((D_delayed !== SCD_delayed) & cond0);
buf buf0 (buf0_out_Q, buf_Q);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
Q,
buf0_out_Q,
VPWR,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfrtp (
Q,
CLK,
D,
SCD,
SCE,
RESET_B
);
// Module ports
output Q;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire RESET;
wire mux_out;
reg notifier;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire RESET_B_delayed;
wire CLK_delayed;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign cond0 = (RESET_B_delayed === 1'b1);
assign cond1 = ((SCE_delayed === 1'b0) & cond0);
assign cond2 = ((SCE_delayed === 1'b1) & cond0);
assign cond3 = ((D_delayed !== SCD_delayed) & cond0);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfrtp (
Q,
CLK,
D,
SCD,
SCE,
RESET_B
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
wire buf0_out_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out , D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET, , VPWR, VGND);
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET);
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfrtp (
Q,
CLK,
D,
SCD,
SCE,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfrtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfrtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfrtp_1 (
Q,
CLK,
D,
SCD,
SCE,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfrtp_1 (
Q,
CLK,
D,
SCD,
SCE,
RESET_B
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfsbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire SET;
wire mux_out;
reg notifier;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire SET_B_delayed;
wire CLK_delayed;
wire buf0_out_Q;
wire not1_out_qn;
// Name Output Other arguments
not not0 (SET, SET_B_delayed);
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
SET,
notifier,
VPWR,
VGND
);
assign cond0 = (SET_B_delayed === 1'b1);
assign cond1 = ((SCE_delayed === 1'b0) & cond0);
assign cond2 = ((SCE_delayed === 1'b1) & cond0);
assign cond3 = ((D_delayed !== SCD_delayed) & cond0);
buf buf0 (buf0_out_Q, buf_Q);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
Q,
buf0_out_Q,
VPWR,
VGND
);
not not1 (not1_out_qn, buf_Q);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (
Q_N,
not1_out_qn,
VPWR,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfsbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
SET_B
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire SET;
wire mux_out;
reg notifier;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire SET_B_delayed;
wire CLK_delayed;
// Name Output Other arguments
not not0 (SET, SET_B_delayed);
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
SET,
notifier,
VPWR,
VGND
);
assign cond0 = (SET_B_delayed === 1'b1);
assign cond1 = ((SCE_delayed === 1'b0) & cond0);
assign cond2 = ((SCE_delayed === 1'b1) & cond0);
assign cond3 = ((D_delayed !== SCD_delayed) & cond0);
buf buf0 (Q, buf_Q);
not not1 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfsbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
SET_B
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
wire buf0_out_Q ;
wire not1_out_qn;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out , D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET, , VPWR, VGND);
buf buf0 (buf0_out_Q , buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
not not1 (not1_out_qn, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (Q_N , not1_out_qn, VPWR, VGND );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfsbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfsbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{control|Control Signals}}
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfsbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{control|Control Signals}}
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfsbp_1 (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfsbp_1 (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
SET_B
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfstp (
Q,
CLK,
D,
SCD,
SCE,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire SET;
wire mux_out;
reg notifier;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire SET_B_delayed;
wire CLK_delayed;
wire buf0_out_Q;
// Name Output Other arguments
not not0 (SET, SET_B_delayed);
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
SET,
notifier,
VPWR,
VGND
);
assign cond0 = (SET_B_delayed === 1'b1);
assign cond1 = ((SCE_delayed === 1'b0) & cond0);
assign cond2 = ((SCE_delayed === 1'b1) & cond0);
assign cond3 = ((D_delayed !== SCD_delayed) & cond0);
buf buf0 (buf0_out_Q, buf_Q);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
Q,
buf0_out_Q,
VPWR,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfstp (
Q,
CLK,
D,
SCD,
SCE,
SET_B
);
// Module ports
output Q;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire SET;
wire mux_out;
reg notifier;
wire cond0;
wire cond1;
wire cond2;
wire cond3;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire SET_B_delayed;
wire CLK_delayed;
// Name Output Other arguments
not not0 (SET, SET_B_delayed);
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
SET,
notifier,
VPWR,
VGND
);
assign cond0 = (SET_B_delayed === 1'b1);
assign cond1 = ((SCE_delayed === 1'b0) & cond0);
assign cond2 = ((SCE_delayed === 1'b1) & cond0);
assign cond3 = ((D_delayed !== SCD_delayed) & cond0);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfstp (
Q,
CLK,
D,
SCD,
SCE,
SET_B
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
wire buf0_out_Q;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out , D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET, , VPWR, VGND);
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET);
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfstp (
Q,
CLK,
D,
SCD,
SCE,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfstp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfstp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfstp_1 (
Q,
CLK,
D,
SCD,
SCE,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfstp_1 (
Q,
CLK,
D,
SCD,
SCE,
SET_B
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfxbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire mux_out;
reg notifier;
wire cond1;
wire cond2;
wire cond3;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire buf0_out_Q;
wire not0_out_qn;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
notifier,
VPWR,
VGND
);
assign cond1 = (SCE_delayed === 1'b0);
assign cond2 = (SCE_delayed === 1'b1);
assign cond3 = (D_delayed !== SCD_delayed);
buf buf0 (buf0_out_Q, buf_Q);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
Q,
buf0_out_Q,
VPWR,
VGND
);
not not0 (not0_out_qn, buf_Q);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (
Q_N,
not0_out_qn,
VPWR,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfxbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire mux_out;
reg notifier;
wire cond1;
wire cond2;
wire cond3;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
notifier,
VPWR,
VGND
);
assign cond1 = (SCE_delayed === 1'b0);
assign cond2 = (SCE_delayed === 1'b1);
assign cond3 = (D_delayed !== SCD_delayed);
buf buf0 (Q, buf_Q);
not not0 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfxbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfxbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
wire buf0_out_Q ;
wire not0_out_qn;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out , D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (buf0_out_Q , buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
not not0 (not0_out_qn, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (Q_N , not0_out_qn, VPWR, VGND );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfxbp (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfxbp (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.