code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sky130_fd_sc_hvl__sdfxbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfxbp (
//# {{data|Data Signals}}
input D,
output Q,
output Q_N,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfxbp_1 (
Q,
Q_N,
CLK,
D,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfxbp_1 (
Q,
Q_N,
CLK,
D,
SCD,
SCE
);
output Q;
output Q_N;
input CLK;
input D;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__sdfxbp base (
.Q (Q),
.Q_N(Q_N),
.CLK(CLK),
.D (D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfxtp (
Q,
CLK,
D,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input CLK;
input D;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire mux_out;
reg notifier;
wire cond1;
wire cond2;
wire cond3;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire buf0_out_Q;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
notifier,
VPWR,
VGND
);
assign cond1 = (SCE_delayed === 1'b0);
assign cond2 = (SCE_delayed === 1'b1);
assign cond3 = (D_delayed !== SCD_delayed);
buf buf0 (buf0_out_Q, buf_Q);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
Q,
buf0_out_Q,
VPWR,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfxtp (
Q,
CLK,
D,
SCD,
SCE
);
// Module ports
output Q;
input CLK;
input D;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire mux_out;
reg notifier;
wire cond1;
wire cond2;
wire cond3;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N dff0 (
buf_Q,
mux_out,
CLK_delayed,
notifier,
VPWR,
VGND
);
assign cond1 = (SCE_delayed === 1'b0);
assign cond2 = (SCE_delayed === 1'b1);
assign cond3 = (D_delayed !== SCD_delayed);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfxtp (
Q,
CLK,
D,
SCD,
SCE
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfxtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
wire buf0_out_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out , D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfxtp (
Q ,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfxtp (
Q,
CLK,
D,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfxtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfxtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfxtp_1 (
Q,
CLK,
D,
SCD,
SCE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdfxtp_1 (
Q,
CLK,
D,
SCD,
SCE
);
output Q;
input CLK;
input D;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__sdfxtp base (
.Q (Q),
.CLK(CLK),
.D (D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdlclkp (
GCLK,
SCE,
GATE,
CLK,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output GCLK;
input SCE;
input GATE;
input CLK;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire m0;
wire m0n;
wire clkn;
wire CLK_delayed;
wire SCE_delayed;
wire GATE_delayed;
wire SCE_gate_delayed;
wire GCLK_b;
reg notifier;
wire awake;
wire SCE_awake;
wire GATE_awake;
// Name Output Other arguments
not not0 (m0n, m0);
not not1 (clkn, CLK_delayed);
nor nor0 (SCE_gate_delayed, GATE_delayed, SCE_delayed);
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (
m0,
SCE_gate_delayed,
clkn,
notifier,
VPWR,
VGND
);
and and0 (GCLK_b, m0n, CLK_delayed);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
GCLK,
GCLK_b,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign SCE_awake = ((GATE_delayed === 1'b0) & awake);
assign GATE_awake = ((SCE_delayed === 1'b0) & awake);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdlclkp (
GCLK,
SCE,
GATE,
CLK
);
// Module ports
output GCLK;
input SCE;
input GATE;
input CLK;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire m0;
wire m0n;
wire clkn;
wire CLK_delayed;
wire SCE_delayed;
wire GATE_delayed;
wire SCE_gate_delayed;
wire GCLK_b;
reg notifier;
wire awake;
wire SCE_awake;
wire GATE_awake;
// Name Output Other arguments
not not0 (m0n, m0);
not not1 (clkn, CLK_delayed);
nor nor0 (SCE_gate_delayed, GATE_delayed, SCE_delayed);
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (
m0,
SCE_gate_delayed,
clkn,
notifier,
VPWR,
VGND
);
and and0 (GCLK_b, m0n, CLK_delayed);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
GCLK,
GCLK_b,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign SCE_awake = ((GATE_delayed === 1'b0) & awake);
assign GATE_awake = ((SCE_delayed === 1'b0) & awake);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdlclkp (
GCLK,
SCE,
GATE,
CLK
);
output GCLK;
input SCE;
input GATE;
input CLK;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdlclkp (
GCLK,
SCE,
GATE,
CLK,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output GCLK;
input SCE;
input GATE;
input CLK;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire m0;
wire m0n;
wire clkn;
wire SCE_GATE;
wire GCLK_b;
// Name Output Other arguments
not not0 (m0n, m0);
not not1 (clkn, CLK);
nor nor0 (SCE_GATE, GATE, SCE);
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (
m0,
SCE_GATE,
clkn
,,
VPWR,
VGND
);
and and0 (GCLK_b, m0n, CLK);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
GCLK,
GCLK_b,
VPWR,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdlclkp (
GCLK,
SCE,
GATE,
CLK
);
// Module ports
output GCLK;
input SCE;
input GATE;
input CLK;
// Local signals
wire m0;
wire m0n;
wire clkn;
wire SCE_GATE;
// Name Output Other arguments
not not0 (m0n, m0);
not not1 (clkn, CLK);
nor nor0 (SCE_GATE, GATE, SCE);
sky130_fd_sc_hvl__udp_dlatch$P dlatch0 (
m0,
SCE_GATE,
clkn
);
and and0 (GCLK, m0n, CLK);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdlclkp (
GCLK,
SCE,
GATE,
CLK,
VPWR,
VGND,
VPB,
VNB
);
output GCLK;
input SCE;
input GATE;
input CLK;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdlclkp (
//# {{scanchain|Scan Chain}}
input SCE,
//# {{clocks|Clocking}}
input CLK,
input GATE,
output GCLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdlclkp (
//# {{scanchain|Scan Chain}}
input SCE,
//# {{clocks|Clocking}}
input CLK,
input GATE,
output GCLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdlclkp_1 (
GCLK,
SCE,
GATE,
CLK,
VPWR,
VGND,
VPB,
VNB
);
output GCLK;
input SCE;
input GATE;
input CLK;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__sdlclkp base (
.GCLK(GCLK),
.SCE (SCE),
.GATE(GATE),
.CLK (CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdlclkp_1 (
GCLK,
SCE,
GATE,
CLK
);
output GCLK;
input SCE;
input GATE;
input CLK;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__sdlclkp base (
.GCLK(GCLK),
.SCE (SCE),
.GATE(GATE),
.CLK (CLK)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdlxtp (
Q,
D,
SCD,
SCE,
GATE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input D;
input SCD;
input SCE;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire GATE_delayed;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire cond0;
wire cond1;
wire cond2;
reg notifier;
wire mux_out;
wire buf0_out_Q;
// Name Output Other arguments
assign cond0 = (SCE_delayed === 1'b0);
assign cond1 = (SCE_delayed === 1'b1);
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (
buf_Q,
mux_out,
GATE_delayed,
notifier,
VPWR,
VGND
);
buf buf0 (buf0_out_Q, buf_Q);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
Q,
buf0_out_Q,
VPWR,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdlxtp (
Q,
D,
SCD,
SCE,
GATE
);
// Module ports
output Q;
input D;
input SCD;
input SCE;
input GATE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire GATE_delayed;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire cond0;
wire cond1;
wire cond2;
reg notifier;
wire mux_out;
// Name Output Other arguments
assign cond0 = (SCE_delayed === 1'b0);
assign cond1 = (SCE_delayed === 1'b1);
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (
mux_out,
D_delayed,
SCD_delayed,
SCE_delayed
);
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (
buf_Q,
mux_out,
GATE_delayed,
notifier,
VPWR,
VGND
);
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdlxtp (
Q,
D,
SCD,
SCE,
GATE
);
output Q;
input D;
input SCD;
input SCE;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdlxtp (
Q ,
D ,
SCD ,
SCE ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input SCD ;
input SCE ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_out ;
wire buf_Q ;
wire buf0_out_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out , D, SCD, SCE );
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , mux_out, GATE, , VPWR, VGND);
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdlxtp (
Q ,
D ,
SCD ,
SCE ,
GATE
);
// Module ports
output Q ;
input D ;
input SCD ;
input SCE ;
input GATE;
// Local signals
wire mux_out;
wire buf_Q ;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hvl__udp_dlatch$P `UNIT_DELAY dlatch0 (buf_Q , mux_out, GATE );
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdlxtp (
Q,
D,
SCD,
SCE,
GATE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input D;
input SCD;
input SCE;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdlxtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input GATE,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdlxtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input GATE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdlxtp_1 (
Q,
D,
SCD,
SCE,
GATE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input D;
input SCD;
input SCE;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__sdlxtp base (
.Q(Q),
.D(D),
.SCD(SCD),
.SCE(SCE),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__sdlxtp_1 (
Q,
D,
SCD,
SCE,
GATE
);
output Q;
input D;
input SCD;
input SCE;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__sdlxtp base (
.Q(Q),
.D(D),
.SCD(SCD),
.SCE(SCE),
.GATE(GATE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_dff$P (
Q,
D,
CLK
);
output Q;
input D;
input CLK;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_dff$P (
//# {{data|Data Signals}}
input D,
output Q,
//# {{clocks|Clocking}}
input CLK
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_dff$PR (
Q,
D,
CLK,
RESET
);
output Q;
input D;
input CLK;
input RESET;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_dff$PR (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET,
//# {{clocks|Clocking}}
input CLK
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N (
Q,
D,
CLK,
RESET,
NOTIFIER,
VPWR,
VGND
);
output Q;
input D;
input CLK;
input RESET;
input NOTIFIER;
input VPWR;
input VGND;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input NOTIFIER,
input VPWR,
input VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_dff$PS (
Q,
D,
CLK,
SET
);
output Q;
input D;
input CLK;
input SET;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_dff$PS (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input SET,
//# {{clocks|Clocking}}
input CLK
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N (
Q,
D,
CLK,
SET,
NOTIFIER,
VPWR,
VGND
);
output Q;
input D;
input CLK;
input SET;
input NOTIFIER;
input VPWR;
input VGND;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input SET,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input NOTIFIER,
input VPWR,
input VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_dff$P_pp$PG$N (
Q,
D,
CLK,
NOTIFIER,
VPWR,
VGND
);
output Q;
input D;
input CLK;
input NOTIFIER;
input VPWR;
input VGND;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_dff$P_pp$PG$N (
//# {{data|Data Signals}}
input D,
output Q,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input NOTIFIER,
input VPWR,
input VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_dlatch$P (
Q,
D,
GATE
);
output Q;
input D;
input GATE;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_dlatch$P (
//# {{data|Data Signals}}
input D,
output Q,
//# {{clocks|Clocking}}
input GATE
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_dlatch$PR (
Q,
D,
GATE,
RESET
);
output Q;
input D;
input GATE;
input RESET;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_dlatch$PR (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET,
//# {{clocks|Clocking}}
input GATE
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_dlatch$PR_pp$PG$N (
Q,
D,
GATE,
RESET,
NOTIFIER,
VPWR,
VGND
);
output Q;
input D;
input GATE;
input RESET;
input NOTIFIER;
input VPWR;
input VGND;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_dlatch$PR_pp$PG$N (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET,
//# {{clocks|Clocking}}
input GATE,
//# {{power|Power}}
input NOTIFIER,
input VPWR,
input VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N (
Q,
D,
GATE,
NOTIFIER,
VPWR,
VGND
);
output Q;
input D;
input GATE;
input NOTIFIER;
input VPWR;
input VGND;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N (
//# {{data|Data Signals}}
input D,
output Q,
//# {{clocks|Clocking}}
input GATE,
//# {{power|Power}}
input NOTIFIER,
input VPWR,
input VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_isolatchhv_pp$PLG$S (
UDP_OUT,
UDP_IN,
VPWR,
LVPWR,
VGND,
SLEEP
);
output UDP_OUT;
input UDP_IN;
input VPWR;
input LVPWR;
input VGND;
input SLEEP;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_isolatchhv_pp$PLG$S (
//# {{data|Data Signals}}
input UDP_IN,
output UDP_OUT,
//# {{power|Power}}
input SLEEP,
input LVPWR,
input VPWR,
input VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_mux_2to1 (
X,
A0,
A1,
S
);
output X;
input A0;
input A1;
input S;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_mux_2to1 (
//# {{data|Data Signals}}
input A0,
input A1,
output X,
//# {{control|Control Signals}}
input S
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_mux_4to2 (
X,
A0,
A1,
A2,
A3,
S0,
S1
);
output X;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_mux_4to2 (
//# {{data|Data Signals}}
input A0,
input A1,
input A2,
input A3,
output X,
//# {{control|Control Signals}}
input S0,
input S1
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_pwrgood_pp$G (
UDP_OUT,
UDP_IN,
VGND
);
output UDP_OUT;
input UDP_IN;
input VGND;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_pwrgood_pp$G (
//# {{data|Data Signals}}
input UDP_IN,
output UDP_OUT,
//# {{power|Power}}
input VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_pwrgood_pp$P (
UDP_OUT,
UDP_IN,
VPWR
);
output UDP_OUT;
input UDP_IN;
input VPWR;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_pwrgood_pp$P (
//# {{data|Data Signals}}
input UDP_IN,
output UDP_OUT,
//# {{power|Power}}
input VPWR
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_pwrgood_pp$PG (
UDP_OUT,
UDP_IN,
VPWR,
VGND
);
output UDP_OUT;
input UDP_IN;
input VPWR;
input VGND;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__udp_pwrgood_pp$PG (
//# {{data|Data Signals}}
input UDP_IN,
output UDP_OUT,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__xnor2 (
Y,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire xnor0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
xnor0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__xnor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire xnor0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B);
buf buf0 (Y, xnor0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__xnor2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__xnor2 (
Y,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire xnor0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
xnor0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__xnor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire xnor0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B);
buf buf0 (Y, xnor0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__xnor2 (
Y,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__xnor2 (
//# {{data|Data Signals}}
input A,
input B,
output Y,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__xnor2 (
//# {{data|Data Signals}}
input A,
input B,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__xnor2_1 (
Y,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__xnor2_1 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__xor2 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire xor0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, B, A);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
xor0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__xor2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, B, A);
buf buf0 (X, xor0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__xor2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__xor2 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire xor0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, B, A);
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
xor0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__xor2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, B, A);
buf buf0 (X, xor0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__xor2 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__xor2 (
//# {{data|Data Signals}}
input A,
input B,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__xor2 (
//# {{data|Data Signals}}
input A,
input B,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__xor2_1 (
X,
A,
B,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hvl__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hvl__xor2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hvl__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_ms__dlclkp_1 (
input GATE,
input CLK,
output GCLK
);
endmodule
| 7.212805 |
module sky130_fd_sc_ms__dlclkp_2 (
input GATE,
input CLK,
output GCLK
);
endmodule
| 7.212805 |
module sky130_fd_sc_ms__dlclkp_4 (
input GATE,
input CLK,
output GCLK
);
endmodule
| 7.212805 |
module \$adffe (ARST, CLK, D, EN, Q);
parameter ARST_POLARITY =1'b1;
parameter ARST_VALUE =1'b0;
parameter CLK_POLARITY =1'b1;
parameter EN_POLARITY =1'b1;
parameter WIDTH =1;
input ARST, CLK, EN;
input [WIDTH -1 :0] D;
output [WIDTH -1 :0] Q;
wire GCLK;
generate
if (WIDTH < 5) begin
sky130_fd_sc_ms__dlclkp_1 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
end
else if (WIDTH < 17) begin
sky130_fd_sc_ms__dlclkp_2 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
end
else begin
sky130_fd_sc_ms__dlclkp_4 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
end
endgenerate
$adff #(
.WIDTH(WIDTH),
.CLK_POLARITY(CLK_POLARITY),
.ARST_VALUE(ARST_VALUE) ,
.ARST_POLARITY (ARST_POLARITY)
)
flipflop(
.CLK(GCLK),
.ARST(ARST),
.D(D),
.Q(Q)
);
endmodule
| 7.72891 |
module \$dffe ( CLK, D, EN, Q);
parameter CLK_POLARITY =1'b1;
parameter EN_POLARITY =1'b1;
parameter WIDTH =1;
input CLK, EN;
input [WIDTH -1:0] D;
output [WIDTH -1:0] Q;
wire GCLK;
generate
if (WIDTH < 5) begin
sky130_fd_sc_ms__dlclkp_1 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
end
else if (WIDTH < 17) begin
sky130_fd_sc_ms__dlclkp_2 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
end
else begin
sky130_fd_sc_ms__dlclkp_4 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
end
endgenerate
$dff #(
.WIDTH(WIDTH),
.CLK_POLARITY(CLK_POLARITY),
)
flipflop(
.CLK(GCLK),
.D(D),
.Q(Q)
);
endmodule
| 7.215766 |
module \$dffsre ( CLK, EN, CLR, SET, D, Q);
parameter CLK_POLARITY =1'b1;
parameter EN_POLARITY =1'b1;
parameter CLR_POLARITY =1'b1;
parameter SET_POLARITY =1'b1;
parameter WIDTH =1;
input CLK, EN, CLR, SET;
input [WIDTH -1:0] D;
output [WIDTH -1:0] Q;
wire GCLK;
generate
if (WIDTH < 5) begin
sky130_fd_sc_ms__dlclkp_1 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
end
else if (WIDTH < 17) begin
sky130_fd_sc_ms__dlclkp_2 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
end
else begin
sky130_fd_sc_ms__dlclkp_4 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
end
endgenerate
$dffsr #(
.WIDTH(WIDTH),
.CLK_POLARITY(CLK_POLARITY),
.CLR_POLARITY(CLR_POLARITY),
.SET_POLARITY(SET_POLARITY)
)
flipflop(
.CLK(GCLK),
.CLR(CLR),
.SET(SET),
.D(D),
.Q(Q)
);
endmodule
| 7.063232 |
module \$aldffe ( CLK, EN, ALOAD, AD, D, Q);
parameter CLK_POLARITY =1'b1;
parameter EN_POLARITY =1'b1;
parameter ALOAD_POLARITY =1'b1;
parameter WIDTH =1;
input CLK, EN, ALOAD;
input [WIDTH -1:0] D;
input [WIDTH-1:0] AD;
output [WIDTH -1:0] Q;
wire GCLK;
generate
if (WIDTH < 5) begin
sky130_fd_sc_ms__dlclkp_1 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
end
else if (WIDTH < 17) begin
sky130_fd_sc_ms__dlclkp_2 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
end
else begin
sky130_fd_sc_ms__dlclkp_4 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
end
endgenerate
$aldff #(
.WIDTH(WIDTH),
.CLK_POLARITY(CLK_POLARITY),
.ALOAD_POLARITY(ALOAD_POLARITY),
)
flipflop(
.CLK(GCLK),
.D(D),
.AD(AD),
.Q(Q)
);
endmodule
| 7.710209 |
module \$sdffe ( CLK, EN, SRST, D, Q);
// parameter CLK_POLARITY =1'b1;
// parameter EN_POLARITY =1'b1;
// parameter SRST_POLARITY =1'b1;
// parameter SRST_VALUE =1'b1;
// parameter WIDTH =1;
// input CLK, EN, SRST;
// input [WIDTH -1:0] D;
// output [WIDTH -1:0] Q;
// wire GCLK;
// generate
// if (WIDTH < 5) begin
// sky130_fd_sc_ms__dlclkp_1 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
// end
// else if (WIDTH < 17) begin
// sky130_fd_sc_ms__dlclkp_2 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
// end
// else begin
// sky130_fd_sc_ms__dlclkp_4 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
// end
// endgenerate
// $sdff #(
// .WIDTH(WIDTH),
// .CLK_POLARITY(CLK_POLARITY),
// .SRST_POLARITY(SRST_POLARITY),
// .SRST_VALUE(SRST_VALUE)
// )
// flipflop(
// .CLK(GCLK),
// .SRST(SRST),
// .D(D),
// .Q(Q)
// );
//endmodule
| 7.043312 |
module \$sdffce ( CLK, EN, SRST, D, Q);
parameter CLK_POLARITY =1'b1;
parameter EN_POLARITY =1'b1;
parameter SRST_POLARITY =1'b1;
parameter SRST_VALUE =1'b1;
parameter WIDTH =1;
input CLK, EN, SRST;
input [WIDTH -1:0] D;
output [WIDTH -1:0] Q;
wire GCLK;
generate
if (WIDTH < 5) begin
sky130_fd_sc_ms__dlclkp_1 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
end
else if (WIDTH < 17) begin
sky130_fd_sc_ms__dlclkp_2 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
end
else begin
sky130_fd_sc_ms__dlclkp_4 clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
end
endgenerate
$sdff #(
.WIDTH(WIDTH),
.CLK_POLARITY(CLK_POLARITY),
.SRST_POLARITY(SRST_POLARITY),
.SRST_VALUE(SRST_VALUE)
)
flipflop(
.CLK(GCLK),
.SRST(SRST),
.D(D),
.Q(Q)
);
endmodule
| 6.900616 |
module sky130_fd_sc_hd__a2bb2o (
X,
A1_N,
A2_N,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A1_N;
input A2_N;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire and0_out;
wire nor0_out;
wire or0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out, B1, B2);
nor nor0 (nor0_out, A1_N, A2_N);
or or0 (or0_out_X, nor0_out, and0_out);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
or0_out_X,
VPWR,
VGND
);
buf buf0 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__a2bb2o (
X,
A1_N,
A2_N,
B1,
B2
);
// Module ports
output X;
input A1_N;
input A2_N;
input B1;
input B2;
// Local signals
wire and0_out;
wire nor0_out;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out, B1, B2);
nor nor0 (nor0_out, A1_N, A2_N);
or or0 (or0_out_X, nor0_out, and0_out);
buf buf0 (X, or0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__a2bb2o (
X,
A1_N,
A2_N,
B1,
B2
);
// Module ports
output X;
input A1_N;
input A2_N;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire and0_out;
wire nor0_out;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out, B1, B2);
nor nor0 (nor0_out, A1_N, A2_N);
or or0 (or0_out_X, nor0_out, and0_out);
buf buf0 (X, or0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__a2bb2o_1 (
X,
A1_N,
A2_N,
B1,
B2,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A1_N;
input A2_N;
input B1;
input B2;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__a2bb2o_1 (
X,
A1_N,
A2_N,
B1,
B2
);
output X;
input A1_N;
input A2_N;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
| 7.212805 |
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