code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sky130_fd_sc_hd__clkbuf (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkbuf_1 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkbuf_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkbuf_2 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkbuf_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkbuf_4 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkbuf_4 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkbuf_8 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkbuf_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkbuf_16 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkbuf_16 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkdlybuf4s15 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
buf0_out_X,
VPWR,
VGND
);
buf buf1 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkdlybuf4s15 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkdlybuf4s15 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkdlybuf4s15_1 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__clkdlybuf4s15 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkdlybuf4s15_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__clkdlybuf4s15 base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkdlybuf4s15_2 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__clkdlybuf4s15 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkdlybuf4s15_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__clkdlybuf4s15 base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkdlybuf4s18 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
buf0_out_X,
VPWR,
VGND
);
buf buf1 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkdlybuf4s18 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkdlybuf4s18 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkdlybuf4s18_1 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__clkdlybuf4s18 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkdlybuf4s18_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__clkdlybuf4s18 base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkdlybuf4s18_2 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__clkdlybuf4s18 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkdlybuf4s18_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__clkdlybuf4s18 base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkdlybuf4s25 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
buf0_out_X,
VPWR,
VGND
);
buf buf1 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkdlybuf4s25 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkdlybuf4s25 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkdlybuf4s25_1 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__clkdlybuf4s25 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkdlybuf4s25_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__clkdlybuf4s25 base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkdlybuf4s25_2 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__clkdlybuf4s25 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkdlybuf4s25_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__clkdlybuf4s25 base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkdlybuf4s50 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_X,
buf0_out_X,
VPWR,
VGND
);
buf buf1 (X, pwrgood_pp0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkdlybuf4s50 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkdlybuf4s50 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkdlybuf4s50_1 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__clkdlybuf4s50 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkdlybuf4s50_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__clkdlybuf4s50 base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkdlybuf4s50_2 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__clkdlybuf4s50 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkdlybuf4s50_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__clkdlybuf4s50 base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkinv (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire not0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
not0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkinv (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A);
buf buf0 (Y, not0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkinv (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A);
buf buf0 (Y, not0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkinv_1 (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkinv_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__clkinv base (
.Y(Y),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkinv_2 (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkinv_2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__clkinv base (
.Y(Y),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkinv_4 (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkinv_4 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__clkinv base (
.Y(Y),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkinv_8 (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkinv_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__clkinv base (
.Y(Y),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkinv_16 (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkinv_16 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__clkinv base (
.Y(Y),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkinvlp (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire not0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
not0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkinvlp (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A);
buf buf0 (Y, not0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkinvlp (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A);
buf buf0 (Y, not0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkinvlp_2 (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__clkinvlp base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkinvlp_2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__clkinvlp base (
.Y(Y),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkinvlp_4 (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__clkinvlp base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__clkinvlp_4 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__clkinvlp base (
.Y(Y),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__conb (
HI,
LO,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output HI;
output LO;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire pullup0_out_HI;
wire pulldown0_out_LO;
// Name Output Other arguments
pullup pullup0 (pullup0_out_HI);
sky130_fd_sc_hd__udp_pwrgood_pp$P pwrgood_pp0 (
HI,
pullup0_out_HI,
VPWR
);
pulldown pulldown0 (pulldown0_out_LO);
sky130_fd_sc_hd__udp_pwrgood_pp$G pwrgood_pp1 (
LO,
pulldown0_out_LO,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__conb (
HI,
LO
);
// Module ports
output HI;
output LO;
// Name Output
pullup pullup0 (HI);
pulldown pulldown0 (LO);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__conb (
HI,
LO
);
// Module ports
output HI;
output LO;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Name Output
pullup pullup0 (HI);
pulldown pulldown0 (LO);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__conb_1 (
HI,
LO,
VPWR,
VGND,
VPB,
VNB
);
output HI;
output LO;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__conb base (
.HI (HI),
.LO (LO),
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__conb_1 (
HI,
LO
);
output HI;
output LO;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__conb base (
.HI(HI),
.LO(LO)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__decap (
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__decap ();
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__decap ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__decap_3 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__decap_3 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__decap base ();
endmodule
| 7.212805 |
module sky130_fd_sc_hd__decap_4 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__decap_4 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__decap base ();
endmodule
| 7.212805 |
module sky130_fd_sc_hd__decap_6 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__decap_6 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__decap base ();
endmodule
| 7.212805 |
module sky130_fd_sc_hd__decap_8 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__decap_8 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__decap base ();
endmodule
| 7.212805 |
module sky130_fd_sc_hd__decap_12 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__decap_12 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__decap base ();
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfbbn (
Q,
Q_N,
D,
CLK_N,
SET_B,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input D;
input CLK_N;
input SET_B;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire RESET;
wire SET;
wire CLK;
wire buf_Q;
wire CLK_N_delayed;
wire RESET_B_delayed;
wire SET_B_delayed;
reg notifier;
wire D_delayed;
wire awake;
wire cond0;
wire cond1;
wire condb;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
not not1 (SET, SET_B_delayed);
not not2 (CLK, CLK_N_delayed);
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (
buf_Q,
SET,
RESET,
CLK,
D_delayed,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (SET_B_delayed === 1'b1));
assign condb = (cond0 & cond1);
buf buf0 (Q, buf_Q);
not not3 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Local signals
wire RESET;
wire SET ;
wire CLK ;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
not not2 (CLK , CLK_N );
sky130_fd_sc_hd__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D);
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfbbn (
Q,
Q_N,
D,
CLK_N,
SET_B,
RESET_B
);
// Module ports
output Q;
output Q_N;
input D;
input CLK_N;
input SET_B;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire RESET;
wire SET;
wire CLK;
wire buf_Q;
wire CLK_N_delayed;
wire RESET_B_delayed;
wire SET_B_delayed;
reg notifier;
wire D_delayed;
wire awake;
wire cond0;
wire cond1;
wire condb;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
not not1 (SET, SET_B_delayed);
not not2 (CLK, CLK_N_delayed);
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (
buf_Q,
SET,
RESET,
CLK,
D_delayed,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (SET_B_delayed === 1'b1));
assign condb = (cond0 & cond1);
buf buf0 (Q, buf_Q);
not not3 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfbbn_1 (
Q,
Q_N,
D,
CLK_N,
SET_B,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input D;
input CLK_N;
input SET_B;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfbbn_1 (
Q,
Q_N,
D,
CLK_N,
SET_B,
RESET_B
);
output Q;
output Q_N;
input D;
input CLK_N;
input SET_B;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfbbn_2 (
Q,
Q_N,
D,
CLK_N,
SET_B,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input D;
input CLK_N;
input SET_B;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfbbn_2 (
Q,
Q_N,
D,
CLK_N,
SET_B,
RESET_B
);
output Q;
output Q_N;
input D;
input CLK_N;
input SET_B;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfbbp (
Q,
Q_N,
D,
CLK,
SET_B,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input D;
input CLK;
input SET_B;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire RESET;
wire SET;
wire buf_Q;
wire CLK_delayed;
wire RESET_B_delayed;
wire SET_B_delayed;
reg notifier;
wire D_delayed;
wire awake;
wire cond0;
wire cond1;
wire condb;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
not not1 (SET, SET_B_delayed);
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (
buf_Q,
SET,
RESET,
CLK_delayed,
D_delayed,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (SET_B_delayed === 1'b1));
assign condb = (cond0 & cond1);
buf buf0 (Q, buf_Q);
not not2 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
// Local signals
wire RESET;
wire SET ;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
sky130_fd_sc_hd__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfbbp (
Q,
Q_N,
D,
CLK,
SET_B,
RESET_B
);
// Module ports
output Q;
output Q_N;
input D;
input CLK;
input SET_B;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire RESET;
wire SET;
wire buf_Q;
wire CLK_delayed;
wire RESET_B_delayed;
wire SET_B_delayed;
reg notifier;
wire D_delayed;
wire awake;
wire cond0;
wire cond1;
wire condb;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
not not1 (SET, SET_B_delayed);
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (
buf_Q,
SET,
RESET,
CLK_delayed,
D_delayed,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (SET_B_delayed === 1'b1));
assign condb = (cond0 & cond1);
buf buf0 (Q, buf_Q);
not not2 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfbbp_1 (
Q,
Q_N,
D,
CLK,
SET_B,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input D;
input CLK;
input SET_B;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfbbp_1 (
Q,
Q_N,
D,
CLK,
SET_B,
RESET_B
);
output Q;
output Q_N;
input D;
input CLK;
input SET_B;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrbp (
Q,
Q_N,
CLK,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire RESET;
reg notifier;
wire D_delayed;
wire RESET_B_delayed;
wire CLK_delayed;
wire awake;
wire cond0;
wire cond1;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
D_delayed,
CLK_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (RESET_B === 1'b1));
buf buf0 (Q, buf_Q);
not not1 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Local signals
wire buf_Q;
wire RESET;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrbp (
Q,
Q_N,
CLK,
D,
RESET_B
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire RESET;
reg notifier;
wire D_delayed;
wire RESET_B_delayed;
wire CLK_delayed;
wire awake;
wire cond0;
wire cond1;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
D_delayed,
CLK_delayed,
RESET,
notifier,
VPWR,
VGND
);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (RESET_B === 1'b1));
buf buf0 (Q, buf_Q);
not not1 (Q_N, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrbp_1 (
Q,
Q_N,
CLK,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrbp_1 (
Q,
Q_N,
CLK,
D,
RESET_B
);
output Q;
output Q_N;
input CLK;
input D;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrbp_2 (
Q,
Q_N,
CLK,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrbp_2 (
Q,
Q_N,
CLK,
D,
RESET_B
);
output Q;
output Q_N;
input CLK;
input D;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrtn (
Q,
CLK_N,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input CLK_N;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire RESET;
wire intclk;
reg notifier;
wire D_delayed;
wire RESET_B_delayed;
wire CLK_N_delayed;
wire awake;
wire cond0;
wire cond1;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
not not1 (intclk, CLK_N_delayed);
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
D_delayed,
intclk,
RESET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (RESET_B === 1'b1));
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intclk, CLK_N );
sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, intclk, RESET);
buf buf0 (Q , buf_Q );
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrtn (
Q,
CLK_N,
D,
RESET_B
);
// Module ports
output Q;
input CLK_N;
input D;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire RESET;
wire intclk;
reg notifier;
wire D_delayed;
wire RESET_B_delayed;
wire CLK_N_delayed;
wire awake;
wire cond0;
wire cond1;
// Name Output Other arguments
not not0 (RESET, RESET_B_delayed);
not not1 (intclk, CLK_N_delayed);
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (
buf_Q,
D_delayed,
intclk,
RESET,
notifier,
VPWR,
VGND
);
assign awake = (VPWR === 1'b1);
assign cond0 = (awake && (RESET_B_delayed === 1'b1));
assign cond1 = (awake && (RESET_B === 1'b1));
buf buf0 (Q, buf_Q);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfrtn_1 (
Q,
CLK_N,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK_N;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
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