code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sky130_fd_sc_hd__dfrtn_1 (
Q,
CLK_N,
D,
RESET_B
);
output Q;
input CLK_N;
input D;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.RESET_B(RESE... | 7.212805 |
module sky130_fd_sc_hd__dfrtp (
Q,
CLK,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input CLK;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire RESET;
reg notifier;
wire D_delayed;
w... | 7.212805 |
module sky130_fd_sc_hd__dfrtp (
Q ,
CLK ,
D ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
// Local signals
wire buf_Q;
wire RESET;
// Delay Name Output Other arguments
... | 7.212805 |
module sky130_fd_sc_hd__dfrtp (
Q,
CLK,
D,
RESET_B
);
// Module ports
output Q;
input CLK;
input D;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire RESET;
reg notifier;
wire D_delayed;... | 7.212805 |
module sky130_fd_sc_hd__dfrtp_1 (
Q,
CLK,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
... | 7.212805 |
module sky130_fd_sc_hd__dfrtp_1 (
Q,
CLK,
D,
RESET_B
);
output Q;
input CLK;
input D;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
)... | 7.212805 |
module sky130_fd_sc_hd__dfrtp_2 (
Q,
CLK,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
... | 7.212805 |
module sky130_fd_sc_hd__dfrtp_2 (
Q,
CLK,
D,
RESET_B
);
output Q;
input CLK;
input D;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
)... | 7.212805 |
module sky130_fd_sc_hd__dfrtp_4 (
Q,
CLK,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
... | 7.212805 |
module sky130_fd_sc_hd__dfrtp_4 (
Q,
CLK,
D,
RESET_B
);
output Q;
input CLK;
input D;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
)... | 7.212805 |
module sky130_fd_sc_hd__dfsbp (
Q,
Q_N,
CLK,
D,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire SET;
reg notifier;
wi... | 7.212805 |
module sky130_fd_sc_hd__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other a... | 7.212805 |
module sky130_fd_sc_hd__dfsbp (
Q,
Q_N,
CLK,
D,
SET_B
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire SET;
reg notifier;
w... | 7.212805 |
module sky130_fd_sc_hd__dfsbp_1 (
Q,
Q_N,
CLK,
D,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
... | 7.212805 |
module sky130_fd_sc_hd__dfsbp_1 (
Q,
Q_N,
CLK,
D,
SET_B
);
output Q;
output Q_N;
input CLK;
input D;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
... | 7.212805 |
module sky130_fd_sc_hd__dfsbp_2 (
Q,
Q_N,
CLK,
D,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
... | 7.212805 |
module sky130_fd_sc_hd__dfsbp_2 (
Q,
Q_N,
CLK,
D,
SET_B
);
output Q;
output Q_N;
input CLK;
input D;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
... | 7.212805 |
module sky130_fd_sc_hd__dfstp (
Q,
CLK,
D,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input CLK;
input D;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire SET;
reg notifier;
wire D_delayed;
wire SE... | 7.212805 |
module sky130_fd_sc_hd__dfstp (
Q ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not ... | 7.212805 |
module sky130_fd_sc_hd__dfstp (
Q,
CLK,
D,
SET_B
);
// Module ports
output Q;
input CLK;
input D;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire SET;
reg notifier;
wire D_delayed;
wir... | 7.212805 |
module sky130_fd_sc_hd__dfstp_1 (
Q,
CLK,
D,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPW... | 7.212805 |
module sky130_fd_sc_hd__dfstp_1 (
Q,
CLK,
D,
SET_B
);
output Q;
input CLK;
input D;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmo... | 7.212805 |
module sky130_fd_sc_hd__dfstp_2 (
Q,
CLK,
D,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPW... | 7.212805 |
module sky130_fd_sc_hd__dfstp_2 (
Q,
CLK,
D,
SET_B
);
output Q;
input CLK;
input D;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmo... | 7.212805 |
module sky130_fd_sc_hd__dfstp_4 (
Q,
CLK,
D,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPW... | 7.212805 |
module sky130_fd_sc_hd__dfstp_4 (
Q,
CLK,
D,
SET_B
);
output Q;
input CLK;
input D;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmo... | 7.212805 |
module sky130_fd_sc_hd__dfxbp (
Q,
Q_N,
CLK,
D,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
reg notifier;
wire D_delayed;
wire CLK_delayed;
wi... | 7.212805 |
module sky130_fd_sc_hd__dfxbp (
Q ,
Q_N,
CLK,
D
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q ... | 7.212805 |
module sky130_fd_sc_hd__dfxbp (
Q,
Q_N,
CLK,
D
);
// Module ports
output Q;
output Q_N;
input CLK;
input D;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
reg notifier;
wire D_delayed;
wire CLK_delayed;
... | 7.212805 |
module sky130_fd_sc_hd__dfxbp_1 (
Q,
Q_N,
CLK,
D,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.VPWR(VPWR)... | 7.212805 |
module sky130_fd_sc_hd__dfxbp_1 (
Q,
Q_N,
CLK,
D
);
output Q;
output Q_N;
input CLK;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfxbp base (
.Q (Q),
.Q_N(Q_N),
.CLK(CLK),
.D (D)
);
endmodul... | 7.212805 |
module sky130_fd_sc_hd__dfxbp_2 (
Q,
Q_N,
CLK,
D,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input CLK;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.VPWR(VPWR)... | 7.212805 |
module sky130_fd_sc_hd__dfxbp_2 (
Q,
Q_N,
CLK,
D
);
output Q;
output Q_N;
input CLK;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfxbp base (
.Q (Q),
.Q_N(Q_N),
.CLK(CLK),
.D (D)
);
endmodul... | 7.212805 |
module sky130_fd_sc_hd__dfxtp (
Q,
CLK,
D,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input CLK;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
reg notifier;
wire D_delayed;
wire CLK_delayed;
wire awake;
// ... | 7.212805 |
module sky130_fd_sc_hd__dfxtp (
Q ,
CLK,
D
);
// Module ports
output Q ;
input CLK;
input D ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , D, CLK );
b... | 7.212805 |
module sky130_fd_sc_hd__dfxtp (
Q,
CLK,
D
);
// Module ports
output Q;
input CLK;
input D;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
reg notifier;
wire D_delayed;
wire CLK_delayed;
wire awake;
// ... | 7.212805 |
module sky130_fd_sc_hd__dfxtp_1 (
Q,
CLK,
D,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
... | 7.212805 |
module sky130_fd_sc_hd__dfxtp_1 (
Q,
CLK,
D
);
output Q;
input CLK;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfxtp base (
.Q (Q),
.CLK(CLK),
.D (D)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfxtp_2 (
Q,
CLK,
D,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
... | 7.212805 |
module sky130_fd_sc_hd__dfxtp_2 (
Q,
CLK,
D
);
output Q;
input CLK;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfxtp base (
.Q (Q),
.CLK(CLK),
.D (D)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dfxtp_4 (
Q,
CLK,
D,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
... | 7.212805 |
module sky130_fd_sc_hd__dfxtp_4 (
Q,
CLK,
D
);
output Q;
input CLK;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dfxtp base (
.Q (Q),
.CLK(CLK),
.D (D)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__diode (
DIODE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input DIODE;
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__diode (
DIODE
);
// Module ports
input DIODE;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__diode (
DIODE
);
// Module ports
input DIODE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hd__diode_2 (
DIODE,
VPWR,
VGND,
VPB,
VNB
);
input DIODE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__diode base (
.DIODE(DIODE),
.VPWR (VPWR),
.VGND (VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__diode_2 (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__diode base (.DIODE(DIODE));
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlclkp (
GCLK,
GATE,
CLK,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output GCLK;
input GATE;
input CLK;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire m0;
wire clkn;
wire CLK_delayed;
wire GATE_delayed;
reg notifier;
... | 7.212805 |
module sky130_fd_sc_hd__dlclkp (
GCLK,
GATE,
CLK
);
// Module ports
output GCLK;
input GATE;
input CLK;
// Local signals
wire m0;
wire clkn;
// Name Output Other arguments
not not0 (clkn, CLK);
sky130_fd_sc_hd__udp_dlatch$P dlatch0 (
m0,
GAT... | 7.212805 |
module sky130_fd_sc_hd__dlclkp (
GCLK,
GATE,
CLK
);
// Module ports
output GCLK;
input GATE;
input CLK;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire m0;
wire clkn;
wire CLK_delayed;
wire GATE_delayed;
reg noti... | 7.212805 |
module sky130_fd_sc_hd__dlclkp_1 (
GCLK,
GATE,
CLK,
VPWR,
VGND,
VPB,
VNB
);
output GCLK;
input GATE;
input CLK;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK (CLK),
.VPWR(VPWR),
.VGND... | 7.212805 |
module sky130_fd_sc_hd__dlclkp_1 (
GCLK,
GATE,
CLK
);
output GCLK;
input GATE;
input CLK;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK (CLK)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlclkp_2 (
GCLK,
GATE,
CLK,
VPWR,
VGND,
VPB,
VNB
);
output GCLK;
input GATE;
input CLK;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK (CLK),
.VPWR(VPWR),
.VGND... | 7.212805 |
module sky130_fd_sc_hd__dlclkp_2 (
GCLK,
GATE,
CLK
);
output GCLK;
input GATE;
input CLK;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK (CLK)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlclkp_4 (
GCLK,
GATE,
CLK,
VPWR,
VGND,
VPB,
VNB
);
output GCLK;
input GATE;
input CLK;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK (CLK),
.VPWR(VPWR),
.VGND... | 7.212805 |
module sky130_fd_sc_hd__dlclkp_4 (
GCLK,
GATE,
CLK
);
output GCLK;
input GATE;
input CLK;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK (CLK)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlrbn (
Q,
Q_N,
RESET_B,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input RESET_B;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire RESET;
wire intgate;
reg ... | 7.212805 |
module sky130_fd_sc_hd__dlrbn (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
// Local signals
wire RESET ;
wire intgate;
wire buf_Q ;
// ... | 7.212805 |
module sky130_fd_sc_hd__dlrbn (
Q,
Q_N,
RESET_B,
D,
GATE_N
);
// Module ports
output Q;
output Q_N;
input RESET_B;
input D;
input GATE_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire RESET;
wire intgate;
reg ... | 7.212805 |
module sky130_fd_sc_hd__dlrbn_1 (
Q,
Q_N,
RESET_B,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input RESET_B;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlrbn base (
.Q(Q),
.Q_N(Q_N),
.RESE... | 7.212805 |
module sky130_fd_sc_hd__dlrbn_1 (
Q,
Q_N,
RESET_B,
D,
GATE_N
);
output Q;
output Q_N;
input RESET_B;
input D;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlrbn base (
.Q(Q),
.Q_N(Q_N),
.RESE... | 7.212805 |
module sky130_fd_sc_hd__dlrbn_2 (
Q,
Q_N,
RESET_B,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input RESET_B;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlrbn base (
.Q(Q),
.Q_N(Q_N),
.RESE... | 7.212805 |
module sky130_fd_sc_hd__dlrbn_2 (
Q,
Q_N,
RESET_B,
D,
GATE_N
);
output Q;
output Q_N;
input RESET_B;
input D;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlrbn base (
.Q(Q),
.Q_N(Q_N),
.RESE... | 7.212805 |
module sky130_fd_sc_hd__dlrbp (
Q,
Q_N,
RESET_B,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input RESET_B;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire RESET;
reg notifier;
wire D_d... | 7.212805 |
module sky130_fd_sc_hd__dlrbp (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Local signals
wire RESET;
wire buf_Q;
// Delay N... | 7.212805 |
module sky130_fd_sc_hd__dlrbp (
Q,
Q_N,
RESET_B,
D,
GATE
);
// Module ports
output Q;
output Q_N;
input RESET_B;
input D;
input GATE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire RESET;
reg notifier;
wire D_... | 7.212805 |
module sky130_fd_sc_hd__dlrbp_1 (
Q,
Q_N,
RESET_B,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input RESET_B;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(... | 7.212805 |
module sky130_fd_sc_hd__dlrbp_1 (
Q,
Q_N,
RESET_B,
D,
GATE
);
output Q;
output Q_N;
input RESET_B;
input D;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(... | 7.212805 |
module sky130_fd_sc_hd__dlrbp_2 (
Q,
Q_N,
RESET_B,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input RESET_B;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(... | 7.212805 |
module sky130_fd_sc_hd__dlrbp_2 (
Q,
Q_N,
RESET_B,
D,
GATE
);
output Q;
output Q_N;
input RESET_B;
input D;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(... | 7.212805 |
module sky130_fd_sc_hd__dlrtn (
Q,
RESET_B,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input RESET_B;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire RESET;
wire intgate;
reg notifier;
wire D_dela... | 7.212805 |
module sky130_fd_sc_hd__dlrtn (
Q ,
RESET_B,
D ,
GATE_N
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Local signals
wire RESET ;
wire intgate;
wire buf_Q ;
// Delay Name O... | 7.212805 |
module sky130_fd_sc_hd__dlrtn (
Q,
RESET_B,
D,
GATE_N
);
// Module ports
output Q;
input RESET_B;
input D;
input GATE_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire RESET;
wire intgate;
reg notifier;
wire D_... | 7.212805 |
module sky130_fd_sc_hd__dlrtn_1 (
Q,
RESET_B,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input RESET_B;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N... | 7.212805 |
module sky130_fd_sc_hd__dlrtn_1 (
Q,
RESET_B,
D,
GATE_N
);
output Q;
input RESET_B;
input D;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N... | 7.212805 |
module sky130_fd_sc_hd__dlrtn_2 (
Q,
RESET_B,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input RESET_B;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N... | 7.212805 |
module sky130_fd_sc_hd__dlrtn_2 (
Q,
RESET_B,
D,
GATE_N
);
output Q;
input RESET_B;
input D;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N... | 7.212805 |
module sky130_fd_sc_hd__dlrtn_4 (
Q,
RESET_B,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input RESET_B;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N... | 7.212805 |
module sky130_fd_sc_hd__dlrtn_4 (
Q,
RESET_B,
D,
GATE_N
);
output Q;
input RESET_B;
input D;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N... | 7.212805 |
module sky130_fd_sc_hd__dlrtp (
Q,
RESET_B,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input RESET_B;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire RESET;
reg notifier;
wire D_delayed;
wire GATE_del... | 7.212805 |
module sky130_fd_sc_hd__dlrtp (
Q ,
RESET_B,
D ,
GATE
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
... | 7.212805 |
module sky130_fd_sc_hd__dlrtp (
Q,
RESET_B,
D,
GATE
);
// Module ports
output Q;
input RESET_B;
input D;
input GATE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire RESET;
reg notifier;
wire D_delayed;
wire GATE... | 7.212805 |
module sky130_fd_sc_hd__dlrtp_1 (
Q,
RESET_B,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input RESET_B;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)... | 7.212805 |
module sky130_fd_sc_hd__dlrtp_1 (
Q,
RESET_B,
D,
GATE
);
output Q;
input RESET_B;
input D;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)... | 7.212805 |
module sky130_fd_sc_hd__dlrtp_2 (
Q,
RESET_B,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input RESET_B;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)... | 7.212805 |
module sky130_fd_sc_hd__dlrtp_2 (
Q,
RESET_B,
D,
GATE
);
output Q;
input RESET_B;
input D;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)... | 7.212805 |
module sky130_fd_sc_hd__dlrtp_4 (
Q,
RESET_B,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input RESET_B;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)... | 7.212805 |
module sky130_fd_sc_hd__dlrtp_4 (
Q,
RESET_B,
D,
GATE
);
output Q;
input RESET_B;
input D;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)... | 7.212805 |
module sky130_fd_sc_hd__dlxbn (
Q,
Q_N,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire GATE;
wire buf_Q;
wire GATE_N_delayed;
wire D_delayed;... | 7.212805 |
module sky130_fd_sc_hd__dlxbn (
Q ,
Q_N ,
D ,
GATE_N
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE_N;
// Local signals
wire GATE ;
wire buf_Q;
// Delay Name Output Other arguments
not... | 7.212805 |
module sky130_fd_sc_hd__dlxbn (
Q,
Q_N,
D,
GATE_N
);
// Module ports
output Q;
output Q_N;
input D;
input GATE_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire GATE;
wire buf_Q;
wire GATE_N_delayed;
wire D_dela... | 7.212805 |
module sky130_fd_sc_hd__dlxbn_1 (
Q,
Q_N,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlxbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE_N(GATE_N),
... | 7.212805 |
module sky130_fd_sc_hd__dlxbn_1 (
Q,
Q_N,
D,
GATE_N
);
output Q;
output Q_N;
input D;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlxbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE_N(GATE_N)
);
... | 7.212805 |
module sky130_fd_sc_hd__dlxbn_2 (
Q,
Q_N,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlxbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE_N(GATE_N),
... | 7.212805 |
module sky130_fd_sc_hd__dlxbn_2 (
Q,
Q_N,
D,
GATE_N
);
output Q;
output Q_N;
input D;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlxbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE_N(GATE_N)
);
... | 7.212805 |
module sky130_fd_sc_hd__dlxbp (
Q,
Q_N,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
output Q_N;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire GATE_delayed;
wire D_delayed;
reg notifier;
... | 7.212805 |
module sky130_fd_sc_hd__dlxbp (
Q ,
Q_N ,
D ,
GATE
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_dlatch$P `UNIT... | 7.212805 |
module sky130_fd_sc_hd__dlxbp (
Q,
Q_N,
D,
GATE
);
// Module ports
output Q;
output Q_N;
input D;
input GATE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire GATE_delayed;
wire D_delayed;
reg notifie... | 7.212805 |
module sky130_fd_sc_hd__dlxbp_1 (
Q,
Q_N,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
output Q_N;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hd__dlxbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE(GATE),
.VPWR(V... | 7.212805 |
module sky130_fd_sc_hd__dlxbp_1 (
Q,
Q_N,
D,
GATE
);
output Q;
output Q_N;
input D;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hd__dlxbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE(GATE)
);
endmodul... | 7.212805 |
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