code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module start_for_minus_vudo_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 7.106633 |
module start_for_minus_vudo (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_minus_vudo_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_minus_vudo_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 7.106633 |
module start_for_minus_vvdy_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 7.106633 |
module start_for_minus_vvdy (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_minus_vvdy_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_minus_vvdy_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 7.106633 |
module start_for_minus_vwdI_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 7.106633 |
module start_for_minus_vwdI (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_minus_vwdI_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_minus_vwdI_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 7.106633 |
module start_for_minus_vxdS_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 7.106633 |
module start_for_minus_vxdS (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_minus_vxdS_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_minus_vxdS_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 7.106633 |
module start_for_Not_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 3'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 7.152232 |
module start_for_Not_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 3'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 3'd1;
if (mOutPtr == 3'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 3'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 3'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_Not_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_Not_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 7.152232 |
module start_for_packer_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 6.663088 |
module start_for_packer_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH + 1) {1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_packer_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_packer_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.663088 |
module start_for_pipe0_data_handler_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 7.858354 |
module start_for_pipe0_data_handler_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH + 1) {1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_pipe0_data_handler_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_pipe0_data_handler_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 7.858354 |
module start_for_pipe0_dram_dispatcher_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 7.858354 |
module start_for_pipe0_dram_dispatcher_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH + 1) {1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_pipe0_dram_dispatcher_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_pipe0_dram_dispatcher_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 7.858354 |
module start_for_pipe1_dram_dispatcher_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd4;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 7.858354 |
module start_for_pipe1_dram_dispatcher_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd4;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH + 1) {1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_pipe1_dram_dispatcher_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_pipe1_dram_dispatcher_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 7.858354 |
module start_for_pipeline_data_passer_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 7.858354 |
module start_for_pipeline_data_passer_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH + 1) {1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_pipeline_data_passer_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_pipeline_data_passer_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 7.858354 |
module start_for_read_mode_dram_helper_app_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 6.804635 |
module start_for_read_mode_dram_helper_app_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH + 1) {1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_read_mode_dram_helper_app_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_read_mode_dram_helper_app_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.804635 |
module start_for_read_mode_pcie_helper_app_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 6.804635 |
module start_for_read_mode_pcie_helper_app_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH + 1) {1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_read_mode_pcie_helper_app_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_read_mode_pcie_helper_app_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.804635 |
module start_for_Reduce_eOg_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd6;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 7.208465 |
module start_for_Reduce_eOg (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd6;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_Reduce_eOg_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_Reduce_eOg_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 7.208465 |
module start_for_Reduce_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd6;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 7.208465 |
module start_for_Reduce_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd6;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_Reduce_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_Reduce_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 7.208465 |
module start_for_relu_array_array_ap_fixed_10u_relu_config7_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 7.034272 |
module start_for_relu_array_array_ap_fixed_10u_relu_config7_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_relu_array_array_ap_fixed_10u_relu_config7_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_relu_array_array_ap_fixed_10u_relu_config7_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 7.034272 |
module start_for_relu_array_array_ap_fixed_10u_relu_config9_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 7.034272 |
module start_for_relu_array_array_ap_fixed_10u_relu_config9_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_relu_array_array_ap_fixed_10u_relu_config9_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_relu_array_array_ap_fixed_10u_relu_config9_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 7.034272 |
module start_for_relu_array_array_ap_fixed_128u_relu_config3_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 7.034272 |
module start_for_relu_array_array_ap_fixed_128u_relu_config3_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_relu_array_array_ap_fixed_128u_relu_config3_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_relu_array_array_ap_fixed_128u_relu_config3_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 7.034272 |
module start_for_relu_array_array_ap_fixed_16u_relu_config3_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 7.034272 |
module start_for_relu_array_array_ap_fixed_16u_relu_config3_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_relu_array_array_ap_fixed_16u_relu_config3_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_relu_array_array_ap_fixed_16u_relu_config3_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 7.034272 |
module start_for_relu_array_array_ap_fixed_2u_relu_config3_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 7.034272 |
module start_for_relu_array_array_ap_fixed_2u_relu_config3_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_relu_array_array_ap_fixed_2u_relu_config3_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_relu_array_array_ap_fixed_2u_relu_config3_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 7.034272 |
module start_for_relu_array_array_ap_fixed_2u_relu_config5_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 7.034272 |
module start_for_relu_array_array_ap_fixed_2u_relu_config5_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_relu_array_array_ap_fixed_2u_relu_config5_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_relu_array_array_ap_fixed_2u_relu_config5_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 7.034272 |
module start_for_relu_array_array_ap_fixed_2u_relu_config7_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 7.034272 |
module start_for_relu_array_array_ap_fixed_2u_relu_config7_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_relu_array_array_ap_fixed_2u_relu_config7_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_relu_array_array_ap_fixed_2u_relu_config7_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 7.034272 |
module start_for_relu_array_array_ap_fixed_5u_relu_config3_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 7.034272 |
module start_for_relu_array_array_ap_fixed_5u_relu_config3_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_relu_array_array_ap_fixed_5u_relu_config3_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_relu_array_array_ap_fixed_5u_relu_config3_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 7.034272 |
module start_for_relu_array_array_ap_fixed_5u_relu_config4_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 7.034272 |
module start_for_relu_array_array_ap_fixed_5u_relu_config4_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_relu_array_array_ap_fixed_5u_relu_config4_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_relu_array_array_ap_fixed_5u_relu_config4_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 7.034272 |
module start_for_relu_array_array_ap_fixed_64u_relu_config3_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 7.034272 |
module start_for_relu_array_array_ap_fixed_64u_relu_config3_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_relu_array_array_ap_fixed_64u_relu_config3_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_relu_array_array_ap_fixed_64u_relu_config3_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 7.034272 |
module start_for_relu_array_array_ap_fixed_8u_relu_config3_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 7.034272 |
module start_for_relu_array_array_ap_fixed_8u_relu_config3_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_relu_array_array_ap_fixed_8u_relu_config3_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_relu_array_array_ap_fixed_8u_relu_config3_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 7.034272 |
module start_for_relu_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 7.034272 |
module start_for_relu_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH + 1) {1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_relu_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_relu_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 7.034272 |
module start_for_Resize_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 3'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 7.200395 |
module start_for_Resize_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 3'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 3'd1;
if (mOutPtr == 3'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 3'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 3'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_Resize_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_Resize_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 7.200395 |
module start_for_softmax_array_array_ap_fixed_10u_softmax_configcud_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 6.578711 |
module start_for_softmax_array_array_ap_fixed_10u_softmax_configcud (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_softmax_array_array_ap_fixed_10u_softmax_configcud_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_softmax_array_array_ap_fixed_10u_softmax_configcud_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.578711 |
module start_for_softmax_array_array_ap_fixed_5u_softmax_config1eOg_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 6.578711 |
module start_for_softmax_array_array_ap_fixed_5u_softmax_config1eOg (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_softmax_array_array_ap_fixed_5u_softmax_config1eOg_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_softmax_array_array_ap_fixed_5u_softmax_config1eOg_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.578711 |
module start_for_softmax_array_array_ap_fixed_5u_softmax_config9fYi_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 6.578711 |
module start_for_softmax_array_array_ap_fixed_5u_softmax_config9fYi (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_softmax_array_array_ap_fixed_5u_softmax_config9fYi_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_softmax_array_array_ap_fixed_5u_softmax_config9fYi_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.578711 |
module start_for_Split_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd5;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 6.992822 |
module start_for_Split_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd5;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_Split_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_Split_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.992822 |
module start_for_ThreshoAem_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 7.590045 |
module start_for_ThreshoAem (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_ThreshoAem_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_ThreshoAem_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 7.590045 |
module start_for_ThreshoBew_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 7.590045 |
module start_for_ThreshoBew (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_ThreshoBew_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_ThreshoBew_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 7.590045 |
module start_for_ThreshoCeG_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 7.590045 |
module start_for_ThreshoCeG (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_ThreshoCeG_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_ThreshoCeG_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 7.590045 |
module start_for_write_mode_app_output_data_caching_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 6.81609 |
module start_for_write_mode_app_output_data_caching_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH + 1) {1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_write_mode_app_output_data_caching_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_write_mode_app_output_data_caching_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.81609 |
module start_for_write_mode_dram_helper_app_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd4;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 6.81609 |
module start_for_write_mode_dram_helper_app_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd4;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH + 1) {1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_write_mode_dram_helper_app_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_write_mode_dram_helper_app_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.81609 |
module start_for_write_mode_pcie_helper_app_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 6.81609 |
module start_for_write_mode_pcie_helper_app_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd7;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH + 1) {1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_write_mode_pcie_helper_app_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_write_mode_pcie_helper_app_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.81609 |
module start_for_write_mode_pre_merged_app_input_data_forwarder_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 6.81609 |
module start_for_write_mode_pre_merged_app_input_data_forwarder_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd8;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH + 1) {1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_write_mode_pre_merged_app_input_data_forwarder_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_write_mode_pre_merged_app_input_data_forwarder_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.81609 |
module start_for_zeropad2d_cl_array_array_ap_fixed_1u_config12_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 6.631903 |
module start_for_zeropad2d_cl_array_array_ap_fixed_1u_config12_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_zeropad2d_cl_array_array_ap_fixed_1u_config12_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_zeropad2d_cl_array_array_ap_fixed_1u_config12_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.631903 |
module start_for_zeropad2d_cl_array_array_ap_fixed_5u_config11_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 6.631903 |
module start_for_zeropad2d_cl_array_array_ap_fixed_5u_config11_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_zeropad2d_cl_array_array_ap_fixed_5u_config11_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_zeropad2d_cl_array_array_ap_fixed_5u_config11_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.631903 |
module start_for_zeropad2d_cl_array_array_ap_fixed_5u_config13_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] SRL_SIG[0:DEPTH-1];
integer i;
always @(posedge clk) begin
if (ce) begin
for (i = 0; i < DEPTH - 1; i = i + 1) SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
| 6.631903 |
module start_for_zeropad2d_cl_array_array_ap_fixed_5u_config13_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_zeropad2d_cl_array_array_ap_fixed_5u_config13_U0_shiftReg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH)
) U_start_for_zeropad2d_cl_array_array_ap_fixed_5u_config13_U0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.631903 |
module start_part (
input vga_clk, //VGA时钟，25.175MHz
input rst, //置位信号，高电平有效
input ena, //模块有效信号
output reg [3:0] red, //输出到VGA的红色数据信号
output reg [3:0] green, //输出到VGA的绿色数据信号
output reg [3:0] blue, //输出到VGA的蓝色数据信号
output hs, //行时序有效信号
output vs, //场时序有效信号
//mp3
input mp3_clk, //mp3时钟，1MHz
input DREQ, //mp3向开发板请求数据信号
output RSET, //mp3硬件重置信号
output CS, //mp3寄存器片选信号，低电平有效
output DCS, //mp3数据片选信号，低电平有效
output MOSI, //向mp3输出的数据
output SCLK //spi总线时钟线，控制mp3的相关逻辑
);
// 分辨率为640*480时行时序各个参数定义
parameter H_SYNC_PULSE = 96 ,
H_BACK_PORCH = 48 ,
H_ACTIVE_TIME = 640 ,
H_FRONT_PORCH = 16 ,
H_LINE_PERIOD = 800 ;
// 分辨率为640*480时场时序各个参数定义
parameter V_SYNC_PULSE = 2 ,
V_BACK_PORCH = 33 ,
V_ACTIVE_TIME = 480 ,
V_FRONT_PORCH = 10 ,
V_FRAME_PERIOD = 525 ;
wire [11:0] h_cnt, v_cnt;
// wire vga_clk;
wire active;
// clk_start start_div(.clk_in1(clk),.clk_out1(vga_clk),.reset(0));
vga_driver start_vga (
.vga_clk(vga_clk),
.rst(rst),
.h_cnt(h_cnt),
.v_cnt(v_cnt),
.hs(hs),
.vs(vs),
.active(active)
);
parameter IMAGE_WIDTH=320,
IMAGE_HEIGHT=240,
IMAGE_SIZE=76800,
WIDTH_TIMES=2,
HEIGHT_TIMES=2;
reg [16:0] start_addr;
wire [15:0] start_data;
always @(posedge vga_clk or posedge rst) begin
if (rst) start_addr <= 17'd0;
else if (active) begin
if(h_cnt>=H_SYNC_PULSE+H_BACK_PORCH &&
h_cnt<=H_SYNC_PULSE+H_BACK_PORCH+IMAGE_WIDTH*WIDTH_TIMES-1'b1 &&
v_cnt>=V_SYNC_PULSE+V_BACK_PORCH &&
v_cnt<=V_SYNC_PULSE+V_BACK_PORCH+IMAGE_HEIGHT*HEIGHT_TIMES-1'b1)
begin
red <= start_data[15:12];
green <= start_data[10:7];
blue <= start_data[4:1];
start_addr<=(h_cnt-(H_SYNC_PULSE+H_BACK_PORCH))/WIDTH_TIMES+(v_cnt-(V_SYNC_PULSE+V_BACK_PORCH))/HEIGHT_TIMES*IMAGE_WIDTH;
end else begin
red <= 4'b0000;
green <= 4'b0000;
blue <= 4'b0000;
end
end else begin
red <= 4'b0000;
green <= 4'b0000;
blue <= 4'b0000;
end
end
rom_start_pic start_pic (
.clka (vga_clk), // input wire clka
.ena (ena), // input wire ena
.addra(start_addr), // input wire [16 : 0] addra
.douta(start_data) // output wire [15 : 0] douta
);
start_bgm display_start_bgm (
.mp3_clk(mp3_clk),
.rst(rst),
.DREQ(DREQ),
.RSET(RSET),
.CS(CS),
.DCS(DCS),
.MOSI(MOSI),
.SCLK(SCLK)
);
endmodule
| 7.753675 |
module Start_REE_CPU (
haddr,
hclk,
hprot,
hrdata,
hready,
hresp,
hrst_b,
hsel,
hsize,
htrans,
hwdata,
hwrite,
intr,
ree_cpu_rst_addr,
ree_cpu_rst_n
);
input [31:0] haddr;
input hclk;
output hready;
input hrst_b;
input hsel;
input [31:0] hwdata;
input hwrite;
output [31:0] hrdata;
output intr;
output [1 : 0] hresp;
input [3 : 0] hprot;
input [2 : 0] hsize;
input [1 : 0] htrans;
output [31:0] ree_cpu_rst_addr;
output ree_cpu_rst_n;
wire [ 31:0] haddr;
wire hclk;
wire hready;
wire hrst_b;
wire hsel;
wire [ 31:0] hwdata;
wire hwrite;
wire [ 31:0] hrdata;
wire intr;
wire [1 : 0] hresp;
wire [3 : 0] hprot;
wire [2 : 0] hsize;
wire [1 : 0] htrans;
wire [ 31:0] ree_cpu_rst_addr;
wire ree_cpu_rst_n;
wire ree_cpu_rst_addr_set_en;
wire ree_cpu_rst_n_set_en;
reg ree_cpu_rst_addr_set_en_reg;
reg ree_cpu_rst_n_set_en_reg;
reg [ 31:0] ree_addr;
reg ree_rst_n;
assign ree_cpu_rst_addr_set_en = (haddr == `SET_ADDR) & hwrite & hsel;
assign ree_cpu_rst_n_set_en = (haddr == `SET_RST_ADDR) & hwrite & hsel;
always @(posedge hclk or negedge hrst_b) begin
if (!hrst_b) begin
ree_cpu_rst_addr_set_en_reg <= 0;
end else begin
ree_cpu_rst_addr_set_en_reg <= ree_cpu_rst_addr_set_en;
end
end
always @(posedge hclk or negedge hrst_b) begin
if (!hrst_b) begin
ree_addr <= 32'h1007FFFF;
end else if (ree_cpu_rst_addr_set_en_reg) begin
ree_addr <= hwdata;
end
end
always @(posedge hclk or negedge hrst_b) begin
if (!hrst_b) begin
ree_cpu_rst_n_set_en_reg <= 0;
end else begin
ree_cpu_rst_n_set_en_reg <= ree_cpu_rst_n_set_en;
end
end
always @(posedge hclk or negedge hrst_b) begin
if (!hrst_b) begin
ree_rst_n <= 0;
end else if (ree_cpu_rst_n_set_en_reg) begin
ree_rst_n <= hwdata[0];
end
end
reg [31:0] ihrdata;
always @(posedge hclk or negedge hrst_b) begin
if (!hrst_b) ihrdata[31:0] <= {32{1'b0}};
else if ((hwrite == 1'b0) && (hsel == 1'b1))
case (haddr)
`SET_ADDR: ihrdata <= ree_addr;
`SET_RST_ADDR: ihrdata <= {31'b0, ree_rst_n};
default: ihrdata <= {32{1'b0}};
endcase
else ihrdata <= {32{1'b1}};
end
assign hrdata[31:0] = ihrdata;
assign hready = 1;
assign hresp = 2'b00;
assign ree_cpu_rst_addr = ree_addr;
assign ree_cpu_rst_n = ree_rst_n;
assign intr = 1'b0;
endmodule
| 6.580607 |
module start_screen (
input clk,
input rst,
input [6:0] switch,
output reg [2:0] r,
output reg [2:0] g,
output reg [1:0] b,
output hs,
output vs
);
parameter UP_BOUND = 31;
parameter DOWN_BOUND = 510;
parameter LEFT_BOUND = 144;
parameter RIGHT_BOUND = 783;
parameter TITLE = "RPG ESCAPE";
reg [79:0] title = TITLE;
reg h_speed, v_speed;
reg [9:0] up_pos, down_pos, left_pos, right_pos;
wire pclk;
reg [1:0] count;
reg [9:0] hcount, vcount;
reg [79:0] screen[29:0];
assign pclk = count[1];
wire [0:7] data;
wire [7:0] grass;
wire [10:0] v_offset, h_offset, char_xoffset, char_yoffset;
assign v_offset = (vcount - 31) % 16;
assign h_offset = (hcount - 144) % 8;
assign char_xoffset = (hcount - 144) / 8 - 35;
assign char_yoffset = (vcount - 31) / 16 - 9;
wire [7:0] char;
assign char = char_yoffset != 0 ? 8'b0:
char_xoffset == 9 ? title[7:0] :
char_xoffset == 8 ? title[15:8] :
char_xoffset == 7 ? title[23:16] :
char_xoffset == 6 ? title[31:24] :
char_xoffset == 5 ? title[39:32] :
char_xoffset == 4 ? title[47:40] :
char_xoffset == 3 ? title[55:48] :
char_xoffset == 2 ? title[63:56] :
char_xoffset == 1 ? title[71:64] :
char_xoffset == 0 ? title[79:72] : 8'b0;
font_rom f0 (
char * 16 + v_offset,
data
);
Grass grass0 (
.clka(pclk), // input clka
.addra((vcount % 8) * 8 + hcount % 8), // input [5 : 0] addra
.douta(grass) // output [7 : 0] douta
);
always @(posedge clk) begin
if (rst) count <= 0;
else count <= count + 1'b1;
end
assign hs = (hcount < 96) ? 1'b0 : 1'b1;
always @(posedge pclk or posedge rst) begin
if (rst) hcount <= 0;
else if (hcount == 799) hcount <= 0;
else hcount <= hcount + 1'b1;
end
assign vs = (vcount < 2) ? 1'b0 : 1'b1;
always @(posedge pclk or posedge rst) begin
if (rst) vcount <= 0;
else if (hcount == 799) begin
if (vcount == 520) vcount <= 0;
else vcount <= vcount + 1'b1;
end else vcount <= vcount;
end
always @(posedge pclk or posedge rst) begin
if (rst) begin
r <= 3'b000;
g <= 3'b000;
b <= 2'b00;
end else begin
if (vcount >= 31 && vcount <= 510 && hcount >= 144 && hcount <= 783) begin
if (char_xoffset >= 0 && char_xoffset <= 9 && char_yoffset == 0) begin
if (data[h_offset]) begin
r <= 3'b000;
g <= 3'b000;
b <= 2'b11;
end else begin
r <= grass[7:5];
g <= grass[4:2];
b <= grass[1:0];
end
end else begin
r <= grass[7:5];
g <= grass[4:2];
b <= grass[1:0];
end
end else begin
r <= 3'b000;
g <= 3'b000;
b <= 2'b00;
end
end
end
endmodule
| 6.679151 |
module start_show (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [639:0] data;
input [8:0] rdaddress;
input rdclock;
input [8:0] wraddress;
input wrclock;
input wren;
output [639:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [639:0] sub_wire0;
wire [639:0] q = sub_wire0[639:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (wrclock),
.clock1 (rdclock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({640{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.init_file = "begin.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 480,
altsyncram_component.numwords_b = 480,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 9,
altsyncram_component.widthad_b = 9,
altsyncram_component.width_a = 640,
altsyncram_component.width_b = 640,
altsyncram_component.width_byteena_a = 1;
endmodule
| 6.813417 |
module start_show (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q
);
input [639:0] data;
input [8:0] rdaddress;
input rdclock;
input [8:0] wraddress;
input wrclock;
input wren;
output [639:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 6.813417 |
module start_square #(
H_SIZE = 80, // half square width (for ease of co-ordinate calculations)
IX = 320, // initial horizontal position of square centre
IY = 240, // initial vertical position of square centre
IX_DIR = 1, // initial horizontal direction: 1 is right, 0 is left
IY_DIR = 1, // initial vertical direction: 1 is down, 0 is up
D_WIDTH = 640, // width of display
D_HEIGHT = 480 // height of display
) (
input wire i_clk, // base clock
input wire i_ani_stb, // animation clock: pixel clock is 1 pix/frame
input wire i_rst, // reset: returns animation to starting position
input wire i_animate, // animate when input is high
output wire [11:0] o_x1, // square left edge: 12-bit value: 0-4095
output wire [11:0] o_x2, // square right edge
output wire [11:0] o_y1, // square top edge
output wire [11:0] o_y2 // square bottom edge
);
reg [11:0] x = IX; // horizontal position of square centre
reg [11:0] y = IY; // vertical position of square centre
reg x_dir = IX_DIR; // horizontal animation direction
reg y_dir = IY_DIR; // vertical animation direction
assign o_x1 = x - H_SIZE; // left: centre minus half horizontal size
assign o_x2 = x + H_SIZE; // right
assign o_y1 = y - H_SIZE; // top
assign o_y2 = y + H_SIZE; // bottom
always @(posedge i_clk) begin
if (i_rst) // on reset return to starting position
begin
x <= IX; // initial x position
y <= IY; // initial y position
x_dir <= IX_DIR; // initial x direction
y_dir <= IY_DIR; // initial y direction
end
if (i_animate && i_ani_stb) begin
x <= (x_dir) ? x + 2 : x - 2; // move left if positive x_dir
y <= (y_dir) ? y + 2 : y - 2; // move down if positive y_dir
if (x <= H_SIZE + 1) // edge of square is at left of screen
x_dir <= 1; // change direction to right
if (x >= (D_WIDTH - H_SIZE - 1)) // edge of square at right
x_dir <= 0; // change direction to left
if (y <= H_SIZE + 1) // edge of square at top of screen
y_dir <= 1; // change direction to down
if (y >= (D_HEIGHT - H_SIZE - 1)) // edge of square at bottom
y_dir <= 0; // change direction to up
end
end
endmodule
| 6.777669 |
module Start_Stop_Detector (
input scl,
input sda,
output reg start_detected,
output reg stop_detected
);
reg sda_shadow;
reg start_or_stop;
initial begin
// Clear the Output and internal Registers
start_or_stop = 0;
start_detected = 0;
stop_detected = 0;
end
always @(scl or sda) begin
// Add the code for Start Stop bit Detector
sda_shadow = (~scl | start_or_stop) ? sda : sda_shadow;
start_or_stop = ~scl ? 1'b0 : (sda ^ sda_shadow);
if (start_or_stop == 1'b1) begin
// Start or Stop Condition is detected
// Therefore two possibilities are there
// sda_shadow = 0 & sda = 1 => Stop Condition
// sda_shadow = 1 & sda = 0 => Start Condition
if (sda_shadow == 1'b0 && sda == 1'b1) begin
// Stop Condition
stop_detected = 1'b1;
end else if (sda_shadow == 1'b1 && sda == 1'b0) begin
// Start Condition
start_detected = 1'b1;
end
end else begin
// Clear the both condition
start_detected = 1'b0;
stop_detected = 1'b0;
end
end // always end
endmodule
| 7.061777 |
module start_sync (
input wire clk_in_domain,
input wire start_in,
input wire clk_out_domain,
input wire start_out
);
reg input_seen = 0; //on clock domain A
//this should be sufficient to prevent metastability
reg [3:0] output_buffer;
assign start_out = output_buffer[3] ^ output_buffer[2];
always @(posedge clk_in_domain) begin
input_seen <= start_in ? ~input_seen : input_seen;
end
always @(posedge clk_out_domain) begin
output_buffer <= {output_buffer[2:0], input_seen};
end
endmodule
| 7.272237 |
module start_test ();
parameter WHITE = 12'b111111111111;
parameter BLACK = 12'b000000000000;
wire start_color;
reg [9:0] x;
reg [8:0] y;
reg vsync = 0;
reg video_on = 0;
wire [11:0] rgb;
assign rgb = (start_color) ? BLACK : WHITE;
start_screen_image START_IMG (
start_color,
x,
y,
vsync,
video_on
);
always #1 x = x + 1;
always @(x) begin
if (x == 639) begin
x = 0;
y = y + 1;
end
end
initial begin
#0 video_on = 1;
x = 0;
y = 50;
vsync = 0;
end
endmodule
| 6.546147 |
module start_vga_control_module (
clk,
rst_n,
ready_col_addr_sig,
ready_row_addr_sig,
ready_sig,
gameready_sig,
tetris_rom_data,
tetris_rom_addr,
ready_red_sig,
ready_green_sig,
ready_blue_sig
);
input clk;
input rst_n;
input [10:0] ready_col_addr_sig;
input [10:0] ready_row_addr_sig;
input ready_sig;
input gameready_sig;
input [16:0] tetris_rom_data;
output [16:0] tetris_rom_addr;
output ready_red_sig;
output ready_green_sig;
output ready_blue_sig;
//&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
reg [8:0] m;
reg m_avail;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
m <= 9'd0;
m_avail <= 1'd0;
end else if (ready_sig && ready_row_addr_sig < 259) begin
m <= ready_row_addr_sig[8:0];
m_avail <= 1'd1;
end else m_avail <= 1'd0;
end
/**************************************************/
reg [8:0] n;
reg n_avail;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
n <= 9'd0;
n_avail <= 1'd0;
end else if (ready_sig && ready_col_addr_sig < 305) begin
n <= ready_col_addr_sig[8:0];
n_avail <= 1'd1;
end else n_avail <= 1'd0;
end
/**************************************************/
assign tetris_rom_addr = m * 305 + n;
//assign ready_red_sig = (ready_sig && gameready_sig && show_block)? tetris_rom_data[0]: 1'b0;
//assign ready_green_sig = (ready_sig && gameready_sig && show_block)? tetris_rom_data[1]: 1'b0;
//assign ready_blue_sig = (ready_sig && gameready_sig && show_block)? tetris_rom_data[2]: 1'b0;
assign ready_red_sig = ( ready_sig && gameready_sig && m_avail && n_avail ) ? ~tetris_rom_data[ 0 ] : 1'b0;
assign ready_green_sig = ( ready_sig && gameready_sig && m_avail && n_avail ) ? ~tetris_rom_data[ 0 ] : 1'b0;
assign ready_blue_sig = ( ready_sig && gameready_sig && m_avail && n_avail ) ? ~tetris_rom_data[ 0 ] : 1'b0;
/**************************************************/
endmodule
| 6.83718 |
module state3 (
input clk,
input rst_n,
input A,
input B,
output o_a,
output o_b
);
localparam IDLE = 5'b00000, S1 = 5'b00010, S2 = 5'b00100, S3 = 5'b01000, S4 = 5'b10000;
reg [4:0] state_n;
reg [4:0] state_c;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
state_c <= IDLE;
end else begin
state_c <= state_n;
end
end
always @(*) begin
case (state_c)
IDLE: begin
state_n <= S1;
end
S1: begin
if (A & B) begin
state_n <= S2;
end else begin
state_n <= state_c;
end
end
S2: begin
if (A) begin
state_n <= S3;
end else begin
state_n <= state_c;
end
end
S3: begin
if (!A & B) begin
state_n <= IDLE;
end else if (A & !B) begin
state_n <= S4;
end else begin
state_n <= state_c;
end
end
S4: begin
end
default: begin
state_n <= IDLE;
end
endcase
end
assign o_a = (state_c == S1) | (state_c == S2);
assign o_b = (state_c == S2);
reg [4:0] cur_sta;
reg [4:0] nex_sta;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cur_sta <= IDLE;
end
case (cur_sta)
IDLE: begin
cur_sta <= S1;
end
S1: begin
if (A & B) begin
cur_sta <= S2;
end else begin
cur_sta <= S1;
end
end
S2: begin
if (A) begin
cur_sta <= S3;
end else begin
cur_sta <= S2;
end
end
S3: begin
if (!A & B) begin
cur_sta <= IDLE;
end else if (A & !B) begin
cur_sta <= S4;
end else begin
cur_sta <= S3;
end
end
S4: begin
cur_sta <= S4;
end
default: begin
state_n <= IDLE;
end
endcase
end
assign o_a = (cur_sta == S1) | (cur_sta == S2);
assign o_b = (cur_sta == S2);
endmodule
| 8.24311 |
module StateControl (
clk,
rst,
//乡道传感器状态
c_sensor_state,
//计数器进位状态
counter_carry_flag,
//当前状态
current_state
);
input clk, rst, c_sensor_state, counter_carry_flag;
output [1:0] current_state;
reg [1:0] current_state;
parameter mgcr = 0, mycr = 1, mrcg = 2, mrcy = 3;
wire div_clk;
//实例化分频
DivFreq fdiv (
.clk(clk),
.clk_out(div_clk)
);
always @(posedge div_clk or negedge rst) begin
if (!rst) current_state <= mgcr;
else
case (current_state)
mgcr: begin
if (c_sensor_state == 1 && counter_carry_flag == 1) current_state <= mycr;
else current_state <= mgcr;
end
mycr: begin
if (counter_carry_flag == 1) current_state <= mrcg;
else current_state <= mycr;
end
mrcg: begin
if (c_sensor_state == 0 && counter_carry_flag == 1) current_state <= mrcy;
else if (c_sensor_state == 1 && counter_carry_flag == 1) current_state <= mrcy;
else current_state <= mrcg;
// if(counter_carry_flag==1)
// current_state<=mrcy;
// else
// current_state<=mrcg;
end
mrcy: begin
if (counter_carry_flag == 1) current_state <= mgcr;
else current_state <= mrcy;
end
endcase
end
endmodule
| 6.65961 |
module StateController (
input btnC,
btnL,
btnR,
btnU,
btnD, //single pulse inputs
input clk, //1kHz, same as single pulse one
input [1:0] nextStateMenu, //00 goes to volume bar, 01 goes to pokemon, 10 goes to fruit ninja, 11 goes to potion mixing
input pokemon_ended,
fruit_ninja_ended,
potion_mixing_ended,
output reg [3:0] state = 4'b0000, //change to 0000
input done_initialize,
input potion_win
//input [11:0] freq //comment out
);
reg [10:0] countUnlock = 11'd0;
always @(posedge clk) begin
case (state)
// 4'b1111: begin//locked state, comment out
// if (freq >= 200 && freq <= 700) begin
// countUnlock <= countUnlock + 1;
// end else begin
// countUnlock <= 0;
// end
// if (countUnlock == 1999) begin
// countUnlock <= 0;
// state <= 4'b0000;
// end
// end
4'b0000: begin //menu
if (btnC == 1) begin
if (nextStateMenu == 2'b00) state <= 4'b0001;
else if (nextStateMenu == 2'b01) state <= 4'b0010;
else if (nextStateMenu == 2'b10)
state <= 4'b0100; //temporary only, remember change back to 0100
else if (nextStateMenu == 2'b11) state <= 4'b0110; //remember to change back to 0110
end
end
4'b0001: begin //volume bar
if (btnC == 1) begin
state <= 4'b0000; //go back to menu
end
end
4'b0010: begin //pokemon game
if (pokemon_ended == 1) begin
state <= 4'b0011; //go to pokemon game over page
end
end
4'b0011: begin // pokemon game over
if (btnC == 1) begin
state <= 4'b0000; //go back to menu
end
end
4'b0100: begin //fruit ninja
if (fruit_ninja_ended == 1) begin
state <= 4'b1001; //go back to menu
end
end
4'b0101: begin //potion mixing
if (potion_mixing_ended == 1) begin //change back to potion_mixing_ended later
state <= 4'b0111; //go to game over
end else if (potion_win == 1) begin
state <= 4'b1000; //go to win page
end
end
4'b0110: begin //potion mixing initialization
if (done_initialize == 1) begin
state <= 4'b0101;
end
end
4'b0111: begin //potion win
if (btnC == 1) begin
state <= 4'b0000;
end
end
4'b1000: begin
if (btnC == 1) begin
state <= 4'b0000;
end
end
4'b1001: begin
if (btnC == 1) begin
state <= 4'b0000;
end
end
endcase
end
endmodule
| 6.908965 |
module StateDisplay (
clken,
halt,
digitout
);
input clken, halt;
output [7:0] digitout;
assign digitout[7] = (~clken);
assign digitout[6] = (~clken);
assign digitout[5] = halt;
assign digitout[4] = 1'b0;
assign digitout[3] = (~clken) || halt;
assign digitout[2] = (~clken) || halt;
assign digitout[1] = (~clken) || halt;
assign digitout[0] = 1'b0;
//From 7 to 0: from a to g, plus dot
endmodule
| 7.126126 |
module statefull (
input pkt_vld_in,
input [511:0] pkt_data_in,
output reg pkt_vld_out,
output reg [511:0] pkt_data_out,
output reg [ 15:0] action_out,
output reg [ 7:0] state_out,
input reset,
input clk
);
reg [23:0] ram_cam[0:15];
reg [23:0] ram2[0:128];
reg [7:0] state_tmp;
reg [23:0] action_tmp;
reg [3:0] cam_q_tmp;
reg mm_cam_vld;
wire [511:0] fifo_pkt_dout;
reg cam_q_vld;
reg fifo_pkt_rd;
wire cam_out_vld;
wire [3:0] cam_q_data;
fifofall #( //存放packet数据
.C_WIDTH(512),
.C_MAX_DEPTH_BITS(8)
) fifo_state_tx ( // Outputs
.dout (fifo_pkt_dout),
.full (),
.nearly_full(),
.empty (fifo_pkt_empty),
// Inputs
.din (pkt_data_in),
.wr_en (pkt_vld_in),
.rd_en (fifo_pkt_rd),
.rst(reset),
.clk(clk)
);
cam #() cam_inst (
.data_in_vld(cam_q_vld),
.data_in(fifo_pkt_dout[3:0]),
.cam_out_vld(cam_out_vld),
.cam_out(cam_q_data),
.reset(reset),
.clk(clk)
);
always @(posedge clk) begin //查cam表
if (reset) begin
cam_q_vld <= 0;
end else begin
if (pkt_vld_in) begin
cam_q_vld <= 1;
end else begin
cam_q_vld <= 0;
end
end
end
always @(posedge clk) begin //查mm_cam表
if (reset) begin
ram_cam[0] <= {16'h00ff, 8'h00};
action_tmp <= 0;
mm_cam_vld <= 0;
end else begin
if (cam_q_vld) begin
state_tmp <= ram_cam[cam_q_data][7:0];
action_tmp <= ram_cam[cam_q_data][23:8];
cam_q_tmp <= cam_q_data;
mm_cam_vld <= 1;
end else begin
mm_cam_vld <= 0;
end
end
end
always @(posedge clk) begin //查 mm_cam表
if (reset) begin
cam_q_vld <= 0;
ram2[0] <= {16'h00ff, 8'h01};
ram2[1] <= {16'h00ff, 8'h02};
ram2[2] <= {16'h0200, 8'h03};
fifo_pkt_rd <= 0;
pkt_vld_out <= 0;
action_out <= 0;
state_out <= 0;
end else begin
if (mm_cam_vld) begin
if (action_tmp[15:8] > 0) begin
action_out <= action_tmp;
state_out <= state_tmp;
fifo_pkt_rd <= 1;
pkt_vld_out <= 1;
pkt_data_out <= fifo_pkt_dout;
end else if (action_tmp[7:0] > 0) begin
ram_cam[cam_q_data] <= ram2[cam_q_data*8+state_tmp];
action_out <= action_tmp;
state_out <= state_tmp;
pkt_data_out <= fifo_pkt_dout;
fifo_pkt_rd <= 1;
pkt_vld_out <= 1;
end
end else begin
action_out <= 0;
fifo_pkt_rd <= 0;
pkt_vld_out <= 0;
state_out <= 0;
end
end
end
endmodule
| 6.860701 |
module stateless (
clk,
i__pkt_1,
i__pkt_2,
i__pkt_3,
i__cons_1,
i__opcode,
i__sel_1,
i__sel_2,
i__sel_3,
i__sel_4,
i__sel_5,
o_write,
o_read
);
// Parameters
parameter COUNT_WIDTH = 32;
// Input signals
input int32_t i__pkt_1;
input int32_t i__pkt_2;
input int32_t i__pkt_3;
input int32_t i__cons_1;
input logic [3:0] i__opcode;
input int2_t i__sel_1;
input int2_t i__sel_2;
input int2_t i__sel_3;
input int2_t i__sel_4;
input int2_t i__sel_5;
// Sequential elements
input logic clk;
int32_t r__register__pff;
int32_t pkt_1;
int32_t pkt_2;
int32_t pkt_3;
int32_t cons_1;
logic [3:0] opcode;
int2_t sel_1;
int2_t sel_2;
int2_t sel_3;
int2_t sel_4;
int2_t sel_5;
// Output signals
output logic [COUNT_WIDTH-1:0] o_write;
output logic [COUNT_WIDTH-1:0] o_read;
// Intermediate signals
int32_t op_bin_1;
int32_t op_bin_2;
int32_t op_cond_1;
int32_t op_cond_2;
int32_t op_cond_3;
// 3-way mux
function int32_t mux3(input int32_t x, input int32_t y, input int32_t z, input int2_t sel);
case (sel)
2'd0: return x;
2'd1: return y;
2'd2: return z;
2'd3: return z;
endcase
endfunction
// 4-way mux
function int32_t mux4(input int32_t x, input int32_t y, input int32_t z, input int32_t w,
input int2_t sel);
case (sel)
2'd0: return x;
2'd1: return y;
2'd2: return z;
2'd3: return w;
endcase
endfunction
//------------------------------------------------------------------------------
// Write register
//------------------------------------------------------------------------------
always_comb begin
o_read = r__register__pff;
// Operands for binary operators
op_bin_1 = mux3(pkt_1, pkt_2, cons_1, sel_1);
op_bin_2 = mux3(pkt_1, pkt_2, cons_1, sel_2);
// Operands for conditional operator
op_cond_1 = mux4(pkt_1, pkt_2, pkt_3, cons_1, sel_3);
op_cond_2 = mux4(pkt_1, pkt_2, pkt_3, cons_1, sel_4);
op_cond_3 = mux4(pkt_1, pkt_2, pkt_3, cons_1, sel_5);
case (opcode)
// arithmetic
4'd0: o_write = (op_bin_1 + op_bin_2);
4'd1: o_write = (op_bin_1 - op_bin_2);
// bit-wise operators (and, or, and xor)
4'd2: o_write = (op_bin_1 & op_bin_2);
4'd3: o_write = (op_bin_1 ^ op_bin_2);
4'd4: o_write = (op_bin_1 | op_bin_2);
// relational
4'd5: o_write = (op_bin_1 == op_bin_2);
4'd6: o_write = (op_bin_1 != op_bin_2);
4'd7: o_write = (op_bin_1 >= op_bin_2);
4'd8: o_write = (op_bin_1 < op_bin_2);
// shifts
4'd9: o_write = (op_bin_1 << op_bin_2);
4'd10: o_write = (op_bin_1 >> op_bin_2);
// conditional
default: o_write = (op_cond_1 ? op_cond_2 : op_cond_3);
endcase
end
//------------ Latch into register--------------------------------
always_ff @(posedge clk) begin
r__register__pff <= o_write;
pkt_1 <= i__pkt_1;
pkt_2 <= i__pkt_2;
pkt_3 <= i__pkt_3;
cons_1 <= i__cons_1;
opcode <= i__opcode;
sel_1 <= i__sel_1;
sel_2 <= i__sel_2;
sel_3 <= i__sel_3;
sel_4 <= i__sel_4;
sel_5 <= i__sel_5;
end
endmodule
| 7.643371 |
module Stateless_Seven_Segment_Display (
input [3:0] i_Nibble,
output o_Segment_A,
output o_Segment_B,
output o_Segment_C,
output o_Segment_D,
output o_Segment_E,
output o_Segment_F,
output o_Segment_G
);
integer w_Display;
always @(i_Nibble)
case (i_Nibble)
0: w_Display = 7'h81;
1: w_Display = 7'hCF;
2: w_Display = 7'h92;
3: w_Display = 7'h86;
4: w_Display = 7'hCC;
5: w_Display = 7'hA4;
6: w_Display = 7'hA0;
7: w_Display = 7'h8F;
8: w_Display = 7'h80;
9: w_Display = 7'h84;
10: w_Display = 7'h88;
11: w_Display = 7'hE0;
12: w_Display = 7'hB1;
13: w_Display = 7'hC2;
14: w_Display = 7'hB0;
15: w_Display = 7'hB8;
endcase
assign o_Segment_A = w_Display[6];
assign o_Segment_B = w_Display[5];
assign o_Segment_C = w_Display[4];
assign o_Segment_D = w_Display[3];
assign o_Segment_E = w_Display[2];
assign o_Segment_F = w_Display[1];
assign o_Segment_G = w_Display[0];
endmodule
| 7.016911 |
module statem (
input wire clk,
input wire rst,
input wire [15:0] sw,
output wire [15:0] Fout
);
reg [ 3:0] op0 = 0;
reg [15:0] A0 = 0;
reg [15:0] B0 = 0;
integer i = 0;
wire SF; // sign flag
wire OF; // overflow flag
wire ZF; // zero flag
wire CF; // carry flag
always @(posedge clk or negedge rst) begin
if (rst == 0) begin
i = 0;
op0 = 0;
end else if (i == 0) begin
A0 = sw[15:0];
i = i + 1;
end else if (i == 1) begin
B0 = sw[15:0];
i = i + 1;
end else if (i == 2) begin
op0 = sw[3:0];
i = i + 1;
end else if (i == 3) begin
op0 = 4'b0001;
i = 0;
A0 = {SF, OF, ZF, CF};
B0 = 0;
end
end
alu a (
.op(op0),
.A(A0),
.B(B0),
.out(Fout),
.CF_out(CF),
.OF_out(OF),
.SF_out(SF),
.ZF_out(ZF)
);
endmodule
| 7.9351 |
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