code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module statemachine_tb ();
logic clk;
logic reset;
logic halt;
logic fetch;
logic exec1;
logic exec2;
statemachine sm (
.clk (clk),
.reset(reset),
.halt (halt),
.fetch(fetch)
);
endmodule
| 6.801401 |
module sequenceDetector (
clk,
reset,
x,
y,
button,
out,
state
);
input clk;
input reset;
input x, y;
input button;
output out;
output state;
reg [3:0] state;
wire out = ((state == 3) || (state == 6));
reg button_reg;
reg button_sync;
wire button_done;
reg [31:0] button_count;
parameter DEBOUNCE_DELAY = 32'd0_500_000; /// 10nS * 1M = 10mS
always @(posedge clk) button_reg <= button;
always @(posedge clk) button_sync <= button_reg;
assign button_done = (button_count == DEBOUNCE_DELAY);
assign button_click = (button_count == DEBOUNCE_DELAY - 1);
always @(posedge clk)
if (!button_sync) button_count <= 0;
else if (button_done) button_count <= button_count;
else button_count <= button_count + 1;
always @(posedge clk)
if (reset) state <= 0;
else if (button_click) begin
case (state)
3'b000:
if (x && !y) state <= 1;
else if (x && y) state <= 4;
else state <= 0;
3'b001:
if (x && !y) state <= 2;
else if (x && y) state <= 4;
else state <= 0;
3'b010:
if (x && y) state <= 3;
else if (x && !y) state <= 2;
else state <= 0;
3'b011: if (x && y) state <= 5;
else if (x && !y) state <= 1;
else state <= 0;
//---------------end of first sequence----------
3'b100: if (x && y) state <= 5;
else if (x && !y) state <= 1;
else state <= 0;
3'b101:
if (x && y) state <= 6;
else if (x && !y) state <= 1;
else state <= 0;
3'b110:
if (x && y) state <= 6;
else if (x && !y) state <= 1;
else state <= 0;
endcase
end else state <= state;
endmodule
| 7.152895 |
module states1 (
input clk,
input st1Begin, //state 1 will be running
input async_rs, //asynchronous reset
input enabler, //if it's on to be running
output [17:0] out,
output st1Over
); //state 1 has done
reg [17:0] r_out;
reg r_st1Over;
reg localReset;
reg rs;
initial begin
r_out <= 18'b1100_0000_0000_0000_00;
r_st1Over <= 0;
localReset <= 0;
end
always @(posedge clk, posedge async_rs, posedge localReset) begin
if (localReset == 1 || async_rs == 1) begin
r_out <= 18'b1100_0000_0000_0000_00;
r_st1Over <= 0;
localReset <= 0;
end //the cycle has been over => reset all value
else
begin
if (st1Begin == 1 && enabler == 1) begin
r_out <= (r_out >> 1);
if (r_out == 6) r_st1Over <= 1'b1; //prepare to end the state
if (r_out == 3) localReset <= 1'b1; //prepare to reset cycle
end
if (enabler == 0 || st1Begin == 0) begin
r_out <= 18'b1100_0000_0000_0000_00;
r_st1Over <= 0;
localReset <= 0;
end
end //else localReset = 0
end //always clk
assign st1Over = r_st1Over;
assign out = r_out;
endmodule
| 6.734189 |
module states2 (
input clk,
input st2Begin, //state 2 will be running
input async_rs, //asynchronous reset
input enabler, //if it's on to be running
output [17:0] out,
output st2Over
); //state 2 has done
reg [17:0] r_out;
reg r_st2Over;
reg localReset;
initial begin
r_out <= 18'b0000_0000_0000_0001_11;
r_st2Over <= 0;
localReset <= 0;
end
always @(posedge clk, posedge async_rs, posedge localReset) begin
if (async_rs == 1 || localReset == 1) begin
r_out <= 18'b0000_0000_0000_0001_11;
r_st2Over <= 0;
localReset <= 0;
end //if async_rs = 1 or the cycle has been over => reset all value
else
begin
if (st2Begin == 1 && enabler == 1) begin
r_out <= (r_out << 1);
if (r_out == 18'b0111_0000_0000_0000_00) r_st2Over <= 1'b1; //prepare to end the state
if (r_out == 18'b1110_0000_0000_0000_00) localReset <= 1'b1; //prepare to reset cycle
end
if (enabler == 0 || st2Begin == 0) begin
r_out <= 18'b0000_0000_0000_0001_11;
r_st2Over <= 0;
localReset <= 0;
end
end //else async_rs = 0
end //always clk
assign st2Over = r_st2Over;
assign out = r_out;
endmodule
| 7.368798 |
module states3 (
input clk,
input st3Begin, //states 3 will be running
input async_rs, //asynchronous reset
input enabler, //if it's on to be running
output [17:0] out,
output st3Over
); //states 3 has done
reg [17:0] r_out;
reg signed [8:0] r_right;
reg [8:0] r_left;
reg [5:0] counter;
reg r_st3Over;
reg localReset;
initial begin
r_out = 18'b0000_0000_0000_0000_00;
r_right = 9'b1000_0000_0;
r_left = 9'b0000_0000_1;
r_st3Over = 0;
counter = 0;
localReset = 0;
end
always @(posedge clk, posedge async_rs, posedge localReset) begin
if (async_rs == 1 || localReset == 1) begin
r_out <= 18'b0000_0000_0000_0000_00;
r_left <= 9'b0000_0000_1;
r_right <= 9'b1000_0000_0;
counter <= 0;
localReset <= 0;
r_st3Over <= 0;
end //if async_rs = 1 or the cycle has been over => reset all value
else
begin
if (st3Begin == 1 && enabler == 1) begin
if (counter[0] == 0) begin
r_right <= (r_right >>> 1);
r_left <= (r_left << 1) + 1'b1;
r_out <= {r_left, r_right};
end //counter even
else r_out <= 18'b0000_0000_0000_0000_00; //counter odd
counter = counter + 1'b1;
if (r_out == 18'b111111111_111111111) r_st3Over <= 1; //prepare to end the state
if (counter == 19) localReset <= 1; //prepare to reset cycle
end
if (enabler == 0 || st3Begin == 0) begin
r_out <= 18'b0000_0000_0000_0000_00;
r_left <= 9'b0000_0000_1;
r_right <= 9'b1000_0000_0;
counter <= 0;
localReset <= 0;
r_st3Over <= 0;
end
end //else reset = 0
end //always clk
assign out = r_out;
assign st3Over = r_st3Over;
endmodule
| 7.522493 |
module states4 (
input clk,
input st4Begin, //states 4 will be running
input async_rs, //asynchronous reset
input enabler, //if it's on to be running
output [17:0] out,
output st4Over
); //states 4 has done
reg [17:0] r_out;
reg signed [8:0] r_left;
reg [8:0] r_right;
reg r_st4Over;
reg localReset;
initial begin
r_out <= 18'b1111_1111_1111_1111_11;
r_right <= 9'b1111_1111_1;
r_left <= 9'b1111_1111_1;
r_st4Over <= 0;
localReset <= 0;
end
always @(posedge clk, posedge async_rs, posedge localReset) begin
if (async_rs == 1 || localReset == 1) begin
r_out <= 18'b1111_1111_1111_1111_11;
r_right <= 9'b1111_1111_0;
r_left <= 9'b0111_1111_1;
localReset <= 0;
r_st4Over <= 0;
end //if async_rs = 1 or the cycle has been over => reset all value
else
begin
if (st4Begin == 1 && enabler == 1) begin
r_out <= {r_left, r_right};
r_left <= (r_left >> 1);
r_right <= (r_right << 1);
if (r_out == 18'b000000001_100000000) r_st4Over <= 1; //prepare to end the state
if (r_out == 18'b000000000_000000000) localReset <= 1; //prepare to reset cycle
end
if (enabler == 0 || st4Begin == 0) begin
r_out <= 18'b1111_1111_1111_1111_11;
r_right <= 9'b1111_1111_0;
r_left <= 9'b0111_1111_1;
localReset <= 0;
r_st4Over <= 0;
end
end //else reset = 0
end //always clk
assign out = r_out;
assign st4Over = r_st4Over;
endmodule
| 7.198969 |
module states5 (
input clk,
input st5Begin, //states 5 will be running
input async_rs, //asynchronous reset
input enabler, //if it's on to be running
output [17:0] out,
output st5Over
); //states 5 has done
reg signed [17:0] r_out;
reg r_st5Over;
reg finishloading;
reg localReset;
initial begin
r_out = 18'b1000_0000_0000_0000_00;
r_st5Over = 0;
finishloading = 0;
localReset = 0;
end
always @(posedge clk, posedge async_rs, posedge localReset) begin
if (async_rs == 1 || localReset == 1) begin
r_out <= 18'b1000_0000_0000_0000_00;
finishloading <= 0;
localReset <= 0;
r_st5Over <= 0;
end //if async_rs = 1 or the cycle has been over => reset all value
else
begin
if (st5Begin == 1 && enabler == 1) begin
if (finishloading == 0) begin
r_out <= r_out >>> 1;
if (r_out == 18'b1111_1111_1111_1111_11)
finishloading <= 1; //finished loading all led on
end //first cycle: loading led
else
begin
r_out <= r_out << 1;
if (r_out == 18'b1000_0000_0000_0000_00) r_st5Over <= 1; //prepare to end the state
if (r_out == 18'b0000_0000_0000_0000_00) localReset <= 1; //prepare to reset cycle
end //second cycle: unloading led
end //st5 started running
if (enabler == 0 || st5Begin == 0) begin
r_out <= 18'b1000_0000_0000_0000_00;
finishloading <= 0;
localReset <= 0;
r_st5Over <= 0;
end
end //else reset = 0
end //always clk
assign out = r_out;
assign st5Over = r_st5Over;
endmodule
| 6.644644 |
module states6 (
input clk,
input st6Begin, //states 6 will be running
input async_rs, //asynchronous reset
input enabler,
output [17:0] out,
output st6Over
); //states 6 has done
reg [17:0] r_out;
reg r_st6Over;
reg finishloading;
reg localReset;
initial begin
r_out = 18'b0000_0000_0000_0000_01;
r_st6Over = 0;
finishloading = 0;
localReset = 0;
end
always @(posedge clk, posedge async_rs, posedge localReset) begin
if (async_rs == 1 || localReset == 1) begin
r_out <= 18'b0000_0000_0000_0000_01;
r_st6Over <= 0;
finishloading <= 0;
localReset <= 0;
end //if async_rs = 1 or the cycle has been over => reset all value
else
begin
if (st6Begin == 1 && enabler == 1) begin
if (finishloading == 0) begin
r_out <= (r_out << 1) + 1'b1;
if (r_out == 18'b1111_1111_1111_1111_11)
finishloading <= 1; //finished loading all led on
end //first cycle: loading led
else
begin
r_out <= r_out >> 1;
if (r_out == 18'b0000_0000_0000_0000_01) r_st6Over <= 1; //prepare to end the state
if (r_out == 18'b0000_0000_0000_0000_00) localReset <= 1; //prepare to reset cycle
end //second cycle: unloading led
end //st6 started running
if (enabler == 0 || st6Begin == 0) begin
r_out <= 18'b0000_0000_0000_0000_01;
r_st6Over <= 0;
finishloading <= 0;
localReset <= 0;
end
end //else reset = 0
end //always clk
assign out = r_out;
assign st6Over = r_st6Over;
endmodule
| 6.89263 |
module StateSwitch (
output reg [1:0] state,
input [5:0] enb,
input [1:0] state1,
input [1:0] state2,
input [1:0] state3,
input [1:0] state4,
input [1:0] stateRst,
input [1:0] stateOnline,
input clk
);
parameter RED = 2'b00;
parameter YELLOW = 2'b01;
parameter GREEN = 2'b10;
parameter UNDEFINED = 2'b11;
always @(clk) begin
case (enb)
6'b100000: state <= state1;
6'b010000: state <= state2;
6'b001000: state <= state3;
6'b000100: state <= state4;
6'b000010: state <= stateRst;
6'b000001: state <= stateOnline;
default: begin
state <= GREEN;
end
endcase
end
endmodule
| 7.045739 |
module STATE_1MS_TOP (
state_1ms_rst_n,
clk_sys,
state_1ms_start,
reset_out,
dump_start,
pluse_start,
bri_cycle,
rt_sw,
soft_dump,
load,
loadchoice,
datain
);
input state_1ms_rst_n;
input clk_sys;
input state_1ms_start;
output reset_out;
output dump_start;
output pluse_start;
output bri_cycle;
output rt_sw;
output soft_dump;
input load;
input [3:0] loadchoice;
input [15:0] datain;
wire \state_1ms_0_timecount_[19] , \state_1ms_0_timecount_[18] ,
\state_1ms_0_timecount_[17] , \state_1ms_0_timecount_[16] ,
\state_1ms_0_timecount_[15] , \state_1ms_0_timecount_[14] ,
\state_1ms_0_timecount_[13] , \state_1ms_0_timecount_[12] ,
\state_1ms_0_timecount_[11] , \state_1ms_0_timecount_[10] ,
\state_1ms_0_timecount_[9] , \state_1ms_0_timecount_[8] ,
\state_1ms_0_timecount_[7] , \state_1ms_0_timecount_[6] ,
\state_1ms_0_timecount_[5] , \state_1ms_0_timecount_[4] ,
\state_1ms_0_timecount_[3] , \state_1ms_0_timecount_[2] ,
\state_1ms_0_timecount_[1] , \state_1ms_0_timecount_[0] ,
timeup_n, GND_net, VCC_net;
timer timer_0 (
.rst_n(state_1ms_rst_n),
.clk_sys(clk_sys),
.datain({
GND_net,
GND_net,
\state_1ms_0_timecount_[19] ,
\state_1ms_0_timecount_[18] ,
\state_1ms_0_timecount_[17] ,
\state_1ms_0_timecount_[16] ,
\state_1ms_0_timecount_[15] ,
\state_1ms_0_timecount_[14] ,
\state_1ms_0_timecount_[13] ,
\state_1ms_0_timecount_[12] ,
\state_1ms_0_timecount_[11] ,
\state_1ms_0_timecount_[10] ,
\state_1ms_0_timecount_[9] ,
\state_1ms_0_timecount_[8] ,
\state_1ms_0_timecount_[7] ,
\state_1ms_0_timecount_[6] ,
\state_1ms_0_timecount_[5] ,
\state_1ms_0_timecount_[4] ,
\state_1ms_0_timecount_[3] ,
\state_1ms_0_timecount_[2] ,
\state_1ms_0_timecount_[1] ,
\state_1ms_0_timecount_[0]
}),
.work_n(timeup_n),
.state_start(state_1ms_start),
.state_over_n(VCC_net),
.timeup_n(timeup_n)
);
VCC VCC (.Y(VCC_net));
GND GND (.Y(GND_net));
state_1ms state_1ms_0 (
.clk_sys(clk_sys),
.clken_p(timeup_n),
.rst_n(state_1ms_rst_n),
.load(load),
.loadchoice({loadchoice[3], loadchoice[2], loadchoice[1], loadchoice[0]}),
.datain({
datain[15],
datain[14],
datain[13],
datain[12],
datain[11],
datain[10],
datain[9],
datain[8],
datain[7],
datain[6],
datain[5],
datain[4],
datain[3],
datain[2],
datain[1],
datain[0]
}),
.reset_out(reset_out),
.dump_start(dump_start),
.pluse_start(pluse_start),
.bri_cycle(bri_cycle),
.rt_sw(rt_sw),
.soft_dump(soft_dump),
.timecount({
\state_1ms_0_timecount_[19] ,
\state_1ms_0_timecount_[18] ,
\state_1ms_0_timecount_[17] ,
\state_1ms_0_timecount_[16] ,
\state_1ms_0_timecount_[15] ,
\state_1ms_0_timecount_[14] ,
\state_1ms_0_timecount_[13] ,
\state_1ms_0_timecount_[12] ,
\state_1ms_0_timecount_[11] ,
\state_1ms_0_timecount_[10] ,
\state_1ms_0_timecount_[9] ,
\state_1ms_0_timecount_[8] ,
\state_1ms_0_timecount_[7] ,
\state_1ms_0_timecount_[6] ,
\state_1ms_0_timecount_[5] ,
\state_1ms_0_timecount_[4] ,
\state_1ms_0_timecount_[3] ,
\state_1ms_0_timecount_[2] ,
\state_1ms_0_timecount_[1] ,
\state_1ms_0_timecount_[0]
})
);
endmodule
| 6.93894 |
module state_cola_1 (
input wire sys_clk,
input wire sys_rst_n,
input wire pi_money,
output reg po_cola
);
reg [2:0] state;
parameter ZERO = 3'b001, ONE = 3'b010, TWO = 3'b100;
//状态机的赋值
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) state <= ZERO;
else
case (state)
ZERO:
if (pi_money == 1'b1) begin
state <= ONE;
po_cola <= 1'b0;
end else begin
state <= state;
po_cola <= 1'b0;
end
ONE:
if (pi_money == 1'b1) begin
state <= TWO;
po_cola <= 1'b0;
end else begin
state <= state;
po_cola <= 1'b0;
end
TWO:
if (pi_money == 1'b1) begin
state <= ZERO;
po_cola <= 1'b1;
end else begin
state <= state;
po_cola <= 1'b0;
end
default: state <= ZERO;
endcase
endmodule
| 7.271812 |
module state_cola_2 (
input wire sys_clk,
input wire sys_rst_n,
input wire pi_money_one,
input wire pi_money_half,
output reg po_cola,
output reg po_money
);
reg [4:0] state;
wire [1:0] pi_money;
//独热码
parameter ZERO = 5'b00001, HALF = 5'b00010, ONE = 5'b00100, ONE_HALF = 5'b01000, TWO = 5'b10000;
assign pi_money = {pi_money_one, pi_money_half};
//状态机的赋值
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) state <= ZERO;
else
case (state)
ZERO:
if (pi_money == 2'b01) state <= HALF;
else if (pi_money == 2'b10) state <= ONE_HALF;
else state <= state;
HALF:
if (pi_money == 2'b01) state <= ONE;
else if (pi_money == 2'b10) state <= TWO;
else state <= state;
ONE:
if (pi_money == 2'b01) state <= ONE_HALF;
else if (pi_money == 2'b10) state <= TWO;
else state <= state;
ONE_HALF:
if (pi_money == 2'b01) state <= TWO;
else if (pi_money == 2'b10) state <= ZERO;
else state <= state;
TWO:
if (pi_money == 2'b01) state <= ZERO;
else if (pi_money == 2'b10) state <= ZERO;
else state <= state;
default: state <= ZERO;
endcase
//state 和 pi_money如何影响po_money
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) po_money <= 1'b0;
else if (state == TWO && pi_money == 2'b10) po_money <= 1'b1;
else po_money <= 1'b0;
//state 和 pi_money如何影响po_cola
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) po_cola <= 1'b0;
else if((state == ONE_HALF && pi_money == 2'b10) || (state == TWO && pi_money == 2'b01)
|| (state == TWO && pi_money == 2'b10))
po_cola <= 1'b1;
else po_cola <= 1'b0;
endmodule
| 8.719373 |
module state_controller (
input clk,
input reset,
input start,
input [9:0] enemy_laser_h,
input [9:0] plane_h,
input [9:0] enemy_0_v,
input [9:0] enemy_1_v,
input [9:0] enemy_2_v,
input [9:0] enemy_3_v,
input [9:0] enemy_4_v,
input [9:0] enemy_5_v,
input [9:0] enemy_6_v,
input [9:0] enemy_7_v,
output reg [1:0] state
);
parameter press_start = 0, playing = 1, gamover = 2;
parameter gameover_condition = 380;
reg [1:0] next_state;
always @(posedge clk or posedge reset) begin
if (reset) state <= 0;
else state <= next_state;
end
always @(*) begin
case (state)
0:
if (start) next_state = playing;
else next_state = state;
1:
if (enemy_laser_h >= plane_h && enemy_laser_h < plane_h + 20) next_state = gamover;
else if (enemy_0_v >= 380) next_state = gamover;
else if (enemy_1_v >= 380) next_state = gamover;
else if (enemy_2_v >= 380) next_state = gamover;
else if (enemy_3_v >= 380) next_state = gamover;
else if (enemy_4_v >= 380) next_state = gamover;
else if (enemy_5_v >= 380) next_state = gamover;
else if (enemy_6_v >= 380) next_state = gamover;
else if (enemy_7_v >= 380) next_state = gamover;
else next_state = state;
2: next_state = state;
3: next_state = state;
endcase
end
endmodule
| 6.516943 |
module state_converter (
input clk,
input rst,
input wire [7:0] ms,
input wire [7:0] sec,
input wire [7:0] min,
input start,
input pause,
input reset,
output reg clr_signal,
output reg add_signal,
reg [1:0] State
);
parameter ACTIVE = 2'b00;
parameter PAUSE = 2'b01;
parameter ERROR = 2'b10;
wire time_legal;
time_exceed te (
clk,
rst,
ms,
sec,
min,
time_legal
);
always @(posedge clk or negedge rst) begin
if (rst) begin
State <= PAUSE;
add_signal <= 'b0;
clr_signal <= 'b1;
end else begin
case (State)
ACTIVE: begin
if (pause) begin
add_signal <= 'b0;
clr_signal <= 'b0;
State <= PAUSE;
end else if (reset) begin
add_signal <= 'b0;
clr_signal <= 'b1;
State <= PAUSE;
end else if (time_legal) begin
add_signal <= 'b1;
clr_signal <= 'b0;
end else begin
add_signal <= 'b0;
clr_signal <= 'b1;
State <= ERROR;
end
end
PAUSE: begin
if (pause) begin
add_signal <= 'b0;
clr_signal <= 'b0;
end else if (reset) begin
add_signal <= 'b0;
clr_signal <= 'b1;
end else if (start) begin
add_signal <= 'b1;
clr_signal <= 'b0;
State = ACTIVE;
end
end
ERROR: begin
if (pause || start) begin
add_signal <= 'b0;
clr_signal <= 'b0;
end else if (reset) begin
add_signal <= 'b0;
clr_signal <= 'b1;
State <= PAUSE;
end
end
default: ;
endcase
end
end
endmodule
| 8.074048 |
module state_data_ctrl (
input clk,
input rst,
input power,
input [1:0] mode,
input [3:0] state,
output reg [35:0] data
);
parameter non_act = 4'b0000;
parameter none_s = 4'b0001;
parameter none_s_2 = 4'b0110;
parameter start = 4'b0010;
parameter move = 4'b0011;
parameter switch = 4'b0100;
parameter reverse = 4'b0101;
always @(posedge clk, negedge rst) begin
if (!rst) begin
data <= 6'b11_1110;
end else if (!power) begin
data <= 35'b011000_001111_001111_111110_111110_111110; //off
end else begin
case (mode)
2'b01: begin
case (state)
non_act: begin
data <= 35'b010001_001010_010111_001101_111110_111110; //hand
end
none_s: begin
data <= 35'b010111_100100_001010_111110_111110_111110; //n/a
end
none_s_2: begin
data <= 35'b010111_100100_001010_111110_111110_111110; //n/a
end
start: begin
data <= 35'b011100_011101_001010_011011_011101_111110; //start
end
move: begin
data <= 35'b010110_011000_011111_001110_001111_100000; //movefw
end
switch: begin
data <= 35'b011100_100000_010010_011101_001100_010001; //swicth
end
reverse: begin
data <= 35'b011011_001110_011111_111110_111110_111110; //rev
end
default: begin
data <= 35'b010001_001010_010111_001101_111110_111110; //hand
end
endcase
end
2'b10: begin
data <= 35'b011100_001110_010110_010010_111110_111110; //semi
end
2'b11: begin
data <= 35'b001010_011110_011101_011000_111110_111110; //auto
end
default: begin
data <= 35'b011000_010111_111110_111110_111110_111110; //on
end
endcase
end
end
endmodule
| 8.168938 |
module state_decoder (
i_state,
o_7seg
);
input [2:0] i_state;
output reg [6:0] o_7seg;
always @(i_state) begin
case (i_state)
3'b000: o_7seg = 7'b0010010;
3'b001: o_7seg = 7'b1000001;
3'b010: o_7seg = 7'b1000001;
3'b011: o_7seg = 7'b1000001;
3'b100: o_7seg = 7'b0010010;
3'b101: o_7seg = 7'b0001110;
default: o_7seg = 7'b1111111;
endcase
end
endmodule
| 6.507637 |
module STATE_GRAPHIC(CLK, RESET, W_IN, Z_OUT)
input clk;
input rst_n;
input w_i;
output z_o;
parameter IDLE = 2'b00;
parameter S0 = 2'b01;
reg [1:0] curr_state;
reg [1:0] next_state;
reg z;
reg z_o;
// state reg
always@(posedge clk or negedge rst_n)
if (~rst_n) curr_state <= IDLE;
else curr_state <= next_state;
// next state logic
always@(*)
case (curr_state)
IDLE : if (w_i) next_state = S0;
else next_state = IDLE;
S0 : if (w_i) next_state = S0;
else next_state = IDLE;
default : next_state = IDLE;
endcase
//output logic
always@(*)
case (curr_state)
IDLE : if (w_i) z = 1'b0;
else z = 1'b0;
S0 : if (w_i) z = 1'b1;
else z = 1'b0;
default : z = 1'b0;
endcase
// mealy output to delay 1 clk for moore
always@(posedge clk or negedge rst_n)
if (~rst_n) z_o <= 1'b0;
else z_o <= z;
endmodule
| 7.222595 |
module state_m (
// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
clk,
reset,
newt,
sel,
follow,
first
// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration
// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
input clk, reset, newt;
output follow, first;
output [1:0] sel;
// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
// Wire Declaration
reg follow, first;
reg [1:0] sel;
reg [2:0] filter;
parameter idle = 0, tap1 = 1, tap2 = 2, tap3 = 3, tap4 = 4;
always begin
case (filter)
idle: begin
sel = 2'b0;
follow = 1'b0;
first = 1'b0;
end
tap1: begin
sel = 2'b0;
follow = 1'b0;
first = 1'b1;
end
tap2: begin
sel = 2'b01;
follow = 1'b0;
first = 1'b0;
end
tap3: begin
sel = 2'b10;
follow = 1'b0;
first = 1'b0;
end
tap4: begin
sel = 2'b11;
follow = 1'b1;
first = 1'b0;
end
default: begin
sel = 2'b00;
follow = 1'b0;
first = 1'b0;
end
endcase
end
always @(posedge clk or posedge reset) begin
if (reset) filter = idle;
else
case (filter)
idle: begin
if (newt) filter = tap1;
end
tap1: begin
filter = tap2;
end
tap2: begin
filter = tap3;
end
tap3: begin
filter = tap4;
end
tap4: begin
if (newt) filter = tap1;
else filter = idle;
end
endcase
end
endmodule
| 6.610127 |
module STATE_MEMORY #(
parameter depth = 512,
parameter address_width = $clog2(depth)
) (
input CLK,
input RST,
input FLUSH,
input WREN,
input [address_width-1:0] WADDR,
input [address_width-1:0] RADDR,
output STATE,
input DATA
);
reg [depth-1:0] state_mem;
always @(posedge CLK) begin
if (RST | FLUSH) begin
state_mem <= 0;
end else if (WREN) begin
state_mem[WADDR] <= DATA;
end
end
assign STATE = state_mem[RADDR];
endmodule
| 8.073548 |
module's output value
state - used for switching between bios output and instruction memory output
*/
module State_Mux_32
#(parameter DATA_WIDTH = 32)
(
input mux_select, clk, rst, hlt,
input [(DATA_WIDTH -1):0] input_data_1, input_data_2,
output [(DATA_WIDTH -1):0] mux_output
);
reg state;
always @ ( posedge clk )
begin
case( state )
1'b0:
begin
if( mux_select )
state <= 1'b1;
end
1'b1:
begin
if( rst )
state <= 1'b0;
end
endcase
end
assign mux_output = (state == 1'b1) ? input_data_2 : input_data_1;
endmodule
| 9.302274 |
module state_register (
ALE,
CLE,
CE,
command,
state
);
input ALE, CLE, CE;
input command;
reg [3:0] command;
output [7:0] state;
reg [7:0] state;
//reg [3:0]mid;
always @(command or CE) begin
if (CE) state = 0;
else if (state[7]) //state][7]=1 意味着是两单位命令
case (command)
4'b0010: begin
//state[5]=1; //1000_0010 写状态
state[1] = 1; //
end
4'b0110: begin
state[5] = 1; //1110_XXXX forming状态
end
default: state = 0;
endcase
else
case (command)
4'b0001: begin
state[0] = 1; //读命令 0000_0001
end
4'b0100: begin
state[7] = 1; //写命令第一条 1000_0000
state[6] = 0;
end
4'b0111: begin
state[7] = 1; //forming 命令第一条 1100_0000
state[6] = 1;
end
default: state = 0;
endcase
end
/*always@(negedge ALE)
begin
state[2]=1; //state[2]置1 表示地址准备好了
end */
endmodule
| 6.849679 |
module state_switch (
clk_sys,
rst_n,
time_up_in,
start,
state_over_in,
datain_scale,
datain_scan,
datain_noise,
datain_pluse,
datain_state_1ms,
dataout,
state_start,
state_over_n,
clk_en_scale,
clk_en_scan,
clk_en_noise,
clk_en_pluse,
clk_en_st1ms
);
input clk_sys;
input rst_n;
input time_up_in;
input [4:0] start;
input [3:0] state_over_in;
input [21:0] datain_scale;
input [19:0] datain_scan;
input [19:0] datain_noise;
input [19:0] datain_pluse;
input [19:0] datain_state_1ms;
output reg state_start;
output reg [21:0] dataout;
output reg state_over_n;
output reg clk_en_scale;
output reg clk_en_scan;
output reg clk_en_noise;
output reg clk_en_pluse;
output reg clk_en_st1ms;
always @(posedge clk_sys) begin
if (!rst_n) begin
state_over_n <= 1'b1;
dataout <= 22'd0;
end else begin
case (start)
5'b00001: begin
state_over_n <= state_over_in[0];
dataout <= datain_scale;
end
5'b00010: begin
state_over_n <= state_over_in[1];
dataout <= datain_scan;
end
5'b00100: begin
state_over_n <= state_over_in[2];
dataout <= datain_noise;
end
5'b01000: begin
state_over_n <= state_over_in[3];
dataout <= datain_pluse;
end
5'b10000: begin
state_over_n <= 1'b1;
dataout <= datain_state_1ms;
end
default: begin
state_over_n <= 1'b1;
dataout <= 22'd0;
end
endcase
end
end
always @(posedge clk_sys) begin
if (!rst_n) state_start <= 1'b0;
else if (start == 5'd1 | start == 5'd2 | start == 5'd4 | start == 5'd8 | start == 5'd16)
state_start <= 1'b1;
else state_start <= 1'b0;
end
always @(posedge clk_sys) begin
if (!rst_n) begin
clk_en_scale <= 1'b0;
clk_en_scan <= 1'b0;
clk_en_noise <= 1'b0;
clk_en_pluse <= 1'b0;
clk_en_st1ms <= 1'b0;
end else begin
if (start[0]) clk_en_scale <= time_up_in;
else clk_en_scale <= 1'b0;
if (start[1]) clk_en_scan <= time_up_in;
else clk_en_scan <= 1'b0;
if (start[2]) clk_en_noise <= time_up_in;
else clk_en_noise <= 1'b0;
if (start[3]) clk_en_pluse <= time_up_in;
else clk_en_pluse <= 1'b0;
if (start[4]) clk_en_st1ms <= time_up_in;
else clk_en_st1ms <= 1'b0;
end
end
endmodule
| 7.867447 |
module state_transition (
input clk,
rst_n,
input en_in,
input en1,
input en2,
input [1 : 0] rd,
input [3 : 0] opcode,
output reg en_fetch_pulse,
output reg en_group_pulse,
output reg en_pc_pulse,
output reg [1 : 0] pc_ctrl,
output reg [3 : 0] reg_en,
output reg alu_in_sel,
output reg [2 : 0] alu_func
);
reg en_fetch_reg, en_fetch;
reg en_group_reg, en_group;
reg en_pc_reg, en_pc;
reg [3 : 0] current_state, next_state;
localparam INIT = 4'b0000;
localparam IF = 4'b0001;
localparam ID = 4'b0010;
localparam EX_AL = 4'b1000;
localparam WB = 4'b0011;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
current_state <= INIT;
end else begin
current_state <= next_state;
end
end
always @(*) begin
case (current_state)
INIT: begin
if (en_in) begin
next_state = IF;
end else begin
next_state = INIT;
end
end
IF: begin
if (en1) begin
next_state = ID;
end else begin
next_state = current_state;
end
end
ID: begin
if (opcode[3] == 1'b0) begin
next_state = EX_AL;
end else begin
next_state = current_state;
end
end
EX_AL: begin
if (en2) begin
next_state = WB;
end else begin
next_state = current_state;
end
end
WB: begin
next_state = IF;
end
default: next_state = current_state;
endcase
end
always @(*) begin
if (!rst_n) begin
en_fetch = 1'b0;
en_group = 1'b0;
en_pc = 1'b0;
pc_ctrl = 2'b00;
reg_en = 4'b0000;
alu_in_sel = 1'b0;
alu_func = `ALU_ADD;
end else begin
case (next_state)
INIT: begin
en_fetch = 1'b0;
en_group = 1'b0;
en_pc = 1'b0;
pc_ctrl = 2'b00;
reg_en = 4'b0000;
alu_in_sel = 1'b0;
alu_func = `ALU_ADD;
end
IF: begin
en_fetch = 1'b1;
en_group = 1'b0;
en_pc = 1'b1;
pc_ctrl = 2'b01;
reg_en = 4'b0000;
alu_in_sel = 1'b0;
alu_func = `ALU_ADD;
end
ID: begin
en_fetch = 1'b0;
en_group = 1'b0;
en_pc = 1'b0;
pc_ctrl = 2'b00;
reg_en = 4'b0000;
alu_in_sel = 1'b0;
alu_func = `ALU_ADD;
end
EX_AL: begin
case (opcode)
`ADD: begin
en_fetch = 1'b0;
en_group = 1'b1;
en_pc = 1'b0;
pc_ctrl = 2'b00;
reg_en = 4'b0000;
alu_in_sel = 1'b1;
alu_func = `ALU_ADD;
end
default: begin
en_fetch = 1'b0;
en_group = 1'b1;
en_pc = 1'b0;
pc_ctrl = 2'b00;
reg_en = 4'b0000;
alu_in_sel = 1'b1;
alu_func = `ALU_ADD;
end
endcase
end
WB: begin
en_fetch = 1'b0;
en_group = 1'b0;
en_pc = 1'b0;
pc_ctrl = 2'b00;
alu_in_sel = 1'b0;
alu_func = 3'b000;
case (rd)
2'b00: reg_en = 4'b0001;
2'b01: reg_en = 4'b0010;
2'b10: reg_en = 4'b0100;
2'b11: reg_en = 4'b1000;
default: reg_en = 4'b0000;
endcase
end
default: begin
en_fetch = 1'b0;
en_group = 1'b0;
en_pc = 1'b0;
pc_ctrl = 2'b00;
reg_en = 4'b0000;
alu_in_sel = 1'b0;
alu_func = 3'b000;
end
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
en_fetch_reg <= 1'b0;
en_pc_reg <= 1'b0;
en_group_reg <= 1'b0;
end else begin
en_fetch_reg <= en_fetch;
en_pc_reg <= en_pc;
en_group_reg <= en_group;
end
end
always @(*) begin
en_fetch_pulse = en_fetch & (~en_fetch_reg);
end
always @(*) begin
en_pc_pulse = en_pc & (~en_pc_reg);
end
always @(*) begin
en_group_pulse = en_group & (~en_group_reg);
end
endmodule
| 7.027363 |
module state_unit (
input clk,
input rst_n,
input [`INST_BUS] inst,
input mem_enable,
output reg [`STATE_BUS] state,
output reg [`STATE_BUS] next_state
);
wire arithmetic = inst == `INST_ADD || inst == `INST_SUB ||
inst == `INST_ADDU || inst == `INST_AND || inst == `INST_OR ||
inst == `INST_XOR || inst == `INST_SLL || inst == `INST_SLT;
wire branch = inst == `INST_BEQ || inst == `INST_BNE || inst == `INST_BLTZ;
wire halt = inst == `INST_HALT;
always @* begin
case (state)
`STATE_IF: next_state = `STATE_ID;
`STATE_ID:
if (arithmetic || branch || mem_enable) next_state = `STATE_EXE;
else if (halt) next_state = `STATE_HALT;
else next_state = `STATE_IF;
`STATE_EXE:
if (arithmetic) next_state = `STATE_WB;
else if (branch) next_state = `STATE_IF;
else if (mem_enable) next_state = `STATE_MEM;
else next_state = `STATE_INVALID;
`STATE_MEM:
if (inst == `INST_LW) next_state = `STATE_WB;
else next_state = `STATE_IF;
`STATE_WB: next_state = `STATE_IF;
`STATE_HALT: next_state = `STATE_HALT;
`STATE_INIT: next_state = `STATE_IF;
`STATE_INVALID: next_state = `STATE_INVALID;
default: next_state = `STATE_IF;
endcase
end
always @(posedge clk, negedge rst_n)
if (!rst_n) state <= `STATE_INIT;
else state <= next_state;
endmodule
| 7.092008 |
module state_update #(
parameter N = 32,
parameter Q = 18,
parameter Ts = 0.00001
) (
input signed [N-1:0] ialpha,
ibeta,
valpha,
vbeta,
omega,
theta,
stheta,
ctheta,
input clk,
reset,
output signed [N-1:0] ialphae,
ibetae,
omegae,
thetae,
output signed [4*4*N-1:0] F,
F_transpose //Jacobian matrix
);
////////////////////////////////////////////////////////////////MACHINE PARAMETERS//////////////////////////////////////////////////////////////
parameter sf = 2 ** Q;
parameter Rs = 1.477;
parameter Lambda = 0.2026;
parameter Ls = 0.0211;
parameter signed [N-1:0] Lambda_Ts_Ls = ((Lambda * Ts) / Ls) * sf;
parameter signed [N-1:0] Rs_Ts_Ls = ((Rs * Ts) / Ls) * sf;
parameter signed [N-1:0] F00 = sf - Rs_Ts_Ls;
parameter signed [N-1:0] Ts_Ls = (Ts / Ls) * sf;
parameter signed [N-1:0] T = Ts * sf;
parameter signed [N-1:0] numerator = 2 ** 31 - 1;
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
wire signed [N-1:0] mult_temp0,mult_temp1,mult_temp2,mult_temp3,mult_temp4,mult_temp5,mult_temp6,mult_temp7,mult_temp8,mult_temp9;
wire of0, of1, of2, of3, of4, of5, of6, of7, of8;
////////////////////////////////////////////////////////////////STATE ESTIMATION///////////////////////////////////////////////////////////////////
//ialphae = ialpha + (valpha -R*ialpha + omega*Lambda*sin(theta)) * (Ts/Ls)
qmult #(Q, N) mult0 (
valpha,
Ts_Ls,
mult_temp0,
of0
);
qmult #(Q, N) mult1 (
ialpha,
Rs_Ts_Ls,
mult_temp1,
of1
);
qmult #(Q, N) mult2 (
omega,
Lambda_Ts_Ls,
mult_temp2,
of2
);
qmult #(Q, N) mult3 (
stheta,
mult_temp2,
mult_temp3,
of3
);
assign ialphae = ialpha + mult_temp0 - mult_temp1 + mult_temp3;
//ibetae = ibeta + (vbeta -R*ibeta - omega*Lambda*cos(theta)) * (Ts/Ls)
qmult #(Q, N) mult4 (
vbeta,
Ts_Ls,
mult_temp4,
of4
);
qmult #(Q, N) mult5 (
ibeta,
Rs_Ts_Ls,
mult_temp5,
of5
);
qmult #(Q, N) mult7 (
ctheta,
mult_temp2,
mult_temp7,
of7
);
assign ibetae = ibeta + mult_temp4 - mult_temp5 - mult_temp7;
// omegae = omega
assign omegae = omega;
//thetae = theta + omega*Ts
qmult #(Q, N) mult6 (
omega,
T,
mult_temp6,
of6
);
assign thetae = theta + mult_temp6;
///////////////////////////////////////////////////////////////////JACOBIAN MATRIX////////////////////////////////////////////////////////////////////
//Jacobian Matrix coefficients
wire signed [N-1:0] F0[0:3], F1[0:3], F2[0:3], F3[0:3]; //Line 1 to 4
qmult #(Q, N) mult9 (
Lambda_Ts_Ls,
stheta,
mult_temp9,
of9
);
//Line 1
assign F0[0] = F00; // 1 - R*Ts/Ls
assign F0[1] = 0;
assign F0[2] = mult_temp9; // sin(theta)*(Lambda*Ts/Ls)
assign F0[3] = mult_temp7; // omega*cos(theta)*(Lambda*Ts/Ls)
qmult #(Q, N) mult8 (
Lambda_Ts_Ls,
ctheta,
mult_temp8,
of8
);
//Line 2
assign F1[0] = 0;
assign F1[1] = F00; // 1 - R*Ts/Ls
assign F1[2] = -mult_temp8; // -cos(theta)*(Lambda*Ts/Ls)
assign F1[3] = mult_temp3; // omega*sin(theta)*(Lambda*Ts/ls)
//Line 3
assign F2[0] = 0;
assign F2[1] = 0;
assign F2[2] = sf;
assign F2[3] = 0;
//Line 4
assign F3[0] = 0;
assign F3[1] = 0;
assign F3[2] = T;
assign F3[3] = sf;
assign F = {
F3[3],
F3[2],
F3[1],
F3[0],
F2[3],
F2[2],
F2[1],
F2[0],
F1[3],
F1[2],
F1[1],
F1[0],
F0[3],
F0[2],
F0[1],
F0[0]
};
assign F_transpose = {
F3[3],
F2[3],
F1[3],
F0[3],
F3[2],
F2[2],
F1[2],
F0[2],
F3[1],
F2[1],
F1[1],
F0[1],
F3[0],
F2[0],
F1[0],
F0[0]
};
endmodule
| 6.58873 |
module StaticImage #(
parameter IMG_WIDTH = 200,
parameter IMG_HEIGHT = 150
) (
input clock,
input reset,
input start,
output reg start_ack,
input ready,
output valid,
output [7:0] pixel
);
localparam OUT_WIDTH = 800, OUT_HEIGHT = 600;
localparam IMG_N_PIXEL = IMG_WIDTH * IMG_HEIGHT,
IMG_X_START = (OUT_WIDTH-IMG_WIDTH)/2,
IMG_Y_START = (OUT_HEIGHT-IMG_HEIGHT)/2;
wire [7:0] pixel_data;
reg [9:0] img_row, img_col;
reg [14:0] img_pxl;
wire row_active, col_active, pxl_active;
assign col_active = (img_col > (IMG_X_START - 1)) & (img_col < (IMG_X_START + IMG_WIDTH));
assign row_active = (img_row > (IMG_Y_START - 1)) & (img_row < (IMG_Y_START + IMG_HEIGHT));
assign pxl_active = row_active & col_active;
IMG_MEM img_mem (
.clka (clock),
.addra(img_pxl),
.douta(pixel_data)
);
assign pixel = pxl_active ? pixel_data : 8'd0;
assign valid = (img_row < OUT_HEIGHT);
wire start_edge;
reg start_ack_r;
assign start_edge = start_ack_r & ~start_ack;
always @(posedge clock) begin
if (reset) begin
img_row <= OUT_HEIGHT;
img_col <= OUT_WIDTH;
img_pxl <= 15'd0;
start_ack <= 1'b0;
start_ack_r <= 1'b0;
end else begin
start_ack <= start;
start_ack_r <= start_ack;
if (start_edge) begin
img_row <= 10'd0;
img_col <= 10'd0;
end else if (valid & ready) begin
if (img_col == (OUT_WIDTH - 1)) begin
img_col <= 10'd0;
img_row <= img_row + 10'd1;
end else img_col <= img_col + 10'd1;
end
if (start_edge) img_pxl <= 15'd0;
else if (pxl_active) img_pxl <= img_pxl + 15'd1;
end
end
endmodule
| 7.965751 |
module StaticImageBlank (
input clock,
input reset,
input [7:0] pixel,
input valid,
output readyStatic,
output readyDown,
output [7:0] pixelout
);
localparam ROW_COMPARE = 1200;
localparam COL_COMPARE = 1200;
reg [12:0] rowcount;
reg [12:0] colcount;
wire [12:0] nextcolcount;
wire [12:0] nextrowcount;
assign nextrowcount = ((rowcount == ROW_COMPARE && colcount == COL_COMPARE) ? 0 : (colcount == COL_COMPARE ? rowcount + 1 : rowcount));
assign nextcolcount = (colcount == COL_COMPARE ? 0 : (valid ? colcount + 1 : colcount));
assign readyStatic = (rowcount < 600) && (colcount < 800);
assign readyDown = (rowcount < 600) && (colcount < 800) && valid;
assign pixelout = readyDown ? pixel : 0;
always @(posedge clock) begin
if (reset) begin
rowcount <= 0;
colcount <= 0;
end else begin
rowcount <= nextrowcount;
colcount <= nextcolcount;
end
end
endmodule
| 7.497743 |
module staticRamDiscretePorts (
address, // Address Input
data, // Data input
we_,
clock,
Q //output
);
parameter ROMFILE = "noFile";
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 8;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
//--------------Input Ports-----------------------
input [ADDR_WIDTH-1:0] address;
input [DATA_WIDTH-1:0] data;
input we_;
input clock;
//--------------Output Ports-----------------------
output reg [DATA_WIDTH-1:0] Q;
integer i;
//--------------Internal variables----------------
reg [DATA_WIDTH-1:0] mem[RAM_DEPTH-1:0];
//--------------Code Starts Here------------------
initial begin
$readmemb(ROMFILE, mem);
for (i = 0; i < RAM_DEPTH; i = i + 1) begin
//#1 $display("%d",mem[i]);
end
end
always @(posedge clock) begin
if (!we_) begin
mem[address] <= data;
end else begin
Q <= mem[address];
end
end
endmodule
| 7.6946 |
module W0RM_Static_Timer #(
parameter LOAD = 0,
parameter LIMIT = 2
) (
input wire clk,
input wire start,
output wire stop
);
// log base 2 function
function integer log2(input integer n);
integer i, j;
begin
i = 1;
j = 0;
//integer i = 1, j = 0;
while (i < n) begin
j = j + 1;
i = i << 1;
end
log2 = j;
end
endfunction
localparam TIMER_BITS = log2(LIMIT);
reg [TIMER_BITS-1:0] timer = 0;
reg go = 0;
reg stop_r = 0;
always @(posedge clk) begin
if (go) begin
if (timer == LIMIT) begin
timer <= 0;
go <= 0;
stop_r <= 1;
end else begin
timer <= timer + 1;
end
end else if (start) begin
timer <= LOAD;
go <= 1;
stop_r <= 0;
end else begin
go <= 0;
timer <= 0;
stop_r <= 0;
end
end
assign stop = stop_r;
endmodule
| 6.769402 |
module static_background (
input blank,
input [10:0] hcount, // Screen placement horizontal
input [10:0] vcount, // Screen placement vertical
output r,
output g, // Color Output
output b
);
assign r = (((hcount < 640) && (hcount >= 0) && (((vcount < 40) && (vcount >= 0)) || ((vcount <= 480) && (vcount > 440))) && (blank == 0)) // Top/Bottom Bar
|| ((hcount < 40) && (hcount >= 0) && (((vcount < 210) && (vcount >= 100)) || ((vcount < 380) && (vcount >= 270))) && (blank == 0)) // Left Bars
|| ((hcount < 640) && (hcount >= 600) && (((vcount < 210) && (vcount >= 100)) || ((vcount < 380) && (vcount >= 270))) && (blank == 0)) // Right Bars
|| ((hcount < 290) && (hcount >= 100) && (((vcount < 210) && (vcount >= 100)) || ((vcount < 380) && (vcount >= 270))) && (blank == 0)) // Left Blocks Center
|| ((hcount < 540) && (hcount >= 350) && (((vcount < 210) && (vcount >= 100)) || ((vcount < 380) && (vcount >= 270))) && (blank == 0)) // Right Blocks Center
) ? 1'b1 : 1'b0;
assign g = 1'b0;
assign b = 1'b0;
endmodule
| 7.160647 |
module static_phy_read #(
parameter integer DQS_WIDTH = 4
) (
input wire clk0,
input wire ctrl_rden,
input wire [ 3:0] phy_calib_rden_delay,
output wire [DQS_WIDTH-1:0] phy_calib_rden
);
genvar i;
generate
for (i = 0; i < DQS_WIDTH; i = i + 1) begin : gen_phy_calib_rden
static_phy_srl_delay srl_delay_phy_calib_rden (
.Clk (clk0),
.Data (ctrl_rden),
.Delay(phy_calib_rden_delay),
.Q (phy_calib_rden[i])
);
end
endgenerate
endmodule
| 6.669854 |
module static_reg #(
parameter WIDTH = 1
) (
input wire clk,
input wire reset_n,
input wire [WIDTH-1:0] static_i,
output wire [WIDTH-1:0] static_o
);
//internal signals
reg [WIDTH-1:0] static_r;
reg static_up;
wire static_en;
//---------------------------
//Main Code
//---------------------------
always @(posedge clk) begin
if (static_en) begin
static_r[WIDTH-1:0] <= static_i[WIDTH-1:0];
end
end
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
static_up <= 1'b1;
end else if (static_en) begin
static_up <= 1'b0;
end
end
//Enable for registers
assign static_en = static_up;
//assign outputs
assign static_o[WIDTH-1:0] = static_r[WIDTH-1:0];
endmodule
| 9.735885 |
module of the design
`timescale 1 ns/100 ps
module status_signal(fifo_full, fifo_empty, fifo_threshold, fifo_overflow, fifo_underflow, wr, rd, fifo_we, fifo_rd, wptr,rptr,clk,rst_n);
input wr, rd, fifo_we, fifo_rd,clk,rst_n;
input[4:0] wptr, rptr;
output fifo_full, fifo_empty, fifo_threshold, fifo_overflow, fifo_underflow;
wire fbit_comp, overflow_set, underflow_set;
wire pointer_equal;
wire[4:0] pointer_result;
reg fifo_full, fifo_empty, fifo_threshold, fifo_overflow, fifo_underflow;
assign fbit_comp = wptr[4] ^ rptr[4];
assign pointer_equal = (wptr[3:0] - rptr[3:0]) ? 0:1;
assign pointer_result = wptr[4:0] - rptr[4:0];
assign overflow_set = fifo_full & wr;
assign underflow_set = fifo_empty&rd;
always @(*)
begin
fifo_full =fbit_comp & pointer_equal;
fifo_empty = (~fbit_comp) & pointer_equal;
fifo_threshold = (pointer_result[4]||pointer_result[3]) ? 1:0;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n) fifo_overflow <=0;
else if((overflow_set==1)&&(fifo_rd==0))
fifo_overflow <=1;
else if(fifo_rd)
fifo_overflow <=0;
else
fifo_overflow <= fifo_overflow;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n) fifo_underflow <=0;
else if((underflow_set==1)&&(fifo_we==0))
fifo_underflow <=1;
else if(fifo_we)
fifo_underflow <=0;
else
fifo_underflow <= fifo_underflow;
end
endmodule
| 8.52834 |
module W0RM_Static_Timer_tb;
reg clk = 0;
reg start = 0;
always #2.5 clk <= ~clk;
initial begin
#11 start = 1;
#5 start = 0;
end
W0RM_Static_Timer #(
.LOAD (0),
.LIMIT(7)
) timer_0_7 (
.clk (clk),
.start(start),
.stop (stop_timer_0_7)
);
W0RM_Static_Timer #(
.LOAD (1),
.LIMIT(12)
) timer_1_12 (
.clk (clk),
.start(start),
.stop (stop_timer_1_12)
);
W0RM_Static_Timer #(
.LOAD (0),
.LIMIT(200)
) timer_0_200 (
.clk (clk),
.start(start),
.stop (stop_timer_0_200)
);
W0RM_Static_Timer #(
.LOAD (0),
.LIMIT(4)
) timer_0_4 (
.clk (clk),
.start(start),
.stop (stop_timer_0_4)
);
endmodule
| 6.769402 |
module station(
input clk,
input iq,
input signed [17:0] drive, // not counting beam
input start,
input signed [17:0] mech_x,
input signed [17:0] piezo,
input start_outer,
// Output ADCs at 20 MHz IF
output signed [15:0] a_field,
output signed [15:0] a_forward,
output signed [15:0] a_reflect,
output signed [17:0] cav_eig_drive,
output signed [17:0] piezo_eig_drive,
input [11:0] beam_timing,
// Local Bus for simulator configuration
`AUTOMATIC_self
);
`AUTOMATIC_decode
`define SAT(x,old,new) ((~|x[old:new] | &x[old:new]) ? x[new:0] : {x[old],{new{~x[old]}}})
`define UNIFORM(x) ((~|(x)) | &(x)) // All 0's or all 1's
// Virtual Piezo
// Couple the piezo to mechanical drive
(* lb_automatic *)
outer_prod piezo_couple // auto
(.clk(clk), .start(start_outer), .x(piezo), .result(piezo_eig_drive),
`AUTOMATIC_piezo_couple
);
// Amplifier compression step
wire signed [17:0] compress_out;
(* lb_automatic *)
a_compress compr // auto
(.clk(clk), .iq(iq), .d_in(drive), .d_out(compress_out),
`AUTOMATIC_compr);
reg signed [17:0] compress_out_d=0;
always @(posedge clk) compress_out_d <= compress_out;
wire signed [17:0] ampf_in = compress_out_d; // was drive
// Amplifier low-pass filter, maximum bandwidth 3.75 MHz
wire signed [17:0] amp_out1;
(* lb_automatic *)
lp_pair #(.shift(2)) amp_lp // auto
(.clk(clk), .drive(ampf_in), .drive2(24'b0), .res(amp_out1), `AUTOMATIC_amp_lp);
// Configure number of modes processed
// I don't make it host-settable (at least not yet),
// because of its interaction with interp_span.
parameter n_mech_modes = 7;
parameter n_cycles = n_mech_modes * 2;
parameter interp_span = 4; // ceil(log2(n_cycles))
parameter mode_count = 3;
// Allow tweaks to the cavity electrical eigenmode time scale
parameter mode_shift=18;
// Control how much frequency shifting is possible with mechanical displacement
parameter df_scale=0; // see cav_freq.v
// Instantiate one cavity
wire signed [17:0] field, forward, reflect;
(* lb_automatic *)
cav_elec #(.mode_shift(mode_shift), .interp_span(interp_span), .df_scale(df_scale), .mode_count(mode_count)) cav_elec // auto
(.clk(clk),
.iq(iq), .drive(amp_out1), .beam_timing(beam_timing),
.field(field), .forward(forward), .reflect(reflect),
.start(start), .mech_x(mech_x), .eig_drive(cav_eig_drive),
`AUTOMATIC_cav_elec
);
// Pseudorandom number subsystem
wire [31:0] rnda, rndb;
(* lb_automatic *)
prng prng // auto
(.clk(clk), .rnda(rnda), .rndb(rndb),
`AUTOMATIC_prng);
// ADCs themselves
// Offsets could be allowed to drift
(* lb_automatic *)
adc_em #(.del(1)) a_cav // auto
(.clk(clk), .strobe(iq), .in(field), .rnd(rnda[12: 0]), .adc(a_field), `AUTOMATIC_a_cav);
(* lb_automatic *)
adc_em #(.del(1)) a_for // auto
(.clk(clk), .strobe(iq), .in(forward), .rnd(rnda[25:13]), .adc(a_forward), `AUTOMATIC_a_for);
(* lb_automatic *)
adc_em #(.del(1)) a_rfl // auto
(.clk(clk), .strobe(iq), .in(reflect), .rnd(rndb[12: 0]), .adc(a_reflect), `AUTOMATIC_a_rfl);
endmodule
| 6.930712 |
module station_management_tb ();
reg reset;
reg clock;
wire mdc;
reg mdi;
wire mdo;
reg mode;
reg begin_transaction;
reg [4:0] phy_address;
reg [4:0] reg_address;
reg [15:0] data_in;
wire [15:0] data_out;
station_management U_station_management
(
.reset(reset),
.clock(clock),
.mdc(mdc),
.mdi(mdi),
.mdo(mdo),
.mode(mode),
.begin_transaction(begin_transaction),
.phy_address(phy_address),
.reg_address(reg_address),
.data_in(data_in),
.data_out(data_out)
);
integer i;
initial
begin
$dumpfile("test.vcd");
$dumpvars(0,station_management_tb);
end
initial
begin
mdi = 0;
reset = 1;
clock = 1;
mode = 0;
begin_transaction = 0;
phy_address = 5'b00001;
reg_address = 5'b00010;
data_in = 16'hFEDC;
#20 reset = 0;
#20 begin_transaction = 1;
#10 begin_transaction = 0;
#490
for (i=0; i<16; i = i + 1)
begin
reading_bit((i%2)? 1'b1 : 1'b0);
end
mdi = 0;
#50
$finish();
end
always
#5 clock = ~clock;
task reading_bit;
input bit;
begin
mdi = bit;
@(posedge mdc);
end
endtask
task writing_bit;
begin
@(posedge mdc);
end
endtask
endmodule
| 6.70789 |
module station_management_tb ();
reg reset;
reg clock;
wire mdc;
reg mdi;
wire mdo;
reg mode;
reg begin_transaction;
reg [4:0] phy_address;
reg [4:0] reg_address;
reg [15:0] data_in;
wire [15:0] data_out;
station_management U_station_management
(
.reset(reset),
.clock(clock),
.mdc(mdc),
.mdi(mdi),
.mdo(mdo),
.mode(mode),
.begin_transaction(begin_transaction),
.phy_address(phy_address),
.reg_address(reg_address),
.data_in(data_in),
.data_out(data_out)
);
integer i;
initial
begin
$dumpfile("test.vcd");
$dumpvars(0,station_management_tb);
end
initial
begin
mdi = 0;
reset = 1;
clock = 1;
mode = 0;
begin_transaction = 0;
phy_address = 5'b00001;
reg_address = 5'b00010;
data_in = 16'hFEDC;
#20 reset = 0;
#20 begin_transaction = 1;
#10 begin_transaction = 0;
#490
for (i=0; i<16; i = i + 1)
begin
reading_bit((i%2)? 1'b1 : 1'b0);
end
mdi = 0;
#50
$finish();
end
always
#5 clock = ~clock;
task reading_bit;
input bit;
begin
mdi = bit;
@(posedge mdc);
end
endtask
task writing_bit;
begin
@(posedge mdc);
end
endtask
endmodule
| 6.70789 |
module statistic (
input [31:0] A,
input [31:0] B,
input clk,
input rst,
input syscall_t,
input condi_suc,
input un_branch_t,
input branch_t,
input strong_halt,
// output for convenience, bit width set as 32
output reg [31:0] total_cycles,
output reg [31:0] uncondi_num,
output reg [31:0] condi_num,
output reg [31:0] condi_suc_num,
output reg [31:0] SyscallOut
);
// there are slightly different form the logisim
wire is_show;
assign is_show = (A != 32'd10) && (A != 32'd50) && syscall_t;
initial begin
total_cycles = 0;
uncondi_num = 0;
condi_num = 0;
condi_suc_num = 0;
SyscallOut = 0;
end
always @(posedge clk) begin
if (rst) begin
total_cycles <= 0;
uncondi_num <= 0;
condi_num <= 0;
condi_suc_num <= 0;
SyscallOut <= 0;
end else begin
if (strong_halt) begin
total_cycles = total_cycles + 1;
end
if (strong_halt & un_branch_t) begin
uncondi_num = uncondi_num + 1;
end
if (strong_halt & branch_t) begin
condi_num = condi_num + 1;
end
if (strong_halt & condi_suc) begin
condi_suc_num = condi_suc_num + 1;
end
if (is_show) begin
SyscallOut = B;
end
end
end
endmodule
| 7.65806 |
module statistic_accum #(
parameter DATA_WIDTH = 16,
parameter BOUND_WIDTH = 10, // ширина границам
parameter BOUND_NUM = 32, // количесвто границ
parameter BOUND_NUM_WIDTH = 5 // количество бит в которые можно записать число BOUND_NUM
) (
input clk,
input reset_n,
input data_val_i, // сигнал валидности от кордика
input start_search_max, // должен быть выставлен до тех пор, пока не появится data_val_o
input clear_i, // обнуление массива при новом цикле накопления точек
input [DATA_WIDTH-1:0] data_i,
output data_val_o,
output [ BOUND_NUM_WIDTH-1:0] max_num_o,
output [DATA_WIDTH*BOUND_NUM-1:0] arr_o
);
reg [DATA_WIDTH-1:0] hit_arr[0:BOUND_NUM-1];
// Распределение точек по границам.
genvar i;
generate
for (i = 0; i < BOUND_NUM; i = i + 1) begin
always @(posedge clk) begin
if (!reset_n || clear_i) begin
hit_arr[i] <= 0;
end else if (data_val_i) begin
if ((data_i >= i * BOUND_WIDTH) && (data_i < i * BOUND_WIDTH + BOUND_WIDTH)) begin
hit_arr[i] <= hit_arr[i] + 1;
end
end
end
end
endgenerate
// Преобразование массива в один длинный регистр.
generate
for (i = 0; i < BOUND_NUM; i = i + 1) begin
assign arr_o[(i*DATA_WIDTH+DATA_WIDTH)-1 : i*DATA_WIDTH] = hit_arr[i];
end
endgenerate
reg data_val;
reg [DATA_WIDTH-1:0] max_value;
reg [BOUND_NUM_WIDTH:0] max_num, cnt_max = 0;
// Поиск максимума.
always @(posedge clk) begin
if (!reset_n || clear_i) begin
cnt_max <= 0;
max_num <= 0;
max_value <= 0;
data_val <= 0;
end else if (start_search_max) begin
// Пройти по всему массиву и запомнить максимум
// и номер ячейки в котором был максимум
if (cnt_max < BOUND_NUM) begin
if (max_value < hit_arr[cnt_max]) begin
max_value <= hit_arr[cnt_max];
max_num <= cnt_max;
end
cnt_max <= cnt_max + 1;
end else begin
data_val <= 1;
end
end
end
assign data_val_o = data_val;
assign max_num_o = max_num;
endmodule
| 6.967717 |
module statreg (
in,
enable,
out
);
/*
* STATUS REGISTER - statreg.v
*
* Inputs:
* - in (4 bits): The status bits generated by the ALU. The status register
* saves these bits so that the control unit can use them in branches.
* For a description of the status bits, see the description of alu.v.
* - enable: When this is set to 1, the values of in are saved.
*
* Outputs:
* - out (4 bits): The status bits saved from the ALU.
*
*/
input [3:0] in;
input enable;
output [3:0] out;
reg [3:0] outreg;
initial outreg = 4'b0000;
always @(enable, in) if (enable == 1'b1) outreg = in;
assign out = outreg;
endmodule
| 7.660307 |
module stats16 #(
parameter BASE = 0
) (
input wire clk,
input wire pps,
input wire [15:0] data,
// IO
input [7:0] port_id,
output [7:0] in_port,
input read_strobe
);
// data
reg [15:0] min;
reg [15:0] max;
reg [15:0] chg0;
reg [15:0] chg1;
// stats
reg [15:0] smin;
reg [15:0] smax;
reg [15:0] avg;
// main logic
always @(posedge clk) begin
if (pps == 1'b1) begin
// init
min <= data;
max <= data;
chg0 <= data;
chg1 <= 0;
// stats
smin <= min;
smax <= max;
avg <= ({1'b0, min} + {1'b0, max}) >> 1;
end else begin
// collect
min <= (data < min) ? data : min;
max <= (data > max) ? data : max;
chg1 <= chg1 | (data ^ chg0);
end
end
// read
assign in_port =
(port_id == BASE + 1) ? smin[7:0] :
((port_id == BASE + 0) ? smin[15:8] :
((port_id == BASE + 3) ? smax[7:0] :
((port_id == BASE + 2) ? smax[15:8] :
((port_id == BASE + 5) ? avg[7:0] :
((port_id == BASE + 4) ? avg[15:8] :
((port_id == BASE + 7) ? chg1[7:0] :
((port_id == BASE + 6) ? chg1[15:8] : 8'bz)))))));
endmodule
| 7.801978 |
module stats_dma_latency #(
// Counter width (bits)
parameter COUNT_WIDTH = 16,
// Tag width (bits)
parameter TAG_WIDTH = 8,
// Length field width (bits)
parameter LEN_WIDTH = 16,
// Status field width (bits)
parameter STATUS_WIDTH = 4
) (
input wire clk,
input wire rst,
/*
* Tag inputs
*/
input wire [ TAG_WIDTH-1:0] in_start_tag,
input wire [ LEN_WIDTH-1:0] in_start_len,
input wire in_start_valid,
input wire [ TAG_WIDTH-1:0] in_finish_tag,
input wire [STATUS_WIDTH-1:0] in_finish_status,
input wire in_finish_valid,
/*
* Statistics increment output
*/
output wire [ TAG_WIDTH-1:0] out_tag,
output wire [ LEN_WIDTH-1:0] out_len,
output wire [STATUS_WIDTH-1:0] out_status,
output wire [ COUNT_WIDTH-1:0] out_latency,
output wire out_valid
);
reg [COUNT_WIDTH-1:0] count_reg = 0;
reg [TAG_WIDTH-1:0] out_tag_reg = 0;
reg [LEN_WIDTH-1:0] out_len_reg = 0;
reg [STATUS_WIDTH-1:0] out_status_reg = 0;
reg [COUNT_WIDTH-1:0] out_latency_reg = 0;
reg out_valid_reg = 1'b0;
assign out_tag = out_tag_reg;
assign out_len = out_len_reg;
assign out_status = out_status_reg;
assign out_latency = out_latency_reg;
assign out_valid = out_valid_reg;
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [LEN_WIDTH-1:0] len_mem_reg[2**TAG_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [COUNT_WIDTH-1:0] count_mem_reg[2**TAG_WIDTH-1:0];
integer i;
initial begin
for (i = 0; i < 2 ** TAG_WIDTH; i = i + 1) begin
len_mem_reg[i] = 0;
count_mem_reg[i] = 0;
end
end
always @(posedge clk) begin
count_reg <= count_reg + 1;
out_tag_reg <= 0;
out_len_reg <= 0;
out_status_reg <= 0;
out_latency_reg <= 0;
out_valid_reg <= 0;
if (in_start_valid) begin
len_mem_reg[in_start_tag] <= in_start_len;
count_mem_reg[in_start_tag] <= count_reg;
end
if (in_finish_valid) begin
out_tag_reg <= in_finish_tag;
out_len_reg <= len_mem_reg[in_finish_tag];
out_status_reg <= in_finish_status;
out_latency_reg <= count_reg - count_mem_reg[in_finish_tag];
out_valid_reg <= 1'b1;
end
if (rst) begin
count_reg <= 0;
out_tag_reg <= 0;
out_len_reg <= 0;
out_status_reg <= 0;
out_latency_reg <= 0;
out_valid_reg <= 0;
end
end
endmodule
| 6.574299 |
module status (
data,
Z,
N
);
input [15:0] data;
output reg N, Z;
always @* begin
if (data == 0) begin
Z <= 1;
N <= 0;
end else if (data[15] == 1'b1) begin
Z <= 0;
N <= 1;
end else begin
Z <= 0;
N <= 0;
end
end
endmodule
| 6.54827 |
module. It is responsible for
// displaying Mouse Status on the on-board LEDs.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module StatusLED(
input RESET,
input CLK,
inout [7:0] BUS_DATA,
input [7:0] BUS_ADDR,
input BUS_WE,
output reg [7:0] StatusLED
);
//Define the BUS_ADDR for the StatusLEDs
parameter [7:0] StatusLEDBaseAddr = 8'hC0;
//Tristate bus read controler
reg TransmitX;
//if the WriteEnable is high, we read the status from the data bus to the internal register
always@(posedge CLK) begin
if((BUS_ADDR == StatusLEDBaseAddr) & BUS_WE)
StatusLED <= BUS_DATA;
end
//if the WriteEnable is low, we transmit the status from the internal register
//otherwise, we keep the data bus at high impedance.
always@(posedge CLK) begin
if((BUS_ADDR == StatusLEDBaseAddr) & ~BUS_WE)
TransmitX <= 1'b1;
else
TransmitX <= 1'b0;
end
assign BUS_DATA = (TransmitX) ? StatusLED : 8'hZZ;
endmodule
| 7.574457 |
module Status_Engine (
clk,
rst,
// input(s)
i_SET_ID,
i_Status_En,
i_RAM_Data,
i_Mask_Data,
// output(s)
o_SETID_MOD,
o_Done
);
// ==========================================================================
// == Parameters
// ==========================================================================
parameter KWID = 104; // Key width
parameter IDWID = 8; // Data bits
parameter SEGWID = IDWID + 2; // Segment width + status bit - 10 bits (user predefined)
parameter MASKWID = KWID / 8; // 13
parameter DATA = SEGWID + MASKWID; // 23
// ==========================================================================
// == Local Parameters
// ==========================================================================
localparam IDLE = 1'b0;
localparam ST1 = 1'b1;
// ==========================================================================
// == Port Declarations
// ==========================================================================
input clk;
input rst;
input [IDWID-1:0] i_SET_ID;
input i_Status_En;
input [DATA-1:0] i_RAM_Data;
input [MASKWID-1:0] i_Mask_Data;
output [DATA-1:0] o_SETID_MOD;
output o_Done;
// ==========================================================================
// == Signal Declaraions
// ==========================================================================
reg PS, NS;
reg Done;
reg [DATA-1:0] Mod_ID;
// ==========================================================================
// == Architecture: FSM
// ==========================================================================
// ====================
// -- Cell_Empty
wire Cell_Empty;
assign Cell_Empty = (i_RAM_Data[22:21] == 2'b00);
// ====================
// == Current State : Synchronous Process
always @(posedge clk or posedge rst) // -- Async Reset
begin
if (rst) PS <= IDLE;
else if (i_Status_En == 0) PS <= IDLE;
else PS <= NS;
end
// == Next State Logic : Combinational Process
always @(PS, i_RAM_Data, i_SET_ID) begin
case (PS)
IDLE: begin
Done <= 1'b0;
Mod_ID <= {2'b01, i_SET_ID, i_Mask_Data};
NS <= ST1;
end
ST1: begin
Done <= 1'b1;
NS <= IDLE;
if (!Cell_Empty) Mod_ID <= {2'b11, i_RAM_Data[20:0]};
else Mod_ID <= {2'b01, i_SET_ID, i_Mask_Data};
end
default: begin
NS <= IDLE;
Done <= 1'b0;
end
endcase
end
// ==========================================================================
// == Output Assignments
// ==========================================================================
assign o_SETID_MOD = Mod_ID;
assign o_Done = Done;
endmodule
| 7.116012 |
module Status_Register (
input [3:0] Status_in,
input clk,
S,
output reg [3:0] Status
);
initial Status = 4'b0000;
always @(negedge clk) begin
if (S) Status <= Status_in;
end
endmodule
| 7.180259 |
module status_register_32_bits (
output reg [31:0] Q,
input [31:0] D,
input LE,
CLR,
CLK
);
initial Q = 32'b0000000000000000000000000000000; // Start registers with 0
always @(negedge CLK, negedge CLR)
if (!LE) Q <= D; // Enable Sync. Only occurs when Clk is high
else if (!CLR) // clear
Q <= 32'b0000000000000000000000000000000; // Clear Async
else Q <= Q; // enable off. output what came out before
endmodule
| 8.068783 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module status_router4(
input rst,
input clk,
input srst, // @ posedge clk
// 4 input channels
input [7:0] db_in0,
input rq_in0,
output start_in0, // only for the first cycle, combinatorial
input [7:0] db_in1,
input rq_in1,
output start_in1, // only for the first cycle, combinatorial
input [7:0] db_in2,
input rq_in2,
output start_in2, // only for the first cycle, combinatorial
input [7:0] db_in3,
input rq_in3,
output start_in3, // only for the first cycle, combinatorial
// output (multiplexed) channel
output [7:0] db_out,
output rq_out,
input start_out // only for the first cycle, combinatorial
);
wire [7:0] db_int [1:0];
wire [1:0] rq_int;
wire [1:0] start_int; // only for the first cycle, combinatorial
status_router2 #(
.FIFO_TYPE ("TWO_CYCLE") //= "ONE_CYCLE" // higher latency, but easier timing - use on some levels (others - default "ONE_CYCLE")
) status_router2_top_i (
.rst (rst), // input
.clk (clk), // input
.srst (srst), // input
.db_in0 (db_int[0]), // input[7:0]
.rq_in0 (rq_int[0]), // input
.start_in0 (start_int[0]), // output
.db_in1 (db_int[1]), // input[7:0]
.rq_in1 (rq_int[1]), // input
.start_in1 (start_int[1]), // output
.db_out (db_out), // output[7:0]
.rq_out (rq_out), // output
.start_out (start_out) // input
);
status_router2 status_router2_01_i (
.rst (rst), // input
.clk (clk), // input
.srst (srst), // input
.db_in0 (db_in0), // input[7:0]
.rq_in0 (rq_in0), // input
.start_in0 (start_in0), // output
.db_in1 (db_in1), // input[7:0]
.rq_in1 (rq_in1), // input
.start_in1 (start_in1), // output
.db_out (db_int[0]), // output[7:0]
.rq_out (rq_int[0]), // output
.start_out (start_int[0]) // input
);
status_router2 status_router2_23_i (
.rst (rst), // input
.clk (clk), // input
.srst (srst), // input
.db_in0 (db_in2), // input[7:0]
.rq_in0 (rq_in2), // input
.start_in0 (start_in2), // output
.db_in1 (db_in3), // input[7:0]
.rq_in1 (rq_in3), // input
.start_in1 (start_in3), // output
.db_out (db_int[1]), // output[7:0]
.rq_out (rq_int[1]), // output
.start_out (start_int[1]) // input
);
endmodule
| 8.081644 |
module stat_counter (
// Clock and Reset Signals
sys_clk,
s_reset_n,
count_inc,
count_dec,
reg_sel,
reg_wr_data,
reg_wr,
cntr_intr,
cntrout
);
parameter CWD = 1; // Counter Width
//-------------------- Parameters -------------------------------------
// ------------------- Clock and Reset Signals ------------------------
input sys_clk;
input s_reset_n;
input count_inc; // Counter Increment
input count_dec; // counter decrement, assuption does not under flow
input reg_sel;
input reg_wr;
input [CWD-1:0] reg_wr_data;
output cntr_intr;
output [CWD-1:0] cntrout;
// ------------------- Register Declarations --------------------------
reg [CWD-1:0] reg_trig_cntr;
// ------------------- Logic Starts Here ----------------------------------
always @(posedge sys_clk or negedge s_reset_n) begin
if (s_reset_n == 1'b0) begin
reg_trig_cntr <= 'b0;
end else begin
if (reg_sel && reg_wr) begin
reg_trig_cntr <= reg_wr_data;
end else begin
if (count_inc && count_dec) reg_trig_cntr <= reg_trig_cntr;
else if (count_inc) reg_trig_cntr <= reg_trig_cntr + 1'b1;
else if (count_dec) reg_trig_cntr <= reg_trig_cntr - 1'b1;
else reg_trig_cntr <= reg_trig_cntr;
end
end
end
// only increment overflow is assumed
// decrement underflow is not handled
assign cntr_intr = ((reg_trig_cntr + 1) == 'h0 && count_inc);
assign cntrout = reg_trig_cntr;
endmodule
| 6.702345 |
module stat_sprite_mem (
clock,
select,
x,
y,
out
);
//select -> number of the sprite -> 64 posibilities
//x -> w position of the pixel in the 16x16 array
input clock;
input [3:0] x, y;
input [5:0] select;
output reg [1:0] out;
wire [1:0] sprite1;
wire [1:0] sprite2;
//....continue to make sprites for more moving sprites
wire [7:0] address;
assign address = {x, y};
//first bit of the sprite pattern
//pattern loaded in mif-file: sprite1.mif
ram_stat_sprite1 rms1 (
.clock(clock),
.address(address),
.wren(1'b0),
.data({2{1'b0}}),
.q(sprite1)
);
//pattern loaded in mif-file: sprite1.mif
ram_stat_sprite2 rms2 (
.clock(clock),
.address(address),
.wren(1'b0),
.data({2{1'b0}}),
.q(sprite2)
);
//select the correct sprite
always @(select or sprite1 or sprite2) begin
case (select)
0: out = sprite1;
1: out = sprite2;
default: begin
out = 0;
end
endcase
end
endmodule
| 6.960753 |
module stat_top #(
parameter integer bit_width = 64,
parameter integer vec_width_index = 4,
parameter integer vec_width_value = 32,
parameter integer vec_num = 16,
parameter integer vec_width_total = (vec_width_index + vec_width_value) * vec_num
) (
input wire rst,
stat_clk,
data_clk,
input wire up_clk, // unused, should be the same as stat_clk
input wire up_wr,
input wire up_rd,
input wire [32-1:0] up_addr,
input wire [31 : 0] up_data_wr,
output wire [31 : 0] up_data_rd,
input wire clr_in,
output wire clr_done,
input wire tx_stat_chk,
input wire [ 3:0] tx_stat_base_addr,
input wire [ bit_width-1:0] tx_stat_bit,
input wire [vec_width_total-1:0] tx_stat_vec,
input wire rx_stat_chk,
input wire [ 3:0] rx_stat_base_addr,
input wire [ bit_width-1:0] rx_stat_bit,
input wire [vec_width_total-1:0] rx_stat_vec
);
// CPU access
wire up_cs_tx = (up_addr[17] == 1'b0) ? 1'b1 : 1'b0; // rd 0800xxxx
wire up_cs_rx = (up_addr[17] == 1'b1) ? 1'b1 : 1'b0; // rd 0802xxxx
wire [31:0] up_data_rd_rx;
wire [31:0] up_data_rd_tx;
assign up_data_rd = up_cs_rx ? up_data_rd_rx : (up_cs_tx ? up_data_rd_tx : 32'hdeadbeef);
// CTRL to STAT global clear
wire clr_in_cdc;
synchronizer_level clr_in_sync (
.clk_out(stat_clk),
.clk_en (1'b1),
.reset_n(!rst),
.sync_in(clr_in),
.sync_out_p1 (),
.sync_out_reg2(clr_in_cdc)
);
// CPU clear command return
reg [1+3+6-1:0] clr_cntr; // 2*8*64=1024
assign clr_done = (clr_cntr == 10'h3ff) ? 1'b1 : 1'b0;
always @(posedge rst or posedge stat_clk) begin
if (rst) clr_cntr <= 'd0;
else if (clr_in_cdc) clr_cntr <= clr_done ? clr_cntr : (clr_cntr + 'd1);
else clr_cntr <= 'd0;
end
// RX: DATA to STAT packet statistic check point
wire rx_stat_chk_cdc;
synchronizer_level rx_stat_chk_sync (
.clk_out(stat_clk),
.clk_en (1'b1),
.reset_n(!rst),
.sync_in(rx_stat_chk),
.sync_out_p1 (rx_stat_chk_cdc),
.sync_out_reg2()
);
reg [3:0] rx_stat_base_addr_sync;
always @(posedge stat_clk) if (rx_stat_chk_cdc) rx_stat_base_addr_sync <= rx_stat_base_addr;
bit_vec_stat rx_stat_inst (
.rst(rst),
.clk(stat_clk),
.up_rd(up_rd && up_cs_rx),
.up_addr(up_addr),
.up_data_rd(up_data_rd_rx),
.clr_in(clr_in_cdc),
.stat_chk(rx_stat_chk_cdc),
.stat_base_addr(rx_stat_base_addr_sync),
.stat_bit(rx_stat_bit),
.stat_vec(rx_stat_vec)
);
defparam rx_stat_inst.bit_width = bit_width, rx_stat_inst.vec_width_index = vec_width_index,
rx_stat_inst.vec_width_value = vec_width_value, rx_stat_inst.vec_num = vec_num,
rx_stat_inst.vec_width_total = (vec_width_index + vec_width_value) * vec_num;
// TX: DATA to STAT packet statistic check point
wire tx_stat_chk_cdc;
synchronizer_level tx_stat_chk_sync (
.clk_out(stat_clk),
.clk_en (1'b1),
.reset_n(!rst),
.sync_in(tx_stat_chk),
.sync_out_p1 (tx_stat_chk_cdc),
.sync_out_reg2()
);
reg [3:0] tx_stat_base_addr_sync;
always @(posedge stat_clk) if (tx_stat_chk_cdc) tx_stat_base_addr_sync <= tx_stat_base_addr;
bit_vec_stat tx_stat_inst (
.rst(rst),
.clk(stat_clk),
.up_rd(up_rd && up_cs_tx),
.up_addr(up_addr),
.up_data_rd(up_data_rd_tx),
.clr_in(clr_in_cdc),
.stat_chk(tx_stat_chk_cdc),
.stat_base_addr(tx_stat_base_addr_sync),
.stat_bit(tx_stat_bit),
.stat_vec(tx_stat_vec)
);
defparam tx_stat_inst.bit_width = bit_width, tx_stat_inst.vec_width_index = vec_width_index,
tx_stat_inst.vec_width_value = vec_width_value, tx_stat_inst.vec_num = vec_num,
tx_stat_inst.vec_width_total = (vec_width_index + vec_width_value) * vec_num;
endmodule
| 7.26932 |
module sta_rom (
input [4:0] addr,
input [3:0] imm4,
output reg [7:0] label
);
always @(*)
case (addr)
0: label = "S";
1: label = "T";
2: label = "A";
4: label = imm4[3];
5: label = imm4[2];
6: label = imm4[1];
7: label = imm4[0];
default: label = " ";
endcase
endmodule
| 7.020067 |
module stb_extender (
input reset,
// fast clock domain
input clk_in,
input stb_in,
// slow clock domain
input clk_out,
output stb_out
);
reg reg_stb_in, reg_stb_out;
assign stb_out = reg_stb_out;
always @(posedge clk_in or posedge reset)
if (reset) reg_stb_in <= 0;
else begin
if (stb_in) reg_stb_in <= 1;
if (stb_out) reg_stb_in <= 0;
end
always @(posedge clk_out or posedge reset)
if (reset) reg_stb_out <= 0;
else reg_stb_out <= reg_stb_in;
endmodule
| 6.772603 |
module STController (
cp,
resetBtn,
runBtn,
openBtn,
click,
hadFinish,
initTime,
finishTime,
sleepTime,
shinning,
state
);
input cp;
input resetBtn, runBtn, openBtn;
input click;
input hadFinish;
input [2:0] initTime;
input [2:0] finishTime;
input [1:0] sleepTime;
input [2:0] shinning;
output reg [2:0] state = shutDownST;
localparam shutDownST = 0, beginST = 1, setST = 2, runST = 3;
localparam errorST = 4, pauseST = 5, finishST = 6, sleepST = 7;
reg sleep;
reg [2:0] nextState;
always @(posedge cp) begin
if (resetBtn == 0 && state == runST) begin
state <= sleepST;
sleep <= 0;
end else if (resetBtn == 0 && state != sleepST) begin
state <= shutDownST;
sleep <= 1;
end else begin
state <= nextState;
sleep <= 0;
end
end
always @(*) begin
case (state)
shutDownST: begin
if (sleep && resetBtn) begin
nextState = beginST;
end else begin
nextState = shutDownST;
end
end
beginST: begin
if (initTime > 0) begin
nextState = beginST;
end else begin
nextState = setST;
end
end
setST: begin
if (runBtn) begin
nextState = runST;
end else begin
nextState = setST;
end
end
runST: begin
if (!runBtn) begin
nextState = pauseST;
end else if (openBtn && (shinning == 3 || shinning == 7)) begin
nextState = errorST;
end else if (openBtn) begin
nextState = pauseST;
end else if (hadFinish) begin
nextState = finishST;
end else begin
nextState = runST;
end
end
errorST: begin
if (openBtn) begin
nextState = errorST;
end else begin
nextState = runST;
end
end
pauseST: begin
if (runBtn && !openBtn) begin
nextState = runST;
end else if (click) begin
nextState = setST;
end else if (openBtn) begin
nextState = pauseST;
end else begin
nextState = pauseST;
end
end
finishST: begin
if (runBtn == 0) begin
nextState = setST;
end else if (finishTime > 0) begin
nextState = finishST;
end else begin
nextState = shutDownST;
end
end
sleepST: begin
if (resetBtn) begin
nextState <= runST;
end else if (sleepTime == 0) begin
nextState <= shutDownST;
end else begin
nextState <= sleepST;
end
end
endcase
end
endmodule
| 7.490764 |
module stconv (
input [31:0] in,
input [31:0] ir,
output [31:0] out
);
function [31:0] converter;
input [31:0] in;
input [31:0] ir;
case (ir[14:12])
3'b000: converter = {4{in[7:0]}}; // SB
3'b001: converter = {2{in[15:0]}}; // SH
3'b010: converter = in[31:0]; // SW
default: converter = in[31:0]; // SW
endcase
endfunction
assign out = converter(in, ir);
endmodule
| 7.278194 |
module stCU (
input nRST,
//发射控制
input [2:0] Add_Busy, //加减保留站
input [2:0] Mul_Busy, //乘法保留站
input [1:0] Mem_Busy, //访存保留站
input WAW,
input [2:0] stType,
output wire issuable, //cu可发射
output [4:0] stnum,
output insStall //pc暂停取指
);
/* reg [2:0]stType; //指令对应保留站类型 */
reg issueReg;
reg [4:0] stnumReg;
reg full;
initial begin
issueReg = 0;
full = 0;
end
assign issuable = (issueReg && full == 0);
assign insStall = (full || WAW);
assign stnum = stnumReg;
always @(*) begin
//判断保留站是否有空闲
case (stType)
`Addst: begin
if (Add_Busy[2] == 0) begin
issueReg <= 1;
stnumReg <= `Add2;
full <= 0;
end else if (Add_Busy[1] == 0) begin
issueReg <= 1;
stnumReg <= `Add1;
full <= 0;
end else if (Add_Busy[0] == 0) begin
issueReg <= 1;
stnumReg <= `Add0;
full <= 0;
end else full <= 1;
end
`Mulst: begin
if (Mul_Busy[2] == 0) begin
issueReg <= 1;
stnumReg <= `MUL2;
full <= 0;
end else if (Mul_Busy[1] == 0) begin
issueReg <= 1;
stnumReg <= `MUL1;
full <= 0;
end else if (Mul_Busy[0] == 0) begin
issueReg <= 1;
stnumReg <= `MUL0;
full <= 0;
end else full <= 1;
end
`MemLst: begin
if (Mem_Busy[0] == 0) begin
issueReg <= 1;
stnumReg <= `Mem0;
full <= 0;
end else full <= 1;
end
`MemSst: begin
if (Mem_Busy[1] == 0) begin
issueReg <= 1;
stnumReg <= `Mem1;
full <= 0;
end else full <= 1;
end
default: full <= 1;
endcase
end
endmodule
| 6.951967 |
module adder (
sum_out,
carry_out,
carry_in,
ina,
inb
);
output carry_out;
output [3:0] sum_out;
input [3:0] ina, inb;
input carry_in;
wire carry_out, carry_in;
wire [3:0] sum_out, ina, inb;
assign {carry_out, sum_out} = ina + inb + carry_in;
endmodule
| 7.276647 |
module select_bus (
busout,
bus0,
bus1,
bus2,
bus3,
enable,
s
);
parameter n = 16;
parameter Zee = 16'bz;
output [1:n] busout;
input [1:n] bus0, bus1, bus2, bus3;
input enable;
input [1:2] s;
tri [1:n] data;
// net declaration
// net declaration with continuous assignment
tri [1:n] busout = enable ? data : Zee;
// assignment statement with four continuous assignments
assign data = (s == 0) ? bus0 : Zee,
data = (s == 1) ? bus1 : Zee,
data = (s == 2) ? bus2 : Zee,
data = (s == 3) ? bus3 : Zee;
endmodule
| 7.501903 |
module std_fp_add #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left + right;
endmodule
| 9.124708 |
module std_fp_sub #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left - right;
endmodule
| 8.85803 |
module std_fp_mult_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16,
parameter SIGNED = 0
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
input logic go,
input logic clk,
input logic reset,
output logic [WIDTH-1:0] out,
output logic done
);
logic [ WIDTH-1:0] rtmp;
logic [ WIDTH-1:0] ltmp;
logic [(WIDTH << 1) - 1:0] out_tmp;
// Buffer used to walk through the 3 cycles of the pipeline.
logic done_buf[2:0];
assign done = done_buf[2];
assign out = out_tmp[(WIDTH<<1)-INT_WIDTH-1 : WIDTH-INT_WIDTH];
// If the done buffer is completely empty and go is high then execution
// just started.
logic start;
assign start = go & done_buf[0] == 0 & done_buf[1] == 0;
// Start sending the done signal.
always_ff @(posedge clk) begin
if (start) done_buf[0] <= 1;
else done_buf[0] <= 0;
end
// Push the done signal through the pipeline.
always_ff @(posedge clk) begin
if (go) begin
done_buf[2] <= done_buf[1];
done_buf[1] <= done_buf[0];
end else begin
done_buf[2] <= 0;
done_buf[1] <= 0;
end
end
// Move the multiplication computation through the pipeline.
always_ff @(posedge clk) begin
if (reset) begin
rtmp <= 0;
ltmp <= 0;
out_tmp <= 0;
end else if (go) begin
if (SIGNED) begin
rtmp <= $signed(right);
ltmp <= $signed(left);
out_tmp <= $signed({{WIDTH{ltmp[WIDTH-1]}}, ltmp} * {{WIDTH{rtmp[WIDTH-1]}}, rtmp});
end else begin
rtmp <= right;
ltmp <= left;
out_tmp <= ltmp * rtmp;
end
end else begin
rtmp <= 0;
ltmp <= 0;
out_tmp <= out_tmp;
end
end
endmodule
| 6.609331 |
module std_fp_div_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic go,
input logic clk,
input logic reset,
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out_remainder,
output logic [WIDTH-1:0] out_quotient,
output logic done
);
localparam ITERATIONS = WIDTH + FRAC_WIDTH;
logic [WIDTH-1:0] quotient, quotient_next;
logic [WIDTH:0] acc, acc_next;
logic [$clog2(ITERATIONS)-1:0] idx;
logic start, running, finished, dividend_is_zero;
assign start = go && !running;
assign dividend_is_zero = start && left == 0;
assign finished = idx == ITERATIONS - 1 && running;
always_ff @(posedge clk) begin
if (reset || finished || dividend_is_zero) running <= 0;
else if (start) running <= 1;
else running <= running;
end
always_comb begin
if (acc >= {1'b0, right}) begin
acc_next = acc - right;
{acc_next, quotient_next} = {acc_next[WIDTH-1:0], quotient, 1'b1};
end else begin
{acc_next, quotient_next} = {acc, quotient} << 1;
end
end
// `done` signaling
always_ff @(posedge clk) begin
if (dividend_is_zero || finished) done <= 1;
else done <= 0;
end
always_ff @(posedge clk) begin
if (running) idx <= idx + 1;
else idx <= 0;
end
always_ff @(posedge clk) begin
if (reset) begin
out_quotient <= 0;
out_remainder <= 0;
end else if (start) begin
out_quotient <= 0;
out_remainder <= left;
end else if (go == 0) begin
out_quotient <= out_quotient;
out_remainder <= out_remainder;
end else if (dividend_is_zero) begin
out_quotient <= 0;
out_remainder <= 0;
end else if (finished) begin
out_quotient <= quotient_next;
out_remainder <= out_remainder;
end else begin
out_quotient <= out_quotient;
if (right <= out_remainder) out_remainder <= out_remainder - right;
else out_remainder <= out_remainder;
end
end
always_ff @(posedge clk) begin
if (reset) begin
acc <= 0;
quotient <= 0;
end else if (start) begin
{acc, quotient} <= {{WIDTH{1'b0}}, left, 1'b0};
end else begin
acc <= acc_next;
quotient <= quotient_next;
end
end
endmodule
| 7.871496 |
module std_fp_gt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic out
);
assign out = left > right;
endmodule
| 8.426383 |
module std_fp_sadd #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left + right);
endmodule
| 8.768295 |
module std_fp_ssub #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left - right);
endmodule
| 8.839041 |
module std_fp_smult_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input [WIDTH-1:0] left,
input [WIDTH-1:0] right,
input logic reset,
input logic go,
input logic clk,
output logic [WIDTH-1:0] out,
output logic done
);
std_fp_mult_pipe #(
.WIDTH(WIDTH),
.INT_WIDTH(INT_WIDTH),
.FRAC_WIDTH(FRAC_WIDTH),
.SIGNED(1)
) comp (
.clk(clk),
.done(done),
.reset(reset),
.go(go),
.left(left),
.right(right),
.out(out)
);
endmodule
| 7.173413 |
module std_fp_sdiv_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input clk,
input go,
input reset,
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out_quotient,
output signed [WIDTH-1:0] out_remainder,
output logic done
);
logic signed [WIDTH-1:0]
left_abs, right_abs, comp_out_q, comp_out_r, right_save, out_rem_intermediate;
// Registers to figure out how to transform outputs.
logic different_signs, left_sign, right_sign;
// Latch the value of control registers so that their available after
// go signal becomes low.
always_ff @(posedge clk) begin
if (go) begin
right_save <= right_abs;
left_sign <= left[WIDTH-1];
right_sign <= right[WIDTH-1];
end else begin
left_sign <= left_sign;
right_save <= right_save;
right_sign <= right_sign;
end
end
assign right_abs = right[WIDTH-1] ? -right : right;
assign left_abs = left[WIDTH-1] ? -left : left;
assign different_signs = left_sign ^ right_sign;
assign out_quotient = different_signs ? -comp_out_q : comp_out_q;
// Remainder is computed as:
// t0 = |left| % |right|
// t1 = if left * right < 0 and t0 != 0 then |right| - t0 else t0
// rem = if right < 0 then -t1 else t1
assign out_rem_intermediate = different_signs & |comp_out_r ? $signed(
right_save - comp_out_r
) : comp_out_r;
assign out_remainder = right_sign ? -out_rem_intermediate : out_rem_intermediate;
std_fp_div_pipe #(
.WIDTH(WIDTH),
.INT_WIDTH(INT_WIDTH),
.FRAC_WIDTH(FRAC_WIDTH)
) comp (
.reset(reset),
.clk(clk),
.done(done),
.go(go),
.left(left_abs),
.right(right_abs),
.out_quotient(comp_out_q),
.out_remainder(comp_out_r)
);
endmodule
| 8.37227 |
module std_fp_sgt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed out
);
assign out = $signed(left > right);
endmodule
| 8.236193 |
module std_fp_slt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed out
);
assign out = $signed(left < right);
endmodule
| 8.595041 |
module std_mult_pipe #(
parameter WIDTH = 32
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
input logic reset,
input logic go,
input logic clk,
output logic [WIDTH-1:0] out,
output logic done
);
std_fp_mult_pipe #(
.WIDTH(WIDTH),
.INT_WIDTH(WIDTH),
.FRAC_WIDTH(0),
.SIGNED(0)
) comp (
.reset(reset),
.clk(clk),
.done(done),
.go(go),
.left(left),
.right(right),
.out(out)
);
endmodule
| 7.504255 |
module std_div_pipe #(
parameter WIDTH = 32
) (
input reset,
input clk,
input go,
input [WIDTH-1:0] left,
input [WIDTH-1:0] right,
output logic [WIDTH-1:0] out_remainder,
output logic [WIDTH-1:0] out_quotient,
output logic done
);
logic [WIDTH-1:0] dividend;
logic [(WIDTH-1)*2:0] divisor;
logic [WIDTH-1:0] quotient;
logic [WIDTH-1:0] quotient_msk;
logic start, running, finished, dividend_is_zero;
assign start = go && !running;
assign finished = quotient_msk == 0 && running;
assign dividend_is_zero = start && left == 0;
always_ff @(posedge clk) begin
// Early return if the divisor is zero.
if (finished || dividend_is_zero) done <= 1;
else done <= 0;
end
always_ff @(posedge clk) begin
if (reset || finished || dividend_is_zero) running <= 0;
else if (start) running <= 1;
else running <= running;
end
// Outputs
always_ff @(posedge clk) begin
if (dividend_is_zero || start) begin
out_quotient <= 0;
out_remainder <= 0;
end else if (finished) begin
out_quotient <= quotient;
out_remainder <= dividend;
end else begin
// Otherwise, explicitly latch the values.
out_quotient <= out_quotient;
out_remainder <= out_remainder;
end
end
// Calculate the quotient mask.
always_ff @(posedge clk) begin
if (start) quotient_msk <= 1 << WIDTH - 1;
else if (running) quotient_msk <= quotient_msk >> 1;
else quotient_msk <= quotient_msk;
end
// Calculate the quotient.
always_ff @(posedge clk) begin
if (start) quotient <= 0;
else if (divisor <= dividend) quotient <= quotient | quotient_msk;
else quotient <= quotient;
end
// Calculate the dividend.
always_ff @(posedge clk) begin
if (start) dividend <= left;
else if (divisor <= dividend) dividend <= dividend - divisor;
else dividend <= dividend;
end
always_ff @(posedge clk) begin
if (start) begin
divisor <= right << WIDTH - 1;
end else if (finished) begin
divisor <= 0;
end else begin
divisor <= divisor >> 1;
end
end
// Simulation self test against unsynthesizable implementation.
`ifdef VERILATOR
logic [WIDTH-1:0] l, r;
always_ff @(posedge clk) begin
if (go) begin
l <= left;
r <= right;
end else begin
l <= l;
r <= r;
end
end
always @(posedge clk) begin
if (done && $unsigned(out_remainder) != $unsigned(l % r))
$error(
"\nstd_div_pipe (Remainder): Computed and golden outputs do not match!\n",
"left: %0d",
$unsigned(
l
),
" right: %0d\n",
$unsigned(
r
),
"expected: %0d",
$unsigned(
l % r
),
" computed: %0d",
$unsigned(
out_remainder
)
);
if (done && $unsigned(out_quotient) != $unsigned(l / r))
$error(
"\nstd_div_pipe (Quotient): Computed and golden outputs do not match!\n",
"left: %0d",
$unsigned(
l
),
" right: %0d\n",
$unsigned(
r
),
"expected: %0d",
$unsigned(
l / r
),
" computed: %0d",
$unsigned(
out_quotient
)
);
end
`endif
endmodule
| 6.929139 |
module std_sadd #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left + right);
endmodule
| 8.670882 |
module std_ssub #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left - right);
endmodule
| 8.103836 |
module std_smult_pipe #(
parameter WIDTH = 32
) (
input logic reset,
input logic go,
input logic clk,
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output logic signed [WIDTH-1:0] out,
output logic done
);
std_fp_mult_pipe #(
.WIDTH(WIDTH),
.INT_WIDTH(WIDTH),
.FRAC_WIDTH(0),
.SIGNED(1)
) comp (
.reset(reset),
.clk(clk),
.done(done),
.go(go),
.left(left),
.right(right),
.out(out)
);
endmodule
| 6.968167 |
module std_sdiv_pipe #(
parameter WIDTH = 32
) (
input reset,
input clk,
input go,
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed [WIDTH-1:0] out_quotient,
output logic signed [WIDTH-1:0] out_remainder,
output logic done
);
logic signed [WIDTH-1:0]
left_abs, right_abs, comp_out_q, comp_out_r, right_save, out_rem_intermediate;
// Registers to figure out how to transform outputs.
logic different_signs, left_sign, right_sign;
// Latch the value of control registers so that their available after
// go signal becomes low.
always_ff @(posedge clk) begin
if (go) begin
right_save <= right_abs;
left_sign <= left[WIDTH-1];
right_sign <= right[WIDTH-1];
end else begin
left_sign <= left_sign;
right_save <= right_save;
right_sign <= right_sign;
end
end
assign right_abs = right[WIDTH-1] ? -right : right;
assign left_abs = left[WIDTH-1] ? -left : left;
assign different_signs = left_sign ^ right_sign;
assign out_quotient = different_signs ? -comp_out_q : comp_out_q;
// Remainder is computed as:
// t0 = |left| % |right|
// t1 = if left * right < 0 and t0 != 0 then |right| - t0 else t0
// rem = if right < 0 then -t1 else t1
assign out_rem_intermediate = different_signs & |comp_out_r ? $signed(
right_save - comp_out_r
) : comp_out_r;
assign out_remainder = right_sign ? -out_rem_intermediate : out_rem_intermediate;
std_div_pipe #(
.WIDTH(WIDTH)
) comp (
.reset(reset),
.clk(clk),
.done(done),
.go(go),
.left(left_abs),
.right(right_abs),
.out_quotient(comp_out_q),
.out_remainder(comp_out_r)
);
// Simulation self test against unsynthesizable implementation.
`ifdef VERILATOR
logic signed [WIDTH-1:0] l, r;
always_ff @(posedge clk) begin
if (go) begin
l <= left;
r <= right;
end else begin
l <= l;
r <= r;
end
end
always @(posedge clk) begin
if (done && out_quotient != $signed(l / r))
$error(
"\nstd_sdiv_pipe (Quotient): Computed and golden outputs do not match!\n",
"left: %0d",
l,
" right: %0d\n",
r,
"expected: %0d",
$signed(
l / r
),
" computed: %0d",
$signed(
out_quotient
),
);
if (done && out_remainder != $signed(((l % r) + r) % r))
$error(
"\nstd_sdiv_pipe (Remainder): Computed and golden outputs do not match!\n",
"left: %0d",
l,
" right: %0d\n",
r,
"expected: %0d",
$signed(
((l % r) + r) % r
),
" computed: %0d",
$signed(
out_remainder
),
);
end
`endif
endmodule
| 7.505299 |
module std_sgt #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left > right);
endmodule
| 7.663941 |
module std_slt #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left < right);
endmodule
| 8.095256 |
module std_seq #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left == right);
endmodule
| 8.302327 |
module std_sneq #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left != right);
endmodule
| 7.44378 |
module std_sge #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left >= right);
endmodule
| 7.297458 |
module std_sle #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left <= right);
endmodule
| 8.057164 |
module std_slsh #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = left <<< right;
endmodule
| 7.70425 |
module std_srsh #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = left >>> right;
endmodule
| 8.663189 |
module std_const #(
parameter WIDTH = 32,
parameter VALUE = 0
) (
output logic [WIDTH - 1:0] out
);
assign out = VALUE;
endmodule
| 8.794277 |
module std_wire #(
parameter WIDTH = 32
) (
input wire logic [WIDTH - 1:0] in,
output logic [WIDTH - 1:0] out
);
assign out = in;
endmodule
| 8.485736 |
module std_slice #(
parameter IN_WIDTH = 32,
parameter OUT_WIDTH = 32
) (
input wire logic [ IN_WIDTH-1:0] in,
output logic [OUT_WIDTH-1:0] out
);
assign out = in[OUT_WIDTH-1:0];
`ifdef VERILATOR
always_comb begin
if (IN_WIDTH < OUT_WIDTH)
$error(
"std_slice: Input width less than output width\n",
"IN_WIDTH: %0d",
IN_WIDTH,
"OUT_WIDTH: %0d",
OUT_WIDTH
);
end
`endif
endmodule
| 8.248138 |
module std_pad #(
parameter IN_WIDTH = 32,
parameter OUT_WIDTH = 32
) (
input wire logic [ IN_WIDTH-1:0] in,
output logic [OUT_WIDTH-1:0] out
);
localparam EXTEND = OUT_WIDTH - IN_WIDTH;
assign out = {{EXTEND{1'b0}}, in};
`ifdef VERILATOR
always_comb begin
if (IN_WIDTH > OUT_WIDTH)
$error(
"std_pad: Output width less than input width\n",
"IN_WIDTH: %0d",
IN_WIDTH,
"OUT_WIDTH: %0d",
OUT_WIDTH
);
end
`endif
endmodule
| 8.450332 |
module std_not #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] in,
output logic [WIDTH-1:0] out
);
if (WIDTH == 1) begin
lakeroad_xilinx_ultrascale_plus_not1_1 _impl (
in,
out
);
end else if (WIDTH == 8) begin
lakeroad_xilinx_ultrascale_plus_not8_1 _impl (
in,
out
);
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 8.707194 |
module std_and #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
if (WIDTH == 1) begin
lakeroad_xilinx_ultrascale_plus_and1_2 _impl (
left,
right,
out
);
end else if (WIDTH == 32) begin
lakeroad_xilinx_ultrascale_plus_and32_2 _impl (
left,
right,
out
);
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 8.159461 |
module std_or #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
if (WIDTH == 1) begin
lakeroad_xilinx_ultrascale_plus_or1_2 _impl (
left,
right,
out
);
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 8.160076 |
module std_xor #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
// if (WIDTH == x) begin
// lakeroad_xilinx_ultrascale_plus_op _impl(in, out);
// end
// //else begin
$error("Unsupported bitwidth %0d", WIDTH);
// end
endmodule
| 8.185133 |
module std_add #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
if (WIDTH == 2) begin
lakeroad_xilinx_ultrascale_plus_add2_2 _impl (
left,
right,
out
);
end else if (WIDTH == 3) begin
lakeroad_xilinx_ultrascale_plus_add3_2 _impl (
left,
right,
out
);
end else if (WIDTH == 4) begin
lakeroad_xilinx_ultrascale_plus_add4_2 _impl (
left,
right,
out
);
end else if (WIDTH == 8) begin
lakeroad_xilinx_ultrascale_plus_add8_2 _impl (
left,
right,
out
);
end else if (WIDTH == 32) begin
lakeroad_xilinx_ultrascale_plus_add32_2 _impl (
left,
right,
out
);
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 7.105468 |
module std_sub #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
if (WIDTH == 5) begin
lakeroad_xilinx_ultrascale_plus_sub5_2 _impl (
left,
right,
out
);
end else if (WIDTH == 6) begin
lakeroad_xilinx_ultrascale_plus_sub6_2 _impl (
left,
right,
out
);
end else if (WIDTH == 32) begin
lakeroad_xilinx_ultrascale_plus_sub32_2 _impl (
left,
right,
out
);
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 7.29825 |
module std_gt #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (WIDTH == 5) begin
lakeroad_xilinx_ultrascale_plus_ugt5_2 _impl (
left,
right,
out
);
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 7.445889 |
module std_lt #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (WIDTH == 3) begin
lakeroad_xilinx_ultrascale_plus_ult3_2 _impl (
left,
right,
out
);
end else if (WIDTH == 4) begin
lakeroad_xilinx_ultrascale_plus_ult4_2 _impl (
left,
right,
out
);
end else if (WIDTH == 32) begin
lakeroad_xilinx_ultrascale_plus_ult32_2 _impl (
left,
right,
out
);
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 7.925865 |
module std_eq #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (WIDTH == 1) begin
lakeroad_xilinx_ultrascale_plus_eq1_2 _impl (
left,
right,
out
);
end else if (WIDTH == 5) begin
lakeroad_xilinx_ultrascale_plus_eq5_2 _impl (
left,
right,
out
);
end else if (WIDTH == 6) begin
lakeroad_xilinx_ultrascale_plus_eq6_2 _impl (
left,
right,
out
);
end else if (WIDTH == 32) begin
lakeroad_xilinx_ultrascale_plus_eq32_2 _impl (
left,
right,
out
);
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 8.155468 |
module std_neq #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (0 == 1) begin
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 7.624981 |
module std_ge #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (0 == 1) begin
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 6.896227 |
module std_le #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (WIDTH == 4) begin
lakeroad_xilinx_ultrascale_plus_ule4_2 _impl (
left,
right,
out
);
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 8.161124 |
module std_lsh #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left << right;
endmodule
| 8.684363 |
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