code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module statemachine_tb ();
logic clk;
logic reset;
logic halt;
logic fetch;
logic exec1;
logic exec2;
statemachine sm (
.clk (clk),
.reset(reset),
.halt (halt),
.fetch(fetch)
);
endmodule
| 6.801401 |
module sequenceDetector (
clk,
reset,
x,
y,
button,
out,
state
);
input clk;
input reset;
input x, y;
input button;
output out;
output state;
reg [3:0] state;
wire out = ((state == 3) || (state == 6));
reg button_reg;
reg button_sync;
wire button_done;
reg [31:0] b... | 7.152895 |
module states1 (
input clk,
input st1Begin, //state 1 will be running
input async_rs, //asynchronous reset
input enabler, //if it's on to be running
output [17:0] out,
output st1Over
); //state 1 has done
reg [17:0] r_out;
reg r_st1Over;
reg localReset;
reg rs;
initial begin
... | 6.734189 |
module states2 (
input clk,
input st2Begin, //state 2 will be running
input async_rs, //asynchronous reset
input enabler, //if it's on to be running
output [17:0] out,
output st2Over
); //state 2 has done
reg [17:0] r_out;
reg r_st2Over;
reg localReset;
initial begin
r_out <= 1... | 7.368798 |
module states3 (
input clk,
input st3Begin, //states 3 will be running
input async_rs, //asynchronous reset
input enabler, //if it's on to be running
output [17:0] out,
output st3Over
); //states 3 has done
reg [17:0] r_out;
reg signed [8:0] r_right;
reg [8:0] r_left;
reg [5:0] cou... | 7.522493 |
module states4 (
input clk,
input st4Begin, //states 4 will be running
input async_rs, //asynchronous reset
input enabler, //if it's on to be running
output [17:0] out,
output st4Over
); //states 4 has done
reg [17:0] r_out;
reg signed [8:0] r_left;
reg [8:0] r_right;
reg r_st4Over;... | 7.198969 |
module states5 (
input clk,
input st5Begin, //states 5 will be running
input async_rs, //asynchronous reset
input enabler, //if it's on to be running
output [17:0] out,
output st5Over
); //states 5 has done
reg signed [17:0] r_out;
reg r_st5Over;
reg finishloading;
reg localReset;
... | 6.644644 |
module states6 (
input clk,
input st6Begin, //states 6 will be running
input async_rs, //asynchronous reset
input enabler,
output [17:0] out,
output st6Over
); //states 6 has done
reg [17:0] r_out;
reg r_st6Over;
reg finishloading;
reg localReset;
initial begin
r_out = 18'b000... | 6.89263 |
module StateSwitch (
output reg [1:0] state,
input [5:0] enb,
input [1:0] state1,
input [1:0] state2,
input [1:0] state3,
input [1:0] state4,
input [1:0] stateRst,
input [1:0] stateOnline,
input clk
);
parameter RED = 2'b00;
parameter YELLOW = 2'b01;
parameter GREEN = 2'b10;
... | 7.045739 |
module STATE_1MS_TOP (
state_1ms_rst_n,
clk_sys,
state_1ms_start,
reset_out,
dump_start,
pluse_start,
bri_cycle,
rt_sw,
soft_dump,
load,
loadchoice,
datain
);
input state_1ms_rst_n;
input clk_sys;
input state_1ms_start;
output reset_out;
output dump_start;
out... | 6.93894 |
module state_cola_1 (
input wire sys_clk,
input wire sys_rst_n,
input wire pi_money,
output reg po_cola
);
reg [2:0] state;
parameter ZERO = 3'b001, ONE = 3'b010, TWO = 3'b100;
//状态机的赋值
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) state <= ZERO;
else
cas... | 7.271812 |
module state_cola_2 (
input wire sys_clk,
input wire sys_rst_n,
input wire pi_money_one,
input wire pi_money_half,
output reg po_cola,
output reg po_money
);
reg [4:0] state;
wire [1:0] pi_money;
//独热码
parameter ZERO = 5'b00001, HALF = 5'b00010, ONE = 5'b00100, ONE_HALF = 5'b01000, TW... | 8.719373 |
module state_controller (
input clk,
input reset,
input start,
input [9:0] enemy_laser_h,
input [9:0] plane_h,
input [9:0] enemy_0_v,
input [9:0] enemy_1_v,
input [9:0] enemy_2_v,
input [9:0] enemy_3_v,
input [9:0] enemy_4_v,
input [9:0] enemy_5_v,
input [9:0] enemy_6_v,
... | 6.516943 |
module state_converter (
input clk,
input rst,
input wire [7:0] ms,
input wire [7:0] sec,
input wire [7:0] min,
input start,
input pause,
input reset,
output reg clr_signal,
output reg add_signal,
reg [1:0] State
);
parameter ACTIVE = 2'b00;
parameter PAUSE = 2'b01;
... | 8.074048 |
module state_data_ctrl (
input clk,
input rst,
input power,
input [1:0] mode,
input [3:0] state,
output reg [35:0] data
);
parameter non_act = 4'b0000;
parameter none_s = 4'b0001;
parameter none_s_2 = 4'b0110;
parameter start = 4'b0010;
parameter move = 4'b0011;
parameter switch = 4'... | 8.168938 |
module state_decoder (
i_state,
o_7seg
);
input [2:0] i_state;
output reg [6:0] o_7seg;
always @(i_state) begin
case (i_state)
3'b000: o_7seg = 7'b0010010;
3'b001: o_7seg = 7'b1000001;
3'b010: o_7seg = 7'b1000001;
3'b011: o_7seg = 7'b1000001;
3'b100: o_7seg = 7'b0... | 6.507637 |
module STATE_GRAPHIC(CLK, RESET, W_IN, Z_OUT)
input clk;
input rst_n;
input w_i;
output z_o;
parameter IDLE = 2'b00;
parameter S0 = 2'b01;
reg [1:0] curr_state;
reg [1:0] next_state;
reg z;
reg z_o;
// state reg
always@(posedge clk or negedge rst_n)
if (~rst_n) curr_state <= IDLE;
else curr_state <= n... | 7.222595 |
module state_m (
// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
clk,
reset,
newt,
sel,
follow,
first
// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration
// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
input clk, reset, newt;
output follow, first;
output [1... | 6.610127 |
module STATE_MEMORY #(
parameter depth = 512,
parameter address_width = $clog2(depth)
) (
input CLK,
input RST,
input FLUSH,
input WREN,
input [address_width-1:0] WADDR,
input [address_width-1:... | 8.073548 |
module's output value
state - used for switching between bios output and instruction memory output
*/
module State_Mux_32
#(parameter DATA_WIDTH = 32)
(
input mux_select, clk, rst, hlt,
input [(DATA_WIDTH -1):0] input_data_1, input_data_2,
output [(DATA_WIDTH -1):0] mux_output
);
reg state;
always @ ( posedge c... | 9.302274 |
module state_register (
ALE,
CLE,
CE,
command,
state
);
input ALE, CLE, CE;
input command;
reg [3:0] command;
output [7:0] state;
reg [7:0] state;
//reg [3:0]mid;
always @(command or CE) begin
if (CE) state = 0;
else if (state[7]) //state][7]=1 意味着是两单位命令
case (command)
... | 6.849679 |
module state_switch (
clk_sys,
rst_n,
time_up_in,
start,
state_over_in,
datain_scale,
datain_scan,
datain_noise,
datain_pluse,
datain_state_1ms,
dataout,
state_start,
state_over_n,
clk_en_scale,
clk_en_scan,
clk_en_noise,
clk_en_pluse,
clk_en_st1ms... | 7.867447 |
module state_transition (
input clk,
rst_n,
input en_in,
input en1,
input en2,
input [1 : 0] rd,
input [3 : 0] opcode,
output reg en_fetch_pulse,
output reg en_group_pulse,
output reg en_pc_pulse,
output reg [1 : 0] pc_ctrl,
output reg [3 : 0] reg_en,
output reg alu_i... | 7.027363 |
module state_unit (
input clk,
input rst_n,
input [`INST_BUS] inst,
input mem_enable,
output reg [`STATE_BUS] state,
output reg [`STATE_BUS] next_state
);
wire arithmetic = inst == `INST_ADD || inst == `INST_SUB ||
inst == `INST_ADDU || inst == `INST_AND || inst == `INST_OR ||
... | 7.092008 |
module state_update #(
parameter N = 32,
parameter Q = 18,
parameter Ts = 0.00001
) (
input signed [N-1:0] ialpha,
ibeta,
valpha,
vbeta,
omega,
theta,
stheta,
ctheta,
input clk,
reset,
output signed [N-1:0] ialphae,
ibetae,
omegae,
thetae,
output... | 6.58873 |
module StaticImage #(
parameter IMG_WIDTH = 200,
parameter IMG_HEIGHT = 150
) (
input clock,
input reset,
input start,
output reg start_ack,
input ready,
output valid,
output [7:0] pixel
);
localparam OUT_WIDTH = 800, OUT_HEIGHT = 600;
localparam IMG_N_PIXEL = IMG_WIDTH * I... | 7.965751 |
module StaticImageBlank (
input clock,
input reset,
input [7:0] pixel,
input valid,
output readyStatic,
output readyDown,
output [7:0] pixelout
);
localparam ROW_COMPARE = 1200;
localparam COL_COMPARE = 1200;
reg [12:0] rowcount;
reg [12:0] colcount;
wire [12:0] nextcolcount... | 7.497743 |
module staticRamDiscretePorts (
address, // Address Input
data, // Data input
we_,
clock,
Q //output
);
parameter ROMFILE = "noFile";
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 8;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
//--------------Input Ports-----------------------
input ... | 7.6946 |
module W0RM_Static_Timer #(
parameter LOAD = 0,
parameter LIMIT = 2
) (
input wire clk,
input wire start,
output wire stop
);
// log base 2 function
function integer log2(input integer n);
integer i, j;
begin
i = 1;
j = 0;
//integer i = 1, j = 0;
while (i < n) ... | 6.769402 |
module static_background (
input blank,
input [10:0] hcount, // Screen placement horizontal
input [10:0] vcount, // Screen placement vertical
output r,
output g, // Color Output
output b
);
assign r = (((hcount < 640) && (hcount >= 0) && (((vcount < 40) ... | 7.160647 |
module static_phy_read #(
parameter integer DQS_WIDTH = 4
) (
input wire clk0,
input wire ctrl_rden,
input wire [ 3:0] phy_calib_rden_delay,
output wire [DQS_WIDTH-1:0] phy_calib_rden
);
genvar i;
generate
for (i = 0; i < DQS_WIDTH; i = i + 1) beg... | 6.669854 |
module static_reg #(
parameter WIDTH = 1
) (
input wire clk,
input wire reset_n,
input wire [WIDTH-1:0] static_i,
output wire [WIDTH-1:0] static_o
);
//internal signals
reg [WIDTH-1:0] static_r;
reg static_up;
wire static_en;
//---------... | 9.735885 |
module of the design
`timescale 1 ns/100 ps
module status_signal(fifo_full, fifo_empty, fifo_threshold, fifo_overflow, fifo_underflow, wr, rd, fifo_we, fifo_rd, wptr,rptr,clk,rst_n);
input wr, rd, fifo_we, fifo_rd,clk,rst_n;
input[4:0] wptr, rptr;
output fifo_full, fifo_empty, fifo_threshold, fifo_overflow,... | 8.52834 |
module W0RM_Static_Timer_tb;
reg clk = 0;
reg start = 0;
always #2.5 clk <= ~clk;
initial begin
#11 start = 1;
#5 start = 0;
end
W0RM_Static_Timer #(
.LOAD (0),
.LIMIT(7)
) timer_0_7 (
.clk (clk),
.start(start),
.stop (stop_timer_0_7)
);
W0RM_Static_Timer #(
... | 6.769402 |
module station(
input clk,
input iq,
input signed [17:0] drive, // not counting beam
input start,
input signed [17:0] mech_x,
input signed [17:0] piezo,
input start_outer,
// Output ADCs at 20 MHz IF
output signed [15:0] a_field,
output signed [15:0] a_forward,
output signed [15:0] a_reflect,
... | 6.930712 |
module station_management_tb ();
reg reset;
reg clock;
wire mdc;
reg mdi;
wire mdo;
reg mode;
reg begin_transaction;
reg [4:0] phy_address;
reg [4:0] reg_address;
reg [15:0] data_in;
wire [15:0] data_out;
station_management U_station_management
(
.reset(reset),
.clock(clock),
.mdc(mdc),
.mdi(... | 6.70789 |
module station_management_tb ();
reg reset;
reg clock;
wire mdc;
reg mdi;
wire mdo;
reg mode;
reg begin_transaction;
reg [4:0] phy_address;
reg [4:0] reg_address;
reg [15:0] data_in;
wire [15:0] data_out;
station_management U_station_management
(
.reset(reset),
.clock(clock),
.mdc(mdc),
.mdi(... | 6.70789 |
module statistic (
input [31:0] A,
input [31:0] B,
input clk,
input rst,
input syscall_t,
input condi_suc,
input un_branch_t,
input branch_t,
input strong_halt,
// output for convenience, bit width set as 32
output reg [31:0] total_cycles,
output reg [31:0] uncondi_num,... | 7.65806 |
module statistic_accum #(
parameter DATA_WIDTH = 16,
parameter BOUND_WIDTH = 10, // ширина границам
parameter BOUND_NUM = 32, // количесвто границ
parameter BOUND_NUM_WIDTH = 5 // количество бит в которые можно записать число BOUND_NUM
) (
input clk,
input reset_n,
input data_val_i, ... | 6.967717 |
module statreg (
in,
enable,
out
);
/*
* STATUS REGISTER - statreg.v
*
* Inputs:
* - in (4 bits): The status bits generated by the ALU. The status register
* saves these bits so that the control unit can use them in branches.
* For a description of the status bits, see... | 7.660307 |
module stats16 #(
parameter BASE = 0
) (
input wire clk,
input wire pps,
input wire [15:0] data,
// IO
input [7:0] port_id,
output [7:0] in_port,
input read_strobe
);
// data
reg [15:0] min;
reg [15:0] max;
reg [15:0] chg0;
reg [15:0] chg1;
// stats
reg [15:0] smin;
re... | 7.801978 |
module stats_dma_latency #(
// Counter width (bits)
parameter COUNT_WIDTH = 16,
// Tag width (bits)
parameter TAG_WIDTH = 8,
// Length field width (bits)
parameter LEN_WIDTH = 16,
// Status field width (bits)
parameter STATUS_WIDTH = 4
) (
input wire clk,
input wire rst,
/*
... | 6.574299 |
module status (
data,
Z,
N
);
input [15:0] data;
output reg N, Z;
always @* begin
if (data == 0) begin
Z <= 1;
N <= 0;
end else if (data[15] == 1'b1) begin
Z <= 0;
N <= 1;
end else begin
Z <= 0;
N <= 0;
end
end
endmodule
| 6.54827 |
module. It is responsible for
// displaying Mouse Status on the on-board LEDs.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module StatusLED(
input RESET,
input CLK,
inout ... | 7.574457 |
module Status_Engine (
clk,
rst,
// input(s)
i_SET_ID,
i_Status_En,
i_RAM_Data,
i_Mask_Data,
// output(s)
o_SETID_MOD,
o_Done
);
// ==========================================================================
// == Parameters
// ============================================... | 7.116012 |
module Status_Register (
input [3:0] Status_in,
input clk,
S,
output reg [3:0] Status
);
initial Status = 4'b0000;
always @(negedge clk) begin
if (S) Status <= Status_in;
end
endmodule
| 7.180259 |
module status_register_32_bits (
output reg [31:0] Q,
input [31:0] D,
input LE,
CLR,
CLK
);
initial Q = 32'b0000000000000000000000000000000; // Start registers with 0
always @(negedge CLK, negedge CLR)
if (!LE) Q <= D; // Enable Sync. Only occurs when Clk is high
else if (!CLR) // cl... | 8.068783 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
module stat_counter (
// Clock and Reset Signals
sys_clk,
s_reset_n,
count_inc,
count_dec,
reg_sel,
reg_wr_data,
reg_wr,
cntr_intr,
cntrout
);
parameter CWD = 1; // Counter Width
//-------------------- Parameters -------------------------------------
// ------------... | 6.702345 |
module stat_sprite_mem (
clock,
select,
x,
y,
out
);
//select -> number of the sprite -> 64 posibilities
//x -> w position of the pixel in the 16x16 array
input clock;
input [3:0] x, y;
input [5:0] select;
output reg [1:0] out;
wire [1:0] sprite1;
wire [1:0] sprite2;
//....conti... | 6.960753 |
module stat_top #(
parameter integer bit_width = 64,
parameter integer vec_width_index = 4,
parameter integer vec_width_value = 32,
parameter integer vec_num = 16,
parameter integer vec_width_total = (vec_width_index + vec_width_value) * vec_num
) (
input wire rst,
stat_clk,
da... | 7.26932 |
module sta_rom (
input [4:0] addr,
input [3:0] imm4,
output reg [7:0] label
);
always @(*)
case (addr)
0: label = "S";
1: label = "T";
2: label = "A";
4: label = imm4[3];
5: label = imm4[2];
6: label = imm4[1];
7: label = imm4[0];
default: label = " ";
... | 7.020067 |
module stb_extender (
input reset,
// fast clock domain
input clk_in,
input stb_in,
// slow clock domain
input clk_out,
output stb_out
);
reg reg_stb_in, reg_stb_out;
assign stb_out = reg_stb_out;
always @(posedge clk_in or posedge reset)
if (reset) reg_stb_in <= 0;
else... | 6.772603 |
module STController (
cp,
resetBtn,
runBtn,
openBtn,
click,
hadFinish,
initTime,
finishTime,
sleepTime,
shinning,
state
);
input cp;
input resetBtn, runBtn, openBtn;
input click;
input hadFinish;
input [2:0] initTime;
input [2:0] finishTime;
input [1:0] sleepTim... | 7.490764 |
module stconv (
input [31:0] in,
input [31:0] ir,
output [31:0] out
);
function [31:0] converter;
input [31:0] in;
input [31:0] ir;
case (ir[14:12])
3'b000: converter = {4{in[7:0]}}; // SB
3'b001: converter = {2{in[15:0]}}; // SH
3'b010: converter = in[31:0]; // SW... | 7.278194 |
module stCU (
input nRST,
//发射控制
input [2:0] Add_Busy, //加减保留站
input [2:0] Mul_Busy, //乘法保留站
input [1:0] Mem_Busy, //访存保留站
input WAW,
input [2:0] stType,
output wire issuable, //cu可发射
output [4:0] stnum,
output insStall //pc暂停取指
);
/* reg [2:0]stType; //指令对应保留站类型 */
... | 6.951967 |
module adder (
sum_out,
carry_out,
carry_in,
ina,
inb
);
output carry_out;
output [3:0] sum_out;
input [3:0] ina, inb;
input carry_in;
wire carry_out, carry_in;
wire [3:0] sum_out, ina, inb;
assign {carry_out, sum_out} = ina + inb + carry_in;
endmodule
| 7.276647 |
module select_bus (
busout,
bus0,
bus1,
bus2,
bus3,
enable,
s
);
parameter n = 16;
parameter Zee = 16'bz;
output [1:n] busout;
input [1:n] bus0, bus1, bus2, bus3;
input enable;
input [1:2] s;
tri [1:n] data;
// net declaration
// net declaration with continuous assignment
... | 7.501903 |
module std_fp_add #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left + right;
endmodule
| 9.124708 |
module std_fp_sub #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left - right;
endmodule
| 8.85803 |
module std_fp_mult_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16,
parameter SIGNED = 0
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
input logic go,
input logic clk,
input logic reset,
... | 6.609331 |
module std_fp_div_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic go,
input logic clk,
input logic reset,
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] o... | 7.871496 |
module std_fp_gt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic out
);
assign out = left > right;
endmodule
| 8.426383 |
module std_fp_sadd #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left + right);
endmodule
| 8.768295 |
module std_fp_ssub #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left - right);
endmodule
| 8.839041 |
module std_fp_smult_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input [WIDTH-1:0] left,
input [WIDTH-1:0] right,
input logic reset,
input logic go,
input logic clk,
output logic [WIDTH-1:0]... | 7.173413 |
module std_fp_sdiv_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input clk,
input go,
input reset,
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH... | 8.37227 |
module std_fp_sgt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed out
);
assign out = $signed(left > right);
endmodule
| 8.236193 |
module std_fp_slt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed out
);
assign out = $signed(left < right);
endmodule
| 8.595041 |
module std_mult_pipe #(
parameter WIDTH = 32
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
input logic reset,
input logic go,
input logic clk,
output logic [WIDTH-1:0] out,
output logic done
);
std_fp_mult_pipe #(
... | 7.504255 |
module std_div_pipe #(
parameter WIDTH = 32
) (
input reset,
input clk,
input go,
input [WIDTH-1:0] left,
input [WIDTH-1:0] right,
output logic [WIDTH-1:0] out_remainder,
output logic [WIDTH-1:0] out_quotient,
out... | 6.929139 |
module std_sadd #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left + right);
endmodule
| 8.670882 |
module std_ssub #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left - right);
endmodule
| 8.103836 |
module std_smult_pipe #(
parameter WIDTH = 32
) (
input logic reset,
input logic go,
input logic clk,
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output logic signed [WIDTH-1:0] out,
output logic... | 6.968167 |
module std_sdiv_pipe #(
parameter WIDTH = 32
) (
input reset,
input clk,
input go,
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed [WIDTH-1:0] out_quotient,
outp... | 7.505299 |
module std_sgt #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left > right);
endmodule
| 7.663941 |
module std_slt #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left < right);
endmodule
| 8.095256 |
module std_seq #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left == right);
endmodule
| 8.302327 |
module std_sneq #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left != right);
endmodule
| 7.44378 |
module std_sge #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left >= right);
endmodule
| 7.297458 |
module std_sle #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left <= right);
endmodule
| 8.057164 |
module std_slsh #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = left <<< right;
endmodule
| 7.70425 |
module std_srsh #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = left >>> right;
endmodule
| 8.663189 |
module std_const #(
parameter WIDTH = 32,
parameter VALUE = 0
) (
output logic [WIDTH - 1:0] out
);
assign out = VALUE;
endmodule
| 8.794277 |
module std_wire #(
parameter WIDTH = 32
) (
input wire logic [WIDTH - 1:0] in,
output logic [WIDTH - 1:0] out
);
assign out = in;
endmodule
| 8.485736 |
module std_slice #(
parameter IN_WIDTH = 32,
parameter OUT_WIDTH = 32
) (
input wire logic [ IN_WIDTH-1:0] in,
output logic [OUT_WIDTH-1:0] out
);
assign out = in[OUT_WIDTH-1:0];
`ifdef VERILATOR
always_comb begin
if (IN_WIDTH < OUT_WIDTH)
$error(
"std_slice: Input width ... | 8.248138 |
module std_pad #(
parameter IN_WIDTH = 32,
parameter OUT_WIDTH = 32
) (
input wire logic [ IN_WIDTH-1:0] in,
output logic [OUT_WIDTH-1:0] out
);
localparam EXTEND = OUT_WIDTH - IN_WIDTH;
assign out = {{EXTEND{1'b0}}, in};
`ifdef VERILATOR
always_comb begin
if (IN_WIDTH > OUT_WIDTH)
... | 8.450332 |
module std_not #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] in,
output logic [WIDTH-1:0] out
);
if (WIDTH == 1) begin
lakeroad_xilinx_ultrascale_plus_not1_1 _impl (
in,
out
);
end else if (WIDTH == 8) begin
lakeroad_xilinx_ultrascale_plus_not8_1 _impl (
... | 8.707194 |
module std_and #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
if (WIDTH == 1) begin
lakeroad_xilinx_ultrascale_plus_and1_2 _impl (
left,
right,
out
);
end else if (WIDTH == 32) ... | 8.159461 |
module std_or #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
if (WIDTH == 1) begin
lakeroad_xilinx_ultrascale_plus_or1_2 _impl (
left,
right,
out
);
end else begin
$error("U... | 8.160076 |
module std_xor #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
// if (WIDTH == x) begin
// lakeroad_xilinx_ultrascale_plus_op _impl(in, out);
// end
// //else begin
$error("Unsupported bitwidth %0d", WI... | 8.185133 |
module std_add #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
if (WIDTH == 2) begin
lakeroad_xilinx_ultrascale_plus_add2_2 _impl (
left,
right,
out
);
end else if (WIDTH == 3) ... | 7.105468 |
module std_sub #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
if (WIDTH == 5) begin
lakeroad_xilinx_ultrascale_plus_sub5_2 _impl (
left,
right,
out
);
end else if (WIDTH == 6) b... | 7.29825 |
module std_gt #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (WIDTH == 5) begin
lakeroad_xilinx_ultrascale_plus_ugt5_2 _impl (
left,
right,
out
);
end else begin
$error("Unsupported bitwidt... | 7.445889 |
module std_lt #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (WIDTH == 3) begin
lakeroad_xilinx_ultrascale_plus_ult3_2 _impl (
left,
right,
out
);
end else if (WIDTH == 4) begin
lakeroad_xi... | 7.925865 |
module std_eq #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (WIDTH == 1) begin
lakeroad_xilinx_ultrascale_plus_eq1_2 _impl (
left,
right,
out
);
end else if (WIDTH == 5) begin
lakeroad_xil... | 8.155468 |
module std_neq #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (0 == 1) begin
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 7.624981 |
module std_ge #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (0 == 1) begin
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 6.896227 |
module std_le #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (WIDTH == 4) begin
lakeroad_xilinx_ultrascale_plus_ule4_2 _impl (
left,
right,
out
);
end else begin
$error("Unsupported bitwidt... | 8.161124 |
module std_lsh #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left << right;
endmodule
| 8.684363 |
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