code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module_ref:ALU:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module contructure_ALU_0_0 (
ALUB,
ALUA,
fun,
valE,
cc
);
input wire [63 : 0] ALUB;
input wire [63 : 0] ALUA;
input wire [2 : 0] fun;
output wire [63 : 0] valE;
output wire [2 : 0] cc;
ALU inst (
.ALU... | 8.503178 |
module_ref:ALU_A:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module contructure_ALU_A_0_0 (
icode,
valC,
valA,
ALUA
);
input wire [3 : 0] icode;
input wire [63 : 0] valC;
input wire [63 : 0] valA;
output wire [63 : 0] ALUA;
ALU_A inst (
.icode(icode),
.valC... | 6.95175 |
module_ref:ALU_B:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module contructure_ALU_B_0_0 (
icode,
ifun,
valB,
ALUB
);
input wire [3 : 0] icode;
input wire [3 : 0] ifun;
input wire [63 : 0] valB;
output wire [63 : 0] ALUB;
ALU_B inst (
.icode(icode),
.ifun(... | 7.054509 |
module_ref:CCreg:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module contructure_CCreg_0_1 (
clk,
cc,
W_stat,
m_stat,
zf,
of,
sf
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
input wire clk;
input wire [2 : 0] cc;
input wire [2 : 0] W_stat;
in... | 8.318049 |
module_ref:cond:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module contructure_cond_0_0 (
icode,
ifun,
dstE,
sf,
of,
zf,
e_dstE,
e_cnd
);
input wire [3 : 0] icode;
input wire [3 : 0] ifun;
input wire [3 : 0] dstE;
input wire sf;
input wire of;
input wire zf;
o... | 6.97121 |
module_ref:data_memory:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module contructure_data_memory_0_1 (
clk,
enabler,
enablew,
dstM,
data,
dmem_error,
valM
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
input wire clk;
input wire enabler;
inpu... | 6.624664 |
module_ref:decodeReg:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module contructure_decodeReg_0_1 (
clk,
icode,
ifun,
reg1_read_src,
reg2_read_src,
valC,
valP,
stat,
bubble,
stall,
D_icode,
D_ifun,
D_reg1_read_src,
D_reg2_read_src,
D_valC,
D_val... | 6.591553 |
module_ref:d_stat:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module contructure_d_stat_0_0 (
icode,
cnd,
imem_error,
d_stat
);
input wire [3 : 0] icode;
input wire cnd;
input wire imem_error;
output wire [2 : 0] d_stat;
d_stat inst (
.icode(icode),
.cnd(cn... | 6.592894 |
module_ref:EReg:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module contructure_EReg_0_0 (
cnd,
clk,
icode,
ifun,
valC,
valA,
valB,
dstE,
dstM,
stat,
bubble,
E_icode,
E_ifun,
E_valC,
E_valA,
E_valB,
E_stat,
E_dstE,
E_dstM
);
input wire cnd... | 7.203466 |
module_ref:MREG:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module contructure_MREG_0_0 (
clk,
stat,
icode,
cnd,
valE,
valA,
dstE,
dstM,
bubble,
M_stat,
M_icode,
M_cnd,
M_valE,
M_valA,
M_dstE,
M_dstM
);
(* X_INTERFACE_INFO = "xilinx.com:signal:... | 7.796524 |
module_ref:m_stat:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module contructure_m_stat_0_0 (
dmem_error,
stat,
m_stat
);
input wire dmem_error;
input wire [2 : 0] stat;
output wire [2 : 0] m_stat;
m_stat inst (
.dmem_error(dmem_error),
.stat(stat),
.m_st... | 6.875876 |
module_ref:predPC:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module contructure_predPC_0_0 (
clk,
F_stall,
predPC,
pc
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
input wire clk;
input wire F_stall;
input wire [63 : 0] predPC;
output wire [63 : 0... | 7.261877 |
module_ref:regFile:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module contructure_regFile_0_1 (
clk,
dstE,
dstM,
M,
E,
srcA,
srcB,
d_rvalA,
d_rvalB
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
input wire clk;
input wire [3 : 0] dstE;
inp... | 7.561119 |
module_ref:selectPC:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module contructure_selectPC_0_0 (
predPC,
M_icode,
M_Cnd,
M_valA,
W_icode,
W_valM,
pc
);
input wire [63 : 0] predPC;
input wire [3 : 0] M_icode;
input wire M_Cnd;
input wire [63 : 0] M_valA;
input w... | 6.981835 |
module_ref:setRegIO:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module contructure_setRegIO_0_0 (
icode,
srcA,
srcB,
d_srcA,
d_srcB,
d_dstE,
d_dstM
);
input wire [3 : 0] icode;
input wire [3 : 0] srcA;
input wire [3 : 0] srcB;
output wire [3 : 0] d_srcA;
output ... | 7.060395 |
module contructure_wrapper (
W_stat,
W_stat_1,
clk,
m_stat,
rst,
stat
);
input [2:0] W_stat;
output [2:0] W_stat_1;
input clk;
input [2:0] m_stat;
input rst;
input [2:0] stat;
wire [2:0] W_stat;
wire [2:0] W_stat_1;
wire clk;
wire [2:0] m_stat;
wire rst;
wire [2:0] stat;... | 6.80425 |
module_ref:WREG:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module contructure_WREG_0_0 (
clk,
stat,
icode,
valE,
valM,
dstE,
dstM,
W_stat,
W_icode,
W_valE,
W_valM,
W_dstE,
W_dstM
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
inpu... | 8.032614 |
module名稱,輸出入名稱*/
module cont_8bit_adder(sum, cout, a, b, cin);
/*定義port,包含input, output*/
input [7:0] a, b;
input cin;
output [7:0] sum;
output cout;
/*將a、b、cin相加,而cout為第8bit值,sum則為0~7bit值*/
assign {cout,sum} = a+b+cin;
endmodule
| 6.820984 |
module CONT_STATE_DEBUG (
input [5:0] state,
output [5:0] state_debug
);
assign state_debug = state;
endmodule
| 7.280768 |
module Contador_Disp (
input Reset,
input CLK,
output reg [1:0] Out_Sel,
output reg [3:0] Out_An
);
reg [1:0] Cont;
always @(posedge CLK or posedge Reset) begin
if (Reset) begin
Out_Sel <= 2'b00;
Out_An <= 4'b1111;
end else begin
case (Cont)
2'b00: begin
... | 6.740581 |
module cont_test #(
parameter W = 4
) (
input wire clk,
input wire rst,
input wire load,
input wire enable,
input wire [W-1:0] d,
output wire max_tick,
output wire min_tick,
output wire [W-1:0] q
);
reg [W-1:0] count;
always @(posedge clk, posedge rst) begin
if (rst) c... | 7.208073 |
module Counter8_tb ();
reg CLK;
reg rst_n;
wire [2:0] oQ;
wire [6:0] oDisplay;
Counter8 uut (
.CLK(CLK),
.rst_n(rst_n),
.oQ(oQ),
.oDisplay(oDisplay)
);
initial begin
rst_n = 0;
#10 rst_n = 1;
CLK = 0;
#1000 $finish;
end
always #10 CLK = ~CLK;
endmodule
| 7.057075 |
module top_conv12 (
clk,
in,
filter,
out
);
input clk;
input [287:0] in;
input [17:0] filter;
output [199:0] out;
/*
mac_new mac1(clk,{in[25:20],in[15:10],in[5:0]},filter,out[1:0]);
mac_new mac2(clk,{in[27:22],in[17:12],in[7:2]},filter,out[3:2]);
mac_new mac3(clk,{in[29:24],in[19:14],in[9:4]}... | 6.56674 |
module conv1x1_16to4ch #(
parameter GROUP_CHANNEL = 16,
parameter BW_MATMUL = 2 * `BITWIDTH + $clog2(4 / `N),
parameter BW_CONV1x1 = BW_MATMUL + 2
) (
input [16*`BITWIDTH-1:0] feature,
input [4*16/`N*`BITWIDTH-1:0] weight,
output signed [4*BW_CONV1x1-1:0] conv1x1_4chout
);
// input reorder
... | 7.000349 |
module conv1 (
input clk,
input ena,
input iRst_n,
input [32 * 32 * 8 - 1:0] tensor_in,
input [25 * 8 - 1:0] filter_in,
input [7:0] bias_in,
output reg [28 * 28 * 8 - 1:0] tensor_out,
output reg overflow,
output reg done
);
reg [4:0] rowCnt;
reg [4:0] colCnt;
reg [5 * 5 * 8 ... | 6.506767 |
module ram_dual_port
(
clk,
clken,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
byteena_a,
byteena_b,
q_a,
q_b
);
parameter width_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_a = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_a = 1'd0;
parameter numwords_b = 1'd0;
parameter l... | 8.296277 |
module round_robin_arbiter (
rst_an,
clk,
req_in,
grant_final,
memory_controller_waitrequest
);
parameter N = 4;
input rst_an;
input clk;
input [N-1:0] req_in;
input memory_controller_waitrequest;
output [N-1:0] grant_final;
wire [N-1:0] req_final;
wire [N-1:0] req;
reg [N-1:0] r... | 6.544797 |
module stupleToSSeq_tSSeq_3_Int__n3 (
input [7:0] I_0_0,
input [7:0] I_0_1,
input [7:0] I_0_2,
input [7:0] I_1_0,
input [7:0] I_1_1,
input [7:0] I_1_2,
input [7:0] I_2_0,
input [7:0] I_2_1,
input [7:0] I_2_2,
output [7:0] O_0_0,
output [7:0] O_0_1,
output [7:0] O_0_2,
... | 6.674959 |
module stupleToSSeq_tInt_n3 (
input [7:0] I_0,
input [7:0] I_1,
input [7:0] I_2,
output [7:0] O_0,
output [7:0] O_1,
output [7:0] O_2,
output valid_down,
input valid_up
);
assign O_0 = I_0;
assign O_1 = I_1;
assign O_2 = I_2;
assign valid_down = valid_up;
endmodule
| 6.674959 |
module sseqTupleAppender_tSSeq_3_Int__n2 (
input [7:0] I0_0_0,
input [7:0] I0_0_1,
input [7:0] I0_0_2,
input [7:0] I0_1_0,
input [7:0] I0_1_1,
input [7:0] I0_1_2,
input [7:0] I1_0,
input [7:0] I1_1,
input [7:0] I1_2,
output [7:0] O_0_0,
output [7:0] O_0_1,
output [7:0] O_... | 7.061223 |
module sseqTupleAppender_tInt_n2 (
input [7:0] I0_0,
input [7:0] I0_1,
input [7:0] I1,
output [7:0] O_0,
output [7:0] O_1,
output [7:0] O_2,
output valid_down,
input valid_up
);
assign O_0 = I0_0;
assign O_1 = I0_1;
assign O_2 = I1;
assign valid_down = valid_up;
endmodule
| 7.061223 |
module corebit_and (
input in0,
input in1,
output out
);
assign out = in0 & in1;
endmodule
| 8.125026 |
module coreir_ult #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 < in1;
endmodule
| 7.861561 |
module coreir_term #(
parameter width = 1
) (
input [width-1:0] in
);
endmodule
| 6.849594 |
module coreir_shl #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 << in1;
endmodule
| 8.595943 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module coreir_lshr #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 >> in1;
endmodule
| 8.306547 |
module coreir_eq #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 == in1;
endmodule
| 7.939296 |
module coreir_const #(
parameter width = 1,
parameter value = 1
) (
output [width-1:0] out
);
assign out = value;
endmodule
| 8.127638 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module \commonlib_muxn__N2__width2 (
input [1:0] in_data_0,
input [1:0] in_data_1,
input [0:0] in_sel,
output [1:0] out
);
wire [1:0] _join_out;
coreir_mux #(
.width(2)
) _join (
.in0(in_data_0),
.in1(in_data_1),
.out(_join_out),
.sel(in_sel[0])
);
assign out =... | 7.889703 |
module \commonlib_muxn__N2__width1 (
input [0:0] in_data_0,
input [0:0] in_data_1,
input [0:0] in_sel,
output [0:0] out
);
wire [0:0] _join_out;
coreir_mux #(
.width(1)
) _join (
.in0(in_data_0),
.in1(in_data_1),
.out(_join_out),
.sel(in_sel[0])
);
assign out =... | 7.889703 |
module lutN #(
parameter N = 1,
parameter init = 1
) (
input [N-1:0] in,
output out
);
assign out = init[in];
endmodule
| 7.756611 |
module RShift_Atom (
input [7:0] I__0,
input [7:0] I__1,
output [7:0] O,
output valid_down,
input valid_up
);
wire [7:0] lshr8_inst0_out;
coreir_lshr #(
.width(8)
) lshr8_inst0 (
.in0(I__0),
.in1(I__1),
.out(lshr8_inst0_out)
);
assign O = lshr8_inst0_out;
assign v... | 7.73328 |
module Partition_S_no16_ni1_tElSTuple_3_Int__vTrue (
input clk,
input [7:0] I_0_0,
input [7:0] I_0_1,
input [7:0] I_0_2,
input [7:0] I_10_0,
input [7:0] I_10_1,
input [7:0] I_10_2,
input [7:0] I_11_0,
input [7:0] I_11_1,
input [7:0] I_11_2,
input [7:0] I_12_0,
input [7:0]... | 6.630566 |
module Partition_S_no16_ni1_tElSSeq_1_Int__vTrue (
input clk,
input [7:0] I_0_0_0,
input [7:0] I_10_0_0,
input [7:0] I_11_0_0,
input [7:0] I_12_0_0,
input [7:0] I_13_0_0,
input [7:0] I_14_0_0,
input [7:0] I_15_0_0,
input [7:0] I_1_0_0,
input [7:0] I_2_0_0,
input [7:0] I_3_0_0... | 6.630566 |
module Partition_S_no16_ni1_tElInt_vTrue (
input clk,
input [7:0] I_0_0,
input [7:0] I_10_0,
input [7:0] I_11_0,
input [7:0] I_12_0,
input [7:0] I_13_0,
input [7:0] I_14_0,
input [7:0] I_15_0,
input [7:0] I_1_0,
input [7:0] I_2_0,
input [7:0] I_3_0,
input [7:0] I_4_0,
... | 6.630566 |
module NativeMapParallel_n3 (
input [7:0] I0_0,
input [7:0] I0_1,
input [7:0] I0_2,
input [7:0] I1_0,
input [7:0] I1_1,
input [7:0] I1_2,
output [7:0] O_0__0,
output [7:0] O_0__1,
output [7:0] O_1__0,
output [7:0] O_1__1,
output [7:0] O_2__0,
output [7:0] O_2__1,
outp... | 7.274395 |
module NativeMapParallel_n1_unq3 (
input [7:0] I_0__0,
input [7:0] I_0__1,
output [7:0] O_0,
output valid_down,
input valid_up
);
wire [7:0] RShift_Atom_inst0_O;
wire RShift_Atom_inst0_valid_down;
RShift_Atom RShift_Atom_inst0 (
.I__0(I_0__0),
.I__1(I_0__1),
.O(RShift_Atom_in... | 7.274395 |
module NativeMapParallel_n1_unq4 (
input [7:0] I_0_0__0,
input [7:0] I_0_0__1,
output [7:0] O_0_0,
output valid_down,
input valid_up
);
wire [7:0] NativeMapParallel_n1_inst0_O_0;
wire NativeMapParallel_n1_inst0_valid_down;
NativeMapParallel_n1_unq3 NativeMapParallel_n1_inst0 (
.I_0__0(I_... | 7.274395 |
module NativeMapParallel_n1_unq1 (
input [7:0] I0_0,
input [7:0] I1_0,
output [7:0] O_0__0,
output [7:0] O_0__1,
output valid_down,
input valid_up
);
wire [7:0] atomTupleCreator_t0Int_t1Int_inst0_O__0;
wire [7:0] atomTupleCreator_t0Int_t1Int_inst0_O__1;
wire atomTupleCreator_t0Int_t1Int_in... | 7.274395 |
module NativeMapParallel_n1_unq2 (
input [7:0] I0_0_0,
input [7:0] I1_0_0,
output [7:0] O_0_0__0,
output [7:0] O_0_0__1,
output valid_down,
input valid_up
);
wire [7:0] NativeMapParallel_n1_inst0_O_0__0;
wire [7:0] NativeMapParallel_n1_inst0_O_0__1;
wire NativeMapParallel_n1_inst0_valid_do... | 7.274395 |
module Mux2xOutBits2 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
input S
);
wire [1:0] coreir_commonlib_mux2x2_inst0_out;
\commonlib_muxn__N2__width2 coreir_commonlib_mux2x2_inst0 (
.in_data_0(I0),
.in_data_1(I1),
.in_sel(S),
.out(coreir_commonlib_mux2x2_inst0_out)
);... | 7.816223 |
module Mux2xOutBits1 (
input [0:0] I0,
input [0:0] I1,
output [0:0] O,
input S
);
wire [0:0] coreir_commonlib_mux2x1_inst0_out;
\commonlib_muxn__N2__width1 coreir_commonlib_mux2x1_inst0 (
.in_data_0(I0),
.in_data_1(I1),
.in_sel(S),
.out(coreir_commonlib_mux2x1_inst0_out)
);... | 7.639545 |
module LUT2_8 (
input I0,
input I1,
output O
);
wire coreir_lut2_inst0_out;
lutN #(
.init(4'h8),
.N(2)
) coreir_lut2_inst0 (
.in ({I1, I0}),
.out(coreir_lut2_inst0_out)
);
assign O = coreir_lut2_inst0_out;
endmodule
| 7.722694 |
module LUT1_2 (
input I0,
output O
);
wire coreir_lut1_inst0_out;
lutN #(
.init(2'h2),
.N(1)
) coreir_lut1_inst0 (
.in (I0),
.out(coreir_lut1_inst0_out)
);
assign O = coreir_lut1_inst0_out;
endmodule
| 8.126826 |
module LUT1_1 (
input I0,
output O
);
wire coreir_lut1_inst0_out;
lutN #(
.init(2'h1),
.N(1)
) coreir_lut1_inst0 (
.in (I0),
.out(coreir_lut1_inst0_out)
);
assign O = coreir_lut1_inst0_out;
endmodule
| 7.409016 |
module LUT1_0 (
input I0,
output O
);
wire coreir_lut1_inst0_out;
lutN #(
.init(2'h0),
.N(1)
) coreir_lut1_inst0 (
.in (I0),
.out(coreir_lut1_inst0_out)
);
assign O = coreir_lut1_inst0_out;
endmodule
| 7.399772 |
module LShift_Atom (
input [7:0] I__0,
input [7:0] I__1,
output [7:0] O,
output valid_down,
input valid_up
);
wire [7:0] shl8_inst0_out;
coreir_shl #(
.width(8)
) shl8_inst0 (
.in0(I__0),
.in1(I__1),
.out(shl8_inst0_out)
);
assign O = shl8_inst0_out;
assign valid_... | 8.458485 |
module NativeMapParallel_n3_unq2 (
input [7:0] I_0__0,
input [7:0] I_0__1,
input [7:0] I_1__0,
input [7:0] I_1__1,
input [7:0] I_2__0,
input [7:0] I_2__1,
output [7:0] O_0,
output [7:0] O_1,
output [7:0] O_2,
output valid_down,
input valid_up
);
wire [7:0] LShift_Atom_inst0... | 7.274395 |
module NativeMapParallel_n3_unq3 (
input [7:0] I_0_0__0,
input [7:0] I_0_0__1,
input [7:0] I_0_1__0,
input [7:0] I_0_1__1,
input [7:0] I_0_2__0,
input [7:0] I_0_2__1,
input [7:0] I_1_0__0,
input [7:0] I_1_0__1,
input [7:0] I_1_1__0,
input [7:0] I_1_1__1,
input [7:0] I_1_2__0,... | 7.274395 |
module Register8 (
input clk,
input [7:0] I,
output [7:0] O
);
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst0_O;
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst1_O;
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst2_O;
wire DFF_init0_has_ce... | 6.73316 |
module Register_Array_8_Bit_t_0init_FalseCE_FalseRESET (
input clk,
input [7:0] I,
output [7:0] O
);
wire [7:0] Register8_inst0_O;
Register8 Register8_inst0 (
.clk(clk),
.I (I),
.O (Register8_inst0_O)
);
assign O = Register8_inst0_O;
endmodule
| 7.102239 |
module Register_Array_1_Array_8_Bit__t_0init_FalseCE_FalseRESET (
input clk,
input [7:0] I_0,
output [7:0] O_0
);
wire [7:0] Register_Array_8_Bit_t_0init_FalseCE_FalseRESET_inst0_O;
Register_Array_8_Bit_t_0init_FalseCE_FalseRESET Register_Array_8_Bit_t_0init_FalseCE_FalseRESET_inst0(
.clk(clk),
... | 7.102239 |
module Register_Array_1_Array_1_Array_8_Bit___t_0init_FalseCE_FalseRESET (
input clk,
input [7:0] I_0_0,
output [7:0] O_0_0
);
wire [7:0] Register_Array_1_Array_8_Bit__t_0init_FalseCE_FalseRESET_inst0_O_0;
Register_Array_1_Array_8_Bit__t_0init_FalseCE_FalseRESET Register_Array_1_Array_8_Bit__t_0init_Fal... | 7.102239 |
module Register_Bitt_0init_FalseCE_FalseRESET (
input clk,
input I,
output O
);
wire [0:0] Register1_inst0_O;
Register1 Register1_inst0 (
.clk(clk),
.I (I),
.O (Register1_inst0_O)
);
assign O = Register1_inst0_O[0];
endmodule
| 7.503354 |
module Counter2_Mod4CE (
input CE,
input clk,
output [1:0] O
);
wire [1:0] Counter2CER_inst0_O;
wire LUT2_8_inst0_O;
wire and_inst0_out;
Counter2CER Counter2CER_inst0 (
.CE(CE),
.clk(clk),
.O(Counter2CER_inst0_O),
.RESET(and_inst0_out)
);
LUT2_8 LUT2_8_inst0 (
.I0(C... | 6.745207 |
module Add_Atom (
input [7:0] I__0,
input [7:0] I__1,
output [7:0] O
);
wire [7:0] coreir_add8_inst0_out;
coreir_add #(
.width(8)
) coreir_add8_inst0 (
.in0(I__0),
.in1(I__1),
.out(coreir_add8_inst0_out)
);
assign O = coreir_add8_inst0_out;
endmodule
| 6.918465 |
module renamedForReduce (
input [7:0] in0,
input [7:0] in1,
output [7:0] out
);
wire [7:0] Add_Atom_inst0_O;
Add_Atom Add_Atom_inst0 (
.I__0(in0),
.I__1(in1),
.O(Add_Atom_inst0_O)
);
assign out = Add_Atom_inst0_O;
endmodule
| 7.384035 |
module ReduceParallel_n3 (
input [7:0] I_0,
input [7:0] I_1,
input [7:0] I_2,
output [7:0] O
);
wire [7:0] renamedForReduce_inst0_out;
wire [7:0] renamedForReduce_inst1_out;
renamedForReduce renamedForReduce_inst0 (
.in0(I_0),
.in1(renamedForReduce_inst1_out),
.out(renamedForR... | 7.174445 |
module Reduce_S_n3 (
input clk,
input [7:0] I_0,
input [7:0] I_1,
input [7:0] I_2,
output [7:0] O_0,
output valid_down,
input valid_up
);
wire [7:0] ReduceParallel_n3_inst0_O;
wire [7:0] Register_Array_1_Array_8_Bit__t_0init_FalseCE_FalseRESET_inst0_O_0;
wire [0:0] reg_P_inst0_out;
R... | 7.025687 |
module NativeMapParallel_n3_unq4 (
input clk,
input [7:0] I_0_0,
input [7:0] I_0_1,
input [7:0] I_0_2,
input [7:0] I_1_0,
input [7:0] I_1_1,
input [7:0] I_1_2,
input [7:0] I_2_0,
input [7:0] I_2_1,
input [7:0] I_2_2,
output [7:0] O_0_0,
output [7:0] O_1_0,
output [7:0... | 7.274395 |
module NativeMapParallel_n1 (
input [7:0] I_0__0,
input [7:0] I_0__1,
output [7:0] O_0
);
wire [7:0] Add_Atom_inst0_O;
Add_Atom Add_Atom_inst0 (
.I__0(I_0__0),
.I__1(I_0__1),
.O(Add_Atom_inst0_O)
);
assign O_0 = Add_Atom_inst0_O;
endmodule
| 7.274395 |
module renamedForReduce_unq1 (
input [7:0] in0_0,
input [7:0] in1_0,
output [7:0] out_0
);
wire [7:0] NativeMapParallel_n1_inst0_O_0;
NativeMapParallel_n1 NativeMapParallel_n1_inst0 (
.I_0__0(in0_0),
.I_0__1(in1_0),
.O_0(NativeMapParallel_n1_inst0_O_0)
);
assign out_0 = NativeMap... | 7.384035 |
module ReduceParallel_n3_unq1 (
input [7:0] I_0_0,
input [7:0] I_1_0,
input [7:0] I_2_0,
output [7:0] O_0
);
wire [7:0] renamedForReduce_inst0_out_0;
wire [7:0] renamedForReduce_inst1_out_0;
renamedForReduce_unq1 renamedForReduce_inst0 (
.in0_0(I_1_0),
.in1_0(renamedForReduce_inst1_... | 7.174445 |
module Reduce_S_n3_unq1 (
input clk,
input [7:0] I_0_0,
input [7:0] I_1_0,
input [7:0] I_2_0,
output [7:0] O_0_0,
output valid_down,
input valid_up
);
wire [7:0] ReduceParallel_n3_inst0_O_0;
wire [7:0] Register_Array_1_Array_1_Array_8_Bit___t_0init_FalseCE_FalseRESET_inst0_O_0_0;
wire ... | 7.107378 |
module Conv2d (
input clk,
input [7:0] I_0,
input [7:0] I_1,
input [7:0] I_10,
input [7:0] I_11,
input [7:0] I_12,
input [7:0] I_13,
input [7:0] I_14,
input [7:0] I_15,
input [7:0] I_2,
input [7:0] I_3,
input [7:0] I_4,
input [7:0] I_5,
input [7:0] I_6,
input ... | 7.302381 |
module sseqTupleAppender_tTSeq_3_0_Int__n2 (
input [7:0] I0_0,
input [7:0] I0_1,
input [7:0] I1,
output [7:0] O_0,
output [7:0] O_1,
output [7:0] O_2,
output valid_down,
input valid_up
);
assign O_0 = I0_0;
assign O_1 = I0_1;
assign O_2 = I1;
assign valid_down = valid_up;
endmodu... | 7.061223 |
module sseqTupleAppender_tInt_n2 (
input [7:0] I0_0,
input [7:0] I0_1,
input [7:0] I1,
output [7:0] O_0,
output [7:0] O_1,
output [7:0] O_2,
output valid_down,
input valid_up
);
assign O_0 = I0_0;
assign O_1 = I0_1;
assign O_2 = I1;
assign valid_down = valid_up;
endmodule
| 7.061223 |
module corebit_xor (
input in0,
input in1,
output out
);
assign out = in0 ^ in1;
endmodule
| 7.624638 |
module corebit_not (
input in,
output out
);
assign out = ~in;
endmodule
| 8.318293 |
module corebit_eq (
input I0,
input I1,
output O
);
wire not_inst0_out;
wire xor_inst0_out;
corebit_not not_inst0 (
.in (xor_inst0_out),
.out(not_inst0_out)
);
corebit_xor xor_inst0 (
.in0(I0),
.in1(I1),
.out(xor_inst0_out)
);
assign O = not_inst0_out;
endmodule... | 7.456911 |
module corebit_const #(
parameter value = 1
) (
output out
);
assign out = value;
endmodule
| 7.833235 |
module corebit_and (
input in0,
input in1,
output out
);
assign out = in0 & in1;
endmodule
| 8.125026 |
module coreir_ult #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 < in1;
endmodule
| 7.861561 |
module coreir_term #(
parameter width = 1
) (
input [width-1:0] in
);
endmodule
| 6.849594 |
module coreir_slice #(
parameter hi = 1,
parameter lo = 0,
parameter width = 1
) (
input [width-1:0] in,
output [hi-lo-1:0] out
);
assign out = in[hi-1:lo];
endmodule
| 8.799926 |
module coreir_shl #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 << in1;
endmodule
| 8.595943 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module coreir_mem #(
parameter has_init = 0,
parameter depth = 1,
parameter width = 1
) (
input clk,
input [width-1:0] wdata,
input [$clog2(depth)-1:0] waddr,
input wen,
output [width-1:0] rdata,
input [$clog2(depth)-1:0] raddr
);
reg [width-1:0] data[depth-1:0];
always @(posedge... | 7.482949 |
module coreir_lshr #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 >> in1;
endmodule
| 8.306547 |
module coreir_eq #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 == in1;
endmodule
| 7.939296 |
module coreir_const #(
parameter width = 1,
parameter value = 1
) (
output [width-1:0] out
);
assign out = value;
endmodule
| 8.127638 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module \commonlib_muxn__N2__width8 (
input [7:0] in_data_0,
input [7:0] in_data_1,
input [0:0] in_sel,
output [7:0] out
);
wire [7:0] _join_out;
coreir_mux #(
.width(8)
) _join (
.in0(in_data_0),
.in1(in_data_1),
.out(_join_out),
.sel(in_sel[0])
);
assign out =... | 7.889703 |
module \commonlib_muxn__N4__width8 (
input [7:0] in_data_0,
input [7:0] in_data_1,
input [7:0] in_data_2,
input [7:0] in_data_3,
input [1:0] in_sel,
output [7:0] out
);
wire [7:0] _join_out;
wire [7:0] muxN_0_out;
wire [7:0] muxN_1_out;
wire [0:0] sel_slice0_out;
wire [0:0] sel_sl... | 7.889703 |
module \commonlib_muxn__N2__width4 (
input [3:0] in_data_0,
input [3:0] in_data_1,
input [0:0] in_sel,
output [3:0] out
);
wire [3:0] _join_out;
coreir_mux #(
.width(4)
) _join (
.in0(in_data_0),
.in1(in_data_1),
.out(_join_out),
.sel(in_sel[0])
);
assign out =... | 7.889703 |
module \commonlib_muxn__N2__width3 (
input [2:0] in_data_0,
input [2:0] in_data_1,
input [0:0] in_sel,
output [2:0] out
);
wire [2:0] _join_out;
coreir_mux #(
.width(3)
) _join (
.in0(in_data_0),
.in1(in_data_1),
.out(_join_out),
.sel(in_sel[0])
);
assign out =... | 7.889703 |
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