code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Contador_Corriente (
input wire clkc,
input wire resetc,
input wire enc,
input wire upc,
input wire downc,
output wire [4:0] qc
);
//Signal Declarations
reg [4:0] q_actc, q_nextc;
//Body of "state" registers
always @(posedge clkc, posedge resetc)
if (resetc) q_actc <= 5'b0... | 6.687076 |
module contador_decadico (
clk,
clear,
s
);
input clk, clear;
output [3:0] s;
wire and1;
wire and2;
wire and3;
wire clr_aux;
// parte combinacional para o contador
assign and3 = (s[3] & s[1]);
assign clr_aux = and3 | clear;
// usando flip-flops jk para montar um contador de modulo 10... | 6.960246 |
module contador_gray_cond (
clk,
reset_L,
enable,
salida_gray
);
input clk, reset_L, enable;
output [4:0] salida_gray;
wire [4:0] salida_gray;
reg [4:0] contador;
always @(posedge clk)
if (!reset_L) contador <= 0;
else if (enable) contador <= contador + 1;
assign salida_gray = {... | 7.5841 |
module contador_TB ();
wire clk;
wire enable;
wire reset_L;
wire [4:0] salida_gray_cond;
wire [4:0] salida_gray_est;
contador_Tester T_1 (
.clk(clk),
.reset_L(reset_L),
.enable(enable),
.salida_gray_cond(salida_gray_cond),
.salida_gray_est(salida_gray_est)
);
contador_gr... | 6.609938 |
module contador_Tester (
output reg clk,
output reg reset_L,
output reg enable,
input [4:0] salida_gray_cond,
input [4:0] salida_gray_est
);
reg Comparador;
reg estructural;
reg conductual;
always begin
#1 clk = ~clk;
end
initial begin
clk = 1;
... | 6.638459 |
module Contagem_Dsp7Seg (
input wire FPGA_CLK,
output reg [7:0] SEG,
output wire [3:0] DIG
);
// --> Constantees: Pulsos de clock para cada intervalo de tempo
parameter TICK_D0 = 18'd50000; // Contagem de pulsos para inserir o valor no 1o digito
parameter TICK_D1 = 18'd100000; // Contagem de pulsos ... | 7.391725 |
module contain_20b(
input [19:0] x_in,
input [19:0] y_in,
input [19:0] z_in,
output [`TARGET-1:0] x_out,
output [`TARGET-1:0] y_out,
output [`TARGET-1:0] z_out
)
// contain 20 bit signed int to 9 bit
parameter TARGET = 5'd9;
wire [4:0] x_hi;
hi_one_pos hi0(.in(x_in),.out(x_hi));
wire [4:0] y_hi;
hi_one_pos h... | 7.7817 |
module ContextNestingBottom ( // @[:@3.2]
input [3:0] io_in1, // @[:@6.4]
input [3:0] io_in2, // @[:@6.4]
output [4:0] io_outDefault, // @[:@6.4]
output [4:0] io_outWrap, // @[:@6.4]
output [4:0] io_outGrow // @[:@6.4]
);
wire [3:0] _T_3 = io_in1 + io_in2; // @[UIntTypeClass.scala 23:22:@12... | 7.532728 |
module ContextNestingBottom_1 ( // @[:@20.2]
input [3:0] io_in1, // @[:@23.4]
input [3:0] io_in2, // @[:@23.4]
output [4:0] io_outDefault, // @[:@23.4]
output [4:0] io_outWrap, // @[:@23.4]
output [4:0] io_outGrow // @[:@23.4]
);
wire [3:0] _T_3 = io_in1 + io_in2; // @[UIntTypeClass.scala 2... | 7.532728 |
module ContextNestingTop ( // @[:@36.2]
input clock, // @[:@37.4]
input reset, // @[:@38.4]
input [3:0] io_in1, // @[:@39.4]
input [3:0] io_in2, // @[:@39.4]
output [4:0] io_mod1Default, // @[:@39.4]
output [4:0] io_mod1Wrap, // @[:@39.... | 7.532728 |
module ContextNestingBottom (
input [3:0] io_in1,
input [3:0] io_in2,
output [4:0] io_outDefault,
output [4:0] io_outWrap,
output [4:0] io_outGrow
);
wire [3:0] _T_3 = io_in1 + io_in2; // @[UIntTypeClass.scala 23:22]
assign io_outDefault = {{1'd0}, _T_3}; // @[UIntTypeClass.scala 23:22]
as... | 7.532728 |
module ContextNestingBottom_1 (
input [3:0] io_in1,
input [3:0] io_in2,
output [4:0] io_outDefault,
output [4:0] io_outWrap,
output [4:0] io_outGrow
);
wire [3:0] _T_3 = io_in1 + io_in2; // @[UIntTypeClass.scala 23:22]
assign io_outDefault = io_in1 + io_in2; // @[UIntTypeClass.scala 22:22]
... | 7.532728 |
module ContextNestingTop (
input clock,
input reset,
input [3:0] io_in1,
input [3:0] io_in2,
output [4:0] io_mod1Default,
output [4:0] io_mod1Wrap,
output [4:0] io_mod1Grow,
output [4:0] io_mod2Default,
output [4:0] io_mod2Wrap,
output [4:0] io_mod2Grow
);
wire ... | 7.532728 |
module context_2x2 #(
parameter H_SIZE = 800 //800 //83 //1650
) (
input clk,
input [7 : 0] pixel_in,
input de_in,
input h_sync_in,
input v_sync_in,
output context_valid,
output A11_hsync,
output A11_vsync,
output [7 : 0] A11,
output [7 : 0] A12,
output [7 : 0] A21,
... | 6.666957 |
module context_3x3 #(
parameter H_SIZE = 2200 //800 //83 //1650
) (
input clk,
input [7 : 0] pixel_in,
input de_in,
input h_sync_in,
input v_sync_in,
output context_valid,
output [10 : 0] center,
output [10 : 0] up,
output [10 : 0] down,
output [10 : 0] left,
output [... | 7.228296 |
module context_handler_sync #(
parameter CHDR_W = 256,
parameter ITEM_W = 32,
parameter NIPC = 2
) (
// Clock and reset
input wire clk,
input wire rst,
// Context stream in (AXI-Stream)
input wire [CHDR_W-1:0] s_axis_context_tdata,
input wire [ 3... | 7.40262 |
module context_level #(
parameter H_SIZE = 800,//800 //83 //1650
parameter CONTEXT_SIZE = 7,
parameter CONTEXT_CENTER = 4,
parameter P_GUESS_INT_WIDTH = 6
)
(
input clk,
input [7 : 0] pixel_in,
input de_in,
input h_sync_in,
input v_sync_in,
input signed [P_GUESS_INT_WIDTH-1... | 8.020416 |
module context_update (
Errval,
A_Q,
B_Q,
C_Q,
N_Q,
A_Q_update,
B_Q_update,
C_Q_update,
N_Q_update,
C_Q_sign
);
input signed [8:0] Errval;
input [12:0] A_Q;
input signed [6:0] B_Q;
input signed [7:0] C_Q;
input [6:0] N_Q;
output [12:0] A_Q_update;
output signed [6:... | 6.821279 |
module contin_mode_openclose (
input clk_25m,
input rst_n,
input [15:0] datain,
input fifo_full1_in,
output reg [15:0] dataout,
output reg fifo_full1_out
);
reg contin_mode_open_reg;
always @(posedge clk_25m or negedge rst_n) begin
if (!rst_n) begin
contin_mode_open_reg <= 0;
... | 6.984846 |
module ALUControl (
input [2:0] ALUOp,
input [2:0] fn,
output reg [3:0] ALUOperation
);
parameter [2:0] ARTHEMATIC = 3'b000, SHIFT = 3'b001, MEM = 3'b010;
always @(ALUOp, fn) begin
if (ALUOp == ARTHEMATIC)
case (fn)
3'b000: ALUOperation <= 4'b0000; //add
3'b001: ALUOperation... | 8.639118 |
module Contoller (
input clk,
rst,
input [18:0] Instruction,
input Zero,
carryOut,
output reg RegWrite,
ConstEnable,
MemRead,
MemWrite,
MemToReg,
RegTwoAddr,
BranchSel,
JumpSel,
noChange,
push,
pop,
StackSel,
Halt,
output [3:0] ALUOperation
);
... | 6.934609 |
module contor (
contor,
ascii_out,
done,
reset,
clock
);
input [15:0] contor; // one digit ascii
output [7:0] ascii_out;
output done;
input reset;
input clock;
wire [15:0] in;
wire [15:0] time_counter; // 2 digit ascii
wire decrement;
wire [6:0] index;
assign in = conto... | 6.766198 |
module contrastBrightness (
input [23:0] tRGB,
input clk,
input reset,
output [23:0] uptRGB
);
wire [ 7:0] tR;
wire [ 7:0] tG;
wire [ 7:0] tB;
reg [10:0] uptRtest;
reg [10:0] uptGtest;
reg [10:0] uptBtest;
wire [ 7:0] uptR;
wire [ 7:0] uptG;
wire [ 7:0] uptB;
assign tR = tRGB[... | 7.12191 |
module deco (
input [8:0] i_instruccion,
output reg [3:0] condJ,
output reg [2:0] Sel_op,
output reg [5:0] Sel_reg,
output reg W,
output reg [1:0] Sel_outbus,
output reg [2:0] Sel_DW,
input rst,
input clk
);
parameter
LoadRxNum =3'b000,
LoadRxARy =3'b001,
StoreARxNum... | 6.676829 |
module jump (
input [3:0] condJ,
input [7:0] Rx,
input [2:0] Ban,
output [7:0] o_direccion_instruccion,
input rst,
input clk
);
reg [7:0] PC;
always @(posedge clk, posedge rst) begin
if (rst) PC <= 0;
else
case (condJ)
4'b0000: PC <= PC;
4'b0001: // etapa de ... | 8.472182 |
module of the accelerator, with below function.
// Input data needs 785 cycles to finish the inner product.
// So '7fffffff' is added around 800th entry in the weight data
// and on reading the same counter1 stalls at 800 and doesn't
// incremen... | 7.222527 |
module control1 (
RegDst,
Jump,
Branch,
MemRead,
MemtoReg,
ALUop,
MemWrite,
ALUSrc,
RegWrite,
Sign,
instruction
);
//I use the disjucnctive normal form to define each control output
output wire RegDst;
output wire Branch;
output wire MemRead;
output wire MemtoReg;
... | 6.876486 |
module control1 (
clk,
rst_n,
key_pressed,
answer,
wait_counter,
prepare_judge,
enable_counter,
change_instruction,
decrease_life
);
input clk; // Clock
input rst_n; // Asynchronous reset active low
input key_pressed; //User input new answer, 1 when key is pressed
input a... | 6.876486 |
module control (
input [5:0] op,
output reg [2:0] alu_op,
output reg [1:0] regDst,
output reg aluSrc,
output reg [1:0] memToReg,
output reg regWrite,
memRead,
memWrite,
branch,
jump
);
always @(*) begin
case (op)
6'h0 : //R-format
begin
regDst <= 2'b1;
... | 7.715617 |
module Controlador (
input wire clk,
input wire [7:0] entrada_dados,
//input wire print_flag, // vai receber do modulo do sensor quando é para passar a proxima tira
input wire ready, // vai receber do pwm quando é que é para enviar o proximo bit
input wire controlador_valid,
output reg saida_da... | 6.552554 |
module controladortest2;
// Inputs
reg clock;
// Outputs
wire enablegain;
wire enableadc;
wire enabledac;
wire spissb;
wire sf_ce0;
wire fpgainitb;
// Instantiate the Unit Under Test (UUT)
controlador uut (
.clock(clock),
.enablegain(enablegain),
.enableadc(enableadc),
... | 7.206208 |
module controlador_memoria (
codigo_produto,
valor_preco,
produto_existe
);
input [3:0] codigo_produto; //codigo do produto na maquina
output reg [3:0] valor_preco; // preco do produto
output reg produto_existe; //se o produto existe ou nao
always @(codigo_produto) begin
case (codigo_produt... | 7.133289 |
module controlador_principal (
input wire clk,
input produto_existe,
valor_correto,
tempo,
input [1:0] habilitador,
output reg [1:0] estado
);
localparam [1:0] q0 = 0, q1 = 1, q2 = 2, q3 = 3;
reg [1:0] estado_reg, estado_prox;
always @(posedge clk) begin
estado_reg <= estado_prox;
... | 6.522258 |
module ControlCenter
/*** PARAMETERS ***/
#(
parameter
// WL
CLOCKSPEED = 100000000
)
/*** IN/OUT ***/
(
// IN
input clk, // Probably won't need this
btnC, // Function:
btnU, // Function: increase
btnL, // Function:
btnR, // Function:
btnD, // Function:
// Sw... | 7.7066 |
module ControlCircuit_tb;
reg clk; //250Hz
reg rst;
reg key_flag;
reg [3:0] key_val;
wire [3:0] money1out, money0out, time1out, time0out;
wire [1:0] state;
ControlCircuit CC (
.clk(clk),
.rst(rst),
.key_flag(key_flag),
.key_val(key_val),
.money1out(money1o... | 7.409627 |
module controlcodes (
input [31:0] instr,
output [ 2:0] alucontrol
);
reg [2:0] alucontrol;
always @(instr) begin
casex ({
instr[31:26], instr[5:0]
})
// Sets the value of alucontrol based on which function we are doing (found from the opcode and funct field)
12'b000100xxxxxx: a... | 7.53396 |
module controldivfreq (
rst,
clk32,
clk_d1,
clk_d2,
pd_before,
pd_after,
clk_i,
clk_q
);
input rst; //复位信号，高电平有效
input clk32; //FPGA系统时钟:32MHz
input clk_d1;
input clk_d2;
input pd_before;
input pd_after;
output clk_i;
output clk_q;
wire gate_open, gate_close, clk_in... | 8.016456 |
module microstore (output reg FR, RF, IR, MAR,
MDR, ReadWrite, MOV, MC, MD, ME, output reg [1:0] MA,
output reg [1:0] MB, output reg [4:0] OP, input [5:0] state );
always @ (state)
case(state):
6'b000000:
FR = 0;
RF = 1;
IR = 0;
MAR = 0;
MDR = 0;
ReadWrite = 0;
MOV = 0;
MA = 2'b00;
... | 6.744273 |
module inverter (output reg InvOut, input In, Inv);
always @ (In, Inv)
case(Inv):
1'b0:
if(In == 0) InvOut = 0;
else InvOut = 1;
1'b1:
if(In == 1) InvOut = 0;
else InvOut = 1;
endcase
endmodule
| 7.365361 |
module InverterMux (output reg InvIn, input MOC, Cond,
Entrythree, Entryfour, input [1:0] S);
always @ (S) begin
case(S):
2'b00: InvIn = MOC;
2'b01: InvIn = Cond;
2'b10: InvIn = Entrythree;
2'b11: InvIn = Entryfour;
endcase
end
endmodule
| 7.278959 |
module inverter (output reg InvOut, input In, VarInv);
always @ (In, VarInv)
case(VarInv):
1'b0:
if(In == 0) InvOut = 0;
else InvOut = 1;
1'b1:
if(In == 1) InvOut = 0;
else InvOut = 1;
endcase
endmodule
| 7.365361 |
module InverterMux (output reg InvIn, input MOC, Cond,
Entrythree, Entryfour, input [1:0] S);
always @ (S) begin
case(S):
2'b00: InvIn = MOC;
2'b01: InvIn = Cond;
2'b10: InvIn = Entrythree;
2'b11: InvIn = Entryfour;
endcase
end
endmodule
| 7.278959 |
module Controle (
OPcode,
bit_menos_sig,
halt,
addi,
jump,
beq,
dadoEscrito,
acessarMemoria,
imediato,
escreveMemoria,
leMemoria,
operacaoULA,
escreveRegistrador,
lw
);
input wire [2:0] OPcode;
input wire bit_menos_sig;
output wire halt;
output wire addi;... | 6.5869 |
module controleAlu (
opAlu,
twoandOne,
sinal_ula
);
input [2:0] opAlu;
output reg twoandOne;
output reg [2:0] sinal_ula;
always @(*) begin
if (opAlu[1] & opAlu[2]) begin
twoandOne = 1;
end else begin
twoandOne = 0;
end
sinal_ula = opAlu;
end
endmodule
| 7.42724 |
module controleAlu_tb ();
reg [2:0] opAlu;
wire twoandOne;
wire [2:0] sinal_ula;
controleAlu control (
opAlu,
twoandOne,
sinal_ula
);
initial begin
//$dumpfile ("testbench/ALU_tb.vcd");
//$dumpvars(0, ALU_tb);
$monitor("opAlu = %d, twoandOne = %b, sinal_ula = %d", o... | 6.521065 |
module controler #(
parameter WR_LEN = 16,
RD_LEN = 8
) (
input clk,
input rst_n,
//user port
input [7:0] din,
input din_vld,
input rd_en,
output [7:0] dout,
output dout_vld,
input tx_busy, //串口发送忙标志
//mem port
output i2c_scl,
... | 7.510012 |
module controlfibonacci (
input clk,
fov,
fcarry,
fneg,
fzero,
rst_in,
output reg [7:0] selection_sr,
selection_multa,
selection_alu,
selection_multb,
output reg rst_out,
output reg [3:0] writer
);
reg [2:0] sState, rState;
parameter [2:0] AssignFunc = 3'b000;
par... | 7.628975 |
module ControlFlushMux (
select,
regDst,
gt_bra,
le_bra,
eq_bra,
memRead,
memToReg,
aluOp,
memWrite,
regWrite,
jump,
seOp,
regDstOut,
gt_braOut,
le_braOut,
eq_braOut,
memReadOut,
memToRegOut,
aluOpOut,
memWriteOut,
regWriteOut,
jump... | 7.374742 |
module ControlInterface #(
parameter ADDR_BITS = 4,
parameter DATA_BITS = 8
) (
output [DATA_BITS-1 : 0] controlWord,
output [ADDR_BITS-1 : 0] controlAddress,
output wire controlReady,
input wire SCLK,
input wire MOSI,
input wire SS
);
parameter REGISTER_SIZE = ADDR_BITS + DATA_BITS;
... | 8.522416 |
module controlKeyboard (
input clk,
input resetn,
input ps2_key_pressed,
input [7:0] last_data_received,
output reg left,
right,
enter,
startGame
);
reg [2:0] current_state, next_state;
localparam S_IDLE = 3'b000, S_MAKE = 3'b001, S_BREAKCODE1 = 3'b010, S_BREAKCODE2 = 3'b100;
... | 7.737283 |
module ControlledIncrementor (
input A,
input [7:0] Z,
output [7:0] Out
);
wire [7:0] w;
wire [7:0] Cin;
assign w = (A == 1'b1) ? 1 : 0;
HalfAdder H (
Z[0],
w[0],
Out[0],
Cin[0]
);
genvar j;
generate
begin
for (j = 1; j < 8; j = j + 1) begin
FullAd... | 6.866516 |
module ControllerD (
input [5:0] Op,
input [5:0] Funct,
input Equal,
input LTZ,
input EQZ,
output NPCOp,
output [1:0] ExtOp,
output [1:0] PCSrc,
output GenD
);
wire addu, subu, ori, lw, sw, beq, lui, j, jal, jr, nop;
assign addu = (Op == `R) && (Funct == `ADDU),
subu = (O... | 6.817521 |
module ControllerE (
input [5:0] Op,
input [5:0] Funct,
output [3:0] ALUOp,
output ALUSrc,
output [1:0] GenE
);
wire addu, subu, ori, lw, sw, beq, lui, j, jal, jr, nop;
assign addu = (Op == `R) && (Funct == `ADDU),
subu = (Op == `R) && (Funct == `SUBU),
ori = (Op == `ORI),
lw... | 7.178287 |
module ControllerM (
input [5:0] Op,
input [5:0] Funct,
output MemWrite,
output [1:0] OpWidth,
output LoadSigned,
output GenM
);
wire addu, subu, ori, lw, sw, beq, lui, j, jal, jr, nop;
assign addu = (Op == `R) && (Funct == `ADDU),
subu = (Op == `R) && (Funct == `SUBU),
ori = (... | 6.900166 |
module.v */
`timescale 1ns / 1ps
module ControllerTopmodule
(
input wire CLK_50MHZ,
input wire BTN_WEST, /* reset button */
inout wire PS2_CLK,
inout wire PS2_DATA,
output wire [7:0] LED,
output wire [3:0] VGA_R,
output wire [3:0] VGA_G,
output wire [3:0] VGA_B,
output wire VGA_HS,
output wire VGA_V... | 8.021191 |
module ControllerW (
input [5:0] Op,
input [5:0] Funct,
output RegWrite
);
wire addu, subu, ori, lw, sw, beq, lui, j, jal, jr, nop;
assign addu = (Op == `R) && (Funct == `ADDU),
subu = (Op == `R) && (Funct == `SUBU),
ori = (Op == `ORI),
lw = (Op == `LW),
sw = (Op == `SW),
... | 6.967541 |
module controller_4_display (
input [3:0] a,
b,
c,
d,
input clk,
output [6:0] disp,
output [3:0] transistor
);
wire [7:0] count;
wire mux_disp;
decoder_7seg_4b i_decoder (
.in (mux_disp),
.out(disp)
);
soft_gtv i_soft_gtv (
.rst(0),
.clk(clk),
.spd_b... | 7.601956 |
module cnt3b (
input clk,
en,
ld,
input [2:0] inp,
output reg [2:0] out,
output co
);
always @(posedge clk) begin
if (ld) out <= inp;
else if (en) out <= out + 1;
end
assign co = &{out, ~ld};
endmodule
| 6.885576 |
module reg8b (
input clk,
rst,
en,
input [7:0] inp,
output reg [7:0] out
);
always @(posedge clk, posedge rst) begin
if (rst) out <= 8'b00000000;
else if (en) out <= inp;
end
endmodule
| 7.750283 |
module datapath (
input clk,
ld_en,
cnt_en,
cnt_rst,
c3_ld,
c3_en,
UXRX,
output co3,
output [7:0] N
);
wire co8;
wire [7:0] cnt8;
wire [2:0] cnt3;
cnt8b BRG_Counter (
clk,
cnt_en,
cnt_rst,
cnt8,
co8
);
reg8b BRG_Reg (
clk,
1'b0,
... | 6.91752 |
module Controller_FSM (
input clk_100,
input x,
output [1:0] state,
output rst_n
);
localparam STATEMENT = 0;
localparam START = 1;
localparam CLOSE = 2;
reg [ 1:0] cur_state = 0;
reg [ 1:0] next_state = 0;
reg [25:0] counter = 0;
always @(posedge clk_100) begin
case (cur_state)
... | 7.191421 |
module controller_instruction_rom_0 (
// inputs:
address,
address2,
byteenable,
byteenable2,
... | 6.781468 |
module controller_jtag_uart_0_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [8:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr;
... | 6.630967 |
module controller_jtag_uart_0_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [8:0] wfifo_used;
input clk;
input fifo_clea... | 6.630967 |
module controller_jtag_uart_0_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [8:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg ... | 6.630967 |
module controller_jtag_uart_0_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [8:0] rfifo_used;
input clk;
i... | 6.630967 |
module is working,set 1
//inner_busy:set 1 to enable hash_core and message_schedule module
//first_block_core : when the first cycle of the core dealing with the first block ,set 1
///////////////////////////////////////
module controller(
input wire clk,
input wire reset,
... | 6.727661 |
module controller_qam_16 #(
parameter wid_count = 4
) (
input clk,
input rst_clk,
input rst_n,
input ready_mapper,
input ready_zero,
input ready_filter,
output clk_164, ... | 6.551429 |
module controller_ram_duel_port (
address_a,
address_b,
byteena_a,
clock_a,
clock_b,
data_a,
data_b,
rden_a,
rden_b,
wren_a,
wren_b,
q_a,
q_b);
input [13:0] address_a;
input [13:0] address_b;
input [3:0] byteena_a;
input clock_a;
input clock_b;
input [31:0] data_a;
input [31:0] data_b;
in... | 6.764452 |
module controller_ram_duel_port (
address_a,
address_b,
byteena_a,
clock_a,
clock_b,
data_a,
data_b,
rden_a,
rden_b,
wren_a,
wren_b,
q_a,
q_b
);
input [13:0] address_a;
input [13:0] address_b;
input [3:0] byteena_a;
input clock_a;
input clock_b;
input [31... | 6.764452 |
module controller_rom #(
parameter top_address = 16'h8000,
address_size = 5'd14
) (
input clk,
input reset_n,
// Instruction
input [14:0] instruction_addr,
output [31:0] instruction_q,
input iBus_cmd_valid,
// Data Bus
input [15:0] data_addr,
input [31:0] data_d... | 8.471229 |
module controller_rtl_29 (
input clock,
reset,
input x,
y,
E,
F
);
parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010;
parameter S3 = 3'b011;
parameter S4 = 3'b100;
parameter S5 = 3'b101;
parameter S6 = 3'b110;
parameter S7 = 3'b111;
reg [2:0] state, next_stat... | 7.051171 |
module controller (clk,
rst_n,
test_mode,
operation,
//DECLEARE_MARCHC
//DECLEARE_MARCHA
//DECLEARE_APNPSF
complete);
//-------------------------------
input clk;
input rst_n;
input test_mode;
input [2:0]operation;
//COMPLETE_MARCHC_INPUT
//COMPLET... | 7.691033 |
module Controller_SystolicArray (
output reg rst,
output reg clr,
output reg start_PE11,
output reg start_PE12,
output reg start_PE21,
output reg start_PE22,
input wire PE11_delayed_done,
input wire PE22_delayed_done,
input wire idle,
input wire clr,
input wire rst,
inpu... | 6.906548 |
module controller_unit (
/* input signals */
input wire [ 7 : 0] opcode, /* opcode byte */
input wire [`FWIDTH - 1 : 0] flags, /* ALU flags */
input wire clk, /* clock signal */
input wire res, /* reset signal */... | 6.530527 |
module controller_unit_tb;
/* input signals */
reg [7:0] opcode;
reg clk;
reg res;
/* output signals */
wire [1:0] ac_source;
wire write_ac;
wire mar_source;
wire write_mar;
wire [1:0] mdr_source;
wire write_mdr;
wire write_flags;
wire [1:0] pc_source;
wire write_pc;
wire write_ir;
wir... | 6.530527 |
module controller_v1 (
z,
c,
clk,
CLB,
op,
LoadIR,
IncPC,
SelPC,
LoadPC,
LoadReg,
LoadAcc,
SelAcc,
SelALU
);
// input define
input wire z, c, clk, CLB;
input wire [3:0] op;
// output define
output reg LoadIR, IncPC, SelPC, LoadPC, LoadReg, LoadAcc;
output... | 6.503922 |
module that take an input of 4-bit
opcode representing the operation taking
place and outputs a corresponding one-hot
number representing the input opcode.
=================================================
*/
module controlLogic (opCode, sel);
//---------------------------------------------
//Local Parame... | 8.081392 |
module ControlModule (
clk,
rst,
operation,
run
);
// Inputs
input clk;
input rst;
input [1:0] operation;
input run;
// Registered Outputs
output reg [31:0] INSel;
output reg [3:0] ALUMODE;
output reg [6:0] OPMODE;
output reg [4:0] INMODE;
output reg MemWrite;
output reg Write... | 7.466042 |
module ControlMux (
out,
inA,
inB,
sel
);
output reg [17:0] out;
input [17:0] inA;
input [17:0] inB;
input sel;
always @(*) begin
if (sel == 0) begin
out <= inA;
end else begin
out <= inB;
end
end
endmodule
| 6.889262 |
module ControlPanel (
SinIn,
PWMIn,
TriangularIn,
rectangleIn,
SignalOut,
OutMode,
reset
);
input reset;
input [15:0] SinIn, PWMIn, TriangularIn, rectangleIn;
output reg [15:0] SignalOut;
input [1:0] OutMode;
/**********选择输出波形************/
always @(*) begin
case (OutMode)
... | 6.733734 |
module ControlRegister (
inout [7:0] Data,
input ReadSignal,
input WriteSignal,
input [5:0] cw0_i,
input [5:0] cw1_i,
input [5:0] cw2_i,
input [2:0] EnabStatusLatches_i,
output [5:0] cw0_o,
output [5:0] cw1_o,
output [5:0] cw2_o,
output reg [2:0] readback,
output [2:0] En... | 6.822423 |
module controls (
input rst,
input[7:0] sw, //switch inputs
input clk,
output btn_adj,
output btn_left_right,
output btn_shoot,
);
endmodule
| 6.556343 |
module controlSign (
input [2:0] state,
input [5:0] opCode,
input zero,
input sign,
output reg IRWre,
output reg PCWre,
output reg ALUSrcA,
output reg ALUSrcB,
output reg DBDataSrc,
output reg RegWre,
output reg WrRegDSrc,
output reg InsMemRW,
output reg mRD,
outp... | 7.282938 |
module nopSet (
clk,
s1,
s2,
oldF,
oldD,
newF,
newD
);
input clk, s1, s2;
input [31:0] oldF, oldD;
output reg [31:0] newD, newF;
initial begin
end
always @(posedge clk) begin
if (s1 == 1'b0 && s2 == 1'b0) begin
newF = 32'b0;
newD = 32'b0;
end else if (s1 == 1... | 6.777343 |
module controlstate (
clk,
rst_n,
enable,
cod_start,
cod_clr,
PI_en,
dl_en,
ADD_en,
dp_en,
mc_en,
filter_en,
over
);
input clk, rst_n, enable, over;
output cod_start, cod_clr, PI_en, dl_en, ADD_en, dp_en, mc_en, filter_en;
reg cod_start, cod_clr, PI_en, dl_en, ADD_e... | 6.674955 |
module controlsuma (
input clk,
fov,
fcarry,
fneg,
fzero,
output reg [7:0] instreg,
instmulta,
instalu,
instmultb,
output reg escr1,
escr2,
escr3,
escr0
);
reg rEstado, sEstado;
parameter AssignFunc = 0;
parameter SavingData = 1;
initial begin
sEstado ... | 6.658024 |
module ControlSystem (
input clk,
input [15:0] sw,
input btnL,
input btnU,
input btnC,
input btnD,
input btnR,
input PS2Clk,
input PS2Data,
inout [3:0] JB,
output [15:0] led,
output [6:0] seg,
output [3:0] an,
output dp,
output [3:0] vgaRed,
output [3:0] v... | 6.865765 |
module, replase magic number with pre-defined macros
*/
module ControlUnit
(PCSrc, resultSrc, memWrite, ALUControl, ALUSrc, immSrc, regWrite, opcode, funct3, funct7, zero);
`include "Parameters.vh"
input [6 : 0] opcode; // Operation code of an instruction
input [2 : 0] funct3; // function ... | 8.375445 |
module ControlUnitCurrentState (
input [2:0] NextState,
output reg [2:0] CurrentState,
input clk,
input reset
);
always @(posedge clk) begin
if (reset == 1) CurrentState = 3'd0;
else CurrentState = NextState;
end
endmodule
| 7.328817 |
module ControlUnitMUX (
input [10:0] controlInstruction_in,
input ControlWire,
output reg [10:0] controlMuxout
);
reg [10:0] zeroData = 10'b0;
always @(*)
case (ControlWire)
0: controlMuxout = zeroData;
1: controlMuxout = controlInstruction_in;
default: controlMuxout = controlInst... | 8.414875 |
module: ControlUnit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_control;
// Inputs
reg arst;
reg clk;
reg request;
reg confirm;
reg [1:0] password;
reg [1:0] syskey;
... | 7.944032 |
module controleUnitTeste;
integer dataLine; //número total de linhas a serem lidas do arquivo de entrada.
reg [6:0] inputDatas[0:13];
//Entradas
reg clk;
reg reset;
reg [3:0] opCode;
reg printtingScreen;
reg done;
reg rdempty;
//////////////////////////////
//Saídas
wire new_instruction;
... | 7.287324 |
module controlUnitTester ();
reg [3:0] opcode;
wire RegWrite;
wire MemtoReg;
wire MemWrite;
wire [2:0] ALUControl1;
wire [2:0] ALUControl2;
wire ALUSrc;
wire RegDst;
wire PCEn;
wire MemRead;
controlUnit CU_1 (
opcode,
RegWrite,
MemtoReg,
MemWrite,
ALUControl1,
... | 7.426107 |
module ControlUnit_tb;
`include "../src/utils/Assert.vh"
`include "../src/Parameters.vh"
// Input stimulus
reg [6 : 0] opcode;
reg [2 : 0] funct3;
reg funct7;
reg zero;
// Output
wire PCSrc;
wire resultSrc;
wire memWrite;
wire [2 : 0] ALUControl;
wire ALUSrc;
wire [1 : 0] immSrc;
wire reg... | 6.552998 |
module: ControlUnit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ControlUnit_TEST;
reg [5:0] opcode;
wire RegDst;
wire ALUSrc;
wire MemtoReg;
wire RegWrite;
... | 7.944032 |
module ControlUnit_TestCase;
// Inputs
reg [5:0] opCode;
// Outputs
wire regDst;
wire aluSrc;
wire memtoReg;
wire regWrite;
wire memRead;
wire memWrite;
wire branch;
wire [2:0] aluOp;
// Instantiate the Unit Under Test (UUT)
Mips_ControlUnit uut (
.opCode(opCode),
.regDst(regDst... | 6.90858 |
module: CU
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module controlUnit_tf;
// Inputs
reg [5:0] op;
reg zero;
// Outputs
wire RegOut;
wire InsMenRW;
wire ExtSel;
wire DataMe... | 6.786456 |
module ControlWordRegister (
inout [7:0] Data,
input WriteSignal,
input [5:0] ControlWord0i,
input [5:0] ControlWord1i,
input [5:0] ControlWord2i,
output [5:0] ControlWord0o,
output [5:0] ControlWord1o,
output [5:0] ControlWord2o,
input [2:0] EnableCounterLatchi,
output [2:... | 7.056116 |
module control_2_tb_v;
parameter delay = 160;
// Inputs
reg clk;
reg ButtonOut;
reg reset;
// Outputs
wire clear;
wire count;
wire stop;
// Instantiate the Unit Under Test (UUT)
control_2 control_2_tb (
.clk(clk),
.button_out(ButtonOut),
.clear(clear),
.count(count),
... | 6.624989 |
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