Datasets:
Formats:
text
Languages:
English
Size:
1K - 10K
Tags:
circuit-diagrams
document-understanding
graph-recovery
connectivity-verification
vision-language-models
digital-logic
License:
| license: cc-by-4.0 | |
| language: | |
| - en | |
| tags: | |
| - circuit-diagrams | |
| - document-understanding | |
| - graph-recovery | |
| - connectivity-verification | |
| - vision-language-models | |
| - digital-logic | |
| size_categories: | |
| - 1K<n<10K | |
| pretty_name: LogicBench-1K | |
| # LogicBench-1K | |
| Digital logic circuit diagrams with topology-level ground-truth graph annotations. | |
| **Official repository:** [github.com/tkcl-research/LogicBench1k](https://github.com/tkcl-research/LogicBench1k) | |
| ## Paper | |
| > **Stroke-Level Connectivity Verification: Grounding Vision-Language Models Against Topology Hallucination in Diagram Understanding** | |
| > Abdullah Ibne Hanif Arean, Niamul Hassan Samin, Md Arifur Rahman, Renu Akter Suity, Juena Ahmed Noshin, and Md Ashikur Rahman | |
| > *International Conference on Document Analysis and Recognition (ICDAR), 2026* | |
| ## Dataset summary | |
| | Property | Value | | |
| |----------|-------| | |
| | Samples | 1,000 | | |
| | Image format | JPEG, 512x512 px | | |
| | Annotation format | JSON (directed graph per image) | | |
| | Train / Val / Test | 700 / 100 / 200 | | |
| | Gate vocabulary | AND, OR, NOT, NAND, NOR, XOR, XNOR | | |
| | Total gates / edges | 6,174 / 6,423 | | |
| ## Dataset structure | |
| ``` | |
| LogicBench-1K/ | |
| ├── images/ | |
| ├── annotations/ | |
| │ └── splits/ | |
| ├── metadata/ | |
| └── schema/ | |
| ``` | |
| ## Splits | |
| | Split | File | Count | Sample ID range | | |
| |-------|------|-------|-----------------| | |
| | Test | `annotations/splits/test.txt` | 200 | lb1k_00000-lb1k_00199 | | |
| | Train | `annotations/splits/train.txt` | 700 | lb1k_00200-lb1k_00899 | | |
| | Validation | `annotations/splits/val.txt` | 100 | lb1k_00900-lb1k_00999 | | |
| ## Load a sample | |
| ```python | |
| import json | |
| from huggingface_hub import hf_hub_download | |
| sample_id = "lb1k_00042" | |
| ann_path = hf_hub_download("TKCL-HF/LogicBench-1K", f"annotations/{sample_id}.json", repo_type="dataset") | |
| img_path = hf_hub_download("TKCL-HF/LogicBench-1K", f"images/{sample_id}.jpg", repo_type="dataset") | |
| with open(ann_path) as f: | |
| graph = json.load(f) | |
| ``` | |
| ## Citation | |
| If you use LogicBench-1K, please cite: | |
| > **Stroke-Level Connectivity Verification: Grounding Vision-Language Models Against Topology Hallucination in Diagram Understanding** | |
| > Abdullah Ibne Hanif Arean, Niamul Hassan Samin, Md Arifur Rahman, Renu Akter Suity, Juena Ahmed Noshin, and Md Ashikur Rahman | |
| > *International Conference on Document Analysis and Recognition (ICDAR), 2026* | |
| ```bibtex | |
| @inproceedings{arean2026slcv, | |
| author = {{Abdullah Ibne Hanif Arean} and {Niamul Hassan Samin} and {Md Arifur Rahman} and {Renu Akter Suity} and {Juena Ahmed Noshin} and {Md Ashikur Rahman}}, | |
| title = {Stroke-Level Connectivity Verification: Grounding Vision-Language Models Against Topology Hallucination in Diagram Understanding}, | |
| booktitle = {International Conference on Document Analysis and Recognition (ICDAR)}, | |
| year = {2026} | |
| } | |
| ``` | |
| ## License | |
| [Creative Commons Attribution 4.0 International (CC BY 4.0)](https://creativecommons.org/licenses/by/4.0/) | |