repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/acl_fp_sqrt.v | 81,598 | module MODULE1
(
VAR64,
VAR101,
VAR93,
VAR26,
VAR45) ;
input VAR64;
input VAR101;
input VAR93;
input [25:0] VAR26;
output [24:0] VAR45;
tri0 VAR64;
tri1 VAR101;
tri0 VAR93;
reg [23:0] VAR2;
reg [23:0] VAR131;
reg [23:0] VAR24;
reg [23:0] VAR85;
reg [23:0] VAR89;
reg [23:0] VAR3;
reg [23:0] VAR80;
reg [23:0] VAR34;
reg ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv3sd3/sky130_fd_sc_ls__clkdlyinv3sd3_1.v | 2,164 | module MODULE2 (
VAR5 ,
VAR8 ,
VAR7,
VAR2,
VAR4 ,
VAR6
);
output VAR5 ;
input VAR8 ;
input VAR7;
input VAR2;
input VAR4 ;
input VAR6 ;
VAR1 VAR3 (
.VAR5(VAR5),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR5,
VAR8
);
output VAR5;
input VAR8;
supply1 VAR7;
supply0 VAR2;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_28.v | 2,215 | module MODULE2 (
VAR3,
VAR6 ,
VAR5 ,
VAR4 ,
VAR1
);
output VAR3;
input VAR6 ;
input VAR5 ;
input VAR4 ;
input VAR1 ;
VAR7 VAR2 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR3,
VAR6
);
output VAR3;
input VAR6 ;
supply1 VAR5;
supply1 VAR4 ;
supply0 VAR1 ;
VAR7 VAR2 (
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4b/sky130_fd_sc_lp__and4b_4.v | 2,300 | module MODULE2 (
VAR7 ,
VAR1 ,
VAR5 ,
VAR11 ,
VAR6 ,
VAR10,
VAR3,
VAR4 ,
VAR2
);
output VAR7 ;
input VAR1 ;
input VAR5 ;
input VAR11 ;
input VAR6 ;
input VAR10;
input VAR3;
input VAR4 ;
input VAR2 ;
VAR8 VAR9 (
.VAR7(VAR7),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR4(VAR4),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_gpiov2/sky130_fd_io__top_gpiov2.behavioral.v | 41,380 | module MODULE1 (VAR24, VAR43,VAR36,VAR31,
VAR7, VAR72, VAR56, VAR34, VAR30, VAR32, VAR65, VAR57, VAR21, VAR2,
VAR37, VAR58, VAR63, VAR6, VAR67, VAR18, VAR3, VAR35, VAR28,
VAR9, VAR39, VAR61, VAR42
);
input VAR39;
input VAR2;
input VAR56;
input VAR65;
input VAR21;
input VAR57;
input VAR28;
input VAR35;
input VAR30;
inpu... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlxbp/sky130_fd_sc_ls__dlxbp.functional.pp.v | 1,822 | module MODULE1 (
VAR6 ,
VAR14 ,
VAR1 ,
VAR10,
VAR5,
VAR4,
VAR7 ,
VAR3
);
output VAR6 ;
output VAR14 ;
input VAR1 ;
input VAR10;
input VAR5;
input VAR4;
input VAR7 ;
input VAR3 ;
wire VAR13;
VAR8 VAR2 VAR9 (VAR13 , VAR1, VAR10, , VAR5, VAR4);
buf VAR12 (VAR6 , VAR13 );
not VAR11 (VAR14 , VAR13 );
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/next_hop_ram.v | 1,148 | module MODULE1(clk, addr, VAR7, VAR8, VAR10, en, reset);
input clk;
input [12:2] addr;
input [31:0] VAR7;
output [31:0] VAR8;
input [3:0] VAR10;
input en;
input reset;
wire [3:0] VAR12;
VAR9 VAR4 (
.address ( addr[12:2] ),
.VAR16 ( clk ),
.VAR3 ( VAR7[7:0] ),
.VAR20 ( en ),
.VAR2 ( VAR10[0] ),
.VAR19 ( VAR8[7:0] )
);
... | mit |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_spram_64x14.v | 12,787 | module MODULE1(
VAR9, VAR3, VAR23,
clk, rst, VAR24, VAR52, VAR26, addr, VAR30, VAR33
);
parameter VAR21 = 6;
parameter VAR39 = 14;
input VAR9;
input [VAR12 - 1:0] VAR23;
output VAR3;
input clk; input rst; input VAR24; input VAR52; input VAR26; input [VAR21-1:0] addr; input [VAR39-1:0] VAR30; output [VAR39-1:0] VAR33;
w... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_v6_gtx_x4_250/source/pcie_pipe_misc_v6.v | 7,525 | module MODULE1 #
(
parameter VAR6 = 0 )
(
input wire VAR8 ,
input wire VAR7 ,
input wire VAR20 ,
input wire VAR12 ,
input wire [2:0] VAR9 ,
input wire VAR18 ,
output wire VAR28 ,
output wire VAR21 ,
output wire VAR19 ,
output wire VAR10 ,
output wire [2:0] VAR23 ,
output wire VAR4 ,
input wire VAR22 ,
input wire VAR5
)... | lgpl-3.0 |
secworks/gcm | src/rtl/gcm_ghash.v | 4,933 | module MODULE1(
input wire clk,
input wire VAR8,
input wire VAR13,
input wire VAR20,
input wire [127 : 0] h0,
input wire [127 : 0] VAR22,
output wire [127 : 0] VAR9,
output wire ready
);
function [127 : 0] VAR3(input [127 : 0] VAR15);
begin
VAR3 = {VAR15[126 : 0], 1'b0} ^ (128'h1b & {128{VAR15[127]}});
end
endfunction
... | bsd-2-clause |
apotocnik/redpitaya_guide | cores/axi_bram_reader_v1_0/axi_bram_reader.v | 3,094 | module MODULE1 #
(
parameter integer VAR53 = 32,
parameter integer VAR6 = 13,
parameter integer VAR35 = 32,
parameter integer VAR18 = 15
)
(
output VAR13,
input [VAR53-1:0] VAR1,
output [VAR53-1:0] VAR56,
output [VAR6-1:0] VAR42,
output [3:0] VAR2,
output VAR12,
output VAR49,
input wire VAR14,
input wire VAR59,
input w... | gpl-3.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/niosII_microc_lab1/db/ip/niosII_system/submodules/niosII_system_nios2_qsys_0_jtag_debug_module_sysclk.v | 7,153 | module MODULE1 (
clk,
VAR7,
VAR33,
VAR28,
VAR29,
VAR13,
VAR26,
VAR6,
VAR4,
VAR18,
VAR30,
VAR17,
VAR24,
VAR25,
VAR27,
VAR5,
VAR21,
VAR12,
VAR9
)
;
output [ 37: 0] VAR13;
output VAR26;
output VAR6;
output VAR4;
output VAR18;
output VAR30;
output VAR17;
output VAR24;
output VAR25;
output VAR27;
output VAR5;
output VAR21;
... | gpl-2.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/uart16550/bench/verilog/uart_device_utilities.v | 11,431 | module MODULE1;
task VAR13;
input [3:0] VAR21;
begin
end
endtask
task VAR51;
begin
end
endtask
task VAR25;
begin
end
endtask
task VAR2;
begin
end
endtask
task VAR15;
begin
end
endtask
task VAR33;
begin
end
endtask
task VAR29;
input VAR4;
begin
if (~VAR4)
begin
end
begin
end
else
begin
end
... | gpl-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_avalon_st_adapter.v | 6,212 | module MODULE1 #(
parameter VAR18 = 34,
parameter VAR22 = 0,
parameter VAR3 = 34,
parameter VAR23 = 0,
parameter VAR25 = 0,
parameter VAR19 = 0,
parameter VAR21 = 1,
parameter VAR5 = 1,
parameter VAR1 = 0,
parameter VAR9 = 34,
parameter VAR8 = 0,
parameter VAR10 = 1,
parameter VAR20 = 0,
parameter VAR6 = 1,
parameter V... | gpl-3.0 |
vipinkmenon/scas | hw/fpga/source/memory_if/mig_7series_v1_8_ecc_merge_enc.v | 5,947 | module MODULE1
parameter VAR19 = 100,
parameter VAR24 = 64,
parameter VAR21 = 72,
parameter VAR1 = 4,
parameter VAR23 = 1,
parameter VAR3 = 64,
parameter VAR27 = 72,
parameter VAR25 = 8,
parameter VAR20 = 4
)
(
VAR10, VAR4,
clk, rst, VAR22, VAR14, VAR7, VAR17, VAR29
);
input clk;
input rst;
input [2*VAR20*VAR24-1:0] VA... | mit |
prernaa/CPUVerilog | memory/phase2_unified/memory.v | 2,722 | module MODULE1( clk, rst, VAR18, VAR32, addr, VAR25, VAR33, VAR15);
parameter VAR31=16;
parameter VAR5=16;
parameter VAR2=2;parameter VAR11=3;
input clk;
input rst;
input VAR18;
input VAR32;
input [VAR31-1:0] addr; input [VAR5-1:0] VAR25; input [3:0] VAR33;
output [VAR5-1:0] VAR15;
reg [VAR5-1:0] MODULE1 [0:2**VAR31-1]... | mit |
scalable-networks/ext | uhd/fpga/usrp2/fifo/ll8_to_fifo19.v | 3,517 | module MODULE1
(input clk, input reset, input VAR30,
input [7:0] VAR6,
input VAR16,
input VAR44,
input VAR37,
output VAR46,
output [18:0] VAR43,
output VAR39,
input VAR3 );
wire [7:0] VAR35;
wire VAR15, VAR11, VAR8, VAR25;
VAR12 VAR41
(.clk(clk), .reset(reset), .VAR30(VAR30),
.VAR4(VAR6), .VAR1(VAR16), .VAR18(VAR44),
.... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapvgnd2/sky130_fd_sc_ls__tapvgnd2.symbol.v | 1,276 | module MODULE1 ();
supply1 VAR4;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/alt_vipvfr131_common_unpack_data.v | 1,455 | module MODULE1
( VAR12,
reset,
VAR19,
read,
VAR15,
VAR18,
write,
VAR9,
VAR13);
parameter VAR5 = 128;
parameter VAR11 = 24;
input VAR12;
input reset;
input [VAR5 - 1 : 0] VAR19;
output read;
input VAR15;
input VAR9;
output reg write;
output [VAR11 - 1:0] VAR18;
input VAR13;
wire VAR17;
wire VAR14;
assign VAR14 = ~VAR15;... | mit |
kyzhai/NUNY | src/hardware/nuny_new2.v | 6,414 | module MODULE1 (
address,
VAR31,
VAR6);
input [14:0] address;
input VAR31;
output [11:0] VAR6;
tri1 VAR31;
wire [11:0] VAR9;
wire [11:0] VAR6 = VAR9[11:0];
VAR52 VAR28 (
.VAR46 (address),
.VAR14 (VAR31),
.VAR34 (VAR9),
.VAR44 (1'b0),
.VAR10 (1'b0),
.VAR4 (1'b1),
.VAR18 (1'b0),
.VAR12 (1'b0),
.VAR51 (1'b1),
.VAR26 (1'b1... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inputiso0p/sky130_fd_sc_hdll__inputiso0p.pp.symbol.v | 1,372 | module MODULE1 (
input VAR1 ,
output VAR7 ,
input VAR4,
input VAR2 ,
input VAR5 ,
input VAR6 ,
input VAR3
);
endmodule | apache-2.0 |
AngelTerrones/ADA | rtl/ada_bram.v | 2,163 | module MODULE1 #(
parameter VAR9 = 32,
parameter VAR6 = 8
)(
input VAR13,
input VAR12,
input [VAR6-1:0] VAR14,
input [VAR9-1:0] VAR8,
output reg [VAR9-1:0] VAR2,
input VAR11,
input VAR1,
input [VAR6-1:0] VAR10,
input [VAR9-1:0] VAR5,
output reg [VAR9-1:0] VAR4
);
reg [VAR9-1:0] VAR3 [(2**VAR6)-1:0];
integer VAR7; | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor3b/sky130_fd_sc_hs__nor3b.pp.blackbox.v | 1,295 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR3 ,
VAR2 ,
VAR5,
VAR6
);
output VAR1 ;
input VAR4 ;
input VAR3 ;
input VAR2 ;
input VAR5;
input VAR6;
endmodule | apache-2.0 |
martinmiranda14/Digitales | Lab_6/new/VGA_driver.v | 4,053 | module MODULE1(VAR8, VAR2, VAR16,VAR12,VAR15);
input VAR8; output VAR2, VAR16;
output [9:0]VAR12;
output [9:0]VAR15;
parameter VAR9 = 10'd800; parameter VAR6 = 10'd500;
parameter VAR4 = 10'd16; parameter VAR7 = 10'd64; parameter VAR10 = 10'd80;
parameter VAR3 = 10'd3; parameter VAR13 = 10'd4; parameter VAR14 = 10'd13;
... | apache-2.0 |
tmolteno/TART | hardware/FPGA/fifo/fifo15l.v | 6,243 | module MODULE1 (
VAR39,
VAR12,
VAR26,
VAR13,
VAR16,
VAR28,
VAR10,
VAR2,
VAR38,
VAR43,
VAR6, VAR21,
VAR9
);
parameter VAR42 = 16;
input VAR39;
input VAR12;
input VAR26;
output [VAR42-1:0] VAR13;
input VAR16;
input VAR28;
input [VAR42-1:0] VAR10;
output VAR2;
output VAR38;
output VAR43;
output VAR6;
output VAR21;
output ... | lgpl-3.0 |
kevintownsend/convey_spmv | rtl/pe/spmv_pe.v | 20,740 | module MODULE1(clk, VAR10, VAR16, VAR11, VAR7, VAR13, VAR3, VAR17, VAR4, VAR8, VAR21, VAR23, VAR15, VAR19, VAR1, VAR9, VAR5, VAR14, VAR6, VAR12, VAR2, VAR25);
parameter VAR20 = 0;
input clk;
input [63:0] VAR10;
output [63:0] VAR16;
input VAR11;
output VAR7;
output reg VAR13;
output reg VAR3;
output reg [47:0] VAR17;
ou... | apache-2.0 |
niketancm/tsea26 | lab2-3/rtl/bit_reversal.v | 1,029 | module MODULE1
(
input wire [VAR4-1:0] VAR2,
input wire [2:0] VAR3,
output reg [VAR4-1:0] VAR5);
integer VAR1;
always@* begin
VAR5 = VAR2;
casex(VAR3)
3'b000: for(VAR1=1;VAR1<7;VAR1=VAR1+1)
VAR5[VAR1] = VAR2[7-VAR1];
3'b001: for(VAR1=1;VAR1<8;VAR1=VAR1+1)
VAR5[VAR1] = VAR2[8-VAR1];
3'b010: for(VAR1=1;VAR1<9;VAR1=VAR1+1... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/decap/sky130_fd_sc_hvl__decap_4.v | 1,878 | module MODULE1 (
VAR6,
VAR2,
VAR1 ,
VAR3
);
input VAR6;
input VAR2;
input VAR1 ;
input VAR3 ;
VAR5 VAR4 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule
module MODULE1 ();
supply1 VAR6;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR3 ;
VAR5 VAR4 ();
endmodule | apache-2.0 |
James534/Tempest | fpga/fpga_hw/top_level/DE0_Nano_SOPC/synthesis/submodules/DE0_Nano_SOPC_cpu_jtag_debug_module_tck.v | 8,218 | module MODULE1 (
VAR7,
VAR1,
VAR10,
VAR30,
VAR8,
VAR17,
VAR18,
VAR25,
VAR16,
VAR33,
VAR5,
VAR31,
VAR37,
VAR22,
VAR13,
VAR3,
VAR27,
VAR23,
VAR24,
VAR21,
VAR32,
VAR14,
VAR2,
VAR6,
VAR12,
VAR20,
VAR29,
VAR28,
VAR11,
VAR36,
VAR19
)
;
output [ 1: 0] VAR29;
output VAR28;
output [ 37: 0] VAR11;
output VAR36;
output VAR19;
inp... | mit |
google/skywater-pdk-libs-sky130_fd_io | cells/top_gpiov2/sky130_fd_io__top_gpiov2.functional.v | 30,040 | module MODULE1 (VAR94, VAR2,VAR90,VAR89,
VAR5, VAR32, VAR82, VAR100, VAR56, VAR7, VAR63, VAR38, VAR49, VAR71,
VAR16, VAR130, VAR30, VAR53, VAR70, VAR78, VAR23, VAR110, VAR74,
VAR26, VAR62, VAR124, VAR137
);
input VAR62;
input VAR71;
input VAR82;
input VAR63;
input VAR49;
input VAR38;
input VAR74;
input VAR110;
input VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a31o/sky130_fd_sc_hdll__a31o.behavioral.pp.v | 2,046 | module MODULE1 (
VAR2 ,
VAR15 ,
VAR16 ,
VAR3 ,
VAR6 ,
VAR8,
VAR7,
VAR9 ,
VAR10
);
output VAR2 ;
input VAR15 ;
input VAR16 ;
input VAR3 ;
input VAR6 ;
input VAR8;
input VAR7;
input VAR9 ;
input VAR10 ;
wire VAR4 ;
wire VAR13 ;
wire VAR5;
and VAR17 (VAR4 , VAR3, VAR15, VAR16 );
or VAR14 (VAR13 , VAR4, VAR6 );
VAR12 VAR1 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/buflp/sky130_fd_sc_lp__buflp_2.v | 2,024 | module MODULE2 (
VAR7 ,
VAR6 ,
VAR3,
VAR2,
VAR4 ,
VAR1
);
output VAR7 ;
input VAR6 ;
input VAR3;
input VAR2;
input VAR4 ;
input VAR1 ;
VAR5 VAR8 (
.VAR7(VAR7),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR7,
VAR6
);
output VAR7;
input VAR6;
supply1 VAR3;
supply0 VAR2;... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_4.behavioral.v | 5,359 | module MODULE1( VAR1, VAR9, VAR5, VAR7, VAR3, VAR10, VAR2 );
input VAR3, VAR10, VAR2, VAR5, VAR1, VAR9;
output VAR7;
VAR6 VAR4(.VAR1(VAR1),.VAR9(VAR9),.VAR5(VAR5),.VAR7(VAR7),.VAR3(VAR3),.VAR10(VAR10),.VAR2(VAR2));
VAR6 VAR8(.VAR1(VAR1),.VAR9(VAR9),.VAR5(VAR5),.VAR7(VAR7),.VAR3(VAR3),.VAR10(VAR10),.VAR2(VAR2)); | apache-2.0 |
uwsampa/zynqWrapper | hardware/system_top.v | 5,946 | module MODULE1
(
VAR25,
VAR6,
VAR41,
VAR7,
VAR24,
VAR28,
VAR50,
VAR43,
VAR66,
VAR30,
VAR3,
VAR51,
VAR4,
VAR55,
VAR1,
VAR34,
VAR32,
VAR57,
VAR17,
VAR19,
VAR60
);
inout [53:0] VAR25;
input VAR6;
input VAR41;
input VAR7;
inout VAR24;
inout VAR28;
inout VAR50;
inout VAR43;
inout VAR66;
inout VAR30;
output VAR3;
inout [2:0]... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o21ai/sky130_fd_sc_ms__o21ai.behavioral.v | 1,530 | module MODULE1 (
VAR3 ,
VAR13,
VAR6,
VAR4
);
output VAR3 ;
input VAR13;
input VAR6;
input VAR4;
supply1 VAR12;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR7 ;
wire VAR8 ;
wire VAR9;
or VAR11 (VAR8 , VAR6, VAR13 );
nand VAR5 (VAR9, VAR4, VAR8 );
buf VAR10 (VAR3 , VAR9 );
endmodule | apache-2.0 |
azonenberg/antikernel-ipcores | noc/rpcv3/RPCv3EchoNode.v | 5,316 | module MODULE1 #(
parameter VAR10 = 32,
parameter VAR33 = 16'h0000
) (
input wire clk,
output wire VAR7,
output wire[VAR10-1:0] VAR32,
input wire VAR25,
input wire VAR15,
input wire[VAR10-1:0] VAR18,
output wire VAR5);
wire VAR8;
wire VAR3;
wire[15:0] VAR26;
wire[15:0] VAR16;
wire[7:0] VAR29;
wire[2:0] VAR23;
wire[20:0... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4/sky130_fd_sc_ms__and4.functional.v | 1,296 | module MODULE1 (
VAR3,
VAR5,
VAR7,
VAR6,
VAR1
);
output VAR3;
input VAR5;
input VAR7;
input VAR6;
input VAR1;
wire VAR2;
and VAR4 (VAR2, VAR5, VAR7, VAR6, VAR1 );
buf VAR8 (VAR3 , VAR2 );
endmodule | apache-2.0 |
freecores/eco32 | fpga/src/dsp/display.v | 2,870 | module MODULE1(clk,
VAR20, VAR62, VAR39, VAR51,
VAR26, VAR46,
VAR43, VAR45, VAR15, VAR25, VAR33);
input clk;
input [4:0] VAR20;
input [6:0] VAR62;
input VAR39;
input VAR51;
input [15:0] VAR26;
output [15:0] VAR46;
output VAR43;
output VAR45;
output [2:0] VAR15;
output [2:0] VAR25;
output [2:0] VAR33;
wire VAR23;
wire [... | bsd-2-clause |
rkrajnc/minimig-mist | rtl/minimig/agnus_beamcounter.v | 17,047 | module MODULE1
(
input clk, input VAR40,
input reset, input VAR14, input VAR97, input VAR94,
input VAR50, input VAR24, input [15:0] VAR71, output reg [15:0] VAR41, input [8:1] VAR10, output reg [8:0] VAR51, output reg [10:0] VAR26, output reg VAR84, output reg VAR79, output VAR75, output reg VAR68, output VAR83, output... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv3sd3/sky130_fd_sc_ls__clkdlyinv3sd3.functional.pp.v | 1,867 | module MODULE1 (
VAR10 ,
VAR8 ,
VAR12,
VAR6,
VAR3 ,
VAR4
);
output VAR10 ;
input VAR8 ;
input VAR12;
input VAR6;
input VAR3 ;
input VAR4 ;
wire VAR5 ;
wire VAR9;
not VAR11 (VAR5 , VAR8 );
VAR7 VAR2 (VAR9, VAR5, VAR12, VAR6);
buf VAR1 (VAR10 , VAR9 );
endmodule | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mem/db_mv_ram.v | 4,259 | module MODULE1(
VAR17 ,
VAR10 ,
VAR12 ,
VAR20 ,
VAR14 ,
VAR3 ,
VAR1 ,
VAR9 ,
VAR18 ,
VAR4 ,
VAR2 ,
VAR11 ,
VAR7 ,
VAR5
);
parameter VAR21 = 2*VAR16 ;
parameter VAR19 = 7 ;
input VAR17 ; input VAR10 ; input VAR12 ; input VAR20 ; input [VAR19-1:0] VAR14; input [VAR21-1:0] VAR1; output [VAR21-1:0] VAR3;
input VAR9 ; input... | gpl-3.0 |
chriz2600/DreamcastHDMI | Core/source/i2c_slave/i2cSlave.v | 8,469 | module MODULE1 (
input clk,
input rst,
inout VAR48,
input VAR25,
output[7:0] VAR5,
output[9:0] VAR64,
output VAR43,
output VAR23,
output[7:0] VAR31,
output[7:0] VAR73,
output[7:0] VAR11,
output VAR3 VAR72,
output [23:0] VAR62,
output VAR52,
output VAR7,
output[7:0] VAR26,
output VAR37,
output VAR1,
output [1:0] VAR9,
i... | mit |
hoangt/NOCulator | hring/hw/buffered/src/c_wf_alloc_mux.v | 4,727 | module MODULE1
(clk, reset, VAR1, req, VAR24);
parameter VAR9 = 8;
localparam VAR7 = VAR3(VAR9);
parameter VAR4 = 0;
parameter VAR30 = VAR16;
input clk;
input reset;
input VAR1;
input [0:VAR9*VAR9-1] req;
output [0:VAR9*VAR9-1] VAR24;
wire [0:VAR9*VAR9-1] VAR24;
wire [0:VAR7-1] VAR28, VAR37, VAR6;
VAR31
.VAR18(0),
.VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv.functional.v | 1,367 | module MODULE1 (
VAR5,
VAR6
);
output VAR5;
input VAR6 ;
wire VAR2;
wire VAR1;
pulldown VAR4 (VAR2 );
bufif0 VAR3 (VAR5, VAR1, VAR6 );
endmodule | apache-2.0 |
csail-csg/riscy-OOO | procs/asic/bluespec_verilog/RegA.v | 2,264 | module MODULE1(VAR5, VAR2, VAR6, VAR1, VAR9);
parameter VAR3 = 1;
parameter VAR10 = { VAR3 {1'b0}} ;
input VAR5;
input VAR2;
input VAR9;
input [VAR3 - 1 : 0] VAR1;
output [VAR3 - 1 : 0] VAR6;
reg [VAR3 - 1 : 0] VAR6;
always@(posedge VAR5 or VAR4 VAR2) begin
if (VAR2 == VAR8)
VAR6 <= VAR7 VAR10;
end
else
begin
if (VAR9)... | mit |
bluespec/Flute | builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkCSR_MIP.v | 9,917 | module MODULE1(VAR34,
VAR10,
VAR50,
VAR54,
VAR41,
VAR62,
VAR30,
VAR61,
VAR37,
VAR33,
VAR36,
VAR20,
VAR56,
VAR17,
VAR63,
VAR70,
VAR64);
input VAR34;
input VAR10;
input VAR50;
output [63 : 0] VAR54;
input [27 : 0] VAR41;
input [63 : 0] VAR62;
input VAR30;
output [63 : 0] VAR61;
output [63 : 0] VAR37;
input [27 : 0] VAR33... | apache-2.0 |
lvd2/ngs | fpga/current/dma/dma_fifo_oneshot.v | 1,471 | module MODULE1(
input wire clk,
input wire VAR18,
input wire VAR9, input wire VAR3,
output wire VAR17, output wire VAR5, output wire VAR13, output wire VAR7,
input wire [7:0] VAR11, output wire [7:0] rd );
reg [9:0] VAR6;
reg [9:0] VAR1;
always @(posedge clk, negedge VAR18)
if( !VAR18 )
VAR6 = 10'd0;
else if( VAR9 )
VA... | gpl-3.0 |
olgirard/openmsp430 | core/synthesis/actel/src/smartgen/dmem.v | 2,908 | module MODULE1(VAR49,VAR68,VAR39,VAR17,VAR56,VAR5,VAR4,VAR31);
input [7:0] VAR49;
output [7:0] VAR68;
input VAR39, VAR17;
input [9:0] VAR56, VAR5;
input VAR4, VAR31;
wire VAR80, VAR73;
VAR80 VAR67(.VAR75(VAR80));
VAR73 VAR77(.VAR75(VAR73));
VAR19 VAR21(.VAR85(VAR73), .VAR45(VAR73), .VAR81(
VAR56[9]), .VAR23(VAR56[8]), ... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/probec_p/sky130_fd_sc_hd__probec_p_8.v | 2,065 | module MODULE1 (
VAR5 ,
VAR8 ,
VAR2,
VAR3 ,
VAR6 ,
VAR4
);
output VAR5 ;
input VAR8 ;
input VAR2;
input VAR3 ;
input VAR6 ;
input VAR4;
VAR7 VAR1 (
.VAR5(VAR5),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR5,
VAR8
);
output VAR5;
input VAR8;
supply0 VAR2;
supply0 VAR3... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/probe_p/sky130_fd_sc_hvl__probe_p.functional.pp.v | 1,796 | module MODULE1 (
VAR1 ,
VAR8 ,
VAR12,
VAR6,
VAR9 ,
VAR7
);
output VAR1 ;
input VAR8 ;
input VAR12;
input VAR6;
input VAR9 ;
input VAR7 ;
wire VAR4 ;
wire VAR3;
buf VAR2 (VAR4 , VAR8 );
VAR5 VAR11 (VAR3, VAR4, VAR12, VAR6);
buf VAR10 (VAR1 , VAR3 );
endmodule | apache-2.0 |
chriswynnyk/american-put-verilog | american_put_cyclone/src/value_buffer.v | 1,211 | module MODULE1(
clk,
VAR7,
VAR16,
VAR6,
VAR2,
VAR8,
VAR10,
VAR3,
VAR15,
VAR11,
VAR12,
VAR9,
VAR14
);
input clk;
input [63:0] VAR7;
input [63:0] VAR16;
input [63:0] VAR6;
input [63:0] VAR2;
output [63:0] VAR8;
output [63:0] VAR10;
output [63:0] VAR3;
output [63:0] VAR15;
output [63:0] VAR11;
output [63:0] VAR12;
output ... | apache-2.0 |
cliffordwolf/yosys | techlibs/xilinx/lut_map.v | 3,503 | module MODULE1 (VAR14, VAR19);
parameter VAR4 = 0;
parameter VAR35 = 0;
input [VAR4-1:0] VAR14;
output VAR19;
generate
if (VAR4 == 1) begin
if (VAR35 == 2'b01) begin
VAR11 VAR5 (.VAR15(VAR19), .VAR3(VAR14[0]));
end else begin
VAR17 #(.VAR10(VAR35)) VAR5 (.VAR15(VAR19),
.VAR26(VAR14[0]));
end
end else
if (VAR4 == 2) beg... | isc |
VectorBlox/PYNQ | Pynq-Z1/vivado/ip/arduino_io_switch_1.0/src/arduino_switch_analog_top.v | 6,259 | module MODULE1(
input [11:0] VAR14, input [5:0] VAR15, output [5:0] VAR24, output [5:0] VAR22,
output [5:0] VAR9, input [5:0] VAR28, input [5:0] VAR27, output [5:0] VAR2, output VAR20,
input VAR26,
input VAR10,
output VAR5,
input VAR19,
input VAR17
);
assign VAR2 = VAR9;
VAR11 VAR12( .VAR6(VAR14[1:0]),
.VAR21(VAR24[0])... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and2b/sky130_fd_sc_hd__and2b.blackbox.v | 1,270 | module MODULE1 (
VAR4 ,
VAR7,
VAR5
);
output VAR4 ;
input VAR7;
input VAR5 ;
supply1 VAR1;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
spacemonkeydelivers/mor1kx | rtl/verilog/mor1kx_store_buffer.v | 2,679 | module MODULE1
parameter VAR29 = 4,
parameter VAR19 = 32
)
(
input clk,
input rst,
input [VAR19-1:0] VAR25,
input [VAR19-1:0] VAR23,
input [VAR19-1:0] VAR31,
input [VAR19/8-1:0] VAR7,
input VAR28,
input VAR8,
output [VAR19-1:0] VAR30,
output [VAR19-1:0] VAR10,
output [VAR19-1:0] VAR15,
output [VAR19/8-1:0] VAR9,
output... | mpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfrbp/sky130_fd_sc_hs__dfrbp.pp.blackbox.v | 1,343 | module MODULE1 (
VAR7,
VAR2 ,
VAR4 ,
VAR3 ,
VAR6 ,
VAR1 ,
VAR5
);
input VAR7;
input VAR2 ;
input VAR4 ;
output VAR3 ;
output VAR6 ;
input VAR1 ;
input VAR5 ;
endmodule | apache-2.0 |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/submodules/niosII_system_timer_0.v | 6,781 | module MODULE1 (
address,
VAR16,
clk,
VAR21,
VAR19,
VAR22,
irq,
VAR33
)
;
output irq;
output [ 15: 0] VAR33;
input [ 2: 0] address;
input VAR16;
input clk;
input VAR21;
input VAR19;
input [ 15: 0] VAR22;
wire VAR13;
wire VAR28;
wire VAR15;
reg [ 3: 0] VAR10;
wire VAR8;
reg VAR6;
wire VAR4;
wire [ 31: 0] VAR27;
reg [ 31... | apache-2.0 |
Marcoslz22/Tercer_Proyecto | TOP.v | 4,900 | module MODULE1
(
input clk,
input reset,
input [7:0] VAR12,
input VAR15,
input VAR65,
output [7:0] VAR108,
output VAR23,VAR31,VAR24,VAR64, VAR55, VAR66,
output [7:0] VAR13,
output reg VAR8
);
wire VAR7, interrupt,VAR78, VAR2, VAR92, VAR38,VAR25, VAR20,VAR75,VAR72,VAR16,VAR50;
wire VAR100,VAR101;
wire [7:0] VAR49;
wire ... | mit |
emqual/titan_wiggle | titan_wiggle/source/ddr3_init_sm.v | 1,151 | module MODULE1 (rst, clk, VAR9, VAR8);
input wire rst;
input wire clk;
input wire VAR9;
output reg VAR8;
reg [7:0] VAR2;
parameter VAR5 = 3'b000,
VAR1 = 3'b001,
VAR6 = 3'b010,
VAR10 = 3'b011,
VAR7 = 3'b100;
reg [2:0] state, VAR4;
always @(posedge clk or posedge rst)
if (rst) state <= VAR5;
else state <= VAR4;
always @(... | bsd-3-clause |
ptracton/vscale_soc | rtl/uart16550-1.5.4/bench/verilog/wb_master_model.v | 28,419 | module MODULE1
(
VAR28 ,
VAR31 ,
VAR25 ,
VAR38 ,
VAR20 ,
VAR37 ,
VAR43 ,
VAR15 ,
VAR12 ,
VAR2 ,
VAR17 ,
VAR36 ,
VAR10 ,
VAR4
);
parameter VAR19 = 1 ;
parameter VAR11 = 1 ;
parameter VAR45 = 1 ;
real VAR39 ;
input VAR28 ,
VAR31 ;
output VAR25 ;
reg VAR25 ;
output [ 2: 0] VAR38 ;
reg [ 2: 0] VAR38 ;
output [ 1: 0] VAR20 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2111o/sky130_fd_sc_lp__a2111o.behavioral.pp.v | 2,070 | module MODULE1 (
VAR2 ,
VAR14 ,
VAR4 ,
VAR1 ,
VAR17 ,
VAR18 ,
VAR16,
VAR11,
VAR15 ,
VAR3
);
output VAR2 ;
input VAR14 ;
input VAR4 ;
input VAR1 ;
input VAR17 ;
input VAR18 ;
input VAR16;
input VAR11;
input VAR15 ;
input VAR3 ;
wire VAR8 ;
wire VAR7 ;
wire VAR9;
and VAR13 (VAR8 , VAR14, VAR4 );
or VAR5 (VAR7 , VAR17, VA... | apache-2.0 |
onchipuis/mriscv_vivado | mriscv_vivado.srcs/sources_1/ip/ddr_axi/ddr_axi/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_reg.v | 6,113 | module MODULE1 #
(
parameter integer VAR6 = 32,
parameter integer VAR7 = 32,
parameter VAR10 = 32'h0,
parameter VAR5 = 32'h1
)
(
input wire clk ,
input wire reset ,
input wire [VAR6-1:0] VAR1 ,
input wire VAR12 ,
input wire VAR2 ,
input wire [VAR6-1:0] VAR11 ,
output wire [VAR7-1:0] VAR9
);
reg [VAR6-1:0] VAR3;
always ... | mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/lsu_pipelined.v | 18,726 | module MODULE1
(
clk, reset, VAR42, VAR26, VAR21, VAR13, VAR36, VAR14, VAR25,
VAR59, VAR9, VAR31, VAR48, VAR56, VAR87,
VAR34,
VAR78,
VAR37
);
parameter VAR23=32; parameter VAR30=4; parameter VAR24=32; parameter VAR81=2; parameter VAR72=32; parameter VAR47=0;
parameter VAR8=6; parameter VAR12=1;
parameter VAR2=1;
parame... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a31o/sky130_fd_sc_hdll__a31o.symbol.v | 1,369 | module MODULE1 (
input VAR7,
input VAR8,
input VAR3,
input VAR6,
output VAR4
);
supply1 VAR1;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | rtl/mkOCApp4B_scenario4.v | 50,709 | module MODULE1(VAR354,
VAR363,
VAR103,
VAR235,
VAR156,
VAR71,
VAR119,
VAR118,
VAR200,
VAR56,
VAR226,
VAR148,
VAR262,
VAR215,
VAR194,
VAR181,
VAR125,
VAR290,
VAR373,
VAR149,
VAR139,
VAR283,
VAR301,
VAR116,
VAR64,
VAR122,
VAR111,
VAR282,
VAR337,
VAR343,
VAR320,
VAR280,
VAR347,
VAR386,
VAR195,
VAR232,
VAR164,
VAR252,
VAR1... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o221a/sky130_fd_sc_hs__o221a.behavioral.pp.v | 2,100 | module MODULE1 (
VAR13,
VAR5,
VAR14 ,
VAR10 ,
VAR15 ,
VAR1 ,
VAR8 ,
VAR3
);
input VAR13;
input VAR5;
output VAR14 ;
input VAR10 ;
input VAR15 ;
input VAR1 ;
input VAR8 ;
input VAR3 ;
wire VAR8 VAR6 ;
wire VAR8 VAR16 ;
wire VAR12 ;
wire VAR2;
or VAR9 (VAR6 , VAR8, VAR1 );
or VAR7 (VAR16 , VAR15, VAR10 );
and VAR18 (VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor2b/sky130_fd_sc_lp__nor2b.symbol.v | 1,326 | module MODULE1 (
input VAR7 ,
input VAR5,
output VAR6
);
supply1 VAR4;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_1.v | 2,615 | module MODULE1 (
VAR12 ,
VAR8 ,
VAR2 ,
VAR10 ,
VAR11 ,
VAR9 ,
VAR5,
VAR4 ,
VAR6 ,
VAR13 ,
VAR1
);
output VAR12 ;
output VAR8 ;
input VAR2 ;
input VAR10 ;
input VAR11 ;
input VAR9 ;
input VAR5;
input VAR4 ;
input VAR6 ;
input VAR13 ;
input VAR1 ;
VAR7 VAR3 (
.VAR12(VAR12),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR11... | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/debug/sirv_jtag_dtm.v | 16,208 | module MODULE1 (
VAR28,
VAR15,
VAR59,
VAR16,
VAR67,
VAR41,
VAR52,
VAR5,
VAR86,
VAR77,
VAR21,
VAR40
);
parameter VAR34 = 2;
parameter VAR38 = 34;
parameter VAR61 = 5; parameter VAR42 = 2;
parameter VAR66 = 4'h1;
parameter VAR68 = 3'h5;
localparam VAR87 = 5;
localparam VAR73 = 0;
localparam VAR31 = 4'h0;
localparam VAR51... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or4b/sky130_fd_sc_hd__or4b.blackbox.v | 1,316 | module MODULE1 (
VAR9 ,
VAR6 ,
VAR4 ,
VAR3 ,
VAR8
);
output VAR9 ;
input VAR6 ;
input VAR4 ;
input VAR3 ;
input VAR8;
supply1 VAR5;
supply0 VAR1;
supply1 VAR7 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
jas0n1ee/THU-DSD | FB/jtag_uart.v | 22,069 | module MODULE7 (
clk,
VAR3,
VAR28,
valid
)
;
input clk;
input [ 7: 0] VAR3;
input VAR28;
input valid;
reg [31:0] VAR50; VAR77 VAR50 =
always @(posedge clk) begin
if (valid && VAR28) begin
("%VAR15", ((VAR3 == 8'hd) ? 8'ha : VAR3));
VAR38 (VAR50);
end
end
endmodule
module MODULE5 (
clk,
VAR9,
VAR42,
VAR58,
VAR66,
VAR56,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/buf/sky130_fd_sc_hd__buf.functional.pp.v | 1,746 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR3,
VAR7,
VAR9 ,
VAR4
);
output VAR1 ;
input VAR5 ;
input VAR3;
input VAR7;
input VAR9 ;
input VAR4 ;
wire VAR12 ;
wire VAR2;
buf VAR6 (VAR12 , VAR5 );
VAR11 VAR10 (VAR2, VAR12, VAR3, VAR7);
buf VAR8 (VAR1 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand2b/sky130_fd_sc_hd__nand2b.pp.symbol.v | 1,296 | module MODULE1 (
input VAR1 ,
input VAR4 ,
output VAR3 ,
input VAR6 ,
input VAR7,
input VAR2,
input VAR5
);
endmodule | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/rw_manager_inst_ROM_no_ifdef_params.v | 2,953 | module MODULE1 (
VAR15,
VAR48,
VAR6,
VAR46,
VAR20,
VAR14);
parameter VAR38 = "VAR21.VAR30";
input VAR15;
input [19:0] VAR48;
input [6:0] VAR6;
input [6:0] VAR46;
input VAR20;
output [19:0] VAR14;
tri1 VAR15;
tri0 VAR20;
wire [19:0] VAR58;
wire [19:0] VAR14 = VAR58[19:0];
VAR17 VAR1 (
.VAR19 (VAR15),
.VAR36 (VAR6),
.VAR... | gpl-3.0 |
deepakcu/digital_design | flops/flop_sync_rst.v | 1,588 | module MODULE1(
input clk,
input rst,
input din,
output reg VAR1
);
always@(posedge clk)
if(rst)
VAR1 <= 0;
else
VAR1 <= din;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/or3/sky130_fd_sc_hvl__or3.symbol.v | 1,272 | module MODULE1 (
input VAR2,
input VAR8,
input VAR5,
output VAR7
);
supply1 VAR4;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_32.v | 22,998 | module MODULE2 (
clk,
reset,
VAR63,
VAR75,
VAR156,
VAR119,
VAR185
);
parameter VAR93 = 18;
parameter VAR29 = 32;
parameter VAR146 = 16;
localparam VAR138 = 38;
input clk;
input reset;
input VAR63;
input VAR75;
input [VAR93-1:0] VAR156; output VAR119;
output [VAR93-1:0] VAR185;
localparam VAR25 = 18; localparam VAR123 =... | mit |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/iface/ip/mem_splitter/acl_iface_address_to_bankaddress.v | 1,954 | module MODULE1 #(
parameter integer VAR4 = 32, parameter integer VAR5 = 2, parameter integer VAR8 = VAR4-VAR3(VAR5)
)
(
input logic [VAR4-1:0] address,
output logic [VAR5-1:0] VAR7, output logic [VAR3(VAR5)-1:0] VAR1, output logic [VAR4-VAR3(VAR5)-1:0] VAR2
);
integer VAR9;
logic [VAR4:0] VAR6;
assign VAR6 = {1'b0,addr... | mit |
sh-chris110/chris | FPGA/chris.system.dma.ok/Qsys/soc_design/synthesis/submodules/soc_design_SystemID.v | 2,203 | module MODULE1 (
address,
VAR3,
VAR2,
VAR1
)
;
output [ 31: 0] VAR1;
input address;
input VAR3;
input VAR2;
wire [ 31: 0] VAR1;
assign VAR1 = address ? 1500519446 : 255;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21o/sky130_fd_sc_hdll__a21o.behavioral.v | 1,510 | module MODULE1 (
VAR8 ,
VAR11,
VAR6,
VAR1
);
output VAR8 ;
input VAR11;
input VAR6;
input VAR1;
supply1 VAR5;
supply0 VAR4;
supply1 VAR13 ;
supply0 VAR7 ;
wire VAR9 ;
wire VAR10;
and VAR2 (VAR9 , VAR11, VAR6 );
or VAR3 (VAR10, VAR9, VAR1 );
buf VAR12 (VAR8 , VAR10 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2bb2a/sky130_fd_sc_ms__o2bb2a.behavioral.pp.v | 2,171 | module MODULE1 (
VAR11 ,
VAR9,
VAR16,
VAR7 ,
VAR2 ,
VAR18,
VAR4,
VAR1 ,
VAR6
);
output VAR11 ;
input VAR9;
input VAR16;
input VAR7 ;
input VAR2 ;
input VAR18;
input VAR4;
input VAR1 ;
input VAR6 ;
wire VAR5 ;
wire VAR10 ;
wire VAR17 ;
wire VAR13;
nand VAR8 (VAR5 , VAR16, VAR9 );
or VAR14 (VAR10 , VAR2, VAR7 );
and VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o311ai/sky130_fd_sc_lp__o311ai_m.v | 2,432 | module MODULE1 (
VAR10 ,
VAR11 ,
VAR3 ,
VAR8 ,
VAR1 ,
VAR9 ,
VAR7,
VAR4,
VAR12 ,
VAR2
);
output VAR10 ;
input VAR11 ;
input VAR3 ;
input VAR8 ;
input VAR1 ;
input VAR9 ;
input VAR7;
input VAR4;
input VAR12 ;
input VAR2 ;
VAR6 VAR5 (
.VAR10(VAR10),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR7... | apache-2.0 |
f3zz3h/Embedded-Co-Design | ts7300_top_restored/ts7300_top.v | 24,078 | module MODULE1(
VAR35,
VAR1,
VAR100,
VAR151,
VAR136,
VAR6,
VAR88,
VAR23,
VAR138,
VAR5,
VAR7,
VAR141,
VAR149,
VAR105,
VAR21,
VAR52,
VAR130,
VAR71,
VAR72,
VAR49,
VAR31,
VAR101,
VAR53,
VAR47,
VAR68,
VAR2,
VAR34,
VAR157,
VAR41,
VAR91,
VAR133,
VAR57,
VAR125,
VAR119,
VAR40,
VAR69,
VAR93,
VAR39,
VAR60,
VAR90,
VAR118,
VAR124,
... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_1.behavioral.pp.v | 3,372 | module MODULE1( VAR9, VAR2, VAR3, VAR11, VAR5, VAR1, VAR8, VAR7 );
input VAR1, VAR5, VAR2, VAR9, VAR3;
inout VAR8, VAR7;
output VAR11;
VAR4 VAR6(.VAR9(VAR9),.VAR2(VAR2),.VAR3(VAR3),.VAR11(VAR11),.VAR5(VAR5),.VAR1(VAR1),.VAR8(VAR8),.VAR7(VAR7));
VAR4 VAR10(.VAR9(VAR9),.VAR2(VAR2),.VAR3(VAR3),.VAR11(VAR11),.VAR5(VAR5),.V... | apache-2.0 |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/proj_pointer_basic_hls_ip_integ/proj_pointer_basic_hls_ip_integ.cache/ip/2018.2/5aea95b49c8de87e/design_1_rst_ps7_0_50M_0_stub.v | 1,873 | module MODULE1(VAR8, VAR5, VAR6,
VAR2, VAR9, VAR10, VAR3, VAR7,
VAR4, VAR1)
;
input VAR8;
input VAR5;
input VAR6;
input VAR2;
input VAR9;
output VAR10;
output [0:0]VAR3;
output [0:0]VAR7;
output [0:0]VAR4;
output [0:0]VAR1;
endmodule | mit |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_3/hdl/verilog/feedforward_dadd_64ns_64ns_64_5_full_dsp.v | 1,936 | module MODULE1
VAR15 = 6,
VAR21 = 5,
VAR25 = 64,
VAR11 = 64,
VAR27 = 64
)(
input wire clk,
input wire reset,
input wire VAR22,
input wire [VAR25-1:0] VAR26,
input wire [VAR11-1:0] VAR10,
output wire [VAR27-1:0] dout
);
wire VAR19;
wire VAR6;
wire VAR8;
wire [63:0] VAR1;
wire VAR5;
wire [63:0] VAR2;
wire VAR16;
wire [63... | gpl-3.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_056.v | 1,436 | module MODULE2 (
VAR1,
VAR11
);
input [31:0] VAR1;
output [31:0]
VAR11;
wire [31:0]
VAR9,
VAR5,
VAR2,
VAR12,
VAR4,
VAR10,
VAR6;
assign VAR9 = VAR1;
assign VAR2 = VAR5 - VAR9;
assign VAR5 = VAR9 << 4;
assign VAR6 = VAR10 - VAR4;
assign VAR10 = VAR2 << 11;
assign VAR4 = VAR12 - VAR9;
assign VAR12 = VAR2 << 2;
assign VAR1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2bb2o/sky130_fd_sc_lp__a2bb2o.behavioral.v | 1,705 | module MODULE1 (
VAR3 ,
VAR4,
VAR11,
VAR5 ,
VAR8
);
output VAR3 ;
input VAR4;
input VAR11;
input VAR5 ;
input VAR8 ;
supply1 VAR2;
supply0 VAR6;
supply1 VAR15 ;
supply0 VAR1 ;
wire VAR12 ;
wire VAR9 ;
wire VAR16;
and VAR13 (VAR12 , VAR5, VAR8 );
nor VAR7 (VAR9 , VAR4, VAR11 );
or VAR14 (VAR16, VAR9, VAR12);
buf VAR10 (... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_16.behavioral.pp.v | 1,074 | module MODULE1( VAR2, VAR3 );
inout VAR2, VAR3;
VAR1 VAR5(.VAR2(VAR2),.VAR3(VAR3));
VAR1 VAR4(.VAR2(VAR2),.VAR3(VAR3)); | apache-2.0 |
lfmunoz/vhdl | ip_blocks/axi_to_stellarip/vivado_prj/vivado_prj.srcs/sources_1/ip/axi_traffic_gen_0/axi_traffic_gen_v2_0/hdl/src/verilog/axi_traffic_gen_v2_0_ex_fifo.v | 7,372 | module MODULE1
parameter VAR8 = 10,
parameter VAR41 = 8 ,
parameter VAR26 = 3 ,
parameter VAR14 = 1 ,
parameter VAR3 = 0 ,
parameter VAR21 = 6 ,
parameter VAR37 = 0 ) (
input VAR7 ,
input VAR1 ,
input [VAR8-1:0] VAR12 ,
input VAR30 ,
input VAR34 ,
output [VAR8-1:0] VAR40 ,
output VAR24 ,
output VAR39 ,
output VAR33 ,
o... | mit |
drichmond/riffa | fpga/altera/de4/riffa_wrapper_de4.v | 37,115 | module MODULE1
parameter VAR133 = 128,
parameter VAR89 = 256,
parameter VAR327 = 5,
parameter VAR300 = "VAR280")
( input [VAR133-1:0] VAR107,
input [0:0] VAR137,
input [0:0] VAR87,
input [0:0] VAR62,
output VAR88,
input [0:0] VAR148,
output [VAR133-1:0] VAR312,
output [0:0] VAR123,
input VAR182,
output [0:0] VAR267,
ou... | bsd-3-clause |
Jam-G/MIPS | Pipeline.v | 5,433 | module MODULE1(
input clk,
output [31:0] VAR11,
output [5:0] VAR13,
output [4:0] VAR86,
output [4:0] VAR12,
output [4:0] VAR101,
output [4:0] VAR83,
output [5:0] VAR105,
output [31:0] VAR43,
output [5:0] VAR91,
output [2:0] VAR98,
output VAR103,
output VAR51,
output VAR61,
output VAR15,
output VAR100,
output [1:0] VAR9... | lgpl-3.0 |
aquaxis/FPGAMAG18 | modules/cache_v1/src/fmrv32im_cache_intelmem.v | 2,620 | module MODULE1
parameter VAR49 = ""
)
(
input [9:0] VAR46,
input [9:0] VAR25,
input [3:0] VAR7,
input VAR28,
input VAR41,
input [31:0] VAR14,
input [31:0] VAR19,
input VAR47,
input VAR9,
output [31:0] VAR10,
output [31:0] VAR38
);
VAR40 VAR11 (
.VAR46 (VAR46),
.VAR25 (VAR25),
.VAR7 (VAR7),
.VAR44 (VAR28),
.VAR35 (VAR41... | mit |
LSaldyt/qnp | output/vs/var16_multi.v | 1,321 | module MODULE1 (VAR5, VAR3, VAR12, VAR15, VAR17, VAR11, VAR8, VAR18, VAR19, VAR16, VAR9, VAR13, VAR1, VAR6, VAR22, VAR14, valid);
input VAR5, VAR3, VAR12, VAR15, VAR17, VAR11, VAR8, VAR18, VAR19, VAR16, VAR9, VAR13, VAR1, VAR6, VAR22, VAR14;
output valid;
wire [7:0] VAR2 = 8'd120;
wire [7:0] VAR7 = 8'd60;
wire [7:0] VA... | mit |
jakobwenzel/artnet-avr | fpga/top.v | 3,474 | module MODULE1(input VAR20, input VAR45, output VAR28, output VAR39);
parameter VAR12 = 170;
wire VAR14;
reg reset = 1;
always @(posedge VAR14) begin
reset <= 0;
end
reg VAR36 = 0;
wire VAR35,VAR9;
reg[12:0] VAR23=0;
wire read;
wire write ;
wire VAR10, VAR11;
reg VAR5 = 0;
VAR37 VAR41(
.VAR40(VAR45),
.VAR1(VAR20),
.VAR... | gpl-3.0 |
ncos/Xilinx-Verilog | INTERFACES/src/CAN/can_controller_tesbench.v | 1,604 | module MODULE1();
reg VAR7;
reg VAR11;
wire VAR3;
reg [107:0] VAR13;
wire [107:0] VAR1;
reg VAR2;
wire VAR6;
wire VAR5;
reg [107:0] VAR4;
wire [107:0] VAR10;
reg VAR8;
wire VAR9;
wire VAR12;
pullup(VAR3);
always
VAR7 = ~VAR7;
begin | mit |
liqimai/ZPC | PersonalComputer/vag.v | 2,918 | module MODULE1(
input clk, input VAR1, input[15:0] VAR9,
output valid, output[9:0] VAR20,output[9:0] VAR16,
output VAR10, output VAR8, output VAR3,
output VAR6,
output VAR21
);
reg[10:0] VAR2; reg[9:0] VAR5; VAR12 begin
VAR2 <= 0;
VAR5 <= 0;
end
always @ (posedge clk or negedge VAR1)
if(!VAR1) VAR2 <= 11'd0;
else if(VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a32o/sky130_fd_sc_hs__a32o.behavioral.v | 2,118 | module MODULE1 (
VAR3 ,
VAR17 ,
VAR11 ,
VAR9 ,
VAR12 ,
VAR2 ,
VAR6,
VAR15
);
output VAR3 ;
input VAR17 ;
input VAR11 ;
input VAR9 ;
input VAR12 ;
input VAR2 ;
input VAR6;
input VAR15;
wire VAR12 VAR7 ;
wire VAR12 VAR14 ;
wire VAR18 ;
wire VAR16;
and VAR4 (VAR7 , VAR9, VAR17, VAR11 );
and VAR1 (VAR14 , VAR12, VAR2 );
or... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_16/bsg_mem/bsg_mem_1rw_sync.v | 4,795 | if (VAR39 == VAR38 && VAR14 == VAR15) \
begin: VAR37 \
VAR19 VAR6 \
(.VAR13 (VAR2 ) \
,.VAR47 (VAR18) ,.VAR46 (~VAR23 ) ,.VAR1 (~VAR43 ) ,.VAR5 (VAR41) ,.VAR44 (VAR28) ,.VAR4 (1'd0 ) ,.VAR3 (3'd3 ) ,.VAR7 (2'd1 ) ,.VAR45 (1'd0 ) ,.VAR16 (1'b1 ) ); \
end
if (VAR39 == VAR38 && VAR14 == VAR15) \
begin: VAR37 \
VAR9 VAR6 \... | bsd-3-clause |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/radio_controller_v1_07_a/hdl/verilog/spi_top.v | 6,557 | module MODULE1
(
VAR19, VAR32,
VAR46, VAR48, VAR39, VAR43, VAR21, VAR49, VAR5,
VAR6, VAR45, VAR7
);
parameter VAR22 = 1;
input VAR19; input VAR32;
input [13:0] VAR46;
input [7:0] VAR48;
input VAR39;
input [17:0] VAR43;
input VAR21;
input VAR49;
output VAR5;
output [VAR47-1:0] VAR6; output VAR45; output VAR7;
wire [VAR1... | bsd-2-clause |
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