repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
polysome/hydra | implementation/hydra_wrapper_v2.v | 25,383 | module MODULE1(VAR26, VAR33,
VAR49, VAR22, VAR38, VAR82, VAR107, VAR32, VAR4, VAR3, VAR7, VAR81, VAR28, VAR91, VAR53,
VAR80, VAR1, VAR74, VAR89, VAR11, VAR58, VAR106, VAR96, VAR20, VAR24, interrupt,
VAR102 ,
VAR18
);
input VAR26;
input VAR33;
input VAR102;
input VAR49;
input [1:0] VAR22;
input [31:0] VAR38;
input VAR82... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlymetal6s6s/sky130_fd_sc_ms__dlymetal6s6s.pp.symbol.v | 1,358 | module MODULE1 (
input VAR3 ,
output VAR6 ,
input VAR2 ,
input VAR1,
input VAR4,
input VAR5
);
endmodule | apache-2.0 |
ShirmanXia/EE469SPRING16 | lab4/nios_system/synthesis/submodules/nios_system_nios2_qsys_0_cpu_debug_slave_tck.v | 8,393 | module MODULE1 (
VAR16,
VAR12,
VAR4,
VAR6,
VAR5,
VAR30,
VAR15,
VAR18,
VAR37,
VAR40,
VAR36,
VAR7,
VAR2,
VAR34,
VAR27,
VAR25,
VAR33,
VAR9,
VAR17,
VAR39,
VAR14,
VAR20,
VAR11,
VAR31,
VAR21,
VAR3,
VAR13,
VAR26,
VAR32,
VAR22,
VAR28
)
;
output [ 1: 0] VAR13;
output VAR26;
output [ 37: 0] VAR32;
output VAR22;
output VAR28;
inp... | gpl-3.0 |
tmatsuya/milkymist-ml401 | cores/lm32/rtl/spiprog.v | 6,605 | module MODULE1 (input VAR26 ,
input VAR3 ,
output VAR24 ,
input VAR23 ,
input VAR8 ,
input VAR32 ,
input VAR11 ,
input VAR7 ,
input VAR29 ,
output VAR37 ,
output VAR16 ,
output VAR39 ,
input VAR17);
wire VAR15 ;
wire VAR25;
wire VAR20;
wire VAR9 ;
wire VAR40;
wire VAR12;
wire [7:0] VAR10 ;
wire [8:0] VAR33 ;
wire [8:0]... | lgpl-3.0 |
theapi/de0-nano | neopixels/neopixels.v | 4,613 | module MODULE1(
input VAR8,
input [1:0] VAR13,
output VAR7
);
reg VAR3;
reg [3:0] VAR2;
reg [3:0] VAR12 = 4'b0;
reg [7:0] VAR14 = 7'b0;
reg [7:0] VAR11 = 7'd40; reg VAR4 = 1'b0;
reg VAR10 = 1'b0;
reg [32:0] counter = 32'b0;
reg VAR1 = 1'b0;
reg [7:0] VAR5 = 8'b0;
reg [1:0] VAR6 = 2'b00;
reg VAR9 = 1'b1;
assign VAR7 = V... | mit |
dk00/old-stuff | csie/09computer-architecture/project/code/dcache_top.v | 7,416 | module MODULE1
(
VAR11,
VAR8,
VAR50,
VAR16,
VAR4,
VAR24,
VAR28,
VAR33,
VAR31,
VAR6,
VAR18,
VAR39,
VAR34,
VAR1
);
input VAR11;
input VAR8;
input [256-1:0] VAR50;
input VAR16;
output [256-1:0] VAR4;
output [32-1:0] VAR24;
output VAR28;
output VAR33;
input [32-1:0] VAR31;
input [32-1:0] VAR6;
input VAR18;
input VAR39;
out... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4bb/sky130_fd_sc_lp__nor4bb_m.v | 2,322 | module MODULE2 (
VAR2 ,
VAR7 ,
VAR10 ,
VAR11 ,
VAR4 ,
VAR3,
VAR8,
VAR5 ,
VAR1
);
output VAR2 ;
input VAR7 ;
input VAR10 ;
input VAR11 ;
input VAR4 ;
input VAR3;
input VAR8;
input VAR5 ;
input VAR1 ;
VAR6 VAR9 (
.VAR2(VAR2),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR5(VAR5),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sedfxbp/sky130_fd_sc_ls__sedfxbp.pp.symbol.v | 1,518 | module MODULE1 (
input VAR6 ,
output VAR1 ,
output VAR8 ,
input VAR10 ,
input VAR2 ,
input VAR3 ,
input VAR4 ,
input VAR7 ,
input VAR11,
input VAR5,
input VAR9
);
endmodule | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/core/e203_exu_alu_lsuagu.v | 29,774 | module MODULE1(
input VAR53, output VAR100,
input [VAR50-1:0] VAR54,
input [VAR50-1:0] VAR52,
input [VAR50-1:0] VAR113,
input [VAR94-1:0] VAR133,
input [VAR61-1:0] VAR136,
output VAR60,
input VAR167,
input VAR92,
output VAR128,
input VAR140,
output VAR76, input VAR83, output [VAR50-1:0] VAR27,
output VAR120,
output VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21oi/sky130_fd_sc_lp__a21oi_lp.v | 2,269 | module MODULE2 (
VAR8 ,
VAR5 ,
VAR7 ,
VAR2 ,
VAR1,
VAR4,
VAR10 ,
VAR6
);
output VAR8 ;
input VAR5 ;
input VAR7 ;
input VAR2 ;
input VAR1;
input VAR4;
input VAR10 ;
input VAR6 ;
VAR9 VAR3 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR6(VAR6)
);
endmodule
module MODULE... | apache-2.0 |
jfzazo/msix-7series | msix_manager.v | 14,913 | module MODULE1 #(
parameter VAR28 = 9,
parameter VAR26 = 32,
parameter VAR23 = 32,
parameter VAR21 = 32'h0,
parameter VAR9 = 32'h100,
parameter VAR48 = 1
)(
input wire clk,
input wire VAR30,
input wire [VAR28-1:0] VAR12,
input wire [VAR28-1:0] VAR80,
input wire [VAR26-1:0] VAR56,
output wire [VAR26-1:0] VAR25,
input wi... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_4.functional.v | 1,046 | module MODULE1( VAR3, VAR6, VAR8 );
input VAR3, VAR6;
output VAR8;
wire VAR7;
not VAR2( VAR7, VAR3 );
wire VAR4;
not VAR5( VAR4, VAR6 );
or VAR1( VAR8, VAR7, VAR4 );
endmodule | apache-2.0 |
spmohara/Interfacing-FPGA-with-LCD | interfacing_fpga_with_lcd.v | 3,194 | module MODULE1(clk, VAR12, VAR2, VAR9, VAR6, VAR10, VAR8, VAR5, VAR11);
parameter VAR7 = 15;
input clk;
output VAR12, VAR2, VAR9, VAR6, VAR10, VAR8, VAR5, VAR11;
reg VAR12, VAR2, VAR9, VAR6, VAR10, VAR8, VAR5, VAR11;
reg [VAR7+8-1:0] VAR13;
reg VAR1;
reg [5:0] VAR4;
reg VAR14;
reg [6:0] VAR3;
always @ (posedge clk)
beg... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and4bb/sky130_fd_sc_hdll__and4bb.behavioral.v | 1,520 | module MODULE1 (
VAR12 ,
VAR13,
VAR4,
VAR11 ,
VAR8
);
output VAR12 ;
input VAR13;
input VAR4;
input VAR11 ;
input VAR8 ;
supply1 VAR10;
supply0 VAR3;
supply1 VAR9 ;
supply0 VAR5 ;
wire VAR1 ;
wire VAR2;
nor VAR6 (VAR1 , VAR13, VAR4 );
and VAR7 (VAR2, VAR1, VAR11, VAR8 );
buf VAR14 (VAR12 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2.pp.symbol.v | 1,324 | module MODULE1 (
input VAR1 ,
output VAR2 ,
input VAR4,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sedfxtp/sky130_fd_sc_hd__sedfxtp.pp.symbol.v | 1,493 | module MODULE1 (
input VAR9 ,
output VAR7 ,
input VAR8 ,
input VAR6 ,
input VAR5 ,
input VAR4 ,
input VAR10 ,
input VAR2,
input VAR3,
input VAR1
);
endmodule | apache-2.0 |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/cpu/k580wm80a.v | 10,791 | module MODULE1(
input clk,
input VAR32,
input reset,
input VAR50,
input [7:0] VAR31,
output reg [15:0] addr,
output reg sync,
output rd,
output reg VAR38,
output VAR48,
output reg [7:0] VAR20,
output VAR18);
reg VAR87,VAR75,VAR68,VAR23,VAR21,VAR60,VAR49,VAR14,VAR73,VAR85,VAR15,VAR44,VAR17,VAR82,VAR78,VAR79,VAR22,VAR67;... | gpl-3.0 |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/Pmods/PmodAMP2_v1_0/ipshared/digilentinc.com/pwm_v1_0/hdl/PWM_v1_0.v | 3,289 | module MODULE1 #
(
parameter integer VAR56 = 32,
parameter integer VAR14 = 4
)
(
output wire VAR52,
output wire interrupt,
input wire VAR40,
input wire VAR32,
input wire [VAR14-1 : 0] VAR43,
input wire [2 : 0] VAR35,
input wire VAR41,
output wire VAR29,
input wire [VAR56-1 : 0] VAR36,
input wire [(VAR56/8)-1 : 0] VAR55... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/einvp/sky130_fd_sc_lp__einvp_4.v | 2,130 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR4 ,
VAR6,
VAR3,
VAR9 ,
VAR8
);
output VAR5 ;
input VAR1 ;
input VAR4 ;
input VAR6;
input VAR3;
input VAR9 ;
input VAR8 ;
VAR2 VAR7 (
.VAR5(VAR5),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR5 ,
VAR1 ,
VAR4
);
output VAR5... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21bai/sky130_fd_sc_hs__o21bai.blackbox.v | 1,353 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR3 ,
VAR5
);
output VAR6 ;
input VAR4 ;
input VAR3 ;
input VAR5;
supply1 VAR1;
supply0 VAR2;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and2/sky130_fd_sc_ms__and2.symbol.v | 1,260 | module MODULE1 (
input VAR5,
input VAR2,
output VAR1
);
supply1 VAR3;
supply0 VAR7;
supply1 VAR4 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xor3/sky130_fd_sc_hdll__xor3.symbol.v | 1,317 | module MODULE1 (
input VAR6,
input VAR1,
input VAR2,
output VAR7
);
supply1 VAR4;
supply0 VAR8;
supply1 VAR3 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux2i/sky130_fd_sc_lp__mux2i.behavioral.v | 1,654 | module MODULE1 (
VAR7 ,
VAR8,
VAR6,
VAR9
);
output VAR7 ;
input VAR8;
input VAR6;
input VAR9 ;
supply1 VAR5;
supply0 VAR2;
supply1 VAR12 ;
supply0 VAR11 ;
wire VAR1;
VAR3 VAR4 (VAR1, VAR8, VAR6, VAR9 );
buf VAR10 (VAR7 , VAR1);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o221a/sky130_fd_sc_ls__o221a_2.v | 2,444 | module MODULE2 (
VAR12 ,
VAR9 ,
VAR6 ,
VAR10 ,
VAR11 ,
VAR8 ,
VAR7,
VAR5,
VAR4 ,
VAR2
);
output VAR12 ;
input VAR9 ;
input VAR6 ;
input VAR10 ;
input VAR11 ;
input VAR8 ;
input VAR7;
input VAR5;
input VAR4 ;
input VAR2 ;
VAR3 VAR1 (
.VAR12(VAR12),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR8(VAR8),
.VA... | apache-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_NVMeHostController_0_0/src/pcie_7x_0_core_top/source/pcie_7x_0_core_top_gtp_pipe_reset.v | 20,013 | module MODULE1 #
(
parameter VAR38 = "VAR37", parameter VAR10 = 1, parameter VAR20 = 6'd63, parameter VAR31 = 1
)
(
input VAR12,
input VAR66,
input VAR72,
input VAR70,
input [VAR10-1:0] VAR30,
input [VAR10-1:0] VAR17,
input VAR42,
input [VAR10-1:0] VAR27,
input [VAR10-1:0] VAR33,
input VAR53,
input [VAR10-1:0] VAR13,
i... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_2.behavioral.pp.v | 1,328 | module MODULE1( VAR1, VAR4, VAR6, VAR8, VAR3, VAR9 );
input VAR8, VAR6, VAR4;
inout VAR3, VAR9;
output VAR1;
VAR2 VAR5(.VAR1(VAR1),.VAR4(VAR4),.VAR6(VAR6),.VAR8(VAR8),.VAR3(VAR3),.VAR9(VAR9));
VAR2 VAR7(.VAR1(VAR1),.VAR4(VAR4),.VAR6(VAR6),.VAR8(VAR8),.VAR3(VAR3),.VAR9(VAR9)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21bo/sky130_fd_sc_ls__a21bo.functional.v | 1,483 | module MODULE1 (
VAR7 ,
VAR6 ,
VAR5 ,
VAR4
);
output VAR7 ;
input VAR6 ;
input VAR5 ;
input VAR4;
wire VAR9 ;
wire VAR2;
nand VAR3 (VAR9 , VAR5, VAR6 );
nand VAR1 (VAR2, VAR4, VAR9);
buf VAR8 (VAR7 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o22ai/sky130_fd_sc_ls__o22ai_2.v | 2,352 | module MODULE2 (
VAR4 ,
VAR7 ,
VAR2 ,
VAR10 ,
VAR8 ,
VAR5,
VAR6,
VAR11 ,
VAR3
);
output VAR4 ;
input VAR7 ;
input VAR2 ;
input VAR10 ;
input VAR8 ;
input VAR5;
input VAR6;
input VAR11 ;
input VAR3 ;
VAR1 VAR9 (
.VAR4(VAR4),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR11(VAR11),
.... | apache-2.0 |
sh-chris110/chris | FPGA/chris.system_ok/Qsys/soc_design/synthesis/submodules/altera_reset_controller.v | 12,023 | module MODULE1
parameter VAR14 = 6,
parameter VAR30 = 0,
parameter VAR45 = 0,
parameter VAR55 = 0,
parameter VAR20 = 0,
parameter VAR17 = 0,
parameter VAR44 = 0,
parameter VAR72 = 0,
parameter VAR53 = 0,
parameter VAR75 = 0,
parameter VAR23 = 0,
parameter VAR67 = 0,
parameter VAR40 = 0,
parameter VAR2 = 0,
parameter VA... | gpl-2.0 |
tmatsuya/milkymist-ml401 | cores/vgafb/rtl/vgafb_graycounter.v | 1,185 | module MODULE1
(output reg [VAR1-1:0] VAR4,
input wire VAR6, input wire VAR5,
input wire VAR3);
reg [VAR1-1:0] VAR2;
always @ (posedge VAR3)
if (VAR5) begin
VAR2 <= {VAR1{1'VAR7 0}} + 1; VAR4 <= {VAR1{1'VAR7 0}}; end
else if (VAR6) begin
VAR2 <= VAR2 + 1;
VAR4 <= {VAR2[VAR1-1],
VAR2[VAR1-2:0] ^ VAR2[VAR1-1:1]};
end
end... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21ba/sky130_fd_sc_hd__o21ba_4.v | 2,316 | module MODULE2 (
VAR2 ,
VAR7 ,
VAR8 ,
VAR9,
VAR1,
VAR3,
VAR6 ,
VAR10
);
output VAR2 ;
input VAR7 ;
input VAR8 ;
input VAR9;
input VAR1;
input VAR3;
input VAR6 ;
input VAR10 ;
VAR5 VAR4 (
.VAR2(VAR2),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR10(VAR10)
);
endmodule
module MODULE2 ... | apache-2.0 |
maijohnson/comp3601_blue_15s2 | AudioController/tone_lut16.v | 3,044 | module MODULE1 (input [5:0] VAR40, output [15:0] VAR21);
parameter
VAR17 = 16'd47779,
VAR30 = 16'd45097,
VAR44 = 16'd42566,
VAR8 = 16'd40177,
VAR13 = 16'd37922,
VAR22 = 16'd35794,
VAR23 = 16'd33784,
VAR9 = 16'd31888,
VAR11 = 16'd30099,
VAR45 = 16'd28409,
VAR37 = 16'd26815,
VAR25 = 16'd25310,
VAR19 = 16'd23889,
VAR46 = ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrtp/sky130_fd_sc_lp__sdfrtp.symbol.v | 1,510 | module MODULE1 (
input VAR6 ,
output VAR7 ,
input VAR8,
input VAR2 ,
input VAR5 ,
input VAR10
);
supply1 VAR9;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
cafe-alpha/wasca | v12/fpga_firmware/wasca/synthesis/submodules/altera_up_clock_edge.v | 4,630 | module MODULE1 (
clk,
reset,
VAR6,
VAR4,
VAR1
);
input clk;
input reset;
input VAR6;
output VAR4;
output VAR1;
wire VAR2;
reg VAR5;
reg VAR3;
always @(posedge clk)
VAR5 <= VAR6;
always @(posedge clk)
VAR3 <= VAR5;
assign VAR4 = VAR2 & VAR5;
assign VAR1 = VAR2 & VAR3;
assign VAR2 = VAR3 ^ VAR5;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2111a/sky130_fd_sc_ms__o2111a.pp.blackbox.v | 1,427 | module MODULE1 (
VAR7 ,
VAR10 ,
VAR8 ,
VAR3 ,
VAR9 ,
VAR1 ,
VAR5,
VAR4,
VAR2 ,
VAR6
);
output VAR7 ;
input VAR10 ;
input VAR8 ;
input VAR3 ;
input VAR9 ;
input VAR1 ;
input VAR5;
input VAR4;
input VAR2 ;
input VAR6 ;
endmodule | apache-2.0 |
fbalakirev/red-pitaya-notes | cores/gpio_delayed_trigger_v1_0/gpio_delayed_trigger.v | 2,422 | module MODULE1 #
(
parameter integer VAR20 = 8,
parameter integer VAR11 = 4,
parameter integer VAR5 = 4
)
(
input wire VAR8,
input wire VAR26,
inout wire [VAR20-1:0] VAR29,
input wire [VAR5-1:0] VAR12,
input wire VAR22,
input wire [31:0] delay,
output wire VAR3,
output wire VAR4,
output wire VAR27
);
reg [VAR20-1:0] VA... | mit |
zeldin/iceGDROM | fpga/source/vexriscv/peripherals.v | 4,275 | module MODULE1 (
input clk,
input VAR8,
output reg[31:0] VAR6,
input wire[31:0] VAR38,
input wire[5:0] addr,
input VAR34,
input VAR36,
input[3:0] VAR2,
inout[7:0] VAR4,
inout[7:0] VAR18,
input VAR27,
input VAR25,
output VAR1,
input VAR20,
output wire VAR24,
output VAR33
);
wire [7:0] VAR31;
reg [7:0] VAR11;
reg [7:0] V... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/latsnq/gf180mcu_fd_sc_mcu9t5v0__latsnq_1.behavioral.pp.v | 2,990 | module MODULE1( VAR27, VAR6, VAR2, VAR1, VAR5, VAR22 );
input VAR6, VAR27, VAR2;
inout VAR5, VAR22;
output VAR1;
reg VAR10;
VAR21 VAR17(.VAR27(VAR27),.VAR6(VAR6),.VAR2(VAR2),.VAR1(VAR1),.VAR5(VAR5),.VAR22(VAR22),.VAR10(VAR10));
VAR21 VAR7(.VAR27(VAR27),.VAR6(VAR6),.VAR2(VAR2),.VAR1(VAR1),.VAR5(VAR5),.VAR22(VAR22),.VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdlclkp/sky130_fd_sc_hdll__sdlclkp.pp.blackbox.v | 1,315 | module MODULE1 (
VAR5,
VAR8 ,
VAR6,
VAR1 ,
VAR7,
VAR2,
VAR3 ,
VAR4
);
output VAR5;
input VAR8 ;
input VAR6;
input VAR1 ;
input VAR7;
input VAR2;
input VAR3 ;
input VAR4 ;
endmodule | apache-2.0 |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/eth_tri_mode/MAC_tx/flow_ctrl.v | 7,767 | module MODULE1
(
VAR21 ,
VAR18 ,
VAR16 ,
VAR3 ,
VAR15 ,
VAR10 ,
VAR13 ,
VAR23 ,
VAR5 ,
VAR12 ,
VAR11 ,
VAR6 ,
VAR2
);
input VAR21 ;
input VAR18 ;
input VAR16 ;
input VAR3 ;
input VAR15 ;
input [15:0] VAR10 ;
input VAR13 ;
output VAR23 ;
input VAR5 ;
output VAR12 ;
input VAR11 ;
output VAR6 ;
input VAR2 ;
reg VAR20 ;
re... | apache-2.0 |
alexforencich/xfcp | lib/eth/lib/axis/rtl/axis_mux.v | 9,643 | module MODULE1 #
(
parameter VAR45 = 4,
parameter VAR31 = 8,
parameter VAR37 = (VAR31>8),
parameter VAR44 = (VAR31/8),
parameter VAR15 = 0,
parameter VAR24 = 8,
parameter VAR26 = 0,
parameter VAR16 = 8,
parameter VAR10 = 1,
parameter VAR68 = 1
)
(
input wire clk,
input wire rst,
input wire [VAR45*VAR31-1:0] VAR52,
inpu... | mit |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/video_sys/submodules/video_sys_CPU_jtag_debug_module_sysclk.v | 6,854 | module MODULE1 (
clk,
VAR2,
VAR25,
VAR10,
VAR6,
VAR17,
VAR13,
VAR11,
VAR14,
VAR20,
VAR31,
VAR23,
VAR19,
VAR4,
VAR12,
VAR32,
VAR1,
VAR5,
VAR29
)
;
output [ 37: 0] VAR17;
output VAR13;
output VAR11;
output VAR14;
output VAR20;
output VAR31;
output VAR23;
output VAR19;
output VAR4;
output VAR12;
output VAR32;
output VAR1;... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand4b/sky130_fd_sc_ms__nand4b.behavioral.pp.v | 1,998 | module MODULE1 (
VAR14 ,
VAR2 ,
VAR3 ,
VAR16 ,
VAR13 ,
VAR9,
VAR15,
VAR17 ,
VAR5
);
output VAR14 ;
input VAR2 ;
input VAR3 ;
input VAR16 ;
input VAR13 ;
input VAR9;
input VAR15;
input VAR17 ;
input VAR5 ;
wire VAR8 ;
wire VAR11 ;
wire VAR1;
not VAR6 (VAR8 , VAR2 );
nand VAR10 (VAR11 , VAR13, VAR16, VAR3, VAR8 );
VAR7 V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand3b/sky130_fd_sc_ms__nand3b.functional.v | 1,401 | module MODULE1 (
VAR7 ,
VAR1,
VAR8 ,
VAR9
);
output VAR7 ;
input VAR1;
input VAR8 ;
input VAR9 ;
wire VAR3 ;
wire VAR2;
not VAR6 (VAR3 , VAR1 );
nand VAR4 (VAR2, VAR8, VAR3, VAR9 );
buf VAR5 (VAR7 , VAR2 );
endmodule | apache-2.0 |
tmolteno/TART | hardware/FPGA/ddrmem/scheduler.v | 12,190 | module MODULE1 (
VAR31,
VAR8,
VAR43,
VAR20,
VAR17,
VAR13,
VAR26,
VAR29,
VAR42,
VAR23,
VAR36,
VAR22,
VAR44,
VAR21, VAR39, VAR7,
VAR33,
VAR38,
VAR34, VAR6,
VAR1,
VAR9, VAR37,
VAR32
);
input VAR31;
input VAR8;
input VAR43;
input VAR20; input VAR17;
input VAR13;
output VAR26;
input [22:0] VAR29;
input VAR42; output VAR23;
... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busreceiver/sky130_fd_sc_lp__busreceiver_m.v | 2,083 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR2,
VAR8,
VAR5 ,
VAR3
);
output VAR1 ;
input VAR4 ;
input VAR2;
input VAR8;
input VAR5 ;
input VAR3 ;
VAR7 VAR6 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR1,
VAR4
);
output VAR1;
input VAR4;
supply1 VAR2;
supply0 VAR8;... | apache-2.0 |
lvd2/zxevo | fpga/baseconf/trunk/vg93/fapch_zek.v | 1,845 | module MODULE1
(
input wire VAR6,
input wire VAR4,
output reg VAR11,
output reg VAR9
);
reg [3:0] VAR3;
reg VAR1;
reg VAR5;
always @ (posedge VAR6)
begin
VAR5 <= VAR4;
VAR3 <= { VAR3[2:0], VAR5 };
if (VAR3 == 4'hF || VAR3 == 4'h0)
VAR1 <= VAR3[3];
end
reg [4:0] VAR10;
always @ (posedge VAR6)
begin
VAR10 <= { VAR10[3:0]... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrbn/sky130_fd_sc_lp__dlrbn.pp.blackbox.v | 1,436 | module MODULE1 (
VAR7 ,
VAR3 ,
VAR9,
VAR8 ,
VAR4 ,
VAR1 ,
VAR5 ,
VAR2 ,
VAR6
);
output VAR7 ;
output VAR3 ;
input VAR9;
input VAR8 ;
input VAR4 ;
input VAR1 ;
input VAR5 ;
input VAR2 ;
input VAR6 ;
endmodule | apache-2.0 |
huhydro/chriskyElbertV2FPGA | freqdiv.v | 1,134 | module MODULE1(
input clk,
input VAR4,
output VAR1,
input [1:0] select
);
reg [23:0]counter;
reg VAR2;
reg [23:0]VAR3;
assign VAR1=VAR2;
always@(posedge clk or negedge VAR4)
begin
if(~VAR4) begin
counter<=24'd0;
VAR2<=1'b0;
end
else
begin
case(select)
2'b0:
begin
VAR3 <= 24'd5;
end
2'b1:
begin
VAR3 <= 24'd5999999;
end
... | gpl-2.0 |
cynngah/virtualsynthesizer | synthkeyboard.v | 1,424 | module MODULE1(VAR5, VAR2, VAR1);
MODULE2(VAR4
endmodule
module MODULE2(VAR4, VAR3, VAR7);
input VAR4;
input VAR3;
output reg [3:0] VAR7;
reg [3:0] counter;
reg flag;
reg [7:0] VAR6; | mit |
camacazio/icestick_JSTK2_ORGB | source/RGB_color_set.v | 1,800 | module MODULE1(
input clk,
input [1:0] VAR1,
output [23:0] VAR3
);
reg [1:0] VAR4 = 2'd0;
reg [7:0] VAR5;
reg [7:0] VAR2;
reg [7:0] VAR6;
always @ (posedge VAR1[0])
begin
VAR4 <= VAR4+1;
end
always @ (posedge clk)
begin
if(VAR1[1]) begin
VAR5 <= 8'b01011111;
VAR2 <= 8'b01011111;
VAR6 <= 8'b01011111;
end
else if (VAR4 =... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_NVMeHostController_0_0/src/pcie_7x_0_core_top/source/pcie_7x_0_core_top_gt_rx_valid_filter_7x.v | 9,187 | module MODULE1 #(
parameter VAR29 = 28,
parameter VAR41 = 1
)
(
output [1:0] VAR25,
output [15:0] VAR45,
output VAR39,
output VAR16,
output [ 2:0] VAR5,
output VAR19,
input [1:0] VAR18,
input [15:0] VAR9,
input VAR1,
input VAR28,
input [ 2:0] VAR17,
input VAR15,
input VAR30,
input VAR4,
input VAR13,
input VAR26
);
loca... | gpl-3.0 |
csturton/wirepatch | system/hardware/cores/fabric/ovl_combo_wrapped.v | 3,819 | module MODULE1(
clk,
rst,
enable,
VAR1,
VAR13,
VAR3,
select,
VAR7,
out,
VAR4,
VAR8
);
parameter VAR2 = 7;
parameter VAR6 = 3;
input clk;
input rst;
input enable;
input [VAR6-1:0] VAR1;
input VAR13;
input VAR3;
input [1:0] select;
input VAR7;
output out;
output VAR4;
output VAR8;
reg VAR4;
wire [2:0] VAR5;
VAR11 VAR11 (... | mit |
red0bear/AES128 | rtl/shift_rows.v | 4,276 | module MODULE1
(
output [127 : 0] VAR14, output [127 : 0] VAR5, input [127 : 0] VAR10 );
localparam integer VAR9 = 128; localparam integer VAR4 = 8; localparam integer VAR19 = 4; localparam integer VAR2 = 4;
wire [VAR4 - 1 : 0] state[0 : VAR19 - 1][0 : VAR2 - 1];
wire [VAR4 - 1 : 0] VAR12[0 : VAR19 - 1][0 : VAR2 - 1];
... | lgpl-3.0 |
mrehkopf/sd2snes | verilog/sd2snes_obc1/address.v | 4,137 | module MODULE1(
input VAR20,
input [15:0] VAR24, input [2:0] VAR26, input [23:0] VAR16, input [7:0] VAR3, input VAR14, output [23:0] VAR23, output VAR4, output VAR6, output VAR15, output VAR11, input [23:0] VAR19,
input [23:0] VAR8,
output VAR17,
output VAR18,
output VAR12,
output VAR5,
output VAR22,
output VAR27,
outp... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or3b/sky130_fd_sc_lp__or3b_4.v | 2,209 | module MODULE2 (
VAR9 ,
VAR1 ,
VAR6 ,
VAR8 ,
VAR10,
VAR7,
VAR2 ,
VAR3
);
output VAR9 ;
input VAR1 ;
input VAR6 ;
input VAR8 ;
input VAR10;
input VAR7;
input VAR2 ;
input VAR3 ;
VAR4 VAR5 (
.VAR9(VAR9),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR3(VAR3)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21boi/sky130_fd_sc_ls__a21boi.pp.blackbox.v | 1,401 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR2 ,
VAR5,
VAR3,
VAR6,
VAR4 ,
VAR1
);
output VAR8 ;
input VAR7 ;
input VAR2 ;
input VAR5;
input VAR3;
input VAR6;
input VAR4 ;
input VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o21a/sky130_fd_sc_ms__o21a.functional.pp.v | 1,998 | module MODULE1 (
VAR8 ,
VAR6 ,
VAR15 ,
VAR10 ,
VAR2,
VAR7,
VAR12 ,
VAR3
);
output VAR8 ;
input VAR6 ;
input VAR15 ;
input VAR10 ;
input VAR2;
input VAR7;
input VAR12 ;
input VAR3 ;
wire VAR1 ;
wire VAR4 ;
wire VAR11;
or VAR13 (VAR1 , VAR15, VAR6 );
and VAR5 (VAR4 , VAR1, VAR10 );
VAR14 VAR16 (VAR11, VAR4, VAR2, VAR7);
... | apache-2.0 |
vipinkmenon/scas | hw/fpga/ipcore_dir/user_strm_fifo.v | 14,029 | module MODULE1(
VAR310,
VAR252,
VAR378,
VAR250,
VAR17,
VAR402,
VAR113,
VAR304,
VAR194,
VAR57,
VAR190
);
input VAR310;
input VAR252;
input VAR378;
input VAR250;
output VAR17;
input [63 : 0] VAR402;
output VAR113;
input VAR304;
output [63 : 0] VAR194;
output [9 : 0] VAR57;
output [9 : 0] VAR190;
VAR33 #(
.VAR326(0),
.VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/ha/sky130_fd_sc_lp__ha_4.v | 2,184 | module MODULE1 (
VAR9,
VAR10 ,
VAR5 ,
VAR8 ,
VAR6,
VAR4,
VAR7 ,
VAR1
);
output VAR9;
output VAR10 ;
input VAR5 ;
input VAR8 ;
input VAR6;
input VAR4;
input VAR7 ;
input VAR1 ;
VAR3 VAR2 (
.VAR9(VAR9),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR1(VAR1)
);
endmodule
module MODULE1... | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/verilog/boundtop.v | 71,955 | module MODULE10 (VAR126, VAR223, VAR327, VAR368, VAR162, VAR160, VAR132, VAR407, VAR82, VAR376, VAR72, VAR100, VAR435, VAR354, VAR204, VAR261, VAR432, VAR121, VAR148, VAR151, VAR43, VAR383, VAR361, VAR179, VAR95, VAR398, VAR195, VAR94, VAR209, VAR62, VAR262, VAR120, VAR420, VAR106, VAR8, VAR189, VAR226, VAR32, VAR213, ... | mit |
tloinuy/opencpi-opencv | opencpi/tools/cdk/include/hdl/onewire.v | 1,458 | module MODULE1(input VAR1, output VAR2);
assign VAR2 = VAR1;
endmodule | gpl-2.0 |
lsnow/mips32 | alu.v | 3,483 | module MODULE1(
clk, VAR38, VAR32, VAR9, VAR18,
VAR12,
VAR37, VAR26,VAR10, ready);
input clk;
input [31:0] VAR38; input [31:0] VAR32; input [31:0] VAR9;
input [20:0] VAR18;
wire VAR15, VAR16, VAR27, VAR25, VAR11, VAR20;
wire [2:0] VAR30;
wire [3:0] logic;
wire VAR43;
wire [2:0] VAR5;
assign {VAR15, VAR16, VAR27, VAR25,... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/prcfg/qpsk/prcfg_adc.v | 6,198 | module MODULE1 (
clk,
VAR15,
VAR27,
VAR8,
VAR19,
VAR35,
VAR11,
VAR20,
VAR9,
VAR29,
VAR14
);
parameter VAR7 = 0;
parameter VAR22 = 32;
localparam VAR34 = 2;
localparam VAR17 = 8'hA2;
input clk;
input [31:0] VAR15;
output [31:0] VAR27;
input VAR8;
input VAR19;
input [(VAR22-1):0] VAR35;
output VAR11;
output VAR20;
output... | gpl-3.0 |
alexforencich/verilog-ethernet | rtl/eth_phy_10g_rx_watchdog.v | 4,691 | module MODULE1 #
(
parameter VAR1 = 2,
parameter VAR3 = 125000/6.4
)
(
input wire clk,
input wire rst,
input wire [VAR1-1:0] VAR4,
output wire VAR7,
input wire VAR9,
input wire VAR5,
input wire VAR6,
input wire VAR8,
output wire VAR2
); | mit |
victor1994y/BipedRobot_byFPGA | Project_BipedRobot.srcs/sources_1/ip/clk_wiz_1/clk_wiz_1.v | 4,086 | module MODULE1
(
output VAR1,
output VAR3,
input VAR4,
output VAR2,
input VAR6
);
VAR5 VAR7
(
.VAR1(VAR1),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(VAR6)
);
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/decap/sky130_fd_sc_hdll__decap.symbol.v | 1,219 | module MODULE1 ();
supply1 VAR1;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfxbp/sky130_fd_sc_ms__sdfxbp.symbol.v | 1,434 | module MODULE1 (
input VAR9 ,
output VAR6 ,
output VAR8,
input VAR5,
input VAR1,
input VAR7
);
supply1 VAR2;
supply0 VAR10;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfrtp/sky130_fd_sc_hd__sdfrtp_4.v | 2,583 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR9 ,
VAR12 ,
VAR11 ,
VAR4,
VAR5 ,
VAR7 ,
VAR1 ,
VAR8
);
output VAR3 ;
input VAR2 ;
input VAR9 ;
input VAR12 ;
input VAR11 ;
input VAR4;
input VAR5 ;
input VAR7 ;
input VAR1 ;
input VAR8 ;
VAR6 VAR10 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR12(VAR12),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR... | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/registers.v | 26,643 | module MODULE1
parameter VAR68 = 128,
parameter VAR46 = 12,
parameter VAR54 = 512, parameter VAR162 = "VAR18",
parameter VAR79 = 2,
parameter VAR146 = 32,
parameter VAR44 = "VAR11",
parameter VAR168= 1,
parameter VAR29= 1
)
(
input VAR102,
input VAR172,
input [VAR68-1:0] VAR188,
input VAR161,
input VAR199,
input [VAR13... | gpl-3.0 |
titorgalaxy/Titor | rtl/verilog/timer/Timer.v | 5,138 | module MODULE1(
dout,
din,
address,
VAR7,
VAR16,
enable,
interrupt,
reset,
clk
);
output reg [VAR5-1:0] dout;
input wire [VAR5-1:0] din;
input wire [VAR5-1:0] address;
input wire [VAR6-1:0] VAR7;
input wire VAR16;
input wire enable;
output reg interrupt;
input reset;
input clk;
localparam VAR17 = 0;
localparam VAR15 = ... | gpl-3.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_29.v | 20,335 | module MODULE1 (
clk,
reset,
VAR71,
VAR177,
VAR8,
VAR63,
VAR149
);
parameter VAR50 = 18;
parameter VAR112 = 29;
parameter VAR42 = 15;
localparam VAR160 = 30;
input clk;
input reset;
input VAR71;
input VAR177;
input [VAR50-1:0] VAR8; output VAR63;
output [VAR50-1:0] VAR149;
localparam VAR133 = 18; localparam VAR30 = 36;... | mit |
CospanDesign/nysa-artemis-platform | artemis/slave/wb_nysa_artemis_platform/rtl/artemis_clkgen.v | 2,311 | module MODULE1 (
input clk,
input rst,
output VAR8,
output VAR3
);
wire VAR18;
wire VAR16;
wire VAR34;
wire VAR17;
VAR4 VAR20 (
.VAR1 (VAR16 ),
.VAR25 (VAR34 )
);
VAR6 #(
.VAR14 ("VAR9" ),
.VAR7 ("VAR31" ),
.VAR22 ("VAR30" ),
.VAR21 (1 ),
.VAR13 (10 ),
.VAR29 (0.00 ),
.VAR36 (3 ),
.VAR5 (0.00 ),
.VAR11 (0.50 ),
.VAR32 ... | gpl-2.0 |
dcsun88/ntpserver-fpga | sv/ip/ocxo_clk_pll/ocxo_clk_pll.v | 3,999 | module MODULE1
(
input VAR1,
output VAR6,
input VAR3,
output VAR4
);
VAR2 VAR5
(
.VAR1(VAR1),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR4(VAR4)
);
endmodule | gpl-3.0 |
drichmond/riffa | fpga/altera/de5/DE5Gen2x8If128/hdl/DE5Gen2x8If128.v | 24,095 | module MODULE1
parameter VAR176 = 8,
parameter VAR113 = 128,
parameter VAR161 = 256,
parameter VAR127 = 5
)
(
output [7:0] VAR56,
input VAR68,
input VAR89,
input [VAR176-1:0] VAR16,
output [VAR176-1:0] VAR13,
input VAR57
);
wire VAR97;
wire VAR83;
wire [11:0] VAR172;
wire [31:0] VAR106;
wire VAR38;
wire VAR162;
wire VA... | bsd-3-clause |
zeruniverse/pipelined_CPU | .v source code/alu.v | 1,690 | module MODULE1(VAR8, VAR3, VAR7, VAR2);
input wire [31:0] VAR8; input wire [31:0] VAR3; input wire [3:0] VAR7; output reg [31:0] VAR2; wire [31:0] VAR4;
wire [31:0] VAR6;
wire VAR1,VAR5; assign VAR4=VAR8+VAR3;
assign VAR6=VAR8-VAR3;
always @* begin
case(VAR7)
4'b0001: begin VAR2<=VAR8 & VAR3; end 4'b1001: begin VAR2<=V... | gpl-3.0 |
buhii/LGA-FHP2 | modulus3.v | 11,422 | module MODULE1
(
input [8:0] VAR3,
output [1:0] VAR2
);
function [1:0] VAR1;
input [8:0] VAR3;
begin
case ( VAR3 )
0: VAR1 = 2'd0;
1: VAR1 = 2'd1;
2: VAR1 = 2'd2;
3: VAR1 = 2'd0;
4: VAR1 = 2'd1;
5: VAR1 = 2'd2;
6: VAR1 = 2'd0;
7: VAR1 = 2'd1;
8: VAR1 = 2'd2;
9: VAR1 = 2'd0;
10: VAR1 = 2'd1;
11: VAR1 = 2'd2;
12: VAR1 = ... | mit |
subailong/miaow | src/verilog/rtl/rfa/rfa.v | 3,122 | module MODULE1(
VAR11, VAR31,
VAR34, VAR24,
VAR23, VAR29,
VAR19, VAR1,
VAR4,
clk, rst, VAR18, VAR5,
VAR21, VAR8,
VAR35, VAR33,
VAR26, VAR25, VAR10
);
input clk;
input rst;
input VAR18, VAR5, VAR21,
VAR8, VAR35, VAR33,
VAR26, VAR25, VAR10;
output VAR11, VAR31, VAR34,
VAR24, VAR23, VAR29,
VAR19, VAR1;
output [15:0] VAR4;... | bsd-3-clause |
MeshSr/onetswitch45 | ons45-app52-ref_ofshw/vivado/onets_7045_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/wildcard_match.v | 14,233 | module MODULE1
parameter VAR11 = 16,
parameter VAR3 = 0,
parameter VAR65 = 4,
parameter VAR43 = 64
)
( input [VAR64-1:0] VAR32,
input VAR16,
input [VAR8-1:0] VAR12,
output VAR61,
output VAR54,
output [VAR26-1:0] VAR5,
output VAR77,
input [VAR53 -1:0] VAR41,
output [VAR43-1:0] VAR21,
output [VAR43-33:0] VAR78,
input VAR... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/einvp/sky130_fd_sc_hd__einvp_1.v | 2,130 | module MODULE2 (
VAR2 ,
VAR8 ,
VAR7 ,
VAR1,
VAR5,
VAR9 ,
VAR6
);
output VAR2 ;
input VAR8 ;
input VAR7 ;
input VAR1;
input VAR5;
input VAR9 ;
input VAR6 ;
VAR4 VAR3 (
.VAR2(VAR2),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR2 ,
VAR8 ,
VAR7
);
output VAR2... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_ds_2/synth/design_1_auto_ds_2.v | 16,099 | module MODULE1 (
VAR3,
VAR36,
VAR59,
VAR24,
VAR37,
VAR98,
VAR57,
VAR6,
VAR19,
VAR82,
VAR22,
VAR38,
VAR13,
VAR91,
VAR43,
VAR12,
VAR86,
VAR46,
VAR9,
VAR63,
VAR97,
VAR55,
VAR48,
VAR21,
VAR70,
VAR67,
VAR49,
VAR28,
VAR45,
VAR73,
VAR51,
VAR62,
VAR32,
VAR47,
VAR52,
VAR84,
VAR54,
VAR10,
VAR88,
VAR77,
VAR5,
VAR71,
VAR56,
VAR25,... | mit |
ckdur/mriscv_vivado_arty | mriscv_vivado.srcs/sources_1/imports/uart/uart_tx.v | 4,519 | module MODULE1 #
(
parameter VAR19 = 8
)
(
input wire clk,
input wire rst,
input wire [VAR19-1:0] VAR22,
input wire VAR2,
output wire VAR3,
output wire VAR21,
output wire VAR7,
input wire [3:0] VAR8,
input wire [1:0] VAR18,
input wire [1:0] VAR13,
input wire [1:0] VAR1,
input wire [15:0] VAR10
);
reg VAR15 = 0;
reg VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o21ai/sky130_fd_sc_ms__o21ai.pp.symbol.v | 1,352 | module MODULE1 (
input VAR3 ,
input VAR8 ,
input VAR4 ,
output VAR5 ,
input VAR6 ,
input VAR2,
input VAR7,
input VAR1
);
endmodule | apache-2.0 |
GustavoOS/ARMAria | src/BarrelShifter.v | 2,454 | module MODULE1(
VAR11, VAR2,
VAR1,
VAR4,
VAR9, VAR10, VAR6 );
input [31:0] VAR11, VAR2;
input [3:0] VAR1;
output reg VAR9, VAR10, VAR6;
output reg [31:0] VAR4;
reg [31:0] VAR5, VAR7;
reg VAR8;
wire VAR3;
assign VAR3 = (VAR4 == 0);
always @ ( * ) begin
VAR9=0; VAR10=0; VAR6=0; VAR4=0; VAR5=0; VAR8=0; VAR7=0;
case (VAR1)... | mit |
Triple-Z/COExperiment_Repo | Project_Assignment_OnBoard/dm.v | 3,633 | module MODULE1 (addr, din, VAR4, VAR6, clk, dout, VAR1, VAR9, rst);
input [11:0] addr;
input [31:0] din;
input [1:0] VAR4;
input [1:0] VAR6;
input clk;
output reg [31:0] dout;
input [4 :0] VAR1;
output [31:0] VAR9;
input rst;
reg [31:0] VAR3 [31:0];
wire [1:0] VAR5;
wire [9:0] VAR7;
reg [7:0] VAR2;
reg [31:0] VAR8;
ass... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srsdfxtp/sky130_fd_sc_lp__srsdfxtp.functional.pp.v | 2,462 | module MODULE1 (
VAR4 ,
VAR11 ,
VAR19 ,
VAR8 ,
VAR17 ,
VAR22,
VAR2 ,
VAR9 ,
VAR6 ,
VAR13 ,
VAR21
);
output VAR4 ;
input VAR11 ;
input VAR19 ;
input VAR8 ;
input VAR17 ;
input VAR22;
input VAR2 ;
input VAR9 ;
input VAR6 ;
input VAR13 ;
input VAR21 ;
wire VAR14 ;
wire VAR1 ;
wire VAR15;
VAR12 VAR20 (VAR1 , VAR19, VAR8, V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_hdll__udp_dlatch_pr_pp_pg_n.blackbox.v | 1,472 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR4 ,
VAR2 ,
VAR1,
VAR5 ,
VAR7
);
output VAR3 ;
input VAR6 ;
input VAR4 ;
input VAR2 ;
input VAR1;
input VAR5 ;
input VAR7 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/controller/round_robin_arb.v | 7,530 | module MODULE1
parameter VAR20 = 100,
parameter VAR15 = 3
)
(
VAR7, VAR3,
clk, rst, req, VAR5, VAR14, VAR4
);
input clk;
input rst;
input [VAR15-1:0] req;
wire [VAR15-1:0] VAR11;
reg [VAR15*2-1:0] VAR13;
always @(VAR11)
VAR13 = {VAR11, VAR11};
reg [VAR15*2-1:0] VAR8;
always @(req) VAR8 = {req, req};
reg [VAR15-1:0] VAR... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21boi/sky130_fd_sc_hs__a21boi.pp.blackbox.v | 1,348 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR5 ,
VAR6,
VAR3,
VAR1
);
output VAR2 ;
input VAR4 ;
input VAR5 ;
input VAR6;
input VAR3;
input VAR1;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/mux2/sky130_fd_sc_hvl__mux2.symbol.v | 1,326 | module MODULE1 (
input VAR4,
input VAR5,
output VAR7 ,
input VAR8
);
supply1 VAR6;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_2.behavioral.pp.v | 1,182 | module MODULE1( VAR2, VAR4, VAR7, VAR5 );
input VAR2;
inout VAR7, VAR5;
output VAR4;
VAR6 VAR3(.VAR2(VAR2),.VAR4(VAR4),.VAR7(VAR7),.VAR5(VAR5));
VAR6 VAR1(.VAR2(VAR2),.VAR4(VAR4),.VAR7(VAR7),.VAR5(VAR5)); | apache-2.0 |
Xilinx/PYNQ | boards/ip/fsm_io_switch_1.1/hdl/fsm_io_switch_v1_1.v | 2,786 | module MODULE1 #
(
parameter VAR16 = 20,
parameter VAR21 = 0,
parameter integer VAR49 = 32,
parameter integer VAR48 = 5
)
(
input [VAR16-1:0] VAR53,
input [3:0] VAR17,
output [VAR16-1:0] VAR24,
output [7:0]VAR8,
input [VAR16-1:0] VAR2,
output [VAR16-1:0] VAR44,
input wire VAR3,
input wire VAR42,
input wire [VAR48-1 : 0... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21o/sky130_fd_sc_ls__a21o.blackbox.v | 1,326 | module MODULE1 (
VAR7 ,
VAR5,
VAR3,
VAR1
);
output VAR7 ;
input VAR5;
input VAR3;
input VAR1;
supply1 VAR2;
supply0 VAR4;
supply1 VAR8 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_lp__udp_dlatch_pr_pp_pg_n.blackbox.v | 1,464 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR4 ,
VAR7 ,
VAR1,
VAR6 ,
VAR5
);
output VAR3 ;
input VAR2 ;
input VAR4 ;
input VAR7 ;
input VAR1;
input VAR6 ;
input VAR5 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v6es_gtx_x4_250/example_design/PIO_TO_CTRL.v | 3,948 | module MODULE1 (
clk,
VAR1,
VAR3,
VAR6,
VAR4,
VAR5
);
input clk;
input VAR1;
input VAR3;
input VAR6;
input VAR4;
output VAR5;
reg VAR2;
reg VAR5;
always @ ( posedge clk or negedge VAR1 ) begin
if (!VAR1 ) begin
VAR2 <= 0;
end else begin
if (!VAR2 && VAR3)
VAR2 <= 1'b1;
end
else if (VAR6)
VAR2 <= 1'b0;
end
end
always @ ... | lgpl-3.0 |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/vivado_cores/sfa_2x2_v1_0/sfa_2x2.v | 28,968 | module MODULE1(
input wire VAR23,
output wire VAR214,
output wire [31 : 0] VAR316 ,
input wire VAR210,
output wire VAR301,
output wire [31 : 0] VAR13 ,
output wire VAR35 ,
input wire VAR65 ,
input wire [31 : 0] VAR147 ,
output wire VAR145 ,
input wire VAR313 ,
input wire [31 : 0] VAR258 ,
input wire VAR161 ,
output wir... | bsd-3-clause |
Pylonight/MIPS-CPU | cpu/Anvyl_DISP.v | 2,225 | module MODULE1(
output [7 : 0] VAR6,
output [5 : 0] VAR2,
input clk,
input rst,
input [23 : 0] VAR1
);
reg [7 : 0] VAR5;
reg [5 : 0] VAR4;
reg [3 : 0] VAR3;
reg [19 : 0] VAR7;
assign VAR6 = ~VAR5;
assign VAR2 = ~VAR4;
always @(posedge clk or negedge rst)
begin
if (rst == 0)
begin
VAR7 = 0;
end
else
begin
VAR7 = VAR7+1;... | gpl-2.0 |
csturton/wirepatch | system/hardware/cores/fabric/ovl_ported/redundant/ovl_decrement.v | 1,451 | module MODULE1 (VAR10, reset, enable, VAR9, VAR1);
parameter VAR11 = VAR8;
parameter VAR3 = 1;
parameter VAR6 = 1;
parameter VAR13 = VAR2;
parameter VAR18 = VAR21;
parameter VAR12 = VAR14;
parameter VAR4 = VAR23;
parameter VAR19 = VAR15;
parameter VAR16 = VAR7;
input VAR10, reset, enable;
input [VAR3-1:0] VAR9;
output ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlrtp/sky130_fd_sc_hdll__dlrtp.blackbox.v | 1,374 | module MODULE1 (
VAR8 ,
VAR1,
VAR7 ,
VAR6
);
output VAR8 ;
input VAR1;
input VAR7 ;
input VAR6 ;
supply1 VAR3;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
zuloloxi/mecrisp-ice | nandland/icestorm/j1a.v | 9,990 | module MODULE2(
output [1:0] VAR96,
input VAR128, VAR76, VAR10,
input [10:0] VAR77,
input VAR41, VAR39, VAR52,
input [10:0] VAR59,
input [1:0] VAR64, VAR131
);
parameter VAR126 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter VAR102 = 256'h0000000000000000000000000000000000000000000000... | bsd-3-clause |
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