text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163
values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751
values | repo_full_name stringclasses 752
values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```unknown
/*
*
*/
/dts-v1/;
#include <intel/intel_adsp_ace30_ptl.dtsi>
/ {
model = "intel_adsp_ace30_ptl";
compatible = "intel";
chosen {
zephyr,sram = &sram0;
zephyr,console = &mem_window3;
};
};
``` | /content/code_sandbox/boards/intel/adsp/intel_adsp_ace30_ptl.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 76 |
```yaml
boards:
- name: intel_adsp
vendor: intel
socs:
- name: cavs25
variants:
- name: 'tgph'
- name: ace15_mtpm
- name: ace20_lnl
- name: ace30_ptl
``` | /content/code_sandbox/boards/intel/adsp/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 67 |
```yaml
identifier: intel_adsp/ace15_mtpm
name: ACE 1.5 MTL M Audio DSP
type: mcu
arch: xtensa
toolchain:
- zephyr
- xcc
- xt-clang
supported:
- dma
testing:
ignore_tags:
- net
- bluetooth
vendor: intel
``` | /content/code_sandbox/boards/intel/adsp/intel_adsp_ace15_mtpm.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 80 |
```unknown
/*
*
*/
/dts-v1/;
#include <intel/intel_adsp_ace20_lnl.dtsi>
/ {
model = "intel_adsp_ace20_lnl";
compatible = "intel,intel_adsp_ace20_lnl";
chosen {
zephyr,sram = &sram0;
zephyr,console = &mem_window3;
};
};
``` | /content/code_sandbox/boards/intel/adsp/intel_adsp_ace20_lnl.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 85 |
```unknown
config BOARD_INTEL_ADSP
select SOC_INTEL_CAVS_V25 if BOARD_INTEL_ADSP_CAVS25
select SOC_INTEL_CAVS_V25 if BOARD_INTEL_ADSP_CAVS25_TGPH
select SOC_INTEL_ACE15_MTPM if BOARD_INTEL_ADSP_ACE15_MTPM
select SOC_INTEL_ACE20_LNL if BOARD_INTEL_ADSP_ACE20_LNL
select SOC_INTEL_ACE30_PTL if BOARD_INTEL_ADSP_ACE30... | /content/code_sandbox/boards/intel/adsp/Kconfig.intel_adsp | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 117 |
```unknown
/*
*
*/
/dts-v1/;
#include <intel/intel_adsp_cavs25_tgph.dtsi>
/ {
model = "intel_adsp_cavs25_tgph";
compatible = "intel,intel_adsp_cavs25_tgph";
aliases {
dma0 = &lpgpdma0;
};
chosen {
zephyr,sram = &sram0;
zephyr,console = &mem_window3;
};
};
``` | /content/code_sandbox/boards/intel/adsp/intel_adsp_cavs25_tgph.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 105 |
```unknown
#
if DAI_INTEL_SSP
config DAI_SSP_HAS_POWER_CONTROL
def_bool y
endif
``` | /content/code_sandbox/boards/intel/adsp/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 25 |
```yaml
identifier: intel_adsp/ace20_lnl
name: ACE 2.0 LNL Audio DSP
type: mcu
arch: xtensa
toolchain:
- xcc
- xt-clang
- zephyr
supported:
- dma
testing:
ignore_tags:
- net
- bluetooth
- mcumgr
vendor: intel
``` | /content/code_sandbox/boards/intel/adsp/intel_adsp_ace20_lnl.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 84 |
```unknown
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_GEN_ISR_TABLES=y
CONFIG_GEN_IRQ_VECTOR_TABLE=n
CONFIG_BUILD_OUTPUT_BIN=n
CONFIG_MM_DRV=y
CONFIG_CRYPTO=y
CONFIG_DCACHE_LINE_SIZE=64
``` | /content/code_sandbox/boards/intel/adsp/intel_adsp_ace15_mtpm_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 47 |
```yaml
identifier: intel_adsp/cavs25
name: cAVS 2.5 Audio DSP (converged Audio Voice and Speech)
type: mcu
arch: xtensa
toolchain:
- xcc
- zephyr
supported:
- dma
- dai
testing:
ignore_tags:
- net
- bluetooth
vendor: intel
``` | /content/code_sandbox/boards/intel/adsp/intel_adsp_cavs25.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 82 |
```unknown
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_GEN_ISR_TABLES=y
CONFIG_GEN_IRQ_VECTOR_TABLE=n
CONFIG_BUILD_OUTPUT_BIN=n
CONFIG_MM_DRV=y
CONFIG_MM_DRV_INTEL_ADSP_MTL_TLB=y
CONFIG_DCACHE_LINE_SIZE=64
``` | /content/code_sandbox/boards/intel/adsp/intel_adsp_ace20_lnl_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 56 |
```unknown
CONFIG_MAIN_STACK_SIZE=4096
CONFIG_GEN_ISR_TABLES=y
CONFIG_GEN_IRQ_VECTOR_TABLE=n
CONFIG_BUILD_OUTPUT_BIN=n
CONFIG_DAI_SSP_HAS_POWER_CONTROL=y
CONFIG_DCACHE_LINE_SIZE=64
``` | /content/code_sandbox/boards/intel/adsp/intel_adsp_ace30_ptl_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 48 |
```restructuredtext
.. _intel_adsp_cavs25:
Intel ADSP CAVS 2.5
###################
Overview
********
This board configuration is used to run Zephyr on the Intel CAVS 2.5 Audio DSP.
This configuration is present, for example, on Intel `Tiger Lake`_ microprocessors.
Refer to :ref:`intel_adsp_generic` for more details ... | /content/code_sandbox/boards/intel/adsp/doc/intel_adsp_cavs25.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 244 |
```restructuredtext
.. _boards-intel-adsp:
Intel ADSP
##########
.. toctree::
intel_adsp_generic
chromebooks_adsp
intel_adsp_cavs25
intel_adsp_ace15_mtpm
``` | /content/code_sandbox/boards/intel/adsp/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```restructuredtext
.. _intel_adsp_ace15:
Intel ADSP ACE 1.5
##################
Overview
********
This board configuration is used to run Zephyr on the Intel ACE 1.5 Audio DSP.
This configuration is present, for example, on Intel Meteor Lake microprocessors.
Refer to :ref:`intel_adsp_generic` for more details on Int... | /content/code_sandbox/boards/intel/adsp/doc/intel_adsp_ace15_mtpm.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 253 |
```restructuredtext
.. _intel_adsp_generic:
Intel ADSP cAVS and ACE
#######################
Intel's Audio and Digital Signal Processing (ADSP) hardware offerings
include the Converged Audio Voice Speech (cAVS) series and its successor,
the Audio and Context Engine (ACE). These Xtensa-based ADSPs can be integrated
int... | /content/code_sandbox/boards/intel/adsp/doc/intel_adsp_generic.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,288 |
```unknown
config BOARD_INTEL_RPL_P_CRB
select SOC_RAPTOR_LAKE
``` | /content/code_sandbox/boards/intel/rpl/Kconfig.intel_rpl_p_crb | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 20 |
```restructuredtext
.. _zephyr-audio-dsp-development-on-chromebooks:
Zephyr Audio DSP Development on Chromebooks
###########################################
The Audio DSP on Intel Chromebooks is configured to use the SOF
"Community" key for firmware signing, and can therefore accept
arbitrary user-developed firmware ... | /content/code_sandbox/boards/intel/adsp/doc/chromebooks_adsp.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,680 |
```cmake
board_set_flasher_ifnset(misc-flasher)
board_finalize_runner_args(misc-flasher)
``` | /content/code_sandbox/boards/intel/rpl/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 23 |
```yaml
identifier: intel_rpl_p_crb
name: Raptor Lake P CRB
type: mcu
arch: x86
toolchain:
- zephyr
ram: 2048
supported:
- acpi
- smp
- smbus
- watchdog
- rtc
- pwm
- gpio
- spi
- i2c
testing:
ignore_tags:
- net
- bluetooth
vendor: intel
``` | /content/code_sandbox/boards/intel/rpl/intel_rpl_p_crb.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 105 |
```yaml
identifier: intel_rpl_s_crb
name: Raptor Lake S CRB
type: mcu
arch: x86
toolchain:
- zephyr
ram: 2048
supported:
- acpi
- smp
- smbus
- watchdog
- rtc
- pwm
- gpio
testing:
ignore_tags:
- net
- bluetooth
vendor: intel
``` | /content/code_sandbox/boards/intel/rpl/intel_rpl_s_crb.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 95 |
```unknown
config BOARD_INTEL_RPL_S_CRB
select SOC_RAPTOR_LAKE
``` | /content/code_sandbox/boards/intel/rpl/Kconfig.intel_rpl_s_crb | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 20 |
```unknown
CONFIG_PIC_DISABLE=y
CONFIG_LOAPIC=y
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_NS16550=y
CONFIG_UART_NS16550_VARIANT_NS16750=y
CONFIG_UART_CONSOLE=y
CONFIG_X2APIC=y
CONFIG_SMP=y
CONFIG_BUILD_OUTPUT_EFI=y
CONFIG_BUILD_NO_GAP_FILL=y
``` | /content/code_sandbox/boards/intel/rpl/intel_rpl_s_crb_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 72 |
```unknown
/*
*/
/dts-v1/;
#include <mem.h>
#define DT_DRAM_SIZE DT_SIZE_M(2048)
#include <intel/raptor_lake_s.dtsi>
/ {
model = "intel_rpl_s_crb";
compatible = "intel,raptor-lake-crb";
chosen {
zephyr,sram = &dram0;
zephyr,console = &uart_ec_0;
zephyr,shell-uart = &uart_ec_0;
};
aliases {
watchdo... | /content/code_sandbox/boards/intel/rpl/intel_rpl_s_crb.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 134 |
```yaml
boards:
- name: intel_rpl_p_crb
vendor: intel
socs:
- name: raptor_lake
- name: intel_rpl_s_crb
vendor: intel
socs:
- name: raptor_lake
``` | /content/code_sandbox/boards/intel/rpl/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 61 |
```unknown
/*
*/
/dts-v1/;
#include <mem.h>
#define DT_DRAM_SIZE DT_SIZE_M(2048)
#include <intel/raptor_lake_p.dtsi>
/ {
model = "intel_rpl_p_crb";
compatible = "intel,raptor-lake-crb";
chosen {
zephyr,sram = &dram0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
};
aliases {
watchdog0 = &tc... | /content/code_sandbox/boards/intel/rpl/intel_rpl_p_crb.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 130 |
```unknown
CONFIG_PIC_DISABLE=y
CONFIG_LOAPIC=y
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_NS16550=y
CONFIG_UART_NS16550_VARIANT_NS16750=y
CONFIG_UART_CONSOLE=y
CONFIG_X2APIC=y
CONFIG_SMP=y
CONFIG_BUILD_OUTPUT_EFI=y
CONFIG_BUILD_NO_GAP_FILL=y
``` | /content/code_sandbox/boards/intel/rpl/intel_rpl_p_crb_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 72 |
```unknown
config BUILD_OUTPUT_STRIPPED
default y
config MP_MAX_NUM_CPUS
default 2
# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 1900000000 if APIC_TSC_DEADLINE_TIMER
default 1900000000 if APIC_TIMER_TSC
default 19200000
if APIC_TIMER
config APIC_TIMER_I... | /content/code_sandbox/boards/intel/rpl/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 285 |
```cmake
board_set_flasher_ifnset(misc-flasher)
board_finalize_runner_args(misc-flasher)
``` | /content/code_sandbox/boards/intel/adl/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 23 |
```unknown
/*
*
*/
#include "intel_adl.dts"
/ {
model = "Intel Alder Lake RVP";
compatible = "intel,alder-lake-rvp";
chosen {
zephyr,console = &uart0_legacy;
zephyr,shell-uart = &uart0_legacy;
};
};
``` | /content/code_sandbox/boards/intel/adl/intel_adl_rvp.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 69 |
```unknown
config BOARD_INTEL_ADL_RVP
select SOC_ALDER_LAKE
``` | /content/code_sandbox/boards/intel/adl/Kconfig.intel_adl_rvp | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 18 |
```unknown
CONFIG_PIC_DISABLE=y
CONFIG_LOAPIC=y
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_NS16550=y
CONFIG_UART_CONSOLE=y
CONFIG_X2APIC=y
CONFIG_SMP=y
CONFIG_BUILD_OUTPUT_EFI=y
CONFIG_BUILD_NO_GAP_FILL=y
``` | /content/code_sandbox/boards/intel/adl/intel_adl_rvp_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 60 |
```restructuredtext
.. _intel_rpl_crb:
Raptor Lake CRB
###############
Overview
********
Raptor Lake processor is a 13th generation 64-bit multi-core processor built
on a 10-nanometer technology process. Raptor Lake is based on a Hybrid
architecture, utilizing P-cores for performance and E-Cores for efficiency.
Rapt... | /content/code_sandbox/boards/intel/rpl/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 522 |
```unknown
/*
*
*/
#include "intel_adl.dts"
/ {
model = "Intel Alder Lake CRB";
compatible = "intel,alder-lake-crb";
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
};
aliases {
rtc = &rtc;
};
};
&uart0 {
status = "okay";
};
``` | /content/code_sandbox/boards/intel/adl/intel_adl_crb.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 89 |
```yaml
identifier: intel_adl_crb
name: Alder Lake CRB
type: mcu
arch: x86
toolchain:
- zephyr
ram: 2048
supported:
- acpi
- watchdog
- pwm
- gpio
- rtc
- i2c
- spi
- smp
testing:
timeout_multiplier: 4
ignore_tags:
- net
- bluetooth
vendor: intel
``` | /content/code_sandbox/boards/intel/adl/intel_adl_crb.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 105 |
```unknown
/*
*
*/
/dts-v1/;
#include <mem.h>
#define DT_DRAM_SIZE DT_SIZE_M(2048)
#include <intel/alder_lake.dtsi>
/ {
chosen {
zephyr,sram = &dram0;
};
aliases {
watchdog0 = &tco_wdt;
sdhc0 = &emmc;
};
};
``` | /content/code_sandbox/boards/intel/adl/intel_adl.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 87 |
```unknown
config BOARD_INTEL_ADL_CRB
select SOC_ALDER_LAKE
``` | /content/code_sandbox/boards/intel/adl/Kconfig.intel_adl_crb | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 18 |
```unknown
CONFIG_PIC_DISABLE=y
CONFIG_LOAPIC=y
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_NS16550=y
CONFIG_UART_CONSOLE=y
CONFIG_X2APIC=y
CONFIG_SMP=y
CONFIG_BUILD_OUTPUT_EFI=y
CONFIG_BUILD_NO_GAP_FILL=y
``` | /content/code_sandbox/boards/intel/adl/intel_adl_crb_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 60 |
```yaml
boards:
- name: intel_adl_crb
vendor: intel
socs:
- name: alder_lake
- name: intel_adl_rvp
vendor: intel
socs:
- name: alder_lake
``` | /content/code_sandbox/boards/intel/adl/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```yaml
identifier: intel_adl_rvp
name: Alder Lake RVP
type: mcu
arch: x86
toolchain:
- zephyr
ram: 2048
supported:
- acpi
- smp
- watchdog
testing:
timeout_multiplier: 4
ignore_tags:
- net
- bluetooth
vendor: intel
``` | /content/code_sandbox/boards/intel/adl/intel_adl_rvp.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 83 |
```unknown
config BUILD_OUTPUT_STRIPPED
default y
config MP_MAX_NUM_CPUS
default 2
# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 1900000000 if APIC_TSC_DEADLINE_TIMER
default 1900000000 if APIC_TIMER_TSC
default 19200000
if APIC_TIMER
config APIC_TIMER_IR... | /content/code_sandbox/boards/intel/adl/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 259 |
```unknown
/*
*
*
*/
/dts-v1/;
#include <intel/intel_socfpga_agilex.dtsi>
/ {
model = "Intel SoC FPGA Agilex";
compatible = "intel,socfpga-agilex";
#address-cells = <1>;
#size-cells = <1>;
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sram = &mem0;
};
};
&uart0 {
status = "o... | /content/code_sandbox/boards/intel/socfpga/agilex_socdk/intel_socfpga_agilex_socdk.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 190 |
```restructuredtext
.. _intel_adl_n:
Alder Lake N
############
Overview
********
Alder Lake processor is a 64-bit multi-core processor built on 10-nanometer
technology process.
Currently supported is N-processor line, Single Chip Platform that consists of
the Processor Die and Alder Lake N Platform Controller Hub (A... | /content/code_sandbox/boards/intel/adl/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 433 |
```unknown
# The Zephyr build from this defconfig is expected to boot from
# Intel Arm Trusted Firmware (ATF)
# Boot Flow: BL21 -> BL31 -> Zephyr
CONFIG_ARM_ARCH_TIMER=y
# Serial Drivers
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_UART_NS16550_ACCESS_WORD_ONLY=y
# Enable Console
CONFIG_CONSOLE=y
CONFIG_UA... | /content/code_sandbox/boards/intel/socfpga/agilex_socdk/intel_socfpga_agilex_socdk_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 107 |
```yaml
board:
name: intel_socfpga_agilex_socdk
socs:
- name: agilex
``` | /content/code_sandbox/boards/intel/socfpga/agilex_socdk/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 27 |
```yaml
identifier: intel_socfpga_agilex_socdk
name: Intel SoC FPGA Agilex
type: mcu
arch: arm64
toolchain:
- zephyr
- cross-compile
vendor: intel
``` | /content/code_sandbox/boards/intel/socfpga/agilex_socdk/intel_socfpga_agilex_socdk.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```unknown
config BOARD_INTEL_SOCFPGA_AGILEX_SOCDK
select SOC_AGILEX
help
Intel SoC FPGA Development Kit (Agilex)
``` | /content/code_sandbox/boards/intel/socfpga/agilex_socdk/Kconfig.intel_socfpga_agilex_socdk | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```unknown
# The Zephyr build from this defconfig is expected to boot from
# Intel Arm Trusted Firmware (ATF).
# Boot Flow is: ATF BL21 -> ATF BL31 -> Zephyr
# Compiler Options
CONFIG_FORTIFY_SOURCE_RUN_TIME=y
# Arm Features
CONFIG_ARM_ARCH_TIMER=y
CONFIG_CACHE_MANAGEMENT=y
CONFIG_ARMV8_A_NS=y
# Serial Drivers
CONF... | /content/code_sandbox/boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 190 |
```yaml
identifier: intel_socfpga_agilex5_socdk
name: Intel SoC FPGA Agilex5
type: mcu
arch: arm64
toolchain:
- zephyr
- cross-compile
vendor: intel
``` | /content/code_sandbox/boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 53 |
```yaml
board:
name: intel_socfpga_agilex5_socdk
socs:
- name: agilex5
``` | /content/code_sandbox/boards/intel/socfpga/agilex5_socdk/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 29 |
```restructuredtext
.. _intel_socfpga_agilex_socdk:
Intel Agilex SoC Development Kit
#################################
Overview
********
The Intel Agilex SoC Development Kit offers a complete design environment
that includes both hardware and software for developing Intel Agilex
F-Series FPGA designs. This kit is re... | /content/code_sandbox/boards/intel/socfpga/agilex_socdk/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 576 |
```unknown
/*
*
*/
/dts-v1/;
#include <intel/intel_socfpga_agilex5.dtsi>
/ {
model = "Intel SoC FPGA Agilex5";
compatible = "intel,socfpga-agilex5";
#address-cells = <1>;
#size-cells = <1>;
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sram = &mem0;
};
};
&sdmmc {
status = "ok... | /content/code_sandbox/boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 171 |
```unknown
config BOARD_INTEL_SOCFPGA_AGILEX5_SOCDK
select SOC_AGILEX5
help
Intel SoC FPGA Development Kit (Agilex5)
``` | /content/code_sandbox/boards/intel/socfpga/agilex5_socdk/Kconfig.intel_socfpga_agilex5_socdk | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 39 |
```unknown
config HAS_COVERAGE_SUPPORT
default y
config MAX_THREAD_BYTES
default 5
``` | /content/code_sandbox/boards/intel/socfpga/agilex5_socdk/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 20 |
```yaml
identifier: intel_ish_5_8_0
name: Intel ISH 5.8.0 SoC
type: mcu
arch: x86
toolchain:
- zephyr
ram: 640
supported:
- serial
testing:
ignore_tags:
- net
- bluetooth
vendor: intel
``` | /content/code_sandbox/boards/intel/ish/intel_ish_5_8_0.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 75 |
```yaml
identifier: intel_ish_5_6_0
name: Intel ISH 5.6.0 SoC
type: mcu
arch: x86
toolchain:
- zephyr
ram: 640
supported:
- serial
testing:
ignore_tags:
- net
- bluetooth
vendor: intel
``` | /content/code_sandbox/boards/intel/ish/intel_ish_5_6_0.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 75 |
```unknown
/*
*
*/
/dts-v1/;
#include "intel/intel_ish5_8.dtsi"
/ {
model = "intel_ish_5_8_0";
compatible = "intel,ish_5_8_0";
chosen {
zephyr,sram = &sram;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
};
};
``` | /content/code_sandbox/boards/intel/ish/intel_ish_5_8_0.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 94 |
```unknown
#
#
#
# uart & console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
``` | /content/code_sandbox/boards/intel/ish/intel_ish_5_8_0_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```unknown
#
config BOARD_INTEL_ISH_5_6_0
select SOC_INTEL_ISH_5_6_0
``` | /content/code_sandbox/boards/intel/ish/Kconfig.intel_ish_5_6_0 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```restructuredtext
.. _intel_socfpga_agilex5_socdk:
Intel Agilex 5 SoC FPGA Development Kit
#########################################
Overview
********
The Intel Agilex 5 SoC FPGA Development Kit offers a complete design
environment that includes both hardware and software for developing
Intel Agilex 5 E-Series bas... | /content/code_sandbox/boards/intel/socfpga/agilex5_socdk/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 676 |
```yaml
identifier: intel_ish_5_4_1
name: Intel ISH 5.4.1 SoC
type: mcu
arch: x86
toolchain:
- zephyr
ram: 640
supported:
- serial
testing:
ignore_tags:
- net
- bluetooth
vendor: intel
``` | /content/code_sandbox/boards/intel/ish/intel_ish_5_4_1.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 75 |
```unknown
/*
*
*/
/dts-v1/;
#include "intel/intel_ish5.dtsi"
/ {
model = "intel_ish_5_4_1";
compatible = "intel,ish_5_4_1";
chosen {
zephyr,sram = &sram;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
};
};
``` | /content/code_sandbox/boards/intel/ish/intel_ish_5_4_1.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 92 |
```unknown
/*
*
*/
/dts-v1/;
#include "intel/intel_ish5.dtsi"
/ {
model = "intel_ish_5_6_0";
compatible = "intel,ish_5_6_0";
chosen {
zephyr,sram = &sram;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
};
};
``` | /content/code_sandbox/boards/intel/ish/intel_ish_5_6_0.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 92 |
```yaml
boards:
- name: intel_ish_5_4_1
vendor: intel
socs:
- name: intel_ish_5_4_1
- name: intel_ish_5_6_0
vendor: intel
socs:
- name: intel_ish_5_6_0
- name: intel_ish_5_8_0
vendor: intel
socs:
- name: intel_ish_5_8_0
``` | /content/code_sandbox/boards/intel/ish/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 114 |
```unknown
#
#
#
# uart & console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
``` | /content/code_sandbox/boards/intel/ish/intel_ish_5_4_1_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```unknown
#
#
#
# uart & console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
``` | /content/code_sandbox/boards/intel/ish/intel_ish_5_6_0_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```unknown
#
config BOARD_INTEL_ISH_5_4_1
select SOC_INTEL_ISH_5_4_1
``` | /content/code_sandbox/boards/intel/ish/Kconfig.intel_ish_5_4_1 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```unknown
#
config BOARD_INTEL_ISH_5_8_0
select SOC_INTEL_ISH_5_8_0
``` | /content/code_sandbox/boards/intel/ish/Kconfig.intel_ish_5_8_0 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```unknown
#
#
if TEST
config TEST_EXTRA_STACK_SIZE
default 1024
endif # TEST
config SYS_CLOCK_TICKS_PER_SEC
default 2048 if HPET_TIMER # HPET timer's frequency is 32768 HZ
default 2000 if APIC_TIMER_TSC # APIC timer's frequency is 19.2 MHZ or 100 MHZ
``` | /content/code_sandbox/boards/intel/ish/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 79 |
```restructuredtext
.. _boards-beagle:
BeagleBoard.org Foundation
##########################
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/beagle/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```unknown
CONFIG_MPFS_HAL=n
CONFIG_BASE64=y
CONFIG_INCLUDE_RESET_VECTOR=y
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_XIP=n
CONFIG_INIT_STACKS=y
CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
CONFIG_FPU=n
``` | /content/code_sandbox/boards/beagle/beaglev_fire/beaglev_fire_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```unknown
/*
*
*/
/dts-v1/;
#include <microchip/mpfs.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include <mem.h>
/ {
model = "BeagleV-Fire";
compatible = "beagle,beaglev-fire", "microchip,mpfs";
aliases {
};
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sram = ... | /content/code_sandbox/boards/beagle/beaglev_fire/beaglev_fire.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 152 |
```yaml
board:
name: beaglev_fire
vendor: beagle
socs:
- name: polarfire
``` | /content/code_sandbox/boards/beagle/beaglev_fire/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```restructuredtext
.. _intel_ish:
Intel Integrated Sensor Hub (ISH)
#################################
Overview
********
Intel Integrated Sensor Hub (ISH) is a lower-power/always-on co-processor
inside many Intel Processors. It helps offload sensor processing tasks from
the core processor for better power saving.
Ha... | /content/code_sandbox/boards/intel/ish/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 556 |
```unknown
config BOARD_BEAGLEV_FIRE
select 64BIT
select SCHED_IPI_SUPPORTED
select CPU_HAS_FPU_DOUBLE_PRECISION
``` | /content/code_sandbox/boards/beagle/beaglev_fire/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```yaml
identifier: beaglev_fire
name: Beagleboard BeagleV-Fire
type: mcu
arch: riscv
toolchain:
- zephyr
ram: 3840
testing:
ignore_tags:
- net
- bluetooth
vendor: beagle
``` | /content/code_sandbox/boards/beagle/beaglev_fire/beaglev_fire.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 64 |
```unknown
config BOARD_BEAGLEV_FIRE
select SOC_POLARFIRE
``` | /content/code_sandbox/boards/beagle/beaglev_fire/Kconfig.beaglev_fire | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 16 |
```unknown
#
#
#
CONFIG_GPIO=y
CONFIG_PINCTRL=y
CONFIG_BUILD_OUTPUT_HEX=y
# custom callback for the antenna switch
CONFIG_CC13X2_CC26X2_HAS_CUSTOM_RF_HWATTRS=y
CONFIG_CC13X2_CC26X2_BOOTLOADER_ENABLE=y
CONFIG_CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE=y
CONFIG_CC13X2_CC26X2_BOOTLOADER_BACKDOOR_PIN=15
# Enable MPU and ha... | /content/code_sandbox/boards/beagle/beagleconnect_freedom/beagleconnect_freedom_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 162 |
```cmake
#
# Download cc1352-flasher (path_to_url using the following command:
# pip3 install cc1352-flasher
find_program(CC1352_FLASHER NAMES cc1352_flasher)
board_set_flasher_ifnset(misc-flasher)
board_finalize_runner_args(misc-flasher ${CC1352_FLASHER} --bcf)
``` | /content/code_sandbox/boards/beagle/beagleconnect_freedom/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 75 |
```restructuredtext
.. _beaglev_fire:
BeagleV-Fire
#############
Overview
********
BeagleV-Fire is a revolutionary single-board computer (SBC) powered by the Microchips
PolarFire MPFS025T 5x core RISC-V System on Chip (SoC) with FPGA fabric. BeagleV-Fire opens up new
horizons for developers, tinkerers, and the open-... | /content/code_sandbox/boards/beagle/beaglev_fire/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 723 |
```unknown
*
*
*/
#include <zephyr/dt-bindings/pinctrl/cc13xx_cc26xx-pinctrl.h>
&pinctrl {
/* UART0 */
uart0_tx_default: uart0_tx_default {
pinmux = <13 IOC_PORT_MCU_UART0_TX>;
bias-disable;
};
uart0_rx_default: uart0_rx_default {
pinmux = <12 IOC_PORT_MCU_UART0_RX>;
bias-disable;
input-enable;
};
... | /content/code_sandbox/boards/beagle/beagleconnect_freedom/beagleconnect_freedom-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 712 |
```c
/*
*
*/
/*
* Implements the RF driver callback to configure the on-board antenna
* switch.
*/
#define DT_DRV_COMPAT skyworks_sky13317
#include <zephyr/init.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/pinctrl.h>
#include <ti/drivers/rf/RF.h>
#include <driverlib/r... | /content/code_sandbox/boards/beagle/beagleconnect_freedom/board_antenna.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 960 |
```unknown
# BeagleConnect Freedom board configuration
config BOARD_BEAGLECONNECT_FREEDOM
select SOC_CC1352P7
``` | /content/code_sandbox/boards/beagle/beagleconnect_freedom/Kconfig.beagleconnect_freedom | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 27 |
```yaml
identifier: beagleconnect_freedom
name: BeagleConnect Freedom
type: mcu
arch: arm
ram: 144
flash: 704
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- gpio
- i2c
- spi
- uart
- hwinfo
vendor: beagle
``` | /content/code_sandbox/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 86 |
```yaml
board:
name: beagleconnect_freedom
vendor: beagle
socs:
- name: cc1352p7
``` | /content/code_sandbox/boards/beagle/beagleconnect_freedom/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
# BeagleConnect Freedom board configuration
if BOARD_BEAGLECONNECT_FREEDOM
config BOARD_ANTENNA_INIT_PRIO
int "Board antenna switch initialization priority"
default 70
help
Set the priority for board init, must be greater than
KERNEL_INIT_PRIORITY_DEVICE but smaller than
IEEE802154_CC13XX_CC26... | /content/code_sandbox/boards/beagle/beagleconnect_freedom/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 92 |
```unknown
/*
*
*/
/dts-v1/;
#include <ti/cc1352r7.dtsi>
#include "beagleconnect_freedom-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
#define BTN_GPIO_FLAGS (GPIO_ACTIVE_LOW | GPIO_PULL_UP)
/ {
model = "BeagleConnect Freedom";
compatible = "beagle,beagleconnect-freedom";
aliases {
l... | /content/code_sandbox/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,589 |
```restructuredtext
.. _boards-phytec:
PHYTEC
######
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/phytec/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
# ARM Options
CONFIG_AARCH64_IMAGE_HEADER=y
CONFIG_ARMV8_A_NS=y
CONFIG_ARM64_VA_BITS_36=y
CONFIG_ARM64_PA_BITS_36=y
# Cache Options
CONFIG_CACHE_MANAGEMENT=y
CONFIG_DCACHE_LINE_SIZE_DETECT=y
CONFIG_ICACHE_LINE_SIZE_DETECT=y
# Platform Configuration
# Zephyr Kernel Configuration
CONFIG_XIP=n
# Serial Dri... | /content/code_sandbox/boards/phytec/phyboard_lyra/phyboard_lyra_am6234_a53_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 111 |
```cmake
# PHYTEC phyBOARD-Lyra AM62x M4/A53
#
#
if(CONFIG_SOC_AM6234_M4)
board_runner_args(openocd "--no-init" "--no-halt" "--no-targets" "--gdb-client-port=3339")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
endif()
``` | /content/code_sandbox/boards/phytec/phyboard_lyra/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 79 |
```restructuredtext
.. _beagleconnect_freedom:
BeagleConnect Freedom
#####################
Overview
********
BeagleBoard.org BeagleConnect Freedom is a wireless
Internet of Things board based on the SimpleLink multi-Standard CC1352P7 wireless MCU.
.. figure:: img/beagleconnect_freedom.webp
:align: center
:wi... | /content/code_sandbox/boards/beagle/beagleconnect_freedom/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,449 |
```yaml
identifier: phyboard_lyra/am6234/m4
name: PHYTEC phyBOARD-Lyra AM62x M4
type: mcu
arch: arm
toolchain:
- zephyr
ram: 192
vendor: phytec
``` | /content/code_sandbox/boards/phytec/phyboard_lyra/phyboard_lyra_am6234_m4.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```unknown
# PHYTEC phyBOARD-Lyra AM62x M4/A53
#
#
config BOARD_PHYBOARD_LYRA
select SOC_AM6234_A53 if BOARD_PHYBOARD_LYRA_AM6234_A53
select SOC_AM6234_M4 if BOARD_PHYBOARD_LYRA_AM6234_M4
help
PHYTEC phyBOARD-Lyra AM62x M4/A53
``` | /content/code_sandbox/boards/phytec/phyboard_lyra/Kconfig.phyboard_lyra | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 87 |
```yaml
board:
name: phyboard_lyra
vendor: phytec
socs:
- name: am6234
``` | /content/code_sandbox/boards/phytec/phyboard_lyra/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 29 |
```yaml
identifier: phyboard_lyra/am6234/a53
name: PHYTEC phyBOARD-Lyra AM62x A53
type: mcu
arch: arm64
toolchain:
- zephyr
- cross-compile
ram: 1024
testing:
ignore_tags:
- net
- bluetooth
vendor: phytec
``` | /content/code_sandbox/boards/phytec/phyboard_lyra/phyboard_lyra_am6234_a53.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 79 |
```unknown
/*
*
*/
/dts-v1/;
#include <ti/ti_am6234_a53.dtsi>
/ {
model = "PHYTEC phyBOARD-Lyra AM62x A53";
compatible = "phytec,phyboard-lyra-am62xx-a53", "ti,am625";
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sram = &ddr0;
};
cpus {
cpu@0 {
status = "okay";
};
cpu@... | /content/code_sandbox/boards/phytec/phyboard_lyra/phyboard_lyra_am6234_a53.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 341 |
```unknown
# PHYTEC phyBOARD-Lyra AM62x M4
#
# Author: Daniel Schultz <d.schultz@phytec.de>
#
# Platform Configuration
CONFIG_CORTEX_M_SYSTICK=y
# Zephyr Kernel Configuration
CONFIG_XIP=n
# Enable Pinctrl
CONFIG_PINCTRL=y
# Serial Driver
CONFIG_SERIAL=y
# GPIO Driver
CONFIG_GPIO=y
# Enable Console
CONFIG_CONSOLE=... | /content/code_sandbox/boards/phytec/phyboard_lyra/phyboard_lyra_am6234_m4_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 98 |
```unknown
/*
* Author: Daniel Schultz <d.schultz@phytec.de>
*
*/
/dts-v1/;
#include <ti/am62x_m4.dtsi>
/ {
model = "PHYTEC phyBOARD-Lyra AM62x M4";
compatible = "phytec,phyboard-lyra-am62xx-m4", "ti,am625";
chosen {
zephyr,sram = &sram0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sra... | /content/code_sandbox/boards/phytec/phyboard_lyra/phyboard_lyra_am6234_m4.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 498 |
```ini
# PHYTEC phyBOARD-Lyra AM62x M4/A53
#
#
source [find board/ti_am625evm.cfg]
``` | /content/code_sandbox/boards/phytec/phyboard_lyra/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```restructuredtext
.. _phyboard_lyra_am62xx_a53:
phyBOARD-Lyra AM62x A53 Core
############################
Overview
********
PHYTEC phyBOARD-Lyra AM62x board is based on TI Sitara applications
processor, composed of a quad Cortex-A53 cluster and a single Cortex-M4 core.
Zephyr OS is ported to run on the Cortex-A53 ... | /content/code_sandbox/boards/phytec/phyboard_lyra/doc/phyboard_lyra_am62xx_a53.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 737 |
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