text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163
values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751
values | repo_full_name stringclasses 752
values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```unknown
/*
*/
&pinctrl {
uart0_default: uart0_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 6)>,
<NRF_PSEL(UART_RX, 0, 8)>,
<NRF_PSEL(UART_RTS, 0, 5)>,
<NRF_PSEL(UART_CTS, 0, 7)>;
};
};
uart0_sleep: uart0_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 6)>,
<NRF_PSEL(UART_RX, 0, 8... | /content/code_sandbox/boards/ezurio/bl654_sensor_board/bl654_sensor_board-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 408 |
```cmake
board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000")
board_runner_args(nrfjprog "--softreset")
board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
include(${ZEPHYR_BASE... | /content/code_sandbox/boards/ezurio/bl654_sensor_board/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 104 |
```yaml
identifier: bl654_sensor_board
name: BL654_Sensor_Board
type: mcu
arch: arm
ram: 256
flash: 1024
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- adc
- ble
- counter
- gpio
- i2c
- pwm
- watchdog
- netif:openthread
vendor: ezurio
``` | /content/code_sandbox/boards/ezurio/bl654_sensor_board/bl654_sensor_board.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 105 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable GPIO
CONFIG_GPIO=y
# Enable uart driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# 32KHz clock source
CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y
CONFIG_CLOCK_CONTROL_NRF_K32SRC_150PPM=y
``` | /content/code_sandbox/boards/ezurio/bl654_sensor_board/bl654_sensor_board_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 77 |
```unknown
# BL654 Sensor Board configuration
config BOARD_BL654_SENSOR_BOARD
select SOC_NRF52840_QIAA
``` | /content/code_sandbox/boards/ezurio/bl654_sensor_board/Kconfig.bl654_sensor_board | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 25 |
```cmake
# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
# - power@40000000 & clock@40000000 & bprot@40000000
# - acl@4001e000 & flash-controller@4001e000
list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")
``` | /content/code_sandbox/boards/ezurio/bl654_sensor_board/pre_dt_board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 72 |
```yaml
board:
name: bl654_sensor_board
vendor: ezurio
socs:
- name: nrf52840
``` | /content/code_sandbox/boards/ezurio/bl654_sensor_board/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 31 |
```unknown
# BL654 Sensor Board configuration
if BOARD_BL654_SENSOR_BOARD
config BT_CTLR
default BT
endif # BOARD_BL654_SENSOR_BOARD
``` | /content/code_sandbox/boards/ezurio/bl654_sensor_board/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 31 |
```restructuredtext
.. _mg100:
Ezurio Sentrius MG100 Gateway
##############################
Overview
********
The Sentrius MG100 Gateway offers a compact, out of box Bluetooth to low power cellular gateway
solution.
Based on the Pinnacle 100 socket modem, the Sentrius MG100 gateway captures data from any
Bluetooth 5... | /content/code_sandbox/boards/ezurio/mg100/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,957 |
```unknown
/*
*
*/
/dts-v1/;
#include <nordic/nrf52840_qiaa.dtsi>
#include "bl654_sensor_board-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "Ezurio BL654 Sensor Board";
compatible = "ezurio,bl654-sensor-board";
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0... | /content/code_sandbox/boards/ezurio/bl654_sensor_board/bl654_sensor_board.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 964 |
```cmake
board_runner_args(nrfjprog "--softreset")
board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/ezurio/bl654_dvk/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 67 |
```unknown
# BL654 DVK board configuration
config BOARD_BL654_DVK
select SOC_NRF52840_QIAA
``` | /content/code_sandbox/boards/ezurio/bl654_dvk/Kconfig.bl654_dvk | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 26 |
```unknown
/*
*/
&pinctrl {
uart0_default: uart0_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 6)>,
<NRF_PSEL(UART_RX, 0, 8)>,
<NRF_PSEL(UART_RTS, 0, 5)>,
<NRF_PSEL(UART_CTS, 0, 7)>;
};
};
uart0_sleep: uart0_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 6)>,
<NRF_PSEL(UART_RX, 0, 8... | /content/code_sandbox/boards/ezurio/bl654_dvk/bl654_dvk-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 724 |
```restructuredtext
.. _bl654_sensor_board:
Ezurio BL654 Sensor Board
#########################
Overview
********
The BL654 Sensor Board hardware provides support for the Ezurio
BL654 module which is powered by a Nordic Semiconductor nRF52840 ARM
Cortex-M4F CPU.
This sensor board has the following features:
* :abb... | /content/code_sandbox/boards/ezurio/bl654_sensor_board/doc/bl654_sensor_board.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,289 |
```yaml
identifier: bl654_dvk
name: BL654_DVK
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- adc
- usb_device
- ble
- pwm
- watchdog
vendor: ezurio
``` | /content/code_sandbox/boards/ezurio/bl654_dvk/bl654_dvk.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 74 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable RTT
CONFIG_USE_SEGGER_RTT=y
# enable GPIO
CONFIG_GPIO=y
# enable uart driver
CONFIG_SERIAL=y
# enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_RTT_CONSOLE=y
# 32kHz clock source
CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y
CONFIG_CLOCK_CONTROL_NRF_K32SRC_500... | /content/code_sandbox/boards/ezurio/bl654_dvk/bl654_dvk_nrf52840_pa_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 93 |
```unknown
/*
*
*/
/dts-v1/;
#include <nordic/nrf52840_qiaa.dtsi>
#include "bl654_dvk-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "Ezurio BL654 Dev Kit";
compatible = "ezurio,bl654_dvk";
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,uart-mcumgr ... | /content/code_sandbox/boards/ezurio/bl654_dvk/bl654_dvk.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,634 |
```yaml
identifier: bl654_dvk/nrf52840/pa
name: BL654_DVK_NRF52840_PA
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- adc
- usb_device
- ble
- pwm
- watchdog
vendor: ezurio
``` | /content/code_sandbox/boards/ezurio/bl654_dvk/bl654_dvk_nrf52840_pa.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 85 |
```yaml
board:
name: bl654_dvk
vendor: ezurio
socs:
- name: nrf52840
variants:
- name: pa
``` | /content/code_sandbox/boards/ezurio/bl654_dvk/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 40 |
```cmake
# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
# - power@40000000 & clock@40000000 & bprot@40000000
# - acl@4001e000 & flash-controller@4001e000
list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")
``` | /content/code_sandbox/boards/ezurio/bl654_dvk/pre_dt_board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 72 |
```unknown
# BL654 DVK board configuration
if BOARD_BL654_DVK
config BT_CTLR
default BT
if DAC
config I2C
default y
endif # DAC
endif # BOARD_BL654_DVK
if BOARD_BL654_DVK_NRF52840_PA
# Limit max power for FCC compliance with power amplifier
choice BT_CTLR_TX_PWR
default BT_CTLR_TX_PWR_MINUS_4
endchoice
end... | /content/code_sandbox/boards/ezurio/bl654_dvk/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 103 |
```unknown
/*
*
*/
#include "bl654_dvk.dts"
/ {
/* Information from Nordic SDK-Based Application Development and SKY66112 datasheet */
sky66112_fem: fem {
compatible = "generic-fem-two-ctrl-pins";
ctx-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
crx-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
ctx-settle-time-us = <23>;
... | /content/code_sandbox/boards/ezurio/bl654_dvk/bl654_dvk_nrf52840_pa.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 144 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable RTT
CONFIG_USE_SEGGER_RTT=y
# enable GPIO
CONFIG_GPIO=y
# enable uart driver
CONFIG_SERIAL=y
# enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_RTT_CONSOLE=y
# 32kHz clock source
CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y
CONFIG_CLOCK_CONTROL_NRF_K32SRC_500... | /content/code_sandbox/boards/ezurio/bl654_dvk/bl654_dvk_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 93 |
```cmake
board_runner_args(nrfjprog "--softreset")
board_runner_args(jlink "--device=nRF52832_xxAA" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/ezurio/bl652_dvk/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 67 |
```unknown
# BL652 DVK board configuration
config BOARD_BL652_DVK
select SOC_NRF52832_QFAA
``` | /content/code_sandbox/boards/ezurio/bl652_dvk/Kconfig.bl652_dvk | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 26 |
```yaml
identifier: bl652_dvk
name: bl652_dvk
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 64
flash: 512
supported:
- adc
- nvs
- i2c
- pwm
- spi
- watchdog
vendor: ezurio
``` | /content/code_sandbox/boards/ezurio/bl652_dvk/bl652_dvk.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 90 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable RTT
CONFIG_USE_SEGGER_RTT=y
# enable GPIO
CONFIG_GPIO=y
# enable uart driver
CONFIG_SERIAL=y
# enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_RTT_CONSOLE=y
# 32kHz clock source
CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y
CONFIG_CLOCK_CONTROL_NRF_K32SRC_500... | /content/code_sandbox/boards/ezurio/bl652_dvk/bl652_dvk_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 93 |
```unknown
/*
*/
&pinctrl {
uart0_default: uart0_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 6)>,
<NRF_PSEL(UART_RX, 0, 8)>,
<NRF_PSEL(UART_RTS, 0, 5)>,
<NRF_PSEL(UART_CTS, 0, 7)>;
};
};
uart0_sleep: uart0_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 6)>,
<NRF_PSEL(UART_RX, 0, 8... | /content/code_sandbox/boards/ezurio/bl652_dvk/bl652_dvk-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 724 |
```cmake
# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
# - power@40000000 & clock@40000000 & bprot@40000000
# - acl@4001e000 & flash-controller@4001e000
list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")
``` | /content/code_sandbox/boards/ezurio/bl652_dvk/pre_dt_board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 72 |
```restructuredtext
.. _bl654_dvk:
Ezurio BL654 DVK
################
Overview
********
The BL654 Development Kit hardware provides
support for the Ezurio BL654 module powered by a Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU.
It is also pin compatible with the BL654PA which adds a power amplifier. The "pa" vari... | /content/code_sandbox/boards/ezurio/bl654_dvk/doc/bl654_dvk.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,484 |
```yaml
board:
name: bl652_dvk
vendor: ezurio
socs:
- name: nrf52832
``` | /content/code_sandbox/boards/ezurio/bl652_dvk/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 31 |
```unknown
# BL652 DVK board configuration
if BOARD_BL652_DVK
config BT_CTLR
default BT
if DAC
config I2C
default y
endif # DAC
endif # BOARD_BL652_DVK
``` | /content/code_sandbox/boards/ezurio/bl652_dvk/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 47 |
```unknown
/*
*
*/
/dts-v1/;
#include <nordic/nrf52832_qfaa.dtsi>
#include "bl652_dvk-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "Ezurio BL652 DVK";
compatible = "ezurio,bl652_dvk";
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,uart-mcumgr = &u... | /content/code_sandbox/boards/ezurio/bl652_dvk/bl652_dvk.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,195 |
```cmake
board_runner_args(nrfjprog "--softreset")
board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000")
board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000")
include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE... | /content/code_sandbox/boards/ezurio/pinnacle_100_dvk/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 104 |
```unknown
# Pinnacle(TM) 100 DVK board configuration
#
config BOARD_PINNACLE_100_DVK
bool
default y
select SOC_NRF52840_QIAA
``` | /content/code_sandbox/boards/ezurio/pinnacle_100_dvk/Kconfig.pinnacle_100_dvk | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 40 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable RTT
CONFIG_USE_SEGGER_RTT=y
# Enable GPIO
CONFIG_GPIO=y
# Enable uart driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# 32KHz clock source
CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y
CONFIG_CLOCK_CONTROL_NRF_K32SRC_150PPM=y
``` | /content/code_sandbox/boards/ezurio/pinnacle_100_dvk/pinnacle_100_dvk_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 90 |
```cmake
# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
# - power@40000000 & clock@40000000 & bprot@40000000
# - acl@4001e000 & flash-controller@4001e000
list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")
``` | /content/code_sandbox/boards/ezurio/pinnacle_100_dvk/pre_dt_board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 72 |
```yaml
identifier: pinnacle_100_dvk
name: pinnacle-100-dvk
type: mcu
arch: arm
ram: 256
flash: 1024
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- adc
- ble
- counter
- gpio
- i2c
- pwm
- spi
- usb_device
- watchdog
- netif:modem
vendor: ezurio
``` | /content/code_sandbox/boards/ezurio/pinnacle_100_dvk/pinnacle_100_dvk.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 113 |
```yaml
board:
name: pinnacle_100_dvk
vendor: ezurio
socs:
- name: nrf52840
``` | /content/code_sandbox/boards/ezurio/pinnacle_100_dvk/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
/*
*/
&pinctrl {
uart0_default: uart0_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 6)>,
<NRF_PSEL(UART_RX, 0, 8)>,
<NRF_PSEL(UART_RTS, 0, 5)>,
<NRF_PSEL(UART_CTS, 0, 7)>;
};
};
uart0_sleep: uart0_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 6)>,
<NRF_PSEL(UART_RX, 0, 8... | /content/code_sandbox/boards/ezurio/pinnacle_100_dvk/pinnacle_100_dvk-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,090 |
```restructuredtext
.. _bl652_dvk:
Ezurio BL652 DVK
################
Overview
********
The BL652 Development Kit hardware provides
support for the Ezurio BL652 module powered by a Nordic Semiconductor nRF52832 ARM Cortex-M4F CPU.
This development kit has the following features:
* :abbr:`ADC (Analog to Digital Conv... | /content/code_sandbox/boards/ezurio/bl652_dvk/doc/bl652_dvk.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,219 |
```unknown
# Pinnacle(TM) 100 DVK board configuration
if BOARD_PINNACLE_100_DVK
config MODEM
default NETWORKING
config MODEM_HL7800
default NETWORKING
config NORDIC_QSPI_NOR
default BOOTLOADER_MCUBOOT
config NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE
default 4096 if NORDIC_QSPI_NOR
config BT_CTLR
default BT
en... | /content/code_sandbox/boards/ezurio/pinnacle_100_dvk/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 105 |
```unknown
/*
*
*/
/dts-v1/;
#include <nordic/nrf52840_qiaa.dtsi>
#include "pinnacle_100_dvk-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "Pinnacle 100 Dev Kit";
compatible = "ezurio,pinnacle-100-dvk";
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephy... | /content/code_sandbox/boards/ezurio/pinnacle_100_dvk/pinnacle_100_dvk.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,921 |
```unknown
/*
*
*/
#include <nordic/nrf5340_cpunet_qkaa.dtsi>
&gpiote {
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&timer0 {
status = "okay";
};
&timer1 {
status = "okay";
};
&timer2 {
status = "okay";
};
&flash1 {
/*
* For more information, see:
* path_to_url#fla... | /content/code_sandbox/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_common.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 341 |
```yaml
identifier: bl5340_dvk/nrf5340/cpuapp
name: BL5340-DVK-application-MCU
type: mcu
arch: arm
toolchain:
- gnuarmemb
- xtools
- zephyr
ram: 448
flash: 1024
supported:
- counter
- gpio
- i2c
- pwm
- qspi
- spi
- uart
- usb_device
- watchdog
vendor: ezurio
``` | /content/code_sandbox/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 115 |
```cmake
if(CONFIG_BOARD_BL5340_DVK_NRF5340_CPUAPP_NS)
set(TFM_PUBLIC_KEY_FORMAT "full")
endif()
if(CONFIG_BOARD_BL5340_DVK_NRF5340_CPUAPP OR CONFIG_BOARD_BL5340_DVK_NRF5340_CPUAPP_NS)
board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000")
elseif(BOARD_BL5340_DVK_NRF5340_CPUNET)
board_runner_args(j... | /content/code_sandbox/boards/ezurio/bl5340_dvk/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 201 |
```restructuredtext
.. _pinnacle_100_dvk:
Ezurio Pinnacle 100 DVK
#######################
Overview
********
The Pinnacle 100 cellular modem seamlessly incorporates a powerful Cortex M4F
controller, full Bluetooth 5 and LTE-M/NB-IoT capabilities all with full
regulatory certifications and LTE carrier approvals. The P... | /content/code_sandbox/boards/ezurio/pinnacle_100_dvk/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,835 |
```unknown
/*
*
*/
/*
* Default Flash planning for bl5340_dvk CPUAPP (Application MCU).
*
* Zephyr build for BL5340 with ARM TrustZone-M support
* implies building Secure and Non-Secure Zephyr images.
*
* Secure image will be placed, by default, in flash0
* (or in slot0, if MCUboot is present).
* Secure imag... | /content/code_sandbox/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 412 |
```unknown
/*
*
*/
/* Default shared SRAM planning when building for BL5340 DVK.
* This file is included by both nRF5340 CPUAPP (Application MCU)
* and nRF5340 CPUNET (Network MCU).
* - 64 kB SRAM allocated as Shared memory (sram0_shared)
* - Region defined after the image SRAM of Application MCU
*/
/ {
chose... | /content/code_sandbox/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_shared_sram_planning_conf.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 185 |
```yaml
identifier: bl5340_dvk/nrf5340/cpunet
name: BL5340-DVK-network-MCU
type: mcu
arch: arm
toolchain:
- gnuarmemb
- xtools
- zephyr
ram: 64
flash: 256
supported:
- counter
- gpio
- i2c
- spi
- uart
- watchdog
vendor: ezurio
``` | /content/code_sandbox/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 101 |
```unknown
# BL5340-DVK board configuration
config BOARD_BL5340_DVK
select SOC_NRF5340_CPUAPP_QKAA if BOARD_BL5340_DVK_NRF5340_CPUAPP
select SOC_NRF5340_CPUAPP_QKAA if BOARD_BL5340_DVK_NRF5340_CPUAPP_NS
select SOC_NRF5340_CPUNET_QKAA if BOARD_BL5340_DVK_NRF5340_CPUNET
``` | /content/code_sandbox/boards/ezurio/bl5340_dvk/Kconfig.bl5340_dvk | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 94 |
```yaml
identifier: bl5340_dvk/nrf5340/cpuapp/ns
name: BL5340-DVK-application-MCU-Non-Secure
type: mcu
arch: arm
toolchain:
- gnuarmemb
- xtools
- zephyr
ram: 192
flash: 192
supported:
- counter
- gpio
- i2c
- pwm
- spi
- uart
- usb_device
- watchdog
vendor: ezurio
``` | /content/code_sandbox/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 114 |
```cmake
# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
# - flash-controller@39000 & kmu@39000
# - power@5000 & clock@5000
# - /reserved-memory/image@20000000 & /reserved-memory/image_s@20000000
list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")
``` | /content/code_sandbox/boards/ezurio/bl5340_dvk/pre_dt_board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable TrustZone-M
CONFIG_ARM_TRUSTZONE_M=y
# This board implies building Non-Secure firmware
CONFIG_TRUSTED_EXECUTION_NONSECURE=y
# Enable GPIO
CONFIG_GPIO=y
# Enable UART driver
CONFIG_SERIAL=y
# Enable c... | /content/code_sandbox/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 90 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable TrustZone-M
CONFIG_ARM_TRUSTZONE_M=y
# Enable GPIO
CONFIG_GPIO=y
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Setup clocks
CONFIG_CLOCK_CONTROL_NRF_K... | /content/code_sandbox/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 121 |
```yaml
board:
name: bl5340_dvk
vendor: ezurio
socs:
- name: 'nrf5340'
variants:
- name: 'ns'
cpucluster: 'cpuapp'
``` | /content/code_sandbox/boards/ezurio/bl5340_dvk/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```unknown
/*
*
*/
/dts-v1/;
#include <nordic/nrf5340_cpuappns_qkaa.dtsi>
#include "bl5340_dvk_nrf5340_cpuapp_common.dtsi"
/ {
model = "Ezurio BL5340 (nRF5340) Application";
compatible = "ezurio,bl5340-dvk-cpuapp";
chosen {
zephyr,sram = &sram0_ns;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_ns... | /content/code_sandbox/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 157 |
```unknown
/*
*
*/
#include "bl5340_dvk_nrf5340_cpuapp_common-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,uart-mcumgr = &uart0;
zephyr,bt-mon-uart = &uart0;
zephyr,bt-c2h-uart = &uart0;
zephyr,display = &i... | /content/code_sandbox/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,930 |
```unknown
/*
*/
&pinctrl {
i2c1_default: i2c1_default {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 1, 2)>,
<NRF_PSEL(TWIM_SCL, 1, 3)>;
};
};
i2c1_sleep: i2c1_sleep {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 1, 2)>,
<NRF_PSEL(TWIM_SCL, 1, 3)>;
low-power-enable;
};
};
spi2_default: spi2_default {... | /content/code_sandbox/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,342 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable GPIO
CONFIG_GPIO=y
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
``` | /content/code_sandbox/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```unknown
# BL5340-DVK board configuration
if BOARD_BL5340_DVK_NRF5340_CPUAPP || BOARD_BL5340_DVK_NRF5340_CPUAPP_NS
config DOMAIN_CPUNET_BOARD
string
default "bl5340_dvk/nrf5340/cpunet"
help
The board which will be used for CPUNET domain when creating a multi
image application where one or more images shou... | /content/code_sandbox/boards/ezurio/bl5340_dvk/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 232 |
```unknown
/*
*
*/
/dts-v1/;
#include <nordic/nrf5340_cpuapp_qkaa.dtsi>
#include "bl5340_dvk_nrf5340_cpuapp_common.dtsi"
/ {
model = "Ezurio BL5340 (nRF5340) Application";
compatible = "ezurio,bl5340-dvk-cpuapp";
chosen {
zephyr,sram = &sram0_image;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_p... | /content/code_sandbox/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 190 |
```unknown
/*
*/
&pinctrl {
uart0_default: uart0_default {
group1 {
psels = <NRF_PSEL(UART_TX, 1, 8)>,
<NRF_PSEL(UART_RX, 1, 10)>,
<NRF_PSEL(UART_RTS, 1, 7)>,
<NRF_PSEL(UART_CTS, 1, 9)>;
};
};
uart0_sleep: uart0_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 1, 8)>,
<NRF_PSEL(UART_RX, 1, ... | /content/code_sandbox/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 196 |
```unknown
# BL5340-DVK board configuration
if BOARD_BL5340_DVK_NRF5340_CPUAPP || BOARD_BL5340_DVK_NRF5340_CPUAPP_NS
config I2C
default GPIO || DAC
# Code Partition:
#
# For the secure version of the board the firmware is linked at the beginning
# of the flash, or into the code-partition defined in DT if it is int... | /content/code_sandbox/boards/ezurio/bl5340_dvk/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 795 |
```unknown
/*
*
*/
/dts-v1/;
#include <nordic/nrf5340_cpunet_qkaa.dtsi>
#include "bl5340_dvk_nrf5340_cpunet-pinctrl.dtsi"
#include "bl5340_dvk_nrf5340_cpunet_common.dtsi"
/ {
model = "Ezurio BL5340 (nRF5340) Network";
compatible = "ezurio,bl5340-dvk-cpunet";
chosen {
zephyr,console = &uart0;
zephyr,shell-ua... | /content/code_sandbox/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 299 |
```restructuredtext
.. _boards-digilent:
Digilent, Inc.
##############
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/digilent/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```yaml
identifier: arty_a7/designstart_fpga_cortex_m1
name: Digilent Arty A7 ARM DesignStart Cortex-M1
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 32
flash: 64
supported:
- flash
- spi
- gpio
``` | /content/code_sandbox/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m1.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 85 |
```cmake
if(CONFIG_BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M1)
board_runner_args(openocd "--use-elf" "--config=${BOARD_DIR}/support/openocd_arty_a7_arm_designstart_m1.cfg")
board_runner_args(jlink "--device=Cortex-M1" "--reset-after-load")
elseif(CONFIG_BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M3)
board_runner_args(o... | /content/code_sandbox/boards/digilent/arty_a7/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 173 |
```unknown
/*
*
*/
/dts-v1/;
#include <arm/armv7-m.dtsi>
#include "arty_a7_arm_designstart.dtsi"
/ {
model = "Digilent Arty A7 ARM DesignStart Cortex-M3";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m3";
reg = <0>;
#address-cells ... | /content/code_sandbox/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m3.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 354 |
```unknown
# Digilent Arty board configuration
config BOARD_ARTY_A7
select SOC_DESIGNSTART_FPGA_CORTEX_M1 if BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M1
select SOC_DESIGNSTART_FPGA_CORTEX_M3 if BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M3
``` | /content/code_sandbox/boards/digilent/arty_a7/Kconfig.arty_a7 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 70 |
```yaml
identifier: arty_a7/designstart_fpga_cortex_m3
name: Digilent Arty A7 ARM DesignStart Cortex-M3
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 32
flash: 32
supported:
- flash
- spi
- gpio
``` | /content/code_sandbox/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m3.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 85 |
```c
/*
*
*/
#include <cmsis_core.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/init.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(board, CONFIG_LOG_DEFAULT_LEVEL);
#include "board.h"
#define DAPLINK_QSPI_MUX_NODE DT_NODELABEL(daplink_qspi_m... | /content/code_sandbox/boards/digilent/arty_a7/board.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 514 |
```unknown
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
``` | /content/code_sandbox/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m1_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```yaml
board:
name: arty_a7
vendor: digilent
socs:
- name: designstart_fpga_cortex_m1
- name: designstart_fpga_cortex_m3
``` | /content/code_sandbox/boards/digilent/arty_a7/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 47 |
```objective-c
/*
*
*/
#ifndef __INC_BOARD_H
#define __INC_BOARD_H
enum board_daplink_qspi_mux_mode {
/* eXecute-In-Place mode */
BOARD_DAPLINK_QSPI_MUX_MODE_XIP,
/* Normal mode */
BOARD_DAPLINK_QSPI_MUX_MODE_NORMAL,
};
/**
* @brief Select the mode of the DAPlink QSPI multiplexer.
*
* Note: The multiplexer ... | /content/code_sandbox/boards/digilent/arty_a7/board.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 246 |
```unknown
/*
*
*/
/dts-v1/;
#include <arm/armv6-m.dtsi>
#include "arty_a7_arm_designstart.dtsi"
/ {
model = "Digilent Arty A7 ARM DesignStart Cortex-M1";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m1";
reg = <0>;
#address-cells ... | /content/code_sandbox/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m1.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 310 |
```unknown
# Digilent Arty board configuration
if BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M1 || BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M3
config CPU_CORTEX_M_HAS_SYSTICK
default y
config CPU_HAS_ARM_MPU
default y if BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M3
config NUM_IRQS
default 7
config GPIO
default y if "$(dt... | /content/code_sandbox/boards/digilent/arty_a7/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 138 |
```restructuredtext
.. _bl5340_dvk:
Ezurio BL5340 DVK
#################
Overview
********
The BL5340 Development Kit provides support for the Ezurio
BL5340 module which is powered by a dual-core Nordic Semiconductor
nRF5340 ARM Cortex-M33F CPU. The nRF5340 inside the BL5340 module is a
dual-core SoC based on the Arm ... | /content/code_sandbox/boards/ezurio/bl5340_dvk/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,816 |
```unknown
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=50000000
CONFIG_ARM_MPU=y
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
``` | /content/code_sandbox/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m3_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 42 |
```unknown
# Digilent Arty board configuration
config BOARD_INIT_PRIORITY
int "Board initialization priority"
default 50
depends on BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M1 || BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M3
depends on "$(dt_nodelabel_enabled,daplink_qspi_mux)"
help
Board initialization priority. The... | /content/code_sandbox/boards/digilent/arty_a7/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 95 |
```yaml
description: ARM DesignStart FPGA DAPLink QSPI bus multiplexer
compatible: "arm,daplink-qspi-mux"
include: base.yaml
properties:
interrupts:
required: true
description: |
IRQ line connected to the level-detect non-interrupt DAPLink shield
fitted signal
mux-gpios:
type: phandle-a... | /content/code_sandbox/boards/digilent/arty_a7/dts/bindings/arm,daplink-qspi-mux.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 104 |
```ini
source [find interface/cmsis-dap.cfg]
source [find target/swj-dp.tcl]
adapter speed 5000
set _CHIPNAME cortex_m3
set _ENDIAN little
set _WORKAREASIZE 0x4000
set _CPUTAPID 0x412FC231
source [find openocd_arty_a7_arm_designstart.cfg]
``` | /content/code_sandbox/boards/digilent/arty_a7/support/openocd_arty_a7_arm_designstart_m3.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 82 |
```ini
swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
if {![using_hla]... | /content/code_sandbox/boards/digilent/arty_a7/support/openocd_arty_a7_arm_designstart.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 107 |
```ini
source [find interface/cmsis-dap.cfg]
source [find target/swj-dp.tcl]
adapter speed 5000
set _CHIPNAME cortex_m1
set _ENDIAN little
set _WORKAREASIZE 0x4000
set _CPUTAPID 0x411CC210
source [find openocd_arty_a7_arm_designstart.cfg]
``` | /content/code_sandbox/boards/digilent/arty_a7/support/openocd_arty_a7_arm_designstart_m1.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 82 |
```unknown
/*
*
*/
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <mem.h>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
chosen {
zephyr,console = &uartlite0;
zephyr,shell-uart = &uartlite0;
zephyr,flash = &itcm;
/* Use DTCM as SRAM by default */
zephyr,sram = &dtcm;
};
aliases {
le... | /content/code_sandbox/boards/digilent/arty_a7/dts/arty_a7_arm_designstart.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,566 |
```yaml
identifier: zybo
name: Digilent Zybo
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 524288
supported:
- gpio
vendor: digilent
``` | /content/code_sandbox/boards/digilent/zybo/zybo.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 62 |
```restructuredtext
.. _arty:
Digilent Arty
#############
Overview
********
The `Digilent Arty`_ is a line of FPGA-based development boards aimed for makers
and hobbyists. The Arty is available in several configurations, each with a
different Xilinx FPGA (Spartan-7, Artix-7, or Zynq-7000 series).
Each board is equi... | /content/code_sandbox/boards/digilent/arty_a7/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,889 |
```unknown
/*
*
*/
/dts-v1/;
#include <xilinx/zynq7000.dtsi>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include "zybo-pinctrl.dtsi"
/ {
model = "Digilent Zybo board";
compatible = "digilent,zynq-zybo", "xlnx,zynq-7000";
#address-cells = <1>;
#size-cells ... | /content/code_sandbox/boards/digilent/zybo/zybo.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 547 |
```cmake
board_runner_args(openocd "--use-elf" "--cmd-reset-halt" "halt")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
``` | /content/code_sandbox/boards/digilent/zybo/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 39 |
```unknown
/*
*
*/
#include <zephyr/dt-bindings/pinctrl/pinctrl-zynq.h>
&pinctrl0 {
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart1_10_grp";
function = "uart1";
};
conf {
groups = "uart1_10_grp";
slew-rate = <IO_SPEED_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx ... | /content/code_sandbox/boards/digilent/zybo/zybo-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 158 |
```unknown
# The GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
CONFIG_ARM_ARCH_TIMER=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=325000000
CONFIG_PINCTRL=y
CONFIG_SERIAL=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
``` | /content/code_sandbox/boards/digilent/zybo/zybo_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 65 |
```yaml
board:
name: zybo
vendor: digilent
socs:
- name: xc7z010
``` | /content/code_sandbox/boards/digilent/zybo/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 29 |
```unknown
# Digilent Zybo board configuration
config BOARD_ZYBO
select SOC_XILINX_XC7Z010
``` | /content/code_sandbox/boards/digilent/zybo/Kconfig.zybo | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 27 |
```ini
source [find interface/ftdi/digilent-hs1.cfg]
transport select jtag
source [find target/zynq_7000.cfg]
``` | /content/code_sandbox/boards/digilent/zybo/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```restructuredtext
.. _boards-alientek:
Alientek
########
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/alientek/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```cmake
board_runner_args(jlink "--device=STM32L475VE" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/alientek/pandora_stm32l475/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```yaml
board:
name: pandora_stm32l475
vendor: alientek
socs:
- name: stm32l475xx
``` | /content/code_sandbox/boards/alientek/pandora_stm32l475/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```yaml
identifier: pandora_stm32l475
name: STM32L475 Pandora
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 128
flash: 512
supported:
- gpio
- counter
``` | /content/code_sandbox/boards/alientek/pandora_stm32l475/pandora_stm32l475.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 69 |
```unknown
config BOARD_PANDORA_STM32L475
select SOC_STM32L475XX
``` | /content/code_sandbox/boards/alientek/pandora_stm32l475/Kconfig.pandora_stm32l475 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```restructuredtext
.. _zybo:
Digilent Zybo
#############
Overview
********
The `Digilent Zybo`_ (ZYnq BOard) is a feature-rich, ready-to-use embedded software and digital
circuit development board. It is built around the Xilinx Zynq-7000 family, which is based on the
Xilinx All Programmable System-on-Chip (AP SoC) ... | /content/code_sandbox/boards/digilent/zybo/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,215 |
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