text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```unknown
/*
*
*/
#include <zephyr/dt-bindings/display/panel.h>
/{
chosen {
zephyr,display = &lcdif;
};
en_mipi_display_rk055hdmipi4ma0: enable-mipi-display-rk055hdmipi4ma0 {
compatible = "regulator-fixed";
regulator-name = "en_mipi_display";
enable-gpios = <&nxp_mipi_connector 32 GPIO_ACTIVE_HIGH>;
regulator-boot-on;
};
lvgl_pointer {
compatible = "zephyr,lvgl-pointer-input";
input = <>911_rk055hdmipi4ma0>;
};
};
&nxp_mipi_i2c {
status = "okay";
gt911_rk055hdmipi4ma0: gt911-rk055hdmipi4ma0@5d {
compatible = "goodix,gt911";
reg = <0x5d>;
irq-gpios = <&nxp_mipi_connector 29 GPIO_ACTIVE_HIGH>;
reset-gpios = <&nxp_mipi_connector 28 GPIO_ACTIVE_LOW>;
};
};
&zephyr_lcdif {
status = "okay";
width = <720>;
height = <1280>;
display-timings {
compatible = "zephyr,panel-timing";
hsync-len = <6>;
hfront-porch = <12>;
hback-porch = <24>;
vsync-len = <2>;
vfront-porch = <16>;
vback-porch = <14>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
/*
* Pixel clock is given by the following formula:
* (height + vsync-len + vfront-porch + vback-porch) *
* (width + hsync-len + hfront-porch + hback-porch) * frame rate
*/
clock-frequency = <62346240>;
};
pixel-format = <PANEL_PIXEL_FORMAT_BGR_565>;
data-bus-width = "24-bit";
backlight-gpios = <&nxp_mipi_connector 0 GPIO_ACTIVE_HIGH>;
};
&zephyr_mipi_dsi {
status = "okay";
nxp,lcdif = <&lcdif>;
dpi-color-coding = "24-bit";
dpi-pixel-packet = "24-bit";
dpi-video-mode = "burst";
dpi-bllp-mode = "low-power";
autoinsert-eotp;
/*
* PHY clock is given by the following formula:
* (pixel clock * bits per pixel) / MIPI data lanes
*/
phy-clock = <748154880>;
hx8394-rk055hdmipi4ma0@0 {
status = "okay";
compatible = "himax,hx8394";
reg = <0x0>;
reset-gpios = <&nxp_mipi_connector 21 GPIO_ACTIVE_HIGH>;
data-lanes = <2>;
width = <720>;
height = <1280>;
pixel-format = <MIPI_DSI_PIXFMT_RGB565>;
};
};
``` | /content/code_sandbox/boards/shields/rk055hdmipi4ma0/rk055hdmipi4ma0.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 698 |
```restructuredtext
.. _rk055hdmipi4ma0:
RK055HDMIPI4MA0 MIPI Display
############################
Overview
********
The Rocktech RK055HDMIPI4MA0 MIPI Display is a 5.5 inch TFT 720x1280 pixels
panel with LED backlighting, full viewing angle, MIPI interface and
capacitive touch panel from Rocktech.
More information about the shield can be found
at the `RK055HDMIPI4MA0 product page`_.
This display uses a 40 pin FPC interface, which is available on many
NXP EVKs.
Pins Assignment of the Rocktech RK055HDMIPI4MA0 MIPI Display
============================================================
+-----------------------+------------------------+
| FPC Connector Pin | Function |
+=======================+========================+
| 1 | LED backlight cathode |
+-----------------------+------------------------+
| 21 | Controller reset |
+-----------------------+------------------------+
| 22 | Controller LPTE |
+-----------------------+------------------------+
| 26 | Touch ctrl I2C SDA |
+-----------------------+------------------------+
| 27 | Touch ctrl I2C SCL |
+-----------------------+------------------------+
| 28 | Touch ctrl reset |
+-----------------------+------------------------+
| 29 | Touch ctrl interrupt |
+-----------------------+------------------------+
| 32 | LCD power enable |
+-----------------------+------------------------+
| 34 | Backlight power enable |
+-----------------------+------------------------+
Requirements
************
This shield can only be used with a board which provides a configuration
for the 40 pin FPC interface
Programming
***********
Set ``--shield rk055hdmipi4ma0`` when you invoke ``west build``. For
example:
.. zephyr-app-commands::
:zephyr-app: samples/drivers/display
:board: mixmrt1170_evk_cm7
:shield: rk055hdmipi4ma0
:goals: build
References
**********
.. target-notes::
.. _RK055HDMIPI4MA0 product page:
path_to_url
``` | /content/code_sandbox/boards/shields/rk055hdmipi4ma0/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 471 |
```unknown
config SHIELD_ST7789V_TL019FQV01
def_bool $(shields_list_contains,st7789v_tl019fqv01)
config SHIELD_ST7789V_WAVESHARE_240X240
def_bool $(shields_list_contains,st7789v_waveshare_240x240)
``` | /content/code_sandbox/boards/shields/st7789v_generic/Kconfig.shield | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 70 |
```unknown
/*
*
*/
#include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
/ {
chosen {
zephyr,display = &st7789v_st7789v_tl019fqv01;
};
mipi_dbi_st7789v_tl019fqv01 {
compatible = "zephyr,mipi-dbi-spi";
spi-dev = <&arduino_spi>;
dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */
reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */
write-only;
#address-cells = <1>;
#size-cells = <0>;
st7789v_st7789v_tl019fqv01: st7789v@0 {
compatible = "sitronix,st7789v";
mipi-max-frequency = <20000000>;
reg = <0>;
width = <320>;
height = <170>;
x-offset = <0>;
y-offset = <35>;
vcom = <0x2b>;
gctrl = <0x35>;
vrhs = <0x0f>;
vdvs = <0x20>;
mdac = <0x60>;
gamma = <0x01>;
colmod = <0x55>;
lcm = <0x2c>;
porch-param = [0c 0c 00 33 33];
cmd2en-param = [5a 69 02 01];
pwctrl1-param = [52 a1];
pvgam-param = [D0 00 02 07 0B 1A 31 54 40 29 12 12 12 17];
nvgam-param = [D0 00 02 07 05 15 2D 44 44 1C 18 16 1C 1D];
ram-param = [00 F8];
rgb-param = [CD 08 14];
mipi-mode = <MIPI_DBI_MODE_SPI_4WIRE>;
};
};
};
&arduino_spi {
status = "okay";
cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */
};
``` | /content/code_sandbox/boards/shields/st7789v_generic/st7789v_tl019fqv01.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 506 |
```unknown
if SHIELD_ST7789V_TL019FQV01 || SHIELD_ST7789V_WAVESHARE_240X240
if DISPLAY
choice ST7789V_PIXEL_FORMAT
default ST7789V_RGB888 if SHIELD_ST7789V_TL019FQV01
default ST7789V_RGB565 if SHIELD_ST7789V_WAVESHARE_240X240
endchoice
if LVGL
config LV_Z_BITS_PER_PIXEL
default 24 if SHIELD_ST7789V_TL019FQV01
default 16 if SHIELD_ST7789V_WAVESHARE_240X240
choice LV_COLOR_DEPTH
default LV_COLOR_DEPTH_16 if SHIELD_ST7789V_WAVESHARE_240X240
endchoice
config LV_COLOR_16_SWAP
default y if SHIELD_ST7789V_WAVESHARE_240X240
endif # LVGL
endif # DISPLAY
endif # SHIELD_ST7789V_TL019FQV01 || SHIELD_ST7789V_WAVESHARE_240X240
``` | /content/code_sandbox/boards/shields/st7789v_generic/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 234 |
```unknown
/*
*
*/
#include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
/ {
chosen {
zephyr,display = &st7789v_st7789v_waveshare_240x240;
};
mipi_dbi_st7789v_waveshare_240x240 {
compatible = "zephyr,mipi-dbi-spi";
spi-dev = <&arduino_spi>;
dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */
reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */
write-only;
#address-cells = <1>;
#size-cells = <0>;
st7789v_st7789v_waveshare_240x240: st7789v@0 {
compatible = "sitronix,st7789v";
mipi-max-frequency = <20000000>;
reg = <0>;
width = <240>;
height = <240>;
x-offset = <0>;
y-offset = <0>;
vcom = <0x19>;
gctrl = <0x35>;
vrhs = <0x12>;
vdvs = <0x20>;
mdac = <0x00>;
gamma = <0x01>;
colmod = <0x05>;
lcm = <0x2c>;
porch-param = [0c 0c 00 33 33];
cmd2en-param = [5a 69 02 01];
pwctrl1-param = [a4 a1];
pvgam-param = [D0 04 0D 11 13 2B 3F 54 4C 18 0D 0B 1F 23];
nvgam-param = [D0 04 0C 11 13 2C 3F 44 51 2F 1F 1F 20 23];
ram-param = [00 F0];
rgb-param = [CD 08 14];
mipi-mode = <MIPI_DBI_MODE_SPI_4WIRE>;
};
};
};
&arduino_spi {
status = "okay";
cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */
};
``` | /content/code_sandbox/boards/shields/st7789v_generic/st7789v_waveshare_240x240.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 521 |
```unknown
config SHIELD_WAVESHARE_PICO_UPS_B
def_bool $(shields_list_contains,waveshare_pico_ups_b)
``` | /content/code_sandbox/boards/shields/waveshare_ups/Kconfig.shield | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
/*
*
*/
&pico_i2c1 {
waveshare_pico_ups: ina219@43 {
status = "okay";
compatible = "ti,ina219";
reg = <0x43>;
brng = <1>;
pg = <3>;
sadc = <12>;
badc = <12>;
shunt-milliohm = <100>;
lsb-microamp = <20>;
};
};
``` | /content/code_sandbox/boards/shields/waveshare_ups/waveshare_pico_ups_b.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 103 |
```unknown
/*
*
*/
&pinctrl {
i2c1_default: i2c1_default {
group1 {
bias-pull-up;
};
};
};
&pico_i2c1 {
status = "okay";
};
``` | /content/code_sandbox/boards/shields/waveshare_ups/boards/rpi_pico.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
```restructuredtext
.. _st7789v_generic:
Generic ST7789V Display Shield
##############################
Overview
********
This is a generic shield for display shields based on ST7789V display
controller. More information about the controller can be found in
`ST7789V Datasheet`_.
Pins Assignment of the Generic ST7789V Display Shield
=====================================================
+-----------------------+--------------------------------------------+
| Arduino Connector Pin | Function |
+=======================+===============+============================+
| D8 | ST7789V Reset | |
+-----------------------+---------------+----------------------------+
| D9 | ST7789V DC | (Data/Command) |
+-----------------------+---------------+----------------------------+
| D10 | SPI SS | (Serial Slave Select) |
+-----------------------+---------------+----------------------------+
| D11 | SPI MOSI | (Serial Data Input) |
+-----------------------+---------------+----------------------------+
| D12 | SPI MISO | (Serial Data Out) |
+-----------------------+---------------+----------------------------+
| D13 | SPI SCK | (Serial Clock Input) |
+-----------------------+---------------+----------------------------+
Current supported displays
==========================
+----------------------+------------------------------+
| Display | Shield Designation |
| | |
+======================+==============================+
| TL019FQV01 | st7789v_tl019fqv01 |
| | |
+----------------------+------------------------------+
| Waveshare 240x240 | st7789v_waveshare_240x240 |
| 1.3inch IPS LCD | |
+----------------------+------------------------------+
Requirements
************
This shield can only be used with a board that provides a configuration
for Arduino connectors and defines node aliases for SPI and GPIO interfaces
(see :ref:`shields` for more details).
Programming
***********
Set ``--shield st7789v_tl019fqv01`` when you invoke ``west build``. For example:
.. zephyr-app-commands::
:zephyr-app: samples/subsys/display/lvgl
:board: nrf52840dk/nrf52840
:shield: st7789v_tl019fqv01
:goals: build
References
**********
.. target-notes::
.. _ST7789V Datasheet:
path_to_url
``` | /content/code_sandbox/boards/shields/st7789v_generic/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 506 |
```unknown
config SHIELD_SEEED_XIAO_ROUND_DISPLAY
def_bool $(shields_list_contains,seeed_xiao_round_display)
``` | /content/code_sandbox/boards/shields/seeed_xiao_round_display/Kconfig.shield | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 29 |
```unknown
/*
*
*/
#include <freq.h>
#include <zephyr/dt-bindings/display/panel.h>
/ {
chosen {
zephyr,display = &gc9a01_xiao_round_display;
};
vbatt {
compatible = "voltage-divider";
io-channels = <&xiao_adc 0>;
output-ohms = <470000>;
full-ohms = <940000>;
};
lvgl_pointer {
compatible = "zephyr,lvgl-pointer-input";
input = <&chsc6x_xiao_round_display>;
};
aliases {
rtc = &pcf8563_xiao_round_display;
};
xiao_round_display_mipi_dbi {
compatible = "zephyr,mipi-dbi-spi";
spi-dev = <&xiao_spi>;
dc-gpios = <&xiao_d 3 GPIO_ACTIVE_HIGH>;
write-only;
#address-cells = <1>;
#size-cells = <0>;
gc9a01_xiao_round_display: gc9a01@0 {
status = "okay";
compatible = "galaxycore,gc9x01x";
reg = <0>;
mipi-max-frequency = <DT_FREQ_M(100)>;
pixel-format = <PANEL_PIXEL_FORMAT_RGB_565>;
width = <240>;
height = <240>;
display-inversion;
};
};
};
&xiao_adc {
status = "okay";
};
/*
* xiao_serial uses pins D6 and D7 of the Xiao, which are used respectively to
* control the screen backlight and as touch controller interrupt.
*/
&xiao_serial {
status = "disabled";
};
&xiao_i2c {
clock-frequency = < I2C_BITRATE_FAST >;
pcf8563_xiao_round_display: pcf8563@51 {
status = "okay";
compatible = "nxp,pcf8563";
reg = <0x51>;
};
chsc6x_xiao_round_display: chsc6x@2e {
status = "okay";
compatible = "chipsemi,chsc6x";
reg = <0x2e>;
irq-gpios = <&xiao_d 7 GPIO_ACTIVE_LOW>;
};
};
&xiao_spi {
status = "okay";
cs-gpios = <&xiao_d 1 GPIO_ACTIVE_LOW>, <&xiao_d 2 GPIO_ACTIVE_LOW>;
sdhc_xiao_round_display: sdhc@1 {
compatible = "zephyr,sdhc-spi-slot";
reg = <1>;
status = "okay";
mmc {
compatible = "zephyr,sdmmc-disk";
status = "okay";
};
spi-max-frequency = <DT_FREQ_M(24)>;
};
};
``` | /content/code_sandbox/boards/shields/seeed_xiao_round_display/seeed_xiao_round_display.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 622 |
```unknown
if SHIELD_SEEED_XIAO_ROUND_DISPLAY
if DISPLAY
if LVGL
config INPUT
default y
choice LV_COLOR_DEPTH
default LV_COLOR_DEPTH_16
endchoice
config LV_COLOR_16_SWAP
default y
endif # LVGL
endif # DISPLAY
endif # SHIELD_XIAO_ROUND_DISPLAY
``` | /content/code_sandbox/boards/shields/seeed_xiao_round_display/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 71 |
```restructuredtext
.. _waveshare_pico_ups_b_shield:
Waveshare Pico UPS-B shield
###########################
Overview
********
The Waveshare Pico UPS-B shield is an uninterruptible Power supply (UPS)
module designed for the Raspberry Pi Pico which uses the Texas Instruments' INA219
current/power Monitor. It communicates with the Raspberry Pi Pico over I2C
.. figure:: waveshare_pico_ups_b.jpg
:align: center
:alt: Waveshare Pico UPS-B shield
Waveshare Pico UPS-B shield
Hardware
--------
- INA219
- Senses bus voltages from 0 to 26 V
- Reports current, voltage and power
- 16 Programmable Addresses
- SOT23-8 and SOIC-8 packages
- Calibration registers
- ETA6003
- Switching charger with power path management
- Up to 95% DC-DC efficiency
- 0m power path MOSFET
- Up to 2.5A max charging current
- Connectivity
- Raspberry Pi Pico compatible (I2C)
- 2 pin jst header for Li-po battery
-------+-----------------------+---------------------------+
| Name | Function | Usage |
+=======+=======================+===========================+
| GP0 | None | |
+-------+-----------------------+---------------------------+
| GP1 | None | |
+-------+-----------------------+---------------------------+
| GP2 | None | |
+-------+-----------------------+---------------------------+
| GP3 | None | |
+-------+-----------------------+---------------------------+
| GP4 | None | |
+-------+-----------------------+---------------------------+
| GP5 | None | |
+-------+-----------------------+---------------------------+
| GP6 | I2C1_SDA ACTIVE_LOW | INA219 |
+-------+-----------------------+---------------------------+
| GP7 | I2C1_SCL ACTIVE_LOW | INA219 |
+-------+-----------------------+---------------------------+
| GP8 | None | |
+-------+-----------------------+---------------------------+
| GP9 | None | |
+-------+-----------------------+---------------------------+
| GP10 | None | |
+-------+-----------------------+---------------------------+
| GP11 | None | |
+-------+-----------------------+---------------------------+
| GP12 | None | |
+-------+-----------------------+---------------------------+
| GP13 | None | |
+-------+-----------------------+---------------------------+
| GP14 | None | |
+-------+-----------------------+---------------------------+
| GP15 | None | |
+-------+-----------------------+---------------------------+
| GP16 | None | |
+-------+-----------------------+---------------------------+
| GP17 | None | |
+-------+-----------------------+---------------------------+
| GP18 | None | |
+-------+-----------------------+---------------------------+
| GP19 | None | |
+-------+-----------------------+---------------------------+
| GP20 | None | |
+-------+-----------------------+---------------------------+
| GP21 | None | |
+-------+-----------------------+---------------------------+
| GP22 | None | |
+-------+-----------------------+---------------------------+
| GP23 | None | |
+-------+-----------------------+---------------------------+
| GP24 | None | |
+-------+-----------------------+---------------------------+
| GP25 | None | |
+-------+-----------------------+---------------------------+
| GP26 | None | |
+-------+-----------------------+---------------------------+
| GP27 | None | |
+-------+-----------------------+---------------------------+
| GP28 | None | |
+-------+-----------------------+---------------------------+
- Power Supply
- 3.3V ~ 5V
- Components
- Power switch
- Power LED
- Charging LED
For more information about the Waveshare Pico UPS-B:
- `Waveshare Pico UPS website`_
- `INA219 data sheet`_
- `ETA6003 data sheet`_
Programming
***********
Set ``--shield waveshare_pico_ups_b`` when you invoke ``west build`` or ``cmake`` in your Zephyr application. For
example:
.. zephyr-app-commands::
:zephyr-app: samples/sensor/ina219
:tool: all
:board: rpi_pico
:shield: waveshare_pico_ups_b
:goals: build flash
.. _Waveshare Pico UPS website:
path_to_url
.. _INA219 data sheet:
path_to_url
.. _ETA6003 data sheet:
path_to_url
``` | /content/code_sandbox/boards/shields/waveshare_ups/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,076 |
```unknown
/*
*
*/
/*
* This file is intentionally empty. Please confer with shield documentation
* for instructions to use this shield.
*/
``` | /content/code_sandbox/boards/shields/atmel_rf2xx/atmel_rf2xx.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 27 |
```restructuredtext
.. _seeed_xiao_round_display:
Seeed Studio XIAO Round Display
###############################
Overview
********
Seeed Studio Round Display for XIAO is an expansion board compatible with all
XIAO development boards. It features a fully covered touch screen on one side,
designed as a 39mm disc. It contains onboard RTC, charge chip, TF card slot
within its compact size, perfect for interactive displays in smart home,
wearables and more.
More information can be found on `the Getting Started page`_
.. figure:: img/seeed_xiao_round_display.webp
:align: center
:alt: Seeed Studio XIAO Round Display
Seeed Studio XIAO Round Display (Credit: Seeed Studio)
Programming
***********
Set ``--shield seeed_xiao_round_display`` when you invoke ``west build``.
LVGL Basic Sample
=================
For example:
.. zephyr-app-commands::
:zephyr-app: samples/subsys/display/lvgl
:board: xiao_ble/nrf52840
:shield: seeed_xiao_round_display
:goals: build
.. _the Getting Started page:
path_to_url
``` | /content/code_sandbox/boards/shields/seeed_xiao_round_display/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 257 |
```unknown
/*
*
*/
/ {
chosen {
zephyr,ieee802154 = &ieee802154_atmel_rf2xx_xplained;
};
};
&xplained1_spi {
status = "okay";
ieee802154_atmel_rf2xx_xplained: rf2xx@0 {
compatible = "atmel,rf2xx";
reg = <0x0>;
spi-max-frequency = <6000000>;
irq-gpios = <&xplained1_header 2
(GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>;
reset-gpios = <&xplained1_header 0 GPIO_ACTIVE_LOW>;
slptr-gpios = <&xplained1_header 3 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
``` | /content/code_sandbox/boards/shields/atmel_rf2xx/atmel_rf2xx_xplained.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 169 |
```unknown
config SHIELD_ATMEL_RF2XX
def_bool $(shields_list_contains,atmel_rf2xx)
config SHIELD_ATMEL_RF2XX_ARDUINO
def_bool $(shields_list_contains,atmel_rf2xx_arduino)
config SHIELD_ATMEL_RF2XX_MIKROBUS
def_bool $(shields_list_contains,atmel_rf2xx_mikrobus)
config SHIELD_ATMEL_RF2XX_XPRO
def_bool $(shields_list_contains,atmel_rf2xx_xpro)
config SHIELD_ATMEL_RF2XX_LEGACY
def_bool $(shields_list_contains,atmel_rf2xx_legacy)
config SHIELD_ATMEL_RF2XX_XPLAINED
def_bool $(shields_list_contains,atmel_rf2xx_xplained)
``` | /content/code_sandbox/boards/shields/atmel_rf2xx/Kconfig.shield | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 173 |
```unknown
/*
*
*/
/ {
chosen {
zephyr,ieee802154 = &ieee802154_atmel_rf2xx_xpro;
};
};
&ext1_spi {
status = "okay";
ieee802154_atmel_rf2xx_xpro: rf2xx@0 {
compatible = "atmel,rf2xx";
reg = <0x0>;
spi-max-frequency = <6000000>;
irq-gpios = <&ext1_header 6
(GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>;
reset-gpios = <&ext1_header 4 GPIO_ACTIVE_LOW>;
slptr-gpios = <&ext1_header 7 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
``` | /content/code_sandbox/boards/shields/atmel_rf2xx/atmel_rf2xx_xpro.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 159 |
```unknown
/*
*
*/
/ {
chosen {
zephyr,ieee802154 = &ieee802154_atmel_rf2xx_legacy;
};
};
&ext1_spi {
status = "okay";
ieee802154_atmel_rf2xx_legacy: rf2xx@0 {
compatible = "atmel,rf2xx";
reg = <0x0>;
spi-max-frequency = <6000000>;
irq-gpios = <&ext1_header 10
(GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>;
reset-gpios = <&ext1_header 8 GPIO_ACTIVE_LOW>;
slptr-gpios = <&ext1_header 11 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
``` | /content/code_sandbox/boards/shields/atmel_rf2xx/atmel_rf2xx_legacy.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 157 |
```unknown
if SHIELD_ATMEL_RF2XX || \
SHIELD_ATMEL_RF2XX_ARDUINO || \
SHIELD_ATMEL_RF2XX_MIKROBUS || \
SHIELD_ATMEL_RF2XX_XPRO || \
SHIELD_ATMEL_RF2XX_LEGACY || \
SHIELD_ATMEL_RF2XX_XPLAINED
if NETWORKING
orsource "boards/*.defconfig"
endif # NETWORKING
endif # SHIELD_ATMEL_RF2XX || \
# SHIELD_ATMEL_RF2XX_ARDUINO || \
# SHIELD_ATMEL_RF2XX_MIKROBUS || \
# SHIELD_ATMEL_RF2XX_XPRO || \
# SHIELD_ATMEL_RF2XX_LEGACY || \
# SHIELD_ATMEL_RF2XX_XPLAINED
``` | /content/code_sandbox/boards/shields/atmel_rf2xx/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 187 |
```unknown
/*
*
*/
/ {
chosen {
zephyr,ieee802154 = &ieee802154_atmel_rf2xx_arduino;
};
};
&arduino_spi {
status = "okay";
/* D10 */
cs-gpios = <&arduino_header 16
(GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
ieee802154_atmel_rf2xx_arduino: rf2xx@0 {
compatible = "atmel,rf2xx";
reg = <0x0>;
spi-max-frequency = <6000000>;
/* D2 */
irq-gpios = <&arduino_header 8
(GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>;
/* D8 */
reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>;
/* D9 */
slptr-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
``` | /content/code_sandbox/boards/shields/atmel_rf2xx/atmel_rf2xx_arduino.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 203 |
```unknown
/*
*
*/
/ {
chosen {
zephyr,ieee802154 = &ieee802154_atmel_rf2xx_mikrobus;
};
};
&mikrobus_spi {
status = "okay";
/* CS */
cs-gpios = <&mikrobus_header 2 GPIO_ACTIVE_LOW>;
ieee802154_atmel_rf2xx_mikrobus: rf2xx@0 {
compatible = "atmel,rf2xx";
reg = <0x0>;
spi-max-frequency = <6000000>;
/* INT */
irq-gpios = <&mikrobus_header 7
(GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>;
/* AN */
reset-gpios = <&mikrobus_header 0 GPIO_ACTIVE_LOW>;
/* PWM */
slptr-gpios = <&mikrobus_header 6 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
``` | /content/code_sandbox/boards/shields/atmel_rf2xx/atmel_rf2xx_mikrobus.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 207 |
```unknown
CONFIG_LED_STRIP=y
``` | /content/code_sandbox/boards/shields/adafruit_neopixel_grid_bff/adafruit_neopixel_grid_bff_display.conf | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 6 |
```unknown
/*
*/
#include <zephyr/dt-bindings/led/led.h>
/ {
aliases {
led-strip = &bff_led_strip;
};
};
``` | /content/code_sandbox/boards/shields/adafruit_neopixel_grid_bff/adafruit_neopixel_grid_bff.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```unknown
config SHIELD_ADAFRUIT_NEOPIXEL_GRID_BFF
def_bool $(shields_list_contains,adafruit_neopixel_grid_bff)
``` | /content/code_sandbox/boards/shields/adafruit_neopixel_grid_bff/Kconfig.shield | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
#include "adafruit_neopixel_grid_bff.overlay"
/ {
chosen {
zephyr,display = &bff_led_matrix;
};
bff_led_matrix: bff-led-matrix {
compatible = "led-strip-matrix";
status = "okay";
led-strips = <&bff_led_strip>;
width = <5>;
height = <5>;
start-from-right;
circulative;
};
};
``` | /content/code_sandbox/boards/shields/adafruit_neopixel_grid_bff/adafruit_neopixel_grid_bff_display.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 96 |
```unknown
# Intentionally left blank.
``` | /content/code_sandbox/boards/shields/adafruit_neopixel_grid_bff/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 9 |
```unknown
/*
*/
#include <dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h>
&pinctrl {
pinctrl_bff_ws2812: pinctrl_bff_ws2812 {
ws2812 {
pinmux = <PIO0_P26>;
};
};
};
&pio0 {
status = "okay";
bff-ws2812 {
compatible = "worldsemi,ws2812-rpi_pico-pio";
status = "okay";
pinctrl-0 = <&pinctrl_bff_ws2812>;
pinctrl-names = "default";
bit-waveform = <3>, <3>, <4>;
bff_led_strip: bff_led_strip {
status = "okay";
gpios = <&xiao_d 3 GPIO_ACTIVE_HIGH>;
chain-length = <25>;
color-mapping = <LED_COLOR_ID_GREEN
LED_COLOR_ID_RED
LED_COLOR_ID_BLUE>;
reset-delay = <280>;
frequency = <800000>;
};
};
};
``` | /content/code_sandbox/boards/shields/adafruit_neopixel_grid_bff/boards/adafruit_qt_py_rp2040.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 234 |
```unknown
CONFIG_WS2812_STRIP_RPI_PICO_PIO=y
``` | /content/code_sandbox/boards/shields/adafruit_neopixel_grid_bff/boards/adafruit_qt_py_rp2040.conf | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 14 |
```restructuredtext
.. _adafruit_neopixel_grid_bff:
Adafruit 5x5 NeoPixel Grid BFF
##############################
Overview
********
The `Adafruit 5x5 NeoPixel Grid BFF`_ is a 5x5 grid of WS2812B RGB LEDs,
which Adafruit refers to as "neopixels". The BFF series of shields are
designed to be compatible with any Adafruit Qt Py or Seeed Studio Xiao
board.
.. figure:: adafruit_neopixel_grid_bff.jpg
:align: center
:alt: Adafruit 5x5 NeoPixel Grid BFF
Adafruit 5x5 NeoPixel Grid BFF (Credit: Adafruit)
Pin Assignments
===============
+-----------------------+---------------------------------------------+
| Shield Connector Pin | Function |
+=======================+=============================================+
| A3 | WS2812B driver pin [1]_ |
+-----------------------+---------------------------------------------+
.. [1] This is the default pin when the board is delivered as is by Adafruit.
It can be changed away from the default using the onboard solder jumpers,
but this shield will no longer work without a matching device tree update.
Programming
***********
LED Strip Example
=================
Set ``--shield adafruit_neopixel_grid_bff`` when you invoke ``west build``. For example:
.. zephyr-app-commands::
:zephyr-app: samples/drivers/led_strip
:board: adafruit_qt_py_rp2040
:shield: adafruit_neopixel_grid_bff
:goals: build
LED Display Matrix Example
==========================
.. warning::
When using this example, all of the LEDs will be set to their maximum
brightness. Having all of the LEDs on at once can cause the PCB to overheat
or draw too much current from any on-board voltage regulators.
Adafruit does provide solder pads for your own power supply on the
underside of the BFF for this reason. It is not required, but is strongly
recommended if all of the LEDs are fully on for any significant amount of
time.
Set ``--shield adafruit_neopixel_grid_bff_display`` when you invoke ``west build``. For example:
.. zephyr-app-commands::
:zephyr-app: samples/drivers/display
:board: adafruit_qt_py_rp2040
:shield: adafruit_neopixel_grid_bff_display
:goals: build
.. _Adafruit 5x5 NeoPixel Grid BFF:
path_to_url
``` | /content/code_sandbox/boards/shields/adafruit_neopixel_grid_bff/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 551 |
```restructuredtext
.. _boards-enjoydigital:
EnjoyDigital
############
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/enjoydigital/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
/*
*
*/
/dts-v1/;
#include <riscv32-litex-vexriscv.dtsi>
/ {
model = "LiteX VexRiscV";
compatible = "litex,vexriscv";
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sram = &ram0;
};
aliases {
watchdog0 = &wdt0;
};
ram0: memory@40000000 {
device_type = "memory";
reg = <0x40000000 0x10000000>;
};
};
&ctrl0 {
status = "okay";
};
&uart0 {
status = "okay";
current-speed = <115200>;
};
&timer0 {
status = "okay";
};
&wdt0 {
status = "okay";
};
&mdio0 {
status = "okay";
};
&phy0 {
status = "okay";
};
ð0 {
status = "okay";
};
&dna0 {
status = "okay";
};
&spi0 {
status = "okay";
};
&prbs0 {
status = "okay";
};
&i2c0 {
status = "okay";
};
&pwm0 {
status = "okay";
};
&gpio_out {
status = "okay";
};
&gpio_in {
status = "okay";
};
&i2s_rx {
status = "okay";
};
&i2s_tx {
status = "okay";
};
&clk0 {
status = "okay";
};
&clk1 {
status = "okay";
};
&clock0 {
status = "okay";
};
``` | /content/code_sandbox/boards/enjoydigital/litex_vexriscv/litex_vexriscv.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 351 |
```unknown
config BOARD_LITEX_VEXRISCV
select SOC_LITEX_VEXRISCV
``` | /content/code_sandbox/boards/enjoydigital/litex_vexriscv/Kconfig.litex_vexriscv | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 24 |
```yaml
board:
name: litex_vexriscv
vendor: litex
socs:
- name: litex_vexriscv
``` | /content/code_sandbox/boards/enjoydigital/litex_vexriscv/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```unknown
#
#
#
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_GPIO=y
CONFIG_XIP=n
CONFIG_CLOCK_CONTROL=y
CONFIG_HEAP_MEM_POOL_SIZE=4096
CONFIG_SPI_NOR_SFDP_RUNTIME=y
``` | /content/code_sandbox/boards/enjoydigital/litex_vexriscv/litex_vexriscv_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 49 |
```unknown
if BOARD_LITEX_VEXRISCV
if NETWORKING
config NET_L2_ETHERNET
default y
endif # NETWORKING
endif # BOARD_LITEX_VEXRISCV
``` | /content/code_sandbox/boards/enjoydigital/litex_vexriscv/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 45 |
```yaml
#
#
#
identifier: litex_vexriscv
name: LiteX SoC with VexRiscV softcore CPU
type: mcu
arch: riscv
toolchain:
- zephyr
ram: 262144
supported:
- gpio
- uart
- spi
- i2s
- i2c
- watchdog
testing:
ignore_tags:
- bluetooth
- xip
vendor: litex
``` | /content/code_sandbox/boards/enjoydigital/litex_vexriscv/litex_vexriscv.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 106 |
```restructuredtext
.. _atmel_at86rf2xx_transceivers:
Atmel AT86RF2XX Transceivers
############################
Overview
********
The Atmel AT86RF2xx is a high performance radio transceiver targeted for IEEE
802.15.4, ZigBee, RF4CE, 6LoWPAN, and ISM applications. The AT86RF2xx is a
true SPI-to-antenna solution and can be operated by any external
microcontroller.
The current IEEE 802.15.4 AT86RF2xx Zephyr driver currently works with any
2.4 Ghz transceiver, except AT86RF230. The RF2xx driver allows use of
:ref:`ieee802154_interface` and :ref:`thread_protocol_interface` network
stacks.
This is a generic shield focused not only on Atmel Development Boards Kits.
There are compatible designations for `AT AVR-RZ600`_ and `AT REB233-XPRO`_.
This means, any Atmel board with 10-pin Xplained or 20-pin Xplained Pro
extension headers can be used. You can check
`Atmel Xplained Pro Hardware Development Kit User Guide`_ for more information.
Besides that, Arduino and MikroBus standard headers are available to complement
the shield module configurations. For any other project that doesn't fit on
the current available variations an overlay can be created. However, the
overlay is the last resource and is recommended use standard header always
possible.
RZ600 Module
============
The RZ600 Development Kit needs Atmel Xplained or Xplained-Pro header
connector. The modules from this kit are available without any transceiver
advanced features. For Xplained headers the `atmel_rf2xx_xplained`_ must be
selected. For Xplained-Pro header the `atmel_rf2xx_legacy`_ must be enabled.
.. image:: ATAVRRZ600.jpg
:align: center
:alt: AVR-RZ600
Pins Assignment of the RZ600 Module
===================================
+---------+--------+-------------------------------------+
| Pin | Name | Function |
+=========+========+=====================================+
| 1 | RST | GPIO - Reset |
+---------+--------+-------------------------------------+
| 2 | MISC | DNU - Do Not Use |
+---------+--------+-------------------------------------+
| 3 | IRQ | GPIO - Interrupt |
+---------+--------+-------------------------------------+
| 4 | SLP_TR | GPIO - Multi purpose control signal |
+---------+--------+-------------------------------------+
| 5 | CS | SPI Chip Select |
+---------+--------+-------------------------------------+
| 6 | MOSI | SPI Master Out / Slave In |
+---------+--------+-------------------------------------+
| 7 | MISO | SPI Master In / Slave Out |
+---------+--------+-------------------------------------+
| 8 | SCLK | SPI Clock |
+---------+--------+-------------------------------------+
| 9 | GND | |
+---------+--------+-------------------------------------+
| 10 | VDD | POWER +3.3V |
+---------+--------+-------------------------------------+
REB233-XPRO Module
==================
The REB233-XPRO development kit uses Atmel Xplained Pro header. It is enabled
selecting `atmel_rf2xx_xpro`_ option.
.. image:: atreb233-xpro-top.jpg
:align: center
:alt: REB233-XPRO Top
Pins Assignment of the REB233-XPRO Module
=========================================
+---------+--------+-------------------------------------+
| Pin | Name | Function |
+=========+========+=====================================+
| 1 | ID | DNU - Do Not Use |
+---------+--------+-------------------------------------+
| 2 | GND | |
+---------+--------+-------------------------------------+
| 3 | DIG1 | DNU - Do Not Use |
+---------+--------+-------------------------------------+
| 4 | DIG3 | DNU - Do Not Use |
+---------+--------+-------------------------------------+
| 5 | DIG2 | GPIO - RX Frame Time Stamping |
+---------+--------+-------------------------------------+
| 6 | CLKM | DNU - Do Not Use |
+---------+--------+-------------------------------------+
| 7 | RST | GPIO - Reset |
+---------+--------+-------------------------------------+
| 8 | | |
+---------+--------+-------------------------------------+
| 9 | IRQ | GPIO - Interrupt |
+---------+--------+-------------------------------------+
| 10 | SLP_TR | GPIO - Multi purpose control signal |
+---------+--------+-------------------------------------+
| 11 | SDA | EEPROM - AT24MAC602 |
+---------+--------+-------------------------------------+
| 12 | SCL | EEPROM - AT24MAC602 |
+---------+--------+-------------------------------------+
| 13 | | |
+---------+--------+-------------------------------------+
| 14 | | |
+---------+--------+-------------------------------------+
| 15 | CS | SPI Chip Select |
+---------+--------+-------------------------------------+
| 16 | MOSI | SPI Master Out / Slave In |
+---------+--------+-------------------------------------+
| 17 | MISO | SPI Master In / Slave Out |
+---------+--------+-------------------------------------+
| 18 | SCLK | SPI Clock |
+---------+--------+-------------------------------------+
| 19 | GND | |
+---------+--------+-------------------------------------+
| 20 | VDD | POWER +3.3V |
+---------+--------+-------------------------------------+
.. note:: DIG2 is not current implemented on RF2xx driver.
Arduino Shields
===============
Arduino Uno R3 header is available without advanced features. It is enabled
selecting `atmel_rf2xx_arduino`_ variant option.
Pins Assignment of the Arduino Shield Modules
=============================================
+---------+--------+-------------------------------------+
| Pin | Name | Function |
+=========+========+=====================================+
| D0 | | |
+---------+--------+-------------------------------------+
| D1 | | |
+---------+--------+-------------------------------------+
| D2 | IRQ | GPIO - Interrupt |
+---------+--------+-------------------------------------+
| D3 | | |
+---------+--------+-------------------------------------+
| D4 | | |
+---------+--------+-------------------------------------+
| D5 | | |
+---------+--------+-------------------------------------+
| D6 | | |
+---------+--------+-------------------------------------+
| D7 | | |
+---------+--------+-------------------------------------+
| D8 | RST | GPIO - Reset |
+---------+--------+-------------------------------------+
| D9 | SLP_TR | GPIO - Multi purpose control signal |
+---------+--------+-------------------------------------+
| D10 | CS | SPI Chip Select |
+---------+--------+-------------------------------------+
| D11 | MOSI | SPI Master Out / Slave In |
+---------+--------+-------------------------------------+
| D12 | MISO | SPI Master In / Slave Out |
+---------+--------+-------------------------------------+
| D13 | SCLK | SPI Clock |
+---------+--------+-------------------------------------+
| D14 | | |
+---------+--------+-------------------------------------+
| D15 | | |
+---------+--------+-------------------------------------+
| | GND | |
+---------+--------+-------------------------------------+
| | VDD | POWER +3.3V |
+---------+--------+-------------------------------------+
| | VCC | POWER +5.0V |
+---------+--------+-------------------------------------+
MikroBus Shields
================
MikroBus header is available without advanced features. It is
enabled selecting `atmel_rf2xx_mikrobus`_ variant option.
Pins Assignment of the MikroBus Shield Modules
==============================================
+---------+--------+-------------------------------------+
| Pin | Name | Function |
+=========+========+=====================================+
| AN | RST | GPIO - Reset |
+---------+--------+-------------------------------------+
| RST | | |
+---------+--------+-------------------------------------+
| CS | CS | SPI Chip Select |
+---------+--------+-------------------------------------+
| SCK | SCLK | SPI Clock |
+---------+--------+-------------------------------------+
| MISO | MISO | SPI Master In / Slave Out |
+---------+--------+-------------------------------------+
| MOSI | MOSI | SPI Master Out / Slave In |
+---------+--------+-------------------------------------+
| VCC-3.3 | VDD | POWER +3.3V |
+---------+--------+-------------------------------------+
| GND | GND | |
+---------+--------+-------------------------------------+
| GND | GND | |
+---------+--------+-------------------------------------+
| VCC-5.0 | VCC | POWER +5.0V |
+---------+--------+-------------------------------------+
| SDA | | |
+---------+--------+-------------------------------------+
| SCL | | |
+---------+--------+-------------------------------------+
| TX | | |
+---------+--------+-------------------------------------+
| RX | | |
+---------+--------+-------------------------------------+
| INT | IRQ | GPIO - Interrupt |
+---------+--------+-------------------------------------+
| PWM | SLP_TR | GPIO - Multi purpose control signal |
+---------+--------+-------------------------------------+
Supported variations
====================
The below table suggests shield variation accordingly with end user
application. When a standard connector (arduino, mikrobus, xplained,
xplained-pro) is available on board, user should select the matching shield
configuration. When atmel_rf2xx shield is used with a board that doesn't
feature a standard connector, a dedicated <board>.overlay file should be
provided. The remaining configurations should be used based on the board
standard headers available.
+-----------------------------+------------------------------+-----------+
| Connector Standard | Shield Designation | Variation |
+=============================+==============================+===========+
| Without standard (overlay) | `atmel_rf2xx`_ | 1 |
+-----------------------------+------------------------------+-----------+
| Atmel Xplained header | `atmel_rf2xx_xplained`_ | 2 |
+-----------------------------+------------------------------+-----------+
| Atmel Xplained Pro header | `atmel_rf2xx_xpro`_ | 3 |
+-----------------------------+------------------------------+-----------+
| Atmel Xplained Pro header | `atmel_rf2xx_legacy`_ | 4 |
+-----------------------------+------------------------------+-----------+
| Arduino | `atmel_rf2xx_arduino`_ | 5 |
+-----------------------------+------------------------------+-----------+
| MikroBus | `atmel_rf2xx_mikrobus`_ | 6 |
+-----------------------------+------------------------------+-----------+
Requirements
************
This shield requires a board which provides a configuration that allows an
SPI interface, an interrupt signal and two GPIO. (see :ref:`shields` for more
details).
.. note::
Boards that already have a network interface: Check network
documentation to understand how properly configure both interfaces.
To keep simple, make sure IEEE 802.15.4 is the only interface enabled
at Networking -> Link Layer Options. This will avoid problems running
Zephyr samples.
Tested Boards
=============
+------------------------------+------------------------------+-----------+
| Board | Disabled Interface | Variation |
+==============================+==============================+===========+
| ATMEL sam4s_xplained | | 2 |
+------------------------------+------------------------------+-----------+
| ATMEL sam4e_xpro | Ethernet | 3 , 4 |
+------------------------------+------------------------------+-----------+
| ATMEL sam_v71_xult/samv71q21 | Ethernet | 3 , 4 , 5 |
+------------------------------+------------------------------+-----------+
Sample usage
************
You can try use IEEE 802.15.4 and/or OpenThread with the Zephyr Echo server
and Echo client samples, which provide out-of-the-box configuration for
both IEEE 802.15.4 and OpenThread. To enable IEEE 802.15.4 support in the
samples, build them with ``overlay-802154.conf`` overlay config file. Same
way, to enable OpenThread support, build them with ``overlay-ot.conf`` overlay
config file. See :zephyr:code-sample:`sockets-echo-server` and
:zephyr:code-sample:`sockets-echo-client` samples for details.
Build and Programming
*********************
Set ``--shield <shield designator>`` when you invoke ``west build``.
.. zephyr-app-commands::
:zephyr-app: samples/net/sockets/echo_server
:host-os: unix
:board: sam4s_xplained
:gen-args: -DOVERLAY_CONFIG=overlay-802154.conf
:shield: atmel_rf2xx_xplained
:goals: build flash
:compact:
.. zephyr-app-commands::
:zephyr-app: samples/net/sockets/echo_server
:host-os: unix
:board: [sam4e_xpro | sam_v71_xult/samv71q21]
:gen-args: -DOVERLAY_CONFIG=overlay-802154.conf
:shield: [atmel_rf2xx_xpro | atmel_rf2xx_legacy]
:goals: build flash
:compact:
.. zephyr-app-commands::
:zephyr-app: samples/net/sockets/echo_server
:host-os: unix
:board: [sam_v71_xult/samv71q21 | frdm_k64f | nucleo_f767zi]
:gen-args: -DOVERLAY_CONFIG=overlay-802154.conf
:shield: atmel_rf2xx_arduino
:goals: build flash
:compact:
.. zephyr-app-commands::
:zephyr-app: samples/net/sockets/echo_server
:host-os: unix
:board: lpcxpresso55s69_ns
:gen-args: -DOVERLAY_CONFIG=overlay-802154.conf
:shield: atmel_rf2xx_microbus
:goals: build flash
:compact:
References
**********
.. target-notes::
.. _AT AVR-RZ600:
path_to_url
.. _AT REB233-XPRO:
path_to_url
.. _Atmel Xplained Pro Hardware Development Kit User Guide:
path_to_url
.. _atmel_rf2xx:
path_to_url
.. _atmel_rf2xx_xplained:
path_to_url
.. _atmel_rf2xx_xpro:
path_to_url
.. _atmel_rf2xx_legacy:
path_to_url
.. _atmel_rf2xx_arduino:
path_to_url
.. _atmel_rf2xx_mikrobus:
path_to_url
``` | /content/code_sandbox/boards/shields/atmel_rf2xx/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,496 |
```restructuredtext
.. _boards-qemu:
QEMU
####
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/qemu/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```cmake
#
set(SUPPORTED_EMU_PLATFORMS qemu)
set(QEMU_ARCH xilinx-aarch64)
set(QEMU_CPU_TYPE_${ARCH} cortex-r5)
set(QEMU_FLAGS_${ARCH}
-nographic
-machine arm-generic-fdt
-dtb ${CMAKE_CURRENT_LIST_DIR}/fdt-single_arch-zcu102-arm.dtb
)
set(QEMU_KERNEL_OPTION
"-device;loader,file=\$<TARGET_FILE:\${logical_target_for_zephyr_elf}>,cpu-num=4"
"-device;loader,addr=0xff5e023c,data=0x80008fde,data-len=4"
"-device;loader,addr=0xff9a0000,data=0x80000218,data-len=4"
)
board_set_debugger_ifnset(qemu)
``` | /content/code_sandbox/boards/qemu/cortex_r5/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 176 |
```yaml
identifier: qemu_cortex_r5
name: QEMU Emulation for Cortex-R5
type: qemu
simulation: qemu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 65536
flash: 32768
testing:
default: true
ignore_tags:
- net
- bluetooth
vendor: xlnx
``` | /content/code_sandbox/boards/qemu/cortex_r5/qemu_cortex_r5.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 90 |
```unknown
CONFIG_XIP=n
CONFIG_QEMU_ICOUNT_SHIFT=3
CONFIG_ISR_STACK_SIZE=512
CONFIG_THREAD_STACK_INFO=y
# enable uart driver
CONFIG_SERIAL=y
# enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
CONFIG_ARM_MPU=y
``` | /content/code_sandbox/boards/qemu/cortex_r5/qemu_cortex_r5_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 66 |
```unknown
/*
*
*
*/
/dts-v1/;
#include <arm/xilinx/zynqmp_rpu.dtsi>
/ {
model = "QEMU Cortex-R5";
compatible = "xlnx,zynqmp-qemu";
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,ocm = &ocm;
};
};
&uart0 {
status = "okay";
current-speed = <115200>;
clock-frequency = <99999901>;
};
&ttc0 {
status = "okay";
clock-frequency = <5000000>;
};
``` | /content/code_sandbox/boards/qemu/cortex_r5/qemu_cortex_r5.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 159 |
```yaml
board:
name: qemu_cortex_r5
vendor: qemu
socs:
- name: zynqmp_rpu
``` | /content/code_sandbox/boards/qemu/cortex_r5/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
config BOARD_QEMU_CORTEX_R5
select SOC_XILINX_ZYNQMP_RPU
``` | /content/code_sandbox/boards/qemu/cortex_r5/Kconfig.qemu_cortex_r5 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 24 |
```restructuredtext
.. _litex-vexriscv:
LiteX VexRiscv
##############
LiteX VexRiscv is an example of a system on a chip (SoC) that consists of
a `VexRiscv processor <path_to_url`_
and additional peripherals. This setup can be generated using
`Zephyr on LiteX VexRiscv (reference platform)
<path_to_url`_
or `LiteX SoC Builder <path_to_url`_
and can be used on various FPGA chips.
The bitstream (FPGA configuration file) can be obtained using both
vendor-specific and open-source tools, including the
`F4PGA toolchain <path_to_url`_.
The ``litex_vexriscv`` board configuration in Zephyr is meant for the
LiteX VexRiscv SoC implementation generated for the
`Digilent Arty A7-35T or A7-100T Development Boards
<path_to_url`_
or `SDI-MIPI Video Converter <path_to_url`_.
.. image:: img/litex_vexriscv.jpg
:align: center
:alt: LiteX VexRiscv on Digilent Arty 35T Board
LiteX is based on
`Migen <path_to_url`_/`MiSoC SoC builder <path_to_url`_
and provides ready-made system components such as buses, streams, interconnects,
common cores, and CPU wrappers to create SoCs easily. The tool contains
mechanisms for integrating, simulating, and building various designs
that target multiple chips of different vendors.
More information about the LiteX project can be found on
`LiteX's website <path_to_url`_.
VexRiscv is a 32-bit implementation of the RISC-V CPU architecture
written in the `SpinalHDL <path_to_url`_.
The processor supports M, C, and A RISC-V instruction
set extensions, with numerous optimizations that include multistage
pipelines and data caching. The project provides many optional extensions
that can be used to customize the design (JTAG, MMU, MUL/DIV extensions).
The implementation is optimized for FPGA chips.
More information about the project can be found on
`VexRiscv's website <path_to_url`_.
To run the ZephyrOS on the VexRiscv CPU, it is necessary to prepare the
bitstream for the FPGA on a Digilent Arty A7-35 Board or SDI-MIPI Video Converter. This can be achieved
using the
`Zephyr on LiteX VexRiscv <path_to_url`_
reference platform. You can also use the official LiteX SoC Builder.
Bitstream generation
********************
Zephyr on LiteX VexRiscv
========================
Using this platform ensures that all registers addresses are in the proper place.
All drivers were tested using this platform.
In order to generate the bitstream,
proceed with the following instruction:
1. Clone the repository and update all submodules:
.. code-block:: bash
git clone path_to_url
cd zephyr-on-litex-vexriscv
git submodule update --init --recursive
Generating the bitstream for the Digilent Arty A7-35 Board requires F4PGA toolchain installation. It can be done by following instructions in
`this tutorial <path_to_url`_.
In order to generate the bitstream for the SDI-MIPI Video Converter, install
oxide (yosys+nextpnr) toolchain by following
`these instructions <path_to_url#getting-started---complete-flow>`_.
#. Next, get all required packages and run the install script:
.. code-block:: bash
apt-get install build-essential bzip2 python3 python3-dev python3-pip
./install.sh
#. Add LiteX to path:
.. code-block:: bash
source ./init
#. Set up the F4PGA environment (for the Digilent Arty A7-35 Board):
.. code-block:: bash
export F4PGA_INSTALL_DIR=~/opt/f4pga
export FPGA_FAM="xc7"
export PATH="$F4PGA_INSTALL_DIR/$FPGA_FAM/install/bin:$PATH";
source "$F4PGA_INSTALL_DIR/$FPGA_FAM/conda/etc/profile.d/conda.sh"
conda activate $FPGA_FAM
#. Generate the bitstream for the Arty 35T:
.. code-block:: bash
./make.py --board=arty --variant=a7-35 --build --toolchain=symbiflow
#. Generate the bitstream for the Arty 100T:
.. code-block:: bash
./make.py --board=arty --variant=a7-100 --build --toolchain=symbiflow
#. Generate the bitstream for the SDI-MIPI Video Converter:
.. code-block:: bash
./make.py --board=sdi_mipi_bridge --build --toolchain=oxide
Official LiteX SoC builder
==========================
You can also generate the bitstream using the `official LiteX repository <path_to_url`_.
In that case you must also generate a dts overlay.
1. Install Migen/LiteX and the LiteX's cores:
.. code-block:: bash
wget path_to_url
chmod +x litex_setup.py
./litex_setup.py --init --install --user (--user to install to user directory) --config=(minimal, standard, full)
#. Install the RISC-V toolchain:
.. code-block:: bash
pip3 install meson ninja
./litex_setup.py --gcc=riscv
#. Build the target:
.. code-block:: bash
./litex-boards/litex_boards/targets/digilent_arty.py --build --timer-uptime --csr-json csr.json
#. Generate the dts and config overlay:
.. code-block:: bash
./litex/litex/tools/litex_json2dts_zephyr.py --dts overlay.dts --config overlay.config csr.json
Programming and booting
*************************
Building
========
Applications for the ``litex_vexriscv`` board configuration can be built as usual
(see :ref:`build_an_application`).
In order to build the application for ``litex_vexriscv``, set the ``BOARD`` variable
to ``litex_vexriscv``.
If you were generating bitstream with the official LiteX SoC builder you need to pass an additional argument:
.. code-block:: bash
west build -b litex_vexriscv path/to/app -DDTC_OVERLAY_FILE=path/to/overlay.dts
Booting
=======
To upload the bitstream to Digilent Arty A7-35 you can use `xc3sprog <path_to_url`_ or
`openFPGALoader <path_to_url`_:
.. code-block:: bash
xc3sprog -c nexys4 digilent_arty.bit
.. code-block:: bash
openFPGALoader -b arty_a7_100t digilent_arty.bit
Use `ecpprog <path_to_url`_ to upload the bitstream to SDI-MIPI Video Converter:
.. code-block:: bash
ecpprog -S antmicro_sdi_mipi_video_converter.bit
You can boot from a serial port using litex_term (replace `ttyUSBX` with your device) , e.g.:
.. code-block:: bash
litex_term /dev/ttyUSBX --speed 115200 --kernel zephyr.bin
``` | /content/code_sandbox/boards/enjoydigital/litex_vexriscv/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,652 |
```unknown
config BOARD_QEMU_CORTEX_R5
select QEMU_TARGET
``` | /content/code_sandbox/boards/qemu/cortex_r5/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 16 |
```unknown
if BOARD_QEMU_CORTEX_R5
config BUILD_OUTPUT_BIN
default n
if USERSPACE
config COMPILER_ISA_THUMB2
default n
endif
endif # BOARD_QEMU_CORTEX_R5
``` | /content/code_sandbox/boards/qemu/cortex_r5/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 47 |
```cmake
set(SUPPORTED_EMU_PLATFORMS qemu)
set(QEMU_binary_suffix riscv32)
set(QEMU_CPU_TYPE_${ARCH} riscv32)
set(QEMU_FLAGS_${ARCH}
-nographic
-machine virt
-bios none
-m 256
)
board_set_debugger_ifnset(qemu)
``` | /content/code_sandbox/boards/qemu/riscv32e/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 74 |
```unknown
/*
*
*
*/
/dts-v1/;
#include <qemu/virt-riscv32.dtsi>
/ {
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sram = &ram0;
};
};
&uart0 {
status = "okay";
};
``` | /content/code_sandbox/boards/qemu/riscv32e/qemu_riscv32e.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 78 |
```unknown
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_STACK_SENTINEL=y
CONFIG_QEMU_ICOUNT_SHIFT=6
CONFIG_XIP=n
CONFIG_RISCV_PMP=y
``` | /content/code_sandbox/boards/qemu/riscv32e/qemu_riscv32e_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 44 |
```yaml
board:
name: qemu_riscv32e
vendor: qemu
socs:
- name: qemu_virt_riscv32e
``` | /content/code_sandbox/boards/qemu/riscv32e/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```yaml
identifier: qemu_riscv32e
name: QEMU Emulation for RISC-V (RV32E) 32-bit
type: qemu
simulation: qemu
arch: riscv
toolchain:
- zephyr
- xtools
supported:
- netif
testing:
default: true
ignore_tags:
- net
- bluetooth
``` | /content/code_sandbox/boards/qemu/riscv32e/qemu_riscv32e.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 83 |
```unknown
config BOARD_QEMU_RISCV32E
select SOC_QEMU_VIRT_RISCV32E
``` | /content/code_sandbox/boards/qemu/riscv32e/Kconfig.qemu_riscv32e | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 24 |
```restructuredtext
.. _qemu_cortex_r5:
ARM Cortex-R5 Emulation (QEMU)
##############################
Overview
********
This board configuration will use QEMU to emulate the Xilinx Zynq UltraScale+
(ZynqMP) platform.
This configuration provides support for an ARM Cortex-R5 CPU and these devices:
* ARM PL-390 Generic Interrupt Controller
* Xilinx Zynq TTC (Cadence TTC)
* Xilinx Zynq UART
.. note::
This board configuration makes no claims about its suitability for use
with an actual ZCU102 hardware system, or any other hardware system.
Hardware
********
Supported Features
==================
The following hardware features are supported:
+--------------+------------+----------------------+
| Interface | Controller | Driver/Component |
+==============+============+======================+
| GIC | on-chip | generic interrupt |
| | | controller |
+--------------+------------+----------------------+
| TTC | on-chip | system timer |
+--------------+------------+----------------------+
| UART | on-chip | serial port |
+--------------+------------+----------------------+
The kernel currently does not support other hardware features on this platform.
Devices
========
System Timer
------------
This board configuration uses a system timer tick frequency of 1000 Hz.
Serial Port
-----------
This board configuration uses a single serial communication channel with the
on-chip UART0.
Known Problems or Limitations
==============================
The following platform features are unsupported:
* Dual-redundant Core Lock-step (DCLS) execution is not emulated.
* Xilinx Zynq TTC driver does not support tickless mode operation.
Programming and Debugging
*************************
Use this configuration to run basic Zephyr applications and kernel tests in the
QEMU emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample:
.. zephyr-app-commands::
:zephyr-app: samples/synchronization
:host-os: unix
:board: qemu_cortex_r5
:goals: run
This will build an image with the synchronization sample app, boot it using
QEMU, and display the following console output:
.. code-block:: console
*** Booting Zephyr OS build v2.2.0 ***
threadA: Hello World from qemu_cortex_r5!
threadB: Hello World from qemu_cortex_r5!
threadA: Hello World from qemu_cortex_r5!
threadB: Hello World from qemu_cortex_r5!
threadA: Hello World from qemu_cortex_r5!
threadB: Hello World from qemu_cortex_r5!
threadA: Hello World from qemu_cortex_r5!
threadB: Hello World from qemu_cortex_r5!
threadA: Hello World from qemu_cortex_r5!
threadB: Hello World from qemu_cortex_r5!
Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`.
Debugging
=========
Refer to the detailed overview about :ref:`application_debugging`.
References
**********
1. ARMv7-A and ARMv7-R Architecture Reference Manual (ARM DDI 0406C ID051414)
2. Cortex-R5 and Cortex-R5F Technical Reference Manual (ARM DDI 0460C ID021511)
3. Zynq UltraScale+ Device Technical Reference Manual (UG1085)
``` | /content/code_sandbox/boards/qemu/cortex_r5/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 725 |
```unknown
config BOARD_QEMU_RISCV32E
select QEMU_TARGET
``` | /content/code_sandbox/boards/qemu/riscv32e/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 17 |
```unknown
if BOARD_QEMU_RISCV32E
# Use thread local storage by default so that this feature gets more CI coverage.
config THREAD_LOCAL_STORAGE
default y
config BUILD_OUTPUT_BIN
default n
config HAS_COVERAGE_SUPPORT
default y
endif # BOARD_QEMU_RISCV32E
``` | /content/code_sandbox/boards/qemu/riscv32e/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 64 |
```unknown
config BOARD_QEMU_NIOS2
select SOC_QEMU_NIOS2
``` | /content/code_sandbox/boards/qemu/nios2/Kconfig.qemu_nios2 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 18 |
```cmake
set(SUPPORTED_EMU_PLATFORMS qemu)
set(QEMU_CPU_TYPE_${ARCH} nios2)
set(QEMU_FLAGS_${ARCH}
-machine altera_10m50_zephyr
-nographic
)
board_set_debugger_ifnset(qemu)
``` | /content/code_sandbox/boards/qemu/nios2/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 60 |
```yaml
identifier: qemu_nios2
name: QEMU Emulation for NIOS II
type: qemu
simulation: qemu
arch: nios2
ram: 128
flash: 128
toolchain:
- zephyr
- xtools
testing:
default: true
ignore_tags:
- net
- bluetooth
vendor: qemu
``` | /content/code_sandbox/boards/qemu/nios2/qemu_nios2.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 80 |
```restructuredtext
.. _qemu_riscv32e:
RISCV32E Emulation (QEMU)
#########################
Overview
********
The RISCV32E QEMU board configuration is used to emulate the RISCV32 (RV32E) architecture.
Programming and Debugging
*************************
Applications for the ``qemu_riscv32e`` board configuration can be built and run in
the usual way for emulated boards (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Flashing
========
While this board is emulated and you can't "flash" it, you can use this
configuration to run basic Zephyr applications and kernel tests in the QEMU
emulated environment. For example, with the :zephyr:code-sample:`synchronization` sample:
.. zephyr-app-commands::
:zephyr-app: samples/synchronization
:host-os: unix
:board: qemu_riscv32e
:goals: run
This will build an image with the synchronization sample app, boot it using
QEMU, and display the following console output:
.. code-block:: console
*** Booting Zephyr OS build v3.1.0-rc1-59-g0d66cc1f6645 ***
thread_a: Hello World from cpu 0 on qemu_riscv32e!
thread_b: Hello World from cpu 0 on qemu_riscv32e!
thread_a: Hello World from cpu 0 on qemu_riscv32e!
thread_b: Hello World from cpu 0 on qemu_riscv32e!
thread_a: Hello World from cpu 0 on qemu_riscv32e!
thread_b: Hello World from cpu 0 on qemu_riscv32e!
thread_a: Hello World from cpu 0 on qemu_riscv32e!
thread_b: Hello World from cpu 0 on qemu_riscv32e!
thread_a: Hello World from cpu 0 on qemu_riscv32e!
thread_b: Hello World from cpu 0 on qemu_riscv32e!
thread_a: Hello World from cpu 0 on qemu_riscv32e!
thread_b: Hello World from cpu 0 on qemu_riscv32e!
Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`.
Debugging
=========
Refer to the detailed overview about :ref:`application_debugging`.
``` | /content/code_sandbox/boards/qemu/riscv32e/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 528 |
```unknown
/dts-v1/;
#include <intel/nios2-qemu.dtsi>
/ {
model = "qemu_nios2";
compatible = "qemu,nios2";
aliases {
uart-0 = &jtag_uart;
uart-1 = &ns16550_uart;
};
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &ns16550_uart;
zephyr,shell-uart = &ns16550_uart;
};
};
&jtag_uart {
status = "okay";
current-speed = <115200>;
};
&ns16550_uart {
status = "okay";
current-speed = <115200>;
};
``` | /content/code_sandbox/boards/qemu/nios2/qemu_nios2.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 163 |
```unknown
CONFIG_HAS_ALTERA_HAL=y
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_INCLUDE_RESET_VECTOR=n
CONFIG_EXTRA_EXCEPTION_INFO=y
CONFIG_QEMU_ICOUNT_SHIFT=4
``` | /content/code_sandbox/boards/qemu/nios2/qemu_nios2_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 44 |
```unknown
if BOARD_QEMU_NIOS2
config BUILD_OUTPUT_BIN
default n
endif
``` | /content/code_sandbox/boards/qemu/nios2/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 20 |
```yaml
board:
name: qemu_nios2
vendor: altr
socs:
- name: qemu_nios2
``` | /content/code_sandbox/boards/qemu/nios2/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```unknown
config BOARD_QEMU_NIOS2
select QEMU_TARGET
``` | /content/code_sandbox/boards/qemu/nios2/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 15 |
```unknown
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_EXTRA_EXCEPTION_INFO=y
CONFIG_QEMU_ICOUNT_SHIFT=6
``` | /content/code_sandbox/boards/qemu/leon3/qemu_leon3_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```cmake
set(SUPPORTED_EMU_PLATFORMS qemu)
set(QEMU_binary_suffix sparc)
set(QEMU_CPU_TYPE_${ARCH} leon3)
set(QEMU_FLAGS_${ARCH}
-nographic
-machine leon3_generic
-icount auto
)
board_set_debugger_ifnset(qemu)
``` | /content/code_sandbox/boards/qemu/leon3/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 69 |
```yaml
board:
name: qemu_leon3
vendor: gaisler
socs:
- name: leon3
``` | /content/code_sandbox/boards/qemu/leon3/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```unknown
/*
*
*/
/dts-v1/;
#include <gaisler/leon3soc.dtsi>
/ {
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sram = &ram0;
};
};
&timer0 {
interrupts = <6>;
};
&uart0 {
interrupts = <3>;
status = "okay";
};
&ram0 {
reg = <0x40000000 0x40000000>;
};
``` | /content/code_sandbox/boards/qemu/leon3/qemu_leon3.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 115 |
```yaml
identifier: qemu_leon3
name: QEMU Emulation for LEON3
type: qemu
simulation: qemu
arch: sparc
ram: 1048576
flash: 524288
toolchain:
- zephyr
- xtools
supported:
- netif
testing:
default: true
ignore_tags:
- net
- bluetooth
``` | /content/code_sandbox/boards/qemu/leon3/qemu_leon3.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 85 |
```unknown
#
if BOARD_QEMU_LEON3
config UART_INTERRUPT_DRIVEN
default y
endif
``` | /content/code_sandbox/boards/qemu/leon3/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 21 |
```unknown
#
config BOARD_QEMU_LEON3
select QEMU_TARGET
select CPU_HAS_FPU
``` | /content/code_sandbox/boards/qemu/leon3/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 21 |
```restructuredtext
.. _qemu_nios2:
Altera Nios-II Emulation (QEMU)
###############################
Overview
********
This board configuration will use QEMU to emulate the Altera MAX 10 platform.
This configuration provides support for an Altera Nios-II CPU and these devices:
* Internal Interrupt Controller
* Altera Avalon Timer
* NS16550 UART
.. note::
This board configuration makes no claims about its suitability for use
with an actual ti_lm3s6965 hardware system, or any other hardware system.
Hardware
********
Supported Features
==================
The following hardware features are supported:
+--------------+------------+----------------------+
| Interface | Controller | Driver/Component |
+==============+============+======================+
| IIC | on-chip | Internal interrupt |
| | | controller |
+--------------+------------+----------------------+
| NS16550 | on-chip | serial port |
| UART | | |
+--------------+------------+----------------------+
| TIMER | on-chip | system clock |
+--------------+------------+----------------------+
The kernel currently does not support other hardware features on this platform.
Devices
========
System Clock
------------
This board configuration uses a system clock frequency of 50 MHz.
Serial Port
-----------
This board configuration uses a single serial communication channel with the
CPU's UART0.
If SLIP networking is enabled (see below), an additional serial port will be
used for it.
Known Problems or Limitations
==============================
The following platform features are unsupported:
* Memory protection through optional MPU. However, using a XIP kernel
effectively provides TEXT/RODATA write protection in ROM.
* Writing to the hardware's flash memory
* Serial port in Direct Memory Access (DMA) mode
* Serial Peripheral Interface (SPI) flash
* General-Purpose Input/Output (GPIO)
* Inter-Integrated Circuit (I2C)
* Ethernet
Programming and Debugging
*************************
Use this configuration to run basic Zephyr applications and kernel tests in the QEMU
emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample:
.. zephyr-app-commands::
:zephyr-app: samples/synchronization
:host-os: unix
:board: qemu_nios2
:goals: run
This will build an image with the synchronization sample app, boot it using
QEMU, and display the following console output:
.. code-block:: console
***** BOOTING ZEPHYR OS v1.8.99 - BUILD: Jun 27 2017 13:09:26 *****
threadA: Hello World from arm!
threadB: Hello World from arm!
threadA: Hello World from arm!
threadB: Hello World from arm!
threadA: Hello World from arm!
threadB: Hello World from arm!
threadA: Hello World from arm!
threadB: Hello World from arm!
threadA: Hello World from arm!
threadB: Hello World from arm!
Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`.
Debugging
=========
Refer to the detailed overview about :ref:`application_debugging`.
Networking
==========
The board supports SLIP networking over an emulated serial port
(``CONFIG_NET_SLIP_TAP=y``). The detailed setup is described in
:ref:`networking_with_qemu`.
References
**********
* `CPU Documentation <path_to_url`_
* `Nios II Processor Booting Methods in MAX 10 FPGA Devices <path_to_url`_
* `Embedded Peripherals IP User Guide <path_to_url`_
* `MAX 10 FPGA Configuration User Guide <path_to_url`_
* `MAX 10 FPGA Development Kit User Guide <path_to_url`_
* `Nios II Command-Line Tools <path_to_url`_
* `Quartus II Scripting Reference Manual <path_to_url`_
.. _Altera Lite Distribution: path_to_url
``` | /content/code_sandbox/boards/qemu/nios2/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 851 |
```unknown
#
config BOARD_QEMU_LEON3
select SOC_LEON3
``` | /content/code_sandbox/boards/qemu/leon3/Kconfig.qemu_leon3 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 16 |
```yaml
identifier: qemu_cortex_a53/qemu_cortex_a53/smp
name: QEMU Emulation for Cortex-A53 SMP
type: qemu
simulation: qemu
arch: arm64
toolchain:
- zephyr
- cross-compile
ram: 128
supported:
- smp
testing:
default: true
ignore_tags:
- net
- bluetooth
vendor: qemu
``` | /content/code_sandbox/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_smp.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 92 |
```cmake
set(SUPPORTED_EMU_PLATFORMS qemu)
set(QEMU_ARCH aarch64)
set(QEMU_CPU_TYPE_${ARCH} cortex-a53)
if(CONFIG_ARMV8_A_NS)
set(QEMU_MACH virt,gic-version=3)
else()
set(QEMU_MACH virt,secure=on,gic-version=3)
endif()
set(QEMU_FLAGS_${ARCH}
-cpu ${QEMU_CPU_TYPE_${ARCH}}
-nographic
-machine ${QEMU_MACH}
)
if(CONFIG_XIP)
# This should be equivalent to
# ... -drive if=pflash,file=build/zephyr/zephyr.bin,format=raw
# without having to pad the binary file to the FLASH size
set(QEMU_KERNEL_OPTION
-bios ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.bin
)
endif()
board_set_debugger_ifnset(qemu)
``` | /content/code_sandbox/boards/qemu/cortex_a53/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 194 |
```restructuredtext
.. _qemu_leon3:
LEON3 Emulation (QEMU)
######################
Overview
********
The LEON3 QEMU board configuration is used to emulate the LEON3 processor.
Programming and Debugging
*************************
Applications for the ``qemu_leon3`` board configuration can be built and run in
the usual way for emulated boards (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Flashing
========
While this board is emulated and you can't "flash" it, you can use this
configuration to run basic Zephyr applications and kernel tests in the QEMU
emulated environment. For example, with the :zephyr:code-sample:`synchronization` sample:
.. zephyr-app-commands::
:zephyr-app: samples/synchronization
:host-os: unix
:board: qemu_leon3
:goals: run
This will build an image with the synchronization sample app, boot it using
QEMU, and display the following console output:
.. code-block:: console
*** Booting Zephyr OS build zephyr-v2.4.0-27-g7b37fdd5303b ***
threadA: Hello World from qemu_leon3!
threadB: Hello World from qemu_leon3!
threadA: Hello World from qemu_leon3!
threadB: Hello World from qemu_leon3!
threadA: Hello World from qemu_leon3!
threadB: Hello World from qemu_leon3!
threadA: Hello World from qemu_leon3!
threadB: Hello World from qemu_leon3!
threadA: Hello World from qemu_leon3!
threadB: Hello World from qemu_leon3!
Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`.
Debugging
=========
Refer to the detailed overview about :ref:`application_debugging`.
``` | /content/code_sandbox/boards/qemu/leon3/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 417 |
```unknown
CONFIG_ARM_ARCH_TIMER=y
# Cache management
CONFIG_CACHE_MANAGEMENT=y
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable serial port
CONFIG_UART_INTERRUPT_DRIVEN=y
# Avoid timing skew in tests
CONFIG_QEMU_ICOUNT=y
# Enable XIP
CONFIG_XIP=y
``` | /content/code_sandbox/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_xip_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 75 |
```unknown
CONFIG_ARM_ARCH_TIMER=y
# Cache management
CONFIG_CACHE_MANAGEMENT=y
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable serial port
CONFIG_UART_INTERRUPT_DRIVEN=y
# Avoid timing skew in tests
CONFIG_QEMU_ICOUNT=y
``` | /content/code_sandbox/boards/qemu/cortex_a53/qemu_cortex_a53_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 65 |
```unknown
config BOARD_QEMU_CORTEX_A53
select SOC_QEMU_CORTEX_A53
``` | /content/code_sandbox/boards/qemu/cortex_a53/Kconfig.qemu_cortex_a53 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 20 |
```yaml
identifier: qemu_cortex_a53/qemu_cortex_a53/xip
name: QEMU Emulation for Cortex-A53 (XIP)
type: qemu
simulation: qemu
arch: arm64
toolchain:
- zephyr
- cross-compile
ram: 128
testing:
default: true
only_tags:
- xip
vendor: qemu
``` | /content/code_sandbox/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_xip.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 84 |
```unknown
CONFIG_ARM_ARCH_TIMER=y
# Cache management
CONFIG_CACHE_MANAGEMENT=y
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable serial port
CONFIG_UART_INTERRUPT_DRIVEN=y
# icount does not work well with SMP
CONFIG_QEMU_ICOUNT=n
# We have multiple QEMU-A53 boards, so let us exercise ARMV8_A_NS on this one
# (plus it is needed for SMP)
CONFIG_ARMV8_A_NS=y
# PSCI is supported with NS
CONFIG_PM_CPU_OPS=y
# SMP-related
CONFIG_SMP=y
CONFIG_MP_MAX_NUM_CPUS=2
CONFIG_TIMEOUT_64BIT=y
``` | /content/code_sandbox/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_smp_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 148 |
```unknown
/*
*
*
*/
#include "qemu_cortex_a53.dts"
``` | /content/code_sandbox/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_smp.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 16 |
```yaml
board:
name: qemu_cortex_a53
vendor: arm
socs:
- name: qemu_cortex_a53
variants:
- name: smp
- name: xip
``` | /content/code_sandbox/boards/qemu/cortex_a53/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 48 |
```yaml
identifier: qemu_cortex_a53
name: QEMU Emulation for Cortex-A53
type: qemu
simulation: qemu
arch: arm64
toolchain:
- zephyr
- cross-compile
ram: 128
testing:
default: true
ignore_tags:
- net
- bluetooth
vendor: qemu
``` | /content/code_sandbox/boards/qemu/cortex_a53/qemu_cortex_a53.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 76 |
```unknown
/*
*
*
*/
#include "qemu_cortex_a53.dts"
``` | /content/code_sandbox/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_xip.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 16 |
```unknown
/*
*
*
*/
/dts-v1/;
#include <arm64/qemu/qemu-virt-a53.dtsi>
/ {
model = "QEMU Cortex-A53";
compatible = "qemu,arm-cortex-a53";
psci {
compatible = "arm,psci-0.2";
method = "hvc";
};
chosen {
zephyr,sram = &sram0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,flash = &flash0;
zephyr,pcie-controller = &pcie;
};
soc {
sram0: memory@40000000 {
compatible = "mmio-sram";
reg = <0x0 0x40000000 0x0 DT_SIZE_M(128)>;
};
};
};
&uart0 {
status = "okay";
current-speed = <115200>;
};
&pcie {
eth0: pcie@1,0 {
compatible = "intel,e1000";
vendor-id = <0x8086>;
device-id = <0x100e>;
interrupts = <1>;
interrupt-parent = <&pcie>;
reg = <0x0800 0 0 0 0>;
status = "okay";
};
};
``` | /content/code_sandbox/boards/qemu/cortex_a53/qemu_cortex_a53.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 302 |
```unknown
config QEMU_CORTEX_A53_ETH_E1000
bool
default y if !NET_TEST
depends on BOARD_QEMU_CORTEX_A53 && NETWORKING && DT_HAS_INTEL_E1000_ENABLED
select ETH_E1000
select NET_L2_ETHERNET
select PCIE
select PCIE_CONTROLLER
select PCIE_ECAM
``` | /content/code_sandbox/boards/qemu/cortex_a53/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 75 |
```unknown
if BOARD_QEMU_CORTEX_A53
config BUILD_OUTPUT_BIN
default y
config MAX_THREAD_BYTES
default 3
if NETWORKING
choice NET_QEMU_NETWORKING
default NET_QEMU_ETHERNET if QEMU_CORTEX_A53_ETH_E1000
endchoice
config NET_DRIVERS
default n if QEMU_CORTEX_A53_ETH_E1000
endif # NETWORKING
# QEMU PCI requires at least 256M of virtual space
config KERNEL_VM_SIZE
default 0x80000000 if PCIE
# QEMU PCI requires physical addresses with more than 32 bits
choice ARM64_VA_BITS
default ARM64_VA_BITS_40 if PCIE
endchoice
choice ARM64_PA_BITS
default ARM64_PA_BITS_40 if PCIE
endchoice
if QEMU_ICOUNT
config QEMU_ICOUNT_SHIFT
default 4
config QEMU_ICOUNT_SLEEP
default y
endif # QEMU_ICOUNT
endif # BOARD_QEMU_CORTEX_A53
``` | /content/code_sandbox/boards/qemu/cortex_a53/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 215 |
```restructuredtext
.. _qemu_cortex_a53:
ARM Cortex-A53 Emulation (QEMU)
###############################
Overview
********
This board configuration will use QEMU to emulate a generic Cortex-A53 hardware
platform.
This configuration provides support for an ARM Cortex-A53 CPU and these
devices:
* GIC-400 interrupt controller
* ARM architected timer
* PL011 UART controller
Hardware
********
Supported Features
==================
The following hardware features are supported:
+--------------+------------+----------------------+
| Interface | Controller | Driver/Component |
+==============+============+======================+
| GIC | on-chip | interrupt controller |
+--------------+------------+----------------------+
| PL011 UART | on-chip | serial port |
+--------------+------------+----------------------+
| ARM TIMER | on-chip | system clock |
+--------------+------------+----------------------+
The kernel currently does not support other hardware features on this platform.
Devices
========
System Clock
------------
This board configuration uses a system clock frequency of 62.5 MHz.
Serial Port
-----------
This board configuration uses a single serial communication channel with the
CPU's UART0.
Known Problems or Limitations
==============================
The following platform features are unsupported:
* Writing to the hardware's flash memory
Programming and Debugging
*************************
Use this configuration to run basic Zephyr applications and kernel tests in the QEMU
emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample:
.. zephyr-app-commands::
:zephyr-app: samples/synchronization
:host-os: unix
:board: qemu_cortex_a53
:goals: run
This will build an image with the synchronization sample app, boot it using
QEMU, and display the following console output:
.. code-block:: console
***** Booting Zephyr OS build zephyr-v2.0.0-1657-g99d310da48e5 *****
threadA: Hello World from qemu_cortex_a53!
threadB: Hello World from qemu_cortex_a53!
threadA: Hello World from qemu_cortex_a53!
threadB: Hello World from qemu_cortex_a53!
threadA: Hello World from qemu_cortex_a53!
threadB: Hello World from qemu_cortex_a53!
threadA: Hello World from qemu_cortex_a53!
threadB: Hello World from qemu_cortex_a53!
Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`.
Debugging
=========
Refer to the detailed overview about :ref:`application_debugging`.
Networking
==========
The board supports the QEMU built-in Ethernet adapter to connect to the host
system. See :ref:`networking_with_eth_qemu` for details.
It is also possible to use SLIP networking over an emulated serial port.
Although this board only supports a single UART, so subsystems like logging
and shell would need to be disabled, therefore this is not directly supported.
References
**********
1. (ID050815) ARM Cortex-A Series - Programmers Guide for ARMv8-A
2. (ID070919) Arm Architecture Reference Manual - Armv8, for Armv8-A architecture profile
3. (ARM DAI 0527A) Application Note Bare-metal Boot Code for ARMv8-A Processors
4. AArch64 Exception and Interrupt Handling
5. Fundamentals of ARMv8-A
``` | /content/code_sandbox/boards/qemu/cortex_a53/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 737 |
```unknown
# QEMU Cortex-M0 board configuration
config BOARD_QEMU_CORTEX_M0
select SOC_NRF51822_QFAA
``` | /content/code_sandbox/boards/qemu/cortex_m0/Kconfig.qemu_cortex_m0 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 29 |
```cmake
#
#
set(SUPPORTED_EMU_PLATFORMS qemu)
set(QEMU_CPU_TYPE_${ARCH} cortex-m0)
set(QEMU_FLAGS_${ARCH}
-cpu ${QEMU_CPU_TYPE_${ARCH}}
-machine microbit
-nographic
-vga none
)
board_set_debugger_ifnset(qemu)
``` | /content/code_sandbox/boards/qemu/cortex_m0/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 71 |
```unknown
/*
*/
&pinctrl {
uart0_default: uart0_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 24)>,
<NRF_PSEL(UART_RX, 0, 25)>;
};
};
uart0_sleep: uart0_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 24)>,
<NRF_PSEL(UART_RX, 0, 25)>;
low-power-enable;
};
};
};
``` | /content/code_sandbox/boards/qemu/cortex_m0/qemu_cortex_m0-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 124 |
```c
/*
*
*/
#include <soc.h>
#include <zephyr/init.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/nrf_clock_control.h>
#include <zephyr/drivers/timer/system_timer.h>
#include <zephyr/sys_clock.h>
#include <hal/nrf_timer.h>
#include <zephyr/spinlock.h>
#include <zephyr/irq.h>
#define TIMER NRF_TIMER0
#define COUNTER_MAX 0xFFFFFFFFUL
#define COUNTER_HALF_SPAN 0x80000000UL
#define CYC_PER_TICK (sys_clock_hw_cycles_per_sec() \
/ CONFIG_SYS_CLOCK_TICKS_PER_SEC)
#define MAX_TICKS ((COUNTER_HALF_SPAN - CYC_PER_TICK) / CYC_PER_TICK)
#define MAX_CYCLES (MAX_TICKS * CYC_PER_TICK)
static struct k_spinlock lock;
static uint32_t last_count;
static uint32_t counter_sub(uint32_t a, uint32_t b)
{
return (a - b) & COUNTER_MAX;
}
static void set_comparator(uint32_t cyc)
{
nrf_timer_cc_set(TIMER, NRF_TIMER_CC_CHANNEL0, cyc & COUNTER_MAX);
}
static uint32_t get_comparator(void)
{
return nrf_timer_cc_get(TIMER, NRF_TIMER_CC_CHANNEL0);
}
static void event_clear(void)
{
nrf_timer_event_clear(TIMER, NRF_TIMER_EVENT_COMPARE0);
}
static void int_disable(void)
{
nrf_timer_int_disable(TIMER, NRF_TIMER_INT_COMPARE0_MASK);
}
static void int_enable(void)
{
nrf_timer_int_enable(TIMER, NRF_TIMER_INT_COMPARE0_MASK);
}
static uint32_t counter(void)
{
nrf_timer_task_trigger(TIMER,
nrf_timer_capture_task_get(NRF_TIMER_CC_CHANNEL1));
return nrf_timer_cc_get(TIMER, NRF_TIMER_CC_CHANNEL1);
}
/* Function ensures that previous CC value will not set event */
static void prevent_false_prev_evt(void)
{
uint32_t now = counter();
uint32_t prev_val;
/* First take care of a risk of an event coming from CC being set to
* next tick. Reconfigure CC to future (now tick is the furthest
* future). If CC was set to next tick we need to wait for up to 0.5us
* (half of 1M tick) and clean potential event. After that time there
* is no risk of unwanted event.
*/
prev_val = get_comparator();
event_clear();
set_comparator(now);
if (counter_sub(prev_val, now) == 1) {
k_busy_wait(1);
event_clear();
}
/* Clear interrupt that may have fired as we were setting the
* comparator.
*/
NVIC_ClearPendingIRQ(TIMER0_IRQn);
}
/* If settings is next tick from now, function attempts to set next tick. If
* counter progresses during that time it means that 1 tick elapsed and
* interrupt is set pending.
*/
static void handle_next_tick_case(uint32_t t)
{
set_comparator(t + 2U);
while (t != counter()) {
/* already expired, tick elapsed but event might not be
* generated. Trigger interrupt.
*/
t = counter();
set_comparator(t + 2U);
}
}
/* Function safely sets absolute alarm. It assumes that provided value is
* less than MAX_TICKS from now. It detects late setting and also handles
* +1 tick case.
*/
static void set_absolute_ticks(uint32_t abs_val)
{
uint32_t diff;
uint32_t t = counter();
diff = counter_sub(abs_val, t);
if (diff == 1U) {
handle_next_tick_case(t);
return;
}
set_comparator(abs_val);
}
/* Sets relative ticks alarm from any context. Function is lockless. It only
* blocks TIMER interrupt.
*/
static void set_protected_absolute_ticks(uint32_t ticks)
{
int_disable();
prevent_false_prev_evt();
set_absolute_ticks(ticks);
int_enable();
}
void timer0_nrf_isr(void *arg)
{
ARG_UNUSED(arg);
event_clear();
uint32_t t = get_comparator();
uint32_t dticks = counter_sub(t, last_count) / CYC_PER_TICK;
last_count += dticks * CYC_PER_TICK;
if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
/* protection is not needed because we are in the TIMER interrupt
* so it won't get preempted by the interrupt.
*/
set_absolute_ticks(last_count + CYC_PER_TICK);
}
sys_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ? dticks : (dticks > 0));
}
void sys_clock_set_timeout(int32_t ticks, bool idle)
{
ARG_UNUSED(idle);
uint32_t cyc;
if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
return;
}
ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
uint32_t unannounced = counter_sub(counter(), last_count);
/* If we haven't announced for more than half the 24-bit wrap
* duration, then force an announce to avoid loss of a wrap
* event. This can happen if new timeouts keep being set
* before the existing one triggers the interrupt.
*/
if (unannounced >= COUNTER_HALF_SPAN) {
ticks = 0;
}
/* Get the cycles from last_count to the tick boundary after
* the requested ticks have passed starting now.
*/
cyc = ticks * CYC_PER_TICK + 1 + unannounced;
cyc += (CYC_PER_TICK - 1);
cyc = (cyc / CYC_PER_TICK) * CYC_PER_TICK;
/* Due to elapsed time the calculation above might produce a
* duration that laps the counter. Don't let it.
*/
if (cyc > MAX_CYCLES) {
cyc = MAX_CYCLES;
}
cyc += last_count;
set_protected_absolute_ticks(cyc);
/* FIXME - QEMU requires clearing the events when setting the comparator,
* but the TIMER peripheral HW does not need this. Remove when fixed in
* QEMU.
*/
event_clear();
NVIC_ClearPendingIRQ(TIMER0_IRQn);
}
uint32_t sys_clock_elapsed(void)
{
if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
return 0;
}
k_spinlock_key_t key = k_spin_lock(&lock);
uint32_t ret = counter_sub(counter(), last_count) / CYC_PER_TICK;
k_spin_unlock(&lock, key);
return ret;
}
uint32_t sys_clock_cycle_get_32(void)
{
k_spinlock_key_t key = k_spin_lock(&lock);
uint32_t ret = counter_sub(counter(), last_count) + last_count;
k_spin_unlock(&lock, key);
return ret;
}
static int sys_clock_driver_init(void)
{
nrf_timer_prescaler_set(TIMER, NRF_TIMER_FREQ_1MHz);
nrf_timer_bit_width_set(TIMER, NRF_TIMER_BIT_WIDTH_32);
IRQ_CONNECT(TIMER0_IRQn, 1, timer0_nrf_isr, 0, 0);
irq_enable(TIMER0_IRQn);
nrf_timer_task_trigger(TIMER, NRF_TIMER_TASK_CLEAR);
nrf_timer_task_trigger(TIMER, NRF_TIMER_TASK_START);
if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
set_comparator(counter() + CYC_PER_TICK);
}
event_clear();
NVIC_ClearPendingIRQ(TIMER0_IRQn);
int_enable();
return 0;
}
SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
``` | /content/code_sandbox/boards/qemu/cortex_m0/nrf_timer_timer.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,645 |
```yaml
identifier: qemu_cortex_m0
name: QEMU Emulation for Cortex-M0
type: qemu
simulation: qemu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 16
flash: 256
testing:
default: true
ignore_tags:
- net
- bluetooth
``` | /content/code_sandbox/boards/qemu/cortex_m0/qemu_cortex_m0.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 82 |
```unknown
/*
*
*/
/dts-v1/;
#include <nordic/nrf51822_qfaa.dtsi>
#include "qemu_cortex_m0-pinctrl.dtsi"
/ {
model = "QEMU Cortex-M0";
compatible = "bbc,qemu-microbit";
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,bt-mon-uart = &uart0;
zephyr,bt-c2h-uart = &uart0;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
};
aliases {
watchdog0 = &wdt0;
};
};
&gpiote {
status = "okay";
};
&gpio0 {
status = "okay";
};
&uart0 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-1 = <&uart0_sleep>;
pinctrl-names = "default", "sleep";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0x8000>;
};
slot0_partition: partition@8000 {
label = "image-0";
reg = <0x00008000 0x1a000>;
};
slot1_partition: partition@22000 {
label = "image-1";
reg = <0x00022000 0x1a000>;
};
scratch_partition: partition@3c000 {
label = "image-scratch";
reg = <0x0003c000 0x2000>;
};
storage_partition: partition@3e000 {
label = "storage";
reg = <0x0003e000 0x00002000>;
};
};
};
``` | /content/code_sandbox/boards/qemu/cortex_m0/qemu_cortex_m0.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 472 |
```yaml
board:
name: qemu_cortex_m0
vendor: nordic
socs:
- name: nrf51822
``` | /content/code_sandbox/boards/qemu/cortex_m0/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 31 |
```unknown
CONFIG_QEMU_ICOUNT_SHIFT=6
# Enable GPIO
CONFIG_GPIO=y
# Clock control
CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# icount is kinda broken when the NRF timer emulation is used
CONFIG_QEMU_ICOUNT=n
``` | /content/code_sandbox/boards/qemu/cortex_m0/qemu_cortex_m0_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 79 |
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