text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```yaml
identifier: qemu_x86/atom/nommu
name: QEMU Emulation for X86 (MMU disabled)
type: qemu
arch: x86
simulation: qemu
toolchain:
- zephyr
- xtools
testing:
default: true
only_tags:
- kernel
- userspace
vendor: qemu
``` | /content/code_sandbox/boards/qemu/x86/qemu_x86_atom_nommu.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 77 |
```unknown
CONFIG_PIC_DISABLE=y
CONFIG_LOAPIC=y
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000
CONFIG_TEST_RANDOM_GENERATOR=y
CONFIG_X86_MMU=y
CONFIG_DEBUG_INFO=y
CONFIG_SCHED_SCALABLE=y
CONFIG_WAITQ_SCALABLE=y
CONFIG_X86_VERY_EARLY_CONSOLE=y
``` | /content/code_sandbox/boards/qemu/x86/qemu_x86_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 86 |
```unknown
/*
*
*/
/dts-v1/;
#include <mem.h>
#ifndef DT_DRAM_BASE
#define DT_DRAM_BASE 0
#endif
#ifndef DT_DRAM_SIZE
#define DT_DRAM_SIZE DT_SIZE_K(4096)
#endif
#include <intel/lakemont.dtsi>
/ {
model = "QEMU X86 (Lakemont) emulator";
compatible = "qemu,x86_lakemont_emulator";
aliases {
uart-0 = &uart0;
};
chosen {
zephyr,sram = &dram0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
};
dram0: memory@0 {
device_type = "memory";
reg = <DT_DRAM_BASE DT_DRAM_SIZE>;
};
soc {
uart0: uart@3f8 {
compatible = "ns16550";
reg = <0x000003f8 0x100>;
io-mapped;
clock-frequency = <1843200>;
interrupts = <4 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
interrupt-parent = <&intc>;
current-speed = <115200>;
reg-shift = <2>;
status = "okay";
};
hpet: hpet@fed00000 {
compatible = "intel,hpet";
reg = <0xfed00000 0x400>;
interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>;
interrupt-parent = <&intc>;
status = "okay";
};
};
};
``` | /content/code_sandbox/boards/qemu/x86/qemu_x86_lakemont.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 358 |
```unknown
CONFIG_PIC_DISABLE=y
CONFIG_LOAPIC=y
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000
CONFIG_TEST_RANDOM_GENERATOR=y
CONFIG_X86_MMU=y
CONFIG_DEBUG_INFO=y
CONFIG_SCHED_SCALABLE=y
CONFIG_WAITQ_SCALABLE=y
CONFIG_X86_VERY_EARLY_CONSOLE=y
CONFIG_SRAM_OFFSET=0x100000
CONFIG_KERNEL_VM_SIZE=0x400000
CONFIG_KERNEL_VM_BASE=0x40000000
CONFIG_KERNEL_VM_OFFSET=0
CONFIG_LINKER_USE_BOOT_SECTION=y
CONFIG_LINKER_USE_PINNED_SECTION=y
# For now, the mapped stacks require physical addresses
# and cannot deal with mapping a stack with virtual
# address. So make sure memory mapped stack is not
# enabled.
CONFIG_THREAD_STACK_MEM_MAPPED=n
``` | /content/code_sandbox/boards/qemu/x86/qemu_x86_atom_virt_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 187 |
```unknown
/*
*
*/
#include "qemu_x86.dts"
``` | /content/code_sandbox/boards/qemu/x86/qemu_x86_atom_nopae.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 13 |
```unknown
#
config BOARD_QEMU_X86_64
select SOC_ATOM
``` | /content/code_sandbox/boards/qemu/x86/Kconfig.qemu_x86_64 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 15 |
```unknown
/*
*
*/
#define DT_DRAM_BASE 0x100000
#define DT_DRAM_SIZE DT_SIZE_K(256)
#include "qemu_x86.dts"
``` | /content/code_sandbox/boards/qemu/x86/qemu_x86_tiny.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```unknown
/dts-v1/;
#include <mem.h>
#ifndef DT_DRAM_BASE
#define DT_DRAM_BASE 0
#endif
#ifndef DT_DRAM_SIZE
#define DT_DRAM_SIZE DT_SIZE_M(32)
#endif
#define DT_FLASH_SIZE DT_SIZE_K(4096)
#include <intel/atom.dtsi>
#include <zephyr/dt-bindings/pcie/pcie.h>
/ {
model = "QEMU X86 emulator";
compatible = "qemu,x86_emulator";
flash0: flash@500000 {
compatible = "soc-nv-flash";
reg = <0x00500000 DT_FLASH_SIZE>;
};
aliases {
uart-0 = &uart0;
uart-1 = &uart1;
eeprom-0 = &eeprom0;
eeprom-1 = &eeprom1;
rtc = &rtc;
};
chosen {
zephyr,sram = &dram0;
zephyr,flash = &flash0;
zephyr,console = &uart0;
zephyr,bt-hci = &bt_hci_uart;
zephyr,shell-uart = &uart0;
zephyr,uart-pipe = &uart1;
zephyr,bt-mon-uart = &uart1;
zephyr,code-partition = &slot0_partition;
zephyr,flash-controller = &sim_flash;
zephyr,ieee802154 = &ieee802154;
zephyr,canbus = &can0;
};
pcie0: pcie0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "pcie-controller";
acpi-hid = "PNP0A08";
ranges;
can0: can0 {
compatible = "kvaser,pcican";
status = "okay";
vendor-id = <0x10e8>;
device-id = <0x8406>;
interrupts = <11 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
can-transceiver {
max-bitrate = <1000000>;
};
};
eth0: eth0 {
compatible = "intel,e1000";
vendor-id = <0x8086>;
device-id = <0x100e>;
interrupts = <11 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
interrupt-parent = <&intc>;
status = "okay";
};
};
sim_flash: sim_flash {
compatible = "zephyr,sim-flash";
#address-cells = <1>;
#size-cells = <1>;
erase-value = <0xff>;
flash_sim0: flash_sim@0 {
compatible = "soc-nv-flash";
reg = <0x00000000 DT_SIZE_K(1024)>;
erase-block-size = <1024>;
write-block-size = <4>;
};
};
eeprom1: eeprom1 {
status = "okay";
compatible = "zephyr,emu-eeprom";
size = <DT_SIZE_K(4)>;
pagesize = <DT_SIZE_K(8)>;
partition = <&eepromemu_partition>;
rambuf;
};
eeprom0: eeprom0 {
status = "okay";
compatible = "zephyr,sim-eeprom";
size = <DT_SIZE_K(4)>;
};
ieee802154: ieee802154 {
compatible = "zephyr,ieee802154-uart-pipe";
};
};
&uart0 {
status = "okay";
current-speed = <115200>;
};
&uart1 {
status = "okay";
current-speed = <115200>;
bt_hci_uart: bt_hci_uart {
compatible = "zephyr,bt-hci-uart";
status = "okay";
};
};
&hpet {
status = "okay";
};
&flash_sim0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/*
* Storage partition will be used by FCB/LittleFS/NVS
* if enabled.
*/
storage_partition: partition@1000 {
label = "storage";
reg = <0x00001000 0x00010000>;
};
slot0_partition: partition@11000 {
label = "image-0";
reg = <0x00011000 0x00010000>;
};
slot1_partition: partition@21000 {
label = "image-1";
reg = <0x00021000 0x00010000>;
};
eepromemu_partition: partition@31000 {
label = "eeprom-emu";
reg = <0x00031000 0x00010000>;
};
};
};
``` | /content/code_sandbox/boards/qemu/x86/qemu_x86.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,107 |
```unknown
/*
*
*/
#include "qemu_x86.dts"
``` | /content/code_sandbox/boards/qemu/x86/qemu_x86_atom_xip.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 13 |
```unknown
if BOARD_QEMU_X86 || BOARD_QEMU_X86_64 || BOARD_QEMU_X86_LAKEMONT || BOARD_QEMU_X86_TINY
# The EEPROM emulator must be initialized after the flash simulator
config EEPROM_INIT_PRIORITY
default 60
depends on EEPROM
config BUILD_OUTPUT_BIN
default n
config QEMU_TARGET
default y
config HAS_COVERAGE_SUPPORT
default y
endif # BOARD_QEMU_X86 || BOARD_QEMU_X86_64 || BOARD_QEMU_X86_LAKEMONT || BOARD_QEMU_X86_TINY
if BOARD_QEMU_X86
config FLASH_SIMULATOR
default y
depends on FLASH
config KERNEL_VM_SIZE
default 0x10000000 if ACPI
config MULTIBOOT
default y
config MULTIBOOT_INFO
default y if MULTIBOOT
config MULTIBOOT_MEMMAP
default y if MULTIBOOT
config QEMU_ICOUNT
default n if HPET_TIMER && SHELL
config QEMU_ICOUNT_SHIFT
default 5
endif # BOARD_QEMU_X86
if BOARD_QEMU_X86_64
config KERNEL_VM_SIZE
default 0x10000000 if ACPI
endif # BOARD_QEMU_X86_64
if BOARD_QEMU_X86_LAKEMONT
config KERNEL_VM_SIZE
default 0x400000
config MULTIBOOT
# This is needed for QEMU to load the ELF image
default y
config X86_PC_COMPATIBLE
# QEMU presents a PC-compatible machine
default y
config QEMU_ICOUNT
default n if HPET_TIMER && SHELL
config QEMU_ICOUNT_SHIFT
default 5
endif # BOARD_QEMU_X86_LAKEMONT
if BOARD_QEMU_X86_TINY
config KERNEL_VM_SIZE
default 0x400000
config MULTIBOOT
# This is needed for QEMU to load the ELF image
default y
config X86_PC_COMPATIBLE
# QEMU presents a PC-compatible machine
default y
config QEMU_ICOUNT
default n if HPET_TIMER && SHELL
config QEMU_ICOUNT_SHIFT
default 5
config HAVE_CUSTOM_LINKER_SCRIPT
default y
config CUSTOM_LINKER_SCRIPT
default "${ZEPHYR_BASE}/boards/qemu/x86/qemu_x86_tiny.ld"
config X86_EXTRA_PAGE_TABLE_PAGES
# This is needed for gen_mmu.py to map the flash into memory
default 2 if DEMAND_PAGING && !LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT
config DEMAND_PAGING_PAGE_FRAMES_RESERVE
# Need to accommodate the heap for newlib or common malloc in libc-hook.c
default 6 if NEWLIB_LIBC || (COMMON_LIBC_MALLOC && COMMON_LIBC_MALLOC_ARENA_SIZE != 0)
endif # BOARD_QEMU_X86_TINY
``` | /content/code_sandbox/boards/qemu/x86/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 600 |
```unknown
#
config BOARD_QEMU_X86
bool
select CPU_HAS_FPU
config BOARD_QEMU_X86_64
bool
select X86_64
config BOARD_QEMU_X86_LAKEMONT
bool
select CPU_HAS_FPU
config BOARD_QEMU_X86_TINY
bool
select CPU_HAS_FPU
``` | /content/code_sandbox/boards/qemu/x86/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 70 |
```unknown
#
config BOARD_QEMU_X86_LAKEMONT
select SOC_LAKEMONT
``` | /content/code_sandbox/boards/qemu/x86/Kconfig.qemu_x86_lakemont | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 20 |
```unknown
CONFIG_PIC_DISABLE=y
CONFIG_LOAPIC=y
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000
CONFIG_TEST_RANDOM_GENERATOR=y
CONFIG_X86_MMU=n
CONFIG_DEBUG_INFO=y
CONFIG_SCHED_DUMB=y
CONFIG_WAITQ_DUMB=y
CONFIG_X86_VERY_EARLY_CONSOLE=n
``` | /content/code_sandbox/boards/qemu/x86/qemu_x86_atom_nommu_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 84 |
```yaml
identifier: qemu_x86_lakemont
name: QEMU Emulation for X86 (Lakemont)
type: qemu
simulation: qemu
arch: x86
toolchain:
- zephyr
- xtools
- llvm
testing:
default: true
only_tags:
- kernel
ignore_tags:
- benchmark
vendor: qemu
``` | /content/code_sandbox/boards/qemu/x86/qemu_x86_lakemont.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 84 |
```restructuredtext
.. _qemu_x86:
X86 Emulation (QEMU)
####################
Overview
********
The X86 QEMU board configuration is used to emulate the X86 architecture.
This board configuration provides support for an x86 Minute IA (Lakemont) CPU
and the following devices:
* HPET
* Advanced Programmable Interrupt Controller (APIC)
* NS16550 UART
Hardware
********
Supported Features
==================
This configuration supports the following hardware features:
+--------------+------------+-----------------------+
| Interface | Controller | Driver/Component |
+==============+============+=======================+
| HPET | on-chip | system clock |
+--------------+------------+-----------------------+
| APIC | on-chip | interrupt controller |
+--------------+------------+-----------------------+
| NS16550 | on-chip | serial port |
| UART | | |
+--------------+------------+-----------------------+
Devices
=======
HPET System Clock Support
-------------------------
The configuration uses an HPET clock frequency of 25 MHz.
Serial Port
-----------
The board configuration uses a single serial communication channel that
uses the NS16550 serial driver operating in polling mode. To override, enable
the UART_INTERRUPT_DRIVEN Kconfig option, which allows the system to be
interrupt-driven.
If SLIP networking is enabled (see below), an additional serial port will be
used for it.
Known Problems or Limitations
=============================
The following platform features are unsupported:
* Isolated Memory Regions
* Serial port in Direct Memory Access (DMA) mode
* Serial Peripheral Interface (SPI) flash
* General-Purpose Input/Output (GPIO)
* Inter-Integrated Circuit (I2C)
* Ethernet
* Supervisor Mode Execution Protection (SMEP)
Programming and Debugging
*************************
Applications for the ``qemu_x86`` board configuration can be built and run in
the usual way for emulated boards (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Flashing
========
While this board is emulated and you can't "flash" it, you can use this
configuration to run basic Zephyr applications and kernel tests in the QEMU
emulated environment. For example, with the :zephyr:code-sample:`synchronization` sample:
.. zephyr-app-commands::
:zephyr-app: samples/synchronization
:host-os: unix
:board: qemu_x86
:goals: run
This will build an image with the synchronization sample app, boot it using
QEMU, and display the following console output:
.. code-block:: console
***** BOOTING ZEPHYR OS v1.8.99 - BUILD: Jun 27 2017 13:09:26 *****
threadA: Hello World from x86!
threadB: Hello World from x86!
threadA: Hello World from x86!
threadB: Hello World from x86!
threadA: Hello World from x86!
threadB: Hello World from x86!
threadA: Hello World from x86!
threadB: Hello World from x86!
threadA: Hello World from x86!
threadB: Hello World from x86!
Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`.
For qemu_x86_64 platform, it also supports to use UEFI bootable method
to run Zephyr applications and kernel tests, but you need to set up
some environment configurations as follows:
* Please install uefi-run in your system environment according to this
reference link path_to_url Note that uefi-run
from snapstore may not work because of strict snap confinements.
The preferred method is installing with cargo.
* Please install OVMF in your system environment according to this
reference link path_to_url
The easiest way is to install a special ``ovmf`` package found in many distros.
For example, use the following command in Ubuntu:
.. code-block:: console
sudo apt install ovmf
* Set system environment variable OVMF_FD_PATH,
for example:
.. code-block:: console
export OVMF_FD_PATH=/usr/share/OVMF/OVMF_CODE.fd
Now you can build application, for example UEFI boot test sample found under
:zephyr_file:`tests/boot/uefi`:
.. zephyr-app-commands::
:zephyr-app: tests/boot/uefi
:host-os: unix
:board: qemu_x86_64
:goals: run
This will build an image with the uefi boot test app, boot it on
qemu_x86_64 using UEFI, and display the following console output:
.. code-block:: console
UEFI Interactive Shell v2.2
EDK II
UEFI v2.70 (EDK II, 0x00010000)
Mapping table
FS0: Alias(s):F0a:;BLK0:
PciRoot(0x0)/Pci(0x1,0x1)/Ata(0x0)
BLK1: Alias(s):
PciRoot(0x0)/Pci(0x1,0x1)/Ata(0x0)
Press ESC in 1 seconds to skip startup.nsh or any other key to continue.
Starting UEFI application...
*** Zephyr EFI Loader ***
Zeroing 524544 bytes of memory at 0x105000
Copying 32768 data bytes to 0x1000 from image offset
Copying 20480 data bytes to 0x100000 from image offset 32768
Copying 540416 data bytes to 0x185100 from image offset 53248
Jumping to Entry Point: 0x112b (48 31 c0 48 31 d2 48)
*** Booting Zephyr OS build zephyr-v2.6.0-1472-g61810ec36d28 ***
Hello World! qemu_x86_64
Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`.
Debugging
=========
Refer to the detailed overview about :ref:`application_debugging`.
Networking
==========
The board supports SLIP networking over an emulated serial port
(``CONFIG_NET_SLIP_TAP=y``). The detailed setup is described in
:ref:`networking_with_qemu`.
It is also possible to use the QEMU built-in Ethernet adapter to connect
to the host system. This is faster than using SLIP and is also the preferred
way. See :ref:`networking_with_eth_qemu` for details.
``` | /content/code_sandbox/boards/qemu/x86/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,444 |
```cmake
set(SUPPORTED_EMU_PLATFORMS qemu)
set(QEMU_binary_suffix riscv64)
set(QEMU_CPU_TYPE_${ARCH} riscv64)
set(QEMU_FLAGS_${ARCH}
-nographic
-machine virt
-bios none
-m 256
)
board_set_debugger_ifnset(qemu)
``` | /content/code_sandbox/boards/qemu/riscv64/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 74 |
```yaml
identifier: qemu_riscv64/qemu_virt_riscv64/smp
name: QEMU Emulation for RISC-V 64-bit SMP
type: qemu
simulation: qemu
arch: riscv
toolchain:
- zephyr
supported:
- netif
- smp
testing:
default: true
ignore_tags:
- net
- bluetooth
``` | /content/code_sandbox/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 88 |
```yaml
identifier: qemu_riscv64
name: QEMU Emulation for RISC-V 64-bit
type: qemu
simulation: qemu
arch: riscv
toolchain:
- zephyr
supported:
- netif
testing:
default: true
ignore_tags:
- net
- bluetooth
``` | /content/code_sandbox/boards/qemu/riscv64/qemu_riscv64.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 72 |
```unknown
config BOARD_QEMU_RISCV64
select SOC_QEMU_VIRT_RISCV64
``` | /content/code_sandbox/boards/qemu/riscv64/Kconfig.qemu_riscv64 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```linker script
/*
*
*/
#include <zephyr/devicetree.h>
#include <zephyr/offsets.h>
#include <zephyr/linker/linker-defs.h>
#include <zephyr/linker/linker-tool.h>
#include <zephyr/sys/util.h>
#include <zephyr/kernel/mm.h>
/* Bounds of physical RAM from DTS */
#define PHYS_RAM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
#define PHYS_RAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
/* Bounds of flash from DTS */
#define FLASH_ROM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
#define FLASH_ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
/* Virtual base address for the kernel; with CONFIG_MMU this is not necessarily
* the same as its physical location, although an identity mapping for RAM
* is still supported by setting CONFIG_KERNEL_VM_BASE=CONFIG_SRAM_BASE_ADDRESS.
*/
#ifdef K_MEM_IS_VM_KERNEL
#define KERNEL_BASE_ADDR \
(CONFIG_KERNEL_VM_BASE + CONFIG_KERNEL_VM_OFFSET)
#define KERNEL_RAM_SIZE \
(CONFIG_KERNEL_VM_SIZE - CONFIG_KERNEL_VM_OFFSET)
#define PHYS_RAM_AVAIL \
(PHYS_RAM_SIZE - CONFIG_SRAM_OFFSET)
#else
#define KERNEL_BASE_ADDR (PHYS_RAM_ADDR + CONFIG_SRAM_OFFSET)
#define KERNEL_RAM_SIZE (PHYS_RAM_SIZE - CONFIG_SRAM_OFFSET)
#endif
/* "kernel RAM" for linker VMA allocations starts at the offset */
/* Physical RAM location where the kernel image is loaded */
#define PHYS_LOAD_ADDR (PHYS_RAM_ADDR + CONFIG_SRAM_OFFSET)
#ifdef CONFIG_USERSPACE
#define SMEM_PARTITION_ALIGN(size) MMU_PAGE_ALIGN_PERM
#define APP_SHARED_ALIGN MMU_PAGE_ALIGN_PERM
#endif
MEMORY
{
#if defined(K_MEM_IS_VM_KERNEL)
ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = PHYS_RAM_AVAIL
#endif
RAM (wx) : ORIGIN = KERNEL_BASE_ADDR, LENGTH = KERNEL_RAM_SIZE
#if defined(CONFIG_DEMAND_PAGING) && !defined(CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT)
FLASH (rw) : ORIGIN = FLASH_ROM_ADDR, LENGTH = FLASH_ROM_SIZE
#endif
/*
* On 32-bit x86, fake memory area for build-time IDT generation data.
*
* It doesn't matter where this region goes as it is stripped from the
* final ELF image. The address doesn't even have to be valid on the
* target. However, it shouldn't overlap any other regions.
*/
IDT_LIST : ORIGIN = 0xFFFF1000, LENGTH = 2K
}
#if defined(K_MEM_IS_VM_KERNEL)
#define ROMABLE_REGION ROM
#define RAMABLE_REGION RAM
#else
#define ROMABLE_REGION RAM
#define RAMABLE_REGION RAM
#endif
#ifdef CONFIG_MMU
#define MMU_PAGE_ALIGN . = ALIGN(CONFIG_MMU_PAGE_SIZE);
#else
#define MMU_PAGE_ALIGN
#endif
#if defined(CONFIG_DEMAND_PAGING) && !defined(CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT)
#undef SECTION_PROLOGUE
#define SECTION_PROLOGUE(name, options, align) \
name options : ALIGN_WITH_INPUT align
#undef SECTION_DATA_PROLOGUE
#define SECTION_DATA_PROLOGUE(name, options, align) \
name options : ALIGN_WITH_INPUT align
#undef GROUP_ROM_LINK_IN
#define GROUP_ROM_LINK_IN(vregion, lregion) > vregion AT > lregion
#undef GROUP_DATA_LINK_IN
#define GROUP_DATA_LINK_IN(vregion, lregion) > vregion AT > lregion
#undef GROUP_NOLOAD_LINK_IN
#define GROUP_NOLOAD_LINK_IN(vregion, lregion) > vregion AT > lregion
#endif
/* Used to align areas with separate memory permission characteristics
* so that the page permissions can be set in the MMU. Without this,
* the kernel is just one blob with the same RWX permissions on all RAM
*/
#ifdef CONFIG_SRAM_REGION_PERMISSIONS
#define MMU_PAGE_ALIGN_PERM MMU_PAGE_ALIGN
#else
#define MMU_PAGE_ALIGN_PERM
#endif
/* For all source files under arch/x86/. */
#define LIB_ARCH_X86_IN_SECT(lsect) \
*libarch__x86__core.a.a:(.##lsect) \
*libarch__x86__core.a:(.##lsect##.*)
#ifdef CONFIG_MINIMAL_LIBC
/* For all source files under lib/libc/minimal/.
* These files includes, for example, math and string functions.
*/
#define LIB_C_IN_SECT(lsect) \
*liblib__libc__minimal.a:(.##lsect) \
*liblib__libc__minimal.a:(.##lsect##.*)
#endif /* CONFIG_MINIMAL_LIBC */
#ifdef CONFIG_NEWLIB_LIBC
/* For Newlib libc-hook.c. */
#define LIB_C_IN_SECT(lsect) \
*liblib__libc__newlib.a:libc-hooks.c.obj(.##lsect) \
*liblib__libc__newlib.a:libc-hooks.c.obj(.##lsect##.*)
#endif /* CONFIG_NEWLIB_LIBC */
#ifdef CONFIG_PICOLIBC
/* For Picolibc libc-hook.c. */
#define LIB_C_IN_SECT(lsect) \
*liblib__libc__picolibc.a:libc-hooks.c.obj(.##lsect) \
*liblib__libc__picolibc.a:libc-hooks.c.obj(.##lsect##.*)
#endif /* CONFIG_PICOLIBC */
/*
* For drivers that are usually used (e.g. serial)
*/
#define LIB_DRIVERS_IN_SECT(lsect) \
*libdrivers__serial.a:(.##lsect) \
*libdrivers__serial.a:(.##lsect##.*) \
*hpet.c.obj(.##lsect) \
*hpet.c.obj(.##lsect##.*) \
*intc_ioapic.c.obj(.##lsect) \
*intc_ioapic.c.obj(.##lsect##.*) \
*intc_loapic.c.obj(.##lsect) \
*intc_loapic.c.obj(.##lsect##.*) \
*intc_system_apic.c.obj(.##lsect) \
*intc_system_apic.c.obj(.##lsect##.*) \
*random_timer.c.obj(.##lsect) \
*random_timer.c.obj(.##lsect##.*) \
*uart_console.c.obj(.##lsect) \
*uart_console.c.obj(.##lsect##.*)
/* For all source files under kernel/. and kernel related files */
#define LIB_KERNEL_IN_SECT(lsect) \
*libkernel.a:(.##lsect) \
*libkernel.a:(.##lsect##.*) \
*libsubsys__demand_paging__*.a:(.##lsect) \
*libsubsys__demand_paging__*.a:(.##lsect##.*)
/* For particular file packaged in libzephyr.a. */
#define LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, objfile) \
*libzephyr.a:objfile.c.obj(.##lsect) \
*libzephyr.a:objfile.c.obj(.##lsect##.*)
/* For source files under lib/os/ with commonly used functions. */
#define LIB_ZEPHYR_IN_SECT(lsect) \
LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, assert) \
LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, bitarray) \
LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, cbprintf_complete) \
LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, cbprintf_nano) \
LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, configs) \
LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, coverage) \
LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, heap) \
LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, heap-validate) \
LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, mutex) \
LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, notify) \
LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, printk) \
LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, sem) \
LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, stdout_console) \
LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, sys_clock_init) \
LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, rb) \
LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, tracing_none) \
LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, tracing_tracking) \
LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, thread_entry) \
LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, work_q)
/*
* Catch all for all internal/external kernel functions
* as they are usually defined as "static inline" where
* they are attached to the source which uses them.
* Hence the need to specify them here so they can be pinned.
*/
#define ZEPHYR_KERNEL_FUNCS_IN_SECT \
*(.text.atomic_*) \
*(.text.k_*) \
*(.text.sys_*_bit) \
*(.text.sys_bitfield_*) \
*(.text.sys_clock_hw_cycles_per_sec) \
*(.text.sys_cache_*) \
*(.text.sys_dcache_*) \
*(.text.sys_icache_*) \
*(.text.sys_mutex_*) \
*(.text.sys_notify_*) \
*(.text.sys_dlist_*) \
*(.text.sys_slist_*) \
*(.text.sys_sflist_*) \
*(.text.sys_sfnode_*) \
*(.text.sys_io_*) \
*(.text.sys_in*) \
*(.text.sys_out*) \
*(.text.sys_read*) \
*(.text.sys_write*) \
*(.text.sys_get_be*) \
*(.text.sys_get_le*) \
*(.text.sys_put_be*) \
*(.text.sys_put_le*) \
*(.text.sys_mem_swap) \
*(.text.sys_memcpy_swap) \
*(.text.z_*)
/* For logging subsys */
#define LIB_SUBSYS_LOGGING_IN_SECT(lsect) \
*log_*.c.obj(.##lsect) \
*log_*.c.obj(.##lsect.*) \
*mpsc_pbuf.c.obj(.##lsect) \
*mpsc_pbuf.c.obj(.##lsect.*)
epoint = K_MEM_PHYS_ADDR(CONFIG_KERNEL_ENTRY);
ENTRY(epoint)
/* SECTIONS definitions */
SECTIONS
{
#include <zephyr/linker/rel-sections.ld>
#ifdef CONFIG_LLEXT
#include <zephyr/linker/llext-sections.ld>
#endif
/DISCARD/ :
{
*(.plt)
}
/DISCARD/ :
{
*(.iplt)
}
#ifdef CONFIG_LINKER_USE_BOOT_SECTION
SECTION_PROLOGUE(boot.text,,)
{
#include <snippets-rom-start.ld>
MMU_PAGE_ALIGN
lnkr_boot_start = .;
z_mapped_start = .;
lnkr_boot_text_start = .;
KEEP(*(.boot_text.__start))
*(.boot_text)
*(.boot_text.*)
*(.text.k_mem_paging_backing_store_init)
*(.text.k_mem_paging_eviction_init)
MMU_PAGE_ALIGN_PERM
lnkr_boot_text_end = .;
} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
SECTION_PROLOGUE(boot.rodata,,)
{
MMU_PAGE_ALIGN_PERM
lnkr_boot_rodata_start = .;
*(.boot_rodata)
*(.boot_rodata.*)
MMU_PAGE_ALIGN_PERM
lnkr_boot_rodata_end = .;
} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
SECTION_PROLOGUE(boot.data,,)
{
MMU_PAGE_ALIGN_PERM
. = ALIGN(4);
lnkr_boot_data_start = .;
*(.boot_data)
*(.boot_data.*)
lnkr_boot_data_end = .;
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
SECTION_PROLOGUE(boot.bss, (NOLOAD),)
{
. = ALIGN(4);
lnkr_boot_bss_start = .;
*(.boot_bss)
*(.boot_bss.*)
lnkr_boot_bss_end = .;
} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
SECTION_PROLOGUE(boot.noinit, (NOLOAD),)
{
. = ALIGN(4);
lnkr_boot_noinit_start = .;
*(.boot_noinit)
*(.boot_noinit.*)
lnkr_boot_noinit_end = .;
MMU_PAGE_ALIGN
lnkr_boot_end = .;
} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
lnkr_boot_text_size = lnkr_boot_text_end - lnkr_boot_text_start;
lnkr_boot_rodata_size = lnkr_boot_rodata_end - lnkr_boot_rodata_start;
lnkr_boot_data_size = lnkr_boot_data_end - lnkr_boot_data_start;
lnkr_boot_bss_size = lnkr_boot_bss_end - lnkr_boot_bss_start;
lnkr_boot_noinit_size = lnkr_boot_noinit_end - lnkr_boot_noinit_start;
#endif /* CONFIG_LINKER_USE_BOOT_SECTION */
#ifdef CONFIG_LINKER_USE_PINNED_SECTION
SECTION_PROLOGUE(pinned.text,,)
{
#ifndef CONFIG_LINKER_USE_BOOT_SECTION
#include <snippets-rom-start.ld>
#endif
MMU_PAGE_ALIGN
lnkr_pinned_start = .;
#ifndef CONFIG_LINKER_USE_BOOT_SECTION
z_mapped_start = .;
#endif
lnkr_pinned_text_start = .;
LIB_KERNEL_IN_SECT(text)
LIB_ARCH_X86_IN_SECT(text)
*(.text._OffsetAbsSyms)
*(.pinned_text)
*(.pinned_text.*)
LIB_ZEPHYR_IN_SECT(text)
LIB_C_IN_SECT(text)
LIB_DRIVERS_IN_SECT(text)
LIB_SUBSYS_LOGGING_IN_SECT(text)
*_divdi3.o(.text)
*_udivdi3.o(.text)
*_udivmoddi4.o(.text)
*_umoddi3.o(.text)
*_popcountsi2.o(.text)
*(.gnu.linkonce.t.exc_*)
*(.text.*.constprop)
*(.text.*.constprop.*)
#if defined(CONFIG_NEWLIB_LIBC) || defined(CONFIG_PICOLIBC)
*libc*.a:(.text)
*libc*.a:(.text.*)
#endif
#ifdef CONFIG_COVERAGE
*(.text._sub_I_00100_0)
#endif
ZEPHYR_KERNEL_FUNCS_IN_SECT
#include <zephyr/linker/kobject-text.ld>
MMU_PAGE_ALIGN_PERM
lnkr_pinned_text_end = .;
} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
MMU_PAGE_ALIGN_PERM
lnkr_pinned_rodata_start = .;
#include <zephyr/linker/common-rom.ld>
/* Located in generated directory. This file is populated by calling
* zephyr_linker_sources(ROM_SECTIONS ...). Useful for grouping iterable RO structs.
*/
#include <snippets-rom-sections.ld>
#include <zephyr/linker/thread-local-storage.ld>
SECTION_PROLOGUE(pinned.rodata,,)
{
#include <zephyr/arch/x86/ia32/scripts/static_intr.ld>
LIB_KERNEL_IN_SECT(rodata)
LIB_ARCH_X86_IN_SECT(rodata)
*(.pinned_rodata)
*(.pinned_rodata.*)
LIB_ZEPHYR_IN_SECT(rodata)
LIB_C_IN_SECT(rodata)
LIB_DRIVERS_IN_SECT(rodata)
LIB_SUBSYS_LOGGING_IN_SECT(rodata)
/* Static strings */
*(.rodata.str*.*)
*(.rodata.*.str*.*)
#if defined(CONFIG_NEWLIB_LIBC) || defined(CONFIG_PICOLIBC)
*libc*.a:(.rodata)
*libc*.a:(.rodata.*)
#endif
#include <snippets-rodata.ld>
#include <snippets-pinned-rodata.ld>
#include <zephyr/linker/kobject-rom.ld>
MMU_PAGE_ALIGN_PERM
lnkr_pinned_rodata_end = .;
} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
SECTION_PROLOGUE(pinned.data,,)
{
MMU_PAGE_ALIGN_PERM
lnkr_pinned_data_start = .;
. = ALIGN(4);
#include <zephyr/arch/x86/ia32/scripts/shared_kernel_pages.ld>
#include <zephyr/arch/x86/ia32/scripts/dynamic_intr.ld>
LIB_KERNEL_IN_SECT(data)
LIB_ARCH_X86_IN_SECT(data)
*(.pinned_data)
*(.pinned_data.*)
LIB_ZEPHYR_IN_SECT(data)
LIB_C_IN_SECT(data)
LIB_DRIVERS_IN_SECT(data)
LIB_SUBSYS_LOGGING_IN_SECT(data)
#ifdef CONFIG_COVERAGE
*(.data.__gcov_.*)
/*
* This is for the struct gcov_info for
* various functions.
*/
*(.data..LPBX*)
#endif
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
#include <zephyr/linker/common-ram.ld>
#include <zephyr/arch/x86/pagetables.ld>
#include <zephyr/linker/kobject-data.ld>
/* Located in generated directory. This file is populated by the
* zephyr_linker_sources() Cmake function.
*/
#include <snippets-pinned-data-sections.ld>
lnkr_pinned_data_end = .;
/* Located in generated directory. This file is populated by the
* zephyr_linker_sources() Cmake function.
*/
#include <snippets-pinned-ram-sections.ld>
SECTION_PROLOGUE(pinned.bss, (NOLOAD),)
{
. = ALIGN(4);
lnkr_pinned_bss_start = .;
LIB_KERNEL_IN_SECT(bss)
LIB_ARCH_X86_IN_SECT(bss)
*(.pinned_bss)
*(.pinned_bss.*)
LIB_ZEPHYR_IN_SECT(bss)
LIB_C_IN_SECT(bss)
LIB_DRIVERS_IN_SECT(bss)
LIB_SUBSYS_LOGGING_IN_SECT(bss)
#ifdef CONFIG_COVERAGE
*(.bss.__gcov0.*)
#endif
lnkr_pinned_bss_end = .;
} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
#ifdef CONFIG_USERSPACE
/* PINNED APP SHARED MEMORY REGION */
#include <app_smem_pinned.ld>
_app_smem_pinned_size = _app_smem_pinned_end - _app_smem_pinned_start;
_app_smem_pinned_num_words = _app_smem_pinned_size >> 2;
#endif /* CONFIG_USERSPACE */
SECTION_PROLOGUE(pinned.noinit, (NOLOAD),)
{
. = ALIGN(4);
lnkr_pinned_noinit_start = .;
LIB_KERNEL_IN_SECT(noinit)
LIB_ARCH_X86_IN_SECT(noinit)
*(.pinned_noinit)
*(.pinned_noinit.*)
LIB_ZEPHYR_IN_SECT(noinit)
LIB_C_IN_SECT(noinit)
LIB_DRIVERS_IN_SECT(noinit)
LIB_SUBSYS_LOGGING_IN_SECT(noinit)
#ifdef CONFIG_ZTEST
/* For tests/kernel/mem_slab/ tests */
*(.noinit.*.k_mem_slab_buf_*)
/* For tests/kernel/mem_heap tests */
*(.noinit.*.kheap_buf_*)
/* Pin ztest_thread_stack.
* This must be done or else double fault
* may arise: testing exceptions while
* page fault for the ztest stack.
*/
*libsubsys__testsuite__ztest.a:(.noinit.*)
#endif
lnkr_pinned_noinit_end = .;
MMU_PAGE_ALIGN
lnkr_pinned_end = .;
} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
lnkr_pinned_text_size = lnkr_pinned_text_end - lnkr_pinned_text_start;
lnkr_pinned_rodata_size = lnkr_pinned_rodata_end - lnkr_pinned_rodata_start;
lnkr_pinned_data_size = lnkr_pinned_data_end - lnkr_pinned_data_start;
lnkr_pinned_bss_size = lnkr_pinned_bss_end - lnkr_pinned_bss_start;
lnkr_pinned_noinit_size = lnkr_pinned_noinit_end - lnkr_pinned_noinit_start;
#endif /* CONFIG_LINKER_USE_PINNED_SECTION */
#if defined(CONFIG_DEMAND_PAGING) && !defined(CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT)
/* From now on, put symbols into FLASH */
#undef ROMABLE_REGION
#define ROMABLE_REGION FLASH
/* This is to align the following sections in flash
* to their corresponding virtual addresses.
* In other words, the offset from start of flash
* for these sections would be the same from start of
* their virtual addresses. This provides a simple and
* direct mapping from backing store.
*/
flash_load_offset :
{
. = FLASH_ROM_ADDR + (lnkr_pinned_end - KERNEL_BASE_ADDR);
} > FLASH AT > FLASH
#endif
GROUP_START(ROMABLE_REGION)
. = ALIGN(8);
SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)
{
__text_region_start = .;
#if !defined(CONFIG_LINKER_USE_BOOT_SECTION) || \
!defined(CONFIG_LINKER_USE_PINNED_SECTION)
z_mapped_start = .;
#endif
#if !defined(CONFIG_LINKER_USE_BOOT_SECTION) || \
!defined(CONFIG_LINKER_USE_PINNED_SECTION)
/* Located in generated directory. This file is populated by calling
* zephyr_linker_sources(ROM_START ...). This typically contains the vector
* table and debug information.
*/
#include <snippets-rom-start.ld>
#endif
/* Needs KEEP() as ENTRY() is given a physical address */
KEEP(*(.text.__start))
*(.text)
*(".text.*")
*(.gnu.linkonce.t.*)
*(.init)
*(.fini)
*(.eini)
#ifndef CONFIG_LINKER_USE_PINNED_SECTION
#include <zephyr/linker/kobject-text.ld>
#endif
MMU_PAGE_ALIGN_PERM
} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
__text_region_end = .;
__text_region_size = __text_region_end - __text_region_start;
__rodata_region_start = .;
#ifndef CONFIG_LINKER_USE_PINNED_SECTION
#include <zephyr/linker/common-rom.ld>
/* Located in generated directory. This file is populated by calling
* zephyr_linker_sources(ROM_SECTIONS ...). Useful for grouping iterable RO structs.
*/
#include <snippets-rom-sections.ld>
#include <zephyr/linker/thread-local-storage.ld>
#endif
SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
{
*(.rodata)
*(".rodata.*")
*(.gnu.linkonce.r.*)
#ifndef CONFIG_DYNAMIC_INTERRUPTS
#ifndef CONFIG_LINKER_USE_PINNED_SECTION
#include <zephyr/arch/x86/ia32/scripts/static_intr.ld>
#endif /* !CONFIG_LINKER_USE_PINNED_SECTION */
#endif /* CONFIG_DYNAMIC_INTERRUPTS */
#ifndef CONFIG_LINKER_USE_PINNED_SECTION
/* Located in generated directory. This file is populated by the
* zephyr_linker_sources() Cmake function.
*/
#include <snippets-rodata.ld>
#include <zephyr/linker/kobject-rom.ld>
#endif
} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
#include <zephyr/linker/cplusplus-rom.ld>
MMU_PAGE_ALIGN_PERM
/* ROM ends here, position counter will now be in RAM areas */
__rodata_region_end = .;
__rodata_region_size = __rodata_region_end - __rodata_region_start;
GROUP_END(ROMABLE_REGION)
/*
* Needed for dynamic linking which we do not have, do discard
*/
/DISCARD/ : {
*(.got.plt)
*(.igot.plt)
*(.got)
*(.igot)
}
/* RAMABLE_REGION */
GROUP_START(RAMABLE_REGION)
/* Located in generated directory. This file is populated by the
* zephyr_linker_sources() Cmake function.
*/
#include <snippets-ram-sections.ld>
#ifdef CONFIG_USERSPACE
/* APP SHARED MEMORY REGION */
#include <app_smem.ld>
_image_ram_start = _app_smem_start;
_app_smem_size = _app_smem_end - _app_smem_start;
_app_smem_num_words = _app_smem_size >> 2;
_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);
#endif /* CONFIG_USERSPACE */
SECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD),)
{
MMU_PAGE_ALIGN_PERM
#if !defined(CONFIG_USERSPACE)
_image_ram_start = .;
#endif
/*
* For performance, BSS section is forced to be both 4 byte aligned and
* a multiple of 4 bytes.
*/
. = ALIGN(4);
__kernel_ram_start = .;
__bss_start = .;
*(.bss)
*(".bss.*")
*(COMMON)
*(".kernel_bss.*")
/*
* As memory is cleared in words only, it is simpler to ensure the BSS
* section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.
*/
. = ALIGN(4);
__bss_end = .;
} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
__bss_num_words = (__bss_end - __bss_start) >> 2;
#include <zephyr/linker/common-noinit.ld>
MMU_PAGE_ALIGN_PERM
SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)
{
__data_ram_start = .;
*(.data)
*(".data.*")
*(".kernel.*")
#ifdef CONFIG_DYNAMIC_INTERRUPTS
#ifndef CONFIG_LINKER_USE_PINNED_SECTION
#include <zephyr/arch/x86/ia32/scripts/dynamic_intr.ld>
#endif /* !CONFIG_LINKER_USE_PINNED_SECTION */
#endif /* CONFIG_DYNAMIC_INTERRUPTS */
/* Located in generated directory. This file is populated by the
* zephyr_linker_sources() Cmake function.
*/
#include <snippets-rwdata.ld>
#ifndef CONFIG_LINKER_USE_PINNED_SECTION
#include <zephyr/arch/x86/ia32/scripts/shared_kernel_pages.ld>
#endif /* !CONFIG_LINKER_USE_PINNED_SECTION */
. = ALIGN(4);
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
__data_rom_start = LOADADDR(_DATA_SECTION_NAME);
#include <zephyr/linker/cplusplus-ram.ld>
#ifndef CONFIG_LINKER_USE_PINNED_SECTION
#include <zephyr/linker/common-ram.ld>
#include <zephyr/arch/x86/pagetables.ld>
/* Must be last in RAM */
#include <zephyr/linker/kobject-data.ld>
#endif /* !CONFIG_LINKER_USE_PINNED_SECTION */
/* Located in generated directory. This file is populated by the
* zephyr_linker_sources() Cmake function.
*/
#include <snippets-data-sections.ld>
MMU_PAGE_ALIGN
__data_ram_end = .;
/* All unused memory also owned by the kernel for heaps */
__kernel_ram_end = KERNEL_BASE_ADDR + KERNEL_RAM_SIZE;
__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;
_image_ram_all = (KERNEL_BASE_ADDR + KERNEL_RAM_SIZE) - _image_ram_start;
z_mapped_size = z_mapped_end - z_mapped_start;
#ifndef LINKER_ZEPHYR_FINAL
/* static interrupts */
SECTION_PROLOGUE(intList,,)
{
KEEP(*(.spurIsr))
KEEP(*(.spurNoErrIsr))
KEEP(*(.intList))
KEEP(*(.gnu.linkonce.intList.*))
} > IDT_LIST
#else
/DISCARD/ :
{
KEEP(*(.spurIsr))
KEEP(*(.spurNoErrIsr))
KEEP(*(.intList))
KEEP(*(.gnu.linkonce.intList.*))
}
#endif
/* Located in generated directory. This file is populated by the
* zephyr_linker_sources() Cmake function.
*/
#include <snippets-sections.ld>
#define LAST_RAM_ALIGN MMU_PAGE_ALIGN
#include <zephyr/linker/ram-end.ld>
GROUP_END(RAMABLE_REGION)
#include <zephyr/linker/debug-sections.ld>
/DISCARD/ : { *(.note.GNU-stack) }
}
``` | /content/code_sandbox/boards/qemu/x86/qemu_x86_tiny.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 6,688 |
```yaml
board:
name: qemu_riscv64
vendor: qemu
socs:
- name: qemu_virt_riscv64
variants:
- name: smp
``` | /content/code_sandbox/boards/qemu/riscv64/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 43 |
```unknown
/dts-v1/;
#include <qemu/virt-riscv64.dtsi>
/ {
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sram = &ram0;
};
};
&uart0 {
status = "okay";
};
``` | /content/code_sandbox/boards/qemu/riscv64/qemu_riscv64.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 75 |
```unknown
config BOARD_QEMU_RISCV64
select QEMU_TARGET
``` | /content/code_sandbox/boards/qemu/riscv64/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 16 |
```unknown
if BOARD_QEMU_RISCV64
config BUILD_OUTPUT_BIN
default n
config HAS_COVERAGE_SUPPORT
default y
config QEMU_ICOUNT_SHIFT
default 6 if QEMU_ICOUNT
endif # BOARD_QEMU_RISCV64
``` | /content/code_sandbox/boards/qemu/riscv64/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 54 |
```unknown
CONFIG_PRIVILEGED_STACK_SIZE=2048
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_STACK_SENTINEL=y
CONFIG_XIP=n
CONFIG_RISCV_PMP=y
CONFIG_SMP=y
CONFIG_MP_MAX_NUM_CPUS=2
CONFIG_IDLE_STACK_SIZE=1024
CONFIG_QEMU_ICOUNT=n
``` | /content/code_sandbox/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 74 |
```unknown
/dts-v1/;
#include <qemu/virt-riscv64.dtsi>
/ {
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sram = &ram0;
};
};
&uart0 {
status = "okay";
};
``` | /content/code_sandbox/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 75 |
```unknown
CONFIG_PRIVILEGED_STACK_SIZE=2048
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_STACK_SENTINEL=y
CONFIG_XIP=n
CONFIG_RISCV_PMP=y
``` | /content/code_sandbox/boards/qemu/riscv64/qemu_riscv64_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 45 |
```unknown
CONFIG_XIP=n
CONFIG_BUILD_OUTPUT_BIN=n
CONFIG_ARCV2_INTERRUPT_UNIT=y
CONFIG_ARCV2_TIMER=y
CONFIG_ARC_HAS_STACK_CHECKING=n
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_QEMU_ICOUNT_SHIFT=6
CONFIG_ARC_MPU_ENABLE=y
``` | /content/code_sandbox/boards/qemu/arc/qemu_arc_qemu_arc_hs_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 66 |
```unknown
CONFIG_ISA_ARCV3=y
CONFIG_XIP=n
CONFIG_BUILD_OUTPUT_BIN=n
CONFIG_ARCV2_INTERRUPT_UNIT=y
CONFIG_ARCV2_TIMER=y
CONFIG_ARC_HAS_STACK_CHECKING=n
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_QEMU_ICOUNT_SHIFT=6
``` | /content/code_sandbox/boards/qemu/arc/qemu_arc_qemu_arc_hs5x_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 66 |
```restructuredtext
.. _qemu_riscv64:
RISCV64 Emulation (QEMU)
########################
Overview
********
The RISCV64 QEMU board configuration is used to emulate the RISCV64 architecture.
Get the Toolchain and QEMU
**************************
The minimum version of the `Zephyr SDK tools
<path_to_url`_
with toolchain and QEMU support for the RISCV64 architecture is v0.10.2.
Please see the :ref:`installation instructions <install-required-tools>`
for more details.
Programming and Debugging
*************************
Applications for the ``qemu_riscv64`` board configuration can be built and run in
the usual way for emulated boards (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Flashing
========
While this board is emulated and you can't "flash" it, you can use this
configuration to run basic Zephyr applications and kernel tests in the QEMU
emulated environment. For example, with the :zephyr:code-sample:`synchronization` sample:
.. zephyr-app-commands::
:zephyr-app: samples/synchronization
:host-os: unix
:board: qemu_riscv64
:goals: run
This will build an image with the synchronization sample app, boot it using
QEMU, and display the following console output:
.. code-block:: console
***** BOOTING ZEPHYR OS v1.8.99 - BUILD: Jun 27 2017 13:09:26 *****
threadA: Hello World from riscv64!
threadB: Hello World from riscv64!
threadA: Hello World from riscv64!
threadB: Hello World from riscv64!
threadA: Hello World from riscv64!
threadB: Hello World from riscv64!
threadA: Hello World from riscv64!
threadB: Hello World from riscv64!
threadA: Hello World from riscv64!
threadB: Hello World from riscv64!
Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`.
Debugging
=========
Refer to the detailed overview about :ref:`application_debugging`.
``` | /content/code_sandbox/boards/qemu/riscv64/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 489 |
```yaml
identifier: qemu_arc/qemu_arc_hs
name: QEMU Emulation for ARC HS
type: qemu
simulation: qemu
arch: arc
toolchain:
- zephyr
- cross-compile
- arcmwdt
testing:
default: true
ignore_tags:
- net
- bluetooth
vendor: snps
``` | /content/code_sandbox/boards/qemu/arc/qemu_arc_qemu_arc_hs.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 78 |
```unknown
/*
*
*/
/dts-v1/;
#include "qemu_arc.dtsi"
/ {
model = "QEMU ARC EM";
compatible = "snps,qemu-arcem";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "snps,arcem";
reg = <0>;
};
};
};
``` | /content/code_sandbox/boards/qemu/arc/qemu_arc_qemu_arc_em.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 99 |
```yaml
identifier: qemu_arc/qemu_arc_hs/xip
name: QEMU Emulation for ARC HS (XIP)
type: qemu
simulation: qemu
arch: arc
toolchain:
- zephyr
- cross-compile
testing:
default: true
ignore_tags:
- net
- bluetooth
vendor: snps
``` | /content/code_sandbox/boards/qemu/arc/qemu_arc_qemu_arc_hs_xip.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 76 |
```cmake
set(SUPPORTED_EMU_PLATFORMS qemu)
set(QEMU_CPU_TYPE_${ARCH} arc)
if(${CONFIG_SOC_QEMU_ARC_EM})
set(QEMU_CPU_TYPE_${ARCH} arcem)
set(QEMU_FLAGS_${ARCH} -cpu arcem)
elseif(${CONFIG_SOC_QEMU_ARC_HS})
set(QEMU_CPU_TYPE_${ARCH} archs)
set(QEMU_FLAGS_${ARCH} -cpu archs)
elseif(${CONFIG_SOC_QEMU_ARC_HS5X})
set(QEMU_ARCH arc)
set(QEMU_CPU_TYPE_${ARCH} hs5x)
set(QEMU_FLAGS_${ARCH} -cpu hs5x)
elseif(${CONFIG_SOC_QEMU_ARC_HS6X})
set(QEMU_ARCH arc64)
set(QEMU_CPU_TYPE_${ARCH} hs6x)
set(QEMU_FLAGS_${ARCH} -cpu hs6x)
endif()
# For old QEMU we had 'simhs' qemu board, however we are going to rename it
# to 'virt' board. It will be renamed in ARC QEMU in the nearest Zephyr SDK
# (where ARCv3 HS6x support will be added to QEMU)
# Let's rely on the QEMU defaults instead of specifying exact board name,
# until the updated Zephyr SDK will be set as default. By that we keep both SDKs
# (old and new) working for ARCv2.
# After that we can specify board explicitly with '-M virt' option.
list(APPEND QEMU_FLAGS_${ARCH}
-m 8M
-nographic
-no-reboot
-monitor none
-global cpu.firq=false
-global cpu.num-irqlevels=15
-global cpu.num-irq=25
-global cpu.ext-irq=20
-global cpu.freq_hz=10000000
-global cpu.timer0=true
-global cpu.timer1=true
-global cpu.has-mpu=true
-global cpu.mpu-numreg=16
)
set(BOARD_DEBUG_RUNNER qemu)
``` | /content/code_sandbox/boards/qemu/arc/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 441 |
```unknown
CONFIG_XIP=y
CONFIG_BUILD_OUTPUT_BIN=n
CONFIG_ARCV2_INTERRUPT_UNIT=y
CONFIG_ARCV2_TIMER=y
CONFIG_ARC_HAS_STACK_CHECKING=n
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_QEMU_ICOUNT_SHIFT=6
CONFIG_ARC_MPU_ENABLE=y
``` | /content/code_sandbox/boards/qemu/arc/qemu_arc_qemu_arc_hs_xip_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 66 |
```unknown
#
config BOARD_QEMU_ARC
select SOC_QEMU_ARC_EM if BOARD_QEMU_ARC_QEMU_ARC_EM
select SOC_QEMU_ARC_HS if BOARD_QEMU_ARC_QEMU_ARC_HS || BOARD_QEMU_ARC_QEMU_ARC_HS_XIP
select SOC_QEMU_ARC_HS5X if BOARD_QEMU_ARC_QEMU_ARC_HS5X
select SOC_QEMU_ARC_HS6X if BOARD_QEMU_ARC_QEMU_ARC_HS6X
``` | /content/code_sandbox/boards/qemu/arc/Kconfig.qemu_arc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 106 |
```c
/*
*
*/
#include <zephyr/devicetree.h>
#include <zephyr/arch/arc/v2/mpu/arc_mpu.h>
#include <zephyr/arch/arc/arch.h>
#include <zephyr/linker/linker-defs.h>
/*
* for secure firmware, MPU entries are only set up for secure world.
* All regions not listed here are shared by secure world and normal world.
*/
static struct arc_mpu_region mpu_regions[] = {
#if defined(CONFIG_COVERAGE_GCOV) && defined(CONFIG_USERSPACE)
/* Region Coverage */
MPU_REGION_ENTRY("COVERAGE",
(uint32_t)&(__gcov_bss_start),
(uint32_t)&__gcov_bss_size,
REGION_IO_ATTR),
#endif /* CONFIG_COVERAGE_GCOV && CONFIG_USERSPACE */
#if DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0
#ifdef CONFIG_XIP
/* Region RAM */
MPU_REGION_ENTRY("RAM",
DT_REG_ADDR(DT_CHOSEN(zephyr_sram)),
DT_REG_SIZE(DT_CHOSEN(zephyr_sram)),
REGION_KERNEL_RAM_ATTR | REGION_DYNAMIC),
#else
/* Region RAM */
/*
* In case if Zephyr is configured with CONFIG_XIP=n it linked into
* SRAM. So RAM region should have EXECUTE permission.
*/
MPU_REGION_ENTRY("RAM_RX",
(uintptr_t)__rom_region_start,
(uintptr_t)__rom_region_size,
REGION_ROM_ATTR),
MPU_REGION_ENTRY("RAM_RW",
(uintptr_t)_image_ram_start,
(uintptr_t)__arc_rw_sram_size,
REGION_KERNEL_RAM_ATTR | REGION_DYNAMIC),
#endif /* CONFIG_XIP */
#endif /* zephyr_sram > 0 */
#if DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) > 0
/* Region DCCM */
MPU_REGION_ENTRY("FLASH",
DT_REG_ADDR(DT_CHOSEN(zephyr_flash)),
DT_REG_SIZE(DT_CHOSEN(zephyr_flash)),
REGION_ROM_ATTR),
#endif
/*
* Region peripheral is shared by secure world and normal world by default,
* no need a static mpu entry. If some peripherals belong to secure world,
* add it here.
*/
#ifndef CONFIG_ARC_SECURE_FIRMWARE
/* Region Peripheral */
MPU_REGION_ENTRY("PERIPHERAL",
0xF0000000,
64 * 1024,
REGION_KERNEL_RAM_ATTR),
#endif
};
struct arc_mpu_config mpu_config = {
.num_regions = ARRAY_SIZE(mpu_regions),
.mpu_regions = mpu_regions,
};
``` | /content/code_sandbox/boards/qemu/arc/arc_mpu_regions.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 561 |
```unknown
CONFIG_ISA_ARCV3=y
CONFIG_XIP=n
CONFIG_BUILD_OUTPUT_BIN=n
CONFIG_ARCV2_INTERRUPT_UNIT=y
CONFIG_ARCV2_TIMER=y
CONFIG_ARC_HAS_STACK_CHECKING=n
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_QEMU_ICOUNT_SHIFT=6
``` | /content/code_sandbox/boards/qemu/arc/qemu_arc_qemu_arc_hs6x_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 66 |
```yaml
identifier: qemu_arc/qemu_arc_hs6x
name: QEMU Emulation for ARC HS6x
type: qemu
simulation: qemu
arch: arc
toolchain:
- cross-compile
- zephyr
testing:
default: true
ignore_tags:
- net
- bluetooth
vendor: snps
``` | /content/code_sandbox/boards/qemu/arc/qemu_arc_qemu_arc_hs6x.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 75 |
```unknown
/*
*
*/
/dts-v1/;
#include <mem.h>
#include "skeleton.dtsi"
#define DT_FLASH_SIZE DT_SIZE_M(4)
#define DT_SRAM_SIZE DT_SIZE_M(4)
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
};
intc: arcv2-intc {
compatible = "snps,arcv2-intc";
interrupt-controller;
#interrupt-cells = <2>;
};
timer0: timer0 {
compatible = "snps,arc-timer";
interrupts = <16 1>;
interrupt-parent = <&intc>;
};
timer1: timer1 {
compatible = "snps,arc-timer";
interrupts = <17 1>;
interrupt-parent = <&intc>;
};
/* We are carving out of DRAM for a pseudo flash and sram region */
flash0: flash@80000000 {
compatible = "soc-nv-flash";
reg = <0x80000000 DT_FLASH_SIZE>;
};
sram0: sram@80400000 {
device_type = "memory";
reg = <0x80400000 DT_SRAM_SIZE>;
};
ns16550_uart0: uart@f0000000 {
compatible = "ns16550";
clock-frequency = <10000000>;
reg = <0xf0000000 0x400>;
current-speed = <115200>;
interrupt-parent = <&intc>;
interrupts = <24 1>;
reg-shift = <2>;
};
ns16550_uart1: uart@f0002000 {
compatible = "ns16550";
clock-frequency = <10000000>;
reg = <0xf0002000 0x400>;
current-speed = <115200>;
interrupt-parent = <&intc>;
interrupts = <25 1>;
reg-shift = <2>;
};
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &ns16550_uart0;
zephyr,shell-uart = &ns16550_uart0;
zephyr,uart-pipe = &ns16550_uart1;
};
};
``` | /content/code_sandbox/boards/qemu/arc/qemu_arc.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 520 |
```unknown
/*
*
*/
/dts-v1/;
#include "qemu_arc.dtsi"
/ {
model = "QEMU ARC HS";
compatible = "snps,qemu-archs";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "snps,archs";
reg = <0>;
};
};
};
``` | /content/code_sandbox/boards/qemu/arc/qemu_arc_qemu_arc_hs6x.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 97 |
```yaml
board:
name: qemu_arc
vendor: qemu
socs:
- name: qemu_arc_em
- name: qemu_arc_hs
variants:
- name: xip
- name: qemu_arc_hs5x
- name: qemu_arc_hs6x
``` | /content/code_sandbox/boards/qemu/arc/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 64 |
```yaml
identifier: qemu_arc/qemu_arc_hs5x
name: QEMU Emulation for ARC HS5x
type: qemu
simulation: qemu
arch: arc
toolchain:
- zephyr
- cross-compile
testing:
default: true
ignore_tags:
- net
- bluetooth
vendor: snps
``` | /content/code_sandbox/boards/qemu/arc/qemu_arc_qemu_arc_hs5x.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 75 |
```unknown
/*
*
*/
/dts-v1/;
#include "qemu_arc.dtsi"
/ {
model = "QEMU ARC HS";
compatible = "snps,qemu-archs";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "snps,archs";
reg = <0>;
};
};
};
``` | /content/code_sandbox/boards/qemu/arc/qemu_arc_qemu_arc_hs5x.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 97 |
```unknown
/*
*
*/
/dts-v1/;
#include "qemu_arc.dtsi"
/ {
model = "QEMU ARC HS";
compatible = "snps,qemu-archs";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "snps,archs";
reg = <0>;
};
};
};
``` | /content/code_sandbox/boards/qemu/arc/qemu_arc_qemu_arc_hs.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 97 |
```yaml
identifier: qemu_arc/qemu_arc_em
name: QEMU Emulation for ARC EM
type: qemu
simulation: qemu
arch: arc
toolchain:
- zephyr
- cross-compile
testing:
default: true
ignore_tags:
- net
- bluetooth
vendor: snps
``` | /content/code_sandbox/boards/qemu/arc/qemu_arc_qemu_arc_em.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 71 |
```unknown
if BOARD_QEMU_ARC
if NETWORKING
config NET_L2_ETHERNET
default y
# Required to satisfy dependency of networking stack on RNG
config TEST_RANDOM_GENERATOR
default y
endif # NETWORKING
endif
``` | /content/code_sandbox/boards/qemu/arc/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```unknown
#
config BOARD_QEMU_ARC
select QEMU_TARGET
select HAS_COVERAGE_SUPPORT
``` | /content/code_sandbox/boards/qemu/arc/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 20 |
```unknown
CONFIG_XIP=y
CONFIG_BUILD_OUTPUT_BIN=n
CONFIG_ARCV2_INTERRUPT_UNIT=y
CONFIG_ARCV2_TIMER=y
CONFIG_ARC_HAS_STACK_CHECKING=n
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_QEMU_ICOUNT_SHIFT=6
CONFIG_ARC_MPU_ENABLE=y
``` | /content/code_sandbox/boards/qemu/arc/qemu_arc_qemu_arc_em_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 66 |
```unknown
/*
*
*/
/dts-v1/;
#include "qemu_arc.dtsi"
/ {
model = "QEMU ARC HS";
compatible = "snps,qemu-archs";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "snps,archs";
reg = <0>;
};
};
};
``` | /content/code_sandbox/boards/qemu/arc/qemu_arc_qemu_arc_hs_xip.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 97 |
```restructuredtext
.. _boards_posix:
POSIX/Native Boards
###################
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/native/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```unknown
CONFIG_CONSOLE=y
CONFIG_NO_OPTIMIZATIONS=y
CONFIG_LOG_BACKEND_UART=n
``` | /content/code_sandbox/boards/native/nrf_bsim/nrf52_bsim_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 20 |
```cmake
set(SUPPORTED_EMU_PLATFORMS native)
board_set_debugger_ifnset(native)
board_set_flasher_ifnset(native)
board_finalize_runner_args(native)
``` | /content/code_sandbox/boards/native/nrf_bsim/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 38 |
```yaml
identifier: nrf5340bsim/nrf5340/cpunet
name: NRF53 Net Core BabbleSim board
type: native
arch: posix
simulation: native
env:
- BSIM_OUT_PATH
toolchain:
- zephyr
testing:
ignore_tags:
- gpio
- modem
- uart
- bsim_skip_CI
``` | /content/code_sandbox/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 83 |
```restructuredtext
.. _qemu_arc:
ARCv2 & ARCv3 Emulation (QEMU)
###############################
Overview
********
This board configuration will use QEMU to emulate set of generic
ARCv2 and ARCv3 hardware platforms.
The following features of ARC ISA cores are currently supported:
* CPU:
* ARCv2 EM
* ARCv2 HS3x
* ARCv3 HS5x
* ARCv3 HS6x
* Only little-endian configurations
* Full 32 register set
* ARC core free-running timers/counters Timer0 & Timer1
* ARC core interrupt controller with multiple priority levels
* DW UART
* 5 slots for MMIO Virtio devices
Hardware
********
Supported Features
==================
The following hardware features are supported:
+--------------+------------+----------------------+
| Interface | Controller | Driver/Component |
+==============+============+======================+
| ARCv2 INTC | on-chip | interrupt controller |
+--------------+------------+----------------------+
| DW UART | on-chip | serial port |
+--------------+------------+----------------------+
| ARC TIMER0 | on-chip | system clock |
+--------------+------------+----------------------+
The kernel currently does not support other hardware features on this platform.
Devices
========
System Clock
------------
This board configuration uses a system clock frequency of 1 MHz.
Serial Port
-----------
This board configuration uses a single serial communication channel with the
DesignWare UART.
Known Problems or Limitations
==============================
The following platform features are unsupported:
* Memory-protection unit (MPU)
* MMIO Virtio Ethernet
Programming and Debugging
*************************
Use this configuration to run basic Zephyr applications and kernel tests in the QEMU
emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample
(note you may use ``qemu_arc/qemu_em``, ``qemu_arc/qemu_hs``, ``qemu_arc/qemu_hs5x`` or
``qemu_arc/qemu_hs6x`` depending on target CPU):
.. zephyr-app-commands::
:zephyr-app: samples/synchronization
:host-os: unix
:board: qemu_arc/qemu_em
:goals: run
This will build an image with the synchronization sample app, boot it using
QEMU, and display the following console output:
.. code-block:: console
*** Booting Zephyr OS build zephyr-v2.2.0-2486-g7dbfcf4bab57 ***
threadA: Hello World from qemu_arc!
threadB: Hello World from qemu_arc!
threadA: Hello World from qemu_arc!
threadB: Hello World from qemu_arc!
Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`.
Debugging
=========
Refer to the detailed overview about :ref:`application_debugging`.
References
**********
1.`Programmers Reference Manual for ARC HS
<path_to_url`_
``` | /content/code_sandbox/boards/qemu/arc/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 643 |
```unknown
CONFIG_CONSOLE=y
CONFIG_NO_OPTIMIZATIONS=y
``` | /content/code_sandbox/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 14 |
```yaml
identifier: nrf5340bsim/nrf5340/cpuapp
name: NRF53 BabbleSim - Application Core target
type: native
arch: posix
simulation: native
env:
- BSIM_OUT_PATH
toolchain:
- zephyr
testing:
ignore_tags:
- gpio
- modem
- uart
- bsim_skip_CI
``` | /content/code_sandbox/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 83 |
```unknown
/*
*
*/
/dts-v1/;
#include <mem.h>
#include <arm/nordic/nrf54l15_cpuapp.dtsi>
/ {
model = "Nordic NRF54L15 BSIM NRF54L15 Application";
compatible = "bsim,nrf54l15-bsim-nrf54l15-cpuapp", "bsim,nrf54";
chosen {
zephyr,entropy = &rng;
zephyr,flash-controller = &rram_controller;
zephyr,flash = &cpuapp_rram;
};
/delete-node/ cpus;
/delete-node/ clocks;
/delete-node/ sw-pwm;
soc {
/delete-node/ memory@20000000;
/delete-node/ memory@2002f000;
peripheral@50000000 {
/delete-node/ spi@4a000;
/delete-node/ uart@4a000;
/delete-node/ vpr@4c000;
/delete-node/ mailbox@0;
/delete-node/ interrupt-controller@f0000000;
/delete-node/ gpio@50400;
/delete-node/ i2c@c6000;
/delete-node/ spi@c6000;
/delete-node/ uart@c6000;
/delete-node/ i2c@c7000;
/delete-node/ spi@c7000;
/delete-node/ uart@c7000;
/delete-node/ i2c@c8000;
/delete-node/ spi@c8000;
/delete-node/ uart@c8000;
/delete-node/ pwm@d2000;
/delete-node/ pwm@d3000;
/delete-node/ pwm@d4000;
/delete-node/ adc@d5000;
/delete-node/ nfct@d6000;
/delete-node/ gpio@d8200;
/delete-node/ gpiote@da000;
/delete-node/ i2s@dd000;
/delete-node/ qdec@e0000;
/delete-node/ qdec@e1000;
/delete-node/ i2c@104000;
/delete-node/ spi@104000;
/delete-node/ uart@104000;
/delete-node/ watchdog@108000;
/delete-node/ watchdog@109000;
/delete-node/ gpio@10a000;
/delete-node/ gpiote@10c000;
};
/delete-node/ spu@50003000;
/delete-node/ gpiote@5000d000;
/delete-node/ crypto@50844000;
};
rng: rng {
status = "okay";
compatible = "zephyr,native-posix-rng";
};
};
&grtc {
owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>;
/* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */
child-owned-channels = <3 4 7 8 9 10 11>;
status = "okay";
};
&cpuapp_rram {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
storage_partition: partition@0 {
label = "storage";
reg = <0x0 DT_SIZE_K(500)>;
};
};
};
&temp {
status = "okay";
};
&radio {
status = "okay";
/* This feature is not yet supported by the RADIO model */
/delete-property/ dfe-supported;
};
&clock {
status = "okay";
};
``` | /content/code_sandbox/boards/native/nrf_bsim/nrf54l15bsim_nrf54l15_cpuapp.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 800 |
```yaml
identifier: nrf54l15bsim/nrf54l15/cpuapp
name: NRF54L15 BabbleSim - Application Core target
type: native
arch: posix
simulation: native
env:
- BSIM_OUT_PATH
toolchain:
- zephyr
supported:
- counter
testing:
ignore_tags:
- gpio
- modem
- uart
- bsim_skip_CI
``` | /content/code_sandbox/boards/native/nrf_bsim/nrf54l15bsim_nrf54l15_cpuapp.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 93 |
```c
/*
*
*/
#include <stdbool.h>
#include <stdlib.h>
#include "bs_tracing.h"
#include "bstests.h"
#include "bs_cmd_line.h"
#include "bs_dynargs.h"
#include "posix_native_task.h"
#include "nsi_tracing.h"
#include "nsi_main.h"
#include "nsi_cpu_ctrl.h"
static const char exe_name[] = "nrf_bsim options:";
static char *testid;
static bool cpu_autostart;
static void cmd_testid_found(char *argv, int offset)
{
bst_set_testapp_mode(testid);
}
static void cmd_testlist_found(char *argv, int offset)
{
bst_print_testslist();
nsi_exit(0);
}
static void cmd_autostart_found(char *argv, int offset)
{
nsi_cpu_set_auto_start(CONFIG_NATIVE_SIMULATOR_MCU_N, cpu_autostart);
}
static void nrfbsim_register_args(void)
{
static bs_args_struct_t args_struct_toadd[] = {
{
.option = "cpu" STRINGIFY(CONFIG_NATIVE_SIMULATOR_MCU_N) "_testid",
.name = "testid",
.type = 's',
.dest = (void *)&testid,
.call_when_found = cmd_testid_found,
.descript = "Which of the bs tests shall be run. Run -testslist for more info"
},
{
.is_switch = true,
.option = "cpu" STRINGIFY(CONFIG_NATIVE_SIMULATOR_MCU_N) "_testslist",
.type = 'b',
.call_when_found = cmd_testlist_found,
.descript = "Print information about the available bs application tests"
},
#if (CONFIG_NATIVE_SIMULATOR_MCU_N == CONFIG_NATIVE_SIMULATOR_PRIMARY_MCU_INDEX)
{
.option = "testid",
.name = "testid",
.type = 's',
.dest = (void *)&testid,
.call_when_found = cmd_testid_found,
.descript = "Alias of cpu" STRINGIFY(CONFIG_NATIVE_SIMULATOR_MCU_N) "_testid"
},
{
.is_switch = true,
.option = "testslist",
.type = 'b',
.call_when_found = cmd_testlist_found,
.descript = "Alias of cpu" STRINGIFY(CONFIG_NATIVE_SIMULATOR_MCU_N) "_testslist"
},
#endif
{
.option = "cpu" STRINGIFY(CONFIG_NATIVE_SIMULATOR_MCU_N) "_autostart",
.name = "autostart",
.type = 'b',
.dest = (void *)&cpu_autostart,
.call_when_found = cmd_autostart_found,
.descript = "Automatically start CPU" STRINGIFY(CONFIG_NATIVE_SIMULATOR_MCU_N)
},
ARG_TABLE_ENDMARKER
};
bs_add_extra_dynargs(args_struct_toadd);
bs_args_override_exe_name((char *)exe_name);
}
NATIVE_TASK(nrfbsim_register_args, PRE_BOOT_1, 100);
``` | /content/code_sandbox/boards/native/nrf_bsim/argparse.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 658 |
```yaml
identifier: nrf52_bsim
name: NRF52 BabbleSim board
type: native
arch: posix
simulation: native
env:
- BSIM_OUT_PATH
toolchain:
- zephyr
testing:
ignore_tags:
- modem
- bsim_skip_CI
supported:
- gpio
- counter
``` | /content/code_sandbox/boards/native/nrf_bsim/nrf52_bsim.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 75 |
```cmake
# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
# - power@40000000 & clock@40000000 & bprot@40000000
# - acl@4001e000 & flash-controller@4001e000
list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")
``` | /content/code_sandbox/boards/native/nrf_bsim/pre_dt_board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 72 |
```unknown
CONFIG_CONSOLE=y
CONFIG_NO_OPTIMIZATIONS=y
``` | /content/code_sandbox/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 14 |
```c
/*
*
*/
#include <stdbool.h>
#include <stdint.h>
#include "fake_timer.h"
#include <zephyr/arch/posix/posix_soc_if.h>
#include <posix_board_if.h>
#include <posix_soc.h>
#include "nsi_hw_scheduler.h"
/**
* Replacement to the kernel k_busy_wait()
* Will block this thread (and therefore the whole Zephyr) during usec_to_wait
*
* Note that interrupts may be received in the meanwhile and that therefore this
* thread may lose context.
* Therefore the wait time may be considerably longer.
*
* All this function ensures is that it will return after usec_to_wait or later.
*/
void arch_busy_wait(uint32_t usec_to_wait)
{
bs_time_t time_end = nsi_hws_get_time() + usec_to_wait;
while (nsi_hws_get_time() < time_end) {
/*
* There may be wakes due to other interrupts or nested calls to
* k_busy_wait in interrupt handlers
*/
nhw_fake_timer_wake_in_time(CONFIG_NATIVE_SIMULATOR_MCU_N, time_end);
posix_halt_cpu();
}
}
/**
* Will block this thread (and therefore the whole Zephyr) during usec_to_waste
*
* Very similar to arch_busy_wait(), but if an interrupt or context switch
* occurs this function will continue waiting after, ensuring that
* usec_to_waste are spent in this context, irrespectively of how much more
* time would be spent on interrupt handling or possible switched-in tasks.
*
* Can be used to emulate code execution time.
*/
void posix_cpu_hold(uint32_t usec_to_waste)
{
bs_time_t time_start;
int64_t to_wait = usec_to_waste;
while (to_wait > 0) {
/*
* There may be wakes due to other interrupts or nested calls to
* cpu_hold in interrupt handlers
*/
time_start = nsi_hws_get_time();
nhw_fake_timer_wake_in_time(CONFIG_NATIVE_SIMULATOR_MCU_N, time_start + to_wait);
posix_change_cpu_state_and_wait(true);
to_wait -= nsi_hws_get_time() - time_start;
posix_irq_handler();
}
}
``` | /content/code_sandbox/boards/native/nrf_bsim/cpu_wait.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 476 |
```objective-c
/*
*
*/
#ifndef BOARDS_POSIX_NRF52_BSIM_BOARD_IRQ_H
#define BOARDS_POSIX_NRF52_BSIM_BOARD_IRQ_H
#include <zephyr/types.h>
#include "../common/irq/board_irq.h"
#ifdef __cplusplus
extern "C" {
#endif
void nrfbsim_WFE_model(void);
void nrfbsim_SEV_model(void);
#define IRQ_ZERO_LATENCY BIT(1) /* Unused in this board*/
#ifdef __cplusplus
}
#endif
#endif /* BOARDS_POSIX_NRF52_BSIM_BOARD_IRQ_H */
``` | /content/code_sandbox/boards/native/nrf_bsim/board_irq.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 117 |
```unknown
/*
*
*/
/dts-v1/;
#include <mem.h>
#include <arm/nordic/nrf5340_cpunet.dtsi>
/ {
model = "Nordic NRF5340 BSIM NRF5340 Network";
compatible = "bsim,nrf5340-bsim-nrf5340-cpunet","bsim,nrf53";
/* We need to remove aliases to nodes we delete */
aliases {
/delete-property/ sram-0;
/delete-property/ sram-1;
/delete-property/ gpiote-0;
/delete-property/ wdt-0;
/delete-property/ i2c-0;
/delete-property/ spi-0;
/delete-property/ gpio-0;
/delete-property/ gpio-1;
};
chosen {
zephyr,bt-hci-ipc = &ipc0;
nordic,802154-spinel-ipc = &ipc0;
zephyr,ieee802154 = &ieee802154;
/delete-property/ zephyr,flash-controller;
zephyr,flash = &flash1;
};
soc {
/delete-node/ memory@20000000;
/delete-node/ memory@21000000;
/delete-node/ gpiote@4100a000;
/delete-node/ watchdog@4100b000;
/delete-node/ i2c@41013000;
/delete-node/ spi@41013000;
/delete-node/ acl@41080000;
/delete-node/ vmc@41081000;
/delete-node/ gpio@418c0500;
/delete-node/ gpio@418c0800;
};
/delete-node/ cpus;
/delete-node/ sw-pwm;
};
&radio {
/* These features are not yet supported by the RADIO model */
/delete-property/ dfe-supported;
};
&ieee802154 {
status = "okay";
};
&flash1 {
reg = <0x01000000 DT_SIZE_K(256)>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
storage_partition: partition@0 {
label = "storage";
reg = <0x00000000 DT_SIZE_K(256)>;
};
};
};
/* We re-use the IPC shared buffer definition from the real HW. But note the start address of the
* buffer won't be used.
*/
#include <../boards/nordic/nrf5340dk/nrf5340_shared_sram_planning_conf.dtsi>
``` | /content/code_sandbox/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 565 |
```yaml
boards:
- name: nrf52_bsim
vendor: zephyr
socs:
- name: native
- name: nrf5340bsim
vendor: zephyr
socs:
- name: nrf5340
- name: nrf54l15bsim
vendor: zephyr
socs:
- name: nrf54l15
# Note the 53 and 54 are referring to the real SOC yamls, but we only use their name and cpu-cluster
# definitions. In practice these board uses the same native SOC (SOC_POSIX) as the nrf52_bsim
``` | /content/code_sandbox/boards/native/nrf_bsim/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 144 |
```c
/*
*
*
* SW side of the IRQ handling
*/
#include <stdint.h>
#include <zephyr/irq_offload.h>
#include <zephyr/kernel_structs.h>
#include "kernel_internal.h"
#include "kswap.h"
#include "irq_ctrl.h"
#include "posix_core.h"
#include "board_soc.h"
#include <zephyr/sw_isr_table.h>
#include "soc.h"
#include "bs_tracing.h"
#include <zephyr/tracing/tracing.h>
#include "bstests.h"
static bool CPU_will_be_awaken_from_WFE;
typedef void (*normal_irq_f_ptr)(const void *);
typedef int (*direct_irq_f_ptr)(void);
static struct _isr_list irq_vector_table[NHW_INTCTRL_MAX_INTLINES];
static int currently_running_irq = -1;
static inline void vector_to_irq(int irq_nbr, int *may_swap)
{
/**
* Call the test IRQ sniffer, and if it returns
* true ignore the interrupt
*/
bool ret;
ret = bst_irq_sniffer(irq_nbr);
if (ret) {
return;
}
bs_trace_raw_time(6, "Vectoring to irq %i (%s)\n", irq_nbr,
hw_irq_ctrl_get_name(CONFIG_NATIVE_SIMULATOR_MCU_N, irq_nbr));
sys_trace_isr_enter();
if (irq_vector_table[irq_nbr].func == NULL) { /* LCOV_EXCL_BR_LINE */
/* LCOV_EXCL_START */
posix_print_error_and_exit("Received irq %i without a "
"registered handler\n",
irq_nbr);
/* LCOV_EXCL_STOP */
} else {
if (irq_vector_table[irq_nbr].flags & ISR_FLAG_DIRECT) {
*may_swap |= ((direct_irq_f_ptr)
irq_vector_table[irq_nbr].func)();
} else {
#ifdef CONFIG_PM
posix_irq_check_idle_exit();
#endif
((normal_irq_f_ptr)irq_vector_table[irq_nbr].func)
(irq_vector_table[irq_nbr].param);
*may_swap = 1;
}
}
sys_trace_isr_exit();
bs_trace_raw_time(7, "Irq %i (%s) ended\n", irq_nbr,
hw_irq_ctrl_get_name(CONFIG_NATIVE_SIMULATOR_MCU_N, irq_nbr));
}
/**
* When an interrupt is raised, this function is called to handle it and, if
* needed, swap to a re-enabled thread
*
* Note that even that this function is executing in a Zephyr thread, it is
* effectively the model of the interrupt controller passing context to the IRQ
* handler and therefore its priority handling
*/
void posix_irq_handler(void)
{
uint64_t irq_lock;
int irq_nbr;
static int may_swap;
const int cpu_n = CONFIG_NATIVE_SIMULATOR_MCU_N;
irq_lock = hw_irq_ctrl_get_current_lock(cpu_n);
if (irq_lock) {
/* "spurious" wakes can happen with interrupts locked */
return;
}
irq_nbr = hw_irq_ctrl_get_highest_prio_irq(cpu_n);
if (irq_nbr == -1) {
/* This is a phony interrupt during a busy wait, no need for more */
return;
}
if (_kernel.cpus[0].nested == 0) {
may_swap = 0;
}
_kernel.cpus[0].nested++;
do {
int last_current_running_prio = hw_irq_ctrl_get_cur_prio(cpu_n);
int last_running_irq = currently_running_irq;
hw_irq_ctrl_set_cur_prio(cpu_n, hw_irq_ctrl_get_prio(cpu_n, irq_nbr));
hw_irq_ctrl_clear_irq(cpu_n, irq_nbr);
currently_running_irq = irq_nbr;
vector_to_irq(irq_nbr, &may_swap);
currently_running_irq = last_running_irq;
hw_irq_ctrl_reeval_level_irq(cpu_n, irq_nbr);
hw_irq_ctrl_set_cur_prio(cpu_n, last_current_running_prio);
} while ((irq_nbr = hw_irq_ctrl_get_highest_prio_irq(cpu_n)) != -1);
_kernel.cpus[0].nested--;
/* Call swap if all the following is true:
* 1) may_swap was enabled
* 2) We are not nesting irq_handler calls (interrupts)
* 3) Next thread to run in the ready queue is not this thread
* 4) we are in a irq postfix (not just in a WFE)
*/
if (may_swap
&& (hw_irq_ctrl_get_cur_prio(cpu_n) == 256)
&& (CPU_will_be_awaken_from_WFE == false)
&& (_kernel.ready_q.cache) && (_kernel.ready_q.cache != _current)) {
z_swap_irqlock(irq_lock);
}
}
/**
* Thru this function the IRQ controller can raise an immediate interrupt which
* will interrupt the SW itself
* (this function should only be called from the HW model code, from SW threads)
*/
void posix_irq_handler_im_from_sw(void)
{
/*
* if a higher priority interrupt than the possibly currently running is
* pending we go immediately into irq_handler() to vector into its
* handler
*/
if (hw_irq_ctrl_get_highest_prio_irq(CONFIG_NATIVE_SIMULATOR_MCU_N) != -1) {
if (!posix_is_cpu_running()) { /* LCOV_EXCL_BR_LINE */
/* LCOV_EXCL_START */
posix_print_error_and_exit("programming error: %s "
"called from a HW model thread\n",
__func__);
/* LCOV_EXCL_STOP */
}
posix_irq_handler();
}
}
/**
* @brief Disable all interrupts on the CPU
*
* This routine disables interrupts. It can be called from either interrupt,
* task or fiber level. This routine returns an architecture-dependent
* lock-out key representing the "interrupt disable state" prior to the call;
* this key can be passed to irq_unlock() to re-enable interrupts.
*
* The lock-out key should only be used as the argument to the irq_unlock()
* API. It should never be used to manually re-enable interrupts or to inspect
* or manipulate the contents of the source register.
*
* This function can be called recursively: it will return a key to return the
* state of interrupt locking to the previous level.
*
* WARNINGS
* Invoking a kernel routine with interrupts locked may result in
* interrupts being re-enabled for an unspecified period of time. If the
* called routine blocks, interrupts will be re-enabled while another
* thread executes, or while the system is idle.
*
* The "interrupt disable state" is an attribute of a thread. Thus, if a
* fiber or task disables interrupts and subsequently invokes a kernel
* routine that causes the calling thread to block, the interrupt
* disable state will be restored when the thread is later rescheduled
* for execution.
*
* @return An architecture-dependent lock-out key representing the
* "interrupt disable state" prior to the call.
*
*/
unsigned int posix_irq_lock(void)
{
return hw_irq_ctrl_change_lock(CONFIG_NATIVE_SIMULATOR_MCU_N, true);
}
/**
* @brief Enable all interrupts on the CPU
*
* This routine re-enables interrupts on the CPU. The @a key parameter is a
* board-dependent lock-out key that is returned by a previous invocation of
* board_irq_lock().
*
* This routine can be called from either interrupt, task or fiber level.
*/
void posix_irq_unlock(unsigned int key)
{
hw_irq_ctrl_change_lock(CONFIG_NATIVE_SIMULATOR_MCU_N, key);
}
void posix_irq_full_unlock(void)
{
hw_irq_ctrl_change_lock(CONFIG_NATIVE_SIMULATOR_MCU_N, false);
}
void posix_irq_enable(unsigned int irq)
{
hw_irq_ctrl_enable_irq(CONFIG_NATIVE_SIMULATOR_MCU_N, irq);
}
void posix_irq_disable(unsigned int irq)
{
hw_irq_ctrl_disable_irq(CONFIG_NATIVE_SIMULATOR_MCU_N, irq);
}
int posix_irq_is_enabled(unsigned int irq)
{
return hw_irq_ctrl_is_irq_enabled(CONFIG_NATIVE_SIMULATOR_MCU_N, irq);
}
int posix_get_current_irq(void)
{
return currently_running_irq;
}
/**
* Configure a static interrupt.
*
* posix_isr_declare will populate the interrupt table table with the
* interrupt's parameters, the vector table and the software ISR table.
*
* We additionally set the priority in the interrupt controller at
* runtime.
*
* @param irq_p IRQ line number
* @param flags [plug it directly (1), or as a SW managed interrupt (0)]
* @param isr_p Interrupt service routine
* @param isr_param_p ISR parameter
* @param flags_p IRQ options
*/
void posix_isr_declare(unsigned int irq_p, int flags, void isr_p(const void *),
const void *isr_param_p)
{
if (irq_p >= NHW_INTCTRL_MAX_INTLINES) {
bs_trace_error_time_line("Attempted to configure not existent interrupt %u\n",
irq_p);
return;
}
irq_vector_table[irq_p].irq = irq_p;
irq_vector_table[irq_p].func = isr_p;
irq_vector_table[irq_p].param = isr_param_p;
irq_vector_table[irq_p].flags = flags;
}
/**
* @internal
*
* @brief Set an interrupt's priority
*
* Lower values take priority over higher values.
*/
void posix_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
{
hw_irq_ctrl_prio_set(CONFIG_NATIVE_SIMULATOR_MCU_N, irq, prio);
}
/**
* Similar to ARM's NVIC_SetPendingIRQ
* set a pending IRQ from SW
*
* Note that this will interrupt immediately if the interrupt is not masked and
* IRQs are not locked, and this interrupt has higher priority than a possibly
* currently running interrupt
*/
void posix_sw_set_pending_IRQ(unsigned int IRQn)
{
hw_irq_ctrl_raise_im_from_sw(CONFIG_NATIVE_SIMULATOR_MCU_N, IRQn);
}
/**
* Similar to ARM's NVIC_ClearPendingIRQ
* clear a pending irq from SW
*/
void posix_sw_clear_pending_IRQ(unsigned int IRQn)
{
hw_irq_ctrl_clear_irq(CONFIG_NATIVE_SIMULATOR_MCU_N, IRQn);
}
#ifdef CONFIG_IRQ_OFFLOAD
/**
* Storage for functions offloaded to IRQ
*/
static void (*off_routine)(const void *);
static const void *off_parameter;
/**
* IRQ handler for the SW interrupt assigned to irq_offload()
*/
static void offload_sw_irq_handler(const void *a)
{
ARG_UNUSED(a);
off_routine(off_parameter);
}
/**
* @brief Run a function in interrupt context
*
* Raise the SW IRQ assigned to handled this
*/
void posix_irq_offload(void (*routine)(const void *), const void *parameter)
{
off_routine = routine;
off_parameter = parameter;
posix_isr_declare(OFFLOAD_SW_IRQ, 0, offload_sw_irq_handler, NULL);
posix_irq_enable(OFFLOAD_SW_IRQ);
posix_sw_set_pending_IRQ(OFFLOAD_SW_IRQ);
posix_irq_disable(OFFLOAD_SW_IRQ);
}
#endif
/*
* Very simple model of the WFE and SEV ARM instructions
* which seems good enough for the Nordic controller
*/
static bool CPU_event_set_flag;
void nrfbsim_WFE_model(void)
{
if (CPU_event_set_flag == false) {
CPU_will_be_awaken_from_WFE = true;
posix_halt_cpu();
CPU_will_be_awaken_from_WFE = false;
}
CPU_event_set_flag = false;
}
void nrfbsim_SEV_model(void)
{
CPU_event_set_flag = true;
}
``` | /content/code_sandbox/boards/native/nrf_bsim/irq_handler.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,510 |
```c
/*
*
*/
#include <stdio.h>
#include <stdlib.h>
#include <soc.h>
#include <posix_native_task.h>
#include <nsi_cpu_if.h>
#include "bstests.h"
#include "bs_tracing.h"
#include "phy_sync_ctrl.h"
#include "nsi_hw_scheduler.h"
#include "nsi_cpu_ctrl.h"
#include "nsi_host_trampolines.h"
/*
* These hooks are to be named nsif_cpu<cpu_number>_<hook_name>, for example nsif_cpu0_boot
*/
#define nsif_cpun_pre_cmdline_hooks _CONCAT(_CONCAT(nsif_cpu, CONFIG_NATIVE_SIMULATOR_MCU_N),\
_pre_cmdline_hooks)
#define nsif_cpun_save_test_arg _CONCAT(_CONCAT(nsif_cpu, CONFIG_NATIVE_SIMULATOR_MCU_N),\
_save_test_arg)
#define nsif_cpun_pre_hw_init_hooks _CONCAT(_CONCAT(nsif_cpu, CONFIG_NATIVE_SIMULATOR_MCU_N),\
_pre_hw_init_hooks)
#define nsif_cpun_boot _CONCAT(_CONCAT(nsif_cpu, CONFIG_NATIVE_SIMULATOR_MCU_N),\
_boot)
#define nsif_cpun_cleanup _CONCAT(_CONCAT(nsif_cpu, CONFIG_NATIVE_SIMULATOR_MCU_N),\
_cleanup)
#define nsif_cpun_irq_raised _CONCAT(_CONCAT(nsif_cpu, CONFIG_NATIVE_SIMULATOR_MCU_N),\
_irq_raised)
#define nsif_cpun_test_hook _CONCAT(_CONCAT(nsif_cpu, CONFIG_NATIVE_SIMULATOR_MCU_N),\
_test_hook)
#define nsif_cpun_irq_raised_from_sw _CONCAT(_CONCAT(nsif_cpu, CONFIG_NATIVE_SIMULATOR_MCU_N),\
_irq_raised_from_sw)
NATIVE_SIMULATOR_IF void nsif_cpun_pre_cmdline_hooks(void)
{
run_native_tasks(_NATIVE_PRE_BOOT_1_LEVEL);
#if defined(CONFIG_NATIVE_SIMULATOR_AUTOSTART_MCU)
nsi_cpu_set_auto_start(CONFIG_NATIVE_SIMULATOR_MCU_N, true);
#endif
}
#define TESTCASAE_ARGV_ALLOCSIZE 128
static struct {
char **test_case_argv;
int test_case_argc;
int allocated_size;
} test_args;
NATIVE_SIMULATOR_IF void nsif_cpun_save_test_arg(char *argv)
{
if (test_args.test_case_argc >= test_args.allocated_size) {
test_args.allocated_size += TESTCASAE_ARGV_ALLOCSIZE;
test_args.test_case_argv = nsi_host_realloc(test_args.test_case_argv,
test_args.allocated_size * sizeof(char *));
if (test_args.test_case_argv == NULL) { /* LCOV_EXCL_BR_LINE */
bs_trace_error_line("Can't allocate memory\n"); /* LCOV_EXCL_LINE */
}
}
bs_trace_raw(9, "cmdarg: adding '%s' to testcase args[%i]\n",
argv, test_args.test_case_argc);
test_args.test_case_argv[test_args.test_case_argc++] = argv;
}
static void test_args_free(void)
{
if (test_args.test_case_argv) {
nsi_host_free(test_args.test_case_argv);
test_args.test_case_argv = NULL;
}
}
NATIVE_TASK(test_args_free, ON_EXIT_PRE, 100);
NATIVE_SIMULATOR_IF void nsif_cpun_pre_hw_init_hooks(void)
{
run_native_tasks(_NATIVE_PRE_BOOT_2_LEVEL);
phy_sync_ctrl_connect_to_2G4_phy();
/* We pass to a possible testcase its command line arguments */
bst_pass_args(test_args.test_case_argc, test_args.test_case_argv);
phy_sync_ctrl_pre_boot2();
}
NATIVE_SIMULATOR_IF void nsif_cpun_boot(void)
{
run_native_tasks(_NATIVE_PRE_BOOT_3_LEVEL);
bst_pre_init();
phy_sync_ctrl_pre_boot3();
posix_boot_cpu();
run_native_tasks(_NATIVE_FIRST_SLEEP_LEVEL);
bst_post_init();
}
NATIVE_SIMULATOR_IF int nsif_cpun_cleanup(void)
{
/*
* Note posix_soc_clean_up() may not return, but in that case,
* nsif_cpun_cleanup() will be called again
*/
posix_soc_clean_up();
uint8_t bst_result = bst_delete();
return bst_result;
}
NATIVE_SIMULATOR_IF void nsif_cpun_irq_raised(void)
{
posix_interrupt_raised();
}
NATIVE_SIMULATOR_IF int nsif_cpun_test_hook(void *p)
{
(void) p;
bst_tick(nsi_hws_get_time());
return 0;
}
NATIVE_SIMULATOR_IF void nsif_cpun_irq_raised_from_sw(void)
{
void posix_irq_handler_im_from_sw(void);
posix_irq_handler_im_from_sw();
}
``` | /content/code_sandbox/boards/native/nrf_bsim/nsi_if.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,005 |
```objective-c
/*
*
*/
#ifndef _BOARD_POSIX_NRF52_BSIM_TIME_MACHINE_H
#define _BOARD_POSIX_NRF52_BSIM_TIME_MACHINE_H
#include "bs_types.h"
#include "time_machine_if.h"
#include <zephyr/toolchain.h>
#ifdef __cplusplus
extern "C" {
#endif
/* This header and prototype exists for backwards compatibility with old bsim tests */
void tm_set_phy_max_resync_offset(bs_time_t offset_in_us);
#ifdef __cplusplus
}
#endif
#endif
``` | /content/code_sandbox/boards/native/nrf_bsim/time_machine.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 104 |
```c
/*
*
*/
/*
* Here we define the shared memory buffers for the RPMSG IPC back-end in simulation.
* In real HW, these are booked in RAM thru device tree configuration.
* In this simulated target, we just define them at build time to have the size defined
* in device tree.
*
* Note that this file is only compiled as part of the application core image, and therefore
* when the network core is built with the IPC service, we cannot produce an executable
* with the network core image alone, as we would lack this buffer during linking.
*/
#include "nsi_cpu_if.h"
#include <zephyr/device.h>
#define DT_DRV_COMPAT zephyr_ipc_openamp_static_vrings
#define DEFINE_BACKEND_BUFFER(i) \
NATIVE_SIMULATOR_IF \
char IPC##i##_shm_buffer[DT_REG_SIZE(DT_INST_PHANDLE(i, memory_region))];
DT_INST_FOREACH_STATUS_OKAY(DEFINE_BACKEND_BUFFER)
``` | /content/code_sandbox/boards/native/nrf_bsim/ipc_backend.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 195 |
```unknown
/*
*
*/
/dts-v1/;
#include <mem.h>
#include <arm/nordic/nrf52833.dtsi>
/* We resuse the pinctrl definitions directly from the real board : */
#include <../boards/nordic/nrf52833dk/nrf52833dk_nrf52833-pinctrl.dtsi>
/ {
model = "nrf52 bsim";
compatible = "bsim,nrf52833";
/* We need to remove aliases to nodes we delete */
aliases {
/delete-property/ i2c-0;
/delete-property/ i2c-1;
/delete-property/ spi-0;
/delete-property/ spi-1;
/delete-property/ spi-2;
/delete-property/ spi-3;
/delete-property/ adc-0;
/delete-property/ wdt-0;
/delete-property/ pwm-0;
/delete-property/ pwm-1;
/delete-property/ pwm-2;
/delete-property/ pwm-3;
/delete-property/ qdec-0;
};
chosen {
zephyr,ieee802154 = &ieee802154;
zephyr,flash = &flash0;
/* UART used by the BT controller UART HCI driver by default: */
zephyr,bt-c2h-uart = &uart1;
};
soc {
/delete-node/ memory@20000000;
/delete-node/ adc@40007000;
/delete-node/ i2c@40003000;
/delete-node/ i2c@40004000;
/delete-node/ pwm@4001c000;
/delete-node/ pwm@40021000;
/delete-node/ pwm@40022000;
/delete-node/ pwm@4002d000;
/delete-node/ qdec@40012000;
/delete-node/ spi@40003000;
/delete-node/ spi@40004000;
/delete-node/ spi@40023000;
/delete-node/ spi@4002f000;
/delete-node/ nfct@40005000;
/delete-node/ watchdog@40010000;
/delete-node/ acl@4001e000;
/delete-node/ usbd@40027000;
};
/delete-node/ sw-pwm;
};
&radio {
/* These features are not yet supported by the RADIO model */
/delete-property/ dfe-supported;
};
&gpiote {
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&ieee802154 {
status = "okay";
};
&flash0 {
reg = <0x00000000 DT_SIZE_K(512)>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
storage_partition: partition@0 {
label = "storage";
reg = <0x00000000 DT_SIZE_K(512)>;
};
};
};
&uart0 {
compatible = "nordic,nrf-uarte";
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-1 = <&uart0_sleep>;
pinctrl-names = "default", "sleep";
};
&uart1 {
compatible = "nordic,nrf-uarte";
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart1_default>;
pinctrl-1 = <&uart1_sleep>;
pinctrl-names = "default", "sleep";
hw-flow-control;
bt_hci_uart: bt_hci_uart {
compatible = "zephyr,bt-hci-uart";
status = "okay";
};
};
``` | /content/code_sandbox/boards/native/nrf_bsim/nrf52_bsim.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 830 |
```unknown
if SOC_SERIES_BSIM_NRFXX
config BUILD_OUTPUT_BIN
default n
config BUILD_OUTPUT_EXE
# When the IPC service is used, the net core image requires the application core image, as it needs
# access to its IPC buffer. Without it, the executable cannot be built.
default y if !(BOARD_NRF5340BSIM_NRF5340_CPUNET && IPC_SERVICE && (NATIVE_SIMULATOR_EXTRA_IMAGE_PATHS = ""))
config OUTPUT_PRINT_MEMORY_USAGE
default n
config NATIVE_SIMULATOR_NUMBER_MCUS
default 2 if BOARD_NRF5340BSIM_NRF5340_CPUNET || BOARD_NRF5340BSIM_NRF5340_CPUAPP
default 1
config NATIVE_SIMULATOR_MCU_N
default 1 if BOARD_NRF5340BSIM_NRF5340_CPUNET
default 0
config NATIVE_SIMULATOR_AUTOSTART_MCU
default y if BOARD_NRF5340BSIM_NRF5340_CPUNET
config NATIVE_SIMULATOR_PRIMARY_MCU_INDEX
default 1 if SOC_SERIES_BSIM_NRF53X
default 0
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 1000000 if NRF_GRTC_TIMER
default 32768
config SYS_CLOCK_TICKS_PER_SEC
default 128 if !TICKLESS_KERNEL
default 10000 if NRF_GRTC_TIMER
default 32768
config BT_CTLR
default y if BOARD_NRF52_BSIM || BOARD_NRF5340BSIM_NRF5340_CPUNET || BOARD_NRF54L15BSIM_NRF54L15_CPUAPP
depends on BT
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
default 4096 if BT_HCI_IPC
default 4096 if NRF_802154_SER_HOST && BOARD_NRF5340BSIM_NRF5340_CPUAPP
default 4096 if NRF_802154_SER_RADIO && BOARD_NRF5340BSIM_NRF5340_CPUNET
if BOARD_NRF5340BSIM_NRF5340_CPUAPP
config IPC_SERVICE_BACKEND_RPMSG_SHMEM_RESET
default y if IPC_SERVICE_BACKEND_RPMSG
config BT_HCI_IPC
default y if BT
endif # BOARD_NRF5340BSIM_NRF5340_CPUAPP
# The 15.4 driver Tx encryption is currently not functional with this
# simulated board => we disable it by default. With this Openthread will normally
# default to encrypt packets on its own.
config NRF_802154_ENCRYPTION
default n
if CONSOLE
config POSIX_ARCH_CONSOLE
default y
endif # CONSOLE
endif # SOC_SERIES_BSIM_NRFXX
``` | /content/code_sandbox/boards/native/nrf_bsim/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 569 |
```objective-c
/*
*
*/
#ifndef BSIM_NRF_ARGS_H
#define BSIM_NRF_ARGS_H
#include "bsim_args_runner.h"
/* This header is present to avoid breaking backwards compatibility with old bsim tests */
#endif
``` | /content/code_sandbox/boards/native/nrf_bsim/argparse.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 46 |
```unknown
config BOARD_NRF52_BSIM
select SOC_POSIX
``` | /content/code_sandbox/boards/native/nrf_bsim/Kconfig.nrf52_bsim | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 15 |
```unknown
config BOARD_NRF54L15BSIM
select SOC_POSIX
``` | /content/code_sandbox/boards/native/nrf_bsim/Kconfig.nrf54l15bsim | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 17 |
```unknown
config BOARD_NRF52_BSIM
bool
select SOC_SERIES_BSIM_NRF52X
select SOC_COMPATIBLE_NRF52833
select NRF_RTC_TIMER
select CLOCK_CONTROL
help
NRF52 simulation model
Will produce a console Linux process which can be executed natively.
It needs the BabbleSim simulator both in compile time and to execute
config BOARD_NRF5340BSIM_NRF5340_CPUNET
bool
select SOC_SERIES_BSIM_NRF53X
select SOC_COMPATIBLE_NRF5340_CPUNET
select NRF_RTC_TIMER
select CLOCK_CONTROL
help
Simulated NRF53 Network core
Will produce a console Linux process which can be executed natively.
It needs the BabbleSim simulator both in compile time and to execute
config BOARD_NRF5340BSIM_NRF5340_CPUAPP
bool
select SOC_SERIES_BSIM_NRF53X
select SOC_COMPATIBLE_NRF5340_CPUAPP
select NRF_RTC_TIMER
select CLOCK_CONTROL
help
Simulated NRF53 Application core
Will produce a console Linux process which can be executed natively.
It needs the BabbleSim simulator both in compile time and to execute
config BOARD_NRF54L15BSIM_NRF54L15_CPUAPP
bool
select SOC_SERIES_BSIM_NRF54LX
select SOC_COMPATIBLE_NRF54L15
select SOC_COMPATIBLE_NRF54L15_CPUAPP
select CLOCK_CONTROL
help
Simulated NRF54L15 Application core
Will produce a console Linux process which can be executed natively.
It needs the BabbleSim simulator both in compile time and to execute
if SOC_SERIES_BSIM_NRFXX
# The following file is normally parsed only for the ARM architecture, which is
# used by Nordic SoCs, so to make the symbols defined in this file available for
# the simulated nrf5x_bsim boards, which use the POSIX architecture, the file
# must be read also from here.
source "soc/nordic/common/Kconfig.peripherals"
source "boards/native/common/extra_args/Kconfig"
endif # SOC_SERIES_BSIM_NRFXX
# This would eventually be shared by a possible family of simulated NRF boards
# which use BabbleSim. When that happens, we can move this to a common
# Kconfig file
config SOC_SERIES_BSIM_NRFXX
bool
select NATIVE_LIBRARY
select SOC_COMPATIBLE_NRF
select HAS_NRFX
select HAS_NORDIC_DRIVERS
select PINCTRL_DYNAMIC if PINCTRL
help
Any NRF simulated SOC with BabbleSim, based on the POSIX arch
config SOC_SERIES_BSIM_NRF52X
bool
select SOC_SERIES_BSIM_NRFXX
select SOC_COMPATIBLE_NRF52X
help
Any NRF52 simulated SOC with BabbleSim, based on the POSIX arch
config SOC_SERIES_BSIM_NRF53X
bool
select SOC_SERIES_BSIM_NRFXX
select SOC_COMPATIBLE_NRF53X
help
Any NRF53 simulated SOC with BabbleSim, based on the POSIX arch
config SOC_SERIES_BSIM_NRF54LX
bool
select SOC_SERIES_BSIM_NRFXX
select SOC_COMPATIBLE_NRF54LX
help
Any NRF54L simulated SOC with BabbleSim, based on the POSIX arch
if SOC_SERIES_BSIM_NRF53X
# Let's reuse the RTC sync options so applications which use it can be reused as is
source "soc/nordic/nrf53/Kconfig.sync_rtc"
endif # SOC_SERIES_BSIM_NRF53X
``` | /content/code_sandbox/boards/native/nrf_bsim/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 776 |
```unknown
CONFIG_CONSOLE=y
CONFIG_NO_OPTIMIZATIONS=y
# Start SYSCOUNTER on driver init
CONFIG_NRF_GRTC_START_SYSCOUNTER=y
``` | /content/code_sandbox/boards/native/nrf_bsim/nrf54l15bsim_nrf54l15_cpuapp_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```objective-c
/*
*
*/
/**
* @file Extra definitions provided by the board to soc.h
*
* Background:
* The POSIX ARCH/SOC/board layering is different than in normal archs
* The "SOC" does not provide almost any of the typical SOC functionality
* but that is left for the "board" to define it
* Device code may rely on the soc.h defining some things (like the interrupts
* numbers)
* Therefore this file is included from the inf_clock soc.h to allow a board
* to define that kind of SOC related snippets
*/
#ifndef BOARDS_POSIX_NRF_BSIM_BOARD_SOC_H
#define BOARDS_POSIX_NRF_BSIM_BOARD_SOC_H
#include <zephyr/toolchain.h>
#include <zephyr/sys/util.h>
#include <stdint.h>
#include <stdbool.h>
#include <zephyr/types.h>
#include <stddef.h>
#include <zephyr/irq.h>
#include <nrfx.h>
#include "cmsis.h"
#include "soc_nrf_common.h"
/* For offloading interrupts we can use any free interrupt */
#if defined(CONFIG_BOARD_NRF52_BSIM)
#define OFFLOAD_SW_IRQ SWI0_EGU0_IRQn
#elif defined(CONFIG_BOARD_NRF5340BSIM_NRF5340_CPUAPP)
#define OFFLOAD_SW_IRQ EGU0_IRQn
#elif defined(CONFIG_BOARD_NRF5340BSIM_NRF5340_CPUNET)
#define OFFLOAD_SW_IRQ SWI0_IRQn
#elif defined(CONFIG_BOARD_NRF54L15BSIM)
#define OFFLOAD_SW_IRQ SWI00_IRQn
#endif
#define FLASH_PAGE_ERASE_MAX_TIME_US 89700UL
#define FLASH_PAGE_MAX_CNT 256UL
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* BOARDS_POSIX_NRF_BSIM_BOARD_SOC_H */
``` | /content/code_sandbox/boards/native/nrf_bsim/board_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 382 |
```unknown
config BOARD_NRF5340BSIM
select SOC_POSIX
``` | /content/code_sandbox/boards/native/nrf_bsim/Kconfig.nrf5340bsim | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 16 |
```c
/*
*
*/
#include "nsi_main.h"
void posix_exit(int exit_code)
{
nsi_exit(exit_code);
}
``` | /content/code_sandbox/boards/native/nrf_bsim/common/posix_arch_if.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 26 |
```unknown
/*
*
*/
/dts-v1/;
#include <mem.h>
#include <arm/nordic/nrf5340_cpuapp.dtsi>
/ {
model = "Nordic NRF5340 BSIM NRF5340 Application";
compatible = "bsim,nrf5340-bsim-nrf5340-cpuapp","bsim,nrf53";
/* We need to remove aliases to nodes we delete */
aliases {
/delete-property/ sram-0;
/delete-property/ i2c-0;
/delete-property/ spi-0;
/delete-property/ i2c-1;
/delete-property/ spi-1;
/delete-property/ spi-4;
/delete-property/ i2c-2;
/delete-property/ spi-2;
/delete-property/ i2c-3;
/delete-property/ spi-3;
/delete-property/ wdt-0;
/delete-property/ wdt-1;
/delete-property/ pwm-0;
/delete-property/ pwm-1;
/delete-property/ pwm-2;
/delete-property/ pwm-3;
/delete-property/ pdm-0;
/delete-property/ i2s-0;
/delete-property/ qdec-0;
/delete-property/ qdec-1;
/delete-property/ gpio-0;
/delete-property/ gpio-1;
/delete-property/ gpiote-0;
};
chosen {
zephyr,entropy = &rng_hci;
zephyr,flash = &flash0;
zephyr,bt-hci = &bt_hci_ipc0;
nordic,802154-spinel-ipc = &ipc0;
zephyr,ieee802154 = &ieee802154;
};
soc {
/delete-node/ memory@20000000;
peripheral@50000000 {
/delete-node/ dcnf@0;
/delete-node/ oscillator@4000;
/delete-node/ regulator@4000;
/delete-node/ ctrlap@6000;
/delete-node/ i2c@8000;
/delete-node/ spi@8000;
/delete-node/ i2c@9000;
/delete-node/ spi@9000;
/delete-node/ spi@a000;
/delete-node/ i2c@b000;
/delete-node/ spi@b000;
/delete-node/ i2c@c000;
/delete-node/ spi@c000;
/delete-node/ adc@e000;
/delete-node/ watchdog@18000;
/delete-node/ watchdog@19000;
/delete-node/ comparator@1a000;
/delete-node/ pwm@21000;
/delete-node/ pwm@22000;
/delete-node/ pwm@23000;
/delete-node/ pwm@24000;
/delete-node/ pdm@26000;
/delete-node/ i2s@28000;
/delete-node/ qspi@2b000;
/delete-node/ nfct@2d000;
/delete-node/ qdec@33000;
/delete-node/ qdec@34000;
/delete-node/ usbd@36000;
/delete-node/ regulator@37000;
/delete-node/ kmu@39000;
/delete-node/ vmc@81000;
/delete-node/ gpio@842500;
/delete-node/ gpio@842800;
};
/delete-node/ spu@50003000;
/delete-node/ gpiote@5000d000;
/delete-node/ crypto@50844000;
};
/delete-node/ cpus;
/delete-node/ sw-pwm;
};
&ieee802154 {
status = "okay";
};
&flash0 {
reg = <0x00000000 DT_SIZE_K(1024)>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
storage_partition: partition@0 {
label = "storage";
reg = <0x00000000 DT_SIZE_K(1024)>;
};
};
};
/* We re-use the IPC shared buffer definition from the real HW. But note the start address of the
* buffer won't be used.
*/
#include <../boards/nordic/nrf5340dk/nrf5340_shared_sram_planning_conf.dtsi>
``` | /content/code_sandbox/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 979 |
```objective-c
/*
*
*/
#ifndef _BSTESTS_ENTRY_H
#define _BSTESTS_ENTRY_H
#include "bs_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* TEST HOOKS:
*
* You may register some of these functions in your testbench
*
* Note that you can overwrite this function pointers on the fly
*/
/*
* Will be called with the command line arguments for the testcase.
* This is BEFORE any SW has run, and before the HW has been initialized
* This is also before a possible initialization delay.
* Note that this function can be used for test pre-initialization steps
* like opening the back-channels. But you should not interact yet with the
* test ticker or other HW models.
*/
typedef void (*bst_test_args_t)(int, char**);
/* It will be called (in the HW models thread) before the CPU is booted,
* after the HW models have been initialized. Note that a possible delayed
* initialization may delay the execution of this function vs other devices
* tests pre-initialization
*/
typedef void (*bst_test_pre_init_t)(void);
/*
* It will be called (in the HW models thread) when the CPU goes to sleep
* for the first time
*/
typedef void (*bst_test_post_init_t)(void);
/* It will be called (in the HW models thread) each time the bst_timer ticks */
typedef void (*bst_test_tick_t)(bs_time_t time);
/*
* It will be called (in the HW models thread) when the execution is being
* terminated (clean up memory and close your files here)
*/
typedef void (*bst_test_delete_t)(void);
/*
* It will be called (in SW context) when a HW interrupt is raised.
* If it returns true, the normal interrupt handler will NOT be called and
* Zephyr will only see a spurious wake
* Note: Use this only to perform special tasks, like sniffing interrupts,
* or any other interrupt related cheat, but not as a normal interrupt handler
*/
typedef bool (*bst_test_irq_sniffer_t)(int irq_number);
/*
* This function will be called (in SW context) as a Zephyr PRE_KERNEL_1
* device driver initialization function
* Note that the app's main() has not executed yet, and the kernel is not yet
* fully ready => You canNOT spawn new threads without wait time yet (or it
* will crash)
*/
typedef void (*bst_test_fake_ddriver_prekernel_t)(void);
/*
* This function will be called (in SW context) as a Zephyr POST_KERNEL
* device driver initialization function
* You may spawn any test threads you may need here.
* Note that the app main() has not executed yet.
*/
typedef void (*bst_test_fake_ddriver_postkernel_t)(void);
/*
* This function will be called (in SW context) as the Zephyr application main
*/
typedef void (*bst_test_main_t)(void);
struct bst_test_instance {
char *test_id;
char *test_descr;
bst_test_args_t test_args_f;
bst_test_pre_init_t test_pre_init_f;
bst_test_post_init_t test_post_init_f;
bst_test_tick_t test_tick_f;
bst_test_delete_t test_delete_f;
bst_test_irq_sniffer_t test_irq_sniffer_f;
bst_test_fake_ddriver_prekernel_t test_fake_ddriver_prekernel_f;
bst_test_fake_ddriver_postkernel_t test_fake_ddriver_postkernel_f;
bst_test_main_t test_main_f;
};
#define BSTEST_END_MARKER \
{NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL}
struct bst_test_list {
struct bst_test_instance *test_instance;
struct bst_test_list *next;
};
typedef struct bst_test_list *(*bst_test_install_t)(struct bst_test_list
*test_tail);
struct bst_test_list *bst_add_tests(struct bst_test_list *tests,
const struct bst_test_instance *test_def);
void bst_set_testapp_mode(char *test_id);
void bst_pass_args(int argc, char **argv);
void bst_pre_init(void);
void bst_post_init(void);
void bst_main(void);
void bst_tick(bs_time_t Absolute_device_time);
bool bst_irq_sniffer(int irq_number);
uint8_t bst_delete(void);
/* These return codes need to fit in a uint8_t (0..255), where 0 = successful */
enum bst_result_t {Passed = 0, In_progress = 1, Failed = 2};
void bst_print_testslist(void);
/**
* Interface for the fake HW device (timer) dedicated to the tests
*/
void bst_ticker_set_period(bs_time_t tick_period);
void bst_ticker_set_next_tick_absolute(bs_time_t absolute_time);
void bst_ticker_set_next_tick_delta(bs_time_t absolute_time);
void bst_awake_cpu_asap(void);
#ifdef __cplusplus
}
#endif
#endif
``` | /content/code_sandbox/boards/native/nrf_bsim/common/bstests.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,039 |
```c
/*
*
*/
#include "bs_tracing.h"
#include "nsi_cpu_if.h"
/*
* Default (weak) implementation for nsif_cpu<n>_save_test_arg() expected by the argument
* parsing defined in bsim_args_runner.
* Note that the real implementation is provided by the board code.
* This exists in case the total device image is assembled lacking some of the embedded MCU images
* or the user tries to target a non-existent MCU
*/
static void save_test_arg_warn(const char *func, char *argv)
{
bs_trace_warning("%s not defined. You may be passing a test argument to a CPU without"
" image or a non-existent CPU. Argument \"%s\" will be ignored\n",
func, argv);
}
/* Define N instances of void nsif_cpu<n>_save_test_arg */
F_TRAMP_BODY_LIST(NATIVE_SIMULATOR_IF __attribute__((weak)) void nsif_cpu,
_save_test_arg(char *argv) { save_test_arg_warn(__func__, argv); })
``` | /content/code_sandbox/boards/native/nrf_bsim/common/bsim_extra_cpu_if_stubs.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 210 |
```objective-c
/*
*
*/
#ifndef BOARDS_POSIX_BSIM_COMMON_PHY_SYNC_CTRL_H
#define BOARDS_POSIX_BSIM_COMMON_PHY_SYNC_CTRL_H
#include "bs_types.h"
#ifdef __cplusplus
extern "C"{
#endif
void phy_sync_ctrl_set_last_phy_sync_time(bs_time_t time);
void phy_sync_ctrl_set_max_resync_offset(bs_time_t max_resync_offset);
void phy_sync_ctrl_connect_to_2G4_phy(void);
void phy_sync_ctrl_pre_boot2(void);
void phy_sync_ctrl_pre_boot3(void);
#ifdef __cplusplus
}
#endif
#endif /* BOARDS_POSIX_BSIM_COMMON_PHY_SYNC_CTRL_H */
``` | /content/code_sandbox/boards/native/nrf_bsim/common/phy_sync_ctrl.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 130 |
```c
/*
*
*/
#include <stdarg.h>
#include "bs_tracing.h"
/*
* Provide the posix_print_* functions required from all POSIX arch boards
* (This functions provide a lower level, more direct, print mechanism than
* Zephyr's printk or logger and therefore can be relied on even if the kernel
* is down.
*/
#if (CONFIG_NATIVE_SIMULATOR_NUMBER_MCUS > 1)
static const char *cpu_prefix = "CPU";
static const unsigned int cpu_number = CONFIG_NATIVE_SIMULATOR_MCU_N;
#else
static const char *cpu_prefix;
static const unsigned int cpu_number;
#endif /* (CONFIG_NATIVE_SIMULATOR_NUMBER_MCUS > 1) */
void posix_vprint_error_and_exit(const char *format, va_list vargs)
{
bs_trace_vprint(BS_TRACE_ERROR, cpu_prefix, cpu_number, 0, BS_TRACE_AUTOTIME, 0,
format, vargs);
}
void posix_vprint_warning(const char *format, va_list vargs)
{
bs_trace_vprint(BS_TRACE_WARNING, cpu_prefix, cpu_number, 0, BS_TRACE_AUTOTIME, 0,
format, vargs);
}
void posix_vprint_trace(const char *format, va_list vargs)
{
bs_trace_vprint(BS_TRACE_RAW, cpu_prefix, cpu_number, 2, BS_TRACE_AUTOTIME, 0,
format, vargs);
}
void posix_print_error_and_exit(const char *format, ...)
{
va_list variable_argsp;
va_start(variable_argsp, format);
posix_vprint_error_and_exit(format, variable_argsp);
va_end(variable_argsp);
}
void posix_print_warning(const char *format, ...)
{
va_list variable_argsp;
va_start(variable_argsp, format);
bs_trace_vprint(BS_TRACE_WARNING, cpu_prefix, cpu_number, 0, BS_TRACE_AUTOTIME, 0,
format, variable_argsp);
va_end(variable_argsp);
}
void posix_print_trace(const char *format, ...)
{
va_list variable_argsp;
va_start(variable_argsp, format);
bs_trace_vprint(BS_TRACE_RAW, cpu_prefix, cpu_number, 2, BS_TRACE_AUTOTIME, 0,
format, variable_argsp);
va_end(variable_argsp);
}
int posix_trace_over_tty(int file_number)
{
return bs_trace_is_tty(file_number);
}
void nsi_vprint_error_and_exit(const char *format, va_list vargs)
{
bs_trace_vprint(BS_TRACE_ERROR, cpu_prefix, cpu_number, 0, BS_TRACE_AUTOTIME, 0,
format, vargs);
}
void nsi_vprint_warning(const char *format, va_list vargs)
{
bs_trace_vprint(BS_TRACE_WARNING, cpu_prefix, cpu_number, 0, BS_TRACE_AUTOTIME, 0,
format, vargs);
}
void nsi_vprint_trace(const char *format, va_list vargs)
{
bs_trace_vprint(BS_TRACE_RAW, cpu_prefix, cpu_number, 2, BS_TRACE_AUTOTIME, 0,
format, vargs);
}
``` | /content/code_sandbox/boards/native/nrf_bsim/common/trace_hook.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 647 |
```c
/*
*
*/
#include <stddef.h>
#include <stdbool.h>
#include "bs_cmd_line.h"
#include "bs_dynargs.h"
#include "bs_utils.h"
#include "bs_types.h"
#include "bs_tracing.h"
#include "nsi_tasks.h"
#include "nsi_hws_models_if.h"
#include "NRF_HWLowL.h"
#include "xo_if.h"
#include "bsim_args_runner.h"
/* By default every second we will inform the Phy simulator about our timing */
#define BSIM_DEFAULT_PHY_MAX_RESYNC_OFFSET 1000000
static struct {
double start_offset;
bs_time_t max_resync_offset;
bool delay_init;
bool sync_preinit;
bool sync_preboot;
} sync_args;
static bs_time_t phy_sync_ctrl_event_timer = TIME_NEVER;
static bs_time_t last_resync_time;
static void psc_program_next_event(void)
{
if (sync_args.max_resync_offset != TIME_NEVER) {
phy_sync_ctrl_event_timer = last_resync_time + sync_args.max_resync_offset;
bs_time_t now = nsi_hws_get_time();
if (phy_sync_ctrl_event_timer < now) {
phy_sync_ctrl_event_timer = now;
}
} else {
phy_sync_ctrl_event_timer = TIME_NEVER;
}
nsi_hws_find_next_event();
}
static void phy_sync_ctrl_event_reached(void)
{
last_resync_time = nsi_hws_get_time();
hwll_sync_time_with_phy(last_resync_time);
psc_program_next_event();
}
NSI_HW_EVENT(phy_sync_ctrl_event_timer, phy_sync_ctrl_event_reached, 900);
static void phy_sync_ctrl_init(void)
{
last_resync_time = nsi_hws_get_time();
psc_program_next_event();
}
NSI_TASK(phy_sync_ctrl_init, HW_INIT, 100);
/**
* Keep track of the last time we synchronized the time with the Phy
*/
void phy_sync_ctrl_set_last_phy_sync_time(bs_time_t time)
{
last_resync_time = time;
psc_program_next_event();
}
/**
* Configure the maximum resynchronization offset
* (How long, in simulation time, can we spend without talking with the Phy)
* Note that this value may be configured as a command line argument too
*/
void phy_sync_ctrl_set_max_resync_offset(bs_time_t max_resync_offset)
{
sync_args.max_resync_offset = max_resync_offset;
psc_program_next_event();
}
/* For backwards compatibility with the old board code */
void tm_set_phy_max_resync_offset(bs_time_t offset_in_us)
{
phy_sync_ctrl_set_max_resync_offset(offset_in_us);
}
static double tmp_start_of;
static void cmd_start_of_found(char *argv, int offset)
{
if (tmp_start_of < 0) {
bs_trace_error_line("start offset (%lf) cannot be smaller than 0\n", tmp_start_of);
}
sync_args.start_offset = tmp_start_of;
xo_model_set_toffset(sync_args.start_offset);
}
static void cmd_no_delay_init_found(char *argv, int offset)
{
sync_args.delay_init = false;
}
static void cmd_no_sync_preinit_found(char *argv, int offset)
{
sync_args.sync_preinit = false;
}
static void cmd_no_sync_preboot_found(char *argv, int offset)
{
sync_args.sync_preboot = false;
}
static double tmp_max_resync_offset;
static void cmd_max_resync_offset_found(char *argv, int offset)
{
if (tmp_max_resync_offset < 500) {
bs_trace_warning("You are attempting to set a very low phy resynchronization of %d."
"Note this will have a performance impact\n",
tmp_max_resync_offset);
}
sync_args.max_resync_offset = tmp_max_resync_offset;
}
static void phy_sync_ctrl_register_args(void)
{
static bs_args_struct_t args_struct_toadd[] = {
{
.option = "start_offset",
.name = "start_of",
.type = 'f',
.dest = (void *)&tmp_start_of,
.call_when_found = cmd_start_of_found,
.descript = "Offset in time (at the start of the simulation) of this device. "
"At time 0 of the device, the phy will be at <start_of>"
},
{
.is_switch = true,
.option = "sync_preinit",
.type = 'b',
.dest = (void *)&sync_args.sync_preinit,
.descript = "Postpone HW initialization and CPU boot until the Phy has "
"reached time 0 (or start_offset) (by default not set)"
},
{
.is_switch = true,
.option = "no_sync_preinit",
.type = 'b',
.call_when_found = cmd_no_sync_preinit_found,
.descript = "Clear sync_preinit. Note that by default sync_preinit is not set"
},
{
.is_switch = true,
.option = "sync_preboot",
.type = 'b',
.dest = (void *)&sync_args.sync_preboot,
.descript = "Postpone CPU boot (but not HW initialization) until the "
"Phy has reached time 0 (or start_offset) (by default not set)"
"If sync_preinit is set, this option has no effect."
},
{
.is_switch = true,
.option = "no_sync_preboot",
.type = 'b',
.call_when_found = cmd_no_sync_preboot_found,
.descript = "Clear sync_preboot. Note that by default sync_preboot is not set"
},
{
.is_switch = true,
.option = "delay_init",
.type = 'b',
.dest = (void *)&sync_args.delay_init,
.descript = "If start_offset is used, postpone HW initialization and CPU boot "
"until start_offset is reached (by default not set)"
},
{
.is_switch = true,
.option = "no_delay_init",
.type = 'b',
.call_when_found = cmd_no_delay_init_found,
.descript = "Clear delay_init. Note that by default delay_init is not set"
},
{
.option = "mro",
.name = "max_resync_offset",
.type = 'd',
.dest = (void *)&tmp_max_resync_offset,
.call_when_found = cmd_max_resync_offset_found,
.descript = "Set the max Phy synchronization offset, that is, how far the device "
"time can be from the Phy time before it resynchronizes with the Phy "
"again (by default 1e6, 1s). Note that this value may be changed "
"programmatically by tests"
},
ARG_TABLE_ENDMARKER
};
bs_add_extra_dynargs(args_struct_toadd);
sync_args.max_resync_offset = BSIM_DEFAULT_PHY_MAX_RESYNC_OFFSET;
}
NSI_TASK(phy_sync_ctrl_register_args, PRE_BOOT_1, 10);
void phy_sync_ctrl_connect_to_2G4_phy(void)
{
static bool ever_run;
if (ever_run) {
return;
}
ever_run = true;
bs_trace_raw(9, "%s: Connecting to phy...\n", __func__);
hwll_connect_to_phy(bsim_args_get_2G4_device_nbr(),
bsim_args_get_simid(),
bsim_args_get_2G4_phy_id());
bs_trace_raw(9, "%s: Connected\n", __func__);
}
void phy_sync_ctrl_pre_boot2(void)
{
static bool ever_run;
if (ever_run) {
return;
}
ever_run = true;
if (((sync_args.start_offset > 0) && (sync_args.delay_init))
|| sync_args.sync_preinit) {
/* Delay the next steps until the simulation time has
* reached either time 0 or start_offset.
*/
hwll_wait_for_phy_simu_time(BS_MAX(sync_args.start_offset, 0));
sync_args.sync_preboot = false; /* Already sync'ed */
}
}
void phy_sync_ctrl_pre_boot3(void)
{
static bool ever_run;
if (ever_run) {
return;
}
ever_run = true;
/*
* If sync_preboot was set, we sync with the phy
* right before booting the CPU
*/
if (sync_args.sync_preboot) {
hwll_wait_for_phy_simu_time(BS_MAX(sync_args.start_offset, 0));
}
}
``` | /content/code_sandbox/boards/native/nrf_bsim/common/phy_sync_ctrl.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,858 |
```objective-c
/*
*
*/
/**
* This header exists solely to allow drivers meant for the native_sim board
* to be used directly in the nrf5*_bsim boards.
* Note that such reuse should be done with great care.
*
* The command line arguments parsing logic from native_sim was born as a copy
* of the one from the BabbleSim's libUtil library
* They are therefore mostly equal except for types and functions names.
*
* This header converts these so the native_sim call to dynamically register
* command line arguments is passed to the nrf*_bsim one
*/
#ifndef BOARDS_POSIX_NRF_BSIM_CMDLINE_H
#define BOARDS_POSIX_NRF_BSIM_CMDLINE_H
#include "../../native_posix/cmdline_common.h"
#ifdef __cplusplus
extern "C" {
#endif
static inline void native_add_command_line_opts(struct args_struct_t *args)
{
void bs_add_extra_dynargs(struct args_struct_t *args);
bs_add_extra_dynargs(args);
}
#ifdef __cplusplus
}
#endif
#endif /* BOARDS_POSIX_NRF_BSIM_CMDLINE_H */
``` | /content/code_sandbox/boards/native/nrf_bsim/common/cmdline.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 227 |
```c
/*
*
*
* Note this run in the runner context, and therefore
* this file should therefore only be built once for all CPUs.
*/
#include "bs_tracing.h"
#include "bs_dump_files.h"
#include "bs_pc_backchannel.h"
#include "nsi_tasks.h"
#include "nsi_main.h"
#include "nsi_hw_scheduler.h"
#include "NRF_HWLowL.h"
#include "bsim_args_runner.h"
static uint8_t main_clean_up_trace_wrap(void)
{
return nsi_exit_inner(0);
}
static void trace_registration(void)
{
bs_trace_register_cleanup_function(main_clean_up_trace_wrap);
bs_trace_register_time_function(nsi_hws_get_time);
}
NSI_TASK(trace_registration, PRE_BOOT_1,
0 /*we want to run this as early as possible */);
static void open_dumps(void)
{
bs_dump_files_open(bsim_args_get_simid(),
bsim_args_get_global_device_nbr());
}
NSI_TASK(open_dumps, PRE_BOOT_2, 500);
static void exit_hooks(void)
{
hwll_terminate_simulation();
bs_dump_files_close_all();
bs_clean_back_channels();
}
NSI_TASK(exit_hooks, ON_EXIT_PRE, 500);
``` | /content/code_sandbox/boards/native/nrf_bsim/common/runner_hooks.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 252 |
```objective-c
/*
*
*/
#ifndef BOARDS_POSIX_BSIM_COMMON_BSIM_ARGS_RUNNER_H
#define BOARDS_POSIX_BSIM_COMMON_BSIM_ARGS_RUNNER_H
#include <stdint.h>
#include "bs_cmd_line.h"
#ifdef __cplusplus
extern "C" {
#endif
void bs_add_extra_dynargs(bs_args_struct_t *args_struct_toadd);
char *bsim_args_get_simid(void);
char *bsim_args_get_2G4_phy_id(void);
unsigned int bsim_args_get_global_device_nbr(void);
unsigned int bsim_args_get_2G4_device_nbr(void);
/* Will be deprecated in favor of bsim_args_get_simid() */
char *get_simid(void);
/* Will be deprecated in favor of bsim_args_get_global_device_nbr() */
unsigned int get_device_nbr(void);
#ifdef __cplusplus
}
#endif
#endif /* BOARDS_POSIX_BSIM_COMMON_BSIM_ARGS_RUNNER_H */
``` | /content/code_sandbox/boards/native/nrf_bsim/common/bsim_args_runner.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 190 |
```c
/*
*
*
* Common command line arguments and overall command line argument handling
* for Zephyr Babblesim boards.
*
* Note that this is code runs in the native simulator runner context,
* and not in any embedded CPU context.
* This file should therefore only be built once for all CPUs.
*/
#include <stdint.h>
#include <stdbool.h>
#include <limits.h>
#include <string.h>
#include "bs_cmd_line.h"
#include "bs_cmd_line_typical.h"
#include "bs_dynargs.h"
#include "bs_tracing.h"
#include "bs_dump_files.h"
#include "bs_rand_main.h"
#include "nsi_cpu_if.h"
#include "nsi_tasks.h"
#include "nsi_main.h"
#include "nsi_cpu_ctrl.h"
#include "NRF_HWLowL.h"
#include "NHW_misc.h"
static bs_args_struct_t *args_struct;
/* Direct use of this global is deprecated, use bsim_args_get_global_device_nbr() instead */
uint global_device_nbr;
#define MAXPARAMS_TESTCASES 1024
static struct bsim_global_args_t {
BS_BASIC_DEVICE_OPTIONS_FIELDS
} global_args;
static bool nosim;
/* Extra "command line options" provided programmatically: */
static int extra_argc;
static char **extra_argv;
static void cmd_trace_lvl_found(char *argv, int offset)
{
bs_trace_set_level(global_args.verb);
}
static void cmd_gdev_nbr_found(char *argv, int offset)
{
bs_trace_set_prefix_dev(global_args.global_device_nbr);
}
static void print_no_sim_warning(void)
{
bs_trace_warning("Neither simulation id or the device number "
"have been set. I assume you want to run "
"without a BabbleSim phy (-nosim)\n");
bs_trace_warning("If this is not what you wanted, check with "
"--help how to set them\n");
bs_trace_raw(3, "setting sim_id to 'bogus', device number to 0 "
"and nosim\n");
}
static void print_mcus_info(char *argv, int offset)
{
(void) argv;
(void) offset;
bs_trace_raw(0, "CPU #, Name , Autostart\n");
bs_trace_raw(0, "-------------------------------\n");
for (int i = 0; i < NSI_N_CPUS; i++) {
bs_trace_raw(0, "CPU %2i, %12s, %i\n",
i, nhw_get_core_name(i), nsi_cpu_get_auto_start(i));
}
}
static void bsim_register_basic_args(void)
{
#define args (&global_args)
/* This define allows reusing the definitions provided by the utils library */
static bs_args_struct_t args_struct_toadd[] = {
ARG_TABLE_S_ID,
ARG_TABLE_P_ID_2G4,
ARG_TABLE_DEV_NBR,
ARG_TABLE_GDEV_NBR,
ARG_TABLE_VERB,
ARG_TABLE_SEED,
ARG_TABLE_COLOR,
ARG_TABLE_NOCOLOR,
ARG_TABLE_FORCECOLOR,
{
.is_switch = true,
.option = "nosim",
.type = 'b',
.dest = (void *)&nosim,
.descript = "Do not connect to the Physical layer simulator"
},
BS_DUMP_FILES_ARGS,
{
.manual = true,
.option = "argstest",
.name = "arg",
.type = 'l',
.descript = "The arguments that follow will be passed straight to the testcase "
"init function (Note: If more than 1 MCU is present, argtest corresponds "
"to argstests" NSI_STRINGIFY(NSI_PRIMARY_MCU_N) " )"
},
{
.manual = true,
.option = "argstest<n>",
.name = "arg",
.type = 'l',
.descript = "The arguments that follow will be passed straight to cpu<n>'s "
"testcase init function), where 0 <= n < " NSI_STRINGIFY(NSI_N_CPUS)
" is the cpu number"
},
{
.manual = true,
.option = "argsmain",
.name = "arg",
.type = 'l',
.descript = "The arguments that follow will be passed to main (default)"
},
{
.is_switch = true,
.option = "cpu_print_info",
.call_when_found = print_mcus_info,
.type = 'b',
.descript = "Print information about each MCUs",
},
ARG_TABLE_ENDMARKER
};
#undef args
bs_add_dynargs(&args_struct, args_struct_toadd);
}
NSI_TASK(bsim_register_basic_args, PRE_BOOT_1, 0);
static void bsim_cleanup_args(void)
{
bs_cleanup_dynargs(&args_struct);
}
NSI_TASK(bsim_cleanup_args, ON_EXIT_POST, 0);
void bs_add_extra_dynargs(bs_args_struct_t *args_struct_toadd)
{
bs_add_dynargs(&args_struct, args_struct_toadd);
}
static void nsif_cpun_save_test_arg(int n, char *c)
{
F_TRAMP_LIST(NATIVE_SIMULATOR_IF void nsif_cpu, _save_test_arg(char *argv))
void(*fptrs[])(char *) = {
F_TRAMP_TABLE(nsif_cpu, _save_test_arg)
};
fptrs[n](c);
}
static void nsi_handle_one_cmdline_argument(char *argv)
{
static enum {Main = 0, Test = 1} parsing = Main;
static uint test_cpu_n;
if (bs_is_option(argv, "argstest", 0)) {
parsing = Test;
test_cpu_n = NSI_PRIMARY_MCU_N;
return;
} else if (bs_is_multi_opt(argv, "argstest", &test_cpu_n, 0)) {
parsing = Test;
return;
} else if (bs_is_option(argv, "argsmain", 0)) {
parsing = Main;
return;
}
if (parsing == Main) {
if (!bs_args_parse_one_arg(argv, args_struct)) {
bs_args_print_switches_help(args_struct);
bs_trace_error_line("Incorrect option %s\n",
argv);
}
} else if (parsing == Test) {
nsif_cpun_save_test_arg(test_cpu_n, argv);
} else {
bs_trace_error_line("Bad error\n");
}
}
/**
* Check the arguments provided in the command line: set args based on it or
* defaults, and check they are correct
*/
void nsi_handle_cmd_line(int argc, char *argv[])
{
bs_args_set_defaults(args_struct);
global_args.verb = 2;
bs_trace_set_level(global_args.verb);
for (int i = 0; i < extra_argc; i++) {
nsi_handle_one_cmdline_argument(extra_argv[i]);
}
for (int i = 1; i < argc; i++) {
nsi_handle_one_cmdline_argument(argv[i]);
}
}
void nsi_register_extra_args(int argc, char *argv[])
{
int new_size = extra_argc + argc;
extra_argv = realloc(extra_argv, new_size*sizeof(char *));
for (int i = 0; i < argc; i++) {
memcpy(&extra_argv[extra_argc], argv, argc*sizeof(char *));
}
extra_argc += argc;
}
static void clear_extra_args(void)
{
free(extra_argv);
}
NSI_TASK(clear_extra_args, ON_EXIT_PRE, 100);
static void postcheck_cmd_line(void)
{
static const char *bogus_sim_id = "bogus";
static const char default_phy[] = "2G4";
/**
* If the user did not set the simulation id or device number
* we assume he wanted to run with nosim (but warn him)
*/
if ((!nosim) && (global_args.s_id == NULL) && (global_args.device_nbr == UINT_MAX)) {
print_no_sim_warning();
nosim = true;
}
if (nosim) {
if (global_args.s_id == NULL) {
global_args.s_id = (char *)bogus_sim_id;
}
if (global_args.device_nbr == UINT_MAX) {
global_args.device_nbr = 0;
}
hwll_set_nosim(true);
}
if (global_args.device_nbr == UINT_MAX) {
bs_args_print_switches_help(args_struct);
bs_trace_error_line("The command line option <device number> "
"needs to be set\n");
}
if (global_args.global_device_nbr == UINT_MAX) {
global_args.global_device_nbr = global_args.device_nbr;
bs_trace_set_prefix_dev(global_args.global_device_nbr);
}
global_device_nbr = global_args.global_device_nbr;
if (!global_args.s_id) {
bs_args_print_switches_help(args_struct);
bs_trace_error_line("The command line option <simulation ID> "
"needs to be set\n");
}
if (!global_args.p_id) {
global_args.p_id = (char *)default_phy;
}
if (global_args.rseed == UINT_MAX) {
global_args.rseed = 0x1000 + global_args.device_nbr;
}
bs_random_init(global_args.rseed);
}
NSI_TASK(postcheck_cmd_line, PRE_BOOT_2, 0);
/*
* Get the simulation id
*/
char *bsim_args_get_simid(void)
{
return global_args.s_id;
}
/*
* Get this device number in the simulation, as it is
* known in the overall simulation.
* In general this is the device number you want
*/
unsigned int bsim_args_get_global_device_nbr(void)
{
return global_args.global_device_nbr;
}
/*
* Get this device number in the 2G4 Phy simulation
*/
unsigned int bsim_args_get_2G4_device_nbr(void)
{
return global_args.device_nbr;
}
/*
* Get this device number in the 2G4 Phy simulation
*/
char *bsim_args_get_2G4_phy_id(void)
{
return global_args.p_id;
}
char *get_simid(void)
{
return bsim_args_get_simid();
}
unsigned int get_device_nbr(void)
{
return bsim_args_get_global_device_nbr();
}
``` | /content/code_sandbox/boards/native/nrf_bsim/common/bsim_args_runner.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,235 |
```c
/*
*
*/
#include <zephyr/init.h>
#include <stdint.h>
#include <string.h>
#include "bs_types.h"
#include "bs_tracing.h"
#include "bstests.h"
#include "bs_oswrap.h"
#include "nsi_host_trampolines.h"
/*
* Result of the testcase execution.
* Note that the executable will return the maximum of bst_result and
* {the HW model return code} to the shell and that
* {the HW model return code} will be 0 unless it fails or it is
* configured illegally
*/
enum bst_result_t bst_result;
static struct bst_test_instance *current_test;
static struct bst_test_list *test_list_top;
__attribute__((weak)) bst_test_install_t test_installers[] = { NULL };
struct bst_test_list *bst_add_tests(struct bst_test_list *tests,
const struct bst_test_instance *test_def)
{
int idx = 0;
struct bst_test_list *tail = tests;
struct bst_test_list *head = tests;
if (tail) {
/* First we 'run to end' */
while (tail->next) {
tail = tail->next;
}
} else {
if (test_def[idx].test_id != NULL) {
head = bs_malloc(sizeof(struct bst_test_list));
head->next = NULL;
head->test_instance = (struct bst_test_instance *)
&test_def[idx++];
tail = head;
}
}
while (test_def[idx].test_id != NULL) {
tail->next = bs_malloc(sizeof(struct bst_test_list));
tail = tail->next;
tail->test_instance = (struct bst_test_instance *)
&test_def[idx++];
tail->next = NULL;
}
return head;
}
static struct bst_test_instance *bst_test_find(struct bst_test_list *tests,
char *test_id)
{
struct bst_test_list *top = tests;
while (top != NULL) {
if (!strcmp(top->test_instance->test_id, test_id)) {
/* Match found */
return top->test_instance;
}
top = top->next;
}
return NULL;
}
__noubsan void bst_install_tests(void)
{
int idx = 0;
if (test_list_top) {
/* Tests were already installed */
return;
}
/* First execute installers until first test was installed */
while (!test_list_top && test_installers[idx]) {
test_list_top = test_installers[idx++](test_list_top);
}
/* After that simply add remaining tests to list */
while (test_installers[idx]) {
test_installers[idx++](test_list_top);
}
}
/**
* Print the tests list displayed with the --testslist command
* line option
*/
void bst_print_testslist(void)
{
struct bst_test_list *top;
/* Install tests */
bst_install_tests();
top = test_list_top;
while (top) {
bs_trace_raw(0, "TestID: %-10s\t%s\n",
top->test_instance->test_id,
top->test_instance->test_descr);
top = top->next;
}
}
/**
* Select the testcase to be run from its id
*/
void bst_set_testapp_mode(char *test_id)
{
/* Install tests */
bst_install_tests();
/* By default all tests start as in progress */
bst_result = In_progress;
current_test = bst_test_find(test_list_top, test_id);
if (!current_test) {
bs_trace_error_line("test id %s doesn't exist\n", test_id);
}
}
/**
* Pass to the testcase the command line arguments it may have
*
* This function is called after bst_set_testapp_mode
* and before *init_f
*/
void bst_pass_args(int argc, char **argv)
{
if (current_test && current_test->test_args_f) {
current_test->test_args_f(argc, argv);
}
}
/**
* Will be called before the CPU is booted
*/
void bst_pre_init(void)
{
if (current_test && current_test->test_pre_init_f) {
current_test->test_pre_init_f();
}
}
/**
* Will be called when the CPU has gone to sleep for the first time
*/
void bst_post_init(void)
{
if (current_test && current_test->test_post_init_f) {
current_test->test_post_init_f();
}
}
/**
* Will be called each time the bstest_ticker timer is triggered
*/
void bst_tick(bs_time_t time)
{
if (current_test == NULL) {
return;
}
if (current_test->test_tick_f) {
current_test->test_tick_f(time);
} else if (current_test->test_id) {
bs_trace_error_line("the test id %s doesn't have a tick handler"
" (how come did we arrive here?)\n",
current_test->test_id);
}
}
bool bst_irq_sniffer(int irq_number)
{
if (current_test && current_test->test_irq_sniffer_f) {
return current_test->test_irq_sniffer_f(irq_number);
} else {
return false;
}
}
static int bst_fake_device_driver_pre2_init(void)
{
if (current_test && current_test->test_fake_ddriver_prekernel_f) {
current_test->test_fake_ddriver_prekernel_f();
}
return 0;
}
static int bst_fake_device_driver_post_init(void)
{
if (current_test && current_test->test_fake_ddriver_postkernel_f) {
current_test->test_fake_ddriver_postkernel_f();
}
return 0;
}
SYS_INIT(bst_fake_device_driver_pre2_init, PRE_KERNEL_1, 0);
SYS_INIT(bst_fake_device_driver_post_init, POST_KERNEL, 0);
void bst_main(void)
{
if (current_test && current_test->test_main_f) {
current_test->test_main_f();
}
}
/**
* Will be called when the device is being terminated
*/
uint8_t bst_delete(void)
{
static bool already_deleted;
if (already_deleted) {
return bst_result;
}
already_deleted = true;
if (current_test && current_test->test_delete_f) {
current_test->test_delete_f();
}
while (test_list_top) {
struct bst_test_list *tmp = test_list_top->next;
nsi_host_free(test_list_top);
test_list_top = tmp;
}
if (bst_result == In_progress) {
bs_trace_raw_time(2, "TESTCASE NOT PASSED at exit (test return "
"(%u) indicates it was still in progress)\n", bst_result);
} else if (bst_result != Passed) {
bs_trace_raw_time(2, "The TESTCASE FAILED (test return code %u)\n",
bst_result);
}
return bst_result;
}
#if defined(CONFIG_NATIVE_SIMULATOR_MCU_N)
#include "bstest_ticker.h"
void bst_ticker_set_period(bs_time_t tick_period)
{
bst_ticker_amp_set_period(CONFIG_NATIVE_SIMULATOR_MCU_N, tick_period);
}
void bst_ticker_set_next_tick_absolute(bs_time_t time)
{
bst_ticker_amp_set_next_tick_absolutelute(CONFIG_NATIVE_SIMULATOR_MCU_N, time);
}
void bst_ticker_set_next_tick_delta(bs_time_t time)
{
bst_ticker_amp_set_next_tick_delta(CONFIG_NATIVE_SIMULATOR_MCU_N, time);
}
void bst_awake_cpu_asap(void)
{
bst_ticker_amp_awake_cpu_asap(CONFIG_NATIVE_SIMULATOR_MCU_N);
}
#endif /* defined(CONFIG_NATIVE_SIMULATOR_MCU_N) */
``` | /content/code_sandbox/boards/native/nrf_bsim/common/bstests_entry.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,620 |
```objective-c
/*
*
*/
/**
* This header defines replacements for inline
* ARM Cortex-M CMSIS intrinsics.
*/
#ifndef BOARDS_POSIX_NRF52_BSIM_CMSIS_INSTR_H
#define BOARDS_POSIX_NRF52_BSIM_CMSIS_INSTR_H
/* Implement the following ARM intrinsics as no-op:
* - ARM Data Synchronization Barrier
* - ARM Data Memory Synchronization Barrier
* - ARM Instruction Synchronization Barrier
* - ARM No Operation
*/
#ifndef __DMB
#define __DMB()
#endif
#ifndef __DSB
#define __DSB()
#endif
#ifndef __ISB
#define __ISB()
#endif
#ifndef __NOP
#define __NOP()
#endif
void __WFE(void);
void __WFI(void);
void __SEV(void);
/*
* Implement the following ARM intrinsics as non-exclusive accesses
*
* - STR Exclusive(8,16 & 32bit) (__STREX{B,H,W})
* - LDR Exclusive(8,16 & 32bit) (__LDREX{B,H,W})
* - CLREX : Exclusive lock removal (__CLREX) - no-op
*
* Description:
* These accesses always succeed, and do NOT set any kind of internal
* exclusive access flag;
* There is no local/global memory monitors, MPU control of what are
* shareable regions, exclusive reservations granules, automatic clearing
* on context switch, or so.
*
* This should be enough for the expected uses of LDR/STREXB
* (locking mutexes or guarding other atomic operations, inside a few lines
* of code in the same function): As the POSIX arch will not make an embedded
* thread lose context while just executing its own code, and it does not
* allow parallel embedded SW threads to execute at the same exact time,
* there is no actual need to protect atomicity.
*
* But as this ARM exclusive access monitor mechanism can in principle be
* used for other, unexpected, purposes, this simple replacement may not be
* enough.
*/
/**
* \brief Pretend to execute a STR Exclusive (8 bit)
* \details Executes a ~exclusive~ STR instruction for 8 bit values.
* \param [in] value Value to store
* \param [in] ptr Pointer to location
* \return 0 Function succeeded (always)
*/
static inline uint32_t __STREXB(uint8_t value, volatile uint8_t *ptr)
{
*ptr = value;
return 0;
}
/**
* \brief Pretend to execute a STR Exclusive (16 bit)
* \details Executes a ~exclusive~ STR instruction for 16 bit values.
* \param [in] value Value to store
* \param [in] ptr Pointer to location
* \return 0 Function succeeded (always)
*/
static inline uint32_t __STREXH(uint16_t value, volatile uint16_t *ptr)
{
*ptr = value;
return 0;
}
/**
* \brief Pretend to execute a STR Exclusive (32 bit)
* \details Executes a ~exclusive~ STR instruction for 32 bit values.
* \param [in] value Value to store
* \param [in] ptr Pointer to location
* \return 0 Function succeeded (always)
*/
static inline uint32_t __STREXW(uint32_t value, volatile uint32_t *ptr)
{
*ptr = value;
return 0;
}
/**
* \brief Pretend to execute a LDR Exclusive (8 bit)
* \details Executes an ~exclusive~ LDR instruction for 8 bit value.
* Meaning, it does not set a exclusive lock,
* instead just loads the stored value
* \param [in] ptr Pointer to data
* \return value of type uint8_t at (*ptr)
*/
static inline uint8_t __LDREXB(volatile uint8_t *ptr)
{
return *ptr;
}
/**
* \brief Pretend to execute a LDR Exclusive (16 bit)
* \details Executes an ~exclusive~ LDR instruction for 16 bit value.
* Meaning, it does not set a exclusive lock,
* instead just loads the stored value
* \param [in] ptr Pointer to data
* \return value of type uint8_t at (*ptr)
*/
static inline uint16_t __LDREXH(volatile uint16_t *ptr)
{
return *ptr;
}
/**
* \brief Pretend to execute a LDR Exclusive (32 bit)
* \details Executes an ~exclusive~ LDR instruction for 32 bit value.
* Meaning, it does not set a exclusive lock,
* instead just loads the stored value
* \param [in] ptr Pointer to data
* \return value of type uint8_t at (*ptr)
*/
static inline uint32_t __LDREXW(volatile uint32_t *ptr)
{
return *ptr;
}
/**
* \brief Pretend to remove the exclusive lock
* \details The real function would removes the exclusive lock which is created
* by LDREX, this one does nothing
*/
static inline void __CLREX(void) { /* Nothing to be done */ }
/**
* \brief Model of an ARM CLZ instruction
*/
static inline unsigned char __CLZ(uint32_t value)
{
if (value == 0) {
return 32;
} else {
return __builtin_clz(value);
}
}
#endif /* BOARDS_POSIX_NRF52_BSIM_CMSIS_INSTR_H */
``` | /content/code_sandbox/boards/native/nrf_bsim/common/cmsis/cmsis_instr.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,210 |
```c
/*
*
*/
#include <stdint.h>
#include "irq_ctrl.h"
#include "posix_core.h"
#include "posix_board_if.h"
#include "board_soc.h"
#include "bs_tracing.h"
/*
* Replacement for ARMs NVIC functions()
*/
void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
hw_irq_ctrl_raise_im_from_sw(CONFIG_NATIVE_SIMULATOR_MCU_N, IRQn);
}
void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
hw_irq_ctrl_clear_irq(CONFIG_NATIVE_SIMULATOR_MCU_N, IRQn);
}
void NVIC_DisableIRQ(IRQn_Type IRQn)
{
hw_irq_ctrl_disable_irq(CONFIG_NATIVE_SIMULATOR_MCU_N, IRQn);
}
void NVIC_EnableIRQ(IRQn_Type IRQn)
{
hw_irq_ctrl_enable_irq(CONFIG_NATIVE_SIMULATOR_MCU_N, IRQn);
}
uint32_t NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
return hw_irq_ctrl_is_irq_enabled(CONFIG_NATIVE_SIMULATOR_MCU_N, IRQn);
}
void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
hw_irq_ctrl_prio_set(CONFIG_NATIVE_SIMULATOR_MCU_N, IRQn, priority);
}
uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
return hw_irq_ctrl_get_prio(CONFIG_NATIVE_SIMULATOR_MCU_N, IRQn);
}
void NVIC_SystemReset(void)
{
bs_trace_error_time_line("%s called. Exiting\n", __func__);
}
/*
* Replacements for some other CMSIS functions
*/
void __enable_irq(void)
{
hw_irq_ctrl_change_lock(CONFIG_NATIVE_SIMULATOR_MCU_N, false);
}
void __disable_irq(void)
{
hw_irq_ctrl_change_lock(CONFIG_NATIVE_SIMULATOR_MCU_N, true);
}
uint32_t __get_PRIMASK(void)
{
return hw_irq_ctrl_get_current_lock(CONFIG_NATIVE_SIMULATOR_MCU_N);
}
void __set_PRIMASK(uint32_t primask)
{
hw_irq_ctrl_change_lock(CONFIG_NATIVE_SIMULATOR_MCU_N, primask != 0);
}
void __WFE(void)
{
nrfbsim_WFE_model();
}
void __WFI(void)
{
__WFE();
}
void __SEV(void)
{
nrfbsim_SEV_model();
}
``` | /content/code_sandbox/boards/native/nrf_bsim/common/cmsis/cmsis.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 471 |
```objective-c
/*
*
*/
/**
* This header defines replacements for CMSIS compiler attributes.
*/
#ifndef BOARDS_POSIX_NRF52_BSIM_CMSIS_COMPILER_H
#define BOARDS_POSIX_NRF52_BSIM_CMSIS_COMPILER_H
#include <zephyr/toolchain.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __PACKED
#define __PACKED __packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed
#endif
#ifdef __cplusplus
}
#endif
#endif /* BOARDS_POSIX_NRF52_BSIM_CMSIS_COMPILER_H */
``` | /content/code_sandbox/boards/native/nrf_bsim/common/cmsis/cmsis_compiler.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 143 |
```objective-c
/*
*
*/
/*
* Replacement for Nordic's nrf soc/nordic/common/soc_secure.h
*/
#ifndef BOARDS_POSIX_NRF52_BSIM_SOC_SECURE_H
#define BOARDS_POSIX_NRF52_BSIM_SOC_SECURE_H
#include <stdint.h>
#include <nrf.h>
#include <hal/nrf_ficr.h>
static inline void soc_secure_read_deviceid(uint32_t deviceid[2])
{
deviceid[0] = nrf_ficr_deviceid_get(NRF_FICR, 0);
deviceid[1] = nrf_ficr_deviceid_get(NRF_FICR, 1);
}
#endif /* BOARDS_POSIX_NRF52_BSIM_SOC_SECURE_H */
``` | /content/code_sandbox/boards/native/nrf_bsim/soc/soc_secure.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 152 |
```objective-c
/*
*
*/
/**
* This header defines replacements for inline
* ARM Cortex-M CMSIS intrinsics.
*/
#ifndef BOARDS_POSIX_NRF52_BSIM_CMSIS_H
#define BOARDS_POSIX_NRF52_BSIM_CMSIS_H
#include <stdint.h>
#include "cmsis_instr.h"
#if defined(CONFIG_SOC_COMPATIBLE_NRF52833)
#include "nrf52833.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
void __enable_irq(void);
void __disable_irq(void);
uint32_t __get_PRIMASK(void);
void __set_PRIMASK(uint32_t primask);
void NVIC_SetPendingIRQ(IRQn_Type IRQn);
void NVIC_ClearPendingIRQ(IRQn_Type IRQn);
void NVIC_DisableIRQ(IRQn_Type IRQn);
void NVIC_EnableIRQ(IRQn_Type IRQn);
void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority);
uint32_t NVIC_GetPriority(IRQn_Type IRQn);
void NVIC_SystemReset(void);
#ifdef __cplusplus
}
#endif
#endif /* BOARDS_POSIX_NRF52_BSIM_CMSIS_H */
``` | /content/code_sandbox/boards/native/nrf_bsim/common/cmsis/cmsis.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 236 |
```objective-c
/*
*
*/
#ifndef BOARDS_POSIX_NRF_BSIM_SOC_PINCTRL_SOC_H
#define BOARDS_POSIX_NRF_BSIM_SOC_PINCTRL_SOC_H
/* We reuse the real SOC's header: */
#include "../soc/nordic/common/pinctrl_soc.h"
#endif /* BOARDS_POSIX_NRF_BSIM_SOC_PINCTRL_SOC_H */
``` | /content/code_sandbox/boards/native/nrf_bsim/soc/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```objective-c
/*
*
*/
#ifndef BOARDS_POSIX_NRF_BSIM_SOC_SOC_NRF_COMMON_H
#define BOARDS_POSIX_NRF_BSIM_SOC_SOC_NRF_COMMON_H
/* We reuse the real SOC's header: */
#include "../soc/nordic/common/soc_nrf_common.h"
#endif /* BOARDS_POSIX_NRF_BSIM_SOC_SOC_NRF_COMMON_H */
``` | /content/code_sandbox/boards/native/nrf_bsim/soc/soc_nrf_common.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 77 |
```c
/*
*
*/
#include <stdint.h>
#include <kernel_internal.h>
/*
* Replacement for the nrfx nrfx_coredep_delay_us()
* which busy waits for the given number of microseconds.
*
* This function will replace at *link* time the
* nrfx one which had been marked as weak.
*/
void nrfx_coredep_delay_us(uint32_t time_us)
{
if (time_us == 0) {
return;
}
arch_busy_wait(time_us);
}
``` | /content/code_sandbox/boards/native/nrf_bsim/soc/nrfx_coredep.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 105 |
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